1986_Harris_Analog_Product_Data_Book 1986 Harris Analog Product Data Book

User Manual: 1986_Harris_Analog_Product_Data_Book

Open the PDF directly: View PDF .
Page Count: 898

Download
Open PDF In Browser	View PDF

Volume 5
$5.00

Harris Semiconductor
Sector Capabilities
Harris Semiconductor, one of the top ten U.S. semiconductor merchant suppliers, is a sector of Harris
Corporation - a producer of advanced information processing, communication and microelectronic
products for the worldwide Information Technology market.
Harris Semiconductor is organized to address the standard products, custom products, and gallium
arsenide semiconductor markets.

SEMICONDUCTOR PRODUCTS DIVISION:
Harris Semiconductor offers a wide selection of standard analog and digital circuits through its Semiconductor Products Division:
Analog Products
Harris is a major force in analog integrated circuitry, offering a broad line of products including: analogto-digital converters, digital-to-analog converters, sample-and-hold circuits, multiplexers, switches,
voltage references, operational amplifiers, telecommunications and speech processing products,
hybrid subsystems and active filters.
Digital Products
Harris is a pioneer in developing and producing digital CMOS products including: CMOS RAMs, CMOS
PROMs, CMOS microprocessors, CMOS peripherals, CMOS data communications products, and a full
line of 80C86/88 microprocessors and peripherals. Semicustom circuit design problems are solved by a
complete line of SSI, MSI, and LSI standard cells and programmable logic products featuring on-chip
testability. The Harris SHIPsTM (Semicustom Highly Integrated Peripherals) service features total
in-plant capability, proven LSI cells, and an array of customer design entry levels. (See complete digital
product listing, page 13-2)

CUSTOM INTEGRATED CIRCUITS DIVISION (CICD)
Harris designs, develops and manufactures analog, digital bipolar, and CMOS circuits for specialized
military and commercial applications. CICD offers a full line of radiation hardened products guaranteed
to customer specifications. Strategic, tactical and communications ICs are available as full custom,
semicustom and data sheet p·roducts. (See complete CICD product listing, page 13-3 & 13~4)

MICROWAVE SEMICONDUCTOR DIVISION
Harris Microwave Semiconductor Division develops and manufactures gallium arsenide field effecttransistors (GaAs FETs), digital integrated circuits, monolithic microwave integrated circuits, and GaAs FET
microwave amplifiers. (See complete Microwave product listing, page 13-4)

Copyright

© Harris Corporation 1986
(All rights reserved)
Printed in U.S.A.

Harris Linear,

Data Acquisition and
Telecom Products
Harris Semiconductor's spectrum of analog products meet many specialized requirements ranging from
precision to high speed performance. Capitalizing on advanced linear processing technologies
developed over the past 19 years, Harris Semiconductor offers analog products of high quality and
unmatched performance.
This data book describes Harris Semiconductor's complete line of Linear, Data Acquisition, and
Telecommunication products. In addition, it includes a complete set of data sheets for product
specifications; a section of application notes with design details for specific applications of Harris
products; and a description of Harris' quality and high reliability program.
If you need more information on these and other Harris products, please contact the nearest Harris sales
office listed in the back of this data book. Or return the reply card attached inside back cover.

Harris Semiconductor products are sold by description only. All specifications in
this data book are applicable only to packaged products; specifications for dice
are available upon request. Harris reserves the right to make changes in circuit
design, specifications and other information at any time without prior notice.
Accordingly, the reader is cautioned to verify that data sheets and other
information in this publication are current before placing orders. Information
contained in the application notes is intended soley for general guidance; use of
the information for user's specific application is at user's risk. Reference to
products of other manufacturers are solely for convenience of comparison and
do not imply total equivalency of design, performance, or otherwise.

ii

Operational Amplifiers, Comparators, & Control Functions

III
EJ

CMOS Analog Switches

EI

General I nformation

Multiplexers
Analog-to-Digital Converters
Digital-to-Analog Converters
Sample & Hold Amplifiers and Signal Processors
Telecommunications
Harris Quality and Reliability
Application Notes

Packaging

iii
IfJ

Appendices

OJ

Chip Information

iii

lEI
III
II
III
III
III
IIiI

CMOS Digital Products

13-2

CICD Rad Hard Products

13-3

CICD Future Rad Hard Products

13-4

Harris Microwave Semiconductor
Gallium Arsenide/Microwave Products

13-4

Harris Sales Locations

13-5

TI
Z

...JS?

Alpha Numeric Product Index

1-2

Analog Product Listing

1-4

Ordering Information

1-8

IC Handling Procedure

1-10

Harris Analog IC Technologies

1-10

Competitive Cross Reference Chart

1-13

High Temperature Electronics

1-27

Advanced Packaging Techniques

1-27

1-1

«Ia:«
W:!i
Za:

Wo
t:lu..

~

Alpha Numeric Product Index
PAGE
2-12
2-20
2-25
2-30
2-34
7-5
7-10
2-38
2-42
2-46
2-50
2-56
2-62
2-66
2-71
2-72
2-76
2-80
2-84
2-88
2-92
2-98
2-105
2-109
2-116
2-120
2-128
2-129
2-129
2-129
2-129
2-134
2-141
2-142
2-142
2-142
2-148
2-153
2-157
2-164
2-169
2-176
7-17
7-24

HA-OP07
HA-OP27
HA-OP37
HA-2400/04/05
HA-2406
HA-2420-1
HA-2420/25
HA-2500/02/05
HA-2510/12/15
HA-2520/22/25
HA-2539
HA-2540
HA-2541
HA-2542
HA-2544 ADVANCE
HA-2600/02/05
HA-2620/22/25
HA-2630/35
HA-2640/45
HA-2650/55
HA-2720/25
HA-4600/02/05
HA-4741
HA-4900/02/05
HA-5002
HA-5033
HA-5101/5111 ADVANCE
HA-5102
HA-5104
HA-5112
HA-5114
HA-5130/35
HA-5134 ADVANCE
HA-5141
HA-5142
HA-5144
HA-5147
HA-5151/52/54
HA-5160/62
HA-5170
HA-51S0/S0A
HA-5190/95
HA-5320
HA-5330

Precision Operational Amplifier ...................................................................................
Precision, Low Noise Operational Amplifier...............................................................
High Slew Rate, Precision, Low Noise Operational Amplifier ..................................
PRAM Four Channel Programmable Amplifiers ............................. ,...........................
Digital Selectable Four Channel Operational Amplifier ............................................
High Temperature Sample and Hold Amplifier ..........................................................
Fast Sample and Hold Amplifier ..................................................................................
High Slew Rate Operational Amplifiers.......................................................................
High Slew Rate Operational Amplifiers.......................................................................
High Slew Rate Operational Amplifiers.......................................................................
High Slew Rate, Wide Bandwidth Operational Amplifier ..........................................
High Slew Rate, Wide Bandwidth Operational Amplifier ..........................................
High Slew Rate, Unity Gain Stable Operational Amplifier........................................
High Slew Rate, Power Operational Amplifier ...........................................................
Video Operational Amplifier .........................................................................................
General Purpose High Performance Operational Amplifiers ....................................
Wide Bandwidth Operational Amplifiers .....................................................................
High Performance Current Boosters ...........................................................................
High Voltage Operational Amplifiers ...........................................................................
Dual General Purpose High Performance Operational Amplifier ............................
Programmable Low Power Operational Amplifiers....................................................
Quad General Purpose High Performance Amplifiers...............................................
Quad General Purpose High Performance Amplifier ................................................
Quad High Speed Comparators .....................................................................;.............
Wideband, High Slew Rate, High Output Current Buffer .........................................
Wideband, High Slew Rate Current Buffer .................................................................
Low Noise, High Performance Operational Amplifiers .............................................
Dual Low Noise Operational Amplifier ........................................................................
Quad Low Noise Operational Amplifier ......................................................................
Dual High Slew Rate, Low Noise Operational Amplifier ...........................................
Quad High Slew Rate, Low Noise Operational Amplifier .........................................
Precision Operational Amplifiers .................................................................................
Precision Quad Operational Amplifier ........................................................................
Ultra-Low Power Operational Amplifier ......................................................................
Dual Ultra-Low Power Operational Amplifier .............................................................
Quad Ultra-Low Power Operational Amplifier ...........................................................
High Slew Rate, Precision, Low Noise Operational Amplifier ..................................
Low Power Operational Amplifiers ..............................................................................
High Slew Rate, Wide Bandwidth J-FET Operational Amplifiers .............................
J-FET Precision Operational Amplifier .......................................................................
J-FET Precision, Low Bias Current Operational Amplifier .......................................
High Slew Rate, Fast Settling Operational Amplifiers ...............................................
High Speed Precision Sample and Hold Amplifier ....................................................
Very High Speed Precision Sample and Hold Amplifier ...........................................

HC-5502A
HC-5504
HC-5508/09
HC-5510/11
HC-5512/12A
HC-5512C
HC-5512D
HC-5552/53/54/57
HC-5560 ADVANCE
HC-5572 ADVANCE
HC-5580 ADVANCE
HC-5581 ADVANCE
HC-5590 ADVANCE
HC-55536
HC-55564

SLiC Subscriber Line Interface Circuit ....................................................................... 8-7
SLiC Subscriber Line Interface Circuit ....................................................................... 8-12
SLiCs Subscriber Line Interface Circuit ..................................................................... 8-17
Monolithic CODECs ...................................................................................................... 8-24
PCM Monolithic Filter ................................................................................................... 8-33
PCM or CVSD Monolithic Filter ................................................................................... 8-40
PCM Monolithic Filter Military Temperature Range .................................................. 8-48
Monolithic CMOS Serial Interface CODEC/Filter Family ......................................... 8-57
Transcoder ...................................................................................................................... 8-82
2400/1200/600/300 BPS Modem .................................................................................... 8-86
Trunk Subscriber Line Interface Circuit (TSLlC) ....................................................... 8-83
DAA Subscriber Line Interface Circuit (DAASLlC) ................................................... 8-84
Digital Line Transceiver ................................................................................................ 8-85
All-Digital Continuously Variable Slope Delta Demodulator (CVSD) ..................... 8-68
All-Digital Continuously Variable Slope Delta Modulator/Demodulator (CVSD) .. 8-72

HF-10

Universal Active Filter .............................................................................................:..... 8-79

HI-1818A/1828A
HI-200
HI-201

Low Resistance Single 8/Differential 4 Channel CMOS Analog Muxiplexer ......... 4-68
Dual SPST General Purpose CMOS Analog Switch .................................................. 3-6
Quad SPST General Purpose CMOS Analog Switch ................................................ 3-12

1-2

Alpha Numeric Product Index

(Continued)
PAGE

HI-201 HS
HI-300
HI-301
HI-302
HI-303
HI-304
HI-305
HI-306
HI-307
HI-381
HI-384
HI-387
HI-390
HI-5040
HI-5041
HI-5042
HI-5043
HI-5044
HI-5045
HI-5046/46A
HI-5047/47A
HI-5048
HI-5049
HI-5050
HI-5051
HI-506/507
Hl c506A/507A
HI-506LA/507LA
HI-508/509
HI-508A/509A
H 1-508LA/509LA
HI-516
HI-518
HI-524
HI-539
HI-546/547
HI-548/549
HI-5610
HI-5618A/18B
HI-562A
HI-565A
HI-5660/60A
HI-5680
HI-5685/85A
HI-5687
HI-5690V
HI-5695V
HI-5697V
HI-574A
HI-5811
HI-674A
HI-7541
HI-774
HI-774A
HI-DAC16B/C

Quad SPST High Speed CMOS Analog Switch .......................................... .
3-18
Dual SPST Precision CMOS Analog Switch ................................................... .
3-27
SPDT Precision CMOS Analog Switch ........................................................................... . 3-27
Dual DPST Precision CMOS Analog Switch .................................................................. . 3-27
Dual SPDT Precision CMOS Analog Switch ................................................................. . 3-27
Dual SPST Precision CMOS Analog Switch ............................................. .
3-27
SPDT Precision CMOS Analog Switch ..................
................................... .
3-27
Dual DPST Precision CMOS Analog Switch ............................................ .
3-27
Dual SPDT Precision CMOS Analog Switch ..........................
.................................. . 3-27
Dual SPST Precision CMOS Analog Switch .............
....................... . 3-32
Dual DPST Precision CMOS Analog Switch ................
............................. . 3-32
SPDT Precision CMOS Analog Switch ......................
....................... . 3-32
Dual SPDT Precision CMOS Analog Switch .....................
.................. . 3-32
Low ON Resistance SPST Analog Switch .................................................................... . 3-38
3-38
Low ON Resistance Dual SPST Analog Switch ........................ .
Low ON Resistance SPDT Analog Switch ........................................................... .
3-38
3-38
Low ON Resistance Dual SPDT Analog Switch
3-38
Low ON Resistance DPST Analog Switch ......... .
..................... '" 3-38
Low ON Resistance Dual DPST Analog Switch.
Low ON Resistance DPDT Analog Switch
.....................
3-38
Low ON Resistance 4PST Analog Switch .....
3~8
........................
Low ON Resistance Dual SPST Switch .. .
..................
....... 3-38
Low ON Resistance Dual DPST Switch ........ .
...........................
3-38
3-38
Low ON Resistance SPDT Switch ...................... .
Low ON Resistance Dual SPDT Switch ....................
........................
.. 3-38
Single 16/Diff. 8 Channel CMOS Analog Multiplexer....
.....................
4-5
Single 16/Diff. 8 Channel CMOS Analog MUX with Active Overvoltage Protection .. 4-11
Latched Sing.le 16/Diff. 8 Channel CMOS Analog MUX with Overvoltage
Protection....... ........................ ...
...... .... ... .... .... ... ..... ........ ... ......... ...... ........
. 4-17
Single 8/Diff. 4 Channel CMOS Analog Multiplexer..... .....................
4-18
Single 8/Difl. 4 Channel CMOS Analog MUX with Active Overvoltage Protection .. 4-25
Latched Single 8/Ditt.4 Channel CMOS Analog MUX with Overvoltage Protection. 4-31
Programmable Single 16/Diff. 8 Channel CMOS High Speed Analog MUX.....
4-32
Programmable Single 8/Diff. 4 Channel CMOS High Speed Analog MUX
4-37
4 Channel Video Multiplexer ............................................. ....................................
... 4-42
4 Channel Low Level Difl. Multiplexer .......................................................................... 4-47
Single 16/Diff. 8 Channel CMOS Analog MUX with Active Overvoltage Protection .. 4-56
Single 8/Ditt. 4 Channel CMOS Analog MUX with Active Overvoltage Protection ... 4-62
........................ 6-17
10-Bit High Speed D/A Converter
8-Bit High Speed D/A Converter
.........................
........................... 6-23
12-Bit High Speed D/ A Converter
.................
..... 6-5
12-Bit High Speed D/A Converter with Reference ................
.................... 6-10
12-Bit High Speed D/ A Converter.
......................... ......................
...... 6-30
12-Bit D/A Converter with Reference (OOC to +70 0 C) .........
...... 6-39
12-Bit D/A Converter with Reference (-40 0 C to +85 0 C)...... .................
·.· ..... 6-45
... 6-48
12-Bit D/A Converter with Reference (-55 0 C to +125 0 C) ..................
Fast 12-Bit V-DAC with Reference (OOC to +70 0 C)........
...... 6-51
Fast 12-Bit V-DAC with Reference (-400C to +85 0 C) ......
6-51
Fast 12-Bit V-DAC with Reference (-55 0 C to +125 0 C)
.6-51
25/1s, Complete 12-Bit A/D Converter with Microprocessor Interface
........ 5-5
Complete, Monolithic 12-Bit Latched D/ A Converter.......................................
6-57
12/1s, Complete 12-Bit A/D Converter with Microprocessor Interface ...........
.. .... 5-16
12-Bit Multiplying D/A Converter ..................................................................
.. 6-66
8.5/1s, Complete 12-Bit AID Converter with Microprocessor Interface ....................... 5-27
7/1s, Complete 12-Bit A/D Converter with Microprocessor Interface .......
.5-38
16-Bit D/A Converter................................................................... ......................
6-73

HV-1 000/1 OOOA

Induction Motor Energy Saver ......................................................................... .

HY-94741/42
HY-9574
HY-9590/91
HY-9595/96
HY-9674
HY-9712

Low Power Sampling 12-Bit A/D Converter with 8/16-Bit Microprocessor Interface. 5-84
Sampling 12-Bit A/D Converter with 8/16-Bit Microprocessor Interface.....
5-51
Data Acquisition Front End ............................................................................................... 7-28
Programmable Gain Ampliifier with Multiplexed Inputs ................................................ 4-72
Sampling 12-Bit A/D Converter with 8/16-Bit Microprocessor Interface
........ 5-68
Complete 12-Bit Data Acquisition Subsystem ...................................
.. .................... 5-86

1-3

2-183

Analog Product Listing
Analog-to-Digital Converters
HI-574A
HI-674A
HI-774
HI-774A

25ps, Complete 12-Bit A/D Converter with Microprocessor Interface ........................ .
12tJs, Complete 12-Bit A/D Converter with Microprocessor Interface ........................ .
8.5ps, Complete 12-Bit A/D Converter with Microprocessor Interface ....................... .
7ps, Complete 12-Bit A/D Converter with Microprocessor Interface ......................... ..

PAGE
5-5
5-16
5-27
5-38

Data Acquisition Module Products
HY-94741/42
HY-9574
HY-9590/91
HY-9595/96
HY-9674
HY-9712

Low Power Sampling 12-Bit A/D Converter with 8/16-Bit Microprocessor
Interface ..........................................................................................................................
Sampling 12-Bit A/D Converter with 8/16-Bit Microprocessor Interface .....................
Data Acquisition Front End ...............................................................................................
Programmable Gain Ampliifier with Multiplexed Inputs ................................................
Sampling 12-Bit A/D Converter with 8/16-Bit Microprocessor Interface .....................
Complete 12-Bit Data Acquisition Subsystem ................................................................

5-84
5-51
7-28
4-72
5-68
5-86

Digital-to-Analog Converters
HI-5618A/18B
HI-5610
HI-562A
HI-565A
HI-5660/60A
HI-5680
HI-5685/85A
HI-5687
HI-5811
HI-7541
HI-5690V
HI-5695V
HI-5697V
HI-DAC16B/C

8-Bit High Speed D/A Converter ......................................................................................
10-Bit High Speed D/A Converter ....................................................................................
12-Bit High Speed D/A Converter ....................................................................................
12-Bit High Speed D/A Converter with Reference .........................................................
12-Bit High Speed D/A Converter ....................................................................................
12-Bit D/A Converter with Reference (OOC to +70 0 C) ...................................................
12-Bit D/A Converter with Reference (-400C to +85 0 C) ................................................
12-Bit D/A Converter with Reference (-55 0 C to +125 0 C) ..............................................
Complete, Monolithic 12-Bit Latched D/A Converter .....................................................
12-Bit Multiplying D/A Converter .....................................................................................
Fast 12-Bit V-PAC with Reference (OOC to +700 C) ........................................................
Fast 12-Bit V-DAC with Reference (-400 C to +85 0 C) ....................................................
Fast 12-Bit V-DAC with Reference (-55 0 C to +125 0 C) ..................................................
16-Bit D/A Converter ..........................................................................................................

6-23
6-17
6-5
6-10
6-30
6-39
6-45
6-48
6-57
6-66
6-51
6-51
6-51
6-73

Multiplexers
SINGLE a/DIFFERENTIAL 4 CHANNEL:
HI-508/509
HI-508A/509A
HI-508LA/509LA
HI-518
HI-548/549
HI-1818A/1828A

Single 8/Differential 4 Channel CMOS Analog Multiplexer...........................................
Single 8/Differential 4 Channel CMOS Analog MUX with Active Overvoltage
Protection ........................... ............................................................................................
Latched Single 8/Differential 4 Channel CMOS Analog MUX with Overvoltage
Protection .......................................................................................................................
Programmable Single 8/Differential 4 Channel CMOS High Speed Analog MUX ......
Single 8/Differential 4 Channel CMOS Analog MUX with Active Overvoltage
Protection ... ........................ ............................................................................................
Low Resistance Single 8/Differential 4 Channel CMOS Analog Multiplexer ..............

4-18
4-25
4-31
4-37
4-62
4-68

SINGLE 16/DIFFERENTIAL a CHANNEL:
HI-506/507
H 1-506A/507A
H 1-506LA/507LA
HI-516
HI-546/547

Single 16/Differential 8 Channel CMOS Analog Multiplexer. ........................................
Single 16/Differential 8 Channel CMOS Analog MUX with Active Overvoltage
Protection .......................................................................................................................
Latched Single 16/Differential 8 Channel CMOS Analog MUX with Overvoltage
Protection .......................................................................................................................
Programmable Single 16/Differential 8 Channel CMOS High Speed Analog MUX ....
Single 16/Differential 8 Channel CMOS AnalogMUX with Active Overvoltage
Protection .......................................................................................................................

4-5
4-11
4-17
4-32
4-56

4 CHANNEL:
HI-524
HI-539

4 Channel Video Multiplexer ...•......................................................................................... 4-42
4 Channel Low Level Differential Multiplexer ................................................................. 4-47

1-4

Analog Product Listing (Continued)
Operational Amplifiers: High Slew-Rate
SINGLES:
HA-OP37
HA-2510/12/15
HA-2520/22/25
HA-2539
HA-2540
HA-2541
HA-2542
HA-2620/22/25
HA-5101/5111 ADVANCE
HA-5147
HA-5160/62
HA-5190/95

High Sleyv Rate, Precision, Low Noise Operational Amplifier ................................. .
High Slew Rate Operational Amplifiers ..................................................................... .
High Slew Rate Operational Amplifiers ................................................................... .
High Slew Rate, Wide Bandwidth Operational Amplifier ......................................... .
High Slew Rate, Wide Bandwidth Operational Amplifier ........................................ .
High Slew Rate, Unity Gain Stable Operational Amplifier ....................................... .
High Slew Rate, Power Operational Amplifier .......................................................... .
Wide Bandwidth Operational Amplifiers .................................................................... .
Low Noise, High Performance Operational Amplifiers ............................................ .
High Slew Rate, Precision, Low Noise Operational Amplifier ................................. .
High Slew Rate, Wide Bandwidth J-FET Operational Amplifiers ............................ .
High Slew Rate, Fast Settling Operational Amplifiers .............................................. .

PAGE
2-25
2-42
2-46
2-50
2-56
2-62
2-66
2-76
2-128
2-148
2-157
2-276

Dual High Slew Rate, Low Noise Operational Amplifier ............................. .

2-129

PRAM Four Channel Programmable Amplifiers ........................................................ . 2-30
Digital Selectable Four Channel Operational Amplifier ........................................... . 2-34
Quad High Slew Rate, Low Noise Operational Amplifier ....................................... . 2-129

Operational Amplifiers: Wide Bandwidth
SINGLES:
HA-OP37
HA-2510/12/15
HA-2520/22/25
HA-2539
HA-2540
HA-2541
HA-2542
HA-2600102/05
HA-2620/22/25
HA-5147
HA-5160/62
HA-5190/95

High Slew Rate, Precision, Low Noise Operational Amplifier ..................................
High Slew Rate Operational Amplifiers .......................................................................
High Slew Rate Operational Amplifiers .......................................................................
High Slew Rate, Wide Bandwidth Operational Amplifier ..........................................
High Slew Rate, Wide Bandwidth Operational Amplifier ..........................................
High Slew Rate, Unity Gain Stable Operational Amplifier ........................................
High Slew Rate, Power Operational Amplifier ...........................................................
General Purpose High Performance Operational Amplifiers...................................
Wide Bandwidth Operational Amplifiers .....................................................................
High Slew.Rate, Precision, Low Noise Operational Amplifier ..................................
High Slew Rate, Wide Bandwidth J-FET Operational Amplifiers .............................
High Slew Rate, Fast Settling Operational Amplifiers..............................................

2-25
2-42
2-46
2-50
2-56
2-62
2-66
2-72
2-76
2-148
2-157
2-276

DUALS:
HA-5112

Dual High Slew Rate, Low Noise Operational Amplifier ........................................... 2-129

QUADS:
HA-2400104/05
HA-2406
HA-5114

PRAM Four Channel Programmable Amplifiers ......................................................... 2-30
Digital Selectable Four Channel Operational Amplifier ............................................ 2-34
Quad High Slew Rate, Low Noise Operational Amplifier ........................................ 2-129

Operational Amplifiers: Precision
HA-OP07
HA-OP27
HA-5134 ADVANCE
HA-5147
HA-5170
HA-5180/80A

W:;:

Zo:
WO

QUADS:
HA-2400104/05
HA-2406
HA-5114

«I0:«
C!Ju..
Z

DUALS:
HA-5112

Z

..... !:

Precision Operational Amplifier ..................................................................................
Precision, Low Noise Operational Amplifier........ .................................
Precision Quad Operational Amplifier ........................................................................
High Slew Rate, Precision, Low Noise Operational Amplifier ..................................
J-FET Precision Operational Amplifier .......................................................................
J-FET Precision, Low Bias Current Operational Amplifier .......................................

1-5

2-12
2-20
2-141
2-148
2-164
2-169

Analog Product Listing (Continued)
Operational Amplifiers: Low Power
SINGLES:

HA-5141
HA-5151/52/54

PAGE
Ultra-Low Power Operational Amplifier ...................................................................... 2-142
Low Power Operational Amplifiers .............................................................................. 2-153

DUALS:

HA-5142
HA-5151/52/54

Dual Ultra-Low Power Operational Amplifier ............................................................. 2-142
Low Power Operational Amplifiers .............................................................................. 2-153

QUAPs(

HA-5144
HA-5151/52/54

Quad Ultra-Low Power Operational Amplifier ........................................................... 2-142
Low Power Operational Amplifiers .............................................................................. 2-153

Operational Amplifiers: General Purpose
SINGLES:

HA-2600/02/05
HA-5101/5111 ADVANCE

General Purpose High Performance Operational Amplifiers .................................... 2-72
Low Noise, High Performance Operational Amplifiers ............................................. 2-128

DUALS:

HA-5102
HA-5112

Dual Low Noise Operational Amplifier ........................................................................ 2-129
Dual High Slew Rate, Low Noise Operational Amplifier ........................................... 2-129

QUADS:

HA-2400/04/05
HA-2406
HA-5104
HA-5114

PRAM Four Channel Programmable Amplifiers .........................................................
Digital Selectable Four Channel Operational Amplifier ............................................
Quad Low Noise Operational Amplifier ......................................................................
Quad High Slew Rate, Low Noise Operational Amplifier .........................................

2-30
2-34
2-129
2-129

Operational Amplifiers: High Voltage
HA~2640/45

High Voltage Operational Amplifiers ........................................................................... 2-84

Operational Amplifiers: Addressable
HA-2400/04/05
HA-2406

PRAM Four Channel Programmable Amplifiers ......................................................... 2-30
Digital Selectable Four Channel Operational Amplifier ............................................ 2-34

Operational Amplifiers: Current Buffers
HA-2630/35
HA-5002
HA-5033

High Performance Current Boosters ........................................................................... 2-80
Wideband, High Slew Rate, High Output Current Buffer ......................................... 2-116
Wideband, High Slew Rate Current Buffer ................................................................. 2-120

Operational Amplifiers: Sample and Hold
HA-2420-1
HA-2420/25
HA-5320
HA-5330

High Temperature Sample and Hold Amplifier ..........................................................
Fast Sample and Hold Amplifier ..................................................................................
High Speed Precision Sample and Hold Amplifier ....................................................
Very High Speed Precision Sample and Hold Amplifier ...........................................

7-5
7-10
7-17
7-24

Comparators
HA~4900/02/05

Quad High Speed Comparators ................................................................................... 2-109

Control Functions
HV-1000/1000A

Induction Motor Energy Saver ..................................................................................... 2-183

1-6

Analog Product Listing (Continued)
Switches
SPST:

HI-5040

PAGE

Low ON Resistance SPST Analog Switch ...................................................................... . 3-37

2 x SPST:
HI-200
HI-300
HI-304
HI-381
HI-5041
HI-5048
4

Dual SPST General Purpose CMOS Analog Switch .................................................... ..
Dual SPST Precision CMOS Analog Switch ................................................................. ..
Dual SPST Precision CMOS Analog Switch .................................................................. .
Dual SPST Precision CMOS Analog Switch ................................................................. ..
Low ON Resistance Dual SPST Analog Switch ............................................................ ..
Low ON Resistance Dual SPST Switch ......................................................................... ..

3-6
3-27
3-27
3-32
3-37
3-37
Z

x SPST:

H 1-201
HI-201HS

Quad SPST General Purpose CMOS Analog Switch .................................................... . 3-12
Quad SPST High Speed CMOS Analog Switch ............................................................ .. 3-18

C!lu..

SPDT Precision CMOS Analog Switch .............................................................. ;............ .
SPDT Precision CMOS Analog Switch ,............................................ ;............................. .
SPDT Precision CMOS Analog Switch ....................... ;...... : ........................................... ..
Low ON Resistance SPDT Analog Switch ..................................................................... ..
Low ON Resistance SPDT Switch ................................................................................... .

3-27
3-27
3-32
3-37
3-37

Dual SPDT Precision CMOS Analog Switch ........................., ....................................... ..
Dual SPDT Precision CMOS Analog Switch ................ " .................................. ,............ "
Dual SPDT Precision CMOS Analog Switch ..... ,............................................................ .
Low ON Resistance Dual SPDT Analog Switch ............................................................. .
Low ON Resistance Dual SPDT Switch ...........................................................................

3-27
3-27
3-32
3-37
3-37

2 x SPOT:
HI-303
HI-307
HI-390
HI-5043
HI-5051
OPST:

HI-5044

Low ON Resistance DPST Analog Switch ...................................................................... . 3-37

2 x OPST:
HI-302
HI-306
HI-384
HI-5045
HI-5049

Dual DPST Precision CMOS Analog Switch ...................................................................
Dual DPST Precision CMOS Analog Switch ..................... ;............................................ .
Dual DPST Precision CMOS Analog Switch ............................ ,.................... :................ .
Low ON Resistance Dual DPST Analog Switch ................................................... " ........ .
Low ON Res.istance Dual DPST Switch ................................ ,........................................ ..

3-27
3-27
3-32
3-37
3-37

OPOT:

HI-5046/46A

Low ON Resistance DPDT Analog Switch ...................................................................... 3-37

4PST:

HI-5047/47A

Low ON Resistance 4PST Analog Switch ...................................................................... . 3-37

Telecommunication Circuits
HC-5502A
HC-5504
HC-5508/09
HC-5510/11
HC-5512/12A
HC-5512C
HC-5512D
H C-5552/53/54/57
HC-5560 ADVANCE
HC-5572 ADVANCE
HC-5580 ADVANCE
HC-5581 ADVANCE
HC-5590 ADVANCE
HC-55536
HC-55564
HF-10

Zo:

wo

SPOT:

HI-301
HI-305
HI-387
HI-5042
HI-5050

-,S!
«I0:«
w:;:

SLiC Subscriber Line Interface Circuit .......................................................................
SLiC Subscriber Line Interface Circuit .......................................................................
SLiCs Subscriber Line Interface Circuit .....................................................................
Monolithic CODECs ......................................................................................................
PCM Monolithic Filter ...................................................................................................
PCM or CVSD Monolithic Filter ...................................................................................
PCM Monolithic Filter (-55 0 C to +125 0 C) ..................................................................
Monolithic CMOS Serial Interface CODEC/Filler Family .........................................
Transcoder ......................................................................................................................
2400/1200/600/300 BPS Modem ...................................................................................
Trunk Subscriber Line Interface Circuit (TSLlC} ....................................................
DAA Subscriber Line Interface Circuit (DAASLlC) ...................................................
Digital Line Transceiver ................................................................................................
All-Digital Continuously Variable Slope Delta Demodulator (CVSD) .....................
All-Digital Continuously Variable Slope Delta Modulator/Demodulator
(CVSD) .......................................................................................................................
Universal Filter ...............................................................................................................

1-7

8-7
8-12
8-17
8-24
8-33
8-40
8-48
8-57
8-82
8-86
8-83
8-84
8-85
8-68
8-72
8-79

==

Ordering Information
Harris products are designated by "Harris Product
Code". These products will always begin with the
leUer'H'and specific device numbers are isolated by

hyphens. An example product code is shown below.
When ordering, please refer to products by the full
code identification.

HARRIS PRODUCT CODE EXAMPLE

H I

T

PREFIX:
H (HARRIS)
FAMILY:
A: Analog
C: Communications
D: Digital
F: Filters
I: Interface
M: Memory
V: 'Analog, High Voltage
Y: Analog Hybrids

1 -:
2 -:
3 -:
4 -:
4P -:
5 -:
7 -:

9 -:

1 -

0508A -

T

I

PART NUMBER

T

TEMPERATURE:
-1: OoC to +2000 C'
-2: -55 0 C to +125 0 C
-4: -25 0 C to +85 0 C
-5: OOC to +75 0 C
-6: 100% +25 0 C Probe (Dice Only)
-7: Dash-7 High Reliability Commercial
Product. OoC to +75 0 C
-8: Dash-8 Program, Hi-Rei Processing
with Burn-in, -55 0 C to +125 0 C
-9: -400 C to +850 C
-9+: -400 C to +850C with Burn-in
/883: MIL-STD-883 Class B, Full Compliance

PACKAGE:
Dual-In-Line, Ceramic
Metal Can
Dual-in Line, Plastic
Ceramic Leadless Chip Carriers (LCC)
Plastic Leaded Chip Carriers (PLCC)
LCC Hybrid
Mini-DIP, Ceramic
Chip Form

COMMERCIAL, INDUSTRIAL PRODUCTS
Harris Semiconductor offers a variety of product
grades to let you satisfy system requirements.
These grades are differentiated in four areas:
1)
2)
3)
4)

5

Operating Temperature Range
Electrical Performance
Package Type
Additional Screening Tests

* Special high temperature testing available on
certain product types. Consult factory for
availability.

cified over the -55 0C to +1250C temperature
range with the additional screening indicated in
Chapter 9. Please refer to the "Military Products"
section for information regarding Harris Semiconductor's MIL-STD-883 compliant program.
SPECIAL ORDERS

These parts are marked with appropriate prefix and
suffix designations. Product designations for each
of the grading parameters are illustrated in the
Product Code Example. The information contained
in this catalog is intended to describe the expected
product performance under the specified operating
conditions for each temperature and performance
grade.
Device testing sufficient to assure conformance is
performed to provide the highest quality in the most
cost-effective manner. For those customers who
wish to have additional screening (burn-in, etc.),
Harris offers DASH 7, DASH 8 and DASH 9+
screening programs (described in section 9 of thi~
catalog).
Military customers are advised that the Harris DASH
8 program is not fully compliant to MIL-STD-883.
The Harris DASH 8 program provides products spe-

1-8

For best availability and price, it is urged that
standard "Product Code" devices be specified,
which are available worldwide from authorized
distributors. Where enhanced testing is needed,
please refer to the Harris standard DASH 7, DASH 8
or DASH 9+ screening options described in this data
book.
Harris application engineers may be
consulted for information concerning suitability of a
product for a given application.
If additional electrical parameter guarantees for
reliability screening are absolutely required, a
Request For Quotation and Source Control
Drawing should be submitted through the local
Harris Sales Office or Sales Representative. Harris
reserves the right to decline to quote, or to request
modification to, special screening requirements.
MILITARY PRODUCTS
Harris offers a full line of products that are
processed in full conformance to the provisions of
military standards including MIL-STD-883C for

MILITARY PRODUCTS (Continued)
Class B parts. The requirements for these products
are controlled in one or two ways:
1. Government standards (such as JAN Slash
Sheets or DESC Drawings)
2. Harris Standards
The Harris standard Military Products Program is
based on its experience in the JAN program. JAN
certifications are maintained on our production and
Product Assurance operations and form the basis of
our MIL-STD-883 conformance program. These
areas are regularly audited by Harris and by the U.S.
government to assure compliance.
Selected products have been qualified to the MILM-38510 requirements and are listed on the QPL.
There are also a number of Harris parts which are
specified by DESC Drawings. In addition, Harris
offers many products as fully conformant to MILSTD-883 via an internal standards program. Please
contact the factory or your local Harris Sales Office

or Representative for the latest status on military
standard compliant product offerings.
The information in this catalog is intended to describe the expected part behavior under certain
operating conditions. The product descriptions
contained in this catalog, particularly in the area of
electrical performance, do not precisely reflect
those of our JAN qualified, DESC or MIL-STD-883
compliant products and are not necessarily test requirements for Harris military standard compliant
products.

z
..... !:

«Ia:

ul.L

0...--'
0
«CI:

2

Ordering Information

2-3

Standard Products
Packaging Availability

2-3

Selection Guides

2-5

Operational Amplifiers Glossary

2-11

Product Information

2-12

ABSOLUTE MAXIMUM RATINGS
As with all semiconductors, stresses listed under "Absolute Maximum Ratings"
may be applied to devices (one at a time) without resulting in permanent damage.
This is a stress rating only. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. The conditions listed under
"Electrical Characteristics" are the only conditions recommended for
satisfactory operation.

2-1

0...!;2:

00

u

Operational Amplifiers, Comparators
and Control Functions
PAGE

HA-OP07
HA-OP27
HA-OP37
HA-2400/04/05
HA-2406
HA-2500/02/05
HA-2510/12/15
HA-2520/22/25
HA-2539
HA-2540
HA-2541
HA-2542
HA-2544
HA-2600/02/05
HA-2620/22/25
HA-2630/35
HA-2640/45
HA-2650/55
HA-2720/25
HA-4600/02/05
HA-4741
HA-4900/02/05
HA-5002
HA-5033
HA-5101/5111
HA-5102
HA-5104
HA-5112
HA-5114
HA-5130/35
HA-5134
HA-5141/42/44
HA-5147
HA-5151/52/54
HA-5160/62
HA-5170
HA-5180/80A
HA-5190/95
HV-1 000/1 OOOA

Precision Operational Amplifier .......................................:., .......................................... :. ..... ..
Preceision, Low Noise Operational.All)p1ifier ................ ,................................ ,.................. ..
High Slew Rate, Precision, Low Noie;e Operational Amplifierc ........................................ :..
PRAM Four Channel Programmable Amplifiers ..................................................................
Digital Selectable Four Channel Operational Amplifier ......................................................
High Slew Rate. Operational Amplifiers ................. ;.. , .•.... :................ :.................................. .
High Slew Rate Operational Amplifiers ................................................................................
High Slew Rate Operational Amplifiers ................................................................................
High Slew Rate, Wide Bandwidth Operational Amplifier .................................................. ..
High Slew Rate, Wide Bandwidth Operational Amplifier .................................................. ..
High Slew Rate, Unity Gain Stable Operational Amplifier .................................................
High Slew Rate, PQwer Operational Amplifier .................................................................... .
Video Operational Amplifier ...................................................................................................
Wide Bandwidth Operational Amplifiers .......................................................................,...... .
Wide Bandwidth Operational Amplifiers ............................................................................. ..
High Performance Current Boosters .....................................................................................
High Voltage Operational Amplifiers ................................................................................... ..
Dual High Performance Operational Amplifiers ................................................................ ..
Programmable Low Power Operational Amplifiers .............................................................
Quad High Performance Operational Ampl ifiers .................................................................

g~:~ ~~e:~~ene~ ~~~~~~~t~~~::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::':::::::::::::::::::::::::::::::

High Slew Rate, High Output Buffer Amplifier .................................................................. ..
Wideband, High Slew Rate Buffer Amplifier ...................................................................... ..
Low Noise, High Peformance Operational Amplifiers ........................................................ .
Dual Low Noise Operational Amplifier .................................................................................
Quad Low Noise Operational Amplifier ................................................................................
Dual High Slew Rate, Low Noise Operation\ll Amplifier .................................................... .
Quad High Slew Rate, Low Noise Operational Amplifier ...................................................
Precision Operational Amplifiers ...........................................................................................
Precision Quad Operational Amplifier ................................................................................ ..
Ultra-Low Power Operational Amplifiers ............................................................................ ..
High Slew Rate, Precision; Low Noise Operational Amplifier .......................................... ..
Ultra-Low Power Operational Amplifiers ............................................................................ ..
High Slew Rate, Wide Bandwidth J-FET Operational Amplifiers ..................................... .
J-FET Precision Operational Amplifier .................................................................................
J-FET Precision, Low Bias Current Operational.Amplifier .................................................
High Slew Rate, Fast Settling Operational Amplifier ..........................................................
Induction Motor Energy Saver ...............................................................................................

2-2

2-12
2-20
2-25
2-30
2-34
2-38
2-42·
2-46
2-50
2-56
2-62
2-66
2-71
2-72
2-76
2-80
2-84
2-88
2-92
2-98
2-105
2-109
2-116
2-120
2-128
2-129
2-129
2-129
2-129
2-134
2-141
2-142
2-148
2-153
2-157
2-164
2-169
2-176
2-183

Ordering Information
HARRIS PRODUCT CODE EXAMPLE

H A 7
PREFIX:

------IT

H (HARRIS)

T

5135 -

M

T

PART NUMBER

TEMPERATURE:
OOc to +200o C

FAMILY: _ _ _ _ _ _ _--.J
A
C
o

5

--,--

-

Analog
Communications
Digital
Filters
Interface
Memory
Analog, High Voltage
Analog Hybrids

4

-

*

-55°C to +12So C
-250C to +8S o C

OoC to +7S o C
100% +2S oC Probe (Dice Only)
Dash-? High Reliability Commercial
Product. OOC to +7S 0 C
Oash-8 Program
HA2-2S20-8 (Example only)

-40°C to +8So C

PACKAGE: - - - - - - '
Dual-in-Line, Ceramic
Metal Can
Dual-In Line, Plastic
Leadless Carriers
Lee Hybrid

*

Special high temperature testing available
on certain product types. Consult factory for
availability.

Mini-DIP, Ceramic
Chip Form

Standard Products Packaging Availability
PACKAGE

PLASTIC
DIP

CERAMIC
DIP

3TEMPERATURE

-5

CERAMIC
MINI DIP

1-7

-1

-2

-4

-5

-8

-9

-2

-4

LCC PLCC
4-

4P-

-5

-8

-8

-5

X

X
X
X

X
X

2-

7-7

SURFACE
MOUNT

METAL
CAN

-5

-8

X

X
X
X

-1

-2

-4

X
X
X

X
X

DEVICE NUMBER
HA-OP07
HA-OP27
HA-OP37
HA-2400
HA-2404
HA-2405
HA-2406
HA-2500
HA-2502
HA-2505
HA-2510
HA-2512
HA-2515
HA-2520
HA-2522
HA-2525
HA-2539
HA-2540
HA-2541
HA-2542
HA-2544
HA-2600
HA-2602
HA-2605
HA-2620
HA-2622
HA-2625

X
X
X

X
X
X
X

X

X
X
X
X

X

X
X
X

X

X
X

X
X

X
X

X

X

X

X

X

X

X

X
X
X

X

X
X

X
X

X

X
X
X

X

X
X
X

X

X
X

X

X

X
X

X
X
X

2-3

X

X

X

X

X
X
X

X

X
X

X

X

X
X
X
X

X
X
X

X

X

X
X
X

X
X
X

X

X
X

X
X
X

X
X

X
X

X
X
X

X
X
X
X
X

X
X
X
X

Standard Products Packaging Availability

PACKAGE

TEMPERATURE

(Continued)

PLASTIC
DIP

CERAMIC
DIP

CERAMIC
MINI DIP

METAL
CAN

3-

1-

7-

2-

-5

-7

-1

-2

-4

-5

-7

-8

-9

-2

-4

-5

-8

-1

-2

-4

-5

SURFACE
MOUNT
LCC PLCC

-8

4-

4P-

-8

-5

DEVICE NUMBER

HA-2630
HA-2635
HA-2640
HA-2645

i

X
X
X

HA-4600
HA-4602
HA-4605

X
X

X

X
X

X

X

X
X

X
X

X

X

X
X

X

X
X

X
X

X
X
X

X

X

X
X
X

X
X

X

HA-5111
HA-5112
HA-5114

X
X
X

HA-5130
HA-5134
HA-5135

X

HA-5141
HA-5141A
HA-5142
HA-5142A
HA-5144
HA-5144A
HA-5147

X
X
X

HA-5151
HA-5152
HA-5154

X
X
X

HA-5190
HA-5195
HV-1000

X
X

X
X
X
X

HA-5180
HA-5180A

X
X

HA-5002
HA-5033
HA-51 0.1
HA-5102
HA-5104

HA-5160
HA-5162
HA-5170

X
X

HA-2650
HA-2655
HA-2720
HA-2725

HA-4741
HA-4900
HA-4902
HA-4905

X

X

X

X

X

X
X

X
X

X
X

X
X

X
X
X
X

X
X
X
X

X
X
X
X

X
X

X
X

X
X

X
X

X
X

X

X

X

X

X

X

X

X

X

X

X

X

X

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

X

X

X

X

X

X

X

X

X

X
X

X
X

X
X
X

X

X

X

X

X

X

X

X
X

X
Xl

X
X

X
X

X

X

X
X

x

I
X

X

x

X

X

X

X

X

X

X

X

X
X
X

X

X
X

X
X

X
X

X
X

X
X

X
X

X
X

X

X
X

X

X

X
X

X

2-4

X

X

X
X
X
X

X

X
X
X
X
X
X

X

X

Selection Guide

OPERATIONAL AMPLIFIERS: HIGH SLEW-RATE
Temp. Range
Part
Number

-5SoC

ooc

10
+12SOC

10
+7S OC

Open Loop
Gain
(V/mV)

Minimum
Gain
Stable

Comments

Page

x

17

63

0.3

8

1500

5

Low Noise

2-25

X

35

100

0.5

8

1800

10

Low Noise

2-148

HA-2620

X

35

100

0.6

1

150

5

HA-2622

X

35

100

0.6

5

150

5

2-76

35

100

0.6

5

150

5

2-76

60

12

1.0

125

15

Unity

2-42

X

60

12

1.0

125

15

Unity

2-42

X
X

2-76

HA-2510

X

65

12

1.0

100

15

Unity

X

X

70

100

1.0

0.02

100

10

JFET

2-157

HA-5160

X

X

120

100

1.9

0.02

150

10

JFET

2-157

HA-2520

X

120

20

1.9

100

15

3

2-46

HA-2522

X

120

20

1.9

125

15

3

2-46

120

20

1.9

125

15

3

2-46

200

150

6.5

5000

30

5

2-176

200

150

6.5

5000

30

5

2-176

X
X

HA-5195

X

2-42

HA-2541

X

X

300

40

4.7

6000

10

Unity

HA-2542

X

X

350

60

5.5

6000

10

2

HA-2540

X

X

X

400

400

6.0

5000

15

10

2-56

HA-2539

X

X

X

600

600

9.5

5000

15

10

2-50

HA-5111

X

X

20

60

0.3

150

500

10

Low Noise

2-128

HA-5112

X

X

20

60

0.3

130

250

10

Low Noise

2-129

HA-5114

X

X

HA-2400

X

2-62
Power Output

2-66

Q

I/)

Q

c.:G

::;:z
o=>
UU-

HA-5162

HA-5190

...

Bias
Current
(nA)

X

HA-2525

<
;:)

Full Power
Bandwidth
(MHz)

X

HA-2515

z
iii

Bandwidth
Product
(MHz)

HA-OP37

HA-2512

...0w

Slew
Rate
(V//Js)

HA-5147

HA-2625

I/)

.40OC
10
+8S OC

2-129

20

60

0.3

130

250

10

Low Noise

30

40

0.5

50

150

10

Addressable

2-30

<
;:)

HA-2404

30

40

0.5

50

150

10

Addressable

2-30

0

HA-2405

X

30

40

0.5

50

150

10

Addressable

2-30

HA-2406

X

30

40

0.5

50

150

10

Addressable

2-34

X

2-5

D •.-"'"

::;:0

:G

:;:2

o=>
uu..
c.,-....J
:;0
2kSl

0.5

O.S

SW

Closed Loop Bandwidth

AVCL=+1.0

0.6

2.5

AO

Open Loop Output Resistance

-

45

-

ICC

Supply Current

-

1.0

1.3

Po

Power Consumption

AL

f

~

~

2KSl

100H,

No Load

i 12

VCC-±15V
VCC ~ ±3V

-

V

-

dB

130

-

dB

140

-

dB

:!:. 11.5
± 10

.± 12

0.5

0.8

-

V/p.s

0.6

2.5

-

MH,

-

45

-

n

1.0

1.7

mA

50
S

mW

-

35
6.0

V

ELECTRICAL CHARACTERISTICS at Vs =± 15V, OOC ~TA-:;:+700C, unless otherwise stated.
HA-OP07C

HA-OP07E
SYMBOL
VOS
TCVOS
lOS
TCIOS
IS
TCIS
IVA

MIN

TYP

MAX

MIN

TVP

MAX

UNITS

-

50

130

-

50

250

~V

-

0.4

0.6

-

0.4

1.3

}lV/oC

Input Offset Current

-

5.3

-

S.O

nA

Avg.lnput Offset Current Drift

-

20

40

-

20

50

pAroC

Input Bias Current

-

-

5.5

-

-

9.0

nA

Avg. Input Bias Current Drift

-

20

40

-

20

50

pA/oC

±. 12

-

-

120

-

±. 12

110

VS-±3Vto±18V

100

130

INote 3)

120

-

AL ~ 600Sl
AL ~ 2kn

:t 10
± 12

-

-

±1O
±11.5

PARAMETER
Input Offset Voltage
Avg. Input Offset Voltage
Drift Without External Trim

Input Voltage Range

CMAA

Common Mode Rejection Ratio

PSRA

Power Supply Rejection Ratio

AVO

Large Signal Voltage Gain

Vo

CONDITIONS

Output Voltage Swing

VCM

~±

10V

-

V

106

120

-

dB

-

94

130

-

dS

-

100

-

-

dB
V

NOTES: 1. Absolute maximum ratings are limiting values, applied individually beyond which the serviceability
of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied.
2. Derate at 6.8mW/oC for operation at ambient temperatures above +75 0 C.
3.

VOUT ~± 10V; RL ~ 2kl1.

Gain dB ~ 20 10910 Average

.·.120dB = 1000V/mV
140dB ~ 10,000V/mV

2-14

TEST CIRCUITS

,...
C)

Q.

SLEW RATE AND TRANSIENT RESPONSE TEST CIRCUIT

a
I

c(
IN

@)

J:

J>I nnI

I

-

-

SMALL SIGNAL RESPONSE
Vertical Scale: (Volts: 50mV/Div. Output)
(Volts: 100mV/Div. Input)
Horizontal Scale: (Time: 1J.1s/Div.1

I> OUT

I100PF

LARGE SIGNAL RESPONSE
Vertical Scale: (Volts: 5V/Div.1
Horizontal Scale: (Time: 5J.1s/Div.l

c,;,"",

::;:~
o=>
uu.
Q,: - '

::;:0

«'"

"-~

00

u

INPUT

"

INPUT

OUTPUT

~

OUTPUT

l

V

I"

"~

SETTLING TIME CIRCUIT

-.l

~

+15V
2N441~

.,

......
5k

5k

A

.AAA
',",,",

+15V?

VIN

no

-0

2k~
'>~

~~

A~'~
~
"''"'
-~V

TO
OSCILLOSCOPE

.....J

:r
-=

J-100
pF

~

2N4416

~

~: 3k

~~

-

'" VOUT

eAv=-l.
e Feedback and summing
resistors should be 0.1%.
e Clipping diodes are optional.
HP5082-2810 recommended.

2k

2-15

PERFORMANCE CURVES

INPUT OFFSET VOLTAGE, INPUT BIAS

INPUT BIAS CURRENT VS.

AND OFFSET CURRENT VS. TEMPERATURE

DIFFERENTIAL INPUT VOLTAGE

"-

""-

~ INPUT

BIAS CURRENT

l

~
II:

0

0

II:

a

~

'\ ~
.

"-.

0

.....

:/ -2

INPUT OFFSET CU RENT

..............

""""-

...

0
-60

iii ...

/TVp~rL-

.;> l'-...iVOS
I+6D

TEMPERATURE

i..--"

..-

..-

vV

.".

-6

-

...

+'20

-10

+'60

-8

-6

-4

'0

-2

DIFFERENTIAL INPUT VOLTAGE-VOL T8

oc

OFFSET VOLTAGE
STABILITY VS. TIME

INPUT - NOISE VS. FREQUENCY

VSUPPL Y = ±15V

I

Tc = ±lOC

'IV· '000

10

~

-

J

~

~ 10

ZATION PERIOD.

1\

'2

. \"-~
..g \

NOTE: MEASUREMENT AND
ENVIRONMENTAL SYSTEMS
ALLOWED 12 HOUR STABILI-

---- --

,..
,.2~

,.

b~Dh,6~s, 1 1

NOISE VJL TAGE

8

!Il

-5

~

I-

~

-10

20

30
TIME-DAYS

~SECI"RENT

'0

lK

'00

10K

OPEN LOOP FREQUENCY RESPONSE
.. '60

:

140

~

120

."r-.... .....

~ 100

~

g

8
...

z

.50

~

"'"

80
60

..... i"o."
GAIN

~ASEANGLE

.....

40

...... "-

...... ,\.

20

*-2~,

00

I
I

'0

'00

lK

10K

FREQUENCV -Hz

2-16

lOOK

1M

"

~

:z:
.00 ..

,
,

...

10M

iE
II:
II:

a

.4 ~

.,/

FREQUENCY - HZ

!
':;

/

.2

o

40

.0

••

\

•

,

.7

;!

246810

,.../

lOOK.

PERFORMANCE CURVES (Continued)

....
o
o
«
J:
Q.

CLOSED LOOP FREQUENCY RESPONSE

SMALL SIGNAL BANDWIDTH AND

FOR VARIOUS CLOSED LOOP GAINS

PHASE MARGIN VS. LOAD CAPACITANCE

I

.....

BO

!9

70
Z· BO

"-

2.&

~

~50

,

......... ~

I'..

~40

9 30

~20
9
10
u

"-

"""

-10

10

100

lK

10K

TOOK

PHASE MARGIN

"

1M

FREQUENCY,Hz

10M

100

00

10

laO

2.5

BANDWIDTH

"K\'\

2,4

2.35

1000
10,000
LOAD CAPACITANCE-pf .

OUTPUT VOLTAGE SWING VS.

MAXIMUM OUTPUT VOLTAGE SWING VS.

FREQUENCY AND SUPPLY VOLTAGE

LOAD RESISTANCE AND SUPPLY VOLTAGE

36
VSUPPL Y '"

d:

30

g~

25

~"

20

~l20V

VSU"LY;,±l~
VSUPPLr:±10V

w

~ 15

~

o
>

10

i3

5

~

VSUPP/Y = I±5V

~
!i!

20

~

15

g

10

~
!5

5

~w

\

I,

lK

S 25

'"l\

,

_\

I
100

~ 30

RL = 2K

10K

o

iVSUPPLY

VSUjLY '"' :tl0V .'

L

L/

10

1M

VSUjLY
100

-±5v

lK

LOAD RESIST ANC~-OHMS

FREOUENCY, Hz

NORMALIZED AC PARAMETERS
VS. SUPPLY VOLTAGE

1. 1

1.0

BA~OWlbTH

VI

0 .•

II-~LEWRATE

0,8
0,7

0.6 0

±2

14

±6

±8

+
_10 ±T2 +
_14 +
_16 ±18 t20

SUPPl y VOLTAGE - VOLTS

+15/

J

'(

1"-TOOK

=

10K

PERFORMANCE CURVES (Continued)
CMRR VS. FREQUENCY

PSRR VS. FREQUENCY

-.....

140
120

140

~

100

""

eo
eo
40

10

~

:!!80

'"

'"
Ie

""

lK

100

"'-

100

a;

20
0,

...........

120

10K

FREaUENCY-Hz

60

40

""

20

a

lOOK

01

""1""-""

100

10

lK

"lOOK

10K

FREQUENCY Hz

SETTLINGTIME FOR VARIOUS

POWER SUPPLY CURRENTVS.

OUTPUT STEP VOLTAGES

TEMPERATURE AND SUPPLY VOLTAGE
!:1.4

~CIJ 10

"'to ......
~g

«0
... :>

10mV

5

g~ 0

~~ -5

t-. t:--.

0.'"

~~-10

o

L---:

V. V
10mV

a

2

4

w

«

P

!.
~

lmv,

§

lmvl

U

>

t

!'"-' F:::::h...

•

8

10

::>

12

14

'"

1.

SETTLING TlME- J.lS

Vs = +20V
..1,
±,.2~VS"+15V

:1::1.0

-.IT

Vs '= +10V

±.Br--- vS '" +SV
!.G

±.4
:1::.2
0
-80

-40

0

+4"

+eo

+120

+160

TEMPERATURE oc

APPLYING THE HA-OP07 OPERATIONAL AMPLIFIERS
1.

2.

POWER SUPPL Y OECOUPLlNG: Although not absolutely
necessary, it is recommended that all power supply lines
be decoupled with .01JJ F ceramic capacitors to ground.
Decoupling capacitors should be located as near to the
amplifier terminals as possible.
CONSIDERATIONS FOR PROTOTYPING: The following
list of recommendations are suggested for prototyping.
Resolving low level signals requires minimizing leakage
currents caused by external circuitry. Use of quality
insulating materials, thorough cleaning of insulating
surfaces, and implementation of moisture barriers
when required is suggested.

3.

When driving large capacitive loads (> 500pF), as small
value resistor (~50 n) should be connected in series with
the output and inside the feedback loop.

4.

OFFSET VOLTAGE ADJUSTMENT: A 20 Kn balance
potentiometer is recommended if offset nulling is required.
However, other potentiometer values such as 10Kn, 50Kn,
and lOOK!'! may be used. The minimum adjustment
range for given values is±2mV.

5.

SATURATION RECOVERY: Input and output saturation recovery time is negligible in most applications. How-·
ever, care should be exercised to avoid exceeding the
absolute maximum ratings of the device.

6.

01 FFERENTIAL INPUT VOLTAGES: Inputs are shunted
with back-to-back diodes for overvoltage protection.
In applications where differential input voltages in excess
of IV are applied between the inputs, the use of limiting
resistors at the inputs is recommended.

•

• Error voltages generated by theromocouples formed
between dissimilar metals in the presence of temperature gradients should be minimized. Isolation of
low level circuitry from heat generating components
is recommended.
• Shielded cable input leads, guard rings, and shield
drivers are recommended for the most critical applications.

2-18

APPLICATIONS

.....

o

PRECISION INTEGRATOR

OFFSET NULLING CONNECTIONS

0.

o

c

I



c..>u..

c..--I

::;;0



HA-OP27A1E
L MIN J TYP I MAX

HA-OP27C/G
MIN
TYP
MAX

UNITS

60

30

100

pV

1.5

0.4

2.0

J./V/Mo

50

12

75

nA

HA·OP27B/F
MIN
TYP
MAX

PARAMETER

SYMBOL

CONDITIONS

Input Offset Voltage

Vas

(Note 1)

10

25

20

VOS/Time

(Note 2)

0.2

1.0

0.3

Long-Term VOS
Stability
Input offset Current

35

lOS

±10

±40

i12

±55

±15

±80

nA

0.08

0.18

0.08

0.18

0.09

0.25

pVp-p

fo 10 Hz (Note 3)
fa ::: 30 Hz (Note 3)
fo::: 1000 Hz (Note 3)

3.5
3.1
3.0

5.5
4.5
3.8

3.5
3.1
3.0

5.5
4.5
3.8

3.8
3.3
3.2

8.0
5.6
4.5

nV/yHz

fa = 10 Hz (Note 3)
fa = 30 Hz (Note 3)
fo = 1000 Hz (Note 3)

1.7
1.0
0.4

4.0
2.3
0.6

1.7
1.0
0.4

4.0
2.3
0.6

1.7
1.0
0.4

0.6

Input Bias Current

IB

Input Noise Voltage

e np _p

0.1 Hz to 10 Hz

Input Noise
Voltage Density

en

Input Noise
Current Density

In

(Note 3. 5)

Input ResistanceDifferential-Mode
Input ResistanceCommon-Mode

=

RIN

(Note 4)

RINCM

(Note 4)

Input Voltage Range

IVR

Common-Mode
Rejection Ratio

CMRR

Power Supply
Rejection Ratio

PSSR

Large-Signal
Voltage Gain

Ava

VCM

=±11

1.5

V

Slew Rate

SR

Gain Bandwidth Prod.

Ro

Power Consumption

Pd

Offset Adjustment
Range

GO

±12.3

±11.0

±12.3

±11.0

±12.3

V

114

126

106

123

100

120

dB

10

10

20

pV/v

1000
800
250

1800
1500
700

1000
800
250

1800
1500
700

700
600
200

1500
1500
500

RL2: 2kn
RL 2: 600n

±12.0
±10.0

±13.8

±12.0
±10.0

±13.8
±11.5

±l1.S

±ll.S

±10.0

±13.5
±11.5

V

RL 2: 2kn (Note 4)

7.0

10

7.0

10

7.0

10

VIps

(Note 4)

5.0

8.5

5.0

8.5

5.0

8.5

MHz

70

0

RL 2: 2kCl, Va = ±10 V

GBW

Open Loop Output
Resistance

MO

±11.0

Vs = ±4 V to ±18 V

RL =6000. Vo =±lV,
Vs =±4V. (Note 4)
Va

0.8

1.2
2.5

RL2:1kCl,VO=±10V

Output Voltage
Swing

pAlyHz

Va

=0.10 =0

70

70

V/mV

(Note 4)

Va

=0

90

Rp= 10 kO

140

±4.0

90
±4.0

140

100

170

±4.0

mW
mV

NOTES:

operation. Excluding the initial hour of operation, changes in

1. Input Offset Voltage measurements are performed by automated test
equipment approximately 0.5 seconds after application of power. NE
Grades Guaranteed Fully Warmed up.

3. Sample tested.

2. Long Term I nput Offset Voltage Stability refers to the average trend
line of VOS vs. Time over extended periods after the first30 days of

5. See test circuit and typical 0.1 Hz to 10 Hz noise photograph.

during the first 30 days are typically 2.5 pV.
4. Guaranteed by design.

2-21

Vas

HA-OP27
Electrical Characteristics for Vs = ±15 V, -55 0 e::s TA::S + 125 0 e, unless otherwise noted.
PARAMETER

SYMBOL

CONDITIONS

VOS

(Note 1)

Input Offset Voltage
Average Input

MIN

HA·OP27A
TYP
MAX

30

60

MIN

HA-OP27B
TYP
MAX

-

50

200

MIN

HA·OP21C
TYP
MAX

-

70

J

UNITS

300

pV

flV/DC

TCVOS

Offset Drift

TCVOSN

-

0.2

0.6

-

0.3

1.3

-

0.4

1.6

Input Offset Current

lOS

-

15

50

-

22

65

-

30

135

nA

IS

-

±20

±60

-

±26

±95

-

±35

±150

nA

IVR

±10.3

±11.S

-

±10.3

±11.5

-

±10.2

±11.5

-

V

100

119

-

94

116

-

dB

Input Bias Current

Input Voltage

R~nge

(Note 2)

Common Mode
Rejection Ratio

CMRR

VCM = ±10 V

106

122

Power Supply
Rejection Ratio

PSRR

Vs = ±4.S V to ±18 V

-

2

16

-

2

20

-

4

51

jlVN

Ava

RL;:: 2KO, Vo == ±lQ V

600

1200

-

500

1000

-

300

600

-

V/mV

V.oM

RV2:,,2kJl

±11.5

±13.S

-

±".0

±13.2

-

±10.5

±13.0

-

V

Large Signal
Voltage Gain

Output
Voltage Swing

....

ElectricaICharaQteri$tic~If.orVS= ±15V,-250e:;;IA::S + 85 0 e, oOe::s TA:;; + lOOe,
.
. ' ". unlessothe(wis.e noted .
.

'

.;

....

PARAMETER
Input Offset Voltage
Average Input

..

.....

I

SYMBOL

CONI1ITIONS
..

'

VOS

MIN

HA-OP27E
TYP
MAX

-

20

50

MIN

HA-OP27F
TYP
MAX

-

40

MIN

HA-OP27G
TYP
MAX

140

-

55

UNITS

220

pV

jN/DC

TCVOS

Offset Drift

TCVOSN

(Note 2)

-

0.2

0.6

-

0.3

1.3

-

0.4

1.6

I nput Offset Current

lOS

-

-

10

50

-

14

65

-

20

135

nA

IS

-

-

±14

±60

-

±18

±95

-

±25

±150

nA

±10.5

±11.8

-

±10.S

±11.B

-

±10.5

±11.8

-

V

110

124

-

102

121

-

96

116

-

dB

-

2

15

2

16

-

2

32

INN

750

1500

-

700

1300

-

450

1000

-

V/mV

±11.7

±13.6

-

±11.4

±13.S

-

±11.D

±13.3

Input' Bias Current
Input Voltage Range

Common Mode

IVR
, ...• CMRR

VCM" ±10 V

Rejection Batio
P9wer Supply
Rejection Ratio
Large Signal
Voltage Gain

PSRR

Ava

V's

RL

=±4.S V to ±18V

<: 2kCl,

Vo" ±10 V

Output
Voltage Swing

VOM

At. 22kO

NOTES:
1. Inpul Offset Voltage measurements are performed by automated test
equipment approximately 0.5 seconds after application of power.

V

2. The TeVOS performance is within the specifications unnulled or when
nulled with Rp = 8kfl to 20kfl.

Test Circuits
LARGE AND SMALL SIGNAL RESPONSE
TEST CIRCUIT
LARGE SIGNAL RESPONSE

SMALL SIGNAL RESPONSE

2-22

HA-OP27

"
c..
N

Test Circuits (continued)

o
I



.s
w

5

4

[\.

1',...... ......

-,

en
Q

"

z

...co

~o

rr-.
1/1 CORNER = 2.7Hz

>

I
I

10

100
FREQUENCY (Hz)

2-24

1000

:II H.6.RRIS

HA-OP37

PRELIMINARY

Ultra-Low Noise, Precision,
High-Speed Operational Amplifier

Features

Applications

• Low Noise ........................................ 3nVlv'HZ at 1 kHz

• Low Level Transducer Amplifiers

• Low Drift ........................................................ 0.2/lV/OC

• Instrumentation Amplifiers

• Low VOS ................................................................ 10 /lV

• Audio Preamplifiers

• High Gain ...................................................... 1800 V/mV

• Precision Threshold Detectors

• High CMRR ......................................................... 126 dB

• Signal Conditioners

• High

S~ew

o:G
::;;z

0:::>

Rate .................................................... 20V//ls

uu..

Co: ...J

::;;0

«II:
,,-I-

Description

oiS
u

The HA-OP37 operational amplifier is a connection
between precision and high speed performance. The low
device nojse, 3 nV/VHz at 1 KHz, allows accurate high
speed amplification of extremely low level signals.
Precision is attained by a low Vos of typically 10 /lV, a
high gain of 1800 V/mV, a differential input resistance of
6MO and an average input offset drift of just 0.2 /lV/OC.
High speed is guaranteed by a slew rate of 17V/ /lS and a
gain bandwidth product of 63 MHz. Alsothe HA-OP37 has
a CMRR above 120 dB and a PSRR of typically 1 /lVIV.

high speed applications where gains are greater than five.
The HA-OP37 can be used for precision threshold
detectors, instrumentation amplifiers, many audio circuits such as RIAA phone preamplifiers, and in signal
conditioning circuits for data acquisition systems.
The HA-OP37 can also be used as an enhancement for
existing designs by directly replacing the 725, OP05,
OP06, OP07 and OP27 where gains are greater than five.
The HA-OP37 is available in TO-99 metal can, both epoxy
and ceramic 8 pin mini-DIPs, as well as 20 pin LCe
packages.

This combination of characteristics makes the HA-OP37
an outstanding choice for all low noise, precision and

Pinouts

Schematic
TOP VIEWS

BALANCE

BALAN"~B

':'

..,

L.

v+

-IN 2

-

1

+IN 3

+

6 OUT

11- 4

':.>"J

~."
BALAN"

""
~

5 Ne

..

V-teASEl

-

~- N-~
t--_-<::w
~."

""-::1

-,

..

.

••

.

,...........

..:...

2-25

,,,.n·,

OM

Specifications
Absolute Maximum Ratings
Supply Voltage .......................................................... ±22V
Internal Power Dissipation (Note 1) ..................... 500mW
Input Voltage (Note 3) ............................................. ±22V
Output Short Circuit Duration ......................... Indefinite
Differential Input Voltage (Note 2) ........................ ±O.7V
Differential Input Current (Note 2) ...................... ±25mA
Storage Temperature Range ............... -650C to +1500 C
Operating Temperature Range
HA-OP37A, OP37B, OP37C (J,Z) ....... -550C to +1250 C
HA-OP37E, OP37F, OP37G (J,Z) .......... -25 0C to +850C
HA-OP37E, OP37F, OP37G (P) ................. OOC to +700 C

Electrical Characteristics
PARAMETER
Input Offset Voltage
Long Term

Maximum Ambient
Package Type
Temperature for Rating
TO-99 (J)
8-Pin Hermetic DIP (Z)
8-Pin Plastic DIP (P)

Derate Above Maximum
Ambient Temperature
'7.1mW/oC
6.7mW/oC
5.6mW/oC

2. The OP3Ts inputs are protected by back-to-back diodes. Current
limiting resistors are not used in order to achieve low noise. If
differential input voltage exceeds ±0.7V, the input current should be
limited to 25mA.
3. For supply voltages less than ±22V, the absolute maximum input
voltage is equal to the supply voltage.

at Vs = ±15 V, T A = 25 0 C, unless otherwise noted.

SYMBOL

CONDITIONS

HA-OP37A1E
MIN TYP MAX

HA-OP'7B/F
MIN TYP MAX

VOS

(Note 1)

10

25

20

VaS/Time

(Note 2)

0.2

1.0

0.3

±10

35
±40

I

HA-OP37C G
MIN TYP MAX

UNITS

60

30

100

pV

1.5

0.4

2.0

IlViMo

50

12

75

nA

±12

±55

::tlS

±80

nA
pVp-p

Vas

Stability.

Input Bias Current

lOS
IB

Input Noise Volt{lge

enp _p

0.1 Hz to 10 Hz
(Note 3, 5)

0.08

0.18

0.08

0.18

0.08

0.25

Input Noise
Voltage Density

en

fa::: 10 Hz (Note 3)
fa ::: 30 Hz (Note 3)
fa::: 1000 Hz (Note 3)

3.5
3.1
3.0

5.5
4.5
3.8

3.5
3.1
3.0

5.5
4.5
3.8

3.8
3.3
3.2

8.0
5.6
4.5

Input Noise
Current Density

In

fa::: 10 Hz (Note 3)
fa = 30 Hz (Note 3)
fa = 1000 Hz (Note 3)

1.7
1.0
0.4

4.0
0.6

1.7
1.0
0.4

0.6

Input Offset Current

Input ResistanceDifferential Mode
Input ResistanceCommon Mode

RIN

(Note 4)

RINCM

(Note 4)

Input Voltage Range

IVR

Common Mode
Rejection Ratio

CMRR

VCM=±ll V

Power Supply
Rejection Ratio

PSSR

Vs = ±4 V to ±16 V

Large Signal
Voltage Gain

AVO

RL ;:::2KCl, Va = :t10V
RL ;:::lKO. Va = ±10V
RL = 6000, Va = ±lV~
Vs = ± 4V, (Note 4)

Output
Voltage'Swing

Vo

RL;::: 2kO
RL;::: 6000

2.3

1.5

4.0

1.7

2.3

1.0
0.4

1.2

0.6

0.8

nV/.../Hz

PA/VHz

MO

2.5

GO

±11.0

±12.3

±11.0

±12.3

±11.0

±12.3

V

114

126

106

123

100

120

dB

10

10

20

1000
800
250

1800
1500
700

1000
800
250

1500
700

700
400
200

1500
1500
500

±12.0

±13.8
±11.5

±12.0
:tl0.0

±13.8
±11.5

±11.5
±10.0

±13.5
±11.5

±10.0

1800

IlVIV

V/rnV

SR

RL;::: 2kO (Note 4)

14

20

14

20

14

20

VipS

GBW

fa = 10 kHz (Note 4)
fa = 1 MHz (Note 4)

60

80
63

60

80

60

63

80
63

MHz

Open Loop Output
Resistance

RO

Vo = 0,10 =0

70

70

0

Power Consumption

Pd

Slew Rate
Gain Bandwidth Prod

Offset Adjustment
Range

70

(Note 4)

Vo = 0

90

Rp = 10 kO

±4.0

140

90
±4.0

140

100
±4.0

170

mW
mV

NOTES:
1. Input Offset Voltage measurements are performed by automated test
equipment approximately 0.5 seconds after application of power. AlE
Grades Guaranteed Fully Warmed up.
2. Long Term Input Offset Voltage Stability refers to the average trend
line of

Vas

vs. Time over extended periods after the first30 days of

operation. Excluding the initial hour of operation. changes in

during the first 30 days are typically 2.5 /lV.
3. Sample tested.
4. Guaranteed by design.
5. See test circuit and typical 0.1 Hz to 10 Hz noise photograpt).

2-26

Vas

HA-OP37

,....
a..

M

Electrical Characteristics for Vs = ±15 V. -55 0 C :::; TA:::; 125 0 C. unless otherwise noted.
PARAMETER
Input Offset Voltage
Average Input

HA-OP37A
TYP
MAX

MIN

HA-OP37B
TYP
MAX

SYMBOL

CONDITIONS

MIN

Vas

(Note 1)

-

30

60

-

50

200

(Note 2)

HA-OP37C
MAX
TYP

I

MIN

-

70

o
I

UNITS

300

pV

TCVOSN

-

0.2

0.6

-

0.3

1.3

-

0.4

1.8

pV/ae

Input Offset Current

lOS

-

15

50

-

22

85

-

30

135

nA

IB

-

±20

±60

-

±28

±95

±35

±150

nA

Input Voltage Range

IVR

±10.3

±11.S

-

:::t:10.3

±11.S

-

±10.2

±11.S

-

V

Common Mode
Rejection Ratio

CMRR

VCM = ±lQ V

108

122

100

119

-

94

116

-

dB

Power Supply
Rejection Ratio

PSSR

VS:: ±4.S V to ±18 V

-

2

16

-

2

20

-

4

51

JNN

Ava

RL 2: 2kO, Vo::: ±10 V

600

1200

-

500

1000

-

300

800

-

V mV

Large Signal
Voltage Gain

0,:"":
:;;;:~
o=>

UU-

Output

Voltage Swing

J:

TevOS

Offset Dnft

Input BIas Current

c(

RL 2: 2kO

VOM

±11.5

-

±13.S

±13.2

±11.0

-

±13.D

±10.5

-

V

c.:-'

:;;;:0

«a:
c..~

00

Electrical Chalracteristics for Vs = ±15 V. -25 0 e :::; T A:::; 85 0 e. ooe :::; T A:::; + 70 0 e.

u

unless otherwise noted.
PARAMETER

Input Offset Voltage
Average Input

CONDITIONS

SYMBOL
Vas

MIN

HA-OP37E
TYP
MAX

-

20

50

J

MIN

HA-OP37F
TYP
MAX

MIN

HA-OP37G
TYP
MAX

-

40

140

-

55

UNITS

220

pV

TeVOS

Offset Drift

TCVOSN

-

0.2

0.6

-

0.3

1.3

-

0.4

1.8

pV/oe

Input Offset Current

lOS

-

10

50

-

14

85

-

20

135

nA

IB

-

±14

±60

-

~18

±95

-

±25

±150

nA

Input Voltage Range

IVR

±10.5

±11.B

-

±10.S

:::t:l1.8

-

:r:1O.5

±11.B

-

V

Common Mode
Rejection Ratio

CMRR

VCM",±1DV

110

124

-

102

121

-

96

118

-

dB

Power Supply
Rejection Ratio

PSSR

Vs = ±4.5 V to :1:18V

-

2

15

-

2

16

-

2

32

pVIV

Large Signal
Voltage Gain

Ava

RL 2:: 2kn, Vo = ::t:l0 V

750

1500

-

700

1300

-

450

1000

-

V/mV

Output
Voltage SWing

VOM

±11.7

:1:13.6

-

±11.4

±13.5

-

±11.D

±13.3

-

V

Input Bias Current

(Note 2)

RL",2kCl

NOTES.
1. Input Offset Voltage measurements are performed by automated test
equipment approximately 0.5 seconds after application of power.

2. The TevOS performance is within the specifications unnulled or when
nulled Rp ; 8kO to 20kO.

Test Circuits
LARGE AND SMALL SIGNAL RESPONSE
TEST CIRCUIT
LARGE SIGNAL RESPONSE

SMALL SIGNAL RESPONSE

IN - - - "....

>-t--t--o OUT

(IN ~ 20mV!OIV; OUT ~ 100mV/OIV;
TIME ~ 100ns/OlV)

(IN ~ lV/OIV; OUT ~ 5V/OIV; TIME ~ lns/OIV)
50pF

IN
IN

OUT
OUT

2-27

HA-OP37

Test Circuits (continued)
SUGGESTED OFFSET VOLTAGE ADJUSTMENT

V+

*

Offset adjustment range is approximately ±4mV

SUGGESTED STABILITY CIRCUITS

Low resistances are preferred for low noise applications as a 1KO resistor
has 4nv"fHzof thermal noise. Total resistances of greather than 10KQ on
either input can reduce stability. In most high resistance applications, a
few picofarads of capacitance across the feedback resistor will improve

stability.

GAIN, PHASE SHIFT VERSUS FREQUENCY

. . . ~=:::
40dB

1000

r':: 1"0~~

PHASE

~

~ ....

"

;20dB

il

GAIN

OdB

=tq
I

.......

1200

1\

1400

,

1600

N~

1800

2000

I I I I II II

10
(MHz)

2-28

100

HA-OP37

r--

M

Typical

0..

o

Perfor~ance

I



NOTE: ALL CAPACITOR VALUES ARE FOR
NON-POLARIZED CAPACITORS ONLY

c:..:>LJ..

0..-....1

::;:0

«a::

o..~

00

c:..:>

LOW FREQUENCY NOISE

VOLTAGE NOISE VERSUS FREQUENCY
10

9

~

5

r- TA = 25 C
r- VS=±15V
0

r\.

,i'

>

-=w 4 I' \. "
'"(5
2:

~,

""'-

w

'",....
C(

-

l/f CORNER = 2.7Hz

-'

o
>

1
1

10

100
FREQUENCY (Hz)

2-29

1000

m~RIS

HA·2400/04/05
PRAM Four Channel
Programmable Amplifier

FEATURES
•

DESCRIPTION
HA-2400/240412405 comprise a series of four-channel
programmable amplifiers providing a level of versatility unsurpassed by any other monolithic operational amplifier. Versatility is achieved by employing four input amplifier channels,
anyone (or none) of which may be electronically selected and
connected to a single output stage through DTLiTTL compatible
address inputs. The device formed by the output and the
selected pair of inputs is an op amp which delivers excellent
slew rate, gain bandwidth and power bandwidth performance.
Other advantageous features for these dielectrically isolated
amplifiers include high voltage gain and input impedance coupled with low input offset voltage and offset current. External
compensation is not required on this device at closed loop
gains greater than 10.
Each channel of the HA-2400/2404/2405 can be controlled and operated with suitable feedback networks in any of
the standard op amp configurations. This speCialization makes
these amplifiers excellent components for multiplexing, signal
selection, and mathematical function designs. With 10V / /l s
slew rate, 40MHz gain bandwidth, and 30M ohms input impedance these devices are ideal building blocks for signal generators,
active filters, and data acquisition designs. Programmability
coupled with 2mV typical, offset voltage and 5nA offset current
makes these amplifiers outstanding components for signal
conditioning circuits.
HA-2400/2404/2405 are available in a 16 pin dual-in-line
package. HA-2400 is specified from -55 0 C to +125 0 C. HA2404 is specified over the -25 0 C to +85 0 C range, while HA2405 operates from DoC to +75 0 C.

PROG RAMMABI LlTY
30V//ls

•

HIGH SLEW RATE

•

WIDEGAINBANDWIDTH

•

HIGH GAIN

•

LOW OFFSET CURRENT

40MHz
150,000
5nA
30M 11

•

HIGH INPUT IMPEDANCE

•

SINGLE CAPACITOR COMPENSATION

•

DTL/TTL COMPATIBLE INPUTS

APPLICATIONS
•

THOUSANDS OF NEW APPLICATIONS; PROGRAM
-

SIGNAL SELECTION/MULTIPLEXING
OPAMP GAIN
OSCILLATOR FREQUENCY
FI LTER CHARACTERISTICS

-

ADD-SUBTRACT FUNCTIONS
INTEG RATO R CHARACTE RISTI CS
COMPARATOR LEVELS

SCHEMATIC

PINOUT

Condensed circuit diagram for a programmable amplifier

TOP VIEWS

(PRAM HA-2400)

TRUTH TABLE
SELECTED

01

DO

EN

L

L

H

H

H

H

x

X

L

CHANNEL

Diagram includes: DNE INPUT STAGE, DECODE CONTROL,
BIAS NETWDRK AND OUTPUT STAGE
NONE

2-30

SPECIFICA TIONS

-It)

o

ABSOLUTE MAXIMUM RATINGS
Internal Power Dissipation (Note 13)
300mW
Operating Temperature Range
-55 0 C ~ TA ~ +125 0 C (HA-2400)
-25 0 C ~ TA ~ +85 0 C (HA-2404)
OOC ~ TA ~ +75 0 C (HA-2405)
Storage Temperature Range
-65 0 C ~ TA ~ +150 0 C

45.0V
Voltage Between V+ and V- Terminals
Differential Input Voltage
±. VSuppl y
-0.76V to +10.0V
Digital Input Voltage
Short Circuit Protected
Output Current
(Jsc~±33mA)

ELECTRICAL CHARACTERISTICS

Test Conditions: VSuppl y =± 15.0V Unless Otherwise Specified.
Digital Inputs: VIL =+O.5V, VIH =+2.4V. Limits apply to each of
the four channels, when addressed.

PARAMETER
INPUT CHARACTERISTICS

TEMP.

HA·2400/HA·2404
LIMITS
MIN.
TYP.
MAX.

MIN.

HA·2405
LIMITS
TYP.

MAX.

UNITS

o::t

o
o
o

o::t

N

I



u

40

0

5
0

E

1\

1-0

,R

1.1

"0

t:

H--

a::

i'--- ~Sr:RRENT

-551-50 -25

~
"0

.~

:--....

--- ~

0

+25

+50

+75

1.0

'":::>

r-

I

+100

1-

"-

~

K

.~

SLEiNRATE

0.9

§

'"

r-- - c

0

Z

0.8
-55)-50 -25

+125

lemperature (DC)

0

+25

""

+50

~

"'"

+75

+100

Temperature (DC)

+125

OPEN LOOP FREQUENCY AND PHASE RESPONSE

CD
~

c:

';ij

POWER SUPPLY CURRENT DRAIN
AS A FUNCTION OF TEMPERATURE

r.!:l

.~

~

'"
>

40

c.

20

f.--:::: ~'

'"

- - - CCOMP

-20
10

~

c:

';ij

+50

+75

+100 +125

c.

20
-20
10

~

-;;;

o. 9

VsLEWAATE

Y

~

r

~ANDW!DTH/

§
o

Z

8
+

+ 15

1M

\r-

10M

100

lK

10K

lOOK

1M

10M

Frequency (Hz)
OPEN LOOP VOLTAGE GAiN
VS. TEMPERATURE

1.1

~

lOOK

-'

"0

,.-~

10 K

II~III

-

40

0
0

1.2

1.0

"'"lK

I-

VI'.

60

NORMALIZED A.C. PARAMETERS
VS. SUPPLY VOLTAGE

'":::>

,

100
80

:iic.

~

-

~~ml
,

'.

120

0

c::

r-.

FREQUENCY RESPONSE VS. CCOMP

'"C>
'"
"0
>

Temperature (DC)

.s

15pf

+

Supply Voltage

2-:32

~

30

r-.

-

II

1I1111I

Frequency (Hz)

r.!:l

I
+25

""100

=

0

CD

0

~:

c'~lgSSTALKI ~EI~ECTION.I~r~ ~ +1

-CCOMP=OIlF

-'

c:
c.

'.

"

60

"0
0
0

;:::::--

-55!-50 :--25

r... ..

C>

~

e-- VSUPPLY'
±150V~
VSUPPLY = :.10.0V

..

80

'"

-TT-

YSUPPL Y , ,200V

no
100

'"'"

C>

60
90
120
150
180
210

100M

'"

Cl

'"c:
en
«
'"
.c
'"
"~

Lt)

10

2a

~

-

c..

I"

a

::I:
1/

::>

~

c.

1.0

~

:':::"~;' AN~E

-

>

N

..,

1 ~OK:~L

~

'0

."~'"

-

a

CCOMP = OpF
........ CCOMP - 15pF

c..

.s

o::r
o
o
o
o::r

EQUIVALENT INPUT NOISE VS. BANDWIDTH

OUTPUT VOLTAGE SWING VS. FREQUENCY

""gj

o
.......

"1

~

::>

fr
::>

o

O. 1
10K

.1
lOOK

10M

1M

100Hl

1kHz

Frequency (Hz)

10kHz

100kHz

lMHz

Upper 3dB Frequency
Lower 3dB Frequency' 10 Hz
Broadband Noise Characteristics

~ti

:;;z
0::>
u"Q..'-I
:;;0
---n---'~-

uLL.
c.: -'
:2 0

etC<:

c..!z

00

u

HA-2406

Characteristic Curves

V+ = 15VDC. V- = -15VDC. T A = 25 0 C unless otherwise stated.
NORMALIZED A. C. PARAMETERS
VS. TEMPERATURE

INPUT BIAS CURRENT AND OFFSET CURRENT
AS A FUNCTION OF TEMPERATURE
60

......

I-IBllslcJR~E~TI

-

40

«

-

0

""+
E

o

25

Iffiffit
50

OPEN LOOP FREQUENCY AND PHASE
RESPONSE

cc
~

120

c::

..

100

"ft:j

~

80

J3

60

>

'0

40

g-

20

....J

0

o

a;

c.

1"-"1"-"

o

VSUPPl Y = ± 20.0V
1"-" 'VSUPPl
Y = ±15.0V

"

75

50

25

Temperature (Oe)

75

-

4.0

0.9

Z

4.50

CI)

~

'"
E
0

t!)

-

~

0;

POWER SUPPLY CURRENT DRAIN AS A
FUNCTION OF TEMPERATURE

::>

<"..~
-SO"'' '<"

1:

Temperature (Oe)

~

",<'\

'"::>

>

o

::>

~

0;

-

u
>'i:i
c.

"

1.0

0::

10

u

4.25

ro."-s-

""
~
't:;

c::

«
,g

~~~o~j

N

.s
~::>

III

u

VSUPPl Y = ±10.0V

-20
10

c::

'.

..

CR'OSSTALK1RE'JECTION,'A~ =+1 11111

'.

,,- -

'.

......

".

r-....

'-::;.

-

V

p....
I

-CCOMP"'OpF
- - - CCOMP"" 15pF

111111
100

IIIIIII
-U11~1
I

-

111I'i~

1111111

lK

10K

['('

lOOK

1M

10M

~

30
60

120

~

«

180

210
100M

FREQUENCY RESPONSE VS. CCOMP
100

'"

80

t!)

en

o

25

50
Temperature (Oe)

J3

60

>

40

0
0

20

'0

75

c.

...J

c::

NORMALIZED A. C. PARAMETERS VS.
SUPPLY VOLTAGE

'"c.

0

-20
10

1M

Frequency (Hz)

1.2

>
o

.n
+i

E

OPEN LOOP VOLTAGE GAIN VS.
TEMPERATURE
1.1

VSUPPLY =± 20.0~"

~

'"
0::

't:;

1.0

......-

"

0;

>

"".~

---

V

BANDWIDTH 1

VSUPPLY =±15.0~.,,~
VSUPPL v = ± 10.0V r-..,

--

105

....

VsLEWRATE /

I---

0.9

0;

E
o
Z

1---1---

r'"

V

V

0.8

±10

±15

±20

100

Supply Voltage

o

25

50

Temperature (Oel

2-36

10M

~
'"

150

120

'm

~

Cl

90

Frequency (Hz)

cc

~

1- ..

100M

:7l

1¥

0..

HA-2406
Characteristic Curves lContiniJlld)
.OUTPUT VOLTAGE aWING,VS. FREQUENCY

EQUIVALENT INPUT NOISE VS. BANDWIDTH
100

-'"

~

CCOMP - OpF
/CCOMp· 15pF

Ii!

20

-'"

10

~

~1 o '= ~OK'
:
~O:;Ol
·0

:l
c;

...

...

>

...

~

'"

-=,
CI.

c

~

.:::':~TT:.NCE

z

1.0

,..-:::::1-""'

~

k:

'"
a-

c'"

.1

O. 1
10K

lOOK

±~~:J
INPUT
ov

__

L

SLEW RATE AND SETTLING

'.

~.~
lNPU~
-6.OV

I

I
I ERROR BAND

__ ~ _ :~Il~:~ ~:~~E

I

.

SLEW RATE AND TRANSIENT RESPONSE

L

~

-------.,.. ...............
...---

OVERSHOOT

lMHz

Upper 3dB Frequency.
lower3dB Frequency ·10Hz
Broadband Noise Characteristics

Frequency (Hz) ,

TRANSIENT RESPONSE

100kHz

10kHz

1kHz

100Hl

10M

1M

L."T~~~~~

I!

I

l.V/dT.

i

!

AV= 1

SELECTED
CHANNEl

~I

COMP

1---I---4-0.".OV
>+--4---<1,",""00

:p-!.l

OUT

SETTLING TrME

---l
I

Measured on both positiVII and
.

,DOD

negBt~trllnsitions.

Typica' Applications
AMPLIFIER, NON-INVERTING
PROGRAMMABLE GAIN

SAMPLE AND HOLD

....

11-----'+'---<> ~15V

>--iI'~-..,..--'O OUTPUT

>--D---.,---o

·ISV,

Sample charging rati;'
Hold drift rate =

=.!.!
Vlsec,
·C

2 Vlsec.
e

Switch pedestal error = 9. Volts

e

OUTPuT

1, -fSOxl0-6A
12 - 200 x 10-9 A at +2So e
- 600 x 10-9 A at -ssoe
-100 x 10-9 A at +12So e
Q - 2 x 10-12 eou!.

For more examples, see Harris Application Note 514.-

2-3.7

m~RIS

HA·2500/02/05
Precision High Slew Rate
Operational Amplifiers

FEATURES

DESCRIPTION
30V/JJ.S

• HIGH SLEW RATE

HA-2500/2502/2505 comprise a series of monolithic operational amplifiers whose designs are optimized to deliver excellent
slew rate, bandwidth, and settling time specifications. The
outstanding dynamic features of this internally compensated
device are complemented with low offset voltage and offset
current.

330ns

• FAST SETTLING
• WIDE POWER BANDWIDTH

500kHz

• HIGH GAIN BANDWIDTH

12MHz

• HIGH INPUT IMPEDANCE

50Ml1
10nA

• LOW OFFSET CURRENT

These dielectrically isolated amplifiers are ideally suited for
applications such as data acquisition, R.F., video, and pulse
conditioning circuits. Slew rate of ±25V / JJ. sand 330ns (0.1%)
settling time make these devices excellent components in fast,
accurate data acquisition and pulse amplification designs. 12
MHz bandwidth and 500kHz power bandwidth make these
devices well suited to R.F. and video applications. With 2mV
typical offset voltage plus offset trim capability and 10nA
offset current, HA-2500/2502/2505 are particularly useful
components in signal conditioning designs.

• INTERNALLY COMPENSATED

APPlICA TIONS
• DATA ACQUISTION SYSTEMS
• R.F.AMPLIFIERS

The gain and offset voltage figures of the HA-2500 series are
optimized by internal component value changes while the
similar design of the HA-2510 series is maximized for slew rate.

• VIDEO AMPLIFIERS
• SIGNAL GENERATORS

HA-2500/2502/2505 are available in metal can (TO-99) packages. HA-2500 and HA-2502 are specified over the, -55 0 C to
+125 0 C range.
HA-2505 is specified from OOC to +75 0 C.

• PULSE AMPLIFICATION

PINOUTS
TOP VIEWS
BALANCE

COMPENSATION

IN-

v+

IN+

OUT

v-

BALANCE

COMPENSATION

v·

2-38

SPECIFICA T/ONS
."
Q
.......

ABSOLUTE MAXIMUM RATINGS
Voltage Between V+ and V- Terminals
Differential Input Voltage
Peak Output Current
Internal Power Dissipation

Operating Temperature Range
HA-2S00/2S02
HA-2S05
Storage Temperature Range

40.0V
± IS.0V
SOmA
300mW

ELECTRICAL CHARACTERISTICS

INPUT CHARACTERISTICS
Offset Voltage

Q
.......

-SSoC ~ TA ~ +12S oC
OOC ~ TA ~+7S0C
-65 0C ~TA~ +150 0C

Q
Q

."
N

•

 10
4. Vo = ±.10.0V
5. CL = 50pF

Full

80

74

90

6. Vo = ± 200mV
7. Vo =:!: 200mV
B. See transient response test circu its and waveforms Page 2-31 .

9.

4

6

t::..v =±5.0V

90

6
74

10. This parameter value is based on
11.

design calculations.
Fu II power bandwidth guaranteed based

on slew rate measurement using:

FPBW = S. R./27TV pea k.
12. VOUT=±5V

2-39

n:G
O::::l

::;;0

...«""~
00

u

PERFORMANCE CURVES
V+ = 15VDC, V- = 15VDC, TA = 25°C UNLESS OTHERWISE STATED
100

INPUT BIAS AND OFFSET CURRENT
vs TEMPERATURE

-

0

I---- ~~CURRE~T

- ---

60

«c:

-

40

I

c:
~

EQUIVALENT INPUT NOISE
vs BANDWIDTH

:l

c.
c:>

---......

'\

20

t--

:l

U

c:

-4 0
-25

0

+25

.~Z
:l
CT

-2 0

+50

+15

Temperature °c

'"

I-::

I

UJ

+100

~.;

c."'0

-

r-----.

~OK S"UR(:,'~:STANCI

~ ~.~

~FSETCURRENT

0

-50

:;;:1.

k

01
100Hl

+12~

1kHz

10kHz

100kHz

1MHz

Upper 3dB Frequency
Lower 3dB Frequency - 10Hz

NORMALIZED AC PARAMETERS
vs TEMPERATURE
OPEN-LOOP FREQUENCY ANO PHASE RESPONSE

I

120

t---- t:--

0

/Xl
SLEW

lATE

r1k

BANDW!OTH

.,

c: '"
'"c.'"
""
o ~

~J,[

100

"C

g- .::
.3 t;

111111

'00

111111

0

.00

P~~E

I'

60

gOO
1

0

~

~

SOOii;

1

20

>

200

'"
a.

!I\

0

1SO"

I'

-20
10

lOOk

10k

1k

100

1M

100M

10M

Frequency Hz

.B
-50

-25

0

+25

+50

+15

Temperature °c

+100

+125

OPEN LOOP FREQUENCY RESPONSE FOR
VARIOUS VALUES OF CAPACITORS FROM
COMPENSATION PIN TO GROUND

NORMALIZED AC PARAMETERS
vs SUPPL Y VOLTAGE AT +25 0 C
I

120

II llillL
lllillL

BANDWIIDT\

D-

0

V-

I--

V
./

--

I---- V V

j---SLEWAA!e

/Xl

./

100

g- ~

80

o '"
...Je,,)

•0

;; 8,

Op'

'Op'

t-I::""
!'

40

c.'"

o

,I

-E

>

2il

lOOp'

t!llIl

:t:Hl!!
ttm!

300pF

0

1111 ~I

-2o
10

l000pF i

1k

100

10k

lOOk

1M

t10M

100M

Frequency Hz
NOTE: External compensation components are not required for

B

±IO

±IS

stability, but may be added to reduce bandwidth if desired.

±20

Supply Voltage
OUTPUT VOLTAGE SWING
vs FREQUENCY AT +25 0 C

OPEN LOOP VOLTAGE GAIN
vsTEMPERATURE
VLpPLy.I±200V

0

.....--:: -;:.--

V /-

/"

~201

-

t:::VSUPPLt =

5

VS~PPLY Lsov
""

'" c:

±l~OV

II

a
"""

26

",.-

s:
ben

111111"h

V SUPPLY "':!:. 15V

0..

~t

~

20

5

11111111 I

vsu:~~~';11IOV

~o

0..>

a

\

6

BO

-50

-25

+25

+50

+15

.. 100

O'OK

+125

Temperature °c

lOOK

,

MEG

10MEG

Frequency Hz

2-40

PERFORMANCE CURVES (continued)

POWER SUPPLY CURRENT
vs TEMPERATURE

VOLTAGE FOLLOWER PULSE RESPONSE

5

-

/



3

- 50

-25

/

. . .
25

V

~ f-'"

50

75

+100

RL = 2Kn ,CL = 50pF
Upper Trace: Input
Lower Trace: Output

+125

Temperature °C

SLEW RATE ANO
SETTLING TIME

'5'~
INPUT

L

-5.0V

SLEW RATE AND
TRANSIENT RESPONSE

TRANSIENT RESPONSE

L

"\

"

Verticai = 5V/Div.
Horizontal = 200ns/Div.
TA= +25 0 C, Vs = ± 15.0V

SUGGESTED
VOS ADJUSTMENT
.v

OVERSHOOT

I

I

OUT

I

I
i--RISE TIME

SeTIlINGTIME

I NOTE:

~':~:::,:~.~~~siKI"""" Ind

2-41

m

HA·251 0/12/15

HARRIS

High Slew Rate
Operational Amplifiers
DESCRIPTION

FEATURES
60V//1s

• HIGH SLEW RATE

The HA-2510/2512/2515 are a series of high performance
operational amplifiers which set the standards for maximum
slew rate, highest accuracy and widest bandwidth for internally
compensated monolithic devices. In addition to excellent
dynamic characteristics, these dielectrically isolated amplifiers
also offer low offset current and high input impedance.

250ns

• FAST SETTLING
• WIDE POWER BANDWIDTH

1,000kHz

• HIGH GAIN BANDWIDTH.

12MHz

• HIGH INPUT IMPEDANCE

100MD

• LOW OFFSET CURRENT

The +60V/ /1 s slew rate and 250ns (0.1%) settling time of these
amplifiers is ideally suited for high speed D/A, A/D, and pulse
amplification designs. HA-2510/2512/2515's superior 12MHz
gain bandwidth and 1000kHz power bandwidth is extremely
useful in R. F. and video applications. For accurate signal
conditioning these amplifiers also provide 10nA offset current,
coupled with 100Mn
input impedance, and offset trim
capability.

10nA

• INTERNALLY COMPENSATED

APPLICATIONS

The HA-2510 and HA-2512 have guaranteed operation form
-55 0 C to +125 0 C and are available in metal can and ceramic
mini DIP packages. Both are offered as a military grade part
with the HA-2510 also available in LCC package. The HA-2515
has guaranteed operation from DoC to +75 0 C and is available
in plastic and ceramic mini DIP and metal can packages.

• DATA ACQUISITION SYSTEMS
• R.F. AMPLIFIERS
• VIDEO AMPLIFIERS
• SIGNAL GENERATORS
• PULSE AMPLIFICATION

PINOUTS

BALANCE
IN-

DB

SCHEMATIC
TOP VIEWS
COMPENSATION

2

7

Vt

INt

3

6

OUT

v-

4

5

BALANCE

COMPENSATION

v-

2-42

SPECIFICA T/ONS
It)
,....
.......
N
,....
.......
o
,....

ABSOLUTE MAXIMUM RATINGS
Voltage Between V+ and V- Terminals
Differential Input Voltage
Peak Output Current
Internal Power Dissipation

Operating Temperature Range
HA-2510/2512
HA-2515
Storage Temperature Range

40.0V

± 15.0V
50mA
300mW

It)

N

~

:I:

ELECTRICAL CHARACTERISTICS

V+=+15V D. C., V- = -15V D. C.
HA-2510
-55 DC to +125 0C

PARAMETER

-55 0 C ~ TA~ +125 0 C
OOC ~ TA ~ +75 0 C
-65 0 C ~ TA ~ +150 0 C

TEMP.

HA-2512
-55 0C to +1250C

HA-2515
DoC to 750C

TYP

MAX

+25 0 C
Full

4

8
11

Full

20

Bias Current

+25 0 C
Full

100

200
400

125

250
500

125

Offset Current

+25 0 C
Full

10

25
50

20

50
100

20

Input Resistance (Note 10)

+25 0 C

50

Full

± 10.0

+25 0 C
Full

10K
7.5K

15K

7.5K
5K

15K

7.5K
5K

15K

V!V
V!V

Full

80

90

74

90

74

90

dB

12

MHz

MIN

MIN

TYP

MAX

5

10
14

MIN

TYP

MAX

UNITS

5

10
14

mV
mV

INPUT CHARACTERISTICS
Offset Voltage
Offset Voltage Average Drift

Common Mode Range

25

100

40

40

± 10.0

Common Mode Rejection Ratio
(Note 2)
Gain Bandwidth Product (Note 3)

+25 0 C·

250
500

nA
nA

00

50
100

nA
nA

100

Mn
V

± 10.0

12

12

OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 1)

Full

± 10.0 .± 12.0

± 10.0 ± 12.0

± 10.0 :':. 12.0

V

Output Currer.t (Note 4)

+25 0 C

±10

±20

± 10

:':.20

±10

:':.20

mA

Full Power Bandwidth
(Note 4,11)

+25 0 C

750

1000

600

1000

600

1000

kHz

TRANSIENT RESPONSE
Rise Time (Notes 1,5,6 & 8)

+25 0 C

25

50

25

40

Overshoot (Notes 1,5,7 & 8)

+25 0 C

Slew Rate (Notes 1,5,8 & 12)

+25 0 C

Settling Time (Notes 1,5,8 & 12)

+25 0 C

0.25

+25 0 C

4

± 50

±40

±65

25

50

25

50
±40

±60
0.25

25

50

25

50

ns
%

:':.60

V//lS

0.25

j.1S

POWER SUPPLY CHARACTERISTICS
Supply Current
Power Supply Rejection Ratio
NOTES: 1.
2.
3.
4.
S.

RL"2kl!
VCM"±10V
AV>10
VO" ± 10.0V
CL" SOpF

Full

80

74

90

6. VO" ± 200mV
7. Vo"±200mV
8. See transient response test circuits and waveforms Page 2-35.

9.

4

6

AV" ±S.OV

2-43

90

4

6
74

UU-

c.:...J

:;0

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain
(Note 1,4)

:;~
o=>

/lV/OC

30

100

o.:~

6

90

10. This parameter value is based on
design calculations.
11. Full power bandwidth guaranteed based
on slew rate measurement using:
FPBW "S. R./27TV pea k.
12. VOUT" :':.SV

mA
dB

10
4. VO=±.10.0V

I

V = ±'5.0V
9. This parameter value is based
upon design calculations.

2-47

74

± 120

V/p.s

0.20

p.s

4

mA

90

dB

10. Full power bandwidth guaranteed
based upon slew rate measurement

FPBW = S. R.l27TV pea k.
11. VOUT =±'5V
12. Guaranteed by design.

0=
u"

c.::;:c

o~
<-

PERFORMANCE CURVES
V+ = 15V D. C., i A = 250C unless otherwise stated.
INPUT BIAS AND OFFSET CURRENT
vsTEMPERATURE

."

EQUIVALENT INPUT NOISE
vs BANDWIDTH

0

.,
oCt
c::

I

VSJpPLY'.t'15V

I'.

>100

"t-.....

0

"leURA'!. _ r-r"-.

.,0

~

~OK

:::'' _TANC

c::
~

:>

(.)

+4 0

.,

~

"-

0

t'-- ~

0

I

0

."

-55-flO

0

- 1"--

kt

(JfFSETCURRENT

'25

.5O

.,.

"00

0.1
100Hz

-125

Temperature °c

~
1kHz

NORMALIZED AC PARAMETERS
vs TEMPERATURE

OPEN-LOOP FREQUENCY AND PHASE RESPONSE

I IIIlr

0

"

co
c."'C

0

O."m

0

-'Cl
c:: do

0

o c::

..
0=

I Iill

11111

IJlllJ

c. ..

•

Jill
GAiN'"

10

o

>

,

PHASE

",

,

IIII
100

10

IK

10'

100'

,.

-551-50

(I

_25

+50

+15

.100

+125

Temperature °c

OPEN LOOP FREQUENCY RESPONSE FOR VARIOUS
VALUES OF CAPACITORS FROM BANDWIDTH CONTROL
PIN TO GROUND

NORMALIZED AC PARAMETERS
vsSUPPLY VOLTAGE AT+250C
co
c."'C

o c::

:K

BJowlOL

BAt.lDWIOTH

~R~~E

.3~

..

c:: ..
",

c. ..
0=
o

>

9

Frequency Hz

,

_zo

-IS

Supply Voltage

.

OPEN LOOP VOLTAGE GAIN
vs TEMPERATURE
88

,
,
co

"'C
I

c::

,

.

~8

...... '"c::

vsup!'

- "-""

............

VSUPiLY-~

......-'-

v5ulv:!,J,!/

t::--.,

V

...........

-55-SO

-"

0

."

'5O

.,

..

1-",

20

."->

V SUPPLY

1

..

..

0

•

Illl20V

I . ,.

V Upp

I

..

.... -

~

OUTPUT VOLTAGE SWING
vs FREQUENCY AT +25 0C

30

8:I '3:
en
0

b....

3

,

10.

Frequency Hz

I

0

,
,...

i"o..

IIII

0
-10

,

1M H,

110kHz

10kHz

Upper 3dB Frequency
Lower 3dB Frequency - 10Hz

I

V SUPPLY -± 10V

•
•

r-....

•,..

+125

Temperature °c

Iflllll
,oo.

'MEG

I~III

'OMEG

Frequency Hz

2-48

PERFORMANCE CURVES (continued)
POWER SUPPLY CURRENT
vsTEMPERATURE

VOLTAGE FOLLOWER PULSE RESPONSE

..
.6

«E

•..

~

.2
VSUI'fLV-.l:.20V_
VSUPPLV=!15V_

'r--VS~

.•

.•

1\

/

II

~

, ." ."

-"

-55!-50

b ~~

~
~v

+100

.)5

+125

RL =2KS"l,CL =SOpF
Upper Trace: Input; 1.67V/Div,
Lower Trace: Output; SV/Div.

Temperature DC

"

Horizontal = IOOnsiDiv.
TA=+2S0C, VS=±ISV

POWER SUPPLY REJECTION RATIO
VS. FREQUENCY
~ IOOf--t+ttttttt--+lH-t1IHtt--+++f++IIf-I-+H++HI-+-I-+H+HI

~
~ ~f--I-+H++ttt-+-I~~~-+~f++IIf-~~HI-+-I-+H+HI
~ f-1-+1-l+lttt-+-I+!l+Hl'~.w NEGAnVESUPPLy".jj.-4-++!.(jjjj

~ "f-~H#ffi-+-I~P~OS~ITI~VE~SU£~~Ly~~~~H+Hffi-444+Hffi

i ,,~ttttI=WUl~Ufj$t!l:~.
~ 2of-~H#ffi-+-I~~-+~~~~~~+-I+H~
l~Ot"kH'--'LLWl,lll
kH,--,..l...J.l.lJll"lL
kH -,.LLJJlJ,llJ,..LH,~LllLll,lll.H-'..L.J.l.lJllJJ
fREQUENCV-Hl

SLEW RATE AND
SETTLING TIME

"]

L

INPUT
-1.67V

I

",mJ

INPUT

ov

t

OVERSHO~

.v

L

IN

______ _

: IN : ERROR BAND
I
~±lOmV FROM
-'SLEW I FINAL VALUE

OUTPUT

J

I

~-.1T~

SUGGESTED
VOS ADJUSTMENT

SLEW RATE AND
TRANSIENT RESPONSE

TRANSIENT
RESPONSE

667.12

OUT

RATE:

I.
= !JVIIlT
SETTLING TIME

-I
I

TYPICAL APPlICA TlONS
10K

COMPENSATION CIRCUIT FOR INVERTING UNITY GAIN

10K

~~~--oOUT

2K

500PFT

2-49

Slew Rate

l':::

120V/Ils

Bandwidth

l':::

10M Hz

Settling Time

l':::

500ns

;II

HA·2539

HA.R.RIS

Very High Slew Rate Wideband
Operational Amplifiers

Description

Features
•

The Harris HA-2539 represents the ultimate in high slew rate
wideband, monolithic, operational amplifiers. It has been designed and constructed with the Harris high frequency Bipolar
dielectric isolation process and features dYl1'llmic parameters
never before available from a truly differential device.

600V/ps

VERY HIGH SLEW RATE

•

OPEN LOOP GAIN

15kV!V

•

WIOE GAIN-BANDWIDTH

600MHz

•

POWER BANDWIDTH

9.5MHz

•

LOW'OFFSETVOLTAGE

•

INPUT VOLTAGE NOISE

•

OUTPUTVOLTAGESWING

3mV

With a 600V/ ps slew rate and a 600MHz gain-band-width-product, the HA-2539 is ideally suited for use in video and RF amplifier designs, in closed loop gains of 10 or greater. Full ±10V
swing coupled with outstanding A.C. parameters and complemented by high open loop gain makes the devices useful in high
speed data acquisition systems.

6nV/~
'±'10V

Applications
•

PULSE AND VIDEO AMPLIFIERS

•

WIDEEMND AMPLIFIERS

•

HIGH SPEED SAMPLE-HOLD CIRCUITS

•

RF OSCILLATORS

Pinouts

The HA-2539 is available in the 14 pin ceramic and epoxy
packages, as well as a 20 pin LCC package. The HA-2539-2
denotes -55 0 C to +125 0 C operation while the HA-2539-5
operates over the OOC to +75 0 C range.

Schematic
TOP VIEWS
-INPUT
N.C.

N.C.

N.C.

N.C.

N.C.

N.C.
N.C.

N.C.
OUTPUT

OUTPUT

2-50

HA-2539
Specifications
ABSOLUTE MAXIMUM RATINGS

(Note 1)

Voltage between V+ and V- Terminals
Differential Input Voltage
Output Current
Internal Power Dissipation (Note 2)
Operating Temperature Range: (HA-2539-2)
(HA-2539-5)
Storage Temperature Range

ELECTRICAL CHARACTERISTICS

35V
6V
50mA (Peak)
870mW (Cerdip)
-55 0C-t---oOUT

gOOn
AV= 10
'CL $; 10pF

100£1

LARGE SIGNAL RESPONSE

SMALL SIGNAL RESPONSE

Vertical Scale: A=O.5V /Oiv., B=5.0V10iv.
Horizontal Scale: Time: 50ns/Oiv.

Vertical Scale: Input=10mV/Div.,Output=50mV/Oiv:
Horizontal Scale: 20n~/Oiv.

A

B

SETTLING TIME TEST CIRCUIT

•

200n"

INPUT

""""'' ' 01'-.....- - - 1

0-.....

SETTLE POINT (Summing Node) capacitance should be less
than 10pF. For optimum settling time results, it is recommended that the test circuit be constructed directly onto the
device pins. A Tektronix 568 Sampling Oscilloscope with S-3A
sampling heads is recommended as a settle point monitor.

500n**

-v
SETTLE
POINT

Load Capacitance should be less than 10pF.
It is recommended that resistors be carbon composition and
that feedback and summing network ratios be matched.

2Kn··

2-52

HA-2539

Applications
FREQUENCY COMPENSATION
COMPENSATION BY OVERDAMPING

STABILIZATION USING ZIN
R2

Rl

SET: AV=- -=-3

SET AV=l+iG =5

-=

Rl

REDUCING DC ERRORS
COMPOSITE AMPLIFIER

INPUT

1-=
OUTPUT

-=
-=
DIFFERENTIAL GAIN ERROR (3%)
HA-2539 20dB VIDEO GAIN BLOCK

2-53

HA-2539
Performance Curves
INPUT OFFSET VOLTAGE AND BIAS CURRENT
VS TEMPERATURE
4

INPUT NOISE VOLTAGE AND
NOISE CURRENT VS FREQUENCY

III, ",L ),1,ll!1

7

5

1

E

,

-

B

f-.

6

~

OFFSET VOLTAGE

BIAS CUR RENT

5

~

4

;0
~

5

~\

>

0

o

~

4O~

\1\

,

~

3

*

~'

3

0

1

5

0

.40

·40

TEMPERATURE"

.EO

+120

10

+160

o~

~

~g~TEArl'

1

1

z

o~

5

~

4

0
-EO

LI±UJI

II

1

"""'"

1IIIIIiI

o
lOOK

10K

lK

100

CURRENT NOISE

ac

BROADBAND NOISE (O.1Hz to 1mHz)
Vertical Scale: 10MV/Div.
Horizontal Scale: 50ms/Div.

COMMON MODE REJECTION RATIO
VS FREQUENCY

10 0

0

0

r-..

0

......... r-.

0

1M

lOOK

10K

lK

10M

FREQUENCY

OPEN LOOP GAIN/PHASE
VS. FREQUENCY HA-2539

POWER SUPPLY REJECTION RATIO
VSFREQUENCY
100

80
100

r-

"-

0

"-

PHASE

0

Ii

0'

l~IN
r-..

0

0
0

:::::: ::
0

0
-1 0

0
lK

100

10K

lOOK
FRE'OUENCV-Hl

1M

10M

2-54

90'

f'

01--

lK

10K

lOOK

1M

10M

"

100M

I

1

Performance Curves (Continued)
OUTPUT VOLTAGE SWING
VS.FREQUENCY

CLOSED LOOP FREQUENCY RESPONSE
FOR VARIOUS CLOSED LOOP GAINS
8

vsu~p!y ~WJI

v+= 15V

100
0

4

0

•
•

0
0
0

:=.

0

VSUPPl Y = ±IDV

2

0

~

0

VSUPPL Y " !5V

0
-I 0

I.

10.

10K

lOOK

1M

....... ~

I I

4

100M

I.M

,

~

8

FREQUENCY-Hz

I"""
1111

0

I.

10K

lOOK
1M
FREnUENCYIHz

10M

100M

NORMALIZED AC PARAMETERS
VS. TEMPERATURE

OUTPUT VOLTAGE SWING
VS. LOAD RESISTANCE
4

3
8

.2
BANDWIDTH

4

/V--

0

•
2

/
o
o

/

.1

/'

/

.0

-

~ ........

~
~~"ATE

.9
.8
.7

..
2.0

400

I•

800

• 00

-110

1.2K

....

40

80

TEMPERATURE-DC

"
".

I~

RESISTANCE - Ohms

SETTLING TIME FOR VARIOUS
OUTPUT STEP VOLTAGES

POWER SUPPLY CURRENT VS.
TEMPERATURE AND SUPPLY VO'L TAGE

28.~----~----

10
10mV

•

, / 1mV

.,- . /

4

2

•

"-,'mY

10mV

"\.

8
0

"
40

8.

120.

241----f---+---+----I----I----+-l

/
/

2
4

__~____~______~____~____~~

V

/

8

160

"
200

~1~80~--...
JO~--~---~~.~--+~8~0----+1~20~--+~,~"J

240

TEMPERATURE-DC

2-55

m~RIS

HA-2540
Wideband, Fast Settling
Operational Amplifiers
GENERAL DESCRIPTION

FEATURES
• VERY HIGH SLEW RATE

400V/J./s

• WIDE GAIN-BANDWIDTH

400MHz
6MHz

• POWER BANDWIDTH
•

LOW OFFSET VOLTAGE

•

INPUT VOLTAGE NOISE

• OUTPUT VOLTAGE SWING
•

The Harris HA-2540 is a wideband, very high slew rate, monolithic operational amplifier featuring superior speed and bandwidth characteristics. Bipolar construction coupled with dielectric isolation allows this truly differential device to deliver outstanding performance in circuits where closed loop gain is 10
or greater. Additionally, the HA-2540 has a drive capability of
±10V into a 1K ohm load. Other desirable characteristics include low input voltage noise, low offset Voltage, and fast
settling time.

200ns

• FAST SETTLING TIME

8mV
6nV/

/Hz
±10V

A 400V/ J..Is slew rate ensures high performance in video and
pulse amplification circuits, while the 400MHz gain-bandwidth-product is ideally suited for wideband signal amplification. A settling time of 200ns also makes the HA-2540 an excellent selection for high speed Data Acquisition Systems.

MONOLITHIC BIPOLAR CONSTRUCTION

APPlICA TIONS
•

PULSE AND VIDEO AMPLIFIERS

•

WIDEBAND AMPLIFIERS

The HA-2540-2 is specified over the -55 0 C to +125 0 C range
while the HA-2540-5 is specified from OOC to +75 0 C.

.. HIGH SPEED SAMPLE-HOLD CIRCUITS
•

The HA·2540 is available in the 14 pin ceramic and epoxy
packages, as well as a 20 pin LCC package.

FAST, PRECISE D/A CONVERTERS

SCHEMATIC

PINOUT
TOP VIEWS

ININ+

v-

2-56

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS (Note

1)

Voltage between V+ and V- Terminals
Differential Input Voltage
Output Current
Internal Power Dissipation (Note 2)
Operating Temperature Range: (HA-2540.2)

35V
6V
50mA (Peak)
870mW (Cerdip)
-55 0 C< TA <+125 0C
00Cr---oOUT

900n
AV= 10

lOOn

'CL~10pF

SMALL SIGNAL RESPONSE

LARGE SIGNAL RESPONSE
Vertical Scale: (Volts: A=0.5v/Oiv., B=5.0V/Oiv.)
Horizontal Scale: (Time: 50ns/Oiv.)

Vertical Scale: Input=10mV/Oiv.; Output=50mV/Oiv.
Horizontal Scale: 20ns/Oiv.

A

B

SETTLING TIME TEST CIRCUIT

* Load Capacitance should be less than 10pF.

200Sl **

INPUT o--t~NV'-"""---I

It is recommended that resistors be carbon composition and
that feedback and summing network ratios be matched.

SETTLE POINT (Summing Node) capacitance should be less
For optimum settling time results, it is recommended that the test circuit be constructed directly onto the

than 1 OpF.

500n--*

device pins. A Tektronix 568 Sampling Oscilloscope with S-3A
sampling heads

-v
SETTLE
POINT

5Kn"

2-58

is recommended as a settle point monitor.

PERFORMANCE CURVES (Continued)
OUTPUT VOLTAGE SWING VS. FREQUENCY

CLOSED LOOP FREQUENCY RESPONSE
28

av

VSUPPl y =:!:\
100

24

90

80

~

70

'll

,

40

0
0

30

VSUPPLy=±.10V

~ 16

~

1\

,

10

0

20

,

50

"~
0

f".

60

10

I IIIII

-10

lK

100

10K

lOOK

1M

10M

~

VSUPPLy:!:5V

100M

o

FRED.UENCY - Hz

10K

lK

II

~
c..:t3

:;:Z
10M

lOOK
1M
FREnUENCY - Hz

100M

0:::>

U

LL

0...--'

:;:0

<{o::

o...~

00

u

NORMALIZED AC PARAMETERS
VS. TEMPERATURE

OUTPUT VOLTAGE SWING VS. LOAD RESISTANCE

4

3
8
2
4

L

0

.1~~IOTH

o

/V

6

I

2

..

SLEW~

9
8

8

/

J

7

,

0

400

100

lK

600
800
RESISTANCE - OHMS

-80

1,2K

SETTLING TIME FOR VARIOUS
OUTPUT STEP VOLTAGES

/lmV

2
2

VSUPPly=±15V
0

'\.

8

"

10mV " -

80

120

2

lmV

"-

-1 0

40

VSUPPl Y = ±5V/

6

'\.

,

160

4

r
I

I

120

8

/

/

6
4

40
90
TEMPERATURE - DC

POWER SUPPLY CURRENT
VS. TEMPERATURE AND SUPPLY VOLTAGE

L

0
8

-40

"-

160

8

200

0
-80

240

-40

... 0
TEMPERATURE-oC

SETTLING TIME - ns

2-59

+80

+120

+160

PERFORMANCE CURVES

INPUT OFFSET VOLTAGE AND BIAS CURRENT
VS. TEMPERATURE

INPUT NOISE VOLTAGE AND NOISE CURRENT
VS. FREQUENCY

7

1

6

0

5

~

OFFSET VOLTAGE

....... i--

~

4

>

~

6

3

•

1 ~

1

1

0
-80

,40

-40

'80

"~

I
~

BIAS CURRENT

+120

1

4

\\

~

15

~

10

3

1

~~~TEAn
5

0
10

0

+160

5

'.\
~ 01\

>

E

8

U!!J 1

Ilt,"L!,I,l~!1

4

II

~

1

..:;;

CURRENT NOISE

II 1111
100

o
lOOK

10K

lK

TEMPERATURE = DC

BROADBAND NOISE (O.lHz TO 1MHz)
Vertical Scale: lOI.LV/Div.
Horizontal Scale: 50mo/DiY.

COMMON MODE REJECTION RATIO VS. FREQUENCY

V!15V RL=lK

110

100

80

-

60

l-

40

t-

r20

1K

10K

1001<

10M

1M

FREOUENCY - Hz

POWER SUPPLY REJECTION
RATIO VS. FREQUENCY

OPEN LOOP GAIN/PHASE
VS. FREQUENCY HA-2540

100

0'
100

0

0

0

0

0

45'

GAIN

90'

PHA~Ei

~SUPPlY

0

NEGATIVE SUPPl Y

1350

,

0

~

'.

.

0

0

-1 0

2250
100

0
lK

10K

lOOK

1M

10M

FREQUENCY - Hz

2-60

1800

1K

10K

lOOK

1M

FREOUENCY - Hz

10M

100M

APPLICATIONS
WIDEBAND SIGNAL SPLITTER

With one HA-2540 and two low capacitance switching diodes, signals exceeding 10MHz can -be separated. This circuit
is most useful for full wave rectification, AM detectors or sync generation.
2K

200

2K

BOOTSTRAPPING FOR MORE OUTPUT
CURRENT AND VOLTAGE SWING
~----~~------o+v

SIGNAL INo-,N""_~

L....--4-----O_v

2-61

mHA.RRIS
PRELIMINARY

HA·2541

Wideband, Fast Settling, Unity Gain Stable,
Operational Amplifier

Features

Applications

•

Unity Gain Bandwic;lth ......................................... 40MHz

•

•

High Slew Rate .................................................. 280Vlps

• Wideband Amplifiers

•

Fast Settling Time ....................................................90ns

• High Speed Sample-Hold Circuits

Pulse and Video Amplifiers

• Power Bandwidth ...................................................4MHz

• Fast, Precise D/A Converters

•

Output Voltage Swing ........................................... ±10V

•

•

Unity Gain Stability

•

Monolithic Bipolar Construction

High Speed AID Input Buffer

Description
The HA-2541 is the first unity gain stable monolithic
operational amplifier to achieve 40MHz unity gain
bandwidth. A major addition to the Harris series of high
speed, wideband op amps, the HA-2541 is designed for
video and pulse applications requiring stable amplifier
response at low closed loop gains.

monolithic operational amplifier. But features such as
280V Ips slew rate and 40MHz unity gain bandwidth
clearly show that this is not the case for the HA-2541.
These features, along with90nssettling time, make this
product an excellent choice for high speed data acquisition systems.

The uniqueness of the HA-2541 is that its slew rate and
bandwidth characteristics are specified at unity gain.
Historically, high slew rate, wide bandwidth and unity
gain stability have been incompatible features for a

Packaged in a TO-S metal can or 14 pin ceramic DIP,
the HA-2541 is pin compatible with the HA-2540 and
HA-5190 op amps. The HA-2541-2 is specified over the
temperature range of -550C to +125 0C.

Pinouts

Schematic
TOP VIEWS

14

13
BALANCE 3
IN- 4
IN+ 5

V- 6

12 BALANCE
11 V+
10 OUTPUT

9

2-62

BALANCE

Specifications HA -2541
Absolute Maximum Ratings (Note 1)

Operating Temperature Range:

Voltage Between V+ and V- ... "."." ........................ "",,. 35V
Differential Input Voltage ................................................ 6V
Output Curren!.. ................... ,',., ................ ,.... 50mA (Peak)
Internal Power Dissipation (Note 2) TO-8"."".""".1.5W
Dip"." """.,,'" 1.6W

HA-2541-2 """""""""""""""""".,,-550 C :s T A :s +125 0 C
HA-2541-5 """"""""."."."""".,,""""" OoC :s T A :s +75 0 C
Storage Temperature Range """,,-65 0 C:S TA:S +150 0 C
Maximum Junction Temperature """"""""""""".+175 0 C

Electrical Characteristics

VSUPPLY ~ ±15 Volts; RL ~ 2K Ohms, Unless Otherwise Specified
HA-2541-5

HA-2541-2
-55 0 C to +125 0 C
PARAMETER

TEMP

MIN

TYP

aoc to +75 0 C

MAX

MIN

TYP

MAX

UNITS

~~

::;;:2
o=>
uu..
Q..--'

::;;:0

«0:

INPUT CHARACTERISTICS
Offset Voltage (Note 11)'

+25 0 C
Full

Average Offset Voltage Drift
Bias Current
Offset Current
Input Resistance
Input Capacitance
Common Mode Range
Input Noise Voltage (f ~ 1kHz, Rg

~

00)

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 3)
Common-Mode Rejection Ratio (Note 5)
Unity Gain-Bandwidth (Note 6)

Full
+25 0 C
Full
+25 0 C
Full
+25 0 C
+25 0 C
Full
+25 0 C

2

2'

6

6'

20
6

35

1

50
7

20
6

35

1

50
7

9

9
100

100
1

1

±10

±10
10

+25 0 C
Full
Full
+25 0 C

10K
5K
70

Full
+25 0 C
+25 0 C

±10

+25 0 C
+25 0 C
+25 0 C

3

J1A
J1A
J1A
J1A
Kohms
pF
V

10

nV/JHZ

40

V/V
V/V
dB
MHz

10K
5K
70
40

mV
mV
J1V/oC

OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 4)
Output Current (Note 4)
Output Resistance
Full Power Bandwidth (Note 3 & 7)
Differential Gain
Differential Phase
Harmonic Distortion (Note 10)
TRANSIENT RESPONSE (Note 8)
Rise Time
Overshoot
Slew Rate
Settling Time:
10V Step to 0.1%

±11

±10

10

±11

V
mA
Ohms

10

0.2

2
4
0.1
0.2

+25 0 C

<0.01

<0.01

%

+25 0 C
+25 0 C
+25 0 C

4
40
280

4

ns

40
280

%
V/J1s

90

ns

200

2
4
0.1

+25 0 C

90

+25 0 C
Full

33

3

200

MHz
%
Degree

POWER REQUIREMENTS
Supply Current
Power Supply Rejection Ratio (Note 9)

Full

33
40

70

2-63

45
70

mA
mA
dB

Q..~

00
U

HA-2541
Notes:
6. Vo = 90mV
1. AbsolLite maximum ratings are limiting values, applied individually, beyond which the 'serviceability of the circuit ma{ 7. Full Power Bandwidth guaranteed based on slew
be impaired. Functional operability under any of these condiSlew Rate
.
tions is not necessarily implied.
rate measurement uSing FPBW = - - - 271VPEAK
2. TO-8: BjA = 1000 C/W, BjG = 15 0 C/W.
8. Refer to Test Circuits section of data sheet.
Recommended heat sink: Thermalloy 2240A liSA = 27 0 C/W
Cerdip: IijA = 91 0 C/W, IijG = 35 0 C/W
9. VSUPPLY = ±5VDC to ±15VDC
Recommended heat sink: AAVID #5802 liSA = 15 0 C/W
10. V1N = 1VRMS; f = 10KHz; Av = 10
3. VO = ±10V
11. Relaxed Offset Voltage "C" version
4. RL = lKH
available in 1986.
5. VGM = ±10V

Test Circuits
TEST CIRCUIT *

. LARGE SIGNAL RESPONSE

SMALL SIGNAL

RE~PONSE

OV

OV

OV

SETTLING TIME TEST CIRCUIT
r---------------

u":;:0

Q..• ...J

 175 0 C)'
'FOR THE GIVEN DIE SIZE AND THERMAL IMPEDANCE DATA, THESE CURVES
REPRESENT THE MAXIMUM ALLOWABLE POWER DISSIPATION BEFORE A
JUNCTION TEMPERATURE OF 1750 C IS EXCEEDED.

2-65

125

m~RIS

HA-2542

PRELIMINARY

Wideband, High Slew Rate, High Output
Current Operational Amplifiers
Applications

Features
•

Stable at Gains of 2 or Greater

•

Pulse and Video Amplifiers

•

Gain Bandwidth (AVCL

=2) ............................. 120MHz

•

Wideband Amplifiers

•

High Slew Rate ................................................... 30OV/.us

•

Coaxial Cable Drivers

•

High Output Current.. ..•....................................... 100mA

•

Fast Sample-Hold Circuits

•

Power Bandwidth ........•....................................... 5.5MHz

•

•

Output Voltage Swing .......•................................... ±10V

High Frequency Signal
Conditioning Circuits

•

Monolithic Bipolar Construction

Description
The HA-2542 is a wideband, high slew rate, monolithic
operational amplifier featuring an outstanding combination of speed, bandwidth, and output drive capability.
Utilizing the advantages of the Harris D. I. technology this
amplifier offers 350V/.us slew rate, 120MHz gain bandwidth, and ±100mA output current. Application of this
device is further enhanced through stable operation down
to closed loop gains of 2.
For additional flexibility, offset null and frequency compensation controls are included in the HA-2542 pinout.

The capabilities of the HA-2542 are ideally suited for high
speed coaxial cable driver circuits with gain. With 5.5MHz
full power bandwidth, this amplifier is most suitable for
high frequency signal conditioning circuits and pulsel
video amplifiers. Other applications utilizing the HA-2542
advantages include wideband amplifiers and fast samplehold circuits.
Packaged in a 12 pin (TO-B) can, the HA-2542 is pin compatible with the HA-2540, HA-2541, HA-5190, LH0032,
and HOS-050e.

Schematic

Pinout
TOP VIEWS
14
13 BALANCE
BALANCE 3
IN- 4
IN+ 5
V- 6

12 COMPENSATION
11 V+

10 OUTPUT

9

c

2-66

Specifications HA-2542
'II:t

II)

Absolute Maximum Ratings (Note 1)

I

HA-2542-2 ...................................-55 0 C :s T A :s +125 0 C
HA-2542-5 ........................................ OoC :s TA :s +75 0 C
Storage Temperature Range ..... -65 0 C :s TA :s +150 oC
Maximum Junction Temperature ...................... +175 0 C

Voltage between V+ and V- Terminals .................... 35V
Differential Input Voltage ........................................... 6V
Output Current.. ...................................... 125mA (Peak)
107mARMS (Continuous)
Internal Power Dissipation (Note 2) TO-8 ........... 1.5W
Dip ............ 1.6W

Electrical Characteristics

N

Operating Temperature Range:

VSUPPLY ; ±15 Volts; RL ; 1K ohms, unless otherwise specified.
HA-2542-2
-55 0 C to +1250 C

PARAMETER
INPUT CHARACTERISTICS
Offset Voltage
Average Offset Voltage Drift
Bias Current
Offset Current
Input Resistance,
Input Capacitance
Common Mode Range
Input Noise Voltage (f ; 1kHz, Rg ; 00)
TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 3)

TEMP

MIN

20

1

TYP

MAX

UNITS

10
20

mV
mV
IlV/OC

35
50
7
9

10

IlA
IlA
IlA
IlA
Kohms
pF
V
nV/..[HZ

120

V/V
V/V
dB
'MHz

1
100
1
±10

±10
10

OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 3)
Output Current (Note 6)
Output Resistance
Full Power Bandwidth (Note 3 & 7)
Differential Gain
Differential Phase
Harmonic Distortion (Note 10)

Full
+25 0 C
+25 0 C
+25 0 C
+25 0 C
+25 0 C
+25 0 C

±10
100

+25 0 C
+25 0 C
+25ClG

20
35
50
7
9

100
1

Common-Mode Rejection Ratio (Note 4)
Gain-Bandwidth-Product (Note 5)

Power Supply Rejection Ratio (Note 9)

MIN

10
20

10K
5K
70

POWER REQUIREMENTS
Supply Current

MAX

I.
.,;G

HA-2542-5
DoC to +750 C

::Ez
o=>
u"a.: --'
::Eo

--+---0 0 UT
990n

Ion

AVCL = tOO· PHASE AND GAIN
NON INVERTING CIRCUIT (A\lCL.= 2)

IN 0-----1

>-...---<>

OUT

son

son

AVCL = 2· PHASE AND GAIN
VIDEO CABLE DRIVER

IN 0----1
IN

OUT

VIDEO CABLE DRIVER PULSE RESPONSE
(tV/DIV.; tOOns/DIV.)

2-70

IJ~RIS

HA·2544

ADVANCED

Video Operational Amplifier
Features

Applications

•
•
•
•
•
•

•
•
•
•
•
•
•

Unity Gain Bandwidth .......................................... 33MHz
High Slew Rate .................................................... 1S0VI/ls
Low Supply Curren!. ............................................... 10mA
Differential Gain Error ......................................... <0.1 dB
Differential Phase Error ..........................................<0.1 0
Gain Tolerance at SMHz ......................................... 0.2dB

Video Systems
Video Test Equipment
Radar Displays
Imaging Systems
Pulse Amplifiers
Signal Conditioning Circuits
Data Acquisition Systems

a.:t-=

::;;;~

0::>

Description

c..lLJ..

c..-...I

The HA-2544 is a dielectrically isolated, monolithic operational amplifier designed and constructed in the Harris
High Frequency Process. It is another addition to the
Harris series of high spe~d, wideband op-amps and offers
true video performance combined with the versatility of
an op-amp.
The HA-2544 features 33MHz unity gain bandwidth and
150V//ls slew rate while offering video performance of
<0.1 dB differential gain error, <0.1 0 differential phase
error, and gain tolerance of just 0.2dB at 5MHz. High
performance and low power requirements are met with a
supply current of only 10mA.
Uses of the HA-2544 range from video and video test
equipment to radar displays and other precise imaging

Pinouts

systems where stringent gain and phase requirements
have previously been met with costly hybrids and discrete
circuitry. The HA-2544 can also be used as a standard
wideband, high speed, and fast settling op-amp in circuits
such as pulse amplifiers and high speed data acquisition
systems.

The HA-2544 is guaranteed over the military temperature
range (-55 0 C to +125 0 C) in either the -2 or -8 versions, and
over the commercial temperature range (OOC to+75 0 C) as
a -5 version. The HA-2544 is available in TO-99 metal can.
20 pin LCC, and both epoxy and ceramic Mini-DIP
packages.

Schematic
TOP VIEWS

COMPENSATION

BALANCE

08

COMPENSATION

Z

7

v+

tN+

3

6

OUT

v-

4

5

BALANCE

IN-

v-

2-71

::;;;0

«a::
c..~

00
(.)

HA·2600/02/05
Wideband, High Impedance
Operational Amplifiers
FEATURES

DESCRIPTION

• WIDE BANDWIDTH

12MHz

• HIGH INPUT IMPEDANCE

500M!1

• LOW INPUT BIAS CURRENT

HA-260012602/2605 are internally compensated bipolar operational amplifiers that feature very high input impedance (500
Mn, HA-2600) coupled with wideband AC performance. The
high resistance of the input stage is complemented by low offset
voltage !O.5mV, HA-2600) and low bias and offset current
I1nA, HA-2600) to facilitate accurate signal processing. Input
offset can be reduced further by means of an external nulling
potentiometer. 12MH z unity gain-bandwidth product, 7V / Il s
slew rate and 150,OOOV IV open-loop gain enables HA-2600/
2602/2605 to perform high-gain amplification of fast, wide band
signals. These dynamic characterisitics, coupled with fast
settling times, make these amplifiers ideally suited to pulse
amplification designs as well as high frequency (e.g. video)
applications. The frequency response of the amplifier can be
tailored to exact design requirements by means of an external
bandwidth control capacitor.

InA

• LOW INPUT OFFSET CURRENT

InA

• LOW INPUT OFFSET VOLTAGE

0.5mV

• HIGH GAIN

150K VIV

• HIGH SLEW RATE

7V/lls

• OUTPUT SHORT CIRCUIT PROTECTION

APPlICA TIONS
• VIDEO AMPLIFIER

In addition to its application in pulse and video amplifier designs, HA-2600/2602/2605 is particularly suited to other high
performance designs such as h'igh-gain low distortion audio
amplifiers, high-Q and wideband active filters and high-speed
comparators.

• PULSE AMPLIFIER
• AUDIO AMPLIFIERS AND FILTERS
• HIGH-Q ACTIVE FI LTERS
• HIGH-SPEED COMPARATORS

The HA-2600 and HA-2602 have guaranteed operation from
-55 0 C to +125 0 C and are available in metal can and ceramic
mini DIP packages. Both are offered as a military grade part.
The HA-2605 has guaranteed operation from DoC to +75 0 C
and is available in plastic and ceramic mini DIP and metal can
packages.

• LOW DISTORTION OSCILLATORS

PINOUTS

SCHEMATIC
COMPENSATION

Case Connected to VBALANCE

v-

TOP VIEWS
COMPENSATION

IN-

v+

IN+

OUT

v-

BALANCE

2-72

SPECIFICATIONS
U')

ABSOLUTE MAXIMUM RATINGS
Voltage Between V+ and V- Terminals
Differential Input Voltage
Peak Output Current
Internal Power Dissipation

45.0V

.± 12.0V
Full Short Circuit Protection
300mW

ELECTRICAL CHARACTERISTICS

-55 0 C ~TA~+1250C
OOC ~TA ~+750C
-65 0 C ~TA ~+1500C

TEMP

MIN

TVP

MAX

0.5
2

4
6

HA-2605
ooc to +75 0 C

HA-2602
-55 0 C to +125 0 C
MIN

TVP

MAX

MIN

TVP

MAX

UNITS

INPUT CHARACTERISTICS
Offset Voltage
Offset Voltage Average Drift

+25 0 C
Full

mV
mV
IlV iOC

Full
10
30

15

25
60

25
40

nA
nA

25
60

25
40

nA
nA

Bias Current

+25 0 C
Full

Offset Current

+25 0 C
Full

Input Resistance (Note 10)

+25 0 C

100

Full

± 11.0

+25 0 C
Full

lOOK
70K

150K

80K
60K

150K

80K
70K

150K

VIV
VIV

Full

80

100

74

100

74

100

dB

12

MHz

Common Mode Range

1
10

10
30
500

40

300

40

± 11.0

Mn

300

V

i 11.0

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 1.41
Common Mode Rejection Ratio
(Note 2)
Unity Gain Bandwidth Product (Note 31

+25 0 C

12

12

OUTPUT CHARACTERISTICS

± 10.0

±'12.0

V

Output Current (Note 41

+25 0 C

i 15

±.22

i 10

i18

i 10

±. 18

rnA

Full Power Bandwidth (Notes 4, 111

+25 0 C

50

75

50

75

50

75

kHz

Output Voltage Swing (Note 11

± 10.0 ±. 12.0

Full

± 10.0 ± 12.0

TRANSIENT RESPONSE
Rise Time (Notes 1, 5, 6 & 7)

+25 0 C

30

60

30

60

30

60

ns

Overshoot (Notes 1. 5, 6 & 71

+25 0 C

25

40

25

40

25

40

%

Slew Rate (Notes 1. 5, 7 & 121

+25 0 C

Settling Time (Notes 1, 5, 7 & 121

+25 0 C

±4

±7

±4

i4

±7
1.5

1.5

±7

Vi IlS

1.5

Ils

POWER SUPPLY CHARACTERISTICS
Supply Current
Power SupplV Rejection Ratio (Note 9)
NOTES:

+25 0 C
Full

3.0
80

3.7

90

3.0
74

90

4.0

3.0
74

4.0

90

rnA
dB

1. RL; 2Kn
2. VCM~±10V
3. Vo < 90mV

7. Vo ~ i 200mV

10. This parameter value guaranteed

8. See Transient Response Test
Circu its & Waveforms Page 2-57.

11. Full power bandwidth guaranteed

4. VO~'±10V

9.

I::..VS

~

±5V

by design calculations.

by slew rate measurement:

5. CL=100pF
6. Vo ~ ±200mV

FPBW = S. R./27TV pea k.
12. VOUT = ± 5V

2-73

I

4(

::I:

V+;+15VD.C., V-;-15VD.C.
HA-2600
-55 0 C to +125 0 C

PARAMETER

Operating Temperature Ranges:
HA-2600/HA-2602
HA-2605
Storage Temperature Range:

0
........
N
0
........
0
0
CD
N

0.::"":

:;:~
o=>
uu..

c..-....I

:;:0

--.....-~VO = (1 + llfl VREF

J

50PF
'

*5OpF'

1 000

Z,n

=

GAIN

_10 12

Zou1' ,01
1
2

0.9999

SLEW RATE' 4V/II' MIN

MIN
MAX

OUTPUT SWING"

t. IOV MIN. TO 50kHz

MINIMUM BIAS CURRENT IN REFERENCE CELL
SHORT CIRCUIT PROTECTiON

* A small load capacitance is recommended in all applications where
practical to prevent possible high frequency oscillations resulting

from external wiring parasitics.
Capacitance up to 100pF has
negligible effect on the bandwidth or slew rate.

2-74

PERFORMANCE CURVES
II)

=15V 0_ C.,

V+

5

110

l00r-----r-----r-----~----~--__,

!gIOO

10

~

~ 80

~ 1Or-----r-----t---.

~A- - ""-

1==

z

"

5

OffSET

5

V

,.,.S

-1 0

V-

-1 5

-SO

-25

0

+25

......

+50

+75

+100+125

1kHz

10kHz
100kHz
IMHz
UPPER 3dB FREQUENCY
LOWER 3dB FR EQUENCY - 10Hz
BROADBAND NOISE CHARACTERISTICS

TEMPERATURE DC
INPUT BIAS CURRENT AND OFFSET CURRENT
AS A FUNCTION OF TEMPERATURE

20

o

0

--.....

800

"" ~

400

100

~.

100Hz

1kHz

10kHz 100kHz

~

IMHz

~

"'~

35

15

+5

+25

+45

lOvF
10V~~~~~==J:====l===~

+65

IVr-----~----~~~----~------~

+85

g' o. IV r------t~------t------"<;~------~
~

"
"«

g

§
z

o

~

-+lOS +125

1
I

IOMHz lOOMHz

~s

TA

~-

~ lSV
0

-t

2SoC

80

60
40

~

"

---....

-

~'-"~-l

~ 100
z

«

:!'

~

'"

1

OPEN LOOP fREQUENCY AND PHASE RESPONSE

,

~

I

J:

110

1000

CD
N

~-

-

oct
"-....

-2 0
10Hz

lOMHz

+_2~C

"-....

;;: 40

~

• I. 15V

~4S) ~

6

...--- ~

Vs
TA

""'C1';

~ 60
0

o.........
N
o
.........
o
o

TA =25 0 C unless otherwise stated.

10
0 r-~--t----+----+----t--''''''''''',,",,~

0.01 VI\;;O'""Hc-,----;-;lO'"O''"Hc-'----~lM"'H~'-----cl;;;OM~H;:-'---;l"'OO'"MH,

fREQUENCY Hz

TEMPERATURE DC
INPUT IMPEDANCE VS. TEMPERATURE, 100Hz

OPEN-LOOP FREQUENCY RESPONSE FOR VARIOUS VALUES Of
CAPACITORS FROM COMPENSATION PIN TO GROUND

OUTPUT VOLTAGE SWING VS. FREQUENCY

Note- E>

~ 10r-----r-----r-~

5

0

110

~

.--

OffS[1

,,,,s ,,/'
~

-I5 50

25

,

\. .........

PHASE

0

---

0°
10°

~~

00°

'"

~

0
0

+25
+50
TEMPERATURE °c

+75

+100+125

1kHz

10kHz

100kHz

IMHz

IOMHz

~I 00°

l'

-10
10Hz

UPPER JdB FREQUENCY
LOWER JdB fREQUENCY - 10Hz
BROADBAND NOISE CHARACTERISTICS

INPUT BIAS CUR~ENT AND OffSET CURRENT_
AS A fUNCTION OF TEMPERATURE

I00°
I 40°

100Hz

1kHz

10kHz 100kHz IMHz

IOMHz lOOMHz

OPEN LOOP FREQUENCY AND PHASE RESPONSE

110
~ 100

1000

1OV~~~
IOVr==

-...... t'-....

800

~

'-.

100
35

15

+5

+25

+45

TEMPERATURE

+65

+85

+105 +125

110

~l 0

I

V

/

100kHz

IMHz

lOMHz

J

I.

I

..:!:.20V SUPPLY

./

/

V

10kHz

Note: External Compensation is ReqUired For
Closed Loop Gain < 5 If External Compensation is Used, Also Connect 100pF Capacitor
From Output to Ground.

OUTPUT VOLTAGE SWING VS. fREQUENCY

I,

1kHz

FREQUENCY Hz
OPEN-LOOP fREQUENCY RESPONSE fOR VARIOUS VALUES Of
CAPACITORS fROM COMPENSATION PIN TO GROUND

O.OIVl':-OkccHZ--I'"'OO='kccHZ---IC7M!cH-Z--7.IO"'M':-HZ----:I:::OOMHZ

12SoC

+, I 5
~
,/

100Hz

~

>

5

10

FREQUENCY Hz

10
St

~

i1!

.........

°c

10

00

0

~§! a.lv f-----+----+---+--"<~"

INPUT IMPEDANCE VS. TEMPERATURE. 100Hz

-SSoC

00

~

§

IV f - - - - - j -

~

""'-,

~

g '40

+,

""

400

z

- --

..!: 15V SUPPLY

!g
z 100

~

l"- e-- _2IOVSUpp(y
t-r-1~~

t-- r--

--

r-r--

)

80 55

10

10
15
SUPPLY VOLTAGE - VOLTS

15

5

25
45
65
TEMPERATURE 0c

85

105

125

OPEN-LOOP VOLTAGE GAIN VS. TEMPERATURE

COMMON MODE VOLTAGE RANGE
AS A FUNCTION Of SUPPLY VOLTAGE

TRANSIENT RESPONSE

SLEW RATE AND
TRANSIENT RESPONSE

SLEW RATE

~

35

SUGGESTED VOS ADJUSTMENT
AND COMPENSATION HOOK-UP

mv

,v

INPUT

OV

:~~T===110%~j
:

,

I~RISETlME

!

-'v

~

10% __ _
-5V -

NOTE: MEASURED ON BOTH POSITIVE
AND NEGATIVE TRANSISTlONS.

100KQ

9(1%-----

: :--d
• I

I I

,..._">----0 OUT
I
T_I SLEW RATE

!

I

dVl dT

-v

2-78

BANDWIDTH
CONTROL

TYPICAL APPLICA TIONS

DEFINITIONS
II)

N
........
N
N

HIGH IMPEDANCE COMPARATOR

INPUT OFFSET VOLTAGE-That voltage which
must be 'applied between the input terminals
through two equal resistances to force the output

voltage to zero.

+15,OV

........

o

N
CD
N
I

INPUT OFFSET CURRENT-The difference in the
currents into the two input terminals when the

>------:t-----
uu..

cause the amplifier to cease operating.

c.:-'

::;;:0

«a:

c..!z

00

u

HA-2630/35

mHARRIS

Not Recommended
For New Designs
See HA-5002

FEATURES
•

OUTPUT CURRENT

±400mA

•

SLEW RATE

500V /p s

•

BANDWIDTH

8MHz

•

FULL POWER BANDWIDTH

8MHz

•

INPUT RESISTANCE

•

OUTPUT RESISTANCE

•

POWER SUPPLY RANGE

•

PACKAGE IS ELECTRICALLY ISOLATED

High Performance Current Booster
DESCRIPTION

HA-2630 and HA-2635 are monolithic, unity voltage gain
current amplifiers delivering extremely high slew rate, wide
bandwidth, and full power bandwidth even under heavy output
loading conditions. This dielectrically isolated current booster
also offers high input impedance and low output resistance.
These devices are intended to be used in series with an operational amplifier and inside the feedback loop whenever additional output current is required. Output current levels are
programmable by selecting two optional external resistors.

2.0 x 10 6 n
2.0 n
±5V to ±20V

APPlICA TIONS
•

COAXIAL CABLE DRIVERS

•

AUDIO OUTPUT AMPLIFIERS

•

SERVO MOTOR ORIVERS

•

POWER SUPPLIES (BIPOLAR)

•

PRECISION DATA RECORDING

These current amplifiers offer an exceptional 500V / p s slew
rate and 8MHz bandwidth which allows them to be used with
many high performance op amps .in precision data recording
and high speed coaxial cable driver designs. 2.0M ohm input
resistance and 2 ohm output resistance coupled with ±400mA
output current make HA-2630 and HA-2635 ideal components
in high fidelity audio output amplifier designs.
HA-2630 and HA-2635 are available in an electrically isolated
TO-8 type can for ease of mounting with or without a heat
sink. HA-2630 is specified over the -55 0 C to +125 0 C range.
HA-2635 is specified from OOC to +75 0 C.

PINOUT

SCHEMATIC

TOP VIEW

OUT

v+

* Optional Current
Limiting Resistor

2-80

SPECIFICA TlONS

I.t)
('I)

ABSOLUTE MAXIMUM RATINGS

o

Voltage Between V+ and V- Terminals
Input Voltage Range
Output Current (Note 2)
Internal Power 0 issipation (Note 6) Free Air:
In Heat Sink:

Operating Temperature Range:
-55°C -:; TA -:; +125 0 C
OOC -:; TA -:; +75°C
Storage Temperature Range:
-65°C -:; TA -:; +150 oC

40V
± V Supply
±700mA
lW
4W

('I)

(HA-2630)
(HA-2635)

CD
N

«
::I:
I

ELECTRICAL CHARACTERISTICS
VSupply = ±15 Volts

RL

=50 Ohms

PARAMETER
INPUT CHARACTERISTICS
Bias Current

Unless otherwise specified.

TEMP.

HA-2630
-55°C to +125 0 C
MIN.
TYP.
MAX.

HA-2635
OOC to +75~C
MIN.
TYP.
MAX.

o.:~

:;:~

O:::l

UNITS

Input Resistance

+25 0 C

2.0

2.0

Mil

Input Capacitance

+25 0 C

5.0

5.0

pF

.95

V/V

Full

.85

150
200

.95

Offset Voltage (VOUT - VIN)

+25 0 C
Full

70

Bandwidth (-3dB)

+25 0 C

8.0

30

150
200

30

.85

70

±200
±300

±200
±300

J.lA
J.lA

mV
mV

8.0

MHz

OUTPUT CHARACTERISTICS
Output Voltage Swing

Full

±10

:t12

±10

:t12

V

Output Current (Nole 1)

Full

±300

±400

±300

±400

mA

Output Resistance

+25 OC

2.0

2.0

il

Full Power Bandwidth (Note 1)

+25 0 C

8.0

8.0

MHz

TRANSIENT RESPONSE
Rise Time (Note 3)

+25 0 C

30

30

ns

Slew Rate (Note 4)

+25 0 C

POWE R SUPPLY CHARACTERISTI CS
Supply Current

Full

Supply Voltage Range

Full

Power Supply Rejection Ratio (Note 5)

Full

NOTES:

1.

:;:0

«a:
c..!;;!
u

00

+25 0 C
Full

TRANSFER CHARACTERISTICS
Voltage Gain (Note 1)

uu.
c..--'

200

500

15
±5

200

15

20
±20

500

±5
66

66

V/J.ls

23

mA

±20

V
dB

5. llVSUPPLY ~ :±.5V.

VO~:±,10V

2. Heat sink is required for continuous short circuit
protection, regardless of current limit setting.
3. Va ~ O.4V p-p.
4. Vo~ 10V p-p.

6. Without heat sink, derate by 14mW/oC ambient
temperature above 1 DOoe ambient, with heat
sink, derate by 67mW/oC case temperature above

115°C case.

2-81

PERFORMANCE CURVES
V+= 15VDC, V-= 15VDC, TA= 250C UNLESS OTHERWISE STATED
OPEN LOOP FREQUENCY ANO
PHASE RESPONSE (RL = Son, CL ",10pfi

OUTPUT SWING
(RLlMIT= onl

,
,

17.

A~

-

~

0

~
.A ~=5Dr.
,.A ~
~

.........

Rl-30DQ~

PHASE

0

,

o

10

,
,

...

1
0

1

.........
GtN,

0
-2 0

15
Supply Voltage !tVoltsl

,.

-30
lOOK

20

Frequlncy,Hl

2
270

I

'''''

,

31
100M

NORMALIZED AC PARAMETERS vs.
SUPPLY VOLTAGE (RL = son I

NORMALIZEO AC PARAMETERS vs.
TEMPERATURE (RL = 50m
2
.2
.1
.1

.0

.9

or-

...V
V

"

8

-25

+25

+50

+15

+100

?

/SLEWRATE

8

I
-50

~~

,

-3dbBANDWID~

'~EWRATE

-3b~IDTH

0

I

.7

+125

10

Temileralure,!OCJ

12

14

16

18

20

SupplvVoltage,(Volts)

OUTPUT CURRENT LIMITING vs.
LIMITING RESISTANCE

OUTPUT CURRENT CHARACTERISTIC

fTl!f

1000

"

100

2.'

-250 -:2Po

~

-10

-10

-50

I /

-I LIMITfRZI

/

/

"'1"',,/

0

V

/I

R2= 100

POWER DISSIPATION vs. LIMITING RESISTANCE

, WITH OUTPUT SHORTEO TO GROUND; VIN = +10V

-

1-

-

r- r-

1

,

--

200

250

~'jiLlJ

-7.5
H2=20r.!
-10.0

14

16

18

'~
~ I"-....

1

1

12

150

eASEL.PERAJOE

3

1

10

100

MAXIMUM ALLOWABLE INTERNAL
POWER DISSIPATION vs. TEMPERATURE

4

t--

II
J!RI:Z.5,l

Output Load Current, {mA)

10
100
limiting Risistance, (01

3

50

I

-5.0

R2 =s.on

,

AI-IOVl Z
I/AI"'O" I

HI=20r!
7.'

+llIMITUI,)

0
90

20

iMB(':~~!~~~~:~~URi

100

110

n
120

TemperaturlDC

limitIng Resislance,{Q)

2-82

130

140

.......

TYPICAL APPLICATION
20dB, 5MHz VIDEO COAXIAL LINE DRIVER
HA-2530

HA-2630

son COAX

"""L.r
a.:G
:;:;;::
0:::>

uu...
c.:....1
:;:0



,

(.)

"
VOLTAGE
~OISE

5

\

5

4

"\.\

o

Z

-......... BIAS CURRENT

. .

0

15

.25

-25

'"
E

.......,

O"jET CURRiNT

-50

'" ,,\

C

"r':

~'"

Q

-

>

2

:::>

,'25

'00

3

cc

-'"

,

0
10

NORMALIZEO AC PARAMETERS
vsTEMPERATURE

(.)

'"+
.s
~

a:

2"

co 120

.~

';;;
C!l

--

8

Z

~25

-25

... 50

.15

0

8

'"
E

BA:::~ ...........
-50

0

'0

0

co
o

0

I

~~

c·

-0

§o

,

-0

'":::> o SLEW RATE " " " .........

~

Frequency Hz

..........

1. 4

1.

,

0- 13
lOOK

10K

1K

100

OPEN LOOP FREQUENCY ANO
PHASE RESPONSE

N

~

CURRENT
NOISE
_

I'---

Temperature,oC

o

,

0. 14

' ............

0

«c

INPUT NOISE CHARACTERISTICS

0-....

10

.. 125

:ii
c-

Temperature,oC

o

-4

I

i ,9

PHASE

~

~ "-

__ : I,

~

>

...J

45'

i

I

I

0
10

100

lK

i

10K

\

t

l~ ~ ,80'

lOOK

,M

I

1\ "

I

1 i, 10'

I

10M

Frequency Hz
OPEN LOOP FREQUENCY RESPONSE FOR
VARIOUS VALUES OF CAPACITORS FROM
COMPENSATION PIN TO GROUND

NORMALIZEO AC PARAMETERS
vsSUPPLY VOLTAGE AT+250C

>1.2

~
;t; CL~'00j'F

<=>

M

+,
o

-"
~.
'"

~

a:

>

§o
Z

.9

/
.8

10

C.

I

~
30pl
_100pF

40

.3c

." ,/

20

,~
c.!:I

~~ ~

'":::>

"iii

~

SlEWAAT~

,

~. 80f--""'I?-~:N.""",,;;:-----+1_-_:tC:~~~;t;

__

I

'"co

30

40

Supply Voltage, Volts
Frequency Hz
NOTE:

2-86

External Compensation Components are not Required for
Stability. But May be Added to Reduce Bandwidth if Desided.
C L ::;: 100pF is Also Required for Stability Only if External
Compensation Capacitor is Used.

PERFORMANCE CURVES (continued)
OUTPUT VOLTAGE SWING
vs FREQUENCY AT +25 0 C

OUTPUT CURRENT CHARACTERISTIC

40

100
I---

AV

""~ ~

c:
~

10 0

VSUPPL Y - !10V

o

>

0>

'"
0
>
.,.
'"
0-

,

o

1

"'~
~

0

AV

=

'0

I

~
0-

10K

1K

'~25"1 :'5"/

'55"/

I
I

/I

AI,'

=

1, VSUPPLY '" !20V

V,N - -151,'
·20

30
AV: I, VSUPPLY

V,N
·40

=

-35V

I

'I

Output Load Current, rnA

SWITCHING WAVEFORM AND TEST CIRCUIT
VOLTAGE FOLLOWER
PULSE RESPONSE

SLEW RATE AND TRANSIENT
RESPONSE TEST CI RCUIT

IN

I

i\
\

J

'I

~

RL~5K'CL ~50pF

Vertical ~ 10V/Oiv.
Horizontal ~ 5jJs/Div.

SUGGESTED

±40V

1M

lOOK

Frequency, Hz

T A ~ +25 0 C
Vs ~ ±40V

vas

ADJUSTMENT

-v

2-87

I
I

1/ /11
5
/'0
of 15 _55°CJ20
1+250C
+t50C
·10

·55" 1'''''ll''''
l I

1

I

I
I

.l 10

I

o

'I

V,N: + 15V

II 1//
II "-

~

)

I, VSUPPL Y ~ !2IJV

. .55::5:\;5\ 10

~

~

.,

I

30

0>

CIJ

I

.

V,N: +3!iV

I--- VSUPPL Y - ±20V
.~

1, VSUPPL Y = ±40V

""SUPPL Y : ±40V

HA·2650/55
Dual High Performance
Operational Amplifier
FEATURES
• SLEW RATE

5V//J.s

• BANDWIDTH

8MHz

• BIAS CURRENT

35nA

• AVG. OFFSET VOLTAGE DRIFT

8/J.V/oC
75mW

• POWER CONSUMPTION
• SUPPLY VOLTAGE RANGE

±2VTO±20V

APPlICA TlONS

HA-Z650/2655 contains two internally compensated operational amplifiers offering high slew rate and high frequency performance combined
with exceptional DC characteristics.
5V II" sec slew rate and 8M Hz
bandwidth make these amplifiers suitable for processing fast, wideband
signals extending into the video frequency spectrum. Signal processing
accuracy is enhnaced by front-end performance that includes 1.5mV
offset voltage, 8/J.V/oC offset voltage drift and low offset and bias
current (1 nA and 35nA respectively). Offset voltage can be trimmed to
zero on the devices offered in dual-in-line packages. Signal conditioning
is further enhanced by 500M input impedance.
Applications for HA-2650/2655 include video circuit designs such as
high impedance buffers, integrators, tone generators and filters. These
amplifiers are also ideal components for active filtering of audio and
voice signals.

• VIDEO AMPLIFIERS
• HIGH IMPEDANCE, WIDEBAND BUFFERS

HA-2650/2655 are offered in 14 pin DIP and metal TO-99 packages and
are also available in dice form. HA-2650 is specified form -55 0 C to
+125 0 C. HA-2655 operates from OOC to +75 0 C.

• INTEGRATORS
• AUDIO AMPLIFIERS
• ACTIVE FILTERS

PINOUTS

SCHEMATIC
TOP VIEWS
v+

----+_ _ _ _ _ ONE_HALFHA_2&!iOJHA_2655 _ _ _

~_

_ _ _ _~:

~-~~--r-~-~-r-~~,-._,-v.

i
I

I
I
I
I
I

Rl

20U

I
I
I
I


c.: -'

:;;0



Vo

[--+-

?
~
90'

.,

1

~

o

Lel

r=
.-

NORMALIZED AC PARAMETERS VS. SUPPLY VOLTAGE
1. 1

. I
4~i~rE 121 I
IA' YI
A'" y!
I
1/ BAN OWl OTH I

l-:

DC9

B

I I

(VOLTAGE FOLLOWER)
RL ~ 2k
CL ~ 50pF

Mtlm-i
lk

;1

i

7

±to

i.t

10k
FREQUENCY 1Hz)

~1.2

...

lOOk

-- ......

o

~1.1 c-t---t w
=.

.

-

--

t-

--

~

~ 1.0 -

o
w
=>

~ .9
o

-t- t-t-- - - - t--

±15

±20

o

...............

c-- -

:_~~WRATEo

~

1-- - ' -

---- -

r-- ,,-

--7~'

"" .B
~ -55

SUPPLY VOLTAGE

._--

/"

~

N

1M

_.-

~

!

I-}1---

i5

II Illil

NORMAlIZEQ AC PARAMETERS VS. TEMPERATURE

U

V

~s ~ ±15V
L"VS~±10V
Vs ~ ±5V
Vs ~ ±2V

Jl1

-

o

100M

,
I

I

100

J-J

1\

BV

~1. 0

.0 1

I I

~

Vo - 2V

~o. 11-

10M

lHV

Vo

0

o

I

~ 20

S

00

1
PHASE

JIIVo !II
2av

"-

II
U

I

"~ 40
>

. I

IllIillll
III!II

r-- r--

-25

+25

r-

-RANO~-:-H

+50

+75

+125

TEMPERATURE 10C)

z

INPUT NOISE VOLTAGE VS. FREQUENCY

__ 70

>
-7 50 ~
w

~ 40
~
~ 30
w

~1 0 1

'"
E

,:.

v

~

RESI~

I J
100

2.0

VS=±2V

1.5

1

, lk
FREQUENCY (Hz)

10k

!

1.0
-55

lOOk

I

___ 1

l

-25

o

COMMON MODE REJECTION RATIO
VS. FREUUENCY

!g 100
~

~ 80

z

o

~~

.........

.... ,

60

w

g

,. 40

....

,.,.z

o

8 2a

,

a
100Hz

1kHz

10kHz
FREQUENCY - Hz

2-90

100kHz

t- I

1

-+--+-t-t ..,

i r-tt-ttJj

+25
+50
TEMPERATURE 10C)

120

o
;::

I

IT. t"tl-t[

=>

U

I I

!'O 0
10

3.0,--

~ 10kSlSOURCE RESISTANCE
""- ~ 1

~ 2o OSlSOURCE
z

POWER SUPPL Y CURRENT VS. TEMPERATURE

1 1
I I

~ 60 K\

lMHz

+75

+125

PERFORMANCE CHARACTERISTICS
II)

~

SLEWING WAVEFORM

TRANSIENT RESPONSE/SLEW RATE CIRCUIT

o

II)

CD

C\I
I

OV
>-~-'-~HDVOUT

--

VOUT

Note: Numbers in parentheses refer to the second half of

~

~

~

OV

""

VERTICAL 5V/DIV.

HORIZONTAL lJ.1s/DIV.

TO-116 package.

TYPICAL APPLICATIONS
LOW COST HIGH FREOUENCY GENERATOR
r -____

~R~2~-----------------------------EO~~
AMPLITUDE ADJUST

j;4R lC

12\

3 3\R2l
(Eo)pp ;

2VZ~~)

ABSOLUTE-VALUE CIRCUIT
R

Eio-~~~

R

R ______~______~~~__~~__~
____~~
V+

.14
12

>-<~-OEo;

lEil

10

R
HIGH IMPEDANCE
HIGH GAIN
HIGH FREOUENCY INVERTING AMP

lOOK

BW; 100KHz
AV; 100

Zin;2x10 9 n
Eo

-15V

2-91

:t;

:;;2

10

25°C

0.07

25°C
Full

15

Full

0.70

0.07

170
25
80

80

2-93

15
76

10

%

0.70

V/,us

170
25

250

Q

250
76

,uA
,uA
dB

«a:

...
12
00
(..)

SPECIFICA TIONS
ELECTRICAL CHARACTERISTICS V+=+15.0V, V··=-15.0V

HA-2720
-55,oC to +125 0 C
PARAMETER

TEMP.

INPUT CHARACTERISTICS
Offset Voltage

HA-2725
oOC to +75 0 C

ISET = 1.5/lA
: ISET = 15/lA
ISET - 1.5/lA
ISET = 15/lA
MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS

25°C
Full

2.0

3.0
5.0

2.0

3.0
5.0

2.0

5.0
7.0

2.0

5.0
7.0

mV
mV

Offset Current

25°C
Full

0.5

3.0
7.5

1.0

10
20

0.5

5.0
7.5

' 1.0

10
20

nA
nA

Bias Current

25°C
Full

2.0

5.0
10

8.0

20
40

2.0

10
10

8.0

30
40

nA
nA

Input Resistance (Note 10)

25°C

50

5

50

5

MQ

Input Capacitance

25°C

3.0

3.0

3.0

3.0

pF

25°C
Full

30K lOOK
20K

25°C
Full

80

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Notes 3 & 9)
Common Mode Rejection Ratio (Note 4)
OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 3)

25°C
Full

30K 120K
20K

90

90

90

80

± 12 i:13.51
±10

25K 120K
20K

25K 40K
20K
74

74

V/V
V/V
dB
dB

90

± 12 i:13.5
±10

±12 ±13.5
i 10

i:.12 ±13.5
i:.l0

V
V
rnA

Output Current (Note 5)

25°C

±0.5

i5.0

iO.5

i 5.0

Output Resistance

25°C

2K

500

2K

500

Output Short-Circuit Current

25°C

3.7

19

3.7

19

rnA

TRANSIENT RESPONSE
Rise Time (Note 6)

25°C

2.0

0.2

2.0

0.2 '

/ls

Overshoot (Note 6)

25°C

5

15

5

15

%

Slew Rate (Note 7)

25°C

0.1

0.8

0.1

0.8

V//lS

25°C
Full

20

POWER SUPPLY CHARACTE RISTICS
Supply Current
Power Supply Rejection Ratio tNote 8)

NOTES:

Full

210

80

80

210

20
450

50

450

50
76

Q

16

dB

1. For supply voltages less than tlS.0V, the absolute maximum input voltage is equal to supply voltage.
2. Derate at 6.8mW/oC for operation ambient temperatures above 7S0C.

VSUPPLY
3, T

= ±3.0V

= +2SoC and Full

4. V CM =±1.5V
5. Va = ±2,OV

VSUPPLY = ±15.0V

ISET = 1.5IJ.A

ISET = 15IJ.A

T - +25 0 C

RL = 75KQ

T = Full

RL = 75Kn

RL = 5KQ
RL = 75Kn

V CM = ±5.0V
Va = ±10.0V

6.

- - - - - - A V = +1, V 1N = 400mV, RL = 5K, C L = 100pF
7. Va = ±2.0V
Va = ±10.0V
RL = 20K
8. :!J.v = ±1.5V
.lv = ±5,OV
9. V a =±1.0V
V a =±10.0V
10. This parameter based upon design calculations.

2-94

/lA
/lA

PERFORMANCE CURVES

II)

UNLESS OTHERWISE NOTEO: T A =+25 0 C, Vs

N

=±15VOC

o

,....

N
N

I

«
::I:
INPUT BIAS CURRENT
vs. SET CURRENT
10'

=1=

INPUT BIAS CURRENT
vs. TEMPERATURE

INPUT OFFSET CURRENT
VI. TEMPERATURE

""

t3VSVsSt 18V

" H ....+--t-+--t-+-I,---j
.......

3"r--;--+-~-.~rv<-v-s<~,~-,,-v-+-;---1
2S'r--;--+-~-t--;--+-;---1

•

"of--d--+-+--t--t--+-+----i
1/

1

•

1
'.1

100

O.500C

SetCulI'1m'I,uA)

CHANGE IN OFFSET VOLTAGE
vs.ISET IUNNULLEOI

t

111111 II
:~~'~vs ~ t3V

250C

OOe

+25 0C+50oC
Temperalure

O=>

'r---.,

os

+1SoC +IOOoC.125 0C

::;;:0

~~S'C::-c.SO~'C::---:c1S!:::'C:--.~'C:--.:-;:1SC;;'V::--.'!;SO;;-,-':-;:1SC;;'C::--.,=oo;;;:'C-"~12'~OC
Tempe,alure

INPUT NOISE CURRENT
vs.ISET

INPUT NOISE VOLTAGE
vs.ISET

L,.o
:i!1O- 14

'.s

D',
?
, ~
"
,
,
, Isn=,0
::;..- ?
"

"

111111
VS·~ISV

IS~T~JJ~

,
,

,,
"

1K

'00

10

f

,

-soc

M

-2St

ISET=I~ ~

. .

ac

25t

POWER SUPPL Y REJECTION
vs.ISET

J lllllllll
I 1111111

1111
VS·tl!iV

r-

~

VS"t3V

,

,0'

0.'

II

t3VSVsStl8V

'00

,0'

80

10

,.,

'DO

SIJtCumnl!,uA1

10
SIICurrtnt UA

100
SfICurr.nl-IJA

SUPPLY CURRENT vs.
TEMPERATURE

NORMALIZED BANDWIDTH
VS. TEMPERATURE

1401--I--I-+-+-+---::-I--::c::-1--I
Vs = ~ 15V

.J

~15]..1.A

lOD~~==i=i=:j:=t:=1=~==1

'~
ISET=I.5IJA~
1

,

"'r--t---f-+-+-t--f----1--j
801--1---+-+-+-+---1-::-1--1

9

401--I_'S_'_''+'_."_A+_+_+V-,-,_=tj-"",V--':::--I

.•

VS"t3V

·sooe

2S oC

ODC

2S DC

500e

75°C

loooe

. .

-soc

12!i~C

Temperature

2-96

·25t

"OOt

"

.......

I'-...

. ....

+25C

T,mDerature

+50t

+15C+l00C+125C

. ."

15t

STANDBY SUPPLY CURRENT
vs.ISET

,0'

!
!

SOOt

T.mpBfllule

OPEN LOOP VOL TAGE GAIN
YS.ISET

'"

I"

10

1

100C

moe

PERFORMANCE CURVES
It)
('II

.........

o

PHASE MARGIN vs. SET CURRENT

SLEW RATE vs.ISET

('II

"'"
('II
I



U"-

C.:....I

:;:0

«a:

SUGGESTED
OFFSET NULL

c..~

00
U

-v
SerCu,,"nliIJ AI

v- OR
GNO

v-

v-

TRANSIENT RESPONSE/SLEW RA TE CIRCUIT

SLEWING WAVEFORM

INPUT

ov

OUTPUT

/

/
VERTICAL
HORIZONTAL
ISET-l00I1A

v-

2-97

\
WIDIV

lpS/OIV

;It

Not
FEATURES

•
•

HA·4600102105

HARRIS

For NeW DeSigns
See HA-510 4

LOW OFFSET VOLTAGE

DESCRIPTION
The HA-4600 series are high performance dielectrically isolated
monolithic quad operational amplifiers with superior specifications not previously available in a quad amplifier. These amplifiers offer· excellent dynamiC performance coupled with low
values for offset voltage and drift, input noise voltage and
power consumption.

0.3mV

HIGH SLEW RATE

±4V/ll s
SMHz

• WIOE BANDWIDTH

•
•
•
•

High Performance
Quad Operational Amplifier

Recol1\l1\e~ded

LOWDRIFT

2IlV/ OC

FAST SETTLING (0.01%, 10V STEP)

4.21l s

LOW POWER CONSUMPTION
SUPPLY RANGE

35mW/AMP

A wide range of applications can be achieved by using the
features made available by the HA-4600 series. With wide
bandwidth (SMHz), low power (35mW/amp), and internal
compensation, these devices are ideally suited for precision
active filter designs. For audio applications these amplifiers
offer low noise (SnV/ v'HZl and excellent full power bandwidth
(60kHz). The HA-4602/4605 is particularly useful in designs
requiring low offset voltage (O.3mV) and drift (2 iN/OC), such
as instrumentation and signal conditioning circuits. The high
slew rate (4V/lls) and fast settling time (4.2 Ils to 0.01%, 10V
step) makes these amplifiers useful components in fast, accurate data acquisition systems.

±5V TO ±20V

APPLICATIONS
•

HIGH Q, WIDE BAND FILTERS

•

INSTRUMENTATION AMPLIFIERS

•

AUDIO AMPLIFIERS

•

DATA ACQUISITION SYSTEMS

•

INTEGRATORS

•

ABSOLUTE VALUE CIRCUITS

•

TONE DETECTORS

The HA-4600 series are available in 14 pin CERDIP packages
which. are interchangeable with most other quad op amps.
HA-4600/4602-2 is specified from -55 0 C to +125 0 C and
HA-4600/4605-5 is specified overOoC to +75 0 C range.

PINOUT

SCHEMATIC
TOP VIEW

Out

14

1

Out
4

Inputs

Inputs

1

4

V+

11

v-

10
Inputs

2
Out
2

Inputs
3

Out
3

ONE FOURTH ONLY (HA-4600)

2-98

SPECIFICA TIONS

-It)

c

ABSOLUTE MAXIMUM RATINGS (Note 1)
TA = +25 0C Unless Otherwise Stated
Voltage Between V+ and V- Terminals
Differential Input Voltage
Input Voltage (Note 2)
Output Short Circuit Duration (Note 3)

Electrical Characteristics

Power Dissipation (Note 4)
Operating Temperature Range
HA-4600/4602-2
HA-4600/4605-5
Storage Temperature Range

40.0V
±7V
±15.0V
Indefinite

880mW

N
C
C
C

-55 0CSTA S+125 0C
OOCSTAS+75 0 C
-65 0CSTAS+150 oC

CD
qo
I

«J:

V+ = + 15V, V- = -15V

HA-4600-2
HA-4600-5
PARAMETER

TEMP

MIN

HA-4602-2
HA-4605-5

TYP

MAX

0.3

2.5
3.0

MIN

0.:""':

~~

TYP

MAX

UNITS

3.0

9
10

mV
mV

INPUT CHARACTERISTICS
Offset Voltage
Av. Offset Voltage Drift

+25 0C
Full
Full

Bias Current

130

200
325

Offset Current

+25 OC
Full

30

75
125

Common Mode Range
Input Noise Voltage (f = 1kHz)

Full

J.l.V/oC

5

+25 0C
Full

±12

+25 0C

Input Resistance

200

400
500

nA
nA

70

150
175

nA
nA

±12

V

8

8

500

500

nV/jHi.
kn

250K

V!V

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 5)

Full

lOOK
86

Channel Separation (Note 6)

Full
+25 0C

Small Signal Bandwidth

+25 0C

Common Mode Rejection Ratio (Note 9)

75K

250K

dB

80
-108

-108

dB

8

8

MHz

±12
±10

±13
±12

V
V

60

kHz

±8

±15

mA

200

n

OUTPUT CHARACTERISTICS
Output Voltage Swing (R L = 10K)
(RL=2K)
Full Power Bandwidth (Note 5)
Output Current (Note 7)

Full
Full

±12
±10

±13
±12

±10

±15

+250C
Full

60

+25 0C

200

+25 0C
+25 0C

50

150

50

150

Overshoot

30

45

45

Slew Rate

+25 0C

30
±4

Output Resistance
TRANSIENT RESPONSE (Note 8)
Rise Time

±2

±4

±1

4.2

Settling Time (Note 10)

ns
%

V/J.l.S

4.2

J.l.s

POWER SUPPL Y CHARACTERISTICS
Supply Current
Power Supply Rejection Ratio (Note 9)

+25 OC
Full

4.6
86

2-99

5.5

5.0
74

7.5

mA
dB

o=>

c..c:..>u..
.


NOTES:
1.

Absolute maximum ratings are limiting values, applied
individually, beyond which the serviceability of the circuit
may be impaired. Functional operability u.nder any of
these conditions is not necessarily implied.

2.

For supply voltages less than ±15V, the absolute maximum
input voltage is equal to the supply voltage.

3.

Anyone amplifier may be shorted to ground indefinitely.

4.

Oerate 5.8mW/oC above TA = +25 0 C.

5.

VOUT=±10V; RL=2Kohms.

6.

Channel separation value is referred to the input of the

amplifier. Input test conditions are: f = 10kHz; VIN =
200mV peak-to-peak; RS = 1K ohms. (Refer to Channel
Separation vs. Frequency Curve for test circuits.)
7.

Output current is measured with VOUT = ±5 volts.

8.

For transient response test circuits and measurement
conditions refer to Test Circuits section of the data sheet.

9.

AV = ±5.0 volts.

10.

Settling time is measured to 0.1% of final value for a 10
volt input step, AV = -1.

TEST CIRCUITS
1K

1K
IN o-MI'-.....- I

>--*--_--<0 OUT

lK

I'""

LARGE SIGNAL
RESPONSE·
CIRCUIT
(Volts: 5V/Oiv.,
Time: 5/..lS/0iv.)

... II

OV

I

SMALL SIGNAL
RESPONSE
CIRCUIT
(Volts: 10mV/Oiv.,
Time: 50ns/Oiv.)

OUTPUT

-INPUT

~

I

I'"

/

I

1
l'

h

\

\

OV

OV

11
HORIZONTAL: 50 NSEC/OIV.

VERTICAL: 10mV!DlV

VERT.5V/DIV.
H~RZ. 5fJs/DIV.

SETTLING TIME CI RCUIT
+15V

2N4416
~'----('1 TO

OSCILLOSCOPE

• AV = -1.
• Feedback and summing
resistors should be 0.1%.
• Clipping diodes are optional.
HP5082-2810 recommended.

2-100

PERFORMANCE CURVES
It)

o
N
o
........
o
o

........

V+=+15V, V-= -15V, TA =+25 0 C Unless Otherwise Stated.

OFFSET VOLTAGE INPUT BIAS AND OFFSET
CURRENT VS. TEMPERATURE

OPEN LOOP FREQUENCY RESPONSE

CD
o::t

180

~IASC~RREN~

I'

0

.........

0

o~

'9 0
1

--r--

1
1

~~

::

o

., 0

{TYPICAL}

0

900

(HASE_

I

.10

- f-

-

Ivos\ HA-4600

4

.1 0

0

0.4 2.

0
0,2

·300

0

!lOpF

',GAIN!

0

./

I-- k - - - -

I-I-

.) 0

0

t--

CL

~

~
~ ~ +6 0

......... ' " OFfSET CURRENT

0

RL"2K

.B0

1



100M

:;00

'"

I
I

10K

lOOK

10M

1M

u"C.: -'



2ND ORDER STATE VARIABLE FILTER (1kHz, Q = 10)

u"c..
......
«0:
c..!2;

:;;:0
00

u

~~~~~~------------------~'-~BANDPASS

948K

r-------------l
I

I

I

I

I

i

I
I

I

49.9K

I
I
I

24.9K

NOTES: ,. MAKE R,C, = R2C2

,

2. fe = 2nR,C,

3.Q='h(1+~~)

I

IL ____________
-=(OPTIONAL)...I:

The state variable filter is relatively insensitive to component
changes (changes can be adjusted out with potentiometers)
and also has low sensitivity to amplifier bandwidths. (Amplifier
gain bandwidth product should be» Q x fCI. The bandwidth
criteria will determine whether a general purpose op amp like
Harris HA-4741 or the wide band HA-4602/4605 should
be used.
This filter finds wide application because multiple filtering
functions are available simultaneously (High pass, Lo pass,
Band pass, Band reject). In this circuit the various RC products
are matched with pot adjustments allowing for non-interactive

adjustment of Q and fC. This allows capacitors (C I, C2) with
loose tolerances to be used. To tune for fC, apply a sine wave
at fC to the input, adjust Rl for equal amplitudes at the Hi pass
and Band pass terminals (they will be phased 90 0 apart) then
adjust R2 for equal amplitudes at the Band pass and Lo pass
terminals.
The state variable filter is often used as building blocks in
multiple pole Butterworth of Chebyshev filters. Many references
contain normalized tables indicating settings for Q and fC of
each pole· pair section.

2-103

APPlICA TIONS (Continued)
SALLEN AND KEY 2ND ORDER LO PASS FILTER

NOTES:
IN

Rl

R2
OUT

= R2

1.

Make R1

2.

fe

= 21TR1JC1C2

3.

Q

= y,

1

J

C2

C1

In this filter all component values affect both 0 and fC. Precision, temperature stable resistors and capacitors must be used.

The advantage of using the Sallen and Key filter is simplicity,
but in any application this must be weighed against the statevariable type filter for accuracy, practicality, and cost. Amplifier bandwidth limitations are much more apparent at moderate
frequencies and 0 values with this filter design. (For accuracy,
amplifier gain-bandwidth product should be»fc x 0 2). The
wide bandwidth of the HA-4602/4605 is particularly advantageous in this design even at audio frequencies.

For economy, this filter could be used in the low 0 stages
of multiple-pole filter design, while the state variable type is
used in the more critical stages.

INSTRUMENTATION AMPLIFIER

,--,
I

\

~
~}-'-+-++-..,
\

' ..... _""

I

rI
I
I
I
I

I

I

L_J.~T~~A~) J
__

Instrumentation amplifiers (differential amplifiers) are specifically designed to extract and amplify small differential signals
from much larger common mode voltages.
To serve as building blocks in instrumentation amplifiers, op
amps must have very low offset voltage drift, high gain and wide
bandwidth. The HA-4602/4605 is ideally suited for this appli-

cation, delivering superior input and speed characteristics.
The optional circuitry makes use of the fourth amplifier section
as a shield driver which enhances the AC common mode rejection by nullifying the effects of capacitance-to-ground
mismatch between input conductors.

2-104

m~RIS

HA·4741
Quad Operational Amplifier
DESCRIPTION

FEATURES
•
•
•
•
•
•
•
•

SLEW RATE
BANDWIDTH
INPUT VOLTAGE NOISE
INPUT OFFSET VOLTAGE
INPUT BIAS CURRENT
SUPPLY RANGE
NO CROSSOVER DISTORTION
STANDARD QUAD PIN-OUT

The HA-4741, which contains four amplifiers on a monolithic
chip, provides a new measure of performance for general purpose
operational amplifiers. Each amplifier in the HA-4741 has
operating specifications that equal or exceed those of the 741type amplifier in all categories of performance .

1.6V/J.ls
3.5MHz
9nV/Hz
O.5mV
60nA
±2V TO±20V

HA-4741 is well suited to applications requiring accurate signal
processing by virtue of its low values of input offset voltage
(O.5mV), input bias current (60nA) and input voltage noise
(9nV/ .[HZ at 1kHz). 3.5MHz bandwidth, coupled with high
open-loop gain, allow the HA-4741 to be used in designs requiring amplification of wide band signals, such as audio amplifiers.
Audio application is further enhanced by the HA-4741's negligible output crossover distortion. These excellent dynamic
characteristics also make the HA-4741 ideal for a wide range of
active filter designs. Performance integrity of multi-channel
designs is assured by a high level of amplifier-to-amplifier
isolation (108dB at 1kHz).

APPlICA TIONS
• UNIVERSAL ACTIVE FILTERS
• 03 COMMUNICATIONS FILTERS

A wide range of supply voltages (±2V to ±20V) can be used to
power the HA-4741, making it compatible with almost any
system including battery-powered equ ipment.

• AUDIO AMPLIFIERS
• BATTERY-POWERED EQUIPMENT

The HAA741 is available in a 20 pin LCC package as well
as both 14 pin ceramic and epoxy mini·dips. The HA-4741·2
operates from ·55 0 C to +125 0 C and the HA·4741·5 operates
over the OOC to +75 0 C temperature range.

SCHEMATIC

PINOUT
TOP VIEWS

INPUTS

1

INPUTS

INPUTS

3

2
OUT

2L...1._ _ _...L..J

QUAD OP AMP

()I,,) HA-4741

2-105

SPECIFICA TlONS
ABSOLUTE MAXIMUM RATINGS
TA = +25 0C Unless Otherwise Stated
Voltage Between V+ and V- Terminals
Differential Input Voltage
Input Voltage (Note 1)
Output Short Circuit Duration (Note2)

ELECTRICAL CHARACTERISTICS

Power Dissipation For
Epoxy Package. (Note 3)
Operating Temperature Range
HA-4741·2
HA·4741·5
Storage Temperature Range

40.0V
±30.0V
±15.0V
Indefinite

880mW
- 55 0C:$T A~+1250C
OOC:$TA~+750C

- 65 0C:$T A ~+150oC

V+=+15V. V-= -15V
HA·4741·2
- 55 0 C to +125 0 C

PARAMETER

MIN.

TYP.

MAX.

UNITS

3.0

1.0

5.0

mV

5.0

4.0

6.5

mV
/lV/OC

TYP.

MAX.

+25 0 C

0.5

Full

4.0

Full

5

+25 0 C

60

TEMP.

HA·4741·5
DoC to +75 0 C
MIN.

INPUT CHARACTERISTICS
Offset Voltage
Av. Offset Voltage Drift
Bias Current

Full
15

Full
Common Mode Range

200

60

325

+25 0 C

Offset Current

5

30

30

75
± 12

Full

oifferentiall nput Resistance

+25 0 C

Input Voltage Noise (f = 1kHz)

+25 0 C

300

nA

400

nA

50

nA

100

nA

V

±12

MDo

nVIVth

TRANSFER CHARACTERISTiCS
Large Signal Voltage Gain (Note 4)

Common Mode Rejection Ratio

+25 OC

50K

Full

25K

lOOK

15K

+25 0 C

80

80

dB

Full

74

74

dB

25K

V/V
V/V

50K

Channel Separation (Note 5)

+25 0 C

90

-108

90

-108

Small Signal Bandwidth

+25 0 C

2.5

3.5

2.5

3.5

MHz

dB

OUTPUT CHARACTERISTICS
Output Voltage Swing (RL = lOKI
(RL=2KI
Full Power Bandwidth (Notes 4 & 91
Output Current (Note 61
Output Resistance

Full

±12

± 13.7

±12

±13.1

Full

±10

± 12.5

± 10

± 12.5

V
V

+25 0 C

14

25

14

25

kHz

Full

±5

± 15

±5

±15

mA
Do

+25 0 C

300

Rise Time (Note 111

+25 0 C

75

140

75

140

Overshoot (Note 111

+25 0 C

25

40

25

40

Slew Rate (Note 121

+25 0 C

±1.6

300

TRANSIENT RESPONSE (Notes 7 & 101

±1.6

ns

%

V//l s

POWER SUPPLY CHARACTERISTICS
Supply Current

Power Supply Rejection Ratio (Note 81

NOTES:

1.

2.
3.
4.
5.
6.

+25 0 C
Full

5.0
80

7.0
80

rnA
dB

For supply voltages less than:t 15V, the absolute

7. See Pulse Response Characteristics.

maximum input voltage is equal to the supply
voltage.
One amplifier-may be shorted to ground indefinitely.
Derate 5.8mW/oC above TA == +25 0 C.

8. 6V=:t5.0V.
9. Full power bandwidth guaranteed based upon slew

VOUT = ±.10, RL = 2K.
Referred to input; f = 10kHz, RS = 1 K.
VOUT =:!: 10.

2-106

rate measurement FPBW = S. R./21r Vpeak.
10 RL = 2K. CL = 50pF.
11. VOUT = ±. 200mV.
12. VOUT=:!:5V.

PERFORMANCE CURVES
V+=+15V,V- = -15V,TA=+250 C

Unless Otherwise Stated.
OUTPUT VOLTAGE SWING
VS.FREQUENCY

11111

OPEN LOOP FREQUENCY RESPONSE
"0 = 2811

0

V

•

V

Va: 811

... 110

tvSK~15V
V ·.IOV

~!!~5V

0

111111 II

+100

I

1~~II,'~t

.90

.so

1,10' 2V

Cl "50pF

IIIII
II '"!2V

0'

"-

GAIN

'70

0

*II

.60
'50

0.:1--'
::;;:~
o=>

PHASE

.40

.10
'10

u

1111

so'

1

11111

-10
10

10K
lK
FREQUENCY - Hl

100

lOOK

10M

1M

a.."""
a..!z
00

::;;:0
~a:

Cl=5OpF

1

1

u"-

(VOLTAGE FOLLOWER)
Rl = OPEN

'-r-

.30

100

1111111
10K

1K

FREQUENCY

lOOK
~

Hz

NORMALIZED AC PARAMETERS
VS. TEMPERATURE

NORMALIZEO AC PARAMETERS
VS. SUPPLY VOLTAGE
2

1

BANOWIO~

0

1

/~
SLEW RATE
BANDWIDTH

9

0

f--

If
I

B

SLEW RATE

"!15V

"!10

.

~ 20

100

SUPPLY VOLTAGE

TEMPERATURE

5

I

0

I

~25

1

, ~
~
~

15

0

_r---.

0
NDISEVOLTAGE

"-..

o~
~

[[[[I
1[[[1

•

6

PHASE MARGIN

BANDWIDTH

.

0-

3

[\

~

"

-

0

10

0

o

NOISEGURRENT

2

r---..

1

0
10

100

1000
LOAD CAPAcITANCE _pF

2-107

,

5

"

.

0

,~ I i~

[

I

50

06

~ ...........

_oc

SMALL SIGNAL BANOWIOTH AND PHASE
MARGIN VS.LOAD CAPACITANCE

INPUT NOISE VS. FREQUENCY

~~

"

9

I

,

20

BA~~

/ ' f..-

/'

10,000

100,000

PERFORMANCE CURVES (Continued)
MAXIMUM OUTPUT VOLTAGE
SWING VS. LOAD RESISTANCE

CHANNEL SEPARATION VS. FREQUENCY

I 11111111

• >10

I

"

f--H-++tHtt---+--r-H+tttt--..ft+t--"J~bH-tt+!t-+-t+1tttt1

'::~~~,',
,~,I
:

11'111

~ 25f--+-r-+++HH-~~~H+~-+-+44+~

~
w

~20f--+-r-++~H-~-4~H+~-+-+44+~

1,1, +H++HtI'---_t-+++ttH1

o
>

C,S'20l0G(~)
IDOVOI
i

·SO~

~ 15f--b~+++HH--1-4-rH+~_+-+44+~

:l= ~.:+-H:H+:~~;t-+++mt
ob
-11111111

I 11111111

I

10 /

o

~

~

I III

"

100

~

..

5L--+-r-+++HH--1-4-rH+~-+-+44+~
I

lOOK

OL'OO~L-~~Ull'K-~~LU~l~OK-~~~U'~OOK

fREQUENCY -Ill

LOAO RESISTANCE - OHMS

INPUT BIAS AND OFFSET CURRENT
VS. TEMPERATURE

POWER CONSUMPTION
VS. TEMPERATURE

80

-f-

Vs - ~ 15V

BIAS CURRENT

~~

~

40

r-

>10

""""- r-..

-

Vs '±10V

-

r"-.
""""-

10

--

VSd5V

t::~t;:rR A~r
.15
TEMPERATURE -"C

-

40

."

+100

·50

+125

·15

.50

'15

TEMPERATURE_DC

."

+125

PULSE RESPONSE
TRANSIENT RESPONSE/SLEW
RATE CIRCUIT

L~
VIN

n
-::-

1
~OPFV_

SLEW RESPONSE

TRANSIENT RESPONSE

(Volts: 5v/Div, Time: 5/Js/Div)

(Volts: 40mV/Oiv., Time: lOOns/Div.)

'".
VOUT
2KS2

-5V H-+-+-+-+-+-+-+-I-!
+5V H-+---V-+-+-Hr\-t-.+-I
-5V H-f-V-t-t-t-+--t-i"-t--i

2-108

m~RIS

HA·4900/02/05
Precision Quad Comparator

FEATURES

DESCRIPTION

• FAST RESPONSE TIME

130ns

• LOWOFFSETVOLTAGE

2.0mV

• LOW OFFSET CURRENT

10nA

The HA-4900 series are monolithic, quad, precision comparators offering fast response time, low offset voltage, low
offset current, and virtually no channel-to-channel crosstalk
for applications requiring accurate, high speed, signal level
detection. These comparators can sense signals at ground
level while being operated from either a single +5 volt supply
(digital systems) or from dual supplies (analog networks) up
to ±15 volts. The HA-4900 series contains a unique current
driven output stage which can be connected to logic system
supplies (V Logic+ and VLogic-) to make the output levels
directly compatible (no external components needed) with
any standard logic or special system logic levels. In combination analog/digital systems, the design employed in the
HA-4900 series input and output stages prevents troublesome ground coupling of signals between analog and digital
portions of the system.

• SINGLE OR DUAL-VOLTAGE SUPPLY
OPERATION
• SELECTABLE OUTPUT LOGIC LEVELS
• ACTIVE PULL-UP/PULL-DOWN OUTPUT
CIRCUIT - NO EXTERNAL RESISTORS
REQUIRED

APPLICATIONS

• THRESHOLD DETECTOR

These comparators' combination of features makes them
ideal compo;;;;;;ts for signal detection and processing in data
acquisition systems, test equipment, and microprocessor/
analog signal interface networks.

• ZERO-CROSSING DETECTOR
• WINDOW DETECTOR
• ANALOG INTERFACES FOR MICROPROCESSORS

All devices are available in 16 pin dual-in-line ceramic packages. The HA-4900/4902-2 operates from -55 0 C to +125 0 C
and the HA-4905-5 operates over a OOC to +75 0 C temperature range.

• HIGH STABILITY OSCILLATORS
• LOGIC SYSTEM INTERFACES

PINOUTS

SCHEMATIC
TOP VIEWS

IN+2

ONE FOURTH ONLY (HA-4900 SERIES)

2-109

o.:G
:;:z
O::l

u"-

---oVOUT

OVERDRI~r-_ _ _ _ __

INPUT

----- -

T

VTH =ov

IOOmV

f

IOOmV

~

-.L------VTH=OV

T

OVERDRIVE

OUTPUT
T=O

For input and output voltage waveforms for various input overdrives see Performance Curves.

2-111

a.:t3
:;;2
0::::>

uu..

a..-"'"
:;;0
«'"
a.. I-

015
u

PERFORMANCE CURVES
V+ ~ 15V, V- ~ -15V, V Logic(+) ~ 5.0V, VLogic(-) ~ OV, TA ~ +25 0 C, Unless Otherwise Stated.

INPUT BIAS CURRENT VS. TEMPERATU RE

INPUT OFFSET CURRENT

VS.

TEMPERATURE

100
BO

0

...

5

"""-

r--.....

0

--

0

0

/

5

I

0

-25

-55

25

50

75

100

0

125

--.

-25

-55

50

25

TEMPERATURE, (Oe)

~

100

75

125

TEMPERATURE, (OC)

INPUT BIAS CURRENTvs. COMMON MOOE INPUT VOLTAGE
(VOl FF. ~ OV)

0
0

-

"'"

0

...........

--....

\

0
0
-1

"

"

COMMON MODe INPUT VOLTAGE

\
15

SUPPL Y CU RRENT vs. TEMPE RATU RE

SUPPLY CURRENTvs. TEMPERATURE

FOR ±15V SUPPLIES AND +5V LOGIC SUPPLY

FOR SINGLE +5V OPERATION

V+=5.0V

VLOGIC(+) = s.nv

...

"r----,----r----,----r----,----r----,---,
V+" 15.0V
v-= 15.0V

Ipst

v- = VlOGIc(-) = GND

............

IpSL

Vour= H

-........: ........

VLOGIClt) = 5.0V

lO~--1=====~==~====~V=O=UT=O=L~~SV~LO=G=IC~[-}=o=GN=0=t==~
- __-4---+---+---+~_+--_+--~

5

IpST

VOUT = H

f_---+~--f_--+--_+[PS' --+"'-./-+---+---1

4

VOUT"H

IpS-

f_---+----if_---+----+VOUT Lr-j'--.----l---+-----l

3

0

,,/

IpS+

Your = l

,.

--......

~
IpSL

Your = l

V----f_---+----1
l-----+---jf-------+----+ IPS
- = HIYour
IpSl
VOUT=l~
1

-50

-25

25

50

75

100

0

-50

125

-25

25
TEMPERATURE, (OC)

TEMPeRATURE, (OC)

2-112

50

75

100

125

PERFORMANCE CURVES (Continued)

-Ln

o
N
o
o
o

RESPONSE TIME FOR VARIOUS INPUT OVERORIVES

CD

\

\ I\\.
,\'\ /V
\~
\ \\

Vour
VOLTS

::~~

=SmV-......

.2~V,~ ~ ~

Your
VOLTS

or::rI

-=

OVEROR1~E - 20mV .............

.......... OVERDRIVE = 20'rV



400

uu.

a..-...J

TIMEns

ns

:;;0

«0:
a..!z

MAXIMUM PACKAGE OISSIPATION
vs. TAMBIENT
2.0
1.75

00

u

MAXIMUM POWER DISSIPATION vs. SUPPLY VOLTAGE
(NO LOAD CONDITION)

r\

250

\.

1.50

\

200

1.25

Iz'

\
\

0.75

~

p ....

iii

100

V

~

50

0.2 5

/'

V
L..,:::: ,:::::: ~

25

50

75

100

/

.......-

"ffi

\

0.50

V

v,
150

o

125

--

I--- v

I-

~-,

k- rk- I-"

10
SUPPLY VOL rAGE, (VOL lSI

---

~

/'

l.?

~

\
V\OGlCt l
12

-

r14

AMBIENT TEMPERATURE' oc

APPLYING THE HA-4900 SERIES COMPARATORS
1.

SUPPLY CONNECTIONS: This device is exceptionally
versatile in working with most available power supplies.
The voltage applied to the V+ and V- terminals determines
the allowable input signal range; while the voltage applied
to the VL + and VL- determines the output swing. In
systems where dual analog supplies are available, these
would be connected to V+ and V-, while the logic supply
and return would be connected to VLogic+ and VLogic-.
The analog and logic supply commons can be connected
together at one point in the system, since the comparator
is immune to noise on the logic supply ground. A negative
output swing may be obtained by connecting VL+ to
ground and V L- to a negative supply. Bipolar output
swings (15V P-P, max.) may be obtained using dual supplies. In systems where only a single logic supply is available (+5V to +15V), V+ and VLogic+ may be connected
together to the positive supply while V-. and VLogicare grounded. If an input signal could swing negative with
respect the V- terminal, a resistor should be connected in
series with the input to limit input current to < 5mA
since the C-B junction of the input transistor would be
forward biased.

2-113

2.

UNUSED INPUTS: Inputs of unused comparator sections
should be tied to a differential voltage source to prevent
output "chatter". .

3.

CROSSTALK: Simultaneous high frequency operation of
all other channels in the package will not affect the output
logic state of a given channel, provided that its differential
input voltage is sufficient to define a given logic state
(L1VIN ~ ±Vosl. Low level or high impedance input lines
should be shielded from other signal sources to reduce
crosstalk and interference.

4.

POWER SUPPLY DECOUPLlNG: Decouple all power
supply lines with .01 J1 F ceramic capacitors to a ground
line located near the package to reduce coupling between
channneis or from external sources.

5.

RESPONSE TIME: Fast rise time « 200ns) input pulses
of several volts amplitude may result in delay times somewhat longer than those illustrated for 1OOmV steps. Operating speed is optimized by limiting the maximum differential input voltage applied, with resistor-diode clamping
networks.

APPLICA TIONS

r------------,

r----

------,

I
I

DIA

I
I
MEMORY

I
ANALOG
INPUTS
COMPARATORS

I
I
I

I
I

L ___________ ..1

INTERFACE

MICROPROCESSOR

I

L_________ __ J

ANALOG INPUT MODULE

PROCESSOR

DATA ACQUISITION SYSTEM

In this circuit the HA-4900 series is used in conjunction with a D to A converter to form a simple, versatile, multi-channel analog
input for a data acquisition system. In operation the processor first sends an address to the D to A, then the processor reads
the digital word generated by the comparator outputs.
To perform a simple comparison, the processor sets the D to A to a given reference level, then examines one or more comparator
outputs to determine if their inputs are above.or below the reference. A window comparison consists of two such cycles with
2 reference levels set by the D to A. One way to digitize the inputs would be for the processor to increment the D to A in steps.
The D to A address, as each comparator switches, is the digitized level of the input. While stairstepping the D to A is slower than
successive approximation, all channels are digitized during one staircase ramp.

+5.0V

TTL TO CMOS

CMOS TO TTL

LOGIC LEVEL TRANSLATORS

The HA-49'QO series comparators can be ,used as versatile logic interface devices as shown in the circuits
above. Negative logic devices may also be interfaced with appropriate supply connections;
If separate supplies are used for Vc and VLogic-, these logic level translators will tolerate several volts of
ground line differential noise.
"
'-

2-114

APPLICA TIONS (Continued)
Lt)

o
C\I
o
........
o
o
Q)

........

INPUT

>l.....- - - - - O HI

+10.

HI REF

O--I-i---I

LO REF

0--11-+--1

vcc

~
I

«
:I:

4.7K
3W

lK
51K

>1-+-----0
I

LO

L ______ ...JI
lK

0.:"":
WINDOW DETECTOR

The high switching speed, low offset current and low offset
voltage of the HA-4900 series makes this window detector
circuit extremely well suited to applications requiring fast,
accurate, decision-making. The circuit above is ideal for
industrial process system feedback controllers. or "outof-limit" alarm indicators.

RS-232 TO CMOS LINE RECEIVER

This RS-232 type line receiver to drive CMOS logic uses a
Schmitt trigger feedback network to give about 1 volt input
hysteresis for added noise immunity. A possible problem in
an interface which connects two equipments, each plugged
into a different AC receptacle, is that the power line voltage
may appear at the receiver input when the interface connection is made or broken. The two diodes and a 3 watt input
resistor will protect the inputs under these conditions.

+15V

,'>---_--0 VOH~4.2V
R2
2K

v+
IN914

-15V

"I

R2
150K

Rl

toon

150K

150K

Rl

-=-

I

-=-

'L
"-

F~

R3

13K

-15V

SCHMITT TRIGGER (ZERO CROSSING
DETECTOR WITH HYSTERESIS)

I

2.llfiCi

This circuit has a 100mV hysteresis which can be used in
applications where very fast transition times are required
at the output even though the signal input is very slow.
The hysteresis loop also reduces false triggering due to noise
on the input. The waveforms below show the trip points
developed by the hysteresis loop.

SDK

C1

-=OSCILLATOR/CLOCK GENERATOR

This self-starting fixed frequency oscillator circuit gives
excellent frequency stability. R1 and C1 comprise the
frequency determining network while R2 provides the
regenerative feedback. Diode 01 enhances the stability by
compensating for the difference between VOHand VSuppl y .
In applications where a precision clock generator up to
100kHz is required, such as in automatic test equipment,
C1 may be replaced by a crystal.

VaH

OV~~----------~L--

Input to Output Waveform
Showing Hysteresis Trip Points

2-115

________+J__

:;;~
o=>
uLJ..
0.• ....1

:;;0

«'"
0.1o~
u

HA-B002

mHARRIS
PRELIMINARY

Monolithic, Wideband, High Slew Rate,
High Output Current Buffer

Features

Applications

• Voltage Gain ................. ,...........................................0.995

• Line Driver

• High Input Impedance ....................................... 3000 KO

• Data Acquisition

• Low Output Impedance ............................................... 30

• 110MHz Buffer

• Very High Slew Rate ..................................... 1300Vltlsec

• High Power Current Booster

• Very Wide Bandwidth ......................................... 110MHz

• High Power Current Source

• High Output Current .......................................... ±200mA

• Sample and Holds

• Pulsed Output Current ....................................... ..400mA

• Radar Cable Driver

• Monolithic Construction

• Video Products

Description
The HA-5002 is a monolithic, wideband, high slew rate,
high output current, buffer amplifier.
Utilizing the advantages of the Harris 0.1. technologies,
the HA-5002 current buffer offers 1300V/tlsec slew rate
with 11 OM Hz of bandwidth. The ±200mA output current
capability is enhanced by a 3 ohm output impedance.
The monolithic HA-5002 will replace the hybrid LH0002
with corresponding performance increases. These characteristics range from the 3000K ohm input impedance to

Pinout

the increased output voltage swing. Monolithic design
technologies have allowed a more precise buffer to be developed with more than an order of magnitude smaller
gain error.
The HA-5002 will provide many present hybrid users with
a higher degree of reliability and atthesametime increase
overall circuit performance.
The HA-5002 is available in a-pin can, a-pin mini-dip, and
20-pin Lee packages.

Schematic
TOP VIEWS

VI+

IN

VI+

OUT

V2-

V2+

NC

NC

R9

RNI
R4

V2+

RI
QI

IN 4

VI'

OUT
OUT

Q2
QI5
V2'
RN3
VI'
IN

v"
2-116

Specifications HA-5002
Absolute Maximum Ratings (Note 1)

Operating Temperature Range

Voltage Between V+ and V- pins .................................. 44V
Input Voltage .......................................... Equal to Supplies
Output Current .................................. Continuous ±200mA
Output Curren!.. .................... (SOms On, 1s Off) ± 400mA
Internal Power Dissipation (Note 2)
TO-99 (+2S 0 C) ....................................................... 1.11W
Mini-DIP (+2S 0 C) .................................................. 1.B7W
LCC (+2S 0 C) .......................................................... 1.S1W

Maximum Junction Temperature ........................... +17So C
HA-S002-2 ....................................... -55 0 C ~ TA ~ +12S o C
HA-S002-5 ............................................ DoC ~ TA ~ +7S o C
Storage Temperature Range ........ -6S o C ~ TA ~ +1S0 0 C

Electrical Characteristics

VSUPPLY = ± 12V to ± 1SV, RS = SOIl,RL = 1Kll, CL = 10pF, unless otherwise specified.
OOC 10 +75 0 C

- 550C 10 +125 0 C

PARAMETER

TEMP

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

..:G

:;;2

0;;;:)

INPUT CHARACTERISTICS

C,,)LL

Offset Voltage
Avg. Offset Voltage Drift
Bias Current
Input Resistance
Input Noise Voltage (10Hz-1 MHz)

+2SoC
Full
Full
+25 0 C
Full
Full
+25 0 C

S
10
10
2
3.4
3
4

1.5

20
30

5
10
10
2
2.4
3
4

7
10
1.5

20
30
7
10

mV
mV
/lVioC
/lA
/lA
Mil
/lVp-p

TRANSFER CHARACTERISTICS
Voltage Gain (Note 7)
RL = 10011
RL=1KII
RL=1KII
-3dB Bandwidth (Note 4)
AC Current Gain

+25 0 C
+25 0 C
Full
+250 C
+2SoC

V/V
V/V
V/V
MHz

0.971
0.995

0.971
0.995
0.990

0.990
110
40

110
40

AlmA

±11.2
±13.9
±10.S
3
--_--QOUT

RL

o;tj
:;:;;::

0;:)

uu..

0........

:;:0

«'"
o..!z

00

SMALL SIGNAL WAVEFORMS

SMALL SIGNAL WAVEFORMS

= son

RS

RL = 100n

RL

RS

LARGE SIGNAL WAVEFORMS

LARGE SIGNAL WAVEFORMS

RS

= son
= 1Kn

= son

RS

= son

RL = 1Kn

RL = 1Kn

2-119

u

mHA.RRIS

HA-5033
Video Buffer

FEATURES

DESCRIPTION

•

DIFFERENTIAL PHASE ERRDR

0.1 0

•

DIFFERENTIAL GAIN ERROR

0.1%

•

HIGH SLEW RATE (i15V)

•

WIDE BANDWIDTH (SMALL SIGNAL)

•

WIDE POWER BANDWIDTH

•

FAST RISE TIME

•

HIGH OUTPUT DRIVE

•

WIDE POWER SUPPLY RANGE

•

REPLACE COSTLY HYBRIDS

The HA-5033 is a unity gain monolithic I. C. designed for any
application requiring a fast, wideband buffer. Featuring a bandwidth of 250MHz and outstanding differential phase/gain

1300V /J.1S

characteristics, this high performance voltage follower is an
excellent choice for video circuit design. Other features, which

250MHz
DC to 65MHz

include a minimum slew rate of 1000V/J.1 s and high output
drive capability, make the HA-5033 applicable for line driver
and high speed data conversion circuits.

3ns
i 10V WITH lOOn LOAD
i5VTO±16V

The high performance of this product is a result of the Harris
Dielectric Isolation process. A major feature of this process
is that it produces both PNP and NPN high frequency transistors which makes wide bandwidth designs,such as the HA5033, practical. Alternative process methods typically produce
PNP transistors of lower frequency response, which results in

APPlICA TIONS
•

VIDEO BUFFER

•

HIGH FREQUENCY BUFFER

•

ISOLATION BUFFER

a lower AC performance.
The HA-5033 is available in a 12 pin (TO-8) metal can or an
Spin epoxy mini-dip. The HA-5033-2 is specified over the military temperature range of -55 0 C to +1250C. The HA-5033-5
is specified over the commercial temperature range of OOC to

• HIGH SPEED LINE DRIVER
•

IMPEDANCE MATCHING

•

CURRENT BOOSTERS

•

HIGH SPEED A/D INPUT BUFFERS

+75 0 C.

PINOUTS

SCHEMATIC
TOPVIEWS

t--l'--+-i::: Q1
A11
~,+-oVOUT
A10

METAL CAN PACKAGE

MINI-DIP

2-120

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS (Note

CO)
CO)

1)

0

it)
I

Voltage Between V+ and V-pins
Input Voltage
Output Current (Peak)
Internal Power Dissipation (Note 2)
TO-8 (+25 0C)
Mini-dip (+250C)

40V
Equal to Supplies
±200mA

ELECTRICAL CHARACTERISTICS

PARAMETER

Maximum Junction Temperature
200 0C
Operating Temperature Range HA-5033-2 -55 0C9A$+125 0C
OOC$T A$+750C
HA-5033-5
Storage Temperature Range
-65 0C9A$+150 0C


(.)u...

INPUT CHARACTERISTICS
Offset Voltage
Average Offset Voltage Drift
Bias Current
Input Resistance
Input Capacitance
Input ~oise Voltage (Note 3)

c... ...J
:a; 0

+25 0C
Full
Full
+25 0C
Full
+25 0C
+25 0C
+25 0C

5
6
33
20
30
1.5
1.6
20

15
25

5
6
33
20
30
1.5
1.6
20

35
50

15
25
35
50

mV
mV
pV IOC
pA
pA
Mn
pF
pVp-p

TRANSFER CHARACTERISTICS
Voltage Gain RL = lOOn
RL=IKn
RL=lOon
-3dB Bandwidth

+25 0C
+25 0C
Full
+25 0C

.93

.93

250

250

V!V
V!V
V!V
MHz

Full
Full
+25 0C
+25 0C
+25 0C

±10
:tIl
:tl00
5
65

±10
:tll
:tl00
5
65

V
V
rnA
n
MHz

+250C
+25 0C
+250C
+25 0C
+250C
+250C
+25 0C

3
1
10
1.3
50
.1
.1

3
1
10
1.3
50
.1
.1

ns
ns
%
V/ns
ns
degrees
%

.99

.99

.92

.92

OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = lOOn
RL = 1Kn(Note 4)
Output Current
Output Resistance
Full Power Bandwidth (Note 5)
TRANSIENT RESPONSE
Rise Time (Note 6)
Propagation Delay
Overshoot
Slew Rate (Note 7)
Settling Time to .1%
Differential Phase Error}
Differential Gain Error (Note 8)

1.0

1.0

POWER REQUIREMENTS
Supply Current
Power Supply Rejection Ratio
Harmonic Distortion (Note 9)

+25 0C
Full
Full
+25 0C

21
21
54

25
30

21
21
54

<0.1

2-121

<0.1

25
30

rnA
rnA
dB
%

-""-0 OUT

IN

loon
-12

-15

..m:J

;:::Jr------------~~

L

INPUT
OV

OVERSHOOT

I

OUTPUT

I

I

I

NOTE: MEASURED ON 80TH POSITIVE
AND NEGATIVE TRANSITIONS.

RISE TIME

= 25 0 C, RS =50n, RL = 100r2

TA

+10V RESPONSE
TA

:;;0



.§. 6. 0
w

"~
<{

5. 0

o
>

4. 0

~
~

/'"

-

A

J..---

/ ~ ~ r-./jV
f.--- ~
,..."..

3. 0

..- V--

o
2. 0

DA: V+ = +1SV
B: V+ = +12V
V+ +10V
D: V+=+5V

v+= +10V V-=-10V

C,

D, V+ "" +5V
40

J

+40

+80

j=-SV -

+120

=

c:

A, V+ '" +15V v- '" -'5~_
8, V+= +12V V- '" -12V

1.0
80

8

c

v -= -1SV

v-

=-12V

v-= -lOV
v-" -5V

0.:""'=
:;d~

~5~5----~25~----~------~----~+1~2~5

o=>
uu..
c.:...J

+160

::;:0

300
±V"±15V

20

I - I-f-'"""

~ 600

'"

20

30

40

00

80

~

80

00

~

'OUT-mA

V-PARAMETER
MAGNITUDE Vs. FREQUENCY,

Y-PARAMETERS
PHASE VS. FREQUENCY

180

~
a:

~

...

90

Jil

vp..-

'-':: -

r-

46

w

0

:f"
~

-45

if

r-I'-

Ilr

136

-90

V22

rV12

V

-136
-180

106

107

,

'"

108
FREQUENCY - Hz

./

10'

FREQUENCY Hz

*SIEMENS ;;n-1

2-126

PERFORMANCE CURVES (Continued)
TOTAL HARMONIC DISTORTION VS. FREQUENCY

POWER SUPPLY REJECTION RATIO VS. FREQUENCY
~

70

±V=I±12V

:;; 60
os

eo

:i

50

""

z

0

~

0:

40
30

'j
~

i;l

ffi

:r"

0

.07

15
Z

.OS

0:

TA=+25 0 C -

~

0

.09

to

"0

~

....

""

.03

........

20

"

e- .01
o
e-

....



uLL.

c.: -'
:;:0

«D:

a..!2

TOTAL HARMONIC DISTORTION VS.
RMS INPUT VOLTAGE

00

u

1. 0

1

1

V

/

L

o

100 200 300 400

500 600 700 800 900

lK

LOAD RESISTANCE (OHMS)

OUTPUT SWING VS. FREQUENCY'
6. 0
±V = ±12V
RL == lOon

en

5, 5

"

0

±V =±15V
RL = lOon

~ ::5


2.S

~

2.0

w

-...

MINI-DIP

-...

0

NO HEAT SINK

r--

TO-SCAN

.~o

~

"lAT S'I

NK

e-

t::

=>

0

\

25

35

45

55

65

75

85

95

105 115

-

\

\
\

1.S

\.

1.0

o

10K

125

_

~~:!~~MS

NO HEAT SINKIN FREE AIR
-

\

......

.5
15

±vl±15v

lOOK

1M

10M

100M

1G

FREQUENCY (Hz)

AMBIENT TEMPERATURE loCI

*This curve was obtained by noting the output voltage necessary to produce an observable distortion for a given frequency. If higher
distortion is acceptable, then a higher output voltage for a given frequency can be obtained.
However, operating the HA-5033 with increased distortion {to the right of curve shown}, will also be accompanied by ah increase
in supply current. The resulting increase in chip temperature must be consider'ed and heat sinking will be necessary to prevent thermal
runaway.
This characteristic is the result of the output transistor operation. If the signal amplitude or signal frequency or both are increased
beyond the curve shown, the NPN, PNP output transistors w'ill approach a condition of being simultaneously on. Under this condition,
thermal ru naway can occur.

2-127

mHARRIS

HA·5101/5111

ADVANCE

Low Noise, High Performance
Operational Amplifiers

Features

Applications

• Low Noise ........................................ 3.5nV/VHz at 1KHz
• Wide Bandwidth .................................... 10MHz (Comp.)
60MHz (Uncomp.)
• High Slew Rate ...................................... .10V/JiS (Comp.)
30V/Jis (Uncomp.)
• Low Offset Voltage Drlft ...................................... 3JiV/OC
• High Gain ................................................. ,...... 6 x 106 V/V

• High Quality Audio Preamplifiers
•
•
•
•

High Q Active Filters
Low Noise Function Generators
Low Distortion Oscillators
Low Noise Comparators

• High CMRR/PSRR .................................................. 100dB
• High Output Drive Capability ................................ 30mA

Description
The HA-51 01 /5111 are dielectrically isolated operational
amplifiers featuring low noise and high performance.
Both amplifiers have an .excellent noise voltage density of
3.5nV/v'HZ at 1KHz. The uncompel']sated HA-5111 is stable at a minimum gain of ten and has the same DC specifications as the unity gain stable HA-5101. The difference
in compensation yields a 60MHz gain-bandwidth product
and a 30V/Jis slew rate for the HA-5111 versus a 10MHz
unity gain bandwidth and a 10V/Jis slew rate for the
HA-5101.
DC characteristics of the HA-5101/5111 assure accurate
performance. The 1mV offset voltage is externally adjustable and offset voltage drift is just 3JiV/OC. An offset current of only 30nA reduces input current errors and an
open loop voltage gain of 6 x 106V/V increases loop gain
for low distortion amplification.

The HA-5101/5111 are ideal for audio applications, especially low-level signal amplifiers such as microphone,
tape head, and phono cartridge preamplifiers. Additionally, it is well suited for low distortion oscillators, low
noise function generators, and high Q filters.
The HA-5101/5111-2 has guaranteed operation from
-55 0 C to +125 0 C and can be ordered as a military grade
part (HA-5101/5111-8). The HA-5101/5111-5 has guaranteed operation from OOC to 75 0 C. All devices are available
in ceramic mini DIP and TO-99 can packages. Additionally, the HA-5101/5111-8 is available in a 20 pin LCC
package and the HA-5101/5111-5 is available in a plastic
mini DIP package.

Schematic

Pinouts
TOP VIEWS

eACANC'~S *
IN

6

OUT

V

* HA-5101

2

+IN 3
4

1

+

V+

6 OUT
5 BALANCE

NC/HA-5111 Compensation

2-128

;J)

HARRIS

PRELIMINARY

HA·5102/04/12/14
Low Noise High
Performance
Operational Amplifiers

o::t
,...
~
,...
;;:

o

.........
N

o
,...
FEATURES

It)

DESCRIPTION

•

LOW NOISE

•

WIDE BANDWIDTH

8MHz (COMP.)
60MHz (UNCOMP.)

•

HIGH SLEW RATE

3V/IlS (COMP.)
20V/IlS (UNCOMP.)

Low noise and high performance are key words describing
HA-5102/04/12/14. These general purpose amplifiers offer
an array of dynamic specifications ranging from 3V 111 s slew
rate and 8MHz bandwidth (5102/04) to 20V/IlS slew rate and
60MHz gain-bandwidth-product (HA-5112/14l. Complementing these outstanding parameters is a very low noise specification
of 4.3 nV IVill at kHz.

4.3 nVA/HZ

•

LOW OFFSET VOLTAGE

•

SINGLE SUPPLY OPERATION

•

AVAILABLE IN DUALS OR QUADS

HIGH Q,ACTIVE FILTERS

•

AUDIO AMPLIFIERS

•

INSTRUMENTATION AMPLIFIERS

•

INTEGRATORS

•

SIGNAL GENERATORS

PINOUTS

0.5mV

This impressive combination of features make this series of
amplifiers ideally suited for designs ranging from audio amplifiers and active filters to the most demanding signal conditioning and instrumentation circuits.
These operational amplifiers are available in dual or quad form
with industry standard pinouts allowing for immediate interchangeability with most other dual and quad operational amplifiers.
HA-5102
Dual, Compensated
HA c 5112
Dual, Uncompensated
Quad, Compensated
HA-5104
HA-5114
Quad, Uncompensated

TOP VIEWS

,",~.,.
2

"

7

OUT

{

3·

+

v_

4

. 6}
+

:I:

o.:~
:::;;2

Fabricated using the Harris standard high frequency process,
these operational amplifiers also offer excellent input specifications such as 0.5mV offset voltage and 30nA offset current:
Complementing these specifications are 108dB open loop gain
and 108dB channel separation. Consuming a very modest
amount of power (90mW/package for duals and 150mW/package for quads). HA-5102/04/12/14 also provide the flexibility
of operating from a single +5V supply.

APPlICA TlONS
•

I

c(

IN

5

L-I._ _ _ _'-'-

HA-5104/14

HA-5102/12

2-129

'"'
3

0::>

uu..

c..-...J
:::;;0

«'"

c..!2;
00
u

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS

(Note 1)

TA = +25 0C Unless Otherwise Stated
Voltage Between V+ and V- Terminals
Differential Input Voltage
Input Voltage (Note 2)
Output Short Circuit Duration (Note 3)

Power Dissipation (Note 4)
Operating Temperature Range
HA-5102/5104/5112/5114-2
HA-5102/5104/511215114-5
Storage Temperature Range

40.0V
±.7V
±15.0V
Indefinite

880mW
-550C~TA~+1250C
OOC~TA~+750C

-650C~TA~+1500C

ELECTRICAL CHARACTERISTICS
V+= 15VDC; V-= -15VDC
HA-5102-2
HA-5104-2
HA-5112-2
HA-5114-2
0
0
-55 C to +125 C -55 0C to +125 0C
PARAMETER

TEMP

MIN

TYP MAX

MIN

HA-5102-5
HA-5112-5
OOC to +75 0C

HA-5104-5
HA-5114-5
OOC to +75 0C

TYP MAX MIN TYP MAX MIN TYP MAX

UNITS

0.5

mV
mV
/lV/DC
nA
nA
nA
nA

INPUT CHARACTERISTICS
Offset Voltage
Offset Voltage Average Drift
Bias Current
Offset Current
Input Resistance
Common Mode Range

+25 0C
Full
Full
+25 0C
Full
+25 0C
Full
+250C
Full
.±12

0.5
3
130
30

2.0
2.5

3
130

200
325
75
125

30

500

2.5
3.0

0.5
3
130

200
325
75
125

30

500

2.0
2.5

0.5
3
130

200
325
75
125

30

500

500

±12

±12

±12

lOOK 250K
86

lOOK 250K
86

lOOK 250K
86

2.5
3.0
200
325
75
125

k{l

V

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 5)
Common Mode Rejection Ratio (Note 6)
Small Signal Bandwidth
HA-5102/5104
Gain Bandwidth Product
HA-5112/5114AV= 10
Channel Separation (Note 7)

t25 0C
Full
lOOK 250K
Full
86
+25 0C
8
+25 0C
60
+25 0C
108

MHz

8
60
108

VIV
dB

60
108

60
108

MHz
dB

±13
i12
±15

V
V
mA

50
250
110

kHz
kHz

OUTPUT CHARACTERISTICS
Output Voltage Swing (RL = 10K)
(RL =2K)
Output Current (Note 8)
Full Power Bandwidth
(Note 9) HA-5102/5104
HA-5112/5114
Output Resistance

Full
Full
Full
+25 0C
+25 0C
+25 0C

:t12
±10
flO

±13
±12
±15

±12 :t13
:tl0 :t12
±10 ±15

50
250
110

50
250
110

2-130

±12
±10
il0

:t13
±12
±15
50
250
110

±12
±10
il0

n

SPECIFICATIONS

,..
........
N
,..
........
~

ELECTRICAL CHARACTERISTICS
V+

= 15VDC; V- = -15VDC

~

o

........
N

HA-5102-2
HA-51 04-2
HA-5112-2
HA-5114-2
-55 0C to +125 0C -55 0C to +125 0C
PARAMETER

HA-5102-5
HA-5112-5
OOC to +75 0C

HA-5104-5
HA-5114-5
OOC to +75 0C

II)
I

ct
J:

TEMP

MIN TYP MAX

+250C
+25 0C

50
38

100
60

50
38

100
60

50
38

100
60

50
38

100
60

ns
ns

0..:"":
::;:~

+25 0C
+25 0C

20
30

35
40

20
30

35
40

20
30

35
40

20
30

35
40

%
%

::;:0

MIN

TYP MAX MIN

o
,..

TYP MAX MIN TYP MAX

UNITS

TRANSIENT RESPONSE (Note 10)
Rise time
HA-51 02/51 04
HA-5112/5114
Overshoot
HA-5102/5104
HA-5112/5114
Slew Rate
HA-5102/5104
HA-5112/5114
Settling Time (Note 11)
HA-5102/5104
HA-5112/5114

+25 0C :';.1
+25 0C ±12

:!;3
±20

+25 0C
+25 0C

4.5
0.6

±1
±12

:!:1
±12

:!:3
±20

:!:1
:'::.12

±3
±20

:!:3
:'::.20

V/MS
V/Ms

4.5
0.6

4.5
0.6

4.5
0.6

MS
MS

17
4.3

17
4.3

17
4.3

17
4.3

nV/JHi
nV/VHz

5.1
.57

5.1
.57

5.1
.57

5.1
.57

pA/YHz
pAlVHZ

870

870

870

870

nVrms

NOISE CHARACTERISTICS
Input Noise Voltage
f= 10Hz
f = 1KHz
Input Noise Current
f= 10Hz
f = 1KHz
Broadband Noise Voltage
f= OCto-30KHz

+25 0C

)

+25 0C

+25 0C

POWER SUPPLY CHARACTERISTICS
Supply Current
HA-5102/5112
HA-5104/5114
Power Supply Rejection Ratio
(Note 6)

+25 0C
+25 0C
Full

3.0
5.0
86

5.0
6.5

3.0
5.0
86

2-131

5.0
6.5

3.0
5.0
86

5.0
6.5

3.0
5.0
86

5.0
6.5

mA
mA
dB

o=>
(..)LL.
0..- .....

--'--r-o OUT

J

I

1\

OUTPUT B

OV

'INPUT

VOLTS: Input A: .5V/Div., Output B: 5V/Div.
TIME: SOOns/Div.

TIME: SOns/Diy.

>+-t---o VOUT

2-132

-

-1

OV

.-

VOLTS: Input A: .OlV/Div" Output B: 50mV!Oiv,

I-=~i-,>---o TO
OSCILLOSCOPE

•
•
•

I T
1 'IT·

AU

SETTLING TIME CIRCUIT

2KH

-f

1

1
I

20011

·-l-t

-dds ll

AV = -I. IHA-5102l51041. "AV = -10 IHA-5112/51141
Feedback and summing resistors should be 0.1%
Clipping diodes are optional HP5082-2810 recommended.

SCHEMATIC

+v

l
f-

J

-<
[

J

L:

'I

~

1
1

J

~

~

H

J

-

[
/I

CI
v

~

'11

1

-v

~

-INPUT

+INPIiT

2-133

OUTPUT

mHARRIS HA·5130/35
Precision
Operational Amplifier

FEATURES

DESCRIPTION

•

LOWOFFSETVOLTAGE

•

LOWOFFSETVOLTAGEDRIFT

O.4)1V/OC

•

LOW NOISE

9nV/j!h

•

OPEN LOOP GAIN

10IiV

10 7

•

BANDWIDTH (UNITY GAIN)

•

ALL BIPOLAR CONSTRUCTION

2.5MHz

•

HIGH GAIN INSTRUMENTATION
PRECISION DATA ACQUISITION

A Super Beta input stage is combined with laser trimming, dielectric isolation, and matching techniques to produce 251-1 V (Max.) input offset voltage and O.4p V/oC input offset voltage average drift. Other features
enhanced by this process include 9nV (Typ.l Input Noise Voltage, 1nA
Input Bias Current, and 140dB Open Loop Gain.
These features coupled with 120dB CMRR and PSRR make HA-51301
5135 an ideal device for precision DC instrumentation amplifiers. Excellent input characteristics in conjunction with 2.5MHz bandwidth and
0.8V/I-I s slew rate, makes this amplifier extremely useful for precision
integrator and biomedical amplifier designs. These amplifiers are also
well suited for precision data acquisition and for accurate threshold detector applications.

APPLICATIONS

•

HA-5130/5135 are precision operational amplifiers manufactured using a
combination of key technological advancements to provide outstanding
input characteristics.

•

PRECISION INTEGRATORS

•

BIOMEDICAL AMPLIFIERS

•

PRECISION THRESHOLD DETECTORS

HA-5130/35 is packaged in an 8 pin (TO·99) can and an 8 lead Cerdip
and is pin compatible with many existing op amp configurations. The
HA-5135 is also available in a 20 pin LCC.
HA-5130/5135-2 is specified for -55 0 C to +125 0 C operation while
HA-5130/5135-5 operate from OOC to +75 0 C.

PINOUTS

SCHEMATIC
TOP VIEWS

BAL20" BALI
IN-

2

7

V+

IN+

3

6

OUT

v-

4

5

BAll

BAL 1

(80TH BAL 1 PINS ARE INTERNALLY CONNECTED)

2-134

SPECIFICA TlONS
ABSOLUTE MAXIMUM RATINGS

Lt)
CO)

(Note 1)

.......
C

TA ~ +25 0 C Unless otherwise stated
Voltage Between V+ and V- Terminals
Differential Input Voltage

Power Dissipation (Note 2)
Operating Temperature Range
HA-5130/5135-2
HA-5130/5135-5
Storage Temperature Range

40.0V
± 15.0V

Output Short Circuit Duration

Indefinite

300mW

,...

CO)

Lt)

-55 0C ~TA~ +125 0C
OOC~TA~+750C

I



uu..

c..-...J
:;;0

«a:

c..!2
u

00

TEST CIRCUITS
SLEW RATE AND TRANSIENT RESPONSE TEST CIRCUIT

SMALL SIGNAL RESPONSE
Vertical Scale: (Volts: 50mV/Diy. Output)
(Volts: 100mV/Diy. Input)
Horizontal Scale: (Time: lJ.1s/DiyJ

LARGE SIGNAL RESPONSE
Vertical Scale: (Volts: 5V/DiyJ
Horizontal Scale: (Time: 5ps/DivJ

\

\

INPUT

ov

"

:

ov

INPUT

OUTPUT

li

ov

V

OUTPUT

l/

I.......

"

SETTLING TIME CIRCUIT

+15V

2N4416

5Kfl

t-.-----(:) TO

5Kfl

OSCILLOSCOPE

--.--u

>-...

VOUT

= -1.

•

AV

•

Feedback and summing
resistors should be 0,1%.

• Clipping diodes are optional.
HP5082-2810 recommended.

2Kn

2-136

""

ov

PERFORMANCE CURVES
an

CO)

........
C)
CO)

,..

INPUT BIAS CURRENT vs.
DIFFERENTIAL INPUT VOLTAGE

INPUT OFFSET VOL TAGE.INPUT BIAS
AND OFFSET CURRENT vs. TEMPERATURE

anI

c(

::I:
80

~
w

~

0

70

""

'"

60

>
t;;

50

0

40

~

>~ 30

;::

20
10

o
-80

"\ ~

'""

~INPUT BIAS CURRENT

........

.....- ........
INPUT OFFSET CURRENT

;:::>- r---...
+40

-40

........

/""

............
r.......

V

~

a.:~

TYP~~ALIVOS

r

+80

:;;~
o=>

-6

-

uLL-

C.: -'

-4
+160

+120

-10

-8

-6

-4

-2

:;;0

10

«0::
o..!;z

DIFFERENTIAL INPUT VOLTAGE-VOLTS

TEMPERATURE oC

00

u

HA-5130 OFFSET VOLTAGE
STABILITY vs. TIME

bO~D\TI~JS

I I

VSUPPLY = ±15V

INPUT NOISE vs. FREQUENCY

I

Te = ±l OC
AV·= 1000

~ 10
5
0

~

NOTE: MEASUREMENT AND
ENVI RONMENT AL SYSTEMS
ALLOWED 12 HOUR STABILIZATION PERIOD.

-- - .... -

1 .4
1

~ 10

~

8

i'"

4

\

w

~
g
w
'"i5z

--

~

14
12

5

>~

0

\

NOISE vJL TAGE

~ECrENT

;::

246810

20

30
TIME-DAYS

........--

/

./

10

100

lK

10K

FREQUENCY - HZ

OPEN LOOP FREQUENCY RESPONSE
., 160

~
~

140
120

()O

'"'"

t--...'

~ 100

450

~

~

80

~

.......

60

GAIN

§
z

~

o

~ASEANGLE

........
........

40
20

"........

0

1350

~\

'\.

-20

1

.2

o

40

10

100

lK

10K

FREOUENCY -Hz

2-137

lOOK

1M

1BOo
10M

1

100K

PERFORMANCE CURVES (Continued)

CLOSED LOOP FREQUENCY RESPONSE
FOR VARIOUS CLOSED LOOP GAINS

SMALL SIGNAL BANDWIDTH AND
PHASE MARGIN vs. LOAD CAPACITANCE

6()0

80

!g 70

"-

Z· 60
50
1;40

9

30

d

10

z

a:

"''"

"' "-

w

.....:::.

1

10

100

10K

lK

PHASE MARGIN

C; 400

"-

"~ 20
-10

2.6

500

~

~

lOOK

::I
iE

-~

300

~

200

1"-

1M

10M

2.5

100

BANDWIDTH

1\\

FREQUENCY,Hz

00
10

100

1000

2.4

'\

2.35

10,000

LOAD CAPACITANCE-pF

OUTPUT VOLTAGE SWING vs.
FREQUENCY AND SUPPLY VOLTAGE
35
VSUPPL Y =

~

30

~
g

25

i"

~20V

VSUPPLY1±15~

I
20

VSUPPl, =

rov

w
"

~

15

g

10

§

5

~

lK

~ 30

Rl = 2K

~
~

~

"z

~\

~

25

1

VSUPPLY = +15/

20
5

\

I
VSUPP,Y = (5V

I

100

MAXIMUM OUTPUT VOLTAGE SWING vs.
LOAD RESISTANCE AND SUPPLY VOLTAGE

_\

tOOK

VSUjl Y = :tl0V

J

5

"-1'-

10K

f

0

/

~

10

1M

VSUprL Y = ±5V

100

lK

LOAD RESISTANCE-OHMS

FREOUENCY, Hz

NORMALIZED AC PARAMETERS
vs. SUPPLY VOLTAGE

ffi~

1. 1

~~

1.0

>- +,

"'w

BA~DWIIDTH

V1

~ ~ 0,9

II-~LEWRATE

~>

S ~ 0.8
~@
a: 0.7

<

"'~
a:~

~~

0.6 0

±2

±4

±6

:to

±to

±t2

+_14

+
_16

SUPPLY VOLTAGE - VOLTS

2-138

+
_18 ±20

10K

PERFORMANCE CURVES (Continued)

II)
('I)

PSRR

CMRR vs. FREQUENCY

VS.

FREQUENCY

o('I)

,..

140

140

..............

120

'"'" ~

100
80
80

40
20
0,

10

...........

120

100

II)
I

~

100
80

60

'"

lK

10K

FREQUENCY-Hz

.0

""

20
0

100K

01

c(

'" ""

100

10

lK

J:

"'- ~
10K

lOOK

FREQUENCY Hz

a.:t;

:;;:2
0::::J

uu..

POWER SUPPLY CURRENT VS.
TEMPERATURE AND SUPPLY VOLTAGE

SETTLING TIME FOR VARIOUS
OUTPUT STEP VOLTAGES

c.:-'
::;;0
eta:

c..!z

00

u

J
±1.21rt~S;;;+15V
htI

±1A

rLUl

10

10'"
wg

5

1-"
g~

0

i~

-5

"'I-

lil ..

vs=·J.!Ov·

10mV

I----: ~

!:;g-10
o
0

r- ~
10mV

2

•

~

~

:!:1.0

1mV

I

VS=+1QV

:t.R

1m)

:t.6

t""'" ~

•

12
6
·10
SETTLING TIME-ps

VS~+5V

"

,.

±.4

±.2
0
-80

-40

0

+40
TEMPERATURE

.....

+120

+160

oc

APPLYING THE HA-5130/5135 OPERATIONAL AMPLIFIERS
1.

2.

POWER SUPPLY OECOUPLING: Although not absolutely
necessary, it is recommended that all power supply lines
be decoupled with .011l F ceramic capacitors to ground.
Oecoupling capacitors should be located as near to the
ampl1fier terminals as possible.
CONSIDERATIONS FOR PROTOTYPING: The following
list of recommendations are suggested for prototyping.
Resolving low level signals requires minimizing leakage
currents cau~ed by external circuitry. Use of qual ity
insulating materials, thorough cleaning of insulating
surfaces, and implementation of moisture barriers
when required is suggested.

3.

When driving large capacitive loads (> 500pFl, as small
value resistor (~50
should be connected in series with
the output and inside the feedback loop.

4.

OFFSET VOLTAGE ADJUSTMENT: A 20 KD. balance
potentiometer is recommended if offset nulling is required.
However, other potentiometer values such as 10Kn, 50KD.,
and 100KSl may be used. The minimum adjustment
range for given values is±2mV.

5.

SATURATION RECOVERY: Input and output saturation recovery time is negligible in most applications. However, care should be exercised to avoid exceeding the
absolute maximum ratings of the device.

S.

DIFFERENTIAL INPUT VOLTAGES: Inputs are shunted
with back-to-back diodes for overvoltage protection.
In applications where differential input voltages in excess
of IV are applied between the inputs, the use of limiting
resistors at the inputs is recommended.

•

• Error voltages generated by theromocouples formed
between dissimilar metals in the· presence of temperature gradients should be minimized. Isolation of
low level circuitry from heat generating components
is recommended.
• Shielded cable input leads, guard rings, and shield
drivers are recommended for the most critical applications.

2-139

m

APPlICA TlONS
PRECISION INTEGRATOR

OFFSET NULLING CONNECTIONS

C
V+

---..,

I
I

I
I

R
OUT

I
I
I

OPTIONAL
,CONN ECTI ON

I

I
I
I

__ J

The excellent input and gain characteristics of HA5130 are well suited for precision integrator applications. Accurate integration over seven decades of
frequency using HA-5130, virtually nullifies the need
for more expensive chopper-type amplifiers.

• Although Rp is shown equal to 20k, other values such
as 50k, lOOk, and 1M may be used. Range of adjustment is approximately !2.5mV. Vos TC of the
amplifier is optimized at minimal VOS.

ZERO CROSSING DETECTOR

INPUT
OUTPUT

:':13V
RIN

2001's/DIV

~
INPUT

.:!:5mV
200I's/DIV.

,I .\

J

!

\

I

I,

I

I
I
1----- -./\N'----~

1

I'

I

~
I
I
I

_

I

J

RF

I

I

I

I

I

I

I

* OPTIONAL FOR

Low VOS coupled with high open loop Gain, high
CMRR, and high PSRR make HA-5130 ideally

OUTPUT SWING
LIMITING

suited for precision detector applications.

PRECISION INSTRUMENTATION AMPLIFIER (AV = 100)
2K

2K

2K

2-140

2K

II H.AR.RIS

HA·5134

'11::1"

C")
,....
It)

ADVANCED

«
J:
I

Precision Quad
Operational Amplifier

Features

Applications

•
•
•
•
•
•
•
•

•
•
•
•

Low Offset Voltage ........................................... Typ 25j.JV
Low Offset Voltage Drift ..........•..............•... Max 5j.JV/OC
Offset Voltage Match ................. Full Temp. Max 250j.JV
High Channel Separation ...................................... 120dB
Low Noise ......................................................... 7nV//HZ
Wider Bandwidth ..................................................... 4MHz
High CMRR/PSRR .................................................. 120dB
Dielectric Isolation

Instrumentation Amplifiers
State-Variable Filters
Precision Integrators
Threshold Detectors

• Precision Data Acquisition Systems
• Low-Level Transducer Amplifiers

a.:G

::;;:z

0::>

u'"
c..-....J
::;;:0

«a:

Description

c..!2;
00
u

The HA-5134 is a precision quad operational amplifier
that is pin compatible with the LT1014, OP11, RM4156,
and LM148 as well as the HA-4741. Each amplifier features guaranteed maximum values for offset voltage of
250j.JV, offset voltage drift of 5j.JV/OC, and offset current of
25nA over the full military temperature range while
CMRR/PSRR is guaranteed greater than 94dB and AVOL
is guaranteed above 250K V/V from -55 0 C to +125 0 C.
Precision performance of the HA-5134 is enhanced by a
noise voltage density of 7nV/.,[Hz at 1KHz, noise current
density of 2pAlVHZ at 1KHz and channel separation of
120dB. Each unity-gain stable quad amplifier is fabricated
using the dielectric isolation process to assure performance in the most demanding applications.

Pinouts

The HA-5134 is ideal for compact circuits such as instrumentation amplifiers, state-variable filters, and low-level
transducer amplifiers. Other applications include precision data acquisition, precision integrators, and accurate
threshold detectors in designs where board space is a
limitation.
The HA-5134-2 has guaranteed operation from -55 0 C to
+125 0 C and can be ordered as a military grade part
(HA-5134-8). The HA-5134-5 is guaranteed from OOC to
+75 0 C and all devices are available in ceramic dual-in-line
packages. The HA-5134-8 is also available in a 20 pin leadless chip carrier (LCC) package.

Schematic
TOP VIEWS
vee

2-141

{II

~RIS

HA-B141/42/44
Ultra-Low Power
Operational Amplifiers

Features

Applications

• Low Supply current ....................................... 45pA/AMP

• Portable Instruments

• Wide Operating Voltage Range ........................ 2V to 3V

• Meter Amplifiers

• Single or Dual Supply Operation

• Telephone Headsets

• High Slew Rate ..................................................... l.5V/ps

• Microphone Amplifiers

• High Gain ............................................................ 100kV/V

• Instru.mentation

• Unity Gain Stable
• "A" Suffix Devices Combine the Above Characteristics
with Perclsion Input Specifications
• Available in Singles, Duals and Quads

Description
The HA-5141/42/44 ultra-low power operational amplifiers provide AC and DC performance characteristics
similar to or better than most general purpose amplifiers
while only drawing 1/30 of the supply current of m6st
general purpose amplifiers. These amplifiers are well
suited to applications which require low power dissipation and good electrical characteristics.
The HA-5141/42/44 provides accurate signal processing
by virtue of their low input offset voltage (0.5mV), low
input bias current (45nA), high open loop gain (100kVIV)
and low noise, for low power operational amplifiers
(20nV/VHz). These characteristics coupled with a 1.5/ps

slew rate and a 400kHz bandwidth make the HA5141/42/44 ideal for use in low power instrumentation,

audio amplifier and active filter designs. The wide range
of supply voltages (2V to 30V) also allow these amplifiers
to be very useful in low voltage battery powered
equipment.
These amplifiers are available in singles (HA-5141, can or
Mini-Dip), duals (HA-5142, Can Mini-Dip or 20 pin LCG)
or quads (HA-5144, 14 pin Dip or 20 pin LCC) with industry standards pinouts which allow the HA-5141
15142/5144's to be interchangeable with most other operational amplifiers.

TOP VIEWS

N/C

IN+2

HA-5141

HA-5142

2-142

HA-5144

Specifications HA -5141/42/44
ABSOLUTE MAXIMUM RATINGS (Note 11
Voltage Between V+ and V- Terminals
Differential Input Voltage
Output Current
Internal Power Dissipation

40V
±7V
SIC Protected
500mW

Operating Temperature Range
Storage Temperature Range

OOCST AS+75 0 C
-55 0 CSTAS+125 0 C
-65 0 STAS.j.150 0 C

ELECTRICAL CHARACTERISTICS V+= 5V. V-= OV
HA-5141/42/44A -2 or-5
PARAMETER

TEMP.

MIN

TYP

MAX

0.5

HA-5141/42/44 -2 or-5
MIN

TYP

MAX

UNITS

2
5

2

6
B

mV
mV

INPUT CHARACTERISTICS
Offset Voltage (Note 12)

+250C
Full

a:G
:;:2
0:::>

Full

3

iN/oC

uu...
c.:-'
:;:0
.eta::

Bias Current

+250C
Full

45

75
100

45

100
125

nA
nA

oiS
u

Offset Current

+25 0C
Full

0.3

10
15

0.3

10
20

nA
nA

Common Mode Range

+25 0C
Full

Average Offset Voltage orift

3

ot04
ot04

oto 3.5
oto 3

V
V

Differential Input Resistance

+250C

0.6

Input Noise Voltage (f = 1kHz)

+250C

20

20

nVIjHz

Input Noise Current (f = 1kHz)

+25 0C

0.25

0.25

pA/..jHz

lOOK

V/V
V/V

105

MHz

Mn

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Notes 2,10)
Common Mode Rejection Ratio (Note B)
Closed Loop Bandwidth (Notes 2,3)

+25 0C
Full

50K
30K

Full

BO

lOOK

20K
15K
77

+25 0C

105

dB

OUTPUT CHARACTERISTICS

ot04

oto 3.5

Output Voltage Swing (Note 2)

+250C

Full Power Bandwidth (Note 4)

+250C

60

45

kHz

Output Current (Note 5)

+250C

+3
-O.B

+3
-O.B

mA
mA

Source
Sink

V

TRANSIENT RESPONSE (Note 7)
Rise Time (Notes 2.3)

+250C

Slew Rate(Notes 2,3)

+25 0C

Settling Time (Note 6)

+250C

10

+250C
Full

45

600
1.5

1

0.5

600

ns

1

V/}J.s

10

}J.'

POWER SUPPLY CHARACTERISTICS
Supply Current per Amplifier
Power Supply Rejection Ratio (Note 11)

Full

BO

65
75

105

50
77

105

BO
100

}J.A
}J.A

dB

NOTES:
Absolute maximum ratings are limiting values,
applied individually beyond which. the serviceability
of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied.

6.

2.

RL = 50kn

9. VOUT = 200MVPP

3.

CL = 50p!

4.

RL = 50kn; F'ull Power Bandwidth guaranteed
based on Slew Rate measurement using:
, HBW = Slew Rate
27TVPeak
Va = +3.5V (Source I. +1.5V (Sink)

10. VOUT = 1.0V to 3.5V NON "A", 0.7V to 4.0V for
"A" version.

1.

5.

7.

Settling Time i's measured to 0.1% of final value for
a 3V oulputstep and AV = -1.
Maximum'input slew rate = 10V/.s

B. 'VCM = OV to 3.5V

11. +VS = +5V to +15V
12. VO=1.4V

2-143

... 1-

HA-5141142144

TEST CIRCUITS
SLEW RATE AND TRANSIENT RESPONSE
TEST CIRCUIT

IN

U----\
~--~---e~--~-----(lOUT

LARGE SIGNAL RESPONSE

SMALL SIGNAL RESPONSE

Vertical Scale:

(Volts: Input = 5V/Div.)
. (Volts: Output = 2V/Div.)
Hori,zontal Seal!: I,Trme:' 2J.ls/Div.)

Vertical Scale:

(Volts: Input = 100mV/Div.)
(Volts: Output = 50mV/Div.)
Horizontal Scale: (Time: 2ps/Div.)

+VSUPPL Y = +15V, -VSUPPL Y = -15V

+VSUPPL Y = + 15V , -VSUPPL Y = -15V

Vertical Scale:

(Volts: Input = 100mV/Div.)
(Volts: Output = 50mV /Div.)
Horizontal Scale: (Time: 5J..Ls/Div.)

Vertical Scale:

(Volts: Input = 2V/Div.)
(Volts: Output =-1V/Div.)
Horizontal Scale: (Time: 5ps/Div.)

INPUT
INPUT

OUTPUT

OUTPUT

+VSUPPL Y = +5V, -VSUPPL Y = OV

+VSUPPL Y = +5V, -VSUPPL Y = OV

2-144

HA-5141142144
PERFORMANCE CURVES
Vs =±2.5V. TA =+25 0 C Unless Otherwise Stated

OPEN LOOP FREQUENCY RESPONSE
11 0

IIIIII
111111

100

'!l

90

~
~

~

CL = 50pF

0

GAIN

80

......
i

PHASE

50

g
ffi

20

1;

10

INPUT BIAS CURRENT

0

2 DO

70

40
30

24

DO

80

ill
~
o

INPUT OFFSET CURRENT AND BIAS
CURRENT VS. TEMPERATURE

II~~ .. 50kn

20
0
1

140

8

1
1200
1400
1
1BOO

Ie3 0

10

1K

100

10K

1M

100K

20

-r

4

0

-40 -20

"'0

20

FREQUENCY - Hz

40

60

TEMPERATURE -

BANDWIDTH AND PHASE MARGIN
VS. LOAD CAPACITANCE

J.

80

100

120

oc

NORMALIZED AC PARAMETERS VS.
SUPPLY VOLTAGE
1.6

1000'r-----r--,r-.-.-ro",------r--,--r-r-rTT"

R~.IJ.~

BANDWIDTH

8

INPUT OFFSET CURRENT

...

0
-1 0

1

I

00
000

RL = 50kH
CL =5Opf

1.1$l~

...r-~PH~A~S~EMfA~R=G~,Nr-+-+-r+~9F~~~-r--i--t-t-rttfioAi

1-.:..:.:::::..:r=:=i-+-+-+-l.JJJI---..
r---... r----.
I
•..I-----t---f-+-+-H-H+"""'.....::+--+--"I".....d-H+lO.3 ~
..... i'--~
400f-----+---jf-+-+-H+I-l-----+---+r-...-'''''''~!-++-+-JO.2 ~

....::::

/(

--

~

...-

BANDWIDTH

1/

~

2OOf-----+--1f-+-+-H+I-l-----+---l-!-+!-+++++lO.1 ~

lj

.•

0.4

OO,~O-----L---L~~-L~~,~O~O-----L--J--L-L-LLL,~OOO
LOAD CAPACITANCE - pF

• • •

•

± 3 4 ,±± e ± 7

10

SUPPLY VOLTAGE -VOLTS

OUTPUT VOLTAGE SWING VS.
FREQUENCY AND SINGLE SUPPLY
VOLTAGE
NORMALIZED AC PARAMETERS VS.
TEMPERATURE

14

i
5:>

VSrLr"m

RL = s!kn

JJ1U

12
10

I

'Z"

.~
~

8

6

g
~
15

VSUPPl Y .. +5V

VSJpPL~ •~3~

4

o

lK

vsrTi'i"i
10K

1. 2

~
... "1

~

~~:~~

.

~
'\ ~
"~~

SLEW RATE

r-..

...o~ 0, ,
~

....-

-

-r-..

o.8

~~ o.7

•

O.

-60
100K

BANDWIDTH

"~ 1.0

1M

FREQUENCY - Hz

2-145

-40

-20

-

10

20

40

TEMPERATURE -

60

oc

80

100

120

HA-5141142144

PERFORMANCE CURVES (continued)
MAXIMUM OUTPUT VOLTAGE SWING
VS. LOAD RESISTANCE AND SINGLE
SUPPLY VOLTAGE
INPUT NOISE VS. FREQUENCY
10,000

1000

0

~
o

"'

>,

1

~"
NOISE VOLTAGE

1

.g
"~

,0

1

5

1o
100K

1111111
lK

100

I
/

10

~

1

10'

VSUPPL Y '" +2DV

4

12

w

NJ,.~ ~W~I~NT '"

......

/'

6

"r

VSUPPLY - +10V

I

",

~

8

6

V'OP~L Y ! +5~

4

V'UP~L Y ! +iv
~

FREQUENCY - Hz

lK

100

10K

100'

LOAD RESISTANCE - OHMS

PSRR AND CMRR

VS. FREQUENCY

POWER SUPPL Y CURRENT VS.
TEMPERATURE AND SINGLE SUPPLY
VOLTAGE

140

120

I'-....

100

ao

~

.......

~

III r-....
,ao
a:
a:

w

~60

~

+PSRR CMRR

ill

r-...

~

0

""
~

20

~

10

it

i'lK

100K

10K

I-.".,.-

vl.=+.I,v
V5 .. +6\1

./"

/

--

-60

1M

-40

'lis" +2V

I--

-20

20

-140

--

-120

-100

lOOKn
~

1Kn

r-r-

VOl

~

~-"'oo,~"

)

lKH

-

100

.... 1"-

,.n

-

o

-

.

I

'V
0-

-20

40

60

TEMPERATURE - OC

CHANNEL SEPARATION VS. FREQUENCY

...

-

I

~I

,.n

•

V02

IIIIIII,. I I II
FREQUENCY - Hz

2-146

10.

/'

,/"

FREQUENCY - Hz

:..0

"S~~3"

a: 3

.......
100

:1

.. 4

.......

0

0
10

---

§ 80
;~ 50

iffiR~

.......

~

70

lOOK

80

100
,.

120

140

HA-5141142144
o::t
o::t

SCHEMATIC

........
N

o::t

........
,...
o::t
,...
Lt)
I


uu..
a..-...J

:;;:0

«1=

~~--~------~--~----------~

2-147

__~~____~~_v

a..z
00
u

m~RIS

HA·5147

PRELIMINARY

Ultra-Low Noise Precision Hi.gh Slew Rate
Wideband Operational Amplifiers

Features

Applications

• High Speed .......................................................... 35VIIls

• High Speed Signal Conditioners

• Wide Gain Bandwidlh ..................................... 120 MHz

• Wide Bandwidth Instrumentation Amplifiers

• Low Noise ..................................... 3 nVI

.;Hz al1

KHz

• Low Level Transducer Amplifiers

• Low VOS ................................................................. 10llV

• Fast, Low Level Voltage Comparators

• High CMRR ......................................................... 126 dB

• Highest Quality Audio Preamplifiers

• High Gain ...........................••.........•................ 1800V/mV

• Pulse/RF Amplifiers

Description
The HA-5147 monolithic operational amplifier features an
unparalleled combination of precision DC and wideband
high speed characteristics. Utilizing the Harris D. I. technology and advanced processing techniques, this unique
design unites low noise (3 nV/v'Hz) precision instrumentation performance with high speed (35V/IlS) wideband
capability.
This amplifier's impressive list of features include low
Vos (10 IlV), wide gain-bandwidth (120 MHz), high open
loop gain (1800V/mVj, and high CMRR (126dB).
Additionally, this flexible device operates over a wide
supply range (±5V to ±20V) while consuming only
140 mW of power.

Pinouts

This device is ideally suited for low level transducer signal
amplifier circuits. Other applications which can utilize the
HA-5147's qualities include instrumentation amplifiers,
pulse or RF amplifiers, audio preamplifiers, and signal
conditioning circuits.
This device can easily be used as a design enhancement
by directly replacing the 725, OP25, OP06, OP07, OP27
and OP37 where gains are greater than ten. The HA-5147
is available in TO-99 metal can, both epoxy and ceramic
8 pin mini-DIPs, as well as 20 pin LCC packages.

Schematic
TOP VIEWS

.It:
om

BALANCE

BALANCE~B
-IN 2

-

+IN 3

+

V' 4
V-leASEI

Using the HA-5147 allows designers to minimize errors
while maximizing speed and bandwidth in applications
requiring gains greater than ten.

BALANCE

1 V+
~

OUT

5 NC

l '''

I ..
lOl'U

K~'

CJ

,."'l

L ..

...
ani

."

j:

-r--W-r-r~''''-'I+---+-r-:':r~r-I "I I
..
t c¥ . . ,,~'~ ~.u ... t---I--*;-~'"
l'{J" ~r" ~'''.

:,:'

-----1:;".

'n ""

f;,~'h

'.'"

.;!l f:,~

~r' ",,~,

....~. ...
~ "

2-148

f{ii
'n."

;;.-"_'_r.:'-K'H "

t--"'"",'"'----K

Specifications HA -5147
Absolute Maximum Ratings (Note 1)

=

V+

=1SV, V-

II)
I

HA-S147-2,8 ............................... -SSOC:5 TA:5 +12S o C
HA-S147 -S ........................................ OOC:5 TA:5 +7So C
Storage Temperature Range ..... -6So C:5 TA:5 +1S0o C

«::I:

= -1SV, CL :5 10pF, Rs = 100n

HA-S147A
PARAMETER

'I"'"

Operating Temperature Ranges:

T A +2S o C Unless Otherwise Stated
Voltage Between V+ and V- Terminals .................. ±22V
Differential Input Voltage (Note 2) ........................ ±0.7V
Internal Power Dissipation .................................. SOO mW
Output Short Circuit Duration ......................... Indefinite

Electrical Characteristics

....

•

TEMP

MIN

HA-S147

TYP

MAX

10
30
0.2
t10
±20
7
15
11.5
6
0.08

25
60
0.6
±40
±60
35
50

MIN

TYP

MAX UNITS

100
300
1.8
±80
±150
75
135

.18

30
70
0.4
U5
±35
12
30
11.5
4
0.09

3.5
3.1
3.0

5.5
4.5
3.8

3.8
3.3
3.2

8.0
5.6
4.5

1.7
1.0
0.4

4.0
2.3
0.6

1.7
1.0
0.4

INPUT CHARACTERISTICS
Offset Voltage
Average Offset Voltage Drift
Bias Current
Offset Current
Common Mode Range
Differential Input Resistance (Note 3)
Input Noise Voltage
0.1 Hz to 10 Hz (Note 4)
Input Noise Voltage Density (Note 5)
fO = 10 Hz
fO = 30 Hz
fO = 1000 Hz
Input Noise Current Density (Note 5)
fO = 10 Hz
fO=30Hz
fO = 1000 Hz

+25 0 C
Full
Full
+25 0 C
Full
+25 0 C
Full
Full
+25 0 C
+25 0 C

...:!j

10.3
1.5

10.3
0.8

0.25

+25 0 C

/lV
/lV
INIOC
nA
nA
nA
nA
V
Mn
/lVp-p
nVljHz

+25 0 C

PAlfoZ

0.6

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 6)
Common Mode Rejection Ratio (Note 7)
Gain Bandwidth Product fO = 10 kHz
(Note 3)
fO = 1 MHz

+25 0 C
Full
Full
+25 0 C
+25 0 C

1000
600
114
120

1800
1200
126
140
129

700
300
100
120

1500
800
120
140
120

VlmV
VlmV
dB
MHz
MHz

+25 0 C
Full
+25 0 C
+25 0 C

±10.0
±11.7
445

±11.5
13.8
500
70

±10.0
±11.4
445

±11.5
13.5
500

V
V
kHz

70

n

OUTPUT CHARACTERISTICS
Output Voltage Swing RL = 600 n
RL = 2K n
Full Power Bandwidth (Note 8)
Output Resistance,Open Loop
TRANSIENT RESPONSE (Note 9)
Rise Time
Slew Rate (Note 11)
Setting Time (Note to)
Overshoot

+25 0 C
+25 0 C
+25 0 C
+25 0 C

28

22
35
400
20

50
28
40

22
35
400
20

40

ns
VI/ls
ns
%

4.0
51

mA
mA
/lV/V

50

POWER SUPPLY CHARACTERISTICS
Supply Current
Power Supply Rejection Ratio (Note 12)

3.5

3.5

+25 0 C
Full
Full

2

2-149

4.0
4

16

:Ez
0:;:)
uLL.
a.:....J
:EO

~~
00
u

HA-5147
NOTES:
1.

Absolute maximum ratings are limiting values, applied individually,
beyond which the serviceability of the circuit may be impaired.

Fl,mctional operability under any of these conditions is not necessarily
implied.
2.

For differential input voltages greater than O.7V, the input current must
be limited to 25 mA to protect the back-to-back input diodes.

3.

This parameter value is based upon design calculations.

7.

VCM = ±10V

8.

FuJI power bandwidth guaranteed based on slew rate measurement

Slew Rate
using: FPBW = - - 2" VPEAK
9.

Refer to Test Circuits section of the data sheet.

4.

Refer to Typical Performance section of the data sheet.

10. Settling time is specified to 0.1 % of final value fora 1OVoutput step and
Av=-10.

5.

Sample tested.

11. VOUT = 10V Step

6.

VOUT = ±10V, RL = 2K !l

12. Vs = ±4V to ±18V

Test Circuits
LARGE AND SMALL SIGNAL RESPONSE
TEST CIRCUIT

IN

OUT

LARGE SIGNAL RESPONSE

SMALL SIGNAL RESPONSE

(Volts: Input ~ O.SV/Oiv.)
(Volts: Output ~ 5V/Oiv.)
Horizontal Scale: (Time: SOOns/Oiv)

Vertical Scale:

(Volts: Input ~ 10mV/Oiv)
(Volts: Output ~ 1OOmVIOiv)
Horizontal Scale: (Time: 100ns)

Vertical Scale:

2-150

HA-5147

"o:::r
,....

Test Circuits (continued)

It)
I

«

:I:

SETTLING TIME TEST CIRCUIT
+15V

500£1

o AV=-10
• Feedback and summing
resistors should be 0.1%
• Clipping diodes are optional.
HP5082-2810 recommended.

200£1

'Kll

c..:G

:;;:2

0::>

u LL
a..--I

:;;:0

SUGGESTED OFFSET VOLTAGE ADJUSTMENT

V+

.,-; C?ffset adjustment range is
approximately ±4mV.

SUGGESTED STABILITY CIRCUITS

Low resistances are preferred for 'low noise applications as a 1Kn resistor
has 4 nVJHz of ther~al noise. Total resistances of greater than 10KO: on
either input can reduce stability. In most high resistance applications, a
few picofarads of capacitance across the feedback resistor will improve
stability.

2-151



10

100

FREQUENCY (Hz)

2-152

1000

HA·5151/52/54
PRELIMINARY

Low Power
Operational Amplifiers

Features
•
•
•
•
•
•
•

Applications

Low Supply Current .......................... < 200/JA/Amplifler
Dual Supply Voltage Range ...................... ±1V to ±15V
Single Supply Voltage Range ......................... 2V to 30V
Full Power Bandwidth ........................................... 80KHz
Low VOS Drift .......................................................3/JV/OC
Low Noise ....................................................... 15nV/v'Hz
Dielectric Isolation

•
•
•
•
•
•

Portable Instuments
Meter Amplifiers
Telephone Headsets
Microphone Amplifiers
Remote Sensor/Transmitter
Battery Powered Equipment

Description
The HA-5151/52/54 series is a group of dielectrically
isolated bipolar amplifiers designed to provide excellent
AC performance while drawing less than 200/JA of supply
current per amplifier. These unity gain stable amplifiers
are especially well suited for portable and lightweight
equipment where available power is limited.
The HA-5151/52/54 series combines superior low power
AC performance with DC precision not usually found in
general purpose amplifiers. The DC performance is centered around low input offset voltage (0.5mV), low offset
voltage drift (3/JV/0C), and low input bias current (70nA).
This is combined with a very low input noise voltage of
15nV/v'RZ at 1KHz.
The AC performance of the HA-5151/52/54 series
surpasses that of typical low power amplifiers with 4.5V/
/Jsec slew rate and a full power bandwidth of 80KHz. This

Pinouts

makes the HA-5151/52/54 series an excellent choice for
virtually all audio processing applications as well as remote sensor/transmitter designs requiring both low
power and high speed. The suitability of the HA-5151/52/54 series for remote and low power operation is
further enhanced by the wide range of supply voltages
(±1V to ±15V) as well as single supply operation (2V to
30V).
These amplifiers are available in singles (HA-5151, can or
mini-dip), duals (HA-5152, can, mini-dip or 20 pin LCC) or
quads (HA-5154, 14 pin dip or 20 pin LCC), as well as over
both the commercial (OOC to +75 0C) and military (-55 0C
to +125 0C) temperature ranges. These amplifiers also
carry industry standard pinouts which allow the
HA-5151/52/54's to be interchangeable with most otHer
operational amplifiers.

TOP VIEWS
OUT 1

V+

Ne

v-

v+
OUT4

OUT

,..

IN-1

.

,

OUT

OUT2

INtl

•

IN+2

HA-5151

} INPUTS 3

HA-5152

2-153

HA·5154

Specifications HA-5151 /52/54
Absolute Maximum Ratings (Note 1)

Operating Temperature Range

Voltage Between V+ and V- Terminals ........................ 40V
Differential Input Voltage ............................................. ±7V
Output Curren!.. ........................................... SIC Protected
Internal Power Dissipation ...................................... 500mW

HA-5151/52/54-5 ................................. OoC:S TA:S +75 0 C
HA-5151/52/54-2 ............................ _55 0 C:S TA:S +125 0 C

Electrical Characteristics

Storage Temp. Range ................... -65 0 C:S T A :S <-1500C

V+ ~ 15V, V- ~ -15V, RS ~ 1O0ll, CL:S 10pF unless otherwise specified.

PARAMETER

TEMP

-550 e
MIN

::; TA ::; +1250 e
TYP

MAX

0.5

2

ooe::; TA::; +75 0 e
MIN

TYP

MAX

2

3

mV

4

mV

150

/lV/oC
nA

250

nA

30

nA

50

nA

UNITS

INPUT CHARACTERISTICS
Offset Voltage

+25 0 C

Full

3

Average Offset Voltage Drift
Bias Current

Full

3

+25 0 C

70

Offset Current

+25 0 C

3
250

Full
10

Differential Input Resistance
Input Noise Voltage (f ~ 1 kHz)
Input Noise Current (I = 1 kHz)

Full
+25 0 C

10

30
50

Full
Common Mode Range

70

150

V
m!l

±10

±10

1.5

1.5

+25 0 C

14.8

14.8

nV/~

+25 0 C

0.25

0.25

pA/,JHZ

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Notes 2, 4)
Common Mode Rejection Ratio (Note 7)
Bandwidth (Notes 2, 3)

+25 0 C

50K

100K

100K

V/V

Full
Full

25K

50K

2SK

SDK

V/V

80

105

80

105

dB

1.3

MHz

+25 0 C

50K

1.3

OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 2)
Full Power Bandwidth (Note 2, 4, 8)

+25 0 C

80

80

V
kHz

Output Current

+25 0 C

±3

±3

mA

Full

±10

±10

TRANSIENT RESPONSE (Notes 2, 3)
Rise Time

+25 0 C

Slew Rate (Note 6)
Settling Time (Note 5)

+25 0 C

300
2

4.5

2

+25 0 C

5

+25 0 C

200

300

ns

4.S

V/lS

5

/ls

POWER SUPPLY CHARACTERISTICS
Supply Current
Power Supply Rejection Ratio (Note 9)

Full

200

250
275

Full
105

80

80

250

/lA/Amp

275

/lA/Amp

105

NOTES:
1.

2.
3.
4.
5.

Absolute maximum ratings are limiting values, applied individually
beyond which the serviceability of the circuit may be impaired.
Functional operability under any of these conditions is not necessarily implied.

RL
CL

~

6.

Maximum input slew rate'" 30V/j.1sec.

7.

VCM

8.

Full Power Bandwidth is guaranteed by equation:

Full Power Bandwidth =

10kO
100pF

VO' ±10V

±10V.

9. :"VS

Settling Time is specified to 0.1% of final value for a 10V output

step and AV = -1.

2-154

=

±5V.

Slew Rate
2 IT V Peak

dB

HA-5151/52/54

o::r

II)

Test Circuits

.........
N
II)
.........

SLEW RATE AND TRANSIENT
RESPONSE TEST CIRCUIT

INu----I

,....
II)
,....
II)

>-___

~_e.--_e--_n

OUT

I

c(

:I:

a.:t;
::;;;2

LARGE SIGNAL RESPONSE

SMALL SIGNAL RESPONSE

(Volts: Input ~ 5V/Diy.)
(Volts: Output = 2V/Diy.)
Horizontal Scale: (Time: 5I's/Div.)

Vertical Scale:

Vertical Scale:

(Volts: Input = 100mV/DiY.)
(Volts: Output = 50mV/Diy.)
Horizontal Scale: (Time: 51's/DiY.)

INPUT
INPUT

OUTPUT

OUTPUT

+VSUPPLY

=+15V. -VSUPPLY =-15V

+VSUPPLY = +15. ,VSUPPLY = -15V

(Volts: Input ~ 1V/Diy.)
(Volts: Output = 1V/DiY.)
Horizontal Scale: (Time: 51's/DiY.)

Vertical Scale:

(Volts: Input = 100mV/DiY.)
(Volts: Output = 50mV/DiY.)
Horizontal Scale: (Time: 51's/DiY.)

Vertical Scale:

INPUT

INPUT

OUTPUT

OUTPUT

+VSUPPLY

=+5V. -VSUPPLY =OV

+VSUPPLY = +5V. -VSUPPLY = OV

2-155

o=>
u"-

C.:-'

::;;;0

«0:

c.!2

00

u

HA-5151/52/54
Schematic

t---+---w-D OUTPUT

2-156

HA-5160/62

m1~RIS

Wideband, JFET Input
High Slew Rate, Uncompensated
Operational Amplifier

FEATURES

N
CD

o

CD
,...

It)
I

«
::I:

DESCRIPTION

•

WIDE GAIN BANDWIDTH

100MHz

•

HIGH SLEW RATE

120V/~s

•

SETTLING TIME (0.2%)

•

POWER BANDWIDTH

•

OFFSET VOLTAGE

•

BIAS CURRENT

280ns
1000kHz
1.0mV
20pA

APPlICA TIONS
•

VIDEO AND RF AMPLIFIERS

•

DATA ACQUISITION

•

PULSE AMPLIFIERS

•

PRECISION SIGNAL GENERATION

The HA-5160/5162 is a wideband, uncompensated, operational amplifier
manufactured with FET/Bipolar technologies and dielectric isolation. This
monolithic amplifier features superior high frequency capabilities further
enhanced by precision laser trimming of the input stage to provide excelent input characteristics. This device has excellent phase margin at a closed
loop gain of 10 without external compensation.
The HA-5160/5162 offers a number of important advantages over similar
FET input op amps from other manufacturers. In addition to superior
bandwidth and settling characteristics, the HAR RIS devices have nearly
constant slew rate, bandwidth, and settling characteristics over the operating
temperature range. This provides the user predictable performance in
applications where settling time, full power bandwidth, closed loop bandwidth, or phase shift is critical. Note also that HAR RIS specified all parameters at ambient (rather than junction) temperature to provide the designer
meaningful data to predict actual operating performance.
Complementing the HA-5160/5162's predictable and excellent dynamic
characteristics are very low input offset voltage, very low input bias current,
and extremely high input impedance. This ideal combination of features make
these amplifiers most suitable for precision, high speed, data acquisition
system designs and for a wide variety of signal conditioning applications.*
The HA-5160 provides excellent performance for applications which require
both precision and high speed perfornance. The HA-5162 meets or exceeds
the performance specifications of National's hybrid op amp, the LH0062.
* -2 denotes a range of -55 0 C to +125 0 C and -5 denotes a OOC to +75 0 C
range.

SCHEMATIC

PINOUT

COMPENSATION

TOP VIEW

vCase connected to V-

2-157

n:G

:::;;2

o=>
uu..
c..-...J

:::;;0


uu..

a.:2;0
.
 -=~200n

-=
LARGE SIGNAL RESPONSE
Vertical Scale: (Volts: A = O.5V/Div., B = 5V/Div.)
Horizontal Scale: (Time: 500ns/Div.)

SMALL SIGNAL RESPONSE
Vertical Scale: (Volts: A = 10mV/Div., B = 100mV/Div.)
Horizontal Scale: (Time: 1OOns/Div.)

I\.

A

OUTPUT B

I
I

OV

1
\

il

OUTPUTB

II
INPUT A

.I

"

OV

OV

~

INPUT A

OV

SETTLING TIME CIRCUIT

*~*~
...500

5k

...
v

YVV

+15V ~.

~K
VINO

;O~

... 7

~

-15V
,..

+15V
TO
~ClllOSCOPE

.. 2N4416

~

2k~
~

=.~2N4416
- ~3k

50j:"
pF

AAA

v;kY

2-159

"'VOUT

• AV=-10
• Feedback and summing
resistors should be 0.1% .

*

Clipping Diodes are optional.

HP5082-2810 recommended.

PERFORMANCE CURVES

INPUT OFFSET VOLTAGE AND
BIAS CURRENT VS. TEMPERATURE

OPEN LOOP FREQUENCY RESPONSE
+2.50

110

iii

+2.0

4K

+1.5
OFFSET VOLTAGE

3K

;;

+1.0

!

w

+0.50 ~
I-

....

g
.,wI-

+0.0
-0.50
BIAS CURRENT

.......
-40

-80

+40
+80
TEMPERATURE (OC)

It
0

1.0

80

'"w

70

I-

50

40
30

PHASE

zw

20

I

~

\

1

100

lK

10K

lOOK

+120

iii 90

:s

+ 10V

z

80

'w"
«
'"
!:;

70

:;;:

M

---........ \

~

30

..

10

~

r"--.

10M

100M

I

""'-

50pF

lOOK
FREOUENCY (Hz)

1M

2-160

,

100

lK

10K

lOOK

JOOF-

P

IV'

,"",-"

0

10M

100pF -

"" "'' -'

20

-10
10

OpF

""'- 1"",-"",-"
~" V "- /'
""'- ~/ "-X
.""'-" K

50

g
zw

~~

60
40

g

~

FREQUENCY (Hz)

10K

l\.
1\ \.

OPEN LOOP FREQUENCY RESPONSE
FOR VARIOUS BANDWIDTH CONTROL
CAPACITANCES
100

5

lK

1M

1350

FREQUENCY (Hz)

f\

0

VLpPLY=±7V

"- ~

1

10

~

450

-2.0
+160

'\

0

f'...

............

110

VSUPPLY = ±15V

5

.........

0

.g

-10
10

.-........

VLpPLY -

~

00

GAIN

....
>

0

VSUPPLY = ±20V

30

......

60

51

OUTPUT VOL TAGE SWING
VS.FREQUENCY
35

" '" "-

90

z
:;;:

-1.50

1/1

o

100

:s

t-..

-

\.

:::--..." '\.\.

1M

,'"

10M

100M

PERFORMANCE CURVES (Continued)

N

(0

o

(0
,....

It)
I

NORMALIZED AC PARAMETERS
VS. TEMPERATURE

INPUT NOISE VOLTAGE AND
NOISE CURRENT VS. FREQUENCY
160
140
120

~1:

"'' ' "'''-

~60 I'.
40

'\.'\.

10

0.5

/NPUT NOISE CURRENT

--.........

0.2

1K
FREQUENCY (Hz)

CJ

~

!

~

1'."

~
f";:

0.7

>

0.6

...0

lOOK

,

~ B~NDWfoTJ

0.8

..:3

o

10K

0.9

.....~

0.1

I
100

0.4
0.3

20

1.0

0.6

/SOURCE RESISTANCE = on

""- K'~/

~ ~SLEWRATE

0.7

SOURCE RESISTANCE = l00Kn
/

1.1

0.8

I

R\.

«~

a,:t-=
:;;:~

BANDWIDTH

0.5

~

I

+40

+80

o=>
UU-

0.4

-SO

0..-....1

o

-40

+120

+160

TEMPERATURE (OC)

:;;:0

«ex:

o..~

00

u

OUTPUT VOLTAGE SWING
VS. LOAD RESISTANCE

SETTLING TIME FOR VARIOUS
OUTPUT STEP VOLTAGES
+10

14
~ 12

co

~ 10

~

W

~
~

~

:=

5

NEGATIVE SWINY........-

8
6

4
2

V

V

~

~+5

V

L ~T1VE
~

~

W

co

~

SWING -

...~

~

~ -5

o
200

0

400

600

BOO

10mV

/
~

10mV

lK

LOAD RESISTANCE (n)

100

2-161

V
~

400
200
300
SETTLING TIME (nsl

500

600

PERFORMANCE CURVES (Continued)

POWER SUPPLY REJECTION
RATIO VS. FREQUENCY

COMMON MODE REJECTION
RATIO VS. FREQUENCY
100

~
I-

z
o
~

I'-...

300pF

-~

...

...,

'~S40
ii! 0
ffi
~ 20

...

+

o

1

10

100

lK

10K

80~--_r----~--_r~~~

~~
>-::!. 60

-

-

1oo,---,-----,---,-----l----,----,

lOOK

300pF

FREOUENCY Hz

8.8,-----,------.-----,--------,----==--"'-------,

8.5 ~----+__----_b_"'--'t_=-"""-"'=-::;..f~--__l

1
I-

8.0 ~-----/-+____r___r7f_----_r'"

:l

"

~

~

7,5

"'

°1~--~--~~--~--~10~K,-~1~00~K~~lM

1M

POWER SUPPLY CURRENT
VS. TEMPERATURE

a:

SUPPLY

: = § i o n _p_O+S_IT_IV_E-+'_...._'_'--1

FREQUENCY Hz

il:a:

~RF

~~..... ...

~----tV__----+__----+----_r-----+----___I

7·~8':c0-----_4":0-------L----.......:'40::-------:8LO------cl~20-:-----:-'160
TEMPERATURE

2-162

oc

APPLYING THE HA-5160/5162
N
CD
.........

1. POWER SUPPLY OECOUPLlNG: Although not absolutely
necessasry. it is recommended that all power supply lines be
decoupled with 0.01 J.1 F ceramic capacitors to ground decoupling capacitors should be located as near to the amplifier
term;nal~ as possible.
2. STABILITY: The phase margin ofthe HA-5160/5162 will be
improved by connecting a small capacitor (>lOpF) between the

J

o

output and the inverting input of the device. This small capacitor compensates for the input capacitance of the FET.

CD
,...

CAPACITIV~

c(

it)

3.

LOAOS: When driving large capacitive loads
(>100pF'l; it is suggested that a small resistor (~100n).
be connecte~ in series with the output of the Qevice and inside
the feedback loop.

I

::r:::

APPlICA T/ONS
SUGGESTED COMPENSATION FOR UNITY GAIN STABILITY *

<>.:G
::;;2
INVERTING

NON INVERTING

o=>

u"-

a..:;:0
.....
«a:

a..!2

.

2k

00

u

2k

o-~-~~..~.~
.. ~----~~

0------1>

>-_>-----0

~A-5160/5162

1~160/5162

'VALUES WERE DETERMINED EXPERIMENTALLY
FOR OPTIMUM SPEEO AND SETTLING TIME

VERTICAL SCALE: (VOLTS: 2V/DIV.)
HORIZONTAL SCALE: (TIME: 500ns/DIV.)

"
OUTPUT~~-+-4--+-~-4--+-~l~~

2-163

HA-5170

mHARRIS

Precision JFET Input
Operational Amplifier
FEATURES

DESCRIPTION

•

LOWOFFSETVOLTAGE

•

LOW OFFSET VOLTAGE DRIFT

•
•

LOW NOISE
HIGH OPEN LOOP GAIN

IODIN
2P.V!oC
10nV/v'Hz"
600K V/V

• WIDE BANOWIDTH

8M Hz

APPLICA TIONS
.. HIGH" GAIN INSTRUMENTATION AMPLIFIERS
•

The Harris HA-5170 is a precision, JFET input, operational amplifier
which features low noise, low offset voltage and low offset voltage drift.
Constructed using FET/Bipolar technology, the Harris Oielectric Isolation
(DI) process, and laser trimming this amplifier offers low input bias and
offset currents. This operational amplifier design also completely eliminates the troublesome errors due to warm-up drift.
Complementing these excellent input characteristics are dynamic performance characteristics never ~efore available from precision operational
amplifiers. An 8V/J.1s slew rate and 8MHz bandwidth allow the designer
to extend precision instrumentation applications in both speed and bandwidth. These characteristics make the HA-5170 well suited for precision
integrator amplifier designs.

PRECISION DATA ACQUISITION

• PRECISION INTEGRATORS
• PRECISION THRESHOLD DETECTORS

The superior input characteristics also make the HA-5170 ideally suited
for transducer signal amplifiers, precision voltage followers and precision
data acquisition systems.
The HA-5170 is available in metal can (TO·99).'20 pin LCC, and both
ceramic and epoxy mini-dip packages.

PINOUT

SCHEMATIC
TOP VIEWS

BALDS
IN-

2

7

IN+

3

6

v-

4

5

N/C
N/C
V+
OUT

SAL
.AL

2-164

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS

o

......

(Note 1)

"r'"

TA = +25 0 C Unless otherwise stated
Voltage Between V+ and V-Terminals
Differential Input Voltage

44.0V
± 30.0V

Output Short Circuit Duration

Indefinite

ELECTRICAL CHARACTERISTICS
PARAMETER

LI)

Power Dissipation (Note 2)
Operating Temperature Range
HA-5170-2
HA-5170-5
Storage Temperature Range

675mW
-550C~TA ~+1250C
OOC~TA~+750C
-650C~T A ~ +150 0 C

V+= 15V, V-=-15V

TEMP.

MIN

HA-5170-2
TYP

MAX

MIN

HA-5170-5
TYP
MAX

UNITS

INPUT CHARACTERISTICS
+25 0C
Full

Offset Voltage
Average Offset Voltage Drift (Note 3)

Bias Current
Bias Current Average Drift
Offset Current

0.1

0.3
0.5

0.1

0.3
0.5

rnV
rnV

Full

2

5

2

5

IJ.V/oC

+25 0C
Full

20
3

100
30

20
0.1

100
2

pA
nA

Full

3

+25 0C
Full

3

30
5

3

Offset Current Average Drift

Full

Common Mode Range

Full

0.3
±l0

pA/OC

3

+15.1
-12

±10

60
0.1

pA
nA

0.3

pA/OC

+15.1
-12

V

Differential Input Resistance

+25 0C

6 x 10 10

B x 1010

il

Input Capacitance

+250C

12

12

pF

Input Noise Voltage a.1Hz to 10Hz (Note 3) +250C

0.5

5

0.5

5

IJ.Vp-p

20
12
10

150
50
25

20
12
10

150
50
25

nV/./Hi
nViJHz
nV/JHz

Input Noise Voltage Density .(Note 3)

to = 10Hz
to = 100Hz
to= 1000Hz

+250C

,

Input Noise Current Density (Note 3)

to = 10Hz
to = 100Hz
to= 1000Hz

+25 0C
.05
.01
.01

.05
.01
.01

pA/jHz
pA/JI1z

V/V
V/V

pA/JHz

TRANSFER CHARACTERISTICS

Large Signal Voltage Gain (Note 4)
Common Mode Rejection Ratio (Note 5)

+250C
Full

300K
200K

BOOK

300K
250K

BOOK

Full

85

100

90

100

dB

+25 0 C

4

8

4

8

MHz

Output Voltage Swing (Note 6)

+25 0C

±10

+12

~10

i12

V

Full Power Bandwidth (Note 7)

+250C

80

120

80

120

kHz

Output Current (Note 8)

+25 0 C

il0

Output Resistance (Note 9)

+25 0C

Closed loop Bandwidth (AVCL:::: +1)

OUTPUT CHARACTERISTICS

±10
45

rnA
il

45

TRANSIENT RESPONSE

Rise Time

+25 0C

Slew Rate

+25 0C

Settling Tim. INote 101

+25 0 C

45

100

45

8

5

5

1

100

ns

8

V/I's

1

~s

POWER SUPPLY CHARACTERISTICS

Supply Current

Full

Power Supply Rejection Ratio (Note 11)

Full

1.9
85

NOTES:
1. Absolute maximum ratings are limiting values, applied
individually beyond which the serviceability of the circuit
may be impaired. Functional operability under any of
these conditions is not necessarily implied.

2. Derate at 6.8 mW/oC for operation at ambient temperatures above +75 0 C.
3. Parameter is not 100% tested.
or exceed these specifications.

2.5

1.9

105

90% of all units meet

90

7. RL

co;

2k;

2.5

105

rnA
dB

Full power bandwidth guaranteed based on

slew rate measurement using FPBW '" SLEW RATE
21TVPEAK
8. VOUT = 10V.

9. Output resistance measured under open loop conditions
It = 100Hz).

4. VOUT = ±10V; RL = 2k.

10. Settling time is measured to 0.1% of final value for a 10V
output step and AV '" -1.

5. VCM = ±10V O. C.

11. VSUPP =±5V D. C. to ±20V D. C.

B. RL= 2kil.

2-165

I

!

.. 10HZ FILTER
AV = 25,000

VERTICAL SCALE:
HORIZON TAL SCALE:

2-166

200nV/Div. (Noise Referred to Input)
5mVDiv. At Output, AVCL = 25,000
1 Sec.lDiv.

PERFORMANCE CURVES

o

....

INPUT VOLTAGE NOISEVS. FREQUENCY

II)

0 .•

«
:::r:
I

0 .•
0.'

~~100

0.3

.......

::---.

0.2 ...........

""'

-

'~"
0

>

III

,....
,..

OFFSET VOLTAGE VS. TEMPERATURE DRIFT
OF REPRESENTATIVE UNITS

.0

0z

0.'

°

0.'

....-

0.2
0.3

••

.00

.0

'OOK

'OK

'K

/'

0.'

FREQUENCY HZ

""

-/'

0 .•
0 .•

-6.0

SETTLING TIME FOR VARIOUS
OUTPUT STEP VOLTAGES

.....
V

..

-2SO

/'

........

/'

-

:--"1<'"
./

r--

soo

250

7SO

.ODD

n;t-=
::;:~
o~
uu.

.250

TEMPERATURE (OC)

a..-..J
::;:0



~ -5

~~

i!:
::>
0

-.0

•

0 .•

°

s,ETTLING TiME

/

•

...

(~s)

1
!t1in

-

I

0,1

POWER SUPPLY CURRENTVS.
SUPPL Y VOLTAGE 8< TEMPERATURE
<1 3
+1{5OC

t-

il:

a:
a:

::>

2

" •

~oc

J.OC

./

~

t

~

/

0.01

E

0.001

ts'

t

! 10

-soo

,±20

15

./

-2SO

..

2SO

soo

7SO

'ODD

1250

TEMPERATURE -OC

SUPPLY VOLTAGE (V)

POWER SUPPLY REJECTION
RATIO VS. FREQUENCY

COMMON MODE REJECTION
RATIO VS. FREQUENCY

·11

'20

120

~UIR+

.......
• 00

'00

r"-

60

r-.

j
~60

PSRR-

I

~-80
a:
a:

.......

~,

f

40

l"-

40

.......

20

.0

r-.

i'j6D

100

lK

10K

'OOK

"

20

.0

'M

FREQUENCY (Hz)

100

lK

'OK

FREQUENCY (Hz)

2-167

lOOK

1M

PERFORMANCE CURVES (Continued)
SMALL SIGNAL BANDWIDTH & PHASE 'MARGIN
VS. LOAD CAPACITANCE

OUTPUT VOLTAGE SWING VS.
.FREQUENCY & SUPPLY VOLTAGE

RL .12K~
60 0

--

500

0

i'-

0

BANDWIDTH

"MARGI~

6

8

5

4

± 10V

"

\

LpplLlJs

6

K

2

8

100

~

1

4

0

0

r--.

10

RL-2K
CL" 50pf

II

4

20 0

PHASE

II
t6vLppLJs

100

10000

'000

II

±15V UPPLIES

II

1K

II

10K

100K

1M

FREQUENCY (Hz)

LOAD CAPACITANCE

NORMALIZED AC PARAMETERS
VS. SUPPLY VOLTAGE

I
0
8
BANDWIDTH

6

MAXIMUM OUTPUT VOL TAGE SWING
VS. LOAD RESISTANCE

TA = 2SOC

1/

•

35

I

VSLEWRATE

2

0

j
±2

±4

±6

,,:.I=t1 V
±S

±10 ±12 ±14 ±16 ±18

±20

5

V

SUPPLY VOLTAGE (V)

I

0

V

NORMALIZED AC PARAMETERS
VS. TEMPERATURE

5

fa0: 1.2
ffiu.",

Wo
~:Q 1.

w"
....

,~

WO:

~ 1.0
,,:E
~"
fa!i
N a.. 0.9
:

~

~~

"

51
V

I~ ~~WIDTH

100

~

0.8

_25 0

_550

00

250

50

I

V

Vs ="'!:6

lK

10K

I
100K

LOAD RESISTANCE (OHMS)

~RATE

0:

~

I-"~

I

0

0:"

Vs ""!10V

150

r

1000

125

TEMPERATURE (OC)

CLOSED LOOP FREQUENCY RESPONSE FOR
.
VARIOUS CLOSED LOOP GAINS

OPEN LOOP FREQUENCY RESPONSE
+11 0

IIIII
IIIII
IIIII

+100

'll

+90

z

+80

~

+70

w
"

+6 0

g

+5 0
+4 0

~

§

11111i11

100

RL' ~~~

Cl;; 50pF

GAIN

1'IJ.111

00

0

45D

0

....

11111

l"-

PHASE

i'-

+30

f5

+2 0

~

+1 0
0

1350

0

180 0

0

....

-1 0
10

100

1K

1M

10M

100M

10

100

1K

10K

lOOK

FREQUENCY (Hz)

2-168

1M

10M

100M

mHARRIS HA-51BO/BOA
Low Bias Current, Low Power
JFET Input Operational Amplifier

--+'--t--o
R10
031

v-

Balance

2-169

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Note 1)
TA = +25 0C Unless otherwise stated
Voltage Between V+ and V- Terminals
Differential Input Voltage

Power Dissipation (Note 2)
Operating Temperature Range
HA-5180/5180A-2
HA-5180/5180A-5
Storage Temperature Range

40V
±40V
Indefinite

Output Short Circuit Duration

300mW
-550C~TA~+1250C
00C~TA~+750C

-650C~TA~+150oC

ELECTRICAL RATINGS V+= 15V, V- = -15V

I
PARAMETER

TEMP.

MIN

5180A-2
TYP MAX

I
MIN

5180A-5
TYP MAX

I
UNITS

INPUT CHARACTERISTICS
Offset Voltage
Average Offset Voltage Drift
Bias Current (note 3)
Offset Current (Note 3)
Common Mode Range
Differential Input Resistance
Input Noise Voltage, 0.1 Hz to 10Hz
Input Noise Voltage Density
fo = 10Hz
fo = 100Hz
fo = 1000Hz
Input Noise Current (f=lkHz)

+25 0C
Full
Full
+25 0C
Full
+25 0C
Full
Full
+25 0C
+25 0C
+25 0C

0.1

±10

5
250
100
30
6
±12
10 12
5

0.5
1

0.1

1000
500
200
30
±10

1000
30
200
5

mV
mV
pV IOC
fA
pA
fA
pA
V

n

IlVp-P

200
120
70
0.01

+25 0C

5
250
6
30
1
±12
10 12

0.5
1

200
120
70
0.01

nV/VHZ
nV/v'Hz
nV/.,fHz
pA/VHz

1M

V!V
V!V
dB
MHz

TRANSFER CHARACTERISTICS
+25 0C
Full
Full
+25 0C

200k
150k
90

±10
±10

Full Power Bandwidth (Note 7)
Output Current (Note 8)
Output Resistance (Note 9)

+25 0C
Full
+25 0C
+25 0C
+25 0C

TRANSIENT RESPONSE
Overshoot
Rise Time
Slew Rate
Settling Time (Note 10)

+25 0C
+25 0C
+25 0C
+25 0C

Large Signal Voltage Gain (Note 4)
Common Mode Rejection Ratio (Note 5)
Closed Loop Bandwidth (AVCL = +1)

1M

200k
150k
90

110
2

110
2

OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 6)

±10

±12

±10
±10

110
±15
25

30
75
7
2

4

±10

50
4

V
V
kHz
rnA

±12
110
±15
25

30
75
7
2

n

50

%

ns
V/lls
ps

POWER SUPPLY CHARACTERISTICS
Supply Current
Power Supply Rejection Ratio (Note 11)

Full
Full

85

0.7
105

2-170

85

0.8
105

rnA
dB

SPECIFICA TIONS (Continued)
c:(

ELECTRICAL RATINGS V+= 15V, V- =-15V
PARAMETER

Q

TEMP.

MIN

5180-2
TYP MAX

MIN

5180-5
TYP MAX

r

CO

.........
Q

UNITS

CO
,...
II)
I

INPUT CHARACTERISTICS
Offset Voltage
Average Offset Voltage Orift
Bias Current (Note 3)
Offset Current (Note 3)
Common Mode Range
Oifferentiallnput Resistance
Input Noise Voltage, O.lHz to 10Hz
Input Noise Voltage Oensity
fo = 10Hz
fo = 100Hz
fo = 1000Hz
Input Noise Current (f=1 kHz)

c:(
+25 0 C
Full
Full
+25 0 C
Full
+25 0 C
Full
Full
+25 0 C
+25 0 C
+25 0 C

1

.:tID

3
4

5
1000
250
100
500
30
200
30
6
.:t12
10 12
5

1

.:tID

3
4

mV
mV

5
250
1000
6
30
30
200
1
5
±.12
1012
5

pV/oC

200
120
70
0.01

nV/.jff{

fA
pA
fA
pA
V

n

Vp-p

+25 0 C

+25 0 C
Full
Full
+25 0 C

200k
150k
90

:!:10

Full Power Bandwidth (Note 7)
Output Current (Note 8)
Output Resistance (Note 9)

+25 0 C
Full
+25 0 C
+25 0 C
+25 0 C

TRANSIENT RESPONSE
Overshoot
Rise Time
Slew Rate
Settling Time (Note 10)

+25 0 C
+25 0 C
+25 0 C
+25 0 C

Common Mode Rejection Ratio (Note 5)
Closed Loop Bandwidth (AVCL = +11

nVtyHz

nV/JHz
pAl.jHZ

1M

200k
150k
90

110
2

1M

V/V
V/V
dB
MHz

110
2

OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 6)

;t12

.:tID
.:tID

;tID
.:tID

110
±15
25

;tID

30
75
7
2

50

0.7
105

1

4

4

V
V
kHz
mA

:!:12
110
±15
25

n

30
75
7
2

50

%
ns
VIps
ps

0.8
105

1

mA
dB

POWER SUPPLY CHARACTERISTICS
Supply Current
Power Supply Rejection Ratio (Note 11)

<>.:G

::;:;2

o=>
uu.

200
120
70
0.01

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 4)

:I:

Full
Full

85

NOTES:
1. Absolute maximum ratings are limiting values. applied individually beyond which the serviceability of the circuit may
be impaired. Functional operability under any of these conditions is not necessarily implied.
2. Oerate at 6.9 mW/oC for operation at ambient temperatures
above +75 0 C.

85

6. RL = 2k

7. RL =2k. Vpeak =10V; Full power bandwidth guaranteed
based on slew rate measurement using FPBW = SLEW RATE
.
27TVPEAK
8. VOUT = ;tl0V.
9. Output resistance specified under open loop conditions
(f = 100Hz)

3. This parameter is guaranteed by design and is not 100% tested.

10.

Settling time is specified to 0.1% of final value for a 10V
output step and AV =-1.

11.

VSUPP = ±5V D.C. to ±20V D.C.

4. VOUT = ±10V; RL = 2k. Gain dB = 20 log IOAv.
5. VCM =il0V D.C.

2-171

....
-.....
::;:;0
-

0

/

il:

a: 10
a:

. . . 1'--.
-5

~

-1 0

::>

":rl

lmV'\

"

3

4

iii

\

5

o:G

/

1.0

:;:z

o=>

uLL.
c.:"'"

SETTLING TIME (~sl

:;:0

<0:
c..~

/
0.1
00

L

200

00
(,)

400

61)0
800
1000
TEMPERATURE (OC)

1200

1400

OPEN LOOP FREQUENCY RESPONSE
OUTPUT VOLTAGE SWING VS. LOAO RESISTANCE
120

1~~I. ~J~.llF

100

51---t+Ht1ltt-+++++++H-+-I+fWhIo/~~l1N1ffHllili

I'.

80

~rHfflOO~~~~~~Hll#~~

~AIN
80

5~W--l-Wm~~~vn~irw

PHASE

40

1000

I'-.,

o~~~~~~I-lJ~~-++HH*-v+s+.IH~L~v

1

~

0

01~~llW,~0~.m~I~~~Lli~lk-L~llW'0~k~l~lllllllll~ook

1800

10

100

1k
10k
FREQUENCY (Hz)

TOOk

1M

10M

LOAD RESISTANCE (OHMS)

OUTPUT VOLTAGE SWING VS. FREQUENCY

~~~+Jv
25

t-

~

RL'" TkO

CL" 50pF

-~~~j

l\

IIIIII I

1\

U~I~I±IJV

~

15

10

o
100

1111111

I

I U~I~±5J
1111111
lk

~

I
10k

lOOk

1M

10M

FREQUENCY - Hz

2-173

APPLICATION HINTS
The HA-5180/5180A offers one of the lowest input bias currents
of any monolithic operational amplifier and is ideal for use in
applications for measuring signals from very high impedance or
very low current sources. To fully utilize the capabilities of the
HA-5180/5180A care should be taken to minimize noise pickup
and current leakage paths with the use of shielding and guarding techniques and by placing the device as close as possible to
the signal source. The small size and low quiesent current (possible battery operation) of the HA-5180/5180A allows easy installation at the signal source or inside a probe. The HA-5180/
5180A is internally compensated and is capable of driving long
signal cables which have several hundred pF capacitive loading.
If it is not possible to place the HA-5180 very close to the
signal source then the use of shielded coaxial cable will offer
the best isolation of the high impedance signal line from external
noise sources. However, the effects of leakage, capacitance and
vibrational noise should be taken into account when using
coaxial cables. Leakage can be minimized by using cables with
very high insulation resistance (such as polyethylene or Virgin
Teflon). For example, the current to voltage converter circuit (as
shown in Fig. 1) will eliminate leakage across the insulation of
the cable by forcing the signal line to the same potential as the
shield. This circuit also provides fast response to input signals
because the cable capacitance is never forced to be charged or
discharged. However, the cable capacitance directly increases
the input capacitance of the circuit and could cause the circuit
to become unstable; if so, adding capacitance across Rf will
stablilize the circuit again. Leakage can also be reduced in the
high-impedance non-inverting configuration (see Fig. 2) by
bootstrapping the shield to the same potential as the signal
source instead of ground. If low closed-loop gains are used,
the non-inverting configuration could also become unstable due
to the positive feedback to the input through the cable capacitance. One method of compensating this circuit is to place a
small (low leakage) capacitor from the input to ground. This
technique will also reduce the effective capacitance presented to
the signal source. When large closed-loop gains and/or long
cable lengths are used, a buffer should be added to the circuit
to drive the shield.
Rf

>--+--0 OUT

"">-____o__--{l

OUT

RS

Figure 2. VERY HIGH IMPEDANCE NON-INVERTING
AMPLIFIER

When using coaxial cable with the HA-5180 the cable should
be kept as rigid and vibration free as possible. Frictional movement of the shield over the insulation can generate, electrical
charge which is picked up by the high impedance signal line as
noise. Movement and bending of the cable can also cause charge.
movement due to small changes in cable capacitance and capacitance to surrounding objects. Another source of noise currents is that which is generated by the movement of a conductor
in a magnetic feild.
For lowest leakage at the device inputs either use a teflon IC
socket or connect the signal line to the HA-5180/5180A
inputs using teflon standoffs. A guard ring, as shown in Fig. 3,
applied to both sides of the pc board and bootstrapped to the
same potential as the input signal will minimize leakage paths
across the pc board. Pin 8 of the TO-99 can, which is internally
tied to the case, should also be tied to the bootstrap potential to
help minimize noise pickup and leakage currents across the
package insulation. This technique will also reduce common
mode input capacitance.
Cleanliness of circuit boards and components is also important
for achieving low leakage currents. Printed circuit boards and
components should be thoroughly cleaned by using a low residue solvent such as TMC FrilOn,'rinsed by deionized water and
dried with nitrogen. The circuit board should be protected from
high contamination and high humidity environments. A good
quality conformal coating 'with low dielectric absorption provides the best protection 'from humidity and contamination.
Input protection is generally not necessary when designing with
the HA-5180/5180A. Many electrometer type devices, especially
CMOS, require elaborate zener protection schemes which may
compromise overall performance. The Harris dielectric isolation
process and JFET input design enables the HA-5180/5180A to
withstand input signals several volts beyond either supply and
large differential signals equal to the rail-to-rail supply voltage
without damage or degradation of performance.

Figure 1. CURRENT TO VOLTAGE CONVERTER

2-174

APPLICATION HINTS (Continued)
----~--,

~

0'

0 - - - > OUT

CO
,..

Iij"'o,"

Lt)
I


<..)L.L.

>-----{)

IN

a..-...J
:;;;0


uLL.
<>-- ......

INPUT CHARACTERISTICS
Offset Voltage

..:G
:;2

19

- FULL
FULL

70

2-177

90

28

19
70

90

28

rnA
dB

c(a::

<>-1-

05
u

NOTES:
I. Absolute maximum ratings are limiting values, applied
individually, beyond which the serviceability of the circuit may be impaired. Functional operability under any
of these conditions is not necessarily implied.

5. Vo=90mV.
6. AV = 10.
7. Full power bandwidth guaranteed based on slew rate

2. Derate at 8.7mW/oC for operation at ambient temperatures above +75 0 c. Heat sinking required at temperatures above +75 0 c. TJA = 115 0 C!W; TJC = 35 0 C/W.
Thermalloy model 6007 heat sink recommended.

measurement using FPBW = Slew Rate.
21TVpeak
8. Refer to Test Circuits section of data sheet.

3. RL =200f7.,CL --~----,-O
F
* .1' PROBE

~u.
l.r

ryn

(
l/1 F
-V

I

~

Load Capacitance should be less than 10pF.
It is recommended that resistors be carbon compositionr- and

that feedback and summing network ratios be matched.

MONITOR

•••

2Kn**

2-178

SETTLE POINT (Summing Nodel capacitance should be less
than 10pF. For optimum settling time results, it is recommended that the test circuit be constructed directly onto the
device pins. A Tektronix 568 Sampling Oscilloscope with S-3A
sampling heads is recommended as a settle point monitor.

PERFORMANCE CURVES

It)

V+ = +15V, V-

en
o
en
.,...

= -15V, TA = +250 C unless otherwise stated.

,

It)

INPUT OFFSET VOLTAGE AND
BIAS CURRENT VS. TEMPERATURE

4

=:: ::::::::...........

r--.....

..........

r-.....

""

OPEN LOOP FREQUENCY RESPONSE

I

~o

I

+40

+80

;'
z


PHASE /'

§

+180

1350

20

..

z
w

1\

0

0

..:G

1800

:;;2

0::::>

-10
lK

10K

lOOK

lMEG

u"-

":;;0
..--'

2250

IOMEG l00MEG

-12:

00

u

OUTPUT VOLTAGE SWING
VS. FREQUENCY

NORMALIZED AC PARAMETERS
VS. TEMPERATURE

S
0:

18

1.2

-

0:

w
..

16

~~
ffi~

~

1.1
1.0

tu!;;(
~ffi

.9

0::>

f~

.•

~~

.7

c>

~

:IE

. lOOK
lMEG
FREQUENCY - Hz

IOMEG

I

""

o
+40
+80
TEMPERATURE - OC

+120

+180

l00MEG

NORMALIZED AC PARAMETERS
VS. LOAD CAPACITANCE

INPUT NOISE VOLTAGE AND
NOISE CURRENT VS. FREQUENCY
140

1.2

~

1

120

~ 100

",

~

1,

,

BANDWy

B

1

80

w

SLEWRA"l"-

"

&0

\.

40

"'-

35
30

- ~iiinl NOISE
~
g 40
II~
~
I' J 11111 l";!; 2o

v6LTAGJ~

100

200

SOURCE RESISTANCE10
100

260

LOAD CAPACITANCE - pF

VOLTAGE NOISE SOU RCE
25
RESISTANCE' 5Kn
20

V.

r-.....

'"

.8
10

SLEWRAJE_

.........-aANDWIDTH~

-80

i
10K

/'

---

on

lK
FREQUENCY - Hz

2-179

15

I""-

10

r-10K

lOOK

w
!!!
0

z

!Zw
0:

cr:

:>

"t-

.
:>

;!;

PERFORMANCE CURVES (Continued)

OUTPUT VOLTAGE SWING
VS. LOAD RESISTANCE

SETTLING TIME FOR VARIOUS
OUTPUT STEP VOLTAGES

I'

5

~

2.5

J~ I-- o.~~ -

V

,

~ 0
~ -2,5
g

/

/

~

w

/

~

II

400

200

800

800

lK

,

.....

1'""'"'-

-5

::>

o

UK

LOAO RESISTANCE - OHMS

o

W

~

~

~

~

f
80

1'""'"'I--

ro

SETTLING TIME -

120

1~

0100

100

!g

~

..........

80

80

.......-

~ 80
"8 40

E
-

~ 18

..ill

4

I 11111111

I

1---

" NEGATIVE SUPPLY

lK

10K
FREQUENCY - Hz

1_

lK

lMEG

VSUPPL Y' t 16V .....
VSUPPLy=tlOV-.......::: I'-...

-

,

!!; 8

~

lW

POSITIVE SUPPLY -

'r-..

,20

0(24

12

~

t'-,

POWER SUPPLY CURRENT
VS. TEMPERATURE

~

80

ns

40

100

"u

80

I--

80

......

I:

:::>

V

r-r-.

:IE

~20

~l

POWER SUPPLY REJECTION
RATIO VS. FREQUENCY

COMMON MODE REJECTION RATIO
VS. FREQUENCY

25

V

,

0--.
TEMPERATURE - ac

-

+120

4-110

2-180

IIIIIII I

10K
FREQUENcY - Hz

...
1_

lMEO

APPLYING THE HA-5190/5195
It)

1. POWER SUPPLY DECOUPLlNG: Although not absolutely
necessary, it is recommended that all power supply lines be
decoupled with O.01pF ceramic capacitors to ground. Oecoljjlling capacitors should be located as near to the amplifier
terminals as possible.

4. OUTPUT SHORT CIRCUIT: HA-5190/5195 does not have

output short circuit protection. Short circuits to ground can
be tolerated for approximately 10 seconds. Short circuits to
either supply will result in immediate destruction of the device.

It)
I


u"0..--'

:;;0

APPLICATIONS



DESCRIPTION

FEATURES

The controller circuit senses the load on the motor and then
controls a TRIAC to apply reduced voltage to lightly loaded
motors, full voltage to heavily loaded motors.

LOAD ANTICIPATOR SENSES SHOCK LOADS AND
RESPONDS INSTANTLY WITH FULL POWER

• WITHSTANDS LINE SURGES TO 3500V
The HV-1 000/1 OOOA are available in a 16 lead plastic
DIP. Ideal for mounting inside induction motors, they can
also be mounted in a heat sunk circuit box for external,
after market application.

• CAUSES MOTOR TO RUN QUIETER, COOLER
• CAN BE MOUNTED INSIDE MOTOR
• NEEDS ONLY 3 RESISTORS, 3 CAPACITORS AND A
TRIAC TO ASSEMBLE COMPLETE CONTROLLER

PINOUT

APPlICA TIONS

TOP VIEW

• MACHINE TOOLS
• INDUSTRIAL SEWING MACHINES
• PRESSES

NC
OVERRIDE

POTCT
POTCW

DISC PACK DRIVES
~

NC

POT CCW

• CONVEYORS
•

AC IN

AC RET
EXT CAP HI
EXT CAP LO

• HEAT PUMPS

ANY APPLICATION WHERE FOR SOME OF THE
TIME THE MOTOR IS DRIVING LESS THAN ITS
RATED LOAD

PHASE SENSE
COMPENSATION

MOOE
TRIAC GATE RETURN

NC
TRIAC GATE

FUNCTIONAL DIAGRAM
POT
OVERRIDE CCW

POT POT CAP CAP PHASE
CT CW HI
LO SENSE MODE

AC IN o-+-----.

120/240V
A.C.

TRIAC

AC RETO'-+----I

L----1I--'O GATE

L-____~----~::::::~--------------------J
COMPENSATION

2-183

RETURN

SPEC/FICA T/ONS
ABSOLUTE MAXIMUM RATINGS
Input Voltage (With 5k Input Resistor)
Input Voltage (Without Input Resistor)
Power Dissipation
Operating Temperature Range

Storage Temperature
lead Temperature (Soldering, 10 seconds)
Output Current (10 microsecond Pulse)

3500VPEAK
±400VPEAK
500mW
OOC to +750C

-40 0C to +100 0C
3000C
500mA

ELECTRICAL CHARACTERISTICS See Note (a)
HV-l000/l000A using its internal power factor settings (pins 4, 5, 6, 7 shorted together). See Figure 1 for definition of ac, the current zero crossing, and at, the TRIAC trigger point. Frequency = both 50Hz and 60Hz unless
otherwise stated.
MIN

TYP

Skew (b)

PARAMETER

Difference Between Positive and
Negative at for a c =320

DEFINITION

o

±6.5

Degrees

load Anticipator
Trip Point (60Hz 0 peration)

Value of ac at which load
Anticipator Trips at ~,OHz

16

23

Degrees

load Anticipator (c)
Trip Point (50Hz Operation)

Value of ac at which load
Anticipator Trips at 50Hz

13

19

Degrees

Full load Power Factor
Setting

Value of a c at which ac - at

39

43

47

Degrees

Full load Power Factor (d)

Power "actor when a c =

.68

.73

.77

Power
Factor

No load Power Factor
Setting

Value of ac when at = 1460

Maximum Input Voltage

Breakover Voltage of Input
Protection SC Rs

Current Drain

RMS Input Current to chip
(Pin 16)

Maximum Output Voltage

Breakover Voltage of Output Stage
with Input to Chip Biased Normally
with AC Power

et

MAX

Degrees

32
400

500
2.0

600

UNITS

rnA
RMS

800

NOTES:
(a)

No guarantee of power savings can be given since the
savings achieved depend entirely on the motor and its
application. However, for a completely unloaded motor
driving only a flywheel or a pulley, power savings of 50%
are typical. It is not uncommon to observe savings of as
much as 80%. In'all applications the percentage of power
saved will depend on how much of the time the motor
'funs lightly loaded. Harris Application Note 542 covers
the subject of selecting suitable applications.

(b) The presence of skew results in partial rectification of the
AC power through the motor and reduced power savings.
The skew numbers shown here may decrease the power
savings of an unloaded motor as indicated on a rotating
wheel type, electric, utility power meter by approximately
10% maximum.
The skew is greatest at no load ( ()c = 32 0 ) , and decreases
linearly to zero as the motor approaches full load.
(c) The effect of a shock load is to shift ()c (the current zero
crossing) temporarily closer to the voltage zero crossing. If
the shock is severe enough to perturb ()c all the way back to

the load anticipator trip point, the HV-l 000 will discontinuously switch (trip) to full power. The anticipator trip point
is increased by the absolute value of an external potentiometer, 10k ohms increasing it about 6 degrees. A circuit
utilizing an external potentiometer is shown in Figure 6.
(d) This full load power factor is typical of a wide variety of
U.S., single phase, 60Hz, capacitor start induction motors
of power levels between )1\ HP and 1 HP. Many other motors, both larger and smaller and operating at 50Hz, can
also be driven satisfactorily by this power factor setting.
However, there are some motors for which this full load
power factor setting is not satisfactory, being either too
high or too low. To suit these motors, a potentiometer
must be added as shown in Figure 6. The potentiometer
should then be adjusted so that full voltage is applied to
the motor ( a c = a t) wh~n the motor is fully loaded. An
oscilloscope and a dynamometer are required to do this setup precisely, although .other loading means can be substituted for a dynamometer, if none is available. The
absolute value of the potentiometer determines the range
of adjustment, a 5k potentiometer giving a much larger
range of adjustment than a 1k potentiometer.

2-184

THEORY OF OPERATION
c(
Induction motors run at a speed which depends primarily on
the supply frequency, little on voltage. They draw almost a
co~stant current regardless of the load - the motor responds
to load with a change in power factor. Thus, a lightly loaded
motor wastes energy by heating its windings with inductive
current. The HV-1 000/1 OOOA measures the load using the
current phase angle and then saves power by applying to the
motor only sufficient voltage to drive the 10ad.!1) The voltage is
adjusted by TRIAC phase control.

II

I'-::-t

MOTOR

1-&,'

VOLTAGE
WAVEFORM

:6-{\.

I

"J""17

~

o
o
o

....

oo

....o
I

>
::I:
"

The controller chip triggers a TRIAC which is in series with the
motor. This varies the RMS voltage across the inotor. The
resulting voltage waveform across the motor is shown at the top
of Figure 1; A motor can be characterized by the relation
between the two parameters ac and at, shown in Figure 1 for a
typical motor. At point A, the motor is running fully loaded
with full voltage applied, as it was designed. At point B, the
motor is running lightly loaded with voltage reduced to the
point of stalling. The function of the controller is to force
the motor to operate along the load line AB, rather than AC
which it does naturally~ Figure 2 shows an example of the
typical power savings which results when the controller chip is
incorporated in a motor.

Ll6Hnv
LOADED MOTOR
WITH REDUCED
VOLTAGE
IMAX VOL TAlE)

"

(MIlilYOlTAIiiEI

-e-tDEGAEES

II

«D:

FIGURE 1
Voltage Waveform Characteristics of a TRIAC Controlled
Induction Motor

...

POWER INPUT "RATED LOAD

,

The key' features of the circuit are firstly that all analog processing is carried out with the circuitry running entirely on 50Hz 60Hz alternating current. Direct current is not used at all.
Secondly it is integrated using dielectric isolation, with junction
breakdowns of 400V. Junctions are stacked in both the input
regulator and the SCR output stage so that the composite
breakdown voltage of these stages is ±800V.
The analog processing which achieves the control "function is
explained conceptually in Figure 3. At any given load condition,
the controller tries to force the motor current phase a c to a
pre-programmed set phase. The phase to voltage converter
measures the difference between the set phase and a c, and
increments a pedestal voltage at a rate praportional to the
difference, delaying the trigger point at, where a reference ramp
intersects the pedestal. The delayed triggering reduces the
voltage applied to the motor, decreasing the motor winding
current so that ac is forced to the set phase by the modulation
of at. The set phase is itself a slow function of at, which produces the sloping controller characteristic fo Figure 1. This
is achieved via the feedback path from the output stage to the
phase to voltage converter.
An additional feature of the phase to voltage converter is the
load anticipator. If f}c is typically more than O.42ms less than
the set 'phase for 60Hz operation, which means the motor has
received a sudden heavy load, the full line voltage is immediately
applied to the motor. This allows the motor to respond at once
to a step function load. If the load is abruptly removed, the
controller cuts back the voltage applied to the motor over a time
period set by the external time constant capacitor. This mechanism is described in mOre detail in Harris Application Note 542.

(1) This circuit principle was first described by F. J. Nola in
U.S. Pat. 4052648.

2-185

...

POWER OUTPUT % RAtED LOAD

"..

FIGURE 2
Power Savings as a Function of Load for a 1/3 HP Motor

CURRENT

~~MDTOR
I

PflASE

I

lec)

VOLTAGE

-I

I

ERROR

I : MO~EO~~:SE
I I UETPHASE

:
:
I

I
J
TRIGGER POINT
1le,I

,

PEDESTAL

RAMP

0:::>
,-,,,-

c ........
:;:0

1lZ

'"

..:G
:;:2

ANALOS PROCESSING

FIGURE 3
Relation of the Voltage and Current Waveforms to the
Analog Processing Function

<1.!2
00
'-'

APPlICA TIONS INFORMATION
Improvement of the efficiency of single phase induction motors
may be achieved in two ways. For motors which drive a steady
load equal to their rated capacity, the best method is to use a
run capacitor with an auxiliary winding. This causes the internal
field structure of the motor to resemble that of a three phase
motor, an inherently more efficient arrangement. However,
if a capacitor run motor is used to driva less than its rated load,
its power consumption will usually be greater than a motor
without a run capacitor. If this is the case for a significant
fraction of the time, a run capacitor is not effective for improving
efficiency. By contrast an electronic energy saving motor
controller produces significant improvements in efficiency for
lightly loaded motors, and is therefore, the best choice for motors
which spend a significant part of their time lightly loaded.
Electronic energy saving controllers are useful for machine
tools, industrial sewing machines, heat pumps, presses, conveyors, disc pack drives, and commercial washing machines; in
other words for any application where the load on the motor is
either variable or ill defined. Run capacitors are useful for
refrigerators, air conditioners, and ventilation fans - all applications where the load on the motor is steady and well defined.
An electronic energy saving controller should not be applied in
a circumstance where a motor is driving a constant, steady load

equal to its rated load. In this circumstance the power dissipated
in the TRIACs may actually increase the total power usage.
However, it sometimes happens that induction motors are relatively conservatively designed, and the real power capability of
the motor is greater than that stated. This may come about,
for instance, because the motor may have been designed to
operate with worst case low line voltage, say, 100V for a nominal 115V motor. In such a circumstance, an electronic energy
saving controller can produce useful savings, because in reality,
the conservative design of the motor is causing it to be operating
at less. than its full capability. This circumstance can be tested
experimentally by connecting a power meter to the motor and
then adjusting the set power factor with a potentiometer on
the controller circuit to test whether reduced power consump~
tion can be obtained. Once set up in this way, the controller
will continue to give the motor just sufficient voltage to drive
the load in hand, even if the line voltage drifts high. In other
words, the energy saving controller also acts as a line voltage
regulator. This is especially beneficial in areas where the line
voltage fluctuates, since high line voltage can cause an induction
motor to consume excessive amounts· of power. For more
information see Harris Application Note 542 "Using the
HV-l000 Induction Motor Energy Saver"..

APPLICATION CIRCUITS
'2OV""'''''"

1
1

ACRET

""" +,"'--f-y'iIfof

switched together. However, if this is not possible and a switch
has to be placed in series with the motor between the motor
and HV-l000, the circuit of Figure 5 should be used. The
0.01 II F (SOOV) capacitor ke~ps the phase sense property of
HV-l000 alive while the switch is open, ensuring a smooth
start-up when the switch is closed.

He 15

NO"
OVERRIDE 13

:=='2
1

ACRET

"" 'N

"''''---+...w......-~

He. 15
Nt 14

PHASE 1
SENSE

COMPENSATION

-SNUBBER--

::.:

11

,2OV_
INDUCTION
MOTO'

non
lW

FIGURE 4
Basic Application Circuit for the HV-l000

NOTE:

TRIACCan_lon.~!!!!!!!y:!!!~

Basic Circuit
-SNUBBER-22DfI

Figure 4 shows the basic application circuit for HV-l000. This
circuit would be suitable for a 1/2 HP motor. For smaller or
larger motors, the time constant capacitor (between pins 2 and
3) and snubber capacitor should be scaled in proportion to
the size of the motor.
Operation with a Motor Switch

We recommend that the HV-l000 circuit should be permanently wired to the motor so that HV-l000 and motor are

~

lW

FIGURE 5
Application Circuit with Switch on Motor
To Adjust the Phase Setting

When it is required to adjust the full load, power factor setting,
a potentiometer should be added as shown in Figure S. The
larger the absolute value of the potentiometer. the greater the
range of adjustment. 1k ohms is recommended as a starting

2-186

APPLICATION CIRCUITS (continued)
point if potentiometer adjustment is required. Adding the
potentiometer also increases sensitivity of the load anticipator,
a 10k potentiometer advances the anticipator trip point by
6 degrees. In general the smallest absolute value of potentiometer that covers the desired range of adjustment should be
used. 10k ohms is the maximum potentiometer value normally
needed.

1

NOTES:
(a) Stability: A small number of motors, primarily amongst
the larger (above 1 HP) single phase motors may not
necessarily run in a stable fashion with the application
circuit of Figure 4. The symptoms are irregular vibration
and repeated jerky application of full power to the motor.
An oscilloscope placed in differential mode across pins
2 and 3 will show rapid fluctuations in voltage instead
of the steady voltage levels characteristic of control
equilibrium. This and similar effects are described in
Harris Application Note 542. The problem is helped by
increasing the inertia on the shaft (e.g., adding a flywheel),
by increasing the time constant capacitor and sometimes
by adding a potentiometer and adjusting it for smaller
power savings. If all these measures fail it may be that
a special application circuit will be needed as described
in Application Note 542. The effect is dependent on
which company manufactured the motor.

ACIN.jl''-'-hii.....

ACRET

FIGURE 6
Application Circuit for HV-1 000/1 OOOA with Potentiometer
to get Increased Anticipator Sensitivity and Adjustable
Phase Setting
Electronic Override
Pin 13 is a TTL logic input which commands full output power.
It can be activated with a switch as shown in Figure 7. The
diode between pins 13 and 1 needs 5V capability, it is to
prevent negative potentials being applied to pin 13.

(b) Selection of components: The TRIAC used should have a
current rating which allows the locked motor current of
the motor (often three or more times the run current! to be
conducted for as long as this may persist. Normally heat
sinking will be required to conduct away the heat of the
TRIAC. The 5k input resistor only performs a useful
purpose during voltage surges in excess of 600V. When
this happens, internal crowbar clamps on chip between
pins 1 and 16 break over and momentarily conduct about
an ampere, causing thousands of volts to be dropped across
the 5k resistor. For this reason the physically large size
of a 1W resistor is needed, otherwise the terminals of the
resistor would arc over. The time constant capacitor
between pins 2 and 3 is normally chosen to be the smallest
value that will allow the motor to run in a stable fashion.
If it is chosen too large, the HV-1000 will not throttle
back the voltage as quickly, if the load suddenly decreases.
This effect reduces the power savings.

"12OVI24OV
ACINPUT

HV-1OOOJ1000A
, ACRET

PHASE 12

SENSE
COMPENSATION

B TRIAC GATE

RETURN

11

TRIAC 9
G~TE

NOTE: TR1ACConnectiam!:!!!!!!!!~.!!"own

FIGURE 7
Application Circuit for HV-1000/1000A Illustrating
Electronic Override

2-187


:I:

3-2

Data Sheet Index
Ordering Information

3-3

t!l
0(1)

-'w

<:I:
Zu
2
15mW

All devices provide break-before-make switching and are TTL
and CMOS compatible for maximum application versatility.
HI-200 is an ideal component for use in high frequency analog
switching. Typical applications include signal path switching,
sample and hold circuit, digital filters,and op amp gain switching
networks.

APPlICA TlONS

•

HIGH FREQUENCY ANALOG SWITCHING

•

SAMPLE ANO HOLD CIRCUITS

•

DIGITAL FI LTERS

•

OP AMP GAIN SWITCHING NETWORKS

H1-200 is available in DIP and metal (TO-100) cans. H1-200-2
is specified from -55 0 C to +1250 C while H1-200-5 operates
from OOC to +750C. H1-200 is functionally and pin compatible
with other available "200 series" switches.

FUNCTIONAL DIAGRAM

PINOUT
TOP VIEWS

IN 1
V.

A1
NO

1

GND

3

NO

4

1N1
OUl2

v-

~f"
:

'I

13

NO

11

v.

11

NO

:~p-1:

Al

A,

OUT 1

1N1

SWITCH OPEN
FOR LOGIC HIGH

OUT 1

VREF
OUT 2

IN 2

A2

CASETIEDTO V-

OUT 2

3-6

SPECIFICATIONS

c

ABSOLUTE MAXIMUM RATINGS
Supply Voltage
VREF to Ground
Digital Input Voltage:
Analog Input Voltage (One Switch)

44V (±22)
+20V, -5V
+VSupply +4V
-VSupply -4V
+VSupply +2.0V
-VSupply -2.0V

C
N

450mW

Total Power Dissipation*
Operating Temperature
HI-200-2
HI-200-4
HI-200-5
Storage Temperature

I

-55 0 C to + 125 0 C
-25 0 C to +85 0 C
OOC to +75 0 C
-65 0 C to +150 0 C

*Derate 6mW/oC Above TA = 75 0 C

ELECTRICAL CHARACTERISTICS
Unless Otherwise Specified
Supplies= +15V, -15V; VREF = Open; VAH(Logic Level High) =2.4V VAL(Logic Level Low) = +O.8V
For Test Conditions, consult Performance Characteristics
HI-200-2
-55°C to +125 0C
MIN.
TYP.
MAX.

HI-200-5**
OOC to +750C
MIN.
TYP.
MAX.

-15

-15

PARAMETER
ANALOG SWITCH CHARACTERISTICS
VS, Analog Signal Range

TEMP.

RON, On Resistance INote 1)

+25 0C
Full

55
80

70
100

IS (OFF), Off Input Leakage Current INote 6)

+25 0C
Full

1
100

5
500

ID(OFF), Off Output Leakage Current INote 6)

+25 0C
Full

1
100

5
500

1
10

+25 0C
Full

1
100

5
500

1
10

10ION), On Leakage Current INote 6)

Full

DIGITAL INPUT CHARACTERISTICS
VAL, Input Low Threshold
VAH, Input High Threshold

Full
Full

lA, Input Leakage Current IHigh or Low) INote 2)

Full

+15

+15

V

72

80
100

11
11

1
10

50
500

nA
nA

50
500

nA
nA

50
500

nA
nA

0.8

V
V

1.0

Il A

55

0.8
2.4

UNITS

,

I

2.4
1.0

SWITCHING CHARACTERISTICS
tOPEN, Break - Belore Make Delay INote 3)

+25 0C

60

60

ns

ton. Switch on Time

+25 0C

240

500

240

ns

toll, Switch off Time

+25 0C

330

500

500

ns

"Off Isolation" INote 4)

+25 0C

70

70

dB

Cs 10 FF), Input Switch Capacitance

+25 0 C

5.5

5.5

pF

CD 10FF), {

+25 0C

5.5

5.5

pF

COlON),

+25 0 C

11

11

pF

CA, Digital Input Capacitance

+25 0C

5

5

pF

COS 10FF), Orain-To-Source Capacitance

+25 0 C

0.5

0.5

pF

+25 0C
Full
+25 0 C
Full
+25 0 C
Full

15

Output Switch Capacitance

POWER REQUIREMENTS INote 5)
PO. Power Dissipation

1+, Current
1-, Current

NOTES, 1. V O UT=i10V

15
60

60
0.5

0.5
2.0
2.0

5,

IOUT=1mA

2. Digital Inputs are MOS gates - Typical Leakage is Less Than.1nA.

2.0
0.5

0.5

6.

2.0

VA = +3V or VA = OV for Both Switchefl

Ref1:!r to leakage current measurement diagram
3-9

on page

3. VAH = 4.0V
4. VA = 5V, RL = 1kr! ,CL = 10pF, Vs = 3VRMS, f = 100kHz

** Note: HI-200-4 has same specifications as HI-200-5 over the temperature range -200C to +_85 0 C.

3-7

mW
mW
rnA
rnA
rnA
rnA

SCHEMATIC DIAGRAMS
TTL/CMOS
REFERENCE CIRCUIT

SWITCH CELL

V-REF CELL

A'>---------~~----------_.--_,

OUTPUT

R4

GND
A'~----------~~--------~

v+
"

OIGITAL INPUT BUFFER
AND LEVEL SHIFTER

.--+-+--+ A'

200n

ALL N-CHANNEL
BOOIES TO vALL P-CHANNEL
BOOIES TO V+
EXCEPT AS SHOWN.

V-

3-8

PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS
(UNLESS OTHERWISE SPECI FlED T A = 25°C, VSUPPL Y =±15V, VAH

= 2.4V VAL = O.SV AND

VREF

=OPEN).

C)
C)

N

I

ON RESISTANCE vs. ANALOG SIGNAL LEVEL,
SUPPLY VOLTAGE AND TEMPERATURE

,

v2

RON =;;;;p;

-

1 rnA

,

v2

,...

IN

,...

-:=t.

.!.Y IN

OUT

HI-200

-=
ON RESISTANCE vs. TEMPERATURE
80

C!J

Den
...J
UJ

.70

---VIN = OV

60

E
.t::
a,
1;;

40

~

a~

:;:en
u

~

50

~

:;;

«:I:
Zu
«Ien -

,.

.--~

~

.~

a:

30

<:

a

20
10
0

-50

-25

+25

0

+50

+75

+100

+125

Ambient Temperature _oC

(HI-200)
ON RESISTANCE vs. ANALOG SIGNAL LEVEL
AND POWER SUPPLY VOLTAGE
100

I

V"

E

.t::

a

I

~

:;;

1;;

50

.;;;

-

""" r--.

r---

V+ = +10V
V- = -10V

----

V+=+12.5V

i-"""

....

V-

V---12~V+=+15V

I"--

-

.......

V_=-15V,......-

-~

a:
'"

c:

a

0
-15

-10

-5

0

Analog Signal Level - Volts

3-9

+5

+10

+15

PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS (Continued)
SWITCH LEAKAGE CUR RENT vs.
TEMPERATURE (HI-200)
100

OFF LEAKAGE CURRENT
vs. TEMPERATURE

/

/

/

V

ISIOFFI

/
ISIOFFI/IDIOV

±14V

-=-

-=-

.I

.I

10

/

«c:

/

/

/

I

/

/

1:
~

"

u

1.0

V

/

/

101:;/

/

ON LEAKAGE CURRENT
vs. TEMPERATURE
IN
OUT

/

HI-200

/

/

1

/

/

/

-=-

±14V

.l

+125 0 C

Temperatu re

SWITCH CUR RENT vs. VOLTAGE
90

80

./

70

«

60

E
I

1:
~

50

"

40

~

30

u
.c:

./

. / '"

---

V

o
o

~

/
±2

SWITCH CURRENT
vs. VOLTAGE

IN~:
r

r--~--~O

/'

.~

en 20
10

V

/'

V

......-

±3

±5

±6

Voltage Across Switch - Volts

3-10

±7

~

.14V

PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS (Continued)
o
o

N

I

(HI-200)
SWITCH TIME vs. TTL LOGIC LEVEL
ON/OFF SWITCH TIME vs.
LOGIC LEVEL

500

1\

400

.
..

300

E

i=

-£

"ien

'~F

"

c:
I

+10V

\

; - ;+ BREAK-BEFORE-MAKE

~
i""""-

200

-

,

6

--

)

HI-200

IOIN-24L_ f - -

~

..n..

MAKE BEFORE·_
BREAK

lK~
~

VA

-

100

IN

OUT

::: ::: 35pF

-

0
2.5

3.0

3.5

4.0

4.5

5.0

TTL Logic Level (V AH) - Volts

SWITCHING WAVEFORMS
DIGITAL
INPUT

VA = 4.0V

50~

\.

VA = O.OV

/

~O%
--tOFF--

-tON
SWITCH
OUTPUT

'\

90%

OV

r10%
~

tON. tOFF(CMOS INPUT)
VREF = OPEN. VAH = +15V

tON. tOFF (TTL INPUT)
VAH =+4.0V

f(

I'

1\

It

J
[

I
J

iAJ

Top: TTL Input
Bottom: Output

Top: CMOS Input
Bottom: 0 utput

Vertical: 2V/Div.
Horizontal: 200ns/Div.

3-11

\.
Vertical: 5V/Div.
Horizontal: 200ns/Div.

;m~RIS

HI·201
Quad SPST CMOS
Analog Switch

FEATURES

DESCRIPTION

•

ANALOG VOLTAGE RANGE

±15V

•

ANALOG CURRENT RANGE

80mA

• TURN-ON TIME

185ns

•

55n

LOW RON

•

LOW POWER OISSIPATION

•

TTL/CMOS COMPATIBLE

HI-201 is a monolithic device comprising four independently
selectable SPST switches which feature fast switching speeds
(185m) combined with low power dissipation (15mW at 25 0 C).
Each switch provides low "0 N" resistance operation for input
signal voltages up to the supply rails and for signal currents up
to 80mA. Employing Dielectric Isolation and.CMOS processing,
HI-201 operates without any applications problems induced
by latch-up or SC R-mode phenomena.

15mW

APPlICA TIONS

All devices provide break-before-make switching and are TTL
and CMOS coinpatible for maximum application versatility.
HI-201 is an ideal component for use in high frequency analog
switching. Typical applications include signal path switching,
sample and,hold circuit, digital filters,and op amp gain switching
networks.

• HIGH FREQUENCY ANALOG SWITCHING
• SAMPLE ANO HOLO CIRCUITS
•

DIGITAL FILTERS

•

OPAMPGAINSWITCHINGNETWORKS

HI-201 is available in a 16 lead dual-in-line package and a
20 pin LCC package. HI-201-2 is specified from -55 0 C to
+125 0 C while HI-201-5 operates from OOC to +75 oC. HI-201
is functionally and pin compatible with other available
"200 series" switches.

PIN OUT

FUNCTIONAL DIAGRAM
TOP VIEWS

A,

,

TYPICAL SWITCH

OUT 1 2

IN

IN 1 J

v·

4

GND 5
:N 4 6

OUT 4 7

A, 8

11 IN 3
10 OUT 3

9 A3

~

~

~

-

3-12

SPEC/FICA TlONS

,..

ABSOLUTE MAXIMUM RATINGS
Supply Voltage Between Pins 4 and 13
VREF to Ground
Digital Input Voltage:
Analog Input Voltage (One Switch)

C

Total Power Dissipation*
750mW
Operating Temperature
HI-201-2
-55 0 C to +125 0 C
HI-201-4
-25 0 C to +85 0 C
HI-201-5
OOC to +75 0 C
Storage Temperature
-65 0 C to +150 0 C
*Derate 8mW/oC Above TA = +75 0 C

44V (±22)
+20V, -5V
VSupply(+) +4V
VSupply(-) -4V
+VSupply +2.0V
-VSupply -2.0V

N

I

ELECTRICAL CHARACTERISTICS
Unless Otherwise Specified:
Supplies = +15V, -15V; VREF = Open; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = +O.8V
For Test Conditions consult Performance Characteris6cs
HI-201-2
-55 DC to +125 0 C
PARAMETER

TEMP.

MIN.

Full

-15

TYP.

HI-201-5 •

DoC to +75 0 C

MAX.

MIN.

+15

-15

TYP.

MAX.

UNITS

+15

V

ANALOG SWITCH CHARACTERISTICS
VS, Analog Signal Range

t:J
0",
....IUJ

RON, On Resistance (Note

1)

IS(OFF). Oft Input Leakage Current (Note 6)

70
100

55
75

80
100

11

Full

55
80

+25 0 C

2

5
500

2

50
250

nA
nA

+25 0 C

Full

n

IO{OFF), Off Output Leakage Current (Note 6)

+25 OC
Full

2

5
500

2

50
250

nA
nA

IO(ON), On Leakage Current (Note 6)

+25 0 C
Full

2

5
500

2

50
250

nA
nA

0.8

V

DIGITAL INPUT CHARACTERISTICS

VAL, Input Low Threshold

Full

VAH, Input High Threshold

Full

lA, Input Leakage Current (High or Low) (Note 2)

Full

0.8
2.4

V

2.4
1.0

1.0

iJ. A

SWITCHING CHARACTERISTICS
tOPEN, Break-Before Make Delay (Note 3)

+25 0 C

30

30

ns

tON, Switch ON Time

+25 0 C

185

500

185

ns

tOFF, Switch OFF Time

+25 0 C

220

500

220

ns

"Off Isolation" (Note 4)

+25 0 C

80

80

dB

CS(OFF), Input SWitch CapaCItance

+25 O C

5.5

5.5

pF

COIOFF)

+25 0 C

5.5

5.5

pF

+25 0 C

II

II

pF

Input Capacitance

+25 0 C

5

5

pF

CDS(OFFj, Drain-to-Source Capacitance

+25 O C

0.5

0.5

pF

+25 O C
Full

15

+25 0 C
Full

D.5

+25 O C
Full

0.5

COlON)

CA,

~igital

}

Output Switch Capacitance

POWER REQUIREMENTS (Note 5)

Po, Power Dissipation (Note 5j

1+, Current (Pm 13)

1-, Current (Pin 4)

NOTES: 1. VOUT ~:t 10V

lOUT

= 1 mA

3. VAH ~ 4.0V

= 5V,

RL ~ 1kf2 ,CL

mW
mW

2.0

mA
mA

2.0

mA
mA

0.5
2.0
0.5
2.0

5, VA = +3V or VA = OV for All Switches

2. Digital Inputs are MQS gates - Typical Leakage is Less Than 1nA.

4. VA

60

15
60

= 10pF. Vs = 3VRMS, f

6.

Refer to leakage current measurement diagram
on page 3-15

~ 100kHz

.. Note: HI-201-4 has same specifications as HI-201-5 over the temperature range -20 o C to +85 0 C.

3-13

«::I:
2U
«I-

"'0;':
:;;:'"
U

SCHEMATIC DIAGRAMS
TTL/CMOS
REFERENCE CIRCUIT

V-REF CELL

SWlrCH CELL
A')---------~~----------_.--_.

OUTPUT

GND
A')-----______~~--------~

DIGITAL INPUT BUFFER
AND LEVEL SHIFTER

V+

.....--+--+-_ A'

200 n

'----+-+--++--I~A'

ALL N-CHANNEL
BODIES TO VALL P-CHANNEL
BODIES TO V+
EXCEPT AS SHOWN.

V-

3-14

PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS
(UNLESS OTHERWISE SPECIFIEO TA = 25°C, VSUPPLY =±15V, VAH =2.4 V VAL = O.8V ANO VREF = OPEN).

,....
o

N

I

ON RESISTANCE vs. ANALOG SIGNAL LEVEL,
SUPPLY VOLTAGE ANO TEMPERATURE

.

v2
RON 'lmA
IN

#-=

~V'N

lmA

,

v2

,.,

'"'

OUT

HI-201

ON RESISTANCE vs. TEMPERATURE
80
10

E

..c

-

60

O

.,
"c:
tJ!
';;;
.,
I

a:

c:

&0
40

---

...

30

~

I-"'""

~

V,N' OV

~

r0-

~

0

20
10
0

-&0

0

·2&

+2&

+&0

+1&

+125

+100

Ambient Temperature - °c
(HI-20l)
ON RESISTANCE vs. ANALOG SIGNAL LEVEL
AND POWER SUPPLY VOLTAGE
100

V
V+ = +10V

E

"...

.z::

.,,

0

"c:

co
1;;

&0

"iJ

-

V-.-l0V....
v+· +12.&V
V-·-12.&V

/'

V

V

fo""""
~

V-

/v+. +l&V--:

~

V

V-~V

V

a:

c:
0

0
-15

·10

-&

0

+&

Analog Signal Level - Volts

3-15

+10

+1&

PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS (Continued)
SWITCH LEAKAGE CURRENT vs.
TEMPERATURE (HI-201)
10 0

OFF LEAKAGE CURRENT

/

vs. TEMPERATURE

/

V

/
IS(OFFI/IDIOV

+14V

-=-

_

T

~

0
f

/


t.)

1.0

V

/

/

/

ON LEAKAGE CURRENT
vs. TEMPERATURE

ID(y

IN
OUT

HI-201

/

/

/v

/
-=.I.

O. I
+25 0 C

±14V'

+125 0 C

+IOOOC

Temperature

SWITCH CURRENT VS. VOLTAGE
90
80
70

./


....

3

:--i--

1+

"""- "-

I-

<
...z
w

a:
a:

::l
t.)

w
C>

::l

«

""«w

r-r+V = +15V

z
0
~

~

~

~

~

~

~

75
T - TEMPERATURE IOC)

125

LEAKAGE CURRENT vs ANALOG INPUT VOLTAGE

oS

-"

....

.0 1
25

6

...z

.10

125

SUPPLY CURRENT vs TEMPERATURE

5

....

1.0

t.)

«

<
.5

10.0

a:
a:

w
C>

....

+10

IDIONI vs TEMPERATURE *

10.0

w

""«

+5

100.0

Z

w

--=----

--'"

~
A

-5

*

100.0

::l

./

VIN - ANALOG INPUT (VOLTS)

ISIOFFI or IDIOFFI vs TEMPERATURE

t.)

..........

0

V-=-15V
V-=-12V
V- III -10V
V-=-8V

V+=+15V

VIN - ANALOG INPUT (VOLTS)

1...

..........

........

20 - 8 V+=+12V
C V+= +10V
0 V+=+8V
0
0
-15

+15

~

....

100
80
60
40
20
0
-20

,
lOON

~

-40
-$

...-r

-

ISOFF/IOOr;,

-80
-100
-120
-140

~

~

i--' i"""

I-'"

1/
I-'"

"
V+=+15V
V-=-15V
ISOFF-VO=OV

~

-160
-180

'On-iSjoy
-200
-14-12-10 -8 -6 -4 -2
2 4 6 8 10 12 14
VIN - ANALOG INPUT IVOLTS)

W

°

T - TEMPERATURE IOC)

'THEORETICALLY, LEAKAGE CURRENT WILL CONTI·NUE TO DECREASE BELOW +25 0 C. BUT DUE TO
ENVIRONMENTAL CONDITIONS, LEAKAGE MEASUREMENTS BELOW THIS TEMPERATURE ARE NOT
REPRESENTATIVE OF ACTUAL SWITCH PERFORMANCE.

3-21

I

TA" +250C
0

~ 60

5

;;;50

~

o

N

80

70

:1
t;
iii

,....

ON RESISTANCE vs ANALOG SIGNAL LEVEL
AND POWER SUPPLY VOLTAGE

ON RESISTANCE vs ANALOG SIGNAL LEVEL
AND TEMPERATURE

+15

TYPICAL PERFORMANCE CURVES (Continued)
DIGITAL INPUT LEAKAGE CURRENT vs TEMPERATURE

*

LEAKAGE CURRENT vs ANALOG INPUT VOLTAGE
(VIN ?:+14V, VIN'S-14V)
10

20
40

IAHl

60
-20

"15'"

-40
-60
-80

,3

a:
a: -100

::>

"w
"'"
"
~

2

-120

1

w

-140

~

-160

0
1
-2
-3

~

IAH2

-180
-200

IAL

-220

/'

-4

~:~;~~v-

-240
-260
-280

-5
-6

VAH1"'5V-

25

35

45

55

65

75

85

95

105

115

v+ = +15V

-8

T- TEMPERATURE (OC)

-

-

V- '" -15V
TA=+25 O C
ISOFF-VO = OV '~OFF-VS=~V _

7

125

-9
-10

-16.0 -15.5 -15.0 -14.5 -14.0 +14.0 +14.5 +15.0 +15.5 +16.0
VIN - ANALOG INPUT (VOLTS)

SWITCHING TIME vs TEMPERATURE

-

180
160

SWITCHING TIME vs POSITIVE AND NEGATIVE
SUPPLY VOLTAGE

tOFF2

140

350

RL

]

w

100

";::
"l'z

80

~

250

........

";::
"l'z 150
~

1\

"-.

f"'... I"--1OFF2

\

100

~

60

~

lK

TA=250C

w 200

120

I

=

_~l=35pF

300

I'- ~ t::- tO~F1

50

tON

tOFFl

40

tON

±5

V+ +15V
V·-·15V -

20

RL

.±6

±7

±8

±9

±10

±l'

±12

±13

±14

±15

V+, V- - POSITIVE AND NEGATIVE SUPPl V (VOLTS)

lKU

=

Cl = 35pF
-55

-35

-15

25

45

65

85

105

125

T - TEMPERATURE (OC)

SWITCHING TIME vs NEGATIVE SUPPLY VOLTAGE

SWITCHING TIME vs POSITIVE SUPPLY VOLTAGE
350
30

I

350

v- = -,5V

O-~~:~~~
TA=250C

"-

"r-...

200

"i:

175

~

150

z

1

250

w
"
;::

200

~

100

:\.......

v+ = +15V
!--- RL = lKn
CL = 35pF
TA=250C

250

w

~

.........

~

~

200

"~ 150

tOFF2

tOFt

100
50

........

'\. f"'... I"--

t()FF2

"r-...

" I'.....

tON

50
10

11

12

13

tOJFl
tON

14

15

10

11

12

13

14

V - NEGATIVE SUPPLY (VOLTS)

V+ - POSITIVE SUPPLY (VOLTS)

"THEORETICALLY, LEAKAGE CURRENT WILL CONTINUE TO DECREASE BELOW +25 0 C. BUT DUE TO
ENVIRONMENTAL CONDITIONS, LEAKAGE MEASUREMENTS BELOW THIS TEMPERATURE ARE NOT
REPRESENTATIVE OF ACTUAL SWITCH PERFORMANCE.

3-22

15

TYPICAL PERFORMANCE CURVES (Continued)
U)

J:

SWITCHING TIME vs INPUT LOGIC AMPLITUDE

,

350

V+'+I'5V
,---y-=-15V
300
RL-1Kll

1;;;250
;::
co
z

CL == 35pF

-

~
....

3.0

~

2.5

0

c
....
C

:J:

200

;:

t=
~

O
N
I

,---VAL = OV
TA = 250C

::E

y-

INPUT SWITCHING THRESHOLD vs
POSITIVE AND NEGATIVE SUPPLY VOLTAGES

r-...

150

'"w
...
"c0;
.......
II:

'OFF2

:J:

! 100
50

•olFl

~

'ON

:J:

;!!

,

<

>

-I
4
1.82
VAH - DIGITAL INPUT AMPLITUPE (VOLTS)

2.0
1.8
1.5
1.0
.5
0
5

7
~V

8
9
10
11
12
13
- POWER SUPPLY VOLTAGE (VOLTS)

14

15

CAPACITANCE vs ANALOG INPUT
CHARGE INJECTION vs ANALOG INPUT

I

50

t

3ti

I

rflOUT
dV...2.rL
g 40 I-~~t

~

30

~.

~

*

~~VA~

20
~ 10 r w 0 I-~ -10

':'

40

30 ../"""

./

./

-20

../

,
"0-40
~
~O

V+=+15V

-

".:,

~~:i~~~PFRIN = Oil

!::

~

VOoUT

./

26
-20

.

./

lI00"CLKdVO

~
1lz

-

15r-----

CDOFF or CSOFF

10

-50
-10

-5
0
+5
VIN - ANALOG INPUT (VOLTS)

+10

CDSOFF.

:" ...

O~==~==~====~~~====±==='~
-15
-10
-5
+5
+10
+15
VIN - ANALOG INPUT (VOLTS)

.\

OFF ISOLATION vs FREQUENCY
140

v+1=+\~

'00

z

0

80

§

80

~
....

--

.. "'1"-

---

~ou,.

VIN '"
t-

~

tf=l00n

1=~~Kn
-=

OFF ISOLATION ~ 20 LOG

.OK

I

VA-3V

lOOr---~~~++ttH---~~-++1HH~--~--~~+++H

~L·1Kn

40 )-

o

V!'!'~)

120r---+--++++++ft----+-+-++1f-H-++----+-~;;,:1~RMS

VA-3V

~

l!;

20

140r---~-r'-TTTTnr~-r-'~-rrn~--~--~rT"Tn

II

V-"'-15V
VIN-3VRMS

120

~

CROSSTALI( vs FREQUENCY,

.:.c

r-:......... -

VIN

Va

100K

1M

10M

f - FREQUENCY iHzl

3-23

SWITCHING CHARACTERISTICS
SWITCHING CHARACTERISTICS vs INPUT VOLTAGE

LOGIC INPUT

Typical delay, tON, tOFF, settling time and switching transients
in this circuit.
V+

3

= +15V

en
I--'

2

0

2:.

Va

OUT

I::::J

"N

RL

lK
LOGIC
INPUT

t.:>

r

'"--',
0

35PF

GND

V-

=-15V

-

0

:2

CL

«

>

to

If RL or CL is increased,there will be corresponding increases
in rise and/or fall RC times.
VO - OUTPUT SWITCHING WAVEFORMS

+10
+5

+5

VIN = +10V 0

VIN

= +5V

to

+5
VIN=OV

0

-5

-5

to

3-24

VIN

= -5V

SWITCHING CHARACTERISTICS (Continued)
VO - OUTPUT SWITCHING WAVEFORMS

o

VIN; -10V

-5

-10

APPLICATION INFORMA TION
LOGIC COMPATIBILITY

POWER SUPPLY CONSIDERATIONS

The HI-201HS is TTL compatible. Its logic inputs (Pins 1, 8,

The electrical characteristics specified in this data sheet are
guaranteed for power supplies of '±VS ; '±15V. Power supply
voltages less than '±15V will result in reduced switch performance. The following information is intended as a design
aid only;

9, 16) are designed to react to digital inputs which exceed a fix-

ed, internally generated TTL switching threshold. The H1201HS can also be driven with CMOS logic (0-15V), although
the switch performance with CMOS logic will be inferior to
that with TTL logic (0-5V).
The logic input design of the HI-201HS is largely responsible for
its fast switching speed. It is a design which features a unique
input stage consisting of complementary vertical PNP and NPN
bipolar transistors. This design differs from that of the standard
HI-201 product where the logic inputs are MOS transistors.
Although the new logic design enhances the switching sp,eed
performance, it also increases the logic input leakage currents.
Therefore, the H1-201 HS will exhibit larger digital input leakage
currents in comparison to the standard H1-201 product.

POWER SUPPLY VOLTAGES

SWITCH PERFORMANCE

.±.12 ~ .!.VS .;t15V

Minimal variation

'±'VS< ,±,12V

Parametric variation
becomes increasingly large
(increased ON resistance,
longer switching times).

'±'Vs < '±10V

Not recommended

SINGLE SUPPLY
CHARGE INJECTION

Charge injection is the charge transferred, through the internal
gate-to-channel capacitances, from the digital logic input to
the analog output. To optimize charge injection performance
for the H1-201HS, it is advisable to provide a TTL logic input
with fast rise and fall times,

The switch operation. of the HI-201HS is dependent upon an
internally generated switching threshold voltage optimized for
:!: 15V. power supplies. The H1-201 HS does not provide the
necessary internal switching threshold in a single supply system.
Therefore, if single supply operation is required, the HI-300
series of switches is recommended. The H1-300 series will
remain operational to a minimum +5V single supply.

If the power supplies are reduced from ±151t, charge injection
will become increasingly dependent upon the digital input
frequency. Increased logic input frequency will result in larger
output error due to charge injection.

Switch performance will degrade as power supply voltage is
reduced from optimum levels (± '1511). So it is recommended
that a 'single supply design be thoroughly evaluated to ensure
that the switch will meet the requirements of the application.

SCHEMA TIC DIA GilA MS
TTL/CMOS
REFERENCE CIRCUIT

SWITCH CELL

Vee

a
I
I
R41

I
I

I
I
I

ANALOG
OUT

-,I\NALOG
IN.'

I
I
I
I

I
I
I
I

u

DIGITAL INPUT AND
LEVEL SHIFTER

'--='+++--
ROSION) VS. VD AND
TEMPERATURE

I v+

RDSION) VS. VD AND
POWER SUPPLY VOLTAGE

RGEN"O

:!:

I
Yo _DRAIN VOLTAGE lVOLTI)

VII - DRAIN VOLTAGE (VOLTI)

IN

~~::v

II

"

Ii

...'"

Q~

=

10Kn

L
-'5V

tND

··
·

*':"

i
I

,

~c

OFF ISOLATION
VS. FREQUENCY

IHI"-"'.. HI..-

,'i'O;"i
I
I

~

i
~

9

II

z
. ;;

Al

I.

l

,

-...I

If RGEN. Rl or CL is increased, thare will be proportional
increases in rise andlor fall RC times.

;=~:~
e-

R~j I10PF
~CL

I
I
I

VOEN

DEVICE POWER DISSIPATION
VS. SWITCHING FREQUENCY
SINGLE LOGIC INPUT

I

D

,

VLOGIC

~~'--~-;"---±1---iO--~~'-~."~-d.~.

S

ttI-3Ot ..
1

1D

111.

·

HI~ruHI-3D7

'iYTI
I

ruHI~J
1DO

I
I

0

HI-3OII .... HI-303

.

."

10K

I." I.

LOGIC SWITCHING FREQUENCY 1Hz)

... """'CVCU

."H-,Io-++ok-+"'±'::'N'=":'---i
ISIOFF) OR IDIOFF)
VS. TEMPERATURE'

'U~~~_:~~~~w::~~~~~~
~
IVDI-IVsI"14V

~.~----~~~--~I.~--~

om.~

____~~~__~,.~__~
T _l'bPIRAYUIII! t-Cl

TEMf'EftATUltE--c

* The net laakage into the source or drain is the n-channellaakage minus the p-channal leakage. This difference can be positive,
negative, or zero depending on the analog voltage and temperature, and will vary greatly from unit to unit.

OUTPUT ON CAPACITANCE
VS. DRAIN VOLTAGE
~ Mr-r-~~~-'-'-'

~

i.
u

~

.~r-+-+-+-+-+-4-~

I .~+-+-+-+-+-4-4-~
§ ·~o-+,-+.-+.~.~u~,,~,,~u
\'D-DRAINVOLTACJIIVOLTil

"'~HE
~.,

IDION) VS. TEMPERATURE'

DIGITAL INPUT CAPACITANCE
VS.INPUTVOLTAGE

" .-,--,--,--.--.--.--,---,

""

i
CJ

I-

I II

,.L!TOT.. ,LLJOAJ

' : - - DUE

t

ACTIVE INPUr)

I

--

HI-k..!.HIJ.

~ 4~~*-~=t;~~~~~

II
01.

'~':'ii"i
•

•

•

VIN-IM'UT VOLTAGE

U

M

(VOL"

d

~.

:.
:.
:11
o

OA

0.8

I-Ti_(jJs)

3-30

1.2

1.6

HI-300 - HI-307

,....

TYPICAL PERFORMANCE CURVES (Continued)

o

~

Y+"+I5V
V---l&V
VIMf"4.ov
YINL-OV

f- >-"

f- ~f-

,

Iii

~L >-">-" --

+~

I

-_I-f

VINM-.'&V

--

Ii
211 4Ii 8& 8&
T _ TDl'ERATURE (OC)

-

v+"+'&V
V-"-I&V

VINL-OY

->-"

lG11 1211

-66-3&

-,s

I

. "r..

SWITCHING TIME ANO BREAK
BEFORE MAKE TIME VS.
POSITIVE SUPPLY VOLTAGE
HI-300 thru HI-303

SWITCHING TIME VS.
NEGATIVE SUPPLY VOLTAGE
HI-300 thru HI-303

SWITCHING TIME VS.
TEMPERATURE
HI-304 thru HI-307

SWITCHING TIME VS.
TEMPERATURE
HI"300 thru HI-303

--!!.
"'''

--

..

....v

"

SWITCHING TIME VS.
NEGATIVE SUPPL Y VOLTAGE
HI-304 thru HI-307

I-~-+~-~~:~

\

Ii
'0
'6
y- NEUATIYESUI'PLVVOLTAGEf\/I

v+

Ii

INPUT SWITCHING THRESHOLD

vs. POSITIVE SUPPLY VOLTAGE
HI-300 thru HI-307

HI-3I)I"", HI407.o111t1!

Y-"-ISV
T ... -2IIDC

\.
o

o

"

v+ I'OIITIVlaI'ft,YM

-

VINH"'&V

t-~-t~-vtNL·OY

10

POSITIV£IUPPLYVO~TAOEIVI

o

I

10

11

V+ POIfTlVESWl'LYVOLTAOE!VOLTSI

11

SCHEMATIC DIAGRAMS
SWITCH CELL

DIGITAL INPUT BUFFER
AND LEVEL SHIFTER

.-~~~~~~~~~~~~

V+O-~~~~~~~~~~~t-~~-1~~~~~~~~~-t~~~-t~~~~---+--~~,

oz.
zoo 0

LOGIC IN 0---../1111'-+.......

01.

GNOo-------~----~+---~--~----~

V·o-------~--------------------------~----------~----~~----~--_+----~
SWITCH CELL
DRIVER
(ONE PER SWITCH CELL)

I

I

...::::I

-

.c
o
o

~
I

\

-.

Y'NL"i

V.NEGATlVESUl'f'LY!VOLTI)

SWITCHING TIME VS.
POSITIVE SUPPLY. VOLTAGE
HI-304thru HI-307

_·w

VIl... ·"4.O\I'

,'-. ...
. ...,,.. ..., ~

T".2IIIC
VINIH"""

.

T,,-2IIC

~

-V+-,&V

• • '.'21

T .. TEMP£RAruRE lat,

I
Y·-.'IV

A

l-:

HI·381/384/
387/390

m'HA.RRIS

CMOS Analog Switches
FEATURES
•
•
•
•
•
•
•
•
•

APPLICATIONS

ANALOG SIGNAL RANGE (±15V SUPPLIES)
LOW LEAKAGE (TYP. @25 0 C)
LOW LEAKAGE (TYP @125 0 C)
LOW ON.RESISTANCE (TYP. @25 0 C)
BREAK-BEFORE-MAKE DELAY (TYP.)
CHARGE INJECTION
TTL COMPATIBLE
SYMMET.RICAL SWITCH ELEMENTS
LOW OPERATING POWER (TYP.)

±15V
40pA
InA
35rl
60ns
30pC

•
•
•
•
•

SAMPLE AND HOLD i.e. LOW LEAKAGE SWITCHING
OP AMP GAIN SWITCHING i.e. LOW ON RESISTANCE
PORTABLE BATTERY OPERATED CIRCUITS
LDW LEVEL SWITCHING CIRCUITS
DUAL OR SINGLE SUPPLY SYSTEMS

DESCRIPTION

1.0mW

The HI-381 through HI-390 series of switches are monolithic
devices fabricated using CMOS technology and the Harris dielectric isolation process. These devices are TTL compatible and
are available in four switching configurations. (See device pinout
for particular switching function with a logic "I" input,)

FUNCTIONAL DIAGRAM
...------0() S

These switches feature low leakage and supply currents, low and
nearly constant 0 N resistance over the analog signal range, breakbefore-make switching and low power dissipation.

IN

L-------l~o

The HI-381 and HI-387 switches are available in a 14 pin epoxy
or ceramic DIP orl0 pin metal can. The HI-384 and HI-390
are available in a 16 pin epoxy or ceramic DIP. Each of the
individual switch types are available in the -55 0 C to +125 0 C
and OOC to +75 0 C operating ranges.

0

TYPICAL SWITCH - JOO SERIES

PINOUTS

(SWITCH STATES ARE FOR A LOGIC "I" INPUT)
DUAL SPST HI-381

SPOT HI-J87

(TOP VIEWS)

(TOP VIEWS)
D2

DIP

DIP

NC

*The substrate and case are

*The substrate and case are
internally tied to V-.
(The
case sh OU Id not be used as
the V- connection, however.)

internally tied to V-.

case should

(The

not be used as

the V- connection, however.)

,DUAL DPST HI-J84

DUAL SPOT HI-J90

(TOP VIEW)

(TOP VIEW)

DIP

3-32

SPECIFICA T/ONS

o

en

ABSOLUTE MAXIMUM RATINGS (Note 1)

C")

........

44V (±22)

Voltage Between Supplies

Total Power Dissipation
14 Pin Epoxy DIP
14 Pin Ceramic DIP
16 Pin Epoxy DIP
16 Pin Ceramic DIP
10 Pin Metal Can*
*Derate 6.SmW/oC above TA = 70 0 C

Digital Input Voltage
V++4.0V
V- -4.0V
Analog Input Voltage

526mW
588mW
625mW
685mW
435mW

CO
C")
........

o::t

CO
........
C")
'I"'"

CO

C")

V++1.5V
V-' -1.5V
Storage Temperature Range

r-..

I

Operating Temperature
H1-3XX-2
HI-3XX-5

-65 0 e to +150 oe

-55 0 C to +1250 C
ooe to +75 0 e

ELECTRICAL CHARACTERISITICS Unless otherwise specified; Supplies = +15V, -15V; VIN = Logic Input,
VIN for logic "1" =4V, for logic 0 =.8V
·55 0 C to +125 0 C
PARAMETER

TEMP

MIN

TYP

MAX

OOC to +75 0 C
MIN

TYP

MAX

UNITS

C!l
0(1.)

-'w

ANALOG SWITCH CHARACTERISTICS
Analog Signal Range

FULL

RON ON Resistance (Note 2)

+25 0 C
FULL

-15
35
40

50
75

35
40

50
75

n
n

ISOFF OFF Input Leakage Current (Note 3)

+25 0 C
FULL

.04
1

1
100

.04
0.2

5
100

nA
nA

IDOFF OFF Output Leakage Current
(Note 3)

+25 0 C
FULL

.04
1

1
100

.04
0.2

5
100

nA
nA

lOON ON Leakage Current (Note 4)

+25 0 C
FULL

.03
0.5

1
100

.03
0.2

5
100

nA
nA

.8

V
Il A
Il A

+15

-15

+15

V

DIGITAL INPUT CHARACTERISTICS
VINL Input Low Level

FULL

VINH Input High Level

FULL

IINH Input Leak. Current (High) (Note 5)

FULL

1

1

IINL Input Leak. Current (Low) (Note 5)

FULL

1

1

.8
4

4

SWITCHING CHARACTERISTICS
(HI-387/
tOPEN, Break-Before Make Delay 390 only) +25 0 C

60

V

ns

60

tON, Switch ON Time

+25 0 C

210

300

210

300

tOFF, Switch OFF Time
OFF Isolation (Note 6)

+25 0 C

160

250

160

250

+25 0 C

Charge Injection (Note 7)

+25 0 C

60
3

CSOFF Input Switch Capacitance

+25 0 C

16

16

dB
mV
pF

CDOFF Output Switch Capacitance

+25 0 C

14

14

pF

COON Output Switch Capacitance

+25 0 C

35

35

pF

CIN (High) Digital Input Capacitance

+25 0 C

5

5

pF

CIN (Low) Digital Input Capacitance

+25 0 C

5

5

pF

1+ Current (Note 8)

+25 0 C
FULL

.09

.5
1

.09

.5
1

rnA
rnA

1- Current (Note 8)

+25 0 C
FULL

.01

10
100

.01

100

IlA
Il A

1+ Current (Note 9)

+25 0 C
FULL

.01

10
100

.01

100

IlA
IlA

1- Current (Note 9)

+25 0 C
FULL

.01

10
100

.01

100

IlA
IlA

60
3

ns
ns

POWER REQUIREMENTS

"3-33

«:r:
2<..>
«I~~

::;;:(1.)
<..>

ELECTRICAL CHARACTERISTICS NOTES:
1. As with all semiconductors, stresses listed under "Absolute
Maximum Ratings" may be applied to devices (one at a time)
without resulting in permanent damage. This is a stress rating
only. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. The conditions
listed under "Electrical Characteristics" are the only conditions
recommended for satisfactory operation.
2. Vs = ± 1OV, 10 UT = -10mA on resistance derived from the
voltage measured across the switch under the above conditions.

5. The di.gital inputs are diode protected MOS gates and typical
leakages of 1nA or less can be expected.
6. Vs = 1VRMS, f = 500kHz, CL = 15pF, RL = 1k,
CL = CFIXTU RE + CPR OBE, "off isolation" = 2010g VSIVo·
7. Vs = OV, CL = 10,OOOpF, Logic Orive = 5V pulse. Switches
are symmetrical; Sand 0 may be interchanged.
8. VIN = 4V.

(one input) (all other inputs = 0)

9. VIN = O.8V. (all inputs)

3. VS='±14V,VO=+14V.

10. To drive from OTL/TTL circuits, pull-up resistors to +5V
Supply are recommended.

4. VS=VO=.:t14V.

TEST CIRCUITS

BREAK-BE FORE-MAKE TEST CIRCUIT (tBBM)

SWITCHING TEST CIBCUIT (tON, tOFF)

SWITCH TYPE
5V

HI-381 thru HI-390

SWITCH TYPE

VINH

HI-387 and HI-390

5V

+15V
V+

o-----1!---()..~

VSl =+3V

o-+-O------r-r-<' OUT 1

VS2= +3V

V-

LOGIC
INPUT

,-1SV

LOGIC "1" "" SWITCH ON*
LOGIC OV
INPUT

SWITCH

OUTPUT

ov

~

50%

~!-':5:...0%~

_ __

lOGIC

:~,O%"

---ItoN~

---t tOFF

RU = RL2 = 300n:
CL1=CL2=33pF

LOGIC "1" SWITCH ON

r--l
ov--1
L--

INPUT

-----+J
i :!
I:

r r

VINH

~
I

50%
ov __ _ _ _~f:
,

!--

*Inverted logic for HI-381

SWITCH
OUTPUT

,

'\.50%'
OV

t88M

3-34

'\.~OUTl
50%

, fo°UT2
,

~\..-+;------I-!~ : 50%

---!

r-

--i

t--

t88M

TYPICAL PERFORMANCE CURVES
ROS(ON) VS. Vo AND
POWER SUPPLY VOLTAGE

ROS(ON) VS. Vo AND
TEMPERATURE
V+-+15V

o0)

M

,...

CO

V-"-16V

~

t-

r--.:.: ;:::
0

-

''''

..soc

10

~

0

CO
M

::::::E::::

'2SOC

r--

o::r

......

"""

CO
M

A Vt-.,5V, 11---15V
B V+" +10V, V-" -lOV
C V+-+7.5V, V---7.511

+15

I

~~,~D~V~"~~~V~'~:~'~"~V~O____~~~__~__~

Vo -DRAIN VOLTAGE (VOLTS)

VO-ORAINVDLTAGE (VOLTS}

DEVICE POWER DISSIPATION
VS. SWITCHING FREQUENCY
SINGLE LOGIC INPUT

F~~:~~:~

OFF ISOLATION
VS. FREQUENCY

f-- TA-25OC

I-- Vs~ 15V
RL~

I

2k

f--

/

0

;;;

'00

"oz
~

~

II

60

./

0

~

t.:l
0",

I

-'U,J

~" r-::.:..,oon I
r--RL"~
v+ .. t15J. v-" -15V


I-

::J

..
0

rrGTr

::J

~

VINL"r
v-

.

~

V+=+15V

0

>

,

0

I
I

u;

TA=25OC
VtNH .. .f

InA

V

~

«
w

ON LEAKAGE CURRENT
vs. TEMPERATURE

IOION)
./

...J

;-

100pA

10pA . /

OUT

IN

V

......
50°

25°

75°

100°

125°

.210 (ON)

TEMPERATURE - °c

-=~

:tl0V

NORMALIZED "ON" RESISTANCE
vs. ANALOG CURRENT
1.4
w

t.)

z

~

"ON" RESISTANCE
vs. ANALOG CURRENT

_ 1.3

.,,<

Cii e
w a:o

I- 1.2
20
Slw
a:
oa:
Ww
Nu.. 1.1
-....I w
a:

.1
I
.i

.

<::;;
a:
0

z

1.0
0

±YIN

-

.........

20
40
60
ANALOG CURRENT - rnA

o
'11:1'
oII)

80

3-43

IN 0 - 0

VIN
RON=!

oorl ~

I

;10V

CHARA~TER/ST/CSAND

PERFORMANCE

"OFF" ISOLATION

TESTC/RCWTS (continued)

FREQUENCY

VS.

-20 0

~ -16 0

z

a

;:: -12 0

:5

Rl ~ lOOn

~
~

~

a

....... 1--8 0

"OFF··ISOlATlON

I-

--

~ 20 IOg(~)
VOUT

Rl

-4 0

~

~
10Kn

f
IIIIIIIIlOOK

I 1111111
10

100

lK
10K
FREQUENCY - Hz

·CROSSTALK

VS.

1M

FREQUENCY

20 0

16 0

,

1"-,

.r-.
,

12 0

r-...

i'-

r-...

,

Rl

~

lOOn

ff1IlIL.1

I

[l1tffi-lJ

0

r-...
0

i 11111

'--_ _ _ _ _.... RL

r-...

Rl ~ lKn

~

I I

"CROSSTALK·· ~ 20

IOg(~)
VOUT

InntI-+-I.
Rl 10Kn
~

: 11111
0

10

100

I I

11111110K II

lK
FREQUENCY - Hz

1M

lOOK

POWER CONSUMPTION vs. FREQUENCY
20 0

+10V

16 0

0-+--04"-;-0-----11-1

-10V 0--+--.(1

1
V

12 0

TOGGLE
AT 50%
OUTY

I

0

/

0

,

o~'
\ lK

-

-

/

+5V

V

10K
lOOK
TOGGLE FREQUENCY 150% DUTY CYCLE) - Hz

1M

3-44

+15V -15V

SWITCHING CHARACTERISTICS
ON/OFF SWITCH TIME
VS. LOGIC LEVEL

~I

+10V

lK

C!l
SWITCHING TIMES FOR POSITIVE DIGITAL TRANSISTION

120

120

660

480

/

600

oS:

::;;:en
U

540

\

420
360

«:I:
2U
«Ien -

660

600
540

°en
.....leu

SWITCHING TIMES FOR NEGATIVE DIGITAL TRANSISTION

\

'""""

300
240

r.........

180
120

--

420

r

-

300

r--~

240

3.GV

4.2V

4.8V

L

I
tOFF

-r-r

60
3.0V

tON

I

180
120

2.4V

/

I

360

tON

1/

5V~V AH~2.4V

480

1.5V ~V Al~OV

./'

-- --

O.5V

OV

lOV
DIGITAL "LOW" (VAL)

SWITCHING WAVEFORMS
TOP: CMOS INPUT (5V /DIV)

TOP: TTlINPUTOV/DIV)
VAH = 3V. VAL = O.8V
BOTTOM: OUTPUT (5V/DIV)

VAH = 10V, VA.L= OV
BOTTOM: OUTPUT (5V/DIV

h

~'

.....

r

,

\

\

I

V

/

60

OIGITAl"HIGH" (VAH)

-

J

V
~

I

~

200ns/OIV

200ns!DIV

3-45

1.5V

SCHEMA TIC DIAGRAMS
SWITCH CELL

TTL/CMOS
REFERENCE CIRCUIT*

R3

v+

RI
200n
TO P2

vIN

v-

R2
9K

'----_--~---'VVI~~'"

200.11

ALL N-CHANNEL
BODIES TO V-

OUT

v-

ALL P-CHANNEL
BODIES TO V+
EXCEPT AS SHOWN

3-46

Product Index

4-2

Ordering Information

4.;03
~

Standard Products
Packaging ~vanabmty

xw
w

4-3

"

Selection Guide

4-4

Product Information

4-5

ABSOLUTE MAXIMUM RATINGS
As with al/ semiconductors, stresses listed under "Absolute Maximum Ratings"

may be applied to devices (one at a time) without resulting in permanent damage.
This is a stress rating only. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. The conditions listed under
"Electrical Characteristics" are the only conditions recommended for
satisfactory operation.

4-1

~

:;)

:Ii

Product Index
Page
HI-S06/HI-S07

..

S~~9Ie';,t~pi!f~fi~riti.~y!$:qha'~·nel;~M6~;\nal~g·~.Ulti~lexers ... ;.:?::~::;;.:.,.:;!: ......;.;.::.~: .. ;.•:. . 4~Q
Slt1gIeI1~fi;jJtfer~ntlal~8qpanneL CMPS Analpg~Mu Ittplexers. Wtll'h ActiVeOvervqltage :.;

H I-S06A/H 1-507A

proti!qii~~:.; .. ;';.;;. ':,~ .• """,;, ,.'.. ;.;.....• ::~~t'.';~:;:> .... ;;:'.::.. ;: ....... ,........ ,....• "::.' ":'.' J": .:. :.. ;~:. ;i'~'''''' ',"

. ;'

HI-S06LAlHI-S07L~.'13ingle:16/Differential 8' ChanoetiCMOS Analog, Multiplexers

HI-S08/HI-S09

.with

....".~~-, ~.'" ".

.LatchEisand'

i1!~:,;~f~!~;:~j~:;;~:;~~i.:~~.~~·~·~~;·~~~:··~;;i§·~~~~·I~;·~I::~~~~:::::::;:.:,:::::~;:;::;:::::::·::::::::',::::::;.4.18'

'HF,;50MiHI:S09A, ,"

Single a/Differential' 4' 'Channel CMOS Analog Multiplexers with Active Overvoltage
Protection .,., ... ,.. ,........ ', .................... ,.. ,.. ,......... ,."., ..................... ,........................ ,................... 4-2S

HI-S08LA/HI-S09LA

Single 8/Differential 4 Channel CMOS Analog Multiplexers with Latches and
Overvoltage Protection ............................................................................................................ 4-31

HI-S16

16 Channel/Differential 8 Channel CMOS High Speed Analoll, Multiplexer .................... 4-32

HI-S18

8 Channel/Differential 4 Channel CMOS High Speed Analog Multiplexer ...................... 4-37

HI-S24

4 Channel Video Multiplexer .................................................................................................. 4-42

HI-S39

Monolithic, 4 Channel, Low Level, Differential Multiplexer ................................................ 4-47

HI-S46/HI-S47

SinglJ'16iDifferential 8 Channel CMOS Analog Multiplexers with Active Overvoltage
Protection ................................................................................................................................. 4-S6·

HI-S48/HI-S49

Single 8/Differential 4 Channel CMOS Analog Multiplexers with Active Overvoltage
Protection ........................................................................,.... ;........................: ..... :..................... 4-62

HI-1818A/1828A

Low On

HY-9S9S/9S96

Differential 8-Bit/Single 16-Bit Multiplexer with Programmable Gain Amplifier .............. 4-72

R,~sistance

Single 8/Differential,4 Channel CMOS Analog Multiplexers ........... 4-68

. ';."

4-2

Ordering Information
HARRIS PRODUCT CODE EXAMPLE

H

I

0506 -

1

5

--r

-r-

PREFIX: _ _ _ _ _ _T..J

T

PART NUMBER

H (HARRIS)

TEMPERATURE:
OOC to +200o C *
-550C to +12S oC

FAMILV:-----'J
A
Analog
C
Commul"ications
o
Digital
F Filters
I Interface
M Memory
V
Analog, High Voltage
Y
Analog Hybrids
PACKAGE:
1 3 4 4P -

o

-

-250C to +85 0 C
aOc to +7S o C
100% +2So C Probe (Dice Only)
Oash-7 High Reliability Commercial
Product. OOC to +7S o
Dash-a Program
-40DC to +8S0 C

c

-----'
Dual-ln-Line, Ceramic
Dual-In Line, Plastic
Leadless Carriers (LeG)
Plastic Leaded Chip Carrier (PLCC)
Lee Hybrid
Mini-DIP, Ceramic
Chip Form

*

Special high temperature testing available
on certain product types. Consult factory for
availability.

Standard Products Pac.kaging Availability
PACKAGE

PLASTIC
DIP

SURFACE MOUNT

CERAMIC
DIP

LCC

PLCC

-5

-2

-4

-5

-7

-8

-8

-5

HI-OS06
HI-OS06A

X
X

X
X

X

X
X

X
X

X
X

X
X

X

HI-OS07
HI-OS07A

X
X

X
X

X

X
X

X
X

X
X

X
X

X

HI-OS08
HI-OS08A

X
X

X
X

X

X
X

X
X

X
X

X
X

X

HI-OS09
HI-OS09A

X
X

X
X

X

X
X

X
X

X
X

X
X

X

HI-OS16
HI-OS18

X
X

X
X

X
X

X
X

X
X

HI-OS24
HI-OS39

X
X

X
X

X
X

X
X

X
X

X
X

HI-1818A
HI-1828A

X
X

X
X

X
X

X
X

X
X

X
X

HI-OS46
HI-OS47

X
X

X
X

X
X

X
X

X
X

X
X

X
X

X
X

X
X

X
X

*
*
*
*

X
X

HI-OS48
HI-OS49

*
*
*
*

TEMPERATURE
DEVICE NUMBER
MULTIPLEXERS

'Available as MIL-STD-883 Only:

4-3

X

x

Selection Guide
CMOS MULTIPLEXERS

FUNCTION

OEVICE

TTL
'HIGH'
MIN(V)

RON(Il)
(TYP)

IO(OFF)
(nA)
(TYP)

'(ON)
(ns)
(TYP)

'(OFF)
(ns)
(TYP)

Low RON
Low Leakage

4.0

2S0

O.OS

3S0

2S0

FEATURE
)

4-Channel
Differential

8-Channel

8-Channel
Differential

HI-1828A

Po(mW)
(TYP)
S

.lRON
(TYP)

PAGE

N/A

4-68

HI-S09

Low RON

2.4

180

0.3

2S0

2S0

23

5%

4-18

HI-S09A

Analog Input
Overvoltage Protection

4.0

1.2K

0.3

300

300

7.S

N/A

4-2S

HI-S49

Analog Input
Overvoltage Protection
with Low .lRON

4.0

1.2K

0.3

300

300

7.S

7%

4-62

HI-S09LA
Advanced

Address Latches and
Overvoltage Protection

2.0

lK

2.0

SOO

SOO

40

N/A

4-31

HI-1818A

Low RON
Low Leakage

4.0

2S0

0.1

3S0

2S0

S

N/A

4-68

Max

HI-S08

LOiN RON

2.4

180

0.3

2S0

2S0

23

5%

4-18

HI-S08A

Analog Input
Overvoltage Protection

4.0

1.2K

0.3

300

300

7.S

N/A

4-2S

HI-S48

Analog Input
Overvoltage Protection
with Low .lRON

4.0

1.2K

0.3

300

300

7.S

7%
Max

4-62

HI-S08LA
Advanced

Address
Address Latches and
Overvoltage Protection

2.0

lK

2.0

SOO

SOD

40

N/A

4-31

HI-507

Low RON

2.4

180

0.3

250

250

30

5%

4-S

HI-507A

Analog Input
Overvoltage Protection

4.0

1.2K

0.3

300

300

7.5

N/A

4-11

HI-S47

Analog Input
Overvoltage Protection
with Low .lRON

4.0

1.2K

0.3

300

300

'. 7.5

7%

4-56

Address Latches and
Overvoltage Protection

2.0

HI-S07LA
Advanced

Max
lK

2.0

500

500

60

N/A

4-17

HI-S06

Low RON

2.4

180

0.3

2S0

250

30

N/A

4-5

HI-506A

Analog Input
Overvoltage Protection

4.0

1.2K

0.3

300

300

7.5

N/A

4-11

HI-S46

Analog Input
Overvoltage Protection
with Low .lRON

4.0

1.2K

0.3

300

300

7.S

7%
Max

4-56

HI-S06LA
Advanced

Address Latches and
Overvoltage Protection

2.0

lK

4.0

SOO

SOO

60

N/A

4-17

8-Channel
4-Differential

HI-S18
Low Leakage

High Speed

2.4

480

0.1

80

80

360

N/A

4-37

16-Channel
8-Differential

HI-S16
Low Leakage

High Speed

2.4

620

0.03S

100

80

S2S

N/A

4-32

4-Channel

HI-S24

Video
Bandwidth

2.4

700

0.2

180

180

S40

N/A

4-42

4-Channel
Differential

HI-S39

Low Level
Signals

4.0
RON
= 411

6S0
ID(OFF)
= .003

0.03

2S0

160

2.S

0.6%

4-47

8-Differential

HY-9S95
Advanced

I n put Overvoltage
Protected, Latched
Programmable. Gain

4.0

1.2K

0.3

TBD

TBD

TBD

N/A

4-72

16-Channel

HY-9S96
Advanced

Input OV
Protected, Latched
Programmable Gain.

4.0

lK

0.3

TBD

TBD

TBD

N/A

4-72

16-Channel

4-4

II HARRIS

HI·506/507
Single 16/Differential8 Channel
CMOS Analog Multiplexer

Features

Description

• Low On Resistance (lYp.) .•.•.•...•.•..• 1800

These monolithic CMOS multiplexers each include an array of sixteen analog
switches, a digital decode circuit for channel selection, voltage reference for logic
thresholds, and an ENABLE input for device selection when several multiplexers are
present.

• Wide Analog Signal Flange •.•.•..••.••• ±lS V
• TTUCMOS Compatible •.•.•.. 2.4 V (logic "1")
• Access Time (lYp.) ••••.••.••..•••.••• 2S0 ns
• 44 V Maximum Power Supply
• Break.Before-Malre Switching

• No Latch-up

The switching threshold for each digital input is established by an internal +5 V
reference, providing a guaranteed minimum 2.4V for ''1'' and maxiinum 0.8 Vfor "0".
This allows direct interface without pullup resistors to signals from most logic families:
CMOS, TTL, DTL and some PMOS. For protection against transient overvoltage, the
digital Inputs include a series 2000 resistor and diode clamp to each supply.

• Replaces DGS06AJDGSOIAA and
DGS07A1DG507AA

The HI-50S is a sixteen channel single-ended multiplexer, and the HI-507 is an eight
channel differential version. Each device is available in a 28 pin ceramic or plastic
DIP, a 28 pin ceramic LCC or 28 pin plastic LCC (PLCC) package. The recommended supply voltage is ±15 V, and reasonable performance is available down to ±7 V.
If Inputovervoltage protection is needed, the HI-506AJ507A multiplexers are recommended. For further informafon see Application Notes,520 and 521.

Applications
• Data Acquisition Systams
• Precision Instrumentation
• Demultlplexing

The HI-5061507 is offered In both commercial and military grades. For additional
Hi-Rei screening including 160 hour bum-in specify the .. -8" suffix. For MIL-STD-883
compliant parts, request the 5061883 o,r 507/883 data sheet.

• Selector Switch

Pinouts

...,..-v--;21

2

26
25
2'
23
22
21

IN 12
IN 11
IN 10
IN 9
GND
NC
ADDRESS A3

20
10
II
12
13

19

I!
11
16
IS

I'

Functional Diagrams

m$!;::::~~;!:~

lbpVIew
.Vsupp
NC'
NC
IN 16
IN 15
IN 14
IN 13

The Dielectric Isolation (01) process used in fabrication of these devices eliminates
the problem of latchup. Also, 01 offers much lower substrate leakage and parasitic
capacitance than conventional junction-isolated CMOS (See Application Note 521).
With the low ON resistance (1600 typical), this allows low static error, fast channel
switching rates, and fast settling.

!:~!:~3!~~
,VSUPP
1MB
IN 1
1MB
IN S
IN'
IN 3
'IN 2
IN I
ENAILE
ADDRESS Au
ADDRESS AI
ADDRESS A2

oJ~:df.;;:===:l-oOUT
I

IN I

OUT

h

IN2

GND
NC

IN 16
NC

Aa

NC

A,
A,

+SUPPlY
OUT
V SUPPlY
IN8

Ao
ENABLE

l ___

••
•

IN 16

DECODER

DRIVER

L. ___

~N(f)""U')CO'"

~~:iJ!5~~;!;:!5

,HI4-S06(~

Hll-S06 (ceremic)
HI3-S06 (plastic)

H14P506 (P

AD AI A~ "3 EN

C)

HI-501

~~~~f8m~

Top View

~~:!::!:iE~!:

·"supp
OUT 8
NC
IMBB
IN18
IN 68
lUI
nUB
IN 31
lUI
IN II
GND
NC
NC

OUT A
27

-"supp

26

INIA

25

'N1A

2'
23
22
21

IN 6A
IN 5A

IN 4A

20

IN 3A
IN 2A

10

19

IN IA

"

IB
11

ENABLE
AOORESS AD
ADDRESS AI
ADDRESS A2

12
13
I.

16
IS

OUT A

IN8B

GND
NC
NC
A,
A,

NC

IN 18

OUT 8

OUlB
+SUPPl'ri
aUlA
-SUPPLY
INBA

Ao
ENABLE

:;q5;;1j~:i1i~;e:
~~~~~iE~

Hll-S07 (ceramic)
,HI3-507 (plastic)

HI4-S07 (LCC)
H14P507 (PLCC)

4-5

ADA, A2

HI-507

EN

HI-506l507 Specifications
ABSOWTE MAXIMUM RATINGS (Note 1)
VSupply(+) to VSupply (-)
VSupply(+) to GND
VSupplyH to GND
Digital Input Overvoltage:
VEN, VA {VsuPPI Y(+)
VSuppIYC-)

Continuous Current, S or D:
20 rnA
Peak Current, S or D
(Pulsed at 1 ms, 10% dutv cycle max): 40 rnA
Power Dissipation* (Cerdip)
1.96 W
Operating Temperature Range:
HI--506lS07-2,-S
-SsoC to +12SoC
HI-S06lS07-4
-2SoC to +SsoC
HI-S06lS07-S
OOC to +7SoC
Storage Temperature Range -6S~C to +1S0oC

44V
22V
2SV
+4V}
-4 V

or 20 rnA, whichever occurs first.
Analog Signal Overvoltage (Note 7)
VD, Vs {VSUPPIY(+)
VSuppIYC-)

*Derate 19.6 mW/oC above TA =7SoC,

+2V}
-2V

ELECTRICAL CHARACTERISTICS Unless Otherwise Specified:
Supplies= +1S V, -1S V; VAH(Logic Level High) = +2.4 V, VAL
(Logic Level'Low) = +O.S V. For Test Conditions, consult Performance Characteristics Section.
HI-506IHI-507

-2, -8
PARAMErER
ANALOG CHANNEL CHARACTERISTICS
"VS, Analog Signal Range
"RON, On Resistance (Note 2)
""RON, (Any Two Channels)
"IS (OFF), Off Input Leakage Current (Note 3)

"10 (OFF), Off Output Leakage Current (Note 3)

HI-506/501
-4, -5

TEMP. MIN. TYP. MAX. MIN. TYP. MAX. ~NITS
HI~506

Full
-15
+25°C
Full
+25°C
+25°C
Full
+25°C
Full
Full
+25°C
Full
Full
Full

180

+15
300
400

5

-15
180

+15
400
500

5
000

OD3
50

50

0.3
0.3
HI-506
300
300
HI-507
200
200
0.3
"10 (ON), On Channel Leakage Current (Note 3)
0.3
300
HI-506
300
HI-507
200
200
50
50
"IDIFF. Differential Off Output Leakage Current
(HI-507 Only)
DIGITAL INPUT CHARACTERISTICS
*VAL, Input Low Threshold
Full
+0.8
+0.8
*VAH;, Input High Threshold
Full
+2.4
+2.4
1D
"IA Input Leakage Current (High or Low) (Note 4) Full
1D
SWllCHING CHARACTERISTICS
250 500
250
"tA, Access TIme
+25°C
1000
Full
1000
25
80
"tOPEN, Break-Before-Make Delay
+25°C 25
80
250 500
250
"toN (EN), Enable Delay (ON)
+25°C
Full
1000
1000
250
250 500
"toFF (EN), Enable Delay (OFF)
+25°C
Full
1000
1000
1.2
Settling Time (0.1%)
1.2
+25°C
2.4
(OD1%)
2.4
+25°C
"Off Isolation" (Note 5)
68
50
68
+25°C 50
Cs (OFF), Channel Input Capacitance
5
+25°C
5
44
44
CD (OFF), Channel Output Capacitance HI·50S +25°C
HI-507 +25°C
22
22
CA, Digital Input Capacitance
5
+25°C
5
0.08
ODS
CDS (OFF), Input to Output Capacitance
+25°C
POWER REQUIREMENTS
"I +, Current, Pin 1 (Note 6)
Full
1.5
1.5 ao
"1-, Current Pir127 (Note 6)
Full
0.4
1D
0.4
1D
'

TRUTH TABLES

ao

V
11
11
%
nA
nA

nA
nA

nA
nA

nA
nA
nA

V
V
pA
ns
ns
ns
ns
ns
ns
ns

"s
"s

dB
pF
pF
pF
pF
pF
mA
mA

"ON"

As A2 A1 AD EN CHANNEL
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
,H

X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

A2
X
L
L
L
L
H
H
H
H

A1
X
L
L
H
H
L
L
H
H

AD

EN

X
L
H
L
H
L
H
L
H

L
H
H
H
H
H
H
H
H

1. Absolute maximum ratings are "mliing values, applied individually.
beyond which the serViceability of the CirCUIt may be ImpaIred.
Functional operation under any of Ihese conditions IS not necessarily
Implied.

5. VEN O.BV. RL lK. Cl 15pF. Vs 7VRMS. f 100kHz. Worsl case ISOlallon occurs on channel BS due to proximity of the output pins.

2 "OUT .!lOV. lOUT ·lmA.
3. 10nA.IS the practical lower limit for high speed measurement In the producllon test environment
4. Digital Input leakage IS primarily due to the clamp diodes (see Schematlc). TYPical leakage IS less than InA at 2SoC.

7 Signal voltage at any analog Input or output (S or D) Will be clamped to
the supply rail by Internal diodes. limit the resulting current as snown
under Absolute MaXimum Ratings. If an overvoltage condition IS antlclpated (analog Input exceeds either power supply voltage). the Harris
HI-SOSA/S07A m!-lltlplexers are recommended.

6. VEN. VA

4-6

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

NONE
1
2
3
4
5
6

7
8
9
10
11
12
13
14
15
16

HI-507

*100% tested for Dash 8. Leakage currents not tested at _55°C.
NOTES:

L

L H

OV or 2.4V.

ON
CHANNEL
PAIR
NONE
1
2
3
4
5
6

7
8

HI-506/507

r--.

Performance Characteristics and Test Circuits
ON RESISTANCE vs.
INPUT SIGNAL LEVEL, SUPPLY VOLTAGE

Unless Otherwise Specified; TA = 25°C, VSupply = ±15 V,
VAH = 2.4 V, VAL = 0.8 V.

o

II)

CD

o

II)
I

TEST CIRCUIT
NO.1

VS.

ON RESISTANCE
ANALOG INPUT VOLTAGE, TEMPERATURE

NORMALIZED ON RESISTANCE
VS. SUPPLY VOLTAGE

400

2.2
+ 125 0 C?:. TA?:. -550C

:; 2.0

~

S
~
~
~

TA"'+125 0 C

200
TA",+25 0 C

.j
0:
~

--

300

TA =

0

>

-55 0 C

.e

1,2

~

1.0

:5

o

·5

-'0

-'5

0

'5

...........

-.......

0.8
0.•

, '5

"0

"'"

~ 1.4

~

I--

'00

~

OV

"-

~ 1.6

.......

~

I--

VIN

"~ 1.8

,./' V

±9

~7

±1O

VIN Analog Input(Volts)

--

!11

t12

!13

±14

±15

Supply Voltage (Volts)

LEAKAGE CURRENT VS. TEMPERATURE
IDOnA

TEST CIRCUIT
NO. 2*

~I

IOnA

1f31
N

./

OIfOutpul

10 (O"~~~o(Qn)

:.

On Le::r
-

Current

+lOV

V

/'

'"A

/

/

100pA

'O.BV

OUT

~LeakageCurrent

r-----

TEST CIRCUIT
NO. 3*

OUT

A 'OiOFF)

-=-

-=- :;:10V

l-=-

TEST CIRCUIT
NO. 4*

I'" ~!~~::eu~urrent -

±10V

-=-

I .i

T-=-

EN

"Two measurements per channel:
+10 V/-10 V and -10 V/+10 V.
(Two measurements per device for IO(OFF)
+10 V/-10 Vand -10 V/+10 V.)

IS {Off)

IOpA
15"

50"

15"
TemperatureOC

"

100 0

125

..I.
+2.4V

LOGIC THRESHOLD
VS. POWER SUPPLY
VOLTAGE

POWER SUPPLY
CURRENT
VS. TEMPERATURE

OFF ISOLATION VS.
FREQUENCY

3. 0

'00
I
80

-

-

f--

,

VEN

0

~

60

2.4V-

±6 ±8

tl0 tlZ

t14 t16 t18 tzp

ov

40

rno

Power Supply Voltage (Volts)

20

o

o
-55 -35 -15 -5

25 45 65 85 105 '25

Temperature (OC)

4-7

rnmr=

:tr'K
]

IrLI'O~
II -' I
VEN ~ 0/ 1 I I

I-

~~

o

~

0
VEN

+O.8V

+10V

104

1

I I IIII~!
CLOAO,,~,;8.F

105

"""

II
VS,;,,7 VRMS

'0 6

Frequency (Hl)

HI-506/507

Performance Characteristics and Test Circuits (continued)'
ON CHANNEL CURRENT VS. VOLTAGE

TEST CIRCUIT
NO.5

ON CHANNEL CURRENT
VS. VOLTAGE

~ 60r--+--~--i---r­

.s

I

u

i

~4---+----I---~-=::ol.-~;;;;;j::.--I

50

40r--+--~~~~~~---+

30
r-~~-b~+---r--+--~--+-~

1

+1
±4
±6
±S ±10 ±12
VIN - Voltage Across Switch

±14

±16

TEST CIRCUIT
NO.6
VS.

SUPPLY CURRENT VS. TOGGLE FREQUENCY

SUPPLY CURRENT
TOGGLE FREQUENCY

I

I
iSUPPIY

= ±15 -....;
50n

VSUPPly l =

±10V ....

I

.7

I
1K

/J

-

10K
lOOK
Toggle Frequency, (Hz)

-::-

EN

L.---"'iF----y"-'

+3.5V

High = 3.5V
VA { Low = OV
50% DUTY CYCLE
10M

1M

·Similar connection for HI·507

TEST CIRCUIT
ACCESS TIME VS. LOGIC LEVEL (HIGH)

+15V

NO .7

VS.

600

~
~

!i.
I

ACCESS TIME
LOGIC LEVEL (HIGH)

IN 1

400

.---4...-...---4 A2
~~

......

IN 2 THRU IN 151-0-......

'HI-50a

IN 16

:;:1OV- PROBE

-----,

I

200

;5

o

"

13
Logic Level (High), (Volts)

2

14

15

3.5V

ACCESS TIME

ADDRESS
DRIVE (VA)

~
50%
OV
I

+1OV

~90%
I

I

--I

>-- ... V~NPUT

-

I

I)

\

,iDIV,

S1 0N

OUTPUT

-1OV

OUTPUT

~VlDlVi

I
tA

I

:

S16 0N

I-

200 NS/DIV

4-8

I

L.
_ _ _ _I
I _ -::-

·Similar connection for HI·507

Switching Waveforms
.

I

I

It

I

I

IJ

HI-50G/507

.....
o

Switching Waveforms (continued)

U)

CD
o

TEST CIRCUIT

NO.8

U)
I

BREAK-BEfORE-MAKE
DELAY (tOPEN)

BREAK-BEfORE-MAKE
DELAY(tOPEN)

3.5V

VA INPUT

I i~VEIVAI
~

l - t- r/D1V

ADDRESS

~
50%
50%
r

5, ON

DUTPUTA

VOUT

,
1

12.5pF

I

IV

-----+I

I+'OPEN

S16 ON

ciUTPUT
IV/OIV -

..1

~-

100 NS!OIV

'Similar connection for HI-50?

TEST CIRCUIT

NO.9
ENABLE DELAY (tON(EN),tOff(EN)

3.5V

5o::f-

__ \

J

ENABLE DRIVE

--

I

I

ENABLE DELAY (tON(EN),tOff(EN)

+15V

I

90%1

I

OV

D-

~UTA
90%

.- ..

ENABLE
DRIVE
2V/DIV

,

.1

'I

-...,1,...----' 1
----+i 'ONIENII- I 'OFF I
1
I --+1 lEN 1 I+--

r-

/

82 THRU
S16 OFF

lJ
1

...l 5, ON
OUTPUT'
2V/DIV

~

'Similar connection for HI-50?

Schematic Diagrams

ADDRESS INPUT BUffER
LEVER SHifTER
.v

ADDRESS DECODER

TO P-CHANNEl
DEVICE OF
THE SWITCH

TO N-CHANNEl

DEVICE OF
THE SWITCH

v-

Ail N-Channel Bodies to VAil P-Channel Bodies to V+
Unless Otherwise Indicated

Delete A3 or A3 Input for HI-50?

4-9

~

---i

I

J
--I
•

HI-506/507
TIL REFERENCE CIRCUIT

MULTIPLEX SWITCH

'NO

Die Characteristics

Transistor Count
Die Size
Thermal Constants

8ja
8jc

Tie Substrate to:
Process:

421
110 x 83 mils
51OC/w
For Ceramic DIP
20OC/w

I

-VSupply
CMOS-DI

4-10

~HARRIS

HI·506AI507A

Single 16/Differential8 Channel
CMOS Analog Multiplexer with Active Overvoltage Protection

Features

Description

• Analog Overvoltage Protection •••..•••• 70 Vpp

The HI-506A and HI-S07A are anal9g ml.lltiplexe~ with Active Overvoltage Protection. Analog input levels may greatly exceed either pciwer supply without damaging
the device or disturbing the signal path of other channels. Active protection circuitry
assuras that signal fidelity is maintained even under faun condHions that would destroy
other multiplexers. Analog inputs can withstand constant 70 von peak-to-peak levels
and typically survive static discharges beyond 4,000 volts. Digital inputs will also sus,tain continuous faults up to 4 volts greater than either supply. In addition, signal
sources are protect~ from short circuiting should ml.lltiplexer supply loss occur; each
input presents 1kOof resistance under this condiiion. These features make the
HI-S06A,andHI-S07A ideal for use in systems where the analog inputs originate from
external equipment or separately powered ci rcuitry. Both devices are fabricated with
44volt dielectrically isolated CMOS technology. The50SA is a 16channel device and
the 507A is an 8 channel differential version. If input overvoltage protection is not needed, the HI-S06 and HI-507 multiplexers are recommended. For further information
see Application Notes S20 and S21.

• No Channel Interaction During Overvoltage
• ESD Resistant .•••••••.•••••••. > 4,000 Volts
• 44 V Maximum Power Supply
• Fall Safe with Power Loss (No Latchup)
• Break-Before-Make Switching
• Analog Signal Range •••••.• ; ••.•• , •.• ±15 V
• Access Time (1\Iplcal) ••••••••••••.••• 500 ns
• Standby Power (Typical) •.•••••.••.••• 7.5 mW

:r::

Each device is available in a 16 pin plastic or cerami~ DIP, a 2,0 pin ceramic LCC
package.

Applications
• OatS Acquisition

The HI-S06A/S07A are offered in both commercial and military grades. Additional HiRei screening including,160 hour burn-in is specified by the "-8" suffix.

• Industrial Controls
• Telemetry

Pinouts "

Functional Diagrams

Top View
+Vsupp
NC
NC
tH16
IN 15IN 14
IN 13
IN 12
IN 11
IN 10
IN 9
GND
VREf
ADDRESS A3

'VsuPP
IN8
IN 7
IN 6
IN 5
IN 4
21
20
19

10
Ii
12
13
14

. IN 3

Ie
17
i6

15

IN 2
INI
ENA8LE
ADDRESS AD
ADDRESS AI
ADDRESS Ai

Ik

INI

O)~::=~~~ ~

OUT

'k

IN2

GND

IN 16
NC
NC
+VSUPPLY
OUl
-v SUPPLY
IN 8

VR"
A,

A,
AT

An
ENABLE

HI1-506A (ceramic)
HI3-506A (plastiC)

..... C'\I

~

'<:T

an

(D

IN 16

l ___

•
••

VREf
NC

10
12
13
14

a::a a::a a::a

HI1-507A (ceramic)
HI3-507A (plastic)

I I

L ___

'C:O

to

HI-506A

co ......
a:a

IN 14

..... C\I"CO) "'¢' I.t) (0

15

.k

r...

~~~.~ ~ ~:!:

II

DECODER
DRIVER

~~~~~~~

Top VieW
28
27
26
25
2.
23
22
21
20
19
18
17
16

II
II

I

HI4-506A(LCC)

+Vsupp
OuT 8
NC
IN 88
IN 78
IN 68
IN58
IN 48
IN 38
IN 28
IN 18
GNO

OUT

I
,-

~~:5:~'~~~

OUT A
,Vsupp
IN 8A
IN 7A
!liSA
IN 5A
IN 4A
IN 3A
IN 2A
IN lA
ENA8LE
ADDRESS AD
ADORESSA.
ADDRE,SSA2

IN ilA

IN 8B
NC
OU1B
+VSUPPLY
aUlA
-v SUPPLY
,INBA

GND
VR"
NC

A,

DUTA

••

OuT B

IN 18

IN88

••

I

AT

An
ENABLE

;$~<'i:::;;j!j6V

\

-l51-tOV

ACCESS TIME
vs. LOGIC LEVEL (HIGH)

A3

E
t= 700 ~~
:i.

AO
+4V

900
800

IN15

5011

-=-

THRU

'Similar Connection for HI-507A

ACCESS TIME VS. LOGIC LEVEL (HIGH)

c

'HI-506A

-=-

-=-

IN16
O,UT

+4.OV

6

I

7

8 9 10 11 12 13
Logic level (High), Volts

14

I
I
I
L ____ -'

15

Switching Waveforms
VAH - 4.0V

I~PUT

ADDRESS

VA
2VIOIV.

RIVEIVAJ

~OV

%VAH

I

-

'~

It'

OUTPUT

1:~
I
-lOV

OUTPUT A
'A

I

I

'Similar Connection for HI-507A

--.1

PROBE

-----,

I
I_

\

5r OlV

I
J

r-....
200ns/Div.

4-14

i

HI-506A/507A
c(

Switching Waveforms (continued)

.....
o

II)

TEST
CIRCUIT
NO.9
BREAK-BEFORE-MAKE
DELAY (tOPEN)

---::y::50".

BREAK-BEFORE-MAKE DELAY(tOPEN)

."

"

I~PUT

VA
2V/DIV .

8A ON

1/

VOUT

50"

I

I

1\ I

12.5pF

--+I t+'OPEN

l\ I

OUiPUT
O.5V/D1V,

I

V

TEST
CIRCUIT
NO. 10

~
100ns/01Y.

'Similar Connection for HI-507A

ENABLE DRIVE

ENABLE DELAY (tON(EN),tOFF(EN)

ENABLE DELAY (tON(EN),tOFF(EN»

V AH' 4,0 V

5:(- ---\. . ___
r'---+!-'l
OV

I

90'

_...-_.Jr:

--+i
I

'ONIENII-

OUTPUT

I
I

1--+1

lA ON

~

!(

'OFF I
lEN I 14--

OUTPUT A \
2V/DIV.

-IN lTHRU
IN 8 OFF

1

1

lOOns/Dlv.

"

'Similar Connection for HI·507A

Schematic Diagrams

ADDRESS INPUT BUFFER
AND LEVEL SHIFTER

LEVEL
SHIFTED
ADDRESS
TO DECODE
lEVEL

.....+-.".j---'-- K6I~~~~

TO DECODE

L __________________________________ _

4-15

CD

o
II)
I

lAON
OUTPUT

;C

HI-506A/507A
Schematic Diagrams (continued)
MULTIPLEX SWITCH
D:C~rre >i>--=====.......------..--,

ADDRESS DECODER

TO N CHANNEL
DeVICE OF

THE SWITCH

otc~~

»----------<------'

ENABLE

A3

Delete A3 or
Input for HI-507A

Die Characteristics

v

Transistor Count
Die Size
Thermal Constants

485
161 x 85 mils
Oja
0jc

~~:g~

-VSupply
CMOS-DI

Tie Substrate to:
Process:

4-16

I

For Ceramic DIP

HI·506LA/HI·507LA

~ HARRIS

Single 16/0ifferential 8 Channel
CMOS Analog Multiplexers with
Latches and Overvoltage Protection

ADVANCED
Features

+VSUPPLY
NC
RS
IN 16
IN 15
IN 14
IN 13
IN 12
IN 11·
IN 10
IN9
GNO
lliR
ADDRESS A3

1
2
3
4
5.
6
7
8
9
10
11
12
13
14

I

Each channel can withstand overvoltage to ±2SVOe with respect to ground with power ON or OFF.
An OFF channel remains OFF in the presence of overvoltage. If the channel is ON, output voltage is
clamped below the supply rail, which protects the load circuit.
The HI-SOSLA offers 16 single-ended channels, and the HI-S07LA is an 8 channel differential
version. The recommended supply voltages are ±1SV, though operation at reduced levels or with a
single supp!y may also be inplemeoted. The package is a 28 pin ceramic or plastic DIP.
Each product is specified for the commercial temperature range (ODe to +7S 0 C,-S suffix) and the
military range 1-!iSoe to +12s oC,-2 suffix). For Mll-STO-883 coopliant parts, request the
506LA/883 or 507LA/883 data sh.e•.

HI-506LA

.

SWITCH CElLI

LATCH

A,
OIBITAL

AOOflESS

{

.
0

"

Do

"

"

LEVU
SHIFTEfI

0

"

OUTPUT

CLiI

11'1

flEsn

HI-507LA
28
27
26
25
24
23
22
21
20
19
18
17
16
15

+VSUPPlY
OUT 8
RS
IN 88
IN 78
IN 68
IN 58
IN 48
IN 38
IN 28 10
IN 18 11
GNO 12
YiH 13
NC 14

DEVICE

FUNCTION

HI-506LA 16-Channel

HI-507LA 8-Channel
Differential

OUT A
-VSUPPLY
INBA
IN 7A
IN6A
IN 5A
IN4A
IN 3A
IN2A
IN 1A
ENABLE·
ADDRESS Ao
ADDRESS A1
ADDRESS A2

FEATURE
Addr.ss
LaIche. and
Overyoltago
Protection
Addre..
Latche. and
Oyorvoltage
Protection

DIGITAL
ADDRESS

r

"

"

"
Ct.

Do

OUTA

LEVEL
SHIFTER

ITO OTHER lEVEl A

SWITCHEI'
CTOOTHERSlVEIII
SWITCHEIt

"

OUTI

RESET

11111

iii

iii

TIL
"HIGH"
MIN IVI

RONIl
ITYPI

1010FFI
InAI
ITYPI

qONI
In.1
ITYPI

qOFFI
lnal
ITYPI

PDI"WI
ITYPI

2.0

lK

4.0

500

500

60

2.0

lK

2.0

500

500

60

CAUTION: These davices are sensitive to electrostatic discharge. Proper I. C. Ila~'~ling procedures should be followed.

4-17

I

CD

Functional Diagram
28 OUT
27 -VSUPPLY
26 IN 8
25 IN 7
24 IN 6
23 IN 5
22 IN 4
.21 IN 3
20 IN 2
19 IN 1
18 ENA8LE
17 ADDRESS Ad
16 ADDRESS A1
15 ADDRESS A2

-

l:

II)

The overvoltage performance of these multiplexers is particularly useful in redundant systems, where
the inputs and output must present a high inpedance when power is ott. This is achieved by a switch
cell with three MOSFET's in series rather than the conventional transmission gate design.

TOP VIEWS

II)

o

These monolithic CMOS multiplexers feature on~board address latches, plus overvoltage protection
for the analog inputs and the output as well. Each model includes digital inputs for channel selection
and an Enable input tor device selection under program control. In addition, Write (Wit) and Reset
IRS) inputs allow the program to store or clea~ the channel address.

Pinout

.....

o

C
-I

Description

• Analq Overvoltage protection
• Resettable Latches (RS)
• TTL/DTL and CMOS Com~atible
•. Failsafe for conditions of Overvoltage & Loss of Power
• No SCR Latch-up
• Break-before-make switching
• Microprocessor Bus compatible
• Very low le8kage-ID(off)~4nA (typ)
• Acess time-tA = 500nS (tvp)
• Minimum write pulse width (WR) = 300nS
• OFF isolation = -100dB. tvP @ 10Kz

«-I

mHARRIS

HI-50B/509
Single 8/Differential4 C.hannel
CMOS Analog Multiplexer

Features

Description

• RON •.............•..••............. 180!)

These monolithic CMOS multiplexers each include an array of eight analog switches,
a digital decode circuitfor channel selection, a voltage reference for logic thresholds,
and an ENABLE input for device selection when several multiplexers are present.
The Dielectric Isolation (01) process used in fabrication of these devices eliminates
the problem of latch-up. Also, 01 offers much lower substrate leakage and parasitic
capacitance than conventional junction-isolated CMOS (see Applicati.on Note 521).
Combined with the low ON resistance (180!) typical), these benefits allow low static
error, fast channel switching rates, and fast settling.

• Wide Analog Signal Range .. ; ....•.••.. ±15 V
• TTL/CMOS Compatible ...•.•. 2.4 V (Logic "1")
• Fast Access ....•.•........•........ 250 ns
• Fast Settling (0.01%) ...••...•........ 600 ns
• 44V Maximum Power Supply

Switches are guaranteed to break-before-make, so that two channels are never shorted
together.

• Break-Before-Make Switching

The switching threshold for each digital input is established by an internal +5V
reference, providing a guaranteed minimum 2.4 V for "I" and Maximum 0.8 V for "0".
This allows direct interface without pull-up resistors to signals from most logic families:
CMOS, TIL, DTL and some PMOS. For protection against transient overvoltage, the
digital inputs include a series 200!) resistor and a diode clamp tO'each supply.

• No Latch-Up
• Replaces DG508A/DG508AA and
DG509A/DG509AA

The HI-508 is an eight channel single-ended multiplexer, and the HI-509 is a four channel differential version. The recommended supply voltage is ±15 V; however,
reasonable performance is available down to ± 7 V. Each device is available in a 16
pin plastic or ceramic DIP, a20 pin ceramic LCC or 20 pin plastic LCC (PLCC) package.
If input overvoltage protection is needed, the HI~508A/509A multiplexers are recommended. For further information, see Application Notes 520 and 521.

Applications
• Data Acquisition Systems
• Precision Instrumentation
• Demultlplexing

The HI-508/509 is offered in both commercial and military grades, suitable for
. spacecraft/military applications. For additional HI-Rei screening including 160 hour
burn-in, specify the" -8" suffix. For further information see Application Notes 520
and 521. For MIL-STD-.883 compliant parts,request the 5081883 or 509/883 datashee!.

• Selector Switch

Pinouts

~

M

;;;::
Top View



~~ ,~

IN 2

IN 4
OUT
(N.C.)

ENABLE

IN 8
IN 7

A,
A,

L ___

••
•

An
(N.C.)

OUT

I
,-

IN 8

OECOOER/
ORIVER

L ___

~

co~~~~

H11-508 (ceramic)
H13-508 (plastic)

~ - 6,~ ~

H14-508 (LCC)
HI4P508 (PLCC)

AO AI A2

~

~ ~ 8~ ~
~ ~ ~~

CI)

>

I

Top View

.AO
EN
·VSUp
IN IA
IN 2A
IN 3A
IN 4A
OUT A -..;; _ _ _:.r

EN

HI-508

Al
GNO
+VSUP
IN 18

IN.28
IN 38
IN 48

•

IN 4Ao-lod'l".......

IN 4A
OUT A
(N.C.)
IN B
IN 4B

ENABLE

Ao
(N.C.)
A,
GND

IN

18o-l-oIo(J~~~~~~~I-JOUT 8

••

IN 4Br....IL..,,-,"'.........

OUT 8
~

H11-509 (ceramic)
H13-509 (plastiC)

~~~~&

~~6~~

";:
H14-509 (LeC)
HI4P509 (PLCC)

4-18

AO Al

HI-509

EN

HI-50B/509 Specifications
ABSOWTE MAXIMUM RATINGS (Note 1)

Q)

o

Continuous Current, S or D:
20 mA
Peak Current, S or D
(Pulsed at 1 ms, 10% duty cycle max): 40 mA
Power Dissipation'(Cerdip)
1.09 W
Operating Temperature Range:
HI-50S/509-2,-S
-55°C to +125°C
HI-50S/509-4
-25°C to +SsoC
HI-50S/509-5
O°C to + 75°C
Storage Temperature Range -65°C to +150°C

44V
22V
25V

VSupply( +) to VSupply (-)
VSupply(+) to GND
VSupplyH to GND
Digital Input Overvoltage:

VEN, VA { VSupply( +)
+4 V }
VSupplyH
-4 V
or 20 mA, whichever occurs first.
Analog Signal Overvoltage (Note 7)
VD, Vs { VSupply( +)
VSupplyH

It)

........
CO

o

It)
I

'Derate 10.9 mW/oC above TA =75°C

+2V}
-2V

ELECTRICAL CHARACTERISTICS Unless Otherwise Specified:
Supplies= +15 V, -15 V; VAH(Logic Level High) = +2.4 V, VAL(Logic Level Low)
+O.S V. For Test Conditions, consult Performance Characteristics Section.

PARAMETER
ANALOG CHANNEL CHARACTERISTICS
'VS, Analog Signal Range
'RON" On Resistance (Note 2)

HI-S08/S09
HI-S08lHI-S09
-4, -5
-2, -8
TEMP. MIN. TYP. MAX. MIN. TYP. MAX. ~NITS

Full
-15
+25°C
Full
6RON, Any Two Channels
+25°C
'IS (OFF), Off Input Leakage Current (Note 3)
+25°C
Full
'10 (OFF), Off Output Leakage Current (Note 3)
+25°C
HI·50S
Full
Full
HI·509
'10 (ON), On Channel Leakage Current (Note 3) +25°C
HI·50S
Full
Full
HI·509
'IDIFF, Differential Off Output Leakage Current
Full
(HI·5Q9 Only)
DIGITAL INPUT CHARACTERISTICS
'VAL, Input Low Threshold
Full
Full
2.4
'VAH" Input High Threshold
'IA, Input Leakage Current (High or Low) (Note 4) Full
SWITCHING CHARACTERISfICS
'tA, Access Time
+25°C
Full
'tOPEN, Break·Before·Make Interval
+25°C' 25
'tON (EN), Enable Turn·On
+25°C
Full
'tOFF (EN), Enable Turn·Off
+25°C
Full
ts, Settling Time to 0.1%
+25°C
to 0.01%
+25°C
"Off Isolation" (Note 5)
+25°C 50
Cs (OFF), Channel Input Capacitance
+25°C
CD (OFF), Channel Output Capacitance HI·50S +25°C
HI·509 +25°C
CA, Digital Input Capacitance
+25°C
CDS (OFF), Input to Output Capacitance
+25°C
POWER REQUIREMENTS
'1+, Positive Supply Current (Note 6)
Full
'1-, Negative Supply Current (Note 6))
Full
PO, Power Dissipation
Full

180

+15
300
400

-15
180

5
0.03

+15
400
500

5
0.03
50
0.3
200
100

200
100

0.3

0.3
200
100
50

200
100
50

O.S

0.8

250
SO
250
250

1.0

500
1000

250
1000
25

500
1000
500
1000

360
600
68
5
22
11

80
250
1000
250
1000

50

360
600
6S
5
22
11

5

5

.08

.08

1.5
0.4

2
1
45

1.5
0.4

2
1
45

~

w

{)

{)

A2 A1

Ao EN

X X X L
L
L
L
L
H
H
H
H

L L
L H
H L
H H
L L
L H
H L
H H

V
V
pA

2.4
1.0

HI-50S

V
%
nA
nA
nA
nA
nA
nA
nA
nA
nA

50

0.3

TRUTH TABLES

ns
ns
ns
ns
ns
ns
ns
ns
ns
dB
pF
pF
pF
pF
pF

H
H
H
H
H
H
H
H

"ON"
CHANNEL
NONE
1
2
3
4
5
6
7
8

HI-S09

A1

Ao EN

X X L
L L
L H
H L
H H

H
H
H
H

"ON"
CHANNEL
PAIR
NONE
1
2
3
4

mA
mA
mW

*100% tested for Dash 8. Leakage currents not tested at _55°C.
NOTES: 1. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability
of the circuit may be impaired. Functional operaticn under any of these conditions is not necessarily implied.
2. VOUT " ±10V. lOUT" -1 mAo
3. Ten nanoamps is the practical lower limit for high
speed measurement in the production test
environment.

4. Digital input leakage is primarily due to the clamp
diodes (see Schematic). Typical leakage is less
than 1 nA at 25°C.
5.

~~N ; fO~ ~O~'kHz.\~o;fc;'~~f~a~gn ~c~urs

on

~annel 4 due to proximity of the output pins.

6. VEN. VA" 0 V or 2.4 V.

4-19

7. Signal vOltage at any analog input or output (5 or
D) will be clamped to the supply rail by internal
diodes. Limit the resulting current as shown under
absolute maximum ratings. If an overvoltage condition is antiCipated (analog input exceeds either
power supply voltage), the HARRIS HI·508A1509A
multiplexers are recommended.

xw

..J

a..

5::>

:;;;

HI-50B/509

Performance Characteristics and Test Circuits
Unless Otherwise Specified; TA
VAH = 2.4 V, VAL = 0.8 V.

ON RESISTANCE VS.
INPUT SIGNAL LEVEL, SUPPLY VOLTAGE

= 25°C, VSupply = ±15 V,
TEST CIRCUIT
NO.1

VS.

RON=~
1mA

ON RESISTANCE
ANALOG INPUT VOLTAGE, TEMPERATURE
NORMALIZED ON RESISTANCE
VS. SUPPLY VOLTAGE

400

E 300

~Ii 200

..

.j
c5

....-

=+1250C
TA =+250C
TA

100

TA = -550C

o

-5

-10

-15

--- -

+5

2.2

..... "
........

~

/

1.8

-;;1. 6
~ 1.4
::S 1. 2

i

+10

+1250C?:TA?: -550C
VIN = OV

"E 2.0

~

+15

VIN Analog Input(Volts)

"

"'-..

........

..... r----

1. 0

p. 8
O. B
t7

!'8

±lO

tg

:tll

t12

t13

±14

1"15

Supply Voltage (Volts)

LEAKAGE CURRENT VS. TEMPERATURE

TEST CIRCUIT
NO.2"

IDOnA

TEST CIRCUIT
NO.4"

N

~

./

10nA ~
OffOU1pUl
F=======Leakage Current
~
loIOff)-'").oEloIOnlonL·

[

Z

±1OV

Current

3
~

/'

lnPJ

+O.8V

OUT

/

A IOIOFF)

-=-

+O.BV

-=-±10V

*

*"

TEST CIRCUIT
NO.3"

./

,/

/

100pA

'Off Input

leakage Current IS IOff)

...::I..,±1OV

+2AV

f

10pA
250

500

75 0
Temperature DC

1000

LOGIC THRESHOLD

vs. POWER SUPPLY VOLTAGE

125 0

·Two measurements per channel:
+10 V/-10 V and -10 VI+10 V.
(Two measurements per device for IO(OFF) :
+10 VI-10 V and -10 VI+10 V.)

POWER SUPPLY CURRENT
vs. TEMPERATURE

OFF ISOLATION VS.
FREQUENCY

3.0

10 0

..

"

~

.§

-,....

-

0

~

>~

J

1

ts :!8 tiD

t12 t14 t16 t18 ±2D
Power Supply Voltage (Volts)

Q

.~

EN=5~

1.0
EN = DV'-

~

r-

0
-55-35-15 -5 25 45 65 85105125
Temperature (DC)

4-20

!
~

0
'-

0
0

o

RL

....

C

E 2.0

1

11111111

0

104

=

I,K

rn -~
h~L 1
10M

III I

VEN
I I

II

=o~:rr

I IIII~

.CLOAp,~,~8pF

105

-

-:-

Frequency (Hz}

107

HI-50B/509

en
oIt)

Performance Characteristics and Test Circuits (continued)
ON CHANNEL CURRENT vs. VOLTAGE

.........

TEST
CIRCUIT
NO.5

00

o

ON CHANNEL CURRENT
vs. VOLTAGE

VIN - Voltage Across Switch

SUPPLY CURRENT
vs. TOGGLE FREQUENCY

TEST
CIRCUIT
NO.6
SUPPLY CURRENT vs. TOGGLE FREQUENCY

/
±15"'-J

VSupply ~

V/

~_o--___--lA't.

IN 2~-<)-.,

Al

'HI-50S T~NR~~'-l")-...J

AO

INjl

VSupply :: ±lOV"

'I'

lK

-=-

V

I
10K

-=-

EN
3,5V

High "3.5V

lOOK

1M

VA { Low" OV
50% DUTY CYCLE

10M

Toggle FrequencY,Hz

-15/-1OV

'Similar connection for HI·5t 9

ACCESS TIME vs. LOGIC LEVEL (HIGH)

ACCESS TIME
vs. LOGIC LEVEL ,(HIGH)

TEST
CIRCUIT
NO.7

+15V

600

]
E
;::

V+
IN 1
r-_-~--l,,~

400

S

:<.

Al
AO
EN

.......
200

IN 2 THRU IN 71--0---,

HI-50a IN 8
GNO

:5

o

2

13

14

OUT f-----'~---,

200
fl

8, ON
OUTPUT

I OFF I

I'VIO:V,

I--- I--

1
100 NS/DIV,

-15V

'Similar connection for HI-S09

Schematic Diagrams
ADDRESS DECODER

ADDRESS INPUT BUFFER
LEVER SHIFTER

TO P-CHAN.
DEVICE OF
THE SWITCH

TO N-CHAN.

DEVICE OF
THE SWITCH

ENABLE

Delete A2 or A2
Input for HI-509
All N-Channel Bodies to VAil P-Channel Bodies to V+ Unless Otherwise Indicated

4-22

HI-SOB/S09

-

Schematic Diagrams (continued)

0')

o

It)

MULTIPLEX SWITCH

TTL REFERENCE CIRCUIT

00

oIt)

V·

Y

I

Applications
32 CHANNEL BUFFERED MULTIPLEXER
CHANNEL
4

1()

8

0

····
··

OUT

16

~

17 0

HI-50B

4
•

···
··
···
··

OUT
A2
A1
AO
EN

9
4

HI-50B
OUT
A2
A1
AO
EN

24 ~
25

32

O!

···

oi·

A2
A1
AO f - - EN

9

~

9. ' J

HI -508

HI-50S
OUT

4

1 2f B

31 4

(

A2
A1
AO
EN

7

6

HA-2405
PRAM

5f

OUT

~200
10

~

OUTP UT

7

6

DO D1

1

402BA
DECODER"

EN

A 10
B 13
C 12

CaMP
-'-15pF

()
,AO

(

A1 A2

.

)
)
A3 A4

CHANNEL SELECT

'Optional; Provides Greater Isolation for AC Signals.

4-23

)
SYSTEM ENABLE

HI-50B/509

Applications (continued)
ONE OF 8 DECODER
ACTIVE LOW

I

ACTIVE HIGH

+5V

+5V

I

~~
~{:~~.~{:~10 K
~:;->-~~:10

.0

A2

.(')

AO Al A2

666

~ 4,000 Volts
• 44 V Maximum Power Supply
• Fall Safe with Power Loss (No Latchup)
• Break·Before·Make Switching
• Analog Signal range .................. ±1S V
• Access Time (Typical) •.•.•••.••.•••.• 500 ns
• Standby Power (Typical) ••.•.•.••••.•• 7.5 mW

Applications

Each device is available in a 16 pin plastic or ceramic Dlp,·a 20 pin ceramic LCC
package.

• Data Acquisition

The HI·508AJ509A are offered in both commercial and rnilitary grades. Addition Hi·
Rei screening including 160 hour burn·in is specified by the "-8" suffix.

• Industrial Controls
• Telemetry

Pinouts

Functional Diagrams
HI·SOBA
Top View

~

'"
~

~~;8:
-~-~

":

IN 1

Al

AO

A2
GNO
+VSUP
IN 5
IN 6
IN 7
IN 8

EN
·VSUp
IN 1
IN 2
IN 3
IN 4
OUT

IN4
OUT

ENABLE

(N.C.)

(N.C.)

INa
IN 7

A,

A,

IN 8

.-

OUT

I

lk

IN 2

flo

lk

L ___

•••

11
II
II
II
II

lk
I

II

DECOOERI
DRlm
L ___

HI1·S0BA (ceramic)
HI3·S0BA (plastic)
HI4·S0BA (LeC)

HI~S08A
~

C'j

Top View

AO
EN
·VSUp
IN lA
IN 2A
IN 3A
IN 4A
OUTA

~~~ ~

IN lAo-t-M....-o4I~-C;~,...----t-aOUT A

3:~~~~

GNo
+VSUP
IN 18
IN 28
IN 38
IN 48
OUT 8

H11·S09A (ceramic)
H13·S09A (plastic)

••

I

Al

IN 4Ao-....M

IN4A
OUT A

ENABLE

(N.C.)

(N.C.)

aUTB
IN4B

GND

flo

....~~"...'!-I

IN 18 CJoo1"""W""4l'i'i-'!<1~",~~~=--+-oOUT 8

••

A,

~ ~ ~.SE ~

~~~~~

::;:
H14·S09A {LeCl

4-25

CO

o
U)
I

Features
• No Channel Interaction During Overvoltage

U)

~

AD Al

HI·S09A

EN

HJ-508A/509A Specifications
ABSOWTE MAXIMUM RATINGS, (Note 1)
Voltage between Supply Pins
V+ to Ground
V- to Ground
Digital Input Overvoltage:

Continuous Current, S or D:
20mA
Peak Current, S or D
(Pulsed at 1 ms, 10% duty cycle max): 40 mA
Power Dissipation" (CERDIP)
1.28 W
Operating Temperature Range:
HI-508A/509A-2,-8'
-55°C to +125°C
OOC to +75°C
HI-508A/509A-5
Storage Temperature Range -65°C to +150 oC

44V
22V
25V

VEN, VA {Vsu,PPIY(+)
+4V}
VSupplyH
-4 V
or 20 mA, whichever occurs first
Analog Input Oilervoltage:
Vs {VsuPPI Y(+)
VSupplyH

"Derate 12.8 mW/oC above TA = 75°C

+20 V}
-20 V

ELECTRICAL CHARACTERISTICS Supplies= +15 V, -15 V; VAH (Logic Level High) =
+4.0 V. VAL(Logic Level Low) = +0.8 V. (unless otherwise specified).
For Test Conditions; consult Performance Characteristics Section.
HI-508AI509A
-5
TEMP. MIN. TYP. MAX. MIN. TYP. MAX. UNITS
HI-S08AJHI-509A

-2, -8

PARAMETER
ANALOG CHANNEL CHARACTERISTICS
"VS, Analog Signal Range
"RON, On Resistance (Note 2)
"IS (OFF), oil Input Leakage Cu~ient (Note 3)
"ID (OFF), Off Output Leakage Current (Note 3)
HI·508A
HI·509A
"ID(OFF) with Input Overvoltage Applied (Note 4)

HI-50BA .
Full
-15
+25°C
Full
+25°C
Full
+25°C
Full
Full
+25OC
Full
+25°C
Full
Full
Full

"ID (ON), On Channel Leakage Current (Note 3)
HI-50BA
HI-509A
IDIFF. Differential Off Output Leakage Current
(HI-509AOnly)
DIGITAL INPUT CHARACTERISTICS
"VAL, Input Low Threshold
(Note 8)
Full
"VAH , Input High Threshold
Full
"IA Input Leakage Current (High or Low) (Note 5) 'Full
SWITCHING CHARACTERISTICS
"tA, Access lime
+25°C
Full
"tOPEN, Break-Before-Make Delay
+25°C
"tON (EN), Enable Delay (ON)
+25°C
Full
*lOFF (EN), Enable Delay (OFF)
+25°C
Full
Settling lime (0.1 0Al)
+25°C
(0.D1%)
+25°C
"OFF Isolation" (Note 6)
+25°C
Cs (OFF), Channel Input Capacitance
+25°C
, CD (OFF), Channel Output Capacitance HI-50BA +25°C
HI-509A +25°C
CA, Digital Input Capacitance
+25°C
CDS (OFF), Input to Output Capacitance
+25°C
POWER REQUIREMENTS
PD, Power Dissipation
Full
"I +, Current (Note 7)
Full
"1-, Current (Note 7)
Full

1.2
15
0.03

-15

+15
15
1.8

15
1.8
0.03

50
0.1
200
100

200
100

4.0

4.0
2.0

0.1

0.1
200
100
50

200
100
50

0.8

0.8

4.0

4.0
1.0

1.0

0.5

05
1.0

25

1.0

80
300
300

50

~:gli~~I~da:~~~~:~~9~h~~i~:i~~:~:~iI~of the circuil may be impaired. Functional operation under any of these conditions is not naeessar-

\r6~~Ii~±1OV.

~

2.
lOUT
-100pA,
'
3. Ten nanoamps is the practical lower limit for high
speed measurement in the production test
environment.
4. Analog Overvoltage .., ±33 v.

5.

+15
1.8
2.0
50

0.1

25
500
1000
500
1000

80
300
1000
300
1000

1.2

1.2

3.5
68

3.5
50

5
25
12
5
0.1
75
05
0.02

68
5
25
12
5
0.1
75
05
0.02

2.0
1.0

*100% tested for Dash a Leakage ~u~rents' not tested at _55°C.

NOTES: 1:

TRUTH TABLES

~i~~:! i(~~t~~~':~:t:~)~~f~!rl~~~~: I;I::P

than 1 nA at 25°C.

.

6. ~~N ; fO! ~O~\HZ~ ~o~Lc;S~i~~a~~n=o:Curs
, on Miannel 4 due to proximity of the output pins.

~ ¥oEMiv~"\;mO~~~'tircUits, 1kO pull·u
, resistors to +5.0 V supply are

4-26

recommen~ed.

2.0
1.0

V
Kll
Kll
nA
nA
nA
nA
nA
nA
pA
nA
nA
nA
nA

V
V
pA

J..?---------..------------ . > - - - - - - - - - - - 4 - - - - - - - - - '

Die Characteristics

Transistor Count
Die Size
Thermal Constants
Tie Substrate to:
Process:

253
116 x 79 mil
78 00 C/W}
..
25
C/W
For Ceramic
DIp

!lja
!lje

-VSuppJy
CMOS - DI

4-30

mJ.~RIS

HI-50BLA/HI-509LA
Single 8 Differential 4 Channel
CMOS Analog Multiplexers With
Latches and Overvoltage Protection

Features
• Analog Over voltage protection

• TTL/OlL and CMOS Compatible
• Failsafe for

cond~ions

• No SCR Latch-up

= 500nS (typ)

• Minimum wr~e pulse width (WR) = 300 nS
• OFF isolation = -100dB, typ

anI

The HI-508LA offers '8 single-ended channels, and the HI-509LA IS an 4 channel differential
version .. The recommended supply voltages are +15V, though operation at reduced levels or with a
single supply may also be rnplemented. The package isan18 pin ceramic or plastiC DIP.

• Very low leakage - 10(off) :::. 2nA (typ)
• Access time - tA

These monolithic CMOS multiplexers feature on-board address latches, plus overvoltage protection

Each channel can withstand overvoltage to +25VDC with respect to ground with power ON or OFF.
An OFF channel remains OFF in the presence of overvoltage. If the channel is ON, output voltage is
clamped below the supply rail, which protects the load circuit.

• Microprocessor Bus compatible

@

Each product is specified for the commercial temperature range (OoC to +75 0 C,-5 suffix) and the
military range (-55 0 C to +125 0 C,-2 suffix)' For MIL-STO-883 conpliant parts, request the
508LAf883 or 509LAf883 data sheet.

10kHz

Functional Diagram

Pinout
TOP VIEWS

HI-50BLA
SWITCH CELLS

iiS

Wii

18

Ao

17 Al
16 A2
15 GNO

ENA8LE
-VSUPPLY
IN 1
IN 2

14 +VSUPPLY
13 IN 5

HI-50BLA

IN 3

12 IN 6

IN 4

11

OUT

10 IN 8

"

LATCH

AO

DIGITAL
ADDRESS

J

A,

00

lEVEl
SHIFTER

·0

0
0

o

OUTPUT

IN.

IN 7

HI-509LA
Wii

18

Ao

17

irS

IN 2A
IN 3A

13 IN 2B

r

7

12 IN 38

Wi

IN4A

8

11

IN 48

10

OUT B

Al
16 GNO

ENABLE
-VSUPPLY
IN lA

HI-509LA

OUT A

DEVICE

15 +VSUPPLY
14 IN 18

FUNCTION

FEATURE

HI-50SLA

S-Channel

Address
Lalches and
Overvoltage

HI-509LA

4-Channel
Differential

Address
Lalches and
Overvoltage

~

c:o
o

the inputs and output must present a high inpedance when power is off. This is achieved by a switch
cell with three MOSFET's in series rather than the conventional transmission gate deSIgn.

• Break-before-make switching

J:
..J

The ovefvoltage performance of these multiplexers is particularly useful in redundant systems, where

of OvervoHage & Loss of Power

Q)

o
anI

Description
for the analog Inputs and the output as well. Each model includes digital inputs for channel selection
and an Enable input for device selection under program control. In addition, Write (WR) and Reset
(R'Sl inputs allow the program to store or clear the channel address.

• ReseHable Latches (RS)

c(
..J

DIGITAL
AODRESS

LATCH

00

OUT A

lEVEL
SHIFTER

·0

(TO OTHER THREE A

DECODE

A,

0,

SWITCHES~

.,

(TO OTHER THREE B
SWITCHES~

IN lB

\

RS

TTL
':HI6 H"
MIN IVI

RON!l
ITYPI

IO(OFFI
(nAI
ITYPI

IIONI
In'l
(TYPI

tlOFFI
In'l
ITYPI

PO(mWI
(TYPI

2.0

1K

2.0

500

SOO

40

2.0

1K

1.0

500

500

40

Protection

Protection

CAUTION: These devices are sensitive to electrostatic discharge. Proper I. C. handling procedures should be followed.

4-31

mHA.RRIS

HI·516
16 Channel/Differential
8 Channel CMOS High Speed
Analog Multiplexer

PRELIMINARY
DESCRIPTION

FEATURES
•

ACCESS TIME (TYP)

lOOns

•

SETTLING TIME (0.1%)

250ns

•

LOW LEAKAGE (TYP) IS(OFF)
ID(OFF)

10pA
30pA

•

LOW CAPACITANCE (TYP) Cs OFF
CD OFF

2pF
18pF

•

HIGH OFF ISOLATION AT 500kHz

90dB

•

LOW CHARGE INJECTION

0.3pC

•

SINGLE ENDED TO DIFFERENTIAL
SELECTABLE (SDS)

•

LOGIC LEVEL SELECTABLE (LLS)

APPlICA TIONS
•

DATA ACQUISITION SYSTEMS

•

PRECISION INSTRUMENTATION

•

INDUSTRIAL CONTROL

The HI-516 is a monolithic dielectrically isolated, high speed, high performance CMOS analog multiplexer. It offers unique built-in channel selection decoding plus an inhibit input for disabling all channels. The dual
function of address input A3 enables the HI-516 to be user programmed
either as a single ended 16-channel multiplexer by connecting 'out A' to
out B' and using A3 as a digital address input, or as an 8-channel differential mUltiplexer by connecting A3 to the V- supply. The substrate leakages and parasitic capacitances are reduced substantially by using the Harris
dielectric isolation process to achieve optimum performance in both high
and low level signal applications. The low output leakage current (10 Off
< 100pA @ 25 0 C) and fast settling (tSETTLE = 800ns to 0.01%) characteristics of the device make it an ideal choice for high speed data acquisition
systems, precision instrumentation, and industrial process control.
The HI·516 is available in a 28 lead dual·in·line package and a 28 lead
LCC package (·8 only). It is offered in both commercial and military grades.
for additional Hi·Rel screening including 160 hour burn·in, specify the
·8 suffix.

FUNCTIONAL DIAGRAM

PINOUT

VDD/LLS

TOP VIEWS

INIA

,...----1-<
EN~--------~~

~~--------;+~

Al>-t--~----,4++-I

A2>-t-------,-I4++-I
A3

I
A3 Decode
A3 Q Q
H H L

I
I
I
I

L

L H

I

v-

L L

I

I

DECODER

I
I

IL

I

__________
INPUT BUFFER AND DECODERS

4-32

I

~

I
____ I
~

MULTIPLEXER
SWITCHES

SPECIFICA TlONS
CD
,....

ABSOLUTE MAXIMUM RATINGS

II)

Digital Input Overvoltage:
-6V< VAH <+6V
TTL
A3 VSUPPL Y (-)
VSUPPLY(+)
CMOS
GNO
Analog Input Voltage:
{ VSUPPL y(+)
Vs
VSUPPL y(_)

Voltage Between Supply Pins
Total Power Dissipation * (Cerdip)
Operating Temperature Ranges:
HI-516-2.-S
HI-516-5
Storage Temperature Range

-2V
+2V
-2V
+2V
-2V

33V
2000mW
-55 0C to +125 0C
OOC to 75 0C
-65 0C to 150 0C

*Oerate 20mW/oC above 75 0C

ELECTRICAL CHARACTERISTICS (Unless otherwise specified) Supplies =+15V, -15V; VAH (Logic Level High) =+2.4V,
VAL (Logic Level Low) =+O.SV; VOO/LLS =GNO. (Note 1)
OOC to +75 0C

-55 0C to +125 0C
PARAMETER
ANALOG CHANNEL CHARACTERISTICS
VS, Analog Signal Range (Note 2)
RON, On Resistance (Note 3)
IS (OFF), Off Input Leakage Current
IO(OFF), Off Output Leakage Current
IO(ON), On Channel Leakage Current
DIGITAL INPUT CHARACTERISTICS
VAL Input Low Threshold (TTL)
VAH Input High Threshold (TtL)
VAH Input Low Threshold (CMOS)
VAL Input High Threshold (CMOS)
IAH Input Leakage Current (High)
IAL Current (Low)
SWITCHING CHARACTERtsTiCS
tA, Access Time
tOPEN, Break before make delay
tON(EN), Enable Delay (ON)
tOFF(EN), Enable Delay (OFF)
Settling Time (0.1%)
(0.01%)
Charge Injection (Note 4)
Off Isolation (Note 5)
CS(OFF), Channel Input Capacitance
CO(OFF), Channel Output Capacitance
CA, Digital Input Capacitance
COS(OFF), Input to Output Capacitance
POWER REQUIREMENTS
PO, Power Dissipation
1+, Current (Note 6)
1-, Current (Note 6)
NOTES:

TEMP

MIN

Full
+25 0C
Full
+25 0C
Full
+25 0C
Full
+25 0C
Full

-14

Full
Full
Full
Full
Full

TYP

MAX

MIN

+14
750
1,000

-15

620
0.01

TYP

MAX

UNITS

620

-15
750
1,000

n
n

0.Q1

50

50

0.03

0.03
100

100
0.04

0.04

100

100
O.S
2.4
0.3VOO

~

+25 0C
Full
+25 0C
+250C
+25 0C
+25 0C
+25 0C
+25 0C
+25 0C
+25 0C
+25 0 C
+25 0 C
+25 0C

100
20
100
SO
250
SOO
0.3

Full
Full
Full

150
200
150
150

V
V

100

1

IJA

~

IJ.A

150
200

ns
ns
ns
ns
ns
ns
ns
pC
dB
pF
pF
pF
pF

20
100
SO
250
800

90

90

2
18

2
IS

5
0.02

0.02

5

525
25
25

4-33

0.3VOD

0.3

525

1. VDD/llS pin = open or grounded for TTL Compatibility
VDD/lLS pin = VDD for CMOS Compatibility
2. At temperatures above 90 0 C, care must be taken to assure Vs
remains at least 1.0V below the VSUPPL y for proper operation.
3. VIN = ± 10V. lOUT = -100J.lA

V
V

0.7VOO

~I

nA
nA
nA
nA
nA
nA

O.S
2.4

0.7VOO

V

mW
30
30

rnA
rnA

4. VIN = OV, Cl = 100pF, Enable input
pulse = 3V, f = 500kHz.
5. VEN = O.8V, Vs = 3VRMS, f = 500kHz, CL
RL = 1 k, Pin 3 grounded.
6. VEN = +2.4V

= 40pF,

I

TRUTH TABLES.

HI-516 USED AS A 16-CHANNEL MUL TIPLEXERDR

HI-516 USED AS A DIFFERENTIAL
8-CHANNEL MULTIPLEXER

8 CHANNEL DIFFERENTIAL MULTIPLEXER *
USE A3 AS DIGITAL
ADDRESS INPUT

A3 CONNECT TO V- SUPPL Y
ON CHANNEL TO

ON CHANNEL TO

ENABLE

A2

Al

AO

OUT A

OUT B

L

X

X

X

NONE

NONE

H

L

L

L

IA

lB

L

L

H

2A

2B

L

H

L

3A

3B

H

L

H

H

4A

4B

H

H

L

L

5A

5B

NONE

H

H

L

H

6A

6B

6A

NONE

H

H

H

L

7A

7B

7A

NONE

H

H

H

H

8A

8B

H

BA

NONE

L

NONE

lB

ENABLE

A3

A2

Al

AO

OUTA

OUTB

L

X

X

X

X

NONE

NONE

H

L

L

L

L

lA

NONE

H

H

L

L

L

H

2A

NONE

H

H

L

L

H

L

3A

NONE

H

L

L

H

H

4A

NONE

H

L

H

L

L

5A

H

L

H

L

H

H

L

H

H

L

H

L

H

H

H

H

L

L

H

H

L

L

H

NONE

2B

H

H

L

H

L

NONE

3B
4B

H

H

L

H

H

NONE

H

H

H

L

L

NONE

5B

H

H

H

L

H

NONE

6B

H

H

H

H

L

NONE

7B

H

H

H

H

H

NONE

BB

• For 16-Channel single-ended funcdon, tie 'out A' to
'out B', for dual 8-channel function use the A3 address
pin to select between MUX A and MUX B, where MUX A

is selected with A3 low.

DIE CHARACTERISTICS
Transistor Count
Die Size
Thermal Constants

n e Su bstrate to:

647
90 x 147 mils
Oja
Ojc

Process:

4-34

I

50 0 CIW For Ceramic DIP
IBoCIW
'
-VSuppl y
CMOS - 01

PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS
CD
,...

TEST CIRCUIT NO. 2*

TEST CIRCUIT NO.1
ON RESISTANCE vs. INPUT SIGNAL LEVEL

&I)

I

- l O U T 100~A

----V2----

IN

OUT
±10V~

RON

±10V

1.

=.-:!.L

100llA

TESTCIRCUIT NO. 4*

TEST CIRCUIT NO. 3*

OUT

OUT

±10V~

I

A IO(ON)

EN

+0.8V

EN

±10V

+10V-=-

~

T
+2.4V

-

TEST CIRCUIT NO.5
ACCESS TIME
+15V

3:5V

+V

ADDRESS

A3/SDS

RIVE(VA)

~
50%

A2

OV

I

-

+~

OUTPUT

±10V

IN 16

+10V

~-'OV

,

: ...

I

--+r

A1
AO

IN 1
IN 2THRU
IN 15

PROBE

I

1
'A

----..,I
12.5pF

1_

I
I

- _ _ ..II
L __
"Two measurements per channel: +10V/-10V and -10V/+10V.
(Two measurements per device for 'O(OFF): +10V/-10V and -10V/+10V)

4-35

PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS (Continued)

TEST CIRCUIT NO.6
BREAK-BEFORE MAKE DELAY ItOPEN)

ENABLE DRIVE

+15V
3.5V

A3
A2

I I~VEIVAI

IN 1

ADDRESS

~

IN 2
THRU
IN 15
IN 16

A1

~
50%

OUTPUTA

I

-+I

VOUT

50n

50%,

I

+5V

+V

-

j+--

'OPEN

-

2.4V
12.5pF

-15V

TEST CIRCUIT NO.7
ENABLE DELAY (tON(EN). tOFF(EN))

ENABLE DRIVE

+ISV
3.5V

5~-

-

-

-

90%1
-'-~I
---+j 'ONIENII+-

I

.

~'"_ __
I
:

IN 2
THRU
IN 16

OV
\

OUTPUT A

I~

-v

OUT 1-0-.....--.

soon

I 'OFF I
1---+1 IENII-

-1SV

TEST CIRCUIT NO.8
CHARGE INJECTION TEST CIRCUIT

+ISV
+2.4V
3.0V

EN~
vo~

AO.Al.A2.
A3/S DS

T
t.VO IS THE MEASURED VOLTAGE ERROR
DUE TO CHARGE INJECTION. THE ERROR
VOLTAGE IN COULOMBS IS Q = CLX t.Vo.

4-36

m

HI-518

HARRIS

8 Channel/Differential
4 Channel CMOS High Speed Analog Multiplexer
FEATURES

DESCRIPTION
80ns

• ACCESS TIME (TYP)
• SETTLING TIME (0.1%)
• LOW LEAKAGE (TYP)

,250ns
IS(OFF)
5pA

• LOW CAPACITANCE (TYP)

Cs (OFF)

• HIGH OFF ISOLATION AT 500kHz
• LOW CHARGE INJECTION

ID (OFF) 15pA
2pF
CD (OFF) 10pF
86dB
0.3pC

• SINGLE ENDED TO DIFFERENTIAL SELECTABLE (SDS)
• LOGIC LEVEL SELECTABLE (LLS)

APPLICA TlONS

The HI-518 is a monolithic dielectrically isolated, high speed, high
performance CMOS analog multiplexer. It offers unique built-in
channel selection decoding plus an inhibit input for disabling all
channels. The dual function of address input A2 enables the HI-518
to be user programmed either as a single ended 8-channel multiplexer by connection 'out A' to 'out B' and using A2 as a digital
address Input, or as a 4-channel differential multiplexer by
connecting A2 to the V- supply. The substrate leakages and
parasitic capacitances are reduced substantially by using the Harris
dielectric isolation process to achieve optimum performance in both
high and low level signal applications. The low output leakage
current (I D Off < 100pA@25 0 C) and fast settling (tSETTLE;800ns
to 0.01%) characteristics of the device make it an ideal choice for
high speed data acquisition systems, precision instrumentation, and
industrial process control.
The HI-518 is available in an 18 lead dual-in-line package and a
20 lead LCCpackage (-8 only). It is offered in both commercial
and military grades. For additional Hi-Rei screening including
160 hour burn-in, specify the "-8" suffix.

• UATAACQUISITION SYSTEMS
• TELEMETRY
• INDUSTRIAL CONTROL

PINOUT

FUNCTIONAL DIAGRAM
TOP VIEWS

r----

VOO!LLS

I

I
I

OUT A

>--+---~~

DECODER

AO>-+---~H4

IN4A

Al>--~--~~H1

A,
IN 18

OUTB

OECODER

L ___________ -L ______

I

INPUT BUFFER AND DECODERS

4-37

~

MULTIPLEXER SWITCHES

co
,....
Ll)
I

J:

•

SPECIFICATIONS HI-51H
...

A13S0lUTE MAXIMUM RATINGS
DigitallnputOvervoltage:
{ -6V < VAH < +6V
TTL
A2 VSUPPlY (-)

-2V
+2V
-2V

CM OS { VSUPPl y(+)
GND
Analog Input Voltage:
{ VSUPPl Y(+)
Vs
VSUPPlY{-)

+2V
-2V

E l ECTR ICAl CHARACTE R ISTICS

33V
1.19mW

Voltage Between Supply Pins
Total Power Dissipation * (Cerdip)
Operating Temperature Ranges:
HI-518-2,-8
HI-518-5
Storage Temperature Range

-55 0 C to +1250 C
DoC to 75 0 C
-65 0 C to 1500 C

*Derate 11.9mW/OC above 75 0 C

(U nless otherwise specified) Supplies; +15V, -15V; VAH (Logic level High) ,; +2.4 V,
VAL (logic level low) ; +O.8V; VDD/llS; Gnd. (Note 1).
-55 0C to +1250C

PARAMETER

TEMP

MIN

Full

-14

TYP

OOC to +750C

MAX

MIN

+14

-15

TYP

MAX

UNITS

ANALOG CHANNEL
CHARACTERISTICS
Vs Analog Signal Range (Note 2)
RON On Resistance (Note 3)

+25 0C
Full

4S0

IS (OFF) Ofllnput
Leakage. Current

+25 0C
Full

.005

10 (OFF) Off Output

+25 0C
Full

.015

Leakage Current
10 (ON) On Chann.1
Leakage Current

+25 0 C
Full

.015

750
1000

4S0

+15

V

750
1000

n
n

50

nA
nA

50

nA
nA

50

nA
nA

O.S

V

0.05
0.60

50

0.10
50
0.10
50

OIGITAL INPUT
CHARACTE RISTICS
VAL Input Low Threshold (TTLI

Full

VAH Input High Threshold (TTLI

Full

VAL Input Low Threshold (CMOS)

Full

VAH Input High Threshold (CMOS)

Full

IAH Input Leakage Current (High)

Full

1

IAL Input Leakage Current (Low)

Full

20

0.8
2.4

V

2.4
0.3 VOO

O.7VOO

0.3VOO

V
V

O.7VOO

j1A

20

j1A

125
150

os
ns

SWITCHING CHARACTERISTICS
+250C
Full

tA, Access Time

80

125
150

SO

tOPEN, Break before make Delay

+25 0C

20

tON (EN), Enable Delay (ON)

+25 0C

80

150

SO

150

ns

tOFF (EN), Enable Oelay (OFF)

+25 0C

60

125

60

125

ns

Settling Time (0.1%)

+25 0C

250

250

os

+25 0C

800

SOO

ns

(0.01%)

20

ns

Charge Inj.ction (Not. 4)

+25 0C

0.3

0.3

pC

Off Isolation (Note 5)

+25 0C

S6

86

dB

Cs (OFF) Channel Input Capacitance

+25 0C

2

pF

CD (OFF) Channel

Output Capacitance

+25 0 C

CA, Oigitallnput Capacitance

+25 0C

10

10

pF

3

pF

0.02

pF

COS (OFF) inputto Output
+25 0C

0.02

PO, Power Dissipation

Full

360

450

360

540

mW

1+, Current (Not. 6)

Full

12

15

12

18

mA

1-, Current (Note 6)

Full

12

15

12

lS

mA

Capacitance
POWER REQUIREMENTS

1. VOD/LLS Pin = Open or Grounded
ed for TTL compatibility. VOD/LLS
for CMOS compatibility.
2. At temperatures above 90 0 C, care must
be taken to assure Vs remains at least
1.0V below the VSUPPL y.

3. VIN ~ t 10V, lOUT ~ -1 00 IlA.
4. VIN ~ OV, CL ~ 100pF, Enable
Input pulse

= 3V, f

= 500kHz.
1 k. Due to the pin
to pin capacitance between IN 8/48

5. CL = 40pF, RL

=

4-38

(Pin 3) and Out B (Pin 2) channel

8/48 exhibits 60dS of Off Isolation
under the above test conditions.

6. VEN

~

+2.4V.

HI-518

co
,....

TRUTH TABLES

Lt)
I

HI-518 USED AS 8 CHANNEL MULTIPLEXER OR
4 CHANNEL DIFFERENTIAL MU LTIPLEXER
USE A2 AS DIGITAL
ADDRESS INPUT

ON CHANNEL TO

HI-518 USED AS DIFFERENTIAL
4 CHANNEL MULTIPLEXER
A2 CONNECT TO
V- SUPPLY

ON CHANNEL TO

ENABLE

A2

Al

AO

OUT A

OUT B

ENABLE

Al

AO

OUT A

OUT B

L
H
H
H
H
H
H
H
H

X
L
L
L
L
H
H
H
H

X
L
L
H
H
L
L
H
H

X
L
H
L
H
L
H
L
H

NONE
lA
2A
3A
4A
NONE
NONE
NONE
NONE

NONE
NONE
NONE
NONE
NONE
lB
2B
3B
4B

L
H
H
H
H

X
L
L
H
H

X
L
H
L
H

NONE
lA
2A
3A
4A

NONE
lB
2B
3B
4B

PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS
TEST CIRCUIT NO. 2*

TEST CIRCUIT NO.1
ON RESISTANCE vs.
INPUT SIGNAL LEVEL

- l O U T 100JjA

4

IN

EN !-----() +O.8V

.

V2

r--o

OUT

OUT

r-.
~

±10V-::~

f---o

±10V--'-

RON=~

l

lOOIlA

VIN

*Two measurements per channel: +10V/-l0V and
-10V/+l0V.
(Two measurements per device for
'O(OFF): +10V/-l0V and +10V/-l0V)

4-39

HI-518
PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS (Continued)
TEST CIRCUIT NO. 4*

TEST CIRCUIT NO. 3*

OUT

±10V

OUT

-=-

I

EN

A

'D(ON)

-.I..

±10V

EN

+O.8V
+10V~

T

-

+2.4V

"Two measurements per channel: +10V/-l0V and -10V/+l0V.
(Two measurements per device for ID(OFF): +10V/-l0V and -10V/+l0V)

TEST CIRCUIT NO.5
ACCESS TIME
+15V

3.SV

ADDRESS

+V

DRIVE(VAI

~
50%
OV
1

-

--.1

OUTPUT

~-IOV
,

1

1
'A

IN

2T~:~I--o--""

Al

+~
:

±10V

IN 1
r - - -.....-.---1 A2/SDS

=

:nov

IN 8

AO

PROBE

------,
I
I
I

2.4V

1_

I
I
- _ _ ..JI
L __

TEST CIRCUIT NO.6
ENABLE DRIVE

BREAK-BEFORE MAKE DELAY (tOPEN)
+lSV

3.SV
+SV

~

~VE(VAI

~
50%
50%
I

Al

OUTPUTA

son

I

--+I
t+'OPEN

IN I

A2/SDS

ilAOORESS

-

-

AD

IN 2
THRU
IN 7
IN 8

VOUT

2.4V
11.SpF

-15V

4-40

HI-518

co
,...

PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS (Continued)

It)
I

TEST CIRCUIT NO.7
ENABLE DRIVE

ENABLE DELAY (tON(ENh tOFF(EN))
+15V

3.5V

5~I

-

-

90%f

I

IN 1

A2/SDS

OV

\

'ONIENII+-

I

'OFF

IN 2
THRU
IN 8

Al

OUTPUT A

AO

~

_;----If:

~

+V

~..._ __

-

-

EN

I

1--+1 IENII+--

TEST CIRCUIT NO.8
CHARGE INJECTION TEST CIRCUIT

+15V
+2.4V

3.0V

EN~
VO~
T

-----'--'-I-_-{") Vo

Iel

':>Vo IS THE MEASURED VOLTAGE ERROR
DUE TO CHARGE INJECTION. THE ERROR
VOLTAGE IN COULOMBS IS Q
CLX ':>Vo.
0

DIE CHARACTERISTICS
Transistor Count
Die Size
Thermal Constants

356
90 x 93 mils

tfja
tfjc

Ti e Su bstrate to:
Process:

84 0 C/W} For Ceramic Dip
25 C/W

-VSupply
CMOS-OI

4-41

= 100pF

-

HI-524
4 Channel Wid,band and Video Multiplexer

Features

Applications

• Crosstalk (10 MHz) ............................................ < -60dB

Wideband Switching

• Fast Access Time ............... ;....................................150n8

• Radar

• Fast Settling Time ........ ;..........................................200ns

• TV Video

• TTL Compatible

• ECM

Description
The HI-524 is a four channel CMOS analog multiplexer
designed to process single-ended signals with bandwidths up to 10MHz. The chip includes a 1 of 4 decoder for
channel selection and an Enable input to inhibit all
channels (chip select).

feedback element with the amplifier. This feedback
resistance matches and tracks the channel RON
resistance, to minimize the amplifier VOS and its variation
with temperature.
The HI-524 is well suited to the rapid switching of video
and other wideband signals in telemetry, instrumentation,
radar and video systems. It is packaged in an 18 pin
ceramic or plastic DIP and operates on ±15V supplies.

Three CMOS transmission gates are used in each
channel, as compared to the single gate in more conventional CMOS multiplexers. This provides a double barrier
to the unwanted coupling of signals from each inputtothe
output. In addition, Dielectric Isolation (01) processing
helps to insure that Crosstalk is less than -60dB at 10MHz.

The HI-524 is offered in both commercial and military
grades. For aditional Hi-Rei screening including 160 hour
burn-in, specify the "-8" suffix.

The HI-524 is designed to operate into a wide band buffer
amplifier such as the HARRIS HA-2541. The multiplexer
chip includes two "on" switches in series, for use as a

Pinout

Functional Diagram
18

81G GNO

TOP VIEW

F811NI

>-''''t---......l

IN 2

xV
SIG
SIG
SIG
PWR

OUT
GNU
GNU
IN4
GNU
IN 3
GNU

AI

FB (IN)
·V
FB (DUTI
SIG GNU
IN 2
SIG GNU
IN I
EN
AD

FBIOUTI
SIG GNO

~~

_ _.....J

o--t---f--<

IN 3

SIG GNO

OUTPUT

TRUTH TABLE

>-+_ _.....J

IN 4

A1

AD

EN

SIG GNO

X
L
L
H
H

X
L
H
L
H

L
H
H
H
H

>-+---'

SIG GNO ~

-+.::-Ib+::-'

l..-r:-:-1-:-....

·15V PWR +15V

GNO

4-42

EN

AD

Al

ON
CHANNEL
NONE
1"
2

3
4

"CHANNEL 1 IS SHOWN
SELECTED IN THE DIAGRAM

HI-524 Specifications
Absolute Maximum Ratings

Operating Temperature Range

Digital Input Overvoltage:
-6V < VAH < +6V

HI-524-2. -B ...............................................-55 0 C to +125 0 C
H 1-524-5 ........................................................... OOC to 75 0 C
Storage Temp. Range ............................... -65 0 C to 1500 C

Analog Input (VS) or Output (VO)
+VSUPPL Y +2V
-VSUPPL y -2V
Voltage Between Supply ............................................... 33V
Either Supply to Ground ............................................ 16.5V
Total Power Dissipation' (Ceramic) ........................ 1.23W

Electrical Characteristics

'Oerate 12.3mW/o C above 750C

(Unless otherwise specified) Supplies = +15V. -15V; VAH (Logic Level High)
= +2.4V. VAL = (Logie Level Low) = +O.BV; VEN = +2.4V

PARAMETER

TEMP

HI-524-2. -8
-550 C to +1250 C
MIN
TYP
MAX

HI-524-5
DOC to +75 0 C
MIN
TYP
MAX

UNITS

ANALOG CHANNEL CHARACTERISTICS
VS, Analog Signal Range
RON. On Resistance (Note 1)
IS (OFF), Off Input Leakage Current (Note 2)
10 (OFF), Off Output Leakage Current (Note 2)
10 (ON), On Channel Leakage Current (Note 2)
3dB Bandwidth: (Note 3)

Full
+25 0 C
Full
+25 0 C
Full
+25 0 C
Full
+25 0 C
Full
+25 0 C
Full

+10

-10

+10

-10
700

700

1.5K

1.5K
0.2

0.2
50

50
0.2

0.2
50

50
0.7

0.7
50

50

16
11

16
13

V
II
II
nA
nA
nA
nA
nA
nA
MHz
MHz

DIGITAL INPUT CHARACTERISTICS
VAL Input Low Threshold (TTL)
VAH Input High Threshold (TTL)
IAH Input Leakage Current (High)
AL Current (Low)

Full
Full
Full
Full

0.8
2.4

0.8
2.4

0.05
4

1
25

0.05
4

1
25

+25 0 C
+25 0 C
+25 0 C
+25 0 C
+25 0 C
+25 0 C
+25 0 C
+25 0 C
+25 0 C
+25 0 C

150
20
180
180
200
600
-65
4
10
5

300

150
20
180
180
200
600
-65
4
10
5

300

Full
Full
Full

540
18
18

V
V
p.A
p.A

SWITCHING CHARACTERISTICS
tAo Access Time (Note 4)
tOPEN. Break before make delay (Note 4)
tON (EN). Enable Delay (ON). RL = 500n
tOFF (EN). Enable Delay (OFF), RL =50011
Settling Time (0.1%) (Note 4)
(0.01%)
Crosstalk (Note 5)
CS(OFF). Channel Input Capacitance
CD(OFF).Channel Output Capacitance
CA. Digital Input Capacitance

300
250

ns
ns
ns
ns
ns
ns
dB
pF
pF
pF

POWER REQUIREMENTS
PD. Power Dissipation
1+. CUrrent (Note 6)
1-. Current (Note 6)
NOTES:
1. VIN = ±10V; lOUT = 100p.A
(See Test Circuits # 1)
2. va = ±10V: VS = ±10V
(See Test Circuits # 2,3,4.)
3. MUX output is buffered with HA-5033 amplifier
4. (See Test C;'rcuit #5)

25
25

540
18
18

25
25

mW
mA
mA

5. VIN = 10MHz. 3Vp-p on one channel, with any other channel
selected. (Worst case is channel 3 selected with input on channel
4). MUX output is buffered with HA-2541 as shown in Applications
section. Terminate all channels with 75!l.
6. Supply currents vary less than O.5mA for switching rates from OC
to 2M Hz.

4-43

--- .-~.----------HI-524 Performance Characteristics and Test Circuits
ON RESISTANCE

= 25 0 C, VSUPPL Y = ±15V, VAH = 2.4V, VAL = O.BV)

(Unless otherwise specified TA

ON RESISTANCE VS. ANALOG
INPUT VOLTAGE

1,000,-------------:;,...,
TA = +1 250C
900 -r---..;~----~
800
TA = +1250C
RON (III 700

TEST CIRCUIT NO.1

600
500

_lOUT 100pA
--V2-

TA=-550C

400 +-~~~---,--r_r-~_,__~--I
-10 -8 -6 -4 -2 0 2 4 6 8 10

OUT

VIN (VOLTSI
ON RESISTANCE

VS.

SUPPLY VOLTAGE

1,000 - . - - - - - - - - - - - - - - - ,
TA = +250C
R

_

VIN = OV

900

V2

RON (Ill

ON - 100pA

BOO

700

+-~~_,__~~___,____,-r__,____,__~""

9,0

10,0

11 ,0

12,0

13.0

14.0

15.0

(VOLTSI

LEAKAGE CURRENT
TEST CIRCUIT NO. 2*

LEAKAGE CURRENT
VS. TEMPERATURE

ltJ1
N

i

4

+O.BV

OUT

3

A IO(OFFI

±IOV -=-

~

1.0
0.9

LEAKAGE
CURRENT
(nAI

.J.

V
IO(ot~/

1"

TEST CIRCUIT NO. 3*

±IOV-=-

/

2

-=-=FIOV

+--+---o

0.7
0.6
0.5
0.4

EN

+O.BV

t=FIOV

L

O.B

./

/

~

./

/

0.3
'S(OFFI

0.2
TEST CIRCUIT NO. 4*

0.1

/

/
o

+2.4V

f

L

/

"

-'-

I
25

75
100
50
TEMPERATURE (OCI

• Two measurements per channel:
+10Vl-10V and -10Vl+10V
(Two measurements per device for 'D(OFF):
+10V/-10V and -10V/+10V.)

4-44

./

~OFFI

'o(ONI
-=-±IOV

/

/

V

125

150

HI-524
Performance Characteristics and Test Circuits

(Continued)

'o:t
N
It)

I

TEST CIRCUIT NO.5
SETTLING TIME
ACCESS TIME
BREAK-BEFORE-MAKE DELAY *

HI·524
±3V O--+-.s

700

(VIN

~

OV, TA

~

+250C)

TA~+250C

"

0.'
OB
-6

-4

-2

0

2

4

6

01 =-,---'-::---',-:-,--,:-:,-'-,---:-,'-:,,--,:-:,"-,-'-",

ANALOG INPUT, VIN (VOLTS)

SUPPLY VOLTAGE (VOLTS)

LEAKAGE CURRENT

LEAKAGE CURRENT
vs. TEMPERATURE

TEST
CIRCUIT
NO. 2*
(Similar connections for side "8")

'0»

~

'°

1

/

V

IO(OFFI-IS(OFF)

7~

TEMPERATURE

TEST
CIRCUIT
NO. 3*

+O.8V

'QO'

oc

(Similar connections for side "B")

*Three measurements = +10V/-10V.
-10V/+10V. and OV

TEST
CIRCUIT
NO. 4*
_

<4V

f

(Similar co0!l9ctions for side "8")

4-50

±10V

TEST CIRCUITS (Continued)

en

CO)
it)

TEST CIRCUIT
NO.5

I

SUPPL Y CURRENT vs.
TOGGLE FREQUENCY

'4
(FUNCTIONAL LlMIT)-

2

/
VS\PPL Y '"

•
6
VSUPPL V 1=

± 1C_ _

4

A,

± 15

7/
lLJ

IN3A

EN

10kHz
100kHz
TOGGLE FREQUENCY, Hz

1kHz

-=-

-=-

~

100Hz

~

IN2A

IN4A

~V

2

+10/+5 V

HI-539

AD

VA

lMHz 3M Hz 10MHz

{HIgh" 4.0V
LOW'" OV
50% DUTY CYCLE

-=-

-=-

(SIMILAR CONNECTIONS FOR "8" SIDE)

TEST CIRCUIT
NO.6
ACCESS TIME vo.
LOGIC LEVEL (HIGH)

+15V
320
300

A,

,--.....-.-....,AO

]
~
;::

HI-539

~
u

PROBE

u 240

=

~

..." 220
200

10

3

11

12

13

14

-=-

-----,

EN

1
I

+5V

I
I
I
L- ____
...II

15

LOGIC LEVEL (HIGH), VOL TS

(SIMILAR CONNECTIONS FOR "8" SIDE)

ACCESS TIME
4V

__ ~.

ADDRESS

I

~ DRIVE (VA)

~.

-~

I

-

+~

I~

-

OUTPUT

~
I
-'OV

I

--.1

1

1

f-- VA INPUT

Y

IDIV .

I

!1
l

I

S,ON

I
tA

1_

OUTPUT
5V/DIV.

S4DN

Example: tA for 4V logic level

200ns/DIV.

4-51

J

TEST CIRCUITS (Continued)
TEST CIRCUIT
NO.7
ADDRESS DRIVE

BREAK-BEFORE-MAKE DELAY (tOPEN)
+16V

I I

VAH =4V

I I~VE(VA)
ADDRESS

~

~
50%
50%
, ,
.......

-

-QUTPUTA

r-I

VA INPUT

VID'V .

,

S,ON

I+-

"ON

V-

DLTPUT

'l'/D'I - r-

1

hOPENI

v

lOOns/DIV.

(SIMILAR CONNECTION FOR "6" SIDE)

TEST CIRCUIT
NO;S
ENABLE DRIVE

ENABLE DELAY (tON(EN). tOFF(EN))

I I
VAH =4V

5~/
I

I

OV

I

OUTPUT A

r-

:

tONIEN) -----t1
I

I

I

I

I

DRIVE
2V/DIV.

.. 1 .. 1
I II

I
~
90%

ENABLE

90%

52 THRU S4

I+- I toFF I
I - I IENI I+--

S,ON

OUJpUT
2V/DIV·l

O~FI

100ns/DIV,

(SIMILAR CONNECTION fOR "BH SIDE)

TEST CIRCUIT
NO.9
SINGLE-ENDED CROSSTALK
HI-539

01 FFERENTIAL CROSSTALK

INSTRUMENTATION

INSTRUMENTATION

AMPLIFIER-

AMPLIFIER-

r

mVp _p

I

• AD606 OR 883630, FOR EXAMPLE

4-52

,

,\

1J1
I W

DEFINITIONS
Q)

CHARGE INJECTION - Charge (in pC) transferred, during a
transition between channels, through the internal gate-tochannel capacitance. The resulting voltage error varies inversely with the output (or input) capacitance.
'

DIFFERENTIAL OFFSET VOLTAGE ( 6 VOS) - Voltage
between the multiplexer output terminals with both channel
input terminals shorted to ground.

M
in
I

DIFFERENTIAL ON RESISTANCE (6RON) - The absolute
difference in On Resistance for the two sides of a channel.

CROSSTALK - Signal at the multiplexer output, coupling
though the COS capacitance of an OFF channel. Amplitude
is proportional to source resistance for the ON channel. See
Test Circuit # 9 for single-ended and differential versions
of crosstalk.

INPUT TO OUTPUT CAPACITANCE (CDS) - Capacitance
from one input terminal of a channel to the corresponding
output of the multiplexer. This parameter is responsible
for Crosstalk.

DIFFERENTIAL LEAKAGE CURRENT ( 6IS(OFFl.
610(OFFl. 6ID(ON)) - The absolute difference in leakage
for the two sides of a channel.

APPLICATIONS
GENERAL
The H1-539 accepts inputs in the range -15V to +15V, with
performance guaranteed over the ±10V range. At these higher
levels of analog input voltage it is comparable to the HI-509,
and is plug-in compatible with that device (as well as the
HI-509AI. However, as mentioned earlier, the HI-539 was
designed to introduce minimum error when switching low level
inputs.
Special care is required in working with these low level signals.
The main concern with signals below 100mV is that noise,
offset voltage, and other aberrations can represent a large
percentage error. A shielded, differential signal path is essential, especially to maintain a noise level below 50 fJ.Vrms.
LOW LEVEL SIGNAL TRANSMISSION
The transmission cable carrying the transducer signal is critical
in a low level system. It should be as short as practical and
rigidly supported. Signal conductors should be tightly twisted
for minimum enclosed area, to guard against pickup of electromagnetic interference, and the twisted pair should be shielded

against capacitively coupled (electrostatic) interference.
A braided wire shield may be satisfactory, but a lapped foil
shield is better since it allows only one tenth as much leakage
capacitance to ground per foot. A key requirement for the
transmission cable is that it presents a balanced lineto sources
of noise interference. This means an equal series impedance
in each conductor plus an equally distributed il11pedance from
each conductor to ground. The result should be signals equal
in magnitude but opposite in phase at any transverse plane.
Noise will be coupled in phase to both conductors, and may
be rejected as common mode voltage by a differential amplifier
connected to the multiplexer output.
Coaxial cable is not suitable for low-level signals because the
two conductors (center and shield) are unbalanced. Also,
ground loops are produced if the shield is grounded at both
ends by standard BNC connectors. If coax must be used, carry
the signal on the center conductors of two equal-length cables
whose shields are terminated only at the transducer end. As
a general rule, terminate (ground) the shield at one end only,
preferably at the end with greatest noise interference. This is
usually the transducer end for both high and low level signals.

Table 1
IMPEDANCE
PER FOOT

WIRE
GAGE

EQUIVALENT
WIDTH OF P.C.
CONDUCTOR
(2 oz. Cu.)

D.C.
RESISTANCE
PER FOOT

INDUCTANCE
PER FOOT

AT 60Hz

AT 10kHz

18
20
22
24
26
28
30
32

0.47"
0.30"
0.19"
0.12"
0.075"
0.047"
0.029"
0.018"

0.0064S1
0.0102.11
0.0161S1
0.0257S1
0.041S1
0.06612
0.105S1
0.168S1

0.36JlH
0.37J.lH
0.37J.lH
0.40J.lH
0.42J.lH
0.45J.lH
0.49J.lH
0.53J.lH

O.0064S1
0.0102.11
0.0161S1
0.0257.11
0.04112
0.06612
0.10512
0.16SS1

0.0235.11
0.0254.11
0.0288S1
0.0345S1
0.0488S1
0.0718.11
0.110.11
0.171S1

4-53

~

LU

X

LU
....J
0-

6

~

:;;;

APPlICA TlONS (Continued)
WATCH SMALL t:N ERRORS

The use of bias current resistors is acceptable only if one is
confident that the sum of signal plus common-mode voltage
will remain within the input range olthe multiplexer/amplifier
combination.

Printed circuit traces and short lengths of wire can add substantial error to a signal even after it has traveled hundreds of
feet and arrived on a circuit board. Here, the small voltage
drops due to current flow through connections of a few
milliohms must be considered, especially to meet an accuracy
requirement of 12 bits or more.

Another solution is to simply run a third wire from the low
side of the signal source, as in Figure 1B. This wire assures a
low common-mode voltage as well as providing the path for
bias currents. Making the connection near the multiplexer
will save wire, but it will also unbalance the line and reduce
the amplifier's common-mode rejection.

Table 1 is a useful collection of data for calculating the effect
of these short connections. (Proximity to a ground plane will
lower the values of inductance.)

DIFFERENTIAL OFFSET, .lVOS

As an example, suppose the HI-539 is feeding a 12 bit converter system with an allowable error of ±1/2 LSB (±1.22mV).
If the .interface logic draws 100mA from the 5V supply, this
current will produce 1.28mV across 6 inches of # 24 wire;
more than the error budget. Obviously, this digital current
must not be routed through any portion of the analog ground
return network.

There are two major sources of D. VOS. That part, due to the
expression (RON D.IO(ON) + IO(ON) D.RON) becomes significant with increasing temperature, as shown in the Electrical
Characteristics section. The other source of offset is the
thermocouple effects due to dissimilar materials in the signal
path. These include silicon, aluminum, tin, nickel-iron and
(often) gold, just to exit the package.

PROVIDE PATH FOR IBIAS

For the thermocouple effects in the package alone, the constraint on D. VOS may be stated in terms of a limit on the
difference in temperature for package pins leading to any
channel of the H1-539. For example, a difference of O.13 0 C
produces a 5J.lV offset. Obviously, this D.T effect can domin~
ate the D. VOS parameter at any temperature unless care is
taken in mounting the H1-539 package.

The input bias current for any 0 C-coupled amplifier must have
an external path back to the amplifier's power supply. No
such path exists in Figure lA, and consequently the amplifer
output will remain in saturation.
A single large resistor (1 MD to 1OMD) from either signal line
to power supply common will provide the required path,
but a resistor on each line is necessary to preserve accuracy.
A single pair of these bias current resistors on the HI-539
output may be used if their loading effect can be tolerated
(each forms a voltage divider with RON). Otherwise, a resistor
pair on each input channel of the multiplexer is required.

Temperature gradients across the HI-539 package should be
held to a minimum in critical applications. Locate the HI-539
far from heat producing components, with any air currents
flowing lengthwise across the package.

4-54

APPLICATIONS (Continued)

en

M
HI-539

+v

"FLOATING"
SOURCE

-v
Figure 1A

HI-539

+v

I

I

<~

-v

.>

1 T010M : :

4>

 4,000 Volts
• Guaranteed RON Matching
• 44 V Maximum Power Supply
• Break-Before-Make Switching
• Analog Signal Range ....•.•.•.•.••••. ±15 V
• Access Time (Typical) •.•..•.••••••.•. 500 ns
• Standby Power (Typical) .•...•.•...•.• 7.5 mW

The HI-5461547 are offered in both commercial and military grades. Additional HiRei screening to MIL-STD-883 available, specified by the "/883" suffix. For details,
see the separate "883" data sheet.

Applications
• Data Acquisition

Each device is available in a 16pin plastic or ceramic DIP, a 20 pin ceramic LCC or
20 pin plastic LCC (PLCC) package.

• Industrial Controls
• Telemetry

Pinouts

Functional Diagrams
Top View

OUT

.. VSUpp

1B

Ne
Ne

11

VSUpp

16
15

INB
INT

"13

1N6
1N5

IN 16

IN 15
IN
IN
IN
iN

14
13
12
11

IN 10

10

,"9

11

GNO
VRH
ADDRESS A3

12
'3

12

IN.

11

1N3
1N2

20
19
18
17

16
15

14

INI
ENABLE
ADDRESS AD
ADDRESS AI
ADDRESS AZ

H11-546 (ceramic)
H13-546 (plastic)

"""":NM

"'::f"1r.! CD t--

~,~~~~~:@;

H14-546 (ceramic)
HI4P546 (plastic)

HI-546

QlCCalCCCDCOCD
T""" N
C") "<
LJ.J

IN15

AO

IN16

...J

EN

OUT

5=>

500

-=

en

THRU

"-

+4V

:;:

10M
Toggle Frequency, Hz

·Similar Connection for HI-54?

TEST
CIRCUIT

VS.

+15V

90 0

E
.=
:i.

::-

A3

80 0
70 o~- t---

f-V~EF}OPE'N fo~ Logic Hi~h L';"<'6V

I

AO

son,

........

40 0
30 3

4

-=

""
5

V'
'N ,

IN 2THRU IN15

A,

VAEF'" Logic High for logic High Levels...-'6V
0 1\
50 0

VREF

A,

60

0

ACCESS TIME
LOGIC LEVEL (HIGH)

NO.8

ACCESS TIME VS. LOGIC LEVEL (HIGH)

-1S/-1OV

·HI-546

EN

INIS
OUT

+4.0V

7

8

9

10

II

12

Logic Level (High), Volts

13

14

I
I
L ____
...II

15

·Similar Connection for HI-54?

Switching Waveforms
V AH - 4.0V

ADDRESS
RIVEIVAI

~
',vAH
' ov
I

I~PUT

VA
2V/OIV

-

.~

r

OUTPUT

~
I
-IOV
I

--+1

'A

I
I

I
6

I~

PROSE

-----,

1_

DUTPUT A
5V/DIV.

\

I

r-...
200ns!Dlv.

I

I
J

HI-546/547

Switching waveforms (continued)
TEST
CIRCUIT

BREAK-BEFORE-MAKE DELAY(tOPEN)

NO.9

BREAK-BEFORE-MAKE
DELAY (tOPEN)

VAH' 4.0 V

•,y

I~PUT

VA
2V/DIV .

r-iADDRESS

~

~VEIVAI

.

*HI-546 T:~:

~
\..

. .... OUTPUT

50'

lAON

8AON

I/'

VOUT

50'

,

_

I
14--

J

l :1 1

OU+PUT
0.5V/DIV.

V

IOPEN

'1
~

100ns/D,y.

'Similar Connection for HI-547

TEST
CIRCUIT
NO. 10

ENABLE DRIVE
VAH

5~I

-

90'

4.0 V

-

-

ENABLE DELAY (tON(EN),tOFF(EN»

t. .--.. . ,.

{.---+:-'\
I

--.--...1'1

ENABLE DELAY (tON(EN),tOFF(EN)

OV

OUTPUT

lA ON

.. ~

I ·'OU· I
- I lEN) I+--

--+j 'ONIENII+,--

I

I

t- IN 1 THRU

r

OUTPUT A ' \
2V/DIV.

I I

IN 8 OFF

100ns/D,y.

'Similar Connection for HI-547

Schematic Diagrams

ADDRESS INPUT BUFFER
AND LEVEL SHIFTER

LEVEL
SHIFTED
AOOAESS
TO DECODE
LEVEL

....+-;;t---;-- TO~J~i~
DECODE

"

HI-546/547
Schematic Diagrams (continued)
ADDRESS DECODER

olc~~~ >.
TO P CHANNEL
DEVICE OF
THI! SWITCH

MULTIPLEX SWITCH
OVEFMlLTAGE PROTeCTION

r-------- --------,
~

V+

I
I
I

:

TO N CHANNEL

DEVICE OF
THE SWITCH

A/ OR

A/
D:C~~

»----------4_-----'

ENABLE

Delete A3 or As
Input for HI-547

Die Characteristics

v

Transistor Count
Die Size
Thermal Constants

6ja
6jc

Tie Substrate to:
Process:

485
161 x 85 mils
50OCIW} For Ceramic Dip
180CIW
-VSupply
CMOS-DI

4-61

mHARRIS

f ..

I

Single a/Differential 4 Channel
CMOS Analog Multiplexers with Active Overvoltage Protection
Features
l

•

Description

Analog Overvoltage Protection ••••••••. 70 Vpp

The H1·548 and 549 are analog multiplexers with Active Overvoltage Protection and
guaranteed RON matching. Analog input levels may greatly exceed either power supply without damaging the device ordisturbing the signal path of other channels.
Active protection circuitry assures that signal fidelity is maintained even under fault
conditions that would destroy other mUltiplexers, Analog inputs can withstand con·
stant 70 volt peak-to-peak levels and typically survive static discharges beyond 4,000
volts. Digital inputs will also sustain continuous faults upto 4 volts greater than either
supply. In addHion, signal sources are protected from short circuiting should multiplexersupply loss occur; each input presents 1kIJ of resistance under this condition. These
features make the HI-548 and HI-549 ideal for use in systems where the analog inputs originate from external eq uipment or separately powered circuitry. Both devices
are fabricated with 44 volt dielectrically isolated CMOS technology. The 548 is an
8 channel device and the 549 is a 4 channel differential version. If input overvoltage
protection is not needed, the HI-508 and HI-509 multiplexers are recommended. For
further information see Application Notes 520 and 521.

• No Channel Interaction During Overvoltage
• ESD Resistant •••••••. : ••.•.• '.'. >4,000 Volts
• Guaranteed RON Matching
• 44 V Maximum Power Supply
• Break·Before·Make Switching
• Analog Signal Range •.•••.•.•••••••.• ±15 V
• Access Time (Typical) ••••••.••••.••.• 500 ns
• Standby Power (Typical) ••.•••••••..•• 7.5 mW
I

The HI-548/549 are offered in both commercial and military grades. Addition Hi-Rei
screening to MIL-STP-883 available, specified by the "/883" suffix. For details, see
the separate "883" data sheet.

Applications
• Data Acquisition

Each device is available in a 16 pin plastic or ceramic DIP, a 20 pin ceramic LCC or
20 pin plastic LCC (PLCC) package.

• Industrial Controls
• Telemetry

Functional Diagrams

Pinouts
~

..,

;;:; ~t:i;~
-~-~

Top View

~

Al
A2
GND
+VSUP
IN 5
IN 6
IN 7
IN 8

AO
EN
·VSUp
IN I
IN 2
IN 3
IN 4
OUT

ENABLE

IN4
OUT
(N.C.)
IN 8
IN 7

It

IN I
IN 2

••
•

An
(N.C.)
A,
A2

OUT

,I -

IN B

It

L___
II
II
II
II
II

DECDOERI
DRIVER

It
I

II

L.. ___

~

H11·548 (ceramic)
H13·548 (plastic)

CQ~~~~

~-~~C!J

H14·548 (ceramic)
HI4P548 (plastic)

HI·548

~

:S~~~~

Top View

AU
EN
·vSUp
IN lA
IN 2A
IN 3A
IN 4A
OUT A

IN IAo-Il-l\N-....._-d~...~----+-oOUTA

~~t!..~~

Al
GNU
I+vsup
IN 18
IN 28
IN 38
IN 48
OUT 8

•

I

IN 4AI
! ENABLE

IN4A
OUT A
(N.C.)
aUTB
IN 4B

An
(N.C.)

c:·>-Io-llM_..:..a1........

IN IBo-....fIN""'4".,~-O'!""4...............~-oDUT B

••

A,
GND

H11·549 (ceramic)
H13·549 (plastic)
AD AI

H14·549 (ceramic)
HI4P549 (plastic)

4-62

HI·549

EN

HI-548/549 Specifications

en

ABSOWTE MAXIMUM RATINGS (Note 1)

o::t

Lt)

Voltage between Supply Pins
V+ to Ground
V- to Ground
Digital Input Overvoltage:

Continuous Current, S or D:
20 mA
Peak Current, S or D
(Pulsed at 1 ms, 10% duty cycle max): 40 mA
Power Dissipation* (Ceramic)
1.28 W
Operating Temperature Range:
HI-548/549-2,
-55°C to +125°C
HI-548/549-4
-25°C to +85°C
HI-548/549-5
O°C to + 75°C
Storage Temperature Range -65°C to +150°C

44V
22V
22V

VEN, VA {vsuPPI Y(+)
+4V}
VSupplyH
-4 V
or 20 mA, whichever occurs first.
Analog Input Overvoltage:
Vs {VsuPPI Y(+)
VSupplyH

.......
CO
o::t

Lt)
I

*Derate 12.8 mW/oC above TA = 75°C

+20V}
-20V

ELECTRICAL CHARACTERISTICS Supplies= + 15 V, -15 V; Vjl.H(Logic Level High) =
+4.0 V, VAL(Logic Level Low) = +0.8 V. (unless otherwise spcified).
For Test Conditions, consult Performance Characteristics Section.
HI-548/HI-549

-2
PARAMETER

TEMP. MIN. TYP. MAX. MIN. TYP. MAX.

ANALOG CHANNEL CHARACTERISTICS
'VS, Analog Signal Range
'RON, On Resistance (Note 2)

'ID (OFF), Off Output Leakage Current (Note 3)
HI-548
HI-549
'ID(OFF) with Input Overvoltage Applied (Note 4)
'ID (ON), On Channel Leakage Current (Note 3)
HI-548
HI-549
IDIFF. Differential Off Output Leakage Current
(HI-549 Only)
DIGITAL INPUT CHARACTERISTICS
'VAL, Input Low Threshold
(Note 8)
'VAH" Input High Threshold
'lA, Input Leakage Current (High or Low) (Note 5)
SWITCHING CHARACTERISTICS,
'tA, Access Time
'tOPEN, Break-Belore-Make Delay
'tON (EN), Enable Delay (ON)
'tOFF (EN), Enable Delay (OFF)

HI-546
HI-549

CA, Digital Input Capacitance
CDS (OFF), Input to Output CapaCitance
POWER REQUIREMENTS
PD, Power Dissipation
'I +, Current (Note 7)
'1-, Current (Note 7)
'100% tested for Dash
NOTES: 1.

8. Leakaae currents not tested 'at

Full
+25°C
Full
+25°C
+25°C
Full
+25°C
Full
Full
+25OC
Full
+25°C
Full
Full
Full

-15
1.5
1.8

+15
1.8
2.0
7.0

0.03
50

50
0.1

0.1
200
100

200
100

4.0

4.0
2.0

0.1

0.1
200
100
50

200
100
50

0.8

0.8

en

V

KO
KO
%
nA
nA
nA
nA
nA
nA
pA
nA
nA
nA
nA

1.0

!'8
!'8

1000

ns
ns
ns
ns
ns

4.0
1.0
0.5

a:
A2 AI

AD

EN

"ON"
CHANNEL

X X X L
L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H

80

25

300
300

25
500
1000
500
1000

1.2
3.5
68
5
25
12
5
0.1
7.5
0.5
0.02

2.0
1.0

80
300
300
1000

50

1.2
3.5
68
5
25
12
5
0.1
7.5
0.5
0.02

10nA is the practical lower limit for high speed measurement In the production test environment

4

Analog Overvoltage

-100/iA

!'8
!'8
dB
pF
pF
pF
pF
pF

2.0
1.0

mW
mA
mA

5

Digital input leakage is primarily due to the clamp diodes (see
Schematic), Typical leakage is less than InA at 250C

6

VEN = O.SV, RL = lK, CL = lSpF, Vs = 7VRMS. f = 100kHz. Worst case
isolation occurs on channel 4 due to proximity of the output pins
VEN, VA

=

OV or 4.0V

To drive from DTLITTL Circuits. 1kU pull-up resistors.to +5.0V supply
are recommended

±33V

4-63

AI

AD

EN

X X L

0.5
1.0

50

1.0

V
V
pA

-5500.

3

~

+15
1.5
1.8
7.0

0.03

Full
Full
Full

VOUT

=

1.2
1.5

4.0

+25°C
Full
+25°C
+25°C
Full
+25°C
Full
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C

2

±10V, lOUT

-15

NONE
1
2
3
4
5
6
7
8

H
H
H
H
H
H
H
H

HI·549
Full
Full
Full

Absolute maximum ratings are limiting values, applied Individually,
beyond which the serviceability of the circwt may be impaired
Functional operation under any of these conditions is not necessarily
implied.
=

TRUTH TABLES
~NITS

HI·548

6RON, Any Two Channels
'IS (OFF), Off Input Leakage Current (Note 3)

Settling Time (0.1%)
(0.01%)
"OFF Isolation" (Note 6)
Cs (OFF), Channel Input Capacitance
CD (OFF), Channel Output Capacitance

HI-548/549
-4, -5

L
L
H
H

L
H
L
H

H
H
H
H

ON
CHANNEL
PAIR
NONE
1
2
3
4

xww

...J

a..

is

:::;)

::;;;

~---- .-~~-------

HI-548/549
Performance Characteristics and Test Circuits

ON RESISTANCE vs.
INPUT SIGNAL LEVEL, SUPPLY VOLTAGE

Unless Otherwise Specified TA = 25°C, VSupply = ±15 V,
VAH = +4 V, VAL = 0.8 V
TEST CIRCUIT
NO.1

NORMALIZED ON RESISTANCE
vs. SUPPLY VOLTAGE

ON RESISTANCE
vs. ANALOG INPUT VOLTAGE
1.4
TA-+125 DC

1.3

'"11. 1

!

~
~

t

I

c: 1.2

-'

Q!!

~

.......

1.3

......

c •

~~

i;

TA = -55DC

0.9

+125 DC ~TA ~-55DC _
VIN =+5V

1.5

r:;

TA - +25 DC

1. 0

i

~
1.4
·ii;'+1

~

zir:

O. 8

!:.

1. 2

........

1. 1
1. 0

o. 9
O. 8

-10

-8

-6

-4

±5

10

-2
V1N - Analog Input (Volts)

LEAKAGE CURRENT VS. TEMPERATURE
100nA

±6

±7

TEST CIRCUIT
NO.2·

gn
N

:

~E3~~~~IO(ONI,

±9
±lO ill
±12
Supply Voltage - Volts

±ll

t14

+O.8V

ff OUTPUT
CURRENT

±10V-="

rL

-V /

A IDIOFFl

./

/

+o.av

-=:-+'f.OV

"*

J-

"'lINo measurements per channel:
+10 V/-10 V and -10 V/+10 V•
(Two measurements per device for IO(OFF):
+10 v/-10 V and -10 V/+10 V.)

./

Pi~~~~TCURRENT IS (Offl

...::::... ±10V

10pA

25'

50'

75'
100'
Temperature -OC

+4V

ANALOG INPUT
OVERVOLTAGE CHARACTERISTICS

;-11
5 5· ~ 1
;1
2

!~

ANALOG INPUT
CURRENT (lIN';"

9 3-~ E
6 2'~

3I.! 1
o

TEST CIRCUIT
NO.5

...-

4-';!E-

......-

;;.-

...... 1""

/'

V

,V

OUTPUT OFF
LEAKAGE CURRENTlolOFfI
±18
~21
±24
±27
t30 t3l t3G
Y,N - Analog Input OveNaltage (Volts)

~

.!lr/
±15

±15

TEST CIRCUIT
NO.3·

TEST CIRCUIT
NO.4·

100pA

t8

OUT

LEAKAGE

/

...... ......

4-64

f
ANALOG INPUT
OVERVOLTAGE CHARACTERISTICS

HI-548/549

Q)

Performance Characteristics and Test Circuits (continued)

"I:t

&I)

ON CHANNEL CURRENT VS. VOLTAGE
±14

1: ±1 2
E ±to
~

'"'

!......:V

h

±8

0. ~
L&:: ~

l..o"

TEST CIRCUIT

CO
"I:t

ON CHANNEL CURRENT
VS. VOLTAGE

NO.6

V-55OC
+25 0C

&I)
I

~ ~+1250C

t...- P"

:!6

±8

±10

±12

VIN - Voltage Across Switch

+15/+1OV

SUPPLY CURRENT

SUPPLY CURRENT vs. TOGGLE FREQUENCY

vs. TOGGLE FREQUENCY
TEST CIRCUIT

"

NO.7

IN'r-~:>---'

T~:~f"--'-Cr-"

*HI-548

IN8
OUT 1---<:>-......._ - ,

-=-

+4V

VAH '" 4V
VAL = O.8V
50% DUTY CYCLE

Toggle Frequency. Hz

'Similar connection for HI-549

ACCESS TIME VS. LOGIC LEVEL (HIGH)

TEST CIRCUIT

NO.8

VS.

A,

900
]

800

~

6001\.

,

500 \

~

:!-

40 0
300 3

IN I

IN 2 THRU IN 7 f"--{)---,

AI

E 70 0
;::
t!

ACCESS TIME
LOGIC LEVEL (HIGH)

*HI-548

AO

SOH

IN 8

EN

PROSE

----I

OUT

I

...... ,......
4

5

I

I
6

8 9 10 11 12 13
Logic LeveIIHigh), Volts

14

I
I

15

Switching Waveforms

ACCESS TIME

VAH = 4.0

ADDRESS
DRIVE(VA)

~
5R
W
1

L ____
-'I

'Similar connection for HI-549

I-- I--

I~PUT

1

VA
lV/OIV.

I

-

'~OVOUTPUT A
I

V

90%

I

I

I

1

-IOV

OUTPUT A

\

_I'A 1_

5¥/OIV j

J

i'..
200ns/Oiv.

4-65

I

HI-548/549

Switching Waveforms (continued)
TEST CIRCUIT
NO.9

BREAK-BEFORE-MAKE DELAY (tOPEN)

BREAK-BEFORE-MAKE DELAY(tOPEN)

~
50~',
50%
I

I~PUT

VA
2V/DIV

r

OUTPUT

/

I

I+'OPEN

-.I

OUTPUT
.5V/DIV.

\ I
,I
~

V
lOOns/Diy.

'Similar connection for HI·549

TEST CIRCUIT
NO. 10
ENABLE DRIVE

ENABLE DELAY (tON(EN),tOFF(EN»

ENABLE DELAY (tON(EN),tOFF(EN»

EN;8LE

DRIVE
2V/DIV.

90%{
_.,.---J

II

I

OUTPUT
2VIDIV.

\

---+j 'ON lEN 11 -

I

I
1--+1

'-

100ns/DIY.

'Similar connection for HI-549

Schematic Di~grams
TTL REFERENCE CIRCUIT

r----------,
I
.
vd
I
I

I
I

I

I

I

I
I
I

ADDRESS INPUT BUFFER
. " AND LEVEL SHIFTER

I
I 03
I
IL __G!!D______ ....JI
lEVEL SHIFTER

I

LEVEL
SHIFTED
ADDRESS
TO DECODE

I
I

LEVEL

~+.,+--t.. SHIFTED

~~~~~~I~r,

I
I

II

1\

I
GND
L:':";;;'
___ ' __ .___________________________
JI

4-66

ADDRESS
TO DECODE

HI-5481549

en

Schematic Diagrams (continued)

~
It)

CO
~
It)

MULTIPLEX SWITCH

I

DE~~g~ )i:l>------------,--------,-,

ADDRESS DECODER

EJ
v-

L _______________

~

ENABLE

v-

Die Characteristics

DE~~~r~:>.o>----------~--------'

Transistor Count
Die Size
Thermal Constants
Tie Substrate to:
Process:

253
116 x 79 mil
(J ja

(Jjc

4-67

78OCIW} For Ceramic Dip
250CIW
-VSuppJy
CMOS - DI

·m HARRIS

HI·1S1SAI1S2SA
Low Resistance Single S/Differential
4 Channel CMOS Analog Multiplexers

FEATURES

DESCRIPTION

• SIGNAL RANGE

±15V
250n

•

"ON" RESISTANCE (TYP.I

•

INPUT LEAKAGE AT +125 0 C (TYP.)

20nA

•

ACCESS TIME (TYP.)

350ns

•

POWER CONSUMPTION (TYP.)

•

DTLrrn COMPATIBLE ADDRESS

•

-55 0 C to +125 0 C OPERATION

The HI-1818A/1828A are monolithic high performance CMOS
analog multiplexers offering built-in channel selection decoding
plus an inhibit (enable) input for disabling all channels.
Dielectric Isolation (01) processing is used for enhanced
reliability and performance (se~ Application Note 521).
Substrate leakage and parasitic capacitance are much lower,
resulting in extremely low static errors and high throughput
rates. LOI(\I output leakage (typically O.lnA) and low channel
ON resistance (250 n) assure optimum performance in low level
or current mode applications.

5mW

APPLICA TIONS
•

DATA ACQUISITION SYSTEMS

•

PRECISION INSTRUMENTATION

•

DEMULTIPLEXING

•

SELECTOR SWITCH

The 1818A is a single-ended 8 channel mu!tiplexer, while the
H1-1828A is a differential 4 channel version. Either device
is ideally suited for medical instrumentation, telemetry systems,
and microprocessor based data acquisition systems.
The HI-1818A/1828A is offered in both commercial and military grades. For additional Hi-Rei screening including 160
hour burn-in, specify the "-8" suffix.

FUNCTIONAL DIAGRAM

PINOUT
HI~1818A

ADDRESS Al
+5.0V SUPPLY
ENABLE
ADDRESS A2
IN 8
-IN 7
IN 6
IN 5

HI-1818A

Top View
16
15
14
13
12
11
10

2
3
4
5
6
7
8

ADDRESS AO
-15VSUPPLY
+15V SUPPLY
INI
OUT
IN2
IN 3

ADDRESS {
INPUT
BUFFERS

IN I

OUT

IN8

9 IN 4
HI-1828A

HI-1828A
Top View
ADDRESS Al
+5.0V SUPPLY
ENABLE
OUT 5THRU 8
IN 8
IN 7
IN 6

1
2
3
4
5
6
7
IN 5 8

EiiffiE

16
15
14
13
12
11
10

".""{

ADDRESS AO
-15V SUPPLY
+15V SUPPLY
IN 1
OUT 1 THRU 4
IN 2
IN 3

INPUT

8UFFERS

9 IN 4

4-68

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS (NOTE 1)
40.0V
30.0V

Supply Voltage Between Pins 14 and 15
Logic Supply Voltage, Pin 2
Analog Input Voltage: VSuppl y +2V

Digital Input Voltage
Total Power Dissipation (Note 2)*
Storage Temperature Range

VSupply -2V

V-Supply to V+ ~upply
1.11W
-65 0 C to +150 0 C

*Derate 11.1mW/OC above 75 0 C for ceramic package.

c(
CO
N
CO

...
......~
CO

CO

..!.

:::E:

ELECTRICAL CHARACTERISTICS
Supplies" +15V, -15V. +5V

PARAMETER

HH818A·21182BA·2
_55 0 C to +125°C

250
300

"5
400
500

n
n

50

20

50

nA

100
50

250
125

100
50

250
125

nA
nA

100
50

250
125

100
50

250
125

nA
nA

0.4

V
V

1

~A

250

Full

300

"5
400
500

-15

+2SoC

"'SIOFFI, Input Leakage Current
"'OIONI. On Channel Leakage Current

Full

20

IHI·1818A}
IHI-1828A}
'OIOFFI Output leakage Current
IHI-181BAI
IHI-1828A}

Full
Full
Full

IA. Input Leakage Current

-15

UNITS

MIN.

VAH,lnput High Threshold (Note 4)

Full

MAX.

MAX.

0lG1TAL INPUT CHARACTERISTICS
VAL,lnput low Threshold

MIN.

TYP.

TYP.

ANALOG CHANNEL CHARACTERISTICS
·VIN. Analog Signal Range
·RON. ON Resistance (Note 3)

TEMP.

HI-1818A-SI1828A-5
DoC to+7S OC

V

Break-Befort-Make Oeley
Settling Time (0.1%1
10.025%)
CIN. Channel Input CapacItance
COUT. Channel Output"Capacitance
IHI-181BA}
IHI-1828A}
COSIOFFI. Orain-To-Sourca Capacitance
co, Oigitallnpu~ Capacitance

tONIEN), Enable delay (ON)

Full

Full
Full
Full

0.4
4.0

4.0
.01

1

.01

+2S oC
Full

350

+25oC
+2SoC
+2SoC
+25 0C

100
1.08
2.8

100
1.08
2.8

~.

4

4

pF

+25 0C
+25 0C
+25 0C
+250C

20
10

20
10

0.6
5

0.8
5

pF
pF
pF
pF

+250C

300

+250C

NOTES,

Full
Full
Full
Full

1. Voltage ratings apply whan voltages at all other pin. ere
within their normal operating"ranges.
2. Derate l'.1mW/oC above 750C
3. VOUT-±10V, 10ur=-lmA.

500
1000

350

L
L
L
H
H
H
H

300

500

300

X

L

4

L
L

5
6

L
L
H

7
8
NONE

"'

~.

os
1000

5
0.1
0.3
0.3

0.5
1
1

ns
ns
ns

mW
0.5
1
1

mA
mA
mA

4. To drive from DTlITTL circuits, lkSl pull-up resiston
to +5.0V supply are recommended.
5. Time measured to 90% of final output level;
VOUT:: -S.OV to+5.0V. Digital Inputs = OV to +4.0Y.

·'00% Tested for Dash 8 at +250C and +1250C Only.

DIE CHARACTERISTICS
Transistor Count
Die Size
Thermal Constants

X

L
L
L

"ON"
CHANNEL
I
2
3

EN

n.

1000

1000

5
0.1
0.3
0.3

ADDRESS
AI
An
L
L
H
L
H
L
H
H
L
L
L
H
H
L
H
H

100a

500
1000

300

Full
POWER REQUIREMENTS
Po, Power Dissipation
*1+. Currant Pin 14
*1"1 Current Pin 15
*Il, Current Pin 2

A2

X

Full
tOFFIEN1. Enable delay 10FF)

HI-1818A

L

SWITCHING CHARACTERISTltS

TS. Access Time (Note 51

TRUTH TABLES

210
68.5 x 104 mils
8ja
8jc

Tie Substrate to:
Process:

4-69

I

90 0 cIW For Ceramic DIP
36 0 CIW
-VSupply
CMDS- 01

HI-1828A
ADDRESS
Al
An EN
L
L
L
L
H
L
H
L
L
H
H
L
X
H
X

"ON"
CHANNELS
I and 5
2 and 6
3 and 1
4 and 8
NONE

PERFORMANCE CHARACTERISTICS
ON CHANNEL CURRENT
vs. VOLTAGE

ON RESISTANCE vs.
ANALOG SIGNAL LEVEL

---

1 rnA

v

IN

OUT
Test Circuit
+60

Test Circuit
350

:I:

o

~ 250

u

z

200

enw

-

~ 150

o

100
-10

-8

-6

--

-4
-2
+2
+4
VI- SIGNAL LEVEL IVOLTS)

-55°C
+40

0

~ +20

:::?'

w

U

~

:.--

-20

~

.Th ?
~
+125

§:
'" -40

-8

-6

+10

~

+8

PROBE
r.--..,

4V

-5VOC

I

I

I

-:-:pOV

"J

I

rlrE

L

'

===

:;:10V

EN

~

4V

-1

L

ov---1

UT

±lOV-=-

-

r---r

+4V

!

'S(OFF) A

-

+6

+4

A 'O'OFFI

-=~

J

+2

ACCESS TIME

OUT

±1QV

-2

ON LEAKAGE

N

: ..

-4

VOLTAGE ACROSS SWITCH

LEAKAGE CURRENTS vs. TEMPERATURE
OFF LEAKAGE

~

+25OC

-60
-10
+8

+25OC

,/

'"

''"z"
'J:"

55~

+6

+125 C
~ W~

:E,

--~
~

'" 300
:E

~

«

*Two measurements per channel:
+10V/-l0V and -10V/+l0V.
(Two measurements per device for 'OIOFFI:
+10V/-l0V and -10V/+l0Vl.

4V

lDOnA
~

r

I

Ari INP'uT
2V1DIV. -

50%

././

,---

/ //

loION)=IOIOFFJ
HI-letBA
HI-1828A

lDnA

+5V

\V./ /

lnA

./
l00pA

90%

IS(OFF)~

// V

TA

(HI-1818A/1828A)

+

OUTPUT
Y/DIV.
-5V

100ns/DIV.
lOpA

25

50

100

75

TEMPERATURE-

125

oc

4-70

I

I

-

+10

SCHEMA TIC DIAGRAM
c(

ADDRESS INPUT BUFFER

CD
N
CD

,....

C
CD

+-+-+---+A
ALL N-CHANNEL
BODIESTO VALL P-CHANNEL
BODIESTO V+
UNLESS OTHERWISE
INDICATED.

4---f-+-+---+A

DECODER GATE

r--------,

i

i,

A2 OR A2

TO!
P CHANNEL

AI OR AI

SW!
PIS TO

I

N CHANNEL
NIS SW

!

I

I'

~~WIT~~~~_ ~

A2 OR A2 NOT USED
FOR HI-1828A

MULTIPLEX SWITCH
FROM DECODE

-V

FROM DECODE

4-71

,....
CD
,....

I

HY·9595/98

mHARRIS
ADVANCE INFORMATION

Programmable Gain Amplifier
with Multiplexed Inputs

Features

HY·9595 Features

• 12 Bit Accuracy

.8 Differential Input Channels

• Digital Controlled Gain and Input Channel Se,lection
• Intemal Latches for Channel and Gain Select, Bits
• Non-Inverting Amplifier GaIns ..... +1. +2. +4 and +8
• Gain Error ............•.................... 0.01%
• Channel-to-Channel Settling Time

max ...... ;.13pS
typ ......... 9pS

continuous ... Vsupply + 20V
transient .......... 2000V

• Input o-voJtage Protaction

HY·9596
• 16 Pseudo-DifferentieVSingle Ended Input
Channels

Applications

• Low Power Dissipation .................... 190mW
• Process Control Systems
• Status Monitoring Systems

• Amplifier Offsat Adjustment
• Compact 32 Pin DIP
• Compatible with 12 BitA/D Converters (HI-574A. 674A.
ate.) and Sampling A/D Converters (HY-9574. 9674.
9474. ate.)
• Available Temperature Ranges:
Commercial (-5) ..... _............... O°C to +75°C
Industrial (-9) .................... -40°C to +85°C
Military (-2) ..................... -55°C to +125°C

• Multi-Channel High Reliability Data Acquisition
Systems
• Industrial and Scientific Instrumentation
• Military Systems

Functional Diagram
HY-9595

{

"",

PROGRAMMA8LE

GAIN

,B(291

ANALOG
INPUTS

2A(61
28(28)
:::

~A(l:"

HY-9596

'{ .:!
::;:::
::::~:

ANALOG

>---0(18)
VOUT

,,,un

:

.

.

IN16(231
IN161Z2)

8B(22)

SENSE (141

4-72

9----------+_'

PROGRAMMABLE
GAIN

> __

~('81

V OUT

HY-9595/9596
De$cription
The HY-9595/9596 is a high performance Programmable
Gain Amplifierwith multiplexed inputs. The amplifiergain and
the input channel are selected digitally, and can be controlled
through hardware or software. Internal registers latch the
digital control bits, eliminating the need for external latches.
This part connects multiple analog inputs to data acquisition
systems.
The HY-9595 provides eight (8) pairs of multiplexed differential inputs.
The HY-9596 provides sixteen (16) single-ended (pseudo differential) multiplexed inputs.
Multiplexer Section
The analog Input Multiplexer includes active input overvoltage
protection circuitry, and can withstand a continuous input up
to 20 volts greaterthan either supply. This feature protects the
multiplexer against damage when supplies are off, but input
signals are present -- essential in systems where the analog
inputs originate outside the equipment. Equally important,
the HY-9595/9596 can withstand brief input transient spikes
of over 4000 volts, which would otherwise require complex
external protection.
An overvoltage condition on a deselected input does not
cause distortion on the selected input channel.

Programmable Gain Amplifier Section
The Programmable Gain Amplifier (PGA) provides non-inverting
gains under digital control; the gains are +1, +2, +4 and +8.
A different gain can be se'fected for each input channel. A fully
differential amplifier is used in both versions, so the pseudodifferential inputs on the HY-9596 are referenced to the
SENSE input, rather than to the supply ground.
The resistor network is laser trimmed to minimize gain
errors.
Input Voltage Ranges
The HY-9595/9596 accepts the standard ±1 OV input range.
Care must be taken in the system design to avoid overdriving
the amplifier, which could result in output signal distortion.
Temperature Grades
The HY-9595/9596 will be available initially in Commercial
(O°C to +75°C) and Industrial (-40°C to +85°C) temperature
grades. A grade is also being developed for the military
temperature range (-55°C to +125°C).
Power Requirements
Power requirements are +5V and ±15V, with typical dissipation
of 190mW.
Package

The Input Multiplexer is guaranteed to break-before-make, so
two channels are never shorted together.
Multiplexer Expansion ports are included so external
multiplexers can be added, if required.

All models are packaged in a 32-pin DIP with 600 mil row
centers. Plastic packages are used for Commercial and Industrial
grades. Ceramic hermetic packages will be used for the
Military temperature grade.

Package

Pinouts

1.700 MAX

AZ
N/C
GNO
IA
2A
4A
5A

8A
+V
MUX EXP A
MUX EXP 8
VREF lOW
+5V lOGIC

HY-9595

HY-9596

TOP VIEW

TOP VIEW

AI
AO
EN
18
Z8
3B
48
58
68
)8
88
·V
Go
GI
V OUT

AZ
A3
GNO
INI
INZ
IN3
IN4
IN5
IN6
IN)
INB
+V
MUX EXP
SENSE
VREF lOW

Wi!

+5VlOGIC

T
AI
Ao
EN
INg
INIO
INIl
INIZ
INI3
INI4
INI5
INI6
·V

Go
GI
V OUT

I

..160

MIN

...L

1.500±.010

C· "=J
lOM

R
I--~ l
i

4-73

.100 MAX

-i

Product Index

5-2

Ordering Information

5;'3

Standard Products
Packaging Availability

5-3

~

Q~

'a:
Ow
'I>

«2
Q

Selection Guide

5-4

Product Information

5-5

ABSOLUTE MAXIMUMRATINGS
As. with all semiconductors, stresses listed under "Absolute Maximum Ratings"
may be applied to devices (one at a time) without resulting in permanent damage.
This is a stress rating only. Exposure to absolute maximum rating conditions for
ex.tended periods may affect device reliability. The conditions listed under
"Electrical Characteristics" are the only conditions recommended for
satisfactory operation.

5-1

t.)

Product Index
Page

Hl c 574A

Fast. Complete 12-Bit AID Converter with Microprocessor Interface ............................... 5-5

HI-674A

Fast. Complete 12-Bit AID Converter with Microprocessor Interface ............................... 5-16

HI-774

Fast. Complete 12-Bit AID Converter with Microprocessor Interface ............................... 5-27

HI-774A

Very Fast. Complete 12-Bit AID Converter with Microprocessor Interface ...................... 5-38

HY-9574

Sampling 12-Bit AID Converter with 8/16-Bit Microprocessor Interface .......................... 5-51

HY-9674

Sampling 12-Bit AID Converter with 8/16-Bit Microprocessor Interface .......................... 5-68

HY-94741 1742

Low Power Sampling 12-Bit AID Converter with 8/16-Bit Microprocessor Interface ..... 5-84

HY-9712

Complete 12-Bit Data Acquisition Subsystem ..................................................................... 5-86

5-2

Ordering Information
HARRIS PRODUCT CODE EXAMPLE

H

T

5

574A -

-1

-r

PART NUMBER

T

TEMPERATURE:
OOc to +2000 C

*

·550 C to +1250 C
-250C to +85o C

OOc to +750 C

6
M V Y -

-

Interface
Memory
AnaloQ, High Voltage
Analog Hybrids

Oash-7 High Reliability Commercial
Product. OOC to +750 C

9

PACKAGE:-----....
Dual-in-Line. Ceramic
Metal Can
Dual-In line, Plastic

4

-

100% +250 C Probe (Dice Only)

-

Dash-8 Program
HA2-252

HY-9574

X

X

X

HY-9674

X

X

X

TEMPERATURE

SURFACE MOUNT
LCC

CERAMIC
DIP

PACKAGE

-9

DEVICE NUMBER
ANALOG TO DIGITAL

(.)

c(

0

c(

*Available as MIL-STD-883 only.

5-3

· Selection Guide
AID CONVERTERS
Temp. Range
_55°C

Part
Number
HI-574AJD
HI-574AKD
HI-574ALD
HI-574ASD
HI-574ATD
HI-574AUD
HI-674AJD
HI-674AKD
HI-674ALD
HI-674ASD
HI-674ATD
HI-674AUD

Resolution
Bits

O·C

I.
I.
• 12SOC +75~C

I

·40oC
I•
+8S OC

Package

NonLineartty
Max.
250 C (LSB)

X

28 Pin
Cerdip

±1
±112
±1/2
±1
±1/2
±1/2

II-Bits
12-Bits
. 12-Bits
II-Bits
12-Bits
12-Bits

±45
±25
±10
±50
±25
±12.5

28 Pin
Cerdip

±1
+1/2
±1/2
±1
±1/2
±1/2

II-Bits
12-Bits
12-Bits
II-Bits
12-Bits
12-Bits

±45
±25
±10
±50
±25
±12.5

±1
±1/2
±1/2

II-Bits
12-Bits
12-Bits

±45
±25
±10

±,.
±1/2
±1/2
±1
±1/2
±1/2

It-Bits
12-Bits
12-Bits
II-Bits
12-Bits
12-Bits

±45
±25
±10
±50
±25
±12.5

X

±l
±1/2
±1/2
±1
±1

II-Bits
12-Bits
12-Bit$
II-Bits
12-Bits

±45
±25
±10
±50
±25

X
X

±1
±1/2
±1/2
±1
:t1/2

II-Bits
12-Bits
12-Bits
II-Bits
12-Bits

±45
±25
±10
±50
±25

X
X

12
X
X
X

X
X
X

12
X

x
X

HI-774J
HI-774K
HI-774L

x

HI-774AJD
HI-774AKD
HI-774ALD
HI-774ASD
HI-774ATD
HI-774AUD

X

o Ilferentlal
Gain Drift
No'n-Llnearity'
ppm80 C
Max. 25 0 C
Max. Fun Temp

28 Pin
Cerdip

X

X

Conversion Speed (ps)
(Internal Clock)
12-Blt8
8-Blt8

Page

20

13

5-5

12

8

5-16

8.5

6.4

5-27

7

4.5

5-38

20

13

5-51

12

8

5-68

\

W

U
Z

e
e

>
Q

>a:

e
z
i

HY3-9574J
HY3-9574K
HY3-9574L
HY3-9574A
HY3-9574B
HY3-9674J
HY3-9674K
HY3-9674L
HY3-9674A
HY3-9674B

X
X

12

28 Pin
Cerdip

X
X
X
X

12

32 Pin
Plastic

X

X
X
\

12

32 Pin
Plastic

X

X

HY-94741
HY-94742

12

X

X

X

.28Pin
Plastic or
Ceramic

±1/2

12-8its'

±45

20

13

5-84

HY-9712

12

X

X

X

N/A

±1/2

12-Bits

TBD

TBD

TBD

5-86

:::i

w

a:

IL

I.

X

*Maximum' resolution with no missing codes guaranteed.

)

5-4

.mJ HA.R.RIS

HI·574A
Fast, Complete 12-Bit AID Converter
with Microprocessor Interface

FEATURES

DESCRIPTION

•
•
•
•
•
•
•

COMPLETE 12 BIT AID CDNVERTER WITt! REFERENCE AND CLOCK.
FULL 8-, 12- or 16- BIT MICRDPRDCESSOR.BUS INTERFACE.
150 nS BUS ACCESS TIME
NO MISSING CODES OVER TEMPERATURE
MINIMAL SETUP TIME FOR CONTROL SIGNALS
25 ps MAXIMUM ,CONVERSION TIME
LOW NOISE, VIA CURRENT-MODE SIGNAL TRANSMISSION
BETWEEN CHIPS
• BYTE ENABLE/SHORT CYCLE (A. INPUT)
• GUARANTEES BREAK- BEFORE- MAKE ACTION, ELIMINATING
BUS CONTENTION DURING READ OPERATION. LATCHED BY THE
START CONVERT INPUT (TO SET THE CONVERSION LENGTH).

The HI-574A is a complete 12 bit Analog-to-Digital Converter,
including a +10V reference, clock, three-state outputs and a digital
interface for microprocessor control. Successiveapproxjmation
conversion is performed by two monolithic dice housed in a 28
pin package. The bipolar analog die features the Harris 0 ielectric
Isolation protess, which provides enhanced AC performance and
freedom from latch-up.
Custom design of each IC (Bipolar Analog and CMOS Digital) has
yielded improved performance over existing versions of this converter. The voltage comparator features high PSR R plus a high
speed current-mode latch, and provides precise decisions down to
0.1 LSB of input overdrive. More than 2X reduction in noise has
been achieved by using current instead of voltage for transmission
of all signals between the analog and digital ICli. Also, the clock os- .
cillator is current-controlled for excellentstability over temperature.
The oscil.lator is trimmed for a nominal conversion time of 20±lps.

• IMPROVED SECOND SOURCE FOR AD574A AND HS574
• ± 12V TO ± 15V OPERATION

The H1-574A offers standard unipolar and bipolar input ranges,
laser trimmed for specified linearity, gain and offset accuracy. The
buried zener reference circuit is trimmed for minimum temperature
coefficient.

APPUCATIONS
• MILITARY AND INDUSTRIAL DATA ACQUISITION SYSTEMS
• ELECTRONIC TEST AND SCIENTIFIC INSTRUMENTATION.
• PROCESS CONTROL SYSTEMS.

Power requirements are +5V and ±12V to ~15V, with typical dissipation of 385mW at±12V.Three electrical grades each are offered for
the c.ommercial and military temperature ranges. All models are
packaged in a 28 pin Side-Brazed DIP. For additional Hi-Rei
screening including 160 hour burn-in specify the "-8" suffix.

PINOUT
TOP VIEW
+5V SUPPLY VLOGIC
DATA MODE SEL 121ii
CHIP SEL, CS
BYTE AOOR/SHORT
CYCLE,AO
REA~/CONVERT, R/C
CHIP ENABLE, CE
+15V SUPPL Y, VCC
+10V REF, REF OUT
ANALOG
COMMON,AC
REF INPUT, REF IN

STATUS, STS
OBll MSB
OB10

HI-574A

OB9
DBB
DB7
OB6
DB5
DB4
DB3
DB2

-15V SUPPLY, VEE
BIPDLAR OFFSET
BIP OFF
10VINPUT

DIGITAL
DATA
OUTPUTS

DBl
DBO LSB

20VINPUT

DIG COMMON, DC

CAUTION: These devices are sensitive to electronic discharge. Proper I.C. handling procedures should be followed.

5-5

~.

9~
Ow

'i'>

-"-6-+-I...._-r--~l---.J
1 - .. L

t

J

.f-'---1I---'--Q Y,o."
.f-~-+_I:.:S-() DIGITAL

'";:======---1____..L_______....::...,.."

OSCILLATOR

~

~---r-I---

POWER-UP RESET

12 BITS

28

ANALOG CHIP

~----~------~--------~ST~RO~B~E------~-r--

...

12 BITS

........... /
10

0_--+----------+--"'\.
,.. 8

~M_

I
+10Y
REF.

I

OAC

I
10K

~_

l'

:
I
SK

L

S"

SK ,. 10K'
~
SK

I

12

14
(

ANALOG
COMMON

BIP.
OFF

'("NIBBLE" IS A 4 BIT DIGITAL WORD.)

5-6

COMMON

Ht---c......~----+

STATUS

STROBE
CLOCK

)0----+

EOC13

FIGURE 4. HI-574A CONTROL LOGIC

5-12

RESET

c(
~

....

"Stand-Alone Operation"

U')

-

The simplest control int~rface calls for a s.i!!gle control line connected
to RlTI. Also, CE and 12/8 are wired high, CS and All are wired low, and
the output data appears in words of 12 bits each.

I

The RIC signal may have any duty cycle within (and including) the Qldremes
shown in Figures 5 and 6. In general, data may be read when RIC is high
unless STS is also high, indicating a conversion is in progress. liming
parameters particular to this mode of operation are listed below under
"Stand·Alone Mode liming."

m

M,-----..~
--=-ti ~DR
F3~
=)

OBll·0BO

(

}

DAm VALID

FIGURE 5. LOW PULSE FOR RIC - OUTPUTS ENABLED AFTER CONVERSION

RlC-R-ID,--""t--,-

~ I~ ~_I~C-b-

m
DBll.0BO

HIGH-Z

~

HIGH-Z

-------------

------<~)-.

FIGURE 6. HIGH PULSE FOR RIC-OUTPUTS ENABLED WHILE RIC
HIGH, OTHERWISE HIGH-Z

STAND-ALONE MODE TIMING
Symbol Parameter
Min
Low RIC Pulse Width
IHRL
50
tos
STS Delay from RIC
IHOR
Data Valid After RIC Low
25
STS Del~ After Data Valid 300
IHs
High RIC Pulse Width
IHRH
150
1o0R
Data Access Ti me

5-13

lVp

Max

200
500

1000
150

Units
ns
ns
ns
ns
ns
ns

Conversion Length
A Convert Start transition (see Table 1) latches the state of ~, which
determines whether the conversion continues for 12 bits (~ low) or stops
with 8 bits (~ high). If all12 bits are read following an 8 bit conversion, the
three LSB's will read zero and 0 B3 will read ONE.~ is latched because it is
also involved in enabling the output buffers (see "Reading the Output Data").
No other control inputs are latched.
CE
0
X

....
1
1
1
1
1
1
1

CS
X
1
0
0

+
+
0
0
0
0
0

RIC
X
X
0
0
0
0

••
1
1
1

12/8
X
X
X
X
X
X
X
X
1
0
0

Au
X
X
0

1
0

1
0

1
X
0

1

buffers remain in a high impedance state and data cannot be read.
Also, an additional Start Convert will not reset the converter or
reinitiate a conversion while STS is high. (However, if Au changes
state after a conversion begins, an additional Start Convert signal will
latch the new state of Au, possibly causing a wrong cycle length (8 vs
12 bits) for that conversion).
Reading the Output Data
The output data buffers remain in a high impedance state until four
conditions are met: RIC high, STS low, CE high and CS low. At that
time, data lines become active according to the state of inputs 12/8
and Au. Tim,1g constraints are illustrated in Figure 8.

OPERATION
None
None
Initiate 12 bit conversion
Initiate 8 bit conversion
Initiate 12 bit conversion
Initiate 8 bit conversion
Initiate 12 bit conversion
Initiate 8 bit conversion
Enable 12 bit Output
Enable 8 MSB's Only
Enable 4 LSB's Plus 4
Traili ng Zeroes

The 12/8 input will be tied high or low in mjlst applications, though it
is fully TTL/CMOS-compatible. With 12/8 high, all 12 output lines
become active simultaneously, for interface to a 12 or 16 bit data bus .
The Au input is ignored .
With 12/Slow, the output is organized in two 8 bit bytes, selected one at atime
by Au. This allows an 8 bit data bus to be connected as shown in Figure 9. Au is
usually tied to the least significant bit of the address bus, for storing the
HI-S74A output in two consecutive memory locations. (With ~ low, the 8
MSB's only are enabled. With ~ high, 4 MSB's are disabled, bits 4through 7
are forced to zero, and the 4 LSB's are enabled). This two byte format is
considered "left justified data", for which a decimal (or binary!) point is
assumed to the left of byte 1:

TABLE 1
Truth Table for HI-574A Control Inputs.
C'1nversion Start
A conversion may be initiated as shown in Table 1 by a logic transition
on any of three inputs: CE, CS or Ric. The last of the three to reach
the correct state starts the conversion, so one, two or all three may be
dynamically controlled. The nominal delay from each is the same,
and if necessary, all three may change state simultaneously. To
assure that a particular input controls the start of conversion, the
other two should be set up at least SOnS earlier, however. See the
HI-574A Timing Specifications, Convert mode.

BYTE 1

BYTE 2

.1 X X X X X X X

I

xl I X

X X X 0 0 0 01

MSB

I

LSB

Further, Au may be toggled at any time without damage to the
converter. Break-before-make action is guaranteed between the two
data bytes, which assures that the outputs strapped together in
Figure 9 will never be enabled at the same time.

This variety of HI-574A control modes allows a simple interface in
most system applications. The Convert Start timing relationships are
illustrated in Figure 7.

A read operation usually begins after the conversion is complete and
STS is low. For earliest access to the data however, the read should
begin no later than (too + tHS) before STS goes low. See Figure 8.

The output signal STS indicates status of the converter by going high
only while a conversion is in progress. While STS is high, the output

CE

----....J'I--___ ." ___-'1.-----

..

'1

_____

...
".

...

Is..

STS
STS

-----+----'1
"" 1 - - - - 1 - - - - - - - - 1

0811-D80 _ _ _ _ _+-_~HIG:;:H..:IM::..:PE;::DA.::.;NC::.E_ _ _ _ _ _ __

bo.

D811·DBO

-----~~:!!:~~~:D...,.AN-CE---~
0,

FIGURE 7. CONVERT START TIMING

FIGURE 8. READ CYCLE TIMING

5-14

II(
"1;1'

H/-574A TIMING SPECIFICATIONS

......

It)

+25 0 C unless otherwise specified

Symbol

Parameter

I

Min

Typ

Max

Units

100
30
20
20
0
20
0
20
20
13

200

50
50
50
50
50
0
50
15
10

nS
nS
nS
nS
nS
nS
nS
nS
,."S
,."S

75
35
100
0
0
25
0
0
25
500

150

~

Convert Mode
tosc
tHEC
tssc
tHSC
tSRC
tHRC
tSAC
tHAC
te

STS Delay from CE
CE Pulse width
Q§ to CE Setup
CS_Low during CE High
RIC to CE Setup
RIC Low during CE high
Ao to CE Setup
Ao Valid during CE high
Conversion time, 12 bit cycle T min to T max
8 bit cycle T min to T max

25
17

Read Mode
too
tHO
tHL
tsSR
tSRR
tSAR
tHSR
tHRR
tHAR
tHS

Access time from CE
Data Valid ~.fter CE low
Q.!!tput float delay
CSJo CE setup
RIC to CE setup
&. to CE setup
CS valid after CE low
RIC hig h after CE low
Ao valid after CE low
STS delay after data valid

25
50
0
50
0
0
50
300

150

1000

en

Note: Time Is measured from 50% level of digital transitions. tested with a 1 OpF and 2KS1load.

I

)

'-'"
2

.,r-

1218

0::

9~
00::

\

ADDRESS BUS

A.
~r

STS

DBll (MSB)

+r~

«2
0

(.)

2B

~

27
26
25

It.,

24
OAllI
BUS

23
22

HI·574A

21
20
19
lB
17

OBO (LSB)

DIG.

16
15

COM.

J:,

FIGURE 9 INTERFACE TO AN 8 BIT DATA BUS
DIE CHARACTERISTICS
Transistor Count
Die Size:

Analog
Digital

1117
204 x 104 mils
158 x 84 mils

Thermal Constants;
Process:

48'C/W
15'C/W
Bipolar - DI and
CMOS-JI

5-15

nS
nS
nS
nS
nS
nS
nS
nS
nS
nS

m~RIS

HI·674A
12/l-s, Complete 12-Bit AID Converter

with Microprocessor Interface
FEATURES

DESCRIPTION

• COMPLETE 12 BIT A/D CONVERTER WITH REFERENCE AND CLOCK.
• FULL 8', 12- or 16- BIT MICROPROCESSOR BUS INTERFACE.
'150 nS BUS ACCESS TIME
• NO MISSING CODES OVER TEMPERATURE
• MINIMAL SETUP TIME FOR CONTROL SIGNALS
~ 15 tiS MAXIMUM CONVERSION TIME
• LOW NOISE, VIA CURRENT-MODE SIGNAL TRANSMISSION
BETWEEN CHIPS
• BYTE ENABLE/SHORT CYCLE (AD INPUT)
• GUARANTEES BREAK-BEFORE' MAKE ACTION, ELIMINATING
BUS CONTENTION DURING READ OPERATION. LATCHED BY THE
START CONVERT INPUT (TO SET THE CONVERSION LENGTH).
• FASTER VERSION OF THE HI-574A.
• SAME PIN·OUTS AS HI-574A.
•± 12V TO ± 15V OPERATION

The HI-674A is a complete 12 bit Analog-to-Digital Converter,
including a +10V reference, clock, three-state outputs and a digital
interface for microprocessor control. Successive approximation
conversion is performed by two monolithic dice housed in a 28-pin
package. The bipolar analog die features the Harris Dielectric
Isolation process, which provides enhanced AC performance and
freedom from latch-up.
Custom design of each IC (bipolar analog and CMOS digital) has
yielded improved performance over existing versions of this
converter. The voltage comparator features high PSRR plus a high
speed current-mode latch, and provides precise decisions down to
0.1 LSB of input overdrive. More than 2x reduction in noise has
been achieved by using current instead of voltage for transmission
of all signals between the analog and digital IC's. Also, the clock
oscillator is current-controlled for excellent stability over temperature. The oscillator is trimmed for a nominal conversion time
of 12±1 /.ls_
The H1·674A offers standard unipolar and bipolar input ranges,
laser trimmed for specified linearity, gain and offset accuracy.
The buried zener reference circuit is trimmed for minimum temperature coefficient.

APPUCATIONS
• MIlITARY AND INDUSTRIAL DATA ACQUISITION SYSTEMS
• ELECTRONIC TEST AND SCIENTIFIC INSTRUMENTATION.
• PROCESS CONTROL SYSTEMS.

Power requirements are +5V and ±12V to ±15V, with typical
dissipation of 385mW at ±12V. Three electrical grades each are
offered for the commercial and military temperature ranges. All
models are packaged in a 28 pin Side-Brazed DIP. For additional
Hi-Rei screening including 160 hour burn-in specify the "-8" suffix.

PINOUT
TOP VIEW

+5V SUPPL Y VLOGIC ~ 1

28 ~ STATUS, STS

DATA MOOE SEL 12~( 2
CHIP SEL, cli [ 3

27 ~ OBll MSB
26 ] 0810

BYTE ADDRISHORT r 4
CYCLE, AII.~
READ/CONVERT, R/eC 5

25 ' DB9

CHIP ENABLE, CE

~

+15V SUPPL Y, VCC [
+10V REF, REF OUT[
ANALOG r
COMMON, AC ~
REF INPUT, REF IN [

24

6
7
8

23
HI-674A

=
~ DB8

J
J

DB7

22 OB6
21 ] DB5

=

DIGITAL
DATA

,

9
10

20 DB4
19] DB3

-15V SUPPLY, VEE [ 11
BIPOLAR OFFSET [ 12
BIP OFF
10V INPUT [ 13

18
17
16

OUTPUTS

POB2

h DBl

,-J
~ DBO LSB

....._-----'

20VINPUT [14

15]DIGCOMMON,DC

CAUTION: These devices are sensitive to electronic discharge. Proper LC_ handling procedures should be followed.

5-16

HI-674A BLOCK DIAGRAM

BIT OUTPUTS
(

~--------~~----------~
MSB
lSB)

o

(

27

1218 "

CS "

~c:::'

2
3
4

5
CE :::. 6

26

25

24

23

NIBBLE· A
CONTROL
LOGIC

22

21

20

(

q

19

18

16

NIBBLE· C

NIBBLE· B

f--"\

q
17

THREE-STATE BUFFERS AND CONTROL

~~------------~~~~------------~

1

.f-'---t--::-Q
f-----l..;:::=====:::...-L
J __..L_____-=f-~.,-+-'.::..-o
.....-...,I-~
- DIGITAL
POWER-UP RESET

12 BITS

15

,

OSCILLATOR

COMMON

~

'"----r-L--~

28

Hr---CO

SAR

L------r------r--------~ST=R~OB=E~------li--~

DIGITAL CHIP

ANALOG CHIP

1281TS

... "-...../
" 10
V'" IN ~o--+------+-""\.

I
I

10K

"
V",OUT

VlOGIC

8

,L,

~

I

;lrl

'

OAC

I

1

5K
5K

> 10K

2.SK
5K

L

9

12

14

13

I)

1
ANALOG
COMMON

81P.
OFF

·("NIBBLE" IS A 4 BIT DIGITAL WORD.)

5-17

20V
INPUT

10V
INPUT

STS

SPECIFICATIONS
(Typical @ +25°C with Vcc = +15Vor +12V, VLOGIC = +5V, VEE = -15Vor -12V unless otherwise specified)

DC AND TRANSFER ACCURACY SPECIFICATIONS
-MODEL

HI-674AL

12

HI-674AK
+75
12

12

°C
Bits

±1
±1

±1/2
±1/2

±1/2
±112

LSB
LSB

11
11

12
12

12
12

Bits
Bits

±2

±2

±2

LSB

±10

+4

+4

LSB

0.3

0.3

0.3

% of F.S.

0.5
0.22

0.4
0.12

0.35
0.05

% of F.S.
% of F.S.

±2
(10)
±2
(10)
±9

±1
(5)
±1
(5)
±5

(45)

(25)

±1
(5)
±1
(5)
±2
(10)

LSB
(ppmrC)
LSB
(ppmrC)
LSB
(ppm/OC)

±2
±1/2
±2

±1
±1/2
±1

±1
±1/2
±1

LSB
LSB
LSB

HI-674AJ

Temperature Range

oTO

Resolution (max)
Linearity Error
25°C (max)
O°C to + 75°C (max)
Differential Linearity Error
(Maximum resolution for which no missing codes is guaranteed)
25°C
Tmin to Tmax
Unipolar Offset (max)
(Adjustable to zero)
Bipolar Offset (max)
(Adjustable to zero)
Full Scale Calibration Error
25°C (max), with fixed 50 n resistor from
REF OUT to REF IN (Adjustable to zero)
Tmin to Tmax
(No adjustment at + 25°C)
(With adjustment to zero at + 25°C)
Temperature Coefficients
Guaranteed max change, Tm" to Tmax (Using internal reference)
Unipolar Offset
Bipolar Offset
Full Scale Calibration
Power Supply Rejection
Max change in Full Scale Calibration
+ 13.5V_----.. smus

STROBE
CLOCK

}o----+

EOC13

FIGURE 4. HI·674A CONTROL LOGIC

5-23

RESET

,...

~

CD
I

"Stand-Alone Operation"
The ~mplest control int~rface calls for.a s.i!lgle control line connected
to RIC. Also, CE and 1218 are wired high, CSand Ao are wired low, and
the output data appears in words of 12 bits each.
The RICsignal may have any duty cycle within (and including) the extremes
shown in Figures 5 and 6. In general, data may be read when RIC is high
unless STS is also high, indicating a conversion is in progress. Timing
parameters particular to this mode of operation are listed below under
"Stand-Alone Mode Timing."

RiC

dFj

STS
0811·080

~..

DATA
VALID

)

i

J<

Ie

IH,

DAllIVAUO

FIGURE 5. LOW PULSE FOR RIC - OUTPUTS ENABLED AFTER CONVERSION

RiC-O'----Io,-~---STS_II
__1 -----L
~ ~
r
~-~
r---le

0811·080

r=:::\

HIGH·Z
------<~)-.

HIGH·Z

------"-...;.;.-------

FIGURE 6. HIGH PULSE FOR RIC-OUTPUTS ENABLED WHILE RIC
HIGH, OTHERWISE HIGH-Z

STAND-ALONE MODE TIMING
Symbol
IHRL
tos
tHOR
iHS
tHRH
tOOR

Parameter
Min
Low RIC Pulse Width
50
STS Delay from RI.9
Data Valid After RIC Low
25
STS Del!!y After Data Valid 100
High RIC Pulse Width
150
Data Access Time

5-24

Typ

Max
200

300

600
150

Units
ns
ns
ns
ns
ns
ns

c:(

Conversion Length
A Convert Start transition (see Table 1) latches the state of Ao, which
determines whether the conversion continues for 12 bits (Ao low) or stops
with 8 bits (Ao high). If all 12 bits are read following an 8 bit conversion, the
three LSB's will read zero and DB3 will read ONE. Ao is latched because it is
also involved in enabling the output buffers (see "Reading the Output Data").
No other control inputs are latched.
CE

0

...

X

1
1
1
1
1
1
1

CS
X
1

0
0

+
+
0
0
0
0
0

RIC 12/8
X
X
X
X

0
0
0

0

t
t

1
1
1

X
X
X
X
X
X
1
0
0

Au
X
X
0
1

0

1
0
1
X
0
1

OPERATION
None
None
Initiate 12 bit conversion
Initiate 8 bit conversion
Initiate 12 bit conversion
Initiate 8 bit conversion
Initiate 12 bit conversion
Initiate 8 bit conversion
Enable 12 bit Output
Enable 8 MSB's Only
Enable 4 LSB's Plus 4
Trailing Zeroes

buffers remain in a high impedance state and data cannot be read.
Also, an additional Start Convert will not reset the converter or
reinitiate a conversion while STS is high. (However, if A" changes
state after aconversion' begins, an additional Start Convert signal will
latch the new state of A" , possibly causing a wrong cycle length (8 vs
12 bits) for that conversion).
Read ing the Output Data
The output data buffertremain in a high impedance gate until four
conditions are met: RIC high, STS low, CE high and CS low. At that
time, data lines become active according to the state of inputs 1218
and Ao. Timing constraints are illustrated in Figure 8.
The 1218 input will be tied high or low in mjlst applications, though it
is fully TTUCMOS-compatible. With 12/8 high, all 12 output lines
become active simultaneously, for interiace to a 12 or 16 bit data bus.
The A" input is ignored.
With 121'iifow, the output is organized in two 8 bit bytes, selected one at atime
by Ao. This allows an 8 bit data bus to be connected as shown in Figure 9. Ao is
usually tied to the least significant bit of the address bus, for storing the
HI-674A output in two consecutive memory locations. (With Ao low, the 8
MSB's only are enabled. With Ao high, 4 MSB's are disabled, bits 4 through 7
are forced to zero, and the 4 LSB's are enabled). This two byte format is
considered "left justified data", for which a decimal (or binary!) pOint is
assumed to the left of byte 1:

TABLE 1
Truth Table for HI-674A Control Inputs.
Conversion Start
A conversion may be initiate!!...as sho,!n in Table 1 by a logiC transition
on any of three inputs: CE, CS or RIC. The last of the three to reach
the correct state starts the conversion, so ope, two or all three may be
dynamically controlled. The nominal delay from each is the same,
and if necessary, all three may change state simultaneously. To
assure that a particular input controls the start of conversion, the
other two should be set up at least 50nS earlier, however. See the
HI-674A Timing Specifications, Convert mode.
This variety of HI-674A control modes allows a simple interface in
most system applications. The Convert Start timing relationships are
illustrated in Figure 7.

BYTE 1

.1

X X X X X X X
I
MSB

BYTE 2

xl I X

X X X 0 0 0 01
r
LSB

Further, A. may be toggled at any time without damage to the
converter. Break-before-make action is guaranteed between the two
data bytes, which assures that the outputs strapped together in
Figure 9 will never be enabled at the same time.
A read operation usually begins after the conversion is complete and
STS is low. For earliest access to the data however, the read should
begin no later than (tDD + tHS) before STS goes low. See Figure 8.

The output signal STS indicates status olthe converter by going high
only while a conversion is in progress. While STS is high, the output

CE _ _ _ _-'1

Dl11.DIG _ _ _ _ _~-....;;HI;:;aH::..::IM::.p£::OAIICE=-------

Dl11-DBD

FIGURE 7. CONVERT START TIMING

-----!----;;;~;;GH~DAII.".,CE".---+--

FIGURE 8. READ CYCLE
TIMING
(

5-25

•....
-

CD
I

HI-674A TIMING SPECIFICATIONS
+25 0 Cunless otherwise specified

Symbol
Convert Mode
tosc
tHEC
tssc
tHsc
tsRC
tHRc
tsAC
tHAC

to
Read Mode
too
tHo
tHl
tsSR
tSRR
tsAR
tHSR
tHRR
tHAR
tHs

Parameter
STS Delay from CE
CE Pulse width
Q§ to CE Setup
CS Low during CE High
RlQ to CrSetup
RIC Low during CE high
A. to CE Setup
A. Valid during CE high
Conversion time. 12 bit cycle T min to T max
8 bit cycle T min to T max

Min

Typ

Max

Units

100
30
20
20
0
20
0
20
12
8

200

50
50
50
50
50
0
50
9

nS
nS
nS
nS
nS
nS
nS
nS

15
10

p,S
p,S

75
35
100
0
0
25
0
0
25
300

150

nS
nS
nS
nS
nS
nS
nS
nS
nS
nS

6

Access time from CE
Data Valid after CE low
Q!!tput float delay
CSJo CE setup
RIC to CE setu p
&. to CE setup
CS valid after CE low
RIC high after CE low
A. valid after CE low
STS delay after data valid

25
50
0
50
0
0
50
100

150

600

NOTE: Time is measured from 50% level of digital transitions. Tested with a 10pF and 2Kn load.

I

)

ADDRESS BUS

A.
~r

\,.J

2

-r
4

1218

STS
DBn (MSBI

~
27
26

A.

25
24

DAllI
BUS

23
22

HI-674A

21
20
19
18

17
DBO (lSBI
DIG.
COM.

16
15

-:lFIGURE 9. INTERFACE TO AN 8 BIT DATA BUS

Die Characteristics
Transistor Count
Die Size; Analog
Digital

1117
204 x 104 mils
158 x 84 mils

Thermal Constants; OJ.
Ojc

Process

5-26

48'CIW
15'CIW
Bipolar-DI
CMOS-JI

m

HI-774

HARRIS

ADVANCED

8.5J,ls, Complete 12-8it AID Converter
With Microprocessor Interface

Features

Description

• Complete 12 Bit A/D Converter With Reference and
Clock

The HI-774 is a complete 12 bit Analog-to-Digital Converter, including a +10V reference, clock, three-state outputs
and a digital interface for microprocessor control.
Successive approximation conversion is performed by
two monolithic dice housed in a 28-pin package. The
bipolar analog die features the Harris Dielectric Isolation
process, whch provides enhanced AC performance and
freedom from latch-up. The digital die features the Smart
SAR (SSART"), which includes a digital error correction
circuit.

• Digital Error Correction
• Full 8-, 12-, or 16-BII Microprocessor Bus Interface
• 150ns Buss Access Time
• No Missing Codes Over Temperature
• Minimal Setup Time For Control Signals
• 9t.ts Maximum Conversion Time Over Temperature
• Low Noise, Via Current-mode signal transmission
between chips
• Byte enable/short cycle (Ao Input)
~ Guarantees break-before-make action, eliminating
bus contention during read operation. Latched by
the Start Convert Input (To Set the Conversion
Length)
• Faster Version of the HI-574A and HI-674A
• Same Pin-Out as HI-574A and HI-674A

Custom design of each IC (bipolar and CMOS digital) has
yielded improved performance over existing versions of
this converter. The voltage comparator features high
PSRR plus a high speed current-mode latch, and provides
precise decisions down to 0.1 LSB of input overdrive.
More than 2X reduction in noise has been achieved by
using current instead of voltage for transmission of all signals between the analog and digital IC's. Also, the clock
oscillator is current controlled for excellent stability over
temperature. The oscillator is trimmed for a guaranteed
conversion time of 8.5 ± 0.5J.1s over temperature.
The HI-774 offers standard unipolar and bipolar input
ranges, laser trimmed for specified linearity, gain and offset accuracy. The low noise buried zener reference circuit
is trimmed for minimum temperature coefficient.

• ±12V to ±15V Operation

Applications

Power requirements are +5V and ±12V to ±15V, with
typical dissipation of 390mW at ±12V. Three electrical
grades are offered for the commercial temperature range.
All models are packaged in a 28 pin side-brazed, ceramic
DIP.

• Industrial Data Acquisition Systems
• Electronics Test and Scientific Instrumentation
• Process Control Systems

Pinout
TOP VIEW
+5V SUPPLY, VLOGIC
DATA MODE SELECT, 12/8

BYTE ADDR/SHORT CYCLE, AD
READ/CDNVERT, R/C
+12V/+15V SUPPLY, vec

7

+IOV REFERENCE OUT

8

HI-774

DIGITAL
DATA
OUTPUTS

REFERENCE INPUT
-12V/-15V SUPPLY, VEE
BIPDLAR OFFSET, BIP OFF
10V INPUT
20V INPUT

---....-----~

.5-27

DIGITAL CDMMON

---~----~-

HI-774 Block Diagram

BIT OUTPUTS
( ~~~------------~~-------------------~
MSB
LS8\

. 9 (
27

1218 ,...
CS "
A.
;::
RIC
CE

2
3
4
5
6

26

25

~

~

(

24

23

~
OSCILLATOR

I

21

20

(;>
19

~

(;>

(
18

17

lj

NIBBLE· C

NIBBLE· B

NIBB.LE· A
CONTROL
LOGIC

9

~

9

22

THREE-STATE BUFFERS AND CONTROL

f-----vI

'0BI~

1

.r.r-

-

VLOGIC

15 -""' DIGITAL
COMMON

28

~

STS

SSAR™
STROBE

DIGITAL CHIP
ANALOG CHIP

"

o .rLiOM~

12 BITS

'-...../
,... 10

V'" IN

V... OUT

-

• 10K

,... 8

I

DAC

~fL1~

-1
+10V
REF.

I
I
I

J

1

5K
10K

p-

14

12

9

r-

5K

6

:>

ANALOG
COMMON

BIP.
OFF

13
)

0

20V
10V
INPUT INPUT

'("·NIBBLE·· IS A 4 BIT DIGITAL WORD.)

Die Characteristics
Analog Die .......................................................... Bipolar, 01
Digital Die ............. ,............................................... CMOS, JI
Transistor Count ........................................................ -21 00

5-28

+

2.SK

7
11 -

Vee
VEE

Specifications HI-774
DC and Transfer Accuracy Specifications
(TA ~ +25 0 e with Vee ~ +15V or +12V, VLOGle ~ +5V, VEE ~ -15V or -12V unless otherwise specified)

MODEL

HI-774J

Temperature Range

HI-774L

UNITS

o to +75

oC

HI-774K

Resolution (max)

12

12

12

Bits

Linearity Error
25 0 C (max)
OoC to +75 0 C (max)

±1
±1

±1/2
±1/2

±1/2
±1/2

LSB
LSB

Differential Linearity Error
(Maximum resolution for which no missing codes is guaranteed)
25 0 C
Tmin to Tmax

11
11

12
'12

12
12

Bits
Bits

Unipolar Offset (max)
(Adjustable to zero)

±2

±2

±2

LSB

Bipolar Offset (max)
(Adjustable to zero)

±10

±4

±4

LSB

Full Scale Calibration Error
25 0 C (max), with fixed 50n resistor from
REF OUT to REF IN (Adjustable to zero)

0.3

0.3

0.3

% of F.S.

Tmin to Tmax
(No adjustmeat at +25 0 C)
(With adjustment to zero at +25 0 C)

0.5
0.22

0.4
0.12

0.35
0.05

% of F.S.
% of F.S.

Temperature Coefficients (see definitions)
Guaranteed max change, Tmin to Tmax (Using internal reference)
Unipolar Offset
Bipolar Offset
Full Scale Calibration

±2
±2
±9

±1
±1
±5

±1
±1
±2

LSB
LSB
LSB

±2
±1/2
±2

±1
±1/2
±1

±1
±1/2
±1

LSB
LSB
LSB

Power Supply Rejection
Max change in Full Scale Calibration
+13.5V
«z

8

Specifications HI-774
Digital Characteristics (All Models, Over Full Temperature Range)
MIN
Logic Inputs (CE, CS, RIC, A o , 12/8)
Logic "1"
Logic "0"
Current
Capacitance

TYP

+2.0V
-O.SV
0.1/1A
5pF

Logic Outputs (0811-080, STS)
Logic "0" (ISINK - 1.6mA)
Logic "1" (IS0URCE - SOO/1A)
Logic "1" (IS0URCE - 10/1A)

MAX

+5.5V
+0.8V
+5/1A

+O.4V
+2.4V
+4.5V

Leakage (High Z State, 0811-080 only)
Capacitance

±O.1/1A
5pF

t5/1A

HI-774 Timing Specifications (25 0 C unless otherwise specified.)
Into a load with RL " 2KO and CL = 10pF
SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

100
30
20
20
0
20
0
30
8.5
6.4

200

50
50
SO
50
50
0
SO
7
5.25

ns
ns
ns
ns
ns
ns
ns
ns
/1S
/1S

75
3S
70
0
0
25
0
0
25
90

150

Convert Mode
tDSC
tHEC
tssc
tHSC
tSRC
tHRC
tSAC
tHAC
tc

STS Delay from CE
CE Pulse width
CS to CE Setup
CS Low during CE High
RIC to CE Setup
RIC Low during CE High
Ao to CE Setup
Ao Valid during CE High
Conversion time,12 bit cycle T min to T max
8 bit cycle T min to T max

9
6.8

Read Mode
too
tHO
tHL
tSSR
tSRR
tSAR
tHSR
tHRR
tHAR
tHS

Access time from CE
Data Valid after CE low
Output float delay
CS to CE Setup
RIC to CE Setup
Ao to CE Setup
CS Valid after CE low
RIC high after CE low
Ao valid after CF. low
STS delay after data valid

25
50
0
50
0
0
50

150

300

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

NOTE: Time is measured from 50% level of digital transitions, except High Z output conditions which are measured at the 10% or 90% p'oint.

Absolute Maximum Ratings

(Specifications apply to all grades, except where noted)

VCC to Digital Common ................................ o to +16.5V
VEE to Digital Common .................................. 0 to -16.5V
VLOGIC to Digital Common .............................. 0 to +7V
Analog Common to Digital Common ....................... ±1V
Control Inputs (CE, CS, A o , 12/8, R/C) to
Digital Common ..................... -0.5V to VLOGIC +0.5V
Analog Inputs (REF IN, 81P OFF, 10VIN) to
Analog Common ............................................... ±16.SV
20VIN to Analog Common ....................................... ±24V

REF OUT ............................. Indefinite short to common
Momentary short to VCC
Chip Temperature .................................................. +175 0 C
Total Power Dissipation * ................................... 2125mW
Lead Temperature, Soldering .................. 300 0 C, 10 sec.
Storage Temperature ........................... -6S o C to +1500C
Thermal Resistance, ~A······.····.····.·· ... ·· ... ·....... ~o~W

• Derate 21.3mW/oC above 75 0 C

5-30

0JC ................................... 140 C/W

HI-774
Definitions of Specifications

•..........
I

Linearity Error

Full Scale Calibration Error

Linearity error refers to the deviation of each individual
code from a line drawn from "zero" through "full scale".
The point used as "zero occurs V,LSB (1.22mV for 10 volt
span) before the first code transition (all zeros to only the
LSB "on"). "Full scale" is defined as a level 1VoLSB beyond
the last code transition (to all ones). The deviation of a
code from the true straight line is measured from the
middle of each particular code.

The last transition (from 1111 1111 1110 to 1111 1111
1111) should occur for an analog value 1VoLSB below the
nominal full scale (9.9963 volts for 10.000 volts full scale).
The full scale calibration error is the deviation of the
actual level at ttie last transition from the ideal level. This
error, which is typically 0.05 to 0.1% of full scale, can be
trimmed out as shown in Figures 2 and 3. The full scale
calibration error over temperature is given with and
without the initial error trimmed out. The temperature
coefficients for each grade indicate the maximum change
in the full scale gain from the initial value using the
internal 10 volt reference.

The HI-774K and L, grades are guaranteed for maximum
nonlinearity of ±VoLSB. For these grades, this means that
an analog value which falls exactly in the center of a given
code width will result in the correct digital output code.
Values nearer the upper or lower transition of the code
width may produce the next upper or lower digital output
code. The HI-774J grade is guaranteed to ±1 LSB max
error. For this grade, an analog value which falls within a
given code width will result in either the correct code. for
that region or either adjacent one.

Temperature Coefficient$
The temperature coefficients for full-scale calibration,
unipolar offset, and bipolar offset specify the maximum
change from the initial (25 0 C) value to the value at Tmin
or Tmax.
.
Power Supply Rejection

Note that the linearity error is not user-adj ustable.
Differential Linearity Error (No Missing Codes)
A specification which guarantees no missing codes
requires that every combination appear .in a monotonic
increasing sequence as the a'nalog input level is
increased. Thus every code must have a finite width. For
the HI-774 K and L grades which guarantee no missing
codes to 12-bit resolution, all 4096 codes must be present
over. the entire operating temerature ranges. The HI-774J
grade guarantees no missing codes to 11-bit resolution
over temperature; this means that all code combinations
of the upper 11 bits must be present; in practice very few
of the 12"bit codes are missing.
UnipoiarOffset
The first transition should occur at a level VoLSB above
analog common. Unipolar offset is defined as the
deviation of the actual transition from that pOint. This
offset can be adjusted as discussed on the following
pages. The unipolar offset temperature coefficient
specifies the maximum change of the transition point over
temperature, with or without external adjustment.
Bipolar Offset
Similarly, in the bipolar mode, the major carry transition
(0111 1111 1111 to 1000 0000 0000) should occur for an
analog value VoLSB below analog common. The bipolar
offset error and temperature coefficient specify the initial
deviation and maximum change in the error over
temperature.

The standard specifications for the HI-774 assume use of
+5.00 and ±15.00 or ±12.00 volt supplies. The only effect
of power supply error on the performance of the device
will be a small change in the full scale calibration. This will
result in a linear change in all lower order codes. The
specifications show the maximum change in calibration
from the initial value with the supplies at thevarious limits.
Code Width
A fundamental quantity for AID converter specifications
is the code width. This is defined as the range of analog
input values for \'\ihich a given digital output code will
occur. The nominal value of acode width,is equivalent to 1
least significant bit (LSB) of the full scale range or 2.44mV
out of 10 volts for a 12~bit ADC.
.
Quantization Uncertainty
Analog-to-digital converters exhibit an inherent quantization uncertainty of' ±VoLSB. This uncertainty is a
fundamental characteristic of the quantization process
and cannot be reduced for a cbnverterofgiven resolution.
Left-Justified Data
The data format used in the HI-774 is left-justified. This
means that the data represents the analog input as a fraction of full-scale, ranging fro'm 0 to ~ . This implies a
.
binary point to the left of theMSB. 4096

5-31

~

crli)
0 ....

'i'>
«2

8

HI-774
Applying the HI-774
For each application of this converter, the ground connections, power supply bypassing, analog signal source,
digital timing and signal routing on the circuit board must
be optimized to assure maximum performance. These
areas are reviewed in the following sections, along with
basic operating modes and calibration requirements.
PHYSICAL MOUNTING AND LAYOUT
CONSIDERATIONS
Layout-

Unwanted, parasitic circuit components, (L, R, and C) can
make 12 bit accuracy impossible, even with a perfect AID
converter. The best policy is to eliminate or minimize
these parasitics through proper circuit layout, rather than
try to quantify their effects.
The recommended construction is a double-sided printed
circuit board with a ground plane on the component side.
Other techniques, such as wire-wrapping or point-topoint wiring on vectorboard, will have an unpredictable
effect on accuracy.
In general, sensitive analog signals should be routed
between ground traces and kept well away from digital
lines. If analog and digital lines must cross, they should do
so at right angles.
Power Supplies

Supply voltages to the HI-774 (+15V, -15V and +5V) must
be "quiet" and well regulated. Voltage spikes on these
lines can affect the converter's accuracy, causing several
LSB'sto flicker when a constant input is applied. Digital
noise and spikes from a switching power supply are especially troublesome. If switching supplies must be used,
outputs should be carefully filtered to assure "quiet" DC
voltage at the converter terminals.
Further, a bypass capacitor pair on each supply voltage
terminal is necessary to counter the effect of variations in
supply current. Connect one pair from pin 1 to 15 (VLOGIC
supply), one from pin 7 to 9 (VCC to Analog Common) and
one from pin 11 to 9 (VEE to Analog Common). For each
capacitor pair, a 10pF tantalum type in parallel with a O.1pF
ceramic type is recommended.
Ground Connections

The typical HI-774 ground currents are 6mADC into pin 9
(Analog Common) and 3mADC out of pin 15 (Digital
Common). These pins should be tied together at the
package to guarantee specified performance for the
converter. In addition, a wide PC trace should run directly

from pin 9 to (usually) 15V common, and from pin 15 to
(usually) the +5V Logic Common. If the converter is
located some distance from the system's "single point"
ground, make only these connections to pins 9and 15: Tie
them together at the package, and back to the system
ground with a single path. This path should have low
resistance since it will carry about 3mA of DC current.
(Code dependent currents flow in the VCC, VEE and
VLOGIC terminals, but not through the HI-774's Analog
Common or Digital Common).
ANALOG SIGNAL SOURCE
The device driving the HI-774 analog input will see a
nominal load of 5KU (10V range) or 10KU (20V range).
However, the other end of these input resistors may
change as much as ±400mV with each bit decision. These
input disturbances are caused by the internal DAC
changing codes which causes a glitch on the summing
junction. This creates abrupt changes in current at the
analog input causing a "kick back" glitch from the input.
Because the algorithm starts with the MSB, the first
glitches will be the largest and get smaller as the
conversion proceeds. These glitches can occur at 350ns
intervals so an op-amp with a low output impedance and
fast settling is desirable. Ultimately, the input must settle
to within the window of figure 1 at the bit decision points
in order to achieve 12 bit accuracy.
The HI-774 differs from the most high-speed successive
approximation type ADC's in that it does not require a
high performance buffer or sample and hold. With error
correction the input can settle while the conversion is
underway, but only during the first 4.s.us. The input must
be within ±O.76% of the final value when the MSB decision
is made. This occurs approximately 650ns after the
conversion has been initiated. Digital error correction
'also loosens the bandwidth requirements of the buffer or
sample and hold. As long as the input "kick back"
disturbances settle within the window of figure 1 the
device will remain accurate. The combined effect of
settling and the "kick back' disturbances must remain in
the figure 1 window.
If the design is being optimized for speed, the input device
should have a closed loop bandwidth to 3M Hz, and a low
output impedance (calculated by dividing the open loop
output resistance by the open loop gain). If the
application requires a high speed sample and hold the
Harris HA-5330 or HA-5320 are recommended.
In any design the input (pin 13 or 14) should be checked
during a conversion to make sure that the input stays
within the correctable window of figure 1.

5-32

HI-774
o:::t

......
......I

DIGITAL ERROR CORRECTION
The HI-774 features the smart sucessive approximation
register (SSAR'") which includes digital error correction.
This has the advantage of allowing the initial input to vary
within a +31 to -32LSB window about the final value. The
input can move during the first 4.8ps, after which it must
remain stable within ±V,LSB. With this feature a conversion can start before the input has settled completely;
however, it must be within the window as described in
Figure 1.
The conversion cycle starts by making the first 8-bit
decisions very quickly, allowing the internal DAC to seWe
only to 8-bit accuracy. Then the converter goes through
two error correction cycles. At this point the input must be
stable within ±V,LSB. These cycles correct the 8-bit word
to 12-bit accuracy for any errors made (up to +16 or -32
bits). This is up one count or down two counts at 8-bit

resolution. The converter then continues to make the
4LSB decisions, settling out to 12-bit accuracy. The last
four bits can adjust the code in the positive direction by up
to 15 bits. This results in a total correction range of +31 to
-32 bits. When an 8-bit conversion is performed, the input
must settle to within ±V,LSB at 8 bit resolution (which
equals ±8 bits at 12-bit resolution).
With the HI-774 a conversion can be initiated before the
input has completely settled, as long as it meets the
constraints of the Figure 1 window. This allows the userto
start conversion up to 4.8ps earlier than with a typical
analog to digital converter. A typical successive
approximation type ADC must have a constant input
during a conversion because once a bit decision is made it
is locked in and cannot change.

32

16
BIT DECISION POINTS

1\ ...

12

9~
oD:
~w
,>

(~~B~:::~~~I';~~~;~:ri~~) oj---!.-~------~~~~~$=~,\
END OF
CONVERSION
(12 BIT)

-8

«z

8

-16

-31

CONVERSION INITIATED

FIGURE 1. HI-774 ERROR CORRECTION WINDOW VS. TIME

HI-774

.,

lOOk

HI-714

12/8

12/8

GS

cs

A,

A,

Ric

RIC

CE

CE

STS

28

-15V~+15V

Ref IN

lOOk

10

REF IN
REF OUT
REF OUT
RIP OFF

100n

12

SIP Off

+5V

1

+5V

OTO +10V

0------l
INPUTS 0 - - - - - - l 14

ANALOG

9

1DVIN
20VIN

ANA COM

1

±5V

+15V 7

10VIN

ANALOG
INPUTS

-15V 11

20VIN

+15V 7

-15V 11

±.10V

DIG COM

~

15
':'

ANA COM

DIG COM

15
':'

FIGURE 3. BIPOLAR INPUT CONNECTIONS

FIGURE 2. UNIPOLAR CONNECTIONS

5-33

HI-774
RANGE CONNECTIONS AND CALIBRATION
PROCEDURES

The HI-774 is a "complete" AID converter, meaning it is
fully operational with addition of the power supply
voltages, a Start Convert signal, and a few external
components as shown in figures 2 and 3. Nothing more is
required for most applications.
Whether controlled by a processor or operating in the
stand-alone mode, the HI-774 offers four standard input
ranges: OV to +1 OV, OV to +20V, ±5V and ±1 OV. The maximum errors for gain and offset are listed under Specifications. If required, however, these errors may be adjusted
to zero as explained below. Power supply and ground
connections have been discussed in an earlier section.
Unipolar Connections and Calibration-

Refer to figure 2. The resistors shown' are for calibration
of offset and gain. If this is not required, replace R2 with a
500,1% metal fiim resistor and remove the network on pin
12. Connect pin 12 to pin 9. Then, connect the analog signal to pin 13 for the OV to 10V range, orto pin 14 fortheOV
to 20V range. Inputs to +20V (5V over the power supply)
are no problem-the converter operates normally.
Calibration consists in adjusting the converters's most
negative output to its ideal value (of/set adjustment), then,
adjusting the most positive output to its ideal value (gain
adjustment). To understand the procedure, note that in
principle, one is settling the output with respect to the
midpOint of an increment of analog input, as denoted by
two adjacent code changes. Nominal value of an increment is one LSB. However, this approach is impractical
because nothing "happens" at a midpoint to indicate that
an adjustment is complete. Therefore, calibration is performed in terms of the observable code changes instead
of the midpoint between code changes.

For example, midpoint of the first LSB increment should
be positioned at the origin, with an output code of all O's.
To do this, apply an input of +V,LSB (+1.22mV for the 10V
range; +2.44mV for the 20V range). Adjust the Offset
potentiometer R1 until the first code transition flickers
between 000000000000 and 0000 0000 0001.
Next, perform a Gain Adjust.at positive full scale. Again,
the ideal input corresponding to the last code change
is applied. This is 1'hLSB's below the nominal full scale
(+9.9963V for 10V range; +19.9927V for 20V range). Adjust
the Gain potentiometer R2 for flicker between codes 1111
1111 1110 and 11111111 1111.
Bipolar Connections and Calibration-

Refer to Figure 3. The gain and offset errors listed under
Specifications may be adjusted to zero using potentiometers R1 and R2'. If this isn't required, either or both
pots may be replaced by a 500, 1% metal film resistor.
Connect the Analog signal to pin 13 for a ±5V range, or to
pin 14 for a ±10V range. Calibration of offset and gain is
similar to that for the unipolar ranges as discussed above.
First apply a DC input voltage V,LSB above negative full
scale (i.e., -4.9988V for the ±5V range, or -9.9976V for the
±10V range). Adjust the offset potentiometer R1 for
flicker between output codes 0000 0000 0000 and 0000
00000001. Next, apply a DC input voltage 1V,LSB's below
positive full scale (+4.9963V for ±5V range; +9.9927V for
±10V range). Adjust the Gain potentiometer R2 for flicker
between codes 1111 1111 1110 and 1111 1111 1111.
'The 1000 potentiometer R2 provides Gain Adjust for the
10V and 20V ranges. In some applications, a full scale of
10.24V (LSB equals 2.5mV) or 20.48V (LSB equals 5.0mV)
is more convenient. For these, replace R2 by a 500, 1%
metal film resistor. Then, to provide Gain Adjust for the
10.24V range, add a 2000 potentiometer in series with pin
13. For the 20.48 range, add a 5000 potentiometer in
series with the pin 14.

Controlling the HI-774
The HI-774' includes logic for direct interface to most
microprocessor systems. The processor may take full
control of each conversion, or the converter may operate
in the "stand-alone" mode, controlled only by the RIC
input. Full control consists of selecting an 8 or 12 bit
conversion cycle, initiating the conversion, and reading
the output data when ready-choosing either 12 bits at
once or 8 followed by 4, in a left-justified format. The five
control inputs are all TiL/CMOS- compatible: (12/8, CS,
A o , RIC and CE). Table 1 illustrates the use of these inputs
in controlling the converter's operations. Also, a simplified schematic of the internal control logic is shown in
Figure 4.

"Stand-Alone Operation"

The simplest control interface calls for a single control
line connected to RIC. Also, CE and 12/8 are wired high,
CS and Ao are wired low, and the output data appears in
words of 12 bits each.
The RIC signal may have any duty cycle within (and
including) the extremes shown in Figures 5 and 6. In
general, data may be read when RIC is high unless STS is
also high, indicating a conversion is in progress. Timing
parameters particular to this mode of operation are listed
in the "Stand-Alone Mode Timing" chart.

5-34

HI-774

r-------Ilf------+ OVERRIDE
NIBBLE B ZERO

?----r:Hf-------+

INPUT BUFFERS

NIBBLE A, B

;:::::==============j::::[=F-+-l..JH~------+ NIBBLE C

>-.----. STATUS

STItOBE
CLOCK

~~-ll---)o----+ RESET
EDell

FIGURE 4.

HI-774 CONTROL LOGIC

~

RIC

'r~
oa:
_UJ
,>

«2

..J

STS----;-,-"'!..r-_~£...-_ _

~tHDR.

0811·060

FIGURE 5.

DATA VALID

LOW PULSE FOR RIC-OUTPUTS ENABLED AFTER CONVERSION

tDS

HIGH-Z

DB11-oBO

FIGURE 6.

8

~

tc
HIGH-Z

t-

HIGH PULSE FOR RIC-OUTPUTS ENABLE WHILE RIC HIGH, OTHERWISE HIGH-Z

Stand-Alone Mode Timing
SYMBOL

PARAMETER

MIN

tHRL
tDS

Low RIC Pulse Width
STS Delay from RIC

50

tHOR

Data Valid After RIC Low

20

tHS

STS Delay After Data Valid

tHRH

High RIC Pulse Width

to DR

Data Access Time

TYP

MAX

ns

90

200

ns
ns

300

ns

150

ns

150

5-35

UNITS

ns

HI-774
Conversion Length
A Convert Start transition (see Table 1) latches the state of
A o , which determines whether the conversion continues
for 12 bits (Ao low) or stops with 8 bits (Ao high). If all 12
bits are read following an 8 bit conversion, the last three
LSS's will read zero and DS3 will read ONE. Ao is latched
because it is also involved in enabling the output buffers
(see "Reading the Output Data"). No other control inputs
are latched.

CS
X
1

1
1
1
1
1
1
1

+
+
a

••

a
a
a
a
a
a

RIC
X
X

a
a
a
0

••
1
1
1

12/8

A,

OPERATION

X
X
X
X
X
X
X
X

X
X

None
None
Initiate 12 bit conversion
Initiate 8 bit conversion
Initiate 12 bit conversion
Initiate 8 bit conversion
Initiate 12 bit conversion
Initiate 8 bit conversion
Enable 12 bit Output
Enable 8 MSB's Only
Enable 4 LSB's Plus 4
Trailing Zeroes

1
0

a

a
1
a
1
a
1

X

a
1

The 12/8 input will be tied high or low in most
applications, though it is fully TTL/CMOS-compatible .
With 12/8 high, all 12 output lines become active
simultaneously, for interface to a 12 or 16 bitdata bus. The
Ao input is ignored .

Conversion Start
A conversion may be initiated as shown in Table 1 by a
logic transition on any of three inputs: CE, CS orR/C. The
last of the th ree to reach the correct state starts the
conversion, so one, two or all three may be dynamically
controlled. The nominal delay from each is the same, and
if necessary, all threemaychangestate simultaneously. To
assure that a particular input controls the start of
conversion, the other two should be set up at least 50nS
earlier, however. See the HI-774 Timing Specifications,
Convert mode.
This variety of HI-774 control modes allows a simple
interface in most system applications. The Convert Start
timing relationships are illustrated in Figure 7.

CE

Reading the Output Data
The output data buffers remain in a high impedance state
until four conditions are met: RIC high, STS low, CE high
and Cs low. At that time, data lines become active
according to the state of inputs 12/8 and Ao. Timing
constraints are illustrated in Figure 8.

TABLE 1
TRUTH TABLE FOR HI-774 CONTROL INPUTS

CE
0
X

The output signal STS indicates status of the converter by
going high only while a conversion is in progress. While
STS is high, the output buffers remain in a high
impedance state and data cannot be read. Also, an
additional Start Convert will not reset the converter or
reinitiate a conversion while STS is high.

With 12/8 low, the output is organized in two 8 bit bytes,
selected one at a tim'e by Ao. This allows an 8 bit data bus
to be connected as shown in figure 9. Ao is usually tied to
the least significant bit of the address bus, for storing the
HI-774 output in two consecutive memory locations.
(With Ao low, the 8 MSS's only are enabled. With Ao high,
4 MSS's are disabled, bits 4 through 7 are forced low, and
the 4 LSS's are enabled). This two byte format is
considered "left justified data", for which a decimal (or
binary!) pOint is assumed to the left of byte 1:
BYTE 1

BYTE 2

.Ixxxxxxx xii x x x x

0 0 0 01

I

I
MSB

LSB

Further, Ao may be toggled at any time without damage to
the converter. Sreak-before-make action is guaranteed
between the two data bytes, which assures that the
outputs strapped together in Figure 9 will never be
enabled at the same time.

-------JI4----tHEC~-----

CE-----II

CS---'\I

fS---"""'\1

RIC ---~r-+--------t-"\I

R / C - - -...

A.----...

A. - - - " \

,.-+---------1---.. ~---

STS
STS

-----+--.11
'DSC I+---*------~
HIGH IMPEDANCE

DBll-DBO

-----+-------------

DBll-DBO

FIGURE 7. CONVERT START TIMING

-----+-------{.t-FIGURE 8.

See HI-774 Timing Specifications for more information

5-36

READ CYCLE TIMING

HI-774
A read operation usually begins after the conversion is
complete and STS is low. For earliest access to the data

however, the read should begin no later than (t DD + tHS)
before STS goes low. See Figure 8.

\

ADDRESS BUS

r

2

1218

27
26
25
24
DATA
BUS

23
22

HI-774
21
20
19
18
17

16
15
DIG. '--"-~

COM.

-1

FIGURE 9. INTERFACE TO AN 8 BIT DATA BUS

5-37

~

9~
0'"
~w
,>

«z

oc..>

II~RIS

HI-774A

ADVANCED

711S, Complete 12-Bit AID Converter
With Microprocessor Interface

Features

Description

• Complete 12 Bit AID Converter With Reference and
Clock

The HI-774A is a complete 12 bit Analog-to-Digital
Converter, including a +10V reference, clock, three-state
outputs and a digital interface for microprocessor control.
Successive approximation conversion is performed by
two monolithic dice housed in a 28-pin package. The
bipolar analog die features the Harris Dielectric Isolation
process, whch provides enhanced AC performance and
freedom from latch-up. The digital die features the smart
SAR (SSAR'"), which includes a digital error correction
circuit.

• Digital Error Correction
• Full 8-, 12-, or 16-Bit Microprocessor Bus Interface
• 150 nS Buss Access Time
• No Missing Codes Over Temperature
• Minimal Setup Time For Control Signals
• 81ls Maximum Conversion Time Over Temperature
• Low Noise, Via Current-mode signal transmission
between chips
• Byte enable/short cycle (Ao Input)
~

Guarantees break-before-make action, eliminating bus
contention during read operation. Latched by the Start
Convert Input (To Set the Conversion Length)

• Faster Version of the HI-574A and HI-674A
• Same Pin-Out as HI-574A and HI-674A
• ±12V to ±15V Operation

Custom design of each IC (bipolar and CMOS digital) has
yielded improved performance over existing versions of
this converter. The voltage comparator features high
PSRR plus a high speed current-mode latch, and provides
precise decisions down to 0.1 LSB of input overdrive.
More than 2X reduction in noise has been achieved by
using current instead of voltage for transmission of all
signals between the analog and digital IC's. Also, the
clock oscillator is current controlled for excellent stability
over temperature. The oscillator is trimmed for a
guaranteed conversion time of 7 ± 11ls over temperature.
The HI-774A offers standard unipolar and bipolar input
ranges, laser trimmed for specified linearity gain and
offset accuracy. The low noise buried zener reference
circuit is trimmed for minimum temperature coefficient.

Applications

Power requirements are +5V and ±12V to ±15V, with
typical dissipation of 390mW at ±12V. Three electrical
grades each are offered for the commercial and military
temperature ranges. All models are packaged in a 28 pin
side-brazed, ceramic DIP. For information on MIL-STD-883
compliant device's request the HI-774A1883 data sheet.

• Military and Industrial Data Acquisition Systems
• Electronics Test and Scientific Instrumentation
• Process Control Systems

Pinout

TOPVIEW

+5V SUPPLY, VLOGIC [ 1

~

DATA MODE SELECT, 12/SC 2
CHIP SELECT,

CS C

28 JSTATUS, STS
27 JDB11 MSB

3

26 JDB10

BYTE ADDRISHORT CYCLE, AU C 4

25 JOB9

READ/CONVERT, R/C[ 5

24 JDBB

CHIP ENABLE, CE C 6

+12V1+15V SUPPLY, VCC C 7

23 JDB7
HI-774A

22 JDB6

+10V REFERENCE OUT C B

21 JDB5

ANALDG COMMDN [ 9

20 JDB4

REFERENCE INPUT C 10

19 JDB3

-12V1-15VSUPPLY,VEEC11

lBJDB2

BIPOLAR OFFSET, BIP OFF C 12

17 JDBl

10V INPUT[ 13

DIGITAL
DATA
OUTPUTS

16 JDBO LS8

20V INPUT[' 14
- -_ _ _ _15
-1JDIGITAL COMMDN

5-38

HI-774A Block Diagram
c(

-.:t
.....
.....

Block Diagram

I

BIT OUTPUTS
(

~----------------~~------------------~~
MSB
LSB,

12J8

fS

~

2
3
4

A. v5

RIC
CE

26

qqq

()

()
27

25

24

23

21

20

19

lB

~

'(.BI~

OSCILLATOR

I

16

THREE-STATE BUFFERS AND CONTROL

-----./

6

~

)c;>
17

NIBBLE" C

NIBBLE" B

NIBBLE" A
CONTROL
LOGIC

22

ff-

COMMON
STS

SSAR™

STROBE

DIGITAL CHIP

V.i~

IN

...

I
+10V
REF.

I

/
I
I
I

10K

B
V." OUT

12 BITS

............

~ 10

VL08lC

DIGITAL

2B

~

ANALOG CHIP

1,..
15 -

DAC

I t+Ll~

5K

?' 2.SK

10K
SK

14

12

9
C)

)

ANALOG

BIP.
OFF

COMMON
-("·NIBBLE·· IS A 4 BIT DIGITAL WORD.)

Die Characteristics
Analog Die ........................................................ Bipolar, 01
Digital Die ........................................................... CMOS, JI
Transistor Count ....................................................

~

21 00

5-39

13

20V
10V
INPUT INPUT

Specifications HI-774A
DC and Transfer Accuracy Specifications
(TA c+250e with Vee

=+15V or +12V, VLOGle =+5V, VEE =-15V or -12V unless otherwise specified)

MODEL

HI-774AJ

HI-774AK

o TO

Temperature Range

HI-774AL

UNITS

+75

°c

Resolution (max)

12

12

12

Bits

Linearity Error
25°C (max)
OoC to +75 0 C (max)

±1
±1

±1/2
±1/2

±1/2
±1/2

LSB
LSB

Differential Linearity Error
(Maximum resolution for which no missing codes is guaranteed)
25 0 C
Tmin to Tmax

11
11

12
12

12
12

Bits
Bits

Unipolar Offset (max)
(Adjustable to zero)

±2

±2

±2

LSB

Bipolar Offset (max)
(Adjustable to zero)

±10

±4

±4

LSB

Full Scale Calibration Error
2S oC (max), with fixed 50n resistor from
REF OUT to REF IN (Adjustable to zero)

0.3

0.3

0.3

% of F.S.

Tmin to Tmax
(No adjustment at +25 0 C)
(With adjustment to zero at 25 0 C)

0.5
0.22

0.4
0.12

0.35
0.05

% of F.S.
% of F.S.

±2
±2
±9

±1
±1
±5

±1
±1
±2

LSB
LSB
LSB

LSB
LSB
LSB

Temperature Coefficients (see definitions)
Guaranteed max change, Tmin to Tmax (Using internal reference)
Unipolar Offset
Bipolar Offset
Full Scale Calibration
Power Supply Rejection
Max change in Full Scale Calibration
+13.5V

<2
C

(.)

Power Supply Rejection
Max change in Full Scale Calibration
+13.5V0_----.

STATUS

STROBE
CLOCK

I'~--r-J~"---"" RESET

'---~

Eoel3

FIGURE 4,

HI-774A CONTROL LOGIC

RIC---,

'C
STS ------'---~I+_-------~

~'HOR

OBl1-0BO

FIGURE 5.

DATA VALID

LOW PULSE FOR RIC-OUTPUTS ENABLED AFTER CONVERSION

RIC

'OS

STS
I:DDR,
DBl1-DBO

FIGURE 6.

HIGH-Z

DATA VALID

~

t-

'C

HIGH-Z

HIGH PULSE FOR RIC-OUTPUTS ENABLE WHILE RIC HIGH. OTHERWISE HIGH-Z

Stand-Alone Mode Timing
SYMBOL

PARAMETER

MIN

Low RIC Pulse Width

tHRL
tDS

STS Delay from RIC

tHDR

Data Valid After RIC Low

tHS

STS Delay After Data Valid

tHRH

High RIC Pulse Width

tDDR

Data Access Time

TYP

MAX

200

ns
ns

20
90

300

ns
ns

150
150

5-47

UNITS
ns

50

ns

~

......

......I
::r:::

HI-774A
Conversion Length
A Convert Start transition (see Table 1) latches the state of
A o , which determines whether the conversion continues
for 12 bits (Ao low) or stops with 8 bits (Ao high). If al112
bits are read following an 8 bit conversion, the last three
LSB's will read zero, and DB3 will read ONE. Ao is latched
because it is also involved in enabling the output buffers
(see "Reading the Output Data"). No other control inputs.
are latched.
RIC 12/8

CE

CS

0
X

X
1

X
X

0
0

0
0
0
0

t
t

1
1
1
1
1
1
1

t

t

0
0
0
0
0

t
t

1
1
1

Ao

X
X
X
X
X
X
X
X
1

X
X

0
0

0

0
1
0
1

0
1
X
1

The output signal STS indicates status of the converter by
going bigh only while a conversion is in progress. While
STS is high, the output buffers remain in' a high
impedance state and data cannot be. read. Also, an
additional Start Convert will not reset the converter or
reinitiate a conversion while STS is high.
Reading the Output Data
The output data buffers remain in a hig'h impedance state
until four conditions are met: R/C high, STS low, CE high
and CS low. At that time, data lines become active
according to the state of inputs 12/8 and Ao. Timing
constraints are illustrated in Figure 8,

OPERATION
None
None
Initiate 12 Bit Conversion
Initiate 8 Bit Conversion
Initiate 12 Bit Conversion
Initiate 8 Bit Conversion
Initiate 12 Bit Conversion
Initiate 8 Bit Conversion
Enable 12 Bit Output
Enable 8 MSB's Only
Enable 4 lSB's Plus 4
Trailing Zeroes

The 12/8 input will be tied high or low in most
applications, though it is fully TTL/CMOS-compatible.
With 12/8 high, all 12 output lines become active
simultaneously, fq( interface to a 120r 16 bit data bus, The
Ao input is ignored.
Wit.h 12/8 low, the output is organized in two 8 bit bytes,
selected one at a time by Ao' This allows an 8 bit data bus
to be connected as shown in Figule 9. Ao is usually tied to
the least significant bit of. the address bus,for storing the
HI-774A output in two consecutive memory locations.
(With Ao low, the 8MSB's only are enabled. With Ao high,
4 MSB'sare disabled, bits 4 through 7 are forced low, and
the 4 LSB's are enabled). This two byte format is
considered "left justified data", for which a decimal (or
binary!) point is assumed to the left of byte 1:

TABLE 1
TRUTH TABLE FOR HI-774A CONTROL INP.UTS

Conversion Start
A conversion may be initiated as shown in Table 1. by a
logic transition on any of three inputs: CE, CS orR/C. The
last of the three to reach the correct state starts the
conversion, so one, two or all three may be dynamically
controlled. The nominal delay from each is the ·same, and
if necesary, all three may change state simultaneously. To
assure that a particular input controls the start of
conversion, the other two should be set up at least 50nS
earlier, however. See the HI-774A Timing Specifications,
Convert mode.
This variety of HI-774A control modes allows a simple
interface in most system applications. The Convert Start
timing relationships are illustrated in Figure 7.

BYTE 2

BYTEt

IxxxxXXX X I Ix X X X 0 0

• I

o 01

I

lSB

MSB

Further, Ao may be toggled at any time without damage to
the converter. Break-before-make action is guaranteed
between the two data bytes, which assures that the
outputs strapped together in Figure 9 will never be
enabled at the same time.

c. _ _ _...J1.

c·----'I

RIC

RIC

A.------'r~'r_----------------

-----,r-I-------+-.I

A.

STS
STS

-----I--JI
tDSCI+---~-----+I

DB11-DBO

DBl1-DBD----~>HiMiffiijiNcE~~~t:t~

-----1------------

FIGURE 7.

FIGURE 8.

CONVERT START TIMING

READ CYCLE TIMING

See HI-774A Timing Specifications for more information.

5-48

HI-774A
A read operation usually begins after the conversion is
complete and STS is low. For earliest access to the data

Ao

.,

however, the read should begin no later than (too + tHS)
before STS goes low. See figure 8.

\

ADDRESS BUS

r--v-

STS~

1Z/8

DB11(MSB) r=2!.,7........t - - - -

26
25

'-----..Ao

24

23
HI-774A

22

21

20

~
lB
17

n

DBO(LSB) 1--'1.::.6_ _ _--"
DIG.eDM·

FIGURE 9. INTERFACE TO AN 8 BIT DATA BUS

5-49

DATA
BUS

HY-9574

mHARRIS
ADVANCED

Sampling 12. Bit AID Converter with
8/16 Bit IJP Interface

Features

Applications

• Complete 12 Bit Sampling AID Converter with
Reference and Clock

• Precision Industrial Data Acquisition Systems

• Throughput Rate (Typical) ................................. 48kHz
• 32 Pin Plastic Dual-In-Llne Package

• Electronic Test and Scientific Instrumentation
• Process Control Systems
• Peak Detectors

Sample/Hold Features
A/D Converter Features

• Gain DC .......................................................... 2x106 V/V

• Full 8-, 12- or 16 Bit Microprocessor Bus Interface

• Acquisition Tlme .................................... 1.0IlS (±0.01%)

• 150ns Bus Access Time

• Droop Rate ......................................... O.08p.V/IlS (250 C)
2.41lVllls (Full Temp.)

• No Missing Codes Over Temperature

• Aperture Time ..........:...............................................25ns

• Minimal Setup Time for Control Signals

• Pedestal Error ....................................................... 1.0mV

• 25ps Maximum Conversion Time
• Low Noise, via Current-Mode Signal Transmission
Between Chips
• Byte Enable/Short Cycle (Ao Input)

~

• Internal Hold Capacitor

oj:!:!

''''
s.~

• Fully Differential Input

5V1

1101

DJTAL
COMMON

(311

(51

(2)

YCC t&YI ANIDG YEE (I,5YI
COMMON

(231 STATUS

1

(ZZI Msa DBl1
(ZII
DBID
(ZOI
Da9
DBa
1191
THREE
DBl
1111
STATE
(171
OBI
BUFFERS
II DIGITAL
DB&
1181
MULTIDB4
11&1
PLEXER
DB3
1141
1131
DBZ
Dal
I--< (12)
~ (111 LSB DBO

t-t--

r
r
rr
r
rrr-

SAMPLEI

>INPUT 111

-INPUT (32)

>--

r>>

12 B(T
AID CONVERTER

>--v

.--

J-

SIH (301
CONTROL
~

>IOV
REF.

DSC.

T
(31
SIH
OUTPUT

(al
IOV
INPUT

(91
ZDY
INPUT

(41
VREF
OUT

'--(81
YREF
IN

(71
BIPOLAR
OFFSET

5-51

i---

i

---t

CONTROL
LOGIC

--<
--<

(Z&I DATA MODE SELECT IZii
(281 CHIP SELECT Cs
(Z7I BYTE ADDRESSISHORT CYCLE Ao

---<

(21) READ CONVERT

RiC

(HI CHIP ENABLE CE

SAMPLING AOC

HY-9574

T~eHYc9574 is designed for use in precision. high speed
data acquisition systems. The Harris SamplelHold
amplifier (HA-5320) and 12 bit A/D converter (H 1-574A)
have been combined in a single package to reduce
package count and to insure component compatibility.

provides enhanced AC performance and freedom from
latch-up.
Custom design of each IC (Bipolar Analog and CMOS
Digital) has yielded improved versions of this converter.
The voltage comparator features high PSRR plus a high
speed current-mode latch. and provides precise decisions down to 0.1 LSB of input overdrive. More than 2X
reduction in. noise has been achieved by using current
instead of voltage for transmission of all signals between
the analog and digital IC's. Also, the clock oscillator is
current-controlled for excellent stability over temperature. The oscillator is trimmed for a nominal conversion
time of 20 ± 1Jls.

The Sample/Hold (HA-5320) circuit consists of an input
transconductance amplifier capable of providing large
amounts of charging current, a low leakage analog
switch, and an output integrating amplifier. The analog
switch sees virtual ground as its load; therefore, charge
injection on the hold capacitor is constant over the entire
input/output voltage range. The device includes a hold
capacitor, so no external hold capacitor is required.

The Sample/Hold and ADC stages are not connected
internally to provide maximum flexibility to the designer.

The Sample and Hold chip (HA-5320) is manufactured
using the Harris Dielectric Isolation process, which
minimizes stray capacitance and eliminates SCR's. This
allows higher speed and latch-free operation.
The 12 bit successive approximation Analog-to-Digital
section is an HA-574A chip set. It includes a +10V
referehce, clock, three-state outputs and a digital
interface for microprocessor control. The bipolar analog
die features the Harris Dielectric Isolation process, which

The HY-9574 offers standard unipolar and bipolar input
ranges, laser trimmed for specified linearity, gain and
offset accuracy. The buried zener reference circuit is
trimmed for minimum temperature coefficient.
Power requirements are ±15V and +5V, with typical
dissipation of 850mW. All models are packaged in a 32 pin
plastic DIP with 600 mil row centers.

Pinout
TOP VIEW

+8/H IN
-V
S/H OUT
REF OUT
ANALOG GNO
REF IN
8. P. OFF
10V IN
20V IN
DIGITAL GNO
080 [LS8)
081
082
083
OB4
085

-S/H IN
+V
S/H CONTROL
CE
Ric
Ao
CS

1218
VCC [+5V)
STATUS [STS)
0811
0810
089
OBB
OB7
086

5-52

HY-9574 System Specifications
Absolute Maximum Ratings
VCC to Digital Common ................................... O to +16.5V
VEE to Digital Common ................................... 0 to -16.5V
VLogic to Digital Common ....................................O to +7V
Analog Common to Digital Common ......................... ±1V
Digital Inputs (CE, CS, A o , 12/8, RIC, S/H)
to Digital Common ........................ -O.5V to VLogic +O.5V
Analog Inputs (REF IN, SIP OFF, 10VIN +IN, -IN)
to Analog Common ............................................... ±16.5V
20VIN to Analog Common ........................................ ±24V

REF OUT ............................. Indefinite Short to Common,
Momentary Short to VCC
S/H Differential Input.Voltage .................................. ±24V
S/H Output Current, Continuous .......................... ±20mA
'Storage Temperature .............................. -650 C to +150 0 C
ppwer Dissipation ~ ............................................. 256dinw
Lead Temperature, Soldering .................................. 1800 C
Thermal Resistance,· Oja ......................•................. 39 0 C/W
Ojc ........................................ 140 C/W
*Derate 25.6mW/oC above 75 0 C

MAX

UNITS

Maximum Offset Error

±3

LSB

Maximum Sampling Rate (Note 1)

37

kHz

±2
±1

LSB
LSB

MIN

TYP

POWER SUPPLY REJECTION
Maximum change in full scale calibration
+15V ±0.5V
J and A models
All Other Models
-15V ±0.5V

J and A Models
All Other Models

±3
±2

LSB
LSB

+5V ±0.5V

All Models

±Y,

LSB

POWER SUPPLIES

8

Operating Voltages
VLogic
VCC
VEE

4.5
14.5
-14.5

Operating Currents
ILogic
ICC (Note 3)
lEE (Note 3)

5.0
15.0
-15.0

5.5
16.0
-16.0

Volts
Volts
Volts

7
22
32

15
28
41

mA
mA
mA

(In configuration as shown in Figure 1)

ANALOG
INPUT

S/H IN+

S/H IN-

SfH OUT
REF OUT
REF IN

'"'

'"
S!

~

9~
Ow
'i'>
«z

BIP OFF
lOV IN
DIGITAl GND
ANALOG GND
HY-9574

FIGURE 1. FOR CALIBRATION INSTRUCTION SEE "RANGE SELECTION AND CALIBRATION PROCEDURES"
.
SECTION OF THIS DATA SHEET.

5..c53

HY-9574 System Specifications

PARAMETER

TEMP

MIN

TYP

-40 0 C to +85 0 C
250 C

±10
1

5

MAX

UNITS

INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance

V
M!l

D.C. & TRANSFER ACCURACY SPECIFICATIONS
Resolution (Maximum)
Linearity Error
Differential Linearity Error
J and A Models
All Other MOdels

-400 C to +85 0 C

12
±1

Bits
LSB

Full
Full

11
12

Bits
Bits

+5.5
+0.8
-5 (Note 2)
+5 (Note 2)
+0.4

V
V
/lA
/lA
V
V
/lA

DIGITAL INPUT & OUTPUT CHARACTERISTICS
Input Voltage (High), VIH
Input Voltage (Low), VIL
Input Current (VIL = OV)
Input Current (VIH = +5V)
Logic "0" Output (iSINK = 1.6mA)
Logic "1" Output (iSOURCE = 500/lA)
Leakage Current (High Z State, DBO-ll Only)

Full
Full
Full
Full
Full
Full
Full

+2.4
-0.5

+2.4
-5

0.1

+5

POWER SUPPLY CHARACTERISTICS
Positive Supply Voltage
Negative Supply Voltage
Logic Supply Voltage
Positive Supply Current (Note 3)
Negative Supply Current (Note 3)
Logic Supply Current
Power Supply Rejection V+ (Note 10)
J & A Models
All Other Models
Power Supply Rejection V- (Note 10)
J & A Models
All Other Models
Power Dissipation

+16.0
-16.0
+5.5

+14.5
-14.5
+4.5

?8
41
15

V
V
V
mA
mA
mA

25 0 C

±2
±1

LSB
LSB

25 0 C
25 0 C

±2
±1

LSB
LSB
mW

25
17
1000
1.5

/lS
/lS

22
32
7

2SOC

850

TIMING SPECIFICATIONS
Conversion Time

12 Bit Cycle
8 Bit Cycle
STS Delay After Data Valid
S/H Acquisition Time (0.01%)
Aperture Time
Aperture Uncertainty
Droop Rate
Throughput Rate (Note 1)

+25 0 C
+25 0 C
+25 0 C
+25 0 C
+25 0 C
+25 0 C
+25 0 C
-40 0 C to +85 0 C
+25 0 C

5-54

15
10
300

20
13
500
1.0
25
0.3
0.08
17

ns
/lS

ns
ns
0.5
100

/lVI/ls
/lVI/ls

37

kHz

HY-9574 Sample And Hold Amplifier Specifications
Electrical Characteristics

Test Conditions (Unless otherwise specified)
VSuppl y ; ±15V; CH -Internal; Digital Input (Pin 14), VAL; +O.BV (Sample), VAH; +2.0V (Hold).

PARAMETER

ooC S TA S 75 0 C

-400 C S TA S 850 C

OPERATING TEMP RANGE
TEMP

MIN

TYP

Full
25°C
25°C
25°C
Full
25°C
Full
25°C
Full
Full
25°C
Full

±10
1

5

25°C

106

MAX

MIN

I

TYP

MAX

UNITS

INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Capacitance
Offset Voltage
Bias Current
Offset Current
Common Mode Range
CMRR (Note 4)
Offset Voltage T.C.

0.2
70
30
±10
BO

90
5

±10
1
3
0.5
2.0
200
200
100
100

5
0.5
100
30

±10
72
15

90
5

3
1.0
1.5
300
300
300
300

20

V
Mll
pF
mV
mV
nA
nA
nA
nA
V
dB
/1V/OC

TRANSFER CHARACTERISTICS
Gain, dC
Gain Bandwidth Product (Note 5)
CH = 100pF

2 x 106

3 x 105

2.0

25°C

2 x 106

V/V

2.0

MHz

600
1.0

V
mA
kHz
II

OUTPUT CHARACTERISTICS
Output Voltage
Output Current
Full Power Bandwidth (Note 6)
Output Resistance (Hold Mode)
Total Output Noise, DC to 10MHz
Sample
Hold

Full
25°C
25°C
25°C

±10
±10

±10
±10
600
1.0

25°C
25°C

125
125

25°C
25°C
25°C

100
15
45

125
125

200
200

200
200

/1VRMS
/1V RMS

TRANSIENT RESPONSE
Rise Time (Note 5)
Overshoot (Note 5)
Slew Rate (Note 7)

ns
%
V//1S

100
15
45

DIGITAL INPUT CHARACTERISTICS
Input
Input
Input
Input

Voltage
Voltage
Current
Current

(High), VAH
(Low), VAL
(VAL = OV)
(VAH = +5V)

Full
Full
Full
Full

2.0

2.0
O.B
4
0.1

O.B

4
0.1

V
V
/1 A
/1 A

SAMPLE/HOLD CHARACTERISTICS
Acquisition Time (0.1%) (Note 7)
Acquisition Time (0.01%) (Note 7)
Aperture Time (Note B)
Effective Aperture Delay Time
(See S/H Glossary)
Aperture Uncertainty
Hold Capacitor, CH
Droop Rate
Droop Rate
Drift Current (Note 9)
Drift Current (Note 9)
Charge Transfer (Note 9)
Hold Mode Settling Time (0.01%)
Hold MOde Feedthrough
10Vp-p. 100kHz

25°C
25°C
25°C
25°C

-50

O.B
1.0
25
-25
0.3
100
0.06
2.4
B
0.24
0.1
165
2

25°C
25°C
Full
25°C
Full
25°C
Full
Full

1.2
1.5
0

-50

O.B
1.0
25
-25
0.3
100
O.OB
1.2
B
0.12
0.1
165
2

0.5
100
50
10
0.5
250

1.2
1.5
0

0.5
100
50
10
0.5
250

/1S
/1S
ns
ns
ns
pF
/1V//1S
/1V//1S
pA
nA
pC
ns
mV

POWER SUPPLY CHARACTERISTICS
Power Supply Rejection.V+
(Note 10) V-

Full
Full

BO
65

BO
65

5-55

dB
dB

HY-9574· Analog-to-DigitaIConverter Specifications
DC and Transfer Accuracy Specifications
(Typical @ +25 0 e with Vee= +15V, VLOGle = +5V, VEE = -15V unless otherwise specified)
TEMPERATURE RANGE DOC to +75 0 C
HY~9574J

HY-9574K

HY-9574L

UNITS

12

12

12

Bits

±1
±1

±1/2
±1/2

±1/2
±1/2

LSB
LSB

11
11

12
12

12
12

Bits
Bits

Unipolar Offset (Max.) (Adjustable to zero)

±2

±2

±2

LSB

Bipolar Offset (Max.) (Adjustable to zero)

±10

±4

±4

LSB

25 0 C (Max.), with fixed 50n resistor from
REF OUT to REF IN (Adjustable to zero)

0.3

0.3

0.3

% of Full Scale

TMIN to TMAX
(No adjustment at +25 0 C)
(With adjustment to· zero at +250 C)

0.5
0.22

0.4
0.12

0.35
0.05

% of Full Scale
% of Full Scale

±2
(10)
±2
(10)
±9
(45)

±1
(5)
±1
(5)
±5
(2S)

±1
(5)
±1
(5)
±2
(10)

LSB
(ppm/OC)
LSB
(ppm/oC)
LSB
(ppm/OC)

±2
±1/2
±2

±1
±1/2
±1.

±1
±1/2
±1

LSB
LSB
LSB

MODEL

Resolution (Maximum)
LINEARITY ERROR
25 0 C (Maximum)
OOC to +75 0 C (Maximum)
DIFFERENTIAL LINEARITY ERROR
(Max. resolution for which no missing codes is guaranteed)
25°C
TMIN toTMAX

FULL SCALE CALIBRATION ERROR

TEMPERATURE COEFFICIENTS
Guaranteed max change to TMIN or TMAX (Using internal ref.)
Unipolar Offset
Bipolar Offset
Full Scale Calibration

POWER SUPPLY REJECTION
Max. change in Full Scale Calibration
+13.SV < VCC < +16.S or +ll.4V < VCC < +12.6V
+4.SV < VLOGIC < +S.5V
-16.5V < VEE < -13.SV or -12.6V < VEE < -ll.4V
ANALOG INPUT RANGES
Bipolar

Unipolar

-5 to +S
-10 to +10

Volts
Volts

o to +10
o to +20

Volts
Volts

SK, ±25%
10K, ± 25%

Ohms
Ohms

+10.0 ± 0.1 Max.
2.0 Max.

Volts
rnA

INPUT IMPEDANCE
10 Volt Span
20 Volt Span
INTERNAL REFERENCE
Voltage
Output Current
available for extern1jlloads (External load should not
change during conversion.

5-56

HY-9574 Analog-to-Digital Converter Specifications
DC and Transfer Accuracy Specifications
(Typical @ +25 0 e with Vee = +15V, VLOGle = +5V, VEE = -15V unless otherwise specified)
TEMPERATURE RANGE -400C 10 +85 0 C
MODEL

HY-9574A

HY-9574B

UNITS

12

12

Bits

±1
±1

±112
±1

LSB
LSB

11
11

12
12

Bits
Bits

Unipolar Offset (Max.) (Adjustable to zero)

±2

±2

LSB

Bipolar Offset (Max.) (Adjustable to zero)

±10

±4

LSB

0.3

0.3

% of Full Scale

0.8
0.5

0.6
0.25

% of Full Scale
% of Full Scale

Resolution (Maximum)
LINEARITY ERROR
250C (Maximum)
-400C :S T A :S 850C (Maximum)

,

DIFFERENTIAL LINEARITY ERROR
(Max. resolution for which no missing codes is guaranteed)
25 0 C
TMIN to TMAX

FULL SCALE CALIBRATION ERROR
25 0 C (Max.), with fixed 50!! resistor from
REF OUT to REF IN (Adjustable to zero)
TMIN to TMAX

~

(No adjustment at +25 0 C)
(With .adjustment to zero at +25 0 C)

Guaranteed max change to TMIN or TMAX (Using internal re!.)
Unipolar Offset
Bipolar Offset
Full Scale Calibration

±2
(5)
±4
(10)
±20
(50)

±1
(2.5)
±2
(5)
±10
(25)

LSB
(ppm/°C)
LSB
(ppm/°C)
LSB
(ppm/OC)

±2
±1/2
±2

±1
±112
±1

LSB
LSB
LSB

POWER SUPPLY REJECTION
Max. change in Full Scale Calibration
+13.5V < VCC < +16.5 or +11.4V < VCC < +12.6V
+4.5V < VLOGIC < +5.5V
-16.5V < VEE < -13.5V or -12.6V < VEE < -11.4V
ANALOG INPUTS, INPUT RANGES
Bipolar

Unipolar

10 Volt Span
20 Volt Span

_UJ

,>



"

I ........
1

0
-25

PHASE.

90 DEGREES

.......

ip

HY-9574 Sample/Hold Test Circuits
CHARGE TRANSFER AND DRIFT CURRENT

32

-INPUT
S/H OUTPUT ..3~~-+O

,----1 +INPUT

Vo

HY-9574
S/H
CONTROL
INPUT

DRIFT CURRENT TEST

CHARGE TRANSFER TEST

1. Observe the voltage "droop", JoVo/aT:

1. Observe the "pedestal" voltage V p'

S/H
CONTROL

r"'"1
,..,- - ----J L-..J L--

VO
-

h, ~
~h"

S/H
r-""'1 ~ - - - HOLD 1+3.5V)
CONTROL......
.....
' - - ~ SAMPLE 10VI

HOLD 1+3.5VI
SAMPLE 10VI

Vo~
- aVo
" I~-;:.:I

"1 ___ _

lit

,-r~p-

- - - I JoT I I

2. Compute charge tralTSfer. Q = VpCH

I

2. Measure the slope of the, output during hold, aVoIaT, and compute
drift current: 10 = CH aVo/at.

S/H HOLD MODE I'EEDTHROUGH ATTENUATION

ANALOG
MUX OR
SWITCH
10Vpp
10kHz
SINE WAVE

c.E..

r-..

1

';;;.i'

~

9

HY-9574
-INPUT
+INPOT
S/H OUTPUT
S/HCONTROL
VCC

AIN

31

S/H
CONTROL
INPUT
HOLD
SAMPLE

V+

----r--\,

----.I

L-

FEEDTHROUGH IdB)

=20 Log

VOUT
VIN

WHERE VOUT = VOLTS pp, Hold Mode
VIN = VOLTS pp

5-59

ANALOG
GNO

VEE
2

5

TO SUPPLY
COMMON

V-

3

VOUT

HY-9574
Glossary of Terms
Sample and Hold
Acquisition Time- The time required following a
"sample" command, for the output to reach its final value
within ±0.1% or ±0.01 %. This is the minimum sample time
required to obtain a given accuracy, and includes switch
delay time, slewing time and settling time.
Charge Transfer - The smal.1 charge transferred to the
holding capacitor from the inter-electrode capacitance of
the switch when the unit is switched to the Hold Mode.
Charge transfer is directly proportional to sample-to-hold
offset pedestal error, where:
Charge Transfer (pC) = CH (pF) x Offset Error (V)
Aperture Time - The time required for the sample-andhold switch to open, independent of delays through the
switch driver and input amplifier circuitry. The switch
opening time is that interval between the conditions of
10% open and 90% open.
Hold Step Error - The output error due to Charge
Transfer (see above). It maybe calculated from the specified parameter, Charge Transfer, using the following
relationship:
Charge Transfer (pC)
Hold Step (V) =
100pF
See Sample/Hold Amplifier Performance Curves.
Effective Aperture Delay Time (EADT) - The difference
between propagation time from the analog input to the
S/H switch, and digital delay time between the Hold command and opening of the switch.
EADT may be positive, negative or zero. If zero, the S/H
amplifier will output a voltage equal to VIN at the instant
the Hold command was received. For negative EADT, the
output in Hold (exclusive of pedestal and droop errors will
correspond to a value of VIN that occurred before the
Hold command.
Aperture Uncertainty - The range of variation in Effective Aperture Delay Time. Aperture Uncertainty (also
called Aperture Delay Uncertainty, Aperture Time Jitter,
etc.) sets a limit on the accuracy with which.a waveform
can be reconstructed from sample data.
Drift Current - The net leakage current from the hold
capacitor during the hold mode. Drift current can be
calculated from the droop rate using the formula:
ID (pA) = CH (pF) x

!:J.V
_
(Volts/sec)
!:J.T

Analog/Digital Converter
Linearity Error- Linearity error refers to the deviation of
each individual code from a line drawn from "zero"
through "full scale". The point used as "zero" occurs

V,LSB (1.22mV for 10 volt span) before the first code transition (all zeros to only the LSB "on"). "Full scale" is
defined as a level one and one-half (1 V,) LSB's beyond the
last code transition (to all ones). The deviation of a code
from the true straight line is measured from the middle of
each particular code.
The HY-9574K, L, and B grades are guaranteed for
maximum nonlinearity of ±V,LSB. For these grades, this
means that an analog value which falls exactly in the
center of a given code width will result in the correct
digital output code. Values nearer the upper or lower
transition of the code width may produce the next upper
or lower digital output code. The HY-9574J and A grades
are guaranteed to±1 LSB maximum error. For these
grades, an analog value which falls within a given code
width will result in either the correct code for that region
or either adjacent one. Note that the linearity error is not
user-adjustable.
Differential Linearity Error (No Missing Codes) - A
specification which guarantees no missing codes
requires that every code combination appear in a
monotonic increasing sequence as the analog input level
is increased. Thus every code must have a finite width. For
the HY-9574K, L, and Bgrades, which guarantee no missing codes to 12-bit resolution, all 4096 codes must be
present over the entire operating temperature ranges. The
HY-9574J and A grades guarantee no missing codes to
11-bit resolution over temperature; this means that all
code combinations of the upper 11 bits must be present;
in practice very few of the 12-bit codes are missing.
Unipolar Offset - The first transition should occur at a
level V,LSB above analog common. Unipolar offset is
defined as the deviation of the actual transition from that
point. This offset can be adjusted as discussed on the following pages. The unipolar offset temperature coefficient
specifies the maximum change of the transition pOint over
temperature, with or without external adjustment.
Bipolar Offset..:.. Similarly, in the bipolar mode, the major
carry transition (01111111 1111 to 1000 0000 0000)
should occur for an analog value %LSB below analog
common. The bipolar offset error and temperature
specify the initial deviation and maximum change in the
error over temperature.
Full Scale Calibration Error - The last transition (from
1111 1111 1110 to 1111 1111 1111) should occur for an
analog value one and one-half (1 %) LSB's below the nominal full scale (9.9963 volts for 10,000 volts full scale). The
full scale calibration error is the. deviation of the actual
level at the last transition from the ideal level. This error,
which is typically 0.05 to 0.1 % of full scale, can be trimmed
out as shown in Figures 2 and 3. The full scale calibration
error over temperature is given with and without the initial
error trimmed out. The temperature coefficients for each
grade indicate the maximum change in the full scale gain
from the initial value using the internal 10 volt reference.

5-60

HY-9574
Temperature Coefficients - The temperature coefficients for full-scale calibration, unipolar offset, and
bipolar offset specify the maximum change from the
initial (25 0 C) value to the italue at TMIN or TMAX.

range of analog input values for which a given digital output code will occur. The nominal value of a code width is
equivalent to 1 least significant bit (LSB) of the full scale
range or 2.44mV out of 10 volts for a 12-bit ADC.

Power Supply Rejection - The standard specifications
for the HY-9574 assume use of +5.00 and ±15.00 volt
supplies. The only effect of power supply error on the performance of the device will be a small change in the full
scale calibration. This will result in a linear change in all
lower order codes. The specifications show the maximum
change in calibration from the initial value with the supplies at the various limits.

QUantization Uncertainty - Analog-to-digital converters
exhibit an inherent quantization uncertainty of ±Y2LSB.
This uncertainty is a fundamental characteristic of the
quantization process and cannot be reduced for a converter of given resolution.

Code Width - A fundamental quantity for AID converter
specifications is the code width. This is defined as the

Left-Justified Data - The data format used in the
HY-9574 is left-justified. This means that the data represents the analog input as a fraction of full-scale, ranging
from 0 to~. This implies a binary point to the left of
the MSB. 4096

Applying the HY-9574
For each application of this converter, the ground connections, power supply bypassing, analog signal source,
digital timing and signal routing on the circuit board must
be optimized to assLire maximum performance. These
areas are reviewed in the following sections, along with
basic operating modes and calibration requirements.

Physical Mounting and Layout Considerations
Layout - Unwanted, parasitic circuit components, (L, R
and C) can make 12 bit accuracy impossible, even with a
perfect AID converter. The best policy is to eliminate or
minimize these parasitics through proper circuit layout,
rather than try to quantify their effects.

The recommended construction is a double-sided printed
circuit board with a ground plane on the component side.
Other techniques, such as wire-wrapping or point-topoint wiring on vectorboard, will have an unpredictable
effect on accuracy.
In general, sensitive analog signals should be routed
between ground traces and kept well away from digital
lines. If analog and digital lines must cross, they should do
so at rightangles.
Power Supplies - Supply voltages to the HY-9574 (+15V,
-15V and +5V) must be "quiet" and well regulated. Voltage
spikes on these lines can affect the converter's accuracy,
causing several LSB's to flicker when a constant input is
applied. Digital noise and spikes from a switching power
supply are especially troublesome. If switching supplies
must be used, outputs should be carefully filtered to
assure "quiet" DC voltage at. the converter terminals.

Further, a bypass capacitor pair on each supply voltage
terminal is necessasry to counter the effect of variations in
supply current. Connect one pair from pin 24 to 10
(VLOGIC Supply), one from pin 31 to 5 (VCC to Analog
Common) and one from pin 2 to 5 (VEE to Analog

Common). For each capacitor pair, a 10tJF tantalum type
in parallel with a 0.1tJF ceramic type is recommended.
Ground Connections - Pin 5 (Analog Common) and pin
10 (Digital Common) should be tied together at the
package to guarantee specified performance for the converter. In addition, a wide PC trace should run directly
from pin 5 to (usually) 15V common, and from pin 10 to
(usually) the +5V logiC common. If the converter is located
some distance from the system's "Single point" ground,
make only these connections to pins 5 and 10: Tie them
together at the package, and back to the system ground
with a single path. This path should have low resistance.
(Code dependent currents flow in the VCC, VEE and
VLOGIC terminals, but not through the HY-9574's Analog
Common or Digital Common.

Range Connections And Calibration Procedures
The HY-9574 is a "complete sampling" AID converter,
meaning it can be fully operational with addition of the
power supply voltages, a Start Convert signal, and a few
external components as shown in Figures 2 and 3. Nothing more is required for most applications.
Whether controlled by· a processor or operating in the
stand-alone mode, the HY-9574 offers three standard input ranges: OV to +10V, ±5V and ±10V. The maximum
errors for gain and offset are listed under Specifications. If
required, however, these errors may be adjusted to zero
as explained below. Power supply and ground connections have been discussed in an earlier section.
Unipolar Connections and Calibration - Refer to Figure
2. The "resistors shown are for calibration of offset and
gain. If this is not required, replace R2* with a 50n, 1%
metal film resistor and remove the network on pin' 7.
Connect pin 7 to pin 5. Then ponnect the S/H output to
pin 8 for the OV to 10V range. Inputs to +20V (5V over the
power supply) are no problem for the AID - the converter
operates normally. But the S/H cannot handle inputs
over VCC.

5-61

HY-9574
Calibration consists of adjusting the converter's most
negative output to its ideal value (offset adjustment), then,
adjusting the most positive output to its ideal value (gain
adjustment). To understand the procedure, note that in
principle, one is settling the output with respect to the
midpoint of an increment of analog input, as denoted by
two adjacent code changes. Nominal vaiue of an
increment is one lSB. However, this approach is
impractical because nothing "happens" at a midpoint to
indicate that an adjustment is complete'. Therefore,
calibration is performed in terms of the observable
code changes instead of the midpoint between code
changes.
For example, midpoint of the first lSB increment should
be positioned at the origin, with an output code of all O·s.
To do this, apply an input of +%lSB (+1.22mV for the
10V range). Adjust the Offset potentiometer R1 until the
first code transition flickers between 000000000000 and
0000 0000 0001.
Next, perform a Gain Adjust at positive full scale. Again,
the ideal input corresponding to the last code change is
applied. This is one and one-half (1%) lSB's below
the nominal full scale (+9.9963V for 10V range). Adjust the Gain potentiometer R2,tor flicker between codes
1111 1111 1110 and 1111 1111 1111.

Bipolar Connections and Calibration - Refer to. Figure 3.
The gain and offset errors listed under Specifications may
be adjusted to zero using potentiometers R1 and R2*. If
this isn't required, either or both pots may be replaced by
a 50n, 1°j. metal film resistor.

Connect theS/H output to pin 8 f,or a ±5V range, or to pin
9 fora ±10V range. Calibration of offset and gain is similar
to that for the unipolar ranges as discussed above. First
apply a DC input voltage 'hlSB above negative full scale
(I.e., -4.9988V forthe ±5V range, or-9.9976V for the ±10V
range). Adjust the offset potentiometer R1 for flicker between output codes 0000 0000 0000 and 0000 0000 0001 ;
Next, apply a DC input voltage one and one-half (1 %)
lSB's below positive full scale (+4.9963V for ±5V range;
+9.9927 for ±10V range). Adjust the Gain potentiometer
R2 for flicker between codes 1111 1111 1110 and 1111
11111111.
• The 100n potentiometer R2 provides Gain Adjust for the
10V and 20V ranges. In some applications, a full scale of
10.24V (lSB equals 2.5mV) is more convenient. For these,
replace R2 by a 50n, 1% metal film resistor. Then, to provide Gain Adjust for the 10.24V range, add a 200n potentiometer in series with pin 8.
'

+15V
HY-Y574

\

25

1218

26

CS

27 AD
2B RIC
29 CE
3D SIH CNTL

HY-9574
STS 23

25

1218

28CS

HIGH BITS
19 - 22

27 AD

MIDDLE BITS
15-1B

2B RIC
29 CE

LOW 81TS
11-14

3D SIH CNTL

6

REF IN

4

REF OUT

IDVIN

7

BIP OFF

20V1N 9
+5V 24

7 ,81P OFF

I

+INPUT

+15V 31

I

-15V

32 -INPUT

32 'INPUT
5

ANA COM

SfH OUT

REF IN
REF OUT

STS 23
HIGH BITS
19 - 22'
MIDDLE BITS
15-18
LOW 81TS
11-14

SfH OUT

3

10VIN

8

20VIN

9

+5V 24
+15V 31

I

2

DIG COM 10

5

ANALOG INPUT

+INPUT
ANA COM

-15V

2

DIG COM 10

ANALOG INPUT

FIGURE 2. UNIPOLAR CONNECTIONS

FIGURE 3. BIPOLAR INPUT CONNECTIONS

5-62

HY-9574
NIBBLE BZERO
OVERRIDE

1-;------+

'''BLE~

}-*"------+

'IBBLE C

B

INPut BUfFERS

~....- - - -.. STATUS

STROBE
CLOCK

~--"RESET

BlCIS

FIGURE 4. HY-9574 ADC CONTROL LOGIC

Controlling The HY-9574

Vec

The HY-9574 includes logic for direct interface to most
microprocessor systems. The processor may· take· full
control of each conversion, or the converter may operate
in the "stand-alone" mode, controlled only byl the RIC
input. Full control consists of selecting an 8 or 12 bit
conversion cyc1e, capturing the signal with the S/H,
initiating the conversion, and reading the output data
when ready - choosing either 12 bits at once or 8 followed
by 4, in a left-justified format. The six control inputs are all
TTL/CMOS compatible: (12i8, CS, Ao, SIH, RIC and CE).
Table 1 illustrates the use of these inputs in controlling the
converter's operations. Also, a simplified schematic olthe
internal control logic for the ADC is shown in Figure 4.

Hy.g574
START.
CONVERT

--u-

25

1218

26

CS

27 AD
2B RIC
29 CE

30 SIH CHTL
CONNECT {

6

REF IN

RANGE

4
7

REF OUT
61P OFF

FO~RU::~~~:

r------i
,----1

I +INPUT
32 ·INPUT
5

ANA COM

STS 23
HloH BITS
19-22
MIDDLE BITS
15-16

}

TO 12 BIT
DATA BUS

LOW BITS
11-14
{ ToIOVIN}
OR 20VIN

+5V
+15V 31
·15V

2

DIG COM 10

"Stand-Alone Operation"
The simplest control interface calls for a single control
line connected to RIC as shown in Figure 5. The output
data appears in words of 12 bits each.

+

CONNECT ·INPUT IPIN 321
TO SIH OUT IPIN 31 FOR
NORMAL OPERATION

ANALOG INPUTS

FIGURE 5. GENERAL PURPOSE 12 BIT "STAND ALONE"
CONFIGURATION

5-63

HY",9574
The RIC signal may have any duty cycle within (and
including) the extremes shown in Figures 6 and 7. In
general, data may be read when RIC is high unless STS is
also high, indicating a conversion is in progress. Timing
parameters particular to this mode of operation·are listed
below under "Stand-Alone Mode Timing."

W.-o--r~1
;-I~
_--.....;,---b--t

A Convert Start transition (See Table 1) latches the state
of Ao, which determines whether the conversion
continues for 12 bits (Ao low) or stops with 8 bits (Ao
high). If all 12 bits are read following an 8 bit conversion,
the three LSB's will read zero and DB3 will read ONE. Ao is
latched because it is also involved in enabling the output
buffers (see "Reading the Output Data"). No other control
inputs are latched.
TABLE 1. TRUTH TABLE FOR HY-9S74 CONTROL INPUTS

Ie

STS
SIH CNTL

I::IIHoR

"'..

DATA VALID

FIGURE 6. LOW PULSE FOR RIC AFTER CONVERSION

I

IH&

<

DBll·08O DATA VALID)

I

....Jf..

STS -.,..._---,-_ _

~o!

SIH CNTL

HIGH Z
.

I~
~

IC

l

•

HIGH·Z

~D~AT~A~V~AL~lol)-------------

FIGURE 7. HIGH PULSE FOR RIC - OUTPUTS ENABLED
WITH RIC HIGH, OTHERWISE HIGH-Z

Stand-Alone Mode Timing
SYMBOL

PARAMETER

MIN

tHRL

Low RIC Pulse Width

tDS

STS Delay from RIC

tHOR

Data Valid After RIC Low

tHS

STS Delay After Data Valid

300

tHRH

High RIC Pulse Width

150

tDDR

Data Access Time

TYP

MAX

50
200

CS

0

X

X

1
0
0

1
1

1

j
j

0
0
0
0
0

RIC 1218 Ao
X
X

X
X
X
X
X
X
X
X

X
X

1

1

X

1

0
0

0
1

0
0
0
0
j
j

1

0
1
0
1
0
1

OPERATION
None
None
Initiate 12 bit. conversion
Initiate 8 bit conversion
Initiate 12 bit conversion
Initiate 8 bit conversion
Initiate 12 bit conversion
Initiate 8 bit conversion
Enable 12 bit Output
Enable 8 MSB's Only
Enable 4 LSB's Plus 4
Trailing Zeroes

Conversion Start
Once a signal is captured by the S/H, conversion maybe
initiated as shown in Table 1 bya logic transition onany of
three inputs: CE, CS or RIC. The last of the three to reach
the correct state starts the conversion, so one, two or all
three may be dynamically controlled. The nominal delay
from each is the same, and if necessary, all three may
change state simultaneously. To assure that a particular
input controls the start of conversion, the other two
should be set up at least SOns earlier, however. See the
HY-9574 Timing Specifications, Convert Mode.

UNITS
ns

25

CE

t
t
1
1
1
1

OUTPUTS ENABLED

"'iI=1I . ·Ir------..lI-

DBll.oBD

Conversion Length

ns

This variety of HY-9574 control modes allows a Simple
interface in most system applications. The Convert Start
timing relationships are illustrated in Figure 8.

ns

500

1000

ns
ns

150

ns

The output signal STS indicates status of the converter by
going high only while a conversion is in progress. While
. STS is high, the output buffers remain in a high
impedance state and data ca'tinot be read. Also, an

5-64

HY-9574

CE-_ _ _J ..._ - -

CE----'I

CS--.......I

CS--__I

RIC

RIC

Ao

Ao

STS

sTs----+--JI

0811·080----+------+_

HIGH IMPEOANCE

0811·080-----+-------------

FIGURE 8. CONVERT START TIMING

FIGURE 9. READ CYCLE TIMING

additional Start Convert will not reset the converter or
reinitiate a conversion while STS is high. (However, if Ao
changes state after a conversion begins, an additional
Start Convert signal will latch the new state of Ao,
possibly causing a wrong cycle length (8 vs 12 bits) for
that conversion).

to the least significant bit of the address bus, for storing
the HY-9574 output in two consecutive memory locations.
(With Ao low, the 8 MSB's only are enabled. With Ao high,
4 MSB's are disabled, bits 4 through.7 are forced to zero,
and the 4 LSB's are enabled). This two byte format is
considered "left justified data", for which a decimal (or
binary!) pOint is assumed to the left of byte 1:

Reading The Output Data
BYTE 1

The output data buffers remain in a high impedance state
until four conditions are met: R/C high, STS low, CE high
and CS low. At that time, data lines become active
according to the state of inputs 12/8 and Ao. Timing
constraints are illustrated in Figure 9.
The 12/8 input will be tied high or low in most
applications, though it is fully TTL/CMOS compatible.
With 12/8 high, all 12 output lines become active
simultaneously, for interface to a 12 or16 bitdata bus. The
Ao input is ignored.
With 12/8 low, the output is organized in two 8 bit bytes,
selected one at a time by Ao. This allows an 8 bit data bus
to be connected as shown in Figure 10. Ao is usually tied

Ix
I

MSB

X

X

X

X

BYTE 2
X

X

xlix

X

X

X

0

0

0

01

I
LSB

Further, Ao may be toggled at any time without damage to
the converter. Break-before-make action is guaranteed
between the two data bytes, which assures that the
outputs strapped together in Figure 10 will never be
enabled at the same time.
A read operation usually begins after the conversion is
complete and STS is low. For earliest access to the data
however, the read should begin no later than (too + tHS)
before STS goes low. See Figure 9.

5-65

~

r:r~
0'"'
_LU
,>

 ( 2 3 ' STATUS

(22) MSB 0811

THREE
STATE
BUFFERS
& DIGITAL

+INPUT (1)

12 B'T ADC
-'NPUT (32)

MULTI-

PLEXER

(21)

0810

(20'

DB.

(19'

DB8

(181
(17)

DB'
DB6

(16'

DBS

(15'

DB4

(14'
(13'

DB3
DB2

(12'

DB1

(11) LSD DBO

SIH

(3o, 0 - - - - '

CONTROL

..---....I..--'L-.A(2S' DATA MODE SELECT
+10V
REF.

osc.

CONTROL

LOGIC

1218

(26) CHIP SELECT Cs
(27) BYTE ADDRESS/SHORT CYCLE Ao

(2a' READ CONVERT RIC
' - -_ _ _--Jr---y(291 CHIP ENABLE CE

(3'

SIH
OUTPUT

(a'
10V
INPUT

(91
20V
INPUT

(4'
VREF
OUT

(6'
VREF
IN

(7)

BIPOLAR
OFFSET

5-68

SAMPLING ADC

HY-9674
~

......

Description

CD

The HY-9674 is designed for use in precision, high speed
data acquisition systems. The Harris Sample/Hold
amplifier (HA-5320) and 12 bit A/D converter (HI-674A)
have been combined in a single package to reduce
package count and to insure component compatibility.

provides enhanced AC performance and freedom from
latch-up.
Custom design of each IC (Bipolar Analog and CMOS
Digital) has yielded improved versions of this converter.
The voltage comparator features high PSRR plus a high
speed current-mode latch, and provides precise decisions down to 0.1 LSB of input overdrive. More than 2X
reduction in noise has been achieved by using current
instead of voltage for transmission of all signals between
the analog and digital IC's. Also, the clock oscillator is
current-controlled for excellent stability over temperature. The oscillator is trimmed for a nominal conversion
time of 12 ± 1t1s.

The Sample/Hold (HA-5320) circuit consists of an input
transconductance amplifier capable of providing large
amounts of charging current, a low leakage analog
switch, and an output integrating amplifier. The analog
switch sees virtual ground as its load; therefore, charge
injection on the hold capacitor is constant over the entire
input/output voltage range. The device includes a hold
capacitor, so no external hold capacitor is required.
The Sample and Hold chip (HA-5320) is manufactured
using the Harris Dielectric Isolation process, which
minimizes stray capacitance and eliminates SCR's. This
allows higher speed and latch-free operation.
The 12 bit successive approximation Analog-to-Digital
section is an HA-674A chip set. It includes a +10V
reference, clock, three-state outputs and a digital
interface for microprocessor control. The bipolar analog
die features the Harris Dielectric Isolation process, which

The Sample/Hold and ADC stages are not connected
internally to provide maximum flexibility to the designer.
The HY-9674 offers standard unipolar and bipolar input
ranges, laser trimmed for specified linearity, gain and
offset accuracy. The buried zener reference circuit is
trimmed for minimum temperature coefficient.
Power requirements are ±15V and +5V, with typical
dissipation of 850mW. All models are packaged in a 32 pin
plastic DIP with 600 mil row centers.

Pinout
TOP VIEW

+S/H IN

-S/H IN
+V
S/H CONTROL
CE
R/C
AD

-v
S/H OUT
REF OUT
ANALOG GND
REF IN
B. P. OFF
10V IN
20V IN
DIGITAL GND
DBO (LSB)
DB1
OB2
OB3
DB4
PB5

CS

12ia

VCC (+5V)
STATUS (STS)
DBll
DB10
DB9
DBB
DB7

D86

5-69

enI

>

::I:

HY-9674 System Specifications
Absolute Maximum Ratings
VCC to Digital Common ...................................O to +16.5V
VEE to Digital Common ................................... 0 to -16.5V
VLogic to Digital Common ....................................O to +7V
Analog Common to Digital Common ......................... ±1V
Digital Inputs (CE, CS, A o, 12/8, RIC, S/H)
to Digital Common:.......................-0.5V to VLogic +0.5V
Analog Inputs (REF IN, BIP OFF, 10VIN +IN, -IN)
to Analog Common ............................................... ±16.5V
20VIN to Analog Common ........................................ ±24V

REF OUT ............................. Indeflnite Short to Common,
Momentary Short to VCC
S/H Differential Input Voltage .................................. ±24V
S/H Output Current, Continuous .......................... ±20mA
Storage Temperature ..............................-65 0 C to +150 0 C
Power Dissipation .~............................................. 2560mW
Lead Temperature, Soldering .................................. 1800 C
Thermal Resistance, 6ja ........................................ 390 CIW
6jc ........................................ 140 CIW

* Derate 25.6mWoC above 75 0 C
MIN

TYP

MAX

UNITS

±3

LSB

60

77

100

kHz

±2
±1

LSB
LSB

Maximum Offset Error
12-Blt Throughput Rate (Note 1) 2S 0 C
POWER SUPPLY REJECTION
Maximum change in full scale calibration
+15V ±0.5V
J and A models
All Other Models
-15V ±0.5V

J and A Models
All Other Models

±3
±2

LSB
LSB

+5V ±0.5V

All Models

±'h

LSB

5.0
15.0
-15.0

5.5
16.0
-16.0

Volts
Volts
Volts

7
22
32

15
28
41

mA
mA
mA

POWER SUPPLIES
Operating Voltages
4.5
14.5
-14.5

VLogic
VCC
VEE
Operating Currents
ILogic
ICC (Note 3)
lEE (Note 3)

(In configuration as shown in Figure 1)

ANALOG o---,--+----IS/H IN +
INPUT
S/H OUT
+15V

lOOK

~

S/H IN-

..........,NV'-....+---IREF OUT
'-------+---tREF IN

...--.I\N'---4......--t---IBIP OFF
IOV IN

·15V
HY-9674

FIGURE 1. FOR CALIBRATION INSTRUCTION SEE "RANGE SELECTION AND CALIBRATION PROCEDURES"
SECTION OF THIS DATA SHEET.

5-70

HY-9674 System Specifications

PARAMETER

TEMP

MIN

TYP

-400 C to +85 0 C
25 0 C

±10
1

5

MAX

UNITS

INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance

V
MO

D.C. & TRANSFER ACCURACY SPECIFICATIONS
Resolution (Maximum)
Linearity Error
Differential Linearity Error
J and A Models
All Other Models

-40 o C to +85 0 C

12
±1

Bits
LSB

Full
Full

11
12

Bits
Bits

+5.5
+0.8
-5 (Note 2)
+5 (Note 2)
+0.4

DIGITAL INPUT & OUTPUT CHARACTERISTICS
Input Voltage (High). VIH
Input Voltage (Low). VIL
Input Current (VIL = OV)
Input Current (VIH = +5V)
Logic "0" Output (lSINK = 1.6mA)
Logic "1" Output (ISOURCE = 500pA)
Leakage Current (High Z State, DBO-11 Only)

Full
Full
Full
Full
Full
Full
Full

+2.4
-0.5

0.1

+5

V
V
pA
pA
V
V
pA

22
32
7

+16.0
-16.0
+5.5
28
41
15

V
V
V
mA
mA
mA

25 0 C
25 0 C

±2
±1

LSB
LSB

25 0 C
250 C

±2
±1

LSB
LSB
mW

15
10
600
1.5

ps
ps
ns
p.s
ns
ns
pV/p.s
pV/ps
kHz
kHz

+2.4
-5

POWER SUPPLY CHARACTERISTICS
Positive Supply Voltage
Negative Supply Voltage
Logic Supply Voltage
Positive Supply Current (Note 3)
Negative Supply Current (Note 3)
Logic Supply Current
Power Supply Rejection V+ (Note 10)
J & A Models
All Other Models·
Power Supply Rejection V- (Note 10)
J & A Models
All Other Models
Power Dissipation

+14.5
-14.5
+4.5

850

TIMING SPECIFICATIONS
Conversion Time

12 Bit Cycle
8 Bit Cycle
STS Delay After Data Valid
S/H Acquisition Time (0.01%)
Aperture Time
Aperture Uncertainty
Droop Rate
Throu9hput Rate (Note 1) 12 Bit
8 Bit

+25 0 C
+25 0 C
+250 C
+25 0 C
+25 0 C
+25 0 C
+25 0 C
-40 0 C to +85 oC
+25 0 C
+25 0 C

5-71

9
6
100

12
8
300
1.0
25
0.3
0.08
17

60
87

77
110

0.5
100
100
140

HY-9674 Sample And Hold AmplifierSpecifications
Electrical Characteristics
VSuppl y

Test Conditions (Unless otherwise specified)

= ±15V; CH - Internal; Digital Input (Pin 14), VAL = +O.8V (Sample), VAH = +2.0V (Hold).
-40 o C ::; T A ::; 85 0 C

OPERATING TEMP RANGE
PARAMETER

TEMP

MIN

TYP

Full
25 0 C
25 0 C
25 0 C
Full
25 0 C
Full
25 0 C
Full
Full
25 0 C
Full

±10
1

5

25 0 C

106

OoC::; TA::; 750 C

MAX

MIN

TYP

±10
1

5

MAX

UNITS

INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Capacitance
Offset Voltage
Bias Current
Offset Current
Common Mode Range
CMRR (Note 4)
Offset Voltage T.C.

0.2
70
30
±10
80

90
5

3
0.5
2.0
200
200
100
100

0.5
100
30
±10
72

15

90
5

3
1.0
1.5
300
300
300
300

20

V
MO
pF
mV
mV
nA
nA
nA
nA
V
dB
/1V/oC

TRANSFER CHARACTERISTICS
Gain, dC
Gain Bandwidth PFOduct (Note 5)
CH = 100pF

25 0 C

3 x 105

2 x 106
2.0

2 x 106

V/V

2.0

MHz

600
1.0

V
mA
kHz
0

OUTPUT CHARACTERISTICS
Output Voltage
Output Current
Full Power Bandwidth (Note 6)
Output Resistance (Hold Mode)
Total Output Noise, DC to 10MHz
Sample
Hold

Full
25 0 C
25 0 C
25 0 C

±10
±10

±10
±10
600
1.0

25 0 C
25 0 C

125
125

25 0 C
25 0 C
25 0 C

100
15
45

200
200

125
125

200
200

/1V RMS
/1V RMS

TRANSIENT RESPONSE
Rise Time (Note 5)
Overshoot (Note 5)
Slew Rate (Note 7)

100
15
45

ns
%
V//1S

DIGITAL INPUT CHARACTERISTICS
Input
Input
Input
Input

Voltage
Voltage
Current
Current

(High), VAH
(Low), VAL
(VAL = OV)
(V AH = +5V)

Full
Full
Full
Full

2.0

2.0
0.8
4
0.1

0.8
4
0.1

V
V
/1A
/1A

SAMPLE/HOLD CHARACTERISTICS
Acquisition Time (0.1%) (Note 7)
Acquisition Time (0.01%) (Note 7)
Aperture Time (Note 8)
Effective Aperture Delay Time
(See S/H Glossary)
Aperture Uncertainty
Hold Capacitor, CH
Droop Rate
Droop Rate
Drift Current (Note 9)
Drift Current (Note 9)
Charge Transfer (Note 9)
Hold Mode Settling Time (0.01%)
Hold Mode Feedthrough
10Vp-p, 100kHz

25 0 C
25 0 C
25 0 C
25 0 C

-50

25 0 C

0.8
1.0
25
-25
0.3
100
0.08
2.4
8
0.24
0.1
165
2

25 0 C
Full
25 0 C
Full
25 0 C
Full
Full

1.2
1.5
0

-50

0.8
1.0
25
-25
0.3
100
0.08
1.2
8
0.12
0.1
165
2

0.5
100
50
10
0.5
250

1.2
1.5
0

0.5
100
50
10
0.5
250

/1S
/1S
ns
ns
ns
pF
/1V//1S
/1V//1S
pA
nA
pC
ns
mV

POWER SUPPLY CHARACTERISTICS
Power Supply Rejection V+
(Note 10) V-

Full
Full

80
65

80
65

5-72

dB
dB

HY-9674 Analog-to-Digital Converter Specifications
DC and Transfer Accuracy Specifications
(Typical @ +25 0 e with Vee

~

+15V, VLOGle

~

+5V, VEE

~

-15V unless otherwise specified)
TEMPERATURE RANGE DOC to +75 0 C

HY-9674J

HY-9674K

HY-9674L

UNITS

12

12

12

Bits

±1
±1

±1/2
±1/2

±1/2
±1/2

LSB
LSB

(Max. resolution for which no missing codes is guaranteed)
2S oC
TMIN to TMAX

11
11

12
12

12
12

Bits
Bits

Unipolar Offset (Max.) (Adjustable to zero)

±2

±2

±2

LSB

Bipolar Offset (Max.) (Adjustable to zero)

±10

±4

±4

LSB

2S 0 C (Max.), with fixed son resistor from
REF OUT to REF IN (Adjustable to zero)

0.3

0.3

0.3

% of Full Scale

TMIN to TMAX
(No adjustment at +2S 0 C)
(With adjustment to zero at +2S 0 C)

O.S
0.22

0.4
0.12

0.3S
O.OS

% of Full Scale
% of Full Scale

MODEL

Resolution (Maximum)
LINEARITY ERROR
2S o C (Maximum)
ooC to +7S o C (Maximum)
DIFFERENTIAL LINEARITY ERROR

FULL SCALE CALIBRATION ERROR

~

Cl~
'e:

Ew
,>

<{z
Cl

(,,)

TEMPERATURE COEFFICIENTS
Guaranteed max change to TMIN or TMAX (Using internal ref.)
Unipolar Offset
Bipolar Offset
Full Scale Calibration

±2
(10)
±2
(10)
±9
(4S)

±1
(S)
±1
(S)
±S
(2S)

±1
(S)
±1
(S)
±2
(10)

LSB
(ppm/OC)
LSB
(ppm/OC)
LSB
(ppm/oC)

±2
±1/2
±2

±1
±1/2
±1

±1
±1/2
±1

LSB
LSB
LSB

POWER SUPPLY REJECTION
Max. change in Full Scale Calibration
+13.SV < VCC < +16.S or +11.4V < VCC < +12.6V
+4.5V < VLOGIC < +S.SV
-16.5V < VEE < -13.SV or -12.6V < VEE < -11.4V
ANALOG INPUT RANGES
Bipolar

Unipolar

-S to +S
-10 to +10

Volts
Volts

o to +10
o to +20

Volts
Volts

SK, ± 2S%
10K, ± 2S%

Ohms
Ohms

+10.0±0.1 Max
2.0 Max.

Volts
mA

INPUT IMPEDANCE
10 Volt Span
20 Volt Span
INTERNAL REFERENCE
Voltage
Output Current
available for external loads (External load should not
change during conversion.

5..,73

HY-9674 Ahalog-to-Digital Converter
DC and Transfer Accuracy Specifications
(Typical @ +25 0 e with Vee = +15V, VLOGle = +5V, VEE = -15V unless otherwise specified)
TEMPERATURE RANGE -40 0 C to +85 0 C
MODEL

HY-9674A

HY-9674B

UNITS

12

12

Bits

±1
±1

±1/2
±1

LSB
LSB

11
11

12
12

Bits
Bits

Unipolar Offset (Max,) (Adjustable to zero)

±2

±2

LSB

Bipolar Offset (Max,) (Adjustable to zero)

±10

±4

LSB

0,3

0,3

% of Full Scale

0,8
0.5

0.6
0.25

% of Full Scale
% of Full Scale

±2
(5)
±4
(10)
±20
(50)

±1
(2.5)
±2
(5)
±10
(25)

LSB
(ppm/OC)
LSB
(ppm/OC)
LSB
(ppm/OC)

±2
±1/2
±2

±1
±1/2
±1

LSB
lSB
LSB

Resolution (Maximum)
LINEARITY ERROR
25 0 C (Maximum)
-40 0 C ::; T A::; 85 0 C (Maximum)
DIFFERENTIAL LINEARITY ERROR
(Max, resolution for which no missing codes is guaranteed)
25 0 C
TMIN to TMAX

FULL SCALE CALIBRATION ERROR
25 0 C (Max,), with fixed 500 resistor from
REF OUT to REF IN (Adjustable to zero)
TMIN to TMAX
(No adjustment at +25 0 C)
(With adjustment to zero at +25 0 C)
TEMPERATURE COEFFICIENTS
Guaran,teed max change to TMIN or TMAX (Using internal ref.)
Unipolar Offset
Bipolar Offset
Full Scale Calibration

POWER SUPPLY REJECTION
Max. change in Full Scale Calibration
+13.5V < VCC < +16.5 or +11.4V < VCC < +12.6V
+4.5V < VLOGIC < +5.5V
·16.5V < VEE < -13.5V or -12.6V < VEE < -11.4V
ANALOG INPUTS, INPUT RANGES
Bipolar

Unipolar

-5 to +5
-10 to +10

Volts
Volts

o to +10
o to +20

Volts
Volts

5KO, ± 25%
10KO, ± 25%

Ohms
Ohms

INPUT IMPEDANCE
10 Volt Span
20 Volt Span

,

INTERNAL REFERENCE
Voltage
Output Current
available for external loads (External load should not
change during conversion.

+10.0 ± 0,1 Max.
2.0 Max.

5-74

Volts
mA

HY-9674 Analog-to-Digital Converter Specifications

,....

"'it

Digital Characteristics (Note 11)

CD

+2AV (Note 12)
-0.5V
-SJ1A

Logic Outputs (DB11-DBO, STS)
Logic "0" (ISINK - 1.6mA)
Logic "1" (lSOURCE - SOOJ1A)
Leakage (High - Z State, DB11-DBO Only)
Capacitance

I

>

+S.SV
+O.SV
+SJ1A

0.1J1A
SpF

+OAV
+2AV
-SJ1A

= (tacq + tconv)-t, see Harris Application Note 538.

7. Vo

2. Conventional current flowing into the package is designated "+",
current flowing out is "-".
3. Supply current specified for a OV differential between pins 1 and 32.
Supply current will increase with differential input (as may occur in the
Hold Mode) to approximately +39mA and -49mA at 20V.
4. VCM = ±5VDC
5. Vo
6. Vo

CJ)

MAX

J:

Logic Inputs (CE, CS, R/C, Ao, 12/8)
Logic "1"
Logic "0"
Current
Capacitance

NOTES:
1. Maximum T.R.

TYP

MIN

(ALL MODELS, OVER FULL TEMPERATURE RANGE)

= 200mVp-p; RL = 2kO; CL = 50pF.
= 20Vp-p; RL = 2kO; CL = 50pF; Unattenuated output.

0.1J1A
SpF

+SJ1A

= 10V step; RL = 2kO; CL = 50pF.

8. Derived from computer simulation only, not tested.
9. VIN = OV, VAH =+3.5V, tr < 20ns (VIL to VIH)·
10. Based on a one volt delta in each supply, I.e. 15V ± O.5VDC.
11. See "HY-9674 ADC Timing Specifications" for a detailed listing of
digital timing parameters.
12. Although this guaranteed threshold is higher than standard TTL
(+2.0V), bus loading is much less, i.e., typical input current is only
0.25% of a TTL load.

Sample/Hold Amplifier Performance Curves

VSUPPLY ~ ±15VDC

I'

DRIFT CURRENT

VB.

TEMPERATURE

OPEN LOOP GAIN AND PHASE RESPONSE

eN' 100pf. INTERNAL

120

1000.0

.......

"'.......

100
100.0

::

~

"'-

80,,-

~

10.0

1.0

OAIN. dB

/

·25

/

/

45

.......

.......

60

q,

.......

"'-....... 0

40

""".......

20

0

+25 +50 +75 +100 +125
TEMPERATURE. DC

PEDESTAL
30 .-

10

IK

10K

FRfOUENCV!Hzl

VB.

LOGIC (VAH) VOLTAGE
CH: lOOpf. !NHANAL

25

20

1.5

10

100

L -____~-----.-----_+----~~--

VAH IVOlTSl

5-75

gO

........

lOOK

"

T

"'"

1M

\
\
\

135
180

10M

PHASE.
OEOREES

HY-9674 Sample/Hold Test Circuits
CHARGE TRANSFER AND DRIFT CURRENT

32

·INPUT
SfH OUTPUT 1-....--1-0

.----~ +INPUT

Vo

HY·9674
SfH
CONTROL
INPUT

DRIFT CURRENT TEST

CHARGE TRANSFER TEST

1. Observe the voltage "droop", :'Yof:'T:

1. Observe the "pedestal" voltage Yp:

SfH
CONTROL
VO

SfH
r---1""--' - CONTROL - . .
L.J
L-

,.,

-oJ

-

,...,- - - HOLO 1+3.5V!
I-...J L - SAMPLE IOVI

h ih

+V

Vo --""'----

-

t

HOLD (+3.5V!
SAMPLE (OV!

.,....,....;. - ;;.:: - - :. Vo

'" : "i- - -t-

p -

---I.:.T I I

I

2. Measure the slope of the output during hold, :'YoI:'T, and compute
drift current: ID = CH :'YoI:'!'

2. Compute charge transfer: Q = YpCH

S/H HOLD MODE FEEDTHROUGH ATTENUATION
ANALOG
MUX OR
SWITCH
IOVpp
10kHz
SINE WAVE

r.::..

.E...
I

\;::.,I

+INPUT

~

~
S/H
CONTROL
INPUT
HOLO

SfH OUTPUT
SfH CONTROL
VCC

AIN

31

ANALOG
GND

VEE

2

5

,."

V+

----r--\

SAMPLE - - . /

HY-9674
·INPUT

,."

FEEOTHROUGH (dB!

= 20 Log

"--

VOUT
VIN

WHERE VOUT = VOLTS pp. Hold Mode
VIN = VOLTS pp

5-76

TO SUPPLY
COMMON

V·

3

VOUT

HY-9674
Glossary of Terms
Sample and Hold
Acquisition Time - The time required following a
"sample" command, for the output to reach its final value
within ±0.1% or ±0.01%. This isthe minimum sample time
required to obtain a given accuracy, and includes switch
delay time, .slewing time and settling time.
Charge Transfer - The small charge transferred to the
holding capacitor from the inter-electrode capacitance of
the switch when the unit is switched to the Hold Mode.
Charge transfer is directly proportional to sample-to-hold
offset pedestal error, where:

Charge Transfer (pC) = CH (pF) x Offset Error (V)
Aperture Time - The time required for the sample-andhold switch to open, independent of delays through the
switch driver and input amplifier circuitry. The switch
opening time is that interval between the conditions of
10% open and 90% open.
Hold Step Error - The output error due .to Charge
Transfer (see above). It may be calculated from the specified parameter, Charge Transfer, using the following
relationship:
.
Charge Transfer (pC)
Hold Step (V) =
100pF

SeeSample/Hold Amplifier Performance Curves.
Effective Aperture Delay Time (EADT) - The difference
between propagation time froni the analog Input to the
S/H switch, and digital delay time between the Hold command and opening of the switch.

EADT may be positive, negative or zero. If zero, the S/H
amplifier will output a voltage equal to VIN at the instant
the Hold command was received. For negative EADT, the
output in Hold (exclusive of pedestal and droop errors will
correspond to a value of VIN that occurred betor!! the
Hold command.
Aperture Uncertainty - The range of variation in Effective Aperture Delay Time. Aperture Uncertainty (also
called Aperture Delay Uncertainty, Aperture Time Jitter,
etc.) sets a "limit on the accuracy with which a waveform
can be reconstructed from sample data:
Drift Current - The net leakage current from the hold
capacitor during the hold mode. Drift current can be
calculated from the droop rate using the formula:

ID (pA) = CH (pF) x -

il.V

(Volts/sec)

il.T

.Analog/Dlgltal Converter
Linearity Error - Linearity error refers to the deviation of
each individual code from a line drawn from "zero"
through "full scale". The point used as "zero" occurs

'hLSB (1.22mV for 10 volt span) before the first code transition (all zeros to only the LSB "on"). "Full scale" is
defined as a level one and one-half (1 'h) LSB's beyond the
last code transition (to all ones). The deviation of a code
from the true straight line is measured from the middle of
each particular code.
The HY-9674K, L, and B grades are guaranteed for
maximum nonlinearity of ±'hLSB. For these grades, this
means that an analog value which falls exactly in the
center of a given code width will result in the correct
digital output code. Values nearer the upper or lower
transition of the code width may produce the next upper
or lower digital output code. The HY-9674J and A grades
are guaranteed to ±1 LSB maximum error. For these
grades, an analog value which falls within a given code
width will result in eitHer the correct code for that region
or either adjacent one. Note that the linearity error is not
user-adjustable.
.
Differential Linearity Error (No Milling Codes) - A
specification which guarantees no missing codes
requires that every code combination appear In a
monotonic increasing sequence as the analog input level
is increased. Thuseverycode must have a finite width. For
the HY-9674K, L, and B grades, which guarantee no missing codes to 12-bit resolution, all 4096 codes must be
present overthe entire operating temperature ranges. The
HY-9674J and A grades guarantee no missing codes to
11-bit resolution over temperature; this means that all
code combinations of the upper 11 bits must be present;
in practice very few of the 12-bit codes are missing.
Unipolar Offset - The first transition should occur at a
level' 'hLSB above analog common. Unipolar offset is
defined as the deviation of the actual transition from that
point. This offset can be adjusted as discussed on the following pages. The unipolar offsettemperatur~ coefficient
specifies the maximum change of the transition point over
temperature, with or without external adjustment.
Bipolar Offset- Similarly, in the bipolar mode, the major
carry transition (0111 1111 1111 to 1000 0000 0000)
should occur for an analog value 'hLSB below analog
common. The bipolar offset error and temperature
specify the initial deviation and maximum change in the
error over temperature.
Full Scale Calibration Error - The last transition (from
1111 1111 1110 to 1111 1111 1111) should occur for an
analog value one and one-half (1 'h) LSB's below the nominal full scale (9.9963 volts for 10,000 volts full scale). The
full scale calibration error is the deviation of the actual
level at the last transition from the ideal level. This error,
which is typically 0.05toO.1% offull scale, can betrimmed
out as shown in Figures 2 and 3. The full scale calibration
error over temperature is given with and without the initial
error trimmed out. The temperature coefficients for,.each
grade indicate the maximum change in the full scale gain
from the initial value using the internal 10 volt reference.

5-77

HY-9674
Temperature Coefficients - The temperature coefficients for full-scale calibration, unipolar offset, and
bipolar offset specify the maximum change from the
initial (25 0 C) value to the value at TMIN or rMAX.

range of analog input values for which a given digital output code will occur. The nominal value of a code width is
equivalent to 1 least significant bit (LSB) of the full scale
range or 2.44mV out of 10 volts for a 12-bit ADC.

Power Supply Rejection - The standard' specifications
for the HY-9674 assume use of +5.00 and ±15.00 volt
supplies. The only effect of power supply error on the performance of the device will be a small change in the full
scale calibration. This will result in a linear change in all
lower order codes. The specifications show the maximum
change in calibration from the initial value with the supplies at the various limits.

Quantization Uncertainty - Analog-to-digital converters
exhibit an inherent quantization uncertainty of ±'hLSB.
This uncertainty is a fundamental characteristic of the
quantization process and cannot be reduced for a converter of given resolution.

Code Width - A fundamental quantity for AID converter

specifications is the code width. This is defined as the

The data format used in the
HY-9674 is left-justified. This means that the data represents the analog input as a fraction of full-scale, ranging
from 0 to 4095 . This implies a binary point to the left of
the MSB. 4096
Left·Justlfled Data -

Applying the HY-9674
For each application of this converter, the ground connections, power supply bypassing, analog Signal source,
digital timing and signal routing on the circuit board must
be optimized to assure maximum performance. These
areas are reviewed in the following sections, along with
basic operating modes and calibration requirements.

Physical Mounting and Layout Considerations
Layout - Unwanted, parasitic circuit components, (L, R
and C) can make 12 bit accuracy impossible, even with a
perfect AID converter. The best policy is to eliminate or
minimize these parasitics through proper circuit layout,
rather than try to quantify their effects.

The recommended construction is a double-sided printed
circuit board with a ground plane on the component side.
Other techniques, such as wire-wrapping or point-topOint wiring on vectorboard, will have an unpredictable
effect on accuracy.
In general, sensitive analog signals should be routed
between ground traces and kept well away from digital
lines. If analog and digital lines must cross, they should do
so at right angles.
Power Supplies - Supply voltages to the HY-9674 (+15V,
-15V and +5V) must be "quiet" and well regulated. Voltage
spikes on these lines can affect the converter's accuracy,
causing several LSB's to flicker when a constant input is
applied. Digital noise and spikes from a switching power
supply are especially troublesome. If switching supplies
must be used, outputs should be carefully filtered to
assure "quiet" DC voltage at the converter terminals.

Further, a bypass capacitor pair on each supply voltage
terminal is necessasry to counter the effect of variatiOnS in
supply current. eonnect one pair from pin 24 to 10
(VLOGIC Supply), one from pin 31 to 5 (VCC to Analog
Common) and one from pin 2 to 5 (VEE to Analog

Common). For each capacitor pair, a 10pF tantalum type
in parallel with a 0.1pF ceramic type is recommended.
Ground Connections - Pin 5 (Analog Common) and pin
10 (Digital Common) should be tied together at the
package to guarantee specified performance for the converter. In addition, a wide PC trace should run directly
from pin 5 to (usually) 15V common, and from pin 10 to
(usually) the +5V logiC common. If the converter is located
some distance from the system's "single point" ground,
make only these connections to pi;'s 5 and 10: Tie them
together at the package, and back to the system ground
with a single path. This path should have low resistance.
(Code dependent currents flow in the VCC, VEE and
VLOGIC terminals, but not through the HY·9674's Analog
Common or Digital Common.

Range Connections And Calibration Procedures
The HY-9674is a "complete sampling" AID converter,
meaning it can be fully operational with addition of the
power supply voltages, a Start Convert signal, and a few
external components as shown in Figures 2 and 3. Noth·
ing more is required for most applications.
Whether controlled by a processor or operating in the
stand-alone mode, the HY·9674 offers three standard input ranges: OV to, +10V, ±5V and ±10V. The maximur)1
errors for gain and offset are listed under Specifications. If
required, however, these errors may be adjusted to zero
as explained below. Power supply and ground connections have been discussed in an earlier section.
Unipolar Connections and Cal,lbratlon - Refer to Figure
2. The resistors showh are for calibration of offset and
gain. If this is not required, replace R2' with a 50n, 1%
metal film resistor and remove the network on pin 7.
Connect pin 7 to pin 5. Then connect the S/H output to
pin 8 for the OV to 10V range. Inputs to +20V (5V over the
power supply) are no problem fof the AID - the converter
operates normally. But the S/H cannot handle inputs
over VCC.

5-78

HY-9674
Calibration consists of adjusting the converter's most
negative output to its ideal value (offset adjustment), then,
adjusting the most positive output to its ideal value (gain
adjustment). To understand the procedure, note that in
principle, one is settling the output with respect to the
midpoint of an increment of analog input, as denoted by
two adjacent code changes. Nominal value of an
increment is one LSB. However, this approach is
impractical because nothing "happens" at a midpoint to
indicate that an adjustment is complete. Therefore,
calibration is performed in terms of the observable
code changes instead of the midpoint between code
changes.
For example, midpoint of the first LSB increment should
be positioned at the origin, with an output code of all O's.
To do this, apply an input of +'I2LSB (+1.22mV for the
10V range). Adjust the Offset potentiometer R1 until the
first code transition flickers between 0000 0000 0000 and
000000000001.
Next, perform a Gain Adjust at positive full scale. Again,
the ideal input corresponding to the last code change is
applied. This is one and one-half (1 '12) LSB's below
the nominal full scale (+9.9963V for 10V range). Adjust the Gain potentiometer R2 for flicker between codes
1111 1111 1110 and 11111111 1111.

Bipolar Connections and Calibration - Refer to Figure 3.

The gain and offset errors Iisted under Specifications may
be adjusted to zero using potentiometers R1 and R2*. If
this isn't required, either or both pots may be replaced by
a 50n, 1% metal film resistor.

o:t
,....
CD

enI

>
~

Connect the S/H output to pin 8 for a ±5V range, or to pin
9 for a ±10V range. Calibration of offset and gain is similar
to that for the unipolar ranges as discussed above. First
apply a DC input voltage 'I2LSB above negative full scale
(i.e., -4.9988V for the ±5V range, or -9.9976V for the ±10V
range). Adjust the offset potentiometer R1 for flicker between output codes 0000 0000 0000 and 0000 0000 0001.
Next, apply a DC input voltage one and one-half (1 '12)
LSB's below positive full scale (+4.9963V for ±5V range;
+9.9927 for ±10V range). Adjust the Gain potentiometer
R2 for flicker between codes 1111 1111 1110 and 1111
11111111.
* The 1oon potentiometer R2 provides Gain Adjust for the
10V and 20V ranges. In some applications, a full scale of
10.24V (LSB equals 2.5mV) is more convenient. Forthese,
replace R2 by a 50n, 1% metal film resistor. Then, to provide Gain Adjust for the 10.24V range, add a 200n potentiometer in series with pin 8.
!@

9~
Ew
,>
«2
o
c...:o

+15V

HY·9674

HY·9674
25

1218

26

Cs

27 AD
28 RIC
29 CE
30 S/H CNTL

STS 23

25

1218

HIGH 81TS
19 - 22

26

Cs

REF IN

S/H OUT

3

4

REF OUT

10VIN

8

7

81P OFF

20VIN 9
+5V 24

I

+INPUT

+15V 31

32 ·INPUT
ANA COM

28 RIC
29 CE
30 S/H CNTl

LOW BITS
11 -14

6

5

27 AD

MIDDLE 81TS
15 - 18

·15V

6

I

REF IN

5

ANALOG INPUT

MIDDLE 8ITS
15-18
LOW 81TS
11-14
S/H OUT

3

REF OUT

10VIN

8

81P OFF

20VIN 9
+5V 24

+INPUT

+15V 31

32 ·INPUT

2

DIG COM 10

STS 23
HIGH 81TS
19 - 22

·15V

::::t.
TO IOVIN
OR 20VIN

2

ANA COM

ANALOG INPUT

FIGURE 2. UNIPOLAR CONNECTIONS

FIGURE 3. BIPOLAR INPUT CONNECTIONS

5-79

HY-9674

NIBBLE BZERO
OVERRIDE

r--t------ NIBBLE A. B
INPUT BUFfERS

r--....- - - - .>0.......- - - _

NIBBLEC

STATUS

BTROBE
CLOCk

}o--_RESET

EOCI3

FIGURE 4. HY-9674 ADC CONTROL LOGIC

Controlling The HY-9674

VCC

The HY-9674 include.s logic for direct interface to most
microprocessor systems. The processor may take full
control of each conversion, or the converter may operate
in the "stand-alone" mode, controlled only by the RIC
input. Full control consists of selecting an B or 12 bit
conversion cycle, capturing the .signal with the S'/H,
initiating the conversion, and reading the output data
when ready - choosing either 12 bits at once orB followed
by 4, in a left-justified format. The six control inputsareall
TTUCMOS compatible: (12/8, CS, A o, S/H, RIC and GEl.
Table 1 illustrates the use of these inputs in controlling the
converter's operations. Also, a simplifiep sohematic of the
internal control logic for the ADC is shown in Figure 4.

START
CONVERT

I.....J

.-

"Stand-Alone Operation"
The simplest control interface calls for a single control
line connected to RIC as shown in Figure 5. The output
data appears in words of 12 bits each.

CONNECT ·INPUT (PIN al(
TO 8/H OUT (PIN 3) FOR

NORMAL OPERATION

ANALOG INPUTS

FIGURE 5. GENERAL PURPOSE 12 BIT "STAND ALONE"
CONFIGURATION

5-80

HY-9674
The RIC signal may have any duty cycle within (and
including) the extremes shown in Figures 6 and 7. In
general, data may be read when RIC is high unless STS is
also high, indicating a conversion is in progress. Timing
parameters particular to this mode of operation are listed
below under "Stand-Alone Mode Timing."

RIC

STS-~r-·:--tOS--J-fll~_tc-;--~~I
b-I
6

S/H CNTL

tHOR

•

tHS.

0811·080 DATHALlO>

•

<

OAT'-A-V-AL-IO-

Conversion Length
A Convert Start transition (See Table 1) latches the state
of Ao , which determines whether the conversion
continues for 12 bits (Ao low} or stops with 8 bits (Ao
high). If al112 bits are read following an 8 bit conversion,
the three LSB's will read zero and DB3wili read ONE. Ao is
latched because it is also involved in enabling the output
buffers (see "Reading the Output Data"). No other control
inputs are latched.
TABLE 1. TRUTH TABLE FOR HY-9674 CONTROL INPUTS

",en
I

STS
S/H CNTL

-

OUTPUTS ENABLED

I

0
X

X

X

X

X

1
0

X

X
X

X

None

0

Initiate 12 bit conversion

a
I

1

Initiate 8 bit conversion

X

0

Initiate 12 bit conversion

1

j

a
a
a

X

1

X

1

Initiate 8 bit conversion

1

a
a
a
a
a

I

X

0

Initiate 12 bit conversion

j
1
1
1

X
1

1

Initiate 8 bit conversion

,

1
1
tos

~~

t

·1

f·

.I

tc'

HtGH·Z

DATA VALID

FIGURE 7. HIGH PULSE FOR RIC - OUTPUTS ENABLED
WITH RIC HIGH, OTHERWISE HIGH-Z

Stand-Alone Mode Timing
SYMBOL

PARAMETER

MtN

tHRL

Low RIC Pulse Width

tDS

STS Delay from Ric

tHOR

Data Valid After RIC Low

tHS

STS Delay After Data Valid

100

tHRH

High RIC Pulse Width

150

tDDR

Data Access Time

TYP

MAX

200

1
1

0

a
a

Ao

OPERATION

None

X

Enable 12 bit Output

0

Enable 8 MSS's Only

1

Enable 4 LSS's Plus 4
Trailing Zeroes

Conversion Start
Once a signal is captured by the S/H, conversion may be
initiated as shown in Table 1 by a logic transition on any of
three inputs: CE, CS or RIC. The last of the three to reach
the correct state starts the conversion, so one, two or all
three may be dynamically controlled. The nominal delay
from each is the same, and if necessary, all three may
change state simultaneously. To assure that a particular
input controls the start of conversion, the other two
should be set up at least 50ns earlier, however. See the
HY-9674 Timing Specifications, Convert Mode.

UNtTS

This variety of HY-9674 control modes allows a simple
interface in most system applications. The. Convert Start
timing relationships are illustrated in Figure 8.

ns

50

,

CS

I
FIGURE 6. LOW PULSE FOR RIC
AFTER CONVERSION

RIC 12/8

CE

ns
ns

25
300

600

The output signal STS indicates status of the converter by
going high only while a con.version is in progress. While
STS is high, the output buffers remain in a high
impedance state and data cannot be read. Also, an

ns
ns

150

ns

5-81

HY-9674

CE

CE

CS

CS

RIC

RIC

Ao

Ao

STS
STS

HIGH IMPEDANCE
OBI1·0BO-----+-------------

OBI1·0BO

FIGURE 8. CONVERT START TIMING

additional Start Convert wi" not reset the converter or
reinitiate a conversion while STS is high. (However, if Ao
changes state after a conversion begins, an additional
Start Convert signal wi" latch the new state of Ao,
possibly causing a wrong cycle length (8 vs 12 bits) for
that conversion).

to the least significant bit of the address bus, for storing
the HY-967 4 output in two consecutive memory locations.
(With Ao low, the 8 MSB's only are enabled. With Ao high,
4 MSB's are disabled, bits 4 through 7 are forced to zero,
and the 4 LSB's are enabled). This two byte format Is
considered "left justified data", for which a decimal (or
binaryl) point is assumed to the left of byte 1:

Reading The Output Data
BYTE 1

The output data buffers remain in a high impedance state
until four conditions are met: R/~ high, STS low, CE high
and CS low. At that time, data lirles become active
according to the. state of inputs 12/8 and Ao. Timing
constraints are illustrated in Figure 9.
The 12/8 input will be tied high or low in most
applications, though it is fully TTUCMOS compatible.
With 12/8 high, a" 12 output lines become active
simultaneously, for interface to a 12 or 16 bit data bus. The
Ao input is ignored.
With 12/8 low, the output is organized in two 8 bit bytes,
selected one at a time by Ao. This allows an 8 bit data bus
to be connected as shown In Figure 10. Ao is usually tied

Ix x x x x x x x

I
MSB

BYTE 2

II x

x x x
I

0

0

0

0 \'

LSB

Further, Ao may be toggled at any time without da"llage to
the converter. Break-before-make action is guaranteed
between the two data bytes; which assures that the
outputs strapped together in Figure 10 wi" never be
enabled at the same time.
A read operation usually begins after the conversion is
complete and STS is low. For earliest access to the data
however, the read should begin no later than (too + tHS)
before STS goes low. See Figure 9.

5-82

HY-9674
HY-9674 ADC Timing Specifications at +250C *
SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

100

200

ns
ns
ns
ns
ns
ns
ns
ns
IJS
JiS

CONVERT MODE
tosc
tHEC
tssc
tHSC
tSRC
tHRC
tSAC
tHAC
tc

STS Delay from CE
CE Pulse Width
Cs to CE Setup
Cs Low during CE High
Ric to CE Setup
RIC Low during CE High
Ao to CE Setup
Ao Valid during CE High
Conversion Time, 12-Bit Cycle**
a-Bit Cycle **

30

50
50
50
50
50
0
50

20
20
0
20
0
20
12
a

9
6

15
10

READ MODE
too
tHO
tHL
tSSR
tSRR
tSAR
tHSR
tHRR
tHAR
tHS

Access Time from CE
Data Valid after CE Low
Output Float Delay
CS to CE Setup
RIC to CE Setup
Ao to CE Setup
CS Valid after CE Low
RIC High after CE Low
Ao Valid after CE Low
ST-S Delay after Data Valid

75
35
100
0
0
25
0
0
25
300

25
50
0
50
0
0
50
100

150
150

600

..
..
* Time IS measured from 50% levelof digital transitions .
** Tmin to Tmax

\

ADDRESS BUS

Au
'"I"

F
27

lui

STS
DBllINSB)

~
22

21
2D

Au

19
lB

HY·9674

17

16
15

~
13
12

DaD ILSB)
DIGITAL COMMON

n
11

FIGURE 10. INTERFACE TO AN B-BIT DATA BUS

5-83

DATA
BUS

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

HY·94741/742
Low Power Sampling 12 Bit AID
Converter With 8/16 Bit,uP Interface

PRELIMINARY
Features

HY-94741

• Pin for Pin Replacement for the Industry Standard
574 AID Converter

• 10V Input Range (Bipolar & Unipolar)

HY-94742

• Sample-and-Hold Circuit Added for Improved
Performance

• 20V Bipolar Input Range

• Sample-and-Hold Controlled Internally - Operation Is
Transparent to the User
• 12- or 8-Bit Resolution Modes, Software Selectable
~ Permits Faster Measurements when Inputs are
Changing Quickly and Resolution is notas Important
- Full 12-bit Resolution Available when InputsSellle
• Throughput Rate 12-bit ......................... 43kHz (2~.2J.1s)
(Typical)
8-bit ... ~ .......................,65kHz(15.3 J.ls)

Applications

• Successive Approximation AID Converter

• Process Control Systems

• Full 8-, 12-, or 16-Blt Microprocessor Bus Interface

• Precision Industrial Data Acquisition Systems

• 150ns Bus Access Time

• Electronic Test and SCientific Instrumentation

• Plastic 28-Pin Dual-In-Line Package (DIP) for Commercial and Industrial Temperature Ranges; Hermetic
Ceramic Package for Military Range

Functional Diagram

HY-94741/94742
SAMPLING AID CONVERTER

128)STAruS.STS

1211

ID'

I~I

INPUT

,.

(25)

'"

.,

[241
I~I

122J

INPUT

[2ft

(14)

".
1191
(18)

[17)

1181 Lsa

aBIO

.".87
.~

."."

.03
oa,
oa.

r---i..--.-----.q 121

'--___

5-84

DATAMODE SELECT 1218
131 CHiPSElE(;TCS
141 BYTEADDRESSI
SHORT CYClE All
~ ~:t ~~~~~i~~r~RriE

RIC

HY-94741/94742
N
o::t

Description
The HY-9474x is a complete 12-bit Sampling Analogto-Digital Converter, pin- and functionally-compatible
with the popular 574 AID Converter. A high performance
Track-and-Hold Amplifier has been integrated into the
28-pin 574 package to provide accuracy and repeatability
when sampling rapidly changing signals. Analog input
circuits can now enjoy the benefits of a Track-and-Hold
without the need for redesign, because the HY-9474x is a
direct replacement for the 574 AID.

T/H Section
The Track-and-Hold (T/H or S/H) section uses the Harris
HA-2420 chip, consisting of a high performance
operational amplifier, an ultra-low leakage analog switch
and a MOSFET-input amplifier to drive the AID. A hold
capacitor is included inside the package, and none is
required externally. The T/H is configured for non-inverting unity gain.

UNIPOLAR
RANGE

HY-94741

-5 to +5V

o to +10V

HY-94742

-10 to+10V

oto 10V (11

Bits)

The T IH curcuit used in the HY-9474xcannot tolerate input voltages which
exceed the power supply, so the 0 to +20V input range available on the 574
AID is not supported by the HY-9474x.

Temperature Grades
The HY-9474x will be available initially in Commercial
(0 to +75 0 C) and Industrial (-40 to +85 0 C) temperature
grades. A grade is also being developed for the military
temperature range (-55 to +125 0 C).
Power Requirements
Power requirements are +5V and ±15V with typical
dissipation of 700mW.
Package
All models are packaged in a 28-pin DIP with 600 mil row
centers. Plastic packages are used for cOmmercial and
industrial grades. Ceramic hermetic packages will be
used for the military temperature grade.

1-~~-1.&OOMAX ~~~~_I

TOP VIEW

+5V SUPPLY VLOGIC

o::t
.....

>

BIPOLAR
RANGE

MODEL
NUMBER

Pinout

DATA MODE SEL 1218
CHIP SEL. CS
BYTE AOOR/SHORT CYCLE. AO
REA~/CONVERT. R/C
CHIP ENABLE. CE
+15V SUPPLY. VCC
+IDV REF. REF OUT
ANALOG COMMON. AC
REF INPUT. REF IN
·15V SUPPLY. VEE
BIPOLAR OFFSET.- BIP OFF
IDV SPAN INPUT. 10V IN
20V SPAN INPUT, 20V IN

,..
o::t

Process
The T IH and the AID bipolar chip feature the Harris
Dielectric Isolation process which minimizes stray
capacitance for enhanced AC performance. Also,
parasitic SCRs are eliminated, providing latch-free
operation. The CMOS digital chip of the AID uses the
Harris Self-Aligned Junction Isolation (SAJI) process.

en
enI

HY-9474x INPUT VOTAGE RANGES

NOTE:

The Analog-to-Digital (AID) section uses the proven
HI-574A, including a +10V reference, clock, three-state
outputs and a digital interface for microprocessor control.
Successive approximation conversion is performed by
two monolithic dice (bipolar analog and CMOS digital)
housed in the 28-pin package.

o::t

The HY-9474x offers the most popular unipolar and
bipolar input ranges, as shown below:

The Track-and-Hold feature is transparent to the user,
and requires no special considerations. The HY-9474x is
operated exactly like a plain 574 AID, with the T/H
function being controlled internally.

AID Section

.....

Input Ranges

T
.1111

STATUS. STS
OBI I MSB
OBIO
OB9
OBB
OBI
OB6
OB5
OB4
OB3
OB2
OBI
OBO LSB
DIG COMMON: DC

\1"~~~~E

C"'M"=J

R l
I - - .... ---l

i

5-85

.'OGMAX~

J:

I)

HY-9712

HARRIS

PRELIMINARY

Complete 12-Bit Data
Acquisition Subsystem

Features
•

Complete Multi-Channel Data Acquisition System in a
Single Module

•

Companion to the HY-98C86 Microprocessor Module

•

Input Multiplexer
- 16 channels pseudo differential or 8 channels
differential
- input overvoltage protection
multiplexer expansion pins provided
channel select word latched in internal control
register

•

Precision 10V Reference with 10mA Drive Capability
Bi-directional 8 Bit Data Bus Interface
- input control register for channel and gain selection
- two 8 bit data registers for high and low byte of
A/D output

•

Interrupt Output Line to Tell Microprocessor When Data
is Available

•

"Lost Data" Flag Tells When Data Has Not Been Read

•

Tempereture Grades Offered
Military (-55 to +125°C)

Before Next Conversion is Completed

Industrial (-40 to +85°C)
Commercial (0 to +75°C)

Track-and-Hold (T/H)
self contained - no external capacitor required
- low droop rata
lowapparture uncertainty
uncommitted output

•

•

Programmable Gain Amplifier (PGA)
software controllable gains: 1. 2. 4. 8. 128. 256.
512. 1024
- uncommitted output - filtering or waveshaping can
be inserted
gain select word latched in internal control register

•

•

Precision Instrumentation Amplifier (IA)
- resistor programmable gains from 1 to 1000

•

10V and 20V input ranges
bipolar and unipolar conversion modes
no missing codes over temperature
bus interface for 8M Hz systems (8 or 16 bit)

App/;cations

Analog-to-Digital Converter (A/D)

•
•

Avionics
Portable Data Acquisition Systems

- 12 bit resolution
- 8 bit mode for high speed measurements

•

Process Control

•

Robotics

Functional Diagram

o
o
o

r-----------------------------,
BUS INTERFACE

I

I
I

I

I

o
o

o

L _____________________________ J
DATA ACQUISITION SUBSYSTEM

5-86

Product Index

6-2

Ordering Information

6-3

Standard Products
Packaging Availability

6-3
en
a::

6-4

Selection Guide

«w
b~
_w

,>

ClZ
Cl

u

Product Information

6-5

ABSOLUTE MAXIMUM RATINGS
As with all semiconductors, stresses listed under "Absolute Maximum Ratings"
may be applied to devices (one at a time) without resulting in permanent damage.
This is a stress rating only. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. The conditions listed under
"Electrical Characteristics" are the only conditions recommended for
satisfactory operation.

6-1

Product Index

Page

HI-562A

12-Bit High Speed Monolithi~'bigital-to-Analog'CohVerter.;, ... ,....." ............,...................... 6"..5

HI-565A

High Speed Monolithic DigitaHoCAnalog Converter with Reference ....................... ;....... 6-10

HI-5610

10-BitHigh Speed Monolithic Digital-to-Analog Converter ............................................... 6-17

HI-5618A/5618B

8-Bit High Speed Digital-to-Analog Converters ................................................................... 6-23

H 1-5660/5660A

High Speed Monolithic Digital-to-Analog Converter .......................................................... 6-30

HI-5680

12-Bit Low Cost Monolithic Digital-to-Analog Converter ................................................... 6-39

H 1-5685/5685A

High Performance Monolithic 12-Bit Digital-to-Analog Converter .................................... 6-45

HI-5687

Wide Temperature Range Monolithic 12-Bit

H 1-5690V195V197V

High Speed 12-Bit Low Cost Monolithic Digital-to-Analog Converter ............................. 6-51

HI-5811

Complete, Monolithic 12-Bit Latched Digital-to-Analog Converter ................................... 6-57

HI-7541

12-Bit Multiplying Monolithic Digital-to-Analog Converter .., ............................................. 6-66

Digital-to~Analog

Converter ....................... 6-48

HI-DAC16B/DAC16C 16-Bit Digital-to-Analog Converter ........................................................................................ 6-73

6-2

Ordering Information
HARRIS PRODUCT CODE EXAMPLE

H

-1

T
A
C
o

I

-

T

PART NUMBER

TEMPERATURE:
OOc to +2000 C
-550C to +12SoC
4 -250C to +8So C
aOe to +7S o C
100% +2S oC Probe (Dice Only)
Dash-? High Reliability Commercial
Product. OOC to +7So C
8 Dash-B Program
HA2-2S20-8 (Example only)
9 -400C to +8SoC

Analog
Communications
Digital
Filters

M
V
Y -

5

562A ~

Interface
Memory
Analog, High Voltage
Analog Hybrids
PACKAGE: - - - - - - - '
Dual-in-Line, Ceramic
Metal Can
Dual-In Line, Plastic
Leadless Carriers (LeG)
5 Lee Hybrid
Mini-DIP, Ceramic
Chip Form

*

'*

Special high temperature testing available
on certain product types. Consult factory for
availability.

Standard Products Packaging Availability
PACKAGE

PLASTIC
DIP

TEMPERATURE

-5

SURFACE MOUNT
LCC

CERAMIC
DIP
-2

-4

-5

-8

-8
~



DIGITAL TO ANALOG

ClZ
Cl
(.)

HI-562A
HI-565A

X
X

X
X

X
X

HI-5610

X

X

X

HI-5618A
HI-56188

X
X

X
X

X
X

HI-5660
HI-5660A

X
X

X
X

X
X

X
X

HI-56801
HI-5680V
HI-5685AI
HI-5685AV
HI-56851
HI-5685V

X
X
X
X
X
X

HI-56871
HI-5687V

HI-7541

X
X

*

X

*

X

HI-5690V
HI-5695V
HI-5697V
HI-5811

X

X
X
X

X

X

X

X

X

X
X

HI-DAC168/16C

* Available as MI L-STD-883 Only.

6-3

X

Selection Guide
D/A CONVERTERS
SetUlng

Maximum

Pert

Resolution

Output

Time to

(BIIo)

Range

HI' LSB (Typ.)

Gain
Error
(% FSR)

Features

Number

Dln.renltal

Intergr.,

Reference

Supply Voltage

DIP

Non-Linearity

Non-Linearity
(Max. @ 250 C)

Requirements
VIN/RIN
(Yin)

Power
Di.slpatlon t
(YimW. Typ.)

Package

Pin
Count

Page

'10/20K

'5. -15/280

24'

6-5

'10/20K

±15/320

24

6-10

(M••. @'50 C)
(LSB)

(LSB)

-5/-2

-51-2

HI-562A

Industry
Standard

12

-2mA

300ns

±0.024

±1/2 to ±1I4

±1I2 to ±1I4

HI-565A

+10V Reference
On-Chip

12

-2mA

350n5

±0.1

±1I2 to ±3/4

±1I4 to ±1I2

HI-5610

High Speed

10

-5mA

85ns

±C.05

±1I2

±1I2

"0/8K

'5. -15/420

24

6-17

HI-5618A

High Speed

8

-5mA

65n8

±C.78

±1I4

±1I4

"0/8K

'5. -15/330

18

6-23

HI-5618B

High Speed

8

-5mA

65n8

±0.78

±1/2

±1I2

"0/8K

'5. -15/330

18

6-23

HI-5660

Low Glitch

12

-2m A

250ns

±0.1

±3/4

±1I2

',0/20K

±15/230

24

6-30

HI-5660A

Low Glitch

12

-2mA

250ns

±0.1

±1I2

±1I4

'10/20K

±15/230

24

6-30

HI-5680VII

Voltage Current
DAC 80.
OOC to '750 C

12

±10V
-2mA

1.5/.Isl

±0.1

±3/4

±1/2

+5, ±12/320

24

6-39

300ns

·6.3112.6K
(Internal)

Voltage/Current
DAC 80.
-2SoC to +850C

12

±10V
-2mA

±0.1

±3/4

±1/2

+6.3/12.6K
(Internal)

+5, ±12/320

24

6-45

300ns

Voltage/Current

12

±0.1

±3/4

±1/2

·6.3112.6K
(Internal)

+5, ±12/320

24

6-45

±0.1

±3/4

±1/2

·6.3112.6K
(Internal)

+5, ±12/320

24'

6-48

HI-5685VII

HI-5685AVII

(Internal)

Low Drift

1.5/.Isl

±10V
-2mA

1.5/.ISI

±10V
-2mA

1.5/.ISI

,

300ns

-250C to +850C
HI-5687VII

Voltage/Current
DAC 80,

12

300ns

-550 C to -+'1250 C
HI-5690V

Fast Settling YO;
DAC 80
OOC to +750 C

12

±10V

750ns

±0.1

±3/4

±1I2

·6.3112.6K
(Internal)

±12/555

24

6-51

HI-5695V

Fast Settling VO;
DAC 80
-250 C to +85 0 C

12

±10V

750ns

±0.1

±3/4

±1I2

·6.3112.6K
(Internal)

±12/555

24

6-51

HI-5697V

Fast Settling VO;
DAC 80
-550 C to + 1250 C

12

±10V

750ns

±0.1

±3/4

±1I2

·6.3112.6K
(Internal)

±12/555

24'

6-51

HI-58"

Voltage Out
Latched

12

±10V

3ps

±0.1

±1I2

±114

·6.3/5.36K

±15/625

28

6-57

HI-7541

Multiplying;
Low Power;
CMOS

12

ImA

1.Ops Max.

to.305

to.5 to ±1.0

to.S to ±1.0

±10/9K

+15/30 Max.

18

6-66

HI-DACI6B

16 Bit
Monolithic

16

-2mA

I.ll/Js
(14 BitS)

±0.1

±1 Typ.

±1.5 Typ.

+1Oi10K

±15/465

40

6-73

HI-DACI6C

16 Bit
Monolithic

16

-2mA

1.ll/Js
(14 BIts)

±0.1

±2 Typ.

±3 Typ.

+10110K

±15/465

40

6-73

* Surface Mount

/

(Internal)

Package Available

t Most supplies can be varied from :t12 volts to ±15 volts. please see data sheets for speCific information.

6-4

mHARRIS

HI· 562A

c(
('II

CD

LI)

12 Bit High Speed Monolithic
Digital-to-Analog Converter
Features

Applications

• Output Current ............................................... 2mA, F.S.

• CRT Display Generation

• Monolithic Construction

• High Speed AID Converters

• Extremely Fast Settling ............ 300ns To 0.01% (Typ)

• Video Signal Reconstruction

• Low Gain Drift ................................ ±10ppm/O C (Max)

• Waveform Synthesizers

• Linearity Guaranteed Over Temperature...... ±1/2 LSB
(Max)

• High Speed Data Acquisition

• Designed for Minimum Glitches

I

• High-Rei Applications
• Precision Instruments

• Monotonic Over Temperature

Description
The Harris HI-562A is the first monolithic digitalto-analog converter to combine both high speed
performance and 12-bit accuracy on the same chip. The
HI-562A's fast output current settling of 300ns to 0.01 % is
achieved using dielectric isolation processing to reduce
internal parasitics for fast rise and fall times during
switching. Output glitches are minimized in the HI-562A
by incorporating equally weighted current sources
switched. into an R-2R ladder network for symmetrical
turn-ON and turn-OFF switching times. This creates
within the chip a very uniform and constant thermal
distribution for excellent linearity and also completely
eliminates thermal transients during switching. High
stability thin film resistor processing together with laser
trimming provide the HI-562A with guaranteed 12-bit
linearity to within ±1/2 LSB maximum at +25 0 C for -4 and
-5 parts and to within ±1/4 LSB maximum at +250 C for-2

and -8 parts. The HI-562A is recommended as a replacement for higher cost hybrid and modular units for
increased reliability and accuracy in applications such as
CRT displays, precision instruments and data acquisition
systems requiring throughput rates as high as 3.3 MHz for
full range transitions. Its small size makes it an ideal
choice as the heart of high speed AID converter designs
or as a building block in high speed or high resolution
industrial process control systems. The HI-562A is also
ideally suited for aircraft and space instrumentation
where operation over a wide temperature range is
required.
The HI-562A is offered in commercial, industrial and
military grades. For additional Hi-Rei screening including
160 hour burn-in specify the "-8" suffix. All are available in
a hermetically sealed 24-lead dual-in-line package.

Schematic

Pinout
TOP VIEW
1

24

BIT 1 (MSBlIN
BIT 21N

VREF (LO INl

2
3

23
22

BIT31N

Nit

4

21

BIT41N

VREF (HIINl

5

20

BITS IN

Vps+

LOGf~fES{m

GND

For L(;(; Pinout see page 6.

6-5

TTL/CMOS
LOGIC
LEVEL BIT 11N
V+ SELECT IMSBI 2

BIT 121N
3

11

tLSBI

gg


o

02

c.>

Specifications HI-562A
..

Absolute 'Maximum· Ratings

(Referred to Ground)1

Power Supply Inputs
Vps+ ......................................................... +20V
Vps- ........................ , .......... , ........................ -20V

Operating Temperature Range
HI-562A-2

...........................

-55 0 C to +125 0 C

HI-562A-4 ............ ............ ..... -25 0 C to +85 0 C
HI-562A-5 ................................. OOC to +75 0 C

Reference Inputs
VREF (High) ........................................ ±16.5V

HI-562A-8

Digital Inputs
Bits 1-12 (TTL) ................................ -1V, +7.5V
Bits 1-12 (CMOS) ............................. -1V, V ps +
CMOS/TTL Logic Select ............ -W, +16.5V

...........................

-55 0 C to +125 0 C

Storage Temperature Range ............... -65 0 C to +1500 C

Outputs
Pins 7,8,10, 11 ..................................... ±Vps
Pin

9 ................................................. +Vps, -5V

Power Dissipation
Pd, Package (Ceramic DIP) ............ 2000mW'

Electrical Characteristics

v

'Derate 20mWlo C above 750 C

v

(@ +25 0 C, ps+,=+5V; ps - = -15V, VREF = +10V, pin 2 tied to pin 12
unless otherwise noted)

I
PARAMETER

..

CONDITIONS

HI-562A-21HI-562A-8
MIN I TYP I MAX

I

I

I

HI-562A-4/HI-562A-5
MIN
I TYP I MAX

I
UNITS

INPUT CHARACTERISTICS
Digital Inputs (3)

\'"~"."'~

Bit ON "Logic 1"
Bit OFF "Logic 0"

Logic "1"
Logic "0"

TTL/CMOS

Input Current (2)
Logic "1"
Logic "0"

r'·~
Logic "1"
Logic "0"

CMOS

Input Current
Logic "I"
Logic "0"

Reference Input
Input Resistance
Input Voltage

2.0

0.8

V
V

±500
-100

nA
pA

0.3V ps+

V
V

±5oo
-100

nA
pA

2.0
0.8

(Vps+ <9.5V)
Pin 2 tied to Pin 12
Over full temp. range

20
-50

±5oo
-100

20
-50

0.7V ps+

0.7Vps+
Pin 2 tied to Pin 1

0.3V ps+

"

(V ps + 2;:+9.5V)
over full temp. range
20
-50

(± 200/0)

±SOO
-.100

20
50

19.95K
+10

19.95K
+10

Cl

V

TRANSFER CHARACTERISTICS
Resolution
Nonlinearity (3)
Differential
Nonlinearity (3)
Relative Accuracy (S)
Gain Error
Bipolar Offset Error
Unipolar Offset Error
Adjustment Range
Gain
Bipolar Offset
Temperature Stability
Gain Drift (3)
Offset Drift (3)
Unipolar Offset
Bipolar Offset
Differential Nonlinearity
Settling Time (3)
to ±1/2 LSB

Over full temp. range
@+25 0 C
Over full temp. range
@+25 0 C
Over full temp. range
with son (I %) Resistors
All Bits ON

12

±1/4
±1/2

I

12

±1I4

±1/2

±1I4

±1/2

±I

±1I4

±1

MONOTONICITY GUARANTEED
±.024
±.024
±.012

All Bits OFF
See Operating Instructions
With lOon Trim
Potentiometers
Drift specified with internal
span resistors for voltage output
Overfull
temp. range

±0.25
±0.25
±0.05

±0.3
±O.S

All Bits OFF
Over full temp. range
All Bits ON-to-OFF or
OFF-ta-ON

±.024
±.024
±.012

±0.25
±0.25
±0.05

±0.3
±O.S

Bits
LSB
LSB

%FSR (4)

%FSR

±6

±IO

±IO

±1

±2
±4
±2

±I

±2
±4
±2

300

400

300

400

ppm of
FSR/oC

ns

,

6-6
\

Specifications HI-562A (continued)
c(
PARAMETER

HI-562A-2/HI-562A-8
MIN
TYP
MAX

CONDITIONS

I

HI-562A-4/HI-562A-5
MIN
TYP
MAX

N
CD

UNITS

Power Supply Sensitivity (3)
Unipolar Offset
Vps+ @ +5V or +15V
Vps- @ -15V
Bipolar Offset
Vps+ @ 5V or +15V
Vps- @ -15V
Gain
Vps+ @ +5V or +15V
Vps- @ -15V

I

:I:

Major Carry Transient

Peak Amplitude
Settling Time to
90% Complete

it)

From 011 ... lto 100 .. 0
or 100 ... 0 to 011 . .. 1

0.7
35

0.7
35

±0.5
±0.5

±0.5
±0.5

±1.5
±1.5

±1.5
±1.5

mA
ns

All Bits OFF

All Bits OFF, Bipolar mode

All Bits ON

±3.5
±7.5

ppm of
FSR/%V ps

±3.5
±7.5

OUTPUT CHARACTERISTICS
Output Current
Unipolar

-1.6
±0.8

Bipolar
Heslstance
Capacitance

Output Voltage Ranges
Unipolar
Bipolar

Compliance Limit (3)
Compliance Voltage (3)
Output Noise

Using external op amp
and internal scaling
resistors. See Figure 1
and Table 1 for connections

-2.0
+1.0
2K
20

-2.4
±1.2

-2.0
+1.0
2K
20

o to +5
o to +10

o to +5
o to +10

±2.5
±5
±10

±2.5
±5
±10

-3

+10

Over full temp. range
0.1 to 10Hz (All Bits ON)
0.1 to 5 MHz (All Bits ON)

-1.6
±0.8

-3

±1.0
30
100

-2.4
±1.2

mA
ohms
pF

V

+10
±1.0
30
100

V'
V
jJV (p-p)

Vps+ (7)
Vpsps+ \0)
Ips- (5)
ps+ \0)
Ips- 5
,",ower ulsslpatlon

en

'"

POWER REQUIREMENTS

;ame as apove except
over full temp. range

Vps+ - +5V (25 U C)
Vps- =-15V

-15
8
16
11
20
2.80

16.5
-16.5
15
23
20
30
420

NOTES:

5. After 30 .seconds warm-up.

1. Absolute maximum ratings are limiting values, applied individually,
beyond which the serviceability of the circuit may be impaired.
Functional operation under any of these condiitons is not necessari.ly

6. Using an' extern'al

implied.
2. Vps+ tolerance is ±100/0 for HI-562A-2, -8, and ±50/0 for HI-562A-4, -5:
3. See Definitions.
4. FSR is "full scale range" and is 20Vfor ±1 OV ranges, 10V for ±5V ranges,
~tc., or 2mA (±200/0) for current output.

op' amp

4.75
-13.5

-15
8
16
11
20
280

16.5
-16.5
15
23
2u
30
420

V

0'"
_w

mA

02
0

mA
mW

with internal span resistors and specified

external trim resistors in place of potentiometers R1 and ~2. Errors are
adjustable to zero using R1 and R2 potentiometers. (See Operatin.g
Instructions Figure 2.)

7. The HI-562A is designed for Vps+ =5V, but +4.5V $ Vps+ $16.5V maybe
connected if convenient. (For V ps+ above +5V, there is an increase in
power dissipation but little change in performance.

Die Characteristics

Transistor Count ..................... ..

.., ... 150

Die Size ..................................................... 103 x 209 mils
Thermal Impedance
iJja ...................................................................... 50 0 C/W
~c .................................................... .................. 15 0 C/W
Tie Substrate to ................... VREF Lo (Analog Ground)
Process ............................................................. Bipolar-DI

6-7

,>
(..)

HI-562A
Definitions of Specifications
Drift

Digital Inputs
The HI-562A accepts digital input codes inbinary format
and maybe user connected for anyone of three binary
; codes: Straight Binary, Two's Complement, or Offset
Binary (see Operating Instructions).
ANALOG OUTPUT
DIGITAL
INPUT
MSB LSB
000 .. ,000
100 ... 000
111. .. 111
Of1 ... 111

51ralght
Binary

Offset
Binary

Two's,
Complement'

Zero

-FS (Full Scale)
Zero
+FS-1LSB
Zero -1 LSB

Zero
-FS
1/2 FS - 1 LSB
+FS - 1 LSB

1/2 FS

+FS -1 LSB
1/2 FS - 1 LSB

'Invert MSB with external inverter to obtain Two'.
Complement Coding

Accuracy
INTEGRAL NONLINEARITY-The maximum deviation
of the actual transfer characteristic from an ideal straight
line. The ideal line is positioned according to "end-point
linearity" for Of A converter products from Harris
Semiconductor, i.e. the line is drawn between the
end-points of the actual transfer characteristic (codes
00 ... 0 and 11 ... 1).
DIFFERENTIAL NONLINEARITY-The difference between one LSB and the output voltage change
corresponding to any two consecutive codes. A
Differential Nonlinearity of ±1 LSB or less guarantees
monotonicity.
MONOTONICITY-The property of a Of A converter's
transfer function which guarantees that the output
derivative will not change sign in response to a sequence
of increasing (or decreasing) input codes. That is, the
only output response to a code change is to remain
constant, increase for increasing code, or decrease for
decreasing code.
Settling Time
That interval between application of a digital step input,
and final entry of the analog output within a specified
window about the settled value. Harris Semiconductor
usually specifies a unipolar 10V full scale step, to be
measured from 50% of the input digital transition, and a
window of ±1f2 LSB about the final value. The device
output is then rated according to the worst (longest
settling) case: low to high, or high to low.

GAIN DRIFT-The change in full scale analog output over
the specified temperature range expressed in parts per
million of full scale range per oC (ppm of FSRfOC). Gain
error is measured with respect to +25 0 C at high (TH) and
low (TL) temperatures. Gain drift is calculated for both
high (TH -25 0 C) and low (+25 0 C - TL) ranges by dividing
the gain error by the respective change in temperature.
The specification is the larger of the two representing
worst case drift.
OFFSET DRIFT-The change in analog output with all
bits OFF over the specified temperature range expressed
in parts per million of full scale range perOC (ppm of FSRf
OC). Offset error is measured with respect to +25 0 C at
high (TH) and low (TL> temperatures. Offset Drift is
calculated for both high (TH -25 0 C) and low (+25 0 C - TL>
ranges by dividing the offset error by the respective
change in temperature. The specification given is the
larger of the two, representing worst-case drift.
Power Supply Sensitivity
Power Supply Sensitivity is a measure of the change in
gain and offset of the DfA converter resulting from a
change in -15V, +5Vor+15V supplies. It is specified under
DC conditions and expressed as parts per million of full
scale range per percent of change in power supply (ppm
of FSRf%).
Compliance
Compliance voltage is the maximum output range for
which specified accuracy limits are guaranteed. Compliance limit implies functional operation only and makes
no claims to accuracy.
Glitch
A glitch on the output of a DfA converter is a large
transient spike resulting from unequal internal ON-OFF
switching times. Worst case glitches usually occur at
half-scale or the major carry code transition from 011 ... 1
to 100 ... 0 or vice versa. Forexample, if turn ON isgreater
than turn OFF for 011 ... 1 to 100 ... 0, an intermediate
state of 000 ... 0 exists, such that, the output momentarily
glitches toward zero output. Matched switching times and
fast switching will reduce glitches considerably.

6-8

HI-562A



Co::

8

m

HI·565A

H.AR.RIS

High Speed Monolithic
Digital-to-Analog
Converter with Reference

DESCRIPTION

FEATURES

The HI-565A is a fast, 12 bit current output, digital to analog
converter. The monolithic chip includes a precision voltage reference, thin-film R-2R ladder, reference control amplifier and twelve
high-speed bipolar current switches.

• DAC AND REFERENCE ON A SINGLE CHIP
• PIN COMPATIBLE WITH AD565A
• VERY HIGH SPEED: SETTLES TO 1/2 LSB IN 250n5, MAX.
FULL SCALE SWITCHING TIME 30ns, TYP.
• GUARANTEED FOR OPERATION WITH ±12V SUPPLIES
• MONOTONICITY GUARANTEED OVER TEMPERATURE
• 1/2 LSB MAX NONLINEARITY GUARANTEED OVER
TEMPERATURE
25ppm/ oC

• LOW GAIN DRIFT (MAX, DAC PLUS
REFERENCE)

250mW

• LOW POWER DISSIPATION

APPLICATIONS

The HarrisSemiconductor dielectric isolation process provides latchfree operation while minimizing stray capacitance and leakage
currents, to produce an excellent combination of speed and accuracy. Also, ground currents are minimized to produce a low and
constant current through the ground terminal. which reduces error
due to code-dependent ground currents.
HI-565A dice are laser trimmed for a maximum integral nonlinearity error of ±1I4 LSB at +25 0 C. In addition, the low noise
buried zener reference is trimmed both for absolute value and
minimum temperature coefficient.
The H1-565A is offered in both commercial and military grades.
For additional Hi-Rei screening including 160 hour burn-in, specify
the "-8" suffix. See Ordering Information.

• CRT DISPLAYS
• HIGH SPEED AID CONVERTERS
• SIGNAL RECONSTRUCTION

Package is a 24 pin side-brazed ceramic DIP. Power dissipation
is typically 250mW. with ±15V supplies.

• WAVEFORM SYNTHESIS

FUNCTIONAL DIAGRAM

PINOUT

TOP VIEW
NC

BIT 1 (MSB) IN

NC

BIT 21N

VCC

BIT 31N

REF OUT (+10V)

BIT 4 IN

REF GNO

BIT 51N

REFIN

BIT SIN

-VEE

BIT liN

BIPOLAR R IN

BIT SIN

IDAC OUT

BIT 91N

10V SPAN R

BIT 10 IN

20V SPAN R

BIT !lIN

POWER GND

BIT 12 (LSB) IN

11

BIP. OFF.
HI-565A

,ov

8

20VSPAN

5K

'0 10VSPAN

IREF

REF

I~

5K

19.95K

9
3.5K

REF

3K

GND

";'

";'

-VEE

PWR
GNO

6-10

MSB LSB

OUT

SPECIFICA T10NS
oct
II)

ABSOLUTE MAXIMUM RATlNGS*

CD

Vee to Power Ground
VEEto Power Ground
Voltage on DAe Output (Pin 9)
Digital Inputs (Pins 13-24) to Power Ground
Ref In to Reference Ground

10V Span R to Reference Ground
±12V
20V Span R to Reference Ground
±24V
Ref Out
Indefinite Short to PowerGround
Momentary Short to Vee
Package Power Dissipation
1960mW
Ceramic (0)*

OV to +18V
OV to -18V
-3V to +12V
-lV to +7.0V
±12V

II)
I

±12V

Bipolar Offset to Reference Ground

... Absolute maximum ratings are limiting values beyond which the serviceability of the circuit may be impaired .
.... Derate 19.6mW/oC above 75°C.

ELECTRICAL CHARACTERISTICS (TA = +25 0 e, Vee = +15V, VEE = -15V, Unless Otherwise Specified)
HI-565AK, HI-565AT

H1-565AJ, H1-565AS
MODEL

MIN

TYP

MAX

MIN

+5.5
+0.8

+2.0

TYP

MAX

UNITS

+5.5
+0.8

V
V

+1.0
-20

/lA
/lA

12

Bits

DATA INPUTS (Note 1) (Pins 13 to 24)
TTL or 5V CMOS (TMIN to TMAX)
Input Voltage
Bit ON Logic "I"
Bit 0 FF Logic "0"
Logic Current (Each Bit)
Bit ON Logic "1"
Bit OFF Logic "0"

+2.0

+1.0
-20

.01
-2.0

.01
-2.0

12

RESOLUTION

en

e::

OUTPUT
Current

Unipolar (All Bits On)
Bipolar (All Bits on or Off)
Resistance (Exclusive of Span Resistors)
Offset
Unipolar
Bipolar (Figure 2, R3 =
50nFixed)
Capacitance
Compliance Voltage, TMIN to TMAX

-1.6
±0.8
1.8k

-2.0
±1.0
2.5k
0.01

-2.4
i1.2
3.2k
0.05

0.05
20

0.15
+10

-1.~

-1.6
±0.8
1.8k

-2.0
i1.0
2.5k
0.01

-2.4
±1.2
3.2k
0.05

mA
mA
n
% of F.S.

0.05
20

0.1
+10

% of F.S.
pF
V

-1.5

ACCURACY (Error Relative to
Full Scale)
+25 0 C
TMIN toTMAX

tl/2

±1/4
(0.006)
.±1/2
(0.0121

(0.012)
±3/4
(0.018)

il/8
(0.003)
il/4
(0.006)

±1/4
(0.006)
±1/2
(0.012)

LSB
% of F.S.
LSB
% OF F.S.

±1/2

±3/4

il/4

il/2

LSB

1

2
10
25

ppm/OC
ppm/oC
ppm/oC
ppm/oC

500
250

ns
ns

DIFFERENTIAL NONLINEARITY
+25 0 C

MONOTONICITY GUARANTEED

TMIN toTMAX
TEMPERATURE COEFFICIENTS
With Internal Reference
Unipolar Zero
Bipolar Zero
Gain (Full Scale)
Differential Nonlinearity

1
5
15
2

10
40

350
150

500
250

5
10
2

SETTLING TIME TO 1/2 LSB
With High.Z External Load (Note 2)
With 75 n External Load

6-11

350
150

<{~

"e::

Sw

">

ClZ

0

c..:>

SPECIFICATIONS (Continued)

HI-565AK, HI-565AT

HI-565AJ, HI-565AS
MIN

MOOEL

TYP

MAX

15
30

30
50

MIN

TYP

MAX

UNITS

15
30

30
50

ns
ns

FULL SCALE TRANSITION (From
50% of Logic Input to 90% of Analog
Output)
Rise Time
Fall Time
TEMPERATURE RANGE
(HI-565AJ/K)
(HI-565AS/T)

Operating

0
-55

+75
+125

0
-55

+75
+125

oC
oc

-65
-25

+150
+150

-65
-25

+150
+150

oC
oc

Storage
D Package (All)
N Package (J, K)
POWER REQUIREMENTS
ICC, +11.4 to +16.5V DC
IEE,-l1.4to -16.5V DC

9.0
-9.5

11.8
-14.5

9.0
-9.5

11.8
-14.5

mA
rnA

ppm of
F.S./%
ppm of
F.S.I%

POWER SUPPLY GAIN SENSITIVITY
(Note 3)
VCC

=+11.4 to +16.5 VOC

3

10

3

10

VEE

=-11.4 to -16.5 VDC

15

25

15

25

PROGRAMMABLE OUTPUT
RANGES (See Table 1)

o to +5
-2.5 to +2.5
o to +10
-5 to +5
-10to+l0

V
V
V
V
V

o to +5
-2:5 to +2.5
o to +10
-5 to +5
-10to+l0

EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50 n Resistor
for R2 (Figure 1)
Bipolar Zero Error with Fixed 50n
Resistor for R3 (Figure 2)
Gain Adjustment Range (Figure 1)
Bipolar Zero Adjustment Range

to.l

to.25

±0.05

±0.15

fO.25
fO.15

±0.1

±0.25

% of F.s.

±0.05

±0.1

% of F.s.
% of F,S.
% of F.S.

fO.25

±a.15

REFERENCE INPUT
Input Impedance

15K

20K

25K

15K

20K

25K

9.90
1.5

10.00
2.5

10.10

9.90
1.5

10.00
2.5

10.10

V
rnA

250

375

250

375

mW

REFERENCE OUTPUT
Voltage
Current (Available for External Loads)
POWER DISSIPATION

NOTES:
1. Guaranteed but not tested over the operating temperature range.
2. See settling time discussion and Figure 3.
3. The Power Supply Gain Sensitivity is tested in reference to a Vee, VEE of±15V.

6-12

DEFINITIONS OF SPECIFICATIONS
DRIFT

DIGITAL INPUTS


Oz
o(.)

APPLYING THE HI-565A (ContinueJl)
-

!

Table 1 - Operating Modes and Calibration

CALIBRATION:

CIRCI:"T CONNECTIONS:
MOOE
Unipolar
(See Fig. 1)

Bipolar
(See Fig. 2)

APPLY
INPUT COOE

ADJUST

TO SET'
Vo

1.43K

All O's
AliI's

Rl
R2

OV
+9.99756V

Pin 9

1.lK

All O's
AliI's

Rl
R2

OV
+4.99878V

NC

Vo

1.69K

All O's
AliI's

R3
R4

-10V
+9.99512V

±5V

Vo

Pin 10

1.43K

All D's
AliI's

R3
R4

-5V
+4.99756V

±2.5V

Vo

Pin 9

1.1K

All O's
AliI's

R3
R4

-2.5V
+2.4987BV

OUTPUT
RAN,GE

PIN10
TO

PIN 11 RESISTOR
(R)
to

oto +10V

Vo

Pin 10

oto +5V

Vo

±10V

With these changes, performance is guaranteed as shown under
Specifications, "External Adjustments". Typical unipolar
zero will be ±1/2 lSB plus the op amp offset.

C,libration is a two step process for each of the ,five output
ranges shown in Table 1. First adjust the negative full scale
(zero for unipolar ranges). This is an offset adjust which translates the output characteristic, i.e. affects each code' by the
same amount.

The feedback capacitor C must be selected to minimize settling
time.
CALIBRATION

Next adjust positive FS. This is a gain error adjustment, which
rotates the output characteristic about-,the, negative FS value.

Calibration provides the maximum accuracy from a converter
by adjusting its gain and offset errors to zero. For the H1-565A,
these adjustments are sim ilar whether the current output is
used, or whether an external op amp is-added to convert this
current,to a voltage. Refer to Table 1 for the voltage output
case, along with Figure 1 or 2.

For the bipolar ranges, this approach leaves an error at the zero
code, whose maximum value is the same as for integral nonlinearity error. In general, only two values of output may be
calibrated exactly; all others must tolerate some error.
Choosing the extreme end points (plus and- minus full scale)
minimizes this distributed error for all othereodes.

,03

-VEE

PWR
GND

-VEE

PWR
OND

Figure 2 - B'ipolar Voltage Output

Figure 1 - Unipolar Voltage Output

6-14

SETTLING TIME


_UJ

02

o

u

+3V

®

OV

50%
DIGITAL
-+,__________
INPUT

OV

®
9.95k

~

«UJ

• Measure tx from scope as shown in Figure 3B. Settling
time equals tx + to. i.e. tx +15ns.

(TURN OFF) -400mV

10 NC

I-_-l---J

DAC
OUTPUT

SETTLING TIME

to =-COMPARATOR DELAY
5k

tx

©

O.8V - - - -

4V

@

Figure 38

6-15

"eQUAL BRIGHTNESS"

I--------..--,I,L-r----

OV

Figure 3A

COMPo
STROBE

50%

COMPo
OUT

OTHER CONSIDERA TIONS
to pin 9 should be short and few. Component leads should be
short on the side connecting to pin 9 (as for feedback capacitor
C). See the Settling Time section.

GROUNDS

The HI-565A has two ground terminals, pin 5 (REF GND) and
pin 12 (PWR GNDI. These should not be tied together riear
the package unless that point is also the system signal ground
to which all returns are connected. (If such a point exists, then
separate paths are required to pins 5 and 12).

BYPASS CAPACITORS

Power supply bypass capacitors on the op amp will serve the
HI-565A also. If no op amp is used, a O.OlIJF ceremic capacitor
from each supply terminal to pin 12 is sufficient, since supply
current variations are small.

The current through pin 5 is near-zero DC*; but pin 12 carries
up to 1.75mA of code - dependent current from bits 1, 2,and
3. The general rule is to connect pin 5 directly to the system
"quiet" point, usually called signal or analog ground. Connect
pin 12 to the local digital or power ground. Then, of course,
a single path must connect the analog/signal and digital/power
grounds.

*Current cancellation is a two-step process within the HI-565A in
which code-dependent variations are eliminated, then the resulting DC current is supplied internally. First an auxiliary 9 bit
R-2R ladder is driven by the complement of the DAC's input
code. Together, the ma,n and auxiliary ladders drew a continuous 2.25mA from the internal ground node, regardless of input
code. Part of this DC current is supplied by the zener voltage
reference, and the remainder is sourced from the positive supply
via a current mirror which is laser trimmed for zero current
through the external terminal (pin 5).

LAYOUT

Connections to pin 9 (lOUT) on the HI-565A are most critical
for high speed performance. Output capacitance of the DAC
is only 20pF, so a small change or additional capacitance may
alter the op amp's stability and affect settling time. Connections

DIE CHARACTERISTICS
Transistor Count
Die Size
Thermal Constants; 0 ja
Ojc
Tie Substrate to:
Process:

6-16

200
179 x 107 mils

51 0 C/W
160 C/W
Rer. Ground
Bipolar - DI

;m~RIS

HI·561 0
10-Bit High Speed Monolithic
Digital-to-Analog Converter

FEATURES

APPlICA TIONS

•
•
•
•
•
•

•
•
•
•
•
•
•

MONOLITHIC CONSTRUCTION
EXTREMEL Y FAST SETTLING . ............. . 850s TO Y2LSB TYP.
LOW GAl NOR I FT . . . . . . . . . . . . . . . . . . . . . . . . . . ±5ppm/OC TYP.

EXCELLENT LINEARITY OVER TEMPERATURE ....... ± HSB MAX.
OESIGNEO FOR MINIMUM GLITCHES
MONOTONIC OVER TEMPERATURE

o
,....
CD

It)
I

CRT DISPLAY GENERATION
HIGH SPEED AID CONVERTERS
VIDEO SIGNAL RECONSTRUCTION
WAVEFORM SYNTHESIZERS
HIGH SPEED DATA ACQUISITION
HIGH RELIABILITY APPLICATIONS
PRECISION INSTRUMENTS

DESCRIPTION
The HI-5610 is an ultra-high speed 10 bit monolithic current output digital-to-analog converter. The fast output current settling of
85ns to %LSB of its final value is achieved using dielectric isolation
processing to reduce internal parasitics for fast rise and fall times
during switching. Output glitches are minimized in the HI-5610 by
incorporating equally weighted current sources switched into an
R-2R ladder network for symmetrical turn-on and turn-off switching times. This creates within the chip a very uniform and constant
thermal distribution for excellent linearity and also eliminates thermal transients during switching. High stability thin film resistor
processing, together with laser trimming provide the H1-5610 with
true 10 bit linearity to within'± %LSB maximum over operating
temperature range. The HI-5610's low offset and gain drift over
the operating temperature range assures that its absolute accuracy
when referred to a fixed 10V reference will not deviate more than
.± 1LSB for both unipolar and bipolar operation.

PINOUT

The HI-5610 is recommended as a replacement for high cost hybrid
and modular units for increased reliability and accuracy in applications such as CRT Displays, precision instruments and data acquisition system requiring through-put rates as high as 12MHz for full
range transitions. Its small size makes it an ideal choice as the
essential part of high speed AID converter designs or as a building
block in high speed or high resolution industrial process control
systems. The HI-5610 is also ideally suited for aircraft and space
instrumentation where operation over a wide temperature range is
required.
The HI-5610 is offered in both commercial and military grades.
For additional Hi-Rei screening including 160 hour burn-in, specify
the "-8" suffix. All are available in a hermetically sealed 24 lead
dual-in-line package.

FUNCTIONAL DIAGRAM
LOGIC

TOP VIEW
Vps+
CMOS/TTL
LOGIC SELECT
• VREF (LO IN)
NC
VREF (HI IN)
VpsBIPOLAR R IN
BIPOLAR ROUT
IOAC OUT
SPAN R
SPAN R
• GNO

11

BIT 1 (MSB) IN
BIT 21N
BIT 3 IN
BIT 41N
BIT 51N
BIT SIN
BIT 7 IN
17 BIT 81N
16 BIT91N
15 BIT10lN
14 NC

12

13

3

S

9
10

24
23
22
21
20
19
18

VREF (HI IN)

5

COMPo CAP"

.. Pin 3 connected to bottom case for high
frequency shielding .
•• For high speed operation, connect O.OlJ.lF
between Pin 13 and GND.
Otherwise,
leave Pin 13 open.

v-

6-17

~

«w

bb:
_w

,>
Cz
o

u

SPECIFICA TIONS
. . ABSOLUTE
MAXIMUM RATINGS
.
.
,
Cz

8

Output Noise Voltag.IS)
O.lHzto 100Hz
O.lHzto lMHz

1.

~

"f~
Ow

Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability 01 the circuit may be
impaired. Functional operation under any of these conditions
is not necessarily implied.

5.

See definitions.

6.

Using an external op amp with internal span resistors and
24.9n ±1% external trim resistors in place 01 potentiometers
R1 and R2. These errors are adjustable to zero using R1 and
R2. (See operating instructions.)

7.

Using an external op amp and internal span resistors. (See
operating instructions lor connections.)

For TTL and OTL compatibility connect +5V to pin 1 and
ground pin 2. The Vps+ tolerance is ±10% lor HI-5610-2,-S.
And ±5% lor HI-5610-5.

S.

Specilied for digital input in all '1's or all 'O's.

9.

FSR is "Full Scale Range" and is 5V for ±2.5V range, 2.5V
for ±1.25V range, etc., or 5mA (±20%1 lor current output.

For CMOS compatibility based on Vps+ 2: 9.5V, (switching
thresholds equal Vps+f2), connect pins 1 and 2. For CMOS
levels below 9.5V, connect pin 2 to ground only (this provides
a threshold of approximately +1.4V).

10.

The HI-5610 accepts digital input codes in binary lor mat and
may be user connected for anyone of three binary codes.
Straight binary, offset binary, or two's complement binary.
(See operating instructions).

6-19

After 30 seconds warm-up.

DEFINITIONS OF SPECIFICATIONS
ACCURACY

INTEGRAL NONLINEARITY - The maximum deviation of the
actual transfer characteristic from an ideal straight line. The ideal
line is positioned according to "end-point linearity" for D/A
converter products from Harris "Semiconductor, i.e. the line is
drawn between the end-points of the actual transfer characteristic
(codes 00 ... 0 and 11. .. 1).
DIFFERENTIAL NONLINEARITY - The difference between one
LSB and the output voltage change corresponding to any two
consecutive codes. A Differential Nonlinearity of ±1 LSB or less
guarantees monotonicity.
MONOTONICITY - The property of a D/A converter's transfer
function which guarantees that the output derivative will not
change sign in response to a sequence of increasing (or decreasing)
input codes. That is, the only output response to a code change is
to remain constant, increase for increasing code, or decrease for
decreasing code.
SETTLING TIME

Settling time is the time required for the output to settle within
the specified error band for any input code transition. It is usually
specified for a full scale transition (11 ... 1 to 00... 0 or vice versa).

OFFSET DRIFT - The change in analog output with all bits OFF
over the specified temperature range expressed in parts per million
of full scale range per oC (ppm of FSR/oC). Offset error is measured with respect to +25 0C at high (TH) and low (TL) temperatures.
Offset Drift is calculated for both high (TH -25 0C) and low (+25 0C
-TL) ranges by dividing the offset error by the respective change
in temperature. The specification given is the larger of the two,
representing worst case drift.
POWER SUPPLY SENSITIVITY

Power Supply Sensitivity is a measure of the change in gain and offset of the D/A converter reSUlting from a change in -15V, +5V or
+15V supplies. It is specified under DC conditions and expressed as
parts per million of full scale range per percent of change in power
supply (ppm of FSR/%).
COMPLIANCE

Compliance voltage is the maximum output voltage range that can
be tolerated and still maintain its specified accuracy. Compliance
limit implies functional operation only and makes no claims to
accuracy.
GLITCH

DRIFT

GAIN DRIFT - The change in full scale analog output over the
specified temperature range expressed in parts per million of full
scale range per oC (ppm of FS R/oC). Gaip error is measured with
respect to +250C at high (TH) and low (TU temperatures. Gain
drift is calculated for both high (TH -25 0C) and low ranges (+25 0C
-TL) by dividing the gain error by the respective change in temperature. The specification is the larger of the two representing worst
case drift.

A glitch on the output of a D/A converter is a transient spike
resulting from unequal internal 0 N-O FF switching times. Worst
case glitches usually occur at half-scale or the major carry code
transition from 011. .. 1 to 100... 0 or vice versa. For example,
if turn ON is greater than turn OFF for 011 ... 1 to 100... 0, an
intermediate state of 000 ... 0 exists, such that, the output momentarily glitches toward zero output. Matched switching times and
fast switching will reduce glitches considerably.

OPERA TING INSTRUCTIONS
CMOSiTTL
LOGIC SELECT
SEE NOTE 3, 4

DECOUPLING AND GROUNDING

For best accuracy and high speed performance, the grounding and
decoupling scheme shown in Figure 1 should be used. Decoupling
capacitors should be connected close to the HI-5610 (~preferably to
the device pin) and should be tantalum or electrolytic bypassed
with ceramic types for best high frequency noise rejection.

FIGURE 1

6-20

OPEIIATING INSTRUCTIONS (continued)
~IGH

UNIPOLAR - STRAIGHT BINARY
OV TO +2.5V OUTPUT RANGE

PRECISION PERFORMANCE

The output accuracy of the HI-5610 depends mainly on the accuracy of voltage appl,ied to the VREF input, since full scale output
current is approximately 4VREF/BKS1. For precision performance
a +10V voltage reference with reasonably low temperature coefficient such as HA-160B is recommended. For voltage output
operation use an external op amp as' current-to-voltage converter
and the HI-5610 internal scaling resistors as feedback elements.
The selected op amp should have a good front-end temperature coefficient such as HA-2600/2605 with offset voltage and offset
current tempco's of 5J..1V/OC and lnA/OC, respectively. The input
reference resistor (7.975KS11 and bipolar offset resistor (3.975KS11
are both intentionally set low by 25S1to allow the user to externally trim-out initial errors to a very high degree of precision. For
high speed voltage output applications where fast settling is required, the HA-2510/2515 is recommended for better than 1 J..Is
settling to 1/2 LSB.

....CD
Q

."

I

OIGITAL
INPUT'

ANALOG OUTPUT

;

11
10
01
00

••...
.....
.....
.....

1
0
1
0

FS - lLSB
%FS
%FS -ILSB
Zero

= 2.49756V
= 1.25000V
= 1.24756V
= O.OOOOOV

UNIPOLAR VOLTAGE OUTPUT CONNECTIONS AND
CALIBRATION

The connections for unipolar +5V and +2.5V voltage output using
an external op amp and the internal span resistors are shown in
Figure 2 and Figure 3, respectively.
FIGURE,3

CALIBRATION - UNIPOLAR
Step 1 Offset
• Turn all bits off (all O'sl
• Adjust R3 for zero volts output
Step 2 Gain
• Turn all bits on (alil'sl
• Adjust R1 for an output of FS-l LSB
That is, adjust for:
4.99512V for OVto +5V range
2.49756V for OV to +2.5V range

BIPOLAR VOLTAGE OUTPUT CONNECTIONS
AND CALIBRATION

The connections for Bipolar ±. 2.5V and ±. I.Z5V voltage output
using an external op amp and the internal span resistors are shown
in Figure 4 and Figure 5, respectively.
CALIBRATION - BIPOLAR
Step I, Offset:
• Turn all bits off (all O'sl
• Adjust RZ for output voltage as follows:
-2.5V,.±2.5V range
-1.25V,±1.25V range

UNIPOLAR - STRAIGHT BINARY
OV TO +5V OUTPUT RANGE
OIGITAL
INPUT
11
10
01
00

.....
.....
.....
.....

, ANALQG OUTPUT
1
0
1
0

FS -II.,SB
%FS
%FS -ILSB
Zero

.------,C-.

=4~99512V

= 2.500DOV
= 2.49512V
= O.OOOOOV

Step 2, Gain:
• Turn all bits on {all l'sl
• Adjust Rl for an output voltage of (+FS -1 LSBI.
Tliat is:, '
+2.49512V,±2,5V range
+1.24756V,±1.25V range

GAIN

6-21

K!
c(1!:!
'a:
Ow

'i'>
Cz
C
<.:t

OPERA TING INSTRUCTIONS (continued)
BIPOLAR ~QFFSET BINARY
±2.5V OUTPUT VOLTAGE RANGE

I

OIGITAL
INPUT
II,
10
01
00

I ...

....
....
....

....

1
0
1
0

ANALOG
OUTPUT
..

GAIN.'

..

.j.:FS·~ 1 LSB

= +2.49512V
ZERO
=+O.OOOOOV
Zero -1 LSB = -0.00488V
.-FS
= -2.50000V

81POLAR TWO'S COMPLEMENT **
.±2.5V OUTPltT VOLTAGE RANGE
DIGITAL
INPUT

ANALOG OUTPUT .

01 .....
00 .....
It .....
10 .....

1
0
1
:0

+FS -ILSB
Zero
Zero -llSB'
-FS

'. = +2.49512V
. = +O.ooooqv
= -O.00488V
= -2.50000V

FIGURE 4

BIPOLAR - OFFSET BINARY
.± 1.25V OUTPUT VOLTAGE RANGE

GAIN

DIGITAL
INPUT
11
1.0
01
00

.',

ANALOG OUTPUT

...

.....
.....

1
0
1
0

+FS-1LSB
, Zero
Zero.-.l LSB
-FS

= +L24756V
= +O.OQOO.OV
=-0.00244V
= -1.25000V

BIPOLAR - TWO'S COMPLEMENT **
.± 1.25V OUTPUT VOLTAGE RANGE

...

DIGITAL
INPUT
01
00
11
10

.....
.....
.....
.....

ANALOG OUTPUT'
1
0
1

+FS - lLSB
Zero
Zl1ro -1LSB
-FS

= +1.24756V
=+O.OOOOOV
=-0.00244V
= -1.25000V

** Invert MSB with external inverter
to obtain two's complement coding.

FIGURE 5

DIE CHARACTERISTICS
Transistor Count
Die Size:
Thermal Constants;

(j ja
(j jc

Tie Substrate to:
Process:

6-22

138
103 x 209 mils
50 0 CIW
150 CM(
Ground (VREF Lo)
Bipolar - 01

Ii HARRIS

HI·561 BA/561BB
8-Bit High Speed
Digital-to-Analog Converters

al

co
or-

CD

II)

;c
co
or-

CD

FEATURES

II)

-

DESCRIPTION

• VERY FAST SETTLING CURRENT OUTPUT

65ns

• MINIMUM NONLINEARITY ERROR
.::!:.1/4 LSB MAX
HI-5618A
.::!:.1/2 LSB MAX
H1-5618B
340mWTYP

• LOW POWER OPERATION
• ON-CHIP RESISTORS FOR GAIN AND
BIPOLAR OFFSET
• GUARANTEED MONOTONIC OVER
TEMPERATURE
• CMOS, TTL, OR DTL COMPATIBLE

APPLICATIONS
• HIGH SPEED PROCESS CONTROL

I

The HI-5618A1B are very high speed 8 bit current output D/Aconverters.
These monolithic devices are fabricated with dielectrically isolated bipolar
processing, which reduces internal parasitic capacitance to allow fast rise and
fall times. This achieves a typical full scale settling time of 65ns to'::!:'l 12 LSB .
Output glitches are minimized by incorporation of equally weighted current
sources, switched to either an R-2R ladder network or ground for symmetrical
turn ON and turn OFF times. High stability thin film resistors provide excellent accuracy without trimming. For example, the HI-5618A has ± 1/4 LSB
maximum nonlinearity error at +25 0 C, with ±3/8 LSB guaranteed over the full
operating temperature range.
The HI-5618A1B are recommended for any application requiring high speed
and accurate conversions. They can be used in CRT displays and systems
requiring throughput rates as high as 20MHz for full scale transitions. Other
applications include high speed process control, defense systems, avionics, and
space instrumentation.
The HI-5618A-5 and HI-5618B-5 are specified for operation from OOC
to +75 0 C. The "-2" versions are specified from -55 0 C to +125 0 C. The
HI-5618A1B is offered in both commercial and military grades. For additional Hi-Rei screening including 160 hour burn-in, specify the "-8".suffix.

• CRT DISPLAY GENERATION
• HIGH SPEED AID CONVERSION
• WAVEFORM SYNTHESIS
• HIGH RELIABILITY APPLICATIONS

Power requirements are +5V and -15V. Package is an 18 pin ceramic DIP.

FUNCTIONAL DIAGRAM
TOP VIEW
CMOS/TTL

+Vps

BIT 1 MSB

CMOS/TTL

BIT 2

VREF HIGH

BIT3

-Vps

BIT 4

BIPOLAR RIN

BIT 5

lOUT

BIT 6

10 VOLT SPAN

BIT 7

20 VOLT SPAN

BIT 8 LSB

GNO

Ew
,>

ClZ

• VIDEO SIGNAL RECONSTRUCTION

PINOUT

~

1~

VREF LOW
VREF
(LOIN)

6-23

BIT

o
u

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Power Supply Inputs
Reference Inputs
Digital Inputs

(Referred to Ground) (I)

Vps+ . . . . . . . . . . . . . +20V
Vps- . . . . . . . . . . . . . . 20V
VREF (Hi). ........ +16.5V
VREF (La) . . . . . . . . . . . OV

Power 0 issipation* . . . . . . . . . . . . . . . . . . . 1330mW
Operating Temperature Range
HI-5618A/B-2 . . . . . . . . . . . . . . . . -55 0 C to +125 0 C
HI-5618A/B-5 . . . . . . . . . . . . . . . . . . OOC to +750C
HI-5618·A/B-8 . . . . . . . . . . . . . . . -55 0C to+1250C

Bits 1-12 (TTL) ... -IV,+7.5V
Bits 1-12 (CMOS). .. -IV, Vps+
CMOS/TTL Logic Sel-IV, +16.5V
Pins 5, 7, 8. . . . . . . . . . .+Vps
Pin 6 ......... +Vps, -2.5V

Outputs

Storage Temperature Range ......... -650C to +1500C

* Derate 13.3mW/oC above 75 0 C.

ELECTRICAL CHARACTERISTICS

(V ps+ =+5V; Vps - =-15V; VREF

=+IOV; Pin 2 to GND,

H1-5618A/B-2
HI-5618A1B-8

HI-561BA/B-5

I TYP I MAX

TEMP

MIN

Logic "1"
Logic "0"

Full
Full

2.0

Logic "1"
Logic "0"

Full
Full

CMOS Logic Input Voltage (4) Logic "1"
Logic "0"

Full
Full

CMOS Logic Input Current

Full
Full

20
-50

+25 0 C
+25 0 C

Bk
+10

Full

B

PARAMETER

unless otherwise noted)

MIN

ITYP I MAX

UNITS

INPUT CHARACTERISTICS
Digital Inputs (2)
TTL logic Input Voltage (3)
TTL Logic Input Current

Logic "1"
Logic "0"

Reference Input
Input Resistance
Input Voltage (lOUT = 5mA:t 20%)

2.0
O.B
20
-50

500
-100

0.7Vps+

20
-50

O.B

V
V

500
-100

nA
f.l.A

ll.3V ps+

V
V

500
-100

nA
f.l.A

0.7Vps+
0.3V ps+
500
-100

20
-50

n

Bk
+10

V

TRANSFER CHARACTERISTICS
Resolution

B

25 0 C
Full
25 0 C
Full

.£1/4
:t3/B
'±'1/2
:t. 5/B

Initial Accuracy (6)
(Relative to External +10V Reference)
Gain
Unipolar Zero
Bipolar Offset (Neg. Full Scale)

25 0 C
25 0 C
25 0 C

±.2

Temperature ,Stability
Gain Drift
Unipolar Zero Drift
Bipolar Zero Drift

Full
Full
Full

±1/4
:!:.1/16
:!:.1/4

Nonlinearity, Integral and
Differential

HI-561BA
HI-5618B

Settling Time (5) to 1/2 LSB
High Impedance (11)
(from all 0'5 to all 1's)
or (from all 1'5 to all 0'5)

+25 0 C

6-24

65

Bits

'±'1/4
:t. 3/B
.±.1/2
:t.5/B

LSB
LSB
LSB
LSB

:t.2

:t.2

:t 1/8

:t liB
:!:.2

LSB
LSB
LSB

±. 1/4
±. 1116
:!:.1/4

LSB
LSB
LSB

75

ns

75

65

SPECIFICATIONS (Continued)

m

HI-561SA/B-2
HI-561SA/B-S

CO
,...

HI-561SAlB-5

...,

CO
PARAMETER

TEMP

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

;C

TRANSFER CHARACTERISTICS (Continued)

CO
,...

Glitch (5) - Major Carry Transition
Duration
Amplitude (See Fig. 4)
Area

+25 0 C
+25 0 C
+25 0 C

20
350
3500

Power Supply Sensitivity (5)
Vps+ =+5V, Vps- =-13V to
Gain
Unipolar Zero
Bipolar Offset

-16.5V
(Input Code 11 ... 1)
(Input Code 00 ... 0)
(Input Code 00 ... 0)

+25 0 C
+25 0 C
+25 0 C

± 0.5

± 1.5

Vps- =-15V, Vps+ =4.5V to 5.5V
(Input Code 11 ... 1)
Gain
Unipolar Zero
(I nput Code 00 ... 0)
Bipolar Offset
(Input Code 00 ... 0)

+25 0 C
+25 0 C
+25 0 C

'±0.5
±. 1.5.

ns
mV
rnV-ns

20
350
3500

±5

...,

CO

I

±.5
ppm of
FSR/% Vps
(9)

±'0.5
.± 1.5

±5

±.5
±0.5
±. 1.5

OUTPUT CHARACTERISTICS
Output Current

Unipolar
Bipolar

+25 0 C
+25 0 C

-5
±. 2.5

-4
t2.0

-6
'±3.0

-4
:!:2.0

-5
±'2.5

-6
.:!:3.0

rnA
rnA

Output Resistance

+25 0 C

500

500

n

Output Capacitance

+25 0 C

20

20

pF

+25 0 C
+25 0 C
+25 0 C
+25 0 C
+25 0 C

+10
+5
.±10
±.5
.± 2.5

+10
+5
.± 10
±.5
±'2.5

V
V
V
V
V

«w

Output Compliance Voltage (5)

+25 0 C

± 1.5

±. 1.5

V

Cz

Output Noise Voltage (S)

+25 0 C
+25 0 C

30
100

30
100

/.lV p-p
/.lV p-p

Output Voltage Range (7)

Unipolar
Bipolar

O.IHz to 100Hz
O.IHz to lMhz

f:2

6~
_w

,>

8

POWER REQUIREMENTS (4)
Vps+

Full

4.5

5

16.5

4.5

5

16.5

Vps -

Full

-13.5

-15

-16.5

-13.5

-15

-16.5

Ips+ (10) (AliI's or all D's in either
TTL or CMOS mode) (3,4)

+25 0 C
Full

9

Ips- (10) (AliI's or all D's in either
TTL or CMOS mode) (3,4)

+25 0 C

19

Full

1. Absolute maximum ratings are limiting values, applied indiv-

6.

12
26

rnA
rnA

19
26

V
rnA
rnA

9
12

V

These errors may be adjusted to zero using external potentio-

meters R1, R2. Ra. R 1 and A2 each provide more than ± 3
LSB's adjustment. (See Operating Instructions). The specifications listed under initial accuracy are based on use of an

idually, beyond which the serviceability of the circuit may be
Impaired. Functional operation under any of these conditions
is not necessarily implied.

external op amp, internal spa·" and offset resistors, and 100

2. The

H 1-5618 accepts digital input codes in binary format
and may be user connected for anyone of three binary codes.
Straight binary, offset binary, or two's complement binary.
(See operating instructions)

3.

For TTL and DTL co.mjJatibility connect +5V to pin 1 and
ground pin 2. The V ps+ tolerance is ±. 10% for HI-5618A/8
and ±.5% for HI-5618A/B-5.

-2, -8;

7.

Using an external op amp with the internal span and offset
resistors. See Operating Instructions.

8.

Specified for all "1's" or all "O's" digital input.

9.

FSR is "Full Scale Range", i.e., 20V for ± 10V range; 10V
for
5V range, etc. Nominal full scale output current is 5mA.

±

4. For CMOS compatibility based on V ps+ ). 9.5V r (switching
thresholds equal V ps+/2), connect pins 1 and 2. For CMOS
levels below 9.5V. connect pin 2 to ground only (this provides
a threshold of approximately +1.4V).
6. See defin itio"s.

n

.:!:.1% resistors, in place of R1 and R2.

10.

After 30 seconds warm-up.

11.

See Test Circuit, Figure 3.

12.

See Test Circuit. Figure 4.

6-25

DEFINITIONS OF SPECIFICATIONS
ACCURACY

SETTLING TIME

INTEG RAL NONLINEARITY - The maximum deviation of the
actual transfer characteristic from an ideal straight line. The ideal
line is positioned according to "end-point linearity" for D/A
converter products from Harris Semiconductor, i.e; the line is
drawn between the end-points of the actual transfer characteristic
(codes 00 ... 0 and 11. .. ll.

Settling time is the time required for the output to settle to within
the specified errOf band for any input code transition. It is usually
specified for a full scale transition. 0/ A settling time may vary
depending upon the impedance level being driven. A comparator
presents a high impedance, while an op amp connected for current
to voltage conversion presents a low impedance. Figure 3a shows
the test circuit used for testing the HI-5618A1B for TS (OFF)
into a high impedance.

DIFFERENTIAL NONLINEARITY - The difference between one
LSB and the output voltage change corresponding to any two
consecutive codes. A Differential Nonlinearity of ±1 LSB or less
guarantees monotonicity.
MONOTONICITY - The property of a D/A converter's transfer
function which guarantees that the output derivative will not
change sign in response to a sequence of increasing (or decreasing)
input codes. That is, the only output response to a code change is
to remain constant, increase for increasing code, or decrease for
decreasing code.
GAIN DRIFT - The change in full scale analog output over the
specified temperature range expressed in fractional LSB's, or parts
per million of full scale range per oC (ppm of FSR/oC). Gain error
is measured with respect to +250C at high (TH) and low (TLl
temperatures. Gain drift is calculated for both high (TH -25 0C) and
low ranges (+25 0C -TL) by dividing the gain error by the respective
change in temperature. The specification is the larger of the two
representing worst case drift.
ZERO DRIFT - The change in analog output with all bits OFF
over the specified temperature range expressed in parts per million
of full scale range per oC (ppm of FSR/oCl. Zero error is measured
with respect to +25 0C at high (TH) and low (TLl temperatures.
Zero Drift is calculated for high (TH -25 0C) and low (+25 0C
-TLl ranges by dividing the offset error by the respective change
in temperature. The specification given is the larger of the two
representing worst,case drift.

GLITCH

A glitch on the output of a D/A converter is a transient spike resulting from unequal internal ON-OFF switching times. Worst case
glitches usually occur at half-scale or the major carry code transition from OIl. .. 1 to 100... 0 or vice versa. For example, ifturn
ON is greater than turn 0 FF for 100... 1 to 100... 0, an intermediate state of 000 .•. 0 exists, such that, the output momentarily
glitches toward zero output. In general, when a D/A is driven by a
set of external logic gates, the unmatched turn on - turn off times
at the gateswill add to the glitch problem. See Figure 4.
POWER SUPPLY SENSITIVITY

Power Supply Sensitivity is a measure of the change in gain and
offset of the D/A converter resulting from a change in the +5V or
-15V supplies. It is specified under DC conditions and expressed
as parts per million of full scale range per percent of change in
power supply (ppm of FSR/%).
COMPLIANCE VOLTAGE

When the D/A converter is used without an op amp, it may be
configured for various ranges of voltage at its output. However,
Compliance Voltage is the maximum full scale voltage for which
the converter will comply with its specifications.

OPERATING INSTRUCTIONS

CONNECTIONS

DECOUPLING AND GROUNDING

For best accuracy and high speed performance, the grounding
and decouplingscheme shown in Figure 1 should be used. Decoupling capacitors should be connected close to the HI-5618A1B;
preferably to the device pin. A solid tantalum or electrolytic capacitor in parallel with a smaller ceramic type is recommended.

OUTPUT
RANGE

PIN 5
TO

PIN 7
TO

PIN 8
TO

Unipolar
Mode

Oto+l0V
o to +5V

NC
NC

A
A

NC
6

400n
330n

Bipolar

± lOV
±5V

0
0
0

NC
A
A

A
NC

± 2.5V

400n
360n
310n

Mode

6

BIAS
RESISTOR RB

CMOS/TTL

LOGIC SELECT
SEE NOTE 3, 4

V ps _

UNIPOLAR AND BIPOLAR VOLTAGE
OUTPUT CONNECTIONS
FIGURE 2

Make connections as shown in the table and Figure 2, for five
standard output ranges:

6-26

* Used in Bipolar Mode only,
tUsed in Unipolar Mode only.

OFFSET
ADJUST

OPERA TlNG INSTRUCTIONS (continued)

m

The H1-5618A/B accepts an 8 bit digital word in Straight Binary
code. In the bipolar mode this code becomes Offset Binary. Also in
bipolar mode, the MSB may be complemented using an external

inverter to obtain 2's complement code.
outputs for some key input codes:

Here are the correct

....COCD

II)

~

UNIPOLAR - STRAIGHT BINARY
OV TO +10V OUTPUT RANGE

BIPOLAR ~ OFFSET BINARY
± 10V OUTPUT VOLTAGE RANGE

....COCD

II)
I

DIGITAL
INPUT

DIGITAL
INPUT

ANALOG OUTPUT

11 .... . 1
10 .... . 0
01 .... . 1
00 .... . 0

FS -1 LSB
HS
YzFS - 1 LSB
Zero

11 .....
10 .....
01 .....
00 .....

= 9.96094V
= 5.00000V
= 4.96094V
= O.OOOOOV

UNIPOLAR -STRAIGHT BINARY
OV TO +5V OUTPUT RANGE
DIGITAL
INPUT
11
10
01
00

.... .
.... .
.... .
.... .

FS -1 LSB
YzFS
YzFS -1 LSB
Zero

1
0
1
0

+FS-l LSB
Zero
Zero -1 LSB
-FS

=+9.92188V
= +O.OOOOOV
= -0.07813V
= -10.0000V

BIPOLAR - TWO'S COMPLEMENT **
± 10V OUTPUT VOLTAGE RANGE
DIGITAL
INPUT

ANALOG OUTPUT
1
0
1
0

ANALOG OUTPUT

01
00
11
10

= 4.98047V
= 2.50000V
= 2.48047V
= O.OOOOOV

.....
.....
.....
.....

ANALOG OUTPUT
1
0
1
0

+FS - 1 LSB
Zero
Zero -1 LSB
-FS

= +9.92188V
= +O.OOOOOV
= -0.07813V
= -10.0000V

** Invert MSB with external inverter to obtain
two's complement coding.

!@



Q;z

8
Output Accuracy of the HI-5618A1B is affected directly by the reference voltage, since 10(F/S)~4 (VREF/8kil). For precision performance, a stable +10V reference with low temperature coefficient
is recommended.

5 J.iV/OC and lnA/OC, respectively. The input reference resistor
(7.9kn) and bipolar offset resistor (3.9k.il) are both intentionally
set low by 100 n to allow the user to externally trim out initial
errors to a high degree of precision.

The output current may be converted to voltage using an external
op amp with the internal span and offset resistors, as shown above
in the table. The op amp should have good front end temperature
coefficients. For example, the. HA-2600/2605 is well suited to this
application, with offset voltage and offset current tempco's of

For high speed voltage output applications where fast settling is
required, the HA-2510/25 is recommended for settling times better
than 250ns to 1/2 LSB. The HA-5190/95 is recommended for applications requiring settling times less than 150ns. (See Applications).

CALIBRATION (See Figure 2)

UNIPOLAR MODE1. Apply zero (all O's) input, and adjust R3 for OV output.
2. Apply full scale (all 1's) input, and adjust R1 for:
+9.96094 Volts, +10 Volt range
+4.98047 Volts,
+5 Volt range
BIPOLAR MODE1. Apply negative full scale (also called bipolar offsetl: All
O's for offset binary; 1000 .... for 2's complement. Adjust
R2 for output voltages as follows:
-10 Volts,
±10 Volt Range

6-27

-5 Volts,
-2.5 Volts,

.± 5 Volt Range
±2.5 Volt Range

2. Apply positive full scale (all 1's for offset Binary; 0111 ....
for 2's complement) Adjust R1 for output voltages as follows:
+9.92188 Volts,
.± 10 Volt Range
+4.96094 Volts,
±5 Volt Range
+2.48047 Volts,
±2.5 Volt Range
3. Apply zero input (1-1100 .... for offset Binary; 0000....
for 2's complement). Output should be zero volts. Any
error is due to nonlinearity in the DAC, and cannot be
nulled without disrupting the calibration in steps 2 and 3.

TEST CIRCUlTS
SETTLING TIME

Turn-off settling time ("FS(OFF)) is somewhat longer than TS(ON)
for the HI-5618. Typical TS(OFF) performance is shown in Figure
3C, using the circu.it of Figure 3A.
Refer to Figure 3B; Settling time ·following t\lrn-off equals TX
plus TO. The comparator delay To may be measured at 1mV/cm,
using a Tektronix 7A 13 differ~ntial comparator or equivalent.
Th.en, TX is easily measured in a short procedure:
• Adjust delay on generator # 2 for TX approximately 1# s
•

•

Adjust the VLSB supply for 50 percent triggering at COMPo
OUT (equal brightness). .
.

•

OVM reads -1 LSB. Adjust VLSB supply so DVM reads
-1/2 LSB.
Switch the LSB to P (pulse); COMPo OUT pulse disappears.

•
•

Reduce generatQr#2 d~lay until COMPo OUT pulse reappears;
adjust delay for "equal brightness".

•

Measure TX from scope. (Any overshoot will be less than
1/2 LSB, so it is not necessary to examine the other side of the
envelope, i.e. final value plus 1/2 LSB.)

Switch the LSB to +5V (ON).

®
2k

15 3.9k

J'Ul...

7 NC

14

2k

""100kHz

Figure 3A
+3V

®

50%

ov

DIGITAL

I---.jl------------ INPUT

ov
DAC
OUTPUT

®

(TURN OFF! -400mv '

TO;: COMPARATOR DELAY
TX

+3V

®

COMPo
STROBE

OV
"EQUAL BRIGHTNESS"

+3V

COMPo
OUT

@
OV

Figure3B
TCOFFI SETTLING TIME

1LSB

(FULL SCALE TO ZERO TRANSITION.

+25OC

1/2 LSB

114 LSB
1/8 LSB
1/16LSB

I
60

I
75

I
100

I
125

I
160

NANOSECONDS

Figure 3C

6-28

C
175

I
200

I
226

I

260

TEST CIRCUIT (Continued)

m
CO
,....

OUTPUT GLITCH MEASUREMENT
+5V

""I LSB

+5V

",..-.~. ,~

T

4V r I

DV..-J

L

CD

II)

C
CO
,....
CD

II)

I

1

30PF

* ADJUST 500!1TRIMMER SO THAT INPUT SIGNALS
CROSS THEIR RESPECTIVE SWITCHING THRESHOLDS
AT THE SAME TIME.

Figure 4

APPLICATIONS
HIGH SPEED VOLTAGE OUTPUT

HI-5818

+15V

+5V
~-----..,

5

~

* l 11 F

«~
'a:
Ow
'i'>

Cz

8

~~-I-+-Ovo

...-M,.y..-I-~20k

-15V
MATCHEO OUAL N-FET,
MICRO POWER SYSTEMS MP-835
OR EQUIVALENT
• NOMINAL VALUE, SELECTED FOR OPTIMUM STEP RESPONSE.

DIE CHARACTERISTICS
Transistor ,Count
Die Size:
Thermal Constants;

122
103 x 209 mils

9 ja
9jc

Tie Substrate to:
Process:

75 0 C/W
17 oC/W

Ground (VREF Lo)
Bipolar - DI

6-29

JI'-5660/5660A
High Speed Monolithic
Digital-ta-Analog Converter
FEATURES

DESCRIPTION

• MONOLITHIC CONSTRUCTION

The HI-5660 is a current output, 12 bit monolithic digital-toanalog converter. I It offers high' speed plus enhanced accuracy,
through internal cilncellationof ground currents.
'

350ns '

• FAST SETTliNG (TO ±1/2 LSB)

• ±1I2 LSB MAX. NONLINEARITY GUARANTEEO OVER
TEMPERATURE
• INTERNAL CANCELLATION OF GROUNO CURRENT
• EXCELLENT POWER SUPPLY REJECTION

1ppm/%PS

• LOW COST

APPlICA TIONS

Fabrication of the H1-5660 features the Harris bipolar dielectric
isolation process, which eliminates latchup and minimizes parasitic
capacitance and leakage currents. The chip includes nichrome
thin-fil,m resistors, laser frimmed at the wafer level to a maximum
linearity error cif ±1I4 LSB at +25 0 C.
Near zero current in the Analog Ground terminal simplifies use of
the HI-5660 by minimizing noise and offsets between the package
and the system analog ground. This is accomplished by adding a
complement current to the internal ground from an auxiliary
R-2R ladder, and then supplying the resultant OC current from the
positive power supply.
Electrical performance is similar to that of the A0566A. Pinouts
are identical except for pin 1, which requires a +5V supply (versus
no connection on the A0566A).

• HIGH SPEEO A/O CONVERTERS

• WAVEFORM SYNTHESIS

The HI-5660 is offered in two accuracy grades each for the commercial and military temperature ranges. Package is a 24 pin ceramic OIP, and power requirements are ± 12V to +15V.

PINOUT

FUNCTIONAL DIAGRAM

• CRT DISPLAYS

TOP VIEW
24 LEAD DIP
VCC

BIT 1 (MSB) IN

N.C,

BIT 21N

ANALOG GND
AMP SUMMING
JUNCTION

BIT 31N
BIT4IN

VREF (HI IN)

BIBIN

VEE

BIT61N

BIPOLAR R IN

BIT71N

N.C.

BIT BIN

IDAC OUT

BIT 91N

BIPOLAR A IN

.OV
5.

AMP
SUMMING 4'
JUNCTIONo-~----.
5

••

r-t----ll-l---.,-o'DAC
• OUT

.SK

ANALOG 3
OND

o--.lW"----JI::...o-

10V SPAN R
20V SPAN R

10V
10 SPAN R

9.95.

VREFo--.lW'---

Current

Unipolar (All Bits On)
Bipolar (All Bits on or Off)
Resistance (Exclusive of Span Resistors)
Offset
Unipolar
Bipolar (Figure 2, R3 =
50n Fixed)
Capacitance
Compliance Voltage, TM IN to TMAX

-1.6
±0.8
2.0K

-2.0
±1.0
2.5K
.01

-2.4
i1.2
3.0K
..05

.05
25

.15

-3

+12

-1.6
±D.8
2.0K

-2.0
±1.0
2.5K
.01

-2.4
i1.2
3.0K
.05

.05
25

0.10

-3

rnA
rnA

.n

% of FS

+12

% of FS
pF
V

ACCU RACY (Error Relative to
Full Scale)
+25 0 C
TMIN to TMAX

±1/4
(0.006)

±112
(0.012)

il/2
(0.012)
±3/4
(0.018)

±1/8
(0.003)
±1/4
(0.006)

±1/4
(0.006)
±1/2
(0.012)

LSB
% of FS
LSB
% of FS

±3/4

±1/4

.±1I2

LSB

DIFFERENTIAL NONLINEARITY
+25 0 C

±1/2

MONOTONICITY GUARANTEEO (±1 LSB MAX)

TMIN to TMAX
TEMPERATURE COEFFICIENTS

Unipolar Zero
Bipolar Zero
Gain (Full Scale)
Differential Nonlinearity

2
10
10
2

2
10
10
6

ppm/OC
ppm/oC
ppm/OC
ppm/oC

SETTLING TIME TO 112 LSB
With High Z External Load (Note 2)
With 75n External Load

500
250

500
250

6-31

ns
ns

Cz
C
c:.:I

SPECIFICA TlONS (continued)

HI-5660-5
MOOEL

MIN

TYP

HI-5660A-5
MAX

MIN

+75
+150

0
-25

TYP

MAX

UNITS

+75
+150

OC
OC

12

TEMPERATURE RANGE
Operating
Storage

0
-25

POWER REQUIREMENTS
VCC, +4.5V to +16.5VoC
VEE, -11.4 to -16.5VoC

7
-13

12
-17

7
-13

-17

mA
mA

1
1

10
10

1
1

10
10

ppm of FS/%
ppm of FS/%

POWER SUPPLY GAIN SENSITIVITY
VCC=+4.5to+16.5VoC; VEE=-15V
VEE=-11.4to-16.5VoC; VCC=+15V

oto +5
-2.5 to +2.5
oto+l0
-5 to +5
-10 to+l0

PROGRAMMABLE OUTPUT
RANGES (See Table 1)

o to +5
-2.5 to +2.5
Oto+l0
-5 to +5
-10to+l0

V
V
V
V
V

EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50n Resistor
for R2 (Figure 1)
Bipolar Offset Error with Fixed 50n
Resistor for R3 (Figure 2)
Gain Adjustment Range (Figure 1)
Bipolar Offset Adjustment Range (Fig. 2)

.to. 1

iO.25

.to.05

.to.15

iO.25
.to.15

iO.l

iO.25

% of FS

.to.05

±a.l

% of FS
% of FS
%ofFS

20K

24K

n

230

330

mW

iO.25
to.15

REFERENCE INPUT
Input Impedance

16K

POWER DISSIPATION

20K

24K

230

330

16K

MULTIPL YING MODE PERFORMANCE
(All Models)
Quadrants
Two (2): Bipolar Operation at Digital Input Only.
Reference Voltage
Unipolar: +10V Max, +2V Min.
Accuracy
10 Bits (iO.05% of Reduced F.S') for 2VoC Reference Voltage.
Reference Feedthrough (Unipolar Mode,
All Bits OFF, and +2V to +10V (p-p).
Sinewave Frequency for 1/2 LSB
(p-p) Feedthrough)
22kHz Typical
Output Slew. Rate 10%-90%
1.3mA/lls
90%-10%
1.3mA/lls
Output Settling Time (All Bits ON and a
+2V to +10V Step Change in Reference
Voltage)
1.5J.lS to 0.01% F.S.

•

CONTROL AMPLIFIER
Full Power Bandwidth (+ 1OV to +3V)
Small Signal· Closed-Loop Bandwidth

200
2.4

200
2.4

NOTES:
1. The Digital Input Levels are Guaranteed but not Tested Over the Temperature Range.
2. See Settling Time Section.

6-32

kHz
MHz

SPECIFICA TIONS (continued)

«

o

ELECTRICAL CHARACTERISTICS ITA =+25 0 e, Vee =+15V, VEE =-15V, Unless Otherwise Specified)

CD
CD

II)

HI-5660-2,
HI-5660-S
MODEL

MIN

.......

o

HI-5660A-2,
HI-5660A-S

TYP

MAX

MIN

5.5
O.S

2.0
0.0

TYP

CD
CD

MAX

UNITS

5.5
O.S

V
V

10
-50

/lA
/lA

12

Bits

-2.4

±1.2

mA
mA

3.0K
.05

% of FS

.10

% of FS

+12

pF
V

II)
I

DATA INPUTS (Note 1) (Pins 13 to 24)
TTL or 5V CMOS (TMIN to TMAX)
Input Voltage
Bit ON Logic "1"
Bit OFF Logic "0"
Logic Current (Each Bit)
Bit ON Logic "1"
Bit OFF Logic "0"

2.0
0.0
2
-10

2
-10

10
-50

RESOLUTION

12

OUTPUT
Current

Unipolar (All Bits 0,,)
Bipolar (All Bits on or Off)
Resistance (Exclusive of Span Resistors)
Offset
Unipolar
Bipolar (Figure 2, R3 =
5012 Fixed)
Capacitance
Compliance Voltage, TMIN to TMAX

-1.6
±O.S
2.0K

-2.0
±1.0
2.5K
.01

-2.4

±1.2
3.0K
.05

.05
25

-1.6
±D.S
2.0K

.15

-3

+12

-2.0
±1.0
2.5K
.01
.05
25

-3

!1

ACCU RACY (Error Relative to
Full Scale)
+25 0 C
TMIN to TMAX

±1/4

±1/2

±l/S

±1/4

LSB

(0.006)

(0.012)

(0.003)

(0.006)

% of FS

±1/2

±3/4

±1/4

il/2

(0.012)

(O.OlS)

(0.006)

(0.012)

LSB
% of FS

(.)

±1/2

±3/4

±1/4

.±1/2

LSB

MONOTONICITY GUARANTEED (il LSB MAX)

TMIN to TMAX
TEMPERATURE COEFFICIENTS

Unipolar Zero
Bipolar Zero
Gain (Full Scale)
Differential Nonlinearity

1
5
7
2

2
10
10
6

1
5
7
2

2
10
10
2

ppmloC
ppmloC
ppmloC
ppmloC

SETTLING TIME TO 1/2 LSB
With High Z External Load (Note 2)
With 75H External Load

'e:
Ow
'i'>

ClZ
CI

DIFFERENTIAL NONLINEARITY
+25 0 C

~

«~

500
250

500
250

6-33

ns
ns

SPECIFICATIONS (continued)

HI-5660-2,
HI-5660-8
MODEL

MIN

TYP

HI-5660A-2,
HI-5660A-8
MAX

MIN

+125
+150

-55
-65

TYP

MAX

UNITS

+125
+150

oc
oc

12

TEMPERATURE RANGE
Operating
Storage

-55
-65

POWER REQUIREMENTS
VCC, +4.5V to +16.5VOC
VEE, -11.4 to -16.5VD C

7
-13

12
-17

7
-13

-17

mA
mA

1
1

10
10

1
1

10
10

ppm of FS/%
ppm of FS/%

POWER SUPPLY GAIN SENSITIVITY
VCC = +4.5 to +16.5VOC; VEE = -15V
VEE=-11.4to-16.5VDC; VCC=+15V
PROGRAMMABLE OUTPUT
RANGES (See Table 1)

o to +5
-2.5 to +2.5
o to +10
-5 to +5
-10to+l0

o to +5
-2.5 to +2.5
o to +10
-5 to +5
-10to+1O

V
V
V
V
V

EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50n Resistor
for R2 (Figure 1)
Bipolar Offset Error with Fixed 50.\1
Resistor for R3 (Figure 2)
Gain Adjustment Range (Figure 1)
Bipolar Offset Adjustment Range (Fig. 2)

±0.1

to.25

±0.05

to.15

to.l

to.25

% of FS

to.05

±0.1

% of FS
% of FS
% of FS

20K

24K

n

230

330

mW

to.25
to.15

±0.25
to.15

REFERENCE INPUT
Input Impedance

16K

POWER DISSIPATION

20K

24K

230

330

16K

MULTIPLYING MODE PERFORMANCE
(All Models)
Quadrants
Two (2): Bipolar Operation at Digital Input Only.
Reference Voltage
Unipolar: +10V Max, +2V Min.
Accuracy
10 Bits (±0.05% of Reduced F.SJ for 2VDC Reference Voltage.
Reference Feedthrough (Unipolar Mode,
All Bits 0 FF, and +2V to +10V (p-p),
Sinewave Frequency for 1/2 LSB
(p-p) Feedthrough)
22kHz Typical
Output Slew Rate 10%-90%
1.3mA/iJs
90%-10%
1.3mA/iJs
Output Settling Time (All Bits ON and a
+2V to +10V Step Change in Reference
Voltage)
1.5J..1S to 0.01% F.S.
CONTROL AMPLIFIER
Full Power Bandwidth (+10V to +3V)
Small Signal Closed-Loop Bandwidth

200
2.4

200
2.4

NOTES:
1. The Digital Input Levels are Guaranteed but not Tested Over the Temperature Range.
2. See Settling Time Section.

6-34

kHz
MHz

DEFINITIONS OF SPECIFICA TIONS
DIGITAL INPUTS

The H1-5660 accepts digital input codes in binary format and
may be user connected for anyone of three binary codes:
Straight Binary, Two's Complement*, or Offset Binary (See
Operating Instructions).
ANALOG OUTPUT
OIGITAL
INPUT

Straight
Binary

MSB ... LSB
Zero
000 ...000
Y:.FS
100 ... 000
111 ... 111 +FS - 1 LSB
011...111 Y:.FS -- 1 LSB

Offset
Binary

Two's
Complement*

-FS (Full Scale)
Zero
+FS -1 LSB
Zero - 1 LSB

Zero
-FS
Zero - 1 LSB
+FS - 1 LSB

*Invert MSB with external inverter to obtain Two's
Complement Coding

input digital transition, and a window of ±1/2 LSB about the
final value. The device output is then rated according to the
worst (longest settling) case: low to high, or high to low.

«
o

<0
<0
........
I/)

DRIFT

GAIN DRIFT - The change in full scale analog output over the
specified temperature range expressed in parts per million of
full scale range, per oC (ppm of FSR/oC). Gain error is measured with respect to +250C at high (TH) and low (TLl temperatures. Gain drift is calculated for both high (TH -25 0C) and
low ranges (+25 0C -TLl by dividing the gain error by the respective change in temperature. The specification is the larger of
the two representing worst case drift.

o

<0
<0

I/)
I

OFFSET DRIFT - The change in analog output with all bits
OFF over the, specified temperature range expressed in parts
per million of full scale range per oC (ppm of FSR/OC). Offset
error is measured with respect to +25 0C at high (TH) and low
(TLl temperatures. Offset Drift is calculated for both high
(TH" -25 0C) and low (+25 0C -TLl ranges by dividing the offset
error by the respective change in temperature. The specification
given is the larger of the two, representing worst-case drift.·

ACCURACY
POWER SUPPLY SENSITIVITY

INTEGRAL NONLINEARITY - The maximum deviation of
the actual transfer characteristic from an ideal straight line.
The ideal line is positioned according to "end-point linearity"
for O/A converter products from Harris Semiconductor, i. e.
the line is drawn between the end-points of the actual transfer
characteristic (codes 00 ... 0 and 11 ... 1).
OIFFERENTIAL NONLINEARITY - The difference between
one LSB and the output voltage change corresponding to any
two consecutive codes. A Oifferential Nonlinearity of ±1 LSB
or less guarantees monotonicity.
MONOTONICITY - The property of a D/A converter's transfer
function which guarantees that the output derivative will not
change sign in response to a sequence of increasing (or decreasing) input codes. That is, the only output response to a
code change is to remain constant, increase for increasing code,
or decrease for decreasing code.
SETTLING TIME

That interval between application of a digital step input, and
final entry of the analog output within a specified window
about the settled value. Harris Semiconductor usually specifies
a unipolar 10Vfull scale step, to be measured from 50% of the

Power Supply Sensitivity is a measure of the change in gain and
offset of the DIA converter resulting from a change in -15V
or +15V supplies. It is specified under DC conditions and
expressed as parts per million of full scale range per percent of
change in power supply (ppm of FSR/%)'
COMPLIANCE

The HI-5660's current output may be converted to voltage
using the standard connections shown in Figures 1 and 2. The
choice of operational amplifier should be reviewed for each
application, since a significant trade-off may be made between
speed and accuracy.
For highest precision, use an HA-5130. This amplifier contri-

oc:

_UJ

,>

ClZ

Compliance voltage is the maximum output voltage range that
can be tolerated and still maintain its specified accuracy" Compliance limit implies functional operation only and makes no
claims to accuracy"

A glitch on the output of a D/A converter is a transient spike
resulting from unequal internal ON-OFF switching times. Worst
case glitches usually occur at half-scale or the major carry
code transition from 011...1 to 100... 0 or vice versa. For example, if turn ON is greater than turn OFF for 011 ... 1 to
100 ... 0, an intermediate state of 000 ... 0 exists, such that, the
output momentarily glitches toward zero output. Matched
switching times and fast switching will reduce glitches
considerably.

APPLYING THE HI-5660
OP AMP SELECTION

g?

«LLI
,I-

butes negligible error, but requires about 11/.1s to settle within
±Q.l% following a 10V step.
The Harris Semiconductor HA-2600 is the best all-around choice
for this application, and it settles in 1.5J.ls (also to ±0.1% following al0V step). Remember, settling time for the DAC-amplifier
combination isVtD2 + tA 2, where to, tA are settling times for
the DAC and amplifier.

6-35

oc..J

APPl YING THE HI-5660 (continued)
Table 1 - Operating Modes and Calibration

CIRCUIT CONNECTIONS:

MOOE
Unipolar
(See Fig. 1)

Bipolar
(See Fig. 2)

OUTPUT
RANGE

PIN10
TO

oto +10V

Vo

Pin 10

oto +5V

Vo

±10V

CALIBRATION:

PIN 11 RESISTOR
(R)*
TO

APPLY
INPUT CODE

ADJUST

TO SET
Vo

1.43K

All O's
AliI's

Rl
R2

OV
+9.99756V

Pin 9

1.1K

All O's
AliI's

Rl
R2

OV
+4.99878V

NC

Vo

1.69K

All O's
AliI's

R3
R4

-10V
+9.99512V

±5V

Vo

Pin 10

1.43K

All O's
AliI's

R3
R4

-5V
+4.99756V

±2.5V

Vo

Pin 9

1.1K

All O's
All I's

R3
R4

-2.5V
+2.49878V

*Many op amps do not require this resistor, since a bias current of 60nA produces a worst case output
error of only 1 OOJ.N. For a low bias current amplifier, connect its non~inverting input directly to ground.

NO-TRIM OPERATION

The H1-5660 will perform as specified without calibration
adjustments. To operate without calibration, substitute 50 n
resistors for the lOOn trimming potentiometers: In Figure 1
replace R2 with 50n ; also remove the network on pin 7 and
connect 50n to ground. For bipolar operation in Figure 2,
replace R3 and R4 with 50n resistors.
With these changes, performance is guaranteed as shown under
Specifications, "External Adjustments".
Typical unipolar
zero will be ±1/2 LSB plus the op amp offset.
When using wide bandwidth op amps, the feedback capacitor C
may be selected to minimize settling time.
CALIBRATION

Calibration provides the maximum accuracy from a converter
by adjusting its gain and offset errors to zero. For the HI-5660,

these adjustments are similar whether the current output is
used, or whether an external op amp is added to convert this
current to a voltage. Refer to Table 1 for the voltage output
case, along with Figure 1 or 2.
Calibration is a two step process for each of the five output
ranges shown in Table 1. First adjust the negative full scale
(zero for unipolar ranges). This is an offset adjust which translates the output characteristic, i.e. affects each code by the
same amount.
Next adjust positive FS. This is a gain error adjustment, which
rotates the output characteristic about the negative FS value.
For the bipolar ranges, this approach leaves an error at the zero
code, whose maximum value is the same as for integral nonlinearity error. In general, only two values of output may be
calibrated exactly; all others must tolerate some error.
Choosing the extreme end points (plus and minus full scale)
minimizes this distributed err.or for all other codes.

Figure 1 - Unipolar Voltage Output

Figure 2 - Bipolar Voltage Output

6-36

SETTLING TIME


ClZ

o<.J

FUNCTIONAL DIAGRAM VOLTAGE OUTPUT

17

16 24

BIPOLAR

REF

21

IS

22

HI-5680V
HI-5685 V
HI-5687 V

FUNCTIONAL DIAGRAM CURRENT OUTPUT

17

BIPOLAR

16

24

21

22

13

20

REF

SCALING
NeTWORK

HI-5680 I
HI-5685 I
HI-5687 I

6-40

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS
Power Supplv Inputs

Reference
Digital Inputs

+Vs
-Vs
+VLOGIC

o

(1)

CO

+20V
-20V
+20V

Input (pin 16)
Output drain

+Vs
2.5mA

Bits 1 to 12

-lVto+12V

Power Dissipation *

2040mW

(D

.."

I

Operating Temperature Range
HI·56BOI/V·5
Storage Temperature Range

OOC to +75 0 C

:::a:::

-65°C to +150 0 C

*

Derate 20.4mW/oC above 75 0 C

ELECTRICAL CHARACTERISTICS
ITA = +25 0 C, Vs = ±15V, VLOGIC = +5V, PIN 16 CONNECTED TO PIN 24 UNLESS OTHERWISE SPECIFIED.)
HI·56BO
PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

12

Bits

+5.5
+O.B

Volts
Volts

±%
±%
±0.3
±0.15

LSB
LSB
%FSR
%FSR

DIGITAL INPUT (3)
Resolution
Logic Levels
Logic "1"
Logic "0"

TTL Compatible
at+11lA
at -100J.LA

+2
0

ACCURACY (3)
Linearity Error
Differential Lin. Error
Gain Error (2)
Offset Error (2)
Monotonicity

OOC to +75 0 C
OOC to +75 0 C

±l<.
±%
±0.1
±.05
Guaranteed

OOC to +75 0 C

(I)

a:

DRIFT (3)
Total Bipolar Drift
(includes gain, offset
and linearity drifts.)
Total Error
Unipolar (Note 6)
Bipolar (Note 6)
Gain

OOC to


Cz

OOC to

±20

ppm/oC

±O.OB
±0.06

±0.15
±.1

%FSR
%FSR

±15

±30

ppm/oC

±5
,:1:1
±5

±7
:t3
±10

ppm/oC
ppm/oC
ppm/oC

+75 0 C

Including internal
reference
Exclusive of internal
reference

Unipolar Offset
Bipolar Offset
CONVERSION SPEED (3)
Voltage Models
Settling time (3)

to ±0.01% of FSR for
FSR Change

With 10Kn Feedback
With 5Kn Feedback
For 1 LSB change
Slew Rate
Current Models
Settling time (3)

10

3
1.5
1.5
15

Ils
J.Ls
V/Ils

300
1000

ns
ns

/..IS

to ±0.01% of FSR for
FSR Change

10 to lOOn load
lKn load
ANALOG OUTPUT
Voltage Models
Output current
Output Resistance
Short Circuit Duration

rnA

±5
.05
continuous

to common

6-41

n

0

u

SPECIFICATIONS (continued)
HI·5680X
PARAMETER

CONDITIONS

MIN

ANALOG OUTPUT
Current Models
Output Current
Unipolar
Bipolar
Output Resistance
Unipolar
Bipolar
Compliance (3)

-1.6
±0.8

TYP

-2
±1

MAX

-2.4
± 1.2

2.0
2.0
-2.5

INTERNAL REFERENCE
Output Voltage
Output Impedance
External Current
Tempco of Drift

+6.174

+10
+6.3
1.5

+6.426
+2.5

20

POWER SUPPLY
SENSITIVITY (3)
+15V supply
-15V supply
+5Vsupply
POWER SUPPLY
REQUI REMENTS (5)
Range
+15V
-15V
+5V

+11.4
-11.4
+ 4.5

Current
+15V
-15V
+5V

UNITS

mA
mA

Kn
Kn
V
V

n

mA
ppm/oC

.002
.002
.002

~

+15
-15
+5

+16.5
-16.5
+16.5

V
V
V

8
-12
4.5

11
-20
8

mA
mA
mA

%FSR

NOTES:
1. Absolute maximum ratings are limiting values, applied
individually, beyond which the serviceability of the circuit
may be impaired. Functional operation under any of these
conditions is not necessarily implied.
2. Adjustable to zero using external potentiometers.

4. FSR is "Full Scale Range" and is 20V for ± 10V range, 10V
for ± 5V range, etc., or 2mA ( ±. 20%) for current output.
5. The HI-5680 will operate with supply voltages as low as
±. 11.4 V. It is recommended that output voltage range -10V
to +10V not be used if the supply voltages are less than
± 12V.

3. See definitions.
6. With gain and offset errors adjusted to zero at 25 0 C.

DIE CHARACTERISTICS

Transistor Count
Die Size:
Thermal Constants;

8 ja
8jc

Tie Substrate to:
Process :

6-42

259
210x125mils
49 0 C/W
12 oC/W
Ground
Bipolar - 01

DEFINITIONS OF SPECIFICATIONS
DIGITAL INPUTS

ACCURACY

The H1-5680 accepts digital input codes in complementary,
binary, complementary offset binary, and complementary
two's complement binary.

INTEGRAL NONLINEARITY - The maximum deviation of the
actual 'transfer characteristic from an ideal straight line. The
ideal line is positioned according to "end-point linearity" for
D/A converter products from Harris Semiconductor, i.e. the line
is drawn between the end-points of the actual transfer characteristic (codes 00 ... 0 and 11...1).

c

CO
CD

It)

ANALOG OUTPUT

DIGITAL
INPUT

Complementary
Binary

Complementary
Offset
Binary

MSB LSB
000 ...000
100 ...000
111...111
011...111

+ Full Scale
Mid Scale -1 LSB
Zero
+% Full Scale

+ Full Scale
-1 LSB
- Full Scale
Zero

Complementary
Two's
Complement'

I

DIFFERENTIAL NONLINEARITY - The difference between
one LSB and the output voltage change corresponding to any
two consecutive codes. A Differential Nonlinearity of:!:1 LSB or
less guarantees monotonicity.

-LSB

MONOTONICITY - The property of a O/A converter's transfer
function which guarantees that the output derivative will not
change sign in response to a sequence of increasing (or decreasing) input codes. That is, the only output response to a
code change is to remain constant, increase for increasing code,
or decrease for decreasing code.

+ Full Scale

Zero
- Full Scale

• Invert MSB with external inverter to obtain CTC Coding

POWER SUPPLY SENSITIVITY
SETTLING TIME

That interval between application of a digital step input, and
final entry of the analog output within a specified window about
the settled value. Harris Semiconductor usually specifies a
unipolar 10V or bipolar full scale step, to be measured from
50% of the input digital transition, a'nd a window of ±¥.. LSB
about the final value. The device output is then rated according
tll the worst (longest settling) case: low to high, or high to low.

Power Supply Sensitivity is a measure of the change in gain and
offset of the D/A converter resulting from a change in -15V,
or +15V supplies. It is specified under DC conditions and
expressed as parts per million of full scale range per percent of
change in power supply (ppm of FSR/%l.
COMPLIANCE

'0::
Ow

Compliance voltage is the maximum output voltage range that
can be tolerated and still maintain its specified accuracy. Compliance limit implies functional operation only and makes no
claims to accuracy.

DRIFT

GAIN DRIFT - The change in full scale analog output over the
specified temperature range expressed in parts per million of
full scale per °C (ppm of FSR/"C). Gain error is measured with
respect to +25"1: at high (TH) and low (TL) temperatures.
Gain drift is calculated for both high (TH -25°C) and low
ranges (+25OC-h) by dividing the gain error by the respective
change in temperature. The specification is the larger of the
two representing worst case drift.
OFFSET DRIFT - The change in analog ;output with all bits
OFF over the specified temperature range expressed in parts
per million of full scale range per OC (ppm of FSR/"Cl. Offset
error is measured with respect to +25OC at high (TH) and low
(TL) temperatures. Offset Drift is calculated for both high
(TH -25°C) and low (+25OC -h) ranges by dividing the
offset error by the respective change in temperature. The
specification given is the larger of the two, representing worst·
case drift.

,6-43

~
«~

GLITCH

A glitch on the output of a D/A converter is a transient spike
resulting from inequal internal ON-O FF switching times. Worst
case glitches usually occur at half-scale or the major carry code
transition from 011...1 to 100... 0 or vice versa. For example,
if turn ON is greater than turn OFF for 011...1 to 100...0, an
intermediate state of 000 ... 0 exists, such that, the output
momentarily glitches toward zero output. Matched switching
times and fast switching will reduce glitches considerably.
(Measured as one half the product of duration and amplitude.)

'i'>
Cz

8

OPERA T1NGINSTRUCTIONS
CURRENT OUTPUT HI-56801/8SI/871

DECOUPLING AND GROUNDING

For best accuracy and high frequency performance, the. grounding and decoupling scheme shown in Figure 1 should be used.
Oecoupling capacitors should be connected close to the HI·
5680 (preferrably to the device pins) and should be tantalum
or electrolytic bypassed with ceramic types for best high frequency noise rejection.
R2

+vs

-VS~

FIGURE 3

tRa should equal the DAC's output resistance, which is 2Kn//
RFEEDBACK.

EXTERNAL AMPLIFIER CONNECTIONS
To use the HI-56801 with an external amplifier connect as follows:

[

RANGE

PIN 17
10

PIN 18
10

PIN 19
10

PIN 20
10

010+10V
010 +5V
±10V
±5V
±2.5V

N.C.
N.C.
15
15
15

B
B
N.C.
B
B

18*
15
B
18*
15

19*
N.C.
N.C.
19*
N.C.

,.
HI-568DI

16

"'these connections help reduce stray capacitance in the feedback

FIGURE 1

loop.

ANALOG GROUND

GAIN AND OFFSET CALIBRATION

REFE RENCE SUPPLY

An internal 6.3Volt reference is provided on board all HI-5680
models. This voltage (pin 24) is accurate to ±2% and must be
connected to the reference input (pin 16) for specified operation.
This reference may be used externally, provided current drain
is limited to 2.5mA. An external buffer amplifier is recommend·
ed if this reference is to be used to drive other system compon·
ents. Otherwise, variations in the load driven by the reference
will result in gain variations of the HI-5680. All gain adjustments
should be made under constant load conditions.

(Applies to Figure 2 and 3.)
UNIPOLAR CALIBRATION
Step 1:

Offset
Turn all bits OFF (11 ... 1)
Adjust R2 for zero volts out

Step 2:

Gain
Turn all bits 0 N (00 ... 0)
Adjust Rl for FS-l LSB
That Is:
4.9988 for 0 to +5V range
9.9976 for 0 to +1 OV range

Step 1:

0 ffset
Turn all bits OFF (11...1)
Adjust R2 for Negative FS
That Is:
-10V for ± 10V range
-5V for ±5V range
-2.5V for ±2.5 range

VOLTAGE OUTPUT HI-5680V/85V/87V

BIPOLAR CALIBRATION

FIGURE 2

RANGE CONNECTIONS

Step 2: Gain

CONNECT

RANGE

PIN
15

PIN
17

PIN
19

Unipolar

oto +5V
oto + 10V

18
18

N.C.
N.C.

20
N.C.

Bipolar

±2.5V
±5V
±10V

18
18
19

20
20
20

20
N.C.
15

Turn all bits ON (00 ... 0)
Adjust Rl for positive FS-l LSB
That Is:
+9.9951V for ±10V range
+4.9976V for ±5V range
+2.4988V for ±2.5V range
This Bipolar procedure adjusts the output range end points.
The maximum error at zero (half scale) will not' exceed
the Linearity error. See the "Accuracy" specifications.

6-44

mHA.RRIS

HI·5685/5685A



SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Power Supply Inputs

Reference
Digital Inputs

(1)

+20V
+VS
-20V
-VS
+VLDGIC +20V
Input (pin 16) ..!Vs
Output drain 2.5mA
Bits 1 to 12

For functional diagram. definition of

-IV to +12V
specifi~ations

Power Dissipation *
*Derate 20.4mW/oC abov~ 75 0 C
Operating Temperature Range
HI-56851/V-4
HI-5685AI/V-4

2040mW

Storage Temperature Range

-650 to +15O"C

-25 0 Cto +85 0 C
-25"1: to +85"1:

and operating instructions. see the HI-56BO.

ELECTRICAL CHARACTERISTICS
(T A.=+25"1:. Vs = ±15V • VLOGIC = ~V. PIN 16 CONNECTED TO PIN 24 UNLESS OTHERWISE SPECIFIED)
HI-5685
PARAMETER

MIN

CONDITIONS

TYP

MAX

UNITS

DIGITAL INPUT (3)
Resolution
Logic Levels
Logic "1"
Logic "0"
Accuracy (3)
Linearity Error
Differential Lin. Error
Gain Error (2)
Offset Error (2)
Monotonicity

TTL Compatible
at +1 IlA
at -100 pA
at+25 0 C
-25 0 Cto +85 0 C

to.l
±D.05
GUARANTEED

-25 DC to +85 0 C

DRIFT (3) HI-5685
Gain
Offset
Unipolar
Bipolar

-25°C to +85 0 C

DRIFT (3) HI-5685A
(Low Drift)
Gain
Offset
Unipolar
Bipolar

-250C to +85 0 C

CONVERSION SPEED
Voltage Models
Settling Time (3)

+2
0

Bits

+5.5
+0.8

V
V

±%
±%
±%
to.15
±0.1

LSB
LSB
LSB
%FSR (4)
%FSR

±20
±1
±5

.±3
±10

±10

PPM/DC

PPM/oC

±1
±5

to ±0.01% of FSR for
FSR Change

Withl0KilFeedback
With 5KilFeedback
For 1 LSB Change
Slew Rate
Current Models
Settling Time (3)

12

3
1.5
1.5
15

IlS

300
1.0

ns
ps

ps
IlS

V/ ps

to ±0.01% of FSR for
FSR Change

10to 100ilload
lKilload

6-46

SPECIFICATIONS (continued)
c(
II)

HI·5685
. PARAMETER

TYP

MIN

CONOITIONS

UNITS

CD

II)
I I)

ANALOG OUTPUT
Voltage Models
Output Current
Output Impedance (DC)
Current Models
Output Current
Unipolar
Bipolar
Output Resistance
Unipolar
Bipolar
Compliance (3)

co

MAX

co
CD

II)

rnA

±5

n

0.05

I

::I:

Full Scale
-1.6
fO.S

-2
±1

-2.4
±1.2

2.0
2.0
+10

-2.5

rnA
rnA

Kn
Kn
V

INTERNAL REFERENCE
Output voltage
Output Impedance
External Current
Tempco of Drift

+6.174

+6.3
1.5

+6.426

V

n

+2.5
±20

rnA
PPM/oC

+15V

.002

%FSR
./iVs

-15V
+5V

.002
.002

±10

POWER SUPPLY SENSITIVITY (3)

POWER SUPPLY REQUI REMENTS(5)

Cf.)

a:

Range
+15V
-15V
+5V

+11.4
-11.4
+4.5

Current
+15V
-15V
+5V

+15
-15
+5

+16.5
-16.5
+16.5

V
V
V

8
·12
4.5

11
-20
8

rnA
rnA
rnA

NOTES:
1. Absolute· maximum ratings are limiting values, applied
individually, beyond which the serviceability of the circuit
may be impaired. Functional operation under any of these
conditions is not necessarily implied.

4. FSR is "full scale range" and is 20V for ±10V range, 10V
for ±5V range, etc., or 2mA (±20%) for current output.

2. Adjustable to zero using external potentiometers.

5. The HI·5685 will operate with supply voltages as low as
±11.4V. It is recommended that output voltage range -10V
to +lDV not be used if the supply voltages are less than
±12.5V.

3. See Definitions on H·I-5680.

DIE CHARACTERISTICS
Transistor Count
Die Size:
Thermal Constants;

e ja
e jc

Tie Substrate to:
Process:

6-47

259
210 x 125 mils
49 0 C/W
120 CIW
Ground
Bipolar - 01


Cz
C
<.>

m

HI·5687

HARRIS

Wide Temperature Range
Monolithic 12-Bit
Digital-to-Analog Converter

FEATURES

DESCRIPTION

•

DAC87ALTERNATESOURCE

•

MONOLITHIC CONSTRUCTION
(SINGLE CHIP)

•

FAST SETTLING

•

GUARANTEED SPECIFICATIONS

-55 0 Cto 1250 C

•

WAFER LASER TRIMMED

•

APPLICATIONS RESISTORS ON-CHIP

•

ON-BOARD REFERENCE

•

DIELECTRIC ISOLATION (DI) PROCESSING

•

±12V POWER SUPPLY OPERATION

•

MILSTD 883 PROCESSING AVAILABLE

APPLICATIONS

•

HIGH SPEED AID CONVERTERS

•

PRECISION INSTRUMENTATION

•

CRT DISPLAY GENERATION

The HI-5687 is a monolithic direct replacement for the popular
DAC87-CBI wide temperature range d-to-a converter. Single
chip construction, along with several design innovations make
the HI-5687 the optimum choice for low cost, high reliablility
applications.
Harris unique Dielectric Isolation (DI) processing reduces internal parasitics resulting in fast switching times and minimum glitch.
ON board span resistors are provided for good tracking over temperature, and are laser trimmed to high accuracy. These may be used
with the on-board op-amp (voltage output models; HI-5687V),
or with a user supplied external amplifier (HI-56871).
Internally, the HI-5687eliminates code dependent ground currents
by routing current from the positive supply to the internal ground
mode, as determined by an auxiliary R-2R ladder. This results in a
cancellation of code dependent ground currents allowing virtually
zero variation in current through the package common, pin 21.
The H1-5687 is available in both current and voltage output models
which are 100% tested over the -55 0 C to +125 0 C temperature
range. All models include a buried zener reference featuring low
temperature coefficient. In addition, the voltage output models
include an on-board output amplifier. Both versions operate
with a +5V logic supply and a ±VS in the range of ± OI.4V to
16.5V).
Reference HI-5680 for Functional Diagrams, (see pg. 5-40). Definitions of Specifications, (see pg. 5-43). and Operating Instructions, (see pg. 5-44).
For additional Hi-Rei screening including a 160 hour burn-in,
specify the "-8" suffix.

PINOUT
TOP VIEW

TOP VIEW

(MSBI BIT 1

6.3V REF OUT

(MSBI BIT 1

BIT 2

GAIN ADJUST

BIT 2

GAIN ADJUST

BIT 3

+VS

BIT 3

+VS

6.3V REF OUT

BIT4

COMMON

BIT 4

COMMON

BIT 5

..[JUNCTION

BIT 5

SCALING NETWORK

BIT 6

20V RANGE

BIT 6

SCALING NETWORK

BIT 7

10V RANGE

BIT7

SCALING NETWORK

BIT 8

BIPOLAR OFFSET

BIT 8

BIPOLAR OFFSET

BIT 9

REF INPUT

BIT 9

BIT 10

VOUT
-VS

BIT 11
(LSBI BIT 12

LOGIC SUPPL Y

REF INPUT

BIT 10

10

BIT 11

11

lOUT
-VS

(LSBI BIT 12

12

LOGIC SUPPL Y

HI·56B71
CURRENT OUTPUT

VOLTAGE OUTPUT

6-48

,SPECIFICA nONS
ABSOLUTE MAXIMUM RATINGS
Power Supply Inputs

Reference

Digital Inputs

+Vs
-Vs
+VLOGIC

......
(1)

+20V
-20V
+20V

Input (pin 16)
Output drain

± Vs

Bits 1 to 12

-IVto+12V

Power Dissipation'
* Derate 20.4mW/oC abpve 75 0 C
Operating Temperature Range
HI-56871/V-2
HI-56871/V-8

2040mW

Storage Temperature Range

-65"1: to +ISO"!:

2.5mA

CO
CD
It)
I

-55"1: to +125"1:
-550C to +125 0 C

For functional diagram, definition of specifications and operating instructions, see the HI-568D.

ELECTRICAL CHARAC'fERISTICS
ITA=+25 0 C, Vs =±15V, VLOGIC = +5V, PIN 16 CONNECTED TO PIN 24UNLESS OTHERWISE SPECIFIED.)
HI·5687.
PARAMETER

MIN

CONDITIONS

TYP

MAX

UNITS

12

Bits

DIGITAL INPUT (3)
Resolution
logic levels
logic "I"
logic "0"

TTl Compatible
at +lpA
at -IOOpA

+2
0

+5.5
+0.8

V
V

±%
+%

lSB
lSB

±%
±1
±0.2
±O.I

LSB
lSB (4)
%FSR
%FSR

ACCURACY (3)
linearity Error

At +25 0 C
-55°C to +125 0 C

Differential lin. Error

at +25 0 C
-55°C to +125 0C

Gain Error (2)
Offset Error (2)
Monotonicity

±%

±%
±O.!
±0.05
GUARANTEED

-550C to +1250C

en

II:

«LLI

bb:

_UJ

,>

02
0

DRIFt (3)
Total Bipolar Drift
(includes gain, offset
and linearity drifts)

u

-55 0C to +125 0C
±15

±30

ppm/oC

Total Error (NOTE 6)
Unipolar
Bipolar

±0.13
±D.12

±0.3
±D.24

%FSR
%FSR

Gain
including internal
reference

±10

±25

ppm/OC

excluding internal
reference

±5

±10

ppm/oC

Unipolar Offset

±1

±3

ppm/OC

Bipolar Offset

±5

±10

ppm/oC

CONVERSION SPEED
Voltage Models
Settling Time (3)

to ±0.01% of FSR for
FSR Change

With 10K n Feedback
With 5Kn Feedback
For I lSB Change
Slew Rate
Current Models
Settling Time (3)

3
1.5
1.5
15

ps
IlS
IlS

Vips

to ±0.01% of FSR for
FSR Change

10 to lOOn load
IKn load

300
1.0

6-49

ns
IlS

SPECIFICATIONS (continued)
HI·5687
PARAMETER

MIN

CONDITIONS

TYP

MAX

UNITS

ANALOG OUTPUT
Voltage Models
Output Current
Output Impedance (DC)
Current Mo dels
Output Current
Unipolar
Bipolar
Output Resistance
Unipolar
Bipolar
Compliance (3)

+5

mA

on

0.05
Full Scale
-1.6
±0.8

-2
±1

-2.4
±1.2

2.0
2.0
+10

-2.5

mA
mA

Kon
Kn
V'

INTERNAL REFERENCE
Output Voltage
Output Impedance
External Current
Tempco of Drift

+6.174

+6.3
1.5
±5

+6.426
+2.5
±10

V

on

mA
ppm/oC

POWER SUPPLY SENSITIVITY (3)
+15V

±.002

-15V
+5V

±.002
±.002

%FSR

--;rv;-

POWER SUPPLY REQUIREMENTS (5)
Range
+15V
-15V
+5V

+11.4
-11.4
+4.5

Current
+15V
-15V
+5V

+15
-15
+5

+16.5
-16.5
+16.5

V
V
V

8
·12
4.5

11
-20
8

mA
mA
mA

NOTES:
4. FSR is a "full scale range" and is 20V for :!:10V range, 10V
for ±5V range, etc., or 2mA (±20%) for current output.

1. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit
may be impaired. Functional operation under any of these
conditions is not necessarily implied.
2. Adjustable to zero using external potentiometers.

5. The HI-5687 will operate with supply voltages as low as
±11.4V. It is recommended that output voltage ranges-l0V
to +1OV and not be used if the supply voltages are less than
±12.5V.

3. See Definitions.

6. With gain and offset errors adjusted to zero at 250C.

DIE CHARACTERISTICS
Transistor Count
Die Size:
Thermal Constants;

() ja
() jc

Tie Su bstrate to:
Process:

6-50

259
210 x 125 mils
49 0CIW
120CIW
Ground
Bipolar - 01

~ ~RIS

HI-5690V/95V/97V

>
,....
Q)

........

ADVANCED

High Speed, 12 Bit Low Cost Monolithic
Digital-to-Analog Converter

>

it)

~

>
C

Q)

Features

CD

Applications

• Voltage Output with Fast Settling .................................... 7S0ns
High Slew Rate .................................................................. SOV/j1S
• Industry Standard Pinout - AD-DAC 80 & HI-S680 compatible
• Two-Supply Operation ......................................... 11.4V to 16.SV
-11.4V to -16.SV

it)
I

• High Speed AID Converters
• Precision Instrumentation
• CRT Display Generation

• Low Noise Voltage Reference
1/F (O.lHz to 10Hz) .......................................................... 1Sj1Vp-p
•
•
•
•
•

Guaranteed Monotonic Over Full Temperature Range
Application Resistors On-Chip
Monolithic Construction (Single Chip)
Dielectric Isolation (01) Processing
Complete Family of Temperature Grades

Description
The HI-5690V series of complete 12 bit digital to analog
converters includes a low noise, low temperature
coefficient buried zener reference and a fast settling
output amplifier. The series consists of the HI-5690V,
-5695V and -5697V, for the commercial, industrial and
military temperature ranges. Monolithic (Single chip)
construction along with several design innovations make
these converters an optimum choice for high speed, high
reliability applications.
The Harris unique Dielectric Isolation (01) processing rl'lduces internal parasitics, resulting in fast switching times
and minimum glitch. Wafer-level laser trimming of span
resistors and bit current cells ensures high accuracy and
exceptional tracking over temperature.
Internally, the HI-5690V series eliminates code dependent
ground currents by routing current from the positive

Pinout

supply to the internal ground node, as determined by an
auxiliary R-2R ladder. This results in a cancellation of
code dependent ground currents, allowing virtually zero
variation in current through the package common, thus
minimizing analog ground noise seen by the converter.
The HI-5690V series operates from two supplies ±Vs in
the range of ±11.4 Volts to ±16.5 volts. It is pin compatible
with the AD-DAC SO series and HI-56S0 series, and since
Pin 13 is not internally connected (Logic supply on
standard 56S0's) this device is compatible in applications
with or without +5 Volts applied to Pin 13. The converter
performance is guaranteed over the full power supply
operating range, but not all output ranges are available
with low supply voltages. Hi-Rei screening including a
160 hour burn-in, may be specified by adding the suffix -S.
The package is a 24 pin side-brazed, ceramic DIP.

TOP VIEW

(MSB) BIT 1

6.3V REF OUT

BIT 2

GAIN ADJUST

MODEL

INPUT CODE

OUTPUT
MODE

TEMPERATURE
RANGE

BIT 3

3·

+VS

HI1-5690V-5 Complementary Binary

Voltage

OOC to 75 0 C

BIT 4

4

COMMON

HI1-5695V-4 Complementary Binary

Voltage

-250 C to +S50 C

BIT 5

5

LJUNCTION

HI1-5697V-2 Complementary Binary

Voltage

-55 0 C to +125 0 C

BIT 6

6

20V RANGE

HI1-5697V-S* Complementary Binary

Voltage

-55 0 C to +125 0 C

10V RANGE

BIT 7
BIT 8

8

BIPOLAR OFFSET

BIT 9

9

REF INPUT

BIT 10

10

VOUT

BIT 11

11

-VS

(LSB) BIT 12

12

NC

""The suffiX "-8" signifies military high reliability product
With burn-in (160 hours)

6-51

~

«t=!
'e::
Ow

'i'>
Cz

oc..>

Specifications HI-5690V/95V/97V
Absolute Maximum Ratings (Note 1)

Operating Temperature Range

Power Supply Inputs+Vs ............................................. +20V

HI-5690V-5 ..................................................... 0OCto +75 0 C
H 1-5695V-4 ..................................................-25 0 C to +B5 0 C
H 1-5697V-2 ................................................-55 0 C to +1250 C
H 1-5697V-B ................................................-55 0 C to +1250 C
Storage Temperature Range .................. -65 0 C to +150 0 C

-Vs ................................................-20V
Reference
Input (pin 16) +Vs
Analog output can be shorted to common or either
supply. (Note2)
Digital Inputs
Bits 1 to 12 ..................................................... -1V to +12V
Power Dissi pation * ................................................ 2040mW

*Derate 20AmW/oC above 75 0 C

Electrical Characteristics

(Guaranteed over the specified ranges for both temperature and supply voltage unless
otherwise noted. Pin 16 connected to Pin 24, unless otherwise noted. RL; 2Kn)
HI-5690V, HI-5695V, and HI-5697V

PARAMETER
DIGITAL INPUT (Note 3)
Resolution
Logic Levels
Logic '1'
Logic '0'
Input Currents
IIH
IlL
ACCURACY (Note 3)
Linearity Error All grades
HI-5690V, HI-5695V
HI-5697V

CONDITIONS

TTL Compatible
+1J.lA
-100J.lA

+25 0 C

Monotonicity

Offset Error (Note 4)
HI-5690V
HI-5695V, HI-5697V

TYP

MAX

UNITS

12

Bits

+5.5
+O.B

Volts
Volts

+1
-100

J.lA
J.lA

±3/16
±1/5
±1/4

±1/2
±1/2
±3/4

LSB
LSB
LSB

±1/5
±1/5
±1/4

±3/4
±3/4
±1

LSB
LSB
LSB

+2
0

+2V
+O.BV

Differential Lin.Error
HI-5690V
HI-5695V
HI-5697V
Gain Error (Note 4)
HI-5690
HI-5695V
HI-5697V

MIN

Guaranteed
+25 0 C
+25 0 C
+25 0 C

±0.05
±0.05
±0.05

±0.30
±0.20
±0.20

%FSR (5)
%FSR
%FSR

+25 0 C
+25 0 C

±0.02
±0.02

±0.15
±0.10

%FSR
%FSR

±15
±10
±15

±25
±20
±30

ppm/OC
ppm/oC
ppm/OC

±10

±30

ppm/OC

±B
±B

±20
±20

ppm/OC
ppm/oC

THERMAL DRIFT (Note 3)
Total Bipolar Drift (Includes gain,
offset & linearity drifts.)
HI-5690V
HI-5695V
HI-5697V
Gain
HI-5690V
HI-5695V
HI-5697V

6-52

Specifications HI-5690V/95V/97V (Continued)

->
>

I'

m

>

HI-5690V, HI-5695V, and HI-5697V

II)

PARAMETER

CONDITIONS

MIN

Unipolar Offset
Bipolar Offset

±1.5
±5

With 10K Feedback
With 5K Feedback
HI.5690V. HI-5695V
HI-5697V
For 1 LSB change
Slew Rate
ANALOG OUTPUT
Output current
Output Resistance
INTERNAL REFERENCE
Output Voltage
Output Resistance
External Current
Reference Drift
HI-5690V
HI-5695V
HI-5697V
Output Noise at +25 0 C
Wideband
Low Frequency

to ±0.01% of FSR
for FSR Change
FSR = 20V; ±15V
Supplies
FSR = 10V

Major Carry

ppm/oC
ppm/OC

±0.08
±0.10
±0.13

±0.17
±0.20
±0.30

%FSR(4)
%FSR
%FSR

±0.06
±0.09
±0.12

±0.12
±0.12
±0.30

%FSR
%FSR
%FSR

0.9

1.5

{..IS

0.75
0.75
0.50
50

1.2
1.2

{..IS

m

o

m
CD

{..IS
{..IS

VI/ls

±5
DC

mA

n

0.05

12

Cz

8

HI-5690V/95V/97V
NOTES:

1. Absolute maximum ratings are limiting values, applied jndividu~lIy, beyond which the service'ability of the circuit may be impaired.
Functional operation under any of these conditions is not necessarily implied.

2. The output is designed to withstand a temporary short to common or either supply for a mimimum of one minute.
3. See definitions.
4.

Adjustable to zero using external potentiometers,

5.

FSR is "Full Scale Range" and is equal to the fu'll scale output voltage minus th,e zero scale output voltage (Le. 20V for ±10V range,
10V for .±5V range. etc.)

6.

With gain and offset errors adjusted to zero at 25 0C.

7.

The HI-569XV series will operate with supply voltages as low as ±11.4V. It is recommended that output voltage range -1 OV to +10V
not be used if the supply voltages are less than ±13V.

d FSR = FSR (TH) - FSR (+25 0 C)
or FSR (+25 0 C) - FSR (TU

Digital Inputs
The HI-5690V series accepts digital input codes in complementary binary, complementary offset binary, and
complementary two's complement binary.

Vo = Steady-state response to any input code.
Total. Bipolar Drift is the variation of output vOltage with
temperature, in the bipolar mode of operation. It represents the net effect of drift in Gain, Offset, Linearity and
Reference Voltage. Total Bipolar Drift values are calculated, based on measurements as explained above.
Gain and Offset need not be calibrated to zero at +25 0 C.
The specified limits for TBD apply for any input code and
for any power supply setting within the specified operating range .

ANALOG OUTPUT

DIGITAL
INPUT

COMPLEMENTARY
BINARY

COMPLEMENTA.RY
OFFSET
BINARY

COMPLEMENTARY
TWO's
COMPLEMENT"

MSB LSB
000 ... 000
100 ... 000
111 ... 111
011 ... 111

+Full Scale
Mid Scale -1 LSB
Zero
+1/2 Full.Scale

+Full Scale
-1 LSB
-Full Scale
Zero

-LSB
+Full Scale
Zero
-Full Scale

Accuracy
LINEARITY ERROR (Short for "Integral Linearity Error."
Also, sometimes called "Integral Nonlinearity"and "Nonlinearity".)- The maximum deviation of the actual transfer
characteristic from an ideal straight line. The ideal line is
positioned. according to end-point linearity for DIA converter.products from Harris Semiconductor, i.e. the line is
drawn between the end-points of the actual transfer characteristic (codes 00 ... 0 and 11 ... 1).

*Invert MSB with external inverter to obtain GTC Coding

Settling Time
That interval between application of a digital step input,
and final entry of the analog output within a specified window about the settled value. Harris Semiconductor
usually specifies a unipolar 1OV full scale step, to be measured from 50% of the input digital transition, and a window of ±1 12 LSB about the final value. The device output
is then rated according to the worst (longest settling)
case: low to high, or high to low. In a 12 bit system ±1/2
LSB = ±0.012% of FSR.

DIFFERENTIAL LINEARITY ERROR - The difference between one LSB and the output voltage change corresponding to any two consecutive codes. A Differential
Nonlinearity of ±1 LSB or less guarantees monotonicity.

Thermal Drift

MONOTONICITY - The property of a D/A converter's
transfer function which guarantees that the output
derivative will not change sign in response to a sequence
of increasing (or decreasing) input codes. That is, the
only output response to a code change is to remain
constant, increase for increasing code, or decrease for
decreasing code.

Thermal drift is based on measurements at +25 0 C, at high
(TH) and low (TL) temperatures. Drift calculations are
made forthe high (TH-25 0 C) and low (+25 0 C-TL) ranges,
and the larger of the two val ues is given as a specification
representing worstcase drift.
Gain Drift, Offset Drift, Reterence Drift and Total Bipolar
Drift are calculated in parts per million per oC as follows:
Gain Drift = ~ FSRI ~oC
FSR
Offset Drift =

TOTAL ERROR-The net output error resulting from all internal effects (primarily non-ideal Gain, Offset, Linearity
and Reference Voltage). Supply voltages may be set to
any values within the specified operating range. Gain and
offset errors must be calibrated to zero at +25 0 C. Then the
specified limits for Total Error apply for any input code
and for any temperature within the specified operating
range.

x 106

.l Offset! ~oC

FSR

Reference Drift =

~ VREF/~OC

x 10 6

VREF
Total Bipolar Drift=

NOTE: FSR =

~Vo/~oC

Power Supply Sensitivity
x 10 6

Power Supply Sensitivity is a measure of the change in
gain and offset of the D/A converter resulting from a
change in -Vs, or +Vs supplies. It is specified under DC
conditions and expressed as full scale range percent of
change divided by power supply percent change.

FSR

Full Scale Output Voltage
- Zero Scale Output Voltage

6-54

Specifications HI-5690V195V197V

P.S.S. =

>
......

Output Voltage Ranges

~

Full Scale Range x 100
Full Scale Range (Nominal)
~ Vs x 100
Vs (Nominal)

en

;;
en
;;

HI-569XV

II)

Glitch
A glitch on the output of a D/A converter is a transient
spike resulting from unequal internal ON-OFF switching
times. Worst case glitches usually occur at half-scale, i.e.
the major carry code transition from 011...1 to 100... 0 or
vice versa. For example, if turn ON is greater than OFF for
011...1 to 100 ... 0, an intermediate state of 000 ... 0 exists,
such that, the output momentarily glitches toward zero
output. Matched switching times and fast switching will
reduce glitches considerably. (Measured as one half the
product of duration and amplitude.)

,VS!"

3.9."

o

en
CD

II)
-Vs
10K TO lOOK

Figure 2.
RANGE CONNECTIONS
CONNECT

Decoupllng and Grounding

For best accuracy and high frequency performance, the
grounding and decoupling scheme shown in Figure 1
should be used. Decoupling capacitors should be
connected close to the HI-569XV (preferably to the device
pins) and should be tantalum or electrolytic bypassed
with ceramic types for best high frequency nOise
rejection.

PIN
17

o to +5V
o to +10V

18

N.C.

20

18

N.C.

N.C.

±2.5V

18

20

20

±2.5V

18

20

N.C.

±10V

19

20

15

RANGE

Unipolar
Bipolar

PIN
19

PIN
15

Gain and Offset Calibration

UNIPOLAR CALIBRATION
Step 1:

Offset
Turn all bits OFF (11 .. 1)
Adjust R2 for zero volts out

Step 2:

Gain
Turn all bits ON (00 ... 0)
Adjust R1 for FS-1LSB
That is:
4.9988 for 0 to +5V range
9.9976 for 0 to +10V range
BIPOLAR CALIBRATION

Step 1:

Figure 1.

Reference Supply

Offset
Turn all bits OFF (11 ... 1)
Adjust R2 for Negative FS
That Is:
-10V for ±10V range
-5V for ±5V range
-2.5V for ±2.5 range

Step 2: Gain

An internal 6.3 Volt reference is provided on board all
HI-569XV models. This voltage (pin 24) is accurate to
±0.8% and must be connected to the reference input (pin
16) for specified operation'. This reference may be used
externally, provided current drain is limited to 2.5mA. An
external buffer amplifier is recommended if this reference
is to be used to drive other system components.
Otherwise, variations in the load driven by the reference
will result in gain variations of the HI-569XV. All gain
adjustments should 'be made under constant load
conditions.

Turn all bits ON (00 ... 0)
Adjust R1 for positive FS-1 LSB
That is:
+9.9951 V for ±10V range
+4.9976V for ±5V range
+2.4988V for ±2.5V range
This Bipolar procedure adjusts the output range end points. The
maximum error at zero (half scale) will not exceed the Linearity error.
See the "Accuracy" specifications.

6-55

I

HI-5690Vl95V197V' . .
Functional Block Diagram
17

16 24

BIPOLAR

REF

,.

21

22

Ole & Package CharacterIstics
Transistor Count ...................................................................280
Die Size ............................................................... 219 x 123 mils
Thermal Impedance;
Bja ................................................................. 49 0 C/W
Bjc ................................................................ 12oC/W
Tie Substrate to: ............................................................ Ground
Process ....................................................................... Bipolar-DI

6-56

10V

m

HI·5811

HA.RRlS

Complete, Monolithic 12-Bit
Latched Digital-to-Analog Converter

ADVANCED
Features

Applications

• Microcomputer Interface with Double-Buffered
Latches

•
•
•
•

• Single Chip Construction
• Alternate Source for the DAC811

.....
.....
co

it)
I

Microprocessor Controlled Data Acquisition Systems
Precision Instrumentation
Waveform Synthesizers
Industrial Process Control

• 6.3V Reference On-Chip
• Voltage Output: ±10V, ±SV, +10V
• Monotonicity Guaranteed Over Temperature
• Linearity guaranteed over temperature: 1/2 LSB Max
• Guaranteed for Operation with
±12V and ±1SV Supplies
• TTL/SV CMOS-Compatible Logic Inputs

Description
The HI-5811 is a complete, monolithic 12 bit digital-toanalog converter. It includes a preCision voltage reference, microcomputer interface logic, double-buffered
latch and a voltage output amplifier. The DAC features
high speed current switches and a laser-trimmed thin film
resistor network for fast, accurate operation.
The input latch is separated into three independently
controlled 4-bit groups (nibbles), which allows the twelve
input data lines to connect directly to a 4, 8, 12 or 16 bit
bus. 'oata may be either left or right justified. An additional
12 bit latch buffers the internal DAC and blocks conversion of the partial and temporary words which appear
while assembling 12 bits from a narrower data bus. Thus,
the converter output can receive full12 bit updates from a
4 bit or 8 bit data bus. To save computer instructions, the

Pinout

same command may load (strobe) both the D/A latch
and the final input nibble(s).
The HI-5811 is offered in two electrical grades for each of
three operating temperature ranges: J-K, A-B, and R-S
grades for the commercial, industrial, and military ranges.
Each grade is laser-trimmed at the wafer level and guaranteed monotonic over its operating range. The maximum
linearity error at +25 0 C is ±1/4LSB (K, Band S grade) and
±1/2 LSB (J, A and R grades).
Settling Time to ±O.Ol% of full scale is 4J.1s maximum. The
HI-5811 is specified for operation with supplies form ±12V
to ±15V, with a maximum. power dissipation of 800mW.
Package is 28 pin plastic DIP (J and K grades) or a 28 pin
ceramic side-brazed DIP (A, B, R, and S grades).

Functional Diagram
TOP VIEW

VOO +5V

Wii
iJiAc

VREF OUT
BIP. OFFSET
~ JUNCTION

Hi

10V RANGE

NO

VOUT
ACOM
GAIN A~J.
·VCC

NC
011 (MSB)
010
Og

SJ

vour

+VCC

DB

03

07

02

06

01

05

DO (LSB)
OCOM

04

IOV
RF

6-57

~

ccj:!
'cc
Ow
'i'>

Cz

8

Specifications HI-58tt
Absolute Maximum Ratings

Operating Temperature

+vcc to ACOM ..................................................... 0 to +18V
-vcc to ACOM ..................................................... 0 to -18V
VDD to DCOM .........................................................O to +7V
vDD to ACOM ............................................................... ±7V
ACOM to DCOM ........................................................... ±7V
Digital Inputs (pins 2-14,16-19)
to DCOM ......................................................... -O.4V to +18V
External Voltage Applied to 10V Range Resistor .... ±12V
REF OUT.. .................................. lndefinite short to ACOM
External Voltage Applied to DAC Output ........ -5V to +5V
Power Dissipation(A, S, R, S)* ............................. 2000mW
(J, K) (75 0 C) ............................ 1600mW

J, K ................................................................. 0oc to +75 0 C
A, S .............................................. " .............. -25 0 C to +85 0 C
R, S ............................................................-55 0 C to +125 0 C
Storage Temperature (A, S, R, S) ......... -65 0 C to +1500 C
(J, K) ................... -600 C to +100 0 C

Electrical Characteristics
MOOEL
PARAMETER

NOTE:
Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability. Meta/lids of

ceramic packages are connected to

-Vee.

T A = +25 0 C, ±VCC = 12V or 15V unless otherwise noted.

HI-5811A,J
MIN

*Derate 20mW/o C above 750C

TYP

HI-5811B,K
MAX

MIN

HI-5811S

HI-5811R

TYP

MAX

MIN

TYP

MAX

MIN

TYP

UNITS

MAX

INPUT
DIGITAL INPUT
Resolution
Codes

12


Cz
c

u

HI-5811
!!!e~nput I~hesarecontrolled by NA, Ne....NCandWR.
NA, NB, and·Nc are internally NORed with WR so thatthe
l!:!£ut latches transmit data when.E,9th NA (or NB, N.QLand
WR are at logic "0". When either NA (or NB, NC) orWR go
to logic "1", the input data is latched into the input
registers and held until both NA (or NB, NC) andWR go to
logic "0".
The Df A latch is controlled by L5AC and WR. iJ5AC and
WR are internally NORed so that the latches transmit data
to the Df A switches when both 05Ac and WR are at logic
"0". When either L5'AC or WR are at logic "1", t~ata is
latched in the DfA latch and held until LDAC and WR go to
logic "0".
All latches are leveHriggered. Data present when the control signals are logic "0" will enter the latch. When anyone
of the control signals returns to logic "1", the data is
latched. A truth table for all latches is given in Table 2.
TABLE 2.

HI-5811 INTERFACE LOGIC TRUTH TABLE

WR

NA

NB

NC

lDAC

OPERATION

1
0

X
0

X
1

X
1

X
1

No Operation
Enables Input Latch 4
MSB's
Enables Input Latch 4
Middle Bits
Enables Input Latch 4
LSB's
Loads 01 A Latch From
Input Latches
All Latches Transparent

0

1

0

1

1

0

1

1

0

1

0

1

1

1

0

0

0

0

0

0

GAIN AND OFFSET ADJUSTMENTS

Figures 3 and 4 illustrate the relationship of Offset and
Gain adjustments to unipolar and bipolar DfA converter
output.
OFFSET ADJUSTMENT

For unipolar (USB) configurations, apply the digital input
code that should produce zero voltage output and adjust
the Offset potentiometer for zero output. For bipolar
(BOB, BTC) configurations, apply the digital input code
that should produce the maximum negative output voltage and adjust the Offset potentiometer for minus full
scale voltage. Example: If the Full Scale Range is connected for 20V, the maximum negative output voltage is10V. See Table 3 for corresponding codes.

TABLE 3.

DIGITAL INPUT/ANALOG OUTPUT VOLTAGE
ANALOG OUTPUT VOLTAGE

DIGITAL INPUT

Oto+10V

±5V

±10V

12-Bit Resolution
MSB
LSB
111111111111
100000000000
011111111111
000000000000
1LSB

+9.9976V
+5.0000V
+4.9976V
O.OOOOV
2.44mV

+4.99?6V
O.OOOOV
-0.0024V
-5.0000V
2.44mV

+9.9951V
O.OOOOOV
-0.0049
-10.0000V
4.88mV

"X" = Don't Care.

.L

+FULL SCALE

w

~

~ T RANGE
OF
GAIN A~J.

">,..
::>

I!:
::>
:;: RANGE OF

j

~z
_

~

OFFSET AoJ'l

"" OFFSET

A~J.

GAIN A~J.

LOGIC 0

I

1,,-+-----+1:

~~~~~~~TESr

-

ROTATES
THE
LINE

:f 1 I

I

I

LOGIC 1

~. +FULL~CALE T..L

'"~

1LSBJ
FULL SCALE
RANGE

15 _

r....,.>-+--iA~+-t-n-+-+-t

~

~ RANGE OF
"" OFFSET A~J.

OFFSET ADJ.
TRANSLATES

1

~~~;II~LL Y T

FIGURE 4.

±12V OPERATION

DIGITAL INPUT CODE

VERTICALL Y

",..>
,..~
::>
"'"

For either unipolar or bipolar configurations, apply the
digital input that should give the maximum postive
voltage output. Adjust the Gain potentiometer for this
postive full scale voltage. See Table 3 for positive full scale
voltages.

ALL BITS
I ./
.

FIGURE 3. RELATIONSHIP OF OFFSET AND GAIN
ADJUSTMENTS FOR A UNIPOLAR DIA
CONVERTER

w

GAIN ADJUSTMENT

RANGE OF
GAIN A~J.
GAIN ADJ.
ROTATES
THE LINE

~ALLBITS

The HI-5811 is fully specified for operation on ±12V
power supplies. However, in order for the output to swing
to ±10V, the power supplies must be ±13.5V or greater.
When operating with ±12V supplies, the output swing
should be restricted to ±8V in order to meet
specifications.
LOGIC INPUT COMPATIBILITY

The HI-5811 digital inputs are TTL, LSTTL, and 54174HC
CMOS-compatible over the operating range of VDD. The
input switchinQ threshold remains at the TTL threshold
over the supply range.

LOGIC 1

-FULL SCALE

The logic input current over temperature is low enough to
permit driving the HI-5811 directly from the outputs of
4000B and 54174C CMOS devices.

olGITALINPUT CODE

RELATIONSHIP OF OFFSET AND GAIN
ADJUSTMENTS FOR A BIPOLAR DIA
CONVERTER

6-62

HI-58H

Installation
POWER SUPPLY CONNECTIONS
Decoupling: For optimum performance and noise rejection, power supply decoupling capacitors should be
added as shown in the Connection Diagram, Figure 5.

CONNECT FOR
BIPOLAR OPERATION

VOO
VOO
BPO
SUMMING
JUNCTION
VOUT
ACDM
GAIN ADJUST
·VCC
+VCC

~;--J
26
25
24

I

·VCC

10kn TO 100Ko

3.9Mn

12

17

12kOi

3.9Mll

.

~
10kni

+VCC
0.01
_#F

FIGURE 6.

EQUIVALENT RESISTANCES.

I#F

13

OUTPUT RANGE CONNECTIONS
DCOM

Internal scaling resistors provided in the HI-5811 may be
connected to produce bipolar output voltage ranges of
±10V and ±5V or unipolar output voltage range of 0 to
+10V. The 20V range (±10V bipolar range) is internally
connected. Refer to Figure 7. Connections for the output
ranges are listed in Table IV.

-=
FIGURE 5.

O---./'IN"--O

.VCC

20

18

I

~.O

GAIN VCC
ADJUST
10Kn TO 100KO

21

19

CO
Ln

1.0Mn

22

10

Offset and Gain may be trimmed by installing external
Offset and Gain potentiometers. Connect these potentiometers as shown in Figure 5. TCR of the potentiometers
should be 100 ppm/OC or less. The 1.0MO and 3.9MO resistors (20% carbon or better) should be located close to
the HI-5811 to prevent noise pickup. if it is not convenient
to use these high value resistors, an equivalent "T" network, as shown in Figure 6, may be substituted in each
case. The Gain Adjust (pin 22) is a high impedance point
and a 0.001JlF to 0.01JlF ceramic capacitor should be connected from this pin to Analog Common to reduce noise
pickup in all applications, including those not employing
external gain adjustment.

OFFSET
ADJUST

23

II

14

.....
.....

EXTERNAL OFFSET AND GAIN ADJUSTMENT

POWER SUPPLY, GAIN, AND OFFSET
POTENTIOMETER CONNECTIONS.

These capacitors (1JlF tantalum recommended) should
be located close to the HI-5811.

FROM
RBPO
27 BIPOLAR
VOLTAGE O~----.r.N"'-----O OFFSET
REFERENCE
5.36kn
26 SUMMING
.-------------0 JUNCTION
25
.-----QIOV RANGE
4.26kn

The HI-5811 features separate digital and analog power
supply returns to permit optimum connections for low
noise and high speed performance. The Analog Common
(pin 23) and Digital Common (pin 15) should be connected together at one point. Separate returns minimize
current flow in low level signal paths if properly
connected. Logic return currents are not added into the
analog signal return path. A ±0.5V difference between
ACOM and DCOM is permitted for specified operation.
High frequency noise on DCOM with respect to ACOM
may permit noise to be coupled through to the analog output, therefore, some caution is required in applying these
common connections.
The Analog Common is the high quality return for the D/A
converter and should be connected directly to the analog
reference point of the system. The load driven by the output amplifier should be returned to the Analog Common.

6-63

4.26kn
24

'">-.....--~:) VOUT
RESISTOR TOLERANCES ±25%

FIGURE 7. OUTPUT AMPLIFIER VOLTAGE RANGE
SCALING CIRCUIT.
TABLE 4.
Output
Range

o to +10V
±5V
±10V

OUTPUT RANGE CONNECTIONS.
Digital
Input Codes
USB
BOB or BTC
BOB or BTC

Connect
Pin 25 to
24
24
NC

Connect
Pin 27 to
23
26
26

~


ClZ

o
u

HI-5811
Applications

8-BIT INTERFACE

MICROCOMPUTER BUS INTERFACING

The control logic of HI-5811 permits interfacing to rightor left-justified data formats illustrated in Figure 9. When a
12-bit 01 A converter is loaded from an 8-bit bus, two bytes
of data are requi'red. Figures 10 and 11 show an addressing scheme for right-justified and left justified data respectively. The base address is decoded from the highorder address bits. AO and A1 address the appropriate
latches. Note that adjacent addresses are used. For the
right justified case X... X10 loads the 8 LSB's and X... X01
loads the 4 MSB's and simultaneously transfers input
latch data to the 01 A latch. Addresses X... XOO and X... X11
are not used.

The HI-5811 interface logic allows easy interface microcomputer bUB structures. The control signal WA is derived
from external device select logic and the 1/0 Write or
Memory Write (depending upon the system design) signals from the microcomputer.
The latch enable line NA, NB, NC and LOAC determine
which of the latches are enabled. It is permissible to enable two or more· hitches simultaneously as shown in
some of the following examples.
The double-buffered latch permits data to be loaded into
the input latches of several HI-5811 's and later strobed
into the O/A latch of all O/A's Simultaneously updating all
analog outputs. All the interface schemes shown below
use a base address decoder. If blocks of memory are
unused, the base address decoder can be simplified or
eliminated altogether. For instance if half the memory
space is unused, address line A15 of the microcomputer
can be used as the chip select control.

Left-justified data is handled in asimilar manner, shown in
Figure 11, The HI-5811 still occupies two adjacent locations in the microcomputer's memory map.

1x 1x 1x 1x 1011101010910811071061051041031021011001
.a. Right-Justified

.

1011101 QI 091 081 071 0~1 051 041 103 102 101 100 I x I x 1x 1x I
b. Left-Justified

FIGURE 9. 12-BIT DATA FORMATS FOR 8-BIT SYSTEMS.

4-BIT INTERFACE

16

An interface to a 4-bit microcomputer is shown in Figure
8. Each HI-5811 occupies .four address locati.ons. A
74LS139 provides the two t6 four decoder and selects
these with the base address. Memory Write (WA) of the
microcomputer is connected directly to the WR pin of the
HI-5811. A 8205 decoder is an alternative device to use instead of the 74LS139.
16
14

OBO

10

17
13

OBI

9
IB
MICRO COMPUTER

12

OB2

B
IS
11

0B3

10

17
OBI

DO

DB
01
Og

IB
0B2
MICROCOMPUTER·
0B3

DO

084

D4

0B5

DB

086

01

087

B
Ig

02
DID

D3

HI·5811

011
14
13
12
11

D4

D5
06
07

os
Wii

D9
02
06

HI-5Bl1
LDAC

010

4.

D3

Wii

NA

1i8

07
011

WI!

OBO

It-----------------------~~Nc

FIGURE 10. RIGHT-JUSTIFIED DATA BUS INTERFACE.

AN

INTERFACING MULTIPLE HI-5811'SIN
8-BIT SYSTEMS

A2

LOAC
AI

AD

AI

Au

Y2

NA

YI

Na

Yo

iii:

1/274LSI39

FIGURE 8. ADDRESSING AND CONTROL FOR 4-BIT
MICROCOMPUTER INTERI'ACE.

Many applications require that the outputs of several O/A
converters be updated simultaneously such as automatic
test systems. The interface shown in Figure 12 uses a
74LS138 decoder to decode a set of eight adjacent
addresses to load the input latches of four HI-5811 'so The
example shows a right-justified data format.
A ninth address using A3 causes all HI-5811's to. be
updated simultaneously. If a particular HI-5811 is always
loaded last, for instance, 01 A #4, A3 is not needed, thus

HI-S811
saving 8 address spaces for other uses. Incorporate A3
into the Base Address Decoder, remove the inverter, con-

nect the common LDAC line to NC of DI A #4, and connect
G1 of the 74LS138 to +5V.

........
CO
It)
I

14

DBO

13

DB'

12

DB'
OB3

11

10
OU

16

MltRO- 0..
COMPUTER

11

D4

05
06
D7
06
DO
DO

01

KI-51111

010

086

16

D2

01'
D3

Wii
LDAC

FIGURE 11. LEFT-JUSTIFIED DATA BUS INTERFACE

ADDRESS BUS
A3 A2 A,

MICROCOMPUTER

OPERATION

AO

0
0
0
0
0
0
0
0

0
0
0
0

0
0

0
1

LOAD 4 MSB-DI A #1

1

0

LOAD 8 MSB-DI A #2

1

1

LOAD 4 MSB-OI A #2

1
1

0
0

0

LOAD 4 MSB-DI A #3

1

LOAD 4 MSB-OI A #3

1

1

0

LOAD 8 MSB-DI A #4

1

1

1

LOAD 4 MSB-OI A #4

1

X

X

X

LOAD D/A LATCH ALL

LOAD 8 LSB-O/A #1

D/A

.,1-----'1
.,1---------4
AoI------1
' - - _.....
FIGURE 12.

INTERFACING MULTIPLE HI-5811's TO AN
8-BIT BUS

12- AND 16-BIT MICROCOMPUTER INTERFACE
For this application the input latch enables lines, NA, NB,

NC are tied low, causing the latches to be transparent.The
DI A latch, and therefore HI-58.l1 is selected by the address decoder and strobed by WR.

Die Characteristics
690

Transistor Count
Die Size

123 X 134 mils

Thermal Constants Ceramic

IIja 50 0 C/W
IIjc 17 0 C/W

Plastic

IIja 62 0 CIW
IIjc 20 0 C/W

Tie Su bstrate to:

-VCC
Bipolar JI

Process:

6-65

~

<{LU

6~
_LU

,>

02

ot..)

HI.. 7541

mKASlRIS

12-Bit Multiplying
Monolithic Digital-toAnalog Converter

FEATURES

DESCRIPTION

• FULL FOUR QUAORANT MULTIPLICATION
• .01% RELATIVE ACCURACY OVER TEMPERATURE
100pF MAX

• LOW OUTPUT CAPACITANCE
• TIL/CMOS COMPATIBLE

The Harris HI-7541 is a 12-Bit Monolithic Digital to Analog
converter, offering full four quadrant multiplying capability.
The chip features dielectrically isolated CMOS technology
to ,assure fast settling time and freedom from latch-up. Included are thin film ladder and applications resistors, laser trimmed
for accurecy over the full operating temperature range.

• MONOLITHIC CONSTRUCTION
• VERY LOW OUTPUT LEAKAGE CURRENT
•

The H1-7541 is recommended as a high performance direct
replacement for the A07541 device. It operates on a single
+5V to +15V supply and is available in an IS-pin ceramic
package as well as in dice form. For additional Hi-Rei screening
including 160 hour burn-in, specify the "-8" suffix.

±100nA MAX

LOW GAIN ERROR

0.1%

APPLICA TIONS
• PROGMMMABLE GAIN AMPLIFIERS
• PROGRAMMABLE FUNCTION GENERATION

FUNCTIONAL DIAGRAM

PINOUT

TOP

VREF

10UT1

RFEEDBACK

IOUT2

VREF IN

GND
(MSB) BIT 1

VDD+
BIT 12 (LSB)

2.

2.

2.

.,

S2

.11

.,2

BIT 10

BIT4

BIT9

BIT 5

BIT8
81T7

2R

":'

loUT2

BIT11

BIT 2
BIT 3

BIT6

2.

IOUT1
I

BIT1
IMSB)

~
BITZ

81T11

81T12

ILSB)
RFEEDBACK

DIGITAL INPUTS lOll. TIL; CMOSCOMPATIBLEI
LOGIC: A SWITCH IS CLOSED TO IOUT1 fOR ITS

DIGITAL INPUT IN A HIGH (LOGIC 11 STATE.

6-66

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Referred to Ground)l
Power Supply Inputs VDD
Reference Inputs VREF (Hi)
Digital Input Range Bits 1-12

Power Dissipation
Derate above +75 0 C by12.4mW/OC.
Operating Temperature Range
HI-7541SD/TD
HI-7541AD/BD
HI-7541JD/JD/KD
HI-7541SD/883 AND TD/883.
Storage Temperature Range

+17V
:!:25V
VDD to GND

Output Voltage (Pins 1 and 2)

-400mV to VDD

ELECTRICAL CHARACTERISTICS

PARAMETER

1235mW

-55 0 C to +125 0 C
-25 0 C to +85 0 C
OOC to +75 0 C
-55 0 C to +125 0 C
-65 0 C to +150 0 C

(@25 0 C. VDD =+15V. VREF = +10V Unless otherwise noted)

CONDITIONS

INPUT CHARACTERISTICS
Digital Inputs

Bit ON = "Logic 1"
Bit 0 FF = " Logic 0"

Input Voltage
2.4

Logic 1. VIH
Logic 0, VIL
Input Current
Logic 1
Logic 0

2.4

VIN=15V
VIN=OV

Reference Input
Input Resistance
Input Voltage

0.8

0.8

V
V

1
-1

1
-1

p.A
p.A

ct
7
-10

9

12
+10

7
-10

9

Kn

12
+10

ClZ

V

8

TRANSFER CHARACTERISTICS
Resolution

Integral (2)
Nonlinearity
Differential (2)
Nonlinearity
Gain Error (2)
Gain Tempco (2)(5)
Settling Time (2) (5)
to±l/2 LSB
PSRR (2)

Over Full Temp. Range

12

. Bits

12

Over Full Temp Range
Over Full Temp Range
@+25 0 C
Over Full Temp. Range
Over Full Temp. Range

±1/2

±1

LSB

±1/2

LSB

± 16.7
±10

±1
± 12.5
± 16.7
±10

LSB
PPM/DC

1
±.Ol
:.02

1
'±.01
2:.02

p.s
%FSR/oC
%AVDD

±50

!50

nA

±200
100

±200
100
±1

nA
pF
mVpp

+16

I vi

2

mA

±12.5

12.0V~VDD~16.0V

Over Full Temp. Range
OUTPUT CHARACTERISTICS
Output (2)
Leakage Current
Capacitance (2) (5)
Feed Through (2)(5)

VREF = ±10V
@+25 0 C
Over Full Temp. Range

±1

VREF -20 Vpp @10kHz

POWER REQUIREMENTS

II

VDD
100 (3)

(See Fig. 6, 8 & 9)

I

+5

I

6-67

+15

+16
2

+5

+15

I

~

W

6~
_w
,>

I

NOTES:
1. Absolute maximum ratings are limiting values, applied
individually, beyond which the serviceability of the circuit
may be impaired. Functional operation. under any of these
conditions is not necessarily implied.

2.
3.
4.
5.

See Definitions.
After 30 seconds warm-up.
Specification's subject to change
Guaranteed by design, not tested.

without

notice.

DEFINITIONS OF SPECIFICATIONS
unipolar 10V full scale step, to be measured from 50% of the
input digital transition, and a window of ±1/2 LSB about the
final value. The device output is then rated according to the
worst (longest settling) case: low to high, or high to low.

ACCURACY

INTEGRAL NONLINEARITY - The maximum deviation of
the actual transfer characteristic from an ideal straight line.
The ideal line is positioned according to "end-point linearity"
for D/A converter products from Harris Semiconductor, i.e. the
line is drawn between the end-points of the actual transfer
characteristic (codes 00 ... 0 and 11 ... 1).

FEEDTHROUGH ERROR

Variation in VOUT due to variation in VREF, for the condition
all bits OFF (zero output current!.

DIFFERENTIAL NONLINEARITY - The difference between
one LSB and the output voltage change corresponding to any
two consecutive codes. A Differential Nonlinearity of ±1 LSB
or less guarantees monotonicity.

GAIN

The gain is defined only when the MDAC is used with an output
operational amplifier in which case it is VOUT/VREF.
POWER SUPPL Y REJECTION RATIO (PSRR)

MONOTONICITY - The property of a D/A converter's transfer
function which guarantees that the output derivative will not
change sign in response to a sequence of increasing (or decreasing) input codes. That is, the only output response to a
code change is to remain constant, increase for increasing code,
or decrease for decreasing code.

Variation in VOUT due to variation in VDD, expressed in
%FSR/% Vps .
OUTPUT CAPACITANCE

Measured capacity from 10 un or 10 UT2 terminals to ground.

SETTLING TIME

OUTPUT LEAKAGE CURRENT

That interval between application of a digital step input, and
final entry of the analog output within a specified window about
the settled value. Harris Semiconductor usually specifies a

Current leakage to ground from 10 un (all bits low) or 10 UT2
(all bits high) with no connection to the span resistor (Pin 18).

OPERA TING INSTRUCTIONS
BYPASSING AND GROUNDING

For best accuracy and high frequency performance the grounding
and bypass scheme shown in Figure 1 should be used. Bypass
capacitors should be connected close tathe HI-7541 (preferably

to the device pins) .and should be tantalum in parallel with a
smaller ceramic type for best high frequency noise rejection.

Voo+
O,O'jJF
Vps+

Fa

18

HI-7541

O.'/lF
Vps_

FIGURE 1

6-68

OPERA TlNG INSTRUCTIONS

(CONTINUED)

UNIPOLAR BINARY OPERATION

bration of gain will require either R1 (to increase gain) or R2
(to decrease gain), but not both. If both these resistors are
amitted, the gain error is guaranteed not to exceed ±O.15% of
full scale, over the military temperature range. See the "Offset"
section for calibration of the error at zero.

For most applications the HI-7541 requires an output operational amplifier, since both loUrl and IOUT2 should remain
at ground potential to avoid linearity errors. Figure 2 shows the
connections for unipolar straight binary operation. The cali-

RFEEDBACK

BIT 1 (MSBIo----.----1

HI-7541

loun

> ___---VOUT
BIT 12 (LSBI

0-_--'-_--1'5
"-_""""11""""_...... IOUT2

*A Schottky diode to ground should be connected to IOUTl or IOUT2, for any application in which a negative
voltage greater than 400mV may be applied. This can occur with certain high speed op amps, whose inverting
input may offer a low impedance to the negative supply rail during turn-on of power.
For these applications, the HI~7541 output will source excessive current and suffer damage unless it is clamped
with a Schottky diode (such as the HP5082-2811 or equivalent!.

f:2


Oz

FIGURE 2

o(.)

CODE TABLE- UNIPOLAR OPERATION

DIGITAL INPUT
1
1
1
0
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

NOMINAL ANALOG OUTPUT
1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
1
0
1
1
0

-VREF (1 - 2-12)
-VREF (1/2 + 2-12)
-VREF/2
-VREF (1/2 _2-12)
-VREF (2 -12)
0

CODE TABLE - BIPOLAR (OFFSET) OPE-RAIfION

NOMINAL ANALOG OUTPUT

DIGITAL INPUT
1
1
1
0
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

6-69

1
0
0
1
0
0

1
0
0
1
0
0

1
1
0
1
1
0

-VREF ( 1-2-11)
-VREF (2- 11 )
0
VREF (2- 11 )
VREF (1-2-11)
VREF

OPERATING INSTRUCTIONS

(CONTINUED)

BIPOI.AR (4-QUADRANT) BINARY OPERATION

requires eitherR 1 or R2, but not both. The network R3/R5/R7
assures that Vo = OV at tile zero (midrange) code 100000
000000, for which IOUT1 a,nd IOUT2 differ by 1/2 LSB.

Figure 3 shows the configuration for bipolar offset binary
coded operation. As in the unipolar case, gain calibration

VREF~~~~1-----------------------~----------------~

BIT'
MSB

IOUT1

R2° lK

>-----VOUT

HI-1541

IOUT2

BIT 12
LSB

*A Schottky diode to ground should be connected to IOUTl or IOUT2, for any.application in which a negative
voltage greater than 400mV may be applied. This can occur with certain high speed op amps, whose inverting
input may offer a low impedance to the negative supply rail during turn-on of power.
For these applications, the HI-7541 output ,will source excessive current and suffer damage unless it is clamped
with a Schottky diode (such as the HP5082-2811 or equivalent).

FIGURE 3
OFFSET AND GAIN CAI.IBRATION

UNIPOLAR CALIBRATION (Fig. 2)
Step 1:

Unipolar Zero Offset Adjustment
• Turn all bits 0 FF (00... 00)
• Adjust offset trimpot (See Figure 5)
for VOUT =OV.

Step 2:

Unipolar Gain Adjustment
• Turn all bits ON 111 ... 111
• Adjust R1 or R2 for an output of
VOUT =-VREF (1-2- 12)
BIPOLAR CALIBRATION (Fig. 3)

Step 1:
~

Step 2:

B'ipolar Offset Adjustment
• Set VREF =+10V
• Turn all bits OFF (0000 ...00)
• Adjust R5 so that VOUT =10V
Bipolar Gain Adjustment
• Set VREF =+10V
• Turn all bits ON (1111 ...11)
• Adjust Rl or R2 so that YOUr =-9.99512V

6-70

OPERA TING INSTRUCTIONS
SELECTING AN OPERATIONAL AMPLIFIER

The bandwidth of the MDAC itself can be approximated by
modeling it as a voltage source (Vref) followed by a series
resistance (Ro) and capacitance (Co) as in figure 4. The halfpower frequency then is;

The outputs 10UT1 and 10UT2 must remain very close to
ground potential for the H1-7541 to maintain its accuracy.
Because of this constraint, most applications require selection
of a suitable output op-amp. Harris Analog Products Oivision
offers a wide range of high performance op-amps which are
well suited to a variety of applications.

f=
2iTRoCo
If Ro = 10Kfl and Co = 50pf then f = 318KHz. However,
an output amplifier virtually eliminates Co by maintaining
zero volts across it, thus extending the DAC/amplifier bandwidth
almost to that of the amplifier alone.

COMPENSATION

In the standard configurations of Figures 1 and 2 the output
capacitance of the MOACalong with the feedback resistance
introduces a pole in the open loop response of the system.
This pole may cause undesirable phase shift leading to excessive ringing or even oscillation. The phase shift may be compensated by placing a capacitor in the feedback loop. Figure
4 shows this scheme. The compensation is exact for RoCo =
RFB CFB. This is a special case, however, since both Ro and
Co are dependent on the digital code for a CM OS MOAC.

TABLE 1 HARRIS OP AMPS
(TYPICAL AT TA = +25 0 C)
Op Amp
HA-

Full Power
B. W.

Offset
Voltage

Ollset
Voltage

Bias
Current

CFB'
Compensation
for 45 0 P.M.

Drift

A practical approach is to turn all bits of the MOAC ON while
applying a square wave of appropriate magnitude to the reference input.
Then select a feedback capacitor which gives
approximately 20% of overshoot, which is equal to a 45 0 Phase
Margin. This form of compensation reduces the overall bandwidth of the system, which is dependent on the op amp selected.

Settling

Time**

2600

75KHz

500j./V

5j./V/oC

lnA

20pl

1.5j./s

1515

1.6MHz

5mV

30j./V/oC

125nA

l1pl

200ns

5100

150KHz

500/.1 V 5j./V/oC

10pA

lBpl

1.7j./s

5130

600KHz

100j./V lj./V/OC

lnA

30pl

llj./s

5190

6.5MHz

10j./V/oC

5j./A

1pl

70ns

3mV

* For standard configuration such as Figure 3. Vref equals 1 KHz 10V peak to peak
square wave.

MDAC EQUIVALENT
CIRCUIT WITH COMPENSATION

** For the Op Amp alone. AVCL = -1, 10V step to 0.1%.

HI-7541

OFFSET

The amplifier's Offset Voltage VOS contributes a code dependent output error, since VOS is multiplied by a gain factor
(1 + RF/ROUT) in which ROUT is code dependent. ROUT
ranges from 10kSl to 30kSl for nonzero input codes. RF is
10kSl ,which leads to an output error variation of 2/3 VOS
(from 4/3 Vos to 2 Vos).

FIGURE 4
200K

OP AMP PARAMETERS

lOOK

.-.Iw.....~N'~

The addition. of the output amplifier has a direct effect on many
of the MDAC parameters, including bandwidth, settling time,
accuracy and tempco. Settling time is difficult to measure for
the H1-7541 since the current outputs have almost no voltage
compliance. The output settling time of the MDAC-OP AMP
system can be measured; and if the settling time of the Op Amp
itself is known, that of the MDAC can be estimated by the RootSum of Squares method;

HI-7541

E+'5V
20K
-15V

lOOK

FB''------+-------

"">-4-<: VOUT
1--_ _ _IOUT2'r-=-_
__
_+---1
*See Figure 2

FIGURE 5

TMDAC =JT2MDAC/AMP -T2AMP

6-71

OPERATING INSTRUCTIONS (Continued)
This effect applies for offset. introduced at the noninverting
terminal as well as VOS inherent in the amplifier. Therefore, the
common technique of nulling VOS (due to bias current) with a
resistor from the noninverting input to ground is not recommended. Instead, choose an amplifier with low Vos (200IlV
or less) and low IBIAS (75nA or less), and connect the noninverting input directly to ground. The HA-5130 and HA-5170
are recommended for these high accuracy applications.

Output Leakage Current from theHI-7541 flows through the
feedback resistor to create another type of offset error. This
leakage is insignificant except at high temperature, where the
maximum output error is one millivolt. To null this error,
inject an opposing current at the summing junction using a
network as shown in Figure 5. All lead lengths connecting to
IOUT1 should be short, to minimize capacitance to ground and
maintain a fast settling time.

PERFORMANCE CURVES
FEEDTHROUGH ERROR vs. FREQUENCY

GAIN ERROR vs. SUPPLY VOLTAGE
'.0

0.3

~

0.10

0.2

/

.010

0.'

i.I'"
.00

/

,

'K

'00

,.oK

'OK

'M

FREQUENCY Hz

SUPPLY VOLTAGE - VOL T8

FIGURE 6

FIGURE 7

LINEARITY vs. SUPPLY VOLTAGE

SUPPL Y CURRENT vs. SUPPLY VOLTAGE

'.2

,.,

.03

1.0
.9
.8
.02

.7

.6
.5
.4

.0'

.3
.2
.1

'5

'0
SUPPLY VOLTAGE - VOLTS

3

4

5

6

7

8

9

10

'1

12

13

14

SUPPLY VOLTAGE - VOLTS

FIGURE 8

FIGURE 9

DIE CHARACTERISTICS
Transistor Count
Die Size:
Thermal Constants;

Tie Substrate to:
Process:

198

111 x 99 mils

Bja

81 0 C!W

Bic

23 0 C!W

6-72

Ground
CMOS- 01

16

;m~RIS

HI·DAC16BI
DAC16C
16-Bit 0 to A Converter

()

....«>()
«
c

.......
CD

....«>

()

FEATURES

DESCRIPTION

«
c
I

• 16 BIT RESOLUTION
• MONOLITHIC 01 BIPOLAR CONSTRUCTION
• FAST SETTLING TIME
• LOW DIFF. NON LIN. DRIFT
• LOW GAIN DRIFT
• ON-CHIP SPAN OFFSET RESISTORS
COMPATIBLE
• TTL!5V-CMOS
LOW
UNIPOLAR
OFFSET
•
LOW
UNIPOLAR
OFFSETT.C.
•
• EXCELLENT STABILITY

1J1s TO .003%FS

± 0.3ppm/oC
± 1ppm/ oC

&

~ 1/2LSB@+25 0 C

± 0.2ppm/ oC

The HARRIS HI-DAC16 is a 16-bit, current output D/A converter.
Single. chip construction includes thin-film application resistors
for use with an external op amp. These permit standard output
voltage ranges of 0 to +5V, 0 to +10V, ±2.5V, ±5V and ±10V.
The HI-DAC16B is monotonic to 15 bits; and the HI-DAC16C to
14 bits,
Reference and span resistors have adjacent placement on the chip
for optimum match and thermal tracking. Futhermore, this layout
feature helps minimize the superposition error caused by selfheating of the span resistor, reducing it to less than 1/10LSB.
This and other design innovations have produced exceptionally
stable operation over temperature. Typical temperature coefficients
are ± 1ppm/OC for gain error and 0.3ppm/oC for differential nonlinearity error.
The internal architecture is an extension of the earlier HI-562
with several major improvements. All code dependent ground
currents are steered to a separate non-critical path, namely, power
supply ground. This feature allows the precision ground of the
converter to be sensed with virtually zero voltage drop referred to
system ground. The result is the complete elimination of nonlinearities due to code dependent ground currents while yielding an
extremely low unipolar offset of less than 1/2LSB. Because of this
separation, the user may route the precision ground some distance
to the system ground without degrading converter accuracy.

APPlICA TlONS
• HIGH RESOLUTION CONTROL SYSTEMS
• HIGH FIDELITY AUDIO RECONSTRUCTION
• PRECISION FUNCTION GENERATION
AND INSTRUMENTATION

PINOUT

The HARRIS HI-DAC 16 delivers a stable, accurate output without sacrifice in speed. Settling time to within ±0.003% is one
microsecond. Overall performance of this monolithic device should
be attractive for applications such as high fidelity audio and highresolution control systems.

TOP VIEW

-

-VPS 1
40 -P.S. GNO
CONTROL AMP, -IN 2
39 -+VPS
CONTROL AMP,+IN 3
38 _BIT 1 (MSBI
10V SPAN R 4
37 -BIT 2
BIPOLAR O/S 5
36 -BIT 3
lOUT 6
35 _BIT 4
N.C.- 7
34 -BIT5
N.C._ 8
33 _BIT6
20V SPAN R 9
32 _BIT 7
N.C. - 10
31 -BIT 8
VREF IN - 11
30 -BIT 9
ANALOG GND - 12
291- BIT 10
N.C. - 13
281-BIT 11
N.C. - 14
271-BIT 12
N.C.- 15
261-BIT 13
N.C. 16
251- BIT 14
GND TERM 17
241- BIT 15
±5V TERM R 18
231- BIT 16 (LSBI
±10V TERM R 19
221- N.C.
N.C. - '--_
20
_ _ _-211J N.C.

Two accuracy grades are offered, and typical power dissipation is
465mW. Package is a 40 pin ceramic DIP. For further information, see Application Note 539.

6-73

If?

<{LU

6h:

~LU

,>

CO2

co

'-'

11
12
VREF ANALOG
IN
GND

39

4

20V
SPAN R

GROUND
CURRENT
CANCELLATION,
CIRCUIT

J

'

."

-I

2R~12R~12R~12R~1

10K

'f

......

3

---II2RII

RII

I

c::::

lOUT

U

P.S.GND

10K 40

5

CONTR.AMP.+lN
R

~

10V
SPAN R

II

R

o OIS

BIPOLAR

I I

:ae:C")

:::!

c:::.

~

"t::I

s:;

19

Q)

O:!:1OVTERM
SPANR

3.3K

246fl'ljl
:!:.5VTERM
SPAN R
1.42K
17

CONTR.AMP.-IN

*R = 1.25Kfl

2

GNDTERM

~

lit

SPECIFICATIONS

0

CD
.,..

ABSOLUTE MAXIMUM RATINGS (Referred to Ground)
Power Supply Inputs
Reference Inputs
Digital Inputs

Vps+
Vps VREF (Hi)
Bits 1 to IS

Outputs

2440mW

+20V
-20V
:!:,Vps
-lV,+12V

Power Dissipation •
Operating Temperature Range
HI-DAC lSB/C

O"C to +7 5"C

±'vps

Storage Temperature Range

-65"C to +150"C

0

tt:

10
lO

±.3
±0.43

6-75

i5

±.1

/ls

SPECIFICATIONS (Continued)

Glitch (2)

CONDITIONS

MIN

TYP

From 0111 ... 1 to 100.... 0
orl00 ... 0toOll ... 1

Power Supply (2)
Rejection Ratio, PSR R (3)
Vps +
Vps-

I

HI-DAC16C

HI-DAC16B
PARAMETER

MAX

MIN

TYP

MAX

UNITS

1300

1300

mV-ns

1.5
1.5

1.5
1.5

ppm of
FSR/% Vps

~
CHARACTE RISTICS

Output Current
Unipolar
Bipolar

-1.6
±0.8

-2
±1

-2.4
± 1.2

-1.6
±'0.8

-2
±.1

Resistance

2.5k

·2.5k

Capacitance

10

10

oto +5
oto +10

oto +10

±2.5

±2.5

±5
.tl0

±5
±10

Output Voltage Ranges
Unipolar
Bipolar

Using external op amp
and internal scaling
resistors. See Figure 1
and Table 1 for connections

Compliance Limit (2)
Compliance Voltage (2)
Output Noise

mA

pF

oto +5

+10

-3

-2.4
± 1.2

V

+10

-3

V

Full Temperature Range

±1

±.1

V

0.1 to 5MHz (All bits ON)

30

30

INRMS

POWER REUUIREMENTS
Vps+(7)
Vps-

Full Temperature Range

Ips+ (4)
Ips- (4)

All Bits ON or OFF
Full Temperature Range

13.5
-13.5

+15
-15

16.5
-16.5

+13
-18

+18

-25

Power Dissipation

13,5
-13.5

+15
-15

16.5
-16.5

+13
-18

+18

-25

465

465

V

mA
mW

NOTES:
1. Absolute' maximum ratings are limiting values, applied
individually, beyond which the serviceability of the circuit
may be impared. Functional operation under any of these
conditions is not necessarily implied.

4, After 30 seconds warm-up.

2. See Definitions.
3. FSR is "full scale range" and is 20V for±10V range, 10V
for ±5V range, etc., or 2mA (±20%) for current output.

6-76

5. Using an external op amp with internal span resistors and
specified external trim resistors in place of potentiometers
Rl and R2. Errors are adjustable to zero using Rl and R2
potentiometers. (See Operating Instructions Figure 2.)

DEFINITIONS OF SPECIFICATIONS

o
o
«
c

CD
.....
DIGITAL INPUTS

DRIFT

The HI·DAC 16B/C accepts digital input codes in binary format
and may be user connected for anyone of three binary codes.
Straight Binary, Two's Complement, or Offset Binary. (See
Operation Instructions).

GAIN DRIFT - The change in full scale analog output over the
specified temperature range expressed in parts per million of
full scale per "I: (ppm of FSRI"C). Gain error is measured with
respect to +25"1: at high (TH) and low IT LI temperatures.
Gain drift is calculated for both high (TH -25°C) and low
ranges (+25"1:-h) by dividing the gain error by the respective
change in temperature., The specification is the larger of the
two representing worst case drift.

ANALOG OUTPUT
Straight
Binary

DIGITAL
INPUT
MSB LSB
000...000
100... 000
111...111
011 ... 111

Offset
Binary

m
CD
.....
o

«
c

I

OFFSET DRI FT - The change in analog output with all bits
OFF over the specified temperature range expressed in parts
per million of full scale range per "I: (ppm of FSRI"C). Offset
error is measured with respect to +2SOC at high (THland low
(h) temperatures. Offset Drift is calculated for both high
(TH -25°C) and low (+25"1: -h) ranges by dividing the
offset error by the respective change in temperature. The
specification given is the larger of the two, representing worst·
case drift.

Two's
Complement *

·FS 9(Full Scale)
Zero
Zero
Zero
-FS
%FS
Zero - 1 LSB
+FS -1 LSB +FS -1 LSB
%FS-l18B Zero - 1 LSB +FS -1 LSB

*Invert MSB with external inverter to obtain Two's
Complement Coding
POWER SUPPLY SENSITIVITY

ACCURACY

INTEGRAL NONLINEARITY - The maximum deviation ofthe
actual transfer characteristic from an ideal straight line. The
ideal line is positioned according to "end-point linearity" for>
D/A converter products from Harris Semiconductor, i.e. the line
is drawn between the end-points of the actual transfer characteristic (codes 00 ... 0 and 11 ... 11.
DIFFERENTIAL NONLINEARITY - The difference between
one LSB and the output voltage change corresponding to any
two consecutive codes. A Differerftial Nonlinearity of:!:l LSB or
less guarantees monotonicity.
MONOTONICITY - The property of a D/A converter's transfer
function which guarantees that the output derivative will not
change sign in response to a sequence of increasing (or decreasing) input codes. That is, the only output response to a
code change is to remain constant, increase for increasing code,
or decrease for decreasing code.
SETTLING TIME

Settling time is the time required .for the output to settle to
within the specified error band for any input code transition.
It is usually specified for a full scale or major carry transition.

6-77

Power Supply Sensitivity is a measure of the change in gain and
offset of the D/A converter resulting from a change in -15V,
or +15V supplies. It is specified under DC conditions and
expressed as parts per million of full scale range per percent of
change in power supply (ppm of FSR/%1.

~



Cz
cu
COMPLIANCE

Compliance voltage is the maximum output voltage range that
can be tolerated and still maintain its specified accuracy. Com·
pliance limit implies functional operation only and makes no
claims to accuracy.

GLITCH

A glitch on the output of a DI A converter is a transient spike
resulting from unequal internal ON-OFF switching times. Worst
case glitches usually occur at half·scale or the major carry code
transition from 011. .. 1 to 100... 0 or vice versa. For example,
if turn ON is greater than turn OFF for 011 ... 1 to 100... 0, an
intermediate state of 000 ... 0 exists, such that, the output
momentarily glitches toward zero output. Matched switching
times and fast switching will reduce glitches considerably.
(Calculated as the product of duration and amplitude.)

OPERATING INSTRUCTIONS
GAIN AND ZERO CALIBRATION
UNIPOLAR AND BIPOLAR VOLTAGE OUTPUT
CONNECTIONS

FIGURE 1

BIPOLAR
OFFSET
ADJUST

Rl

+15V
100Kn
Y
UNIPOLAR
CO..,
R3 pOKn OFFSET
.
lOOn
6
ADJUST
5'
-15V

.~
4

+15V

The HI-OACI6B/C input reference resistor, bipolar offset
resistor and span resistors are optimized for excellent tracking
over temperature. LASER trimming of the reference circuit
resistors corrects the unipolar Gain and Offset errors to high
accuracy. The remaining error can be adjusted with trimming
Ilotentiorneters. The bipolar Gain and Offset errors are greater
since the LASE R correction is done in the unipolar mode, how·
ever these too are easily adjusted. Figure 1 illustrates the
connections for unipolar and bipolar operation. Trimming
potentiometers RI. R2, and R3 are required for adjustment.
UNIPOLAR CALIBRATION
Step 1:

Offset
_ Turn all bits OFF (00 .. 0)
- Adjust R3 for zero volts output

Step 2:

Gain
_Turn all bits ON (11 .. 1)
- Adjust R2 for an output of
That is, adjust for:

ZOKn! 500Kn 3
RZ
-15V
GAIN
ADJUST

FS~1

LSB

9.999847 for+l0V range
4.999924 for +5V range

BIPOLAR CALIBRATION
TABLE 1

OUTPUT
RANGE

Step 1:

Offset
Turn all bits 0 FF (00 .. 0)
Adjust Rl for an output of
-10Vfor± 10Vrange
-5V for ± 5V range
-2.5V for ± 2.5V range

Step 2:

Gain
Turn all bits ON (11 .. 1)
Adjust R2 for FS·l LSB output
That is, adjust for:

CONNECTIONS
PIN5 PIN4 PIN9 PIN B
to
to
to
to

UNIPOLAR
MODE

oto +10V
oto +5V

0
0

A
A

N.C.
PIN6

19
*

BIPOLAR
MOOE

±10V
±5V
.±2.5V

C
C
C

N.C.
A
A

A
N.C.
6

19
18
*

9.999695 for ± 10V range
4.999847 for ± 5V range
2.499924 for ± 2.5V range .

*Connect an external 1.1 K ohm resistor to ground.

OTHER CONSIDERATIONS

GROUNDS

The HI·OACI6 has two ground terminals, pin 12 (REF GNO)
and pin 40 (PWR GNO). The.se should not be tied together
near the package unless that point is also the system signal
ground to which all returns are connected. (If such a point exists,
then separate paths are required to pins 12 and 40).

6-78

The current through pin 12 is near·zero OC*, but pin 40 carries
up to 1.75mA of code· dependent current from bits 1, 2, and 3.
The general rule is to connect pin 12 directly to the system
signal, or analog ground. Connect pin 40 to the local digital
or power ground. Then, of course, a single path must connect
the analog/signal and digital/power grounds.

OTHER CONSIDERATIONS (Continued)

o
o
«
c
-----...
(0
.,..

*Current cancellation is a two-step process in which codedependent variations are eliminated, then the resulting DC
current is supplied internally_ First, an auxiliary 13-bit R-2 R
Ladder is driven by the complement of the DAC's input code_
Together the main and auxiliary ladders draw a continuous
3_25mA from the internal ground node, regardless of input code_
Part of this 0 C current is supplied by the zener voltage reference, and the remainder is sourced from the positive supply
via a current mirror which is laser trimmed for zero current
through the external terminal (pin 121.

COMPOSITE AMPLIFIER

It is desirable at times to have an output amplifier which
combines the qualities of those op-amps available to the designer_
For instance one may wish to combine the excellent front-end
characteristics of the HA-5130 with the speed of a device such
as the HA-2540 (tsettle =250ns to 0.1%)_ In these instances
there is the option of the composite amplifier_ The basic
configuration is shown in Figure 2_

COMPOSITE AMPLIFIER
LAYOUT

Connections to pin 6 (lOUT) on the HI-DACI6 are most
critical for high speed performance_ Output capacitance of the
DAC is only 10pF, so a small additional capacitance will alter
the op amp's stability and affect settling time_ Connections to
pin 6 should be short and few_ Component leads should be
short on the side connecting to pin 6.

4

SI'ANI-'---------~I_---~

J-1

lr------~.t-'
'0

6

HI DAm

MP'Bl5
OR EQUIVALENT

I5K~~-"""-OVO

~~/
~~,,,o

HA·2540

VO"OVTO+10V

BYPASS CAPACITORS

FIGURE 2

Power supply bypass capacitors on the op amp will serve the
HI-DACI6 also. If no op amp is used, a O.OI/-lF ceramic capacitor from each supply terminal to pin 40 is sufficient, since
supply current variations are small.

THERMAL EFFECTS

A consideration when using the DAC16 is Temperature Stability.
In applications where full scale shift could be a problem, the use
of a heat sink and/or a cooling fan is suggested. This will decrease the magnitude of the total variation by lowering the effective thermal resistance between the package and its environment.
The device should be kept in a stable isothermal environment,
and a warm-up time consistent with accuracy requirements
should be provided.

The composite amplifier may be used to achieve a compromise
depending on the requirements of a design. Trade-offs in performance can be made and the following equations apply:

Offset;

VOFF

=

VOFF2 + VOFFI
AOI

Bias;

IBIAS

=

IBIAS2 + IBIASI

Gain;

Vo

V, = AV(S) = AV2(S)

[1 + AV1(S)]

The amplifier A2 should be of wide bandwidth and fast settling
time.

SELECTING AN OPERATIONAL AMPLIFIER

The HI-DACI6 is a high resolution, high accuracy DAC. Many
applications will require an op-amp used as a current-to-voltage
converter at the DAC output. (Careful consideration should be
given the choice of this amplifier as a poor selection can seriously degrade the inherent qualities of the DAC.)
The HA-5130 is an excellent choice to maintain high accuracy
with an average Offset Drift of only 0.4 f..l V/oC leading to an
error over temperature of 30 f..lV (0.0003% FSR for a 10V FSI.
Initial offset and bias current are 10 f..lV and 3nA respectively,
while input noise current of 0.2pA/.jHZ. Settling time is
adequate for most audio applications. (11 Jls typo to 0.1%).

6-79

DIE CHARACTERISTICS
Transistor Count
Die Size:
Thermal Constants;

Bja
Bjc

Tie Substrate to:
Process:

190
215 x 125 mils
41 0 C/W
11 0 CIW
Analog Ground
Bipolar - 01

m

CD
.,..

o
«
c
I

Product Index

7-2

Ordering Information

7-3

Standard Products
Packaging Availability

7-3

Selection Guide

7-4
!@
~~

Product Information

7-5

~~

:20
~a:

:cc..

cns:2
en

ABSOLUTE MAXIMUM RATINGS
As with all semiconductors, stresses listed under "Absolute Maximum Ratings"
may be applied to devices (one at a time) without resulting in permanent damage.
This is a stress rating only. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. The conditions listed under
"Electrical Characteristics" are the only conditions recommended for
satisfactory operation.

7-1

Product Index
Page
HA-2420-f

200 0 C Sample and Hold Amplifier ........................................................................................ 7-5

HA-2420/2425

Fast Sample and Hold ............................................................................................................. 7-10

HA-5320

High Speed Precision Monolithic Sample and Hold Amplifier .......................................... 7-17

HA-5330

Very High Speed Precision Monolithic Sample and Hold Amplifier ................................. 7-24

HY-9590/91

Data Acquisition Front End Including: Multiplexer, PGA and Sample/Hold Stages ....... 7-28

7-2

Ordering Information
HARRIS PRODUCT CODE EXAMPLE

1

H

-r

T

I M V

Filters
Interface
Memory
Analog, High Voltage

Y

Analog Hybrids

-

2

2420 -

--r-

T

PART NUMBER

TEMPERATURE:
OOC to +200 0 C
-550C to +12S0C
-2S0 C to +8SoC
OOC to +7S 0 C
100% +2S o C Probe (Dice Only)
Dash-7 High Reliability Commercial
Product. OOC to +7So C
8 Dash-B Program
-40 o C to +8SoC

*

PACKAGE:-----....I
Dual-ln~Line, Ceramic

4P

5

*

Dual-In line. Plastic
Leadless Carriers (LeG)
Plastic Leaded Carriers (PLCC)
Lee Hybrid
Mini-DIP, Ceramic
Chip Form

Special high temperature testing available
on certain product types. Consult factory for
availability.

Standard Products Packaging Availability
PACKAGE
TEMPERATURE

PLASTIC
DIP

-5

CERAMIC
DIP
-2

-4

-5

SURFACE MOUNT
PLCC
LCC

-8

-8

X

X

-5

DEVICE NUMBER
SAMPLE AND HOLD
HA-2420
HI-2425

X
X

HI-5320
HI-5330

X
X
X

* Available as MIL-STO-883 only.

7-3

X

X
X

X
X

X

*

*

Selection Guide
SAMPLE AND HOLD
Temp. Range
-55°C

Part
Number

to

Features

+125°

ooc _40°C
to
to
+7S o C +6sOe

HA-2420
HA-2425

Low Charge Transfer
Low Droop Rate

X

X

HA-5320

High Speed Precision
Complete-Includes
Hold Capacitor

X

X

HA-5330

High Speed Precision
Complete-Includes
Hold Capacitor

X

X

Package

Acquisition
Time,
(to 0.01%)
Typ., 250C

Charge
Transfer
Typ., 25 0 C

Aperture
Time
Typ., 25 0 C

Gain
Bandwidth
Product
Typ., 25 0 C

Page

3.2/1s

5pC

30ns

2.5MHz

7-10

1/1s

O.lpC

25ns

2.0MHz

7-17

0,5/1s

0,05pC

20ns

4.5MHz

7-24

14 Pin Cerdip,
Epoxy DIP,
LCC, PLCC
14 Pin Cerdip,
LCC
X

14 Pin Cerdip,
Com

DATA ACQUISITION FRONT END
Temp. Range

Part
Number

-55°C

to

Features

ooc
to

+125 0 C +7S OC

-40°C
to

+ssOe

Package

Acquisition
Time,
(to 0.01%)
Typ., 25 0 C

Droop
Rate
(CH INT.)

Gain
Error
Max.

Effective
Aperture
Delay

Aperture
Uncertainty

CMRR

Page

HY-9590

8-Channel Differential
Mulitplexer,
Programmable Gain
Amplifier,
Precison Sample/Hold

X

X

X

32 Pin
Plastic/or
Ceramic DIP

6/1s

0.08/1V//1s

0,01%

-25ns

0.3ns

70dB

7-28

HY-9591

16-Channel Single
Ended Multiplexer,
Programmable Gain
Amplifier,
Precision Sample/Hold

X

X

X

32 Pin
Plastic/or
Ceramic DIP

6/1s

0.08/1V //1S

0.01%

-25ns

0.3ns

70dB

7-28

7-4

m~RIS

HA·2420·1
High Temperature
Sample and Hold Amplifier

FEATURES

DESCRIPTION

(TA =200 0 C)

• LOW DROOP RATE (CH =0.01/.1F)
• FAST ACQUISITION TIME (±0.01%)
• HIGH SLEW RATE
• WIDE BANDWIDTH
LOW EFFECTIVE APERTURE DELAY TIME
• TTL
• COMPATIBLE CONTROL INPUT

The HA-2420-1 is a monolithic sample-and-hold amplifier guaranteed to operate over the -55 0 C to +200 0 C temperature range. The
circuit consists of a high performance operational amplifier in series
with an ultra low leakage analog switch and a MOSFET input
unity gain output buffer amplifier.

22/.1V//.ls
3.2/.1s
7V//.Is
2.5MHz

With an external holding capacitor connected to the switch output,
a versatile, high performance sample-and-hold circuit is formed.
When the switch is closed, the device behaves as an operational
amplifier, and any of the standard op amp feedback networks may
be connected around the device to control gain, frequency response,
etc. When the switch is opened, the output will remain at its last
level.

30ns

APPlICA TIONS
AND NUCLEAR INSTRUMENTATION
• GEOTHERMAL
OIL
WELL
LOGGING
•
ENGINE MONITORING
• AUTOMOTIVE
A TO 0 CONVERSION SYSTEMS
• o TO A DEGLITCHER
• AUTO
• ZERO SYSTEMS
• PEAK DETECTOR
• GATED OPAMP

Performance as a sample-and-hold at 200 0 C compares very favorably with other monolithic, hybrid and discrete circuits having lower temperature ranges. High slew rate, wide bandwidth, and low
acquisition time provide an excellent dynamic response. The ability to operate at gains other than unity eliminate the need for an
external scaling amplifier.
The device may also be used as a versatile operational amplifier with
a gated output for applications such as analog switches, multiplexed
sample-and-holds, etc.
Power requirement is .:t15V. The package is a 14 pin ceramic DIP.

PINOUT

FUNCTIONAL DIAGRAM
TOP VIEW
IN-

SAMPLE/HOLD
CONTROL

IN+

GND

OFFSET
AOJ.
OFFSET
ADJ.

N.C.

SAMPLE/
HOLD
CONTROL

HOLO
CAP.

v-

N.C.

N.C.

v+

OUT

N.C.

I

-----,
I

~

I

IN-

L--t----- ___C/~ ____ J
HIGH
GAIN
AMP

7-5

HOLD
CAP.

LOW
LEAKAGE
SWITCH

lOUT

I

HIGH
IMPEDANCE
MOSFET
FOLLOWER

....
I

o

N
IIIit
N
I

c(

::l:

SPECIFICA TIONS
ABSOLUTE MAXIMUM RATINGS
Voltage Between V+ and V- Terminals
40V
Differentiall/lput Voltage
±24V
Digital Input Voltage (Pin 14)
+8V,-15V
Output Current
Short Circuit Protected

Internal Power Dissipation*
1500mW
Operating Temperature Range
-55 0 C ~ TA ~ +200 oC
Storage Temperature Range
-650C"" TA ~ +150oC
.*Derate 10.35mW/OC above 75 0 C

ELECTRICAL CHARACTERISTICS Test Conditions (Unless otherwise specified) VSUPPL Y =±15.0V; CH =1000pF;
Digital Input (Pin 14), VI L =+O.8V (Sample), VIH =+2.0V (Hold)

TEMP

PARAMETER
INPUT CHARACTERISTICS
'Offset Voltage
'Bias Current
'Offset Cu~r~nt
Input Resistance
Common Mode Range
TRANSFER CHARACTERISTICS
'Large Signal Voltage Gain (Note 1,4)
'Common Mode Rejection (Note 21
Hold Mode Feedthrough Attenuation (Note B)
Gain Bandwidth Product (Note 3)
OUTPUT CHARACTERISTICS
'Output Voltage Swing (Note 1)
Output Current
Full Power Bandwidth (Note 3, 4)
Output Resistance (O:C.)
TRANSIENT RESPONSE
Rise Time (Note 3, S),
Overshoot (Note 3, S)
Slew Rate (N ote. 3,6)
OIGITAL INPUT CHARACTERISTICS
Digital Input Current (VIN = OV)
Oigitallnput C~rrent (VIN = +S.OV)
Digital Input Voltage (Low)
Digital Input Voltage (High)
SAMPLE/HOLD CHARACTERISTICS
Acquisition Time to .1% 10V Step (Note 3)
Acquisition Time to .01% 10V Step (Note 3)
Aperture Time
Effective Apenure Oelay Time
Aperture Uncertainty Time
"Drift Current (Note 3,

n

"Hold Step Error (Note 7)
POWER SUPPLY CHARACTERISTICS
'Supply Current (+)
"Supply Current (-)
"Power Supply Rejection
NOTES:

+2S OC
Full
+2S oC
Full
+2S oC
·Full
+2S oC
Full

7-6

10

4
6
200
400
SO
100

10
±10
25K
80

Full
+2S OC
+2S oC
+2SOC

tID
tIS

50K
90
-76
2.S

UNITS
. mV
mV
nA
nA
nA
nA
M!2
V
V/V
dB
dB
MHz
V
mA
kHz

100
.15

+2SOC
+2S oC
+2S oC
Full
Full
Full
Full

HA-2420-1
TYP
MAX
2
3
SO

Full
Full
+250C
+2S oC

n

SO
2S

ns
%
V/"s
0.8
20
0.8

2.0

+2S OC
+2S OC
+2SoC
+25 0 C
+2S oC
+25 0 C
Full
+2SoC

2.3
3.2
30
30
S
S
220
9

Full
Full
Full

5.5
4.5

1; RL=2kn
2. VCM = ±10VDC
3. AV = +1, RL = 2kn ,CL = 50pF
4. VOUT = 20V peak-to-peak

"100% Tested

MIN

80

~O

mA

JJA
V
V

"SI'S
SO
15

6

ns
ns
ns
pA
nA
mV
mA
mA
dB

5. VOUT = 200mV peak-to-peak
6. VOUT = 10.0V peak-to-peak
7. VIN=OV
8. fiN';; 100kHz

P'ERFORMANCE CURVES
'f"'"
I

o

VSUPPL Y = ± 15V, CH = 1 ,OOOpF, TA = +2000 C, unless otherwise specified.

N

"I:t

N

I

«
J:

HOLD STEP VOLTAGE *
VS.
HOLD CAPACITANCE

TYPICAL PERFORMANCE
VS.
HOLD CAPACITANCE
10.000 ............- - - - - - - - - - ,

-50-r---------------,
VIN =0 VOLTS

1,000
100

-30

-20

101--_-.:~::;:.~~-_

-10
1.0
1,OOOpF

100pf

0.1

O.01p.F

O.1pf

2.0~F

+--,--.---.-.,.---1

0.01
10pF

100pf 1,OOOpF O.01}tF O.1I-'F 1.0J,i.f
CH VALUE

DRIFT CURRENT
VS,
TEMPERATURE
HOLD STEP VOLTAGE
VS.
INPUT VOLTAGE

*

/

100nA

CH '" 1.000pF
TEMP = 2000C

1/

10nA

PEDESTAL *
VOLTAGE -10

(mVl

-----------

/

1.DnA

-20+----.----.,-----.-----l
-10

-5

0

+5

+10

./

D.lnA

INPUT VOLTAGE (VOLTS)

I
25 0

*Hold step voltage is the output error
following a switch from sample to hold.

7-7

500

750
1000 1250 15()O
TEMPERATURE OC

1750

2000

APPLICATIONS
dielectric for the bypass and hold capacitors. In addition,
the holding capacitor should have extremely high inSUlation
resistance ancj low dielectric absorption.

Operation of the HA-2420-1 at +200 0 C is similar to that of
the -2 version at +125 0 C. Most of the maximum limits are
the same, except for slight increases in supply and input bias
currents, and a 55X increase in drift current. (Drift current
is responsible for voltage droop error in the HOLD mode.)
At high temperatures, a guard ring is essential, to counteract
the increased flow of drift current from the hold capacitor.
See Figure 2.

Figure 1 shows a typical unity gain circuit, with Offset
Zeroing. All of the other normal op amp feedback configurations may be used with the HA-2420-1. The input amplifier may be.!lsed as a gated amplifier by utilizing Pin 11 as
the output. This amplifier has excellent drive capabilities
along with exceptionally low swi.tch leakage.

The components .and materials external to this integrated
circuit must carry a similar qualification for high temperature operation. TEFLON@* wire insulation and a TEFLON
IC socket (if used) are recommended, along with TEFLON

For more applications, consult Harris Application Note 517,
or factory applications group.

GUARD RING LAYOUT

BASIC SAMPLE-AND-HOLD

(BOTTOM VIEW)

(TOP VIEW)

OUT

Figure 2

Figure 1

GLOSSARY OF TERMS
EADT may be positive, negative or zero. If zero, the S/H
amplifier will output a voltage equal to VIN at the instant
the Hold command was received. For negative EADT, the
output in Hold (exclusive of pedestal and droop errors)
will correspond to a value of VIN that occurred before
the Hold command.

ACQUISITION TIME:

The time required following a "sample" command, for the
output to reach its final value within ± 0.1% or ±. 0.01%.
This is the minimum sample time required to obtain a given
accuracy, and includes switch delay time, slewing time
and settling time.

APERTURE UNCERTAINTY:

APERTURE TIME:

The range of variation in Effective Aperture Delay Time.
Aperture Uncertainty (also called Aperture Oelay Uncertainty, Aperture Time Jitter, etc.) sets a limit on the accuracy with which a waveform can be reconstructed from
sample data.

The time required for the sample-and-hold switch to open,
independent of delays through the switch driver and input
amplifier circuitry. The switch opening time is that interval
between the conditions of 10% open and 90% open.
EFFECTIVE APERTURE DELAY TIME (EADT):

DRIFT CURRENT:

The difference between propagation time from the analog
input to the S/H switch, and digital delay time between
the Hold command and opening of the switch.

The net leakage current from the hold capacitor during the
hold mode. Drift current can be calculated from the droop
rate using the formula:
e:.V
ID (pA) = CH (pF) x (Volts/sec)

LH

TEFLON is a registered trademark of Dupont Corporation

7-8

SCHEMATIC
?I

o

OFF SET ADJ

r-------~----~~~--~--~--_+--~~+_~~------------------~_.~~--~----------_+----_ov.

N
'o::t
N
I


II.

0

30

0
0

20

oJ

10

zW

~

90
80

"""- "
""I""""
" "
"'~

CH = 100pF
~CH=1000pF

~

CH = .01/1F

,,~

'\

10-

"" """' .""'"'~' '

CH = 1.01lF

CH=O.IIlF~

"-....... ~ ~

II.

0

~

-10

&

""-~

-20
-30

/

10

100

lK

V

10K

lOOK

1M

~

10M

100M

FREQUENCY. Hz

f-~ J.-50

+25
+50
T(OC)

-25

+75

+100

+125

OPEN LOOP PHASE RESPONSE
HOLD MODE FEED THROUGH ATTENUATION
CH - 1000pF

-

faw

-30

ffi

i.

-40
-50

V

-60
-70

/

60

~.

80

:i!

100
120

II.

140
160

~

§

-80

CH -1000pF

>- ..... CH =1.01lF

V / ''"\
/i

'< R',,--,cr;; 100P

40

l!::
"

/

~I7CH = O;OIIl F . I
20

" "'' "'

...........

."'~/I
CH = 0.11l~

J --......"

~

'\\
'\

180

\
\

Z 200

~

-90

'\

i""-~

220

240
100

lK
10K
lOOK
1M
±10V SINUSOIDAL INPUT FREQUENCY (Hz)

10

10M

7-12

100

lK

10K
lOOK
FREQUENCY. Hz

1M

10M

\

100M

HA-2420/2425
OFFSET AND GAIN ADJUSTMENT
HOLD STEP VS.INPUT VOLTAGE
HOLD STEP VOLTAGE (MV)

+10

GAIN ADJUSTMENT
-10

I

-5

+5

+10

I
DC INPUT VOLTAGE (V)

"

CH = 10,000 pF

The linear variation in pedestal voltage with sample-and-hold
input voltage causes a -0.06% gain error (CH = 1000pF). In
,some applications (O/A deglitcher, AID converter) the gain
error can be adjusted elsewhere in the system, while in
other applications it must be adjusted at the sample-andhold. The two circuits shown below demonstrate how to
adjust gain error at the sample-and-hold.

-20

The recommended procedure for adjusting gain error is:
-25

1. Perform offset adjustment.
-30

2. Apply the nominal input voltage that should produce
a +10V output.

-35

Figure 1

3. Adjust the trim pot for +10V output in the hold mode.
4. Apply the nominal input voltage that should produce a
-10V output,

OFFSET ADJUSTMENT

The offset voltage of the HA-2420/2425 may be adjusted
using a 100krl trim pot, as shown in Figure 6, The recommended adjustment procedure is:

5, Measure the output hold voltage (V-10 NOMINAL).
Adjust the trim pot for an output hold voltage of
(V-10 NOMINAl)+(-10V)
2

1. Apply zero volts to the sample-and-hold input, and a
square wave to the S/H control.
2. Adjust the trim pot for zero volts output in the hold
mode.

NONINVERTING CONFIGURATION
INVERTING CONFIGURATION
,002RF

+IN

HA-2420t2425

-IN

5tH
CONTROL
RF
5tH CONTROL
INPUT

J1JL
GAIN
StH CONTROL
INPUT

GAIN

~

-=i

Figure 2

Figure 3

7-13

~ I+~

HA-2420/2425
TEST CIRCUITS
HOLD STEP ERROR AND DRIFT CURRENT

-IN

INPUT

HA-2420t2425

JlIL
StH CONTROL
INPUT

Figure 4
HOLD STEP ERROR TEST

DRIFT CURRENT TEST

1. With a D.C. input voltage, observe the following

1. With a D.C. input voltage, observe the following
wavefo rms:
.

waveforms:
StH
CONTROL
OUTPUT

StH
CONTROL

4V----,-,
, - , - - - HOLD
OV ----l L-...J '---.;.. SAMPLE

VSTEP~

4V--.----, ,----,--- HOLO
OV--J
U
L..- SAMPLE

OUTPUT---""-....

f--- p.;;. -jtN

'-J : "J __

~

2. Measure the slope of the output during hoi'd,
and compute drift current from: I D = CH AV /At

2. Set rise/fall times of S/H Control to approximately
20 ns.

HOLD MODE FEEDTHROUGH ATTENUATION

SINE WAVE
INPUT

-

-

+5
EN
IN2
IN1
IN3
IN4
HI-50SA
IN5
MUX
OUT
IN6
IN7
INS
A2
A1 .
AO

-IN

HA-2420/2425

V
OUTPUT
OUT

-

VINp-p

1..
-

-

StH CONTROL
INPUT

Figure 5
NOTE: Compute hold mode feed through attenuation from the formula:
Feedthrough Attenuation =20 Log V~~NTH~~~D
Where,VOUT HOLD = Pea~-Peak value of output sinewave during the hold mode.

7-14

t.v /At,

HA-2420/2425

ACQUISITION TIMES

(CH

= 1000pF)

-10V TO OV
5tH

-1V TO OV

+10V TO OV
5tH

5V

5~

5V
5tH

OV

I

I

\

,\

I

\

I

/

ri

2r

1~,

OV

1
1

1\
2V

5o~mv

1~,

-100mVTO OV

+1V TO OV
5tH

..

OV

5V

5tH

111'

+100mVTO OV
5tH

5~

5V

OV
OV
OV

r
500rV

1'1'

50mV

50?n,

50jV

5tH
CONTROL

~

5Ofn,

-4V
HOLD

'--_ _ OV

SCHEMATIC
OFF SET ADJ

.-------~--4r--~--~~----~~_++_~4r----------------~~~~--~--~----~----Ov.

RP

~-¥~~+-+_~--+_--+_----+_--__oCH

R9

.-__---+--i__I--+......:~:::::-:~_t-----{)OUT
RIO

6000-+---+--_+-------+--4-----1

R14

L-_______+_----------------+~--~~----_+---4---+----+-----+------+-----~~~----~OvI ••

IN-

7-15

HA-2420/2425
APPlICA TIONS
BASIC SAMPLE-AND-HOLD
(TOP VIEW)

GUARD RING LAYOUT
(BOTTOM VIEW)

CONTROL

CONTROL

~-~-"'-~IN(-)

GN°MHOLDING I
CAPACITOR'"

I

-

~

~

+
IN

$
OUT

OUT

v+_

$

~v-

$

~---- -

Figure 7
NOTES:
This guard ring is recommended to minimize the drift
during hold mode.

1. Figure 6 shows a typical unity gain circuit, with Offset

Zeroing. All of the other normal op amp feedback
configurations may be used with the HA-2420t2425.
The input amplifier may be used as a gated amplifier by
utilizing Pin 11 as the output. This amplifier has excellent drive capabilities along with exceptionally low
switch leakage.

3. The holding capacitor should have extremely high insulation resistance and low dielectric absorption. Polystyrene
(below +85 0 C), Teflon, or Parlene types are recommended.

2. The method used to reduce leakage paths on the P.C.
board and the device package is shown in Figure 7.

For more applications, consult Harris Application Note
517, or factory applications group.

GLOSSARY OF TERMS
ACQUISITION TIME:

amplifier will output a voltage equal to V,N at the instant
the Hold command was received. For negative EADT, the
output in Hold (exclusive of pedestal and droop errors)
will correspond to a value of V,N that occurred before the
Hold command.

The time required following a "sample" command, for the
output to reach its final value within ±0.1% or ±0.01%. This
is the minimum sample time required to obtain a given accuracy, and includes switch delay time, slewing time and
settling time.

APERTURE UNCERTAINTY:

APERTURE TIME:

The range of variation in Effective Aperture Delay Time.
Aperture Uncertainty (also called Aperture Delay Uncertainty, Aperture Time Jitter, etc.) sets a limit on the accuracy with which a waveform can be reconstructed from sample
data.

The time required for the sample-and-hold switch to open,
independent of delays through the switch driver and input
amplifier circuitry. The switch opening time is that interval
between the conditions of 10% open and 90% open.

DRIFT CURRENT

EFFECTIVE APERTURE DELAY TIME (EADT):

The net leakage current from the hold capacitor during the
hold mode. Drift current can be calculated from the droop
rate using the formula:

The difference between propagation time from the analog
input to the StH switch, and digital delay time between the
Hold command and opening of the switch.

IDhlAI

EAOT may be positive, negative or zero. If zero, the StH

=CH (pF) x ~~ (Volts/sec)

DIE CHARACTERISTICS
Transistor Count:
Die Dimensions:
Thermal Constants:

78

8 ja
8 jc

Tie Substrate to:
Process:

97 x 61 mils
1170 C/W
46 0 C/W

7-16

-VSUPPLY
Bipolar,
Dielectric Isolation

;m~RIS

HA·5320
High Speed
Precision Monolithic
Sample and Hold Amplifier
DESCRIPTION

FEATURES

•
•

2x10 6 V/V
1.0).lS (0.01%)
0.08pV/llS (25 0 C)
DROOP RATE
17 llV/llS (FULL TEMP)
25ns
APERTURE TIME
1.0 mV
HOLD STEP ERROR (SEE GLDSSARY)

•
•

INTERNAL HOLD CAPACITO R
FULLY DIFFERENTIAL INPUT

•

TTl COMPATIBLE

•
•
•

GAIN, dc
ACQUISITION TIME

APPLICATIONS
•

PRECISION DATA ACQUISITION SYSTEMS

•
•

D/A CONVERTER DEGLITCHING
AUTO·ZERO CI RCUITS

•

PEAK DETECTORS

PINOUT

The HA-5320 was designed for use in precision, high speed data acquisition systems.
The circuit consists of an input transconductance amplifier capable of
providing large amounts of charging current, a low leakage analog
switch, and an output integrating amplifier. The analog switch sees
virtual ground as its load; therefore, charge injection on the hold
capacitor is constant over the entire input/output voltage range. The
pedestal voltage resulting from this charge injection can be adjusted to
zero by use of the offset adjust inputs. The device includes a hold
capacitor. However, if improved droop rate is required at the expense
of acquisition time, additional hold capacitance may be added externally.
This monolithic device is manufactured using the Harris Dielectric
Isolation Process, minimizing stray capacitance and eliminating SCR's.
This allows higher speed and latch-free operation. The HA-5320
is available in a ceramic 14-pin DIP. For further information, please
see Application Note number 538.

FUNCTIONAL DIAGRAM

TOP VIEW

v+

-INPUT

StH CONTROL

+INPUT

SUPPLY GNO

-INPUT
+INPUT

OFFSET AOJ.
OFFSET

A~J.

vREF GNU
OUTPUT

OUTPUT

N.C.
EXTERNAL
HOLD CAPACITOR

S/H
CONTROL

14

N.C.

v+
INTEGRATOR
BANDWIDTH
INTEGRATOR
BANDWIDTH

EXTERNAL

HOLD
CAPACITOR

7-17

o

N

CO)

anI

 ..........,................_',3

INPUT

!

SlH CONJROL CH,....,.,'.'+---1
~.

DIGITAL
OUTPUT

HA-6320

CONVERT

'3

~

81

1

><>-+_...J11-_ _ _ _ _ _ _;:I RIC
IO.1CH

__ ..I

e----------, ~~~~~~
SYSTEM
POWER
GROUND

SYSTEM
SIGNAL
GROUND

Figure 1

TYPICAL HA-5320 CONNECTIONS; NONINVERTING UNITY GAIN MODE.

7-20

PERFORMANCE CURVES
o

VSUPPLY =±15VDC

N
M

II)

DRI FT CURR~NT
VS. TEMPERATURE

TYPICAL SAMPLE AND HOLD PERFORMANCE
AS FUNCTION OF HOLDING CAPACITOR

I

E
w'
<.?

1.0,

CH = 100 pF

«
~

0.1

CH = 1000 pF

>
Q.

1.5

...I

0.01

0

1.0

W

CH = .01pF

~

til

C

...I

0

-10

-8

-6 -4

-2

2

4

6

8

0.5

J:

10

DC INPUT (VOLTS)
0.0
2

3

4

LOGIC LEVEL HIGH (VOLTS)

7-21

5

\
CHARGE TRANSFER AND DRIFT CURRENT

-INPUT
2

8/H
CONTROL
INPUT

14

OUTPUT

+INPUT

7

8
8/H CONTROL

11 N.C.

HA·5320

(CH

=100pF)

DRIFT CURRENT TEST

CHARGE TRANSFER TEST
1. Observe the "hold step" voltage Vp:

1. Obsarve the voltage "droop". LlVot Ll T:
StH---r--1 .---, __ HOLD (+3.5)
CONTROL --I
....,
' - SAMPLE (OV)

StH
,..,
,..... ____ HOLD (+3.5V)
CONTROL ----J L-...J L-- SAMPLE (OV)

~_,:::.._i

V -J'oo....

.i.

Vo

Vo
N.C.

~

o

"'"

Vp

I

I

LlT---'

""'__

f-~
~T

LlVo

2. Measure the slope of the output during hold. LlVot Ll T.
and compute drift current: 10 =CH Llvot Ll t.

2. Compute charge transfer: Q = VpCH

HOLD MODE FEED THROUGH ATTENUATION
V+

V-

HA·5320

ANALOG
MUXOR
SWITCH

5
-IN

VIN

VOUT

...+ ___::;.2.. +IN

10 Vpp
10 KHz
SINE WAVE

OUT ....7:........_4C~1

14 StH CONTROL
AIN

N.C.

N.C.

StH
,CONTROL
INPUT

TO
SUPPLY
COMMON

..J\.....-

Feedthrough in dB = 20 log VOUT where:
.
VIN·
VOUT = Volts PP. Hold Mode.
VIN = Volts pp.

7:-22

TO
SIGNAL
GND

GLOSSARY OF TERMS
o

EFFECTIVE APERTURE DELAY TIME (EADT):

ACQUISITION TIME:

N
M

Ion
I

The time required following a "sample" command, for the output
to reach its final value within ±0.1% or ±0.01%. This is the minimum
sample time required to obtain a given accuracy, and includes switch
delay time, slewing time and settling time.

The difference between propagation time from the analog input
to the StH switch, and digital delay time between the Hold
. command and opening of the switch.

CHARGE TRANSFER:

The small charge transferred to the holding capacitor from the
inter-electrode capacitance of the switch when the unit is switched
to the Hold mode. Charge transfer is directly proportional to sample'to-hold offset pedestal error, where:
Charge Transfer (pC) = CH (pF) x Offset Error (V)

The time required for the sample-and-hold switch to open, independent of delays through the switch driver and input amplifier
circuitry. The switch opening time is that interval between the
conditions of 10% open and 90% open.

DRIFT CURRENT:

The net leakage current from the hold capacitor during the hold
mode. Drift current can be calculated from the droop rate using the
formula:

HOLD STEP ERROR:

Hold Step Error is the output error due to Charge Transfer (see
above). It may be calculated from the specified parameter, Charge
Transfer, using the following relationship:
=

APERTURE UNCERTAINTY:

The range of variation in Effective Aperture Delay Time. Aperture
Uncertainty (also called Aperture Delay Uncertainty, Aperture
Time Jitter, etc.) sets a limit on the accuracy with which a waveform can be reconstructed from sample data.

APERTURE TIME:

HOLD STEP (V)

EADT may be positive, negative or zero. If zero, the StH
amplifier will output a voltage equal to VIN at the instant the
Hold command was received. For negative EADT, the output in
Hold (exclusive of pedestal and droop errors) will co rrespond to a
value of VIN that occurred before the Hold command.

.1V
10 (pA) = CH (pF)x_(Voltstsec)
.1T

CHARGE TRANSFER (pC)
HOLD CAPACITANCE (pF)

See Performance Curves.

DIE CHARACTERISTICS
Transistor Count:
Die Dimensions:
Thermal Constants:
Tie Substrate to
Process:

eja
ejc

7-23

175
90.2 x 143.7 mils
75 0 CtW
15 0 CtW
-VSuppl y
Bipolar
Dielectric Isolation

----+-+-0

1--+---.-.-1

VREF
LOW

TIH
CNTL

GAIN SELECT
Go GI

EXT.
CH

+V GNO ·V

TIN OUT

16 INPUT
SINGLE END
MUX

CHANNEL 16
SENSE

MUX
ENABLE

MUX
EXPANSION

VREF
LOW

7-28

TIN
CNTL

EXT.
CN

HY-9590/91

...

0)

Description

(:)

The HY-9590 and the HY-9591 are data acquisition front
end subsystems which can be used to interface multiple
sensors to an Analog-to-Digital Converter (ADC) for
computer processing. Both products combine an analog
input Multiplexer (MUX), a Programmable Gain Instrumentation Amplifier (PGA), and a Track-and-Hold (T/H)
amplifier. Adding a timing circuit and one ADC yields a
complete data acquisition system.
The HY-9590 provides eight pairs of multiplexed differential inputs.

amplifier. With the internal 100pF holding capacitor
(INT CH), the T/H has an effective aperture delay time
(EADT) of -25ns. (See 1986 Harris Analog Data Book,
page 7-23 for definition of EADT). External capacitance
can be added to reduce droop rate and pedestal error at
the expense of increased acquisition time.
The electrical differences between the HI-5900/5901 and
the pin compatible HY-9590/91 are summarized below:

Differences Between HI-590X and HY-959X

The HY-9591 has sixteen single-ended or pseudo differential channels of multiplexed inputs.
Both devices provide input fault protection. Input channel
expansion can be easily implemented with external multiplexers. Both input lines of the instrumentation (PGA)
amplifier are buffered by high-quality non-inverting
amplifiers. These buffers isolate each line from external
source impedances, preserving the high CMRR of the
amplifier block. Also, the buffers provide a high input
impedance for each channel.
The PGA, which includes an op amp, a laser trimmed
monolithic resistor network, and a four channel differential multiplexer, offers preCision inverting gain values of
-1, -2, -4, and -8. The voltage gain is selected by a two bit
digital word. The output of the PGA drives the Track-andHold amplifier, and the ground side of the PGA is isolated
by a buffer amplifier to further enhance the CMRR.

PARAMETER
External
Hold Capacitor

HY-9590/91

HI-5900/01

Required

Optional, 100pF supplied

Tied From CH
Pin to GND

Tied From CH
Pin to T/H OUTPUT

If a HY-9590/91 is intended to replace a HI-5900/01, the
external hold capacitor must be either: (a) disconnected
from pin 17', or (b) disconnected from ground and re-connected to pin 18 (T/H OUT). It should be noted that by
using only the internal 100pF hold capacitor, the
HY-9590/91 outperforms the HI-5900/01 using the standard 1000pF capacitor in pedestal error and aperture
uncertainty.

The output Track/Hold amplifier is a monolithic device,
internally connected for non-inverting unity gain. In the
"track" mode, it operates as a high performance buffer

The HY-9590/91 accepts the standard ±10V input range.
Power requirements are ±15V with typical dissipation of
580mW. All models are packaged in a 32 pin plastic DIP
with 600 mil row centers, except military temperature
parts, which use a ceramic package.

Pinouts

Package

TOP VIEW

,.

TOP VIEW

1.700 MAX

"2
NIC
I"

T

2"

.160
MIN

..L

48
58

LEAD
FRAME

1.500i.010

8A

-v

+V
MUX EXP
SENSE

t= =J

12

,81OMAX

VREf lOW

R~~~ l

T/H CONTROL

HY-9590

HY-9591

I

I

7-29

I

.1qOMAX-i

0)

an

0)
I

>
::I:

I
I
I
I

!
I
I
!
I
I
I
I
I

Product Index

8-2

Ordering Information

8-3

Standard Products
Packaging Availability

8-3

Glossary of Telecom Terms

8-4

Telecom Line Card Glossary

8-5

en

,2

:;:s;?

01-

'-'et
w'-'

Product Information

8-7

ABSOLUTE MAXIMUM RATINGS
As with all semiconductors, stresses listed under "Absolute Maximum Ratings"
may be applied to devices (one at a time) without resulting in permanent damage.
This is a stress rating only. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. The conditions listed under
"Electrical Characteristics" are the only conditions recommended for
satisfactory operation.

8-1

-

-'
W2
1-:::>

:;:

Product Index
P~ge

HC-5502A

. Subscriber Line Interface Circuit (SLlC) .............................................................................. 8-7

HC-5504

Subscriber Line Interface Circuit (SLlC) .............................................................................. 8-12

HC-5508/09

Subscriber Line Interface Circuit (SLIC) .............................................................................. 8-17

HC-5510/5511

Monolithic CODECs ................................................................................................................ 8-24

HC-5512/5512A

PCM Monolithic Filters ........................................................................................................... 8-33

HC-5512C

PCM or CVSD Monolithic Filter ............................................................................................. 8-40

HC-5512D

PCM Monolithic Filter Military Temperature Range ............................................................ 8-48

HC-5552/53/54/57

Monolithic Combo Family .....................................................................................,................. 8-57

HC-55536

All-Digital Continuously Variable Slope Delta Demodulator (CVSD) Decode Only ....... 8-68

HC-55564

All-Digital Continuously Variable Slope Delta Modulator (CVSD) .................................... 8-72

HF-10

Universal Active Filter ............................................................................................................. 8-79

HC-5560

Transcoder ................................ ;.............................................................................................. 8-82

HC-5580

Trunk Subscriber Line Interface Circuit (TSLIC) ................................................................ 8-83

HC-5581

DAA Subscribe( Line Interface Circuit (DAASLlC) ............................................................. 8-84

HC-5590

Digital Line Transceiver .......................................................................................................... 8-85

HC-5572

2400/1200/600/300 BPS Modem ............................................................................................ 8-86

8-2

Ordering Information
HARRIS PRODUCT CODE EXAMPLE

3
-T

H C
PREFIX: _ _ _ _ _ _T...J
H (HARRIS)

5502A -

5

T

PART LUMBER

TEMPERATURE:
OOC to +200o C

FAMILY: - - - - '
A
Analog
C
Communications
Digital
Fitters

~550C

o

M
V

*

to + 12SoC
-2S o C to +8S o C
DOG to +7S 0 C
100% +2So C Probe (Dice Only)
Oash-7 High Reliability Commercial
Product. DoC to +7So C
Oash-8 Program
HA2-2S20-8 (Example only)

Interface
Memory
Analog, High Voltage
Analog Hybrids

-40°C to +8Sc C

PACKAGE: - - - - - '
DuaHn-Line, Ceramic
Metal Can
Dual-In Line, Plastic
3 Leadless Carriers
Lee Hybrid
Mini-DIP, Ceramic
Chip Form

.

*

Special high temperature testing available
on certain product types. Consult factory for
availability.

Standard Products Packaging Availability
PACKAGE

PLASTIC
DIP

3-5

-7

HC-5502A

X

HC-5504

X

TEMPERATURE

SURFACE MOUNT
LCC
PLCC
44P-

CERAMIC
DIP
1-2

-8

-8

-5

-7

X

X

X

X

X

X

X

X

X

X

-9

-5

DEVICE NUMBER
TELECOM

HC-5508
HC-5509

X

X

I-=>
::;;;

X
X

HC-5512
HC-5512A

X
X

X
X

HC-5512C

X

X

X

HC-55536

HC-5560
HF-0010

X

X
X

HC-55564

X

X

X

X

X

X

X

X

X

X

X

8-3

U«

Wu
..J_

wz

HC-5510
HC-5511

HC-5512D

en

,z

::;;;0
oj:::

X

Glossary of Telecom Terms
BORSCHT: Acronym for functions provided by a subscriber line interface circuit. Includes Battery feed, Overvoltage protection, Ringing, Supervision, Coding, Hybrid and Test functions.
CHIP POWER DOWN: Ability to minimize device power dissipation by shutting down majority of power consuming circuitry, putting the device in an "idle" state. Not to be confused with Power Denial, which minimizes power
dissipation across the 2w loop.
DC/DC CONVERTER: Converts one DC voltage to another. Commonly used in transmission equipment where
different DC voltages are required throughout a system.
FAULT CURRENTS: These are loop currents tt1at flow during loop fault conditions, i.e., shorts in the line.
Integrated on the SLiC is a fault current limit circuit which protects the SLiC from excessive power.
FREQUENCY RESPONSE: A measure of the variation of the transmission performance of the SLiC with respect
to frequency variations.
IDLE CHANNEL NOISE (ICN): Noise measurements must characterize the annoyance to a user of unwanted
signals. ICN is a measure of these unwanted signals under idle (no signal) channel conditions.
INSERTION LOSS OR TRANS HYBRID GAIN VARIATION: Simply the gain or loss of a signal through the SLiC
from 2w to 4w and from 4w to 2w.
LEVEL LINEARITY OR GAIN TRACKING: A measure of the linearity of gain over a range of signal levels at a
particular frequency. (Dynamic range usually +3dBm to -55dBm).
LINE POLARITY REVERSAL: Refers to 2w side tip and ring lines. Tip lines normallymore positive with respect to
the ring line. Reverse polarity is used for signaling purposes .on trunk lines.
LONGITUDINAL CURRENT REJECTION: Ability of SLiC to suppress currents induced in the subscriber loop
by power lines, antennae, etc.
LOOP CURRENT LIMIT: This is the maximum current the SLiC will allow in the subscriber loop. It is controlled
by sensing loop current across the feed resistors, and adjusting the DC bias voltage at ring feed accordingly.
LOW FREQUENCY LONGITUDINAL BALANCE: Measure of degree of match of tip to ground and ring to
ground impedance in the presence of large longitudinal currents at power line frequencies (50, 60 Hz).
OVERLOAD LEVEL: Upper limit of the SLiCs dynamic range where speech signals just start to clip. This
parameter sets the maximum speech power level the device can handle.
PROGRAMMABLE DC FEED: Ability to control the tip feed and ring feed output DC bias voltages that establish
loop current.
PSRR: Measures the SLiCs ability to reject noise in the power supply. SLiC must not allow the noise to couple
into the speech paths.
SURGE PROTECTION: Adequate protection of the SLiC must be provided against lightning, low frequency induction, and power contact surges. The combination of split feed resistors, adiode bridge and ability of the feed
amplifiers to reject longitudinal currents afford adequate protection to the SLiC.
TRANS HYBRID LOSS: A measure of the SLiCs ability to separate the bidirectional speech transmission path
into distinct transmit and receive paths on the 4w side.
2W LONGITUDINAL BALANCE: A measure of the degree of balance of tip to ground and ring to ground.
Mismatches result in degradation of longitudinal current suppression in on-hook and off-hook conditions.

8-4

Telecom Line Card Glossary
RING RELAY: Allows switching of AC ringing signal from ring generator to drive subscriber telephone ringer via
tip or ring side.
RING RELAY DRIVER: SLiC output to drive ring relay coil.
SNUBBER NETWORK: RC network across ring relay contacts to reduce effects of inductive kickbacks to SLiC.
DC ISOLATION CAPACITOR: Blocks DC loop current from transformer.
ZENER DIODE: Secondary protection for RX and TX amplifiers.
AC HYBRID TRANSFORMER: Provides 2wire-4wire and 4wire-2wire conversion of voice signals.
BALANCING NETWORK: Provides 2wire line impedance matching and transhybrid balance.
DC FEED RESISTORS: Four 150n resistors that provide 600n of 2wire impedance and provide sense
mechanism for SLiC to detect switch hook, ground key and ring trip. Also provides some high voltage protection
to SLiC by dividing in half any voltage transient.
TX/RX AMPLIFIERS: Amplifies voice signal lost in hybrid transformer. Also provides impedance conversion
from 2wire-4wire and 4wire-2wire.
SUPERVISION NETWORK: Monitors SLiCs switch hook, ringtrip, and ground key detection functions, and
flags controller.
CONTROLLER: Stores ring command, ring trip, switch hook information, etc., until system CPU or line circuit
can react.

en

,2

:;:0
oj::

U«
-

UJu

-'

UJ2
I-~

:;:

8-5

m~RIS

HC·5502A
SLIC
Subsciber Line Interface Circuit

c:(
N

o

It)
It)
I

o

~

DESCRIPTION

FEATURES
• MONOLITHIC INTEGRATED DEVICE
• 01 HIGH VOLTAGE PROCESS
• COMPATIBLE WITH WORLDWIDE PBX
PERFORMANCE REQUIREMENTS
• CONTROLLED SUPPLY OF BATTERY FEED
CURRENT FOR SHORT LOOPS
• INTERNAL RING RELAY DRIVER
• LOW POWER CONSUMPTION DURING STANDBY

The HARRIS SLiC incorporates many of the BORSHT functions
on a single IC chip. This includes DC battery feed, a ring
relay driver, supervisory and hybrid functions. This device is designed to maintain transmission performance in the presence of externally
induced longitudinal currents. Using the unique HARRIS dielectric
isolation process, the SLiC can operate directly with a wide range of
station battery voltages.
The SLiC also provides selective denial of power. If the PBX system
becomes overloaded during an emergency, the SLiC will provide system
protection by denying power to selected subscriber loops.

• SWITCH HOOK, GROUND KEY AND RING TRIP
DETECTION FUNCTIONS

The HARRIS SLiC is ideally suited for the design of new digital
PBX systems, by eliminating bulky hybrid transformers.

• SELECTIVE DENIAL OF POWER TO SUBSCRIBER
LOOPS

SLiC is available in either a 24 pin dual-in-line plastic or ceramic
package. The SLiC is also available as unpackaged die.

APPLICATIONS
• SOLID STATE LINE INTERFACE CIRCUIT FOR
ANALOG AND DIGITAL PBX SYSTEMS
• DIRECT INWARD DIAL (010) TRUNKS
• VOICf MESSAGING PBX's
(I)

FUNCTIONAL DIAGRAM

PINOUT

,2

:;;0
oj::
uct
Wu
...j

-

W2

1-::>

TOP VIEW
TIP
RING
VB+

:;;

TX
AG
CAP 4

CAPl'

Rx

CAP3

DG
RS

+IN
-IN
OUT

ii1i

CAP 2

TF

RC

TX

2WIRE
LOOP

RF
VB-

15011

BG

POWER DENIAL

'Optional

8-7

Lf--~----~
PO

L ___

~~~!~:!!!!

-,

~-----F~

I

______ ...J

TRANSMIT
OUTPUT

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Maximum Continuous Supply Voltages (VB-)
(VB+)
(VB+ - VB-)
Operating Ambient Temperaure Range (T A)
Storage Temperature Range (RSRG)
Thermal Resistance ( () J-A) (Plastic)
Thermal Resistance (() J-A) (Ceramic)

-60 to +.5 Volts
-.5 to +15 Volts
75 Volts
OOC to +75 0 C
-40 oC to +85 0 C
60 oC/W
61 0 C/W

RECOMMENDED OPERATING CONDITIONS
Positive Supply Voltage (VB+)
Negative Supply Voltage (VB-)
Minimum High Level Logic Input Voltage
Maximum Low Level Logic Input Voltage
Loop Resistance (RL)
Ambient Operating Temperature Range (T A)

10.8 to 13.2 Volts
-42 to -58 Volts
2.4 Volts
0.8 Volts
200 to 1200 Ohms
OOC to +75 0 C

ELECTRICAL CHARACTERISTICS
(VB- =-48V, VB+ =+12V, AG

=BG =DG =OV, TA =25 0 C Unless Otherwise Stated)
CONDITIONS

PARAMETER

On Hook Power Dissipation
Off
Off
Off
Off
Off
Off

Hook
Hook
Hook
Hook
Hook
Hook

Power Dissipation
IB+
IBLoop Current
Loop CUrrent
Loop Current

I Long. = 0
RLOOP = 600 Ohms. ILong = 0
RLOOP = 600 Ohms.ILong = 0
RLOOP = 600 Ohms.ILong = 0
RLOOP = 1200 Ohms.ILong = 0
RLOOP = 1200 Ohms, VB- = -42V. I Long = 0
RLOOP = 200 Ohms. I Long = 0

MIN

TYP

MAX

UNITS

135
743

174
795
4.3
38

mW
mW
mA
mA
mA
mA
mA

21
17.5
25.5

30

34.5

Fault Cwrents

14
47
30
47

TIP to Ground
RING to Ground
TIP to RING
TIP and RING to Ground

mA
mA
mA
mA

Ring Relay Drive VOL

10L = 62mA

0.2

0.. 5

V

Ring Trip Detection Period

RLOOP = 600 Ohms

2

3

Ring Cycles

Switch Hook Detection Threshold

SHO=VOL
SHO = VOH
GKO=VOL
1iKli = VOH

5

mA
mA
mA

Ground Key Detection Threshold

10
20

Receive Input Impedance
Transmit Output Impedance
Two Wire Return Loss
SRL LO
ERL
SRL HI

(Return Loss Referenced
to 600!l+2.16pF)

Longitudinal Balance

1V Peak-Peak 200Hz ··3400Hz
58
60
50

2 Wire Off Hook
2 Wire On Hook
4 Wire Off Hook
Low Frequency Longitudinal Balance

10
5

0

Dial Pulse Distortion

90

k Ohms

1

Ohm

15.5
24
31

dB
dB
dB

65
63
58

dB
dB
dB
23

R.E.A. Method

-67

8-8

ms

d8rnC

.. ~

SPECIFICATIONS (Continued)



Logic Inputs
Logic '0' VI L
Logic '1' VIH
Logic Outputs
Logic '0' VOL
Logic'l'VOH

,2

::;;;0

2.0

0.8
5.5

Volts
Volts

0.5
5.5

Volts
Volts

::;;;

Max Two LS Loads
2.7

0.1
5.0

TABLE 1

OVERVOL TAGE PROTECTION AND
LONGITUDINAL CURRENT REJECTION
The SLiC device, in conjunction with an external protection
b~idge, will withstand high voltage lightning surges and power
line c'rasses.

TEST
PERFORMANCE
(MAX)
PARAMETER CONDITION

UNITS

Longitudinal
Surge

10J.1s Rise!
1000J.1s Fall

±1000 (Plastic)
±.500(Ceramic)

V Peak
V Peak

Metallic Surge

10J.1s Rise!
1000J.1s Fall

±1000 (Plastic)

± 500 (Ceram ic)

V Peak
V Peak

10J.1s Rise!
1000J.1s Fall

± 500 (Ceram ic)

T/GND
R!GND
50/60Hz
Current
T!G'NO
R!GND

High voltage surge conditions are as specified in Table 1.
The SLiC will withstand longitudinal currents up to a maximum
or 30mA RMS, 15mA RMS per leg, without any performance
degradation.

8-9

700V rms
limited to
lOA rms

:!:1000 (Plastic)

11

V Peak
V Peak
Cycles

PIN ASSIGNMENTS
PIN
NUMBER

SYMBOL
TIP

1

I

DESCRIPTION
Ali analog input connected to the TIP (more positive) side of the subscriber loop
through a 150Qleed resistor and a ring relay. Functions with the Ring terminal (Pin 2)
to receive voice signals from the telephone and for Loop Monitoring Purposes.
An analog input connected to the RING (more negative) side of the subscriber loop
through a 150Hfeed resistor. Functions with the Tip terminal (Pin 1) to receive
voice signals from the telephone and for loop monitoring purposes.
Positive Voltage Source - Most positive supply. VB+ is typically 12 volts with an
operational range 01 10.8 to 13.2 volts.

2

RING

3

VB+

4

CAP 1

Capacitor # 1 - Optional Capacitor used to improve power supply rejection. This pin
should be 1,lt open il unused.

5

CAP 3

6

DG

Capacitor # 3 - An external capacitor to be connected between this terminal and
analog ground. Required for proper operation of the loop current limiting function,
and lor filtering -48V supply. Typical value is 0.3j.lF, 30V.
Digital Ground - To be connected to zero potential and serves as a reference for
all digital inputs and outputs on the SLiC.

7

RS

Ring Synchronization Input - A TTL-compatible clock input. The clock is arranged
such that a positive transition occurs, on the negative going zero crossing of the
ring voltage source, ensuring that the ring relay is activated and deactivated when
the instantaneous ring voltage is near zero. If synchronization is not required, tie to +5V.

8

Rii

9

TF

10

RF

11

VB-

Relay Driver - A low active open collector logic output. When enabled, the
external ring relay is energized. Maximum All voltage is 15 volts.
Tip Feed- A low impedance analog output connected to the T terminal (Pin 1)
through a 150llfeed resistor. Functions with the RF terminal (Pin 10) to provide loop current, feed voice signals to the telephone set, and sink longitudinal
current.
Ring Feed - A low impedance analog output connected to the R terminal (Pin 2)
through a 150llfeed resistor. Functions with the TF terminal (Pin 9) to provide
loop current, feed voice signals to the telephone set, and sink longitudinal currents.
Negative Voltage Source - Most negative supply. VB- is typically -48 volts with an
operational range of -42 to ..:.58 volts. Frequently referred to as "battery".

12

BG

13

SHD

14

GKD

15

Po

16

RC

17

CAP 2

18
19
20
21

OUT
-IN
+IN

22

CAP4

23

AG

24

TX

RX

Battery Ground - To be connected to zero potential. All loop current and some
quiescent current flows into this ground terminal.
Switch Hook Detection - A low active LS TTL -compatible logic output. This output
is enabled for loop currents exceeding 1OmA and disabled for loop currents less
than 5mA.
Ground Key Detection - A low active LS TTL -compatible logic output. This output is
enabled if the DC current into the ring lead exceeds the DC current out of the tip
lead by more than 20mA ,and disabledil this current difference is less than 10mA.
Power Denial - A low active TTL-compatible logic input. When enabled, the loop
current is limited to a maximum 2mA, the switch hook detect (SHD) and ground key
detect (m) are not necessarily valid, and the relay driver (Rii) output is disabled.
Ring Command - A low active TTL-compatible logic input. When enabled, the
relay driver (fill) output goes low on the next rising edge '!L!he ring sync (RS)
input, as long as the SLIC is not in the power denial state (PO = 0) or the subscriber
is not already off-hook (SfIli = Oi.
Capacitor'#2 - An external capacitor to be connected between this terminal and
digital ground. Prevents false ground key indications from occurring during ring trip
detection. Typical value is 0.15j.lF, 10V. This capacitor is not used il ground key
function is not required.
The analog output of the spare operational amplifier.
The inverting analog input of the spare operational amplifier.
The non-inverting analog input of the spare operational amplifier.
R·eceive Input, Four Wire Side - A high impedance (90kQ) analog input which is
internally biased. Capacitive coupling to this input is required. AC signals appearing
at this input differentially drive the tip feed and ring feed terminals, which in turn
drive tip and ring through 300 Ohms of feed- resistance on each side of the-line.
Capacitor #4 - An external capacitor to be connected between this terminal and
analog ground. This capacitor prevents false ground key indication and false ring
trip detection from occurring when longitudinal currents are induced onto the
subscriber loop from near proximity power lines and other noise sources. 1'his
capacitor is also required for the proper operation of ring trip detection. Typical
value is 0.5j.lF,to 1.0j.lF, 20V. This capacitor should be nonpolarized.
Analog Ground - To be connected to zero potential and serves as a reference for the
transmit output (TX) and receive input (RX) terminals.
Transmit Output, Four Wire Side - A low impedance (10Qmax) analog output
which represents the differential voltage across tip and ring. Transhybrid balancing
must be performed (using the SLiC microcircuit's spare op amp) beyond this output
to completely implement two to four wire conversion. This output is unbalanced
and referenced to analog ground. Since the DC level of this output varies with loop
current, capacitive coupling to the next stage is essential.

8-10

APPLICATIONS DIAGRAM

cc

('\II

o
It)

TYPICAL LINE CIRCUIT APPLICATION
WITH THE MONOLITHIC SLIC

It)
I

o

::t

RING GENERATOR

__

~ -,'~[f]

SYSTEM CONTROLLER

16
BALANCE
NETWORK
21
RECEIVE !4----+--::-....,.--i
TRANSMIT..,2"'4----i*'l

RELAY DRIVER

TIP
TIP FEED

OP-AMP {
SLiC
HC-5502A

:::~::--=----+-+,
..

L::::.J

SWITCHING
NETWORK

OUTPUTF----i~

RING FEED

Cll-'-------,
17
C2
CJ 5
22

RING o-.....----"WV------1~----'
RBJ

TYPICAL COMPONENT VALUES
Cl = 0.5pF (Note 1)
C5 = 0.5IlF. 20V
C2 =0.15pF. 10V
C6 = C7 = 0.5pF (10% M.tch Required) (Note 2). 20V
CJ = O.JpF. JOV
CB = D.OlpF, 10DV
C4 = 0.5pV to 1.0pF,
C9 = O.OlpF, 20V, ±20%
± 10%, 20V (Should be nonpolarized)
Rl-+ RJ = lDOkn (0.1% Match Required, 1% .b.olute value), ZB = 0 for 600n Termin.tion. (Note 2)
RBI = RB2 = RBJ = RB4 = 150n (0.1% M.tch Required, 1% .b.olute value)
RS = 1KO , Cs = O.lpF, 200V typic.IIV, depending on VRing and line length ..
Z1 = 150V to 20DV transient protector: PTe usid as ring ballast.
NOTE 1:

C1 is an optional capacitor used to improve +12V supply rejection. This pin must be left open if unused.

NOTE 2:

To obtain the specified transhybrid loss it is necessary for the thee legs of the balance network, C6-R1 and R2
and C7-ZB-Rl, to match in impedance to within 0.3%. Thus, if C6 and C7 a~d 1 IJ. F each, a 20% match is
adequate. It should be noted that the transmit output to C6 sees a -10.5 to -21 volt step when the loop is

closed and that too large a value for C6 may produce an excessively long transient at the op amp output to the
PCM Filter ICDDEC.
A 0.5 pF and 100Kn gives a time constant of 50msec. The uncommitted op amp output is internally clamped
to stay within ± 5.5V and also has current limiting protection.
NOTE 3:

Secondary protection diode bridge recommended is MDA 220 or equivalent.
ADDITIONAL INFORMATION IS CONTAINED
IN APPLICATION NOTE 549, "THE HC-550X TELEPHONE SLlC."
BY GEOFF PHILLIPS

8-11

CI)

,2

::;:0

OJ::
e:.:>«
We:.:>

...J_

W2
~::l

:;:

;m HARRIS

HC·5504

SLIC
Subscriber Line Interface Circuit
DESCRIPTION

FEATURES
• MONOLITHIC INTEGRATED DEVICE
• DI HIGH VOLTAGE PROCESS
• COMPATIBLE WITH WORLDWIDE PBX
PREFORMANCE REQUIREMENTS
• CONTROLLED SUPPLY OF BATTERY FEED
CURRENT FOR SHORT LOOPS
• INTERNAL RING RELAY DRIVER
• ALLOWS INTERFACING WITH NEGATIVE
SUPERIMPOSED RINGING SYSTEMS
• LOW POWER CONSUMPTION DURING STANDBY
• SWITCH HOOK GROUND KEY AND RING TRIP
DETECTION FUNCTIONS
• SELECTIVE DENIAL OF POWER TO SUBSCRIBER
LOOPS

The HARRIS SLiC incorporates many of the BORSHT functions on
a single IC chip. This includes DC battery feed, a ring relay driver, supervisory and hybrid functions. This device is designed to maintain transmission performance in the presence of externally induced longitudinal
currents.
The SLiC also provides selective denial of power. If the PBX system
becomes overloaded during an emergency, the SLiC will provide system
protection by denying power to selected subscriber loops.
The HAR RIS SLiC is ideally suited for the design of new PBX systems,
be eliminating bulky hybrid transformers.
SLiC is available in either a 24 pin dual-in-line plastic or ceramic package. The SLiC is also available in die form.

APPlICA TlONS
• SOLID STATE LINE INTERFACE CIRCUIT FOR
ANALOG AND DIGITAL PBX SYSTEMS
• DIRECT INWARD DIAL (OlD) TRUNKS
• VOICE MESSAGING PBXs

FUNCTIONAL DIAGRAM

PINOUT
TOP VIEW

TIP
RING
RFS
VB+
CAP 3
DG
RS

ii1i
TF
RF
VBBG

TX
AG
CAP4
Rx
+IN
-IN
OUT
CAP 2

RC
PiS
GKD
SHD

8-12

SPECIFICA T/ONS
ABSOLUTE MAXIMUM RATINGS

o::r
o

RECOMMENDED OPERATING CONDITIONS

It)
It)
I

Maximum Continuous Supply Voltages (VB-)
(VB+)
(VB+ -VB-)
Operating AmbientTemperature Range (TA)
Storage Temperature Range (RSRG)
Thermal Resistance (OJ-A) (Plastic)
Thermal Resistance (OJ-A) (Ceramic)

elECTRICAL CHARACTERISTICS

-60 to +0.5V
-.5 to +15V
75V
O·C to +75 OC
-:.40·C to +85·C
60 0 C/W
61 0 C/W

Positive Supply Voltage (VB +)
Negative Supply Voltage (VB-)
Mimimum High Level Logic Input Voltage
Maximum Low Level Logic Input Voltage
Loop Resistance (RL)
Ambient Operating Temperature Range (T A)

10.8 to 13.2V
-42 to -58V
2.4V
0.8V
200 to 1200.Q
OOC to +75 0 C

o

:I:

VB- - -48, VB+ - + 12V, AG-BG-DG -OV, TA -25·C Unless Otherwise Stated

PARAMETER
On Hook Power Dissipation
Off Hook Power Dissipation
Off Hook IB+
Off Hook IBOff Hook Loop Current
Off Hook Loop Current
Off Hook Loop Current
Fault Currents
TIP to Ground
RING to Ground
TIPto RING
TIP and RING to Ground
Ring Relay Drive VOL
Ring Trip Detection Period
Switch Hook Detection Threshold
Ground Key Detection Threshold
Dial Pulse Distortion
Receive Input Impedance
Transmit Output Impedance
Two Wire Return Loss
SRL LO
ERL
SRL HI
Longitudinal Balance
2 Wire Off Hook
2 Wire On Hook
4 Wire Off Hook
Low Frequency Longitudinal Balance
Insertion Loss
2 Wire - 4 Wire
4 Wire - 2 Wire
Frequency Response

CONDITIONS
ILong. = 0
RLOOP = 600 Ohms,ILong. = 0
RLDDP = 600 Ohms,ILong. = 0
RLOOP = 600 Ohms, I Long. = 0
RLOOP = 1200 Ohms,ILong. = 0
RLOOP = 1200 Ohms, VB- = -42V, ILong. = 0
RLOOP = 200 Ohms, I Long. = 0

MIN

17.5
36

TYP

MAX

UNITS

135
390
3
35
21

174
704
4.3
40

41

48

mW
mW
mA
mA
mA
mA
mA

14
63
41
63
0.2
2

10L = 62mA
RLODP = 600 Ohms
SHD = VOL
SHD = VDH
GKD = VOL
GKD = VOH

0.5

10
20
10
5
90

mA
mA
mA
mA
V
Ring Cycles
mA
mA
mA
mA
ms
k Ohms
Ohm

15.5
24
31

dB
dB
dB

65
63
58

dB
dB
dB
dBrnC
dBmop
dB
dB
dB

IV Peak-Peak 1200Hz-3400Hz)
58
60
50
R.E.A. Method
I kHz, OdBm Input Level

23
-67

@

Idle Channel Noise
2 Wire - 4 Wire

i.05
i.05
i.02

1
-89
1
-89

4 Wire - 2 Wire
Absol ute Delay
2 Wire - 4 Wire
4 Wire - 2 Wire

iO.2
iO.2
in.05

5
-85
-85

dBrnC
dBmop
dBrnC
dBmop
!1 s
!1s

8-13

2:

01-

I Return Loss Referenced
to 60011+2.16!1F)

200 - 3400Hz Referenced
to Absolute Loss at 1kHz and
OdBm Signal Level

VJ
I

::;;~

ue:(
Wu

...J_

W2:

I-=>
::;;

SPECIFICA TIONS (Continued)
PARAMETER

CONDITIONS

MIN

TYP

Envelope Delay
2 Wire - 4 Wire
4 Wire - 2 Wire
Trans Hybrid Loss

4 Wire - 2 Wire

Power Supply Rejection Ratio
VB+to 2 Wire
VB+ to Transmit
VB- to 2 Wire
VB- to Transmit
VB+to 2 Wire
VB+ to Transmit
VB- to 2 Wire
VB- to Transmit

Balance Network Set Up
for 600 Ohm Termination
at 1kHz

36

J..Ls
J..Ls

40

dB

+4
+4

dBm
dBm

at 1kHz
+3 to -40dBm
-40 to -50dBm
-50 to -55dBm
+3 to -40dBm
-40 to -50dB m
-50 to -55dBm

dB
dB
dB
dB
dB
dB

±0.05
±0.1
±0.3
±'0.05
±'0.1
±0.3

30 - 60Hz, RLOOP = 600n

15
15
15
15

dB
dB
dB
dB

200 -16kHz
RLOOP= 600n

30
30
30
30

dB
dB
dB
dB

Logic Inputs
Logic '0' VIL
Logic '1' VIH
Logic Outputs
Logic '0' Vo L
Logic '1' VOH

UNITS

2
2

Overload Level
2 Wire - 4 Wire
4 Wire - 2 Wire
Level Linearity
2 Wire - 4 Wire

MAX

0.0
2.0

0.8
5.5

V
V

0.5
5.5

V
V

Max Two LS Loads
0.1

2.7

OVERVOLTAGE PROTECTION AND
LONGITUDINAL CURRENT REJECTION
TABLE 1

The SLiC device, in conjunction with an external protection
bridge, will withstand high voltage ligntning surges and power
line crosses.

TEST
PERFORMANCE
PARAMETER CONDITION
(MAX)

UNITS

Longitudinal
Surge

High voltage surge conditions are as specified in Table 1.

Metallic Surge

The SLiC will withstand longitudinal currents up to a maximum or 30mA RMS, 15mA RMS per leg, without any performance degradation.

T/GND
R/GND
50/60Hz
Current
T/GND
R/GND

8-14

10J..Ls Risel
1000).s Fall
10J..Ls Risel
1000J..Ls Fall

±IOOO (Plastic)
±500 (Ceramic)

V Peak
V Peak

±1000 (Plastic)
±500 (Ceramic)

V Peak
V Peak

10J..Ls Risel
1000J..Ls Fall

±1000 (Plastic)
±500(Ceramic)

V Peak
V Peak

700V rms
Limited to
lOA rms

11

Cycles

PIN ASSIGNMENTS
o::t

o

PIN
NUMBER SYMBOL
1
2
3
4
5
6
7
8
9

10
11
12
13
14

15

16

17

18
19
20
21

22

23
24

DESCRIPTION

II)
II)
I

TIP

An Analog input connected to the Tip (More Positive) side of the subscriber loop through a 150nteed resistor and a ring relay. Functions with the Ring terminal (Pin 2) to receive voice signals from the telepho.ne and for loop monitoring purposes.
RING
An Analog input connected to the Ring (More Negative) side of the subscriber loop through a 150meed resistor. Functions
with the Tip terminal (Pin 1) to receive voice signals from the telephone and for loop monitoring purposes.
RFS
Senses ring side of loop for ground key and ring trip detection. During ringing, the ring signal is inserted into the line at this
node and RF is isolated from RFS via a relay.
Positive Voltage Source-Most positive supply. VB + is typically 12 volts with an operational range of 10.8 to 13.2 volts.
VB+
CAP 3 Capacitor 1i3-An external capacitor to be connected between this terminal and analog ground. Required for proper opera·
tion of the loop current limiting function, and for filtering -48V supply. Typical value is 0.3J1F, 3OV.
Digital Ground-To be connected to zero potential and serves as a reference for all digital inputs and outputs on the SliC
oG
microcircuit.
RS
Ring Synchronization Input-a TTL - compatible clock input. The clock is arranged such that a positive pulse 15o·5ooJl s)
occurs on the negative going zero crossing of the ring voltage source, ensuring that the ring relay is activated and deactivated when the instantaneous ring voltage is near zero. If synchronization is not required, then tie to +5V.
Ro
Relay Driver-a low active open collector logic output. When enabled, the external ring relay is energized. Maximum AD
voltage is 15 volts.
Tf
Tip Feed-A low impedance Analog output connected to the T terminallPin 1) through a 150.Q feed resistor. Functions
with the RF terminal IPin 10) to provide loop current, feed voice signals to the telephone set, and sink longitudinal currents.
RF
Ring Feed-A low impedance Analog output connected to the R terminallPin 2) through a 150Q feed resistor. Functions
with the TF terminallPin 9) to provide loop current, feed voice signals to the telephone set, and sink longitudinal currents.
Negative Voltage Source-Most negative supply. VB - is typically -48 volts with an operational range of -42 to -58
VBvolts. Frequently referred to as "battery."
BG
Battery Ground- To be connected to zero potential. All loop current and some quiescent current flows into this ground ter·
minal.
SHD
Switch Hook oetection-A low active LS TTL· compatible logic output. This output is typically enabled for loop currents exceeding
-GKD 7.5 rnA and typically disabled for loop currents less than 7.5mA.
Ground Key Detection-A low active LS TTL· compatible logic output. This output is typically enabled if the DC current into the ring
lead exceeds the DC current out of the tip lead by more than 12.5 rnA, and typically disabled if this current difference is less than
12.5mA.
PO
Power Denial-A low active TTL-compatible logic input. When enabled, the loop current is limited to a maximum 2mA,
the switch hook detect ISHo)and ground key detect IGKo) are not necessarily valid and the relay driver lAD) output is
disabled.
-RC
Ring Command-A low active TTL·compatible logic input. When enabled, the relay driver IRD) output goes low on the next
high level of the ring sync IRS) input, as long as the SLiC is not in the power denial state IPD =0) or the subscriber is not
already off·hook ISHo =0).
CAP 2 Capacitor #2-An external capacitor to be connected between this terminal and digital ground. Prevents false ground key
indications from occuring during ring trip detection. Typical value is 0.15J1F, 10V. This capacitor is not needed if ground
key function is not required and pin 17 may be left open or connected to digital ground.
OUT
The analog output of the spare operational amplifier. The output voltage swing is typically ± 5V.
-IN
The inverting analog input of the spare operational amplifier.
+IN
The non-inverting analog input of the spare operational amplifier.
RX
Receive Input, Four Wire Side-A high impedance 190k.Q) an'alog input which is internally biased. Capacitive coupling to this input is
required. AC signals appearing at this input differentially drive the tip feed and ring feed terminals, which in turn drive tip and ring
through 300 Ohms of feed resistance on each side of the line.
CAP 4 Capacitor #4-An external capacitor to be connected between this terminal and analog ground. This capacitor prevents false
ground key indication and false ring trip detection from occuring when longitudinal currents are induced onto the subscriber loop
from near proximity power lines and ,other noise sources. This capactior is also required for the proper operation of ring trip detec·
tion. Typical value is 0.5 JlF to 1.0 JlF, 20V. This capacitorshould be ooopolamed.
AG
Analog ground-To be connected to zero potential and serves as a reference for the transmit output iTX) and receive input IRX) terminals.
TX
Trans"!it Output, Four Wire Side-A low impedance 11 O.Qmax) analog output which represents the differential voltage across tip and
ring. Transhybrid balancing must be performed lusing the SLiC microcircuit's spare op amp) beyond this output to completely imple·
, men! two to four wire conversion. This output is unbalanced and'referenced to analog ground. Since the DC level of this output
varies with loop current, capacitive coupling to the next stage is essential.

o

~

-

8-15

en

,2

:::;:0

oi=
u
:::;:

APPLICATIONS DIAGRAM

ZI

0

~
U

-4SV

150V PE;:S(:AX)
RING GENERATOR
TYPICAL COMPONENT VALUES
C2 = 0.15/iF, 10V
C3 = 0.3/iF, 30V
C4 = 0.5 "F to 1.0" F 10%, 20V (Should be non-pol.rized)
C5 = 0.5/iF, 20V
C6 =C7 =0.5/iF (10% Match Required)
CS = O.OI/iF, 100V
C9 =O.OII'F, 20V ± 20%
Rl = R2 = R3 = lOOk (0.1% Match Required, ZB = 0 for 600n Terminations
RBI = RB2 = RB3 = RB4 = 150n (0.1% Match Required, 1% Absolute)
RSI = RS2 = 1Kn Typically
CSI =CS2 =O.I/iF, 200V typically, depending on VRING and Line Length.
ZI = 150V to 200V transient protection.
PTe used as ring generator ballast.

®

NOTES:

CD

CD Secondary protection diode bridge recommended is an MDA 220 or equivalent.
®

To obtain the specified transhybrid loss of 40dB it is necessary for the 3 legs of
the balance network, C6 - Rl and R2 and C7 - ZB - R3, to match in impedance to
within 0.3%. If C6 and C7 are l/iF each, a 20% match is adequate. It sho.;ld be
noted that the transmit output to C6 sees a -22V step when"the loop is closed.
Too large a value for C6 may produce an excessively long transient at the op amp
output to the PCM Filter/CODEC. A 0.5/iF and 100kn gives a time constant
of 50msec. The uncommited op amp output is internally clamped to stay within
±5.5V and also has CUHent limiting protection.
ADDITIONAL INFORMATION IS CONTAINED IN
APPLICATION NOTE 549
"THE HC-550X TELEPHONE SLlCs"
BY GEOFF PHILLIPS

8-16

!)HARRIS

He-550B/OS

PRELIMINARY

SLICs
Subscriber Line Interface Circuits

en

~
CO
o
it)
it)
I

o

::J:

Features

Description

• Monolithic Integrated Device
• 01 High Voltage Process
• Compatible with Worldwide PBX Performance
Requirements
. • Controlled Supply of Battery Feed Current for
Short Loops
• Internal Ring Relay Driver and Message Waiting
Relay Driver
• Programmable Loop Current Limit and Self-Test
Function (HC-SS09)
• Low Power Consumption During Standby
• Switch Hook, Ground Key, Ring Trip and
Message Waiting Detection Functions
• Selective Denial of Power to Subscriber Loops
• Two On Chip Op Amps for Transhybrld Balance
and 2 Wire Impedance Matching

Applications
• Solid State Line Interface Circuit for PBX or
Central Office Systems
• Hotel/Motel (Message/Waiting) Switching Systems
• Direct Inward Dialing (DID) Trunks
• . Voice Messaging PBX's
• Analog Trunk Echo Cancellor Interface

Pinout

The HC-5508/09 SLiCs incorporate many of the BORSHT
functions on a monolithic IC. These include DC battery feed
with loop current limiting, overvoltage protection, ringing,
supervisory and hybrid functions. The devices are designed
to maintain specified transmission performance in the presence of externally induced longitudinal currents.
The SLiCs also provide selective denial of power, a 40mA
loop current limit, line fault protection, and thermal current
limiting. If a PBX/CO system becomes overloaded during an
emergency or is subjected to line faults, the SLiCs will
provide system protection by denying power to selected
subscriber loops or by limiting loop current. Switch hook,
ground key, ring trip, and message waiting detection
functions are also incorporated into the SLiC devices.
The Harris SLiCs are ideally suited for the design of PBX and
CO systems, replacing bulky hybrid transformers.
The HC-5508 SLiC is available in a 28 pin Dual-In-Line
plastic package, or in die form. The HC-5509 is available in a
44 pin PLCC or in a die form which allow users the option to
access additional functions including a self test function and
an externally programmable loop current limit.
Both SLiCs are ideally suited for use with the HC-5512/12A
PCM filters, the HC-5510/11 PCM CODECs, and the HC5552/3/417 serial interface PCM combos.

Functional Diagram
TOP VIEW

e..>«
We..>

-' wz

BG
VBRF

1-::1

:E

TF
VFB

iiii
HC-550B

CI.l
,z
of::

:=;;0

OG

MWR
C4
TX

Cl

Dun

RX

-INI

RFS

RING

HC-5509
AVAILABLE IN
SURFACE MOUNT
44 PIN PLCC

8-17

HC-5508/09
Description of Pin Functions
PIN

SYMBOL

DESCRIPTION

1

AG

Analog Ground - To be connected to zero potential. Servesasa reference for the transmit output
(TX) and receive input (RX) terminals.

2

VS+

Positive Voltage Source - Most positive supply. VS+ is typically 12 volts with an operational range
of 10.8 to 13.2 volts.

3

C3

Capacitor #3 - An external capacitor to be connected between this terminal and analog ground.
Required for proper operation of the loop current limiting function, and. for filtering - 48V supply.
Typical value is 0.3pF, 30V.
.

4

Fl

Function Address 1 - TTL and CMOS compatible input used with FO function address line to
externally select logic functions; ring command, message waiting, and loop power denial. Thethree selectable functions are mutually exclusive. (See Truth Table 1.)

5

FO

Function Address 0 - TTL and CMOS compatible input used with Fl function address line to
externally select logic functions; ring command, message waiting, and loop power denial. The
three selectable functions are mutually exclusive. (See Truth Table 1.)

6

RS

Ring Synchronization Input - A TTL compatible clock input. The clock is arranged such that a
positive pulse (50-500ps) occurs on 'the negative going zero crossi~g of the ring voltage source,
ensuring that the ring relay is activated and deactivated when the instantaneous ring voltage is
near zero. If synchronization is not required, then tie to +5V.

7

SH5

Switch Hook Detection - A low active LS TTL compatible logic output. This output is typically
enabled for loop currents exceeding 12mA and typically disabled for loop currents less than
12mA.

8

GKi5

Ground Key' Detection - A low active LS TTL compatible logic output. This output is typically
enabled if the DC current into the ring lead exceeds the DCcurrentoutofthetip lead by more than .
15mA and typically disabled if this current difference is less than 15mA.

9

C2

Capacitor #2 - An external capacitor to be connected between this terminal and digital ground.
Prevents false ground key indications from occurring during ring trip detection. Typicalvalue is
0.15pF, 10V. This capacitor is not needed if ground key function is not required and may be left
open or connected to digital ground.

10

OUT2

The analog output of spare operational amplifier Number 2. The output voltage swing is typically
±5V.

11

-IN2

12

oun

13

-INl

The inverting analog input of spare operational amplifier Number 1.

14

TIP

An analog input connected to the TIP (more positive) side of subscriber loop through a son feed
resistor and a ring relay. Functions with the RING terminal to receive voice signals from the
telephone and for loop monitoring purposes.

The inverting analog input of spare operational amplifier Number 2.
The analog output of spare operational amplifier Number 1. The output voltage swing is typically
±5V.

8-18

HC-5508/09

en

~
CO
o
It)

Description of Pin Functions (Continued)
PIN

SYMBOL

15

RING

An Analog input connected to the RING (more negative) side of the subscriber loop through a 500
feed resistor. Functions with the TIP terminal to receive voice signals from the telephone and for
loop monitoring purposes.

16

RFS

Senses ring side of loop for ground key detection. During Ring Injected ringing, the ring signal is
inserted into the line at this node to isolate RF from the ring signal via the ring relay. For balanced
or Tip Injected Ringing, the RF and RFS pins must be shorted.

17

RX

Receive Input, Four Wire Side - A high impedance analog input which is internally biased.
Capacitive coupling to this input is required. AC signals appearing at this input differentially drive
the Tip Feed and Ring Feed terminals, which in turn drive TIP and RING through 100 ohms of feed
resistance on each side of the line.

18

C1

Capacitor #1 - An external capacitor to be connected between this terminal and ground. It
prevents false ring trip detection and false message waiting detection from occurring when
longitudinal currents are induced onto the subscriber loop from power lines and other noise
sources. Typical value is O.5iJF to 1.OpF, 20V. This capacitor should be nonpolarized.

19

TX

Transmit Ouput, Four Wire Side - A low impedance (100max) analog output which represents
the differential voltage across TIP and RING. Transhybrid balancing must be performed (using
the SLiC microcircuit spare op amps) beyond this output to completely implement two to four
wire conversion. This output is referenced to analog ground. Since the DC level of this output
varies with loop current, capacitive coupling to the next stage is necessary.

20

C4

Capacitor #4 - An external capacitor to be connected between this terminal and analog ground.
This capacitor prevents false ground key indication from occurring when longitudinal currents
are induced into the subscriber loop from power lines and other noise sources. Typical value is 0.5
JlF to 1.OpF, 20V. This capacitor should be nonpolarized.

21

MWR

Message Waiting Relay Driver - A active low open collector logic output. Used to switch a high
voltage onto the line to drive telephone set neon lamp to indicate a message is waiting.

22

DG

Digital Ground - To be connected to zero potential. Serves as a reference for all digital inputs and
outputs on the SLiC microcircuit.

23

RD

Ring Relay Driver - A active low open collector logic output. Used to switch ring signals onto the
2 wire line.

24

VFB

Feedback signal from the tip feed amplifier. To be used in conjunction with transmit output signal
(TX) and the spare op-amps to accommodate 2W line impedance matching.

25

TF

Tip Feed - A low impedance analog output connected to the TIP terminal through a son feed
resistor. Functions with the RF terminal to provide loop current, feed voice signals to the
telephone set, and sink longitudinal currents.

26

RF

Ring Feed - A low impedance analog output connected to the RING terminal through a son feed
resistor. Functions with the TF terminal to provide loop current, feed voice signals to the
telephone set, and sink longitudinal currents.

27

VB-

Negative Voltage Source - Most negative supply. VB- is typically -48 volts with an operational
range of -25 to -58 volts. Frequently referred to as "battery".

28

BG

Battery Ground - To be connected to zero potential: All loop 'current and some quiescent current
. flows into this ground terminal.

DESCRIPTION

a

8-19

It)
I

o

:::I:

Specifications HC-5508/09
Absolute Maximum Ratings

Recommended Operating Conditions

Max. Continuous Supply Voltages(VB+) ..... -O.5V to +15V
(VB+)-(VB-) ........ +75V
Operating Ambient Temperature (TA) ........ OoC to +75 0 C
(TS) ... -25 0 C to +125 0 C
Storage Temperature Range

Positive Power,Supply (VB+) ............................ +12V ±5%
Negative Power Supply(VB-) ......................... -25V to -58V
Ambient Operating Temperature Range
(TA) ........................ OoC to +75 0 C

Electrical Characteristics

Typical Conditions .Unless Otherwise Stated:
VB- = -48V, VB+ = 12V, AG = DG = BG = OV, TA = 25 0 C,
All AC Parameters are Specified at Goon

TABLE 1

F1

FO

0
0
1
1

0
1
0
1

ACTION

Normal Loop Feed
RD Active
MWR Active
Loop Power Denial Active

A.C. Transmission Performance
PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

RX Input Impedance

300Hz to 3.4KHz

1

MO

4W Input Overload Level

300Hz to 3.4KHz

+4

dBm

2W In put Overload Level

300Hz to 3.4KHz

+4

dBm

2W Longitudinal Impedance

Per Lead

2W Return Loss
SRL LO
ERL
SRL HI

200Hz to 500Hz
500Hz to 2.5KHz
2.5KHz to 3.2KHz

100

0

25
25
25

35
40
40

dB
dB
dB

per ANSI/IEEE STD
455-1976
300Hz to 3400Hz
10Hz to 3400Hz

55
60

65
63

dB
dB

Off Hook

per ANSI/IEEE STD
455-1976
300Hz to 3400Hz

50

55

dB

Low Frequency Longitudinal Balance
2W and 4W

R.E.A. Method

-67
23

dBmop
dBrnC

Per Lead

15

mArms

2W Longitudinal to Metallic. Balance
Off Hook
On Hook
4W Longitudinal to Metallic Balance

Longitudinal Current Capability

8-20

Specifications HC-5508/09

PARAMETER

en
o
CO
o
it)

.......

A.C. Transmission Performance (Continued)
CONDITIONS

MIN

TYP

MAX

UNITS

it)
I

Insertion Loss
2W/4W, 4W/2W

OdBm @ 300Hz to 3400Hz

±0.2

dB

Ref. to -10dBm
+3 to -40dBm
-40 to -50dBm
-50 to -55dBm
+3 to -40dBm
-40 to -50d Bm
-50 to -55dBm

±0.05
±0.1
±0.3
±0.05
±0.1
±0.3

dB
dB
dB
dB
dB
dB

300Hz to 3400Hz
300Hz to 3400Hz

2
2

/1s
/1s

500Hz to 1KHz
1KHz to 2.6KHz
2.6KHz to 2.8KHz

2
2
2

/1S
/1s
/1s

o

:I:

Level Linearity

2W/4W

4W/2W

Absolute Delay
2W/4W
4W/2W
Envelope Delay Distortion
2W/4W, 4W/2W

36

D{3

40

Transhybrid Loss, THL

OdBm @ 1KHz

Total Harmonic Distortion
2W/4W, 4W/2W, 4W/4W

Ref. Level OdBm
300Hz to 3400Hz

-52

dB

C-Message
Psophometric
3KHz Flat

5
-85
15

dBrnC
dBmop
dBrn

Idle Channel Noise
2W and 4W

Power Supply Rejection Ratio
VB+ to 2W
VB+ to 4W
VB- to 2W
VB- to 4W
VB+ to 2W
VB+ to 4W
VB- to 2W
VB- to 4W

30Hz to 200Hz
VNOISE = 100mVrms

200Hz to 16KHz
VNOISE = 100mVrms

8-21

25
25
25
25

dB
dB
dB
dB

30
30
30
30

dB
dB
dB
dB

en
,2

:;;0

at:::
Uet

Wu

-

-'
W2

I-=>

:;;

Specifications HC-5508/09
D.C. Performance
CONDITIONS

PARAMETER

MIN

Loop Current Limit

TYP

MAX

UNITS

40

46

mA

±2

mA

Loop Current During Power Denial
Fault Currents
TIP to Ground
RING to Ground
TIP and RING to Ground
TIP to RING

40
60
100
40

mA
mA
mA
mA

Switch Hook Detection Threshold
Ground Key Detection Threshold

12
15

mA
mA

Message Waiting Detection Threshold
Ring Trip Detection Threshold

15
15

mA
mA

Ring Trip Detection Period
Dial'Pulse Distortion

2
0.1

Relay Driver Outputs (RD, MWR)
On Current
Off Leakage Current
Delay Time
Rise and Fall Time

+12V to OV

Input Current (FO, F1, RS)

2.0
OV

0:;

VIN

0:;

5V

Cycles
mS

mA

50
±10

VSAT ~ 1.2V

TTL/CMOS Logic Inputs
(FO, F1, RS)
Logic '0' VIL
Logic '1' VIH

3

10
10

J1A
J1S
J1S

0.8
5.5

V
V

±100

J1A

Ring Synchronization (RS)
Pulse Width
Delay Time, Sync to Driver Off

25
20

20

J1S
J1s

Logic Inputs
Logic '0' VIL
Logic '1' VIH

0.0
2.0

0.8
5.5

V
V

0.5
5.5

V
V

Logic Outputs
Logic '0' VIL
Logic '1' VIH

Max Two LSLoads
0.1
2.7

. Power Dissipation
On Hook

mW

200

Uncommitted Op Amps
PARAMETER
Input Offset Voltage
In put Offset Cu rrent
Input Bias Current
Differential Input Resistance
Input Noise Voltage
Output Voltage Swing
Output Resistance

CONDITIONS

f

~

RL

MIN

TYP

MAX

UNITS

10

15
100
400

mV
nA
nA
M!1
nV/ Hz

1KHz

1
20

~

±5

10K!1

10
1

Small Signal GBW

8-22

V
!l
MHz

HC-5508/09 Applications Diagram
Overvoltage Protection and
Longitudinal Current Rejection

TABLE 2.
TEST
CONDITION

PERFORMANCE
(MAXIMUM)

UNITS

lOllS Risel
1000llS Fall

±1000 (Plastic)
±500 (Ceramic)

V Peak
V Peak

Metallic Surge

lOllS Fall
1000llS Fall

±1000 (Plastic)
±500 (Ceramic)

V Peak
V Peak

T/GND
R/GND

lOllS Risel
1000llS Fall

±1000 (Plastic)
±500 (Ceramic)

V Peak
V Peak

11

Cycles

PARAMETER

The SLiC devices, in conjunction with an external protection bridge, will withstand high voltage lightning surges
and power line crosses.

It)
I

Longitudinal

Surge

High voltage surge conditions are as specified in Table 2.
The SLiCs will withstand longitudinal currents up to a
maximum total of 30m Arms (15mArms per leg) without
any performance degradation.

en
o
CO
o
It)

o

l:

50/60Hz Current

T/GND
R/GND

700V rms
Limited to

lOA rms

Applications Diagram

CSI
IMPEDANCE MATCHING
AND BALANCE NETWORK
RX 17

1- - - - - - -

FROM PCM
FILTER

TIPo--.,....4--0-_"O'...--/VII'--......---.!.:!j14 TIP

SLiC
HC-5508

VB·

10+

.INlr-~_"

26 RF

CI.>
,2

Dun 1-'1....
2:;-_..
(

16 RFS

:;0
RBAL

o~

RBAL

u

::;;;

CL = 100pF

HC-5510/11
HC-5510 Pin Assignments
DESCRIPTION

PIN NO.

SYMBOL

1
2

SC1
SC2

Internally connected to GN DA.

3

VFX

Analog input to the encoder. This signal will be sampled at the end of the encoder time slot and the
resulting PCM code will be shifted out during the subsequent encode time slot.

4
5
6

NC
GNDA
SIGR

7
8

DR

NC

9

PDN

10

VFR

11
12
13
14

NC
NC
GNDD

15

TSX

16
17

VCC
CLKR

18

FSR

19

CLKX

20

FSX

21

SIGX

22
23

VBB
DC

24

CLKC

DX

Connects VFX to an external sample / hold capacitor if fitted for use with pin compatible NMOS
CODEC. Insures gain compatibility.

Unused
Analog ground. All analog signals are referenced to this pin. Must be same potential as GNDD.
Receive signaling bit output. During receive signaling frames the least significant (last) bit shifted into
DR is internally latched and appears at this output-SI GR will then remain valid until changed during
a subsequent receive signaling frame or reset by a power-down command.
Unused
Serial PCM data input to the decoder. During the decodertime slot, PCM data is shifted into DR,
most significant bit first, on the falling edge of CLKR.
TTL output level which goes high when the CODEC is in the power-down mode. May be used to
power-down other circuits associated with the PCM channel. Can be wire ANDed with other
PD N outputs.
Analog output from the decoder. The decoder sample and hold amplifier is updated approximately
15jJS after the end of the decode time slot.
Unused
Unused
Digital ground. All digital levels are referenced to this pin. Must be same potential as GNDA.
Serial PCM "Three-State" output from the encoder. During the encoder time slot, the PCM code for
the previous sample of VFX is shifted out, most significant bit first, on the rising edge of CLKX.
Time sl.ot output. This TTL compatible open-drain output pulses low during the encoder time slot.
May be used to enable external.:!:hree-State" bus drivers if highly capacitive loads must be driven.
Can be wire ANDed with other TSX outputs.
5V (±5%) input.
Master dec.oder clock input used to shift in the PCM data on DR and to operate the decoder sequencer.
May operate at 1.536MHz, 1.544MHz or 2.048MHz. May be asynchronous with CLKX or CLKC.
Decoder frame sync pulse. Normally occurring at an 8kHz rate, this pulse is nominally one CLKR cycle
wide. Extending the width of FSR to two or more cyclesof CLKR signifies a receive signaling frame.
Master encoder clock input used to shift out the PCM data on DX ~nd to operate the encoder sequencer.
May operate at 1.536MHz, 1.544MHz or 2.048MHz. May be asynchronous with CLKR or CLKC.
Encoder frame sync pulse. Normally occurring at an 8kHz rate, this pulse is nominally one CLKX cycle
wide. Extending the width of FSX to two or more cycles of CLKX signifies a transmit signaling frame.
Transmit signaling input. During a transmit signaling frame, the signal at SIGX is shifted out of DX
in place of the least significant (last) bit of PCM data.
-5V (±5%) input.
Serial control data input. Serial data on DC is shifted into the CODEC on the falling edge of CLKC.
In the fixed time slot mode, DC doubles as a power-down input.
Control clock input used to shift serial control data into DC. CLKC must pulse 8 times during a period
of time less than or equal to one frame time, although the 8 pulses may overlap a frame boundary.
CLKC need not be synchronous with CLKX OT CLKR. Connecting CLKC continuously high places
the HC-5510/HC-5511 into the fixed time slot mode.

8-28

HC-5510/11

,....
,....
(:)
,....

HC-5511 Pin Assignments

II)
II)

OESCRIPTION

PIN NO.

SYMBOL

1
2

SCI
SC2

Internally connected to GNOA.
Connects VFX to an external sample / hold capacitor if fitted for use with pin compatible NMOS
COOEC. Insures gain compatibility.

3

VFX

Analog input to the encoder. This signal will be sampled at the end of the encoder time slot and the
resulting PCM code will be shifted out during the subsequent encode time slot.

4 \

NC

5
6
7

GNDA
NC
DR

8

PDN

9

VFR

10
11
12
13

NC
NC
GNDD

14

TSX

15
16

VCC
CLKR

17

FSR

18

CLKX
FSX

20
21

VB8
DC

22

CLKC

~

Unused

Ox

19

I

o

I

Analog ground. All analog signals are referenced to this pin. Must be same potential as GNDD.
Unused
Serial PCM data input to the decoder. During the decoder time slot, PCM data is shifted into 0 R,
mostsignificant bit first, on the falling edge of CLKR.
Open drain output which turns off when the CODEC is in the power-down mode.
May be used to power-down other circuits associated with the PCM channel. Can be
wire AN Oed with other PO N outputs.
Analog output from the decoder. The decoder sample and hold amplifier is updated approximately
15ps after the end of the decode time slot.
Unused
. Unused
Digital ground. All digital levels are referenced to this pin. Nlust be same potential as GNDA.
Serial PCM "Three-8tate" output from the encoder. During the encoder time slot, the PCM code for
the previous sample of VFX is shifted out, most signficant bit first, on the rising edge of CLKX.
Time slot output. This TTL compatible open-drain output pulses low during the encoder time slot.
May be used to enable extarnal.::Jhree-State" bus drivers if highly capacitive loads must be driven.
Can be wire ANDed with other TSX outputs.
5V (±5%) input.
Master decoder clock input used to shift in the PCM data on 0 R and to operate the decoder sequencer.
May operate at 1.536MHz, 1.544MHz or 2.048MHz. May be asynchronous with CLKX or CLKC.
Decoder frame sync pulse. 'Normally occurring at an 8kHz rate, this pulse is nominally one CLKR
cycle wide.
Master encoder clock input used to shift out the PCM data on 0 X and to operate the encoder sequencer.
May operate at 1.536MHz, 1.544MHz, or 2.048MHz. May be asynchronous with CLKR or CLKC.
Encoder frame sync pulse. Normally occurring at an 8kHz rate, this pulse is nominally one CLKX
cycle wide.
-5V (±5%) input.
Serial control data input. Serial data on DC is shifted into. the CODEC on the falling edge of CLKC.
In the fixed time slot mode, DC doubles as a power-down input.
Control clock input used to shift serial control data into DC. CLKC must pulse 8 times during a period
of time less than or equal to one frame time, although the 8 pulses may overlap a frame boundary.
CLKC need not be synchronous with CLKX or CLKR. Connecting CLKC continuously high places
the HC-5510/HC-5S11 into the fixed time slot mode.

en
,Z
::i!0

oi=
(.) 0.1/l F

PDN

VFX

,-1+----'
se2

...----IVFX1~~~-4~~~-IGSx

R3

PDN

vFXO

TSx t--t---I~ TSx
DX
DX
ClKX
ClKX

I+-t-.....-FSX

HC-5512/5512A

PWRO{
TO SllC +----IPWRO+
"'---DR

...-----IPWRI
DC
R5

~------------;-~~-'------+5V
~-----------------------~-------t---~~---5V

XMT gain

= 20 x log

(R3 ;2R2 ) +3dB

RCV gain

= 20 x log

(~)
R4 + R5

The power supply decoupling capacitors should be O.lpF. In order to take advantage of the excellent noise performance of
the HC-551 O/HC5511/H C-5512, care must be taken in board layout to prevent coupling of digital noise into the sensitive
analog lines. The above application is configured for a fixed time slot mode of operation .
• The external sample/hold capacitor required for use with pin·compatible NMOS CODECs introduces attenuation due to
the capacitive divider formed with Cl. The SC pins connect VFX to this sample/hold capacitor (via a 300 n resistor) to
ensure gain compatibilitY. The HC-5510/11 itself does not require an external sample/hold capacitor.
For use with Monolithic Slics, such as HC-5502A; HC-5504 and HC-550B. -rhe output may be taken directly at VFRO.

8-32

m~RIS

HC·5512/5512A

«
We.>

...J-

W2

FUNCTIONAL DIAGRAM

I-:::l

:::;;

GI.

VF.I_...!2i1....-'.......~

VFxl+·",1_"'""1~

13

SNDD

FIGURE 1

8-33

GNDA

PON

SPECIFICA T/ONS
ABSOLUTE MAXIMUM RATINGS
Supply Voltages
Power Dissipation
Input Voltage
Output Short-Circuit Duration
Operating Temperature Range
Storage Temperature
Lead Temperature (Soldering, 10 seconds)

±7V
lW/Package
±7V
Continuous
-25 0 C to +1250 C
-65 0 C to +150 0 C

300 0 C

DC ELECTRICAL CHARACTERISTICS
Unless otherwise noted, T A = ooC to 75 0 C, VCC = 5.0V±5%, VBB = -5.0V ±5%, clock frequency is 1.544MHz.
Typical parameters are specified at T A = 25 0 C, VCC = 5.0V, VBB = -5.0V. Digital interface voltages measured
with respect to digital ground, GNDD. Analog voltages measured with respect to analog ground, GNDA.

Symbol

Parameter

Units

Conditions

POWER DISSIPATION
leco

Vcc Standby Current

PDN = VDD, Power Down Mode

50

100

Isso

Vss Standby Current

PDN = VOD' Power Down Mode

50

100

p.A
p.A

lec1

Vcc Operating Current

PWRI = Vss, Power Amp Inactive

3.0

4.0

mA

Iss1

VSB Operating Current

PWRI = V BS, Power Amp Inactive

3.0

4.0

mA

lec2

Vcc Operating Current

Note 1

4.6

6.4

mA

Iss2

VBB Operating Current

Note 1

4.6

6.4

mA

10

p.A

DIGITAL INTERFACE
VSS"VIN"VCC

-10

Vas" VIN " Vcc

-100

VBB" VjN" Vec -0.5V

-10

-0.1

p.A

Input low Voltage, ClK, PDN

0

0.8

V

Input High Voltage, ClK, PDN

2.2

Vcc

V

VILO

Input low Voltage, ClKO

V BS

VBB +0.5

V

V 110

Input Intermediate Voltage, ClKO

0.8

V

VIHO

Input High Voltage, ClKO

Vcc

V

IINC

Input Current, ClK

IINP

Input Current, PDN

IINO

Input Current, ClKO

VIL
VIH

p.A

-0.8
Vec- 0.5

TRANSMIT INPUT OP AMP
IBxl

Input leakage Current, VFxl

VBB"VFxl"Vcc

Rlxl

Input Resistance, VFxl

VSB"VFxl"Vcc

VOSxl

Input Offset Voltage, VFxl

-2.5V"V IN " + 2.5V

VCM

Common·Mode Range, VFxl

CMRR

Common·Mode. Rejection Ratio

PSRR

Power Supply Rejection of Vcc
or VSB

ROL

Open loop Output Resistance,
GS x

RL

Minimum load Resistance, GS x

- 2.5V" VIN " 2.5V

-100

100

nA
M[J

10
-20

20

-2.5

2.5

mV
V

60

dB

60

dB
k[J
k[J

10
100

pF

CL

Maximum load Capacitance, GS x

VOxl

Output Voltage Swing, GS x

R L", 10k

±2.5

V

AVOL

Open loop Voltage Gain, GS x

RL",10k

5,000

VIV

Fe

Open loop Unity Gain Bandwidth,
GS x

2

8-34

MHz

SPECIFICA T/ONS
<
We..>

-'
w2

2

5

dBrncO

3

6

dBrncO

0.0004

dB/'C

0.01

dBN
-70

-0.1
-0.05
-0.1

0.1
0.05
0.1

dB

dB
dB
dB

~

SPECIFICATIONS
AC ELECTRICAL CHARACTERISTICS (Continued)
Unless otherwise specified, T A = 25 0 C. All parameters are specified for a signal level of 0 dBmO at 1 kHz. The

odBmO level is assumed to be 1.54 Vrms measured at the output of the transmit or receive filter.
Symbol

Parameter

Conditions

Units

RECEIVE FILTER (Unless otherwise noted, the receive filter is preceded by a sin xIx filter with an input signal level of 1.54 Vrms.l
IBR

Input Leakage Current, VFRI

RIR

Input Resistance, VFRI

ROR

Output Resistance, VFRO

CL R

Load Capacitance, VFRO

RLR

Load Resistance, VFRO

PSRR3

Power Supply Rejection of Vce or
VBB , VFRO

VOSRO Output DC Offset, VFRO

3.2V$V ,N $3.2V

-100

100

10

nA
MD

1

3

D

100

pF

10

k!!

VFRI Connected to GNDA
f = 1 kHz

35

dB

VFRI Connected to GNDA

-200

GAR

Absolute Gain

f = 1 kHz (HC-5512A)
f = 1 kHz (HC-5512)

GR R

Gain Relative to Gain at 1 kHz

Below 300 Hz
300 Hz to 3.0 kHz (HC-5512A)
300 Hz to 3.0 kHz (HC-5512)
3.3 kHz
3.4 kHz
4.0 kHz
4.6 kHz and Above

-0.1
-0.125

0
0

-0.125
- 0.15
-0.35
- 0.7

200

mV

0.1
0.125

dB
dB

0.125
0.125
0.15
0.03
-0.1
-14
- 32

dB
dB
dB
dB
dB
dB
dB

DAR

Absolute Delay at 1 kHz

100

I'S

DDR

Differential Envelope Delay 1 kHz
to 2.6 kHz

100

I'S

DPRI

Single Frequency Distortion
Products

f = 1 kHz

-48

dB

DPR2

. Distortion at Maximum Signal
Level

2.2 Vrms Input to Sin xix Filter,
f = 1 kHz, RL = 10k

-45

dB

Total C·Message Noise at VFRO

3

Temperature Coefficient of 1 kHz
Gain

0.0004

dBl'C

GARS

Supply Voltage Coefficient of
1 kHz Gain

0.01

dBIV

CTXR

Crosstalk, Transmit to Receive
VFO
R2010g-VFxO
Gaintracking Relative to GAR

GRRL

Transmit Filter Output = 2.2 Vrms
VFRI =0 Vrms, f =0.3 kHz to 3.4 kHz
Measure VFRO
Output Level = + 3 dBmO
+ 2 dBmO to - 40 dBmO
- 40 dBmO to - 55dBmO
Note 5

8-36

5

dBrncO

NCR
GART

-70

-- 0.1
-0.05
- 0.1

0.1
0.05
0.1

dB

dB
dB
dB

SPECIFICATIONS
c(
N

AC ELECTRICAL CHARACTERISTICS (Continued)

T""

IJ)
IJ)

Unless otherwise specified, T A
C. All parameters are specified for a signal level of 0 dBmO at 1kHz. The
OdBmO level is assumed to be 1.54 Vrms measured at the output of the transmit or receive filter.
=250

.......
N

T""

Symbol

Parameter

Units

Conditions

RECEIVE OUTPUT POWER AMPLIFIER
IBP

Input Resistance. PWRI

ROP1

Output Resistance. PWRO +.
PWRO-

CLP

Load Capacitance. PWRO +.
PWRO-

I

o

:I:

Input Leakage Current,'PWRI

RIP

IJ)
IJ)

0.1

- 3.2V" V IN" 3.2V

3

I'A

Mn

10
Amplifiers Active

n

1

500

GAp+

Gain. PWRI to PWRO +

GAp-

Gain. PWRI to PWRO-

RL =60011 Connected Between
PWRO + and PWRO - . Input
Level =0 dBmO (Note 4)

GRpL

Gaintracking Relative to 0 dBmO
Output Level

V =2.05 Vrms. RL =60011 (Notes 4. 5)
V = 1.75 Vrms. RL = 30011

SlOp

SignallDistortion

V = 2.05 Vrms. RL =60011 (Notes 4. 5)
V = 1.75 Vrms. RL = 30011

VOSP

Output DC Offset. PWRO+.
PWRO-

PWRI Connected to GNDA

- 50

PSRR5

Power Supply Rejection of Vce
or VBB

PWRI Connected to GNDA

45

Note 1:

Maximum power consumption will depend on the load impedance connected to the po,wer amplifier. The specification

1
-1

pF

VIV
VIV

-0.1
-0.1

0.1
0.1

dB
dB

- 45
-45

dB
dB

50

mV

dB

listed assumes 0 dBm is delivered to 60o.l!connected from PWRO+ to PWRO-.
Note 2: Voltage input to receive filter at OV, VFRO connected to PWRI, 600n from PWRO+ to PWRO-. Output measured from
PWRO+ to PWRO-.
Note 3: The OdBmO level for the filter is assumed to be 1.54 Vrms measured at the output of the XMT or ReV filter.
Note 4: The odBmO level for the power amplifiers is load dependent. For RL = 600n to GNDA the OdBmO level is 1.43 Vrms
measured at the amplifier output for RL = 300nthe OdBmO level is 1.22Vrms.
Note 5: VFRO cqnnected to PWRI, input signal applied to VFRI.

en

,Z

:;;0
oj::::

Uet

INTERFACE

.~/RCu/T

Wu
-'
WZ

-

FOR HC-5510 CODEC

I-:::l

:;;

R2

R1

- - - - - - - - - - -,,
'I
INTERFACE CIRCUIT

~

I
I
I
I
I
I
I
I
I
I
I
I

TRANSFORMERS
600

O.ljlF
16
VFxO

I
I
I

600

Ox

14

PCM

OUT

1601<

,

-::-GNDA

HC-5512/HC-5512A

-::- I

11

1::

VFx

13
PWRO-

HC-5510
PDN

PDN

RS ,
600 16

,

10
VFR'

10

VFR

DR

PCM

IN

L ___________ J

Note l' Transmit voltage gain
Note 2, Receive gain

Note 3:

=

=

Rl;2 A2

xF

(Tha filter itself introduces a 3dB gain) (Rl +R2 :?: 10k).

R3 ~~4

(A3 +R4 "2=: 10k)
In the configuration shown, the receive filter power amplifiers will drive a 60anT to R termination to a signal level of 8,5dBm.
An alternative errangement, using a transformer winding ratio equivalent to 1.414:1 and 300n resistor, AS, will provide a
maximum signal level of 10.1dBm across a 6001~ termination impedance,

8-37

PIN ASSIGNMENTS
Pin
No.

Name

Function

VFxl+

The non·inverting input to
the transmit filter stage.
The inverting input to the
transmit filter stage.
The output used for gain
adjustments of the transmit
filter.

2

3

The low power receive filter
output. This pin can directly
drive the receive port of an
electronic hybrid.
The input to the receive filter
differential power amplifier.
The non·inverting output of
the receive fi Iter power
amplifier. This output can
directly interface conven·
tional transformer hybrids.
The inverting output of the
receive filter power amplifier.
This output can be used with
PWRO + to differentially
drive a transformer hybrid.
The negative power supply
pin. Recommended input is
-5V.
The positive power supply
pin. The recommended input
is 5V.
The input pin for the receive
filter stage.

4

5

PWRI

6

PWRO+

7

PWRO-

8

9

Vee

10

Pin
No.

Name

Function

11

GNDD

Digital ground input pin. All
digital signals are refer·
enced to this pin.

12

ClK

Master input clock. Input frequency can be selected as
2.048 MHz, 1.544 M Hz or
1.536 MHz.

13

PDN

The input pin used to power
down the HC~5512/12A during
idle periods. logic 1 (Vee)
input voltage causes a
power down condition. An internal pull-up is provided.

14

ClKO

This input pin selects internal counters in accordance with the ClK input
clock frequency:
ClK

Connect ClKO to:

2048 kHz
1544 kHz
1536 kHz
An i.nternal
provided.

VBB
pull-up

The output of the transmit
filter stage.

16

TYPICAL PERFORMANCE CHARACTERISTICS

Transmit Filter Stage

Receive Filter Stage
10

10

II

-10

~
""'c=>

-20

1\

-10

~

I

-30

II Illl....+4 ,FILT ER
-

FUEll+lllll

-20

""'
c

X/~~

SIN

=> -30

LI).h:t

>-

>-

~ -40

-40
~
:;;

:;;

«

« -50

-50
800 0

1

-70

-70
10

0.1
FREQUENCY

cf

X=

-60

-60

0.1

1

8-38

10

1

FREQUENCY

(kHz)

is

Analog ground input pin. All
analog signals are referenced to this pin. Not internally connected to GNDD.

GNDA

15

Vee
GNDD

(kHz)

FUNCTIONAL DESCRIPTION


100

VBB ",VIN '" Vee -0.5V

-10

-0.8

Input leakage Current, VF,I

Vaa '" VF,I '" Vec

-100

RI,I

Input Resistance, VF,I

Vss",VF,I", Vee

10

VOS,I

Input Offset Voltage, VFxl

-20

20

VeM

Common·Mode Range, VFxl

-2.5

2.5

CMRR

Common·Mode Rejection Ratio

PSRR

Power Supply Rejection of Vee
or Vss

ROL

Open loop Output Resistance,
GS x

-2.5V ",V IN ", +2.5V

nA
Mf!
mV
V

60

dB

60

dB
kf!
kf!

10

RL

Minimum load Resistance, GS x

CL

Maximum load Capacitance, GS x

VOxl

Output Voltage Swing, GS x

RL",10k

±2.5

V

AVOL

Open loop Voltage Gain, GSx

RL", 10k

3400

VIV

Fe

Open loop Unity Gain Bandwidth,
GS x

100

2

8-41

~­

W2

::;;:

TRANSMIT INPUT OP AMP
IB,I

en

,2

::;;:0

pF

MHz

SPECIFICATIONS
AC ELECTRICAL CHARACTERISTICS
Unless otherwise specified, TA = 25 0 C. All parameters are specified for a signal level of 0 dBmO at 1kHz. The

odBmO level is assumed to be 1.54 Vrms measured at the output of the transmit or receive filter.

Symbol

Units

Conditions

Parameter

TRANSMIT FI LTER (Transmit filter input op amp set to the non-inverting unity gain mode, with VFxl = 1.09 Vrms
unless otherwise noted.)

-3.2V«
We:..>
-'
w2
I-:::J

-

:;:

SPECIFICATIONS
AC ELECTRICAL CHARACTERISTICS

(Continued)

Unless otherwise specified, T A; 25 0 C. All parameters are specified for a signal level of 0 dBmO at 1KHz. The

odBmO level is assumed to be 1.54 Vrms measured at the output of the transmit or receive filter.
Symbol

Parameter

Typ

Min

Conditions

Max

Units

RECEIVE OUTPUT POWER AMPLIFIER
IBP

Input leakage Current. PWRI

RIP

Input Resistance. PWRI

ROPl

Output Resistance. PWRO +.
PWRO-

ClP

load Capacitance.PWRO +.
PWRO-

GAp+

Gain. PWRI to PWRO +

GAp"

Gain. PWRI to PWRO -

RL = 600n Connected Between
PWRO + and PWRO -. Input
level = 0 dBmO (Note 4)

GRpl

Galntracking Relative to 0 dBmO
Output level

V = 2.05 Vrms. RL = 600n
V = 1.75 Vrms. RL = 300n (Notes 4. 5)

SlDp

SignallDlstortion

V = 2.05 Vrms. RL = 60011 (Notes 4.
5)
V=1.75Vrms, RL = 30011

VOSP

Output DC Offset. PWRO+,
PWRO-

PWRI Connected to GNDA

- 50

PSRR5

Power Supply Rejection of Vee
or VBB

PWRI Connected to GNDA

45

Note1:

Maximum power consumption will depend on the load impedance connected to'the power amplifier. The specification

-2.5V:sV IN :s25V

0.1

3

Amplifiers Active

II

500

-0.1
- 0.1

0.1
0.1

dB
dB

-45
-45

dB
dB

50

mV
dB

TYPICAL PERFORMANCE CHARACTERISTICS
Transmit Filter Stage

Receive Filter Stage
10

II

-10
w

c

:::>
....
:::;

...

....

...::e
:::;

:IE

«
We..>
...1-

W2

1-;::)

:E

HC-5512D
PCM or CVSD Monolithic Filter
Pinout

Features
• +sv, -sv Power Supplies

TOP VIEW
CEROIP

• Low Power Consumption:
4SmW (SOOn OdBm Load) ,
30mW (Power Amps Disabled)

BOTTOM VIEW
LCC

• Power Down Mode: ...................................... O.SmW

VF,O

• No External Anti-Aliasing Components

GNOA

• Sin x/x Correction in Receive Filter

CLKO
PON

• SO/60Hz Rejection in Transmit Filter

CLK

• TTL and CMOS Compatible Logic

GNOO

PWAO+

• All Inputs Protected Against Static Discharge
Due to Handling

PWAO·

VFAI

VBB

vcc

• Military Temperature Range ....... -SSoC to +12S o C

Description
The HC-55120 filter is a monolithic circuit containing
both transmit and receive filters originally designed for
PCM COOEC filtering applications in 8kHz sampled
systems.

used to simu.late classical LC ladder filters which exhibit
low component sensitivity.

The fi Iter lends itself well as a cost effective replacement
of a discrete audio input/output filter for CVSO/
PCM/AOPCM/PAM speech filtering. Other applications
include telephone line cards, modems and multiplexers.

The transmit filter isa fifth order ellciptic low pass filter in
series with a fourth order Chebyshev high pass filter. It
provides a flat response in the passband and rejection of
signals below 200Hz and above 3.4kHz.

The HC-55120 is a wider specification version of the
HC-5512 that meets military requirements and most
03/04 and CCITT specifications. To meet the Harris
Military Oash -8 program (-55 0 C to +125 0 C), the
HC-55120 undergoes a manufacturing process which
requires more test, burn-in and inspection than the
HC-5512.
The filter is manufactured using double-poly silicon gate
CMOS technology. Switched capacitor integrators are

Transmit Filter Stage

Receive Filler Stage
The receive filter Is a fifth order elliptic low pass filter
designed to reconstruct the voice signal from the
decoded/demultiplexed signal which, as a result of the
sampling process, is a stairstep signal having the inherent
sin x/x frequency response. The receive filter approximates the function required to compensate for the
degraded frequency response and restore the flat
passband response.

Functional Diagram
os.

PWRI VFRO

Vee

v ••

8-48

GNDD

GNDA

·fDN

Specifications HC-5512D
C

N

,....

Absolute Maximum Ratings

Lt)
Lt)

Supply Voltages ........................................................................................ ±7V
Input Voltage ............................................................................................ ±7V
Output Short-Circuit Duration ................................................... Continuous
Operating Temperature Range ......................................... -55 0 C to +125 0 C
Storage Temperature .......................... ,.............................. -65 0 C to +150 0 C
Lead Temperature (Soldering, 10 seconds) ...................................... 300 0 C

DC Electrical Characteristics

SYMBOL

I

o

J:

Unless otherwise noted, TA = -S5 0 C to +125 0 C, VCC + 5.0V ±5%,
Clock Frequency is 1.S44MHz. Typical parameters are specified at T A = + 2S o
C, VCC = + S.OV, VBB = -S.OV. Digital interface voltages measured with respect
to digital ground, GNDD. Analog voltages measured with respect to analog
ground, GNDA.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

SO
-SO
3.0
-3.0
4.6
-4.6

200

pA
pA
mA
mA
mA
mA

POWER DISSIPATION
ICCO
IBBO
ICC1
IBB1
ICC2
IBB2

VCC
VBB
VCC
VBB
VCC
VBB

Standby Current
Standby Current
Operating Current
Operating Current
Operating Current
Operating Current

PDN = VDD, Power Down Mode
PDN = VDD, Power Down Mode
PWRI = VBB, Power Amp Inactive
PWRI = VBB, Power Amp Inactive
Note 1
Note 1

-200
-7.0
-9.0

7.0
9.0

DIGITAL INTERFACE
IINC
IINP
IINO
Vil
VIH
VllO
VIIO
VIHO

Input
Input
Input
Input
Input
Input
Input
Input

Current, ClK
Current, PDN
Current, ClKO
low Voltage, ClK, PDN
High Voltage, ClK, PDN
low Voltage, ClKO
Intermediate Voltage, ClKO
High Voltage, ClKO

GNDD ~ VIN ~ VCC
GNDD ~ VIN ~ VCC
GNDD ~ VIN ~ VCC - O.SV

-10
-100
-10
0
2.2

10
100
0
0.8
VCC
VBB +O.S
0.8

VBB
-0.8
VCC -o.S

VCC

pA
pA
pA
V
V
V
V
V

VCM
CMRR
PSRR+
PSRRROl
Rl
Cl
VOxl
AVOl
Fc

Input leaKage Current, VFxl
Input Resistance, VFxl
Input Offset Voltage, VFxl
Common Mode Range, VFxl
Common Mode Rejection Ratio
Power Supply Rejection of VCC
Power Supply Rejection of VBB
Open loop Output Resistance, GS x
Minimum load Resistance, GS x
Maximum load Capacitance, GS x
Output Voltage Swing, GS x
Open loop Voltage Gain, GS x
Open loop Unity Gain Bandwidth,
GS x

01-

U«

Wu

-

-'
wZ
1-:::>

TRANSMIT INPUT OP AMP
IBxl
Rlxl
VOSxl

en

,Z
::;;;~

::;;;

VBB ~ VFx l ~ VCC
VBB ~ VFx l ~ VCC
-2.SV ~ VIN ~ +2.SV
-2.SV

~

VIN

~

+2.SV

-100
10
-20
-2.S
60
60
60

100
20
2.S

10
100
2.S

-2.S
3000

Rl2: 10k
Rl,'> 10k

2

8-49

nA
M!l
mV
V
dB
dB
dB
kl1
k!l
pF
V
V/V
MHz

Specifications HC-5512D
AC Electrical Characteristics

SYMBOL

Unless otherwise noted, typical parameters are specified at TA = +25 0 C. All
parameters are specified for a signal level of OdBm at 1kHz. The OdBm level is
assumed to be 1.54Vrms measured at the output of the transmit or receive filter.

PARAMETER

CONDITIONS

TRANSMIT FILTER (Transmit filter input op amp set to the noninverting unity gain mode, with VFxl
RLx
CL x
RO x
PSRR1
PSRR2
GAx
GR x

Minimum Load Resistance
Load Capacitance, VFxO
Output Resistance, VFxO
VCC Power Supply Rejection, VFxO
VBB Power Supply Rejection, VFxO
Absolute Gain
Gain Relative to GAx

CTR x

Absolute Delay at 1kHz
Differential Envelope Delay from
1kHz to 2.6kHz
Single Frequency Distortion
Products
Distortion at Maximum Signal Level
Level
Total C Message Noise at VFxO
with VIN = 0
Total C Message Noise at VFxO
with VIN = 0
Temperature Coefficient of
1kHz Gain
Supply Voltage Coefficient of
1kHz Gain
Crosstalk, Receive to Transmit

GRx L

20 log VFxO
VFRO
Gaintracking Relative to GAx

DAx
DDx
DP x 1
DP x 2
NC x 1
NC x 2
GAxT
GAxS

-3.2V

< VOUT < 3.2V

MIN

TYP

10

30
35
2.8

3.0
-41
-35

-1.5
-0.15
-0.35
-1.0
-15

0.16Vrms, 1kHz Signal Applied to
VFxl+, Gain = 20dB, RL =10k

Gain Setting Op Amp at 20dB,
Non-Inverting

Receive Filter Output = 2.2Vrms
VFxl+ = OVrms, f = 0.2kHz to 3.4kHz
Measure VFxO
Output Level = +3dBmO to -45dBmO
-50dBmO
-55dBmO

8-50

UNITS

= 1.09Vrms unless otherwise noted)

1
f = 1kHz, VFxl+ = OVrms
Same as above
f = 1kHz
Below 50Hz
50Hz
60Hz
200Hz
300Hz to 3kHz
3.3kHz
3.4kHz
4.0kHz
4.6kHz and Above

MAX

-0.1
-0.15
-0.25

100
3

3.2
-35
-35
-30
0.15
0.15
0.15
0.0
-10
-30
230
60

kll
pF
fl

dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
j1S
j1S

-40

dB

-40

dB

10

dBrncO

10

dBrncO

0.0004

dB/oC

0.01

dBIV
-60

dB

0.1
0.15
0.25

dB
dB
dB

Specifications HC-5512D

C

N
,...

Unless otherwise noted, typical parameters are specified at T A ~ + 25 0 C. All
(Continued) parameters are specified for a signal level of OdBm at 1kHz. The OdBm level is
assumed to be 1.54Vrms measured at the output of the transmit or receive filter.

AC Electrical Characteristics

II)
II)
I

o

J:

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

RECEIVE FILTER (Unless otherwise noted, the receive filter is preceded by a sin x/x filter with an input signal level of \.54Vrms.)
IBR
RIR
ROR
CLR
RLR
PSRR3
VOSRO
GAR
GRR

DAR
DDR
DPR1
DPR2
NCR
GART
GARS
CTXR

Input Leakage Current, VFRI
Input Resistance, VFRI
Output Resistance, VFRO
Load Capacitance, VFRO
Load Resistance, VFRO
Power Supply Rejection of VCC or
VBB, VFRO
Output DC Offset, VFRO
Absolute Gain
Gain Relative to Gain at 1kHz

Absol ute Delay at 1kHz
Differential Envelope Delay 1kHz
to 2.6kHz
Single Frequency Distortion
Products
Distortion at Maximum Signal
Level
Total C-Message Noise at VFRO
Temperature Coefficient of 1kHz
Gain
Supply Voltage Coefficient of
1kHz Gain
Crosstalk, Transmit to Receive
2010 VFRO
VFxO
g

GRRL

Gaintracking Relative to GAR

-2.5V $ VIN $ 2.5V

-100
10

100
3
100

nA
Mfl
fl
pF
kfl
dB

200
0.2
0.125
0.15
0.15
0.0
-10
-30
100
100

mV
dB
dB
dB
dB
dB
dB
dB
/1s
/1S

-40

dB

-40

dB

10
0.0004

dBrncO
dBloC

0.01

dBN

1

VFRI Connected to GNDA
f ~ 1kHz
VFRI Connected to GNDA
f ~ 1kHz
Below 300Hz
300Hz to 3.0kHz
3.3kHz
3.4kHz
4.0kHz
4.6kHz and Above

f

~

10
35
-200
-0.2

0

-0.15
-0.5
-1.0

1kHz

2.2Vrms Input to Sin xix Filter,
f ~ 1kHz, RL ~ 10k

Cf)

,2:

-60

Transmit Filter Output ~ 2.2Vrms
VFRI = OVrms, f ~ 0.3kHz to 3.4kHz
Measure VFRO
Output Level = +3dBmO to -45dBmO
-50 dBmO
-55 dBmO
Note 3

8-51

dB

:;:0
oj::
e..>

....l_

W2:

1-:::>

-0.1
-0.15
-0.25

0.1
0.15
0.25

dB
dB
dB

:;:

Specifications HC-5512D
AC Electrical Characteristics

Unless otherwise noted, iypical parameters are specified at T A= +25 0 C.· All
(Continued) parameters are specified for a signal leVel of OdBm at 1kHz. The OdBm level is
assurfled to· be 1.54Vrms measured at the output of the transmit or receive filter.

PARAMETER

SYMBOL

MIN

CONDITIONS

TYP

MAX

RECEIVE OUTPUT POWER AMPLIFIER
IBP
RIP
ROP1
CLP
GAp+
GAp-

Input Leakage Current, PWRI
Input Resistance, PWRI
Output Resistance, PWRO + PWROLoad Capacitance, PWRO + PWROGain, PWRI to PWRO+
Gain, PWRI to PWRO-

GRpL

Gaintracking Relative to OdBmO
Output Level
Signal/Distortion

S/Dp
VOSP
PSRR5

JJA
Mn
{l'

Amplifiers Active
RL = 600n Connected Between
PWRO+ and PWROInput Level = OdBmO (Note 2)
V = 2.05Vrms, RL = 600n
V = 1.75Vrms, RL = 300n (Notes 2,3)
V = 2.05Vrms, RL = 600n
V = 1.75Vrms, RL = 300n (Notes 2,3)
PWRI Connected to GNDA
PWRI Connected to GNDA

Output D,C Offset, PWRO + PWROPower Supply Rejection of VCC
or VBB

NOTES: 1.

3

0.1
10

-2.5V :S VIN :S 2.5V

500

pF
V/V
V/V

0.1
0.1
-45
-45
50

dB
dB
dB
dB
mV
dB

-1
-0.1
-0.1

-50
45

Maximum power consumption will depend on the load impedance connected to the
power am'plifier. The specification listed assulT)es OdBm is delivered to 600n connected
from PWRO+ to PWRO-.

2.

The OdBmO level for the power amplifiers is load dependent. For RL = 600n to GNDA the
OdBmO level is 1.43Vrms measured at the amplifier output. For RL = 300ft the OdBmO
level is 1.22Vrms.

3.

VFRO connected to PWRI, input signal applied to

VF~1.

Typical Performance Characteristics
TRANSMIT FILTER STAGE

RECEIVE FILTER STAGE

1D

1D r--....-r""',',TT,m"--..'+4."""""F'ILrTTEmR

D

1/

·ID
m;
:5!. ·2D

....
CI

·3D

::::;

·4D

:::>
I-

....IE

...

\

m;

;:-

I

CI

)~

.1: - FI~TJRI11~IL;:-pt--ltf~
I

·20
-3D

SIN x/xHIf+IlfI

...
:IE

·5D
-6D

·70
D.1

0.1

10
FREQUENCY (kHz)

1
FREQUENCY (kHz)
FIGURE 3.

FIGURE 2.

8-.52

1D

HC-5512D

C

....N
.."

Pin Assignments

.."
I

PIN
NO.

o

:I:
NAME

FUNCTION

1

VFxl+

The non-inverting input to the transmit filter stage.

2

VFxl-

The inverting input to the transmit filter stage.

3

GS x

The output used for gain adjustments of the transmit filter.

4

VFRO

The low power receive filter output. This pin can directly drive the receive port of an
electronic hybrid.

5

PWRI

The input to the receive filter differential power amplifier.

6

PWRO+

The non-inverting output of the receive filter power amplifier. This output can directly interface
conventional transformer hybrids.

7

PWRO.-

The inverting output of the receive filter power amplifier. This output can be used with PWRO+ to
differentially drive a transformer hybrid.

8

Vee

The negative power supply pin. Recommended input is -5V.

9

VCC

The positive power supply pin. Recommended input is 5V.

10

VFRI

The input pin for the receive filter stage.

11

GNDD

Digital ground input pin. All digital signals are referenced to this pin

12

ClK

Master input clock. Input frequency can be selected as 2.048MHZ. 1.544MHz or 1.536MHz.

13

PDN

The input pin used to power down the HC-5512D during idle periods. logic 1 (VCC) input voltage
causes a power down condition, An internal pull-up is provided.

14

ClKO

This input pin selects internal counters in accordance with the ClK input clock frequency:

,

ClK

Connect CLKO to:

2048kHz
1544kHz
1536kHz

VCC
GNDD
vee

en

An intern·al. pull-up is provided.
15

GNDA

,2

Analog ground input pin. All analog signals are referenced to this pin. Not internally connected
to GNDD.

::;;0
oj::
e:..>«
We:..>
w2

-'

16

VFxO

The output of the transmit filter stage.

-

~:::I

::;;

8-53

HC-5512D

Functional Description
The HC-5512D monolithic filter contains four main sections; Transmit Filter, Receive Filter, Receive Filter Power
Amplifier, and Frequency Divider/Select Logic (Figure 1).
A brief description of the operation for each section is
provided below.

stopband rejection and sin x/x gain correction. A postfilter which is similar to the transmit postfilter follows the
low pass stage. It attenuates clock frequency noise and
provides a low output impedance capable of directly driving an electronic subscriber-line-interface circuit.

Transmit Filter

Receive Filter Power Amplifiers

The input stage of the transmit filter is a CMOS, operational amplifier which provides an input resistance of
greater than 10Mfl, a voltage gain of greater than 3,000,
low power consumption (less than 3mW), high power
supply rejection, and is capable of driving a 10k!} load in
parallel with up to 25pl=.' The inputs and output of the
amplifier are accessible for added flexibility, Non-inverting mode, inverting mode, or differential amplifier mode
operation can be implemented with external resistors. It
can also be connected to provide a gain of up to 20dB
without degrading the overall filter performance.

Two power amplifiers are also provided to interface to
transformer coupled line circuits in PCM applications.
These two amplifiers are driven by the output of the
receive postfilter through gain setting resistors, R3 and R4
(Figure 4). The power amplifiers can be deactivated,
when not required, by connecting the power amplifier
input (pin 5) to the negative power supply VBB. This
reduces the total filter power consumption by approximately 10mW-20mW depending on output signal
amplitude.
Power Down Control

The input stage is followed by a prefilter which is a twopole RC active low pass filter designed to attenuate high
frequency noise before the input signal enters the
sWitched-capacitor high pass and low pass filters,
A high pass filter is provided to reject 200Hz or lower noise
which may exist in the signal path, The low pass portion of
the switched-capacitor filter provides stopband attenuation,

A power down mode is also provided. A logic 1 power
down command applied on the PDN pin (pin 13) will reduce the total filter power consumption to less than 1mW.
If the PWRI pin (pin 5) is connected to VBB, the power
amplifier output will enter a high impedance (three-state)
mode. Otherwise, the power amplifier output will be
clamped to VBB.
Frequency Divider and Select Logic Circuit

The output stage of the transmit filter, the postfilter, is also
a two-pole RC active low pass filter which attenuates
clock frequency noise by at least 40dB. The output of the
transmit filter is capable of driving a ±2.5V peak to peak
signal into a 10kfl load in parallel with up to 25pF.
Receive Filter

The input stage of the receive filter is a prefilter which is
similar to the transmit prefilter. The prefilter attenuates
high frequency noise that may be present on the receive
input signal. A switched capaCitor low pass filter follows
the prefilter to provide the necessary passband flatness,

This circuit divides the external clock frequency down to
the switching frequency of the low pass and high pass
switched capacitor filters. The divider also contains a
TTL-CMOS interface circuit which converts the external
TTL clock level to the CMOS logic level required for the
divider logic. This interface circuit can also be directly
driven by CMOS logic. A frequency select circuit is provided to allow the filter to operate with 2.048MHz,
1.544MHz or 1.536MHz clock frequencies. By connecting
the frequency select pin CLKO (pin 14) to VCC, a
2.048MHz clock input frequency is selected. Digital
ground selects 1.544MHz and VBe selects 1.536MHz.

8-54

HC-5512D

C

N

Interface Circuit for HC-5510 CODEC
R2

"'It)""
It)
o•

R1

INTERFACE CIRCUIT
r- -

I

-

I

-

-

-

-

-

-

-

-

J:

-,

TRANSFORMERS

I
11

600

1
I

O.lJ.lF

~VFx

I

I
1

I
1
1

Ox

14

PCM
OUT

1::4

I

HC-55121HC-5512A/HC-5512C"
-=- GNOA HC-5510/5511
HC-55120"
13
9
r-t---rtiPWROPON~-----~PON
-=-1

I

17

1

I

1
1
IL ___________ .JI

Note 1. Transmit voltage gain

0

8

PCM
IN

4

R1;2 R2 xVi (The lilter itself introduces a 3dB gain) (R1 + R2

~

10k).

Note 2. Receive gain R3 ~4R4
(R3 + R4
Note 3.

~

10k)

In the configuration shown, the receive filter power amplifiers will drive a eoo!} T to R termination to a signal level of8.5dBm.
An alternative arrangement, using a transformer winding ratio equivalent to 1.414:1 and 3000 resistor, AS, will provide a
maximum signal level of 10.1 dBm across a 600!} termination impedance.

"Note 4. The HC-5512C/HC-5512D may be used in some PCM telephone applications. it does meet mostCCITT andD3/D4 specifications for PCM telephone transmission systems.

FIGURE 4.

.•

Interface Circuit for HC-55564 CVSD

CIl

,2

:;;0

oi=

AUDIO SOURCE

VFxl+ PWRO+
INPUT
LEVEL ADJUST

VFxlGS x

CA

*~

VFRO
PWRI

AGC
5

VFXO

3

VFRI

AUDIN

DOUT

AUDOUT

DIN

~

FZ

C

~

"'"'
"'
U

u
"'

J:

1

+5V

VCC

CLKO
PDN

-5V

Vee

GNDD

VDD

J:

APT
e/D

e..>«
We..>
...J_
w2
I-:::l

4

:;;

14

(TO DATA I/F)

12

(FROM DATA I/F)

13
11
10

}

EXTERNAL
CONTROL

.1/1
11

8

*RA. RS and CA optional

2

**
CLK. GEN.

FIGURE 5.

8-55

RD .100KD to 1Mr2

HC-5512D
Applications Information
Gain Adjust

Figure 4 shows the signal path interconnections between
the HC-5512D and HC-5510 Single channel CODEC. The
transmit RG coupling components have been chosen
both for minimum passband droop and to present the correct impedance to the CODEC during sampling.
Figure 5 shows the signal path interconnections between
the HC-5512D and the HC-55564 CVSD. For the circuit
shown, the audio signal into the CVSD should be 1Vp-p
over the 3.2kHz band to obtain a flat response. RA, RS and
CA form a simple lead lag filter at the output of the
HC-5512D receive filter which introduces a pole and a
zero at 3.3kHz to help compensate against the filters'
inherent sin xix characteristic. (See Figure 3). Note that
inherent +3dS
the transmit side of the filter provides
voltage gain, and the resistor RD, at VFRI causes a voltage
loss from audio out to VFRI, owing to the 100kO output
impedance of the CVSD at audio out. Generally, the
higher the RD value used, the more thermal noise introduced to the circuit.

an

Optimum noise and distortion performance will be obtained for the HC-5512D filter when operated with system

peak overload voltages of ±2.5V to ±3.2 at VFxO and
VFRO. When interfacing toa PCM CODECorCVSDwith a
peak overload voltage outside this range, further gain or
attenuation may be required.
For example, the HC-5512/12A/12C/12D filter can be
used with the HC-551 0/11 series CODEC which has a 5.5V
peak overload voltage, or with the HC-55564 CVSD which
has a 4.0V peak overload voltage. A gain stage following
the transmit filter output and an attenuation stage following the CODEC or CVSD output are required in this case.
Board Layout

Care must be taken in PCS layout to minimize power
supply and ground noise. Analog ground 0 feach filter
and each CVSD should be connected to digital ground at
a single point, which should be bypassed to both power
supplies. Further power supply decoupling adjacent to
each filter and CODEC, and each filter and CVSD is recommended. Ground loops should be avoided between
GNDA and GNDD, between the GNDA traces of adjacent
filterS and CODECs, and between the analog ground
traces of adja~nt filters and CVSDs.

8-56

HC-tJtJtJ2' :J;j
HC-5554/57

m

HA.RRIS

PRELIMINARY

Monolithic CMOS
Serial Interface COFIDEC Family

.....

II)
~
II)
II)
II)
I

o

::I:
Features

Pinouts

M

• Complete CODEC/FILTER (COFIDEC) Family

TOP VIEW

~

II)

II)
II)
II)

• HC-5552 - p-Law with Short Frame Signaling (18 Pin)

I

• HC-5553 - p-Law with Both Short and Long Frame
Signaling (20 Pin)

VBB

VFxl+

GNDA

VFxl-

• HC-5554 - p-Law without Signaling (16 Pin)

VFRD

GS,

VCC

TS,

• HC-5557 - p-Law (16 Pin)

0,

DR
BCLKRI
CLKSEL
MCLKR/PON

• Low Standby Power (1 mW Typical)
• ±5V Power Supplies

::I:

FS,

FSR

• Low Operation Power (60mW Typical)

o

BCLKx
MCLK x

• Meets or Exceed all 03/04 and CCITI Specifications
• TTL or CMOS Compatible Digital Interfaces
• PCM Data Serial Input/Output
• Synchronous or Asynchronous Operation
• Automatic Power-Down

VBB

VFxl+

GNDA

Vfxl-

VFRD

GS,

VCC

rs;

FSR

FS,

DR
BCLKRI
CLKSEL
MCLKR/PDN

0,
BCLKx

MCLK x

SFR

SF,

SIGR

SIG x

v••

VFxl+

GNDA

Vfxl-

VFRD

GS,

VCC

TSx

FSR

FS,

DR

0,

~mlY

BCLK x

MCLKR/PDN

MCLK x

SIGR

SIG x

CI)

,2

DUAL-IN-LiNE PACKAGE

:;:0

oj::

U«
Wu

-

-'
W2

Description

1-:;:)

:;:

The CODEC/FILTER (COFIDEC) family includes A-Law
and p-Law monolithic CODEC/FIL TERS implemented
with double-poly CMOS technology.

The receive side of the device consists of:
• an expanding decoder (A-Law or p-Law) to reconstructthe analog sig nal
• a switched-capacitor low-pass filter which corrects
for the sinx/x response of the decoder output and
rejects signals above 3400Hz
• an RC active filter followed by a Single ended power
amplifier able to drive a 600X load
• a precision voltage reference

The transmit side of the device consists of:
• an amplifier with external gain adjustment
• an RC active prefilter to eliminate high frequency
noise
• a switched capaCitor band-pass filter including a
notch filter at 55Hz to reject signals below 200Hz and
above 3400Hz

The PCM word is transmitted/received in a serial format
compatible with industry standard.

• a change redistribution coder which samples and
encodes filtered signal in the companded p-Law or
A-Law PCM format

The device is operated with two (transmit and receive)
master clocks (1.536MHz, 1.544MHz or 2.048MHz) which
may be asynchronouS:

• a precision voltage reference

Also required are transmit and receive bit clock which
may vary from 64KHz to 2.048MHz and transmit and
receive frame sync pulses.

• an internal auto-zero network to cancel the transmit
offset

8-57

HC-5552/53/54/57
Functional Diagram

Pin Description
HC-5552
PIN #

HC-5553
PIN #

HC-5554
HC-5557
PIN #

FUNCTION

NAME

1

1

1

VBB

2

2

2

GNPA

Ground Analog Ground. All signals are referenced to this pin.

Negative Power Supply VBB = -5V ±5%.

3

3

3

VFRO

Analog Output of the Receiver Filter.

4

4

4

VCC

Positive Power Supply VCC = +5V ±5.

5

5

5

FSR

Receive Frame Sync Pulse. An 8KHz pulse train which enables the PCM
word to be shifted into the receiver register.

6

6

6

DR

Receive Data Input. The receiver register clocks in DR input with bit clock
falling edge following an FSR rising edge.

7

,7

7

BCLKR
& CLKSEL

Bit Clock which shifts DR data into the receiver register. May vary from
64KHz to 2.048MHz. Alternately may be a clock selection in synchronous
mode. See Table 1 in Functional Description for synchronous operation.

8

8

8

MCLKR
& PDN

Receive Master Clock must be 1.536, 1.544 or 2.084MHz. May be
asynchronous with MCLKx and BCLKR. If MCLKR is low, the COFIDEC
operates in synchronous mode. If MCLKR is tied high, the COFIDEC is
powered down.

9

SFR

When high during FSR, SFR indicates a receive signaling frame in long
frame mode.

9

10

SIGR

The signaling bit appears at this output after each receive signaling frame.

10

1.>1

SIGX

Signaling Data Input. This input is inserted in place of LSBor PCM word
during signaling frame.
.

12

SFX

When high during FSX, SFX indicates a transmit signaling frame in long
frame mode.
Transmit Master Clock. Must be 1.536, 1.544 or 2.048MHz. May be
asynchronous with MCLKR. See table 1 in Functional Description for
synchronous operation.

11

13

9

MCLKX

12

14

10

BCLKX

'."

"

Bit Clock. May vary from 64KHz to 2.04!1MHz, but must be synchronous with
MCLKX·

13

15

11

DX

Three-State PCM data output enabled by FSX'

14
-

16

12

FSx

Transmit Frame Sync Pulse. An .8KHz pulse train which enables the PCM
word to be shifted out through DX with BCLKX'

15

17

13

TSX

Open drain output. Pulled down durning time slot.

16

18

14

GSX

Analog output of transmit amplifier. Used to set the gain.

17

19

15

VFXI-

Inverting input of transmit amplifier.

18

20

16

VFXI+

Non inverting input of transmit amplifier.

8-58

Functional Description HC-5552/53/54/57
Power Up/Power Down

Asynchronous Operation

The COFIDEC is automatically placed into the powerdown mode when VCC and VBB are applied to the circuit.
All the analog blocks are de-activated and the Ox and
VFRO outputs are in their high impedance state.

Two asynchronous modes are allowed with excellent
transmission performance:

When a low level or a clock is applied on MClKR, the
COFIDEC powers up.
During the first two frames, the Ox output is in the high impedance state. To compensate rapidly for the offset of the
transmit section, the auto-zero circuit is in quick capture
mode during the first 512 frames and the input of the low
pass filter is set to zero during the first 256 frames.
When a high level is applied on MClKR, the device goes
into power down mode.
Transmit Section
The input of the transmit section is an operational amplifier whose gain can be externally adjusted. This amplifier
exhibits low noise, wide bandwidth and low offset voltage
(1 mV typical). The input amplifier drives an anti-aliasing
RC active filter. The switched capacitor band-pass filter is
split into a 5th order elliptic low-pass filter and a 3rd order
elliptic high-pass filter which includes a 55Hz notch filter
to guarantee excellent line (50 or 60Hz) rejection. The
structure of each filter is fully differential so that their performance is not affected by parasitic elements.
The A/D converter is of acompanding type according toA
(HC-5557) or Ii (HC-5552/53/54) coding laws.
Receive Section

10 / MClKR is fully independent of MClKX and must be
2.04BM Hz for HC-5557 (A law) and 1.544 or 1.536MHz for
HC-5552/53/54 (j1 law) (freq MClKX ~ freq MClKR
± 50ppm).
20 / If required, MClKX can also be used as a master clock
for both transmit and receive sections (MClKX input connected externally to MClKR input).
In both modes, BClKX and BClKR may operate from
64KHz to 2.04BMHz. BClKX must be synchronous with
MClKX, but BClKR may be asynchronous with MClKR
(freq BClKR ~ freq MClKR ± 50ppm).

BCLKR/CLKSEL

HC-5557

HC-5552/53/54

Clock

2.048MHz

1.S44/1.S36MHz

Low
High or Open

1.S36/1.S44MHz

2.048MHz

2.048MHz

1.S36/1.S44MHz

C\I

It)
It)
It)
I

o

J:

Detection of Short or Long Frame Operation

Signaling
In transmission, the signaling bit provided by SIGX input
is latched by the Bth BClKX rising edge after FSX low to
high transition and inseted in place of the lSB of the PCM
word during the frame.
In reception, the signaling bit is extracted from the PCM
word (lSB) in the receive register and transferred to SIGR
output. The data at SIGR output will be held until next
signaling frame. At the same time the decoder compensates for the loss of the lSB by setting the LSB to 1/2 to
minimize noise and distortion.
• In SHORT frame, the COFIDEC senses a signaling frame
when FSX (FSR) is still high during the 1st falling edge of
BClKX (BClKR) after FSX (FSR) low to high transition.
• In lONG frame, the frame sync pulses FSX and FSR are 3
or more bit cl6ck periods long. A signaling frame is identified from SFX and SFR for transmit and receive sections
respectively. SFX (SFR) must be high for 3 or more BClKX
(BClKR) periods for a signaling frame and stay low for a
non signaling frame.
NOTE: Transmit and Receive Sections must be both in LONG frame or
both in SHORT frame.

The bit clock BClKX may vary from 64KHz to 2.04BMHz
provided that BClKX is synchronous with MClKX. For
1.544MHz operation, the device automatically compensates for the 193rd clock pulse of each frame.

.........

Similarly, when FSR is high, the first BClKR rising edge
enables the PCM word to be latched in from DR input with
the B following falling edges of BClKR.

Upon power up a short frame operation is assumed.

TABLE 1.

J:

CO)
It)

In both short and long frame operation, when FSX is high,
the first BClKX rising edge enables the Ox buffer and
shifts the sign bit out. The other bits are sh ifted out with
the 7 following rising edges of BClKX. The falling edge of
the Bth BCLKX pulse disables the Ox buffer.

As for the transmit part, the filters are fully differential.
The output amplifier has a unity gain and can drive a
6000/500pF load.

A low level on MClKR input presets the circuit into
synchronous mode. In this case, MClKX and BClKX are
used for both transmit and receive sections, and BClKR is
used as a master clock select. A high level or open circuit
selects the normal frequency and a low level selects the
alternate frequency (See Table 1 below).

I

o

Data Acquisition and Transmission

A long frame of short frame operation is detected by sensing FSX on the 3rd rising edge of BClKX after FSX low to
high transition. At this time, if a high level is sensed on
FSX, a long frame operation is detected.

Synchronous Operation

~

It)
It)
It)

The degradation of the signal to total distortion ration
under all permitted asynchronous conditions does not
exceed 0.5dB as compared to the same measurement
made with fully synchronous clocks.

The receive section includes an expanding D/A converter
according to A (HC-5557) or Ii (HC-552/53/54) coding
laws. The decoder is followed by a 5th order switched
capacitor low-pass filter and an RC active filter.

Seperately trimmed voltage references are provided for
transmit and receive sections respectively. Clocking
circuits and internal power supplies are also fully
independent. This arrangement greatly reduces crosstalk
between the transmit and receive blocks and improves
performance.

.....

It)

HC-5553 can be used for both short and long frame signaling. For short
frame use, SFX and SFR should be tied low or left open circuit.
HC-5552 is intended for short frame application only. Signaling is not
possible with HC-5554 or HC-5557.

8-59

CI)

,2

:;;0
oj::::
u

:;;

Specifications HC-5552/53/54/57
Absolute Maximum Ratings
vee to GND ..................................................... -0.3V to +7V
VBB to GND ..................................................... +0.3V to -7V
Voltage at any Digital
Input or Output ..................... Vee +0.3V to GND -0.3V
Voltage at any Analog
Input or Output ...................... Vee +0.3V to VBB -0.3V

Electrical Characteristics

SYMBOL

Operating Temperature Range .................-25 0 e to +800 e
Storage Temperature Range .................. -65 0 e to +150 0 e
Lead Temperature (Soldering 10 seconds) .......... +300 0 e

Unless otherwise specified: Vee; 5.0V ± 5%, VBB -5V ± 5%, GND ; OV
T A; +ooe to +700 e: typical characteristics specified at Vee; 5.0V, VBB ; 5.0V,
T A; +25 0 e; all signals are referenced to GND.
CONDITIONS

PARAMETER

MIN

TYP

MAX

UNITS

0.6

V

Digital Interface
VIL

Input Low Voltage

VIH

Input High Voltage

VOL

Output Low Voltage

OX, IL = 5.0mA
SIGR, IL = 1.0mA
TSX, IL = 3.2mA, Open Drain

VOH

Output High Voltage

OX, IL = -5.0mA
SIGR, IL = -1.0mA

2.4
2.4

IlL

Input Low Current (Note 1)

GND:SVIN:SVIL, All Digital Inputs

-10

10

p.A

IIH

Input High Current (Note 1)

10

p.A

10Z

Output Current in High Impedance State

:s VIN :s VCC
OX, GND :s Vo :s VCC

-10
-10

10

p.A

-200

200

V

2.2

VIH

0.4
0.4
0.4

V
V
V
V
V

Analog Interface with Transmit Input Amplifier (All Devices)
IIXA

Input Leakage Current

-2.5V

RIXA

Input Resistance

-2.5V

:s V :s +2.5V, VFXI+ or VFXI:s V :s +2.5V, VFXI+ or VFXI-

ROXA

Output Resistance

Closed Loop, Unity Gain

RLXA

Load Resistance

GSX

nA
Mn

10
1

3

n
kn

10
50

pF

CLXA

Load Capacitance

GSX

VOXA

Output Level

GSXRL = 10kn

±2.8

AVXA

Voltage Gain

VFXI+ to GSX

5000

FUXA

Unity Gain Bandwidth

VOSXA
VCMXA
CMRRXA

Common-Mode Rejection Ratio

60

80

dB

PSRRXA

Power Supply Rejection Ratio

60

70

dB

±4.2

V
V/V

1

2

Offset Voltage

-20

1

Common-Mode Voltage

-2.5

MHz
20
+2.5

mV
V

Analog I nterface with Receive Filter (All Devices)
RORF

Output Resistance

Pin VFRO

RLRF

Load Resistance

VFRO = ±2.5V

CLRF

Load Capacitance

VOSRO

Output DC Offset Voltage

1

3

n

500

pF

100

mV

n

600

-100

Power Dissipation (All Devi6~s)
ICCO

Power-Down Current

0.15

.5

mA

IBBO

Power-Down Current

0.05

0.3

mA

ICC1

Active Current

6

9

mA

IBB1

Active Current

6

9

mA

NOTE: 1). SFX, SFR: Internal pull down (2 Ii A typical)
BelR: Internal pull up (2 Ii A typical)

8-60

Specifications HC-5552/53/54/57

.....

.."

.......

Transmission Characteristics (Continued) Unless otherwise specified: TA = +ooe to
.
Vee = 5V ± 5%, VBB = -5V ± 5%, GND = OV, f = 1.02kHz,
+700 e,

VIN = OdBmO, transmit input amplifier connected for unity
gain non-inverting.
SYMBOL

PARAMETER

MIN

CONDITIONS

TYP

MAX

UNITS

f = 50Hz 60Hz
f = 60Hz 120Hz
f = 120Hz 200Hz
f = 200Hz 300Hz
f = 300Hz 3000Hz
f = 3000Hz 3400Hz
f = 3400Hz 3600Hz
f = 3600Hz 4000Hz
f = 4000Hz 4600Hz
f = 4600Hz and Up

Transmit Gain
Relative to Gain
at 820Hz (OdBmO)

I

o

::I:
C")

.."

C\i
.."

Transmit Section Transfer Characteristics
GXR

oo:t
.."
.."
.."

-35
-7
-0.15
+0.15
+0.15
+0.15
+0.15
0
-14
-32

I

-1.8
-0.15
-0.7

dB
dB
dB
dB
dB
dB
dB
dB
dB
dB

.."
.."
I

o

::I:

AG (dB)

+0.15

o

-0.15

-0.7

----120 200

300

3000

!3600
3400

4000 4600

f (Hz)

'"

,2:

::;;;S?
01-

U«

Wu
W2:

....1_

I-::::l

::;;;

AG (dB)

+0.15
·-0.15=:::0
-1.B
-7

I
I

- - - J ____

-14

I

-25

-----1-I

I

I
I

I

I

I

-30
-32
-35

I
I

I

I

I

I
I

I

---r --------1I

I

5060

120 200

300

f (Hz)

5000

8-61

Specifications HC-5552/53/54/57
Transmission Characteristics (Continued) Unless otherwise specified: TA = +ooe to +7oo e,
Vee = 5V ± 5%, VBB ~ -5V ± 5%, GND = OV, f = 1.02kHz,
VIN = OdBmO, transmit input amplifier connected for unity
gain non-inverting.
PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Amplitude Response
Absolute Levels

Maximum Overload Levels

Nominal OdBO levels is 4dBm (6000)
OdBmO (All devices)

1.2277

Vrms

HC-5552, HC-5553, HC-5554
(3.17dBmO)
HC-5557 (3.14dBmO)

2.501
2.492

VDC
VDC

GXA

Transm it Gain, Absol ute

TA = +25 0 C, VCC = 5V, VBB= -5V
Input at GSX = OdBrTiO at 1020Hz

GXATV

Absolute Transmit Gain
Variati.on with Temperature and
Supply Voltage

TA = +OoC to +700 C
VCC = 5V ± 5%, VBB = -5V ± 5%

GXRL

Transmit Gain Variations
with level

Sinusoidal Test Method
Reference Level = -10dBmO
VFXI+ = -40dBmO to +3dBmO
VFXI+ = -50dBmO to -40dBmO
VFXI+ = -55dBmO to -50dBmO

0.15

dB

±0.15

dB

0.2
-0.4
-1.2

0.2
0.4
1.2

dB
dB
dB

-0.15

0.15

dB

±0.15

dB

0.15

GRA

Receive Gain, Absolute

TA = +25 0 C, VCC = 5V, VBB = -5V
Input = Digital Code Sequence
for OdBmO Signal at 1020Hz

GRATV

Absolute Receive Gain
Variation with Temperature and
Supply Voltage

TA = +OoC to +700 C

Receive Gain Variations
with Level

Sinusoidal Test Method
Reference In put PCM Code
Corresponds to an Ideally
Encoded = 10dBmO Signal
PCM Level Level = -40dBmO to +3dBmO
PCM Level = -50dBmO to -40dBmO
PCM Level = -55dBmO to -50dBmO

0.2
-0.4
-1.2

+0.2
+0.4
+1.2

dB
dB
dB

RL = 6000

-2.5

2.5

V

290

315

/1S

140
100
50
20
60
80
140

220
145
75
50
100
110
200

/1S
/1S
/1S
/1S
/1S
/1S
/1S

160

180

/1S

40
90
120
140

60
120
140
175

/1S
/1S
/1S
/1S

GRRL

VRO

Receive Ouput Drive Level

VCC = 5V ± 5%, VBB = -5V ± 5%

.Envelope Delay Distortion with Frequency
DXA

Transmit Delay, Absolute

f = 1600Hz

DXR

Transmit Delay, Relative to DXA

f
f
f
f
f
f
f

ORA

Receive Delay, Absolute

f = 750Hz

ORR

Receive Delay, Relative to ORA

f.= 500Hz f = 1600Hz f = 2600Hz f = 2800Hz -

=
=
=
=
=
=
=

500Hz 600Hz 800Hz 1000Hz 1600Hz 2600Hz2800Hz -

8-62

600Hz
800Hz
1000Hz
1600Hz
2600Hz
2800Hz
3000Hz

1600Hz
260Hz
2800Hz
3000Hz

Specifications HC-5552/53/54/57

,...

It)

Transmission Characteristics (Continued) Unless otherwise specified: TA ; +ooe to +700 e,
Vee; 5V ± 5%, VBB; -5V ± 5%, GND; OV, f; 1.02kHz,

~
It)
It)
It)

VIN ; OdBmO, transmit input amplifier connected for unity
gail1 non-inverting.

I

o

:t

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+0.15
+0.15
+0.15
0
-14

dB
dB
dB
dB
dB

-30
-40

dB
dB

CO)
It)

Receive Section Transler Characteristics
GRR

SOS

Receive Gain
Relative to Gain
at 820Hz (OdBmO)

Spurious Out-ol-Band
Signals at the
channel output

N

I;
I;
I;
I;

I ; OHz
3000Hz
3400Hz
3600Hz
4000Hz

-

-

-

3000Hz
3400Hz
3600Hz
4000Hz
4600Hz

-0.15
-0.7

Image Signals at VFRO:
f; 4600Hz 7600Hz
f; 7600Hz 8400Hz

It)
It)
It)
I

o

:t

~G (dB)

en

,z

:;;0
oj::::

U«

-14

UJu
...J _
UJz
1-::>

:;;

I
I
I

---------------------~-

I
I

-30
-40

I
--------------------rI
I
- - --- --- ------- -- --,

3000

:3600
3400

8-63

40004600

7000 7600 8000 8400

f (Hz)

Specifications HC-5552/53/54/57
Transmission C"haracterlstlcs (Continued)

Unless otherwise specified: TA=+OOCto +7OCC,

vcc: 5V ± 5%, VBB: -5V ± 5%, GND: OV, f: 1.02kHz,
YIN: OdBmO, transmit input amplifier connected for unity
gain non-inverting.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Noise
NXC

Transmit Idle Channel Noise,
C Message Weighled

HC-5552, HC-5553, HC-5554
VFXI+ =DV

12

15

dBrnCO

NXp

Transmit Noise,
P Message Weighted

HC-5507
VFXI+ = OV

-74
-70

.,69
.,67

dBmOp
dBmOp

NRC

Receive Idle Channel Noise,
C Message Weighted

HC-5552, HC-5553, HC-5554
PCM Code equals alternating
Positive and Negative Zero

8

11

dBrnCO

NRP

Receive Idle Channel Noise,
P Message Weighted

HC-5557
PCM Code equals Positive Zero

-82

-79

dBmOp

NRS

Noise, Single Frequency

f = OKHz to 100KHz, Loop Around
Measurment, VFXI+ = OVrms

-53

dBmO

(Note 1)
(Note 2)

Power Supply Rejection
PPSRX

Positive Power Supply Rejeclion
Transmit

VFXI+ = OVrms
VCC = 5.0VDC + 100mVrms
f = 0 - 50KHz

40

dBC

NPSRX

Negative Power Supply Rejection
Transmit

VFxl+ = OVrms
VBB = -5.0VDC + 100mVrms
f = 0 - 50KHz

40

dBC

PPSRR

Positive Power Supply Rejection
Receive

PCM Code equals Posilive Zero
VCC = 5.0VDC + 100mVrms
f= 0 - 4000Hz
f = 0 - 50KHz

40
25

dBC
dB

PCM Code equals Positive Zero
VBB = -5.0VDC + 100mVrms
f = 0 -4000Hz
f = 0 - 50KHz

40
25

dBC
dB

Sinusoidal Test MethOd
Level = 3.OdBmO
= OdBmO to -30dBMO
= -40dBmO XMT
RCV
= -55dBmO XMT
RCV

33
36
29
30
14
15

dBC
dBC
/ dBC
dBC
dBC
dBC

NPSRR

Negative Power Supply Rejection
Receive

Distortion

STDX/R

Signal to Total Distortion
Transmit or Receive
Channel

SFDX

Single Frequency Distortion
Transmit

SFDR

Single Frequency Distortion
Receive

IMD

Intermodulation Distortion

!

,",

Loop Around Measurement,
VFXI+ = -4dBmO to -21dBmO,
two frequencies in the range
300Hz to 3400Hz

-46

dB

-46

dB

-41

dB

Crosstalk
CTX-R

Transmit to Receive Crosstalk
OdBmO Transmit Level

f = 300Hz - 3400Hz
DR = Steady PCM Code

-90

-75

dB

CTR-X

Receive to Transmit Crosstalk
OdBmO Receive Level

f = 300Hz - 3400Hz
VFXI+ = OV

-90

-70

dB

NOTE: 1). Quantization Noise. measured by extrapolation from the distortion result.
2). Idle Channel Noise, due to alternating sign bit of a perfectly zeroed encoder,

8-64

HC-5552/53/5457

It)

PARAMETER

SYMBOL

.....

Timing Specifications
CONDITIONS

MIN

TYP

MAX

UNITS

Clocks

'I:t

It)
It)
It)
I

l/TPM

Frequency of Master Clock

Depends on the Device used
and the BCLKR/CLKSEL pin
Selection

1.536
1.544
2.048

MHz
MHz
MHz

TWMH

Width of Master Clock High

VIH

= 2.2V

160

ns

TWML

Width of Master Clock Low

VIL

= 0.6V

160

ns

TRM

Rise Time of Master Clock

50

ns

TFM

Fall Time of Master Clock

50

ns

TPB

Period of Bit Clock

15625

ns

TWBH

Width of Bit Clock High

VIH

= 2.2V

160

ns

TWBL

Width of Bit Clock Low

VIL

= 0.6V

160

ns

o

::t

C")
It)

C\I

It)
It)
It)
I

488

TRB

Rise Time of Bit Clock

TPB

~

488ns

50

ns

TFB

Fall Time Bit Clock

TPB

~

488ns

50

ns

o

::t

Frame Sync Pulses
TSFB

Frame Sunc High Set up
before 1st Bit Clock rising

50

ns

THOLD

Frame Sunc Low Hold
after Bit Clock rising

50

ns

TWFH

Width of Frame Sync High

100

ns

TSFBS

Frame Sync Low Set up
before 1st Bit Clock falling

Short Frame without Signaling

100

ns

THFBS

Frame Sync High Hold
after 1st Bit Clock falling

Short Frame with Signaling

100

ns

TSFBL

Frame Sync Low Set up
before 3rd Bit Clock rising

Short Frame with Signaling

100

ns

THFBL

Frame Sync High Hold
after 3rd Bit Clock rising

Long Frame

100

ns

TWFL

Width of Frame Sync Low

Long Frame and 64KBitis

TSSFB

SFX/R Set up before 1st Bit Clock rising

THSFB

en
,z

::;:0

100

ns

Long Frame Signaling

0

ns

SFX/R Hold after 3rd Bit Clock rising

Long Frame Signaling

100

ns

Load

Data

= 150pF + 2 LSTTL loads

TDBXE

Delay from 1st Bit Clock rising to TSX Low

TDBXZ

Delay from 8th Bit Clock
falling to TSX disabled

TDBDE

Delay from 1st Bit Clock
rising to Data output enabled

Load

= 150pF + 2 LSTTL loads

TDBD

Delay from Bit Clock
rising to Data output valid

Load

= 150pF + 2 LSTTL loads

TDBDZ

Delay from 8th Bit Clock
falling to Data ciutput disabled

TSSGB

SIGX. Set up before 8th Bit Clock rising

50

ns

THSGB

SIGX. Hold after 8th Bit Clock rising

roo

ns

TSDB

Data input Set up before Bit Clock falling

50

ns

THDB

Data input Hold after Bit Clock falling

50

ns

TDBSG

Del~y from 8th Bit Clock

300

ns

20

140

ns

50

165

ns

20

165

ns

180

ns

165

ns

50

Load

~

50pF + 2 LSTTL loads

falling to SIGR valid

8-65

oj::
u
::;:

HC-5552/53/5457
Timing Diagrams
_TPM---I
I

I

MCLKX/R

I
II

TWBH~

+---t-- TWBL TRB ~Ir

II

'I

I

I

ITWFH •

d

II

I

I

I'

I

I

•

."'".... THRBS

'I11III,
~

i.

SHORT FRAME WITH SIGNALING

- I

TWFL I

.4---,.... THFBL

i

FSX/RlI'ItIIA

TSSFP~""

LONG FRAME

-1--:THSFB

WMI

SFX/R

TWML

III
.I~ TSFBL

II~I I I,

FSX/R

~t-

SHDRT FRAME WITHOUT SIGNALING

II

:

TFM

----------------~

II

II

I

i-TPB-'

II

-..TSFBS

I~I
' 1I
1

• __ 1
_ _oI!

I

I

~

;....TFB

I

I

I

I
'I-TSFB~
,

.j--..,.Ir

•

LONG FRAME SIGNALING

BCLKX
I
I

r'i--

FSX

-----7

I'

TOBXE ~....
TSX

:\......_...,.....--------- - - .U. .
------~<-----'>t~-2--x====~===~~~
TDBDE

DX

~-f-

TOBD

SIGX

BCLKR/X

------.--"'---------

----,.+-~-..11

HC-5552/53/54/57
......

it)

~
it)

Operating Instructions
Two O.1I1F decoupling capacitors are required from the
common ground point to Vee and VSS.

Ground should be applied to the device before any other
connection. Although Vee and VSS can be connected in
any order, one should check that voltages on all inputs
and on supply rails stay within absolute maximum ratings
even for very short periods to avoid any latch-up. All
ground connections to each device should meet at a common point as close as possible to the GND pin.

The ground point of each eOFIDEe should be tied to a
common card ground in star formation, rather than via a
ground bus.

it)
it)
I

o

:I:
C")
it)

........
C\I

it)
it)
it)
I

o

RING

SLlC*

TX

+5V

TIP
RX

VBB

VFXI+

GND

VFXI-

VFRO

GSX

VCC

TSX
FSX

FSR

:I:

R1
TO PCM
HIGHWAY

Ox

DR
BCLKR

BCLKX

MCLKR

MCLKX

BCLKX
(2.048MHz/HC-5557)
(1.544MHz/HC-5554)

HC-5554/5557
FROM
PCM HIGHWAY
POWER
DOWN
RECEIVE
FRAME
SYNC

TRANSMIT
FRAME
SYNC

*HC-5502A, HC-5504, HC-5508 OR TRANSFORMER
en

TYPICAL SYNCHRONOUS APPLICATION

,2

:;;0

of::
u«
Wu
....J_
w2

I-=>
:;;

NOTICE:
Harris Semiconductor's products are sold by description only. Harris Semiconductor reserves the right to make changes in circuit design and/or specfications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders.
For maintenance of performance and reliability, Harris Semiconductor strongly recommends that the "I.C. Handling Procedures",10cated in Section 1 of
the current Analog Products Data Book, be followed closely by any activity involved with I. C Products.

8-67

(IJ

HA.RRIS

HC·55536

All-Digital Continuous Variable
Slope Delta Demodulator (CVSD)

FEATURES

DESCRIPTION

•

REQUIRES FEWER EXTERNAL PARTS

•

LOW POWER DRAIN: 1.5mW FROM SINGLE 3.0-7.0V
SUPPLY

•

TIME CONSTANTS DETERMINED BY CLOCK FREQUENCY; NO CALIBRATION OR DRIFT PROBLEMS;
AUTOMATIC OFFSET ADJUSTMENT

..

FILTER RESET BY DIGITAL CONTROL

•

AUTOMATIC OVERLOAD RECOVERY

•

AUTOMATIC "QUIET" PATTERN GENERATION

The HC-55536 is a CMOS integrated circuit used to convert
serial NRZ digital data to an analog (voice) signal. Conversion
is by delta demodulation, using the continuously variable slope
(CVSD) method.
While signals are compatible with otherCVSD circuits, the
internal design is unique. The analog loop filters have been
replaced by digital filters which use very low power and
require no external timing components. This digital approach
allows inclusion of many desirable features, which otherwise
would be difficult to implement. Internal time constants are
optimized for a 16K bit/sec data rate. However, the device
is usable from 9K bits/sec to above 64K bits/sec.

APPLICATIONS

The HC-55536 is available in a 14 pin ceramic DIP package.
Chips are available, probe tested at +25 0 C.

•

SPEECH SYNTHESIS

•

AUDIO MANIPULATIONS; DELAY LINES, ECHO
GENERATION/SUPPRESSION, SPECIAL EFFECTS, ETC.

•

PAGERS

PINOUT AND PIN DESCRIPTION

FUNCTIONAL DIAGRAM

TOP VIEW
(13)

VDD
NC
AUDIO OUT
NC

FORCE
ZERO

NC
F. Z.

DIGITAL INPUT
NC

NC

NC

NC

CLOCK

NC

GROUND

8-68

SPEC/FICA T/ONS
CD
M

ABSOLUTE MAXIMUM RATINGS
Voltage at any Pin
Maximum VOO Voltage
Minimum VOO Voltage
Operating VO~ Range

GNO -O.3V to Voo +0.3V
+7.0V
+3.0V
+3.0V to +7.0V

Operating Temperature (-5)

OOC to 75 0 C

Storage Temperature Range

-65 0 C to +150 0 C

It)
It)
It)
I

o

::I:

ELECTRICAL CHARACTERISTICS Voo: +5.0V; Bit Rate: 16K Bits/sec; TA: +25 0 C.

PARAMETER

MIN

TYP

MAX

UNIT

NOTE

16

64
70
+7.0
1.5

K Bits/Sec

(1)

Clock Sampling Rate
Clock 0 uty Cycle
Supply Voltage
Supply Current
Logic "1" Input, VIH
Logic "0" Input, VIL
Audio Output Voltage
Audio Output Impedance
Syllabic Filter Time Constant

30
+3.0
0.3
4.5

3.5

0.5
150
4.0
0.94
24
0.1
0.2
Fig. 1

L.P. Signal estimate Filter Time Conatant
Step Size Ratio
Resolution
Minimum Step Size
Slope Overload
Signal/Noise Ratio
Quieting Pattern Amplitude
Clamping Threshold

1.5
1.2

25
10
0.75

%

V
mA
V
V
VRMS
kn
ms
ms
dB

(2)
(2)
(3)
(4)
(5)
(5)
(6)

%

(7)

%

(8)
(9)

dB
mV p_p

(10)

F. S.

(11)
en

,2

:;;0

Of:
Uct

Wu

-

-'
W2

I-=>

NOTES:
1.

:;;

There is one N R'Z data bit per clock period.

7.

Clock must be

2.

3.

4.

Logic inputs are CMOS compatible at supply voltage and are
diode protected.
Digital data input is N RZ at clock (ate
and changes with negative clock transitions.

8.

The minimum step size between levels is twice the resolution.

9.

For large signal amplitudes or high frequencies, the encoder
may become slope-overloaded. Figure 1 shows the frequency
response at various signal levels, measured with a 3kHz low-

As mentioned elsewhere, this output includes a DC bias

pass filter having a 130dB/octave roll-off to -SOdS.

of VDD/2. Therefore an AC coupling capcitor (min.
4.7
f) is required unless the output filter also includes
this bais.

10. The "quieting" pattern or idle-channel audio output steps at
1/2 the bit rate, changing state on negative clock transitions.

Presents approximately

150kr

in series with recovered
11. The recovered signal will be clamped, and the computation
will be inhibited, when the recovered signal reaches threequarters of full-scale value, and will unclamp when it falls
below this value (positive or negative).

audio boltage. Zero-signal reference is VODJ2.
5.

Minimum quantization voltage level expressed as a percentage
of supply voltage.

phased with digital data such that a positive clock transition
occurs in the middle of each received data bit.

Note that filter time constants are inversely proportional
to clock rate.

6, Step size compression ratio of the syllabic filter is defined as
the ratio of the filter output, with an equal 1-0 bit density
input to the filter, to its minimum output.

8-69

SIGNAL LEVEL
OUTPUT DB

FIG. 1. Illustrates the frequency response of the HC-55536
for varying input levels. To prevent slope overload (slew
rate limiting) do not exceed the OdB boundary. The fre,.
quency response is directly proportional to the sampling
rate. The output levels were measured after filtering.

ODB IN • !lOY
Voo=+&Y

-OOB

-ODB IN

-

~~

*
Q

II)
II)

I~

I

0

DIG OUT

VDD

FZ

ANALOG GND

DIG IN

AOUT

APT

AGC

DIGITAL IN

AOUT

AIN

ENC/DEC

NC

CLOCK

NC

DIGITAL GND

ill

APT

A IN

ENc'iiDEi

:J:

DECODE

~!i
~~

is

Pin Assignments
PIN #
14-PIN
DIP

PIN #
20-PIN
LCC

SYMBOL

DESCRIPTION

1

2

VOO

2

3

Analog Gnd

3

4

AOUT

Audio Out recovered from 10 bit OAC. May be used as side tone at the transmitter.
Presents approximately 150 kilohm source with OC offset of VOOf2. Within ±2dB of
Audio Input. Should be externally AC coupled.

4

6

AGC

Automatic Gain Control output. A logic low level will appear at this output when the
recovered signal excursion reaches one-half of full scale value. In each half cycle full
scale is VOO/2. The mark-space ratio is proportional to the average signal level.

5

8

A'N

Audio Input to comparator. Should be externally AC coupled.
approximately 280 kilohms in series with VOOf2.

6,7

1,5,7,9,
10,11,
15,17

NC

No internal connection is made to these pins.

8

12

Oigital Gnd

9

13

Clock

Sampling rate clock. In the decode mode, must be synchronized with the digital input
data such that the data is valid at the positive clock transition. In the encode mode,
the digital data is clocked out on the negative going clock transition. The clock rate
equals the data rate,

10

14

E'iiCOd'ef

A single CVSO can provide half-duplex operation. The encode or decode function is
selected by the logic level applied to this input. A low level selects the encode mode, a
high level the decode mode.

Positive supply voltage. Voltage range is +3.0V to +7.0V.
Analog Ground connection to OfA ladders and comparator.

Presents
en

,2

::;;:0
oj::::

u«

UJu

Oecode

NOTE:

11

16

APi'

12

18

Oigital In

13

19

FZ

14

20

OigitalOut

Logic ground. OV reference for all logic inputs and outputs

Alternate Plain Text input. Activating this input causes a digital quieting pattern to be
transmitted, however; internally the CVSO is still functional and a signal is still
available at the AOUT port. Active low.
Input for the received digital NRZ data.
Force Zero input. Activating this input resets the internal logic and forces the digital
output and the recovered audio output into the "quieting" condition. An alternating
1-0 pattern appears althe digital output at 'htheclock rate. When this is decoded by a
receive CVSO, a 10mVp-p inaudible signal appears at audio output. Active low.
Output for transmitted digital NRZ dat,a.

No active input should be left in a "floating condition."

8-73

-'

-

UJ 2
1-::>

::;;:

Specifications HC-55564
Absolute Maximum Ratings

Operating Temperature

Voltage at Any Pin ............. " .. " GND -0.3V to VDD
Maximum VDD Voltage ............................................
Minimum VDD Voltage .......................................... ".
Operating VDD Range .............................. +3.0V to

+0.3V
+7.0V
+3.0V
+7.0V

Storage Temperature ........................... -65 0 C to +150 0 C
Operating Temperature .......................... -55 0 C to +125 0 C

Electrical Characteristics
Unless otherwise noted, TA = 25 0 C, VDD = +5.0V, Sampling Rate = 16Kbps, AG = DG = OV, AIN = 1.2Vrms.

SYMBOL

PARAMETER

ClK

Sampling Rate

IDD

Supply. Current

VIH

logic '1' Input

Vil

logic '0' Input

VOH

logic '1' Output

VOL

logic '0' Output
Clock Duty Cycle

MIN

TYPICAL

MAX

UNITS

9

16

64

Kbps

0.3

1.5

mA

3.5

Note 1

V

Note 2

V

Note 2

V

Note 3

0.4

V

Note 3

70

%

1.5
4.0

30

CONDITIONS

Audio Input Voltage

0.5

1.2

Vrms

AC coupled. Note 4

Audio Output Voltage

0.5

1.2

Vrms

AC coupled. Note 5

Audio Input Impedance

280

kO

Note 6

lOUT

Audio Output Impedance

150

kO

Note 6

AE-D

Transfer Gain

dB

No load. Audio In to
Audio Out.

AE

Encode Gain

.34

dB

AD

Decode Gain

1.23

dB

tSF

Syllabic Filter
Time Constant

4.0

mS

Note 7

tSE

Signal Estimate Filter
Time Constant

mS

Note 7

AIN
AOUT
liN

-2.0

+2.0

1.0

Resolution

0.1

%

Note 8

Minimum Step Size

0.2

%

Note 9

VQP

Quieting Pattern
Amplitude

10

mVp-p

VAL

AGC Lo Threshold

1.24

Vp-p

Note 11

VAH

AGC Hi Threshold

3.85

Vp-p

Note 11

Clamping Threshold

0.75

F.S.

Note 12

VCTH

8-74

Fl = OV or APT = OV, or
AIN =OV. Note 10

HC-55564
oo:t

NOTES:

CD

1.

There is one NRZ (Non-Return Zero) data bit per clock period. Data is
clocked out on the negative clock edge. Data is clocked into the CVSD
on the positive going edge (see Figure 2). Clock may be run at less than
9Kbps and greater than 64Kbps.

2.

Logic inputs are CMOS compatible at supply voltage and are diode
protected. Digital data input is NRZ at clock rate.

3.

Logic outputs are CMOS compatible at supply voltage and will withstand short-circuits to VOO or ground. Digital data output is NRZ and
changes with negative clock transitions. Each output will drive two
LS TTL loads.

4.

Recommended voice input range for best voice performance. Should
be externally AC coupled.

5.

May be used for side-tone in encode mode. Should be externally AC
coupled. Varies with aduio input level by ±dB.

6.

Presents series impedance with audio signal. Zero signal reference is
approximatey VDD/2.

7.

Note that filter time constants are inversely proportional to clock rate.
Both filters approximate single pole responses.

8.

Minimum quantization voltage level expressed as a percentage of
supply voltage.

9.

The minimum step size between levels is twice the resolution.

10.

The "quieting" pattern or idle-channel audio output steps at one-half
the bit rate, changing state on negative clock transitions.

11.

A logic "0" will appear at theAGC output pin when the recovered signal
reaches one-half of full-scale value (positive or negative). i e. at VDD/2
±25% of VDD.

12.

The recovered signal will be clamped, and the computation will be
inhibited, when the recovered signal reaches three-quarters of fullscale value, and will unclamp when it falls below this value (positive or
negative).

an
an
anI

o

J:

Timing Waveforms
SAMPLING CLOCK:

01

It
II

DIGITAL NRZ IN:

"tl

I:

II

I:

~II~

II
It
It

II

II

II
II

DIGITAL NRZ OUT:

L

II

DEC/ENC

0

~I

en
,2
::;;:0
oj:::

u<

-

UJu

-'

UJ 2

'OS

I

0

'OS: DATA SET UP TIME. 1DOns TYPICAL

FIGURE 2. CVSD TIMING DIAGRAM

8-75

I-=>
::;;:

HC-55564
Interface Circuit for HC-55564 CVSD
AUDIO SOURCE
HC·5512ClI2o'

INPUT
lEVEL ADJUST
RA. RB. CA
OPTIONAL

VFX1+

PWRO+

VFX1-

VFXo

~

RB 5

AUDIO OUT

AGC
AIN

VFRI

GSx

CA

HC·55564

AoUT

ooUT
DIN
FZ

VFRO

4

14
IZ

13

ITO DATA I/FJ
IFRoM DATA I/FJ

I

EXTERNAL
CONTROL

PWRI
I Voo

CLKO
PoN

+5V

VCC

-5V

II
VBB
GNoo
GNoA ClK

0.111

-

OII1~~11115.

8 DIGITAL
GNo

'HC·5512C/12o ALSO AVAILABLE IN
LCC FOR TOTAL SURFACE MOUNT
APPLICATION SOLUTION
"RD 100Kllio IMll

ClK. GEN.
FIGURE 3,

CVSD Hookup for Evaluation
The circuit in Figure 3 is sufficient to evaluate the voice
quality of the CVSD, since when encoding the feedback
signal at the audio output pin is the reconstructed audio
input signal. CVSD design considerations are as follows;
1) Care should be taken in layout to maintain isolation
between analog and digital signal paths for proper
noise consideration.
2) Power supply decoupling is necessary as close to the
device as possible. A O.1uf should be sufficient.
3) Ground, then power, must be present before any input
signals are applied to the CVSD. Failure to observe this
may cause a latchup condition which may be
destructive. Latchup may be removed by cycling the
power off/on. A power-up reset circuit may be used
that strobes Force Zero (pin 13) during power-up as
follows:

4) Analog (signal) ground (Pin 2) should be externally
tied to Pin 8 and power ground. It is recommended that
the AIN and AOUT ground returns connect only to
Pin 2.
5) Digital inputs and outputs are compatible with
standard CMOS logic using the same supply voltage.
All unused logic inputs must be tied to the appropriate
logic level for desired operation. TTL outputs will
require 1K Ohm pull-up resistors. Pins 4 and 14 will
each drive CMOS logic or one low power TTL input.
6) Since the Audio Out pins are internally DC biased to
VDD/2, AC coupling is required. In general, a value of
O.1J.1f is sufficient for AC coupling of the CVSD audio
pins to a filter circuit.
7) The AGC output may be externally integrated to drive
an AGC pre-amp, or it could drive an LED indicator
through a buffer to indicate proper speaking volume.

8-76

HC-55564
Figures 4, 5, and 6 illustrate the typical frequency
response of the HC-55564 for varying input levels and for
varying sampling rates. To prevent slope overload (slew
limiting), the OdS boundry should not be exceeded. The
frequency response is directly proportional to the

SIGNAL lEVEL
@AOUT

OdB

sampling clock rate. The flat bandwidth at OdS doubles
for every 16kHz increase in sampling rate. The output
levels were measured in the encode mode, without
filtering, from AIN to AOUT, at VOD =+5V. OdS =1.2Vrms.

1.1)
1.1)
1.1)
I

o

:::E:

i"'ol-ol-o
f""IIIIo.

f--- 6dB

~

-12dB
-IBdB

,
"-

-24dB

~

~

-!OdB
-36dB

100

"I:t
CO

1000

10000
INPUT FREOUENCY @ AIN IHzl

FIGURE 4. TRANSFER FUNCTION FOR CVSD AT 16Kbps
SIGNAL lEVEL
@AOUT

r-......... .-.

OdB
f---6dB

........ iii...

~

-12dB
-18dB
-24d8

(I)

-30d8

,2

::;;0

o~

-36d8

uc(

Wu
-'

-

W2

1-::::1

100

1000

10000
INPUT FREQUENCY @ AIN IHzl

FIGURE S. TRANSFER FUNCTION FOR CVSD AT 32Kbps

-

SIGNAL LEVEL
@AOUT
Od8
-6d8

.........

-12dB
-18dB
-24d8
-!Od8
-36dB

100

10000

1000

INPUT FREQUENCY @ AIN IHzl

FIGURE 6. TRANSFER FUNCTION FOR CVSD AT 64Kbps

8-77

::;;

HC-55564
The following typical performance distortion graphs
wererealized with the test configuration of Figure 7. The
measurement vehicle for Total Harmonic Distortion
(THO) was an HP-339A distortion measurement set, and

for 2nd and 3rd harmonic distortion, an HP-3582A
spectrum analyzer. All measurement conditions were at
VOO = +5V, and 2nd and 3rd harmonic distortion
measurements were C-message filtered. OdB = 1.2Vrms.

HC·55564

.33JlI
ADUT "'3'--_---i

.33Jl1· rv

1-__5'oi AIN

FUNCTION
GENERATOR

DEC! 10
ENC 8
DGND 2
AGND

1 VDD

11m
13

I--

FZ

HP3582A
SPECTRUM
ANALYZER
OR HP339A
DISTORTION
ANALYZER

C·MESSAGE
FILTER

+5V

-

FIGURE 7. TEST AND MEASUREMENT CIRCUIT
-10

-20

THO
-30

=::::::::::::

-40
-24

INPUT FRED=1 KHz

16KHl

32KHz

---

~ 64KHz

-16

-8
INPUT SIGNAL LEVEL dB

FIGURE 8.CVSD SIGNAL LEVEL VERSUS TOTAL
HARMONIC DISTORTION
CVSD SIGNAL TO 2ND AND 3RO HARMONIC DISTORTION C·MESSAGE WEIGHTED

CVSD INPUT LEVEL VERSUS 2ND AND 3RD HARMONIC DISTORTION CMESSAGE WEIGHTED
-I o INPUT FREQUENCY

-10

V,N=0.5VRMS
16KHZ CLOCK

1KHz

-2

o

dB -3 0

-

16KHZ CLOCK

3RO

-

~

-4 0

-

~
2ND

-50
-24

-17

-II

-3.8

-50"'0- - - - - - - , 0...
0 0 - - - - - - - 2 0...
0-0- - - - - - - - - ' 3 0 0 0

+3.0
INPUT LEVEL(dB)

A)

CVSO SIGNAL TO 2ND AND 3RD HARMONIC DISTORTION C·MESSAGE WEIGHTED

CVSD INPUT LEVEL VERSUS 2ND AND 3RO HARMONIC OISTORTION C·MESSAGE WEIGHTED
-10

-I 0

-2 o

1KHz
··20

-

-30 ~

---..::::::::

·40

-50

-17

-24

-II

J~

~

-30

"-

dB

-40

-3.8

·6 U

+3.0
INPUT LEVEL(dB)

1000

-40

-50
-24
C)

-

-17

............;:

-11

-3.8

+3.0

·60

INPUT LEVEL(dB)

o
C)

FIGURE 9A, e, C. CVSD INPUT LEVEL VERSUS
2ND AND 3RD HARMONIC DISTORTION

V,N-0.5VRMS
64KHZ CLOCK

'"

-40
-50

3RO

4000
INPUT FREDUENCY(H,)

'\.

-30

--

3000

~

dB

~-;7

~

CVSO SIGNAL TO 2NO AND 3RO HARMONIC DISTORTION C·MESSAGE WEIGH TEO

-20

--..

--

-10

64KHZ CLOCK

dB

2000

B)

1KHz

~

-.....::::: ~
3RD

INPUT FREQUENCY

-20

-

-5 0

CVSD INPUT LEVEL VERSUS 2ND AND 3RD HARMONIC DISTORTION C·MESSAGE WEIGHTED

-30

'\

2N;:--'"

B)

-10

V,N-0.5VRMS
32KHZ CLOCK

INPUT FREDUENCY
32KHZ CLOCK

dB

INPUT FREDUENCY(H,)

A)

1000

--::

~~
3RO

2000

3000

4000
INPUT FREQUENCY(H,)

FIGURE 10A, B, C. CVSD INPUT FREQUENCY VERSUS
2ND AND 3RD HARMONIC DISTORTION

8-78

HF-10

mHARRIS

o
.,..
I

LL

J:

PRELIMINARY
Universal Active Filter
Features
•
•
•
•
•
•
•
•
•
•

Applications

Industry Standard Pinout
Low Crosstalk ........................................................................... -60dB
Low Clock Feed Through .....................................................2mVrms
Low Standby Current ............................................................... SOO/iA
Clock to Center Frequency Ratio Accuracy ±2%
Filter Cutoff Frequency Stability Direclly Dependent on
External Clock Quality
Separate High-pass (or Notch or All-Pass),
Band-Pass, Low-pass Outputs
fo x Q Range up to 50kHz Minimum
Operates to fo = 20kHz Minimum
Specifications Guaranteed for T A from -5S o C to +12S o C

Description

• General Purpose Audio-Band Filtering
• Real-Time Programming
~ Prototyping
~ Dynamic Reconfiguration
• High Q Applications
• Precision Filtering at Low Q
• Precision Oscillators
• Extended Temperature
• Voice Response Systems
~ Modems
~ Tone Generators
• Data Acquisition Systems
• Building Block for Precision Higher-Order
Filters (Directly Cascadable)

Pinout

The HF-10 consists of two fully independent second order switched
capacitor CMOS filter sections. Each second order section is a
modified state-variable filter. In each section there are three
operational amplifiers and an additional "summing node". The extra
summing node is a direct benefit of the switched capacitor design
approach. This provides increased versatility as compared to the
classical continuous-time active filter. The transfer function of each
section is tailored by the user's choice of feedback configuration,
external resistor values. and external clock rate.
The HF-10 topology is very useful since it produces three different, but
related, transfer functions simultaneously. Each transfer function has
the same pole locations but different zero locations. One of the outputs is either a notch, all-pass, or high-pass signal, depending on the
feedback configuration chosen by the user; the other outputs are
band-pass and low-pass signals. The center frequency of the complex
pole pair, fo, is determined by the external clock frequency and the
state of the "50/100/CL" input. This value can also be scaled by a function of the external resistor val ues depending on the feedback configuration. The other important filter characteristics, such as gain, Q, etc.
are determined by functions of external resistor values. Any of the
classical filter configurations (Butterworth, Bessel, Cauer/Elliptic,
Chebyshev, etc.) can be realized.
The second order sections can be used separately with the constraint
that the clock input for each section be driven by signals of the same
level (I.e., either TTL or CMOS logic levels), and that the two clock
signals share the same digital ground. If it is desired that a fourth order
function be realized, the two sections can be cascaded. The "L Sh"
(level shift) input is used in conjunction with the clock inputs to allow
compatibility with either TTL or CMOS clock levels.
The HF-10 can be powered-down by connecting the "50/100/CL" input to Vo-. This disables the reference current generators forthe operational amplifiers and the clock level shifters.

TOP VIEW
LPA
BPA
N/AP/HPA

8-79

BPB
N/AP/HPB

INVA

INVB

SIA
SAiB
VA+

SIB
AGNO

Vo+
LSh
CLKA

VA'
Vo'
50JIOOJCL
CLKB

System Block Diagram
IHVA

en

,Z

:;;:0
oj::

U«
wZ

Wu

--'

1-::::1

:;;:

VA·@-VD·@--

INVa

SIB

AGNB@-

Filter Block Diagram
N/AP/HP SI

The HF-10 provides a number of advantages over other universal active filters: higher accuracy at frequency extremes; superior clock
feedthrough suppression; significantly lower crosstalk; better performance over -55 0 C to +125 0 C; drives smaller impedance to higher peak
output voltage; and capable of precision oscillator applications (phase
is continuous when frequency is changed).
The device is available in a 20 pin ceramic package in commercial and
military temperature ranges. Application note is available.

LPB

BP

LP

HF-10 Specifications
Absolute Maximum Ratings
Supply Voltages .................................................. ±6.5 Volts
Power Dissipation .................................................... 300mW
Operating Temperature ........................... -55 0 C to +125 0 C
Storage Temperature ............................................... +1500 C

Lead Temperature (Soldering. 10 Sec.) ..................300 0 C
Output Loading ........................................ RLOADE 3.5KO
CLOAD ~ 100pF

Electrical Characteristics (Complete Filter) ±4.5V < Vs < ±5.5V. -55 0 C < T A < +125 0 C. Refer to Figure 1.
PARAMETER

Frequency Rimge
Clock to Center Frequency
Ratio
fClK/fo = 50
fClK/fo

= 100

ORange

o Accuracy (0 Deviation from
an Ideal Continuous Filter)
fClK/fo = 50
fClK/fo

= 100

fo XO Product
fo Temperature Coefficient
fClK/fo = 50

fClK/fo

= 100

o Temperature Coefficient
Crosstalk
Clock Feedthrough
Clock Frequency
Power Supply Current
Standby Current

CONDITIONS

fo XO < 50kHz
Pin 12 = VD+, 0 = 10
fo XO < 50kHz
Pin 12 = AGND, 0 = 10
fo XO < 50kHz
fo XO < 50kHz

MIN

TYP

50

MAX

UNITS

20K

Hz

±2%
±2%
0.5

100

Pin 12 = VD+, 0 :s 20
fo XO <50kHz
Pin 12 = AGND. 0 ~ 20
fo XO < 50kHz

±4%
±3%
50K

TA = 25 0 C
Pin 12 = VD+. fo XO < 50kHz
External Clock Temperature Independent
Pin 12 = AGND, foXQ < 50kHz
External Clock Temperature Independent
TA = 25 0 C
fo XO < 50kHz, Q Setting
Resistors Temperature Independent
INVA = OdBm @ 1kHz
INVB = OV
See Figure 2
Min @ fClK/fo = 50, Max @ fClK/fo = 100
TA = 25 0 C
Pin 12 = VA-

Hz
±100

ppm/OC

±100

ppm/OC

±500

ppm/OC

-60
2
2.5

dB
5
2048

mVrms
kHz
rnA
/lA

MAX

UNITS

13
500

Electrical Characteristics (Internal Operational Amplifiers)
±4.5V < Vs < ±5.5V. -55 0 C < T A <+125 0 C, Refer to Figure 1
PARAMETER

Voltage Swing (Pins 1. 2. 3, 18,
19.20)
Op Amp Gain-BW Product
Op Amp Slew Rate
Power Supply Rejection
Ratio (PSRR)

CONDITIONS

MIN

RlOAD = 3.5KO

±3.5

DC Only

2.5
5
40

8-80

TYP

V
3.8
15

MHz
V/J1S
dB

HF-l0

o
,..

Pin Assignments

I

SYMBOL

LL.

DESCRIPTION

::I:

LP, BP,
N/AP/HP (A or B)

Low-pass, band-pass, notch or all-pass or high-pass outputs of each second order section.

INV (A or B)

Inverting input of the summing op amp of each filter.

S1 (A or B)

Inverting summing input pin used in most filter configurations.

SA/B

Activates a switch connecting one of the inputs of the filter's second summer to either analog ground
(SA/B low to VA-) or to the low-pass output of the circuit (SA/B high to VA+). This allows flexibility in the
various modes of operation of the I. C.

VA+, VD+

Analog positive supply and digital positive supply. These pins are internally connected through the I.C.
substrate and therefore, VA+ and VDx should be derived from the same power supply source. They have
been brought out separately so they can be bypassed by separate capacitors, if desired. They can be
externally tied together and bypassed by a single capacitor.

VA-, VD-

Analog and digital negative supply respectively. The same comments as for VA+, VD+ apply here.

L Sh

Level shift pin. Accommodates various clock levels with dual or single supply operation. With dual ±5V
supplies, the HF-10 can be driven with CMOS clock levels (±5V), and the "LSh" pin should betied either to
the system ground or to the negative supply pin. If the same supplies as above are used and TTL clock
levels, derived from a OV to 5V supply, are used, the "L Sh" pin should be tied to the system ground. For
single supply operation (OV and 1OV), the VD- and VA- pins should be connected to the system ground, the
AGND pin should be biased at 5V, and the "L Sh" pin should also be tied to the system ground. This will
accommodate both CMOS and TTL clock levels.

CLK (A or B)

Clock inputs for each switched capacitor filter building block. Should both be of the same level (TTL or
CMOS). The level shift (L Sh) pin description discusses how to accommodate their levels. The duty cycle
of the clock should preferably be close to 50%, especially when clock frequencies above 200kHz are used.
This allows the maximum time for the op amps to settle, yielding optimum filter operation.

50/100/CL

By tying this pin to VD+, a 50:1 clock to filter center frequency operation is obtained. Tying at mid-supplies
(i. e., analog ground with dual supplies) allows the filter to operate at a 100:1 clock to center frequency
ratio. When tied to VD-, a simple current limiting circuit is triggered to limit the overall supply current. The
filtering action is then aborted.

AGND

Analog ground pin. Should be'connected to the system ground for dual supply operation or biased at midsupply for single supply operation. The Non-inverting inputs of the filter op amps are connected to the
AGND pin so'a "clean" ground is mandatory.

Note. All pms are protected agamst static discharge.

en

,z

::;:0
oj::

Typical Filter Configuration

u«

+5V
AGNO
·5V
NA

"A

"A

:!: O.l"F ~

I

:r

wz
1-::>
::;:

O.1JiF~

LPA

R1

v"

R,A

SA/B

'9

Wu
....J_

+5

,:::ftj"-

v.

200kHz

1 LPA
LPa
aPA
apa
N/AP/HPA N/AP/HPa
lNVA
1NVa
Sla
SlA
HF·IO
6 SA/8 IUAFI AGNO
7 VA+
VA8 VD+
Vo·
9 L Sh
501100/CL
10 CLKA
CLK8

20
19
18
11
16
15
14
13
12

R3a
R28

Ala

·5V
·5V

11

FIGURE 1.
LPA
aPA
OR N/AP/HPA
FROM Hf.10

LO-

I--

RMS
VOLT·
METER

......

200kHz

ap FIlTER

fl = 180kHz
IH =. 220 kHz

FIGURE 2. MEASURING CHANNEL A CLOCK FEEDTHROUGH

8-81

m~RIS

HC-5560

ADVANCE
Transcoder
Features

Applications

• Single 5V Supply ........................................... 10mA Max.
• Mode Selectable Coding Including:
~ AMI (T1, T1C)
~ B8ZS (T1)
~ B6ZS (T2)
~ HDB3 (PCM30)
• North American and European Compatibility
• Simultaneous Encoding and Decoding
• Asynchronous Operation
• Loop Back Control
• Transmission Error Detection
• Alarm Indication Signal
• Replaces CD22103, MJ1440, MJ1471 and TCM2201
Transcoders

• North American and European PCM Transmission
Lines where Pseudo Ternary Line Code Substitution
Schemes are Desired
• Any Equipment that Interfaces T1, T1C, T2 or PCM30
Lines Including Multiplexers, Channel Service Units,
(CSUs) Echo Cancellors, Digital Cross-Connects
(DSXs), T1 Compressors, etc.

Description
The HC-5560 digital line transcoder provides encoding
and decoding of pseudo ternary line code substitution
schemes. Unlike other industry standard transcoders, the
HC-5560 provides four worldwide compatible mode
selectable code substitution schemes, including HDB3
(High Density Bipolar 3), B6ZS, B8ZS (Bipolar with 6 or 8
Zero Substitution). and AMI (Alternate Mark Inversion).
The HC-5560 is fabricated in CMOS and operates from a

single 5V supply. All inputs and outputs are TTL compatible. The HC-5560 is available in 20 pin dual-in-line
ceramic packages over the commercial temperature
range. OOC to +70 0 C.
The HC-5560 is ideally suited for use with the HC-5562
Receive Line Interface Unit (RLlU). Application Note
Number 573 is available.

Functional Diagram

Pinout
TOP VIEW

MODE 1 0 - - - - - _ - - - - - - - - ,

FORCE AIS
MODE SELECT I
NRZ DATA IN
CLOCK ENC
MODE SELECT 2
NRZ DATA OUT
CLOCK DEC

'ii'ESEf IiiS
AIS
VSS

VDD
OUTPUT ENABLE
RESET
DUll
OUT2
BIN
LOOP TEST ENABLE
AIN
CLOCK
ERROR

SELECT

20---_--t--------,

NRZ DATA IN

OVss
OVDD

~~rL...-...L..,

CLOCK
(ENCODER)

}-HI---oCLOCK

~~!:~~ o----l

.-_+-+-__-+-+__-OOUT1
+ - + - - + - + - - - i - i - - - o DUT2

LOOP TEST
ENABLE

NRl DATA

OUT
A1No-----'

.,.0-----....
FORCEAIS~
RESET~

CLOCK
(DECODER)

0--------+--+--+1

~o------~

8-82

ERROR

t - - - -......OO A1•

IJ H.ARRIS

HC·55BO

PRELIMINARY

Trunk Subscriber Line
Interface Circuit - TSLIC

Features

Applications

• Meets FCC Part 68 Isolation and Most Signal
Transmission Requirements

• Trunk Interfaces for Private Branch Exchanges (PBXs),
Automatic Call Distributors (ACDs), Remote SWitching
Units (RSUs), Least Cost Routing Systems (LCRs),
Hybrid Key Systems, and Remote Line Testers.

• Requires No External Transformers or Optolsolators
• Externally Programmable Termination Impedance

Q

co

It)
It)
I

o

J:

• Simple Interface to Data and Voice Systems
• Single Supply Operation from 5V to 15V
• Fully Integrated, Using Dielectric Isolation

Description
The Harris Trunk Subscriber Line Interface Circuit
(TSLlC) incorporates into a single integrated circuit. the
line interface on the terminal, private switching exchange,
or subscriber end of the public switched telephone network.
Using the Harris dielectric isolation process, the TSLIC
bridges the required isolation boundary without need for
transformers or optoisolators.

Pinout

The on-chip functions include on/off hook mode control,
ring detection, hybrid, relay driver, loop current monitor,
and a general purpose detector. The DC termination characteristic includes loop current limiting to minimize
power dissipation. The off-hook AC termination impedance is externally set, giving complex or resistive line
matching capability. The device can be interfaced to both
loop-start and ground-start trunk lines.

Functional Diagram
V-

,z

::;;C
oj::
(,)<1
We.:
...J _

TOP VIEW

XMIT
RELOR
RELC
VCC

GNO
RCV

ROO
ROCAP
GPO

ON/OFF

TIP'
OCCAP
LCM

Z/15
RING'
GPI
LlNE2
V+ •
LlNEI
ReAP

GENERAL

r----r-G:::::::::r-------t-GENERAL

PURPOSE

PURPOSE

OUTPUT

INPUT

OUTPUT
RINGDETECT:+:[~~~---_7-{

RINGERCA'

ROCAP

R"+-....------I
ZTERMl15

DCCA,

Mrc:::~==~-----~----~
vee
XMIT

GROUND

LDO,CURRENT
MONITOR

t====1f::

It-

T1P

'
RING'

,--++v.·
LINE 1

iiNlOFFHOOK

llNE2

8-83

wz

1-=

:;

m~RlS

He·5581

PRELIMINARY

DAA Subscriber Line
Interface Circuit - DAASLIC
Applications

Features

• Data Access Arrangement (DAA)

• Meets FCC Part 68 Isolation and Most Signal
Transmission Requirements

( • Telephone Answering Machines

• Requires No External Transformer or Optoisolators

• Facsimile Machines

• Externally Programmable Termination Impedance

• Modems and Multiplexers

• Simple Interface to D.ata and Voice Systems
• Single Supply Operation from 5V to 15V
• Fully Integrated, Using Dielectric Isolation

Description
The Harris Data Access Arrangement Subscriber Line
Interface Circuit (DAASLlC) incorporates into a single
integrated circuit, the line interface on the terminal or
subscriber end of the public switched telephone network.
Using the Harris dielectric isolation process, the
DAASLIC bridges the required isolation boundary
without need for transformers or optoisolators.

Pinout

The on-Chip functions include on/off-hook mode control,
ring detection, hybrid, dual transmit inputs, squelch, loop
current monitor, and a general purpose detector. The DC
termination characteristic includes loop current limiting
to minimize power disSipation. The off-hook AC termination impedance is externally set, giving complex or resistive line matching capability.

Functional Diagram
TOP VIEW

XMIT2
XMITl

SO
VCC

GND
RCV

ROO
RDCAP

GPO
ON/OFF

TIP'
DCCAP

LCM
Z/15
RING'
GPI
LlNE2
V+'
LlNEI
RCAP

8-84

HC-5590

mHARRIS
ADVANCE INFORMATION

Digital Line Transceiver
-DLT

Features

Applications

• Monolithic Integrated Device

• Integrated Voice and Data Transmission

• Data Rates up to 160K BItS/s will Support Two Band
One 0 Channel with Additional Overhead for Frame
and Handshake Information

• Integrated Digital Services Network
(ISDN) U-Interface

Q

C»

U)
U)
I

o

l:

• Secure Voice and Data Terminals

• Full Duplex Transmission using AMI Line Code Adaptive Hybrid Techniques
• On Chip Clock Recovery Circuit Allows the Device to be
Operated in Either a Master or Slave Mode
• Low Idle Power Dissipation Using State-of-the-art
CMOS Technology
• Line Interface Driver
• Synchronous Serial Mode Allows External Protocol
Generation with DL T Transparently Receiving/Transmitting

Description
The Harris Digital Line Transceiver (DLT) implements a
complete full duplex data transmission system using an
echo cancellation technique. Data rates up to 160KB/s
can be accommodated. Functions of the circuit can be
divided into three groups:
-transmit
-receive
-control/interface
The transmit functions include scrambler, bipolar coder

and transmit filter. Tne receive functions and receive filter, ,ff equalizer, echo canceller, detector, timing recovery and descrambler.
Transmitted and received bit streams are synchronous.
Both are locked to a master clock running at 3.88MHz (for
a 160KB/s data rate). The subscriber DL T extracts the
clock from the received signal and locks its own transmitter to the recovered clock.

en

,2

::e: o
oj::
(.)<
w(.)
.....
W2

Block Diagram

r---------------------i

1-::;)

++5

I

BX

~-5

I

I
I

M

He-5590 OLT
BLOCK DIAGRAM

I

NETR

LINE
I/O

FETR

FCLK

VT

I

I

VR

I

I
I
I

BR

I

+

I

I

I ~!ljTIMr"fLJ
L-i--r-i-i--

:

~

CONTROL

ACTR OTER ECOIS SIGM RS

8-85

SIGO

01

XTAL

MCLK

ANALOGGNO

DIGITAL GNO

::e:

m~RIS

HC-5572

ADVANCE INFORMATION
Modem Signal Processor
Features
• Monolithic Integrated Device

• Answer Tone Generation and Detection

• CCITT V.22 BISIV.22 and BELL 212A Compatible

• CCITT V.25 2100Hz Tone Generation and Detection

• Adaptive and Compromise Equalizers Ensure Modem
Performance Over Poor Telephone Line Conditions

• State-of-the-art CMOS Technology, Ensuring Low
Power Dissipation

• Microprocessor-Compatible Interface Bus
• Programmable Mode Selection

Description
The Harris Modem Signal Processor is a single chip
synchronous voiceband modem intended for use in
switched or leased lines. It is programmable for operation
at 2400, 1200, 600, or 300 bits per second (BPS), full
duplex (FOX) data transmission compatible with CCITT
V.22 BIS, V.22 or BELL 212A specifications.

the modem's performance over poor telephone line conditions.

Switched capacitor techniques are used in the HC-5572 to
perform various signal processing functions. Adaptive
and compromise equalizers are included to ensure

The HC-5572 is fabricated using CMOS technology. All
digital input and output signals are TTL compatible.
Power supply requirements are ±5V.

The telephone line interface with the HC-5572 can be accomplished with either a solid-state terminal SLlC, such
as the Harris HC~5580, or through a transformer-based
Data Access Arrangement (DAA).

Functional Diagram
HC-5512 MODEM

TXD
TXC 4- I----

I

~

CLOCKS

1:

~

~

¢:

XI
X2

03
02

CONTROL

01

LOGIC/

00

A2

AI
AD

11 PROCESSOR

INTERfACE

ViR
Rii

RXO

ENCODER

~

,.---+

FILTER/
EQUALIZER

TONE

GENERATOR/
FSX TXMT

TXA

t
U

+- r- VOD

TONE
DETECTOR

+- f- vss

FSK

r-

DECODER/
DESCRAM8lER

..

DECISION
CIRCUIT

.
..

1
ADAPTIVE
EQUALIZER

I+~

DEMODULATOR

DGNO

+- f-

AGND

- ....

RXC

1

FILTER/

EQUALIZER

..

t
AUTOMATIC
GAIN

CONTROL

L

8-86

+- f-

RECEIVER
'---

-

-1
...

MODULATOR

CLOCK/CARRIER
RECOVERY
CIRCUITS

-

cs

RES

-

SCRAMBLER

RXA

The Total Approach to Quality

9-2

Harris Standard Flows

9-2

Quality Beginning to End

9-6

Electrical Screening and Test Procedures

9-9

Harris and The JAN Program

9-12

Burn-In Circuit Index

9-13
c!li:

.-'<
.=
<-

>-

Burn-In Circuit Drawings

9-15

-

tQ

:::;)-'

OW
a:

9-1

Harris Quality and Reliability

Harris Takes the Total Approach to Quality
Quality and reliability do not occur by accident in microcircuit manufacturing. They can
be achieved only as a result of precise design, capable manufacturing methods,carefully
controlled production processes and accurate screening and testing. Quality and reliability
must be totally designed and built into the product. They are not characteristics that can
be added after manufacture. They must be part and parcel of the flow from the original
design through final assembly and test.
The major steps affecting microcircuit reliability and quality are:
•
•
•
•
•
•
•

Initial circuit selection and design.
Selection of package materials and design.
Die layout and geometry.
Raw material inspection and QC.
Wafer/die production process and controls.
Die/package assembly and controls.
Screening and test procedures.

'.

Harris Standard Flows
Harris Semiconductor offers a variety of standard product flows which cover the myriad
of application environments our customers experience. These flows run the gambet of
low cost commercial parts to fully qualified JAN microcircuits. All of these grades have one
thing in common. They result from meticulous attention to quality, starting with design
decisions made during product devel-opment and ending with the labeling of shipping containers for delivery to' our customers. The standard flows offered are:
Dash 5 -. Electrical performance guaranteed from OOC to +750C.
Dash 7 - Dash 5 plus 96 hours of burn-in to reduce infant
mortality risk in customer applications.
Dash 2 - Electrical performance guaranteed from -55 0 C to +125 0C.
Dash 8 - Electrical performance guaranteed from -55 0 0 to +1250C
plus 160 hours of burn-in with PDA of 5%. 100% preseal
visual per Mil Std 883C Method 2010.
JAN
Class B - Fully qualified and certified microcircuit manufactured per
Mil M 38510 requirements.
Details of the individual process requirements are contained in the flow charts which follow.

Harris Semiconductor Standard Processing Flows
IN-HOUS~.

BB

INCOMING
MATERIAL
AND
CHEMICAL
INSPECTION

ANALYTICAL
CAPABILITY

JAN CLASS B

AS
APPLICABLE

AS
APPLICABLE

AS
APPLICABLE

AS
APPLICABLE

AS
APPLICABLE

REQUIRED
CONTROLS
PER
MIL-M-38510
CLASS B
AS
APPLICABLE

ALL CRITICAL MATERIALS
RECEIVE LOT ACCEPTANCE
BY HARRIS IQC. INCLUDES:
•
•
•
•
•
•
•
•

SOLBENTS/ACIDS
RESISTS
SILICON
TARGETS/SOURCES
GASES
WIRE/PERFORMS
PACKAGES
PKG. MATERIALS

BETA SCOPE
SIMS
SEM
ION IMPLANT

FILM THICKNESS
THIN FILM
TECHNOLOGY
SPUTTERED
ALUMINUM

WAFER
FABRICATION
ALL CRITICAL PROCESS
ARE MONITORED BY
STATISTICAL PROCESS
CONTROL CHARTS.
CONTROL AND CAPABILITY
ISSUES ARE RESOLVED IN
LINE TO MINIMIZE AMOUNT
OF PRODUCT NOT CONFORMING TO SPECIFICATIONS

PROJECTION
ALIGNMENT
CV PLOT
PHOTO RESIST
TOLERANCES
IMPLANT
PROFILES
COMPOSITIONS
IN-PROCESS
PROBES FOR ACTICE
AND PASSIVE DEVICE
PARAMETERS
(1) TA = -55 0 C to +125 0 C for all grades except
DASH-7 (DASH-7 T A = OOC to +75 0 C)

9-3

Harris Semiconductor Standard Processing Flows
(continued)
/
-{j

. LASER
TRIMMING
AT BOTH
PACKAGE AND
WAFER LEV.ELS

PROBE/DICE
PREPARATION

/-2

II

-7/-8

II

JAN Class B

VISUAL
INSPECTION
WITHQC
MONITOR

VISUAL
INSPECTION
WITHQC
MONITOR

VISUAL
INSPECTION
PER
MIL-STD-883.
METHOD 2010.
CONDITION B,
WITHQC·
MONITOR

HIGH/ROOM
TEMP
PROBE TEST

ASS EM BlY 111

DIE ATIACH
CONTROL
WIRE BOND
CONTROL
PRE-SEAL
WASH IN
LAMINAR
FLOW
PRE-SEAL
VISUAL
INSP.ECTION
IN CLASS 100
LAMINAR
FLOW

Lead Frame Clean

YES

YES

YES

Die and Frame Attach
Control

YES

YES

YES

Wire Bond

YES

YES

YES

4-HOUR

4-HOUR

4-HOUR

AS REQUIRED

AS REQUIRED

YES

YES

YES

PER
MIL-STD-883
METHOD 2010,
CONDITIONB

YES

YES

YES

NO

NO

YES

YES.

YES

YES

YES

YES

YES

YES

QA Wire Bond
Control

Pre-Seal Clean
Pre-Seallnspect

Cerdip Sealing .
QA Seal Control
Stabilization Bake

NO

Temperature Cvcle

YES

AS
APPLICABLE
YES

Centrifuge

YES

YES

YES

Tin-Plating

YES

YES

YES

YES

YES

YES
YES

AS
APPLICABLE

QA Tin-Plating
Inspect

PARTICLE
IMPACT NOISE
DETECTION
(PINO)
AS
REQUIRED

YES

Gross Leak Test

YES

PIN.D Test 100%

AS
APPLICABLE

AS
APPLICABLE
AS
APPLICABLE
AS·
APPLICABLE

Frame Removal

YES

YES

YES

Load Shipping Tubes

YES

YES

YES

QA Final Inspect

YES

YES

YES

QA Documentation
Inspect

NO

NO

YES

Fine Leak Test

YES

111 Example for a Cerdip
package part.

9-4

~

YES

Harris Semiconductor Standard Processing Flows
(continued)

-5/-2

TEST

II

-7/-8

II

JAN Class B

(2)

@ = Operation
@ = QA Monitor

AC/OC SINGLE
INSERTION TEST
CAPABILITY;
HIGH/LOW TEMP

YES

YES

YES

YES

YES

NO

NO

NO

Group A and
C Samples Only

Pre Burn-I n Electrical
Test

NO

YES

YES

Burn-In

NO

DASH-8:
160HR@
+125OC
DASH 7:
96HR@
+125 0 C

160HR@
+125OC,OR
PER
SLASH SHEET

Post Burn-In Test

NO

YES

YES

Apply Burn-In PDA
(as applicable)

NO

Brand

YES

Electrical Test Sorting
Operation
QAMonitor

BURN-IN

QUAUTY
CONFORMANCE
GROUPS A, B, C,
AND 0 AS
REQUIRED

DELTAS PER
SLASH SHEET
REQUIREMENT
IF APPUCABLE
IN-HOUSE
PACKAGE
MOISTURE
MONITOR
CAPABIUTY

External Visual
Quality
Conformance

COMPUTERIZED
LOT
TRACEABILITY
MONITORING
SYSTEM

YES

PER SLASH
SHEET

YES

Final Data Review

or Stock
-5/ -7 ooC to +750 C
-2/-8/ JAN -550 C to +1250 C

9-5

o!l~

>--

YES

YES

YES

1-=
-'-'

/ Advantages of Standard Flows
Wherever feasible, and in accordance with good value engineering practice, the IC user should
specify device grades based on one of the five standard Harris manufacturing flows. These
are more than adequate for the overwhelming majority of applications and may be utilized
quite effectively if the user engineer bases his designs on the standard data book or slash
sheet (as applicable) electrical limits.
Some of the more important advantages gained by using standard as opposed to custom
flows are as follows:
• Lower cost than the same or an equivalent flow executed on a custom basis. This results from the higher efficiency achieved with a constant product flow and the elimination of such extra cost items as special fixturing, test programs, additional handling,
and added documentation.
• Faster delivery. The manufacturer often can supply many items from inventory and,
in any case, can establish and maintain a better product flow when there is no need to
restructure process and/or test procedures.
• Increased confidence in the devices. A continuing flow of a given product permits
the manufacturer to monitor trends which may bear on end-product performance or
reliability and to implement corrective action, if necessary.
• Reduction of risk. Since each product is processed independent of specific customer
orders, the manufacturer absorbs production variability within its scheduling framework without major impact on deliveries. In a custom flow, a lot failure late in the
production cycle can result in significant delays in delivery due to the required recycling time.

Despite the advantages of using standard flows, there are cases where a special or. custom
flow is mandatory to meet design or other requirements. In such cases, the Harris Marketing
groups stand ready to discuss individual customer needs and, where indicated, to accomodate
appropriate custom flows.

Quality Beginning to End
There are several significant elements which comprise Harris Semiconductor's approach to
quality that don't show on a process flow chart. Some of these are as follows:

INITIAL CIRCUIT SELECTION AND DESIGN
Once operational characteristics and parameter limits have been defined there are many
different circuit configurations capable of conforming to them. Harris designers are tasked
to choose those which are capable of meeting the required performance specifications with
maximum reliability.
Powerful computer aided design (CAD) techniques are applied in developing the original
concepts and detailed schematics, with computer modeled circuit simulation used to corroborate projected product performance. Monte Carlo methods, and other simulation techniques are also used, as appropriate to achieve specific objectives.
Regardless of the circuit approllch selected, high reliability, top performance, and maximum
potential yield to the required specifications are the governing criteria.

9-6

Individual active device types and component values are selected to provide optimum circuit
performance and to minimize sensitivity to parametric changes which may occur with aging
or as a result of environmental conditions.
Since most Harris products are sold into military, industrial and commercial end use applications most circuits are designed to meet military temperature range requirements at the outset. This results in more capable products introduced to all segments of the marketplace.

Die Layout and Geometry
Conformance with good layout practice is a must, for consistently reliable devices cannot
be assembled from poorly designed chips. Therefore, the IC layout phase at Harris is controlled by ground rules which establish the "do's" and "don'ts" for each manufacturing process. These rules define dimensions and toleranced to insure product immunity to process
variations, while maximizing product reliability under worst-case stress conditions. Computerized ground rule software packages are used by the chip designers to assure dimensional
adherence of diffusion windows as well as interconnect width and spacing. Automatic
checkout procedures confirm that the product conforms to the established ground rules.

POlYCAVSTALLINE SUBSTRATE

Dielectric isolation eliminates latch-up
by placing a silicon-dioxide isolation
barrier between devices. This separates
all active elements, eliminating interface
junctions that cause parasitic SCRs.

Cross-sectional view of high-frequency
PNP device formation in the D I process.

Raw Material Inspection and QC
Acknowledging that Hi-Rei, high performance devices can be manufactured only by using
top quality materials, Harris subjects incoming materials, piece parts and supplies to documented tests and inspections. The techniques used are selected for optimum evaluation of
the materials checked. to ensure full compliance with Harris internal specifications. Close
coordina~ion with the suppliers is maintained to assure a reliable supply of quality materials.

9-7

Wafer Die Production Process and Controls
Harris has a wide range of state-of-the-art wafer and die processing capabilities, permitting
the circuit designer to choose the optimum production technique for each type of device.
Depending on specific design and performance specifications, devices, may be fabricated
using either conventional or complementary bipolar, CMOS, combined bipolar and CMOS,
NMOS or PMOS construction. Two complementary vertical bipolar processes are available,
offering frequency responses two orders of magnitude higher than conventional fabrication
techniques.
Regardless of the process involved, statistical process control charts are employed to maximize the visibility of wafer lot variability during production. These charts take the form of
X/R charts for variables data and e/p charts for attributes data. Typical process control
points include diffusion, thin film, photo resist steps as well as inspection points or electrical
device measurements. The goal of the control charts is three fold:

• Isolate and eliminate special causes of variability to preclude the production
of wafers with a process which is not operating correctly.
• Define the natural limits of variability in a process to determine its capability in light
of engineering expectation.
• Provide a reference baseline for process enhancements or changes to improve capability or reduce cost.
With high reliability an integral part of its manufacturing philosphy, Harris Semiconductor
does not have separate production lines for standard and JAN devices. Rather, all Harris
devices of a given type are manufactured on the same line. Product grades are selected
by the application of screening tests and inspection from the same generic process flows in
wafer fab.

Die/Package Assembly and Controls
Each major process operation (mount, bond, seal, trim) is carefully monitored by in-process
quality control steps. In addition, many mechanical and environmental tests areimplemented during the die/package assembly stage. The specific controls and tests utilized at each
step are in strict compliance with the applicable standards for the device reliabitity class
designation.

Burn-In
100% burn-in is a screening procedure used when applicable to detect devices subject to
infant mortality failure modes. Biases are applied to simulate worst-case operational
conditions, permitting the identification and elimination of marginal units.
The applied voltage levels, operational state, temperature and test period vary with the type
of device and reliability class, as governed by the applicable standards. Electrical test of
the device is performed both prior to and after the burn-in period.

9-8

Electrical Screening and Test Procedures
While many factors are critical in the production of I. C. devices, the electrical screening
and test procedures, are critical to matching product performance to customer need. All
products receive 100% electrical test per the data sheet requirements for each product type.
In addition product lots received a battery of QA inspections and tests to assure compliance
with Harris production standards.

Reliability Assessment and Enhancement
At Harris, realibility assurance is a dynamic program with the primary and ultimate goal
of securing full product performance throughout its usage life. Each manufacturing phase
from original design to final packaging is subject to continuous review, analysis, and evaluation, with modifications introduced as needed to improve product performance and reliability. There are three important sources of reliability data:
1.
2.
3.

Initial qualification
Add on life
Field failure history

New Products/Processes/Packages
Two requirements are imposed on the product development phase of new circuits and processes. First is the use of proper process methodology, design techniques, and layout
practices. New designs are reviewed throughout the course of their development for conformance to the constraints defined by process ground rules. These rules document the
results of years of experimentation and experience and reflect a relatively conservative
approach to process capability and technology. Second is demonstration of reliability pefformance of a new product or process through a series of stress tests designed to accelerate
typical failure mechanisms in integrated circuits. Qualification requirements are illustrated
in Table I for a variety of product/process/package maturity conditions. These tests are
executed by the Harris Reliability organization for each new product/package/process
before circuits are committed to the marketplace. Failure rate predictions are made based
on test results. More importantly, failure analysis results are fed back into design and
process engineering organizations to generate corrective action (if applicable) and enhance
product performance. Each new product entry must meet minimum failure rate standards
to qualify for sale to customers.

"Add On"

o!l~

An important source of reliability information is performance of established products
through extended life testing under worst-case operating conditions. Failure rate predictions for specific products or product types are available on request via Harris Semiconductor Reliability bulletins;
Accelerated life test are utilized to estimate the expected field failure rate of our products.
Life tests are conducted periodically on regular production samples. Sample sizes are
typically 200 units which are operated at 1250C at nominal supply voltages and with
forcing and loading conditions simulating typical application environments. Where possible,
operating conditions are structured to provide maximum thermal and electrical acceleration
of the natural failure mechanisms found in I. C. devices.
All rejected devices are carefully analyzed and. activation energies are assigned based on the
observed failure mechanisms. There rates are then computed based on thermal derating
factors per the Arrhenius equation. The results are reported in the Harris Reliability bulletins based on derating to +550C operations and nominal supply conditions. Failure
rates are reported at the 60% confidence level and the 95% confidence level.
Finally, life tests are monitored at mid-point intervals to assure that failure rates are decreasing and that no wearout mechanisms are at work.
9-9

>-~=
-a>

-'--~=
co

-'-'

OW
ex:

9-11

Harris and the JAN Program
Harris Semiconductor became an active participant in the JAN program as the first microcircuit manufacturer to JAN-qualify a PROM, receiving a QPL-2 qualification in 1972
and the higher level QPL-1 qualification in 1974 for the military version of the HPROM0512, as defined by MIL-M-38510, Slash Sheet 201. Since this initial effort, Harris has
received JAN line certification for production lines supplying dielectrically isolated (DI)
operational amplifiers, analog switches, analog multiplexers,and junction isolated op amps.

Harris will continue to pursue further line certification and part qualification efforts, offering users an ever-expanding line for JAN-qualified devices.

JAN-Qualified Devices
MIL-M-385101

OPL-1

HA2-2600

High Performance
Operational Amplifier

12202BGC

Now
Qualified

HA2-2620

Very Wide Band,
Uncompensated Op Amp

12203BGC

Now
Qualified

HA2-2600

Precision
High ~Iew Rate Op Amp

12204BGC

Now
Qualified

HA2-2510

High Slew Rate Op Amp

12205BGC

Now
Qualified

HA2-Z520

High Slew Rate
Uncompensated Op Amp

12206BGC

Now
Qualified

HA1-4741

Quad Operational Amp

11003BC"iI

Now
O"alified

HI-201

QuadSPST
CMOS Analog Switch

12302BEB

Now
Qualified

TYPE

FUNCTION

9-12

Burn-In Circuit Index
DRAWING
NUMBER
HA-OP07
HA-OP27
HA-OP37
HA-2400/04/05
HA-2406
HA-2420/25
HA-2420 (LCC)
HA-2500/02/05
HA-2510/12/15
HA-2520/22/25
HA-2539
HA-2540
HA-2541
HA-2542
HA-2544
HA-2600/02/05
HA-2620/22/25
HA-2630/35
HA-2640/45
HA-2650/55
HA-2720/25
HA-4600/02/05
HA-4741
HA-4900/02/05
HA-5002
HA-5033
HA-5101
HA-5102
HA-5104
HA-5111
HA-5112
HA-5114
HA-5130/35
HA-5134
HA-5141
HA-5142
HA-5144
HA-5147
HA-5151
HA-5152
HA-5154
HA-5160/62
HA-5170
HA-5180
HA-5190/95
HA-5320
HA-5330
HC-5502A
HC-5504
HC-5508
HC-5510
HC-5511
HC-5512/5512A
HC-5512C
HC-5512D
HC-5554
HC-5557
HC-55564
HF-10
HI-200
. HI-200 (LCC)

Precision Operational Amplifier .............................................................................................
Ultra-Low Noise, Precision Operational Amplifier. ..............................................................
Ultra-Low Noise, Precision, High-Speed Operational Amplifier ....................................... .
PRAM, Four Channel Operational Amplifiers ......................................................................
Digitally Selected 4 Channel Operational Amplifier .......................................................... ..
Fast Sample and Hold Operational Amplifiers .....................................................................
Fast Sample and Hold Operational Amplifiers ................................................................... ..
Precision High Slew Rate Operational Amplifiers ...............................................................
High Slew Rate Operational Amplifiers .............................................................................. ..
Uncompensated High Slew Rate Operational Amplifiers ...................................................
Very High Slew Rate Wideband Operational Amplifiers ................................................... ..
Wideband, Fast Settling Operational Amplifiers ................................................................ ..
Wideband, Fast Settling, Unity Gain Stable Operational Amplifiers ............................... ..
Wideband, High Slew Rate, High Output Current Operational Amplifiers ..................... ..
Video Operational Amplifiers .................................................................................................
Wideband, High Impedance Operational Amplifiers ...........................................................
Very Wideband, Uncompensated Operational Amplifiers ................................................. ..
High Performance Current Booster .......................................................................................
High Voltage Operational Amplifiers.: ................................................................................. ..
Dual High Performance Operational Amplifiers ................................................................. .
Wide Range Programmable Operational Amplifiers .......................................................... ..
High Performance Quad Operational Amplifiers ............................................................... ..
Quad Operational Amplifier ...................................................................................................
Precision Quad Comparators ............. ,.................................................................................. .
Monolithic, Wideband, High Slew Rate, High Output Current Buffer ............................. ..
Video Buffer .............................................................................................................................
Low Noise, High Performance Operational Amplifier ......... ; ............................................. ..
Low Noise, High Performance Operational Amplifiers .......................................................
Low Noise, High Performance Operational Amplifers ...................................................... ..
Low Noise, High Performance Operational Amplifiers .......................................................
Low Noise, High Performance Operational Amplifiers .......................................................
Low Noise, High Performance Operational Amplifiers .......................................................
Precision Operational Amplifiers ...........................................................................................
Precision Quad Operational Amplifiers .............................................................................. ..
Ultra-Low Power Operational Amplifier ................................................................................
Ultra-Low Power Operational Amplifier .............................................................................. ..
Ultra-Low Power Operational Amplifier ............................................................................... .
Ultra-Low Noise, Precision High Slew Rate, Wideband Operational Amplifier .............. .
Low Power Operational Amplifier ..........................................................................................
Low Power Operational Amplifier ........................................................................................ ..
Low Power Operational Amplifier ..........................................................................................
Wideband, JFET Input, High Slew Rate, Uncompensated Operational Amplifier .......... .
Precision JFET Input Operational Amplifier ...................................................................... ..
Low Bias Current, Low Power JFET Input Operational Amplifier .................................... .
Wideband, Fast Settling Operational Amplifiers ................................................................ ..
High Speed Precision Monolithic Sample and Hold Amplifier ......................................... .
Very High Speed Precision Monolithic Sample and Hold Amplifier ............................... ..
Subscriber Line Interface Circuit (SLlC) ..............................................................................
Subscriber Line Interface Circuit (SLlC) ............................................................................ ..
Subscriber Line Interface Circuit (SLlC) ..............................................................................
PCM CODEC ............................................................................................................................
PCM CODEC ............................................................................................................................
PCM Monolithic Filter .............................................................................................................
PCM or CVSD Monolithic Filter .............................................................................................
PCM or CVSD Monolithic Filter .............................................................................................
Monolithic CMOS Serial Interlace COFIDEC Family ..........................................................
Monolithic CMOS Serial Interface COFIDEC Family ............... :........................................ ..
All-Digital Continuously Variable Slope Delta Modulator (CVSD) .................................. ..
Universal Active Filter .............................................................................................................
Dual SPST CMOS Analog Switch .........................................................................................
Dual SPST CMOS Analog Switch .........................................................................................

4
5
5
1
2
3
4
4
4
5
5
5
5
4
4
4
6
7
8
10
11
11
12
13
6
4
8, 9
11
5
9
14
4
11
4
8, 9
11
5
4
8, 9
11
4
4
4
5
15
16
17
18
19
20
21
22
22
22
23
23
24
25
26
27

olI~

.. =

>--IX>

-'-.....-o -15V
02

A2
OUT 2
IN2

GNO

VREF

INO

IN.

OUT 4

A4

+15V

+v

OUT3

C2

••

A.

NOTES:
R1, R2, R3, R4 = 10kn, 5%,
C1, C2 = .011lF
01, 02 = IN4002

NOTES:
C1= C2 = 0.01 f..l F
R = 10Kn ±5%,
01 = 02 = IN4002

02

c!l~

>--

1-=
-'«
-

HI-303; HI-304; HI-305; HI-306; HI-307

HI-300; HI.;;301; HI-302

CQ

«-

::::>-'

OW

a:

+V
.1

.2

S3

M

03

'I'

.,

.q.l

___

-o+15V

O~

S2

1N1

'~2

GNt;)

-v

NOTES:
R1, R2, R3, R4 = 10kn, 5%,
C1,C2 = .01!lF
01,02 = IN4002

rI==~:kL

+15V

1----1--....-0-0 -15V

NOTES:
R1 to R4 = 10Kn
C1=0.01f..l F
01 = IN4002

9-19

HI-381; HI-387

HI.!.a84; HI-390

.,
SllNC

"'

NC/S2

clINe

Ne/D2

NC/D1

D2/Ne

NCISI

o.

.3

".
".

IN2

+16V

-V

+V

-16V

Dl

I--

81
INI

S2/NC

IN 1

Dl

GND

C2

D3

'--

S3

e-

S4

.~

-V

OND ~

Dl ~

h

D.

D4

+V

~el

+i

10V

+lSV

IN' ~
S2~

D2

-:-

NOTES:

NOTES:

Rl - R4 = 10kn, ±5%,
Cl -C2= .01j./F
Dl - D2 = IN4002

Rl - R4 = 10kn, ±5%,
Cl - C2 = .01j./F
Dl - D2 = IN4002

HI-S06/S07; HI-506A/S07A; HI-S46/S47

HI-S040Through HI-SOSl

"'

".
"~

O.

Dl

+V
NC/OUTS

.,
AI

'-_+~

•

_____

--<:)+5V

-=-

5

1..!!.....--H~....--o-I6V

NC
IN 16/88

C2

IN 15/78
IN 14/68

00

-V

S3

VR

S4

VL

I.

IN 10/28

IN lIlA

,.

D4

+V

11

IN9/1B

EN

18

A2

12

OND

17

VREF

NJ
AI

A3/Ne

A2

IN 13/58

D2

S2

8

•

+5V

o-....--+-~f-!i4

"

NOTES:

NOTES:

Rl-R4=10kH,5%,
Cl , C2, C3 = .01 j./ F
Dl, D2, D3 = IN4002

Rl,R2=10Kn
Cl,C2,C3 = .Olj./f
Dl, D2, D3 = IN4002

HI-S06/S07(LCC); HI-S06A/S07A (LCC)

IN 12/48

IN 11/38

1
1

e3

03

HI-S06LA/507LA

OUT/OUT A

c,

NC/OUTB

27

3

iii

IN 8/IN BA

4

IH7/IN7A

"

·•
·
,.•

IN 161INIB

,S IN/IN 78

IN 8/JN IA

"

INS/IN'S

7

NOTES:

Rl, R2 = 10KH
Cl, C2, C3 = .01 f.J. f
Dl, D2, D3 = IN4002

Rl = R2 = lKn
Cl =C2=0.1 f.J.F
Dl = D2 = IN4002

9-20

,.

.

"

23

IN 14/IN88

IN6JINSA

IN 13/IN58

IN4/lN4A

22

IN 12/1N4B

IN 31IN 3A

21

IN 11/IN3B

IN2IIN2A

20

IN 1011N 28

IN l/1N1A

"

EN

AD
13

NOTES:

2B

2

W.

....,

"

"

A,

II

A2

"

R2
~15V

02

C2

HI-50S/508A (Lee)

HI-50S/50SA; HI-54S
r---------------------------~~--~5V
C3

r---_.--~--------_.--_.---o5V
C3

16
-16V

15

-15V

o-.....--.--t----'';

"

Cl

01

+V J-"--t-...,.-...,.-_o+I&V

IN 1

C2

NC

.---1---1
8

IN3

IN6

7

IN4

IN 7

. -____++-'8'-1 OUT

IN 8

NC

2

INS

IN3

INB

IN

, ..

10

10K
10K

NOTES:

NOTES:

Rl ~ 10krl
Cl, C2, C3 ~ .01 Il f
01,02,03 = IN4002

Rl ~ 10krl
Cl, C2, C3 ~ .01 J.L f
01,02, 03 ~ IN4002

.-------------------------

HI-509/509~;

HI-50SLA/509LA

HI-539; HI-549

.-------------------------_--~--_

_oSV
C3

2

Ao

Al

17

3

EN

A2

16

-15Vo-.....-.._-_..:.'-j ·V

GND

15

02
6

IN1/1A

+v

IN 212A

INS/1S

7

IN 3I3A

IN6/2B

8

IN 4/4A

IN 7/38

r-V""''y-+-f-'9'-1

IN 814B

OUT

lAO

Al

EN

GNO

o-+-+-.....--=-j

-v

01

r'--.....-"t--t-Q+15V
11

•

IN 3A

7

IN 4A

r----'-I-+-~. OUTA

10

-=t-';.:5_ _ _ _ _-::L

+v

14

IN 1B

13

IN 28

12

IN 38

11

IN 4B

OUTB

+1liV

D2

C2

10

I'"'-t-+---,

"'
NOTES:

NOTES:

Rl
Cl
01

"2

~

Rl, R2 = 10krl
Cl ,C2, C3 ~ .01 Ilf
01,02, 03 ~ IN4002

lKn
C2 = 0.1 J.LF
~ 02 ~ IN4002

~

HI-509/509A (Lee); HI-549 (Lee)

5V

OUT A (-=_ _ _,

-v

C3

INBI8A

C2

IN7nA
IN6J8A

-15V

--.....-+--1

0-.....
01

+V~I~8~--",,~-,--~_+-o'6V

-v
IN1A

NC

NC

IN£A

OUT
A

Ne

17

IN28

15
,.

8

C2

11

OUT IN3B

IN2A

IN3A

IN5/SA
IN4I4A

IN 18

IN4B

14

22

IN 1214B

IN3/3A

21

IN 11/3B

IN2/2A

20

IN10/2B

IN lIlA

19

IN9/1B

r--'-I...,.+"-I

23

GNO
VOD/LLS
A3/SDS

EN 1-",..8+-+____..,

+-+--,

AO I"L7

Al 1-""'6~--1-..
A2 ~':.:;6~--1-..

+--.....--o5V
C3

R2

NOTES:
Rl,R2~10kn

Ct, C2, C3 ~ .01 J.Lf
01,02, 03 ~ IN4002

Rl

NOTES:

'Rl, R2 = 10krl
!01, 02, 03 ~ IN4002
C1, C2, C3 ~ .01 J.I r-

9-21

HI-516 (Lee)

HI-518

+15V

QUIA

18

-v

17

Cl

,

"

IN4/4A

16

B lNI4J6B

INBi6A 24

IN3/3A

15

,

lN5I&A Z3

IN7nA

IN 15/78

IN 13f5B

,.

IN1/1A

13

EN

12

AD

11

Al

10

C2

IN ..,,,,, 22

8 IN i2/46

9 IN

IN2/2A

-15V
R2

,,/38

IH3f3A 21

10 IN 10128

IN2/2A 20

11 lN9{1B

INlnA 19

9

A2/SDS

5V

NOTES:
Rl,R2=10k12
Cl, C2, C3 = .01 !J. F
01,02,03 = IN4002

NOTES:
Rl, R2 = 10kS1
Cl, C2, C3 = .01 !J.F
01,02,03= IN4002

HI-524

HI-562A

18

FB(lN)

OUT

0--...----.--''-1 ~:~S/TTl

-v

SIG GND

IN'

o--.......--~--t--'-I

IN 1

12

PWR GND

EN

11

Al

AD

10

7

IN3

8

22

•

21

to

20

VAH (HI IN)

19

-lSV o--~-~-t--t--:i VpsBIPOLAR AtN

"

IN 2

13

SIG GND

24

3

VREF (LO IN)

SIG OND

SIG GNO

6

(MSB) BIT 1

lOGIC SEL.
16

FB(OUT!

•

R2

8

7

18

BIPOLAR ROUT

8

17

tDAC OUT

9

16

10

10V SPAN R

10 15

11

20VSPANR

'1

r-____~~12,

~D

14

(LSS) BIT 12

t-':.::3_-4-o fO

C3

NOTES:
Rl, R2 = 10kS1
Cl,C2,C3=.OI !J.F
01,02,03 = IN4002

HI-562A (Lee)

NOTES:
Cl -C3 = .01 !J.F
01 - 03 = IN4002
10 = 100 KHz, 50% Duty Cycle

HI-565A

fo

"

BIT 1
IMSB)

fl

23

f,/2

t,/4

(MSB) BIT 1

BIT4

+1SV

Cl

Dl

-=-lSV
BIPOLAR R IN

D3

C3

3

Vps+

22

•

REF. OUT

21

f,/8

5

ANALOG OND

•

20

f1/16

1.

f1/32

7

18

f,/64

6

REF. IN

7

Vps-

8

BIPOLAR

-=-

BIT9

NOTES: .
Cl -C3 = .01!J.I
01 - D3 = IN4002
h = 100 KHz

9-22

17

11

,.
,.
,.

(lSB) BIT 12

13

OFFSET IN

9

NOTES:
Cl -C3 = .01 !J.F
01 - 03 = IN4002
10 = 100 KHz, 50% Duty Cycle·

2.

NC

BIT 2

DAC OUT

10

lOV'SPAN Rl

11

20V SPAN A

12

P.S. GND

10

of,/128
f1/256

f,/512
f,/1024
f1/2048

HI-1818A

HI-574A/674A
'5V
2

DATA MODE

3

CHIP SELECT

STATUS

28

0812

27

DB11

26

CS

,

BYTE ADD/SHORT

5

READ/CONVERT RIC

6

CHIP ENABLE CE

OB10

CYCLE AO
fO

25

'5V

24

3

7

+15V

D67

22

•

+10V REF OUT

DBS

21

REF IN

D.'

.
.
5

"

D.3

"

18

12

BIPOLAR OFF

D.2

"

13

lOV SPAN

D.,

16

NC 14

20VSPAN

OJ
VfN

R2

D2

..

R8

cV

15

'v

"

fN 1

13

fN'

DUT

12

fN7

fN2

11

fN3

"

+15V

D3

fN5

DIGITAL OND 1-"15'----_-;

NOTES:
R1 - R13 = 10KSl
C1-C3=0.1 J..IF
D1 - D3 = IN4002
VIN = Triangle Wave Form, +5V to -5V. 1 KHz
to = 10 KHZ,90% Duty Cycle, OV to 5V

NOTES:
C1,C2,C3 = .01f..1F
D1, D2, D3 = IN4002

HI-5610

HI-1828A

~vo-.--~~~-~

-15V

+'5

02

Cl
VCC

-v

15

EN

W

14

1 VPS+

0,

2 lLS
3 VREF LO

+15\1

• Ne

03
fN 1

OUTB

5 VREF HI

+'0

13

6

-'5
12

fN'

OUT A

fN 7

fN2

11

fN'

fN3

10

vps-

7 BIPOLAR
R IN

a
9

BIPOLAR

rD~~TOUT

10 SPAN R
11 SPAN R

12 GND
fN4

fN 5

BIT 24

(MSB~ 23

3 22
.2'
5 20
6 ,.
7 '8
8 17

• '6
BIT 10 15

(L~B~

14

COMPo '3
CAP.

R,

NOTES:
R1 = 50kSl
D2, D3, D1 = IN4002
C2, C3, C1 = 0.01 f..I F
to = 1 KHz, 50% Duty Cycle

NOTES:
R1, R2 = 20kSl
C1, C2, C3 = .01 f..I F
D1, D2, D3 = I N4002

to

10

""~
>--

1-=
-'«
-co

H 1-5660/5660A

HI-5618A/5618B

«-

::>-'

OW
a::

+v,.

0'
3

+10V'o--1>--...---------.-o+15V

BIT 12

BIT2

BIT 11

•

BIT3

BIT 10

13

7

SIT4

BIT9

12

•

BIT5

BIT8

11

9

SIT6

81T7

+10V

,.

BIT 1 (MSB)

5

R,

15

10/4

C3

IOUTt

f1/16

" 5
" 6

HI-7541 (LCC)

GNO

+15V

C,

+5V

HI-7541

11/4

fO/128

17

NOTES:
Cl -C3 = 0.01 J.lF
01 - 03 = IN4002
10 = 100KHz (TTL Logic Levels)

11/2

{MSB~

+15V

,.
,.

SCALING

BIT 1

+15V

.,

01

10

11/512

BIT 1 {MSBI

f1/2

81T2

BIT 11

'1/4

BIT 3

BIT 10

11/256

.

17

,

15

'112048

'1/1024

'1/512

11/128
"/8

11/64

BIT 9

BIT4
BIT 6

NOTES:
Cl, C2 = .01 J.lI, 01, 02 = IN4002
11 = 100kHz
Square Wave, TTL Level (0-5V)

BIT 12 {LSBI

NOTES:
Cl, C2 = .01 J.lI
'1/,. '1/32
01,02 = IN4002
11 = 100kHz
Square Wave, TTL Level (0-5V)

9-24

81T7

BIT 8

'1/64

"/128

I.

'11256

HV-l000

I

I

HY-9574

ACHI

AC LO
(GND)

(220 VRMS MAX)

AC HI

NC

1-"6"---t........"..' .....

,.

,w

NC 14

EXT POT

OVERRIDE

PHASE SENSE

'3

'2
11 R2

NC

EXT POT

~_ _ _-'l7 MODE SELECT

L _ _ _.!!j8 TRIAC RET

NOTES:
R1 ~5KD ,1W,5%
R2 ~ 100KD, V,W, 5%
R3 = 500KD, V,W, 5%

C1
D1

NC 10

TRIAC GATE

1-'9,-~,,",,3f'---'

= 0.47/lF
= 12V Zener, %W

NOTES:
R1 through R6~ 10KD ±'10%%Watt
R7 through R19 ~ 5KD ±.10% % Watt
CR1 = IN 4001 or Equivalent

HY-9590; HY-9591; HY-9595; HY-9596

NOTES:
R = 4.7K ±. 10%
C~ 0.1pF,50V

9-25

"It

Application Note Index

10-2

Application Note Abstracts

10-8

Application Notes

10-11

ABSOLUTE MAXIMUM RATINGS
As with all semiconduc,tors, stresses listed under ';Absolute Maximum Ratings"
may be applied to devices (one at a time) without res'ulting in permanent damage.
This is a stress rating only. Exposure to absolute maximum ra'ting conditions for
extended periods may affect device reliability. The conditions listed under
"Electrical Characteristics" are the only conditions recommended for
satisfactory operation.

10-1

Application Note Index
APPLICATION

A. N. NUMBER(S)

PAGE

Absolute Accuracy ................................ ,..................................................522 .............. ;.. ,.................................... 10-53
Active Filter ................................................................................................514 ............. ~ ................ :....................... 10-14
ADC Accuracy (Linearity. Gain & Offset Error) ...................................520. 530 ..................... .'.............. ,......... 10-37, 71
ADC Microprocessor Interface ............. :: .............. ;.................................529, 545 .................... ,......................... 10-69, 135
ADC Servo Type ............. :.........................................................................524 ...................................................... 10-56
.ADC Successive Approximation .......... ~ ................. :................................524 ........................... ,.......................... 10-56
ADC Tracking., ..........................................................................................524 ....................................................;.10-56
Adder-Subtractor ....................................... :...............................................514 ...................................................... 10-14
Adding Multiplexer Channels .................................................................520 ....................................................... 10-37
AGC Amplifier ..........................................................................................526 ...................................................... 10-63
AGC with Squelch Control .....................................................................544 ...................................................... 10-129
Aliasing ......................................................................................................538 ...................................................... 10-93
Alternate Plain Text (APT) ......................................................................607 ...................................................... 10-226
Alternatives to CMOS Switches and Multiplexers ................................520 ...................................................... 10-37
AMI Code ..................................................................................................573 ...................................................... 10-215
Analog Multiplexer ...................................................................................514.545 .............................................. 10-14. 135
Analog to Digital Converters ..................................................................524, 530. 531, 560 ............................. 10-56. 71. 74. 206
Analog Switches .......................................................................................520.521.531,532, ............................ 10-37. 46. 74, 78
534,543 .............................................. 10-82. 122
Attenuator ..............................................................................;.................. 514 ............. ,........................................ 10-14
Audio Circuits/Drivers .............................................................................548, 552. 554 ...................................... 10-142, 179.192
Auto Zero Amplifiers ................................................................................531 ...................................................... 10-74
Auto Zero Circuit .....................................................................................538 ...................................................... 10-93
Automatic Gain Control (AGC) ..............................................................607 ...................................................... 10-226
Automatic Offset Correction (DAS) .......................................................530 ...................................................... 10-71
Balance Network ......................................................................................549 ...................................................... 10-154
Balanced Modulator .................................................................................514 ...................................................... 10-14
Bandpass Filter .................. ,......................................................................554 ...................................................... 10-192
Bar Code Scanner ....................................................................................544 ...................................................... 10-129
Basic CMOS Switch .................................................................................521 ...................................................... 10-46
Battery Feed ..............................................................................................549 ...................................................... 10-154
Battery Ground (BG) ...............................................................................549 ...................................................... 10-154
Bias Current Test (Op Amps) .................................................................508 ...................................................... 10-11
Bias Current Reduction in High Speed Op Amps ................................525 ...................................................... 10-59
BORSHT .................................................................................,.................. 549 ...................................................... 10-154
Broadband Noise in Op Amps ...............................: ................................519 ...................................................... 10-30
B825/B625 (Bipolar Code Substitutions) ..............................................573 ...................................................... 10-215
Capacitive Feedback (Op Amps) ............................................................515 ...................................................... 10-21
Care and Feeding of Switches ................................................................520 ...................................................... 10-37
Cascading High Speed Amplifiers .........................................................541 ...................................................... 10-109
Central Office (C.O.) ................................................................................ 549 ...................................................... 1p-154
Charge Injection in Switches ..................................................................534 ...................................................... 10-82
Charge Pool Power Supply .....................................................................544 ...................................................... 10-129
CMOS Analog Switches ..........................................................................520, 521, 531, 532, ............................ 10-37. 46, 74, 78
534.543 .............................................. 10-82, 122
CMOS Versus Bipolar Switches Devices ...............................................521 ...................................................... 10-46
Coaxial Cable Driver ................................................................................525. 548. 552 ...................................... 10-59, 142. 179
CODEC (Timing) ......................................... ,............................................570 ...................................................... 10-210
Common Mode Rejection Ratio Test (Op Amps) ................................. 508 ...................................................... 10-11
Comparator ...............................................................................................509, 514 .............................................. 10-13. 14
Compensation to Input CapaCitance (Op Amp) ...................................515 ...................................................... 10-21
Complex Load ..........................................................................................549 ...................................................... 10-154
Compliance ...............................................................................................522 ...................................................... 10-53
CompOSite Amplifier ................................................................................539, 541. 550, 552 ............................. 10-100, 109. 173, 179
Com puter Interface ..................................................................................535 ...................................................... 10-87
Constant Current Source/Sink Circuit ............... ;..................................540 ...................................................... 10-105
Continuity Check (OpAmps) .................... ~ ............................................508 .............·......................................... 10-11
Continuously Variable Slope Delta Modulator (CVSD) ....................... 607 ...................................................... 10-226
. Crystal Osciliator......................................................................................548 ...................................................... 10-142
Current Loop Transmitter .......................................................................544 ...................................................... 10-129

10-2

Application Note Index (Continued)
APPLICATION

A. N. NUMBER(S)

PAGE

Crystal Oscillator. .....................................................................................548 ......................................................
Current Loop Transmitter .......................................................................544 ......................................................
Current to Voltage Converter .................................................................525. 553 ..............................................
Current Sense Amplifier ..........................................................................540 ......................................................
Current Sink Circuit .................................................................................540 ......................................................
Current Source Circuit ............................................................................540 ......................................................

10-142
10-129
10-59, 184
10-105
10-105
10-105

DAC 16 ......................................................................................................539 ......................................................
DAC De-Glitcher ......................................................................................517 ......................................................
DAC Gain Drift .........................................................................................522 ......................................................
DAC Offset Drift (Unipolar or Bipolar) ..................................................522 ......................................................
DAC Output Current to Voltage Converter ...........................................525, 539 ..............................................
DAC Settling Time ...................................................................................522 ......................................................
DAC Transfer Function ...........................................................................522 ......................................................
DACs ..........................................................................................................522, 524, 530, 539, ............................
Data Acquisition System .........................................................................524, 529, 530, 535 .............................
560 ......................................................
Data Acquisition System Configurations .............................................. 531 ......................................................
Data Bus Interface (HI-DAC-16) ............................................................539 ......................................................
DC Error Reduction in High Speed Op Amps ......................................541 ......................................................
DC Gain Controlled Video Amplifier ..................................................... 526 ......................................................
DC Motor Speed Control ........................................................................552 ......................................................
Definition of Multiplexer/Analog Switch Terms ................................... 520 ......................................................
Demultiplexing ..........................................................................................520 ......................................................
0.1. ..........................................................................................................521 ......................................................
Dielectric Isolation Advantages in Switches ......................................... 521 ......................................................
Differential Multiplexing ..........................................................................520 ......................................................
Differential Nonlinearity ..........................................................................522 ......................................................
Digital Interface (Multiplexers) ...............................................................520, 545 ..............................................
Digital Interface With Switches .............................................................. 520 ......................................................
Digital Offset Correction (DAD) ............................................................. 530 ......................................................
Droop Rate Error (S&H) ..........................................................................538 ......................................................

10-100
10-23
10-53
10-53
10-59, 100
10-53
10-53
10-53, 56, 71, 100
10-56, 68, 71,87
10-206
10-74
10-100
10-109
10-63
10-179
10-37
10-37
10-46
10-46
10-37
10-53
10-37, 135
10-37
10-71
10-93

Encode/Decode ........................................................................................607, 576 .............................................. 10-226, 224
Expanding the HY-9590/9591 ................................................................. 560 ...................................................... 10-206
Fast Settling Operational Amplifier ........................................................ 525, 526 ..............................................
Fault Loop Current Limiting ...................................................................549 ......................................................
Feed Resistors ..........................................................................................549 ......................................................
Feedthrough ..............................................................................................538 ......................................................
Filter ...........................................................................................................514 ......................................................
Filters (DAS) .............................................................................................535 ......................................................
Flash Converter Drivers ...........................................................................548, 552 ..............................................
Floating Body JI Technology .................................................................521 ......................................................
Force Zero (FZ) ........................................................................................607, 576 ..............................................
Four Wire Side (4W) ................................................................................549 ......................................................
Frequency Compensation .......................................................................525, 541 ..............................................

10-59, 63
10-154
10-154
10-93
10-14
10-87
10-142,179
10-46
10-226, 224
10-154
10-59, 109

Gain Controlled Video Amplifier ............................................................ 526 ...................................................... 10-63
Gated Op Amp Applications (Sample & Hold) HA-2420/2425 ............ 517 ...................................................... 10-23
Ground Current Cancellation .................................................................539 ...................................................... 10-100
Ground Key Detection (GKD) ................................................................ 549 ...................................................... 10-154
HA-2400/2404/2405 ..................................................................................514, 519 .............................................. 10-14, 30
HA-2420/2425 ...........................................................................................520, 524, 531, 538 ............................. 10-37,56,74,93
HA-2500/2502/2505 .................... '" ........................................................... 519 ...................................................... 10-30
HA-2510/2512/2515 ..................................................................................519 ...................................................... 10-30
HA-2520/2522/2525 ..................................................................................519 ...................................................... 10-30
HA-2539 .....................................................................................................541 ...................................................... 10-109

10-3

en

g:~

«0
z

Application Note Index (Continued)
A. N. NUMBER(S)

APPLICATION

PAGE

HA-2540 .....................................................................................................541 ...................................................... 10-109
HA-2541 .....................................................................................................550 ...................................................... 10-173
HA-2542 ............................................................................. :....................... 552 ...................................................... 10-179
HA-2600/2602/2605 ..................................................................................519 ...................................................... 10-30
HA-2620/2622/2625 ......................................................................:...........509, 519 .............................................. 10-13, 30
HA-2640/2645 ...........................................................................................519 ...................................................... 10-30
HA-2720/2725 ............................................................................................519 ...................................................... 10-30
HA-2730/2735 ...........................................................................................519 ...................................................... 10-30
HA-4600/4602/4605 ..................................................................................519 ...................................................... 10-30
HA-4i'41 .....................................................................................................519 ...................................................... 10-30
HA-5033 .....................................................................................................548 ....................................................... 10-142
HA-5102/5104/5112/5114 .........................................................................554 ...................................................... 10-192
HA-5130/5135 ...........................................................................................519 ...................................................... 10-30
HA-5141/5142/5144 ..................................................................................544 ...................................................... 10-129
HA-5170 .....................................................................................................540 ...................................................... 10-105
HA-5180 .....................................................................................................555 ...................................................... 10-199
HA-5190/5195 ...........................................................................................525, 526 .............................................. 10-59, 63
HA-5320 .....................................................................................................538 ...................................................... 10-93
HDB3 .........................................................................................................573 ...................................................... 10-215
Heat Sinking the HA-2541 & HA-2542 .................................................. ,550, 552 ............. ,................................ 10-173, 179
HI-200 ............. :.............................................................................. :........... 520,521,531,532 ............................. 10-37, 46, 74, 78
HI-201 ........................................................................................................520, 521, 531, 532 ............................. 10-37, 46, 74, 78
HI-201HS ...................................................................................................520, 521, 531, 532, ............................ 10-37., 46, 74, 78
543 ...................................................... 10-122
HI-301 to HI-307 .......................................................................................520, 521, 531, 532, ............................ 10-37, 46, 74, 78
534 ...................................................... 10-82
HI-381 to HI-390 .......................................................................................520, 521, 531, 532, ............................ 10~37, 46, 74, 78
534 ...................................................... 10-82
HI-506/507/508/509 ..................................................................................520, 521, 524, 531 ............................. 10-37,46, 56, 74
HI-506A/507A/508A1509A ........................................................................520.521.531 ...................................... 10-37.46.74
H 1-506LA/507LA/508LAl509LA ...............................................................545 ...................................................... 10-135
HI-516/518 .................................................................................................531 ...................................................... 10-74
HI-5040 to HI-5051 ...................................................................................520. 521. 531. 532 ............................. 10-37.46.74,78
HI-5618 ......................................................................................................530 ...................................................... 10-71
HI-562A ......................................................................................................524 ...................................................... 10-56
HI-574A/674A ..............................................................................,.............. 560, 529, 530, 531, ............................ 10-206, 68, 71, 74
,
545 ...................................................... 10-135
HI-774A ......................................................................................................524, 529 .............................................. 10-56, 68
HI-5320 ......................................................................................................531, 538 .............................................. 10-74, 93
HI-5330 ......................................................................................................524 ...................................................... 10-56
HY-9590/9591 ............................................................................................560, 529, 530 ...................................... 10-206,68, 71
High Accuracy Multiconverter DAS System ...................... :.................. 535 ...................................................... 10-87
High Impedance Transducers Interface ................................................540, 555 .............................................. 10-105, 199
High Power Audio Circuits .....................................................................552 ...................................................... 10-179
High Slew-Rate Op Amp .........................................................................541 ...................................................... 10-109
High Speed Amplifiers .............................................................................514, 515, 525, 526, ............................ 10-14, 21, 59, 63
541 ........................................ ~ ............. 10-109
High Speed. Precision MUX System .......................................................553 ...................................................... 10-184
High Speed Sample & Hold ....................................................................525, 543, 548 ...... :............................... 10-59, 122, 142
High Speed Switch ...................................................................................543 ...................................................... 10-122
High Throughput MUX/DEMUX .............................................................550 ...................................................... 10-173
HV-1000 .....................................................................................................542 ...................................................... 10-113
Hybrid Conversion 2W to 4W .................................................................549 ...................................................... 10-154
Hybrid Conversion 4W to 2W .................................................................549 ...................................................... 10-154
IMES (Induction Motor Energy Saver) ..................................................542 ...................................................... 10-113
Impedance of Electrical Connections ....................................................535 ...................................................... 10-87
Input CapaCitance COnsiderations (Op Amps) .....................................515 ...................................................... 10-21
Input Overvoltage Protection in Switches .......... ··.................. i .............. ·521, 532 .............................................. 10-46,]8
Instrumentation Amplifier........................................................................540, 553, 555 ...................................... 10-105, 184, 199
Integrator ...................................................................................................514, 543 .............................................. 10-14, 122

10-4

Application Note Index (Continued)
APPLICATION

A. N. NUMBER(S)

PAGE

Interface DTLlTTLfCMOS .......................................................................520 ...................................................... 10-37
Inverting Programmable Gain Amplifier ................................................ 514, 534 .............................................. 10-14,82
J-FET Input Precision Op Amp Stage Description ..............................540 ...................................................... 10-105
Latched Multiplexers ................................................................................545 ......................................................
Latch Proof JI Technology .....................................................................521 ......................................................
Latch-Up in Analog Switches .................................................................521 ......................................................
Least Significant Bit (LSB) ......................................................................522 ......................................................
Level Linearity ..........................................................................................549 ......................................................
Line Coding ..............................................................................................573 ......................................................
Linear Dielectric Isolation Technology .................................................. 521 ......................................................
Logarithmic Amplifier ..............................................................................553 ......................................................
Logarithmic Current to Voltage Converter ............................................555 ......................................................
Longitudinal Balance ...............................................................................549 ......................................................
Longitudinal Current. ...............................................................................549 ......................................................
Loop Current Limit.. .................................................................................549 ......................................................
Low Level Signals ....................................................................................535 ......................................................
Low Noise Op Amps ................................................................................553, 554 ..............................................
Low-Pass Filter .........................................................................................543 ......................................................
Low Power Op Amps ...............................................................................544 ......................................................
Low Supply Voltage Operation of Switches .........................................534 ......................................................

10-135
10-46
10-46
10-53
10-154
10-215
10-46
10-184
10-199
10-154
10-154
10-154
10-87
10-184, 192
10-122
10-129
10-82

Metallic Current ........................................................................................549 ......................................................
Microprocessor Interface ........................................................................535 ......................................................
Microphone Amplifier ..............................................................................544 ......................................................
Monostable Multivibator ..........................................................................544 ......................................................
Most Significant Bit (MSB) ......................................................................522 ......................................................
Motor Controller (HV-1000) ....................................................................542 ",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, .................
Multiplexed Sample & Hold ....................................................................517 ......................................................
Multiplexer Accuracy (Input-Output Offset) ......................................... 520 ......................................................
Multiplexer Timing in a DAS ...................................................................520 ......................................................
Multiplexer VREF ......................................................................................520 ......................................................
Multiplexers ...............................................................................................520,521,524,531, ............................
545 ......................................................
Multiplexers Overvoltage Protected vs. Unprotected ........................... 520 ......................................................
Multiplexers with Latches ................... ""'" .............................................. 545 ......................................................
Multiplying OfA Converter ......................................................................514 ......................................................
Multivibrator ..............................................................................................514, 544 ..............................................

10-154
10-87
10-129
10-129
10-53
10-113
10-23
10-37
10-37
10-37
10-37, 46, 56, 74
10-135
10-37
10-135
10-14
10-14, 129

NAB Pre-Amplifier Circuit... ....................................................................544, 553, 554 ......................................
Noise in Operational Amplifiers ............................................................. 519, 554 ..............................................
Noise Reduction In JFET Op Amps .......................................................554, 555 ..............................................
Non-Inverting Programmable Gain Amplifier ....................................... 514 ......................................................
Nonlinearity (Linearity Error) ..................................................................522 ......................................................
Non-Return to Zero (NRZ) ......................................................................573, 576, 607.. ....................................
Nyquist Frequency ...................................................................................538 ......................................................

10-129,184,192
10-30, 192
10-192, 199
10-14
10-53
10-215,224,226
10-93

Offset Current Test (Op Amps) ..............................................................508 ......................................................
Offset Nulling! of High Speed Op Amps ................................................525, 541 ..............................................
Offset Voltage Test (Op Amps) ..............................................................508 ......................................................
Op Amp Properties of the HI-5320 and HI-2420 .................................. 538 ......................................................
Open Loop Voltage Gain Test (Op Amps) ............................................ 508 ......................................................
Operational Amplifier Noise Considerations ........................................519 ......................................................
Operational Amplifier Test Procedures .................................................508 ......................................................
Operational Amplifier Stability ...............................................................515, 525 ..............................................
Oscillator ...................................................................................................514, 541 ..............................................
Output Current Boosting (Op Amps) .................................................... 525, 526, 541.. ... :................................
Output Current Test (Op Amps) ............................................................ 508 ......................................................
Output Limiter ..........................................................................................525 ......................................................

10-11
10-59,
10-11
10-93
10-11
10-30
10-11
10-21,
10-14,
10-59,
10-11
10-59

10-5

109

59
109
63, 109

Application Note Index (Continued)
APPLICATION

A. N. NUMBER(S)

PAGE

Output Short Circuit Protection (Op Amps) ......................................... 541 ......................................................
Output Voltage Swing Increase (Op Amps) .......................................... 541 ......................................................
Output Voltage Swing Test (Op Amps) ................................................. 508 ......................................................
Overvoltage Protected Multiplexer ......................................................... 521 ......................................................
Overvoltage Protection of Switches .......................................................521. 532. 534 ......................................

10-109
10-109
10-11
10-46
10-46.78.82

Parasitic SCR Latch-Up ...........................................................................521 ......................................................
PCM 30/CEPT ...........................................................................................573 ......................................................
Peak Detector ...........................................................................................538. 555 ..............................................
Phase Selector ..........................................................................................514 ......................................................
Photo Diode Current to Voltage Converter ...........................................f?55 ......................................................
Pop-Corn Noise in Op Amps ..................................................................519 ......................................................
Power Denial (PO) ...................................................................................549 ......................................................
Power Dissipation Measurement (Op Amps) ........................................ 508 ......................................................
Power Saving with HV-1000 ....................................................................542 ......................................................
Power Supply Considerations for Switches ..........................................532 ......................................................
Power Supply Rejection Ratio Test (Op Amps) ................................... 508 ......................................................
PRAM .........................................................................................................514 ......................................................
Precision Op Amps ..................................................................................553 ......................................................
Precision Integrator ..... ,...........................................................................555 ......................................................
Precision JFET Operational Amplifier ................................................... 540. 555 ..............................................
Private Branch (PBX) ...............................................................................549 ......................................................
.Programmable Analog Microcircuit ....................................................... 514 ......................................................
Programmable Adder-Subtractor ........................................................... 514 ......................................................
Programmable Attenuator .......................................................................514 ......................................................
Programmable Gain Amplifiers (PGA) .................................................. 514.531.534. 535 .............................
543.553 ..............................................
Programmable Power Supply .................................................................514 ......................................................
Protection of Analog Switches ............................................................... 521 ......................................................
Pulse Code Modulation (PCM) ...............................................................576. 607 ..............................................

10-46
10-215
10-93. 199
10-14
10-199
10-30
10-154
10-11
10-113
10-78
10-11
10-14
10-184
10-199
10-105. 199
10-154
10-14
10-14
10-14
10-14.74.82.87
10-122. 184
10-14 '
10-46
10-224.226

Quieting Pattern (QP) ..............................................................................576. 607 .............................................. 10-224. 226
Radiofrequency AGC Amplifier ..............................................................526 ......................................................
Ramp Generator .......................................................................................514 ......................................................
Reference Pins of Switches ....................................................................532 ......................................................
Remote Sensor Loop Transmitter ..........................................................554 ......................................................
Resolution .................................................................................................522 ......................................................
R Loop .......................................................................................................549 ......................................................
RIAA Pre-Amplifier ...................................................................................554 ......................................................
Ring Injection ...........................................................................................549 ......................................................
Ring Feed Sense (RFS) ...........................................................................571 ......................................................
Ring Synchronization ..............................................................................571 ......................................................
Ring Trip Detection (RTD) ............................... !...................................... 549 ......................................................
Sampl~

10-63
10-14
10-78
10-192
10-53
10-154
10-192
10-154
10-213
10-213
10-154

& Hold ..........................................................................................517. 520. 524. 531 ............................. 10-23. 37. 56. 74
538. 514. 525 ....................................... 10-93. 14.59
Sample & Hold Applications ...................................................................538 ...................................................... 10-93
Sample & Hold Peak Detector ................................................................555 ...................................................... 10-199"
Sample & Hold Sample Rates .................................................................538 ...................................................... 10-93
Sample & Hold Accuracy (Offset. Charge Inj .• Gain. Drift Error) ...... 520 ...................................................... 10-37
Sampling Rate (DAS) ...............................................................................535 ...................................................... 10-87
Sense Circuits ...........................................................................................540 ...................................................... 10-105
Signal Conditioning ...................................................... :.......................... 534 ...................................................... 10-82
Signal Generator ......................................................................................514 ...................................................... 10-14
Signal Processing System .......................................................................538 ...................................................... 10-93
Signal Splitter ...........................................................................................541 .................................... ,................. 10-109
Sine Wave Oscillator ................................................................................514. 540 ............................ :................. 10-14. 105
Single Ended vs. Differential Signal Paths ............................................535 ...................................................... 10-87
Single Op Amp Instrumentation Amplifier ............................................540 ...................................................... 10-105
Single Supply ()peration of Switches .................................................... 532, 534 .............................................. 10-78. 82

10-6

Application Note Index (Continued)
APPLICATION

A. N. NUMBER(S)

PAGE

16 Bit Settling Time .................................................................................539 ......................................................
Spot Noise in Op Amps ...........................................................................519 ......................................................
Stability (Op Amps) .................................................................................515,525 ..............................................
Static Discharge .......................................................................................521 ......................................................
Static Handling Precautions ...................................................................520 ......................................................
Subscriber Line Interface Circuit (SLlC) ...............................................549, 571 ..............................................
Surge Protection ......................................................................................549 ......................................................
Switches ....................................................................................................520, 521, 531, 532, ............................
534, 543.......................... ....................
Switch Alternatives ...................................................................................531 ......................................................
Switch Applications in Data Acquisition Systems ................................ 531 ......................................................
Switch Hook Detection (SHD) ................................................................549 ......................................................
Switch Power Supply Considerations .................................................... 532 ......................................................
Switch Selection Criteria .........................................................................520, 531 ..............................................
Switching Video Signals ..........................................................................543 ......................................................
Syllabic Filter ............................................................................................607 ......................................................
Synchronous Rectifier .............................................................................514 ......................................................

10-100
10-30
10-21,59
10-46
10-37
10-154, 213
10-154
10-37, 46, 74, 78
10-82, 122
10-74
10-74
10-154
10-78
10-37,74
10-122
10-226
10-14

T1rr1Crr2 .................................................................................................573 ......................................................
Test Procedures for Operational Amplifiers .........................................508 ......................................................
Thermal Loop Current Limiting ..............................................................549 ......................................................
Tip Feed/Ring Feed Amplifiers (TFrrR) ................................................ 549 ......................................................
Tip/Ring .....................................................................................................549 ......................................................
Tone Correction Circuit ..........................................................................554 ......................................................
Track and Hold .........................................................................................514 ......................................................
Transcoder ................................................................................................573 ......................................................
Transducers ..............................................................................................535, 553, 554, 555 .............................
Transhybrid Loss ......................................................................................549 ......................................................
Transversal Amplifier ............................................................................... 549 ......................................................
Transmission Gate Design ......................................................................521 ......................................................
Two Wire Side (2W) .................................................................................549 ......................................................

10-215
10-11
10-154
10-154
10-154
10-192
10-14
10-215
10-87, 184, 192, 1
10-154
10-154
10-46
10-154

Understanding PCM Coding ...................................................................574 ...................................................... 10-221
Universal Mixer Stage ..............................................................................554 ...................................................... 10-192
/.lP Interface .............................................................................................(.529, 535, 545 ...................................... 10-68, 87, 135
Video Amplifier .........................................................................................525, 526, 541, 548 ............................. 10-59, 63, 109, 14
Video Gain Block .....................................................................................548 ...................................................... 10-142
Video Signal Switching ............................................................................543 ...................................................... 10-122
Wideband Operational Amplifier .............................................................541 ...................................................... 10-109
Weinbridge Oscillator ..............................................................................544 ...................................................... 10-129

10-7

Applications Note Abstracts
AN#

TITLE

ABSTRACTS

PAGE

508

Test Procedures For
Operational Amplifiers

Operational amplifier test procedures fo( offset voltage, bias current,
offset current, open loop voltage gain, common mode rejection ratio,
,power supply rejection ratio, output voltage swing, output current, continuity checks, power dissipation measurements.

10-11

509

A Simple Comparator
Using The HA-2620

Performance characteristics, application schematics output parameter
coritrol methods.

10-13

514

The HA-2400 PRAM Four
Channel Operational
Amplifier

HA-2400 Programmable Analog Microcircuit ,description, frequency
compensation, applications (analog ,multiplexer, non-inverting
programmable gain amplifier, inverting programmable gain amplifier,
programmable atteriuator, programmable adder-subtractor, phase
selector, phase detector, synchronous rectifier, balanced modulator,
integrator, ramp generator, track and hold, sample and hold, sine wave
oscillator, multivibrator, active filter, programmable power supply,
comparator, multiplying D/A converter),

10-14

515

Operational Amplifier
Input capacitance and stability, capacitive feedback compensation,
Stability: Input CapaCitance guidelines for compensation requirements.
Considerations

10-21

517

Applications Of A
Monolithic Sample And
Hold/Gated Op Amp

General Sample and Hold information and fourteen specific applications, including filtered Sample & Hold DAC De-Glitcher, IntegrateHOld-Reset, Gated Op Arrip, etc.

10-23

519

Operational Amplifiers
Noise Prediction.

Noise Model and equations, procedure for computing total output noise,
example, broadband noise measurement, spot noise prediction
techniques, typical spot noise curves, popcorn noise discussion,

10-30

520

CMOS Analog Multiplexers
And Switches; Application
Considerations

Switch selection criteria, datasheet definitions, care and feeding of
multiplexers and switches, digital interface, practical multiplexer applications alternative to CMOS switches and multiplexers.

10-37

521

Getting The Most Out Of
CMOS Devices For Analog
Switching Jobs

CMOS versus bipolar device performances, over voltage and channel interaction conditions, JI technology and latch-up, floating-body JI technology, fool-proof CMOS analog multiplexer, other DI benefits.,

10-46

522

Digital To Analog
Converter Terminology

Explains DAC terminology, Resolution Gain Error, Offset Error, L,inearity Error, Differential Linearity Error, Drift, Settling Time, etc.

10-53

524

Digital To Analog
To use of High Speed DAC's in tracking, servo, and successive approxiConverter High Speed ADC mation Analog to Digital Converters. Design ideas for Data Acquisition
Applications
Systems,

10-56

525

HA-5190/5195 Fast Settling
Operational Amplifier

Internal schematic, prototyping considerations, frequency compensation, performance enhancement methods, applications.

10-59

526

HA-5190/5195 Video
Applications

Video applications, video response tests, SIN ratio measurements,
power supply requirements temperature considerations, design hints,
prototyping tips, RF AGC amplifier, DC gain controlled video amplifier,

10"63

529

Microprocessor Interface
Methods For High-Speed
Data Acquisition Systems

Applications for the HI-574A family and HY-9590/9591. Data Acquistion
Systems, Microprocessor interfacing and a software flowchart.

10-68

530

A Data Acquisition And
Conversion System With
Less Than ±1 LSB Offset
Error

Description of a system incorporating automatic digital correction of
offset error.

10-71

10-8

Application Note Abstracts (Continued)
AN#

TITLE

ABSTRACTS

PAGE

531

Analog Switch Applications System configurations, analog switch types, CMOS switch selection
In A/D Data Conversion
guidelines, alternate uses of CMOS switches.
Systems

10-74

532

Common Questions
Concerning CMOS Analog
Switches

Power supply considerations, input overvoltage protection, single
supply operation, various questions about Harris D. I. switches.

10-78

534

Additional Information On
The HI-300 Series Switch

"ON" resistance, leakage currents, switching speeds, power supply
requirements, internal switch operation and schematics: single supply
operation, charge injection, power supplies conditions and protective
circuitry.

10-82

535

Design Considerations For
A Data Acquisition System
(DAS)

A collection of guidelines for the design of a Data Acquisition System.
Includes Signal Conditioning, Transducers, Single-Ended vs. Differential Signal Paths, Low Level Signals, Filters, Programmable Gain
Amplifiers, Sampling Rate, and computer interfacing.

10-87

538

Monolithic Sample/Hold
Combines Speed And
Precision

Description and electrical speCifications for the HA-5320 Sample/Hold
Amplifiers, explanation of errors sources, and HA-5320 applications.

10-93

539

A Monolithic 16 Bit D/A
Converter

Detailed description of the HI-DAC16 D-A Converter, chip photo and
schematic, plus applications and interface considerations.

10-100

540

HA-5170 Precision Low
Noise J-FET Input
Operational Amplifier

Internal design and technology, J-FET noise discussion, trimming of
offset voltage, Single Op Amp instrumentation amplifier, sine wave
oscillator, high impedance transducers interface, current source/sink
and current sense circuits.

10-105

541

Using HA-2539 Very High
Slew-Rate Wideband
Operational Amplifier

Prototyping considerations, output short circuit protection, offset
voltage adjustment, frequency compensation, composite amplifier
scheme DC error reduction, boosting output current, increasing output
signal swing, cascade amplifier, video gain block, high frequency oscillator, wideband signal splitter.

10-109

542

Using The HV-1000
Induction Motor Energy
Saver

What is an IMES? IMES application; HV-1000 algorithm; load antiCipation; basic circuit application of HV-1000; measuring power savings;
handling precautions and reliability.

10-113

543

New High Speed Switch
Offers Sub-50ns Switching
Times

Application enhancement using the HI-201 HS, high speed multiplexers,
high speed sample and hold, analog switch and Op Amp circuitry,
integrator with start/reset, low pass filter with select break frequency,
amplifier with programmable gain, future applications.

10-122

544

Micropower Op Amp
Family

Operation, noise performance, applications (remote sensor loop transmitter, charge pool power supply, low power microphone preamplifier,
AGC with squelch control, Wein bridge oscillator, bar code scanner,
monostable multivibrator).

10-129

545

New Multiplexers Simplify
System Design

Description and applications for the Harris HI-50XL family of latched
overvoltage protected multiplexers.

10-135

548

A Designer's Guide For
The HA-5033 Video Buffer

Operation, video performance, video parameter specifications, Y
parameters, applications (flash converter pre-driver, coaxial line driver,
video gain block, high speed sample and hold, audio drivers, crystal
osci !lator).

10-142

10-9

Application Note Abstracts (Continued)
AN#

TITLE

ABSTRACTS

PAGE

549

The HC-550X Telephone
Subscriber Line Interface
Circuit

Complete description of device functionality and applications of SLiC.

10-154

550

Usi ng the HA-2541

Protyping guidelines, thermal considerations and heat sinking, performance enhancements, applications (Wein bridge oscillator, high power
gain stage, video stage with clamp, multiplexerldemultiplexer, disk drive
write amplifier, gain programmable amp, composite amp).

10-173

552

Using the HA-2542

Prototyping guidelines, thermal considerations and heat sinking, performance enhancements, applications (multi-channel security system,
unbalanced coaxial driver, flash converter driver, programmable power
supply, bridge load driver, high current stage, differential line driver, DC
motor speed control).

10-179

553

Using the HA-5147

Construction and operation, low noise design applications (Instrumentation amplifier bridge sensor, multiplexer, precision threshold detector,
audio driver, NAB amplifier, multivibrator, programmable gain stage, log
amp, professional mixer).

10-184

554

Low Noise Family
HA-5102/04/12/14

Low noise design, operation, applications (Electronic scales, programmabie attentuator, Baxandal Circuit, RIAH amplifier, NAB preamplifier,
microphone amplifier, standard and simple Biquads, professional mixer.

10-192

555

Ultra Low Bias Amplifier,
HA-5180

Construction, layout hints, low noise design, applications (Sample and
Hold, precision sample and hold, pH probe, light sensor, photo diode
sensor, precision integrator, time, atomic partical counter circuit).

10-199

560

Applying the HY-9590
Analog Data Acquisition
Signal Processor

Describes use of the HY-9594 Signal Processor. Includes a description
of the input Multiplexer, Programmable Gain Instrumentation Amplifier,
and tile Track and Hold Amplifier, plus a Data Acquisition System
application.

10-206

570

Understanding CODEC
Timing

Describes in detail CODEC timing sequences and modes of operation.

10-210

571

Using Ring Sync with
HC-5502A and HC-5504
SLiCs

Describes use of the SLiCs Ring Synchronization pin and why you
should use it.

10-213

573

The HC-5560 Digital Line
Transcoder

Full functional and applications description of HC-5560 transcoder and
line codes.

10-215

574

Understanding PCM
Coding

The process of converting analog voice signals into Time Division
Multiplexed (TOM) Pulse Code Modulated (PCM) format is described
and illustrated.

10-221

576

HC-5512C PCM Filter
Cleans Up CVSD CODEC
Signals

Description of application of PCM Filter as an 1/0 filter for the CVSD.

10-224

607

Delta Modulation For Voice
Transmission

Introduction to delta modulation coding technique, 4 general applications, including digital transmission encryption, voice scrambling, and
audio delay: Also CVSDevaluation guidelines.

10-226

10-10

FOR YOUR INFORMATION

co
oIt)

...o

UJ

z

Harris Analog

No. 508

a.
a.

c(

TEST PROCEDURES
FOR OPERATIONAL AMPLIFIERS
By G. G. Miler
The offset voltage of the amplifier under test
(A.U.T.) is measured as follows:
1.

2.

The bias current is equal to the average of the plus
and minus input currents.
The input offset current is measured as follows:

5et + and -V to the desired supply voltage
and close 54 and 55.

Measure the offset voltage, VOFF1, as
above.

2.

Open 54 and 55 and measure VOFF2'

3.

The offset current is equal to (VOFF2 VOFF1) x 10- 7

Measure the voltage at VOFF'

The offset voltage is equal to (VOFF) (10. 3 ). The
feedback amplifier, A 1, drives the input of the A.U.T.
so that the output is at ground reference, VOFF is
driven to 1000 times the voltage necessary to compensate for the offset voltage.

TEST CIRCUIT FOR MEASURING OPEN
LOOP VOLTAGE GAIN

The bias current is measured as follows:
1.

Measure the offset voltage, VOFF1 ,asabove.

2.

Open 54 and measure VOFF2'

3.

The plus input current is equal to (VOFF2VOFF1) x 10-7 .

4.

Close 54 and open 55 and measure VOFF4'

5.

The minus input current is equal to (VOFF4
- VOFF1) x 10-7 .

en

g:~

The open loop voltage gain is measured as follows:

TEST CIRCUIT FOR MEASUREMENT
OF OFFSET VOLTAGE, BIAS CURRENT,
AND OFFSET CURRENT 10K,Q
10K.\}

10Q

1.

A.U.T.
101()2

l(){lK,Q

10-11

1.

5et the +V and -V supply voltages to the
desired value and set-V OUT to ground.

2.

Close 51 so that the sample and hold will
null the offset voltage.

3.

51 can be opened when the circuit stabilizes.
The sample and hold will maintain the voltage which nulls the offset voltage.

4.

5et - VOUT to the desired output voltage,
-V4 and measure VGAIN4'

5.

5et -V OUT to another output voltage, -V5
and measure VGAIN5'

«0
z

6.
[

The gain is equal to
V4 - V5
] x
VGAIN4 - VGAIN5

The output voltage/current is measured by connecting a load resistor, R L, to the output of the
A.U.T. The value of RL is cho,sen to yield an output
current which is the minimum acceptable output current at the desired output voltage. The amplifier
under test is programed to a voltage greater than the
desired output voltage by applying an equal but
opposite polarity voltage to =VOUT' The output voltage, VOUT, is measured to see if it reaches the
desired output voltage. This test is performed driving
the output positive and driving the output negative.

20,000.

-VOUT can be first set to zero and then to-1O volts.
This gives the gain in the plus direction. The gain in
the minus direction can be determined by using zero
and +10 volts. The average gain can be determined by
using output voltages of-l0 and +10 volts.
TEST CIRCUITS FOR MEASUREMENT OF
COMMON MODE REJECTION RATIO AND
POWER SUPPLY REJECTION RATIO

The power dissipation is measured by driving the output voltage to zero by grounding-VOUT and measuring the current in one of the power supply leads.

lOOK
-VOUT

lOOK

The continuity of the bandwidth control point is
checked by applying-5V to-V OUT and grounding
the bandwidth control point through a lOOK resistor.
VOUT should be less than one volt. There is a known
relationship between the voltage at the bandwidth
control point and the output voltage, VOUT' This
relationship depends on the device type. The continuity of the offset control points is determined by
measuring the voltage at these points. These voltages
wi" be slightly less than the positive supply voltage
for the HA-2600 and the HA-2500.

VOFF

10D
VOUT

-v

Common Mode Rejection Ratio:
1.

Set +V to +20 VDC, -V to -10 VDC, VOUT
+5 VDC by applying -5 VDC to -VOUT'

2.

Measure VOFF2'

3.

Set +V to +10 VDC, -v to -20 VDC, VOUT
to -5 VDC by applying +5 VDC to -VOUT'

4.

Measure I VOFF2 - VOFF4 I <1.0 VDC.

SIMPLIFIED SCHEMATIC OF THE COMPLETE
D_C. TEST CIRCUIT FOR OPERATIONAL
AMPLIFIERS,

The +1.0 volt limit corresponds to a rejection ratio of
aOda.
Power Supply Rejection Ratio:
1.

Set +V to +20 VDC, -V to 15 VDC, VOUT
to ground by grounding -VOUT.

2.

Measure VOFF2'

3.

Set +V to +10 VDC.

4.

Measure I VOFF2 - VOFF4 I <1.0VDC.

5.

Set +V to +15 VDC, -V to -10 VDC.

-VOUT

lOOK!}

looKD

6.

Measure VOFF6'

7.

Set -V to -20 VDC.

a.

Measure I VOFF6 - VOFFa I <1.0 VDC.

VOUT

The ±1.0 volt limit corresponds to a rejection ratio of
aOdB.
TEST CIRCUITS FOR MEASURING
OUTPUT VOLTAGE/CURRENT, POWER
DISSIPATION, AND CONTINUITY CHECKS

10-12

APP
NOTS

FOR YOUR INFORMATION

W

I-

o
z

Harris Analog

No. 509

A SIMPLE COMPARATOR USING THE HA-2620
G. G. Miller
The input current and impedance of a
comparator circuit frequently loads the
source and reference signals enough to
cause significant errors. This problem
is frequently eliminated by using a
high impedance operational amplifier
between the signal and the comparator.
Figure 1 shows a simple circuit in which
the operational amplifier is used as a
comparator which is capable of driving
approximately ten logic gates. The input impedance of the HA·2620 is typically 500 M.Q. The input current is
typically 1 nA. The minimum output
current of 15 rnA is obtainable with an
output swing of up to ±10 volts.

Figure 2 shows the waveforms for the
comparator. The stray capacitance at
the bandwidth control point can be
reduced considerably below that of the
breadboard circuit; this would improve
the switching time. The switching time
begins to increase more rapidly as the
overdrive is reduced below 10 mV and
is approximately 111s for an overdrive of
5 mV.
Dependable switching can be
obtained with an overdrive as small as
1 mV. However. the switching time
increases to almost 1211S.

I

+15V

VINo--~+-----'

>

:::(0)1-N-91-6--'r:-<>:;:UT
-15V

-VIN

= 50mV/DIV.+--+--1I----+--+--1

0----1

~
IN916

i\

~o~*~~~~~~~~\~~~

r

v REFERENCE

m
o

II)

270D

HORIZONTAL SWEEP RATIO

FIGURE 1 - HIGH IMPEDANCE COMPARATOR

=500ns/DIV

FIGURE 2 - WAVEFORMS FOR
HA-2620 COMPARATOR

The bandwidth control point is a very
high impedance point having the same
voltage as the amplifier output. The
output swing cpn be conveniently limited by clamping the swing of the bandwidth control point. The maximum
current through the clamp diodes is
approximately 300 11 A. The switching

A common mode range of ±11 volts and
a differential input range of ±12 volts
makes the HA-2620 a very versatile
comparator. The HA-2620 can sink or
supply, a minimum of 15 rnA. The ability to externally clamp the output to
any desired range makes the HA-2620 a
very flexible comparator which is capable of driving unusual loads.

time is dependent on the output voltage
swing and the stray capacitance at the
bandwidth control point.

10-13

£L
D.

«

APP
NOTS

FOR YOUR INFORMATION

Harris Analog

No. 514

THE HA-2400 PRAM FOUR
CHANNEL OPERATIONAL AMPLIFIER
By Don Jones

INTRODUCTION

CIRCUIT CONNECTIONS

Harris Semiconductor has announced a new
linear device, the HA-2400/HA-2405 Four
Channel Operational Amplifier. This com-bines the functions of an analog switch and a
high performance operational amplifier, and
makes practical a large number of new linear
circuit applications.
V+
v- GND CDMP

These input control the selection of the amplifier input channels in accordance with the
truth table below:
GAIN. VOLTSIVOLT
NON-INVERTING INVERTING

I+

I

~

L

~

:

~::~~;~I:~nl
+

I

I

~

I

I

-

:
0:
~
I

L

OUTPUT

2R~P.!:!!IERS~_~_C
01

___

40 + GAIN

COMPENSATION

OUTPUT

Frequency compensation for closed ·Ioop stability is recommended for closed loop gains
less than 10. This is accomplished by connection of a single external capacitor from
Pin 12 to A. C. ground (the V+ supply is reccommended). The following table shows the
minimum suggested compensation for various
closed loop gains, with the resultant bandwidth and slew rate. Obviously, when the
four channels are connected with different
feedback networks, the channel with the
lowest closed loop gain will govern the required compensation.

I

AMPLIFIER

- INPUT
DECODE/
DIFFERENTIAll CONTROL

Do

I

I

15
20
22
25
30
50

The digital inputs can be driven with any DTL
or TTL circuit which uses a standard +5.0V
supply.

I
I

SWITCH

8.0
8.0
8.0
6.0
5.0

>9

>10

I
ANALOG

BANDWIDTH SLEW RATE
(TYPICAL)
(TYPICAL)
(-3d B). MHz VOLTS/11 s

15

r- - 0-0-0- ----,

[£L

CCOMP
pF

I

.-J

ENABLE

DIGITAL INPUTS

A functional diagram of the HA-2400 is
shown above. There are four preamplifier
sections, one of which is selected through the
DTL!TTL compatible inputs and connected
to the output amplifier. The selected analog
input terminals and the output terminal form
a high performance operational amplifier.

DO

Dl

ENABLE

In actuality, the circuit consists of four conventional op-amp input circuits connected in
parallel to a conventional op-amp output
circuit. The decode/control circuitry furnishes
operating current only to the selected input
section.

OFF

H
H
Lor H

CHANNEL 1 CHANNEL
ON

l
l

Lor H
OVSL..:;+O.8V

OFF
ON

OF,F

OFF

OFF
OFF

OFF
OFF

21 CHANNEL 3

CHANNEL 4

OFF
OFF
ON
OFF
OFF

OFF
OFF
OFF
ON
OFF

+2.0V~H;;:':+5.0V

Compensation capacitors of greater value can
be used to obtain lower bandwidth, greater

10-14

generally practical to wire the outputs of two
or more devices directly together. The compensation pins of two devices, however, could
be wired together to produce a switch with
one output and more than four input channels.

phase margin, and reduced overshoot, at the
expense of proportionately reduced slew rate.
External lead-lag networks could also be used
to optimize bandwidth and/or slew rate at a
particular gain.

The voltage at the compensation pin is about
0.7V more positive than the output signal, but has a very high source impedance.
Maximum current from this pin is about
300.uA, which makes it a convenient point for
limiting the output swing through clamping
diodes and divider networks (see Application
Number 13).

APPlICA TIONS
Any circuit function which can be constructed using a conventional operational
amplifier can also be constructed using any
channel of the HA-2400. Similar or different
networks can be wired from the output to
each channel input pair.
The device can
therefore be used to select and condition
different input signals, or to select between
different op-amp functions to be performed
on a single input signal.

Even if the application only requires a single
channel to be switched on and off, it is often
more economical to use the HA-2400, rather
than a separate analog switch and high performance op-amp. Unused analog channel inputs
should be grounded. Unused digital inputs
may be wired to ground for a permanent
"low" input, or either left open or wired to
+5.0V for a permanent "high" input.

To wire a particular op-amp function to a
channel, simply connect the appropriate network between the two inputs for that channel
and the common output in the same manner
as in wiring a conventional op-amp. It is
often possible to design with fewer external
components than would be required in wiring
four separate op-amps (see Application Numbers 2and 3 on the following pages). It should
be remembered that the networks for unselected channels may still constitute a load at
the amplifier output and the signal input, as
if the unselected input terminals were disconnected from the network.

Illustrated on the following pages are a few of
the thousands of possible applications for the
Four Channel Operational Amplifier. These
will give the reader a general impression of
how the units can be connected; and probably
will help generate many other ideas for applications. Also included are some "challenges"
for the reader to modify the illustrated designs
to perform different functions.

APPLICATION NO. 1

If offset adjustment is required, it can generally be accomplished by resistive summation
at either of the inputs for each channel (see
Application Number 8).
The analog input terminals of the OFF channels draw the same bias current as the ON
inputs. The maximum differential input voltage of these terminals must be observed and
their voltage levels must never exceed the
supply voltages.

.,,'

ANALOG MULTIPLEXER WITH BUFFERED INPUT
AND OUTPUT

When the Enable input is held low, all four
input channels are disconnected from the
output. When this occurs, the output voltage
will generally slowly drift towards the negative supply. If a zero volt output condition
is required, one channel should be wired as a
voltage follower with its positive input grounded.

This circuit is used for analog signal selection
or time division multiplexing. As shown, the
feedback signal places the selected amplifier
channel in a voltage follower (non-inverting
unity gain) configuration, and provides very
high input impedance and low output impedance. The single package replaces four input
buffer amplifiers, four analog switches with
decoding, and one output buffer amplifier.

The amplifier output impedance remains low,
even when the inputs are disabled; so it is not
10-15

o:::t
,....

an

W

~

o
Z

a.
a.

«

For low level input signals, gain can be added
to one or more channels by connecting the
(-) inputs to a voltage divider between output
and ground.
Bandwidth is approximately
8 MHz, and the output will slew from one
level to another at about 15.0V per micro·
second.

two HA-2400's which can be programmed to
any of 16 different gains.

APPLICATION NO.3

Expansion to multiplex 5 to 12 channels can
be accomplished by connecting the compensation pins of two or three devices together,
and using the output of only one of the
devices. The Enable input on the unselected
devices must be low.
Expansion to 16 or more channels is accom·
plished in a straightforward manner' by connecting outputs of 4 four-channel multiplexers to the inputs of another four-channel
multiplexer.
Differential signals can be handled by two
identical multiplexers addressed in parallel.

AMPLIFIER, INVERTING PROGRAMMABLE GAIN

The circuit above can be programmed for a
gain of 0, -1, -2, -4 or -8.

I nverting amplifier configurations can also be
used, but the feedback resistors may cause
crosstalk from the output to unselected inputs.

This could also have been accomplished with
one input resistor and one feedback resistor
per channel in the conventional manner, but
this would require eight resistors rather than
five.

APPLICATION NO. 2

APPLICATION NO. 4
INPUT

Z-&OOO

D'",'"

}

COMTROl

''''.

ATTENUATORPROGRAMMABLE

AMPLIFIER, NON-INVERTING PROGRAMMABLE GAIN

This is a non-inverting amplifier configuration
with feedback resistors chosen to produce a
gain of 0, 1, 2, 4, or 8 depending on the
Digital Control inputs.
Comparators at the output could be used for
automatic gain selection for auto-ranging meters, etc.
CHALLENGE:

Design a circuit using only

This circuit performs the function of dividing
the input signal by aselected constant (1, 2,
4, 8, or 00 as illustrated). To multiply by a
selected constant, see circuit No.2. While T,
1T , or L sections could be used in the input
attenuator, this is not necessary since the
amplifier loading is negligible and a constant
input impedance is maintained. The circuit
is thus much simpler and more accurate than
the usual method of constructing a constant
impedance ladder and switching sections in
and out with analog switches.
Two identical circuits may be used to attenuate a balanced line.

APPlICA TlON NO. 5

With a low frequency input signal and a high
frequency digital control signal, a balanced
(surpressed carrier) modulator is formed.

-.::t
,....
II)

w

I-

APPlICA TION NO.7

o
Z

IN,

0.
0.
c(
V,N

ADDER/SUBTRACTDR PROGRAMMABLE FUNCTION

+l!iV

>---I~-.-oOUT

The circuit shown above can be programmed
to give the output functions -K 1 X, -K2 Y ,
-(K3X + K4Y), or K5X - K6Y. Obviously,
many other functions of one or more variables
can be constructed, including combinations
with analog multiplier or logarithmic modules.

INTEGRATOR/RAMP GENERATOR
WITH INITIAL CONDITION RESET

It is difficult in practice to set the initial
conditions accurately in an integrator. This
usually requires wiring contacts of a mechanical relay across the capacitor - - leakage currents of solid state switches produce integration inaccuracy. The scheme shown above
eliminates these reliability and accuracy problems.

This device opens up many new design approaches in digitally controlled analog com-putation or signal manipulation.

APPlICA TION NO. 6

Channel 1 is wired as a conventional integrator, Channel 2 as a voltage follower. When
Channel 2 is switched on, the output will
follow VIN, and C will discharge to maintain
zero volts across it. When Channel 1 is then
switched on the output will initially be at the
instantaneous value of VIN, and then will
commence integrating towards the opposite
polarity. This circuit is particularly suitable
for timing ramp generation using a fixed D. C.
input. Many variations are possible, such as
programmable time constant integrators.

+15V
>--II-~~OUTPUT

PHASE SELECTOR/PHASE DETECTOR/
SYNCHRONOUS RECTIFIER/BALANCED MODULATOR

This circuit passes the input signal at unity
gain, either unchanged, or inverted depending
on the Digital Control input. A buffered
input is shown, since low source impedance
is essential. Gain can be added by modifications to the feedback networks. Signals up to
100 kHz can be handled with 20.0V peak-topeak output. The circuit becomes a phase
detector by driving the Digital Control input
with a reference phase at the same frequency
as the input signal, the average D. C. output
being proportional to the phase difference,
with zero volts at +90 0 . By connecting the
output to a comparator, which in turn drives
the Digital Control, a synchronous full-wave
rectifier is formed.

APPLICATION NO. 8

:>----i}----1----QOUTPUT

TRACK AND HOLD/SAMPLE AND HOLD

Channel 1 is wired as a voltage follower and

10-17

is turned on during the track/sample time.
If the product of R x C is sufficiently short
compared to the period of maximum output
frequency, or sample time, C will charge to
the output level. Channel 2 is an integrator
with zero input signal. When Channel 2 is
then turned on, the output will remain at the
voltage across C.

An even simpler circuit can be made by wiring
one channel as an amplifier, choosing the
compensation capacitor to yield the minimum
required bandwidth or slew rate. When the
Enable input is pulled low, the output will
tend to remain at its last level, because of the
charge remaining on the compensating capacitor.

APPLICATION NO.9

SINE WAVE OSCILLATOR PROGRAMMABLE FREQUENCY

Any oscillator which can be constructed using
an op-amp, such- as the twin-T, phase shift,
crystal controlled types, etc. can be made
programmable by using the HA-2400. Illustrated above is a Wien Bridge type, which is very
popular for signal generators, since it is easily
tunable over a wide frequency range, and has
a very low distortion sine wave output.
The frequency determining networks can be
designed from about 10Hz to greater than
1MHz. Output level is about 6.0V RMS.
By substituting a programmable attenuator
(Circuit No.4) for the Buffer Amplifier, a
very versatile sine wave source for automatic
testing, etc. can be constructed.

APPlICA TION NO. 10

CHALLENGE: A high G, narrow band filter
can be made by feeding back greater than
1/3 of the output to the negative input.
Design a circuit using the HA-2400 and an
RC network which can be programmed either
to generate or to detect an audio tone of the
same frequency. Such a circuit would be
quite useful for data communications.

MULTIVIBRATOR, FREE RUNNING,
PROGRAMMABLE FREQUENCY

This is the simplest of any programmable
oscillator circuit, since only one stable timing
capacitor is required. The output square
wave is about 25.0V peak-to-peak and has
10-18

rise and fall times of about 0.5/1 s. If a programmable attenuator circuit (No.4) is placed
between the output and the divider network,
16 frequencies can be produced with two
HA-2400's and still only one timing capacitor.

Many systems require one or more relatively low current voltage sources which can
be programmed to a few predetermined levels.
It is no longer necessary to purchase a programmable power supply with far more capability than needed. The circu it shown above
produces positive output levels, but could be
modified for negative or bipolar outputs.
Ql is the series regulator transistor, selected
for the required current and power capability.
Rl, Q2 and Q3 form an optional short circuit
protection circuit, with R 1 chosen to drop
about 0.7V at the maximum output current.
The compensation capacitor, C. should be
chosen to keep the overshoot, when switching,
to an acceptable level.

A precision programmable square-triangle generator can also be constructed by adapting
circuit described in Harris Application Note
507 to the HA-2400.

APPLICATION NO. 11

CHALLENGE: Design a supply using only
two HA-2400's which can be programmed to
16 binary weighted (or 10 BCD weighted)
output levels.

APPLICATION NO. 13
ACTIVE FILTER PROGRAMMABLE

Shown above is a second order low pass filter
with programmable cutoff frequency. This
circuit should be driven from a low source
impedance since there are paths from the output to the input through the unselected networks.
Virtually any filter function which can be
constructed with a conventional op-amp can
be made programmable with the HA-2400.

COMPARATOR. FOUR CHANNEL

A useful variation would be to wire one channel as a unity gain amplifier, so that one could
select the unfiltered signal, or the same signal
filtered in various manners. These could be
cascaded to provide a wide variety of programmable filter functions.

When operated open loop without compensation, the HA-2400 becomes a comparator
with four selectable input channels.
The
clamping network at the compensation pin
limits the output voltage to allow DTL or TTL
digital circuits to be driven with a fanout of
up to ten loads.

APPLICATION NO. 12

Output rise and fall times will be about lOOns
for differential inputsignals of several hundred
millivolts, but will be in the microsecond
region for small differential signals.
The circuit can be used to compare several
signals against each other or against fixed
references; or a single signal can be compared
against several references. A "window comparator", which assures that a signal is within
a voltage range, can be formed by monitoring
the output polarity while rapidly switching
between two channels with different reference
inputs and the same signal input.

POWER SUPPLY 'PROGRAMMABLE

10-19

v
,...
It)

...
W

o
Z

no
no

«

APPLICATION NO. 14
DIGITAL INPUT

~
ANALOG
INPUT

'"

,...
MUL TIPL YING D TO A CONVERTER

• A to D Converter, Dual Slope Integrating
• Active Filter, State Variable Type with
Programmable Frequency and/or
Programmable "Q"
• Amplifier with Programmable D.C. Level
Shift
• Chopper Amplifiers
• Crossbar Switches
• Current Source, Programmable
• F.M. Stereo Modulator
• F.S.K. Modem
• Function Generators, Programmable
• Gyrator, Programmable
• Monostable Multivibrator, Programmable
• Multiplier, Pulse Averaging
• Peak Detector with Reset
• Resistance Bridge Amplifier/Comparator
with Programmable Range
• Sense Amp/Line Receiver with
Programmable Threshold
• Spectrum Analyzer, Scanning Type
• Sweep Generator, Programmable
• Switching Regulator
• Touch-Tone ™ Generator/Detector
(Use Harris HD-0165 Keyboard
Encoder I.C.)

The circuit above performs the function,
VOUT = VIN . 1~' where N is the binary
number from 0 to 15 formed by the digital
input. If the analog input is a fixed D.C.
reference, the circuit is a conventional 4-bit
D to A. The input could also be a variable or
A.C. signal, in which case the output is the
product of the analog signal and the digital
signal.
The circuit on the left is a programmable
attenuator with weights of 0, 1/4, 1/2 or 3/4.
The circuit on the right is a non-inverting
adder which adds weights to the first output
of 0, 1/16, 1/8 or 3/16.
If four quadrant multiplication is required,
place the Phase Selector circuit (No.6) in
series with either the analog input or output.
The DO input of that stage becomes the
+ or - sign bit of the digital input.

MORE CHAllENGES
One of our favorite college textbooks paused
at each climactic point with a statement to
the effect that, "Proof of the following
theorem is omitted, and is suggested as an
exercise for the student."

FEEDBACK
We believe we have only scratched the surface
of possible applications for a multiple channel
operational amplifier.

The following is a list of some additional
applications in which we believe the HA-2400
will prove very valuable. The "proofs", at
present, remain as exercises for our ingenious
readers.

If you have a solution for any of the previous
"challenges" or any new application, please
let us know.
Anything from a one word
description to a tested design will be welcome.

10-20

APP
NOTS

FOR YOUR INFORMATION

It)
'r'"
It)

'W

I-

o
Z

Harris Analog

No. 515

a:

Q.

le
duty, serving as a buffer amplifier as well as
a glitch remover, delaying the output by Y,
clock cycle.

The system illustrated automatically zeros a
high gain amplifier. Care in the actual design
is necessary to assure that the zeroing loop is
dynamically stable. A second sample-and-hold,
could be added in series with the output to remove the output discontinuity.

The HA-2420 may be used to remove many
other types of "glitches" in a system. If a delayed sample pulse is required, this can be
generated using a dual monostable multivibrator I.C.

Many variations of this scheme are possible to
suit the individual system.

APPLICATION NO.11

APPLICATION NO. 9
This circuit reconstructs and separates analog
signals which have been time division multiplexed.

Integrate-Hold-Reset

The conventional method, shown on the left,
has several restrictions, particularly when a
short dwell time and a long, accurate hold
time is required. The capacitors must charge
from a low impedance source through the resistance and current limiting characteristics of
the multiplexer. When holding, the high impedance lines are relatively long and subject

HOL~

....,.
Il..lU ~R'
r,'::===1~
'N

7i0

OUT
(

V1N

\

INITIAL

CONDITION
LEVel

De-Multiplexer
OUT

~
MUlTIPlEX~AI
~
~

ANAlOGr

This circuit accurately computes the functions,

-

[ 12

-

I

Vo = Tl Vin dt

I~

I

~
I:~~.-

I

'

I

,

I

and holds the answer for further processing.

•

Lfr~

-

CONTROL

CONTROL

OLD WAY

NEW WAY

to noise pickup and leakage. When FET input
buffer amplifiers are used for low leakage, severe temperature offset errors are often introduced.
Use of the HA-2420 greatly diminishes all of
these problems.

APPLICATION NO. 10

Resetting circuits for integrators have always
been a practical design problem. The reset
circuit must produce an extremely low leakage
current across the integrating capacitor, and
must produce a very low offset voltage when
turned on. The circuit illustrated has excellent
results since the leakage at the switch node is
exceptionally low. Rc and Cc prevent oscillations during reset and their product should be
at least 0.02 times RI XCI'
For the simpler integrate and reset function
without a hold, substitute an ordinary operational amplifier for the upper device.

Automatic Offset Zeroing
'N

APPLICATION NO. 12

OUT

This accurate, low drift peak detector circuit
combines the basic sample-and-hold connection with a comparator, and will detect 20V
p-p signals up to 50kHz,
10-28

When the input signal level exceeds the voltage being stored in the S/H, the comparator
trips, and a new sample of the input is
taken. The S/H offset pot should be adjusted
for a slight positive offset, so that"the comparator will trip back when the new peak is
acquired; otherwise the comparator would
remain "on" and the S/H would follow the
peak back down.

This useful application illustrates how fast repetitive waveforms can be slowed down using
sampling techniques. The input signal is much
too fast to be tracked directly by the X-V recorder; but sampling allows the recorder to be
driven as slow as necessary.
To operate, the waveform is first synched in
on the scope. Then the potentiometer connected to the recorder X input is slowly advanced, and the waveform will be reproduced.
The HA-2420 samples for a very short interval once each horizontal sweep of the scope.
The sampling instant is determined by the potentiometer at the instant when the horizontal
sweep waveform corresponds to the X position
of the recorder.

To make a negative peak detector, reverse the
comparator inputs, and adjust the S/H for a
negative offset.

This principle can be applied to many systems
for waveform analysis, etc.
OUT

APPLICA TION NO. 14

AOJUST FOR

Vos>+SmV

Gated Operational Amplifier

+5V
2K

I~OUT

. c?

CONTROL

RESET

.n..

EOUIVALENT
CIRCUIT

OPEN COLLECTOR
TTL GATE
FEEDBACK

The reset function, which is difficult to
achieve in other peak detector circuits, forces
a new sample at the instantaneous input level.

APPLICA TION NO. 13
Plot High Speed Waveforms
With Sampling Techniques
The following are a few of the many applications where an operational amplifier followed
by a highly efficient analog switch could be
used:

SCOPE er"",O""RIZ",.S",-WE",EP,-------,

X~Y

Analog Multiplexer Element
Gated Oscillator
Precision Timing Circuit
Chopper Type Modulator/Demodulator
Crosspoint Switch Element
Reset or Initial Conditions Switch
Gated Comparator
Automatic Calibration Switch
Gated Voltage Regulator

PLOTTER

10-29

,...
'I'""

It)

lLI

t-

O
Z

~
~



1.2 k-~~~+-~~~+-~~~+-~~~-+-~~~---1

CI)

8

(5
Z

o

,--~~~,--~~~,-~~~--,--~~~---,~~~--,

!1.0~~~~+-~~~~-~~~+-~~~-+-~~~---1

...,-/

.............

I-

HA-5130/35 INPUT NOISE CURRENT
1.4

14

~:;

W

Curve lA

4

.6~~~~+-~~~+-~~~~~~~-+-~~~___1

OJ
I-

i

:::>

~

.4 f--~~-'I..-

;!;

.2f-------+--~~~------~~--_4------___1

o

OL-~~~L-~~~~~~~J-~~~_L~~~~

100

10

1K

10K

100K

10

100

100K

FREQUENCY - HZ

Curve 2
HA-240G INPUT NOISE VOLTAGE

~

10K

1K

FREQUENCY - HZ

Curve2A
HA-2400 INPUT NOISE CURRENT

10-13

?

1

~1O-14.B!

g
~
(jf

~ 1O-15
10-16

lllill1

=
" 10-26

100

'-------'--...LJ.-llllll~-'----.LLlilllL,-LJ--LLUJllL___"__"__Ll_LllJJ
10

L-'--'-'-llllJJL-'~WJJJ'----1,_LLWlli--'-...LlJ-"!,,

10

100

10K

Frequency, Hz

Curve 3
HA-250012510/2520 iNPUT NOISE VOLTAGE

lK
Frequency, Hz

10K

Curve 3A
HA-2500/2510/2520 INPUT NOISE CURRENT
10- 21 _

_

10- 11

~ ~"MII~!II~MIIMII

_ 10-12

·'0o

>

-9.9.r-r;.

~r.

10-13

~

"Q-9.;

'0

z

.

~

i

10-

.J'aRii

2:

!

22

.J'a

~

10- 14

~

oa

t.1

c9J};'~~
~Q,
i:'Q~ /0 IIII

i!

0
'f"J)

I

, I

::0

23
10-

'111111
~

tf'Oq/,C':

'-9,
I

10- 15

<9J'I.r,~

·0.

10- 25 _

"oJ)

IIII

10- 16
10

100

lK
Frequency, Hz

10K

_

10-26 '-----L..1...LlJWll___"--'-'LillJJL-.L-LLUllJ"----~_LLWlJ
10
100
lK
10K
lOOK
Frequency, Hz

lOOK

10-33

lOOK

Z

D..
D..

«

TYPICAL SPOT NOISE CURVES (continued)

Curve 4

Curve 4A
HA-2600/2620 INPUT NOISE CURRENT

HA-2600/2620 INPUT NOISE VOLTAGE
10- 13

10-24

1"-

~

Source Resistance = 300Kn

-I-

t-...

"""-"

Source Resistance

II

10-16
10

"

Source Resistance = 30K!1

100

on

11111

10-27

10

lOOK

10K

lK

100

Curve 5

10K

lOOK

Curve 5A
HA-2640/45 INPUT NOISE CURRENT (VS =:!.:30V)

HA-2640/2645 INPUT VOLTAGE NOISE (VS =:!: 30V )

~ 10- 14

lK
Frequency/Hz

Frequencv, Hz

"'-

?
~
<3
>

Source Resistance

1"-

~

~ 10- 15

j

I

11111111

100Kn
I

~ 25 ~lflllll!ll
1
~

I

Source Resistance

30Kfl

Source Resistance

on

~

10-

r--

~

"

i
II

10-16
10

100

lK

i

1111
10K

lOOK

~

10-26 L--L-Ll-L.Lilll_..LLl..wllL_Ll-LlilllL---L-LLLlillJ
10
10K
lOOK
100
lK
Frequency. Hz

Frequency, Hz

Curve6A
Curve 6

HA-2700 INPUT NOISE CURRENT

HA-2700 INPUT NOISEVOLTAGE

:>:

"«
i~
.~

1O-25~11~1~1111

z

lK
Frequency. Hz

10K

lOOK

10-27 L-....L-L..Ll..1J..W'---L..LL-'.JJWL_LJ-'-LllUL---'---L..L1l..l.W
10
100
lK
10K
lOOK
Frequency, Hz

10-34

TYPICAL SPOT NOISE CURVES (continued)

,...

0')

Ln

W

Curve 7

~

o

Curve 7A

HA-2720/2730 INPUT NOISE VOLTAGE (I SET = IJ..lA)

z

HA-2720/2730 INPUT NOISE CURRENT (lSET = IJ..lA)

0.:
a.

10-12

~ 10-26

Source Resistance == 10 Mn

i

N-

«

~

2:

l""-.
~ 10- 13

i'---,

c

>

I

'0

I"

z

j

~ 10-27

Source Resistance = 1M n

10- 14

j

Source Resistance = 30CKU
Source Resistance -

a~

III

10- 15
10

100

lK

10K

I

10- 2B 10

lOOK

100

1K

10K

lOOK

Frequency, Hz

Frequency, Hz

Curve 8
HA-2720/2730 INPUT NOISE VOLTAGE (lSET = IOJ..lA)

Curve 8A

10-12

HA-2720/2730 INPUT NOISE CURRENT (I SET = I0J..lA)

~

N 10-25

~

2:

1

~

Source Resistance

1

10- 13

=

3m n

c'"

II

~

"

~

~

>

~

'0

~

& 10- 14

Source Resistance;: 300K n

~

"1'-

.~ 10- 26

, I

z

z

r-

j

1

Source Reisstam:e = 0 n

~

'"

I

10- 27
10

100

lK

lOOK

10K

Frequency, Hz

10-15
10

100

lK

10K

lOOK

Frequency, Hz

Curve 9
Curve 9A

HA-2720/2730 INPUT NOISE VOLTAGE (lSET = I00J..lA)

'O-'3~ _

_

:01O-'4m_=-

~

..

I

I

............

HA-2720/2730 INPUT NOISE CURRENT (lSET = I00J..lA)

: I I Source Resistance'" 300Kn.

_ 10-24

;E
~

'0

•
z

Source Resistance = 100Kn

e

Source Resistance = 051

>

'0

~'O-15~IIII.
~
~

.~ 10-25

I

I

I
I

z

j
c

'"

'0-'6 ,Lo-l--LUlil,JLOo-Ll-LLWlJ'~K-L-.-L-LLLll.,ll.OK::-L..L-'-'-':',O:':OK
Frequency. Hz

10-35

11111

10-26
10

100

lilllJ

111111
lK
Frequency, Hz

10K

lOOK

TYPICAL SPOT NOISE CURVES (continued)
Curve 10
HA-4602/4605 INPUT NOISE VOLTAGE

Curve IDA

10-12

HA-4602/4605INPUT NOISE CURRENT

10-

22

10-13

31'.
Sourc eResistlnce'" 1001(0

'"

"-

m- 16

SourceResistlnce=O

10-

IIIII
10-17

25 10

100

lK
Frequencv.Hz

Curve llA
10-24

~

:~; 10-25

!

i

!
~

lOOK

HA-4741 INPUT NOISE CURRENT

1O-14~W:;~
~
Source Resistance - lOOKn
.~

10K

lOOK

10K

Curve 11

~

lK
Frequency, Hz

II IIIII
10

HA-4741 INPUT NOISE VOLTAGE

z

"'

100

1
10- 5~IIIII'IIIIIIIIIIII

<3
a

z

j

10-16~.-.B.BI
~
Frequency, Hz

,

'0

Source Resistance = on

I

,

I

10

100

Curve 12
10-12 r-rnTTlTn-TTTTTTnr-.--rTTTrrrr-,-,rrrrmr-rTTTmn

10- 13

10-14
,~~

"...
10-16

10- 16

1K

10K

I

~
10-27

10-17

I

10-26

c

,

~

,

I

i

<[

lMEG

lOOK

"G.~hms

10~36

10M

100M

lK
Frequency. Hz

10K

lOOK

APP
NOTE

FOR YOUR INFORMATION

It)

w

I-

o
z

Harris Analog

No. 520

CMOS ANALOG MULTIPLEXERS AND SWITCHES;
APPLICATIONS CONSIDERATIONS
Don Jones and AI Little

Introduction
This article describes several important considerations
for the use of CMOS analog multiplexers and switches. It
includes selection criteria, parameter definitions, handling and design precautions, interfacing, typical applications, and special topics such as overvoltage protection
and R.F. switching. Some other devices which perform
analog switching functions are discussed as well.
Application Note 521 is also recommended for the analog
multiplexer and switch user. It details the different CMOS
processes used by various manufacturers, showing the
performance trade-offs and failure modes which may be
encountered with each.

Choosing the Right Device
A. Multiplexers:

Q
C\I

Protected or Unprotected?

Analog input signals which originate externally to a
system can be destructive to a multiplexer for several
reasons:
1. Analog signals may be present while the MUX
power supplies are off.
2. The signal lines may receive induced voltage spikes
from nearby sources.
3. Static electricity may be introduced on the signal
lines by personnel or equipment.
4. Grounding problems are frequent; A. C. power line
voltages at high impedance can appear on the signallines. Signal lines can be accidentally shorted to
other voltage sources.
Each of these situations are common in data acquisition,
telemetry, and process control systems. In each case, a
voltage at the multiplexer input exceeds the rail voltage.
Without current limiting, this voltage will degrade or
destroy the device.

parasitic bipolar transistors within the multiplexer which
turn on during overvoltage. (Application Note 521
explains this mechanism in detail).
A few multiplexers feature built-in overvoltage protection,
designed to eliminate the external networks. The protection capability varies widely among these devices,
however. Some offer very slight advantages over ordinary
multiplexers while others withstand wide voltage extremes. Unfortunately, nearly all suffer from the same
output signal corruption problem described above.
Harris overvoltage protected multiplexers, H 1-50BA/
507 N508A/509A, are an exception to this rule. During
overvoltage, active protection circuitry automatically
shuts off the parasitic transistor, thereby preventing output signal contamination. These devices will withstand a
continuous voltage on anyone input of ±20 Volts greater
than either supply (this limitation is due only to temperature rise considerations at maximum ambient) and have
withstood simulated static discharge conditions of
greater than 4,500 Volts.
It should be emphasized that only the HI-50BA through
509A (and exact equivalents from authorized alternate
suppliers) will have this kind of protection necessary for
inputs from the outside world. Certain CMOS process improvements, such as "floating body" and "buried layer" do
help minimize one failure mode (Iatchup) but will still fail
under excess voltage or current conditions prevalent in
this type application.
A simplified equivalent circuit of the Harris internal
protection network is shown in Figure 1.

lKn

Any conventional CMOS multiplexer can be protected
against overvoltage destruction by external resistordiode networks which limit input current to a safe level.
Such networks are expensive, however, both in cost and
in circuit board space. Another drawback is the output
signal corruption that accompanies an overvoltage regardless of which input is·selected. This occurs due to

10-37

-v"'--_"

ANA LOG

OUT

FIGURE 1.

a:

a.

:

Lf

E. Demultlplexlng

I

IIL ___ ...JII

Since the switches in a CMOS MUX conduct equally well
in either direction, it is perfectly feasible to use it as a
single input-selected multiple output switch. Figure 5
illustrates its use as a demultiplexer, with capacitors to
hold the output signal between samples. When the
address lines are synchronous with the address of the
original multiplexer, the output lines will create the
original inputs, except level changes will be in steps.
Overvoltage protection is not effective with signals

injected at the normal MUX output, so an external network

'::'"

la) LOW ACCURACY

I

I

I.
I

Ie) LOW ACCURA·
CY

10-42

: Lf :
'-- _ _ ..J

FIGURE 6.

":'

Id) HIGH ACCURACY

Application Note 520
C. Switching Spikes And Charge Injection
Transient effects when turning a switch off or on are of
concern in certain applications. Short duration spikes are
generated (Figure 7(a)) as a result of capacitive coupling
between digital signals and the analog output. These have
the effect of creating an acquisition time interval during
which the output level is invalid even when little or no
steady state level change is involved. The total net energy
(charge injection) coupled to the analog circuit is of concern when switching the voltage on a capacitor, since the
injected charge will change the capacitor voltage at the
instant the switch is opened (Figure 7(b)).

.,

+- [5j

feedthrough vs. frequency characteristics of the OFF
switch. Optimizing the first characteristic requires a
low RON x CD product, and the second a low value of
CDS (OFF).
One approach is to use the 30 ohm switch types of the
H 1-5040 series.
Figure 9 illustrates three circuit configurations; (a) is a
simple series switch, (b) is a series-shunt configuration to
reduce feedthrough, and (c) is a SPDTselector configuration with series-shunt elements. A 1K ohm load is
illustrated, which might be the input impedance of a buffer amplifier; a lower load resistance would improve the
response characteristics. but would create greater losses
in the switch and would tend to distort high level signals.

o

N

It)

W

I-

o
z

0:
D..

«

I
I

-.J

SCOPE
lMn,20pf

(al

(bl
SIG. GEN.

FIGURE 7.

Charge injection is measured in picocoulombs; the voltage transferred to the capacitor computed by
Charge (pC)
V=
Capacitance (pF)

(a)

Both of these effects are, in general, considerably less for
CMOS switches than for equivalent resistance JFET or
PMOS devices, since the gate drive signals for the two
switching transistors are of opposite polarity. However,
complete cancellation is not possible, since the Nand P
channel switches do not receive gate signals quite simulaneously, and their geometrics are necessarily different to
achieve the desired D.C. resistance match.

51G. GEN.

(b)

In applications where transients create a problem, it is frequently possible to minimize the effect by cancellation in
a differential circuit, similar to Figure 8.

DIFFERENTIAL

"" i-~:! ~ ~

~
I: ;-+:-----1~

en

g:~
HI-504SA

r-----l

SIGNAL "v

R'

_

-

I

I

I

Rsll\l

-=

L-T-.J

~I

~~
I

SIG. GEN.

FIGURE 8.

-=

Among the Harris analog switches, the HI-201 is the best
from the transient standpoint, having turn-on spikes of
about 100mV peak, 50ns width at the 50% pOint, and
charge injection at turn-off of about 20 picocoulombs.
Transients of the HI·5040 series are several times higher.
D. High Frequency Switching
When considering a switching element for R.F. or video
type information, two factors must be watched: attenuation vs. frequency characteristics of an ON switch, and

lei
FIGURE 9.

Figure 10 shows ON and OFF frequency response for
each of the above configurations. Arbitrarily, we will define useful frequency response as the region where ON
losses are less than -3dB and OFF isolation is greaterthan
-40dB.

10-43

«0
z

Application Note 520
The simple configuration (a) has excellent ON response,
but OFF isolation limits the useful range to about 1MHz
(the data sheet in<;licates -BOdS isolation at 100kHz, but
this is measured with 100 ohms load, which acounts for
the 20dS difference).

18

SIG GNU >-1:,:3-1-_ _---..1

The circuit in (b) shows a good improvement in isolation
produced by the low impedance of the shunt switch. The
useful range is about 10MHz; which could also be
achieved in a simple SPOT 2-switch selector if source
impedances are very low.

IN 2 -.....,!1C!,4.1---.1o'"

16

1-»
SWITCH~~N

/~
0

oV

V

7

V V
/

"-

V

7
V-

-5 0

0

SIG GNU

L

V

V

o--t----+"'-< OUTPUT

_--'-I-_r

>--f----'

IN 4

SIG GNU >---=4+-_ _--'

0

-,

IN3

,LJJ.Jo

0

F8(UUT)

SIG GNU ;>-'1""5+--_ _-'

The selector switch in (c) has excellent characteristics,
both ON and OFF curves indicating 40MHz useful response. Additional switches connected to the same point
would reduce the ON response because of added shunt
capacitance; but this could be eliminated by feeding
separate summing amplifier inputs.

0

F8[1N)

V

~V

10
FREQUENCY MHz

[.)
[ b)

SIG GNU

[

·15V PWR +15V
GNU

EN

Au

AI

FIGURE 11.

1/

the convenience of unity gain stability plus 90ns settling
(to ±0.1%) and ±10V output swing. Also, the HI-524 includes a feedback resistance for use with the HA-2541.
This resistance matches and tracks the channel ON resistance, to minimize offset voltage due to the buffer's bias
currents.

vV'

V

Careful layout is, of course, important for high frequency
switching applications to avoid feedthrough paths or excessive load capacitance.

100

FIGURE 10.

For many applications, a better approach is to use the
HI-524 monolithic wideband CMOS multiplexer. This
device utilizes a series-shunt multiple switching network
to achieve low crosstalk without sacrificing or compromising other operational parameters. As shown in
Figure 11, each channel comprises three CMOS FET
switch gates, with two in series and the third shunted to
ground. The two series switches ensure both a high off
isolation and low feed-through capacitance. The shunt
grounding switch, closed automatically by the control
logic when its corresponding series pair are open, shunts
nonselected channels to ground, thus minimizing cross
talk. With this circuit topology, crosstalk is typically-60dS
at 10MHz.
A buffer amplifier is used with the HI-524 for high frequency applications, due to its higher ON resistance, and
should offer sufficient bandwidth and slew rate to avoid
degradation of the anticipated signals. For video switching, the HA-5033 and HA-2542 offer good performance
plus ±100mA output current for driving coaxial cables.
For general wideband applications, the HA-2541 offers

Alternatives to CMOS Switches
and Multiplexers
CMOS devices are excellent in many applications.
However, there are some other devices which merit consideration in certain analog switching circuits where they
may improve performance, reduce parts count, or be
more economical.
A. The PRAM, Programmable Amplifier
The HA-2400/2405 is a unique monolithic bipolar circuit
which combines analog switching with high performance
operational ampl ifiers. It basically consists of four op amp
type input stages, anyone of which is connected to a
single output by bipolar switches controlled through a
TTL compatible address decoder. In a single package, it
contains the equivalent of 5 op amps plus a 4 channel
multiplexer. It has literally hundreds of applications in signal selection and programmable signal conditioning.
Figure 12 illustrates a four channel multiplexer. Connections from the output to each input stage are always the
same as a comparable op amp circuit; the +1 gain connection is illustrated.

10-44

Application Note 520

r--

v·

V-

GNO

be wired 4 ways to make programmable active filters,
oscillators, etc., etc. Harris Application Note 514 shows
many possibilities.

COMP

0-0-0- - - - ,

I

I
I

o

N

It)

W

I-

o

INPUT

Z

I

a.
a.

I

«

I OUTPUT
'''''

I
I
I
I

>-~[}--~--+5mV

2. Cannot be used in reverse as a demultiplexer.

+5V

2K

3, Disabling the device (enable pin low) does not open
the output line, or drive the output to zero. Adding
channels may be accomplished by tying compensation pins together.
RESET

.n..

Figure 13 illustrates the PRAM used as a programmable
gain amplifier. Any connection possible with op amps can

10-45

OPEN COLLECTOR

TTL GATE

FIGURE 14.

FOR YOUR INFORMATION

Harris Analog

No. 521

GETTING THE MOST OUT OF CMOS DEVICES
FOR ANALOG SWITCHING JOBS
By: Ernie Thibodeaux
and AI Little

Introduction
CMOS analog switches and multiplexers are now widely
used for a broad range of applications. They offer low
power consumption, low on-resistance, and will conduct
a signal in either direction. In addition, CMOS switch
structures exhibit no DC offset voltage and can usually
handle signals up to the supply rails.
Not all CMOS analog switches are alike, however.
Different technologies are employed by different manufacturers. Some types, handicapped by inherent process
limitations, can create significant problems for the user.
Switches built with older types of junctipn isolation, for
example, can literally self-destruct when a latch-up condition occurs. To prevent destruction, costly external
protective circuits are needed, but the devices can still
latch up unless the power is turned on and off in a set
sequence. Switch circuits can also be destroyed by electrostatic discharge, input overvoltage spikes and power
supply transients.

However, certain overvoltage conditions can forwardbias these junctions to cause high currents that could
possibly destroy the devices.

GATE

l
1
SOURCE

~~
V-

Vs

v+

I
[V+ 2 Vs 2 V-j

n-CHANNEL

1

BODY

DRAIN
~OUT

~~I

T

p-CHANNEL

GATE
Newer types of technologies include latch-proof junction
isolation (JI), floating-body junction isolation, and dielectric isolation (01). Both JI techniques are conventional
processes that have been slightly mOdified to alleviate the
old problem of latch-up. However, both of these JI
technologies still require costly external protection circuits to guard against burn-out in such applications as
analog-signal multiplexing that interface them with the
outside world. That is why JI devices are best suited for
internal-switching applications where the electrical
environment can be controlled. In contrast, the improved
01 technology, by virtue of its construction, offers analogswitching devices suitable for many inside applications,
as well as providing on-board analog protection for
devices that interface with the other circuits. Happily, the
smaller substrate area of the 01 device delivers a better
speed-power product than the JI technology.

The Basic CMOS Switch
The basic CMOS transistor (Figure 1) has parasitic junctions that are reverse-baised during normal operation.

FIGURE 1. BAD
In the basic CMOS analog switch, the parasitic junctions are reversedbiased during normal operation. Large overvoltages, however, make them
forward-biased and draw large currents.

The parasitic junctions are actually npn and pnp transistors that are normally reverse-biased by the appl ied body
potentials. However, because many analog switches, and
especially multiplexers, are connected to their analog
sources through long lines, they are highly susceptible to
externally induced voltage spikes, For example, these
spikes, which can often exceed the p-channel body
potential, V+, can inadvertently turn on a normally off
switch through the parasitic pnp transistor (Figure 1).
The n-channel device is similarly affected when the parasitic npn transistor is turned on by a negative overvoltage.
This action, commonly known as channel interaction,
causes momentary channel-to-channel shorting, which
introduces significant errors in the system. This intermittent condition is rarely isolated because it occurs only
randomly.

10-46

Application Note 521

,...
N

it)

One of the adverse effects of channel interaction is
illustrated in Figure 2. Channel 1 of an analog multiplexer
is selected when all other channels are off. Channel 16 receives an input-noise spike that momentarily exceeds the
positive supply. The sequence causeS channel 1 read-out
to be +16V because of interaction with channel 16 just before initiating the hold command to the sample-and-hold
device. To prevent this annoyance requires additional
protective circuits that clamp each channel input to a voltage below the threshold of the parasitics to ensure that
the channels remain inactive under any conditions.

W

t-

0

ISHORT

Z

h

IFA~

0.:
Q.


<.>

0..

;!:

9

CD

-'

<
z:
<

~

V·
DI devices also protect digital inputs. For example, the diodes in this circuit quickly discharge any static charge that may appear on an MOS input
gate.

u...
u...
c:>

c:>

«

FIGURE 11. DIGITAL PROTECTION.

""
::5
-'

::>

Z

Q.
Q.

V, = 0.6V

ANALOG INPUT
CURRENT [IINI

4 ~

I-

~

o
TO
ADDRESS
BUFFER

DIGITAL IN

IX!

z:

IX!

~ 12

II)

V, = 0.6V

21
18

N

V+

I-

6

2

::>
0..

I-

::>
c:>

3

0
±36

FIGURE 10. BLOCKING CROSS TALK.
DI switches have minimal cross-talk problems. An overvoltage of 33V produces a cross-talk current of only 5nA - an absolute error from channel
interaction of only 6j.1V.

In addition to handling continuous input overvoltages, the
HI-506A/507A/S08A/S09A multiplexers also survive very
large transient conditions. These devices typically
withstand repeated static discharges well beyond 4,000
volts at any analog input. In fact, even the unprotected
HI-506/507/508/S09 units can withstand discharges
beyond 3,000 volts, though they do not compare to the
steady state and signal protection offered by the "A"
series.

TO P3

Adding Benefits

P2

Additional DI benefits are passed on to the user in the
design of the digital input-protection circuit shown in
Figure 11. The fabrication of all components as isolated
silicon islands eliminates any possibility of latch-up. The
diodes switch fast and quickly discharge any static
charge that may appear at the digital MOS input gates.
Tests have shown that the digital inputs can typically
withstand repeated discharges at the 2,000 volt level.
The DI technology enables a wide variety of active
elements to be integrated on the same chip to provide
maximum versatility. For example, in the transistor-transistor-Iogic/CMOS reference circuit shown in Figure 12,
the bipolar technology enables realization of a simple
zener reference circuit, consisting of resistor R2 and transistors 01, 02, and 03·

Q6

en

g:~

Q9
5V

FIGURE 12. PACKING IT IN.
01 technology increases chip density of analog switch, allowing more circuit capability per package. Forexample, DI designs make possible this internal logic reference circuit in HI-200 and HI-201 switches.

10-51

«0
z

Application Note 521
The circuit develops a stable 5V reference for interfacing
with TTL and eliminates the need for an additional 5V
logic supply. Current for the zener (03) is supplied
through the normally on MOSFET, P1, which can be
easily turned off if not needed to minimize power
consumption when interfacing with CMOS-logic circuits.
P1 turns off when V+ or supply voltage VDD is applied to
the reference terminal VREF to convert the ICs
power consumption from bipolar to CMOS level. If power
is not critical, VREF can be left open to speed switching.

16-channel analog multiplexers ±15V supplies is shown
in Figure 13. The DI device consumes only 100mW at
1MHz to yield the best speed-power product.

400
l320
z

C>

ii: 240
:IE
:::>

In high-speed data acquisition systems, the designer is
concerned with both quiescent power and dynamic
power consumption. If JI devices are used, the
capacitance or leakage currents are so high they
contribute a major portion of total power consumption.
That situation is caused by the large-geometry parasitic
junctions formed by the n- junction.
In contrast, the smaller substrate area of the DI device
provides much less power drain. Dynamic-power
consumption as a function of frequency for several

~ 160

C>

c:.:>

a::

~ 80

JI

C>

"-

0
lk
10k
lOOk
TOGGLE FREQUENCY [IN Hz) (50% DUTY)

1M

FIGURE 13. 01 PERFORMS.
01 devices not only perform well, but do it with less power, Dynamic-power
consumption data for commercial multiplexers shows 01 device
consuming only 100mW at lMHz.

10-52

APP
NOTS

FOR YOUR INFORMATION

o
z

Harris Analog
DIGITAL TO ANALOG
CONVERTER TERMINOLOGY
By Dick Ti Tung

INTRODUCTION

The term FS(1l2 n ) is the smallest output level that
the DAC can resolve and it is known as the 1 LSB
output level change. It is universal practice that the
input code of a DAC is written in the form of binary
integer with the fractional nature of the corresponding number understood.

In recent years the development and rapid reduction
in cost of digital integrated circuits have resulted in
an explosion in the applications of digital processing
systems in the area of data acquisition and automatic
process control. The need for a building block,
such as the digital-to-analog converter (DAC), which
interfaces the, digital system with the analog world,
is evident.

As an example, the transfer function of an ideal
3-bit binary DAC is plotted as shown in Figure 1.
Since a 3-bit DAC has only 8 discrete input codes
which correspond to 8 different output levels (ranging from zero to 7/8 FS), no other output levels can
exist and it is plotted as a bar graph. The line that
connects the Zero and FS is called the Gain Curve.

The purpose of digital-to-analog conversion is to
produce a unique but consistent analog quantity,
voltage or current, for a given digital input code.
The most commonly used· input digital code to a
DAC is the natural binary number. A natural binary
number is represented as

OUTPUT
FS

N = An2n + An_12n-1 + ... + A121 + A020 +
A_12-1 + ... + A_n 2-n

1.
8

where the coefficients A i (for n )i )-n) assume the
values of "0" or "1" and is called a "bit". The left
half portion of the binary number N

GAIN CURVE .......... /

.2

:
!

/

8

An2n + An_12n-1 + ... + A121 + A020

A_12-1 + A_22-2 + ... + A_n2-n

....---:;

}8/

1l/

constitutes the fractional part of the number N. The
bit that carries the greatest weight (left most bit) is
called the most significant bit, or MSB. Similarly,
the bit with the smallest weight (right most bit) is
called the least significant bit, or LSB.

000

7

/

~

constitutes the integer part of the number N, whereas
the right portion

001

010

i
011

100

101

110

111 INPUT

Figure 1 - Ideal Transfer Function
Straight Binary (Unipolarl

The analog output of a n-bit binary DAC is related
to its binary number in the following manner:
Eo = FS(A_12-1 + A"'22-2 + ... + A_ n 2- n )

There are two other input codings associated with
binary DACs known as Bipolar codes, which are
offset binary and two's complement binary codes.
The offset binary code is obtained by offsetting the
binary code such that the half-scale code, 10 ... 0,
becomes zero. And the two's complement code is
achieved by inverting the MSB of the offset binary

where the term FS is defined as the nominal FullScale output of the DAC and it is known as the unreachable Full-Scale. It is easy to see that the actual
Full-Scale output of the DAC, EFS, with all the
input bits "1" is

= FS(2- 1

+ 2-2 + . . . + 2- n )

it)

....W

No. 522

EFS

N
N

= FS(1-2- n ).

10-53

0:
D.

II(

TERMINOLOGY
code such that it is mathematically consistent with
computer arithmetic. The transfer functions for the
3-bit DAC with offset binary input code and two's
complement input code are plotted as shown in
Figure 2 and Figure 3, respectively. (The +FS 'and
-FS limits are used for easy interpretation of Bipolar
operations. They are not confined by the previous
definition of FSJ
I

In practical DACs, the zero output level may not be
exactly zero (offset error), the range from zero to
FS may not be exactly as specified (gain error), the
differences in output levels may not be changing
uniformly (nonlinearity), and so on. In selecting a
DAC for a given application, some characteristics
may ha've to be weighted more than the others.
An understanding of some of the terms and characteristics involved in D/A conversion is helpful in
choosing the correct part.

OUTPUT
+FS

000

001

010

011

'--''-.--'rO~~--~--~~

100
_!01

J
-4

-~

_______ -F:
Figure 2 - Ideal Transfer Function
Offset Binary (Bipolarl

Least Significant Bit (LSB) - The digital input bit
carrying the lowest numerical weight (1/2 n ),; or the
analog output lev,el shift associated with 'this ,bit
(FSR/2 n ) which is the smallest possible analog output
step.
Most Significant Bit (MSB) - The digital input bit
carrying the highest numerical weight (1/2); or the
analog output level shift associated with this bit. In a
binary DAC the MSB creates a 1/2 FSR output
level shift.
Resolution - An indication of the number of possible
analog output levels a DAC will produce. Usually,
it is expressed as the number of input bits. For
example, a 12-bit binary DAC will have 212 = 4096
possible output levels (including zero) and it has
a resolution of 12 bits.
Absolute Accuracy - A measure of the deviation of
the analog output level from the ideal value under
any input combination. Accuracy can be expressed
as a percentage of full scale range, a number of bits
(n bits accuracy means a magnitude of 1/2 n FSR
possible error may exist), or a fraction of the LSB
(if a DAC with n-bit resolution has 1/2 LSB accuracy
the magnitude of the possible error is 1/2(1/2 n FSR)).
Accuracy may be of the same, higher, or lower order
of magnitude as the resolution. Possible error in
individual ~bit weight may be cumulative with combination of bits and may change due to temperature
variations. Usually, the accuracy of a DAC is expressed in terms of nonlinearity, differential nonlinearity, and zero and gain drift due to temperature
variations.
Nonlinearity (linearity error) - A measure of the
deviation of the analog output level from an ideal
straight line transfer curve drawn between zero and
full scale (commonly referred as endpoint lInearity).
Differential Nonlinearity - A measure of -the deviation between the actual output level change from the
ideal (1 LSB) output level change for a one bit
change in input code. A differential nonlinearity
of ±1 LSB or I'ess guarantees monotonicity; that is
the output always increases for an increasing input.

OUTPUT
+FS

010

all INPUT

Figure 3 - Ideal Transfer Function
Two's Complement (Bipolarl

Gain Drift - A measure of the change in full scale
analog output, with all bits 1's, over the specified
temperature range expressed in parts per million
of full scale range per oC (PPM of FSR/oC). It is
measured with respect to +250 C at high (TH) and
low (TLl temperature, and it is specified the larger
of the two representing worst case drift.
Offset Drift (Unipolar or Bipolar) - A measure of
the change in analog output,with all bits O's, over the
specified temperature range expressed in parts per
million of full scale range per oC (PPM of FSR/oC).
It is measured with respect to +250 C at high (TH)
and low (TLl temperature, and it is specified the
larger of the' two representing worst case drift.

10-54

Settling Time -' The total time measured from a
digital input change to the time the analog output
reaches its new value within, a specified error band,
Usually, the settling time is specified for a DAC to
settle for a Full-Scale code change (00 . . . o,to
11 . . . 1 or 11 . . . 1 to 00 ... 0) to within +1/2
LSB of its final value.

N
N

OUTPUT

Lt)

FS

W

2

I-

8

o
Z
n:
Q.

J!
8
5

8
Compliance - Compliance voltage is the maximum
output voltage range that can be tolerated and still
maintain the specified accuracy.

4

01(

8
1
8

2

The effects of gain error, offset error, nonlinearity,
and differential nonlinearity on the transfer functions
are plotted, respectively, as shown in Figure 4, 5,
6, & 7. A conversion chart which shows the number
of bits and its resolution is given in Table 1.

'8
1

8
OIL..--'-__-'---'__-'--_'----'-_..L--.J...
000 001

010

011

100

101

110

111

Figure 6 - Linearity Error

OUTPUT

FS
7

8

OUTPUT

.2

FS

8

5

8
4

'8
~

8

1.
8

1

'8

o

~~

000

__

001

~

010

__

L-~__- L _ _L-~__- L

011

100

101

110

111

Figure 4 - Gain Error

OIL..--'-_-'----'_-'--_'---L._..L---L000

OUTPUT

001

010

011

100

101

110

111

Figure 7 - Differential Linearity Error
(Non-Monotonicity)

FS
7

8

C/.)

'W
g:1-

6

'8

Table 1 - Conversion Chart



The typical data acquisition system is depicted in
Figure 3. The HI-506 multiplexer is used as an
analog input selector. Which is controlled by a
binary counter to address the appropriate' channel.
The HA-5330 is a high speed sample and hold.
Sample Hold Control is tied to the status (STS)
output of the H 1-774A, so that whenever a conversion is in process the S/H is in the hold mode.
A conversion is initiated by the clock input going low, and when the clock goes high the mux address changes. The mux will be acquiring the next
channel while the ADC is converting the present
input, held by the S/H. The clock low time should
be between 225ns and 6.5j..ls, with the period greater
than 8.5J.ls. With this timing RIC will be high at the
end of a conversion so the output data will be valid
"-' lOOns before STS goes low. This allows STS to
clock the data into the storage register. The register
address will be offset by one, if this is a problem
then a 4-bit latch can be added to the input of the
storage register. With a 100KHz clock rate each
channel will be read every 160J.ls.

COUNTER
(74191)

+1/2 LSB

DIGITAL

OUTPUT

~60nS(TYp)
-1/2 LSB

J

~CLOCK

Figure 1. Tracking ADC

en

SPANR

g:~

«0

DAC

This 16-channel data acquisition system is applicable
to industrial process control, and multi-channel panel
display. It can also interface with an intelligent terminal, such as a micro-computer system, to provide
multi-channel data conversion function. The offset
error and gain error of the data acquisition system
over the operating temperature range can be easily
compensated by proper programming.

z

'OACOUT

+v

!

By the same token, a 15-channel data acquIsition
system with offset correction could be easily incorporated as shown in Figure 4. Consider the case that
one of the analog input channels is dedicated to sense
the ground level, and its binary equivalent is stored in
latch register B in its complementary form to establish
a ground reference in real time. All the other analog
input channels will then be converted and stored in

-v

D
SAR

>

DIGITAL
OUTPUT

RB
":"

CLOCK

'---+

DATA READY

r - - ' \ H r - 6 0 n s (TYP)

J

~CLOCK
Figure 2. Successive-Approximation ADC

10-57

12-BIT
ADC
HI-774A

HI-506
HA-5330
16
CHANNEL
MUX

STORAGE
REGISTER

8tH
CLK
SELECT

BINARY
COUNTER

<1<.._-------4>-- CLOCK
INPUT

t1
t2

=

MUX SETTLING

=CONVERSION INITIATED

Figure 3. 16 Channel Data Acquisition System

HI-50616
CHANNEL
MUX

HA-5330
StH

HI-774A
12-BIT
ADC

RtC

STS

TIMING AND
CONTROL

Figure 4. 15 Channel Data Acquisition System with Offset Correction

10-58

BINARY
ADDER

12 BIT
OUTPUT

APP
NOTS

FOR YOUR INFORMATION

it)

N

it)

w

t-

o
Z
n:
Harris Analog c(D.

No. 525

HA-5190/5195 FAST SETTLING
OPERATIONAL AMPLIFIER
By G. Cotreau, D. Jones, R. Whitehead

INTRODUCTION
The military temperature range HA-5190 and its
commercial temperature equivalent, HA-5195, are
monolithic operational amplifiers featuring±200V Ips
slew rate, 150mHz gain-bandwidth-product, and 70ns
settling time. Similar performance has previously
been available only in more costly modular and hybrid
amplifiers, which require much higher bandwidth aDd
slew rate to achieve the same settling time as HA5190/5195. Since it exhibits a classical -6dB/octave
rolloff over most of its frequency range, remarkably smooth output wave forms are generated by HA5190 when reasonable care is employed.
Applications for this op amp include pulse, R F, and
video amplifiers, wave form generators, high speed
data acquisition and instrumentation circuits.

INSIDE THE HA-519015195

Figure 1. HA-5190/5195 Schematic.

Figure 1 shows the schematic of the HA-5190/5195
design. The schematic can be simplified to show the
AC signal path as shown in Figure 2.
The input stage consists of two symmetrical differential transistor pairs. The signal path for positive
going signals is 01, 02, and 03, while negative going
signals pass through 04, 05, and 06. The signal then
goes through the output stage (represented by the
voltage follower symbol) consisting of one PNP and
two NPN emitter followers.
In Figure 2. the compensation network is C1. C2. C3.
and R29. Th is network makes the ampl ifier system
appear as second-order critically damped. The scheme
produces the dominant pole plus two zeros. The zeros
are positioned to cancel the effects of undesired poles
developed by the Ft of the transistors.

Figure 2. Simplified HA-5190 Schematic.

10-59

CONSIOERATIONS FOR PROTOTYPING
When using the HA-5190, high frequency layout
techniques are recommended for bread-boarding.
The device should be mounted through a ground
plane. If an IC socket is to be used, Teflon types
are recommended. Feedback components should
be mounted between Teflon insulated standoffs
located as close as possible to the device pins.

(a) Gain =-1

The input impedance characteriStic of the HA-5190
is such that the closed loop performance (DC and AC)
will depend on both the feedback component ratio
and the actual impedance presented to each amplifier
input. For best high frequency performance, resistor
values for feedback networks should be limited to a
maximum of 5K ohms (preferably less than 1 K ohm).
Film type resistors are recommended. Power supply
decoupling with ceramic capacitors from the device
supply pins to ground is essential.

",

(b) Stabilization using ZIN.

It is recommended that optimum circuit values for a
particular application be developed through experi-mentation using amplifiers from several production
runs. The PC artwork in the vicinity of the HA5190 should be prototyped early to determine any
sensitivites to layout.

Cl1000pF

(e) Gain

= +1

OPERATION AT ELEVATED TEMPERATURES

~

HA-5190/5195 may be used without a heat sink up
to +75 0 C ambient. Above this temperature the power
derating is B.7mW/OC and a heat sink should be used.
THERMALLOY model 6007 heat sink is recommended. For temperatures up to -I-1250C, the thermal
resistance of the heat sink should be 30.6 0 C/W maximum.

~

(d) Stabilization using ZIN.

".

FREQUENCY COMPENSATION
HA-5190/5195 is stable in standard DC amplifier
configurations with closed loop gains exceeding +5 or
-4. At these or higher gains, optimum AC performance
can be achieved by keeping network resistor values as
low as is practical.
(e) Non-inverting gain stage.
Quite simple circuitry, as illustrated in Figure 3, gives
excellent performance for lower closed loop gains.
The compensation schemes use the amplifier's differential input impedance to reduce both the input and
feedback signals thereby raising the effective noise
gain approximately 14dB to a stable point on the
frequency response curve.

",

,

.---~---,
.

,
:

,

Inverting and non-inverting unity gain connections for
HA-5190 are shown in Figure 3 (a) and (c). R3 and
R5 serve only to balance DC voltage offsets due to
input bias current, and may be replaced with a short
for AC applications. C1 is not neccessary for stability,
but helps reduce overshoot and smooth the frequency
response. Settling time or frequency response can be
optimized (about 30mHz small signal bandwidth is
practical) by fine tuning component values.

C2

,:

(f) Integrator

Figure 3. Compensation 1 + ~
recommended when
R1

10-60

< 5.

R,

For closed loop gains between 1 and 5, reducing R 1
in Figure 3 (a) and (e) will raise the gain with minimum effect on bandwidth. However, in the inverting
configuration, R 1 determines the input impedance,
and it may be more practical to raise R2 at the expense of bandwidth. In Figure 3 (e). R4 and R5 may
be reduced as gain is increased and removed entirely
at gai ns greater than +4.

V+ INPUT

R2

It)

N

It)

R5 ~--.I'.IV'-"1""""I1/
R4

~50Kn

W

ZOOKn

t-

v-

O

z

(b)
RANGE OF ADJUSTMENT FOR BOTH NON-INVERTING (lEFT) AND INVERTING
AMPLIFIERS (RIGHT) DETERMINED BY PRODUCT OF VSUPPLY AND R3/R4 RATIO.

AV=l+_A_'_

For applications requiring 100% feedback at high
frequencies, such as integrators and low pass filters,
HA-5190/5195's compensation scheme should be
thoroughly evaluated through experimentation. The
circuit in Figure 3 (f) is quite stable, using the two 1 K
ohm resistors.

n:

D.

II(

R2+ R3

Figure 4. Offset Nulling.

SUGGESTED METHODS FOR
PERFORMANCE ENHANCEMENT
To avoid compromising AC performance, the HA5190 design does not include provisions for internal
offset adjustment.

(a)

..

VALUES SHOULD BE DETERMINED

EXPERIMENTALLY FOR OPTIMIZED
PERFORMANCE.

The circuits in Figure 4 (a) and (b) show two possible
schemes for offset voltage adjustment.

v+

Figure 5 (a) and (b) uses the inherent qualities of the
F ET to reduce input bias currents by several orders of
magnitude and raise input impedance to thousands of
megohms. Both circuits are shown in the unity gain
follower mode. Circuit gain can be implemented using
normal feedback techniques. To optimize for speed,
care should be taken in layout. Experimental results
yielded slew rates of approximately 130V l/1s.

(b)

Rl AND

v-

R2~15K"

INPUT FETS ARE MATCHED PAIR 2N5564

Figure 5 (c) illustrates a composite inverting amplifier
which greatly reduces DC errors due to the HA-5190
input bias current and gain, while retaining superior
settling time. The 0 dB frequency of the integrator
section approximates the open loop low frequency
pole (",2.5kHz) of the HA-5190. This circuit might
also be connected as a current-to-voltage amplifier
for use with a high accuracy, high speed DAC.

AF
AIN

t
10Kn

Figure 6 shows a composite amplifier scheme for
boosting output current drive of the HA-5190/5195.
The circuit gain (shown AV = 5) can be adjusted using
normal feedback systems. HA-5190 used in conjunction with HA-2630 can drive 50 ohm coaxial cable with
10 volt peak-to-peak signals at speeds up to 200V I J. s.

(e)

Figure 5. Reducing Input Bias Currents.

APPlICA TIONS

OUT

INTRODUCTION
HA-5190/5195 represents an ideal building block for
high speed, precision data acquisition systems and for
video pulse amplification. Although this amplifier can
be used in a wide variety of other applications, the
ones to be discussed show where it can be used most
advantageously.

,Kr!

Figure 6. Boosting Output Current.

10-61

Application 1 Fast DAC Output Buffer

GAIN

The circuit at right illustrates the HA-5190's usefulness as a high speed DAC buffer.
The amplifier operates as a current-to-voltage converter/output buffer to the HI-5610 which is a precision 10 bit DAC with output current settling time
less than lOOns. The voltage divider on the noninverting input serves to null any DC errors introduced
into the system. The amplifier maximizes speed of the
system since its dynamic performance exceeds that
of the DAC.

Application
1

l~

L...,tW---..

-15V

Application 2 High Speed Sample/Hold
+15V

Sample/Hold circuits are used in many areas of data
acquisition systems such as de-glitchers for D/A converters and input stages for successive approximation
A/D converters.

lKn

The circuit at right uses the speed and drive capability of the HA-5190 coupled with two high speed
DMOS FET switches.

Application
2

The input amplifier is allowed to operate at a gain of
-5 although the overall circuit gain is unity. Acquisition times of less than lOOns to 0.1 % of a 1 volt input
step are possible. Drift current can be appreciably
reduced by using F ET input buffers on the output
stage of the Sample/Hold.

.. OPTIONAL (SWITCH DRIVE ENHANCEMENT)

Application 3 Video Pulse Amplifier/75 ohm
Coaxial Driver
HA-5190/5195 is also well suited for video pulse applications. The circuit at right could be found in various types of video broadcasting equipment where 75
ohm systems are commonly employed.

n

3

HA-5190 can drive the 75 ohm coaxial cable with
signals up to 2.5 volts peak-to-peak without the need
for cLlrrent boosting. In this circuit the overall gain
of the circuit is approximately unity because of the
impedance match ing network.

Application 4 Output Limiter
HA-5190 is rated for ± 5 volt output swing, and saturates at ± 7 volts. As with most op amps, recovery
from output saturation ls slow'compared to the amplifier's normal response time; so some form of limiting,
either of the input signal or in the feedback path, is
desirable if saturation might occur. The circuit
above illustrates a feedback limiter, where gain is reduced if the output exceeds ± (Vz + 2Vf). A 5 volt
zener with a sharp knee characteristic is recommended.

Application

4

10-62

:rrT:'~

120

Application

RIN

75

n

FOR YOUR INFORMATION

CD
N

II)

w

I-

o
Z

Harris Analog

No. 526

VIDEO APPLICATIONS
HA-S190/S19S
By L. E. Garner

INTRODUCTION
Offering superior performance in video and RF circuits, the HA-5190/5195 family can be used effectively in the design of television broadcast studio
equipment, test instruments, and monitoring or
surveillance TV systems. A very high 200V /!J.s slew
rate, a full power bandwidth of 6.5MHz, and a fast
settling time of only 70ns (typ) are but three of the
unique characteristics which make these devices
ideal for critical wideband video and RF applications.
Other features include true differential operation,
excellent stability with gains ~5, and complete freedom from latch up, the latter a result of the exclusive
HARRIS dielectric isolation process combined with
optimized chip design and layout.

VIDEO RESPONSE TESTS
Referring to Figure 1, the test video ampli'fier comprised an HA5190/5195 op amp, BNC coaxial input
jack J1, input level control R1 shunted by impedance
matching resistor R2, input series stabilization
resistor R3, gain control network R4-Rgain, series
output limiting resistor Rs, and BNC coaxial output
jack J2.
Operational power was supplied by a
well regulated and filtered dual line operated
power supply,

The op amp family can be used, typically, as studio
tape head, test instrument, and video camera preampIifiers, as buffers, as broadcast relay Iink repea~ers,
as coaxial line drivers, and as cable or industrial
system video repeater and bridging amplifiers. Extremely versatile, the devices can be operated effectively in AGC and dc gain controlled configurations
as well as in fixed gain designs, and are fully capable
of driving low impedance loads.

R4

Rgain

When used in standard video amplifier configurations,
the HA-5190/5195 devices easily meet or exceed the
performance tolerance specifications of applicable
current FCC (NTSC) composite TV signal standards
as well as the requirements of EIA Tentative
Standard RS-170A.

1Kn

Figure 1-Test Video Amplifier

1r::m~~II~R
147AVIDEO
TEST
GENERATORS

VIDEO PERFORMANCE
The overall color video performance of the HA 5190/
5195 family was confirmed by checking a number of
standard devices.
Tests were made to determine
both video response and signal/noise ratio under
typical operating conditions. The basic video amplifier circuit illustrated in Figure 1 was used for the
tests, with the actual procedures abstracted from those
described in EIA Standard RS-250-B. The general
test setup is shown in Figure 2.

75n

TEST
AMPLIFIER

(FIGURE 11

Figure 2-Video Response Test Setup

10-63

a.:a..

Ot---.....I

RF AGC AMPLIFIER

R6

GAIN SET

10Kil

Designed. and checked as a buffer for the head preamp of a studio video tape recorder, the circuit
shown in Figure 7 functions ·as a wide band adjustable AGC amplifier. With an effective bandwidth
of approximately 10 MHz, it is capable of handling
RF input signal frequencies from 3.2 to 10MHz at
levels ranging from 40mV up to 3V p-p.

-12V

Figure 7-RF AGC Amplifier

v-p-p
R4

VIDEO
INPUT

AGe action.is achieved by using opto coupler/isolator
OCI as part of the gain control feedback loop. In
operation, the positive peaks of the amplified output
signal drive the eCI LED into a conducting state.
Since the resistance of the eCI photosensitive
element is inversely proportional to light intensity,
the higher the signal level, the lower the feedback
resistance to the op amp inverting input and hence
the greater the negative feedback, thereby lowering
stage gain.
Any changes in gain occur smoothly
because the inherent memory characteristic of the
photoresistor acts to integrate the peak signal inputs.
In practice, the stage gain is adjusted automatically
to a point where the output signal positive peaks
are approximately one diode drop above ground.

'e

GAIN SET control R5 applies a fixed dc bias to the
op amp non-inverting input, thus establishing the
steady-state zero input signal current through the
eCI LED and determining the signal level at which
AGC action begins.
In experimental tests under
large signal conditions (i.e., EIN = 3V p-p), a GAIN
SET value of -0.26V provid.ed unity gain, while a
value of -1.55V yielded on AV of 2.7 , with a flat
response to 5.0MHz at both levels.
Under small
signal conditions (i.e:, EIN = 40mVl. gains from 8
to 50 could be achieved as the GAIN SET value
was adjusted from 0.65V to -80mV. At AV = 8,
the frequency response was flat to 5MHz, while at
AV = 80, the response was limited to that of the
HA-5190/5195.

VIDEO

11iS!

Rl
1Sil

OUTPUT

r
R6

5.6K!l

-'2V

--,

,--I

I

I

0'

R1

2N3904

10K!}

: R8>O~-~~~~

,

I

,

,

I

,

I

-

l_~~11!

I

_J

C3
O.1Il F

+'2V
OC1-CLAIREX eLM 8500/2

C1. C2 - TANTALUM TYPES

Figure 8-DC Gain Controlled Video Ampliflar (Analog Multiplierl

DC GAIN CONTROLLED VIDEO AMPLIFIER
Suitable for use in virtually any application requiring
a variable gain wideband or video amplifier, the
circuit illustrated in Figure 8 employs a cascaded
op amp integrator and transistor buffer (Q1) to drive
the amplifier gain control element.
Except for a
simple modification, the HA-5190/5195 stage is
connected as a conventional non-inverting operational amplifier, and includes input and output
impedance matching 'resistors R1 and R4, respectively, series stabilization resistor R2, and power supply bypass capacitors Cl and C2. The circuit differs
from standard designs in that the gain control network includes a photoresistor, part of eci.

The effective AGC range depends on a number of
factors, including individual device characteristics,
the nature of the RF drive signal, the initial setting
for R5, et al.
Theoretically, however, the AGC
range can be as high as 4000:1 for a perfect op amp,
for the eCI photoresistor can vary in value from
1 Megohm with the LED dark to 250n with the
LED full on.

10-66

Referring to the schematic diagram, opto coupler/
isolator OCI contains two matched photoresistors,
both activated by a common LED.
The effective
resistances offered by these devices is inversely proportional to the light emitted by the LED.
The
greater the current through the LED, then, the more
intense its light emission, and the lower the effective
values of the photoresistors. One photoresistor is
part (with R3) of the HA-5190/5195 gain network,
while the other forms a voltage-divider with R6
to control the bias applied to the integrator noninverting terminal.

ACKNOWLEDGEMENTS
A.

B.

In operation, the dc voltage supplied by GAl N
control R8 is applied to the integrator inverting
input terminal through input resistor R7. Depending
on the relative magnitude of the control voltage,
the integrator output will either charge or discharge
C3.
This change in output, amplified by Q1, con·
trois the current supplied to the OCI LED through
series limiting resistor R5.
This action continues
until the voltage applied to the integrator noninverting input by the R6-photoresistor voltage
divider matches the control voltage applied by
R8 to the inverting input.
At the same time, of
course, the ratio of the R3-photoresistor gain network
is changing, adjusting the op amp stage gain.
As
the control (R8) voltage is readjusted, the OCI
photo-resistances track these changes, automatically
readjusting the op amp gain in accordances with the
new control voltage setting.

J. Carl Cooper of HARRIS CVS (Consolidated
Video Systems), 1255 E. Arques Ave., Sunnyvale, CA. 94086, cUlveloped the basic circuits
described herein and, in addition, devised
and executed the initial evaluation and performance tests.
Richard Whitehead and Robert Junkins of
HARRIS SEMICONDUCTOR, P.O. Box 883,
Melbourne, Fla. 32901, carried out additional
confirmation tests of circuit performance
and made other significant contributions
to this publication.

CD
N

lI)

W

I-

o
z

0:

c..



In (Max offset

2n1)

VP1
In(2)

40

zg

CHI

8,0VFS

2B

CH2

& 20V FS

HI-59DD
OR
HI-59DI

29 CLK IN
13 eLK OUT
10 SERIAL OUT
33 CE

CH15

CHID

•

10

":"

11

HI-5712
ANALOG TO DIGITAL
CONVERTER

31 SC
32 ST
MSB
22 t9 1

DIGITAL
eONTROL
INPUTS

DIGITA.L CONTROL
INPUTS
START CONVERT
STATUS

-U-

-+----+H+H++-+H+-..

AUTO ZSTROBE ....

BI+-"MS,.,B"-_ _ _--J
B2+----'-----'
. 3 + - - - - - - -.....

E~::::::::::::::::~~

Bl~E~~~~~~~~~~~~~

.B

.,0
B9

. ::;+..:L:::SB'--_ _ _ _ _ _ _ _-'-_'-----'

Figure 3 - Auto-Zero Analelg tel Digit81 Converter

10-72

Various configurations can be employed to minimize
parts count. Fully automatic offset correction is
added to the H 1-5900/H 1-5712 DAS component
set using only four additional I,C.'s as shown in
Figure 3. External digital logic or a microprocessor
selects a spare input channel which has been previously grounded.
Receipt of the Auto-Z strobe
initializes the auto-zero function by clearing the latch
to all zeroes, resulting in a D/A output of 32 LSB's of
positive offset.
The microprocessor then initiates
an analog to digital conversion sequence. The Conversion Complete status line of the A/D causes the
latch to strobe and store the digital offset correction
term to the D/A converter. The analog correction
term is then injected into the zero adjust pin of
the A/D converter. Care must be taken when injecting the correction term to this point on the A/D
since the ratio of RA/RB is affected by the impedance of the summing junction.

+125 0 C ambient. In no case did the offset after
correction ever exceed 1 LSB of the analog to digital
converter.

oC")
Lt)

W

t-

O
RS

RA

OFFSET
AFTER CORRECTION

147kn

O.5mV

OTO +20V

68Hl
82512

147krl

1.0mV

-5V TO +5V

58011

147kl1

1.0mV

-10V TO +10V

68W

147kn

2.0mV

HI-5712 INPUT
CONFIGURATION

o TO +10V

Table 1 - Offset Correction Accuracy

Along with the straight forward benefit of greatly
improved offset performance, this correction technique eliminates the requirement for any offset adjustments, either initially or during the operating
life of the DAS. In practice, the auto-zero function
need only to be used after system power is applied
or after a significant change in ambient temperature.
Therefore, high performance microprocessor-based
DAS systems reqUiring maximum performance can
employ this technique to improve accuracy with
minimal impact on throughput rate.

Table 1 lists the accuracy of correction for various
full scale input ranges. The offset after correction
listed in the Table is the maximum observed offset
when 10 different 5900's and 5712's were tested
at all temperature ranges between -55 0 C, and

10-73

Z

D.
D.

oct

APP
NOTS

FOR YOUR INFORMATION

Harris Analog

No. 531

ANALOG SWITCH APPLICATIONS IN AID
DATA CONVERSION SYSTEMS
By Richard Whitehead
and hold circuits. By moving the multiplexing task
to the digital domain, slower and lower cost AID
converters can be used.

INTRODUCTION
A choice of three approaches is available when implementing a data conversion system: 1). "buildfrom-scratch", 2) buy sub-systems and configure
a system, or 3) purchase a pre-engineered system
Also, as a matter
which meets the requirements.
of economics, the users of sensor-based data acquisition systems make it common practice to ensure
a maximum number of elements are shared in the
system. An invaluable tool used in this process is
the analog switch or multiplexer; The purpose of
this article is to focus attention on those parts of the
system which require analog switches and to emphasize the importance of relative operating parameters.

TYPES OF ANALOG SWITCHES
The most commonly used types of analog switches
found in today's data conversion systems are: reed
relay, JFET, and CMOS.
Reed relays offer low
ON and high OFF resistance and are capable of
handling very high voltages, but have slow speeds.
JFET switches have lower OFF leakage current and
are capable of very high speeds. CMOS switches,
'which are the most popular and widely used in multiplexer applications, have low OFF leakage currents,
good speed, and stable ON resistance under varying
input signal conditions.

IJASIC SYSTEM CONFIGURATIONS
SELECTING THE PROPER CMOS
ANALOG SWITCH

AID data conversion systems can be categorized into
two general groups: 1) low level signal conversion
(analog srgnals below 1 volt) and 2) high level signal
conversion (analog signals above 1 volt).
Within
these categories, four basic data conversion configurations are illustrated to point out the advantages
of using analog switches.

The data conversion system error budget should be
used to narrow the field of CMOS analog switches
suitable for the application. Primarily, the speed of
the switch must be consistent with the systems's
sample rate requirements without introducing un~
acceptable transfer error.
Significant dynamic
errors inherent to CMOS analog switches are OFF
channel leakage current and a settling time value
dictated by the device's ON resistance and its inherent capacitance. Figure 2 shows the equivalent
of a CMOS analog switch giving all of the inherent
and distributed properties which may become the
source of unwanted system errors.

Conditioning the analog signals prior to multiplexing
(Figure 1A) is the most popular system arrangement
and is both efficient and capable of high performance
This configuration, which shares the level
signals. Figure 1B represents a more austere approach
resulting in lower cost and decreased performance.
This type is useful in less demanding applications
such as processing high level signals.
To process
multichannel, single event information such as
wind tunnel or seismographic measurements the
arrangement shown in Figure 1C is most likely to
be used.
This configuration represents a more expensive, less efficient approach due to the decreased
number of shared elements. Figure 1D shows the
elimination of the analog multiplexer and sample

Other system restrictions may further narrow the
field of candidates suitable to performing the switching task. These restrictions could include,low power)
budget, hostile environment, cost, alternate sourcing, and package density. It's poSsible that all of

10-74

these restrictions could occur, and this situation
mat influence the user to seek a compromise solution to his problem.

HIGHLIGHTS

Fortunately, CMOS analog switches consume very
little power and only the most demanding power
budget would feel the strain of their power requirements. If the poerating environment of the device
includes high voltage spikes, excessive noise pickup,
andlor power supply interruptions, the selection
should be narrowed to the internally protected
analog multiplexers such as the HARRES HI-506AI
507 A or the H 1-546/547. These multiplexers come
with guaranteed overvoltage specifications which
engance the reliability of the data conversion system.
They also insure output signal integrity while an
overvoltage condition occurs on an
unselected
channel. It should also be ensured that the CMOS
analog switch selected does not exhibit any inherent
latch-up tendencies. The Harris dielectrically isolated
CMOS analog switches offer latch free operation.

,....
C")
II)

In AID data conversion systems analog switches
are mainly used as multi-channel multiplexers
to increase system efficiency through shared
elements.

I-

CMOS analog switches are the most widely used
in data conversion systems.

Il.

w

o
Z

a:

+18V

-15V

-10V

QUESTION #7:
Figure 5. Varying the Supplies to Meet the VIN
.
V Supply Requirements

<
HI-5043

The device pins mentioned above have their own
individual functions even though they are all associated wth the logic reference circuits of their respective designs.
For the HI-201, the VREF pin is
the terminal which establishes the logic threshold
levels for which the switch will change state. Although it is normally left open when driving from
+5V logic (DTL or TTL), it can be connected to a
higher supply in order to raise the switching threshold
levels when driving from CMOS Logic greater
than 5 volts.
The VREF pin enables the user to
change from TTL to CMOS Logic.

SINGLE SUPPLY OPERATION
Single supply operation is a topic which is discussed
frequently and the following are examples of typical
questions.
QUESTION #5: Can the switch be operated at a
single power supply?
QUESTION #6: What is the minimum
supply possible?

and

What is the difference between
the VL and VR pins on the
VREF pins on the HI-201 ?

power

The reference circuit of the H1-50XX series
of switches is different from the H1-201, which
accounts for the VR and VL pins.,):ven though the
VR terminal is brought out on the package, it is
recommended that this pin be grounded.
This
terminal establishes the ground for the internal ref-

Usually engineers with critical power requirements
request single supply operation. An example would
be battery operated applications such as portable
equipment.
In these cases the designer is limited
to single supply, low supply or both.

10-80

N

C")
It)

erence circuit. The VL pin performs a similar function to the VREF pin on the HI-201. It is normally
connected to 5 volts for TTL logic but can be tied to
a higher supply for CMOS levels. This effectively
raises the switching thresholds to accomodate the
higher CMbs level.

w

I-

o
z

0:

The next question is easily the most frequently asked
question about HARRIS HI-50XX series of switches.

Q.

1-

For the sample and hold circuit, shown in Figure 5,
a common problem is sample to hold offset error.
It is caused by the same mechanisms discussed
for the small signal application, but in this case the
charge is transferred to the hold capacitor and an
offset voltage is created. The voltage is determined
by the following relationship. V = Q/CH.

o
V+

POSITIVE SUPPLY VOLTAGE (VOLTS)

SWITCHING TIME VS. V+POSITIVE SUPPLY VOLTAGE
v-=ov

TA = 250(;

2

,

I\\'ON

,~ r-..

+5V

v+ -

+10V

+15V

Figure 4 - Charge Transfer

POSITIVE SUPPLY (VOL TSI

10-84

rt>

I

+

those junctions are forward biased, a fault condition
exists where the signal is passed through the parasitic
transistor. This is what occurs if the power supplies
Depending on the polarity of the
go to ground.
input signal, either the N or P channel FET parasitics
will be forward biased and the signal passed through
the switch.

~-T'--oO OUT

~H~

I

Figure 5 - Sample and Hold
Charge injection can create problems in the type of
applications just described. A typical curve of the
HI-300 series charge injection performance is shown
in Figure 6 as an aid to designing in these type of
circuits.

u5 0

z

...240
:cl

30

IN

""'

'~" 20
d 10

........ .........

:J:

+15

10

-5

0

+5

RIN -

s

D

OUT

on

CL= lO,aOOpf

+10

tO
Z

I

IMPEDANCE
INDUCTANCE
PER FOOT

PER FOOT
AT 60Hz
AT 10KHz

a.D064n
O,0102S1

a.016m
0.0257.11
0.041.11
a.066H
0.105.11
O.l68n

O.0235S1
O.0254S1

o

.I

0.0288.11

O.034Sfl
O.048B~1

a. TWO POLE SECTION

0.071an
O.llon
0.171.11

FIGURE 7. Impedance of Electrical Connections, +20°C

As an example, suppose the ADC in Fig. 1 has
12-bit resolution, and the system accuracy is to be
± 1;' LSB (± 1.2mV). The interface logic might draw
100 mA from the + 5V supply. Flowing through six inches of #24 wire, this current produces a drop of
1.2BmV; more than the entire error budget. Obviously,
this digital current must not be routed through any
portion of the analog ground return network.

b. THREE POLE SECTION

FIGURE 9. Butterworth Low-Pass Filters

PROGRAMMABLE GAIN AMPLIFIER
(PGA)

FILTERS
The presampling or anti-aliasing filters shown in
Fig. 1 are normally required with high-level signals of
significant bandwidth, especially if the signal is to be
reconstructed by a digital-to-analog converter after
processing. If low level signals require a passive filter,
the differential configuration of Fig. B preserves some
degree of impedance balanceonthe line.

Unless the ratio of highest to lowest signals an·
ticipated on any channel is:s 2, some form of
programmable gain amplification is desirable bet·
ween the multiplexer and A-D converter. Without this
variable gain block, the MSB's are idled one after
another as input level decreilses. Although the
resolution of an n-bit converter remains a constant
FS/2 n by definition, resolution referred to the input
level is decreasing (FS = Full Scale).
ConSidering resolution as referred to the input
level, a 12-bit converter digitizes an input of .06FS to
only B bits. The full 12-bit resolution applies only for
VIN;;;' FS/2. Therefore to fully utilize the converter, gain
shou Id be added as necessary before each conversion, to meet the condition FS/2:=;VIN:=;FS. Then the
amount of gain introduced by the PGA is noted by the
computer to keep track of the actual input value.
Three other services are performed by the PGA:
1. Buffering: Prevents a loading effect due to the
multiplexer's ON resistance.
2. Differential to Single-Ended Conversion:
Necessary.for the majority of Track (or Sample) IHolds
and A-D converters.
3. Common Mode Rejection (CMR). When con·
nected to the output of a differential multiplexer, the
PGA's differential input rejects the common mode
voltage accumulated by a signal transmission cable.
Fig. 10 shows a subtractor or "pseudo-differential"
PGA suitable for wideband signals with low common
mode content. In this circuit, CMR is limited by
precision of the "K" ratio and variations in the channelsource impedance.

R

FIGURE 8. A Passive, Two Pole, Low Pass,
Differential Input Filter

A low-pass Butterworth response is best for the
channel bandlimiting filter in most data acquisition
systems. The Butterworth filter output decreases
monotonically with frequency, though this attenuation is very slight within the passband. Other
filter types produce ripple in the passband, whose
amplitude degrades accuracy unless expensive, high
tolerance components are used.
Butterworth is not the most linear phase
response, and if signal group delay is critical an ellip-

10-91

=

K*R

DIFF MUX

System Sample Rate
(Highest Channel Rate)
X (Number of Channels)
- --Also, a very high sample rate is required to
preserve the high frequency content of a transient
event on a single channel. The most commonly encountered requirement though, is a multichannel DAS
(see Fig. 1) with a modest bandwidth on each channel.
For example, each data source. might be an accelerometer with an output ranging through several
hundred Hertz.
Notice that the low and high bandwidth signals
just described cannot be handled efficiently with the
same system. A sample rate high enough for the
highest bandwidth channel will oversample the lower
bandwidth channels, generating unnecessary data.
High and low bandwidth data are best handled by
separate multiplexer/converter systems.
Presampling filters are essential to ensure accuracy in the sequence of digital samples representing a given channel. Since the multiplexer is a sam·
pier (as is the Sample/Hold and A-D Converter) this
means a separate filter dedicated to each channel
preceding the multiplexer. A single filter following the
multiplexer would do the job, but its modest response
time wOuld form a bottleneck restricting the sample
rate. Guidelines are needed then, to relate a given
level of accuracy to data bandwidth, filter cutoff
frequency, and number of filler poles.
As mentioned earler, a filter limits the error due
to alias frequencies by restricting the bandwidth of
both signal and noise. Either acting alone or in concert may cause error, since alias frequencies arise in
several ways:
1. Overlap of the signal spectrum and the lower
sideband associated with the sampling frequency f S.
2. Overlap of the upper and lower sidebands
associate,d with any two consecutive harmonics of fs.
3. Overlap of any sideband with wideband nOise
from the data channel.
A band-reject filter would control case 1, but a
low-pass type is needed to handle cases 2 and 3 as
well. Again, the Butterworth response is preferred in
most applications, but it does offer increasing phase
shift and gain error for frequencies approaching the
cutoff (-3d B) frequency. This cutoff should be set no
higher than necessary for acceptable gain error in
the highest signal components. A higher cutoff will
only include unnecessary noise bandwidth.
Finally, for a given accuracy specification such
as ± V. LSa, a tradeoff may be made between the
sample rate and number of poles. These poles usually
come from the filter, but the number may include any
pole(s) inherent in the transducer, provided they occur
at an acceptable location relative to, the cutoff
frequency.
Fig. 12 shows aliasing error due to the signal
spectrum alone vs sampling rate for different numbers of poles. The horizontal axis is normalized to
Sampling Frequency/Cutoff Frequency. Notice that a
2-pole filter requires a sampling frequency 30 times
the filter cutoff frequency, just to obtain 1 % accuracy. For ± V. LSB error in a 12-bit system
(± .01 %), a 5-pole filter requires sampling at 11 times
the cutoff frequency. Remember, Fig. 12 applies bnly
to the signal spectrum. Noise will cause some additional aliasing error.
Clearly, Nyquist's Sampling Theorem is not a
practical guide for sampling rate in real applications.
Actual (as opposed to hypothetical) filters cannot
bandlimit a signal sufficiently to permit the
theoretical minimum of two samples per cycle of
highest Signal frequency.

R

•
R

* K VALUE MAY BE SWITCHED FOR
PROGRAMMABLE GAIN.

FIGURE 10. Subtractor or Pseudo-Differential PGA

Fig. 11 is the full differential PGA, necessary for
low-level, high common mode signals. This version offers the highest gain accuracy and for high gain, the
best CMR.
DIH MUX

K·R

*

VARY K TO CHANGE THE GAIN.

FIGURE 11. Full Differential PGA

The PGA normally precedes the Track/Hold, since
the PGA would amplify any error introduced by that
device. This order must be reversed to implement an
auto-range capability, because the signal voltage
must be held at the PGA inDut for the duration of an
auto-range subroutine by the computer. Such an
algorithm consists of:
• Set PGA gain
• Trigger a conversion
• Note RESULT
• Iterate until (FS/2 ~ RESULT::S FS)

SAMPLING RATE
Throughput rate for a DAS may be defined as the
maximum number of digital samples per second that
it can produce without exceeding its specified limit
for accuracy. The system may run at a lower speed to
avoid generating redundant and useless data; but if a
waveform of significant bandwidth is to be reconstructed from the digital samples, then "the higher the
better" is generally the rule for sampling rate.
The required rate is often higher than one would
suppose. For example, using the criteria of data bandwidth alone, a very low sample rate is required for
the slowly changing voltage outputs from a solar
panel. Once per minute for each channel might be
enough. With 60 channels though, the rate required is
once per second. In addition, one might require a
maximum of one second for notice of failure on any
channel, boosting the required sample rate to 60
samples per second. In this manner low bandwidth
channels may require a high speed DAS, according to
the relationship:

10-92

APP
NOTS'

FOR YOUR INFORMATION

co

C"')
II)

w

I-

o
z

Harris Analog

No. 538

MONOLITHIC SAMPLE/HOLD COMBINES
SPEED AND PRECISION
By Tarlton Fleming

INTRODUCTION
operate in an existing HA-2420 socket if pin 6 is
grounded, preferably to the system signal ground.

A new Sample-Hold amplifier from Harris Semiconductor offers the best combination of speed and accuracy available in a monolithic device. It was
developed for moderate to high speed applicationsand particularly as an input for successive-approximation AID converters wh ich perform a precise
conversion in 30 microseconds or less. This secondgeneration design includes a 100pF MOS hold capacitor, and offers a 1.0 microsecond acquisition time
along with high accuracy over the commercial and
military temperature ranges.

The HA-5320 delivers optimum performance when
used as intended - relying on the internal 100pF
hold capacitor alone. At +75OC this capacitor allows
only 19J..LV of droop in 15J..Ls.
The Droop Rate is
proportional to Drift Current, which increases with
temperature (Figure 3). Droop may be reduced by
adding external cpacitance CH as shown in Figure 1B.
This extra capacitance will reduce the bandwidth
(Figure 5) and affect other parameters as shown in
Figure 4. Also, a capacitor of value 0.1 CH should
be added at pin 8 to reduce output noise in the Hold
mode.
Whether operating with additional hold
capacitance or not, an HA-5320 offers a considerable
improvement in accuracy over the HA-2420. Particularly welcome is the elimination of variation in
"pedestal" error with input voltage. Further, the
residual pedestal error may be nulled to zero, yielding
great accuracy at a given temperature.

This new product, the HA-5320, can track a signal
indefinitely (like an op amp) while in the sample
mode. At the instant a digital HOLD command is
applied the corresponding signal level is held and
maintained at the output. The ratio of sample
(track) to hold time is set by the user, according to
the duty cycle of his digital control signal.
I

COMPARISON WITH EARLIER DESIGN
The HA-5320 retains the versatility of its predecessor, the popular HA-2420. That is, both have the
uncommitted differential inputs of an op amp,
allowing their Sample-Hold function to be combined
with many conventional op amp circuits. Their
circuit designs are different, though, producing
significant differences in performance. These are
best illustrated by describing the new device in
contrast with older HA-2420. Table 1 summarizes
the electrical characteristics of each, based on a
100pF hold capacitor.

UNITY·GAIN NONINVERTING CONNECTION
I-----------~

.

I

IN-

I

~+-(jVo

IN+
8tH

CONTROLo-~~--~

Both IC's are packaged.in a 14 pin DIP and operate
on :±:15V SUPPlies. The hold capacitor connections
differ as shown in Figure 1. Otherwise, the pinouts
are compatible to this extent: Either device will

Figure lA. HA-2420 Diagram

10-93

0:

D..

+!-'-OOUTPUT

(HA-4905)

The author wishes to thank design engineer Paul
Hernandez and senior technician Roger O'Brien
for their technical support.

2KU
RESETo--------~--"""'-......_O+5V

t..r
Figure 9. Positive Peak Detector

10-99

co

CO')
II)

w

tO
Z

c.:Q.
Vp

11 -

,(IDS

vP,

(IDs

ViDsS )+"2 ViDsS 1

£>IOSS
lOSS

£>1 OS

-

loS I

In this circuit, the mismatch of the drain load resistor sets the JFET drain current mismatch.

INSIDE THE HA-5170
The Harris technology has two important advantages. First, a unique ion implant process produces
JFET's with excellent matching and low l/f noise.
Second, the JFET's are in their own dielectrically
isolated islands which completely eliminates the
largest gate current component - the island to
substrate leakage.
The HA-5170 has two voltage gain stages. The first
consists of a differential JFET pair with resistor
loads which develops a gain of 10. The second is
a complete bipolar op amp with a gain of 30K. The
absence of active loads in the first stage insures that
the offset voltage, offset voltage drift and noise
voltage result exclusively from the input JFET pair.
When it comes to JF ET noise, bigger is better. The
JFET input noise voltage,both the l/f and white
components, is inversely proportional to the square
root of the gate area. Likewise, the input noise
voltage due to the drain load resistors is inversely
proportional to the square root of the resistance
value. The JFET's "weigh in" at a whopping 110
mil2 gate area with the resistors at 14K 11. This
results in typical noise voltages of 12nV /Hz at 1 K
Hz, 25nV /Hz at 10Hz and 1 J1 V p-p over the 0.1
to 10Hz frequency band.

£>IOS = _ £>R
lOS
R

Thus, the offset voltage can be zeroed by trimming
the load resistors. Since Vp has a large positive temperature coefficient, the offset voltage drift is normally degraded. By making the loads from composite resistors, thin film resistors in series with diffused
resistors, the temperature coefficient of the ll. R/R
ratio can be set to cancel both the trimming induced
drift and also the JF ET mismatch induce drift. This
makes the HA-5170 the first JFET op amp in which
trimming the offset voltage simultaneously trims the
offset temperature drift. Furthermore, the offset
voltage drift is reduced to even lower values when
the offset voltage is nulled externally with an offset adjustment pot. The 5170 has a typical offset
voltage of 100 J1 V, offset drift of 3 f.l V /OC (without
external offset nulling), and warm-up drift of only
20J1V.
The excellent dc performance of the HA-5170 is
complemented with dynamic ac performance never
before available from preCision operational amplifiers.
The 8V / JJ. slew rate and 5M Hz bandwidth allow
the designer to extend precision instrumentation
applications in bolth speed and bandwidth. The fast
settling time of the HA-5170 (typically less than

10-105

(/.)

'U.J

it I«0
:2

1.5J.Ls, settling to 0.01%) also makes it well suited
for fast precision A/D and 0/A converter designs.

APPlICA TIONS
Several applications which utilize the design features
and excellent performance of the HA-5170 are
described below.
Single Op Amp Instumentation Amplifier
The HA-5170 may be used as a single op amp instrumentation amplifier because of a unique design
feature which places the offset adjust terminals at
the juncture of two differential gain stages. The
instrumentation amplifier, as shown in Fig. 1, is
very simple and provides good performance features
such as low noise, low offset voltage, low offset
voltage drift and high input impedance at low cost.

VIN

,~

'rrt
-

1-11

5

4

,AA

T

R;

J

VOUT

inputs with a common mode
range of
-Vsupply+3V to +Vsupply+O.1V. If resistor values
R1 = R2 = 16Kn are used, for example, this circuit
will provide a closed loop gain of 200 with a 3dB
bandwidth of 20kHz and a THO < 0.5% (Vout
'" 2V p_p ). The gain linearity is typically better than
0.2%. However, the gain also changes about 0.2%/V
with both common mode and power supply voltages.
The gain T.C. is around 450ppm/OC but this can
be reduced to less than 200ppm/o C just by using
carbon film resistors which normally have negative
T.C.'s (approximately 260ppm/o C for 16Kn. re'sistors). Of course using resistors which have negative T.C.'s near 450ppm/OC will cancel gain T.C.'s
altogether. If a variable gain is desired, a trim pot
(in addition to R1 and R2) may be placed between
the offset adjust pins. Resistors R 1 and R2 and the
maximum value of the trim pot will set the minimum
gain. As the resistance of the trim pot is decreased,
the gain will increase proportionally to the inverse
of the trim pot resistance. This relationship of gain
and trim pot resistance is shown in Fig. 2.
This circuit also maintains all to the HA-S170's
excellent as and dc characteristics such as low offset
voltage, low offset voltage drift, low noise, and high
gain.

.. -v

~~~-+--r-1--+~r-+--r~--+--+~~

~R2

4~r-+-4-~-+-+~~~+-4-~~-7~~

L~

z4Wr-1--+~--t-1--+-f--r-~;~~r-4-~

(

~400~+-~-+-4--~+-~~~~+-~-+~H

VREF
Figure 1. Single Op Amp I nstrumentation Amplifier

§~~~~~~~~~~+-+-+-~
~

fil

The gain of the first differential stage is internally
fixed at a gain approximately equal to 12. A feedback resistor R1 connected between the output
(Pin 6) and the balance pin (Pin 5) will close the
loop around the second differential stage and set
its gain. The closed loop gain of the instrumentation amplifier varies directly with the value of R1
and is approximately
AVCL

=

12.5 V/V/Kn.

The minimum gain which can be applied is about
125 (R1 = R2 = 10K!"! ) because the current into
pins 1 or 5 must be limited to 4mA.
The second resistor (R2, which is connected between Pin 1 and a reference voltage) is used to
establish a reference voltage level for the output.
This reference voltage may be placed at ground
potential or may be variable for 4se as offset adjustment. The resistor R2 should also be matched
with R1 in order to maintain high common mode
and power supply rejection ratios. Standard 1%
tolerance r~sistors will typically provide 90dB rejection ratios.
The two inputs of the HA-5170, pins 2 and 3, may
now be used as high impedance, true differential

g~O~1--+--+--+I~~~1--t--~-r~--1--t1
u
/'1'
2~r-~+~~~~r-~~+-~-r-r~
2~~~~--+--+~r-1--t--r--r~--1--t1
200

L

o

100 200

300

~o

500

~o

700 800 900 1000 1100 1200

CONDUCTANCE BETWEEN, PINS 1 AND 5 Ipn)'

Figure 2. Closed Loop Gain Vs. Conductance Of Trimpot

SINE WAVE OSCILLATOR
The instrumentation amplifier circuit described above
can be easily modified to produce a low distortion
sine wave oscillator with voltage controlled amplitude
as shown in Fig. 3. The small changes in gain of the
instrumentation amplifier that occur with changes in
common mode voltage has been exploited here to
provide oscillator amplitude control with a voltage
source. Another unique feature of this circuit is
that is does not require any of the nonlinear components that most other sine wave oscillators require.

The phase lead network, which consist of R3, R4,
and C 1, cancel the phase lag through the ampl ifier
and oscillation occurs at the frequency where the
product of amplifier gain and voltage feedbac~ ex-

10-106

actly equals one.

AV=
where A
10k 11 ),
and W is
feedback

ative common mode voltages decrease amplitude.
A typical curve of amplitude versus common mode·
voltage is shown in Figure 4. The gain non-linearity
of the instrumentation amplifier is small, however,
and distortion less than 0.5% can be obtained over a
100Hz to 100kHz range.

The amplifier gain is expressed as

A
(1 +jwIWo)

is the dc gain (about 125 for R 1 = R2 =
Wo is the bandwidth (about 200K rad/s)
the frequency of oscillation. The voltage
is expressed as

Frequencies down to 10Hz can be achieved by
lowering Wo with a capacitor in parallel with R 1.

HIGH IMPEDANCE TRANSDUCERS
For their product to be equal to one, both of the
following must be true:

Wo

The oscillation amplitude is stabilized at the point
where the loop gain is equal to one by the small
gain nonlinearity of the instrumentation amplifier.

The HA-5170 is well suited as a preamplifier for high
impedance transducers, such as photo diodes and hydrophones, because of its high input im pedance and
low current noise. Fig. 5 shows a photo diode preamplifier circuit whose output voltage is approximately the photo diode current times the value
of R 1. When no light is present, the output of the
HA-5170 is
Vo= IND R1 + IN R1 +VNR +VN
where IND = Shot noise of diode
IN = Noise current of Op Amp
VNR = Noise voltage of resistor
VN = Noise voltage of Op Amp

>---+--....:0 VOUT
HP5082-4203
Photo diode

Figure 3. Sine Wave Oscillator With Voltage Controlled Amplititude

This operating point and initial amplitude is set by
the resistor divider network of R3 and trim pot
R4 (R4« R3). The amplitude can then be varied
by applying a common mode voltage (VIN) through
R3. Positive common mode voltages increase amplitude by decreasing gain non-linearity while neg-

1/

0

/

I
V

Figure 5. Photodiode Preamplifier

The signal to noise 'ratio is maximized when the rms
sum of op amp and resistor noise current sources is
equal to or lower than the noise current of the photo
diode. Noise voltage sources are converted to noise
current sources by dividing by R 1. The noise current
of the photo diode may be approximated by the shot
noise formu la 2q Id, where Id is the dark current, and
is in the range of 10- 13 to 10- 14 A//Ffi., depending
upon the choice of photo diodes. The rms sum of the
three sources is approximately 4 x 10- 14 AI [Hz
at 1 kHz, assuming R 1 = 20MI1. This rms summation
is approximately the same magnitude as the noise
current of the photo diode with the dominant noise
source being the resistor noise (about 2.9 x 10- 14
A/.[HZ). If a bipolar op amp were used instead of
the HA-5170, the noise current (typ. 4 x 10- 13
A/jHi.) would be much higher than the noise current
of the photo diode. The response time of the photo
diode can be improved by applying 5 to 20 volts of
reverse bias but the increased speed is achieved at
the expense of higher shot noise.
A resistor equal to the feedback resistor could be
inserted between the non-inverting input and ground
to reduce offset voltage. This is usually not necessary
since the output offset voltage would only be 600j1V
for a 20MI1 resistor.

.2
3
VIN (volts)

Figure 4. Oscillation Amplitude Vs. VIN

10-107

o

"I:t

."

W

I-

o
z

0:

a..

--...,+----~r,N
~50K.n

A,

SET: AV'

200Kn

-~=-3

R,

vA3
~100n

(.(

AV=l+~

(bl

R2+ R3

AV=-

~

RANGE OF ADJUSTMENT FOR BOTH NON-INVERTING (LEFT) AND INVERTING
AMPLIFIERS (RIGHT) DETERMINED BY PRODUCT OF VSUPPlY AND R31R4 RATIO.

Figure 3. b. STABILIZATION USIIIIG ZIN
Figure 2. OFFSET NULLING

As with many wideband, high speed devices, recovery from output saturation can be in the order
of microseconds.
HA-2539's saturation recovery
from its positive rail is of the classical variety where
voltage charges on the "body" capacitances of output devices must discharge before normal operation
can be resumed. Recovery from the negative rail
is similar to the positive rail recovery except during
saturation small signal oscillation may occur. This
oscillation is due mainly to a regenerative signal
coupled back to the input during saturation.

Reducing DC Errors
A composite amplifier scheme may be used to reduce
errors due to offset voltage and bias current. Figure 4 shows HA-2539 and HA-5170 in a composite
configuration which greatly reduces DC errors without compromising the high speed, wideband characteristics of HA-2539.
The HA-2539 amplifies signals above 40KHz which
are fed forward via C2 and R2. Resistors R4 and
R5 set the voltage gain at -10. The slew rate of this
circuit was measured at 350V / J.1 s. Settling time to
a 0.1 % level for a 10V output step is under 150ns
and the gain bandwidth product is 300MHz.

General Applications
FREQUENCY COMPENSATION

The HA-5170 amplifies signals below 40KHz, as set
by Cl and R 1, and controls the dc input characteristics such as offset voltage, d~ift, and bias currents
of the composite amplifier. Therefore, it has an
offset voltage of 100 J.1 V, drift of 2 J.1 VlOC and bias
currents in the 20pA range. The offset voltage may
be externally nulled by connecting a 20K pot to
pins 1 and 5 with the wiper tied to the negative
supply. The dc gains of the HA-5170and HA-2539
are cascaded which means that the dc gain of the
composite amplifier is well over 160dB.
The excellent AC and DC performance of this composite amplifier is complemented by its low noise
performance, 0.5J.1 V rms from O.lHz 100Hz,
and makes it very useful in high speed data acquisition systems.

HA-2539 is stable in standard operational amplifier circuits with closed loop gains exceeding +10
or -9. Keeping the network resistor values as low
as practical in these configurations should optimize
the dynamic performance.
Circuit configurations shown in Figure 3 may be
used to stabilize HA-2539 at closed loop gains less
than specified. Figure 3 (a) employs capacitance
to over damp HA-2539's response. Stable operation to gains of 5 are practical. Figure 3 (b) uti-

R410Kn
INPUT

-!OUTPUT

Figure 3.8. COMPENSATION BY OVERDAMPING

lizes the amplifier's differential input impedance
to reduce input and feedback signals thereby raising
noise gain to a stable point on the response curve.
Gains of -3 are practical.

Figure 4. COMPOSITE AMPLIFIER

10-110

Application Note 541

.....

•

Boosting Output Power And
IncI'Basing Output Signal Swing

II)

Figure 5 shows a cost effective method for increasing
output voltage swing or boosting power of HA-2539
while adapting the device to supply rails which exceed the absolute maximum ratings. The supply
rail values are limited only by the breakdown voltages
of the transistors used, provided R 1 through R4,
are set to limit the voltage at the device supply pins
to nominal supply values (±15V). Transistor selection should be limited to high fT (greater than
60MHz) types such as MPS-A06 and MPS-A56.
Physical layout properties may necessitate the use
of phase lead compensation, in which case CF may be
added.
It has unmeasurable distortion and very
low noise within the audio band.
r-----~-----o+v

R,
4K

R2
4K

I-

o

AV~30.8

A2
SET, AV",33.3

A,

Z

HA-2539t>-..--...----'\IV'v---......--j

,

2K

~c,

"--______-+ _J

60n

a.:a.
«

3pF to 5pF

APPLICATION 1 CASCADED AMPLIFIER SECTION

APPLICATION 2: VIDEO GAIN BLOCK
Video drivers and gain blocks .used in color video
. systems are most always required to have outstanding differential phase and differential gain specifications.
These requirements historically have
eliminated the use of. operational amplifiers and
favor large discrete amplifiers which can be tailored
to minimize system errors.
This configuration utilizes the wide bandwidth
and speed of HA-2539 plus the output drive cap-

!SIGNALOUT

R3
4K

w

A,
SET:

':'

ability of HA-2630. Stabilization circuitry is avoided
by operating HA-2539 at a closed loop gain of 10
while maintaining an overall block gain of unity.
However, gain of the block may be varied using the
equation:

R4
4K

'------_------ (iNSIDE MOTORI

L:>IMTl

L-_~~=~~:

______'W________________~I
22011

If the HV-1000 is inadvertently inserted backwards
into its socket, the chip is not damaged. Usually, the
motor will be observed to run without any control.
Normal operation will resume when the package is
rotated.

'

START

CAPACITOR

(INSIDE MOTOR)

Figure 9.
Application Circuit Which Ensures Full Power Starting Under
All Conditions.

10-120

Because of the relatively high voltages (including
multi kilovolt lightning surges) to be found on the
HV-1000 circuit, it is recommended for best reliability, that if a printed circuit board is used, the

conductors having large potential differences should
be widely spaced. Coating the whole assembly with
resin or varnish will usually improve the reliability
achieved.

N

o::r
It)

w

t-

O

ACKNOWLEDGEMENTS

Z

a:

The authors wish to acknowledge several helpful
conversations with Frank J. Nola of the NASA
Marshall Space Flight Center. The development of
the HV-1000 was aided by the donation of a motor
collection by Reliance Electric, Leeson Electric,
Gould Electric, Bodine Motors and Emerson Electric.
Illuminating comments from the engineering staff of
Doerr Electric and the G.E. General Purpose Motor
Division were invaluable.

D..

«

BIBLIOGRAPHY
The following selected readings may be of interest to
those wishing to further pursue the study of single
phase induction motor energy savers.
1.

NASA Technical Brief MFS 23280. Summer
1977. "Save Power in AC Induction Motors".

2.

U.S. Patent 4052648. "Power Factor Control
System for AC Induction Motors". F .J. Nola.

3.

NASA Technical Brief MFS 23988.
Spring
"Fast Response Power Saver for In1979.
duction Motors".

4.

NASA Technical Brief MFS 25323. Summer
"Improved Power Factor Controiier".
1980.

5.

"Circuit Saves Power in AC Induction Motors".
F.J. Nola, EDN, P185, September 5, 1979.

6.

"Improvement in Energy Efficiency of Induction Motors by Means of Voltage Control". N.
Mohan. IEEE Trans. on Power Apparatus and
Systems. Vol PAS-99, No.4, July/Aug 1980.
P1466.

7.

"Energy Efficiency of Electric Motors". A Report Prepared for the U.S. Department of Energy.
Report No. HCP/M50217-01 reprinted
April 1978.

8.

"Load Responsive Motor Controller". NASA
Tech Briefs. Spring 1981. Vol. 6, No. 1,MFS25560.

9.

"The Case for the Power Factor Sensing Motor
Controller". M.L. Cohen. Proceedings of the
Second International MOTORCON Conference,
March 29, 1982. P 621. Published by Intertec
Communications, Oxnard, California.

10. "Energy-Efficient Electric Motors". A book by
J.C. Andreas, Published by Marcel Dekler Inc.,
of New York, 1982.

10-121

APP
NOTE

FOR YOUR INFORMATION

Harris Analog

No. 543

NEW HIGH SPEED SWITCH OFFERS
SUB-SOns SWITCHING TIMES
By. Carl Wolfe

INTRODUCTION

load will increase when the outputs are made common.

An ideal CMOS analog switch would exhibit such
characteristics as zero resistance when turned on,
infinite resistance when turned off, zero power
consumption, and zero switching time. Unfortunately, such a device is usually found as an example
in a college textbook. The real world offers tradeoffs and imperfections which prevent the realization
of the ideal. The integrated circuit designer works
within these limits and attempts to optimize device
performance by utilizing new technologies and improving circuit design. The development of a new
high speed analog switch required the use of both
of these techniques to achieve its performance.
(See Appendix I: "Inside the HI-201HS"I.

The next application is a high speed sample and hold
which takes advantage of the improved performance
of the HI-201 HS and the precision F.E.T. input of
the HA-5160 high slew rate amplifier. A sample
and hold circuit or track and hold as it is sometimes
called, has two operating modes. In one mode the
switch is closed and the capacitor charges to the input
voltage. The second mode occurs when the switch
is opened and the capacitor holds this charge for a
specified period of time.
The speed of a sample and hold circuit is directly
related to the switching device used and the output
amplifier. This characteristic of a sample and hold
circuit is called the acquisition time. It is defined
as the time required following a "sample" command,
for the output to reach its final value, The acquisition time includes the switch delay time, the time
constant of the switch on resistance and hold capacitor (T = RON CHOLDI , and the slew and settling times of the output amplifier.

Thi! HARRIS HI-201HS is the industry's first sub50ns monolithic analog switch and along with fast
switching speed, offers improved performance and
pin compatibility with indu~trystandard 201's (Fig.
1I. This article will discuss the technology, performance, and applications for this product.

IMPROVE THOSE EXISTING DESIGNS
The application circuits which follow are examples
of typical applications and illustrate how the H1201 HS can improve existing applications where
standard 201's are presently being used.
The first example is a high speed multiplexer shown
in Fig. 2. The analog multiplexer is a circuit which
switches a number ot analog inputs to a single output
and is used heavily in data conversion and avionic
applications. This function can be easily achieved
with the .HI-201HS by tieing the outputs together
and selecting the appropriate analog input. The H1201 HS is an excellent choice for this application since
its low on resistance and leakage current will reduce
system error, and its high speed is unmatched by any
other monolithic analog switch. Since the output
capacitance is additive, the RC time constant of the

10-122

The photographs shown in Fig. 3 illustrate the improvement in the acquisition time possible by using
the H1-201 HS. The first photograph represents
the sample/hold circuit using a standard 201 switch
and an HA-5100 operational amplifier. The first
waveform is the "Sample" voltage (V AI. The second
waveform is the voltage on the hold capacitor (V 1I.
And the third waveform is the output of the amplifier
(V21.
The second photograph is the same ci rcu it with a
HI-201 HS and on HA-5160 op amp. Comparison of
the photographs shows the H1-201 HS has significantly reduced the switch delay time and the high slew
rate of the 5160 amplifier has also contributed to
the reduced acquisition time.
A source of error in this circuit is a d. c. offset which
is called sample to hold offset error. This error is

C"')

primarily due to the charge injection (Q) of the
switch and is related to the hold capacitance by the
following expression,

'Il3'

It)

W

HI-201HS

15

offset error (Vo) = charge transfer (Q).

10

CH

....
o
z

a:

Il.

«

The reduced charge injection of the H 1-201 HS
(typically 10 pc) will result in immediate reduction of
this error.
Using analog switches with operational amplifiers
is common in circuit design. An example is shown
in Figure 4 which is an integrator with start/reset
capability.

VA
TOP ViEW
Al

1

16

A2

OUTl

2

15

OUT 2

IN 1

3

13

v+
NC

v·

,.

•

va

IN 2

GI\lD

5

12

IN.

6

11

IN 3

OUT4

7

10

OUT 3

A.

S

9

(a)

LOGIC

A3

VA

SWITCH

o - VAL~.8V

ON

1 - VAH~2.4V

OFF

va
TYPICAL SPECIFICATIONS

(±15V Supply)

Analog Signal Range

±15V

On Resistance

3011

Off Leakage

.3nA

Switch On Time
Power Dissipation

en

(b)

«0
z

30ns

Figure 2.
High Speed Analog. Multiplexer: (a) circuit
response using the standard 201 (.T access = 400n,) (b)
circuit response using HI-201HS Itaccess - 50n5). The
access time is defined as total time required to activate
an "off" switch to the uOIi" state. Access time',is normally
measured from the initiation of the digital input pulse
(VA) to the 90% pOint of the output transition.

,,1)OmW

Figure 1.
Typical Pinout and Specifications - The HI201HS is pin compatible with standard 201's and offers
improved performance.

g:~

Specifications given are typical

Vtlues at TA = 25OC.

10-123

+V

13
HI-201HS

VIN

0--+-'+--<>
~~----oVOUT

-v

-v

Figure 3A. High' $pHd SaMple and Hold:
The basic
sample and hold samples the input voltage when the switch
is closed, ancf the capacitor' holds the voltage when the switch
is open; -The speed of the switching :element affects the
speed of the sample andhQld;

Figure 4A. Integrator with Start/Reset: A low logic input
pulse disconnects the integrator 'f,om the analog inplit
and discharges the capacitor. When the logic input changes
to a high state, ,integrator is activated.

,

VA
VA

V1

VO

V2

Figurit'3B. Circuit response to a "Sample" command
using a standa!d 201 and an HA-5100 _rational amplifier
(Acquisition time, = 1.5~s1

Figure 4B. Low Level
using standard 201 switch.

Integration-

Circuit

response

VA

V1

VO
V2

Figure 3C. 'Circuit response ,using an HI-201HSand
HA-5160:
HI-201HS significantly reduces switch delay
time. (Acquisition time - 500nsl

Figure 4C. Low
level
integration-Circuit
response
illustrates improved charge injection of the HI-201HS.

10-124

I

The switch is used to apply the input signal and to
reset the integrator. Applying a low logic level removes the input signal and the capacitor is discharged.
When a logic level high is present, the input signal is
integrated with a rate of change equal to

('I)

o::r

VON

>''------t-...,...--t-t---o VOUT

W

I-

o

dVO/dt=..i=-Vi
Cf R1Cf

z

0:

o

o

o-+....:..r;:>----J

The reduced on resistance, leakage current, and
charge injection of the HI-201 HS will improve the
performance of this circuit and an example of this
improved peformance can be seen in the photographs
in Figure 4. These photographs illustrate the reduced
charge injection which the 201 HS offers. The component values are R1 = 1Ml1 ,C = 150pF and VIN
= -1 V. With these values, the amplifier will integrate
the input signal with a slope of 6.6mv/Ii- s. For a
50 Ii- s time period, the amplifier will integrate to a
magnitude of ;:;:: 300mV. The photographs of the
test results indicate this to be true, but it should be
apparent that the two photographs are quite different. The first photograph represents the amplifier
output using a standard 201 as the reset switch.
The second photograph is the same circuit with a
201 HS.

Q.

- ___

J

'--,,+--" - __ .J

Figure 6.
Amplifier with Programmable Gain- Switch
selection activates a new voltage gain which is determined
by the resistive feedback.

Depending on which switch is selected, a particular
cutoff frequency is introduced by the expression,
FC=
27TR Cx

The offset error in the first photograph is due to the
charge injection of the switch. Using the expression
Q = V x C and knowing the standard 201 has a typical
charge transfer of 30pc, this offset can be calculated.
V = Q/C = 30pc/150pf=200mV.

A programmable gain amplifier is shown in Figure 6.
Similar in function to the filter application, the gain
of the amplifier is determined by selection of a switch.

C,

When using switches with other components it is
important that a switch be selected which introduces
a minimal amount of error to the circuit. Operational
amplifier gain error due to high on resistance or
offset voltages due to excessive leakage current and
charge injection are examples of potential error
created by the switch. The previous applications have
demonstrated that the 201 HS offers improved
performance by minimizing circuit error and increasing system speed.

15

C2

ON THE DRAWING BOARD

10

C3

Other examples of combining switches and amplifiers
are shown in figures 5 and 6. In both these applications the switch is used to tailor the amplifiers
performance. Figure 5 is a low pass filter with a
selectable break frequency.
+V
13
HI-201HS
I

__ .J

LP,
10

,.

LP2

__ J

11

Since the introduction of the HI-201HS switch,
many engineers have expressed an interest in using
this new product. Although much of their work is in
a preliminary stage and they do not want to divulge
exact details on their designs, the following information is intended to give you an idea of how other
engineers are considering using the H 1-201 HS.

!

LP3

---'

co

__ J

LPO

Lt)

lOOK
10K

The majority of the engineers are interested in taking
advantage of the products fast switching speed. One
particular engineering group is investigating replacement of DMOS (double-diffused MOS) transistors
with the HI-201HS.

>'------....L...--oVOUT

·V

Figure 5.
Low Pass Filter with Selectable Break Frequency- Switch selection places various values of capacitance in parallel with the feedback resistor. The value of the
capacitor determines the break frequency. The break frequency is that frequency at which the signal begins attenuation.

The DMOS transistor is capable of extremely fast
switch ing speeds (1 ns) and until now, switches

10-125

fabricated using CMOS technology have not been
fast enough to be considered. But the H 1-201 HS
is attractive since it offers unprecedented switching
speed along with the established benefits of CMOS
technology. Such benefits include a wider analog
signal range capability and lower operating power
requirements.

SIG 1

i

OVOUT

LOGICINPUT~
fo lMH,

I- T--I

T ~ l/f
T ~ 1/106
T ~ 10-6 sec ~ 1 /is

..!.~ 500ns
2

Figure 7.
High Frequency Switching - HI-201HS fast
switching times allow it to transfer data at a higher rate
of frequency.

Another area where the H 1-201 HS is generating interest is in the area of medical electronics. This is
a growing field and improvements are continously
being made as products become available much of the
medical equipment being designed requires both high
speed and accuracy.
Medical test equipment is primarily used to transmit
or receive information from the patient. An example
where both these functions are used is in the area
of ultrasound. Ultrasound testing requires that a
signal be transmitted to the patient and the return
signal is then amplified and displayed or recorded.
The 201 HS is being considered for the use in such
an application and would be used to control the
transmission and reception of these signals.

I

VOUT
1Kn

SIG2

11

1· t t ~~

A common application for analog switches is time
division multiplexing, where many signals are processed on a single channel. High speed switching
allows higher information capacity on the channel,
since the switching speeds of an analog switch are
directly related to the maximum switch activation
frequency. The faster a switch can turn on and
off, the higher the possible switching frequency.
An example of this relationship is shown in Figure
7. If a switch is activated at a frequency of 1MHz,
it must turn on and off within a 500ns time period.
Since the H 1-201 HS has a maximum on and off times
of 50ns, and can turn on and off within a lOOns
time period, it theoretically possible that it can
be activated at a 5MHz frequency rate. This improved capability is making the HI-201 HS an
attractive component to design engineers requiring
high frequency data processing. Conversations with
engineers indicates that possible applications are
computer graphics and visual display circuit designs.

15

9

11

j

.J

SELECT

10

9

SlG'
SELECT

'1

1

VIN~~~VOUT

['
Figure 8.
Video Switching with Improved 150lationI mproved high frequency off state performance is obtained
by using a T -Switch configuration. When two series switches
are off, the third switch is shorted to ground.

The designers are not only interested in fast switching
speed, but also in low on resistance. This is an important aspect of the switch since many of the electrical signals in medical electronics are of a small
magnitude. An example is patient monitoring equipment which converts physiological parameters into
electrical signals. If these low level electrical signals
require switching before amplification, a low on
resistance switch is essential to minimize the voltage
drop across the switch itself. The low on resistance
of the H 1-201 HS enables it to be used in applications
using signals of smaller magnitude.
Video circuit design involves the control of high frequency signals.
Applications which require the
switching of these high frequency signals are usually
limited by the off isolation and crosstalk performance
of the switch. Off isolation is defined as the amount
of feedthrough of an applied signal through an off
switch. Crosstalk is the amount of cross coupling of
an "off" channel to the output of an "on" channel.
Both of these switch characteristics will degrade as
the frequency of the input signal increases.
The H 1-201 HS has some improvement over the
standard 201 in these areas but the configuration
shown in Figure 8 is being used by designers to improve the isolation capabilities of CMOS analog
switches. This configuration is known as "T" switching since the three switches used for passing the signal
could be thought of in the shape of the letter T. The
simplified figure shows that when switches # 1 and
# 2 are off, switch # 3 is tied to ground. When
switches -#= 1 and,# 2 are on, #3 is off. This improves isolation by having two channels in series off
and any feedthrough is fed to ground.

10-126

CONCLUSION
The HAR R IS H1-201 HS is the fastest monolithic
CMOS analog switch available. It offers improved
performance for existing designs and should be considered for use in any application where switching
speed is an important criteria.
ACKNOWLEDGEMENTS
The author would like to thank Gary Maulding,
Frank Cooper, and Bob Junkins for their technical
assistance, Ken Timko and Dick Whitehead for their
editorial comments, and the dynamic duo of Lilly
Andrews and Kathy Glines for their secretarial
skills and patience in the preparation of this paper.

REFERENCES
1.

D. F. Stout, "Handbook of Operational Amplifier Circuit Design". New York: McGraw-Hili,
1976.

2.

J. G. Graeme, G.E. Tobey, and L. P. Huelsman,
"Operational Amplifiers: Design and Applications". New York: McGraw Hill, 1971.

3.

J. A. Connelly, "Analog Integrated Circuits"
New York: John Wiley & Sons, 1975.

4.

HA-2420/2425 Fast Sample and Hold data
sheet, Harris Semiconductor.

The D. C. static level shifter achieves high switching
speeds through the use of a unique bipolar input stage
and a network of switching and holding MOS transistors. Devices MN5, MP5, MN9 MP9 are the switching transistors and MN6, MP6, MN10, MP10 are the
holding transistors. The major advantage of the
bipolar input transistors is that its transconductance
(gm) is much higher than that possible with F. E. T.
transistors.
To understand the level shifter operation, consider
a change of logic input from low state to high.
Initially VA is low, 0 ; 01 ; 0',; -15V and 6 ;
01 ; (f; 15V. VB is at ground and ON2, OP2 are
off. When VA goes high, ON2, OP2 turn on, which
slew the gates of switching devices MN5, MP5 with
a current I ; (VA -2VBE)/R. The switching devices
overcome the holding devices, MN10, MP10 and
switch the internal nodes 01, and 61. CMOS buffers
111, 113 provide large drive currents to the switch
cell, while inverters 112, 114 provide delayed feedback signals. The feedback signals turn off holding
devices MN10, MP10 while turning on holding devices
MN6, MP6. The feedback also turns on ON2, OP2
by means of MN 1, MP1. These feedback signals
have retu rned the level sh ifter to a static condition
by turning the bipolar input stage and MOS switching transistors off.

on
LOGIC

INPUT

APPENDIX I -

INSIDE THE HI-201HS

The HI-201 is a TTL compatible quad CMOS analog
switch which features switching times under 50ns
and a typical "on" resistance of 35n. The fast
switching times are achieved through a combination
of process and circuit design techniques. The H 1201 HS is fabricated using a dielectric isolation
process with complementary PNP and NPN bipolar
transistors and polysilicon-gate CMOS. The use of
bi-technology process enabled a unique circuit called
at>. C. Static Level Shifter to be designed.
The typical CMOS analog switch consists of a switch
cell which is driven by a level shifter. The level
shifter converts a single logic input into two complementary outputs which drive the gates of the
CMOS switch cell (Fig. A). The switch cell represents
a capacitive load to the level shifter, so fast switching
times require large drive currents to charge these
capacitances quickly. The D. C. Static level shifter
circuit (Fig. B) provides large drive currents only
when switching and dissipates little power in a
quiescent condition.

10-127

Figure A.
Simplified I. C. Analog Switch OperationLevel Shifter converts logic input into drive signal for CMOS
switch cell.

Figure B.
Simplified D. C. Static Level Shifter - The
level shifter consists of a unique bipolar input stage and a
network of SWitching and holding devices.

CO)

o::r
It)
W

I-

o
Z

~
Il.

----~-_+-o OUTPUT

FOR
R= 20KU

0.1""

f ~ :~~lfzF
1=~

2N4391

LOW VOLTAGE WEIN BRIDGE OSCILLATOR

10-132

APPLICA TION NOTE 544
Application 6-Bar Code Scanner
the received signal. Amplifier A4 is used as a comparator whose reference is maintained at the midpoint of
the peak to peak signal by resistors R5 and RS. This
provides a more accurate edge detection and less ambiguity in bar width. Amplifier A5 is used as an optional
noise gate which only allows data to pass through the
gate when the peak to peak modulation signal is larger
than 1 diode drop. This circuit is operated by a single
supply voltage with low power consumption which
makes it ideal for battery operated data entry systems.

The circuit shown below illustrates a method of interfacing a HEOS-1000 emitter-detector pair with a HA5144 for use as a bar code scanner circuit. The HA5144 is used as an amplifier system which converts the
bar and space widths of the printed bar code into a
pulse width modulated digital signal. Amplifier A1 is
used to amplify the current output of the detector. The
output of A1 is passed to two precision peak detector
circuits which detect the positive and negative peaks of

o::r
o::r

It)

w
~

o
z
a.:
CL
--

ANALOG INPUT, VIN

MODE OF
OPERATION

NEGATIVE
QVERVOL TAGE
(VIN :$~'4V)

NORMAL
OPERATION
(-10V:$VIN :$+10Vl

POSITIVE
OVERVOL TAGE
(VIN2:- +14Vl

CS

_

OUT

f---o

Power On;

OXO

000

XOO

Switch Open

OXX

XXX

XXx*

Power Off

OXX

-

XXX*

Switch Closed

Power On;

6800 SYSTEM

HI-50XL

(Switch MOSFETs' N-P-N, where X = OFF; a = ON)
* State of the P-channel MOSFET is indeterminate.

OATABUS ______________

--,~

AO-AN EN

74123
~

R/WO--- A
DBE

CONTROL SIGNALS
The Address inputs AO, Al, A2, A3 and Enable are
latched into an internal buffer when .WR goes from
low to high. These digital inputs are DTL, TTL and
CMOS compatible. Each latch output is level shifted
into the decode section, which activates the appropriate channel, (if any). The device may be reset
(all channels OFF) by taking RS low. Usually, AS
is tied to the system reset line to assure that all
channels are OFF fOllowing a turn-on of power.
The reset ( RS) line may also be tied to the power
supply with a resistor and capacitor to provide a
delay from initial power-up.
Refer to Figure 3.

0---

B

Q

425ns

WR

OUT

---0

cs 0 - - - RD
'--ANALOG
INPUTS

---'-------------~l:
IN

___J

(MINIMUM OBE LOW TIME REQUIRED)

Figure 4. 50XL Control Requirements

THE 50Xl-SYSTEM INTERFACE
There are perhaps eight basic ways to connect a 50XL
multiplexer in a microprocessor system. Most of these
are options common to the interface of any peripheral
device, so the most appropriate method is usually indicated by the system hardware and its intended use.

The reset function overrides all others, just as WR
(Write) overrides the address inputs (AO - A3 and EN
are ignored when iNR is high). With WR low and RS
high, the switches respond immediately to a change in
channel address; i.e., the latches are "transparent".

To operate the 50XL, three functions must be provided - chip (device) selection, channel selection (AO,
A, . . . AN, EN) and control (WR, RS). Channel
selection is accomplished by a direct connectioneither to the data bus (simpler software) or to the address
bus (higher clock speed allowable). For either case, a
chip select is obtained in the usual way, using either
an address bus decoder or the "bit flag" method, in
which one address line is dedicated to the 50XL.
Further, many systems will offer access to the 50XL
through an option of either "memory mapping" or
"I/O mapping", yielding eight different interface
connections.

Members of the 50X L family are easily interfaced to
a microprocessor system. The channel select lines
may be tied directly to either the address or the data
bus. No I/O interface device (PIA, PPI) is required
since latches are provided on the HI-50XL chip.
However, some additional hardware may be necessary
for deriving the H 1-50X L WR signal, depending on
system requirements. Refer to Figure 4.

10-136

high transition at MUX's iiiTR input. The 50XL
requires a minimum 300ns for this WR pulse, and if
necessary, a monostable multi vibrator (one-shot)
may be added to extend the pulse's duration. To
clarify these system timing relationships, the parameters relevant to an 8085 I/O Write operation are
shown in Figure 6, along with two selected waveforms from Figure 5 and the 50XL Write Pulse.
As an alternative, however, the timing requirements
may easily be met using a programmable peripheral
interface device (PPI, PIA, or equivalent).

Four of these cases are illustrated in Figure 5, in
which each H 1-506L multiplexer is installed in the
I/O space of an 8085 microprocessor. Channel
selection is by the data bus (# 1,:#2) and the address bus (#3,#4). Device selection is provided by
an address decoder ( :# 1,# 3) and by the dedicated
address line "bit flags" (#2,#4).
For each multiplexer, external gates and control lines
are arranged to write a 5 bit word (AO, A 1, A2, A3,
EN) to the address inputs, and latch it by a low-to-

II)

o::t

II)

W

I-

o
z

0.:
Q.

«

H 1-506L :tt 1
AO-A3

EN

As

CSg
HI-506L #2
AO-A3

EN

As
WR

HI-506L #3

RS
en

g:~

<1:0

z

Csg

HI-506L #4
AO-A3

EN

As

Figure 5. 50XL Interface Examples

10-137

plexer's WR input is derived by appropriate gating of
this chip select with the 8085 WR and lo/iiii signals.

SYSTEM APPLICATION EXAMPLE

In the upper system a D-type flip-flop simultaneously initiates a conversion and switches the Sample/Hold
to Hold. This.is acceptable since the Hold mode settling is only 185ns, and at least 1J.ls will elapse before
the converter's first bit decision. Similarly, the lower
system uses a flip-flop to initiate conversions and
another flip-flop to control the HI-200 switch,
forming a 32 channel multiplexer.

Figure 7 includes two separate data acquisition systems controlled by an 8085 microprocessor. In
the upper system, 16 analog channels are multiplexed into a Sample/Hold - A/D Converter combination which provides sample rates as high as 2.7kHz
per channel. In the lower system, two H1-506ls are
operated as a single 32 channel mUltiplexer, delivering the analog signal through a buffer amplifier
directly to an A/D converter. Bandwidth of these 32
analog signals is limited since no Sample/Hold is used
(for 12 bit accuracy, BW must not exceed 2 hertz).
However, each channel may be digitized every 736 J.ls,
for a 1.36kHz sample rate.

The two multiplexers in the lower system are operated in parallel so two analog signals are always presented to the analog switch. Crosstalk in the switch is not
a concern since only low BW signals are involved. As
an alternative, one may eliminate the HI-200 switch
and its flip-flop by connecting the MUX outputs together and using the ENable controls to enable one
multiplexer at a time. However, output capacitances add together to increase the output time
constant. Additional settling time must be allowed
for the multiplexer, so the result is a lower channel
rate than with the H1-200 switch arrangement.

In each system of Figure 7, control of the HI-506l
multiplexer is as shown in Figure 5,#2. That is, the
latched address inputs are connected directly to the
data bus for channel selection, and a single bit of the
I/O address is used as a chip select. (Up to eight peripherals may be controlled in this manner). The multi-

+25OC

MIN liMITS
FUll TEMP. RANGE

UNITS

tWW. Write Pulse Width

155

300'

n.

tOW. A, EN Data Valid To WRITE
(Stabilization Time)

85

226

ns

twO. A. EN Data Valid After WRITE
(Hold Time)

20

100

n.

tAS. RESET Pulse Width (not shown)

250

400

n.

TVPICAL

PARAMETER

ClK

8085 .
MICRO,
PROCESSOR

AOo ' A 0 7

ALE

101M

FIGURE 5. POINT

®

FIGURE 5. POINT

®

2 GATE OELA YS

50Xl MULTIPLEXER
(FIGURE 5,#1 )

~,

GATE DELAY

"..,",~~--li='"

r-'

tWW---I_'--

'TO MEET THE MINIMUM two REQUIREMENT,
8085 ClK MUST NOT EXCEED 2MHz.

Figure 6. Timing Requirements.

10-138

Initiation of a Read operation by the processor
toggles a flip-flop in each system, setting the converters to Read and (for the upper system) switching the Sample/Hold to Sample. Finally, each converter's STATUS output is inverted and tied directly
to one of the processor's interrupt request terminals,
with higher priority to the upper converter. The processor may execute instructions until a conversion is
completed in either system - then it vectors to a Read
routine, stores the data, and triggers another conversion. Each result will occupy two bytes of memory

since a 12 bit word must be transmitted on an 8 bit
data bus. The H 1-574A accomplishes this by monitoring the AO address line with its AO control input,
allowing the converter to route the two bytes into
consecutive memory locations.

Machine language routines suitable for exercising the
system of Figure 7 are listed in the following section.
Also, detailed parametric limits for the H 1-506L
and H 1-507L multiplexers are listed in Figure 8.

Figure 7. HI-50XL System Application.

10-139

data buses to specific jobs, control information may
be conveyed to the system components by individual
bit signals on these buses. The programmer simply
writes an appropriate control word to the location of
a given component. Control words are composed
according to the bit information shown below:

SOFTWARE CONTROL
These brief assembly routines implement the basic
operations required in Figure 7. Since hardware
connections commit various lines of the address and

"1": MUX ENable (All)

"1 ": Selects Middle or Lower MUX
(with D4)
"1 ": Selects Upper MUX

Not Used
MUX Select
("0": Middle;
"1": Lower)

Not Used

r

"1 ": Selects Lower ADC

MUX Channel
Select

"1": Selects Top ADC
Not Used
Conversion Length
("0" = 12 Bit;
"1" = 8 Bit)

[

~,--~'--~1

r-~--'-~r-~-L-r~~L,~~

I I
A7

A61 A51 A41

A31 A21

Al

I

AO

I I

I

D7

D6

X

X

,r-------~·------~I
Dl

I I
DO

OPERATIONS
1.

Select Channel 5 of upper MUX:

I

X

X

0

1

0

MVI
OUT
2.

I

0

= 10 HEX

I

1

X

1

0

1

0

I

= 85 HEX

I

= OOH

Move control word to Accumulator
Write word to MUX

A,85H
10H

StH to HOLD and start a conversion, upper converter:

I

X

X

X

X

X

X

1

0

I

= 02H

I

X

X

X

X

X

X

X

X

Write word to Flip-flop

02H

OUT

3.

0

0

Read output of top converter, following an interrupt via 8085 RST7.5 input. (Converter output is 1101 0110,1001.):
Read 1st byte -

I

X

X

'X

X

X

X

1

0

I

=02H

I

=03H

I

1

1

0

1

0

1

1

0

I

0

0

0

I

(8MSBs)

= D6H

Read 2nd byte -

I

X

X

X

X

X

X

1

1

I

1

0

0

1

0
(4LSBs)

Interrupt RST7.5 causes a JUMP to the following service routine:
Read first byte
Move data to D register pair
Read second byte
Move data to E register pair
Move control word to Accumulator
Reset Interrupt

02H
IN
MOV
D,A
03H
IN
MOV
E,A
MVI
A,lAH
SIM
(Store data instructions)
RET

Return

10-140

= 90H

It)
4.

o:::r

Select Channel 14 of lower MUX:

It)

~_X____X________O____X_____X____X____X~I =20H

x

x

0

= 9EH

0

Note: MUX channels are numbered 0 to 15.

MV1
OUT

W

I-

Z

A,9EH
20H

a.:
Il.

Move control word to Accumulator

Write word to MUX

c(

5.

Initiate a conversion in lower converter:

x
6.

x

x

x

x

o

o

= 04H

x

x

x

x

x

x

x

x

Read output of lower converter following an interrupt via 8085 RST5.5 input:
This is accomplished with a routine identical to that in Operation 113, except location 04H is used instead of 02H,
and 05H instead of 03H.

10-141

= OOH

APP
NOTS

FOR YOUR INFORMATION

Harris Analog

No. 548

A DESIGNERS GUIDE FOR THE HA-5033 VIDEO BUFFER
Carl Wolfe

Introduction

the TO-8 metal can and the 8 pin epoxy Mini-Dip. The
pinouts for each package are illustrated in Figure 1.

Harris Semiconductor is an industry leader in the high
speed, wideband, monolithic operational amplifier
market. Due to the high performance of Harris products, designers in the more specialized areas of electronics have shown interest in utilizing these products
in their applications. One such area is video design. In
an effort to address this market, Harris has introduced
the HA-5033 video buffer.

TOP VIEWS

This paper will discuss the HA-5033 design and provide additional performance characteristics not shown
in the data sheet.
METAL CAN PACKAGE

HA-5033 Description

FIGURE 1. HA-5033 PINOUTS: TO·a METAL CAN·PIN COMPATIBLE WITH THE LHOO33 HYBRID. a PIN MINI-DIP - FABRICATED USING A COPPER LEAD FRAME. ADVANTAGES
INCLUDE EXCELLENT THERMAL CHARACTERISTICS
AND BOARD SPACE SAVINGS.

The HA-5033 is a unity gain monolithic I.C. designed
for any application requiring a fast wideband buffer. A
voltage follower by design, this product is optimized
for high speed 500 and 750 coaxial cable driver applications common in color video systems.

The high performance of this product (summarized in
Table 1) Is the result of the Harris High Frequency
Dielectric Isolation Process. A major feature of this
process is that it provides both PNP and NPN high frequency transistors. which make wide bandwidth designs, such as the HA-5033, practical.

Critical performance characteristics are summarized
in Table 1. Outstanding differential phase/gain characteristics combined with an output current capability of
±100mA makes the HA-5033 an excellent choice forthe
line driver applications required in video circuit design.
PARAMETER

MIN

TYP

Input Offset Voltage
Input Bias Current
.1
Differential Phase
.1
Differential Gain
Slew Rate (±15V)
1000
±100
Output Current
Bandwidth (small signal)
250
65
Bandwidth (VIN = 1 VRMS)
Supply Current

MAX

UNITS

15
35

mV
p.A
degree

A Closer Look
Most manufacturer's data sheets provide a schematic
diagram and depending upon the complexity of the
product, this schematic may be comprehensive or possibly a simplified version. Schematics are a visual
means of presenting information, ranging from reliability data, such as transistor counts, to circuit information for circuit analysis or computer simulation. But the
most important reason for the schematic is to communicate to the customer the internal structure of the product and therefore, some insight into its operation.

%
VIpS

20

mA
MHz
MHz
mA

TABLE 1. HA·5033 SPECIFICATIONS: TA =+25oC;
±VSUPPLY =±12V (UNLESS OTHERWISE SHOWN)

At first glance, a schematic may appear as nothing
more than a collection of resistors and transistors. But
upon closer examination, particular areas of operation
should become evident. Using the HA-5033 as an example (Figure 2), it will be shown thatthe HA-5033 consists of a signal path, bias network, and performance
optimization circuitry.

Other features, which include a minimum slew rate of
1000V/ps, make the HA-5033 useful in high speed AID
data conversion and sample/hold circuits.
The HA-5033 is offered in two package configurations,

10-142

Application Note 548

co
qo
an
W

r-----'

t-

O

I~----~_r~--_r----_r--_r_r~--_,

I
I
I
I

SLEW ENHANCEMENT

 PDC + PAC
PDC = (+V)(+I) + (-V)(-I)
PAC = (lIT)ojT v(t) i (t) d t

For the Harris HA-5033, the maximum junction temperature is Tjmax = 200 0C. The thermal impedances forthe
HA-5033 in the TO-8 metal can package are OJ-c =
31 0C/W and 0j-a = 99 0C/W. The epoxy mini-dip thermal impedances are OJ-c = 27 0C/W and OJ-a = 90 0 C/W.

Video Performance
The images which appear on your television picture
tube are created by a process called scanning3. Scanning is a method of recreating the optical image of a
scene one line at a time. Referring to Figure7a, an electron beam moves or "scans" from left to right and
quickly returns to a position below its starting spot.
This process continues until the bottom of the picture
is reached and the beam returns to the original top left
hand position. This method is called sequential scanning.

Recommended heat sinks for the HA-5033 in the TO-8
metal can package are the Thermalloy 2240A 1 and
I ERC-UP-T08-51CB2 (base), IERC-UP-C7 (top). Thermal impedances are Os-a = 27 0C/W and 0s-a = 1OOC/W,
respectively. Oc-s is dependent upon the type of insulator or thermal jOint compound used. Both products are
two piece heat sinks, but differ in design.
By using the given product information and supplying
an operating ambient temperature, the designer can
determine the maximum power the system will dissipate and not exceed the maximum junction temperature.

STARTING POINT

For example, Figure 6 shows the maximum power dissipation for the HA-5033 in a TO-8 metal can package to
be 1.75W at 25 0C.
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6

- - --

--

-.......

1.4

1.2
1.0
.S
.6

...........

SEnUENTIAL SCANNING

-........

TO-SCAN

~

~O HEtT SIINK -

.4
.2

15

25

35

45

55

65

75

85

SECONO HALF OF
OF LINE 263

MINI-DIP
NO HEAT SINK

95

LINE 264,
FIELO 2

;::;;;

,-

105 115

LINE 265,
FIELO 2

125

LINE 266,
FIELD 2

---=------- :
-

4---

I

- - - - - =-:
- - - -.~.

I

I

•

I

AMBIENT TEMPERATURE (OCI

.I.

FIGURE 6. HA-5033 MAXIMUM POWER DISSIPATION VS
AMBIENT TEMPERATURE: FREE AIR
~~-------------------/

FIRST HALF
OF LINE 263

The maximum power dissipation of the HA-5033/
2240A heat sink system is calculated to be,
Pdmax

200-25
=_
_

INTERLACED SCANNING

= 3.01W

31 + 27

FIGURE 7. SCANNING SEQUENCE

10-145

LINE 1,
FIELD 1
LINE 2,
FIELD 1
LINE 3,
FIELD 1

LINE 262,
FIELD 1

W

I-

o
Z
a.:
a..
«

Application Note 548
Incorporated into present television broadcast standards is a technique called interlaced scanning. Interlaced scanning recreates the scene by providing two
half scans. As shown in Figure 7b, the first scan traces
out the odd numbered lines, the second scan fills in the
even numbered lines. This technique avoids the flicker
problem and excessive bandwidths required forsimilar
picture definition using sequential scanning.
The United States NTSC (National Television Systems
Committee) broadcast standard is a 525 line standard.
Each scan consists of 262'h lines. The first scan is
known as field one, the second, field two. Therefore,
the complete picture consists of two fields.

The first 21 lines of each field are blank. Those lines are
left open and are not used to broadcast video information. Instead, these lines contain other important information, such as sync pulses, data transmission, and
test signals. The test signals contained In these lines
are called the Vertical Interval Test Signals (VITS)4,5,
which allows real-time monitoring of the television
broadcast signal quality. These test signal~ were used
to evaluate the video performance of the HA-5033.
Four test signals are commonly used in the vertical interval. They are the multlburst, color bar, composite
and vertical interval reference. These test signals are
shown in Figures 8 through 11.

:;
w

>
w

...

...

w

0:;:

100

:1i~

100 IRE

IRE
i!:

80

~

In
0:

60

:::0

40

o
o

>

'"

z
c[
>

...

~

w

0:

co

0:

...

...

20

...
c[

~

co
c[
::E

0

w

0:

w

~

'"
-40
THREE STEP
MODULATED
PEDESTAL

-40

FIGURE 9. COLOR BAR (FIELD 2, LINE 17) ENABLES MONITORING OF COLOR TRANSMISSION QUALITY

FIGURE 8. MULTIBURST SIGNAL (FIELD 1, LINE 17) ALLOWS FREQUENCY RESPONSE CHECKS

w

:1...
0:

;;:
In

IRE

120

IRE

o

120

!;;:

...

100

o

80

::E

60

w

100

:::0

80

o

60

LUMINANCE
REFERENCE

40

40

20

20

-40

CHROMINANCE
REFERENCE

-40

...z

~

FIGURE 11. VERTICAL INTERVAL REFERENCE SIGNAL
(FIELD 1 AND 2, LINE 19) PROVIDES COLOR AND GAIN REFERENCES

FIGURE 10. COMPOSITE SIGNAL (FIELD 1, AND 2, LINE 18)
DESIGNED FOR GAiN AND TIME DELAY TESTS

10-146

co

Application Note 548

~
It)

w

Each test signal was created to allow various distortions to be measured without interfering with the normal video transmission. These signal distortions which
exist in television systems are defined as linear or nonlinear. Non-linear distortion, such as differential phase
and gain, vary with the amplitude of the picture signal.
Linear distortions, usually dependent upon frequency
response, are independent of signal level. Forexample,
the multiburst test signal is very useful for frequency
response checks, where as the composite signal con·
tains signals for checking gain error.
Determining the HA-5033's performance level with
respect to the NTSC standard required the definition of
a measurement methOd. Test equipment was needed
that would produce the necessary NTSC test signals
and also monitor the device under test performance.
The test configuration, shown in Figure 12 consisted of
a Tektronix 149A NTSC6 generator and Marconi TF
2914A video analyzer7.

VIDEO PARAMETER

I-

VERTICAL
INTERVAL
TEST SIGNAL
GENERATOR

VIDEO SIGNAL
ANALVZER
MARCONI
~ TF2914A
75.Q',> INSERTION

... !.

TEKTRONIX 149A*
NTSC SIGNAL
GENERATOR

l~I::t;ZER
-12V

'TEKTRONIX 1910 NTSC DIGITAL
GENERATOR RECOMMENDED

FIGURE 12. HA-5033 NTSC PERFORMANCE TEST CONFIGURATION

The TF 2914A has the capability of measuring 24 separate video parameters. Other advantages include direct
readout and much more accuracy than possible using
scope methods. Table 2 lists the video parameters
tested on the HA-5033 along with the particular VITS
utilized by the TF 2914A.

VERTICAL INTERVAL TEST SIGNAL USED

Luminance Bar Amplitude

Luminance Bar, Composite Signal (Fig. 10)

Sync Amplitude

Sync Pulse, Composite Signal (Fig. 10)

2T Pulse to Bar Ratio

2T Pulse/Luminance Bar, Composite Signal (Fig. 10)

Chrominance to Luminance Gain Inequality Chrominance Component Amplitude of the 12.5T Pulse and Luminance Bar Amplitude, Composite Signal (Fig. 10)
Chrominance to Luminance Delay

Time Difference of Chrominance and Luminance Components
of the 12.5T Pulse, Composite Signal (Fig. 10)

Luminance Non-Linearity

Largest and Smallest Step Amplitude of the Modulated Step
Staircase, Composite Signal (Fig. 10)

Signal to Noise Ratio

Luminance Bar Level to Noise Voltage, Composite Signal
(Fig. 10)

Chrominance to Luminance Crosstalk

Chrominance Component of 3 Step Modulated Pedestal and
Luminance Bar, Multiburst Signal (Fig. 8)

Low Frequency Error

Amplitude of Low Frequency Signals

Bar Tilt

Difference of Luminance Bar Amplitude, Composite Signal
(Fig. 10)

2T K Factor

2T Pulse, Composite Signal (Fig. 10)

Differential Gain

Amplitude Deviation of Modulated Step Staircase, Composite
Signal (Fig. 10)

Differential Phase

Phase Deviation of Modulated Step Staircase, Composite Signal (Fig. 10)

Flag

Luminance Amplitude, Multlburst Signal (Fig. 8)

Multiburst 1-6

Amplitude of Each Frequency Burst, Multlburst Signal (Fig. 8)

Color Reference Burst Amplitude

Color Burst Amplitude, Multlburst Signal (Fig. 8)

TABLE 2. TF 2814A VIDEO MEASUREMENT PARAMETERS
REFERRED TO VERTICAL INTERVAL TEST SIGNALS

10-147

o
z

0:

11.

«

Application Note 548
Since the TF 2914A measurement includes any inaccuracies of the NTSC signal generator, a "delta" measurement was neccesary. The NTSC generator was
connected directly to the analyzer and the results recorded. Next, the HA-S033 was inserted and the results

recorded. The difference between the two readings
was considered the actual HA-S033 performance. Table 3 lists the video performance results of the HAS033.

VIDEO PARAMETER

Luminance Bar Amplitude
Sync Amplitude
2T Pulse to Bar Ratio
Chrominance to Luminance Gain Inequality
Chrominance to Luminance Delay
Luminance Non-Linearity
Signal-to-Noise Ratio
Chrominance to Luminance Crosstalk
Low Frequency Error
Bar Tilt
2T K Factor
Differential Gain
Differential Phase
Flag
Multiburst 1 Amplitude
Multiburst 2 Amplitude
Multiburst 3 Amplitude
Multiburst 4 Amplitude
Multiburst S Amplitude
Multiburst 6 Amplitude
Color Reference Burst Amplitude

HA-S033

UNITS

93.6
37.S
99.9
99.9
1.S
0.1
66
51.6
0.3
0.3
0.1
0.1
0.1
99.S
49.2
49.3
S1.0
50.4
49.7
SO.O
40.4

IREIRE
IRE
IRE
nS
%
db
IRE
mv
IRE
K
%
degree
IRE
IRE
IRE
IRE
IRE
IRE
IRE
IRE

TABLE 3. HA-5033 NTSC VIDEO PERFORMANCE

- IEEE Standard 205-1958 defines the levels of television video signal in terms of IRE units.
100 IRE units = 0.714V, pop

Applying The HA-5033

For the epoxy mini-dip, additional heatsinking can be
derived from soldering the no connection pins #2, 3,
and 7 to the ground plane. Also, pin #6 can be tied to
either supply, grounded or left open. But to optimize
device performance and im prove isolation, it is recommended that this pin be grounded.

The most important consideration when designing
with the HA-S033 is layout. The wide bandwidth of the
buffer necessitates that high frequency layout procedures be followed. Recommended procedures include
the use of a ground plane, minimization of all lead
lengths, avoiding sockets, and proper power supply
decoupling.

Another method of enhancing device performance is
power supply decoupling. Forthe HA-5033, it is recommended that the positive and negative power supplies
be bypassed with capacitors to ground. Ceramic capacitors ranging in value from .01 to .1 /IF will minimize
high frequency variations in supply voltage. Solid tantalum capacitors 1/lF or larger will optimize low frequency performance. It is also recommended that the
bypass capacitors be connected as close to the HAS033 as possible, preferably directly tothe supply pins.

Standard practice in RFlVideo layout is the use of a
ground plane. A ground plane minimizes distributed
circuit capacitance and inductance which degrade
high frequency performance. The ground plane can
also incorporate the metal case of the HA-S033, since
pin #2 is internally tied to package. This feature allows
the user to make contact between the ground plane
and the package which extends shielding, provides additional heat sinking and eliminates the useof a socket.
IC sockets contribute bandwidth limiting interlead capacitance and should be avoided.

Finally, keeping all lead lengths as short as possible
will minimize distributed capaCitance and reduce
board space. It is essential that the guidelines dis-

10-148

Application Note 548

co

~
It)

cussed above be followed to avoid marginal performance.

Figure 13 illustrates the gain peaking which occurs in
the 150MHz region.

Another consideration when applying the HA-5033 is
load capacitance. Although the HA-5033 is designed to
handle load capacitance values up to .01pF, it has a
worst case stability region in the area of 50pF. The computer simulation of the HA-5033 frequency response in

There are three suggested methods of dealing with this
particular characteristic of the HA-5033. Isolating the
load capacitance from the buffer output is the object of
the first method. This is accomplished by placing a
series resistor between the output and the load.

2.0-,--,....---,.--,.-r"T"'T"'T'T,....----,.-.-T""T'""'T"'T'T"T"T"--,.-·1-"-I,....-r-r"'T'T-r1

J

CL = 50pF

1.6

1.2

~
~

z

~

.80
CL = JOOpF

1\ CL =10pF

.40

FREUUENCY (H,)

FIGURE 13. COMPUTER SIMULATION OF HA- 5033
VS FREQUENCY AND LOAD CAPACITANCE

A second technique utilizes the HA-5033 frequency
response with respect to load capacitance. Referring
once again to Figure 13, notice that the gain peaking is
removed with additional load capacitance. This is the
basis of method two, adding additional load capacitance to approach a region of stability.

GAIN

CHARACTERISTICS

bility without sacrificing performance.
An explanation of why adding capacitance will stabilize the HA-5033 can be found in the Y parameter data
shown in Figure 14. The expression for the buffer gain
in terms of Y parameter is:
AV= VOUT = ~

A drawback to adding more load capacitance is that
the buffer's dynamic characteristic will degrade and
bandwidth performance will be less than data sheet
specifications. The third method solves this trade-off
by using a "bootstrap" technique of adding capacitance from input to output. This method achieves sta-

VIN

Y22 + YL

Y21 = Forward Transmittance
Y22 = Output Admittance
YL = Load Admittance

Y21.Y22

'80

!

10-1

¥"
;(,'2

~

~

Vll-

90

Y22

~ 10-2

~

IT

'3S

.... J~,

~- F

-

'S~-

'"

2'

w
0

T

l-

V22

r-

...z=> 10-3

,.""

-45
-90

'0-4

-135

V"

=-f

V'2
10-5

'0·

-180
1().

I

'07

'08

I

J1

~

1"'07

'0·

fREQUENCY Hz

*SIEMENS ",n-l

FIGURE 14. HA-5033 Y PARAMETER DATA

10-149

f'...~

,oS
FREQUENCY - Hz

I

r
i

iii

n
II
'0·

W

I-

o
Z

~

Q.

«

Application Note 548
Notice that the load admittance, Y22 , phase becomes
inductive (-jYL ; -900 ) at high frequency. 50 ifthe load,
YL, is capacitive ( + jY c ; +900 ) and the su m of Y22 + YL
become small, peaking occurs. Adding additional capacitance changes the effective phase angle and peaking can be reduced.
Using the HA-5033 as the analog input buffer of a flash
converter is an example of application where the suggested stabilization methods are useful. Although its
been stressed to keep all distributed capaCitance to a
minimum to optimize device operation, the load which
a flash converter presents to the buffer represents a
greater concern.
Flash or parallel converters are a special case, since
the analog input circuit must drive a non-linear input
impedanceS. This non-linearity is due to the potential
input impedance changes of the 255 parallel comparators which comprise the converter analog input. In ad-

CONVERT

~

dition to the non-linearity, the input capacitance of
these converters tends to be relatively large, 100-300pF.
Example of the various stabilization methods tested
with the TWR 1007 S bit video flash converter are
shown in Figure 15. Figure 15a illustrates the series resistor method. 15b is the load capaCitance method and
15c is the bootstrap method. Photographs of the experimental results show the analog input sampling convert signal (pin 30), the M5B digital output (01 pin 40),
and the buffer output (converter input).
It is recommended that a complete evaluation for each
method be conducted to determine the optimum component values. The value of the series resistor will depend upon the input capacitance of the particular converter used. A suggested starting value is500hms. With
the capacitance methods, the distributed capacitance
of the layout will affect component values. These experimental results were obtained using C ; 240pf.

~

OV

••v
-.RS

"SO
DIGITAL
OUTPUT

v"

28."
1l,1&,

..v

.....
41,41

12,1'
19,21

li,lI,W
YRT 11

~ -=

OV

-.!v
BUFFER
OUTPUT

OV
4

3 Z 1 >
(MS') !!

I

FIGURE 158. ENHANCING 5033 PERFORMANCE IN FLASH CONVERTER APPLICATIONS: SERIES RESISTOR METHOD

••v
CONVERT

OV

21,43

v,.

~:: ~:: 20

VHT 11

DIGITAL
OUTPUT

OV

·zv
BUFFER
OUTPUT

OV

FIGURE 15b. LOAD CAPACITANCE METHOD,

10-150

..v
47,48
49,50

12.1.
19,21

Application Note 548

co
"11:1'

lot)

W

....

CB 240pf

o

-6V

CONVER~

OV

28,43

41,48

>---<>----,-V"'-\13, IS, 49, SO
16,18,20

z

12,14
19,21

a:a.

«

VRT 11

DIGITAL
OUTPUT

OV

BUFFER
OUTPUT

OV
06
(LSB)

07 06 05 > 04 03 02 01 :>
:!
(MSBJ ~

:i

~

FIGURE 15c. BOOTSTRAP CAPACITANCE METHOD

The signal levels in most video applications are 1V p-p
or less. Although the HA-5033 was shown with ±15V
power supplies in the converter applications, lower
power supplies will accommodate these video signal
levels. For example, at ±5V power supplies. the HA5033 can swing ±2V into a 75 ohm load.
The HA-5033 is an excellent high speed line device
capable of driving 50 ohm and 75 ohm coaxial cable.

These type of drive requirements are common in video
circuit design. Figures 15 and 16 illustrate two typical
application examples. Figure 15 is an example of a 50
ohm system using the HA-5033 alone. Rm matches the
buffer output impedance to the cables characteristic
impedance. Depending upon the response required,
this resistor may not be necessary. If used, the output
voltage will be one half the input voltage.

VOUT

Rl
50\1

VOUT
POSITIVE PULSE RESPONSE
TA = 25 DC
RS = 50Q
RM=RL=50Q

NEGATIVE PULSE RESPONSE
TA = 25 DC
RS = 50Q
RM = RL = 50Q

\=

Vo = vIN/~ y, vlN
,ilL + RMJ

Vo =VIN/~\=Y,VIN
,ilL + RM)

FIGURE 15. VIDEO COAXIAL LINE DRIVER - 50 OHM SYSTEM

Figure 16 illustrates the use of the buffer within the
feedback loop of an operational amplifier. This configuration provides additional output current capability for the HA-2539 op amp and gives the designer voltage gain control.
Another application which utilizes the HA-5033's output drive capability is the high speed sample and hold
circuit shown in Figure 17. The input buffer provides
drive current tothe hold capacitor while the output buffer functions as a data line driver. The switching element in this application is the HI-201 HS high speed
CMOS switch which contributes it's own benefits to the
application9. Depending upon the application requirements, using the HA-5033 as the output buffer in Figure

soon
100n

FIGURE 16. VIDEO GAIN BLOCK

10-151

Application Note 548

17a may not be acceptable. Lab tests have shown that
the input bias current of the HA-S033 becomes a factor
for low values of hold capacitance « .0 1J.lF) during the
hold mode.

0,
R,

A solution is to add a low bias current F.E.T. input
stage, as shown in Figure 17b. 01 acts as a voltage follower and 02 is a current source. Matching 01,02 and
Rl, R2 are important considerations in order to minimize offset voltages.

VqUT

R3

RF

RL (SPEAKER)

R,

(b)
FIGURE 18. AUDIO DRIVERS

A common method of achieving an audio oscillator.circuit isto use a transistor or IC amplifier with LC or RC
feedback". An alternative technique of generating sinusoidal waveforms, using the HA-S033, is shown in Figure 19. Crystal oscillators offer improved frequency stability over time and temperature. This particular oscillator configuration 10 produces an 18.18 MHz,
2.8V p•p sinusoidal waveform into a 1K ohm load.

(a)

">--+-0

OUTPUT

-Vss
(b)
FIGURE 178. HIGH SPEED SAMPLE/HOLD (b) MODIFIED
OUTPUT BUFFER

When the drive capability of the HA-S033 is insuffi·
cient, consider adding an external output stage. Figure
18a illustrates an example where a push-pull complementary output stage has been added to the HA-S033.
Although unable to drive the low impedances of speakers, typically 4-8 ohm, the buffer can be used to drive
audio output transistors. A variation of this configuration is shown in Figure 18b, where separate buffers individually drive each transistor base. A low noise input
stage is provided by the HA-Sl02.

R'

FIGURE 19. CRYSTAL OSCILLATOR: ±V
C2 = 39p!; 18MHz QUARTZ CRYSTAL

= ±15V, C1 = 12p!;

Conclusion
The HA-S033 is a high performance integrated circuit
presently being utilized in a wide variety of applications. This paper has provided additional information
to aid designers in applying the HA-S033 video buffer
in future applications.

References
Vo

R3

-Vee

(a)

Rl (SPEAKER)

1. Thermalloy Semiconductor
Accessories Catalog
Thermalloy Inc. Dallas, Texas.
2. Heat Sink/Dissipator Products and
Thermal Management Guide
I nternational Electronic Research Corp.
Burbank, California

10-152

Application Note 548

co
~

U')

Further Reading

3. William L. Hughes, "Television
Fundamentals and Standards"
Electronic Engineers Handbook ed.
Donald G. Fink
(McGraw-Hili, 1975) p. 20-3

1. "TVlVideo Sync Primer", Hewlett-Packard
Product Note 005-1,1981.
2. Stu Rasmussen and Clifford B. Schrock
"Television Operational Measurements,
Video and RF for NTSC Systems"
Tektronix, 1980.

4. "VITS Analysis for TV Screening"
Tektronix Application Note #T900, 1978
5. "Video Facility Testing/Technical
Performance Objectives." NTC
Report No.7, Published by the
Public Broadcasting Service for the
NTC, 1976.

3. "Electrical
Television
Electronic
RS-250-B,

Performance Standards for
Relay Facilities"
Industries Association Standard
1976.

4. L. E. Weaver, Television Video
Transmission Measurements,
(London, Marconi Instruments, 1971).

6. Tektronix 1984 Product Catalog.
7. Marconi Instruments 1983-84
Product Catalog.

5. F. F. Mazda, ed., Electronic Engineers
Reference Book,
5th ed. (London Butterworth, 1982).

8. "Monolithic Video ND Converter",
TRW TDC1007J Data Sheet, 1978.

Acknowledgements

9. "New High Speed Switch Offers Sub-50ns
Switching Time"
Harris Application Note 543,1983.

1. Technical contributions of John Prentice
and Robert Junkins.

10. Tor Hougen, "Keep Your Oscillator
Simple", EDN, June, 1984, p. 236-238.

2. Sales and Technical Staff of
Marconi Instruments.

NOTICE: Information cont~ined in application notes is intended solely for general guidance; use of the information
for user's specific application is at user's risk.

10-153

W

I-

o
Z
a.:
D..
«

APP
NOTS

FOR YOUR INFORMATION

Harris Analog

No. 549

THEHC~550X

TELEPHONE SUBSCRIBER LINE
INTERFACE CIRCUITS (SLlC)
Geoff Phillips, C. Eng., M.I.E.E.

1.0 Introduction
This note will describe each subfunction of the SLiC
and will discuss several system design features,
including balance networks and complex Impedance
matching.

The HC-550X family of telephone subscriber line
interface circuits (SLlC) integrate most of the
BORSCHT functions of the traditional hybrid and
transformer interface circuits onto one chip. The
circuits are manufactured in a 200V dielectric isolation
(01) process and together with a secondary protection
diode bridge give 1 kV of isolation from lightning
induced faults between the subscriber loop and the
telephone office.

2.0 An Overview of the Basic Phone
Loop And Its Environment
Figure 1 illustrates a simplified telephone network.
Each subscri ber is connected via a 2 wi re (2W) loop to a
switch office which provides intersubsciber loop
switching and signal processing (analog and/or
digital).

The BORSCHT functions provided are:
• BATTERY FEED WITH LOOP CURRENT
LIMITING
• OVERVOLTAGE PROTECTION
• RINGING
• SUPERVISION/SIGNALING
• HYBRID

The SLiC is the primary interface between the-4 wire
(4W) (ground referenced) low voltage switch
environment and the 2W ("floating") high voltage loop
environment.

The HC-5502A is intended for use in systems utilizing
single ended tip (positive side) injected ringing and
limits the short loop current to 30mA; the HC-5504 is
intended for use in ring side (negative side) injected
ringing systems and will limit the short loop current to
40mA. It should be noted that the HC-5504 can also be
configured to operate in switches employing either of
the two single ended ringing methods and in balanced
ringing systems.

The loop consists of a wire A (the tip wire), the
telephone set or its equivalent, and wire B (the ring
wire). A DC voltage is applied across the tip and ring
wires at the line card which is housed in the telephone
office: The battery is usually a nominal -48V, and is
often called th~ quiet or talking battery. When the
telephone is off-hook, a DC path is established around
the loop. DC loop current will flow around the loop
from tip feed to ring feed. This is called Battery Feed.

BIDIRECTIONAL
4

RING
~........;.GE;;;N~ER;.;;A.;.:.T.;;.;OR.;........

~

I

+ITlP

'~\
TELE-

PHONE
SET OR
DA.A.

TIP LINE

I

I+-

HI-+-+--

=--..-i1=,.."..,.,.,,-:---+--f
' ~RING LINEI
+IRING

SUBSCRIBER LOOP
TWO WIRE
(2W)

,

I

----J

II

TRANSMIT (TX)
SIGNAL

(H9X),

I

ONE CHANNEL OF
LINE CARD

I

---II----.-+I. ....

---FOUR
(4W) WIRE
~

FIGURE 1. SIMPLIFIED TELEPHONE NETWORK.

10-154,

SWITCH

TELE~ONE
OFFICE

)

Application Note 549

en

The SLiC must be able to sense this DC current and
flag the switch controller: This is referred to as Switch
Hook Detection (SHD). It tells the switch controller
that the line is busy, and is a supervisory function.
The subscriber set is often located very close to the
switch office. Thus, the loop resistance will be very low
and the SLiC should incorporate a feedback network
that will limit the loop current to a specified maximum
to prevent battery power drain and minimize power
dissipation at the board level. The HC-550X SLiCs
sense the loop current and adjust the voltage on the
ring side of the line to cause line current saturation.
The telephone can be rung by switching a ring relay to
connect a ring generator to the loop. The on-off
switching of the relay (cadencing) is controlled by the
Ring Command (RC) input which gates the relaydriver
output. When the user answers the telephone, the ring
relay is automatically tripped, the ring command signal
is inhibited and the 2W loop is made ready for voice
transmission. Voice signals are transmitted onto the
loop by directly modulating the DC feed. This AC voice
signal is coupled to the users earpiece via a transformer in the telephone set. Voice transmission forthe
2W to the 4W system is called the hybrid function. For
2W to 4W transmission, the subscriber talking into his
set modulates the resistance of the telephone microphone. This causes AC current in the loop which is
sensed by the SLiC and transmitted as a ground referenced voltage signal to the signal processing electronics within the switch.
Subscriber loops are usually measured in terms of loop
resistance. The nominal loop length is 1200 ohms.
Owing to the length of the lines and their location near
power lines, common mode or longitudinal currents
are often induced. The SLiC has to distinguish
between these noise Signals (longitudinal) and the
transversal signals, and reject the unwanted longitudinal components: this is a measure of the SLiC's
longitudinal balance. The primary noise sources are
60/50Hz power lines, cable cross talk, and R.F.
transmissions. The Harris SLiCs will accomodate
15mARMS of noise currents on each side of the loop.
The line is also subjected to lightning strikes. Together
with primary and secondary protection networks, the
SLiC must withstand 1kV peak of lightning induced
energy. In fact, the plastic encapsulated Harris SLiC
can withstand a 1kV peak strike with a small signal
diode bridge providing voltage clamping, and current
steering.

3.0 The Harris HC-550X
The HC-550X family of SLiCs are primarly intended for
use within Private Branch Exchanges (PBX) although they can be used in the larger switch networks
found in Central Offices (C.O.).

10-155

"It'

Figure 2 shows the functional schematic of the SLiC.
The subfunctions to be described are:

It)

A. Line Feed Amplifiers
B. Transversal Amplifiers
C. Loop Current Limiting: Metallic, Fault and
Thermal Limiting
D. Ring Trip and Ground Key Detection
E. Spare or Uncommitted Operational Amplifier
F. Logic Network

o

3. 1 Line Feed Amplifiers
The line feed amplifiers are high power op amps, and
are connected to the subscriber loop through 300
ohms of feed resistance; the configuration is shown in
Figure 3. The feed resistors provide a 600 ohm balanced load for the 2W to 4W transmission, and limit
longitudinal currents; the two resistors immediately
adjacent to the feed amplifiers function as sense resistors for 2W to 4W transmission and Signalling
purposes.
The tip feed amplifier is configured as a unity gain
non-inverting buffer. A -4V bias (derived from the
negative battery (VB-) in the bias network) is applied to
the input of the amplifier. Hence, the tip feed DC level is
at -4V. The principal reason for this offset is to
accomodate sourcing and sinking of longitudinal
noise currents up to 15mARMS without saturating the
amplifier output. The tip feed amplifier also feeds the
ring feed amplifier, which is configured as a unity gain
inverting amplifier as seen from the TF amplifier. The
non inverting input to the RF amp is biased at a VB-/2.
Looking into this terminal the amplifier has a non inverting gain of 2. Thus, the DC output at ring feed is:
VRF(DC)

=

(4 + VB-) Volts

For a -48 volt battery, VRF = -44 volts. Hence, the nominal battery feed across the loop provided by the SLiC is
40 volts. When the subscriber goes off-hook this DC
feed causes current (metallic current) to flow around
the loop.
The received audio Signal VRX from the switch is fed
into the tip feed amplifier and appears at the TF terminal. It is also fed through the ring feed amplifier and is
inverted. Thus, a differential signal of 2VRX appears
across the line: for a 600 ohm line this compensates the
6dB loss due to the 600 ohms of line feed resistance.
The VRX signal causes AC audio currents to flow
around the loop which are then AC coupled to the earpiece of the telephone set. Figure 4 shows the single
ended AC equivalent circuit of the subscriber loop for
voice transmission. In the general case the signal design equation for 4W to 2W transmission is given by:
VLlNE = (

ZLiNE
)
600 + ZLiNE

x 2VRX

W

~

z

a.:

Il.

O.
FOR KVTX < VB5

VRF

VTX = 2(ITIP + IRING) (RB2+ RB4)
where ITiP and IRING are assumed positive as
indicated in Figure 1. This DC level is used as an input
to a comparator whose output feeds into the logic
circuitry as SH. This signal is used to gate SHD.

10-157

Vii 12

FIGURE 5.

LOOP CURRENT LIMIT CONTROL.

'¢
It)

w

I-

o
Z

a.:

D.
c(

Application Note 549
output of the amplifier after being filtered by R20 and
C4 to attenuate AC signals is fed into a detector whose
output GK gates the necessary logic to drive GKD or
inhibit the ring relay driver to remove ringing signals
from the line in an off-hook condition. In order to prevent false ground key owing to line noise or during ring
trip, the internal GKD logic is delayed via C2. An internal current source of 511A has to charge C2 up to a 5V
level before allowing the ground key signal to propagate. Thus, for C2 ~ 0.15I1F, a delay of 150ms is established.

'LOOP
(rnA)

"B =12V

40 +---"-,,~504'LOOP SATURATION

Vii =-48V

"'"

30 + - - - - - - . . . . 3 0 , . HC-5502A 'LOOP SATURATION

20

Ringing the line and Ring Trip Detection are discussed
more fully in Section 4.

RLOOP = (RFl + RF2 + HF3 + RF4 <' RLiNE + RSET)
10~+-~~~-+-+-P~~~~+-~~~-+-+~-

600

800

lK

UK

1.4K

1.6K

1.8K

2.0K

2.ZK

2.4K RLOOP

(m
FIGURE 6.

DC LOOP CURRENT CHARACTERISTICS.

generated in the bias network, and is equivalent to
30mA or 40mA loop current, typically, for the
HC-5502A and HC-5504, respectively. When the
metallic input exceeds the set reference level, the
transconductance amplifier sources current. This
current will charge C3 in positive direction causing the
RF (Ring Feed) voltage to approach the TF (Tip Feed),
effectively reducing the battery feed across the loop
which will limit the DC loop current. C3 will continue to
charge until an equilibrium level is attained at ILOOP =
ILOOP MAXmA. The time constant of this feedback
loop is set by R21 (90K ohm) and C3 which is nominally
0.33I1F.
The RF voltage level is also modified to reduce or
control loop current during ring linefaults (e.g. ground
or power line crosses), and thermal overload. Figure 2
illustrates this. It can be seen that the thermal and fault
current circuitry works in parallel with the transconductance amplifier.

3.4 Longitudinal Amplifier
The longitudinal amplifier is an op amp configured as a
closed loop differential amplifier with a nominal gain of
0.1 (HC-5504) or 0.581 (HC-5502A). The output is a
measure of any imbalance between ITIP and IRING as
described in Figure 1. The transfer function of this
amplifier is given by:
VLONG

~

K(ITIP - IRING)150

Where K is the gain factor of the amplifier. The gain
factor is much Jess than one since ring voltage (up to
150Vpea k) can appear at the Ring or Ring Feed Sense
terminals and are attenuated to protect the amplifier.
The longitudinal amplifier's principle functions are
Ring Trip Detection (RTD) and Ground Key Detection
(GKD). GKD provides a means for the subscriber to
flag a PBX attendant and is used extensively in Europe:
The ring line is grounded at the telephone set via a
push switch incorporated within the telephone. This
causes a DC current imbalance between the tip and
ring sides of the loop which gives rise to a negative voltage at the output of the longitudinal amplifier. The

10-158

3.5 Uncommitted Op Amp
An uncommitted op amp is provided on the chip. This
is a standard op amp with an output swing of ±5V. It is
primarily intended to be used to balance the
transhybrid return signal discussed in Section 3.2
above. The amplifier has an offset voltage of 10mV; an
open loop gain of 66dB; a GBW product of 2MHz; slews
at 1V/l1s typically, and has a ±2mA output current drive
capability.

3.6 The Logic Network
The logic network utilizes 12L logic. All external inputs
and outputs are LS TTL compatible: the relay driver is
an open collector output that can sink 60mA with a
VCE of 1V.
Figure 7 is a schematic of the combination logic within
the network. The external inputs RC (Relay Control)
and PO (Power Denial) allow the switch controller to
ring the line or deny power to the loop, respectively.
The Ring Synchronization input (RS) facilitates
switching of the ring relay near a ring current zero
crossing in order to minimize inductive kick-back from
the telephone ringer.
The internal inputs SH and GK control ring trip and
provide supervisory flags to the system controller via
the Switch Hook Detect (SHD) and Ground Key Detect
(GKD) outputs.

4.0 Designing with the Harris SLie
General application circuits for the HC-5502A and
HC-5504 SLiCs are given in Figures 8 and 9. In this
section, several specific design and application areas
will be discussed:
A.
B.
C.
D.
E.

Ringing the Line
Power Denial
Transhybrid and Longitudinal Balance
Complex Impedance Matching
Surge Protection

4.1 Ringing The Line
The HC-5502A is used for tip injected ringing (also
called Single ended ground referenced ringing), and
the HC-5504 is used for ring injected or single ended

Application Note 549
C»

~

_ _ _ _ _ _ _ _-ICE,XT

~
it)

W

I-

o
Z

c.:a..

c(
16)Kr----4-+--------+---+-------------~

FIGURE 7.

HC-5502A104 LOGIC GATE SCHEMATIC.

RING

+12 ± 1.2V

-42 TO -S8V

ICD

NOTES:
Cl is an optional capacitor used to improve +12V supply rejection. This pin must be left
open if unused.

TYPICAL COMPONENT VALUES

Cl ~ O.5M,o---- -

FIGURE 7. SUMMING AMPLIFIER FOR COMPOSITE VIDEO PLUS CLAMPING CIRCUIT

One drawback resulting from the algebraic Rddition of the
input waveforms is the requirement that each input
component exist only during the period that it is needed in
the composite signal. An example of this is the color burst
which can be present at its input terminal only during its
portion of the composite signal since no gating circuitry is
available.
The multiplexer circuit in Figure 8 can be used for video
signal construction by gating each component through to
the HA-2541 as it is required. The inherent channel separation of the multiplexer allows each component of the
composite signal to be continuously present at the input.
This has several important implications. The first is that
the duration of each component of the signal is precisely
controlled by a digital timing chain (which can be easily
reproduced at remote locations with high precision).
Second, the only analog signals needed are the color
burst and the picture information. All reference signals
such as the horizontal synchronization, the 0 volt
reference, and the previously unmentioned vertical
synchronization signals can be simulated with accurate
DC references. These are gated, along with the other
components, to form the composite video signal.

synchronization pulse. The new pulse will enable switching equipment to combine the separate signals for
whatever effect is needed.
It should be noted that widely varying horizontal speeds
may necessitate the use of analog delay chains with the
synchronization technique. This will produce pictures of
compatible quality and proportion (vertical speed is more
constant and contains a dead zone for any differences,
vertical retrace).

An extension of the multiplexed signal construction
technique is a type of signal modification. When several
cameras are used together without a common synchronization signal, they are not easily combined for special
effects and switching. A solution to this problem would be
to strip the synchronization pulses off of each of the incoming camera waveforms and apply a new common

10-176

ALL RESISTORS 5Kl!
SWITCHES HI·5051

FIGURE 8. MULTIPLEXING WITH HA-2541

Application Note 550

oII)

HA-53Z0

The multiplexer system used for video signal construction
has other applications of interest. The concept of combining several channels into one can be reversed to form a
demultiplexer, where the function is to take several combined channels and separate them into their original form.
This type of application can be implemented to solve
some well-known industrial problems.

II)

W

t-

O
Z

Q.
Q.

HA-5320

5K

IK

12VDC
PANCAKE
TYPE
/

FIGURE 14. CONTROLLING DC MOTOR SPEED WITH HA-2542

10-183

+5

+5

APP
NOTS

FOR YOUR INFORMATION

Harris Analog

No. 553

HA-5147, ULTRA LOW NO,ISE AMPLIFIER
By Alan Hansford

Introduction
Engineers interested in precision signal processing will
find the HA-5147, with its unique features, very interesting. Utilizing an advanced design with special device
geometries, the HA-5147 has moved the Harris dielectric
process into a new arena of both speed arid precision.
Perhaps one of the most remarkable features of the
HA-5147 is its ultra low noise performance, which makes
it the first monolithic amplifier to combine speed, precision, and ultra low noise operation (Figure 1).
To realize Ihis device, Inlense allenllon was given 10 Ihe
"lola I" design from inpul 10 oulpul (Figure 2).
The input stage consists of a cross-coupled differential
pair which provides a very high CMRR (125dB) through
the use, of CASCODE circuits. Effective use of the bias
current cancellation scheme also keeps the bias currents
to a mere 10nA. With laser trimming of the load resistors
Rl and R2, the offset voltage is kept below 25fJ.V at 25 0 C.
The entire input stage has been optimized for low noise
operation and is largely responsible for the amplifier's
ultra low noise voltage of 3.0nV/jHZ@ 1KHz. Low frequency noise, on the other hand, is particularly important
in DC applications and the HA-5147's 2.7Hz lower noise
corner will prove quite beneficial for many users.

The loading on Rl and R2 is kept to a minimum through
the use of emitter followers between the input stage and
the second differential pair. C4 provides a feedforward
path around the second stage at high frequencies and
feeds into the level shifter and current mirror section. This
portion of the design provides a differential to singleended conversion and relies on C2 to tailor the rolloff of
the second stage. Two vertically-constructed PNP transistors within the level shifter dramatically increase the
frequency response of the amplifier compared to that of
other construction techniques.
Emitter foll·owers in the fourth stage reduce the capacitive
loading effects of Cl by providing a separate driver for Cl
and the. output stage. The output stage here is a high
speed buffer that employs complementary transistors as
well as short circuit protection.
The high performance features of the HA-5147 have quite
clearly moved this device closer to the "ideal" than any
other amplifier in its class. Yet, with some simple external
components,' this device can be positioned even closer to
the "ideal." An offset nulling potentiometer can reduce
Vos (Figure 3a), while the already hefty output stage
(lout = 20mAmin) can be boosted without reducing the excellent speed and bandwidth characteristics (Figure 3b).
HA-5l47

PRECISION

OP-J7
Vo,
Vo, DRIFT
Vo, TEMPCO
Ibias
10 ,

NOISE VOLTAGE
NOISE CURRENT
OPEN LOOP GAIN
CMRR
PSRR
GAIN BANDWIDTH
SLEW RATE
POWER BANDWIDTH
POWER CONSUMPTION

25jlV
1IlV/mo.
O.2/lV/C
:tl0nA
±7nA
J.OnV/$.
O.4pA/yIiZ
1.8V/j./V
l26dB
l20dB
6JMHz
17V~'

270KHz
90mW

PRECISION
WIOEBANO

WIOEBANO
HA - 2620

25/lV
l/lV/mo.
O.6j./V/C
±8nA
tl0nA
J.OnV/$.
O.4pA/$
1.8V/j./V
l25dB
lJOdB
l20MHz
J7V/Il',
560KHz
85mW

4mV
10j./V/mo.
5j./V/C
±lnA
:tlnA
l6nV/ffz
1.6pA/JHZ
O.15V/j./V
100dB
90dB
100MHz
J5V~'

550KHz
90mW

FIGURE 1.
The HA-5147 combines the qualities of precision Op Amps with those of the wideband speed category.

10-184

Application Note 553
C")
U')
U')

w

I-

o
Z

Il.
Il.

10

FIGURE 3a.

FIGURE 3b.

Nulling the HA·5147's offset voltage to 0 volts brings it closer to "ideal"

The HA·5147's output current can be boosted to ±100mA by using the
HA-5033. AC performance is not affected.

Low Noise Design
Since the HA-5147 is a very low noise operational amplifier, low noise design techniques must be used to make
the most of this feature. There are two primary means of
keeping noise down, one requires the amplifier inputs to
look. into low source resistances and the other requires
bandwidth limiting by filtering. A short outline of noise
prediction will be presented here to support these
concepts.

As an illustration of noise prediction, the noise density for
the standard inverting amplifier configuration (Figure 4a)
will be determined. The total noise is derived from the
combination of several noise sources, only three of which
are of any significance. These are the amplifier's noise
voltage, the thermal noise of the feedback components,
and the noise generated by the current noise of the amplifier within the feedback components.

Noise can be divided into several categories, which include thermal noise (white noise) and flicker noise (pink
noise or 1/f nOise). The feedback components are
strongly dominated by thermal noise making thermal
noise the most important of these from a system design
standpoint (an exception to this are high gain DC amplifiers which require low 1/f noise as measured by the
noise corner"). Flicker noise is more a function of the
amplifier construction quality, and system design variations are less effective in reducing this type of noise.

The total noise is defined as the square root of the sum of
the squares of the individual noise terms.

Noise is usually rated in oneof two ways. The first is RMS
voltage or current (a measure of peak-to-peak noise in a
given bandwidth) and the second is by noise density
spectrum in VI
and A/,fHi. (a measure of the spectral
content of the noise in the frequency domain). The two
rating schemes are related, with RMS noise levels
generated from the integration of the noise density
spectrum over a desired frequency bandwidth.

fRZ

En: G

(Eamp)2 + (E feedback)2 + (Ecurrent noise in)2
network
feedback network

En : total noise
G : gain of stage
Eamp : amplifier noise voltage ........ 3.0nv/jH;" @ f
Efeedback
network

=

J 4KTReq

where...

> 1KHz

K: 1.381 E-23
T: 300
Req = R II Rt

E current noise in = Inoise Heq
'noise: 0.4PA/~ @ f > 1KHz

feedback network
or more specifically ...
En: G

10..:185

J (Eamp)2

+

Req4KT

+

(I noise Req)2

en

g:~

«0
2:

Application Note 553
RI

12

10

a
RI
VOLTAGE NOISE

11111111

c.l.w~m"
1111111

DC BIAS CURRENTS

10

100

OPTIMIZED IF
Req=RIIRI=Rc

1K

10K

lDOK

1M

FREOUENCY _ Hz

b
FIGURE 4. NOISE PREDICTION CIRCUITS

FIGURE 5. HA-5147 NOISE CHARACTERISTICS

A reasonable estimate of noise levels can be generated with these two
basic amplifier circuits.

The HA-S147's exceptional noise characteristics may be used to improve

Both the amplifier noise voltage and noise current are
constant above 1KHz and rise slightly for lower frequencies (Figure 5). The resistor thermal noise is derived
from the parallel combination of the feedback network
(Req) and several constants (4KT). The third noise term
again uses the equivalent resistance of the feedback network (Req) as well as the current noise generated at the
input terminals of the amplifier.

existing and new high quality audio systems.

RMS noise is derived in part as the integral of the noise
density spectrum over a given bandwidth. Below is the
complete expression ...

Erms (from fO to f 1)

~

r

E noise

2 df

density
spectrum

.IfO
It should be evident from the above formula that extremely large values of Req (especially over 10Kohm) will
dominate the noise density while low values for Req will
yield to the amplifier's own noise characteristics. Note
the asyptotic convergence of the noise voltages in Figures
3a-3c at low values of Req.
A second circuit (Figure 4b) balances the effects of input
bias currents by placing a resistor Rc , equal to Req , between the non-inverting input and ground. While reducing
DC errors, this configuration adds two additional terms to
the noise formula.
En

~

G

(Eamp)2

+

Req4KT + (Inoise Req)2
+ Rc 4KT + (Inoise Rc)2

The original contributors to output noise remain as before
and the additional terms represent the thermal contribution by Rc and the associated amplifier current
noise seen through that resistor. To optimize DC design,
Rin II Rf ~ Req ~ Rc , therefore the noise density equation
reduces to ...
En

~G

V

(Eamp)2 + 2Req4KT + 2(lnoise Req)2

Again the relationship between large values of Req and a
high noise density spectrum remains.

The strict integration assuming En is constant works well
forfo above"" 1KHz. Both the amplifier's noise voltage
and the noise current increase for frequencies below
1KHz. This makes for difficult integration since complicated expressions for Inoise and Eamp must be
generated. To avoid this problem, graphical integration
techniques or sampled methods can be used with great
success.
The curves in Figures 6a-6c illustrate the relationship
between the RMS noise and Req for both amplifier designs. It should be apparent from the predicted RMS noise
curves that increased bandwidth causes an increase in
noise voltage. An interesting effect of this relationship is
that only absolute bandwidth (f1-fO) is important. The
general frequencies of interest (if they are above 1KHz)
are irrelevant. More simply, 100Hz of bandwidth near
10KHz contains as much noise as 100Hz of bandwidth
near 1MHz. This implies that bandwidth should be restricted with' appropriate high and low pass filtering, if the
lowest noise voltages are to be attained.
Ftom the previous discussion, it is apparent that low noise
designs require low resistor values. This is not to say that
high gain should be avoided, just that low input and
source resistance values are required for low noise opera-

10-186

Application Note 553
C")
II)
II)

W

t-

O
Z

D.
D.
c(

FIGURE 6a. PREDICTED NOISE
Predicted RMS noise at output for bandwidth of 10KHz· 500KHz for HA·5147.

"

~.: :
~"''''''''''''
. 'T11
II

~

_

"

-=-

_.

-=-

R'q-RIIAf

=-rf~;

,

="

V.

+

KA-5147

.

""c:'

A-5141

'Tn; 1
I

11

t

i

,

j,

~

+-+

Ii

!-

-

%

lil Hf, -I

-

~

-

'i,

otT

-

=11

I

'it

-

I

FIGURE 6b. PREDICTED NOISE

FIGURE 6c. PREDICTED NOISE

Predicted RMS noise at output for bandwidth of 20Hz - 20KHz for HA-S147.

Predicted RMS noise at output for bandwidth of 10Hz -1 DOHz for HA-S147.

R6
"VALUE CHOSEN TO
PROVIDE ADEQUATE
DC BIAS CURRENT

10K

E

,.xi.o.

CMRR AT 2KH' .

==
FOR THIS CIRCUIT,
Av=100
USE 0.1%

META~

..

FILM RESISTORS.

FOR BEST CMRR MATCH R4/R6 AND R5/R7.

R2 CAN BE MADE ADJUSTABLE.

~~
10

"

'OK

tOOK

~.

FREQUENCY - Hz

FIGURE 7. INSTRUMENTATION AMPLIFIER

FIGURE 8. HA-S147 CMRR VS. FREQUENCY

Thanks to higher speed and more bandwidth, this standard three amplifier

The instrumentation amplifier's maximum CMRR can now be moved to
much higher frequencies when using the HA-5147.

instrumentation amplifier will have 10MHz bandwidth and 550KHz power

bandwidth.

tion. Closer examination of the RMS noise formula will
also show that limiting bandwith, with filtering, will also
reduce noise levels. Additionally, metal film and wirewound resistors have lower excess noise (a component of
resistor noise in addition to thermal noise) than carbon
resistors and are therefore preferred.

Applications
Heavily used throughout the world of signal processing is
the instrumentation amplifier and it is this particular cir-

cuit that can best utilize all of the features of the HA-5147.
By using the HA-5147, the standard 3 amplifier instrumentation circuit (Figure 7) is now able to extend its
bandwidth to 10MHz or its power bandwidth to 500KHz.
Additionally, the maximum CMRR (>120dB) is extended
to higher frequencies (Figure 8). Other "error producing"
input referred parameters of the HA-5147 such as noise,
Vos, Ibias, Vos drift and temperature coefficients have
been minimized, thus maximizing the capabilities of this
application.

10-187

Application Note 553
RI

...-------_---'lM~---,
R;

Eo

=Vrel

(I+RI/R; 10/4

FIGURE 9, LOW LEVEL BRIDGE AMPLIFIER
Very small bridge signals are sensed and amplified accurately when using
the precision performance of the HA-5147

Another circuit requiring very accurate amplification of its
signal is the transducer bridge amplifier (Figure 9). The
HA-5147, shown in an inverting bridge amplifier configuration, is recommended when it is necessary to detect
very small bridge level signals. Its high open loop gain
(>120dB), low noise, and excellent values for Vos, Vos
drift, and bias current provide exceptional sensitivity to
the smallest transducer variations. Full scale calibration
of this circuit is made possible by placing a small valued
potentiometer in series with Ri. Nulling is accomplished
with R2.

The high slew rate (37V //1s) and the excellent output current drive (±20mA min.) make HA-5147 highly suitable as
an input output buffer amplifier for analog multiplexers
(Figure 10). The precision input characteristics of the
HA-5147 help simplify system "error budgets" while its
speed and drive capabilities provide fast charging of the
multiplexer's output capacitance. This eliminates any increased multiplexer acquisition time, which can be
induced by more limited amplifiers. The HA-5147
accurately transfers information to the next stage while
effectively reducing any loading effects on the multiplexer's output.
Staying within the realm of signal processing, another
standard and much used circuit configuration can be
enhanced by the speed and precision of the HA-5147. A
precision threshold detector (Figure 11) requires low
noise, low and stable offset voltage, high open loop gain,
and high speed. These requirements are met by the
HA-5147, while adding excellent CMRR and PSRR to the
list. The standard variations of this circuit can easily be
implemented using the HA-5147. For example, hysteresis
can be generated by adding R1 to provide a small amount
of positive feedback. The circuit becomes a pulse width
modulator if Vref and the input signal are left to vary.
Although the output drive capability of this device is excellent, the optional buffering circuit may be used to drive
heavier loads while preventing loading effects on the
amplifier.

RI

R;

Av = I+RI/R;
TRANSDUCER
INPUTS

ANALOG MUX

RI

R;

RI

ADDRESS INPUTS
RI

FIGURE 10. HIGH SPEED INPUT/OUTPUT ANALOG MULTIPLEXER BUFFERING
Reduced "error" budgets and higher speeds of operation are easily achieved when the combined speed and
precision of the HA-5147 are used in these buffer amplifier applications.

10-188

Application Note 553
M

It)
It)

*I.NPUT RESISTORS NECESSARY IF DIFFERENTIAL
INPUT VOLTAGE EXCEEDS ± IV.

R*

-,

r- ,

2N;:04

,

2N222Z

,

SIG.IN 0--'1/\/'..-..-1
R* I
I
L- _

I

I

I

I

--¥I'v-- ....J

Rl
(OPTIONAL FOR HYSTERESIS)

TAPE
HEAD

I

I
L

-=

r·
l/lf

I

> --I

*OC BLOCKING CAPACITOR, OPTIONAL,
TO BLOCK OUTPUT OFFSET VOLTAGE
IF HA-5147 IS NOT NULLED.

I

~
O.OI/lf
R2
5.3K

J

OPTIONAL OUTPUT
BUFFERING CIRCUIT

FIGURE 11. PRECISION THRESHOLD DETECTOR

FIGURE 13. PROFESSIONAL AUDIO NAB TAPE PLAYBACK
PREAMPLIFIERS

This device can be used to increase response times while maintaining
precise detection.

This NAB tape playback preamplifier fully utilizes the speed, bandwidth,
and noise features of the HA-5147

Engineers working with professional audio designs will
find the HA-S147 highly desirable for many of their applications. With its exceptional noise characteristics (Figure
5), wide power bandwidth (500KHz), and modest power
consumption (8SmW), this device can be used as a high
quality audio preamplifier or as an intermediate stage
gain block. A circuit similar to that in Figure 3b can be incorporated into studio or stage monitors.

An audio circuit which can make maximum use of the
speed, bandwioth, and low noise of the HA-S147 is the
NAB tape playback preamplifier (Figure 13). This circuit is
configured to provide low frequency boost to 50Hz, flat
response to 3KHz, and high frequency attenuation above
3KHz. Compensation for variations in tape and tape head
performance can be achieved by trimming R1 and R2.

The audio preamplifier of Figure 3b has a limited output
current range. The audio power amplifier in Figure 12
overcomes this limitation and can provide an even greater
boost to the HA-S147. 01 and 02 are a complementary
pair arranged in a push pull manner, with R1 and R2 providing the necessary drive current. The maximum output
voltage corresponds to the minimum output current since

Signal generation applications will also find this high
precision device useful. As an astable multivibrator
(Figure 14) the power bandwidth of the HA-S147 extends
the circuit's frequency range to approximately SOOKHz. Rt
can be made adjustable to vary the frequency if desired.
Any timing errorsdueto Vos or Ibiashave been minimized
by the precision characteristics of the HA-S147. 01 and
02, if used, should be matched to prevent additional
timing errors. These clamping diodes may be omitted by
tying Rt and the positive feedback resistor Rf directly to
the output.

(1S-Vbe-Vo)/R1
is the drive current to the transistors. 01 and 02 insure the
proper biasing of the transistors as well as a clean crossover from 01 to 02.
+15

Rl
(-400KHz) where Fo-1/2RtCt
HIGH POWER OUTPUT
INPUT

0--..,....---1

01
lN914
lN914
02

50K

LOW LEVEL SIGNAL
TO ADDITIONAL AMPLIFIER

249
R2

01

10K
lK

02

FIGURE 12. HIGH POWER AMPLIFIER

FIGURE 14. ASTABLE MULTIVIBRATOR

The additional drive capability of the power transistors allows the HA-S147
to drive very heavy loads.

Higher frequencies of operation and reduced timing errors make the
HA-5147 an attractive building block in signal generation applications.

10-189

W

I-

0

Z

c..
c..

 1KHz

+

(Inoise Req)2

> 1KHz

Application Note 554
noise seen through that resistor. To optimize DC design,
Rin
Rf ~ Req ~ Rc , therefore the noise density equation
reduces to ...

II

(.1

En

J (Eamp)2

~G

~
lI)
lI)

W

I-

o

+ 2Req4KT + 2(lnoise Req)2

Again the relationship between large values of Req and a
high noise density spectrum remains.

Z

a:

Q.

«
~
~I'l

(bl

R,

~
-=-

-=-

Roq~ AliA!

./

FIGURE 1.
Ibl

A reasonable estimate of noise levels can be generated with these two
basic amplifier circuits.

Both the amplifier noise voltage and noise current are
constant above 1KHz and rise slightly for lower frequencies (Figure 2). The resistor thermal noise is derived from
the parallel combination of the feedback network (Req)
and several constants (4KT). The third noise term again
uses the equivalent resistance of the feedback network
(Req) as well as the current noise generated at the input
terminals of the amplifier.
NOISE VOLTAGE
00.

HA~5112114

1.1

IbI

I UJ.U. t;:::-h411111111

10,"Vrm

HA-51021114

R,

~
R,

'"

I IIII

',',m ,

00

00.

+R.... RII A,oRe

ill

R.,,,R.,'R,

"

IIII

'OK

00.

FIGURE 3a. PREDICTED NOISE
Predicted RMS noise at output for bandwidth of 0.1Hz-50KHz for
HA-5102/04 and 0.1Hz-250KHz for HA-5112/14.

NOISE CURRENT

•

00.

nvtv'Hi

NOISE CURRENT

pA/v'Hi

I~
NOISE VOLTAGE

llll

,

111111
00

'OK
FREOUENCY

FIGURE 2.
Noise current and voltage for HA-5102/04/12/14.

FIGURE 3b. PREDICTED NOISE

It should be evident from the above formula that
extremely large values of Req (especially over 10Kohm)
will dominate the noise density while low values for Req
will yield to the amplifier's own noise characteristics. Note
the asyptotic convergence of the noise voltages in Figures
3a-3c at low values of Req.

Predicted RMS noise at output for bandwidth of 20Hz-20KHz for
HA-5102/04/12/14.

100pVrm

~
r10"Vrm

A second circuit (Figure 1b) balances the effects of input
bias currents by placing a resistor Rc , equal to Req ,
between the non-inverting input and ground. While reducing DC errors, this configuration adds two additional
terms to the noise formula.

't==

E
E

R,

",

t=
~(bl

"',m

~
-=-

-=-

A",~ AIiAf

,

"

~
R.

-=-

-=-

+A"'I-RIIRI-R,

~

"

(Eamp)2 + Req4KT + (Inoise Req)2
+ Rc 4KT + (Inoise Rc)2

00

Au" ur Req

The original contributors to output noise remain as before
and the additional terms represent the thermal contribution by Rc and the associated amplifier current

~

Rc

FIGURE 3e. PREDICTED NOISE
Predicted RMS noise at output for bandwidth of 20Hz-100Hz for
HA-5102/04/12/14.

10-193

Application Note 554
RMS nOise is derived in part as the integral of the noise
density spectrum over a given bandwidth. Below is the
complete expression ...

Erms (from fO to f1) =

E

noise
density

"

2 df

spectrum

The strict integration assuming En is constant works well
for fO above =1 KHz. Both the amplifier's noise voltage and
the noise current increase for frequencies below 1KHz.
This makes for difficult integration since complicated expressions for Inoise and Eamp must be generated. To
avoid this problem, graphical integration techniques or
sampled methods can be used with great success.

-rc;.
,,
,,

"

_____ -.J

*CllndCzIMPROYE

TRANSIENT REJECTION

R7SENSORRESISTANCE

FIGURE 4.

The curves in Figures 3a-3c illustrate the relationship
between the RMS noise and Req for both amplifier designs. It should be apparent from the predicted RMS noise
curves that increased bandwidth causes an increase in
noise voltage. An interesting effect of this relationship is
that only absolute bandwidth (f1-fO) is important. The
general frequencies of interest (if they are above 1KHz)
are irrelevant. More simply, 100Hz of bandwidth near
10KHz contains as much noise as 100Hz of bandwidth
near 1MHz. This implies that bandwidth should be restricted with appropriate high and low pass filtering, if the
lowest noise voltages are to be attained.
From the previous discussion, it is apparent that low noise
designs require low resistor values. This is not to say that
high gain should be avoided, just that low input and
source resistance values are required for low noise operation. Closer examination of the RMS noise formula will
also show that limiting bandwidth, with filtering, will also
reduce noise levels. Additionally, metal film and wirewound resistors have lower excess noise (a component of
resistor noise in addition to thermal noise) than carbon resistors and are therefore preferred.

Applications
Electronic scales have come into wide use and the HA5102, as a very low noise device, can improve such designs. One circuit (Figure 4) uses a strain gauge sensing
element as part of a resistive Wien-bridge. An auto-zero
circuit is also incorporated into this design by including a
sample-and-hold network.
The bridge signal drives the inverting input of a differentially-configured HA-51 02. The non-inverting input is
driven by the other half of the HA-5102 used as a buffer for
the holding capacitor, Ch. This second amplifier and its
capacitor Ch form the sampli ng ci rcuit used for automatic
output zeroing. The 20Kohm resistor between the holding
capacitor Ch and the input terminal, reduces the drain
from the bias currents. A second resistor Rg is used in the
feedback loop to balance the effect of Re. If R7 is approximately equal to the resistance of the strain gauge, the input signal from the bridge can be roughly nulled with RS.

Auto-zeroing scale circuit uses a strain gauge/bridge arrangement to
improve sensitivity.
.

With very close matching of the ratio R4/R1 to R3/R2, the
output offset can be nulled by closing S1. This will charge
Ch and provide a 0 volt difference to the inputs of the second amplifier, which results in a 0 volt output. In this
manner, the output of the strain gauge can be indirectly
zeroed. R10 and potentiometer R11 provide an additional
mechanism for fine tuning Vout, but they may also increase offset voltage away from the zero point. C1 and C2
reduce the circuit's susceptibility to noise and transients.
The rise of digital equipment and computers, has created
an entire realm of signal processing equipment. In most
cases the computer requires elaborate circuitry to bridge
over into the analog domain. The digitally programmable
attenuator (Figure 5) is a rather simple circuit that still
allows a great deal of control of analog signals.
The first stage is a simple buffer used to isolate the signal
source from the attenuator stages to follow. Each of the
subsequent stages is preceded by a voltage divider
formed by two resistors and CMOS switch. Provided that
the CMOS switch for each stage is "closed", the drive
signal will be attenuated according to the basic voltage
divider relationship at each stage. In the event a switch is
"open" nearly all of the signal strength will be passed to
the next stage through the 1K resistor. The amplifiers act
as buffers for the divider networks and reduce interaction
between stages.
Eight levels of attenuation are
possible with the circuit as illustrated in Figure 5, but more
stages could be added. Each divider network must be
closely matched to the resistor ratios shown or the level of
attenuation will not match the levels in the logic chart.

Audio Applications
The HA-5102/04/12/14 series lends itself to audio designs. This is due in large part to the low noise characteristics of the series. With 4.0nVI
@ 1KHz, very low
noise designs can be realized with little effort. This allows
more attention to be placed on the quality of the designs.

10-194

JHz

Application Note 554
qo
II)
II)

w

0.27/l1
VD",

TO AMP AND TONE CONTROL.

'.
49.9K

,--- -------------,
N.

...N.W.
~:

l~L-fL$D
-1-'
AI

/I'

,1,2

-=-

HI-lDtSWITCH

N''"
FIGURE 5.

FIGURE 7.

Several resistors may be combined to obtain the precise resistor values
used in this precision attenuatar or a potentiometer may prove adequate.

The RIAA amplifier provides industry standard signal correction for vinyl
record recordings .

.~
*-=-

~Oll HA·lI1Z"4. II'

"
~DI44 ..1 ~---+--+--~

11"0

III

fl4T'l

"l

'-.tIN----.Nv---NV'--"

~

$

~
FIGURE 8.
FIGURE 6.

PROFESSIONAL AUDIO NAB TAPE PLAYBACK
PREAMPLIFIER

The tone correction circuit requires a low impedance driving source. yet it
provides a great deal of control over the output waveform.

This NAB tape playback preamplifier fully utilizes the speed. bandwidth.
and noise features of the HA-5102.

The fOllowing group of designs point to some of the
applications in which the HA-5102/04/12/14 series can
improve performance without major circuit alterations.
They depend, in part, on the ±20V/I.ISec slew rate of the
HA-5112/14, which will allow a small signal to be passed
without distortion up to 12MHz. The bandwidth of these
devices is more than adequate for audio use. The
HA-5102/04 will pass a full 10V signal out to 200KHz
without distortion and at unity gain. Many other uses for
these devices exist. The audio applications simply
suggest the more likely uses for the series.

excellent centerpiece for these. One such circuit is the
RIAA preamplifier used to match the frequency ch!lr!lcteristics of vinyl records !lnd phonograph cartridges.

Tone correction of an audio signal is an application that
relies on both the low distortion and the low noise of the
HA-51 02. The Baxandal-type circuit in Figure 6 uses input
buffering because of the relatively low input impedance of
the RC networks. The output stage is basically a summation amplifier with the high frequency contribution varied
by the treble control and the low frequency by the bass
control. The component values given in Figure 6 !llIow
±12dB of gain over the audio range.
One of the more common audio !lpplications is sign!ll
correction for recording !lnd playback. Sever!ll st!lnd!lrd
circuits are available !lnd the HA-5102 should prove an

The RIAA circuit essentially provides low frequency boost'
below 318Hz !lnd high frequency !lttenuation !lbove
3150Hz. Recent modific!ltions to the' response st!lndard
include !I 31.5Hz peak g!lin region to reduce DC oriented
distortion from external vibration. The circuit in Figure 7
provides the desired response and with the extra amplifier
of the HA-51 02, the package can economically provide an
additional stage of gain and isolation for a cleaner response and pickup.
The NAB (magnetic tape standard) amplifier circuits are
also well suited for use with the HA-5102 (Figure 8). The
NAB preamplifier is configured to provide low frequency
boost to 50Hz, flat response to 3KHz, and high frequency
attenuation above 3KHz. Compensation for variations in
tape and tape head performance can be achieved by trimming R1 and R2.
The low noise characteristics of the HA-5102 family lead
to low system noise and improved signal to nOise ratios:
This has become increasingly more important as the

I-

o
Z
a.:
D.
«

Application' Note 554
various recording mediums have progressed to the point
of near perfection, at least so far as the ear is concerned.
At the other end of the audio spectrum, opposite the
playback arena, is initial sound generation and the
microphone. The HA-S104/14 is a very practical choice
for a dynamic microphone preamplifier (Figure g). The
relativl9ly Simple design alloWs for DC coupling of both
input and o u t p u t : '

40Hz to 20KHz. The other component values give an adequate range of operation to allow for virtually universal
filtering in the audio region. wo, Q, and gain (H) can all be
independently adjusted by adjusting R1 - R3 respectively
and in succession.

...
,.
&G'

·10

·'2

The microphone sees an input impedance equal to R1 + R2
(2Kohm). The input impedance of the amplifier group is
not matched to the SOOohm impedance of the microphone. This is because the instrumentation amplifier does
not rely on input power, but rather input voltage alone for
its driving source. In many cases the frequency range of
, the microphone will be extended with the reduced
loading.

-,."',"'.I'-1H....

''P.....M('-'.:>-'

:

MATCHED

LOAD'D.~

,,
,,
,

*'

10K

RS, RS, and R7 provide stable DC gain in conjunction with
R3 and R4, which form the DC feedback network around
t~e first two amplifiers" R7also controls the DC offset at
the output. RS, Rg, and C3 provide the proper A9 gain
above O.SHz. R'14 is tuned for maximum CMRR by
matching the feedback element ratios of the third amplifier [R11/R1O = (R13 + R14)1 R12]. With a total gain of
4dB, the 2mV microphone signal is increased to the standard 1Vrms output.
The optional output stage provides a SOOohm matched
output impedance to maximize the power transfer to the
next stage. The HA-S104 arid the HA-S114 will both function well in this circuit. There will, however, be an extra
unused amplifier. To avoid this unused amplifier the tone
correction circuit in Figure S is recommended for use with
the fourth amplifier. If the HA-S114 is used, the DC gain
resisfors R' and R3' in Figure S must be used with the tone
correction circuit to inst,tred proper DC stability.

I

~

OUTPUT STAGE

Av"WB

FIGURE 9.
The dynamic microphone preamplifier does not use a transformer which
reduces both complexity and cost.
2A

0.8 D.1

One of the most useful circuits.in audio filtering is the
Biquad. This universal filter offers low pass, high pass,
band pass, band elimination, and all pass functions. The
G...
HA-S104 is an excellent .choice ,for the four amplifier
Biquad circuit in Figure 10. This is due in large part to the o-"""."'3."',.-~W"""-f"
low nO.iseand high slew rate characteristics' of the
9-+-M('-'.....
HA-S104, both of which reduc6.distortion effects.

.,
1'~

R'. A3 MIN" A3 MAX

R'«RP01

The Biquad consists of two successive integration stages
followed by an inverting st.age. The entire group has a
feedback loop from the front to the back consisting of R1
which is chiefly responsible for controlling the center frequency, woo The first stage of integration is termed a
"poor" integrator because of R2 which limits the range of
integration. R2 and C form the time constant of the first
stage integrator with R3influencingthe gain (H) almost
directly. The band pass function is taken after the first
stage with t~19 low pass function taken after the third :~ ~~:~~~~ ': :~:~T::::I~~UENCYI
R CDNTROLS H (IAIII)
stage. The remaining' filter operations are generated by 3
various combination of the three stages.
The Biquad is "orthogonally" tuned, meaning that wo, Q,
and gain (H) can all be.independl9ntly adjusted. The·component values in Figure 10 will allowwo to range from

..

,,0

o

.,

10K

R,

18K

",

The biquad offers a universal filter with wo' Q, and gain "orthogonally"
tuned.

10-196 .

Application Note 554

o::r

LO
LO

The standard Biquad circuit in Figure 10 uses three stages
of inverting amplifiers. This produces negative feedback
for stability (any odd number of stages would produce the
same effect). There, however, is no restriction such that
only inverting stages must be used. The standard Biquad
of Figure 10 has been altered in Figure 11 by combining
the function of the last two stages into one non-inverting
integrator. This reduces the number of amplifiers required for the band pass function to just two. The
bandpass transfer function is of course altered to reflect
the consolidation of the last two stages and is as follows ...

LIJ

tO
Z

D.
D.

2.4K FOR OUTPUT CURRENT LIMITING

FIGURE 12.
The bandpass stages can be incorporated mto a multIple band equalIzer.

v.

2.

600

therefore ....
GAIN" n-15dB

Wo

J2/R1R4CC

Q

J2R22/R1R4

Rt

2.

-

2.
10.

H

-R1 R4C/2R3

if C1

=

C2

=

C

>----....-oV out

The two amplifier Biquad bandpass filter constructed
around the HA-5102 can easily be incorporated into a ten
band graphic equalizer. By restricting gain to ±12dB and
requiring Q =1.7, a very usable design can be generated.
See Figure 12.

667

FIGURE 13.

R,

The 600 ohm input impedance provides for proper audio level signal
mixing uSing the HA-5104.

FIGURE 11.
The two amplifier biquad forms an economical band pass filter, which in
this case is oriented towards a ten band equalizer.

A high signal to noise ratio is important in signal construction applications. The low noise aspect of the HA-5104
aids in lowering the system noise and thereby raises the
system sensitivity. The signal combination circuit in
Figure 13 incorporates input buffering with several other
features to form a relatively efficient mixer stage.

The circuit in Figure 13 uses buffer stages to prevent
channel crosstalk back through the mixer resistor
network. The potentiometers used for each stage allow
for convenient signal strength adjustment while main
taining input impedance matching at the 6000hm audio
standard. The feedback resistor Rf will permit the output
signal gain to be as high as 15dB. The circuit in Figure 14
illustrates
some
of the other possible buffer
combinations. These include a differential input stage, a
voltage follower as well as both non-inverting and
inverting stages. The allowable resistor ratios and
recommended device types are also included. One
restriction applies to this type of mixer network which is
Rg >2.4Kohm. This limits the worst case output current
for each of the input buffers to less than 10mA.
The bulk of the HA-5102/04/12/14 series applications
have involved audio uses. This does not represent the full
range of application of the series. In general, most

10-197

Application Note 554
common amplifier applications, excluding video, could
benefit from the group. The goal here was to introduce the
designer to some of the more common and well know

designs using the series, in hope of triggering interest for
more exclusive uses.

">-......I\N\,-...,

>-_oIV"'~.

HA-5102/04 OR IF R,/R2 AND
RJ/R4>10; THEN HA-SllZ114

HA-Sl0Zl04

HA-51 02/04 OR IF R6/RS>10;
~.....~"""'"- THEN HA-5112/14

HA-5102/04 OR IF R7/R8~9;
THEN HA-511Z/14

IF R11 = 5 x Rg AND Rg:;: R10;

THEN GAIN' 0-15dB

HA-5102/04 OR IF (RlO"#INPUTSIIRg > 10
THEN HA-511Z114

FIGURE 14.
Universal mixer stage combines the more useable configurations of the
HA-5102/04/12/14 family to meet most signal construction needs.

References
"D-C Amplifier Noise Revisited", AI Ryan & Tim Scranton
Analog Dialog, 1969.

Instruction Manual, model 2173C Transistor Noise
Analyzer Control Unit. Quan-Tech, Division of KMS
Industries. Whippany, New York.

Fitchen, F.C. and Motchenbacker, C.D. Low Noise Electronic Design, New York: John Wiley and sons, 1973.

M. E. VanValkenburg, Analog Filter Design, New York.
Holt, Rinehart and Winston, 1982.

10-198

FOR YOUR INFORMATION

Lt)
Lt)
Lt)

w
~

o
Z

Harris Analog

No. 555

a.
a.

oCt

ULTRA LOW BIAS AMPLIFIER, HA-5180
by Alan Wayne Hansford
Most amplifiers depend on the voltage at the inputs to determine the output voltage, and require a parasitic input
bias current for proper operation. Typically these currents are in thetJA range, but they needn't be so large. A
very few devices fall into the ultra low bias current group
which ranges from fA levels to a few pA. The HA-5180 is
one of the few, with only 250fA of Bias current.
DC offset errors are created at the output of most
amplifiers from the interaction of input bias currents with
circuit resistances. If bias currents are significantly
reduced, as with the HA-5180, the DC errors are also
significantly reduced: This implies that with very low bias
currents, larger resistances can be used without creating
a DC error that exceeds normal bias current/resistance
combinations. A great many high source impedance
applications are only practical with some means of bias
reduction, typically FET buffering. The ultra-low bias
amplifiers, like the HA-5180, eliminate the need for FET
buffering with its FET input stage. This makes the
HA-5180 particularly well suited for atomic particle
detectors and precision sampling circuits, to name two.
The outstanding features of the HA-5180 do not end
simply at input bias current, but combine to form a very
usable device. The Common Mode Rejection Ratio
(CMRR) and Power Supply Rejection Ratio (PSRR) are
both examples of this. The rejection of a common signal
appearing at both input terminals of the device is 105dB
(CMRR) and the rejection of power supply fluctuations is
110dB (PSRR): The open loop gain is a very respectable
1000KVIV. All of these outstanding features reflect the
quality built into the HA-5180.
Given the type of device and the primary emphasis on low
input bias currents, the HA-5180 has several other points
worthy of praise. The basic speed of the device with a
2MHz bandwidth and a 7V/tJSec slew rate, is above
average and noteworthy for any amplifier. This becomes
even more apparent in light of the low supply current
(O.8mA). The relationship between supply current and
speed usually implies that a high speed device requires a
high supply current. Yet, the design of the HA-5180 has
judiciously metered its use of available supply current to
optimize speed at gains as low as unity.

Building Tips
The HA-5180 was designed with high performance in
mind as indicated by its parameter list. The design enhancements did not stop at the drawing board however,
and have been brought into the user's control. The most
interesting development is the case connection to pin 8 of
the can. By grounding the can through pin 8, a high level
of shielding may be easily implemented. The effects of
shielding should be further increased by using a grounding plane under the HA-5180. Both of these techniques
will also improve the heat transfer away from the chip and
package to extend the operational safety margins.
The remarkably low input bias currents are extremely important to many applications. They, in spite of their merit,
can not stand alone in every circuit design. For this reason
the voltage offset pins were included in the design of the
HA-5180. With pins 1 and 5 (Figure 1), the offset voltage
can be reduced below the very acceptable value of 100tJV,
establishing an amplifier with nearly ideal characteristics.

o

CI)

'W

~b-

FIGURE 1.
Nulling the HA-5180s offset adjust to 0 volts brings it closer to the "ideal".

Low Noise Design
Since the HA-5180is a moderately low noise operational
amplifier, low noise design techniques must be used to
make the most of this feature. There are two primary
means of keeping noise down, one requires the amplifier
inputs to look into low source resistances and the other
requires bandwidth limiting by filtering. A short outline of
noise prediction will be presented here to support these
concepts.

10-199

<0
z

Application Note 555
Noise can be divided into several categories, which include thermal noise (white nOise) and flicker noise (pink
noise or 1/f noise). The feedback components are
strongly' dominated by thermal noise making thermal
noise the most important of these from a system design
standpoint (an exception to this are high gain DC amplifiers which require low 1If noise as measured by the lower
"1/f noise corner"). Flicker noise is more a function of the
amplifier construction quality, and system design variations are lesS effective in reducing this type of noise.
Noise is usually rated in one of two ways. The first is RMS
voltage or current (a measure of peak-to-peak noise in a
given bandwidth) and the second is by noise density
and AI
(a measure of the specspectrum in VI
tral content of the noise in the frequency domain). The
two rating schemes are related, with RMS noise levels
generated from the integration of the noise density spectrum over a desired frequency bandwidth.

v'RZ

RI
(.)

':"

lit

DC BIAS CURRENTS

OPTIMIZED IF
Roq= R RI= R,

II

FIGURE 2.

(Eamp)2

+

(E feedback)2
network

+

..

J4KTReq

where." K = 1.381 E-23
T = 300
Req = R II Rf

E current noise in = Inoise Req
feedback network
Iu:
Inoise = 0.01 pAl" Hz @f> 1KHz
or more specifically ...
En = G J(Eamp )2

+

Req4KT

.viI/iIi
z

1

ID
FREQUENCY

10

IK

NOISE VOLTAGE

1Megohm for the HA-5180) will dominate the noise
density while low values for Req will yield tothe amplifier's
own noise characteristics. Note the asyptotic con
vergence of the noise voltages in Figures 4a-4c at low
values of Req .
A second circuit (Figure 2b) balances the effects of input
bias currents by placing a resistor Rc , equal to Req , between the non-inverting input and ground. While reducing
DC errors, this configuration adds two additional terms to
the noise formula.
En = G

+

with these two

Due to the extreme'IY low noise currents, only the voltage noise generates a
significant contribution.

En = total noise
= gain of stage
Eamp = amplifier noise vOltage ......... 70nV/jHz @ f > 1KHz
=

genera~ed

111

FIGURE 3.

(E current noise in)2
feedback network

G

E feedback
network

NOISE PREDICTION CIRCUITS

A reasonable estimate of noise levels can be
basic amplifier circuits.

The total noise is defined as the square root of the sum of
the squares of the individual noise terms.
En = G

':"

(b)

v'RZ

As an illustration of noise prediction, the noise density for
the standard inverting amplifier configuration (Figure 2a)
will be determined. The total noise is derived from the
combination of several noise sources, only three of which
are of any significance. These are the amplifier's noise
voltage, the thermal noise of the feedback components,
and the noise generated by the current noise of the amplifier within the feedback components.

R

(Eamp)2 + Req4KT + (Inoise Req)2
+ Rc 4KT + (Inoise Rc)2

(Inoise Req)2

Both the amplifier noise voltage and noise current are
constant above 1KHz and rise slightly for lower
frequencies (Figure 3). The resistor thermal noise iis
derived from the parallel combination of the feedback
network (Req) and several constants (4KT). The third
noise term again uses the equivalent resistance of the
feedback network (Req) as well as the current noise
generated at the input terminals of the amplifier.

The original contributors to outputnoise remain as before
and the additional terms represent the thermal
contribution by Rc and the associated amplifier current
noise seen through that resistor. To optimize DC design,
Rin'l Rf = Req = Rc , therefore the noise density equation
reduces to ...

It should be evident from the above formula that
extremely large values of Req (usually over 10Kohm, but

Again the relationship between large values of Req and a
high noise density spectrum remains.

I

En = G

10-200

J (Eamp)2

+ 2Req4KT + 2(lnoise Req)2

Application Note 555
RMS noise is derived in part as the integral of the noise
density spectrum over a given bandwidth. Below is the
complete expression ...

Erms (from fO to f1) =

E

noise
density
spectrum

2 df

The strict integration assuming En is constant works well
for fO above ""'1 KHz. Both the amplifier's noise voltage and
the noise current increase for frequencies below 1KHz.
This makes for difficult integration since complicated

mVrms

expressions for Inoise and Eamp must be generated. To
avoid this problem, graphical integration techniques or
sampled methods can be used with great success.
The curves in Figures 4a-4c illustrate the relationship
between the RMS noise and Req for both amplifier
designs. It should be apparent from the predicted RMS
noise curves that increased bandwidth causes an
increase in noise voltage. An interesting effect of this
relationship is that only absolute bandwidth (f1-fO) is
important. The general frequencies of interest (if they are
above 1KHz) are irrelevant. More simply, 100Hz of
bandwidth near 10KHz contains as much noise as 100Hz
of bandwidth near 1MHz. This implies that bandwidth
should be restricted with appropriate high and low pass
filtering, if the lowest noise voltages are to be attained.

mVrms

Req Dr Req =Re

R. q or Req = Re

FIGURE 4a.

FIGURE 4b.

PREDICTED NOISE

Predicted RMS noise at output of HA-51BO for a bandwidth of
O.1Hz-110KHz.

RU! or Req

FIGURE 4c.

PREDICTED NOISE

Predicted RMS noise at output ofHA-51BOfor a bandwidth of 20Hz-20KHz.

2

Ae

PREDICTED NOISE .

Predicted RMS noise at output of HA-51BO for a bandw.idth of 20Hz-100Hz.

10-201

It)
It)
It)

w

I-

o
Z

Application Note 555
From the previous discussion, it is apparent that low noise
designs require low resistor values. This is not to say that
high gain should be avoided, just that low input and
source resistance values are required for low noise operation. Closer examination of the RM8 noise formula will
also show that limiting bandwith, with filtering, will also
reduce noise levels. Additionally, metal film and wirewound resistors have lower excess noise (a component of
resistor noise in addition to thermal noise) than carbon resistors and are therefore preferred.

>~+--"',
I

I

I

I
I

I

I

5Kt

-=

:

.-15V~_j
~H/S-V
HI-201 SWITCH

,I
,I
I

I
I
I
I
I

)

l,

.,,', -PI-' '"..
,,,' D1*

......

Applications

....

*IN914

*Diode used'for S/H peak detector

FIGURE Sa.
"Fasl" sample-and-hold must be nulled using the offset polentiometers
but offers very short aquisition times.

The "precision" circuit achieves a lower error voltage by
closing the feedback loop around both amplifiers. This
adds a delay to the feedback signal and increases the
overshoot. The DC error voltages are reduced in this configuration and can be reduced further with the Vos offset
nulling potentiometers, hence the term "precision". C1
improves transient response while R1 provides isolation
of the input and the output during the hold cycle. 81 determines whether the holding capacitor Ch follows the input
voltage or holds a previous value. The necessary feedback to the input buffer is provided by 82 during the hold
operation. 01 converts the sample-and-hold into a peak
voltage sample-and-hold. 02 reduces the reverse saturation of the input buffer when used in the peak mode.

I

I

I
I

I
I
I

I
I
I

~J
HI-201 SWITCHES

.ll

" 01*" ...
,~---,~~,
,

('~
I

* Dj'odes used

IN914.

...
I

for S/H peak detector

FIGURE 5b.
"Precision" sample-and-hold is an excellent use of the HA-5180, but, because of the extended feedback, has greater overshoot.

1M

~

40K Hz Bandwidth; C

The "fast" sample-and-hold incorporates feedback
around each amplifier separately. This makes for a much
faster response, but does tend to increase DC error voltages. The effects of DC offset can be minimized with the
Vos offset nulling potentiometers. As with the precision
sample-and-hold, 81 controls the charging and holding
operation of the holding capacitor Ch. 01, as before, converts the circuit into a peak voltage sample-and-hold.
Like the sample-and-hold, the differential instrumentation amplifier relies on extremely high input impedance
for effective operation. The HA-S1aO with its JFET input
stage, performs well as a multimeter preamplifier (Figure e). The standard three amplifier configuration is used
with very close matching of the resistor ratios RS/R4 and
(R7 + Ra)/Re, to insure high common mode rejection
(CMRR). The gain is controlled through R3 and is equal to
2R1/R3. Additional gain can be had by increasing the
ratios RS/R4 and (R7 + Ra)/Re·

1M

3KHz Bandwidth; C

One of the most critical applications, relative to input bias
currents, is the sample-and-hold. The HA-S1aO requires
such a low input bias current (2S0fA) that the drain on
holding capacitors is all but eliminated. Figure S illustrates both a "precision" sample-and-hold as well as a
"fast" sample-and-hold. Both circuits buffer the input voltage and the sampled voltage on Ch.

0.053).1F

= 3900pF

FIGURE 6.
The standard three amplifier instrumentation configuration gives a multimeter preamplifier extremely high input impedance.

The capacitors C1 and C2 improve the AC response by
limiting the effects of transients and noise. Two
suggested values are given for maximum transient
suppression at frequencies of interest. 80me of the faster

10-202

Application Note 555
It)
It)
It)

DVM's are operating at a peak sampling frequency of
3KHz, hence the 4KHz low pass time constant. The 40KHz
low pass time constant for AC voltage ranges is an
arbitrary choice, but should be chosen to match the
bandwidth of the other components in the system. C1 and
C2 may however, reduce CMRR for AC signals if not
closely matched. Input impedances have also been added
to provide adequate DC bias currents for the HA-S180
when open circuited.

w

I-

o
z

ZERO AOJUST

0:
a.

«

-15V

Sensors And Transducers

FIGURE 7.
Cadmium Sulfide celis controllwo light detection circuits,

Most passive transducers and sensors vary in resistance
relative to light, sound, pressure, etc. Often the average
resistance of the transducer is quite large. This presents a
problem in the choice of an amplifier, since bias currents
are typically high enough to create a significant error
voltage (Verror = Ibias R). Extremely low input bias
currents of the HA-S180 minimize this effect for the most
part and allow for more conventional transducer and
sensor circuits.

+15V

The circuit in Figure 7 uses a light sensitive cadmium sulfide cell to form a crude light level detecton module. If R,
the sensor matching resistor, is equal to the "dark" resistance of the cadi mum sulfide cell, the amplifier output will
range from 0 volts to =12 volts as the light level ranges
from "dark" to "bright". The circuit in Figure 8 operates in
a'similar manner but use the standard non-inverting configuration instead of the voltage follower configuration.
This allows for variable gain. Although the "dark" resistance of the cadmium sulfide cell is only =7Kohms, the
principles of operation apply to other types of detectors
which require the high input impedance of the HA-S180
for reasonable linearity and useability.

FULL SCALE ADJUST

FIGURE 8.
Cadmium Sulfide cells control two light detection circuits.

R1 ~ RpROBE ~100Megohm

An example of a high resistive value sensor that depends
heavily on high amplifier input impedance is the pH probe
and Detector, with the average probe resistance on the
order of 1OOMegohms. The circuits in Figures 7 and 8 may
still be used with this type of transducer, but a bridge circuit may prove more appropriate (Figure 9). The greatest
sensitivity is achieved if R1 is approximately equal to the
probe resistance. The circuit can be "zeroed" with R2
while the full scale voltage is controlled by RS. The correlation between pH and output voltage may not be linear,
which would necessitate a shaping circuit. A calibration
scheme, using solutions of known pH, may prove adequate and more reliabile over a period of time due to
probe variance.
The general schematic could be applied to strain gauges
or any other type of resistive sensor. The key is the
extremely low input bias current required by the HA-S180,
which allows higher value resistances to be used without
producing significant error Voltages. This leads to more
conventional designs with less exotic circuitry.
Along the same lines as the pH meter and light level
detector, is the photo-diode current to voltage converter
(Figure 10). One common use of this type of device is as a
light to voltage converter for dens ito meters. This circuit
depends on the light level/current relationship of a photo-

FIGURE 9.
Another popular sensor circuit is the bridge network. The pH probe can be

replaced with nearly any resistive sensor.

diode. Since the diode will only pass as much current as
the light level will allow, the diode becomes a light
controlled current sink. A current source is summed
along with the photo-diode current, and a difference
current appears at the input of the HA-S180. Relying on
ideal amplifier input impedance, which is nearly the case
with the HA-S180, all of the difference current is applied to
Rf. The output is then defined as ...
Vout = (Iref - Id)Rf
Several current sources may be used. The simplest is a
resistor with I = (VCC - Vbe)R. A more accurate current source is the two transistor current mirror, where I =
(VCC - Vbe)/Rref (Figure 10). Since the controlling component, Rref, is not in the current path for I, a more
accurate summation at the amplifier input terminal can
take place. The stage can be zeroed with R or Rref as the
case may be. The nulling potentiometer will provide the
fine zero.
\

The precision integrator is a classic circuit which can also
benefit from the JFET inputs of the HA-S180. The traditional relationship between C and R holds very well in one

10-203

C/O
'W

8::1«0
2:

Application Note 555
+16V

lrel

J

Many signal 'processing applications depend on low amplifier bias currents for their operation. One such design
involves logarithmic amplifiers (Figure 12). The inputsensitivity is governed by the system bias currents in such a
circuit. The HA-5180, with its low input bias currents, can
extend the sensitivity of the logarithmic current to voltage
converter. The specific application may well_be an atomic
particle counter in which the current from the detector is
converted into a voltage. For the design in Figure 12 the
output voltage is defined as ...

R,

R,eI

2N38BU

-15V

lrel

= 12VCC - Vb.IIRrei

USing the schematic values, the expression reduces to .....
FIGURE 10.

Vo = -In[2000Iinl

The low bias currents of the HA-51BO provide a nearly ideal summing point
forthe circuit currents in this photo-diode current to voltage converter.

n

design (Figure 11), since the drain on C by the amplifier is
so small. A second HA-5180 has been incorporated into
this design to allow a threshold voltage to be adjusted.
The threshold voltage is set while present at the input with
81 and 82 closed. 81 is opened before 82, then 83 is
closed momentarily to reset the output voltage. The stage
will then take the time integral of the input signal relative
to the threshold voltage. R2 provides stable gain during
the threshold setting procedure. The nulling potentiometer reduces the effects of Vos.
The precision integrator can be converted into a preCision
timer with a few modifications. The reset switch used to
discharge the capacitor C is used as the timer on reset
switch. The output will be proportional to the elapse time
as long as the input voltage is constant and not equal to
the threshold voltage. If the timer needs a hold function, a
switch must be inserted to isolate the capacitor C from the
resistor R.

This is a typical matched transistor pair logarithmic
amplifier. The matching removes a constant from the
output expression and improves temperature stability.
The temperature stability will be even greater if Rt varies
inversely with temperature.
The input range of this circuit can be extended by using
another HA-5180 as a current preamplifier to the logarithmic converter, as shown in Figure 12.
The HA-5180 is an extremely powerful building block. The
sample-and-hold and the preCision integrator are
examples of the low drain placed on circuit capacitors by
the bias currents. The bias currents themselves are nearly
low enough to class the HA-5180 as an "Ideal amplifier" in
that respect. The transducer applications illustrate the
HA-5180's merit in this area. The list of applications and
uses could continue on, but the material presented should
allude to the general applications and uses of the
HA-5180.

Vref
R2

> __

~-O

INTEGRATOR.u•

R2
-15V
TIMERout

HiS 0 - - - - - - - '

FIGURE 11.
81 and 82 when closed, provide a threshold settling for this precision
integrator while 83 allows the output to be reset.

10-204

Application Note 555

Vout

=

-In ( _lin ) =
Irol

-

In ( l_i n ) =- In (2000 lin)
500j.tA

+10V

It)
It)
It)

w

I-

o

r-----------,

Z

a:CL
~

AD

-=-

-=-

L

lin
-:..

-15V

TEMPEAATUAE
SENSITIVE

l'inAinU + Aa/Ab)
ID=
A

---:-------~
FIGURE 12
Logarithmic current to voltage converter depends on the low bias currents
of the HA-51BO for accuracy.

References
"O-C Amplifier Noise Revisited", AI Ryan & Tim Scranton Analog Dialog, 1969.
Fitchen, F.C. and Motchenbacker, C.D. Low Noise Electronic Design, New York: John Wiley and sons, 1973.
Instruction Manual, model 2173C Transistor Noise Analyzer Control Unit. Quan-Tech, Division of KMS Industries. Whippany, New York.

10-205

APP
NOTS

FOR YOUR INFORMATION

Harris Analog

No. 560

APPLYING THE HY-9590 ANALOG DATA
ACQUISITION SIGNAL PROCESSOR
By John E. Sullivan

INTRODUCTION
The HY-9590 Analog Data Acquisition Signal Processor
is a powerful building block for use in a Data Acquisition Subsystem (DAS),. or in stand-alone operation.
Incorporating a differential analog multiplexer, a programmable gain instrumentation amplifier and track
and hold ampl ifier, the HY -9590 is an ideal signal conditioning element for a wide range of commercial, industrial and military applications.

FUNCTIONAL OPERA TION
OF THE HY-9590

The multiplexer selects one of eight possible differential
analog input signals to be processed, or it can be dis-

CHAN I

MUX OUT
A

Expansion lines, MUX OUT A and MUX OUT B, can
be used either to expand the number of input channels
or as monitor outputs. The multiplexer exhibits a
nominal 1.2 kilohm ON resistance; therefore, when
using MUX OUT A or MUX OUT B 'as monitor points,
a high impedance monitor (
1 megohm) should be
used to minimize loading affects.

>

As illustrated in Figure 1, the HY-9590 incorporates
three primary components. An input multiplexer controls selection of the signal to be processed, the programmable gain instrumentation amplifier provides
common mode signal rejection and gain while the
track and hold amplifier stores the instantaneous
signal level for final signal processing. Signal acquisition,
including multiplexer, amplifier, and track and hold
settling times, is less than 10J,ls to 0.01% accuracy.

. INPUT
MULTIPLEXER

abled to the high impedance state. All analog input
lines have full overvoltage protection and can tolerate
inputs up to 20 volts in excess of the poWer supply
voltages for extended periods and transient spikes up
to several hundred volts.

Select lines AO, A1 and A2 operate in binary mode
(000 selects channel 1 and 111 selects Channel 8). The
enable line, when LOW, DISABLES the multiplexer
and forces its output to the high impedance state. Both
the select and enable lines have an operating range of
V- to +0.8 volts for a logic 0 input and 4 volts to V+
for a logic 1 input. When driving these inputs with
TTL logic, a 1 K ohm pullup resistor is recommended
to ensure proper switching. All unused inputs (both
signal and cO!1trol) can be hardwired to either V- or
ground for a logic 0' and +5 volts (VCC) or V+ for
a logic 1.

. PROGRAMMABLE GAIN
INSTRUMENTATION AMP

TRACK AND HOLD AMPLIFIER

A-I----"
B-I----"

>--+--oT/H

OUTPUT

A~---" ~--~~

CHANa

BI-t==~~,:====~J
Ao AI A2
CHANNEL
SELECT

EN

MUX
OUT
B

V REFERENCE
LOW

GO
GI
GAIN
SELECT

TiH
CONTROL

, FIGURE 1 - FUNCTIONAL BLOCK DIAGRAM

10-206

EXT
CH

PROGRAMMABLE GAIN INSTRUMENTATION
AMPLIFIER
The programmable gain instrumentation amplifier
(PGA) operates in the true differential mode with A
input signals being inverted and B input signals being
noninverted. Some applications will have true differential input signals with an infinite impedance to ground.
These applications should incorporate a 5 megohm
resistor to ground from both the MUX OUT A and
MUX OUT B outputs to allow amplifier bias currents
to flow to ground.
The PGA has digitally selectable gains of -1, -2, -4 and
-8 in binary format (00, G = -1; 11, G =-8). The digital
control levels are identical to those of the input multiplexer, and as such require 1 k ohm puilup resistors
when driven from TTL logic.
The VREF LOW line can be tied to ground or used for
offset nulling as illustrated in Figure 2. Other configurations such as level shifting or quasi-differential outputs can also be implemented as shown in Figure 5.
TRACK AND HOLD AMPLIFIER
The track and hold amplifier stores and holds the
instantaneous signal level applied to its input when the

T /H
fully
with
hold

line goes to a logic 1. The T /H mode control is
TTL compatible and requires no puilup resistor,
the track mode defined as -5 to +O,8V and the
mode defined as +2 to +7 volts.

This device includes an internal 100pF hold capacitor
for fast acquisition time. For some applications, an
external hold capacitor may be added to reduce droop
rate and pedestal error at the expense of acquisition
time. This capacitor should be selected for minimum
dielectric absorption and leakage as found in teflon or
polystyre(le types.
The hold capacitor terminal (pin 17) remains at virtual
ground potential. Any PC connection to this terminal
should be kept short and "guarded" by the ground
plane. This is to prevent errors caused by nearby signal lines or power supply voltages.
Figure 3 illustrates the typical track and hold performance as a function of the hold capacitor. As the hold
capacitor increases, the acquisition time also increases
and the droop rate hold step error decreases.
The hold step voltage error is also a constant magnitude over the DC input range as shown in Figure 4.
This error may be nulled out by using the VREF output circuit as shown in Figure 2.

I------+---,L

10

14
13
B
A
MUX
OUT

CH1
CH2

12

+15V

10pF

1.0 ~--'d---

GND

CH3

......'

0.5 ~"'---+

10pF

CH4

21

-15V'

CH5

0.1 '---~~----'.J----___j

CH6
CH7
18
I

vcc

16 17,

+15~

100K

I

~O ~ __

OFFSET (HOLD STEP)
ERROR. MILLIVOL TS

VOUT

CH8

.01

..Lc
T H

100

J

1000

10K

lOOK

CH VALUE. PICOFARADS

FIGURE 3 -

100 -15

TYPICAL TRACK AND HOLD
PERFORMANCE AS FUNCTION
OF HOLDING CAPACITOR

HOLD STEP VOL TAGE (MILLIVOLTS)
TA = +250 C

*THESE PULLUP RESISTORS

CH • 100 pF

0.1

CH

= l000pF

0.01

ARE USED WHEN INTERFACING TTL LOGIC ONLY.
VOUT' G(B - A) + VREF
G' -1, -2, -4,-8

1.0

-10 -8

-6 -4 -2

2

4

6

8

10

DC INPUT·(VOLTSI

FIGURE 2 - TYPICAL CONFIGURATION

FIGURE 4 - HOLD STEP vs. INPUT VOLTAGE

10-207

o

CD

it)

W

I-

o
Z

D.

0..

0----'

FIGURE 5 - EXPANDING THE HY-9590 TO 16 INPUT CHANNELS

SELECTED
CHANNEL
1
2
3
4
5
6
7
8
9
10

11
12
13
14
15
16

A3

A2

A1

AO

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

10-208

c

CD
In

+5V
+15V

W

-15V

t-

12
CH1

1A

T/H OUT

18

13

DB11 (MSB)

14 20V FS IN

DB9

CH2

CH3

CH4
CH5
CH6

2B

3A

EXT. CH

17

HI-9590
GND

3B
4A
4B

VREF

5A
5B
6A

A
MUX
B

15

CH7

T/H CONTROL

7B
CH8

8A

G1

-=

14

100Kr!

f'

HI-674A
10 REF IN

100rl

-=

12 BIP OFF

DB7

DB5
DB4
DB3
DB2

CE
4

16

DB8

DB6
REF OUT

20Kr!

13

6B
7A

a..
a..
"-- FROM EQUATION.
VLA IS POSITIVE

A

A

FIGURE 3.

FIGURE 5.

For Case I, refer to Figures 2 and 3. In this situation the
desired result is obtained, namely, that ring sync occurs
during the negative peak of VC4. This helps achieve ring
trip faster because, once a subscriber goes off-hook, a
negative DC shift is observed at V C4. This shift
approaches a comparator threshold in the ring trip
detection circuit. If the negative peak of VC4(AC)
precedes the negative going DC shift at VC4, one can
achieve ring trip in a shorter time frame. Also this
configuration allows ring trip to occur for long lines, in the
order of 3000 ohms. At these line lengths, the DC negative
shift will never reach the threshOld because there is not
enough DC current through the sense resistor, RB4.
However, the negative peak ofVC4 (AC) will cross the ring
trip detector comparator threshold and ring trip will
occur.

For Case II refer to Figures4 and 5. Here ring sync must be
synchronized with the positive zero crossing of VRING
(AC) as it appears on the line so as to coincide with the
negative peak of VC4 (AC), as in the previous case. One
can see from Figure 5 that ring sync on the negative zero
crossing would coincide with the positive peak ofVC4, inhibiting ring trip for loops greater than approximately 800
ohms.

Conclusion 1: For this case make sure ring sync is
synchronized with the negative zero crossing of VRING as
it appears on the line.

Conclusion 2: For this case make sure ring sync is
synchronized with the positive zero crossing .01 VRING
(AC.).
For all other ring configurations, namely, tip injected and
balanced ringing for the 5504, if ring sync is used, it must
be synchronized with the negative zero crossing of
VRING(AC).

Acknowledgement
The author wishes to thank Geoff Philliips for his contribution to this paper.

10-214

APP
NOTE

FOR YOUR INFORMATION

CW)

.....
w

II)

I-

o
z

Harris Analog

No. 573

THE HC-5560 DIGITAL LINE TRANSCODER
David J. Donovan

1.0 Introduction
The Harris HC-55S0 digital line transcoder provides mode
selectable, psuedo ternary line coding and decoding
schemes for North American and European transmission
lines. Coding schemes include.Alternate Mark Inversion
(AMI), Bipolarwith N Zero Substitution (BNZS), and High
Density Bipolar 3 (HDB3), used for transmission lines as
follows:
AMI: North American T1 (1.544MHz) and
T1C(3.152MHz) lines
BSZS: North American T2(S.3212MHz) lines
B8ZS: North American T1 (1.544MHz) lines
HDB3: European PCM30(2.048 & 8.448MHz) CEPT lines.
Recommended by CCITT
The transcoder is a single chip, single supply device
fabricated with standard cell CMOS. Features include
simultaneous coding and decoding, asynchronous
operation, loop back mode, transmission error detection,
an alarm indication signal, and a full chip reset.
This application note will describe why coding for digital
transmission is necessary, the types of coding, which is
best, and why, and the functionality and applications of
the HC-55S0 digital line transcoder.

2.0 Why Line Coding?

transmitted is assigned a different level, OV and +3V, for
example:

OATA
o 0

o

n

o

n

o

UNIPOLAR (UNBALANCED) SIGNAL

n

There are, however, a number of disadvantages:
• The average power (Ao/2) is two times other codes
• The coded signal contains DC and low frequency
components. When long strings of zeros are present, a
DC or baseline wander occurs. This results in loss of
timing and data because a receiver/repeater cannot
optimally discriminate ones and zeros.

I

qs:

+1~n
·IWW

I

LJ1JL

DC WANDER

• Repeaters/receivers require a minimum pulse density
for proper timing extraction. Long strings of ones or
zeros contain no timing information and lead to timing
jitter and possible loss of synchronization.

Transmission of serial data over any distance, be it a
twisted pair, fiber optic link, coaxial cable, etc., requires
"maintenance" of the data as it is transmitted (through repeaters, echo cancellors etc.). The data integrity must be
maintained through data reconstruction, with proper
timing, and retransmitted. Line codes were created to
facilitate this "maintenance".

2.2 Bipolar Coding is Better

In selecting a particular line coding scheme some considerations must be made, as not all line codes adequately
provide the all important synchronization between
transmitter and receiver. Other considerations for line
code selection are noise and interference levels, error
detection/checking, implementation requirements, and
the available bandwidth.

1 1

• There is no provision for line error rate monitoring.

With bipolar, or balanced, coding, the same data may be
transmitted more efficiently achieving the same error
distance with half the power (Ao/4). This coding is often
referred to as Non-Return to Zero (NRZ) coding as the
signal level is maintained for the duration of the signal
interval.

0

Fl:J

o o

1

0

0

1

,------,'R~~F
BIPOLAR (BALANCED) SIGNAL

2.1 Unipolar Coding
The most basic transmission code is unipolar or
unbalanced coding whereby each discrete variable to be

Although bipolar coding is more efficient than unipolar, it
still lacks provisions for line error monitoring, and is
susceptible to DC wal1lder and timing jitter.

10-215

0:

Q.

c(

Application Note 573
The HC-5560 digital line transcoder provides a number of
augmented bipolar coding schemes which:
• Eliminate DC Wander
• Minimize Timing Jitter
• Provide for Line Error Monitoring

B8ZS is used commonly inNorth American T1 (1.544MHz)
and T1 C(3.152MHz) carriers. For every string of 8 zeros,
bipolar code is substituted according to the following
rules:
1) If the immediate preceding pulse is of (-) polarity, then
code each group of 8 zeros as 000-+0+-.

This is accomplished by introducing controlled redundancy in the code through extra coding levels.

2) If the immediate preceding pulse is of (+) polarity, then
code each group of 8 zeros as 000+-0-+.

3.0 Line Code Descriptions

1------ B-------~

The HC-5560 transcoder allows a user to implement any
of the four line coding schemes described below.

e.g. PCM Code

I 0 1 0 0 0 0 0 0 0 0 1 I 0
000-+0+-

AMI, Alternate Mark Inversion, is used primarily in North
American T1 (1.544MHz) and T1C (3.152MHz) carriers.
Zeros are coded as the absence of a pulse and one's are
coded alternately as positive or negative pulses. This type
of coding reduces the average voltage level to zero to
eliminate DC spectral components, thereby eliminating
DC wander.

e.g. PCM Code 0

0

0

1 0

1 1 1 0

1 0 0 0 0 0 1

AMI Code

To facilitate timing maintenance at regenerative repeaters
along a transmission path, a minimum pulse. density of
logic1's is required. Using AMI, there is a possibility of
long strings of zeros and the required density may not
always exist, leading to timing jitter and therefore higher
error rates.
A method for insuring a minimum logic 1 density by substituting bipolar code in place of strings of O's is called
BNZS or Bipolar with N Zero Substitution. B6ZS is used
commonly in North American T2 (6.3212MHz) carriers.
For every string of 6 zeros, bipolar code is substituted
according to the following rule:
If the immediate preceding pulse is of (-) polarity, then
code each group of 6 zeros as 0-+0+.-, and ilthe immediate
preceding pulse is of (+) polarity, code each group of
6 zeros as 0+-0-+. One can see the consecutive logic 1
pulses of the same polarity violate the AMI coding
scheme.

BBZSI-I~V=ViOlatiOn
000+-0-+

BBZSI+I~

The BNZS coding schemes, in addition to eliminating DC
wander, minimize timing jitter and allow a line error
monitoring capability.
Another coding scheme is HDB3, high density bipolar 3,
used primarily in Europe for 2.048MHz carriers. This code
is similar to BNZS in that it substitutes bipolar code for 4
consecutive zeros according to the following rules:
1) If the polarity of the immediate preceding pulse is (-)
and there have been an odd (even) number of logic 1
pulses since the last substitution, each group of 4 consecutive zeros is coded as 000-(+00+).
2) If the polarity of the immediate preceding pulse is (+)
then the substitution is 000+(-00-) for odd (even) number of logic 1 pulses since the last substitution.

1---4--~
e.g. PCM Code

000HDB3

+00+

------u

V= Violation

-00-

HDB31+1~

0 0 0 1 0 1 1 1 0 0 0 0 0 0
.

1---4 ---I
0 I 1 1 0 0 0 0 0 0 1

H - - R_ R ~
~ -U- ¥ -:000+

1-----6-----1
e.g. PCM Coda

0 0 0 0 I

0-+0+-

B6ZSI-I~ V=Vlolallon
0+-0

-+

B6ZSI+I~

The 3 in HDB3 refers to the coding format that precludes
strings of zeros greater than 3. Note that violations are
produced only in the fourth bit location olthe substitution
code and that successive substitutions produce alternate
polarity violations.

10-216

Application Note 573
4.2 Receiver (Decoder)
101010101111101

AMI-IlL----,Ur----------"y
8BZS

The receiver accepts as its input the ternary data from the
transmission line that has been externally split into two
binary unipolar return to zero signals (AIN and BIN).
These signals are decoded, according to the rules of the
selected line code into one binary unipolar NRZ output
signal (NRZ OUT).

8BZS

The encoder and decoder sections of the chip perform
independently (excluding loopback condition) and may
operate simultaneously.

H083
FIGURE 1. SUMMARY OF CODING SCHEMES PROVIDED BY
THE HC-5560 TRANSCODER.

A summary graph of all four substitution coding schemes
is illustrated in Figure 1. To simplify timing recovery, logic
1's are encoded with 50% duty cycle pulses.

4.0 Functional Description
The HC-5560 transcoder can be divided into six sections:
transmitter(coder), receiver(decoder), error detector, all
ones detector, testing functions, and output controls. A
block diagram is shown in Figure 2.
MOOE SELECT

0---..,...--+-------,

OVSS
OVOO

MRZ OATA 1M
CLOCK
(ENCOOER)

......-1--+----1----4---0 OUT I
t----+-++----t--1---00UT 2

LOOP TEST
ENABLE
MRZ OATA
OUT

AIMo---...J
BIN

The Error output signal is' active high for one cycle of ClK
DEC upon the detection of any bipolar violation in the
received AIN and BIN signals' that is not part of the selected
line coding scheme. The bipolar violation is not removed,
however, and shows up as a pulse in the NRZ DATA OUT
signal, In addition, the Error output signal monitors the
received AIN and BIN signals for a string of zeros that
violates the maximum consecutive zeros allowed for the
selected line coding scheme (i.e., 8 for B8ZS, 6 lor B6ZS, and
4 for H DB3). In the event that an excessive amount of zeros is
detected, the Error output signal will be active high for one
cylce of ClK DEC during the zero that exceeds the maximum
number. In the case that a high level should simultaneously
appear on both received input signals AIN and BIN a logical
one is assumed and appears on the NRZ data out stream with
the error signal' active.

>+---I--QCLOCK

OUTPUT

mill

4.3 Error Detector

0-------'

FORCE AIS 0-------+

4.4 All Ones Detector
An input signal received at inputs AIN and BIN that consists of all ones (or marks) is detected and signalled by a
high level at the alarm indication signal (AIS) output is set
to a high level when less than three zeros are received during one period of Reset AIS immediately followed by
another period of Reset AIS containing less than three
zeros. The AIS output is reset to a low level upon the first
period 01 Reset AIS containing 3 or more zeros.

j[ffifo-------+

IOEg;::R~ 0 - - - - - - - - 1 - - - - +......

ERROR

4.5 Testing Functions

L...-_---'

RESET AIS

0------+1

\--------I>-OAIS

FIGURE 2. HC-5560 TRANSCODER FUNCTIONAL BLOCK
DIAGRAM • .

4. 1 Transmitter (Coder)
The transmitter codes a non-return to zero (NRZ) binary
unipolar input signal (NRZ IN) into two binary unipolar
return to zero (RZ) output signals (OUT1, OUT2). These
output signals represent the NRZ data stream modified
according to the selected encoding scheme (i.e., AMI,
B8ZS, B6ZS, HDB3) and are externally mixed together
(usually via a transistor or transformer networi<) to create
a ternary bipolar signal for driving transmission lines.

A logic high level on l TE enables a loop back condition
where OUT1 . is internally connected to input AIN and
OUT2 is internally connected to BIN (this disables inputs
AIN and BIN to external signals). In this condition, the input signal NRZ DATA IN appears at output NRZ DATA
OUT (delayed by the amount of clock cycles it takes to encode and decode the selected line code). A decode clock
must be supplied for this operation. The Reset input can
be used to initialize this process.

4.6 Output Controls
The output controls are Output Enable and Force AIS.
These pins allow normal operation, force OUT1 and
OUT2 to zero, or force OUT1 and OUT2 to output all ones
(AIS condition).

10-217

Application Note 573
5.0 Applications
The outputs must be mixed externally, via a transistor/transformer network, to produce the ternary 'bipolar'
code selected and to drive the transmission line. The
length of Out1 and Out2 are set by the length of the
positive ECLK pulse.

The HC-5560 transcoder is designed for use in North
American and European PCM transmission lines where
psuedo ternary line code substitution schemes are desired. Any equipment that interfaces to n, T1 C, T2 or
PCM30 transmission lines may incorporatetranscoders.
Such equipment includes multiplexers, channel service
units, echo cancellors, repeaters, etc. This section will
illustrate and describe a basic circuit application, and
various system level applications examples.

5.1 Basic Applications Circuit
The basic applications circuit is shown in Figure 3. The
encoder accepts serially clocked unipolar non-return to
zero (NRZ/PCM) data at the NRZ IN pin and codes it into
two unipolar return to zero (RZ) signals at pins Out1 and
Out2. A coding scheme is chosen via mode select pins
MS1 and MS2. Data is clocked in on the negative edge of
ECLK and clocked out on the positive edge of ECLK.

To decode ternary coded data, the signal must first be
split into two unipolar signals and presented to the AIN
and BIN pins. This may be accomplished by an amplifier
with a differential output, and two comparators. Both inputs are sampled by the positive edge of DCLK. Decoded
data is clocked out in NRZ form to the NRZ OUT pin on the
positive edge of DCLK.
All the logic inputs and outputs are TTL compatible.

5.2 System Level Examples
Examples of system level transcoder applications are illustrated in Figure 4 through 8.

+5

FROM CODEC
TRANSCODER.
OR RB050

NRZ IN

Dun

VDD

TU2. TIC.
PCM30
LINE OUTPUT

ENCOOER
OUT2

ECLK
V+

-----

CONTROL

MSI

FORCE ALARM

FAIS

MS2

LOOP TEST ENABLE

LTE

CLOCK

RESET

RAIS

ALARM CLOCK}
AIS J--__- O ALARM
ERROR MONITORS
ERR J--__- O ERROR

OUT ENABLE

AIN

§jll

NRZ OUT J--__- o TO CODEC. TRANSCODER. OR RB060

INPUT

OECOOER

HC-5560

-

MS1

SELECTS

o
o

AMI
B8ZS
B6ZS
HDB3

FIGURE 3. BASIC TRANSCODER APPLICATIONS CIRCUIT.

10-218

Application Note 573

,....

C")

it)

5560
T1 ~

B
G

B

IB8lSj
5560

'"

T1 ('

"'

IB8lSj
5560

B

T1 t'

I-

't', T1

o

z

IB8lSj
5560

G
B
G

5560

5560

B

IB8lSj
5560

T2 16.3212MB/Sj

IB6lSj

186lSj

IB8lSj

0:

Il.

,- T1

«

"'
( T1

ID8lSj
5560

5560
T1 (

W

5560

B

G
ID8lSj

'"( T1

188lSj

FIGURE 4. M12 MUL TlPLEXER

HC-5560
T1

EJ EJ

(

I

I
I
I

I

I

I
I

I
T1

HC-5560

I

I
I

I

I

I

I

I

I
I

I

I

I
I
I

I

I

I

EJ 0

(

I

I
I
I
I

J--I---

I

I

PBX

I

I
I

I
I
I
I---

I---

en

g:~

FIGURE 5. CHANNEL SERVICE UNIT (CSU)

«0
z

T1 {I

,

GB

T1 LINE

HC-5560

GB
HC-5560

FIGURE 6. ECHO CANCELLOR

10-219

'-

(

T1 LINE

Application Note 573

T1
DIGITAL
CRDSS-CDNNECT
[DSXI

FIGURE 7. DIGITAL CROSS CONNECT (DCS)

HC-556D
T1 (

B
B

a
HC-5560

HC-5560

Tl

(

FIGURE 8. T1 COMPRESSION BY ADPCM

10-220

(

T1 ADPCM LINK

APP
NO

FOR YOUR INFORMATION

Harris Analog

No. 574

UNDERSTANDING PCM CODING
David J. Donovan

1.0 Introduction
The process of converting analog voice signals into Time
Division Multiplexed (TOM) Pulse Code Modulated
(PCM) format is described and illustrated herein. Application Note No. 570, "Understanding CODEC Timing", by
D.J. Donovan is recommended reading as accompanyment to this application note.

~

8ANOLIMITEO
VOICE CHANNELS ' -

CH1~
I

I

I

I
I

I

:

I

,

I:

I"I~'
I I

CH3'~~

.
•

~!:::
I

:
I

I

[I
I
I

i:
I
I

:
II

~
~

--....,..7",-7'----''''',-+,-+-'l,~

I

I

:

I

:

I

I

I

I

I

I

I

1

I

I

I

I

I

I I

:

I

I

:

I

I

I

I

I
i
I
1111~'I~"
~:I
l-..l...1i.1

~

~.

i. .t.
I:

I

I

I

CHANNELS 4 THRU 231321 ARE HERE

...

..

~

FIGURE 1 (A THROUGH E).

3.0 Quantizing
The PAM samples still represent the voice signal in analog
form. For digital transmission, further processing is
required. Pulse Code Modulation (PCM) is a technique
used to convert the PAM samples to a binary weighted
code for digital transmission. PCM coding is a two step
process performed by the CODEC. The first step is
quantization, where each sample is assigned a specific
quantizing interval. The second step is PCM coding of the
quantizing interval into an 8 bit PCM code word. Each is
discussed in the text that follows.
Converting PAM samples to a digital signal involves
assigning the amplitude of a PAM i'\ample one of a whole
range of possible amplitude values, which are divided into
quantizing intervals. There are 256 possible quantizing
intervals, 128 positive and 128 negative. The boundaries
between adjacent quantizing intervals are called decision
values.

10-221

ICI

I
I

I
CH241321..-,."...T,_<;.,--......,,-!,--+~,

I::~R~~~~~~ •••~ §

181

,

I

2.0 Sampling

There are relatively large intervals between each PAM
sample that may be used for transmitting PAM samples
from other voice channels. Interleaving several voice
channels on a common bus is the fundamental principle
of Time Division Multiplexing (TOM). As the number of
voice channels on the TOM bus increases, the time alloted
to each sample is reduced, and bandwidth requirements
increase (See Figure 1E).

:

,

I
:

IAI

.

CH2L---~~----4-~~---T:--~---1~~

Analog time varying voice input information is transmitted over two-wire (2w) pairs (channels) from subscribers.
The PCM filter band-limits voice signals to 4kHz, one per
channel, and removes power line and ringing frequencies.
Research has shown that voice transmission band-limited
to 4kHz has enough fidelity for telephony purposes.

The process of converting filtered voice information into a
digitized pulse train format begins with sampling the
voice signal at uniform intervals. These intervals are
determined by the Nyquist Sampling Theorem, which
simply states that any signal may be completely re-constructed from its representative sampling, if it is sampled
at least twice the maximum frequency of interest. The
telephone system, being a worldwide standard 8kHz
sampling system, satisfies Nyquist, as all voice signals are
band-limited to 4kHz. When the voice waveform is
sampled, a train of short pulses is produced, each representing the amplitude of the waveform at the specific
instant of sampling. This process is called Pulse Amplitude MOdulation (PAM). The envelope of the PAM
samples replicate the original waveform. Figures 1A thru
10 illustrate representative PAM samples for up to 24(30)
individual voice channels in a tl-Law (A-Law) telephone
system.

~

:
1

101

'IEI

Application Not" 574
If PAM samples are uniformly quantized, there will be
situations where several different amplitude values will be
assigned the same quantizing interval during encoding.
Then, during decoding, one signal amplitude value is recovered for each quantizing interval which corresponds
to the midpoint of the quantizing interval. This results in
small discrepencies that occur between the original waveform and the quantized approximation; i.e., infinite analog
levels in the original waveform being assigned finite quantizing intervals. These discrepancies result in a quantizing
noise or quantizing distortion, the magnitude of which is
inversely proportional to the number of discrete quantizing intervals. These noise signals may be of the same
order of magnitude as the input signal, thereby reducing
the signal to quantizing noise ratio to an intolerable level.
For this reason non-uniform quantization is used. Large
signals need a smaller number of quantizing intervals,
while small signals require a larger number of quantizing
intervals. Such a non-uniform quantization process is defined as companding characteristics by both Bell and
CCITT.
The PCM CODEC performs this non-uniform or
non-linear quantization through p-Law or A-law
companding characteristics shown in Figure 2. This
process enhances lower amplitude signals, to allow them
to compete with system noise, and attenuates higher
amplitude signals, preventing them from saturating the
system. This form of signal compression results in a
relatively uniform signal to quantization noise ratio,
approaching 40dB for a wide range of input amplitudes.
Also, the dynamic range approaches that of a 13(11) bit
A/D or 80(66)dB for p-Law (A-Law) companding. The
digital realization of this companding process is obtained
by Ii segment and chord piecewise linear approximation
to a semi-logarithmic function.
Both the p-Law and A-law companding characteristics
are composed of 8 linear segments or chords in each
quadrant. Within each chord are 16 uniform quantization
intervals, or steps. With p-Law, moving away from the origin, each chord is twice the width of the preceding chord,
and each group of 16 uniform steps is twice the width of
the preceding group. It is also referred to as the 15 ,Segment characterisfic. The first chord about the origin in the
positive and the negative quadrant are of the same slope
and are therefore considered one chord (chord 0).
With A-law, the first two chords and step groups in each
quadrant are uniform. Successive chords and steps follow
the same pattern asp-Law. A-Law is referred to as the.13
segment characteristic. The first two chords about the origin in the positive quadrant, and the first two chords about
the origin in the negative quadrant are all of the same
slope and therefore are considered one chord (chord 1).
There are 64 uniform steps in chord 1, 32 positive and 32
negative. However, for purposes of encoding and decoding samples that fall into the quantization intervals in
chord 1, a different 3 bit chord code (refer to Figure 3) is
assigned for the first segment of 16 uniform steps closest
to the origin ahd the next segment moving away from the
origin. Chord 1 in A-Law is twice that of chord 0 in p-Law.

OUANTIlINB
INTERVALS

&MOlD I

STEP

CHDIlU5

1/2

INPUT IMGlAL IREFERREO TO 11

-128

FIGURE 2.

Thep-Law companding characteristic is used primarily in
North America and Japan, while A-Law is used primarily
in Europe. The differences are minimal and are summarized below:
p-Law
• Step sizes double for each successive chord
• Virtual edge =+/-8159 units
• Input level = 3.172dBmO
• 2 codes for 0 input
A-Law

•
•
•
•

Step sizes double for each successive chOrd after
the second chord
Virtual edge = +/-4096 units
Input level = 3.14dbmO
No code for 0 input

The input level is determined with reference to the power
level at the central office or 'switch'. That pOint is referred
to as the zero transmission level point (OTLP). All CODEC
measurements must be translated to the on.p. The unit of
translated level is the dBmO (dB relative to 1mW referred
to a transmission level of OTLP).
There is no absolute voltage standard for the CODEC,
however, a standard exists relative to full scale. The point
at which the CODEC begins to clip is called the virtual
edge. It is measured in normalized voltage units or steps,
+/-8159 steps for p-Law and +/-4096 steps for A-Law. If a
PAM sample representing the peak of a voice input signal
hits the virtual edge of a p-Law system, it has a relative
power of +3.172dBmO. The corresponding A-Law relative
power is +3.14dBmO. These numbers are chosen to
minimize intrinsic gain error at OdBmO and 1000Hz.

10-;-222

Application Note 574

o::r
......

4.0 Encoding

&n

The second stage of conversion to binary PCM data for
transmission involves the coding of the 256 quantizing intervals assigned to the individual PAM samples into 8 bit
binary words (7 data bits plus 1 sign bit). The MSB in each
word is a polarity bit indicating a 1 for positive quadrant
quantizing intervals, and a 0 for negative quadrant quantizing intervals. The next three bits represent the chord,
and the last four bits identify the step within the chord.
The 8 bit PCM word partitioning is illustrated in Figure 3.
BIT NUMBER

2

BIT WEIGHT-MSB +1SIGN

26

3
25

4
24

5
23

6
22

CHORD

7

formation are contained in channels 0 and 16, respectively (see Figure 5). Bits 2, 4, 6, and 8 are inverted for
transmission per CCITT recomendation. These multiplexed frames of 32, 256 bit channels constitute the
2.048MHz PCM30-CEPT (Committee of European Postal
and Telegraph) transmission channel.

- - t - - CHANNEll---t---CHANNfL 2-----t
818283848586878881828384858687 BB

8

21

t I'HZ4 fa ,HI I ,;,

20 LSB

I

SYNC ANOALAAM [B.BITS)

STEP

PI;i~:M!~I~:LI~;IG /
I "4 III ,,221 ",*,,,1 l f.5.'::"

.... _ - -

'H3

I

SIGNALLING 18·BITS)

I

:0:::"

I

A-Law and f,J-Law coding about the origin differ. f,J-Law
defines two codes for OV input while A-Law defines no
code for OV input (see Figure 4). The two f,J-Law zero
codes represent a normal quantization step that is divided
into halves by the y-axis of the companding curve (refer to
Figure 2). These half steps represent the lowest resolvable
sig nal of the f,J-Law characteristic.

+FULL SCALE
+CENTER
-CENTER
-FULL SCALE

I

(1"31m '" I,,21 "3 W

FIGURE 3.

INPUT

1 /

SYNC BIT

BINARY
EQUIV.

/l-LAW

A-LAW

11111111
10000000
00000000
01111111

10000000
11111111
0111 1111
00000000

10101010
11010101
01010101
00101010

FIGURE 4.

5.0 Multiplexing and Transmission
Each 8 bit PCM word is transmitted in its respective time
slot, which is assigned to each CODEC by the system
controller (See App. Note 5:70). A number of PCM words
may be transmitted consecutively from .different
channels, creating a PCM TOM signal for transmission.
Each CODEC channel has an average data rate of 8K
samples/sec x 8 bits = 64kbits/s. This means that within a
1/8kHz = 125f,Js period, 24(30) PCM words of 8 bits each
are transmitted consecutively in af,J-Law (A-Law) system.

FIGURE 5.

6.0 Line Coding
PCM code generated by the CODEC function is in
Non-Return to Zero (NRZ) format. It cannot effectively be
transmitted directly on a transmission line because the
signal contains a DC component and lacks timing
information.
An additional coding step is necessary which converts
NRZ code to a pseudo ternary code suitable for
transmission. Practical coding schemes include Alternate
Mark Inversion (AMI), Bipolar with N Zero Substitution
(BNZS), and High Density Bipolar 3 (HDB3) coding.
These schemes eliminate the dc component of NRZ code,
thereby eliminating the troublesome dc wander
phenomenon. They also provide a means for detecting
line coding errors, and enhance synchronization between
transmitter and receiver through reduction of timing jitter.
For additional information, refer to Application Note 573,
"The HC-5560 Transcoder", by D. J. Donovan.

7.0 Demultiplexing
After transmission, the CODEC must recover the 8 bit
PCM words from the TOM signal, sort out, decode, and
distribute the PCM information appropriately. The
demultiplexing process is fully controlled electronically.

8.0 Decoding

5. 1 Ji-Law Systems
For f,J-Law systems, the bus format allows 24 groups, or
timeslots, of 8 bit PCM words, plus one synchronization
(sync) bit tor a total of 193 bits per frame (see Figure 5).
This sync bit partitions the boundary between timeslots
24 and 1, and allows the time slot counter at the receive
end to maintain sync with the transmit end. All signalling
information is contained in bit 8 (LSB) of the PCM word.
These multiplexed frames of 24,193 bit channels constitute the 1.544MHz T1 transmission channel.

5.2 A-Law Systems
For A-Law systems, the bus format groups data into 32
timeslots of 8 bit PCM words each, giving 30 voice channels plus one 8 bit sync and alarm channel, and one 8 bit
signalling channel. The sync and alarm, and signalling in

The CODEC receive function allocates a signal amplitude
to each 8 bit PCM word which corresponds to the
midpOint of the particular quantizing interval. The
expanding characteristic is the same as that for non-linear
companding on the transmit side. If the LSB of a f,J-Law
PCM word contains signalling information, it is extracted
by the CODEC, latched into a flip-flop, and distributed to
the CODEC signalling output (Si9R). This means that
there is a lost bit (LSB) in the incoming PCM data stream
during a signalling frame. The decoder interprets the
missing LSB as a 1/2 (i.e. halfway between a 0 and a 1) to
minimize noise and distortion. The PCM words are
decoded in the order in wliich they are received and then
converted to PAM pulses. The PAM pulses are summed,
then low pass filtered, which smoothes the PAM envelope
and reproduces the original voice signal.

10-223

W

t-

O

z

0.:
oct

c.

APP
NOTS

FOR YOUR INFORMATION·

Harris Analog

No. 576

HC-5512C PCM FILTER
CLEANS UP CVSD CODEC SIGNALS
P. G. Phillips and D. J. Donovan
The HC-5512 is a CMOS switched capacitor PCM Filter
originally designed for use with the PCM CODEC to filter
transmit and receive audio signals. The HC-5512C is a
wider specification version of the HC-5512 that conveniently lends itself to be configured as a input/output
filter for the HC-55564 CVSD. This offers the designer
extremely high quality filter characteristics for a minimum
component count and .system cost.
The HC-5512C Filter is manufactured using double-poly
silicon gate CMOS technology. Switched capacitor
integrators are used to simulate LC ladder filters with low
component sensitivity. The IC contains two switched capacitor filters. The transmit filter is a fifth order
elliptic low pass filter cascaded with a fourth order
Chebyshev high pass filter. It has a flat band pass response and/ejects signals of frequencies less than 200Hz
and greater than 3.4kHz. The receive filter is a fifth order
elliptic low pass filter with SINX/X compensation. The
response of this filter can be tailored for CVSD use with an
external RC network to flatten the SINX/X correction
characteristic.
The HC-55564 is a half duplex modulator/demodulator
CMOS integrated circuit used to convert voice signals
into serial NRZ digital data and reconvert that data into
voice. Continuously Variable Slope Deltamodulation
(CVSD) is the method of conversion. As in any sampling
system, the reconstituted signal contains noise due to

switching. In addition, to prevent alias distortion, the in~
put signal must be filtered to remove frequencies above
one-half .the sampling frequency. In order to minimize
these unwanted nOise frequencies, and to pre-condition
the input signal, it is necessary to filter the input and the
decoded output of the CVSD.
The transmit and receive filter responses are shown in
Figures 1A 'and 1B. The transfer characteristic ofthe
CVSD is illustrated in Figure 2. A suggested circuit configuration is shown in Figure 3.
The HC-5512C filter is configured such that it utilizes a
2.048MHz clock for the switched capacitors. A 16kHz or
32kHz sampling clock for the CVSD is easily derived as
shown in Figure 3. .A 32kHz sampling clock is
recommended to enhance noise performance, frequency
response, and dynamic range of the CVSD. For the circuit
as shown the audio signal into the CVSD should be 1Vp-p
over the 3.2kHz band to obtain a flat response. As can be
seen from Figure 2, for lower frequency signals, higher
signal levels can be used. However, an external
compensation network is required to flatten the inherent
SINX/X output response of the receive filter stage (see
Figure 1B). RA, RB and CA form a simple lead lag.filter at
the output of the receive filter in ·the HC-5512C. This
introduces a pole at 1kHz and a zero at 3.3kHz in order to
give some degree of compensation against the filter's
SINX/X characteristics.

Receive Filter Stage

Transmit Filter Stage
10

10
+3
0

I

-10
iii
:!! -20
w
c -30
:>

...::::;
...:I!

'"

\

-10

II
-

FIL TER

FUEl'+llt;;: Yr

iii
:!! -20
w
c
:> -30
::::;
-40

I

Illl.;...~

SIN ~/X

...

...:I!

-40

'"

-50
-60

-50
X= -

-60

-70

1

-70
0.1

FREQUENCY (kHz)

10

0.1

FIGURE lA. TRANSMIT FILTER STAGE

,I

800 0
1

FREQUENCY (kHz)

FIGURE.1B. RECEIVE FILTER STAGE

10-224

10

Application Note 576
CD

......

The CVSD is AC coupled to the filter since the audio
in/out ports of the CVSD are DC biased at VDD/2. (In fact,
audio can be directly coupled to VFRI if desired.) It is often
necessary to provide a side tone back to the user headset
so the speaker may hear his own voice, thus preventing a
dead feeli ng in the instrument. The side tone is provided
at the audio out pin of the CVSD during the encode operation and is of the same amplitude as the input signal,
transfer gain excepted.

-OdB

-OdB IN

-6dB

-6dB IN

-12dB

-12dB IN

-IBdB

-IBdB IN

-24dB

-24dB IN

-30d6

-30dB IN

-36dB

-36dB IN

100

200

300
fREQUENCY

--------'=--'====--M
0-________________-+_-4-__- J

0---------------=--.>--1

~

Illustrates the .,frequency response of the HC-55564 for varying input
levels. To prevent slope overload (slew rate limiting) do not exceed the OdS
boundary. The frequency response is directly proportional to the sampling
rate. The output levels were measured after filtering.
.5V

ENG/DEC

1:04049
116

FIGURE 3. SUGGESTED CVSD-PCM FILTER INTERFACE

10-225

o
Z
a.:
Q.

OdB IN " 1.20V RJS
Voo =+5V

~

oml

If"

W

I-

.

SIGNAL LEVEL
OUTPUT Id BI

The CVSD has an Automatic Gain Control (AGC) output.
The signal present is a digital output whose duty cycle is
proportional to the average input audio level. The signal
may be integrated to provide feedback information to an
AGC amplifier or a voice level indicator.
The Force Zero (FZ) input to the CVSD is used to reset all
the internal counters at the start of an encode or decode
cycle to prevent momentary overload. It will also recover
the part from a latch-up condition. Cycling FZ during
power-up sequencing is recommended. A suggested
power-up reset circuit is shown in Figure 3 on the FZ
control line. During the time FZ is active (low), an
alternating 1,0 quieting pattern appears at the NRZ output
which is at half the sampling clock rate, and is decoded
inaudible. The quieting pattern may also be generated by
activating the Alternate Plain Text (APT) input (low), or by
removing the signal from the audio input pin.

II)

Additional information on CVSD is contained 'in Application Note 607.

Dour ITO DATA IIF)

-5V

DIN IFROM DATA ifF)

3000

APP
NOTS

FOR YOUR INFORMATION

Harris Analog

No. 607

DELTA MODULATION FOR VOICE TRANSMISSION
By Don Jones

INTRODUCTION TO DELTAMOD
Delta modulation has evolved' into a simple, efficient
method of digitizing voice for secure, reliable communications and for voice I/O in data processing.
To illustrate basic principles, a very simple delta
modulator and demodulator are illustrated in Figure
1. The modulator is a sampled data system employing a negative feedback loop. A comparator senses
whether or not the instantaneous level of the analog
voice input is greater or less than the feedback signal.
The comparator output is clocked by a flip-flop to
form a continuous NRZ digital data stream. This
digital data is also integrated and fed back to the
comparator. The feedback system is such that the
integrator ramps up and down to produce a rough
approximation of the input waveform. An identical
integrator in the demodulator produces the same
waveform, which when filtered, reproduces the
voice.
'
One can see that the digital data O's and 1 's are commands to the integrators to' "go up" or "go down"
respectively. Another way of looking at it is that the
digital data stream also has analog significance;
it approximates the differential of the voice, since
analog integration of the data reproduces the voice.
Note that the integrator output never stands still;
it always travels either up or down by a fixed amount
in any clock period. Because of its fixed integrator
output slope, the simple delta modulator is less than
ideal for encoding human voice which may have a
wide dynamic amplitude range.
The integrator cannot track large, high frequency
signals with its fixed slope. Fortunately, human
speech has statistically smaller amplitudes at higher
frequencies, therefore an integrator time constant of
about 1 millisecond will satisfactorily reproduce voice
in a,3kHz bandwidth.
A more serious limitation is that voice amplitude
changes which are less than the height of the integrator ramp during one clock period cannot be
resolved. So dynamic range is proportional to clock
frequency, and satisfactory range cannot be obtained
at desirable low clock rates.

10-226

A means of effectively increasing dynamic range is
called "companding" (compressing-expanding); where
at the modulator, small signals are given higher
relative gain, and an inverse characteristic is produced
at the demodulator.
The CVSD: A popular effective scheme for companded delta modulation is known as CVSD (continuously variable slope deltamod) shown in Figure 2.
Additional digital logic, a second integrator, and an
analog multiplier are added to the simple modulator.
Under small input signal conditions, the second
integrator (known as the syllabic filter) has no
input, and circuit function is identical to the simple
modulator, except that the multiplier is biased to
output quite small ramp amplitudes giving good
resolution to the small signals.
A larger signal input is characterized by consecutive
strings of 1's or O's in the data as the integrator
attempts to track the input. The logic input to the
syllabic filter actuates whenever 3 or more consecutive O's or 1's are present in the data. When this
happens, the syllabic filter output starts to build
up, increasing the multiplier gain, passing larger
amplitude ramps to the comparator, enabling the
system to track the larger signal. Up to a limit,
the more consecutive 1's or O's generated, the.larJler
the ramp amplitude. Since the larger signals increase
the negative feedback of the modulator and the
forward gain of the, demodulator, companding takes
place. By listening tests, the syllabic filter time
constant of 4 to 10 milliseconds is generally considered optimum.
An outstanding characteristic of CVSD is its ability,
with fairly simple circuitry, to transmit intelligible
voice at relatively low data rates. Companded PCM,
for telephone quality transmission, requires about
64K bits/sec· data rate per channel. CVSD produces
equal quality at 32K bits/sec. (However, at this
rate it does not handle tone signals or phase encoded
modern transmissions as well.)
\

CVSD is useful at even lower data rates. At 16K
bits/sec the reconstructed voice is remarkably natural,
but has a slightly "Fuzzy Edge". At 9'.6K bits/sec
intelligibility is still excellent, although the sound

is reminiscent of a damaged loudspeaker. Of course,
very sophisticated speech compression techniques
have been used to transmit speech at even lower data

rates; but CVSD is an excellent compromise between
circuit simplicity and bandwidth economy.'

,...
Q

CD

W

t-

O

z

Ii
Q.

B in Cans.
Dimensions are MIN

and

in inches.

MAX

sse means .§.asic .§pacing Between fenters

12-2

Harris Analog Package Selection Guide

(Continued)

PACKAGE CONFIGURATION (See Note)

PART NUMBER

CAN

PLASTIC

CERDIP

HC-5552
HC-5553
HC-5554
HC-5SS7
HC-SSS36

0
E
C2
C2
B1

HC-SSS64
HD-016S
HF-10
HI-200
HI-201

B1
G
E
B1
C1

HI-201 HS
H 1-300101 104/0S
H 1-302/03/06/07
HI-381/387
HI-384/390
HI-S06/S07
H I-S06A/S07 A
H 1-506L1S07L
HI-S08/S09
HI-S08A/S09A
H I-S08L1S09L
HI-516
HI-518
HI-524
HI-539
HI-546/547
HI-S48/549
HI-562A
HI-565A
HI-574A
HI-674A
HI·774
HI-774A
HI-1818A/28A
HI-5040 thru 5051
HI-5043/45
HI-561O
H 1-5618A/18B
HI-5660/60A
H 1-5680/85/85A/87
H I-S690V195V 197V
HI-5721
HI-7541
HI-DAC16B/C
HV-1000/1000A
HY-94741/2
HY-9574
HY-9674
HY-9590/91
HY-959S/96

X

N

0
0
X
X

N
N
N

0
S
S
S

0
0
P
S

P
P
0
S

0

SIDE BRAZED

CERAMIC
LEAD LESS
CHIP CARRIER

PLASTIC
LEADED
CHIP CARRIER

T

T

C1
B1
B1
B1
C1

T

H
H
H
C1
C1

U

AB

T

AA

T

AA
AA
AA

0
H
0
0
C1
H
C1

J
J
K

K
K
K
0
0

C1
C1

0

C1

U
T
U

AB
AA

V
V
V

J
0

J
J
J
K

U
U

I
L

0
HA
HB
HB
HB
HB

NOTE: "Package Configuration" references drawings on the following pages. Package designations constructing the part number are explained in the
Ordering Information, Section 1.

12-3

Package Configuration
.300 CERAMIC DUAL-IN-LINE

0

. . .,

PKG.
DIM.
If;AO
CODE COUNT

LS1

DIM.

.

DIM.

DIM.

DIM.

DIM.

DIM.

B

B1

e

a

E

.,
:o;s

.315

.

.155

.140

.050

Ssi

:200

.Ot6

-:1iO

'F23

No

"
"
" lsi

.155

.140

.Ots

.050

200

:170

:023

OrO

.155

.140

.016

.050

ToO

:170

:023

:070

:o;s

T85

.155

.140

.016

050"

.753

ToO

-:1To

m3

.00'

m
'DO

170

.140

m

:070"..

.140

.016

.050*

170

:ii23

B1

MSi

e,
e,
a
E

".
Msi
".
lsi
"
"
Lsi
LSI

.155

.200
.155

.1411

:200

ill

.Ot6

.018

m

.00'

.1.,

:m

.00'

.753

mo" ms
.050·

3i5

:DiS

00'

Fs

00'

Ts5

.
.

"
"
305

2i5

DIM.
L1

.

DIM.

'"

Ts5

.753

.285

305
.285

DIM.

DIM.

S1

a

MiN

:320'

Fa

.290

.090

.125

.09<>

.m

.30'

.090

"310
.300

:m-

110
. 090

.150

Tiii

. 080

~

.150

.O8
Source Exif Data: 
File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
Create Date                     : 2013:08:09 16:52:02-08:00
Modify Date                     : 2013:08:10 21:50:34-07:00
Metadata Date                   : 2013:08:10 21:50:34-07:00
Producer                        : Adobe Acrobat 9.55 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:82ef1d0d-8f88-ea43-a4ae-b97e4753f8d3
Instance ID                     : uuid:31dc7d2e-b86e-9a4f-99bb-2fcf41ed8c1e
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 898

EXIF Metadata provided by EXIF.tools