1986_Intersil_Component_Data_Catalog 1986 Intersil Component Data Catalog

User Manual: 1986_Intersil_Component_Data_Catalog

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-UU:I
Component Data
Catalog

1986

CAUTION: Intersil's products are not intended for use as components in any life support or other medical
devices intended for surgical implant into the human body,
Intersil cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an Intersil product. No circuit patent
licenses are implied. Intersil reserves the right to change the circuitry and specifications without notice at any time.
Printed in U.S.A. © Copyright !985, Intersil, Inc., All Rights Reserved

@isaregisteredtrademarkOfGeneral Electric Company, U.S.A.

Table of Contents
Description

Page

Section 1

Selector Guides .................................................................... 1-1

Section 2 -

Discretes

2N2607 P-Charinel JFET General Purpose Amplifier ....................................................... 2-1
2N2608 P-Channel JFET General Purpose Amplifier ....................................................... 2-1
2N2609 P-Channel JFET General Purpose Amplifier ........................................................ 2-1
2N2609JAN P-Channel JFET General Purpose Amplifier .................................................. 2-1
2N3684 N-Channel JFET Low Noise Amplifier ........................ , ...................................... 2--2
2N3685 N-Channel JFET Low Noise Amplifier ......................... ~ ..................................... 2-2
2N3686 N-Channel JFET Low Noise Amplifier ............................................................... 2-2
2N3687 N-Channel JFET Low Noise Amplifier ............................................................... 2-2
2N3810/A Dual Matched PNP General Purpose Amplifier ................................. ~ ............... 2-3
2N3811/ A Dual Matched PNP General Purpose Amplifier ................................ ; ................. 2--3
.2N3821 N-Channel JFET High Frequency Amplifier ........................................................ 2-5
2N3821JAN N-Channel JFET High Frequency Amplifier .................... ~ ............................... 2-5
2N3821JTX N-Channel JFET High Frequency Amplifier .................................................... 2-5
2N3821JTXV N-Channel JFET High Frequency Amplifier .................................................. 2-5
2N3822 N-Channel JFET High Frequency Amplifier ........................................................ 2-5
2N3822JAN N-Channel JFET High Frequency Amplifier ............... : ............ : ...................... 2-5
2N3822JTX N-Channel JFET High Frequency Amplifier .................................................... 2-5
2N3822JTXV N-Channel JFET High Frequency Amplifier ........•.................. , ...................... 2--5
2N3823 N-Channel JFET High Frequency Amplifier ........................................................ 2-7
2N3823JAN N-Channel JFET High Frequency Amplifier ................................................... 2-7
2N3823JTX N-Chan.nel JFET High Frequency Amplifier .................................................... 2-7
2N3823JTXV N-Channel JFET High Frequency Amplifier ......... , ..... , .......•.......................... 2-7
2N3824 N-Channel JFET Switch ........................................... , ..................................... 2-8
2N3921 Dual N-Channel JFET (3eneral Purpose Amplifier ................................................ 2-9
2N3922 Dual N-Channel JFET General Purpose Amplifier ................................................ 2-9
2N3954 Dual N-Channel JFET General Purpose Amplifier ............................... , ............... 2 -11
2N3954A Dual N-Channel JFET General Purpose Amplifier ............................................. 2-11
2N3955 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-11
2N3955A Dual N-Channel JFET General Purpose Amplifier., ........................................... 2-11
2N3956 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-11
2N3957 Dual N-Channel JFET General Purpose Amplifier ., .......................... , .................. 2-11
2N3958 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-11
2N3970 N-Channel JFET Switch ...........................................................'..................... 2-13
2N3971 N-Channel JFET Switch ................................................................................ 2-13
2N3972 N-Channel JFET Switch ................................................................................ 2"': 13
2N3993 P-Channel JFET General Purpose Amplifier/Switch ..................... , ...... : ................ 2-15
2N3994 P-Channel JFET General Purpose Amplifier/Switch ............................................. 2-15
2N4044 Dielectrically Isolated Dual NPN General Purpose Amplifier ................................... 2-17
2N4045 Dielectrically Isolated Dual NPN General Purpose Amplifier ................................... 2-17
2N4100 Dielectrically Isolated Dual NPN General Purpose Amplifier ................................... 2-17
2N4878 Dielectrically Isolated Dual NPN General Purpose Amplifier ................................... 2-17
2N4879 Dielectrically Isolated Dual NPN General Purpose Amplifier .................................... 2-17
2N4880 Dielectrically Isolated Dual NPN General Purpose Amplifier ................................... 2 -17
ITE4091 N-Channel JFET Switch ............................................................................... 2-19
2N4091 N-Channel JFET Switch ................................................................................ 2-19
2N4091 JANTX N-Channel JFET Switch ...................................... , .............................. 2-19

Table
. of Contents
,

Page

Description

Section 2

Discretes (Cont.)

ITE4092 N-Channel JFET Switch ........................ '....................................................... 2-19,
2N4092 N-Channel JFET Switch ............................................................... " ............... 2-19
2N4092 JANTX N-Channel JFET Switch ..................................................................... 2-19
ITE4093 N-Channel JFET Switch ....................................................... , ....................... 2-19
2N4093 N-Channel JFET Switch ................................................................................ 2-19
2N4093 JANTX N-Channel JFET Switch .................. : .................................................. 2-19
2N4117 N-Channel JFET General Purpose Amplifier ...................................................... 2-21
2N4117A N-Channel JFET General Purpose Amplifier .................................................... 2-21
2N4118 N-Channel JFET General Purpose Amplifier ...................................................... 2;...21
2N4118A N-Channel JFET General Purpose Amplifier .................................................... 2-21
2N4119 N-Channel JFET General Purpose Amplifier ...................................................... 2-21
2N4119A N-Channel JFET General Purpose Amplifier .................................................... 2-21
2N4220 N-Channel JFET General Purpose Amplifier/Switch ............................................ 2-22
2N4221 N-Channel JFET General Purpose Amplifier/Switch ............................................ 2~22
2N4222 N-,Channel JFET General Purpose Amplifier/Switch ............................................ 2-22
2N4223 N-Channel JFET High Frequency Amplifier ....................................................... 2-23
2N4224 N-Channel JFET High Frequency Amplifier ....................................................... 2-23
2N4338 N-Channel JFET Low Noise Amplifier .............................................................. 2-24
2N4339 N-Channel JFET Low Noise Amplifier ...... ~ ....................................................... 2-24
2N4340 N-Channel JFET Low Noise Amplifier ..•......... ; ................................................. 2-24
2N4341 N-Channel JFET Low Noise Amplifier .............................................................. 2-24
.2N4351 N-Channel Enhancement Mode MOSFET General Purpose Amplifier/Switch ............. 2-25
ITE4391 N-Channel JFET Switch ............................................................................... 2-26
2N4391 N-Channel JFET Switch ................................................................................ 2-26
ITE4392 N-Channel JFET Switch ............................................................................... 2-26
2N4392 N-Channel JFET Switch ............................................................... ; ................ 2-26
ITE4393 N-Channel JFET Switch ............................................................................... 2:"26
2N4393 N-Channel JFET Switch .............................................•.................................. 2-26
ITE4416 N-Channel JFET High Frequency Amplifier ....................................................... 2-28
2N4416/A N-Channel JFET High Frequency Amplifier .................................................... 2-28
2N4856N-Channel JFET Switch ................................................................................ 2-30
2N4856JAN,JTX,JTXV N-Channel JFET Switch ....................................... ; ...................... 2..:30
2N4857 N-Channel JFET Switch ................................................................................ 2-30
2N4857JAN,JTX,JTXV N-Channel JFET Switch ............................................................. 2-30
2N4858 N-Channel JFET Switch ............................... '................................................. 2-30
2N4858JAN,JTX,JTXV N-Channel JFET Switch .................. , ................................ , ......... 2-30
2N4859 N-Channel JFET Switch ................................................................................ 2-30
2N4860 N-Channel JFET Switch ................................................ : ............................... 2 -30
2N4861 N-Channel JFET Switch.: .............................................................................. 2-30
2N4867/ AN-Channel JFET Low Noise Amplifier ........................................................... 2-32
2N4868/ A N-Channel JFET Low Noise Amplifier ........................................................... 2-32
2N4869! A N-Channel JFET Low Noise Amplifier ........................................................... 2-32
2N5018 P-Channel JFET Switch .: .............................................................................. 2-34
2N5019 P-Channel JFET Switch .......................................................................... ; ..... 2-34.
2N5114 P-Channel JFET Switch ................................................................................ 2-'36
2N5114JAN,JTX,JTXV P-Channel JFET Switch .............. ~ ............................................... 2-36
2N5115 P-ChannelJFET Switch .......................................................... : ..................... 2-36
2N5115JAN,JTX,JTXV P-Channel JFET Switch .................. ; .................................. ; ........ 2-36
2N5116 P-Channel JFET Switch ................................................................................ 2-36

2

Table of Contents
Description

Section 2 -

Page

Discretes (Cont.)

2N5116JAN,JTX,JTXV P-Channel JFET Switch .............................................................. 2-36
2N5117 Dielectrically Isolated Dual PNP General Purpose Amplifier ................................... 2-38
2N5118 Dielectrically Isolated Dual PNP General Purpose Amplifier ................................... 2-38
2N5119 Dielectrically Isolated Dual PNP General Purpose Amplifier ................................... 2-38
2N5196 DualN-Channel JFET General Purpose Amplifier ............................................... 2~40
2N5197 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-40
2N5198 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-40
2N5199 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-40
2N5397 N-Channel JFET High Frequency Amplifier ....................................................... 2-42
2N5398 N-Channel JFET High Frequency Amplifier ....................................................... 2-42
2N5432 N-Channel JFET Switch ................................................................................ 2 -44
2N5433 N-Channel JFET Switch ................................................................................ 2-44
2N5434 N-Channel JFET Switch ........................................................ ; ....................... 2-44
2N5452 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-46
2N5453 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-46
2N5454 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-46
2N5457 N-Channel JFET General Purpose Amplifier/Switch ............................................ 2-48
2N5458 N-Channel JFET General Purpose Amplifier/Switch ............................................ 2-48
2N5459 N-Channel JFET General Purpose Amplifier/Switch ............................................ 2-48
2N5460 P-Channel JFET Low Noise Amplifier ........................................................... ; .. 2-49
2N5461 P-Channel JFET Low Noise Amplifier .............................................................. 2-49
2N5462 P:...Channel JFET Low Noise Amplifier .............................................................. 2-49
2N5463 P-Channel JFET Low Noise Amplifier .............................................................. 2-49
2N5464 P-Channel JFET Low Noise Amplifier .............................................................. 2-49
2N5465 P-Channel JFET Low Noise Amplifier ............................................................... 2-49
2N5484 N-Channel JFET High Frequency Amplifier ....................................................... 2-50
2N5485 N-Channel JFET High Frequency Amplifier ....................................................... 2-50
2N5486 N-Channel JFET High Frequency Amplifier ........................................................ 2-50
2N5515 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-52
2N5516 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-52
2N5517 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-52
2N5518 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-52
2N5519 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-52
2N5520 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-52
2N5521 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-52
2N5522 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-52
2N5523 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-52
2N5524 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-52
2N5638 N-Channel JFET Switch ................................................................................ 2-54
2N5639 N-Channel JFET Switch ................................................................................ 2-54
2N5640 N-Channel JFET Switch ................................................................................ 2-54
2N5902 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-56
2N5903 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-56
2N5904 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-56
2N5905 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-56
2N5906 Dual N-Channel JFET General Purpose Amplifier .......................................... ; .... 2-56
2N5907 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-56
2N5908 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-56
2N5909 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-56

3

Table of Contents
'Oescription

Section 2 -

Page

Discretes (Cont.)

2N5911 Dual N-Channel JFET High Frequency Amplifier ............•.............•..................... 2-58
IT5911 Dual N-Channel JFET High Frequency Amplifier: .............'..•...•...............'....... , ....... 2-58
2N5912 Dual N-Channel JFET High Frequency Amplifier ................................................ 2-58
IT5912 Dual N-Channel JFET High Frequency Amplifier ............................................... , .. 2-58
2N6483 Dual N-Channel JFET Low Noise Amplifier ................•...................................... 2:...60
2N6484 Dual N-Channel JFET Low Noise Amplifier ...........•........................................... 2-60
2N6485 Dual N-Channel JFET Low Noise Amplifier ....... : ............................. , ................. 2-60
IMF6485 Dual N-Channel JFET Low Noise Amplifier ....... ; .. , ........................................... 2-62
3N161 Diode Protected P-Channel Enhancement Mode MOSFETGeneral Purpose Amplifier/
Switch ............................................................................................................. 2-64
3N163 P-Channel Enhancement Mode MOSFET General Purpose Amplifier/Switch .............. 2-65
3N164 P-Channel Enhancement Mode MOSFET General Purpose/Switch ........................... 2-65
3N165 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier ................. 2-67
3N166 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier ................. 2-67
3N170 N-Channel Enhancement Mode MOSFET Switch ................................................. 2-69
3N171 N-Channel Enhancement Mode MOSFET Switch ...... , .......................................... 2-69
3N 172 Diode Protected P-Channel Enhancement Mode MOSFET General Purpose Amplifier /
'
.Switch .............................................................. , ............................................. 2-7.1
3N173 Diode Protected P-Channel Enhancement Mode MOSFET General Purpose Amplifier/
Switch ............................................................................................................ 2-71
3N 188 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier ................. 2 - 72
3N189 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier ................. 2-72
3N 190 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier ................. 2 - 72
3N191 Dual P--Channel Enhancement Mode MOSFETGeneral Purpose Amplifier ................. 2-72
ID100 Dual Low Leakage Diode ................................................................................ 2-74
ID101 Dual Low Leakage Diode ................................................................................ 2-74
IT100 P-Channel JFET Switch ............................................ : ...................................... 2-76
IT101 P-Channel JFET Switch ................. '.................................................................. 2-76
IT120 Dual NPN General Purpose Amplifier .................................................................. 2-77
IT120A Dual NPN General Purpose Amplifier ................................................................ 2:... 77
IT121 Dual NPN General Purpose Amplifier .................................................................. 2- 77
IT122 Dual NPN General Purpose Amplifier .................................................................. 2-77
IT124 Dual Super-Seta NPN General Purpose Amplifier ................................... : .............. 2 -79
IT126 Dual NPN General Purpose Amplifier .................................................................. 2-81
IT127 Dual NPN General Purpose Amplifier .................................................................. 2-81
IT128 Dual NPN General Purpose Amplifier .................................................................. 2-81
IT129 Dual NPN General Purpose Amplifier .................................................................. 2-81
IT130 Dual PNP General Purpose Amplifier ................................................................... 2-83
IT130A Dual PNP General Purpose Amplifier ........................................ , ....................... 2-83
IT131 Dual PNP General Purpose Amplifier .................................. , ................................. 2-83
IT132 DualPNP General Purpose Amplifier .................................'..........................•...... 2-83
IT136 Dual PNP General Purpose Amplifier ................................................................... 2-85
IT137 Dual PNP General Purpose Amplifier .................................................................. 2-85
IT138 Dual PNP General Purpose Amplifier ........................................................ , .......... 2-85
IT139 Dual PNP General Purpose Amplifier .................................................................. 2-85
IT500 Dual Cascoded N-Channel JFET General Purpose Amplifier .................. : ................. 2-87
·IT501 Dual Cascoded N-Channel JFET General Purpose Amplifier ..........................•......... 2 .... 87
1T502 Dual Cascoded N-Channel JFET General Purpose Amplifier .................................... 2-87
IT503 Dual Cascoded N-Channel JFET General Purpose Amplifier .................................... 2-87

4

Table of Contents
Description

Section 2 -

Page

Discretes (Cont.)

IT504 Dual Cascoded N-Channel JFET General Purpose Amplifier .................................... 2-87
IT505 Dual Cascoded N-Channel JFET General Purpose Amplifier .................................... 2-87
IT550 Dual N-Channel JFET Switch ........................................................................... 2-90
IT1700 P-Channel Enhancement Mode MOSFET General Purpose Amplifier ........................ 2-92
IT1750 N-Channel Enhancement Mode MOSFET General Purpose Amplifier/Switch .............. 2-93
J105 N-Channel JFET Switch ................................................................................... 2-94
J106 N-Channel JFET Switch ................................................................................... 2-94
J107 N-Channel JFET Switch ................................................................................... 2-94
J111 N-Channel JFET Switch ................................................................................... 2-95
J112 N-Channel JFET Switch ................................... '........................................... : .... 2-95
J113 N-Channel JFET Switch ................................................................................... 2-95
J 174 P-Channel J FET Switch .................................................................................... 2 -97
J175 P-Channel JFET Switch ......................................................................... .' ..... : .... 2-97
J176 P-Channel JFET Switch .................................................................................... 2-97
J177 P-Channel JFET Switch .................................................................................... 2-97
J201 N-Channel JFET General Purpose Amplifier .......................................................... 2-99
J202 N-Channel JFET General Purpose Amplifier ......................................................... ;2-99
J203 N-Channel JFET General Purpose Amplifier ...................................... , ................... 2-99
J204 N-Channel JFET General Purpose Amplifier .......................................................... 2-99
J308 N-Channel JFET High Frequency Amplifier ... , ..................................................... 2-100
J309 N-Channel JFET High Frequency Amplifier ..... : ........................................ : .......... 2-100
J310 N-Channel JFET High Frequency Amplifier ....................................... ; ............ : .... 2-100
LM114/H Dual NPN General Purpose Amplifier ........................................................... 2-102
LM114A1AH Dual NPN General Purpose Amplifier ....................................................... 2-102
M116 Diode Protected N-Channel Enhancement Mode MOSFET General Purpose Amplifier. 2 -104
U200 N-Channel JFET Switch ................................................................................. 2-105
U201 N-Channel JFET Switch ................................................................................. 2-105
U202 N-Channel JFET Switch ................................................................................. 2-105
U231 Dual N-Channel JFET General Purpose Amplifier ................................................ 2-106
U232 Dual N-Channel JFET General Purpose Amplifier ................................................ 2-106
U233 Dual N-Channel JFET General Purpose Amplifier ................................................ 2-106
U234 Dual N-Channel JFET General Purpose Amplifier ................................................ 2-106
U235 Dual N-Channel JFET General Purpose Amplifier ................................................ 2-106
U257 Dual N-Channel JFET High Frequency Amplifier ......................... , ................... : .... 2-108
U304 P-Channel JFET Switch ................................................................................. 2-109
U305 P-Channel JFET Switch ................................................................................. 2-109
U306 P-Channel JFET Switch ................................................................................. 2-109
U308 N-Channel JFET High Frequency Amplifier ......................................................... 2-111
U309 N-Channel JFET High Frequency Amplifier ......................................................... 2-111
U310 N-Channel JFET High Frequency Amplifier ...................... : .................................. 2-111
U401 Dual N-Channel JFET Switch ............................... , ............................. , ............ 2 -113
U402 Dual N-Channel JFET Switch .......................................................................... 2-113
U403 Dual N-Channel JFET Switch .......................................................................... 2-113
U404 Dual N-Channel JFET Switch .......................................................................... 2-113
U405 Dual N-Channel JFET Switch .......................................................................... 2-113
U406 Dual N-Channel JFET Switch .......................................................................... 2-113
U1897 N-Channel JFET Switch ............................................................................... 2-115
U1898 N-Channel JFET Switch ............................................................................... 2-115
U1899 N-Channel JFET Switch ..................................... ;;'....................................,.... 2-115

5

Table of Contents
Page

Description

Section 2 -

Discretes (Cont.)

VCR2N Voltage Controlled Resistors ..........................................•.............................. 2-117
VCR3P Voltage Controlled Resistors ......................................................................... 2-117
VCR4N Voltage Controlled Resistors ............................... , ............... ~ •........................ 2-117
VCR7N Voltage Controlled Resistors ........................ ; ................................................ 2-117
VCR11N Voltage Controlled Resistors ....................................................................... 2-120

Section 3 -

Analog Switches and Multiplexers

D123 SPST 6-Channel JFET Switch Driver ......................................... , ......................... 3-1
D125 SPST 6-Channel JFET Switch Driver ................................................................... 3-1
D129 4-Channel Decoded JFET Switch Driver ............................................................... 3-6
DG118 SPST 4-Channel Driver With Switch ................................... ; .............................. 3-8
DG123 SPST 5-Channel Driver With Switch .................................................................. 3-8
DG125 SPST 5-Channel Driver With Switch .................................................................. 3-8
DG126 Dual DPST 80 Ohm JFET Analog Switch .......................................................... 3-12
DG129 Dual DPST 30 Ohm JFET Analog Switch .......................................................... 3:...12
DG133 Dual SPST 30/35 Ohm JFET Analog Switch ...................................................... 3-12
DG134 Dual SPST 80 Ohm JFET Analog Switch .......................................................... 3-12
DG140 Dual DPST 10/15 Ohm JFETAnalog Switch ...................................................... 3-12
DG141 Dual ~PST 10 Ohm JFET Analog Switch .......................................................... 3-12
DG151 Dual SPST 15 Ohm JFET Analog Switch .......................................................... 3-12
DG152 Dual SPST 50 Ohm JFET Analog Switch .......................................................... 3-12
DG153 Dual DPST 15 Ohm JFET Analog Switch .. , ....................................................... 3-12
DG154 Dual DPST 50 Ohm JFET Analog Switch .......................................................... 3'-12
DG139 DPDT 30 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG142. DPDT 80 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG143 SPDT 80 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG144 SPDT 30 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG145 DPDT 10 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG146 SPDT 10 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG161 SPDT 15 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG162 SPDT 50 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG163 DPDT 15 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG164 DPDT 50 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG180 Dual SPST 10 Ohm High-Speed Driver With JFET Switch ..................................... 3-22
DG181 Dual SPST 30 Ohm High-Speed Driver With JFET Switch ..................................... 3-22
DG 182 Dual SPST 75 Ohm High-Speed Driver With JFET Switch ..................................... 3 -22
DG183 Dual DPST 10 Ohm High-Speed Driver With JFET Switch ..................................... 3-22
DG184 Dual DPST 30 Ohm High-Speed Driver With JFET Switch ..................................... 3-22
DG185 Dual DPST 75 Ohm High-Speed Driver With JFET Switch ...................................... 3-22
DG186 SPDT10 Ohm High-Speed Driver With JFET Switch ............................................ 3-22
OG187 SPDT 30 Ohm High-Speed Driver With JFET Switch ............................................ 3-22
DG188 SPDT 75 Ohm High-Speed Driver With JFET Switch ............................................ 3-22
DG189 Dual SPDT10 Ohm High-Speed Driver With JFET Switch ..................................... 3:"'22
DG190 Dual SPDT 30 Ohm High-Speed Driver With JFETSwitch ..................................... 3-22
DG191 Dual SPOT 75 Ohm High-Speed Driver With JFET Switch ..................................... 3-22
DG200 Dual SPST CMOS Analog Switch ..• ; ................................................................. 3-27
IH5200 Dual SPST CMOS Analog Switch ..................................................................... 3-27
DG201 Quad SPST CMOS Analog Switch .................................................................... 3-32

6

Table of Contents
Description

Section 3 -

Page

Analog Switches and Multiplexers (Cont.)

IH5201 Quad SPST CMOS Analog Switch ................................................................... 3-32
DG211 SPST 4-Channel Analog Switch ....................................................................... 3-36
DG212 SPST 4-Channel Analog Switch ....................................................................... 3-36
DGM181 Dual SPST 50 Ohm High-Speed CMOS Analog Switch ...................................... 3-39
DGM182 Dual SPST 50/75 Ohm High-Speed CMOS Analog Switch .................................. 3-39
DGM184 Dual DPST 50 Ohm High-Speed CMOS Analog Switch ...................................... 3-39
DGM185 Dual DPST 50/75 Ohm High-Speed CMOS Analog Switch .................................. 3-39
DGM187 SPOT 50 Ohm High-Speed CMOS Analog Switch ............................................. 3-39
DGM188 SPOT 50/75 Ohm High-Speed CMOS Analog Switch ......................................... 3-39
DGM190 Dual SPOT 50 Ohm High-Speed CMOS Analog Swi.tch ...................................... 3-39
DGM191 Dual SPOT 50/75 Ohm High-Speed CMOS Analog Switch .................................. 3-39
G115 6-Channel MOSFET Switch .............................................................................. 3-45
G123 4-Channel MOSFET Switch .............................................................................. 3-45
G116 5 Channel MOSFET Switch .............................................................................. 3-48
G118 6 Channel MOSFET Switch ..................................... " ....................................... 3-48
G119 6 Channel MOSFET Switch .............................................................................. 3-48
IH311 High Speed SPST 4-Channel Analog Switch ....................................................... 3-52
IH312 High Speed SPST 4-Channel Analog Switch ....................................................... 3-52
IH401 QUAD Varafet Analog Switch ........................................................................... 3-59
IH401A QUAD Varafet Analog Switch ............................................................ , ............ 3-59
IH5009 Quad 100 Ohm Virtual Ground Analog Switch ................................................ : .... 3-65
IH5010 Quad 150 Ohm Virtual Ground Analog Switch .............................................•...... 3-65
IH5011 Quad 100 Ohm Virtual Ground Analog Switch .................................................. ~. 3-65
IH5012 Quad 150 Ohm Virtual Ground Analog Switch .................................................... 3-65
IH5013 Triple 100 Ohm Virtual Ground Analog Switch ....... " ........................................... 3-65
IH5014 Triple 150 Ohm Virtual Ground Analog Switch .................................................... 3-65
IH5015 Triple 100 Ohm Virtual Groung Analog .Switch .................................................... 3-65
IH5016 Triple 150 Ohm Virtual Ground Analog Switch ..................................................... 3-65
IH5017 Dual 100 Ohm Virtual Ground Analog Switch , .................................................... 3-65
lH5018 Dual 150 Ohm Virtual Ground Analog Switch ..................................................... 3-65
IH5019 Dual 100 Ohm Virtual Ground Analog Switch ..................................................... 3-65
IH5020 Dual 150 Ohm Virtual Ground Analog Switch ..................................................... 3-65
IH5021 Single 100 Ohm Virtual Ground Analog Switch ................................................... 3-65
IH5022 Single 150 Ohm Virtual Ground Analog Switch ................................................... 3-65
IH5023 Single 100 Ohm Virtual Ground Analog Switch ................................................... 3-65
IH5024 Single 150 Ohm Virtual Ground Analog Switch ................................................... 3-65
IH5025 Quad 100 Ohm Positive Signal Analog Switch ........... , ........................................ 3-71
IH5026 Quad 150 Ohm Positive Signal Analog Switch .................................................... 3-71
IH5027 Quad 100 Ohm Positive Signal Analog Switch .................................................... 3 - 71
IH5028 Quad 150 Ohm Positive Signal Analog Switch .................................................... 3 - 71
IH5029 Triple 100 Ohm Positive Signal Analog Switch .................................................... 3-71
IH5030 Triple 150 Ohm Positive Signal Analog Switch .................................................... 3-71
IH5031 Triple 100 Ohm Positive Signal Analog Switch .................................................... 3-71
IH5032 Triple 150 Ohm Positive Signal Analog Switch .......................,............................. 3-71
IH5033 Dual 100 Ohm Positive Signal Analog Switch ..................................................... 3-71
IH5034 Dual 150 Ohm Positive Signal Analog Switch ..................................................... 3-71
IH5035 Dual 100 Ohm Positive Signal Analog Switch ..................................................... 3-71
IH5036 Dual 150 Ohm Positive Signal Analog Switch ..................................................... 3-71
IH5037 Single 100 Ohm Positive Signal Analog Switch .......... : ........................................ 3-71

7

Table of Contents
Description

Page

Section 3 -Analog Switches and Multiplexers (Cont.)
IH5038 Single 1'50 Ohm Positive Signal Analog Switch ..................................................... 3-71
IH5040 SPST 75 Ohm High-Level CMOS Analog Switch ....... , .........................................,3-.79
IH5041 Dual SPST 75 Ohm High-Level CMOS Analog Switch .......................................... 3-79
IH5042 SPOT 75 Ohm High-Level CMOS Analog Switch ............. ; ......................... , ....... ,. 3-79
IH5043 Dual SPOT 75 Ohm High-Level CMOS Analog Switch ............................... , ......... , 3-79
IH5044 DPST 75 Ohm High-Level CMOS Analog Switch .............................. ; ....... , .......... 3-]9
IH5045 Dual DPST 75 Ohm High-Level CMOS Analog Switch .......................................... 3-79
IH5046 DPDT 75 Ohm High-Level CMOS Analog Switch ........................................' .......... 3-79
IH5047 4PST 75 Ohm High-Level CMOS Analog Switch ....... ; ..... : .................................... 3-79
IH5048 Dual SPST 35 Ohm High-Level CMOS Analog Switch ........................................... 3-88
IH5049 Dual DPST 35 Ohm High-Level CMOS Analog Switch .......................................... 3-88
IH5050 SPOT 35 Ohm High-Level CMOS Analog Switch ................................................. 3-88
IH5051 Dual SPOT 35 Ohm High-Level CMOS Analog Switch ......................" ................... 3-88
IH5052 QUAD CMOS Analog Switch ........................................................................... 3-93
IH5053 QUAD CMOS Analog Switch ........................................................................... 3-93
IH5108 8-Ch~nnel Fault Protected Analog Multiplexer ............................................. , ....... 3-99
IH5116 16-Channel Fault Protected Analog Multiplexer .............. 01 . . . . . . . . . . . . . , " . . . . . . . . . . . . . . . . . . . 3 -1 07
IH5140 SPST High-Level CMOS Analog Switch ..................................... ; ................ ; .... 3-110
IH5141 Dual SPST High-Level CMOS Analog Switch ..................................................... 3 -110
IH5142 SPOT Hig~-Level CMOS Analqg Switch ................................................ ; .... , ..... 3-110
IH5f43 Dual SPOT High-Level CMOS Analog Switch .................................................... 3-110
IH5144 DPST High-Level CMOS Analog Switch ................................ ; .......................... 3-110
IH5145 Dual DPST High-Level CMOS Analog Switch ............................... , ..................... 3-110
IH5148 Dual SPST High-Level CMOS Analog Switch ...................... : ..... ; ....................... 3-119
IH5149 Dual DPST High-Level CMOS Analog Switch ........................ , .. , ...... , .................. 3-119
IH5150 SPOT High-Level CMOS Analog Switch .......................,.................................... 3-119
IH5151 Dual SPOT High-Level CMOS Analog Switch ........ , ........................................... 3-119
IH5208 4-Channel Differential Fault Protectbu Analog Multiplexer .................................... 3-127
IH52168-Channel Differential Fault Protected Analog Multiplexer •........• ~ ......................... 3-135
IH5341 Dual SPST CMOS RFlVideo Switch ............... : ................................................ 3-1.38
IH5352 QUAD SPST CMOS RFlVideo Switch ............................................................. 3-144
IH6108 8-Channel CMOS Analog Multiplexer ................................... , .......................... 3-149
IH6116 16-Channel CMOS Analog Multiplexer ................................ ; ............. ; ............. 3-155
IH6201 Dual CMOS DriverlVoltage Translator ........................... ; ................................. 3-162
IH6208 4-Channel Differential CMOS Analog Multiplexer ............................................... 3-166
IH6216 8-Channel Differential CMOS Analog Multiplexer ............. ; ................................. 3-172
MM450 Dual Differential High Voltage Analog Switch .................................................... 3-178
MM550 Dual Differential High Voltage Analog Switch ................................................... 3-178
MM451 Four Channel High Voltage Multiplexer ............................................................3.-178
MM551 Four Channel High Voltage Multiplexer ........................................................... 3-178
MM452 Quad SPST High Voltage Analog Switch ............ "................... : ........................ 3-178
MM552 Quad SPST High Voltage Analog Switch .......................................................... 3-178
MM455 Three SPST High Voltage Analog Switch ..,...................................................... 3-178
MM555 Three SPST High Voltage Analog Switch ........................................................ :)-178

Section 4 -

Amplifiers -

Operational and Special Purpose

ICH8500/ A Ultra Low Input-Bias Operational Amplifier ..................................................... 4-1
ICH8510 Power Operational Amplifier ........................................................................... 4-7

8

Table of Contents
Description

Section 4 (Cont.)

Page

Amplifiers -

Operational and Special Purpose

rCH8520 Power Operational Amplifier ........................................................................... 4-7
ICH8530 Power Operational Amplifier ........................................................................... 4-7
ICH8515 Power Operational Amplifier ......................................................................... .4-16
,ICL7605 Commutating Auto-Zero (CAZ) Instrumentation Amplifier ...................................... 4-23
ICL7606 Commutating Auto-Zero (CAD) Instrumentation Amplifier ...................................... 4-23
ICL76XX Series Low Power CMOS Operational Amplifiers .............................................. .4-34
ICL7650 Chopper-Stabilized Operational Amplifier .......................................................... 4-50
ICL7652 Chopper-Stabilized Low-Noise Operational Amplifier ........................................... 4-57
ICL8007 JFET Input Operational Amplifier .................................................................... 4-65
ICL8021 Low Power Bipolar Operational Amplifier .......................................................... 4-69
ICL8022 Dual Low Power Bipolar Operational Amplifier ....................................... : .......... .4-69
ICL8023 Triple Low Power Bipolar Operational Amplifier .................................................. 4-69
. ICL8043 Dual JFET Input Operational Amplifier ............................................................ .4-74
ICL8048 Logarithmic Amplifier .................................................................................... 4-82
ICL8049 Antilog Amplifier ......................................................................................... 4-82
ICL8063 Power Transistor Driver/Amplifier ................................................................... .4-90
LH2108 Dual Super-Beta Operational Amplifier ............................................................ .4-99
LH2308 Dual Super-Beta Operational Amplifier ............................................................ .4-99
LM108/A Super-Beta Operational Amplifier ................................................................ 4-102
LM308/A Super-Beta Operational Amplifier ................................................................ 4-102
NE/SE592 Video Amplifier ................................................................................ ; ..... 4-106

Section 5 -

Special Analog Functions

AD590 2-Wire Current Output Temperature Transducer .................................................... 5-1
ICL7660 CMOS Voltage Converter ............................................................................... 5.,.12
ICL7662 CMOS Voltage Converter .............................................................................. 5-20
ICL7663 CMOS Programmable Micropower Positive Voltage Regulator ............................... 5-27
ICL7664 CMOS Programmable Micropower Negative Voltage Regulator .............................. 5-27
ICL7665 Micropower Under/Over Voltage Detector ......................................................... 5-39
ICL7667 Dual Power MOSFET Driver .......................................................................... 5-47
ICL7673 Automatic Battery Back-up Switch .................................................................. 5-55
ICL8013 Four Quadrant Analog Multiplier ..................................................................... 5-63
ICL8038 Precision Waveform Generator/Voltage Controlled Oscillator ................................. 5-72
ICL8069 Low Voltage Reference ................................................................................ 5-81
ICL8211 Programmable Voltage Detector ..................................................................... 5-83
ICL8212 Programmable Voltage Detector ..................................................................... 5-83
IH5110 General Purpose Sample & Hold ..................................................................... 5-94
IH5111 General Purpose Sample & Hold ..................................................................... 5-94
IH5112 General Purpose Sample & Hold ..................................................................... 5-94
IH5113 General Purpose Sample & Hold ..................................................................... 5-94
IH5114 General Purpose Sample & Hold ..................................................................... 5-94
IH5115 General Purpose Sample & Hold ..................................................................... 5-94

Section 6 -

Data Acquisition

AD7520 10/ 12-Bit Multiplying D/ A Converter ................................................................. 6-1
AD7521 10/12-Bit Multiplying D/ A Converter ........................................................ ; ........ 6-1

9

Table of Contents
Page

Description

Section 6 -

Data Acquisition (Cont.)

AD7530 10/12-Bit Multiplying D/A Converter ................................................................. 6-1
AD7531 10/12-Bit Multiplying D/ A Converter ............................ ; .................................•.. 6-1
AD7523 8-Bit Multiplying D/ A Converter ....................................................................... 6-7
AD7533 10-Bit Multiplying D/ A Converter ................. , .........................................', ........ 6-11
AD7541 12-Bit Multiplying D/A Converter .................................................................... 6-16
ADC0802 8-Bjt J,LP-Compatible AID Converter ............................................................... 6-22
ADC0803 8-Bit J,LP-Compatible AID Converter .. ; ............................................................ 6-22
ADC0804 8-Bit J,LP-Compatible AID Converter ................................................................6-22
ICL7106 3 Y2-Digit LCD Single-Chip AID Converter ....................................................... 6-37
ICL7107 3 Y2-Digit LED Single-Chip AID Converter ....................................................... 6-37
ICL7109 12-Bit J,LP-Compatible AID Converter ............................................................... 6-48
ICL7115 14-Bit High-Speed CMOS J,LP-Compatible AID Converter .................................... 6-66
ICL7116 3 Y2-Digit with Display Hold Single-Chip AID Converter ........................................ 6-78
ICL7117 3 Y2-Digit with Display Hold Single-Chip AID Converter ...................................... 6-78
ICL7126 3 Y2-Digit Low-Power Single-Chip AID Converter .............................................. 6-88
ICL7129 4 Y2 Digit I.CD Single-Chip AID Converter ....................................................... 6-98
ICL7134 14-Bit Multiplying J,LP-Gompatible D/A Converter .............................................. 6-109
ICL7135 4 Y2-Digit BCD Output AID Converter ............................................................ 6-121
ICL7136 3 Y2-Digit LCD Low Power AID Converter ...................................................... 6-132
ICL71373 Y2-Digit LED Low Power Single-Chip AID Converter ...................................... 6-142
ICL8018A 4-Bit Expandable Current Switch ................................................................ 6-151
ICL8019A 4-Bit Expandable Current Switch ................................................................ 6-151
ICL8020A 4-Bit Expandable ~urrent Switch ................................................................ 6-151
ICL7104/ICL8052 12/14/16-Bit J,LP-Compatible 2-Chip AID Converter ................... " ......... 6-157
ICL7104/1CL8068 12/14/16-Bit J,LP-Gompatible 2-Chip AID Converter ............................. 6-157
.

Section 7 -

(

Timer/Counter Circuits

ICM7206 CMOS Touch-Tone Encoder .......................................................................... 7-1
ICM7207/A CMOS Timebase Generator ....................................................................... 7 -10
ICM7208 7-Digit LED Display Counter ......................................................................... 7 -15
ICM7209 Timebase Generator ................................................................................... 7 -22
ICM7213 One Second/One Minute Timebase Generator ................................................. 7 -25
ICM72Hi 6-Digit LED Display 4-Function Stopwatch ...................................................... 7 -30
ICM7216A 8-Digit Multi-Function Frequency Counter/Timer .............................................. 7-36
ICM7216B 8-Digit Multi-Function Frequency Counter/Timer .............................................. 7-36
ICM7216C 8-Digit Multi-Function Frequency Counter/Timer .............................................. 7 -36
ICM7216D 8-Digit Multi-Function Frequency Counter/Timer ............................................. 7-36
ICM7217 4-Digit LED Display Programmable Up/Down Counter ........................................ 7 -52
ICM7227 4-Digit LED Display Programmable Up/Down. Counter ........................................ 7 -52
ICM7224 4 Y2-Digit LCD/LED Display Counter .......................... ; ................................... 7 -67
ICM7225 4 Y2-Digit LCD/LED Display Counter .............................................................. 7 -67
ICM7226A1B 8-Digit Multi-Function Frequency Counter/Timer .......................................... 7-75
ICM7236 4 Y2-Digit CounterlVacuum Fluorescent Display Driver ........................................ 7-88
ICM7240 Programmable Timer ................................................................................... 7 -93
ICM7250 Programmable Timer ...................................... , .......................................... ;. 7-93
ICM7260 Programmable Timer ................................................................................... 7-93
ICM7241 Timebase Generator ............................ , .................... : ............................... 7-103
ICM7242 Long-Range Fixed Timer ........................................................................... 7-105

10

Table of Contents
Page

Description

Section 7 ICM7245
IGM7249
ICM7555
ICM7556

Stepper Motor Quartz Clock ....................................................................... 7 -111
S-Y2 Digit LCD J..!-Power Event/Hour Meter .................................................... 7-115
General Purpose Timer .............................................................................. 7 -123
Dual General Purpose Timer ..................................... ,.................................. 7-123

Section 8 ICM7211
ICM7212
ICM7218
ICM7231
ICM7232
ICM7233
ICM7234
ICM7235
ICM7243
ICM7280
ICM7281
ICM7283

Timer/Counter Circuits (Cont.)

Display Drivers

4-Digit LCD/LED Display Driver ..................................................................... 8-1
4-Digit LCD/LED Display Driver ........................ ; ............................................ 8-1
8-Digit LED Multiplexed Display Driver ............................................................ 8-1 0
Numeric Triplexed LCD Display Driver ............................................................ 8-20
Numeric Triplexed LCD Display Driver ............................................................ 8-20
Alphanumeric Triplexed LCD Display Driver ...................................................... 8-20
Alphanumeric Triplexed LCD Display Driver ...................................................... 8-20
4-Digit Vacuum Fluorescent Display Driver ...................................................... 8-40
8'-Character LED J..!P-Compatible Display Driver ................................................ 8-45
Dot Matrix LCD Controller/Row Driver ............................................................ 8-54
40-Column LCD Dot Matrix Display Driver ....................................................... 8-69
LCD Dot Matrix Controller/Row Driver ............................................................ 8-79

Section 9 -

Microcontrollers, Microperipherals, Memory

ICM7170 J..!P'-Compatible Real-Time Clock ..................................................................... 9-1
IM4702/4712 Baud Rate Generator ............................................................................. 9-9
IM6402 Universal Asynchronous Receiver Transmitter (UART) .......................................... 9-16
IM6403 Universal Asynchronous Receiver Transmitter (UART) .......................................... 9-16
IM6653 4096-Bit CMOS UV EPROM .......................................................................... 9-25
IM6654 4096-Bit CMOS UV EPROM .......................................................................... 9-25
IM80C35 B-Bit CMOS Microcontroller .......................................................................... 9-33
IM80C39 B-Bit CMOS Microcontroller .......................................................................... 9-33
IM80C48 B-Bit CMOS Microcontroller .......................................................................... 9-33
IM80C49 B-Bit CMOS Microcontroller .......................................................................... 9-33
IM82C43 CMOS I/O Expander ..........................•....................................................... 9-45

Section 10 - High Reliability/Military Products and Ordering
Information .................................................................................................... 10:"1

11

Alphanumeric Index
2N2607 P-Channel JFET General Purpose Amplifier ....................................................... 2-1
2N2608 P-Channel JFET General Purpose Amplifier .............................................• , ... ; .... 2-1
2N2609 P-Channel JFET General Purpose .Amplifier ....................................................... 2-1
2N2609JAN P-Channel JFET Gen.eral Purpose Amplifier ............................................ , ...".2-'1
2N3684 N-Channel JFET Low Noise Amplifier ............................................................... 2-2
2N3685 N-Channel JFET Low Noise Amplifier ............................................................... 2-2'
2N3686 N-Channel JFET Low Noise Amplifier ............................................................... 2-2
2N3687 N-Channel JFET Low Noise Amplifier ............................................................... 2-2
2N3810/A Dual Matched PNP General Purpose Amplifier ................................................. 2-3
2N3811 / A Dual Matched PNP General Purpose Amplifier ................................................. 2-3
2N3821 N-Channel JFET High Frequency Amplifier ............................................... ; ....../.2-5
2N3821JAN N-Channel JFET High Frequency Amplifier ................................................... 2-5
2N3821 JTX N-Channel JFET High Frequency Amplifier ...... : ............................................. 2-5
2N3821JTXV N-Channel JFET High Frequency Amplifier ........ ~ ......................................... 2-5
2N3822 N-Channel JFET High Frequency Amplifier .................... : ................................... 2-5
2N3822JAN N-Channel JFET High Frequency Amplifier ................................................... 2-5
2N3822JTX N-Channel JFET High Frequency Amplifier .................................................... 2-$
2N3822JTXV N-Channel JFET High Frequency Amplifier .................................................. 2-5
2N3823 N-Channel JFET High Frequency Amplifier ........................................................ 2-7
2N3823JAN N-Channel JFET High Frequency Amplifier ................................................... 2-7
2N3823JTX N-Channel JFET High Frequency Amplifier .................................................... 2..., 7
2N3823JTXV N-Channel JFET High Frequency Amplifier .................................................. 2-7
2N3824 N-Channel JFET Switch .................... ~ ............................................................ 2-8
2N3921 Dual N-Channel JFET General Purpose Amplifier ................................................ 2-9
2N3922 Dual N-Channel.JFET General Purpose Amplifier ..................................... , .......... 2-9
2N3954 Dual N-Channel JFET General Purpose Amplifier ............................................... 2 -11
2N3954A Dual N-Channel JFET General Purpose Amplifier ..... ; ....................................... 2-11
2N3955 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-11
2N3955A Dual N-Channel.JFET General Purpose Amplifier ............................................. 2-11
2N3956 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-11
2N3957 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-11
2N3958 Dual N-Channel JFET General Purpose Amplifier ...................... , ....................;.... 2-11
2N3970 N-Channel JFET Switch ................................................................................. 2-13
2N3971 N-Channel JFET Switch ................................................................................ 2-13
2N3972 N-Channel JFET Switch ................................................................................ 2-13
2N3993 P-Channel JFET General Purpose Amplifier/Switch ............................................. 2-15
2N3994 P-Channel JFET General Purpose Amplifier/Switch ............................................. 2-15
2N4044 Dielectrically Isolated Dual NPN General Purpose Amplifier ................................... 2-17
2N4045 Dielectrically Isolated Dual NPN General, Purpose Amplifier ................................... 2-17
2N4091 JANTX N-Channel JFET Switch ..................................................................... 2-19
2N4091 N-Channel JFET Switch ................................................................................ 2-19
2N4092 JANTX N-Channel JFET Switch .......................... : .......................................... 2-19
2N4092 N-Channel JFET Switch ........................................................... '..................... 2-19
2N4093 JANTX N-Channel JFET Switch ..................................................................... 2-19
2N4093 N-Channel JFET Switch ................................................................................ 2-19
2N4100 Dielectrically Isolated Dual NPN General Purpose Amplifier ................................... 2-17
2N4117 N-Channel JFET General Purpose Amplifier ...................................................... 2-21
2N4117A N-Channel JFET General Purpose Amplifier .................................................... 2-21
2N4118 N-Channel JFET General Purpose Amplifier ...................................................... 2-21
2N4118A N-Channel JFET General Purpose Amplifier .................................................... 2-21
2N4119 N-Channel JFET General Purpose Amplifier ...................................................... 2-21
2N4119A N-Charinel JFET General Purpose Amplifier .................................................... 2-21
2N4220 N-Channel JFET General Purpose Amplifier/Switch ............................................ 2-22
2N4221 N-Channel JFET General Purpose Amplifier/Switch ............................................ 2-22

12

Alphanumeric Index

(Continued)

2N4222 N-Channel JFET General Purpose Amplifier/Switch ............................................ 2-22
2N4223 N-Channel JFET High Frequency Amplifier ....................................................... 2-23
2N4224 N-Channel JFET High Frequency Amplifier .................................................... : .. 2-23
2N4338 N-Channel JFET Low Noise Amplifier .............................................................. 2-24
2N4339 N-Channel JFET Low Noise Amplifier .............................................................. 2-24
2N4340 N-Channel JFET Low Noise Amplifier .............................................................. 2-24
2N4341 N-Channel JFET Low Noise Amplifier .............................................................. 2-24
2N4351 N-Channel Enhancement Mode MOSFET General Purpose Amplifier/Switch ............. 2-25
2N4391 N-Channel JFET Switch ................................................................................ 2-26
2N4392 N-Channel JFET Switch ................................................................................ 2-26
2N4393 N-Channel JFET Switch ................................................................. , .............. 2-26
2N4416/A N-Channel JFET High Frequency Amplifier .................................................... 2-28
2N4856 N-Channel JFET Switch ................................................................................ 2-30
2N4856JAN,JTX,JTXV N-Channel JFET Switch ............................................................. 2-30
2N4857 N-Channel JFET Switch ................................................................................ 2-30
2N4857 JAN,JTX,JTXV N-Channel JFET Switch ............................................................. 2-30
2N4858 N-Channel JFET Switch ................................................................................ 2-30
2N4858JAN,JTX,JTXV N-Channel JFET Switch ............................................................. 2-30
2N4859 N-Channel JFET Switch ................................................................................ 2-30
2N4860 N-Channel JFET Switch ................................................................................ 2-30
2N4861 N-Channel JFET Switch ................................................................................ 2-30
2N4867/ A N-Channel JFET Low Noise Amplifier ........................................................... 2-32
2N4868/ A N-Channel JFET Low Noise Amplifier ........................................................... 2-32
2N4869/ A N-Channel JFET Low Noise Amplifier ........................................................... 2-32
2N4878 Dielectrically Isolated Dual NPN General Purpose Amplifier ......................... ; ......... 2-17
2N4879 Dielectrically Isolated Dual NPN General Purpose Amplifier ................................... 2-17
2N4880 Dielectrically Isolated Dual NPN General Purpose Amplifier ................................... 2-17
2N5018 P-Channel JFET Switch ................................................................................ 2-34
2N5019 P-Channel JFET Switch ................................................................................ 2-34
2N5114 P-Channel JFET Switch ...................................................................... :·, ........ 2-36
2N5114JAN,JTX,JTXV P-Channel JFET Switch ........................ ; ..................................... 2-36
2N5115 P-Channel JFET Switch ................................................................................ 2-36
2N5115JAN,JTX,JTXV P-Channel JFET Switch .............................................................. 2-36
2N5116 P-Channel JFET Switch ................................................................................ 2-36
2N5116JAN,JTX,JTXV P-Channel JFET Switch .............................................................. 2-36
2N5117 Dielectrically Isolated Dual PNP General Purpose Amplifier ................................... 2-38
2N5118 Dielectrically Isolated Dual PNP General Purpose Amplifier ................................... 2-38
2N5119 Dielectrically Isolated Dual PNP General Purpose Amplifier ................................... 2-38
2N5196 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-40
2N5197 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-40
2N5198 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-40
2N5199 Dual N-Channel JFET General Purpose Amplifier ........................................... : ... 2-40
2N5397 N-Channel JFET High Frequency Amplifier ....................................................... 2-42
2N5398 N-Channel JFET High Frequency Amplifier ....................................................... 2-42
2N5432 N-Channel JFET Switch ................................................................................ 2 -44
2N5433 N-Channel JFET Switch ................................................................................ 2 -44
2N5434 N-Channel JFET Switch ................................................................................ 2-44
2N5452 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-46
2N5453 Dual N-Channel JFET General Purpose Amplifier .............. : ................................ 2-46
2N5454 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-46
2N5457 N-Channel JFET General Purpose Amplifier/Switch ............................................ 2-48
2N5458 N-Channel JFET General Purpose Amplifier/Switch ............................................ 2-48
2N5459 N-Channel JFET General Purpose Amplifier/Switch ............................................ 2-48
2N5460 P-Channel JFET Low Noise Amplifier .............................................................. 2-49

13

Alphanumeric Index

(Continued) -

2N5461 P-Channel JFETLow Noise Amplifier ...................•. ; ................... :., .•...•............ 2 ...,49
2N5462 P-Channel JFET Low Noise Amplifier ....... ~.~, .," .•............................................... 2-:49
2N5463 P-Channel JFET Low Noise Amplifier ........................... : .................................. 2 ...049
2N5464 P-ChanneIJFET Low Noise Amplifier ............... : .............................................. 2;,..49
2N5465 P-Channel JFET Low Noise Amplifier ............... : ............ : ................................. 2-49
.2N5484 N-Channel JFET High Frequency Amplifier ..... : .............. '.........................,........... 2-50
2N5485 N,..channel JFET High Frequency Amplifier ..... ; ... ~ ........... ,.: ................. , ............. 2:..,50
2N5486 N-Channel JFET High Frequency Amplifier ... '..............•........................ : ............. 2-.50
2N5515 Dual N-Channel JFET Low Noise Amplifier ........................................-............... 2-,52
2N5516 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-52
2N5517 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-52
2N5518 Dual N-Channel JFET Low Noise Amplifier .... ~ ........................... : ... : .................. 2-52
2N5519 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-52
2N5520 Dual N-Channel JFET Low Noise Amplifier ........................................................ 2 .... 52
2N5521 Dual N-Channel JFET Low Noise Amplifier ........................................................ 2-52
2N5522 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-52
2N5523 Dual N-Channel JFET Low Noise Amplifier ........................................................ 2-52
2N5524 Dual N-Channel JFET Low Noise Amplifier ................................................... : ... 2-52
2N5638 N-Channel JFET Switch ................................................................................ 2-54
2N5639 N-Channel JFET Switch ....,............................................................................ 2..,.54
2N5640 N-Channel JFET Switch ............. : .....................................................••........... 2-54
2N5902 Dual N-Channel JFET General Purpose Amplifier .. , ....... : .................................... 2-56
. 2N5903 Dual N-Channel JFET G~neral Purpose Amplifier. .............................................. 2-56
2N5904 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-56
2N5905 Dual N-Channel JFET General Purpose Amplifier .. , ............................................ 2-56
2N5906 Dual N-Channel JFET General Purpose Amplifier ......... , ..................................... 2-56
2N5907 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-56
2N5908 Dual N-Channel JFET General Purpose Arnplifier .................. : ............................ 2-56
2N5909 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-56
2N5911 Dual N-Channel JFET High Frequency Amplifier .................. : .............................. 2-58
2N5912 Dual. N-Channel JFET High Frequency Amplifier ........................... : ..................... 2-58
2N6483 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-60
2N6484 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-60
2N6485 Dual N-Channel JFET Low ,N9ise Amplifier ....................................................... 2-60
3N161 Diode Protected P-ChannelEnhancement Mode MOSFET General Purpose Amplifierl
.
Switch ..................................... ::.....•....•....•..,........................................................... 2-64
3N163 P-Channel Enhancement Mode MOSFET General Purpose AmplifierlSwitch .............. 2-65
3N164 P-Channel Enhancement Mode MOSFET General Purpose/Switch ........................... 2,..65
3N165 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifie~ ................. 2-.67
3N166 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier ................. 2-67
3N170 N-Channel Enhancement Mode MOSFET Switch ................. : ......... , ..................... 2-69
3N171 N-Channel Enhancement Mode MOSFET Switch .................................................. 2-69
3N172 Diode Protected P-Channel Enhancement Mode MOSFET General Purpose Amplifierl
Switch ..................................• : ......................................................_.................... 2-71
3N173 Diode Protected P-Channel ~nhancement Mode MOSFET General Purpose Amplifierl
Switch .......................................................................... : ................................... 2-71
3N188 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier .................. 2,.. 72
3N189 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier ................. 2-72
3N190 Dual P-Channel Enhancement Mbde MOSFET General Purpose Amplifier ................. 2-72
3N1.91 Dual P-Channel Enhancemel1tMo.d.EI: MPSFET General Purpose Amplifier ................. 2-72
AD590 2-:Wire Current Output Temperature TransdUcer .................... : ............................... 5-1
AD7520 10/12-8it Multiplying D/A·Cqhyerter .....• : .......... : .............. ~ ................................ 6-1
AD7521 10/12-8it Multiplying D/A C6nverter: ................................................................ 6-1
AD7523 8-8it Multiplying 01 A Converter ............................................,........................... 6-7

14

Alphanumeric Index

(Continued)

AD7530 10/12-Bit Multiplying DI A Converter .. , .............................................................. 6-1
AD7531 10/12-Bit Multiplying DI A Converter .......................................................... : ...... 6-1
AD7533 10-Bit Multiplying DI A Converter .................................................................... 6-11
AD7541 12-Bit Multiplying DI A Converter .................................................................... 6-16
ADC0802 8-Bit /lP-Compatible AID Converter ............................................................... 6-22
ADC0803 8-Bit /lP-Compatible AID Converter ............................................................... 6-22
ADC0804 8-Bit /lP-Compatible AID Converter ............................................................... 6-22
D123 SPST 6-Channel JFET Switch Driver ................................................................... 3-1
D125 SPST 6-Channel JFET Switch Driver ................................................................... 3-1
D129 4-Channel Decoded JFET Switch Driver ............................................................... 3-6
DG118 SPST 4-Channel Driver With Switch .................................................................. 3-8
DG123 SPST 5-Channel Driver With Switch .................................................................. 3-8
DG125 SPST 5-Channel Driver With Switch .................................................................. 3-8
DG126 Dual DPST 80 Ohm JFET Analog Switch .......................................................... 3-12
DG129 Dual DPST 30 Ohm JFET Analog Switch .......................................................... 3-12
DG133 Dual SPST 30/35 Ohm JFET Analog Switch ...................................................... 3-12
DG134 Dual SPST 80 Ohm JFET Analog Switch .......................................................... 3-12
DG139 DPDT 30 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG140 Dual DPST 10/15 Ohm JFET Analog Switch ...................................................... 3-12
DG141 Dual SPST 10 Ohm JFET Analog Switch ........................ ; ................................. 3-12
DG142 DPDT 80 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG143 SPDT 80 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG144 SPDT 30 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG145 DPDT 10 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG146 SPDT 10 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG151 Dual SPST 15 Ohm JFET Analog Switch .......................................................... 3-12
DG152 Dual SPST 50 Ohm JFET Analog Switch .......................................................... 3-12
DG153 Dual DPST 15 Ohm JFET Analog Switch .......................................................... 3-12
DG154 Dual DPST 50 Ohm JFET Analog Switch .......................................................... 3-12
DG161 SPDT 15 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG162 SPDT 50 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG163 DPDT 15 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG164 DPDT 50 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG180 Dual SPST 10 Ohm High-Speed Driver With JFET Switch ..................................... 3-22
DG181 Dual SPST 30 Ohm High-Speed Driver With JFET Switch ..................................... 3-22
DG182 Dual SPST 75 Ohm High-Speed Driver With JFET Switch ..................................... 3....,22
DG183 Dual DPST 10 Ohm High-Speed Driver With JFET Switch ..................................... 3,...22
DG184 Dual DPST 30 Ohm High-Speed Driver With JFET Switch ..................................... 3-22
DG185 Dual DPST 75 Ohm High-Speed Driver With JFET Switch ..................................... 3-22
DG186 SPDT 10 Ohm High-Spee~ Driver With JFET Switch ............................................ 3-:22
DG187 SPDT 30 Ohm High-Speed Driver With JFET Switch ............................................ 3-22
DG188 SPDT 75 Ohm High-Speed Driver With JFET Switch ................................ ; ........... 3-22
DG189 Dual SPDT 10 Ohm High-Speed Driver With JFET Switch ....... ; ............................. 3-22
DG190 Dual SPDT 30 Ohm High-Speed Driver With JFET Switch ..................................... 3-22
DG191 Dual SPDT 75 Ohm High-Speed Driver With JFET Switch ..................................... 3-22
DG200 Dual SPST CMOS Analog Switch ..................................................................... 3-27
DG201 Quad SPST CMOS Analog Switch .................................................................... 3-32
DG211 SPST 4-Channel Analog Switch ....................................................................... 3-36
DG212 SPST 4-Channel Analog Switch ....................................................................... 3-36
DGM181 Dual SPST 50 Ohm High-Speed CMOS Analog Switch ...................................... 3-39
DGM182 Dual SPST 50175 Ohm High-Speed CMOS Analog Switch .................................. 3-39
DGM184 Dual DPST 50 Ohm High-Speed CMOS Analog Switch ...................................... 3-39
DGM185 Dual DPST 50175 Ohm High-Speed CMOS Analog Switch .................................. 3-39
DGM187 SPDT 50 Ohm High-Speed CMOS Analog Switch ............................................. 3-39

15

Alphanumeric Ind.x

(Continued)

OGM188 SPOT 50/75 Ohm High-Speed CMOS AnalogSwitch ........ i ....... , ..........•........... ; .. 3-"'39
DGM190 Dual SPOT 50 Ohm High-Speed .CMOS Analog Switch .......... ,; .......................... 3-'39
DGM191 Dual SPOT 50/75 Ohm High-Speed CMOS Analog Switch ......... ;." ...................... 3..;39
G115 6-Channel MOSFET Switch ........................................... ; ..... : ..:.•.... ; .................... :.3-45
G.116 5 Channel,MOSFET Switch .................................... :· ........... '...... ; ....................... 3-48
G118 6 Channel MOSFET Switch ............................................................................... 3-48
G119 6 Channel. MOSFET. Switch ........................... ; ...'............................., ................... 3-48
G123 4-Channel MOSFET. Switch ..................................................................... , ........ 3-45
lCH85001 A Ultra Low Input-Bias Operational Amplifier .... ; ............. : .............'..................... 4-1
ICH8510 Power Operational Amplifier ............................................................................ 4-7
ICH8515 Power Operational Amplifier ................................... ; ........................... , ......... , 4~ 16
ICH8520 Power Operational Amplifier ............................ ; .......................... , .. : .... , ...... , .... 4-'7
ICH8530 .Power Operational Amplifier ........................................................................... 4-7
ICL76XXSeries Low Power CMOS Operational Amplifiers .............................................. .4-34
ICL7104/1CL8052 12/14/16-Bit j.LP-Compatible 2-Chip AID Converter .... .'........................ 6-157
ICL7104/1CL8068 12/14/16-Bit /o1P-Compatible 2-Chip AID Converter ............................. 6-157
IGL7106 .3 }'2-Digit .LCD Single-Chip AID Converter ....................................................... 6-37
ICL7107 3 }'2-Digit LED Single-Chip AID Converter ....................................................... 6-37
ICL7109 12-Bit /o1P-Compatible AID Converter .............................................................. 6-48
ICL7115 14-Bit High..cSpeed CMOS /o1P-Compatible AID Converter .................................... 6-66
ICL71163 }'2-Digit with Display Hold Single-Chip AID Converter ........................................ 6-78
ICL7117. 3}'2-Digit with Display Hold Single-Chip AID Converter ...................................... 6-78
ICL7126 3 Y.2-Digit Low-Power Single-Chip AID Converter ............................................... 6-88
ICL7129 4 Y2 Digit LCD Single-Chip AID. Converter ....................................................... 6-98
ICL7134 14-Bit Multiplying /o1P-Compatible D/A Converter .............................................. 6-109
ICL7135 4 }'2-Digit BCD Output AID Converter ........................................................... 6-121
ICL7136 3 }'2-Digit LCD Low Power AID Converter .................... : ......................... '........ 6-132
ICL71373 }'2-Digit LED Low Power Singl9-'-Chip AID Converter ...................................... 6-142
ICL7605 Commutating Auto-Zero (CAZ) Instrumentation Amplifier ................. : .. : ................ .4-23
ICL7606 CommutatingAuto-Zero (CAD) Instrumenta:tion Amplifier .': .... ; .............................. .4-23
ICL7650 Chopper..cStabilized Operational Amplifier ............. ; ........................................... .4-50
ICL7652 Chopper..cStabilized Low-Noise Opera:tiona:IAmplifier .......................................... .4-57
ICL7660 CMOS Voltage Converter ................•..... ; ....................................................... 5-12
ICL7662 CMOS Voltage Converter ....•......................................................................... 5-20
ICL7663 CMOS Programmable Micropower Positive Voltage Regulator ..................... , ........... 5-27
ICL7664 CMOS Programmable MicrOpower Negative Voltage Regulator ......... : ..... ; .............. 5-27
ICL7665 Micropower Under/Over Voltage Detector .......................................................... 5-39
ICL7667 Dual Power MOSFET .Driver ............................................................................5-47
ICL7673 Automatic Battery Back-up Switch .................................................................... 5-55
ICL8007 JFET Input Operational Amplifier! .................... ; .... :.\ ........................... , ............ 4-65
ICL8013 Four Quadrant Analog Multiplier ..................................................................... 5-63
ICL8018A 4-Bit Expandable Current Switch ........ : .......................................... , ............ 6-151
ICL8019A 4-Bit Expandable Current Switch ................................................................ 6-151
ICL8020A 4-Bit Expandable Current Switch ...... '.; ........ : ........................... ; .... ; .............. 6-151
ICL8021 Low Power Bipolar Operational Amplifier ... , .................. " .................................. 4-69
ICL8022 Dual Low Power Bipolar Operational Amplifier ................................................... .4-69
ICL8023 Triple Low Power Bipolar Operational Amplifier ................ , ........... , .................... .4-69
ICL8038 Precision Waveform GeneratorlVoltage Controlled Osc;iIIat9r ........................•........ 5-72
ICL8043 Dual JFET Input Operational Amplifier ................................ ; ............................. 4-74
ICL8048 Logarithmic Amplifier ............................... ~ ....................... ; ............................ .4:-82
ICL8049 Antilog Amplifier ........................................................................................ .4-82
ICL8063 Power Transistor Driver I Amplifier ............ ",'" ................ ~ .... ,; .... "...................... .4-90
ICL8069 Low Voltage Reference ............•• ; ...... ;......•.................... :; .. ; ............................. 5-81
.ICL8211 Programmable Voltage Detector ..................................................................... 5-,83

16

Alphanumeric Index

(Continued)

ICL8212 Programmable Voltage Detector ..................................................................... 5-83
ICM7170 I.LP-Compatible Real-Time Clock ..................................................................... 9-1
ICM7206 CMOS Touch-Tone Encoder .......................................................................... 7-1
ICM7207 / A CMOS Timebase Generator ....................................................................... 7 -10
ICM7208 7-Digit LED Display Counter ......................................................................... 7 -15
ICM7209 Timebase Generator ................................................................................... 7 -22
ICM7211 4-Digit LCD/LED Display Driver ..................................................................... 8-1
ICM7212 4-Digit LCD/LED Display Driver ..................................................................... 8-1
ICM7213 One Second/One Minute Timebase Generator ................................................. 7 -25
ICM7215 6-Digit LED Display 4-Function Stopwatch ...................................................... 7 -30
ICM7216A 8-Digit Multi-Function Frequency Counter/Timer .............................................. 7-36
ICM7216B 8-Digit Multi-Function Frequency Counter/Timer •............................................. 7 -36
ICM7216C 8-Digit Multi-Function Frequency Counter/Timer .............................................. 7 -36
ICM7216D 8-Digit Multi-Function Frequency Counter/Timer ............................................. 7-36
ICM7217 4-Digit LED Display Programmable Up/Down Counter ........................................ 7 -52
ICM7218 8-Digit LED Multiplexed Display Driver ............................................................ 8-1 0
ICM7224 4 1'2-Digit LCD/LED Display Counter .............................................................. 7 -67
ICM7225 4 1'2-Digit LCD/LED Display Counter .~ ............................................................. 7 -67
ICM7226A1B 8-Digit Multi-Function Frequency Counter/Timer .......................................... 7 -75
ICM7227 4-Digit LED Display Programmable Up/Down Counter ........................................ 7 -52
ICM7231 Numeric Triplexeq LCD Display Driver ............................................................ 8-20
ICM7232 Numeric Triplexed LCD Display Driver ............................................................ 8-20
ICM7233 Alphanumeric Triplexed LCD Display Driver ...................................................... 8-20
ICM7234 Alphanumeric Triplexed LCD Display Driver .........•.............................. ; ............• 8-20
ICM7235 4-Digit Vacuum Fluorescent Display Driver ...................................................... 8-40
ICM7236 4 1'2-DigitCounterlVacuum Fluorescent Display Driver. ....................................... 7-88
ICM7240 Programmable Timer ................................................................................... 7 -93
ICM7241 Timebase Generator ................................................................................. 7 -103
ICM7242 Long-Range Fixed Timer ........................................................................... 7 -105
ICM7243 8-Character LED I.LP-Compatible Display Driver ................................................ 8-45
ICM7245 Stepper Motor Quartz Clock ... ; ................................................ ~ ........... , ...... 7 -111
ICM7249 5-1'2 Digit LCD I.L-Power Event/Hour Meter .................................................... 7-115
ICM7250 Programmable Timer ................................................................................... 7 -93
ICM7260 Programmable Timer ................................................................................... 7-93
ICM7280 Dot Matrix LCD Controller/Row Driver ............................................................ 8-54
ICM7281 40-Column LCD Dot Matrix Display Driver ....................................................... 8-69
ICM7283 LCD Dot Matrix Controller/Row Driver ............................................................ 8-79
ICM7555 General Purpose Timer ..............................•............................................... 7 -123
ICM7556 Dual General Purpose Timer ....................................................................... 7 -123
10100 Dual Low Leakage Diode ................................................................................ 2-74
10101 Dual Low Leakage Diode ................................................................................ 2-74
IH311 High Speed SPST 4-Channel Analog Switch ....................................................... 3-52
IH312 High Speed SPST 4-Channel Analog Switch ....................................................... 3-52
IH401 QUAD Varafet Analog Switch ........................................................................... 3-59
IH401A QUAD Varafet Analog Switch ......................................................................... 3-59
IH5009 Quad 100 Ohm Virtual Ground Analog Switch .................................................... 3-65
IH5010 Quad 150 Ohm Virtual Ground Analog Switch .................................................... 3-65
IH5011 Quad 100 Ohm Virtual Ground Analog Switch .................................................... 3-65
IH5012 Quad 150 Ohm Virtual Ground Analog Switch .................................................... 3-65
IH5013 Triple 100 Ohm Virtual Ground Analog Switch .................................................... 3-65
IH5014 Triple 150 Ohm Virtual Ground Analog Switch .................................................... 3-65
IH5015 Triple 100 Ohm Virtual Groung Analog Switch ........... ; ........................................ 3-65
IH5016 Triple 150 Ohm Virtual Ground Analog Switch .................................................... 3-65
IH5017 Dual 100 Ohm Virtual Ground Analog Switch ..................................................... 3-65

17

Alphanumeric Index
IH5018
IH5019
IH5020
IH5021
IH5022
IH5023
IH5024
IH5025
IH5026
IH5027
IH5028
IH5029
IH5030
IH5031
IH5032
IH5033
IH5034
IH5035
IH5036
IH5037
IH5038
IH5040
IH5041
IH5042
IH5043
IH5044
IH5045
IH5046
IH5047
IH5048
IH5049
IH5050
IH5051
IH5052
IH5053
IH5108
IH5110
.IH5111
IH5112
IH5113
IH5114
IH5115
IH5116
IH5140
IH5141
IH5142
IH5143
IH5144
IH5145
IH5148
IH5149
IH5150
IH5151
IH5200

(Continued)

Dual 150 Ohm Virtual Ground Analog Switch ....... : .................. ; .................. ; ...... ,30-65
f"'ual 100 Ohm Virtual Ground Analog Switch ..................................................... 3-65
Dual 150 Ohm Virtual Ground Analog Switch ................ : ......................•............. 3-65
Single 100 Ohm Virtual Ground Analog Switch , ............. ; .................................... 3-65
Single 150 Ohm Virtual Ground Analog Switch ................. ; ................................. 3-65
Single 100 Ohm Virtual Ground Analog Switch .................................. ; .... , .......... ;.3-65
Single 150 Ohm Virtual Ground Analog Switch ................................................... 3-65
Quad 100 Ohm Positive Signal Analog Switch .........................................,............ 3-71
Quad 150 Ohm Positive Signal Analog Switch ..................................................... 3-71
Quad 100 Ohm Positive Signal Analog Switch .................................................... 3-71
Quad 150 Ohm Positive Signal Analog Switch ..................................................... 3-71
Triple 100 Ohm Positive Signal Analog Switch ............ ; ....................................... 3-71
Triple 150 Ohm Positive Signal Analog Switch .................................................... 3-71
Triple 100 Ohm Positive Signal Analog .Switch .................................................... 3-71
Triple 150 Ohm Positive Signal Analog Switch .................................................... 3- 71
Dual 100 Ohm Positive Signal Analog Switch ........... : ......................................... 3-71
Dual 150 Ohm Positive Signal Analog Switch ..................................................... 3-71
Dual 100 Ohm Positive Signal Analog Switch ..................................................... 3-71
Dual 150 Ohm Positive Signal Analog Switch ..................................................... 3-71
Single 100 Ohm Positive Signal Analog Switch ................................................... 3-71
Single 150 Ohm Positive Signal Analog Switch ................................................... 3-71
SPST 75 Ohm High-Level CMOS Analog Switch ................................................. 3-79
Dual SPST 75 Ohm High-Level CMOS Analog Switch .......................................... 3-79
SPOT 75 Ohm High-Level CMOS Analog Switch ................................................. 3-79
Dual SPOT 75 Ohm High-Level CMOS Analog Switch .......................................... 3-79
DPST 75 Ohm High-Level CMOS Analog Switch ................................................. 3-79
Dual DPST 75 Ohm High-Level CMOS Analog Switch .......................................... 3-79
DPDT 75 Ohm High-Level CMOS Analog Switch ............................................ , .... 3-79
4PST 75 Ohm High-Level CMOS Analog Switch ...............•................................. 3-79
Dual SPST 35 Ohm High-Level CMOS Analog SWitch .......................................... 3-88
Dual DPST 35 Ohm High-Level CMOS Analog Switch .......................................... 3-88
SPOT 35 Ohm High-Level CMOS Analog Switch ................................................. 3-88
Dual SPOT 35 Ohm High-Level CMOS Analog Switch .......................................... 3-88
QUAD CMOS Analog Switch ........................................................................... 3 .... 93
QUAD CMOS Analog Switch ........................................................................... 3-93
8-Channel Fault Protected Analog Multiplexer ..................................................... 3-99
General Purpose Sample & Hold ..................................................................... 5-94
General Purpose Sample & Hold ..................................................................... 5-94
General Purpose Sample & Hold ..................................................................... 5-94
General Purpose Sample & Hold .................................. ; .................................. 5-94
General Purpose Sample & Hold ..................................................................... 5-94
General Purpose Sample & Hold ..................................................................... 5-94
16-Channel Fault Protected Analog Multiplexer ........... "..................................... 3-107
SPST High-Level CMOS Analog Switch ........................................................... 3-110
Dual SPST High-Level CMOS Analog Switch .................................................... 3-110
SPOT High-Level CMOS Analog Switch ........................................................... 3'-110
Dual SPOT High-Level CMOS Analog Switch .................................................... 3-110
DPST High-Level CMOS Analog Switch ........................................................... 3-110
Dual ,DPST High-Level CMOS Analog Switch .................................................... 3-110
Dual SPST High-Level CMOS Analog Switch .................................................... 3-119
Dual DPST High-Level CMOS Analog Switch .................................................... 3-119
SPOT High-Level CMOS Analog Switch ... ; ............ : .......................................... 3-119
Dual SPOT High-Level CMOS Analog Switch .................................................... 3-119
Dual SPST CMOS Analog Switch ................. ,' .................................................. 3-27

18

Alphanumeric Index

(Continued)

IH5201 Quad SPST CMOS Analog Switch ................................................................... 3-32
IH5208 4-Channel Differential Fault Protected Analog Multiplexer .................................... 3-127
IH5216 8-Channel Differential Fault Protected Analog Multiplexer .................................... 3-135
IH5341 Dual SPST CMOS RFlVideo Switch ............................................................... 3-138
IH5352 QUAD SPST CMOS RFlVideo Switch ............................................................. 3-144
IH6108 8-Channel CMOS Analog Multiplexer .............................................................. 3-149
IH6116 16-Channel CMOS Analog Multiplexer ............................................................ 3-155
IH6201 Dual CMOS DriverlVoltage Translator ............................................................. 3-162
IH6208 4-Channel Differential CMOS Analog Multiplexer ............................................... 3-166
IH6216 8-Channel Differential CMOS Analog Multiplexer ............................................... 3-172
IM80C35 8-8it CMOS Microcontroller .......................................................................... 9-33
IM80C39 8-8it CMOS Microcontroller .......................................................................... 9-33
IM80C48 8-8it CMOS Microcontroller .......................................................................... 9-33
IM80C49 8-8it CMOS Microcontroller .......................................................................... 9-33
IM82C43 CMOS I/O Expander .................................................................................. 9-45
IM4702/4712 8aud Rate Generator ............................................................................. 9-9
IM6402 Universal Asynchronous Receiver Transmitter (UART) .......................................... 9-16
IM6403 Universal Asynchronous Receiver Transmitter (UART) .......................................... 9-16
IM6653 4096-8it CMOS UV EPROM .......................................................................... 9-25
IM6654 4096-8it CMOS UV EPROM .......................................................................... 9-25
IMF6485 Dual N-Channel JFET Low Noise Amplifier ...................................................... 2-62
IT100 P-Channel JFET Switch ................................................................................... 2-76
In01 P-Channel JFET Switch ................................................................................... 2-76
IT120 Dual NPN General Purpose Amplifier .................................................................. 2-77
IT120A Dual NPN General Purpose Amplifier ................................................................ 2 - 77
IT121 Dual NPN General Purpose Amplifier .................................................................. 2-77
IT122 Dual NPN General Purpose Amplifier .................................................................. 2-77
IT124 Dual Super.,..8eta NPN General Purpose Amplifier .................................................. 2-79
IT126 Dual NPN General Purpose Amplifier .................................................................. 2-81
IT127 Dual NPN General Purpose Amplifier .................................................................. 2-81
IT128 Dual NPN General Purpose Amplifier. ................................................................. 2-81
IT129 Dual NPN General Purpose Amplifier .................................................................. 2..,81
IT130 Dual PNP General Purpose Amplifier ......., .......................................................... 2-83
IT130A Dual PNP General Purpose Amplifier ................................................................ 2-83
.IT131 Dual PNP General Purpose Amplifier .................................................................. 2-83
IT132 Dual PNP General Purpose Amplifier ... ; .............................................................. 2-83
IT136 Dual PNP General Purpose Amplifier .................................................................. 2-85
IT137 Dual PNP General Purpose Amplifier .................................................................. 2-85
IT138 Dual PNP General Purpose Amplifier ............................................................ , ..... 2-85
IT139 Dual PNP General Purpose Amplifier .................................................................. 2-85
IT500 Dual Cascoded N-Channel JFET General Purpose Amplifier .................................... 2-87
IT501 Dual Cascoded N-Channel JFET General Purpose Amplifier .................................... 2-87
IT502 Dual Cascoded N-Channel JFET ~eneral Purpose Amplifier .................................... 2-87
IT503 Dual Cascoded N-Channel JFET General Purpose Amplifier .................................... 2-87
IT504 Dual Cascoded N-Channel JFET General Purpose Amplifier ....... : ............................ 2-87
IT505 Dual Cascoded N-Channel JFET General Purpose Amplifier .................................... 2-87
IT550 Dual N-Channel JFET Switch ........................................................................... 2-90
IT1700 P-Channel Enhancement Mode MOSFET General Purpose Amplifier ........................ 2-92
IT1750 N-Channel Enhancement Mode MOSFET General Purpose Amplifier/Switch .............. 2-93
IT5911 Dual N-Channel JFET High Frequency Amplifier .................................................. 2-58
IT5912 Dual N-Channel JFET High Frequency Amplifier .................................................. 2-58
ITE4091 N-Channel JFET Switch ............................................................................... 2..,.19
ITE4092 N-Channel JFET Switch ............................................................................... 2-19
ITE4093 N-Channel JFET Switch ............................................................................... 2-19

19

Alphanumeric Index

(Continued)

ITE4391 N-Channel JFET Switch .................................... ; ... :; ..... : ................ : ............. 2....:26
ITE4392 N-Channel JFET Switch ............. : .. ;;' ............. : . .'. .' .......•.... , ..... : ....................... 2-26
ITE4393 N-Channel JFET Switch .............................................................................. 2-26
ITE4416 N-Channel JFET High Frequency Amplifier ............................ ~, ......................... 2-28
J105 N-Channel JFET Switch .................................... : ................... : ......... ,................. 2-94
J106 N-Channel JFET Switch ................................................................................... 2-94
J107 N-Channel JFET Switch ............................................................ : ...................... 2-94
J 111 'N-Channel JFET Switch ................................................................................... 2 - 95
J112 N-Channel JFET Switch ................................................................... : ............... 2-95
J113 N-Channel JFET Switch .................................................................................. :2-95
J174 P-Channel JFET Switch ................................................................................ ; ... 2-97
J175 P-Channel JFET Switch ................................................................................... :2-97
J176 P-Channel JFET Switch .........................................................·............................ 2-97
J177 P-Channel JFET Switch .................................................................................... 2-97
J201 N-Channel JFET General Purpose Amplifier ...................................... , ................... 2-99
J202 N-Channel JFET General Purpose Amplifier .......................................................... 2-99
J203 N-Channel JFET General Purpose Amplifier ........................................................... 2-99
J204 N-Channel JFET General Purpose Amplifier .......................................................... 2-99
J308 N-Channel JFET High Frequency Amplifier ......................................................... 2-100
J309 N-Channel JFET High Frequency Amplifier ....................................... ; ................. 2-100
J310 N-Channel JFET High Frequency Amplifier ........ ! ................................................ 2-100
LH2108 Dual Super-Beta Operational Amplifier ................................. ; ........................... 4-99
LH2308 Dual Super-Beta Operational Amplifier ............................................................. 4-99
LM1 081 A Super-Beta Operational Amplifier ................................................................ 4-102
LM114/H Dual NPN General Purpose Amplifier ........................................................... 2-102
LM 114A1 AH Dual NPN General Purpose Amplifier ............... ; ................ : ...................... 2 -102
LM308/A Super-Beta Operational Amplifier ................................................................ 4-102
M116 Diode Protected N-Channel Enhancement Mode MOSFET General Purpose Amplifier. 2-104
MM450 Dual Differential High Voltage Analog Switch ................................................... 3-178
MM451 Four Channel High Voltage Multiplexer ........................................................... 3-178
MM452 Quad SPST High Voltage Analog Switch ......................................................... 3-178
MM455 Three SPST High Voltage Analog Switch ....................... ~ ................................. 3-178
MM550 Dual Differential High Voltage Analog Switch ................................................... 3-178
MM551 Four Channel High Voltage Multiplexer ...................... ; ........... : ........................ 3-178
MM552 Quad SPST High Voltage Analog Switch ......................................................... 3 -178
MM555 Three SPST High Voltage Analog Switch ........................................................ 3-178
NE/SE592 Video Amplifier ................................................................................. , .... 4-106
U200 N-Channel JFET Switch ..................................................................... : ........... 2-105
U201 N-Channel JFET Switch ..........................................'....................................... 2-105
U202 N-Channel JFET Switch ................................................................................. 2-105
U23.1 Dual N-Channel JFET General Purpose Amplifier ................................................ 2-106
U232 Dual N-Channel JFET General Purpose Amplifier ................................................ 2-106
U233 Dual N-Channel JFET General Purpose Amplifier ................................................ 2-106
U234 Dual N-Channel JFET General Purpose Amplifier ................................................ 2-106
U235 Dual N-Channel JFET General Purpose Amplifier ........... : .................................... 2-106
U257 Dual N-Channel JFET High Frequency Amplifier .................................................. 2-108
U304 P-Channel JFET Switch ................................................................................. 2-109
U305 P-Channel JFET Switch .......................................................... ; ....... ~ .............. 2-109
U306 P-Channel JFET Switch ............................................................................ : .... 2-109
U308 N-Channel JFET High Frequency Amplifier ......................................................... 2-111
U309 N-Channel JFET High Frequency Amplifier ......................................................... 2-111
U310 N-Channel JFET High Frequency Amplifier ......................................................... 2-111
U401 Dual N-Channel JFET Switch .......................................................................... 2-113
U402 Dual N-Channel JFET Switch ........................................................................... 2-113

20

Alphanumeric Index

(Continued)

U4o.3 Dual N-Channel JFET Switch .......................................................................... 2-113
U404 Dual N-Channel JFET Switch .......................................................... ; ................ 2-113
U4o.5 Dual N-Channel JFET Switch .......................................................................... 2-113
U4o.6 Dual N-Channel JFET Switch ...................................... ; ................................... 2-113
U1897 N-Channel JFET Switch ............................................................................... 2-115
. U1898 N-Channel JFET Switch ........................................................................ ~ ...... 2-115
U1899 N-Channel JFET Switch ............................................................................... 2-115
VCR2N Voltage Controlled Resistors ......................................................................... 2-117
VCR3P Voltage Controlled Resistors ......................................................................... 2-117
VCR4N Voltage Controlled Resistors ......................................................................... 2-117
VCR7N Voltage Controlled Resistors ......................................................................... 2-117
VCR 11 N Voltage Controlled Resistors ....................................................................... 2 -120.

21

IIO~OIl.

,408-996-5000
TWl<;" 91'0-338-2014

10600'Ridgeview Court, Cupertino, CA 95014

ALPHANUMERIC CROSS REFERENCE
ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

-ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

103M

2N5458
2N3684
2N5686
2N5457
2N5457

2N2606
2N2607
2N2608
2N2609
2N2609JAN

2N2607
2N2607
2N2608
2N2609
2N2609JAN

2N3331
2N3332
2N3333
2N3334
2N3335

2N5270
2N5268
1T132
1T132
ITr32

1035
104M
105M
105U
106M

2N5459
2N5458
2N5459
2N434O
2N5485

2N2639

1T120
ITI22

1Tl22
1T120
1Tl22

2N3336
2N3347
2N3348
2N3349
2N3350

1T132

2N2640

2N2641
2N2642
2N2643

107M

2N5485
2N3685
2N3686
'2N4339
2N3822

2N2644
2N2652
2N2652A
2N2720
2N2721

IT122
1Tl20
1T120
1Tl20
ITI22

2N3351
2N3352
2N3365
2N3366
2N3367

1T138
1Tl39
2N434O
2N4338
2N4338

2N3821
2N3822
2N4341

2N2722
2N2802
2N2803
2N2804
2N2805

1Tl20
\ln39
'Tl39
1Tl39
1T139

2N3368
2N3369
2N3370
2N3376
2N3378

1284A
1285A
1286A
130U

2N4340
2N4222
2N3821
2N4220
2N3687

2N2806
2N2807
2N2841
2N2842
2N2843

1T139
1Tl39
2N2607
2N2607
2N2607

1325A
135U
14T
155u
1714A

2N4222
2N4339
2N4224
2N4416
2N434O

2N2844
2N2903
2N2903A
2N2910
2N2913

1825
1835
1975
1985
1995

2N4391
2N3823
2N4338
2N434O
2N4341

2N2914
2N2915

2oo0M
2001M
2005
200U
2015

2N3823
2N3823
2N4392
2N3824
2N4391

2025
2035
2045
2078A
2079A

1005
100U
102M
1025

IIDU
120U
125U
1277A
1278A
1279A
1280A
1281A
1282A
1283A

SD:~:,=~;~'i,CT

INTERSIL
EQU,IVALENT,

2N3814
2N381,5
2N3816
2N3816A
2N3817

ITI32
1T132
1T130'
ITI30A
1T130

2N3817A
2N3819
' 2N3820
2N3821
2N3822

lT1aOA
2N5484
2N2608
2N3821
2N3822

2N3823
2N3824
2N3907
2N3908
2N3909

2N3823
2N3824
1T120
1T120
2N2609

2N4341
2N4339
2N4338
2N2608
2N2608

2N3909A
2N3921
2N3922
2N3949
2N3950

2N2609
2N3921
2N3922
1T132
1Tl32

2N3380
2N3382
2N3384
2N3386
2N3409

2N2609
2N3994
2N3993
2N5114
1Tl22

2N3954
2N3954A
2N3955
2N3955A
2N3956

2N395'
2N3954A
2N3955
2N3955A
2N3956

2N2607
ITI22
1Tl20
1T122
1Tl22

2N3410
2N3423
2N3424
2N3425

1Tl22
1Tl22
1Tl22
1T122
1T122

2N3957
2N3966
2N3967
2N3967A
2N3968

2N3957
2N4416
2N4221
2N4221
2N3685

1Tl20
1Tl20
1Tl20
1Tl20
ITI20

2N3436
2N3437
2N3438
2N3452
2N3453

2N4341
2N434O
2N4338
2N4220
2N4338

2N3968A
2N3969
2N3969A
2N3970
2N3971

2N3685
2N3686
2N3686
2N3970
2N3971

2N2917
2N2918
2N2919
2N2919A
2N2920

1Tl22
1Tl20
1T120
2N2920

2N3454
2N3455
2N3456
2N3457
2N3458

2N4338
2N4340
2N4338
2N4338
2N4341

2N3972
2N3993
2N3993A
2N3994
2N3994A

2N3972
2N3993
2N3993
2N3994
2N3994

2N4392
2N3821
2N3821
2N3955
2N3955

2N2920A
2N2936
2N2937
2N2972
2N2973

2N2920
1Tl20
1T120
1T122
1T122

2N3459
2N3460
2N3513
2N3514
2N3515

2N4339
2N4338
ITl22
1T122
1T122

2N4009
2N4010
2N4011
2N4015
2N4016

ITI32
1T132
1T132
1T139
1T137

2N3821
2N4224

2N2915A

2N2916
2N2916A

2N3411

ITI22

ITl37

1T138
1T139
1T137

I

2080A
2081A

2N3955A

2093M
2094M
2095M

2N3687
2N3686
2N3686

2N2974
2N2975
2N2976
2N2977
2N2978

1T120
1T120
ITl20
1T120
1T120

2N3516
2N3517
2N3521
2N3522
2N3574

ITi22
1T122
1T122
1T122
2N2607

2N4017
2N4018
2N4019
2N4020
2N4021

1T139
1T139
1T139
ITl39

2098A
2099A
210U
2130U
Z132U

2N3954
2N3955A
2N4416
2N5452
2N3955

2N2979
2N2980
2N2981
2N2982
2N3043

1T120
1T121
1T122
1T122
1T121

2N3575
2N3578
2N3587
2N3608
2N3680

2N2607
2N2608
1T122
3N172
1Tl20

2N4022
2N4023
2N4024
2N4025
2N4026

ITl39
1T137
ITl37 '
ITI37
3N163

2134U

2N3956

2N3955A

11139

2136U

2N3957

2138U
2139U
2147U

2N3958
2N3958
2N3958

2N3044
2N3045
2N3046
2N3047
2N3048

ITI22
1T122
1T121
1T122
1T122

2N3684
2N3684A
2N3685
2N3685A
2N3686

2N3684
2N3684
2N3685
2N3685
2N3686

2N4038
2N4039
2N4065
2N4066
2N4067

2N4351
2N4351
3N163
3N166
3N166

2148U
2149U
2315
2325
2335

2N3958
2N3958
2N3954
2N3955
2N3956

2N3049
2N3050
2N3051
2N3052
2N3059

1T139
1Tl39
1Tl39
1T129
1Tl39

2N3686A
2N3687
2N3687A
2N3726
2N3727

2N3686
2N3687
2N3687
1T131
1T130

2N4082
2N4083
2N4084
2N4085
2N4091

2N3954
2N3955
2N3954
2N3955
2N4091

2345
2355

2N3957
2N3958
2N4869
2N4091
2N4392

2N3066
2N3067
2N3068
2N3069
2N3070

2N4340
2N4338
2N4338
2N4341
2N4339

2N3728
2N3729
2N3800
2N3801
2N3802

ITI22
1T121
1T132
1T132
1T132

2N4091A

2N409IJAN,
2N409IJANTX
2N409IJANTXV
2N4092

2N4091
2N409IJAN
2N409IJANTX
2N409lJANTXV
2N4092

2N2060
2N2060A
2N20608
2N2223
2N2223A

1T120
1T121
ITl22
ITl21

2N3071
2N3084
2N3085
2N3086
2N3087

2N4338
2N4339
2N4339
2N4339
2N4339

2N3803
2N3804
2N3804A
2N3805
2N3805A

1Tl32
1T13O
1T130A
ITl30
1T130A

2N4092A
2N4092JAN
2N4092JANTX
2N4092JANTXV
2N4093

2N4092
2N4092JAN
2N4092JANTX
2N4092JANTXV
2N4093

2N2386
2N2386A
2N2453
2N2453A
2N2480

2N2608
2N2608
1Tl22
1Tl21
1T122

2N3088
2N3088A
2N3089
2N3089A
2N3113

2N4339
2N4339
2N4339
2N4339
2N2607

2N3806
2N3807
2N3808
2N3809
2N3810

ITI22

2N4093A

1T122
1T122
1Tl22
2N3810

2N4093JAN
2N4093JANTX
2N4093JANTXV
2N41oo

2N4093
2N4093JAN
2N4093JANTX
2N4093JANTXV
2N4100

2N2480A
2N2497
2N2498
2N2499
2N2500

ITl21
2N2608
2N2608
2N2609
2N2608

2N3277
2N3278
2N3328
2N3,329
2N3330

2N2606
2N2607
2N5265
2N5267
2N5268

2N3812
2N3813

2N381OA
2N3811
2N3811A
1T132
1T132

2N4117
2N4117A
2N4118
2N4118A
2N4119

2N4117
2N4117A
2N4118
2N4118A
2N4119

241U

250U
251U

1T12l

"CONSULT FACTORY

2N3810A

~~~mA

22

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRO~UCT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

2N4119A
2N4120
2N4139
2N4Z20
2N4220A

2N4119A
3N163
2N3822
2N4220
2N4220

2N5045
2N5046
2N5047
2N5078
2N5090

2N5453
2N54S4
2N5454
2N5397
1T122

2N5484
2N5485
2N5486
2N5515
2N5516

2N5484
2N548S
2N5486
2N5515
2N5516

2N6484
2N6485
2N6502
2N6503
2N6550

2N6484
2N648S
ITl22
ITl22
2N4868A

2N4221
2N4221A
2N4222
2N4222A
2N4223

2N4221
2N4221
2N4222
2N4222
2N4223

2N5103
2N5104
2N5105
2N5114
2N5114JAN

2N4416
2N4416
2N4416
2NSl14
2NSl14JAN

2N5517
2N5518
2NS519
2N5520
2N5521

2N5517
2N5518
2N5519
2N5520
2N5521

2N6568
25C294
25Jll
25J12
25J13

2N5432
1T122
2N2607
2N2607
2N5270

2N4224
2N4267
2N4268
2N4302
2N4303

2N4224
3N163
3N161
2N4302
2N5459

2N5114JANTX
2N5114JANTXV
2N5115
2N5115JAN
2N5115JANTX

2N5114JANTX
2N5114JANTXV
2N5115
2N5115JAN
2N5115JANTX

2N5522
2N5523
2N5524
2N5545
2N5546

2N5522
2N5523
2N5524
2N3954
2N3955A

25J15
25J16
25J47
25J48
25J49

2N2607
~~2607

2N4304
2N4338
2N4339
2N4340
2N4341

2N5458
2N4338
2N4339
2N4340
2N4341

2N5115JANTXV
2N5116
2N5116JAN
2N5116JANTX
2N5116JANTXV

2N5115JANTXV
2N5116
2N5116JAN
2N5116JANTX
2N5116JANTXV

2N5547
2N5549
2N5555
2N5556
2N5557

2N3955
2N4093
J310
2N3685
2N3684

25J50
25J78
25J79
25J80
25Kll

2N4342
2N4343
2N4351
2N4352
2N4353

2N5461
2N5462
2N4351
3N163
3Nl72

2NSl17
2NSllB
2N5119
2N5120
2N5121

2NS117
2N5118
2N5119
1Tl31
1T132

2N5558
2N5561
2N5562
2N5563
2N5564

2N3684
U401
U402
U404
IT550

25K12
2SK13
25K132
25K133
25K134

2N4360
2N4381
2N4382
2N4391
2N4392

2N5460
2N2609
2N5115
2N4391
2N4392

2N5!22
2NS123
2N5124
2N5125
2N5158

1Tl32
1T131
1Tl32
1Tl32
2N5434

2N5565
2N5566
2N5592
2N5593
2N5594

IT550
IT550
2N3822
2N3822
2N3822

2SK135
25KI5
2SK17
25K178
2$K179

2N4393
2N4416
2N4416A
2N4417
2N4445

2N4393
2N4416
2N4416A
2N4416
2N5432

2NS159
2N5163
2N5196
2N5197
2N5198

2N5433
2N3822
2N5196
2N5197
2N5198

2N5638
2N5639
2N5640
2N5647
2N5648

2N5638
2N5639
2N564O
2N4117A
2N4117A

25K18
25K180
2SK19
25K23
25K30

ITE4416
2N5459
2N5458

2N4446
2N4447
2N4448
2N4856
2N4856A

2N5434
2N5432
2NS434
2N4856
2N4856

2N5199
2N5245
2N5246
2N5247
2N5248

2N5199
ITE4416
2N5484
2N5486
2N5486

2N5649
2N5653
2N5654
2N5668
2N5669

2N4117A
,2N5638
2N5639
2N5484
2N5485

25K32
25K33
25K34
25K37
2SK41

2N3822
2N5397
2N3822
2N5484
2N5459

2N4856JAN
2N4856JANTX
2N4856JANTXV
2N4857
2N4857A

2N4856JAN
2N4856JANTX
2N4856JANTXV
2N4857
2N4857

2N5254
2N52S5
2N5256
2N5257
2N5258

ITI32
1Tl32
1Tl30
2N5457
2N5458

2NS670
2N5793
2N5794
2N5795
2N5796

2N5486
1T129
1Tl29
ITl39
1Tl39

2SK42
25K43
25K44
25K46
25K48

2N3822
ITE4092
ITE4416
2N5459
2N3821

2N4857JAN
2N4857 JANTX
2N4857JANTXV
2N4858
2N4858A

2N4857JAN
2N4857JANTX
2N4857 JANTXV
2N4858
2N4858

2N5259
2N5265
2N5266
2N5267
2N5268

2N5459
2N2607
2N2607
2N2608
2N2608

2N5797
2N5798
2N5799
2N5800
2N5801

2N2608
2N2608
2N2608
2N2608
2N4393

25K49
25K50
25K54
25K55
25K56

2N5484
ITE4416
2N3822
2N3822
2N5459

2N4B58JAN
2N4858JANTX
2N4858JANTXV
2N4859
2N4859A

2N485BJAN
2N4858JANTX
2N4858JANTXV
2N4859
2N4859

2N5269
2N5270
2N5277
2N5278
2N5358

2N2609
2N2609
2N4341
2N4341
2N4220

2N5802
2N5803
2N5843
2N5844
2N5902

2N4393
2N4392
1Tl30
ITl30
2N5902

2SK61
25K65
25K66
25K68
2SK72

2N5397
J201
2N3821
2N3822
2N5196

2N4859JAN
2N4859JANTX
2N4860
2N4860A
2N4860JAN

2N4856JAN
2N4856JANTX
2N4860
2N4860
2N4857JAN

2N5359
2N5360
2N5361
2N5362
2N5363

2N4220
2N4221
2N4221
2N4222
2N4222

2N5903
2N5904
2N5905
2N5906
2N5907

2N5903
2N5904
2N5905
2N5906
2N5907

3G5
3N145
3N146
3N147
3N148

2N3821
3N163
3N163
3N189
3N189

2N4860JANTX
2N4861
2N4861A
2N486IJAN
2N4861JANTX

2N4B57 JANTX
2N4861
2N4861
2N4858JAN
2N4858JANTX

2N5364
2N5391
2N5392
2N5393
2N5394

2N4222
2N4867A
2N4B68A
2N4869A
2N4869A

2N5908
2N5909
2N5911
2N5912
2N5949

2N5908
2N5909
2N5911
2N5912
2N5486

3N149
3N15O
3N151
3N155
3N155A

3Nl61
3N163
3N190
3N163
3N163

2N4867
2N4867A
2N4868
2N4868A
2N4869

2N4867
2N4867A
2N4868
2N4868A
2N4869

2N5395
2N5396
2N5397
2N5398
2N5432

2N4869A
2N4869A
2N5397
2N5398
2N5432

2N5950
2N5951
2N5952
2N5953
2N6085

2N5486
2N5486
2N5484
2N54B4
1Tl22

3N156
3N156A
3N157
3N157A
3N158

3N163
3N163
3N163
3N163
3N163

2N4869A
2N4878
2N4879
2N4880
2N4937

2N4869A
2N4878
2N4879
2N4880
1n31

2N5433
2N5434
2N5452
2N5453
2N5454

2N5433
2N5434
2N5452
2N5453
2N5454

2N60B6
2N6087
2N6088
2N6089
2N6090

ITI22
1T121
ITI21
ITI22
1Tl21

3N158A
3N160
3N161
3N163
3N164

3N163
3N161
3N161
3Nl63
3N164

2N4938
2N4939
2N494O
2N4941
2N4942

ITI32
IT132
IT132
1T131
1Tl32

2N5457
2NS458
2N5459
2N5460
2N5461

2N5457
2N5458
2N5459
2N5460
2N5461

2N6091
2N6092
2N6441
2N6442
2N6443

1T121
1T121
ITl22
1Tl22
ITl22

3N165
3N166
3N167
3N168
3N169

3N165
3N166
3N161
3N161
3N170

2N4955
2N4956
2N4977
2N4978
2N4979

1Tl22
1Tl22
2N5433
2N5433
2N4859

2N5462
2N5463
2N5464
2N5465
2N5471

2N5462
2N5463
2N5464
2N5465
2N5265

2N6444
2N6445
2N6446
2N6447
2N6448

IT122
ITl21
ITl21
1Tl21
1T121

3N170
3N171
3NI72
3N173
3N174

3N170
3N171
3N172
3NI73
3N163

2N5018
2N5019
2N502O
2N5021
2N5033

2N5018
2N5019
2N2843
2N2607
2N5460

2N5472
2N5473
2N5474
2N5475
2N5476

2N5265
2N5265
2N5265
2N5265
2N5266

2N6451
2N6452
2N6453
2N6454
2N6483

U310
U310
U310
U310
2N6483

3N175
3N176
3N1n
3N178
3N179

3N170
3N170
3N171
3NI72
3N172

"CONSULT FACTORY

I
23

....
..

......

2N5457
2NS457
~~5457

....
..
..

2N4868
2.~5484

2.~3821

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE

SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALT£RNATE
SOURCE PRODUCT

INTEIISIL
EQUIVALENT

ALT.ERNATE
SOURCE PRODUCT '

, INTERSIL
EQUIVALENT

3NI80 '
3NI81
3NI82
3NI83
3NI88

3NI72
3NI61
3NI61
3NI61
3NI88

AD7520KD
AD7520KN
AD7520LD
AD7520LN
AD7520SD

AD7520KD
AD7520KN
AD7520LD
AD7520LN
AD7520SD

AH0139D/883
AHOI4OCD
AHOl4OD
AH0140D/883
AHOl41CD

DG I 39AK/883B
DGl40BK
DGI40AK
DG 140AKl883B
DGI41BK

BF801
BF802
BF804
BF805
BF806

2N4867
2N4338
2N4338
2N4869
2N4869

3NI89
3NI90
3NI91
3N207
3N208

3NI89
3NI9O
3NI91
3NI90
3NI88

AD7520TD
AD7520UD
AD752lJD
AD752lJN
AD7521KD

AD7520TD
AD7520UD
AD7521JD
AD752lJN
AD7521KD

AHOl41D
AH0141D/883
AHOl42CD
AHOl42D
AH0142D/883

DGI41AK
DGI41AKl883B
DGI42BK
DGI42AK
DG142AK/883B

BF808
BF810
BF811
BF815
BF816

2N4868
2N4858
2N4858
2N4858
2N4858

3SK22
3SK23
3SK28
42T
4360TP

2N5486
2N5397
2N5397
2N4392
2N5462

AD7521KN

BF817

AD7521lD

DG143AK

BF818

AD7521LN
AD7521SD
AD752lTD

AD7521LN
AD7521SD
AD752ITO

AHOl43CD
AH01430
AH0143D/883
AHOl44CD
AHOl44D

DGI43BK

A07521LD

DG143AK/883B
DGI44BK
DGI44AK

BFSIO
BF II
BF 12

2N4858
2N4858
U401
U401
U402

5033TP
588U
58T
59T
703U

2N5460
2N4416
2N5457
2N4416
2N4220

AD7521UD
AD7523AD
AD7523BD
AD7523CD
AD7523JN

AD7521UD
AD7523AD
AD7523BD
AD7523CD
AD7523JN

AHOI44D/883
AHOl45CD
AHOl45D
AH0145D/883
AHOI46CD

DG144AK/883B
DGI45BK
DGI45AK
DG I 45AK/883B
DGI45BK

BFQI3
BFQI4
BF l5
BFS 16
BF 23

U406
IT5912

704U
705U
707U
714U
734EU

2N4220
2N4224
2N4860
2N3822
2N4416

AD7523KN
AD7523SD
AD7523TD
AD7523UD

AD7523KN
AD7523LN
AD7523SD
AD7523TD
AD7523UD

AHOl46D
AHOI46D/883
AHOl51CD
AH0151D/883
AHOl52CD

DGI46AK
DG146AK/8838
DGI5IBK
DGl5IAK/883B
DGI52BK

BF 44
BFr
BF 45
BF 49A
BF 49B

IT5912
2N3055
2N3958

734U
751U
752U
753U
754U

2N5516
2N434O
2N434O
2N4341
2N434O

AD7530JD
AD7530JN
AD7530KD
AD7530KN
AD7530LD

AD7530JD
AD7530JN
AD7530KD
AD7530KN
AD7530LD

AHOl52D
AH0152D/883
AHOl53CD
AHOl53D
AH0153D/883

DGI52AK
DG I 52AK/883B
DGI53BK
DGI53AK,
DG I 53AKlS83B

BFQ49C
BFS21
BFS21A
BFS67
BFS67P

2N3958
2N5199
2N5199
2N3821
2N5459

755U

2N4341
2N434O
ITE4416
ITE4416
2N4416

AD7530LN

DGI54BK

AD753lJN
AD7531KD
AD7531KN

AD7530LN
AD753lJD
AD753lJN
AD7531KD
AD7531KN

AHOl54CD

AI90
AI91
AI92
AI93
AI94
AI95
AI96
AI97

2N5484
2N5484
2N5484
ITE4416
ITE4391

AD7531LD
AD7531LN
AD7533AD
AD7533BD
AD7533CD

AD7531LD
AD7531LN
AD7533AD
AD7533BD
AD7533CD

AI98
AI99
A5T382I
A5T3822
A5T3823

ITE4392
ITE4393
2N5484
2N5484
2N4416

AD7533JN
AD7533KN
AD7533LN
AD7533SD
AD7533TD

AD7533JN
AD7533KN
AD7533LN
AD7533SD
AD7533TD

A5T3824
A5T5460
A5T5461
A5T5462
ADI08

2N4341
2N5460
2N5461
2N5462
LMI08

AD7533UD
' AD754IAD,
AD7541BD
AD754lJN
AD754IKN

AD30B
AD3954A
AD3955
AD3956

LM308
2N3954
2N3954A
2N3955
2N3956

AD3958
AD503
AD589
AD590
AD5905

AD7521KN

A07523LN

U403
U404
U405

U403
lT5912

AH0154D

DG154AK

AHOI54D/883
AHOl55D
AHOl61CD

DGI43AK/883B
DGI5IAK
DGI61BK

BFS68
BFS68P
BFS70
BFS71
BFS72

2N3823
2N4416
2N3821
2N3822
2N3823

AHOl61D
AHOl61D/883
AHOl62CD
AHOl62D
AHOI62D/883B

DGI61AK
DGI61AKl883B
DGI62BK
DGI62AK
DG 162AK/883B

BFS73
BFS74
BFS75
BFS76
BFS77

2N3821
2N4856
2N4858
2N4859

AHOl63CD
AHOl63D/883
AHOl64CD
AHOl64D

DGI63BK
DGI63AK
DG I 63AK/883B
DGI64BK
DGI64AK

BFS78
BFS79
BFS80
BFTIO
BFTlI

2N4860
2N4861
2N4416A
2N5397
2N5019

AD7533UD
AD754IAD
AD7541BD
AD754lJN
AD7541KN

AHO 1640/883
AH5009CN
AH50IOCN
AH5012CN
AH5013CN

DG I 64AK/883B
IH5009CPD
IH50lOCPD
IH5012CPE
IH5013CPD

BFWIO
BFWII
BFWI2
BFWI3
BFW39

2N3823
2N3822
2N4416
2N4867
1Tl29

AD7541SD
AD754lTD
AD810
AD811
AD812

AD7541SD
AD754lTD
2N4878
2N4878
2N4878

AH5014CN
AH5015CN
AH5016CN
AM50llCN
BC264

IH5014CPD
IH5015CPE
IH5016CPE
IH50llCPE
2N5458

BFW39A
BFW54
BFW55
BFW56
BFW61

ITi20
2N3822
2N3822
2N4860
2N4224

2N3958
AD503
ICL8069
AD590
2N5905

AD813
AD814
AD815
AD816
AD818

2N4878
1T124
1Tl24
1Tl20A
1Tl4O

BC264A
BC264B
BC264C
BC264D
BCY87

2N5457
2N5458
2N5458
2N4416
1Tl21

BFXII
BFX.15
BFX36
BFX70

ITl32
1Tl22
1Tl31
ITi22
ITl22

AD5906

2N5906

AD5907

2N5907

2N5908
AD5908
2N5909
AD5909
AD7506/COM/CHIPS IH6116C/D

AD820
AD821
AD822
AD830
AD831

ITl32
1Tl30A
1Tl30A
2N552O
2N5521

BCY88
BCY89
BF244
BF244A
BF244B

1Tl22
1Tl22
2N5486
2N5484
2N5485

BFX78
BFX82
BFX83
BFX99

AD7506/MIUCHIPS
AD7506JD
AD7506JD/883B
AD7506JN
AD7506KD

IH6116M/D
IH6116CJI
IH6116CJI/883B
IH6116CPI
IH6116CJI

AD832
AD833
AD833A
AD835
AD836

2N5522
2N5523
2N5524
2N3954
2N3955

BF244C

BF245
BF245A
BF245B
BF245C

2N5486
2N5486
2N4416
2N4416
2N4416

AD7506KD/883B
AD7506KN
AD7506SD
AD 7506SD/883B
AD7506TD

IH6116CJI/883B
IH6116CPI
IH6116MJI
IH6116MJI/883B
IH6116MJI

AD837
AD838
AD839
AD840
AD841

2N3955
2N3956
2N3957
2N5520
2N5521

BF246
BF246A
BF246B
BF246C
BF247

2N5485
2N5639
2N5638
2N5638
2N4091

BFV85

ITI22

BFY86
BFY91
BFY92
BN209

1T122
ITI22
1Tl22
1Tl22

AD7506TD/883B
AD7507/COM/CHIPS
AD7507/MIUCHIPS
AD7507JD
AD7507JD/8838

IH6116MJI/883B
IH6216C/D
IH6216M/D
IH6216CJI
IH6216CJI/883B

AD842
AHOl26CD
AHOl26D
AHOl26D/883
AHOl29CD

2N5523
DGI26BK
DGI26AK
DG I 26AK/883B
DGI29BK

BF247A
BF247B
BF247C
BF256
BF256A

2N4091
2N4091
2N4091
2N5484
2N5484

BSV22
BSV78
BSV79
BSV80
BSX82

2N4416
2N4856A
2N4857A
2N4858A
2N3822

AD7507JN
AD7507KD
AD7507KD/883B
AD7507KN '
AD7507SD

IH6216CPI
IH6216CJI
IH6216CJI/883B
IH6216CPI
IH6216M/D

AH0129D

DG129AK

AHOI29D/883
AHOl33CD
AHOl33D
AHOl33D/883

DGI29AK/883B
DGI33BK
DGI33AK
DG 133AKl883B

BF256B
BF256C
BF320
BF320A
BF320B

2N4416
2N4416
2N5461
2N5460
2N5461

C21
C2306
C38
C413N
C610

2N5196
2N4338
2N5434
2N4392

AD7507SD/8838
AD7507TD
AD7507TD/883B
AD7520JD

IH6216MJI/8838
IH6216MJI
IH6216MJI/883B
AD7520JD
AD7520JN

AHOl34CD
AHOl34D
AH0134D/883,
AHOl39CD
AHOl39D

DGI34BK
DGI34AK
DG I 34AKl883B
DGI39BK
DGI39AK

BF320C
BF346
BF347
BF348
BF800

2N5462
ITE4392
J201
J310
2N4867

C611
C612
C613
C614 '
C615

2N4221
2N4221
2N4221
2N4220
2N4221

756U

AD3954

A07520JN

··CONSULT FACTORY

AD7531JO

AH0163D

24

BFX71
BFX12

BFY20
BFY81
BFY82
BFY83

BFY84

2N4857

ITl22
2N5397
2N5019
2N5019
1T120A
1T122
1T122
ITI22
1T122
1T122

2N3821

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

C620
C621
C622
C623
C624

2N4220
2N4220
2N4220
2N4220
2N4220

01202
01203
0123AL
D123AP
DI23BP

2N3821
2N4220
0123AL
0123AK
01238K

DG151BP
OGI52AL
DG152AP
OGI52BP
OGI53AL

DG1518K
OGI52AL
DG152AK
OG152BK
DG153Al

OGI88BP
DG189Al
OGI89AP
OGI89BP
OGI90AL

OGI88BK
DG189Al
OGI89AK
OG189BK
OGMI90AL

C625
C650
C651
C652
C653

2N4220
2N4220
2N4220
2N4220
2N4220

DI23SP
0125AL
0125AP
OI25BP
0129Al

0123BJ
0125AL
0125AP
D125BK
O129Al

DG153AP
DG153BP
OGI54AL
OGI54AP
OGI54BP

OGI53AK
OGI53BK
OGI54AL
OG154AK
OGI54BK

OGI90AL
OGI90AP
OGI90AP
DG190BP
OGI90BP

OGI90AL
OGMI90AK
OGI90AK
OGMI9DCJ
OGM190BK

C6690
C6691
C6692
C673
C674

2N4341
2N4341
2N4339
2N4341
2N4341

0129AP
0129BP
01301
01302
01303

D129AK
0129BK
2N4222
2N4220
2N4220

DG161Al
DG161AP
OGI6lBP
DG162Al
OGI62AP

OG161AL
OG161AK
OG161BK
OG162Al
OG162AK

OG190BP
OG191AL
0G191AL
OGI91AP
0G191AP

OG190BK
OGM191Al
OGI91AL
OGM191AK
OGI91AK

C680
C680A
C681
C681A
C682

2N4338
2N4338
2N4338
2N4338
2N4339

01420
01421
01422
02T2218
02T2218A

2N4868
2N3822
2N4869
ITl29
ITI29

OG162BP
DGI63Al
OGI63AP
OGI63BP
OGI64AL

OG162BK
OGI63AL
OGl63AK
OG163BK
OGI64AL

OGI91BP
DG191BP
0G191BP ,
OG200AA
OG200AK

OGMI91CJ
OGM191BK
OG191BK
OG200AA
OG2ooAK

C682A
C683
C683A
C684
C684A

2N4339
2N4339
2N4339
2N4220
2N4220

D2T2219
02T2219A
D2T2904
02T2904A
02T2905

ITl29
ITl29
IT139
ITl39
ITl39

DG164AP
DG164BP
DGl80AA
DG180Al
OGI80AP

DG164AK
OG164BK
OG180AA
OGI80AL
OGl80AK

DG200Al
OG200AP
OG200BA
OG2ooBK
OG200BP

OG200AL
OG200AK
OG200BA
OG200BK
OG200BK

C685
C685A
COO
C81
C84

2N4220
2N4220
2N4338
2N4338
2N4338

02T2905A
02T918
OA102
DA402
DAClO20lCD

1T139
ITI29
2N5196
2N5196
A07520lD

OGI80BA
OGI80BP
OGI81AA
DG181AA
DG181Al

OGl80BA
OGl80BK
DGM181AA
OG181AA
OGM181AL

OG200CJ
OG201AK
OG201AP
OG201BK
OG20lCJ

OG200CJ
OG20lAK
OG20lAK
OG20lBK
OG201CJ

C85
C91
C92
C93
C94

2N4338
2N4858
2N4091
2N4393
2N5457

OAC1020lD
OAC1021lCO
OACI021LD
OAC1022LCO
DAC1022lD

AD7520UD
A07520KO
A07520TD
AD7520JD
A07520SD

DG181Al
OG181AP
OGI81AP
OG181BA
OGI81BA

OG181AL
OGMI81AK
OGI81AK
OGMI81BA
OGI81BA

DG210BP
OG281AA
OG281AP
OG281BA
OG281BP

OG201BK

IHI82CTW
IH182CJO

C94E
C95
C95E
C96E
C97E

2N5457
2N5457
2N5459
2N5484
2N3822

OACI218LCO
OAC1218LCN
OACI218LCN
OAC1219LCO
OACI219LCN

A07541BD
A07541LN
A07541KN
AD7541AD
AD754lJN

OG181BP
OGI81BP
OG181BP
OGI82AA
OGI82AA

OGMI81CJ
OGMI81BK
OG181BK
OGMI82AA
OGI82AA

OG284AP
OG284BP
OG287AA
OG287AP
OG287BA

IHI85MJE
IHI85CJE
IHI88MTW
IHI88MJO
IHl88CTW

C98E
CA308
CC4445
CC4446
CC697

2N3822
LM308
2N5432
2N5434
2N4856

OAC1220LCO
OACI220LD
OACI221LCO
OAC1221LO
OAC1222LCO

AD7521LD
A07521U0
A07521KO
A0752\T0
A0752lJD

DG182Al
OG182AL
OGI82AP
OGI82AP
OGI82BA

DGM182AL
OGI82AL
OGM182AK
OGI82AK
OGMI82BA

OG287BP
OG290AP
OG290BP
OG381AA
OG381AK

IHl88CJO
IH191MJE
IHI9ICJE.
OGM182AA
OGMI82AK

COnoolH
C022015E
CF2386
CF24
CFM 13026

ICMI424C
ICM7051A
2N5458
2N3824
2N4858

OACI222LO
OGI23AL
OGI23AP
OGI23BP
0G125AL

A0752150
OG123AL
OG123AK
OG1238K
OG125AL

OGI82BA
OGI82BP
OGI82BP
OGI82BP
OGI83AL

OGI82BA
OGMI82CJ
OGMI82BK
OGI82BK
OGI83AL

OG381AP
OG381BA
OG381BK
OG381BP
OG381CJ

OGMI82AK
OGM181BA
OGM181BK
OGMI81BK
OGM181CJ

CM600
CM601
CM602
CM603
CM640

2N4092
2N4091
2N4091
2N4091
2N4093

OG125AP
OGI25BP
OGI26AK
OGI26AL
OG126BP

DG12SAK
OGI258K
OGI26AK
OG126AL
OGI26BK

OGI83AP
OGI83BP
OGI84AL
OGI84AL
OGI84AP

DG183AK
OGI83BK
OGM184AL
OGI84AL
OGM184AK

OG384AK
OG384AP
OG384BK
OG384BP
OG384CJ

DGM185AK
OGMI85AK
DGM184BK
OGMI84BK
OGMI84CJ

CM641
CM642
CM643
CM644
CM645

2N4093
2N4093
2N4092
2N4092
2N4092

OGI29AL
OGI29AP
OGI29BP
OG133AL
OG133AP

OG129AL
DG129AK
OGI29BK
OG133AL
OGI33AK

OG I84AP
OGI84BP
OGI84BP
OGI84BP
OGI85AL

OGl84AK
OGM184CJ
OGM184BK
OGl84BK
OGMI85AL

DG387AA
OG387AK
OG387AP
OG387BA
OG387BK

OGMI88AA
OGMI88AK
OGMI88AK
OGMI87BA
OGMI87BK

CM646
CM647
CM650
CM651
CM652

2N4092
2N4091
2N5432
2N5433
2N5432

OGI33BP
OG134AL
OGI34AP
OGI34BP
OGI39AL

OGI33BK
DG134AL
DG134AK
OG134BK
OG139AL

OGI85AL
OGI85AP
0G185AP
OGI85BP
OGI85BP

OGI85AL
OGM185AK
OG185AK
OGM185CJ
OGM185BK

DG387BP
OG390AK
OG390AP
OG390BK
OG390BP

DGM187BK
OGMI91AK
OGMI91AK
OGM190BK
OGMI90BK

CM653
CM697
CM8DO
CM856
CM860

2N5433
2N5433
2N5433
2N5433
2N4868A

OG139AP
OGI39BP
OGI40AL
OGI40AP
OGl40BP

OG139AK
OGI39BK
OGI40AL.
OGI40AK
OGI40BK

OGl858P
OGI86AA
OGI86AL
OGI86AP
OGI86BA

OG185BK
OG186AA
OG186AL
OGI86AK
OGl86BA

OG390CJ
OG503
OG5040AK
OG5040AL
OG5040CJ

OGMI9DCJ
A0503
IH5040MJE
IH5040MFD
IH5040CPE

CMX740
CP640
CP643
CP650
CP651

2N5432
2N4091
2N5434
2N5432
2N5433

OG141AL
OGI41AP
OG141BP
OGI42AL
OG142AP

OG141AL
OG141AK
OG141BK
OG142AL
OGI42AK

OGI86BP
OGI87AA
OGI87AA
OGI87AL
OGI87AL

OGI86BK
OGM187AA
OGI87AA
OGMI87AL
OGI87AL

OG5040CK
OG5041AA
OG5041AK
OG504IAL
OG5041CJ

IH5040CJE
IH5041MTW
IH504IMJE
IH504IMFO
IH5041CPE

CP652
CP653
01101
01102
01103

2N5433
2N5433
2N3821
2N3821
2N4338

OGI42BP
OG143AL
OGI43AP
OG143BP
OGI44AL

OG142BK
OG143AL
OGI43AK
OG143BK
OG144AL

OGl87AP
OGI87AP
OGI87BA
OGI87BA
OGI87BP

OGMI87AK
OGI87AK
OGM187BA
OGI87BA
OGMI87BK

OG5041CK
OG5042AA
OG5042AK
OG5042AL
OG5042CJ

IH5041CJE
IH5042MTW
IH5042MJE
IH5042MFO
IH5Q42CPE

01177
01178
01179
01180
01181

2N3821
2N3821
2N4338
2N3822
2N4338

OGI44AP
DG144BP
OG145AL
OG145AP
OG145BP

OGl44AK
DG144BK
OGI45AL
OGI45AK
OGI45BK

OGI87BP
OGI88AA
OGI88AA
OGI88AL
OG188AL

OGI87BK
OGMI88AA
OGI88AA
OGMI88AL
OGI88AL

OG5042CK
OG5043AK
OG5043AL
OG5043CJ
OG5043CK

IH5042CJE
IH5043MJE
IH5043MFO
IH5043CPE
IH5043CJE

01182
01183
01184
01185
01201

2N4338
2N4341
2N4340
2N4339
2N4224

OGl46AL
DG146AP
OGl46BP
OG151AL
OGI51AP

OGI46AL
OGl46AK
OGI46BK
DG15lAl
OGI51AK

OGl88AP
OGI88AP
OG188AP
OG188BA
OGI88BA

OGMI88BK
OGMI88AK
OGI88AK
OGMI88BA
OGI88BA

OG5044AA
OG5044AK
OG5044AL
OG5044CJ
OG5044CK

IH5044MTW
IH5044MJE
IH5044MFO
IH5044CPE
IH5044CJE

"CONSULT FACTORY

25

:m~~~j~

,' .. ".'
ALTERNATE
SOURCE P,!ODUC.T

'..

..........

""

INTERSIL
EoUIVALE"lT

DG5045AK
OG5045AL

IH5045MJE
IH5045MFD

DG504SCJ
DG5045CK

IH5045CPE
IH5045CJE

DG506J\~

IH6116MJI

DG506BR

IH6116CJI

DG506CJ
OG507AR.
DGS07BR

IH6116CPI
IH6216MJI
IH6216CJI
IH6216CPI

ALTERNATE
SO""I:E. PIIO!)UCT

:

INTERSIL
EQUIVAL:ENT

E212
E230
E231
E232

2N5397
2N5397
2N4867
2N4868
2N4869

E270
E271
£300
E304
E30S

J270
J27\
2NS397
2NS486
2NS464

E308
E309
E310
E311
E312

J308
J309
J310
J310
2NS397

IH6208CPE
DGlllAL
DGlllAK
DGlllBK
2N3821

E400
E401
E402
E410

DN3067A
DN3068A

2N4338

DN3069A

2N3822
2N3821

£412
E413
E414

DG507CJ

DG508AP
DGSOBBP
DG508CJ

DGS09AP
DGS09BP
DGS09CJ

DGMlllAL
DGMlllAP
DGMUlBP
DNJa66A

DN3070A
DN3071A

ON336SA
ON336SB
DN3366A'
DN3366B
DN3367A
DN3367B

IH610BMJE

IH6108CJE
IH6108CPE
lHS20BMJE

IH6208CJE

2N4338

E211

E411

HIl-0506A-2
HII-OS06A-5
HII-0506A-8

IH5116MJI
lHS116UI
IHS116MJI/883B

ESM4445
ESM4446

2NS432
2N5434
2N5432
2NS434

G116AL
G116AP
G116BP

HII-OS09-2
HIl-OS09-S

GII6AK

2N4386
2NS4B5

Gl17Al
GllBAL
G118AP

2N4341

-H1OOA

2N3821
2N3821

2~4222

FEI02

2N4119

2N4339
2N4220

FE102A

2N4119
2N4118
2N4118
2N4092

FEI04
FEI04A

G1l68P

G119AL
GI23AL
Gl23AP
GET54S7

GETS458
GETS4S9
HA2720

2N3821

IH6216MJI

HII-0507A-2
HIl-0507A-5

IH6216MJII883B
IH5216MJI
IH5216UI

2N5460

HIl-OS07A-8
HIl-OS08-2

IHS216MJI/883B
IH6108MJE

HIl-OS08-5

IH6!08CJE
IH6108MJE/883B
tH5108MJ£
IH5108UE
IHSI08MJE/883B

G116AL

IH6208CJE
IH6208MJE/8838
IHS208MJE

HII-OS09A-S

IHS208IJE

G1l7Al
GllBAL

Hll-OS09A-8

HIl-5040-2

IHS208MJE/883B
IHS040MJE

Gl18AK
Gll9AL

HIl-5040-5

IHS040CJE

HII-5040-8

IHS040MJEI883B

G123Al

HIl-504l-2

GI23AK

HIl-5041-5
" HIl-S041-8

IHS041CJE
IHS041MJEI883B

HI 1-5042-2

IH5042MJE
IH5042CJE
IHS142MJE/8838

2NS4S7
2N5458

2N54S9
ICL8021

2N3821

HA7807
HA7809

ITI32
tTI32

HD43871

ICM70S0H
ICM70S0G
3NI63

FE3819
FE4302

2NS484
2NS4S7
2NS4S9
2NS4S8
2N4416

HEP801
HEP802

2N3822

HEP803
HEPFOO21
HEPFlO35

2NSOl9
2NS484
JI76

2N4416

2N4416
2N4339

2NS398
2N5458

J204
2NS4S7
2NS459

FE4303
FE4304

FES245
FES246
FES247

FES4S7
FE5458
FES4S9

2NS486
2N54S7

FE5484

2N5484

FES48S

J107

FE5486

2NS48S
2N5486

JlOS
JI06

FMllOO

El12A

JI12
JI13
JI13

JIll
ICMl115A
J11l

JI12

J204

ICMI1l5B

FF400

2N5457
2N39S4A

HI0-OS07-6

2N5906
2NS906

HIO-OS07 A-6
HI0-OS08-6

2N3954

FMIl02A
FMl103

2NS906
2N39SS

HIO-OS08A-6
HI0-0509-6
HI0-0509A-6

FMllOM
FMll04
FMll04A
FMll05
FMll05A

2NS908

HIO-S040-6

2N39S7

2N5909
2N3954A
ITSOO

HI0-5041-6
HI0-S042·6
HI0-S043-6 .
HI0-S044-6

FMll06
FMII06A

2N3954A
1T500

HIO-S04S-6
H10-5046-6

2N3954
ITSOO
2N39S5

HI0-5047-6
HI0-5049-6
HI0-SOSO-6

IT502
2N3957
ITS03
2N39SS
2NS908

HI0-SOSI-6
HII-0200-2
HII-020D-4
HIl-0200-S
HIl-0200-6

ICM7050U

EI7S
EI76

J175
J176
JI77

FMl107
FMll07A

J201
J202
J203
J204
2NS397

FMll08A

"CONSULT FACTORY

HI0-0387-6
HI0-0390-6
HI0-OS06-6
HI0-OS06A'6

FMllOOA
FMllOIA
FMll02

EI426
El74

Jl74

HI0-0201-6
"10-0381'6
HI0-0384-6

2NS4S8
2NS4S9

JIOS
J106

JI07

HEPF2004
HEPF200S

2NS484

FMll08
FMl109

FMll09A
FMIIIO
FMIIIOA

26

IH6208MJE

G116BK
G116BJ

2N3822
2N3821
2N3821

ICl7667
2NS397

IH6216CJI

HIl-OS09-8
HII-0509A-2

FE204

HDIGl030

DGM190BK

HII-OS07-8

FE300
FE302
FE304

HD43871

DGM188AK

HIl-OS07-2
HIl-OS07-5

2N5486

2N4338

2N3821

DGMI8SAK/883B
OGMI87BK
DGMI88AK/883B
DGMI91AK

2NS486
2N4221
2N4221

2N4869
2N4868

EllO
[Ill
Ell15
ElllA
E112

E204
E210

2N4339
2N4340

HIl-OS08A-8

FE202

E20l

FP4339

Gl1S8J

2N4338

E202
E203

2N3956
2N39S7

GllSBK

DNX2

El77

IT5911

G1l58P

FEI600
FE200

EII3A
E114
EllSI

2N39S7

FM39S8

FM39S6

GlISBP

2N4338

E1l3

FM39S7

2N5454

2N5458

2N4338
2N4220

E109

ITS911

ESM4304

DN3460A
DN34608
ONXI

E"IOS

HII-OS06-8

DGM191AK/8838
IH6116MJI
IH6116CJI
IH6116MJI/883B

HIl-0506-5

HIl-0508-8
HIl-0508A-2
Hll·0508A-S

FEiOO

EI06
El07
El08

HIl-0390-S
HI 1-0390-8
HIl-OS06-2

3NI63
GllSAK

FE0654B

DU4340
ElOO
EI0l

2N3954
2N39S4A
2N39SS
2N39S5A'
2N39S6

FM3954A
FM3955
FM3955A

HI 1-0390-2

FT703
FT704
GllSAP

FE06S4A

El02
El03

FM3954

HIl-0387-8

2N4093
2NS457
2NS4S9

2N4338

DGM182AK/883B
DGM185AK

'DGM184BK

2N39SS
2N39SS
2N39S7
2N39SS
IT5911

2N3955A

ESM4093
ESM4302
ESM4303

2N4220

DGMI82AK
DGMI81BK

2N3954

2N5019

2N4339

DG201AK
DG201BK

DG20lBK
DG20lAK/883B

2N39S5
2N39S5A
ITS911

2N5019
3N161

DN34378
ON3'438A
DN3438B
DN34S8A
DN3458B

DG200AKI.883B

FM1207
FM12Q8

FT3820

ESM4447
ESM4448

INTERSIL
EQUIVALENT

FMI209
FMl210
FM12I1

FT3909

2N4340

2N4338

HIl-0384-S

2N4091
2N4092

DN3437A

DNXl

HIl-0384-S
HIl-0387-2
HIl-0387-S

HIl-0384-2

ESM4091
ESM4092

2N4341
2N4222

DNXB

HIl-0381-2
HIl-0381-5
HIl-0381-8

E431
ESM2S
ESM2SA

2N3686
2N4Q91

DN3436A
DN3436B

DNX9
DS0026
DU4339

2N3954
2N3955A
2N39SS
2N3954
2N3954

FT0654C
FT0654D
H3820

2N4338
2N4338

DNXS
DNX6

HI1~0201-8

J309(X2)
J310(X2)
U401
U401

2N4339
2N4220

ONX3
ONX4

FM1206

HIl-0200-8
HIl-0201·2
HIl-0201-4
HIl·0201-5

FT06S4B

DN3370A
DN3370B

DN34S9B

FM1202
FMI203
FMI204
FMI20S

2N3957
2N5909
2N5196
2N3954
2N3954

ALTERNATE
SOURCE PRODUCT

IT5912

E421
E430

DN3368A
ON3368B
DN3369A'
DN3369B

DN34S9A

FMllll

FMIlllA
FMII12
FM1200
FM1201

INTERSIL
EQUIVALENT

1T5911

E41S
E420

2N4220
2N4091

2N4091
2N4341
2N4221

ALTERNATE
SOURCE PRODUCT

FP4340
FT0654A

2N4338

2N3687

,".

2NS484

HIl-5042-5
HII-5042-8
HIl-S043-2

IHS041MJE

IHS143MJE
IH5143CJE

HIl-S043-S
HII-5043-8

IHS143MJEl883B

HIl-S044-2
HIl-S044-S

IH5144MJE
IHSJ44CJE

HII-5044-8
HII-S045-2
HIl-504S-S

IH5144MJE/883B
IHSI4SMJE

HIl-5045-S

IH514SCJE
IHS14SMJE/8838

HIl~5046-2

IHS046MJE

HIl-5046·S
HIl-S046-8
HIl-5047-S

IHS046CJE
IHS046MJEl8838
IHS047MJE
IHS047CJE

DGM184C/O

Hll·5047~8

IHS047MJEl883B

OGM187C/D

HIl-5049-2
HIl-S049-S
HIl-5049-8
HIl-5050-2

IHS149MJE
tHS149CJE
IH5149MJEt,8838

2NS484

2NS4S9
OG20lCID
OGMI81C/O

DGMI90C/D
IH6116C/O
IH5116C/O
IH6216C/O

HII-S047-2

Hil-SOSO-S

IH51S0MJE
IH51S0CJE

IH5216C/D

HIl-SOSO-8

IH5150MJEJ8838

IH6108C/D
IHSI08CID
IH6208C/D

HIl-SOSI-2
Hil-SOSI-S

IHSISIMJE

HU-5051-8

IHSI51MJE/883B

IHS20BC/D

HI2-0200-2

OG200AA

IH5140C/D
IHS141C/O
IH5142C/O

HI2-0200-4

DG200BA
OG200BA
OG200AAI883B

IHSlS1CJE

IHSI43C/D

HI2-0200-S
HI2-0200-8
HI2-0381-2

IHS144C/D

HI2-0381-S

DGMI81BA

IHS145C/O

OGM18lAA/883B

IHS046C/D

HI2-0381-8
H12-0387-2

IH5047C/D
IH5149CI.D
IH5150C/O

HI2-0387-S
H12-0387-8
HI3-0200-S

OGMI88AAl883B
DG200CJ

IHSOSICID
DG200AK
DG200BK
DG200BK
OG200C/D

HI3-0201-S
HI3-0381-5
H13-0384-S
HI3-0390-S
HI3-0506-5

DG20lCJ
OGMI81CJ
DGMI84CJ
DGMI90CJ
IH6116CPI

OGM182AA

DGMI88AA
DGM1878A

ALTERNATE
SOURCE PROOUCT

INTERalL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE

SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

HI3-0506A-5
HI3-0507-5
HI3-0507A-5
HI3-0508-5
HI3-0508A-5

IH5116CPI
IH6216CPI
IH5216CPI
IH6108CPE
IH5I0SCPE

ITC4023
ITC4024
ITC4025
1TE2453
11E2639

ITI37
ITI37
ITI37
ITI20
ITl20

J109
JI09-18
J110
J110-18
J111

JI06
JI06
JI07
JI07
Jill

J4393
J4416
J4856
J4857
J4858

ITE4393
ITE4416
ITE4856
ITE4857
ITE4858

HI3-0509-5
HI3-0509A-5
10100
10101
IMF3954

IH620BCPE
IH5208CPE
10100
10101
2N3954

ITE2640
ITE2641
11E2642
11£2643
ITE2644

ITI22
11122
ITl20
ITl22
ITl22

Jill-IS
JlllA
Jll1A-18
J112
Jl12-18

Jll1
Jill
Jll1
J112
J112

J4859
J4860
J4861
J4867
J4867A

ITE4859
ITE4860
ITE4861
2N4867
2N4867A

IMF3954A
IMF3955
IMF3955A
IMF3956
IMF3957

2N3954A
2N3955
2N3955A
2N3956
2N39S7

ITE2720
11£2721
ITE2722
11£2903
ITE2913

1T120
ITl22
1Tl20
ITI22
ITI22

JI12A
J112A-18
J113
J113-18
J113A

J112
J112
J113
J113
J113

J4867RR
J4868
J4868A
J4868RR
J4869

2N4867
2N4868
2N4868A
2N4868
2N4869

IMF3958
IMF5911
IMF5912
IMF6485
IT 100

2N3958
IMF5911
IMF5912
IMF6485
1Tl00

ITE2914
11£2915
ITE2916
ITE2917
ITE2918

ITI22
IT120
ITI20
1Tl22
1Tl22

Jl13A-IS
J114
J1401
JI402
JI403

Jl13
2N5555
IT501
IT502
IT503

J4869A
J4869RR
J5103
J5104
J5105

2N4869A
2N4869
2N5484
2N5485
2N5486

ITIOI
ITlO8
ITI09
ITI20
ITI20A

ITIOI
ITE4416
ITE4416
IT120
ITl20A

ITE2919
ITE2920
ITE2936
ITE2937
ITE2972

1Tl20
1Tl20
1Tl20
ITI20
ITl22

J1404
JI405
JI406
JI74
J174-18

IT503
IT504
IT505
JI74
JI74

J5163
K114-18
K210-18
K211-18
K212-18

2N5486
2N5555
2N5397
2N5397
2N5397

ITI21
ITI22
!TI24
ITI26
ITI27

ITl21
\T122
ITI24
1T126
ITI27

ITE2973
11£2974
ITE2975
ITE2976
ITE2977

ITl22
ITI20
ITl20
1Tl20
1Tl20

JI75
J175-18
JI76
J176-18 '
JI77

JI75
JI75
J176
J176
JI77

K300-18
K304-18
K305-18
K308-18
K309-18

2N5397
2N5486
2N5484
J308
J309

ITI28
1Tl29
ITI30
ITI30A
ITI31

IT128
ITl29
!TI30
1Tl30A
ITI31

ITE2978
ITE2979
ITE3066
ITE3067
ITEJ068

1Tl20
1Tl20
2NJ685
2N3686
2N3687

JI77-18
J201
J201-18
J202
J202-18

JI77
J201
J201
J202
J202

K310-18
KE3684
KE3685
KE3686
KEJ687

J310
2NJ684
2N3685
2NJ686
2N3687

IT132
ITl36
ITI37
11138
1T139

1T132
1T136
ITI37
1T13S
ITI39

ITE3347
11E3348
ITE3349
ITE3350
ITE3351

1Tl37
1Tl38
ITl39
1T137
1Tl38

J203
J203-18
J204
J204-18
J210

J203
J203
J204
J204
2N5397

KE3823
KE3970
KE3971
KE3972
KE4091

2N3823
ITE4391
ITE4392
ITE4393
ITE4091

ITl40
1T1700
1T1701
1T1702
ITl750

1T140
1Tl7oo
3NI72
3NI63
IT1750

ITE3680
ITE3800
ITE3802
ITE3804
ITE3806

1Tl20
ITI32
ITI32
1T130
1T132

J211
J212
J230
J231
J232

2N5397
2N5397
2N4867
2N4868
2N4869

KE4092
KE4093
KE4220
KE4221
KE4222

ITE4092
ITE4093
2N5457
2N5459
2N5459

IT2700
IT2701
IT400
IT500
IT500P

3NI65
3NI65
2N4392
IT500
IT500

ITE3807
ITE3808
ITE3809
ITE3810
ITE381\

ITI32
1T132
ITI32
1T130
1Tl30

J270
J270-18
J271
J271-18
J300

J270
J270
J271
J271
2N5397

KE4223
KE4391
KE4392
KE4393
KE4416

J204
ITE4391
ITE4392
ITE4393
ITE4416

IT501
1T501P
lT502
IT502P
IT503

IT501
1T501
IT502
IT502
IT503

ITE3907
ITE3908
ITE4017
ITE4018
ITE4019

1T120
1T120
1T139
1T139
1Tl39

J304
J305
J308
J309
J310

2N5486
2N5484
J308
J309
J310

KE4856
KE4857
KE4858
KE4859
KE4860

ITE4391
ITE4392
ITE4393
ITE4391
ITE4392

IT503P
IT504
IT505
IT550
IT5911

IT503
IT504
IT505
IT550
IT5911

ITE4020
ITE4021
IT£4022
ITE4023
11£4024

1T139
1Tl39
ITI39
1T137
1T137

J315
J316
J317
J3970
J3971

2N5397
U309
U310
ITE4391
ITE4392

KE4861
KE510
KE5103
KE5104
KE5105

ITE4393
ITE4393
J204
ITE4416
ITE4416

IT5912
ITC2972
ITC2973
ITC2974
ITC2975

IT5912
IT122
1T122
ITI20
1T120

ITE4025
ITE4091
ITE4092
ITE4093
IT£41\7

1Tl37
ITE4091
ITE4092
ITE4093
2N41\7

J3972
J401
J402
J403
J404

ITE4393
IT501
IT502
IT503
IT503

KE511
KH5196
KH5197
KH5198
KH5199

ITE4392
2N5196
2N5197
2N5198
2N5199

ITC2976
ITC2977
ITC2978
ITC2979
ITC3347

1T120
1T120
1T120
ITI20
ITl37

ITE41\8
ITE4119
ITE4338
ITE4339
ITE4340

2N4118
2N41\9
2N4338
2N4339
2N4340

J405
J406
J4091
J4092
J4093

IT504
IT505
ITE4091
ITE4092
ITE4093

KS5183
KS5240BOIH
KS5240BOIJ
KS5240BIOH
KS5240BI2H

ICM7269
ICM7245B
ICM7245A
ICM7245D
ICM7245E

ITC3348
ITC3349
ITC3350
ITC3351
ITC3352

ITl38
ITI39
1Tl37
1T138
ITI39

ITE4341
IT£439I
ITE4392
ITE4393
ITE4416

2N4341
ITE4391
ITE4392
ITE4393
11£4416

J410
J41\
J412
J420
J421

IT502
IT503
IT503
IT591\
IT5912

KS5240B20H
KS5240UOIE
LDF603
LDF604
LDF605

ICM724SF
ICM7245U
2N4221
2N4221
2N4221

ITC3800
ITC3802
ITC3804
ITC3806
ITe3807

ITI32
ITI32
1T130
1T132
1T132

ITE4867
ITE4868
ITE4869
JlOO
JIOI

2N4867
2N4868
2N4869
2N5458
2N4338

J4220
J4221
J4222
J4223
J4224

J204
J202
J203
J202
J202

LFl I 201D
LFI\ 201 0/883
LF1\202D
LF 1\ 2020/883
LFl,IS080

IH202MJE
IH202MJE/883B
IH6108MJE

ITC3808
ITC3809
ITC3810
ITC3811
ITC4017

ITl32
1T132
ITI30
1T130
1T139

JI02
JI03
JI05
JI05-18
JI06

2N5457
2N5459
JI05
JI05
JI06

J430
J4302
J4303
J4304
J431

J309(X2)
2N4302
2N5459
2N5458
J310(X2)

LFI\ 5080/883
LF1\5090
LFI\509D/883
LFl320lD
LFl320lN

IH6108MJE/883B
IH6208MJE
IH6208MJE/883B
DG20lBK
DG20lCJ

ITC4018
ITC4019
ITC4020
ITC4021
ITC4022

1T139
ITI39
1T139
ITl39
In39

JI06-18
JI07
J107-18
Jl08
JI08-18

JI06
JI07
J107
J105
JI05

J433
J4338
J4339
J4391
J4392

2N5457
2N5457
2N5457
IT£439I
ITE4392

LF\3202D
LFI3508D
LF13508N
LFl3509D
LF13509N

IH202CJE
IH6108CJE
IH6108CPE
IH6208CJE
IH6208CPE

"CONSULT FACTORY

27

~~gl~~883B

."0,-

•

. A!LTEIINATE
SOURCE PRODUCT·

_.

!.INTERS.L
EQUIVALENT

. .ALTERNjl.TE
.
SOURCE PRODUCT

·"iTER.IL
EQUIVALENT

ALtEIlNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTEIISIL
EQUIVALENT

LH0042
LH210B
LH230B
LM105
LMlOB

LH0042
lH2108
LH2308
LM105
LM.l08

LTCI044
LTC1052
LTC7652
M103
MlO4

ICLl660
ICL7650
ICL7652
3N161
3N161

MDlOO3A
M07003B
M07004
M07007
M07007A

ITI32
1Tl32
1Tl29
1Tl29
ITI29

MEM807A
MEM814
MEM816
MEM817
MEM823

3Nl72
3N161
3Nl72
3N172
MFE823

LMl13
LM114
lM114AH
LM114H

ICL8069
!TI20
1Tl20A
ITI20A
1Tl20.

MlO6
M107
M108
Ml13
Ml14

3N166
3N189
3N191
3N161
3N161

M07007B
M0708
M0708A
M0708B
.M08001

1Tl29
1Tl29
1Tl29
IT129
ITI20

MEM954
MEM954A
MEM954B
MEM955
MEM955A

3N188
3N188
3N188
3N190
3N190

lM115
LMIlSA
LM115AH
LM1l5H
LM194

1T120
1Tl20A
1Tl20A
1Tl20
ITI20A

MIl6
Ml17
M119
M163
M164

MIl6
2N4351
3N161
3N163
3N164

MD8002
M08003
M0918
M0918A
MD918B

!TI20
1Tl22
1T122
ITI22
1Tl22

MEM95.5B
MF510
MFB03
MF818
MFE2000

3N190
2N4092
2N4338
2N4858
2N4416

LM305
LM308
LM394
LM4250
LS3069

LM305
LM308
1Tl20A
LM4250
2N5458

M5001
M511
M511A
M517
M58434P

ICM7269
3Nl72
3N172
3N163
ICM70380

M0982
M0984
MEFl03
MEFlO4
MEF3069

1Tl39
1Tl39
2N5457
2N5459
2N4341

MFE2001
MFE2004
MFE2005
MFE2006
MFE2007

2N4416
2N4093
2N4092
2N4091
2N4860

LS3070
LS3071
LS3458
LS3459
LS3460

2NS4S8
2N5458
J204
J204
J204

M58435P
M58436-001P
M58437-001P
MAl807
MA7809

!CMll15B
ICM7050G
ICM7070L
1Tl32
1Tl32

MEF3070
MEF3458
MEF3459
MEF3460
MEF3684

2N4339
2N4341
2N4339
2N4338
2N3684

MFE2008
MFE2009
MFE2010
MFE2011
MFE2012

2N4859
2N4859
2N4859
2N5433
2NS434

LS3684
LS3685
LS3686
LS3687
LS3819

2N3684
2N3685
2N3686
2N3687
2N5484

MAT-QIAH
MAT-01FH
MAT-01GH
MAT-QIH
MB101

ITI40·
1Tl40
1Tl40
1T140
ICM7245B

MEF3685
MEF3686
MEF3687
MEF3821
MEF3822

2N3685
2N3686
2N3687
2N3821
2N3822

MFE2012
MFE2093
MFE2094
MFE2095
MFE2133

2N5433
2N4338
2N4339
2N4340
2N4860

lS382 I
LS3822
LS3823
LS3921
LS3922

2N54S7
2NS458
2N5458
2N3921
2N3922

MBI03
MBlO5
MBlO7
MB108
MB143

ICM7245E
ICM7245U
ICM72450
ICM7245E
ICM7245A

MEF3823
MEF3954
MEF3955
MEF3956
MEF3957

2N3B23
2N3954
2N3955
2N3956
2N3957

MFE2912
MFE3002
MFE3003
MFE3020
MFE3021

2N5433
3N170
3N164
3N166
3N166

LS3966
LS3967
LS3968
LS3969
LS4220

ITE4416
ITE4416
ITE4416
ITE4416
J204

MB144
MB510
MB511
MB512
MB513

ICM7245F
ICMll15B
ICM7050H
ICM7050H
ICM7050G

MEF3958
MEF4223
MEF4224
MEF4391
MEF4392

2N3958
2N4223
2N4224
ITE4391
ITE4392

MFE4007
MFE4008
MFE4009
MFE4010
MFE4011

2N3686
2N3686
2N3685
2N2608
2N2608

LS4221
LS4222
LS4223
LS4224
LS4338

J202
J203
J202
J202
2N5457

MB521
MB522
MB531
MB533
M8541

ITS9068
ITS9068
ICM7050H
ICM7050H
ICM7052

MEF4393
MEF4416
MEF4856
MEF4857
MEF4858

ITE4393
ITE4416
2N4856
2N4857
2N4858

MFE4012
MFE823
MHW590
MJ41
MJ6

2N2609
ITI700
AD590
ICM1424C
ICM7220

LS4339
LS4340
LS434f
LS4391
LS4392

2NS457
2N5457
2N5458
ITE4391
ITE4392

MB542
M8le
MCC14440
MCC14483
M01l20

ICM7052
ICM7245U
ICM1424C
ICM72lO
1Tl22

MEF4859
MEF4860
MEF4861
MEF5103
MEF5104

2N4859
2N4860
2N4861
ITE4416
ITE4416

MKlO
MM450H
MM451H
MM4520
MM452F

2N4416
MM450H
MM451H
MM452J
MM452F

LS4393
LS4416
LS4856
LS4857
LS4858

ITE4393
ITE4416
ITE4091
ITE4092
1TE4093

M01l21
MOl122
MOl123
MOl129
M01l3Q

1Tl22
ITI22
1Tl39
1Tl29
1Tl39

MEF5105
MEF5245
MEF5246
MEF5247
MEF5248

ITE4416
ITE4416
2N5484
2N5486
2N5486

MM455H
MM550H
MM551H
MM5520
MM552F

MM455H
MM550H
MM5S1H
MM552J
MM552F

LS4859
LS4860
LS4861
LS5103
LS5104

ITE4091
ITE4092
ITE4093
2N5484
2N5485

M02218
M02218A
M02219
M02219A
M02369

1Tl29
1Tl29
tTI29
1Tl29
1Tl29

MEF5284
MEF5285
MEF5286
MEF5561
MEF5S62

2N5484
2N5485
2N5486
U401
U402

MM555H
MMFl
MMF2
MMF3
MMF4

MM555H
2N5197
2N3921
2N5198
2N3922

LS5105
LS5245
LS5246
LS5247
LS5248

2N5486
ITE4416
2N5484
2N5486
2N5486

M02369A
M02369B
M02904
M02904A
M02905

1T129
ITI22
1Tl39
In39
1Tl39

MEF5563
MEM511
MEM511A
MEM511C
MEM517

U403
3N172
3Nl72
3Nl72
3Nl72

MMF5
MMF6
MMT3823
MN6091
MN6092A

2N5199
2N3955A
2N3823
ICM7038B
ICM7038E

LS5358
LS5359
LS5360
LS5361
LS5362

J204
J204
J202
J202
J203

M02905A
M02974
M02975
M02978
M02979

1Tl39
1Tl20
1Tl20
1T120
1Tl20

MEM517A
MEM517B
MEM517C
MEM550
MEM550C

3Nl72
3Nl72
3N172
3N189
3N189

MN6093
MN6252
MP301
MP302
MP303

ICM70S1A
ICM7050G
ITl24
ITl24
ITI24

LS5363
LS5364
LS5391
LS5392
LS5393

J203
J203
2N4867A
2N4868A
2N4869A

M03008
M03250
M03250A
M03251
M03251A

1Tl20
1Tl32
1Tl31
1Tl32
ITl31

MEM550F
MEM551
MEM551C
MEM556
MEM556C

3N189
3N190
3N189
3Nl72
3Nl72

MP310
MP311
MP312
MP313
MP318

2N4045
2N4045
2N4044
1Tl24
ITI20A

LS5394
LS5395

LS5458

2N4869A
2N4869A
2N4)!6.9A
2NS457 .
2N5458

MD3409
M03410
M03467
M03725
M03762

1Tl29
1Tl29
ITl39
1Tl29
ITl39

MEM560
MEM560C
MEM561
MEM561C
MEM562

3N161
3Nl61
3N163
3N163
2N4351

MP350
MP351
MP352
MP358
MP360

ITI32
ITI30
1Tl30
1Tl30A
ITI32

LS5459
LS5484
LS5485
LS5486
LS5556

2N5459
2N5484.
2N5485
2N5486
2N3685

MD4957
MD5DOO
MD5DOOA
MD5DOOB
M07000

1Tl32
1Tl32
1Tl32
1Tl32
1Tl29

MEM562C
MEM563
MEM563C
MEM711
MEM712

2N43S1
2N4351
2N4351
M1l6
M1l6

MP361
MP362
MP3954
MP3954A
MP3955

ITl30A
1Tl30A
2N3954
2N3954A
2N3955

LS5557
LS5558
LS5638
LS5639
LS5640

2N3684
2N3684
2N5638
2N5639
2N5640

M07001
MD7002
M07002A
MD7002B
MD7003

1Tl39
1Tl22
1Tl22
1Tl22
ITl32

MEM712A
MEM713
MEM806
MEM806A
MEM807

M1l6
3N170
3N163
3N163
3Nl72

MP3956
MP3957
MP3958
MP5905
MP5906

2N3956
2N3957
2N3958
2N5905
2N5906

LM114~

tm~~.

"CONSULT FACTORY

..

,

28

INTEASIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

MPS907
MP5908
MPS909
MP5911
MP5912

2N5907
2N5908
2N59a9
2N5911
2N5912

NF4303
NF43a4
NF4445
NF4446
NF4447

2N5459
2N5458
2N5432
2N5433
2N5433

PF511
PF5301
PF5301-1
PF5301-2
PF5301-3

2N5114
2N4118A
2N4117A
2N4118A
2N4118A

SG3D5

5G308
5G4250
SG733
SI7135CPI

LM305
LM308
LM4250
UA733
ICl7135CPI

MP7520JD
MP7520JN
MP7520KD
MP7520KN
MP7520lD

AD7520JD
AD7520JN
AD7520KD
AD7520KN
AD7520lD

NF4448
NF500
NF501
NF506
NF5101

2N5433
2N4224
2N4224
2N4416
2N4867

PU091
PlI092
PlI093
Pl1094
PM308

2N3823
2N3823
2N3823
2N3823
LM308

517660
517661
5JM181BCC
SJMIBIBIC
5JM182BCC

ICL7660
ICL7662
JM38510/11101BCC
JM38510/11101BIC
JM38510/11102BCC

MP7520lN
MP7520SD
MP7520TD
MP7520UO
MP7521JO

AD7520lN
A0752050
AD7520TD
AD7520UD
AD752IJD

NF5102
NF5103
NF511
NF5163
NF520

2N4867
2N4867
2N4860
2N4341
2N3684

PN3684
PN3685
PN3686
PN3687
PN4091

2N3684
2N3685
2N3686
2N3687
ITE4091

5JM182BIC
SJM184B£C
5JM185BEC
5JM187BCC
SJM18781C

JM385101l1I02BIC
JM3851O/ll103BEC
JM38510/11104BEC
JM38510/11105BCC
JM38510/11105BIC

MP752lJN
MP7521KD
MP7521KN
MP75211D
MP7521LN

AD752lJN
AD7521KD
AD7521KN
AD7521LD
AD75211.N

NF521
NF522
NF523
NF530
NF5301

2N3685
2N3686
2N3865
2N4341
2N4118A

PN4092
PN4093
PN4220
PN4221
PN4222

ITE4092
ITE4093
J204
J202
J203

5JM188BCC
5JM188BIC
5JM190BEC
SJM191BEC
SL301AT

JM38510/11106BCC
JM38510/11106BIC
JM38510/11107BEC
JM3851O/ll108BEC
1Tl29

MP7521SD
MP752lTD
MP7521UO
MP7523JN
MP7523KN

AD7521SD
AD7521TD
A07521U0
A07523JN
AD7523KN

NF5301-1
NF5301-2
NFS301-3
NF531
NF532

2N4117A
2N4118A
2N4118A
2N4339
2N4341

PN4223
PN4224
PN4342
PN4360
PN4391

J204
J202
2N5461
2N5460
ITE4391

SL30IBT
5L301CT
5L301ET
SL360C
5L362C

1T129
1Tl29
ITl29
1T129
ITl29

MP7523LN
MP7621AD
MP7621BO
MP762lJN
MP762J KN

AD7523LN
AD7541AD
AD7541BD
AD754IJN
AD7541KN

NF533
NF5457
NF5458
NF5459
NFS484

2N4339
2N5457
2N:;458
2N5459
2N5484

PN4392
PN4416
PN4856
PN4857
PN4858

ITE4392
ITE4416
2N48S6
2N4857
2N4858

5M5011
5M5510
SM5530B
5U2000
5U2020

ICM7050G
ICMll15B
ICM7070P
2N4340
2N3954

MP7621S0
MP7621TD
MP804
MP830
MP831

AD7541SD
AD7541TO
2N5520
2N5520
2N5521

NF5485
NF5486
NF5555
NF5638
NF5639

2N5485
2N5486
2N5484
2N5638
2N5639

PN4859
PN4860
PN4861
PN5033
PTC151

2N4859
2N4860
2N4861
2N5460
2N5484

5U2021
5U2022
SU2023
SU2024
5U2025

2N3954
2N3954
2N3954
2N3954
2N3954

MP832
MP833
MPS35
MP836
MPS37

2N5522
2N5523
2N3954
2N3955
2N3955

NF5640
NF5653
NF5654
NF580
NF581

2N5640
2N4860
2N4861
2N5432
2N5432

PTC152
51424
SA2253
SA2254
SA2255

2N5485
ICM1424C
ITl22
ITl22
1T122

5U2026
5U2027
SU2028
5U2029
5U2029

2N3954
2N3954
2N3954
2NSI97
2N3954

MP838
MP839
MP840
MP841
MP842

2N3956
2N3957
2N5520
2N5521
2N5523

NF582
NF583
NF584
NF585
NF6451

2N5433
2N5434
2N5433
2N4859
U310

SA2644
SA2648
SA2710
SA271!
SA2712

1Tl20
ITI20
1T120
ITI20
1Tl21

5U2030
5U2030
SU2031
5U2031
5U2032

2N3955
2N3954
2N5198
2N3954
2N3954

MPFl02
MPFI03
MPFI04
MPF105
MPFl06

2N5486
2N5457
2N5458
2N5459
2N5485

NF6452
NF6453
NF6454
NKT80111
NKT80112

U310
U310
U310
2N4220
2N4220

SA2713
SA2714
SA271S
5A2716
SA2717

IT121
ITl22
1Tl20
ITl20
ITl21

SU2033
5U2034
5U2034
5U2035
5U2035

2N3954
2N3955
2N3954
2N3955
2N3954

MPFl07
MPFI08
MPFI09
MPFlll
MPF112

2N5486
2N5486
2N5484
2N5458
2N5458

NKT80113
NKT80211
NKT80212
NKT80213
NKT80214

2N3821
2N4339
2N4339
2N4339
2N4339

SA2718
SA2719
SA2720
5A2721
SA2722

ITl22
11120
11121
IT122
IT120

SU2074
5U2075
5U2076
SU20n
5U2077

2N3954
2N3954
2N3954
2N395S
2N3954

MPFl61
MPF208
MPF209
MPF256
MPF4391

2N5398
2N3821
2N3821
ITE4416
ITE4391

NKT80215
NKTS0216
NKTB0421
NKT80422
NKTB0423

2N4339
2N4339
2N4220
2N4220
2N4220

SA2723
SA2724
SA2726
SA2727
SA2738

1T121
ITI22
11122
11122
11120A

5U2078
SU2079
SU2080
5U2081
SU2098

2N3955
2N3955
U404
U404
2N5197

MPF4392
MPF4393
MPF820
MPF970
MPF971

ITE4392
ITE4393
J310
J175
J175

NKT80424
NPCI08
NPC211N
NPC212N
NPC213N

2N4220
2N5484
2N4338
2N4338
2N4338

SA2739
5CL54301
SClS478
50Flool
SDFlD02

1Tl20
ICM1424C
ICM7269
2N5432
2N5433

5U2098A
5U20988
SU2099
5U2099A
5U2365

2N5197
2N5196
2N5197
2N5197
2N3954

MPS5010
M5M5OOl
MSM5011
MSMS977
MTF}Ol

ICLB069
ICM7269
ICM1424C
ICM1424C
2NS484

NPC214N
NPC215N
NPC216N
NPD5564
NPD5565

2N4339
2N4339
2N4339
IT550
IT550

SOFlOD3
SOF500
SDF501
50F502
SOF503

2N5434
2N5520
2N5520
2N5520
2N5520

SU2365A
5U2366
5U2366A
5U2367
5U2367A

2N3954
2N3955
2N3955
2N3955
2N3955

MTFI02
MTFI03
MTFlO4
N05700
ND5701

2N5484
2NS4S7
2N5459
ITl20A
11120.!\

NP05566
NP08301
NP08302
NPD8303
OT3

IT550
2N3954
2N3955
2N3956
2N4338

SDFSQ4
SOF50S
50F506
SDF507
50F508

2N5520
2N5520
2N5520
2N5520
2N5520

5U2368
5U2368A
5U2369
5U2369A
5U2410

2N3956
2N3956
2N3957
2N3957
2N5907

ND5702
NDF9401
NDF9402
NDF9403
NDF9404

1Tl20
IT500
IT501
1T502
IT503

PlOO4
PlOO5
P1027
PI028
P1"029

2N5116
2N5115
2N5267
2N5270
2N5270

50F509
SOF51O
SDF512
SOF513
SDF514

2N5520
2N3954
2N3954
2N3954
2N3954

SU2411
5U2412
5U2652
5U2652M
5U2653

2N5908
2N5909
U401
U401
U401

NOF9405
NDF9406
NDF9407
NDF9408
NDF9409

IT504
IT500
IT501
1T502
IT503

PI069E
Pl086E
PI087E
P1117E
P1118E

2N2609
2N5115
2N5516
2N5640
2N5641

SDF661
50F662
SOF663
SES3819
SFT601

1Tl22
ITl22
11122
2N5484
2N4338

5U2653M
5U2654
SU26S4M
5U2655
5U2655M

U401
U401
U401
U402
U402

NDF9410
NE590
NE592
NF3819
NF4302

IT504
AD590
NE592
2N5484
2N5457

Pll19E
PF510
PF5101
PF5102
PF5103

2N5640
2N5115
2N4867
2N4867
2N4867

SFT602
SFT603
SFT604
5G105
5Gl08

2N4338
2N4339
2N4339
LM105
LMI08

5U2656
5U2656M
5X3819
5X3820
TC803lP

U404
U404
2N5484
2N260B
ICM7038A

"CONSULT FACTORY

29

':LTERNATE
SOURCE PRODUCT

IriTERSIL
EQUIVALENT

ALTERNATE
80URCE PRODUCT

'INTI!R8IL
EQUIVALENT

ALTERNATE
80URCE PRODUCT

INTER81L
I;QUIVALENT

ALTERNATE
80URCE PRODUCT

INTf;RSIL
EQUIVALENT

TC8032P

ICM7038F

T0710

1T122

U112

TC8051P
TC8052P
TC8056PA
TC8057P

ICM7038B
ICM7038E
ICMI115B
ICM70380

T0711
T07l3
TIS14
TlS25

1Tl22
ITl22
2N434O
2N3954

~m

Ul177
U1178

2N2608
2N2608
2N2608
2N4220
2N3821

U285
U290
U291
U295
U296

2N5454
2N5432
2N5434
2N5432
2N5434

TOl00
TOI0l
TOI02
T02CO
T0201

1Tl29
1Tl29
ITl29
1T129
1T129

TIS26
TIS27
TI534
TIS41
TlS42

2N3954
2N3955
2N5486
2N4859
2N4393

U1179
U1180
U1181
U1182
U1277

2N3821
2N4221
2N4220
2N3821
2N3684

U300
U3000
U3001
U3002
U301

2N5114
2N4341
2N4339
2N4338
2N5115

TD202
T02219
T0224
T0225
T0226

ITl29
1T129
ITl22
1Tl22
1T122

TI558
TIS59
TIS68
TlS69
TIS70

2N5484
2N5486
2N3955A
2N3955A
2N3956

U1278
U1279
U1280
U1281
U1282

2N3685
2N3686
2N3684
2N3822
2N4341

U3010
U3011
U3012
U304
U305

2N4341
2N4340
2N4338
U304
U305

T0227
T0228
T0229
T0230
T0231

ITl22
ITI22
ITl22
ITl21
1T121

TIS73
TIS74
TI575
TIS88
TIS88A

ITE4391 '
ITE4392
ITE4393
2N4416
2N4416

U1283
U1284
UI285
U1286
U1287

2N434O
2N4341
2N4220
2N4341
2N4092

U306
U308
U309
U310
U311

U306
U308
U309
U310
U310

T0232
T0233
T0234

TIXS33

T0236

ITl22
1T122
ITl22
ITl22
1T122

TIXS42

2N4392
2N4857
2N4391
2N4859
2N5639

Ul321
U1322
U1323
U1324
U1325

2N4860
2N3822
2N3822
2N3687
2N3686

U312
U314
U315
U316
U317

2N5397
2N5555
2N5397
U309
U310

T0237
T0238
T0239
T0240
T0241

1T122
1Tl22
1T122
1T121
1Tl21

TIXS59
TIXS78
TIXS79
TU82CL
TU82CN

2N5459
2N4341
2N4341
OGM182BA
OGM182CJ

U133
U1420
U1421
U1422
U146

2N2608
2N3821
2N3822
2N3822
2N2608

U320
U321
U322
U328
U329

2N5433
2N5434

T0242
T0243
T0244
T0245
T0246

ITl20A
1Tl20A
1Tl29
1Tl29
1Tl29

TL1821L
TU821N
TU82ML
TU85CJ
TU85CN

DGM182BA

OGM182CJ
OGM182AA
IH5045CJE
IH5045CPE

U147
U148
U149
U168
U1714

2N2608
2N2608
2N2609
2N2609
2N4340

U330
U331
U350
U401
U402

U401
U402

T0247
T0248
TD250
T02905
T0400

1Tl29
1T129
IH20A
In39
11139

TU851J
TU851N
TU85MJ
TUBSCL
TU88CN

IH5045CJE
IH5045CPE
IH5045MJE
IH5042CTW
IH5042CPE

U1715
U182
U183
U1837E
UI84

2N4340
2N4857
2N3824
2N5486
2N5397

U403
U404
U405
U406
U410

U403
U404
U405
U406
2N3955

T0401

TD402
TOSOO
T0501
T0502

ITl39
1Tl39
1Tl39
1T139
1Tl39

TU881L
TUBSIN
TU88ML
TLl91CJ
TU91CN

IH5042CTW
IH5042CPE
IH5042MTW
IH5043CJE
IH5043CPE

U1897E
U1898E
UI899E
UI97
UI98

U1897
U1898
U1899
2N4338
2N4340

U411
U412
U421
U422
U423

2N3956
2N3958
2N5908
2N5908
2N5909

T0509
T0510
T05l!
T0512
T0513

1Tl32
1T132
1T132
1Tl32
1Tl32

TU911J
TU911N
TU91MJ
Tl503
TL592

IH5043CJE
IH5043CPE
IH5043MJE
A0503
NE592

UI99
UI994E
U200
U20\
U202

2N4341
2N4416
2N4861
2N4860
2N4859

U424
U425
U426
U430
U431

2N5908
2N5908
2N5909
J309(X2)
J310(X2)

T0514
T0517
T0518
T0519
T0520

1T132
1T132
1Tl32
1T132
1T139

TlC555
TN4117
TN4117A
TN4118
TN4118A

ICM7555
2N4117
2N4117A
2N4118
2N4118A

U2047E
U221
U222
U231
U232

2N4416
2N4391
2N4391
U231
U232

U440
U441
UA105
UAI08
UA305

IT5911
IT5912
LMI05
LM108
LM305

T0521
T0522
T0523
T0524
T0525

1Tl39
1T139
ITl39
1T139
1T132

TN4119
TN4119A
TN4338
TN4339
TN4340

2N4119
2N4119A
2N4338
2N4339
2N4340

U233
U234
U235
U240
U241

U233
U234
U235
2N5432
2N5433

UA308
UA733
UCl00
UCIIO
UC115

LM308
UA733
2N3684
2N3685
2N434O

T0526
T0527
T0528
T05432
T05433

ITl32
1T131
ITl31
2N5432
2N5433

TN4341
TN5277
TN5278
TP5114
TP5115

2N4341
2N4341
2N4341
2N5114
2N5115

U242
U243
U244
U248
U248A

2N5432
2N5433
2N5433
2N5902
2N5906 '

UCI20
UCI30
UC155
UCI700
UC1764

2N3686
2N3687
2N4416
3N163
3N163

T05434
T0550
T05902
T05902A
T05903

2N5434
1T129
2N5902
2N5902
2N5903

TP5116
TSC426
TSC7106CJL
TSC7106CPl
TSC7106RCPL

2N5116
ICL7667
ICl7l06CJL
ICl7l06CPL
ICL7106RCPL

U249
U249A
U250
U250A
U251

2N5903
2N5907
2N5904
2N5908
2N5905

UC20
UC200
UC201
UC21
UC210

2N3686
2N3824
2N3824
2N3687
2N4416

T05903A
T05904
T05904A
T05905
T05905A

2N5903
2N5904
2N5904
2N5905
2N5905

TSC7107CJL
TSC7107CPL
TSC7107RCPL
TSC7109CPL
TSC7109IJL

ICL7107CJL
ICL7107CPL
,ICL7107RCPL
ICL7109CPL
ICL7109IJL

U251A
U252
U253
,U254
U255

2N5909
IT5911
IT5912
2N4859
2N4860

UC2130 '
UC2132
UC2134
UC2136
UC2138

2N5452
2N5453
2N5454
2N5454
2N5454

T05906
T05906A
T05907
T05907A
T05908

2N5906
2N5906
2N5907
2N5907
2N5908

TSC7109MJL
TSC7116CJL
TSC7116CPL
TSC7117CJL
TSC7117CPL

ICL7109MJL
ICL7116CJL
ICL7116CPL
ICL7117CJL
ICL7117CPL

U256
U257
U257/T0·71
U266
U273

2N4861
U257
U257/TO·71
2N4856
2N4118A

UC2139
UC2147
UC2148
UC2149
UC220

2N3958
2N3958
2N3958
2N3958
2N3822

T0590BA
T05909
T05909A
T05911
T059\1A

2N5908
2N5909
2N5909
IT5911
IT59\1

TSC7126CJL
TSC7126RCPL
TSC7135CJI
TSC7135CPI
TSC7650

ICL7126CJL
ICL7126RCPL
ICL7135CJI
ICL7135CPI
ICL7650

U273A
U274
U274A
U275
U275A

2N4118A
2N4119A
2N4119A
2N4119A
2N4119A

UC240
UC241
UC250
UC251
UC2766

2N4869
2N4869
2N4091
2N4392
3N166

T05912
TD5912A
T0700
T0701
T0709

IT5912
IT5912
1T122
ITl22
ITI22

TSC7660
TSC9491
TI·590
U110
U\lI

ICL7660
ICL8069
A0590
2N2608
2N2608

U280
U281
U282
U283
U284

2N5452
2N5453
2N5453
2N5453
2N5454

UC300
UC310
UC320
UC330
UC340

2N2608
2N2607
2N2607
2N2607
2N2607

TD235

"CONSULT FACTORY

TlXS35
TIXS36
TIXS41

30

2~5433

..
....
..

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

UC40
UC400
UC401
UC41
UC410

2N2608
2""5270
2N5116
2N2608
2N5268

UC420
UC450
UC451
UC588
UC703

2N5267
2N5114
2N5116
2N4416
2N4220

UC704
UC705
UC707
UC714
LJC714E

2"'14220
2N4224
2N4860
2N3822
2N4341

UC734
UC734E
UC751
UC752
UC753

2N4416
2N4416
2N4340
2N4340
2N4341

UC754
UC755
UC756
UC805
UC807

2N4340
2N4341
2N4340
2N5270
2N5115

UC814
UC851
UC853
UC854
UC855

2N5270
2N2608
2N2608
2N2608
2N2609

UCN-4111M
UCN-4112M
UCN-4113M
UHP-503
UPDl952P

lCM7038C
ICM7051A
ICM70388
AD503
ICM7220MFA

UPD1962C
UPD1963C
UPD815C
UPD816C
UPD820C

ICM7050G
ICM7050
ICM7038E
ICM70388
ICMl115B

UPD833G
UTlOO

ICM7223

unOI

ALTERNATE
SOURCE PRODUCT

INTERSIL
.EQUIVALENT

ALTERNATE
SOURCE PRODUCT

2N5397

UXC2910
VCRION

2N5397
1T126
2N4869

VCRllN
VCR12N
VCR13N
VCR20N
VCR2N

VNRllN
2N3958
2N3958
2N4341
VCR2N

VCR3P
VCR4N
VCR5P
VCR6P
VCR7N

VCR2P
VCR4N
VCR5P
VCR6P
VCR7N

VF28
VF811
YF8l5
VFW40
VFW40A

2N4392
2N4858
2N4858
lT122
1T120

YR-8069
W245A
W2458
W245C
W300

ICl8069
ITE4416
IT£4416
ITE4416
2N5398

W300A
W300B
W300C
W300D
WG-8038

2N5397
2N5397
2N5397
2N5398
ICl8038

WK5457
WK5458
WK5459
XR8038
ZD140

2N5457
2N5458
2N5459
ICl8038
1Tl29

ZDT41
ZDT42
ZOT44
ZDT45

IT129
1Tl29
1Tl29
1Tl29

"CONSULT FACTORY

31

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

Section 1 - Selector Guides

2.DISCRETES
Switches-Junction FET
N Channel
PART
NUMBER PACKAGE

rOS(ON)
n
Max

Vp
v
Min

IGSS

BVGSS

ID(OFF)

loSS

tap

Crss

ClsS

Max

pA
Max

V
Min

pA
Max

rnA
Min

ns
Max

pF
Max

pF
Max

-4.0
-2.0

8.0
-10.0
-5.0

-100
-250
-250

-50
-40
-40

250
250

50
25

150
75

6
25
25

High Isolation
High Isolation
High Isolation

-0.5

-3.0

-250

-40

250

5

30

50
90
180

3
6
6
6

25

High Isolation

-10.0
-10.0
-7.0
-7.0
-5.0
-5.0

-200
-40
-200
40
-200
40

-40
-50
-40
-50
-40
-50

200
200
200
200
200
200

30
30
15
15
8
8

65
65
95
95
140
140

5
5
5

5

16
16
16
16
16
16

High
High
High
High
High
High

55
75
100

3.5
3.5
3.5

14
14
14

High Isolation
High Isolation
High Isolation

34
60
120
34
60
120

8
8
8
8
8
8

18
18
18
18
18
18

High
High
High
High
High
High

Max

COMMENTS

2N3824
2N3970
2N3971
2N3972

TO-72
TO-18
TO-18
TO-18

250
30
60
100

" 2N4091
2N4091A
" 2N4092
2N4092A
" 2N4093
2N4093A

TO-18
TO-18
TO-18
TO-18
TO-18
TO-18

30
30
50
50
80
80

-5.0
-5.0
-2.0
-2.0
-1.0
-1.0

2N4391
2N4392
2N4393

TO-18
TO-18
TO-18

30
60
100

-4.0
-2.0
-0.5

-10.0
-5.0
-3.0

-100
-100
-100

-40
-40
-40

100
100
100

50
25
5

2N4856
2N4857
2N4858
2N4859
2N4880
2N4861

TO-18
TO-18
TO-18
TO-18
TO-18
TO-18

25
40
60
25
40
60

-4.0
-2.0
-0.8
-4.0
-2.0
-0.8

-10.0
-6.0
-4.0
-10.0
-6.0
-4.0

-250
-250
-250
-250
-250
-250

-40
-40
-40
-30
-30
-30

250
250
250
250
250
250

50
20.
8
50
20

2N4978

TO-18

20

-2.0

-8.0

-500

-30

500

15

55

8

35

Low rOS(ON)

2N5432
2N5433
2N5434

TO-52
TO-52
TO-52

5
7
10

-4.0
-3.0
-1.0

-10.0
-9.0
-4.0

-200
-200
-200

-25
-25
-25

200
200
200

150
100
30

41
41
41

15
15
15

30
30
30

Low rOS(ON)
Low rOS(ON)
Low rOS(ON)

2N5555

T0-92

150

-10.0

-lnA

-25

10nA

15

35

1.2

5

Low Cost

2N5638
2N5639
2N5640
2N5653
2N5654

T0-92
TO-92
T0-92
TO-92
TO-92

30
60
100
50
100

-12.0
-8.0
-6.0
-12.0
-8.0

-lnA
-lnA
-lnA
-lnA
-lnA

-30
-30
-30
-30
-30

lnA
50
lnA25
lnA
5
lnA
40
lnA
15

24
44
63
24
44

4
4
4
3.5
3.5

10
10
10
10
10

Low
Low
Low
Low
Low

ITE4091
ITE4092
iTE4093

TO-92
TO-92
TO-92

30
50
80

-5.0
-2.0
-1.0

-10.0
-7.0
-5.0

-200
-200
-200

-40
-40
-40

200
200
200

30
15
8

65
95
140

5
5
5

16
16
16

Low Cost
Low Cost
Low Cost

ITE4391
ITE4392
ITE4393

TO-92
TO-92
TO-92

30
60
100

-4.0
-2.0
-0.5

-10.0
-5.0
-3.0

-100
-100
-100

-40
-40
-40

100
100
100

50
25
5

55
75
100

3.5
3.5
3.5

14
14
14

Low Cost
Low Cost
Low Cost

Jl05
Jl06
Jl07
Jl08
Jl09
Jll0
Jlll
Jl12
Jl13
Jl14

TO-92
TO-92
TO-92
TO-92
TO-92
TO-92
TO-92
TO-92
TO-92
TO-92

3
6
8
8
12
18
30
50
100
150

-4.5
-2.0
-0.5
-3.0
-2.0
-0.5
-3.0
-1.0
-0.5

-10.0
-6.0
-4.5
-10.0
-6.0
-4.0
-10.0
-5.0
-3.0
-10.0

-3nA
-3nA
-3nA
-3nA
-3nA
-3nA
-lnA
-lnA
-lnA
-lnA

-25
-25
-25
-25
-25
-25
-35
-35
-35
-25

3nA
3nA
3nA
3nA
3nA
3nA
lnA
lnA
lnA
lnA

500
200
100
80
40
10
20
5
2
15

"
"
"
"
"
"

"Also available as JAN/JANTX & JANTXV
""Most TO-92's afe available lead formed to a TO-18 or TO-5 configuration

1-1

8

150
75
30
100
80
100
80

150
75
30

20
20
20
41
41
41
48
48
48
26

5
5

Isolation
Isolation
Isolation
Isolation
Isolation
Isolation

Isolation
Isolation
Isolation
Isolation
Isolation
Isolation

Cost
Cost
Cost
Cost
Cost

Lowest rOS(ON)
Lowest rOS(ON)
Lowest rOS(ON)
Low Cost
Low Cost
Low Cost
Lowest Cost
Lowest Cost
Lowest Cost
Low Cost

2. DISCRETES
Switches .... Junction FET
N Channel
rDS(ON)
PART
NUMBER

PACKAGE

Il
Max

vp.

IGSS'

V

pA

BVGSS

V

ID(017Fl

loss
rnA
Min

tap.
ns
Max

Cras

Clss

pF
Max

pF
Max

15
8

65
95
140

5
5
5

16
16
16

Low Cost
Low Cost
Low Cost

41
41
41

15
15
15

30

Lowest rOS(ON)
Lowest rOS(ON)
Lowest rOS(ON)

8
8

30
30

8

30

Low Cost
Low Cost
Low Cost

5
5
5

16
16
16

Low Cost
Low Cost
Low Cost

Min

Max

Max.

Min

pA
Max

-10.0
-7.0
-5.0

-200
-200
-200

-40
-40
-40

200
200
200

30

PN4091
PN4092
PN4093

10-92
TO-92
TO-92

50
80

-5.0
-2.0
-1.0

PN5432
PN5433
PN5434

TO-92
TO-92
TO-92

5
7
10

-4.0
-3.0
-1.0

-10.0
-9.0
-4.0

-200
-200
-200

-25
-25
-25

200
200
200

150
100
30

U200
U201
U202

TO-18
TO-18
TO-18

150
75
50

-0.5
-1.5
-3.5

-3.0
-5.0
-10.0

-InA
-1nA
-1nA

-30
-30
-30

InA
InA
1nA

3
15

U1897
UI898
UI899

TO-92
TO-92
TO-92

30

-5.0
-2.0
-1.0

-10.0
-7.0
-5.0

-400
-400

-40
-40
-40

200
200
200

30

50
80

-400

'Also available as JAN/JANTX & JANTXV
"Most TO-92's are available lead formed to a TO'18 or TO-5 configuration

1-2

30
30
15

8

Max

25
75
150
65
95
140

30

30

COMMENTS

DlL

2. DISCRETES
Switches-Junction FET
P Channel
PART
NUMBER

PACKAGE

rDS(ON)
fI
Max

Vp

IGSS

BVGSS

'D(OFF)

V
Min

Max

pA
Max

V
Min

pA
Max

loss
mA
Min Max

5.0
5.0
9.5

15nA
15nA
15nA

30
30
30

-2nA
-2nA
-2.5nA

-3-30
-15-30
-15-SO

9.5
5.5

1.2nA
1.2nA

25
25

-1.2nA
-1.2nA

-10
-2

12.0
7.0

2nA
2nA

30
30

-10nA
-10nA

-10

2N3382
2N3384
2N3386

TO·72
TO·72
TO·72

300
lSO

1.0
4.0
4.0

2N3993
2N3994

TO·72
TO·72

lSO
300

4.0
1.0

2NS018
2NS019

TO·18
TO·18

75
150

• 2N5114
• 2N5115
• 2N5116

TO·18
TO·18
TO·18

75
100
150

5.0
3.0
1.0

10.0
6.0
4.0

500
500
500

30
30
30

IT100
IT10l

TO-18
TO-18

75

60

2.0
4.0

4.5
10.0

200
200

J174
J175
J176
Jl77

TO-92
TO-92
TO-92
TO-92

125
2SO
300

5.0
3.0
1.0
0.8

10.0
6.0
4.0
2.25

PN5114
PN5115
PN5116

TO-92
TO-92
TO-92

75
100
lSO

5.0
3.0
1.0

U304
U305
U306

TO-18
TO-18
TO-18

85

5.0
3.0
1.0

180

85

110
175

tap
ns
Max

Crs•
pF
Max

C,••
Max

COMMENTS

16 typ Low rOS(ON)
16 typ Low rOS(ON)
16 typ Low rOS(ON)
4.5
4.5

16
16

-5

100
215

10
10

45
45

Low rOS(ON)
Low rOS(ON)

-500
-500

-30 -90
-15 -60
-5 -25

37
66
102

7
7
7

25
25
25

Low rOS(ON)
Low rDS(ON)
Low rOS(ON)

35
35

-100
-100

-20

12
12

35
35

TIL Compatible
TIL Compatible

lnA
lnA
lnA
lnA

30
30
30
30

-lnA
-lnA
-lnA
-lnA

-20 -100
-7 -60

45

-2 -25
-1.5 -20

90

10.0
6.0
4.0

500

30
30
30

-500
-500
-500

-30 -90
-15 -60
-5 -25

37
68
102

7
7
7

25
25
25

Low Cost
Low Cost
Low Cost

10.0
6.0
4.0

500

30
30
30

-500
-500
-500

-30 -90
-15 -60
-5 -25

70

105

7
7
7

27
27
27

High Off Isolation
High Off Isolation
High Offlsoiation

500

500
500
500

-500

• Also available as JAN/JANTX & JANTXV
"Most TO-92's are available lead formed to a TO-18 or TO-5 configuration

1-3

-10

22

Low Cost
Low Cost
Low Cost
TIL Compatible

70

140

·.·.B··~.·.<.··
.. ··>·.·."'.~.··.··.·:n.';0.,;;;;:"
;. :.:..·."·.·.......
; Stnb

'•
.
~.

2. DISCRETES
Switches and Amplifiers MOSFET
N·Channel
BVoss loss

9,.

loss

rO~ON)

PACKAGE

VGS(TH)
V
Min'

Max

ID(ON)
mA
Min

2N4351

TO-72

1.0

5.0

25

10nA

10

1000

300

3

High Input Z

3N170
3N171

TO·72
TO-72

1.0
1.5

2.0
3.0

25
25

10nA
10nA

10
10

1000
1000

200
200

10
10

. High Input Z
High Input Z

1T1750

TO-72

0.5

3.0

25

10nA

10

3000

50

10

M116
M117

TO-72
TO-72

1.0
1.0

5.0
5.0

30
30

lanA
10nA

100

PARJ
NUMBER

'Max

V
Min

pA
Max

pA
Max

"mho
Min'

ID(ON)
mA.·.
Max

COMMENTS

Low rOS(ON)
Diode Protected
High Input Z

lOQ
100

P·Channel
Generally used where max. isolation between signal.source and logic drive is required: switch "On" resistance varies with signal amplitude.

PART
NUMBER' PACKAGE

9,.

VGS(TH)
V
Min

BVoss
V
Min

loss

MIIIX

pA
Max

IGSS
pA
Max

I'mho
Min

rDS(ON)
0
Max

IIl(ON)
mA
Min

IIl(ON)
mA
Max

COMMENTS

2N4352·

TO-72

-1.0

-5.0

-25

-10nA

10

1000

600

":3

High Input Z

3N155
3N15SA
3N157
3N157A

TO-72
T0-72
TO-72
TO·72

-1.5
-l.S
-1.5
-1.5

-3.2
-3.2

-lnA
-250
-lnA
-250

10
10
10
10

1000
1000
1000
1000

600
300

-5

-5

-3.2

-35
-35
-35
-50

High
High
High
High

3N161
3Nl63
3N164

TO-72
TO-72
TO-72

-1.5
-2.0
-2.0

-5.0
-5.0
-5.0

-25
-40
-30

-10nA
-200
400

-100
-10
10

3500
2000
1000

3N172
3N173

TO-72
TO-72

-2.0
-2.0

-5.0
-5.0

-40
-30

-400

-200

-10nA

-500

IT1700
IT1701

T0-72
T0-72 .

-2.0
-2.0

-5.0
-5.0

-40
-40

200
200

100

-3.2

2000
2000

'-5
-5
-40

Input Z
Input Z
Input Z
Input Z

-3

-120
-30
-30

Diode Protected
High Input Z
High Input Z

250
350

-5
-S

-30
-30

Diode Protected
Diode Protected

400

-2
-2

250
300

-5

400

High Input Z
Diode Protected

Low Leakage Diodes
PART
NUMBER
10100
10101

PACKAGE

'R@ 1V
(PA)
Typ

IR@ 10 V, 125°C
(nA)
Max

BVR@ 1~
(V)
Min

TO-7S
TO-71

0.1
0.1

10
10

30
30

Note 1_ Used to protect the inputs of MOSFETs such as 3NI63, while maintaining input leakage < LM108

ISlAS
(pA Max)

SLEW
RATE
~/,..)

-

GBW
(MHz)

COMPEN·
SATION

VSUPPLY

EXT
INT

:20
:1:18
:1:9

~Mlx)

TEMPERATURE
RANGE
(OC)

Bipolar, Super·Beta
Bipolar, Super·Beta
CMOS, Selectable la

2.0
7.5
2,5,15

2000
50

1.6

1.0
1.0
1.4

•. ICL8007M
• ICL8007C

JFET Input Op-Amp
JFET Inpul Op-Amp

20
50

20
50

6
6

1.0
1.0

INT
INT

:18
:1:18

LH2108
LH2308
ICL7621

Bipolar, Super·Beta
Bipolar, Super·Beta
CMOS, Fixed la

2.0
7.5
2,5,15

2000
7000
50

--

EXT
EXT

0.16

1.0
1.0
0.48

INT

:1:20
:1:18
:1:9

ICL8043M
ICL8043C

JFET Input Op-Amp
JFET Input Op-Amp

20
50

20
50

6
6

1.0
1.0

INT
INT

:18
:1:18

ICL7631

CMOS, Selectable la

5,10,20

50

1.6

1.4

INT

:1:9

1

ICL7641

CMOS, Fixed la

5,10,20

50

1.6

1.4

INT

:1:9

~

VOUT

VSUPPLY

~Min)

~Max)

Vos
(mVMax)

ISlAS
(nA Max)

AVOL
(dB Typ)

TEMPRATURE
RANGE
(OC)

:26
:26

:32
:32

:12
:12

:18
:18

250
250
250

:26
:26

:32
:32
:32
:32

3.0
6.0
3.0
6.0
3.0
6.0
3.0
6.0

100
100
100
100
100
100
100
100

-55 to +125
-25 to +85
-55 to +125
-2510 +85
-55 to +125
-2510 +85
-55 to +125
-25 to +85

..

.!l
·c

g

T
j

Iq

VOS·
(mV MIX)

LM308
ICL7611

..~

AI
.;.fJil

DESCRIPTION

7000

EXT

-55 10 +125

~ to +70
to +70
-55 to +125
-55 10 +125
o to +70

1

-55 to +125
a to +70

1

Oto +70
-55 to +125
-55 to +125
Oto +70
Oto +70
-55 to +125

010 +70
-55 10 +125

Operational Amplifiers: High Output Current

TYPE

!

~

%

(i)

ICH8510M
iCH85101
ICH8515M
ICH85151
ICHB520M
ICHB5021
ICHB530M
ICHB5301

DESCRIPTION

Hybrid Amplifier
Hybrid Amplifier
Hybrid Amplifier
Hybrid Amplifier
Hybrid Amplifier
Hybrid Amplifier
Hybrid Amplifier
Hybrid Amplifier

lOUT
(A Min)
1.0
1.0
1.5
1.25
2.0
2.0
2.7
2.7

:25
:25
1-15

50

250
500
250

500

4. AMPLIFIERS

Operational Amplifiers: Low/Ultra.lowlnputOff$et Voltage

TYPE

e\":i

ICL7650C
ICL76501
ICL7850M

·.·1m

......

."

".

",'

I

DESCRIPTION

Vos
",VMilx)

AVos/AT
"'Vl°C)
(Max)

AVos/At
(ilVlmoiIIh)

(TyP)

(pA Max)

IBIAS

Gaw
(MHz)

VSUPPLY
(V Max)

TEMPERATURE
RANGE
(0C)

::t5
::t5
:1:5

::to.05
::to.05
::to.05

100
100
100

10
10
10

2.0
2.0
2.0

::t9
::t9
::t9

o to +70
-25 to +85
-55 to +125

:1:5
::t5

100
100

30
30
7000

2.0
2.0
1.0
1.0

::t9
::t9
:1:20
::t18

o to +70
-25 to +85
-55 to +125
o to +70

2000
7000

1.0
1.0

::t2O
::t2O

-55 to +125
010 +70

ICL7652C
ICL78521
LM108A
LM308A

CMOS, Chopper·
stabilized
CMOS, Chopperstabilized
Low-noise 7850C
Low-noise 76501
Bipolar, Super·Beta
Bipolar, Super·Beta

500
500

::to.05
::to.05
5.0
5.0

LH2108A
LH2308A

Bipolar, Super·Beta
Bipolar, Super·Beta

500
500

5.0
5.0

-

2000

Operational Amplifiers: Low Input Bias Current
TYPE

DESCRIPTION

IBIAS
(PA Max)

los

GaW
(MHz)

COM PEN·
SATION

VSUPPLY
(V Max)

TEMPERATURE
RANGE
(0C)

(PA Typ)

Vos '
(mV Max)

0.5

2,5,15

0.5
0.5

2,5,15

1.4
1.4

INT
INT

:1:9
::t9

2,5,15

1.4

INT

::t9

0.5

2,5,15

0.48

0.5

2,5,15

0.48

EXT
EXT

::t9

CMOS, Input Protected

50
50
50
,50
50

ICL8007M

JFET Input Op-Amp

20

0.5

20

1.0

INT

:1:18

-55 to +125

ICL8007AM

JFET Inpul, Low Bias

4.0

0.2

1.0

INT

::t18

-55 to +125

ICL8007C

JFET Input Op-Amp

50

0.5

1.0

INT

:l:1j!

010 +70

ICL.8007AC

JFET Input, Low Bias

4.0

0.2

1.0

INT

:1:18

Oto +70

ICH8500
ICH8500A

PMOS Input

0.1

0.7

INT

:1:18

-25 to +85

PMOS Input, Low Bias

0.01

30
50
30
50
50

0.7

INT

:1:18

-25 to +85

'I

ICL7621

CMOS, Fixed Ie

INT

:1:9

0.5

2,5,15
2',5,15

0.48

CMOS, Offset Null Pins

50
50

0.5

ICl7622

0.48

INT

:1:9

Oto +70
-55 to +125

ICL8043M

JFET Inpul Op-Amp

20

0.5

20

1.0

INT

:1:18

-55 to +125

ICL8043C

,JFET Input Op-Amp

50

0.5

50

1.0

INT

:1:18

"a!

ICl7631

CMOS, 'Selectable Ie

5,10,20

1.4

INT

:1:9

CMOS, Selectable Ie

50
50

0.5

ICl7632

0.5

5,10,20

1.4

NONE

:1:9

ICl7641

CMOS, Fixed Ie

5,10,20

1.4

INT

:1:9

CMOS, Fixed Ie

50
50

0.5

ICl7642

0.5

5,10,20

0.044

INT

:1:9

"

ID

fij

,

,

IC,L7611

CMOS, Selectable Ie

ICL7612

CMOS, Extended CMVR

ICL.7613

CMOS, Input Protected

ICL7614

CMOS, Fixed Ie

ICL7615

-

}

.» +~
,-55 to :125

:1:9

','

. "'.",

.".'
III

g

I'

1-16

}

o to +70
}

010 +70
-55 to !125

}

010 +70
-55 to !125

4. AMPLIFrERS

Commutating Auto-Zero (CAl) Instrumentation Amplifiers

TYPE

DESCRIPnON

Vos
{j.V MaX)

'Nos/aT
{j.V/"C)
(Max)

aVos/at
(nV/month)
(Typ)

IBIAS
(pA Max)

SIGNAL
BANDWIDTH
(Hz Max)

TEMPERATURE
RANGE

AVOL
(dB Typ)

(0C)

o

ICL7605C
ICL76051
ICL7605M

CMOS, Compensated
CMOS, Compensated
CMOS, Compensated

5.0
5.0
5.0

0.2
0.2
0.2

40
40
40

1500
1500
1500

10
10
10

105
105
105

to +70
-25 to +85
-55 to +125

ICL7606C
ICL7!l(l61
ICL7606M

CMOS, Uncomp911sated
CMOS, Uncompensated
CMOS, Uncompensated

5.0
5.0
5.0

0.2
0.2
0.2

40
40
40

1500
1500
1500

10
10
10

105
105
105

Oto +70
-25 to +85
-55 to +125

Logl Antilog Amplifiers

TYPE

DESCRIPnON

ICL8048BC
ICl.8048CC

Logarithmic Amplifier,
1V/Decade Output

ICL8049BC
ICL8049CC

. Antilog Ar:npllfler
1V/Decade Input

Vos
(mVMax)

aVOAJtlaT
(mV/"C)
(Typ)

DYNAMIC
RANGE
(dB)

30
60

25
50

0.8
0.8

120
120

±14
±14

±18
±18

10
25

25
50

0.38
0.55

60
60

±14
±14

±18
±18

ABSOLUTE
ERROR
(mVMax)

OUTPUT
SWING
(V Typ)

TEMPERATURE
VSUPPLY
(V Max)

RANGE
(OC)
Oto.+70

o to +70
o to +70
o to +70

Power Transistot Drive Amplifiers

TYPE

ICLB063M
ICL8063C

DESCRIPTION

Bipolar Monolithic
Driver Amplifier

lOUT
(mAMin)

VOUT
(V Min)

Vos
(mVMax)

AYOL
(VN)

+50/-25
+40/-20

±27V

50
75

6
6

IBIAS
Il

Differential
Inputs
~P-Compatlble,

ADC0804

t:

;

ICL711!>J/K

Differential
Inputs

DIGITAL
OUTPUT
FORMAT
8-Blt
Binary
8-Blt
Binary
8-Blt
Binary

~P-Compatlble,

816 Bits

High Speed
Converter

Ao Byte
Enable

INPUT
CONVERSION VOLTAGE OVERALL
SPEED (PS)
RANGE ACCURACY

-

114
(Max)

Oto +5.0V

114
(Max)

Oto +5.0V

-

114
(Max)

Oto +5.0V

-

40
(Max)

0.01% (J)
Oto +5.0V 0.006%(1<)
Oto -5.0V

1-21

TOTAL
. ERROR

GAIN
TEMP.
COEFF.

±'!J LSB

-

(Unadjusted) .
±Y. LSB
(Adjusted)

-

±H.SB
(Unadjusted)

-

+1 LSB

SUPPLY
VSUPPLY/
ISUPPLY

TEMP
RANGE
(0e)

+5V (Typ)
2.5mA(Max)

Oto +70
-40 to +85
-55 to +125

+5V (Typ)
2.5mA(Max)

o to +70
-40 to +85
-55 to +125

+5V (Typ)
2.5mA(Max)

o to +70
-40 to +85
-55 to +125

4 ppml"C +5V (Typ)
5 mA(Typ)

o to

+70

6. DATA ACQUISITION
Dlgltal·ta-Analog Converters (CMOS)
TYPE

I

AD7523

SPECIAL
FEATURES

Blnaryl
pp-Compatlble,
Offset
Low Power
Multiplying CAC Binary
~P-Compatlble,

SUPPLY

GAIN

VSUPPLY

LlNERITY

ISUPPLY

1.5% (Max)

10 ppm/oC
2 ppm/°C

+1SV (Typ)
'1oopA (Max)

o to +70
-25 to +85
-55 to +125

0.2% (J,A,S)
0.1% (I<,B,1)
0.05% (L,C,U)

0.3% (Typ)

10 ppm/°C
2 ppm/°C

+15V(Typ)
2mA(Max)

Oto +70
-25 10 +85
-55 to +125

:l:VREF A
10Kn
(Max)

0.2% (J,A,S)
0.1% (K,B,1)
0.05% (L,C,U)

0.3% (Typ)

10ppm/°C
2 ppm/oC

+15V (Typ)
2 mA(Max)

010 +70
-2510 +85
-55 to +125

:l:VREF A
10Kn
(Max)

0.2% (J,A,S)
0.1% (I<,B,1)
0.05% (L,C,U)

1.4% (Max)

10 ppm/°C
2 ppm/°C

+15V (Typ)
2mA(Max)

Oto +70
-25 to +85
-55 to +125

:l:VREF A
10Kn
(Max)

0.2% (J,A,S)
0.1% (I<,B,1)
0.05% (L,C,U)

0.3% (Typ)

10 ppm/"C
+15V (Typ)
2 ppm/°C , 2mA(Ma~)

010 +70
-25 to +85
-55 10 +125

0.2% (JA,S)
0.1% (K,B,1)
0.05% (L,C,U)

0.3% (Typ)

(Typ)

:l:VREF A
10Kn
(Max)

10 ppm/°C
2 ppm/°C

+15V (Typ)
2mA(Max)

010 +70
-2510 +85
-55 to +125

1,.s
(Max)

:l:VREF A
10Kn
(Max)

0.02% (J,A,S)
O.OW. (K,B,1)
0.01 % (L,C,U)

0.3% (Max)

'2 ppm/°C

+15V (Typ)
2mA(Max)

Oto'+70
-25 to +85
-55 to +125

3,.s
(Max)

:l:VREF A
7KO
(Max)

0.1 % (J,A,S) '0.02% (J)
0.006% (I<,B,1) 0.012% (K)
0.003% (l.,C,U) 0.006% (L)'

5 ppm/°C
1 ppm/°C

+5V (Typ)
0.5 mA (Max)

010 +70
-25 to +85
-55 to +125

200 ns
(Max)

500 ns

AD7530

Blnaryl
Same as '7520
But no leakage Offset
/leed thru specs Binary

500 ns

AD7533

"P-Compatlble,
Lowesl c;osl
1O-blt DAC

Binaryl
Offset
Binary

600 ns

~P-Compatlble,

500 ns

500 ns

8, 9, 10 Bit Lin.
Mulliplylng CAC

Ii

SfABILITY

SETTLING
nME
(TO
0.050/0 FS)

Binaryl
Offset
Binary

i AD7520

~.

DIGITAL
INPUT
FORMAT

i
•••••

Multiplying CAC

Blnaryl
Offsel
Binary

I

AD7531

Same as '7521
But nO leakage
/feed Ihru specs

Binaryl
Offsel
Binary

AD7541

pp-Compatlble,
High performanee CAC

Blnaryl
Offsel
Binary

AD7521

,~,

if AD7134

•••

:~:::

8, 9, 10 BII Lin.

Binaryl
"P-Compatlble,
Low power
2's
Multiplying CAC Complement

(Typ)

(Typ)

(Typ)

(Typ)

OUTPUT
VOLTAGE
CURRENT

NON LIN·
EARITY

GAIN
ERROR

:l:VREF A
10KO
(Max)

0.2% (J,A,S)
0.1% (I<,B,1)
0.05% (L,C,U)

:l:VREF A
10Kn
(Max}

Quad Current Switches For D/A Conversion (Singles or Matched Pairs)
TYPE

DESCRIPTION

ICL8018A

High precision current

ICL8019A

switches for use In
summing D/A converters

ICL8020A

ABSOLUTE
ERROR
(% Max)

ERROR
TEMPCO.
(pPM/"C Max)

:1:0.01
:1:0.10

:1:5
:1:25
:1:50

:1:1.00

1-22

VSUPPLY
(V Max)

ISUPPLY
(rnA Max)

:1:20-

10

:1:25

:1:20
10

:1:20

TEMPERATURE
RANGE
(0C)

~

010 +70

-55 to +125

TEMP
RANGE
(0C)

7. TIMER/COUNTER CIRCUITS
Timer/Counters With Display Drivers
DISPLAY
LED

FUNCTIONS
UNIT
COUNT

LCD VF

UNIVERSAL
COUNTERS

NUMBER
OF
DIGITS

TYPICAL APPLICATIONS
AND COMMENTS

TYPE

ICM7217
ICM7217A

•

ICM72178

•

• • •

•

•

• • •

•••

• •••
•••

2

•••

• • ••

2

•••

•

•

Industrial control: preset/predetermin·
ing counters, sequencers, on/off delay
timers, batch counters. Presets and
loads compare register from
thumbwheel switches

2

!i!
ICM7217C.
••
• ••
••••
2
Q.~---+~~~rr++++++~~~~~~~-------------i
=i
ICM7227
•
••
• •. •
••••
2
Microprocessor compatible interface.
ICM7227A
ICM7227B

I'.

ICM7~7C

•
•
•

ICM7224
ICM7224A

• •

•
•

•
•

•

•

• •••

•••••••
• ••••••

•
•••
•

••

•

2
2

•• ••

15

•

15

••

Industrial control: presel/predetermin.
ing counters, sequencers, onloff delay
timers, batch counters. Presets and
loads compare register from a
microprocessor

2

•

i..~•.t-'C_M_7_225
_ _-+_.+++_t-+-+-'-.+.:...r-t.++-+-++.+.+.+.++-+-+-_15_+.-I
•
!i ICM7225A.
•
•
• • • •
15
ICM7236

•

• ••

•

ICM7236A

•

•

•

•

• •

••••

15.

t------t-t-+-+-+-+-t-t-t-l-l-ll-+-+-+++-+--+-t-t-ll---t-l
!~.

•

ICM7249



CRYSTAL
FREQUENCY

PULSE
WIDTH

OTHER OUTPUTS/COMMENTS

ICM7213

t Pulse/Min

2-4

100

125,1000

4.19 MHz

1 PulseJSec, 2048, 1024, 34.133, 16 Hz

ICM7207A

0.5 Hz

4-5.5

260

1000,
0.391

5.24288 MHz

5 Hz, 1600 Hz (Note 1)

ICM7213

1 Hz

2-4

100

7.B

4.19 MHz

1 Pulse/Min, 2048, 1024, 34.133, 16 Hz

ICM7207A

5 Hz

4-5.5

260

100,0.391

5.24288 MHz

0.5,1600 Hz

ICM7207

5 Hz

4-5.5

260

100,0.312

6.5536 MHz

50 Hz, 1260 Hz

ICM7213

16 Hz

2-4

100

Sq. Wave

4.19 MHz

1 Pulse/Min, 2048, 1024, 34.133, 1 Hz

ICM7207

50Hz

4-5.5 '

260

20,0.312

6.5536 MHz

.5 Hz, 1260 Hz

ICM7213
ICM7213
ICM7207A
ICM7207

1000 Hz
1024 Hz
1260 Hz
1600 Hz

2-4
2-4
4-5.5
4-5.5

100
100
260
260

Sq. Wave
Sq. Wave
Sq. Wave
Sq. Wave

4.096 MHz
4.19 MHz
5.24288 MHz
6.5536 Mhz

2000, 2000 Pulses/Min

1 Pulse/Min, 2048, 34.133, 16, 1 Hz
0.5,5 Hz
5,50 Hz

ICM7213

204s Hz.

2-4

100

Sq. Wave

4.19 MHz

1 Pulse/Min, 1024,34.133,16, 1 Hz

ICM7209

25OkHz- '
10 MHZ

4.s.5.5

11,000

Sq. Wave

1-10 MHz

Note.:
1. Oscillator/controller for frequency counter.
2. Two buffered outputs"":Crystal Frequency and

+

B output. Drives up to 5 TTL loads.

1-24

(Note 2)

8. DISPLAY DRIVER
.

.OF
CHARACTERS
OR DIGITS

'

DISPLAY
TYPE

.

FEATURES AND
COMMENTS

INTERFACE

FONT

.D~D[6

TYPE

ICM7211
ICM7211A
ICM7211M
IGM7211AM

4
4
4
4

ICM7212
ICM7212A
ICM7212M
ICM7212AM

4
4
4
4

ICM7218A
ICM7218B
ICM7218C
ICM721BD
ICM7218E

8 8
8 8
8 8

ICM7231A
ICM7231B
ICM7231C

8 16
8 i6
8 16
10 20
10 20
10 20

ICM7232A
ICM7232B
ICM7232C
ICM7233A
ICM7233B

••
••

B 8
B 8

• ••
•
•

4
4

3
3
3
3
3
3
3
3
3

5
5
4
4
4
4

••

8

ICM7243A
ICM72438

8

•
••
•
•
••
•

•
• ••
••
•
•
••
•• ••
••
••

3

ICM7234A
ICM7234B
ICM7235
ICM7235A
ICM7235M
ICM7235AM

•
••
•

14

SO

7&
10

14

SO

16

200
200

1000
1000
200
200

•
•• •
•
•
•
•

••

•

1000

1000

•
•

•• •
•

•

•
•• • • ••
•• • • ••
• •
• •

550
550
500
500
500
500

Drives Conventional LCD Displays. Includes RC
Oscillator, Divider Chain, latches, Interface and LCD
Drivers. Evaluation Kit Available
Drives Common Anode LED Displays. 28 Current
Controlled Outputs. Includes latches, Interface and
Brightness 'Control. Evaluation Kit Available.
3 Decode Formats Drives UP to 64 Independent LED's .
Includes 8x8 Memory, Multiplexed LED Drivers,
Decoders, Interface and control. Applications Include
Bar Graphs.
'
B Digits, 16 Annunciators on COM 3, Hexadecimal

500
500
.350

B Digits, 16 Annunciators on COM 3, Code B

.350
.350

10 Digits, 20 AnnunCiators on COM 3, Code B

500
500
.350
.350

1000
1000
200
200

• •
• •

-

B Digits, 16 Annunicators on COM 1 + 3, Code B
10 Digits, 20 Annunciators on COM 3, Hexadecimal
10 Digits, 20 Annunciators on COM 1 + 3, Code B
4 Alphanumeric Characters. Evaluation Kit Available
4 Alphanumeric Characters. Full·Width Numbers
5 Alphanumeric Characters. Half·Width Numbers
5 Alphanumeric Characters. Full·Width Numbers
Drives 30 Volt Vacuum Fluorescent Displays Directly.
Includes Latch/Decoder ~P Interface or 4·Bit Inpul.
Hexadecimal or Code B Format Available.

250

8 Alphanumeric Characters + Decimal PI. can be Daisy
Chained or Cascaded. Evaluation Kit Available.

400

lxSO Ch. Dot Matrix LCD Controller' and Row Driver.
Use with ICM7281.

400

2x40 Ch. Dot Matrix LCD Controller and Row Driver.
Use with ICM7281.
Column Driver for use with ICM7280 or ICM7283.

'New Product

1-25

U~UI6

9. MICROCONTROLLERS, MICROPERIPHERALS, MEMORY

Microcontrollers, Microperipherals, Memory
Microcontrollers

8048/80C48 Family Compatible

6
6
6
6

2X the memory of IM80C48
Same as IM80C48 without ROM
Same as IM80C49 without ROM

Microprocessor Peripherals -

INTERNAL
MEMORY

fe ".
MHz

DESCRIPTION

(0C)

ROM

RAM

lK x 8
2Kx8
None
None

64x8
128 x 8
64 x 8
128 x8

PL,
PL,
PI.;
PL,

JL
JL
JL
JL

!

DESCRIPTION

(MHz)
Max

PACKAGE

loMj!Wo~·.".

I'P·Compatible Real·Time Clock, Binary Time
Format, Micropower Standby Operation (2,.A @ 2.8V)

4.19

PG,JG

IM6402
IM6402·1
IM6402A

CMOS' Industry Standard Compatible UART
High·Speed Version of IM6402
10VOperating Version of IM6402

1.0
2.0
4.0

PL
PL, JL
PL,JL'

2.46
3.58
6.0

PL
PL, JL
PL,JL

IM6403
IM6403·1
IM6403A

Like Corresponding IM6402
Device but with On·board Crystal
, Oscillator and Baud Rate Generator

1< 1_C43~"·'

0 - +70
-40 -

+85

CMOS I/O Expander for BOC4B/49 Microcompu.ters

TEMPERATURE
RANGE (OC)
-40 -

PG,JG

.......

IM4702/12

}

See also Display Drivers, Counters, AID, and D/A Converters.

fC

TYPE

TEMPERATURE
' RANGE

PACKAGE

Baud Rale Generator'

3.58

+85

}

-40,... +85

}

-40- +85

}

0- +70

PE,JE

-55 -

-55 -

+125

+125

-40- +85
-40- +85

CMOS EPROMs
ORGANIZATlONI
TYPE

MAX ACCESS
TIME(ns)

Vcc
(VI

IgcMAX(mA)
PERATING

Icc MAX (,.AI
STANDBY

PACKAGE

1024 x 4
IM66531
IM6653M
1M6853-11
IM6853A1
IM6853AM

550
600
450
300
350

5
5
5
10
10

6
6
6
12
12

140
140
140
140
140

JG
JG
JG
JG
JG

-40 -

512x 8
1M68541
IM6854M
IM66M-l I
IM6854AI
IM6854AM

550
600
450
300
350

5
5
5
10
10

6
6
6
12
12

140
140
140
140
140

JG
JG
JG
JG
JG

-40 -

* New Product

1-26

TEMPERATURE
RANGE (OC)

+85
+125
-40 - +85
,..40 - +85
-55 ~ +125

-55 -

-55 -40 -40 -

-55 -

+85
+125
+85
+85
+125

Section 2 -

Discretes

2N2607-2N2609
2N2609JAN
P-Channel JFET
General Purpose Amplifier
APPLICATIONS
•
•
•

CHIP

TOPOGR~PHY

Low-Level Choppers
Data Switches
Commutators

~

Z

(lcr2N2807,8)

5510

~

!

D(2)

l ~FUUR
,-_+-:II
.0017

~1)~~~T

PIN CONFIGURATION
TO·18

.0025 x'OO25

.0035

.0035

1-<0'"

:=

~~~

z

~

NOTE: SUBSTRATE
IS GATE

.013

5503

o

liE':}:,:

S

G,C

PC000111

f----, .016--1

NOTE: ~~i~ATE
CT005811

ABSOLUTE MAXIMUM RATINGS

ORDERING INFORMATION*
TO-18

WAFER

DICE

2N2607/W

2N2607/D

2N2608

2N2608/W

2N2608/D

2N2609

2N2609/W

2N2609/D

2N2607

2N2609JAN

-

(TA = 25°C unless otherwise noted)
Gate-Source Voltage ........... ,.,. , ..... , ................... 30V
Gate-Drain Voltage ............. , ... , .... , .. , ... ,............. 30V
Gate Current ......................... ,." ....... , ......... ", 50mA
Storage Temperature Range ............ -65°C to +200°C
Operating Temperature Range ... "",. -55°C to + 175°C
Lead Temperature (Soldering. 10sec) ..... , .. , ..... +30QoC
Power Dissipation ............. ,."" .. ", ... , ...... " ..... 300mW
Derate above 25°C.""."."""."".""". 2mW/oC

-

'When ordering waler/dice reler to Section 10, page 10-1,

ELECTRICAL CHARACTERISTICS

(@ 25°C unless otherwise noted)
2N2607

SYMBOL

PARAMETER

2N2609
UNIT

MIN

MAX

MIN

MAX

MIN

MAX

vGS - 30V, vos = 0

3

10

30

nA

VGS= 5V, VOS=O, TA=l50°C

3

10

30

p.A

IGSSR

Gate Reverse Current

BVGSS
Vp

Gate·Orain Breakdown Voltage

IG = 1p.A, VOS - 0

Gate·Source Pinch·Off Voltage

VOS=-5V, 10= -1p.A

30

lOSS

Drain Current at Zero Gate
Voltage

VOs= -5V, VGS=O

gl.

Small·Signal Common·SourCe
Forward Transconductance

VOS = -5V, VGS = 0, I = 1kHz

CiS&'

Common·Source Input
CapaCitance

VOS = -5V, VGS = lV, 1= lMHz
(Note I)

Noise Figure (Note 1)

VOS· -5V,
VGS=O,
I = 1kHz

NF

2N2608

TEST CONDITIONS

I RG= 10MU
I RG=lMU

NOTE 1: For design relerence only, not 100% tested.

2-1
Note: All typical values have been guaranteed by characteriZation and are not tested:

30

iJ

30

1

4

1

4

1

4

V

-0.30

-1.50

-0.90

-4.50

-2

-10

rnA

330

1000
10

2500

JJS

17

30

3

3

pF

3
dB

... 2N'3884.,2N3687 .

iz

i
zft

N~Char1nel

"JPET ,,' ,"
Low Noise Amplifier

FEATURES

APPLICATIONS

•
•
•

•
•
•
•

Low Noise
High Input Impedance
Low Capacitance

PIN CONFIGURATION

Low Level Choppers
Data Switches
Multiplexers
Low Noise Amplifiers

CHIP TOPOGRAPHY
5010

TO-72

0(2)

.0013 FULLR
.0017

~1) ~T
•

.0025 x .0025
.0035

~

,0035

:=~

-.l.NOTE: SUBSTRATE
IS GATE

.013

PC000211

CTOOO321

ORDERING INFORM'ATION*
TO-72

,WAFER

DICE

2N3684

2N3684/W

2N3684/D

2N3685

2N3685/W

2N3685/D

2N3686

2N3686/W

2N3686/D

2N3687

2N3687/W

2N36871D

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Gate-Source or Gate-Drain Voltage .................... -sOV
Gate Current , ................................................ 50mA
Storage Temperature Range ............ -65°C to +200°C
Operating Temperature Range ......... -55°C to + 175°C
Lead Temperature (Soidering, 10sec) .............. + 300°C
Power Dissipation .......................................... 300mW
Derate above 25°C .............. ; ........... 2.0mW I"C

'When ordering wafer/dice refer to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS (2S0C unless otherwise noted)
2N3684
SYMBOL

PARAMETER

BVGSS

Gate to Source Breakdown Voltage

Vos = 0, IG = 1.0pA

-50

Vp

Pinch-Off Voltage

VOS = 20V, 10 = O.OOlpA

-2.0

IGSS

Total,'Gate Leakage Current

IVlsl

Forward Transadmitlance

Gos

Common Source Output
Conductance

Ciss

Common

Source Input
CapaCitance

MAX

MIN

-5.0

-1.0

Vos =20V, VGS = 0
f= 1kHz

MIN

_3.5

-0.6

2N3687

MAX

MIN

-2.0

-0.3

-50
-0.1

-0,5
YGS = 0, VOS = 20V

MAX

-50
-0.1

' VGS = -30V, VOS = 0

I,TA = 150'C
Saturation CuO'ent, Drain·te-Source

2N3686

UNIT
MIN

"loss

2N3685

TEST CONDITIONS
-50
-0.1

-0,5

MAX
V

-1.2
-0.1

-0.5

nA

-0.5

pA

2:5

7.5

1.0

3.0

0.4

1.2

0.1

0.5

mA

2000

3000

1500

2500

1000

,2000

500

1500

iJS

50

25

10

5

iJS

4.0

4.0'

4.0

4.0

pF

VOS = 20V, VGS = 0
f=IMHz (Note 1)

1.2

1.2

1.2

1.2

pF
ohms

Crss

Common Source Short Circuit
Reverse Transfer Capacitance

rOS(on)

On Resistance

VOS = 0, VGS = 0

600

800

1200

2400

NF

Noise Figure (Note 1)

f = 100Hz, RG = 10M(/.
NBW = 6Hz, VOS = 10V,
VGS=OV

0.5

0.5

0.5

0.5

NOTE 1: For design reference only, not 100% tested.

2-2
Note: All typical values have been guaranteed by characterization, and are not tested.

dB

,

2N3810/A, 2N3811/A
Dual Matched PNP
General Purpose Amplifier
PIN CONFIGURATION

~

Z

CHIP TOPOGRAPHY

Co»
CD

......

4501
T0-78

~

f-033-1

~
.023

I

......L
EMITIEA
BASE

c,

B,

BASE .0030 )(

.0040

COLLECTOR

.0044
CTOOO4tl

ORDERING INFORMATION*
2N3810

WAFER

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Emitter-Base Voltage (Note 1) ............................. ~5V
Collector-Base or Collector-Emitter Voltage
(Note 1) .................................. , ................. -60V
Collector Current (Note 1) ................................ 50mA
Storage Temperature Range ....... , .... -'65°C to + 175°C
Operating Temperature Range ......... -55°C to + 175°C
Lead Temperature (Soldering, 10sec) .............. + 300°C
ONE SIDE
BOTH SIDES

DICE

2N3810/W

2N3810/D

2N3811/W

2N3811/D

2N3810A
2N3811

.0040

TYP 2 PLACES

PCOOO31 I

TO-78

.0030

TYP 2 PLACES

.0035 x .0034

.0045

E,

E"'TTER .0029 ,.JlO~
.0039
.0039
TVP 2 PLACES

2N3811A
'When ordering waferI dice refer to Section 10, page 10-1.

Power Dissipation .................... .
Derate above 25°C .............. ..

500mW
3.3mW/oC

600mW
4.0mW/oC

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: 25°C Ambient Temperature unless otherwise noted

SYMBOL

PARAMETER

2N3810/A

2N3811/A

MIN

MIN

UNIT

TEST CONDITIONS
MAX

BVceo

Collector-Base Breakdown Voltage

Ic = -10pA, IE = 0

-60

-60

BVCEO

Collector-Emitter Breakdown Voltage
(Note 2)

IC = -10mA, 18 = 0

-60

-60

BVEeO

Emitter-Base Breakdown Voltage

IE = -10pA, IC = 0

-5

-5

lC(off)

Collector Cutoff Current
ITA=+l50'C

IE(off)

hFE

Emitter Cutoff Current

Vce = -50V, IE = 0

Static Forward Current

VCE= -5V

Transfer Ratio
ITA = -55'C
VeE(sa!)

Base-Emitter Saturation Voltage

VCE(sa!)

Collector-Emitter Saturation Voltage

IC = -10pA

100

IC= -l00pA to -lmA

150

Ic = 10mA (Note 2)

125

IC = 100pA

75

V

-10

-10

nA

-10

-10

pA

-20

nA

-20

VeE = 4V, Ic = 0

MAX

225
450

300

900

250
150

VCE = -5V

le= -10pA

-0.7

IC= -100pA

Ie = -100pA

-O.B

-O.B

-0.2

-0.2

Ie = -10pA, Ic = -100pA

(Note 2)

le= -100pA, IC= -lmA

hie

Input Impedance (Note 4)

VCE = -10V

tit.

Forward Current Transfer Ratio (Note 4)

Ic= -lmA

hre

Reverse Voltage Transfer Ratio (Note 4)

f= 1kHz

hoe

Output Admittance (Note 4)

-0.7

-0.25

-0.25

3

30

10

40

150

600

300

900

0.25
5

2-3
Note: All typical values have been guaranteed by characterization and are not tested.

60

V

kn

0.25

5

60

,",S

2

:~

aN3,81o/A,:2N38111A'

=ELECTRICAL
I

,-..
C

o

=
I

CHARACTERISTICS (CONT.)
2N3810/A
,"A~AMETER

SYMBOL

2N3811/A
UNIT

TEST CONDITIONS
MIN MAX MIN MAX

Ihlel

Magnitude 01 small signal

Ilc= -lmA, f= looMHz

VCE= -5V

current gain (Note 4)

I

Ie = - SOOM,

Cobo

Output Capacitance (Note 4)

VCS = -SV, IE * 0, f= lMHz

Cibo

Input Capacitance (Note 4)

VCS

hFE1/hFE2

DC Current Gain Ratio

IVSE1-VSE2 I

Base-Emitter Voltage
Differential

IA devices

= -O.SV,

f = 30MHz

VCE = '-SV, IC - loollA

NF

Base-Emitter Voltage
Differential Gradienl

I A devices

Spot Noise Figure

5

1

4

4

8

0.9

1.0

0.9

8
1.0

0.95

1.0

0.95

1.0
-S

-2.5

-2.5

-3

-3

,-1.5

-l.S

10
5

10
5

VCE - -10V, Ic = -loollA, RG = 3ka,
f - 100Hz, Noise Bandwidth - 20Hz

7

4

VCE - -10V, Ic = -1001lA, RG = 3Ka,
f = 1kHz, Noise Bandwidth = 200kHz

3

1.5

VCE - -10V, Ic = -1001lA, RG - 3ka

2,5

1.5

3.5

2.5

VCE = -SV

I A devices

,n

1

-S

IC= loollA

.6.VSE1- VSE2

5

1

Ie = 0, f = 1MHz

IC = 10pA to, lOrnA

I A devices

1

VeE = -5, Ic

= 100""

f = 10kHz, Noise Bandwidth - 2kHz

(Note 4)

VCE = -10V, Ic = -1001lA, RG = 3ka,
Noise Bandwidth = 15.7kHz (Note 3)

NOTES: 1. Per transIstor.
2. Pulse,width" 3OOjAS, duty cycle" 2.0%.
3.. 3dB down at 10Hz and 10kHz:
4, For design reference only, not 100% tested.

2-4
Note: All typical values have ~n guaranteed by characterization and are not tested. '

pF

mV

pNrc

dB

2N3821, 2N3822,

JAN, JTX, JTXV

N-Channel JFET
High Frequency Amplifier
FEATURES

•
•

CHIP TOPOGRAPHY

Low Capacitance
Up to 6500l-ls Transconductance

2N3821

5010

j

PIN CONFIGURATION

.0013 FULL R
.0011

~1),,~~T

T0-72

.0025 x .0025
00350035

1--

~~~
:::

~

NOTE: SUBSTRATE
IS GATE

.013

5003
2N3822

o

T~._._
1
_

G,C
CTOO6501

.0025

ORDERING INFORMATION*
TO·72

WAFER

1--.016 4

.0025

NOTE: SUBSTRATE
IS GATE
CTOOO521

DICE

2N3821

2N3821/W

2N3821/0

ABSOLUTE MAXIMUM RATINGS

2N3822

2N3822/W

2N3822/0

(TA = 25'C unless otherwise noted)
Gate-Source Voltage ....................................... -50V
Gate-Drain Voltage ......................................... -50V
Gate Current ................................................ , 10mA
Storage Temperature Range ............ -65'C to + 200'C
Operating Temperature Range ......... -55'C to + 175'C
Lead Temperature (Soldering. 10sec) .............. + 300'C
Power Dissipation .. , ............... , .. , ...... ", ... " ..... 300mW
Derate above 25·C .......................... 2,OmW /"C

'When ordering waferI dice refer to Section 10, page 10-1.
tadd JAN, JTX, JTXV to basic part number to specify these devices.

ELECTRICAL CHARACTERISTICS

(25'C unless otherwise noted)
2N3821

SYMBOL

PARAMETER

UNIT
MIN

Gate Reverse Current

VGS = -30V, vos = 0

BVGSS

ITA=150·C
Gate-Source Breakdown Voltage
Gate-Source Cutoff Voltage

IG=-IjJ.A, VOs-O
VOS = 15V, 10 = 0.5nA

-50

VGS(off)

VOS = 15V, 10 = 50jJ.A

-0.5

IGSS

VGS

Gate-Source Voltage

losS

Saturation Drain Current (Note I)

2N3822

TEST CONDITIONS
MAX

2-5
Note: All typical values have been guaranteed by characterization. and are not tested.

0.5

MAX

-0.1

-0.1

-O.t

-0.1

nA
jJ.A

-50

-4
-2

Vos = 15V, 10 = 200jJ.A
Vos = 15V, VGS = 0

MIN

2.5

-6
V
-I

-4

2

10

mA

2Na821,'2N;t8~2, ~AN,

JTX, JTXV

,',

2N3821
SYMBOL

PARAMETER

MIN

MAX

4500

3000

6500

I-1kHz

1500

IYlsl

Common-Source Forward
Transadmittance (Note 2)

1= 100MHz

1500

gos

Common-Source Output
Conductance (Note 1)

C;•• '

Common-Source Input
Capacitance (Note 2)

Crss

Common-Source Reverse Transler
Capacitance (Note 2)

NF

Noise Figure (Note 2)

NOTES:

Vos

s

15V, VGS = 0

1= 1kHz

3000
10

20

6

,'6

3

3

5

5

dB

200

200

nV
-y11z

1. These parameters are measured dunng a 2ms Interval lOOms after DC power IS applied.
2. For design reference only, not 100% tested.

2-6

pF

1= 10Hz

VOS = 15V, VGS = 0,
BW= 5Hz

Note: All typical values have been guaranteed by characterization and 'are not tested.

"

/.IS

1-1MHz
VOS - f5V, VGS = 0,
Rgen - 1meg, BW = 5Hz

"

UNIT,
MAX

Common-Source Forward
Transconductance (Note 1)

Equivalent Input Noise Voltage
(Npte 2)

"

MIN
~

en

2M3822

TEST CONDITIONS

2N3823,JAN, JTX, JTXV

N-Channel JFET
High Frequency Amplifier
FEATURES
•
•
•

CHIP TOPOGRAPHY

Low Noise
Low Capacitance
Transductance Up to 6500MS

.0035 FUlLR

5000

.0025

~- r

T \,

PIN CONFIGURATION

~~~~ T

.017

~

TO-72

,0035 x .0035

:0025 -:oo2s

.0066
NOTE: SUBSTRATE
~0062~
IS GATE

.017

CT00061I

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Gate-Source or Gate-Drain Voltage .................... -30V
. Gate Current ................................................. 10mA
Storage Temperature Range ............ -65°C to +200°C
Operating Temperature Range ......... -55°C to + 175°C
Lead Temperature (Soldering, 10sec) .............. + 300°C
Power Dissipation ......................................... 300mW
Derate above 25°C .......................... 2.0mW 1°C

PCOOO201

ORDERING INFORMATION*

'When ordering wafer/dice refer to Section 10, page 10-1.
tadd JAN,JTX,JTXV to basic part number to specify these devices

ELECTRICAL CHARACTERISTICS
SYMBOL

(25°C unless otherwise noted)

PARAMETER

TEST CONDITIONS

IGSS

Gate Reverse Current

BVGSS

Gate-Source Breakdown Voltage

IG

VGS(off)

Gate-Source Cutoff Voltage

VOS = 15V, 10 = 0.5nA

VGS

Gate,Source Voltage

VOS = 15V, 10 = 400pA
VOS

I

TA=150·C

MIN

VGS = -20V, Vos = 0

= lpA,

UNIT

-0.5

nA

-0.5

pA

-8

V

-30

VOS = 0

= 15V,

MAX

-t.O

=0

-7.5

loSS

Saturation Drain .Current

4

20

Sts

Common-Source Forward
Transconductance (Note 1)

f= 1kHz

3,500

6,500

IVlsl

Common-Source Forward
Transadmittance (Note 2)

f = 100MHz

3,200

gos

Common-Source Output
Transconductance (Note 1)

f= 1kHz

gis.

Common-Source Input
Conductance (Note 2)

goss

Common-Source Output
Conductance (Note 2)

C;ss

Common-Source Input
CapaCitance (Note 2)

Crss

Common-Source Reverse
Transfer Capacitance (Note 2)

NF

Noise Figure (Note 2)

NOTES:

VGS

35

rnA

p.s

800

VOS = 15V, VGS = 0
f

= 200MHz
200
6
pF

f=IMHz
2
VOS = 15V, VGS
RG= lk!1

=0

f= 100MHz

1. These parameters are measured dunng a 2ms ,nterval lOOms after DC power ,s applied.
2. For design reference only, not 100% tested.

2-7
Note: All typical values have been guaranteed by characterization and are not tested.

2.5

dB

!

2,N3824,

N

Switch

"

-; N~hannel JFET
FEATURES
•

rds < 250 Ohms

•

10(Off)

CHIP TOPOGRAPHY
5003

< 0.1nA

PIN CONFIGURATION

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Gate-Source or Gate-Drain Voltage .................... - 50V
Gate Current ................................................. 10mA
Storage Temperature Range ............ -65°C to +200°C
Operating Temperature Range ......... -55°C to + 175°C
Load Temperature (Soldering. 10sec) .............. + 300°C
Power Dissipation ......................................... 300mW
Derate above 25°C ...................... ; ... 2.0mW 1°C

PC000201

ORDERING INFORMATION*

'When ordering waferI dice refer, to Section 10. page 10-1.

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS' 25°C unless otherwise noted
LIMITS
SYMBOL

PARAMETER "

TEST CONDITIONS

,.

I

IGSS

Gate Reverse, Current,

BVGSS

Gate-Source Breakdown Voltage

10(af!)

Drain Cutoff Current

TA = 150·C

VGS

= -30V.

VOS = 0

TA=150·C

VOS = 1.5V. VGS = ,-BV

rds(on)

Drain-Source ON Resistance

VGS=OV.lo=O

CiSS

Common-Source Input Capacitance
(Note 1)

VOS = 15V. VGS = 0

Crss

Commol)-Source Reverse
(Note 1)

f= 1kHz

VGS = -BV. VOS = 0

NOTE 1: For design reference only, not 100% tested.

2~

Note: All typical values have been guaranteed by characterization and are nol tested.

-0.1

nA

-0.1

IJ.A
V

"

0.1

nA

0.1

IJ.A

250

S1

6
f=lMfo!,z

Capacitance

MAX

-50

IG= llJ.A. VOs=O

I
Tran~9r

UNIT
MIN

pF

"

3

2N3921, 2N3922
Dual N-Channel JFET
General Purpose Amplifier
FEATURES
•
•
•

CHIP TOPOGRAPHY

Low Drain Current
High Output Impedance
Matched VGS. AVGS. and gfs

6037

1+--.025--1

PIN CONFIGURATION
TO-71
s,-

.!~itll;; t

D'.~S.
,COPR

__

..

G,

ALL BONO PADS ARE 4 x '" MIL.
CTOOO71!

ABSOLUTE MAXIMUM RATINGS
(TA = 2S0C unless otherwise noted)
Gate-Source or Gate-Drain Voltage (Note 1) ........ -SOV
Gate Current (Note 1) ..................................... SOmA
Storage Temperature Range ............ -6SoC to +200°C
Operating Temperature Range ......... -SSoC to +200°C
Load Temperature (Soldering, 10see) .............. + 300°C
Total Power Dissipation ................................. 300mW
Derate above 2SoC .......................... 1.7mW/oC

PC00051I

ORDERING INFORMATION*
TO·71

WAFER

DICE

2N3921

2N3921/W

2N3921/D

2N3922

2N3922/W

2N3922/D

'When ordering wafer/dice refer to Section 10, page 10--1.

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: (2S0C unless otherwise noted)
PARAMETER

SYMBOL

TEST CONDITIONS

I

IGSS

Gate Reverse Current

BVOGO

Drain-Gate Breakdown Voltage

10=lpA,ls=0

TA -100·C

MIN

VGS = -30V, VOS = 0

VGS(olf)

Gate·Source Cutoff Voltage

VOS = 10V, 10 = InA

VGS

Gate·Source Voltage

VOS = 10V, 10 = 100pA

IG

Gate Operating Current

10S$

Saturation Drain Current (Note 1)

gfs

Common·Source Forward
Transconductance (Note 2)

90S

Common-Source Output Conductance

Ciss

Common·Source Input CapaCitance (Note 3)

Crss

Common·Source Reverse Transfer CapaCitance
(Note 3)

9fs

Common-Source Forward Transconductance

gas.

Common·Source Output Conductance

NF

Spot Noise Figure
(Note 3)

MAX

UNIT

-1

nA

-1

pA

-3

V

50
-0.2

-2.7
-250

I

TA = 100·C

VOG = 10V, 10 = 700pA
Vos -10V, VGS - 0

nA

1

10

rnA

1500

7500

f=lkHz
VOS

= 10V,

pA

-25

35

VGS = 0

!,S

18
pF
f-1MHz

6
1500

VOG = 10V, 10 = 700pA

f= 1kHz

VOS = 10V, VGS = 0

f= 1kHz,
RG = lmeg

2-9
Note: All typical values have been guaranteed by characterization 'and are not tested.

20

!,S

2

dB

·'i

2,N;J921 •.. 2N392~

;

MATCHING CHARACTERISTICS'

tt

;:=z
tt

. .D~DIL
.

2N3921
SYMBOL

PARAMETER

UNIT
MIN

IVGS1- VGS21

Differential Gate-Source Voltage

AlvGS1- VGS2 1

Gate~Source

AT
91.1/9182

Differential Voltage
Change with Temperature

2N3922

TEST CONDITIONS
MAX

MIN

5
VOG= 10V.
10 = 700p.A

TA=O'C
Ts = 100'C
f-lkHz

Transconductance Ratio

NOTES: 1. Per transistor.
2. Pulse test duration =,.2 ms.
3. For design reference ~nly, not 100% tested.

2-10
Note: All typical values have been guaranteed by characterization and are not tested.

10
0.95

1.0

0.95

MAX
5

mV

25

/lVrC

1.0

2N3954-2N3958
2N3954A/2N3955A
Dual N-Channel JFET
G.eneral Purpose Amplifier
FEATURES
•
•
•
•
•

CHIP TOPOGRAPHY

Low Offset and Drift
Low Capacitance
Low Noise
Superior Tracking Ability
Low Output Conductance

N

Z

6037

W
G

!

1·- -.025,,---1

PIN CONFIGURATION

ii
zW

:_'F.l

TO-71

.....

_

G
UI

I:

t

G.

'ALL BOND PADS ARE"

II: "

MIl.

CTOO0811

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Gate-Drain or Gate-Source Voltage .................... -50V
Gate-to-Gate Voltage ................... : .................... ±50V
Gate Current ..................................,' .............. 50mA
Total Device Dissipation 85°C (Each Side) ........ 250mW
Case Temperature
(Both Sides) ........ 500mW
Power Derating (Each Side) ...................... 2.8SmWI"C
(Both Sides) ....................... 4.3mW I"C
Storage Temperature Range ............ -S5°C to +200°C
Lead Temperature (1/1S" from case
for 10 seconds) .......................................... 300°C

PC000501

ORDERING INFORMATION*
TO-71
2N3954

2N3954/W

2N3954A

2N3954A/W

2N3954A1D

2N3955

2N3955/W

2N3955/D

2N3955A

2N3955A/W

2N3955A1D

2N3956

2N3956/W

2N3956/D

WAFER

DICE
2N3954/D

2N3957

2N3957/W

2N39571D

2N3958

2N3958/W

2N3958/D

'When ordering wafer/dice refer to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

(25°C unless otherwise noted)

TEST CONDITIONS

2N3954

2N3954A

2N3955

2N3955A

2N3956

2N3957

2N3958

UNIT

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
Gate Reverse Current
IGSS

BVGSS

VGS = -30V,
I TA = 125°C Vos=O
Gate-Source
Vos-O
Breakdown Voltage
IG = -lIlA

-10

-10

-lOi

-IOi

-10e

-10

-10

pA

-50

-50

-SOi

-50

-5OC

-50

-50

nA

-50

-50

-50

-50

-50

-50

-50

VGS(Off)

Gate-Source Cutoff
Voltage

Vos = 20V,
10= lnA

VGS{o

Gate-Source Forward
Voltage

Vos=O
IG=lrnA

VGS

Gate-Source Voltage

Vos = 20V

Gate Operating Current

Vos = 20V,

-50

-50

-50

-50

-50

-50

-50

ITA = 125°C 10 = 2001lA

-25

-25C

-25C

-25

-25

-25

-25C

nA

5.0

rnA

IG

loss

Saturation Drain
Current

-1.0 -4.5 -1.0 -4.5 -1.0 -4.5 -1.0 -4.5 -1.0 -4.5 -1.0 -4.5 -1.0 -4.5
V
110 = 501lA

Vos = 20V,
VGs=O

110 = 2001lA

2.0

2.0

2.0

2.0

2.0

2.0

2.0

_4.2

-4.2

-4.2

-4.2

-4.2

-4.2

-4.2

-0.5 -4.0 -0.5 -4.0 -0.5 -4.0 -0.4 -4.0 -0.5 -4.0 -0.5 -4.0 -0.5 -4.0

0.5

5.0

0.5

2-11
Note: All typical values have been guaranteed by characterization and are not tested.

5.0

0.5

5.0

0.5

5.0

0.5

5.0

0.5

5.0

0.5

pA

2

j

2Na'5"'2",a9'~ ~":I954A/2N3955A .

'f')

ELECTRICAL .CHARACTERISTICS (CONT.)

:.....

I
C
J

•

I

:IG»

;

i
f')

z
C\I

SYMBOL

' . '

PARAMETER

TEST CONDITIONS

Common-Source Forward

~

Tranaconductance

g""

Coinmon-Source' OutPut
Conductance

q.

Common-Source Input
Capacitance (Note 2)

C...

Common Source Reverse
Transfer Capscitance
(Note 2)

Cdgo

Drain-Gate Capscitance
. (Note 2)

NF

Common-Source Spot .'
Noise Figure .
(Note 2)

lim -la2 1

Differential Gate C~rreni

loss,IIoss2

Drain Saturation
Current Ratio

(Note 2)
Vos = 2OV,
Vas=O

20V,
10 - 200pA
Vos=20V
VGS.=O

Gate-Source Differe.ntial

aT
g';',Ig.",

Voltage Change With
Temperature
Transconductance Ratio

Vas - 20V,
10= 200pA

2N3955A· 2N.395&

2N3957

2N3958

1000

1000

1000

1000

1000

1000

UNIT

1000

I'S
35

35

35

35

35

35

35.

4.0

4.0

4.0

4.0

4.0

4.0

4.0

1.2

1.2

1.2

1.2

1.2

1.2

1.2

1.5

1.5

1.5

1.5

1.5·

1.5

1.5

I = 100Hz

0.5

0.5

0.5

0.5

0.5

0.5

0.5

dB

T -125'C

10

10

10

10

10

10

10

nA

pF

0.95 1.0 0.95 1.0 0.95 1.0 0.95 1.0 0.95 1.0 0.90 1.0 0.85 1.0

IVaS,-vGS2 1 Differential Gate-Source
Voltage

alvGS,-v... 1

2N3955

1-200MHz
1= 1kHz

VDG= 10V,
1.-0

Vos -

2N3954A

I-1kHz

l=lMHz

Vos-20V
V... -O
. Ra=lOMf!

2N3954

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
1000 3000 1000 3000 1000 3000 1000 3000 1000 3000 1000 3000 tOOO 3000

5.0

5.0

10.0

5.0

15

20

25

T=2S'C to
-55'C

0.8

0.4

2.0

1.2

4.0

6.0

8.0

T-25'Cto
125'C
I-1kHz

1.0

0.5

2.5

1.5

5.0

7.5

10.0

0.97 1.0 0.97 1.0 0.97

NOTES: 1. Per Transistor.

.
2. For design reference only, not 100% tested,

2-12
Note: All typiCal values have been guaranteed by characterization and !!fe not tested.

1.0

0.95 1.0 0.95 1.0 0.90 1.0 0.85 1.0

mV

2N3970-2N3972

N-Channel JFET Switch
FEATURES

CHIP TOPOGRAPHY

•
•

Low rDS(on)
ID(OFF) < 250pA

•

Fast Switching

SOOl
.00135 FULL RADIUS
.00l75 (DRAIN)

PIN CONFIGURATION
TO·18

x

I--- --I
.016

.OO3~

.0026

(SOURCE)
CT000911

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Gate-Source or Gate-Drain Voltage .................... -40V
Gate Current ................................................. 50mA
Storage Temperature Range ............ -65°C to +200°C
Operating Temperature Range ......... -55°C to +200°C
Lead Temperature (Soldering. 10sec) .............. + 300°C
Power Dissipation ............................................ 1.SW
Derate above 25°C ........................... 10mW/oC

o
PC000611

ORDERING INFORMATION*
TQ-18

WAFER

DICE

2N3970

2N3970/W

2N3970/D

2N3971

2N3971/W

2N3971 10

2N3972

2N3972/W

2N3972/D

·When ordering wafer I dice refer to Section 10·, page 10-1.

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: 25°C unless otherwise noted
2N3970
SYMBOL

PARAMETER

2N3971

2N3972

TEST CONDITIONS

UNIT
MIN MAX MIN MAX MIN MAX

BVGSS

Gate Reverse Breakdown Voltage

1000

Drain Reverse Current

10(0f!)

Drain Cutoff Current

ITA ~ 150·C
iTA

= 150·C

VOG = 20V, IS = 0
VOG = 20V, VGS = -12V

VGS(Of!)

Gate·Source Cutoff Voltage

Vos = 20V, 10 = lnA

loSS

Saturation Drain Current
(Pulse width 300l'S, duty cycle::; 3%)

VOS = 2OV, VGS = 0

VOS(on)

Drain·Source ON Voltage

VGS=O

-40

-40

IG = -lIlA, VOS = 0

-40
250

2SO

pA

500

500

SOO

nA

250

250

2SO

pA

500

500

nA

-4

-10

-2

-5

-0.5

500
-3

50

150

25

75

5

30

10= 5mA
1.5
30

60

100

30

60

100

25

25

25

6

6

6

RL

10

15

40

450.11

10

15

40

30

60

100

Static Drain·Source ON Resistance

VGS=O, 10= lmA

rels(on)

Drain·Source ON Resistance

VGS=O, 10=0

Ciss

Common·Source Input Capacitance

VOS = 20V, VGS = 0 (Note 1)

Cr••

Common·Source Reverse Transfer
Capacitance

VOS=O, VGS= -12V
(Note 1)

Id

Tum-On Delay Time (Note 1)

1r
loft

Rise Time (Note 1)

Voo = 10V, VGS(on) = 0
10(on) VGS(ofI)
2N3970
20mA -10V
2N3971
2N3972

8SOn
1.6Kn

f= 1kHz

f=lMHz

- 5V
- 3V

NOTE 1: For design reference only, not 100% tested.

2-13
Note: All typical values have been guaranteed by characterization and are not tested.

V

1

rOS(on)

10mA
5mA

V

rnA

2

10= 10mA
lo=20mA

Turn-Off Time (Note 1)

V

250

.11

pF

ns

·..0)~ 2N3.97Q;'2N3972 . ". "
..CO)

.Z .' EL.:ECTRICAL tHARACTERISTICS(CONT.)

,: &\I

~

...

VDD

=

• R _ VDD-VDSlONI

Z

l'

.&\1

D

VIN 0 - -......-

Ra

L -

IDlON)

~VOUT

1_-,

....

;

500

TCO0551I

2-14
Note: All typical '(alues have been guaranteed by characterization and are. not testeP..

.U~UIl.I

2N3993, 2N3994
P-Channel JFET
General Purpose AmplifierISwitch

.~
~

z

FEATURES

APPLICATIONS

•
•

Used in high-speed commutator and chopper applications. Also ideal for "Virtual Gnd" switching; needs no ext.
translator circuit to switch ±10 VAC. Can be driven direct
from TTL or CMOS logic.

Low rOS(on)
High Yfs/Ciss Ratio (High-Frequency Figure-ofMerit)

PIN CONFIGURATION

=

:

CHIP TOPOGRAPHY
5508

TO-72

~Jliil~'-'
.0025

.0027

.016

.0037 x .0035 0

.0027

.0025

=

NOTE: SUBSTRATE IS GATE

CTOO1011

PCO0071I

ABSOLUTE MAXIMUM RATINGS
ORDERING INFORMATION*
TO-72

WAFER

2N3993

2N3993/W

2N3993/D

2N3994

2N3994/W

2N3994/D

'When ordering wafer/dice refer to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS
SYMBOL
BVGSS
lOGO
loSS

10(of!)

@

25°C free-air temperature (unless otherwise noted)

TEST CONDITIONS

PARAMETER
Gate-Source Breakdown Voltage
Drain Reverse Current
Zero-Gate-Voltage Drain Current

Drain Cutoff Current

n

6r~i~-~!:~ ~:::::e ~~~~~i.~~ ~.~~~.~~

..
.................... -25V
Drain-Source Voltage ....................................... -25V ~
Continuous Forward Gate Current .................... -1 OmA
Storage Temperature Range ............ -65°C to + 200°C
Operating Temperature Range ......... -55°C to + 175°C
Lead Temperature (Soldering. 10sec) .............. + 300°C
Power Dissipation ......................................... 300mW
Derate above 25°C .......................... 2.0mWI"C

DICE

(Note 3)

2N3993

2N3994
UNIT

MIN

MAX

MIN

MAX

IG = lIlA.

VOS=O

VOG = -15V,

10=0

-1.2

-1.2

nA

Voo = -15V,

1.-0,
TA = 150'C

-1.2

-1.2

IlA

VOS= -10V,

VGS= 0,
(See Note 1)

Vos= -10V,

VGs=6V

VOS= -10V,

VGS= 6V,
TA = 150'C

VOS= -10V.

VGS -10V

-1.2

VOS= -10V,

VGs=10V,
TA = 150'C

-1

VGS(of!)

Gate-Source Voltage

VOS= -IOV,

10 = -lIlA

rdo(on)

Small-Signal Drain-Source
On-State Resistance

VGS-O,
f= 1kHz

10- 0•

iYf. i

Small-Signal Common-Source
Forward Transfer Admittance

Vos= -IOV,
f= 1kHz,

VGS=O,
(See Note 1)

Ciss

Common-Source Short-Circuit
Input Capacitance (Note 4)

VOS= -10V,
f= IMHz,

VGS=O,
(See Note 2)

2-15
Note: All typical values have been guaranteed by characterization and are not tested.

25

25

-10

4

-2

9.5

12
16

mA
-1.2

nA

-1

IlA
nA

IlA
1

150
6

V

4

5.5

V

300

n

10

/.IS

16

pF

: 2"3,993,·2N3994

iN

:o

ELECTRICAL CHARACTERISTICS (CONT.)
SYMBOL

..

'"

Z
N

TEST CONDITIONS
(Note 3)

PARAMETER

Cr••

Common-Source Short-Circuit
.Reve(VSE1- VSE2)IIL>T

Base Emitter
Voltage Differential
Change with
Temperature

3

S

10

IlVI"C

1L>(lel- ls2)I/L>T

Base Current
Differential
Change with
Temperature

0.3

0.5

1

nAI"C

0.9

le= lallA.
VeE =SV
TA = -S5°C to + 12SoC

1

0.85

1

0.8

1

SMALL SIGNAL CHARACTERISTICS
SYMBOL

PARAMETER

hlb

Input Resistance

hrb

Voltage Feedback Ratio

hie

Small Signal Current Gain

hob

Output Conductance

hie

Input Resistance'

hre

Voltage Feedback .Ratio

hoe

Output Conductance

NOTES:

1.
2.
3.
4.

TYPICAL
VALUE

TEST CONDITIONS

28
Ie ~1 mAo Ves = 5V (Note 4)

43

UNIT
n
x 10- 3

250
Ie = lmA. VeE = SV (Note 4)

.,

60

/lS

9.6

kn

42
12

x

10-~

IlS

Per transistor.
The reverse base-emitter voltage must never exceed 7.0 volts and the reverse base-emitter current must never exceed 101lA.
The lowest 01 two hFE readings is taken as hFEl lor purposes 01 this ratio.
For design relerence only. not 100% tested.

2-18
Note: All typical values have been guaranteed by characterization and are not tested.

ITE4091-ITE4093
2N4091-2N4093
JAN, JTXV, JANTX·
N-Channel JFET
Switch
FEATURES
•
•
•

CHIP TOPOGRAPHY

Low rDS(on)
ID(OFF) < 100pA (JAN TX Types)
Fast Switching

5001

PIN CONFIGURATIONS
TO-18

TO·92

x .0036
.0028
(SOURCE)
CTO05511

ABSOLUTE MAXIMUM RATINGS
G,C

s

o

0

(TA = 25°C unless otherwise noted)
Gate-Source or Gate-Drain Voltage .. , .... , ........... , -40V
Gate Current, ............ ,"',." ........... ,", .. , ..... , ... , 10mA
Storage Temperature Range ............ -65°C to +200°C
Operating Temperature Range ......... -55°C to +200°C
Lead Temperature (Soldering, 10sec) .............. + 300°C
TO-18
T0-92

G

PCOO3711

ORDERING INFORMATION*
TO-92

TO-1St

WAFER

DICE

ITE 4091

2N4091

2N4091/W 2N4091/0

ITE 4092

2N4092

2N4092/W 2N4092/0

ITE 4093

2N4093

2N4093/W 2N4093/0

Power Dissipation".""""""".".
Derate above 25°C"."""""."

Plastic
Storage .............................. " .... -55°C to + 150°C
Operating ............................ " .... - 55°C to + 135°C

tadd JANTX to these part numbers if JANTX processing is desired,
'When ordering wafer/dice refer to Section 10, page 10-1,

ELECTRICAL CHARACTERISTICS

SYMBOL

(25°C unless otherwise noted)

PARAMETER

TEST CONDITIONS

2NIITE
4091

2NIITE
4092

MIN MAX MIN
BVGSS

Gate·Source Breakdown Voltage

IG

= -ljJA,

VOS = 0

(Not JANTX Specified)

200
ITA = 150'C

Voo = 20V, IS = 0

Gate Reverse Current
IGSS
10(OFF)

I(JANTX,

ITE devices only) TA = 150'C

JAN, JTXV; TA = 25'C
Drain Cutoff Current
JAN, JTXV, TA = 150'C

Vp
loSS

VGS = -20V, VOS = 0

~ VOS= 20V

VGS - -12V(4091)
VGS = -8V(4092)
VGS = -6V(4093)

~

Gate·Source Pinch·Off Voltage

VOS - 20V, 10 - lnA

Drain Current at Zero Gate Voltage

VOS - 20V, VGS - 0,
Pulse Test Duraton = 2ms

-5

-40
200

Drain·Source ON Voltage

VGS=O

2-19
Note: All typical values have been guaranteed by characterization and are not tested.

V
200

pA

400

400

400

nA

-100

-100

pA

-200

-200

-200

nA

100

100

100

200

200

200

200

200

200

400

400

400

-10

30

-2

-7

15

-1

-5

pA

nA
V
mA

8
0.2

10 = 4mA
10 = 6.6mA

UNIT

-100

10 = 2.5mA
VOS(ON)

2NIITE
4093

MAX MIN MAX

-40

-40

Drain Reverse Current
1000

360mW
3,3mWrC

1,8W
10mWrC

0.2
0.2

V

2

.O~Dll

ITE4091-ITE4093 .
2N.4091-2N4093 JAN, JTXV, JANTX*
ELECTRICAL CHARACTERISTICS (CONT.)
SYMBOL

PARAMETER

TEST CONDITIONS

2N/ITE

.2NIITE

2""TE

40111

4092

4093

MIN

UNIT

MAX MIN MAX MIN MAX

rOS(on)

Static Drain-Source ON Resislance

VGS=O,10-1mA

30

50

80

rds(on)

Sialic Drain Source
ON Resistance

Vas - 0, 10 = 0, f= 1kHz

30

50

80

Ciss

Common-Source Inpul Capacitance

Vos-20V, VGS-O, f-1MHz

16 .

16

16

IJANTX Only

(Nole 1)

5

5

5

Crss

Common-Source
Reverse Transfer. Capacitance

VOs=O, Vas = -20V, f=1MHz
(Nole 1)

5

5

5

Id(ON)

Turn-ON D.elay TilTle (Nole 1)

Ir

Rise ·Time (Nol", 1)

loft

Turn-OFF Time (Note 1)

VOO =
4091
4092
4093

3~(O~ao(o~~;!
"8lrmA

~

 RL

90%

V'N

V".(ON)

RG

100n

220n

390n

IO(ON)

-15mA

-7mA

-3mA

:

~.~~

_ 6V 10%

t,

90%

10%

510

t--

-12V

-7V

-5V

WF00011I

7.5K.

v

>

t.2K

L-...,.. SAMPLING

~

~-SCOPE-

:

RISE TIME 0.4 ns
INPUT RESISTANCE 10 MHz
INPUT CAPACITANCE 1.5 pF

\ __

~

Ro
v

;.
>
;>

1

SAMPLING SCOPE

12K

~

V'N~

OUTPUT

VIN

?

510

.
510

":"
TCOO171 I

TYPICAL PERFORMANCE CHARACTERISTICS
Vp vs loss

Vp VB rOS(ON)

...
7.0
U
'.0

7.G

4.0

~
>

'.0
2.0

...t.o

7.0

4.0

'\

\.

!

'los = 0.1'1
'los = 0

1\

-'vVas
Ol ""= 020V

2.0

...
...,

4.0

-

3.0

II

1.0

0.&
0..

0..

t.OOO

'0

30

2-37

iPUlood)

...
,.0

.

,
OPOO1211

Note: All typical values have been guaranteed by characterization and are not tested.

Vos "" 20V
Vos'" 0

2.0

_mAl
OPOO1111

I

>

0.&
0.7

OA
0.7

to

'0.0

...
...s.o

U

Vp vs 9fS

......
...s.o
...
~

to.O
1.0

10.0

!...

jJJ

2N5114 = -18V
2N5115= -15V
2N5116 = -15V

Drain Current at Zero Gate Voltage
(Note 1)

tz

OA
0. 7
0.
O.
1,000

••

3,000

10,000

30,000

100,000

• .....Yl
OPOO1311

>

! 2N5117-2N5119

I Dielectrically Isolated Dual PNP
~ General Purpose Amplifier
'P'
'P'

10

I

,FEATURES
•
•
•
•
•

CHIP TOPOGRAPHY

High Gain at Low Current
Low Output Capacitance
Good hFE Match
Tight VBE Tracking
Dlelectrlcally Isolated Matched Pairs for
Differential Amplifiers

4501

1-,033-j

~
.

EMITTER ,1lO29

.0039

.023

L

PIN CONFIGURATION'

EMITTER

x ,1lO29
.0039

TYP 2 PLACES
BASE

COLLECTOR

.ob3o x

.0030

.0040

.0040

TYP 2 PLACES

.0035 x .0034

BASE

..0045

.0044

TYP2PLACES
CT001711

TO-78

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Collector-Base or Collector-Emitter
Voltage (Note 1) ........................................... -45V
Emitter-Base Voltage (Notes 1 and 2) .................. - 7V
Collector-Collector Voltage ................................. 100V
Collector Current (Note 1) ................................ 10mA
Storage Temperature Range ............ -65°C to +200°C
Operating Temperature Range ......... -55°C to +200°C
Lead Temperature (Soldering, 10sec) .............. + 300·C
ONE SIDE
BOTH SIDES

PCOO1101

ORDERING INFORMATION*
TO-78

WAFER

DICE

2N5117

2N5117/W

2N5117/D

2N5118

2N5118/W

2N5118/D

2N5119"

2N5119/W

2N5119/D

400mW
2.3m'l"'oC

Power Dissipation.....................
Derate above 25°C................

750rilW
4.3mW'oC

·When ordering waler/dice reler to Section 10, page la-I,

ELECTRICAL CHARACTERISTICS
SYMBOL

(25°C unless otherwise noted)

PARAMETER

2N5117
2N5118

TEST CONDITIONS

2N5119

UNIT

MIN MAX MIN MAX
hFE

DC Cumint 'Gain
ITA = -55°C

ICBO

Collector Cutoff·Current

IC = lallA. VCE = 5.0V

100

Ic = 500PA. VCE = 5.0V

100

Ic = lallA. VCE

= 5.0V

300

50

30

IE-a. Vce-3OV
,ITA-1S0°C

50
20

0.1

0.1

nA

0.1

0.1

IIA
nA

lEBO

Emitter Cutoff Current

IC = O. VEB = 5.0V

0.1

0.1

IC1,C2
GBW

Coliector·Coliector Leakage

Vcc-l00V

5.0

5.0

Current Gain Bandwith Product (Note 4)

Ie = 5001lA.

100

VCE = 10V

100

COb

Output Capacitance (Note 4)

IE'" 0, Vee = 5.0V. 1= lMHz

Gte

Emiller Transition CapaCitance (Note 4)

IC - 0, VEe

CC1,C2

Coliector·Colleqlor Capacitance (Note 4)

Vee - 0, I = 1MHz

VCEO(sust)

Coliector·Emitter Sustalni,ng Voltage

Ic = 1'.OmA. Ie = 0

NF

Narrow Band Noise Figure (Note 4)

IC = lallA. VCE = 5.0V
BW= 200Hz

BVCBO

Collector Base Breakdown Voltage

Ic = lallA. IE = a

45

45

V

BVEeO

Emitter Base Breakdown Voltage

IE = lallA. Ic = a

7.0

7.0

V

= 0.5V,

0.8

pA
MHz

1= lMHz

I'

2-38
Note: All typical values have been guaranteed by characterization and are not tested.

1.0

0.8

0.8

45
= 1kHz. RG

= 10kO

O.B

1.0
45
4.0

pF
V

4.0

dB

MATCHING CHARACTERISTICS

I
(25°C unless otherwise noted)
2N5117

SYMBOL

PARAMETER

2N5118

~

2N5119

TEST CONDITIONS

UNIT
MIN MAX MIN MAX MIN MAX

DC Current Gain Ratio
hFE1/hFE2

(Note 3)
Base-Emitter Voltage

VSE,-VSE2
Is 1-IS2

Base Current Differential
Base Voltage Differential
Change with Temperature

"(ls 1-ls2)/"T

Base-Current Differential
Change with Temperature

NOTES:

1.
2.
3.
4.

Ie - 10iJA to SOOIlA, VeE

= SV

= 10iJA, VeE = S.OV
Ie = 10iJA to SOOIlA, VeE = SV

0.9

Ie - 10iJA, VeE

= S.OV

0.85

1.0

0.8

1.0
mV

3.0
5.0

5.0

10.0

15

40

nA

TA= -55'Cto + 125'C

3.0

5.0

10

IlV/'C

TA= -55'Cto + 125'C

0.3

0.5

1.0

nAI'C

Per transistor.
The reverse base-la-emitter voltage must never exceed 7.0 volts and the reverse base-to-emitter current must never exceed 101lA.
Lower of two hFE readings is defined as hF E1'
For design reference only, not 100% tested..

2--'l9

Note: All typical values have been guaranteed by characterization and are not tested.

Z

ca

I&)

1.0

Ie

Differential

"(VSE1-VSE2)1 "T

.......
..
N

2N5117-2N5119

i!

2N51'96-2N5199

~
o

Gene·ral· Purpose Amplifier

.!II Dual N-Channel JFET
;;z

PIN CONFIGURATION

"

CHIP TOPOGRAPHY
6037

TO-7,l

0,

ALL80ND PADS ARE 4x 4MIL.
CT000701
PC002501

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Gate-Source or Gate-Drain Voltage (Note 1) ........ -50V
Gate Current (Note 1) ..................................... 50mA
Storage Temperature Range ............ -65°C to +200°(;
Operating Temperature Range ......... ~55°C to + 150°C
Lead Temperature (Soldering, 10sec) .............. + 300°C
ONE SIDE' BOTH SIDES

ORDERING INFORMATION*
T0-71

WAFER

DICE

2N5196

2N5196/W

2N5196/D

2N5197

2N5197/W

2N5197/D

2N5198

2N5198/W

2N5198/D

2N5199

2N5199/W

2N5199/D

Power Dissipation (TA = 85°C) ... .
Derate above 25°C ............... .

250mW
2.6mW/"C

500mW
4.3mW/oC

·When ordering wafer/dice refer to Section 10, page 10-1,

ELECTRICAL CHARACTERISTICS
SYMBOL
IGSS

(25°C unless otherwise noted)
TEST' CONDITIONS

PARAMETER
Gate Reverse Current

MIN

VGS = -30V, Vos = 0
ITA = 150·C

MAX

UNIT

-25

pA

-50

nA
V

BVGSS

Gate-Source' Breakdown )/oltage

IG=-lj.iA, VOS=O

-50

VGS(off)

Gate-Source Cutoff Voltage

VOS = 20V, 10 = lnA

-0.7

-4

VGS

Gate-Source Voltage

-0.2

-3,8

IG

Gate Operating Current

-15

VOG = 20V,Io = 200j.iA
ITA -125·C

lOSS

Saturation Drain Current (Note 2)

VOS = 20V, VGS = 0

Qfs

Common-Source Forward Transconductance (Note 2)

VOS - 20V, VGS

Qfs

Common-Source Forward Transconductance (Note 2)

YOG - 20V, 10 = 200j.iA

gas

Common-Source Output Conductance (Note 2)

VOS = 20V, VGS = 0
VOG = 20V, 10 = 200j.iA

gas

Common-Source Output Conductance (Note 2)

Ciss

Common-Source Input Capacitance (Note 4)

Crss

Common-Source Reverse Transfer Capacitance
(Note 4)

NF

Spot Noise Figure (Note 4)

en

Equivalent Input Noise Voltage (Note 4)

=0
f= 1kHz

pA

-15

nA

0.7

7

rnA

1000

4000

700

1600
50

/J.s

4

6
f=lMHz

pF
2

VOS = 20V, VGS = 0

f = 100Hz,
RG = 10Mn

0.5

dB

f= 1kHz

20

/J.nV

JFIz

2-40
Note: All typical values have been guaranteed by characterization and, are not tested,

Z

VI
CD

ELECTRICAL CHARACTERISTICS (CONT.)
2N5196
SYMBOL

PARAMETER

2N5197

2N5198

2N5199

TEST CONDITIONS

UNIT
MIN MAX MIN MAX MIN MAX MIN MAX

IIG1-IG2 1

Differential Gate Current

VOG =20V,
10 = 2001'ft,

IOSSI/10SS2

Saturation Drain Current Ratio
(Note 2)

VOS = 20V, VGS = OV

9101 / g'02

Transconductance Ratio
(Note 2)

IVGS1-VGS2 1

Differential Gate-Source Voltage

LllvGS1=VGS2 1 Gate-Source Differential Vo~age
Change with Temperature
LIT
(Note 3)
1gOOI-go021

NOTES:

1.
2.
3.
4.

..
~
..
I
N

2N5196-2N5199

125"C

f= 1kHz

Voo = 20V,
10 = 2001'ft,

0.95
0.97

TA - 25"C
TS = 12S"C
TA= -55"C
TR = 2SoC
f= 1kHz

Differential Output Conductance
Per transistor.
Pulse test required, pulsewidth = 300"s, duty cycle
Measured at endpOints TA and T B.
For design reference only, not 100% tested.

5

< 3%.

2-41
Note: All typical values have been guaranteed by characterization and are not' tested.

5

5

1

0.95

1

0.97

1

0.95

1

0.95

5

1

0.95

1

0.9S

nA

1
1

5

5

10

15

5

10

20

40

5

10

20

40

1

1

1

1

mV

",I"C
is

Z

VI

.U~UI6

2N5397, 2N5398

iz

II)

C\I

N~¢hannel JFET
High F~equency Amplifier
FEATURES
G,s = 15dB Minimum (Common Gate) at 450MHz

•
•

,

,

.,

CHIP TOPOGRAPHY
5011

Uw Noise
Low Capacitance

•

" ' " ,

I--- .015---1
I
I

PIN CONFIGURATION

NOTE: SUBSTRATE
IS GATE.

T~.

.012

TO-72

0.0035
.0042
.0025 x -:0032

1

S .0035 x .00405
.0025
.00305 '
CTOO191t

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Drain-Gate Voltage ........................................... 25V
Drain-Source Voltage ............................. : ........... 25V
Continuous Forward Gate Current.. .................... 10mA
Storage Temperature Range ............ -65·C to +200°C
Operating Temperature Range ......... -55°C to + 150°C
Lead Temperature (Soldering, 10sec) .............. + 300°C
Power Dissipation ......................................... 300mW
Derate above 25°C .......................•.. 2.4mW fOC

PCOOO201

ORDERING INFORMATION*
TC>-72

WAFER

DICE

2N5397

2N5397/W

2N5397/D

2N5398

2N5398/W

2N5398/D

'When ordering waferI dice refer to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS

(25°C unless otherwise noted)
2N5397

SYMBOL

PARAMETER

UNIT
MIN

IGSS

2N5398

TEST CONDITIONS

Gate Reverse Current

VGS= -15V, VOS=O
ITA = + 150·C

150·C

MAX

MIN

MAX

-0.1

0.1

nA

-0.1

-0.1

IIA

BVGSS

Gate-Source Breakdown Voltage

VOS=O, IG =

-IlIA

-25

VGS(off)

Gate-Source Cutoff Voltage

VOS = 10V, 10 = InA

-1.0

-6.0

-1.0

-6.0

loSS

Saturation Drain Current (Note I)

VOS = 10V, VOS = 0

10.

30

5

40

rnA

VGS(f}

Gate-Source Forward Voltage

VOS-O,IG-lmA

1

V

Common..source JForward

'-:OS = 10V, 10 = lOrnA

6000

10,000

Transconductance (Note I)

VOS = 10V, VGS = 0

Common..source Output

VOS

Conductance

VOS = 10V, VGS = 0

Common-Source Reverse Transfer

Vos = 10V, 10 = lOrnA

Capacitance (Note 2)

VOS = 10V, VGS = 0

gls
goss
Crs•

= 10V,

10 = lOrnA

VOG = 10V, 10 = lOrnA
Cis.

Common-Source Input CapaCitance
(Note 2)

VOS = 10V, VGS = 0

2-42
Note: All typical values have been guaranteed by characterization and are not tested.

-25

1

f= 1kHz

,

5500

V

10,000

ps

200
400
1.2
1.3

f=IMHz

pF

5.0
5.5

2N5397, 2N5398
ELECTRICAL CHARACTERISTICS (CONT.)
2N5397
SYMBOL

PARAMETER

UNIT
MIN

9iss

9055

Common-Source Input

VOG = 10V, 10 = 10mA

Conductance (Note 2)

VOG = 10V, VGS = 0

Common-Source Output

VOG = 10V, 10 = 10mA

Conductance (Note 2)

VOS = 10V, VGS = 0

Common-Source FOlWard

VOG = 10V, 10 = 10mA
VOS = 10V, VGS

9fs

Transconductance (Note 1, 2)

Gps

Common-Source Power Gain (neutralized)

NF

Common-Source, Spot Noise
Figure (neutralized)

NOTES:

2N5398

TEST CONDITIONS
MAX

MIN

MAX

2000
3000
400
500
f = 450MHz

5500

IlS

9000

=0

5000

10,000

15
dB

VOG = 10V, 10 = 10mA
3.5

(Note 2)

1. Pulse test duration = 2ms
2. For design reference only, not 100% tested.

2-43
Note: All typical values have been guaranteed by characterization and are not tested.

2N5432-2N5434
N-Channel JFET Switch
CHIP TOPOGRA~HY

FEATURES
•

Low rds(on)

.•

Excellent SWitching

•

Low Cutoff Current'

5018

o
.0035 . x .0036

.. if-------::;,,.....,.OO25

PIN CONFIGURATION

.0026

TO-52
NOTE: SUBSTRATE
is GATE

CT0Q2011

PCOO12U

ORDERING INFORMATION·
TO-52

WAFER

2N5432

2N5432/W

2N5432/0

2N5433

2N5433/W

2N5433/0

2N5434

2N5434/W

2N5434/0

ABSOLUTE MAXIMUM RATINGS
(TA = 25·C unless otherwise noted)

DICE

Gate-Source Voltage ....................................... -25V
Gate-Drain Voltage ......................................... -25V
Gate Current .................................. _............. 100mA
Drain Current ............................................... .400mA
Storage Temperature Range ............ -65·C to + 200·C
Operating Temperature Range ......... - 55·C to + 150·C
Lead Temperature (Soldering, 10sec) .............. + 300·C
Power Dissipation ......................................... 300mW
Derate above 25·C ........................ ;. 2.3mW JOC

'When ordering waferI dice refer to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS

(25·C unless otherwise noted)
2N5432

SYMBOL

PARAMETER

2N5433

2N5434

TEST CONDITIONS

UNIT
MIN MAX MIN MAX MIN MAX

IGSS

Gate Reverse Current

BVGSS

Gate Source Breakdown Voltage

ITA = 150·C

VGs= -15V, Vos=O

-200

-200

-200

pA

-200

-200

-200

nA

200

pA

200

nA

-25

IG=-IIlA, Vos=O

-25
200

IO(off)

Drain Cutoff Current

VGS(off)

Gate-Source Cutoff Voltage

VoS = 5V, 10 = 3nA

-4

lOSS

Saturation Drain Current
(Note I)

VOS = 15V, VGS = 0

150

rOS(On)

Static Drain-Source ON Resistance

VoS(on)

Drain-Source ON Voltage

rds(on)

Drain-Source ON Resistance

CiSS

Common-Source Input Capacitance
(Note 2)

Crss

Common-Source Reverse Transfer
CapaCitance (No.te 2)

ITA = 150·C

VoS= 5V, VGS= -IOV

200

2
VGS = 0, 10 = lOrnA
VGS=O, 10=0

f= 1kHz

Vos=O, VGS= -tOY

f=IMHz

2-44
Note: All typical values have been guaranteed by characterization and are not tested..

-10

-25
200.
200

-3

-9

100

-I

V

-4

30

V
rnA

5

7

10

50

70

100

mV

5

.7

10

ohm

30

30

30

15

15

15

Ohm

pF

2N5432~2N5434

ELECTRICAL CHARACTERISTICS (CONT.)
2N5432
SYMBOL

PARAMETER

2N5433

2N5434

TEST CONDITIONS

UNIT
MIN

MAX MIN MAX. MIN MAX

IcJ

Turn-ON Delay Time (Note 2)

VOO= 1.5V,

4

4

tr

Rise Time (Note 2)

VGS(on) = 0,

1

1

1

toff

Turn-OFF Delay Time (Note 2)

VGS(off)= -12V

6

6

6

tf

Fall Time (Note 2)

10(on) = 10mA

30

30

30

NOTES:

1. Pulse test required, pulsewidth 300"s, duty cycle:S 3%.
2. For design reference only, not 100% tested.

Voo

R _ VOo-Vos(ON)
L -

o
VIN

lo(ONI

~VOUT

o---.._-...j-RG

!-

5O1l

TCOO1811

2-45
Note: All typical values have been guaranteed by characterization and are not tested.

4
ns

;Z·2N5452-2N5454

I

Dual N-Channel JFET
, General· Purpose Amplifier
&'4'

!GENERAL DESCRIPTION

I

FEATURES

\ Matched FET pairs for differential amplifiers. This family
of general purpose FETs iscnaracterized for low and
medium frequency differential amplifier applications requiring low drift and low offset voltage.

•
•
•
•

Low
Low
Low
Low

Offset Voltage
Drift
Capacitance
Qutput Conductance

CHIP TOPOGRAPHY

PIN CONFIGURATION

6037
TO-71

0,

ALL BONO PADS ARE 4 x 4 MIL.
CTOOQ701
PC002501

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Gate-Source or Gate Drain Voltage
(Note 1) .................................................... -50V
Gate Current (Note 1).................................... 50mA
Storage Temperature Range ........... -65°C to +200°C
Operating Temperature Range ........ -55°C to + 150°C
Lead Temperature (Soldering, 10sec) ............. +300°C

ORDERING INFORMATION*
TO-71

WAFER

DICE

2N5452

2N5452/W

2N5452/D

2N5453

2N5453/W

2N5453/D

2N5454

2N5454/W

2N5454/D

·When ordering walerI dice reler to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS

Power Dissipation (TC = 85°C) ....
Derate above 25°C................

BOTH SIDES

250mW
2.9mWrC

500mW
4.3mW/oC

(TA = 25°C unless otherwise noted)
2N5452

SYMBOL

ONE SIDE

2N5453

2N5454

TEST CONDITIONS

PARAMETER

UNIT
MIN MAX MIN MAX MIN MAX

VGS = -30V, VOS = 0

-100

-100

~100

pA

-200

-200

-200

nA

-1

-4.5

V

-0.2

-4.2

IGSS

Gate Reverse Current ITA = 150.C

BVGSS

Gate-Source Breakdown
Voltage

Vos=O, IG= -1/'A

-50

VGS(off)

Gate-Source CutoWVoltage

VOS= 20V, 10=lnA

-1

-4.5

-1

-4.5

VGS

Gate-Source Voltage

Vos = 20V, 10 = 50/'A

-0.2

-4.2

-0.2

-4.2

VGS(f)

'Gate-Source Forward Voltage

VOS =0, IG = lmA

lOSS

·Ssturation Drain Current

VOS = 20V, VGS = 0

0.5

5.0

0.5

5.0

0.5

5.0

1000

3000

1000

3000

1000

3000

2

Common-Source Forward
Qt.

Transconductance

I(Note 2)

I
VOS = 20V, VGS = 0

= 1kHz

f= 100MHz

Common-Source Output

gos

Conductance

Ciss

Common-Source Input
CapaCitance (Note 2)

VOS = 20V, 10 = 200p.A

= 20V,

Crss

Common-Source Reverse
Transler Capacitance (Note 2)

VOS

Cdgo

Drain-Gate CapaCitance (Note 2)

VOG=10V, 15=0

-50

1= 1kHz

1000

-50

2

1000

2
rnA

1000

3.0

3.0

3.0

1.0

1.0

1.0

4.0

4.0

4.0

1.2

1.2

1.2

1.5

1.5

1.5

p.s

VGS = 0
1= lMHz

2-46
Note: All typical values have been .guaranteed by characterization and are not tested.

pF

.U~UIL

2N5452-2N5454
ELECTRICAL CHARACTERISTICS (CO NT.)
2N5452
SYMBOL

PARAMETER

UNIT

en

Equivalent Short Circuit
Input NOise Voltage

VOS = 20V. VGS

NF

Common-Source Spot
Noise Figure (Note 2)

VOS = 20V. VGS = 0
RG= 10MS'!

_"-'-'1

=. 0

f= 1kHz
f = 100Hz

wc

1.0

MAX

MIN

20

0.5
0.95

T' 2S"C to -

MIN

20

Vos = 20V. VGS = 0

Gate-Source Voltage

MAX

0.5
0.95

1.0

0.95

MAX
20

-L!L

0.5

d3

5.0

10.0

15.0

0.8

2.0

0.5

1.0

2.5

Differential Change with
"IVGS1-VGS21 Temperature

mV
Vos = 20V. 10 = 200j.tA

9'91/9'92
19091-9092 1
NOTES:

y'1IZ

1.0

0.4

T =2S'C to
+ 125'C

Transconductance Ratio

0.97

Differential Output Conductance

f= 1kHz

1. Per transistor.
2. For desi9n reference only. not 100% tested.

2-47
Note: All typical values have been 9uaranteed by characterization' and are not tested.

1.0
0.25

0.97

1.0
0.25

0.95

1.0
0.25

Z

!
N
I
N

2N5454

TEST CONDITIONS
MIN

IOSSl/IOSS2 Drain Saturation Current Ratio
IVGS1-VGS2 1

2N5453

N

IJS

Z

:

CII
~

! i~N5457.2N5459

IN-Channel JFET
,.... General Purpose Amplifier/Switch
~

10

Z

PJN CONFIGURATION

CHIP TOPOGRAPHY

ft

5010

T0-92

D(2)
.0013 FULLR
.0017

~1) ~T
• .

o

S

.0025

x~

.0036

.0036

:=

~ ~

~
NOTE: SUBSTRATE
IS GATE

.013

G

PCO01311

CT0Q0321

ABSOLUTE MAXIMUM RATINGS

ORDERING INFORMATION*
TO-92

WAFER

DICE

2N5467

2N5457/W

2N5457/D

2N545B

2N5458/W

2N5458/D

2N5459

2N5459/W

2N5459/D

'When

~rda"ing

(TA = 25°C unless otherwise noted)
Drain-Gate Voltage ........................................... 25V
Drain-Source Voltage ......................................... 25V
Continuous Forward Gate Current.. .................... 10mA
Storage Temperature Range ............ -65°C to + 150°C
Operating Temperature Range ......... -55°C to + 135°C
Lead Temperature (Soldering, 10sec) .............. + 300°C
Power Dissipation ......................................... 310mW
Derate above 25°C ........................ 2.82mWrC

waler / dice reler 10 Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
SYMBOL
BVGSS

PARAMETER

TEST CONDITIONS

Gale-Source Breakdown Voltage

IG - -IOpA, Vos - 0

MIN

TYP

-25

-60

Gale Reverse Currenl

VGS(off)

Gale-Source Cutoff Voltage

2N5458

-0.5
VOS=15V,IO=IOnA

2N5459
VGS

Gale-Source Vollage

-8.0
-2.5

VOS = 15V, 10 = 200pA

-3.5

2N5459

VOS = 15V, 10 = 400pA

-4.5

(Nole I)

2N5459

Forward Transler Admittance

2N5458

VOS = 15V, VGS = 0

2N5457
IYlsl

-7.0

-2.0
VOS -15V, 10 = 100pA

2N5458

VOS -15V, VGS = 0, I = 1kHz

2N5459

-200

-1.0

2N5458

Zero-Gale-Voltage Drain Currenl

V
nA

-6.0

2N5457

2N5457
lOSS

.05

VGS = -15V, VOS- 0, TA -IOO'C
2N5457

UNIT

-1.0

VGS - -15V, VOS = 0
IGSS

MAX

V

V

1.0

3.0

5.0

2.0

6.0

9.0

4.0

9.0

16

1000

3000

5000

1500

4000

5500

2000

4500

6000

mA

,,"S

IYosl

Oulpul Admittance

VOSs 15V, VGS-O, I-1kHz

10

50

Ciss

Inpul Capacitance (Nole 2)

VOS=15V, VGS=O, 1=IMHz

4.5

7.0

""

Crss

Aeverse Transler CapaCitance (Nole 2)

VOS = 15V, VGS = 0, 1= IMHz

1.5

3.0

pF

NF

Noise Figure (Nole 2)

VOS -15V, VGS = 0, RG = IMHz
BW -1Hz, I -1kHz

3.0

dB

NOTES:

I. Pulse lest required. PW S 630ms. duty cycle S 10%
2. For deSign relerence only, nol 100% lesled.

2-48
Nole: All typical values have been guaranleed by characterization and are nol lested.

pF

2N5460-2N5465
P-Channel JFET

Low Noise Amplifier
PIN CONFIGURATION

CHIP TOPOGRAPHY
5503

TO·92

q

II'~;}'='=

H

r-

s

0

.016

---i

NOTE: i1U:~i:ATE
CTOO2111

G

PC003111

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Drain-Gate or Source-Gate Voltage
2N5460 - 2N5462 ................................. -40V
2N5463 - 2N5465 ................................. -60V
Gate Current ................................................. 10mA
Storage Temperature Range ............ -65°C to + 150°C
Operating Temperature Range ......... -55°C to + 135°C
Lead Temperature (Soldering, 10sec) .............. +300°C
Power Dissipation ........................................ :310mW
Derate above 25°C ........................ 2.82mWI"C

ORDERING INFORMATION*
TO-92

WAFER

DICE

2N5460

2N5460/W

2N5460/0

2N5461

2N54611W

2N5461/0

2N5462

2N5462/W· 2N5462/0

2N5463

2N5463/W

2N5463/0

2N5464

2N5464/W

2N5464/0

2N5465

2N5465/W

2N5465/0

'When ordering waler/dice refer to Section to, page to-to

ELECTRICAL CHARACTERISTICS
SYMBOL

(25°C unless otherwise noted)

PARAMETER

TEST CONDITIONS

2N5460, 2N5461 , 2N5462
BVGSS

Gate·Source Breakdown Voltage

2N5463, 2N5464, 2N5465

IG = 101lA, VOS = 0

2N5460, 2N5463
VGS(off)

Gate·Source Cutoff Voltage

2N5461, 2N5464

VOS= -15V, 10= 1.011A

2N5462, 2N5465
2N5460, 2N5461, 2N5462
Gate Reverse Current
IGSS
ITA = 100°C

VOs=O

2N5463, 2N5464, 2N5465
2N5460, 2N5461 , 2N5462
2N5463, 2N5464, 2N5465

Zero·Gate Voltage Drain Current

gts

Gate-Source Voltage

Forward Transadmittance

V

0.75

6.0

1.0

7.5

1.8

9.0

IIA

-1.0

rnA

-2.0

-9.0

-4.0

-16

2N5460, 2N5463
2N5461, 2N5464

0.5

4.0

0.8

4.5

2N5462, 2N5465

10 = -O.4mA

1.5

6.0

2N5460, 2N5463

1000

4000

2N5461, 2N5464

1500

5000

2N5462, 2N5465

2000

6000

VOS= -15V

1= 1.0kHz

Output Admittance
Input Capacitance (Note 1)

Crss
NF

Reverse Transler Capacitance (Note 1)

1= lMHz

Common·Source Noise Figure (Note 1)

en

Equivalent Short·Circuit Input
Noise Voltage (Note 1)

I -100Hz
BW= 1.0Hz
RG=I.0MU

VGS= OV

NOTE 1: For deSIgn reference only, not 100% tested.

2-49
Note: All typi"al values have been guaranteed by characterization and are not tested.

V

5.0
1.0
1.0
_5.0

VGS=O
10=0.lmA
10= -0.2mA

VOS = -15V

UNIT

5.0

Ciss

gos

MAX

VGS= 30V
VGS-20V
VGS= 30V

2N5461, 2N5464
2N5462, 2N5465

VGS

TYP

40
60

VGs=20V

2N5460, 2N5463
loss

MIN

75
5.0
1.0

7
2.0

1.0

2.5

60

115

nA

V

IlS
IlS
pF
pF
DB
nV/

.!Hz

II

CD

....CD
10

Z

i
z

(II

2N5484-2N5486

N-Channel ,JFET
'
High Frequency Amplifier
FEATURES

CHIP TOPOGRAPHY

Up. to 400MHz Operation
Economy Packaging
eras < 1.0pF

.0035
.0025 FULL~

PIN CONFIGURATION

.017

•

•

•

5000

T ~. ~:0035

.0025 x .0035
.0025

•_

~ 0(2)1

TO-92

.

I~;[r

~=
~ NOTE: SUBSTRATE
.
IS GATE

q

.017
CTOO221 I

rl

ABSOLUTE MAXIMUM RATINGS
o

S

(TA = 25°C unless otherwise specified)
Drain-Gate Voltage ........................................... 25V
Source Gate Voltage ......................................... 25V
Drain Current ................................................. 30mA
Forward Gate Current ...................................... 10mA
Storage Temperature Range ............ -65°C to + 150°C
Operating Temperature Range ......... -·55°C to + 135°C
Lead Temperature (Soldering. 10sec) .............. + 300°C
Power Dissipation ......................................... 310mW
Derate above 25°C ........................ 2.82mW fOC

Q

PCO0340t

ORDERING INFORMATION*
TO·92

WAFER

DICE

2N5484

2N5484/W

2N5484/D

2N5485

2N5485/W

2N5485/D

2N5486

2N5486/W

2N5486/D

'When ordering waler/dice reler to Section 10. page 10-1.

ELECTRICAL CHARACTERISTICS

(25°C unless otherwise noted)
2N5484

SYMBOL

PARAMETER

2N5485

2N5486

TEST CONDITIONS

UNIT
MIN MAX MIN MAX MIN MAX
-1.0

-1.0

-1.0

-200

-200

-200

IGSS

Gate Reverse Current ITA = l00.C

VGS = -20V. Vos = 0

BVGSS

Gate-Source Breakdown Voltage

IG = -lIlA. VOS - 0

-25

VGS(off)

Gate-Source Cutoff Voltage

VOS - 15V. 10 - 10nA

-0.3 -3.0 -0.5 -4.0 -2.0 -6.0

VOS = 15V. VGS = 0 (Note 1)

loSS

Satliration Drain Current

gts

COmmon-Source Forward
Transconductance

gos

Common-Source Output
Conductance

Re(yta)

Common-Source Forward
Transconductance (Note 2)

Re(yos)

Common-Source Output
Conductance (Note 2)

Re(yis)

Common-Source Input
Conductance (Note 2)

Ciss

Common-Source Input
CapaCitance (Note 2)

1:0

5.0

4.0

nA

-25

-25
10

8.0

20

V
rnA

3000 6000 3500 7000 4000 8000
1= 1kHz
50

VoS=15V. VGS=O

1= 100MHz
1=400MHz
1=,100MHz
I -400MHz
l-l00MHz
1=400MHz

75

60

2500
3000

3500

fJS

75
100

100

100
1000

1000

5.0

5.0

5.0

1.0

1.0

1.0

2.0

2.0

2.0

Common-Source Reverse
Crss

Transler Capacitance (Note 2).

Coss

Common-Source Output
Capacitance (Note 2)

1= lMHz

2-50
Note: All typical velues have been guaranteed by characterization and are not tested.

pF

2N5484-2N5486
ELECTRICAL CHARACTERISTICS (CO NT.)
2N5484
SYMBOL

PARAMETER

2N5485

2N5486
UNIT

TEST CONDITIONS
MIN MAX MIN MAX MIN MAX
vos = 15V, vGS = 0, RG = lM.f!

f= 1kHz

2.5

VOS = 15V, Vo = lmA,
RG= lk.f!
NF

Noise Figure
(Note 2)

f = 100MHz
VOS = 15V, 10 = 4mA,
RG= lk.f!

f = 400MHz

VOS = 15V, 10 = lmA
Gps

NOTES:

Common-Source Power Gain
(Note 2)

16
f = 100MHz

VOS = 15V, 10 = 4mA

1. Pulse test required. Pulse width = 300;. 30V
Crss 0.75pF (Typical)

=

CHIP TOPOGRAPHY

TO·71
TO·78

4000

1-- --1
023

l

CATHODE"

T~
~:~~~~~~~s .0040 x.0040
.017
---.l
~~~~~~!CES ~qQ~DIA
.0030

.0030

.0040

j

ANODEM1

.
CT00331I

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Diode Reverse Voltage ...................................... 30V
Diode to Diode Voltage ....................•............... ±50V
Forward Current ............................................. 20mA
Reverse Current ............................................ 100!-IA
Storage Temperature Range ............ -65°C to + 200°C
Operating Temperature Range ......... -55°C to + 150°C
Lead Temperature (Soldering, 10sec) .............. + 300°C
Power Dissipation ........................ ; ................ 300mW
Derate above 25°C .......................... 2.4mWfOC

PCQ0211 I

ORDERING INFORMATION*

'When ordering wafer/dice refer to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS

(@ 25°C unless otherwise noted)

10100, 10101
SYMBOL

TEST CONDITIONS

PARAMETER

UNIT
MIN TYP MAX

VF

Forward Voltage Drop

IF = lOrnA

0.8

BVR

Reverse Breakdown Voltage

IR=lpA

30

IR

Reverse Leakage Current

VR= 1V

1.1

V
0.1
2.0

I
IiR,-IR2 1
Crss

TA = 125°C

VR = 10V

Differential Leakage Current
Total Reverse Capacitance

VR=10V, f=lMHz (Note 1)

NOTE 1: For design reference only. not 100% tested.

2-74
Note: All typical values have been guaranteed by characterization and are not tested;

V

0.75

pA
10
10

nA

3

pA

1

pF

ID100, ID101
TYPICAL PERFORMANCE CHARACTERISTICS
REVERSE CURRENT vs. VOLTAGE
1.0

11

0.9

."

10

.

_

CAPACITANCE

12

9

.!: •
~

0.8
0.7
0.6

L

--

FORWARD CURRENT

.!'-lmA~

lDO"A
lOjJA •

r-- r-- -- r--

0.3
0.2

/"

hA

0.1

~~

o

10

15

20

25

VOLTAGE

10mA~1I

-

i -t-

VS.

0.4

/1-'"

,/

o

VOLTAGE

0.5

./

t---

f-- f--

"-

VS.

30

00

10

15

VRIVI

25

20

VR (VI

OPOO1811

OP001911

2-75
Note: All typical values have been guaranteed by characterization and are not tested.

30

100 nA

r--r-- - .

"

•

H

o~--'-1.......L..-'.:Jol';-.5-'--'---'-~1';;-.0-'--'--"'-:".4
V F {VI
OPOO201 I

....a
o

2_'
'

1'1100, IT101

P-Channel JFET Switch

8
t GENERAL DESCRIPTION

FEATURES

This P-channel JFET has been designed to directly
interface with TTL logic, thus eliminating the need for costly
drivers, in analog gate circllitry. Bipolar inputs of ±15V can
be switched. The FET is OFF for hi level inputs (+ 5V or
+ 15V) and ON for low level inputs « 0.5 V for
IT100, < 1.5V for 1T101).
'

PIN CONFIGURATION

•
•

Interfaces Directly w/TTL Logic Elements
rOS(on) < 7Sq for SV Logic Drive

•

IO(Ciff)

< 100pA

CHIP TOPOGRAPHY
5514

T()'18

o

G,C

*~---,028 - - - - - I

s

1....

I

PCO0011I

NOTE: SUBSTRATE IS GATE.

CT003411

ORDERING INFORMATION*
TO-18

WAFER

DICE

1T100

IT100/W

1T100/D

1T101

IT10l/W

IT10l/D

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Gate-Source Voltage ......................................... 35V
Gate-Drain Voltage ........................................... 35V
Gate Current ................................................. 50mA
Storage Temperature Range ............ -65°C to +200°C
Operating Temperature Range ......... -55°C to + 150°C
Lead Temperature (Soldering, 10sec) .............. + 300°C
Power Dissipation ......................................... 300mW
Derate above 25°C ......... ; ................ 2.4mW 1°C

'When ordering wafer/dice refer to Section 10, page 10-1,

ELECTRICAL CHARACTERISTICS

(25°C unless otherwise noted)
IT100

SYMBOL

PARAMETER

UNIT
MIN

loss
Vp
BVGSS
IGSS
g15
gos
10(011)

rOS(on)
Ciss
Crss

Drain Current
Pinch Off Voltage
Gate-Source Breakdown Voltage
Gate Reverse Current
Transconductance
Output Conductance
Drain (OFF) Leakage
Drain·Source "ON" Resistance
Input CapaCitance
Reverse Transfer CapaCitance

IT101

TEST CONDITIONS
VGS=O, VDS=-15V
10 = InA, VOS = -15V
IG=lpA, VOs=O
VGS = 20V, VOS = 0

-10
2
35

MAX MIN
-20
4.5

VOS = -10V, VGS = 15V
VGS - 0, VOS - -0, tV
VOG - -20V, VGS - 0 (Note 1)
VOG- -10V, IS-O (Note 1)

NOTE 1: For design reference only, not 100% tested.

2-76
Note: All typical values have been guaranteed by characterization and are not tested.

4

mA
10
V

35
200

8

VGS = 0, VOS'" -15V

MAX

200

pA

1
-100
60
35
12

mS

8

1
-100
75
35
12

pA

n
pF

IT120, IT122
Dual NPN
General Purpose Amplifier
FEATURES
•
•
•
•

CHIP TOPOGRAPHY

High hFE at Low Current
Low Output Capacitance
Good Matching
Tight VBE Tracking

4003
.0045 x .0045
.0035

.0035

·j:---C-O-LL-EC-T-O-RII-,-b. . .=tii;i....,...,,..,..,,=c--ISOLATION
COLLECTOR

PIN CONFIGURATION

/12 TYP 2 PLACES
.0045 x .0045
.0035
.0035
BASE,2 TVP 2 PLACES

.025

I

TO-71
TO-78

~---.,.c..,<--"<-"""
BAse,,1

:~~~ DIAMETER
EMITTER.2
.0040
TYP 2 PLACES .0030

EMITTERlf1

DIAMETER
CTOO3511

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Collector-Base Voltage (Note 1) .......................... 45V
Collector-Emitter Voltage (Note 1) ........................ 45V
Emitter Base Voltage (Notes 1 and 2) .................... 7V
Collector Current (Note 1) ................................ 50mA
Collector-Collector Voltage .................................. 60V
,Storage Temperature Range ............ -65°C to +200°C
Operating Temperatur.e Range ......... -55°C to + 150°C
Lead Temperature (Soldering. 10sec) .............. + 300°C

PCQOO81 I

ORDERING INFORMATION*
TO-78

TO-71

WAFER

DICE

IT120

IT120-T071

IT120/W

IT120/0

TO-78

IT121

IT121-T071

IT121/W

IT121/0

IT122

IT122-T071

IT122/W

IT122/0

ONE
SIDE

PARAMETER

BOTH
SIDES

(25°C unless otherwise noted)
1T120A

SYMBOL

ONE
SIDE

Power Dissipation ........ 250mW
500mW
200mW
400mW
Derate Above
25°C ...................... 1.7mWfOC 3.3mW/oC 1.3mW/oC 2.7mW/oC

'When ordering wafer/dice reler to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS

TO-71

BOTH
SIDES

1T120

IT121

IT122

TEST CONDITIONS

UNIT
MIN MAX MIN MAX MIN MAX MIN MAX

Ie = 101lA, VCE = 5.0V

200

200

80

80

IC = 1.0mA, VCE

225

225

100

100

hFE

DC Current Gain

VSE(ON)

Emitter-Base On Voltage

IC = 101lA, VCE = 5.0V

0.7

0.7

0.7

0.7

VCE(SAT)

Collector Saturation Voltage

IC = 0.5mA, IS = 0.05mA

0.5

0.5

0.5

0.5

1.0

1.0

1.0

1.0

nA

=

5.0V

75

ITA = -55·C

,ICSO

COllector Cutoff Current
ITA = + 150·C

IE=O, VCB= 45V

75

30

30
V

10

10

10

10

/lA

lEBO

Emitter Cutoff Current

IC = 0, VEB = 5.0V

1.0

1.0

1.0

1.0

nA

Cobo

Output Capacitance

IE =0,
VCB =5.0V

2.0

2.0

2.0

2.0

Cte

Emitter Transition
Capacitance

IC=O,
VEB =0.5V

2.5

2.5

2.5

2.5

CC1,C2

Collector to Collector
Capacitance

Vee=O

4.0

4.0

4.0

4.0

IC"C2

COllector to Collector
Leakage Current

Vee = ±60V (Note 3)

10

10

10

10

1=IMHz
(Note 3)

2-77
Note: All typical values have been guaranteed by characterization and are not tested.

pF

nA

2

's

IT120,lr1,22

!: ELECTRICAL cHARACTERISTICS (CONT.)

i

E

1T120A
SYMBOL

PARAMETER

1T120

IT121

IT122
UNIT

TEST CONDITIONS
MIN MAX MIN MAX MIN MAX MIN MAX

VCEO(SUSn

Collector to Emitter
Sustaining Voltage

IC ~ 1,OmA, IB = 0

GBW

Current Gain Bandwidth
Product (Note 3)

Ic
Ic

IVBE1-VBE2 i

Base Emitter Voltage
Differential, .

IIB1-IB21

Base Current Differential

A(VBE1- VBE2)
Ll.T

Base-Emitter

vOltage

Differential

Change with Temperature

=10llA, VCE = 5V
=lmA, VCE = 5V

45

45

45

45

10

10
220

7
180

7

220

V
MHz

180

1

2

3

5

mV

2,5

5

25

25

nA

3

5

10

20

p'vrc

Ic = 10llA, VCE - 5,OV

(Note,3)
TA - -55·C to + 125·C
IC - 10llA, VCE - 5,OV

NOTES: 1, Per transistor.
2. The reverse base-to-emitter voltage must never exceed 7.0 volts and the reverse base-to-emitter current must never exceed 101lA.
3. For deSign reference only, not 100% tested.

2-78
Note: All typical values have been guaranteed by characterization and are not tested.

IT124
Dual Super-Beta NPN
General Purpose Amplifier
FEATURES
•
•
•
•

CHIP TOPOGRAPHY
4003

Very High Gain
Low Output Capacitance
Tight VBE Matching
High GBW

.0045 x .0045
.0035
.0035

-,

COLLECTOR '.1

i:iiiilii=;1i-:::::-:-=:::=-'SOLATION
COLLECTOR
1#2 TYP 2 PLACES
_~ x .0045
.0035
.0035

'l

025

PIN CONFIGURATION

BASE"2 TYP 2 PLACES

~~-

TO-78

DIAMETER

'--- EMITTER'2

.0040

TYP 2 PLACES .0030
DIAMETER
CT003611

ABSOLUTE MAXIMUM RATINGS

ORDERING INFORMATION*

(TA = 25°C unless otherwise noted)
Collector-Base Voltage (Note 1) ............................ 2V
Collector-Emitter Voltage (Note 1) .......................... 2V
Emitter-Base Voltage (Notes 1 and 2) ..................... 7V
Collector-Current (Note 1) ................................ 10mA
Collector-Collector Voltage ................................. 100V
Storage Temperature Range ............ -65°C to + 200°C
Operating Temperature Range ......... -55°C to + 150°C
Lead Temperature (Soldering, 10sec) .............. + 300°C

'When ordering wafer/dice refer to Section 10, page 10-1.

Power Dissipation ...•.................
Derate above 25°C ............... .

E,

e,

c,
PCOOO31 I

TQ.78

ELECTRICAL CHARACTERISTICS

@

ONE SIDE

BOTH SIDES

300mW
2.4mW/oC

500mW
4.0mW/oC

25°C (unless otherwise noted)
LIMITS

SYMBOL

PARAMETER

UNIT

TEST CONDITIONS
MIN MAX
ISOO

Ic = liJA, VCE = IV
hFE

DC Current Gain

IS00

VSE(ON)

Emitter-Base "ON" Voltage

VCE(SAT)

Collector Saturation Voltage

ICBO

Collector Cutoff Current

I
I

TA= -SS·C

600

IC = 10iJA, VCE = IV

0.7
IC = lmA, IB = O.lmA
TA =

+ ISO·C

O.S
100

IE=O, VCB=IV

lEBO

Emitter Cutoff Current

IC = 0, VEB = SV

Cabo

Output Capacitance (Note '3)

IE-O, VCB-IV

Cte'

Emitter Transition Capacitance (Note 3)

IC = 0, VEB = O.SV

CC1 C2

Coilector to Collector Capacitance (Note 3)

VCC=O

IC1C2

Collector to Collector Leakage Current

VCC - ±SOV

Current Gain Bandwidth Product (Note 3)

tv
Ic = 100iJA, VCE = tv

NF

Narrow Band Noise Figure (Note 3)

Ic = IOiJA, VCE = 3V,
f= 1kHz. RG = 10kf!
BW = 200Hz

BVCBO

Collector-Base Breakdown Voltage

BVEBO (Note 2)
VCEO(SUST)

Emitter-Base Breakdown Voltage

IC - 10iJA. IE - 0
IE = 10iJA, IC = 0

7

Collector-Emitter Sustaining Voltage

Ic=lrnA.IB=O

2

IC = 10iJA, VCE =

GBW

'2-79
Note: All typical values have been guaranteed by characterization and are not tested.

I

I

V
pA

100

nA

100

pA

O.B
f= IMHz

1.0

pF

O.B
2S0

pA

10
MHz

100
3

dB

2
V

:

11:124

e MATCHING CHARACTERISTICS

@'

25°C (unless otherwise noted)
LIMITS

SYMBOL

PARAMETER
'.

TEST CONDITIONS
.'

UNIT
TYP MAX

;

IVBE1-VBE2 1

Base Emitter Voltage Differential

IC - 101lA. VCE = 1V

2

5

mV

al(VBE1-VBE?!lt aT

Base Emitter Voltage Differential Change with
Temperature (Note 3)
,

Ic = lallA. VCE = tV
T - -55°C to + 125°C

5

15

p.VI'C

IIB1-IB2 11

Base Current Oifferential

Tc-l01lA. VCE -lV

.6

nA

NOTES:

1. Per transistor..
.
2. The reverse base-to-emitle( voltage must never exceed 7.0 volts and the reverse base-to-emitter current must never exceed lallA.
3. For design releren~e only. not 100% tested.

2,.80

Note: All typical values have 1!een guaranteed by eharacteri:zation and are not tested,

IT126-IT129
Dual NPN
General Purpose Amplifier
FEATURES
•
•
•
•
•

CHIP TOPOGRAPHY
4001

High Gain at Low Current
Low Output Capacitance
Tight Ie Match
Tight VBE Tracking
Dielectrically Isolated Matched Pairs for
Differential Amplifiers

EMln.eR
.0029 )( _.0029_
.0039
.0039
TYP 2 PLACES

PIN CONFIGURATION

BASE
.0030 x -:0030
.0040
.0040
TYP 2 PLACES

EMITTER
BASE

TO·71
TO·78

CTOO371 I

ABSOLUTE MAXIMUM RATINGS
(TA = 25'C unless otherwise specified)
Collector-Base Voltage (Note 1)
IT126, IT127 ........................................... 60V
IT128 .................................................... 55V
IT129 .........................................•.......... 45V

COllect~+;~~:tt~l ~~~~~~~.. ~~~.t~ ..1.~ ........................ 60V
IT128 ..................................................... 55V
IT129 .................................................... 45V
Emitter-Base Voltage (Notes 1 and 2) ................... 7.0V
Collector Current (Note 1) ............................... 1OOmA
Collector-Collector Voltage .................................. 70V
Storage Temperature Range ............ -65'C to + 175'C
Operating Temperature Range ......... -55'C to + 175'C
Lead Temperature (Soldering. 10sec) .............. +300'C

ORDERING INFORMATION*
T078

1°-71

WAFER

DICE

IT126

IT126-T071

IT126/W

IT126/0

IT127

IT127-T071

IT127/W

IT127/0

IT128

IT128-T071

IT128/W

1T128/0

IT129

IT129-T071

IT129/W

1T129/0

T071

PARAMETER

BOTH
SIDES

250mW
1.7
mW/'C

500mW
3.3
mW/'C

IT127

IT128

IT129

TEST CONDITIONS
Ic = 10/'A, VCE = 5V
Ic = LOrnA, VCE = 5V
Ic = lOrnA, VCE = SV
IC = SOmA, VCE = SV
Ic = lmA. VCE = SV
IC = lOrnA, Vce = SV
Ic - SOmA. VCE - SV
IC = lOrnA, Ie = lmA
IC - SOmA, Ie - SmA
Ie = 0, Vce - 4SV, 30V'

hFE

DC Current Gain

VeE(on)

ITA = -SS'C
Emitter·Base On Voltage

VCE(sat)

Collector Saturation Voltage

Iceo

Collector Cutoff Current
ITA - + lS0·C
Emitter Cutoff Current
Ic = 0, VEe = SV

IEeo

ONE
SIDE

(25'C unless otherwise noted)
IT126

SYMBOL

BOTH
SIDES

Total Dissipation at 25'C...... 200mW' 400mW
1.3
2.7
Derating Factor ................... mW/'C mW/'C

'When ordering waferldice refer to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS

ONE
SIDE

Power Dissipation

T078

2-Bt
Note: All typical values have been guaranteed by characterization and are not tested.

UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
150
150
100
70
200 800 200 800 ISO 800 100
170
lIS
230
230
100
100
7S
SO
7S
7S
60
40
0.9
0.9
0.9
0.9
1.0
1.0
1.0
1.0
0.3
0.3
0.3
0.3
1.0
1.0
1.0
1.0
0.1
0.1
0.1
0.1'
0.1
0.1
0.1
0.1'
0.1
0.1
0.1
0.1

V

nA
/'A
nA

r:.
r.-

...~ IT12S-IT129·

.

...t:

···.D~OlL

I,i

.&'<1

'f",1'

ELECTRICAL· CHARACTERISTICS (CONT.)·
IT126
PARAM~T~R

SYMBOL

IT127

IT128

IT129
UNIT

TEST CONDITIONS
MIN MAX MIN MAX MIN MAX MIN MAX

Cobo

output Capacitance (Note 3)

Ie = 0, vcs = 20V

BVC1 C2

Collector to Collector Breakdown
Voltage

IC - ±lpA

Collector to Emitter Sustaining
. Voltage

3

3

3

3

±100

±100

±IQO

?;1?0

Ic=lmA,ls=O

60

60

55

45

BVCBO

Collector Base Breakdown
Voltage

IC = 10pA, Ie = 0

60

60

55

45

BVESO

Emitter Base Breakdown Voltage

IE = 10pA, Ic = 0

7

7

7

7

VceO(sust)

pF

V

MATCHING CHARACTERISTICS
IT126
SYM.BOL

PARAMETER

IT127

IT128

IT129
UNIT

TEST CONDITIONS
MIN MAX MIN MAX MIN MAX MIN MAX

IVSE1-VSE21

Base Emitter Voltage Differential

.1(IVsel·VSE21)

Base Emitter Voltage Differential
Change with Temperature (Note 3)

AT
Ils1-1621

Base Current Differential

IC -lmA, VCE = 5V

1

2

3

5

mV

IC = lmA, VCE = 5V
TA - _55°C to + 125°C

3

5

10

20

,.VfOC

= 5V

2.5

5

10

20

nA

Ic = lmA, VCE - 5V

0.25

0.5

1.0

2.0

pA

Ic = 10pA, VCE

NOTES: 1. Per tnsnsistor.
2. The reverse base-to-emitter voltage must never exceed 7.0 volts and the reverse base-to-emitter current must never exceed 10pA.

3. For design reference only, not 100% tested.

2-132
Note: AU typical values have been guaranteed by characterization and are not tested.

IT130-IT132
Dual PNP
General Purpose Amplifier
FEATURES
•
•
•
•

CHIP TOPOGRAPHY

High hFE at Low Current
Low Output Capacitance
Tight IB Match
Tight VBE Tracking

4503

.0045

x

.0035

.0045

.0035

'!:--------i-_.=iitl--=:c;-;:="""'SOLATION
CgLlECTOR'l f..1
COLLECTOR

PIN CONFIGURATIONS

.2 TYP 2 PLACES

::~

.Of5

TO·71
TO·78

•

x

:~~~

BASE '2 TVP 2 PLACES

~~~

BASE 11

DIAMETER

EMITTER 112
.0040
TVP 2 PLACES .0030'

EMITTER.1

DIAMETER
CTO03811

ABSOLUTE MAXIMUM RATINGS
E,

B,

(TA = 25°C unless otherwise specified)
Collector-Base Voltage (Note 1) .......................... 45V
Collector-Emitter Voltage (Note 1) ........................ 45V
Emitter Base Voltage (Notes 1 and 2) .................... 7V
Collector Current (Note 1) ................................ 50mA
Collector-Collector Voltage .................................. 60V
Storage Temperature Range ............ -65°C to + 175°C
Operating Temperature Range ......... -55°C to + 175°C
lead Temperature (Soldering. 10sec) .............. + 300°C
To-71
T0-78

c,
PC00241 I

ORDERING INFORMATION*
TO-78

TO-71

IT130A

1T130A-T071

WAFER

DICE

IT130AlW

IT130A/D

IT130

IT130-T071

IT130/W

IT130/D

IT131

IT131-T071

IT131/W

IT131/D

IT132

IT132-T071

IT132/W

IT132/D

PARAMETER

BOTH

ONE
SIDE

SIDES

(25°C unless otherwise noted)
IT130A

SYMBOL

SIDES

200mW
400mW
250mW
500mW
Power Dissipation ........ 1.3mW/oC 2.7mWrC 1.7mW/oC 3.3mW/oC

·When ordering wafer/dice refer to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS

BOTH

ONE
SIDE

IT130

1T131

IT132

TEST CONDITIONS

UNIT
MIN MAX MIN MAX MIN MAX MIN MAX

Ic= 10llA, VCE = 5.0V

200

200

80

80

IC = 1.0mA, VCE = 5.0V

225

225

100

100

= 5.0V
= 5.0V

75

hFE

DC Current Gain

VBE(ON)

Emitter·Base On Voltage

IC - 10llA, VCE

VCE(SAT)

Collector Saturation Voltage

IC - 0.5mA, IB = 0.05mA

ICBO

Collector Cutoff Current

ITA = -55·C

ITA =
lEBO
Cob (Note 3)

+ 150·C

IC -101lA, VCE

75

30

30

0.7

0.7

0.7

0.7

0.5

0.5

0.5

0.5

-1.0

-1.0

-1.0

-1.0

nA

-10

-10

-10

-10

IlA

-1.0

-1.0

-1.0

-1.0

nA

= 5.0V

2.0

2.0

2.0

2.0

IE = 0, VCB = 45V

Emitter Cutoff Current

IC - 0, VEB = 5.0V

Output CapacHance

IE = 0, VeB

Gte (Note 3)

Emitter Transition Capacitance

Ic = 0, VEB = 0.5V

2.5

2.5

2.5

2.5

CC1-C2 (Note 3)

Collector to Collector
Capacitance

Vee=O

4.0

4.0

4.0

4.0

IC1-C2

Collector to Collector Leakage
Current

Vee - ±60V

10

10

10

10

VCEO(SUST)

Collector to Emitter Sustaining
Voltage

IC = 1.0mA, IB = 0

GBW

Current Gain
Bandwidth Product (Note 3)

IVBE1-VBE2'

Base Emitter Voltage
Differential

-45

-45

-45

-45

IC = 10llA, VCE = 5V

5

5

4

4

IC = 1mA, VCE = 5V

110

110

90

90

Ic = 10llA, VCE = 5.0V

2-83
Note: All typical values have been guaranteed by characterization arfd' are not tested.

1

2

3

V

pF

nA
V
MHz

5

mV

II

IT130A
PARAMETER

SYMBOL

1T130

IT131

IT132

TEST CONDITIONS

UNIT
MIN MAX MIN MAX MIN MAX MIN MAX

IIB1-IB21

Base Current Differential

IC = 101lA. VCE ~ 5.0V

a(VBE,-VBE2)1 aT

Base-Emitter Voltage Differential
Change with Temperature
(Note 3)

TA = _55°C to + 125°C
Ic = 101lA. VCE = 5.0V

.

NOTES: 1. Per transistor.

2.5

5

25

25

nA

3

5

1Ct

20

,.VloC

,
2. The reverse base-to-emitter voltage must never exceed 7.0V. and the reverse base-to-emitter current must never exceed 101lA.
3. For design reference only. not 100% tested.

2~

Note: All

typic81

values have been guaranteed by characterization and are not tested.

IT136-IT139
Dual PNP
General Purpose Amplifier
FEATURES
•
•
•
•
•

CHIP TOPOGRAPHY

High Gain at Low Current
Low Output Capacitance
Tight Is Match
Tight VSE Tracking
Dielectrically Isolated Matched Pairs for
Differential Amplifiers

4501

R

1- -1
033

EMITTER .0029 ,

PIN CONFIGURATION

EMITTER

.0039

TVP 2 PLACES

.9!l~

I
-L

TO·71
TO·78

.0029

.0039

.023

BASE .

.0040

COLLECTOR

x

-:.9_0~

.0040

TVP 2 PLACES

.09~.~)( _:.~q~

BASE

.0045
.0044
TYP 2 PLACES
CTQ03911

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Coliector·Base Voltage (Note 1)
IT136, IT137 ........................................... 60V
IT138 __ ........ .- ____ ............. __ ... ______ .... __ ... ____ 55V
E.

COllect~~.~~itt~'r' 'v~it~g~" iN~t~' '1'j -- .... -- -- -- --. -- .. -- --. 45V

c,

B.

1T136, IT137.. ________________________________________ . 60V
IT 138 .... ____ . ____ ...... __ ... ______________ ........... __ 55V
IT139 __ ... __ ...... ____ ....... ______ . ________ .......... __ . 45V
Emitter Base Voltage (Notes 1 and 2). ____ .. __ . ______ . __ .7V
Collector Current (Note 1). __ . __ . ____ . ______________ . ____ 100mA
Coliector·Coliector Voltage .. __ . __ ... __ .... ______ .......... __ 70V
Storage Temperature Range __ . ______ ' __ -65°C to + 175°C
Operating Temperature Range ______ . __ -55°C to +175°C
Lead Temperature (Soldering, 10sec) ____ ..... ____ . + 300°C

PC0024U

ORDERING INFORMATION*
TO-78

TO-71

WAFER

DICE

IT136

IT136·T071

IT136/W

IT136/0

IT137

IT137·T071

IT137/W

IT137/0

IT138

IT138·T071

IT138/W

IT138/0

IT139

IT139·T071

IT139/W

IT139/0

TO-71

ONE
SIDE

'When ordering wafer I dice refer to Section 10, page 10-1.

TO·78

ONE

BOTH
SIDES

BOTH
SIDES

SIDE

Power Dissipation ...... __ 200mW
400mW
250mW
500mW
Derate above 25'C ... 1.3mWrC 2.7mW/'C 1.7mW/'C 3.3mWI'C

ELECTRICAL CHARACTERISTICS

(@ 25°C unless otherwise noted)
1T136

SYMSOL

PARAMETER

1T137

IT138

IT139

TEST CONDITIONS

UNIT
MIN MAX MIN MAX MIN MAX MIN MAX

hFE

DC Current Gain
ITA = 55'C

VSE(on)
VCE(sat)

Emitter·Base On Voltage
Collector Saturation Voltage

Ic = 10"A, VCE = 5V

150

Ic = 1.0mA, VCE = 5V

150

= lOrnA,

VCE = 5V

125

Ie = 50mA, VCE = 5V

65

Ic = lmA, VCE = 5V

75

Ic

100

150

800

150

BOO

125

100

70
BOO

70

BO

50

60

40

25

75

60

BOO

40

IC = lOrnA, VCE = 5V

.9

.9

.9

.9

IC = SOmA, VCE = SV

1.0

1.0

1.0

1.0

IC=lmA,IS=·lmA

.3
.6

.3
.6

.3

.3
.6

IC = lOrnA, Is = lmA

2-85
Note: All typical values have been guaranteed by characterization and are. not tested.

.6

V

r:.
r.-

IT136·IT139 ,:
ELECTRICAL CHARACTERISTICS (CO NT.)
IT136
SYMBOL

PARAMETER

IT137

IT138

IT139

TEST CONDITIONS

UNIT
MIN MAX MIN MAX MIN MAX MIN MAX

ICBO

Collector Cutoff Current

lEBO

ITA -' + 150°C
Emitter Cutoff Current

IC = 0, VEB = 5V ,

Cobo

Output Capacitance (Note 3)

IE - 0, VCB - 20V, f -1MHz

BVc,C2

Collector to Collector
Breakdown Voltage

le=±1p.A

VeEO(sust)

Collector to Emit,ter
Sustaining Voltage

BVeBO

Collector Base Breakdown
Voltage

BVEBO
1VBE,-VBE21

0.1

0.1

0.1

0.1"

nA

0.1

0.1

0.1

0.1"

p.A

0.1

0.1

0.1

0.1

nA

3

3

3

3

pF

±100

±100

±100

±100

le=1mA,IB=0

60

60

55

45

Ie = 10p.A, IE = 0

60

60

55

45

Emitter' Base Breakdown
Voltage

IE = 10p.A, Ie = 0

7

7

7

7

Base Emitter Voltage
Differential

Ie = 1mA, VeE = 5V

1

2

3

5

mV

Ic = 1mA, VeE = 5V
TA = _55°C to + 125°C

3

5

10

20

IlV/oC

Base Emitter Voltage Differential
~1(VBE,-VBE2~/~T Change with Temperature
(Note 3) .
,
1IB,-1821

IE'= 0, VCB = 45V, 30V"

Base Current Differential

V

Ie = 10p.A, VeE = 5V

2.5

5

10

20

nA

Ie = 1mA, VeE = 5V

.25

.5

1.0

2.0

p.A

NOTES: 1. Per transistor.
2. The reverse base-to-emitter voltage must never exceed 7.0 volts and the reverse base-to-emitter current must never exceed 10p.A.
3. For design reference only, not 100% tested.

2-86
Note: All typical values have been guaranteed by characterization and' are not tested.

IT500-IT505
Dual Cascoded N-Channel JFET
General Purpose Amplifier
GENERAL DESCRIPTION

FEATURES

A low noise, low leakage FET that employs a cascode
structure to accomplish very low IG at high voltage levels,
while giving high transconductance and very ,high common,
mode rejection ratio.

•

CMRR

•
•
•

IG < 5pA @ 50VDG
Crss < O.5pF
gos > .025/lB

PIN CONFIGURATION

> 120dB

CHIP TOPOGRAPHY
6028

TO·71
low profile
BODY
.00301A

DRAIN 1

-T' ~.I~J·003X'003
ii~I

~~~SOURCE1

~~ '003 ~2~~'iiJ1Ij

003

DRAIN 2
003 x

G,

0,

/11

111111'

033 003
x

~.-r--.J ~~; ~

~

'\

SOURCE 2
.003)( .003

s,

CT00411i

PCOO261 I

ABSOLUTE MAXIMUM RATINGS
(TA ':' 25·C unless otherwise specified)
Drain-Source and Drain-Gate
Voltag~s (Note 1) .................... ; ........................ 60V
Drain Current (Note 1) .................................... 50mA
Gate-Gate Voltage ........................................... ±60V
Storage Temperature .... , ................. -65·C to +200·C
Operating Temperature ................... - 55·C to + 150·C
Lead Temperature (Soldering, 10sec) .............. + 300·C
ONE SIDE
BOTH SIDES

SCHEMATIC DIAGRAM

~~-----+--i-CASE
08000311

Power Dissipation (Note 3) ........
Derate above 25·C................

ORDERING INFORMATION*
To-71
IT500

WAFER
IT500/W

DICE
IT500/D

IT501

IT501/W

IT501/D

IT502

IT502/W

IT502/D

IT503

IT503/W

IT503/D

IT504

IT504/W

IT504/D

IT505

IT505/W

IT505/D

250mW
3.8mWI"C

500mW
7.7mW/oC

NOTE 1. Per transistor.
NOTE 2. Due to the non·symmetrical structure of these devices, the

drain and source ARE NOT interchangeable.
NOTE 3. @ 85°C free air temp.

'When ordering wafer/dice refer to Section 10, page 10-1.

2-87
Note: All typical values have been guaranteed by characterization and are not tested:

·D~Dlb

','

',f

ELECTAICAL CHA'RACTEFUSTIcS (@

25°C

unle~s' otherwise

',.

'.;.

specified)

.,

",

",

.,

,

LIMITS
SYMBOL

CHARACTERISTICS

1EST CONDITIONS

UNIT
MIN MAl!-

=125°C

IGSS

Gate Reverse Current

BVGSS

Gate-Source Breakdown Voltage

VGS(off)

Gate-Source Cutoff Voltage

VGS

Gate-Source Voltage.

IG

Gate Operating Cun:ent

. ITA

YGS = -20V, "DS

.'

=: 0

IG = -l/lA, VOS= 0

-60

VOS = 20V, 10 = lnA

-0.7

-100

pA

-5

nA

-4

V

-0.2. -3.8.

'.

-5

VOG = 50V, 10 = 200/lA
ITA = 125°C
loss

Saturation Drain Cun:ent. (Note 1)

VOS = 20V, VGS = 0

0.7

9fs

Common-Source Forward Tr!\nsconductance
(Note 1) .

VOS = 20V, VGS = 0

1000

9fs

Common-Source Forward Transconductance
(Note 1)

VOG = 20V, 10 = 200/lA

700

pA

-5

nA

7

rnA

4000

-

1600

1= 1kHz
gas

Common-Source 'Out)'rut Conductance

VOS = 20V, VGS" 0

gas

Common-Source' ,Output Conductance

Vos .. 20V, 10 ~ 200/lA

Cg lg2

Gate to Gate Capacitanca (Note 4)

VGI = VG2 = 10V

Cis.

Common-Source Inpul

Crss

Common-Source Reverse Transler Capacitance
(Note 3, 4)

NF

Spot Noise Figure (Not~ 4)

Capactt~nce

/lS
1
0.025
3.5

(Note 4)

1= lMHz

pF

7
pF

0.5
VOS = 2OV; VGS = 0

en

I = 100Hz,
RG = 10Mn

.Equivalent Input Noise. Voltage (Note 4)

IT500
SYMBOL

CHARACTERISTICS

IT501

0.5

dB

1= 10Hz

0.Q35

1= 1kHz

0.010

IT502

IT503

IT504

/lV

.1Hz

IT505

TEST CONDITIONS

UNIT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

IG1-IG2

Differential Gale
Cun:ent

VOG= 20V,
10 = 200/lA

10SSl
-I05S2

Saturation' Drain Cun:ent
Ralio. (Note 1)

VOS = 20V, VGS = OV

9fsl / gis2

Transconductance Ratio
(Note 1)

VGS1-VGS2

Differential Gate-Source
Voltage

AVGS1-VGS2

Gate-Source Differential
Voltage

+ 125°C

f= 1kHz

VOG= 20V
10" 200/lA

5

5

5

5

10

15

0.95

1

0.95

1

0.95

1

0.95

1

0.9

1

0.85

1

0.97

1

0.97

1

0.95

1

0.95

1

0.90

1

0.85

1

5

5

10

15

25.

50

TA = 25"C
Te" 125"C

5

10

20

40

100

200

TA = -55"C
Te=25"C

5

10

20

40

100

200

/mV

/lVrC

AT
Change with Temp.
(Note 2, 4)
Common Mode Rejection
Ratio (Note 4)

CMRR··

A Voo = 10V, 10 = 200/lA

120

120

120

•• CMRR = 20 log10AV001 A [Vgsl-Vgs21, AVOO = 10/-20V

NOTES:

nA

1.
2.
3.
4.

Pulse lest required, pulsewidth = 300j.lS, duty cycle", 3%.
Measured at end points, TA and Te.
With case guarded Crss is typically < 0.15pF.
For design relerence only, not 100% tested.

2-88
Note: All typical values have been guaranteed by characterization and are not tested-

120

120

120

dB

IT500-IT!$05
TYPICAL PERFORMANCE CHARACTERISTICS
OUTPUT CHARACTERISTICS

GATE LEAKAGE

.."
r
i yt
~

IO·~A I--

u

7

_v

r

20"·30

40

SO

-a.tv
vOS·-O.1V
vos·-O.IV
VOS·-UN
VOl- -1.2V

Yos. -ttY
vos' -!.IV

0

o

10

VDII-DRAIN-GATE VOLTAGE - VOLTS

10

0P002211

TYPICAL CAPACITANCE VS. GATEoSOURCE
VOLTAGE

OUTPUT CHARACTERISTICS

10

~ Z.O

1

...

I

1,\

B 1.5
w
:il
~

~

c

~

~

0

1"-.
a

I I I I

.

VD~:~_ l-

f~ •

\

0."

I

~

~

z

r\

~ '0

-0.& -1.0

-1.5

-2.0

=
--

DRAIN TO SOURCE VOLTAGE

0P002111

2.0

I

VOS.

,

1,·0
I 0.0

I

VOS. -D.N

,

1.5

~

10

vo.Jov

~ 2.0

TA· 25~C

o

-2.1

to.

...~
o

-2

-t

...

...

-10

Yos-GATE SOURCE YOLTAGE-VOLTS

Vos-GATE-8OURCE VOLTAGE-VOLTS

OP~1I

OPOO2311

2-89
Note: All typical values have been guaranteed by characterization and are not tested.

PI

JlltS.c);,'
t: Dual N-Channel JFET Switch

~

FEATURES
•
•
•

D~nll:l
.

','

'

.

.

,,

CHIP TOPOGRAPHY

Specified Matching Ch,aracterlstics
High Gain
Low "ON" Resistance,

6033

PIN CONFIGURATION
1'0-71

30

CTOO4011

ABSOLUTE MAXIMUM RATINGS
G.

(25°C Unless otherwise noted)
Gate-Drain crGate-Source Voltage .................... -40V
Gate Current .............. , ............ , ..................... 50mA
Gate-Gate Voltage ................... ;·....................... ±80V
Storage Temperature Range ............. -65°C to +200°C
Operating Temperature Range ......... -55°C to +175°C
Lead Temperature (Soldering; 10sec) .............. +300°C
ONE SIDE
BOTH SIDES

0.
PCOO0511

ORDERING INFORMATION*

Power Dissipation .................... .
Derate above 25°C .............. ..

325mW
2.2mW'oC

650mW
4.3mW'oC

·When ordering wafer/dice refer to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS (25°C unless otherwise noted)
LIMITS
SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
MIN

IGSSR

Gate·Reverse Current

VGS = -20V, Vos = 0
ITA = 150·C

MAX
-100

pA

-200

rnA

-3

V

lOSS

Saturation Drain Current (Note 1)

= -lIlA, VOS = 0
= 15V, 10 = InA
VOS = OV, IG = 2mA
VOS = 15V, VGS = 0

rOS(on)

Static Drain Source ON Resistance

10= 1rnA, VGS=O

gts

Common-Source Forward

gos
Crss

Common-Source Reverse Transfer CapaCitance

f=IMHz

3

Ciss

Common-Source Input CapaCitance

(Note 4)

12

NF

Spot Noise Figure (Note 4)

f=10Hz, Rg =IM

1.0

en

Equivalent Short Circuit Input Noise Voltage
(Note 4)

f= 10Hz

50

BVGSS

Gate-Source Breakdown Voltage

VGS(off)

Gate-Source Cutoff Voltage

VGS(I)

Gate-Source Voltage

IOSS1

-IOSS2

IG

'-40

VOS

-0.5

1.0
5
f= 1kHz

7500

Transconductance (Note 1)

f = 100MHz (Note 4)

7000

Common-Source Output Conductance

f= 1kHz

Saturation Drain Current Ratio (Notes I, 2)

VOG = 15V, 10 = 2mA

VOS

= 15V,

VGS = 0

2-90
Note: All typical values have been guaranteed by characterization, and are' not tested;' ;'

30

rnA

100

n

12,500
I'S

45

0.95

I

pF
dB
nV

-

v'Hz

-

IT550
ELECTRICAL CHARACTERISTICS (CO NT.)
LIMITS
SYMBOL

UNIT'

TEST CONDITIONS

PARAMETER

MIN
IVGS1-VGS2 1
 100dB

CHIP TOPOGRAPHY
4003

TO-71

TO·78

:=x::: . ',

llc---;;CO;;L~LE~C;:;;To;R~'~1:J:i.;:;:I-:o=-""";==-"SOLATION
COLLECTOR
t2 TYP 2 PLACES
.0045 x .0045

.025

.0035

J

.0035

BASE '2 TYP 2 PLACES

: : : OIAMETER
BASEj1
EMITTER It2
.0040
TYP 2 PLACES .0030

EMITTER"1

DIAMETER
CT003511
PCOO081f

ABSOLUTE MAXIMUM RATINGS
(TA = 25·C unless otherwise noted)
Collector-Base Voltage (1) .................................. 45V
Collector-Emitter Voltage (1) ............................... 45V
Collector-Collector Voltage .................................. 45V
Emitter-Base Voltage (1) ...................................... 6V
Collector Current (1) ....................................... 20mA
Storage Temperature Range ............ -65·C to +200·C
Operating Temperature Range ......... -55·C to + 150·C
Lead Temperature (Soldering, 10sec) .............. + 300·C
Power Dissipation (Tc = 25·C) ......................... 800mW
Derate above 25·C ........................... 14mW I"C

ORDERING INFORMATION*
TO-71

T0-78

WAFER

DICE

LM114

LM114H

LM114/W

LM114/D

LM114A

LM114AH

'When ordering wafer/dice refer to Section 10, page lCJ.:-1.

ELECTRICAL CHARACTERISTICS

(NOTE 2)
MAXIMUM LIMITS

PARAMETER

SYMBOL

TEST CONDITIONS

LM114A,
AH

LM114,
H

UNIT

VSEl-2

Offset Voltage

ll1A:$ Ic:$ l0011A

0.5

2.0

mV

IS·2

Offset Current

IC - 1011A

2.0

10

nA

Ie = lIlA

0.5

40

nA

Bias Current
IlVSEIV

Offset Voltage Change

IlVSEIV

Offset Current Change

Ie ~ 1011A

20

Ie -lIlA

3.0

OV:$ VCS :$ VMAX, IC = 1011A

0.2

1.5

mV

1.0

4.0

nA

2-102
Note: All typical values have been guaranteed by characterization and are not tested.

LM114/H, LM114A/ AM
ELECTRICAL CHARACTERISTICS (CONT.)
MAXIMUM LIMITS
SYMBOL

PARAMETER

AVBE/AT

Offset Voltage Drift

AIBl_2/ AT

Offset Current

TEST CONDITIONS

-55·C S TA S + 125·C, Ic = 101lA

AlB/AT

Bias Current

ICBO

Collector-Base Leakage Current

VCB=VMAX

ITA = 125·C (Note 3)
ICEO

Collector-Emitter Leakage Current

VCE = VMAX. VEB = OV

Collector-Collector Leakage Current

Vcc= VMAX

ITA = 125·C (Note 3)
NOTES:

LM114,
10

12

50

60

150

nA

10

nA

50

50
50'
200

50

200

nA

100

300

pA

100

300

nA

1: Per transistor.
2: These specifications apply for TA = + 25·C andOV S VCB S VMAX. unless otherwise specified. For the LM114 and LMI14A.
VMAX = 30V.
3. For desi!!n reference only. not 100% tested.

2-103
Note: All typical values have been guaranteed by characterization and are not tested.

UNIT

H

2.0

10

ITA = 125·C (Note 3)
IC1-C2

LM114A,
AH

,NrC

pA
pA

..... '., '10.'
-.·.S,·'
.'. ····O·.ru
• . .,o~'·.····

, M118
i Diode Protected N-Channel

i.'
.

,.

" .

,

! .,

•

Enhancement· Mode MOSFET
General' "purpose Amplifier
FEATURES

CHIP- TOPOGRAPHY

•

Log IGSS .

•

Integrated Zener

Clamp

1003

for Gate Protection

PIN CONFIGURATION
T0-72

m

G .0025

x .0029

.0035

.0039

.J...L+-'----'\,-'O .0030 , .()()28
IS BODY

.0040

.()()38
CTOO451t

ABSOLUTE MAXIMUM RATINGS

eGo

(TA = 2S0C unless otherwise noted)

PGOO2711

Drain to Source Voltage .................................... 30V
Gate to Drain Voltage ....................................... 30V
Drain Current ................................................. SOmA
Gate Zener Current ..................................... ±0.1 mA
Storage Temperature Range ............ -6SoC to + 200°C
Operating Temperature Range ......... -SsoC to + 150°C
Lead Temperature (Soldering, 10seo) .............. + 300°C
Power Dissipation ......•.................................. 22SmW
Derate above 2SoC .......................... 2.2mWrC

ORDERING INFORMATION*

'When ordering wafer/dice refer to Section 10, page 10-1.

DEVICE SCHEMATIC

tp::
4

0SD00411

ELECTRICAL CHARACTERISTICS

(25°C unless otherwise noted, Vas = 0)
M116

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
MIN MAX

vGS = 2OV, 10 = 100llA, ves = 0

100
I 200

n

rOS(on)

Drain Source ON Resistance

VGS(lh)

Gate .Threshold Voltage

VGS = VOS, 10 = 10llA, VBS = 0

BVOSS.

Drain-Source Breakdown Voltage

10 = lIlA, VGS = VBS· 0

30

BVsos

Source-Drain Breakdown Voltage

IS=lllA, VGO=VBO=O

30

BVGBS

Gate-Body Breakdown Voltage

IG - 10llA, VSB = VOB = 0

30

10(OFF)

Drain Cutoff Current

VOS = 20V, VGS = VBS = 0

10

IS(OFF)

Source Cutoff Current

VSO - 20V, VGO = VBO = 0

10

IGSS
Cgs

Gate-Body Leakage

VGS

=0

100

pA

Gate-Source (Nole 1)

VGe = Voe = Vse = 0, f = 1MHz

Cgd

Gate-Drain Capacitance. (Note 1)

Body Guarded

Cdb

Drain-Body Capacitance (Note 1)

VGe = 0, Voe

2.5
2.5
7

pF

Ciss

Input Capacitance (Note 1)

VGB=O, Voe=10V, Ves-O, f-1MHz

VGS

= 10V,

= 20V,

NOTE 1: For design reference only, not 100% tested.

2-104
Note: All typical values have been guaranteed by characterization and are not tested.

10 = 100llA, Ves = 0

VOS = VBS

= 10V,

f= lMHz.

1

5
V
60

10

nA

U200-U202

N-Channel JFET Switch
FEATURES

APPLICATIONS

•
•

•
•
•

Low Insertion Loss
Good OFF Isolation

PIN CONFIGURATION

Analog Switches
Commutators
Choppers

CHIP TOPOGRAPHY
5001

TO-18
.00135 FULL RADIUS

.00175 (DRAIN)

)(

.oo~

.0026

(SOURCE)
CT000911

o
PC000611

ABSOLUTE MAXIMUM RATINGS
ORDERING INFORMATION*
TO-18
U200

U200/W

DICE
U200/0

U201

U201/W

U201/0

U202

U202/W

U202/0

WAFER

(TA = 25°C unless otherwise noted)
Gate-Drain or Gate-Source Voltage ................. ,,' -30V
Gate Current ......... "., .................................... 50mA ~
Storage Temperature Range ......... , .. -65°C to + 200°C ~
Operating Temperature Range ......... -55°C to + 150°C
Lead Temperature (Soldering. 10sec) "."" ....... + 300°C
Total Device Dissipation (TC = 25°C) " ........ ",,: .... 1.8W
Derate above 25°C ... " ...................... 10mWrC

'When ordering waler I dice rlller to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS

(25°C unless otherwise noted)
U201

U200
SYMBOL

PARAMETER

UNIT
MIN

IGSS

Gate Reverse Current

VGSS = 20V, Vos = 0

ITA = 150'C
BVGSS

Gate-Source Breakdown Voltage

IG = -1jJ.A, VOs=O

-30

VGS(off)

Gate·Source Cutoff Voltage

VOS = 20V, 10 = 10riA

-0.5

10(011)

Drain Cutoff Current

VOS = 10V, VGS = -12V

lOSS

ITA = 150'C
Saturation Drain Current (Note 1)

VOS = 20V, VGS = 0

rds(on)

Drain-Source ON Resistance

VGS = 0, 10 = 0

Ciss

Common-Source Input
Capacitance (Note 2)

VOS = 20V, VGS = 0,

erss

Common-Source Reverse
Transfer Capacitance (Note 2)

VOS=O:
VGS= -12V

NOTES:

U202

TEST CONDITIONS
MAX

MIN

-1

-1

nA

-1

-1

-1

"A

-30
-3

-1.5

25

-30
-5

-3.5

1
15

75

-10

1

1

1
f= 1kHz

MIN .MAX

-1

1

3

MAX

30

1

jJ.A

lPO

rnA
ohm

150

7$

50

30

30

30

8

8

8

f=IMHz

1: Pulse test required, pulsewidth = 300"., duty cycle S 3%.
2. For design reference only, not 100% tested.

2-105
Note: All typical values have been guaranteed by characterization and are not tested.

V
nA

pF

U231-U235,
!=: General
Dual ·N..;ehannel JFET
Purpose Amplifier
fJ

9

FEATURES

APP.LICATIONS

•

•
•

Good Matching Characteristics

PIN CONFIGURATION

Differential Amplifiers
Low and Medium Frequency Amplifiers

CHIP TOPOGRAPHY
6037

·10-71

ALL BOND ~AOS ARE 4)( 4 MIL.
CT004811

ABSOLUTE MAXIMUM RATINGS

ORDERING INFORMATION*

(TA = 25·C unless otherwise noted)
Gate-Source or Gate-Drain Voltage (Note 1) •....... -50V
Gate Current (Note 1) .... ; ........................... : .... 50mA
Storage Temperature Range ............ -65·C to + 200·C
Operating Temperature Range ......... -55·C to + 200·C
Lead Temperature (Soldering, 10sec) .............. +300·C
Power Dissipation ......................................... 300mW
Derate above 25·C .......................... 1.7mWI"C

·When ordering wafer/dice refer to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: 25·C unless otherwise noted.
LIMITS
SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
MIN

-100

pA

-500

nA

-0.5

-4.5

V

-0.3

-4.0

IGSS

Gate Reverse Current

BVGSS

Gale-S()urce Breakdown Vollege

IG -IlIA, VOS = 0

-50

VGS(ofI)

Gate-Source Cutoff Voltege

VOS = 20V, 10 - InA

VGS

Gate-SoUrce Voltage

IG

Gate Operating Current '

loSS

Saturation Drain Current (Note 2)

Vos - 20V, VGS - 0

9fs

Common-Source Forward Transconductance
(Note 1)

Vos = 2OV, VGS - 0

Sf.

Common-Source Forward Transconductance
(Note 1)

Voo = 20V, 10 = 2oo11A

90s
90s

Common-Source Output Capacitance

Vos=20V, VGS = 0

CommOn-SourClil Output Conductance

Voo - 20V, 10 - 2001iA

Q..

Common-Source Input CapaCitance

Crss

Common-Source Reverse Transfer Capacitance

I

TA = 150·C

MAX

VGS =-30V, Vos ··0

-50

en

I

pA

VOG = 20V, 10 - 20011A
-250

nA

0.5

5.0

rnA

f= 1kHz

1000

3000

f-looMHz
(Note 4)

1000

TA = 125·C

/.IS
. 600
f= 1kHz

1600

35
10
6

f-1MHz

2

Vos = 2OV, VGS - 0
Equivalent Short CircuH Input Noise Voltage

(Note 4)

2-106
Note: All typical values have been guaranteed by characterization and are not tested.

f= 100Hz

80

pF
nV

-VHz

.D~OIL

U231-U23S
ELECTRICAL' CHARACTERISTICS:tCONT.)
SYMBOL

MATCHING CHARACTERISTICS

= 20V,

IIGI -IG21

Differential Gate Current (Note 4)

VOG

(10551- 10552)

Saturation Drain Current
Match (Note 2, 4)

V05 = 20V, VG5 = 0

10551
IVG51-VG52 1
6.IVGS1- VG52 1
6.T

-glsl
-1gosl-gos21
NOTES:

1.
2.
3.
4.

10 = 2001lA

Differential Gat&-Source Voltage

125°C

TA = 25°C

1.0

10

10

10

10

nA

5

5

5

10

15

%

5

10

15

20

25

mV

10

25

50

75

100

TA = 25°C
Gate-Source Voltage
Differential Diift (Note 3)

TB-125°C

jJvrc
VOG

(glsl-91s2)

U231 U232 U233 U234 U235
UNIT
MAX MAX MAX MAX MAX

TEST CONDITIONS

= 20V,

10 = 2001lA

f~

Transconductance Match (Note 2)
Differential OUtput Conductance
Per transistor.
Pulse test required, pulse width - 3OOjJs, duty cycle
Measured at end pOints, TA and TB
Eor design reference only, not 100% tested.

TA = -55°C
TB = 25°C

~

3%.

2-107
Note: All typical values have been guaranteed by characterization and are not tested.

1kHz

10

25

50

75

100

3'

5

5

10

15

%

5

5

5

5

5

jJS

'too

I

0287
Dual N-Channel JFET
High Frequency Amplifier

.

FEATURES

.U~UI6
;".;"

•

'...

c','

.

CHIP TOPOGRAPHY

-9'.). 5OO0psFrom DC to 100MHz
-

Matched

Vas.

91. and 90s

'

PIN CONFIGURATION\
T0-99

ABSOLUTE MAXIMUM .RATINGS
(TA .: 2S·C unless otherwise noted)
G,

0,

Gate-Drain or Gate-Source Voltage ·(Note 1) ........ -25V
Gate Current (Note 1) .................•................... 50mA
Storage Temperature Range ............ -65·C to + 200·C
Operating Tempe;ature Range ......... -55·C to + 150·C
Lead Temperature (Soldering, 10sec) .. , ........... +300·C

S,
PC00151i

'ORDERING INFORMATION*

ONE SIDE

Power Dissipation
(TA =85·C) .•.......•............ ,...
Derate above 25·C ...••.•......

·When ordering wafer/dice refer to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS
SYMBOL

250mW
3.8mW

500mW
7.7mWrC

rc

(25·C unless otherwise noted)

PARAMETER

TEST CONDITIONS

Gate Reverse Current

IGSSR

BOTH SIDES

MIN MAX UNIT.

VGS -15V, Vos = 0
jTA = 150°C

;...100

pA

-250

nA

BVGSS

Gate-Source Breakdown Voltage

IG - -lpA, Vos- 0

-25

VGS(off)

Gate-Source Cutoff Voltage

Vos-l0V, io-lnA

-1

-5

5

40

V
loss

Saturation Drain Current (Note 2)

Vos -10V, VGS - 0

91.
91s

Common-Source Forward Transconductance

Vos = 10V, 10 - 5mA

I-1kHz

5000 10,()O(

Coinmon.&>urce Forward Transconductance

Voo - 10V, 10" 5mA

1= 100MHz (Note 3)

5000 10,oo!

gas

Common-Source Output Conductance

Vos = 10V, 10 = 5mA

I-1kHz

150

gOBS

Common-Source Output Conductance

1= 100MHz

150

C;s.

Common-Source Input Capacitance

c,i.

Common.&>urce Reverse Transfer Capacitance

Voo -10V, .10 - 5mA

f-1MHz

e;;

Equivalent Input Noise Voltage

(Note 3)

f-l0kHz

-IO$S2

Drain currerit Retio at Zero Gate Voltage
(Note 2)

VOS" 10V, VGS - 0

IVGS1-VGS2 1

Differllntlal Gate-Source Voltage

9181
9102

T~nsconductance Ratio

1900 1-90021

Differential Output Conductance

IOSS1

mA

jill

5
1,2

nV

30

0.85

0.85
f-lkHz

NOTES: 1. Per transIstor.

2. Pulse test nsquired, pulse width = 300jlll, duty cycle $ 3%.
3. For design reference only, not 100% tested.

2-108
Note: All typical values have been guaranteed by characterization and are not tested.

-

~

1
100

Voo -10V, 10 = 5mA

pF

mV

1

20

jill

.D~DIL

U304-U306

P-Channel JFET Switch
FEATURES

APPLICATIONS

•
•
•

•
•
•

Low ON Resistance
ID(off) < 500pA
Switches directly from TTL Logic (U306)

PIN CONFIGURATION

cCot
o

t

c

I

Analog Switches
Commutators
Choppers

CHIP TOPOGRAPHY

_--.021--_

TO·18

- lJ~111!11~'l=
.0027 (0685)

'~~!':~l 0
x
0037 (.0939)
.0027 (.0685)

I

NOTE: SUBSTRATE IS GATE
CT00491!

o

ABSOLUTE MAXIMUM RATINGS

G.C

(TA = 25·C unless otherwise noted)
Gate-Drain or Gate-Source Voltage (Note 1) .......... 30V
Gate Current ................................................. 50mA
Storage Temperature Range ............ -65·C to + 200·C
Operating Temperature Range ......... -55·C to + 150·C
Lead Temperature (Soldering, 10sec) ................. 300·C
Power Dissipation ......................................... 350mW
Derate above 25·C .......................... 2.8mW

PCOO0111

ORDERING INFORMATION*
To-18

WAFER

DICE

U304

U304/W

U304/D

U305

U30S/W

U305/D

U30S

U30S/W

U30S/D

rc

'When ordering wafer/dice refer to Section 10. page 10-1.

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: 25°C unless otherwise noted.
U304
SYMBOL

PARAMETER

U305

U306

TEST CONDITIONS

UNIT
MIN MAX MIN MAX MIN MAX

laSSR

Gate Reverse Current

Vas = 20V, Vos = 0
ITA = 150·C

Gate·Source Breakdown Voltage

la = lIlA. VOS - 0

VaS(off)

Gate·Source Cutoff Voltage

VOS(on)

Drain·Source ON Voltage

VOS= -15V. 10= -11lA
vas 0, 10
15n:A.. \~~04J,
10 = - 7mA (U30S),
10 = -3mA (U306)

lOSS

Saturation Drain Current (Note 1)

VOS=-15V, Vas=O

Drain Cutoff Current

VOS = -15V, VGS = 12V (U304)
VGS - 7V (U305)
VGS = 5V (U306)

ITA = 150·C
r05(on)

Static Drain·Source ON Resistance

VGS=OV, 10= -1mA

rds(on)

Drain·Source ON Resistance

VGS=OV, 10=0

Ciss

Common·Source Input CapaCitance
(Note 2)

VOS= -15V,
VGS=O

Crss

Common·Source Reverse Transfer
Capacitance (Note 2)

VOS = 0, VGS = 12V
(U304)
Vas = 7V
(U305),
VGS= 5V
(U30S)

500

500

pA

1.0

1.0

1.0

IlA

30

BVass

10(0ff)

500

5

f=1MHz

2-109
Note: All typical values have been guaranteed by characterization and are not testE!(!.

10

3

-1.3
-30

f= 1kHz

30

30
6

1

-0.8
-15

-60

4

V

-0.6
-25

rnA

-500

-500

-500

pA

-1.0

-1.0

-1.0

IlA

85

110

175

85

110

175

n
n

27

27

27

7

7

7

-90

-5

pF

PI

8
'"

.j

:11. D~DlL.

U304--U306
.
.

..

..

.

ELECTRiCAL CHARACTERiStiCS (CONT.)

,'"

=

U304·
SYMBOL

PARAMETER

U304
Turn-ON pelay Time (Nole 2)

Ir

Rise Time (Note 2)

lct(oIf)

Turn-OFF Delay Time (Nole 2)

If

Fall Time (Nole 2)

U306
UNIT

MIN
Id(on)

U305

TEST CONDITIONS
U305

MAX MIN MAX MIN MAX

U306

-6V

-6V

20

25

25

7V

5V

15

25

35

743n

laOOn

10

15

20

0
0
VGS(on) 0
-15mA -7mA -3mA
10(on)

25

,40

60

Voo

-10V

VGS(off) 12V
560n
RL

NOTES: 1. Pulse· tesl pulsewidlh ~ 300jtS, duty cycle S 3%.
2. For design reference only, nol 100% lested.

2-flo
Nole: All typical values have been guaranleed by characterizalion and are nol lested.

ns

.U~UIL!

U308-U310
N-Channel JFET
High Frequency Amplifier

..
Co)

o

FEATURES
•
•
•
•

CHIP TOPOGRAPHY

High Power Gain
Low Noise
Dynamic Range Greater Than 100dB
Easily Matched to 7SU Input

~-1 x .0068 G

.0021

.0058

PIN CONFIGURATIONS
TO-52
NOTE: SUBSTRATE
IS GATE

TYP
0035 x 0035
2 PLACES .00,35
.0025
CT00501I

ABSOLUTE MAXIMUM RATINGS
(TA = 25·C unless otherwise noted)
Gate-Drain or Gate-Source Voltage _______________ •.•.. -25V

o

Gate Current ...............................••......••........ 20mA
Storage Temperature ...................... -65·C to +200·C
Operating Temperature Range ......... - 55·C to + 150·C
lead Temperature (Soldering. 10sec) .............. +300·C
Power Dissipation .....•.•..•.•.•......•....•.•.•.••.•.•.•. 500mW
Derate above 25·C .••••.•••..•.•.•......•.•..• 4mW

S
PC001211

rc

ORDERING INFORMATION*
TO-52

WAFER

DICE

U30S

U30S/W

U30S/0

U309

U309/W

U309/0

U310

U310/W

U310/0

·When ordering wafer/dice refer to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS

(25·C unless otherwise noted)

U30a
SYMBOL

PARAMETER

U310

U309

TEST CONDITIONS
MIN TYP MAX MIN TYP MAX MIN

IGSS
BVGSS
VGS(off)
loSS
VGS(f)
9tg

Gate Reverse Current
trA = 125°C
Gate-Source Breakdown
Voltage
Gate-Source Cutoff Voltage
Saturation Drain Current
(Note 1)
Gat....Source Forward
Voltage
Common-Gate Forward
Transconductance (Note 1)

VGs= -15V
VGS=O

-150

pA

-150

-150

nA

-25

-25

Vos=10V,lo¥lnA

-1.0

-6.0 -1.0

-4.0 -2.5

VOS = 10V, VGS = 0

12

60

10

30

17

-6.0

24

1.0
10

17

10

V

60

rnA

1.0

V

17

iJS

1= 1kHz

Cgd
Cgo

Gate-Source Capacitance

VOS= 10V

1= lMHz
(Note 2)

en

Equivalent Short Circuit
Input Noise Voltage

VOS-l0V,
10-10mA

I-100Hz
(Note 2)

VGS - -10V,

12

1.0

Common Gate Output
Conductance
Drain-Gate. Capacitance

gogo

-150

-150
-25

. VOS=10V,
10= lOrnA

UNIT
MAX

-150

IG = -lILA, Vos =0

IG = lOrnA, VOS = 0

TYP

2-111
Note: All typical values have been guaranteed by characterization and are not tested.

250

250

250

2.5

2.5

2.5

5.0

5.0

5.0

iJS

pF

10

10

10

-nV

v'Hz

IIO~OI6
ELECTRICAL CHARACTERISTICS (CO NT.)
U3d9

U308
SYMBOL

PARAMETER

U310
UNIT

TEST CONDITIONS
MIN TYP MAX MIN TYP MAX MIN T,(P MAX

Common-Gate Forward
Transconductance
91g

Ie 100MHz

15

15

15

1- 450MHz

14

14

14

1= 100MHz

0.18

O.Hi

0.18

,/.IS

Common-Gate Output
Conductance

gog.
Gpg

Common-Gate Power Gain

Vos'= 10V,

1=450MHz

10= lOrnA

I -100MHz

14

16

14

16

14

1=450MHz

10

11

10

11

10

(Note 2)
NF

Noise Figure

0.32

0.32

0.32
16
11

f= 100MHz

1.5

2.0

1.5

2.0

1.5

2.0

f=450MHz

2.7

3.5

2.7

3.5

2.7

3.5

NOTES: 1. Pulse test duration = 2ms.
2. For design reference only, not 100% tested.

2-112
Note: All typical values have been guaranteed by characterization and are not tested.

dB

.U~UI6I

U401-U406
Dual N-Channel JFET Switch
FEATURES
•
•
•
•

CHIP TOPOGRAPHY,

Minimum System Error and Calibration
Low Drift With Temperature
Operates From Low Power Supply Voltages
High Output Impedance

Cb

6037

PIN CONFIGURATION
TO-71

"LL BONO PADS ARE' x • MIL.
CTOOO711

ABSOLUTE MAXIMUM RATINGS
(TA = 25·C unless otherwise noted)
S,

Gate-Drain or Gate-Source Voltage ...................... 50V
Gate Current (Note 1) ..................................... 10mA
Storage Temperature Range ............ -65·C to + 200·C
Operating Temperature Range ......... -55·C to + 150·C
Lead Temperature (Soldering, 10see) .............. + 300·C

PC000511

ORDERING INFORMATION*

ONE SIDE

BOTH SIDES

300mW
2.6mWI"C

SOOmW
SmW/·C

Power Dissipation (TA = 8S·C) ... .
Derate above 2S·C ............... .

'When ordering waler/dice reler to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: 25·C unless otherwise noted.
U401
SYMBOL

PARAMETER

U402

U403

U404

U40S

U406

TEST CONDITIONS

UNIT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

BVGSS

Gate-Source Breakdown
Voltage

Vos - 0, IG = -lIlA

IGSS

Gate Reverse Current
(Note 2)

VOS = 0, VGS = -30V

VGS(off)

Gate-Source Cutoff Voltage

VOS -15V, 10 -InA

VGS(on)

Gata-Source Voltage (on)

VOG

loSS

Saturation Drain Current
(Note 3)

VOS = 10V, VGS = 0

IG

Operating Gate Current

VOG - 15V, 10 = 200jiA

(Note 2)

.1

= 15V,

-50

-50
-25

-50
-25

-50
-25

-50

-50
-25

-25

V
-25

pA

-.5 -2.5 -.5 -2.5 -.5 -2.5 -.5 -2.5 -.5 -2.5 -.5 -2.5
V
-2.3

10 = 200jiA

-2.3

-2.3

-2.3

-2.3

-2.3

0.5 10.0 0.5 10.0 0.5 10.0 0.5 10.0 0.5 10.0 0.5 10.0

TA-125°C

rnA

-15

-15

-15

-15

-15

-15

pA

-10

-10

-10

-10

-10

-10

nA

BVG1-G2

Gate-Gate Breakdown
Voltage

VOS - 0, VGS - 0,
IG - ±ljiA

±50

gfs

Common-Source Forward
Transconductance (Note 3)

VOS· 10V,

2000 7000 2000 7000 2000 7000 2000 7000 2000 7000 2000 7000

gos

Common-Source Output
Conductance

VGS=O

91s

Common-Source Forward
Transconductance

90s

Common-Source Output
Conductance

Voo-15V,

Cis.

Common-Source Input
Capacitance (Note 6)

10 = 2001lA

±50

±50

±50

±50

±50

V

1= 1kHz
20

20

20

20

20

20
I'S

1000 1600 1000 1600 1000 1600 1000 1600 1000 1600 1000 1600
1= 1kHz
2.0

2.0

2.0

2.0

2.0

2.0

B.O

B.O

B.O

8.0

B.O

B.O

I=IMHz
Crss

Common-Source Reverse
Transler capaCitance
(Note 6)

pF
3.0

2-113
Note: All typical values have been 9uaranteed by characterization and are not tested.

3.0

3.0

3.0

3.0

3.0

I U40'.U,~~~

,,' ,'" ;

'4- ELECTRICAL CHARACT':FlISTICS (CONT.)

,i::»

'.
SYMBOL

U401
PARAMETER

U402

'U403

U404

U405

TEST CONDITIONS
MIN MAX MIN MAX MIN MAX ,.IN MAX. MIN

U~

MAX MIN MAX

UNIT

en

Equivalent Short-Circuit
Input Noise Voltage

VOS·15V.
VGS=O

CMRR

Common-Mode Rejection
Ratio

Voo - 10 \0 20V,
10 - 200"" (Note 5, 6)

IVGS1- VGS21

Differential c Gate~$ource
Voltage

Voo = 10V. 10 = 200""

5

10

10

15

20

40

mV

Gate-Sour"". Voltage
Dlfferenti!ll Drift (Not!i 4)

ITA = '-55'C
Voo = 10V. T = +25'c'
10 = 200"" Tg = + 125'(;

10

10

25

25

40

80

pV/'C

""'GS1-VGS21

Ll.T

I

f-10Hz
(Note 6)

20

95

95

NOTES: 1. Per transistor.

2. Approximately doubles for every 10'C increase in TA.
3. Pulse test duration = 300"s; duty cycle :;; 3%.
4. Measured at end points. TA, TB. Tc.
5. CMRR=.20 log10 [

20

. AVoo , ] . AVoo = 10V.
AIVGS1"VG82'

6. For design reference only, not 100% ·tested.

2-114
Note: All typical values have been guaranteed by characterization and are not tested.

20

20

95

20

20

90

.1I5

nV
-VRi
dB

U1897~U1899

N-Channel JFET Switch
FEATURES

APPLICATIONS

•
•

•

Low Insertion Loss
No Error or Offset Voltage Generated By Closed
Switch

PIN CONFIGURATION

Analog Switches, Choppers

CHIP TOPOGRAPHY
5001

TO-92
.00135 FULL RADIUS

q

I
L

:00175 (DRAIN),

0072 NOTE

~

--1

~ .016

o

S

~i'~~:::~ATE

~~
---I

.0025 x .0029
.0035
.0026
(SOURCE)

Cro05,'1

G

PCO01311

ABSOLUTE MAXIMUM RATINGS
ORDERING INFORMATION*
TO-92
U1897

TO-92-18
U1897-18

WAFER
U1897/W

(TA = 25°C unless otherwise noted)
Gate-Drain or Gate-Source Voltage _................... -40V
Forward Gate Current ...................................... 10mA •
Storage Temperature Range ............ -55°C to + 150°C
Operating Temperature Range ......... -55°C to + 135°C
lead Temperature (Soldering, 10sec) .............. + 300°C
Power Dissipation ...................................... ; .. 350mW
Derate above 25°C .......................... 3.2mW fOC

DICE
U1897/D

U1898

U1898-18

U18,98/W

U1898/D

U1899

U1899-18

U1899/W

U1899/D

'When ordering wafer/dice refer to Section 10, page 10-1_

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: 25°C unless otherwise noted
U1897
SYMBOL'

PARAMETER

U1898

U1899
UNIT

TEST CONDITIONS
MIN MAX MIN

BVGSS

Gate-Source Breakdown Voltage

IG = -1 #-lA, VOS = 0

IGSS

Gate Reverse Current

VGS = -20V, VOS = 0

-400

-400

-400

1000

Drain-Gate Leakage Current

VOG = 20V, IS = 0

200

200

200

ISGO

Source-Gate Leakage Current

VSG= 20V, 10=0

200

200

200

10(011)

Drain Cutoff Current

VOS - 20V,
VGS= -12V (U1B97)

200

200

200

ITA = B5'C

-40

MAX MIN' MAX

VGS = -BV (U1B9B)
VGS = -6V (U1B99)

-40

10

10
-7.0-

10
-5.0

nA

VOS = 20V, 10 = lnA

-5.0

lOSS

Saturation Drain Current (Note 1)

VOS - 20V, VGS = 0

30

VOS(on)

Drain-Source ON Voltage

VGS = 0, 10 = 6.6mA (U1897)
10 = 4.0mA (U1898)
10 = 2.5mA (U1899)

0.2

0.2

0.2

V

rOS(on)

Static Drain-Source ON Resistance

10=lmA, VGS=O

30

50

BO

n

Cdg

Drain-Gate Capacitance

VOG

5

5

5

CSg

Source-Gate Capacitance

VSG =20V, 10 = 0

Ciss

Common-Source Input Capacitance

Crss

Common-Source Reverse Transfer
Capacitance

15

-1.0

pA

Gate-Source Cutoff Voltage

Is = 0

-2.0

V

VGS(oll)

= 20V,

-10

-40

B.O

5

5

5

f= lMHz

16

16

16

(Note 2)

3.5

3,5

3.5

VOS = 20V, VGS = 0

2-115
Note: All typical values have been guaranteed by characterization and

are~ot

tested.

V
mA

pF

,

I U1897-U1899
;

:::» ELECTRICAL CHARACTERISTICS (CONT.)

,!

::::»..

U1897
SYMBOL

PARAMETER

U1898

UNIT
MIN MAX MIN MAX

'Id(on)

Tum ON Delay Time (Note 2)

Ir

Rise Time (Note 2)

Ioff

NOTES:

Turn OFF Time (Note 2)

U1899

TEST CONDITIONS
MIN

MAX

Switching Time Test Conditions

15

15

20

U1897 U1898 U1899

10

20

40

40

60

80

3V
Voo
0
VGS(on)
VGS(off) -12V
425n
RL
6.6mA
1010nl

3V
0
-8V

3V
0
-BV
non 1120n
4mA 2.5mA

1. Pulse test pulsewidth - 3001-'s; duty cycle < 3%.
2. For design reference only. not 100% tested.

2-116
Note: All typical values have been guaranteed by characterization and are not tested.

ns

,

.O~OIl.I

VCR2N/3P/4N/7N

Voltage Controlled Resistors

-•
Col

APPLICATIONS
•
•
•
•

.'!
z

CHIP TOPOGRAPHY

-...

VCR2N
5001

Small Signal Attenuators
Filters
Amplifier Gain Control
Oscillator Amplitude Control

.00135 FULL RADIUS

.oom (DRAIN)

Z

PIN CONFIGURATIONS
TO·18

TO-71

r--

• .0036

-:0026

--I

.01.

(SOURCE)
CTOO6BOI

VCR7N
5007

-hD15~

::

G

(3) ,

o
PCOOO611

PC000511

.0025 )( .0025
.0035
.0035

-r

T0-72
(N-Ghannel)

TO·72
(P-Ghannel)

.0013 FULLR
.0017
CTOO69OI

VCR3P

5508

,Rrilm~'='.0025

o

.0027

.016

PC004801

PCOO4701

.0037 x .0035 0
.0025

.0027

ORDERING INFORMATION*

.
.

•

NOTE: SUBSTRATE
IS GATE
CT007001

To-18

TO·72

WAFER

DICE

VCR2N

-

VCR2N/W

VCR2N/O

VCR4N

-

VCR4N/W

VCR4N/O

-

VCR3P

VCR3P/W

VCR3P/O

VCR7N

VCR7N/W

VCR7N/O

VCR4N
5010 (4N)
D(2)

~{Irr~'

'When ordering wafer/dice refer to Section 10, page 10-1.

.0025 • .0025
.0035

.0035

.~:~~~

~

NOTE: SUBSTRATE
IS GATE

.013
CTOO71OJ

VCRllN
6019
0,

--i

G'lf'§§§§~tfeil ~2~~
, { - - .D39

s,
.025 [ll
G, ~. .0037
I _
,.1I
.0027
.0027
..L ____.....
"!-- 0, TYP. 2 PLACES
Sa

~x .0035

.0025

.0025

TYP.2 PLACES
CTOO1201

2-117
Note: All typical values have been guaranteed by characterization and are not tested.

VtR2N/3Pf,4NI7N
, :. ;'.' '0--1-"."0'"

.'OV---i\
TG002501

0,25

WFOOO601

TCOO2601

Circuit Diagrams

Figure 2: Switching Times

TYPICAL PERFORMANCE CHARACTERISTICS
SWITCHING TIMES
VS TEMPERATURE
0123 AND 0125
(SEE NOTES 4 AND 5)

toff(delay) VS IIN(PEAK)

0123
c

1.8

,

1.7

1

1.6

E

:t0

.

1.5

/

N

::; 1.4

c

:I

1.3

Z

1.2

"0

/
1
"
'
/
j

,000

1100

./

L

V

~900

..

VR-O
VEE --20V
V+- ,OV
CCUT-1OpF

:I 700

;:::

V"-O
VEE --20V
V+o < COUT < ,0000F
0< 10UT<4mA

,ov

"Zsoo
~

I-

~300

liN CPEAKI

(mA)

toft (1 mA.

L.-1"'"

."

- --

.......

>800

alOmA

~:;_0_2OV-

~t-...

!

I
-"
1o,,(4mA!/

10.

100

"N

I I

-0

lOUT

.......

i

......
~

~600

V

10" (dellyl

TA·25°C

1.0,

VIN(ON) VS TEMPERATURE
0123

-so

I I
400

75
o 25
TEMPERATURE (OCI

125

-25

25

75

,25

TEMPERATURE tOCI
OPOO2801

OPOO2801

-75

3-3
Note: All typical values have been guaranteed by characterization and are not tested.

OPOIl3OOI

!

1»12311)125';

Q

-TYPICAL' PERFORMANCE CHARACTERISTICS (CONT.)

=

is

liN VS VIN
0123

u
;(

...!

_v.

10'

1.4

!

Vu. • -20V

26'C ~';!- ~

:( 0.3

.;

.,55'C

0.6

V
o

r--+--+--+---I

./

0.21--+--

I

~ 0.2

Vee" 10V

~ 0.4 I--+--+--+-~

126'C i:-'~

U

V, •• 0.5V (0126)
V.·O
V,·4.5V

0.5

I

ffi

IOUT(OFF) VS TEMPERATURE
,0123 ANO 0125'

liN" 1 inA (0123)

-0

VIE .. -20V

II:
0::

....""

VSAT VS TEMPERATURE
0123 ANO 0125

/

r '"""1

10

......-....L.._...J

1

0.1 1=~=.!:IO~Ui!-T,:,·.!.1!mA

I

O'---......-75

0.2
0.4
0.6 0.8
V,. - INPUT VOLTAGE IV)

-25

26

75
TEMPERATURE I'C)

OPOO3101

26

126

45

65

APPLICATIONS
Using INTERSIL'S MOSFET SWITCH, G117, with either
the 0123 or 0125 drivers provides a convenient means of
designing a 5 channel analog multiplexer with a series on/
off switch.

0

f

117

-r

'..

..

I.

I

AFOO0501

Figure 3:

5-Chan~el

105

126

0P003301

QPO07001

r ~~~oo--~----------~
:L~!
-:0 c~o:;j

65

TEMPERATURE I'C)

Multiplexer

Note: All typical valUes have been guaranteed by characterization and are not tested.

D123/D125
APPLICATION TIPS
Interfacing the D123 and D125
In order to meet all the specifications on this data sheet,
certain requirements must be met by the drive circuitry.
The D125 can be turned ON easily, but care must be
exercised to insure turn-off. Keeping VL - VIN S DAV is a
must to insure turn-off. To accomplish this, a shunt resistor
must be added to supply the leakage current (ICES) for DTL
devices. Since ICES = 50pA, a OAV IO.05mA = 8kn or less
resistor should be used. For TTL devices using a 2kn
resistor will insure turn-off with up to 200pA of leakage
current.

Y" ••.•

...

..-

--

D'.

01'L"IIUL"'~

••

110

...... aa

--

~'"

fl'fLI"""'LUIIt

..

-

m._ .........

LD012301

Figure 5: 0125 Interface

Using the ENABLE Control

.

Device pins VR or VL, can be used to enable the D123 or
D125 drivers. For the D123, the enabling driver must sink
IR(ON) X no. of channels used. For the D125, IL(ON) X no. of
channels used must be sourced with a voltage at least + 4V
greater than VIN.

v.

LD012201

Figure 4: 0123 Interface

3-5
Note: All typical values have been guaranteed by characterization and are not tested.

!

8,12'9

" 4-Channel Decoded JFET
Switch Dri,ver
GENERAL DESCRIPTION

FEATURES

The 0129 is a 4-channel driver with binary decode input.
It was designed to provide the DC level-shifting required to
. interface low-level logic outputs' (0.7 to 2.2V) to field-effect
transistor inputs (up to 50V peak-to-peak). For a 5V input
logic supply, the V- terminal can be set at any voltage
between -5V and -30V. The output transistor is capable of
sinking 10mA and will stand-off up to 50V above V- in the
off-state.
The ON state of the driver is controlled by a logic "1"
(open) on all three input logic lines, while the OFF state of
the driver is achieved by pulling anyone of the three inputs
to a logie, "0" (ground).
The 4-channel driver is internally connected such that
each one can be controlled independently or decoded from
a binary counter.
..

•

·Quad Three;;lnputGates Decode Binary Counter
to. Four Lines
• Inputs .Compatible With Low Power TTL and
DTL, IF 200MA Max
• Output Curr.ent Sinking Capability 10mA
-- External Pull-Up Elements Required
• Compatible With G115 and G123 Series
Multichannel MOSFET Switches Which Include
Current-Umiter Pull-Up FETs

=

ORDERING INFORMATION
D129

A,--,--T
-:---'--- - - - - - . , . - - - - - - - - - - - - - 'Package

1

K - 14-pin CERDIP
L - 14-pin' Flat Pak
P - 14-pin Ceramic DIP
(Special Order Only)
Temperature Range
A - Military (- 55·C .to + 125·C)
B - Commercial (,.. 20·C to + 85·C)

~-------------------- Device Chip Type

v'

I.
IN,

13

IN2
12
IN3
IN.
INS

11

IN.

I.
IN,

OUT,

OUl 2

OUT3

OUT4

(eACH DRIVER)

LOOOO701

GNO

vLOOOO601

Flg~re

1: Functional Diagrams (Outline Dwgs DO, FD-2, JD)

Note: All typical values have been guaranteed by characterization and are not tested."

...D

D129

I\)

co

ABSOLUTE MAXIMUM RATINGS
Vo - V- ........................................................ 50V
GND - V- ...................................................... 33V
V+ - GND ....................................................... 8V
VIN - GND ..................................................... ±'6V
Current (any terminal) .....................................:. 30mA

Storage Temperature ...................... -65°C to + 150°C
Operating Temperature ................... -55°C to + 125°C
Power Dissipation (note) ................................ 750mW
Lead Temperature (Soldering, 10sec) ................. 300°C

Note: Dissipation rating assumes device mounted with ali leads welded or soldered to pc board in ambient temperature of 70·C. Derate 1OmW I·C for higher
ambient temperatures,
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure 10
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

Test conditions unless otherwise specified V-

= -20V,

V+

= 5V

MAXIMUM LIMIT

SYM·

PARAMETER

D129M

01291

-5S·C

25°C

85°C

-19.3

-19

-19.8

Va = 10V, VIN = 0.7V

Input Current
Input Voltage High
Input Current
Input Voltage Low

BOL

TEST CONDITIONS

UNIT

12S·C

-20·C

2SoC

-19.3

-19

-19.25

-19.25

-19.8

-19.75

0.1

0.1

20

0.2

0.2

10

VIN = 5V Input Under Test,
VIN = 0 Ali Other Inputs

0.25

0.25

5

1

1

5

VIN = 0, V+ = 5.5V

-250

-200

-160

-250

-225

-200

OUT

VOL

Output Voltage, Low

10= 10mA

VOL

OUtput Voltage, Low

10=lmA

Output Current, High
10H
INPUT
IINH
IINL

.

.

I VIN = 2.2V. V + = 4.5V

V
"A

IlA

TIME

ton

Ioff

Tum-ON Time

I Turn-OFF

I See

Time

0.25
Switching Time Test Circuit

I

I

1.0

0.3

I

I

I

1.5

I

I

SUPPLY

lEE

Negative Supply Current

-2

""

-2.25

IL

LogiC Supply Current

V- = -20V

One Channel "ON"

3

3.3

lEE

Negative Supply Current

V+ = 5.5V

Ali VIN=O,

-10

-25

IlA

Ali Channels "OFF"

0.75

1

mA

Logic Supply Current
IL
• Per gate Input

IN:::::8

-.'OY

.5V

1

ri> I

I

I

-1

r

If''' lOOns
t f .. lOOns
OUT

IN

'Pw. ' ''''

.,~:~
OY

mA

=t-

f .. lOOK Hz

ton~

·'OY - - - - -

OUT

OV - - - - - - - - - -2OV
~90'4
WFOOO701

TCOO2701

Figure 2: Switching Time and Test Circuit

3-7

Note: Ali typical values have been guaranteed by characterization and· are not tested.

; DG11'8IDG123/DG125

Z4

& 5-Channel SPST Driver

c;With Switch
CIt
~

g-.
CD
~

~

g

GENERAL DESCRIPTION

FEATURES

This series includes devices with four and five channel
switching capability. Each channel is composed of a driver
and a MOSFET switch. Two driver versions are supplied for
inverting and noninverting applications. A MOSFET, used
as a current source provides an active pull-up. for faster
.
switching.
An external biasing connection is brought out for biasing,
the current source, for optimization of speed and power.

•

Available With and Without Programmable
Constant Current Pull-up
Zener Protection on All Gates
P-Channel Enhancement-Type MOSFET Switches
Each Switch Summed to One Common Point

•
•
•

ORDERING INFORMATION

TRUTH TABLE

DGl18 A L = K Package

DGl18, DG125

DG123

K - 14-ptn CERDIP
L - 14-pin Flat Package
P - 14-pin Ceramic DIP
(Special Order Only)
Temperature Range
A - Military (- 55°C to + 125°C)
B - Commercial (_20°C to +B5°C)
Device Chip Type

VIN

VR

VIN

VL

L
H
L
H

L
L
H
H

L
L
H
H

H
L
H

OG123

OG125

(One Channel)

(One Channel)

•

v·

"
;t::~:::;~::::::~~3D
,

1

~

I

I

,

:

v·

I•

IN

.,'..., '

.

.."

So"

"

1

1

v'

.

3•
I

I

I

I

I
I
I
I·
I
I

·

___ JI

I
I
I
I
I
I
I

iI

I

I
I
I
I
I
I

..'~2t-------~+-r-~-~

I

I

I1

: !

:

I
I
I

1

_____ JI

1
1

1

1
I.

1
1
1

1
I
I

_____ JI

"

s.~'t====:r;~==Sr3D
sak-

~~'t-------~~r---~
~~3t-------~+-~r_~

I

I
I
I
I
I
I

___ J

1

v-

v-

v.
v'

...

I

OFF
ON
.OFF
OFF

L=OV, H= +V

OGllS

v-

Condo

L

(One Channel)

IN

Switch

_______ JI

1
--_- .. - __ 1

lOOOO201

LDO00101

Figure 1: Schematic & Logic Diagrams (Outline Dwgs DD, FD-2, JD)

3-8
Note: All typical values have been guaranteed by characterization and· are not tested.

lOOO030t

.D~D[6

DG118/DG123/DG125

g

Collector to Emitter (V+ -V-) ............................. 33V
Collector to Pull-up (V + - Vp) .............................. 33V
Drain to Emitter (Vo-V-) .................................. 32V
Source to Emitter (Vs-V-) ................................ 32V
Drain to Source (VO-VS) ................................... 28V
Source to Drain (VS-Vo) ................................... 28V
Logic to Emitter (VL -V-) ................................... 33V
Reference to Emitter (VR-V-) ............................ 31V
Reference to Input (VR - V,N) ................................ 6V

Logic to Input (VL -V,N) ..................................... ±6V
",put to Emitter (V'N-V-) ..................................33V
Current (any terminal) ...................................... 30mA
Storage Temperature ...................... -65°C to +150°C
Operating Temperature ................... -55°C to + 125°C
Dissipation (Note) ......................................... 750mW
Lead Temperature (Soldering, 10sec) ................. 300°C
NOTE: Dissipation rating assumes device is mounted with all leads welded
or soldered to printed circuit board in ambient temperature of 70 o e.
Derate 1OmW I"C for higher ambient temperature.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated' in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
Test conditions unless specified otherwise are as follows: VL = 4.5V, VR
test conditions used for output and power supply specifications.

= 0, V- = -20V, and P = -20V. Input ON and OFF

I

MAX LIMITS

PARAMETER
(NOTE)

TEST CONDITIONS

-55°C

+ 25°C

+ 125°C

UNIT

INPUT

pA

IIN(OFF)

Y,N - O.4V

1

1

100

VIN(ON)

IIN-1mA

1.3

1.0

0.8

V

DG118

IIN(OFF)

VIN - 4.1V

1

1

20

IlA

DG125

IIN(ON)

VIN =0.5V

-0.7

-0.7

-0.7

rnA

DG123

OUTPUT

800

n
n
n

IO(ON)

Vo - 10V. IS(all) - 0

4

4000

nA

IO(OFF)

VS(all)

= 10V.

-4

-4000

nA

-1

-1000

nA

rOS(ON)
All
circuits

IS(OFF)
POWER SUPPLY

All
circuits

100

100

125

Vo = O. Is = -100IlA

200

200

250

Vo - -10V. IS - -1001lA

450

450

Vo = -10V

Vo = 10V. Vs = -10V

ICG(ON)

3
3

rnA

-0.5

rnA

IEE(ON)

-6

rnA

ICC(OFF)

10

pA

IL(OFF)

10

pA

-15

IlA
pA

All
circuits

VO-10V.IS--1mA

IL(ON)
IR(ON)

IR(OFF)

One Channel (ON)

All Channels (OFF)

I t(ON)

circuits

JtlOFFL

rnA

-20

lEE OFF}
SWITCHING TIMES
All

...

CD
.....

ABSOLUTE MAXIMUM RATINGS

DEVICE
NO.

g...

I

See Switching Times

I

I
I

0.3
1

I
I

I
..

NOTE: (OFF) and (ON) subscnpt notation refers to the conduction state of the MOSFET switch for the given test condition .

3-9
Note: All typical values have been guaranteed by characterization and are not tested.

I

p.s
Ils

;;
W

a
I:)

;;
UI

OG'I23

v"

to
I,

01 ,JS
01 tIS

s.
+--,--o'OUT'U1
DG123
OUTPUr

"'p'
TC002301

OG118,125
DG118,125
OUTPUT

oJl..
WFOOO501
OUTPUT

"p'
TCOO2401

i=igure 2: Switching Times

TYPICAL PERFORMANCE CHARACTERISTICS
liN vs VIN
DG123
1.8

i

!

...

..
"

VR- 0
V-'-20V

I.'

,.~

~

,,

II II

1100

!900

...'"

'~:g:NL

~

...u

SWITCHING TIMES vs
TEMPERATURE

-ssoc' ~

II NIl

0.6
0.2

V
0.2

0.4

I
0.6

~

;:

rOS(ON) vs Vo or Vs
IK

VR"'O
v- .. -20V

v+ =

10V

;<;,:~;v3(lpF

--+_1-+--+-/---::1

700

C>

~

I

V
0.8

VIN - INPUT VOLTAGE (VI

z

i

IS'-lmA

Vr:::

~~ ~-55.
_t-t-

' ......

500

u

....
~

300

.......

V+- 10V
-20V
Vp = -20V

v- ..

~~E~

tONr--.....

100

-50

125·_
25·-

o

25

125

10
-10

-10

TEMPE'AATURE (OC)

OP002501

OPO02601

3-10
Note: All typical values have been guaranteed by characterization and are not tested.

OP002701

DG118/DG123/DG125
APPLICATION TIPS
The recommended resistor values for interfacing RTl,
DTl, and TTL logic are shown in Figures 3 and 4.

..

DTL911941

9oI9H'163

TTLS414
TTl9000SEAIES

SU"l

AFOOO21I

Figure 4: DG123 Interface
AFOOO11 I

Figure 3: DG118 and DG125 Interface

Enable Control
The VR and Vl terminals can be used as either a Strobe
or an Enable control. The requirements for sinking current
at VR or sourcing current at VL are: IL(ON) x No. of channels
used, for DG 118 and DG 125, and IR(ON) x No. of channels
used for the DG123 devices. The voltage at VL must be
greater than the voltage at VIN by at least +4V.

3-11

Note: All typical values have been guaranteed by characterization and are not tested.

i~

,DG126,':!,DG129, DG133,
g8 DG134, DG140, DG141,
DG151, DG152', DG153, DG154
DUAL ,JFET Analog Switch
,FEATURES

GENERAL DESCRIPTION
These switching circuits contain two channels in one
package, each, channel conSisting of a driver circuit controlling a SPST or DPST junction - FET switch. The driver
interfaces DTl, TTL or RTl logic signals for multiplexing,
commutating, and Df A converter applications, which permits logic design directly with the switch function. logic "1"
at the input turns the FET switch ON, and'iogic "0" turns it
off.

1

•

Each Channel Complete-:-Interfaces With Most
Integrated Logic
'
' . Low OFF Power DisSipation, 1mW
• Switches Analog Signals Up to 20 Volts Peak-toPeak
• Low rOS(ON). 10 Ohms Max on DG140/A and
DG1411A
• Switching Times Improved 100%-'A' Versions

ORDERING INFORMATION
0126

1A

~

L ___________________

DUAL SPST
00133 (rOS(ON) = 30!'!)
DG134 (rOS(ON) = 80!'!)
DG141 (rOS(ON) = 10!'!)
DG151 (rOS(ON) = 1S!'!)
DG152 (rOS(ON) = 50!'!)

Package
K - 14-pin CEROIP
L - 14-pin Flat Pack
P - 14-pin Ceramic 01 P
(Special Order Only)
Temperature-Range
A - Military (-55'C to +125'C)
B - Industrial (- 20°C to + 80°C)
Device Chip Type

DUAL DPST
DG126 (rOS(ON) = 80!'!)
DG129 (rOS(ON) = 30!'!)
DGI40 (rOS(ON) = 10!'!)
DG153 ('OS(ON) = IS!'!)
DG154 (roS(ON) = 50!'!)

~~_sw,

$W,
SW,
SW,

VIlIENABlE)

lD012101

'0

V.

(ENABLE)
08027401

"

<>:"11-------f.-I~sw,

o-"'j---"! ---+--+-<>sw,

12
VII (ENABLEl
lD012001

Figure 1: Functional Diagrams (Outline Dwgs DO, FD-2, JD)

3-12
Note; All typical values have been guaranteed by characterization and are not tested.

v05027501

DG126, DG129, DG133, DG134, DG140,
DG141, DG151, DG152, DG153,· DG154
ABSOLUTE MAXIMUM RATINGS
Analog Signal Voltage (VA-V- or V+ -VA) ......... 30V
Total Supply Voltage (V + - V-) .......................... 36V
Positive Supply Voltage to Ref. Voltage (V+ - VR) .. 25V
Ref. Voltage to Neg. Supply Voltage (VR - V-) ...... 22V
Power Dissipation (Note) ................................ 750mW

Current (any terminal) ...................................... 30mA
Storage Temperature ...................... -65°C to + 150°C
Operating Temperature ................... -55°C to + 125°C
Lead Temperature (Soldering, 10sec) ................. 300°C

NOTE: Dissipation rating assumes device is mounted with all leads welded or soldered to printed circuit board in ambient temperature below 70'C. For higher
temperature, derate at rate of 1OmW I'C.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (Per Channel)
Applied voltages for all test: DG126, DG129, DG133, DG134, DG140, DG141 (V+ = + 12V, V- = -1BV, VR = 0), and DG151,
DG152, DG153, DG154 (V + = + 15V, V- = -15V, VR = 0). Input test condition which guarantees FET switch ON or OFF as
specified is used for output and power supply specifications
ABSOLUTE MAX LIMIT

SYMBOL
(NOTE)

CHARACTERISTIC

TYPE

TEST CONDITIONS

UNIT

-55°C

25°C

125°C

INPUT
VIN(ON)

Input VOltage-On

V>;.=-12V

2.9 min

2.5 min

2.0 min·

Volts

VIN(OFFI

Input Voltage-Off

V2 = -12V

1.4

1.0

0.6

Volts

IIN(ON)

Input Current

VIN =2.5V

120

60

60

p.A

IIN(OFF)

Input leakage Current

VIN =0.8V

0.1

0.1

2

p.A

80

80

150

n

30

30

50

n

10

10

20

n

15

15

30

n

All .circuits

SWITCH OUTPUT
DG126
DG134
DG129
DG133
rOS(ON)

Drain-Source On Resistance

VIN = (See Note)
Vo = 10V. Is = lOrnA

DG140
DG141
DG151
DG153
DG152
DG154

Vo = 7.5V, IS = lOrnA
50

100

n

VO=VS= -10V

±2

100

nA

Vs = 10V. Vo = -10V

±1

100

nA

Vo=10V, VS=-10V

±1

100

nA

Vo=Vs= -10V

±2

100

nA

Vs = 10V, Vo = -10V

±10

1000

nA

Drain leakage Current

Vo= 10V, VS= -10V

±10

1000

nA

IO(ON) + IS(ON)

Drive leakage Current

Vo=Vs= -7.5V

±2

500

nA

IS(OFF)

Source leakage Current

= - 7.5V

±10

1000

nA

IO(OFF)

Drain Leakage Current

Vo = 7.5V,. Vs = - 7.5V

±10

1000

nA

IO(ON) + IS(ON)

Drive leakage Current

Vo=Vs= -7.5V

±2

500

nA

IS(OFF)

Source leakage Current

Vs = 7.5V, Vo = - 7.5V

±2

200

nA

IO(OFF)

Drain Leakage Current

Vo = 7.5V. Vs = - 7.5V

±2

200

nA

IO(ON) + IS(ON)

Drive leakage Current

IS(OFF)

Source leakage Current

IO(OFF)

Drain Leakage Curr.ent

IO(ON) + IS(ON)

Drive leakage Current

IS(OFF)

Source leakage Current

IO(OFF)

DG126
DG129
DG133
DG134
DG140
DG141

DG151
DG153

DG152
DG154

VIN = (See Note)

Vs = 7.5V, Vo

NOTE: VIN must be a step function with a minimum slew-rate of tV / jJS.

3-13
Note: All typical values have been guaranteed by characterization and are not tested.

50

DG128J DG129, DG133, DG134, DG140,
DG141, DG151, DG152,· DG153, DG154

.:f

.. "
go

ELECTRICAL CHARACTERISTICS (CONT.)

(I) . .

-N
(1)110

"
gg..

SYMBOL
(NOTE)

ABSOLUTE MAX LIMIT
CHARACTERISTIC

TYPE

TEST CONDITIONS

UNIT
25°C

-55"C

125°C

POWER SUPPLY
I, (ON)

Positive Power Supply Drain
Current

12(ON)

Negative Power Supply Drain
Current

IR(ON)

Reference Power Supply
Drain Current

11 (OFF)

Positive Power Supply
Leakage· Current

12(OFF)

Negative Power Supply
Leakage Current

IR(OFF)

Reference Power Supply
Leakage Current

One Driver ON. VIN

= 2.5V

All Circuits

Both Drivers OFF. VIN = O.BV

3

mA

-l.B

mA

-1.4

mA

25

!lA

-25

!lA

-25

!lA

SWITCHING
toN

Turn-On Time

See Below

DG126. DG129. DG133.
DG134. DG152. 00154

600

ns

toFF

Turn-Off Time

See Below

DG126. DG129. DG133.
DG134. DG152. DG154

1.6

p.s

toN

Turn-On Time

See Below

DG140. DG141. DG151. DG153

1.0

p.s

toFF

Turn-On Time

See Below

DG140. 00141. DG151. DG153

2.5

p.s

POWER
PON

ON Driver Power

POFF

OFf Driver Power

175

Both Inputs VIN = 2.5V

I

All Circuits

I Both

Inputs VIN

= 1V

I

NOTE: (OFF) and (ON) subscript notation refers to the conduction state of the FET switch for the given test.

3-14
Note: All typical values have been guaranteed by characterization and are not tested.

I

1

mW

I

I

mW

.O~OIb

DG126, DG129, DG133, DG134, DG140,
DG141, DG151, DG152, DG153, DG154
ELECTRICAL CHARACTERISTICS (CONT.)
DG126, 129, 133, 134, 140, 141

NY:'.

,<0.1"

,,<0.'"

\1 .... _

-

.

DG151, 152, 153, 154

1Wr-------,.
J.MII

.,

.,

""""'

V•• ·?IV

'11'.",.,1'1

WF0269GI

WF026801

.

v.",.O\'

"" •• I:N

'"

INPUI C>-'V1I'rf--""""--'

OUTPUT

TC035201

TC035301

OFF MODEL

OFF MODEL

~OUTPUT

IHPUT

~
A'

m

AI

=

OUTPUT

•

INPUT

TC03550t

TC035401

ON MODEL

ON MODEL

-1'::'

~.n. -c>--t>- -,;
~.::
hVOI,tT
'o,.F
TC035601

1 ='_0

TC035701

Figure 2: Switching Times (at 25°C)

3-15
Note: All typical values have been gualanteed by characterization and are not tested.

DG1'26,DCi29, .DCi33, DG1340,.DG140,
DG141, DGi51, DG152~ DG153,DG154
TYPICAL PERFORMANCE CHARACTERISTICS (per channel)
DG126, 129, 133, 134, 140, 141

DG151, 152, 153, 154

VIN THRESHOLD VII TEMPERATURE

VIN THRESHOLD vs TEMPERATURE

VR =0
V+ = +12V

~~

ON

V-

~

= -12V

VR -0
v+ = +1'5V

2

0
-'
0

~~

%

:

r-

OFF

II:

ON

V- = -12V

-

OFF

%

l-

..

1

I-

::>
~

z

z

:>

:>

o

-15

-26

\

o

126

75

26

-75

-25

TEMPERATURE C'C)

25

OP058101

OP05BOOI

rOS(ON) vsTEMPERATURE
(Normalized to 25'C Value)
2

rOS(ON) vs TEMPERATURE
100

VIN = 2.5V
-VR =0

DGI52.1~

f-V+ = +12V

f-V-

= -lBV

./

1

,

!

-75

..... i-"

10

"

~

iiji;i;;

i,..oo"

1

./

DG151. DGI53

~

."
o

125

75

TEMPE RATURE C'CI

~

1

-25

26

75

-75

125

-26

26

75

126

TEMPERATURE COC)

TEMPERATURE C'c)

QP056301

OP058201

ALL CIRCUITS
ON SUPPLY CURRENT vs
TEMPERATURE
2.6

I--

\000

I
- 1::::-

..

100

I-

z \.8

a:
a:
::>

1.4

OJ

....

> 1.0
-'

Ii!

0.6

0

0.2

-

-

10
;;(

C 2.2 f-- --'

!

~
~

12C~""

;;(
.!;

f-

IRIONI

.E

g

;t;;t;~G'40.
'4'.
151.153

W

w

>
-'
::>

'29.

DGI26.
133.13<4

z

~

0.1

......'"
0

/

om

0.1
TEMPERATURE lOCI

Z

'"'"::>

.

DG152.
1~

25 50 75 100 125

.3
I-

UTf>UT
00142
DG14~

D<3139
DG144
rOS(oNj

Drain-Source On Resistance

DG145
DG146
DG161
DGl63
00162
00164

10(ON) + IS(ON)

Drive 'Leakage Current

IS(OFF)

Source LeBkage Current

10tOFFI

Drain. Leakage Current

10tON) + IStON)'

Orive Leakage Current

00139
D.G142
00143
DG144
DG145
DG146

VO" 10V, IS'" -IOmA
. VIN (See Note)
Vo-l0V, Is= -lamA
VIN (See Note)
VD.= 7.5V,. Is = -HlmA

50

100

n

VO" Vs, -: -10V

2

lOG

nA

Vs';' 10V, VP.'" -10V

1

100

nA

VO=10V, vS.- -10V

1

100

nA

vo=vs= -10V

2

100

nA

VS.-l0V; Vo - -10V

10

1000

nA

lW, Vs = -10V

10

1000

nA

Vo = Vs =·:"7.5V

2·

500

nA

Vs - 7.5V, VD = -7.5V

·10

1000

nA

VIN (see Note)

IS(OFF)

. SOllrce Leakage Currerit

1010FF)

Drain Leakage Current

10(0,,!>-+ IS(ON)

Clm(e Leakage Currerit

IS(OFF)

SOUrce Leakage Current

IO(OFF)

Drain Leakag8 Current

Vo = 1.5V, Vs - -7.5V

10

1000

nA

IO(ON) + IS(ON)

Dilve Leakagli Current

Vp=lIs· -7.5V

2

500

nA

IS(OFF)

Source Leakage Current

Vs-7.5V, 110- -7.5V

2

200

nA

IDlOFFl

Drain Leakage. Current

Vo=7.5V, Vs= -7.5V

2

200

nA

. VO=
00161
00163

00162
00164

NOTE: (OFF) and (ON) subscript notation refers to the oondu.ction state 'of . the FET .switch for the given test.
VIN must be a step function with a minimum slew-rate bf 1VI p.s.
.

3-18
Note: All typicai values have been guaranteed by characterizatkin

and are' not

tested.

.D~[l

DGi3e, DGi42-DGi46, DGi6i-DGi64

UNIT

;
g...

4.0

mA

g

-2.0

mA

-2.0

mA

25

pA

-25

pA

-25

pA

ELECTRICAL CHARACTERISTICS (CONT.)
ABSOLUTE MAX LIMIT

SYMBOL
(NOTE)

PARAMETER

TYPE

TEST CONDITIONS
-55°C

25°C

125°C

11 (ON)
12(ON)

Negative Power Supply
Drain Current

IR(ON)

Reference Power
Supply
Drain Current

I1(OFF)

Positive Power Supply
Leakage Current

12(OFF)

Negative Power Supply
Leakage Current

IR(OFF)

Reference Power
Supply
Leakage Current

VINl =3V
or
VINl =2V
All Circuits

VIN1

= VINE, = O.BV

SWITCHING

toN

Turn-On Time

DG139, DQ142
DG143, OG144
OG162, OG164

See Switching Times

O.B

iJ.S

tOFF

Turn-Off Time

DG139, OG142
DG143,OGt44
DG162, DG164

See

Times

1.6

iJ.S

tON

Turn-On Time

OG145, DG146
OG161, OG163

See Switching Times

1.0

iJ.S

Turn-Off Time

OG145, OG146
DG161, OG163

See . Switching Times

2.5

iJ.S

tOFF

t
I

POWER SUPPLY

Positive Power Supply
Drain Current

;

Sw~ching

NOTE: (OFF) and (ON) subscript notation refers to the conduction state of the FET switch for the given test

3-19
Note: All typical values have been guaranteed by charecterizatiOA and ar& not testeel.·

J
;
!
b
o

...

:

;I)Q13~ 'DG142-DG14,6,.DG181,..DG164

~

i

8

DG139,142, 143, 144, 145, 146'

~."".~.."~~""'f

. •,,01,,$

•

C.' 01/~



--

I uG142. 143

i--"

'i;;;r:r+DG145.146

100

10
E

.!'

I-""

O~

-75

______

-so -25

-L~~~~

0

25

so

1

-75

75 100 125

-so -25

0

25

so

EXCEPT DG145.146

0.1
75 100 125

TEMPERATURE I"C,

TEMPERATURE COCI

~ §§

§~ DG145.146

!

OP003601

25

45

65

85

105

125

TEMPERATURE lOCI
QP003701

OP003801

DG161, 162, 163, 164
VIN1 THRESHOLD vs
TEMPERATURE

RDS(ON) vs TEMPERATURE
100

-

..;::

DG162.164

..,...

~

'"

.£
z

~

10

--

-75

______

-so -25

0

-L~

25

__

so

::

DG161.163

E

O~

looo·em_
IS(OFF) vs TEMPERATURE

~~

1

75 100 125

TEMPERATURE C·CI

-75 -50 -25 0

25

so

75 100 125

TEMPE RATURE I·CI

65

55

105

125

TEMPERATURE C'CI
0f'00400!

OPO03901

45

3-21
Note: All typical values have been guaranteed by characterization and are not tested.·

OPOO4101

iDG180-191

i

High-Speed Driver With

.c; JFET Switch
a

GENERAL DESCRIPTION

FEATURES

The DG180 thru DG191 series of analog gates consist of
2 or 4 N-channel junction-type field-effect transistors (JFED
designed to function as electronic switches. Level-shifting
drivers enable low-level inputs (0.8 to 2V) to control the ONOFF state of each switch. The driver is designed to provide
a turn-off speed which is faster than turn-on speed, so that
break-before-make action is achieved when switching from
one channel to another. In the ON state, each switch
conducts current equally well in both directions. In the OFF
condition, the switches will block voltages up to 20V peakto-peak. Switch-OFF input-output isolation is SOdB at
10MHz, due to the low output impedance of the FET-gate
driving circuit.

•
•

•
•
•
•
•

Constant ON-Resistance for Signals to ±10V
(DG182, 185, 188, 191), to ±7.5V (All Devices)
± 15V Power Supplies
< 2nA Leakage From Signal Channel In Both .ON
and OFF States
TTL, DTL, RTL Direct Drive Compatibility
ton, toff < 150ns, Break-Before-Make Action
Cross-talk and Open Switch Isolation> 50dB at
10MHz (75n Load)
JAN 38510 Approved

ORDERING INFORMATION
PART
NUMBER
DG180
DG181
DG182
DG183
DG184
DG185
DG186
DG187
DG188
DG189
DG190
DG·191

TYPE
Dual
Dual
Dual
Dual
Dual
Dual

SPST
SPST
SPST
DPST
DPST
DPST
SPDT
SPDT
SPDT
Dual SPDT
DuslSPDT
Dual SPDT

o

rOS..l0n)

L

1 1

(M Xl
10
30
75
10
30
75
10
30
75
10
30
75

~ PACKAGE

x

.

A - 10-PIN METAL CAN
L - l4-PIN FLAT PACK
P - CERAMIC DIP
(Special Order Only)
K - CERDIP
.
TEMPERATURE
A - MILITARY (- 55°C to
+ 125°C)
B - INDUSTRIAL (- 20°C to
+ 85°C)

' - - - - - - - DEVICE TYPE
' - - - - - - - - - DRIVER

ONE AND TWO CHANNEL SPDT AND SPST
CIRCUIT CONFIGURATION

TWO CHANNEL DPST CIRCUIT CONFIGURATION

v+

v'

VL

IN

IN

o

II
I I .........' - - - - 4 -........,....J
GNDV-

OG11111871188 SHOWN

ONO

v-

OG1831184/185 SHOWN

LOOO1201

LQOO1301

Figure 1: Functional Diagram (Typical Channel)

3-22
Note: All typical values have been guaranteed by characterization and are not tested.

.n~nll

DG180-191
ABSOLUTE MAXIMUM RATINGS
.
v + -v - ..........................................................
36V

GND-V- ......................................................... 27V
GND-VIN ........................................................ 20V
Current (S or D) See Note 3 ........................... 200mA
Storage Temperature ...................... -65·C to + 150·C
Operating Temperature ................... -55·C to + 125·C
Power Dissipation* ................... 450 (TW), 750 (FLAT),
825(DIP)mW
Lead Temperature (Soldering, 10sec) ................. 300·C

V+ -Vo ........................................................... 33V
Vo-V- ........................................................... 33V
Vo-VS ........................................................... ±22V
VL-V- ............................................................ 36V
VL-VIN ............................................................. 8V
VL-GND ........................................................... 8V
VIN-GND .......................................................... 8V

'Device mounted with all leads welded or soldered to PC board. Derate 6mW;oC (TW); 10mW;oC (FLAT); l1mW;oC (DIP) above 7S"C.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

DUAL SPST (DG180, 181, 182)
Metal Can Package

Flat Package
5,

c:::=====;::;!

CERDIP*

"
r;:=====::I5,
- u - _.. D,

Ne

Ne

Ne

Ne
- - - . .____ IN,

IN'_........ . - - - y+

y,

y-

CDOQ0401

CDOOOSOI

(OUTLINE DWG TO-l00)

(OUTLINE DWG FD-2)

CD000601

(OUTLINE DWG JD)

DUAL DPST (DG183, 184, 185)
Flat Package
54

CERDIP*

C:==:::::::;:;J
D.

D·

INI

y+

"C:=====::J

OND

COOOO701

COOOO801

(OUTLINE DWG FD-2)

(OUTLINE DWG JE)

Figure 2: Pin Configurations and Switching State Diagram

3-23
Note: All typical values have been guaranteed by characterization and are not tested.

...g

?...
...
CD

...,. DG·1·80-191
i..
g

SPOT (OG186, 187, 188)

Metal Can Package

Flat Package

CERDIP'

D,
NC

NC

DtC:::::Jl---,..
5t r--.1. __ .__ --"

VL

IN

NC

v'

v-

COOOO901
cOaOtODI

COOO110J

(OOTLINE DWG FD·2)

(OUTLINE DWG TO·l00)

(OUTLINE DWG JD)

DUAL SPOT (OG189, 190, 191)

Flat Package

CERDIP'

,.
53
D.

NC

v,

Dt

(SUBSTAATE)

" NC

5t

It

INt

vTOP VIEW

OND

CDOO1901

CDOO1201

'Side braze ceramic package available as special order only. Consult factory.
(OUTLINE DWG JE)

(OUTLINE DWG FD·2)

Figure 2: Pin Configurations and Switching State Diagram (Cont.)

ELECTRICAL CHARACTERISTICS (v+
PARAMETER

DEVICE NO.

= + 15V, v-

= -15V, VL = 5V, Unless Noted)

TEST CONDITIONS
(NOTE 1)

A SERIES

B SERIES
UNIT

-SS'C

+2S'C

+ 12S'C

-20'C

+2S'C +8S'C

±1

100

±5

100

SWITCH

IS(off)

IO(olt)

Io(on) + IS(on)

OG181, 182, 184, 185
187, 188, 190, 191
(OG180, 183, 186. 189)

Vs=10V, Vo= -10V, v+ =10V
V- = -20V, VIN = "OFF"

±(10)

(1000)

(15)

(300)

OG181, 184, .187, 190
(OG 180, 183, 186, 189)

Vs = 7.5V, Vo = -7.5V
VIN = "OFF"

±1
±(10)

100
(1000)

±5
(15)

100
(300)

nA

OG182, 185, 188, 191

Vs - 10V, Vo - -10V
VIN="OFF"

.±1

100

±5

100

nA

OG181, 182, 184, 185
187, 188, 190, 191
(OG180, 183,186, 189)

Vs -10V, Vo - -10V, v+ -10V

±1

100

±5

100

±(10)

(1000)

(300)

OG181, 184, 187, 190
(OG180, 183, 186, 189)

Vs = 7.5V, Vo
VIN = "OFF"

±1
±(10)

100
(1000)

(15)
±5
(15)

100
(300)

nA

OG182, 185, 188, 191

Vs = 10V, Vo = -10V
VIN = "OFF"

±1

100

±5

100

nA

OG180, 181, 183, 184
186, 187, 189, 190

Vo = Vs = -7.5V, VIN = "ON"

±2

-200

-10

-200

nA

OG182, 185, 188, 191

Vo-Vs- -10V, VIN-"ON"

±2

-200

-10

-200

nA

nA

nA
V- = -20V, VIN = "OFF"

= -7.5V

3-24
Note: All typical values have been guaranteed by characterization and are not tested.

DG180-191
ELECTRICAL CHARACTERISTICS (CONT.)
PARAMETER

DEVICE NO,

B SERIES

A SERIES

TEST CONDITIONS
(NOTE 1)

-SS'C

UNIT

+12S'C

+2S'C

-20'C

+2S'C +8S'C

INPUT
IINL

I ALL

IINH

All

I

I VIN - OV
I VIN = SV

-2S0

I
I

-2S0

-2S0
10

I

20

I
I

-2S0

I
I

-2S0
10

I
I

-2S0
20

I
I

p.A
p.A

DYNAMIC
ton

Ion Switches

300

30n Switches

ISO

180

2S0

300

2S0

300

7Sn Switches

toff

See switching time test circuit

IOn Switches
30n and 7Sn Switches

CS(off)
CO(ofQ

DG181, 182, 184, 18S,
187, 188, 190, 191
(DG180, 183, 186 189)

CO(on) + CS(on
OFF Isolation

3S0

150

130
9 typical (21 typical)

Vs=-SV, 10=0, f=IMHz
VO- +SV, IS-O, 1-1MHz

6 typical (17 typical)

Vo - Vs - 0, I - 1MHz

14 typical (17 typical)

RL = 7Sn, CL = 3pF

ns

pF

Typically> SOdS at 10MHz (See Note 2)

SUPPLY

1+

1-

DG180, 181, 182, 189
190, 191

I,S

I.S

DG183, 184, 185

0.1

0,1

DG186, 187, 188

0.8

0.8

DG180, 181, 182, 189
190. 191

-S.O

-S.O

DG183, 184, 18S

IL
IGNO

1+

1-

-4.0

-4.0

DG186, 187, 188

-3.0

-3.0

DG180, 181, 182, 183
184, 18S, 189, 190, 191

4.S

4.S

DG186, 187, 188

3.2

3.2

VIN = SV

ALL

-2.0

-2.0

DG180, 181, 182, 189
190, 191

1.5

I.S

DG183, 184, 18S

3.0

3.0

DGI8S, 187, 188

0.8

0.8

DG180, 181, 182, 189
190, 191

-S.O

-S.O

-S.S

-S.S

-S.O

-S.O

DG18S, 184, 18S

VIN = OV

DG186, 187, 188

IL
IGNO

NOTES 1.
2.
S.
.

DG180, 181, 182, 183
184, 18S, 189, 190, 191

4.S

4.S

DG186, 187, 188

3.2

S.2

All

-2.0

-2.0

mA

See SWitching State Diagrams lor VIN " ON " and VIN " OFF " Test Conditions.
Off Isolation typically> SSdB at lMHz for DG180, 18S. 186, 189.
Saturation Drain Current lor DG180, 183, 186, 189 only, typically SOOmA (2ms Pulse Duration). Maximum Current on all other devices
(any terminal) 30mA.

3-2S
Note: All typical values have been guaranteed by characterization and are not tested.

;; D0180-'I91

..g~

a» ELECTRICAL CHARACTERISTICS (CONT.)
DEYICE
NUMBER

CONDITIONS (Note 1)
y+ 15Y, Y- ,.15Y, YL 5Y

=

=

=

vo· -7.5V
Vo- -7.5V

OG180
OG181
OG182
OG183
OGI84
OG185
OG186
OG187
OG188
OG189
OG190
OG191

Vo VoVoVO=
Vo=
Vo'"
Vo =
Vo =
Vo =
VO-

-10V
-7.5V
-7.5V
-10V
-7.5V
-7.5V
-10V
-7.5V
-7.5V
-10V

IS= -10mA
VIN-"ON"

MAXIMUM RESISTANCES (rOS(ON) MAX)
INDUSTRIAL
TEMPERATURE

MILITARY TEMPERATURE
-55°C

+ 25°C

+ 125°C

-20°C

10
30
75
10
30
75
10
30
75
10
30
75

10
30
75
10
30
75
10
30
75
10
30
75

20
60
100
20
60
150
20
60
150
20
60
150

15
50
100
15
50
100
15
50
100
15
50
100

UNIT

+ 25°C + 85°C
15
50
100
15
50
100
15
50
100
15
50
100

25
75
150
25
75
150
25
75
150
25
50
150

n
n
n
n
n
n
n
n
n
n
n
n

APPLICATION HINT (for design only): Normally the minimum Signal handling capability of the OG180 through OG191 family is 20V peak-to-peak
for the 75n switches and 15V peak-to-peak for the Ion and 30n (refer 10 and IS tests above). For other Analog Signals, the following
guidelines can be used: proper switch tum-off requires that V- SVANALOO(peak) -Vp where Vp =7.5V for the Ion and 30n switches and
Vp =5.0V for 75n switches e.g., -10V minimum (-peak) analog Signal and a 75n switch (Vp=5V), requires that V- S -10V -5V= -15V.

logic Input for "OFF" to "ON" Condition (DG180/181/182 Shown)
LOGIC 3V
INPUT
I, <1Ons
If <1Ons

1.SV
SWITCH
OUTPUT

0

A-t-~~---1----~Yo

SWITCH Vs
INPUT
SWITCH
OUTPUT

CL

I30pF

O.9Vo

(REPEAT TEST FOR

0

-15Y ALL CHANNELS)

~

Ion

RL

Yo = Ys RL + FDS(ON)

-=

v-v

Y-

o-

RL

S AL T roS(on)
TC035601

WF027011

Figure 3: Switching Time Test Circuits
output waveform shown for Vs = constant w~h logic input waveform as shown. Note that Vs may be + or.- as per switching time test circuit.
Vo Is the steady state output with switch on. Feedthrough via gate capac~nce may result in spikes at leading and trailing edge of output waveform.
Sw~ch

DUA~

DUAL SPST-DG180/181/182

DPST -DG183/184/185

TEST CONDITIONS

TEST CONDITIONS

00180/181/182
VIN "ON" = O.8V
VIN "OFF" = 2.0V

DG183/184/185

I

.AII Channels
All Channels

. VIN "ON" = 2.0V
VIN "OFF" = O.8V

SWITCH STATES ARE
FOR LOGIC "1" INPUT = 2.0V

DUAL SPOT -DG189/190/191
TEST CONDITIONS

TEST CONDITIONS

DG189/1901191

DG186/187/188
"ON" = 2.0V
"ON" = O.SV
"OFF" = 2.0V
"OFF" = O.SV

All Channels
All Channels

SWITCH STATES ARE
FOR LOGIC "1" INPUT = 2.0V

SPOT-DG186/1871188

VIN
VIN
VIN
VIN

I

Channel
Channel
Channel
Channel

VIN
VIN
VIN
VIN

1

2
2
1

"ON" = 2.0V
"ON" = O.SV
"OFF" = 2.0V
"OFF" = O.8V

Channels
Channels
Channels
Channels

SWITCH STATES ARE
FOR LOGIC "1" INPUT = 2.0V

SWITCH STATES ARE
FOR LOGIC "1" INPUT = 2.0V

3-26
Note: All typical values have been guarantaed by characterization and are not lested.

1
3
3
1

&
&
&
&

2
4
4

2

.U~Ulbi

DG200/lH5200
CMOS Dual SPST
A.nalog Switches

......

i

UI

N

GENERAL DESCRIPTION

FEATURES

The DG200llH5200 solid state analog gates are designed using an improved, high voltage CMOS monolithic
technology. They provide ease-of-use and performance
advantages not previously available from solid state
switches. Destructive latCh-Up of solid state analog gates
has been eliminated by INTERSIL's CMOS technology.
The DG200 is completely spec and pin-out compatible
with the industry standard device, while the IH5200 offers
significantly enhanced specifications with respect to ON
and OFF leakage currents, switching times, and supply
current.

•
•
•
•
•
•
•

8

Switches Greater Than 28Vpp Signals With ±15V
Supplies
Break-Before-Make Switching toff 250ns, ton
700ns Typical
TTL, DTL, CMOS, PMOS Compatible
Non-Latching With Supply Turn-Off
Complete Monolithic Construction
Industry Standard (DG200)
Improved Performance Version (IH5200)

ORDERING INFORMATION
INDUSTRY
STANDARD
PART

IMPROVED
SPEC
DEVICE

DG200AA

IH5200MTW

10-Pin Metal Can

-55°C to + 125°C

DG200AK

IH5200MJD

14-Pin CERDIP

_55°C to + 125°C

DG200AL

IH5200MFD

14-Pin Flat Pak

DG200BA

IH5200lTW

10-Pin Metal Can

TEMPERATURE
RANGE

PACKAGE

55°C to + 125°C
.- 25°C to + 85°C

DG200BK

IH5200lJD

14-Pin CERDIP

- 25°C to + 85°C

DG200BL

IH5200lFD

14-Pin Flat Pak

-25°C to + 85°C

DG200CJ

IH5200CPD

14-Pin Epoxy Dip

CERDIP & EPOXY DUAL-IN-LINE
PACKAGE (outline dwgs JD, PO)

O°C to +70°C

METAL CAN PACKAGE

FLAT PACKAGE

(outline dwg TO-l00)

(outline dwg FD-2)

v+ (SUasTRATI-ANO CASE)

"
I.., 5~~~iF~E'N'

NC

NC

y+

GND

(SUBSTAATE)

NC

Ne

NC

12

Ys~BSTRATE)
'HIe

'" ~~~-.......--~,-- ¥,

'"

y- =~=rr::""::;~E.= D,
V REF

s.

CDOQ1401

TOP VIEW

SWITCH STATES ARE FOR LOGIC
"'" INPUT (POSITIVE LOGIC)
CDOO1501

C0001301

Figure 1: Pin Configurations

3--27

Note: All typical values have been guaranteed by characterization and are not tested.

.•O~OIl

8 DG2001lH5200
(II

10

!

§

"
D

..

.

..

ABSOLUTE MAXIMUM RATINGS
V+-V'- ........................................................ <33V
v+ -Vo ........................................................ < 30V
Vo-V- .........................., .............................. < 30V
Vo-Vs ........................................................ < ±22V
VIN-GND ...................................................... < 20V
Current (Any Terminal) ................................. > 30mA

Storage Temperature ...................... -65'C to + 150'C
Operating Temperature ........•..•....... -55'C to + 125'C
Lead Temperature (Soldering, 10sec) ................. 300·C
Power Dissipation .. : ...................................... 450mW
(All Leads Soldered to a P.C. Board.) Derate 6mW I"C Above 75·C.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. and functional
operation of the device· at thaseor any other Conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

GATE
PROTECTION
RESISTOR
INPUT

LD001501

Figure 2: Functional Diagram (1/2 DG200/1H5200)

DG200 ELECTRICAL CHARACTERISTICS (TA = 25'C, v+ = +15V, v-

MINIMAX LIMITS

PER CHANNEL

SYMBOL

CHARACTERISTIC

= -15V)

TEST
CONDITIONS

MILITARY

COM'LIINDUSTRIAL

UNIT

-55'C

+2S'C

+ 12S'C

+2S'C

+70'C!
+8S'C

±I

±10

±.10

±10

p.A

±IO

±10

I'A

80

100

n

01
-2S'C

IIN(ON)

Input Logic Current

VIN = O.8V See Note I

±10

IIN(OFF)

Input Logic Current

VIN = 2.4V See Note 1

±10

±1

±10

rOS(ON)

Drain-Source On
Resistance

Is=10mA
VANALOG = ±10V

70

70

100

rOS(ON)

Channel-to-Channel
rOS(ON) Match

25
(typ)

30
(typ)

n

VANALOG

Min. Analog Signal
Handling Capability

±tS

±15

V

IO(OFF)

Switch OFF Leakage
Current

VANALOG = -14V to
+14V

±2

100

±5

100

nA

IS(OFF)

Switch OFF Leakage
Current

VANALOG = -14V to
+14V

±2

100

±5

100

nA

200

±10

200

nA

80

IOION)
+ S(ON)

Switch ON Leakage
Current

Vo=Vs= -14V to
+14V

±2

ton

Switch "ON" Time
See Note 1

RL = 1kn, VANALOG
= -10V to + 10V
See Fig. 3

1.0

1.0

I'S

toff

Switch "OFF" Time

RL = 1kn. VANALOG
=-10Vto +10V
See Fig. 3

0.5

0.5

I'S

Q(INJ.)

Charge Injection

See Fig. 4

15

20
(typ)

mV

(typ)

3-28
Note: All typical values have been guaranteed by characterization and are not tested.

DG2001lH5200
PER CHANNEL

SYMBOL

CHARACTERISTIC

MINIMAX LIMITS
MILITARY

TEST
CONDITIONS

-55°C
OIRR

Min. Off Isolation
Rejection Ratio

1= IMHz. RL = 100n.
CL::; 5pF
See Fig. 5 (Note I)

IVI

+ Power Supply
Quiescent Current

VIN =OV or
VIN = 5V

- Power Supply

IV2

COM'L/INDUSTRIAL

+ 125'C

+25°C

01
-2S'C

+2S'C

UNIT

+70'CI
+85'C

50
(typ)

54
(typ)

dB

1000

1000

2000

1000

1000

2000

IlA

1000

1000

2000

1000

1000

2000

IlA

Quiescent Current

CCRR

Min. Channel to
Channel Cross
Coupling Rejection
Ratio

One Channel 011

54
(typ)

dB

50
(typ)

NOTE 1. Pull Down ReSistor must be ::; 2kn
NOTE 2: Typical values are lor design aid only. not guaranteed and not subject to production testing.

IH5200 ELECTRICAL CHARACTERISTICS

(@ 25°C, V+ = +15V, V- = -15VREF open)

PER CHANNEL

SYMBOL

CHARACTERISTIC

MINIMAX LIMITS
TEST
CONDITIONS

MILITARY

COM'L/INDUSTRIAL

-SS'C

+2S'C

+ 125'C

01
-2S'C

+ 25'C

+70'CI
+85'C

UNIT

I'N(ON)

Input Logic Current

Y,N =0.8V

±10

±I

±IO

±10

'±10

p.A

I'N(OFF)

Input Logic Current.

Y,N = 2.4V

±IO

±1

10

±10

±10

p.A

rOS(ON)

Drain·Source On
Resistance

IS·,OmA
VANALOG = ±IOV

70

70

100

80

100

rOS(ON)

Channel·to·Channel
rOS(ON) Match
Min. Analog Signal
Handling Capability

VANALOG

80

"

n

25
(typ)

30
(typ)

n

±15
(typ)

±15
(typ)

V

IO(OFF)

Switch OFF Leakage
Current

VANALOG= -14V to
+14V

±I

50

I

±2

50

nA

IS(OFF)

Switch OFF Leakage
Current

VANALOG= -14V to
+14V

±I

50

I

±2

50

nA

IOION)
+ S(ON)

Switch ON Leakage
Current

Vo=Vs= -14V to
+14V

±1

100

I

±2

100

nA

Ion

Switch "ON" Time
See Note 3

RL = I kn, VANALOG
= -10V to + 10V
See Fig. 3

0.7

0.8

IlS

Ioff

Switch "OFF" Time

RL = Ikn, VANALOG
= -IOV to +IOV
See Fig. 3

0.25

0.4

p.s

Q(INJ.)

Charge Injection

See Fig. 4

5
(typ)

10
(typ)

mV

OIRR

Min. Off Isolation
Rejection' Ratio

1= lMHz. RL = loon.
CL::; 5pF
See Fig. 5

54
(typ)

50

dB

(typ)

IVI

+ Power Supply
Quiescent .Current

Y,N - OV or
Y,N = 5V

IV2

- Power Supply
Quiescent Current

CCRR

Min. Channel to
Channel Cross
Coupling Rejection
Ratio

250

200

150

300

250

200

p.A

10

10

100

10

10

100

p.A

One Channel Off

54
(typ)

3-29
Note: All typical values have bean guaranteed by characterization and are not tested.

50
(typ)

dB

I

gDG200/lH6200
(II

I
::.

8

I

.J

TEST CIRCUITS

WLOGINPUT

w-OINPU'

-:

F"r;;;..

Stu

11.
'
• := -D--\>-W

r~
':'.

m

_OGINNT

LOGIC INPUT

,

CNO~_

It-I

":'

':'

t-~'
'oou

':"

TC003601

TC003701

Figure 3

TC004111

Figure 4

Figure 5

NOTE 3: All channels are turned off by high" 1" logic inputs and all channels are turned on by low "0" inputs; however Q,8V to 2AV describes the min, range
for switching properly, Peak input current required for transition is typically -120/LA,

TYPICAL, PERFORMANCE CHARACTERISTICS
rOS(on) vs VD and Power
Supply Voltage

rDS(on) vs VD
and Temperature
H-+++'
lGO

+.;.
V + = + 15V
' ;' V- =-15V

A-

v· = • 15V. V - = - llV

• - .... :::. • 12Y. V - ::; - 12V
C-Y· ,.10\1.\;-=-1011

__Y_.___.~~,v__-_=_-_._v~

o~_O_-

o~~~~~~~~~

-15-10 -5

0

5

10

15

~

- IS -'0

Yo - DIWH VOLTAGE (VOLTS)

Vo -

5

0

10

OPOO7101

0P003201

IS(off) or lD(off)
vs Temperature·

ID(on)
vs Temperature·

10

15·

DIlAiN VOLTAGE /VOLTS)

aI_

1°~R
~~-+--. ''1

0.1

!':

:

I'

:

I

,...-

,~.~/.~.~'~!~~'~:~~
1,

~: :-: IT---.-++i I
;.

0.01
' i
25 45

I

.1

:

as

as

10S

125

T - TEMPERATURE C·e)
OPOO7201

OPOO7301

3-30
Note: All typical values have been guaranteed by characterization and are not

tested~

DG200/lH5200
APPLICATIONS

V+
Supply
(V)

Using the VREF Terminal
The DG200 has an internal voltage divider setting the
TTL threshold on the input control lines for V + equal to
+ 15V. The schematic shown here with nominal resistor
values, gives approximately 2.4V on the VREF pin. As the
TTL input signal goes from +O.8V to +2.4V, 01 and 02
switch states to turn the switch ON and OFF.

+ 15
+ 12
+ 10
+9
+8
+7

If the power supply voltage is less than + 15V, then a
resistor must be added between V + and the VREF pin, to
restore + 2.4V at VREF. The table shows the value of this
resistor for various supply voltages, to maintain TTL compatibility. If CMOS logic levels on a + 5V supply are being
used, the threshold shifts are less critical, but a separate
column of suitable values is given in the table. For logic
swings of -5V to +5V, no resistor is needed.

TTL
Resistor
(kU)

-

-

-

100
51

-

(34)

34

(27)
18

27
18

V· (+15V)

r-... t--t-::o:-

In general, the "low" logic level should be < O.8V to
prevent Q1 and 02 from both being ON together (this will
cause incorrect switch function). With open collector logic,
and a low value of pull-up resistor, the logic "low" level can
be above O.8V. In this case, INTERSIL can supply parts with
thresholds> 1.5V, allowing the user to define the "low"
as < 1.5V (consult factory). The VREF point should be set at
least 2.6V above this "low" state, or to > 4.1V. An external
resistor of 27kn between V + and VREF is required, for a
+ 15V supply.

}~

GATE
PROTECTION
INPUT RESISTOR

AFOOO6QI

Figure 6.

3-3.1

Note: All typical values have been guaranteed by characterization and are not tested.'

CMOS
Resistor
(kU)

o DO:201/IH5201

i

Quad SPST
~ CMOS Analo~ 'Swi~ch

'

..

g

GENERAL' DESCRIPTION

FEATURES

The DG20111H5201 solid-state analog switches are designed using an improved, high-voltage CMOS monolithic
technology. They provide performance' advantages not
previously available from solid-state switches. Destructive
latch-up .of solid-state analog gates has been eliminated by
INTERSIL's CMOS technology.
The DG201 is completely specification and pin-out com, patible with the industry standard device, while the IH5201
offers significantly enhanced specifications with respect to
ON and OFF leakage currents, switching times, and supply
current.

•
•
•
•
•
•
•

SlIIIltches Greater Than 28Vp_p Signals With ±15V
Supplies
'
.,
Break-Before-Make Switching toff 250ns,
ton Typically 500ns
'
TTL, OTt, CMOS, PMOS Compatible
Non-latching With Supply Turn-Qff
Complete Monolithic .Construction
Industry Standard (OG201)
Improv!td Performance Version IH5201

=

=

ORDERING INFORMATION
INDUSTRY
STANDARD
PART NUMBER

IMPROVED SPEC
PART NUMBER

TEMPERATURE
RANGE

PACKAGE

DG201AK

IHS201MJE

-SS·C to + 12S·C

,16-Pin CERDIP

DG201BK

IHS2011JE

-2S·C to +8S·C

16-Pin CERDIP

DG201CJ

IHS201CPE

O·C to +70·C

16·Pin PlastiC DIP

,

52

V + (SUBSTRATE)

VREF
D3
GATE
PROTECTION

RESISTOR

INPUT

CDOO1601

LOOO1601

Figure 1: Functional Diagram
(1/4 DG201/1H5201)

Figure 2: Pin Configuration
(Outline dwgs JE, PEl
DUAL-IN-LINE PACKAGE

Switch Open For Logic "1" Input

'3-32

Note: All typical values have been guaranteed by characterization and are not tested.

DG201/IH5201

g

ABSOLUTE MAXIMUM RATINGS

......

~
...

V+ to v- .................................................... < 33V
v+ to VD .................................................... < 30V
Vo to v- .................................................... < 30V
VD to Vs ................................................... < ±22V
VREF to v- ................................................. < 33V
VREF to VIN ................................................. < 30V
VREF to GND ............................................... < 20V

VIN to GND ................................................. < 20V
Current (Any Terminal) ................................. < 30mA
Storage Temperature ...................... -65°C to + 150°C
Operating Temperature ................... -55°C to + 125°C
Lead Temperature (Soldering, 10sec) ................. 300°C
Power Dissipation ......................................... 450mW
Derate 6mW rc Above 70°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specificatIons is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

DG201 ELECTRICAL CHARACTERISTICS (TA = 25°C, V+ = + 15V, V- = -15V)
PER CHANNEL

SYMBOL

MINIMAX LIMITS
TEST
CONDITIONS

CHARACTERISTIC

= O.SV
= 2.4V

MILITARY

COMMERCIAL

UNIT

-55'C

+25'C

+ 12S'C

O'C

+2S'C

+70'CI
+85'C

See Note 1

10

±1

10

±t

±1

10

p.A

See Note 1

10

±1

10

±1

±1

10

#LA

80

80

125

100

100

125

51

I'N(ON)

Input Logic Current

Y,N

I'N(OFF)

Input Logic Current

Y,N

ROS(ON)

Drain·Source On
Resistance

IS= 10mA
VANAlOG = ±10V

ROS(ON)

Channel 10 Channel
ROS(ON) Match

25
(typ)

30
(typ)

VANAlOG

Analog Signal
Handling Capability

±15
(typ)

±15
(typ)

IO(OFF)

Switch OFF Leakage
Current

VANAlOG
+14V

= -14V

to

±1

100

±5

100

nA

IS(OFF)

Switch OFF Leakage
Current

VANAlOG
+14V

= -14V

to

±1

100

±5

100

nA

IO(ON)
+IS(ON)

Switch ON Leakage
Current

Vo = Vs = ±14V

±2

200

±S

200

nA

ton

Switch "ON" Time
See Note 2

Rl = 1kn. VANALOG
= -10V to + 10V
See Figure 3

1.0

1.0

p.s

toll

Switch "OFF" Time
See Note 2

Rl = 1kn. VANALOG
= -10V to +10V
See Figure 3

0.5

0.5

p.s

Q(INJ.)

Charge Injection

See Figure 4

15
(typ)

20
(typ)

mV

OIRR

Min. Off Isolation

f = 1 MHz. Rl = 10051.
CL" 5pF
See Figure 5

54
(typ)

50

dB

(typ)

Rejection Ratio

/0

+ Power Supply
Quiescent Current

10

-Power Supply
Quiescent Current

CCRR

Min. Channel to
Channel Cross
Coupling Rejection
Ratio

V,N =OV to 5V

51

"

V

2000

1000

2000

2000

1000

2000

p.A

2000

1000

2000

2000

1000

2000

p.A

One Channel Off

54
(typ)

NOTE 1: Typical values are for design aid only. not guaranteed and not subject to production testing.

3-33
Note: All typical values have been guaranteed by characterization and are not tested.

50
(typ)

dB

i

CII

~
...

o DG201/UtS201
~

110

Z
:::.

g

TEST CIRCUITS

r

m

ANALOG INPUT

g

AHAlOGIMPUT

....

,,-0....,
(Note 2)

J
r~h:

3.
0.I1.

5tU

_

r-'

LOQIC INPUT

(NO~_

= -D-I>-'0'-'1

":'

~-

.

1DOl!

TCOO391 I

TCOO411J

TC004001

Figure 3

-=-

Figure 4.

Figure 5

NOTE 2: All channels are turned off bihigh"1" logic inputs and all channels are turned on by low "0" inputs; however 0.8V to 2.4V describes the min. range
lor switching properly. Peak. input current required lor transition is typically -1201tA.

IH520t ELECTRICAL CHARACTERISTICS

(TA

= 25°C,

V+

PER CHANNEL

SYMBOL

CHARACTERISTIC

= +15V,

V- = -15V)

MINIMAX LIMITS
TEST
CONDITIONS

MILITARY

COMMERCIAL

-55'C

+25'C

+ 125'C

O'C

+25'C

UNIT

+70'CI

+85'C

IIN(ON)

Input Logic Current

VIN =0.8V

1

1

10

1

1

10

p.A

IIN(OFF)

Input Logic Cum;nt

VIN = 2.4V

1

1

10

1

1

10

ROS(ON)

Drain-Source On
Resistance

IS= 10mA
VANALOG = ± 10V

75

75

100

100

100

125

ItA
.11

ROS(ON)

Channel to Channel
ROS(ON) Match

25
(typ)

30
(typ)

.11

VANALOG

Analog Signal
Handling Capability

±15
(typ)

±15
(typ)

V

IO(OFF)'
IS(OFF)

Switch OFF Leakage
Current

VANALOG = -14V to
+14V·

±0.5

50

±2

50

nA

IO(ON)
+IS(ON)

Switch ON Leakage
Current

VO=VS=±14V

±0.5

100

£2

100

nA

ton

Switch "ON" Time
See Note 2

RL = 1kn., VANALOG
= -10V to +10V
See Figure 3

0.7

0.8

p.s

Ioff

Switch "OFF" Time
See Note 2

RL = 1k.l1, VANALOG
= -10V to +10V
See Figure 3

0.35

0.4

p.s

Q(INJ.)

Charge Injection

See Fig. 4

5
(typ)

10
(typ)

mV

OIRR

Min. Off Isolation
Rejection Ratio

1= 1MHz, RL = 100n.,
CL ~5pF
See Figure 5, (Note 1)

54
(typ)

50
(typ)

dB

10

+ Power Supply
Quiescent Current

VIN =OV to 5V

10

- Power Supply
Quiescent Current

CCRR

Min. Channel to
Channel Cross
Coupling Rejection
Ratio

One Channel Off
(Note 1)

1000

750

600

1500

1000

1000

ItA

10

10

100

20

20

200

ItA

54
(typ)

NOTE: Pull Down resistor must be ~ 2k.l1
NOTE: Typical values are lor design aid only, not guaranteed and not subject to production testing.

Note: All typical values have been guaranteed by characterization and are not tested.

50
. (typ)

dB

DG2011lH5201
TYPICAL PERFORMANCE CHARACTERISTICS
I
!

V+=+15V
V-, = -15V

D

100

,\.
C·"

125'C 1-=;;0;

SS'C

t;d...

B

.P

50

25' C 1;:;; ...

'"

A

= +15V. Y- = -15Y
Y+ = +12V. Y- = -12V
C - Y+ +IOY. Y- -lOY
D - Y + = +BV. Y - = -8Y

c-- A - Y+

r- B -

o r-

o

=

=

-15 -10 - 5 0
5 10 15
Vo - DRAIN VOLTAGE (VOLTS)

-15 -10 -5 0
5,10 15
Vo - DRAIN VOLTAGE (VOLTS)

OPOO7401
Temperature

OP007501

~

.s

iiI~

1°BflB

ZIII

~ ~~~~E3~~~~~

f""

I

~!
(,)(,)
Z

I~

-

g~0.111l1.
...

"

.§~

~

0.01

~......-'--'--'--'-"-'--.......

25

45

as

as

105

125
45

T - TEMPERATURE ('C)

as

as

105

125

T - TEMPERATURE ('e)

OPOO7601

0P00'7Ol

y+
Supply
(y)

APPLICATIONS

Using the VREF Terminal
The DG201 has an internal voltage divider that sets the
TTL threshold on the input control lines for V + = 15V. The
schematic is shown here, with nominal resistor values,
giving approximately 2.4V on the VREF pin. As the TTL input
Signal goes from + o.av to + 2.4V, 01 and 02 switch states
to turn the switch ON and OFF.

+15
+12
+ 10
+9
+8
+7

If the power supply voltage· is less than + 15V, then a
resistor needs to be added between V+ and VREF pin, to
restore + 2.4V at VREF. The table shows the value of this
resistor for various supply voltages, to maintain TTL compatibility. If CMOS logic levels with a + 5V supply are being
used, the threshold shifts are less critical, but a separate
column of suitable values is given in the table. For logic
swings of -5V to + 5V, no resistor is needed.

TTL

CMOS
Resistor
(kn)

Re$istor

fie!)

-

100
51
(34)

j

(27)
18

V'(+15VI

In general, the "low" logiC level should be < o.av to
prevent 01 and 02 from both being ON together (this will
cause incorrect switch function). With open collector logic,
and a low value of pull-up resistor, the logiC 'low' level can
be above o.av. In this case, INTERSIL can supply parts with
thresholds > 1.5V(consult factory). The VREF point should
be set at least 2.6V above this" low" state, or to > 4.1 V. An
external resistor of 27kn and VREF is required, for a .+. 15V
supply.

GATE
PROTECl'l011
'"PUT RESISTOR

AFOO070l

Figure 6

3-35
Note: All typical values have been guaranteed by characterization and are not tested,

-

34
27
18

;-1)02'1'1/1)0212
8 SPST 4-Channel Anal
.....

..

...
C\I

g

,. \)C!>,\'l'>

,'

.\.,V"""

,,0"" s·'

GENERAL DESCRIPTION

FEATURES

,.~.

The DG2ll and DG2l2 are low cost.\€~bs monolithic,
QUAD SPST analog switches. The,se can be used in
general purpose switching applications for communications,
instrumentation, process control arid compu~er peripheral
equipment. Both devices provide true bidirectional performance in the ON condition and will block signals to 30V
peak-lo-peak in the OFF condition. The DG2ll and DG212
differ only in that the digital control logic is inverted, as
shown in the truth table.
DG211 and DG2l2 are available in a l6-pin Dual-In-Line
plastic package and are rated for operation over D·C to
70·C.

•
•
•
•

Switches ± 15V Analog Signals
TTL Compatibility
Logic Inputs Accept Negative Voltages
RON. ~ 175 Ohm '

ORDERING INFORMATION
PART NUMBER

TEMPERATURE
RANGE

PACKAGE

DG2llCJ
DG2l2CJ

O·C to +70·C
O·C to +70·C

l6-Pin Plastic DIP
l6-Pin Plastic DIP

DG211

DG212

s,
IN,

S,

Dual·ln·LlRe Package

IN,
0,

0,

S2

S2
IN2

IN2
02

02

S3

S3

1N3

13

V+ (SUBSTRATE)

1N3'
03

'03

S4

S4
IN4

IN4

D4

04
80014301

TOP VIEW
CD032301

80014401

Figure 2. Pin Configuration

Four SPST Switches per Package

Switches Shown for Logic "1" Input
Truth Table

LOGIC

00211

DG212

0
1

ON
OFF

OFF
ON

. Logic "0" ::; 0.8V
Logic "1" 2: 2.4V

Figure 1: Functional Diagrams

:J,-36

Note: All typical values have been guaranteed by characterization and are not tested.

30702Q-<>01

s...

DG211/DG212

.......ICII

ABSOLUTE MAXIMUM RATINGS
V+ to v- ....................................................... 36V
VIN to Ground ............................................ V-, V+
VL to Ground ........................................ -0.3V, 25V
Vs or VD to V+ ......................................... 0, -36V
Vs or VD to V- ............................................ 0, 36V

Peak Current, S or D
(Pulsed at 1msec, 10% duty cycle max) ....... 70mA
Storage Temperature ...................... -65°C to + 125°C
Operating Temperature ........................ O°C to + 70°C
Lead Temperature (Soldering, 10sec) ................. 300°C
Power Dissipation (Package)'
16 Pin Plastic DIP" ................................. .470mW

V + to Ground ................................................. 25V
V- to Ground ................................................ -25V
Current, Any Terminal Except S or D ................. 30mA
Continuous Current, S or D .............................. 20mA

'Device mounted with all leads soldered or welded
to PC board.
"Derate 6.5mW/OC above 25°C

ELECTRICAL CHARACTERISTICS (TA = 25°C)
SYMBOL

TEST CONDITIONS
V1 = + 15V, V2 = -15V,
VL= +5V, GND

PARAMETER

LIMITS
UNIT
MIN1

Typ2

MAX

15

V

115

175

rI

O.ot

5.0

SWITCH
VANALOG

Analog Signal Range

V

ROS(ON)

Drain-Source On Resistance

Vo = ±10V. VIN = 2.4V - DG212
IS=lmA. VIN=0.8V - DG211

= -15V. VL = +5V

-15

IS(off)

Source OFF Leakage Current

10(oft)

Drain OFF Leakage Current

VIN = 2.4V
DG211
VIN =0.8V
DG212

10(ON)

Drain ON Leakage Current3

Vs = Vo = -14V. VIN = 0.8V. DG211
VIN = 2.4V. DG212

VS= 14V. VD= -14V
Vs - -14V. Vo -14V

-5.0

-0.02

-5.0

-0.02

-5.0

-0.15

-10

-0.0004

Vo = 14V. Vs = -14V
VO=-14V. VS=14V

0.01
0.1

5.0
5.0

nA

INPUT
IINH

Input Current With Input
Voltage High

IINL

Input Current With Input
Voltage Low

VIN
VIN

= 2.4V
= 15V

0.003
-1.0

VIN =OV

1.0

p.A

-0.0004

DYNAMIC
Ion

Turn-ON Time

Ioft1
toft2

Turn-OFF Time

CS(oft)

Source OFF Capacitance

Vs = OV. VIN = 5V. f

CO(oft)

Drain OFF Capacitance

Vo = OV. VIN = 5V. f = 1MHz 2

5

Co + S(on)
OIRR

Channel' ON Capacitance

Vo=Vs=OV. VIN=OV. f= lMHz2

16

See Switching Time Test Circuit5
Vs = 10V. RL = lkrl. CL = 35pF

460

1000

360

500

ns

450

OFF Isolation 4
Crosstalk
(Channel to Channel)

CCRR

= 1MHz

2

VIN = 5V. RL = lkrl.
CL = 15pF. Vs = tVRMS. f = 100kHz 2

5
pF

70
dB

90

SUPPLY
1+

Positive Supply Current

1-

Negative Supply Current

IL

Logic Supply Current

NOTES:

VIN

=0

and 2.4V

.1

10

.1

10

.1

10

p.A

1. The algebraic convention whereby the most negative value is a minimum. and the most positive is a maximum. is used in this data
sheet.
2. For design reference only. not 100% tested.
3. 10(on) is leakage from driver into "ON" switch.

~.

4. OFF Isolation = 2010g
Vs =
Vo
5. Switching times only sampled.

i~put to

OFF switch. VD

= oulput.

3-37
Note: All typical values have been guaranteed by characterization and are not tested.

e...
II)

"

DG211/DG212

;:....

Switch output waveform shown for Vs = constant with
logic input waveform as shown. Note the Vs may be + or as per switching time test circuit. Vo is the steady state
output with switch on. Feedthrough via gate capacitance
may result in spikes at leading and trailing edge of output
.
waveform.

I
I
"

+15V
SWITCH

INPUT

SWITCH

5,

OUTPUT

Vs = 'ov o - t - - - - i f

......1-<>_ _>--00 Vo

LOGIC
INPUT
(REPEAT TEST FOR IN2 IN3 ANO IN"

v-

Figure 4: Switching Time Test Circuit

WFQ27301

Figure 3: Switching Time Test Circuit
Logic shown for DG211. Invert for DG212.

+15V

TTL
INQ--'W.......H

-15V

+6V

LD012701

Figure 5: DG212 Schemat.ic (1/4 as shown)

3--38
Note: All typical values have been guaranteed by characterization and are not tested.

DGM181-191
High-Speed
CMOS Analog Switch
GENERAL DESCRIPTION

FEATURES

The OGM181 family of CMOS monolithic switches utilizes
intersil's latch-free junction isolated processing to combine
the speed of the hybrid OG 181 family with the reliability and
low power consumption of a monolithic CMOS construction.
These devices, therefore, are a cost effective replacement
for the OG181 family.
The OGM181 family has a high state threshold of 2.4V;
and a low state of + O.8V.
Very low quiescent power is dissipated in either the ON or
OFF state of the switch. Maximum power supply current is
10IlA from any supply, and typical quiescent currents are in
the 10nA range. OFF leakages are typically less than
200pA at 25°C.

•
•
•
•
•
•
•

Pin and Function Replacement for DG181 Family
Meets or Exceeds All DG181 Family
Specifications With Monolithic Reliability
Low Power Consumption
1nA Leakage From Signal Channel in Both ON
and OFF States
TTL. DTL, RTL Direct Drive Capability
ton. toff < 150ns. Break·Before·Make Action
Crosstalk and Open Load Switch Isolation
> 50dB at 10MHz (75U Load)

ORDERING INFORMATION
TYPE
Dual SPST
Dual DPST
SPOT
Dual SPOT

STANDARD
PART
NUMBER

STANDARD
PART
NUMBER

M X
AT 25°C

DGM161BX
DGM182AX
DGM182BX
DGM184BX
DGM185AX
DGM185BX
DGM187BX
DGM188AX
DGMl88BX
DGM190BX
DGM191AX
DGM191BX

DGMS181BX
DGMS182AX
DGMS182BX
DGMS181BX
DGMS185AX
DGMS185BX
DGMS187BX
DGMS188AX
DGMS188BX
DGMS190BX
DGMS191AX
DGMS191BX

50
50
75
50
50
75
50
50
75
50
50
75

o

ros!on)

M

181

L
A

LPACKAGE
A - lO-PIN METAL CAN
L - 14-PIN FLAT PACK
:
K - CERAMIC DIP
J - EPOXY DIP
TEMPERATURE RANGE
A - MILITARY,.-55°C to
+ 125°C
B - INDUSTRIAL -20°C to
+85°C

L -_ _ _ _ _

DEVICE TYPE

' - - - - - - - - - DRIVER
'------~---- CMOS ANALOG DRIVER

r--~---~--'----~v+

·ud. . t
s
lOO01401

NOTE: 1/2 of DGM182

Figure 1: Functional Diagram (Typical Channel)

3-39
Note: All Iypical values have been guaranteed by characterization and are not tested.

;;
.,.

,..

.

I

I

DUAL SPST (DGM181, 182)
Flat Package (FD-2)

Metal Can Package

C::::====::::;::;J
0,_..........-$,

Dual-In-Line Package

[ :;;::===';:4:3 5,

"'C

"'c

NC

Ne;
IN,

y+

VL

y-

c0000401
COOOOSOI

COOOO601

(OUTLINE DWGS DD, PD)

(OUTLINE DWG TOol00)

SWITCH STATES ARE FOR LOGIC "1" INPUT

DUAL DPST (DGM184, 185)
Flat Package
54

C:::==:::::::;:;;J

Dual-In-Line Package

"

53

D.
0,
5,
IN,

'',

y+

y-

v,

c:::====:J

OND
c0000701

CDOOO801

(OUTLINE DWG FD-2)

(OUTLINE DWGS DE, PEl

SWITCH STATES ARE FOR LOGIC "1" INPUT

Figure 2: Pin Configuration and Switching State Diagram

3-40
Note: All typical values have been guaranteed by characterization and are not tested.

aI:)

DGM181-191

...

I:
CD

SPDT (DGM187, 188)
Metal Can Package

Flat Package (FD-2)

Dual-In-Une Package

I.

NC
NC

NC

0,
52

.NC
VL

v-

V+

GND

COOOO901

COOO1001

c000110J

(OUTLINE DWG TO-100)

(OUTLINE DWGS DD, PD)

SWITCH STATES ARE FOR LOGIC "1" INPUT

DUAL SPDT (DGM190, 191)
Flat Package

Dual-In-line Package
IN,

Ne

v+
(SUBSTRA.TE)

11 Ne

s,

IN,

D,

v+
TOP VIEW
CDOO1201

COOO1301

(OUTLINE DWG FD-2)

(OUTLINE DWGS DE, PEl

SWITCH STATES ARE FOR LOGIC "1" INPUT

Figure 2: Pin Configuration and Switching State Diagram (Cont_)

3-41
Note: All typical values have been guaranteed by characterization and are not tested.

!

!

,......

·.D~

DGM181-f91

co ABSOLUTE MAXIMUM RATINGS
II

g

V+ -v- ............................................................ 36V
:V--VD ........................................................... 33V
VrrV- ............................................................ 33V
. VrrVs ............................................................. ±22V
VL-V- ............................................................ 36V
VL-VIN ............................ , .............................. 30V
VL-VGND ......................................................... 20V
VIN-VGND : ....................................................... 20V
GND-V- ......................................................... 27V

GND-VIN ......................................................... 20V
Current (Any Terminal) .................................... 30mA
Storage Temperature ...................... -65·C to +:150·C
Operating Temperature ................... -55·C to + 125·C
Lead Temperature (Soldering. 10sec) ................. 300·C
Power Dissipation' ................... 450 (TW). 750 (FLAT).
825(OIP)mW
'Device mounted with all leads welded or soldered to PC board. Derate
6mWI'C (TW); 10mWI'C (FLAT); l1mW/'C (DIP) above 7S'C.

. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage·to the ·device. These are stress ratings only. and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
PARAMETER

(v+ = + 15V. v- = -15V. VL = 5V. unless noted)

TEST CONDITIONS
(Note 1)

DEVICE NO.

A SERIES

-55'C

B SERIES

+25'C

+125'C

±1

UNIT

+25'C

+85'C

100

±2.0

200

nA

-20'C

SWITCH
IS(off)

10(011)

= -7.SV

DGMI81, 184. 187, 190

Vs = 7.SV, Vo
VIN-"OFF"

DGM182, 18S, 188, 191

Vs = 10V, VD - -10V
VIN "OFF"

±1

100

±2

200

nA

DGMI81, 184, 187, 190

VS" 7.5V, Vo - -7.5V
VIN-"OFF"

±1

100

±2

200

nA

DGMI82, 185, 188, 191

Vs = 10V, Vo
VIN = "OFF"

±1

100

±2

200

nA

VIN - "ON"

±2

±200

±S

500

nA

-10V, VIN - "ON"

±2

±200

±S

500

nA

20
20

10

20

10

20

IlA
IlA

=

= -10V

= -7.SV,

DGMI81, 184, 187, 190

VO" Vs

DGM182, 18S, 188, 191

Vo

IINL

ALL

VINcOV

±1.0

IINH
DYNAMIC

ALL

VIN-5V

±1.0

DGMI81, 184, 187, 190
DGMI82, 185, 188, 191

See switching time test circuit

10(on) + IS(on)

= VS"

INPUT

Ion

SOO

450

I

250

loll
CS(oll)

ALL
DGMI81, 182, 184, 185,

Vs - -SV, 10 =0, f- lMHz

CO(off)

187, 188, 190, 191

Vo - + SV, IS" 0, f .. 1MHz

6pF typical

Vo=Vs-O, f=IMHz

11 pF typical

COlon) + CS(on)
OFF Isolation

5pF typical

ALL

I

ALL

IL

pF

Typically> SOdS at 10MHz

RL .. 75n, CL = 3pF

SUPPLY
1+

ns

275

10

10

100

10

10

100

100

ALL

10

10

100

100

IGNO
1+

ALL

10

10

100

100

ALL

10

10

100

100

1-

ALL

10

10

100

100

IL

ALL

10

10

100

100

IGNO

ALL

10

10

100

100

VIN - 5V

VIN" OV

Note 1: See Switching State Diagrams for VIN and VIN "OFF" Test Conditions.

3-42
Note: All typical values have been guaranteed by characterization and are not tested.·

100

IlA

DGM181-191
ELECTRICAL CHARACTERISTICS
DEVICE
NUMBER
OGM181
OGM182
OGM184
OGM185
OGM187
OGM188
DGMI90
OGM191

MAXIMUM RESISTANCES rDS(ON)

=

Vo =
Vo=
VoVoVo=
Vo Vo'"
Vo =

=

-55°C

+ 25°C

-

-7.5V
-10V
-7.5V
-10V
-7.5V
-10V
-7.5V
-10V

INDUSTRIAL
TEMPERATURE

MILITARY TEMPERATURE

CONDITIONS (Note 1)
V+ 15V,V- -15V,VL= 5V

Is= -lOrnA
VIN = "ON"

-20°C

+ 25°C

+85°c

-

50
75
50
75
50
75
50
75

50
75
50
75
50
75
50
75

75
100
75
100
·75
100
75
100

-

50
30
50
30
50
30
50

UNIT

+ 125°C

50
30
50
30
50
30
50

75
60
75
60
75
60
75

n
n
n
n
n
n
n
n

APPLICATION COMMENT: The charge iniection in these switches is of opposite polarity to that of the standard OGI80 family, but considerably
smaller.

SWITCHING TIME TEST CIRCuiT
Switch output waveform shown for Vs = constant with
logic input waveform as shown. Note that Vs may be + or
- as per switching time test circuit. Vo is the steady state
output with switch on. Feedthrough via gate capacitance
may result in spikes at leading and trailing edge of output
waveform.
LOGIC
INPUT
tr< 10nl
tf< 10nl

3V--,

SWITCH
INPUT

Vs

SWITCH
OUTPUT

1/
~
J

1.5V~~

0

o.evo

~

..J

J

O.9Vo

O.1VO~
II

ton

toff
WFOO1111

Figure 3: Logic Input for "OFF" to "ON" Condition (DGM1811182 Shown)

SWITCH
INPUT

SWITCH
OUTPUT

SI
O-+--------~-------,

s,'''''+--t-""'; o-------~l-O
,,"o.+--+-~'i ...------+

s.'_'........_'" Oo-----~+~
$,'...'+--t-o"1 - - - -.....
"
"o>--1t--t--+-O"'j
o---t-t.....,

5.0-1---+--+---+--<,..-,
00----.
"
s,O'''+--+-f----t-~-''!

•.'...0+_--..,_+---+_'1

~'oo+--+-+-~-~~_o1
G.

G;

G,
05021001

0S021101

Figure 1: Functional Diagrams and Pin Configurations (Outline Dwgs DO, FD-2, JD, PO)
NOTE: G115 Built-in 16·Pin DIP Only.

3-45
Note: All typical values have been guaranteed by characterization and are not tested.

0115/G123
ABSOLUTE MAXIMUM RATINGS

(25°C)

Source Current (IS) ............... ~ ........................ 100mA
Drain Current (10) ..............•........................... 1OOmA
Gate Current (IG) ......................... : ................... 5mA
Pull-up Control Current (If).: ............................ 100pA
Body to Source (VB-VS .... , ................ -2V to +25V
Body to Drain (VB - Vo) ........................ -2V to + 25V

Body to Gate (VB - VG) ................................... +35V
Body to Pull-up (VB - Vp) ................................. + 35V
Power Dissipation
'
(derate 10mW/oCabove 70°C) .................... 750mW
Lead Temperature (Soldering, 10sec) ................. 300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(per channel unless noted)
LIMITS

DEVICE

PARAMETER

TEST CONDITIONS

ROS(ON)

-20°C

25°C

85°C

125

150

Vso = O. VGO = -30V

Ils=

125

VSO = + 10V. VGO = -20V

limA

250

250

300

500

500

600

VBO= +20V. VGO= -10V

n

Vos= -20V. Vss=VGS=Vps=O

-10

-500

Max

nA

VSO = -20V. VBO = VGO = VPO = 0

-5

-100

Max

nA

IGSS

VGS = -20V. Vos - VSB ~ VPB

=0

-5

-100

Max

nA

VGB = -30V. VPB = -30V. VOS = 0

-0.8

Min

-2.4

Max

mA

-1.5

-1.5

-1.5

Min

VBS= VpS = 0

-4

-4

Max

SVOSS

10 = -101lA. VGB = VSS = VPS = 0

-25

-:4
-25

-25

Min

V

BVsos

IS = -101lA. VGO = VBO = VPO = 0

-25

-25

-25

Min

V

-35

-35

-35

Min

V

-110

-110

-110

Max

V

-35

-35

-35

Min

V

-110

-110

-110

Max

V

Typ

pF

0.4

Typ

pF

18

Typ

pF

9

Typ

pF

3.5

Typ

pF

IS = -101lA. Voo = O.

IG = -101lA. Vos = Vss = VPB

BVGBS
BVpss

=0

Ip = -101lA. Vos = Vss = VGB = 0

GGS. GGO

VGB=O. Vss=O. VOB-O. VPB-O

GOS

f = 1MHz. Body Guarded

3

·

·

G115

.

Max

IS(OFF)

VGS(th)

G123

UNIT

10(OFF)

IG(ON)
G115
and

MINI
MAX

G123

GOB

VOB = -5V. VSB = VGB = VPB = 0
f=IMHz

Both

GSB

VSB = -5V. VOB = O. VGB = VPB = 0
f= lMHz

V

Typical values not garanteed or tested in production

TYPICAL PERFORMANCE CHARACTERISTICS
E

~

10'
VB~" OV

u

10

Z

<[

in

~

15

10'

,-f-'--

....

a:

u

10'

..

50

I

Is"

a:

100~A

Tp. '" 25 C
10



'"

w

>-

.-III p-

~

V SB " VGB,:-O

u

w

0

E

100

..

....
e;

1/

a:

u

::J

~
u
"'z

I-- -

f - ;----I{)
v!'!>

-5

o

V oo - DRAIN BODY VOL TAGE (VI

0P0372Ot

OP037301

3-46
Note: All typical values have been guaranteed by characterization and are not tested.

·
o

0
,3D

>

V(,S

25

20

15

lOO~A

0

-10

GATE SOURCE VOLTAGE (VJ
OP037401

G115/G123·
voltage to be switched (-10V). Therefore, VG should go to
-20V. To insure turn-off VG should not be less than the
most positive voltage to be switched, + 10V. For convenience the same potential as the body could be used.
B-Terminal- This terminal is connected to the body
(substrate) of the chip and must be maintained at a voltage
that is equal to or greater than the most positive voltage to
be switched. This is to ensure that the drain-to-body or the
source-to-body junctions do not become forward biased.
P-Terminal- The potential, with respect to the body, at
this terminal determines the gate-to-source voltage of 01
which determines the amount of drain current available for
driver-collector pull-up. Shorting terminal P to 8 prevents
01 and 03 from conducting, but still allows the body-todrain junction of 01 to act as a forward biased diode for
positive gate voltages, and to act as a Zener diode for
negative voltages which exceed BVOSS (-30 to -90V) for
protecting the gate of 02.
D-Terminal- The common point of the MOSFET
switches (summing point).
S-Terminal- This is the normally-open terminal of the
MOSFET switch and is normally used as the input.

APPLICATION TIPS

Description of Analog Switch
Single Channel

"''":
GATf

SC009201

Figure 3
G-Terminal- This is the control terminal of the switch.
The voltage at this terminal determines the conduction
state of 02. To insure conduction 01 02 when voltages
between ±10V are switched, the gate voltage (VG) should
be at least 10V more negative than the most negative

APPLICATIONS
Dual Current·to·Voltage Converter With Range
Programming

Channel Multiplexer

AF030901

Figure 4

3-47

Note: All typical values have been guaranteed by characterization and are not tested.

AF031001

S! G116,G118,
;; Monolithic
!MOSFET Switch

G119

C5

;. GENERAL DESCRIPTION

FEATURES

;

•
•
•

, These switches may be connected directly to the INTERSIL switch-driver D123 series without need of any interfacing components. These MOSFET switches are inh,~rnally
protected by a Zener diode integrated on the silicon chip. A
MOSFET used as a current source provides an active pullup for' faster switching. The active pull-up FET can be
disabled without sacrificing the Zener protection of the
gates.

r

P-Channel Enhancement-Type MOSFET Switches
Zener Protection on All Gates
With and Without Constant Current Source Pull-,
Up

ORDERING INFORMATION
G116

,~

Package
J - 14·pin Plastic DIP
K - 14-pin CERDIP
L - 14-pin Flat Package
P - 14·pin Hermetic DIP
(Special Order Only)
, L.,"-'- - -_ _ _ _ _ _ _ _ _ _ _
_ _ _ Temperature Range
A - Military (- 55°C to + 125°C)
B - Industrial (- 20°C to + 85°C)
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--,- Device Chip Type
.

~

G116

G118

LD011701

LD011801

G119

LD011901

Figure 1: Functional Diagrams (Outline DwgsPD, JD, FD-2, DO)

3-48
Note: All typical values have been guaranteed by characterization and are not tested,

......
!IJ

t;)

G116, G118, G119

......
~

t;)

ABSOLUTE MAXIMUM RATINGS (25°C)
Source Current (IS) ........................................ 1OOmA
Drain Current (I D) .......................................... 1OOmA
Control Gate Current IG ..................................... 5mA
Pull-Up Gate Current Ip .................................. 100J..lA
Body Voltage (Va) to Any Terminal .......... -2 to + 30V

Power Dissipation (Note) ................................ 750mW
Storage Temperature ...................... -55°C to + 150°C t;)
Operating Temperature ... , ............... -50°C to + 125°C :::
Lead Temperature (Soldering. 10sec) ................. 300°CCG

NOTE: Dissipation rating assumes device is mounted with all leads welded or soldered to printed circuit board in ambient temperature below + 70·C. For
higher temperatures, derate 1OmW I·C.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (Per Channel Unless Noted)
References to pull-up gate P do not apply to G 118.
LIMITS
PARAMETER

rOS(ON)
(Note 1)

TEST CONDITIONS

G116C Series

25°C

25°C

125°C

vso = 0, vGO = -30V, Vps = 0

IS=

100

125

125

VSO = + 10V, VGO = -20V, VPS = 0

-lmA

200

250

250

4S0

600

600

VSO- +20V. VGO= -10V. VPs-O

-O.S

-SOO

-1

G116

-2.S

-2S00

-S

VSO = -20V, VSO = VGO = VPO = 0

IS(OFF)

G116M Series

VOS= -20";
VSO - VGO - VPO = 0
10(OFF)
VG1S to VGSB - 0, VG6S - -30V,
VOS = -20V, VSS = VPS = 0

G116

-3.0

-3000

-6

Gl19

-1.S

-lS00

-3

Gl17

-O.S

-SOO

MINIMAX

UNIT

Max

n

Max

nA

Max

nA

nA

125°C

-1

Max

10 = -10pP., VGS = VSS = VPS = 0

-30

-30

Min

BVSOS

IS = -10pP., VGO = VSO = VpO = 0

-30

-30

Min

BVGSS

IG = -10pP., VPS = VSS = VOS = 0

-30

-30

Min

-110

-110

Max

-30

-30

Min

-110

-110

Max

-1.S

-1.S

Min

-4

-4

Max

-O.S

-0.3

Min

-2

-2.S

Max

BVOSS

Ip = -10pP., VGS = VSS = VOS = 0

BVpSS

/

Is. = -10pP., VOS = -10V, VSS = 0

VGO(th)
IGS(ON)

VGS = -30V, VPS = -30V, VSS = VOS = 0

(Note 2)
IGSS

VGS = -20V, Vos = VSS = VPS = 0

CGO or CGS

Vps = 0, VSS = 0, or VSO = 0

CSO (Note 3)

Body Guarded, f = 1MHz

CSS (Note 3)

VPS = VGS = VOS

= 0,

VpB = VGS = VSS = 0
COG (Note 3)

NOTES:

-1

Max

nA

3

Typ

pF

0.4

0.4

Typ

pF

-3.5

-3.S

Typ

pF

Gl16

18

16
Typ

pF

Typ

pF

VSB = -5V, f = lMHz
Gl18

18

18

G09

10

10

VG6S = -30V, VPB = VSB = 0, VG1S to Gl17
VGSB=O, VOS= -SV, f=lMHz

20

20

VOS = -SV, f = lMHz

rnA

3

-O.S

-500

V

1. For the G 117 this is the resistance from each of the source terminals (S terminals) and the one drain terminal to the internal
junction of the output MOSFETs.
2: Not applicable to G118.
3: Typical values not guaranteed or tested in production.

3-49
Note: All typical values have been guaranteed by characterization' and are not tested.

'G116, G118, G119

,;
;

.. TYPICAL PERFORMANCE CHARACTERISTICS
YD. - ORAIN·BODV VOLTAGE tvl

j

1e,;30 -25 -20

-15 -10

~ ~

~20
~

~~

i

0 100 ~

-5

.9

'-lMHz

w

10

~ ~

/20§

V,. -YG.-O

10

5
5

StNGLE SOURCE.
ALL TYPES

2

VOl· VG• -0

J

~z
~
I

I

1

-30

-25 -20

-15 -10

-5

0

V.. - SOURCE·BODY VOLTAGE (VI
QP057601

OP057701

I
;
i .,.
10'

i

fer'

a,r'
.

~

~::0

c III""

~<

~

~ 1Cf4

0

-10

I

-'0

:§

v•• -GATE-IOURCE VOLTAGE IV}

VG,-GATE·SOURCE VOLTAGE IV!

0P057801

OP0579ot

APPLICATiON TIPS

B-Terminal- This terminal is connected to the body (substrate) of the chip and must be maintained at
a voltage that is equal to or greater than the
most positive voltage to be switched. This is
to insure that the drain-to-body or the
source~to-body junctions do not become forward biased.

Description of Analog Switch

-~:~f[~
~
.

10'

c

.0"

GATE

.

P-Terminal- The potential, with respect to the body, at
this terminal determines the gate-to-source
voltage of Q1 which determines the amount
of drain current available for driver-collector
pull-up. Shorting terminal P to B prevents Q1
and Q3 from conducting, but still allows the
bOdy-to-drain junction of Q1 to act as a
forward biased diode for positive gate voltages, and to act as a Zener diode. for
negative voltages which exceed BVOSS (-30
to -110V) for protecting the gate of Q2.

OOIllAl"
AF037301

Figure 2: Single Channel
G-Terminal- This is the control terminal of the switch; the
voltage at this terminal determines the conduction state of Q2. To insure conduction of
Q2 when voltages between ± 1OV are
switched, the gate voltage (VG) should be at
least 10V more negative than the most
negative voltage to be switched (-1 OV).
Therefore, VG should go to -20V. To insure
turn-off VG should not be less than the most
pOSitive voltage to be switched, + 10V. For
convenience the same potential as the body
could be used.

D-Terminal- The common pOint of the MOSFET switches
(summing point).
S-Terminal - This is the normally-open terminal of the
MOSFET switch and is normally used as the
input.

3-50
Note: All typical values have been guaranteed by characterization and are not tested.

G116, G118, G119
APPLICATIONS

r

........ ~OG

o-:::.t-+---d'f - - - - +

-r::-....-i

O'~~!:\I":':'+-+--+--'f "---4i-*"r...

L

-+---t----~

"",+-+"

..

"'. 1i,_I\I,

AF037501

AF037401

Figure 3: S-Channel Multiplexer
With Series Switch

Figure 4: 3-Channel Differential Multiplexer

3-51
Note: All typical values have been guaranteed by characterization and are not tested.

~ IH3'11/IH312

~

High Speed SPST
; 4-ChannelAnalog S
z

-

"\(>\...

,;;.,v.\;.,/;("l.

GENERAL DESCRIPTION".>""·"

FEAtURES

The IH311 and IH312 are CMO'S;"'<~onolithic, QUAD,
SPST analog switches for use in high-speed switching
applications for communications, instrumentation, process
control and computer peripherals. Both devices provide true
bi-directional performance in the ON condition and will
block signals to 30V peak-to-peak in the OFF condition. The
IH311 and IH312 differ only in that the digital control logic is
inverted, as shown in the truth table.
IH311 and IH312 are available in 16-pin Dual-In-Line
packages and are offered in both military and commercial
temperature ranges.

IH311

•
•
•
•

Switches ± 15V Analog Signals
TTL Compatibility
Logic Inputs Accept Negative Voltages
RON ~ 175 Ohm

ORDERING INFORMATION
PART NUMBER

TEMPERATURE
RANGE

PACKAGE

IH311MJE

-55·C to + 125·C

16 Pin CERDIP

IH311CJE

D·C to +70·C

16 Pin CERDIP

IH311CPE

D·C to +70·C

16 Pin Plastic DIP

IH312MJE

-55·C to + 125·C

16 Pin CERDIP

IH312CJE

O·C to +70·C

16 Pin CERDIP

IH312CPE

O·C to +70OC

16 Pin Plastic DIP

IH312

S1

S1

DUAl·II·LlNE PACKAGE

IN1

IN1
01

01

S2

S2
IN2

IN2

02

02

S3

S3
IN3

IN3
D3

03

S4

S4
IN4

IN4

04

04

TOP VIEW

00035301

CD035401

COO35501

Figure 2: Pin Configuration
(Outline dwgs DE, PEl

Four SPST Switches per Package

Switches Shown for Logic "1" Input
Truth Table
LOGIC

IH311

IH312

0
1

ON
OFF

OFF
ON

Logic "0":0; O.SY
Logic "1" ~ 2.4Y

Figure 1: Functional Diagram

3-52
Note: All typical values have been guaranteed by characterization and are not'· tesled.

307040-001

ABSOLUTE MAXIMUM RATINGS
V+ to V- ............................................... ; ....... 36V
VIN to Ground ........................................... V+, V+
VL to Ground ........................................ -0.3V, 25V
Vs or VD to V + ......................................... 0, -36V
Vs or Vo to V- ............................................ 0, 40V

Peak Current, S or D
(Pulsed at 1msec, 10% duty cycle max) ....... 70mA
Storage Temperature ................... ; .. -65°C to + 125°C
Operating Temperature ................... -55°C to + 125°C
Power Dissipation (Package)"
.
16 Pin Plastic DIP"" ................................. .470mW

V + to Ground ................................................. 25V
V- to Ground ................................................ -25V
Current, Any Terminal Except S or D ................. 30mA
Continuous Current, S or D .............................. 20mA

ELECTRICAL CHARACTERISTICS SYMBOL

"Device mounted with all leads soldered or welded
to PC board.
"·Derate 6.5mWrC above 25°C

MILITARY TEMPERATURE RANGE
TEST CONDITIONS
V1 = + 15V, V2 = -15V
VL=5V, GND

PARAMETER

LIMITS
UNIT
-55°C

+ 25°C

+ 125°C

SWITCH
VANALOG
ROS(ON)

= +5V

Analog Signal Range

V- = -15V, VL

Drain-Source On Resistance

Vo = ±10V, VIN = 2.4V - IH312
IS = lmA, VIN = O.BV - IH311

Source OFF Leakage Current

±15
125

150

±1

100

VS- -14V, VO-14V

±1

100

Vo -14V, Vs - -14V

±1

100

= 14V

±1

100

±2

200

±2

200

IO(off)

Drain OFF Leakage Current

IO(ON)

Drain ON Leakage Current3

Vs = Vo = -14V, VIN
VIN = 2.4V, IH312

Vo - -14V, Vs

= O.BV,

125

V

Vs -14V, Vo = -14V

VIN = 2.4V
IH311
VIN = O.BV
IH312

IS(off)

IH311

n

nA

INPUT
IINH

Input Current With Input
Voltage High

IINL

Input Current With Input
Voltage Low

..-...

.O~Oll ifit

IH311/IH312

= 2.4V

10

±1

10

VIN = 15V

10

±1

10

VIN=OV

10

10

10

VIN

3-53
Note: All typical values have been guaranteed by characterization and are not tested.

p.A

ifit

...
N

.D~OIL
Ion

Tum·ON Time

IotIl

Tum-OFF T'"1e

200

see

Switching Time Test Circuit
Vs = 10V, RL = lkn, CL - 35pF

,1otI2

80

Cs(olf) ,

Source OFF Capacitance
Drain OFF Capacitance

Vs = OV, VIN - 5V, f-1MHz
Vo;'OV, VIN=5V, f= lMHz2

5

CO(oIf)
Co + S(on)
OIRR

Channel ON Capacitance

Vo-VS-OV, VIN-OV, f-1MHz

16

'OFF Isolation4

5

pF

70

VIN = 5V, RL - lkfl,
CL = 15pF" Vs - lVRMS, f = 100kHz 2

Crosstalk
(Channel to Channel)

CCRR

dB

90

"

SUPPLY
1+
1-

Negative Supply, Current

IL

logic Supply Current

NOTES:

ns

"

Positive Supply Current
VIN = 0 and 2.4V'
"

10

1

10

10

1

10

10

1

10

pA

1. The algebraic co,mientionwhereby the most negative value is a minimum, and the most positive is a m'aximum, is used in this data
sheet.
'
2. For design reference, only" not 100% tested.
3. 10(on) is leakage 'from driver into "ON" switch.

4. OFF Isolation - 2010g Vs , Vs = Input to OFF switch, Vo = output.
,VO

3-54
Nota: All typical values have been guaranteed by characterization and are not tested.

~

-......
C')

,IH311/IH312

:z:

...... ABSOLUTE MAXIMUM RATINGS

!

V+ to v- ....................................................... 36V
VIN to Ground ........................................... V+. V+
VL to Ground ........................................ -0.3V. 25V
Vs or VD to V+ ......................................... 0. -36V
Vs or VD to V- ............................................ 0. 40V

Peak Current. S or D
(Pulsed at 1msec. 10o/~ duty cycle max) ....... 70mA
+125°C
storage Temperature ...................... -65°C
Operating Temperature ........................ OOG to + 70°C
Power Dissipation (Package)'
16 Pin Plastic DIP" .................................. 470mW

'0

V + to Ground ................................................. 25V
V- to Ground ................................................ -25V
Current. Any Terminal Except S or D ................. 30mA
Continuous Current. S or D .............................. 20mA

ELECTRICAL CHARACTERISTICS SYMBOL

'Device mounted with all leads soldered or welded
to PC board.
"Derate 6.5mWrC above 25°C

COMMERCIAL TEMPERATURE RANGE
TEST CONDITIONS
V1 = + 15V, V2 = -15V,
VL=5V, GND

PARAMETER

LIMITS
UNIT

+ 25°C

+ 70°C

SWITCH
VANALOG

Analog Signal Range

V- = -15V, VL = +5V

±15

ROS(ON)

Drain-Source On Resistance

Vo = ±10V, VIN = 2.4V - IH212
IS" 1mA, VIN = O.BV - IH211

150

175

Source OFF Leakage Current

±5

100

Vs = -14V, Vo = 14V

±5

100

Drain OFF Leakage Current

Vo -14V, VS'- -14V

±5

100

IO(of!)

VIN = 2.4V
IH311
VIN -O.BV
IH312

Vs -14V, Vo = -14V

IS(oft)

Vo - -,14V, Vs = 14V

±5

100

Drain ON Leakage Currenfl

Vs = Vo = -14V, VIN = O.BV, IH211
VIN * 2.4V, IH212

±5

200

±5

200

VIN = 2.4V

±1

-10

VIN = 15V

±1

10

VIN =OV

±1

-10

IO(ON)

V
n

nA

INPUT
IINH

Input Current With Input
Voltage High

IINL

Input Current With Input
Voltage Low

p.A

DYNAMIC
Ion

Turn-ON Time

Ioft1
10112

Turn-OFF Time

See Switching Time Test Circuit 5
Vs = 10V, RL = 1kn, CL = 35pF

CS(of!)

Source OFF Capacitance

Vs = OV, VIN = 5V, f = 1MHz

5

CO(of!)

Drain OFF capacitance

Vo = OV, VIN = 5V, f = 1MHz2

5

CO+S(on)
OIRR

Channel ON Capacitance

Vo=Vs=OV, VIN-OV, f=1MHz

16

OFF Isolation4
Crosstalk
(Channel to Channel)

CCRR

VIN = 5V, RL = 1kn, CL = 15pF,
.
Vs = 1VRMS, f = 100kHz 2

300
150

ns

pF

70
dB

90

SUPPLY
1+

Positive Supply Current

1-

Negative Supply Current

IL

Logic Supply Current

NOTES:

VIN = 0 and 2.4V

±1

10

±1

-10

±1

10

p.A

1. The algebraic convention whereby the most negative value is a minimum, and the most positive is a maximum, is used in this data
sheet.
2. For design reference only, not 100% tested.
3. 10(on) is leakage from driver into "ON" switch.
4. OFF Isolation = 20log Vs , Vs = input to OFF switch, Vo = output.
Vo
5. Switching times only sampled.

3-55
Note: All typical values have been guaranteed by characterization and are not tested.

Switch output wav!lform shown for Vs = constant with
logic input waveform as shown. Note the Vs may be + or as per switching ~ilT1e test circuit. Vo istl)e 'steady state
output with sWitch on. Feedthroughvia gate bapacitance
may resulUri spikes at leading and trailing' edge of output
waveform. '
, ' , '.
.

f

LOGIC·
INPUT (IN 1) -::\.0

~"'o ~

t,< 20 n5
tf < 20 n5

_ - - - - - - ,~

SWITCH Vs
INPUT

I lof11
_---1~----_-.,.___---J-+--_+_-­
0,9 Vo

SWITCH

OUTPUT (VO) ____~--J
ton

J

'off2

Figure 3: Switching Time Test Circuit
LogiC shown for IH311. Invert for IH312.

Note: All typical values have been guaranteed by characterizatioo:and ·are· noLiested.,:.,." ". "

IID~OIb

IH311/IH312

!

:t

..

I

,(,a

N

+ 15V

+5V
SWITCH
INPUT

Vs

VL

V+
SWITCH
OUTPUT

S1

= 10V D - - t - - - - - - ( y

a-~cr-.--~--o

I

LOGIC
INPUT

Vo

CL
36pF

(REPEAT TEST FOR IN2 IN3 AND IN4)

V-15V
RL

VO=VS
RL

+

rDS(on)

Figure 4: Switching Time Test Circuit

3-57

Note: All typical values have been guaranteed by characterization and are ,not tested..

+16V

TTL
IN~-'W

__r l

+6V

LOO12701

Figure 5: IH311 Schematic (114 as shown)

3-58
Note: All typical values have been guaranteed by characterization and are not tested.

IH4011lH401A
QUAD Varafet Analog Switch
GENERAL DESCRIPTION

FEATURES

The IH401 is made up of 4 monolithically constructed
combinations of a varactor type diode and an N-channel
JFET. The JFET itself is very similar to the popular 2N4391,
and the driver diode is specially designed, such that its
capacitance is a strong function of the voltage across it.
The driver diode is electrically in series with the gate of the
N-channel FET and simulates a back-to-back diode structure. This structure is needed to prevent forward biasing the
source-to-gate or drain-to-gate junctions of the JFET when
used in switching applications.
Previous applications of JFETs required the addition of
diodes, in series with the gate, and then perhaps a gate-tosource referral resistor or a capacitor in parallel with the
diode; therefore, at least 3 components were required to
perform the switch function. The IH401 does this same job
in one component (with a great deal better performance
characteristics).
Like a standard JFET, to practically perform a solid state
switch function a translator should be added to drive the
diode. This translator takes the TTL levels and converts
them to voltages required to drive the diode/FET system
(typically a OV to -15V translation and a 3V to + 15V shift).
With ±15V power supplies, the IH401 will typically switch
18~_p at any frequency from DC to 20M Hz, with less than
30H RDS{on). The IH401A will typically switch 22Vp_p with
less than 50n RDS{on).
.

• . ROS{on) 25n Typical (IH401)
• ID{Off) of 10pA Typical
• Switching Times of 25ns for ton and 75ns for
toff (RL 1kn)
• Built-In Overvoltage Protection (±25V)
• Charge Injection Error of 3mV Typical Into
0.01 IlF Capacitor
• Ciss < tpF Typical
• Can Be Used for Hybrid Construction

=
=

ORDERING INFORMATION
PART NUMBER

PACKAGE

IH401

CERDIP

IH401A

CERDIP

IH401/D

DICE

CD030801

Figure 1: Pin Configuration
(Outline Dwg JE)

3-59
Note: All typical values have been guaranteed by characterization ana,'are.not tested.·

IH401IIH~01A "

Storage Temperature ......................., -65°C to + 150°C
Lead Temperature (Soldering: 10sec) ................. 300°C

Vs to VD .. · ..... ··· .......... · .......................... ,.........,35V
VG to VS, VD ................................................•. 35V
Operating Temperature ................... -55°C to + 125°C

Stresses abQve those listed under Absolute Maximum Ratings may cause permanent damage to the device. Th",se are stress ratings only. and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS AT 25°C/125°C
IH401
SYMBOL

CHARACTERISTIC

UNIT

TEST CONDITIONS
MIN
VORIVE = 15V.
VORAIN = - 7.5V 10 = 10mA

TYP

MAX

20

30

n

ROS(on)

Switch "on" Resistance

Vp

Pinch-Off Voltage

10 = 1nA. VOS = 10V

6

-7.5

V

10(011)

Switch "off" Current
or "off" Leakage

VORIVE = -15V,
VSOURCE = - 7.5V.
VORAIN = + 7.5V

10

±500

pA

10(011)

Switch "off" Leakage
at 125°C

VORIVE = -15V.
VSOURCE = -7.5V.
VORAIN = + 7.5V

0.25

50

nA

IS(oll)

Switch "off" Current

VORIVE = -15V.
VORAIN = -7.5V.
VSOURCE= +7.5V

. 10

±500

pA

IS(off)

Switch "off" Leakage
at 125°C

VORIVE = -15V,
VSOURCE = -7.5V.
VORAIN = + 7.5V

0.3

50

nA·

Vo= Vs = -7.5V.
VO~IVE = + 15V

0.02

±2

nA

Switch Leakage when
10(on) + IS(on) Turned "on"
Vanalog

AC Input Voltage Range
without Distortion

See Figure 3

Vinject

Charge Injection Error
Voltage

See Figure 4

BVdiode

Diode Reverse
Breakdown Voltage. This
Correlates to Overvoltage
Protection

Vo=VS= -V,
10RIVE = 1 jJA.
VORIVE =OV'

BVGSS

Gate to Source or Gate
to Drain Reverse
Breakdown Voltage

lOSS

3

18

Vp_p

3

mVp_p

-30

-45

V

VORIVE = -V.
Vo= Vs = OV.
10RIVE = 1iJA

30

41

V

Maximum Current Switch
can Deliver (Pulsed)

VORIVE = 15V.
VS=OV.
VO=+10V

45

70

mA

fen

Switch "on" time
(Note 1)

See Figure 2

50

,ns

loff

Switch "off" time
(Note 1)

See Figure 2

150

ns

15

NOTE 1: Driving waveform must be > 100ns rise and fall time.

3-60
Note: All typical values have been guaranteed by characterization and are not tested.

IIO~OIlI

IH401/IH401A

...
.....

·5V
+15V

-,s'vSL
STROBE:
INPUT

~

z

'0%

.,5V

SIGNAL

OV

\

-15V

"'"

Your

ton __

-.

",.
loff

-"'" -

-·5V

ton_

TC033601

•

STROBE INPUT

-5V

"'"

lkn

...~

/

OV
i5V SIGNAL

:C---

-5V SIGNAL

10%

(olf - - WF024401

Figure 2: Switching Time Test Circuit and Waveforms

.. 15V

OVLr
-15V

1

C~OOl.1'F

TC033701

TC033801

Figure 3: Analog Input· Voltage Range
Test Circuit

Figure 4: Charge Injection Test Circuit

ELECTRICAL CHARACTERISTICS AT 25°C/125°C
IH401A
SYMBOL

CHARACTERISTIC

TEST CONDITIONS
MIN
VORIVE = 15V.
VORAIN = -10V. 10 = 10mA

UNIT

TYP

MAX

35

50

n

ROS(on)

Switch "on" Resistance

Vp

Pinch-Off Voltage

10 = 1nA. VOS = 10V

4

5

V

10(011)

Switch "off" Current
or "off" Leakage

VORIVE.= -15V.
VSOURCE = -10V.
VDRAIN = + 10V

10

±500

pA

10(011)

Switch· "off" Leakage
at 125°C

VORIVE = ~15V.
VSOURCE = -10V.
VORAIN = + 10V

0.25

50

nA

IS(off)

Switch "off" Current

VORIVE = -15V.
VORAIN = -10V.
VSOURCE = +10V

10

±500

pA

IS(off)

Switch "off" Leakage
at 125°C

VORIVE = -15V.
VSOURCE = -10V.
VORAIN = + 10V

0.3

50

nA

Vo = Vs = -10V.
VORIVE = + 15V

0.02

±2

nA

Switch Leakage when
10(on) + IS(on) Turned "on"
Vanalog

AC Input Voltage Range
without Distortion

See Figure 3

Vinject

Charge Injection
Amplitude

See Figure 4

BVdiode·

Diode Reverse
Breakdown Voltage. This
Correlates to Overvoltage
Protection

VO=VS= -V.
10RIVE = 1/lA.
VORIVE = OV

2

20

-30

3-61
Note: All typical values have been guaranteed by characterization arid are not tested.

22

Vp_p

3

mV p_p

-45

V

',§ . lH4011IH401A
Z
::::.

ELECTRICAL CHARACTERISTICS 'AT 25"C/125°C (tONT.)

~

IH401A
SYMBOL

!

CHARACTERISTIC

UNIT

TEST CONDITIONS
MIN

TYP

MAX
i

BVGSS

Gate to Sowce or Gate
to Drain Reverse
Breakdown Voltage

VORIVE= -V,
Vo=Vs=OV,
,IPRIVE = lIlA

30

41

V

loss

Maximum Current Switch
can Deliver (Pulsed)

VORIVE = 15V,
Vs = OV,
VO=+10V

35

55

~A

ton

Switch "on" time
(Note 1)

See Figure 2

50

ns

toft

Switch "off" time
(Note 1)

See' Figure 2

150

ns

NOTE: Driving waveform must be,

> 1DOns

rise and fall time.

,APPLICATIONS
IH401 Family
In general, the IH401 family can be used in any application formally using a JFET /isolation diode combination
(2N4391 or similar). Like standard FET circuits, the IH401
requires a translator for normal analog switch function. The
translator is used to boost the TIL input signals to the ± 15V
analog supply levels which allow the IH401 to handle ±7.5V
analog signals (or IH401A to handle ±10V analog signalS);
A typical simple PNP translator is shown in Figure 5.
-l!iV

Although this simple PNP circuit represents a minimum of
components, it requires open collector TTL input and t(off)
is limited by the collector load resistor (approximately 1.5J.1s
for 10kn). Improved switching speed can be obtained by
,increasing, the complexity of the translatorl;ltage.
'
A translator which overcomes the problems of the simple
PNP stage is the Intersil IH6201. * This translator driving an
IH401varafet produces the following typical features:
, '. Ion' time of approx. 200ns
• toff time 0.1 approx." 80(1s

• TIL compatible Strobing levels of

IN

L..

,.....,

O.4V...J

L...

• ID(on) +IS(on) typically 20pA up to ±10V analog
signals
• ID(Off) or IS(off) typically 20pA
,. Quiescent current drain of approx. 100nA in either
".on" or "off" case

+15V

,....,

break before
make switch
+2 .• V

ANALOG
SIGNALS

ov...J

J

lQ4(O

FROM TTL
OPEN COLLECTOR

lOGIC

*Th,e IH6201 is a dual translator (two independent
,tran~lators per package) constructed from monolithic
CMOS technology. The schematic of one-half IH6201,
driving one-fourth of an IH401, is shown in Figure 6.

t15V
TC033901

Figure 5

3-62
Note: All typical values have been guaranteed by characterization and are not, tested.

.n~nlb

IH401/IH401A

I...

i

~
.~

r----'

I
I

UV

Uy..r-L.

I
I
I

I

I

IL_v~_J
• I

+I5V

B

+15,r' '.

-15Y~
..
.. I
I

- +15V

I
I

I
I

I

I

B."1..I'
.. -ISV

i

-15Y
05027801

NOTE: Each translator output has a 9 and

11

output.

11

is, just the .inverse of 8 i.e:.

(~ output·is

1sOo
"out of,

Figure 6: IH6201 Driving An IH401

Phas~ with

,.

CD030QOI

NOTE: Either switch is turned on when strobe input goes high.

Figure 7: Dual SPST Analog Switch

Note: AU typical values have been guaranteed by characterization and are not tested.'

respect to 8 output).

+3V

ovs-LT2L1

COO31001

Figure 8: DpDTAnalog :SWltCh

(i§)----<

T2L INPUT 1

'. d ~

liiil---< r2L INPUT 2

COO:J1101

Figure 9: Dual SPDT Analog Switch
A very useful feature of this system is that one-half of an
. IH6201 and one-half of an IH401· can combine to make a
SPOT switch, or an IH6201 plus an IH401 can make a dual
\ SPOT analog switch. (See Figure 9)

.!.j'

00031201

Figure 10: Dual DPST Analog Switch

Note: All typical values have been guaranteed by characterization and IlI"I\ not. tested.,

IH5'009-IH5024
Virtual Ground
Analog Switch
GENERAL DESCRIPTION

FEATURES

The IH5009 series of analog switches were designed to
fill the need for an easy-to-use, inexpensive switch for both
industrial and military applications. Although low cost is a
primary design objective, performance and versatility have
not been sacrificed.
Each package contains up to four channels of analog
gating and is designed to eliminate the need for an external
driver. The odd numbered devices are designed to be
driven directly from TTL open collector logic (15 volts) while
the even numbered devices are driven directly from low
level TIL logic (5 volts). Each channel simulates a SPOT
switch. SPOT switch action is obtained by leaving the diode
cathode,unconnected; for SPOT action, the cathode should
'be grounded (OV). The parts are intended for high performance multiplexing and commutating usage. A logic "0"
turns the channel ON and a logic "1" turns the channel
OFF.

•
•
•
•
•
•

Switches Analog Signals Up to 20 Volts Peak-toPeak
Each Channel Complete - Interfaces With Most
Integrated Logic
Switching Speeds Less Than O.S~
IO(OFF) Less Than SOOpA Typical at 70·C
Effective rds(ON)- sn to son
Commercial and Military Temperature Range
Operation

ORDERING INFORMATION
BASIC
PART NUMBER

CHANNELS

LOGIC
LEVEL

~ACKAGES

IH5009

4'

+15

JD,DD,PD

IH5010

4

+5

JD,DD,PD
JE,DE,PE

IH5011

4

+15

IH5012

4

+5

JE,DE,PE

IH5013

3

+15

JD,DD,PD

IH5014

3

+5

JD,DD,PD

IH5015

3

+15

JE,DE,PE

IH5016

3

+5

JE,DE,PE

IH5017

2

+15

JD,DD,PA

IH5018

2

+5

JD,DD,PA
JE,DE,PA

IH50XX

M

DE

L

Package
PA - 8-PIN PLASTIC DIP
PD - 14-PIN PLASTIC DIP
PE - 16-PIN PLASTIC DIP
DO - 14-PIN CERAMIC DIP
(Special Order Only)
DE - 16-PIN CERAMIC DIP
(Special Order Only)
JD - 14-PIN CERDIP
JE - 1.6-PIN 'CERDIP
' - - - - - - TEMPERATURE RANGE
M = MILITARY (-55°C to
+ 125°C)
C = COMMERCIAL (O°C to
+ 70°C)
L..._ _ _ _ _ _

IH5019

2

+15

IH5020

2

+5

JE,DE,PA

IH5021

1

+15

JD,DD,PA

IH5022

1

+5

JD,DD,PA

IH5023

1

+15

JE,DE,PA

IH5024

1

+5

JE,DE,PA

NOTE: Mil-Temperature range (-55°C to
packages only.

+ 125°C) available in ceramic.

3-65
Note: All typical values have been guaranteed by characterizaijon' and are not tested ..

BASIC PART NUMBER

.~.

·:s.. I H500Q-1tHS024,
. ~,' ... ,..... ,.. ".,': '. . "' ,

'

·.O~1lIL
,

, f i'

:.

.'

"

'. f.~',·

"

~~~';

'I' ABSOLUTE MAXIMUM RATINGS

i
I

Lead Temperature (Soldering, 1O~~~) .......... :: ..... 300·6
Operating Temperature
5009C Series ....... " ........ : ........ :. 0·0' to + 70·0
5009M Series ... :' .......... : ...... :. ":55·C Jo +125·C
Lead Temperature (Soldering/tOsee) ....... : ... , ..... 300·C

Positive Analog Signal Voltage ............................ 30V
Negative Analog Signal Voltage ......................... -15V
Diode Current ......................................... '" ..... 1OmA
Pow~r Dissipation (Note} ......................... ~~ ....• 500mW
Storage Temperature ....... :: ........'..... -65"C to + 150·C

NOTE: Dissipation rating assumes devies is mounted with all leads welded or soldered to printed circuit board in ambient temperature below 75'G. For higher
temperature. derate at rate of 5m/W'G,

.. . . . . . . .

..

Stresses above those listed under Absolute Mllxim~m Ratings may cause permanent damage to the device. These are stress ratings only. ana fu~ctiollal
operation of the device at. these or any other conditions above those indicated in the operational sections of the specificatiQns is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
..,"
.

IH5009 (rOS(ON)::; 100n) IH5010
(rOS(ON)::; 150n) 14 PIN DIP
(OUTLINE DWGS DO, PO, JD)

IH5013 (rOS(ON) ~ 100n) IH5014
. (rOS(ON)::; 150n) 1.4 PIN DIP
(OUTLINE DWGS DO, PE; JE)

IH5011 (rOS(ON)::; 100n) IH5012
(rOS(ON) ::; 150n) 16 PIN DIP
(OUTLINE DWGS DE, PE, JE)

COOO~9Ol

CDOO1801

c0001701

IH5015 (rOS(ON)::; 100n) IH5016
(rDS(ON) ::; 150n) 16. PIN DIP
(OUTLINE DWGS DE, PE, JE)

IH5019 (rOS(ON)::; 100n) IH5020
(rOS(ON) ::; 150n) 8 PIN DIP'
(OUTLINE DWGS DE; PA, JE)

IH5017 (rOS(ON)::; 100n) .1""5018
(rOS(ON)::; 150n) 8 PIN DIP
(OUTLINE DWGS DO: PA, JD)

11 I ~ I;; :~t'-----t:~- r- -'" -:L.~I;~
-'
[1.J
:2

7

:2

10

CDO02101

,'.
7

CDOO2201

c0002001

. IH5023 (rOS(ON)::; 100n) IH5024 (rOS(ON)::; 150n)
8 PIN DIP (OUTLINE DWGS DE, PAl

IH5021 (rDS(ON) ::; 100n) IH5022 (rOS(ON)::; 150n)
8 PIN DIP (OUTLINE DWGS DO, PA, JD)

: I~ 1-~
I

--+-<0.

CDOO2401
CDOQ2301

(Note: Numbers in brackets refer to CERDIP packages.)

Figure 1: Pin Connections

3-66
Note: All typical values have been guaranteed by characterization and are not tested.

IH5009-IH5024
FOUR CHANNEL
IH5009 (rDS(ON):O: 100n) .
IH5010 (rOS(ON):O: 150n)
14 PIN DIP

THREE CHANNEL

IH5011 (rOS(ON):O: 100n)
IH5012 (rOS(ON):O: 150n)
16 PIN DIP

IH5013 (rOS(ON):O: 100n)
IH5014 (rOS(ON):O: 150n)
14 PIN DIP

. IH5015 (rOS(ON):O: 100n)
IH5016 (rOS(ON):O: 150n)
16 PIN DIP

IT
•

3~'

t. b,

8

T.T.

'~8

t. L

,IT.

"~.

t2 b'0

IT

08000801
05016901

05016801

05016701

TWO CHANNEL
IH5017 (rDS(ON):O: 100n)
IH5018 (rOS(ON):O: 150n)
8 PIN DIP

SINGLE CHANNEL

IH5019 (rOS(ON):O: 100n)
IH5020 (rOS(ON):O: 150n)
8 PIN DIP

IH5021 (rOS(ON):O: 100n)
IH5022 (rOS(ON) S 150n)
8 PIN DIP

3~'

"TT!Yr4 31T'

t . .b2
.~.

t.
DSOOO901

IH5023 (rOS(ON):O: 100n)
IH5024 (rOS(ON):O: 150n)
8 PIN DIP

3

,

•

•

2

b7

DSOO3701

08001001

Figure 2: Device Schematics and Pin Connections

ELECTRICAL CHARACTERISTICS

(per channel)
SPECIFICATION LIMIT

SYMBOL
(Note 1)

TEST
CONDITIONS
(Note 2)

TYPE
(Note 4)

-55'e (M)
o'e (e)
MINIMAX

TYP

MINIMAX

+ 125'C (M)
+70'C (C)
MINIMAX

VIN - OV, 10 - 2mA

0.Q1

±0.5

100

p.A

5V Logic Ckts

VIN = +4.5V, VA = ±10V

0.04

±0.5

20

nA

Input Current-OFF

15V Logic Ckts

VIN- +l1V, VA-±10V

0.04

±0.5

20

nA

VIN(ON)

Channel Control Voltage·ON

5V Logic Ckls

See Figure 7, Note 3

0.5

0.5

0.5

.V

1.5

CHARACTERISTIC

IIN(ON)

Input Current-ON

ALL

IIN(OFF)

Input Current-OFF

IIN(OFF)

25'C

UNIT

VIN(ON)

Channel Control Voltage·ON

15V Logic Ckts

See Figure 8, Note 3

1.5

1.5

V

VIN(OFF)

Channel Control Voltage·OFF

5V Logic Ckts

See Figure 6, Note 3

4.5

4.5

V

VIN(OFF)

Channel Control Voltage·OFF

15V Logic Ckts

See Figure 8, Note 3

11.0

11.0

V

10(OFF)

Leakage Current-OFF

5V Logic Ckts

VIN = +4.5V, VA - ±10V

0.02

±0.5

20

nA

10(OFF)

Leakage Current-OFF

15V Logic Ckts

VIN= +11V, VA=±10V

0.02

±O.S

20

nA

IO(ON)

Leakage Current·ON

5V Logic Ckts

VIN = OV, Is = lmA

0.30

±1.0

1000 (M)
200 (C)

nA

±0.5

500 (M)
100 (C)

nA

1.0

10

p.A

2.0

100

p.A

150

385 (M)
240 (C)

n

80

100

250(M)
160 (C)

150

500

= OV, IS = lmA
= OV, Is - 2mA
VIN = OV, IS = 2mA
10 =2mA, VIN = 0.5V

10(ON)

Leakage Current-ON

15V Logic Ckts

VIN

IO(ON)

Leakage Current·ON

5V Logic Ckts

VIN

1[)(ONt

Leakage Current·ON

15V Logic Ckts

rOS(ON)

Drain-Source ON·Resistance

5V Logic Ckts

roo(ON)

Drain-Source ON·Resistance

l(on)

Turn-ON Time

15V Logic Ckts
All

10 = 2mA, VIN = 1.5V

See Figures 5 & 6
3-67

Note: All typical values have been guaranteed by characterization and are not tested.

0.10

150
100

90

n
ns

r&n~Dn

,lflsO09~B5024

_UlNJUl$lJ'I@}UfD

ELECTRICAL CHARACTERISTICS (CONT.)
,

SPECIFICATION LIMIT
SYMBOL
(Note 1)

TEST
CONDITIONS
(Note 2)

TYPE
(Note' 4)

CHARACTERISTIC

-55'C (M)

2S'C

,O'C (C)
MINIMAX

t(off)

Turn-OFF Time
Cross Talk

CT

See Figures 5 & 6
f = 100Hz

All
All

TYP

MINIMAX

300
120

500

,

+12S'C (M)
+,70'e (e)
' MINIMAX

UNIT

ns
dB

NOTES 1: (OFF) and (ON) subscript notation refers to the conduction state of the FET switch for the given ,test.
2: Refer to Figure 2 for definition of terms.
3: V'N(ON) and V'NIOFF) are test conditions guaranteed by the tests of rOSION) and IO(OFF) respectively.
4: "5V Logic CKTS' applies to even-numbered devices. "15V Logic CKTS' ' applies to odd·numbered devices.

TYPICAL PERFORMANCE CHARACTERISTICS
ID(ON) VI. IS AT 25'e

1 1000

1 lOOk

...

....

~

~
I

z

/

Z

0:
0:

i... looo
...0
...
...Z

!='s"mA
f-VA -10V

I

~
c(

c(

I.S
2.0
2.5
. I, - SOURCE CURRENT (mAr

~

10

9

<.> 1.4

~ 1.2
w

-120
-110

25
7S
TEMPERATURE ( Cl

:;
~ 1.0

/'
V

0:

~

...~"
....
c(

I
1

rt ~

:"0.8 ! - ' f-

z

~

cf 0.6

r-o

25
50
75
TEMPERATURE ( CI

100

.

......
c(

/

100

25
50
7S
TEMPERATURE r Ci

"-

-90
-80
-70

10kU

'\.

"- I'\.

a: -60

"-

-so

I' . -

0

t.>

-40
-30
10

100

0P004201

CROSSTALK MEASUREMENT CIRCUIT

.r,

!-100

VI

N

~

'--

~

.'

CROSSTALK AS A
FUNCTION OF FREQUENCY
-130

I /'
Y

':"

1--

0P00e001

RD~ON) VI. TEMPERATURE
(NORMALIZED TO 25'C VALUE)

'"o

(11

':" +iV.'
.15V

...u

OP007911

.N

.

I

R

'.1,0

10D.!>

100

....

~.-

Is

V

I

."

-~~

E::
-~~
t- ;::::

:::> 100

lk

<.>

..."....

I.

.

0:.
0:

:::>

~
c(

g

10k

ID(OFF) VI. TEMPERATURE

0:
0:

a 100

~,

(per channel)

ID(ON) VI. TEMPERATURE

~

v,.

...

-5\1 (5010ETCI
'16VI6008HCI

100
lK
lQK lOOK
FREQUENCY 1Hz.)

OPOO4311

1M

TC004201

OPOO44Q1

DETAILE.D DESCRIPTION
The signals seen at the drain of 'a junction FET type
analog switch can be arbitrarily divided into two categories;
those which are less than ±200mV, and those which are
. greater than ±200mV. The former category iricludesall
those circuits where switching is performed at the virtual
ground point of an op-amp, and it is primarily towards these
applications that the IH5009 family of circuits is directed.

Those devices which feature common drains have another FET in addition to the channel switches. This FET, which
has gate' and source connected' such that VGS = 0, is
intended to compensate for the on-resistance of the switch.
When placed in series with the feedback resistor (Figure 3)
the gain is given by:

By limiting the analog signal at the switching point to
±200mV, no external driver is required and the need for
additional power supplies is eliminated.
Devices are available with both common drains and with
uncommitted drains.

Note: All typical values have been guaranteed by characterization and are nof tested •.

G~N=

10kn + rOS(ON)(compensator)

...

10kn + rOS(switch)

1145009-1115024
SWITCHING CHARACTERISTICS

A.OOO8OI

Figure 3: Use of Compensation FET

TC0G4301

"'"

Clearly, the gain error caused by the switch is dependent
on the match between the FETs rather than the absolute
value of the FET on-resistance. For the standard product,
all the FETs in a given package are guaranteed to match
within son. Selections down to sn are available however.
Contact factory for details. Since the absolute value of
rOS(ON) is guaranteed only to be les$ than 1oon or 1son, a
substantial improvement in gain accuracy can be obtained
by using the compensating FET.

10V

PW-5I,..
tr <0.1/001

.,<0.1".

?5V

7.5V

f1II

10"

OUTPUT

V... ·,OV
f1II
f1II
OUTPUT·~

VA--1OV

WFOO1301

DEFINITION OF TERMS

Figure 5: High Level Logic

Figure 4.
. 'if1N
PW • 5,l1

NOISE IMMUNITY

5 V r - - - -.......
2.5V
Z.5V
toFF

t.--.....-oVOUT

,

ANALOG

OUTNl

,,

,,

__ ...

&!i~T!.L!.A!E

_~

_ _'
lCOOO101

Figure, 7: Interfeclng .wIth

+ 5V Logic

,,',4-+-+-h

,

,

,,r-----'.:..--.,..---,
,,,
,

ANALOG
INPU1Nwtl

:

L ___________

'lSV

1

7

•

I

"

"'~ e~,A.w:TE.ISTtCS4AI" '"

-::.UT " Rn

14

~

-,~'
AF:001001

_LOG

Figure 9

, OUT1'UT

<·'1

,,,
,

,,,
,
:L!~!!~G~T! ____
":' ":'..J
-=-:

..))

,

LCOOO2Ol

Figure 8: Interfec.!ngwlth + 15V Open
Collector Logic

10Kn

,,
I

,
,
,,,
,
,,

I,;

:

ANALOG

INPUTS

,1Gttu

11

I
L -- --, 4

10kn

I

AFOOt1m

Figure, 10
NOTE: Additional applications information is given in Application Bulletins A003 "Understanding and Applying the
Analog Switch" and A004 "The 5009 Series of Low Cost
Analog Switches".

3-70
Note: All typical values have been guaranteed by characterizatiOn, and. are not tested.

, '.

IH5025-IH5038
Positive Signal
Analog Switch
GENERAL DESCRIPTION

FEATURES

The IH5025 series of analog switches was designed to fill
the need for an easy-to-use, inexpensive switch for both
industrial and military applications. Although low cost is a
primary design objective, performance and versatility have
not been sacrificed.
Each package contains up to four channels of analog
,gating and is designed to eliminate the need for an external
driver.
.
The entire family is designed to be driven from TTL open
collector logic (15V), but can be driven from 5V logic if
signal input is less than 1V. Alternatively, 20V switching is
readily obtainable if TTL supply voltage is +25V. Normally,
only positive signals can be switched; however, up to ±10V
can be handled by the addition of a PNP stage (Figure 14)
or by capacitor isolation (Figure 13). Each channel is a
SPST switch. A logic "0" turns the channel ON and a logic
"1" turns the channel OFF.

•
•
•
•
•
•

Switches Up to + 20V Into High Impedance
Loads (i.e. Non-Inverting Input of Operational
Amp.)
Driven From TTL Open Collector Logic
IO(OFF) < 50pA
rOS(ON) < 150n
rOS(ON) Match < 50n Channel to Channel
Switching Speeds < 100ns

ORDERING INFORMATION
BASIC
PART NUMBER

CHANNELS

LOGIC
LEVEL

PACKAGES

IH5025

4

+15

JD,DD,PD

IH5026

4

+5

IH5027
IH5028

4
4

+15
+5

JD,DD,PD
JE,DE,PE

IH5029

3

+15

JD,DD,PD

IH5030

3

+5

IH5031

3

+15

JD,DD,PD
JE,DE,PE

IH5032
IHS033

3
2

+5
+1S

JE,DE,PE
JD,DD,PA

IHSOXX

IHS034

2

+5

2

+15

JD,DD,PA
JE,DE,PA

IHS036

2

+5

JE,DE,PA

IHS037
IH5038

1
1

+15
+5

JD,DD,PA
JD,DD,PA

DE

L

PACKAGE
PA - a-PIN PLASTIC DIP
PD - 14-PIN PLASTIC DIP
PE - 16-PIN PLASTIC DIP
DD - 14-PIN CERAMIC DIP
(Special Order Only)
DE - 16-PIN CERAMIC DIP
(Special Order Only)
JD - 14-PIN CERDIP
JE - 16-PIN CERDIP
L -_ _ _ TEMPERATURE RANGE
M = MILITARY (-SSOC to
+ 12S°C)
C = COMMERCIAL (O°C to
+ 70°C)

JE,DE,PE

IHS03S

M

' - - - - - - - - BASIC PART NUMBER

NOTE: Mil-Temperature range (-5S0C to + 12S°C) available in
ceramic packages only.

IH5025 (rOS(ON) ::; 100n)
IH5026 (rOS(ON)::; 150n)
14 PIN DIP

IH5027 (rOS(ON)::; 100n)
IH5028 (rOS(ON)::; 150n)
16 PIN DIP

IH5029 (rOS(ON):S 100n)
IH5030 (rOS(ON):S 150n)
14 PIN DIP

IH5031 (rOS(ON):S 100n)
IH5032 (rOS(ON):S 150n)
16 PIN DIP

11

4
C0004201

CDOO2501

CDOO2601

Figure 1: Pin Connections

3-71

Note: All typical values have been guaranteed by characterization' and are not tested.

5

12
COOO2701

IH5025-IH5C)38
,
{;

~,

~

IH5033 (rOS(ON) ~ 100.12)
IH5034 (rOS(ON) ~ 150.12)
8 PIN OIP
(3)3

'

IH5037 (rciS(ON)~ 100.12)
IH5038 (rOS(ON) ~ 150.12)
8 PIN DIP

IH5035 (rOS(ON) ~ 100.12)
IH5036 (rOS(ON) ~ 150.12)
8 PIN OIP

6(12)

(3)3

7(15)

(2)2

I
3(3)

(2)2

O-+_4-<~------IHl6(·'4)

4(4)

('3)9-11---<>"1 "'---.--If-Q5(11)

6(14)

'(1)

4(4)

(212

o-j----4'i

5('3)

CDOO2801

CDOO4101

CDOO29()1

NUMBERS )N PARENTHESES INDICATE CERAMIC PACKAGE PIN-OUT

Figure 1: Pin Connections (Cont.)

FOUR CHANNEL
IH5025 (rOS(ON) ~ 100.12)
IH5026 (rOS(ON) ~ 150.12)
14 PIN DIP

THREE CHANNEL
IH5029 (rOS(ON) ~ 100.12)
IH5030 (rOS(ON) ~ 150.12)
14 PIN DIP

IH5027 (rOS(ON) ~ 100.12)
IH5028 (rOS(ON) ~ 150.12)
14PIN DIP

'rr'

'n'

'rr.
'rr"
2

•

,

"

IH5031 (rOS(ON) ~ 100.12)
IH5032 (rOS(ON) ~ 150.12)
~6 PIN DIP

"rr"
10

12

15

13

'rr'
'rr"

"

05001301

2

•

7

•

10

12

DSOQ1401

05001201

05001101

TWO CHANNEL

SINGLE CHANNEL

IH5033 (rDS(ON) ~ 100.12) IH5034
(rOS(ON) ~ 150.12)
8 PIN DIP

IH5035 (rOS(ON) ~ 100.12) IH5036
(rOS(ON) ~ 150.12)
8 PIN DIP

IH5037 (rOS(ON) ~ 100.12) IH5038 .
(rOS(ON) ~ 150.12)
8 PIN DIP

~rr~

5(11)

3(31

'(1)
05001701

6(12)

8(''')
05001501

09001601

Numbers in parentheses indicate CERAMIC PACKAGE LAYOUT

.

Figure 2: Device Schematics

3-72
Note: All typical values have been guaranteed by characterization and are not tested.

i

IH5025-IH5038

§

ABSOLUTE MAXIMUM RATINGS

t

Positive Analog Signal Voltage ............................ 25V
Negative Analog Signal Voltage ..................... -O.5VDC
Drain Current ................................................. 25mA
Power Dissipation (Note) ................................ 500mW
Storage Temperature ...................... -65'C to + 150'C

Operating Temperature
Z
5025C Series ............................ O'C to + 70'C
5025M Series ...................... -55'C to + 125'C to»
Lead Temperature (Soldering, 10sec) ................. 300·C. CD

g

NOTE: Dissipation rating assumes device is mounted with all leads welded
or soldered to printed circuit board in ambient temperature below 7S·C.
For higher temperature, derate at rate of 5m/W·C.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (per channel)
SPECIFICATION LIMIT
SYMBOL
(Note 1)

CHARACTERISTIC

TEST

TYPE

-55'C

CONDITIONS

O·C (C)
IIN(ON)

Input Current·ON

All

UNIT

25'C

(M)
TYP

MINIMAX

0.30

VIN = OV

IIN(OFF)

Input Current-OFF

All

VIN = 15V

VIN(ON)

Channel Control Voltage·ON

All

See Figure 3

1.5

VIN(OFF)

Channel Control Voltage·OFF

All

See Figure 3

14.0

ID(OFF)

Leakage Current·OFF

All

See Figure 5

0.20

+ 125'e (M)
+ 7O'e (e)

1.0

100 (M)
25 (C)

1.0

50 (M)
50 (C)

nA (max)

1.5

1.5

V (max)

nA (max)

14.0

V (min)

0.5

100 (M)
50 (C)

nA (max)
nA (max)

14.0
0.06

MINIMAX

ID(ON)

Leakage Current·ON

Odd Nos.

See Figure 6

1.00

10.0

5000 (M)
250 (C)

ID(ON)

Leakage Current·ON

Even Nos.

See Figure 6

0.10

1.0

500 (M)
25 (C)

nA (max)

100.0

250 (M)
150 (C)

n

(max)

150.0

385 (M)
240 (C)

n

(max)

n

(max)

n

(max)

rDS(ON)
rOS(ON)

Drain·Source ON·Resistance

Drain·Source ON-Resistance

Odd Nos.
Even Nos.

100

VIN = 0.5V, ID = 1rnA
VIN = 0.5V, ID = 1rnA

rDS(ON)

Drain-Source ON-Resistance

Odd Nos.

VIN = 1.0V, ID = lmA

rDS(ON)

Drain-Source ON-Resistance

Even Nos.

VIN-l.0V.ID=lmA

t(oo)

Turn·ON Time

I(off)
Q(INJ)

60.00

150

90.00
85.00

160.0

420 (M)
250 (C)

110.00

200.0

400 (M)
250 (C)

0.2

0.4
0.4

160

All

See Figure 4

0.10

Turn·OFF Time

All

See Figure 4

0.10

0.2

Charge Injection

All

See Figure 5

7.0

20.0

VA(OFF)

Cross Coupling Rejection

All

See Figure 6

0.10

1.0

AraS(ON)

Channel to Channel rDS(ONl Match

All

VIN

= 0.5V.

I1S (max)
mVp•p (max)
mVp. p (max)

n

25.00

ID = 1rnA

1'5 (max)

(max)

Note 1: (OFF) and (ON) subscript notati9n refers to the conduction state of the FET switch for the given test.

+10V~VOU~OSCOftEPA08E
!10XI

VAYl.
. 'vou,

f

10Mu

1'KO

FET "ON" FOR VIN

n

1 K!!

+1SY

OV~LOGtc·

--l
.. r-"
.~:
YOUT

II
II

II
II

tOFF

tON

1.5V

Fer "OFF" FOR VIN ;><.,.14.0V
TC004501

TCOO4601

Figure 3: Test Circuits

Figure 4: Test Circuits

3-=-73
Nole: All typical values have been guaranteed by characterization and are not tested.

OV

+5Y

.oon

~

: ~~y

·,5V

OyJL

.

TCOO4101

1 Ku

'0"",

..•
f.., 1 KC

Figure 5: Test Circuits

+lSV

TCOo4'BOI

t::1gure 6: Test Circuits

TYPICAL PERFORMANCE CHARACTERISTICS (per channel)
IO(OFF) VS. TEMPERATURE

~'"

+10V
lOOnA f-

...

+ , . _. f--

lOOnA

f--

1DnA

..

ii: 10nA r----1

'.

.E

.........,..

~

vP'

+15V

9

./

~

V

InA

.E lOOpA

V
/'

loopA
10pA

IO(ON) VS. TEMPERATURE

/

lDpA

1 pA /

~

/'

tl-

+IOV,::,'
-25

+25

+75

+25

~25

+125

+75

TEMPERATURE (OC)

TEMPERATURE (OC)

OPOO4601

, OPOO4501

CROSS COUPLING REJECTION VS. FREQUENCY
14

~I
I-

::>

~

ROS(ON) Vs. VIN
200

+5V

12

176

10

150

c:

8

6

S

a: 75
4

I

/

125

j'00

-

~io"'"

.,

V

50

25

o L.J::::::t=t=:l::::::L-.L.J
1 KH,

10 KH,

100 KH,

.

+125

OV

1 MH,

FREQUENCY

0.5V

1.0V

1.5V

VIN
OP00471 I

0P004801

3-74
Note: All typical values have been guaranteed by characterization' and are not tested.

LOGIC INTERFACE CIRCUITS

Channel FET has been sel4ilcted betw~en 2.0V and3.9V;
thus with + 15V at the logical.input, and a + 10V signal
input, 1.1 V of margin exists for turn-off. When the IH5025 is
used with 5V TIL logic, a maximum of + 1V can be
switched. The gate of each FET has been brought out so
thaI a "referral resistor" can be placed between gate and
source. This is used to minimize charge injection effects.
The connection, is shown below:

When operating with TIL logic it is necessary to use pUIIup resistors as shown in Figures 6 and 7. This ensures the
necessary positive voltages for proper gating action.

r---------...,...,

TC00400l

LCOOO3OI .

Figure 9

Figure 7: Interfacing with + 5V Logic

For switching levels> + 10V, the + 15V power supply
must be increased so that there is a minimum of 5V of
difference between supply and signal. For example, to
switch + 15V level, + 20V TIL supply is required. Up to
+ 20V levels can be gated.

r--- ---,+,5V
I
I

-

APPLICATIONS

•I
I

I
I

I
I•
I
1..:
_GATE""
_____
"5V_
TTL
."...1I
LC000411

Figure 8: InterfaCing with + 15V Open
Collector Logic
.

THEORY OF OPERATION
The IH5025 series differs from the IH5009 series in that
they may be driven by floating outputs. This family is
generally used when operating into thenon-invertil"lg inpl,rt
of an operational amplifier, while the IH5009series is used
in operations where the output feeds into the inverting
(virtual ground) input.
. The IH5025 model is a basi~ charge. area sViitching _
device, in that proper gating action .depends upon the
.capaoitance vs. voltage· relationship fort"'e diode junctions.
This C vs. V, when integrated, produces total charge Q. It is
Q total which is switched between the series diode and the
gate to source and gate to drain junctions. The charge area
(C vs. V) for the diode has been chosen to be a minimum of
four (4) times the area of the gate to source junction, thus
providing adequate safety margins to insure proper switching action.
If normal logical voltage levels of ground to + 15V (open
collector TIL) are used, only signals which are between OV
and + 10V can be switched. The pinch-off range of the p-

AFOOt2Of

Figure 10: Multiplexer from Positive Output
Transducers

+111,1

ov.fL.
AFOO1301

Figure 11: Sample and Hold Switch

3-75
Note: All typical values have been guaranteed by characterization ",d are not tested.

.~.

"

IIH502.~IiI'038

i
I

APPlJCATIONS:1~.)

!

r - .... - -,,- I

""'--,.211/

I

I

I

I

I

I
I
"lOI/nLGATE
"::"
'''::" J I
L:: ___ "' _____
AFOO1411

flgyre 12: Switching up to +20V $I9".alsYiith TTL

~ogic

r--;---:--':--:-'·"V
:

I"
l~;~

I

. I

TO

:

1'0K1!'
.-~:~~__________J

I

I

eSHIFT· l,O."1OMI
!

.

'";;oJi ~-'

.

~_I"

·

ONO

0,
0,

0,

o•

a~~,2 ~~4 •
SSOO'5Oi

~1401

SWITCH STATES ARE FOR
LOGIC "1" INPUT

I

".'~
.,

ss001201

DUAL DPST IH504S
(rOS(on) < 7SSl)

A

'0/

FLAT PACKAGE.FD-2)

DIP (DE) PACKAGE

OPOT IH5046
(roS(ON) < 7SSl)

,
"o, ",
o,
.. •
'N

v,

v'

Y,o

f·

v,

~

'",-

...,

-

" ......
.~'

GOO

0,

.,

0,

5,

3~DI
,

:.r-- !.o
•

D4

_J

5,

,

v'

f"
I

;-u

I

-v 0 '

"'-:.

II

·
,. · ......

.J..:

_t

b"
v'

o.

.~5

~:'
v'

y"

~J
.NO

88001801

0,

!..,., 03

r-o

D4

88001701

4PST IHS047
(ros (ON) < 7SSl)
v,

,
,
.." •

10 f.
~OI

5,

$,

IN

,4

u!'

5,

~O'l

4~D3,

......

.1

-v 0,

~-.

b"
GNO

,

y"

",

~.,

I

II

" •
o. •

'

1

5,

0,

:-u 0,

•

1

~D.

'foIo!! -Qi>-J

&"

!" !"

v'

ON.

85001801

V'

88001901

Figure 2: Switching. State Diagrams (Cont.),

:Hl2
Note: All typical values have been guaranteed by characterization .and ·are not tested.

TO-l00

i

IH5040~IH504 7
TYPICAL PERFORMANCE CHARACTERISTICS

40

160

I
I
,hv

100

I

'40
'20

+l~~C

10- ~

60

+25"C

+e

0
.,
-10 -5 -25' 0

~

.-1.·e i-= l.·'re

40

·20

S
R

L.-

+25~C

'00

I

25

!

r-- !--+-,12V

50

'15V

S

1? -75

t-+

-10-75

-5 -25

10

'"

0

lk

20

5

0
0

25

5

0
-10 -7.5 -5 -25

7510

I

I
I

',oon

,

L-=-

,

ov..JL ~_
~
SWITCHED
CHANNEL

VOUT

'- -

-

-

-

"

.~

2Vpp
@lMC

-l,oon

5H!'

10k lOOk 1M

OP005201
TCO05301

-12
01"

..
~

~

.

e
,.

-80

l'

1"-1-t--

-60

OFF STATE
~~_
OEPENOS ON PART~-

-40

-2 0

oTHz

~VOUT

l'Do!)

OIRR = 20LOG 2000mVpp
VOUT (mVpp)

TOHz 100Hz lk

2.5

5

7.S

10

OPOO5101

FREQUENCY (Hz)

-100

0

VANAlOG (V)

,

I

,

CCRR = 20LOG 2000mVpp
VOUT (mVpp)

100

~

." :

"'I--

0

10

25

z

~: ~-J¥
3V

1

30

~

>-

I

0

o

I-

g
>
.§.

OPQ05001

1"-",

100

I-""

VANALOG (V)

OPQQ4901

20

l...- ,...-

t5

20 ~ t -

VANALOG (V)

120

,

I

40

15V SUPPLIES

35

i

80

Is!1mA
•

CHARGE INJECTION vs VANALOG
(SEE FIG. B) CL = 10,OOOpF

rOS(on) vs POWER SUPPLY
VOLTAGE

rOS(on) vs VANALOG SIGNAL

80

(Per Channel)

10k lOOk 1M

FREQUENCY (Hz)
TCOO5401
QP005301

3-83
Note: All typical values have been guaranteed by characterization and are not tested.

~i

CIt

!

'*",

I!

~
.1

..

TYPICAL PERFORMANCE CHARACTERISTICS (CONT.)
POWER SlIPPLY QUIESCENT CURRENT
FREQlIENCY RATE

-

l/

/

,,- V
V

.,

V8

LOGIC

V

/

V

1/,

WFQ01601

...

,

LOGIC FREQUENCV@ tO"lo DUTV CYCLE IH~)

0P005401

TEST CIRCUITS

·Jj~-h1.,.

Vour

'tiff

·: rt . m
AlAUlllIIIPUT

AIA~IIPUT

'kO

iU)

OVn~_.
.

1IO.rQ-i>-_'

.

VOUT

'D.oao,F

TC035701

Figure 3

LOGIC IlPUT

~

.,. .,.

f.:~
1010

TC03580t

TC035901

Figure 4

Figure 5

NOTE 1: Some channels are turned on by high "1" logic inputs and other channels are turned on by low "0" inputs; however O.BV to 2.4V describes the min.
range for switching properly. Refer to logic diagrams to see absolute value of logic input required to produce "ON" or "OFF" state.

APPLICATIONS

ANALOG
INPUT

I.""

·3\1

~

> SAMPl E MOOE

ov • > HOLD MODE

AF005BOI

Figure 6: Improved Sample & Hold USing IH5043

3-84

Note: All typical values have been guaranteed by characterization and are' not tested.

IH5040-IH5047
APPLICATIONS (CO NT.)

lOGIC
STROI£

EXAMPLE: If -v ANALOG' -10VOCand +V ANALOG' +10VDC
then Ladder Legs are switched between, 1OVDC. depending upon lIal.
of lotIic Strobe.

JL
r'L
LOGIC
STROlE
2R

AFOO2101

Figure 7: Using the CMOS Switch to Drive an R/2R Ladder Network (2 Legs)

UIOldl

LOPASS
OUTPUT

Constant gain, constant Q. variat>te frequency filter which
provides simultaneous Lowpass. Bandpass, and H ighpass
outputs. With the component values shown, center frequency
will be 235Hz and 23.5Hz for high and low logic inputs
respecti.... ly. Q,. 100, and Gain'" 100.

fn .. Center Frequency'" _,_
21rRC
AFOO2201

Figure 8: Digitally Tuned Low Power Active Filter

3-85
Note: All typical values have been guaranteed by characterization and are not tested.

APPLICATION~

(CONT.)

T'L.r--t.
LOGIC

I
L~2:'~~T~

I
I
I
I
I

LOGIC'
INPUT

~-~6---k:"""--<> +15V

.". I

___ ...J

LCOo0501

Figure 9:. InterfaCing· with TTL Open Collector Logic
(Typ. Example for + 15V Case Shown)

y.
GND

IN

·~--O--4_-o 'VDD

15Y~ y . . . 6Y
IN .. Y- ...16V

LCOOO6OI

Figure 10: Interfacing with CMOS Logic

3-86
Note: All typical values have been guaranteed by characterization and are· hoi· tested. .

·IIIIIU~UI!.I

1H5040-1 H5047
APPLICATIONS (CONT.)
+5V

-..

IN

rrL~

I
I
I

LOGIC

J

~+

I

I

-

+5V

I
":"":" I

.

+ 15V OR + VCc(VI TERMINAL}

1

L~~L~~~ ___ ...J

100
lCOOO711

Figure 11: TTL Logic Interface

3-87
Note: All typical values have been guaranteed by characterization and are nOI tested.

Ii

IH5048~jH5051

I

GENERAL DESCRIPTION

FEATURES

The IH5048 family of analog switches is especiaUymade
,for low charge injection and low leakage. Construction
includes our CMOS high level driver circuitry combined wi~h
unique "VARAFEr' switches.

•
•
•
•
•.
•

I Low Charge Injection

I CMOS Analog Switches
Low· Charge Injection-6mV (Typ.)
Quiescent Current Less Than 1J.LA
TTL, DTL, CMOS, PMOS Compatible
Non-latching With Supply Turn-Off
Low rOS(on) - 3Sn (Typ.)
Pin-Out Compatible With IHS040 Family

.ORDERING INFORMATION
,!g

I

Package
DE -16-Pin Ceramic DIP
(Special Order Only)
FD·2 - l4-Pin Flatpak
JE - l6-Pin CERDIP
PE - l6-Pin Plastic DIP
TW - TO-l00 Metal can
(lHS048, IH5050 Only)
Temperature Range
.
M - Military (- SS"C to + l2S"C)
C - Commercial (O"C to + 70"C)
Basic Part Number

ORDERING INFORMATION
INTERSIL
PART NO.

IH5048 Dual
IHS049 Dual
IHS050
IHS051 Dual

TYPE

'OS(on)

SPST
DPST
SPOT
SPOT

3Sn
3Sn
3Sn
3Sn

NOTE 1. See Switching State diagrams for appHcable package equivalency.

SWITCH STATES ARE FOR
LOGIC '1" INPUT

FLAT PACKAGE (FD-2)

T0-1oo

DIP (DE) PACKAGE

DUAL SPST IH5048
(rDS (ON) < 3Sn)
v,

"

v,

v'
D,
I

'N, "

_J

"

v,

0,

",

-,

..

'N,

v'

'"
D,

0,

","

..

..

",

0,

GNO

.NO
ss00200/

SSOO2101

Figure 1: Switching State Diagrams

Note: All typical values have been guaranteed by characterizatiOri "and are! nortested.,·

v'

v'
$8002201

.D~OIl.

.IH5048-IH5051
SWITCH STATES ARE FOR
LOGIC '1" INPUT

FLAT PACKAGE (FD·2)

DIP (DE) PACKAGE

DUAL DPST IHS049
(rDS (ON) < 3SQ)

T00100

(DG184 EQUIVALENT)

"

v,

s,

D,
D,

S,

..... ,

D,
D,

D,

"
"

OJ

'"
'"

0,
0.

'."

GND

SSOO2301

SS002401

SPOT IHSOSO
(rDS (ON) < 3SQ)

'.

v,

v'

S,

D,

S,

D,
I

_J

v,

v'

"
"

·v·

D,

S,

D,

D,

S,

D,

"
GND

G'D

58002501

S8002601

DUAL SPOT IHSOS1
(rDS (ON) < 3SQ)

ss002701

(DG190 EQUIVALENT)

v.

v,

s,

S,
S,

D,
D,

S,

v'

D,
0,

'"

'N,

'"

D,
D,

D,
D,

GND
GND

ss002801

SS002901

Figure 1: Switching State Diagrams (Cont.)

3-89
Note: All typical values have been guaranteed by characterization and are not tested.

IH5048~IH5051
ABSOLUTE MAXIMUM RATINGS
Current (AnyTermi~al) ............... : .. , .............. < 30mA
Storage Temperature .. : ....... : ........... ..,S.5·C to 150·C
Operating Temperature ................•.. -55~C to + 125·C
Lead Temperature (Soldering. 10sec) ................. 300·C
Power. Dissipation ......................................... 450mW
(All Leads Soldered to a P.C. Board)
Derate SmW I·C Above 70·C

v+ -v- .. ; ....... '......................................... : ... .( 33V
vi' -vo ... :·.: ... : .............................................. < 30V
Vo-V- ........................................................ <30V
Vo-Vs ...................................................... < ±22V
VL-V- ........................................................ < 33V
VL -VIN ....................................................... < 30V
VL -GND ...................................................... < 20V
VIN-GND .................................................... < 20V

+

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
. absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(@ 25·C, V + =

+ 15V, V- = -15V, VL = + 5V)

PER OHANNEL

MINIMAX LIMITS
TEST CONDITIONS

SYMBOL

MILITARY

OHARACTERISTIC
-55·C

IIN(ON)
IIN(OFF}
r05(on)
Ar05(ON)
VANALOG
IO(OFF}'
IsioFFi
I~ON)
+ 5(00)

Ion

+ 125·C

±1

10
10
80

±t
±1

.±1
·40

IS· -10mA
VANALOG - -10V

0
±.1
±1

Vo-VS=-10Vto +tOV

+70·C

±1
±1

10
10
75

45

15
(Typ)
±10
VANALOG = -10V to + 10V

UNIT

+ 25·C

p.A
p.A

n

15
(Typ)
±10

n
V

. ±1

100

±5

100

nA

±2

200

±10

200

nA

'.

RL = lk!1, VANALOG - -.10V

500

1000

ns

to + 10V See Fig. 2

loft

Switch "OFF" Time

Q(lNJ.)
OIRR

Charge Injection
Min. Off Isolation
Rejection Ratio
V + Power Supply

1+ Q

IIIN ~ 2.4V Note t
VIN ~ O.SV Note 1

Input Logic Current
Input Logic Current
Drain·Source On
Resistance
Channel to Channel
rOS(ON) Match
Min. Analog Signal
Handling Capability
Switch OFF Leakage
Current
Switch On Leakage
Current
Switch "ON" Time

COMMERCIAL

+ 25·C

RL=lk!1, VANALOG= -10V
to + 10V See Fig. 2
Sea Fig. 3
f = 1MHz, RL = lOOn, CL S 5pF
Sea Fig. 4, (Note 1)

250

500

.ns

1 (Typ)

2 (Typ)

54
(Typ)

50
(Typ)

mV
dB

1

1

10

10

10

100

p.A

1

1

10

1

1

10

10

10.

100

p.A

10

10

100

p.A

1

10

10

10

100

I'A

Quiescent Current

1- Q
1- LQ

V+ = +'15V, V= -15V, VL= +5V
VL = +5V

V - Power Supply
Quiescent Current
+5V Supply
Quiescent Current

IGNO
CCRR

Gnd SUpply
Quiescent Current
Min. Channel to
Channel Cross
Coupling Rejection
Ratio

1
One Channel Off; Any Other
Channel Switchell as per
Periormance Characteristics (Note 1)

54
(Typ)

50
(Typ)

dB

Note 1: Not tested in production.

TEST CIRCUITS

r , rn
t--

ANALOG IfIIPUT

"'IOV

v1\~-J
~G"
h
INPuT

'

lOpF

J

VO\JT

"'NALOG INPUT

v..n. o---[)---t>--3K

COG'C
INPUT

1D--l>-_

LOGIC INPUT
( N0

1oooo .,F

loon

TC005111

TC005011

Figure 2

":"

~ VOUT

I

":,111,0

"='

5111

Figure 3

TC00411t

Figure 4

NOTE 1: Some channels are tumed on by high "1" logic inputs and other channels are turned on by low "0" inputs; however O.BV to 2.4V describes the min.
range for switching properly. Refer to logic diagrams to see absolute value of logic input required to produce "ON" or "OFF" state.

3-00
Note: All typical values have been guaranteed by characterization arid are not' jested.

.D~Dll

IH5048-IH5051
TYPICAL PERFORMANCE CHARACTERISTICS

(Per Channel)
CHARGE INJECTION vs VANALOG
(SEE FIG. 3) CL = 10,OOOpF

rOS(on) vs POWER SUPPLY
VOLTAGE

roS(on) vs VANALOG SIGNAL

160
100

140

3S

120

80

!

100

60

f

80
60

•

40

..,

0

+121"C

+2I·C

r- r-

.,.·c

0
-10 -5 -25'0

's·1mA
• 1 1SV SUPPLIES
2.5

5

~5

-75

0

T

0
-10 -7.5 -5 -25

10

0

0

25

"ANALOG IV)

100

CHANNEL

iii
<>
0:

~

I

o--f--D---t>--=I
r 1='
I
I
,
I

to-. to-.

I

60
3V

Ov...n..

40

20

o1

CCRR
10

= 2ULOG
100

2000mVpp
Your (mVpp)
lk 10k lOOk 1M

SWITCHED
CHANNEL

I

I
I

loon

L-=-

~.I

~--t~

.10

FREQUENCY (Hz)
TCOO5301

OP005201

-12

0"

-10o

!

-80

ii:"

e -6

0

-40

r-.
r"-"

""""''

0

2.5

5

7.5

10.

OPOO5101

VOU,

to-. "

80

c

>

-7.5· -5 -2.5

"ANALOG (VI

I

OFF

to-. to-.

..

-to

10

r-----7.h

120

;;;

7.5
OPO05021

0P004921

:!.

5

VANALOG IVI

OFF STATE
~
DEPENDS ON PART~-

~VOU'

1

-20

'00n

OIRR = 20LOS 2QOOmVpp
VourfmVDjii
0
1Hz 10Hz 100Hz lk 10k lOOk 1M

TC005401

FREQUENCY (Hz)
OPOO5301

3-91
Note: All typical values have been guarantliled by characterizalion and are not tested.

i

IH6048~IH5051

,

TYPICAL PERFORMANCE CHARACTERISTICS (CO~T;) .

I

. '.'

"IID~

POWER SUPPLY QUIESCENT CURRENTY81.0GIC
FREQUENCY RATE
,"
'000

1
i.-

Ii

i

!i:

j

V
v
/

'DO

/'

10

V'

/'

3V

V

V

V

10

100

1k

'OIl

WFOO1601

lOOk

LOGIC fREQUEN'tV@ 10"10 DUTY CYCLE 1Hz)

OPO05401

3-92
Note: All typical values have been guaranteed by characterization and are not'tested;

1"5052/IH5053

QUAD CMOS Analog Switch
GENERAL. DESCRIPTION

FEATURES

The IH5052/3 analog switches use an improved, high
voltage CMOS technology, which prbvides performance
advantages not previously available from solid state
switches. Early CMOS switches were destroyed when
power supplies were removed with an input signal present.
The INTERSIL CMOS technology has ·eliminated this serious systems problem. Key performance advantages are
TTL compatibility and ultra low-power operation - the quiescen.t current requirEjm~ntis less ,than 10pA. .
The IH5052/3 also guarantees Break-Before-Make
switching. This is accomplished by extending the tON time
(400ns TYP.) such that it exceeds tOFF time (200ns TYP.).
,This insures that an ON channel will be turned OFF before
an OFF channel can turn ON, and eliminates ,the need for
external logic required to avoid channel to channel shorting
during switching. With a logical "0" (0.8V or. less) at ,its
control inputs, the IH5052 switches are closed, while the
IH5053 switches are closed with -a logical "1" (2.4V or
. more) at its control inputs.

•
.•
•.
•
•
•
•
•

Switches Greater Than 20Vpp Signals With ± 15V
Supplies
Quiescent Current Less Than 101lA
Overvoltage Protection to f25V
Break-Before-Make Switching toff 100ns, ton
250ns Typical
TTL, CMOS Compatible
Non-~tchln.9, WIth Supply Turri-Off
.IH50524 Normally Clps,d Switches
IH5053 4 Normally Open Switches

ORDERING ,INFORMATION
IH505X , C

JE,

~

..
. .
~

.

Package

-'

.

JE c 16·Pin CERDIP
DE =·16-Pin 'Ceramic DIP
.
(Special Order Only)
Temperature Range
M - Military
C = Ccmmercial.

' - - - - - - - - Basic Part Number

OUTI,INE DWQS
. 'DE,JE
DUAL-IN-LlNE PACKAGE'
lOb

..
.

D.

D,

v'

ISU. .TIIATEI

II>

a.,TCH STATES AIIII
'0lIl LOQtC ..," tHlI!UT

...

D.

.
.

0;'

v'

VL

Dr

II>

lDOO1801
WF01060t

Figure 1: Functional Diagram

Figure 2: Pin Configurations

3-93
Note: All typical values have been guaranteed by characterization· and, are not tested.

.,,'

Current (Any Terminal) .................... : .• ~._.i.i..:.< 30mA
Storage Tell;lper/iJture ...................... -6S·Cto +1~0·C
Operating, Temperature ....•...........,... _5S·C to +.12S·C
Lead Temperature, (Soldering, 1Osec:) .......••... , ..•• 3!)0·C
Power DissiPation ........................................... 4S0mV'/
(All .Leads Soldered to ,a P.C.,Board)
DElrate 6mW I"C Above 10·C

V+ -V- ............................................ : .......... < 33V
V,+,-Vo •. "........ , •........•.. ,; ..•........•...... , ........... '< 30V
VrrV- •....................................................,... ,~' 30V
VrrVs ................ i ...... ';'; •. t ••••• :; ••• , . . . . . . . . . . . . . , •• ,., <: ±22V

~~=~~.::::::::::::::::::::::::'::::~::::::::,:::::::::::::::::::: ~'~~~

< 20V
,< 20V
Stres$8S above thos~ Iist9d und":' Absolute·M;b.irriuinFiatings 'iIl8Y cause perma~ent damage to the device. These are ~tress ratings"only, and functional
'operation of the device at these1lt'iany otherconditions"aboVethose illdicated in the operational 'sections of the speclficationS'lanet implied, Exposure to
VL-GND ...................................... ; ........ : ......
VIt~-GND ..........•............. ,',... 1 •• ' ......... " ...... '........

$

','

absolute maximum ratirig;,conliJllioA&'for exte'nded periods' may'affect device rellabi!ity.

ELECTRICAL CHARACTERISTICS

'

MINIMAX LIMITS

PER CHANNEL

MiLiTARY

TEST CONDITIONS
SYMBOL

,

(TA =2SoC, V + =+, 15V" V': - ":'1SV, VL -' +.5'.()

CHARACTEFilmC

-55°C

+ 25°C

IIN(ON)

Input Logic Current

VIN - 2.4V (IH5053) = 0.8V (IH5052)

,10

±1

IIN(OFF)

Input, Logic Current

VIN -P.8V (IH5053) - 2.4V (IH5052)

,10

'DS(ON)

Drain-Source On
ResistanCe

IS -lOrnA, Vanalog - -10V to + 10V

75

ArOS(ON)

Channel ,to Channel
'DS(ON) Match

+125°C

,.

,

,COMMERCIAL
0

+ 25°C ,,+70°C

lQ

±10

±1

10

flO

75

100

80

80

100

UNIT

fAA,
,iA'
ri

30
(typ)

.Il

(typ)

±11
(typ)

±10
(typ)

V

25

,

VANALOO

Min. Analog Signal
Handling Capability

IO(OFF) I
IS(OFF)

Switch OFF Leakage'
Current

'\lANALOG= -10V to +10V

±1

100

±5

100

nA

ID(ON)
+IS(ON)

Switch On Leakage
Current'
"

Vo-Vs· -10V to +10V

±2

200

±10,

100

nA

toN

Switch "ON" Time

"RL - lkn, Vanalcg - -10V to + 10V

500

jooo

ns

toFF

Switch "OFF"

250

500

ns

Q(INJ.)

Charge 'i'njection,

15

20
(typ)

mV

(typ)

54
(typ)

'50

dB

(typ)

, See, Fig. 3

TIme

Min, Off IsolatiOn
Rejection Ratio

OIRR
1+

+ Power Supply
Quiescent Current

1-

- Power Supply
Quiescent Current

RL.+lk.ll, VanaIcg- -10V to +10V

See~!"ig. 3

See/Fig. 4
I -lMHz; RL -lOOn, CL'; 5pF
See Fig, 5

V+ - + 15V, V- - -15V, VL= +5V

+5V Supply
Quiescent Current

CCRR

Min, Channel, to ,'Channel One Channel Off
Cross Coupling·· Rejection
RatiO

".

are

10

100

10

10

100

fAA

10

10

100

10

10

100

p.A

10

10

100

10

10,

100

fAA

with GND

IVL

NOTE 1: Typical values

10

54
(typ)

lor design aid only, not guaranteed and not subject to productiOn testing,

I

3-94
Note: All, typical values ha~ been guaranteed by characterization and are notlested,

50
(typ)

dB

IH5052/IH5053
TEST CIRCUITS

rhI ":'

ov.fl. -D-1>--

~
INPUT

VOUT

-D----D-1>--f
r
LOGIC
INPUT

.

.to

TTL
LOGIC INPUT

(NO~_

·

YOUT

"-I

,on

'Opf

m
1:-'

AJW.OG_T

ANALOQINPU'

'":'":"

,oon

TC006121

TCOO6011

TCOO5911

Figure 3

Figure 5

Figure 4

NOTE 1: The 5053 is turned on by high "1" logic inputs and the 5052 is turned on by low "0" inputs; however O.BV to 2.4V describes the min. range for
switching properly. Refer to logic diagrams to see absolute value of logic input required to produce "ON" or "OFF" state.

TYPICAL PERFORMANCE CHARACTERISTICS
ros(ON) vs VANALOG SIGNAL
'00

...

(Per Channel)

ros(ON) vs POWER SUPPLY
VOLTAGE

,.

,.

10

....

+'~·C

",10

·c

+

:::.

J!l

c ..

·Cf=

.

Is = 1111A
@:!:15VSUPP

•

-10 -7.5

-5 -2.5

0

2.5

5

-I.,

7.5

10

.,

I-- e -

....

.

1,..00

:ttl

•

-10 -7.5 -5

-2.5

a

2.5

CHARGE INJECTION vs VANALOG
(SEE Figure 8) CL = 10,OOOpF

4Sr-,..--r-....,..--,.--,-r-'T'""""

-

.. ~+-++-+-l-I-+-~
""r--+-+-+---1r--+-+-+---I

I-"""

5

....

1201-+-+-+-1I--+-+-+-l

1-0

J:t-+-+--+-t-+-+--+--i
,.t-+-+--+-t-+-+--+--i

7.5

': tt~t:t:f:ttj

t.

-'0 -7.5 -5 -2.5

OP005601

OPOO5501

r------.,
I

II

... ~

I

r-..i'o

..
•,

J

".....
TTLLEYELS
C R
,.

fTl

~NEL+D_t>_-I.!

!'or-..
'00

CHANNa.

=I*iOGlv=~':.1
100

tit

10k

,.

~
r.ITofiD

I

*

IiI ,_
I
L -

+cH>--

vour

-r'r-~-.

I

L-----=lJ

1000

111

2.5

I

7.5

to

0P005701

CROSS COUPLING REJECTION vs FREQUENCY

,..

0

VANALOG (II)

"ANALOG (V~

VANALOG (II)

'510

2V""

@1MHz

FREQUENCY (Hz)
OPO05BOI

TC00621 I

CrossCoupling Rejection
Test Circuit

3-95
Note: All typical values have been guaranteed by characterization and. a(Eil. not. tested.

I

1"5052/IH5053

I

TYPICAL PERFORMANCE CHARACTERISTICS (CONT.)

;:,

~

I
;

OFF ISOLATION vs FREQUENCY
-'10

""""
...
"
!
-'00

(

...

~

-40

IV",

@.IIC

'"

-10
OIRR '" 2OLOG

o
1Hz

.UI

.....

v:un::)

10Hz 100Ha tic

,.

,.

,.
TC006301

_auINCY (Hz)
0P005901

Off Isolation Test Circuit
POWER SUPPLY QUIESCENT CURRENT vs LOGIC
FREQUENCY RATE

i''''
,.:

/~

,.~

·
,

too

I~

3.

·
!
•

i!.

~

I

to

a
w

I"

/

§

.1

"

WF001711

101

tic

,.

100II

LOGIC FMOUiNCY @ . . . DUTY CYCLI (Hz)
OPO06001

Logic Input Waveform

r-------~-, ·t5V

I
I
I

....,

(11111 TO

_II)

I

I

IN

I

I
II

V"'"

__

+11V

L..;
__
__
_ _ _ ...... _'--',
'11V
TTL
GATE

LCOOO91 I

Figure 6: + 15V Open Collector TTL Interface to IH5052/5053

r

3-96

Note: All typical values have been guaranteed by characterization and are not tested.

.D~OI1. i

IH5052/IH5053

I

APPLICATIONS

N

PROGRAMMABLE GAIN NON-INVERTING AMPLIFIER WITH SELECTABLE INPUTS

i

!eft
W

.... o--.t---.......

.... -..t---....,""--H
CM,

.... -;;t---.....-r
C'"

.... ---.+---..,...,

u.

C...

.." "

101kU

'101,
'101'
.S!I
AFOO2301

Figure 7: Active Low Pass Filter with Digitally Selected Break Frequency

..

ANALOG IWITCM

OECODUI

VIN'

MUX

SEOUENCE
RATE

VIN2

Do

..

RESET

.~,

D,
VIN4

D,

DUAL

,,-K FLIP ,LOP

I INPUT NAND
Poe'Ia'LlTIEI
TTL - 1 11S IN5410

I'QU'BILlT...
TTL· SNI473
CIIOI - C04027
ENABLE

OUT

CMOS - 1 1/3 CD4023

0----------'
AF002401

TRUTH TABLE (IH5052)
ENABLE

MUX
SEQUENCE
RATE

0
1
1
1
1
1

0
0
1 pulse
2 pulses
3 pulses
4 pulses

SEQUENCER
OUTPUT

SWITCH STATES
(- DENOTES OFF)

2°

21

SW1

SW2

SW3

SW4

0
0
1
0
1
0

0
0
0
1
1
0

ON
-

ON
-

-

-ON

-

ON

Figure 8: 4-Channel Sequencing MUX

3-97
Note: All typical values have been guaranteed by characterization and are not tested.

-

-

,: IM'505211H5053

I

-

:::. A LATCHING DPDT SWITCH
~

I

The latch feature insures positiye switching action in
response to non-repetitive or erratic' commands. The A1
and A2 inputs are normally low. A HIGH input to A2 turns 81
. and $2 ON, a HIGH to A1 turns S3 al)d S4 ON. Desiral:!le for
use with limit detectors, peak detectors, or mechanicalcontact closures.
,

TRUTH TABLE (IHSOS2)
~15V

COMMAND

-sv
So
A,

A2

A1

53 & 54

51 & 52

0
0

0

same
on

same

1
1

A,

OUAO 2 INPUT
NAND GATES

TTL -01l74C1O

OR OM_

.r

STATE OF SWITCHES
AFTER COMMAND

cllas . CD4011

DM74COO

.
AFOO2501

Figure 9: A latching DPOT

3-98
Note: All typical values have been guaranteed by characterization and are not tested.

1
0
1

off
off
on
INDETERMINATE

IH5108
8-Channel Fault Protected
CMOS Analog Multiplexer
GENERAL DESCRIPTION

FEATURES

. The IHS108 is a dielectrically isolated CMOS monolithic
analog multiplexer, designed as a plug-in replacement for
the HIS08A and similar devices, but adds fault protection to
the standard performance. A unique serial MOSFET switch
ensures that an OFF channel will remain OFF when the
input exceeds the supply rails by up to ±2SV, even with the
supply voltage at zero. Further, an ON channel will be
limited to a· throughput of about 1.SV less than the supply
rails, thus affording protection to any following.circuitry such
as op amps, DI A converters, etc.
A binary 3-bit address code together with the ENable
input allows selection of anyone channel, or none at all.
These 4 inputs are all TTL compatible for easy logic
interface; the ENable input also facilitates MUX expansion
and cascading .

•
•
•
•
•
•
•
•

All Channels OFF When Power OFF, for Analog
Signals up to ±2SV
Power Supply Quiescent Current Less Than 1mA
± 13V Analog Signal Range
No SCR LatchliP
Break-Before-Make Switching
Pin Compatible With HI-SOBA
Any Channel Turns OFF If Input Exceeds Supply
Ralls by Up to ± 2SV
TTL and CMOS Compatible Binary Address and
ENable Inputs

.ORDERING INFORMATION
PART NUMBER
IH510BMJE
IH510BIJE,
IH510BCPE

TEMPERATURE RANGE
-55°C to + 125°C
-20°C to +B5°C
O°C to 70°C

PACKAGE
16 pin CERDIP
16 pin CERDIP
16 pin plastic DIP

DECODE TRUTH TABLE

YouT D

A2
X
0
0
0
0

A1
X
0
0

1

1

0
0

1
1

1
1

1
1

Ao
X
0
1
0
1

0
1
0
1

EN
0
1
1
1
1
1
1
1
1

ON SWITCH
NONE
1
2
3
4
5
6
7
B

AO, AI, A2. EN
Logic "1" = VAH::: 2.4V
Logic "0" = VAL ~ O.BV
(outline dwg JE. PEl

Ao

A;

A2

EN (ENABLE INPUT)

3 LINE BINARY ADDRESS INPUTS
(1 0 11 AND EN HI
.
ABOVE EXAMPLE SHOWS CHANNEL. TURNED ON

LOO01901

Figure 1: Functional Diagram

TOPVJEW
CDOO4401

Figure 2: Pin Configuration

3-99
Note: All typical values have been guaranteed by characterization and are not tested.

I .1'11108
,,';;
I A8~OuiTE 'MAXI'M'U~ RATINGS ,.

"

Current (Any Terminal) ....... :;': .................. ~ ....... 20mA
Operating Temperature ......................... -55 to 125·C
Storage Temperature .... ; i-r, ........ ; ......:.... -65 10, .150·C
Lead Temperature (Solderirig, 10sec) .....• ; ........:.• ~OO·C
...................
:'.........; ...
~ .• , .';" f200mW
. POwer Dissipation*
.
'
:::
. ',':

VIN(A, EN) ................................... V- to (V+ -0.05)
VIN(A, EN) to Ground ........................... -15V to 15V
Vs or Vo to V+ ................................ ,. +2SV, '-40V
Vs or Vo ~o V- ...•............. ; ................. -25V, +40V
V+ to Ground ....•................... ~ ....... : ......... : ........ 16V
V- to. Ground •...............•.........................•..... -16V

,

"

"

• All leads soldered or welded 10 PC board: Derale 10tnWI"C above.70·C:

Stresses above Ihoselisled under Absolute Maximum flatings may cause permanenl dama~e 10 Ihe device. These are streSs riltings' only: and l~nctiOnal
operation of Ihe device al lhese or any other conditiOris above Ihose iridicaled in Ihe operational sections· of the specificatioils is' nOI implied: Exposure 10
absolute maximum raling conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(V of; ,= 15V, V- = -15V, VEN = 2.i4V. unless otherwise specified.)
MAX LIMITS

NO
CHARACTERISTIC

MEASURED
TERMINAL

TESTS

. TYP
2$'C

TEST CONDmONS

PER
TEMP

M SUFFIX

CSUFFIX

-55'C

25'C

125'C

~20'CI
G'C

UNIT

25'C

85'CI

-

7O'C

SWITCH
rOS(on)

StoD

8

VO-l0V,
IS--l.0mA

Sequence each
swnch on

700

1000

1000

1500

1200

1200

1800

8

Vo- -10V
IS· -1.0mA

VAL =0,8V,
VAH=2.4V'

500 .

1000

1000

1500

1200

1200

1800

~OS(on)~

'''05(On)

roS(on)max-i'D5(on)min

..,'S'!;.

S

%

rOS(on)avg.
VS-±10V

1S(0II) .

10(011)

S

P

,
10(on)

'0

a..

VS-l0V, VO- -lOY

0,02

iO.S

50

itO

8

VS· -10V, VO= 10V

0,02

iO.5

50

il.0

50

1

VO- 10V, Vs = -IOV

0,02

il.0

100

100

1

VO· -tOV, VS" 10V

O.OS

itO

100

i2.0
±2,0

8

VS(IIIQ = Vo = 10V

Sequence eaCh
switch on

0,1

±2,0

100

i5

100

8

VS(AIQ=VO= -10V

VAL -0.8V,
VAH=2,4V,
VEN=2.4V

0,1

i2,0

100

' i5

100

VEN=0.8V

50
nA

tOO

FAULT
IS with
Power OFF

S

6

VSUpp = OV, VIN - ±2SV,
VEN=VO=OV, Ag, AI, A2=OV

t.O

2.0

5,0

IIS(0ff) with
Ov9fV01lage

S

8

VIN = ±25V, VO· il0V

1.0

5.0

10

AO, At, A21
or,
EN

4

pA

INPUT
IEN(on) IA(on)
or
IEN(Off} IAIOff}
DYNAMIC

I

I

VA =2.4V or OV

0,01

I

I

itO

0.01

it,O
1

ttransition

0

See Figure 3

0.3

IoDen

0

See Figure 4

0.2

IonIEN)

0

See Figure 5

0.6

1,5

ioff(EN)
Ion'foff Break·
Before-Make
Delay Settling
TIme

0

0.4

'I

"OFF" IsolatiOn

D

Cs(oII)

S

VS·O

Coloff}
C05(off}

0

Vo-O

VEN= OV,
I-140kHz

VS-O, Vo=O

to 1 MHz

0

o.to S

I

I

-30

-10

I

-30

,

VA=I5VorOV

8

VEN -

+ SV, Ag, At, A2 Strobed
VIN - ± IOV, Figure 6

VEN-O, RL -200n, CL=3pF, VS-3 YAMS,
f= 500kHz

30

to

I

pA

30

/JS

to

60

dB

5
25
1

pF

3-100
Note: All typical values have been guaranteed by characterization· and are not tested.

,

IH5108
CHARACTERISTIC

MAX UMITS

NO
TESTS
PER
TEMP

MEASURED
TERMINAL

M SUFFIX

TYP
25'C

TEST CONDITIONS

- 55'C

J I
25'C

C SUFFIX

- 2Q'CI

125'C

D'C

I I
25'C

UNIT

85'CI
7O'C

SUPPLY
Supply

1+

Current

I-

1

I

VEN

I

1

~5V

I

All VADD =OV/5V

0.5

0.7

I

0.6

I

0.5

0.02

0.7

I

0.6

I

0.5

I

I

1.0

I

I

1.0

I

Note 1. Readings taken 400rns after the overvoltage occurs.

SWITCHING TIME TEST CIRCUITS
+11SY

V.
tr<100na

V+

"<

~1OV

lOOns

YOUT

Va1:;1; +10V

lISa = -10V
:a:10V
PROBE

-15V

~_""_..._:_:T':.:
..

-

-:t:o

Vour
VS1I= -10V

lISa = +10V

Cp
PROBE IMPEDANCE

~:=
WFOO1801

TC006701

Figure 3: ttransition Switching Test Circuit and Waveforms

+ISV

VOUT ---'¥"'s1'-=_--'fII::..:..._ _ _ _ _ _ _~_
II, ON

SoON

~%

V.

-I tape. 1-

-II... 1WFOO1901

TCOO6801

Figure 4: t open (Break-Before-Make) Switching Test Circuit and Waveforms

+15V

3V

VE.

A2r--'--}-'4>----1-Q VOUT
35pF

WFOO2001
TC006901

Figure 5: ton and toff Switching Test Circuit and Waveforms

3-101
Nole: All typical values have been guaranleed by characterizalion and are nol lesled.

rnA

"~

IMa.s:

It»

!

'SWITCHING TIME TEST CIRCUITS (CaNT.)

lao .ncl1oH OF LOGIC
INPUT s10fta

,

+3V

,

Ao.A,.A•
I-- 4oO-L.I _ _ _S:;EO=.UENCEO

.;;,OV;...._ _...

,I:'

,:

I I

BREAK.BEFORE
MAKEOELAV-V-

II

INPUT

~I '-+1OV

V

:

=-------T----~------

~

BREAK·BEFORE
MAKEOELAV-

IOKn

,
-

-

OV

W

INPUT
--IOV
WFOO2101

TCOO7001

Figure 6: Break-Before-Make Delay Test Circuit and Waveforms
Within the normal analog signal range, the inherent
variation of switch ON resistance will balance out almost as
well as the customary' parallel configuration, but as the
analog signal approaches either supply rail, even for an ON
channel, either the p- or the n-channel will become a source
follower, disconnecting the charmel (Figure 8). Thus protection is provided for any input or output channel against
overvoltage, even in the absence of multiplexer supply
voltages. This applies up to the breakdown voltage of the
respective switches. Figure 9 shows a more de~ailed
schematic of the channel switches, including the back-gate
driver devices which ensure, optimum channel ON resistances and breakdown voltage under the various conditions.

DETAILED DESCRIPTION
The IH5108, like allintersil's multiplexers, contains a set
of CMOS switches that form the channels, and driver and
decoder circuitry to control which channel turns ON, if any.
In addition, the IH5108 contains an internal regulator which
provides a fully TTL compatible ENable input that is
identical in operation to the Address inputs. This does away
with the special conditions that many multiplexer enable
, inputs require for proper'logic swings. The identical circuit
conditions of the ENable and Address lines also helps
ensure the extension of break-before-make switching to
wider multiplexer systems (see applications section).
Another, and more important difference lies in the
switching channel. Previous devices have used parallel nand p-channel MOSFET switches. While this scheme yields
reasonably good ON resistance characteristics and allows
the switching of rail-to-rail input signals; it also has a number
of drawbacks. The sources and drains of the switch
transistors will conduct to the substrate if the input goes
outside the supply rails, and ,even careful use of diodes
cannot avoid channel-to-output and channel-to-channel
coupling in ca!;es of input overrange. The IH5108 uses a
novel series arrangement of the p- and n-channel switches
(Figure 7) combined with a dielectrically isolated process to
eliminate these problems.
'
-15V

+15V

+25YFORCED

-av
OVERVOLTAGE

S

D

S

N-CHAHNELMOSFET-r/JD

ISTURNEDON
BECAUSE Va _ + 25Y

'.CHANNEL

":"

Q

ON.COMMON
OUTPI,IT
LlNEIY

03

Qa

S

Q

TD'"

..l.
':"

EXtE,RNAL

CIRCU1TRY

N-CHANNEL
M08FET IS OFF

MO$FET IS OFF

08001901

(a) OVERVOLTAGE WITH MUX POWER OFF

-l-ll1~
'I-: -~-: ~

-1IV

OVERVOLTl:V
/,

_INPUT~OUTPUT
l~ l~ l~ _
I I T

N-CHANNEL MOSFET
TURNED ON
BECAUSEVoa_ +1OY

as

+--__+-~---="'_.:I

~C~:C:~~AY

, M O S F E T IS OFF
-15VFAOM +15VFROM P.CHANNEL
DRIVERS
DRIVERS MOSFET IS OFF
08002001

(b) OVERVOLTAGE WITH MUX POWER ON

Figure 8: Overvoltage Protection

-15VFROM +15YfROM

DRIVER

DRIVER
08001801

Under some circumstances, if the logic inputs are present
but the multiplexer supplies are not, the circuit will use the
logic inputs as a sort of phantom supply; this could result in
an output up to that logic level. To prevent this from

Figure 7: Series Connection of Channel
Switches

3-102
Note: All typical values have been guaranteed by characterization and are not tested.

IH5108
DETAILED DESCRIPTION (CONT.)
occurring, simply ensure that the ENable pin is LOW any
time the multiplexer supply voltages are missing (Figure 10).
lOOpF

s

08002201

Figure 10: Protection Against Logic Input

MAXIMUM SIGNAL HANDLING
CAPABILITY
The IH510B is designed to handle signals in the ±10V
range, with a typical rOS(on) of 600n; it can successfully
handle signals up to ± 13V, however, rOS(on) will increase to
about 1.Bkn. Beyond ± 13V the device approaches an open
circuit, and thus ±12V is about the practical limit, see Figure
11 .

• '5V

Figure 12 shows the input/output characteristics of an
ON channel, illustrating the inherent limiting action of the
series switch connection (see Detailed Description), while
Figure 13 gives the ON resistance variation with temperature.

0500210)

Figure 9: Detailed Channel Switch Schematic

..

..

t

21<0
"OFf" BEYOND
TIllS VOLTAGE

1.51(0

lK1l

3-103
Note: All typical .values have been guaranteed by characterization and are not tested.

co
....010 IH5i08

is

+1IouT
1.
14
12
10

IIouT

•

VIN

-4

-I
-I
-10
-12
-14

-18
-VOUT
SCOOO201

Figure 12: MUX Output Voltage vs Input Voltage (Channel

Shown; All Channels Similar)

10000

8CIOII

300!1
2OO!l
100II

-SSOC

-25°C

7SOC

125°C

TEMPERATURE
sc000301

Figure 13: Typical rDS(on) Variation With Temperature

3-104
Note: All typical values have been guaranteed by characterization and are not tested.

IH5108
USING THE IH5108 WITH SUPPLIES
OTHER THAN ± 15V
The IH51 08 will operate successfully with supply voltages
from ±5V to ±15V, however rOS(on) increases as supply
voltage decreases, as shown in Figure 14. Leakage currents, on the other hand, decrease with a lowering of supply
voltage, and therefore the error term product of rOS(on) and
leakage current remains reasonably constant. r05(on) also
decreases as signal levels decrease. For high system
accuracy [acceptable levels of rOS(on)] the maximum input
signal should be 3V less than the supply voltages. The logic
levels remain TTL compatible.

FOR

~
s2VSlGNAL5

+lOVSlGNAL
-IOVSlGNAL

APPLICATION NOTES
Further information may be found in:
A003 "Understanding and Applying the Analog Switch,"
by Dave Fullagar
A006 "A New CMOS Analog Gate Technology," by Dave
Fullagar
A020 "A Cookbook Approach to High Speed Data
Acquisition and Microprocessor Interfacing," by Ed
Slieger

zSV

slOV

:t:1SV
SC0Q0401

Figure 14: Typical rDS(on) Variation With
Supply Voltages

IH5108 APPLICATIONS INFORMATION
DECODE TRUTH TABLE
+1&V

-1&V

EN

1-

":'

At
A,

So

5,

+1&V

-15V

At

\'ouT

At

mOR
CMOS
INVERTER

":'

IHI10I

EN

s,.

So

A3

A2

A1

Ao

ON SWITCH

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1

51
52
53
S4
55
56
57

0
1

58
59
S10
511
512
513
514
515
516

AFOO2601

Figure 15: 1 of 16 Channel Multiplexer Using Two IH5108s. Overvoltage Protection Is Maintained
Between All Channels, As Is Break-Before-Make Switching.

3-105
Note: All typical values have been guaranteed by characterization and are not tested.

I
is

1..5108
IH5108 APPLICATIONS INFORMATION (CONT.)
~

T

TTUCMOS INVERTER

:::L>-

Ao

TTUCIIOS NOR GATE

......

IHllOI
10UTOFa
MUX

A.

I

.......

...

I!tI

I

-

I!
•

IH6108

.OUTOFa
MUX

1~

-

'I

•

ANALOG INPUTS

n
J.

'-1
1

IN.

rD-r>i

. . ANALOG INPUTS U

J"

A3

A2

A1

AO

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

(}

0
0
0
1
1
1
1

Jv

AF002701

DECODE TRUTH TABLE

DECODE TRUTH TABLE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0,

S.

i

A4

O.

r--<

....0

.L

J.

>--OVaUT

s!..,.

• OUT OF a
I MUX

'-----ii"

02,

IH5053

IH5101

~

f-D-t>-l
S.

~

~

~

J>'

.~

EN

I

Ih

1

ANALOG INPUTS ..

~
~
I

s.

IN.

IHllOI
10000Fa
MUX

EN

1'17

n
!!!!

~

4...

I

1

j

1 ANALOG INPUTS •

I:

+r

VL

ON SWITCH
81
82
83
84
85
86
87
88
89
810
811
812
813
814
815
816

A4

A3

A2

A1

Ao

ON SWITCH

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
'0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

817
818
819
820
821
5,22
823
824
825
826
827
828
829
830
831
832

Figure 16: 1 Of 32 Multiplexer Using 4 IH5108s and An IH5053 As A Submultlplexer. Note That The
IH5053 Is Protected AgalnstOvervoltages By The IH5108s. Submultiplexlng Reduces
Output Leakage arid Capacitance.

3-106
Note: All typical values have been guaranteed by characterization and are not tested.

IH5116
16-Channel Fault Protec• •
CMOS Analog Multi
GENERAL DESCRIPTION

FEATURES

The IHS116 is a dielectrically
monolithic
analog multiplexer, designed as a plug-in replacement for
the HIS06A and similar devices, but adding fault protection
to the standard performance. A unique serial MOSFET
switch ensures that an OFF channel will remain OFF when
the input exceeds the supply rails by up to ±2SV, even with
the supply voltage at zero. Further, an ON channel will be
limited to a throughput of about 1.SV less than the supply
rails, thus affording protection to any following circuitry such
as op amps, D/A converters, etc. Cross talk onto "good"
channels is also prevented.
A binary 2-bit address code together with the ENable
input allows selection of any channel pair or none at all.
These 3 inputs are all TTL compatible for easy logic
interface. The ENable input also facilitates MUX expansion
and cascading.

•

ORDERING INFORMATION

DECODE TRUTH TABLE

isolat~~r~MOS

PART
NUMBER

TEMPERATURE
RANGE

•
•
•
•
•
•
•
•

PACKAGE

IH5116MJI

-S5°C to + 125°C

28 pin CERDIP

IH5116CJI

O°C to + 70°C

28 pin CERDIP

IH5116CPI

O°C to + 70°C

28 pin Plastic
DIP

'Ceramic package available as special order only
(IHS116MDI/CDI)

All Channels OFF When Power OFF, for Analog
Signals Up to ±25V
Power Supply Quiescent Current Less Than 1mA
±13V Analog Signal Range
No SCR Latchup
Break-Before-Make Switching
TTL and CMOS Compatible Strobe Control
Pin Compatible With HI506A
Any Channel Turns OFF If Input Exceeds Supply
Rails By Up to ±25V
TTL and CMOS Compatible Binary Address and
ENable Inputs

A3

Az

A1

Ao

EN

ON SWITCH

X
0
0
0
0
0
0
0
0

X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

X
0
1
0
1
0
1
0
1
0

0

NONE

1
1
1

1
1

1
1
1

CD031311

Figure 1: Pin Configuration
(Outline dwg JE, PEl

3-107
Note: All typical values have been guaranteed by characterization and are not tested.

1

1

2
3
4
5
6

1
1
1
1
1

1

1
1
1

0
1
0
1
0
1

1
1
1
1
1
1

Logic "1" = VAH 2: 2.4V VENH 2: 2.4V
Logic "0" =' VAL $ 0.8V

TOPYIEW
Y" COMMON TO SUBSTRATE

1

7
8
9

10
11
12
13
14
15
16

!

1ft

1"5110
.\ ,

Z
~
s,~

s.~

s. 0--:---;.
s.~
s.~
s.~
s,~
s,~

VOUT
D

S,C>---+-

S'O~
s,'~

$,,0----'<

s,. o-:----:"'i
s.. ~
s.. ~
S.. ~
TO OEtODE LOGIC
COIiTROlLlIG 10TH
TlElIS OF MUXIfIG

4 LIIIE IIIAR' AOOIIESS IlPUTS
(OGOI) AIIO II • 5V
ABOVE ElWIPlE SHOWS CHAIIIElS I TURNEO 01.
LD011311

Figure 2: Functional Diagram

+15V
+3.0V
VA+~

VOUT
.~~~,

VA

0

O.9~~

~........~~~---r~VO~
35pF

WK'· ;iL.'
open

-t-

-

open

I

Vs
WF00301t

TC038501

Figure 3: t open

(Bre~k·Before-Make)

3-108
Note: All typical values have been guaranteed by characterization and are not tested.

Switching Test

ien

IH5116

......
G»

ABSOLUTE MAXIMUM RATINGS
VIN (A, EN) to Ground ....................... -15V to + 15V
Vs or VD to V+ ............................... +25V to -40V
Vs or VD to V- ................................ -25V to + 40Y

Current (Any Terminal) .................................... 20mA
Operating Temperature ..... :................. -55 to +~25~C
Storage Temperature .......... : .............. -65 to + 150·C
Lead Temperature (Soldering, 10sec) ................. 300·C
Power Dissipation· ...................................... 1200mW

V+ to Ground ................................................. 16V
V- to Ground ................................................ -16V

'Allieads soldered or welded to PC board. Derate 10mW/·C above 70·C.

8tresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (v+
CHARACTERISTIC

= 15V, v- = -15V, VEN = 2.4V, unless otherwise specified.)
MAX LIMITS

NO
MEASURED TESTS
TERMINAL
PER
TEMP

TYP
25·C

TEST CONDITIONS

M SUFFIX

C SUFFIX

UNIT

-55·C

25·C

125·C

G·C

25·C

7G·C

SWITCH
8 to D

ROS(on)

16

VO-l0V,
IS - -1.0mA

Sequence each
switch on

700

1000

1000

1500

1200

1200

lBOO

16

VO= -10V
IS = -1.0mA

VAL = O.BV,
VAH = 2.4V

500

1000

1000

1500

1200

1200

1BOO

LlROS(on)

LlROS(on) -

ROS(on)max""ROS(on)min

5

n

%

ROS(on)avg.
VS=±10V

8

IS(oft)

D

IO(oft)

D

10(on)

16

Vs -10V,
VO- -10V

0.02

±0.5

50

±1.0

50

16

Vs - -10V,
VO= 10V

0.02

±0.5

50

±1.0

50

1

Vo - 10V,
Vs = -10V

0.05

±1.0

100

±2.0

100

0.05

±1.0

100

±2.0

100

0.1

±2.0

100

±4.0

100

100

:1:4.0

100

VEN

= O.BV

1

Vo = -10V,VS = 10V

16

VS(AII) = Vo = 10V

16

VS(AII) = Vo = -10V VAL = O.BV,
VAH = 2.4V

0.1

±2.0

VSUPP = OV, Y,N - ±25V,
VEN = Vo = OV, Ao, A1, A2 = OV or 5V

1.0

2.0

5.0

1.0

2.0

5.0

0.01

-10

-30

-10

-30

O.ot

10

30

10

30

Sequence each
switch on

nA

FAULT
IS with
Power OFF

8

16

IS(off) with
Overvoltage

8

16

A1,
A2, A3
or
EN

4

Y,N = ±25V, Vo

= ±10V

IIA

INPUT
IEN(on) IA(on)
or
IEN(oft) IA(oft)
DYNAMIC

Ao,

VA

4

= 2.4V

or OV

VA = 15V

ttransition

D

0.3

Iopen

D

0.2

Ion(EN)

D

0.6

1.5

toff(EN)

D

0.4

1

Ion-loft BreakBefore-Make
Delay 8ettling
Time

D

"OFF"
Isolation

D

c,,(off)

8

Vs-O

D

Vo=O

CO(off)

16

D to S

COSLoff)
SUPPLY
Supply

I+ I

1+

Current

I- I

I-

Vs

I

IIA

1
ps

VEN - +5V, AD, A" A2 8trobed
Y,N = ±10V.

25

ns

VEN = 0, RL - 2oon, CL - 3pF,
Vs = 3VRM8, f = 500kHz

60

dB

= 0,

Vo = 0

VEN-OV,

5

f= 140kHz

25

to 1 MHz

1

1

I

All VA-OV/5V

0.5

I

I

VEN= 5V

0.02

pF

I

0.6

I

0.6

3-109
Note: All typical values have been guaranteed by characterization and are not tested.

I

I

1.0

I

I

1.0

I

rnA

!z High-Level
IM5140~I'H5145

Family

..

&
... CMOS Analog Switch
10

:!: GENERAL DESCRIPTION

FEATURES

ThelH5140Family of CMOS monolithic switches utilizes
Intersil's latch-free junction isolated processing to build the
fastest switches currently available. These switches can be
toggled at a rate of greater than 1MHz with super fast ton
times (80ns typical) and faster toft times (50ns typical),
guaranteeing break before make switching. This family of
switches combines the speed of the hybrid FET DG 180
family with the reliability and low power consumption of a
monolithic CMOS' construction.
OFF leakages are guaranteed to be less than 200pA at
25°C. Very low quiescent power is dissipated in either the
ON or the OFF state of the switch. Maximum power supply
current is 1pA from any supply and typical quiescent
currents are in the 10nA range which makes these devices
ideal for portable equipment and military applications.
The IH5140 Family is completely compatible with TTL
(5V) logic, TTL open collector logic and CMOS logic. It is pin
compatible with Intersil's IH5040 family and part of the
DG180/190 family as shown in the switching state diagrams.

• . Super Fast Break-Before-Make Switching
• ton 80ns Typ. toft SOns Typ (SPST SWitches)
• Power Supply Currents. Less Than l.pA
• OFF Leakages Less Than 100pA @ 25°C
Guaranteed
• Non-latching With Supply Turn-off
• Single Monolithic CMOS Chip
• Plug-in Replacements for IH5040 Family and Part
of the DG180 Family to Upgrade Speed and
Leakage
• Greater Than 1MHz Toggle Rate
• Switches Greater Than 20Vp-p Signals With ±15V
Supplies
• TTL. CMOS Direct Compatibility

ORDERING .INFORMATION
Order
Function
Part Number
IHSI40
IHSI40
IHS140
IHSI40

MJE
CJE
CPE
MFD

SPST
SPST
SPST
SPST

IHS141
IHS141
IHS141
IHS141
IHS141
IHS141

MJE
CJE
CPE
MFD
CTW
MTW

Dual
Dual
Dual
Dual
Dual
Dual

IHS142
IHS142
'IHSI42
IHS142
IHS142
IHS142

MJE
CJE
CPE
MFD
CTW
MTW

IHS143
IHS143
IHS143
IHS143

Package
CEADIP
CEADIP
Plastic DIP
Flat Pack

-SS'C
O'C to
O'C to
-SS'C

to 12S'C
70'C
70'C
to 12S'C

16 Pin CEADIP
16 Pin CEADIP
16 Pin Plastic DIP
14 Pin Flat Pack
TD·l00
TO·l00

- SS'C
O'C to
O'C to
-SS'C
O'C to
- SS'C

to 12S'C
70'C
70'C
to 12S'C
70'C
to 12S'C

SPOT
SPOT
SPOT
SPOT
SPOT
SPOT

16 Pin CEADIP
16 Pin CEADIP
16 Pin Plastic DIP
14 Pin Flat Pack
TO·l00
TO·l00

-SS'C
O'C to
O'C to
- SS'C
O'C to
- SS'C

to 12S'C
70'C
70'C
to 12S'C
70'C
to 12S'C

MJE
CJE
CPE
MFD

Dual SPOT
Dual SPOT
Dual SPOT
dual SPOT

16
16
16
14

-SS'C
O'C to
O'C to
- SS'C

to 12S'C
70'C
70'C
to 12S'C

IHSI44
IHSI44
IHSI44
IHSI44
IHS144
IHS144

MJE
CJE
CPE
MFD
CTW
MTW

DPST
DPST
DPST
DPST
DPST
DPST

16 Pin CEADIP
16 Pin CEADIP
16 Pin Plastic DIP
14 Pin Flat Pack
TO·l00
TO·l00

- SS'C to 12S'C
O'C to 70'C
O'C to 70'C
- SS'C to 12S'C
O'C to 70'C
- SS'C to 12S'C

IHS14S
IHS14S
IHS14S
IHS14S

MJE
CJE
CPE
MFD

Dual
Dual
Dual
Dual

16
16
16
14

- SS'C to 12S'C
O'C to 70'C
O'C to 70'C
- SS'C to 12S'C

Note:

16
16
16
14
SPST
SPST
SPST
SPST
SPST
SPST

DPST
DPST
DPST
DPST

Pin
Pin
Pin
Pin

Temperature
Range

Pin
Pin
Pin
Pin

Pin
Pin
Pin
Pin

CEADIP
CEADIP
Plastic DIP
Flat Pack

CERDIP
CERDIP
Plastic DIP
Flat Pack

'000

I~T O>-'\/IIIr......."Io--...,

lOOO2001

Figure 1: Functional Diagram Typical Driver!
Gate - IH5142

1. Ceramic (Side braze) d9V1C9S also available; consult factory. .
2. MIL temp range parts also available with MIL-STD-883 proCessing.

3-110
Note: All typical values have been guaranteed by characterization and are not tested ..

IH5140-IH5145
ABSOLUTE MAXIMUM RATINGS
V+ - v- ..................................................... <33V
V+ - Vo ..................................................... < 30V
Vo - V- ..................................................... < 30V
Vo - VS .................................................... < ±22V
VL - V- ...................................................... < 33V
VL - VIN ..................................................... < 30V
VL .............................................................. < 20V
VIN ............................................................. < 20V

Current (Any Terminal) ................................. < 30mA
Storage Temperature ...................... -65·C to + 150·C
Operating Temperature ................... -55·C to + 125·C
Lead Temperature (Soldering 1Osee) .................. 300·C
Power Dissipation ......................................... 450mW
(All Leads Soldered to a P.C. Board)
Derate 6 mWI"C Above 70·C

NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(@ 25·C, v+ =

+15V, v-= -15V, VL= +5V)

PER CHANNEL

MINIMAX LIMITS
TEST CONDITIONS

SYMBOL

CHARACTERISTIC

MILITARY
-55·C

UNIT

COMMERCIAL

+ 25·C + 12S·C

0

+2S·C

+70·C

LOGIC INPUT
IINH

Input Logic Current

VIN = 2.4V Note 1

±1

±1

10

±10

10

IINL
SWITCH

Input Logic Current

VIN = O.BV Note 1

±1

±1

10

±10

10

iJA
iJA

rOS(on)

Drain-Source On
Resistance

IS= -10mA
VANALOG = -10V to +10V

50

50

75

75

100

n

ArOS(on)

Channel to Channel
rOS(on) Match
Min. Analog Signal
Handling Capability

VANALOG

75

30
(typ)

n

(typ)

±11
(typ)

±10
(typ)

V

25

10(011)+
IS(off)

Switch OFF Leakage
Current

Vo= +10V, Vs= -10V
Vo= -10V, Vs= +10V

±.5
±.5

100
100

±5
±5

100
100

nA

10(on)+
IS(on)
CCRR

Switch On Leakage
Current

VO=VS- -10V to +10V

±1

200

±2

200

nA

Min. Channel to
Channel Cross
Coupling Rejection
Ratio

One Channel Off; Any Other
Channel Switches
See Performance Characteristics

ton
toff

Switch "ON" Time
Switch "OFF" Time

See switching time specifications and timing diagrams.

Q(INJ.)

Charge Injection

See Performance Characteristics

OIRR

Min. Off Isolation
Rejection Ratio

f = lMHz, RL = toOn, CL S 5pF
See Performance Characteristics

SUPPLY
1+

+ Power Supply
Quiescent Current

1-

- Power Supply
Quiescent Current

IL

+5V Supply
Quiescent Current

IGNO

Gnd Supply
Quiescent Current

NOTES:

V+ = +15V, V - = -15V,
VL = +5V

54
(typ)

50
(typ)

dB

10
(typ)

15
(typ)

pC

54
(typ)

50
(typ)

dB

1.0

1.0

10.0

10

10

100

iJA

1.0

1.0

10.0

10

10

100

iJA

1.0

1.0

10.0

10

10

100

iJA

1.0

1.0

10.0

10

10

100

IJ.A

See Performance Characteristics

1. Some channels are turned on by high (1) logic inputs and other channels are turned on by low (0) inputs; however O.BV to 2.4V
describes the min. range for switching properly. Refer to logic diagrams to find logical value of logic input required to produce ON or
OFF state.
2. Typical values are for design aid only, not guaranteed and not subject to production testing.

3-111
Note: All typical values have been guaranteed by characterization and are not tested.

=
z
;;

...

.H5140~IMa145
TYPICAL PERFORMANCE CHARACTERISTICS

..• .

~

I

eo
0

S

-

30

+1D

+8

+fS

.'25"C

....

-u·e

20

.'.

I

-r-- t-- i---I'-- r-

40

IH61.'0ATA

I

I

50

-.2OF==:::f:::==:t--T--t-------1

I

! i

eo

1

,

.

I

-20

SOCKn ON CQ'HJt GAOUHDI'lANE JIQ

I
-2

+2

+4

c- ,,,F

~OO=-~~~.~K~~~~.~~-L~UU.OOK~-L~~.~M--~~~,~
...

-10

FREQUENCV (Hzt

ANALOG SIGNAL VOLTAGE (V)
OP006401

0P006201

"OFF" Isolation vs. Frequency

rDS(on) vs. Temp., @ ±15V,
+5V Supplies

ur-~~II~~--r-rT~nn--~,-rr~

... I--------I-----'----l--...:.-...:.~.;.:..~

2~r_----------4_-----------+----------~

.00

\

eo

ul-------I-

eo
§

I

i

--..r-- 1--'

80

"

!

5V, .SV SUPPLIES

r--...i

V

II

I

I

I

50
40

r-

I

30

_~lOV ••SV

TA. '"' +25"C
IH51., DATA

I I T

SUPPLIES--

1

t--...

1%15v. .sv

~IES
T

.'0 +.

20

+&

+4

1'2

OPOO6501

ANALOG SIGNAL, VOLTAGE fV'

Pow.er Supply Currents vs. Logic Strobe
Rate

OPOO6301

rDS(on) vs. Pow.er Supplies

-'20

+.00

I

"I--+-~~=--+--+---

-'00

j

~

~
1

8

.

-

•
-... -eo
>1

4'r_--~~~-+--4---+-

;:

J ....

.\1....(:,

>i _'Oll-;-~:'--+f'--+--+_-+-.::..,t-T:.:.;... ·\1"'11'"' ~

-'00

-VIfW'CT~

r--t--t--t--+--+-+-+-+' .". . .

.ov..
.FRIQuENCY
-V_lOG

-20

c:,
0
100

-'0

-.ERIOO Of 'ULIE REPETITION RATE (101"

-2

+.0

'K

'OK

,-

1M

10M

FREQUENCY ftb)

ANALOG SIGNAL VOLTAGE (V)
OP0111Of

Channel to Channel Cross Coupling
Rejection vs. Frequency

OPOO9601

Charge Injection vs. Analog Signal

3--112
Note: All typical values have .been guaranteed by characterizatioo and are not tested.

.D~DIL

IH5140-IH5145
SWITCHING TIME SPECIFICATIONS
(ton. toft are maximum specifications and ton-toft is minimum specifications)
PART NUMBER

SYMBOL

IH51405141

IH51425143

CHARACTERISTIC

Ion

Switch "ON" time

loff
ton-loff

Sw~ch

Break-belore-make

ton
loff
lon-loff

Switch "ON" time
Switch "OFF" time
Break-belore-make

Ion
toff
ton-loff

TEST
CONDITIONS

COMMERCIAL

MILITARY
-55'C

+ 25'C

+ 125'C

0

+ 25'C

UNIT

+70'C

100

150

75

125

10

5

Figure 3

150
125
'10 (typ)

175
150
5

ns

Switch "ON" time
Switch 'OFF" time
Break-belore-make

Figure 2'

175
125
10

250
150
5

ns

ton
loff
ton-10ft

Switch "ON" time
Switch "OFF" time
Break-belore-make

Figure 3

200
125
'10 (typ)

300
150
5

ns

175

250

125

150

10

5

200

300

125

150

10

5

175

250

125

150

10

5

200
125
'10

300
150
5

Figu;e 2

"OFF" time

ton

Switch "ON" time

10ft

Switch "OFF" time

lon-10ft

Break-belore-make

Ion

Switch "ON" time

10ft

Switch "OFF" time

lon-10ft

Break-belore-make

ton

Switch "ON" time

10ft

Switch "OFF" time

IH5144-

ton-10ft

Break-belore-make

5145

ton
10ft
ton-10ft

Switch "ON" time
Switch "OFF" time
Break-belore-make

Figu;e 4

Figu;e 5

Figu;e 2

Figure 3

ns

ns

ns

ns

ns

I"N_O_T_E_:_S_W_IT_C_H_I_N_G_T_IM_E_S_A_R_E_M_E_A_S_U_R_E_D_@_9_0_%_P_T_S_____'_T_Y.,PicalvaluesIOrdeSign aid only, not guaranteed nor subject to production testing_

fijd

~
"en : ~

NOTE: SWITCHING TIMES ARE MEASURED @ 9O%PT5.

VOUTA

lOpF

,

16

2

15

I~'K!!

ton

:£

lOY

=-i

T 15V

~INPUT l~

13

7

•

i

-=-

.. __

~ .• ~llnAl

1H914

12

~

... UV

~c

~

I I VOUTAORB.
"

I

10%

,I -ISV i" I
~'NPUT
I

9

i :

,

+15v

• ',-"r--'

""f

~'_'OV!~T

11

, ~10V

.lOV@0
-:~ -lOV@ ~

INPUT

IOH

tON

16'1OY

,Op'

..clJ!~

14 -lSY

8

t--

Cotf
-i I--

il

IOV
"

:~-uv

-11Ion

--1:-

TCO0731I

lolf

Figure 4.
TC007111

Figure 2.

I~
VOUTA

lOpF

'"iT" ~I
0.5 •
~

o

.3V

~

-10VL.@

.,v

~
11 ..-,5V

3

--. r0

15

14 -15V

2

lKn

16 :rlOV

1

TTL INPUT

6

TTL INPUT

10
9

z10V

TC00721 I

TC007411

Figure 3.

Figure 5.
3-113

Note: All typical values have been guaranteed by characterization and are not tested.

II

IH5140-IH5145
. FLATPACK (FD-2)

DIP (JE, PEl
VL

12

"

..

ON.

SS00350t

SSOO3601

SPST

IH5140 (rDS(on) < 75U)
FLATPACK (FD-2)

T0-100

DIP (JE, PEl

v'

"

",

o-'-+---<>,-;,,-~.!..o.,

'•• ...,ro.~.....-

_,

GNO
S8003701

ss000901

DUAL SPST
1!'f5141 (rDS(on) < 75U)
FLATPACK (FD-2)

DIP (JE, PEl

T0-100 (00188 EQUIVALENT)

V'

.. o-t---o-o"""'I-<>.'
"

" o-'-l----<>-1r.y8>.,

...

.. o-'--I--""""~""",ro.·,
.. 0::1---<>"---..,..,0.

...

GNO

88004001

SS004201

SSOO410\

SPOT
IH5142 (rDS(on) < 75 U)
FLATPACK (FD-2)

DIP (JE, PEl (D0191 EQUIVALENT)

"
S,
'"
'"

D,
D,

o,
D.

5500<30'

SSOO4401

DUAL. SPDT
IH5143 (ros(OI1) < 75U)

SWITCH STATES ARE FOR LOGIC "1" INPUT

Figure 6: Switching State Diagrams

'3-114
Note: All typical values have been guaranteed by characterization and. are not tested.

iUI

IH5140-IH5145

...

FLATPACK (FD-2)

f

T()..100

DIP (JE, PEl

...2:
UI

'"

"
" <>,-!,..---o'fLf.'-'o D,

UI

',o:.:,l--<>T'4-'<>D,

" o::.l--<>T'4-'-o D,

.. o-=-tl---o~t=<>D.

ON.
8S004501

v-

GND

SSOO46Of

55004601

DPST
IH5144 (ros(on)

< 75Q)

FLATPACK (FD-2)

DIP (JE, PEl (DG185 EQUIVALENT)

" <>"+--<>"""".:.0 .,
13

03

IN,

88004801
55004901

DUAL DPST
IH5145 (roS(on) < 75il)

Figure 6: Switching State Diagrams (Cont.)

TYPICAL SWITCHING WAVEFORMS

SCALE: VERT... 5V10IV. HORIZ.

= 100ns/0IV.

TTL OPEN COLLECTOR LOGfC DRIVE (Corresponds to Figure 8)

+125"C
WFOO4701

WF00220I.

WF002301

TTL OPEN COLLECTOR LOGIC DRIVE (Corresponds to Figure 9)

+25°C

-&SOc
WFOO2401

+12S·C
WF002501

3-115
Note: All typical values have been guaranteed by characterization and are not tested.

WF002601

TYPICAL SWITCHING WAVEFORMS (CONT.)
TTL OPEN COLLECTOR LOGIC DRIVE
(Corresponds to Figure 10)

TTL OPEN COLLECTOR LOGIC DRIVE
(Corresponds to Figure 11)

+25"1:

+25 0 C
WFOO2801

WFOO2701

APPLICATION NOTE

occur. Turning off the supplies would turn off the analog
signal at the same time.
This fault situation can also be eliminated by placing a
diode in series with the negative supply line (pin 14) as
shown in Figure 10. Now when the power supplies are off
and a negative input signal is present this dio(ie is reverse
biased and no current can flow.

To maximize switching speed on the IH5140 family, TTL
open collector logic (15V with a 1kil or less collector
resistor) should be used. This configuration will result in
(SPST) ton and Ioff times of 80ns and 50ns, for signals
between -10V and + 10V. The SPOT and OPST switches
are approximately 30ns slower in both ton and loft with the
same drive configuration. 15V CMOS logic levels can be
used (OV to + 15V), but propagation delays in the CMOS
logic will slow down the switching (typical 50ns -+' 100ns
delays).

I

ANALOG OUT

•

3

•

When driving the IH5140 Family from either +5V TTL or
CMOS logic, switching times run 20ns slower than if they
were driven from + 15V logic levels. Thus Ion is about
105ns, and toff 75ns for SPST switches, and 135ns and
105ns (ton, Iofl) for SPOT or OPST switches. The low level
drive can be made asfa~t as the high level drive if ±5V
strobe levels are I;ISed instead of the usual OV'.... + 3.0V
drive. Pin 13 is taken to -5V instead of the usualGNO and
strobe input is taken from +5V to -5V levels as shown in
Figure 7.

&

l ' ANALOG IN {CHANNEL AI

!

rrL

!iii

.:!!J '

• =
ANALOG, OUT

:

CMOS
LEVEL

IM'UT
STROBE

9

ANALOG IN {CHANNEL 81

AF002801

Figure 7,.

The typical channel of the IH5140 family conslsts of both
P and N-cllimn~1 MOSFETs. The N-channel MOSFET uses
a "Body, Puller" FET'todrive the body to -1SV(±'1Sv
supplies)t6 get good breakdown voltages when the switch
is in the off state (See Fig. 8). This "Body Puller" FET also
allows the N-channel body to electrically float when the
switch is in the on state producing a fair.ly constant
RoS(ON) with different signal voltages. While this "Body
Puller" FET improves switch performance, it can cause a
problem when analog input sigl1als are present (negative
signals only) arid 'power supplies are off. This fault condition
is shown, in Figure 9.

2:.15" FROM

DRIVERS

-16V

AFOO2901

Figure 8.

Current,will flow, from ':'10V analog voltage through the
drain to body junction of Q1, then through the drain ,to body
junction of OS to GNO. This means that there is 10Vacross:
two forward"biased silic,on diodes and current will go to
whatever value', the input signal Source is capable of
supplying. If the ~oalog input $ignal is derived from the
same supplies as the switch this fault condition cannot

AFOO3001

Figure 9.

3-116
Note: All typical values have been guaranteed by characterization: and are not

tes~ed,

IH5140-IH5145
APPLICATION NOTE (CONT.)
'i6

~r:~~UIVALENT

INA

~ PL.IN
... 1
(1.~or-----"f-- -'6V

(,1;)-----.
~
~

+15V

-;;<

IN.

~

,.1

-=1-

. .V

T2LBIN

AF00310l

Figure 10.

APPLICATIONS

+15V
+15V

2

r

3
ANALOG 0--+-"-4
INPUT

6 -+-OOUTPUT

510
-15V
10.000PF
POLY-=- STYRENE

I

LOGIC INPUT

+3V
OV =

IH5143

=> SAMPLE MODE
> HOLD MODE

AFOO3211

Figure 11: Improved Sample and Hold Using IH5143

16
15

+VANALOG

.s-L
TTL

12 "::"
+5V

11

+15V

10

9
2R

R
ETC.

R

LOGIC
STROBE

SL
+VANALOG

TTL

LOGIC
STROBE

R
ETC.
AF003311

EXAMPLE: If - VANALOG - -10VDC and + VANALOG = + 10VDC then Ladder Legs are switched between ± 10VDC, depending upon state of Logic
Strobe.

Figure 12: Using the CMOS Switch to Drive an R/2R Ladder Network (2 Legs)

3-117
Note: All typical values have been guaranteed by characterization and are not tested.

I

·IID~DI6

., I.H5140-IH5145

!z

.,.
j

APPL.ICATIONS (CONT.)
lOOk!)

!

LOGIC
STROBE
AF003401

CONSTANT GAIN, CONSTANT Q; VARIABLE FREQUENCY FILTER WHICH PROVIDES SIMULTANEOUS LOWPASS, BANDPASS, AND HIGHPASS
OUTPUTS. WITH THE COMPONENT VALUES SHOWN, CENTER FREQUENCY WILL BE 235Hz AND 23.5Hz FOR HIGH AND LOW LOGIC INPUTS
RESPECTIVELY, Q = 100, AND GAIN = 100.

fn

= CENTER

.

1

FREQUENCY = 21T RC

Figure 13: Digitally Tuned Low Power Active Filter

3-118

Note: All typical values have been guaranteed by characterization and are not tested.

IH5148-IH5151
High-Level CMOS
Analog Switches
GENERAL DESCRIPTION

FEATURES

The. IH5148 family of solid state analog switches are
designed using an improved, high voltage CMOS technology. Destructive latchup has been eliminated. Early CMOS
switches were destroyed when power supplies were removed with an input signal present; the IH5148 CMOS
technology has eliminated this problem.
Key performance advantages of the 5148 series are TTL
compatibility and ultra low-power operation. RDS(on) Switch
resistance is typically in the 14n To 18n Area, for Signals
in the -10V to + 10V range. Quiescent current is less than
10j.lA. The 5148 also guarantees Break-Before-Make
switching which is logically accomplished by extending the
tON time (200nsec typ.) such that it exceeds toFF time
120nsec typ.). This insures that an ON channel will be
turned OFF before an OFF channel can turn ON. The need
for external logic required to avoid channel to channel
shorting during switching is thus eliminated.
Many of the devices in the 5148 series are pin-for-pin
compatible with other analog switches, and offer improved
electrical characteristics.

•
•
•
•
•
•
•
•

Low RDS(ON) - 25n
Switches Greater Than 20Vpp Signals With ± 15V
Supplies
Quiescent Current Less Than 100j.tA
Break-Before-Make Switching tOFF 120nsec, Typ.
toN 200nsec Typical
TIL, CMOS Compatible
Non-Latching With Supply Turn-Off
Complete Monolithic Construction
±5V to ±15V Supply Range

CMOS ANALOG SWITCH PRODUCT
CONDITIONING
•
•
•
•
•
•
•

The Following Processes Are Performed 100% in
Accordance With MIL-STD-883
Precap Vlsual- Method 2010, Condo B
Stabilization Bake - Method 1008
Temperature Cycle-Method 1010
Centrifuge - Method 2001, Condo E
Hermeticity-Method 1014, Condo A, C
(Leak Rate < 5 x 10- 7 atm ccls)

ORDERING INFORMATION
ORDER PART
NUMBER

FUNCTION

PACKAGE

TEMPERATURE RANGE

HARRIS
EQUIVALENT

IH5148MJE
IHS148CJE
IH5148CPE
IH5148MFD
IH5148CTW
IH5148MTW

Dual
Dual
Dual
Dual
Dual
Dual

SPST
SPST
SPST
SPST
SPST
SPST

16 Pin CERDIP
16 Pin CERDIP
16 Pin Plastic DIP
14 Pin Flat Pack
TO-l00
TO-l00

-SS·C
O°C to
O°C to
- SO°C
O°C to
-SsoC

to 12SoC
lO°C
70°C
to 12S·C
70°C
to 12SoC

HI-5048
HI-S048
HI-S048
HI-5048
HI-S048

IHS149MJE
IHS149CJE
IH5149CPE
IH5149MFD

Dual
DuaL
Dual
Dual

DPST
DPST
DPST
DPST

16
16
16
14

-5S·C
O°C to
O°C to
-SO°C

to 125·C
70°C
70°C
to 12SoC

HI-S049
HI-5049
HI-S049
HI-S049

IHS1S0MJE
IHS1S0CJE
IH51S0CPE
IHS1S0MFD
IH51S0CTW
IHS150MTW

SPOT
SPOT
SPOT
SPOT
SPOT
SPOT

16 Pin CERDIP
16 Pin CERDIP
16 Pin Plastic DIP
14 Pin Flat Pack
TO-l00
TO-l00

-SS·C to 12SoC
O°C to 70°C
O°C to 70°C
-SO°C ,to 12S·C
O·C to 70°C
-SsoC to 12S·C

HI-S050
HI-SOSO
HI-5050
HI-S050
HI-SOSO
HI-5050

IHS1S1MJE
IH51S1CJE
IHS1S1CPE
IHS1S1MFD

Dual
Dual
Dual
Dual

16
16
16
14

-55°C
O°C to
O°C to
-50·C

HI-5051
HI-5051
HI-SOSl
HI-S051

SPOT
SPOT
SPOT
SPOT

Pin
Pin
Pin
Pin

Pin
Pin
Pin
Pin

CERDIP
CERDIP
Plastic DIP
Flat Pack

CERDIP
CEROIP
Plastic DIP
Flat Pack

to 125°C
70·C
lO°C
to 12SoC

HI~S048

NOTES: 1. Ceramic (side braze) devices also available; consult factory.
2. MIL temp range parts also available with MIL-STD-883 processing.

3-119
Note: All typical values have been guaranteed by characterization and are not tested.

304300-002

:.n~oll

i

IH5148.~IH5151·

!I

ABSOLUTE MAXIMuM RATINGS

I

V+, v- ...........................·............................ <3SV
v+, Vo ....................................................... <30V
VO, v- .................................................•...... <;: 30V
Vo, Vs ................................................. : ..... < .±22V
VL,. v- .................................................... :....... < 33V
VL, VIN ............ : .......................................... < 30V
VL ............................. ; ................................. < 20V
VIN................................................: ........... ,. < 20V

'10

Current (Any Terminal) .............................., .. < SOmA
Storage Temperature ...................... -SS·C to + 1S0·C
Operating Temperature ...... ; ..... , ...... -5S·C to . + 12S·C
Lead Temperature (Soldering, 1Qsec) ................. 300·C
Power Dissipation .......... ; .............................. .4S0mW
(All Leads Soldered to a P.C. Board)
Derate SmW I"C Above 70·C

NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions above those indicated in the operational sections. of the spec"ications is not implied.
E~posure to absolute maximum rating conditions for extended periods may affect device reliability.

+15V (vtl

4KO

51(0

16

BD014011

Figure 1: Functional Diagram (Typical SwltchSchematic-IH5150 in 16 pin DIP PKG.)

3-120
Note: All typical values have been guaranteed by characterization and are not tested.

.O~OIL

IH5148-IH5151
ELECTRICAL CHARACTERISTICS

(TA @ 25°C, V+

= +15V,

V-

= -15V,

PER CHANNEL

= +5V)

MINIMAX LIMITS
TEST CONDITIONS

SYMBOL

VL

COMMERCIAL

MILITARY

CHARACTERISTIC

+ 25°C

+ 70°C

IIN(ON)

Input Logic Current

VIN = 2.4V (Note 1)

±1

±1

±10

±1

±10

p.A

IIN(OFF)

Input Logic Current

VIN = 0.8V (Note 1)

±1

±1

±10

±1

±10

p.A

ROS(ON)

Drain-Source On
Resistance

Vo=±10V, 15= -10mA

25

25

50

30

n

-55°C

+ 25°C + 125°C

UNIT

0

AROS(ON)

Channel to Channel
ROS(ON) Match

10
(Typ)

15
(Typ)

n

VANALOG

Min. Analog Signal
Handling Capability

±14
(Typ)

±14
(Typ)

V

Switch OFF Leakage
Current

VANALOG = -10V to + 10V

±0.5

50

±1.0

100

nA

Switch On Leakage
Current

Vo= Vs = -10V to + 10V

±1.0

100

±2.0

100

nA

Q(INJ)

Charge Injection

See Figure 4

(10)
(Typ)

(10)
(Typ)

mV

OIRR

Min. Off Isolation
Rejection Ratio

1= lMHz, RL ~ tOOn, CL:S 5pF
See Figure 5

54
(Typ)

50
(Typ)

dB

IO(OFF)
IS(OFF)
ID(ON) +
IS(ON)

SUPPLY
1+

+ Power Supply
Quiescent Current

1-

- Power Supply
Quiescent Current

IL

+ 5V Supply
Quiescent· Current

IGNO

Gnd Supply
Quiescent Current

CCRR

Min. Channel to
Channel Cross
Coupling Rejection
Ratio

10

10

100

10

p.A

10

10

100

10

p.A

10

10

100

10

p.A

10

10

100

10

p.A

50

dB

VI = + 15V, V2 = -15V.
VL= +5V, VR=O

One Channel Off; Any Other
Channel Swijches as per
Figure B

54
(Typ)

NOTE 1: Some channels are turned on by high "I" logiC inputs and other channels are turned on by low "0" inputs; however O.BV to 2.4V describes the min.
range lor switching properly. ReIer to logic diagrams to lind logical valus 01 logic input required to produce "ON" or "OFF" state.

SWITCHING TIME SPECIFICATION
IH5148 SPST SWITCH
SYMBOL

MAX

UNIT

Ion

Swijch "on" time

PARAMETER

RL=IKn, VANALOG= -IOV

TEST CONDITIONS

MIN

250

ns

loll

Switch "off" time

To + 10V; See Figures 3 and 6

200

ns

IH5149 OPST SWITCH
SYMBOL

MAX

UNIT

ton

Switch "on" time

PARAMETER

RL = 1Kn;· VANALOG = -10V

TEST CONDITIONS

MIN

350

ns

loll

Switch "off" time

To + 10V; See Figures 3 and 6

250

ns

IH5150 & IH5151 SPOT SWITCH
MAX

UNIT

ton

Switch "on" time

RL = lKn, VANALOG = -10V

500

ns

loll

Switch "off" time

To + 10V; See Figures 3 and 6

250

ns

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

NOTE 2: For IH5150 & IH5151 devices, channels which are off lor logic input ~ 2.4V (Pins 3 & 4 on 5150, & Pins 3 & 4, 5 & 6 on 5151) have slower Ion time,
than channels on Pins I, 16, & 8, 9. This is done so switch will maintain break-balora-make action when connected in OT configuration, i.e. Pin 1
connected in Pin 3.

3--121
Note: All typical values have been guaranteed by characterization and are not tested.

...

".U~OIL

10
;; IH5148";I'H5151

;

I

......

' cD

"

SWITCH S1'ATESARE FOR
L()GIC "1" INPUT

DIP (DE) PACKAGE

FLAT PACKAGE

(TW) PACKAGE

10

;

DUAL.SPST IH5148
v,

"

v·

v·
,i

"

I,

.,
.,

0,

I,

0,

I,

.,

v,

II

"

II

I,

0,

.,

.,
lID

v·

..

II

v-

II'

SS007401

•

I,

0,

I,

...

v-

.

v88007601

S$007501

DUAL DPST IH5149
v,

v,

.
.,..
I,

0,
0,

I

_1

..
It

II
lID

.,

.,

.
I,

v·
n

"

..
t,

II
I

0,

,.

...

II

vS5007701

..

V-

55007801

SPDT IH5150

"

,.

"

,.

I,
I,

I,

..

•

,.
V,

n

II

,"

II

I,

..

t,

I,
I,

It

•

•

... .

II
lID

II

V88007901

SSOO8OOI

DUAL SPDTIH5151
v,

,.

.,....
I,

"

OJ

....

..'1
lID

.,

I,
I,

""

II

v·
n
0,

Is

.,

,

....

,.

II
OlD

SSOO82
-

IOpf

I

m
f:'"

_oa ......

:: --D-i>-

1110

",00000

5.0

LOGIC IUUT

tlDro--t>--

~

1

'":'":"

'000

":'''':''
TC03681 I

~

TC037011

TC03691 I

Figure 3

Figure 4

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 5

(Per Channel)

ROS(ON) @ ±15V, ±5V SUPPLIES
Ros(ON)

o

100
90

80
70
60

50
40
30
20
10

±5V SUPPLIES i@

.,...Er-

't!J

A5V SUPPLIEs..

o

-12V-l0-8-6 -4 -2 OV 2 +4V 6 8+10V+121
HDS (ON) vs
ANALOG INPUT VOLTAGE
0P056911

CROSS COUPLING
REJECTION vs FREQUENCY

120

..........

100

=-

~

...

80

ec

60

Vi
C>
II:

:>

.

~ '~-;¥ ~

.....
I" .....

....

.........

~

.....

40
3V
INPu.!!"l.-

20
CCRR

o

1

10

2oLOG 2000mVpp
VOUT (mVpp)
100 1k 10k 100k 1M

SWITCHED
CHANNEL

'"

FREOUENCY (Hz)

r

I
I

I

I

I

I

I

I
I

L""

VOUT

1000

~I
~-I

~----1'" ~

510

TC033521

OP056811

CROSS COUPLING
REJECTION TEST CIRCUIT

3-123
Note: All typical values have been guaranteed by characterization and are not tested,

;; IIf5148-IH5151
;;
,

!

TYPICAL PERFORMANCE CHARACTERISTICS (CONT.)
OFF ISOLATION
,...120

!

i"

-100

'-

~ .....

ii' -80
~

...ei&:"
c
:»

VI

FREQUENCY

.

510

.... 1"'- .....

-60

--

OFF STATE
~_
OEPENDS ON. PART~

-40

-20

20LOG 2000mVpp
VOur(mVpp)
1Hz 10Hz 100Hz lk 10k lOOk 1M

=

OIRR

o

l---o
.
1
1000

Your

....

FREQUENCY (Hz)

TC033111

OFF ISOLATION TEST CIRCUIT
POWER SUPPLY QUIESCENT CURRENT
FREQUENCY RATE

:!!i

~

+

ffi

z:

20

I

~

LOGIC

/

f = TI

~

~

!i!

~

/

~

VI

I

2
1

V
10

TC033411

100

lk

10k

lOOk

LOGIC FREQUENCY @ 10% DUTY CYCLE (Hz)
OP056711

LOGIC INPUT WAVEFORM

TC0367 2.4V VENH > 2.4V
Logic "0" = VAL < O.8V

v+
Db
NC

3

S8b

S7.

S7b
SIb"

S8a
S5a

S4lI
S3a

S2a

Ao
A,
A2

V+ COMMON TO SUBSTRATE
CD035601

Figure 1: Pin Configuration
(Outline dwgs JE, PEl

3-135
Note: All typical values have been guaranteed by characterization and are not tested.

1
1
1
1
1
1
1
1

1

2
3
4
5
6

7
8

IIH5216
!
511

u.o---"'i
S30o---"'i

S40o---"'i

S5ao---"'i
... 0-:--;
57. o---"'i

... 0---"1

Do
till

SI~

S2~0---"I

S3IIo---"I
Mo---"I
S5IIo---"'i
SIll 0---'"<

S~O---:J
S.o---'"<
TO OlCOOl lOGIC
COITROIUNG 80TH
TIERS Of MUXI!IG

3 UIE "I'RY AOIHIfSS IIIPUTS
110 01 AID Ell • 5V
AIOVE EXAMI'U SHOWS CHA.IElS I. 'NO ,_ ON.
LD011211

Figure 2: Functional Diagram

+15V

WK' tIL

+3.0V
VA+~

.wrr~o~

VOUT 0

~~~-r~~----~VO~

O.9VO

Vo

35pF

open

-

open

Vs
TC034611

TC038501

Figure 3: t open (Break-Before-Make) Switching Test

3-136
Nole: All typical values have been guaranteed by characterizalion and are nol l'1sled.

iUI

IH5216

...N
~

ABSOLUTE MAXIMUM RATINGS
VIN (A, EN) to Ground ....................... -15V to + 15V
Vs or VD to V+ ............................... +25V to -40V
Vs or VD to V- ................................ -25V to +40V

Current (Any Terminal) .................................... 20mA
Operating Temperature ...................... -55 to + 125·C
Storage Temperature ......................... - 65 to + 150·C
Lead Temperature (Soldering, 10sec) ................. 300·C
Power Dissipation" ...................................... 1200mW

V+ to Ground ............................. , ................... 16V
V- to Ground ................................................ -16V

"All leads soldered or welded to PC board. Derate 10mW/'C above 70'C.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and lunctional
operation 01 the device at these or any other conditions above those indicated in the operational sections 01 the specilications is not implied. Exposure to
absolute maximum rating conditions lor extended periods may allect device reliability.

ELECTRICAL CHARACTERISTICS (v+
CHARACTERISTIC

= 15V, v- = -15V, VEN = 2.4V, unless otherwise specified.)
MAX LIMITS

NO
MEASURED TESTS
TERMINAL
PER
TEMP

TYP
25'C

TEST CONDITIONS

M SUFFIX

C SUFFIX

UNIT

-55'C

25'C

125'C

G'C

25'C

70'C

SWITCH
S to D

ROS(on)

16

Vo -10V.
IS= -LOrnA

Sequence each
switch on

700

1000

1000

1500

1200

1200

1800

16

Vo - -10V
IS= -1.0mA

VAL - 0.8V,
VAH - 2.4V

500

1000

1000

1500

1200

1200

1800

.:l.Ros(on)

ROS(on)max-ROS(on)min

.:l.ROS(on) =

n

%

5

ROS(on)avg.
VS=±10V
S

IS(oll)

D

10(otl)

D

10(on)

16

Vs -10V,
Vo = -10V

0.02

±0.5

50

±1.0

50

16

Vs - -10V,
Vo = 10V

0.02

±O.S

SO

±1.0

SO

1

Vo -10V.
VS= -10V

O.OS

±1.0

100

±2.0

100

0.05

±1.0

100

±2.0

100

0.1

±2.0

100

±4.0

100

0.1

±2.0

100

±4.0

100

VEN =O.8V

1

VO= -10V,VS-10V

16

VS(AIJ) = Vo

16

VS(AIJ)

= 10V

= Vo =

Sequence each
switch on

-10V VAL - 0.8V,
VAH = 2.4V

nA

FAULT
IS with
Power OFF

S

16

Vsupp = OV, VIN = ±25V,
VEN=VO=OV, A(:), AI, A2=OV or SV

1.0

2.0

S.O

IS(oII) with
OVervoltage

S

16

VIN = ±25V, Vo - ± 10V

1.0

2.0

S.O

A(j, AI, A2
or
EN

4

VA = 2.4V, or OV

om

-10

-30

-10

-30

4

VA=ISV

0.01

10

30

10

30

p.A

INPUT
IEN(on) IA(on)
or
lEN (off} IA(off}
DYNAMIC
ttransition

D

0.3

Iopen

D

0.2

Ion(EN)

D

0.6

I.S

D

0.4

1

\on-loll BreakBelore-Make
Delay Settling
Time

D

"OFF"
Isolation

D

VEN =

S

Vs-O

CO(otl)

D

Vo=O

Supply
Current

D to S

1+
I-

1+
I-

At, A2 Strobed
VIN = ±10V.

VEN = 0, RL = 200n, CL = 3pF,
Vs = 3VRMS, I = SOOkHz

Cs(otl)
CDStoffl
SUPPLY

+SV,' A(:),

Vs = 0, Vo - 0
1
I

1
I

1VEN-OV,
1I = 140kHz
1to 1 MHz

p.A

1

IoIl(EN)

16

1

I'S

25

ns

60

dB

5
25

pF

1

1 0.5
I 0.02

All VA = OV/SV
VEN=SV

3--137
Note: All typical values have been guaranteed by characterization and are not tested.

0.6
0.6

1
I

1
I

1.0
1.0

1
I

mA

; IH5341
('I)

; Dual SPST CMOS
RFIVideo Switch
GENERAL DESCRIPTION

FEATURES

The IHS341 is a dual SPST, CMOS monolithic switch
which uses a "Series/Shunt" ("T" switch) configuration to
obtain high "OFF" isolation while maintaining good frequency response in the "ON" condition.
Construction of remote and portable video equipment
with extended battery life is facilitated by the extremely low
current requirements. Switching speeds are typically
ton = lS0ns and toti = 80ns, and "Break-Before-Make"
switching is guaranteed.
Switch "ON" resistance is typically 40n-SOU with ± 15V
power supplies, increasing to typically 175U for ±5V
supplies. The devices are available in TO-l00 and 14-pin
epoxy DIP packages.

•
•
•
•
•
•
•
•
•

ROS(on) < 75U
Switch Attenuation Varies Less Than 3dB From
DC to 100MHz
"OFF" Isolation> 60dS @ 10MHz
Cross Coupling Isolation> 60dB @ 10MHz
Compatible With TTL. CMOS Logic
Wide Operating Power Supply Range
Power Supply Current < 1~
"Break-Before-Make" Switching
Fast Switching (80ns1150ns Typ)

ORDERING INFORMATION
PART NUMBER

TEMPERATURE
RANGE

PACKAGE

IH5341 CPO

o to +70·C

14-pin
PLASTIC DIP

IH53411TW

-20·C to +85·C

10-pin TO-l00

IH5341MTW

-55·C to + 125°C

10-pin TO-l00

s, o--~------<~--------J

I

ON,D

I

, I

INz

TOPYIEW
TOI'VIEW
COOO3301

LS00781t

Figure 1: Functional Diagram
(Switches are open for a logical "0" control
input, and closed for a logical "1" control
input.)

Outline dwg: PO
Outline dwg: TW
Figure 2: Pin Configurations

3-138
Note: All typical values have been guaranteed by characterization and are not tested.

30S528-002

i

IH5341

en

......

Col

ABSOLUTE MAXIMUM RATINGS

v+

to Ground ............................................... + 17V
V- to Ground ................................................ -17V
VL to Gro.und .......................................... V+ to VLogic Control Voltage ................................ V + to VAnalog Input Voltage ................................. V + to VCurrent (any Terminal) ..................................... 50mA

Operating Temperature:
(M Version) ......................... -55°C to +125°C
(I Version) ............................. -25°C to + 85°C
(C Version) .............................. O°C to + 70 0 e
Storage Temperature ...................... -65°e to + 150 0 e
Lead Temperature (Soldering, 10sec) ................. 300 oe
Power Dissipation ......................................... 250mW
Derate above 25°C @ ........•............. 7.5mW/oe

Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

+15V

-15V

.......~--+-=-o SWITCH

05002901

Figure 3: Equivalent Schematic Diagram IH53411TW (1/2 of actual circuit on chip shown)

3-139
Note: All typical values have been guaranteed by characterization and are not tested.

; IH5341·

:3

!

DC ELECTRICAL CHARACTERISTICS
= + 15V, VL = +5V, v- = -15V, ·TA = 25°C unless

v+

otherwise specified.
M GRADE DEVICE

SYMBOL

PARAMETER
Supply Voltage
Ranges
Positive Supply
Logic Supply
Negative Supply

V+
VL
V-

TEST CONDITIONS

Switch "ON"

Vo = ±5V

Resistance
(Note 4)

IS = lOrnA, VIN
Vo-±10V

ROS(on)

Switch "ON"
Resistance
On Resistance
Match Between
Channels

dROS(on)

-SS·C

+ 25·C

+ 12S·C

IIC GRADE DEVICE

-251
O·C

+2S·C

+851 ,
+70·C

4.5> 16
.4.5> V+
-4> -16

(Note 3)

ROS(on)

TYP

V
75

~

75

100

75

75

100

2.4V

V+ =VL= +5V,
VIN = 3V
V- = -5V, Vo = ±3V
15= lOrnA
IS = lOrnA, Vo = ±5V

125

125

175

150

150

175

250

250

350

300

300

350

VIL
10(011)
or
15(011)

Switch "OFF"
Leakage
(Notes 2 and 4)

VS/O - ±5V
VIN" O.BV
VS/O = ±14V

±0.5

50

±1.0

100

±0.5

50

±1.0

100

10(on)
+
IS(on)

Switch "ON"
Leakage

VS/O =±5V
VIN ~ 2.4V
VS/O = ±14V

±1

50

±2

100

liN

Input Logic
Current

VIN

1+

Positive Supply
Quiescent Current

1IL
NOTES:

1.
2.
3.
4.

> 2.4

V

< O.B

±1

100

±2

100

0.1

.±1

±1

10

±1

±1

10

VIN=OVOr +5V

0.1

1

1

10

1

1

10

Negative Supply
Quiescent Current

VIN =OV or +5V

0.1

1

1

10

1

1

10

Logic Supply
Quiescent Current

VIN -OV pr +5V

0.1

1

1

10

1

1

10

~

2.4V or < OV

AC ELECTRICAL CHARACTERISTICS
= + 15V, VL = + 5V, v- = OV, TA = 25°C unless
SYMBOL

p.A

otherwise specified (Note 5).

PARAMETER

TEST CONDmONS

MIN

TYP

MAX

UNIT

150
BO

300
150

ns

Ion

Switch "ON" Time

See Figure 4

toll
OIRR

Switch "OFF" Time
"OFF" Isolation Rejection Ratio

See Figure 4
See Figure 5 (Note 6)

CCRR

Cross Coupling Rejection 'Ratio

See Figure 6 (Note 6)

60

Switch Attenuation 3dB Frequency

See Figure 7 (Note 6)

100

f3dB

nA

Typical values are not tested in production. They are given as a design aid only..
Positive and negative voltages applied to opposite sides of switch, in both directions successively.
These are the operating voltages at which the other parameters are tested, and are not directly tested.
The logic inputs are either greater than or equal to 2.4V or less than or equal to O.BV, as required, for this test.

V+

NOTES:

n

5

Logical "I" Input
Voltage
Logical "0" Input
Voltage

VIH

UNIT

5. All AC parameters are sample tested only.
6. Test circuit should be built on copper clad ground plane board, with correctly terminated coax leads, etc.

3-140
Note: All typical values have been guaranteed by characterizaiion and, are not tested.

60

dB

iCII

IH5341

~

TEST CIRCUITS

Tn
INPUT

+3V

ov

-""7'50%------'""""

.+1W-T---~~=-----~

YouT

10%

VANALOG + SY

+::

YouT

ov
ov----...

=rI...!TL IN -+--''F't

10"

YOUT

RL =

VANALOG

1Il00

=-

SV

__ 1W _____

~~IO%~~___~

WFOO33(J1
TCOO791 I

Note: Only one channel shown. Other acts identically.

Figure 4: Switching Time Test Circuit and Waveforms

TC008101

TGOOSOOI

VIN

= ±5V

(10Vp_p) @ f

= 10MHz
VIN

VIN
OIRR = 20log - -

Your

= 225mVrms @ f =

10MHz

VIN
CCRR = 20109 - -

vour

Note: Only one channel shown. Other acts identically.

Figure 5: OFF Isolation Test Circuit

Figure 6: Cross-Coupling Rejection Test
Circuit

RL
ATTN: =20 10910---"-ROS(on)+RL
Nominally, at DC, this ratio is equal to -4dB. When the attenuatio
reaches -1 dB, the frequency at which this occurs is f3dB.

TCOO8201

Note: Only one channel shown. Other acts identically.

Figure 7: Switch Attenuation Versus Frequency, Test Circuit

3-141
Note: All typical values have been guaranteed by characterization and are not tested.

i·IH5341

I

TYPICAL PERFORMANCES CHARACTERISTICS
ROS(on) Versus Analog Input Level
with ±SV POl/ier Supplies

Ros(onl Versus Analog Input
Voltage w th ± 1SV Power .Supplies

70 PIN 3= +ISIf, PIN 7= -15V
PIN.l0= +SV .
TA=25·C
.:
60

7

'I

g

i

50

i

40

V

V"

"

PIN 3=PIN 10= +5V
PIN 7= -SV
fo-160 TA=2S·C

~
~120

V

80

if
S

70

II:
II:

80

6

/

50

,

90
80

30
0.1

0

+S
ANALOG INPUT VOLTAGE LEVEL (V)

1

10

100

FREQUENCY (MHz)

QP006701

CPOO6601

100

'\

40

80

-s

·c

TA= +25

90

/

OPOOB801

Typical Switch Attenuation Versus Frequency
(RL = 7S0, See Figure 7)

CCRR (Cross Coupling Rejection) Versus
Frequency (See Figure 6)

-3.3
TA=ZSOC

T,,-.+2S·C

m-3.4

S

" -3.5

.2

if 70
S
II:
II:

.;

100

30
-15 -10 -5 0
5
10 15
ANALOG INPUT VOLTAGE LEVEL (V)

u
u

100

j

g140

OIRR (OFF Isolation Rejection) Versus
Frequency (See Figure 5)

~ -3.8

S

"

~3.7 ' - -

50

~

-3.8

40

UI

~

60

:c

~-

~
• -3.9
-4.0
0.1

30
0.1

1

10

100

l}111111
1

10

OPO07801

0P006901

750

~0--0 DRAIN
SWITCH
L_ _ _ J
(OUT)
I

+15V

SOURCE
0-----<)"'"'1/ (
SWITCH.
(IN)

CONTROL ~_ r-'\...~o­
IN~
DRIVER
TRANSLATOR

100

FREQUENCY (MHz)

FREQUENCY (MHz)

--'11\'-.....- - . ,

Vour r------':r;

ANALOG

~

INPUT
LOOO2201

Figure 8: Internal Switch Configuration

DETAILED DESCRIPTION
As can be seen in Figure 8, the switch Circuitry is of the
so-called "T" configuration, where a shunt switch is closed
when the switch is open. This provides much better
isolation between the input and the output than single
series switch does, especially at high frequencies. The
result is excellent performance in the Video and RF region
compared to conventional Analog Switches.
The input level shifting circuit is similar to that of the
IH5140 Series of Analog Switches, giving very high speed
and guaranteed "Break-belore-Make" action, with negligible static power consumption and TTL compatibility.

1000pFT
CHOLD

r--1-+ 3V

...J

L-ov

TTL. IN ISTROBE)
TCO08301

• Adiust pot for OmYpop step @ YOUT with no analog (AC) signal·
present

Figure 9: Charge Injection Compensation

3-142
Note: All typical values have been guaranteed by characterization and are not tested.

.U~OI1. en
i

IH5341

!

DETAILED DESCRIPTION (CONT.)

+5V

YoUT
DC81AS

VOLTAGE

--sv

o-.J\I..,.,.....,

ANALOG '--.l

INPUT~

...-......-=f:ll

I.F

22I>i'-3SpF
CHOto

T....

1000pF

+ 3V
OV

:rL
TTL
CONT~LII'I
TC008401

Figure 10: Alternative Compensation Circuit

APPLICATIONS
Charge Compensation Techniques

+,15V-IW-_----.

Charge injection results from the signals out of the level
translation circuit being coupled through the gate-channel
and gate-source/drain capacitances to the switch inputs
and outputs. This feedthrough is particularly troublesome in
Sample-and-Hold or Track-and-Hold applications, as it
causes a Sample (Track) to Hold offset. The IH5341
devices have a typical injected charge of 30pC-50pC
(corresponding to 30mV-50mV in a 1000pF capacitor),at
VS/O of about OV.
This 'Sample (Track) to Hold offset can be compensated
by bringing in a signal equal in magnitude but of the
opposite polarity. The circuit of Figure 9 accomplishes this
charge injection compensation by using one side of the
device as a S & H (T & H) switch, and the other side as a
generator of a compensating signal. The 1kn potentiometer allows the user to adjust the net injected charge to
exactly zero for any analog voltage in the -5V to +5V
range.
Since individual parts are very consistent in their charge
injection, it is possible to replace the potentiometer with a
pair of fixed resistors, and achieve less than 5mV error for
all devices without adjustment.
An alternative arrangement, using a standard TTL inverter to generate the required inversion, is shown in Figure 10.
The capacitor needs to be increased, and becomes the only
method of adjustment. A fixed value of 22pF is good for
analog values referred to ground, while 35pF is optimum for
AC coupled signals referred to -5V as shown in the figure.
The choice of - 5V is based on the virtual disappearance at
this analog level of the transient component of switching
charge injection. This combination will lead to a virtually
"glitch-free" switch.

TCOO8501

Figure 11: Overvoltage Protection Circuit

Overvoltage Spike, Protection
If sustained operation with no supplies but with analog
signals applied is pOSSible, it is recommended that diodes
(such as 1N914) be inserted in series with the supply lines
to the IH5341. Such conditions can occur if these Signals
come from a separate power supply or another location, for
example. The diodes will be reverse biased under this type
of operation, preventing heavy currents from flowing from
the analog source through the IH5341.
The same method of protection will provide over ±25V
overvoltage protection on the analog inputs when the
supplies are present. The schematic for this connection is
shown in Figure 11.

3-143
Note: All typical values have been guaranteed by characterization and are not tested.

:: .HS35l:·'
i QUAD SPST CMOS
- RFIVideo Switch
·GENERAL DESCRIPTION

~~

FEATURES

cM'os

The IH5352 is a QUAD SPST,
monolithic vide9
'switch which uses a "Series/Shunt" ("T" switch) configuration to obtain high "OFF" isolation while maintaining
good frequency response in the "ON" condition.
Construction of remote and portable video equipment
with extended battery life is facilitated by the extremely iow
current requirements. Switching speeds are typically
ton = 150ns and toft = 80ns, and "Break-Before-Make"
switching is guaranteed.
Switch "ON" resistance is typically 40n-50n with ±15V
power supplies, increasing to typically 175n for ±5V
supplies.

IH5352CPE
IH53521JE
IH5352MJE

TEMPERATURE
RANGE
Q'C to +70'C

ROS(on)

•

Switch Attenuation Varies Less Than 3dB From
DC to 100MHz
"OFF" Isolation> SOdB @ 10MHz
Cross Coupling I,solation > SOdB @ 10MHz
Directly Compatible with TTL, CMOS Logic
Wide Operating Power Supply Range
Power Supply Current < 1~
"Break-Before-Make" Switching
Fast SWitching (80ns/150ns Typ)

•
•
•
•
•
•
•

APPLICATIONS
•
•
•
•
•

ORDERING INFORMATION
PART
NUMBER

< 7Sn

•

PACKAGE

Video Switch
Communications Equipment
Disk Drives
Instrumentation
CATV

l6-PIN PLASTIC DIP

-25'C to +85°C l6-PIN CERDIP
-55'C to + l25'C l6-PIN CERDIP

IH5352

s., 0

a"'(o~-----J

CD030701

lSOO780l,

Figure 1: Functional Diagram
(Switches are open for a, logic
",0" control Input, and closed
for a logic "1" control input.)

Figure 2: Pin C.onfigurations
Package Outline Drawing:

PE, JE

3-144
Note: All typical values have been guaranteed by characterization amI' are not tested.

305529-003

IH5352
ABSOLUTE MAXIMUM RATINGS (TA = 25'C Unless Otherwise Noted)'
y+ to Ground ................................................ + 17Y
Y- to Ground ................................................ -17V
YL to Ground .......................................... V+ to YLogic Control Yoltage ................................ V+ to VAnalog Input Yoltage ................................. Y + to YCurrent (any terminal) ................................... < SOmA
Operating Temperature:
(M Version) ......•.................. -55'C to + 125'C
(I Version) ............................. -20·C to +85'C
(C Version) .............................. O'C to + 70'C

Storage Temperature ...................... -65'C to + 160'C
Lead Temperature
(Soldering, 10sec) ..................................300·C
Power Dissipation:
CERDIP ............................................ .450mW
derate 4mWrC above 25'C
Plastic ............................................... 350mW
derate 3mWrC above 25°C

Stresses above those listed under" Absolute Maximum Ratings" may cause permanent. damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational Sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS
y+

=

+ l5V, Y-

= -15Y,

YL = +5Y, TA = 25'C unless otherwise noted.

MAXIMUM RATINGS
SYMBOL

PARAMETER

TEST CONDITIONS

TYP
@2S'C

M GRADE DEVICE

IIC GRADE DEVICE

-SS'C +2S'C + l2S'C -2S/0'C . + 25'C

V+

Supply Voltage
Ranges:
Positive Supply

VL

Logic Supply

V-

Negetive Supply
Sw~ch

ROS(on)

"ON"
Resistance
(Note 4)

ROS(on)

Switch "ON"
Resistance

AROS(on)

On Resistance
Match Between
Channels

VIH

Logical "1"
Input Voltage

VIL
10(off)
or
15(011)
10(on)
+
IS(on)

Logical "0"
Input VoIlI!ge
Switch 'OFF'
Leakage
(Note 2 and 4)
Sw~ch

'ON'
Leakage

UNIT

+851

+70'C

5 to 15
(NoteS)

5 to 15

V

-5 to
.-15
Is-lOrnA

IVo - ±5V

50

75

75

VIN2.4
V
<0.6
VS/0-±5V
VS/O" ±14V
VIN $0.8V

±1.0

50

±2.0

±1.0

50

±2.0

100

VS/0-±5V
VS/O - ±14V
VIN --~~<:r

L__ _

MDEO I.pun

DETAILED. DESCRIPTION
Figure 3 shows the internal circuit of one channel of the
IH5352. This is identical to the IH5341 "T-Switch" configuration. Here, a shunt switch is closed, and the two series
switches are open when the video switch channel is open or
off. This provides much better isolation between the input
and output terminals than a simple series switch does,
especially at high frequencies. The result is excellent offisolation in the Video and RF frequency ranges when
compared to conventional analog switches.

SWITCH
O--ODRAlI

(VIDEO OUTPun

I
LOGIC o - - - [ ) 4 - ; > o l
COmOL .'
-

I.PUT

.'

DIUVER
TRA.SLATOR
TC032601

The control input level shifting Circuitry is very similar to
'that of the IH5140 series of Analog Switches, and gives
very high speed, guaranteed "Break-BefOre-Make" action,
low static power consumption and TTL 'compatibility.

NOTE: 1 CHANNEL OF 4 SHOWN

Figure 3: Internal Switch Configuration

1000

1000

TIL
INPUT

+3V
OV
+3.3V

1000

VOUT
VANALOG = +5V

riv
OV

1000

Your
VAl!IALOG= --SV -3.3V
WF027401

~S"L
LOGIC CONTROL SIGNAl.
TC037301

Figure 4: Switching Time Test Circuit and Waveforms

3-146
Note: All typical values heve been guaranteed by characterization and are not tested,

5!
CI

IH5352

W
CI

N

750

RG·59 COAX

750

TC037411

VIN
OIRR = 20 LOG - VOUT
VIN

= 5V

pn SINEWAVE @ 10MHz

Figure 5: Off Isolation Test Circuit

IH5352
+5V
2

15

3

14

4

13

+15V VOUT1

750
VOUT2

750

5

-=

750

16

6

750

7

8

-=
-=

Too37501

CCRR = 20 LOG

~

VOUT

VIN = 225mV RMS SINEWAVE @ 10MHz

Figure 6: Cross-Coupling Rejection Test Circuit

3-147
Note: All typical values have been guaranteed by characterizatiOn and are not tested.

!

.O~OIl

IH5352

'10

-z

750

IH53S2

+5V
RQ.68COAX

NC

NC

RG·59 COAX .

18

VOUT

2

15

3

14

4

13

5

12

8

11

+15V

750

750

750

":"

-15V

7

NC

8

+5V

":"

'::"
TC037601

f - 3dB

~

FREQUENCY WHERE DC SWITCH
ATTENUATION IS DOWN 3dB
VIN = 225mV RMS@ 10-100MHz

Figure 7: Switch Attenuation -3dS Frequency Test Circuit

3-148
Note: All typical values have been guaranteed by characterization and are not lested.

IH6108
S-Channel CMOS
Analog Multiplexer
GENERAL DESCRIPTION

FEATURES

The IH6108 is a CMOS monolithic, one of 8 multiplexer.
The part is a plug-in replacement for the DG508. Three line
decoding is used so that the 8 channels can be controlled
by 3 Address inputs; additionally a fourth input is provided
for use as a system enable. When the ENable input is high
(5V), a channel is selected by the three Address inputs, and
when low (OV) all channels are off. The 3 Address inputs
are TTL and CMOS logic compatible, with a "1" corresponding to any voltage greater than 2.4V.

•
•
•
•
•
•
•
•
•

Ultra Low Leakage - IO(Off):::: 100pA
rOS(on) < 400 Ohms Over Full Signal and
Temperature Range
Power Supply Quiescent Current Less Than
100jJA
±14V Analog Signal Range
No SCR Latchup
Break-Before-Make Switching
Binary Address Control (3 Address Inputs
Control 8 Channels)
TTL and CMOS Compatible Strobe Control
Pin Compatible With DG508, HI-508 & AD7508

ORDERING INFORMATION
PART NUMBER

TEMPERATURE RANGE

PACKAGE

IH6108MJE

-SS·C to + 12S·C

16 pin CERDIP

IH6108CJE

O·C to 70·C

16 pin CERDIP

IH6108CPE

O·C to 70·C

16 pin plastic DIP

Ceramic package available as special order only (IH6108MDE/CDE)

DECODE TRUTH TABLE

S. 0

CV"""""

S. 0

CV"""""

0

CV"""""

VOUT
D

A1
x
0
0

1
1

0

1
1

1

1
1

0
1

Ao
x
0
1
0
1
0
1
0
1

EN
0

1
1
1
1
1
1

ON SWITCH
NONE
1
2
3

4
S
6
7
8

1

1

AO, A1, A2

EN
SWITCH

S. ~

A2
x
0
0
0
0

Logic "1" = VAH::: 2.4V VENH::: 4.SV
Logic "0" = VAL:::: 0.8V

Sa

S. ~
S.

~

AD

A.

A.

EN (ENABLE INPUT)
c0003411

3 LINE BINARY ADDRESS INPUTS
(1 0 1) AND EN @ SV
ABOVE EXAMPLE SHOWS CHANNEL 6 TURNED ON'

Figure 2: Pin Configuration

LDD0231 I

Figure 1: Functional Diagram

3-149
Note: All typical values have been guaranteed by characterization and are not tested.

305530-002

IIU~UIl

IH61("~
ABSOLUTE MAXIMUM RATINGS
VIN (A, EN) to Ground .......................... -15V to 15V
Vs or Vo to V+ ......................................... 0, -32V
Vs or Vo to V- ..........•................................ 0, 32V
V+ to Ground ................................................. 16V
V- to Ground ....... ~ . .'...................................... -16V
Current (Any Terminal) .................................. ~. 30mA

Current (Analog Source or Drain) ...................... 20mA
Operating Temperature ......................... -55 to 125°C
Storage Temperature .......................... ;·. -65 to 150°C
Lead Temp (SOldering, 10sec) .......................... 300°C
Power Dissipation (Package)· ....................... 1200mW
'All leads soldered or welded to PC board. Derate 10mW/'C above 70'C.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and lunctional
operation 01 the device at these or any other conditions above those indicated in the operational sections 01 the specilications is not implied. Exposure to
absolute maximum rating conditions lor extended peri()(js may allect device reliability.

ELECTRICAL CHARACTERISTICS
V+

= 15V,

V - :, ...: 15V, VEN

= + 5'1

MEASURED
TERMINAL

CHARACTERISTIC

(Note 1), Ground = OV, unless otherwise specified.
MAX LIMITS

NO
TES!5 TYP
PER 25'C
TEMP

TEST CONDITIONS

M SUFFIX

C SUFFIX

UNIT

-SS'C 2S'C 12S'C O'C 2S'C 70'C

SWITCH
S to D

rOS(ON)

8

180

Vo = 10V, Is = -1.0mA Sequence each switch on

8

150

Vo=-10V,IS=-1.0riJA VAL
"rOS(on) =

20

arOS(ON)

t.rOS(on)min
rOS(on)avg.

VAH = 2.4V

300

300

400

350

350

450

300

300

400

350

350

450

0.002 Vs = 10V, Vo = -10V

±.5

50

±1

8

0.002 Vs = -10V, Vo -10V

±:5

50

±1

50

1

0.03

±2

100

±5

100

1

0.03 Vo = -10V, Vs = 10V

±2

100

±5

100

8

0.1

VS(ALL) - Vo - 10V

Sequence each switch on

±2

100

±5

100

8

0.1

VSIALLl = Vo = -10V

VAL = 0.8V, VAH = 2.4V

±2

100

±5

100

AI or A2

3

0.01

VA - 2.4V or OV

-10

-30

-10

-30

Inputs

3

0.01

VA=15V or OV

10

30

10

30

-10

-30

-10

-30

-10

-30

-10

-30

10(OFF)

D

1010N) .

D

Vo = 10V, Vs = -10V

VEN =0.8V

.11
%

Vs = ± 10V

8
S

IS(OFF)

= 0.8V,

50
nA

INPUT

Ao,

IAN(ON) or IA(on)
IAN(OFF) IA(off)

Ao,
IA

p.A

AI

A2

3

VEN = 5V

EN

1

VEN=O

All VA = 0 (Address
pins)

DYNAMIC
ttransition

D

0.3

See Fig. 1

Iopen

D

0.2

See Fig. 2

Ion(EN)

D

0.6

See Fig. 3

Ioff(EN)
"OFF" Isolation

0

0.4

D

60

VEN = 0, RL = 200.11, CL = 3pF, Vs = 3VRMS,
f = 500kHz

S

5

Vs=O

Cd(off)

D

25

Vo=O

D to S

1

Supply

+

v+

1

40

Current

-

V-

I

2

Standby

+

V+

1

1

Current

-

V-

I

1

1.5

p.s

1

Cs(oll)

COSloff)
SUPPLY

1

dB

VEN = OV, I = 140kHz to
lMHz

pF

Vs=O, Vo= 0

VEN = 5V
All VA=O or 5V
VEN=O

NOTE 1: See Enable Input Strobing Levels, in Application Section.

3-150
Note: All typical values have been guaranteed by characterization and are not tested.

200

1000

100

1000

100

1000

100

1000

p.A

IM6108
SWITCHING INFORMATION
VA
tr < l00ne
•• <

l00nl

3V

O.aV----jt---5O'Io---\'-ltrans(8-1)

- - -.... +10V
Your
VSl = +10Y

Vs. = -10V

ttrans(l-B)

i-,..=;.;-9!lV!....._¥ -10V
t--S8 ON...-j

t--510N---l

1--580N--

l--J.~=T+i9itv;--11+10V
trans (1-8)

Your'

Vs, = -10V
Vsa = +10V
_ _ _...I-l0V
ttrans(8-1)

TGOOSeOI

WFOO3401

PROBE IMPEOANCE
Rp ~ 1Mil

Cp $ 30pF

Figure 3: ttransltlon Switching Test

3V

+15V

r--~W!,-",,~--o-2V

L-~
VA

____~__J=~=i::~:r~VOUT

~~'00n. ~

If < 100n,

O.8V

o; ;.a~V

\ " '_ _ _ _

Your vs, = -2V
51 ON

35pF

TC008701
WF003501

Figure 4: t open (Break-Before-Make) Swltchi!1g Test

3-151
Note: All typical values have been guaranteed by characterization and are not tested.

,,,<

YEN

100...
If < 100...

'+1sv

r----.-.j,o.",;l-~~--_o VSI
IH6108

L.,....___r-<>-'-r-=-T~Your,

O.IV

Your OV

35pF

VEN

rCOO88Ot

WFOO3601

Figure 5: ton and toff Switching Test

IH6108 APPLICATION INFORMATION
ENable Input Strobing Levels
The ENable input on the IHp10S requires a minimum of

+ 4:5V to trigger to the" 1" state and a maximum of + O.SV
~o

trigger to the "0" state. If the ENable input is being driven
from TTL logic, a pull-up resistor of 1k to 3kn is required
from the gate output to + 5V supply. (See Figure 6)

+5V lKn

DM7404N

TTL LOG,IC

+3V

11

.2l!I"1...

VOUT
AFo05101

Figure 6: ENable Input Strobing from TTL Logic
When the EN input is driven. from CMOS logic, nopullup is necessary, see ,Fig. 7.

3-;.152

Note: All typical values have been guaranteed by characterization and are not tested.

IH6108
IH6108 APPLICATION INFORMATION (CONT.)
+5V

AFOO520t

Figure 7: ENable Input Driven from CMOS Logic
supply voltages decrease, however, the multiplexer error
term (the product of leakage times rOS(on» will remain
approximately constant since leakage decreases as the
supply voltages are reduced.

The supply voltage of the CD4009 affects the switching
speed of the IH6108; the same is true for TTL supply
voltage levels. The following chart shows the effect, on
ttrans for a supply varying from +4.5V to +5.5V.
CMOS OR TTL
SUPPLY VOLTAGE
+4.5V
+4.75V
+5.00V
+5.25V
+5.50V

Caution must be taken to ensure that the enable (EN)
voltage is at least 0.7V below V + at all times. If this is not
done, the Address input strobing levels will not function
properly. This may be achieved quite simply by connecting
EN (pin 2) to V + (pin 13) via a silicon diode as shown in
Figure 8. When using this type of configuration, a further
requirement must be met: the strobe levels of AO and A 1
must be within 2.5V of the EN voltage in order to define a
binary "1" state. For the case shown in Figure 8 the EN
voltage is 11.3V which. means that logic high at AO and A 1
is = +8.8V(logic low continues to be = 0.8V). In this
configuration the IH6108 cannot be driven by TTL (+ 5V) or
CMOS (+ 5V) logic. It can be driven by TTL open collector
logic or CMOS logic with + 12V supplies.

TYPICAL ttrans
@ 25°C
400ns
300ns
250ns
200ns
175ns

The throughput rate can therefore be maximized by using
a + 5V to + 5.5V supply for the ENable Strobe Logic.
The examples shown in Figures 6 and 7 deal with ENable
strobing when expansion to more than eight channels is
required. In these cases the EN terminal acts as a fourth
address input. If eight channels or less are being multiplexed, the EN terminal can be directly connected to + 5V
logic supply to enable the IH6108 at all times.

If the logic and the IH6108 have common supplies, the
EN pin should again be connected to the supply through a
silicon diode. In this case, tying EN to the logic supply
directly will not work since it violates the 0.7V differential
voltage required between V + and EN, (See Figure 9). A
11lF capaCitor can be placed across the diode to minimize
switching glitches.

Using the IH6108 with supplies other than
±15V
The IH6108 can be used with power supplies ranging
from ±6V to ±16V. The switch rOS(on) will increase as the

3,-153

Note: All typical values have been guaranteed by characterization and are not tested.

I.... IH610S

I

-

IH&108 APPLICATION INFORMATION (CONT.)

AFOO5301

Figure 8: IH6108 Connection Diagram for less than ± 15V Supply Operation

1N914 OR ANY SILICON DIODE

CDOO3901

Figure 9: IH6108 C~nnection Diagram with ENable Input Strobing for less than ±15V Supply
Operation

Peak-to-PeakSignal Handling Capability

The electrical specifications of the IH6.108 are guaranteed for ±1OV signals, but the specifications have very
minor changes for ±14V signals. The notable changes are
slightly lower rOS(on) and slightly higher leakages.

The IH6108 can handle input signals up to ± 14V (actually
-15V to + 14.3V because of the input protection diode)
when using ± 15V .supplies.

:r-154
Note: All typical values have been guaranteed by characterization and are not tested.

IH6116
16-Channel
CMOS Analog Multiplexer
'GENERAL DESCRIPTION

FEATURES

The IH6116 is a CMOS monolithic, one of 16 multiplexer,
The part is a plug-in replacement for the DG506. Four line
binary decoding is used so that the 16 channels can be
controlled by 4 Address inputs; additionally a fifth input is
provided to be used as.a system enable. When the ENable
input is high (5V) the channels are sequenced by the 4 line
Address inputs, and when low (OV), all channels are off. The
4 Address inputs are controlled by TTL logic or CMOS logic
elements with a "0" corresponding to any voltage less than
0.8V and a "1" corresponding to any voltage greater than
2.4V. Note that the ENable input must be taken to 5V to
enable the system and less than 0.8V to disable the system.

•
•
•
•
•
•
•
•
•
•

Pin Compatible With DG506, HI-506 & AD7506
Ultra Low Leakage - 10(Off)::: 100pA
± 11 Analog Signal Range
rOS(on) < 700 Ohms Over Full Signal and
Temperature Range
. Break-Before-lIIIake' Switching
TTL and CMOS Compatible Address Control
Binary Address Control (4 Address' ,,,,puts
Control 16 Channels)
Two Tier Submultiplexlng to Facilitate
.
Expaildability
Power Supply Quiescent Current Less Than
1001lA
No SCR Latchup

ORDERING INFORMATION
PART NUMBER
IH6116MJI
IH6116CJI
IH6116CPI

TEMPERATURE RANGE
-55·C to + 125·C
O·C to 70·C
O·C to 70·C

PACKAGE
28 pin CERDIP
28 pin CERDIP
28 pin Plastic DIP
IH6116MDIICDI
DECODE TRUTH TABLE
EN
ON SWITCH
A1
Ao
X
X
0
NONE
1
1
0
0
0
0
1
1
2
0
0
1
0
1
3
0
1
1
1
4
0
0
0
0
1
5
0
1
1
1
0
1
0
6
0
1
0
1
7
1
0
1
1
1
1
8
1
0
0
9
1
0
0
1
1
10
1
0
1
1
0
1
11
0
1
1
1
12
1
0
0
1
13
1
1
0
1
1
1
1
0
14
1
1
1
0
1
15
1
1
1
1
1
16
LogiC "1" = VAH ~ 2.4V VENH ~ 4.5V
Logic "0" = '(Al ::: O.SV
.
A3
X
0

..

h~=LI··

L~~~:fL~.
811~
.12~

.

~ ~.

,

'VOU"OI

.

.,.~

81$~

SI.~·

A2
X
0

y+
He a

TO DECODE LOGIC '
CONTROLUNG BOTH
TIER,"OF MUXING'

~

.,
H"
" ..
.
. ..

DeVOUl)

27

N.C 3

V-

...

.."...,. ..
" ,

"OS

..

1181

810 "

,. EN

SO"

,

....

GNO 12

.. A,

"""

1542
TOPYIEW

4 LINE BINARY ADDRESS INPUTS
0 0 1)ANDENQ.t5V
ABOVE EXAMPLE SHOWS CHANNEL' TURNED ON

yTCOMMON TO SUBSTRATE

(0

C0OO3501

Figure 2: Pin Configuration

LOOO2401

Figure 1: Functional Diagram

3-155
Note: All typical values have been guaranteed by characterization and are not t

YOUT

-15V

+15V

D2

82

TTL OR

-:

CMOS

1H6116

INVERTER

-:
EN

V2
-15V

VA

S32

S"

""

-TTL .... 'mu•• ha.,e
pullup mlstor 10 + 5V to drive EN Inputs
AFOO5601

DECODE TRUTH TABLE
A4

A3

A2

A1

Ao

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
1
1
0
0
1
1
0
0
1
1

DECODE TRUTH TABLE

ON SWITCH
81
82
83
54
85
86
87
88
89
810
811
812
813
814.
815
816

A4

A3

A2

A1

Ao

ON SWITCH

1
1
1
1
1
1
1
1
1
1
1
1·
1
1
1
1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
'1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832

Figure 7: 1 Out of 32 Channel Multiplexer U~ing 2 IH6116s; Using

3-159
Note: All typical values have been guaranteed by characterization and are not tested.

0
0
0
0
1
1
1
1

An IH5041 for Submultiplexing

C)

i

IH6116
IH6116 APPLICATIONS (CONT.)

V,
~15V

i

J
Ao
A,
A2

-

IHl111
lOUT OF "

A3

I
I

....

,

1

l

I

'~7

i

I"

n

41 1,1

1 1 I ~LJoIIIII~Jsl I I I

Do

~

~

03

I
I

11113

~~

.
I

IH111.
1 OUT OF "
MUX

EIilABLE

I

IH5053

~

<'2
A3

1

I I

331 I I 1 I ~~LJo IIN~U~sl I I I 1·1

~

mUI' have
,..I.tor to ctrive EN InpPoIti
....'r..TLuplat.

f--O-t>-l

J.,

IH111.
1 OUT OF "
MUX

A3
j!NA8LE

1
~

~lLOGIIIIILU~11

Ao
A,
A2

I

1

.J

IHe11e
1 OUT OF "
MUX

111 I I I I

0,

I

1111,

....!!!

A3
INA...

...

S.!-,.I
I

11 I I I I JJL~IIN~U~I I I I 1"

Ao
A,
A2

I

~

MUX

INAILE

I

1M

~"

D.

JV2
-l$V
AFOO5701

Figure 8: 1 Out of 64 Multiplexer Using 4 1/16s and IH5053 As Submultiplexer
~eneral note on expandabillty of IH6116
The IH6116 is a two tier multiplexer, where sixteen input
channels are routed to a common output in blocks of 4.
Each block of 4 input channels is routed to one common
output channel, and thus the submultiplexed system looks
like 4 blocks of 4 inputs routed to 4 different outputs with
the 4 outputs tied together; Thus 20 switches are needed to
handle the 16 channels of information. The advantage of
this is lower output capacitance and leakage than would be
possible with a system using all 16 channels tied to one
common output. Also the expandability into 32, 64, 128,
channels etc. is facilitated. Figures 6,7, and 8 show how the
IH6116 can be expanded.
Figure 6 shows a 1 of 32 multiplexer, using 2 IH6116s.
Since the 6116 is itself a 2 tier MUX, the system as shown is
basically a 2 tier system. The four output channels of each

6116 are tied together so that 8 channels are tied to the
VOUT common pOint. Since only one channel of information
is on at a time, the common output will consist of 7 OFF
channels and 1 ON channel. Thus the output leakage will
correspond to 7 10(ofts) and 1 10(on), or about 1.0nA of
typical leakage at room temperature. Throughput speed will
be typically 0.81lS for. ton andO.3~s for toft. Throughput
channel resistance will be in the 500n area.
Figure 7 shows the 1 of 32 MUX of Figure 6, with a third
tier of submultiplexing added to further reduce leakage and
output capacitance. The IH5041 has typical ON resistances
of 50n (max. is 75n) so it only increases thruput channel
resistance from the 500 ohms of Figure 6 to about 550
ohms for Figure 7. Throughput channel speed is a little
slower by about 0.5~s for both ON and OFF time, and
output leakage is about 0.2nA.
3-t60

Note: All typical values have been guaranteed by characterization. and are not

test~.

.O~OlL

IH6116
Figure B shows a 1 of 64 MUXusing 3 tier MUXing
(similar to Figure 7). The Intersil IH5053 is used to get the
third tier of MUXing. The VOUT point will see 3 OFF
channels and 1 ON channel at anyone time, so that the
typical leakages will be about 0.4 nA. Throughput channel
resistance will be in the 550 ohm area with throughput
switching speeds about 1.3J.1s for ON time and O.BJ.IS for
OFF time.
The IH5053 was chosen as the third tier of the MUX
because it will switch the same AC signals as the IH6116
(typically plus and minus 15V) and uses break before make
switching. Also power supply quiescent currents are on the
order of 1-2/lA, so that no excessive system power is
dissipated. Note that the logic of the 5053 is such that it can
be tied directly to the ENable input (as shown in the figures)
with no extra circuitry being required.

the low state. When using TTL logic, a pull-up resistor of
1kn or less should be used to pull the output voltage up to
5V. When using CMOS logic, the high state goes to the
power supply so no pull-up is required.
If used on high voltage logic supplies, EN should be at
least 0.7V below V + at all times. See IH610B data sheet for
details.

APPLICATION NOTES
Further information may be found in:
AOO3 "Understanding and Applying the Analog Switch,"
by Dave Fullagar
A006 "A New CMOS Analog Gate Technology," by Dave
Fullagar
A020 "A Cookbook Approach to High Speed Data
Acquisition and Microprocessor Interfacing," by Ed
Slieger
ROOe "Reduce CMOS Multiplexer Troubles Through
Proper Device Selection," by Dick Wilenken

Enable input strobing levels
The enable input (EN) acts as an enabling or disablihg pin
for the IH6116 when used as a 16 channel MUX. However,
when expanding the MUX to more than 16 channels, the EN
pin acts as another address input. Figures 6 and 7 show the
EN pin used as the A4 input.
For the system to function properly the EN input (pin 1B)
must go to 5V ±5"1o for the high state and less than O.BV for

NOTE: This multiplexer does not require external resistors
and/or diode.s to eliminate what is commonly known as a
latch up or SCR action. Because of this fact, the rOS(ON) of
the switch is maintained at specified values.

3-161
Note: All typical values have been guaranteed by characterization and are not tested.

i...

a

g 1'146201

!

Dual CMOS
Driver Iyoltag~ .Translator
GENERAL DESCRIPTlON

FEATURES

The IH6201 is a CMOS; Monolithic, Dual Voltage Trarislator; it takes low level TTL or CMOS logic signals and
converts them to higher levels (i.e. to ±15V swings). This
translator is typically used in making solid stilte switches, or
analog gates.
Wheli used in conjunction with the IntersillH401 family· of
Varafets, the combination makes a complete solid state
switch capable of switching signals up to 22Vpp and up to
20MHz in frequency. This switch is a "break·before,make"
type (i.e. loft time < Ion time). Tile combination has typical
loft "" 80ns and typo ton"" 20()ns fqr signals. up to 20Vpp in
amplitude.
A TTL "1" input strobe will force. the (J driver output up to
V+ level; the lJ output will be driven down .to the V- level.
When the TTL input goes to "0", the (J output goes to Valid 'lJ goes to V +; thus (J and lJ are 18Qo out of phase with
each other. These complementary outputs can be used to
create a wide variety of functions such asSPDT and DPDT
switches, etc.; alternatively the complementary outputs can
be used to drive Nand P channel MOSFETs, to make a
complete CMOS analog gate.
The driver typically uses + 5V and ± 15V power supplies,
however a wide range of V + and V- is also possible. It is
necessary that V + > 5V for the driver to wprk properly,
however.

•
•
•

-5V

DRIVER
OUTPUT

J---.,
'---_ii,

Driven Direct From TTL or CMOS logic
Translates _Logic Levels Up to 30V Levels
Switches 20VACPP Signals When Used in
Conjunction With Intersil IH401A Varafet (As An
,Analog Gate)
• tON::S 300ns & tOFF::S 200ns for ~OV Level Shifts
• Quiescent Supply Current::s 1001lA for Any State
(D.C.)
• Provides Both Normal & Inverted Outputs

ORDERING INFORMATION
PART NUMBER

TEMPERATURE RANGE

*IHe201CDE

ooe to 70 0 e

"IH6201MDE

-55°e _ + 125"e

IH6201CJE

ooe to 70 0 e

IH6201MJE

-55°e to t25°e

IH6201ePE

ooe to 70 0 e

"SpeCial Order Only

.,

.

"

80000201

Figure 1: Functional Diagram

,.

DRIVER
OUTPUT

•

LOGIC
STROBE

TTL INPUT 1

y-

OND
+5V

1

rll E:-...J

v+

DRIVER
OUTPUT

•

TTL INPUT 2
82 •
COOOO601

(Outline dwgs DE,JE,PEl
V-

Figure 2: Pin Configuration

05003001

Figure 3: Schematic Diagram (One Channel)

3-162
Note: All typical values have been guaranteed by characterization and are not tested:

IH6201
ABSOLUTE MAXIMUM RATINGS
y+
y+
Yy+

to Y- .......................................................
................................................................
................................................................
to YIN ......................................................

35Y
35Y
35Y
40Y

Operating Temperature ............... ,... -55°C to +125°C
Storage Temperature ...................... -65°C to + 150°C
Lead Temperature (Soldering, 10sec) ....•............ 300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions lor extended periods may affect device reliability.

ELECTRICAL SPECIFICATIONS

y+ = +15Y,

v-

= -15V, VL= +5V
IH6201CDE

ITEM
8 or

71

driver output swing

IH6201MDE

TEST CONDITIONS
VIN

= OV .I1..

-2S'C

+2S'C

-SS'C

28

+2S'C

UNIT

+12S'C

28

Vpp

VIN strobe level ("1")lor
proper translation

8~ 14V
Ii~ -14V

3.0

3.0

3.0

2.4

VO.C.

VIN strobe level ("'O")for
proper translation

8 ~ -14V
11~ 14V

0.4

0.4

0.4

0.8

Vo.C.

liN input strobe current draw
(for OV - 5V range)

VIN

±1

±1

10

ton time

VIN = OV .I1.. CL = 30pF
switching turn-on time lig. 58

400

300

ns

toff time

VIN = OV .I1.. CL = 30pF
switching turn-off time fig. 58

300

200

ns

I + (V +) power supply
quiescent current.·

VIN=OVor +5V

100

100

100

100

100

100

IlA

1- (V -) power supply
quiescent current

VIN = OV or + 5V

100

100

100

100

100

100

p.A

IL (vLl power supply
quiescent current

VIN=OVor +5V

100

100

100

100

100

100

p.A

= OV

+ 3V Fig. 58

+8S'C

or +5V

±1

±1

10

IlA

APPLICATIONS
ral" resistor is normally in the 1OOkSl to 1Mil range and is
not too critical.

Input Drive Capability
The strobe input lines are designed to be driven from TTL
logic levels; this means O.BV to 2.4V levels max. and min.
respectively. For those users who require O.BY to 2.0Y
operation, a pull-up resistor is recommended from the TTL
. output to + 5V line. This resistor is not critical and can be in
the 1kil to 10kil range.

, . . - - - - , SIGNAL INPUT
+3V

~

When using 4000 series CMOS logic, the input strobe 'is
connected direct to the 4000 series gate output and no pull
up resistors, or any other interface, is necessary.

REFERRAL
RESISTOR

TTL INPUT ---~
SWITCH
OUTPUT

RL

When the input strobe voltage level goes below Gnd (i.e.
to -15Y) the circuit is unaffected as long as y+ to YIN does
not exceed absolute maximum rating.

TC009201

Figure 4

Output Drive Capability
The translator output is designed to drive the Intersil
IH401 family of Yarafets; these .are N-channel JFETS with
built-in driver diodes. Driver diodes are necessary to isolate
the signal source from the driver!translator output; this
prevents a forward bias condition between the signal input
and the + Yee supply. The IH6201 will drive any JFET
provided some sort of isolation is added i.e.

Making a Complete Solid State Switch That
Can Handle 20Vpp Signals
The limitation on signal handling capability comes from
the output gating device. When a JFET is used, the pinchoff of the JFET acting with the V- supply does the limiting.
In fact max. signal handling capability = 2 (Vp + (V-n Vpp
where Yp = pinch-off voltage of JFET chosen. Le. Vp = 7V,
V- = -15Y :. max. signal handling = 2 (7Y + (-15Y))
Vpp = 2(7Y-15)pp = 2(-'BVpp) = 16Ypp. Obviously to
get;:: 20Ypp, Vp ;:: 5V with Y- = -15Y. Another Simple way
to get 20Vpp with Vp=7V, is to increase V- to -17V. In
fact using V + = + 12V or + 15V andsatting V - = -1 BV

You will notice in Figure 4 that a "referral" resistor has
been added from 2N4391 gate to its source. This resistor is
needed to compensate for the inadequate charge area
curve for isolation diode (Le. if C vs. Y plot for diode ~ 2 [C
vs. Y plot for output JFEn switch won't function; then
adding this resistor overcomes this condition. The "refer3-163

Note: All typical values have been guaranteed by characterization and are not tested.

i
I

lH8201·
APPLICATIONS (CONT.)

NOTE: Each translator output has a 8 and II output. 8 is just
the inverse of lI.

allows one to switch 20Vpp with any member of IH401
family. The advantage of using the Vp = 7V pinch-off (along
with unsymmetrical supplies), over the VP"= 5V pinch-off
(and ± 15Vsupplies), is that you will have· a much lower
ROS(ON) for the Vp = 7 JFET (i.e. for the 2N4391).
TOS(ON) ~ 22n,
rOS(ON) "~ 35n)
Vp '" 7V
Vp = 5V

A very useful feature of this system is that one-half of an
IH6201 and one-half of an IH401 can combine to make a
SPOT switch, or an IH6201 plus an IH401 can make a dual
SPOT analog switch. (See Figure 8)

The IH6201 is a dual translator, each containing 4 CMOS
FETs pairs. The schematic of one-half IH6201, driving onequarter of an IH401, is shown in Figure 5A.

,----1

,. . ,

......

L-

';:~:1
INPUT

STROlE

I
I

I
I

I

I

I

.,.

DSOO3201

I

S

Figure 6: Dual SPST Analog Switch

I

L.!A-"-~E_J

GNO
,

VL

+1SV

+5V

--ov,

-15V
TRANSLATOR
08003101

Figure 5A
08003301

Figure 7: DPDT Analog Switch
NOTE: Either swHch Is turned on when strobe input goes high. .

1 - - - ." - - - I

+15V

b-15V~
I
I
I

I
I
I

I
I

T15Y.Lr'
-15V.

08000401

Figure 8: Dual SPDT

W~I

Figure5B
3-164
Note: All typical values have been guaranteed by characterization and" are not tested.

IH6201
APPLICATIONS (CO NT.)

08003501

Figure 9: Dual DPST

, 3-165
Note: All typical values have been guaranteed by characterization and are not tested.

r;! 1"6208
zI 4-Channel Differential

"- CMOS Analog Multiplexer
GENERAL DESCRIPTION

FEATURES

ThtllH6208 is a monolithic 2 of 8 CMOS multiplexer. The
part is a plug-in replacement for the DG509. Two line binary
decoding is used so that the 8 channels can be controlled in
pairs by the binary inputs; additionally a third input is
provided to use as a system enable. When"the ENable input
is high (5V) the channels are sequenced by the 2 line binary
inputs, and when low (OV) all channels are off. The 2
Address inputs are controlled by TTL logic or CMOS logic
elements with a "0" corresponding to any voltage less than
0.8V and a "1" corresponding to any voltage greater than
2.4V. Note that the ENable input must be taken to 5V to
enable the system, and less than 0.8V to disable the
system.

•
•
•
•
•
•
•
•
•

Ultra Low Leakage - 10(off) ~ 100pA
rOS(on) < 400 Ohms Over Full Signal and
Temperature Range
Power Supply' Quiescent Current Less Than
100pA
±14V Analog Signal Range
No SCR Latchup
Break-Before-Make Switching
Binary Address Control (2 Address Inputs
Control 2 Out of 8 Channels)
TTL and CMOS Compatible Address Control
Pin Compatible With H1509, DG509 & AD7509

ORDERING INFORMATION
PART NUMBER

TEMPERATURE RANGE

PACKAGE

IH6208MJE

-55°C to + 125°C

16 pin CERDIP

IH6208CJE

O°C to 70°C

16 pin CERDIP

IH6208CPE

O°C to 70°C

16 pin Plastic DIP

Ceramic package available as special order only (lH6208MDE/CDE)

DECODE TRUTH TABLE

S1.o--~--..,

Al

Ao

EN

ON
SWITCH
PAIR

X

X

0
0
1
1

0
1
0
1

0
1
1
1
1

NONE
1a, 1b
2a,2b
3a,3b
4a,4b

EN SWITCH
I

'--~)__.;-:..-0----.1.... D,
I
I

Ao,

.--~)__.;-I..-0----.1.... D,

Al
LOGIC" 1" = VAH ? 2.4V VENH ? 4.5V
LOGIC "0" = VAL::; 0.8V

S1bo--~---,

EN

GND

v-

v+
S1b
S2b

S4a

Ae

At

EN

COO03701

Figure 2: Pin Configuration"

2 LINE BINARY ADDRESS INPUTS
(0 0) AND EN "I' SV (EN ...., .. fOR ... 5V. ''0'' FOR 0\11
ABOVE EXAMPLE SHOWS CHANNELS ,. I: 1b ON.
LDOO250\

Figure 1: Functional Di~gram

3-166
..

Note: All typical values have been guaranteed by characterization and are not tested.

IH6208
ABSOLUTE MAXIMUM RATI,NGS
Current (Analog Source or Drain) ...................... 20mA
Operating Temperature ......................... -55 to 125'C
Storage Temperature ................... , ........ -65 to 150'C
Lead Temp (Soldering. 10sec) ...... , ................... 300·C
Power Dissipation (Package» ....................... 1200mW

VIN (A. EN) to Ground ............................... -15V. V1
Vs or Vo to V+ ......................................... 0. -32V
V~ or Vo to V- ............................................ 0. 32V
V to Ground ................................................. 16V
V- to Ground ................................................ -16V
Current (Any Terminal) .................................... 30mA

*Allieads soldered or welded to PC board. Derate 10mW/'C above 70·C.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
v+ = 15V. v- = -15V. VEN = +5V (Note 1). Ground = OV. unless otherwise specified.
MAX LIMITS

NO
MEASURED
TERMINAL

CHARACTERISTIC

~~

TYP
25·C

M SUFFIX

TEST CONDITIONS

TEMP

C SUFFIX

UNIT

- ~'C 25·C 125·C O·C 25·C 70·C

SWITCH
S to D

rOS(ON)

8

180

Vo -10V, Is - -1.0mA!Sequence each switch on

300

300

8

ISO

Vo=-10V,ls--l.DmAVAL=0.8V. VAH=2.4V

300

300

20

ArOS(ON)

"ros(on) =

''DS(on)max-rOS(on)min

400
400

3S0

3S0

4S0

3S0

350

450

n
%

Vs = ±IDV

rOS(on)aYg·
S

IS(OFF)

8

0.002 VS-l0V, Vo- -10V

±.S

50

±1

8

0.002 Vs= -10V, Vo=10V

±.S

SO

±1

50

2

0.03 VO-l0V, Vs= -10V

±2

SO

±5

100

±2

50

±5

100

VEN -0.8V

50

IO(OFF)

D

2

0.03 Vo - -10V, Vs = 10V

8

0.1

VS(ALLj = Vo = 10V

Sequence each switch on

±2

50

±S

100

IOtON)
INPUT

D

8

0.1

VstALL) - -10V

VAL=0.8V, VAH= 2.4V

±2

50

±S

100

IA(on)

2

0.01

VA = 2.4V or OV

-10

-30

-10

-30

IA(off)

2

0:01

VA-15V or OV

10

30

10

30

-10

-30

-10

-30

-10

-30

-10

-30

IA

Ao; At
EN

2

VEN-SV

1

VEN-O

All VA=O
(Address Pins)

nA

p.A

DYNAMIC

SSe Fig. 3
SSe Fig. 4
SSe Fig. 5

ttransilion

D

0.3

\open

D

0.2

tEN(on)

D

0:6

tEN(off)
"OFF" Isolation

D

0.4

D

60

VEN - 0, RL f = 500kHz

1
I.S

2OOn,

Cs(off)

S

5

VS=O

Cd(off)

D

12

VO-O

CIoS

1

Vs - Q, Vo = 0

CdS/offl
SUPPLY
Supply

+

v+

1

40

Current

-

V-

I

2

Standby

+

v+

1

1

Current

-

V-

I

1

'j./S

t
dB '

CL - 3pF, Vs - 3VRMS,

VEN lMHz

av, f =140kHz to

VEN -5V
AIIVA=00r5V
VEN-O

NOTE 1: See Section 1 Enable Input Strobing Levels.

3-167
Nota: All typical values have been guaranteed by characterization and 'are not tested.

pF

200

1000

100

1000

100

1000

100

1000

p.A

B rH6208

=

! SWITCHING INFORMATION
a.ov
1.4V

O.IV

1----'1

O~------~--~--------+_---------

Vs,. I - - - - - t

VA

G.tvs,.

'S4b

10V

IH6208
G4-------~~------~--+_~~-----

O.tvs.
VS4b
PROBE IMPEDANCE

Ap" lMn
CP" 30pF
WF0Q4101

'

TC009301

Figure 3: ttrans Switching Test

VA

,I

.'
______+3.0V
§l%_____-'l

+15V

~

SWITCH OUTPUT

1

J-,
~~~TFIG.2) ~~'A

-::fVs~

'

tope,n

,,'------

~~~_

3t

r--......"1-~~---2V

L""__"'TJ~:Fr.=:l:::VOUT
35pF

Tooo9401

WFOO421t

Figure 4: t open (Break-Before-Make) Switching Test

+15V
IEN(oH)

~~--~--~-t---------t---b~---­

G.Wo

r - -..............~---o ..

V

VOUT

SWITCH OUTPUT
(SEE FIG. a)

35pF

TCOO9501

WF004301

Figure 5: ton and toff Switching Test

3,-168
Note: All typical values have been guaranteed by characterization and l\I"e, n,ot tested.

IH8208
IH6208 APPLICATION INFORMATION

ENable Input Strobing Levels
The ENable input on the IH620B requires a minimum of

+ 4.SV to trigger it into the "1" state and a maximum of
+ O.BV to trigger it into the "0" state. If the ENable input is
being driven from TTL logic, a pull-up resistor of 1k to 3kn
is required from the gate output to + SV supply. (See Figure
6).

1K

+3V
1~

TC009601

Figure 6: ENable Input Strobing From TTL Logic
When the EN input is driven from CMOS logic, no pullup is necessary. (See Fig. 7)

+5V

TC009701

Figure 7: CMOS Logic Driving ENable Pin

3-169
Note: All typical values have been guaranteed by characterization and are not tested.

I IH6208

i

IH6208 APPLICATION INFORMATION (CONT.)
The supply voltage of the CD4009 affects the switching
speed of the IH620S; the same is true for TTL supply
voltage levels. The chart below shows the effect on ttrans
for a supply varying from +4.5V to +5.5V.
CMOS OR
TTL SUPPLY

TYPICAL ttrans
@ 25°C

+4.5V
+4.75V
+5.0V
+5.25V
+5.50V

400ns
300n5
250ns
200ns
175ns

supply voltages decrease, however, the multiplexer, error
term (the product of leakage times r05(on») will remain
approximately constanf,since leakage decreases as the
supply volta,ges are,' reduced.
caution must betaken to ensure that the enable (EN)
voltage is at least O.7V below V+ at all times. If this is not
done the Address Input strobing levels will not function
properly. This may be achieved quite simply by cpnnecting
EN (pin 2) to V+ (pin 14) via a silicon diode as shown in
Figure 8. A further requirement must be met when using this
type of configuration; the strobe levels at AO and A1 must
be within 2.5V of the EN voltage in order to define a binary
"1" state. For the case shown in Figure 8 the EN voltage is
11.3V, which means that logic high at AO and A1
is = + 8.SV (logic low continues to be = O.SV). In this
configuration the IH6208 cannot be drivenby TTL (+ 5V) or
CMOS (+ 5V) loQic. It can be driven by TTL open collector
logic or CMOS logic with + 12V supplies.

The throughput rate can therefore be maximized by using
a + 5V to + 5.5V supply for the ENable Strobe Logic.
The examples shown in Figures 6 and 7 deal with ENable
strobing when expansion to .more than four differential
channels is required; in these cases the' EN terminal acts as
a third address input. If four channel pairs or less are being
multiplexed, the EN terminal can be directly connected to
+ 5V to enable the IH620S at all times.

If the logic arid the IH620S have common supplies, the
EN pin should again be connected to the supply through a
silicon diode. In this case, tying EN to the logic supply
directly will not work since it violates the 0.7V differential
voltage required between V + and EN (See Figure 9). A 1j.LF
capacitor can be placed across the diode to minimize
switching glitohes.

Using the IH6208 with supplies other than
±15V
The IH620S can be used with power supplies ranging,
from ±6V to ±16V. The switch r05(on) will increase as the

IN.14

+12V

·~'~·-l
A CHANNEI.S
COMMON DRAIN OUTPUT

=0,

).-~,~
1

• Do
...._ _ _ _ _.. '

=(COMMON)
B CHANNEL DRAIN OUTPUT
CD003801

Figure 8: IH6208 Connection Diagram for Less Than ± 15V Supply Operation

'3-'170

Note: All typical values have been guaranteed by characterization and are not tested.

IH6208
IH6208 APPLICATION INFORMATION (CONT.)

lN914

EN

IH6208

CO004501

Figure 9: IH6208 Connection Diagram With ENable Input Strobing
for Less .T~n ± 15V Supply Operation

Peak-to-Peak Signal Handling Capability
The IH6208 can handle input signals up to ±14V (actually
-15V to + 14.3V because of the input protection diode)
when using ± 15V supplies.
The electrical specifications of the IH6208 are guaranteed for ± 1OV .signals, but the specifications have very
minor changes for ±14V signals. The notable changes are
slightly lower rDS(on) and slightly higher leakages.

3-171
Note: All typical values have been guaranteed by characterization and are not tested.

, IH821:6
(II

I

S-Channel Differential
CMOS Analog Multiplexer
GENERAL DESCRIPTION

FEATURES

The IH6216 is a CMOS monolithic 2 of 16 multiplexer.
The part is a plug-in replacement for the DG507. Three line
binary decoding is used so that the 16 channels can be
controlled in pairs by the binary inputs; additionally a fourth
input is provided to use as a system enable. When the
ENable input is high (5V) the channels are sequenced by
the 3 line binary inputs, and when low (OV), all channels are
off. The 3 Address inputs are controlled by TTL logic or
CMOS logic elements with a "0" corresponding to any
voltage less than O.BV and a "1" corresponding to any
voltage greater than 3.0V. Note that the ENable input must
be taken to 5V to enable the system and less than O.BV to
disable the system.

•
•
•
•
•
•
•
•
•

•

Pin Compatible With HI507, DG507 & AD7507
± 11V ..Analog Signal Range
rOS(on) < 700 Ohms Over Full Signal and
Temperature Range
Break·Before·Make Switching
TTL and CMOS .Compatlble Address Control
Binary Address Control (3 Address Inputs
Control 2 Out of 16 Channels)
Two Tier Submultlplexlng to Facilitate
Expandability
Power Supply Quiescent Current Less Than
1001lA
No SCR Latchup
Very Low Leakage IO(OFF):OS 100pA

ORDERING INFORMATION
PART NUMBER
IH6216MJI
IH6216CJ1
IH6216CPI

TEMPERATURE RANGE
-55°C to + 125°C
O°C to 70~C
O°C to 70°C

PACKAGE
28 pin CERDIP
28 pin CERDIP
28 pin Plastic DIP

Ceramic package available as special order only (IH6216MDIICDI)

.......,.....
.......,.....
.,.....
~~
..........,.....
.,.....
.,.....

::

~~!T.
...... .,.....
... .,.....

DECODE TRUTH TABLE
ON
SWITCH
PAIR
X
X
NONE
0
X
1
1
0
0
0
1
0
1
2
0
1
0
1
3
0
0
1
1
1
4
1
0
0
1
5
0
1
1
6
1
1
1
0
1
7
1
1
1
1
8
LOGIC "1" = VAH > 3V VENH > 4.5V
LOGIC "0" = VAL < 0.8V
Ail

I

"00

A1

Ao

EN

~

-.,.....

TO DECODE LOGIC
COHTIIOWNG 10TH
TIERS OF MUIING

Ao

AI

A,

EN (ENABLE INPun

3 UNE BINARY ADDRESS INPUTS
(0 0 0) ANOEN_SV

CD004001

ABOVE ElCAMPl.E SHOWS CHANNELS'•• 'b ON.

Figure 2: Pin Configuration

LOOO2601

Figure 1: Functional Diagram

3-172
Note: All typical values have been guaranteed by characterization and are not tested.

I...

IH82i8

CI

ABSOLUTE MAXIMUM RATINGS
VIN (A. EN) to Ground .............................. -15Vo-Vl
Vs or Vo to V + ......................................... 0. -32V
Vs or Vo to V- ........................................... 0. 32V
V+ to Ground ................................................. 16V
V- to Ground ................................................ -16V
Current (Any Terminal) .................................... 30mA

Current (Analog Source or Drain) ...................... 20mA
Operating Temperature ......................... -55 to 125'C
Storage Temperature ............................ -65 to l50'C
Lead Temperature (Soldering. 10sec) ................. 300·C
Power Dissipation (Package)" ....................... 1200mW
• All leads soldered or welded to PC board. Derate 1OmW I'C above 70'C.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operalion of the device at these or any other conditions above those in~icated in the operational sections of the specifications is not implied. Exposure to.
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
v+

= 15V.

v-

= -15V.

VEN

= +5V

MEASURED
TERMINAL

CHARACTERISTIC

(Note 1). Ground

= OV.

unless otherwise specified.
MAX LIMITS

NO
TES,!S TYP
PER 2S'C
TEMP

TEST CONDITIONS

C SUFFIX

M SUFFIX

UNIT

-55'C 25'C 12S'C O'C 2S'C 70'C

SWITCH
S to D

rDS(ON)

16

4BO

VD = 10V, IS = -lmA

Sequence each switch on

600

600

700

650

650

750

16

300

Vo = -10V, .Is = lmA

VAL = O.BV,. VAH = 3V

600

600

700

650

650

750

~rDS(ON)

20

"rOS(on) =

rOS(on)max - rOS(-+--i--i-......

,A I.A ,1
0'

OUTLINE DWG.

OUTLINEDWG

OllTLINE DWGS
JE,FD·2

To-l00

To-l00

DS02~301

D$0214Q1

OUTLINE DWG TO·1oo

OUTLINE DWGS JE, FD·2

Figure 1: Functional Diagram

3-178
Note: All Iypical.values have been guwantaed by characterization· and arenottestEld.

G3

OllTLINEDWG
TO·100
08021501

OUTLINE DWG T().100

02

05021601

OUTLINE DWG T().100

IID~DIL

MM450/451/452/455
MM550/551/552/555
ABSOLUTE MAXIMUM RATINGS

(Note 1)

Gate Voltage (VGG) ......................... + 14.5V to -30V
Bulk Voltage (VSULK) ...................................... + 14V
Analog Input (VIN) ............................. + 14V to -20V
Power Dissipation ......................................... 200mW

Operating Temperature
MM450, MM451 , MM452, MM455 .. - 55·e to + 125·e
MM550, MM551, MM552, MM555 .......... o·e to 70·e
Storage Temperature...................... -65·e to + 150·e
Lead Temperature (Soldering, 10sec) ................. 300·e

NOTE 1: Dissipation rating assumes device is mounted w~h all leads welded or soldered to printed circuit board in ambient temperature below 70·C. For higher
temperature, derate at rate of 10mWI"C for FD package and 6.5 mWI"C for TW package.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(per channel unless noted)
LIMITS

SYMBOL

CHARACTERISTIC

TYPE

Analog Input Voltage

VIN

TEST CONDITIONS

All
VOG=O

Threshold Voltage

VGS(Th)

All

Drain·Source On Resistance

All

IGSS

Gate Leakage Current

All

Drain Leakage Current

10(OFF)

VGS = -25V, VSS = Vos = 0
VOS- -25V

MM550, MM551
MM552, MM555

VGS =VSS= 0

MM450, MM451
MM452, MM455
IS(OFF)

Source Leakage Current

Cos

Drain·Body Capacitance

NOTE 1:

V

Max

600

700

Max

200

250

Max

n
n

t5

100

Max

nA

to.5

200

Max

nA

Max

nA

Max

nA

100

to.5

400

Max

nA

10

Typ

pF

MM450, MM550

14

Typ

pF

MM451 , MM551

24

Typ

pF

MM452, MM552

11

Typ

pF

11

Typ

pF

13

TY1!
Typ

pF
pF

Typ

pF

Typ

pF

Typ

pF

100

VOS = VGS = VSS = 0
f= lMHz
(Note 1)

MM455, MM555

8
9
9

All

5

MM452, MM552

Gate·Source Capacitance

CGS

V

Min

125·C

All

MM450 MM550
MM451, MM551
Gate·Body CapaCitance

Max

1.0

VOS -VGS = 0

MM455, MM555

CGS

±10

20

VSS = -25V

MM550, MM551
MM552, MM555

Source·Body CapaCitance

CSS

liD-lornA
VS=10V
JVGS= -20V

VIN= +10V
MM450, MM451
MM452, MM455

UNIT

70·C

3.0

10 = 10jJA
VIN - -10V

ROS(ON)

MIN

-MAX

25·C

Typical characteristics not tested in production

TYPICAL PERFORMANCE CHARACTERISTICS
RDS(on)

VB

VGS

RDS(on)

10,000~m
g

VGS

VB

RDS(on)

'11.- .I.~.:

10,000

100.000

V11\I-OV
10" 1 rnA

VB

DRAIN CURRENT va GATE
TO SOURCE VOLTAGE

VGS

VU C tlOV
V, .. • -10'11

10

! 8.0

1000

10,000

;

I
T .. • 2S~C
Til· _55°C

.~

1000

~60~~~~~~~~
~40~-r4-~~~1-~
~
o

·s

·s

-16

-22

IO~~~~~---'-L~

o

-4

-8

-12

-16

-20

100 '-''-'--'-'----'---'---'-'
-'6

-II

-19

-20

OP036901

3-179
Note: All typical values have been guaranteed by characterization and are not tested.

2.0 H-+-+-+-il-+~+-H
o~~~~~-L~LJ

o

-to

-2.0

-3.0

..... 0

-SO

VG5 - GATE TOSOURCi VOLTAGE IVI

VGSIYI

VGslVI
OP036801

_17

'lin-a....

Z

T .. " 85"C .

;"
100

'

",,..."'-=....,.""'=.,.-,r-r-r-r-......

.

10= 1 mA

OP037OO1

0P037101

Section 4 - Amplifiers Operational and Special Purpose

ICH8500/A
Ultra Low Input-Bias
Operational Amplifier
GENERAL DESCRIPTION

FEATURES

The ICM8500 and ICH8500A are hybrid circuits designed
for ultra low input bias current operational amplifier applications. They are ideally suited for analog and electrometer
applications where high input resistance and low input
current are of prime importance.
Functionlllly, they are pin for pin identical to the popular
741 monolithic amplifier. These amplifiers are unconditionally stable and the input offset voltage can be adjusted to
zero with an external 20kil potentiometer. The input bias
current for the inverting and noninverting inputs is 0.1 pA
maximum for the ICH8500, and 0.01 pA maximum for the
ICH8500A and are constant over the operating temperature
range of -25°C to +85°C.
Pin 8 is connected to the case. This permits the designer
to operate the case at any desired potential. This is the key
to achieving the ultra low input currents associated with
these two amplifiers. Forcing the case to the same potential
as the inputs eliminates current flow between the case and
the input pins, and leakage currents that may have otherwise existed between any of the other pins and the inputs
are intercepted by the case.

•
•
•
•
•
•

Input Diode Protection
Input Bias Current Less Than O.01pA C8500A) at
All Operating Temperatures
No Frequency Compensation Required
Offset Voltage Null Capability
Short Circuit Protection
Low Power Consumption

APPLICATIONS
•
•
•
•
•
•
•

Femto Ammeter
Electrometers
Long Time Integrators
Flame Detectors
pH Meters
Proximity Detector
Sample and Hold Circuits

ORDERING INFORMATION
ICH

12=~~"::9M""
8500A

TV

DEVICE TYPE

INTERSIL HYBRID
'----------CIRCUIT

v'

CASE

(GUARD)

CO018801

OFFSET
NULL

05019901

Figure 1: Functional Diagram

Figure 2: Pin Configuration
(Outline dwg TV)
4-1

Note: All typical values have been guaranteed by characterization and are not tested.

Cao

i ICM850c)1A
10

zCD

!:!

IID~OIL

ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................................ ±18V
Internal Power Dissipation (1) ......................... 500mW
Differential Voltage ........... ; ............. , ......... , ...... ±O.5V
Storage Temperature ...................... -65°C to + 150°C

Operating Temperature .............•....... -25°C to +85°C
Lead Temperature (Soldering, 10sec) ................. 300°C
Output, Short Circuit Duration ........................ Indefinite

Note: 1. Rating applies for ambient te":lperature, to + 70·C
NOTE: Stresses above those listed u~ "Absolute Maximum Ratings" may cause permanent device failure. These are stress ratings only and functional
operation of the devices at these or any other cond~ions above 1hose indicated in the operation sections of this specHication is not implied. Exposure to
absolute maximum rating condition~ for extended' periods may cause device failures.

ELECTRICAL CHARACTERISTIOS

'(TA

= 25°C

unless otherwise specified, VSUPPLY
ICH8500

SYMBOL
IBIAS
VOS

CHARACTERISTICS
Input Bias Current
(Inverting and Non-Inverting)

TEST
CONDITIONS

±7S

,

±SO

mV

±200

±100

mV

±3.0

±3.0

mV

75

dB

Common Mode Rejection Ratio

± 5 volts common
mode voltage

Large Signal Voltage Gain

pA

mV

At 2S·C

AVOL

±O.o1

+25 to +85·C
-2S to +2S·C

Long Term Input Offset
Voltage Stability

Output Voltage Swing

UNIT

±50

D.Vos/D.t

Common· Mode Voltage Range

TYP MAX

±SO

D.VoslD.T

tNo

MIN

±0.1

, 20kn Potentiometer

Change in Input Offset
Voltage Over Temperature

CMVR

ICH8500A

TYP MAX

Input Offset Voltage
Offset Voltage Adjustment Range

CMRR

MIN

Case at same
potjlntial as inputs

= ±15V)

75

RL'" 10kn

±11

±11

±10

±10

20,000

105

20,000

V
V

105

-

Cfb

Feedback Capacitance

Case guarded,

0.1

0.1

pF

SR

Slew Rate

RL'" 2kn

0.5

0.5

V/IJS

CIN

Input CapaCitance

Case guarded

0.7

0.7

pF

CIN

Input CapaCitance

Case grounded

1.5

1.5

pF

VOLTAGE OFFSET NULL CIRCUIT

VOLTAGE FOLLOWER

LOW LEVEL CURRENT MEASURING
CIRCUIT

OUTPUT
Yo • 1VOLT IpA
= 1012, liN

CASE
GUARD
TCQ281(N

LC014701
1.0014801

NOTE: Adjust input offset voltage to OV±10I'V balore measuring leakage.

Figure 3: Circuit Notes

4-2
Note: All typical values have been guaranteed by characterization and are not tested.

ICH8500/A
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT VOLTAGE RANGE
SUPPLY VOLTAGE

OPEN LOOP VOLTAGE GAIN VI.
FREQUENCY
106

;:

~

i
w

~

o

~

z
o

~
100

1 Ie.

10k

lOOk

'"
8'"

INPUT OFFSET VOLTAGE
SUPPLY VOLTAGE

100

-

4'VSU~LY'+5~

60
8

9

10

11

12

'.

...::>~

!

I

I:;;;;: f--

Tp.."''''aso C -

=

~
~

80

0

~

'j"+25' C

,0

4
13

14

15

16

9

10

1

10

~~

0

"~'"

\.

"

11

12

13

14

15

8

1.6

10

11

12

13

14

15

0P035401

OP035301

INPUT REFERRED NOISE VOLTAGE
500

~

,
I

r-"
~

~ TOO
10

\
I
100

SUPPLY

V8.

80

'I

o

POWER CONSUMPTION
VOLTAGE

~s'.!\odn

\

16

SUPPLY VOLTAGE i'V)

V8.

SUPPLY VOLTAGE ltV}

~~

.. , ...0-

~

OP0352OI

±QUIESCENT SUPPLY CURRENT
SUPPLY VOLTAGE

~
..
~\..

I!:::>

SUPPLY VOLTAGE (:tV)

SUPPLY VOLTAGE bVI

16

TA"'+25"C

o
8

16

~

i

~

12

14

OUTPUT VOLTAGE SWING VB.
SUPPLY VOLTAGE

'"

11

13

0P035101

~

90

10

-

5 VOLT COMMON
MODE VOLTAGE

z

...>w

8

•

~~

;..;;;

SUPPLY VOLTAGE I-V)

±POWER SUPPLY REJECTION
RATIO V8. SUPPLY VOLTAGE

V8.

•

0

~

~

OP035001

10

s

70

SUPPLY VOLTAGE (tVI

0P034901

~

~ .;.:!

'po

1M

FREQUENCY (Hz I

:;'"

80

~
z

o

1

10

•

o

TA· .. 2oC

~

COMMON MODE REJECTION RATIO
V8. SUPPLY VOLTAGE

~

V~UI'P .I,lSV

l"-

:>

V8.

z
\2
Ii:

.

I

::>

'0!1

u

i

'"

~

~
lk

10k

lOOk

FREQUENCY IHzl
OP035501

Note: All typical values have been guaranteed by characterization and are not tested,

50
40
30

iff.!
1

....::

20

~

10

o

8

?'

9

10

11

.'

~

.....,:" '-- f--

... ,..

12

13

14

15

16

SUPPLY VOLTAGE (tVI
CP035601

OP035701

i

.O~OIL

ICH8soO/A

I

currents that may otherwise exist between the ± 15V input
and the inverting input summing junctions. FeedbaCk capacitance" should be kept to minimum in order to
maximize the response time of the circuit to step function
input currents. The time constant of the circuit is approximately the product of the feedback capacitance Ctb times
the feedback resistor Rfb: For instance, the time constant of
the circuit in Figure 4 is 1 sec if Cfb = 1pF. Thus, it takes
approximately 5 sec (5 time' constants) for the circuit to
stabilize to within 1% of its final oiJtput voltage after a step
function of input curre~t has been applied. Ctb of less than
0..2 to O.3pF can be achieved with proper circuit layout. A
practical pico ammeter circuit is illustrated in Figure 5.

APPLICATIONS
;:; ThePICo Ammeter

t~rmina,ls

A very ~ensitive pico ammeter can be constructed with
the ICH850Q. The basic circuit (illustrated in Figure 4)
employs the amplifier in the inverting or current summing
mode.
Care must be taken to eliminate any stray currents from
flowing into the current summing node. This can be
accomplished by forcing all points surrounding the input to
the same potential as the input. In this case the potential of
the input is at virtual ground, or O.V.Therefore, the case of
the device is grounded to intercept any stray leakage

a

Rib" loUn

CURRENT
SOURCE

~U. ENT/

>----'---'--OUTPUT
Vo" .IIN

SUMMING
NODE

Atb

-·IVOl.T/pA

LC014901

Figure 4: Basic Pico Ammeter Circuit

.,sv

.Ib

10t20:

.,

t""
IMNT>---~~--~~----~----~~----------_I

----I,.

cO

~----_--_--------. OU""'T
V•.--I IfW JlIOUSl

.. -I VOl.TIpA

INTERNAl.

olooes

08020001

Figure 5: Pico Ammeter Circuit

Note: All typical values have been guaranteed by characterization and are not tested.

ICH8500/A
.... CAN IE REDUCED TO 10K
IF CIRCUIT IS EllPl.OYED AS
ANINTEORATOR
INPUT TERMINAL

If CIRCUIT

ASAN::'~:~~~~~
VIN-OTOt'OV

CHARGE
STORAGe
CAPACITOR

r--"""-+-----------.

/
SW2

INPUT

~E~~~~~

AS A'::::tt!~g

111700

•

l00ttO

>-~Oy.OI/l'....__+-----...;O r-i~--""'--_--O;"""---f

HOLD CIRCUn
Y,N -OTO:t10V

8

....._

>.....:~-

1T1100
G

OUTPUT

+lSV

'Oof

v, .-...J'I/I."",......_0_15V

IOkn

-ISV

'M"

.ok"
o.c.

lERO

v,
SAMPLE

1T1700

PuLSfOR

CAPACITOR
OISCHARGE
PULSE

ADJUST eNULL TO ELIMINATe
ANV OUTP\lt OfFSET VOLTAGE
DUE TO CHARGE INJECTION

t-----------------------~---JF.OMSW2

,.""
":"

-1SV

TC0264~

Figure 6: Sample and Hold Circuit or Integrator Circuit
The internal diodes CR1 andCR2 together with external
resistor R1 protect the input stage of the amplifier from
voltage transients. The two diodes contribute no error
currents, since under normal operating conditions there is
no voltage across them.

source, drain and gate of switch SW2 are zero or near zero
when the circuit is in the hold mode. Careful construction
will eliminate stray resistance paths and capacitor resistance can be eliminated if a quality capacitor is selected.
The net result is a low drift sample and hold circuit.
As an example, suppose the leakage current due to all
sources flowing into the current summing node of the
sample and hold circuit is 100pA. The rate of change of the
voltage across the 0.01 j.LF storage capacitor is then 1OmV I
sec. In contrast, if an operational amplifier which exhibited
an input bias current of 1nA were employed, the rate of
change of the voltage across CSTO would be 0.1 V Isec. An
error build up such as this could not be tolerated in most
applications.
Wave forms illustrating the operation of the sample and
hold circuit are shown in Figure 7.

Feedback capacitance is the capacitance between the output and the
inverting input terminal of the amplifier.

Sample and Hold Circuit
The basic principle of this circuit (Figure 6) is to rapidly
charge a capacitor CSTO to a voltage equal to an input
Signal. The input signal is then electrically disconnected
from the capacitor with the charge still remaining on CSTO.
Since CSTO is in the negative feedback loop of the
operational amplifier, the output voltage of the amplifier is
equal to the voltage across the capacitor. Ideally, the
voltage across OSTO should remain constant, causing the
output of the amplifier to remain constant as well. However,
the voltage across CSTO will decay at a rate proportional to
the current being injected or taken out of the current
summing node of the amplifier. This current can come from
four sources: leakage resistance of CSTO, leakage current
due to the solid state switch SW2, currents due to high
resistance paths on the circuit fixture, and most important,
bias current of the operational amplifier. If the ICH8500A
operational amplifier is employed, this bias current is almost
non-existant « 0.01pA). Note that the VOltages on the

The Gated Integrator
The circuit in Figure 6 can double as an integrator. In this
application the input voltage is applied to the integrator
input terminal. The time constant of the circuit is the product
of R1 and CSTO. Because of the low leakage current
associated with the ICH8500 and ICH8500A, very large
values of R1 (Up to 10 12 ohms) can be employed. This
permits the use of small values of integrating capacitor
(CSTO) in applications that require long time delays. Waveforms for the integrator circuit are illustrated in Figure 8.
4-5

Note: All typical values have been guaranteed by characterization and are not tested ..

IIO~DIL

~ ·ICH8500/A
8 ~.------____----__--~

I

O....Jr----,

.,

+5V

V,N

SAMPLE PULSE

0--1

+I.V~TIME-.
bl

V,

v,

bl
-f5V

,I

~'

V2

V3

,I

V2

, - - -....,

.1

STATE OF
SW2

II

I

+'.V~'
:

.,

hI

i--CLOSED--I

I

OUTPUT
OP.AMP.

.,

.

STATE OF
SWI

~ .000EN

"'-=LE
0-------

~
I

II

11

II
" CLOSED

~Of'EN_jlIHr
...~_ _

Of'EN

I,

I

V3
-15V

"
CLOSED II

INPUT TO +18V - - - - - - - - " " \
SAH

-15:~
+15V

-15V

STATE OF
SW'

TIME~

+16V~
-15V

0-,
-15V

dl

r--'""'1
•. :.•..•...••
~

>IV

STAn OF
SW2
WINDOW

_____

"--

0=S: -----------_______________

~v--~~------

CLOSED

II

-

I

~OPEN __

Of'EN

II ~LOSEO
IL.:it:

I--CLOSED-t

OPEN

~=LEWINDOW

9\ INTE~~:ri~~
0 ------~---INPUT -lOY

hi INTE~~~~~

V,N
Vo" - RCSTO

1"

0.1 VOLT/SEC.

WF015801

Figure 7: Sample and Hold
Circuit Waveforms

-~---~------WF015901

Figure 8: Gated Integrator Waveforms

Note: All typical values have been guaranteed by characterization and . are nat tested.

U~D[61..

ICH8510/8520/8530
Power Operational
Amplifier

o

CD

GENERAL DESCRIPTION

FEATURES

The ICH8510/8520/8530 is a family of hybrid power
amplifiers that have been specifically designed to drive
linear and rotary actuators, electronic valves, push-pull
solenoids, and DC & AC motors.
There are three models available for up to + 30V power
supply operation: 2.7 amps @ 24 volt output levels, 2 amps
@ 24V and 1 amp @ 24V. All amplifiers are protected
against shorts to ground by the addition of 2 external
protection resistors. For a device operating at lower voltages, see the ICH8515 data sheet.
'
The design uses a conventional 741 operational amplifier, a special monolithic driver chip (BL8063), NPN & PNP
power transistors, and internal frequency compensating
capacitors. The chips are mounted on a beryllium oxide
substrate for optimum heat transfer to the metal package.
This substrate also provides electrical isolation between
amplifiers and metal package.
The I.C. power driver chip has built-in regulators that
provide the 741 with typically a ±13V supply.

•
•
•
•
•
•
•
•
•

Delivers Up to 2.7 Amps @ 24-28V DC (30V
Supplies)
Protected Against Inductive Kick Back With
Internal Power Limiting
Programmable Current Limiting (Short Circuit
Protection)
Package Is Electrically Isolated (Allowing Easy
Heat Sinking)
Open Loop DC Gain> 100dB
20mA Typical Standy Quiescent Current
Popular 8 Pin TO-3 Package
Internal Frequency Compensation
Can Drive Up to 0.1 Horsepower Motors

ORDERING INFORMATION
ICH8SXO

M

KA

I T <=-~-

~ KA = 8 lead T0-3 can

Temperature Range
M - Military -SsoC to
I = Industrial - 20°C to

+ 12SoC
+ 8SoC

Basic Part Number
8S10 = 1A output
8520 = 2A output
8S30 = 2.7A output

y+

(TOPYIEW)

+----""---l-=-...;. voo-=;
'~_-+'W'v-1...;IASC-·

c001B901

y-

08020101

FI ure 1: Functional Dia ram

Fi ure 2: Pin Confl uration

4-7
Note: All typical values have been guaranteed by characterization and are not tested.

i

CD

&II
W

o

g10' ICtl851Qj852018530
'.;.'
. . '.'
. ,
.'
~

AB50LUTEMAXIMUMRATINGS @TA=25·C

i......

Operating Temperature Range M ...... -55·C ~ +125·C
. I ........ -20·C ~ +85·C
Storage Temperature Flange ........ ::.:. -65·C to +150·C
Le~d Temperature (Soldering" 1Psec) ...... ,.",..... ,.3qO·p .
Max Case Temperature ...... , ~ ................ : .......... 150·C

Supply Voltage ............................................ ; .• ~.± 32V
Power Dissipation, Safe Operating Area ...... See Curves
0, Differential Input Voltage ...................................±30V
10 Input Voltage ............................ , ........ ±15V (Note 1)
CD peak Output Current ................... See Curves (Note 2)
Output Short Circuit Duration
(to ground) .............................. Continuous (Note 2)

..

-lj'

Note 1: Rating applies to supply vollSges of ± 15V.For lower supply voltages, VrNMAX ~ Vsupp.
Note 2: Ratings apply as long as package dissipation is not exceeded. Device must be mounted on heat sink, see Figures 12 and 16.
Stresses above those listed under Absolute' Maximum Ratings may cause permanent damage' to ·the device. These arestrEiss ratings only, and flinctional
operation of the device at these or any other conditions above those indicated in the operational sections of the spec~ications is not implied. Exposure to
absolute maximum rating conditions for extended; periods may affect device reliability.

ELECTRICAL CHARACTERISTICS TA = + 25·C. VSUPPLY = ±30V (unless otherwise stated)
SYMBOL

.DESCRIPTION

TEST
CONDITIONS

t.VOSIt.Pd

Input Offset Voltage
Change with
Power DiSsipation

Mtd on Wakefield
403 Heat Sink

Vos

Input Offset Voltage

RS< 10kll
Pd< lW

ISlAS

Input Bias Current

RS< 10kll
Pd< lW

ICH85101

ICH8510M

ICH85201

MIN

MIN

MIN

4
(Typ.)
-6

-3

+6

+3

500

Inpol Offset Current

RS< 10kll
Pd< lW

Large Signal
Voltage Gain

RL-201l
Vo> 2/3 Vsupp

VCMR

Input Voltage Range

Typical

CMRR

Common Mode
Relction Ratio

Rs-l0kll

PSRR

Power Supply

RS-l0kll

SR

'Slew Rate

VOMAX

Ou1pol Voltage Swing

RL-201l

Ay -10

±26V

±26V

IMAX

Output Current (3)

RL-ell
Av-l0

1.0

1.0

10

Power Supply
Quiescent Cur:rent

RL-X
VIN-OV

100
(Typ.)

-10

+10

-10

70
(Typ.)

CL-3pF, Av-l
RL -lOll
Vo - 2/3 Vsupp

-6

+6

70
(Typ.)

-10

MAX

ICH65301

-3

+3

70
(Typ.)

-6

ICH8530M

+6

70
(Typ.)

-3

200
100
(Typ.)

+10

Mifol

500

100

-10

MAX
4
(Typ.)

250

100
(Typ.)
+10

MIN

2
(Typ.)

200
100
(Typ.)

+10

MIN

500

100

200
100
(Typ.)

MAX
4
(Typ.)

250

lOS

Rejection Ratio

MAX
2
(Typ.)

AVOL

NOTE 2:

ICH8520M

UNIT
MAX

-10

MAX
2
(Typ.)

mV/W

+3

mV

250

nA

100

'M
dB

100
(Typ.)
+10

-10

+10

V
dB

70
(Typ.)

70
(Typ.)

77

77

77

77

77

77

(Typ.)

(Typ.)

(Typ.)

(Typ.)

(Typ.)

(Typ.)

0.5
(Typ.)

0.5
(Typ.)

0.5
(Typ.)

0.5
(Typ.)

0.5
(Typ.)

0.5
(Typ.)

VII'S

±26V

±26V

±25V

±25V

V

2.0

2.0

2.7

2.7

A

(RL

(RL - 3011)

-30n

125

100

125

100

125

dB

100

mA

See Figure 7 if P~r Suplies are less than ± 30V '.

ELECTRICAL SPECIFICATIONS TA= -55·C. to +125·C.(M) or TA= -20·C. to +85·C (I).
SYMBOL

DESCRIPTION

TEST
CONDITIONS

VOs

Inpol Offset Voltage

PdoI

~igure

l.C015001

Figure 3: Maximum Output Current
for GlvenRSc

5: Inductive Load (Note catch diode)

NOTE ON AMPLIFIER POWER DISSIPATION
The steady state power dissipation limit is given by

In general, for a given Va, Isc limit, and case temperature
TC, Rsc can be calculated from 'the equation below for Va
positive, lOUT positive.
'
RSC=

PO=

_ _ T.::,J",,(M;;;,.AX=-.)-_T...;cA.:,.'_
R8JC + RBCH + R8HA

where:
TJ =
Maximum junction temperature
TA =
Ambient temperature
R8JC = Thermal resistance from transistor junction to case
of package
R8CH = Thermal resistance from case to heat sink
R8 HA = Thermal resistance f~om heat ,sink to ambient air
And since
TJ =
200"C for silicon transistors
R8JC 9!; 2.0°C/W for a steel. bottom TO-3 package with die
attachment to beryllia substrate header
ROCH;>= .045°C/W for 1 mil thickness of Wakefield type 120
thermal joint compound
.09°C/W for 2 mil thickness of type 120
.13°C/W for 3 mil thickness of type 120
.17°C/W for 4 mil thickness for type 120
.21°C/W for 5 mil thickness of type 120
.24°C/W for 6 mil thickness of type 120

(20.6VO)" + 680-2.2(TC..,2S0C)

ISC(lIMIT)
"For Va negative, replace this term with 10.3 (VA - 1.2)
For example, for 10 = 1.SA @ Va = 2SV and TC = 2SoC,
119S
Rsc = - - = 0.797
1500
Therefore for this application, RsC = 0.820 (closest
standard value).
When 0.820 is used, ISC @ Va = OV will be reduced to
about 1A. Except for small changes in the "±VO(max) Limit"
area, the effects of changing Rsc on the lOUT vs VOUT
characteristics can be determined by merely changing the
lOUT scale on Figure 3 to correspond to the new value.
Changes in TC move the limit curve bodily up, and down.
This internal current limiting cirCUitry however does not at
all restrict the normal use of the driver. For any normal load,
the static load line will be similar to that shown in Figure 3.
4-9

Note: All typical values have been guaranteed' by characterization and are not tested.

I

lCH8smls520/8530
R8HA = The choice of heat sink that a user selects
1'. depends'upbnthe amount of room availablE!
mount the'l\eat Sink.. A sample calculation follows:
by' choosing a Wa:kefield 403 heat sink,' wlthfree
air, natural convection 1no fan). R6HA ~ 2.0·C/W.
Using 4 'mil 'joint compound,

to

Po ..

12001'6_

2S"C

4. 17°CIW.

42W

and @ TA =, 125°C,
"200°C -125°C
,
=18W

200·C- TA

' 200·C- TA
.. - - - - ' - '
(2.0 + 0.17 + 2.0)OC/W
4.17°C/W

4. 17ciC!W

From Figure 6 the worst case steady state power
dissipation 'for an IH8520 (Rsc .'0;62fl) is 'aoout30W and
18W'I"espectively. Thus this heat sink is adequate.

,TYPICAL PERFORMANCE' CHARACTERISTICS
tat 1120. lI'Iu111p1f
lou• .., ....

For

ICtIIS30

ICH_

RIC" ...n

TCASE HOC
Vee ,.~

louT

f

..,ua

. loUT

TeASE '.·C
Vee
!3IV'

For lett.B'G. ......'·
Rile = 1.an
Source CurNftt

,I

on., .........

_c.._
--.
-~

..........1 ....

Dt..... LInH...
with T."",;

'-~~~~~~4-~~~~~~-'
__ ..11 ..act . " , ..'0 ...
•
10 15 20 H 1DV YOuT

. . -25

-21

-15 .. '0

5

-S

10

15

20

25

30

YOUT
sc007001

Safe Operating Area; lOUT vs VOUT vs TC
101(

100

"

15

10

II

30 _ _ _ (WI

... :"1.;.; on YIn

~
10 get ......,... Po'ftf DIu.. tMn.,_IOGo!II''' _ _ ('IOUT·11X'~

sc007101
lC015101

Input ,Offset Voltage vs Power Dissipation

...

"':':.

LC015201

sc007201

Input .Impedance vs Gain vs Frequency

+10
Note: All typical values have been guaranteed by characterizatioll. and .ara not,tastad.

,~

IID~OIL

ICH8510 /8520 /8530
TYPICAL PERFORMANCE CHARACTERISTICS (CONT.)

•I
I

....... +Vee CM' ..Vee t_)

./
.'

40

IK

~
~

ID

;

o

GuIeIGHI: c....... IrOIn •

..

g

0

LC015301

SCOO7301

Quiescent Current va Power Supply Voltage

..

Your _ _ _ Your 2: :tt7'lo Yee

100kHz

1_
,K

111Hz

Vln@f

-

100 c:IoMci Iaop .....

100

,0

--At

IIIClI

At

IIIn

Rf

",on

,....

sc007'"

Rt .. 1Kn

1iir
LCOt5401 '

Large Signal Power Bandwidth

II

At

c..._
IK

,-

Vln@t

1KHI 1OKHI. 100KHI

_HlI

':;'

LC01 ....

SCOO7&Ol

Small Signal Frequency Response

4-11
Note: All typical values have been guaranteed by characlellzalion

ilhd lil'enot I_tett

-::-

Rf~1~RI

080202.01

Figure 8: Non-Inverting Amplifier
.... . .

0

+15" +10

+11 +100 ..., •.

c.o.'T_ CTe)' C·CI
,

SCOO7601 ,

Figure 6: Maximum Output Current
vs. Case Temperature
v'"
III

05020301'

Figure 9:, Inverting Amplifier

...

Power dissipation is another important parameter to
consider. The current prptection circuit protects the device
against short circuits to ground,,(but only for transients to
the oppo~ite supply) provided the, device has adequate heat
sinking. A 'curve of power dissipation Viii Vo under short
circuit conditions is given in Figure 10. The limiting circuit is
more' closely dependent on case temperature than (output
transistor) junction temperatures. Although these operating
conditions are unlikely to be attained in actual use, they do
represent the limiting case a heat sink must cope with. For a
fully safe design, the antic1patedrange, of Vo values that
could occur;' (steady state, includihgfaults) should be
examined for the highes~ power dissipatiOn, and the device
provided with a heat 'sio1( that will'keep the junction
temperature below 200·C and the case temperature below
150·C with the worst case ambient, t~mperature expected.

...
Figure

7:

scoonot

Maximum Output Current
vs. VSUPPLY
.,- ,',>

APPLICATION' NOTES. :>
The maximum input voltage'rang~, for VSUPPLY < ± 15V,
is substantially less t~an thcf avail.~bleoi1tput voltage swing.
Thus non-inverting amplifiers, as ,in Figure 8, should always
be set up witha,gairi greater than iit;out 2.5, (with ±30V
supplies), so that the full oiJtput swing is available without
hazard to the input. At first sight, it would seem that no
restrictions would apply to inverting amplifiers" since the'
inputs are virtual ground and ground. However, under fault
(output short-circuited) or high slew conditions, the input
can be substantially removed from ground. Thus for inverting amplifiers with gains less than about 5, some protection
should be provided at this input. A suitable resistor from the
input to ground will provide protection, but also increases
the effect of input offset voltage at the output. A pair of
diodes, as shown in Figure 10, has no effect on normal
operation, but gives excellent protection.

Source

eIIMeIon ....... '

,.

,(,

.,,~"":

Pella' .

~r----""'---...!'

,--;ani,

For II. ., " " ' " 'lOUT

"'_.-.

TrinMnts

,,;'-'
,,;'

./
·YOUT' 30Y

25'1 20V 15Y

lOY

5Y
sc007601

Figure 10: Power Dissipation under Short
Circuit Conditions

+-12
Note: All typical values have been guaranteed by characterization aod ,are not teste!!;,

ICH8510 /8520 /8530
TYPICAL APPLICATIONS
Actuator Driving Circuit (24 .... 28 VDC rated)

Obtaining Up To 5 Amps Output Current
Capability By Paralleling Amplifiers

.

.

,

....
"

Actuato,
/ .... 'on
Acht.-tOf

/j:::::')
YOu'

05020401

Figure 11: Power Amp Driving Actuator
The gain of the circuit is set to + 10, so a VIN = +2.4V
will produce a +24V output (and deliver up to 2.7 amps
output current). To reverse the piston travel, invert VIN to
-2.4V and VOUT will go to -24V. Diodes 01 and 02 absorb
the inductive kick of the motor during transients (turn-on or
turn-off); their breakdown should exceed 60V.
SCOO7901

Figure 12: Paralleling Power Amps
for .Increased Current Capability
This paralleling procedure can be repeated to get any
desired output current. However, care must be taken to
provide sufficient load to avoid .the amplifiers pulling against
each other.

Driving A 48VDC .Motor

---

--------,
_ow
I
I

1

1
1

1

1

1
I
1
1

__ ____ 1

~--~~-+~-_~_-_~ ~

....

. ....... =
.,.~

90007801

Figure 13: Power Amp Driving 48 VDC Motor

4-13
Note: All typical values have been guaranteed by characterization and are not tested.

I

IC"8510/8520/8530

CD

2,I

0'
..

:I

~.....
....

Precise Rate Control' of an Electronic
Valve

The circuit presented in Figure 14 is also an excellent
way to get a precise power supply voltage; in fact, it is
possible to build a preCision variable power supply using a
BCD coded DAC with' BCD Thumbwheel switches.

There are two methods to get very fine control of the
opening of an orifice driven by an electronic valve.
1. Keep the voltage constant, i.e., 24VDC or 12VDC,
and vary the time the, voltage is applied, i.e., if it
takes five seconds to completely open an orifice at
24VDC, then applying 24V for only 2Y2 seconds
opens it only 50%.
2. Simply vary the DC driving voltage to valve. Most
valves obtain full opening as an inverse of applied
voltage,i.e., valves open 100% in five seconds at
24VDC and in·l0 seconds at 12VDC.
A circuit to perform the second method is shown below;
the advantage of this is that digit switches can precisely set
driving voltage to 0.2% accuracy (S-bit DAC), thereby
controlling the rate at which the valve opens.

There is great power available in the sub-systems shown
in Figures 14 & 15; there the 0/ A converter is shown being
set manually (via digit switches) to get a precise analog
output (binary #x full scale voltage), then the driver
amplifier multiplies this voltage to produce the final output
voltage. It seems obvious that the next logical step is to let
a microprocessor control the 0/ A converter. Then total;
pre-programmable, electronic control of an actuator, electronic valve, motor, etc., is obtained. This would be used in
conjunction with a transducer/multiplex system for electronic monitoring and control of any electromechanical
function.

'Ok

+5" ...

lC015601

Figure 14: Digitally Controlled Electronic

4-14
Note: All typical values have been guaranteed by characterization and are net tested.

Valu~

ICH8510 /8520/8530
4K

.-tIY

+5V Nt.

-=LC015701

21 22
1 1
1 1
1 0
1 0
0 0
0 0
The power

2°
1
1
0
0

23 24 25 26 27 o BITVout
+ 25VDC
1 1 1 1 1 1
1- 1 1 1 1 o
-25VDC
1 1 0 0 1 1
+15VDC
1 1 0 0 1 o
-15VDC
+0.098VDC
0 0 0 0 0 1
-0.098VDC
0 0 0 0 0 o
supply can be set set Ie ± 0.1 VDC.

Figure 15: Digitally Programmable Power Supply

HEAT SINK INFORMATION
Heat sinks are available from Intersil. Order part number
29-0305 ($10.00 ea.) with a ROHA = 1.3°C/watt. A convenient mating connector is also available. Order part number
29-0306 ($4.50 ea.).
Note: This product contains Beryllia. If used in an application where the
package integrity may be breached and the internal parts crushed or
-machined, avoid inhalation of the dust.

APPLICATION NOTES
For Further Applications Assistance, See:
A021 "Power D/A Converters Using The ICH8510/201
30," by Dick Wilen ken
A026 "DC Servo Motor Systems Using The ICH8510/201
30," by Ken McAllister
A029 "Power Op Amp Heat Sink Kit," by Skip Osgood

4-15
Note: All typical values have been guaranteed by characterization and are not tested.

, ICM8515
iPower Operationa'i
~Amplifier

GENERAL DESCRIPTION

FEATURES

The ICH8515 is a hybrid power amplifier specifically
designed to drive linear and rotary actuators, electronic
valves, push-pull solenoids, and DC & AC motors.
The design uses a conventional 741· operational amplifier, a special monolithic driver chip (BL8063), NPN & PNP
power transistors, and an internal frequency compensating
capacitor. The chips are mounted on a. beryllium oxide
substrate, for optimum heat transfer to the metal package.
This substrate provides electrical isolation between the
amplifier and the metal package.
The 8515 has special SOA (safe operating area) circuitry
which allows it to withstand a direct short to ground or to
either supply indefinitely. It has been designed to operate
with ± 12 or ± 15VDC supplies and will deliver typically 1.5 to
1.8A @ +13V out using ±15V supplies.
Internal frequency compensation provides stability down
to unity gain (either inverting or noninverting) even when
using inductive loads.

•
•
•
•
•
•
•
•
•

Delivers Up to 1.5 Amps @ + l2VDC (±15VDC
Supplies)
Protected Against Inductive Kick Back By
Internal Power Limiting
Prograinmable Current Umiting (Short Circuit
.
Protection)
Package Is Electrically Isolated (Allowing Easy
Heat' ·Sinking)
Open Loop DC Gain> 100dB
Popular 8 Pin TO-3 Package
Internal Frequency Compensation
Can Drive Up to 0.033 Horsepower Motors
Pin Equivalent to ICH8510/20/30 Family

ORDERING INFORMATION
PART NUMBER

OUTPUT CURRENT

TEMPERATURE

PACKAGE

ICH8515MKA

1,5A

-55°C to + 125°C

8·Lead TO-3

ICH85151KA

1.25A

-25°C to +85°C

8'Lead TO·3

Y'

(TOP VIEW)

+----1--:,---..;;' Yo~
.....~~+'IN..,........o5ASC-

C1lO19OO1

4
08020501

Figure 1: Functional Diagram

4-16
Note: All typical values have been guaranteed by characterization and· are not tested.

Figure 2: Pin
Configuration
(Outline dwg KA)

n
z

ICH8515

CD

ABSOLUTE MAXIMUM RATINGS

@ TA

...

UI
UI

= 25°C

Supply Voltage ................................................ ±18V
Power Dissipation, Safe Operating Area ...... See Curves
Differential Input Voltage ................ , .................. ±30V
Input Voltage ..................................... ±15V (Note 1)
Peak Output Current ................... See Curves (Note 2)
Output Short Circuit Duration
(to ground) .............................. Continuous (Note 2)

Operating Temperature Range M ...... -55°C to + 125°C
I ......... -25°C to +85°C
Storage Temperature Range ............ -65°C to + 150°C
Lead Temperature (Soldering, 10sec) ................. 300°C
Max Case Temperature ................................... 150°C

Note 1: Rating applies to supply voltages of ± 15V. For lower supply voltages, VINMAX = VSUPPLy.
Note 2: Rating applies as long as package dissipation is not exceeded for heat sink attached.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other cond~ions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
OPERATING CHARACTERISTICS TA = + 25°C.

VSUPPLY

= ±15V

(unless otherwise stated)
ICH85151

SYMBOL

PARAMETER

ICH8515M

TEST CONDITIONS

UNIT
MIN

TYP

MAX

MIN

TYP

MAX

tiVos/tiPd

Input Offset Voltage
Change with
Power Dissipation

Vos

Input

IBIAS

Input Bias Current

RS S 10kn, Pd

< lW

500

250

nA

lOS

Input Offset Current

RS S 10kn, Pd < lW

200

100

nA

AYOL

Large Signal Voltage Gain

VCMR
CMRR

Off~t

Voltage

Input Voltage Range

Mtd. on Wakefield
403 Heat Sink

4
(Typ.)

RS S 10kn, Pd < 1W

RL -10n,
, Vo > 2/3 VSUPPL Y
Typical

1

-6

6

100
(Typ.)

-3

0.7

2
(Typ.)

mV/W

3

mV

100
(Typ.)

-10

+10

dB

-10

+10

V

Common Mode
Rejection Ratio

Rs·l0kn

70
(Typ.)

70
(Typ.)

dB

PSRR

Power Supply
Rejection Ratio

RS= 10n

77
(Typ.)

77
(Typ.)

dB

SR

Slew 'Rate

CL = 30pF, Ay = 1,
RL=10n
Vo ~ 2/3 VSUPP
,RL=10n, Ay=10

0.5
(Typ.)

0.5
(Typ.)

VII'S

±1.25

tiVo

Output Voltage Swing

10

Output Current

RL-5n, Ay=10

IQ

Power Supply
Quiescent Current

RL =00,

OPERATING CHA,RACTERISTICS (continued) TA
Input Offset Voltage

Pd > RL.
VIN
RIN RL
This circuit allows 'precisely set motor drive current with
op. amp. feedback accuracy. If RIN = RF = 1kn, and

I":"

L ______ J
-15V

08020601

Figure 9

IL
RL = 10n, then - = -0.1' AmpslVolt, and if RL = 1n
VIN
(use 4W or more). and RF = RIN = 1kn,
IL
1 Amp
-=-1x1 = - . - .
VIN
Volt
thus if VIN = 1.5V. 1.5 amps will flow thru the motor. Since
one side of the motor will. have a 1.5\{ drop (with respect to
GND), the Vo point will go to 13.5V and develop 12V acrOS$
motor.

HEAT SINK INFORMATION
Heat sinks are available from Intersil. Order part number
29-0305 ($10.00 ea.) with a R6HA = 1.3°C/watt. A convenient mating connector is also available. Order part number
29-0306 ($4.50 ea.).
NOTE: This product contains Beryllia. If used in an application. where the
package integrity may be breached and the internal parts crushed or
machined. avoid inhalation of the dust.

4-22
Note: All typical values have been guaranteed by characterization. and are not tested.. ,

ICL7605/ICL7606
Commutating Auto-Zero (CAZ)
Instrumentation Amplifier
GENERAL DESCRIPTION

FEATURES

The ICL7605/1CL7606 CMOS commutating auto-zero
(CAZ) instrumentation amplifiers are designed to replace
most of today's hybrid or monolithic instrumentation amplifiers, for low frequency applications from DC to 10Hz. This is
made possible by the unique construction of this new
Intersil device, which takes an entirely new design approach
to low frequency amplifiers.
Unlike conventional amplifier designs, which employ
three op-amps and require ultra-high accuracy in resistor
tracking and matching, the CAZ instrumentation amplifier
requires no trimming except for gain. The key features of
the CAZ principle involve automatic compensation for longterm drift phenomena and temperature effects, and a flying
capacitor input.
The ICL7605/1CL7606 consist of two analog sectionsa unity gain differential to single-ended voltage converter
and a CAZ op amp. The first section senses the differential
input and applies it to the CAZ amp section. This section
consists of an operational amplifier circuit which continuously corrects itself for input voltage errors, such as input
offset voltage, temperature effects, and long term drift.
The ICL760511CL7606 is intended for low-frequency
operation in applications such as strain gauge amplifiers
which require voltage gains from 1 to 1000 and bandwidths
from DC to 10Hz. Since the CAZ amp automatically corrects
itself for internal errors, the only periodic adjustment
required is that of gain, which is established by two external
resistors. This, combined with extremely low offset and
temperature coefficient figures, makes the CAZ instrumentation amplifier very desirable for operation in severe
environments (temperature, humidity, toxicity, radiation,
etc.) where equipment service is difficult.

•
•
•
•
•
•
•
•
•

Exceptionally Low Input Offset Voltage - 2jl.V
Low Long Term Input Offset Voltage DrlftO.2jl.V/Year
Low Input Offset Voltage Temperature
Coefficient - O.05jl.V rc
Wide Common Mode Input Voltage Range - O.3V
Above Supply Rail
High Common Mode Rejection Ratio-100 dB
Operates at Supply Voltages As Low As ±2V
Short Circuit Protection On Outputs for ±5V
Operation
Static-Protected I",puts - No Special Handling
Required
Compensated (ICL7605) or Uncompensated
(ICL7606) Versions

AZ
-iNPUT

-oIFF IN
+DIFFIN
C3

Co
C,
C,

DR

osc
v+
(outline cIwg JNI
COO14701

Figure 1: Pin Configuration

ORDERING INFORMATION
Order parts by the following part numbers'
PART NUMBER
ICL7605CJN
ICL76051JN
ICL7605MJN
ICL7605/D
ICL7606CJN
ICL76061JN
ICL7606MJN
ICL7606/D

COMPENSATION

TEMPERATURE RANGE
O·C to +70·C
-25·C to + 85·C
-S5·C to + 125·C

INTERNAL
INTERNAL
INTERNAL
INTERNAL
EXTERNAL
EXTERNAL
EXTERNAL
EXTERNAL

-

O·C to +70·C
-25·C to + 85·C
-55·C to + 125·C

-

PACKAGE
18-PIN CERDIP
18-PIN CERDIP
18-PIN CERDIP
DICE"
18-PIN CERDIP
18-PIN CERDIP
18-PIN CERDIP
DICE"

"Parameter MiniMax Limits guaranteed at 2S·C only for DICE orders.

4-23

Note: All typical values have been guaranteed by characterization and are not tested.

301681-002

II

·1

ICJ.,7895/ICL.7808

!:i
!:!

y+

10

g

!:iu

-

+01" IN
-DIFF IN
OUTPUt
AZ
-INPUT

LSOO6901

Figure 2: Symbol

r'i

I

CAZ
OP
AMP
INPUT
AZ ANALOG
SWITCH
SECTION

DIFFERENTIAL
TO SINGLE
ENDED VOLTAGE
CONVERTER
ANALOG
SWITCH
SECTION

DIFFIN

BIAS

~

+

~l

RFI
R"

~

I

CAZ
OP
AMP
OUTPUT
ANALOG
SWITCH
SECTION

::;:-.... 1

C,

~

r-

I

AZ
INPUT

i t t

oC

0

,
LEVEL
TRANSLATORS

2

OSC

---o.OUTPUT

I

!
RC
OSCILLATOR

I

JR
DIVISION RATIO

I

!

LEVEL
I TRANSLATORS

f
STABILIZED
POWER
SUPPLY

1

'20R .32
DIVIDER NETWORK

V·

I
I

i
V

80006101

Figure 3: Functional Diagram

4-24
Note: All typical values have beEm guaranteed by characterization and are not tested.

.O~O[l

ICL7605/ICL7606

!CIt

ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage (V+ to V-) ........................ 18V
DR Input Voltage ................... (V+ -8) to (V+ +0.3)V
Input Voltage (C1, C2, Ca, C4 +DIFF IN, -DIFF IN,
-INPUT, BIAS, OSC),
(Note 1) ......................... (V- -0.3) to (V+ +0.3)V
Differential Input Voltage (+ DIFF IN to -DIFF IN)
(Note 2) ......................... (V- -0.3) to (V+ +0.3)V
Duration of Output Short Circuit (Note 3) ........ Unlimited

Continuous Total Power Dissipation (Note 4) ..... 500mW
Operating Temperature Range: .
ICL7605/1CL7606CJN ..................... 0 to + 70°C
ICL760511CL76061JN ............... -25°C to +85°C
ICL7605I1CL7606MJN ............ -55°C to +125°C
Storage Temperature Range ............ -65°C to + 150°C
Lead Temperature (Soldering, 10sec) ................. 300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating cond~ions for extended periods may affect device reliabil~.
Note 1: Due to the SCR structure inherent in all CMOS devices, exceeding these limits may cause destructive latch up. For this reason, it is recommended that
no inputs from sources operating on a separate power supply be applied to the 7605/6 before its own power supply is established, and that when
using multiple supplies, the supply for the 7605/6 should be turned on first.
Note 2: No restrictions are placed on the differential input voltages on either the + DIFF IN or - DIFF IN inputs so long as these voltages do not exceed the
power supply voltages by more than 0.3V.
Note 3: The outputs may be shorted to ground (GND) or to either supply (V + or V~). Temperatures and/or supply voltages must be limited to insure that the
dissipation ratings are not exceeded.
Note 4: For operation above 25°C ambient temperature, derate 4mW/oC from 500mW above 25°C.

ELECTRICAL CHARACTERISTICS
Test Conditions:
SYMBOL
Vos

v+ = +5V, v- = -5V, TA = +25°C, DR pin connected to V+ (fCOM~160Hz, fCOMl ~80Hz),
Cl = C2 = Ca = C4 = 1j.1F, Test Circuit 1 unless otherwise specified.

PARAMETER
Input Offset Voltage

TEST CONDITIONS
RsS lkn
MIL version over temp.

AVOS/AT

Average Input Offset
Voltage Temperature
Coefficient (Note 5)

Low or Med Bias Settings

AVos/At

Long Term Input
Offset Voltage Stability

Low or Med Bias Settings

CMVR

Common Mode Input Range

CMRR

Common Mode Rejection Ratio

PSRR

Power Supply Rejection Ratio

-IBIAS

-INPUT Bias Current

en(P'P)

Equivalent Input Noise
Voltage peak·to·peak

P
...

Low
Med
High
Med

VALUE
MIN

Bias Setting
Bias Setting
Bias Setting
Bias Setting

TYP

MAX

±2
±2
±7

±5

0.01
0.01
0.05

-55°C> TA > +25°C
+25°C > TA > +B5°C
+ 25°C> TA > + 125°C

,.v
±20

,.V
,.V
,.V

0.2
0.2
0.2

,.vrc
,.vrc
,.vrc

0.5
-5.3

,.V/Year
+5.3

Case = 0, DR connected to V +, Ca = C4 = I,.F
Cose = I,.F, DR connected to GND, Ca = C4 = I,.F
COSC = I,.F, DR connected to GND, Ca = C4 = 10,.F

94
100
104

Any bias setting, fc = 160Hz
(Includes charge injection currents)

0.15

Low Bias Mode
Med Bias Mode
High Bias Mode
All Bias Modes

en

Equivalent Input
Noise vollege

Band Width
0.1 to 1.0Hz

AVOl

Open Loop Voltage Gain

Rl=10kn

±VO

Maximum Output
Voltage Swing

Rl = lMn
Rl = l00kn
Rl = 10kn

Low Bias Setting
Med Bias Setting
High Bias Setting

Positive Swing
Negative Swing

GBW

Bandwidth of Input
Voltage Translator

Ca = C4 = I,.F

All Bias Modes

fCOM

Nominal Commutation
Frequency

Cose- O

fCOM1

Nominal Input Converter
Commutation Frequency

Casc=O

VBH
VBM
VBl

Bias Voltage
required to set
Quiescent Current

Low Bias Setting
Med Bias Setting
High Bias Setting

IBIAS

Bias (Pin 8) Input Current

90
90
80

V
dB
dB
dB
dB

110

Band Width
0.1 to 10Hz

UNIT

1.5

nA

4.0
4.0
5.0

,.V
,.V
,.V

1.7

,.V

105
105
100

dB
dB
dB

±4.9
±4.8

V
V
V
V

+4.4
-4.5
10

Hz

DR Connected to V +
DR Connected to GND

160
2560

Hz
Hz

DR Connected to V +
DR Connected to GND

80
1280
V+
GND

Hz
Hz

y+ -0.3
y- +1.4
Y- -0.3

Y-

±30

4-25
Note: All typical values have been guaranteed by characterization and are not tested.

V+ + 0.3
V+ -1.4
V- +0.3

V
V
V
pA

P
c:

-

2
_

.D~DIl

!cp ICL7805/ICL7808

a:::.

I

i

ELECTRICAL CHARACTERISTICS (CO NT.)
VALUE
SYMBOL

TEST CONDITIONS

PARAMETER

UNIT
MIN

:s YOR :s Y + + 0.3

lOR

Division Ratio Input
Current

y+ -S.O

YDRH
VORL

DR Yoltage require"+1

S~

.:.r

-2

~~0: -3 I\,

~INJi..TING

...... 1000.

-5

1000

100

0P618401

ffi

5

.a

4

0:
0:

t

iil

j"-...

.......

v+·y- = 10 VOLTS
NO LOAD
NO INPUT

3

-r-

MED BIAS

o

10k

LOBIAS

LOBIAS

-50 -25

~
:a

OP018601

"l'oo..
losc - 5.2 k~Z r
Fo, Cose ~ 0 pF

lk

I'-...

~

-

0:

~

r>..

::1100

--

~

10

0
ZS
50 75 100 lZS
TA • AMBIENT TEMPERATuRE"C

1

10'

100

0P018eQI

FREQUENCY RESPONSE OF THE 10Hz
LOW PASS FILTER USED TO MEASURE NOISE
(TEST CIRCUIT 2),

AMPLITUDE RESPONSE OF THE INPUT
DIFFERENTIAL TO SINGLE ENDED VOLTAGE
CONVERTER

~

TA - +25°C
(V-,V-) = 5 VOLTS
C, = C2 = C3 = C. = 1~P.

.a

"

h~!D=B,:Hz

0

I
_T~=lzslJ

\
\

~
I

II

I

~l'

I

~IASIN

"-

: ,REGION

10

1000

COSC· OSCILLATOR CAPACITANCE· pF

0P018701'

"-

100

1,000

T

TA = 25"C
~ < IV+·V 1< 10 VOLT.S=

~

........

2

.-.

246
8
W
U
"
~
,Y+.V-, • SUPPLY VOLTAGE· VOLTS

OP018S01

%

HI'I~

MED BIAS

OSCILLATOR FREQUENCY AS A FUNCTION OF
EXTERNAL CAPACITIVE LOADING
N

-J.

o

lOOk

lk
10k
RL • LOAD RESISTANCE

SUPPLY CURRENT AS A FUNCTION OF
TEMPERATURE

6

~

...

-4

INPUT CURRENT

ICOM· COMMUTATION FREQUENCY· Hz

...

TA = ZSOC
NO LOADNO INPUT

TA = ZSoC
fIV+ ·V-, = 10V
RL C NNECTED TO GND_

~

~~-1

100

1

......HIBIAS

"
1/

0

I!: 0

I)

1/

~

10

>+4

J

\ V

j~-I00
1-50

I

II

-

-+5

I

I

~ti-400
t=~-350

0:0:

SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE

1\
"-

,

1\

10,GOO

2

345

.10

20 304050

100

I • FREQUENCY· Hz

I - FREQUENCY - Hz
QP018901

QP019001

4-27
Note: All typical values have been guaranteed by characterization and are not tested.

INPUT'
GND OR VOLTAGE
1 AZ -DIFF IN 11
,.-----10 -IN +DIFF IN 17

.,e.,

+DIFFIN

BETWEEN
(V- +0.3) AND
(V- -iI.3) VOLT
1~F

'C.

rI
I

-DrFF IN

-1
I
I OUTPUT

I

S~2

6C.
7V-

IBIAS

OSCll

• OUTPUT V- ,.

+5V

90006201

Figure 6: Simplified Block Diagram

OUTPUT
1M
1K

VOLTAGE GAIN = 1000

The ICL760S/ICL7606 have approximately constant
equivalent input noise VOltage, CMRR, PSRR, input offset
voltage and drift values independent of the gain configuration. By comparison, hybrid-type modules which use the
traditional three op. amp configuration have relatively poor
performance at low gain (1 to 100) with improved performance above a gain of 100.
The only major limitation of the ICL760SIICL7606 is its
low-frequency operation.(10 to 20Hz maximum). However in
many applications bandVliidth is not the most important
parameter.

TC024911

Figure 4: Test Circuit 1

CAZ Op Amp Section
VOUT

Operation of the CAl op-amp section of the ICL760S/
ICL7606 is best iII!Jstrated by referring. to Figure 7. The
basic amplifier configuration; represented by the large
triangles,. has one more input than does a regular op ampthe AZ; or auto-zero terminal. The voltage on the AZ input
is that level at which each of the internal op amps will be
auto-zeroed. In Mo<;le A, op amp # 2 is connected in a unity
gain mode through on-chip analog switches. It charges
external capacitor C2 to a voltage equal to the DC input
offset voltage of the amplifier plus the instantaneous lowfrequency. noise voltage. A short time later, the analog
switches reconnect the on-chip op amps to the configuration shown in Mode B. In this mode, op amp #2 has
capacitor C2 (which is charged to a voltage equal to the
offset and noise voltage of op amp #2) connected in series
to its non-inverting ( + ) input in such a manner as to null out
the input offset and noise voltages of the amplifier. While
one of the on-chip op amps is processing the input Signal,
the second op amp is in an auto"zero mode, charging a
capacitor to a voltage equal to its equivalent DC and low
frequency error voltage. The on~chip amplifiers are connected and reconnected at a nite designated as the commutation frequency (feOM), so that at all times one or the other
of the on-chip op amps is processing the input Signal, while
the voltages on capaCitors Cl and C2 are being updated to
compensate for variables such as low frequency noise
voltage arid input offset voltage changes due to temperature, drift or supply voltages effects.

,TC025011

Figure 5: Test Circuit 2
DC to 10Hz Unity Gain Low Pass Filter

DETAILED DESCRIPTION
CAZ Instrumentation Amp Overview
The CAZ instrumentation amplifier operates on principles
which are very' different from thoSe of the conventional
three op-amp deSigns, which must use ultra-precise
trimmed resistor networks in order to achieve acceptable
accuracy. An important advantage of the ICL760SIICL7606
CAZ instrumenta~ion amp is the provision ·for self-compensation of internal error voltages, whether they are derived
from steady-state conditions, such as temperature and
.supply voltage fluctuations, or are du~ to long term drift.
The CAl instrumentation amplifier is constructed with
monolithic CMOS technology, and consists of three distinct
sections, two analog and one digital. The two analog
sections - a differential to single-ended voltage converter,
and a CAZ op amp - have on-chip analog switches to
steer the input Signal. The analog switches are driven from
a self-contained digital section which consists of an RC
oscillator, a programmable divider, and associated voltage
translators. A functional layout of the ICL760SIICL7606 is
shown in Figure 6.

4-28
Note: All typical values have bean guaranteed by characterization and are not tested.

ICL7605/ICL7606

~

________~~O~UTPUT

.v-r__________~~O~UTPUT

80006301

Figure 7: Diagrammatic representation of the 2 half cycles of operation of the CAZ OP AMP.

c, -+------......-------t

c, -+-+-----;

INFUT

FROMFIQ4
AZ

OUTPUT

NPUT

..

(100k!l)

-INPUT - - - - ' - - - - ' - - - '

~

(C._TATION
FREQUENCY)

er

CL
DS017401

Figure 8: Schematic of analog switches connecting each Internal OP AMP
.
to Its inputs and output.

4-29
Note: All tvDical values have been auaranteed bv characterization and are not tested.

I

··.D~Dll

ICL1605/1CL7606

!:i

S:!

!

..

r--~-GND

-DlFf' IN

OR 'REFERENCE VOLTAGE

_-+-....
s,

'---1

'1M fNquencf.1 wNch ..... A I 8 .... cycled "
known .. .... INPUT COMMUTATION FREQUENCV

{So
'--DS[).17501

Figure 9: Schematic of the differential. to single ended voltage. converter
reference voltage to the input of the CAZ instrumentation
amp. The output signal of this configuration is shown in
Figure 10, where the voltage steps equal the differential
voltage (VA-VB) at commutation times a, b, c, etc. The
output waveform thus represents all information contained
in the input signal from DC up to the commutation frequency, including commutation and noise voltages. Sampling
theory states that to preserve the information to be processed, at least, two samples must be taken within a period
(1/f) of the highest frequency being sampled. Consequently
this scheme preserves information up to the commutation
frequency. Above the commutation· frequency, the input
signal is translated to a lower frequency. This phenomenon
is known as aliasing. Although the output responds to inputs
above the commutation frequency, the frequencies of the
output responses will be below the commutation frequency.

Compared to the standard bipolar or FET input op amps,
the CAZ amp scheme demonstrates a number of important
.advantages:
Effective input offset voltages can be reduced from
1000 to 10,000 times without trimming.
Long-term offset voltage drift phenomena can be
compensated and dramatically reduced.
Thermal effects can be compensated for over a
wide operating temperature range. Reductions can
be as much as 100 times or better.
Supply voltage sensitivity is reduced.
CMOS processing is ideally suited to implement the CAZ
amp structure. The digital section is easily fabricated, and
the transmission gates (analog switches) which connect the
on-chip op amps can be constructed for minimum charge
injection and the widest operating voltage range. The
analog section, which includes the on-chip op amps,
contributes performance figures which are similar to bipolar
or FET input designs. The CMOS structure provides the
CAZ op-amp with open-loop gains of greater than 100dS,
typical input offset voltages of ±5mV, and ultra-low leakage
currents, typically 1pA.
The CMOS transmission gates connect the on-chip op
amps to external input and output terminals, as shown in
Figure 8. Here, one op amp and its associated analog
switches are required to connect each on-chip op amp, so
that at any time three switches are open and three switches
are closed. Each analog switch consists of a P-channel
transistor in parallel with an N-channel transistor.

t---1-__

OUTPUT
VOLTAGE

--~~--1---J.,1

GNDOR
-lREFERENCE
VOLTAGE

INPUT COMMUTATION
PERtOD (1IfCOM1)

DIFFERENTIAL-TO-SINGLE-ENDED UNITY
GAIN VOLTAGE CONVERTER

WF014201

Figure 10: Input to Output Voltage
waveforms from the differential to single
ended voltage converter. For additional
information, see frequency characteristics in
Amplitude Response of the Input Differential
to single ended voltage converter graph on
page 5.

An idealized schematic of the voltage converter block is
shown in Figure 9. The mode of operation is quite simple,
involving two capacitors and eight switches. The switches
are arranged so that four are open and four are closed. The
four conducting switches connect one of the capacitors
across the differential input, and the other from a ground or

4-30

Note: All typical values have been guaranteed by characterization and are not tested.

ICL7605/ICL7606

'AZ -DIFF IN 10

, - - - - i . -IN ...OIFF IN 17
3C<$

:g;

CJ'6

C,13

7 V-

DR12

• BIAS
9

,.

ICl7606 g~~:

6 C2

11

'2

OSC11

OUTPUT

V'

y'10

,."

,.
15

10k!!

1M!!
At
1.5Hz

At + A2
Av = -R-,- = 101 TIMES

,.
17

LOW PASS
FILTER

I

.

o.'~F

19

_
20

OSC 140
OSC 2"
OSC 3"
TEST"
REF HI"
REF LO"
C REF"
C REF"
COMM"
IN HI31
IN LO"
AZ" .
BUFF"

....

lOOk

V·
V-

•

INT27
V· ..

ICL7I06

"

22

21

-::-

}

LCD DISPLAY

AF028201

Figure 11: 3·1/2 Digit Digital Readout Torque Wrench
The vOltage converter is fabricated with CMOS analog
switches, which contain a parallel combination of P-channel
and N-channel transistors. The switches have a finite ON
impedances of 30kn, plus parasitic capacitances to the
substrate: Because of the charge injection effects which
appear at both the switches and the output of the voltage
converter, the values of capacitors .C3 and C4 must be
about 1j.lF to preserve signal translation accuracies to
0.01%. The 1j.lF capacitors, coupled with the 30kn equivalent impedance of the switches, produce a low-pass filter
response from the voltage converter which is down approximately 3dB at 10Hz.

the AID. In order to set the full-scale reading, a value of
gain for the ICL7S05/1CL7S0S instrumentation CAZ amp
must be selected along with an appropriate value for the
rEiference voltage. The gain should be set so that at full
scale, the output will swing about 0.5V. The reference
voltage required is about one-half the. maximum output
swing, or approximately 0.25V.
In this type of system, only one adjustment is required.
Either the amplifier gain or the reference voltage' must be
varied for full-scale adjustment. Total current consumption
of all Circuitry, less the current through the strain .ga\lge
bridge, is typically 2mA. The accuracy is limited only by
resistor ratios and the transducer.

APPLICATIONS
Using the ICL760511CL7606 to Build a
Digital Readout Torque Wrench

SOME HELPFUL HINTS
Testing the ICL7605/1CL7606 CAZ
Instrumentation Amplifier

A typical application for the ICL7S05/1CL7S0S is in a
strain gauge system, such as the digital readout torque
wrench circuit shown in Figure S. In this application, the
CAZ instrumentation amplifier is used as a preamplifier,
taking the differential voltage of the bridge and converting it
to a single-ended voltage referenced to ground. The signal
is then amplified by the CAZ instrumentation amplifier and
applied to the input of a 3-1/2 digit dual-slope AID
converter which drives the LCD panel meter display. The
AID converter device used in this instance is the Intersil
ICL71 OS.
In the digital readout torque wrench circuit, the reference
voltage for the ICL710S is derived from the stimulus applied
to the strain gauge, to utilize the ratiometric capabilities of

Figure 4 and 5 (Test Circuits) provide a convenient
means of·· measuring most of the important electrical
parameters of the CAZ instrumentation amp. The output
signal can be viewed on an oscnloscope after being fed
through a low-pass filter. It is recommended that for most
applications,a low-pass filter of about 1.0 to 1.5Hz be used
to reduce the peak-to-peak noise to about the same level
as the input offset voltage.
.
The output low-pass filter must be a high-input impedance RCtype - not simply a capaCitor across the feedback
resistor R2. Resistor and capacitor-values of about 100kn
and 1.0j.lF are necessary so that the output load impedance
on the CAZ op-amp is greater than 100kn.

4--31
Note: All typical values have been guaranteed by characterization and are not tasted.

EI
~

IID~Oll

IICL1605tlCL7606
;;.;,

51!

!
'a

GND~

____

~

______

~

____

~r-

____

A.f\

~

INPUT
AC

R,ouReE

WAVEFORMS

OUTPUT
VOLTAGE

WF014401

WF014301

Figure 12: Effect of a load capacitor on output voltage waveforms.

'Bias Control

capacitor produces an area error in the output waveform,
and hence an effective gain error. The output low-pass filter
must be of a high-impedance type to avoid these area
errors. For example, a 1.SHz filter will require a 100kn
resistor and a 1.0pF capacitor, or a 1Mn resistor and an
0.1 pF capacitor.

The on-chip op amps consume over 90% of the power
required by the ICL760~/ICL7606. For this reason, the
internal op amps have eXternally~ programmable bias levels. These levels are,set by cOnnecting the elAS terminal to
either V + , GND, or V-, for lOW, MEQ or HIGH BIAS levels,
respectively. The difference between each "bias setting is
about a factor of 3, allowing a 9:1 ratio of quiescent supply
current versus bias setting. This current programmability
provides the user with a choice of device power dissipation
levels, slew rates (the higher the slew rate, the better the
recovery from commutation spikes), and offset errors due to
"IR" Voltage drops and thermoelectric effects (the higher
the power dissipation, the higher the input offset error). In
most cases, the medium bias (MED BIAS) setting will be
found to be the best choice.

Oscillator and Digital Circuitry
Considerations
The oscillator has been designed to run free at about
S.2kHz when the OSC terminal is open circuit. If the full
divider network is used, this will result in a nominal
commutation frequency of approximately 160Hz. The commutation frequency is that frequency at which the on-chip
op amps are switched between the signal processing and
the auto-zero modes. A 160Hz commutation frequency
represents the best compromise between input offset
voltage and low frequency noise. Other commutation frequencies may provide optimization of some parameters, but
always at the expense of others.
The oscillator has a very high output impedance, so that
a load of only a few picofarads on the OSC terminal will
cause a significant shift in frequency. It is therefore recommended that if the natural oscillator frequency is desired
(S.2kHz) the terminal remains open circuit. In other instances, it may be desirable to synchronize the oscillator
with an external clock source, or to run it at another
frequency. The ICl760S/ICL7606 CAZ amp provides two
degrees of flexibility in this respect. First, the DR (division
ratiO) terminal allows a choice of either dividing the oscillator by 32 (DR terminal to V +) or by 2 (DR terminal to GND)
to obtain the commutation frequency. Second, the oscillator
may have its frequency lowered by the addition of an
8Idernal capacitor connected between the OSC terminal
and the V + or system GND terminals; For situations which
require that the commutation frequency be synchronized
with a master clock, (Figure 13) the OSC terminal may be
driven from TIL logic (with resistive pull-up) or by CMOS
logic, provided that the V+ supply is +SV (±10.%) and the
logic driver also operates from a similar voltage supply. The
reason for this requirement is that the logic section (including the OSCillator) operates from an internal -SV supply,
referenced to V+ supply, which is not accessible externally.

Output Loading (Resistive)
With a 10kn load, the output voltage swing can vary
across nearly the entire supply voltage range, and the
device can be used with I,oads as low as 2kn.
However, with loads of less than SOkn, the on-chip op
amps will begin to exhibit the characteristics of transconductance amplifiers, since their respective output impedances are nearly SOkn each. Thus the open-loop gain is
20dB less with a 2kn load than it would be with a 20kn
load. Therefore, for high gain configurations requiring high
accuracy, an output load of 100kn or more is suggested.
There is another consideration in applying the CAZ
instrumentation op amps which must not be overlooked.
This is the additional power dissipation of the ,chip which will
result from a large output voltage SWing into a low resistance load. This added power dissipation can affect the
initial input offset voltages under certain conditions.

Output Loading (Capacitive)

,

In many applications, it is desirable to include a low-pass
filter at the output of the CAZ instrumentation op' amp to
reduce' high-frequency noise outside the desired signal
passband. An obvious solution when using a conventional
op amp would be to place a capacitor across the external
feedback resistor and thus produce a low-pass filter.
However, with the CAZ op amp concept this is not
possible because of the nature of the commutation spikes.
These voltage spikes exhibit a low-impedance characteristic in the direction of the auto-zero voltage and a highimpedance characteristic on the recovery edge, as shown
in Figure 12. It can be seen that the effect of a large load

ThermoelectriC Effects
The ultimate limitations to ultra-high-sensitivity DC amplifiers are due to thermoelectric, Peltier, or thermocouple
effects in electrical junctions consisting of various metals,
(alloys, silicon, etc.) Unless all junctions are at precisely the
4-32

Note: All typical values have been guaranteed by characterization and are not tested.

ICL7605/ICL7606
same temperature, small thermoelectric voltages will be
produced, generally about 0.1 /lV rc. However, these voltages can be several tens of microvolts per ·C for certain
thermocouple materials.

switching transients which occur at both the input and
output terminals because of commutation effects. These
transients have a frequency spectrum beginning at the
commutation frequency, and including all of the higher
harmonics of the commutation frequency. Assuming that
the commutation frequency is higher than the highest inband frequency, then the commutation transients can be
filtered out with a low-pass filter.
The input commutation transients arise when each of the
on-Chip op amps experiences a shift in voltage which is
equal to the input offset voltages (about 5-10mV), usually
occurring during the transition between the signal processing mode and the auto-zero mode. Since the input capacitances of the on-chip op-amps are typically in the 10pF
range, and since it is desirable to reduce the effective input
offset voltage about 10,000 times, the offset voltage autozero capaCitors C1 and C2 must have values of at least
10,000 x 10pF, or 0.1/lF each.
The charge that is injected into the input of each op amp
when being switched into the signal processing mode
produces a rapidly-decaying voltage spike at the input, plus
an equivalent DC input bias current averaged over a full
cycle. This bias current is directly proportional to the
commutation frequency, and in most instances will greatly
exceed the inherent leakage currents of the input analog
switches, which are typically 1.0pA at an ambient temperature of 25°C.
The output waveform in Figure 4 (with no input signal) is
shown in Figure 14. Note that the equivalent noise voltage
is amplified 1000 times, and that due to the slew rate of the
on-Chip op amp!!, the input transients of approximately 7mV
are amplified by a factor of less than 1000.

TTL
OR
CMOS
LOGIC

USE RL - 22k1l
FOR TTL LOGIC
(NOT NEEDED FOR CMOS)
LC008101

Figure 13: ICL7605 being c::locked from
external logic into the oscillator terminal.
In order to realize the extremely low offset voltages which
the CAZ op amp can produce, it is necessary to take
precautions to avoid temperature gradients. All components
should be enclosed to eliminate air movement across
device surfaces. In addition, the supply vol.tages and power
diSSipation should be kept to a minimum by use of the MED
BIAS setting. Employ a high impedance load and keep the
ICL7605/1CL7606 away from equipment which dissipates
heat.

Component Selection
The four capacitors (C1 thru C4) should each be about
1.0/lF. These are relatively large values for non-electrolytic
capacitors, but since the voltages stored on them change
significantly, problerils of dielectric absorption, charge
bleed-off and the like are as significant as they would be for
integrating dual-slope AID converter applications. Polypropylene types are the best for Ca and C4,although Mylar
may be adequate for C1 and C2'
Excellent results have been obtained for commercial
temperature ranges using several of the less-expensive,
smaller-size capaCitors, since the absolute values of the
capacitors are not critical. Even polarized electrolytic capaCitors rated at 1.0/lF and 50V have been used successfully at room temperature, although no recommendations
are made concerning the use of such capaCitors.

OUTPUT
VOLTAGE

WF014511

Figure 14: Output waveform from Test
Circuit 1.

Layout Considerations
Care should be exercised in positioning components on
the PC board particularly the capaCitors C1, C2, Ca and C4,
which must all be shielded from the asc terminal. Also,
parasitic PC board leakage capacitances associated with
these four capaCitors should be kept as low as possible to
minimize charge injection effects.

Commutation Voltage Transient Effects
Although in most respects the CAZ instrumentation
amplifier resembles a conventional op amp, its prinCipal
applications will be in very low level, low-frequency preamplifiers limited to DC through 10Hz. The is due to the finite

4-33
Note: All typical values have been guaranteed by characterization and are not tested.

= ICL76XX

~ ICL76XX, Series Low Power
~

CMOS Operational Amplifiers
GENERAL DESCRIPTION

FEATURES

The ICL761X1762X1763X1764X series is a family of
monolithic CMOS operational amplifiers. These. devices
provide the designer with high performance operation at low
supply voltages and selectable quiescent currents, and are
an ideal design tool when ultra low input current and low
power dissipation are desired.
The basic amplifier ~iII operate at supply voltages
ranging from ± 1.0V to ±av, and may be operated from a
single Lithium cell.
A unique quiescent current programming pin allows
settingof.standby current to 1mA, 100,..A, or 10,..A, with no
external components. This results in power consumption as
low as 201lW. Output swings range to within a few millivolts
of the supply voltages.
Of particular significance is the extremely low (1 pAl input
and 1012n input
current, input noise current of .01 pAl
impedance.. These features optimize Performance in very
high source impedance applications.
The inputs are internally protected and require no special
handling procedures. Outputs are fully protected against
short circuits to ground or to either supply.
AC performance is excellent, with a slew rate of 1.6V/ /lS,
and unity gain bandwidth of 1MHz at IQ 1mAo
Because ot the low power dissipation, operating temperatUres and drift are quite low. Applications utilizing these
features may include stable instruments, extended life
designs, or high density packages.

•
•
•
•
•
•
•
•
•
•

Wide Operating Voltage Range ±1.0V to ±8V
High Input Impedance - 1012n
Programmable Power Consumption - Low As
20llW
Input current Lower Than BIFETs-Typ 1pA
Available As Singles, Dlj8ls, Triples, and Quads
Output Voltage Swings to Within Millivolts Of Vand V+
Low Power Replacement for Many Standard· Op
Amps
Compensated and Uncompensated Versions
Inputs Protected to ±200V (lCL7613/15)
Input Common Mode Voltage Range Greater
Than Supply RaUs (ICL7612)

APPLICATIONS

YHz,

•
•
•
•
•
•

Portable Instruments
Telephone Headsets
Hearing Aid/Microphone Amplifiers
Meter Amplifiers
Medical Instruments
High Impedance Bu·ffers

=

SELECTION GUIDE
DEVICE. NOMi:NCLATURE.
ICL76XX

X

x

SPECIAL FEATURE CODES

xx

C
E
H
I
L
M

.L

Package Code
TV - TO-99, B pin
PA - Plastic B pin Minidip
PO - 14 pin Plastic Dip
PE - 16 pin Plastic Dip
JO - 14 pin CERDIP
JE - 16 pin CEROIP
10 - Dice
L . -_ _ Temperature Range
C ~ O"C to 70"C
M = -55"C to + 125"C
' - - - - - - V o s Selection
A=2mV
B=5mV
C= 10mV
0= 15mV
E = 20mV

o
P
V

4-34
Note: All typical values have been guaranteed by characterization and are not tested.

=
=

=
=

=
=
=

=

INTERNALLY COMPENSATED
EXTERNALLY COMPENSATED
HIGH QUIESCENT CURRENT (1 mAl
INPUT PROTECTED TO ±200V
LOW QUIESCENT CURRENT (10jlA)
MEDIUM QUIESCENT CURRENT (100jlA)
OFFSET NULL CAPABILITY
PROGRAMMABLE QUIESCENT CURRENT
EXTENDED CMVR

302060-002

ICL76XX
ORDERING INFORMATION
NUMBER OF
OP-AMPS IN
PACKAGE,AND
SPECIAL
FEATURES
(SEE ABOVE)

BASIC
PART
NUMBER

ICL7611
ICL7612
ICL7613
ICL7614
ICL7615

SINGLE OP-AMP:
C, 0, P
C, 0, P, V
C, I, 0, P
E, M, 0
E, I, M, 0

ICL7621

DUAL OP-AMP:
C, M

ICL7622

DUAL OP-AMP:
C, M,O

ICL7631
ICL7632

TRIPLE OP-AMP:
C, P
P(3)

ICL7641
ICL7642

QUAD OP-AMP:
C, H
C, L

PACKAGE TYPE AND SUFFIX
a-LEAD TO-99

a-PIN
MINIDIP

a-PIN
SOIC

PLASTIC
DIP (1)
O·C to
+70·C

O·C to
+70·C

-55·C to
+ 125·C

O·C to
+70·C

O·C to
+70·C

ACTV
BCTV
DCTV

AMTV
BMTV

ACPA
BCPA
DCPA

DCPA
DCBA

ACTV
BCTV
DCTV

AMTV
BMTV

ACPA
BCPA
DCPA

CERAMIC DIP (1)
O·C to
+70·C

-55·C to
+ 125·C

DICE

DID

DID
ACPD
BCPD
DCPD

ACJD
BCJD
DCJD

AMJD
BMJD

CCPE
ECPE

CCJE
ECJE

CMJE

CCPD
ECPD

CCJD
ECJD

CMJD

DID

E/D

E/D

NOTES: 1. Duals and quads are available in 14 pin DIP package, triples in 16 pin only.
2. Ordering code must consist of basic part number and package suffix, e.g., ICL7611 BCPA.
3. ICL7632 is not compensatable. Recommended for use in high gain circuits only.
"Parameter MiniMax Limits guaranteed at 25·C only for DICE orders.

DEVICE
ICL7611XCPA
ICL7611XCTV
ICL7611XMTV
ICL7612XCPA
ICL7612XCTV
ICL7612XMTV
ICL7613XCPA
ICL7613XCTV
ICL7613XMTV

DESCRIPTION
Internal compensation, plus
offset null capability
and external 10 control

PIN ASSIGNMENTS
8 PIN DIP (TOP VIEW)
(outline dwg PAl

TO-99 (TOP VIEW)
(outline dwg TV)
10 SET

OFFSET

IQ SET

-IN

v+

+IN

OUT
QFFSET

v• Pin 7 connected to case.
8 PIN DIP (TOP VIEW)
(outline dwg SA)

vFigure 1: Pin Configurations

4-35
Note: All typical values have been guaranteed by characterization and are not· tested.

ICL76XX
DEVICE
ICL7614XCPA
ICL7614XCTV
ICL7614XMTV
ICL7615XCPA
ICL7615XCTV
ICL7615XMTV

DESCRIPTION

PIN ASSIGNMENTS

Fixed 10 (l00IlA), eX1ernal
compensation, and offset
null capability

8 PIN Dip (TOP VIEW)
(outline dwg PAl

TO·99 (TOP VIEW)
(outline dwg TV)
SOI~

COMP

COMP

OFFSET

-IN

y•

• ,N

OUT

y.

'Pin 7 connected to
ICL7621XCPA
ICL7821XCTV
ICL7621XMTV

Dual op amps with internal
compensation; 10 fixed
at 10011A
Pin compaptible willi
Texas Inst. TL082
Motorola MC1458
Raytheon RC4558

case.
• PIN DIP (TOP VIEW)
(outline dwg PAl

TO'99 (TOP VIEW)
(outline dwg TV)

y' OUT. -IN. +IN.

y'

OUT. -IN. +IN.

y'Pin 8 connected to
ICL7822XCPD

case.
14 PIN OIP.(TOP VIEW)
(outline dwgs JD, PO)

Dual op amps with eX1ernal
compensation and offset
null capability; Ia fixed
at 10011A
Pin compatible with
Texas Insl TL083
Fairchild 1lA747

OFFSET

OFFSET. Y' OUT. N/C OUT.

Y'

OFFSET.

14

Nole: Pins 9 and 13 are internally connected.

Figure 1: Pin Configurations (Cont.)

4-38
Note: All typical values have been guaranteed by characterization and are not tested.

y.

ICL76XX
DEVICE
ICL7631XCPE
ICL7632XCPE

DESCRIPTION

PIN ASSIGNMENTS
16 PIN DIP (TOP VIEW)
(outline dwgs JE, PEl

Triple op amps with internal
compensation (lCL7631) and
no compensation (ICL7632).
Adjustable 10
Same pin configuration as
ICLB023.

I.,.

100

SET

y-

SET

16

•
-INa

+fNa

OUT.

V+

10(:

-INe

SET

Note: pins 5 and 15 are internally connected.

ICL7641XCPD
ICL7642XCPD

Quad op amps with internal
compensation.
10 fixed at lmA (ICL7641)
10 fixed at 1011A (lCL7642)
Pin compatible with
Texas Instr. TLOB4
National LM324
Harris HM741

14 PIN DIP (TOP VIEW)
(outline dwg JD, PO)

OUTD -INo

+INo

V-

+INc

-INc

OUTc

8

U

•
Figure 1: Pin Configurations (Cont.)

4-37
Note: AU typical values have been guaranteed by characterization and are not tested.

+INc

OU"",,T
STAGE
o

ONPUT
STAGE

r--L---o

.
+

® >--_____..

OFFSET

+INPUT

.,CD

ouv

..

'.

OUTPUT

y-

y'

o
~INPUT

y-

r--- --.--- - - - - - -

I

j
!
r

TABLE OF JUMPERS

leL 7611
ICL.7613

: :~~;:!:.

1

!

I

!

8. F, H
B. F. H
8, r.H

tel·J6l2

ICI..·7821
leL 7622
ICI..-7631
ICL·7632

ICl·7641
ICL·7642

.1'

C.D. E
C,D, E
E
E

e.
e.

a.F,"

8.F.H

e.G
A.E

NOTES:

oy·--"H....----

.A-"

>-

~

i--'

I 10 = l00"A

100

()

!

....-

10'" 10;,.A;

10

. .A""

'02
'-10' 'OpA

'0

10

12

14

16

+25

+50

+75

FREE·AIR TEMPERATURE

SUPPLY VOL T AGE - VOL 15

'000

I

".15
CD

-

RL:z 10K!!
IQ""lmA

'0

~
0

50

-25

+25

i!:

I

=
-

~

~

90

~
l!!

lIS

~
~>

80

IQ= l()Qs.1A

• ~"""A

75

>-

'l

.......

70

65

-75

-so

-25

'06
VSUpp·,OV

r- ~A

0

+25

r-~~.,~ ~
'o-'mA

r--_~_

102

r""'"

,
~1S

.. SO

+15 qOQ +125

FREE-AIR TEMPERATURE - C

-25

0

+50

+25

+75 +100 +125

0P016701

EQUIVALENT INPUT NOISE
VOLTAGE AS A FUNCTION OF

t~

0:. 600

soo

~
>
l!l0

400

~

§

g

E

200

I!::\.I
' i I:
.i

'00

11:1
' I !:

,~

,

'0

::

T"

' r-... ,.....

,rv

12

'0

'K

'OK

FREQUENCY - Hz

-

,

0P017001

CPO, ....

4-44
Note: All typicel values have been guaranteed by characterization and are not tested.

~

1\

TAo • +2S'C

I
'o"mA
---'o"OpA

•..•• '0 -100""

,
,

,

1.\ ).\""\

v...,,,,.,

,

\

i

v.....

o
'00

i

'K

,2V

.

,

~

\

\

\

r,,__ r--,... ,

t?~'.:

~

I

""\

~

II

r'SV

.

r--_

)J

,. v.u,;;.

.~

I

!'

'00

,

'6

il
:!

rfFII:: · :I
++-

~

3V " VsUPP " llV

300

I-

I

TA "' ....25 C

i~!

Z

:i


~Illli
~.J"ill; Ii iI

I-

OP016801

PEAK-To-PEAK OUTPUT VOLTAGE AS
A FUNCTION OF FREQUENCY

FREQ~ENCY

"~

~ ......

-50

.......
....... r-.....

FREE·AlR TEMPERATURE _·C

FREQUENCY - Hz

....... .......

+100 +125

OP016501

+75 +100 +125

---- .
-

~ r-....

+75

COMMON MODE REJECTION RATIO
AS A FUNCTION OF FREE-AIR
TEMPERATURE

r-

15

~~

+50

5 '0r--+-t--+-~~~~~

I

~

a:

+26

FREE·AIR TEMPERATURE _·C

70

+50

VSUPP" lOV

96

-25

Co • ~r~~/~S

CPO'66OI

lo.',mA

,-60

~ 1~F!~~~~-i--r--t--1

POWER SUPPLY REJECTION RATIO
AS A FUNCTION OF FREE-AIR
TEMPERATURE
'00

./

_oc

TA" +25'C

'00 f--+-+--+-4

FREE·AIR TEMPERATURE - C

i
I
2

o.

I

a

1/

1.0

~

Vsupp '" 10 VOL TS
VOUT ., 8 VOL TS

I
-15

~

~ 1~f--+-~~~~-~-+~

I

I

/

ii

g~ 104

R L ,.. tOOK!!

'O"OOpA _

l-

S
>

>,
z

~
~

+'00 +126

OP016301

!

v- --SVOLTS

100

a:

r-

,

"

tI

--

I::!o. 'OOpA

:ia:

Y'-~5vdTS

~

-NQS'GNAL

I

~

::>

,0'

'000

vi
- y- ~ '0 vbLTS
NOlDAD

-

r-1o = '.mA

INPUT BI.AS CURRENT AS A
FUNCTION OF TEMPERAT~RE

'OK

~\

~

'OOK

'M

10M

FREOU~NCV - Hz

OP017101

ICL76XX
TYPICAL PERFORMANCE CHARACTERISTICS (CONT.)
MAXIMUM PEAK·TO·PEAK OUTPUT
VOLTAGE AS A FUNCTION OF
SUPPLY VOLTAGE

MAXIMUM PEAK·To-PEAK OUTPUT
VOLTAGE AS A FUNCTION OF
FREQUENCY

>

>

6

II

•

!

I

2

II

\

6

,

I
TA .. +125'

2
0
10K

10~ ~

'0

-Iii

II I

~

[""'.
a

TA,

:=

•

!

I

"

I

Ii!

~
lOOK

RL =

2

I·

~'IPPl Y

14

0

1/
,,.

1/

o.01

i

,

10 -tOStA

I

I

!

10

12

14

16

0P017601

>

'0'" lmA

,
2

TA

=.+25 C

.<

>

l00pF

INPUT

c,.

....
...

= l00KU
lOOp'
= +25 C

•

0

>

....

"
S
0

\

2

1--1--+--+-+ RL

'"~

\

0

6

" 10K!!

1\

J
!oUTPUT

,

VSUPP ., TOV

VSUPf' " lOV

R,
C,

......z
0

l\.
10

-2

~ -,
12

-6

~

1 mA

20

40
TIME

~

60

100

120

-"s
OPQ19101

0P035801

4--45

Note: All typical values have been guaranteed by characterization and are not tested.

1/

V
I

2

0.1

:
1.0

10

100

0P017701

VOLTAGE FOLLOWER LARGE SIGNAL
PULSE RESPONSE

VOLTAGE FOLLOWER LARGE
SIGNAL PULSE RESPONSE

a
6

= lQVOlTS
TA ,,25 C

LOAD RESISTANCE - K!!

SUP:Pl y VOLTAGE - VOLTS
OP017501

VOLTAGE FOLLOWER LARGE
SIGNAL PULSE RESPONSE

v· -V-

'V
t:=-

o

10

16

°c

0

a

!
10 -lOO/.1A

Ie;; '~A=

SUPPLY VOLTAGE - VOLTS

~
o

+}5 +100 +125

2

6

"

+50

MAXIMUM PEAK·To-PEAK OUTPUT
VOLTAGE AS A FUNCTION OF LOAD
RESISTANCE

10

1\
"12

... 25

OP017401

.1--

.0

10

0

6

I

I

I

-25

FREe.AIR TEMPERATURE _

~

.1

1/1
l i

0

o-75 -so

VOLTAGE - VOL T8

MAXIMUM OUTPUT SINK CURRENT
AS A FUNCTION OF SUPPLY
VOLTAGE

1---+--

1/,",

16

0P017301

V
1/

i

VSUPP' '" 10 VOL T5 1
10 = 1mA

12

10M

MAXIMUM OUTPUTISOURCE
CURRENT AS A FUNCTION OF
SUPPLY VOLTAGE

: i/

f"""..

I

I

OP017201

I
I

1'....

2K!~

I

1M

40

Rl '" 10K!!

..........

I
!

FREQUENCV - Hz

O~

!'--..

a

TA "+25 C ;.

I II

I

I

ii

Ii

I

~-\

30

I
RL • TOOK!!

11

-55 C

I

J\.
!\i\

12

I

Vwpp '
"lmA

I

I

0

MAXIMUM PEAK·To-PEAK VOLTAGE
AS A FUNCTION OF FREE-NR
TEMPERATURE

=lCL78xX'

a

DETAILED DESCRIJ)TION
Static Protection

Input Offset Nulling

All devices are static protected by the use ,of input
diodes. However, strong static fields should be avoided, as
it is pos~ible for the strQ,ng fields to cause degraded diode
junction characteristics, which may result in increased input'
'
leakage currents.

For those models provided with OFFSET NULLING pins,
nulling may be achieved by conne~ting a 25K pot between
the OFFSET terminals with the wiper connected to V + . At
quiescent currents of 1mA and 100pA,the nulling range
provided is adequate for all Vas selections; however with
10 = 10pA, nulling may not be possible with higher values of
Vas·

Latchup Avoidance

Frequency Compensation

Junctioncisolated CMOS circuits employ configurations
which produce a parasitic 4-layer (p-n-p-n) structure. The 4layer structure has characteristics similar to an SCR, and
under certain circumstances may be triggered into a low
impedance state resulting in excessive supply current. To
avoid this condition, no voltage greater than 0.3V beyond
the supply rails may be applied to any pin. (An exception to
this rule concerns the inputs of the ICL7613 and ICL7615,
which are protected to ±200V.) In general, the op-amp
supplies must be established simultaneously with, or before
any input signals are applied. If this i~ not posSible, the drive
circuits must limit input current flow to 2mA to prevent
latchup.

The ICL7611/12/13, 7621/22, 7631, 7641/42 are internally compensated, and are stable for closed loop gains as
low as unity with capacitive loads up to 100pF
The ICL7614/15 are externally compensated by connecting a capacitor between the COMP and OUT pins. A 39pF
capacitor is required for unity gain compensation; for
greater than unity gain applications, increased bandwidth
and slew rate can be obtained by redUCing the value of the
compensating capacitor. Since the gm of the first stage is
proportional to ViQ, greatest compensation is required
when 10=1 mAo
The ICL7632 is not compensated internally, nor can it be
compensated externally. The device is stable when lIsed as
follows:
10 of 1mA for gains ~ 20
10 of 100pA for gains ~ 10
10 of 10pA for gains ~ 5

Choosing the Proper IQ
Each device in the ICL76XX family has a similar 10 set-up
scheme, which allows the amplifier to be set to nominal
quiescent currents to 10pA, 100pA or 1mA. These current
settings change only very slightly over the entire supply
voltage range. The ICL7611/12/13 and ICL7631/32 have
an external 10 control terminal, permitting user selection of
each amplifiers' quiescent current. (The ICL7614/15, 76211
22, and 7641/42 have fixed 10 settings - refer to selector
guide for details.) To set the 10 of programmable versions,
connect the 10 terminal as follows:

High Voltage Input Protection
The ICL7613 and 7615 include on-Chip thin film resistors
and clamping diodes which allow voltages of up to ±200V to
be applied to either input for an indefinite time without
device failure. These devices will be useful where high
common mode voltages, differential mode voltages, or high
transients may be experienced. Such conditions may be
found when interfacing separate systems with separate
supplies. Unity gain stability is somewhat degraded with
capacitive loads because of the high value of input resistors.

10 = 10pA -10 pin to V+
10 = 100pA -.,. 19, pin to ground. If this is not possible; any
-0.8 to V- + 0.8 can be used.
voltage from V
10 = 1mA-IO pin to V-

Extended Common Mode Input

NOTE: The negative output current available is a function of
the quiescent current setting. For maximum p-p output
voltage swings into low impedance loads, 10 of 1mA should
be selected.

~ange

The ICL7612 incorporates additional processing which
allows the input CMVR to exceed each power supply rail by
0.1 volt for applications where VSUpp ~ ±1.5V. For those
applications where VSUpp S ±1.5V, the input CMVR is
limited in the pOSitive direction, but may exceed the
negative supply rail by 0.1 volt in the negative direction (eg.
for VSUpp = ± 1.0V, the input CMVR would be + 0.6 volts to
-1.1 volts).

Output Stage and ,Load Driving
Considerations
Each amplifiers' quiescent current flows primarily in the
output stage. This is approximately 70% of the 10 settings.
This allows output swings to almost the supply rails for
output loads of 1Mn, 100kn, and 10kn, using the output
stage in a highly iinear class A mode. In this mode,
crossover distortion is avoided and the voltage gain is
maximized. However, the output stage can also be operated
in Class AS for higher output currents. (See graphs under
Typical Operating Characteristics). During the transition
from Class A to Class S operation, the output transfer
characteristic is non-linear and the voltage gain decreases.

OPERATION AT VSUPP

=±1.0 VOLTS

Operation at Vsupp = ± 1.0V is guaranteed at 10 = 10pA
only. This applies to those devices with selectable la, and
devices that are set internally to 10 = 10pA (i.e., ICL7611,
7612, 7613, 7631; 7632, 7642).
OutP!Jt swings to within a few millivolts of the supply rails
are achievabl,e for RL ~ 1Mn. Guaranteed input CMVR is
±0.6V minimum and typically + 0.9V to -O.7V at
VSUpp = ± 1.0V. For applications where greater common
mode range is deSirable, refer to the description of ICL7612
above.

A special feature of the output stage is that it approximates a transconductance amplifier, and its gain is directly
proportional to load impedance. Approximately the same
open loop gains are obtained at each of the 10 settings if
corresponding loads of 10kn, 100kn, and 1Mn are used.

The user is cautioned that, due to extremely high input
impedances, care must be exercised in layout, construction,
4-46

Note: All typical values have been guaranteed by characterization and are not tested.

ICL76XX
board cleanliness, and supply filtering to avoid hum and
noise pickup.

APPLICATIONS
Note that in no case is 10 shown. The value of 10 must be
chosen by the designer with regard to frequency response
and power dissipation.
DUTYCVCLE

_0

VIN-----!+'

.....- - - -

!>--~--

VOUT

Since the output range swings exactly from rail to rail, frequently
and duty cycle are virtually independent of power supply variations.

Figure 6: Precise Triangle/Square Wave
Generator
AF028301

Figure 3: Simple Follower*
1M'

.-".""'--.-VOH

V,.
V,N

TO
SUCCEEDING

INPUT
STAGE

>---+-----f

>---......- - - TO CMOS OR
VOUT

l00k~-_-I

LPTTL LOGIC

COMMON
1M
AF028401

08017601

Figure 7: Averaging AC to DC Converter
for A/D Converters Such as ICL71 06,
7107, 7109, 7116, 7117

·By using the ICL7612 in these applications, the circuits will follow
rail to rail inputs.

Figure 4: Level Detector*

1M

100k.1%

5QOk,1%

lOOk

INPUT
\loUT
1M, 1%

> - -......- - - - V O U T

. - - - - - -.... v+ o--"I'>I'Y-_--I

1M

AF02B501

08017701

Note that AVOL = 25; single Ni-cad battery operation. Input current
(from sensors connected to patient) limited to < 5iJ,A under fault
conditions.

"Low leakage currents allow integration times up to several hours.

Figure 5: Photocurrent Integrator

Figure 8: Medical Instrument Preamp

4-47
Note: All typical values have been guaranteed by characterization and are not tested.

O,2!

r--

;:>

O.1j,lF

O.2~F

1M

I

L--ii-=_.J

I

360Ic

'M

•

OUTPUT

I

L--H":-c.J

AF028601

The low bias currents permit high resistance and low capacitance values )0 be used to achieve low frequency cutoff. fe = 10Hz, AVCL = 4, Passband
ripple - O.ldB
"Note that small capacitors (25-50pF) may be needed for stability in some cases.

Figure 9: Fifth Order Chebyshev Multiple Feedback Low Pass Filter

+8V
16k

TA '" +125'C

l60k

1.5k

VOUT

LCOO8401

NOTES:
1. For devices with external compensation, use 33pF.
2. For deVices with programmable standby current, connect
10 pin to V- (10 = 1mA mode).

AF028701

Q

Note that 10 on each amplifier may be different. AVCL = 10,
= 100, fo -100Hz.

Figure 10: Second Order Biquad Bandpass
FiRer

Figure 11: Burn-In and Life Test Circuit

4-48

Note: All typical values have been guaranteed by characterization and are riot tested,

ICL76XX

>----YOUT

Y'N>----!

I.

l00pF

.". AL .. 10k FOR '0 '" 1rnA

lOOk FOR '0 • l00,.A
1M FOR 10 • lo,.A

·FOR ICL7614115 .
LC0085QI

Figure 13: Unity Gain Frequency
Compensation
Figure 12:

Vos

LCOO83OI

Null Circuit

4-49
Note: All typical values have been guaranteed by characterization and are not tested.

i

D~U16

ICL7650

!:i .Chopper-Stabilized
S! Operational Amplifier
GENERAL DESCRIPTION

FEATURES

The ICL7650 chopper-stabilized amplifier is a highperformance device which offers exceptionally low offset
voltage and input-bias parameters, combined with excellent
bandwidth and speed characteristics. Intersil's unique
CMOS approach to chopper-stabilized arnplifier design
yields a versatile precision component that can replace
more expensive hybrid or monolithic devices.·
The chopper amplifier achieves its low offset by comparing the inverting and non-inverting input voltages in a nulling
amplifier, null8d by alternate clock phases. Two eXternal
capacitors are required to store the correcting potentials on
the two amplifier nulling inputs; these are the only external
components necessary.
The clock oscillator and all the other control circuitry is
entirely self-contained, however the 14-pin version includes
a provision for the use of an external clock, if required for a
particular application. In addition, the ICL7650 is internally
compensated for unity-gain operation.

•
•
•
•
•
•
•
•
•
•

Extremely Low Input Offset Voltage - 2ILV
Low Long-Term and Temperature Drifts of Input
Offset Voltage
Low DC Input Bias Current - 10pA (20pA 7650B)
Extremely High Gain, CMRR and PSRR - Min
120dB
High Slew Rate - 2.5V1ILS
Wide Bandwidth - 2MHz
Unity-Gain Compensated
Very Low Intermodulatlon Effects (Open Loop
Phase Shift < 10·C @ Chopper Frequency)
Clamp Circuit to Avoid Overload Recovery
Problems and Allow Comparator Use
Extremely Low Chopping Spikes at Input and
Output

ORDERING INFORMATION
TEMPERATURE
RANGE

PACKAGE

ICL76S0CPA-1

O·C to +70·C

8-PIN Plastic

ICL7650BCPA-1
ICL7650CPD

O·C to +70·C
O·C to +70·C

ICL7650BCPD

O·C to +70·C

ICL76S0CTV-1

O·C to +70·C

PART

ICL7650BCTV-1

TEMPERATURE
RANGE

PACKAGE

ICL76S0lJD

-2S·C to +8S·C

14-PIN CERDIP

8-PIN Plastic

ICL76S0BIJD
ICL76501TV-1

- 2S·C to + 8S·C
-2S·C to + 8S·C

14-PIN CERDIP

14-PIN Plastic
14-PIN Plastic

ICL7650BITV-1

-2S·C to +8S·C

8-PIN TO-99

8-PIN T0-99

ICL7650MJD

- SS·C to + 12S·C

14-PIN CERDIP
14-PIN CERDIP

PART

8-PIN T0-99

O·C to +70·C

8-PIN TO-99

ICL76S0BMJD

- SS·C to + 12S·C

ICL76S0IJA-1

- 2S·C to + 8S·C

8-PIN CERDIP

ICL76S0MTV-1

-SS·C to + 12S·C

a-PIN TO-99

ICL76S0BIJA-1

-2S·C to + 8S·C

8-PIN CERDIP

ICL76S0BMTV-1

- SS·C to + 12S·C

8-PIN TO-99

CEXT:~

CeXTA

Nc(GUA~: ~

1•

14

:

:~ ~+T eLK OUT

2

+IN ~ 5

10

6

•

NC(GUAAD~ [

INJECT

t3

EXT eLK IN

~ OUTPUT
~ OUTPUT CLAMP

y": [""",_ _.....;:.""J CRETN
14· PIN DIP

CEXT:U:·
..··
7 y+ I CASE

~ ... cu< ..
~A.~K~

-IN 2

---r--l...-'

• OUTPUT

+IN 3

~.

~

~c

5 OUTPUT CLAMP
CR£'N(-')

8 LEAD TO· 99
80006411

c0015721

Figure 1: Functional Diagram

Figure 2: Pin Configuration

4-50
Note: All typical values have been guaranteed by characterization. and are not tested.

302061-003

ICL7650
ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage (V+ to V-) ................... 18 Volts
Input Voltage ................. (V + + 0.3) to (V- - 0.3) Volts
Voltage on oscillator control pins ................. V+ to Vexcept EXT CLOCK IN: ... (V + + 0.3) to (V + - 6.0) Volts
Duration of Output short circuit ..................... Indefinite
Current into any pin ........................................ 10mA
-while operating (Note 4) .............................. 100j.tA

Cont. Total Power Dissipn (TA = 25·C)
CERDIP Package ................................ 500mW
Plastic Package .................................. 375mW
TO-99 ............................................... 250mW
Storage Temp. Range ....................... -65·C to 150·C
Operating Temp. Range ........................... See Note 1
Lead Temperature (Soldering, 10sec) ................. 300·C

Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and lunctional
operation 01 the device at these or any other cond~ions above those indicated in the operational sections 01 the specHications is not implied. Exposure to
absolute maximum rating conditions lor extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
Test Conditions: V+

= +5V,

= -5V,

V-

TA

= +25·C,

(unless otherwise specified)
LIMITS 7650

SYMBOL

PARAMETER

UNIT
MIN

Input Offset Voltage

Vos

Average Temp. Coefficient

AVos

LIMITS 7650B

TEST CONDITIONS
TYP

MAX MIN
±5

TYP

MAX

±2
±5

±10.0

TA= + 25'C
-25'C < TA < +85'C
-55'Cut 'N~ise. VoltaQ'!.'

in.'

,Input NoiSl! Current
u~·,G.illri-' ~ildwidth

GBW.

.,

tr
V+ to'VISUpp

Ich

CMVR= -5V to +1.5

-5.0

-5.2 to
+2.0

110

120

110

120

120

130

t20

130

Rs-l00n
1=0 to 10Hz

I -10Hz

,.

±20
pA

pA

5.0

AVOL

SR,

pV
±75

±50

1.5

-5.0

-5.2 to
+2.0

n

I

VIV
V

1.5

V

I

,I

dB
dB

2

2

0.Q1

0.01

2.0

2.0

pA/v'Hz
MHz

pVp.p

2.5

2.5

V/IJS

'RisJi> Ti"1e'

0.2

0.2

.Ov& +1

o
-1 ~-+--+---+

-2 1--+--+- ----I----i---I

• •

10

14

II

VOLTS
OP020001

l

211

5

0

~

--I----i--"'1

TOTAL SUPPLY VOLTAGE -

OUTPUT WITH· ZERO. INPUT;
GAIN =1000;BAI:.ANCED SOURCE
IMPEDANCE = 10KO

INPUT OFFSET VOLTAGE
VI. CHOPPING FREQUENCY

INPUT OFFSET VOLTAGE CHANGE
VI. SUPPLY VOLTAGE
~

150

"C

0P019701

i

....

I
I

01
EACHSUPPLYVOLTAGE(+ AND-I

I

,

I

:t-+---+-:7fC-t-+-+-+-t

I>

\

,

I.

211

I

o

10

10k

tk

CHOPPING FlIIOuENcY CCLDCII.()U1) HI
0P02011 I

4-52
Note: All typical values have been guaranteed by characterlzalion and are not tested.

23

..
TlM.E~

.7

•

•

m.
HT000021

ICL7850
TYPICAL PERFORMANCE CHARACTERISTICS (CO NT.)
OPEN LOOP GAIN AND PHASE SHIFT
VI. FREQUENCY

,.,,.

OPEN LOOP GAIN AND PHASE SHIFT
VI. FREQUENCY

,.

I

1.

"

10,

"-

"§. -tOO

, ,'.

I'

I.
•

i"
RL =, 10k.n.

cDj • oj''''

Ut o.t

10

100

10

1

.t:

...

,

1.

I

"- , "°1

I•
..

,....

:\..

1.

"

V

,
! • -I •
• Cr .,'.O~f
100

./

r---,

f-~L = 10k.n.

o.t

Ut

1 k 10k tOOk

tOO

10

10

'I"-

0

1.

10'1
·i
no I

~

;"

tk

,. if

I"

10k 100k

'REQUENCY HI

,IIEGUiENCY ...

0PIJ20311

VOLTAGE FOLLOWER LARGE SIGNAL PULSE
RESPONSE"

i!
IIIC

'

!:i 0

~
!;

I

......

+2

~+1

VOLTAGE FOLLOWER LARGE SIGNAL PULSE
RESPONSE·

... 'I/;.
J

CLOCK OUT
LOW,

-1

I!

f/

\.

"- V

I
CLOCK OUT
HIGH

CLOCK OUT
H'GH

..K '\

\\"'-

f

~-2
o

CLOCK OUT
, LOW

o.s.1
1.1
T'..E ....

2

o

2.1

1

~

0.5

1.5

I .
2

T'''E·~S
OP020401

OP020501

• THE TWO DIFFERENT RESPONSES
CORRESPOND TO THE TWO PHASES OF THE
CLOCK.
N-CHANNEL CLAMP CURRENT VI. OUTI'UT
,
VOLTAGE

P-CHANNEL CLAMP CURRENT
VOLTAGE

,.,..

VI. OUTPUT

10e,.A

tll,oA

111,oA

,,.,.

.

110A

ii

1G011A

18

1011A
1M

1011A

~!

7

100pA

100pA

1apA

tapA

tpA
+0.1

+0"

+0.4

o

+0.2

f

1M

1pA

f

-0.1

-0.,

-0.4

-0.2

o

OUTPUT VOLTAGE ,\V +

OUTPUT VOLTAGE AV0P020601

Note: All typical values have been guaranteed by characterization and are not tested.

OP0207OI

i ICL7650

a

Output 'Clamp

RZ

The OUTPUT CLAMP pin allows reduction of the overload recOvery time inherent with chopper-stabilized amplifiers. When tied to the inverting input pin, or summing
jUnction, a current path between this point and the OUTPUT
pin occurs just before the device' output saturates. Thus
uncontrolled .input differential inputs are avoided, together
with the consequent charge build-upon the correctionstorage capacitors. The output swing is slightly reduced.

0 ...........- - · .OUTPUT

Clock
The ICl7650 has an internal oscillator giving a chopping
freqUency of 200Hz, available at the CLOCK OUT pin on the
14-pih devices. Provision has also been made for the use of
an external clock in these parts. The INT100 pin has an
internal pull-up and may be left open for normal operation,
but to utilize an external clock this pin must be tied to V- to
disable the internal clock: The external clock signal may
then be applied to the EXT. CLOCK IN pin. At low
frequencies, the duty cycle of the external clock is not
critical, since an internal divide-by-two provides the desired
50% switching duty cycle. However; since the capacitors
are charged only when EXT ClK IN is HIGH, a 50-80%
positive duty cycle is favored for frequencies above 500Hz
to ensure that any transients have time to settle before the
capacitor~ are turned OFF. The external clock should swing
between V + an~ GROUND for pOwer supplies up to ±6V,
and between V and V+ -6V for highl;lr supply voltages.
Note that a signal of about 400Hz will be present at the EXT
ClK IN pin with INT
high or open. This is the internal
clock signal before the divider.

Ti::025101

Figure 3:

I~L7650/B

Test Circuit

DETAILED DESCRIPTION
Amplifier
The functional diagram shows the major elements of the
ICl7650. There are two amplifiers, the main amplifier, and
the nulling amplifier. Both have otfseMull capability. The
main amplifier is connected continu,ously from the input to
the output, while the nulling amplifier, under the control of
the chopping oscillator and clock circuit, alternately nulls
itself and the main amplifier. The nulling connections, which
are MOSFET gates, are inherently high impedance, and two
external capacitors provide the required storage of the
nulling potentials and the necessary nulling-loop time constants. The nulling arrangement operates over the full
common-mode and power-supply ranges, and is also independent of the output level, thus giving exceptionally high
CMRR, PSRR, and AVOL. ,
.
Careful balancing of the input switches, and the inherent
balance of the input circuit, minimizes chopper frequency
charge injection: at the input terminals, and also the
feedforward-typeinjection into the compensation capaCitor,
which is the main cause of output spikes in this type of
circuit.

1m

In those applications where' a strobe signal is available,
an ~Iternate approach to avoid capacitor misbalancing
during overload can be used; Ita Strobe Signal is connected
to' EXT ClK IN so that it is low during the time that the
overload signal is applied to the amplifier, neither capacitor
will be charged. Since the. leakage at the capacitor pins is
quite I.ow at room temperature, the typical amplifier will drift
less than 10pV/sec, and relatively long measurements can
be made with little change in offset.

Intermodulation
Previous chopper-stabilized amplifiers have suffered from
intermodulation effects between the chopperfrequency and
input signals. These arise because the finite AC gain of the
amplifier necessitates a lImall AC signal at the input. This is
seen by the zeroing circuit as an error signal; which is
chopped and fed back, thus injecting .sum and difference
frequencies and causing disturbances to the gain and
phase vs. frequency characteristics near the' chopping
frequency. These effe<;ts are sUbstantially reduced in the
ICl7650 by feeding the nulling circuit with a dynamic
curre~t, corresponding to the co'1lpensation capacitor current, In such a way as'toJ:ancel that portion of the il1Put
signal due to finite AG gain. Since that is the major error
contribution to the ICl7650, the intermodulation and gainl
phase disturbances are held to very low values, and can
generally be ignored.

'BRIEF APPLICATION NOTES
Component Selection
The two required capacitors, CEx-rA and CEXTB, have
optimum values depending on the clock or chopping
frequency. For the preset internal clock, the correct value is
0.1pF, and to maintain the same relationship between the
chopping frequency and the nulling time constant this value
should be scaled approximately in proportion if an external
clock is used. A high-quality film-type capacitor such as
mylar is preferred, although a ceramic or other lower-grade
capacitor may prove suitable in many applications. For
quickest settling on initial turn-on, low dielectric absorbtion
capacitors (such as polypropylene) should .be used. With
ceramic capacitors, several seconds may be required to
settle to 1pV.

Capacitor Connection

Protec~ion
All device pins are static-protected by the use of input
diodes. However, strong static fields and discharges should
be avoided, as they can cause degraded diode. junction
characteristics, which may result in increased input-leakage
currents.

Static

The nullistorage capaCitors should be connected to the
CEXTA and CEXTB pins, with a common connection to the
CRETN pin. This connection should be made directly by
either a separate wire or PC trace to avoid injecting load
current IR drops into the capacitive circuitry. The outside
foil, where available, should be connected to CRETN.
4-54

Note: All typical values ' eve been guaranteed by characterization and are not tested.

ICL7650'

_....-

.-

N--· -W~

-

NOTE:...!.!J!.1

INVERTING AMPLIFIER

FOLLOWER

+...

-- '
""""'. . .,,0
IXnMAL

C
.~'
:="'''7"
.....

8HOULD •• LOW
IMPEDANCE FOIl

OP1111U11 GUARDING

RETN

~,

.0

O~

?"

8O'n'OII VIEW
80AIID LAYOUT .011......".
GUAIQIIIrIO WITH _ _

NON-INVERTING AMPLIFIER

..........

SSOO6801

Figure 4: Connection of 'Input Guards

Latchup Avoidance

Guarding

Junction-isolated CMOS circuits inherently include a
parasitic 4-layer (p-n-p-n) structure which has characteristics similar to an SCR. Under certain circumstances this
junction may be triggered into a low-impedance state,
resulting in excessive supply current. To avoid this condi'
tion, no voltage greater than 0.3V beyond the supply rails
should be applied to any pin. In general, the amplifier
supplies must be established either at the same time or
before any input signals are applied. If this is not possible,
the drive circuits must limit input current flow to under 1rnA
to avoid latchup, even under fault conditions.

Extra care must be taken in the assembly of printed
circuit boards to take full advantage of the low input
currents of the ICL7650. Boards must be thoroughly
cleaned with TCE or alcohol and blown dry with compressed air. After cleaning, the boards should be coated
with epoxy or silicone rubber to prevent contamination.
Even with properly cleaned and coated boards, leakage
currents may cause trouble, particularly since the input pins
are adjacent to pins that are at supply potentials. This
leakage can be significantly reduced by using guarding to
lower the voltage difference betWeen the inputs and adjacent metal runs. Input guarding of the 8-lead TO-99
package is accomplished by using a 10-lead pin circle, with
the leads of the device formed so that the holes adjacent to
the inputs are empty when it is inserted in the board. The
guard, which is a conductive ring surrounding the inputs, is
connected to a low impedance point that is at approximateIy the same voltage as the inputs. Leakage currents from
high-voltage, pins are then absorbed by the guard.
The pin configuration of tlie 14-pin dual in-line package is
designed to facilitate guarding, since the pins adjacent to
the inputs are not used (this is different from the standard
741 and 101A pin configuration, but corresponds to that of
the LM108).

Output Stage/Load Driving
The output circuit is a high-impedance type (approximately 18kn), and therefore with loads less than this value, the
chopper amplifier behaves in some ways like a transconductance amplifier whose open-loop gain is proportional to
load resistance. For example, the open-loop gain will be
17dB lower with a 1kn load than with a 10kn load. If the
amplifier is used strictly for DC, this lower gain is of little
consequence, since the DC gain is typically ,greater than
120dB even with a 1kn load. However" for wideband
applications, the best frequency response will be achieved
with a load resistor of 10kn or higher. This will result ,in a
smooth 6dB/octave response from 0.1 Hz to 2MHz, with
phase shifts of less than 10· in the transition region where
the main amplifier takes over from the nU,1I amplifier.

Pin Compatibility
The basic pinout of the 8-pin device corresponds, where
possible, to that of the industry-standard 8-pin devices, the
LM741 , LM101, etc. The null-storing external capacitors are
connected to pins 1 and 8, usually used for offset null or
compensation capaCitors, or simply not connected. The
output-clamp pin (5) is similarly used. In the case of the OP05 and OP-07 devices, the replacement of the offset-null
pot, connected between pins 1 and 8 and V +, by two
capacitors from those pins to V-, will provide easy compatibility. As for the LM108, replacement of the compensation
capacitor between pins 1 and 8 by the two capaCitors to Vis all that is necessary. The same operation, with the
removal of any connection to pin 5, will suffice for the
LM101, jlA748, and similar parts.
The 14-pin device pinout corresponds most closely to
that of the LM108 device, owing to the provision of ,"NC"
pins for guarding between the input and all other pins. Since
this device does not use any of the extra pins, and has no
provision for Offset-nulling, but requires a compensation
capacitor, some changes will be required in layout to
convert it to the ICL7650.

Thermo-Electric Effects
The ultimate limitations to ultra-high precision DC amplifiers are the thermo-electric or Peltier effects arising in
thermocouple junctions of dissimilar metals, alloys, silicon,
etc. Unless all junctions are at the same temperature,
thermoelectric voltages typically around 0.1 jlV
but up to
tens of jlVrC for some materials, will be generated. In
order to realize the extremely low offset voltages that the
chopper amplifier can provide, it is essential to take special
precautions to avoid temperature gradients. All components
should be enclosed to eliminate air movement, especially
that caused by power-dissipating elements in the system.
Low thermoelectric-coefficient connections should be used
where possible and power supply voltages and power
dissipation should be kept to a minimum. High-impedance
loads are preferable, and good separation from surrounding
heat-dissipating elements is advisable.

rc,

4-05
Note: All typical values have been guaranteed by characterization and are not tested;'

4

! .ICL7080
d TYPICAL APPUCATI()NS

+7.JV

Clearly the appliCations of the ICL7650 will mirror those
of other op. amps. A.nywhere that the performance of a
circuit can be significantly improved by a reduction of inputoffset voltage and. ~las current, the ICL765Q is the logical
choice. Basic non·'nverting and inverting amplifier circuits
are shown in FiglJr~iI 5 and 6. Both cire;:uits. can use the
output clamping circ:uit to.enhancethe overload recovery
performance. The only limitations on the replacement of
other op amps by the ICL7650 are the supply voltage (±8V
max.) and the output drive capability (10kn load for full
swing). Even these limitations can be overcome using a
simple booster circuit, as shown in Figure 7, to enable the
full output capabilities of the LM741 (or any other standard
device) to be combined .with the input capabilities of the
ICL7650. The pair form a composite device, so loop gain
stability, when the feedback network is added, should be
watched carefully.

".",,,,,,..

_

.

10k

L-~----t
cJl_--_ .....

__ ounvr

LCOO8911

,

FULL "'-IFFECT
,

OUT

..,.,
~

.

>

-

Figure 8: I,.ow Offset Comparator

...

LC008601

Figure 5: Non Inverting Amplifier
With (Optional Clamp)
NOTE: R,I!R2 INQICATES THE PARALLEL COMBINATION
OF R, AND R2

Normal logarithmic amplifiers are limited in dynamic
range in the voltage-input mode by their input-offset voltage. The built-in temperature compensation and convenience features. of the ICL804B can be extended to a
voltage-input dynamic range of close to 6 decades by using
the ICL7650 to offset-null the ICL804B, as shown in Figure
8. The same concept can also be used with such devices as
the HA2500 or HA2600 families of op amps to add very low
offset voltage capability to their very high slew rates and
b!lndwidths. Note that these circuits. will also have their DC
gains, CMRR, and PSRR enhanced.

LC008701

Figure 6: .Inverting Amplifier
With (OptionallClamp
NOTE: R,I!R2 lIilDICATES THE PARALLEL COMBINATION
OFR, .um R2
.

Figure 8 shows the use ·of the clamp circuit to advantage
in a zero-offset comparator. The usual problems in using a
chopper stabilized amplifier in. this application are aVOided,
since the clamp circuit forC8$ the inverting input to follow
the input signal. The threshold input must tolerate the
output clamp current oto VIN/R without disturbing other
portions of the. system.

LCOOOOOl

Figure 9: ICL8048 Offset Nulled by ICL7650

FOR FURTHER APPLICATIONS ASSISTANCE, SEE
A053 AND R017

Note: All typical values heve been guaranteed by characterization and are not testad.

ICL7652
Chopper-Stabilized low-Noise
Operational Amplifier
GENERAL DESCRIPTION

FEATURES

.The ICL7652 chopper-stabilized amplifier offers exceptionally low input offset voltage and is extremely stable with
respect to time and temperature. It is similar to INTERSIL's
ICL7650 but offers improved noise performance and a
wider common-mode input voltage range. The bandwidth
and slew rate are reduced slightly.
INTERSIL's unique CMOS chopper-stabilized amplifier
circuitry is user-transparent, virtually eliminating the traditional chopper amplifier problems of intermodulation effects, chopping spikes. and overrange lock-up.
The chopper amplifier achieves its low offset by comparing the inverting and non-inverting input voltages in a nulling
amplifier, nulled by alternate clock phases. Two external
capacitors are required to store the correcting potentials on
the two amplifier nulling inputs; these are the only external
components necessary.
The clock oscillator and all the other control Circuitry is
entirely self-contained, however the 14-pin version includes
a provision for the use of an external clock, if required for a
particular application. In addition, the ICL7652 is internally
compensated for unity-gain operation.

•
•
•
•
•
•
•
•
•

Extremely Low Input Offset Voltage - 10llY Over
Temperature Range
Ultra Low Long-Term and Temperature Drifts of
Input Offset Yoltage (150nVlMonth, 100nVrC)
Low DC Input Bias Current - 15pA
Extremely High Gain, CMRR and PSRR - Min
110dB
Low Input NoiSe Voltage- O.2IlVp-p (DC - 1Hz)
Internally Compensated for Unity-Gain Operation
Yery Low Intermodulatlon Effects (Open-Loop
Phase Shift < 2·@ Chopper Frequency)
Clamp Circuit to Avoid OVerload Recovery
Problems and Allow Comparator Use
Extremely Low Chopping Spikes at Input and
Output

ORDERING INFORMATION
PART
NUMBER
ICL7652CPD
ICL76521JD
ICL7652CTV
ICL76521TV

TEMP. RANGE

PACKAGE

O'C to +70'C
-25·C to +85·C
O·C to +70·C
-25'C to +85·C

14-pin plastic
14-pin CERDIP
8-pin TO-99
8-pin TO-99

_a-.
-

I

_

- IN

o-I----++--o OUTPUT

14

IITJIIT

z 1Cl_ 13

__

IXYcura
lIT CUI our

II
II

V'

"

I

GUrM

IIUIPUr CLAW

•

V-'"I:..
7 _ _-..:il!-,Como

14 LEAD
(OuOI.o dwg PD, JD)

CLAMP

-0. V·_..

T
~EXTCl.KIN

TOP VIEW

~A'Cl.KOm

---r--L-l

+.

..r--l--r-a

c.nn l

v-

~c

TQ.H

BD012801

(Oulilno dwg TV)

Figure 1: Functional Diagram

CD031811

Figure 2: Pin Configuration


..3100

i
-

!t

!;

...

CEXT'"'G.1,.F-

!

y

10

e +5

~

Q
W

II:

CEXT=1,.F

I:: BROADBAND NOISE

o
25

1..., .. 1000

50

75

100

¥
125

0

~ -5

I&.

w

II:

>..

150

2345878

TIME(ma)

TEMPERATURE ("C)

TIME(ma)
01'036601

0P036501

4-59
Note: All typical values have been guaranteed by characterization and are not tested.

2345878
0P036701

:1 ICL7652

I»

g~

TYPICAL PERFORMANCE CHARACTERISTICS (CONT.)
Voltage Follower Large Signal
Pulse Response·
3
~2

c(ock

III

:I!:l

g

OUT
LOW

~

If

3

t"-

~

III

"g~

CLOCK
OUT
HIGH

0

O~ -2 I
IF

S
AS
0

-1

2

4 6 8 10 12 14
TIME (,.a)

140

2 r- -~LohK
OUT

,--

0

:\

-1

-2
- 2 0

2

~

z 100

~

CLOCK
e-OUT

~~IG~

-

~

I--

~

'I"
4

~

ij120
l!.

f- \LOW

-3

-3
-2 0

Open·Loop Gain and Phase Shift vs
Frequency

Voltage Follower Large Signal
Pulse Response·

80

I
.

30

IpHkE

'-

I r\.

80

40

RL=1Ok

20

I

o

6

8 10 12 14
TIME(,..)

0.1

1

........

~

50

I

70 ~

\

~\

90
110

:!I

!

~.

130

ill

~

150

j)

10 100 1k 10k 1001< 1M
FREQUENCY (Hz)

OP037601

0P037501

I 1_

~ MARGIN-8O"

0P037701

·The two different responses correspond to the two phases of the clock.

N-Channel Clamp Current vs OutPl't
Voltage

:;-

Ii 100,.A
a:

1o,.A

illa:

!

1""

:)

10nA

iii

1nA
100pA

u

a:

iC

~
Z

~
iii
z

:z:

:t
0.8
0.6
11.4
0.2
OUTPUT VOLTAGE jaV-)

~

3

"~

2

2
g

0

6
III

100nA

1UnA

1nA

~ 100pA

10pA
1pA

..3

III

U
A-

=s

Input Offset Voltage Change vs
Supply Voltage

P·Channel Clamp Current vs Output
Voltage

10pA

1pA
-1.0 -0.8 -0.6 -0.4 -Q.2
OUTPUT VOLTAGE (4V+)

-2

5

-3

o

o

0PQ37901

0P037801

Iii
III
II:
~
-

-

I:') ."..,.

""

-1

4

-

~
~

6
8 10 12 14 111
TOTAL SUPPLY VOLTAGE (V)
0P038001

control of the chopping frequency oscillator and clock
Circuit, alternately nulls itself and the main amplifier. The
nulling connections, which are MOSFET gates, are inherently'high-impedance, and two external capacitors provide
the required storage of the nulling potentials and the
necessary nulling-loop time constants. The nulling arrange, rnent operates over the full common-mode and power
supply ranges,. and is also independent of the output level,
thus giving exceptionally high CMRR, PSRR, and AVOL.

Rz
1MO

<';"-

O-~.OUTPtlT

Careful balancing of the input switches, together with the
,inherent balance of the input circuit, minimizes chopper
frequency charge injection at the input terminals. Feedforward-type injection into the compensation capacitor is also
minimized, which is the main cause of output spikes in this
type of circuit.

TC028401

Figure 3: Test Circuit

Intermodulation
Previous chopper-stabilized amplifiers have suffered from
intermodulation effects between the chopper frequency and
input signals. These arise because the finite AC gain of the
amplifier necessitates a small AC Signal at the input. This is
seen by the zeroing circuit as an error signal, which is
chopped and fed back, thus injecting sum and difference
frequencies and causing disturbances to the gain and
phase vs frequency characteristics near the chopping

DETAILED DESCRIPTION
The Functional Diagram (Figure 1) shows the major
elements of the ICL7652. There are two amplifiers, the main
amplifier, and the nulling amplifier. Both have offset-null
capability. The main amplifier is connected continuously
from the input to the output. The nulling amplifier, under the
4-60

Note: All typical values have been guaranteed by characterization and are not tested.

ICL7652
frequency. These effects are substantially reduced in the
ICl7652 by feeding the nulling circuit with a dynamic
current, corresponding to the compensation capacitor current, in such a way as to cancel that portion of the input
signal due to finite AC gain. Since that is the major error
contribution to t!"le ICl7652, the intermodulation and gainl
phase disturbances are held to very low values, and can
generally be ignored.

lower-grade capacitor may prove suitable in many applications. For quickest settling on initial turn-on, low dielectric
absorption capacitors (such as polypropylene) should be
used. With ceramic capacitors, several seconds may be
required to settle to 11lV.
.

Static Protection
All device pins are static-protected by the use of input
diodes. However, strong static fields and discharges should
be avoided, as they can cause degraded diode junction
characteristics which may result in increased input-leakage
currents.

Capacitor Connection
The null-storage capacitors should be connected to the
CEXTA and CEXTB pins, with a common connection to the
CRETN pin. This connection should be made directly by
either a separate wire or PC trace to avoid injecting load
current IR drops into the capacitive circuitry. The outside
foil, where available, should be connected to CRETN.

Latchup Avoidance
Junction-isolated CMOS circuits inherently include a
parasitic 4-layer (p-n-p-n) structure which has Characteristics similar to an SCA. Under certain circumstances this
junction may be trigerred into a low-impedance state,
resulting in excessive supply current. To avoid this condition
no voltage greater than 0.3V beyond the supply rails should
be applied to any pin. In general, the amplifier sllpplies must
be established either at the same time or before any input
signals are applied. If this is not possible, the drive circuits
must limit input current flow to under 1mA to avoid latchup,
even under fault conditions.

Output Clamp
The OUTPUT CLAMP pin allows reduction of the overload recovery time inherent with chopper-stabilized amplifiers. When tied to the inverting input pin, or summing
junction, a current path between this pOint and the OUTPUT
pin occurs just before the device output saturates. Thus
uncontrolled differential input voltages are avoided, together with the consequent charge build-up on the correctionstorage capacitors. The output swing is slightly reduced.

Output Stage/Load Driving

Clock

The output circuit is a high-impedance type (approximately 18kn), and therefore, with loads less than this the
chopper amplifier behaves in some ways like a transconductance amplifier whose open-loop gain is proportional to
load resistance. For example, the open-loop gain will be
17dB lower with a 1kn load than with a 10kn load. If the
amplifier is used strictly for DC, this lower gain is of little
consequence, since the DC gain is typically greater than
120dB even with· a 1kn load. However, for wideband
applications, the best frequency response will be achieved
with a load resistor of 10kn or higher. This will result in a
smooth 6dB/octave response from 0.1Hz to 2MHz, with
phase shifts of less than 2° in the transition region where
the main amplifier ,takes over from the null amplifier.

The ICl7652 has an internal oSCillator, giving a chopping
frequency of 400Hz, available at the CLOCK OUT pin on the
14-pin devices. Provision has also been made for the use of
an external clock in these parts. The INT100 pin has an
internal pull-up and may be left open for normal operation,
but to utilize an external clock this pin miJst be tied to V- to
disable the internal clock. The external ·clock signal may
then be applied to the EXT CLOCK IN pin. An internal
divide-by-two provides the desired 50% input switching duty
cycle. Since the capacitors are charged only when EXT
CLOCK IN is high, a 50%-80% positive duty cycle is
recommended, especially for higher frequencies. The external clock can swing between V+ and V-. The logic
threshold will be at about 2.5V below V + . Note also that a
signal of about 800Hz, with a 70% duty cycle, will be
present at the EXT CLOCK IN pin with INT /EXT high or
open .. This is the internal clock signal before being fed to
the divider.
In those applications where a strobe signal is available,
an alternate approach to a.void capacitor misbalancing
during overload can be used. If a strobe signal is connected
to EXT ClK IN so that it is low during the time that the
overload signal is applied to the amplifier, heither capacitor
will be charged. Since the leakage at the capacitor pins is
quite low at room temperature, the typical amplifier will drift
less than 1OIlV/sec, and relatively long measurements can
be made with little change -in offset.

Thermo-Electric Effects

BRIEF APPLICATION NOTES
Component Selection

The ultimate limitations to ultra-high precision DC amplifiers are the thermo-electric or Peltier effects arising in
thermo-couple junctions of dissimilar metals, alloys, silicon,
etc. Unless all junctions are at the same temperature,
but up
thermo-electric voltages typically around 0.11lV
for some materials, will be generated. In
to tens of IlV
order to realize the extremely low offset voltages that the
chopper amplifier can provide, it is essential to take special
precautions to avoid temperature gradients. All components
should be enclosed to eliminate air movement, especially
that caused by power-dissipating elements in the system.
low thermoeleCtric-coefficient connections should be used
where possible and power supply voltages and power
dissipation should be kept to a minimum. High-impedance
loads are preferable, and good separation from surrounding
heat-dissipating elements is advisable.

The required capacitors, CEXTA and CEXTB, are normally
in the range of 0.11lF to 1.0IlF. A 1.01lF capacitor should be
used in broad bandwidth circuits if minimum clock ripple
noise is desired. For limited bandwidth applications where
clock ripple is filtered out, using a 0.11lF capacitor results in
slightly lower offset voltage. A high-quality film-type capacitor such as mylar is preferred, although a ceramic or other

Extra care must be taken in the assembly of printed
circuit boards to take full advantage of the low input
currents of the ICl7652. Boards must be thoroughly
cleaned with TCE or alcohol and blown dry with compressed air. After cleaning, the boards should be coated
with epoxy or silicone rubber to prevent contamination.

rc

rc,

Guarding

4-61
Note: All typical values have been guaranteed by characterization and are not tested.

i...

.....

2

ICL.7852
~.

Even with properly cleaned and coated boards, leakage
currents may cause trouble, particularly since the input pins
are adjacent to pins that are at· supply potentials. This
leakage Can be significantly reduced by using guarding to
lower the voltage difference between the inputs and' adjacent metal runs. Input guarding of the 8 lead TO-99
package is acc9mplished by using a 10 lead pin circle, with
, the leads of the device f.ormed so that the holes adjacent to
the inputs are empty when it is inserted in the board. The.
guard, which is a conductive ring surrounding the inputs, is
, connected to a low-impedance point that is at approximately the same voltage as the inputs. Leakage currents from
high-voltage pins are then absorbed by the guard.

PIN COMPATIBILITY
, The, basic pinout of the 8:pin de,vice corresponds, where
possible, to that of theindusti"y-standard8-pin devices, the
LM741, LM1 01, etc. The null-s~oring external capacitors are
connected to pin,S 1 and 8, which are usu,ally used fO,r offsetnull or compensation capacitors. The output~clamp pin (5) is
Similarly used. In the case of the OP-05 and OP-07 devices,
the replacement of the offset-null pot; connected between
pins 1 and 8 and Y + , by two capacitors from those pins 1'0
Y-, will prClvide easy compatibility. As for the LM108,
replacement of the compensation capaCitor between pins 1
and 8 by the two capacitors to Y- is all thatis necessary.
The same operation, with the removal of any connection to
pin 5, will suffice for the LM101, jJA748, lind similar parts.
The 14-pin device pinout corresponds most closely to
that of the LM108 device, owing to the provision of "NC"
pins for guarding between the input and all other pins. Since
this device does not use any of the extra pins, and has no
provision for offset-nulling, but requires a compensation
capacitor, some changes will be required in layout to
convert to the ICQ652.

. The pin configuration of the 14"pin dual-in-line package is
designed to facilitate' guarding, since the pins adjacent to
the. inputs. are not used (this is different from the standard
741 and 101A pin configuration; but corresponds to that of
the LM108).

INPUT~~~-.------~~----~

OUTPUT
OUTPUT

INPUT ~++--t

TC----*-1
OUTPUT

yo.

lC017701

Figure 6: Inverting Amplifier
with (Optional) Clamp
Clearly the applications of the ICL7652 will mirror those
of other op-amps. Thus, anywhere that the performance of
a circuit can be significantly improved by a reduction of
input-offset voltage and bias current, the ICL7652 is the
logical choice. Basic non-inverting and inverting amplifier
circuits are shown in Figures 5 and 6. Both circuits can use
the output clamping circuit to enhance the overload recovery performance. The only limitations on the replacement of
other op-amps by the ICL7652 are the supply voltage (±8V
max) and the output drive capability (10kn load for full
swing). Even these limitations can be overcome using a
simple booster circuit, as shown in Figure 7, to enable the
full output capabilities of the LM741 (or any other standard
device) to be combined with the input capabilities of the
ICL7652. The pair form a composite device, so loop gain
stability, when the feedback network is added, should be
watched carefully.

AF031201

Figure 8: Low Offset Comparator
It is possible to use the ICL7652 to offset-null such high
slew rate and bandwidth amplifiers as the HA2500 and
HA2600 series, as shown in Figure 9. The same basic idea
can be used with low-noise bipolar devices, such as the OP05 and also with the ICL8048 logarithmic amplifier, to
achieve a voltage-input dynamiC range of close to 6
decades. Note that these circuits will also have their DC
gains, CMRR and PSRR enhanced. More details on these
and other ideas are explained in application note A053.
Mixing the ICL7652 with circuits operating at ±15V
supplies requires the provision of a lower voltage. Although
this can be done fairly easily, a highly efficient. voltage
divider can be built using the ICL7660 voltage converter
circuit "backwards". A suitable connection is shown in
Figure 10.

Note: All typical values have been guaranteed by characterization and are not tested.

:"

a

ICL7652
TYPICAL APPLICATIONS

OUT

AFOS1311

HA2500l10/20
HA2600120
OR SIMILAR DEVICE

Figure 9: HA2500 or HA2600 Offset-Nulled
by ICL7652

2

'r---<+15V

ICL7IIO

1--.--+ +7.5V
100F

I--+--+ov

AF0308CK

Figure 10: Splitting + 15V with ICL7660
at > 95% efficiency. Same for -15V
FOr further applications a..lstance, _

AOS3 and R017

4-64
Note: All typical values have been guaranteed by characterization and are not tested.

ICLa007
JFET Input Operational Amplifier
GENERAL DESCRIPTION

FEATURES

The Intersi! ICLB007 is a low input current JFET input
operational amplifier. The ICLB007 A is selected for 4 pA
max input current.
The devices are designed for use in very high input
impedance applications. Because of their high slew rate,
high common mode voltage range and absence of "latchup", they are ideal for use as a voltage follower.
The Intersil B007 and B007 A are short circuit protected.
They require no external components for frequency compensation because the internal 6 dB/roil-off insures stability
in closed loop applications. A unique bootstrap circuit
insures unusually good common mode rejection for a JFET
input op-amp and prevents large input currents as seen in
some amplifiers at high common mode voltage.

•
•
•
•
•
•

Ultra Low Input Current
High Slew Rate - 6VI /J5
Wide Input Common Mode Voltage
1MHz Band Width
Excellent Stability
Ideal for Unity Gain Applications

ORDERING INFORMATION
PART
NUMBER

TEMPERATURE
RANGE

to +70·C

ICL8007CTV
ICL8007ACTV

O·C

ICL8007MTV
ICL8007AMTV

-55·C

ICL8007/D

to + 125·C

-

PACKAGE
8 LEAD
TO-99
METAL CAN
DICE"·

··Parameter MinIMax Limits quaranteed at 25·C only for DICE orders.

~.----------.--------~----~~o.·

•••
...,
L.--+-oOUTPUT

Q ••

r'O"V'fW,

CO01690t

TC02590t

ICL8007 pin 4 connected to case (TV package)
ICL8007A pin 8 connected to case (TV package)

Figure 1: Functional Diagram

Figure 2: Pin Configuration

4-65

Note: All typical values have been guaranteed by characterization and are not tested.

g ICLeoo7

a

A'BSOLUTE MAXIM'UM RATINGS
Supply Voltage ................................................ ±18V
Power Dissipation (Note 1) ............................. 500mW
Differential Input Voltage ...................................±30V
Input Voltage (Note 2) ...............................'..... :.±15V
Storage Temp.erature Range;·........... ~65·C to + 150·C

Operating Temperature Range
8007M, 8007AM .................... - 55·C to -+: 125·C
8007C, 8007AC ........................... O·C to + 70·C
Lead Temperature (Soldering, 10sec) ................. 300·C
Output Short-Circuit Duration (Note 3) ............ Indefinite

NOTES:
1. Rating applies lor case temperatures to 12S0C; derate linearly at 6.S mW/oC' lor ambient temperatures above + 7SOC.
2~ For supply voltages less than ± 15V, the absolute maximum input voltage is equal to the supply voltage.
3. Short circu~ may be to ground or e~her supply. Rating applies to + 12SoC case temperature or + 7SOC ambient temperature.
4. For Design only, not 100% tested.

ELECTRICAL CHARACTERISTICS
CHARACTERISTICS

(Vs

= ±15V

unless otherwise specified)
aOO7M

TEST CONDITIONS
MIN

The following specifications apply for T A
Input Offset Voltage

8007C

TYP

MAX

10

20

MIN

a007AM & aOO7AC

TYP

MAX

20

SO

MIN

MAX

15

30

mV

4.0

pA

=25·C:

'Rs ~ 100kn

Input Offset Current

0.5

Input Bias Current (either input)

2.0

Input Resistance

106

106

106

Input Capacitance

2.0

2.0

2.0

Large Signal Voltage Gain

UNIT

TYP

RL ~ 2kn, VOUT - ±10V

0.5
20

50.000

3.0

0.2
50

20,000

0.5

pA

Mn
pF

viv

20,000

Output Resistance

75

75

75

n

Output Short-Circuit Current

25

25

25

rnA

Supply Current

3.4

5.2

3.4

6.0

3.4

6.0

rnA

Power Consumption

102

156

102

160

102

180

mW

Slew Rate

6.0

Unity Gain Bandwidth

1.0

6.0
1.0

2.S

6.0

VIliS

1.0

MHz

Risetime

CL ~ 100pF, RL - 2kn

300

300

300

ns

Overshoot

CL ~ loopF, RL - 2kn

10

10

10

%

The following specifications apply for O·C :5 TA :5
(8007M and 8007AM):
Input Voltage Range
Common Mode Rejection Ratio

+ 70·C (8007C and 8007AC), and -55·C:5 TA:5 + 125·C
±10

±12

±10

±12

±10

±12

V

70

90

70

90

86

95

dB

Supply Voltage Rejection Ratio

70

Large Signal Voltage Gain
Output Voltage Swing

RL ~
RL~

Input Bias Current (either input)

TA = + 125°C
TA= + 70°C

Average Temperature Coefficient
01 Input Offset Voltage

300

25,000
10kn
2kn

±12
±10

70

600

±14
±13

±12
±10

±14
±13

±12
±10

2.0
SO
75

(Note 4)

.-----""9"""9--- Your

TC026011

Figure 3: Transient Response Test Circuit

Note: All typical values have been guaranteed by characterization and are not tested.

70

200

15,000

15,000

75

"VIV
VIV

±14
±13

V
V

1.0
30

nA
pA
50

"V/oC

ICLa007
TYPICAL PERFORMANCE CHARA~TERISTICS

10"
10"

~SII~ ••i&v

t-...

t\.

z 10"

C

...

10>

"....

10'

I!I
~

g

~!U:";.~'5V

8

T•• +25·C

1\

t\.

""-

10

I

10

100

'I

INPUT

7

~

\
~

TA =+2&"C
RL = 'CIkfi

I
1\

OUT..JT

i1

I,

~

10k lOOk 1M 10M

lk

~!:,,..! =(±\~~

_

I~

~

I!I

OUTPUT VOLTAGE SWING AS A
FUNCTION OF FREQUENCY

VOLTAGE FOLLOWER LARGE
SIGNAL PULSE RESPONSE

OPEN LOOP VOLTAGE GAIN

0'23458781

FIlEQUENCYCHzl

'CIk

TIME (~.)

'00k

10M

1M

FREQUENCY (Hz)
QP026001

OP025901

0P025801

INPUT BIAS CURRENT AS A
FUNCTION OF TEMPERATURE

TRANSIENT RESPONSE

OUTPUT SWING AS A FUNCTION OF
SUPPLY VOLTAGE
20

28

T.=25"C
R L ' 2kn

24

20

90"0

16

~

I
I

'2

,CrJ I
o

"

W

i

tI<
tI<

Vs "

f-

o

~
z

103

..a
~

~lSV

~
~

RISE TIME T.· 25 C
RL " 2 kl!
CL"loopF

5

1.0
TIME

2.0

1.S

....

1/

0

./

10

/V

10

//

;)
;)

V

POSIT.VE SWING/

~

/

to'

15

/

5

V

V NEGATIVE SWING

N

:::;

2.5

"

~

./
1 20

~

(ps)

40

60

80

100

120

15

10

5

0

140

SUPPLYV(lTAGE "V)

TEMPERATURE C·C)

0P026301

0P026101

0P026201

INPUT VOLTAGE RANGE AS A
FUNCTION OF SUPPLY VOLTAGE

OPEN LOOP VOLTAGE GAIN AS A
FUNCTION OF SUPPLY VOLTAGE

QUIESCENT SUPPLY CURRENT AS A
FUNCTION OF SUPPLY VOLTAGE
5

20

~
co
z
~

15
POSITIVE /

C
tI<

...

......

~
>

~

...

;)

AI"

10

0

5

~

I/,
V

/

/

V

/NEGAT(VE

T. "25'C

i

4

tI<
tI<

a>

3

~

2

!i
...

....

I-- I--

-

....

V

.0' L-.l-...l-....1..-L-L--l_.l....-J

o

5

10

15

0

SUPPL Y VOLTAGE C'V)

10

10

15

SUPPLY VOLTAGE "VI

0P026401

0P026S01



U

...>

2

~

- -r0- t-

~>
oS

...

;

10'

~

...
0
>
...

-15

25

65

105

10'

I--

'"~

' Rs "

iu

son

III
100

lk

10k

lOOk

FREQUENCY \Hzl

TEMPERATURE I'CI
OP026701

0 ... -

For additional information, see Application Note AO05.,

40-68

Note: All typlcal values have been guaranteed by characterization and are not tested.

~~~~001dtz V

8,0.0

Rs" 1 Mn

I-

10

100

~

'0

-55

WIDEBAND NOISE AS A FUNCTION
OF SOURCE RESISTANCE

INPUT VOLTAGE NOISE AS A
FUNCTION OF FREQUENCY

QUIESCENT SUPPLY CURRENT AS
A FUNCTION OF TEMPERATURE

I

o.1

100

-

~

~

=~~~(cHz
I

I

1

1k 10k 100k 1M 10M , _
SOURCE RESISTANCE (0)
OP026911

.U~UlLi...

ICL8021/ICL8022/
ICL8023

-I
N

Low Power Bipolar
Operational Amplifier
GENERAL DESCRIPTION
The Intersil ICL8021 series are low power operational
amplifiers specifically designed for applications requiring
very low standby power consumption over a wide range of
supply voltages. The electrical characteristics of the 8021
series can be tailored to a particular application by adjusting
an external resistor, RSET, which controls the quiescent
current. This is advantageous because IQ can be made
independent of the supply voltages: it can be set to an
extremely low value where power is critical, or to a larger
value for high slew rate or wideband applications.
Other features of the 8021 series include low input
current that remains constant with temperature, low nOise,
high input impedance, internal compensation and pin-forpin compatibility with the 741.
The Intersil 8022 (8023) consists of two (three) low power
operational amplifiers in a single 14(16)-pin DIP. Each
amplifier is identical to an 8021 low power op amp, and has
separate connections for adjusting its electrical characteristics by means of an external resistor, RSET, which controls
'the quiescent current of that amplifier.

•
•
•
•
•
•
•

VOS = 3mV Max (Adjustable to Zero)
± 1.SV to ± laV Power Supply Operation
Power Consumption - 20j.lW @ ±1V
Input Bias Current - 30nA Max
Internal Compensation
Pin-for-Pin Compatible With 741
Short Circuit Protected

ORDERING INFORMATION
ICLB021

C

PART
NUMBER

TV
LpaCkage
TV - TO-99 Metal can
PA - 8 pin Minidip
JD PD -

14 pin CERDIP
14 pin Plastic DIP

8021 only
8022 only

JE - 16 pin CERDIP
8023 only
PE - 16 pin, Plastic DIP
' - - - - - Temperature
C - Commercial - O·C to + 70·C
M - Military - -SS·C to + 12S·C
' - - - - - - - - Basic Part Number
8021 - Single
8022 - Dual
8023 - Triple

TEMPERATURE
RANGE

-

ICL8021/D
ICL8021CJA
ICL8021C8A
ICL8021 CPA
ICL8021CTY
ICL8021MJA
ICL8021MJD
ICL8021MTY

O·C
O·C
O·C
O·C
-SS·C
-SS·C
-SS·C

ICL8022/D
ICL8022CJD
ICL8022CPD
ICL8022MJD

O·C to 70·C
O·C to 70·C
-SS·C to + 12S·C

ICL8023/D
ICL8023CJE
ICL8023CPE
ICL8023MJE

O·C to 70·C
O·C to 70·C
-SS·C to + 12S·C

to
to
to
to
to
to
to

70·C
70·C
70·C
70·C
+ 12S·C
+ 12S·C
+12S·C

PACKAGE
DICE"
8 Lead CERDIP
8 Lead S.O.l.C
8 Lead MINIDIP
8 Lead Metal Can
8 Lead CERDIP
14 Lead CERDIP
8 Lead Metal Can

-

DICE
14 Lead CERDIP
14 Lead MINIDIP
14 Lead CERDIP

-

DICE
16 Lead CERDIP
16 Lead MINIDIP
16 Lead CERDIP

"Parameter MinIMax Limits guaranteed at 2S·C only for DICE orders.

4-69
Note: All typical values have been guaranteed by charscterization and are not tested.

N

FEATURES

I
fit

ICLII021l1CL~022/1CL8023
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................................ ±18V
Differential Input Voltage (Note 1) ....................... ±15V
Common Mode Input Voltage (Note 1) ................ ±15V
Output Short Circuit Duration .............. , ......... Indefinite
Power Dissipation (Note 2) ............................. 300mW
NOTE 1: For supply voltages less' than

Operating Temperature Range,
"
8021M .................... : .......... -55·C to +125·C
8021 C ..................................... O·C to + 70·C
Storage Temperature Range , ........... -65·C 10 + 150·C
Lead Temperature (Soldering. 10sec) ........ ~ ...... +300·C

'f 15V. the absolute maximum'input voltage is equal to the supply voltage,

NOTE 2: Rating applies for case temperatures io + 125'C; derate linearly at 5,6 mW I'C for ambient temperatures above + 95,·C.

In
Z&KO

V'

05026001

Figure 1: Functional Diagram

10 SET

8AL~,
-IN

2

,10
V·'SET

'IN

3·

OUT

_

'8
7

V-4

sBAL

y'

(outline dwg PAl

(outline dwg TV)

CD017501
CD017401

(outline dwg JE, PEl

(outline dwg JO, PO)

CD017t'101
CO0177ot

Figure 2: Pin Configurations

4-70
Note: All typical values have been guaranteed by characterization and are not tested.

1I0~OIb

ICL8021/ICL8022/ICL8023

~

-i
...

v'

-i
N
N

N
Col

TC034801

Figure 3: Voltage Offset Null Circuit

ELECTRICAL CHARACTERISTICS

(VSUPPLY = ±6V, la = 30j.lA, unless otherwise specified.)
8021C

8021M

CHARACTERISTICS

TEST CONDITIONS
MIN

TYP

MAX

MIN

TYP

UNIT
MAX

The following specifications apply for TA = 2S·C:
2

3

2

6

mV

Input Offset Current

.5

7,5

.7

10

nA

Input Bias Current

5

20

7

30

Input Offset Voltage

RS 5100kn

Input Resistance

Input Voltage Range
Common Mode Rejection Ratio

VSUPPLY'" ±15V
Rs 510kn

10

3

10

±13

±12

±13

V

70

80

70

80

dB

Supply Voltage Rejection Ratio

Rs 510kn

30

Output Resistance

Open Loop

2

Output Voltage Swing

RL <: 20kn, VSUPPLY ~ ± 1'5V

±12

RL<:IOkn, VSUPPLy=±15V·

±II

150

·±14
±I3

30

360

VOUT=O

Slew Rate (Unity Gain)
Unity Gain Bandwidth

RL = 20kn, VIN = 20mV

Transient Response (Unity Gain)

RL'" 20kn, VIN '" 20mV

Ri.setime
Overshoot

Mn

150

IlVN

2

kn

.,±12

±14

V

±II

±13

V

±I3

mA

±I3

Output Short-Circuit Current
Power Consumption

nA

3
±12

480

380

600

IlW

O.IS

0.16

V/JlS

270

270

kHz

1.3
10

1.3
10

IlS
%

The following specifications apply for O·C5TA5 +70·C (B021C) and -SS·C5TA5 +12S·C (B021M)
Input Offset Voliage
RS 5 lOkn

Input Offset Current
Input Bias Current
Average Temperature
Coefficient of Input
Offset Voltage
Average Temperature
Coefficient of Input
Offset Current

RS 5 lOkn

.

Large Signal Voltage Gain

RL = lOkn

50.

Output Voltage Swing

RL<: 10kn

±to

4-71
Note: All typical values have been guaranteed by characterization and are not ·tested.

2.0

4.0

2.0

7.5

mV

1.0

II

1.5

15

nA

10

32

15

50

nA

5

5

IlV/"C

1.7

0.8

pA/·C

50

200

V/mV

±IO

±IS

V

200
±13

=ICL8021/ICL8022/ICL8023
a

II

QUIESCENT CURRENT ADJUSTMENT

&'II

QUIESCENT CURRENT SETTING RESISTOR
(PIN a to V-)

QUIESCENT CURRENT SETTING RESISTOR
(PIN a to V-)
10

Vs

10pA

301lA

1001lA

±1.5

1.5MQ

470kn

l50kQ

-

±3

3.3MQ

1.lMQ

330kQ

lookQ

±6

7.5MQ

2.7MQ

750kQ

220kQ

±9

l3MQ

4MQ

1.3MQ

350kQ

£

.t_

3001lA

±12

laMQ

5.6MQ

1.5MQ

5l0kQ

±15

22MQ

7.5MQ

2.2MQ

620kQ

I~ ,

10"A

10M!!~IIIII~~~~
'~~

:z>

I

M!! ~IIIII~'~O~'~'OO~"A~
IQ = 300fjA

1.fI.Jo1"11111 U IIIII

100.)

o

2

4

6

8

10 12 14 16 18

5UPPL Y VOLTAGE I· VI
OPO.27501

TYPICAL PERFORMANCE CHARACTERISTICS·
(TA = + 2SoC, Vs = ±6V, 10 - 30,iA unless otherwise specified.)
INPUT BIAS CURRENT VS AMBIENT
TEMPERATURE

INPUT BIAS CURRENT VS
QUIESCENT CURRENT

DIFFERENTIAL INPUT IMPEDANCE VS
QUIESCENT CURRENT

lOll
100

C

i

...z.s

~
c
c

...

w
rr:
rr:

;:)

u

10

B

'"c
ii

~
iii

...

50

10

10

IQI_~,,!

1

5

i

C
!

-I-

I"

-

10

30

lOll

~

I IJ

-80

300

-ID"A

I I I

I

I

-IOO"A

-20 0 20

80

100

140

TEMPE RATURE ( CI

QUIESCENT CURRENT ",AI

QUIESCENT CURRENT ("AI

OP027701

0P027601

0P027801

SLEW RATE VS QUIESCENT
CURRENT

FREQUENCY RESPONSE VS
QUIESCENT CURRENT

PHASE MARGIN VS QUIESCENT
CURRENT
RL ·2011U

'iii'
w

5

J

. /~

~
w
C

...
rr:
iI
......

1/

~

4S

:l:z:

30

...

V

'"

...- ....

13
•
rr:

V

05

~IO

c/.

w
-..e..75
z

L

IL

01
10

30

100

30

300

QUIESCENT CURRENT ("AI

100

300

QUIESCENT CURRENT ("AI

0!'

0
0

...

40

~

"'..."

15

>

10

0

z

:;)

>

2

Z

5

:;)

0

RISE TIME

o

4

8

12

~

"z
~

RL • 20kfl

"'"

===

l-

S
>

I-

:;)

100

fI

300

0P028401

EQUIVALENT INPUT NOISE CURRENT
VS FREQUENCY

;i

~ 80

>

"...c...

__ 10 'IOOI~~

50

,

40

.r----

0

...

> 30

10

·30p.A

10' 10 ,.A

c/O

/

..

30

aUIESCENT CURRENT I,.AI

EQUIVALENT INPUT NOISE
VOLTAGE VS FREQUENCY

...

w

~
I i

OP02B301

.!:

10

Ys ' ,6Y

10

16

TIME l,.tlCl

OUTPUT VOLTAGE SWING VS
SUPPLY VOLTAGE

L

Vs' 'ISV

I

OP028201

30

't-..

5

i
rt

0

10
Ik
IOU.
FREOUENCY IHzI

10

:;)

2

:;)

0I-

"'-

...

c

~~

0-

!

50

...~

I-

"I~

.u

0

20

RL • tOka
CL'IOOpF

I-

~~

0-

>
!

...

~R, "50UI

80

MAXIMUM LOAD VS QUIESCENT
CURRENT

TRANSIENT RESPONSE

0

20

i

10

...Z

0-

:;)

!

0
'1

,3

,6

'10

50

SUPPLY VOL TAGE IVI

100

Ik

50

100

500

Ik

FREaUENCY 1Hz,

FREQUENCV 1Hz}

0P02a501

*ICL8021 C guaranteed only for O·C ::; T A ::;

500

0P0287Of

0P02II6OI

+ 70·C

4-73
Note: All typical values have been guaranteed by characterization and are not tested.

!i

ICL8043

,3 Dual JFET Input Operational .
g Amplifier
GENERAL DESCRIPTION

FEATURES

ThelCL8043 contains two FET input op amps, each
similar in performance .to the ICL8007. The inputs and
outputs are fully short circuit protected, and no latch-up
problems exist.· Offset nulling is accomplished by using a.
single pot (for each amplifier) connected to .th!! positive
supply voltage~ The devices have excellent common mode
.
rejection.

•
•
•
•
•

Very Low Input Current - 2pA Typical
High Slew Rate - 6VI j.I8
Internal Frequency Compensation
Low Power DIssipation - 135mW T.yplcal
Monolithic Construction

ORDERING INFORMATION
PART NUMBER

TEMPERATURE
RANGE

ICL8043MJE

- 55°C to 125°C

CERAMIC
16 Pin DIP

ICL8043CPE

O°C,to 70°C

Plastic
16 Pin DIP

ICL8043CJE

O°C to 70°C

CERAMIC
16 Pin DIP

PACKAGE

-...

_NUU

-IN

(outline dwgs JE. PEl
c0017901

08018701

Figure 1: Functional Diagram
(One Side)

Figure 2: Pin
Configuration
16 Pin DIP (Top View)

4-74
Note: All typical values have been guaranteed by characterization and are not tested.

.O~OIL

ICL8043
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................................ ±18V
Internal Power Dissipation (Note 1) .................. SOOmW
Differential Input Voltage ................................... ±30V
Input Voltage (Note 2) ...................................... ±1SV
Voltage between Offset Null and V+ ................. ±O.SV
Storage Temperature Range ............ -6S'C to + 150'C

Operating Temperature Range
8043M ............................... -5S'C to + 12S'C
8043C ..................................... O'C to + 70'C
Lead Temperature (Soldering. 10sec) ................. 300·C
Output Short-Circuit Duration ......................... Indefinite

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods m~y affect device reliability.
NOTES: 1. Rating applies for case temperatures to 12SoC; derate linearly at 9mWI"C for ambient temperatures above +9SoC.
2. For supply voltages less than ± 1SV, the absolute maximum input voltage is equal to the supply voltage.

ELECTRICAL CHARACTERISTICS

(VSUPPLY = ± 1SV unless otherwise specified)
8043M

SYMBOL

CHARACTERISTIC

8043C

TEST CONDITIONS

UNIT
MIN

TYP

MAX

10

20

MIN

TYP

MAX

20

50

The following specifications apply for TA = 2SoC:
VOS

Input Offset Voltage

lOS

Input Offset Current

RS < 100kn

0.5

liN

Input Current (either input)

2.0

RIN

Input Resistance

106

CIN
Ay

Input Capacitance

RO

Output Resistance

ISC

Output

3.0

20

Current

50

pA
Mn

2.0

SO,OOO

mV
pA

106

2.0
RL> 2kn, You! ~ ± 10V

Large Signal Voltage Gain
Short-Circu~

0.5

pF

20,000

VN

75

75

n

25

25

rnA

ISUPPLY

Supply Current (Total)

4.5

6

4.5

6.8

rnA

POISS
SR

Power Consumption

135

180

135

204

mW

Slew Rate

6.0

6.0

V/pB

GBW

Unity Gain Bandwidth

1.0

1.0

MHz

tr

Transient Response (Unity Gain)
Risetime
Overshoot

300
10

300
10

ns
%

The following specifications apply for O·C
t.VIN
CMRR

CL < 100pF, RL = 2kn

< TA < + 70°C

(8043C). - SS·C

< TA < + 12SoC

Input Voltage Range
Common Mode Rejection Ratio

PSRR

Supply Voltage Rejection Ratio

Ay

Large Signal Voltage Gain

t.VO

Output Voltage Swing

VOS

:np\ll Offset Voltage

liN

Input Current (either input)

t.VOSlt.T

Average Temperature Coefficient
of Input Offset Voltage

(8043M):

±10

±12

±10

±12

V

70

90

70

90

dB

70

70

300

25,000
±12

±14

±12

±14

RL> 2kn

±10

±13

±10

±13

15

30

2.0

15

TA = +70°C
75
(Note 3)

NOTE: 3. For Design only, not 100% tested.

4-75
Note: All typical values have been guaranteed by characterization and are not tested.

p.VN
VN

RL> 10kn

TA= +12SoC

600

15,000

V
V

30

60

mV

50

175

pA

nA
75

p'vrc

·S!1 ~:::'~~:RFORMANCE

CHARACTERISTICS

OPEN LOOP VOLTAGE GAIN AS A
FUNCTION OF FREQUENCY
10"
105 ~

ysJ.... = l15Y

TA=+U'C

l'\..

e--:..

10

..
...C
'"
~
z

~

r\..

l'\..

OUTPUT VOLTAGE SWING AS A
FUNCTION OF FREQUENCY
~

VOLTAGE FOLLOWER LARGE-5IGNAL
PULSE RESPONSE· .

v.:;.:.. •• 1~~

1-.
1\

~

I\..

"
.,.~
"II!

,

16

00(

i'\

0
Ik

10k

lOOk

1M

10M

FReQueNCY fHrI
OP020901

INPUT CURRENT AS A FUNCTION
OF TEMPERATURE

OUTPUT SWING AS A FUNCTION OF
SUPPLY VOLTAGE
20

-

TA 1=

I

~li

o

TL

I--

I

alc

=2Icll

POJITIVE SWI,

I
.5

I- Vsupp = :t15V

~:~

1.0
1.5
TIME (.0)

2.0

2.5

.0

80
80 100 .120
TEMPERATURE rC)

1.0

o

:t5
:tIO
:tIS
SUPPLY VOLTAGE

0_

0P030101

OPEN LOOP VOLTAGE GAIN AS A
FUNCTION OF SUPPLY VOLTAGE

V

V"

./V
V
I-- I-- NEjATtE jWlNj- I--

~

TA = 25°C

~

i/17

,/

RISETIME

1/

-8

100 lk 10k lOOk 1M 10M
FREQUENCY (HI)

TRANSIENT RESPONSE

'OUTPUT

-I-i-I-

~-

8

00(

~

r

INPUT

Q

0P029801

..•

I I Yiu" •• ,5V
: I ~~;H:

8

TA • +25°C
RL"OkG

32

INPUT VOLTAGE RANGE AS A
FUNCTION OF SUPPLY VOLTAGE

QUIESCENT SUPPLY CURRENT AS A
FUNCTI.ON OF SUPPLY VOLTAGE

•

20

:/,

T. -'H'C

1/ V

I-- i- POSIT/

i/7

l/V

-

I.-

I-'"

~ciATlVE- -

±20

.--

I.-~

V
1~0~~--:t~5-L-:t~10~--:t~15~-:t20~
SUPPLY VOLTAGE

o

±5
±10
±15
SUPPLY VOLTAGE

0P030401

:t20
OP030501

4-76
Note: All typical values have been guaranteed by characterization and afe not tested.

2
:t5

±10
±15
SUPPLY VOLTAGE

±20

ICL8043
TYPICAL PERFORMANCE CHARACTERISTICS (CONT.)
TOTAL QUIESCENT SUPPLY
CURRENT AS A FUNCTION OF
TEMPERATURE

INPUT NOISE VOLTAGE AS A
FUNCTION OF FREQUENCY

WIDEBAND NOISE AS A FUNCTION
OF SOURCE RESISTANCE

104
Vs= :t11Y

-- r-- ....

-

-;01000

E
.:
>

___ BANDWIDTH
,L... 100 _ . 10H, TO 100kH,.T

1"--0

..~

r--

r

RS=1Mtl

r--;

~

II~: = SOlI

IE

-

10.0

i--'

c

...

1111 I
-15
25
15
TEMP£RATURE COC)

10

105

100

Ik

10k

BANDWIDTH
• 01 H. T.O
01

FREQUENCY (Hz)
OP030701

:::::

Hr'::

100

lOOk

."

1.0

I-

~

>'

Ik·

10k

lOOk

1M

10M 100M

SOURCE RESISTANCE 1m
0P030901

0P030801

v+

10
LC01170t

DS018801

Figure 4: Channel Separation Test Circuit

Figure 3: Offset Voltage Null Circuit

CHANNEL SEPARATION

"

0

Channel separation or crosstalk is measured using the
circuit of Figure 4. One amplifier is driven so that its output
swings ±10V; the signal amplitude seen in the other
amplifier (referred to the input) is then measured. Typical
performance is shown in Figure 5.
.

VOUT (A)

Channel Separation = 20 log (

VIN (8)

T1~

~

·c

.... - I

R=} I'
~

)
10
10
'00

~
't

'Ok
lOOk
FREQUENCY (Hz)

,M

OP031001

Figure 5: Channel Separation Performance

4-77
Note: All typical values have been guaranteed by characterization and are not tested.

.. ICL8043

I

APPLICATIONS

as a normal amplifier while the voltage necesSlity to zero its
offset voltage is stored on the integrator comprised of A2
and Ct.

Applications for any dual amplifier fall into two categories.
There are those which use the two-in-one package concept
simply to save circuit-b9ard space and cost, but more
interesting are those circuits whete the two sides of the dual
are used to complement one another in a 'subsystem
application. The circUits which follow have been selected on
this basis.

The advantage of .this circuit is that it allows chopper
amplifier performance to be achieved at one-tenth the cost.
The only limitation is that during the offset nulling mode, A1
is disconnected from the input. However, in most data
acquisition systems, many inputs are scanned sequentially.
It is fairly simple to synchronize the offset nulling operation
so that it does not occur when that particular amplifier is
being "looked at". For the component values shown in
F;=igure 3, and assuming a total leakage of 50pA at the
inverting input of A2, the offset voltage referred to the input
of At will drift away from zero at only 40p.V/sec. Thus, the
offset nulling information stored on Ct can be "refreshed"
relatively infrequently. The measured offset voltage of At
during the amplification mode was 11 p.V; offset voltage drift
with temperature was less than 0.1 p.V

AUTOMATIC OFFSET SUPPRESSION
CIRCUIT
The circuit shpwn in Figure 6 uses one amplifier (At) as a
normal gain stage, whil!3 the other (A2) forms pari of an
offset voltage zeroing loop. There are two modes of
operation which occur sequentially. First, an offset null
correction mode occurs during which the offset voltage of
At is nulled out. Following this nulling operation, At is used

rc.

TC026301

'SW1, SW2, .. SW3 ARE ALL
PART OF A SINGLE IH5043 CMOS
ANALOG SWITCH CONNECTED AS
SHOWN IN FIGURE 6(b)

Figure 6(a): Automatic Offset Null Circuit

+IV

+l1V

LOGIC
IM'UT

CDD18001

Figure 6(b)

4-78
Note: All typical values have been guaranteed by characterization and are not tested. .

ICL8043

.....

~-

HORIZONTAL

~

50MSIDIV

~~
WF015301

Figure 7: Staircase Generator Circuit

1H5042

,.
1k!1

HORIZONTAl.. '" 2GOmSIDIY

VOUT YREF

WF015401

Figure 8.: Analog Counter Circuit

STAIRCASE GENERATOR

ground to assure complete discharge. The upper trip point
could then be adjusted independently to determine the
pulse count.

The circuit shown in Figure 7 is a high input impedance
version of the so-called "diode pump" or staircase generator. Note that charge transfer takes place at the negativegoing edge of the input-signal.

SAMPLE & HOLD CIRCUIT
Two important properties of the 8043 are used to
advantage in this circuit. The low input bias currents give
rise to slow output decay rates ("droop") in the hold mode,
while the high slew rate (6V/IJS) improves the tracking
speed and the response time of the circuit. See Figure 6.
The ability of the circuit to track fast moving inputs is
shown in Figure 10A. The upper waveform is the input
(10V/div), the lower waveform the output (5V/div). The
logic input is high.
Actual sample and hold waveforms are shown in Figure
10B. The center waveform is the analog input, a ramp
moving at about 67V!ms, the lower waveform is the logic
input to the sample & hold; a logic" 1" initiates the sample
mode. The upper waveform is the output, displaced by
about 1 scope division (2V) from the input to avoid
superimposing traces. The hold mode, during which the
output remains constant, is clearly visible. At the beginning
of a sample period, the output takes about 81JS to catch up
with the input, after which it tracks until the next hold period.

The most common application for staircase generators is
in low cost counters. By resetting the capacitor when the
output reaches a predetermined level, the circuit may be
made to count reliably up to a maximum of about 10. A
straightforward circuit using a LM311 for the level detector,
and a CMOS analog gate to discharge the capacitor, is
shown in Figure 8. An important property of this type of
counter is the ease with which the count can be changed; it
is only necessary to change the voltage at which the
comparator trips; A low cost A-O converter can also be
designed using the same principle since the digital count
between reset periods is directly proportional to the analog
voltage used as a reference for the comparator.
A considerable amount of hysteresis is used in the
comparator shown in Figure 8. This. ensures that the
capacitor is completely discharged during the reset period.
In a more sophisticated circuit, a dual comparator "window
detector" could be used, the lower trip point set close to

4-79
Note: All typical values. have been guaranteed by characterization and are not tested.

~ ICLa043
51!
-11V

10

7

ANALOG .

OUTPUT

11

INPUT

I

-11V

•

•

10.000 pF
POLYSTYRENE

+av = > IIAIIPLI MODE

IH5043

IN = > HOLD MODE

LC011801

Figure 9: Sample And Hold Circuit

....... r

....... ........

A.

l

\

r

....... .......

\
WF015501

r\
\,. .....

~

r-.... ...... ,

~

TOP: INPUT (10V/DIV)
BOTTOM: OUTPUT (5V/DIV)
HORIZONTAL: 10jlll/QIV

.......

--

WF015601

TOP: 2V1DIV
CENTER: 2V1DIV
BOTTOM: 10VlDIV
HORIZONTAL: 10jlll/DIV

Figure 10A

.

4-80
Note: All typical values have been guaranteed by characterization· and are not tested.

Figure 10B

.

ICL8043

..

INSTRUMENTATION AMPLIFIER
A dual JFET-input operational amplifier is an attractive
component around which to build an instrumentation amplifier because of the high input resistance. The circuit shown
in Figure 11 uses the popular triple op-amp approach. The
output amplifier is a High Speed 741 (741 HS, slew rate
guaranteed ~ 0.7V/p.s) so that the high slew rate of the
8043 is utilized to the full extent. Input resistance of the
circuit (either input, regardless of gain configuration) is in
excess of 1012 ohms.
For the component values showl), the overall amplifier
"R1 + R2
gain is 200 (front end gain = - - - , back end
gain, = Rs/R4).
R2
Common mode rejection is largely determined by the
matching between R4 and R5, and RS and R7. In applications where offset nulling is required, a single potentiometer
can be connected as shown in Figure 12.
Another popular circuit is given in Figure 13. In this case
the gain is 1 + R1/R2, and the CMRR determined by the
match between R1 and R4, R2 and R3.
For more information on FET input operational amplifiers,
see Intersil Application Bulletin A005 "The 8007: A High
Performance FET-input Operational Amplifier."

AF030211

Figure 13: Modified Instrumentation Amplifier

..
..

... '"
AF0300tI

Figure 11: Instrumentation Amplifier

AF030111

Figure 12: Offset Nulling Both Amplifiers
With One Potentiometer

Note: All tvDical values have been auaranteed bv characterization and are not tested.

ICL8048/1CL8049
Log! Antilog' Amplifier
GENERAL DESCR:IPTION

FEATURES

The 8048 is a monolithic logarithmic amplifier capable of
handling six decades of current input, or three decades of
voltage input. It is fully temperature, compensated and is
nominally designed to provide 1 volt of output for each
decade change of input. For increased flexibility, the scale
factor, reference current and offset voltage are externally
adjustable.
.
The 8049 is the antilogarithmic counterpart ofthe 8048; it
. nominally generates one decade of output voltage for each
1 volt change at the input.

•
•
•
•
•
•

1/2% Full Scale Accuracy
Temperature Compensated for O·C t.o + 70·C
Operation
Scale Factor 1VIDecade, Adjustable
120dB Dynamic Current Range (8048)
60dB Dynamic Voltage Range (8048 & 8049)
Dual JFET-Input Op-Amps

ORDERING INFORMATION
PART NUMBER

ERROR (25·C)

TEMPERATURE RANGE

ICL8048BCJE

30mV

O·C to +70·C

16 Pin CERDIP

ICL8048BCPE

30mV

O·C to +70·C

16 Pin Plastic DIP

ICL8048CCJE

60rnV

O·C to +70·C

16 Pin CERDIP

ICL8048CCPE

60mV

O·C to +70·C

16 Pin Plastic DIP

ICL8049BCJE

10mV

O·C to +70·C

16 Pin CERDIP

ICL8049BCPE

10mV

O·C to +70·C

16 Pin Plastic DIP

ICL8049CCJE

25mV

O·C to +70·C

16 Pin CERDIP

ICL8049CCPE

25mV

O·C to +70·C

16 Pin Plastic DIP

PACKAGE

.,'NPUT
.--r-----t.:"f'I,OOT

v,.
~'.

\

V,.

GAl.

At OUTPUT

A10UTPUT

05019021

05019121

(ICL8048)

(ICL8049)

Figure 1: Functional Diagram

GROUND'

A, INPUT

GAIN
IREF

NO CONNECnoN 3

,.. NO CONNECTION

A1 OFFSET NULL ..

13

A2 OFFSET NOLL

A, OFFSET NULL 4

A1 OFFSET NULL 5

11

A2 OFFSET NULL

A1 OFFSET NULL

A10UTPUT
NO CONNECTION

,

•

.

10

vYour

A, OUTPUT 7

NO CONNECTION

VIN
1

NO CONN~CTION

CD018111

GROUND

A21NPUT
A2 OFFSET NULL
1

A20FFSET NULL

v+
o Your
•

NO CONNECTION

CD02081'

Figure 2: Pin Configurations (Outline Dwgs, JE, PEl

302800-002
Note: All typical values have been guaranteed by characterization and are not tested.

ICL8048/ICL8049
ABSOLUTE MAXIMUM RATINGS (ICL8048)
Operating Temperature Range .............. O°C to + 70°C
Output Short Circuit Duration ........................ Indefinite
Storage Temperature Range ............ -65°C to + 150°C
Lead Temperature (Soldering, 10sec) ................. 300°C

Supply Voltage ................................................ ±18V
liN (Input Current) ............................................. 2mA
IREF (Reference Current) ................................... 2mA
Voltage between Offset Null and V+ ................. ±O.5V
Power Dissipation ......................................... 750mW

ELECTRICAL CHARACTERISTICS (ICL8048) Vs = ±15V, TA = 25°C, IREF = 1rnA, scale factor adjusted
for 1V1decade unless otherwise specified.
PARAMETER

8048BC

TEST CONDITIONS

MIN

TYP

8048CC
MAX

MIN

TYP

UNIT

MAX

Dynamic Range
liN (lnA - 1mA)
VIN (10mV - 10V)

RIN = 10k!1

Error, % of Fu!1 Scale

TA = 25°C, liN = InA to lmA

.20

0.5

.25

1.0

%

Error•. % of Full Scale

TA-O°C to +70·C.
liN = InA to lmA

.60

1.25

.80

2.5

%

Error, Absolute Value

TA - 25·C, liN -InA to lmA

12

30

14

60

mV

Error, Absolute Value

TA=O·C to +70·C
liN = InA to lmA

36

75

50

150

mV

Temperature Coefficient of VOUT

liN = InA to lmA

O.B

0.8

Power Supply Rejection Ratio

R"ferred to Output

2.5

2.5

Offset Voltage (AI & A2)

Before Nulling

15

Wideband Noise

At Output, for liN = 1COIlA

Output Voltage Swing

120
60

dB
dB

120
60

mvrc
mVIV

15

25

250

50

"V(RMS)
V

RL -10k!1

±12

±14

±12

±14

Rl,=2k!1

±10

±13

±10

±13

Power Consumption
Supply Current

mV

250

V

150

200

150

200

mW

5

6.7

5

6:7

mA

TYPICAL PERFORMANCE CHARACTERISTICS
TRANSFER FUNCTION FOR
CURRENT INPUTS

TRANSFER. FUNCTION FOR
VOLTAGE INPUTS

SMALL SIGNAL BANDWIDTH AS A
FUNCTION OF INPUT CURRENT

.....

i

~

IREF-'mAo

....

r-

--

- i--r-

I:I

V

vt
-

-

--

-- -

~

~ r--- ---- -- -.- -- -j "'" --

i;1

~

'0

-

10 11

OP031101

MAXIMUM ERROR VOLTAGE AT
THE OUTPUT AS A FUNCTION OF
INPUT CURRENT
200

:;:

~

'.i
~

0

>

E

I 1
-I I

'25

~
:>

so

°

10·'

.~
>

I
~

.

!
'"

804B Be 125"CI

25

J
10-8 10- 7

10-1

1
10'S

10-4

10-':J

INPUT CURRENT I"'''PSI

10-5

OP031201

c

tI048 Ie IO"C 10 10"CI
8048 cc 125~C)

IS

10 7

OPOOl301

".

.so

.,.

"

III I"·N·'O'"

.,.

81MB CC fO"C to 1O"el

100

111 I 1111

lll.JJ:8i

.00

,.

8048 cc

so

,.
°

SMALL SIGNAL VOLTAGE GAIN AS A
FUNCTION OF INPUT VOLTAGE FOR
RS= 10kn
'000

"'"

1011'1'1

III

(Rs" 'Olin.,

n

,ov

IV

'0

,
_0'

lmV

.o.V'N

Iii

I

-}_.

-10mV

/ogloe

Wi\i'iT" - -.
You:
"IN

:±f 1ft

°,

INPUT VOLTAGE

QPOS140r

~'IIOLTAGE GAIN·

125~CI

~.ct.-;ti
l00mY

10-3

INPUT CUARENT IAM'SI

MAXIMUM ERROR VOLTAGE AT
THE OUTPUT AS A FUNCTION OF
INPUT VOLTAGE

!:l:

8CM8 CC IO"C 107O"CI

.so

'00

'"
'~"
'"

I I

17S

10 •

INPUT CURRENT I AMPS I

INPUT VOLTAGE

,,~v;v

I

"~

lOOn,"

"

'ov

INPUT VOLTAGE
QP031501

4-83
Note: All typical values have baan guaranteed by characterization and are not tested.

0P031601

I
.....
n

2

I'"

_
CD

ICL8048/ICL8049
ABSOLUTE MAXIMUM RATINGS (ICL8049)
Supply Voltage ............ '.................•...'; .............. ±18V
VIN (Input Voltage) ....•......•........,•..............•...... ±1SV
IREF (Reference Current) .............•..................... 2mA
Voltage between Offset Null and V+ ..............•.. ±o.SV
Power Dissipation .•...•..•................................ 7S0mW

Operating Temperature Range .............. O·C to + 70·C
Output Short Circuit Duration ........................ Indefinite
Storage Temperature Range ............ -6S·C to + 1S0·C
Lead Temperature (Soldering, 10soo) ................. 300·C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. and functional
operation of the device at these or any other conditions above those Indicated in the operational seclions of the specHications is not implied. Exposure to
absolute maximum rating conditions 'for extended periods may affact device reliability.

ELECTRICAL CHARACTERISTICS (ICL8049)

Vs = ± 1SV, TA = 2S·C, IREF = 1mA, scale factor adjusted

for 1 decade (out) per volt (in), unless otherwise specified.
8049BC
PARAMETER

8049CC
UNIT

TEST CONDITIONS
MIN

TYP

MAX

MIN

TYP

MAX

Dynamic Range (VOUT)

Vour-10mV to 10V

Error. Absolute Value

TA = 2S·C. OV:S VIN:S 3V

3

10

5

25

mV

Error. Absolute Value

TA = O·C to + 70·C.
OV:SVIN:S3V

20

75

30

150

mV

Temperature Coefficient. Referred to VIN

VIN ~3V

0.38

0.55

Power Supply Rejection Ratio

Referred to Input, for
VN-OV

2.0

2.0

60

Offset Voltage (At &: A2)

Before Nulling

15

Wideband Noise

Referred to Input, for
VIN sOV

26

Output Voltage Swing

dB

60

25

IS

mV

50

26

p.V(RMS)
V

RL= 10kn

±12

tl4

±12

±14

RL=2kn

±IO

±13

±IO

±13

Power Consumption

mVl·C
p.VIV

V

150

200

150

200

mW

5

6.7

5

6.7

rnA

Supply Current

TYPICAL PERFORMANCE CHARACTERISTICS
TRANSfER FUNCTION
(VOUT AS A FUNCTION OF VIN)
'0

MAXIMUM ERROR VOLTAGE REFERRED TO THE
INPUT AS A FUNCTION OF VIN

r-,....,........--..--...-.,............

.0

r--r-..,.....,..--.---r--,,............,

.00' L.....L.....I..-L--I--ll.-L...J....JI
-4

-3

-2

-1

0

+1

+2

+3

.4

,,..PUT VOLTAGE (VI

INPUT VOLTAGE (VI
OP031701

OP031801

4-84
Note: All typical values have been guaranteed by characterization and are not tested.

.D~DIl

ICL8048/ICL8049
TYPICAL PERFORMANCE CHARACTERISTICS (CONT.)
SMALL SIGNAL BANDWIDTH AS A FUNCTION OF
INPUT VOLTAGE

SMALL SIGNAL VOLTAGE GAIN AS A FUNCTION
OF INPUT VOLTAGE
-100

I

~
~

:i

IREF"' lmA.

-lMr--r~~~-+--+--+~
-:~=-~ - - --

-10 i'\.

z
C

"

loo.""I.I',--.f---+~_- - ____ ---

I

- - - : = --

-' 10'

i

-23

,.

r--- --

--

w

~g

-=

I---

-0.0 1

o

"f'\

--

-- r- -- -t--

,J

ICL8048 OFFSET AND SCALE FACTOR
ADJUSTMENT'"

The ICL8048 relies for its operation on the well-known
exponential relationship between the collector current and
the base-emitter voltage of a transistor:

11

A log amp, unlike an op-amp, cannot be offset adjusted
by simply grounding the input. This is because the log of
zero approaches minus infinity; reducing the input current to
zero starves 01 of collector current and opens the feedback loop around Al. Instead, it is necessary to zero the
offset voltage of Al and A2 separately, and then to adjust
the scale factor. Referring to Figure 3, this is done as
follows:
1) Temporarily connect a 10kU resistor (RO) between
pins 2 and 7. With no input voltage, adjust R4 until
the output· of Al (pin 7) is zero. Remove RO.
Note that for a current input, this adjustment is not
necessary since the offset voltage of Al does not
cause any error for current-source inputs.
2) Set liN = IREF = lmA. Adjust Rs such that the
output of A2 (pin 10) is zero.
3) Set liN = lIlA, IREF = 1mA. Adjust R2 for VOUT = 3
volts (for a 1 volt/decade scale factor) or 6 volts (for
a 2 volt/decade scale factor).
Step #3 determines the scale factor. Setting liN = lIlA
optimizes the scale factor adjustment over a fairly wide
dynamic range, from 1mA to 1nA. Clearly, if the 8048 is to
be used for inputs which only span the range 100pA to
1mA, it would be better to set liN = 1001lA in Step #3.
Similarly, adjustment for other scale fa«tors would require
different liN and VOUT values.

(1)

For base-emitter voltages greater than l00mV, Eq. (1)
becomes
IC = IseQVBE/kT

(2)

From Eq. (2), it can be shown that for two identical
transistors operating at different collector currents, the VBE
difference (~VBE) is given by:

= -2.303 xkT
- log10 [IC1]
IC2
q

(3)

Referring to Figure 3, it is clear that the potential at the
collector of 02 is equal to the ~ VSE between 01 and 02.
The output voltage is ~ VSE multiplied by tl1egain of A2:

(Rf+R2R2)(kT)109l0
[~]
q
IREF

r-- - --

r- --

1---

--

I

OP032001

ICL8048 DETAILED DESCRIPTION

IC = Is[e qVBE/kT -

-i'\.

-

I

INPUT VOLTAGE tVI
0P031901

VOUT = -2.303

I

-Il 1

INPUT VOLTAGE IV)

~VBE

'\

-- --

n

(4)

"See A053 for an automatic offset nulling circuit.

4t

The expression 2.303 x has a numeri~al value of 59mV
at 25°C; thus in order to generate 1 volt/decade at the
output, the ratio (Rl + R2)/R2 is chosen to be 16.9 For this
scale factor to hold constant as a function of temperature,
the (Rl + R2)/R2 term must have a l/T characteristic to
compensate for kT/q.
In the ICL8048 this is achieved by making Rla thin film
resistor, deposited on the monolithic chip. It has a nominal
value of 15.9kn at 25°C, and its temperature coefficient is
carefully designed to provide the necessary compensation.
Resistor R2 is external and should be a low T.C. type; it
should have a nominal value of 1kn to provide 1 volt/
decade, and must have an adjustment range of ±20% to
allow for production variations in the absolute value of R1.
4-85

Note: All typical values have been guaranteed by characterization and are not tested.

II
~

0.

···.lIn~OI1.

ICLa048/1C~L8049

-a
!
R.
GROUNO

,5.111W

c.

GAIN 15

A.OUTPUT

.{

I
R.
'I
L. _ ""1M- _ ...J

'CJI(O

. - (LOW T.c.)

,KO

LC028801

Figure 3: ICL8048 Offset and Scale Factor Adjustment

ICLB049 DETAILED DESCRIPTION'

For voltage references equation 7 becomes

The ICL8049 relies on the'sam8 logarithmic properties Of
the transistor as the ICL8048; The input voltage forces a
specific 6.VSE between .01 and Q2 (Figure 4). This VSE
difference is converted into Ii difference of collector currents by the transistor pair. The equation governing the
behavior of the transistor pair is derived from (2) on the
.
previous page and is. as follows:

ROUT
[
-R2
qVIN]
VOUT=VREFX-- exp
x-RREF
(R1 + R2)
kT

ICL8049 OFFSET AND SCALE' FACTOR
ADJUSTMENT*
As with the IQg amplifier, the antilog amplifier requires
three adjustments. The first step is to null out the offset
voltage of A2. This is accomplished by reverse biasing the
base-emitter of Q2. A2 then operates as a unity gain buffer
with a grounded input. The second step forces VIN = 0; the
output is adjusted for VOUT = 10V.Thls step essentially
"anchors" one point on the transfer function. The third step
applies a specific input and adjusts the output to the correct
voltage. This sets the scale factor. Referring to Figure 4, the
exact procedure for 1 deCade/volt is as follows:
1) Connect the input (pin #" 16) to + l5V. This reverse
biases the base-emitter of Q2. Adjust R7 for
VOUT - OV. Disconnect the input from + l5V.
2) Connect the input to Ground. Adjust R4 for
VOUT = 10V. Disconnect the input from Ground.
3) Connect the input to a precise 2V supply and adjust
R2 for VOUT -100mV.
.
The procedure outlined above optimizes the performance
over a 3 decade range at the output (i.e., VOUT froml0mV
to 10V). For a more limited· range of output voltages, for
example 1V to 10V, it would be better to use a precise 1 volt
supply and adjust for VOUT = lV. For other scale factors
/!.nd/or starting points, different values for R2 and RREF will
be needed, but the same basic procedure applies.

'IC1 = exp[q6.VSE]
Ic:!
. kT
When numerical values for q/kT are put into this equation, it is found that a 6.VSE of 59mV (at 25°C) is required to
change the collector current ratio by a factor of ten. But for
ease of application; it is desirable that a 1 volt cHange at the
input'generate a tenfold change at the output. The requited
input attenuation is achieved by the network comprising R1
and R2. In order that scale factors other than one decade
per volt may be selected, R2 is external to the chip. It
should have a value. of 1kn, adjustable ± 20%, for one
decade per volt. R1 is a thin film resistor deposited on the
monolithic chip; its temperature characteristics are chosen
to compensate the temperature dependence of equation 5,
as explained on the previous page.
The overall transfer function is as follows:
lOUT
[-R2
qVIN]
IREF = exp (R1 + R2) x kT

(6)

Substituting VOUT = lOUT x ROUT gives:
VOUT = ROUT IREF exp [

-R2
qVIN]
x-(R1 + R2)
kT

(8)

(7)

'See A053 for an automatic offsel. nulling circuit

4-86
Note: All Iypicel values have been guaranteed by characterization and are' not tested.

.U~U[l

ICL8048/ICL8049

,..(Ii

.
-.p
!

..

CD

.....

C+1Il/)

R.
1OICO

....

...

c.

.

7

"'pF

....

CD
0
CD

1OICO

•

+-

14~IOUT

R•

R.
_0

R.
11<0

KO

..,

....

RouT

CLOW
T.e.)

..

_0

R.

.

'KO

VouT

.

.

y.
LC028701

Figure 4: ICL8049 Offset and Scale Factor Adjustment
EFFECT OF VARYING "K" ON THE LOG AMPLIFIER

APPLICATIONS INFORMATION
ICL8048 Scale Factor Adjustment
The scale factor adjustment procedures outlined previously for the ICl8048 and ICl8049, are primarily directed
towards setting up 1 volt (~VOUT) per decade (~IIN or
~VIN) for the log amp, or one decade (LWOUT) per volt
(~VIN) for the antilog amp.
This corresponds to K = 1 in the respective transfer
functions:
log Amp: VOUT = -K log

liN
10[-1
IREF

.

'REF·'mA
ROUT -10kn

(9)

V
- IN
Antilog Amp: VOUT = ROUT IREF 10-K

(10)
INPUT VOLTAGE IV)

By adjusting R2 (Figure 3 .and Figure 4) the scale factor
"K" in equation 9 and 10 can be varied. The effect of
changing Kis shown graphically in Figure 5 for the log amp,
and Figure 6 for the antilog amp. The nominal value of R2
required to give a specific value of K can be determined
from equation 11. It should be remembered that R1 has a
±20% tolerance in absolute value, so that allowance shall
be made for adjusting the nominal value of R2 by ±20%.
R2

=

941
(K-.059)

n

OP032101

Figure 5
EFFECT OF VARYING "K" ON THE ANTILOG AMPLIFIER
12

~

(11)

~

.......

~
g

~

Although the op-amps in both the ICl8048 and the
ICl8049 are compensated for unity gain, some additional
frequency compensation is required. This is because the log
transistors inthe feedback loop add to the loop gain. In the
8048, 150 pF should be connected between Pins 2 and 7
(Figure 3). In the 8049, 200 pF between Pins 3 and 7 is
recommended (Figure 4).

........

IREF·,rnA

"-

~

~.~
..... -. ~
.::". L'-

~

Frequency Compensation

~

10

~

-r-

6
-2

"-

l"11li

10-1010-1 10-1 10-7 10-1 10-5 10-4 10-3

INPUT CURRENT CAMPS)
OPOG2201

Figure 6
4-87

Note: All typical values have been guaranteed by characterization and ara not tasted.

i1CL8048/ICL8049

d Error Analysis
::::.

!

2_

d_·

Performing a meaningful error analysis of a circuit containing log and antilog amplifiers is more complex than
dealing with a similar circuit involving only op-amps. In this
data sheet every effort has been made to simplify the
analysis task, without in any way compromising the validity
of the resultant numbers.
The key difference in making error calculations in log/
antilog amps, compared with op-amps, is that the gain of
the former is a function of the input signal level. Thus, it is
necessary, when referring errors from output to input, or
vice versa, to check the input voltage level, then determine
the gain of the circuit by referring to the graphs given in the
Typical Performance Characteristics section.
The various error terms in the log amplifier, the ICL8048,
are Referred To the Output (RTO) of the device. The error
terms in the antilog amplifier, the ICl:.8049, are Referred To
the Input (RTI) of the device. The errors are expressed in
this way because in the majority of systems Ii number of log
amps interface with an antilog amp, as shown in Figure 7.

input voltage. This is because the output amplifier, A2, has
an offset voltage drift which is directly transmitted to the
output. When this error is referred to the input, it must be
divided by the voltage gain, which is input voltage dependent. At VIN = 3V, for example, errors at the output are
multiplied by 1/.023 (= 43.5) when referred to the input.
TRANSFER FUNCTION FOR CURRENT INPUTS

ll:

~ ol--"'Ioo.:+-+"""io'::

~-.~+-+""'"~

~ -4 1---1C---+--+-+="'"40.O-+-~
~ -.I--I--I--I--I--I--~
~L-~~~~

10- 10 lo-t

,0-'

__~~~

10- 7 10-1 10-' 10-4 10-3

INPUT CURRENT IAMI'S)

Actual output will Ii.
within sheded .... for

8048 BC 8t 25·C
OP032301

Figure 8

ERROR OUE TO A IRTO)
-.mV

It is important to note that both the ICL8048 and the
ICL8049 require positive values of IREF,· and the input
(ICL8048) or output (ICL8049) currents (or voltages) respectively must also be positive. Application of negative liN
to the ICL8048 or negative IREF to either circuit will cause
malfunction, 'and if maintained for long periods, would lead
to device degradation. Some protection can be provided by
placing a diode between pin 7 and ground.
LDOO700f

Figure 7
It is very straightforward to estimate the system error at
node (A) by taking the square root of the sum-of-the
squares of the errors of each contributing block.
Total Error =

v'x2 + y2 + z2

at (A)

If required, this error can be referred to the system output
through the voltage gain of the antilog circuit, using the
voltage gain versus input voltage plot.
The numerical values of x, y, and z in the above equation
are obtained from the maximum error voltage plots. For
example, with the ICL8048BC, the maximum error at the
output is 30mV at 25°C. This means that the measured
output will be within 30mV of the theoretical transfer
function, provided the unit has been adjusted per the
procedures described previously. Figl,!re 8 illustrates this
point.
To determine the maximum error over the operating
temperatu~e range, the 0 to 70°C absolute error values
given in the table of electrical characteristics should be
used. For intermediate temperatures, assume a linear
increase in the error between the 25°C value and the 70·C
value.
For the antilog amplifier, the only difference is that the
error refers to the input, i.e., the horizontal axis. It will be
noticed that the maximum error voltage of the ICL8049,
over the temperature range, is strongly dependent on the

SETTING UP THE REFERENCE CURRENT
In both the ICL8048 and the ICl8049 the input current
reference pin (lREF) is not a true virtual ground. For the.
ICl8048, a fraction of the output voltage is seen on Pin 16
(Figure 3). This does not constitute an appreciable error
provided VREF is much greater than this voltage. A 10V or
15V reference satisfies this condition. For the ICl8049, a
fraction of the input voltage appears on Pin 3 (Figure 4),
placing a similar restraint on the value of VREF.
Alternatively, IREF can be provided from a true current
source. One method of implementing such a current source
is shown in Figure 9.

LOG OF RATIO CIRCUIT, DIVISION
The 8048 may be used to generate the log ofa ratio by
modulating the IREF input. The transfer function remains
the same, as defined by equation 9:
VOUT

= -Klog10

[~]
IREF

(9)

Clearly it is possible to perform division using just one
ICl8048, folJowed by an ICl8049. For multiplication, it is
generally necessary to use two log amps, summing their
outputs into an antilog amp.
To avoid the problems caused by the IREF input not being
a true virtual ground (discussed in the previous section), the
circuit of Figure 9 is again recommended if the IREF input is
to be modulated.

Note: All typical values have been guaranteed by characterization and are not tested,

ICL8048/ICL8049
ERROR, % OF FULL SCALE The error as a percentage
of full scale can be obtained from the following relationship:

.1SY

VREFf

J

.,

100 x Error, absolute value
Error, % of Full Scale = -::--:::--=---:-:-:--FuliScale Output Voltage
TEMPERATURE COEFFICIENT OF VOUT OR VIN For
the ICL804S the temperature coefficient refers to the drift
with temperature of VOUT for a constant input current.
For the ICL8049 it is the temperature drift of the input
voltage required to hold a constant value of VOUT.
POWER SUPPL Y REJECTION RA TlO The ratio of the
voltage change in the linear axis of the transfer function
(VOUT for the ICLS048, VIN for the ICLS049) to the change
in the supply voltage, assuming that the log axis is held
constant.
WIDEBAND NOISE For the ICL804S, this is the noise
occurring at the output under the specified conditions. In the
case of the ICLS049, the noise is referred to the input.
SCALE FACTOR For the log amp, the scale factor (K) is
the voltage change at the output for a decade (i. e. 10:1)
change at the input. For the antilog amp, the scale factor is
the voltage change required at the input to cause a one
decade change at the output. See equations 9 and 10.

10----1
2NUII
10""

IREf

PIN 18 ON B04B)
( TO
TO PIN 3 ON 1041
AF030301

Figure 9

DEFINITION OF TERMS
In the definitions which follow, it will be noted that the
various error terms are referred to the output of the log amp,
and to the input of the antilog amp. The reason for this is
explained on the previous page.
DYNAMIC RANGE The dynamic range of the ICL8048
refers to the range of input voltages or currents over which
the device is guaranteed to operate. For the ICL8049 the
dynamic range refers to the range of output voltage over
which the device is guaranteed to operate.
ERROR, ABSOLUTE VALUE The absolute error is a
measure of the deviation from the theoretical transfer
function, after performing the offset and scale factor
adjustments as outlined, (ICLS04S) or (ICL8049). It is
expressed in mV and referred to the linear axis of the
transfer function plot. Thus, in the case of the ICL8048, it is
a measu,re of the deviation from the theoretical output
voltage for a given input current or voltage. For the ICL8049
it is a measure of the deviation from the theoretical input
voltage required to generate a specific output voltage.
The absolute error specification is guaranteed over the
dynamic range.

APPLICATION NOTES
For further applications assistance, see
A007 "The ICL8048/S049 Monolithic Log-Antilog Amplifi-

ers", by Ray Hendry

~9

Note: All typical values have been guaranteed by characterization and are not tested.

ia ICL8083
Power Transistor DriverlAmplifier

-

GENERAL DESCRIPTION

FEATURES

The ICLa063 is a. unique monolithic power transistor
driver and amplifier that allows construction of minimum
chip power amplifier systems. It includes built in safe
operating area circuitry, short circuit protection .and voltage
regulators, and i~ primarily intended for driving complementary output stages.
Designed to operate with all varieties of operational
amplifiers and other functions, two external power transistors, and a to 10 passive components, the ICLa063 is ideal
for use in such applications as linear and rotary actuator
drivers, stepper motor drivers, servo motor drivers, power
supplies, power DACs and electronically controlled orifices.
The ICLa063 takes the output levels (typically ± 11 V) from
an op amp and boosts them to ±30V to drive power
transistors, (e.g. 2N3055 (NPN) and 2N37a9 (PNP». The
outputs from the ICLa063 supply up to 100mA to the base
leads of the external power transistors.
The amplifier-driver contains internal positive and negative regulators, to power an op amp or other device; thus,
only ±30V supplies are needed for a complete power amp.

•
•

•
•
•
•

Converts ±12V Outputs From Op Amps and
Other Linear Devices to ± 30V.. Levels
When Used In Conjunction With General-Purpose
Op Amps and External Complementary Power
Transistors, System Can Deliver> SO Watts to
External Loads
Built-in &lfe Area Protection and Short-Circuit
Protection
Produces 2SmA Quiescent Current in Power
Output Stage
Built-In ± 13V Regulators to Power Op Amps or
Other External Functions
SOOkn Input Impedance With RBIAS 1Mn

=

ORDERING INFORMATION
PART NUMBER

TEMPERATURE
RANGE

ICL8063MJE

-55°C to + 125°C

CERDIP

ICL8063CJE

O°C to +70°C

CERDIP

ICL8063CPE

O°C to +70°C

PLASTIC DIP

PACKAGE

- VREGOUT

,
'5

INPUT
+VREGOUT

-ABIA!

2

FREQ. COMPo CAPAC.
PNP BASE DRIVE OUTPUT

5
•

'2 GND
11 NPN BASE DRIVE OUTPUT

7
•

,. CURRENT COMP. CAPAC.

- RSHORT CKT. PROT.
OUTPUT

•

+ RSHORT CKT. PROT.
CD018211

08019211

Figure 1: Functional Diagram

Figure 2: Pin Configuration

4-90
Note: All typical values have been guaranteed by qharacterizalion and are not tested.

.D~DIL

ICL8063

i

ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................................ ±3SV
Power Dissipation ......................................... SOOmW
Input Voltage (Note 1) ......................................±30V
Regulator Output Currents ................................ 10mA

Operating Temperature Range
ICLS063MJE ........................ -SS'C to + 12S'C
ICL8063CPE ............................. O·C to + 70'C
ICL8063CJE ............................. O'C to + 70'C
Storage Temperature Range ............ -6S'C to + 1S0'C
Lead Temperature (Soldering. 10sec) ................. 300·C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. ,These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods 'may affect device reliability.

ELECTRICAL CHARACTERISTICS

(TA = 2S'C; VSUPPLY = ±30V)
MINIMAX LIMITS

SYMBOL

CHARACTERISTIC

TEST CONDITIONS

O·C

-SS'C +2S·C + 12S·C
Max. Offset Voltage

See Figure 3

150

50

50

10H

Min. Positive Drive
Current

See Figure 4 '

50

50

50

loa

Max. Positive Output
Quiescent Current

See Figure 5

500

250

250

10l

Min. Negative Drive
Current

See Figure 4

25

25

25

10l

Max. Negative Output
Quiescent Current

See Figure 6

VREG

Regulator Output Voltages
Range

IREG

Regulator Output Current

(See Note 2)

ZIN

A.C. Input Impedance

See Figure 8

VSUPPlY

Power Supply Range

10

Power Supply
Quiescent Currents
Range of Voltage Gain

VOUT(MIN)

Minimum Output Swing

IBIAS

Input Bias' -Current

NOTES:

UNIT

ICL8063C

ICL8063M

Vos

AV

P

,

+2S'C +70·C
75

mV

40

mA

300

I1A

20

mA

500

250

250

±13.7
±1.2V

±13.7
±I.OV

±13.7
±1.5V

300

10

10

10

mA

400

,400
(Typ)

kG

±13.7
!I.OV

(Typ)

±13.7
±I.OV

±5 to ±35V

I1A
±13.7
±1.0 V

V

V

10

6

6

7

mA

6±2

6±2

6±2

8±2

VIV

VIN until VOUT flattens

±27

±27

±27

±27

V

See Figure 10

100

100

100

100

I1A

See Figure 9
VIN=8Vp-p

See Figure 9; Increase

1. For supply voltages less than ± 30V the absolute, maximum input voltage is equal ·to the supply voltage.
2. 'Care should be taken to ensure that maximum Power dissipation' is not' exCeeded.

4-91
Note: All typical values have been guaranteed by characterization and are not tested.

IIn~nlL

......

+3D¥

tllli

~--"tIOl n2, and Ra for optimum sensitivity. That means making
Ra "'I to minimize the voltage drop across Ra (the drop
wili b(;, i i.'lrnp x 1 ohm or 1 volt). If 1 amp/volt sensitivity is
d{;sirabIE) let R2 = R1 = 10kSlto minimize feedback current
'>fmr. Thl111 a ± 1V input voltage will produce a ± 1 amp
curr-;,mt through the motor.

n

Capacitors should be at least 50 volts working voltage

c,nd all msistors 1/2W, except for those valued at 0.4 ohms.

POI/,mr across Ra = I xV = 1 amp x 1 volt = 1 watt, so at
least a 2 watt value should be used. Use large heat sinks for
the 2N305G and 2N~791 power transistors. A Delta NC-641
()1' the equivalent is appropriate. Use a thermal compound

when mounting the transistor to the heat sink. (See InterSi!
lCH8510 data sheet for further information).

.....

.... '"

@ow

...
...

.".

GAn

~1ouT

@IW

NOW ' : ' "" (-) IbIRt x

Ii;
LC013201

Figure 17: Constant Current Motor Drive

Building A I-ow Cost 50 Watt per Channel
Audio Amplifier '
For about $20 per channel, it is possible to build a high
fidelity amplifier using the ICL8063 to drive 8 ohm speakers.

Note: Ail typical values have been guaranteed by characterization and are' not tested.

ICL8063
'A channel is defined here as all amplification between
turntable or tape output and power output. (Figure 18)
The input 741 stage is a preamplifier with R.IAA.
equalization for records. Following the first 741 stage is a
10kU control pot, whose wiper arm feeds into the power
amplifier stage consisting of a second 741, the ICL8063 and
the power transistors. To achieve good listening results,
selection of proper resistance values in the power amplifier
stage is important. Best listening is to be found at a gain
value of 6 [(5kU + 1kUI 1kU = 6)]. 3 is a practical minimum, since the first stage 741 preamp puts out only ±10
volt maximum signals, and if maximum power is necessary
this value must be multiplied by 3 to get ±30 volt levels at
the output of the power amp stage.

Each channel delivers about 56 volts p-p across an 8
ohm speaker and this converts to 50 watts RMS power.
This is derived as follows:
Vrms2
56Vp_p
Power = - - - , Vrms = - - 8 ohms
2.82

2

= 20V, (20V) = 400V

2

400V2
Power = - - - = 50 watts RMS Power.
8 ohms
Distortion will be < 0.1 % up to about 100Hz, and then it
increases as the frequency increases, reaching about 1 %
at 20kHz.
The ganged switch at the input is for either disc playing or
FM, either from an FM tuner or a tape amplifier. Assuming
DC coupling on the outputs, there is no need for a DC
reference to ground (resistor) for FM position. To clear the
signal in the FM pOSition, place a 51 kUresistor to ground as
shown in Figure 18 (from FM input position to ground)_

~

"~J
.......

"'".........-.
_J
90007601

Figure 18: Hi·Fi Amplifier

4--97

Note: All typical values have been guaranteed by characterization and are not tested.

I...

ICL8063'

+'II---+----PIE--''"""~--__I

>

.1

'C

~r---~--~--~~-__i

\

-I

,. ,.. ,.
i

1-(111)

OP032601

EOUT

050'.501

Figure 19: Typical Performance Curve of - - vs. Frequency· For Typical Circuit Shown
VIN

-..

,

'"

\

..0----'-----.

\
~

\
0P002701

..

--

~-~~-~--~~_+----_+~4

050' ....

Figure 20: Typical Performance Curve of Input Impedance Versus Frequency
for Typical Circuit Shown
Note: I"tarsil offers a hybrid power amplifier similar to that shown in Figure 11. See ICH8510/8520/8530 data

Note: All typical values have been guaranteed by characterization and are not tested.

s~t

for details.

LH2108/LH2308
Dual Super-Beta Operational
Amplifier
GENERAL DESCRIPTION

FEATURES

The lH210BAllH230BA and lH210B/lH230B series of
dual operational amplifiers consist of two lM10BA or
lM10B type op amps in a single hermetic package. Featuring all the same performance characteristics of the single
device, these duals also offer closer thermal tracking, lower
weight, and reduced insertion cost.

•
•
•
•
•

Low Offset Current - 50pA
Low Offset Voltage-O.7mV
Low Offset Voltage
LH2108A: O.3mV
LH2108: O.7mV
Wide Input Voltage Range-±15V
Wide Operating Supply Range - ±3V to ±20V

ORDERING INFORMATION
PART NUMBER

TEMPERATURE RANGE

LH210BD

-55·C to + 125·C

LH2108AD

PACKAGE

-55·C to + 125·C

16-PIN

LH230BD

O·C to +70·C

CERAMIC

LH230BAD

O·C to +70·C

INV
INPUT

4

14
2
16

NON.INV

5

INPUT

INV
INPUT

12

v~

V+
BALANCE
OUTPUT
COMPENSATION

OUTCOMP,

OUTPUT

SAL/COMP,

BALiCOMPENSATION

-IN.

V·

TIN.

-OUT,
N/C

V·

BALANCE
OUTPUT
COMPENSATION

BAI.o

OUTPUT
OUT,
NON-INV
INPUT

'3

BAL/COMPENSATION
V+
CD014401

Figure 1: Functional Diagram

(outline dwg DE)
COO1451t

Figure 2: Pin Configuration

4-99
Note: All typical values have been guaranteed by characterization and are not tested.

II

I

!::!.
I
;;
3

LH2108/LH~308
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range·
LH21 08A1LH21 08 .....•........... -55°C to + 125°C
LH2308A1LH2408 ...................... O°C to + 70°C
Storage Temperature Range ............ -65°C to + 150°C
Lead Temperature (Soldering. 10sec) ................. 300.oC

Supply Voltage ................................................±20V
Power Dissipation (Note 1) .•..........................• 500mW
Differential Input Current (Note 2) .................... ± 1OmA
Input Voltage (Note 3) ................... : .................. ± 15V
Output Short Circuit Duration ..................... Continuous

ELECTRICAL CHARACTERISTICS
(LH2108/LH2308)

(See Note 4)

LIMITS
PARAMETER

TEST CONDITIONS

UNIT
LH2108

LH2308

Input Offset Voltage

TA = 2SoC

2.0

7.S

Input Offset Current

TA = 2SoC

0.2

t.O

Input Bias Current

TA - 2SoC

2.0

7.0

mV Max
nA Max

Input Resistance (Note S)

TA = 2SoC

30

10

Mn Min

Supply Current

TA = 2SoC

0.6

0.8

rnA Max

Large Signal Voltage Gain

TA = 25°C VS·±ISV
VOUT-±10V, RL~10kn

50

2S

V/mV Min

Input Offset Voltage

3.0

10

Average Temperature Coefficient
of Input Offset Voltage (Note 8)

IS

30

Input Offset Current

0.4

I.S

nA Max

Average Temperature Coefficient
of Input Offset Current (Note 6)

2.5

10

pAloC Max

Input Bias Current

mV Max

pvrc

Max

3.0

10

nA Max

Supply Current

TA=+125°C

0.4

-

rnA Max

Large Signal Voltege Gain

Vs=±ISV, VQUT=±10V
RL~ 10kn

2S

15

VlmV Min

Output Voltage Swing

Vs=±15V, RL=10kn

±13

±13

Input Voltage Range

Vs = ±15V

±13.5

±14

Common Mode Rejection Ratio

VS-±15V, VCM-±13.5V

85

80

Supply Voltage Rejection Ratio

±SV to ±20V

80

80

ELECTRICAL CHARACTERISTICS -

V Min
dB Min

LH2108/LH2308

Input Offset Voltage

TA = 2SoC

O.S

0.5

mV Max

Input Offset Current

TA = 2SoC

0.2

nA Max

Input Bias Current

2.0

Input Resistance

TA - 25°C
TA - 2SoC

'.0
7.0

30

10

Mn Min

Supply Current

TA = 25°C

0.6

0.8

rnA Max

Large Signal Voltage Gain

TA=2SoC VS=±ISV
Your = ± 10V, RL ~ 10kn

80

80

VlmV Min

1.0

0.73

mV Max

5

S

pvrc Max

Input Offset Current

0.4

I.S

nA Max

Average Temperature Coefficient
of Input Offset Current (Note 6)

2.5

10

pArc Max

Input Offset Voltage
Average Temperature Coefficient
of Input Offset Voltage (Note 6)

Input Bias Current

3.0

10

nA Max

Supply Current

TA= + 12SoC

0.4

-

rnA Max

Large Signal Voltage Gain

Vs = ±15V, VOUT= ±10V
RL~ 10kn

40

60

V/mV Min

Output Voltage Swing

VS=±15V, RL=10kn

±13

±13

Input Voltage Range

Vs = ±ISV

±13.S

±14

4-100
Nota: All typical values have been guarantaed by characterization and are not tested:

V Min

LH2108/LH2308
ELECTRICAL CHARACTERISTICS (CONT.)
LIMITS
PARAMETER

TEST CONDITIONS

UNIT
LH2108

LH2308

96

96

Common Mode Rejection Ratio
Supply Voltage Rejection Ratio
NOTES:

96
150·C. and that of the LH23081A

dB Min
96
85·C. The Ihermal resistance of the

1. The maximum lunctlon temperature of the LH21 081 A IS
IS
packages is 100·C C/W, junction to ambient.
2. The inputs are shunted with back-to-back diodes for overvoltage protection. Therefore, excessive current will flow if a differential input
voltage in excess of 1V is applied between the inputs unless some lim~ing resistance is used.
3. For supply voltages less than ± 15V, the absolute maximum input voltage is equal to the supply Voltage.
4. These specifications apply for ±5V:S Vs S ±20V and - 55·C S TA S 125·C, unless otherwise specified, and the LH2308A1LH2308 for
±5V:S Vs S 15V and O·C:S TA:S 70·C.
5. Input resistance is guaranteed by Input Bias Current test.
6. For DeSign only, not 100% tested.

STANDARD
COMPENSATION CIRCUIT

ALTERNATE"
FREQUENCY COMPENSATION

Your

FEEDFORWARD
COMPENSATION

VOUT

YOUT
Ra

+YI

Cf"~2

,+
CO-30pF
Cf

R3

-Improves rejec:ion
of power supply
noire by • factor
often.

C2 =

SSOO6501

88006601 .

Figure 3: Auxiliary Circuit

4-101
Nota: All typical vsiues have been guaranteed by characterization and are not tested.

-=-

2"~ R2

fo=3MHz
SSOO8701

I
~

c

i!

D~D[6

LM108/A, LM308/A
Super-Beta Operational Amplifier
GENERAL DESCRIPTION

FEATURES

These differential input, precision amplifiers provide low
input currents and offset voltages comparable to FET and
chopper stabilized amplifiers. They feature low power
consl,lmption over,a supply voltage range of > 2V to ±20V.
The amplifiers may be frequency compensated with a single
external capacitor. The LM108A and LM308A are high
performance selections from the 108/308 amplifier family.

•
•
•
•
•
•

Input Bias Current - 2nA Max to 7nA Max
Input Offset Current - O.2nA Max to 1nA Max
Input Offset VOltage - O.SmV Max to 7.SmV Max
1::Nos/AT-SIl,Vrc to 30llVrC
Alosl AT-.2.5pArC to 10pArC
Pin for Pin Replacement for 101A/301A

ORDERING INFORMATION
PART
NUMBER

TO-99
CAN

8 PIN
MINIDIP

14 PIN
CERDIP

10 PIN
FLATPAK

LM108A
LM308A

LM108AH*
LM308AH

LM308AN

LM108AJ
LM308AJ

LM108AF
LM308AF

LM108
LM308

LM108H*
LM308H

LM308N

LM108J
LM308J

LM108F
LM308F

-

** DICE

LM308/D

"If 883C processing is desired add 1883C to part number.
""Parametric MinIMax Limits guaranteed at 25°C only for DICE orders.

FREa COMPA8FREa COMP'B
-IN

y+

+IN

OUT

v-

INVERTING INPUT

,.

NON 1~~~TlNG

5

NC

(outline dwg PAl

TOP VIEW

COO16101

(outline dwg JD)
aJ01S301

NC

COMP

GUARD

COMP

-IN

v'

+IN

OUT

y-

GUARD
TOP VIEW

(outline dwg FB-')

(outline dwg TV)

c0016401
, c0016201

Figure 1: Pin Configurations

4-102
NOte: All typical values have been guaranteed by characterization and are not tested.

302030-002

1I0~OIL

LM108/A, LM308/A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
10B, 10BA ............................................. ±20V
30B, 30BA ............................................. ±1BV
Internal Power Dissipation (Note 1)
Metal CAn (TO-99) .............................. SOOmW
DiP ••.. ;· .............................................. SOOmW
Differential Input Current (Note 2) .................... ±10mA

Input Voltage (Note 3) ...................................... ±1SV
Output Short-Circuit Duration ......................... Indefinite ,
Operating Temperature Range
W
10B, 10BA ........................... -SS·C to + 12S·C
30BAt...... ·R····· ................. ·6..S~C·Ct to++17S0
Storage30TB,empera
0:C
C ';;:
ure ange ............ 0
,
Lead Temperature (Soldering,10sec) ...... , .......... 300·C

i

ELECTRICAL CHARACTERISTICS (TA =2S·C unless otherwise specified) (Note 4)
PARAMETER

TEST CONDITIONS

308
MAX

Input Offset Voltage

2.0

Input Offset Current

0.2

Input Bias Current

1.5

Input Resistance

Note 5
VS-±20V
VS=±15V

large Signal
Voltage Gain

Vs - ±15V, Vour= ±10V
RL> 10kn

10

108

308A

.TVP

Supply Current

MIN

MIN

TVP

MAX

7.5

0.3

0.5

1.0

0.2

7

1.5

1.0
7

10

40

40

MIN

30

TYP
0.7

25

0.8

0.3
80

300

108A
MAX

MIN

UNIT

TVP

MAX

2.0

0.3

0.5

mV

0.05

0.2

0.05

0.2

0.8

2.0

0.8

2.0

nA
nA
Mn
mA
mA

70
0.3

0.3

30

70
0.3

0.6

0.6

0.8

300

50

80

300

VlmV

300

THE FOLLOWING SPECIFICATIONS APPLY OVER THE OPERATING TEMPERATURE RANGES
Input Offset Voltage

10

0.73

3.0

1.0

Input Offset Current

1.5

.1.5

0.4

0.4

nA

1.0

5.0

p'vrc

0.5

2.5

pArC

Average Temperature
CoefficiEintof Input
Offset Voltage

Note 6

Average temperature
Coefficient of Input
Offset Current

Note 6

,

8.0

30

1.0

5.0

3.0

2

10

·2.0

10

0.5

Input Bias Current
Large Signal
Voltage Gain

10
Vs = ±15V, Vour= ±10V
RL ~ 10kn

15

2.5
3.0

10

15

25

60

Vs = ±15V
V5=±15V
VCM=±13.5V

80

100

96

110

85

100

96

110

dB

Supply Voltage
Rejection Ratio

±5V to ±20V

80

96

96

110

80

96

96

110

dB

±13

±14

±13

±14

±13

±14

±13

±14

VS=±15V, RL=10kn
TA = + 125·C, Vs = ±20V

±13.5

nA
V/mV

Input Voltage Range

Supply Current

±13.5

3.0
40

mV

Common Mode
Rejection Ratio

Output Voltage
Swing

±13.5

..~
,.
,

±13.5

0.15

0.4

V

0.15 "0.4

V
mA

NOTES: 1. Derate Metal Can package at 6.8 mWrc for operation at ambient temperatures above 75·C and the Dual In-Line package at 9mWI
·C 'for operation at ambient temperatures above 95°C.
2. The inputs are shunted with back-to-back diodes for over-voltage protection. Therefore, excessive current will flow if a differential input
voltage in excess of tV is applied between the inputs unless some limiting resistance is used.
. 3. For' supply voltages less than ± 15V, the maximum input voltage is equal to the supply voltage.
4. Unless otherwise specified, these specHications apply for supply voltages from + 5V to ± 20V for the 108, and 100A and + 5V to
± 15V for the 30B and 30BA.
5.. Input· resistance is guaranteed by Input Bias Current test.
6. For' Design only, not 100% tested. .

4--103
Note: All typical values have been guaranteed by characterization and are not tested.

!~ LM108/A,LM308/A
.

!

INPUT CURRENTS

C

i...

!j,

.

TYPICAL PERFORMANCE CHARACTERISTICS
MAXIMUM DRIFT ERROR

2.0

, lk

1. 5

i

t",.....,

N

1.0

I08A/l08

~

O. 5

a"

r--- t-...

-

"';>

O.2S

r-I108
308

t---,=-

I-I~

w
~ 10

....,...."

-

o"

""

r-... 308(308A OFFSET

... 0.20
~
a>;0.15

ii2
Q

.108A/\08

0.10

OtSlT

-...J.~

o

,.-

I I

J/JALIAL

308A

108A

J;

~ 108/108A,

1.0
lOOk

-5S'C <

~. < 12S'C

O·C":T.< 10'C

1M

10M

INPUT RESISTANCE

TEMPERATURE ('CI

,.-

~

i7

FI

.... 308/308A,

··55 -35 -15 5 2S 45 65.85 lQ5 12S

MAXIMUM OFFSET ERROR

. 100M
0P022201

0P022001

100M

1M
10M
INPUT RESISTANCE

1m·

1m
0P022101

POWER SUPPLY REJECTION

INPUT NOISE VOLTAGE

120

·1000

jloo

~400
:;
.:

280

0

~

...
;;:

OPEN LOOP
VOLTAGE GAIN

..,80

Rs ·1M

~'00

~

40

"...>'
t 20
a 0

ia>;

-20
100

lk

10k

lOOk

1M

10M

Rs' lOOk
Rs'O

40

10
·10

I
100

lk

10k

lOOk

10

FREOUENCY (Hz!

FREQUENCY (Hzl
0P022301

OUTPUT SWING

20

15

SUPPLY VOLTAGEltVI
OP022511

OP022411

OPEN LOOP
FREQUENCY RESPONSE

SUPPLY CURRENT

15
VS' t15V

I

... ~~~ ~

\

T.· 12S'C.

" " "
"
"
f-- --f"~pF

d-

T~'crCi

o

I I I It

o

2

4

6

.

C.'30pF~ I{-

L'::T•• 70'C
T.r. ~'C II
I

T... • -55'C

110

C.'IOOpF-

:+,c..

GAIN
PHASE ___

8

01'022601

"10:

f-- ~c.. :00 pF

-

OUTPUT CURRENT ('mAI

"10:

1

SUPPLY VOLTAGE (tVl
OP022701

Note: All typical values have been guaranteed by characterization and are not tested.

10 100

lk

....
;r-

30 pFFe!!

o

10k lOOk 1M 10M

FREOUENCY IHzI

LM108/A, LM308/A
TYPICAL PERFORMANCE CHARACTERISTICS (CONT.)
CLOSED LOOP
OUTPUT IMPEDANCE
1~ r--r--r--r--~-'=-~

...§,~

r--H~~~--~-4--~

~
~10' r-~-'\r-'\-b~+--4--~
~

~ 1~ t--t---li7'
~ 10"

10

16
To'

'"z

...~

8
C," 3pF

1\

C.-30~
i-I it

lOUT· ±1 mA

10"

"'-......__..........__V;.::S.;.·_,';..;;S.;.V--,
10

100

lk

10k

lOOk

1M

10M

o
lk

""
10k

r-

'1

r-I-\1H-+::.:r',,{-

1

r-HH-t-++--i"'-'U

-2 r-HIH-t-+-,h:~j-.--+--

~ I=t$!=t=~t~t;~t;
~

1'-0.
lOOk

r-r-.r-T--.--.--.-,--

8 I-+-HH......---·+_·+
6 I-+-HH.......,-l-·_ ..l---+·
4 I - r H H......---{-·---

Vs" :!:15V

~ 4

I----H<---li----+--

25'(:

~ 12

~

:::>

l!:

VOLTAGE FO!JJ(;ii"i!:·.:, ~
PULSE RESP(Wl:",;:

LARGE SIGNAL
FREQUENCY RESPONSE

-10

I-+-HH......-+-:
L....L-&....JL....I~_

1M

FREQUENCY IHzl

FREQUENCYIHzI

0P02S00l

0P022901

GUARDING
Extra care must be taken in the assembly of printed
circuit boards to take full advantage of the low input
currents of the 108 amplifier. Boards must be thoroughly
cleaned with TCE or alcohol and blown dry with compressed air. After cleaning, the boards should be coated
with epoxy or silicone rubber to prevent contamination.
Even with properly cleaned and coated boards, leakage
currents may cause trouble at 125·C, particularly since the
input pins are adjacent to pins that are at supply potentials.
This leakage can be significantly reduced by using guarding
to lower the voltage difference between the inputs and
adjacent metal runs. Input guarding of the 8-lead TO-99
package is accomplished by using a 10-lead pin circle, with
the leads of the device formed so that the holes adjacent to
the inputs are empty when it is inserted in the board. The
guard, which is a conductive ring surrounding the inputs, is
connected to a low impedance point that is at approximately the same voltage at the inputs. Leakage currents from
high-voltage pins are then absorbed by the guard.
The pin configuration of the dual in~line package is
designed to facilitate guarding, since the pins adjacent to
the inputs are not used (this is different from the standard
741 and 101A pin configuration).

.,
INVl~~~~ _IVAII\'~-I

.I

IOOpF

lC(J<11:;0!

Figure 3: Frequency Compensat9()'ls',;

e~r;'~"iG'~

ALTERNATE CIRCUIT IMPROVES FiE,i'l,",:-;1l1~/;:!
POWER SUPPLY NOISE BY A FACTOi') Oil' Y',',.;,\

A'

Co

c,

lOpF
lC02'4OI

Figure 2: Frequency Compensation Circuit
STANDARD CIRCUIT

4-105
Note: All typical values have been guarenteed by cheracterization and are not tested.

=Video
NE/SE592
Amplifier
111

(I)

I

GENERAL DESCRIPTION

FEATURES

The NE/SE592 is a monolithic, two-stage, differential
output, wideband video amplifier. It offers fixed gains of 100
and 400 without eXternal components and adjustable gains
from 0 to 400 with one external resistor. The input stage has
been designed so that with the addition of a few external
reactive elements between the gain select terminals, the
circuit can function as a high pass, low pass, or band pass
filter. This feature makes the circuit ideal for use as a video
or pulse amplifier in communications, magnetic memories,
display, video recorder systems" and floppy disc head
amplifiers. The NE/SE592 is a pin-for-pin replacement for
the jJA733 in most applications.

....

2.4k

•
•
•
.•
•

120MHz Bandwidth
Adjustable Gains From 0 to 400
Adjustable Pass Band
No Frequency Compensation Required
Wave Shaping With' Mlnlinal· External
Components

ORDERING INFORMATION
BASIC
PART
NUMBER

PACKAGE
TEMP
RANGE

SES92

-SS·C 10
+ 12S·C

NES92

O·C 10
+70·C

14-PIN
PLASTIC

14-PIN
CERDIP

la-PIN
To-l00

8-PIN
MINI DIP

-

SES92F

SES92H

-

NES92N

NES92F

NES92H

NES92N-8

..

,

t---+--1-t--+---.i'""""ovt-+-<>OUTPUT1
'----+---"JIIIo-j--+--<>OUTPUT 2

1IIPUT'
G ••

...
BDOO6OO1

Figure 1: Functional Diagram (Resistor Values Nominal Only)

14-Pln DIP Package
(JD, PO Package)

10-Pln To-100 Package
(H Package)

8-Pln DIP Package
(N-8 Package)

Qu,GAIN
SELECT

INPUT 1 1
G'A GAIN SELECT 2

7 G'B GAIN SELECT

Goa"'".
SELECT

OUTPUll 4

5 OUTPUT2

y-

TOP VIEW
COO14001

TOP VIEW

CD014301
c001~101

Note: Pin 5 connected to case.

Figure 2: Pin Configurations

4-106
Note: All typical values have been guaranteed by characterization and are not tested.

NE/SE592
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................................. ±8V
Differential Input Voltage .................................... ±5V
Common-Mode Input Voltage .............................. ±6V
Output Current ............................................... 10mA

Operating Temperature Range
SE592 ................................ -55·C to +125·C
NE592 ..................................... O·C to + 70·C
Storage Temperature Range ............ -65·C to + 150 c C
Power Dissipation ......................................... 500mW
Lead Temperature (Soldering, 10sec) ................. 300·C

Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions. lor extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
+ 25°C, VSUPPLY = ±6V, VCM = 0 unless otherwise specified. Vs = ±6.0V

TA =

NE592
SYMBOL.

PARAMETER
Differential Voltage Gain
Gain 1 (Note 1)
Gain 2 (Note 2)

AVOL

BW

SE592

TEST CONDITIONS

RL = 2kU, VOUT = 3Vp-p

UNIT
MIN

TYP

MAX

MIN

TYP

MAX

250
80

400
100

600
120

300
90

400
100

500
'110

Bandwidth
Gain 1 (Note 1)
Gain 2 (Note 2)

40
90

40
90

MHz

Rise Time

t,

Gain 1 (Note 1)
Gain 2 (Note 2) (Note 4)
Propagation Delay
Gain 1 (Note 1)
Gain' 2 (Note 2) (Note 4)

td

VOUT= 1Vp-p

VOUT= lVp-p

Input Resistance
Gain 1 (Note 1)
Gain 2 (Note 2)

RIN

CIN

input Capacitance (Note 2) (Note 4)

los

Input Offset Currant

IBIAS

Input Bias Currant

en

Input Noise Voltage

II.VIN

Input Voltage Range

I CMRR

10
Gain 2

10.5
4.5

12

10.5
4.5

10

7.5
6.0

10

7.5
6.0

10

4.0
30

20

2.0

BW= 1kHz' to 10MHz

3.0

9.0

30

9.0

20

12

±1.0
60

86
60

Supply Voltage Rejection Ratio
Gain 2 (Note 2)

AVs = ±O.SV

50

70

50

70

Voo

Output Offset Voltage
Gain 2 (Note 2)

RL =

00

VOCM

Output Common-Mode Voltage

RL =

00

VO(DIFF)

Differential Output Voltage Swing

RL =2kU

Ro
1+

Output Resistance

1.
2.
3.
4.

0.35

0.75

2.4

2.9

3.4

3.0

4.0

20
=

00

Gain select pins G1A and G1B connected together.
Gain select pins G2A and G2B connected together.
Recommended supply voltage = ± 6V
For design reference only, not 100% tested.

4-107
Note: All typical values have baen guaranteed by characterization and are not tested.

18

-dB

0.35

0.75

2.4

2.9

3.4

3.0

4.0
18

V
dB

V
V
V

20
24

iJA
iJA
jJ.V rms

12
±1.0

RL

pF

2.0
0.4

86
60

Power Supply Current (Note 3)

kU

5.0

60

PSRR

ns

0.4

VCM ±1V, f < 100kHz
VCM ~ 1V, f = 5MHz

I

ns

4.0
30

Common-Mode Rejection Ratio
Gain 2 (Note 2)
Gain 2 (Note 2)

NOTES:

VIV

U
24

rnA

.n~nll

:: NE/SE592

i.

TYPICAL APPLICATIONS

III

z

Filter Networks
SCHEMATIC

FILTER

Vo (S) TRANSFER
VI
FUNCTION

TYPE
LOW PASS

1.4x104 [__
1_]
L
$ + R/L

HIGH PASS

1.4X104 [
S
]
$+ 1/RC
R

BAND PASS

1.4x104 [
S
]
- - L - S2+R/L s+1/LC

AF027501

V

~(S)
Vi

:!!

1.4x104
Z(s)

+ 2re

1.4x104

:!!---

Z(s)

+ 32

BAND REJECT

NOTE;: In the networks above, the R value used is assumed to include the
internal 2re of approximately 32n.

Figure 3: Basic Configuration

+5V

Q

i

___ !! ___ -.J

AMPUTUDE:
FREQuENCY:

I
READ HEAD

- I

DIFFERENTIATOR/AMPUFIER

"='
ZERO CROSSING DETECTOR
AF027611

Figure 4: Disc/Tape Modulated Readback Systems

4-108
Note: All typical values have been guaranteed by characterization and are not tested.

NE/SE592
For frequency f1

< < 1/21r(32)C

dVj
Vo a.1.4x104C d1

AF027101

Figure 5: Differentiation with High Common
Noise Rejection

4-109

Note: All typical values have been guaranteed by characterization and are not tested.

Section 5

Special Analog
Functions

AD590
2-Wire Current Output
Temperature Transducer
GENERAL DESCRIPTION

FEATURES

The AD590. is an integrated-circuit temperature transducer which produces an output current proportional to absolute temperature. The device acts as a high impedance
constant current regulator, passing lilA/oK for supply
voltages between + 4V and + 30.V. Laser trimming of the
chip's thin film resistors is used to calibrate the device to
298.21lA output at 298.2°K (+ 25°C).
The AD590. should be used in any temperature-sensing
application between -55°C and + l50.°C (O.°C and 70'°C for
TO-92) in which conventional electrical temperature sensors are currently employed. The inherent low cost of a
monolithic integrated circuit combined with the elimination
of support circuitry makes the AD590. an attractive alternative for many temperature measurement situations. linearization circuitry, precision voltage amplifiers, resistancemeasuring circuitry and cOld-junction compensation are not
needed in applying the AD590.. In the simplest application, a
resistor, a power source and any voltmeter can be used to .
measure temperature.
In addition to temperature measurement, applications
include temperature compensation or correction of discrete
components, and biasing proportional to absolute temperature. The AD590. is available in chip form making it suitable
for hybrid circuits and fast temperature measurements in
protected environments.
The AD590. is particularly useful in remote sensing
applications. The device is insensitive to voltage drops over
long lines due to its high-impedance current output. Any
well-insulated twisted pair is sufficient for operation hundreds of feet from the receiving circuitry. The output
characteristics also make the AD590. easy to multiplex: the
current can be switched by a CMOS multiplexer or the
supply voltage can be switched by a logic gate output.

•
•
•
•

Linear Current Output: 1pArK
Wide Range: -55°C to + 150°C
Two-Terminal Device: Voltage In/Current Out
Laser Trimmed to to.5°C Calibration Accuracy
(AD590M)
Excellent Linearity: to.5°C Over Full Range
(AD590M)
Wide Power Supply Range: + 4V .to + 30V
Sensor Isolation From Case
Low Cost

•
•
•
•

ORDERING INFORMATION
PART NUMBER/PACKAGE
NON-LINEARITY
(OC)

TO-52
PACKAGE

TO-92
PACKAGE

±3.0
±1.5
±O.8
±O.4
±O.3

AD5901H
AD590JH
AD590KH
AD590LH
AD590MH

AD590lZR
AD590JZR

TEMPERATURE
RANGE

-55°C to
+ 150°C

O,°C to
+ 70°C

DICE"

AD590/D

DICE

··Parameter MiniMax Limits guaranteed at 25°C only lor DICE ·orders.

CASE

(outline dwg TO·52)

+

SUBSTRATE
(LEAVE FLOATING)

(outline dwg TO·92)
PC00421 I
05016601

Figure 1: Functional Diagram

Figure 2: Pin Configurations

5--1
Note: All typical values have been guaranteed by characterization and are not tested.

30.0.10.6-00.2

!

ADS,90

.~

ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)
Forward Voltage (v+ to V-) "."""." ....... ,, ....... +44V
Reverse Voltage (v+ to V-),,""""""""""""" -20V
Breakdown Voltage (Case to V+ or V-) """"".±200V
Storage Temperature Range """",," -65°C to + 150°C

Rated Performance Temperature Range
TO-92 """",,",,",,",,",,"",,",,. O°C to + 70°C
TO-52 "" ........ """"" ........ " .,.55°C to+ 15QoC
Lead Temperature (Soldering, 10sec) ",,",,""" + 300°C

Stresses above thoss listed under" Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the 

298.2

a:
a:

u

...::>
......
::>
0

218

1/

/

L

/

21SOK 298.2"K 42aoK
( - 55·C) ( + 2S'C) ( +15O"C)

TEMPERATURE
OP016201

Figure 8: Simple connection. Output is
proportional to absolute temperature.

5-6
Note: All typical values have been guaranteed by characterization and are, not tested.

AD590
TYPICAL APPLICATIONS

y+

+15V

(ADDITIONAL
SENSORSt

05017101

Figure 10: Average-temperature sensing
scheme. The sum of the AD590
currents appears across R, which
is chosen by the formula:
10kn

DS01700i

Figure 9: Lowest-temperature sensing
scheme. Available current is that of the
"coldest" sensor.

R=

n

n being the number of sensors.

+15V

-,
I

J ~~~~~T
J

.J

A

C

0.1%

[I

':"
80005701

Figure 11: Single-setpoint temperature controlier. The AD590 produces a temperature-dependent
voltage across R (C is for filtering noise). Setting R2 produces a scale-zero voltage. For the Celsius
scale, make R 1kn and VZERO 0.273 volts. For Fahrenheit, R 1.8kn and VZERO 0.460 volts.

=

=

=

5-7
Note: All typical values have been guaranteed by characterization and are not tested.

=

~.

10

AD590

ICII

C

ROW

COLUMN
SELECT

+15V

SEl.ECT

,....-,

ENABLE

R
(OPTtONALI

• 0
5 ,

6 2
IH6108
8-CHANNEi.

-f-:~~~~~~~~~~~t-~~~~~7 3

MUX

'2 •

"

5

'0 6

A058O(&I1
,0Idl
0.1%

.

!

"OUT
I

80005901

Figure 12: Multiplexing sensors. If shorted sensors are possible, a series resistor in series with the D
line will limit the current (shown as R, above: only one is needed). A six-bit digital word will select
one of 64 sensors.

.-----.----------------o+.w
11<0
ZERCSET

IOmV/"C

118kO

101<0
0.'%

1000

201<0
FUlL·SCALE
ADJUST

~
.01<0 2.13.5V
.,..

_I

LCOO76Oi

Figure 13: Centigrade thermometer (O°C-100°C). the ultra-low bias current of the ICL7611 allows
the use of large-value gain-resistors, keeping meter-current error under 1/2%, and therefore saving
the expense of an extra meter-driving amplifier.

Note: All typical values have been guaranteed by characterization and are not tested.

AD590

Y+

SOkIl~+_Vlr-+--""'"

(8Yminl

Y-

LC007701

Figure 14: Differential thermometer. The 50kn pot trims offsets in the devices whether internal or
external, so it can be used to set the size· of the difference interval. This also makes it useful for
liquid-level detection (where there will be a measurable temperature difference).
Y+

r: ----------,
1"A/OK

I

L:

+-__-r_ _- ._ _ _

I
I SEEBECK

+-<>-I..:::C::::O~EF:.::F~IC~IENT

I

=4O,.v/oK

YI=
10.98mY

TYPEK

I

+

Y+
+
YoUT

I

RI
4521!1

Y2=10.98 40.211

j
'::"

'::"
05017201

Figure 15: Cold-junction compensation for type K th~mocouple. The reference junction(s) should
be in close thermal contact with the AD590 case. V must be at least 4V, while ICL8069 current
should be set at 1mA - 2mA. Calibration does not require shorting or removal of the thermocouple:
set R1 for V2 = 10.98mV.lf very precise measurements are needed, adjust R2 to the exact Seebeck
coefficient for the thermocouple used (measured or from table) note V1, and set R1 to buck out this
voltage (i.e., set V2 V1). For other thermocouple types, adjust values to the appropriate Seebeck
coefficient.

=

sao,A

-

:rt:J==xx:)C)(

x

+

~-r~~~tLCOO7801

Figure 16: Simplest thermometer. Meter displays current output directly in degrees Kelvin. Using the
AD590M, sensor output is within ±1.7 degrees over the entire range, and less than ±1 degree over
the greater part of it.

5-9
Note: All typical values have been guaranteed by characterization and are not tested.

i

AD590,'

a

cc
I of
I °C

v+

A,
A.

L,...--I--,
AEFHI

5

E+-- AEF LO

L

9,00 4,02 2.0 12.4 10.0

0

5.00 4.02 2.0 5.11 5.0 11.8

Rn = 28kn nominal

n=l
All values in kn
A

A.
ICL1106

II< ~_INHI

W
/,:::1=1
.B
~
f--'

The ICL71 06 has a VIN span of ±2.0V. and a VCM rE\nge of (V"
-0,5) Volts to (V- + 1) Volts; R is scaled to bring ,each range
within VCM while not exceeding VIN- VREF for both scales is
500mV."Maximum reading on the Celsius range is 199.9°C. limited
by the (short-term) maximum allowable sensor temperature.
Maximum reading on the Fahrenheit range is 199.9°F (93.3°C).
limited by the number of display digits. See note next page.

-COMMON
+-----fINLO

yAF027801

Figure 17: Basic digital thermometer, Celsius and Fahrenheit scales

y+

1.5kO
REF HI
2.2Il1O

AEFLO

i5kIl
SCALE
ADJ
1i5k1l

,_

ICL1106

307

COM
IN HI

, INLO

+
A05IO

yLCOO7901

Figure 18: Basic digital thermometer, Kelvin scale. The Kelvin scale version reads from 0 to'1999°K
theoretically, and from 223°K to 473°K actually. The 2.26kn resistor brings the input within the
ICL7106 VCM range: 2 general-purpose silicon diodes or an LED may be substituted.

5-10
Note: All typical values have been guaranteed by characterization and are not tested.

AD590
y.

7.5kll

ICUOlll

1.235V

SCALE REF
}DJ

HI·

REFLD

1kQ,O.1%

IClnD8

'5kll

21.'' '

'---JWHH--lCOM
IN HI
t--------IINLO

y-

lCOO8OO1

Figure 19: Basic digital thermometer, Kelvin scale with zero adjust. This circuit allows "zero
adjustment" as well as slope adjustment. The ICL8069 brings the input within the common-mode
range, while the 5kn pots trim any offset at 218°K (-55°C), and set the scale factor.
Note on Figure 17, Figure 18 and Figure 19: Since all 3
scales have narrow VIN spans, some optimization of
ICL7106 components can be made to lower noise and
preserve CMR. The table below shows the suggested
values. Similar scaling can be used with the ICL7126/36.
SCALE

VIN RANGE (V)

RIN"rtkn)

CAZ(IlFj

K
C
F

0.223 to 0.473
-0.25 to + 1.0
-0.29 to + 0.996

220
220
220

0.47
0.1
0.1

For all:
Cose = 100pF
Rose = 100kn

CREF = O.1p.F
CINT = O.221lF

5-11
Note: All typical values have been guaranteed by characterization and are not tested.

!~~~!~~age Converter

.D~UIl

GENERAL DESCRIPTION

FEATURES

The Intersil ICL7660 is a monolithic CMOS power supply'
circuit which offers unique performance advantages over'
previously available devices. The ICL7660 performs supply
voltage conversion from positive to negative for an input
range of + 1.5V to + 10.0V, resulting in complementary
output voltages of -1.5V to -10.0V. Only 2 non-critical
external capacitors are needed for the charge pump and
charge reservoir functions. The ICL7660 can also be
connected to function as a voltage doubler and will generate output voltages up to + 1S.6V with a + 10V input. Note
that an additional diode is required for VSUPPLY > 6.5V.
Contained on chip are a series DC power supply regulator, RC oscillator, voltage level translator, and four output
power MOS switches. A unique logic element senses the
, most negative voltage in the device and ensures that the
output N-channel switch source-substrate junctions are not
forward biased. This assures latchup free operation.
The oscillator, when unlOaded, o$cillates at a nominal
frequency of 10kHz for an input supply voltage of 5.0 volts.
This frequency can be lowered by the addition of an
external capacitor to the "OSC"terminal, or the oscillator
may be overdriven by an external clock.
The "LV" terminal may be tied to GROUND to bypass
the internal series regulator and improve low voltage (LV)
operation. At medium to high voltages (+ 3.5 to + 10.0
volts), the LV pin is left floating to prevent device latchup.

•

Simple Conversion of +5V Logic Supply to ±5V
Supplies
,. Simple Voltage Multiplication (VOUT
nVIN)
• 99.9% Typical Open Circuit Voltage Conversion
Efficiency,
• 98% Typical Power Efficiency
• Wide Operating Voltage Range 1.5V to 10.0V
• Easy to Use - Requires Only 2 External
Non-Critical Passive Components

=(-)

APPLICATIONS
•
•

On Board Negative Supply for Dynamic RAMs
Localized /-I-Processor" (8080 Type) Negative
Supplies
Inexpensive Negative Supplies
Data Acquisition Systems

•
•

ORDERING INFORMATION
PART NUMBER

TEMP. RANGE

ICQ660CTV

O· to +10·C

JCL7660CBA

O·C to +70·C

ICL7660CPA

O· ,to +70·C

ICL7660MTV'
ICL7660/D

PACKAGE
TO-99
8 PIN SOIC
',8, PIN MINI DIP

_55· to + 125°C TO-99
'

-

DICE"

• Add' /8,838.to part number if 8838 processing is required.
"Parameter min/max limits guaranteed at 25·C only for DICE orders.

V+(endCASEI

V+

8

OSC
LV
VOUT
CAPCD035201

C0034111

(Outline Dwg BA)
8 LEAD MiniDIP

(Outline Dwg TV)
8 LEAD TO-99

COO35901

(Outline Dwg PAl

Figure 1: Pin Configurations

5-12

Note: All typical values have been guaranteed by characterization and are not tested.

302063--003

ICL7660
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ............................................... 10.5V
LV and OSC Input Voltage
(Note 1) ............... -0.3V to (V± +0.3V) for V+ < 5.5V
(V+ -5.5V) to (V+ +0.3V) for V+ > 5.5V
Current into LV (Note 1) ............... 20j.lA for V+ >3.5V
Output Short Duration (VSUPPLY S 5.5V) ...... Continuous
Power Dissipation (Note 2)
ICL7660CTV ....................................... 500mW
ICL7660CPA ....................................... 300mW
ICL7660MTV ....................................... 500mW

Operating Temperature Range
ICL7660M ........................... -55°C to + 125°C
ICL7660C ................................. O°C to +70°C
Storage Temperature Range ............ -65°C to + 150°C
Lead Temperature
(Soldering, 1Osee) ...........................................300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings -only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

r-------------~--------------~------~--------------------OV+
~-----------------oCAP+

r-------------O CAP-

Your
OSC

LV

=
BD01560r

Figure 2: Functional Diagram

OPERATING CHARACTERISTICS
V + = 5V, TA = 25°C, Case = 0, Test Circuit

Figure 3 (unless otherwise specified)
LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
MIN

TYP

MAX

170

1+

Supply Current

RL = 00

500

!lA

VH1

Supply Voltage Range - Hi

ooe S TA S 70°C, RL = 10kn, LV Open

3.0

6.5

V

(Dx out of circuit) (Note 3)

-55°C S TA S 125°C, RL = 10kn, LV Open
MIN S TA S MAX, .RL = 10kn, LV to GROUND

3.0
1.5

5.0

V

3.5

V

vli

Supply Voltage Range - Lo
(Dx out of circuit)

VH2

Supply Voltage Range - Hi
(DX in circuit)

MIN S TA S MAX, RL = 10kn, LV Open

3.0

10.0

V

Vl2

Supply Voltage Range - Lo
(DX in circuit)

MIN S TA S MAX, RL = 10kn, LV to GROUND

1.5

3.5

V

5-13
Note: All typical values have been guaranteed by characterization and are not tested.

i

a

ICL7660
OPERATING CHARACTERISTICS (CONT.)
LIMITS
SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
MIN

TYP

MAX

55

lOUT = 20mA, TA = 25°C
lOUT = 20mA, O°C::; TA::; + 70°C
Output Source Resistance

ROUT

100

n

120

n

lOUT = 20mA, -55°C::; TA::; + 125°C (Note 3)

150

n

V+ =2V, IOUT=3mA, LV to GROUND
O°C::;TA::; +70°C

300

n

V+ = 2V, lOUT = 3mA, LV to GROUND,
-55°C::; T A::; + 125°C, Ox in circuit (Note 3)

400

n

. Oscillator Frequency

10

kHz

PEl

Power Efficiency

RL = 5kn

95

98

%

VOUT Ef

Voltage Conversion Efficiency

RL =

97

99.9

%

Zose

Oscillator Impedance

V+ =2 Volts

1.0

Mn

V= 5 Volts

100

kn

fose

00

Notes: 1. Connecting any input terminal to voltages greater than V + or less than GROUND may cause destructive latchup.
It is recommended that no inputs from sources operating from external supplies be applied prior to "power up" of
.
the ICL7660.
2. Derate linearly above 50°C by 5.5mWrC.
3. ICL7660M only.

TYPICAL PERFORMANCE CHARACTERISTICS
OPERATING VOLTAGE AS A
FUNCTION OF TEMPERATURE

(Circuit of Figure 3)

OUTPUT SOURCE RESISTANCE AS
A FUNCTION OF SUPPLY VOLTAGE

'!A-~"'~=

~ 7.oF=;:=;::::=P

i

OUTPUT SOURCE RESISTANCE AS A
FUNCTION OF TEMPERATURE

g350
lOUT

rJ ...

~ .
.. 250

./

m200

.

i,oo ~ i-'"'"

I'--.

,.

012345678

TEMPERATUAE(GC)

~ •
o
•

POWER CONVERSION EFFICIENCY
AS A FUNCTION OF OSC.
FREQUENCY

..I..-

Y+""5Y

-50" -250 DO +25° +50" +75°+100"+125°
TEMPERATURE (·C)

SUPPLY VOLTAGE (v+)

OPOO1011

- ~~=+zv

rJ
!i '50

4.ot--

"..
-50

'0

..•

.
.
"
;

SLOPE SSO

7

..

e

20 30 40 50 &0 10 80
LOAD CURRENT !t(m")

V

~

1ft

IV

f--

V

I

20

30

. c:t--J.
I I ......

l100
~

~

w

z

70

so

20.0
1B.O

TA=+25D C
V1"= '2.ov

IV

!

... g:g

12.0

v+:-· 2V

.. .

__ 20;;:
10 ~
I

40

~

so

\

\
\

\

•
1

-2

./

J

"..
i--" V i--"jPY·
012345878
LOAD CURRENT IL (mA)

OPOO0201

NOTE 4. These curves include in the supply current that
current fed directly into the load RL from V + (see Figure 3).
Thus, approximately half the supply current goes directly to
the positive side of the load, and the other half, through the
ICL7660, to the negative side of the load. Ideally, VOUT ==
2 VIN, Is == 2 IL, so VIN • Is == VOUT • IL·

1
~
~,
4.0

2 so

~

1ft

10.0 ~

..
..
l':/
ffi ..

~
o

/

u 20

o

+- 3O~
OPOO0601

SUPPLY CURRENT & POWER CONVERSION
EFFICIENCY AS A FUNCTION OF LOAD CURRENT

ffi ..

50 ~
40 -:;'

lOAD CURRENT IL ImA)

OPQ00101

TA!~OC

1

TA-=+25°CV+ +5V

/
10

2

70

/

50

20
1

80 !(

)t-,.

~ 30

,.,...

3
-4

r

I......

ffi ..

/

::I-2

....
.. ..iii
.. g

1

t-....

!i ..
iii ..

OUTPUT VOLTAGE AS,A FUNCTION
OF OUTPUT CURRENT

V

8.0

i

6.0

~

4.0

i

•z

....

2.0 !:
3JI 4.5 6.0 7.5
LOAD CURRENT IL (mA)

1.5

9.0

OPQO0901

which shows an idealized negative voltage converter.
Capacitor C1 is charged to a voltage, V + , for the half cycle
when switches 81 and 83 are closed. (Note: 8witches 82
and 84 are open during this half cycle.) During the second
half cycle of operation, switches 82 and 84 are closed, with
81 and 83 open, thereby shifting capacitor C1 negatively by
V'I- volts. Charge is then transferred from C1 to C2 such
that the voltage on C2 is exactly V +, assuming ideal
switches and no load on C2. The ICL7660 approaches this
ideal situation more closely than existing non-mechanical
circuits.

Is v+

r--------,-~(+5V)

7

------l
I

,I

"

I
I

I
I

RL

·coscl
Ox

I~~*,,
,

:r

,

..

~VOUT

L __ ..J

In the ICL7660, the 4 switches of Figure 4 are M08
power switches; 81 is a P-channel device and 82, 83 & 84
are N-channel devices. The main difficulty with this ap~
proach is that in integrating the switches, the substrates of
83 & 84 must always remain reverse biased with respect to
their sources, but not so much as to degrade their "ON"
resistances. In addition, at circuit startup, and under output
short circuit conditions (VOUT = V +), the output voltage
must be sensed and the substrate bias adjusted accordingly. Failure to accomplish this would result in high power
losses and probable device latchup.

TCOOO301

NOTES:

1. For large values of Case ( > 1000pF) the values of Cl and C2
should be increased 'to 100"F,
2. Ox is required for supply voltages greater than 6.5V @
- 55'e S TA S + 70'C; refer to performance curves for additional
information.

Figure 3: ICL7660 Test Circuit

This problem is eliminated in the ICL7660 by a logiC
network which senses the output voltage (VOUT) together
with the level translators, and switches the substrates of 83
& 84 to the correct level to maintain necessary reverse bias.

DETAILED DESCRIPTION
The ICL7660 contains all the necessary circuitry to
complete a negative voltage converter, with the exception
of 2 external capacitors which may be inexpensive 10IlF
polarized electrolytic types. The mode of operation of the
device may be best understood by considering Figure 4,

The voltage regulator portion of the ICL7660 is an
integral part of the anti-Iatchup circuitry, however its inherent voltage drop can degrade operation at low voltages.
5-15

Note: All typical values have been guaranteed by characterization and are not tested.

II

i

a

ICL7660
Therefore, to improve low voltage operation the "LV" pin
should be connected to GROUND, disabling the regulator.
For supply voltages greater than 3.5 volts the LV terminal
must be left open to insure latchup proof operation, and
prevent device' damage.

ENERGY IS LOST ONLY IN THE TRANSFER OF
CHARGE BETWEEN CAPACITORS IF A CHANGE IN
VOLTAGE OCCURS. The energy lost is defined by:

where V1 and V2 are the voltages on C1 during the pump
and. transfer cycles. If the impedances of C1 and C2 are
relatively high at the pump frequency (refer to Figure 4)
compared to the value of RL, there will be a substantial
difference in the voltages V1 and V2. Therefore it is not only
desirable to make C2 as large as possible to eliminate
output voltage ripple, but also to employ a correspondingly
large value for C1 in order to achieve maximum efficiency of
operation. '

DO'S AND DON'TS
1.
2.

TCOO0801

Figure 4: Idealized Negative Voltage
Converter

3.

THEORETICAL POWER EFFICIENCY
CONSIDERATIONS
In theory a voltage converter can approach 100%
efficiency if certain conditions are met:
'A The drive circuitry consumes minimal power.
S The output switches have extremely low ON
resistance and virtually no offset.
C The impedances of the pump and reservoir
capacitors are negligible at the pump frequency.
The ICL7660 approaches these conditions for negative
voltage conversion if large values of C1 and C2 are used.

4.

5.

6.

Do not exceed maximum supply voltages.
Do not connect LV terminal to GROUND for supply
voltages greater than 3.5 volts.
Do not short circuit the output to V + supply for
, supply voltages above 5.5 volts for extended
periods, however, transient conditions including
startup are, okay.
When using polarized capacitors, the + terminal of
C1 must be connected to pin 2 of the ICL7660 and
the + terminal of C2 must be connected to
GROUND.
Add diode Ox as shown in Figure 3 for high-voltage,
elevated temperature ,applications.
Add capacitor (~0.1IlF, disc) from pin 8 to ground to
limit rate of rise of input voltage to approximately
2V//lS.

-v+

·NOTE: 1. Your =
FOR
1.SV :5 V,V:5 6.SV
2. Your = -(v+ -VFOX)
FOR 6.5 :5 v+ :5 10.0V

Dx

,...-f4--,
I

ICL7660

I

9----T..------<0 Your·

+

L _____ J

~ 10j. 10V
Current into LV (Note 1) •............... 20IlA for V+ > 10V
Output Short Duration ...............•.......•...... Continuous

Power Dissipation (Note 2)
ICL7662CTY .........•...................•......... 500mW
ICL7662CPA .........•.........................•... 300mW
ICL7662MTY ........••...............•...•......... 500mW
Lead Temperature (Soidering, 10sec) •.••.......•..... 300·C

Stresses above those listed under, Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied, Exposure to
absolute maximum rating conditions for extended periods may affect device reliability,
.

ELECTRICAL CHARACTERISTICS

v+

= 15V,

TA

= 25·C,

COSC

= 0,

unless otherwise stated. Test Circuit

Figure 3.

LIMITS
SYMBOL

PARAMETER

UNIT

TEST CONDITIONS
MIN

V+L
V+H

Supply Voltage Range-La
Supply Voltage Range-Hi

1+

Supply Current

= 10kn, LV = GND
= 10kn, LV = Open
RL = .., 'LV = Open

Ro

Output Source ReSistance

1+5

RL
RL

Min < TA < Max
Min J..U.W-I..J.J.J..WI1--'-J..UJ.IIII

1

10

0P046911

UNLOADED OSCILLATOR
FREQUENCY AS A FUNCTION OF
TEMPERATURE

I:... " "
It«'"

/'

...:- -

~~

./

V

.LLLLLLLL~LL~~~~"-J

II

/'

n•

...•
I :•

•w

I:

OUTPUT SOURCE RESISTANCE AS A
FUNCTION OF TEMPERATURE

v...

100

_

.""'

OP04701!

OUTPUT VOLTAGE AS A
FUNCTION OF LOAD CURRENT

OUTPUT VOLTAGE AS A
FUNCTION OF LOAD CURRENT

11¥

Caoc·'

"-

.t«

H
~II

.......

.........
.........

-a

a

+.

.......

...

..•

"""""""'-

12

S

46""

1011121314161. t74818 ..

LOAD CURRENT IL~

OP0472'I

0P047111

5-22
Note: All typical values have been guaranteed by characterization a"d are not tested.

OP04731I

ICL7662
TYPICAL PERFORMANCE CHARACTERISTICS (CO NT.)
SUPPLY CURRENT & POWER
CONVERSION EFFICIENCY AS A
FUNCTION OF LOAD CURRENT

SUPPLY CURRENT & POWER
CONVERSION EFFICIENCY AS A
FUNCTION OF LOAD CURRENT

.•.....

~.
~

FREQUENCY OF OSCILLATION AS A
FUNCTION OF SUPPLY VOLTAGE

'

j:
L

i.
:10

LOAD CURRENT IL trN\)

00

50

00

70

LOAD CURfloENT IL (IRA)

0P047411

OP04751I

0P047821

SUPPLY CURRENT AS A FUNCTION OF
OSCILLATOR FREQUENCY

LOAD CURRENT ',(rnA)
Is

V+

1-------------1~·~1

+ 5V

·'-">Trrm--rrrrrmr-'-n~m

~~~,.~.~~~--~+H~--+-H~~

! .. -+ ..

~:

:...tfI--++++tH1t-+ttlHtIi
G1

i~~H4~~H4~~H4~
·Cosc:

T

i :~-H-++H+H--~+H~--+!J-,~#l
V

•

•
•
•

M

TC000311

.

.

OICIIAIOII_"

NOTE: 1. For large value of COSC ( > 1000pl) the values of C, and
C2 should be increased to 1001lF.

Figure 3: ICL7662 Test Circuit

OP04791I

NOTE 4.
Note that these curves include in the supply current that current led
directly into the load RL Irom V + (see Figure 3). Thus, approximately half
the supply current goes directly to the positive side 01 the load, and the
other half, through the ICL7662, to the negative side of the load.ldeally,
VLOAD "" 2V,N, IS "" 2 IL, so V,N • IS "" VLOAD • IL

In the ICL7662, the 4 switches of Figure 4 are MOS
power switches; Sl is a P-channel device and S2, S3 & S4
are N-channel devices. The main difficulty with this approach is that in integrating the switches, the substrates of
S3 & S4 must always remain reverse biased with respect to
their sources, but not so much as to degrade their "ON"
resistances. In addition, at circuit startup, and under output
short circuit conditions (VOUT = V+), the output voltage
must be sensed and the substrate bias adjusted accordingly. Failure to accomplish this would result in high power
losses and probable device latchup.

CIRCUIT DESCRIPTION
The ICL7662 contains al\ the necessary Circuitry to
complete a negative voltage converter, with the exception
of 2 external capacitors which may be inexpensive 10IJF
polarized electrolytic capacitors. The mode of operation of
the device may be best understood by considering Figure 4,
which shows an idealized negative voltage converter.
Capacitor Cl is charged to a voltage, V + , for the half cycle
when switches Sl and S3 are closed. (Note: Switches S2
and S4 are open during this half cycle.) During the second
half cycle of operation, switches S2 and S4 are closed, with
Sl and S3 open, thereby shifting capacitor Cl negatively by
V + volts. Charge is then transferred from Cl to C2 such
that the voltage on C2 is exactly V +, assuming ideal
switches and no load on C2. The ICL7662 approaches this
ideal situation more closely than existing non-mechanical
circuits.

This problem is eliminated in the. ICL7662 by a logic
network which senses the output voltage (VOUT) together
with the level translators, and switches the substrates of S3
& S4 to the correct level to maintain necessary reverse bias.
The voltage regulator portion of the ICL7662 is an
integral part of the anti-Iatchup circuitry, however its inherent voltage drop can degrade operation at low voltages.
Therefore, to improve low voltage operation the " LV" pin
should be connected to GROUND, disabling the regulator.
For supply voltages greater than 11 volts the LV terminal
must be left open to insure latchup proof operation, and
prevent device' damage.

5-23
Note: All typical values have been' guaranteed by characterization and are not tested.

i

ICL7662

a

the + terminal of C2 must be connected to
GROUND.

TYPICAL APPLICATIONS

Simple Negative Voltage Converter
The majority of applications will undoubtedly utilize the
ICL7662 for generation of negative supply voltages. Figure
5 shows typical connections to provide a negative supply
where a positive supply of + 4.5V to 20.0V is available.
Keep in mind that pin 6 (LV) is tied to the supply negative
(GND) for supply voltages below 11 volts.
The output characteristics of the circuit in Figure 5 are
those of a nearly ideal voltage source in series with 65
ohms. Thus for a load current of -10mA and a supply
voltage of + 15 volts, the output voltage will be 14.35 volts.
The dynamic output impedance due to the capacitor
impedances is approximately 11 we, where:

TCOOO801

Figure 4: Idealized Negative Converter

THEORETICAL POWER EFFICIENCY
CONSIDERATIONS
In theory a voltage multiplier can approach 100% efficiency if certain conditions are met:
A The drive circuitry consumes l"fIinimal power
8 The output switches have extremely low ON
resistance and virtually no offset.
C The impedances of the pump and reservoir
capacitors are negligible at the pump frequency.
The ICL7662 approaches these conditions for negative
voltage multiplication if large values of C1 and C2 are used.
ENERGY IS LOST ONLY IN THE TRANSFER OF
CHARGE BETWEEN CAPACITORS IF A CHANGE IN
VOLTAGE OCCURS. The energy lost is defined by:

C=C1 =C2
which gives

...:!.. =

1
= 3 ohms
271 fpump x 10~5

we

for C = 10llF and fpump = 5kHz (1/2 of oscillator frequency)

Paralleling Devices
Any number of ICL7662 voltage converters may be
paralleled to reduce output resistance. The reservoir capacitor, C2, serves all devices while each device requires its
own pump capacitor, C1. The resultant output resistance
.
would be approximately

E=1/2 C1 (V12_V22).

ROUT (of ICL7662)

ROUT=--~---------­

where V1 and V2 are the voltages on C1 during the pump
and transfer cycles. If the impedances of C1 and C2 are
relatively high at the pump frequency (refer to Figure 4)
compared to the .. value of RL, there will be a substantial
oifference in the voltages V1 and V2. Therefore it is not only
desirable to ma,ke C2 as large as possible to eliminate
output voltage ripple, but al!:lo to employ a correspondingly
large value for C1 in order to achieve maximum efficiency of
operation.

n (number of devices)

Cascading Devices
The ICL7662 may be cascaded as shown to produce
larger negative multiplication of the initial supply voltage.
However, due to the finite efficiency of each device, the
practical limit is 10 devices for light loads. The output
voltage is defined by:

DO'S AND DON'TS
1.
2.
3.

VOUT = -n (VIN),

Do not exceed maximum supply voltages.
Do not connect LV terminal to GROUND for supply
voltages greater than 11 volts.
When using polarized capacitors, the + terminal of
C1 must be connected to pin 2 of the ICL7662 and

where n is an integer representing the' number of devices
cascaded. The resulting output resistance would be approximately the weighted sum of the individual ICL7662 ROUT
values.
'

,-----...,..---<>

+

VOUT ... - y+

TC038601

Figure 5: Simple Negative Converter

&-24
Note: All typical values have been guaranteed by characterization and are not tested.'

ICL7662

TCOOO91t

Figure 6: Paralleling Devices

V+

H~--9-.....,..- CAN BE ANY
SUITABLE DIODE

Regulated Negative Voltage Supply

TC037901

Figure 10: Positive Voltage Doubler

In some cases, the output impedance of the ICL7662 can
be a problem, particularly if the load current varies substantially. The circuit of Figure 13 can be used to overcome this
by controlling the input voltage, via an ICL7611 low-power
CMOS op amp, in such a way as to maintain a nearly
constant output yoltage. Direct feedback is inadvisable,
since the ICL7662's output does not respond instantaneously to a change in input, but only after the switching
delay. The circuit shown supplies enough delay to accommodate the 7662, while maintaining adequate feedback. An
increase in pump and storage capaCitors is desirable, and
the values shown provides an output impedance of less
than 5.12 to a load of 10mA.

Combined Negative Voltage Conversion
and Positive Supply Doubling
.
Figure 11 combines the functions shown in Figures 5 and
10 to provide negative. voltage co.nversion and positive
voltage doubling simultaneously. This approach would be,
for example, suitable for generating + 9 volts and -5 volts
from an existing + 5 volt supply. In this instance capacitors
C1 and Cs perform the pump and reservoir functions
respectively for the ·generation of the negative voltage,
while capacitors C2 and C4 are pump and reservoir
respectively for the doubled positive voltage. There is a
penalty in this configuration which combines both functions,
however, in that the source impedances of the generated
supplies will be somewhat higher due to the finite impedance of the common charge pump driver at pin 2 of the
device.

-... ...

,....

v.
I~

TC036101

Figure 13: Regulating the Output Voltage

OTHER APPLICATIONS
TC038201

Further information on the operation and use of the
ICL7662 may be found in A051 "Principals and Applications
of the ICL7660 CMOS Voltage Converter" by Peter Bradshaw and Dave Bingham.

Figure 11: Combined Negative Converter
and Positive Doubler

5-26
Note: All typical values have been guaranteed by characterization and are .not tested.

.U~UIl5

ICL7663/7664
CMOS Programmable
Micropower Voltage Regulators

CI
to)

.CI...

GENERAL DESCRIPTION

FEATURES

The ICL7663 (positive) and ICL7664 (negative) series
regulators are low-power, high-efficiency devices which
accept inputs from 1.6V to 10V and provide adjustable
outputs over the same range at currents up to 40mA.
Operating current is typically less than 4p.A, regardless of
load.
Output current sensing and remote shutdown are available on both devices, thereby providing protection for the
regulators and the circuits they power. A unique feature, on
the ICL7663 only, is a negative temperature coefficient
output. This can be used, for example, to efficiently tailor
the voltage applied to a multiplexed LCD through the driver
(e.g., ICM7231 12/3/4) so as to extend the display operating
temperature range many times.
The ICL7663 and ICL7664 are available in either an a-pin
plastic, TO-99 can, CERDIP, and SOIC packages.

•
•
•
•
•
•
•
•

:

Ideal for Battery-Operated Systems: Less Than
4/-lA Typical Current Drain
Will Handle Input Voltages From 1.6V to 16V
Very Low Input-Output Differential Voltage
1.3V Bandgap Voltage Reference
Up to 40mA Output Current
Output Shutdown Via Current-Limit Sensing or
External Logic Signal
Output Voltages Programmable From 1.3V to
16V
Output Voltages With Programmable Negative
Temperature Coefficients (lCL7663 Only)

ORDERING INFORMATION
POSITIVE REGULATOR
TEMPERATURE
RANGE

PART NUMBER

O·C to +70·C
O·C to +70·C
O·C to +70·C

ICL7663CBA
ICL7663CPA
ICL7663CJA
ICL7663/D
ICL7663CTV

O·C to +70·C

NEGATIVE REGULATOR
PACKAGE

8-Lead
8-Lead
B-Lead
DICE"
B-Lead

PART NUMBER

SOIC
MiniDIP
CERDIP

ICL7664/D
ICL7664CBA
ICL7664CJA
ICL7664CPA
ICL7664CTV

TO-99

TEMPERATURE
RANGE
O·C
O·C
O°C
QOC

- +70·C

to
to
to
to

+70·C
+ 70°C
+70·C

PACKAGE
DICE"
8·Lead
8·Lead
B-Lead
B-Lead

SOIC
CERDIP
MiniDIP
T0-99

'-Parameter MinIMax Limits guaranteed at 25°C only lor DICE orders.

...

'

...
~------------~

.
.....

...

r----"" -4·.880
- -4.975

~ -4.970

I I II

VI1=J-r -

-4.855

o

-4.950
1~

10~ loo~

1.0

10.0 100.0

I I I

I

.1.-1

I

o

.--rr

/

/
.&~

3.0

lOUT (mA)

100

90
80
70

VI7=1-115V

6.0
9.0
IaUT2 (mA)

12.0

51 2.0 I--tbol-::::lOf"'9-1.5
1.0 I++-+--+-~-+~--If-I
0.5

H-+-+-++-+--+-iH

OLJ.!'WIL.l.WlIII....1.UJIIII.....I.1J.UllL.UJlIIII

0.1
1.0 10.0 100.0
FREQUENCY (Hz)

lk

I
I

V
~

VIN=I_~V I;;;;; 1:=

_.... T
o

3.0

IVIN= -15V

6.0

9.0

12.0 15.0
OP021601

OP021501

ICL7664 QUIESCENT CURRENT AS
A FUNCTION OF INPUT VOLTAGE

~ 2.5H~'"""f~~

0.01

Viii .. -2VI I

Ioun (mA)

3.0

t-ttlltllll--ttttlt-tttllI-l-ttilllHolHllll

TA= +25°C

o

15.0

3.5~+-+-~~-+~~~

40
30
20
10

2.0
1.8
1.6
~ 1.4
1.2
~ 1.0
~ 0.8
Ii!!
!!. 0.&
0.4
0.2

ICL7664 QUIESCENT CURRENT AS A
FUNCTION OF TEMPERATURE
5.0
4.5
4.0
3.5

5.0 r-"--"--~-~~~"""
-1.4V:5VouT:5V4.5 Voun AND VoUT2
4.0 CONNECTED TOGEtHER

TA-+WC
VIN= -II.ov
AVIN=2.0V

ii
:s- 80
ac 50
ac

If

j...

.......... i- ~

OP021401

ICL7664 INPUT POWER SUPPLY
REJECTION RATIO

,---:

VIN=-~

!

-4.915
-4.980

I I I
I I

TA;' +25"<:

ICL7664 VOUT2 INPUT-oUTPUT
DIFFERENTIAL VS OUTPUT CURRENT

2

4

6

8 10 12 14 16

YiN

1:
_

3.0
2.5

51 2.0
1.5
1.0
0.5

-- -

Iv

r-.

~

o

-20

(V)

V- ::;V

r-. ...

0

20

J =l-l~V

1 I I
v- = -2V

I I I
I I I
40

50

80

TEMPERATURE (OC)
OP021801

0P021701

I I I
I I I

OP021901

DETAILED DESCRIPTION
The ICL7663 and ICL7664 are CMOS integrated circuits
which contain all the functions of a voltage regulator plus
protection circuitry on a single monolithic chip. Referring to
the functional diagrams (Figure 1), it can be seen that each
contains a bandgap-type voltage reference of 1.3 Volts.
This voltage, therefore, is the lowest output voltage the
regulators can control ( -1.3V for the ICL7664). Error
amplifier A drives either a P-channel (ICL7663) or an
N-channel (ICL7664) pass transistor which is sufficient for
low (under about SmA) currents; this transistor is augmented by a duplicate in the ICL7664, which permits higher
current outputs. In the ICL7663, the high curren~ output is
passed by an NPN bipolar transistor connected as a
follower. This configuration gives more gain and lower
output impedance.

extremely low quiescent current. This does limit the dynamic response of the circuits, however, and transients are best
dealt with outside the regulator loop.

BASIC OPERATION
The ICL7663 and ICL7664 are designed to regulate
battery voltages in the SV to 1SV region at maximum load
currents of about SmA to 30mA. Although intended as low
power devices, power dissipation limits must be observed.
For example, the power dissipation in the case of a 10V
supply regulated down to 2V with a load current of 30mA
clearly exceeds the power disSipation rating of the minidip:
(10-2)(30) (10- 3) = 240mW. The test circuit illustrates
proper use of the devices. Although the following discussion
refers to the ICL7663, it applies as well to the parallel
features of the ICL7664 as long as the appropriate polarities
are reversed. Individual features and precautions will be
discussed where appropriate.
CMOS devices generally require two precautions: every
input pin must go somewhere, and maximum values of
applied VOltages and current limits must be rigorously
observed. Neglecting these precautions may lead to, at the
least, incorrect or non-operation, and at worst, destructive
device failure. To avoid the problem of latchup, do not apply
inputs to any pins before supply voltage is applied.

Logic-controlled shutdown is implemented via an MOS
transistor of the appropriate polarity. Current-sensing is
achieved with comparator C, which functions with the
Vour2 line on each chip. Finally, the positive regulator
(ICL7663 only) has an output (Vre) from a buffer amplifier
(B), which can be used to generate programmable-temperature-coefficient output voltages.
The amplifiers, reference and comparator circuitry all
operate at bias, levels well below 1jJA to achieve the
5-32

Note: All typical values have been guaranteed by characterization and are not tested.

ICL7663/7664
-0.3V for the ICL7664 will keep the regulator ON, and a
voltage level of more than l.4V but less than VI~ for the
ICL7663, and less than -l.4V but not less than YiN for the
ICL7664 control will turn the outputs OFF. If there is a
possibility that the control signal could exceed the regulator
input (ViN or YiN), the current from this signal should be
limited to 100pA maximum by a high-value (1 Mil) series
resistor. This situation may occur when the logic signal
originates from a system powered separately from that of
the regulator.

Input Voltages - These regulators accept working inputs
of l.4V to 18V. When power is applied, the rate-of-rise of
the input may be hundreds of volts per microsecond. This is
potentially harmful to the regulators, where internal operating currents are in the nanoampere range. The 0.047J.IF
capacitor on the device side of the switch will limit inputs to
a safe level around 2V I J.l.s. Use of this capacitor is
suggested in all applications. In severe rate-of-rise cases, it
may be advisable to use an RC network on the SHutDowN
pin to delay output turn-on. Battery charging surges, transients, and assorted noise signals should be kept from the
regulators by RC filtering, zener protection, or even fusing.
Output Voltages- The resistor divider R2/R1 is used to
scale the reference voltage, VSET, to the desired output
using the formula VOUT = (1 + R2/R1) VSET. In the
ICL7664, VIN and VSET are negative, so VOUT will also be
negative. Suitable arrangements of these resistors, using a
potentiometer, enables exact values for VOUT to be obtained. Because of the low leakage current of the VSET
terminal, these resistors can be tens of megohms for
minimum additional quiescent drain current. However, some
load current is required for proper operation, so for extremely low-drain applications it is necessary to draw at least 1pA.
This can include the current for R2 and R1.
Output voltages up to nearly the VIN supply may be
obtained at low load currents, while the low limit is the
reference voltage. The minimum input-output differential in
each regulator is obtained using the VOUT1 terminal.
Output Currents - For the ICL7663, low output currents
of less than 5mA are obtained with the least input-output
differential from the VOUT1 terminal (connect VOUT2 to
VOUT1). Either output may be used on the ICL7664, with the
unused output connected to YiN. Where higher currents are
needed, use VOUT2 on the ICL7663 (VOUT1 should be left
open in this case) and parallel VOUT1 and VOUT2 on the
ICL7664.
High output currents can be obtained only as far as
package dissipation allows. It is strongly recommended that
output current-limit sensing be used in such cases.
Current-Limit Sensing - The on-Chip comparator (C in
the block diagrams) permits shutdown of the regulator
output in the event of excessive current drain. As the test
circuits show, a current-limiting resistor, RCL, is placed in
series with VOUT2, and the SENSE terminal is connected to
the load side of RCl. When the current through RCl is high
enough to produce a voltage drop equal to VCl (0.7V for
ICL7663, 0.35V for ICL7664) the voltage feedback is
bypassed and the regulator output will be limited to this
current. Therefore, when the maximum load current (llOAD)
is determined, simply divide VCl by IlOAD to obtain the
value for RCl.
Logic-Controllable Shutdown - When equipment is not
needed continuously (e.g., in remote data-acquisition sys'tems), it is desirable to eliminate its drain on the system until
it is required. This usually means switches, with their
unreliable contacts. Instead, the ICL7663 and ICL7664 can
.be shut down by a logic Signal, leaving only IQ (under 4pA)
,as a drain on the power source. Since this pin must not be
left open, it should be tied to ground if not needed. A
,voltage of less than 0.3V for the ICL7663, and greater than

Additional Circuit Precautions - These regulators have
poor rejection of voltage fluctuations from AC sources
above 10Hz or so. To prevent the output from responding
(where this might be a problem), a reservoir capacitor
across the load is advised. The value of this capacitor is
chosen so that the regl,Jlated output voltage reaches 90%
of its final value in 20ms. From
AV
(20 xl 0- 3)
lOUT
I = C-, C = lOUT
= 0.022--.
At
0.9VOUT
VOUT
In addition, where such a capacitor is used, a currentlimiting resistor is also suggested (see "Current-Limit
Sensing").
Producing Output Voltages With Negative Temperature
Coefficients - The ICL7663 has an additional output (not
present on the ICL7664) which is 0.9V relative to GND and
has a tempco of + 2.5mV IOC. By applying this voltage to
the inverting input of amplifier A (i.e., the VSET pin), output
voltages having negative TC may be produced. The TC of
the output voltage is controlled by the R2/R3 ratio (see
Figure 4 and its design equations).

> ......-OVOUT
+

lVTC
lCO09201

EQ.l: VOUT

R2

R2

R1

R3

= VSET(l + -) + -(VSET - VTcl

R2
EQ.2: TC VOUT = --(TCVTC) in mVrC
R3
WHERE: VSET = 1.3V
VTC = 0.9V
TCVTC = +2.5mV/ O C

Figure 4: Generating Negative
Temperature CoeffiCients

5-33
Nole: All typical values have been guaranleed by characterizalion and are nol lesled.

! I.CL766317664
fi'

APPLICATIONS

:8

..

i

VIN SENS.E
VOUT2
VOUT1
ICL7683

VTC

VIN=~_

J

RCL

GND

-

1

r~~

~R2

-

VOUT

VOUT1
ICL7684

YOUTZ

v,iii

Rl

GND SHDN

1

VOUT

n

Aa
A\:L

SENSE

.. 1
VOUT

R·I

\/seT

VSET

O,047.F

~

I

SHDN

AF028901

_ R2+Rl V
SET
Your

ICL _ O.7V
RCL

R2+Rl
=----VSET
Rl

O.35V
ICI..=-RCL

AF029911

Figure 5: Basic Application of ICL7663 as
Positive Regulator with Current Limit

Figure 6: Basic Application of ICL7664 as
Negative Regulator with Current Limit

SENSE

r - -.....- - - - - - - - - -....-~v,j;

8 v+

Cooc

7

ICL7683

A\:L

VOUTI-'WIt-+-_-o+sv

CAP+ 2

CAP- 4
ICL7680
GNDf3~-~~-1~_ _

l00pF

+-_______~~~-,

V0,
lN4148

l00.F

•
A\:l

'---------------~v,iii

vouT!-'WIr-+-_-o-5V

ICL7664

SENS!'
05017801

'Values depend on load characteristics

Figure 7: Generating regulated split supplies from a single supply.
The oscillation frequency of the ICL7660 is reduced by the external oscillator capacitor, so that it
inverts the battery voltage more efficiently.

5-34
Note: All typical values have been guaranteed by characterization ·and are not tested.

ICL7663/7664
I

1

y+

+

BY£"

~--

L

Vsn

~~

DIPS

PM

OSC
OUT

1

SN.

I

l

SHUTDOWN

ICM7223A

Y-

R,

GND

RADIO
OSC ENABLE
IN
SEG

..

A2

ICL7684

Roc

LCD DISPLAY

VOUT1

Zz>

SStSS

VOUT2

1

L

W

1
SYSTEM_I-

T
REPEAT
SIGNAL

SENSE

VIN

I
LC009401

Figure 8: Once a Day System.
This circuit will turn on a regulated supply to a system for one minute every day, via the SHUTDOWN
pin on the ICL7664, and under control of the ICM7223A Alarm Cloc;j.k circuit. If the system decides it
needs another one minute activation, pulling the REPEAT line to V (GND) during one activation will
trigger a subsequent activation after a snooze interval set by the choice of SN pins (2 mins shown).
Alternatively, activation of the Sleep timer, without pause, can be achieved. See ICM7223A data
sheet for details.

5-35
Note: All typical values have been guaranteed by characterization and are not tested.

I....

-:

.O~DI1.

ICL7663/7864

ICL7663B/4B ADDENDUM TO THE ICL7663/4 OATASHEET

CD

a

This Addendum to the standard ICL7663/4 datasheet
describes changes an~/or'modifications to the DC Operating characteristics 8pplicableto the ICL7663B/ICL7664B
devices. The following table indicates those limits to which
the ICL7663B/ICL7664B is tested and/or guaranteed operational.

ICL7663B POSITIVE REGULATOR
ORDERING INFORMATION
POSITIVE REGULATOR

ICL7663B/D
·ICL76638CBA
ICL7663BCJA
ICL7663BCPA
ICL7663BCTV

O·C
O·C
O·C
O·C

-

to
to
to
to

DICE
a-pin S.O.I.C.
a-pin CERDIP
a-pin MiniDIP
TO-99

70·C
70·C
70·C
70·e

ABSOLUTE MAXIMUM RATINGS ICL7663B
Input Supply Voltage ...•........•............... ,., ......... + 12V
Any Input or OutpuCVoltage(Note ..1) Terminals 1, 2, 3,
4, 5, 6, 7) ........... : ......• (GND -O.3V) to (ViI:! "t O.3V)
Output Source Current
(Terminal 2) ....................................... ,. SOmA
(Terminal 3) .....•................................... 25mA .

Output Sinking Current (Terminal 7) ................. -1 OmA
Power Dissipation (Note 2)
MiniDIP ............................................. 200mW
TO-99 Can ......................................... 300mW

Stresses above thOse listed under" Absolute Maximum'Ratings" may cause permanent damage to the device. These are stress ratings only and funCtional
operation of the device at these or any other conditions above those indicated in the operational sections of the specffications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ICL7663B OPERATING CHARACTERISTICS

ViI:! = 9V, VOUT = 5V, TA = + 25°C, unless otherwise specified.
LIMITS

SYMBOL

PARAMETER

UNIT

TEST CONDITIONS
MIN

Input Voltage

TA- + 25·C
20·Q$TA$ +70·C

IQ

Quiescent Current

jRL = 00
1.4V $ VOUT $ 8.5V

VSET

Reference VoHage

VIN

aVSET
aT
aVSET

I

TVP

1.5
1.6

1.2

MAX
10
10

V

3.5

10

IJA

1.3

1.4

V

Temperature Coefficient

8.5V < VIN < 9V

±200

ppm

Line Regulation

2V are not lested.

0.7

V

n

2
1

n
mA
V

0.9
0

V
nA

200
70

10
25

Open-Circuit Voltage
Maximum Sink Current

10

8

2

mA

ICL7663/7664
ICL7663B OPERATING CHARACTERISTICS (CONT.)
LIMITS
SYMBOL

PARAMETER

UNIT

TEST CONDITIONS
MIN

tNTC

LlT
ILlmin)
NOTES:

Temperature Coefficient

Open Circuit

Minimum Load Current

(Includes VSET Divider)

TYP

MAX
mVl·C

+.2.5

1

/lA

1. Connecting any tenminal to voltages greater than (Viii + O.3V) or less than (GND -O.3V) may cause destructive device latchup. It is
recommended that no inputs from sources operating on external power supplies be applied prior to ICL7663B power-up.
2. Derate linearly above 50·C at 5mW
for minidip and 7.5mW,·C for TO-99 can.
.
3. This parameter refers to the saturation resistance of the MOS pass transistor. The minimum input-output voltage differential at low current
(under 5mA), can be detenmined by multiplying the load current (including set resistor current, but not quiescent current) by this resistance.
4. This output has a positive temperature coefficient. Using it in combination with the inverting input of the regulator at VSET, a negative coefficient
results in the output voltage. See Figure 3 for details. Pin will not source current.

rc

5-37
Note: All typical values have been guaranteed by characterization and are not tested.

IC1.766317884
ICL7664B NEGATIVE REGULATOR
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
ICL7664B
.

Negative Regulator

ICL7664BCPA
ICL7664BCTV
ICL7664B/D
ICL7664BCBA
ICL7664BCJA

o to
o to
o to
o to

+70·C
+70·C

-+70·C
+70·C

B-pin MiniDIP
TO-99
DICE
B-pin S.O.I.C
B-pin. CERDIP

Input Supply Voltage ........................................ -12V
Any Input or Output Voltage (Note 1)
(Terminals 1,2,3,4,5,6;7,) ................ (GND + O.3V)
.
to (ViN-O.3V)
Output Source Current
(Terminal 1,7) .................................... -25mA
Power Dissipation (Note 2)
MiniDIP ............................................. 200mW
TO-99 ............................................... 300mW

Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specijications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ICL7664B OPERATING CHARACTERISTICS

VjN=9V, Vout= -5V, TA= +25·C, unless otherwise

specified.
LIMITS
PARAMETER

SYMBOL

TEST CONDITIONS

UNIT
MIN

Input Voltage

TA = +25·C
O:5TA:5 +70·C

10

Quiescent Current

lRl = 00
}
-1.4V:5 VOUT:5 -8.5V

VSET

Reference Voltage

YiN

 t.3V, OUT1 switch ON
HYST1 switch ON
VSETt < 1.3V, OUT1 switch OFF
HYSTI switch OFF
VSET2 > 1.3V, OUT2 switch OFF
HYST2 switch ON
VSET2 < 1.3V, OUT2 switch ON
HYST2 switch OFF
'See Operating Characteristics for exact thresholds.

HYST2

SETl<>---+------r.~

~~t_t~~------OHY~l
'>-1~_It~---oOUT2

sm <>---+------1;"
0UT1
~---------------~----~_oGND
60006701

Figure 1: Functional Diagram

v+
(CASE)

(Outline dwg PAl

GND
CD016611

CD035SOI

(Outline dwg TV)
CD016711

(outline dwg SA)

Figure 2: Pin Configurations
5-39
Note: All typical values have been guaranteed by characterization and are not tested.,

302067-002

i

ICL7865"

g!:i

ABSOLUTE MAXIMUM RATINGS
Maximum Sink Output Current 00T1 and OUT2 ... 25mA:
Maximum Source Output Current HYST1
and HYST2 ................... '............. ;, ............. ~25mA;
Power Dissipation (Note 1) ............................. 200mW'.
Operating Temperature Range .............. O°C to + 70°C
Storage Temperature Range ............ -55°C to + 125°C
Lead Temperature (Soldering, 10sec) ................. 300°C

Supply Voltage .................................. -O.3V to + 18V
Output Voltages OUT1 and OUT2 (with respect to
GND) (Note 2) ............................... -O.3V to + 18V
Output Voltages HYST1 and HYST2 (with respect to'
V+) (Nate 2) ...... :.;;: ...................... +O.3Vto' -18V
Input Voltages SEH and SET2'
.
(Note 2) ................ : .... (GND-O.3V) to (v+ +O.3V)

Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions, above those indicated in the operational sections of the speCifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
'

ELECTRICAL CHARACTERISTICS
DC OPERATING CHARACTERISTICS (v+

=

5V, TA = +25°C, unless otherwise specified. See Test Circuit

Fig. 4)
LIMITS
SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
MIN

y+

Operating Supply Yoltage

TA = +25·C
O·C ~ TA ~ +70·C

1+

Supply Current

GND ~ YSET1, YSET2 ~ y+
All Outputs Open Circuit
y+ =2Y
y+ =9Y
y+ = 15Y

YSETt
YSET2

Inp~t

t.YSET

Temperature Coefficient
of YSET

t.T
t.YSET

Trip Yoltage

Supply Yoltage Sensitivity
of YSETt, YSET2

ROUTt, ROUT2, RHYST1, RHYST2 = 1MS1

IOlK
IHlK

Output Leakage Currents
on OUT and HYST

YSET

= OY

or YSET 2! 2Y

2.5
2.6
2.9

10
10
15

1.3
1.3

1.45
1.4

Y

I1A
Y

±200

ppm/·C

0.004

%/V

10
-10

200
-100
2000
-500

nA

y+ = 2Y. YSETI = 2Y. IOUTl = 2mA
Y + = 5Y. YSETt = 2Y. IOUTt = 2mA
y+ = 9Y. YSETI = 2Y, IOUTl = 2mA

0.2
0.1
0.06

0.5
0.3
0.2

YHYSTt
YHYSTI
YHYSTt

Y + = 2Y. YSETt = 2Y, IHYSTt = -O.SmA
y+ = SY. YSETI = 2Y, IHYSTt = -O.SmA
y+ = 9Y. YSETt = 2Y, IHYSTI = -O.SmA

-0.15
-0.05
-0.02

-0.3
-0.15
-0.10

YOUT2
YOUT2
YOUT2

y+ = 2Y. YSET2 = OY. IOUT2 = 2mA
Y + = 5Y, YSET2 = ay, IOUT2 = 2mA
Y + = 9Y, YSET2 = OY. IOUT2 = 2mA

0.2
O.IS
0.11

0.5
0.3
0.2S

YHYST2
VHYST2
YHYST2

y+ =2Y, YSET2= 2Y. IHYST2= -0.2mA
Y + = 5Y. YSET2 = 2Y. IHYST2 = -O.SmA
Y + = 9Y. YSET2 = 2Y, IHYST2 = -0.5mA

-0.25
-0.43
0.35

-0.8
-1.0
-1.0

0.01

10

nA

±50

mY

YOUTI
YOUTI
YOUTI

ISET
C.YSET
YSETt"-YSET2

Output Saturation Yoltages

MAX
16
16

y+ = 9Y, TA = 70·C
y+ = 9Y. TA = 70·C

IOlK
IHlK

,

1.6
1.8

1.15
1.2

t.Ys

TYP

YSET' Input Leakage Current

GND ~ YSET ~ y+

t.YSET Input for Complete
Output Change

ROUT = 4.7kS1. RHYST = 20kS1
YOUTLO = 1% Y+, YOUTH I = 99% y+

Difference in Trip Yoltages

ROUT, RHYST = 1MS1

Y

1
±5

±1
ROUT, RHYST = lMS1
NOTES: 1. Derate above ± 2S·C amb.ent temperature at 4mW I·C.
2. Due to the SCR s!ructure inherent in the CMOS process used to fabricate these devices, connecting any terminal to VOltages greater
than (V + + 0.3V) or less than (GND-0.3YJ may" cause destructive device latchup. For these reason, it is recommended that no
inputs from external sources not operating from the same power supply be applied to the device before its supply is established, and
that in muHiple supply systems, the supply to the ICL7665 be turned on first If this is not possible, currents into inputs and/or
outputs must be limited to ±0.5mA and voltages must no!" exceed those defined above.
OutputlHysteresis Difference

~O

Note: All typical values have been guaranteed by characterization and :are not tested.

ICL7665
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL

PARAMETER

UNITS

TEST CONDITIONS
TYP

MIN
tSOld
tSHld
tS02d
tSH2d
!Sold
tsH2d
ts02d
tsH2d
tolr
to2r
tHlr
tH2r
t01l
t021
tH1f
tH21

Output Delay Time
Input Going HI

VSET Switched from 1.0V to 1.6V
ROUT = 4.7kn, CL = 12pF
RHYST = 20kn, CL = 12pF

70
60
120
230

p.s

VSET Switched from 1.6V to 1.0V
ROUT = 4.7kn, CL = 12pF
RHYST = 20kn, CL = 12pF

1040
610
70
30

p.s

VSET Switched between 1.0V and 1.6V
ROUT = 4.7kn, CL = 12pF
RHYST = 20kn, CL = 12pF

120
60
330
25

p.s

VSET Switched between 1.0V and 1.6V
ROUT = 4.7kn, CL = 12pF
RHYST = 20kn, CL = 12pF

30
60
160
30

p.s

Output Delay Time
Input Going LO
Output Rise Times

Output Fall Times

~------------,-------------------------1JV

INPUT

VSET1. VSET2

OUT1

Iso,.

!------------------------1'OY
-------Y· (5Y)
I~----------

__

~----------_+r_----------ONO

J;---------+-------.t+-------------Y· (5Y)

HYST1

!'-------------ONO

"...----------IH----------------------v· (5Y)
OUT2

MAX

1'-----------------------

ONO

r---------+i1r----:-------------------Y· (5Y)
HVST2
I'-----------------·--~QNO
WF014601

Figure 3: Switching Waveforms

Y·

4.7kD

r---------------+---+---+---.-------------oO~

~--~---.----------oHYSTl
~--~~~r_--~--+_--._----~OUT2

INPUT

1.8V-r-l
1.QV ___-.J
L-.

HYST2

TC02541 I

Figure 4: Test Circuits

5-41
Note: All typical values have been guaranteed by characterization and are not tested.

TYPICAL PERFORMANCE CHARACTERISTICS
OUT1 SATURATION VOLTAGE AS
A FUNCTION OF OUTPUT
CURRENT
~ 2.0

,..--.--rr--.::----:=

IU

CJ

~ 1.6

g
~

i

1.2

t--I-+t--t---t---;

0.8

I--t-T-+---b~'

0.4

1-7t~""l;;~"'t"'\i'

::)

~

SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE

...~z
IU

F"

024

48121620

oun OUTPUT CURRENT (mA)

6

8 W

n

OP098701

~ 2.0
IU

~

1.6

~

1.2

~

!ia:

I

V+ =2V

~

~

5.0
4.5

4.0
3.5
Z
IU 3.0
a:
a:
::) 2.5
CJ 2.0
~
II. 1.5
II.
::)
1.0

.....
II. 1.5

HYST1 OUTPUT SATURATION
VOLTAGE VS HYST1 OUTPUT
CURRENT

I-------J;f-----'-;------'---t--+-H

-1.6

L.L.l_---I..._--'--_.l-L-J

-2.0

~--t

HYSTt OUTPUT CURRENT (mA)

OP023201

OP023301

SUPPLY CURRENT AS A
FUNCTION OF AMBIENT
TEMPERATURE

HYST2 OUTPUT SATURATION
VOLTAGE VS HYST2 OUTPUT
CURRENT
-5.0 --4.0 -3.0 -2.0 -1.0

tt-

~

OV" VSETI, VSET2 :s

8-~115J

v+ r-

I I

U>

1--4--+·---t-Al'I+-; -1.0

~t..;: vl=~v tV+ =2V

0z.,
!!l

'~[,o£-7'I---+--+-; -3.0

o!:i

'--L-L_~_~_L_---'

-20

0

+20

+40

+60

OUT2 OUTPUT CURRENT (mA)

AMBIENT TEMPERATURE ("C)

OP023401

DP023501

DETAILED DESCRIPTION

~-<

1-.-t--J.~09---+--; -2.0

--l/'--+--t----t----j -4.0

o

~

:II:

-5.0

<0

~~
~ --t

3

HYST2 OUTPUT CURRENT (mA)
OP023601

be triggered into a potentially destructive high-current
mode. This latchup can be triggered by forward-biasing an
input or output with respect to the power supply, or by
applying excessive supply voltages. In very-low current
analog circuits, such as the ICL7665, this SCR can also be
triggered by applying the input power supply extremely
rapidly ("instantaneously"), e.g. through a low impedance
battery and an ON/OFF switch with short lead lengths. The
rate-of-rise of the supply voltage can exceed 100V//Js in
such a circuil. A low-impedance capacitor (e.g. O.05/JF disc
ceramic) between the V+ and GrouND pins of the ICL7665
can be used to reduce the rate-of-rise of the supply voltage
in battery applications. In line-operated systems, the rateof-rise of the supply is limited by other considerations, and
is normally not a problem.
If the SET voltages must be applied before the supply
voltage V + , the input current should be limited to less than
O.5mA by appropriate external resistors, usually required for
voltage setting anyway. A similar precaution should be
taken with the outputs if it is likely that they will be driven by
other circuits to levels outside the supplies at any time. See
M011 for some other protection ideas.

As shown in the Functional Diagram, the ICL7665 consists of two comparators which compare input voltages on
the SE'f1 and SET2 terminals to an internal 1.3V band-gap
reference. The outputs from the two comparators drive
open-drain N-channel transistors for OUT1 and OUT2, and
open-drain P-channel transistors for HYST1 and HYST2
outputs. Each section, the Under-Voltage Detector and the
Over-Voltage Detector, is independent of the other, although both use the internal 1.3V reference. The offset
voltages of the two comparators will normally be unequal,
so VSET1 will generally not quite equal VSET2.
The input impedances of the SET1 and SET2 pins are
extremely high, and for most practical applications can be
ignored. The four outputs are open-drain MOS transistors,
and when ON behave as low resistance switches to their
respective supply rails. This minimizes errors in setting-up
the hysteresis, and maximizes the output lIexibility. The
operating currents of the bandgap reference and the
comparators are around 100nA each.

PRECAUTIONS
Junction-isolated CMOS devices like the ICL7665 have
an inherent SCR or 4-layer PNPN structure distributed
throughout the die. Under certain circumstances, this can
5-42

Note: All typical values have been guaranteed by characterization· and are not tested.

ICL7665
APPLICATIONS

1
I
v'

Rp2

R"

A21_~ OUT1

OUT2 r-~

ICL7885

SETI

SEn

R"

.1.
AF029011
AF029101

(b) Transfer Characteristics

(a) Circuit Configuration

Figure 5: Simple Threshold Detector
Figure 5 shows the simplest connection of the ICL7665.
for threshold detection. From the graph (b). it can be seen
that at low input voltages OUTI is OFF. or high. while OUT2
is ON. or low. As the input rises (e.g. at power-on) toward
VNOM (usually the eventual operating voltage). OUT2 goes
high on reaching VTR2. If the voltage rises above VNOM as
much as VTRI. OUT 1 goes low. The equations giving
VSETl and VSET2 are, from Figure 1(a):

conditions. The addition of hysteresis. making the trip points
slightly different for rising and falling inputs, will avoid this
condition.
Figure 6(a) shows how to set up such hysteresis, while
Figure 6(b) shows how the hysteresis around each trip point
produces switching action at different pOints depending on
whether VIN is rising or falling (the arrows indicate direction
of change). The HYST outputs are basically switches which
short out R31 or R32 when VIN is above the respective trip
point. Thus if the input voltage rises from a low value, the
trip point will be controlled by Rln, R2n and R3n, until the
trip point is reached. As this value is passed, the detector
changes state, R3n is shorted out, and the trip point
becomes controlled by only Rln and R2n. a lower value.
The input will then have to fall to this new point to restore
the initial comparator state, but as soon as this occurs, the
trip pOint will be raised again.

V
-V
Rll
'V
-V
R12
SETI - IN(R
R) , SET2 - IN(R
R)
11 + 21
12 + 22
Since the voltage to trip each comparator is nominally
1.3V, the value of VIN for each trip point can be found from
VTRl = VSET1

(Rl1+ R2l)
R11

= 1.3

(Rl1+ R2l)
R11

for detector 1

and
VTR2 = VSET2

(R12 + R22)
R12

=

1.3

(R12 + R22)
R12

An alternative circuit for obtaining hysteresis is shown in
Figure 7. In this configuration, the HYST pins put the extra
resistor in parallel with the upper setting resistor. The values
of the resistors differ, but the action is essentially the same.
The governing equations are given in Table 1. These ignore
the effects of the resistance of the HYST outputs, but these
can normally be neglected if the resistor values are above
'
about 100kn.

for detector 2.

Either detector may be used alone. as well as both
together. in any of the circuits shown here.
When VIN is very close to one of the trip voltages, normal
variations and noise may cause it to wander back and forth
across this level, leading to erratic output ON and OFF

5-43
Note:' All typical values have been guaranteed by characterization and are not tested.

II

ICL7665
OUT

I
I "',
I

~~

I

~ HYST1

~ SET1

I

y.

ICL781J6

HYST2 f--<

SET2

-

OUT1

OND

...

I

Au~
I
I

I
1

ON

I'

Au

VL1 VU1

1

OUT2

UND£,WOLTAGE

Rn


__------+--------+1 V,N

R,.

j-DETECTOR 2---I---DETECTOA 1 - AF029211

AF02930i

(a) Circuit Configuration
(b) Transfer Characteristics
Figure 6: Threshold Detector with Hysteresis

V,N

t--'\I\>/Ir-l HYST1

!CL781J6

t----ISET1

HYST2!c-"V\,..,.......
SET2t---...

Rn

AF02941I

Figure 7: An Alternative Hysteresis Circuit
Table 1. Set~Point Equations
c) HYSTERESIS PER FIGURE 7

a) NO HYSTERESIS

Over-Voltage VTRIP =

Rl1 + R21

Under-Voltage VTRIP =

Rll

x VSETl

VUl =
Over-Voltage VTRIP

R12 + R22
R12

b) HYSTERESIS PER FIGURE 6A

VUl =

Rll + R21 + R31

XVSETl

Rll
VL1 =

VU2 =
Under-Voltage VTRIP

Rll + R21
Rll

Under-Voltage VTRIP

XVSETl

R12 + R22 + R32

XVSET2

R12
VL2=

R12 + R22
R12

Rll

xVSETl
.

R21 R31
Rll+---Vl1 =
R21 + R31 XVSETl
Rll

x VSET2

Over-Voltage VTRIP

Rl1 + R21

XVSET2

5-44
Note: All typical values have been guaranteed by characterization and are not tested.

ICL7665
ICL7665B ADDENDUM TO THE ICL7665 DATASHEET
This Addendum to the standard ICL7665B datasheet
describes changes and/or modifications to the DC Operating characteristics applicable to the ICL7665B device. The
following table indicates those limits to which the ICL7665B
is tested and/ or guaranteed operational.

ORDERING INFORMATION
PART NUMBER

TEMPERATURE
RANGE
o to +70·C
o to +70·C

ICl7665BCPA
ICl7665BCTV
ICl7665B/D
ICl7665BCJA
ICl7665BCBA

o to +70·C
o to +70·C

PACKAGE
8 lead MiniDIP
8 lead TO-99
DICE Only
8-lead Cerdip
8-lead S.O.I.C.

ABSOLUTE MAXIMUM RATINGS, ICL7665B
Maximum Sink Output Current OUT1 and OUT2 ... 25mA
Maximum Source Output Current HYST1
and HYST2 .............................................. -25mA
Power Dissipation (Note 1) ............................. 200mW
Operating Temperature Range .................. 0 to + 70·C
Storage Temperature Range ............ - 55·C to + 125·C

Supply Voltage .................................. -0.3V to +12V
Output Voltages OUT1 and OUT2 (with respect to
GND) (Note 2) ............................... -0.3V to + 12V
Output Voltages HYST1 and HYST2 (with respect to
V+) (Note 2) ................................. +0.3V to -12V
Input Voltages SET1 and SET2
(Note 2) ..................... (GND -0.3V) to (V+ +0.3V)

Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

DC OPERATING CHAF,lACTERISTICS v+ = 5V. TA = + 25°C. unless otherwise specified.
SYMBOL

PARAMETER

TEST CONDITIONS

V+

Operating Supply Voltage

TA- +25·C
05 TA 5 +70·C

I

Supply Current

GND 5 VSET1. VSET2 5 V +
All Outputs Open Circu~
V+ ~2V
V+ ~9V

VSET1
VSET2

Input Trip Voltage

aVSET

Temperature Coefficient
of VSET

aT
aVSET
aVS
IOLK
IHLK
IOLK
IHLK
VOUT1
VOUT1
VOUT1
VHYST1
VHYST1
VHYST1
VOUT2
VOUT2
VOUT2
VHYST2
VHYST2
VHYST2

LIMITS
MIN
1.6
1.8

1.15
1.2

Supply Voltage Sensitivity
of VSET1. VSET2

ROUT1. ROUT2. RHYST1. RHYST2 ~ 1Mn

Output leakage Currents
on OUT and HYST

VSET

~

TYP

OV or VSET

<: 2V

10
10

2.5
2.6
1.3
1.3

10
10
1.45
1.4

V

%/V

10
-10

200
-100
2000
-500

~ 2V. VSET1 ~ 2V. IHYST1 ~ -0.5mA
~ 5V. VSET1 ~ 2V. IHYST1 ~ -0.5mA
~ 9V, VSET1 ~ 2V, IHYST1 ~ -0.5mA

V - 2V, VSET2 - OV, IOUT2 - 2mA
V + ~ 5V, VSET2 ~ OV, IOUT2 ~ 2mA
V + ~ 9V, VSET2 ~ OV, IOUT2 ~ 2mA

-0.15
-0.05
-0.02
0.2
0.15
0.11

0.5
0.3
0.25
-0.3
-0.15
0.15
0.5
0.3
0.3

V + - 2V, VSET2 - 2V, IHYST2 - -0.2mA
V + ~ 5V, VSET2 ~ 2V, IHYST2 = -0.5mA
V + ~ 9V, VSET2 ~ 2V, IHYST2 ~ -0.5mA

-0.25
-0.43
0.35

-0.8
-1
-1

5--45

/lA

0.004

0.2
0.1
0.06

Note: All typical values have been guaranteed by characterization and are not tested.

V

ppm/·C

~ 2V, VSET1 ~ 2V, IOUT1 ~ 2mA
~ 5V. VSET1 ~ 2V. IOUT1 ~ 2mA
~ 9V. VSET1 ~ 2V. IOUT1 ~ 2mA

V+
V+
V+
V+
V+
V+

UNITS

±200

V -9V, TA-70·C
V+ ~ 9V. TA ~ 70·C
Output Saturation Voltages

MAX

nA

V

i

i

.D~DIl

ICL7685
DC OPERATING CHARACTERISTICS (CONT.)
SYMBOL

PARAMETER

TEST CONDITIONS
.

LIMITS
MIN

TYP

MAX

UNITS

0.01
10
nA
VSET Input Laakage C\Jrrent
GNDSVSETSV
AVSET Input for Complete
ROUT = 4.7kSl, RHYST = 20kSl ,
VOUTLO = 1% v+, VOUTHI = 99% V+
Output Change
mV
±S
±SO
Difference in Trip Voltages
ROUT, RI+YST = 1 MSl
±1
Output/Hysteresis DifferEmce
NOTES: 1, Derate above ±2S"C ambIent temperature at 4mW/"C.
.
2. Due to the SC~ structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to voltages
greater than. (V + 0.3V) or less than (GND - 0.3V) may cause .destructive device latchup. For this reason, it is recommended
that no inputs from external sources not operating from the same power supply be applied to the device before its supply is
established, and that in multiple supply systems, the supply to the ICL766S8 be tumed on first. If this is not pOSSible, currents
into inputs and/or outputs must be limited to ± O.SmA and voltages must not exceed those defined above.

ISET
Il.VSET

5-46
Note: All typical values have been guaranteed by characterization and are not tested.

ICL7867
Dual Power
MOSFET Driver
GENERAL DESCRIPTION

FEATURES

The ICL7667 is a dual monolithic high-speed driver
designed to convert TIL level signals into high current
outputs at voltages up to 15V. Its high speed and 1.5A peak
current output enable it to drive large capacitive loads with
high slew rates and low propagation delays. With an output
voltage swing only millivolts less than the supply voltage
and a maximum supply voltage of 15V, the ICL7667 is well
suited for driving power MOSFETs in high frequency
switched-mode power converters. The ICL7667's high current outputs (1.5A peak) minimize power losses in the
power MOSFETs by rapidly charging and discharging the
gate capacitance. The ICL7667's inputs are TTL compatible
and can be directly driven by common pulse-width modulation control IC's.

•
•
•
•
•
•
•

1.5A Peak Output Current
Fast Rise and Fall Times
- 40.ns With 1000pF Load
Wide Supply Voltage Range
-VCC=4.5 to 15V
Low Power Consumption
- 4mW With Inputs Low
-120mW With Inputs High
TTL/CMOS Input Compatible Power Driver
-ROUT= 6n
Direct Interface· With Common PWM Control IC' s
Pin Equivalent to DS0026/DS0056; TSC426

TYPICAL APPLICATIONS
•
•
•

Switching Power Supplies
DC/DC Converters
Motor Controllers

ORDERING INFORMATION
PART
NUMBER
ICL7667MTV
ICL7667MJA
ICL7667CPA
ICL7667CJA
ICL7667CTV

TEMPERATURE
RANGE
-55°C to + 125°C

TO-99 Can

a-Pin Cerdip

....---t~>O-__1I>O--- OUT

a-Pin Plastic
a-Pin Cerdip
TO-99 Can

O°C to +70°C

-

ICL7667/D

vcc - -....- - -.....- - - - .

PACKAGE

IN-1

DICE"

"Parameter MinIMax Limits guaranteed at 25°C only for DICE orders.

80006801

Figure 1: Functional Diagram

N.C.

OUT
A

v+

8

7

8

2

3

4

N.C.

IN

v-

IN
B

v+

OUT

B

5

N.C.

N.C.

v-

A

TOP VIEW
TO·.
(TV)

TOP VIEW
8-PlN DIP
(PA. JA)

COO1961I

COO1682J

Figure 2: Pin Configurations

5-47
Note: All typical values have been guaranteed by characlerization and are not tested.

302068-002

i

.O~DIL

IC,L76e1

,

"

iABSOLUTEMAXIMUM RATINGS
Supply Voltage ................................................. 15V
Input Voltage ............................... 15V to (V- -O.3V)
Peak Output Current ......................................... 1~5A
Package Dissipation, TA = ?5·C ....................... 500mW
Linear Derating Factors
TO-99
Plastic
Cerdip
6.7mWfDC
5.6mWfDC
6.7mWfDC
above50·C
above 50'C
above 36'C

Storage Temperature ...................... -65'C to + 150'C
Operating Temperature Range
ICl:7667C .................................. O·C to +70·C
ICL7667M ........................... -55'C to, + 125'C
Lead Temperature (Soldering, 10sec) ................. 300'C

Stresses above those listed under .. Absolute Maldmum Ratings" may cause permanent damage to the device. These are stress ratings only and fUnctional
operation of the device at these or any other, cOnditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (STATIC)
Test Conditions: VCC = 4.5 to 15V, TA = + 25'C unless otherwise noted.
LIMITS
SYMBOL

PARAMETER

UNIT

TEST CONDITIONS
MIN

VIH

Logic 1 Input Voltage

TYP

MAX

2.4

V

VIL

Logic 0 Input Voltage

liN

Input Current

VOH

Output Voltage High

VOL

Output Voltage Low

No Load

0

0.05

V

ROUT

Output Resistance

VIN = VIL
lOUT'" -10mA
Vec"'15V

6

20

n.

ROUT

Output Resistance

VIN=VIH
lOUT = 10mA
Vce = 15V

6

20

n.

Icc

Power Supply Current

VIN = 3V (both inputs)

4

6

mA

Icc

Power Supply Current

VIN = OV (both inputs)

150

400

p.A

0< VIN < Vee

-1

0

No Load

Vee
-0.05

Vcc

0.8

V

1

!lA
V

ELECTRICAL CHARACTERISTICS (DYNAMIC)
Test Conditions: Vce = 15V, TA = +25'C, unless otherwise noted.
LIMITS
SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
MIN

TYP

MAX

T02

Delay Time

Figure 3

50

75

ns

TR

Rise Time

Figure 3

35

50

ns

40

55

ns

20

35

ns

TF
T01

Fall Time

Figure 3

Delay Time

Figure 3

5-48
Note: All typical values have been guaranteed by characterization and arlO not tested.

,

ICL766.7
v + = 15V
+5V

~O.'"F

INPUT

......M.__-_- . OUTPUT

"'.4V

INPUI ----+~~-o--+-

109

INPUT RISE AND
FALL TIMES 

IN4001

-13.5V

, .....

.,

-6
-8

SLOPE.,80

~ -10
::>

~

1000""

IoC"li

r-10kHz
L

-12

II!'<

r- t- .o.=ISUPPLYWI.- OUT
r- l - e, 1~kHz CLOCK RATE

-14

-:
TC025711

5

20

40

80

80

100

IOUT-mA
OP025701

Figure 9: Voltage Inverter

5-53
Note: All typical values have been guaranteed by characterization and are not tested.

i

ICL7667

!i

S!

9 shows a typical charge pump voltage inverter circuit and a
typical performance curve. A common use of this circuit is
to provide a low current negative supply for analog circuitry
or RS232 drivers. With an input voltage of + 15V, this circuit
will deliver 20mA at -12.6V. By increasing the size of the
capacitors, the current capability can be increased and the
voltage loss decreased. The practical range of the input
frequency is 500Hz to 250kHz. As the frequency goes up,
the charge pump capacitors can be made smaller, but the
internal losses in the ICL7667 will rise, reducing the circuit
efficiency.
Figure 10, a voltage doubler, is very similar in both
circuitry and performance. A potential use of Figure 8 would
be to supply the higher voltage needed for EEPROM or
EPROM programming.

TC025801

Figure 10: Voltage Doubler

OTHER APPLICATIONS
RELAY AND LAMP DRIVERS

CLOCK DRIVER

The ICL7667 is suitable for converting low power TTL or
CMOS signals into high current, high voltage outputs for
relays, lamps and other loads. Unlike many other level
translator/driver ICs, the ICL7667 will both source and sink
current. The continuous output current is limited to 200mA
by the 12R power dissipation in the output FETs.

Some microprocessors (such as the 68XX and 65XX
families) use a clock signal to control the various LSI
peripherals of the family. The ICL7667's combination of low
propagation delay, high current drive capability and wide
voltage swing make it attractive for this application. Although the ICL7667 is primarily intended for driving power
MOSFET gates at 15V, the ICL7667 also works well as a 5V
high-speed buffer. Unlike standard 4000 series CMOS, the
ICL7667 uses short channel length FETs and the ICL7667
is only slightly slower at 5V than at 15V..

CHARGE PUMP OR VOLTAGE INVERTERS AND
DOUBLERS
The low output impedance and wide Vee range of the
ICL7667 make it well suited for charge pump circuits. Figure

5-54
Note: All typical values have been guaranteed by characterization and are not tested.

ICL7673
Automatic Battery
Back-up Switch
GENERAL DESCRIPTION

FEATURES

The Intersil ICL7673 is a monolithic CMOS battery
backup circuit that offers unique performance advantages
over conventional means of switching to a backup supply.
The ICL7673 is intended as a low-cost solution for the
switching of systems between two power supplies; main
and battery backup. The main application is keep-alivebattery power switching for use iii volatile CMOS RAM
memory systems and real time clocks. In many applications
this circuit will represent a low insertion voltage loss
between the supplies and load. This circuit features. low
current consumption, wide operating voltage range, and
exceptionally low leakage between inputs. Logic outputs
are provided that can be used to indicate which supply is
connected and can also be used to increase the power
switching capability of the circuit by driving external PNP
transistors.
The ICL7673 is available in either an a-pin plastic minidip
package, a TO-99 metal can, or as dice.

•
•
•
•
•
•
•
•
•

Automatically Connects Output to The Greater
Of Either Input Supply Voltage
If Main Power to External Equipment Is Lost,
Circuit Will Automatically Connect Battery
Backup·
.
Reconnects Main Power When Restored
Logic Indicator Signaling Status Of Main Power
Low Impedance Connection Switches
Low Internal Power Consumption
Wide Supply Range: 2.5 to 15 Volts
Low Leakage Between Inputs
External Transistors May Be Added If Very
Large Currents Need to Be Switched

APPLICATIONS
•
•
•
•

On Board Battery Backup for Real·Time Clocks,
Timers, or Volatile RAMs
Over/Under Voltage Detector
Peak Voltage Detector
Other Uses:
- Portable Instruments, Portable Telephones, Line
Operated Equipment

ORDERING INFORMATION
PART NUMBER
ICl7673CPA

TEMPERATURE RANGE
ODC to +70°C

PACKAGE
B-pin minidip

ICl7673CBA

O°C to +70°C

8-pin SOIC

ICl76731TV

-25°C to + 85°C

8-pin TO-99

ICl7673/D

-

DICE ONLY"

"Parameter MinIMax Limits guaranteed at 2S"C only for DICE orders.

~o-~---------,~~~------~---------o~
~o--+~----------~----~

.--_ _oSbar

Pbar

G.Oo--------------------:.--......---l,--O
08028201

Vp > VS, P1 SWITCH ON AND Pbar SWITCH ON
Vs > Vp, P2 SWITCH ON AND Sbar SWITCH ON

Figure 1: Functional Diagram

5-55
Note: All typical values have been guaranteed by characterization and are not tested.

302070-003

~

i

10

ICL7673
ABSOLUTE MAXIMUM RATINGS
Package Dissipation ...................................... 300mW
Linear Derating Factors
TO-99
PLASTIC
S.7mWrC
6.1mWrC
above,SO'C
above 36·C
Operating 'Temperature Range:
ICL7673CPA/CBA ...................... O·C to + 70·C
"
ICL76731TV ........................... -2S·C to +85·C
Storage Temperature ...................... -6S'C to + 1S0·C
Lead Temperature (Soldering, 10sec) ................. 300·C

Input Supply (Vp or Vs) Voltage ........... -0.3 to + 18V
Output Voltages Pbar and Sbar ............. -0.3 to + 18V
'Peak Current
Input Vp (@ Vp = SV) (note 1) ................ 38rnA
Input Vs (@ Vs 3V) ............................ 30mA
Pbar or Sbar ....... ·:: .................. · .. · ........ 1S0mA
Continuous Current
'
Input Vp (@ Vp = SV) (note 1) ................ 38mA
Input Vs (@ Vs = 3V) ............................ 30mA
Pbar or Sbar ........... '........,: ..................... SOmA

=

Note 1. Derate above 25'C by O.3BmA/'C.
Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to ttie device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied, Exposure to
absolute maximum rating conditions for 'eXtended periods may affect device reliability.

Vp

GNO
CD033901

COO34001

C0036201

(Outline Dwg TV)
8-LEAD TO-99 '

(Outline Dwg BA)
8-LEAD SOle

(Outline Dwg PAl
8-LEAD Mlnidip

Figure 2: Pin Configurations

ELECTRICAL CHARACTERISTICS
SYMBOL

Vp

PARAMETER

Rds(on)Pl

TEST CONDITIONS

TYP

MAX

2.5

-

15

Vp = 0 volts
Iload=OmA

2.S

-

15

QUIESCENT SUPPLY
CURRENT

Vp= 0 volts
Vs = 3 volts
Iload=OmA

-

1.5

5

,.,A

SWITCH RES!STANCE
P1
(NOTE 2)

Vp= 5 volts
VS= 3 volts
I load = 15mA

-

8

15

n

TA = 85·C

16

-

Vp=9 volts
VS= 3 vol,ts
I load = 15mA

-

6

-

n

Vp = 12 volts
VS";3 volts
I load = 15mA

-

5

-

n

Vp = 5 volts
Vs = 3 volts
I load = 15mA

-

2.03

-

'Yorc

@

TC(P1)

UNIT

MIN

Vs=O volts
I load = OmA

INPUT VOLTAGE

Vs

,+

(TA = 2S·C unless otherwise specified)

TEMPERATURE COEFFICIENT
OF SWITCH RESISTANCE P1

5-56
Note: All typical values have been guaranteed by characterization 'and are not tasted.

V

ICL7873
ELECTRICAL CHARACTERISTICS (CONT.)
SYMBOL

PARAMETER

Rds(on)P2

SWITCH RESISTANCE
P2
(NOTE 2)

TEST CONDITIONS

MIN

TYP

MAX

UNIT

-

40

100

n

@ TA = 85°C

60

-

Vp = 0 volts
Vs = 5 volts
I load = 1mA

-

26

-

n

Vp = 0 volts
Vs = 9 volts
I load = 1mA

-

16

-

n

-

0.7

-

%fOC

0,01

20

nA

35

-

0.01

50

120

-

Vp= 0 volts
Vs = 3 volts
I load = 1mA

TC(P2)

TEMPERATURE COEFFICIENT
OF SWITCH RESISTANCE P2

Vp = 0 volts
Vs=3 volts
I load = 1mA

IL(PS)

LEAKAGE CURRENT
(Vp to Vs)

Vp = 5 volts
Vs = 3 volts
I load = 10mA
@ TA = 85°C

IL(SP)

LEAKAGE CURRENT
(Vs to Vp)

Vp - 0 volts
Vs = 3 volts
I load = 1mA
@ TA = 85°C

Vo Pbar

OPEN DRAIN OUTPUT
SATURATION VOLTAGES

Vp = 5 volts
Vs=3 volts
I sink = 3.2mA
I load = OmA

-

-

nA

85

400

-

120

-

-

50

-

mV

-

40

-

mV

-

150

400

mV

@ TA = 85°C

210

-

Vp = 0 volts
Vs = 5 volts
I sink = 3.2mA
I load = OmA

-

85

-

mV

Vp = 0 volts
Vs = 9 volts
I sink = 3.2mA
I load = OmA

-

50

-

mV

@ TA=85°C

Vp = 9 volts
Vs =3 volts
I sink = 3.2mA
I load = OmA
Vp = 12 volts
Vs = 3 volts
I sink = 3.2mA
I load = OmA
Vo Sbar

-

Vp = 0 volts
Vs = 3 volts
I sink = 3.2mA
I load =OmA

5-57

Note: All typical values have been guaranteed by characterization and are not tested.

mV

~ ICL7673

a
G

ELECTRICAL CHARACTERISTICS (CONT.)
SYMBOL

PARAMETER

TEST CONDITIONS

OUTPUT LEAKAGE
CURRENTS
OF Pbar AND Sbar

IL Pbar

MIN

TYP

50

TA '=85°C

-

Vp = 15 volts
VS=O volts
I load = OmA
TA=85°C

Vs =3 volts
I sink = 3.2mA
I load = OmA

Vp=O volts
Vs = 15 volts
Iload=OmA
@

IL Sbar

@

SWITCHOVER UNCERTAINTY
FOR COMPLETE SWITCHING
OF INPUTS AND OPEN
DRAIN OUTPUTS.

Vp - Vs

MAX

UNIT

. 500

900

-

-

50

500

-

900

-

-

5

50

nA

nA

mV

NOTE 2. The minimum input to output voltage can be determined· by multiplying the load current by the· switch resistance.

TYPICAL PERFORMANCE CHARACTERISTICS
ON-RESISTANCE SWITCH P2 AS A FUNCTION OF
INPUT VOLTAGE Vs

ON-RESISTANCE SWITCH P1 AS A FUNCTION OF
INPUT VOLTAGE Vp

100

100

ILOAO = lmA

ILOAD = 15mA
iii
2
:z:

iii
:IE
:z:

...Q:

N

'~"'
;2

'"

e

e

\

10

...
A.

'~"'

;2

--

II)

...

;;;
II:

Z

CI

o

2

4

&

8

....... ........

-

.r- r-

10

II)

...

;;;
II:

Z

CI

o

10 12 14 1&

INPUT VOLTAGE Vp (V)

4

&

8

10

INPUT VOLTAGE Vs
OP015BOI

OP015701

5-58
Note: All typical values have been guatanteed by characterization and· are not tested.

ICL7673
TYPICAL PERFORMANCE CHARACTERISTICS (CONT.)
Pbar OR Sbar SATURATION VOLTAGE AS A
FUNCTION OF OUTPUT CURRENT

SUPPLY CURRENT AS A FUNCTION OF SUPPLY
VOLTAGE

5

.....,...
...:IE

;;;

...,
..,..,...
....=

~

...

O.S

'"e
....

e

CI

0.6

>

~

V

4

J

/

3

2
CI

..,i=e

I-

2

=
e
'"
...=
=

0.4

l-

~

'"=

!Vo=9V

I-

CI

...

Vo=3V Vo=5V

0.2

IL

I-

CI

+S5jC

V
o

I-

40°C
+25°C-

2

4

6

S 10 12 14 16

2

J

V

I

~

1/

7

Vo=15V

140

ISO

OP016001

DETAILED DESCRIPTION

IS LEAKAGE CURRENT Vp to Vs AS A FUNCTION OF
INPUT VOLTAGE

As shown in the functional diagram (Figure 1),the
ICL7673 includes a comparator which senses the input
voltages Vp and VS. The output of the comparator drives
the first inverter and the open-drain N-channel transistor
Pbar. The first inverter drives a large P-channel switch, P1, a
second inverter, and another open-drain N-channel transistor, Sbar. The second inverter drives another large Pchannel switch 'P2. The ICL7673, connected to a main and
a backup power supply, will connect the supply of greater
potential to its output. The circuit provides break-beforemake .switch action as it switches from main to backup
power in the event of a main power supply failure. For
proper operation, inputs Vp and Vs must not be allowed to
float, and, the difference in the two supplies must be greater
than 50 millivolts. The leakage current through the reverse
biased parasitic diode of switch P2 is very low.

1,.-

i~1

1-

101lA

CD

C

~

/

V VV
) v.... ~'"
JV/ ~ V
~~
120
o
40
so

OP015901

..
..

1/

OUTPUT CURRENT (mAl

SUPPLY VOLTAGE (VI

•rr:......
rr:
...'"

V

Vo=I~

IlIA

OUTPUT VOLTAGE

J'J

The output operating voltage range is 2.5 to 15 volts. The
insertion loss between either input and the output is a
function of load current, input voltage, and temperature.
This is due to the P-channels being operated in their triode
region, and, the ON-resistance of the switches is a function
of output voltage Yo. The ON-resistance of the P-channels
have positive temperature coefficients, and therefore as
temperature increases the insertion loss also increases. At
low load currents the output VOltage is nearly equal to the
greater of the two inputs. The maximum voltage drop
across switch P1 or P2 is 0.5 volts, since above this voltage
the body-drain paraSitic diode will become forward biased.
Complete switching of the inputs and open-drain outputs
typically occurs in 50 microseconds.

1001lpA

IIIpA

II

I",
0

10

12

IIPUT Vp VOLTS
0P060901

5-59
Note: All typical values have been guaranteed by characterization and are not tested.

[I
.

E ICl.7673,

...S:!...

INPUT VOLTAGE
The input operating voltage range for Vp or Vs is 2.5 to
15 volts. The input supply voltage (Vp or Vs) slew rate
should be limited t02 volts per microsecond to avoid
potential harm to the circuit. In line-operated systems, the
rate-ol-rise (or fall) of the supply -is a function of power
supply design. For battery applications it may be necessary
to use a capacitor betWeen the input and ground pins to
limit the rate-ol-rise of the supply voltage. A low-impedance
capacitor such as a 0.041J.LF disc ceramic can be used to
reduce -the rate-ol-rise.

+5 VOLT o-_ _B
..... Vp
Vo ",1-1r-oVo
PRIMARY
+5 VOLTS OR
SUPPLY
ICL
+ 3 VOLTS
7673
PIlar

STATUS
INDICATOR

lITHIUM _
BATIERYGNOo-~---+-----u

TC037701

Figure 4: ICL7673 Battery Backup Circuit

STATUS INDICATOR OUTPUTS
The N-channel open drain output transistors can be used
to indicate which supply is connected, or can be used to
drive external PNP transistors to increase the power
switching capability 01 the circuit. When using external PNP
power transistors, the output current is limited by the beta
and thermal characteristics of the power transistors. The
application section details the use 01 external PNP transistors.
'

+5 VOLT o-~_ _ _ _B
..... vp
Vo 1
PRIMARY
SUPPLY
teL
7673

4

APPLICATIONS
A typical discrete battery backup circuit is illustrated in
Figure 3. This approach requires several components,
substantial printed circuit board space, and high labor cost.
It also consumes a fairly high quiescent current. The
ICL7673 battery backup circuit, illustrated in Figure 4, will
often replace such discrete designs and offer much better
performance, higher reliability, and lower system manufacturing cost. A trickle charge system could be implemented
with an additional resistor and diode as shown in Figure 5. A
complet~ low power AC to regulated DC system can be
implemented using the ICL7673 and ICL7663 micropower
voltage regulator as shown in Figure 6.
+5 VOLT

Vo

PlIIMARY
DC PDWfR

+S VOlT DR
+3 VOLT

STATUS

INDICATOR

..=. Nil:AD
BATTERY
STACK

G.Do-......--+--......-----Sk

SQUARE ROOT

7.Sk

Tying the X and Y inputs together and using overall
feedback from the Op Amp results in the square root
function. The output of the mpdulator is again forced to
eql!al the current produced by the Z input.

CD01711 I

Figure 11B: Actual Circuit Connection

Divider Trimming Procedure
1.

Set trimming potentiometers at mid-scale by
adjusting voltage on pins 7, 9 and 10 (Xos, Yos,
ZOS) for zero volts.

2.

With ZIN = OV, trim ZOS to hold the Output constant,
as X,N is varied from -10V through -1V.

3.

With ZIN = OV and X,N = -1 O.OV adjust YOS for zero
Output voltage..

4.

With ZIN = X,N (and/or ZIN = -XIN) adjust XOS for
minimum worst-case variation of Output, as X,N is
varied from -tOY to -tv.

5.

Repeat Steps 2 and 3 if Step 4 required a large initial
adjustment.

6.

With ZIN = X,N (and/orZ'N = -XIN) adjust the gain
control until the. output is the closest average around
+ 10.0V (-10V for ZIN = -X,N) as X,N is varied from
-10V to -3V.

The output is a negative voltage which maintains overall
negative feedback. A diode in series with the Op Amp
output prevents the latchup that would otherwise occur for
negative input voltages.

Z

80007121

Figure 13A: Square Root Block Diagram

SQUARING
The squaring function is achieved by simply multiplying
. with the two inputs tied together. The squaring circuit may
also be used as the basis for a frequency doubler since
.
cos2wt = 1/2 (cos 2wt + 1).

·5-69
Note: All typical values have been guaranteed by characterization' and are not tested.

TYPICAL APPLICATIONS

1*)48

OUTPUT = -

V"1ii%iN

4

GAIN

51<

7.51<

AF029511

CDO.17311

Figure 15: Multiplication

Figure 138: Actual Circuit Connection

Square Root Trimming Procedure
1.
2.

Connect the ICL8013 in the Divider configuration.
Adjust ZOS, YOS, Xos, and' Gain using Steps 1
through 6 of Divider Trimming Procedure.
3. Convert to the Square Root configuration by
connecting XIN to the Output and inserting a diode
between Pin 4 and the Outpu,t node.
4. . With ZIN = OV adjust ZOS for zero Output voltage.

Xos Yos Zos
7 1

•

X.N"'!!:~~r=-~
Z,N_---.!

GAIN~MPLIFIER
Most applications for the ICL8013 are straight forward
variations of the simple arithmetic functions described
above. Although the circuit description frequently disguises
the fact, it has already been shown that the frequency
doubler'is nothing more than a squaring circuit. Similarly the
variable gain amplifier is nothing more than a multiplier, with
the input signal applied at the X input .and the control
voltage applied at the Y input.

VARIABLE

AF029711

Figure 16: Division

y+

Xoso-- ,201<

'\f\; INPUT 0----=1
CON:':J~1'
VOLTAGE
7.5k

yAF029601

Figure 17: Potentiometers ·for Trimming
Offset and Feedthrough

Xos YosZos

AF029901

Figure 14: Variable Gain Amplifier
1*'48

OUTPUT = - v'1QZ;N

4

'--------c::G..,.AI::':N-~5I<

7.51<

AF02961[

Figure 18: Square Root

5-70
Note: All typical values have been guaranteed by characterization and are not tested.

ICL8013
TYPICAL PERFORMANCE CHARACTERISTICS
AMPLITUDE AND PHASE AS A
FUNCTION OF FREQUENCV

_

J

0

I

ID

~ 5

~

.

~,

:::> 10

~

:Ii

i......

J

~

...

I\J
II

"'20
25
lk

FEEDTHROUGH AS A FUNCTION OF
FREQUENCY

100
10

o
f.

l)

I\'~

15

NONLINEARITY AS A FUNCTION
OF FREQUENCY

X-IPT
1

Y-IN

T

~

10k
lOOk 1M 10M
FREQUENCY (Hz)

100

OP027201

lk

10k
FREQUENCY (Hz)

lOOk

OP027301

DEFINITION OF TERMS
Multiplication/Division Error: This is the basic accuracy
specification. It includes terms due to linearity, gain, and
offset errors, and is expressed as a percentage of the full
scale output.
Feedthrough: With either input at zero, the output of an
ideal multiplier should be zero regardless of the signal
applied to the other input. The output seen in a non-ideal
multiplier is known as the feedthrough.
Nonlinearity: The maximum deviation from the best straight
line constructed through the output data, expressed as a
percentage of full scale. One input is held constant and the
other swept through its nominal range. The nonlinearity is
the component of the total multiplication/division error
which cannot be trimmed out.

5-71
Note: All typical values have been guaranteed by characterization and are not tested.

10k lOOk 1M
10M
FREOUENCY (Hz)
OP027401

= ICL8038

a_ Precision Waveform
GeneratorIVoltage
Controlled Oscillator
GEN,ERAL DESCRIPTION

FEATURES

The ICL8038 Waveform Generator is a monolithic integrated circuit capable of producing high accuracy sine,
square, triangular, sawtooth and pulse waveforms with a
minimum of external components. The frequency (or repetition rate) can be selected externally from .001 Hz to more
than 300kHz using either resistors or capacitors, and
frequency modulation and sweeping can be accomplished
with an external voltage. The ICL8038 is fabricated with
advanced monolithic teChnology, using Schottky-barrier
diodes and thin film reSistors, and the output is stable over a
wide range of temperature and supply variations. These
devices may be interfaced with phase locked loop circuitry
to reduce temperature drift to less than 250ppm/oC.

•
•
•
•
•
•
•
•

Low Frequency Drift With Temperature
-250ppmrC
Simultaneous Sine, Square, and Triangle Wave
Outputs
Low Distortion -1% (Sine Wave Output)
High Linearity - 0.1 % (Triangle Wave Output)
Wide Operating Frequency Range-0.001Hz to
300kHz
Variable Duty Cycle - 2% to 98%
High Level Outputs - TTL to 28V
Easy to Use - Just A Handful of External
Components Required

ORDERING INFORMATION
PART NUMBER

STABILITY

TEMP. RANGE

PACKAGE

ICL8038CCJD

250ppm/'C typ

O'C to +70'C

CERDIP

ICL80388CJD

180ppm/'C typ

D'C to +70'C

CERDIP

ICL8038ACJD

110ppm/'C typ

O'C to +70'C

CERDIP

ICL80388MJD'

350ppml'C max

-55'C to + 125'C

CE,RDIP

ICL8038AMJD'

250ppml'C max

- 55'C to + 125'C

CERDIP

ICL8038/D

-

-

DICE"

'Add 18838 to part number if 883 processing is required.
"Parameter MinIMax Limits guaranteed at 25'C only for DICE orders,

r-----------------------~.v+

CURRENT
SOURCE

.,

SINE WAVE
ADJUST
SINE WAVE
OUT

He

TRIANGLE
OUT

c~~{

FREQUENCY
ADJUST

CURRENT
SOURCE
#2
Y-orGND

11

2 SINEWAVE
ADJUST

4
5

TIMtNG
CAPACIT()R
SQUARE WAVE
OUT

FM
BIAS

FMSWEEP
INPUT
CD017801

Boo07301

Figure 2: Pin Configuration
(Outline dwg JD)

Figure 1: Functional Diagram

5-72
Note: All typical values have been guaranteed by characterization and are not tested,

302600-002

ICL8038
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Range ............ -65°C to + 150°C
Operating Temperature Range:
8038AM, 8038BM ................. -55°C to + 125°C
8038AC, 8038BC, 8038CC .......... O°C to + 70°C
Lead Temperature (Soldering, 10sec) ................. 300°C

Supply Voltage (V- to v+) ................................ 36V
Power Dissipation(1) ...................................... 750mW
Input Voltage (any pin) .............................. V- to V +
Input Current (Pins 4 and 5) ............................ 25mA
Output Sink Current (Pins 3 and 9) ................... 25mA

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
NOTE 1: Derate ceramic package at 12.5mWI"C for ambient temperatures above tOo°C.

ELECTRICAL CHARACTERISTICS (VSUPPLY = ±10V or +20V, TA = 25°C, RL = 10kn, Test Circuit Unless
Otherwise Specified)
8038BC(BM)

8038CC
SYMBOL

UNIT
MIN

VSUPPLY
V+
v+, VISUPPLY

8038AC(AM)

GENERAL CHARACTERISTICS
TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

Supply Voltage Operating Range
Single Supply

+10

+30

+10

30

+10

30

V

Dual Supplies

±5

±IS

±S

±IS

±S

±IS

V

Supply Current (VSUPPLY = ±10V)(2)
8038AM. 8038BM
8038AC, 8038BC, 8038CC

12

20

12

15

12

15

rnA

12

20

12

20

rnA

FREQUENCY CHARACTERISTICS (all waveforms)
f max

Maximum Frequency of Oscillation

fsweep

Sweep Frequency of FM Input

100

Sweep FM Range(3)

!l.fI !l.T

100

100
10

10

35:1

35:1

35:1

FM Linearity 10:1 Ratio

0.5

0.2

0.2

Frequency Drift With Temperature(5)
8038 AC, BC, CC O'C to 70'C

250

180

110

kHz
%

ppm"C

8038 AM. BM, -SS'C to 12S'C
!l.fI!l.V

kHz

10

350

Frequency Drift With Supply Voltage
(Over Supply Voltage Range)

0.05

250
0.05

0.05

%IV

OUTPUT CHARACTERISTICS
IOLK

Square-Wave
Leakage Current (Vg = 30V)

VSAT

Saturation Voltage (ISINK = 2mA)

0.2

tr

Rise Time (RL = 4.7kn)

180

tf

Fall Time (RL = 4.7kn)

!l.D

Typical Duty Cycle Adjust (Note 6)

VTRIANGLE

Triangle/Sawtooth/Ramp
Amplitude (RTAI = 100kn)

ZOUT

1
0.2

0.30

1

0.4

0.2

180

40
2
0.33

%

0.33

XVSUPPLY

0.05

0.05

%

Output Impedance (lOUT = SmA)

200

200

200

n

THD (RS - lMn)(4)

2.0

THD

THD Adjusted (Use Figure 6)

1.5

0.2

0.22

0.2
5

0.30

ns
98

0.1

VSINE

0.33

V

Linearity

THD

0.30

2

jJA

ns

40
98

2

0.4

180

40
98

Sine-Wave
Amplitude (RSINE = 100kn)

NOTES: 2.
3.
4.
5.

1

0.5

0.22
1.5
1.0

0.2
3

0.22
1.0
0.8

RA and Rs currents not included.
VSUPPLy=20V; RA and Rs=10kn, f"'10kHz nominal; can be extended 1000 to 1. See Figures 7a and 7b.
82kn connected between pins 11 and 12, Triangle Duty Cycle set at 50%. (Use RA and Re.)
Figure 3, pins 7 and 8 connected, VSUPPLY = ±10V. See Typical Curves for T.C. vs VSUPPLY.

5-73
Note: All typical values have been guaranteed by characterization and are not tested.

xVSUPPLY
1.5

%
%

= ICL8038

a

TEST CONDITIONS
PARAMETER

MEASURE

RA

RB

RL

C1

SW1

IOkn

IOkn

IOkn

3.3nF

Closed

Sweep FM Range(l)

IOkn

10kn

IOkn

3.3nF

Open

Frequency Drift with Temperature

IOkn

IOkn

IOkn

3.3nF

Closed

Frequency at Pin 3

Frequency Drift with Supply Voltage(2)

10kn

IOkn

IOkn

3.3nF

Closed

Frequency at Pin 9

Output Amplitude:

ISine

IOkn

IOkn

IOkn

'3.3nF

Closed

Pk-Pk output at Pin 2

(Note 4)

ITriangle

IOkn

IOkn

IOkn

3.3nl;

Closed

Pk-Pk output at Pin 3
Current into Pin 9

Supply Current

Current into Pin 6
Frequency at Pin 9

Leakage Current (0ff)(3)

10kn

IOkn

3.3nF

Closed

Saturation Voltage (on)(3)

IOkn

IOkn

3.3nF

Closed

Output (low) at Pin 9

Rise and Fall Times (Note 5)

IOkn

IOkn

4.7kn

3.3nF

Closed

Waveform at Pin 9

50kn

-1.6kn

IOkn

3.3nF

Closed

Waveform at Pin 9

""25kn

50kn

IOkn

3.3nF

Closed

Waveform at Pin 9

Triangle Waveform Linearity

IOkn

IOkn

IOkn

3.3nF

Closed

Waveform at Pin 3

Total Harmonic Distortion

IOkn

IOkn

IOkn

3.3nF

Closed

Waveform at Pin 2

Duty Cycle Adiust:
(Note 5)

I MAX
'IMIN

NOTES: 1. The hi and 10 frequencies can be obtained by connecting pin 8 to pin 7 (fhi) and then connecting pin 8 to pin 6 (flo). Otherwise
apply Sweep Voltage at pin 8 (2/3 VSUPPI.Y +2V) ~ VSWEEP ~ VSUPPLY where VSUPPLY is the total supply voltage. In Figure 7b,
pin 8 should vary between 5.3V and 10V with respect to ground.
2. tOV ~ V+ ~ 30V, or ±5V ~ VSUPPLY ~ ±15V.
3. Oscillation can be halted by forcing pin 10 to + 5 volts or -5 volts.
4. Output Amplitude is tesled u"der static conditions by forcing pin I 0 to 5.0V then to - 5.0V.
5. Not tested; for design purposes only.

DEFINITION OF TERMS:
HOV

Supply Voltage (VSUPPLv). The total supply voltage from
V+ to V-

Re

10k

Supply Current. The supply current required from the
power supply to operate the device, excluding load currents
and the currents through RA and Rs.
Frequency Range. The frequency range at the square
wave output through which circuit operation is guaranteed.
Sweep FM Range. The ratio of maximum frequency to
minimum frequency which can be obtained by applying a
sweep voltage to pin a.For correct operation, the sweep
voltage should be within the range
(2/3 VSUPPLy

onn
ICLS038

Vv
RTR'

11

+ 2V) < VSWEEP < VSUPPLY

12

'\IV

2
RSINE

C.
3300pF

8211

-10V

FM Linearity. The percentage deviation from the best-fit
straight line on the control voltage versus output frequency
curve.
'
Output Amplitude. The peak-to-peak signal amplitude
appearing at the outputs.
Saturation Voltage. The output voltage at the collector of
Q23 when this transistor is turned on. It is measured for a
sink current of 2mA.
Rise and Fall Times. The time required for the square wave
output to change from 10% to 90%, or 90% to 10%, of its
final value.
Triangle Waveform Linearity. The percentage deviation
from the best-fit straight line on the rising and falling triangle
waveform.
Total Harmonic Distortion. The total harmonic distortion
at the sine-wave output.

TC026201

Figure 3: Test Circuit

5-74
Note: All typical values have been guaranteed by characterization and are not tested.

ICL8038
TYPICAL PERFORMANCE CHARACTERISTICS

10

10

30

15

15

20

25

7S

30

OPQ28901

QP028801

125

TEMPERATURE ·C

SUPPLY VOLTAGE

'UPPLY VOLTAGE

OP029001

Performance of the Square-Wave Output

aoo

1 1
IJ...
~tl~E ~
j),c!r:::;i ,... ~~c

110 I-f--

r-r-

1
lOG
c

13 OC!:::lj~

C

, -~t7

/.,

~~

25;C

I
F

50

H- f21
o
o
2

i ,

1

~jI'
r.oiI

1 1 l-

TIllE

k:: ~~!SoC

125°C

~ ~"""

12ji°C

•
•
•
LOAD RI!818TANCE-llfi

I'

.... -rl

10

2
4
8
8
LOAD CURRENT-mA

OP029101

10

OP029201

Performance of Triangle-Wave Output
10

.. 1.2

!e

r'

;f
O

1+-

f!lo.t

I:

:; 0.1

OP029501

OP029401

Performance of Sine-Wave Output
12

I

10

....
\
CI

•

,

190.

I



r--------.---+-ov+

ICL8038
10

11

10

12 2

11

r-------~--~~v+

3

12 2

c

c

c

'-----~----.....----<>V- or GND

'----~---~--___ v- orGND

12 2

11

10

LC010S01

82k

'------~---......----<> v- or GND
LC01Q701

lC010601

Figure 5: Possible Connections for the External Timing Resistors
Neither time nor frequency are dependent on supply
voltage, even though none of the voltages are regulated
inside the integrated circuit. This is due to the fact that both
currents and thresholds are direct, linear functions of the
supply voltage. and thus their effects cancel.
To minimize sine-wave distortion the 82kn resistor
between pins 11 and 12 is best made variable. With this
arrangement distortion of less than 1% is achievable. To
reduce this even further, two potentiometers can be connected as shown in Figure 6; this configuration allows a
typical reduction of sine-wave distortion close to 0.5%.

J

7

4

5

6

11

12

I

91-'-',

I

RA

5RA

The capacitor value should be chosen at the upper end
of its possible range.

11.Il

3---0"'"
1

(v+ - V-I

x~=-----'-

A similar calculation holds for RS.

RL

ICL8038

C

Rl x (v+ - V-I
(Rl + R2)

, Rs

10

For any given output frequency, there is a wide range of
RC combinatibns that will work, however certain constraints
are placed upon the magnitude of the charging current for
optimum performance. At the low end, currents of less than
1pA are undesirable because circuit leakages will contribute
significant errors at high temperatures. At higher currents
(I > 5mA), transistor betas and saturation voltages. will
contr'ibute increasingly larger errors. Optimum performance
will, therefore, be obtained with charging currents of10pA
to 1mA. If pins 7 and 8 are shorted together, the magnitude
, of the charging current due to RA can be calculated from:

v+

>RA 1kll

8

SELECTING RA, RB and C

WAVEFORM OUT LEVEL CONTROL AND
POWER SUPPLIES
The waveform generator can be operated either from a
single power-supply (10 to 30 Volts) or a dual power-supply
(±5 to ±15 Volts). With a single power-supply the a:verage
levels of the triangle and sine-wave are at exactly one-half
of the supply voltage, while the square-wave alternates
between V+ and ground. A split power supply has the
advantage that all waveforms move symmetrically about
ground.

,....

>,Ok

2f---o'\IV

>
}-

1G01eIl,

100kU

The square-wave output is not committed. A load resistor
can be connected to a different power-supply, as long as
the applied voltage remains within the breakdown capability
of the waveform generator (30V). In this way, the squarewave output can be made TTL compatible (load resistor
connected to + 5 Volts) while the waveform generator itself
is powered from a much higher voltage.

10k

V-orGND
LC010BOI

Figure 6: Connection to Achieve
Minimum Sine-Wave Distortion

5-77
Note: All typical values have been guaranteed by characterization and are not tested.

.D~D[l
(b)

V+
SWJEEP

RA

VOLTAGE

4

>-8

R.

5

RL

8

ICL8038

10.

11

::C

9~

1U1.

31---->

12

21---->
Blk
V-orGND
LC011001

Figure 7: Connections for Frequency Modulation (a) and Sweep (b)
For larger FM deviations or for frequency sweeping. the
modulating signal is applied batween the positive supply
voltage and pin 8 (Flgure 7b). In this way the entire bias for
the current sources is created by the modulating signal. and
a very large (e.g. 1000:1) sweep range is created (f = 0 at
Vsweep = 0). Cafe must be taken; however. to regulate the
supply voltage; in this configuration the charge current is no
longer a function of the supply voltage (yet the trigger
thresholds still are) and thus the frequency becomes
dependent on the supply voltage. The potential on Pin 8
may be swept down from V+ by (1/3 VSUPPLy-2V).

FREQUENCY MODULATION AND
SWEEPING
The frequency of the waveform generator is a direct
function of the DC voltage at terminal 8 (measured from
V +). By. altering this voltage. frequency modulation is
performed. For small deviations (e.g. ±10%) the modulating
signal can be applied directly to pin 8. merely providing DC
decoupling with a capacitor as shown in Figure 7a. An
eXternal resistor between pins 7 and 8 is not necessary. but
it can be used to increase input impedance from about 8kil
(pins 7 and 8 connected together). to about (R + 8kil).

APPLICATIONS
With a dual supply voltage the external capacitor on Pin
10 can be shorted to ground to halt the ICL8038 oscillation.
Figure 9 shows a FET switch. diode ANDed with an input
strobe signal to allow the output to always start on the same
slope.

The sine wave output has a relatively high output
impedance (1kil Typ). The circuit of Figure 8 provides
buffering. gain and amplitude adjustment. A simple op amp
follower could also be used.

....
,..... 7

4

R8

5

•

2~1TUOE

~
lOOk

•

1CL8038

10

=Fe

To obtain a 1000:1 Sweep Range on the ICL8038 the
voltage across external resistors RA and RS must decrease
to nearly zero. This requires that the highest voltage on
control Pin 8 exceed the voltage at the top of RA and RS by
a few hundred millivolts.

v+

The Circuit of Figure 10 achieves this by using a diode to
lower the effective supply voltage on the ICL8038. The
large resistor on pin 5 helps reduce duty cycle variations
with sweep.
.

_74~:

4.7k

11

'----

"'=
vLC011101

Figure 8: Sine Wave Output Buffer Amplifiers

5-78
Note: All typical values have been guaranteed by characterization and are not tested.

ICL8038
+15V
~IOY

RA

1[:

4

15k

RI

•

5

T

1k
Uk

15k

Uk

1 F
•

ICL8038
A ~IN.14

10

11

2

nn

!---o
INlI.

roC

-[t; --

10k

ICL8038

FREQUENCY

"Iv

OFF
1 I +15V (+10V)
ON -15V (-lOY)

-15V

.".

~

LC011201

Figure 9: Strobe-Tone Burst Generator

DISTORTION
100k

-1OY
LC011301

Figure 10: Variable Audio Oscillator,
20Hz to 20kHz

HIGH
FREQUENCY
SYMMETRY

lN753A

SOOIl

(UV)

4.7kll

lUkU

4.7kll

lGOkO

1Ull

lkO

1kU
>-.....,\N""""~-I8

LOW
FREQUENCY
SY_ETRY

•

4

ICL8038
FUNCTION GENERATOR

SINE-WAVE
OUTPUT

'2

10

11

12

~

3

t--il-'-+--+------t
SO.F
15V

1UkO

100kU

OFFSET
3,1OOpF

SINE-WAVE
DISTORTION

' - - - + _ - -......- -......- - - - - _ - - - - - -_ _ -15V
WF015101

Figure 11: Linear Voltage Controlled Oscillator
The linearity of input sweep voltage versus output frequency can be significantly improved by using an op amp as
shown in Figure 11.

voltage will not exceed the capabilities of the phase
detector. If a smaller VCO signal is required, a simple
resistive voltage divider is connected between pin 9 of the
waveform generator and the VCO input of the phasedetector.

USE IN PHASE-LOCKED LOOPS
Its high frequency stability makes the ICL8038 an ideal
building block for a phase-locked loop as shown in Figure
12. In this application the remaining functional blocks, the
phase-detector and the amplifier, can be formed by a
number of available IC's (e.g. MC4344, NE562, HA2800,
HA2820)

Second, the DC output level of the amplifier must be
made compatible to the DC level required at the FM input of
the waveform generator (pin 8, O.8V +). The simplest
solution here is to provide a voltage divider to V+ (R1, R2
as shown) if the amplifier has a lower output level, or to
ground if its level is higher. The divider can be made part of
the low-pass filter.

In order to match these building blocks to each other, two
steps must be taken. First, two different supply voltages are
used and the square wave output is returned to the supply
of the phase detector. This assures that the VCO input

This application not only provides for a free-running
frequency with very low temperature drift, but it also has the
5-79

Note: All typical values have been guaranteed by characterization and are not tested,

ICL8038
unique feature of producing a large reconstituted sinewave
signal with a frequency identical to that at the input.

For further information, see Intersi! Application Note
A013, "Everything You Always Wanted to Know About The
lel8038.',
y++
DUTY

R,

/,

FMalM
0--

y+

7

'
•

~CVCLE

V

FREOUINCY~

ADJUST

'.

TRIANGLE

5

• 3f--o ¥V
OUT

SQUARE
WAVE

SINE WAVE

OUT
laMa

OUT.
INPUT

-

¥CO
IN
PHA8E~CTDR

t--

AMPLIFIER

DEMODULATED

I

FM

FM

SWEEP

INPUT
liz

II

~
LOW-PASS
FILTER

•

1
10

11

I~::'~

'V\,

2 -..:..

12

/,

-

liNE WAVE
ADJ.

~ ~':.:
ADJ.
V7GND

Figure 12: Waveform Generator Used as Stable

veo

WF01520t

in a Phase-Locked Loop

.--+---I::..'Q10

!o·M
i I~'
1

0.3

l'R. ....~...
I '00 'OOl'OO!

I

I

~

~ ~

I

1"

SINE·CONVERTEA
OS018601

Figure 13: Detailed Schematic

5-80
Note: All typical values have been guaranteed by characterization and are not tested.

ICL8069
Low Voltage Reference
GENERAL DESCRIPTION

FEATURES

The ICL8069 is a 1.2V temperature compensated voltage
reference. It uses the band-gap principle to achieve excellent stability and low noise at reverse currents down to
50pA. Applications include analog-to-digital converters, digital-to-analog converters, threshold detectors, and voltage
regulators. Its low power consumption makes it especially
suitable for battery operated equipment.

•
•
•
•
•

Temperature Coefficient Guaranteed
to 25ppmrC Max
Low Bias Current - SOMA Min
Low Dynamic Impedance
Low Reverse Voltage
Low Cost

ORDERING INFORMATION
ORDER PIN
TO-92

ORDER PIN
TO-52

TEMPERATURE
RANGE

ICL8069CCZR

ICL8069CCSQ

O°C to + 70°C .

MAX. TEMP_ COEFF.
OF VREF
O.OO5%I"C

-

ICL8069CMSQ

-55°C to + 125°C

O.OO5%I"C

ICL8089DCZR

ICL8069DCSQ

O°C to +70°C

O.01%I"C

-

ICL8069DMSQ

-55°C to +125°C

O.01%I"C

-

ICL8069/D

-

DICE'-

• 'Parameter MinIMax Limits guaranteed at 25°C only for DICE orders.

---~--~y

1511l!

1.lIln

r-----

. .7",-*

: ICLIOII t

ICL7107

"'1OVout
IC.....

10kU

---01
. .!_-......_____~.

YOUT

·"""'1

'.2kn
DS025601

1

'--~_-I

05025801

06025701

(a) Simple Reference (1.2 volts or
less)

(b) Buffered 10V Reference using a
single supply.

... LO

(c) Double regulated 100mV reference
for ICL7107 one-chlp DPM circuit.

Figure 1: Functional Diagrams

PC004501

PC00460'

TO-52

TO-92

Figure 2: Pin Configurations

5-81
Note: All typical values have been guaranteed by characterization and are not tested.

303120-002

8 ICL8069
'( ,',',' ,;,
:d ABSduJTe MAXIMUM
GI

'.-

RATINGS
Storage Temperature ......•........•...... - 65°C to, + 150,oC
Operating Temperature
.'
""
ICL8069C .. , .............................. O°C to + 70°C
ICL8069M ........................•.. -55°C to + 125°C
Lead Temperature (Soldering, 10sec) ..... , ........... 300°C

Reverse Voltage .................................. , .. See Note 2
Forward Current ............................................. 10mA
Reverse Current ...................•........... : ....'......... 10mA
Power Dissipation .................. Limited by max forward/
reverse current

NOTE: Stresses above those listed under" Absolute Maximum Ratings" may cause permanent device failure. These are stress ratings only and functional
operation of the devices at these or any other conditions above those indicated in the operati,on sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may cause device failures:
'

ELECTRICAL CHARACTERISTICS
CHARACTERiSTICS

(TA =

25°C unless otherwise noted)

TEST CONDITIONS

Reverse breakdown Voltage

IR =,500f./A

Reverse', breakdown
Voltage change

MIN

TYP

MAX

UNITS

1.20

1.23

1.2S

V

SOf./A $ IR $ SmA

lS

20

mV

Reverse dynamic impedance

IR = 50f./A
IR = SOOf./A

1
1

2
2

n

1

--

Forw~rd Voltage Drop

IF = SOOf./A

0.7

RMS Noise Voltage

10Hz$ f $ 10kHz
IR = SOOjJ.A

S

jJ.V

Long Term Stability

IR =4.7SmA
TA = 2SoC

1

ppm/kHR

V

Breakdown voltage
Temperature coefficient
IR = SOOf./A
TA = operating
Temperature range
(Note 3)

ICLB069C
ICLB069D'

%I"C
.OOS
.01

Reverse Current Rimge

O.OSO

S

mA

TYPICAL PERFORMANCE CHARACTERISTICS
REVERSE VOLTAGE AS A
FUNCTION OF CURRENT

VOLTAGE CHANGE AS A
FUNCTION OF REVERSE CURRENT

REVERSE VOLTAGE AS A FUNCTION
OF TEMPERATURE

,.....

,.

1.245

I

//

~:2S0C.

·'2S·C

~
100.......
1m"
REYEASE CURRENT

10m"

·'v
.2

E

!

I
I

-55°CL__

~>

...
.""

..,.""'" t::: ~.,.
.•

.J

1.0

1.230

1.225

~

r--'"

1.2aG
1.215

1.2

1.4

REVEASE VOLT AQE (V)
OP056301

OP056201

1.235

0

" v.::f
.Ar'l

.4

,.I""'~A

,....

I

--50

-25
0
+25 +50 ... 75 ... 100 +125
TEMPERATURE C-C)
OP056401

Notes:
1)" circuit strays in excess of 200pF a[9 anticipated, a 4,7p.F shunt capacitor will ensure stability under all operating conditions,
2) In normal use, the reverse voltage cannot exceed the reference voltage, However when plugging units into a powered·up test fixture, an instantaneous
voltage equal to the compliance of the test circuit will be seen, This should not exceed, 20V,
3) For the military part, measurements are made at 25"C, - 55"C, and + 125"C, The unit is then classified as a function of the worst case T.C. from 25"C to
-55"C, or 25"C to + 125"C.

5-a2
Note: All typical values have been guaranteed by characterization and are not tested.

ICL8211/ICL8212
Programmable Voltage Detector
GENERAL DESCRIPTION

FEATURES

The IntersillCl8211 18212 are micropower bipolar mono·
lithic integrated circuits intended primarily for precise volt·
age detection and generation. These circuits consist of an
accurate voltage reference, a comparator and a pair of
output buffer1drivers.
Specifically, the ICl8211 provides a 7mA current limited
output sink when the voltage applied to the 'THRESHOLD'
terminal is less than 1.15 volts (the internal reference). The
ICl8212 requires a voltage in excess of 1.15 volts to switch
its output on (no current limit). Both devices have a low
current output (HYSTERESIS) which is switched on for
input voltages in excess of 1.15V. The HYSTERESIS output
may be used to provide positive and noise free output
switching using a simple feedback network.

•
•
•
•
•
•

APPLICATIONS
•
•
•

ORDERING INFORMATION
PART NUMBER
ICl8211CPA
ICL8211CBA
ICl8211CTY
ICl8211 MTY*
ICl8212CPA
ICl8212CBA
ICl8212CTY
ICl8212MTY*
ICL8211/D
ICl8212/D

TEMPERATURE
RANGE
O°C to +70°C
O°C to +70°C
O°C to+70°C
-55°C to+ 125°C
O°C to +70°C
O°C to +70°C
O°C to +70°C
-55°C to+ 125°C

-

High Accuracy Voltage Sensing and Generation:
Internal Reference 1.15 Volts Typical
I.ow Sensitivity to Supply Voltage and
Temperature Variations
Wide Supply Voltage Range: Typ. 1.8 to 30 Volts
Essentially Constant Supply Current Over Full
Supply Voltage Range
Easy to Set Hysteresis Voltage Range
Defined Output Current limit -ICL8211
High Output Current Capability -ICL8212

•
•
•

PACKAGE

Low Voltage Sensor/Indicator
High Voltage Sensor/lndlcator
Non Volatile Out-of-Voltage Range Sensor/
Indicator
Programmable Voltage Reference or Zener Diode
Series or Shunt Power Supply Regulator
Fixed Value Constant Current Source

8 lead Mini DIP
8 lead SOIC
TO·99 Can
TO·99 Can
8 lead Mini DIP
8 lead SOIC
TO·99 Can
TO·99 Can
DICE ••
DICE ••

• Add 18838 to part number if 8838 processing is required .
• 'Parameter MinIMax Limits guaranteed at 25°C only for DICE orders.

VOLTAGE REFEMHCE COMPARATOR OUTPUT BUFFERS

HYSTERESIS

8 v+
~r-"""'"1-""'----1r---"1'-"'-~--_'_ _.:.0

HlCO.·

HYSTERESIS 2

lIS

UIcll

'--_---4_ _..:2'" HYST

v+

7 NIC

THRESHOLO

N/C

OUTPUT 4

OUTPUT 2

5 GROUND

4

GROUND

(outline dINg

PAl

(OUIlin. dINg lV)
CD018601

THRESHOLO

I
I
,,)

;-•

L/"Q20 <" R8
~

,
I

.

~10C1111l
CD036001

•

: :

(outline dwg BA)

08019701

Fi ure 1: Functional Dla ram

Fi ure 2: Pin Confi urations
5-83

Note: All typical values have been guaranteed by characterization and are not tested.

303200-002

(II

=
d

ICL8211/ICL8212

ABS()LUtE MAXIMUM' RATINGS

~

;:
(II
rl_CIO

....

Power Dissipation (Note 1 &2) ........................ 300mW
Operating Temperature Range: .
ICL8211 M/8212M ................. -55·C to +125·C
ICL8211 C/8212C ....................... O·C to + 70·C
Storage Temperature Range ............ -65·C to + 150·C
Lead Temperature (Soldering, 10sec) ........·......... 3dO·C

Supply Voltage .............................. -0.5 to + 30 volts
Output Voltage .............................. -0.5 to + 30 volts
Hysteresis Voltage .................... " .... + 0.5 to -10 volts
Threshold Input Voltage ••••• , ..•.•• :: •.•. , ••..........•••.••••••..
+ 30 to ...:5 volts with respect to GROUND. and + 0
to -30 volts with respect to V+
Current into Any Terminal .............................. ±30mA

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and fu~ctional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may. affect device reliability.
.
NOTE 1: Rating applies for case temperatures to 125·C to ICL8211MTY/8212MTY products. Derate lineariy at' -10mW/·C for ambient temperatures above
100·C.
.
NOTE 2: Derate linearly above 50·C by -10mW/·C for ICL8211C/8212C products. The threshold input voltage may exceed +7 vdlts for short periods of
time. However for continuous operation this voltage must be maintained at a value less than 7 volts.

ELECTRICAL CHARACTERISTICS

(V+ = 5V, TA = 25·C unless otherwise specified)
ICL8211

SYMBOL

1+

PARAMETER

Supply Current

,

VTH

Threshold Trip Voltage

VTHP

Threshold Voltage Disparity
Between Output & Hysteresis
Output

2.0 < v+ < 30
VT = 1.3V
VT=0.9V
lOUT = 4mA
VOUT=2V

V+ -5V
V+ =2V
V+ = 30V

VSUPPlY

Guaranteed Operating Supply
Voltage Range (Note 5)

IOUT=4mA
VOUT = 2V
IHYST=: 7pA
VHYST= 3V
+25·C
o to +70·C
-55·C to + 12S·C

VSUPPlY

Typical Operating Supply
Voltage Range

+2S·C
+ 125°C
-55·C

t!NTH/LlT

Threshold Voltage
Temperature Coefficient

lOUT = 4mA
VOUT=2V
LlV+ = 10% at V+ = 5V

Threshold Input Current

VTH = 1.15V
VTH = 1.00V

IOlK

Output Leakage Current

VOUT= 30V
VOUT= 30V
VOUT=5V
V VOUT= 5V

VSAT

Output Saturation Voltage

ITH

IOH

Max Available Output Current

TYP

MAX

MIN

TYP

MAX

10
50

22
140

40
250

50
10

110
20

250
40

pA
pA

0.98
0.98
1.00

1.15
1.145
1.165

1.19
1.19
1.20

1.00
1.00
1.05

1.15
1.145
1.165

1.19
1.19
1.20

V
V
V

-8.0
30
30
30

2.0
2.2
2.8

30
30
30

V
V
V

1.8
1.4
2.5

30
30
30

1.8
1.4
2.5

30
30
30

V
V
V

V+ = 10V
VHYST= V-

VHYS (max)

Hysteresis Sat Voltage

IHYST = -7pA
VTH = 1.3V
measured with respect to V +

IHYS (max)

Max Available Hysteresis Current

4

VTH = 1.3V

1.0

nA
nA

10

10

1

1

pA
pA
pA
pA

0.4

7.0

12
15

100
5

0.17
15
12

-15

-21

-0.2

-0.1
-15

0.4

-21

V
V
mA
mA
mA

35

0.1
-0.1

mV
250

250

0.17

VTH = 1.0V

ppm/·C

+200

1.0
100
5

VTH = 1.0V
VTH = 1.3V
VTH=I.0V
VTH = 1.3V

VTH = 1.0V
VTH = 1.3V
lOUT = 4mA
(Note 3 & 4)
VTH = 1.0V
VTH = 1.3V
VOUT=5V
-55·C S TA S 125·C VTH = 1.0V

mV

-0.5

2.0
2.2
2.8

.'

Hysteresis Leakage Current

IlHYS

UNIT
MIN

+200

Variation of Threshold Voltage
with Supply Voltage

LlVTH/LlV+

ICL8212

TEST CONDITIONS

0.1

pA

-0.2

V
/J A

NOTES: 3. The maximum output current of the ICL8211 is limited by design to 15mA 'under any operating conditions. The output voltage may
be sustained at any voltage up to + 30V as long as the maximum power dissip.ation of the device is not exceeded.
4. The maximum output current of the ICL8212 is not defined, and systems using the ICL8212 must therefore ensure that the output
current does not exceed 30mA and that the maximum power diSSipation of the device is not exceeded.
5. Threshold Trip -Voltage is 0.80V(min) to 1.30V(max).

5-84

Note: All typical values have been guaranteed by characterization and are not tested.

.D~D[6

ICL8211/ICL8212

TYPICAL PERFORMANCE CHARACTERISTICS COMMON TO ICL8211 AND ICL8212
THRESHOLD INPUT CURRENT AS A FUNCTION OF
THRESHOLD VOLTAGE

HYSTERESIS OUTPUT SATURATION CURRENT AS
A FUNCTION OF TEMPERATURE

c~

10.000
TA 25'C
V' -10V
1.000

-

V' "5V
V'H "1.2V
VHYS "4.5V

I.

1

(or ~.5V wllh
respecllo V' supply)

::>-10

.

U

,-20

100

50-25

./

!-3O

J

10
0.0 1.1 1.15 1.2 2.0 3.0 '.0 1.0 10.0
THRESHOLD VOLTAGE - VrH
(IRREGULAR SCALE)

m
~

-

.,... -20

ICLr"

i

r ICi212

f--

0 +20 +40 +10 +10
TEMPERATURE'C
OP032901

QP032801

TYPICAL PERFORMANCE CHARACTERISTICS ICL8211 ONLY
SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE

SUPPLY CURRENT AS A FUNCTION
OF THRESHOLD VOLTAGE
150

~.VTH=O.IV.i±
TA=:ls,C I
I

- r-.....

f- OUTPUTS jPEN CIRCUIT

,

10
20
SUPPLY VOLTAGE

0.0

30

TA=25'C
V· =5V
Vo = O.5V

1CL8211

o

I

VHVS = V+ -()..25V

i •

~
I I
8 • r-l
f.LJUTPUT
OU+~ 1\
~: I II-.l..vI
I -r-I

HYSTERESIS

I
I

~.12

1.13 1.14 1.15 1.1. 1.17
THRESHOLD VOLTAGE

!!i25t-+-6..r-=!--l--I

1.0 1.1 1.15 1.2 2.0 4.0
THRESHOLD VOLTAGE· VTH
(IRREGULAR SCALE)

0P033001

'"
-25

+5 +35 +65 +95 +125
TEMPERATURE 'c
OP033201

QPQ33101

OUTPUT SATURATION CURRENTS
AS A FUNCTION OF THRESHOLD
VOLTAGE

I

..

§ 75
~

........

"VTH = 1.3V

12

rr::t::::=+=::LT-'

U50t-+-::-~±-;-t...,

Ict'1

f_'O

150

~'25

~ 100

IhL8J,-

o

SUPPLY CURRENT AS A FUNCTION
OF TEMPERATURE

I

TA=25'C
V'=5V
\~PUTSOPEN
CIRCUIT

l..

THRESHOLD VOLTAGE TO TURN
OUTPUTS "JUST ON" AS A
FUNCTION OF TEMPERATURE

-loB

~

-15~

9 1.14 "'--+-1l-7oOUTPUT

lC01410l

r------------~~V·

Figure 10: Low Voltage Battery Indicator

S

~----------~~vo

"'OFF

I

LC014DOI

~

Low trip voltage
RQRS
[
+ RP] x -.:.. x 1.15 volts
VTR1 = (RQ+Rs)
Rp

SCOO6301

High trip voltage
VTR2
.

=

(Rp+RQ)

.

Rp

!:~rr~
!:l

•
:VTRl

Figure 11: Low Voltage Detector
and Memory

.x 1.15 volts

s
::I

ON

!:!

I

:YTR2

r-----------~~~--------------~~V·

E

ON ..

. ~

~

OFF~

a

SUPPLY VOLTAGE
SCOO6201

05019801

Figure 9: Two alternative voltage
detection circuits employing
hysteresis to provide pairs of
well defined trip voltages.

Figure 12: Schematic of Recorder

5-.90

Note: All typical values have been guaranteed by characterization and are not testEld.

e......

ICL8211/ICL8212

to)

A simple circuit to record an out of range voltage
excursion may be constructed using an ICL8211, an
ICL8212 plus a few resistors. This circuit will operate to 30
volts without exceeding the maximum ratings of the I.C.'s.
The two voltage limits defining the in range supply voltage
may be set to any value between 2.0 and 30 volts.

--v:

OUTPUT ICL8212

OUTPUT ICUI211
AS PER FIGURE.

.VNOM

OFF

n
I»

...
to)

~ ~

==

OUTPUT ICI.8211
ICUI212 DISCONNECTED

.......

to)

1= 25"A (ICL82121
1= 130"A (ICL82111

-

ON
SUPPLY YOLTAGE

AF030S01

SUPPLY VOLTAGE

Figure 14: Constant Current
Source Applications

SC006401

Figure 13: Output States of the
ICL8211 and ICL8212 as a
Function of the Supply Voltage
Referring to Figure 12, the ICL8212 is used to detect a
voltage, V2, which is the upper voltage limit to the operating
voltage range. The ICL8211 detects the lower voltage limit
of the operating voltage range, V 1. Hysteresis is used with
the ICL8211 so that the output can be stable in either state
over the operating voltage range VI to V2 by making V3the upper trip point of the ICL8211 much higher in voltage
than V2.
The output of the ICL8212 is used to force the output of
the ICL8211 into the ON state above V2. Thus there is no
value of the supply voltage that will result in the output of
the ICL8211 changing from the ON state to the OFF state.
This may be achieved only by shorting out R3 for values of
supply voltage between VI and V2.
d) Constant Current Sources
The ICL8212 may be used as a constant current source
of value of approximately 251lA by connecting the
THRESHOLD terminal to GROUND. Similarly the ICL8211
will provide a 1301lA constant current source. The equivalent parallel resistance is in the tens of megohms over the
supply voltage range of 2 to 30 volts. These constant
current sources may be used to provide biasing for various
circuitry including differential amplifiers and. comparators.
See Typical Operating Characteristics for complete information.
e) Zener or Precision Voltage Reference
The ICL8212 may be used to simulate a zener diode by
connecting the OUTPUT terminal to the Vz output and
using a resistor network connected to the THRESHOLD
terminal to program the zener voltage

TA = 25"C

v'

~4

Is

~V'

~ 3

..iii
II:

2

N

o

ttl

8';,~

50IIk

VTH

~

OUT

Ktri~1

0.01

0.1

15111<

r- ... ,.;..ot
R,

a:

R,

z
5JAF~

W

I
I .111
1.0

1I11
10

100

SUPPLY CURRENT -I (mal
OP034801

Figure 15: Programmable Zener
or Voltage Reference

Y·o--------.......- ___

YOUT

(Rl +R2)
(Vzener = - - - x 1.15 volts).
Rl
Since there is no internal compensation in the ICL8212 it
is necessary to use a large capacitor across the output to
prevent oscillation.
Zener voltages from 2 to 30 volts may be programmed
and typical impedance values between 3001lA and 25mA
will range from 4 to 7n. The knee is sharper and occurs at a
significantly lower current than other similar devices available.

=

R.;, R, x 1.15 YOLTS
LC014201

Figure 16: Simple Voltage Regulator
f)

Precision Voltage Regulators

The ICL8212 may be used as the controller for a highly
stable series voltage regulator. The output voltage is simply
programmed, using a resistor divider network Rl and R2.
Two capacitors C1 and C2 are required to ensure stability
since the ICL8212 is uncompensated internally.

5-91
Note: All typical values have been guaranteed by characterization and are not tested.

.. ICL821111,CL8212
a
-.... Y·-....------.--,
a
CIt
CIt

any commercial regulator. Applications would therefore
include battery operated equipment especially those operating at low voltages .
g) High supply voltage .dump circuit
. In many circuit applications it is desirable to remove the
power supply in the case of high voltage overload. For
circuits consuming less than 5mAthis may be achieved
using an ICL8211 driving the load directly. For higher load
currents it is necessary to use an external pnp transistor or
darlington pair driven by the output of the ICL8211. Resistors R1 and R2 set up the disconnect voltage and R3
provides optional voltage hysteresis if so desired.
h) Frequency limit detectors
Simple frequency limit detectors providing a GO/NO-GO
output for use with varying amplitude input signals may be
conveniently implemented with the ICL8211/8212. In the
application shown, the first ICL8212 is used as a zero
crossing detector. The output circuit consisting of R3, R4
and C2 results in a slow output positive ramp. The negative
range is much faster than the positive range. R5 and R6
provide hysteresis so that under all circumstances the
second ICL8212 is turned on for sufficient time to discharge
C3. The time constant of R7 C3 is much greater than R4 C2.
Depending upon the desired output polarities for low and
high input frequencies, either an ICL8211 or an ICL8212
may be used as the output driver.
This circuit is sensitive to supply voltage variations and
should be used with a stabilized power supply. At very low
frequencies the output will switch at the input frequency.

CIt

r-----A3
'

:

L.~""'\/\r

,..------

: R3
L-"v"vAV'

b
LC014301

Figure 17: High Voltage Dump Circuits
This regulator may be used with lower input voltages than
.most other commercially available regulators and also
consumes less power for a given output control current than

Y·-~------~~-------------~~~----------~

C,

INPUT

lis'

0-\1+-.....---1

L------+-4---oOUTPUT
TIME CONSTANT R3 C2 '" R. C2 ,; R7 C3
VARY R, FOR OPTION ZERO CROSSING DETECTION
YARY R4 TO SET DETECTION FREQUENCY

INPUT

---iINDETERMINATE
BELOW I.

----;r---"r---+-~

OFF

1;::
.. Ill

~~

1.15Y·
B

-+t+---,-----+-Hf---

5

ON

r

~

(

t.

I
I
I

FREQUENCY_
SC006501

Figure 18: Frequency Limit Detector

5-92
Note: All typical values have been guaranteed by characterization and are oot tlilsted ..

n

ICL8211/ICL8212
i)

i......

Switch bounce filter

Single pole single throw (SPST) switches are less costly
and more available than single pole double throw (SPDT)
switches. SPST switches range from push button and slide
types to calculator keyboards. A major problem with the use
of switches is the mechanical bounce of the electrical
contacts on closure. Contact bounce times can range from
a fraction of a millisecond to several tens of milliseconds
depending upon the switch type. During this contact bounce
time the switch may make and break contact several times.
The circuit shown in Figure 19 provides a rapid charge up of
C1 to close to the positive supply voltage (V +) on a switch
closure and a corresponding slow discharge of C1 on a
switch break. By proportioning the time constant of R1 C1 to
approximately the manufacturer's bounce time the output
as terminal #4 of the ICL8211/8212 will be a single
transition of state per desired switch closure.
j)
Low voltage power disconnector

SWITCH OUTPU OUTPUT
Rl

CLOSE
OPEN

HI
LO

LO
HI

~--------~~~vo

LC014601

Figure 19: Switch Bounce Filter

There are some classes of circuits that require the power
supply to be disconnected if the power supply voltage falls
below a certain value. As an example, the National LM199
precision reference has an on chip heater which malfunctions with supply voltages below 9 volts causing an excessive device temperature. The ICL8212 may be used to
detect a power supply voltage of 9 volts and turn the power
supply off to the LM199 heater section below that voltage.
LC014401

For further applications, see A027 "Power Supply Design
using the ICL8211 and ICL8212" by D. Watson.

Figure 20: Low Voltage Power
Supply Disconnect

5-93
Note: All typical values have been guaranteed by characterization and are not tested.

-2
...N
N

! IHS11'O....IH5115
I General Purpose Sample & Hold

~

;;

i

GENERAL DESCRIPTION

D~Ult.

FEATURES

Each of the ,5110 family is a complete Sample and Hold
pircuit, (except for sampling capacitor) including input buffer
amplifier, output buffer amplifier and CMOS switching logic.
The devices are designed to operate from ±15V and + 5V
supplies. The input logic is designed to "Sample" and
"Hold" from standard TIL logic levels.
The design is such that the input and output buffering is
performed with only one operational amplifier, by switching
the sampling capacitor from the output back to input.
Switches 01, 02, and 03 (see Figure 1) accomplish this
switching. In the sampling mode 01 and 03 are shorted and
02 is open; thus the op. amp. charges up the sampling
capacitor. In the hold mode 01 and 03 are open and 02 is
shorted; thus the sampling cap. is switched back to the
noninverting input of the op. amp.
This structure provides a very accurate d.c. gain of 1 with
very fast settling times (i.e. 5#lS). Additionally the design has
internal feedback to cancel charge injection effects (sample
to hold offsets). 01 and 02 are driven 180 degrees out of
phase to accompli~h this charge nUlling.

'. Low Cost
• Military and Industrial Temperature Ranges
• ±10V Input Voltage R"nge
• O.SmVlSec Drift Typical @ Cs 0.01/lF
• TIL and CMOS Compatible
• Short Circuit Protected
• Input Offset Voltage Adjustable to < 100/lV USing
A 20kn Potentiometer
• 0.1% Guaranteed Sample Accuracy With 10V
Signals and Cs 0.01/lF
• Sample to Hold Offset Is SmV Max

=

=

ORDERING INFORMATION
IHSll0

M

JE

~

package'

JE = 16 pin CERDIP
DE = 16 pin ceramic DIP (special order
only)

Temperature Range
M = Military (- SS·C to + 12S·C)
I = Industrial (- 20·C to + 8S·C)
' - - - - - - - B a 8 i c Part Number

(outline dwg DE, JE)
COO27801

00024101

Figure 1: Functional Diagram

Figure 2: Pin Configuration

5-94
Note: All typical values have been guaranteed by characterization and are not tested.

-002

ien

IH5110-IH5115

......

ABSOLUTE MAXIMUM RATINGS
Supply Voltages .............................................. ±16V
Power Dissipation ......................................... 500mW
Operating Temperature ....................... -25°C to 85°C
-55°C to 125°C

ELECTRICAL CHARACTERISTICS
SYMBOL

Storage Tlilmperature Range ............... -65°C to 150°C
Lead Temperature (Soldering, 10sec) ................. 300°C

(TA = 25°C, Pin 7 = 5V, Pin 8 = GND, Pin 9 = -15V, Pin 11

--IH5110, 51"12, 5114
--

CHARACTERISTIC
MiN

= 15V) Note 3

IH5111, 5113, 5115
UNIT

TVI'

MAX

MIN

TYP

MAX

Close

Aperture Time

120

tacq.

Acquisition Time for Max Analog Voltage Step
Cs = O.Ij.lF (0.1 % Aceur.)
Cs = O.Olj.lF (0.1 % Accur.)
Cs = O.OOIj.lF (0.1 % Accur.)
See Figure 5

25
4
4

35
6
6

25
4
4

35
6

0.3
0.5

2.5
5
10

0.3
0.5
2.0

2.5
5
10

mV/s

5
5
25

<1
<1
12

5
5
25

mVp-p

12

0.1
0.1
0.2

0.5
0.5
0.5

0.1
0.1
0.2

0.5
0.5
0.5

Vdrift

Vinject

Vswttch

Drift Rate
Cs = O.Ij.lF
Cs = O.OIj.lF
Cs = O.OOIj.lF

See Figure 3

2.0

Charge Injection or Sample to Hold Offsets
Cs = O.Ij.lF
Cs = O.OIj.lF
Cs = O.OOIj.lF
See Note '1 & Figure 4

<1
<1

Switching Transients or Spikes
(Duration Less than 2j.ls)
Cs = O.Ij.lF
Cs = O.OIj.lF
Cs =O.OOIj.lF

See Figure 4

Vcouple

A. C. Feedthrough Coupled to Output

Vollset

D.C. Offset When in
Sample Mode Trimmable
to Om V With Ext. 20k!1
Potentiometer

-

.-

5110
5111

Ain

Input Impedance in Hold or Sample
Mode (f '" 1OHz)

It15V

Plus or Minus 15V Supply
Quiescent Current

15V

5V Supply Quiescent Current

Vanalog

D.C. Input Voltage Range

D.VIN

A.C. Inpul Voltage Range
See Note 2 & Figure 6

Istrobe

TTL Logic Strobe Input Current in
Either Hold or Sample Mode

5

ns
j.lS

6

5

V

mVp-p

40
40

--L

5112
5113
See Figure 3

200

10

I

mV
10

5114
5115

5
5
---'100

100

3.4

-- ----0.3
--

6

3.4

10

0.3

.,..,_...

6

rnA

10

A

..
±7.5

±10
20

15

....

M!1

0.1

10

V

0.1

10

IlA

NOTES: 1. Offset voltage of op. amp. must be adjusted to OmV (using 20kfl potentiometer) before charge injection is measured.
2. The A.C. input voltage range differs from the D.C. input VOltage range. All versions will handle any analog input within the range of
plus 10V to minus 10V; however the IH5110, 5112, 5114 has the added restriction that the peak to peak swing should be less than
15Vp-p i.e. ±l.5 Vac.
'.
3. All of the ·electric.al chara~'1eristics specs, are guaranteed with Cs = O.OIj.lF in series with loon as per Figure 3, Os = O.Ij.lF &
Cs = a.OOI jJF are for design aid only.
4. If supplies are reduced to ± 12VDC, analog signal range will be reduced to ± 7Vp-p.

5-95
Note: All typical values have been guaranteed by characterization and are not tested.

fi

......

en
en

..; IH5110-IH5115
I..
10

:z: APPLICATIONS INFORMATION
10

!

1.

N.C.

IH5110
THRU
IH5115
3V

N.C.

ov.-r-L..

S & H OUTPUT

,.

N.C.

"
13

N.C.

20k

N.C.

_

ISV
OFFSET
POTENTIOMEl ER

12

·15V

11

TTL lOGIC STROBE

N.C

10

ISV

C0019201

NOTES: 1. To trim output offset to OmV. set strobe input to sample mode (3V). set analog input to GND. adjust potentiometer until S & H output is OmV.
2. Use a low dielectric absorption capacitor such as polystyrene.
SAMPLE MODE occurs when logic input is greater than 2.4V.
HOLD MODE occurs when logic input is less than O.BV.

Figure 3: Typical Connection Diagram

N.C.

N.C.

1.

PROBE

IS

N.C.

TO 10

SCOPE

I.
O.Ol~F

.

P

l00!l

13
N.C.

2Qk

N.C.

15V

_OFFSET
POTENTIOMETER

12

·3V

~

11

·SV

10

·lSV

N.C.
'SV

C0019301

Adjust offset to OmV before testing for charge injection. See note 1.

CHARGE INJECTION

SWITCHING TRANSIENTS

--.ra:=

SY/DIV.

VA
GNO
LOGIC INPUT
C., O.Ql .. f

r---1'- .- 0·v3V
-.oJ
L-

UPPER TRACE

LOWER TRACE

TIME

SV/DIV.
, . . . - , - .3V

'3V

UPPER TRACE'"

OV

SmV/DIV.

-.I

L.-

OY

LOWER TRACE'" SOOmYfDIY.
TIME '" 10~ ...cm

to.. a/em
WFOl6201

WF016301

Figure 4: Charge Injection (sample to hold offset) Measurement Circuit;
also Switching Transients Test Circuit

5-96
Note: All typical values have been guaranteed by characterization and are not tested.

iUI

IH5110-IH5115

......
f
i
......

ACQUISITION TIME

UI
UI

11

N.C.
+tOV

OV

,.

N.C.

=Fl=. :~:;~Na..uT 2
FiI-'"-'JV'OOV',,1~

... 3V

PUTPUT
TO 10)( SCOPE

PR08E
N.C.

20t -15V
_OFFSET
POTENTIOMETER

13

N.C.

12

••v

'0

TTL LOGfC IN

"

+15V
N.C.

5VIDIV.

-15V

UPPER

TR~E.

=J'"1:: :ov

COO19401
5V/DIV.

LOGIC INPUT

=

+3Y

LOWER TRACE

Cs = 0.01/o1F

::ov

~

TI~E"'SI'-'CIn

WF016401

NOTE: The acquisition time is actually a settling time spec. since the reading is only taken when the output has settled within 1% of its final value. The
61ls spec. (IH5111, 5113 & 5115 is the worst reading of the Ion or Ioff settling time shown above. The above test can be performed with a 0 to
+7.5V or 0 to -7.5V step for the IH5110, 5112, 5114.
.

Figure 5: Typical Circuit for Measurement of A.C. Signal Handling Capability
A.C. PEAK TO PEAK

OUTPUT

TO 10" SCOPE
PROBE

N.C.

2011
_

N.C.

1SV
OFFSET

POTlNTtOllET£R

N.C.

CD019501

To test this parameter, increase the amplitude of the signal
generator until the output starts to distort (it will always show up on
the positive excursion of the sine wave first); then back off until all
distortion is gone. The resultant peak to peak swing must be"
greater than 15Vpp for the IH5110, 5112, 5114 and greater than
20Vpp for the IH5111, 5113, 5115.

TVP.IH5111
HTOOOO3I"

.A"~O.

UPPER TRACE"

.Ltr

LOGIC INPUT"" +3V

UPPER ..

Cs = 0.01/o1F t = kHz

LOWER TRACE'" 1OVIOIV.
TtME = O.5mt/cm

O.

WF016501

Figure 6: Typical Circuit for Measurement of A.C. Peak to Peak Signal Handling Capability

&-97
Note: All typical values have been guaranteed by characterization and are not tested.

! '. 1"'51'10~IH5115
10

I..
10

!

= jAwei wt. This means the slope of input signal = (dV/dt)
is a maximum at t (time) = O. This maximum value is wA (in
amplitude). (i.e.) ilJPut frequency is 10kHz, therefore dVldt
= wA = 6.28 x 10 x 10V = 6.3 x 105V/sec.A = 10V, then
slope or dV / dt - 0.63V / ps. Now if we wish error to be a
Max. of say 1% of full scale 10V, we see that 100mV (1 %/
aperture time = 0.63VIps. Solving this equation we see that
aperture tii:ne must be 160ns or less to get 1 % holding
accuracy. Since our aperture time is 150ns typical, we have
1% accuracy in holding 10kHz varying signals; for Signal
frequencies 1kHz and less, Max. error is 0.1 %. The simple
interpretation of just how the off time of the switch causes
this system error is due to the fact a finite time is required
for the switch to react to a hold command; this reaction time
manifests itself with a system voltage error because the
time varying input Signal is changing to a new value before
the switch has actually turned off. (i.e.) in the above
example off = 10kHz and A = 10V, suppose we gave the
hold command (thru TTL logic) at t = 0 (AC. signal goes
thru zero pt.) At this pOint we have calculated the slope to
be a Max. and equal to 0.63V / ps. If there were no aperture
time error, we would read OV at output of Sample and Hold;
however because of finite time for switch to respond to hold
command, 150ns passes before switch goes off. During this
150ns, the input signal has gone to 100mV above or below
OV, thus the stored value of signal will be 100mV and that is
the reading at the output of the Sample and Hold. If the
input frequency were 1kHz, the "error voltage" would be
10mV.

APPLICATION TIPS
The following text serves as a guide in choosing the
correct deviCe frpmthe IH5110 family.
First, deterniine, tti~~ input ~oltag~ 'range. .
,

".,0("

',e",

:",

'

"'.

The even numbered parts ~re desighed to switch smaller
AC. signal amp.li$uC\es with th~ goal ~ing' to minimize the
charge injection 'effects (sanipleto hold offsets). This
charge injection error ,is sHown ih;Figure,4~Once the voltage
.offset is zeroed,.the5HO has. typical elTor amplitudes of 1
to 2mVp-p (corresponds to lOpe to 20pc of charge). Thus
one could sample very low level d.c. signals with extreme
accuracy. If very low level A.C.Signalsare being sampled,
voltage offset potentiometer can be adjusted for a zero
charge injection effect. Once the potentiometer has been
adjusted, there will be a zero error going from sample to
hold; however there will be a d.c. error caused by adjusting
the potentiometer for zero charge injection and not for zero
voltage offset. '"genera', this d.c. error will be in the area of
2mV to 5mV.
The odd numbered parts are primarily designed to handle
any input in the plus or minus 10V range, regardless of
whether it is AC. or D.C.; to obtain this, the charge injection
is about a factor of 2 higher than the even numbered parts.
The use of Varafet switching elements similar to Intersil's
IH401/401A leads to a trade-off between AC signal swing
and charge injection.
After the voltage range and charge injection require.ments have been determined, all that remains is to determine the input offsel voltage the system can tolerate. By
using the higher numbered parts, it is pO$sible to eliminate
the offset potentiometer if system accuracy will allow 5mV
(5114,5115) or 10mV (5112; 5113) due to the low input
offset voltllge on' these devices. '
The drift rate is specified .at , 10mV/ sec. Max. for all
models: this corresponds to approximately 100pA total
leakage into aO.01pF sampling capacitor (Csr. While the
10mV/sec. is the Max. encountered, a mortftYPical reading
is less than 1mVIsec. (true for any input between -10V and
+ 10V); thus the IH5110 family is ideal for applications
requiring very'low drift or droop rates.
The aperture time is sPec'd M200ns Max..' for all models,
but a more tYpical value is 150ns; this is basically the off
time of switch Q1. The way this aperture time affects system
accuracy is shown below:
Assume the input signal to the Sample and Hold is an
A.C. Signal of peak amplitude A (peak to pejik swing is 2A)
and frequency 2m = w, then Vinput = Ael wt and dV/dt

DEFINITION OF TERMS
Aperture Time: The time it takes to switch from sample
mode to hold mode and the actual opening of switch.
Charge Injection: The amount of charge coupled across
.
,
the switch with no input voltage.
Drift Rate: The amount of drift of output voltage at a rate
caused by current flow through the storage capacitor.

(:~ =~)

This current is the leakage across the switch and the
amplifier'S bias current.
Feed Through: The amount of input Signal that appears at
thEioutput when in the hold mode. Normally caused by
capacitance acroSs the switch.
Offset Voltage: Voltage measured at output with no input
voltage and circuit in sample mode.
Acquisition Time: The time it takes amplifier to reach full
scale output either plus or minus.

5-98
Note: All typical values have been guaranteed by characterization and are not tested.

i

IH5110-IH5115

......
CII

f
......

HI-SPEED SAMPLE AND HOLD

i

CII
CII

OUTPUT

N.C.

",'0Y

-1"'1'O;.,"1-ANALOG

2

OV~ '-"-~STEPINPUT

r

II

TO 10 x SCOPE
PROBE

15

N.C.

N.C.

O.Q01,..F

••

SlOll

13

·5V

'3V

.

"k

'5V
OFFSET
POTENTIOMETER

••

N.C.

TTL lOGIC IN

-

11

-15V

.0

N.C.

SVIDIV.
UPPEATRACE

15V
VA ".
COO19101

---I""L:

LOGIC INPUT
Cs

·3Y

"~;~OV

"'OY

5V/DIV.

OV
LOWER TRACE

7

r--\,.-

-J

",.(tOO1~F

nME

~

,.tOY

'--OV

5,..alcm
WF016101

NOTE: Typical times for the Sample and Hold to acquire the input are 2/Js for turn on (output) goes to + 10V and 3/JS for turn off (output goes down to
OV). As a general note, all the electrical specffications are guaranteed with a sampling capacitor equal to O.OI/Jf. As the above application (Fig.
6) shows, other values of sampling capacitors can be used but the best combinations of S & H specs may not result with values other than
O.OI/JF. The only advantage of using a O.OOI/JF for Cs is the acquis~ion time is 2/JS typical instead of 5/Js typical (with O.OI/JF; however the drift
rate would be worse and charge injection would be affected). To minimize drift rate, use a O.I/JF capacitor; this should produce a O.lmV/sec
rate of change and a charge injection amplitude of 0.2mVp-p. Of courSe the acquisition time will be slowed down to the 25/Js area. Also use a
0.1/JS system for slow speed changes (Le., input frequency is less than 1kHz. The series resistor should be about 100n- 200n to stabilize the
system.

Figure 7: Connection For Hi-Speed Sample and Hold With Following
Typical Performance: W/Cs = 0.001
a. 2f..ts settling time (acquisition time) to 1% accuracy
b. 25mV charge injection amplitude
c. 1OmV /sec drift rate

5-99
Note: All typical values have been guaranteed by characterization and are not tested.

Section 6 -

Data Acquisition

AD7520/AD7530
AD7521/ AD7531
10/12-Bit Multiplying
01 A Converters
GENERAL DESCRIPTION

FEATURES

The AD75201 AD7530 and AD7521 I AD7531 are monolithic, high accuracy, low cost 10-bit and 12-bit resolution,
multiplying digital-to-analog converters (DAC). Intersil's
thin-film on CMOS processing gives up to to-bit accuracy
with TTL/CMOS compatible operation. Digital inputs are
fully protected against static discharge by diodes to ground
and positive supply.
Typical applications include digital/analog interfacing,
multiplication and division, programmable power supplies,
CRT character generation, digitally controlled gain circuits,
integrators and altenuators, etc.
The AD7530 and AD7531 are identical to the AD7520
and AD7521, respectively, with the exception of output
leakage current and feedthrough specifications.

•

AD7520/AD7530: 10 Bit Resolution; 8, 9 and 10
Bit Linearity
AD7521/AD7531: 12 Bit Resolution; 8, 9 and 10
Bit linearity
Low Power Dissipation: 20mW (Max)
Low Nonlinearity Tempco: 2· ppm of FSRrC
Current Settling Time: 500ns to 0.05% of FSR
Supply Voltage Range: + 5V to + 15V
TTL/CMOS Compatible
Full Input, Static Protection
/883B Processed Versions Available

•
•
•
•
•
•
•
•

ORDERING INFORMATION
PART NUMBER/PACKAGE
NONLINEARITY
0.2% (8-Bit)

0.1 % (9-Bit)

0.05% (10-Bit)

TEMPERATURE
RANGE

PLASTIC DIP

CERDIP

CERDIP

AD75120JN
AD7530JN
AD7521JN
AD7531JN

AD7520JD
AD7530JD
AD7521JD
AD7521JD

AD7520SD

AD7520KN
AD7530KN
AD7521KN
AD7531KN

AD7520KD
AD7530KD
AD7521KD
AD7531KD

AD7520TD

AD7520LN
AD7530LN
AD7521LN
AD7531LN

AD7520LD
AD7530LD
AD7521LD
AD7531LD

AD7520UD

O°C to +70°C

-25°C to + 85°C

-55°C to + 125°C

AD7521SD

AD7521\D

AD7521UD

TOP VIEW
10Kll

tOKn

tUII

AD7521 (AD7S31)

AD7520 (A07530)
RFEEOBACK

GND
lIT t (IIU)

GND >

I_
lIII0.
IWtTCMU

Ioun

'+-.....- ......+---.....- - . 6....._-<> lou"

lIT 1 (II") •
,IT 2 I

.. .IT 10 (LS')

.IT tl(LO)

'IT 2
'IT3

• IT3

BIT 4

, 'IT7
.IT4
.ITS ......_ _ _.:.o

.ITS
.IT,
lIT ......._ _ _= .•IT 7

80004601

COO31901

'IT •

COOt3201

(Switches shown for Digital Inputs "High")
(Resistor values are nominal)
Figure 1: Functional Diagram

Figure 2: Pin Configurations

6-1
Note: All typical values have been guaranteed by characterization and are not tested.

300105-002

AD7,52017,53QI'152117531
ABSOLUTE'MAXIMUM RATINGS

(TA

= 25°C

unless otherwise noted)

Supply Voltage (V+) ....................................... + 17V
VREF ............................................................±25V
Digital Input Voltage Range ...................... V+ to GND
Output Voltage Compliance ................. -1 OOmV to V +
Power Dissipation (package)
up to +75°C ...................................... 450mW'
derate above 'i-75°C @ ..•..•.....••..•••..• 6mWrc

Operating Temperature
IN, KN, LN Versions ................. O°C to + 70°C
JD, KD, LD Versions .......•......... -25°C to 85°C
SO, TO, UD Versions ............ -55°C to + 125°C
Storage Temperature ......................... -65°C to 150°C
Lead Temperature, (Soldering, 10sec) ................. 300°C

CAUTION:
1) The digitSl contro" inputs 'are, zener protected;' however, ~rmanent damage may occur on unconnected units under high energy electrostatic
fields. Keep unuSl!d units in conductive foam at all time,S.
2) Do not apply voltages higher than Voo or less than GND potential on any terminal except VREF and RFEEOBACK.

.

.

:

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied, Exposure to
absolute maximum rating Conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
PARAMETER

(v+ .. + 15V, VREF = + 10V, TA = 25°C unless otherwise specified)

TEST CONDITIONS

AD7520
(AD7530)

I

AD7521
(AD7531)

10

I

12

DC ACCURACY (Note 1)
Resolution
Nonlinearity
(Note i!)

J
S

VERSION

't<
T
'L

S, T, 'U: over - 55°C to = 125°C

-10V:S VREF:S = 10V,

UNIT

LIMIT

Bits

Fig, 3

0.2 (8-Bit)

% of FSR

Max

Fig, 3

0.1 (9-Bit)

% of FSR

Max

Fig. 3

0.05 (10-Bit)

% of FSR

Max

2

ppm of FSRrC

Max

U

Nonlinearity Tempco
(Notes 2 and 3)
Gain Error (Note 2)

-10V:S VREF:S

+ 10V

0,3

% of FSR

Typ

10

ppm of FSRrC

Max

200
(300)

nA

Max

Fig, 4

±0,OO5

% of FSR/%

Typ

ns

Typ

Gain Error Tempco (Notes 2 and
3)
Output Leakage Current (either
output)
Power Supply

Reie~tiOn

Over the specified temperature
range

(Note 2)

AC ACCURACY (Note 3)
Output Current Settling Time

1'0 0,05% of FSR (All digital
inputs low to high and high to
low)

Fig. 8

500

Feedthrough Error

VREF = 20V pp, 100kHz
(50kHz)' All digital inputs low

Fig. 7

10

~V

pp

Max

REFERENCE INPUT
Input Aesistance

5k
10k
20k

All digital inputs high
IOUTt at ground.

n

Min
Typ
Max

ANALOG OUTPUT
Voltage Compliance (both outpUts)

(Note 3)

Output Gapacitance
(Note 3)

All digital inputs high

Fig. 6

120
37

pF
pF

Typ
Typ

All digital inputs low

Fig. 6

37
120

pF
pF

Typ
Typ

Fig, 5

Equivalent to 10kn
Johnson noise

IpUT!
IbuT2

lOUT!
IOUT2
Output Noise (both outputsi
(Note 3)

See absolute max, ratings

Typ

DIGITAL INPUTS
Low State Threshold

Over the specified temp range

High St,ate Threshold
Input Current (low to high state)
Input Coding

See Tables 1 & 2

0.8

V

2.4

V

Min

1

pA

Typ

Binary/Offset Binary

,

6-2
Note: All typical values

ha~e

been guaranteed by characterizatiOn and are not tested,

Max

.n~n16 ~

AD7520/7530/7521/7531

...
CII

ELECTRICAL CHARACTERISTICS (CONT.)
PARAMETER

AD7520
(AD7530)

TEST CONDITIONS

I

AD7521
(AD7531)

UNIT

LIMIT

V

+5 to +15
All digital inputs at OV or V +

1

p.A

Typ

All digital inputs high or low

2

rnA

Max

20

mW

Typ

Total Power Dissipation
(Including the ladder network)
2. Using internal feedback resistor, RFEEDBACK.
3. Guaranteed by design, not subject to test.
4. Accuracy not guaranteed unlesS outputs at GND potential.

TEST CIRCUITS NOTE: The followjng test circuits
apply for the AD7520. Similar circuits are used for the
AD7530, AD7521 and AD7531.

+11¥ (ADJUST FOR VOUT ;;. OW)

1>,5V

••
t = 1kHz
8.:::: 1Hz
QUAN

TECH
MODEL

COUNTER

'34D

,
,

WAVE

AD....

ANALYZER

'8IT1.
(Lsa)

IU1

CLOCK

-=-

-.........
CIa
N

CII
Co)

NOTES: 1. Full scale range (FSR) is 10V for unipolar and ±10V for bipolar modes.

,.8IT
BINARY

-...
CII

~

POWER REQUIREMENTS

Power Supply Voltage Range
1+

~...

-=-

-=TC022411

Figure 5: Noise

He

...15

BITlf"'.)' 15

••

TC022211

Figure 3: Nonlinearity

~=::::I:

II

NC

100 IIIYp-,
1MHz

TC022501

. .'0 v

Figure 6: Output Capacitance

VAEF~""'---"---+---'\.fV\.,.---...-~
BIT. (MS8)

BIT 10

VREF "" 20 V p-p 130 kHz SINE WAVE

",'SV

(LSB)

BIT 1 (MSa)

TC022311

Figure 4: Power Supply Rejection

15

h=:::::::J:
BIT ,. (Lsi

••

••
. ",,"'O'''''VOUT

TC022601

Figure 7: Feedthrough Error

Note: All typical values have been guaranteed by characterization and are not tested.

;; AD7520/7530/7521/7531

..

~
.....
(\I

t.o

...'"
.....
o
...
In

(\I

a constant current in each ladder leg independent of the
input code.

,,-+15V
.. 10 V

'!: I1..fl..I1.
DIGITAL INPUT

.:..:y.",.~,...--...,

,

y,."

i
~iil!!...+....!f

10

51

10KI1

1.0

10Kn

10Kn

(11117)

TC022701

Figure 8: Output Current' Settling Time

....

toun

NIIOI

•.......... '-!--......-~-+----6._ _...-_ _ IoUT1

(2)
(1)

RFEE~CK

(11111)

DEFINITION OF TERMS
NONLINEARITY: Error contributed by deviation of the OAC
transfer function from a best straight line function. Normally
expressed as a percentage of full scale range. For a
multiplying OAC, this should hold true over the entire VREF
range.
RESOLUTION: Value of the LSB. For example, a unipolar
converter with n bits has a resolution of (2- n) (VREF). A
bipolar converter of n bits has a resolution of [2- In - 1)j
[VREFj. Resolution in no way implies linearity.
SETTLING TIME: Time required for the output function of
the OAC to settle to within 1/2 LSB for a given digital input
stimulus, i.e., 0 to Full Scale.
.GAIN: Ratio of the OAC's operational amplifier output
voltage to the nominal input voltage value.
FEEDTHROUGH ERROR: Error caused by capacitive cou.piing from VREF to output with all switches OFF.
OUTPUT CAPACITANCE: Capacitance from IOUT1 and
IOUT2 terminals to ground.
OUTPUT LEAKAGE CURRENT: Current which appears on
IOUT1 terminal with all digital inputs LOW or on IOUT2
terminal when all inputs are HIGH.

80004701

(Switches shown for Digital Inputs "High")

Figure 9: 752017521 Functional Diagram
Converter errors are further reduced by using separate
metal interconnections between the major bits and the
outputs. Use of high threshold switches reduces the offset
(leakage) errors to a negligible level.
The level shift~r circuits are comprised of three inverters
with a positive feedback from the output of the second to
the first, (Figure 10). This configuration results in TTLI
CMOS compatible operation over the full military temperature range. With the ladder SPOT switches driven by the
level shifter, each switch is binarily weighted for an ON
resistance proportional to the respective ladder leg current.
This assures a constant voltage drop across each switch,
creating equipotential terminations for the 2R ladder resistors and highly accurate leg currents.,

v+---_~~~--_.--_.---

DETAILED DESCRIPTION
The A07520 (A07530) and A07521 (A07531) are monolithic, multiplying 01 A converters. A highly stable thin film R2R resistor ladder network and NMOS SPOT switches form
the basis of the converter circuit, .CMOS level shifters permit
low power TTLICMOS compatible operation. An external
voltage or current reference and an operational amplifier
are all that is required for most voltage output applications.
A simplified equivalent circuit of the OAC is shown in
Figure 9. The NMOS SPOT switches steer the ladder leg
currents between IOUT1 and IOUT2 buses which must be
held either at ground potential. This configuration maintains

DTunLlCMOS

Note: All typical values have been guaranteed by characterization and are not tested.

INPUT

05015401

Figure 10: CMOS Switch

.U~UlL ~

AD7520/7530/7521/7531

...en
o
.en..
~...
en
...
...
en

to)

+11

+11V

~----~-4----~~----'

VFlEF----,

alT 1 (Msa)

OJGITAL
INPUT

15

•5

:
:
alT ,. (LSa)

,.

to)

WOUT

GND

...
to)

08016401

AF026601

Figure 11: Unipolar Binary Operation
(2-Quadrant Multiplication)

Figure 12: Bipolar Operation
(4-Quadant Multiplication)
TABLE 2
CODE TABLE - BIPOLAR (OFFSET BINARY) OPERATION
DIGITAL INPUT
ANALOG OUTPUT
-VREF (1_2-(n-1»
1111111111
-VREF (2-Tn -l)
1000000001
1000000000
0
VREF (2-(n- II)
0111111111
VREF (1 - 2-(n -11)
0000000001

TABLE 1
CODE TABLE - UNIPOLAR BINARY OPERATION
DIGITAL INPUT

ANALOG OUTPUT

1111111111

-VREF (1 - 2- n)

1000000001

-VREF (1/2+2- n)

1000000000

-VREF/2

0111111111
0000000001

-VREF (1/2-2-n)
-VREF (2 n)

0000000000

0

NOTE: 1. LSB = 2- n VREF

0000000000

VREF

NOTE: 1. LSB=2-(n-1) VREF
2. n = 10 for 7520 and 7521
n = 12 for 7530 and 7531

2. n = 10 for 7520. 7530
n= 12 for 7521.7531

A "Logic 1" input at any digital input forces the corresponding ladder switch to steer the bit current to IOUTl bus.
A "Logic 0" input forces the bit current to IOUT2 bus. For
any code the IOUT1 and IOUT2 bus currents are complements of one another. The current amplifier at IOUT2
changes the polarity of IOUT2 current and the transconductance amplifier at IOUTl output sums the two cu~rents. This
configuration doubles the output range but halves the
resolution of the DAC. The difference current resulting at
zero offset binary code. (MSB;= "Logic 1" • All other
bits = "Logic 0"). is corrected by using an external resistor.
(10 Megohm) •. from VREF to IOUT2.
OFFSET ADJUSTMENT
1. Adjust VREF to approximately + 10V.
2. Connect all digital inputs to "Logic 1" .
3. Adjust IOUT2 amplifier offset adjust trim pot for OV
± 1mV at IOUT2 amplifier output. .
. 4. Connect MSB (Bit 1) to ., Logic 1" and all other bits
to "Logic 0".
5. Adjust IOUTl amplifier offset adjust trimpot for OV ± 1
mV at VOUT.
GAIN ADJUSTMENT
1. Connect all digital inputs to V + .
2. Monitor VOUT for a -VREF (1_2._(n-1» volts
reading. (n = 10 for AD7520 and AD7530. and
n = 12 for AD7521 and AD7531).
3. To increase VOUT. connect a series resistor of up to
500n between VOUT and RFEEDBACK.
4. To decrease VOUT. connect a series resistor of up
to 500n between the reference voltage and the,
VREF terminal.

APPLICATIONS
Unipolar Binary Operation
The circuit configuration for operating the AD7520
(AD7530) and AD7521 (AD7531) in unipolar mode is shown
in Figure 11. With positive and negative VREF values the
circuit is capable of 2-Quadrant multiplication. The "Digital
Input Codel Analog Output Value" table for unipolar mode
is given in Table 1.
ZERO OFFSET ADJUSTMENT
1. Connect all digital inputs to GND.
2. Adjust the offset zero adjust trimpot of th~ output
operational amplifier for OV ± 1 mV at VOUT.
GAIN ADJUSTMENT
1. Connect all AD7520 (AD7530) or AD7521 (AD7531)
digital inputs to V + .
2. Monitor VOUT for a -VREF (1_2~n) reading. (n = 10
for AD7520 (AD7530) and n = 12 for AD7521
(AD7531».
3. To decrease VOU". connect a series resistor (0 to
500n) between the reference voltage and the VREF
terminal.
4. To increase VOUT. connect a series resistor (0 to
500n) in the lOUT1 amplifier feedback loop.

Bipolar (Offset Binary) Operation
The circuit configuration for operating the AD7520
(AD7530) or AD7521 (AD7531) in the bipolar mode is given
in Figure 12. Using offset binary digital input codes and
positive and negative reference voltage values. 4-Quadrant
multiplication can be realized. The "Digital Input Codel
Analog Output Value" table for bipolar mode is given in
Table 2.
6-5

Note: All typical values have been guaranteed by characterization and are not tested,

;;
AD7520/7$30/7521/7531
.In

...

;

.

...
o
..,
...

In

-...2

...-----13

,.

-=.SWITCHU
lIT {

'2
11
10

INTI!R....
.
4· AD.,. ,.

10

•
7

•

In

_I"'OVI
.,IV

,-

lGKn

LA} lIT
SWITCHU

S

05016501

Figure 13: Basic Power DAC

POWER DAC. DESIGN· USING AD7520
A typical power DAG designed for 8 bit accuracy and 10
bit resolution is shown in Figure 13. An INTEASIlIH8510
power operational amplifier (1 Amp continuous output at up
to ±25V) is driven by the AD7520.
A summing amplifier betWeen the AD7520 and the
IH8510 is I,!sed to separate the gain block containing the
AD7520 on-chip resistors from the power amplifier gain
stage whose gain is set only by the external resistors. This
approach minimizes. drift since the reSistor pairs will track
properly. Ot/:1erwise the AD7520 can be directly connected
to the IH8510, by using a 25Vreference for the DAC.··
An important note on the AD7520/101A interface concerns the connection of pin 1 of the DAC) and pin 2 of the
101A. Since this point is thesl.Jlnming junCtion of an .
amplifier with an AC gain of 50;000' or better, stray
capacitance should be minimized; otherwise instabilities
and poor noise performance will result. Note that the output
of the101Ais fed into an inverting amplifier withs gain of
-3,. which can be easil~ changed to a,non-inverting
configuration. (For more information' see: INTEASll AWIlcation Bulletin A021:, Power O/A Converters Using. The
IH8510 by Dick Wilenkeh.)

AnaloglDlgltal. DiVision. , ,
With the AD7520 connected in its normal multiplying
configurati9n as showl:] in Figure, 13, the transfer function is:

(A1

VO" -V'N
+ A2
.
21 , 22

+ A3.3 + ...
'2

An. )
2n

where the coefficients Ax aSsume a value of l' for an ON. bit
and 0 for an OFF bit.
'
By connecting the DAC in the feedback of an operational
amplifier, as shown in Figure 14, the. transfer function
becomes:

ThiS is division of an analog variable (V,N) by a digital
word. With all bits off, the amplifier saturates to its bound,
since division by zero isn't defined. With the LSB (Bit-10)
ON, the gain is 1023. With all bits ON, the gain is 1 (±1
lSB).

Dl(;lj~ :
INPUT

i

~..~r.:;;;,.:;iIL:&i..;t:~:-!I

VO\JT

Too22801

Figure 14: Analog/Digital Divider
.. For further information on the use of this device, see the
following Application Bulletins:

.A016 "Selecting AID Converters," by'David Fullagar
A018 "Do's and Don'ts of Applying AID Converters," by
Peter Bradshaw and Skip Osgood
A020 "A Cookbook Approach to High-Speed Data
Acquisition and Microprocessor Interfacing" by Ed
Sliger
.
-"021 ",Power D/A Converters Using the IH8510," by Dick
Wilenken

VO=

Note: .AII typical values have been guaranteed by characterization and are not tested.

AD7523
8-Bit Multiplying
D/A Converter
GENERAL DESCRIPTION

FEATURES

The AD7523 is a monolithic, low cost, high performance,
10 bit accurate, multiplying digital-to-analog converter
(DAC), in a 16-pin DIP.
Intersil's thin-film resistors on CMOS circuitry provide 8bit resolution (8, 9 and 10-bit accuracy), with TTL/CMOS
compatible operation.
The AD7523's accurate four quadrant multiplication, full
military temperature range operation, full input protection
from damage due to static discharge by clamps to V + and
GND, and very low power dissipation make it a very
versatile converter.
Low noise audio gain controls, motor speed controls,
digitally controlled gain and attenuators are a few of the
wide range of applications of the 7523.

•
•
•
•
•

•
•
•

8, 9 and 10 Bit Linearity
Low Gain and Linearity Temperature CoeffiCients
Full Temperature Range Operation
.
Static Discharge Input Protection
DTL/TTL/CMOS Compatible
+ 5 to + 15 Volts Supply Range
Fast Settling Time: 150ns Max at 25°C
Four Quadrant Multiplication

ORDERING INFORMATION
PART NUMBER/PACKAGE
NONLINEARITY

PLASTIC DIP

CERDIP

CERDIP

0.2%
(8 Bit)

AD7523JN

AD7523AD

AD7523SD

0.1%
(9 Bit)

AD7i523KN

AD7523BD

AD7523TD

0.05%
(10 Bit)

AD7523LN

AD7523CD

AD7523UD

O'C to +70'C

-25'C to
+ 85'C

-55'C to
+ 125'C

TEMPERATURE
RANGE

VREFIN

115)
20Kn

SPOT

SWIT'::':.~:

I

I

: '---+'-+--+~~-+-~++--IOUT2(2)

........:...~IOUT1(I)

4 - -......
I--+i,---~I

I

6

6

BIT2
(5)

BIT3
(6)

RFEEDBACK

(16)
80004801

COO13301

Figure 1: Functional Diagram
(Switches shown for Digital Inputs "High")

s:.-7
Note: All typical values have been guaranteed by characterization and are not tested.

Figure 2: Pin Configuration
Outline Drawings DE, PE

i

i

AD7523

ABSOLUTEMAXIMUM'RATI~GS

(fA = 25·Cunless otherwise noted)

Supply Voltage (V +) ....................................... + 17V
VREF ............................................................±25V
Digital Input Voltage Range ...................... V+to GND
Output Voltage Compliance .................. -100mV to V+
Power Dissipation:
Plastic Packageup to + 70·C ...................................... 670mW
derate above +70·C by .................... 8.3mWI"C

Ceramic Packageup to 75·C ........................................ 450mW
derate above 75·C by ......................... 6mW,rC
Operating Temperatures
.
.'
.
IN, KN, LN Versions ................. O·C to + 70·C
AD, BD, CD Versions ............... -25·C to +85·C
SO, TO, UD Versions ............ ~55·C to + 125·C
Storage Temperature ...................... -65·C to +150·C
Lead Temperature (Soldering, 10sec) .............. + 300·C

CAUTION:
,
I. The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy electrostatic
fields. Keep unused units in conductive foam at 'all times:
2. Do not apply voltages higher than VDD and lower than GND to any terminal except VREF + RFEEDBACK.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating cond~ions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
PARAMETER

(V + = + 15V, VREF = + 10V unless otherwise specified)

TEST CONDI'TIONS

+ 25·C

TA

TA
MIN';'MAX

8
±0.2

8
±0.2

B~

Min

% of FSR

UNIT

1.IMIT

DC ACCURACY (Note 1)
Resolution
Nonlinearity (Note 2)

I

(± Y2 LSB)

I
I

(± Y4 LSB)

-IOV::; VREF S + 10V

±O.I

±O.I

% of FSR

Max
Max

(± Y8 J,.SB)

VOUT1 = VOUT2 = OV

±0.05

±0.05

% of FSR

Max

% of FSR

Max

ppm of FSRI"C
ppm of FSRI"C

Monotonicity
Gain Error (Note 2)

I

Digital Inputs high.

Nonlinearity Tempeo (Notes "2 and 3)
Gain Error Tempcc (Notes 2 and 3)
Output Leakage Current

Guaranteed
±1.5
±1.8

(e~her

2
10
±50

±200

nA

Max
Max
Max

0.02

0.03

% of FSR

Max

150

200

ns

Max

±Y2

±1

LSB

Max

-IOV VREF +IOV

output)

VOUT1 = VOUT2 = 0

AC ACCURACY
Power Supply Reiection (Note 2)

V+

Output Current Settling Time (Note 3)

= 14.0

to 15.0V

To 0.2% of FSR, RL - lOOn
VREF = 20V pp, 200kHz sine wave. All
digital inputs low.

Feedthrough Error (Note 3)
REFERENCE INPUT
Input Resistance (Pin 15)
ANALOG OUTPUT
Output CapaCitance
(Note 3)

5K
20K

n

I

-500

ppml"C

All digital inputs high (VINH)

100
30

pF
pF

All digital inputs low (VINL)

30
100

pF

Max
Max

pF

Max

0.8

':I

Max

2.4
±1

V

IlA

Min
Max

pF

Max

I

Temperature Coefficient (Note 3)
COUT1
CoUT2
CoUT1

~

I
I

All digital inputs high. IOUTI at ground.

CoUT2

Max

I

Max

Max

DIGITAL INPUTS
Low State Threshold (VINU
High State Threshold (VINH)
Input Current (Low or high)
Input Coding

VIN=OVor +15V
See Tables 1 & 2

Input Capacitance (Note 3)

Binary/Offset Binary
4

POWER REQUIREMENTS
Power Supply Voltage Range
1+
NOTES: 1.
2.
3.
4.

Accuracy is tested and guaranteed at
V+ - + 15V, only.
All digital inputs low or high.

Full scale range (FSR) is 10V for unipolar and ± 10V for bipolar modes.
Using internal feedback resistor, RFEEDBACK.
Guaranteed by design; not subject to test.
Accuracy not guaranteed unless outputs at ground potential.

Note: All typical values have been guaranteed by characterization. and. are not tested.

+5 to +16
2

V

I

rnA

I

Max

AD7523
APPLICATIONS

BIPOLAR OPERATION

UNIPOLAR OPERATION

:-lOV

·1SV

VREF

NOTES:

.,
2k

1. R1 AND R2 USED ONLY IF GAIN
ADJUSTMENT IS AEQUIRED.

2. CA1 PROTECTS A07523 AGAINST
NEGATIVE TRANSIENT&.

R21k
DATA ~ MSa
INPUTS: LSB 11

TC022901

LD006201

Figure 3: Unipolar Binary Operation

NOTES:
1. R3/R4 MATCH 0.1% OR BETTER.
2. Rl, R2 USED ONLY IF GAIN
ADJUSTMENT IS REQUIRED.

Table 1. Unipolar Binary Code Table
DIGITAL INPUT
MSB
LSB

11111111

3.
4.

R5-R7 USED TO ADJUST YOUT = OY
AT INPUT CODE 10000000.
CR1 I CR2 PROTECT AD7523
AGAINST NEGATIVE TRANSIENTS.

Figure 4: Bipolar Operation

ANALOG OUTPUT

-VREF

10000001

-VREF

10000000

-VREF

01111111

-VREF

(255)
256
f29)
256
f28)
256

Table 2. Bipolar (Offset Binary) Code Table
DIGITAL INPUT

MSB

ANALOG OUTPUT

LSB

11111111

-VREF

10000001

-VREF

= _VREF

2

~::)

10000000

0
+VREF

00000001

-VREF

b:6)

01111111

00000000

-VREF

b~6)=O

00000001

+VREF

00000000

+VREF

NOTE: 1 LSB = (2- 8) (VREF)

1

= (-)

256

(VREF)

f27)
128
(1:8)
(1~8)

f27)
128
f28)
126

1
NOTE: 1 LSB = (2 - 7) (VREF) = ( - ) (VREF)

126

A typical power DAC designed for 10 bit accuracy and 8
bit resolution is shown in Figure 5. The Intersil IH8510
power operational amplifier (1 Amp continuous output with
up to + 25V) is driven by the AD7523.
A summing amplifier between the AD7523 and the
IH8510 is used to separate the gain block containing the
AD7520 on-chip resistors from the power amplifier gain
stage, whose gain is set only by the external resistors. This
approach minimizes drift since the resistor pairs will track
properly. Otherwise AD7523 can be directly connected to
the IH8510, by using a 25 volt reference for the DAC.

Note: All typical values have been guaranteed by characterization and are not tested.

=
AD7523,
...
10

~

POWER DAC DESIGN USINGAD7523
'6t-----~-----.,

,-------12
+------13

'5
'4

• INTERSIL '3
5 AD7523 12

(

I

81Ti

SWITCHES

6

VR.F (,'OV)

,'5V

HC
HC

0."/\

'OK/\

Your

"
'0

•

l

} :::ITCHfS

'00p'
o... n
7.SKf!

TC036401

Figure 5: Basic Power DAC Design

DEFINITION OF TERMS
NONLINEARITY: Error contributed by deviation of the DAC
transfer function from a best straight line function. Normally
expressed as a percentage of full scale range. For a
multiplying DAC, this should hold true over the entire VREF
range.
RESOLUTION: Value of the LSB. For example, a unipolar
converter with n bits has a resolution of (2- n) (VREF). A
bipolar converter of n bits has a resolution of [2- rn -1)1
[VREFI. Resolution in no way implies linearity.
SETTLING TIME: Time required for the output function of
the DAC to settle to within '1f2 LSB for a given digital input
stimulus, i.e., 0 to Full Scale.
GAIN: Ratio of the DAC's operational amplifier output
voltage to the nominal input voltage value.
FEEDTHROUGH ERROR: Error caused by capacitive coupling from VREF to output with all switches OFF.
OUTPUT CAPACITANCE: Capacity from IOUT1 and IOUT2
terminals to ground.
OUTPUT LEAKAGE CURRENT: Current which appears on
IOUT1 terminal with all digital inputs LOW or on IOUT2
terminal when all inputs are HIGH.

VOUT=-VtNlO

WHERE:

D= 8~' +8:Z+", 8~'

>--6-<>VOUT

AF026BOI

Figure 6: Divider (Digitally Controlled Gain)

VREF

~--------------~
R,

+'5V

,.

VOUT

= YREF ~-!L)
~

Rl +R2

'.---0........

-(~)l
+ A2~
Al

For further information on the use of this device, see the
following Application Notes:
A016 "Selecting AID Converters," by David Fullagar
A018 "Do's and Don'ts of Applying AID Converters," by
Peter Bradshaw and Skip Osgood
A020 "A Cookbook Approach to High-Speed Data
Acquisition and Microprocessor Interfacing" by Ed
Sliger
A021 "Power D/A Converters Using the IH851 0," by Dick
Wilenken

!!!...!
+ ~ +..• • ,T.
21
22
2"

WHERE: D =

AF026901

Figure 7: Modified Scale Factor and Offset

6-10
Note: All typical values have been guaranteed by characterization and are not tested.

AD7533

10-Bit Multiplying
01 A Converter

GENERAL DESCRIPTION

FEATURES
Lowest Cost 10-Bit DAC
8, 9 and 10 Bit Linearity
Low Gain and Linearity Tempcos
Full Temperature Range Operation
Full Input Static Protection
TTL/CMOS Direct Interface
+5 to + 15 Volts Supply Range
Low Power Dissipation
Fast Settling Time
Four Quadrant Multiplication
Direct AD7520 Equivalent
883B Processed Versions Available

The Intersil AD7533 is a low cost, monolithic 10-bit, fourquadrant multiplying digital-to-analog converter (DAC). Intersil's thin-film resistor on CMOS circuitry provide 10, 9 and
8 bit accuracy, full temperature range operation, + 5V to
+ 15V supply voltage range, full input protection from
damage due to static discharge by clamps to V + and
ground and very low power dissipation.
Pin and function equivalent to the industry standard
AD7520, the AD7533 is recommended as a lower cost
alternative for old or new 10-bit DAC designs.
Applications for the AD7533 include programmable gain
amplifiers, digitally controlled attenuators, function generators and control systems.
I

ORDERING INFORMATION

PACKAGE IDENTIFICATION

~

TEMPERATURE RANGE
O'C to
+70'C

-2S'C to
+8S'C

-SS'C to
+ 12S'C

±O.2%
(8-bit)

AD7533JN

AD7533AD

AD7533SD

±O.1%
(9-bit)

AD7533KN

AD7533SD

AD7533TD

±O.O5%
(10-bit)

AD7533LN

AD7533CD

AD7533UD

NONLINEARITY

IL:lpaCkage
D -18-Pin CERDIP DIP
N - 18-Pin Plastic DIP
Nonlinearity and Temperature Range
J,K,L - Commercial
O'C to + 70'C
A,S -Industrial
-25'C to + 85'C
S,T-Military
- 55'C to + 125'C

' - - - - - - - S a s i c Part Number

10Kn

10Kn

10Kn

10Kn

(15)

SPOT
NMOS

IoUT2 (2)

,----+--...... . . _ - - 10011 (11

SWITCHES 4---+-,;---<...
,

A

I

A

8m

BIT3

(5)

(6)

RFEEDBACK

(16)
8ooo49Ol

. Figure 1: Functional Diagram

Figure 2: Pin Configuration

6-11
Note: All typical values have been Quaranteed by characterization and are not tested.

AI)7533,
ABSOLutE MAXIMUM RATINGStTA = 25°C

unless otherwise noted)

V+ .............................................................. +17V
VREF ............................................................±25V
Digital Input Voltage Range ................ : .... N+ to GND
Output Voltage Compliance .. ,., ............... -O.1V to V+
Power Dissipation
Ceramic Package:
__..
..
up to +75°C............. : ...................... : . .450mW·
derates above + 75°C by .................... 6mW I"C

Plastic Package:
up to 70°C ........................................ 670mW
derates above 70°C by ..................... 8.3mW
Operating Temperature. Range:
.
IN, KN, LN Versions ................. O°C to + 70°C
AD, BD, CD Versions ................ -25°C to 85°C
SO, TO, UD Versions ............ -55°C to + 125°C
'Storage Temperature Range ............... ..:65°C to 150·C
Lead Temperature (Soldering, 10sec) .............. + 300°C

rc

CAUTION:
1. The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy electrostatic fields. Keep
unused units in conductive foam at all times.

2. Do not apply vo"ages lower than ground or higher than V + to any pin except VREF and RFB.
Stresses above those listed under AbSolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device' at these or any other conditions above those' indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended p~riods may altect device reliability.

ELECTRICAL CHARACTERISTICS
(V+ = + 15V, VREF= +10V, VOUT1 =VOUT2=O unless otherwise specified.)

TEST CONDITIONS

PARAMETER

TA
+25°C

TA
MIN-MAX

LIMIT

UNIT

DC ACCURACY (Note 1)
Resolution
Nonlinearity (Note 2)
-IOVSVREFS +IOV
VOUT1

= VOUT2 - OV
Inputs = VINH

Gain Error (Note 2 and 5)

Digital

Output Leakage Current (either .output)

VREF = ±IOV

10

10

Min

Bits

±0.2

±0.2

Max

% of FSR

±O.I

±O.I

Max

% of FSR

±O.OS

±O.OS

Max

% of FSR

±1,4

±I.S

Max

% of FS

±50

±200

Ml\x

nA

AC ACCURACY

= 14.0.to

Power Supply Rejection (Note 2)

v+

0.005

0.008

Max

% of FSR/%

Output Current Settling Time (Note 3)

To 0.05% of FSR. RL = loon

600
(Note 6)

800
(Note 3)

Max

ns

Feedthrough Error (Note 3)

VREF = f 10V, 100kHz sine wave.
Digital inputs low.

fO.05

±O.I

Max

% FSR

17.0V

REFERENCE INPUT
5k

Min

20k

Max

n

-300

Typ

ppmrC

100

Max

pF

35

Max

pF

35 ..

Max

pF

100

Max

pF

Low State Threshold .(VINL)

0.8

Max

V

High State Threshold (VINH)'

2,4

Min

V

±I

Max

pA

Max

pF

Input Resistance (Pin 15)

All digital inputs high.

Temperature Coefficient
ANALOG OUTPUT
Both outputs.
See maximum ratings

Voltage Compliance (Note 3)
Output Capacitance (Note 3)

'CoUT!

-IOOmV to V+

All digital inputs high (VINH)

COUT2

..

GoUT1

All digRal inputs low (VINU

GoUT2

DIGITAL INPUTS

= OV

Input Current (liN)

VIN

and V+

Input Coding

See Tables I & 2

Binary/Offset Binary

Input Capacitance (Note 3)

5

6-12
Note: All typical values have been guaranteed by characterization and are not tested.

AD7533
ELECTRICAL CHARACTERISTICS (CONT.)
PARAMETER

TA
+25°C

TEST CONDITIONS

I

TA
MIN-MAX

LIMIT

UNIT

POWER REQUIREMENTS

+15 ±10%

Rated Accuracy

Voo
Power Supply Voltage Range
1+

2

Digital Inputs = VINL to VINH
Digital Inputs = OV or V +

NOTES:

1.
2.
3.
4.
5.
6.

100

I

150

Full scale range (FSR) is 10V for unipolar arid ± 1OV for bipolar modes.
Using internal feedback reSistor, RFEEOBACK.
Guaranteed by design; not subject to test.
Accuracy not guaranteed unless outputs at ground potential.
Full scale (FS) = -(VREF) • (1023/1024)
Sample tested to ensure specification compliance.

The Intersi! A07533 is a 10 bit, monolithic, multiplying
01 A converter. A highly stable thin film R-2R resistor ladder
network and NMOS SPOT switches form the basis of the
converter circuit. CMOS level shifters permit low power
TTL/CMOS compatible operation. An external voltage or
current reference and an operational amplifier are all that is
required for most voltage output applications.
1Q1(n

10Ku

V
Max

mA

Max

p.A

Specifications subiect to
change without notice.

constant current in each ladder leg independent of the input
code.

DETAILED DESCRIPTION

VAEFIN

V

+5to +16

v+--------~~~----~----~--

10Kn

DTLlTTUCilOS

(1$)

INPUT

2OICl1

SPOT
NMOS

SWITCHES
I
I

4

I
I

4

Bin

BIT3

(5)

(8)

louT2(2)
loun(l)

LC006901

Figure 4

AFEEDBACK

(18)

The level shifter circuits are comprised of three inverters
with a positive feedback from the output of the second to
the first, (Figure 4). This configuration results in TTL/CMOS
compatible operation over the full military temperature
range. With the ladder SPOT switches driven by the level
shifter, each switch is binarily weighted for an "ON"
resistance proportional to the respective ladder leg current.
This assures a constant voltage drop across each switch,
creating equipotential terminations for the 2R ladder resistors resulting in accurate leg currents.

LCO06801

(Switches shown for Digital Inputs "High")

Figure 3
A simplified equivalent circuit of the OAC is shown in
Figure 3. The NMOS SPOT switches steer the ladder leg
currents between IOUT1 and IOUT2 busses which must be
held at ground potential. This configuration maintains a

6-13
Note: All typical values have been guaranteed by characterization and are not· tested.

=AD7,j'33
..
II)

...
~

APPLICATIONS

BIPOLAAOPERATION,
"
(4-QUADRANT MULTIPLICATION)

UNIPOLAR OPERATION
(2-QUADRANT MULTIPLICATION)
81POlAR

~

±1OV

v+

R21k

LC007001

LCO07101

NOTES: Inl1. R1 and R2 used only if gain adjustment is
required.
2. Schottky diode CR 1 (HP5082-2811 or equiv) protects
OUT1 terminal against negative transients.

NOTES:
, 1. R3/R4 match 0.05% or better.
2. R1 and R2 used only If gain adjustment Is required.
3. Schottky diodes CR1 and CR2 (HP5082-2811 or equiv)
protect OUT1 and OUT2 terminals against negative
transients.

Figure 5: Unipolar Binary Operation
(2-Quadrant Multiplication)

Figure 6: Bipolar Operation
(4-Quadrant Multiplication)

Table 1. Unipolar Binary Code
DIGITAL INPUT
MSB
LSB
111111~111

1000000001

NOMINAL ANALOG. OUTPUT
(VOUT as shown in Figure 3)
-VREF

r

-VREF

(513)
1024

'.'

1000000000

-VR'EF

Table 2. Bipolar (Offset Binary)
Code Table
DIGITAL INPUT
MSB LSB

023
1024)

(~)=
1024

0111111111

-VREF

(511 )
1024

0000000001

'. -VREF

(10~4)

0000000000

-VREF

_ VREF
2

(-0-) -0
1024

NOMINAL .ANALOG OUTPUT
(VOUTas shown in Figure 4)
-VREF

1000000001

-VREF

1000000000

0

0111111111

+VREF

0000000001 '

+VREF

(~)
512

0000000000

+VREF

(512)
512

NOTES: 1. Nominal Full Scale for the circuit of Figure 3 is given by

1023)
FS= -VREF (1024

(5:2)

(5:2)

NOTES: 1. Nominal Full Scale for the circuit of Figure 4 is given by

1023)
FSR=VREF (512
2. Nominal LSB magnitude for the circuit of Figure 4 is given
by

2. Nominal LSB magnitude for the circun of Figure 3 is given
by
LSB = VREF

(~)
512

1111111111

(_1_)
1024

LSB = VREF

6-14
Note: All typical values have been guaranteed by characterization and lIre not tested.

(.2..)
512

AD7533
POWER DAC DESIGN USING AD7533

r---------~1

r------t2

{

+-----13

-

BIT
SWITCHES

11t----------------------,

15

14

4 INTERSIL 13
5 AD7523 12

6

VRE,(;;1OVI
+15V
NC
NC

• ~'TCHES

11
10

0.1111

1CIKII

VOUT

•

}

100pf

0.1111

7.51(11

AF027011

Figure 7: Basic Power DAC
A typical power DAC designed for 8 bit accuracy and 10
bit resolution is shown in Figure 7. INTERSIL IH8510 power
amplifier (1 Amp continuous output with up to ±25V) is
driven by the AD7533.
A summing amplifier between the AD7533 and the
IH8510 is used to separate the gain block containing the
AD7533 on-chip resistors from the power amplifier gain
stage whose gain is set only by the external resistors. This
approach minimizes drift since the resistor pairs will track
properly. Otherwise the AD7533 can be directly connected
to the IH8510, by using a 25 volts reference for the DAC.
Notice that the output of the LM1 01 A is fed into an inverting
amplifier with a gain of -3, which can be easily changed to
a non-inverting configuration. (For more information write
for: INTERSIL Application Bulletin A021-Power Of A Converters Using The IH8510 by Dick Wilenken.)

CALIBRATE

10k

Fl:f

SQUARE

WAVI!

y
I:N(~~)

TRIANGULAR

WAVI!

RI= 1QkO
O-+-------i>----+'--""Iou"

I')

IlFEEDMCIC

(11)
90005201

CD013S01

Figure 1: Functional Diagram
(Switches shown for Digital Inputs 'High')

6-16
Note: All typical values have been guaranteed by characterization and are not t6sted.
<

Figure 2: Pin Configuration
(Outline dwgs ON, PN)

300150-002

AD7541
ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
V+ ... .'.......................................................... +17V
VREF ............................................................±25V
Digital Input Voltage Range ......................GND to V+
Output Voltage Compliance ................. -1 OOmV to V +
Power Dissipation (package):
up to +75°C ...................................... 450mW
derate above +75°C by ..................... 6mW/oC

Operating Temperature Range:
IN, KN, LN Versions ................. O°C to + 70°C
AD, SO Versions .................... -25°C to + B5°C
SO, TO Versions .................. -55°C to + 125°C
Storage Temperature ...................... -65°C to + 150°C
Lead Temperature (Soldering, 10sec) ................. 300°C

CAUTION
1. The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy electrostatic lields. Keep
unused units in conductive loam at all times.
2. Do not apply voltages higher than VDD or less than GND potential on any' terminal except VREF and Rib.
,Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and lunctional
operation 01 the device at these or any other conditions above those indicated in the operational sections 01 the speCifications is not implied. Exposure to
absolute maximum rating conditions lor extended period may affect device reliability.

ELECTRICAL CHARACTERISTICS (V + = + 15V, VREF = + 10V, TA = 25°C unless otherwise specified)
PARAMETER

TA

TEST CONDITIONS

TA
LIMIT FIG.
MIN-MAX

+ 25°C

UNIT

DC ACCURACY (Note 1)
Resolution
Nonlinearity (Note 2)

S

J

r,:- ~ -10VSVREFS +10V

r- ~ VOUTl = VOUT2 =
Gain Error (Note 2)
Output Leakage Current (either output)

12

12

Min

Bits

±0.024

±0.024

Max

% 01 FSR

±0.012

±0.012

Max

±0.012
±0.012
Guaranteed Monotonic

OV

-10VSVREFS +10V

±0.3

VOUTl = VOUT2 - 0

±50

I

V+ = 14.5 to 15.5V

±0.01

I

1

% 01 FSR

Max

% 01 FSR

±0.4

Max

% 01 FSR

±200

Max

nA

±0.02

AC ACCURACY (Note 3)
% 01 FSR/%

Max

2

Output Current Settling Time

To 0.01 % 01 FSR

1

Max

6

p.s

Feedthrough Error

VREF = 20V pp, 10kHz. All digital
inputs low.

i

Max

5

mV pp

Power Supply Rejection (Note 2)

REFERENCE INPUT
Input Resistance

5K

Min

All digital inputs high.

10K

Typ

10UTl at ground.

20K

Max

n

ANALOG OUTPUT
Both outputs.
See maximum ratings.

Voltage Compliance (Note 4)

"

-100mV to V+

COUTl
COUT2

All digital inputs high (VINH)

200
60

Max
Max

4

pF
pF

CoUTl
CoUT2

All digital inputs low (VINU

60
200

Max
Max

4

pF
pF

Equivalent to 10Kn
Johnson noise

Typ

3

Low State Threshold (VINL)

0.8

Max

High State Threshold (VINH)

2.4

Min

V

±1

Max

p.A

Max

pF

2.0/2.5

Max

rnA

20

Typ

Output capacitance (Note 3)

Output NOise (both outputs)
DIGITAL INPUTS

Input Current

VIN ·'0 or V+

Input Coding

See TBbles 1 & 2

V

Binary/Offset Binary

8

Input CapaCitance (Note 3)
POWER REQUIREMENTS
PQWer Supply Voltage Range
1+

Accuracy is not guarantaed
over this range
All digital inputs high or low

Total PQWer DiSSipation (Including the ladc;ler)
NOTES:

1.
2.
3.
4.

Full scale range (FSR) IS 10V lor unipolar and ± 10V lor bipolar modes.
Using intemal feedback resistor, RFEEDBACK.
Guaranteed by design; not subject to test.
Accuracy not guaranteed unless outputs at ground potential.

6-17
Note: All typical values have been guaranteed by characterization and, are not tested.

+5 to +16

V

..

mW

Specifications sublect to
change without notice.

i

IID~OIl

AD7S41,

&
c

TC023:JOI

Figure 6: Output Capacitance Test Circuit

+15V

YAEF '" 20V p-p 10kHz 8tNE WAVE

8fT 1 (1IS8.

11

r:;::=:t.:

TC023001

Figure 3: Nonlinearity Test Circuit

·1

15

BIT '2(LSB

TC023401

_UNDID
IIIIEWAVE

--

a_TOil

_tv"

+10 V

Figure 7: Feedthrough Error Test Circuit

(~~~Tr-----~----+---~VV\---~--~.~~~,

FOR

,.

t

+15V

VE"""" ,...
:'T:'=(="'~B~)
=OV.DC,.

+-10 V -"VA"'EFC-_-,

r.*7....~.."

EXTRAPOLATE

:, :'~~NQ

BIT 1 (MSB) •

BIT 12

5

(LSB)

AD7",

Too23101

Figure 4: Power Supply Rejection
Test Circuit

TC023501

Figure 8: Output, Current Settling Time
Test Circuit
+1.1V (ADJUST FOR

YOUT '"

OV)

DEFINITION OF TERMS

+1SV

'k

NONLINEARITY: Error contributed by deviation of the OAC
transfer function from a best straight line function. Normally
expressed as a' percentage of full scale range. For
multiplying OAC, this should hold true over the entire VREF
range.

F= 111Hz
,8W=1Hz

a

QUAM
TECH

.....

MODEL
WAVE
ANALYZER

RESOLUTION: Value of the LSB. For example, a unipolar
converter with n bits has a resolution of (2- n) (VREF). A
bipolar converter of n bits has a resolution of [2-(n -1»)
[VREFI. 'Resolutiori in no way implies linearity.
SETTLING TIME: Time required for the output function of
the OAC to settle to within 112 LSB for a given digital input
stimulus, i.e., 0 to Full Scale.

Too23201

Figure 5: Noise Test Circuit

GAIN: Ratio of the'OAC's operational amplifier output
voltage to the nominal input voltage value.
'
FEEDTHROUGH ERROR: Error caused by capacitive coupling from VREF to output with all switches OFF.
6-18
Note: All typical values have been guaranteed by characterization and are not tested.

AD7541
OUTPUT CAPACITANCE: Capacity from IOUTl and IOUT2
terminals to ground.
OUTPUT LEAKAGE CURRENT: Current which appears on
IOUTl terminal with all digital inputs LOW or on IOUT2
terminal when all inputs are HIGH.

DETAILED DESCRIPTION
The Intersil AD7541 is a 12 bit, monolithic, multiplying
0/ A converter. Highly stable thin film R-2R resistor ladder
network and NMOS DPDT switches form the basis of the
converter circuit. CMOS level shifters provide low power
DTL/TTLICMOS compatible operation. An external voltage
or current reference and an operational amplifier are all that
is required for most voltage output applications.

101m

V.... IN

101Ul

LC006701

Figure 10: CMOS Switch

101CO

APPLICATIONS
General Recommendations

(17)

.....

NII08

OWIT"",

Static performance. of the AD7541 depends on loun
and IOUT2 (pin 1 and pin 2) potentials being exactly equal to
GND (pin 3).

IoUT2 (2)

~-"""f----4"""-----:;==:1'

BIT' (MSB)
lilT 20-

BIT '2 (LSB)

<>-'---1'!!.-li.....!J

VOUT

TC023601

Figure 13: General DAC Circuit
with Compensation Capacitor, Co

DYNAMIC PERFORMANCE

INPUT SIGNAL WARNING

The dynamic performance of the DAC, also depends on
the output amplifier selection. For low speed or static
applications, AC specifications of the amplifier are not very
critical. For high-speed applications slew-rate, settling-time,
openloop gain and gain/phase-margin specifications of the
amplifier should be selected for the desired performance.

Because of the input protection diodes on the logic
inputs, it is important that no voltage greater than 4V
outside the logic supply rails be applied to these inputs at
any time, including power-up and other transients. To do so
could cause destructive SCR latCh-up.

6'-21
Note: All typical values have been guaranteed by characterization and are not tested.

Z ADC0802-ADC0804

8 8·Bit IIP·Compatible
9
§

.

AID Converters

I

§

GENERAL DESCRIPTION

FEATURES

The ADC0802 family are cMOS 8-bit successive approximation A/Dconverfers which use a modified potentiometric
ladder, and are designed to operate with the 8080A control
bus via three-state outputs. These converters appear to the
processor as memory locations or lID ports, and hence no
interfacing logic is required.
The differehtial analog voltage input has good commonmode-rejection, and permits offsetting the analog zeroinput-voltage value. In addition, the voltage reference input
can be adjusted to allow· encoding any smaller analog
voltage span to the full 8 bits of resolution:

.• SOC4S and SOCSO/S5 Bus Compatible - No
Interfacing Logic Required
'
• Conversion Time < 100ps
• Easy Interface to Most Microprocessors
• Will Operate in a "Stand Alone" Mode
• Differential Analog Voltage Inputs
• Works With Bandgap Voltage References
• TTL Compatible Inputs and Outputs
• On-Chip Clock Generator
• OV to 5V Analog Voltage Input Range (Single
+5V Supply)
• No Zero-Adjust Required

ORDERING INFORMATION
PART
NUMBER

TEMPERATURE
RANGE

ERROR

PACKAGE

ADC0802LCN
ADC0802LCD
ADC0802LD

± 1/2 bit no adjust

O°C to +70~C
-25°C to +85°C
-55°C to +125°C

20 pin Plastic DIP
20 pin CERDIP
20 pin CERDIP

ADC0803LCN
ADC0803LCD
ADC0803LD

± 112 bit adjusted full-scale

O°C to +70°C
-25°C to +85°C
- 55°C to + 125°C

20 pin Plastic DIP
20 pin CERDIP
20 pin CERDIP

ADC0804LCN
ADC0804LCD

± 1 bit no adjust

O°C to +70°C
-25°C to +85°C

20 pin Plastic DIP
20 pin CERDIP

cs
iiii
11

12
13
14
15
18
17
18

WR
INTR
DBt
DS.
DIIs
DII<
DB,

AID

DBa
DB,
DBa

80003201

TOP VIEW
GDOO6311

Figure 1: Typical Application

6-22
Note: All typical values have been guaranteed by characterization' and are not tested.

(Outline dwg. CD, CN)
Figure 2: Pin
Configuration

ADC0802-ADC0804
AD

2

READ

CS~'[:::::::~::~==:>
WAC
3

________-J~jr~>-~~"'~"~=~R~~~~S~H~IFT~R~E~G~IS~T~E~R~-.
"0" = BUSY AND RESET STATE

~~

__ RESET

INPUT PROTECTION
FOR All lOGIC INPUTS

ClKR

j::

INPUT

19

ClK

TOINTERNAl
CIRCUITS
BV",30V

I START F/F

V"

START
CONVERSION

20

D

(VREF)

VREFJ2

o-9---4~

__--IH LA:,.oi

R

1++++-+------4 SU;;::g~VE

DECODER

SL

8-BIT
SHIFT
REGISTER
R ......-.......I~......

REGISTER
AND lATCH

IF RESET = "0"

RESET
INTRF/F

AGND

8

DAC
VOUT

Q

VIN( +) O"-+-f-+{D-~

DIGITAL OUTPUTS
3-STATE CONTROL
"1" = OUTPUT ENABLE

~----------___________...J

8000330\

Figure 3: Functional Diagram of ADC0802-ADC0804

&-23
Note: All typical values have been guaranteed by characterization and are not tested.

-.8

.D~DIl

o ADC0802~ADC0804

9
I

""

.0

"CiO

§

ABSOLUTE MAXIMUM RATINGS

OPERATING RATIN(lS

Supply Voltage ................................................. 6.SV
Voltage at Any Input.. ................. -0.3V to (V++0.3V)
Storage Temperature Range ............ .;.6S"C to+1S0'C
Package Dissipation at TA = +2S"C ......... ·...... :.875mW
Lead Temperature (Soldering. 10sec) ................. 300·C

Temperature Range·
ADC0802/03LD .................... -SS'C to +12S·C
ADC0802/03/04LCD ............... -40·C to +8S'C
ADC0802/03/04LCN .................. O'C to + 70'C
Supply Voltage Range ............................ 4.SV to 6.3V

Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure· to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (Notes 1 and 7)
Converter Specifications: v+= SV. VREF/2= 2.S00V. TMIN:::: TA:::: TMAX

and fCLK = 640kHz unless otherwise

stated.
MAX

UNIT

ADC0802:
TotsJ Unadiusted Error

Completely Unadiusted

±1/2

LSB

ADC0803:
Total Adjusted Error

With

±1/2

LSB

ADC0804:
Total Unadjusted Error

Completely Unadjusted

±1

LSB

VREF/2 -Input Resistance

Input Resistance at Pin 9

Analog Input Voltage Range

(Note 2)

DC Common;Mode Rejection

Over Analog Inp!Jt Voltage Range

Power Supply SenSitivity

V+ = 5V ±10% Over Allowed
Input Voltage Range

PARAMETER

TEST CONDITIONS

TYP

Full Scale Adjust

PARAMETER

1.0

1.3

kn
V+ +0.05

V

±1/16

±1/8

LSB

± 1/16

± 1/8

lSB

GND-0.05

DC ELECTRICAL CHARACTERISTICS
Digital Levels and DC Specificatio,.s:
SYMBOL

MIN

v+ '" SV and TMIN:::: TA:::: TMAX. unless otherwise noted.
TEST CONDITIONS

MIN
2.0

TYP

MAX

UNIT

v+

V

0.8

V

CONTROL INPUTS (Note 6)

VINH

Logical "I" Input Voltage
(Except Pin 4 ClK IN)

v+ - 5.25V

VINl

loQical "0" Input Voltage
(Exqept Pin 4 elKIN)

v+ = 4.75V

v+ ClK

ClK· IN (Pin 4) Positive Going
Threshold Voltage

2.7

3.1

3.5

V

V- ClK

ClK IN (Pin 4). Negative Going
Threshold Voltage

1.5

1.8

2.1

V

0.6

1.3

2.0

V

0.005

1

pA

2.5

rnA

0.4

V

3

IINHI

ClK IN (Pin 4) Hysteresis
(Vc!LK) - (VCLI()
logical "I" Input Current
(All Inputs)

IINlO

logical "0" Input Current
(All Inputs)

VIN=OV

Supply Current (Includes
Ladder Current)

fClK = 640kHz.
TA = +25"C and
= HI

VH

1+

DATA OUTPUTS AND

VIN=5V
-1

1.3

es

pA

-0.005

IIiffli

logical "0" Output Voltage

la·1.6mA
V" - 4.75V

VOH

logical "I" Output Voltage

10= -360pA
V+ = 4,75V

2.4

V

IlO

3-State Disabled Output
Leakage (All Data Buffers)

VOUT~OV

-3

pA
pA

VOL

VOUT=5V

6-24
Note: All typical values have _been guaranteed by characterization and are not tested.

ADC0802-ADC0804
DC ELECTRICAL CHARACTERISTICS (CO NT.)
TEST CONDITIONS

MIN

TYP

IsoUACE

SYPt(lBOL

Output Short Circuit Current

PARAMETER

VOUT Short to Gnd TA = +25°C

4.5

6

MAX

UNIT
rnA

ISINK

Output Short Circuit Current

VOUT Short to V+ TA- +25°C

9.0

16

rnA

NOTES: 1. All voltages are· measured with respect to GND, unless otherwise specified. The separate AGND point should always be wired to
the DGND, being careful to avoid ground loops.
2. For VIN( _) ,., VIN( +) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block
Diagram) which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the
V + supply. Be careful, during testing at low V + levels (4.SV), as high level analog inputs (SV) can cause this input diode to
conduct-especially at elevated temperatures, and cause errors for analog inputs near full-scale. As long as the analog VIN does not
exceed ·the supply voltage by more than SOmV, the output code will be correct. To achieve an absolute OV to SV input voltage
range will therefore require a minimum supply voltage of 4.950V over temperature variations, initial tolerance and loading.
3. With V + = 6V, the digital logic interfaces are no longer TTL compatible.
4. With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the
conversion process.
S. The CS input is assumed to bracket the WR strobe input so that timing is dependent on the WR pulse width. An arbitrarily wide
pulse width will· hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR
pulse (see Timing Diagrams).
6. ClK IN (pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately.
7. None of these AIDs requires a zero-adjust. However, if an all zero code is desired for an analog input other than O.OV, or if a
narrow full-scale span exists (for example: 0.5V to 4.0Y full-scale) the YIN( _) input can be adjusted to achieve this. See Zero
Error on page 10 of this data sheet.

AC ELECTRICAL CHARACTERISTICS
Timing Specifications: v+
SYMBOL

= 5V and TA = +25°C unless otherwise stated.

PARAMETER

TEST CONDITIONS
y+ = 6V (Note 3)
y+ =5Y

MIN

TYP

MAX

UNIT

100
100

640
640

1280
800

kHz
kHz

fClK

Clock Frequency

Ieoo.

Clock Periods per Conversion (Note 4)

CR

Conversion Rate In Free-Running Mode

tw(WA)1

Width of

tace

Access Time (Delay from Falling Edge of
RD to Output Data Valid)

Cl = 100pF (Use Bus Driver IC
for Larger CLl

135

200

ns

tlh, tOh

3-State Control (Delay from Rising Edge
of m'i to HI-Z State)

Cl = 10pF, Rl = 10k
(See 3-State Test Circuits)

125

250

ns

tWI> tAl

Delay from Falling Edge of
Reset of IN'!'Fi

300

4S0

ns

CIN

Input Capacitance of logic
Control Inputs

S

7.5

pF

GoUT

3-State Output CapaCitance (Data Buffers)

5

7.S

pF

WR

62

WR

tied to WR with
CS = OY, fClK = 640kHz

v·
90%
50%

DATA
OUTPUTS

::~:::'h
~

GND------

1r=2Ono

2.4Y-:--N-=;:;--

M.

iiii
O.8V

DATA

c..OUTPUT

CS

T

T

TC02OBOI

Figure 4: 3-State Test Circuits and Waveforms

6-25
Note: All typical values have been guaranteed by characterization and are not tested.

ns

y.

iffi

T

WF010701

convls

100

to

y+

TC020701

8888

CS - OY (Note 5)

Input (Start Pulse Width).

73

IN'!'Fi

DATA Y+

I;

OUTPUTS Y O l - - - I10%

1r=2Ons
WF010801

IIO~OIl

3 ···ADC0802-ADC0804

co

8
~I

(\I

§
~

TYPICAL PERFORMANCE CHARACTERISTICS
Delay From Failing Edge of .RD to Output Data
Valid vs load Capacitance

logic Input Threshold Voltage vs Supply Voltage

~

1.8

~
~

1.7

9

1.6

>.

i

-SS·C S TA s +125"0
400

I,;

at 1.5

j!:
!;
II.
!

;I

1.4
100

So! 1.34.50

5.00
5.25
s.so
V+ -SUPPLY VOLTAGE (V)

~

o

4.7S

200 400 800 800 1000
LOAD CAPACITANCE (pF)
OP014501

OPQ14401

ClK IN Schmitt. Trip levels VI Supply Voltage

:g

3.5

~
;!!

3.1

~
a

2.7

I
I

I--

I--

...

Yr+

-ssoc s TA s

i2.3

I I
I I

j!:
!

Yr-

a

fClK vs Clock Capacitor

1.'

+l25°C

II\,..- )

,

1.5

~~~I~\
100 1,.,...I-..J..J..u.IJ.LL....lo.L..J..AI.J.I,IJI
10
·100
1000
CLOCK CAPACI1'OR (PF)

4.50
4.75
5.00
5.2S
5.50
Y+ -SUPPLYYOLTAGE(V)
OPOl4601

OP01470i

Effect of Unadjusted Offset Error

Full-SCale Error vs FClK

16

v+ =4.5V

Ido

'f-

10

...

8

Iii
!!!
...
0

y+ -8V

o

4IJII

12

a:

ia:
-y+ =5V

14

8
4
2
0
0.01

800 1200 1800 2000

YlN(+)-VtN(-)-ov.
ASSUMES Vos-zmv.

THIS SHOWS THE NEED
FOR A ZERO ADJ. I'
THE SPAN IS REDUCED.

tcLK(lcHz)

0.1

1.0

VREFI2(V)
0P014801

OP014901

Power Supply Current vs Temperature

Output Current vs Temperature vs VREF/2 Voltage

e

f

i

'eLK-840kHz

~

""f-

~

t
iil

~

-~NK

\Iour=o.4V

2
-50-25 0 25 50 75 100 125
TA-AMBIENTTEMPERATURE("C)
0P015001

v'+'.lJv

Y'+~Uv

131.3

~OUT=2.4V

4

1.6

i ::

·.!o~RC~

8

13

I

f

v+-sv
I I I I
DATA OUTPUT
BUFFERS

i

1.2

iL

1.0
-50 -25 0 25 50 75 100 125
TA-AMBIENT TEMPERATURE ("C)

V+
1.1

=4.~Y

OP015101

6--26
Note: All typical values have been guaranleed by characterization and are not tested.

ADC0802-ADC0804
Start Conversion

_______ A

-~
_________

WR

I

ACTUAL INTERNAL
ITATUSOFTHE

IWIiiiiJI

I

I

j-

~P ________________~I~'~~

,

(LAST DATA WAS READ.

I

·BUSY"

DATA IS VALID IN
OUTPUT LATCHES

'~'N~O~T~B~~Y'J'

1 TO a x 1Ife... ----l--INTPNAL Tc

tv,
WF010901

Output Enable and Reset INTR

OUT=-- - - - -WF011011

Figure 5: Timing Diagrams
Note: All liming is measured from the 50% vollage points.

The error curve of Figure 6b shows the worst case
transfer function for the ADC0802. Here the specification
guarantees that if we apply an analog input equal to the
LSB analog voltage center-value, the AID will produce the
correct digital code.

UNDERSTANDING AID ERROR SPECS
A perfect AID transfer characteristic (staircase waveform) is shown in Figure 6a. The horizontal scale is analog
input voltage and the particular points labeled are in steps
of 1LSB (19.53mV with 2.5V tied to the VREF/2 pin), The
digital output codes which correspond to these inputs are
shown as 0 - 1, 0, and 0 + 1. For the perfect AID, not only
will center-value (A - 1,A,A + 1,. . .) analog inputs produce
the correct output digital codes, but also each riser (the
transitions between adjacent output codes) will be located
± Y2 LSB away from each center-value. As shown, the risers
are ideal and have no width. Correct digital output codes will
be provided for a range of analog input voltages which
extend ± Y2 LSB from the ideal center-values. Each tread
(the range of analog input voltage which provides the same
digital output code) is therefore 1LSB wide.

Next to each transfer function is shown the corresponding error plot. Notice that the error includes the quantization
uncertainty of the AID. For example, the error at point 1 of
Figure 6a is + 1,12 LSB because the digital code appeared Y2
LSB in advance of the center-value of the tread. The error
plots always have a constant negative slope and the abrupt
upside steps are always 1LSB in magnitude, unless the
device has missing codes.

FUNCTIONAL DESCRIPTION
A functional diagram of the ADC0802 series of AID
converters is shown in Figure 3. All of the package pinouts
6-27

Nole: All typical values have been guaranleed by characterizalion and ara not tested.

~ ADC0802~ADC0804

I
I

I

are shown and the major logic control paths are drawn in
heavier-weight lines. The device operates on the successive approximation principle (see APPLICATION NOTE
A016 and A020 for a more detailed description of this
principle). Analog switches are closed sequentially' by
successive-approximation logic until the analog differential
input voltage [VIN( +) - VIN( -)1 matches a voltage derived
from a tapped resistor string across the reference voltage.
The most significant bit is tested first and afterS comparisons (64 clock cycles), an S-bit binary code (1111 1111 =
full-scale) is transferred to an output latch.

Digital Details
The converter is started by having CS and WR simultaneously low. This sets the start flip-flop (F/F) and the
resulting "1" level resets the S-bit shift register, resets the
Interrupt (INTR) F/F and inputs a "1" to the D flip-flop,
DFF1, which is
the input end of the S-bit shift register.
Internal clock signals then transfer tllis "1" to the Q output
of DFF1. The AND gate, G1, combines this "1" output with
a clock signal to provide a reset Signal to t~start.£lF. If
the set signal is no longer present (either WR or CS is a
"1"), the start F/F is reset and the 8-bit shift register then
can have the "1" clocked in, which starts the conversion
process. If the set signal were to still be present, this reset
pulse would have no effect (both outputs of the start F/F
would be at a "1" level) and the S-bit shift register would
continue to be held in the reset mode. This allows for
asynchronous or wide CS and WR signals.
After the "1" is clocked through the S-bit shift register
(which completes the SAR operation) it appears as the
input to DFF2. As soon as this "1" is output from the shift
register, the AND gate, G2, causes the new digital word to
transfer to the 3-state output latches. When DFF2 is
subsequently clocked, the Q output makes a high-to-Iow
transition which causes the INTR F/F to set. An inverting
buffer then supplies the INTR output Signal.
When data is to be read, the combination of both CS and
RD being low will cause the INTR F/F to be reset and the 3state output latches will be enabled to provide the 8-bit
digital outputs.

at

The normal operation proceeds as follows. On the highto-low transition of the WR input, the internal SAR latches
and the Shift-register stages are reset, and the INTR output
will be set high. As long as the C'S input and iNA input
remain low, the AID will remain in a reset state. Conversion will start from 1 to 8 clock periods after at least
one of these inputs makes a low-to-high transition.
After the requisite number of clock pulses to complete the
conversion, the INTR pin will make a high-to-Iow transition.
This can be used to interrupt a processor, or otherwise
Signal the availability of a new conversion. A RD operation
(with CS low) will clear the INTR line high again. The device
may be operated in the free-running mode by connecting
INTR to the WR input with C'S = O. To ensure start-up under
all possible conditions,. an external WR pulse is required
during the first power-up cycle. A conversion-In-process can
be interrupted by islluing a second start command.
Transfer Function

Error Plot
+1LSB / - - - - - - - -

8~ 0+1

.~

I
I

I

_J. ___ .1

_4 _ _ 1.

I

I
I

I

___5__ _

/--+-\-t-'H---\-'

3i7
:I
I
I

1

+--,-_-1

. ST'i
I

0

~ 0-1

~

+1/2LSB

-II2LSB

I

2

4

I
I

QUANT.
ERROR

6

I

-1LSB ' - - - - ' - - ' - - - ' - - A-1
A A+1

A-I A A+l
ANALOG INPUT (\I)NI

ANALOG INPUT (V,N)

SCOO4301

SCOOMOI

a) Accuracy = ±O LSB; A Perfect AID
Transfer Function

Error Plot

+1~BI------.r----

-1 LSB '--_-'-_=---1._ _

A-I A A+l
ANALOG INPUT (ViNI

A-1

A

A+1

ANALOG INPUT (VIN)

SC004701

SCOO4BOI

b) Accuracy = ± h LSB

Figure 6: Clarifying the Error Specs of an AID Converter

6-28
Note: All typical values have been guaranteed by characterization and are not tested.

ADC0802-ADC0804
Digital Control Inputs

Analog Input Current

The digital control inputs (CS. RD. and WR) meet
standard TTL logic voltage levels. These signals are
essentially equivalent to the standard AID Start and Output
Enable control signals. and are active low to allow an easy
interface to microprocessor control busses. For non-microprocessor based applications. the CS input (pin 1) can be
grounded and the standard AID Start function obtained by
an active low pulse at the WR input (pin 3). The Output
Enable function is achieved by an active low pulse at the
RD input (pin 2).

The internal switching action causes displacement currents to flow· at the analog inputs. The voltage on the onchip capacitance to ground is switched through the analog
differential input voltage. resulting in proportional currents
entering the V'N( +) input and leaving the V'N( _) input.
These current transients occur at the leading edge of the
internal clocks. They rapidly decay and do not inherently
cause errors as the on-chip comparator is strobed at the
end of the clock period.

Input Bypass CapaCitors

Analog Operation

Bypass capacitors at the inputs will average these
charges and cause a DC current to flow through the output
resistances of the analog signal sources.. This charge
pumping action is worse for continuous conversions with
the V'N( +) input voltage at full-scale. For a 640kHz clock
frequency with the V'N( +) input at 5V. this DC current is at a
maximum of approximately 5/lA. Therefore. bypass capacItors should not be used at the analog Inputs or the
VREF/2 pin for high resistance sources ( > 1kill. If input
bypass capacitors are necessary for noise filtering and high
source resistance is desirable to minimize capaCitor size,
the effects of the voltage drop across this input resistance.
due to the average value of the input current, can be
compensated by a full-scale adjustment while the given
source resistor and input bypass capaCitor are both in
place. This is possible because the average value of the
input current is a precise linear function of the differential
input voltage at a constant conversion rate.

The analog comparisons are performed by a capacitive
charge summing circuit. Three capacitors (with precise
ratioed values) share a common node with the input to an
auto-zeroed comparator. The input capacitor is switched
between V'N( +) and V'N( _). while two ratioed reference
capacitors are switched between taps on the reference
voltage divider string. The net charge corresponds to the
weighted difference between the input and the current total
value set by the successive approximation register. A
correction is made to offset the comparison by 1.12 LSB (see
Figure 6a).

Analog Differential Voltage Inputs and
Common-Mode Rejection
This AID gains considerable applications flexibility from
the analog differential voltage input. The V,N(-) input (pin 7)
can be used to automatically subtract a fixed voltage value
from the input reading (tare correction). This is also useful in
4mA-20mA current loop conversion. In addition. commonmode noise can be reduced by use of the differential input.

Input Source Resistance
Large values of source resistance where an input bypass
capaCitor is not used, will not cause errors since the input
currents settle out prior to the comparison time. If a lowpass filter is required in the system, use a low-value series
resistor ( :5 1kil) for a passive RC section or add an op amp
RC active low-pass filter. For low-source-resistance applications. (:5 1kill. a 0.11lF bypass capaCitor at the inputs
will minimize EMI due to the series lead inductance of a long
wire. A 100il series resistor can be used to isolate this
capaCitor (both the Rand C are placed outside the
feedback loop) from the output of an op amp. if used.

The time interval between sampling V'N( +) and V'N( _) is
41.12 clock periods. The maximum error voltage due to this
slight time difference between the input voltage samples is
given by:
~Ve(MAX)

= (V p)(21Tfem ) [ -4.5]

fCLK

where:
~Ve is the error voltage due to sampling delay
Vp is the peak value of the common-mode voltage
fern is the com mon.-mode frequency

Stray Pickup
The leads to the analog inputs (pins 6 and 7) should be
kept as short as possible to minimize stray signal pickup
(EM I). Both EMI and undesired digital-clock coupling to
these inputs can cause system errors. The source resistance for these inputs should. in general, be kept below
.5kil. Larger values of source resistance can cause undesired signal pickup. Input bypass capaCitors. placed from
the analog inputs to ground, will eliminate this pickup but
can create analog scale errors as these capcitors will
average the transient input switching currents of the AID
(see Analog Input Current). This scale error depends on
both a large source resistance and the use of an input
bypass capaCitor. This error can be compensated by a full·
scale adjustment of the AID (see Full-Scale Adjustment)
with the source resistance and input bypass capacitor in
place, and the desired conversion rate.

For example. with.a 60Hz common-mode frequenqy. fern.
and a 640kHz AID clock, fCLK, keeping this error to 1.14 LSB
(-5mV) would allow a common-mode voltage. Vp. given by:
[~Ve(MAX)(fCLK)]
Vp = - - - - - - ' (21Tfem )(4.5)

or
Vp =

(5x10- 3) (640 x 103)
.

(6.28) (60) (4.5)

",,1.9V

The allowed range of analog input voltage usually places
more severe restrictions on input common-mode voltage
levels than thiS.
An analog input voltage with a reduced span and a
relatively large zero offset can be easily handled by making
use of the differential input (see Reference Voltage Span
Adjust).

Reference Voltage Span Adjust
For maximum application flexibility, these AIDs have
been designed to accommodate a 5V. 2.5V or an adjusted
6-29

Note: All typical values 'have been guaranteed by characterization and are not tested.

" ADCOa02-ADCOa04

§c

voltage reference. This has been achieved in the design of
thelC as shown in Figure 7.

VREF'
(5V)

I

I

20

>-....w~-+ TO
VREFI2

~

. FS>._--I
ADJ.

R

VREFI2

I I

9

,- t-}fR

: DECODE

TO
2""I1--+-......,Z=E=R:"::O:":S:7'H:::IFT:=':'V=O""
::cA:":G=E:----+ VIN( -)
LT

DIGITAL
CIRCUITS

-i

ANALOG
CIRCUITS

TC020901

I

Figure 8: Offsetting the Zero of the
ADC0802 and Performing an Input Range
.
(Span) Adjustment

t-}-

~}-

5V
(VREF)

....,

R
AGND 8

.~

DG~~O

VaN
:!:10V

2R
6 VIN(+)

TC021001

2R

Figure 7: The VREFERENCE Design on the IC

v+

ADC0802AOC0804

7

~

'Tl0~F
. ':'

~ VaN(-)

';:-

Notice that the reference voltage for the IC is either V2 of
the voltage which is applied to the V+ supply pin, or is
equal to the voltage which is externally forced at the
VREF/2 pin. This allows for a pseudo-ratiometric voltage
reference using, for the V + supply, a 5V reference voltage.
Alternatively, a voltage less than 2.5V can be applied to the
VREF/2 input. The internal gain to the VREF/2 input is 2 to
allow this factor of 2 reduction in the reference voltage.

TC036201

Figure 9: Handling ±10V Analog Input Range

5V

Such an adjusted reference voltage can accommodate a
reduced span or dynamic voltage range of the analog input
voltage. If the analog input voltage were to range from 0.5V
to 3.5V, instead of OV to SV, the span would be 3V. With
0.5V applied to the VIN(-) pin to absorb the offset, the
refererice voltage can be made equal to V2 of the 3V span .
or 1.5V: The AID now will encode the VIN(+) signal from
O.SV to 3.5V with the 0.5V input corresponding to zero and
the 3.5V input corresponding to full-scale. The full 8 bits of
resolution are therefore applied over this reduced analog
input voltage range. The requisite connections are shown in
Figure 8. For expanded scale inputs, the circuits of Figures
9 and 10 can be used.

(VREF)

R
VIN
:!:5V

R

'"
v+

~

ADC0802ADC0804

f

6 VaN(+)

~

+
10PF

'liN( -)

TC036301

Figure 10: Handllng±5V Analog Input Range

Reference Accuracy Requirements
The converter can be operated in a pseudo-raticimetric
mode or an absolute mode. In ratiometric converter applications, the magnitude of the reference voltage is a factor in
both the output of the source transducer and the output of
the AID converter and therefore cancels out in the final
digital output code. In absolute conversion applications,
both the initial value and the temperature stability of the
6-'30
Note: All typical values have been guaranteed by characterization and are not tested.

ADC0802-ADC0804
the magnitude of the VREF/2 input (pin 9) for a digital output
code which is just changing from 1111 1110 to 1111 1111.
When offsetting the zero and using a span-adjusted VREFI
2 voltage, the full-scale adjustment is made by inputting
VMIN to the VIN(-) input of the AID and applying a voltage
to the VIN( +) input which is given by:

reference voltage are important accuracy factors in the
operation of the AID converter. For VREF/2 voltages of
2.5V nominal value, initial errors of ±10mV will cause
conversion errors of ± 1LSB due to the gain of 2 of the
VREF/2 input. In reduced span applications, the initial value
and the stability of the VREF/2 input voltage become even
.more important. For example, if the span is reduced to 2.5V,
the analog input LSB voltage value is correspondingly
reduced from 20mV (5V span) to 10mV and 1LSB at the
VREF/2 input becomes 5mV. As can be seen, this reduces
the allowed initial tolerance of the reference voltage and
requires correspondingly less absolute change with temperature variations. Note that spans smaller than 2.5V place
even tighter requirements on the initial accuracy and
stability of the reference source.
In general, the reference voltage will require an initial
adjustment. Errors due to an improper value of reference
voltage appear as full-scale errors in the AID transfer
function. IC voltage regulators may be used for references if
the ambient temperature changes are not excessive.

VIN( + )fsadj = VMAX - 1.5[

where:
VMAX = the high end of the analog input range
and
VMIN = the low end (the offset zero) of the analog
range. (Both are ground referenced.)

Clocking Option
The clock for the AID can be derived from an external
source such as the CPU clock or an external RC network
can be added to provide self-clocking. TheCLK IN (pin 4)
makes use of a Schmitt trigger as shown in Figure 11.
Heavy capacitive or DC loading of the CLocK R pin
should be avoided as this will disturb normal converter
operation. Loads less than 50pF, such as driving up to 7
AID converter clock inputs from a single CLK R pin of 1
converter, are allowed. For larger clock line loading, a
CMOS or low power TTL buffer or PNP input logic should be
used to minimize the loading on the CLK R pin (do not use a
standard TTL buffer).

Zero Error
The zero of the AID does not require adjustment. If the
minimum analog input voltage value, VIN(MIN), is not
ground, a zero offset can be done. The converter can be
made to output 0000 0000 digital code for this minimum
input' voltage by biasing the AID VIN(-) input at this
VIN(MIN) value (see Applications section). This utilizes the
differential mode operation of the AID.
The zero error of the AID converter relates to the
location of the first riser of the transfer function and can be
measured by grounding the VIN(-) input and applying a
small magnitude positive voltage to the VIN( +) input. Zero
error is the difference between the actual DC input voltage
which is necessary to just cause an output digital code
transition from 0000 0000 to 0000 0001 and the ideal 1.12
LSB value (Y2 LSB = 9.8mV for VREF/2 = 2.500V).

Full-Scale Adjust

Restart During a Conversion
If the AID is restarted (CS and WR go low and return
high) during a conversion, the converter is reset and a new
conversion is started. The output data latch is not updated if
the conversion in progress is not completed. The data from
the previous conversion remain in this latch.

Continuous Conversions
In this application, the CS input is grounded and the WR
input is tied to the INTR output. This WR and INTR node
should be momentarily forced to logic low following a
power-up cycle to insure circuit operation. See Figure 12 for
details.

.

The full-scale adjustment can be made by applying a
differential, input voltage which is 1Y2 LSB down from the
desired analog full-scale voltage range and then adjusting

\".J
ClKR
19

ADC0802ADC0804

R

r

ClK
IN

C

4

(V MAX - VMIN)]
,
256

~

V-

ClK

1
'ClK= 1.1 RC
R=10kO

AF021911

Figure 11: Self-Clocking the AID

6-31
Note: All typical values have been guaranteed by characterization and are not tested.

3 ADC0802-ADC0804

I

r--.________~1~OkI\r-.,..__------__.:;5V (OR VREF)*

I

C\I

I

,--",--o-.;..1=.., CS

L-<>-...:2~RD
~~--~*-~...:3~-W-R
'-----i--C.-4=-1CLK IN

~:>-:~INTR
7

VJN(+)

ADC0802-

ADC0804

o--o--:'-I:~~

DATA
OUTPUTS

10 VREFI2

DOND
COOO641 I

Figure 12: Free-Running Connection
inductance tantalum filter capacitor should be used close to
the converter V + pin, and values of 1JJ.F or greater are
recommended. If an unregulated voltage is available in the
system, a separate SV voltage regulator for the converter
(and other analog circuitry) will greatly reduce digital noise
on the V + supply. An ICL7663 can be used to regulate such
a supply .from an input as low as S.2V.

Driving the Data Bus
This CMOS AID, like MOS microprocessors and memories, will require a bus driver when the total capacitance of
the data bus gets large. Other circuitry, which is tied to the
data bus, will add to the total capacitive loading, even in 3state (high-impedance mode). Backplane bussing also
greatly adds to the stray capacitance of the data bus.
There are some alternatives available to the designer to
handle this problem. Basically, the capacitive loading of the
data bus slows down the response time, even though DC
specifications are still met. For systems operating with a
relatively slow CPU clock frequency, more time is available
in which to establish proper logic levels on the bus and
therefore higher capacitive loads can be driven (see Typi-

Wiring and Hook-Up Precautions
Standard digital wire-wrap sockets are not satisfactory for
breadboarding with this AID converter. Sockets on PC
boards can be used. All logic signal wires and leads should
be grouped and kept as far away as possible from the
analog signal leads. Exposed leads to the. analog inputs can
cause undesired digital noise and hum pickup;. therefore,
shielded leads may be necessary in many applications.

cal Performance Characteristics).
At .higher CPU clock frequencies time can be extended
for 110 reads (and/or writes) by inserting wait states (80BO)
or using clock-extending circuits (6BOO).
Finally, if time is short and capacitive loading is high,
external bus drivers must be used. These can be 3-state
buffers (low power Schottky is recommended, such as the
74LS240 series) or special higher-drive-current products
which are deSigned as bus drivers. High-current bipolar bus
drivers with PNP inputs are recommended.

A single-point analog ground should be used which is
separate from the logic ground points. The power supply
bypass capaCitor and the self-clocking capacitor (if used)
should both be returned to digital ground. Any VREF/2
bypass capaCitors, analog input filter capacitors, or input
signal shielding should be returned to the analog ground
point. A test for proper grounding is to measure the zero
error of the AID converter. Zero errors in excess of Y4 LSB
can usually be traced to improper board layout and wiring
(see Zero Error for measurement). Further information can
be found in A01 B.

Power Supplies
Noise spikeS on the V + supply line can cause conversion
errors as the comparator will respond to this noise. A .low-

6-32
Note: All typical values have been guaranteed by characterization and are not tested.

ADC0802-ADC0804
For example, for an output LED display of 1011 0110, the
MS character is hex B (decimal 11) and the LS character is
hex (and decimal) 6, so

TESTING THE A/D CONVERTER
There are many degrees of complexity associated with
testing an AID converter. One of the simplest tests is to
apply a known analog input voltage to the converter and
use LEOs to display the resulting digital output code as
shown in Figure 13.

VOUT = (-11 + - 6) (5.12) = 3.64V.
16 256
Figures 14 and 15 show more sophisticated test circuits.

For ease of testing, the V~EF/2 (pin 9) should be
supplied with 2.560V and a V supply voltage of 5.12V
should be used. This provides an LSB value of 20mV.
If a full-scale adjustment is to be made, an analog input
voltage of 5.090V (5.120 - fY2 LSB) should be applied to
the VIN( +) pin with the VIN( _) pin grounded. The value of
the VREF/2 input voltage should be adjusted until the digital
output code is just changing from 1111 1110 to 1111 1111.
This value of VREF/2 should then be used for all the tests.

R
ANALOG

..c··

INPUT

",...

R
100XANALOG

ERROR VOLTAGE

15OpF-;;

lD003501

,.

3

N.O.

STMi

O.1"F

17

5

16

DIGITAL
INPUT

A0C0802ADC0804

7

'::"

2.560V
IIREF/2

G.1 PF

..
6

YlN(+)

T

Figure 14: AID Tester with Analog Error
Output. This circuit can be used to generate
"error plots" of Figure 6.

TEST

D

12

10

11

~~~~
~
lDOO3601

Figure 15: Basic "Digital" AID Tester

'"

•
DOND

AID UNDER

15

13

. - - - - - , DIGITAL
OUTPUT

APPLICATIONS
Interfacing 8080/85 or Z-SO
Microprocessors
This converter has been designed to directly interface
with 8080/85 or Z-80 Microprocessors. The 3-state output
capability of the AID eliminates the need for a peripheral
interface device, although address decoding is still required
to generate the appropriate CS for the converter. The AID
can be mapped into memory space (using standard memory-address decoding for CS and the MEMR and MEMW
strobes) or it can be controlled as an I/O device by using
the I/O Rand I/O W strobes and decoding the address bits
AO ~ A7 (or address bits A8 ~ A15, since they will contain
the same 8-bit address information) to obtain the CS input.
Using the I/O space provides 256 additional addresses and
may allow a simpler 8-bit address decoder, but the data can
only be input to the accumulator. To make use of the
additional memory reference instructions, the AID should
be mapped into memory space. See A020 for more
discussion of memory-mapped vs I/O-mapped interfaces.
An example of an AID in I/O space is shown in Figure 16.

Ukll
(I)

LEOs
(I)
LOO0341I

Figure 13: Basic Tester for the AID
The digital-output LED display can be decoded by
dividing the 8 bits into 2 hex characters, one with the 4
most-significant bits (MS) and one with the 4 least-significant bits (LS). The output is then interpreted as a sum of
fractions times the full-scale voltage:
MS LS)
VOUT= (-+-(5.12)V.
16 256

6-33
Note: All typical values have been guaranteed by characterization and are not tested.

rI
•

3 ADC0802-ADC0804

·CD

§

.....

INT(14)

.....

I
(II

UOWR(27)·

i

§

UORD(25)·

10k
•

1

-

'-"

CS

~ \iii
iiD

4

ANALOG
INPUTS

--

'W

CLKIN

DBt

5 INTR
87 V!N(+)
V!N(-)

A0C0802AOC0804

:_~~AGND

:T ':J,
' oio

V+ 1F5V
CLKR
18
(LS8)08o
17

VREFI2
DGND

D8t

~1~F
080(13)·
r

18

DS, (18)·

D82(11)·

15
DB4 14
13
DBa
12
D8e
11
(MS8)DB7

DIb(t)*

Dib

014(5)·
DBs(18)·

DBt(20)·

DB7 (7)*

5V

I

Y

I

~

~
"'"r-~

~

T5
T4
Ta
T2
T,
TO

I

V+

OUT

Bs

8.t

8131

BUS
COMPARATOR

Ib
82

~

8,

So

1

~

I

Ao,s(38)
Ao,4 (38)
Ao,a (38)
Ao,2 (37)
Ao" (40)
Ao,o (1)

1

#,
COOO6511

Note: Pin numbers for 8228 system controller: others are 8080A

Figure 16: ADC0802 to 8080A CPU Interface
The standard control-bus signals of the 8080 (CS, RD
and WR) can be directly wired ,to the digital control inputs of
the AID, since the bus timing requirements, to allow both
starting the converter, and outputting the data onto the data
bus, are met. A bus driver should be used for larger
microprocessor Systems where the data bus leaves the PC
board and lor must drive capacitive loads larger than
100pF.

generalized strobes to provide the appropriate signals. An
advantage of operating the AID in I/O space with the Z-80
is that the CPU will automatically insert one wait state (the
RD and WR strobes are extended one clock period) to allow
more time for the I/O devices to respond. Logic to map the
AID in I/O space is shown in Figure 17. By using MREO in
place of 10RO, a memory-mapped configuration results.
Additional I/O advantages exist as software DMA routines are available and use can be made of the output data
transfer which exists on the upper 8 address lines (A8 to
A 15) during I/O input instructions. For example, MUX
channel selection for the AID can be accomplished with
this operating mode.
.
The 8085 also provides a generalized RD and WR strobe,
with an 101M line to distinguish I/O and memory requests.
The circuit of Figure 17 can again be used, with 101M in
place of 10RO for a memory-mapped interface, and an
extra inverter (or the logic equivalent) to provide 101M for
an I/O-mapped connection.

It is useful to note that in systems where the AID
converter is 1 of 8 or fewer I/O-mapped devices, no
address-decoding circuitry is necessary. Each of the 8
address bits (AO to A7) can be directly used as CS inputs,
one for each I/O device.

Interfacing the Z-80 and 8085
The Z-80 and 80B5 control buses are slightly different
from that of the 8080. General RD and WR strobes are
provided and separate memory request, MREQ, and 110
request, 10RQ, signals have to be combined with the
6-34

Note: All typical values have been guaranteed by characterization and are not tested.

ADC0802-ADC0804
Interfacing 6800 Microprocessor Derivatives
(6502, etc.)

APPLICATION NOTES
Some applications bulletins that may be found useful are
listed here:
A016 "Selecting AID Converters," by Dave Fullagar.
A018 "Do's and Dont's of Applying AID Converters," by
Peter Bradshaw and Skip Osgood.
A020 "A Cookbook Approach to High Speed Data
Acquisition and Microprocessor Interfacing," by Ed
Sliger.
A030 "The ICL7104 - A Binary Output AID Converter for
Microprocessors," by Peter Bradshaw.
R005 "Interfacing Data Converters & Microprocessors,"
by Peter Bradshaw et ai, Electronics, Dec. 9, 1976,

The control bus for the 6800 microprocessor derivatives
does not use the RD and WR strobe signals. Instead it
employs a single R/W line and additional timing, if needed,
can be derived from the cp2 clock. All 1/0 devices are
memory-mapped in the 6800 system, and a special signal,
VMA, indicates that the current address is valid. Figure 16
shows an interface schematic where the AID is memorymapped in the 6800 system. For simplicity, the CS decoding
is· shown using 1/2 DM8092. Note that in many 6800
systems, an already decoded 4/5 line is brought out to the
common bus at pin 21. This can be tied directly to the CS
pin of the AID, provided that no other devices are addressed at HEX ADDR: 4XXX or 5XXX.

Ri)2

In Figure 19 the ADC0802. series is interfaced to the
MC6800 microprocessor through (the arbitrarily chosen)
Port B of the MC6820 or MC6821 Peripheral Interface
Adapter (PIA). Here the CS pin of the AID is grounded since
the PIA is already memory-mapped in the MC6800 system
and no CS decoding is necessary. Also notice that the AID
output data lines are connected to the microprocessor bus
under program control through the PIA and therefore the
AID RD pin can be grounded.

Wii3

ADC0802ADC0804

74C32
AF022011

Figure 17: Mapping the AID as an I/O
device for use with the z-eo CPU

A
1111

1

as

~

v+

1< AD

Imz

4

5

ANALOG
INPUTS
150pFF~

•
7

(LS8)DIo

ClKIN

iNTi
VJN(+)

DB!
ADCII802ADCOII04

DIo
DBa

V!N(-)

DBt

AGND
• VREFI2
10
DGND

DBe
(MS8)DIIr

rH
,f, ?

20

f1i"
Cl.KR

DIIs

~~

F

7

'18

Dz (31) 00

Dz(3O)iiii
lit 12811321
Os (2lt(3OJ

De (27) iii

Dr(28)ijj

1

'~3

YiDM~

4

5

( ABC)
123

lID (33) 1311
01(32)1281

17
11
15
14
13
12
11

2

$V.

AI2 (22) [34J

,.,.

.A

Ala (23)iNi

A14t241(MJ

4-----"

AI, (25) [33J
VMA(5) [FJ
COOO6611

'Note 1: Numbers in parentheses refer to MC6800 CPU pinout.
"Note 2: Numbers or letters in brackets refer to standard MC6800 system common bus code.

Figure 18: ADC0802 to MC6800 CPU Interface

6-35
Note: All typical values have been guaranteed by characterization and are not tested.

18
19
10k

CSt
CB2

y

1~

1

d,
ANALOG
INPUTS

....

-

2

iii

Wi
~
4

CLKIN
5
8- INTA
ViN(+)
7
ViN(-)
8
AGND

'=d,"=:F
r <>io

150pF

CS

9

VREF/2
DGND

'-../

Y+
CLKA

MC8820

~5Y
19

18
(LS8)DBo
17
DB1
18
ADC0802DB:! 15
ADC0804

DBa 14

D8.t
13
Dis
12
Die
11
(MSB)DB7

(IICS852O)

10
11
12
13
14

15
18
17

No

PIA

PSt

PB2
PB3

PB.t

PBs
Pie
PBr

C[)l)06711

Figure 19: ADC0802 to MC6820 PIA Interface

6-36
Note: All typical values have been guaranteed by characterization and are not tested.

p
....

ICL 7106/ICL 7107
3 Y2-Digit LCD/LED
Single-Chip A/D Converter

i

......

GENERAL DESCRIPTION

FEATURES

The IntersillCL7106 and 7107 are high performance, low
power 3 h-digit AID converters containing all the necessary
active devices on a single CMOS I.C. Included are sevensegment decoders, display drivers, a reference, and a
clock. The 7106 is designed to interface with a liquid crystal
display (LCD) and includes a backplane drive; the 7107 will
directly drive an instrument-size light emitting diode (LED)
display.
The 7106 and 7107 bring together an unprecedented
combination of high accuracy, versatility, and ,true economy.
It features auto-zero to less than 10/lV, zero drift of less
than 1/lV
input bias current of 10 pA max., and rollover
error of less than one count. True differential inputs and
reference are useful in all systems, but give the designer an
uncommon advantage when measuring load cells, strain
gauges and other bridge-type transducers. Finally, the true
economy of single power supply operation (7106), enables
a high performance panel meter to be built with the addition
of only 10 passive components and a display.

•

•
•
•

rc,

y'

l"
r-r

fA

t:

~
-

_

!II

..

t:.

08C3
TEST
REF HI

F1
G'

REFLO

.,

COMMON

INLO
AlZ
BUFF

F2

IN HI

ICL7107CJL
ICL7107CDL
ICL7107CPL

O·C to +70·C
O·C to +70·C
O·C to +70·C

ICL7106EV/Kit
ICL71 07EVIKit

Evaluation kits contain IC, display, circuit
board, passive components and hardware.

40
40
40
44

pin
pin
pin
pin

ceramic DIP
plastic DIP
CERDIP
Surface Mount

40 pin CERDIP
40 pin ceramic DIP
40 pin plastic DIP

§

"'(TENSI

-

E3

BP

POL

~~

A84

~:.

D1
C1
B1

C'l'=

.PlGNO

II

G2
C3
A3
G3

y+

83
F2

(MINUS)

O·C
O·C
O·C
O·C

OSC 2
OSC 1

INT

y-

.-

('0001_
POL

to +70·C
to +70·C
to +70·C
to +70·C

PACKAGE

ICL7106CDL
ICL7106CPL
ICL7106CJL
ICL7106CM44

TEST
OSC 3

C-AEF

112
U

•

ORDERING INFORMATION
TEMPERATURE
PART NUMBER
RANGE

C'REF

C2

a
AI

•
•

O$C'
OSC2

C,
81

A'

o

Guaranteed Zero Reading for 0 Volts Input on
All Scales
True Polarity at Zero for Precise Null Detection
1pA Typical Input Current
True Differential Input and Reference
Direct Display Drive - No External Components
Required - LCD ICL7106
.,... LED ICL7107
Low Noise":'Lesll Than 15/lV pop
On-Chip Clock and Reference
Low Power Dissipation-Typically Less Than
10mW
No Additional Active Circuits Required
New Small Outline Surface Mount Package
Available
Evaluation Kit Available

•
•
•
•

F3
83

(71061 (7107)
CD006801
.............. N N N N N N , . ,

.:u..CDWQUCDCI.&..WQ

CD03241 I

Figure 1: Pin Configurat/()ns

6-37
Note: All typical values have been guaranteed by characterization and are not tested.

e........

301650-002

1C;1-7j~6jICL 7107
,

'"~

y .

'

.'.

• "

:

~

ABSOLUTE MAXllliluMRATINGS
Power' Dissipation (Note 2)'
Ceramic Package .............................. 1000mW
Plastic Package .................................... 800mW.
Operating Temperature ........................ O·C to + 70·C
Storage Temperature ........... : .......... -65·'C to + 150·C
Lead Temperature (Soldering, 10sec) ................. 300·C

Supply Voltage
ICL71 06, V+ to V- ................................ 15V
ICL71 07, V+ to GND ..................• , ......... +6V
ICL71 07, V- to GND .............................. ':'9V
Analog Inpilt Voltage (either iriput)(Note 1) ... V + td VReference Input Voltage (either input) ......... V + to VClock I n p u t ' ·
ICL7106 ................ : .................... TEST to V +
ICL7107 .........................;............. GND to V+

.

Stresses above those listed under Absol"le M~imum .Ratings may cause permanent damage to the device. These are stress ratings only, and func~onal
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1: Input voltages may exceed the suppiy voltages provided the input current is limited to ± 100"A.
Note 2: Dissipation rating assu~es device.' is mounted )Nith aU leads soldered to printed circuit board.

ELECTRICAL CHARACTERISTICS

(Note 3)
MIN

TYP

MAX

UNIT

-000.0

±OOO.O

+ 000.0

Digital Reading

VIN =VREF
VREF-l00mV

999

999/1000

1000

Digital Reading

Rollover Error (Difference in
reading for equal poSitive and
negatiVe inputs. near Full' Scale)

- VIN = + VIN",,2oo.0mV

-1

±.2

+1

Counts

Unearity (Max. deviation from
best straight line' lit)

Full scale = 200.0mV
or lull scale", 2.OO0V (Note 6)

-1

±.2

+1

Counts

Common Mode Rejection Ratio
(Note 4)

VCM = ±IV, Villi = OV
Full Scale = 200.0mV

50

Noise (Pk·Pk value not exceeded
95% Of time)

VIN =OV
Full Scale = 200.0mY

15

Leakage" Current Input

YIN = 0 (Note 6)

1

10

pA

Zero Reading Drift

YIN=O
O· < TA < 70·C (Note 6)

0.2

1

p.Y/·C

Scale Factor Temperature
Coefficient

YIN = 199:0mY
0·"<_ _ TODIGITIU. . .

~

-

GI.=."+--(!1}-.......---+--.....=--+-------'
I.'"

co_ -----~------~------+---------------~
L________________________ _
I

INPUT
LOW

_

80003411

Figure 4: Analog Section of 710617107

6-39
Note: All typical values have been guaranteed by characterization and are not tested.

S
ICL71061lCL7107
it:
.
d Auto-zero phase

::::.
. CD

~

....

~

error. However, by selecting the reference capacitor such
that it is large enough in comparison to the stray capacitance, this error can be. held to less than 0.5 count worst
case. (See Component Value Selection.)

During auto-zero three things happen. First, input high
and low are disconnected from the pins and internally
shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback
loop is closed around the system to charge the auto-zero
capacitor CAZ to compensate for offset voltages in the
buffer amplifier, integrator, and comparator. Since the
comparator is included in the loop, the AlZ accuracy is
limited only by the noise of the system. In any case, the
offset referred to the input is less than 10jJV.

Analog COMMON
This pin is included primarily to set the common mode
voltage for battery operation (7106) or for any system where
. the input Signals are floating with respect to the power
supply. The COMMON pin sets a voltage that is approximately 2.8 volts more negative than the positive supply.
This is selected to give a minimum end-of-Iife battery
voltage of about 6V. However, the analog COMMON has
some of the attributes of a reference voltage. When the
total supply voltage is large enough to cause the zener to
regulate (> 7V), the COMMON voltage will have a low
voltage coefficient (0.001 %IV), low output impedance
(~15n), and a temperature coefficient typically less than
80ppml"C.
The limitations of the on-Chip reference should also be
recognized, however. With the 7107, the internal heating
which results from the LED drivers can cause some
degradation in performance. Due to their higher thermal
resistance, plastiC parts are poorer in this respect than
ceramic. The combination of reference Temperature Coefficient (TC), internal chip· dissipation, and package thermal
resistance can increase noise near full scale from 25 IN to
80#lVP-P. Also the linearity in going from a high dissipation
count such as 1000 (20 segments on) to a low dissipation
count such as 1111 (8 segments on) can suffer by a count or
more. Devices with a positive TC reference may require
several counts to pull out of an overrange condition. This is
because overrange is a low dissipation mode, with the three
least significant digits blanked. Similarly, units with a negative TC may cycle between overrange and a nonoverrange
count as the die alternately heats and cools. All these
problems are of course eliminated if an external reference is
used.
The 7106, with its negligible dissipation, suffers from
none of these problems. In either case, an external
reference can easily be added, as shown in Figure 5.

Signal Integrate phase
During signal integrate, the auto-zero loop is opened, the
internal short is removed, and the internal input high and
low are connected to the external pins. The converter then
integrates the differential voltage between IN HI and IN LO
for a fixed time. This differential voltage can be within a wide
common roode range: up to one volt from either supply. If,
on the other hand, the input signal has no return with .
respect to the converter power supply, IN LO can be tied to
analog COMMON to establish the correct common-mode
voltage. At the end of this phase, the polarity of the
integrated signal is determined.

De-Integrate phase'
The final phase is de-integrate, or reference integrate.
Input low is internally connected to analog COMMON and
input high is connected across the previously charged
reference capacitor. Circuitry within the chip ensures that
the capacitor will be connected with the correct polarity to
cause the integrator output to return to zero. The time
required for the output to return to zero is proportional to the
input signal. Specifically the digital reading displayed is

(~).
VREF
Differential Input
1000

The input can accept differential voltages anywhere
within the common mode range of the input amplifier, or
specifically from 0.5 volts below the positive supply to 1.0
volt above the negative supply. In this range, the system
.has a CMRR of 86 dB typical. Mowever, care must be
exercised to assure the integrator Olltput does not saturate.
A worst case condition would be a large positive comrrionmode voltage with a near full-scale negative differential
input voltage. The negative input signal drives the integrator
positive when most of its swing has been used up by the
positive common mode voltage. For these critical applications the integrator output swing can be reduced to less
than the recommended 2V full scale Swing with little loss of
accuracy. The integrator output can swing to within 0.3 volts
of either supply without loss of linearity. See A032 for a
discussion of the effects of stray capacitance.

y+

y'

y'

6.akll

710617107

710617107

ICL lOll

1"
COMMON

Differential Reference

y-

(a,

The reference voltage can be generated anywhere within
the power supply voltage of the converter. The main source
of common mode error is a roll-over voltage caused by the
reference capaCitor losing or gaining charge to stray
capacity on its nodes. If there is a large common mode
voltage, the reference capacitor can gain charge (increase
voltage) when called up to de-integrate a positive signal but
lose charge (decrease lioltage) when called up to deintegrate a negative input signal. This difference in reference
for positive or negative input voltage will give a roll-over

(b'

08012601

Figure 5: Using an External Reference
Analog COMMON is also used as the input low return
during auto-zero and de-integrate. If IN LO is different from
analog COMMON, a common mode voltage exists in the
system and is taken careot by the excellent CMRR of the
converter. However, in some applications IN LO will be set
at a fixed known voltage (power supply common for
6-40

Note: All typical values have been guaranteed by characterization and are not tested.

.O~O[b

ICL7108/ICL 7107
DIGITAL SECTION

instance). In this application, analog COMMON should be
tied to the same pOint, thus removing the common mode
voltage from the converter. The same holds true for the
reference voltage. If reference can be conveniently tied to
analog COMMON, it should be since this removes the
common mode voltage from the reference system.
Within the IC, analog COMMON is tied to an N channel
FET that can sink approximately '30mA of current to hold
the voltage 2.8 volts below the positive supply (when a load
is trying to pull the common line positive). However, there is
only 10pA of source current, so COMMON may easily be
tied to a more negative voltage thus over-riding the internal
reference.

v'
1Mu

TOlCD
DECIMAL POINT

'------0 ~~c'";~ANE
O50127Of

Figure 6: Simple Inverter for Fixed Decimal
Point

v'

7106

BPl----_H

DECIMAL [

POINT
SELECT

TEST

a

S

The TEST pin serves two functions. On the 7106 it is
coupled to the internally generated digital supply through a
500n resistor. Thus it can be used as the negative supply
for externally generated segment drivers such as decimal
points or any other presentation the user may want to
include on the LCD display. Figures 8 and 9 show such an
application. No more than a 1mA load should be applied.

INTEASIL
111750

§

Figures 8 and 9 show the digital section for the 7106 and ......
7107, respectively. In the 7106, an internal digital ground is
generated from a 6 volt Zener diode and a large P channel :..
souroe follower. This supply is made stiff to absorb the ...
relative large capacitive currents when the back plane (BP)
voltage is switched. The BP frequency is the clock frequency divided by 800. For three readings/second this is a 60Hz
square wave with a nominal amplitude of 5 volts. The
segments are driven at the same frequency and amplitude
and are in phase with BP when OFF, but out of phase when
ON. In all cases negligible DC voltage exists across the
segments.
Figure 9 is the Digital Section of the 7107. It is identical to
the 7106 except that the regulated supply and back plane
drive have been eliminated and the segment drive has been
increased from 2 to 8 mA, typical for instrument size
common anode LED displays. Since the 1000 output (pin
19) must sink current from two LED segments, it has twice
the drive capability or 16mA.
In both devices, the polarity indication is "on" for
negative analog inputs. If IN LO and IN HI are reversed, this
indication can be reversed also, if desired.

TEST

7106

P

....

CD4030
__ ..JI

L -_ _ _ _ _---'--'-...J \OND
05012801

Figure 7: Exclusive 'OR' Gate for Decimal
Point Drive
The second function 'is a "lamp test". When TEST is
pulled high (to V + ) all segments will be turned on and the
display should read - 1888., The TEST pin will sink about
10mA under these conditions.
Caution: on the 7106, in the lamp test mode, the
segments have a constant DC voltage (no square-wave)
and may burn the LCD display if left in this mode for several
minutes.
6-41
Note: All typical values have been guaranteed by characterization and are not tested.

..S~ CL'7:tCl811CL
g
..a8
I

7107

DISPLA,( FONT

C:23'1SG189

_
~
...
.

........

.

.

.

........

---

-

-----------------------.-;!!!-----.-+'!----.---.!!-------------.____.____ .____ .__ 3
LCO04501

Figure 8: Digital Section 7106

Ol231.f56189

---f'r-~~;-,,:r------~~;_II~:t::J:::t:~--~~==~v37 t TeST
"0000

I

L----+~~~--_4~~~_~~-_-_~_-_-_-_-_-_-_-_-_-_--_-_~_-_-_-_-_-~-_~_~_-_-_~~~.~$I g~~~~~
osc,

OSC2

OSC3

LC004611

Figure 9: Digital Section 7107

6-42
Note: All typical values have been guaranteed by characterization and are not tested.

.O~DlL

ICL 7106/ICL7107
System Timing

O.lO~F,

respectively. Of course, if different oscillator frequencies are used, these values should be changed in
inverse proportion to maintain the same' output swing.

Figure 10 shows the clocking arrangement used in the
7106 and 7107. Three basic clocking arrangements can be
used:
1. An external oscillator connected to pin 40.
2. A crystal between pins 39 and 40.
3. An R-C oscillator using all three pins.
I

710617107

I

An additional requirement of the integrating capacitor is
that it must have a low dielectric absorption to prevent rollover errors. While other types of capacitors are adequate
for this application, polypropylene capaCitors give undetectable errors at reasonable cost.

I

I
I

The size of the auto-zero capacitor has some influence
on the noise of the system. For 200mV full scale where,
noise is very important, a 0.47~F capaCitor ,is recommended. On the 2 volt scale, a 0.047~F capacitor increases
the speed of recovery from overload and is adequate for
noise on this scale.

TO
:
COUNTER I

I

I

I
I
I
I

I
I

I

L_______ _

~________

~

o

Auto-Zero CapaCitor

I

I

I

e.
g
-e..
....

________ J

EXTERNAL
OSCILLATOR

Reference CapaCitor
A 0.1 ~F capacitor gives good results in most applications. However, where a large common mode voltage exists
(i.e. the REF LO pin is not, at analog COMMON) and a
200mV scale is used, a larger value is required to prevent
roll-over error. Generally 1.0~F will hold the roll-over error
to O.S count in this instance.

TE_T (710&) .
c,rGND(7107)
lCO04701

Figure 10: Clock Circuits
The OSCillator frequency is divided by four before it clocks
decade counters. It is then further divided to form the
three convert-cycle phases. These are signal' integrate
(1000 counts), reference de-integrate (0 to 2000 counts)
and auto-zero (1000 to 3000 counts). For signals less than
full scale, auto-zero gets the unused portion of reference
deintegrate. This makes a complete measure cycle of 4,000
counts (16,000 clock pulses) independent of input voltage.
For three readings/second, an oscillator frequency of
48kHz would be used.
'
To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. Oscillator
frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz,
40kHz, 33 "'13kHz, etc. should be selected, For SOHz rejection, Oscillator frequencies of 200kHz, 100kHz, 6693 kHz,
SOkHz, 40kHz, etc. would be suitable. Note that 40kHz (2.S
readings/second) will reject both SO and 60Hz (also 400
and 440Hz).
~he

Oscillator Components
For all ranges of frequency a 100kn resistor is, recommended and the capacitor is selecte,d from the equation
f

= 0.45.

For 48kHz clock (3 readings/second),C='100pF.

RC

Reference Voltage
The analog input required to generate full-scale output
(2000 counts) is: VIN = 2VREF. Thus, for the 200.0mV and
2.000 volt scale, Vref should equal 100.0 mV and 1.000 volt,
respectively. However, in many applications where the AID
is connected to a transducer, there will exist a scale factor
other than unity between the input voltage and the digital
reading. For instance, in a weighing system, the designer
might like to have a full scale reading when the voltage from
the transducer is 0.682V. Instead of dividing the input down _ ,
to 200.0mV, the designer should use the input voltage ~
directly and select VREF = 0.341V. Suitable values for
integrating resistor and capacitor would be 120kn and
0.22~F. This makes the system slightly quieter and also
avoids a divider network on the input. The 7107 with ±SV
supplies can accept input Signals up, to ±4V. Another
advantage of this system occurs when a digital reading of
zero is desired for VIN O. Temperature 'and weighing
systems with a variable tare are examples. This offset
reading can be conveniently generated by connecting the
voltage transducer between IN HI and COMMON and the
variable (or fixed) offset voltage between COMMON and IN
LO.

COMPONENT VALUE SELECTION
Integrating Resistor
Both the buffer amplifier and the integrator have a class A
output stage with 100pA of quiescent current. They can
supply 20pA of drive current with negligible non-linearity.
The integrating resistor should be large enough to remain in
this very linear region over the input voltage range, but
small enough that undue leakage requirements are not
placed on the PC board. For 2 volt full scale, 470kn is near
optimum and similarly a 47kn for a 200.0 mV scale.

*'

Integrating Capacitor
The integrating capacitor should be selected to give the
maximum voltage swing that ensures tolerance build-up will
not saturate the integrator swing' (approx. 0.3 volt from
either supply). In the 7106 or the 7107, when the analog
COMMON is used as a reference, a nominal ±2 volt full
scale integrator swing is fine. For the 7107 with ±S volt
supplies and analog COMMON tied to supply ground, a
±3.S to ±4 volt swing is nominal. For three readings/second
(48kHz clock) nominal values for CINT are 0.22~F and

7107 Power Supplies
The 7107 is designed to work from ±SV supplies.
However, if a negative supply is not available, it can be
generated from the clock output with 2 diodes, 2 capacitors,
and an inexpensive I.C. Figure 11 shows this application.
See ICL7660 data sheet for an alternative.

6-43
Note: All typical values have been guaranteed by characterization and are not tested.

.D~DIL

.S
.... ICL7106/ICL7107

...S:!....

-

7107

!

~

It:

~

To ..... '
40

OSC.
OSC.
OSC3

100ten
s.tVREF'" 'OO.OnlV

COMMON

/

'GOp'

TEST

REF HI
RlfLO
CREF
CREF

:~,

Do,,·'1

• .01,.F
47KI1

The input signal can be referenced to the center of
the common mode range of the converter.

2,

The, signal is less than

3.

An external reference is used.

±1.5

C,

J•

CDOO7001

volts.

7107

'-'

To pin 1

OlC1

40
-AAA'OOK!!l

...

''If'. v

ose3

TEST
AEF HI
AEF LO

','
To pin 1
40

OSC.

CRE.

,OO«n

••

OSC3
TEST
REFHI
REFLO

A'A

1MO

INHI
INLO
AlZ
aUFF
INT '

•.01,.,
47t(U

',,'[

v-

0....'

0,

10~1I

~i

.

O.47... F ••
47KU

0.22 F

,

IN

,
:
I

I

0,

...='"

v·

O'luv (ICLlO891
1Mn

v·

IN

10tell

'Yf

C,

I

Ai

[TO DISPLAY

G,
GND

I

,
:

I

______________ .1I

2'
c0007101

C,

Figure 14: 7107 with an external band-gap
reference (1.2V type). IN LO is tied to
CO.MMON, . thus establishing the correct
common mode voltage. If COMMON is not
shorted to GND, the input voltage may float
with respect to the power supply and
COMMON acts as a pre-regulator for the
reference. If COMMON is shorted to GND,
the Input is single ended (referred to supply
ground) and the pre-regulator is over-ridden.

} TO OISPLAY

'" 5--

G3

8P

•

/

• .01... F

INT

-

OAt,.F

'ten
~.

Do.',

INHt
INLO
AlZ
BUFF

Jo.

1ten

CO.MON

_n

, '

,

s.. VAEF =' l00.amv

COMMON

Set YREF= 1DD.OmV

:::;:0.1,.,

CRIF
CRIEI'

C AEF

/

4

••

OSC2

OSC.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ "'1 __

Figure 13: 7107 using the internal reference.
Values shown are for 200.0mV full scale, 3
readings per second. IN LO may be tied to
either COMMON for Inputs floating with
respect to supplies, or GND for single ended
inputs~ (See discussion under Analog
COMMON.)

The 7106 and 7107 may be used in a wide variety of
configurations. The circuits which follow show some of the
possibilities, and serve to illustrate the exceptional versatili·
ty of these AID converters.

'-'

,,

}TO DISPLAY

'"

0,

TYPICAL APPLICATIONS

7108

-----.-,~
.••,..,••~'V\.~+--O'N
INLO
O.47.,F
A'Z
471(1.
aUFf

OICl
OSC'
OSC'
TEST

... ~AEF

COMMON

1.1"

CO;~:~===--Jr----~~-1

71G117107

1001(11

REF HI

REF LO D----<,........'VI.IIr.......~I\,_-+_o -5V

G,
CJ
AJ
G,
GND

...,.. .

TEST

ole 3 O l - - - U - - - '
TEST

40

OSC'
OSC •
OSC'

I

TO DISPLAY

'"

v·

GJ
GND

TO DISPLAY

••

Figure 18: 7107 measuring ratiometric ;:i~';s
of Quad Load Cell. The resistor values within
the bridge are determined by the desired
sensitivity.

c0007301

Figure 16: 710617107: Recommended
component values for 2.000V full scale.

6-45
Note: All typical values have been guaranteed by characterization and are not tested.

..S... ICl..71061lCL7107
it
!.. .... .0
......
,t=s=0.,,'l

".D~UIL

=;:.

'OY

To pin 1

....., OIC'

100lm

DOC •

u

ScM/e tack»' adJus.
/

aSC3

TEST
REF HI
REFLO
CREF
C REF

COMMON
IN HI
INLO

AlZ
lUFF
INT
yG,

,

"

II

SHk:on NPH

"mU.,
~.----~
II

-,-

220KII

.

\zero.dIU.'

.D1~F.

-

0.47.. '
47KII

..,
C,

osc •

C,

OSC3

ii'

TEST
REF HI

f1

To

G'
E'

IOgIe

Vee

"".

12KU

-5- IY
-.J

O.U",F

OSC,

D'
A'

UPS 3704 or

•••

lUn
~

l00K'1

1107
V.

D.
B.

.

REFLO
CREF

CREf

COMMON

C.

INHI

A.

IMLO
AlZ

,~

BUFF

E2

.NT

r TO DISPLAY

Go
BP 2 t - - TO BACK PLANE
C0007601

Figure 19: 7106 used as a digital centigrade
thermometer. A silicon diode-connected
transistor has a' temperature coefficient of
about -2mVrC., Calibration is achieved by
placing the sensingtrans,istor in ice water
and adjusting the zeroingpolentiometer for
a 000.0 reading. The sensor should then be
placed'in bOiling water and 'the' scale-factor
potentiometer adjusted for 100.0 reading.

CD4023

or 74Cl0

33KO

C0007801

Figure 21: Circuit for developing Underrange
and Overrange signals from 7107 outputs.
The LM339 is required to ensure logic
compatibility with heavy display loading.

710617107 EVALUATION' KITS

7'ao

Y'

To

TEST
REFHI

f1

AU-LD

.

Yee

,

101
D2

C>

12

DOC.

CR.,
COIIIION
INHI
IHLO

IoJZ

BUf'

B.
EO
AM
POL

TolGgle
OND•

eRE'

f2

f3

..

OSC.

A2

a
o.

~

osc,

y.
0'
C,
11
A'

After purchasing a sample of the 7106 or the 7107, the
majority of users will want to build a simple voltmeter. The
parts can then be evaluated ag'ainst the data sheet specifications, and tried out in the intended application. However,
locating and purchasing even the small number of additional components required, then wiring a breadboard, can
often cause delays of days or sometimes weeks. To avoid
this problem and facilitate evaluation of' these unique
circuits, Intersil is offering a kit which' contains all the
necessary components to build a3V2-digit panel meter.
With the help of this kit, an engineer or technician can have
the system "up and running" in about half an hour.
Two kits are offered, the ICL7106EV/KIT and the
ICL71 07EVIKIT. Both contain the appropriate IC, a circuit
board, a display (LCD for 7106EV/KIT, LeDs for 7107EVI
KIT), passive components, and miscellaneous hardware.

,INT

...
Y-

'"..,
••

Y-

Q,

APPLICATION NOTES

21

A016 "Selecting' AID Converters", by, David Fullagar.
A017 "The Integrating AID Converter", By Lee Evans.
·A018 "Do's and Don'ts of Applying AID Converters", by
Peter Bradshaw and Skip Osgood.
A019 "4"'.t2-Digit Panel Meter Demonstratorl
Instrumentation Boards", by Michael Dufort.
A023 "Low Cost Digital Panel Meter Designs", by David
Fullagar and Michael Dufort.
A032 "Understanding the Auto-Zero and Common Mode
Performance of the ICL7106/7/9 Family", by Peter
Bradshaw.
A046 "Building a Battery-Operated Auto Ranging DVM
with the ICL71 06", by Larry Goff.
A052 "Tips for Using Single-Chip 3V2-Digit AID
Converters", by Dan Watson.

co....
or 74C10

C04077
CDO07701

Figure 20: Circuit for developing Underrange
and Overrange signals from 7106 outputs.

6-46
Note: All typical values have been guaranteed by characterization and are not tested.

.U~UI1.

ICL7106/ICL7107
7'"

i

..

To pin 1

OSCl

.......

n
r-

Scale laclor Mjust
(VRH '" l00mV lor AC 10 RMS)

l00KfI

O&C2
OSC)

.......

'....

TEST
REF HI
REFLO
CREF
C REF

....o
lKn

22t(1l

COMMON
IN HI
INLO

AI.

41KU

aUFF

INT

0.22 F

VG,

e,

)TODIS,....Y

'"

OJ

8"

P

.......

TO BACK PLANE

2'
Coo07901

Figure 22: AC to DC Converter with 7106. TEST is used as a common mode reference level to ensure
compatibility with most op-amps.

05012901

Figure 23: Display Buffering for increased drive current. Requires four DM7407 Hex Buffers. Each
buffer is capable of sinking 40 mAo

6-47
Note: All typical values have been guaranteed by characterization and are not tested.

's '12-Bit
I'CL710'9
IlP-Compatible
~
51!

AID Converter
GENERAL DESCRIPTION

FEATURES

The ICL7109 is a high performance, CMOS, low power
integrating AID converter designed to easily interface with
microprocessors.
The output data (12 bits, polarity and overrange) may be
directly accessed under control of two byte enable inpu.ts
and a chip select input for a simple parallel bus interface. A
UART handshake mode is provided to allow the ICL7109 to
work with industry-standard UARTs in providing serial data
transmission, ideal for remote data logging applications.
The RUN/HOLD input and STATUS output allow monitoring
and control of conversion timing.
The ICL7109 provides the user with the high accuracy,
low noise, low drift, versatility and, ~conomy of the dualslope integrating AID converter. Features like true differential input and reference, drift of less than 1pV rc, max:imum
,input bias current of 10pA, and typical power consumption
of 20mW make the ICL7109 an attractive per-channel
alternative to analog multiplexing for many data acquisition
applications.

•
•

•
•
•
•
•
•

12 Bit Binary (Plus Polarity and Overrange) Dual
Slope Integrating Analog-te-Dlgital Converter
Byte-Organized TTL-Compatible Three-State
Outputs and UART Handshake Mode for Simple
Parallel or Serial Interfacing to Microprocessor
Systems
'
RUN/HOLDlnput and STATUS Output Can Be
Used to Monitor and Control Conversion Timing
True Differential Input and Differential Reference
Low NOise - Typically 15j.1V pop
1pA Typical Input Current
Operates At Up to 30 Conversions Per Second
On-Chip OSCillator Operates With Inexpensive
3.58MHz TV Crystal Giving 7.5 Conversions Per
Second for 60Hz Rejection May Also Be Used
With An RC Network Oscillator for Other Clock
Frequencies

ORDERING INFORMATION
PART NUMBER
ICL7109MDL
ICL71091DL
ICL71091JL
ICL7109CPL

TEMP. RANGE

PACKAGE

-55·C to + 125°C
-25°C to +85°C
-25°C to +85°C
O°C to 70°C

f

f
L

OR~~!

Ceramic DIP
Ceramic DIP
CERDIP
Plastic DIP

TOPYIEW

~~I~G~N~D--~LI~---y~~~

GND-HIGH
ORDER
8YTE
OUTPUTS

40-Pin
40-Pin
40-Pin
40-Pin

OUT~~: I

L

2 STATUS
3 POL
4 DR
5 812
.811

~ :~o
988

:~

1087
::

:: :;
15 82

:~ ~~ST

REF IN-3tIO------~
REF CAP-38
DIFFERENTIAL
REF CAP + 37
REFERENCE
REF IN" 31
+
IN HI 35
INPUT HIGH

CO~:~~ :
ICLlI09
REF

~:~T LOW

INT 32n-~~~~11-~

AZ 311=~~~~~!
~~~ :~
REF IN n.

RUN/~:!
8UF ~ic o,~~ ~:

y+

+5Y
GND
BYTE .. I. LIDi
OSC OUT 2311}------.
CONTROL
HHA
osc IN 22
INPUTS ~'''1.:20
__
CE;;.I;;;LO;,;l;;;D;....__.....:M::0~D~E..:2.:.Jll-'"

24kJl

l "

'R'NT " 20kJl FOR O.ZY REF
- _Jl FOR Z.OY REF
CD032001

(See Figure 2 for typical connection to a UART or Microcomputer)

Figure 1: Pin Configuration and Test Circuit

6-48
Note: -All typical values have been guaranteed by characterization and are not tested.

301655-Q02

.D~DIl.

ICL7109

o
cg

ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage (GND to V+) ............... +6.2V
Negative Supply Voltage (GND to V-) ................. -9V
Analog Input Voltage (Lo or Hi) (Note 1) ...... V + to VReference Input Voltage (Lo or Hi) (Note 1) .. V+ to VDigital Input Voltage
V + + O.3V
(Pins 2-27) (Note 2) ................................ GND -O.3V

Power Dissipation (Note 3)
Ceramic Package ......................... 1W @ + 85°C
Plastic Package ..................... 500mW @ + 70°C
Operating Temperature
Ceramic Package (MOL) ........ -55°C to + 125°C
Ceramic Package (IDL) ............ -25°C to + 85°C
Plastic Package {CPL) ................ O°C to + 70°C
Storage Temperature ...................... -65°C to + 150°C
Lead Temperature (Soldering, 10sec) .............. + 300·C

'COMMENT: Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the devices. This is a stress rating only and
functional operation of the devices at these or any other conditions above those indicated in the operational sections of the· specifications is not implifil(j.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (v+ = +5V, v- = -5V, GND
indicated.) Test circuit' as shown on first page of this data sheet.

= OV,

TA

= 25·C,

unless otherwise

ANALOG SECTION
MIN

TYP

MAX

UNIT

Zero Input Reading

VIN=O.OV
Full Scale = 409.6mV

-OOOOa

±OOOOS

+OOOOa

Octal
Reading

Ratiometric Reading

VIN = VREF
VAEF = 204.6mV

3777a

3777a
4000a

4000a

Octal
Reading

Non-Linearity (Max deviation
from best straight line fit)

Full Scale = 409.6mV to 2.046V
Over full operating temperature
range. (Note 4), (Note 6)

-1

±.2

+1

Counts

Roll-over Error (difference
in reading for equal pos. and
neg. inputs near full scale)

Full Scale = 409.6mV to 2.048V
(Note 5), (Note 6)

-1

±.2

+1

Counts

CMRR

Common Mode Rejection Ratio

VCM ±1V VIN - OV
Full Scale = 409.6mV

VCMR

Input Common Mode Range

Input Hi, Input Lo, Common (Note 4)

en

Noise (p-p value not
exceeded 95% of time)

VIN=OV
Full Scale = 409.6mV

15

Leakage current at Input

VIN - 0 All devices at 25·C
ICL7109CPL O·C S TA S + 70·C (Note 4)
ICL71091DL -25·C S TA S + 85·C (Note 4)
ICL7109MDL - 55·C S TA S + 125·C

1
20
100
2

10
100
250
5

pA
pA
pA
nA

0.2

1

IlV'·C

1

5

ppml"C

SYMBOL

IILK

PARAMETER

TEST CONDITIONS

50
V- +1.5

IlVIV
V+ -1.0

V
IlV

Zero Reading Drift

VIN = OV Rl = on (Note 4)

Scale Factor Temperature
Coefficient

VIN = 408.9mV = > 7770a
reading
Ext. Ref. 0 ppm'·C (Note 4)

1+

Supply Current V + to
GND

VIN = 0, Crystal Osc
3.56MHz test circuit

700

1500

IlA

ISUpp

Supply Current V + to V

Pins 2-21, 25, 26, 27, 29; open

700

1500

IlA

VAEF

Ref Out Voltage

Referred to V +, 25kn
between V + and REF OUT

_2.6

-3.2

V

Ref Out Temp. Coefficient

25kn between V + and REF OUT

-2.4

80

ppml"C

DIGITAL SECTION
SYMBOL

PARAMETER

TEST CONDITIONS

VOH

Output High Voltage

lOUT = 1001lA
Pins 2-16, 18, 19, 20

VOL

OU\j:lut Low Voltage

lOUT = 1.6mA

Output Leakage Current

Pins 3-16 high impedance

Control I/O Pullup
Current

Pins 18, 19,20 VOUT=V+-3V
MODE input at GND

Control I/O Loading

HBEN Pin 19 LBEN Pin 18

Input High Voltage

Pins 18-21, 26, 27
referred to GND

Input Low Voltage

Pins 16-21, 26, 27
referred to GND

VIH
VIL

......P

6-49
Note: All typical values have been guaranteed by characterization and, are not tested.

MIN
3.5

TYP

MAX

4.3

UNIT
V

0.2

0.4

V

±:ot

±1

IlA

5

IlA
50

pF
V

2.5
1

V

§ IC"7109

s!....

ELECTRICAL CHARACTERISTICS (CONT.)
SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

5

pA

Pins 17, 24 VOUT = V+ -3V

25

pA

Pin 21 VOUT = GND +3V

5

pA

High

VOUT= 2.5V

1

mA

Input Pull-up Current

Pins 26, 27 VOUT = V+ ';'3V

InpUt Pull-up Current
Input Pull-down Current

"

OOH

Octillator Output

OOL

Current

Low

VOUT=2.5V

1.5

mA

BOOH

Buffered Oscillator

High

VOUT= 2.5V

2

mA

BOOL

Output Current

Low

VOUT= 2.5V

5

mA

tw

MODE Input Pulse Width

NOTES:

(Note 4)

1. Input voltages may exceed the supply voltages provided the input current is limited to ± 100pA
2. Due to the SCR structure inherent in the process used to fabricate these devices, connecting any digital inputs or outputs to
voltages greater than V + or less than GND may cause destructive device latchup. For this reason it is recommended that no inputs
from sources other than the same power supply be applied to the ICL71 09, before its power supply is established, and that in
multiple supply systems the supply to the ICL7109 be activated first.
3. This limit refers to that of the package and will not be obtained during normal operation.
4. This parameter is not production tested, but is guaranteed by design.
S. Roll-over error for TA = -SsoC to + 125°C is ±3 counts maximum.
6. A full scale voltage of 2.048V is used because a full scale voltage of 4.096V exceeds the devices Common Mode Voltage Range.

TABLE 1: - Pin Assignment and
"

PIN

DESCRIPTION

' SYMBOL
GND

Digital Ground, OV. Ground return for all
digital 'logic.

2

STATUS

Output High during integrate and deintegrate until data is latched.
OUtpUt Low when analog section is in
Auto-Zero configuration.

3

POL

Polarity - HI for Positive input.

4

OR

5

B12

Bit 12

6
7

B11

Bit 11

B10

Bit '10

All

8

B9

Bit 9

three

20

9

B8

Bn 8

B7

Bn 7

11

B6

Bit 6

data

B5

Bn S

bita

13

B4

Bit 4

14

B3

Bit 3

1S

B2

Bit 2

16

B1

Bit 1

17

TEST

InpUt High - Normal Operation.
Input Low - Forces all bit outputs high.
Note: This input is used for test purposes
only. Tie high if not used.

18

mEN

Low g~e62Bble-With Mode (Pin 21) low,
and
L
(Pin 20) low, taking this pin
low activates low order byte oUtpUts B1B8.

DESCRIPTION
ghi~

gnable Load-With Mode (Pin 21) low.
E L AD serves as a master output enable.
When high, B1-B12, POL, OR outputs are
disabled.

21

MODE

InpubLow-,Direct output mode where W
LOA (Pin 20), Frn8il (Pin 19) and r:BEN
(Pin 18) 'act as inputs directly controlling byte
outputs.
Input Pulsed High - Causes immediate entry
into handshake mode and output of data as
in Figure 10.
l!!e!!LHigh - Enables CE/LOAD (Pin 20),
HBEN (Pin 19), and LBEN (Pin 18) as
outputs, handshake mode will be entered and
data output as in Figures 8 and 9 at
conversion completion.

22

OSC IN

Oscillator Input

23

OSC OUT

Oscillator Output

24

OSC SEL

Oscillator Select -Input high configures
OSC IN, OSC OUT, BUF OSC OUT as RC
oscillator - clock will be same phase and
duty cycle as BUF OSC OUT.
-Input low configures OSC IN, OSC OUT
for crystal oscillator - clock frequency will
be 1/S8 of frequency at BUF OSC OUT.

25

BUF OSC
OUT

Buffered Oscillator Output

26

RUN/HOLD

Input High - Conversions continuously
performed every 8192 clock pulses.
Input Low - Conversion in progress
completed, converter will stop in Auto-Zero 7
counts before integrate.

27

SEND

Input- Used in handshake niode to indicate
ability Of an external device to accept data.
Connect to + SV if not used.

28

V-

Analog Negative Supply - Nominally -SV
with respect to GND (Pin 1). '

29

REF OUT

Reference Voltage Output - Nominally 2.8V
down from V' (Pin, 40).

30

BUFFER

Buffer Amplifier Output

output

12

(Least Significant Bn)

- With Mode (Pin 21) high, this pin serves
as a low byte flag oUtput used in handshake
mode. See Figures 8, 9, 10.
HBEN

CE'7COAi5

state
HI = true

Description

SYMBOL

- With Mode (Pin 21) high, this pin serves
as a load strobe used in handshake mode.
See Figures 8, 9, 10.

Overrange - HI if Overranged.
(Most Significant Bit)

10

F~nction

PIN

1

19

ns

50

High&relnable-With Mode (Pin 21) low,
and
/L AD (Pin 20) low, taking this pin
low activates high order byte outputs B9- "
B12, POL, OR.
:..;. With Mode (Pin 21) high, this pin serves
as a high byte flag output used in handshake
mode. See Figures 8, 9, 10.

6-50
Note: All typical values have been guaranteed by characterization and are not tested.

n
r-

ICL7109
PIN

SYMBOL

DESCRIPTION

PIN

SYMBOL

.......

DESCRIPTION

31

AUTO-ZERO

Auto-Zero Node - Inside foil of CAl

36

REF IN +

Differential Reference Input Positive

32

INTEGRATOR

Integrator Output - Outside foil of CINT

37

REF CAP +

Reference Capacitor Positive

33

COMMON

Analog Common - System is Auto-Zeroed
to COMMON

38

REF CAP

Reference Capacitor Negative

39

REF IN
V+

34

INPUT LO

Differential Input Low Side

35

INPUT HI

Differential Input High Side

40

i

Differential Reference Input Negative

Positive Supply Voltage - Nominally + 5V
with respect to GND (Pin 1).

Note: All digital levels are positive true.

v· 40
aND
+IV

aND
+IV

'OND
2S BUF OlC OUT
aSTATUS

1000 pF

REF IN - :It

:::g::~:

,

.SV

.",a,POL,OR

TIRL 23
TIR! 22

MIIal

AZ31

"CDR

211~

RINT 2OkO O.ZV REF
200koav REF

v-a

RullJii&a 21
OIC SlL24
OSCOUT 2 3 t - - -....
OSCIN 22

27 lEND

GNO
PULLUP' fIIlSISTOIIII TO

INPUT

_30

al MOD!

'011 LOWEST POW" COiIlUMPTtOH.
'f8IIJ1·'.....HPUT.IHOULD MAW tOOle(1

GND
.15

REF OUT 2t

17 T!ST

DRRI'I~~~~~~~~~~~~~
DR I.

•

C:: :t---""INT F~

w

-GND

IUR~E

1= ~~ :

T~i't------7---------~~i t,'~
TRE24

+IV

RIPIN..

,. iiiiii

,

t---------o:--

ICL710t
CMOS AID CONVERTER

.,v

COO08121

Figure 2A: Typical Connection Diagram UART Interface- To transmit latest result, send any word to
UART

"IV
ONG
.IV

40 y.
I GNO
17 TEST

ICL710t

21 RUNliR!DI
2 STATUS
II LIlli
tt AIIIiI
12-1'

GIIID

:10 _

DIIO-Oa7

iilho

REF IN :It
·RIFC,., - .
RIFCM·37
REF IN'.
IN HI 35
IN LOlM
COM 33
INT32
AZ31
IUF 30
REF OUT 2t

v-al

SEND 27
IUF OIC OUT 2..
OSC SEL24
OSC OUT 23
OSC IN 22

~--GND

EXTERNAl.
REFERENCE

I.F

n
: INPUT

~~5.F
-tv

R'~T

201111 O.av REF.
200k1l 2V REF.

.IV

aNO

MODIal
COO0821 I

Figure 28: Typical Connection Diagram Parallel Interface With 8048 Microcomputer
Auto-Zero Phase

DETAILED DESCRIPTION
Analog Section

During auto-zero three things happen. First, input high
and low are disconnected from their pins and internally
shorted to analog COMMON_ Second, the reference capacitor is charged to the reference voltage. Third, a feedback
loop .is closed around the system to charge the auto-zero
capacitor CAZ to compensate for offset voltages in the
buffer amplifier, integrator, and comparator. Since the
comparator is included in the loop, the AZ accuracy is
limited only by the noise of the system. In any case, the
offset referred to the input is less than lO/-lV.

Figure 3 shows the equivalent circuit of the Analog
Section of the ICL7109_ When the RUN/HOLD input is left
open or connected to V +, the circuit will perform conversions at a rate determined by the clock frequency (8192
clock periods per cycle). Each measurement cycle is
divided into three phases as shown in Figure 4. They are (1)
Auto-Zero (AZ), (2) Signal Integrate (I NT) and (3) Deintegrate (DE): .

6-51
Note: All typical values have been guaranteed by characterization and are not tested.

I

.~.
....

leL7109

~

CREF
Ct~T

INTEGRATOR
i2-----------

RIFCAP'I-

r--I

I
I

TO ZERO CROll
DETECTOR
DIGITAL IECTlOfII

I

,

COMMON ~--+-""T""-_..J

I.2V

33

1
I
I

AZ- _
CONTROL
INT- LOGIC
DEINT (+)- DIGITAL IECTIOIiI
DEINT(-)-

INT

IN~LO~~~--~~-----------------------------J

1M

I
1

L. ___....:. __________________

21

v+

REF OUT

lCO04901

Figure 3: Analog Section

I

POLARITY
ZERO CROSSING
DE~TECTED
OCCURS
,
ZERO CROSSING
.
I
_
DETECTED
I

I

I

INTEGRATOI1
OUTPUT

1
L,'

INTERNAL CLOCK

h.r ~ J11U1.h... Jl11IlI1r 1.11I1lu"tr

INTERNAL LATCH

1
I,

II

II

h

II

I

I

I

I

I
I

I

I

I_

I-;-AZ PHASE I--I-INT PHASE II

I

STATUS OUTPUT I

I

I-I

DEINT PHASE III----i--AZ-

2048
COUNTS,
MIN.

I

.1.
I

FIXED
2048
COUNTS

I

.1.

I

NUMBER OF COUNTS TO ZERO CROSSING /
PROPORTIONAL TO VIN

1

I

."-

I
I

4098 COUNTS--l
MAX

I

I' "'-AFTER ZERO CROSSING,
ANALOG SECTION WILL '
BE IN AUTOZERO
CONFIGURATION
WF011101

Figure 4: Conversion Timing (RUN/HOLD Pin High)
'(during auto-zero) reference capacitor. Circuitry within the
chip ensures that the capacitor will be connected with the
correct polarity to cause the integrator output to return to
zero crossing (established in Auto Zero) with a fixed slope.
Thus the time for the output to, return to zero (represented
by the num~er of clock periods counted) is proporti,onal to
the input signal.

Signal Integrate Phase
During signal integrate the auto-zero loop is opened,the
internal short is removed and the internal high and low
inputs' are connected to the external pins. The converter
then integrates the differential voltage betw,een INHI and IN
LO for a fixed time of 2048 clock periods. Note that this
differential voltage must be within the common mode range
of the inputs. At the end of this phase, the polarity of the
integrated signal is determined.

Differential Input
The input can accept differential voltages' anywhere
within the common mode range of the input amplifier; or
specifically from 1.0 volts below the positive supply to 1.5
volts above the negative supply. In this range the system
has a CMRR of 86dS typical. However, since the integrator

De-Integrate Phase
The final phase is de-integrate, or, reference integrate.
Input low is internally connected to analog COMMON and
input high is connected across the previously charged
6-52

Note: All typical values have been guaranteed by characterization and are not tested.

ICL7109
also swings with the common mode voltage, care must be
exercised to assure the integrator output does not saturate.
A worst case condition would be a large positive common
mode voltage with a near full-scale negative differential
input voltage. The negative input signal drives the integrator
positive when most of its swing has been used up by the
positive common mode voltage. For these critical applications the integrator swing can be reduced to less than the
recommended 4V full scale with some loss of accuracy. The
integrator output can swing within 0.3 volts of either supply
without loss of linearity.
The ICL7109 has, however, been optimized for operation
with analog common near digital ground. With power
supplies of + 5V and -5V, this allows a 4V full scale
integrator swing positive or negative thus maximizing the
performance of the analog section.

enough that undue leakage requirements are not placed on
the PC board. For 4.096 volt full scale, 200kn is near
optimum and similarly a 20kn for a 409.6mV scale. For
other values of full scale voltage, RINT should be chosen by
the relation
full scale voltage
RINT=

20~

Integrating Capacitor
The integrating capacitor CINT should be selected to give
the maximum. integrator output voltage swing without saturating the integrator (approximately 0.3 volt from either
supply). For the ICL7109 with ±5 volt supplies and analog
common connected to GND, a ±3.5 to ±4 volt integrator
output swing is nominal. For 7-1/2 conversions per second
(61.72kHz clock frequency) as provided by the crystal
oscillator, nominal values for CINT and CAZ are 0.15jAF and
0.33/lF, respectively. If different clock frequencies are used,
these values should be changed to maintain the integrator
output voltage.swing. In general, the value of CINT is given
by

Differential Reference
The reference voltage can be generated anywhElre within
the power supply voltage of the converter. The main source
of common mode error is a roll-over voltage caused by the
reference capacitor losing or gaining charge to stray
capacity on its nodes. If there is a large common mode
voltage, the reference capacitor can gain charge (increase
voltage) when called up to deintegrate a positive Signal but
lose charge (decrease voltage) when called up to deintegrate a negative input signal. This difference in reference
for (+) or (-) input voltage will give a roll-over error.
However, by selecting the reference capacitor large enough
in comparison to the stray capacitance, this error can be
held to less than 0.5 count for the worst case condition (see
Component Values Selection below). .
The roll-over error from these sources is minimized by
having the reference common mode voltage near or at
analog COMMON.

An additional requirement of the integrating capacitor is
that it have low dielectric absorption to prevent roll-over
errors. While other types of capacitors.are adequate for this
application, polypropylene capacitors give undetectable
errors at reasonable cost. up to 85'C. For the military
temperature ~ange, Teflon® capacitors are recommended.
While their dielectric absorption characteristics vary somewhat from unit to unit, selected devices should give less
than 0.5 count of error due to dielectric absorption.

Component Value Selection

Auto-Zero Capacitor.

CINT=

(2048 x clock period){20jJA)
.
integrator output voltage swing

The size of the auto-zero. capacitor has some influence
on the noise of the system: the smaller the capacitor the
lower the over.all system noise. However, CAZ cannot be
increased without limits since it, in parallel with the integrating capacitor forms an R-C time constant that determines
the speed of recovery from overloads and more important
the error that exists at the end of an auto-zero cycle. For
409.6mV full scale where noise is very important and the
integrating resistor small, a value of CAZ twice CINT is
optimum. Similarly for 4.096V full scale where recovery is
more important than noise, a value of CAZ equal to half of
CINT is recommended.

For optimum performance of the analog section, care
must be taken in the selection of values for the integrator
capacitor and resistor; auto-zero capacitor, reference voltage, and conversion rate. These values must be chosen to
suit the particular application.
The most important consideration is that the integrator
output swing (for full-scale input) be as large as possible.
For example, with ±5V supplies and COMMON connected
to GND, the nominal integrator output swing at full scale is
±4V. Since the integrator output can go to 0.3V from either
supply without Significantly affecting linearity, a 4V integrator output swing allows 0.7V for variations in output swing
due to component value and oscillator tolerances. With ±5V
supplies and a common mode range of ± 1V required, the
component values should be selected to provide ±3V
integrator output swing. Noise and rollover errors will be
slightly worse than in the ±4V case. For larger common
mode voltage ranges, the integrator output swing must be
reduced further. This will increase both noise and rollover
errors. To improve the performance, supplies of ±6V may
be used.

For optimal rejection of stray pickup, the outer foil of CAZ
should be connected to the R-C summing junction and the
inner foil to pin 31. Similarly the outer foil of CINT should be
connected to pin 32 and the inner foil to. the R-C summing
junction .. Teflon®, or equivalent, capacitors are recommended above 85'C for their low leakage characteristics.

Reference Capacitor
A 1/lF capacitor gives good results in most applications.
However, where a large reference common mode voltage
exists (i.e. the reference low is not at analog common) and
a 409.6mV scale is used, a larger value is required to
prevent roll-over error. Generally 10jAF will hold the roll-over
error to 0.5 count in this instance. Again, Teflon®, or
equivalent capacitors should be used for temperatures
above 85'C for their low leakage characteristics.

Integrating Resistor
Both the buffer amplifier and the integrator have a class A
output stage with 100~ of quiescent current. They supply
20~ of drive current with negligible non-linearity. The
integrating resistor should be large enough to remain in this
very linear region over the input voltage range, but small
6-53

Note: All typical values have been guaranteed by characterization and ·are not tested.

a
•

...g

''P'

d...

ICL7109
,

Reference Voltage,
,The analog input required to generate a full ,scale output
of 4096, Counts is, VIN = 2VREF. Thus for a normalized
scale,a reference of 2.048V should be used, for a 4.096\1
full scale, and 204.8mV should be used for a OA096V full
scale. However; in many applications where the AID is
sensing the output of a transducer, tl:lere will exist a ,scale
factor other than unity be/ween the absolute output voltage
to be measured and a desired digital output. For instance, in
a weighing system, the designer, might like to have a full
scale reading when the voltage from the transducer is
0.68,2V. Instead of dividing the input down to 409.6mV, the
input voltage !lhould be measured directly and a reference
voltage, of 0.341 V shoul(:l be used. Suitable values for
integrating resistor and capaCitor are 34kn and 0.15IlF.
This avoids a divider on the input. Another advantage of this
system occurs when,a zero re8clingis desired for non-zero
input. Temperature and weight measurements with an
offset or tare are examples. The offset may be introduced
by connecting the voltage output of the transducer between
common and analog high, and the offset voltage between
common and analog low, observing polarities carefully.
However, in processor-based systems using the ICL7109, it
may be more efficient to perform this type of scaling or tare
subtraction digitally using software.
Reference Sources
The stabilitY of the reference voltage is a major factor in
the overall absolute accuracy of the converter. Th~ resolution'of the ICL71 09 at 12 bits is one part in 4096,or
244ppm. Thus if the reference has a temperature c'Oefficientof 80ppmfOC (onboard reference) a temperature
difference of 3°C' will introduce a one-blCabsolute error.
For this reaso~, \t is recommended, that an external highquality reference be I,Jsed where t!'le ambient temperature is
not controlled or where high-accuracy absolute measurements are being made.
'
The ICL71 09 provides 'a REFerence OUTput (pin 29)
which may be used with If resistive divider to generate a
suitable reference voltage. This output will sink up to about
20mA without significant variation in output voltage, and is
provided with a pulluP bias' device Which sources about
101lA. The output voltage is nominally 2;8V below V + , and
has a temperature coefficient o( ±80ppml"C typo When
using the onboard reference, REF OUT (Pin 29) should be
connected to REF- (pin 39), and REF + should be connected to the wiper of a precision potentiometer between
REF' OUT and V +. The circuit for a 204.8mV reference is
shown in the test circuit. For a 2.048mV reference, the fixed
resistor should be removed, and a 25kn precision potentiometer between REF OUT and V + should I;>e used.
Note that if pins 29 and 39 are tied together and pins 39
and 40, 'aCCidentally shorted ,(e.g., during testing), .the
reference supply will sink enough current to destroy the
device. This can be avoided by placing' a 1kn resistor in
series with pin 39.

Throughout this description, logic levels will be referred to
as "Iow"or "high", The actual logic levels an~ defined in
the ,Electrical Charac\eristics Table. For minimum power
consumption, aU. inputs should swing from GND (low) to V +
(high). Inputs driven from TIL gates should have 3-Skn
pullup, resistors added for maximum noise immunity.

MODE Input
The MODE )nput' is used to control the output mode of
the converter. When the MODE pin is low or left open (this
input is provided with a pulldown resistor to ensure a low
level when the pin is left open), the converter is in its
"Direct" output mode, where the output data is directly
accessible under the control of the chip and byte enable
inputs. When the MODE input is pulsed high, the converter
enters the UART handshake mode and outputs the data in,
two bytes, then returns to "direat"mode. When the MODE
input is left high, the converter will output data in the
handshake mode at the end of every conversion cycle. (See
section entitled "Handshake Mode" for further details).

STAJ"US Output
During a conversion cycle, the STATUS Qutput goes high
at the beginning of Signal Ihtegrate (Phase II), and goes low
one-half clock period after new data from the conversion
has been ,stored in the output latches. See Figure 4 for
details of this timing. This signal may be used ·as a "data
valid" flag (data never changes while STATUS is low) to
drive interrupts, or for monitoring the status of the converter.

RUN/HOLD I'nput
When the RUN/HOLD input is high, or left open, the
circuit will continuously perform conversion cycles, updating
the output latches after zero crossing during the Deintegrate (Phase III) portion of the conversiOn cycle (See Figure
4). In this mode of operation, the conversion cycle will be
performed in 8192 clock periods, regardless of the resulting
value.
. If RUI';.)/ROiJ) goes low at any time during Deintegrate
(Phase III) after the zero crossing has occurred, the circuit
~ill immediately terminate Deintegrate and jump to AutoZero. This feature can be used to eliminate the time spent in
Deintegrate after the zero-crossing. If RUN/HOLD stays or
goes'low, the converter will ensure minimum Auto-Zero
time, and then wait in Auto-Zero until the RUN/HOLD input
goes high. The converter will begin the Integrate (Phase II)
portion of the next conversion (and the STATUS output will
,go high) seven clock periods after 'the high level is detected
at RUN/!:i0LD. ,See Figure 6 for details"

DETAILED· DESCRIPTION
Digital Selection
The digital section includes the clock oscillator, and
scaling circuit, a 12-bit binary counter with output latches
and TIL-compatible three-state output drivers, polarity,
over~range and control logic,and UART han9shake logic,
as shown, in Figure' 5.
e..54
Note: All typical values have been guaranteed by characterization and are no\ tested.

·ICL7109

t

t

HIGH ORDER
IIYTE OUTPUTS
B B B a
POL OR 12 11 10 9

TEST

;-;I

LOW ORDER
. BYTE OUTPUTS
B .·B B a B B
8 7 & 5 4 3 2

B
1

17
18
19
20

AD

I
I
I

I
I
I
I
I
I

I

COMPOUT
TO AZ
{
ANALOG
INT
SECTION
DEINT(+)
DEINT(-)
-~.,...----r-l

I
I
I

- -- ---.e-- JI
21

STATUS

27

IIUt!l OSC OSC OSC aUF MODE
HOLD IN OUT SEL OSC·
OUT

It

SEND

GND

80003501

. Figure 5: Digital Section

DEINT TERMINATED
AT ZERO CROSSING

INTEGRATOR

_ -_ _
~

OUTPUT

~ETECTION

~

~

----f

!NTERNAL CLOCK
INTERNAL LATCH

I-AUTDZERD--l
PHASE I
I STATIC IN
I MIN 1790 COUNTS I HOLD STATE
I MAX 2041 COUNTS I

.... 'NT
I PHASE"

j.

,

'I'

Lr 'lIU1.I1... J1ItnnI1.11... ..I1.tLh.Itn......ru--

h

':

I

J ___

r---7 COUNTS----I

~

;

~;;;;~==~=======~~~=;;~~:
t..----------_L-r"l- ~ L ________r-~---

STATUS OUTPUT
RUNIHOLDINPUT:

WF011201

Figure 6: Run/Hold Operation
If the RUN/HOLD input goes low and stays low during
Auto-Zero (Phase I), the converter will simply stop at the
end of Auto-Zero al)d wait for RUN/HOLD to. go high. As
above, Integrate (Phase II) begins seven clock periods after
the high level is detected.

Using the RUN/HOLD input in this manner allows an
easy "convert on demand" interface to be used; The
converter may be held at idle in auto-zero with RUN/HOLD
low. When RUN/HOLD goes high the conversion is started,
and when the STATUS output goes low the new data is
valid (or transferred to the UART - see Handshake Mode).
RUN/HOLD may now be taken low which terminates
deintegrate and ensures a minimum Auto-Zero time before
the next conversion.

Direct Mode
When the MODE pin is left at a low level, the data outputs
(bits 1 through 8 low order byte, bits 9 through 12, polarity
and over-range high order byte) are accessible under
control of the byte and chip enable terminals a$ inputs.
These three inputs are all active low, and are provided with
pullup resistors to ensure an inactive high level when left
open. When the chip enable input is low, taking a byte
enable input low will allow the outputs of that byte to
become active (three-stated on). This allows a variety of
parallel data accessing techniques to be used, as shown in
the section entitled "Interfacing." The timing requirements
for these outputs are shown in Figure 7 and Table 2.

Alternately, RUNiHOLD can be used to minimize conversion time by ensuring that it goes low during Deintegrate,
after zero crossing, and goes high after the hold point is
reached. The required activity on the RUN/HOLD input can
be provided by connecting it to the Buffered Oscillator
Output. In this mode the conversion time is dependent on
the input value measured. Also refer to Intersil Application
Bulletin A032 for a discussion of the effects this will have on
Auto-Zero performance.
6-55

Note: All typical values have been guaranteed by characterization· and are not tested..

ICL7109
Table 2 - Direct Mode Timing
Requirements
(See Note 4 of Electrical Characteristics)
SYMBOL

DESCRIPTION

MIN

TYP

350

220

MAX

UNIT

tSEA

Byte Enable Width

tOAS

Data Access Time
from Byte Enable

tOHS

Data Hold Time
from Byte Enable

tcEA

Chip Enable Width

tOAC

Data Access Time
from Chip Enable

260

400

ns

tOHC

Data Hold Time
from Chip Enable

240

400

ns

emmi~
AS INPUT

400

ns

210

350

ns

150

300

ns

260

ns

r-

'------'

RftR
AS INPUT

LIER

AS INPUT

tOAC

LOW BYTE
OATA - - - - - - - - - - - - - - ... 1--

DATA
VALID

- - - - = HIGH IMPEDANCE
WF011301

Figure 7: Direct Mode Output Timing
It should be noted that these control inputs are asynchronous with respect to the converter clock - the data may be
accessed at any time. Thus it is possible to access the
latches while they are being updated, which could lead to
erroneous data. Synchronizing the' access of the latches
with the conversion cycle by monitoring the STATUS output
will prevent this. Data is never updated while STATUS is
low.

Handshake Mode
The handshake output mode is provided as an alternative
means of interfacing the ICL7109 to digital systems, where
the AID converter becomes active in contrOlling the flow of
data instead of passively responding to chip and byte
enable inputs. This mode is specifically designed to allow a
direct interface between the ICL7109 and industry-standard
UARTs (such as the Intersil IM6402/3) with no external
logic required. When triggered into the handshake mode,
the ICL7.109 provides all the control and flag signals
necessary to sequentially transfer two bytes of data into the
UART and Initiate their transmission in serial form. This
greatly eases th.e task and reduces the cost of designing
remote data acquisition stations using serial data transmission.
Entry into the handshake mode is controlled by the
MbDE pin. When the MODE terminal is held high, the

ICL7109 will enter the handshake mode after new data has
been stored in the output latches at the end of a conversion
(See Figures 8 and 9). The MODE terminal may also be
used to trigger entry into the handshake mode on demand.
.At any time during the conversion cycle, the low to high
transition of a short pulse at the MODE input will cause
immediate entry into the handshake mode. If this pulse
occurs while new data is being stored, the entry into
handshake mode is delayed until the data is stable. While
the converter is in the handshake mode, the MODE input is
ignored, and although conversions will still be performed,
data updating will be inhibited (See Figure 10) until the
converter completes the output cycle and clears the
handshake mode.
When the converter enters the handshake mode, or
when the MODE. input is high, the chip and byte enable
terminals become TIL-compatible outputs which provide
the control signals for the output cycle (See Figures 8, 9,
and 10).
In handshake mode, the SEND input is used by the
converter as an indication of the ability of. the receiving
device (such 'as a UART) to accept data.
Figure 8 shows the sequence of the output cycle with
SEND held high. The handshake mode (Internal MODE
high) is entered after the data latch pulse, and since MODE
remains high the CE/LOAD, LBEN and HBEN terminals are
active as outputs. The high level at the SEND input is
sensed on the same high to low internal clock edge that
terminates the data latch pulse. On the next low to high
internal clock edge the CE/LOAD and the HBEN outputs
assume a low level, and the high-order byte (bits 9 through
12, POL, and OR) outputs are enabled. The CE/LoAD
output remains low for one full internal clock period only,
the data outputs remain active for 1-1/2 internal clock
periods, and the high byte enable remains low for two clock
periods. Thus the CE/LOAD output low level or low to high
edge may be used as a synchronizing Signal to ensure valid
data, and the byte enable as an output may be used as a
byte identification flag. With SEND remaining high the
converter completes the output cycle using CE/LOAD and
LBEN while the low order byte outputs (bits 1 through 8) are
activated. The handshake mode is terminated when both
bytes are sent.
Figure 9 shows an output sequence where the SEND
input is used to delay portions of the sequence, or
handshake to ensure correct data transfer. This timing
diagram shows the relationships that occur using an industry-standard IM6402/3 CMOS UART to interface to serial
data channels. In this interface, the SEND input to the
ICL7109 is driven by the TBRE (Transmitter Buffer Register
Empty) output of the UART, and the CE/LOAD terminal of
the ICL7109 drives the TBRL (Transmitter Buffer Register
Load) input to the UART. The data outputs are paralleled
into the eight Transmitter Buffer Register inputs.

Note: All typical values have been guaranteed by characterization and are not tested.

ICL7109

I

"I"

INTEGRATOR

OUTPUT

INTERNAL

CLOCK

ZERO CROSSING
ZERO CROSSING

OCCURS

L_DeTECTED

.--.r-IL....-J"--I - - ~ f--- ~ r-- r--tr-

INTERNAl.
LATCH
STATUS

OUTPUT
MODO
INPUT

IIOOE HleaH ACTIVATES

INTERNAL UART

MODE NOIIM

91ImD. ~ [JIll

. .ND

SEND

INPUT

III

HIGHS""
DATA

LOWBvn

DATA

TERMINATES

---- \------------

1\\

\\
-------- ------

UARTMODE

a:~, ' /

/

/
',!ODE LOW. NOT
IN HANDSHAKE IfOD£

~

DI6A8LES OUTPUTS ~.

7-.1.±_.1._

HftIii. i:IIR

---------r--::~:=
1--- ------------------- --------- --DATA VALID

)---

DATA-YALID

_ ; DON'T CAM

- - - - = THREt:-STAT~ HIGH IMPEDANCE

_.1._.1._

= THftEE-STATE WITH PUUUP
WF011401

Figure 8: Handshake With Send Held Positive

ZERO CRosatNG

OCCURS

zao CROUtNG

wq~~ ----~~--~~~~'
INTERNAL'
CLOCK
INTERNAl.

LATCH _ _ _ _ _.1

STATUS

OUTPUT
..ODE
INPUT

--------t1--+-----... ,..--t-+----- - - t - - t - - - ' - - l ' i. ._ . . . . . . .

._---r-

..

..........
=-____..;..-11--+------... ,..--1-1-+------ --4--4TE
/

INTE....L UART

MODE ::00:::...

SEND INPUT
(UMT
TBRE)

UART MODE

a.IIIIIIIIIIIIIIIIIIIIII~"'-r==..;..?

-------+--1.
~ -------+--1.

CiiLl!iD OUTPUT
(UARTTIRL)

'--.----

HIGH8YTE _ _ _ _ _ _ _ _ _ _

DATA

LOWlnE
DATA - - - - - - - - - -

•

'" DON'T CARE

- --------t J<--- -

,I'-__-=D~AT:.;;A;.:V.;;AL~ID

- - - - = THREE4TATE HIGH NIIIPEDANCE
WF011501

Figure 9: Handshake - Typical UART Interface Timing

6-57
Note: All typical values have been guaranteed by characterization and are not tested.

..g ICL7109

.D~DIl

~

.

S:!
ZERO CROSS_ DETECTEO

~
~
--+--+-----.....
OUT~~

--+-;;;.=;.:..=;=-'--.... --+--+---

=

POSITM! TIIANSITlON.CAUMS

:~~="~" III••IIIIIIIIII!

.,TEANAI. UAIIT .

.. "

11001; NORM

I=~··
ASc:.,~o,:::

/v
.

_..1. __ .t. __.v-- --':""-l
~

HtOH:~:

--------I--oof ,. ___ ...:.

LiEN _.1_...1 __V - LOW:~!

__________ ....

III =

OONT CARl

--+--+----.,.........--+--1

':~O

_ _r

~-..;...--

...___1-.._ _ _ _.....-+-1.
~-----

.---

___

,... __

~--__t

=THRIE",TATE HIGH IMPEDANCE

-

'-----....
DATAVAUD

i_ '= THltEE-sTATE WITH PULLUP
WFQ11601

Figure 10: Handshake Triggered By Mode
Assuming the UART Transmitter Buffer Register is empty, the SEND input will be high when the handshake mode is
entered after new data is stored. The CE/LOAD and HBEN
terminals will go low after SEND is sensed,. and the high
order byte outputs become active. When CE/LOAD goes
high at the end of one clock period, the high order byte data
is clocked into the UART Transmitter Buffer Register. The
UART TBRE output will now go low, which halts the output
cycle with the HBEN output low, and the. high order byte
outputs active. When tM.l)ART has transferred the data to
the Transmitter R~gister and cle~re,d the.. Transmitter Buffer
Register, the TBRE returns high. On the next ICL7109
internal clock high to low edge, the high order byte outputs
are disabled, and orie-half internal clock later, the. HBEN
output returns high. At the same time, the CE/LOAD and
LBEN outputs go low, and the low order. byte outputs
become active. Similarly, when the CE/LOAD returns high
at the end of one clock periqd, the low order data is clocked
into the UART Transmitter Buffer Register, and TBRE again
goes low. When TBRE returns to a high it will be sensed on
the next ICL7109 internal clock high to low edge, disabling
the data outputs. One-half internal clock later, the handshake mode will be cleared, and the CE/LOAD, HBEN, and
LBEN terminals return high and stay active (as long as
MODE stays high).

to high edge on the MODE input, handshake output
sequences may be performed on demand. Figure 9 shows a
handshake output sequence triggered by such an edge. In
addition, the SEND input is shown as being low when the
converter enters handshake mode. In this case, the whole
output sequence is controlled by the SEND input, and the
sequence for the first (high order) byte is similar to the
sequence for the second byte. This diagram also shows the
output sequence taking longer than a conversion cycle.
Note that the converter still makes conversions, with the
STATUS output and RUN/HOLD input functioning normally.
The only difference is that new data will not be latched
when in hand,shake mode, and is therefore lost.

Oscillator
The ICL7109 is provided with a versatile three terminal
oscillator, to generate the internal clock. The oscillator may
be overdriven, or may be operated with an RC network or
crystal. The OSCILLATOR SELECT input changes the
internal configuration of the oscillator to optimize it for RC or
crystal operation.
When the OSCILLATOR SELECT input is high or left
open (the input is provided with a pullup resistor), the
oscillator is configured for RC operation, and the internal
clock will be of the same freqUency and phase as the signal
at the BUFFERED OSCILLATOR OUTPUT. The resistor
and capacitor should be connected as in Figure 11. The
circuit will oscillate at a frequency given by f ,=f OAS/RC. A
100kn resistor is recommended for useful ranges of

With the MODE input remaining high as in these examples, the converter will output the results of every conversion excepUhose completed during a handshake operation.
By triggering the converter into handshake mode with a low
6-58

Note: All typical values have been guaranteed by characterization' and are not tested.

ICL7109
frequency. For optimum 60Hz line rejection, the capacitor
value should be chosen such that 2048 clock periods is
close to an integral multiple of the 60Hz period (but should
not be less than 50pF).

BUFFERED OSCILLATOR OUTPUT of the ICL7109 may be
used to drive the OSCILLATOR INPUT of the UART, saving
the need for a second crystal. However, the BUFFERED
OSCILLATOR OUTPUT does not have a great deal of drive
capability, and when driving more than one slave device,
external buffering should be used.

Test Input
24

T~
SEL

22

23

25

OSC
IN

OSC
OUT

BUFFEREO
OSC
OUT

When the TEST input is taken to a level halfway between
V + and GND, the counter output latches are enabled,
allowing the counter contents to be examined anytime.
When the TEST input is connected to GND, the counter
outputs are all forced into the high state, and the internal
clock is disabled. When the input returns to the 112 (V +
-GND) voltage (or to v+) and one clock is applied, all the
counter outputs will be clocked to the low state. This allows
. easy testing of the counter and its outputs.

----

R
C

v+ OR OPEN

I('I~,.·

4'5/RC
lCO05101

Figure 11: RC Oscillator

INTERFACING
Direct Mode

When the OSCILLATOR SELECT input is Iowa feedback
device and output and input capacitors are added to 'the
oscillator. In this configuration, as shown iii Figure 11, the
oscillator will operate with most crystals in the 1 to 5MHz
range with no external components. Taking the OSCILLATOR SELECT input. low also inserts a fixed +58 divider
circuit between the BUFFERED OSCILLATOR OUTPUT
and the internal clock. Using an inexpensive 3.58MHz TV
crystal, this division ratio provides an integration time given
by:
T

= (2048

clock periods) x [ __
58
__]
3.58MHz

Figure 13 shows some of the combinations of chip
enable and byte enable control signals which may be used
when interfaCing the ICL7109 to parallel data lines. The CEI
LOAD input may be tied low, allowing either byte to be
controlled by its own enable as in Figure 13A. Figure 13B
shows a configuration where the two byte enables are
connected together. In this configuration, the CE/LOAD
serves as a chip enable, and the HBEN and LBEN may be
connected to GND or serve as a second chip enable. The
14 data outputs will all be enabled simultaneously. Fi~
13C shows the HBEN and LBEN as flag inputs, and CEI
LOAD as a master enable, which could be the READ strobe
available from most microprocessors.

= 33.18ms

This time is very close to two 60Hz periods or 33.33ms. The
error is less than one percent, which will give better than
40dB 60Hz rejection. The converter will operate reliably .at
conversion rates of up to 30 per second, which corresponds
to a clock frequency of 245.8kHz.
v+-.....- - - _ -

24

22

23

25

IN

OSC
OUT

BUFFEREO
OSC
OUT

----~osc osc
SEL
GND

0

----

CRYSTAL
LGO05001

Figure 12: Crystal Oscillator
If at any time the oscillator is to be overdriven, the
overdriving signal should be applied at the OSCILLATOR
INPUT, and the OSCILLATOR OUTPUT should be left
open. The internal clock will be of the same frequency, duty
cycle, and phase as the input Signal when OSCILLATOR
SELECT is left open. When OSCILLATOR SELECT is at
GND, the clock will be a factor of 58 below the input
frequency.
When using the ICL7109 with the IM6403 UART, it is
possible to use one 3.58MHz crystal for both devices. The
6-59
Note: All typical values have been guaranteed by characterization and are not tested.

!... JCL7109

...

:g

A:

GND.-......, . - - -.....

B.

CHIP SELECT 1

GND

c.
89·812
POL. OR

81·812
POL. OR

ANALOG·
IN

ICL7109

ICL7109

ANALOG
IN
RUN/HOLD CONVERT

CONTROL

ANALOG
IN

ICL7109

RUN/HOlii 1--:--.,.,.-.
CONVERT

RUN/HOLD J - - CONVERT

CHIP

S~~~~~ -~--.....

AF022501

8YTE FLAGS·
AF022601

AF022701

Figure 13: Direct Mode Chip and Byte' Enable Combinations

CONVERTER

CONVERTER

CONVERTER

SELECT

SELECT

SELECT

MODE

81·88

•

ANALOG

ANALOG

~

~

RUN/HOLD

ANALOG
. IN
RUN/HOi'D

RUN/HOLD

-5V

8YTE SELECT FLAGS

AF022801

Figure 14: Tri-stating Several 7109's to a Small .Bus
Figure 14 shows an approach to interfacing several
ICL7109s to a bus, ganging the HBEN and LBEN si8nals to
several converters together, and using the CE/LOA inputs
(perhaps decoded from an address) to select the desired
converter.

will lead to scrambled data. This will occur very rarely, in the
proportion of setup-skew times to conversion time. One way
to overcome this is to read the STATUS output as well, and
if it is high, read the data again after a delay of more than
1/2 converter clock period. If STATUS is no,!\, low, the
second reading is correct, and if it is still high, the first
reading is correct. Alternatively, this timing problem is
completely avoided by using a read~after-update sequence,
as shown in Figure 16. Here the high to low transition of the
STATUS output drives an interrupt to the microprocessor
causing it to access the data latches. This application also
shows the RUN/HOLD input being used to initiate conversions unde~ software .control.

Some practical circuits utilizing the parallel three·state
output capabilities of the ICL7109 are shown in Figures 15
through 20. Figure 15 shows a straightforward application to
the Intel 8048/80/85 microprocessors via an 8255PPI,
where the ICL7109 data outputs are active at all times. The
I/O ports of an 8155 may be used in the same way. This
interface can be used in a read·anytime mode, although a
read performed while the data latches are being updated

IHIO

Note: All typical values have been guaranteed by characterization and are not tested.

.O~O[l

ICL7109
~

ADDIIESS BUS

~

CONTROLaus

1I

(
GNO

I

I

MODE

CEiLDAD

1'1'

RO

• ,

POL. DR
RUN/HOLD

ViR

STATUS

ONO

HiEii

LiEN

1

I

I I

~J

~J

AO-Al

Pa,-PBo

I

~

I I

I

tJ

~J

CI

t---+sv

al-81

IN

07-110

PAs-PAc

ICL7101

9

I I

DATABUS

1J fJ

....12

i

~

I I

_.IOIS.

1255
(MDOEO)

_._ETC

I--WTOT - Pes

l0003701

Figure 15: Full-time Parallel Interface to 8048/80/85 Microprocessors

?

ADO_BUS

t

CONTRDLBUS

IJ

;
GND

I

I

MODE

CEILOAD

....,2

• ,

POL, DR

.

9

It

I I

1J f} 1J

1J

RD WR

07-00

All-Al

Pa,_

I

al-81

ONO

LiEN

1

I

~J

, . ~t
II

STBA

-.-

_ _ ETC

8255

PC.

101cll

iiiiii

t~

CI

PCo

RUNtHOLii

STATUS

"S

I I

DATA BUS

PAs-PAc

ICL7101

IN

-~

fr

I I

PCo

INTRA

INTR

+IV
SEE TEXT

LD003801

Figure 16: Full-time Parallel Interface to 8048/80/85 Microprocessors With Interrupt
of this are shown in Figures 18 and 19. It is necessary to
carefully consider the system timing in this type of interface,
to be sure that requirements for setup and hold times, and
minimum pulse widths are met. Note also the drive limitations on long buses. Generally this type of interface is only
favored if the memory peripheral address density is low .50
that simple address decoding can be used. Interrupt handling can also require many additional components, and
using an interface device will usually simplify the system in
this case.

A similar interface to Motorola MC6800 or MaS Technology MCS650X systems is shown in Figure 17. The high to
low transition of the STATUS output generates an interrupt
via the Control Register B CB1 line. Note that CB2controis
the RUN/HOLD pin through Control Register B, allowing
software-controlled initiation of conversions in this system
as well.
The three-state output capability of the ICL7109 allows
direct interfacing to most microprocessor busses. Examples

6-61
Note: All typical values have been guaranteed by characterization and are not tested.

e...

IC1.7109
GNO

119-812~';""'--'"

PA0-6
POI., ORt-_6_ - . /

CRBI--11R-G1!

ICL7108
B1-86

8

MceaoX
OR
MCSISOX

PBO-7
MC6820

ANALOG
IN

STATUS~---~CB1

RUN/iiOLi)

OND-......-

CB2

......_..;,l
ADDRESS
BUS

DATA
BUS

CONTROL
BUS
LDOO3901

. Figure 17: Full-time Parallel Interface to MC680X or MCS650X Microprocessors

119-812
POL. DR
ICL7109

8009. 8080. 8085

Bl-B8

8

ANALOG
IN

C£[OiD~----~
·MEMR or lOR
'or 80801I22I Systam

OND

+5V
LOO0410i

Figure 18: Direct Interface -ICL7109 to 8080/8085

~2

Note: All typical values have been guaranteed by characterization and are not tested.

ICL7109

89-812
POL,OR

81-118

MCI80X

8

OR
MCS850X

ANALOG

IN

~~------------;

~~------------~

AOORESS
BUS

DATA
8US

CONTROL
8US
LD004201

Figure 19: Direct ICL7109 - MC680X Bus Interface

Handshake Mode
The handshake mode allows ready interface with a wide

~ariety of external devices. For instance, external latches
may be clocked by the rising edge of CE/LOAD, and the
byte enables may be used as byte identification flags .or as
load enables.
Figure 20 shows a handshake interface to Intel microprocessors again using an 8255PPI. The handshake operation
with the 8255 is controlled by inverting its Input Buffer Full
(ISF) flag to drive the SEND input to the ICL71 09, and using
the CE/LOAD to drive the 8255 strobe. The internal control
register of the PPI should be set in MODE 1 for the port
used. If the 7109 is in handshake mode and the 8255 IBF
flag is low, the next word will be strobed into the port. The
stroQe will cause ISF to go high (SEND goes low), which will
keep. the enabled byte outputs active. The PPI will generate
an interrupt which when executed will result in the data
being read. When the byte is read, the IBF will be reset low,
which causes the ICL7109 to sequence into the next byte.
This figure shows the MODE input to the ICL7109 connected to a control line on the PPI. If this output is left high, or
tied high separately, the data from every conversion (provided the data access takes less time than a conversion) will
be sequenced in two bytes into the system.
If this output is made to go from low to high, the output
sequence can be obtained on demand, and the interrupt
may be used to reset the MODE bit. Note that the RUNI
HOLD input to the ICL7109 may also be driven by a bit of
the 8255 so that conversions may be obtained on command

under software control. Note that one port of the 8255 is not
used, and can service another peripheral device. The same
arrangement can also be used with the 8155.
Figure 21 shows a similar arrangement with the MC6800
or MCS650X. microproce!\sors, except that both MODE and
RUN/HOLD are tied high to save port·outputs.
The handshake mode is particularly convenient for directly interfacing to industry standard UARTs (such as the
IntersillM6402/6403 or Western Digital TR1602) providing
a minimum component count means of serially transmitting
converted data. A typical UART connection is shown in
Figure 2A. In this circuit, any word received by the UART
causes the UART DR (Data Ready) output to go high. This
drives the MODE input to the ICL7109 high, triggering the
ICL7109 into handshake' mode. The high order byte is
output to the UART first, and when the UART has transferred the data to the Transmitter Register, TBRE (SEND)
goes high and the second byte is output. When TBRE
(SEND) goes high again, LBEN will go high, driving the
UART ORR (Data Ready Reset) which will signal the end of
the transfer of data from the ICL7109 to the UART.
Figure 22 shows· an extension of the one converterone UART scheme to severallCL7109s with one UART. In
this circuit, the word received by the UART (available at the
RBR outputs when DR is high) is used to select which
converter will handshake with the UART. With no external
components, this scheme will allow up to eight ICL7109s to
interface with one UART. Using a few more components to
decode the received word will allow up to 256 converters to
be accessed on one serial line.

Note: All typical values have been guaranteed by characterization and are not tested.

6

........ ICL7109

·~

S!

t

ADDRESS BUS

t

CONTROL.US

'I I

~

1r

II
I I

I I

I I

~J

t} I I

DATA BUS

.

....,2
POL,OR

\

li

ICL7108

8

~J

RD WR

81-118

--

~J

07-00

AD-AI

(

t

a

PA1-PAo

RUNtHOU)

Pc.

MODE

pc,

8008,8010,
80115, 8048 ETC

1255
(MODEl)

mr. PC.
SEND
~ PC$

CEILOAD
IN

tj

t

pc,

INTR
LD004301

Figure 20: Handshake Interface -ICL7109 to 8048, 80/85

·,5V-_---,

CRA l--loo411
ICL7109

MC6800
OR
MCS650X

ANALOG
IN

Ciii:O'Ao~-­
SEND

CA2

ADDRESS
8US

DATA
SUS

CONTROl
BUS
LOO04401

Figure 21: Handshake Interface -ICL7109 to MC6800, MCS650X

Note: All typical values have been guaranteed by characterization and are not tested.

ICL7109

SERIAl. OUTPUT

o

1---

_CMOSUART
SERIAL INPUT 1 - - - -

MOOE

CfJ

U!AD
89·812
POL.·OR

~:-:::

ICL1109

89-B12

8

POL. OR

ICL7109

Bl·B8

Bl·B8

ANALOG

8

ANALOG
IN

IN
RUN/HOLD

-5V

8

ICL7109

81-88

8

ANALOG
IN
RUN/HOLD

+5V

lOOO45Q1

Figure 22: Multiplexing Converters with Mode Input
The applications of the ICL7109 are not limited to those
shown here. The purpose of these examples is to provide a
starting pOint for users to develop useful systems, and to
show ii10me of the variety of interfaces and uses of the
ICL7109. Many of the ideas.suggested here may be used in
combination; in particular the uses ot the STATUS, RUN/
HOLD, and MODE signals may be mixed.

APPLICATION NOTES
A016 "Selecting AID Converters," by David Fullagar
A017 "The Integrating AID Converters," by Lee Evans
A018 "Do's and Don'ts of Applying AID Converters," by
Peter Bradshaw and Skip Osgood
A030 "The ICL7104 -A Binary Output AID Converter for
Microprocessors," by Peter Bradshaw
A032 "Understanding the Auto-Zero and Common Mode
Performance of the ICL7106 Family," by Peter
Bradshaw
ROOS "Interlacing Data Converters & Microprocessors,"
by Peter Bradshaw et ai, Electronics, Dec. 9, 1976.

Note: All typical values have been guaranteed by characterization and are not tested.

!ICL711S.

d.14-Bit High-Speed

,CMOS MP-Compatible
AID Converter
GENERAL DESCRIPTION

FEATURES

The ICL7115 is the first monolithic 14-bit resolution, fast
successive approximation AID converter. It uses thin film
resistors and CMOS circuitry combined with an on~chip
PROM calibration .table to achieve 13-bit linearity without
laser trimming. Special design techniques used in the DAC
and comparator result in high speed operation, while the
fully static Silicon-gate CMOS circuitry keeps the power
dissipation very low.
Microprocessor bus interfacing is made easy by the use
of standard WRite and ReaD cycle timing and control
Signals, combined with Chip Select and Address pins. The
digital output pins are byte-organized and three-state gated
for bus interface to 8 and 16-bit systems.
The ICL7115 provides separate Analog and Digital
grounds. Analog ground, voltage refer~nce and input voltage pins are separated into force and sense lines for
increased system accuracy. Operating with ±5V supplie's,
the ICL7115 accepts OV to + 5V input with a -5V reference
or OV to -5V input with a +5V reference.

•
•
•

DGNO

40 39 38 37 36
35
34

(MSI) 0"

33

0"

32

IUS

5
6

4

3

2

1

31

PART
NUMBER

RESOLUTION
WITH NO
MISSING CODES

TEMP.
RANGE

PACKAGE

ICL7115JCDL
ICL7115KCDL

12 B~s
13 Bits

O'C to +70'C
O'C to +70'C

40 Pin Ceramic
40 Pin Ceramic

ICL7115JIDL
ICL7115KIDL

12 Bits, '
13 Bits

- 25'C to 85'C 40 Pin Ceramic
- 25'C to + 85'C 40 Pin Ceramic

ICL7115JMDL
ICL7115KMDL
ICL7115JMLL
ICL7115KMLL

12 Bits
13 B~s
12 Bits'
13 Bits

- 55'C
- 55'C
- 55'C
- 55'C

to
to
to
to

+ 125'C 40 Pin Ceramic
+ 125'C 40 Pin Ceramic
+ 125'C 40 Pin LCC
+ 125'C 40 Pin LCC

Wli
Sl!
USC2
0SC1

10
11
12

29

TESf

0,

13

28

PRUG

0,

14

Z1

15

26
17 18 19 20 21 22 23 24 25

16

ORDERING INFORMATION

v-

0"

30

•
•
•
•

CAl

0"
0.

ICL7115

•
•
•

=

14-Blt Resolution (LSB 3051lV)
No Missing Codes
Mlcroprocess(lr Compatible Byte-Organized
Buffered Outputs
Fast Conversion (40l-ls)
Auto-Zeroed Comparator for Low Offset Voltage
Low Linearity and Gain Tempco
(1.5ppmI"C, 5ppmrC)
,
Low Power Consumption (60mW)
No Gain or Offset Adjustmen,t Necessary
Provides 3% Useable Overrange
FORCE/SENSE and Sepa~ate Digital and Analog
Ground Pins for Increased System Accuracy

V'

OVR

tSdtSdQ"!mmm
t!r

(Outline DWG LL)

(Outline DWG DL)
Figure 1: Pin Configuration

6-66
Note: All typical values have been guaranteed by characterization and are nol'tested.

301659-002

ICL7115
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage V + to DGND ............. -O.3V to + 6.SV
Supply yoltage V- to DGND .............. +O.3V to -6.SV
VREFs. VREFf. VINs. VINf to DGND ....... +2SV to -2SV
AGND s• AGNDf to DGND ...................... + 1V to -1V
Current in FORCE and SENSE Lines ................. 2SmA
Digital 1/0 Pin Voltages ............... -O.3V to V+ +O.3V
PROG to DGND Voltage ................. V- to V+ +O.3V

Operating Temperature Range
ICL711SXCXX ........................... O'C to +70'C
ICL711SXIXX ................ ; ........ -2S·C to +8S'C
ICL7t1SXMXX ...................... -SS·C to +12S'C
Storage Temperature Range ............ -6S'C to + 1S0'C
Power Dissipation ......................................... SOOmW
derate above 70'C @ 1OOmW I"C
Lead Temperature (Soldering. 10sec) ................. 300·C

NOTE 1: All voltages with respect to DGND, unless otherwise noted.
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of. the spec~ications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

""EF,

...-J\I\"""--o

"'NI

SC

OSC1

OSC2

""EFf

AGNDf
AGND,

17·BITSAR
CONTROL LOGIC

v-~

' . 4 1 - - - - - - - - 0 WR
~-------_oEOC

17

,.----.-"1....-,> OVR
0,3 (MSB)

.............:-7-r....-... Do (LSB)

liD

eli All

Figure 2: ICL7115 Functional Block Diagram

6-67
Note: All typical values have been guaranteed by characterization and are not tested.

BUS

......... ICl.7t15

IIO~O[l

'10

-

u ELECTRICAL CHARACTERISTICS

. DC ELECTRICAL CHARACTERISTICS V+ = +S.OV. V- = -S.OV. VREFs = -S.OV. TA = +2SoC. fClK = SOOkHz unless
otherwise n o t e d '
SYMBOL

. ..

PARAMETER
Resolution

,

14

~=VIL

12

ILE

Integral Unearity Error

Note 1

TC(ILEl

Temperature Coefficient of ILE

TA -

RES(NMC)

Min Resolution' with No Missing
Codes

TC(FSE)

Temperature Coefficient of FSE
Zero Error

Notes 1.2

Temperature Coefficient of ZE

TA - Operating Range

PSRR

Power Supply Rejection Ratio

VIN

Analog Input Range
(VIN•• VREFsl

RIN

Input Resistance (VIN•• VREFsl

13
12
±0.1
±0.08

± 1t2

TA - 25°C

o to

1

ppml"C

±1

-300

TA = 25°C
TA=Operating Range

2

Supply Voltage Range

Functional Operation Only

VIL

Low State Input Voltage

Operating Temperature Range

VIH

High State Input Voltage

Operating Temperature Range

ILIH

Logic Input Current

o V+

Low State .Oujput Voltage

lOUT- 1.6mA
Operating Temperature Range

VOH

High State Oujput Voltage

lOUT = -200pA
Operating Temperature Range

±4.5

±6.0
0.8

2.4

2.8

rnA
V
V
pA
V
V

lOX

Three-State Oujput Current

0< VOUT> V +

1

Logic Input Capscitance

(Note 4)

15

GoUT

Logic Output Capacitance

Three-State (Note 4)

15

6-68

10
0.4

CIN

Note: All typical values have been guaranteed by characterization and are not tested.

kn

V
1

Full·scale range (FSR) is 5V (reference adiusted).
Assume all leads soldered or welded to printed clrcuH board.
Assume all leads soldered or welded to· printed circuit board.

LSB

ppml"C

4
6

VOL

LSB

V

9

TA - Operating Range

VSUPPLY

2.
3.

ppml"C

+5

4

ISUPPLY

%FSR

5
±1

±2

TA - Operating Range

Note 3

%FSR
ppm/oC

Bits

11

2

Supply Current I +. 1-

NOTES: 1.

1.5

12

TA - Operating Range

TeeZE)

Tc(RIN)

±0.018

J
K

ZE

UNIT
Bits

1

J
K
J
K

MAX

±0.012

Operating Range

fA - Operating Range (Note 2)
FSE

TYP

J
K

TA= 25°C

Full Scale calibration Error
(Adjustable to Zero)

MIN'

TEST CONDITIONS
~~VIH

pA
pF

.D~DIL

ICL7115

..P...
en

VALID

A.

~I---_

00-013

-~l+------

-_18_d

EOC

~

= DON'T CARE
Figure 3: Read Cycle Timing with BUS = V,L

~~J~}-

EOC

~

= DON'T CARE

Figure 4: Write Cycle Timing

AC ELECTRICAL CHARACTERISTICS v+ = +S.ov, v- = -S.ov, TA= +2S0C, fclk=SOOkHz unles
otherwise noted. Data derived from extensive characterization testing. Parameters are not 100% production tested.
PARAMETER

SYMBOL

I

TEST CONDITIONS

MIN

TYP

MAX

UNIT

READ CYCLE TIMING

led
lad

Prop. Delay ~ to Data

tro

Prop. Delay ~ to Data

Inc

Prop. Delay Data to Three State

100

ted

Prop. Delay EDC High to Data

200

Prop. Delay

Ao

to Data

~ Low.

Ao

Valid

200

~ Low, ~ Low

200

Cl; Low. Ao Valid

200

ns

WRI'rE CYCLE TIMING

twr

WIt low Time

twe

Prop. Dalay

lao

EOC High Time

Free-Run Mode

COnversion Time

S"C: = V,H
S"C: = V,L

!conv

WI'i

ns

100
low to EDC low

Wait Mode

1

2

0.5

1.5
20
18

6-69
Note: All typical values have been guaranteed by characterization and are not tested,

111clk

.......

...

.1ft

ICL7115"

gTABLE 1: PIN DESCRIPTIONS
PIN

NAME

1
2

VREFf
AGNDf

3

CS

FORCE input 'for analog ground

~ (active low)

5

Ao

Byte select (low = Do-D7,
high = D8-DI3, OVR)

6

BUS

7

DGND

8

D13

Bit 13 (most significant)

9

D12

Bit 12

10

Dl1

Bit 11

Bus select (low = outputs enabled by Ao,
· high - all outputs enabled together)

Bit 9

Output

13

D8

Bit 8

Data

14

D7

Bit 7

15

D6

Bit 6

16

Ds

Bit 5

17

D4

Bit 4

18

D3

Bit 3

19

D2

Bit 2

20

Dl
Do

23

B16

24
25

B17
EOC

26

OVR

x
x

0

0

0

Low Byte is Enabled

0

x

0

1

0

High Byte is Enabled

0

x

0

x

1

Low and High Bytes Enabled Together

x

x

1

x

x Disables Outputs (High-Impedance)

INPUT VOLTAGE

Bit 10

BIS

1

x Initiates a Conversion
x Disables all Chip Commands

TABLE 3: TRANSFER FUNCTION
High Byte

Dl0
D9

21

FUNCTION

BUS

0

0

Digital·GrouND return

12

22

110 CONTROL

AD Ao
x x
x x

0

Chip Select enables reading and writing
(active low)

REi

11

CS WR

· FORCE line for' reference input.

4

2:

TABLE

FUNCTION

VREF= -5.0V

EXPECTED OUTPUT CODE
LSB

OVR MSB

0
+0.0003

0
0

0
0

000000000000
000000000000

0
1

+0.150

0

0

000011110101

1

+2.4997
+2.500

0
0

0
1

111111111111
000000000000

1
0

'Bit 1

+4.9994
+4.9997
+5.000
+5.0003

0
0
1
1

1
1
0
0

111111111111
111111111111
000000000000
000000000000

0
1
0
1

Bit 0 (least significant)

+5.150

1

0

000011110101

1

Bits,

(High = True)
Low Byte

Used for programming only (leave open)

DETAILED DESCRIPTION
The ICl7115 is basically a successive approximation

End Of Conversion flag (low = busy,
· high - conversion complete)

AID converter with an internal structure much more complex than a standard SAR-type converter. Figure 2 shows
the functional diagram of the ICl7115 14-bit AID converter.
The additional Circuitry incorporated into the ICl7115 is
used to perform error correction and to maintain the
operating speed .in the 40j.ls range.
The internal 17-bit DAC of the ICl7115 is designed
around a radix of 1.85 rather than the traditional 2.00. This
radix gives each bit of the DACa weight of approximately
54 % of the previous bit. The result is a useable range that
extends to 3% beyond the full-scale input of the A/D. The
actual value of. each bit is measured and stored in the. onchip PROM. The absolute vahle of each bit weight then
becomes relatively unimportant because ofthe error correction action of the ICl7115.
The output of the high-speed auto-zeroed comparator is
fed to the datainput of a 17-bit successive approximation
register (SAR). This register is uniquely designed for the
ICl7115 in that it tests bit pairs instead of ,individual bits in
the manner of a standard SAR. At the beginning of the
conversip" cycle, the SAR turns on the MSB (B16) and the
MSB-4 bit (B12)' The sequence continues for each liIit pair,
Bx and BX-4, until only the four lSBs remain. The sequence
concludes by testing the four LSBs individually.
The SAR output is fed to the DAC register and to the
preprogrammed 17-word by 17-bit PROM where it acts as
PROM address. PROM data is fed to a 17-bit full-adder/
accumulator where the decoded results from each successive phase of the conversion are summed with the previous
results. After 20 clock cycles, the accumulator contains the

·OVerRange flag (valid at end of conversion
when output code exceeds full-scale, threestate output enabled with high byte)

27

V+

28

PROG

Used for programming only. Tie to V+ for
normal operation

29

TEST

Used for programming only. Tie to V + for
normal operation

30

OSC1

Oscillator inverter input

31

OSC2

Oscillator inverter output

32

"SC

PosHive power supply input

, .Short cycle input (high = 14-bH, low = 12-bit
operation)

33

WR

WRite pulse input (low starts new conversion)

34

Auta:-zero capaCitor connection

35

CAl
V-

36

COMP

Negative power supply input
Used in test, tie to V-

37

Y,N.

38
39

VREF.
AGND.

SENSE line for analaQ ground

40

VINf

FORCE line for input voltage

SENSE line for input voltage
SENSE line for reference input

6-70
Note: All typical values have been guaranteed by characterization and are ,not tested.

ICL7115
final binary data which is latched and sent to the three-state
output buffers. The accuracy of the AID converter depends
primarily upon the accuracy of the data that has been
programmed into the PROM during the final test portion of
the manufacturing process.
The error correcting algorithm built into the ICL7115
reduces the initial accuracy requirements of the DAC. The
overlap in the testing of bit pairs reduces the accuracy
requirements on the comparator which has been optimized
for speed. Since the comparator is auto-zeroed, no external
•adjustment is required to get ZERO code for ZERO input
voltage.
Twenty clock cycles are required for the complete 14-bit
conversion. The auto-zero circuitry associated with the
. comparator is employed during the last three clock cycles
of the conversion to cancel the effect of offset voltage. Also
during this time, the SAR and accumulator are'reset in
preparation for the start of the next conversion. When the
Short Cycle (SC) input is low, 18 clock cycles are required
to complete a 12-bit conversion.
The overflow output of the 17-bit full-adder is also the
OVerRange (OVR) output of the ICL7115. Unlike standard
SAR-type AID converters, the ICL7115 has the capability of
providing valid useable data for inputs that exceed the fullscale range by as much as 3%.

INPUT WARNING
As with any CMOS integrated circuit, no input voltages
should be applied to the ICL7115 until the ±5V power
supplies have stabilized.

INTERFACING TO DIGITAL SYSTEMS
The ICL7115 provides three-state data output buffers,
CS, RD, WR, and bus select inputs (Ao and BUS) for
interfacing to a wide variety of microcomputers and digital
systems. The 1/0 Control Truth Table shows the functions
of the digital control lines. The BUS select and Ao lines are
provided to enable the output data onto either 8-bit or 16-bit
data buses. A conversion is initiated by a WR pulse (pin 33)
when CS (pin 3) is low. Data is enabled on the bus when the
chip is selected and RD (pin 4) is low .

¥REFI

ICl7115

'-------'1 AGNo.

OPTIMIZING SYSTEM PERFORMANCE

r-----t

The FORCE and SENSE inputs for VIN and VREF are
also shown driven by external op-amps. This technique
eliminates the effect of small voltage drops which can
. appear between the input pin of the IC package and the
actual resistor on the chip. If the small gauge wire and the
bonds that connect the chip to its package have more than
300mn of total series resistance, the result can be a
voltage error equivalent to 1LSB. If no op-amps are used for
VIN and VREF, connections should be made directly to the
SENSE lines. The external op-amps also serve to transform
the relatively low impedance althe VIN and VREF pins into
a high impedance. The input offset voltages of these
amplifiers should be kept low in order to maintain the overall
AID converter system accuracy.
When using AID converters with more than 12 bits of
resolution, special attention must be paid to grounding and
the elimination of potential ground loops. A ground loop can
be formed by allowing the return current from the ICL7115's
DAC to flow through traces that are common to other
analog circuitry. If care is not taken, this current can
generate small unwanted voltages that add to or detract
from the reference or input voltages of the AID converter.
Ground loops can be eliminated by the use of the analog
ground FORCE and SENSE lines provided on the ICL7115
as shown in Figures 5 and 6. In Figure 5 the FORCE line is
the only point that is connected to system analog ground. In
Figure 6, the op-amp A3 forces the voltage at AGND to be
equal to analog system ground. The addition of this op-amp
overcomes the main deficiency of the arrangement in
Figure 5: the VIN and VREF sources are not referenced to
true analog system ground.
.The clamp diodes in Figure 6 are required because
spurious op-amp output on AGNDf during power-on can
exceed the absolute max rating of ± 1.0V between AGDf
and DGND. The two inverse-parallel diodes clamp the
voltage between AGNDs and DGND to ±O.7V.

AGNDt

DGND

Figure 5: VIN and VREF Input Buffers

'>----1 101•,
'---------1101.,

!,>-----; VA£Ff
ICl7115

'----------I VAEFS
r---------I AGND,
'7.,---r--4 AGNDt

DIODES IN914

-=-

1-

m

DGND

Figure 6: Using a Forced Ground
Figure 7 illustrates atypical interface to an 8-bit microcomputer. The "Start and Wait" operation requires the
fewest external components and is initiated by a low level
on the WR input to the ICL7115 after the 1/0 or memorymapped address decoder has brought the CS input low.
After executing a delay or utility routine for a period of time
greater than the conversion time of the ICL7115, the
processor issues two consecutive bus addresses to read
output data into two bytes of memory. A low level on Ao
enables the LSBs and a high level enables the MSBs.
6-71

Note: All typical values have been guaranteed by characterization .and are not tested.

.! iCL7115·
'"g
L -____~----~__~AD~D~R~E~S~S~BUSr_--------~~--~

Ao

AO-AN

CSI+-----'

lID 1 + - - - - - - - - 1 lID
WR

1 + - - - - - - - - 1 WR

ICL7115

I

DATA BUS

START
CONVERSION -

WAIT

READ
LOW BYTE

. READ
HIGH BYTE

Figure 7: "Start and Wait" Operation
reads the most significant byte until it detects a high level
on the EOC bit. The "Start and Poll" interface increases
data throughput compared with the "Start and. Wait"
method by eliminating delays between the conversion
termination .and the microprocessor read. operation.

By adqing a threl'l-state buffer and two ccmtrol gates, the
End-of-Conversion (EOC) output can be used to. control a
"Start and Poll'.' interface (FigureS). In this mode, the Ao
and CS lines connect the EOC output to the data bus al~
with the most significant byte of data. After pulsing the WR
line to initiate a conversion, the microprocessor continually

6-72
Ncrte: All typical values have been guaranteed by characterization and are hOI' tested.

.D~Do"

ICL7115

P
..........
UI

I

)

wRI.--------r~--~WR

CS 1.--------+....
ROI.--------+~--__1RD

ICL7115

EOC

BUS

DATA BUS

END OF
____ CONVERSION

_START
CONVERSION

POLL-

READ
HIGH BYTE

READ
HIGH BYTE

READ
LOW BYTE

Figure 8: "Start. and Poll" Operation
Other interface configurations can be used to increase
data throughput without monopolizing the microprocessor
during waiting or polling operations by using the EOC line as
an interrupt generator as shown in Figure 9. After the
conversion cycle is initiated, the microprocessor can continue to execute routines that are independent of the AID

converter until the converter's output register actually holds
valid data. For fastest data throughput, the ICL7115 can be
connected directly to the data bus but controlled by way of
a Direct Memory Access (DMA) controller as shown in
Figure 9.

6-73

Note: All typical values have been guaranteed by characterization and are not tested.

.D~DIL

ADDRESS BUS
AD

AD-AN

AD

CS

ICL7115

RD

RD

WR

WR

EOC

iNf

-=

.p

00-0,

DATA BUS

II

S

INTERRUPT ,----

-

~~~RJERSION

READ
LOW BYTE

Figure 9: Using EOC as an Interrupt

6-74
Note: Ali typical values have been guaranteed by characterization and are not tested.

_READ
HIGH BYTE

I

.n~nlb

ICL7115

e..

,QI

s

I

ADDRESS BUS

Ao-AN
EOCr--------------.IDRQN

DMA
CONTROLLER

ICL7115

I

DATA BUS

EOC

Ao

READ
LOW BYTE
ENDOF
CONVERSION

READ
HIGH BYTE

Figure 10: ,Data to Memory via DMA

6--75

Note: All typical values have been guaranteed by characterization an,d are not tested.

I

START

r--- CONVERSION

Con~roller

.U~UIl

" ICL7115'
~

......

''P'

2'

+5V
28 32

29 27

OVR SC TEST V+
VREFI
OSC
5V
REFERENCE

SYSTEM
CLOCK

EOC ~2:::5__________+

Rl
lOOk

HI

R2
lOOk R3
50k

37 Y,N.

ICL7115 DATA{

INPUT VOLTAGE
+5VTO -5V

OUT

LOW BYTE
21
WR j!3~3__________-.
RD ..4'--_________

LOo-----~--~----~\

CS 3
Ao
DGND
ANALOG
GROUND ':"

35

7

BUS

6

,DIODES IN914
DIGITAL
GROUND

Figure 11: Typical Application with Bipolar Input Range, Forced Ground, and 5 Volt Ultra-Stable
Reference

APPLICATIONS
Figure 11 shows a typical application of the ICL7115 14bit AID converter. A bipolar input voltage range of + 5V to
-5V is the result of using the current through R2 to force a
1/2 scale offset on the input amplifier (A2). The output of A2
swings from OV to -5V. The overall gain of the AID' is
varied by adjusting the 100kil trim resistor, Rs. Since the
ICL7115 is automatically zeroed every conversion, the
system gain and offset stability will be superb as long as a
reference with a tempco of 1ppml"C and stable external
resistors are used.

greater than full-scale, and because the converter's OVR
output flags overrange inputs, a simple microprocessor
routine can be employed to precisely measure and correct
for system gain and offset errors. Figure 12 shows a typical
data acquisition system that uses a 5.0V reference, input
Signal multiplexer, and input signal Track/Hold amplifier.
Two of the multiplexer's input channels are dedicated to
sampling the system analog ground and reference voltage.
Here, as in Figure 11, bipolar operation is accommodated
by an offset resistor between the reference voltage and the
summing junction of A1. A flip-flop in IC3 sets 1C2'S Track/
Hold input after the microprocessor has initiated a WR
command, and resets when EOC goes high at the end of
the conversion.

In Figure 11, note that the 0.22/-1F auto-zero capacitor is
connected directly between the CAZ pin and analog ground
SENSE. A3 forces the analog ground of the ICL7115 to be
the zero reference for the input signal. Its offset voltage is
, not important in this example because the voltage to be
digitized is referred to the analog ground SENSE line rather
than system analog ground. It is important to note that since
the 7115's DAC current flows in A1, A2 and A3 these
amplifiers should be wideband (GBW > 20M Hz) types to
minimize errors.

The first step in the system calibration routine is to select
the multiplexer channel that is connected to system analog
ground and initiate a conversion cycle for the ICL7115. The
results represent the system offset error which comes from
the sum of the offsets from IC1, IC2, and A1. Next the
channel connected to the reference voltage is selected and
measured. These results, minus the system offset error,
represent the system full-scale range. A gain error correction factor can be derived from this data. Since the ICL7115
provides valid data for inputs that exceed full-scale by as
much as 3%, the OVR output can be thought of as a valid
15th data bit. Whenever the OVR bit is high, however, the
total 14-bit result should be checked to insure that it falls
within 100% and 103% of full-scale. Data beyond 103% of
full-scale should be discarded.

The clock for the ICL7115 is taken from whatever system
clock is available and divided down to the 500kHz level for a
conversion time of 40/-ls. Output data is controlled by the
BUS and Ao inputs. Here they are set for 8-bit bus operation
with BUS grounded and Ao under the control of the address
decode section of the external system.
Because the ICL7115's internal accumulator generates
accurate output data for input Signals as much as 3%
6-76

Note: All typical values have been guaranteed by characterization and are not tested.

1I0~OIl.

ICL7115

en

ADDRESS BUS

A.

Uk

I.

ANALOG
INPUTS

1

Figure 12: Multi-Channel Data Acquisition System with Zero and Reference Lines Brought to
Multiplexer for System Gain and Offset Error Correction
The ICL7115 provides an internal inverter which is
brought out to pins OSC1 and OSC2, for crystal or ceramic
resonator oscillator operation. The clock frequency is
calculated from:

and
fCLK

18
z --

!cony

20
fCLK = - - for 14-bit operation
tconv

6-77
Note: All typical values have been guaranteed by characterization and, are not tested.

e..

for 12-bit operation

'~ ICL711617117

'~ 3Y2~[)igit LCOll-i.:D , ' ' ,
,Single.-Chip AID Converter
g with Di~play Hold
~

GENERAL DESCRIPTIO",

FEATURES

The IntersillCL7116 and 71178re high performance, low
power 3-h digit AID converterS. All the necessary active
devices are contained on a single CMOS I.C., including
seven segment decoders, display drivers, reference, and a
clock; The 7116 is designed to interface with a liquid crystal
display (LCD) and includes a backplane drive; the 7117 will
directly drive an instrument-size light emitting diode (LED)
display.
The 7116 and 7117 have almost all of the features of the
7106 and 7107 with the addition ofa HoLD Reading input.
With this input, it is possible to make a measurement and
then retain the value on the display indefinitely. To make
room for this feature the reference input has been referenced to Common rather than being fully differential. These
circuits retain the accuracy, versatility, and true economy of
the 71 06 ~nd 7107. They feature auto-zero to ,less than
10,N, zero drift of less than 1JJ.VrC, input bias current of
10pA maximum, and roll over error of less than one count.
The versatility of true differential input is of particular
advantage when measuring load cells, strain gauges and
other bridge-type transducers. And finally, the true economy
of single power supply operation (7116) enables a high
performance panel meter to be built with the addition of only
eleven passive components and a display.

•

I
HUHI

e;; :,
§
-

A1

_

I

Q1
E1

'1

C'REF

COMMON

{ 82

~

F2

D
(tOOO)....

ICL7116CDL
ICL7116CPL
ICL7116CJL
ICL7116CM44
ICL7117CDL
ICL7117CPL •
ICL7117CJL

TEMPERATURE
RANGE
O·C
O·C
O·C
O·C
O·C
O·C
O·C

to
to
to
to
to
to
to

+70·C

+70·t
+70·C
+ ,70·C
+70·C
+70·C
+70·C

08C2

D2

.2
i I=
-

PART NUMBER

:;T3

RIFHI

C2

=

ORDERING INFORMATION

"";--r..,..-...,oac t

Dt

t:

HoLD Reading Input Allows Indefinite Display
Hold
• $uaranteed Zero Reading for 0 Voltil Input
• True Polarity' at Zero for Precise Null DetectIon
'. 1pA Input' Current Typical
• True, DIfferential Input
• Direct Display Drlve- No External Components
Required - LCD ICL7116
-- LE,D ICL7117
• Low Noise - L.ess Than 15JJ.V pk-pk Typical
• On-Chip Clock and Reference
• Low Power Dissipation - Typically Less Than
10mW
• No Additional Active Circuits Required
• New Small Outline Surface Mount Package
Available
.

V'
C~REF

INH.

INLO

~z

aUFF
!NT

~;
~l!._

(TENS)

~

(MIN~4ilII.----iIiII-'r;;~w:rr'17)
COOO8401

COO3251I

Figure 1: Pin Configurations

6-18
Note: All typical values have been guaranteed by characterization anCi

are noi tested.

PACKAGE
40-Pin
40-Pin
40-Pin
44-Pin
4O-Pin
4O-Pin
40-Pin

Ceramic DIP
Plastic DIP
CERDIP
Surface Mount
Ceramic DIP
Plastic DIP
CERDIP

.u~nlb

ICL7116/7117.
ABSOLUTE MAXIMUM RATINGS

ICL7117
Supply Voltage y+ .......................................... +6V
V- ........................................... -9V
Analog Input Voltage (either input) (Note 1) .. V+ to VReference Input Voltage (either input) .......... V + to VHLDA, Clock Input .................................. Gnd to V+
Power Dissipation (Note 2)
Ceramic Package .............................. 1000mW
Plastic Package ........ , ......................... 800mW
Operating Temperature ........................ O°C to +70°C
Storage Temperature ...................... -65°C to + 150°C
Lead Temperature (Soldering, 10sec) ................. 300°C

Note 1: Input voltages may exceed the supply voltages previded the input current is limited to ± 1001lA.
Note 2: Dissipation rating assumes device is mounted with all .leads soldered to printed circuit board.
Stresses above those listed. under •• Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
abSOlute maximum rating condItions for extended periods may affect device reliability ..

ELECTRICAL CHARACTERISTICS (Note 3)
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

-000.0

±OOO.O

+ 000.0

.Digital Reading

999

999/1000

1000

Digital Reading

IV,N I"" 200.0mV

~1

±O.2

+1

Counts

Full Scale - 200mV
or Full Scale = 2.000Y (Note 7)

-1

±0.2

+1

Counts

Y,N =O.OV
Full Scale = 200.0mV

Ratiometric Reading

Y,N =YREF
VREF= l00mV

Rollover Error (Difference in
reading for equal positive and
negative. reading near Full Scale)
Linearity (Max. deviation from
best straight line fit)
Common Mode Rejection Ratio
(Note 4)

VCM = ±lY, Y,N = OV,
Full Scale =200.0mV

50

Noise (Pk - Pk value not exceeded
95% of time)

V'N":'OV
.
Full Scale = 200.0mV

15

Leakage .C~rrent

Y,N = OV (Note 7)

1

10

0.2

1

1

5

ppm/·C

~.

Input

Zero Reading Drift

V'N=O
O·C < TA < 70·C (Note 7)

Scale Factor Temperature
Coefficient

Y,N = 199.0mV
O·C < TA < 70·C
(Ext. Ref. Oppml"C) (Note 7)

V + Supply Current (Does riot
include LED current for 7117)
V- Supply Current (7117 only)

25kn Detwean COMMON
& pos. Supply

Temp. Coeff. of Anal~ Common
(with respect to pos. upply)

25kn between COMMON
& pos. Supply

p.v1V
p-V
pA
. p-V/·C

,

V'N=O

Analog Common Voltage (With
respect to pos. supply)

2.4

0.6

1.6

rnA

0.6

1.6

rnA

2.6

3.2

V
ppml"C

60

Input ReSistance, Pin 1 (Note 6)

30

70

kn

V'L, Pin 1 (7116 only)

TEST + 1.5

V

V'L, Pin 1 (7117 only)

GND+ 1.5

V

V+ -1.5

V'H, Pin 1 (Both)
7116 ONLY
Pk-Pk Segment Drive Voltage
Pk-Pk Backplane Drive Voltage
(Note 5)

G»

ICL7116
Supply Voltage (V + to V-) ................................ 15V
Analog Input Voltage (either input) (Note 1) . V + to VReference Input Voltage (either input) ......... V + to VHLDR, Clock Input. ................................. Test to V+
Power Dissipation (Note 2)
Ceramic Package ........................... , .. 1000mW
Plastic Package .................................. 800mW
Operating Temperature ........................ O°C to + 70°C
Storage Temperature ...................... -65°C to + 150°C
Lead Temperature (Soldering, 10sec) ................. 300°C

Zero Input Reading

p

.........
...
.........

4
4

V+-V-=9V

6-79
Note: All typical values have been guaranteed by characterization and are. not tested.

Y
5
5

6
6

Y

~ ICL7f18/71'17
po.

i'

ELECTRICAL CHARACTERISTICS (CONT.)

~

-

d

PARAMETER

TEST CONDITIONS

7117 ONLY
Segment Sinking Current
(Except Pin 19 and 20)
(Pin 19 only)
(Pin 20 only)

NOTES:

MIN

TYP

5
10
4

8.0
16
7

MAX

UNIT

V+ = 5.0V
Segment Voltage", 3V

mA

3. Unless otherwise noted, specffiCiltions 'apply t9 both the 7116 and 7117. at TA=25'C, fclock = 48kHz. 7116 is tested in the circuit of
Figure 4. 7117. is tested in the circuit of Figure 5.
4. Refer to "Differential Input" disc,ussion.
'
,
5, Back plane driVe is in phase with segment driVe for 'off' segment, 180' out of phase for 'on' segment. Frequency is 20 times
'
conversion rate. Average DC component is less than 50mV.
6. The 7116 logic' Input has an Internal pull-down resistor connected from HLDR, pin 1, to TEST, pin 37. The 7117 logic input has an
internal pull-down resistor connected from HLDR, pin 1 to GROUND, pin 21.
7. Not tested, guaranteed by design.

TEST CIRCUITS

DETAILED DESCRIPTION
Analog Section

I.

+ -

Figure 4 shows the Analog Section for the ICL7116 and
7117. Each measurement cycle is divided into three
phases. They are (1) auto-zero (A/Z), (2) signal integrate
(IND and (3) de-integrate (DE).

Auto-zero phase
During auto-zero three things happen. First, input high
and low are disconnected from the pins and internally
shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback
loop is closed around the system to charge the auto-zero
capacitor CAZ to compensate for offset voltages in the
buffer amplifier, integrator, and comparator.' Since the
comparator is included in the loop, the A-Z accuracy IS
limited only by the noise of the system. In any case, the
offset referred to the input is less than 101lV.

Signal Integrate phase

AF023601

Figure 2: ICL7116 Test Circuit and Typical
Application With liquid Crystal Display

..

."

+-

.
,

...n

",TPI

l;1 .

1SOU

'Nn

~

Tf3

lir

I.

r+.-::~~Al
11-

.

~~ ~fI

IWi

~v

During Signal integrate, the auto-zero loop is opened, the
internal short is removed, and the intermil input high and
low are connected to the external pins. The converter then
integrates the differential voltage between IN HI.and IN LO
for a fixed time. This differential voltage can be within a wide
common mode range; within ohe volt of either supply. If, on
the other hand, the input Signal has no return with respect
to the ,converter power supply, IN LO can be tied to analog
COMMON to establish the correCt common-mode voltage.
At the end of this phase, the polarity of the integrated signal
is determin·ed.

,~ F~.';~~
i

g

. .~

3 ~

•

•i

,

t---

De-integrate phase

,

,

The final phase is de-integrate, or reference integrate.
Input low is internally connected to analog COMMON and
input high is connected across the previously charged
reference capacitor. Circuitry within the chip ensures that
the capacitor will be connected with the correct polarity to '
cause the integrator output to return to zero. The time
'required for the output to return to zero is proportional to the
input signal. Specifically the digital reading displayed is

INTERSIL 7117

~ ~11'11'1 ~l '" I" ~LI~ I-I ~II~ 1·11-11·1 ~I ~II~

d....

....LAV

III II
.-Jo

I, I
I I'9°0

1000 (::).

AF0237o'l

Figure 3: ICL7117 Test Circuit and Typical
Application With LED Display

6-80
Note: All typical values have been guaranteed by characterization and are not' tested.

e......

.O~O[6

ICL7116/7117

-......
at

c.,,,
r-----I

....
....

..

: vI
I

I
I

10~.

I

......._ - TO OIGITAL SECTION

I

'N HI ($II"-"+~~~-+:::-:-~=-:+__---J
I

!NT

I

I
I
I'

A/Z

C~N~I~U~_ _~_~_~_ _ _-J
I

+-_______---..J

INLO,~II""'---Qi~_-~-_ _ _ _ _ _
I
!NT
L
________
---______________

~

~~~T

____________________________________ _

v-

,

"

05013001

Figure 4: Analog Section of 711617117

Differential Input

impedance (=15n), and a temperature coefficient typically
less than 80ppml"C.

The input can accept differential voltages anywhere
within the common mode range of the input amplifier; or
specifically from 0.5 vQlts below the positive supply to 1.0
volt above the negative supply. In this range the system has
a CMRR of typically 86dS. However, since the integrator
also swings with the common mode voltage, care must be
exercised to assure the integrator output does not saturate.
A worse case condition would be a large positive commonmode voltage with a near full-scale negative differential
input voltage. The negative input signal drives the integrator
positive when most of its swing has been used up by the
positive common mode voltage." For these critical applications the integrator swing can be reduced t6 less than the
recommended 2V full scale swing with little loss of accuracy. The integrator output can swing to within 0.3 volts of
either supply without loss of linearity." See A032 for a
discussion of the effects of stray capacitance.

The limitations of the on-chip reference should also be
recognized, however. With the 7117, the internal heating
which results from the LED drivers can cause some
degradation in performance. Due to their higher thermal
reSistance, plastic parts are poorer in this respect than
ceramic. The combination of reference Temperature Coefficient (TC), internal chip disSipation, imd package thermal
resistance can increase noise near full scale from 251lV to
80IlVpk-pk. Also the linearity in going from a high dissipation count such as 1000 (20 segments on) to a low
dissipation count such as 1111 "(8 segments on) can suffer
by a count or more. Devices with a positive TC reference
may require several counts to pull out of an overload
condition. This is because .overload is a low dissipation
mode, with the three least significant digits blanked. SimilarIy, units with a negative TC may cycle between overload
and a nonoverload count as the die alternately heats and
cools. All these problems are of course eliminated if an
external reference is used.

Reference
The reference input must be generated as a positive
voltage with respect to COMMON. Note that.current flowing
in the COMMON pins' internal resistance causes a slight
shift in the effective reference voltage, disturbing ratiometric
readings at low reference inputs. If pOSSible, do not let this
current vary.

The .7116, with its negligible disSipation, suffers from
none of these problems. In either case, an external
reference can easily be added, as shown in Figure 5.

Analog COMMON

Analog COMMON is also the voltage that input low
returns to during auto-zero and de-integrate. If IN LO is
different from analog COMMON, a common mode voltage
exists in the system and is taken care of by the excellent
CMRR of the converter. However, in some applications IN
LO will be set at a fixed known voltage (power supply
common for instance). In this application, analog COMMON
should be tied to the same pOint, thus removing the
common mode voltage from the converter.

This pin is included primarily t6' set thecommCin mode
voltage for battery operation (7116)' or for any system where
the input signals are floating with respect to the power
supply. The COMMON pin sets a voltage that is approximately 2.8 volts less than the positive supply. This is
selected to provide proper operation with a minimum endof-life battery voltage of about 6V. However, the analog
COMMON does have some of the attributes of a reference
voltage. When the total supply voltage is large enough to
cause the zener to regulate ( > 7V), the COMMON voltage
will have a low voltage coefficient (.001 'YoN), low output
6-81

Note: All typical values have been guaranteed by characterization and are riot tested.

II
•

~ IC~7,118/7~,17

too

o......

,
V·

.

i

AEFHI
COMMON

v'

r-

• ....u

'.8 VOLT
HNER

t-.:~ ~
t-+-

2Ok1l

\'

7116n117

lIZ

REF til

DECIIilAL [
POINT
SELECT

~

DECIMAL
POINTS

I

CD4030

I

\QND

Figure 7: Exclusive 'OR" Gate for Decimal
Point Drive

DS013101

Figure 5: Using an External Reference

The second function is a "lamp test". When TEST is
pulled to high (to V +) all segments will be turned on and the
display should read - 1888. [Caution: on the 7116, in the
lamp test mode, the segments have a constant DC
voltage (no square-wave) and will burn the LCD display
If left in this mode for several minutes.]

Within the IC, analog COMMON is tied to an N channel
FET that can sink 30mA or more of current to hold the
voltage 2.8 volts below the positive supply (when a load is
trying to pull the common line positive). However, there is
only 10~ of source current, so COMMON may easily be
tied to a more negative voltage thus over-riding the internal
reference.

DIGITAL SECTION
Figures 8 and 9 show the digital section for the 7116 and
7117, respectively. In the 7116, an internal digital ground is,
generated from a 6 volt Zener diode and a large P channel
source 'follower. This supply is made stiff to absorb the,
relative large capacitive currents when the back plane (BP)
voltage is switched. The BP frequency is the clock frequency divided by 800, For threereadings/second this is a 60Hz
square wave with a, nominal amplitude of 5 volts. The
segments are-driverr at the same frequency and amplitude
and are in phase with BP when OFF, but out of phase when
ON, In, all cases negligible DC voltage exists across the
segments.
Figure 9 is the Digital Section of the 7117. It is identical to
that of the 7116 except the regulated supply and back plane
drive have been eliminated ~nd the segment drive has been
increased "from 2 to SmA, typical for instrument size
common anode LED displays. Since the 1000 output (pin
19) must sink current from two LED segments, it ,has twice
the drive capability or 16mA.
In both devices the polarity indicator is ON for negative
analog inputs. This can be reversed by simply reversing IN
LOand IN HI.

TEST
The TEST pin serves two functions. On the 7116 it is
coupled to the internally generated digital supply through a
soon resistor. Thus it can be used as the negative supply
for externally generated segment drivers ,such as decimal
pOints or any other presentation the user may want to
inClude on the LCD display. Figures 6 and '7 show such an
applicati,On. No more than a ,1 mA load should be applied.

V.'

,lIIn

TOLCO
DECIMAL POINT

. . 2'

TEST t;37;;-!t--~

I

AF024101

(b)

INTERSn.
1T171O

t

I

L ____ ~
GROUND = DP OFF.

~~~~VT=DPON.

~

7116

:~g±lTOLcD
D+:D+
,
,

'-COMMON

(aj

7116

r-~~ ~,ICL""
,',2V REFERENCE

~

7116/7117

r---------------I~

V·

TO LCD

' - - - - B A C K PLANE

HOLD Reading Input

AF024001

The HLDR input will prevent the latch from being updated
when this input is at a logic "1". The chip will continue to
make AID conversions, however, the results will notba,
updated to the internal latches until this input goes low: This
input can be left open or connected to TEST (7116) or'
GROUND (7117) to continuously update the display. ThiS
inp\Jt'is CMOS compatible, and has a 70kntypical resistance to either TEST (7116) or GROUND (7117).

Figure 6: Simple Inverter ,or Fixed Decimal
Point

6-82
Note: All typical values have been guaranteed by characterization and are not tested.

.U~U16

ICL7116/7117
DISPLAY FONT

a :2 :3 '-I

e......

Gl
......

.........
...

5 6 -: 8 9

------------------------·--·--.--·----.--.----+------4.1~~4+·t-·.-tt~14~+··-~~~tll~-----~~.=~~~~

-----------------------_ ....:=_._.-

LCOO5201

Figure 8: Digital Section 7116

6-83
Note: All typical values have been guaranteed by characterizatiQn and are not tested.

IC1..711617117
DISPLAY FONT (CONT.)

o CI ,It,
C
t
•
I '..' .'."
I·

-------------------------------------

--------,,,
I
I

I
I
I
I
I

I
I

I
I
I

I

I
I
I
I
I
I

35.

--~~------~~----------~--~--~_+----------~v.

naT

,~,

LC005301

Figure 9: Digital Section 7117

System Timing

,and auto-zero (1000 to 3000 counts). For signals less than
full scale, auto-zero gets the unused portion of reference
deintegrate. This makes a complete measure cycle of 4,000
(16,000 clock pulses) independent of input voltage. For
three readings/second, an oscillator frequency of 48kHz
would be used.

Figure 10 shows the clocking arrangement used in the
7116 and 7117. Three basic clocking arrangements can be
used:
1. An external oscillator connected to pin 40.
2. A crystal between pins 39 and 40.
3. An R-C oscillator using all three pins.

,

To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. Oscillator
frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz,
40kHz, 33 YakHz, etc. should be selected. For 50Hz rejection, Oscillator frequencies of 200kHz, 1OOkHz, 66~kHz,
50kHz, 40kHz, etc. would be suitable. Note that 40kHz (2.5
readings/second) will reject both 50 and 60Hz (also 400
and 440Hz).

,
I
I

I
I
I

TO
:
COUN. . . ,
I

I

I
I
I

,

I _______ _
L

~--------

..

I

:
'

_________ J

COMPONENT VALUE SELECTION
Integrating Resistor
Both the buffer amplifier and the integrator have a class A
output stage with 1001lA of quiescent current. They can
supply 201lA of drive current with negligible non-linearity.
The integrating resistor should be large enough to remain in
this very linear region over the input voltage range, but
small enough that undue leakage requirements are not
placed on the PC bOl!,rd. For 2 volts full scale, 470kU is
near optimum and similarly a 47kU resistor is optimum for a
200.0mV scale.

TIlT e111.)
orGND(n'7)
LCO05401

Figure 10: Clock Circuits
The oscillator frequency is divided by four before it clocks
the decade counters. It is then further divided to form the
three convert-cycle phases. These are signal integrate
(1000 counts), reference de-integrate (0 to 2000 counts)
6-84

Note: All typical values have been guaranteed by characterization and are not tested.

ICL7116/7117

IID~DIl

Integrating Capacitor

and an inexpensive I.C. Figure 11 shows this application .
See ICL7660 data sheet for an alternative.
.

The integrating capacitor should be selected to give the
maximum voltage swing that ensures tolerance build-up will
not saturate the integrator swing (approx. 0.3 volt from
either supply). In the 7116 or the 7117, when the analog
COMMON is used as a reference, a nominal ±2 volt full
scale integrator swing is fine. For the 7117 with ±S volt
supplies and analog common tied to supply ground, a ±3.S
to ±4 volt swing is nominal. For three readings/second
"(48kHz clock), nominal values for CINT are 0.22j.1F and
0.10j.lF, respectively. Of course, if different oscillator frequencies are used, these values should be changed in
inverse proportion to maintain the same output swing.
An additional requirement of the integrating capacitor is it
have low dielectric absorption to prevent roll-over errors.
While other types of capacitors are adequate for this
application, polypropylene capacitors give undetectable
errors at reasonable cost.

OSC3t-rllt---'
7117

v-

TC021301

Figure 11: Generating Negative Supply
from +5v

Auto-Zero Capacitor
The size of the auto-zero capacitor has some influence
on the noise of the system. For 200mV full scale where
noise is very important, a 0.47j.1F capacitor is recommended. On the 2 volt scale, a 0.047j.1F capacitor increases
the speed of recovery from overload and is adequate for
noise on this scale.

In fact,in selected applications no negative supply is
required. The conditions to use a single + SV supply are:
1.

The input signal can be referenced to the center of
the common mode range of the converter.

Reference Capacitor

2.

The signal is less than ± 1.S volts in magnitude.

A 0.1 j.lF capacitor gives good results in most applications. If rollover errors occur a larger value, up to 1.0j.lF may
be required.

3.

An external reference is used.

TYPICAL APPLICATIONS

Oscillator Components

The 7116 and 7117 may be used in a wide variety of
configurations. The circuits which follow show some of the
possibilities, and serve to illustrate the exceptional versatility of these A/D converters.

for all ranges of frequency a 1bOkU resistor is recommended and the capacitor is selected from the equation
f""~' For 48kHz clock (3 readings/second), C = 100pF.
RC

Reference Voltage
The analog input required to generate full-scale output
(2000 counts) is: VIN = 2VREF. Thus, for the 200.0mV and
2.000 volt scale, VREF should equal 100.0mV and 1.000
volt, respectively. However, in many applications where the
A/D is connected to a transducer, there will exist a scale
factor other than unity between the input voltage and the
digital reading. For instance, in a weighing system, the
designer might like to have a full scale reading when the
voltage from the transducer is 0.682V. Instead. of dividing
the input down to 200.0mV, the deSigner should use the
input voltage directly and select VREF = 0.341V. Suitable
values for integrating resistor and capacitor would be
120kU and 0.22j.1F. This makes the system slightly quieter
and also avoids a divider network on the input. The 7117
with ±S volts supplies can accept input Signals up to ±4
volts. Another advantage of this system occurs when a
digital reading of zero is desired for VIN *0. Temperature
and weighing systems with a variable tare are examples.
This offset reading can be conveniently generated by
connecting the voltage transducer between IN HI and
COMMON and the variable (or fixed) offset voltage between COMMON and IN LO.

711.
~

Ole'

.

pee 2

,~

..A

.....

Olea
TaT

.'HI

fo-

V+

eMF
c_ ~
eo_

"'HI

..,..

1oI¥MF-'oo.oonv

/

.ICII

.1<

121m
11111

+

• .01,.,

INLO
IoIZ
BUFF
INT

0A7,...F

.A onell

".n.'

v-

IN

-.: ':'IV

y

0.
C3
}TOOllPUlY

Ao

Go
BP

I--

TO /lACK PLANE

2'
CD008501

Figure 12: 7116 using the internal reference.
Values shown are for 200.0mV full scale, 3
readings per second, floating supply voltage
(9V battery).

7117 Power Supplies
The 7117 is designed to work from ±S volt supplies.
However, if a negative supply is not available; it can be
generated from the clock output with 2 diodes, 2. capacitors,
6-85
Note: All typical values have been guaranteed by characterization and are not tested.

P
...j
.......
.........
...
Gt

-IC:L711'S/1117
TYPICAL APPLICATIONS .

.

7117

.

7117

'-"

OSC1

,_Ii]

oscz
OSC3
TEST
REf HI

·OSC1
100tcH
~: : L.I---1I-'VV'v~~ Set YREF =100.GmV
TEST
A.FHI

,_'

y.

,,/

C REF
C REF

COMMON

.~ v

bO."

. AlZ

--=r=.01,..F

---''--:22,..F

Y-

:

G,
C,

rro

A3

I
-.;.,,----- -------:..---~

0:1=

C0008801

7117
Ole 1

..
J...--_

I
I

TO DIGITAL SECTION

I S1
WHIQr~~~~--~~~~~t-----~

I

I
I

I

INT

Uy
AlZ

I

C~NG'F·~----~---1~~h---~
I

:::-

INLOQ'~·~~~----~~--------------~~--------------J
L____'!!."__________________ .!: '!! ____________________________________ _
8D003701

Figure 2: Analog Section of 7126

TEST CIRCUITS
IN
r-------<~----'+-+-.f--llill
IY
240KCl 1Mn

•n

-. i

II

n

- •. -,

AF024201

Figure 3: ICL7126 with Liquid Crystal Display

AF024301

Figure 4: 7126 Clock Frequency
16kHz. (1 reading/sec)

6-90
Note: All typical values have been guaranteed by characterization· and are not tested.

n
r-

ICL7126
input signal. Specifically the digital reading displayed is
1000 (~).

IN

VREF

......

=

Differential Input
The input can accept differential voltages anywhere
within the common mode rante of the input amplifier; or
specifically from 0.5 Volts below the positive supply to 1.0
Volt above the negative supply. In this range the system has
a CMRR of 86 db typical. However, since the integrator also
swings with the common mode voltage, care must be
exercised to assure the integrator output does not saturate.
A worst case condition would be a large positive commonmode voltage with a near full-scale negative differential
input voltage. The negative input Signal drives the integrator
positive when most of its swing has been used up by the
positive common mode voltage. For these critical applications the integrator swing can be reduced to less than the
recommended 2V full scale swing with little loss of accuracy. The integrator.output can swing within 0.3 Volts of either
supply without loss of linearity.

AF024401

Figure 5: Clock Frequency 48kHz.
(3 readings/sec)

Differential Reference
The reference voltage can be generated anywhere within
the power supply voltage of the converter. The main source
of common mode error is a roll-over voltage caused by the
reference capacitor losing or gaining charge to stray
capacity on its nodes. If there is a large common mode
voltage, the reference capaCitor can gain charge (increase
voltage) when called up to de-integrate a positive signal but
lose charge (decrease voltage) when called up to deintegrate a negative input signal. This difference in reference
for (+) or (-) input voltage will give a roll-over error.
However, by selecting the reference capacitor large enough
in comparison to the stray capacitance, this error can be
held to less than 0.5 count for the worst case condition.
(See Component Value Selection.)

DETAILED DESCRIPTION
Analog· Section
Figure 2 shows the Functional Diagram of the Analog
Section for the ICL7126. Each measurement cycle is
divided into three phases. They are (1) auto-zero (A-Z), (2)
signal integrate (IND and (3) de-integrate (DE).
Auto-zero phase
During auto-zero three things happen. First, input high
and low are disconnected from the pins and internally
shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback
loop is closed around the system to charge the auto-zero
capacitor CAZ to compensate for offset voltages in the
buffer amplifier, integrator, and comparator. Since the
comparator is included in the loop, the A-Z accuracy is
limited only by the noise of the system. In any case, the
offset referred to the input is less then 1O~N.
Signal Integrate phase
During signal integrate, the auto-zero loop is opened, the
internal short is removed, and the internal input high and
low are connected to the external pins. The converter then
integrates the differential voltage between IN HI and IN LO
for a fixed time. This differential voltage can be within a wide
common mode range; within one Volt of either supply. If, on
the other hand, the input signal has no return with respect
to the converter power supply, IN LO can be tied to analog
COMMON to establish the correct common-mode voltage.
At the end of this phase, the polarity of the integrated signal
is determined.
De-integrate phase
The final phase is de-integrate, or reference integrate.
Input low is internally connected to analog COMMON and
input high is connected across the previously charged
reference capacitor. Circuitry within the chip ensures that
the capacitor will be connected with the correct polarity to
cause the integrator output to return· to zero. The time
required for the output to return to zero is proportional to the

Analog COMMON
This pin is included primarily to set the common mode
voltage for battery operation or for any system where the
input Signals are floating with respect to the power supply.
The COMMON pin sets a voltage that is approximately 2.8
Volts more negative than the positive supply. This is
selected to give a minimum end-of-life battery voltage of
about 6V. However, the analog COMMON has some of the
attributes of a reference voltage. When the total supply
voltage is large enough to cause the zener to regulate
( < 7V), the COMMON voltage will have a low voltage
coefficient (0.001 %/%), low output impedance (",,15n),
and a temperature coefficient typically less than 80ppm/oC.
The limitations of the on-chip reference should also be
recognized, however. The reference temperature coefficient (TC) can cause some degradation in performance.
Temperature changes of 2 to 8°C, typical for instruments,
can give a scale factor error of a count or more. Also the
common voltage will have a poor voltage coefficient when
the total supply voltage is less than that which will cause the
zener to regulate ( < 7V). These problems are eliminated if
an external reference is used, as shown in Figure 6.

6-91
Note: All typical values have been guaranteed by characterization and are not tested.

6

y'

y+

Y'

8.1-----_-i-4

27KII

7126

COMMON
AF024601

Figure 8: Exclusive 'OR' Gate for
Decimal Point Drive

y-

lal

101
.

D8013201

Figure 6: Using an' External ..Reference

The Second function is a "lamp test." When ,TEST is
pulled high (to V +) all segments will be turned on and the
display should read - 1888. The TEST pin will sink about
10mA under these conditions.
Caution: In the lamp test mode, the segments have a
constant D-C voltage (no square-wave) and may burn
the LCD display if left in this mode for extended
periods.

Analog COMMON is also used as the input low return
during auto·zero and de·integrate. If INLO is different from
analog COMMON, a commoh mode voltage exists in the
system and is taken care of by the excellent CMRR of the
converter. However, in some applications IN LO will be set
at a fixed known voltage (power supply common for
instance). In this application, analog COMMON should be
tied to· the same point,' thus -removing the common mode
voltage from the converter. The same holds true for the
reference voltage. If reference can be conveniently refer·
eMced to analog COMMON, it should be since this removes
the -common mode voltage from the reference system.

DIGITAL SECTION
Figure 9 shows the digital section for the 7126. An
internal digital ground is generated from a 6 Volt Zener
diode and a large P channel source follower. This supply is
made stiff to absorb the relative large capacitive currents
when' the back plane (BP) voltage is' switched. The BP
frequency is the clock frequency divided by 800. For three
readings/second this is a 60 Hz square wave with a nominal
amplitude of 5 Volts. The segments are driven at the same
frequency and amplitude and are in phase. with BP when
OFF, but out of phase when ON. In all cases negligible DC
voltage exists across the segments. The polarity indication
is "ON" for negative analog inputs. If IN LO and IN HI are
reversed, this indication can be reversed also, if desired.

Within the IC, analog COMMON is tied to an N channel
FET that can sink 3mA or more of current to hold' the
voltage 2.8 Volts below the positive supply (when a load is
trying to pull the commofl line positive). However, there is
only 1p.A of source currerit, so COMMON may easily be tied
to a more negative voltage thus over·riding the internal
reference.

TEST
The TEST pin serves two functions. It is coupled to the
internally generated digital supply through a 500n resistor.
Thus it can be used as the negative supply for externally
generated segment drivers such as .decimal pOints or any
other presentation the user may want to include on the LCD
display. Figures 7 and 8 show such an appiication. No more
than a 1rnA load should be applied,

1M!"!

7126

TO LCD·

INTEASIL
IT1750

DECIMAL POINT

AF024501',

Figure 7: Simple Inverter for Fixed
Decimal Point

6-92
Note: All typical values have been guaranteed by characterization and are not tested.

n
r-

ICL7126

.......
N

DISPLAY FONT

G)

0123'156789
----------------------------------.--.---.~-·-----,I~~++~~··--~~.·+4·,+--~1~4-~~+4-·---

TYPICAL SEGMENT OUTPUT

1\'

Three inverters.
One inverter shown for clarity.

--------+-~--~~v__________________________
..J

osc 1

osc 2

OSC3

LCOO5511

Figure 9: Digital Section

,

The oscillator frequency is divided by four before it clocks
the decade counters. It is then further divided to form the
three convert-cycle phases. These are signal integrate
(1000 counts), reference de-integrate (0 to 2000 counts)
and auto-zero (1000 to 3000 counts). For signals less than
full scale, auto-zero gets the unused portion of reference
deintegrate. This makes a complete measure cycle of 4,000
(16,000 clock pulses) independent of input voltage. For
three readings/second, an oscillator frequency of 48kHz
would be used.

I

I
I
I
I

TO
:
COUNTERI
I

I

,
I

I
I

I

I
IL _____ _

~

_____________ ..JI

nST
D5013301

To achieve maximum rejection of 60 Hz pickup, the signal
integrate cycle should be a multiple of 60 Hz. Oscillator
frequencies of 60kHz, 48kHz, 40kHz, 33-1/3kHz, etc.
should be selected. For 50Hz rejection, oscillator frequencies of 66-2/3kHz, 50kHz, 40kHz, etc. would be suitable.
Note that 40kHz (2.5 readings/second) will reject bott, 50
and 60Hz (also 400 and 440Hz).

Figure 10: Clock Circuits

System Timing
Figure 10 shows the clocking arrangement used in the
7126. Three basic clocking arrangements can be used:
1. A,n external oscillator connected to pin 40.
2. A crystal between pins 39 and 40.
3. An R-C oscillator using all three pins.
6-93

Note: All typical values have been guaranteed by characterization and are· not tested.

.....

I JCL7126

5!

COMPONENT VALUE SELECTION

the system slightly quieter and also avoids the necessity of
a divider network on the input. Another advantage of this
system occurs when a digital reading of zero is desired for
VIN =F O. Temperature and weighting systems with a variable tare are examples. This offset reading can be conveniently generated by connecting the voltage transducer
between IN HI and COMMON and the variable (or fixed)
offset voltage between COMMON and IN LO.

Integrating Resistor
Both the buffei.'amplifier and the integrator have a class A
output stage with 6pA. of quiescent current. They can supply
-1 pA. of drive current with negligible non' linearity. The
integrating resistor should be la~ge enough to remain in this'
very linear region over the input'. voltage range, but small
enough that undue leakage 'requirements are not placed on
the PC board. For 2 Volt full scale, ,1..8mn is near optim!Jm '
and similarly 180kn for a 200.0rtlV' scale.

TYPICAL APPLICATIONS

Integrating Capacitor

The 7126 may be used in a wide variety of configurations.
The circuits which follow show some of the possibilities, and
serve to illustrate the exceptional versatility of these AI D
converters.

The integrating capacitor should be selected to give the
maximum voltage SWing that ensures tolerance build-up will
not saturate the integrator swing (approx. 0.3 Volt from
either supply). When the analog COMMON is used as a
reference, a nominal ±2 Volt full scale integrator swing is
fine. For three readings/second (48kHz clock) nominal
values for CINT are 0.047/lF, for 1Isec (16kHz) 0.15/lF. Of
course, if different oscillator frequencies are used, these
values should be changed in inverse proportion to maintain
the same output swing.
The integrating capacitor should have low dielectric
absorption to prevent roll-over errors. While other types
may be adequate for this application, polypropylene capacitors give undetectable errors at reasonable cost.
At three readings/sec., a 750n resistor should be placed
in series with the integrating capacitor, to compensate for
comparator delay. See App. Note A017 for a description of
the need and effects of this resistor.

'-'

osc.

..

To pin 1 11OKO

OSC2
OSC3
TEST

Sel VNf '" tOO.OmY

/

5CIpF

REF HI
REFLO
CREf
C REF
COMMON
INH.

1= 30,•. ~
0.33,..F I I

110ICn

BUFF
INT
G,
C,

..,

Auto-Zero Capacitor

'G,
BP

The size of the auto-zero capacitor has some influence
on the noise of the system. For 200mV full scale where
noise is very important, a 0.321lF capacitor is recommended. On the 2 Volt scale, a 0.033/lF capacitor increases
the speed of recovery from overload and is adequate for
noise on this scale.

220KO

,

1MB

..01,..f

INLO
AiZ

y-

101CO

A,

8

75011

-'L

.. 0.047,..F

IN

,::

tV

T

}TO DISPLAY

~ TO BACK PLANE

2.

CDOO920!

Figure 11: 7126 using the internal
reference.
Values shown are for 200.0mV full scale, 3
readings per second, floating supply voltage
(9V battery).

Reference Capacitor
A 0.1/lF capacitor gives good results in most applications. However, where a large common mode voltage exists
(i.e., the REF LO pin is not analog COMMON) and a 200mV
scale is used, a larger value is required to prevent roll-over
error. Generally 1.0/lF will hold the roll-over error to 0.5
count in this instance.

Oscillator Components
For all ranges of frequency a 50pF capacitor is recommended and the resistor is selected from the approximate
0.45
'
equation f - - - . For 48kHz clock (3 readings/second),
RC
R = 180kn.

Reference Voltage
The analog input required to generate full-scale output
(2000 counts) is: VIN = 2VREF. Thus, for the 200.0mV and
2.000 Volt scale, VREF should equal 100.0mV and 1.000
Volt, respectively. However, in many applications where the
AID is connected to a transducer, there will exist a scale
factor other than unity between the input voltage and the
digital reading. For instance, in a weighing system, the
designer might like to have a full scale reading when the
voltage from the transducer is 0.682V. Instead of dividing
the input down to 200.0mV, the designer should use the
input voltage directly and select VREF = 0.341V. A suitable
value for integrating resistor would be 330kn. This makes
6-94
Note: All typical values have been guaranteed by characterization and are not tested,

ICL7126
'-'

ose 1
osea

.

~

QSe3
SOpF

TEST

REF HI
REF LO

C REF
C REF

COMMON

PO.'

20KIl
,A

ose2

/

OSC 3

.~.
1l

REF LO
CREF
C REF
COMMON

T

.,01"F

IN

0.15/.-'

COO10101

OPt

80003801

Figure 1: Functional Diagram

Figure 2: Pin Configuration
(outline dwg PL)

6-98
Note: All typical values have been guaranteed by characterization and are not tested.

301663-002

ICL7129
ABSOLUTE MAXIMUM RATINGS
Supply Voltages (V + to V-) .............................. 15V
Reference Voltage (REF HI or REF LO) ....... V+ to VInput Voltage (Note 1)
(IN HI or IN LO) ............................. V+ to VVDISP ....................................... DGND -0.3V to V+
Digital Input Pins
1,2, 19,20,21,22,27,
37, 38, 39, 40 ............................ DGND to V+

Power Dissipation (Note 2)
Plastic package ................................... 800mW
Operating Temperature ........................ O°C to + 70°C
Storage Temperature ...................... -65°C to + 150°C
Lead Temperature (Soldering, 10sec) ................. 300°C

Nole 1: Input voltages may exceed Ihe supply voltages provided that input current is limited to ±400/lA. Currents above this value may result in
invalid display readings but will not destroy the device if limited to ± 1rnA.
Nole 2: Dissipation ratings assume device is mounted with all leads soldered to printed circuit board.
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
to V + = 9V, VREF = 1.00V. TA = + 25°C, fCLK = 120kHz, unless otherwise noted.

v-

CHARACTERISTICS

VIN ~ OV
200mV Scale

Zero Reading Drift

VIN ~ OV
O'C __-.........;1~9 VOISP
5k

>...I-----,I~

L--~o--_--.:.=-t VDISP

ICL7129

ICL7129

36 DGND

DGND

18k

75k

~

____~~____________-.23

~

__________.. 23

V-

VlOO05201

Figure 14: Two Methods for Temperature Compensating the Liquid Crystal Display
For different conversion rates,. the value will change in
inverse proportion. Asecond requirement for good linearity
is that the capacitor have lo'lli dielectric absorption. Polypropylene caps give good perf.ormance at a reasonable price.
Finally. the foil side of the cap should be connected to the
integrator output to shield against pick-up.

DISPLAY TEMPERATURE
COMPENSATION
For most applications an adequate display can be
obtained by connecting VOISP (pin 19) to DGND (pin 36). In
applications where a wide temperature range is encountered, the voltage drive levels for some triplexed liquid
crystal displays may need to vary with temperature in order
to maintain good display contrast and viewing angle. The
amount of temperature compensation will depend upon the
type of liquid crystal used. Display manufacturers can
supply the temperature compensation requirements for
their displays. Figure 14 shows two circuits that can be
adjusted to give a temperature compensation of "" + 1OmV I
'c between V + and VOISP. The diode between DGND and
VOISP should hav.e a low turn-on voltage to assure that no
forward current is injected into the chip if VOISP is more
.
negative than DGND.

The only requirement for the reference cap is that it be
low leakage. In order to reduce the effects of stray
capacitance, a 1.0j.lF value is recommended.

CLOCK OSCILLATOR
The ICL7129 achieves its digital range changing by
integrating the input Signal for 10bo clock pulses (2,000
oscillator cycles) on the 2V scale and 10,000 clock pulses
on the 200mV scale. To achieve complete rejection of 60Hz
on both scales, an oscillator frequency of 120kHz is
required, giving two conversions per second.

COMPONENT SELECTION

In low resolution applications, where the converter uses
only 3'Y2 digits and 100j.lV resolution, an R-C type oscillator
is adequate, In this application a C of 51pF is recommended
and the resistor value selected from fosc = 0.45/RC.
However, when the converter is used to its full potential
(41;2 digits and. 10j.lV resolution) a crystal osciilator is
recommended to prevent the noise from increasing as the
input signal is increased due to frequency jitter of the R-C
oscillator. Both R-C and crystal oscillator circuits are shown
in Figure 15.

There are only three passive components around the
ICL7129 that need special consideration in selEiction. They
are the reference capacitor, integr-ator resistor, and integrator capacitor. There is no auto-zero capacitor like that found
in earlier integrating AID converter designs.
The integrating resistor is selected to be high enough to
assure good current linea.rityfrom the buffer amplifier and
integrator and low enough that PC board leakage is not a
problem. A value of 1~Okn should be optimum for most
applications. The integrator capacitor is selected to give an
optimum integrator swing at full-scale. A .large integrator
swing will reduce the effect of noise sources in the
comparator but will affect rollover error if the swing gets too
close to the positive rail (""O.7V). This gives an optimum
swing of ""2.5V at full-scale. For a 150kn integrating
resistor and 2 conversions per second the value is 0.10j.lF.
6-106

Nole: All typical values have been guaranleed by characlerization and are not tested.

ICL712.9
I

I

+5V

I

I

I

ICL7129

I

I

_ _ _ ..JI

L_

2

V~EFHI

~:~: ICL~~LO

~

I
I

I
I
I
I

ICL7129

I

40

DGNO

COM

35

28

IN HI !-,33=--..~W'v--o +

":"

I
___ -.I

L_

36

ICL8069

Y,N

O.l,F

2

V-

-o

IN LO,!-'3=2_+-_ _ _

23

270kll
5pF

v+ ~

120kHz

10pF

~ 01------4--1 ~ v+

-5V
D5027801

05013501

Figure 15: RC and Crystal Oscillator Circuits

Figure 16: Powering the ICL7129 from +5V
and -5V Power Supplies

POWERING THE ICL7129

When a battery voltage between 3.8V and 7V is desired
for operation, a voltage doubling circuit should be used to
bring the voltage on the ICL7129 up to a level within the
power supply voltage range. This operating mode is shown
in Figure 17.

The ICL7129 may be operated as a battery powered
hand-held instrument or integrated into larger systems that
have more sophisticated power supplies. Figures 16, 17,
and 18 show various powering modes that may be used
with the ICL7129.
The standard supply connection using a 9V battery is
shown in Figure 3.
The power connection for systems with +5V and -5V
supplies available is shown in Figure 16. Notice that
measurements are with respect to ground. COMMON is not
connected to INPUT La but is used only as a pre-regulator
for the external voltage reference.
It is important to notice that in Figure 16, digital ground of
the ICL7129 (DGND pin 36) is not directly connected to
power supply ground. DGND is set internally to approximately 5V less than the V + terminal and is not intended to
be used as a power input pin. It may be used as the ground
reference for external logie, as shown in Figure 7 and 8. In
Figure 7, DGND is used as the negative supply rail for
external logic provided that the supply current for the
external logiC does not cause excessive loading on DGND.
The DGND output can be buffered as shown in Figure 8.
Here, the logic supply current is shunted away from the
ICL7129 keeping the load on DGND lew. This treatment of
the DGND output is necessary to insure compatibility when
the external logic is used to interface directly with the logiC
inputs and outputs of the ICL7129.

24

v+
+
:

REF 34
HI

REFLO 35

3.8VT08V
38 OOND

COM 28

ICLl129'N HI "'33"--+-_-'V.....-o

+
ICL7660

23

TC021501

Figure 17: Powering the ICL7129
from a 3.8V to 6V Battery

6-107
Note: All typical values have been guaranteed by characterization and are not tested.

:l... ICL7129
~

g

VOLTAGE REFERENCES

Again measurements are made with respect to COMMON since the entire system is floating. Voltage doubling is
accomplished by using an ICL7660 CMOS voltage convert-,
er and two inexpensive electrolytic capacitors. The same
principle applies in Figure 18 where the ICL7129 is being
used in a system with only a single + 5V power supply. Here
measurements are made with respect to power supply
ground.

The COMMON output of the ICL7129 has a temperature
coefficient of ±80ppm/oC typically. This voltage is only
suitable asa reference voltage for applications where
ambient temperature variations are expected to be minimal.
When the ICL7129 is used in most environments, other
voltage references should be considered. The diagram in
Figures 3 and i 8 show the ICL8069 1.2V band-gap voltage
source used as the reference for the ICL7129, and the
COMMON output as its pre-regulator. The reference voltage for the ICL7129 is set to 1.000V for both 2V and 200mV
full-scale operation.

A Single polarity power supply can be u,sed to power the
ICL7129 in applications where battery operation is not
appropriate or convenient only if the power supply is
isolated from system ground. Measurements must be
made with respect to COMMON or some other voltage
within its input common-mode range.

+5V'~~~~~~~----------.-------~

24
O.l,.F

y+

ICL8088

O.l~F

38

ICL7129

8

33

2

+
3

ICL7880

4

lo,.F

+
YIN

32
y23

5

':'

+
':'
08013601

Figure 18: Powering the ICL7129 from a Single Polarity Power Supply

6-108
Note: All typical values have been guaranteed by characterization and are not tested.

ICL7134
14-Bit Multiplying J,lP-Compatible
D/A Converter
GENERAL DESCRIPTION

FEATURES

The ICL7134 combines a four-quadrant multiplying DAC
using thin film resistor and CMOS circuitry with an on-chip
PROM-controlled correction circuit to achieve true 14-bit
linearity without laser trimming.
Microprocessor bus interfacing is eased by standard
memory WRite cycle timing and control signal use. Two
input buffer registers are separately loaded with the 8 least
significant bits (LS register) and the 6 most significant bits
(MS register). Their contents are then transferred to the 14bit DAC register, which controls the output switches. The
DAC register can also be loaded directly from the data
inputs, in which case the registers are transparent.
The ICL7134 is supplied in two versions. The ICL7134U
is programmed for unipolar operation while the ICL7134B is
programmed for bipolar applications. The VREF input to the
most significant bit of the DAC is separated from the
reference input to the remainder of the ladder. For unipolar
use, the two reference inputs are tied together, while for
bipolar operation, the polarity of the MSB reference is
reversed, ' giving the DAC a true 2's complement input
transfer function. Two resistors which facilitate the reference inversion are included on the chip, so only an external
op-amp is needed. The PROM is coded to correct for errors
in these resistors as well as the inversion of the MSB.

•
•
•
•
•
•
•

14-l3it Linearity (0.003% FSR)
No Gain Adjustment Necessary
Microprocessor-Compatible With Double Buffered
Inputs
Bipolar Application Requires No Extra
Adjustments or External Resistors
Low Linearity and Gain Temperature Coefficients
Low Power Dissipation
Full Four-Quadrant Multiplication

CD010201

Figure 1: Pin Configuration (Outline dwg JI)

ORDERING INFORMATION
TEMPERATURE RANGE
NON-LINEARITY
O°C to +70°C

- 25°C to + 85°C

-55°C to + 125°C

ICL7134BJCJI
ICL7134BKCJI
ICL7134BLCJI

ICL7134BJIJI
ICL7134BKIJI
ICL7134BLlJI

ICL7134BJMJI
ICL7134BKMJI
ICL7134BLMJI

ICL7134UJCJI
ICL7134UKCJI
ICL7134ULCJI

ICL7134UJIJI
ICL7134UKIJI
ICL7134ULlJI

ICL7134UJMJI
ICL7134UKMJI
ICL7134ULMJI

Bipolar Versions
0.01 % (12-bit)
0.006% (13-bit)
0.003% (14-bit)
Unipolar Versions
0.01 % (12-bit)
0.006% (13-bit)
0.003% (14-bit)
PACKAGE: 28-pin CERDIP only

6-109
Note: All typieal values have been

~!:.J.;..'..r;~nI.0ed

by characterization and are not tested.

301664-002

. ICL7134
~

.......

S:!

ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage (v+ to DGND) .............. -O.3V to 7.5V
VRFL, VRFM, RINV, RFB to DGND ...................... ±15V
lOUT, AGNDF, AGNDs .......................... -O.W to·V+
Current i~GNDS, AGNDF ........................... :t. 25mA
An, On, WR, CS, PROG ............... -O.3V to V + O.3V

Operating Temperature Range
ICl7134XXC ............................. O°C to +70°C
ICl7134XXI ........................... - 25°C to + 85°C
ICl7134XXM ........................ -55°C to +125°C
Storage Temperature Range ; ........... -65°C to. + 150°C
Power Dissipation (Note 2) ............................. 500mW
Derate Linearly Above 70°C @ 1OmW JOC
lead Temperature (Soldering, 10sec) ................. 300°C

Note 1: All voltages with respect to DGND.
Note 2: Assumes all leads soldered or welded to printed circuit ,board.
Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditionS above those indicated in the operational sections of the specifications is not implied. Exposure \0
absolute maximum rating conditions for extended periods may affect device reliability.

VRFM

VRFL
F

AINV

RFB

F

A=7IcilTYP

A
2A

2A

A
2A

A
2A

A

2R

2R

2A

,
----~--~~--~~~----------_+--~L-------+_~~--~--~~~T
----~--~~----~~----------~----L-------._~r-------~-oAGN~

AGNIlF
C.DAC

..----+-----------+--1DECOD

PROM

- - - - -oPROG

14-BIT DAC REGISTER

~-----oA1

REGISTER

Ao

CS

.-------------+-~~_+_r-----iA~~

t---------O WR

00·,·····07

De • • • • 0,3
BD004101

Figure 2: ICL7134 Functional Diagram

ELECTRICAL CHARACTERISTICS (v+ = 5V, VREF = 10V, TA = 25°C unless otherwise specified.)
LIMITS
SYMBOL

PARAMETER

TEST CONDITIONS

TYP

MAX

14

Resolution
Non-Linearity

MIN

IJ
IK

Bits

0.003

% FSR
% FSR
% FSR

2

ppm/"C

Test Figure 4

0.012

(Notes 1 and ·2)

0.006

IL

Non-Linearity Temperature Coefficient (Note 3)

Operating Temperature Range

6-110
Note: All typical values have been guaranteed by characterization and are not tested.

UNIT

1

ICL7134

n
I'"

ELECTRICAL CHARACTERISTICS (CO NT.)

Col

.....

LIMITS
PARAMETER

SYMBOL

TEST CONDITIONS

UNIT
MIN

Gain Error

TYP

Test Figure 4
(Notes 1 and 2)

I J
IK

/L
'Gain Error Temperature Coefficient (Note 3)
Monotonicity
(Note 3)

PSRR

ZREF

Reference Input Resistance
Output Capacitance

Bits
Bits

IL

14

Bits
10

TA= +25°C
Operating Temperature Range

50

TA- + 25°C, tJ.V+ -±10%

10

IICL7134U
IICL7134B

VREF - ± 10V, 2kHz Sinewave
VRFl - VRFM (Unipolar Mode)
DAC Register = All O's
DAC Register = All l' s

ppm IV
IJS

JNp.p

4.0

10

kn

160

pF

235
7

I,in

Logic Input Current

Clin
V+

Logic Input Capacitance

(Note 3)

Supply Voltage Range (Note 4)

Functional Operation

1+

Supply Current
Long Term Stability

(Excluding Ladder)

1.0

1000 Hours, + 125°C (Note 3)

10

1.
2.
3.
4.

100
150

1

Equivalent Johnson Res.

High State Input

nA

250
500

Operating Temperature Range
Operating Temperature Range
0"; VIN"; V+

NOTES:

% FSR
ppm/oC

8

13

Output Noise
Low State Input

VINl
VINH

0.006
12

Operating Temperature Range

COUT

% FSR
% FSR

I J

Power Supply Rejection
Output Current Settling Time
Feedthrough Error

0.024
0.012

IK
lOUT Leakage Current

IOlK

2

MAX

kn
0.8

V
V

1.0

p.A

2.4
15
3.5

pF
6.0

V

2.5

mA
ppm/month

Full-Scale Range (FSR) is 10V for unipolar mode, 20V (± 10V) for bipolar mode.
USing internal feedback and reference inverting resistors.
Guaranteed by design, not production tested.
Full scale tested to 0.040% FSR.

AC CHARACTERISTICS
SYMBOL

(V + = 5V, see Timing Diagram)

PARAMETER

tAWs
tAWh
tCWs
tCWh

IWR
tOWs
tOWh

TEST CONDITIONS

MIN

TYP

MAX

Address·WRite Set-Up Time (Min)
Address-WRite Hold Time (Min)

(Note 3)

0

Chip Select·WRite Set·Up Time (Min)

(Note 3)

Chip Select·WRite Hold Time (Min)
WRite Pulse Width Low (Min)
Data-WRite Set·Up Time (Min)

(Note 3)

0
0

Data-WRite Hold Time (Min)

(Note 3)

200
200
0

UNIT

100

ns

DEFINITION OF TERMS
Ao.A1

~

....

transfer function from a straight line function between
endpoints. Normally expressed as a percentage of full scale
range. For a multiplying DAC, this should hold true over the
entire VREF range.

1

ADDRESS VALID, STABLE

.....-r--J .

1---..... -

Ci

I--tcw.

NONLINEARITY: Error contributed by deviation of the DAC

!---tWR

!---+-Icwb·

RESOLUTION: Value of the LSB. For example, a unipolar

\iii

./:::..'-DNDATA

DATA VALID

converter with n bits has a resolution of (2- n) (VREF). A

.1-.:....

bipolar converter of n bits has a resolution of [2 - (n - l)j
[VREFj, Resolution in no way implies linearity,

~

SETTLING TIME: Time required for the output function of
the DAC to settle to within 112 LSB for a given digital input
stimulus, i.e., 0 to full-scale.

WF012601

Figure 3: Timing Diagram

..

GAIN: Ratio of the DAC's operational amplifier output
voltage to the nominal input voltage value.
6-111
Note: All typical values have been guaranteed by characterization and are not tested.

ICL7134
FEEDTHROUGH ERROR: Error caused by capacitive coupling from VREF to output. with all switches OFF.

Table 1: Pin Descriptions
PIN

DESCRIPTION

SYMBOL

PIN

DESCRIPTION

SYMBOL

1

~

Chip Select (active low).
Enables register write.

17

PROG

Used for programming only. Tie to +5V for
normal operation.

2

WR'

WRite. (active J2.w). Writes in register.
Equivalent to CS.

18

VRFL

VREF for lower bits.

19

R,NV

Summing node for reference inverting
amplifier.

3
4
5
6

Do

Bit 0

01

Bit 1

20

VRFM

VREF for MSB only (bipolar).

02

Bit 2

21

RFB

03

Bit 3

Feedback resistor for voltage output
applications.

7

04

Bit 4
B~

Least significant

~5
06

5

Input

9

Bit 6

Data

10

07

Bit 7

11

08

Bit 8

8

12

09

Bit 9

13

010

Bit 10

14

011

Bit 11

15

012

Bit 12

16

013

Bit 13

Bits
(High

22

DGND

Digital GrouND return.

23

AGNDF

Analog GrouND force lines..Use to carry
current from internal Analog GrouND
connections. Tied internally to AGNDs.

24

AGNDs

Analog GrouND sense line. Reference point
for external circuitry. Pin should carry
minimal current; tied internally to AGNDF.

25

lOUT
V+

Current output pin.

26
27

A1

Address 1

28

Ao

Address 0

= True)

Most significant.

8IT1(MS8)

voltage.

"..1------...,

D"
1....81T
BINARY
COUNTER

Pos~ive

lOUT

I.,...
(LSB)

ICL7134U

Do

'01<0

0.001%

'M.

Co
CLOCf1I\-

LINEARITY
ERROR

VREF

16-BIT
REFERENCE

x,oo

'Ok.

0.001%

DAC

TC021601

Figure 4: Non-Linearity Test Circuit

6-112
Note: All typical values have been guaranteed by characterization and are not tested.

l

Control register lines

ICL7134
UNGROUNDED

+sv

StNEWAVE
GENERATOR
4OHz2Vp-p
..0

~.+~

(ADJUSTFO"
"fRROR .. OVoc)

----- 400k for effective input offset less than 25IlV).

These input data pins are also ysed to program the
PROM. under control of the PROG ,pin. This is done in
manufacturing, and for normal read-oniy use the PROG pin
should be tied to V + (+ 5V).

Table 2: Data Loading Controls
CONTROL lIP
Ao

A1

cs WR

ICL7134 OPERATION

X

X

X

1

X

X

1

X

0

0

0

0

load all registers from data bus.

0

1

0

0

load lS register. from data. bus.

1

0

0

0

load MS register from data bus.

0

load DAC register from MS'an,d
lS register.

1

1

0

No operation, device not selected.

Note: Data is latched on LO-HI transition of either

.

TAUE OIP NQQE

~;.~,---'\r-~IOUT

'---l---I---/'/

RE~::NCE

WR" or CS.

VJlEf IN - - - - - ,
AF024901

Figure 9: Eliminating Ground Loops
'0

RESTOF
LA"'A

The reference inverting amplifier used in the bipolar
mode circuit must also be selected carefully.. If 14-bit
accuracy is desired without adjustment, low input bias
current (less than 1nA), low offset voltage (less than 50IlY),
and high gain (greater than 400k) are recommended. If a
fixed reference voltage is used, the gain requirement can be
relaxed. For highest accuracy (better than 13 bits), an
additional op-amp may be needed to correct for IR drop on
the Analog GrouND line (op-amp A2 in Figure .11).This opamp should be selected for low bias current (less than 2nA)
and low offset voltage (less than 501lY).

AF024801.

Figure 8; Bipolar Operation, with
Inverted VREF to .MSB

6-114

Note: All typical values have been guaranteed by characterization and are not tested.'

ICL7134
The op-amp requirements can be readily met by use of
an ICL7650 chopper stabilized device. For faster settling
time, an HA26XX can be used with an ICL7650 providing
automatic offset null (see A053 for details).
The output amplifier's non-inverting input should be tied
directly to AGNDS. A bias current compensation resistor is
of limited use since the output impedance at the summing
node depends on the code being converted in an unpredictable way. If gain adjustment is required, low tempco
(approximately 50ppm/°C) resistors or trim-pots should be
selected.

V... ' N -_ _~_--,

'F8f2"-'-~--------,
'OUT

f"25"--+_-I

DATA
INPUTS

ICL7134U

POWER SUPPLIES
The V + (pin 25) power supply should have a low noise
level, and no transients exceeding 7 volts. Note that the
absolute maximum digital input voltage allowed is V + ,
which therefore must be applied before digital inputs are
allowed to go high. Unused digital inputs must be connect,ed to GND or V+ for proper operation.

Unipolar Binary Operation (ICL7134U)
D5014oo1

The circuit configuration for unipolar mode operation
(lCL7134U) is shown in Figure 10. With positive and
negative VREF values the circuit is capable of two-quadrant
.multiplication. The "digital input code/analog output value"
table for unipolar mode is given in Table 3. The Schottky
diode (HP5082-2811 or equivalent) protects lOUT from
negative excursions which could damage the device, and is
only necessary with certain high speed amplifiers. For
applications where the output reference ground point is
established somewhere other than at the DAC, the circuit of
Figure 10 can be used. Here, op-amp A2. removes the slight
error due to IR voltage drop between the internal Analog
GrouND node and the external ground connection. For 13bit or lower accuracy, omit A2 and connect AGNDF and
AGNDS directly to ground through as Iowa resistance as
possible.

Figure 11: Unipolar Binary Operation
with Forced Ground
Table 3: Code Table - Unipolar Binary
Operation
DIGITAL INPUT

11111111111111
1 0 0 0 0 000 000 0 0 1
1 0 0 0 0 0 0 0 0.0 0.0 0 0
01111111111111
o0 0 0 0 00 00 0 0 0 0 1
o0 0 0 0 00 0 00 0 0 0 0

ANALOG OUTPUT

-VREF(l _1/214)
- VREF(l /2 + 1/214)
-VREF/2
-VREF(1/2 _1/214)
-VREF(1/214)
0

ZERO OFFSET ADJUSTMENT
1.

Connect all data inputs and WR, CS, Ao and A1 to
DGND.
.

2.

Adjust offset zero-adjust trim-pot of the operational
amplifier A2, if used, for a maximum of OV ±50/-IV at
AGNDS·
Adjust the offset zero-adjust trim-pot of the output
op-amp, A1, for a maximum of OV ±50/-IV at VOUT.

VREF IN - - -......- - - - - ,

3.
DATA
INPUTS

GAIN ADJUSTMENT (OPTIONAL)
1.

050'13901-

Connect all data inputs to V + , connect WR,
and A1 to DGND.

CS, Ao

2.

Monitor VOUT for a -VREF (1 _1(214) reading.

3.

To decrease VOUT, connect a series resistor of
lOOn or less between the reference vcil!age and the
VRFM and VRFL terminals (pins 20 and 18).

4.

To increase VOUT, connect a series resistor of
lOOn or less between A1 output and the RFS
terminal (pin 21).
.

Figure 10: Unipolar Binary, Two-Quadrant
Multiplying Circuit

6-:-115
Note: All typical values have been guaranteed by characterization and are nol lesled.

IID~DIl

" ICL7f34·

a

VREFIN
18
YRFl
RINVl

19
RlNV
RINV2

20
YRFM Y+

16. D13(MSB)
15

0

RFB

21

D12

loUT

DATA

ICL7134B

INPUTS

0
+5Y

3
Do(LSB)
17·
PROG

08014101

Figure 12: Bipolar (2'5 Complement), Four-Quadrant Multiplying Circuit

Bipolar (2' s .Complement) Operation
(ICL7134B)

2.

The circuit configuration for bipolar mode Glperation
(ICL7134B) is shown in Figure 12. Using 2's complement
digital input codes and positive and negative reference
voltage values, four-quadrant multiplication is obtained. The
"digital input code/analog output value" table for bipolar
mode is given in Table 4. Amplifier A3, together with internal
resistors RINV1 and RINV2, forms a simple voltage inverter
circuit. The MSB ladder leg sees a reference input of
approximately :"'VREF, so the MSB's weight is reversed
from the polarity of the other bits. In addition, the
ICL7134B's feedback resistance is switched to 2R under
PROM control, so that the bipolar output range is + VREF to
-VREF (1 - 1J213). Again, the grounding arrangement of
Figure 11 can be used, if necessary.

3.

4.
5.

GAIN ADJUSTMENT (OPTIONAL)
1.
2.
3.
4.

Table 4: Code Table - Bipolar
(2'8 Complement) Operation
DIGITAL INPUT

01111'111111111
00000000000001
00000000000000
11111111111111
1 000 0 0 0 0 0 0 0 0 0 1
10000000000000

5.

ANALOG OUTPUT

Connect WR, CS, Ao and A1 to OGNO.
Connect DO, 01 ... 012 to V+, 013 (MSB) to OGNO.
Monitor Your for a -VREF (1- ""2 13) reading.
To increase Your, connect a series resistor of
200n or less between the A1 output and the RFB
terminal (pin 21).
To decrease Your, connect a series resistor of
1oon or less between the reference voltage and the
VRFL terminal (pin 18).

Processor Interfacing

-VREF(1-1/2 13)
-VREF(1/2 13)
0
VREF(1/2 13)
VREF(l _1/2 13)
VREF

The ease of interfacing to a processor can be seen from
Figure 14, which shows the ICL7134 connected to an 8035
or any other processor such as an 8049. The data bus
feeds into both register inputs; three port lines, in combination with the WR line, control the byte-wide loading into
these registers and then the OAC register. A complete OAC
set-up requires 4 write instructions to the port, to set up the
address and CS lines, and 3 external data transfers, one a
dummy for the final transfer to the OAC register.

OFFSET ADJUSTMENT
1.

Adjust the offset zero-adjust trim-pot of the
operational amplifier A2, if used, for a maximum of
OV ±50j.N at AGNOS.
Set data to 00000 .... 00. Adjust the offset zeroadjust trim-pot of the output op-amp A1, for a
maximum of OV ±50j.lV at Your.
Connect 013 (MSB) data input to v+.
Adjust the offset zero-adjust trim-pot of op-amp A3
for a maximum of OV ±50j.lV at the RINV terminal
(pin 19).

Connect all data inputs and WR, CS, Ao and Al to
OGNO.
6-116

Note: All typical values have been guaranteed by characterization and are not tested.

ICL7134
+5V

OV

+5V
P1o..17

} OTHER
I/O

P"

.,.

IM:;:aDBo

Do

P2CI-24

P,.
P,.
IM80C35

OV

CS

8050
8748

ETC.
0,
08,

WR

ICL7134

0,
0,

AGNDF
.".

0"

WR

LOO05401

Figure 14: Interface to 8080 System
lDO05301

Figure 13: ICL7134 Interface to 8048 System

Aa- 15 t-_ _ _ _ _ _-'-'-..,. \ . . _ - - - - - - - - - - - - - - - - - - ,

8212

LOOO5501

Figure 15: 8085 System Interface
A similar arrangement can be used with an 8080A, 8228,
and 8224 chip set. Figure 14 shows the circuit, which can
be arranged as a memory-mapped interface (using MEMW)
or as an I/O-mapped interface (using I/O WRITE). See
A020 and R005 for discussions of the relative merits of
memory-mapped versus I/O-mapped interfacing, as well as
some other ideas on interfacing with 8080 processors. The
8085 processor has a very similar interface, except that the
control lines available are slightly different, as shown in

Figure 15. The decoding of the 10/M line, which controls
memory-mapped or I/O-mapped operation, is arbitrary, and
can be omitted if not necessary. Neither the MC680X nor
R650X processor families offer specific I/O operations.
Rgure 16 shows a suitable interface to either of these
systems, using a direct connection. Several other decoding
options can be used, depending on the other control signals
generated in the system. Note that the R650X family does
not require VMA to be decoded with the address lines.

6-117
Note: All typical values have been guaranteed by characterization and are not tested.

ICL7134

ICL7134

MC·680X
MCS·650X

OPTIONAL
GATE
(SEE TEXT)
lOOO5BOI
lDO05601

Figure 17: Avoiding Digital Feedthrough
in an 8048 to ICL71'34 Interface

Figure 16: R650X and MC680X
Families' Interface to ICL7134

INTERSIL
ANALOG
CIRCUIT

r---A
'---V

1M80C48

INTEL

ICL7134

8080
808S

ETC.

LD00590t

Figure 18: ICL7134 to 8048/80/85 Interface with Low Feedthrough

Digital Feedthrough

allow only 8 bits to be updated at anyone time, but a little
ingenuity will avoid difficulties with DAC steps that would
result from partial updates. The problem can be solved for
the 8048 family by tying the 14 port lines to the data input
lines, with CS, Ao and A1 held low, and using only the WR
line to enter the data into the DAC (as shown in Figure 17).
WR is well separated from the analog lines on the ICL7134,
and is usually not a very active line in 8048 systems.
Additional "protection" can be achieved by gating the
processor WR line with another port line. The heavy use of
port lines can be alleviated by use of the IM82C43 port
expander. The same type of technique can be employed in
the 8080/85 systems by, using an' 8255 PIA (peripheral
Interface adapter) (Figure 18) and in the MC680X and
R650X systems by using an MC6820 (R6520) PIA.

All of the direct interfaces shown above can suffer from a
capacitive coupling problem. The '14 data pins,and 4
control pins, all tied to active lines on a microprocessor bus,
and in close proximity to the sensitive DAC circuitry, can
couple pseudo-random spikes into the analog output.
Careful board layout and shielding can minimize the problems (see PC layout), and clearly wire-wrap type sockets
should never be used. Nevertheless, the inherent capacitance of the package alone can lead to unacceptable digital
feedthrough in many cases. The only solution is to keep the
digital inpIJt lines as inactive as possiblf;l. One easy way to
do this is to use the peripheral interface circuitry available
with all the systems previously discussed. These generally

6-118
Note: All typical values have been guaranteed by characterization and are not tested.

n
r

ICL7134

........
Col

- v..

+ISV

~D?~sv

II

-

.... HP2800

.....

3IIcII

,r ~
-~rJ·

+

+

~

A3

... HP2800

~

+sv

22

~ Ci

~
~
~

18

19

OGNO VAL AlHv

24
20
VAUAGNDs

WR

25

louT

HA2805

II

MSB
,.,5 1413
12 " 10 9

I!:?

21

ICL7I34B

Ao
A,

23

PROG V + AGNIlF RF.

LSB
a 7 8 5 4 3

+

-15V

LSBL _

+5V -

+

~"~

OUT

SV
6IIOIl

LM311

r- +

~

-15V

~-

~

IN927A ~ ~

lMU
1300

~

-1SV
+sv--1!

,F

I-f-o

~f-o ~

~MS8

15 13 12 11 6 5 4 3

t Os. • • • • Qo CC 2 p----!.
AM25L03

S

0

CP

It-~

71

10

14 13 12 11 654
AM25L03

CP

.

0

i

71

10

T
rio-'

2IdI

5100

Iff '~"'E I

k"

1000p

HOLOIAUJi n.

.iT

"""'lr

II(N+I)

1 0 , · · · · · 0 , ~+5V

...

CC
2

~

SHORT
CYCLE
UNE

lN4!48

~

~.;;:.

.~
T
.iTP~

~

14

221J1i..l.-

"J;

l00pF

7

STATUS
D5014201

figure 19: Successive Approximation AID Converter
bits, 'where settling-time is most critical, than for the last 6
bits. The short-cycle line is shown tied to the 15th bit; if
fewer bits are required, it can be moved up accordingly. The
circuit will free-run if the HOLD/RUN input is held low, but
will stop after completing a conversion if the pin is high at
that time. A low-going pulse will restart it. The STATUS
output indicates when the device is operating, and the
falling edge indicates the availability of new data. A unipolar
version may be constructed by tying the MSB (0,3) on an
ICL7134U to pin 14 on the first AM25L03, deleting the
reference inversion amplifier A4, and tying VRFM to VRFL.

Successive Approximation AID Converters
Figure 19 shows an ICL7134B-based circuit for a bipolar
input high speed A/D converter, using two AM25L03s to
form a 14-bit successive approximation register. The comparator is a two-stage circuit with an HA2605 front-end
amplifier, used to reduce settling time problems at the
summing node (see A020). Careful offset-nulling of this
amplifier is needed, and if wide temperature range operation ,is desired, an auto-null circuit using an ICL7650is
probably advisable (see A053). The clock, using two
Schmitt trigger TTL gates, runs at a slower rate for the first 8

6-119

Note: All typical values have been guaranteed by characterization and are not tested.

:... ICL7134

...

..I

.'

S:!

...

Do
Il/Ii .....

...

eli

-

...

----

....

DIGITAl
INPUT

'LSO

ANALOG
G~ND

,_."

OUT

CS.WR

t

I
ANALOG
Q":ND

-::..- DaNO
AODliIESs

PL010001
PL009901

(a) Printed Circuit ~ide of Card
(Single Sided Board)

(b) Top Side with Component Placement

figure 20: Printed Circuit Board Layout (Bipolar Circuit, see figure 12)
A018 "Do's and DonI's of Applying AID Converters," by
Peter Bradshaw and Skip Osgood.
A020 "A Cookbook Approach to High Speed Data
Acquisition and Microprocessor Interfacing," by Ed
Sliger.
A021 "Power AID Converters Using the ICH8510," by
Dick Wilenken.
A030 "The ICL7104 - A Binary Output AID Converter for
Microprocessors," by Peter Bradshaw.
R005 "Interfacing Data Converters & Microprocessors,"
by Peter Bradshaw et ai, Electronics, Dec. 9, 1976.
Most of these are available in the Intersil Data Acquisition
Handbook, together with other material.

PC BOARD LAYOUT
Great care should be taken in the board layout to
minimize ground loop and similar "hidden resistor" problems, as well as to minimize digital signal feedthrough. A
suitable layout for the immediate vicinity of the ICL7134 is
shown in Figure 20, and may be used as a guide.

APPLICATION NOTES
Some applications bulletins that may be found useful are
listed here:
A016 "Selecting AID Converters," by Dave Fullagar.
A017 "The Integrating AID Converter," by Lee Evans.

6-120

Note: All typical values have been guaranteed by characterization and are not tested,

ICL7135
4 Y2-Digit BCD Output
AID Converter
GENERAL DESCRIPTION

FEATURES

The Intersil ICL7135 precision AID converter, with its
multiplexed BCD output and digit drivers, combines dualslope conversion reliability with ±1 in 20,000 count accuracy and is ideally suited for the visual display DVM/DPM
market. The 2.0000V full scale capability, auto-zero and
auto-polarity are combined with true r-Y-

05014301

(a)

(b)
Figure 6: Using an External Reference
UARTs or microprocessors. There are 5 negative going
STROBE pulses that occur in the center of each of the digit
drive pulses and occur once and only once for each
measurement cycle starting 101 pulses after the end of the
full measurement cycle. Digit 5 (MSD) goes high at the end
of the measurement cycle and stays on for 201 counts. In
the center of this digit pulse (to avoid race conditions
between changing BCD and digit drives) the first STROBE
pulse goes negative for Y2 clock pulse width. Similarly, after
digit 5, digit 4 goes high (for 200 clock pulses) and 100
pulses later the STROBE goes negative for the second
time. This continues through digit 1 (LSD) when the fifth and
last STROBE pulse is sent. The digit drive will continue to
scan (unless the previous signal was overrange) but no
additional STROBE pulses will be sent until a new measurement is available. .

Analog Common
Analog COMMON is used as the input low return during
auto-zero and de-integrate. If IN LO is different from analog
COMMON, a common mode voltage exists in the system
and is taken care of by the excellent CMRR of the
converter. However, in most applications IN LO will be set
at a fixed known voltage (power supply common for
instance). In this application, analog COMMON should be
tied to the same pOint, thus removing the common mode
voltage from the converter. The reference voltage is
referenced to analog COMMON.

Reference
The reference input must be generated as a positive
voltage with respect to COMMON, as shown in Figure 6.

DETAILED DESCRIPTION
Digital Section
Figure 7 shows the Digital Section of the 7135. The 7135
includes several pins which allow it to operate conveniently
in more sophisticated systems. These include:
Run/HOLD (Pin 25). When high (or open) the AID will freerun with equally spaced measurement cycles every 40,002
clock pulses. It taken low, the converter will continue the full
measurement cycle that it is doing and then hold this
reading as long as R/Ff is held low. A short positive pulse
(greater than 300ns) will now initiate a new measurement
cycle, beginning with between 1 and 10,001 counts of auto
zero. If the pulse occurs before the full measurement cycle
(40,002 counts) is completed, it will not be recognized and
the converter will simply complete the measurement it is
doing. An external indication that a full measurement cycle
has been completed is that the first strobe pulse (see
below) will occur 101 counts after the end of this cycle.
Thus, if Run/HOLD is low and has been low for at least 101
counts, the converter is holding and ready to start a new
measurement when pulsed high.
STROBE (Pin 26). This is a negative going output pulse that
aids in transferring. the BCD data to external latches,

y+
--~---

DIGITAL
GND

.

CLOCK
IN

RUNI
Hml)

OVER
RANGE

UNDER
RANGE

STiii5iE

BUSY

AF025101

Figure 7: Digital Section of the 7135
BUSY (Pin 21). BUSY goes high at the beginning of signal
integrate and stays high until the first clock pulse after zerocrossing (or after end of measurement.in the case of an
6-125

Note: All typical values have been guaranteed by charadterizati.on and are not tested.

ensures that the tolerance built-up will, not· saturate the
integrator swing (approx. 0.3 volt from either supply). For ±5
volt supplies and analog COMMON tied to supply ground, a
±3.5 to ±4 volt full· scale integrator swing is fine, and 0.47pF
is nominal. In general, the value of CINT is given by

overrange). The internal latches are enabled (i.e., loaded)
during the first clock pulse after busy and are latched at the
end of this clock pulse. The circuit automatically reverts to
auto-zero when not BUSY, so it may also be .considered a
(ZI + AZ) signal. A very simple means for transmitting the
data down a single wire pair from a remote location would
,be to AND BUSY with clock. and subtract 10,001 counts
from the number of pulses received - as mentioned
previously there is one "NO-count" pulse in each reference
integrate cycle.
OVER-RANGE (Pin 27). This pin gOEls positive when the
input signal exceeds the range (20,000) of the converter.
The output F/F is set at the end of BUSY and is reset to
zero at the beginning of Reference integrate in the next
measurement cycle.
UNDER-RANGE (Pin 28). This pin goes positive when the
reading is 9% of range or less. The output F/F is set at the
end of BUSY (if the new reading is 1800 or less) and is reset
at the beginning of signal integrate of the next reading.
POLARITY (Pin 23). This pin is positive for a positive input
signal. It is valid even for a zero reading. In other words,
+ 0000 means the signal is positive but less than the least
significant bit. The converter can be,used as a null detector
by forcing equal frequency of ( + ) and ( - ) readings. The null
at this point should be 'Iess than 0.1 LSB. This output
becomes,valid at the beginning of reference integrate and
remains correct until it is re-validated for the next'measurement.
Digit Dr!ves (Plris 12, 17, 18, 19 and 20). Each digit drive is
a positive going signal fhat lasts for 200 clock pulses. The
scansEiquence is D5 (MSD), D4, D3, D2 and D1 (LSD). All
five digits are scanned and this scan is continuous unless
an over-range occurs. Then all digit drives are blanked from
the end of the strobe sequence until 'the beginning of
Reference Integrate when D5 will start the scan "again. This
can give a blinking display as a visual indication of overrange.
BCD (Pins 13, 14, 15 and 16). The Binary coded Decimal
bits Bs, B4, B2 and B1 are positive logic signals that go on
simultaneously with the digit driver signal.

CINT=(

(10,000) (clock period) (20/lA)
integrator output voltage swing
A very important characteristic of the integrating capacitor is that it has low dielectric absorption to prevent roll-over
or ratiometric errors. A good test for dielectric absorption is
to use the capacitor with the input tied to the reference.
This ratiometric condition should read half scale 0.9999,
and any deviation is probably due to dielectric absorption.
Polypropylene capacitors give undetectable errors at reasonable cost. Polystyrene and polycarbonate capaCitors
may also be used 'in less critical applications.

INTEGRATOR.

OUTP\IT

If.4Y,().I ~
~

INTEGRATE
REFERENC£J
20.001

1~

COUNTS CO

COUNTS MAX.

FULl. MEASUREMENT CYCLE

4O,Q02COUNTS

8USY~

WHEN """LIC....L~ iii

FOR

o~:11~~rL...J""L..JL- D,
~D.

..JL....JL-Il..D:!
---IL-1L-..J D;

COMPONENT VALUE SELECTION

. --I1-...IL-.D',

~~=-~

For optimum performance of the analog section, care
must be taken in the selection of values for the integrator
capaCitor and resistor, auto-zero capacitor, reference voltage, and conversion rate. These values must be chosen to
suit the particular application.

'FIRST Os OF AZ AND
REF INT ONE COUNT LONGER

mRIII! .. II I
r-AUTOZERO

SCANI,

SIGNAL INTEGRATE

FORO~~ANGEnD'

Integrating Resistor

J1~D.~

The integrating resistor is determined by the full scale
input voltage and the output current of the buffer used to
charge the integrator capacitor. Both the buffer amplifier
and the integrator have.a.class A output stage with 100/lA
'of quiescent current. They can supply 20/lA of drive current
with negligible' non-linearity. Values of 5 to 40pA give good
results, with a nominal. of 20/lA, and the exact value of
.integrating resistor may be chosen by
RINT =

[10,0'00 x clock period] x liNT
.
)
integrator output voltage swing

.

,

________ •____-tJ

-11~D:!~

_____ ____

.--n=D:!~

~

__

~

____

~

~~

~~---+--~
WF01?701

.. Figure 8: Timing Diagram for Outputs

full scale voltage
20/lA'

Auto-Zero'and Reference CapaCitor

Integrating CapaCitor

The size of the auto-zero'capacitor has some influence
on the noise of the system, a large capacitor giving less
noise. The reference capaCitor should be large enough

The product of integrating resistor and capacitor Should
be .selected to give the' maximum. voltage, swing which
6-12~

Note: All typical values have been guarant!l 7V), the COMMON voltage will have a low voltage coefficient
(0.001 %/%), low output impedance ("",35n), and a temperature coefficient typically less than BOppml"C.

DE·INTEGRATE PHASE
The next phase is de-integrate, or reference integrate.
Input low is internally connected to analog COMMON and
input high is .connected across the previously charged
reference capacitor. Circuitry within the chip ensures that

6-135
Note: All typical values have been guaranteed by characterization and are not tested.

I
'"

=
ICL7136··
......
2

v,

v'

v'
1.2 VOLT
REFERENCE
(INTERSll
ICL8C!6"I

6.' VOLT
ZENER

liZ
v(8)

(b)
08014501

OS014601

Figure 6: Using an External Reference
The limitations of the on-Chip reference should also be
recognized, however. The reference temperature coefficient (TC) can c:ause some degradation in performance.
Temperature changes. of 2°C to 8°C, typical for instruments,
can give a scale factor error of a count or more. Also, the
COMMON voltage will have a poor voltage coefficient when
the total supply voltage is less than that which will cause the
zener to regulate ( < 7V). These problems are eliminated if
an external reference is used, as shown in Figure 6.
Analog COMMON is also used as the input low return
during auto-zero and de-integrate. If IN LO is different from
analog COMMON, a common-mode voltage exists in the
.system and is taken care of by the excellent CMRR of the
converter. However, in some applications IN LO will be set
at a fixed known voltage (power supply common for
instance). In this application, analog COMMON should be
tied to the same pOint, thus removing the common-mode
voltage from the converter. The same holds true for the
reference voltage. If the reference can be conveniently
referred to analog COMMON, it should be since this
removes the common-mode voltage from the reference
system.
Within the IC, analog COMMON is tied to an N channel
FET which can sink 3mA or more of current to hold the
voltage 3.0V below the positive supply (when a load is trying
to pull the common line positive). However, there is only
1pA of source current,so COMMON may easily be tied to a
more negative voltage, thus overriding the internal reference.
..

TEST
The TEST pin serves two functions. It is coupled to the
internally generated digital supply through a 500n resistor.
Thus, it can be used as the negative supply for external
segment drivers such as for decimal points or any other
presentation the user may want to include on the LCD
display. Figures 7 and 8 show such an application. No more
than a 1mA load should be applied.
The second function is a "lamp test." When TEST is
pulled high (to V +) all segments will be turned on and the
display should read -1888. The TEST pin will sink about
10mA under these conditions .

Caution: In the lamp test mode, the segments have a
constant DC voltage (no square-wave). This may burn
the LCD display if maintained for extended periods.

TOLCO
DECIMAl

POINTS

TC022001

Figure 8: Exclusive "OR" Gate for
Decimal Point Drive
v,

DETAILED DESCRIPTION

1MO

ICL7136

BPI-'2""1-.-11+--

(Digital Sectionl
Figure 9 shows the digital section for the 7136. An
internal digital ground is generated from a 6V Zener diode
and a large P channel source follower. This supply is made
stiff to absorb the relatively large capacitive currents when
the backplane (BP) voltage is switched. The BP frequency
is the clock frequency divided by 800. For three readings/
second this is a 60Hz square-wave with a nominal amplitude of 5V. The segments are driven at the same frequency
and amplitude and are in phase with BP when OFF, but out
of phase when ON. In all cases negligible DC voltage exists
across the segments. The polarity indication is "ON" for

TO LCD
DECIMAL POINT

:~J7~SIL

TEST 1,3=7-I---"'...J TO LCD

BACKPLANE

09014701

Figure 7: Simple Inverter for Fixed
Decimal Point
6-136

Note: All typical values have been guaranteed by characterization and are not tested ..

ICL7136
negative analog inputs. If IN LO and IN HI are reversed, this
indication can be reversed also, if desired.

DISPLAY FONT

0123'-:'5:5:8'3
--------------------.---.--------.--.---.-----~------~~H+~~---·~r+·++-I+--+~-~~~·~~----=~·~~~~n~

*~-

One _ _

for-,.

------------------------&""'---osc

O8CI

osc>

AF025501

Figure 9: Digital Section

System Timing

L

Figure 10 shows the clock oscillator provided in the 7136.
Three basic clocking arrangements can be used:
1. An external oscillator connected to pin 40.
2. A crystal between pins 39 and 40.
3. An RC oscillator using all three pins.
The oscillator frequency is divided by fbur before it clocks
the decade counters. It is then further divided to form the
four convert-cycle phases. These are Signal integrate (1000
counts), reference de-integrate (0 counts to 2000 counts),
zero integrator (11 counts to 140 counts') and auto-zero
(910 counts to 2900 counts). For signals less than fullscale, auto-zero gets the unused portion of reference deintegrate and zero integrator. This makes a complete
measure cycle of 4000 (16,000 clock pulses) independent

...J

TC022101

Figure 10: Clock Circuits

• After an overranged conversion of more than 2060 counts, the zero integrator phase will last 740 counts, and auto-zero will last 260 counts.
6-137
Note: All typical values have been guaranteed by characterization. and are not tested.

of input voltage. For three readings/second, an oscillator
frequency of 48kHz would be used.
To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple. of the 60Hz ~eriod.
Oscillator frequencies of 60kHz, 48kHz, 40kHz, 33-V3kHz,
etc. should be selected. For. 50Hz rejection, oscillator
frequencies of 662t3.kK~;-'I~pkHz, 40kHz, etc. would be
suitable. Note that 4()kl::(Z:(~i? readings/second) will r~je¢t
both 50Hz and 60Hz (ills04QOHz ai1d 440Hz). See also
A052.
.
.

respectively. However, in many applications where the AID
is connected to a transducer, there will exist scale factor
other than unity between the input voltage and the digital
reading. For instance, in a weighing system, the designer
might like to liave a full-scale reading when the voltage from
the transducer is 0.682V. Instead of dividing the input down
. to 200.0mV, the designer should use the input voltage
directly and select VREF = 0.341V. A suitable value for the
integrating resistor would be 330kn. This makes the system
'slightly quieter and also avoids the necessity of a divider
network on the input. Another advantage of this system
occurs when a digital reading of zero is desired for VIN O.
Temperature and weighing systems with a variable tare are
examples. This offset reading can be conveniently generated by connecting the voltage transducer between IN HI and
COMMON and the variable (or fixed) offset voltage between COMMON and IN LO.

a

COMPONENT VALlJE:'SELECTION-

*'

(See also A052)

Integrating Resistor
Both the buffer amplifier and the integrator have a class A
output stage with 6pA of quiescehtcurrent. They can supply
-1 pA of drive current with negligible non-linearity. The
integrating resistor should be large enough to remain in this
very linear region over the input voltage range, but small
enough that undue leakage requirements are not placed on
the PC board. For 2.V full-scale, 1.8Mn is near optimum,
and similarly 180kn for a .200.0mV scale.

TYPICAL APPLICATIONS
The 7136 may be used in a wide variety of configurations.
The circuits which follow show some of the possibilities, and
serve to illustrate the exceptional versatility of these AID
converters.

Integrating CapaCitor .
The integrating capaCitor should be selected to give the
maximum voltage swing that ensures tolerance build-up will
not saturate the integrator swing (approx. 0.3V from either
supply). When the analog COMMON is used as a reference,
a nomil)al ±2V full-scale integrator swing is fine. For three
readings/second (48kHz clock) nominal values for CINT are
0.047j.1F, for 1 reading/second (16kHz) 0.15j.1F. Of course,
if different oscillator frequencies are used, these values
should be changed in inverse proportion to maintain the
same output swing.
The integrating capaCitor should have low .dielectric
absorption to prevent roll-over errors. While other types
may be adequate for this application, polypropylene capacitors give undetectable errors at reasonable cost.

,OSC1

..

To pin 1

11Ok"

osea
ose3

Set Vre' "" 100.OmV

TEST·

/

SOpF

REF HI
REFLO
"C REF

O.1J.!F

C REF

....0

1OkO

COMMON

1Ml!

IN HI

0.011'F

IN LO

0.47"F

A-2

11Ok0

BUFF

The size of the auto-zero capacitor has some influence
on the noise of the system. For 200mV full-scale where
noise is very important, a 0.47j.1F capacitor is recommended. The ZI phase allows a large auto-zero· capaCitor to
be used without causing the hysteresis or overrange
hangover problems that can occur with the ICL7126 or
ICL7106 (see A032).

=

tV

INT
V·
G,
C3
A3
G3
BP

Auto-Zero Capacitor

IN

O.047J.
Ol

.....
EO

POL

n

"'H'

IHLO
.."
BUFF
'NT

v-

...C,

..

'"

B.

c ......
or 74C10

CD4077

CD012001

Figure 18: Circuit for Developing Underrange and Overrange Signals from 7136 Outputs

To pin t
40

leal. '1ICtor .dlu"

(VNf .,. 100mV tor AC to Rill)

ACIN

I'
CD011101

Figure 19: AC to DC Converter with 7136
Test is used as a common-mode reference level to ensure compatibility with most op amps.
A052 "Tips for USing Single-Chip 3Y2-Digit AID
Converters," by Dan Watson.

APPLICATION NOTES
A016 "Selecting AID Converters," by David Fullagar.
A017 "The Integrating AID Converter," by Lee Evans.
A018 "Do's and Dont's of Applying AID Converters," by
Peter Bradshaw and Skip Osgood.
A019 "4Y2-Digit Panel Meter Demonstratorl
Instrumentation Boards," by Michael Dufort.
A023 "Low Cost Digital Panel Meter Designs," by David
Fullagar and Michael Dufort.
A032 "Understanding the Auto-Zero and Common-Mode
Behavior of the ICL7106/7/9 Family," by Peter
Bradshaw.
A046 "Building a Battery-Operated Auto Ranging DVM
with the ICL7106," by Larry Goff.
A047 "Games People Play with Intersil's AID
Converters," edited by Peter Bradshaw.

7136 EVALUATION KIT
After purchasing a sample of the 7136, the majority of
users will want to build a simple voltmeter. The parts can
then be evaluated against the data sheet specifications,
and tried out in the intended application.
To facilitate evaluation of this unique circuit, Intersil is
offering a kit which contains all the necessary components
to build a 3Y2-digit panel meter. With the ICL7136EV/Kit
and the small number of additional components required,
an engineer or technician can have the system "up and
running" in about half an hour. The kit contains a circuit
board, a display (LCD), passive components, and miscellaneous hardware.

6-141

Note: All typical values have been guaranteed by characterization and are not tested.

ICL7137

3 ~2~DigitLED Low Power
Single-Chip AID Converter
GENERAL DESCRIPTION

FEATURES

The Intersil ICL7137 is a high performance, very low
power 3Y2-digit AID converter. All the necessary active
devices are contained on. a single CMOS IC, including
seven-segment decoders, display drivers, reference, and
clock. The 7137 is designed to interface with a light emitting
diode (LED) display. The supply current (exclusive of
. display) is under 200/lA, ideally suited for battery operation.
The 7137 brings together an unprecedented combination
. of high accuracy, versatility, and true economy. The device
features auto-zero to less than 10/lV, zero drift of less th.an
1/lV
input bias current of 10pA max., and rollover error
of less than one .count. The versatility of true differential
input and reference is useful in all systems, but gives the
deSigner an uncommon advantage when measuring load
cells, strain gauges and other bridge-type transducers. And
finally the true economy of the ICL7137 allows a high
performance panel meter to be built with the addition of only
10 passive components and a display.
The ICL7137 is an improved version of the ICL7107,
eliminating the overrange hangover and hysteresis effects,
and should be used in its place in all applications, changing
only the passive component values.

•
•
•
•
•
•
•
•

rc,

•
•
•
•

First-Reading Recovery From Overrange allows
Immediate "OHMS" Measurement
Guaranteed Zero Reading for OV Input
True Polarity at Zero for Precise Null Detection
1pA Typical Input Current
True Differential Input and Reference
Direct LED Display Drive - No External
Components Required
Pin Compatible With The ICL7107
Low Noise -15/lVp-p Without Hysteresis or
Overrange Hangover
On-Chip Clock and Reference
Improved Rejection of Voltage On COMMON Pin
No Additional Active Circuits Required
Evaluation Kit Available ICL7137EV/Kit

ORDERING INFORMATION*
PART NUMBER

TEMPERATURE RANGE

PACKAGE

ICL7137CJL

O·C to +70·C

CERDIP

ICL7137CDL

. O·C to +70·C

40·Pin Ceramic

ICL7137CPL

O·C to +70·C

40-Pin Plastic

ICL7137RCPL

O·C to +70·C

40-Pin Plastic

ICL7137EVIKIT

EVALUATION KIT

-

-

V+

OSCl

en

81

TEST

-

Gl

C+AEF

El
02
C2
82

INHI
INLO

A2
F2
E2

A-Z
BUff
INT

.:. r··~!

~l!~
1
~
_

~

I

';i

I ~~

~

~t:~

(1000) A84

..... ~L!!..._~_~_-_-_-_-=._c.:_:.._-_-_4.;::_=_=_=_=_=-_-_-.J._____________ _

g~~
:::~~
C-"EF
COMMON

~; (TENS)

~~\i

G31 i:

(MIN~~'-liI'----....i.!P DIG GND
CD012101

v·
80004401

. Figure 2: Pin Configuration*
(Outline dw~s Pl, Jl, Dl)

Figure 1: Functional Diagram

6-142
Note: All typical values have been guaranteed by characterization and are not tested.

301669-{)02

ICL7137
ABSOLUTE MAXIMUM RATINGS
Supply Voltage V + .......................................... + 6V
V- ........................................... -9V
Analog Input Voltage (either input)(Note 1) .... V + to VReference Input Voltage (either input) .......... V+ to VClock Input ...........................................GND to V +

Power Dissipation (Note 2)
Ceramic Package .............................. 1000mW
Plastic Package .................................. 800mW
Operating Temperature ........................ O°C to + 70°C
Storage Temperature ..................... - 65°C to + 150°C
Lead Temperature (Soldering, 10sec) ................. 300°C

Note 1: Input voltages may exceed the supply voltages, provided the input current is limited to ± 1OOIlA.
Note 2: Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional

operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (Note 3)
PARAMETER

TEST CONDITIONS

Zero Input Reading

VIN = O.OV
Full-Scale = 200.0mV

Ratiometric Reading

VIN

Roll-Over Error (Difference in
reading for equal positive and
negative reading near full-scale)

- VIN

Linearity (Max. deviation from
best straight line fit)

Full-scale = 200mV
or Full-Scale = 2.000V

Common-Mode Rejection Ratio
(Note 4)

VCM = ±1V, VIN = OV
Full·Scale = 200.0mV

Noise (Pk-Pk value not exceeded
95% of time)

VIN

Leakage Current

@

Input

Zero Reading Drift
Scale Factor Temperature
Coefficient
V + Supply Current (Does not
Include LED current)

= VREF.

VREF

= + VIN

= OV,

= 100mV

"" 200.0mV

MIN

TYP

MAX

UNIT

-000.0

±OOO.O

+ 000.0

Digital Reading

998

999/1000

1000

Digital Reading

-1

±0.2

+1

Counts

-1

±0.02

+1"

Counts

30

Full-Scale = 200.0mV

15

= OV
VIN = OV, O°C < T A < + 70°C
VIN = 199.0mV, O°C < T A < + 70°C
VIN

IlV

1

10

pA

0.2

1

IlV/·C

1

5

ppml"C

70

200

/lA

3.2

V

(Ext. Ref. Oppm/°C)
VIN

= OV

(Note 5)

V - Supply current

40

Analog COMMON Voltage (With
respect to positive supply)

250kn between Common and
Positive Supply

Temp. Coeff. of Analog COMMON
(With respect to positive supply)

250kn between Common and
Positive Supply

Segment Sinking Current
(Except Pins 19 & 20)
(Pin 19 only)
(Pin 20 only)

V+ = 5.0V
Segment Voltage

Power Dissipation Capacitance

vs. Clock Frequency

NOTES: 3.
4.
5.
6.

IlVN

2.4

2.8
150

5

8.0

10
4

16
7

= 3V

ppml"C

mA

40

pF

Unless otherwise noted, specifications apply at TA = 25°C, fclock = 16kHz and are tested in the circuit of Figure 4.
Refer to "Differential Input" discussion.
48kHz OSCillator, Figure 5, increases current by 35/lA (typ).
Extra capacitance of CERDIP package changes oscillator resistor value to 470kn or 150kn (1 reading/sec or 3 readings/sec).

6-143
Note: All typical values have been guaranteed by characterization and are not tested.

a
ICL7137
....
~

I.

".
40KD

+-

-IV

L

ov

1Mn

AF0257QI

Figure 5: Clock Frequency 48kHz
(3 readings/sec)
COO1220!

Figure 3: ICL7137 with LED Display

DETAILED DESCRIPTION

(Analog Section)
Figure 1 shows the Functional Diagram of the Analog
Section for the ICL7137. Each measurement cycle is
divided into four phases. They are 1) auto-zero (A-Z) , 2)
signal integrate (INn, 3) de-integrate (DE) and 4) zerointegrator (ZI).
.
AUTO-ZERO PHASE
During auto-zero three things happen. First, input high
and low are disconnected from the pins and internally
shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback
loop is closed around the system to. charge the auto-zero
capacitor, CAZ, to compensate for offset voltages in the
buffer amplifier, integrator, and comparator. Since the
comparator is included in the loop, the A-Z accuracy is
limited only by the noise of the system. In any case, the
offset referred to the input is less than 10j.lV.
SIGNAL INTEGRATE PHASE
During signal integrate, the auto-zero loop is opened, the
internal short is removed, and the internal input high and
low are connected to the external pins. The converter then
integrates the differential voltage between IN HI and IN La
for a fixed time. This differential voltage can be within a wide
common-mode range; within 1V of either supply. If, on the
other hand, the input signal has no return with respect to
the converter power supply, IN La can be tied to analog
COMMON to establish the correct common-mode voltage.
At the end of this phase, the polarity of the integrated signal
is determined.

TEST CIRCUITS
IN

".

+-

ov

IMn

AF025601

Figure 4: 7137 Clock Frequency 16kHz
(1 reading/sec)

6-144
Note: All typical values have been guaranteed by characterization and are not tested.

ICL7137
However, analog COMMON has some of the attributes of a
reference voltage. When the total supply voltage is large
enough to cause the zener to regulate ( > 7V), the COMMON voltage will have a low voltage coefficient
(0.001 %/%), low output impedance(",,35n), and a temperature coefficient typically less than 150ppmrC.

DE-INTEGRATE PHASE
The next phase is de-integrate, or reference integrate.
Input low is internally connected to analog COMMON and
input high is connected across the previously charged
reference capacitor. Circuitry within the chip ensures that
the capacitor will be connected with the correct polarity to
cause the integrator output to return to zero. The time
required for the output to return to zero is proportional to the
input signal. Specifically; the digital reading displayed is
1000(VINIVREF)·

The limitations of the on-Chip reference should also be
recognized, however. The reference temperature coefficient (TC) can cause some degradation in performance.
Temperature changes of 2°C to 8°C, typical for instruments,
can give a scale factor error of a count or more. Also, the
COMMON voltage will have a poor voltage coefficient when
the total supply voltage is less than that which will cause the
zener to regulate ( < 7V). These problems are eliminated if
an external reference is used, as shown in Figure 6.

ZERO INTEGRATOR PHASE
The final phase is zero integrator. First, input low is
shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Finally, a feedback
loop is closed around the system to input high to cause the
integrator output to return to zero. Under normal conditions,
this phase lasts for between 11 to 140 clock pulses, but
after a "heavy" overrange conver'Sion, it is extended to 740
clock pulses.

V'
Y+ REF

Differential Input

v'

HI

The input can accept differential voltages anywhere
within the common-mode range of the input amplifier; or
specifically from 0.5V below the positive supply to 1.0V
above the negative supply. In this range the system has a
CMRR of 90dB typical. However, since the integrator also
swings with the common-mode voltage, care must be
exercised to assure the integrator output does not saturate.
A worst case condition would be a large positive commonmode voltage with a near full-scale negative differential
input voltage. The negative input signal drives the integrator
positive when most of its swing has been used up by the
positive common-mode voltag'S. For these critical applications the integrator swing can be reduced to less than the
recommended 2V full-scale swing with little loss of accoracy. The integrator output can swing within 0.3V of either
supply without loss of linearity.

6.8 VOLT
ZENER

1.2 VOLT
REFERENCE
(lNTERSIL

I

ICL7137

ICI.808ll)

t
COMMON

v(b)

(a)
0501480)

08014901

Figure 6: Using an External Reference
Analog COMMON is also used as the input low return
during auto-zero and de-integrate. If IN LO is different from
analog COMMON, a common-mode voltage exists in the
system and is taken care of by the excellent CMRR of the
converter. However, in some applications IN LO will be set
at a fixed known voltage (power supply common for
instance). In this application, analog COMMON should be
tied to the same point, thus removing the common-mode
voltage from the converter. The same holds true for the
reference voltage. If the reference can be conveniently
referred to analog COMMON, it should be since this
removes the common-mode voltage from the reference
system.

Differential Reference
The reference voltage can be generated anywhere within
the power supply voltage of the converter. The main source
of common-mode error is a roll-over voltage caused by the
reference capacitance losing or gaining charge to stray
capacity on its nodes. If there is a large common-mode
voltage, the reference capacitor can gain charge (increase
voltage) when called up to de-integrate a positive signal but
lose charge (decrease voltage) when called up to deintegrate Ii negative input signal. This difference in reference for ( + ) or ( - ) input voltage will give a roll-over error.
However, by selecting the reference capaCitor large enough
in comparison to the stray capacitance, this error can be
held to less than 0.5 count for the worst case condition (see
Component Value Selection).

Within the IC, analog COMMON is tied to an N channel
FET which can sink 100iJA or more of current to hold the
voltage 3.0V below the positive supply (when a road is trying
to pull the common line positive). However, there is only
1iJA of source current, so COMMON may easily be tied to a
more negative voltage, thus overriding the internal reference.
'

Analog Common

TEST

This pin is included primarily to set the common-mode
voltage for battery operation or for any system where the
input signals are floating with respect to the power supply.
The COMMON pin sets a voltage that is approximately 3.0V
more negative than the positive supply. This is selected to
give a minimum end-of-life battery voltage of about 6V.

The TEST pin is coupled to the internal digital supply
through a 500n reSistor, and functions as a "lamp test."
When TEST is pulled high (to V +) all. segments will be
turned on and the display should read - 1888. The TEST
pin will sink about 10mA under these conditions.

6-145
Note: All typical values have been guaranteed by characterization and are not tested.

alCL7137

...

, ... DISPLAY FONT
~

o

,.
,.

:·2:: '-: S S -: :3 '3

,I·.-J.

0';'.
•

To SWitch Drive,.

-----r----

.v From Comp.tt.tor O u t p u l - - - - - j - - - - ,

El7,

l'
-~~----~~r_----------;_--r__;--T_----------~v-

.

I

ContrOl Logic

SOO II

I

I
"Three Inverters.
One inverter shown for clarity.

OSC 1

•

TEST

!

~ ::JL~'D

:

~-------~~----------------------------~
,
'
OSC 3';

'---------+-----1

j-----J

AF025801

Figure 7: Digital Section

System, Timing
Figure 9 shows the clock oscillator provided in the 7137.
Three basic clocking arrangements can be used:
1300

1.

An external oscillator connected to pin 40.

2.

A crystal between pins 39 and 40.

3.

An RC oscillator using all three pins.

08015001

Figure a: Display Buffering for
Increased Drive Current

L

DETAILED DESCRIPTION

(Digital Section)
Figure 7 shows the digital section for the 7137. The
segments are driven at 8mA, suitable for instrument size
common anode LED displays. Since the 1000 output (pin
19) must sink current from two LED segments, it has twice
the drive capability or 16mA. The polarity indication is "ON"
for negative analog inpllts. If IN La and IN HI are reversed,
this indication can be reversed also, if desired.

08015101

Figure 9: Clock Circuits
The oscillator frequency is divided by four before it clocks
the decade counters. It is then further divided to form the
four convert-cycle phases. These are Signal integrate (100P
counts), reference de-integrate (0 counts to 2000 counts),

Figure 8 shows a method of increasing the output drive
current, using four DM7407 Hex Buffers. Each buffer is
capable of sinking 40mA.
6-146

Note: All typical values have been guaranteed by characterization and are not tested,

.D~DIl.

ICL7137
Oscillator Components

zero integrator (11 counts to 140 counts') and auto-zero
(910 counts to 2900 counts). For signals less than fullscale, auto-zero gets the unused portion of reference deintegrate and zero integrator. This makes a complete
measure cycle of 4000 (16,000 clock pulses) independent
of input voltage. For three readings/second, an oscillator
frequency of 48kHz would be used.

For all ranges of frequency a 50pF capacitor is recommended and the resistor is selected from the approximate
equation f "" 0.45/RC. For 48kHz clock (3 readings/
second), R = 180kn, while for 16kHz (1 reading/sec),
R = 560kn.

Reference Voltage

To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of the 60Hz ~eriod.
Oscillator frequencies of 60kHz, 48kHz, 40kHz, 33 Y3kHz,
. etc. should be selected. For 50Hz rejection, oscillator
frequencies of 6693kHz, 50kHz, 40kHz, etc. would be
suitable. Note that 40kHz (2.5 readings/second) will reject
both 50Hz and 60Hz (also 400Hz and 440Hz.) See also
A052.

The analog input required to generate full-scale output
(2000 counts) is: VIN = 2VREF. Thus, for the 200.0mV and
2,000V scale, VREF should equal 100.0mV and 1.000V,
respectively. However, in many applications where the A/D
is connected to a transducer, there will exist a scale factor
other than unity between the input voltage and the digital
reading. For instance, in a weighing system, the deSigner
might like to have a full-scale reading when the voltage from
the transducer is O.682V. Instead of dividing the input down
to 200.0mV, the deSigner should use the input voltage
directly and select VREF = 0.341V. A suitable value for the
integrating resistor would be 330kn. This makes the system
slightly quieter and also avoids the necessity of a divider
network on the input. Another advantage of this system
occurs when a digital reading of zero is desired for VIN -4= o.
Temperature and weighing systems with a variable tare are
examples. This offset reading can be conveniently generated by connecting the voltage transducer between IN HI and
COMMON and the variable (or fixed) offset voltage between COMMON and IN LO.

• After an overranged conversion of more than 2060 counts, the zero
integrator phase will last 740 counts, and auto-zero will last 260 counts.

COMPONENT VALUE SELECTION
(See Application Note A052)

Integrating Resistor
Both the buffer amplifier and the integrator have a class A
output stage with 6p.A of quiescent current. They can supply
-1 p.A of drive current with negligible non-linearity. The
integrating resistor should be large enough to remain in this
very linear region over the input voltage range, but small
enough that undue leakage requirements are not placed on
the PC board. For 2V full-scale, 1.8Mn is near optimum,
and similarly 180kn for a 200.0mV scale.

Integrating Capacitor

TYPICAL APPLICATIONS

The integrating capacitor should be selected to give the
maximum voltage swing that ensures tolerance build-up will
not saturate the integrator swing (approx. 0.3V from either
supply). When the analog COMMON is used as a reference,
a nominal ±2V full-scale integrator swing is fine. For three
readings/second (48kHz clock) nominal values for CINT are
0.047p.F, for 1 reading/Second (16kHz) 0.15p.F. Of course,
if different oscillator frequencies are used, these values
should be changed in inverse proportion to maintain the
same output swing.

The 7137 may be used in a wide variety of configurations.
The circuits which follow show some of the possibilities, and
serve to illustrate the exceptional versatility of these A/D
converters.

The integrating capacitor should have low dielectric
absorption to prevent roll-over errors. While other types
may be adequate for this application, polypropylene capacitors give undetectable errors at reasonable cost.

Auto-Zero Capacitor
The size of the auto-zero capacitor has some influence
on the noise of the system. For 200mV full-scale where
noise is very important, a 0.47p.F capacitor is recommended. The ZI phase allows a large auto-zero capacitor to
be used without causing the hysteresis or overrange
hangover problems that can occur with the ICL7107 or
ICL7117 (See Application Note A032).

Reference Capacitor
A 0.1/LF capacitor gives good results in most applications. However, where a large common-mode voltage exists
(Le., the REF LO pin is not at analog COMMON) and a
200mV scale is used, a larger value is required to prevent
roll-over error. Generally, 1.0p.F will hold the roll-over error
to 0.5 count in this instance .
• After an overranged conversion of more than 2060 counts, the zero intergrator phase will last 740 counts, and auto-zero will last 260 counts.
6-147
Note: All typical values have been guaranteed by characterization and are not tested.

e...
...

Co)

...
.........
g

'(11)

ICL7137

.

osc,

To,",,'

.......,

OSC.
OSC.3

.

Set VN' '" 1.000V

OSC)

COMMON

REF LO
C REF
C REF
COMMON

lMiI

D'0....;::7••
' ::-4~---'l'-'O=.O1"".'-'....--_ _--o'N

I.Z

PO.,lIo'F

v-

240Idl

IN

0.47"F

1.eMn

BUFF

INT

G,
C,

v·

A

--.O.Ol,.F

"",

INT

...."

1M!!

IHHI
INLO

'1OIdl

BUFF

e--

REF HI

'Oldl

C REF
C REF

/

SOp.

TEST

RIFLO

INLO

'1OIdl

!

au',

INT
y. G,

.c,

'"

Go

GND

21

AF026001

Figure 17: AC to DC Converter with 7137
A052 "Tips for Using Single-Chip 3V2-Digit AID
Converters," by Dan Watson.

APPLICATION NOTES
A016 "Selecting AID converters," by David Fullagar.
A017 "The Integrating AID Converter," by Lee Evans.
A018 "Do's and Dont's of Applying AID Converters," by
Peter Bradshaw and Skip Osgood.
A019 "4V2-Digit Panel Meter Demonstratorl
Instrumentation Boards," by Michael Dufort.
A023 "Low Cost Digital Panel Meter Designs," by David
Fullagar and Michael Dufort.
A032 "Understanding the Auto-Zero and Common-Mode
Behavior of the ICL71061719 Family," by Peter
Bradshaw.
A046 "Building a Battery-Operated Auto Ranging DVM
with the ICL7106," by Larry Goff.
A047 "Games People Play with Intersil's AID Converters"
edited by Peter Bradshaw.

ICL7137 EVALUATION KITS
After purchasing a sample of the 7137, the majority of
users will want to build a simple voltmeter. The parts can
then be evaluated against the data sheet specifications,
and tried out in the intended application.
To facilitate evaluation of this unique circuit, Intersil is
offering Ii kit which contains all the necessary components
to build a 3V2-digit panel meter. With the ICL7137EVIKit, an
engineer or technician can have the system "up and
running" in about half an hour. The kit contains a circuit
board, LED display, passive components, and miscellaneous hardware.

. 6-'150

Note: All typical values have been guaranteed by characterization and are not tested.

ICL8018A/8019A/8020A
4-Bit Expandable Current-Switch
GENERAL DESCRIPTION

FEATURES

The Intersil ICL8018A family are high speed precIsion
current switches for use in current summing digital-toanalog converters. They consist of four logically controlled
current switches and a reference device on a single
monolithic silicon chip. The reference transistor, combined
with precision resistors and an external source, determines
the magnitude of the currents to be summed. By weighting
the currents in proportion to the binary bit which controls
them, the total output current will be proportional to the
binary number represented by the input logic levels.
The performance and economy of this family make them
ideal for use in digital-to-analog converters for industrial
process control and instrumentation systems.

•
•
•
•
•

TTL Compatible
12 Bit Accuracy
40ns, Switching Speed
Wide Power Supply Range
Low Temperature Coefficient

APPLICATIONS:
•
•
•
•
•

DI A and AID Converters
Digital Threshold Control
Programmable Voltage Source
Meter Drive
X-V Plotters

ORDERING INFORMATION
ACCURACY

MILITARY
TEMP RANGE
CERDIP

COMMERCIAL
TEMP RANGE
PLASTIC DIP

Individual Devices
.01%
0.1%
1.0%

ICL8018AMJD
ICL8019AMJD
ICL8020AMJD

ICL8018ACPD
ICLB019ACPD
ICLB020ACPD

Matched Sets·
.01%
0.1%
1.0%

ICL8018AMXJD
ICL8019AMXJD
ICL8020AMXJD

ICL8018ACXPD
ICL8019ACXPD
ICL8020ACXPD

°NOTE: Units ordered in equal quantities will be matched such
that the VSE'S of the 8019 will be within ±10mV of the
8018 compensating transistor, and the VSE'S of the
8020 will be w~hin ± 50mV. The ICL8018·X matched
sets consist of one 8018, one 8019, and one 8020. The
8019-X contains one 8019 and one 8020, while the
8020-X contains two 8020's. Units shipped as matched
sets will be marked with a unique set number.

.

LOGIC INPUTS
I

BITe
5

BIT 3
e

BIT 2
3

BIT 1
2

v+
D12

r'
v+

LOGIC
INPUTS

REFERENCE
TRANSISTOR

'-}

BIT2
BIT3

1

BIT 4

1

COMPENSATION{E 6
TRANSISTOR C

•

14 V-

BIT2 TO
PRECISION
11 BIT 3 RESISTORS
BIT4

9 BASE LINE
•

OLITPUT

loUT

BASE

OUTLINE DWGS
JD,PD
COO13601

EMITTER

\

10
BITe

...

11
BIT a

.

12
BIT 2

-

13
BIT 1,

TO PRECISION RESISTORS
4CIII
10k
80005301

Figure 1: Functional Diagram

Figure 2: Pin Configuration

6-151
Note: All typical values have been guaranteed by characterization and are not tested.

302200-002

ta

~ IC.L8018A/8019A/8020A

"i
...

ABSOLUTE MAXIMUM RATINGS

=
i

-=
...

a

Supply Voltage ................................................ ±20V
Logie Input Voltage ................................. -2V to V+
VSASELINE .....................................•...... V- to +SV
Output Voltage ........................... VSASELINE to + 20V
Storage Temperature ...................... -6S'C to + 1S0'C

Operating Temperature ICL8018AM
ICL8019/20AM ..................... -SS'C to + 12SoC
ICL8018/19/20AC ...................... O·C to +70'C
Lead Temperature (Soldering, 10sec) .........•....... 300°C

Stresses above those listed under Absolute M~imum Ratings may cause permanent dal)'lage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (4.SV::; V+ ::; 20V, V- = -1SV, TA - 25°C, Voltage
PARAMETER
Absolute Error
ICLB01BA
ICLB019A
ICLB020A

TEST
CONDITIONS

MIN

i

@

pin 6

= -SV)

I

TYP

VINHI = 5.0V
VINLO= O.OV

MAX

UNIT

±.01
±0.1
±1

%

Error Temperature Coefficient
ICLB01BA
ICLB019A
ICLB020A

±2
±2
±2

Settling Time To ±1/2 LSB, RL * lkn
B BIT
12 BIT

100
200

ns

Switching Time To Turn On LSB

40

ns

1.0
0.5
0.25
0.125

mA

Output Current (Nominal)
BIT 1 (MSB)
BIT 2
BIT 3
BIT 4 (LSB)
Zero Oulput Current
Input Coding-Complementary Binary
(See Truth Table)
Logic Input Voltage
"0" (Swijch ON)
"1" (Switch OFF)
Logic Input Current
"0"
"1" (into device)

10

VIN = 5.0V

Outpu1 Voltage Range

VBASELINE + 1V

~IOUT

±5
±25
±50

ppml"C

50

nA

+10

V

O.B

V

-2
0.1

mA
p.A

< 400nA
2.0
-1.0
0.01

VIN -OV
VIN= 5V

Power Supply Reiection
V+
V-

.005
.0005

Supply Voltage Range
V+
V-

4.5
-10

%IV

5
-15

20
-20

V

7
1

10
3

mA

surflY Current (Vsupp - ±20V)

1-

6-152
Note: All typical values have been guaranteed by characterization and are not tested.

n

ICL8018A/8019A/8020A
BASIC 01 A THEORY

limiting value is called full scale output. The maximum
output is always less than the full scale output by one least
significant bit, LSB. For a twelve bit system (resolution 1
part in 4096) with a full scale output of 10.0 volts the
maximum output would be 4095/4096 x 10V. Since the
numbers are extremely close for high resolution systems,
the terms are often used interchangeably.

The majority of digital to analog converters contain the
elements shown in Figure 3. The heart of the 01 A converter
is the logic controlled switching network, whose output is an
analog current or voltage proportional to the digital number
on the logic inputs. The magnitude of the analog output is
determined by the reference supply and the array of
precision resistors, see Figure 4. If the switching network
has a current output, often a transconductance amplifier is
used to provide a voltage output.

The accuracy of a 01 A converter is generally taken to
mean the largest error of any output level from its nominal
value. The accuracy or absolute error is often expressed
as a percentage· of the full scale output.
Linearity relates the maximum error in terms of the
deviation from the best straight line drawn through all the
possible output levels. Linearity is related to accuracy by the
scale factor and output offset. If the scale factor is exactly
the nominal value and offset is adjusted to zero, then
accuracy and linearity are identical. Linearity is usually
specified as being within ±1/2 LSB of the best straight line.

LOGIC INPUTS

REFERENCE

SWITCHING NETWORK

Another desirable property of 01 A converter is that it be
monotonic. This simply implies that each successive
output level is greater than the preceding one. A possible
worst case condition would be when the output changes
from most significant bit (MSB) OFF, all other bits ON to the
next level which has the MSB ON and all other bits OFF,
e.g., 10000 . . . to 01111.

RESISTOR ARRAY

lD00630r

Figure 3: Elements of a DI A Converter

In applications where a quad current switch drives a
transconductance amplifier (current to voltage converter),
transient response is almost exclusively determined by the
output amplifier itself. Where the quad output current drives
a resistor to ground, switching time and settling time are
useful parameters.

DEFINITION OF TERMS
The resolution of a 01 A converter refers to the number
of logic inputs used to control the analog output. For
example, a 01 A converter using two quad current sources
wOl.lld be an S bit converter. If three quads were used, a 12
bit converter would be formed. Resolution is often stated in
terms of one part in, e.g., 256 since the number of
controlling bits is related to total number of identifiable
levels by the power of 2. The four bit quad has sixteen
different levels (see Table 1) each output corresponding to
a particular logic input word.

Switching time is the familiar 10% to 90% rise time type
of measurement. Low capacitance scope probes must be
used to avoid masking the high speeds that current source
switching affords. The settling time is the elapsed time
between the application of a fast input pulse and the time at
which the output voltage has settled to or approached its
final value within a specified limit of accuracy. This limit of
accuracy should be commensurate with the resolution of
the OAC to be used.

Table 1: ICL8018/19/20 Truth Table

LOGIC INPUT

NOMINAL
OUTPUT
CURRENT (rnA)

o 0 0 0
000 1
001 0
001 1
o 10 0
o 10 1
o 1 10
o 1 1 1
1 000
1 00 1
101 0
101 1
1 10 0
1 10 1
1110
1 1 1 1

1.B75
1.750
1.625
1.500
1.375
1.250
1.125
1.000
0.B25
0.750
0.625
0.500
0.375
0.250
0.125
0.000

Typically, the settling time specification describes how
soon after an input pulse the output can be relied upon as
accurate to within ± 1/2 LSB of an N bit converter. Since the
SOlSA family has been designed with all the collectors of
the current switching transistors tied together, the output
capacitance is constant. The transient response is, therefore, a simple exponential relationship, and from this the
settling time can be calculated and related to the measured
rise time as shown in Table 2.

Table 2: Settling Time vs. Rise Time Resistor
Load
±1I2 LSB
BITS OF
RESOLUTION

ERROR

% FULL
SCALE

B
10
12

Note that maximum output of the quad switch is 1 + 11
2 + 1/4 + liS = 1-7/S = 1.S75 mAo If this series of bits
were continued as 1/16 + 1/32 + 1/64 . . . . . 1/2(n -1),
the maximum output limit would approach 2.0 mA. This

.2%
.05%
.01%

NUMBER OF
NUMBER OF
TIME
RISE TIMES
CONSTANTS

6.2
7.6
9.2

Rise Time (10% - 90%) = 2.2 RL Ceff
6-153

Note: All typical values have been guaranteed by characterization and are not tested.

2.S
3.4
4.2

!
CXI

~

m
0
ca

~

CD

S

e

g

i.......
..i=
=

ICI..8018A/8019A/8020A
and the precision resistors at the emitter that determine the
exact value of switched output current. The emitter resistor
of 07 is equal.to that of as, therefore, 07' s collector current
will be IREF or 125tJA. as has 40kn in the emitter so that its
collector. current will .be twice IREF or 250tJA. In the same
way, the 20kn and 10kn in the emitters of 09 and 010
contribute O.5mA and 1mA to the total collector current.

DETAILED DESCRIPTION

An example ofa practical circuit for the ICL8018A quad
current switch is shown .in Figure 4. The circuit can be
analyzed in two sections; the first generates very accurate
....... currents and the second causes these currents to be
switched according to. input logic signals. A reference
current of 125tJA is generated by a stable reference supply
and a precision resistor. An op-amp with low offset voltage
and low input bias current, such as the ICL8008, is used in
conjunction with the internal reference. transistor, as, to
force the voltage on the common base line, so that the
collector current of as is equal to the reference current. The
will be the sum of the reference
emitter current of
current and a small base current causing a drop of slightly
greater than 10 volts across the 80.kn resistor in the emitter
of as. Since this resistor is connected to -15V; this puts the
emitter of
at nearly -5V a(1d the common base line at
one VBE more positive at -4.35V typically.
Also connected to the common base line are the
switched current source transistors 07 through 010. The
emitters of these transistors are also connected through
weighted precision resistors to -15V and their collector
currents summed at pin 8. Since all these transistors, as
through 010, are designed to have equal emitter-base
voltages, it follows that all the emitter resistors will have
equal voltage drops across them. It is this constant voltage

The reference transistor and four current switching transistors are designed for equal emitter current density by
making the number of emitters proportional to the current
switched.

a

The remaining circuitry provides switching Signals from
the logic inputs. In the switch ON mode, zener diodes 05
through OS, connected to the emitter of each current switch.
transistor 07 thru 010, are reverse biased allowing the
transistors to operate, produCing precision currents
summed in the collectors. The transistors are turned off by
raising the voltage on the zeners high enough to turn on the
zeners and raise the emitters of the switching transistor.
This reverse biases the emitter base diode thereby shutting
off that transistor's collector, current.

aS

aS

The analog output current can be used to drive one load
directly, (1 kn to ground for FS = 1.875V for example) or
can be used to drive a transconductance amplifier to give
larger output voltages.

LOGIC INPUTS
i

lIlT 4
S

r--

VIlE.

lis

LIRE.

7

BIT 3

"

lIlT 2

,
BIT 1

y+

432

"':"""'-

--- -- ------

I
I
I
I
I
I
I
I
I
I
I
I

VOUT

INl14
RS

10k

08015701

Figure 4: Typical Circuit

6-154
Note: All typical values have been guaranteed by characterization and are not tested.

ICL8018A/8019A/8020A
ANALOG
VOLTAGE OUT

TO~AL 1

TC0237QI

Figure 5: Expanding the Quad Switch

EXPANDING THE QUAD SWITCH
While there are few requirements for only 4 bit D to A
converters, the 8018A is readily expanded to 8 and 12 bits
with the addition of other quads and resistor dividers as
shown in Figure 5.

BIT 4
5

81T3
4

8112
3

8.Tl
2

,

y'

D"

To maintain the progression of binary weighted bit
currents, the current output of the first quad drives the input
of the transconductance amplifier directly, while a resistor
divider network divides the output current of the second
quad by 16 and the output current of the third by 256.
e.g., ITotal

= 1 x (1 + "1,12 + 1/4 + Ya) + 1,116(1 + "1,12 + 1t4 + Ya)

+ 1,125611 + 1,12 + "1,14 + 1,18)
= 1 + Y2 + "1,14 + Ya + "1,116 + Y32 + Ys4 + 1,1128
+ "1,1256 + Ys12 + 1,11024 + "1,12048.

r-i-r+,-+.,-+--+--if--O·IOUT

L-O-£-=.p!!....jt-!:!!....I-f-~t-F.!!!!+---1- -

-

-TO
OTHER
QUADS

Note that each current switch is operating at the same
high' speed current levels so that standard 10k, 20k, 40k
and 80kn resistor networks can be used. Another advantage of this technique is that since the current outputs of the
second and third quad are attenuated, so are the errors
they contribute. This allows the use of less accurate
switches and resistor networks in these positions; hence,
the three accuracy grades of .01%, 0.1%, and 1% for the
801SA, 8019A and 8020A, respectively. It should be noted
that only the reference transistor on the most significant
quad is required to set up the voltage on the common base
line joining the three sets of switching transistors (Pin 9).

10k

'Ok

OS015801

Figure 6: Simple Zener Reference
The zener current will be typically 1 mA per quad. The
compensation transistor 06 'is connected as a diode in
series with the external zener. The VSE of this transistor will
approximately match the VSE'S of the current switching
transistors, thereby forcing the external zener voltage
across each of the external resistors. The temperature
coefficient of the external zener will dominate the temperature dependence of this scheme, however using a tempera,
ture compensated zener minimizes this problem. Since 06
is operating at a higher current density than the other
switching transistors, the temperature matching of VSE'S is
not op,timum, but should be adequate for a simple 8 or 10 bit
converter.

GENERATING REFERENCE CURRENTSZENER REFERENCE
As mentioned above, the 8018A switches currents determined by a constant voltage across the external precision
resistors in the emitter of each switch. There are several
ways of generating this constant voltage. One of the
simplest is shown in Figure 6. Here an external zener diode
is driven by the same current source line used to bias
internal Zener D11.

6-155
Note: All typical values have been guaranteed by characterizatiQn and are not tested.

.D~DIL

c0 ICL8018A/8019A/8020A

S
CD

.....

.,TO

C

•

...0Gt

BIT 3

81T2
3

81T1

•

CD
.....

V·

•
D.'

C

...
CD

0

CD
..I

S:!

8
lOUT

--TO
OTHER
QUADS

200(1

'Ok

2Dk

...

-15Y
05015901

Figure 7: PNP Reference
The 8018A series is tested for accuracy with 10V
reference voltage across the precision resistors, implying
use of a ,10 volt zener. Using a different external zener
voltage will only slightly degrade accuracy if the zener
voltage is above 5 or 6 volts.
When using other than 10 volt reference; the effects on
logic thresholds should also be noted (see logic levels
below). Full scale adjustment can be made at the output
amplifier.

The op-amp feedback loop using the internal reference
transistor will maintain proper currents in spite of VSE drift,
beta drift, resistor drift and changes in V-. Using this circuit,
temperature drifts of 2 ppmfOC are typical. A discrete diode
connected as shown will keep 06 from saturating and
prevent latch up if V- is disconnected.
In any reference scheme, it is advisable to capacitively
decouple the common base line to minimize transient
effects. A capacitor, .001 J-lF to .1 J-lF from Pin 9 to analog
ground is usually sufficient.

PNP REFERENCE
Another simple reference scheme is shown in Figure 7.
Here an external PNP transistor is used to buffer a resistor
divider. In this case, the -15 volt supply is used as a
reference. Holding the V- supply constant is not too difficult
since the 8018A is essentially a constant current load. In
this scheme, the internal compensation transistor is not
necessary, since the VSE matching is provided by the
emitter-base junction of the external transistor. A small pot
in series with the divider facilitates full scale output adjustment. A capacitor from base to collector of the external
PNP will lower output impedance and minimize transient
effects.

IMPROVED ACCURACY
As a final note on the subject of setting up reference
levels, it should be pointed out that the largest contributor of
error is the mismatch of VSE'S of the current switching
transistors. That is, if all the VSE'S were identical, then all
precision resistors would have exactly the same reference
voltage across them. A one millivolt mismatch compared
with ten volt reference across, the precision resistors will
cause a .01 % error. While decreasing the reference voltage
will decrease the accuracy, the voltage can be increased to
achieve better than .01 °/~ accuracies. The voltage across
the emitter resistors can b,e doubled or tripled with a
proportional increase in resistor values resulting in improved absolute accuracy as well as improved temperature
drift performance. This technique has been used successfully to implement up to 16 bit Of A converters.
'

FULL COMPENSATION REFERENCE
For high accuracy, low drift applications, the reference
scheme of Figure 4, offers excellent performance. In this
circuit, a high gain op-amp compares two currents.,The first
is a reference current generated in RS by the temperature
compensated zener and the virtual ground at the noninverting op-amp input. The second is the collector current
of the reference transistor 06, provided on the quad switch.
The output of the op-amp drives the base of 06 keeping its
collector current exactly equal to' the reference current.
'Since the switching transistor's emitter current densities are
equal and since the preciSion resistors are proportional, all
of the switched collector currents will have the proper value.

For further information see the following Applications
Bulletins.
A016 "Selecting AID Converters" by Dave Fullagar.
A018 "Do's and Don'ts of Applying AID Converters" by
Peter Bradshaw and Skip Osgood.
A020 "A Cookbook Approach to High Speed Data
Acquisition and Microprocessor Interfacing"by Ed
Sliger.
6-156

Note: All typical values have been guaranteed by characterization and are not tested.

.U~UIl.;

ICL80521lCL 7104
and ICL8068/ICL7104

-...
N

14/16-Bit IlP-Compatible
2-Chip AID Converter

n
r

...

GENERAL DESCRIPTION

FEATURES

The ICl7104, combined with the ICl8052 or ICl8068,
forms a member of Intersil's high performance AID converter family. The ICl7104-16, performs the analog switching
and digital function for a 16-bit binary AID converter, with
full three-state output, UART handshake capability, and
other outputs for easy interfacing. The ICl7014-14 is a
14-bit version. The analog section, as with all Intersil's
integrating converters, provides fully precise Auto-Zero,
Auto-Polarity (including :to null indication), single reference
operation, very high input impedance, true input integration
over a constant period for maximum EMI rejection, fully
ratiometric operation, over-range indication, and a medium
quality built-in reference. The chip pair al.so offers optional
input buffer gain for high sensitivity applications, a built-in
clock oscillator, and output signals for providing an external
Auto-Zero capability in preconditioning circuitry, synchronizing external multiplexers, etc.

•

•
•
•
•
•
•
•
•
•
•
•

2

16/14 Bit Binary Three-State Latched Outputs
Plus Polarity and Overrange
Ideally Suited for Interface to UARTs and
Microprocessors
Conversion On Demand or Continuously
Guaranteed Zero Reading for Zero Volts Input
True Polarity at Zero Count for Precise Null
Detection
Single Reference Voltage for True Ratiometric
Operation
Onboard Clock and Reference
AutO-Zero; Auto-Polarity
Accuracy Guaranteed to 1 Count
All Outputs TTL Compatible
±4V Analog Input Range
Status Signal Available tor External Sync, AIZ in
Preamp, etc

ORDERING INFORMATION
PART NUMBER

TEMP. RANGE

PACKAGE

ICLB052CPD

O·C to +70·C

14-Pin Plastic DIP

ICLB052CDD

O·C 10 +70·C

14-Pin Ceramic DIP

ICLB052ACPD

O·C 10 +70·C

14-Pin Plaslic DIP

ICLB052ACDD

O·C to +70·C

14-Pin Ceramic DIP

ICLB06BCJD

O·C to +70·C

14-Pin CERDIP

ICLB06BACJD

O·C to +70·C

14·Pin CERDIP

+11V

PART NUMBER

TEMP. RANGE

PACKAGE

ICL7104-14CJL

O·C to -70·C

40-Pin CERDIP

ICL7104-14CPL

O·C to +70·C

40-Pin Plastic DIP

ICL7104-14CDL

O·C to +70·C

40-Pin Ceramic DIP

ICL7104-16CJL

O·C to +70·C

4O-Pin CERDIP

ICL7104-16CPL

O·C to +70·C

40·Pin Plastic DIP

ICL7104-16CDL

O·C to +70·C

4O-Pin Ceramic DIP

-1IV

rnl
t. •

I-:==

~~~~~~~~~~~~--,

'f

I· .. , ....

I 14 .... 12.

AIIIi

MODE

80005401

Figure 1: ICL8052A (8068A)/ICL7104 16/14 Bit AID Converter Functional Diagram

6-157
Note: All typical values have been guaranteed by characterization and are not tested.

g ICL8052/1CL7,104 .
d ABSOLUTE MAxIMUM RATINGS
.....

~

:::.
(\I
1ft

a
-

;

.....

,

ICL7104
V+ Supply (GND to V+) '. ................ , ............. , .. 12V
V ++ to V- ................................... , ................ 32V
Positive Supply Voltage (GND to V ++) ............... 17V
Negative Supply Voltage (GND to V-) ................. 17V
Analog Input Voltage (Pins 32 -39) (4) ...... V + + to VDigital Input Voltage
'
(Pins 2-30) (5) ........ (GND-0.3V) to (V+ +0.3V)

Power Dissipation (1) All Devices ""."""""." .. 500mW
Storage Temperature ...................... -65°C to + 150°C
Operating Temperature ...... , ... ,., ........... O°C to + 70°C
Lead Temperature (Soldering, 10sec) ., .......... ,., .. 300°C
ICL8052, 8068
Supply Voltage ................................................ ±18V
Differential Input Voltage (8068) ......................... ±30V
(8052) .......................... ±6V
Input Voltage (2) ........ , ........... , ........................ ±1.5V
Output Short Circuit ,Duration,
All Outputs (3) ... , ...... " .. , ................... lndefinite

Notell:
1: Dissipation rating assumes device is mounted with all leads welded or soldered to printed circuit board in ambient temperature below + 70·C. For higher
temperatures, derate 1OmW I·C,
2: For supply voltages less than ± 15V, the absolute maximum input voltage is equallo the supply voltage,
3: Short circuit may be to ground or either supply, Rating applies to + 70·C ambient temperature,
4: Input voltages may exceed the supply voltages provided the input current is limited to ± 1001tA,
5: Connecting any digital inputs or outputs to voltages greater than V + or less than GND may cause destructive device latchup. For this reason it is
recommended that no inputs from sources not on the same power supply be applied to the ICL7104 before :its power supply is established.
Stresses above those listed under" Absolute· Maximum Ratings" may cause permanent damage to the devices, This is a stress rating only and ·functional
operation of ,the devices at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for el(lended periods may affect device reliability,

INTEGRATOR ..
OUT
COMP
OUT

V••
DIGGND
STH

POL

BUFFER
(-+iN)

REF
CAP

O.R.
BIT 18
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BITe
BIT 8
BITT
BITS
BITS
BIT 4
BIT 3
BIT 2

INTEGRATOR
(+IN)

REF
PASS

11

:~1~GRATOR
BUFFER
(-IN)

REF
OUT

V••
DIGGND
STH

BUFFER
OUT

REF
SUPPLY

!,~-- ..
~

POL [

•,.
,."
"
""

ICL7104
-16

"

17

,t
to

.

O.R.
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
N.C.
N.C.
BIT a
BIT 7
BITS
BITS
BIT 4
BIT 3
·BIT2

VCOMPIN
REFCAP 1
VREF
AZ
ANALOG·GND
REFCAP2
BUFIN
ANALOG liP

:

:

··,•
•
•

.....•
.." ~
..
:... ~
.. f 1:1 "I!ill,. ·1
If

ICL7104
,. -14

"

12

!"
"
"..

~

V+

eE7[I'l

SEN

Rlii
MODE
CLOCK· 2
CLOCK 1

17

24

",t

23

It

21

NOTE

LiEN
BIT 1

..

=

c0013711

COO13811

(OUTLINE DWGS DO, JD, PO)

(OUTLINE DWGS DL, JL, PL)

Figure 2: Pin Configurations

ICL7104 ELECTRICAL CHARACTERISTICS
SYMBOL

(V+ =+5V, V++ = +15V,
TEST
CONDITIONS

CHARACTERISTICS

v-

MIN

= -15V, TA=25°C)

TYP

MAX

UNIT

liN

Clock Input

CLOCK 1

Vin'" +5V to OV

±2

±7

±30

'iN

Comparator lIP

CaMP IN (Note 1)

Vin= OV to +5V

-10

±0,001

+10

I'H
I,L

Inputs

MODE

with Pulldown

I'H
I,L

V,H

Inputs

SEN, RtH

with
Pullups

LBEN, MBEN,
HBEN, .CE7[O

Input High Voltage

All Digital Inputs

I

(Note 2)

Y,N = +5V

+1
-10

+5
±0.01

+30·

Vin= OV
Vin= +5V

-10

±O,Ot

+10

Yin =OV

-30

-5

-1

ItA
ItA
ItA
ItA
ItA
ItA

2,5

2.0

-

V

&-158
Note: All typical· values have been guaranteed by characterization and are not tested.

+10

ICL8052/ICL 7104
ICL7104 ELECTRICAL CHARACTERISTICS (CONT.)
SYMBOL

TEST
CONDITIONS

CHARACTERISTICS

VIL

Inpul Low Voltage

f-:V.:.O::.:;L=----_--\ Digital
VOH
Outputs
f-:V.:.O
:::.H'-----\ Three-Stated
On
Digital Outputs
Three-Stated Off

MIN

All Digital Inputs
LBEN
MBEN (IS-only)
HBEN
CEILD
BIT n, POL, OR

1(Note 3)

IOL = I.SmA

I

4.5

V

2.4

3.S

V

-10

±.001

+10

0.3

.4

IOH = -10llA

BIT n, POL, OR

05Vou t:5V+

VOL
Non-Three State
I-V....:O:..:H=------t Digital

STTS

IOL = 3.2mA

I-V....:O:..:L=----_-t Output
VOH

CLOCK 2

IOL = 3201lA

CLOCK 3 (-14 ONLY)

o.S

V

4.S

V

0.27

IOL = I.SmA
2.4

VOH

.4

2Sk

Switch 1

ROS(on)

Switches 2,3

4k

20k

Switches 4,S,S,7,8,9

2k

10k

Switch Leakage

15

1+

Clock Freq. (Note 4)

DC

pA

200

400

200

SOO

kHz

+ SV Supply Current
All outputs high impedance

Freq. = 200kHz

1++

+ ISV Supply Current

Freq. = 200kHz

.3

1.0

1-

- 15V Supply Current

Freq. = 200kHz

25

200

I-~-:-+---t Supply Voltage

Logic Supply

Note 5

4.0

+11.0

V

I-V-~-----\

Positive Supply

+10.0

+16.0

Negative Supply

-16.0

-10.0

V
V

NOTES: 1.
2.
3.
4.
S.

Supply Currents

V
V

3.S

ROS(on)
f-R....:O;:.:S",(o::;n:<..)---\ Switch
IO(of!)
Clock

V
V

3.3

2.4

Range

mA

This spec applies when not in Auto-Zero phase.
Apply only when these pins are inputs, I.e., the mode pin is low, and the 7104 is not in handshake mode.
Apply only when these pins are outputs, i.e., the mode pin is high or the 7104 is in handshake mode.
Clock circuit shown in Figs. 15 and 16.
V + must not be more positive than V + + .

ICL8068 ELECTRICAL CHARACTERISTICS
SYMBOL

CHARACTERISTICS

(VSUPPLY = ±15V unless otherwise specified)

TEST
CONDITIONS

8068

8068A
UNIT

MIN

TYP

MAX

MIN

TYP

MAX

EACH OPERATIONAL AMPLIFIER

vas

Input Offset Voltage

VCM=OV

20

65

20

65

mV

liN
CMRR

Input Current (either input) (Note 1)

VCM = OV

175

250

80

150

pA

Common-Mode Rejection Ratio

VCM - ±10V

Non-Linear Component of CommonMode Rejection Ratio (Note 2)

VCM=±2V

Av

Large Signal Voltage Gain

RL = 50kn

70

90

70

110

90

dB

110

20,000

dB

20,000

VIV

SR

Slew Rate

S

6

GBW

Unity Gain Bandwidth

2

2

ISC

Output Short-Circuit Current

5

10

5

V/jJ.s
MHz
10

mA

COMPARATOR AMPLIFIER

AVOL

Small-signal Voltage Gain

+VO

Positive Output Voltage Swing

RL = 30kn
+12

4000
+13

+12

+13

VIV
V

-yo

Negative Output Voltage Swing

-2.0

-2.6

-2.0

-2.6

V

1.60

1.75

VOLTAGE REFERENCE

1.75

1.90

V

Vo

Output Voltage

RO

Output Resistance

5

5

ohms

TC

Temperature· Coefficient

50

40

ppm/DC

1.5

6-159
Note: All typical values have been guaranteed by characterization and are not tested.

2.0

~
7104
... ICL80521lCL
.

a

ICL8068 ELECTRICAL

CHARACTERISTI~S

.~

~

a

SYMBOL

,

CHARACTERISTICS

VSUPPlY

Supply Voltage Range

ISUPPlY

Supply Current Total

(CONT.)

TEST
CONDITIONS

8068A

8068

UNIT
MIN

TYP

MAX

MIN

±16

±10

±10

TYP

14

MAX
±16

V

14

mA

8

ICL8052 ELECTRICAL CHARACTERISTICS (VSUPPLY = ±15V unless otherwise specified)
SYMBOL

TEST
CONDITIONS

CHARACTERISTICS

8068

8068A
UNIT

MIN

TYP

MAX

MIN

TYP

MAX

EACH OPERATIONAL AMPLIFIER

VOS

Input Offset Voltage

VCM=OV

20

75

20

75

mV

liN
CMRR

Input Current (either input) (Note 1)

VCM=OV

5

50

2

10

pA

Common-Mode Rejection Ratio

VCM - ±10V

Non-Linear Component of CommonMode Rejection Ratio (Note 2)

VCM=±2V

Large Signal Voltage Gain

Rl = 50kn

AV
SR

70

70

90
110

20,000

90

dB

110

dB

6

V/p.s

20,000

Slew Rate

VIV

6

GBW

Unity Gain Bandwidth

1

ISC

Output Short-Circuit Current

20

MHz

1
100

20

mA

100

COMPARATOR AMPLIFIER

AVOl

Small-signal Voltage Gain

+VO

Positive Output Voltage Swing

Rl =30kn
+12

4000
+13

+12

+13

VIV
V

-yo

Negative Output Voltage Swing

-2.0

-2.6

-2.0

-2.6

V

1.60

1.75

VOLTAGE REFERENCE

Vo

Output Voltage

RO
TC

Output Resistance

VSUPPlY

Supply Voltage Range

1.5

1.75

2.0

5

Temperature Coefficient

1.90

V

5

50

ohms

40

±10

±16

ppm/'C
±16

±10,

V

Supply Current Total
12
6
12
6
mA
ISUPPlY
NOTES: 1. The Input bias currents are lunctlon leakage currents which approximately double for every 10'C Increase In the lunctlon temperature,
TJ. Due to limited production test time, the input bias currents are measured with junctions at ambient temperature. In normal
operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, Pd. TJ = TA + ROJAPd
where ROJA is the thermal resistance from junction to ambient. A heat sink can be used to reduce temperature rise.
'
2, This is the only component that causes error in dual-slope converter.

SYSTEM ELECTRICAL CHARACTERISTICS: ICL806817104 (V++ = +15V, v+ = +5V, v- = -15V,
Clock Frequency = 200kHz)
8068A17104·14
CHARACTERISTICS

8068A17104·16

TEST CONDITIONS

UNIT
MIN

TYP

MAX

MIN

TYP

MAX

-0.0000

±O.OOOO

+0.0000

-0.0000

-0.0000

+0.0000

Hexadecimal
Reading

lFFF

2000

2001

7FFF

8000

8001

Hexadecimal
Reading

1

0.5

1

Zero Input Reading

Vin= O,OV
Full Scale = 4.000V

Ratiometric Reading (1)

Vin

Linearity over ± Full Scale (error of
reading from best straight line)

-4V:S Vin:S +4V

0.5

Differential· Linearity (difference between
worst case step of adjacent counts and
ideal step)

-4V:S Vin:S +4V

.01

Rollover error (Difference in reading for
equal positive & negative voltage near
full scale)

-Vin= +Vin-::::=.4V

0.5

Noise (P-P value not exceeded 95% of
time)

Vin= OV
Full scale = 4.OO0V

Leakage Current at Input (2)

Vin=OV

Zero Reading Drift

Vin=OV
O'C:S TA:S 70'C

= VRef.

Full Scale = 4.000V

.01

1

0.5

100

165

0.5

2

2

6-160
Note: All typical values have been guaranteed by characterization and are .not tested.

LSB
LSB

1

LSB

100

165

pA

0.5

2

p.V

2

p.V/·C

ICL8052/ICL7104
SYSTEM ELECTRICAL CHARACTERISTICS: ICL806817104 (CONT.)
8068A17104-16

8068A17104·14
CHARACTERISTICS

TEST CONDITIONS

UNIT
MIN

Yin ~ +4V
Scale Factor Temperature (3) Coefficient 0" TA" 50'C
(ext. ref. OppmrC

TYP

MAX

2

5

MIN

TYP

MAX

2

5

ppmrC

SYSTEM ELECTRICAL CHARACTERISTICS: ICL805217104 (V++ = +15V, v+ = +5V, v-

= -15V,

Clock Frequency = 200kHz)
8052A17104-14
CHARACTERISTICS

8052A17104·16
UNIT

TEST CONDITIONS
MIN

TYP

MAX

MIN

TYP

MAX

-0.0000

to.OOOO

+0.0000

-0.0000

to.OOOO

+0.0000

Hexadecimal
Reading

lFFF

2000

2001

7FFF

8000

8001

Hexadecimal
Reading

1

0.5

1

Zero Input Reading

Yin ~ O.OV
Full Scale

Ratiometric Reading (3)

Vin

Linearity over ± Full Scale (error of
reading from best straight line)

-4V" Vin" +4V

0.5

Differential Linearity (difference between
worst case step of adjacent counts and
ideal step)

-4V" Vin" +4V

.01

Rollover error (Difference in reading for
equal positive & negative voltage near
full scale)

- Yin

~

4.000V

= VRef.
Full Scale ~ 4.000V

~

0.5

+ Vin"'4V

.01

1

0.5

LSB
LSB

1

LSB

Noise (P-P value not exceeded 95% of
time)

Vin~OV

Leakage Current at Input (2)

Yin = OV

20

30

20

30

pA

Zero Reading Drift

Yin = OV
0'" TA" 70'C

0.5

2

0.5

2

/lVrC

Scale Factor Temperature Coefficient

Yin = +4V
0" TA" 70'C
(ext. ref. OppmrC

2

5

2

5

ppm/'C

Full scale

~

4.000V

30

/lV

30

NOTES: 1. Tested with low dielectric absorption integrating capacitor.

2. the input bias currents are junction leakage currents which approximately double for every 10'C increase in the junction temperature,
TJ. Due to limited production test time, the input bias currents are measured with junctions at ambient temperature. In normal
operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, Pd. TJ ~ T A + ROJAPd
where ROJA is the thermal resistance from junction to ambient. A heat sink can be used to reduce temperature rise.
3. The temperature range can be extended to 70'C and beyond if the Auto-Zero and Reference capacitors are increased to absorb the
high temperature leakage of the 8068. See note 2 above.

CONVEIIT
CONTROL

-

_AI

7104

-1.

!-:t='orCHtPSELICTI

' - - - 4 -......._ - ' - - _
CHIP IELaCT 1

AF027101

Figure 3: Full 18 Bit Three State Output

6-161
Note: All typical values have been guaranteed by characterization and are not tested.

I

ICL8052/ICL 7104

d

:::.
(II
10

o

a

- -... 011

011

POL

IOSW

IOSW

7104

POL

7104

...

COfITIIOL

COfITIIOL

011

POL

-.

IOSW

7104

o.ia

LCO07201

Figure 4: Various Combinations
of Byte Disables

AC CHARACTERISTICS

(V++

= +15V,

v+

= +5V,

v-

= -15V)

CElLO

AS INPUT
iII!fj

AS INPUT

IIlIER
AS INPUT
[DR

AS INPUT
HIGH BYTE
DATA

----------------------·~~-t-~~

~=~ BYTE ---------------------------<=)-------.---t.1~.i!i~)!
LOW BYTE

ENABLE

- - - - - - - = HIGH IMPEDANCE
WF013301

Figure 5: Direct Mode Timing Diagram

6-162
Note: All typical values have been guaranteed by characterization and are not tested. .

ICL8052/ICL 7104
Table 1: Direct Mode Timing Requirements (Note: Not tested in production)
SYMBOL

DESCRIPTION

MIN

TYP

tbea

XBEN Min. Pulse Width

300

Ictab

Data Access Time from XBEN

300

lethb

Data Hold Time from XBEN

200

tcea

CE/LD Min. Pulse Width

350
350

letae

Data Access Time from CEI LD

lethe

Data Hold Time from CE/LD

280

Icwh

CLOCK 1 High Time

1000

UNIT

MAX

ns

Table 2: Handshake Timing Requirements
NAME

DESCRIPTION

MIN

TYP

tmw

MODE Pulse (minimum)

20

tsm
t me

MODE pin set·up time

-150

MODE pin high to low Z CE/LD high delay

200

tmb

MODE pin high to

leel

CLOCK 1 high to CE/LD low delay

700

teeh

CLOCK 1 high to CE7iJ) high delay

600

X8E1ii low Z (high) delay

UNIT

MAX

200

lebl

CLOCK 1 high to XBEN low delay

900

Icbh

CLOCK 1 high to XBEN high delay

700

ledh

CLOCK 1 high to data enabled delay

1100

ledl

CLOCK 1 low to data disabled delay

1100

Iss

Send ENable set·up time

-350

lebz

CLOCK 1 high to XBEN disabled delay

2000

leez

CLOCK 1 high to CE/LD disabled delay

lewh

CLOCK 1 High Time

ns

2000
1250

1000

H

CLOCK 1 ( _ 25)

~

--

EITHER:
OR:

INTERNAL LATCH
PULSE IF MODE "HI",
INTERNAL MODE

UART

NOIIM-""""'-....L.-:--IJ

SEN
(EXTERNAL SIGNA~1

OJR.POL01·14

:--~~~~~:tr------~-------

H"'::l::;'-'---..:.::....;;;;~---.-~--.;.;;..\.
r.-':'l::-::r.:::
. '- _ _ _ _ _-1,... _ _.......1 .

..

~

lIlTS ''''

..... __.....

~..........4 -..........~..........__. . . .i._~~ «::~D~A~TA!!V~AU~D~.~S~TA8~;~~ ~

..........__..........

HAND8HAKEIIODETRIGGEREDBY__DR---14 BIT VERSION SHOWN

THIIEE-sTATE _

4 -.....4 - _

THREE-STATE W PULWP ....

-1. HAS EXTRA (iiiEij) PHASE
WF013411

Figure 6: Handshake Mode Timing Diagram

6-163
Note: All typical values have been guaranteed by characterization and are not tested,

: ICL8052/ICL7104
;::

g
......

I

Table 3: Pin Descriptions
PIN

SYMBOL

OPTION

V(++)

Positive Supply Voltage
Nominally + 15V

2

GND

Di~ital Ground .OV,
ground return

3

STTS

STaTuS output. HI during
Integrate and Deintegrate
until data is latched. LO
when analog section is in
Auto-Zero configuration.

4

POL

POLarity. Three-state
output. H I for positive
input.

5

OR

OverRange. Three-state
output.

6

BIT 16
BIT 14

-16
-14

7

BIT 15
BIT 13

-16
-14

8

BIT 14
BIT 12

-16
-14

9

BIT 13
BIT 11

-16
-14

10

BIT 12
BIT 10

-16
-14

11

BIT 11
BIT 9

-16
-14

12

BIT 10
nc

-16
-14

13

BIT 9
nc

-16
-14

14

BIT 8

15

BIT 7

16

BIT 6

17

BIT 5

18

BIT 4

PIN

DESCRIPTION

1

23

24
PIN

OPTION

DESCRIPTION

MBEN

SYMBOL

-16

HBEN

-14

Mid Byte §\jable.
Activates BITS 9-16, see
LBEN(pin 22)
High Eiyte ENable.
Activates BITS 9-14, POL,
OR, see LBEN (pin 22)

HBEN

-16

CLOCK3

-14

SYMBOL

DESCRIPTION

Clock input. External clock or ocsillator.

25

CLOCK1

26

CLOCK2

27

MODE

28

RIH

Run/Hoid: Input HI-conversion~
c?gtinously performed every 2 7(-16) or
2 (-14) clock pulses. Input LOconversion in progress completed,
converter will stop in Auto-Zero 7
counts before input integrate.

29

SEN

Send-ENable:, Input controls timing of
byte transmission in handshake mode.
HI indicates ·send'.

30

CElLO

'C:hip-E:nable/LoaD. With MODE (pin 27)
LO, CElLO serves as a master output
enable; when HI, the bit outputs and
POL, OR are disabled. With MODE HI,
pin serves as a Loal) strobe (-ve
going) used in handshake mode. See
Figures 12 & 13.

31

V(+)

Positive Logic Supply Voltage. Nominally
+5V.

32

'AN,IN

ANalog INput. High side.

33

BUF IN

BUFfer INput to analog chip (ICL8052
or ICL8068)

(Most significant bit)

Data Bits, Three-state
outputs. See Table 4 for
format of §\jables
and bytes.
HIGH = true

High Byte ENable.
Activates 'POL, OR, see
LBEN (pin 22).
RC oscillator pin. Can be
used as clock output.

Clock output. Crystal or RC oscillator.
!!!QullO; Direct output mode where
CElLO, HBEN, MBEN and LBEN act as
inputs directly controlling byte outputs. If
pulsed HI causes immediate entry into
handshake mode (sOe Figure ~
, If HI, enables CEIL , HBEN, MB N,
and LBEN as outputs. Handshake mode
will be entered and data output as in
Figures 12 & 13 at conversion
completion.

19

BIT 3

20

BIT 2

34

REFCAP2· REFerenCe CAPacitor (negative side)

21

BIT 1

Least significant bit.

35

AN.GND.

22

LBEN

Low Eiyte ENable. If not
in handshake mode (see
pin 27) when LO (with
c::E/[5, pin 30) activates
low-order byte outputs,
BITS 1-6
When in handshake
mode (see pin 27),
serves as a low-byte flag
output. See Figures 12,
13, 14.

36

A-Z

Auto-Zero node.

37

VREF

Voltage REFerence input (positive side).

ANalog GrouND. Input low side and
reference· low side.

36

REFCAP1

REFerence CAPacitor (positive side).

39

CaMP-IN

COMParator .INput from 8052/8068

40

V(-)

Negative Supply Voltage. Nominally
-15V.

6'-164
Note: All typical values have been guaranteed by characterization and are not tested,

.D~DIL

ICL8052/ICL7104

n
...

!

-e..

Table 4: Three-State Byte Formats
and ENable Pins

~

7104·16

i

7104·14

Figure 1 shows the functional block diagram of the
operating system. For a detailed explanation, refer to Figure
7 below.

o

Q
ZERO
CROSSING
F/F

CL

......k - 4 -... VREF
POL

CL
TC023811

Figure 7A: Phase I Auto-Zero

AN
liP

D

Q

ZERO
CROSSING

F/F

CL

POL

CL
TC02391 I

Figure 7B: Phase II Integrate Input
for - 16 and 32,368 for - 14 clock periods per cycle (see
Figure 9 conversion timing).
Auto-Zero Phase I Figure 7A
During Auto-Zero, the input of the buffer is shorted to
analog ground thru switch 2, and switch 1 closes a loop
around the integrator and comparator. The purpose of the
loop is to charge the Auto-Zero capacitor until the integrator
output no longer changes with time. Also, switches 4 and 9
recharge the reference capacitor to VREF.

DETAILED DESCRIPTION

Analog Section
Figure 7 shows the equivalent Circuit of the Analog
Section of both the ICL7104/8052 and the ICL7104/8068
in the 3 different phases of operation. If the Run/Hold pin is
left open or tied to V + , the system will perform conversions
at a rate determined by the clock frequency: 131,072
6-165

Nole: All typical values have been guaranteed by characterization and are not tested.

'~ ICL8052/ICL7104

!:i

sa

( 'II

1ft

a

D

Q

ZERO
CROSSING
'F/F
CL

POL

Figure 7C: Phase III

TC024011

+ Oeintegrate

o

Ci
-

Q
ZERO
CROSSING

F/F

6
7

9a,

CL

CL

+

POL

CREF

CL
TC024111

Figure 70: Phase III - Oeintegrate
established in Phase I. The, time, or number of counts,
required to do this is proportional to the input voltage. Since
the Deintegrate phase can be twice as long as the Input
integrate phase, the input voltage required to give a full
scale reading = 2VREF.

Input Integrate Phase II Figure 78
During input integrate the Auto-Zero loop is opened and
the analog input is connected to the buffer input thru switch
3. (The reference capacitor is still being charged to VREF
during this time.) If the input signal is zero, the buffer,
integrator and comparator will see the same voltage that
existed in the previous state (Auto-Zero). Thus the integrator output will no.tchange but will remain stationary during
the entire Input Integrate cycle. If VIN is not equal to zero,
an unbalanced condition exists compared to the Auto-Zero
phase, and the integrator will generate a ramp whose slope
is proportional to VIN. At the end of this phase, the sign of
the ramp is latched into the polarity F/F.

Note: Once a zero crossing is detected, the system automatically reverts
to Auto-Zero phase for the leftover Deintegrate time (unless Run/Hold is
manipulated" see RunlFiold Input in detailed description, digital section),

Buffer Gain
At the end of the auto-zero interval, the instantaneous
noise voltage on the auto-zero capacitor is stored, and
subtracts from the input voltage while adding to the
reference voltage during the next cycle. The result is that
this noise voltage effectively is somewhat greater than the
input noise voltage of the buffer itself during integration. By
introducing some voltage gain into the buffer, the effect of
the auto-zero noise (referred to the input) can be .reduced to
the level of the inherent buffer noise. This generally occurs,
with a buffer gain of between 3 and 10, ,Further increase in
buffer gain merely increases the total offset to be handled
by the auto-zero loop, and reduces the available buffer and
integrator swings, without improving the noise performance
of the, system. The circuit recommended for doing this with
the ICL8068/1CL7104 is shown in Figure 8. With careful
layout, the circuit shown can achieve effective input noise
voltages on the order of 1 to 2 /lV, allowing full 16-bit use

,Deintegrate Phase III Figure 7C & D
During the Deintegrate phase, the switch drive logic uses
the output of the polarity FIF in determining whether to
clOse switches 6 and 9 or 7 and B~ If the input Signal was
positive, switches 7 and 8 are closed and a voltage which is
VREF more negative than during Auto-Zero is impressed on
the buffer input. Negative inputs will cause + VREF to be
,applied to the buffer input via switches 6 and 9. Thus, the
reference capaCitor generates the equivalent ofa (+)
reference, or Ii (-) reference from the single reference
voltage with negligible error. The reference voltage returns
the output of the integrator to the zero-crossing point
6-166

Note: All typical values have been guaranteed by characterization and are. not tested ..

ICL8052/ICL7104
with full scale inputs of as low as 1S0mV. Note that at this
level, thermoelectric EMFs between PC boards, IC pins,
etc., due to local temperature changes can be very troublesome. For further discussion, see App. Note A030.

+15Y

-15V

rb-l

,,'

7

1

05016201

Figure 8: Adding Buffer Gain to ICL8068
Table 5: Typical Component Values (V ++

= + 1SV,

ICL8052/8068 WITH

ICL7104-16

= SV,

V+

V-

= -1SV,

Clock Freq

= 200kHz)

ICL7104-14

UNIT

200

800

4000

100

4000

mV

Buffer Gain

10

1

1

10

1

VIV

Full scale VIN

RINT

100

43

200

47

180

kf!

, CINT

.33

.33

.33

0.1

0.1

J1F

CAZ

1.0

1.0

1.0

1.0

1.0

J1F

Cref

10

1.0

1.0

10

1.0

J1F

VREF

100

400

2000

50

2000

mV

Resolution

3.1

12

61

6.1

244

J1V

POlARITY

D~
INTEGRATOR
OUTPUT

I

I

I.
I ,..

L-

ZERO CROSSING
OCCURS

I

~ /~ERO
CROSSING I
DETECTED
I

_ .1

I--AZ PHASE I--J--INT PHASE II

"l-/'

DEINT PHASE III--I--AZ-

INTERNAL CLOCK

h.r ~ J111I1.h.. J1Il11J1.r ~

INTERNAL LATCH

II

II

1
I
,•

h

I1

1

1

STATUS OUTPUT

I
I

1
1

1
1

I1

1

I
1

NUMBER OF COUNTS TO ZERO CROSSING!
PROPORTIONAL TO Y,N

'I

I

I

""AFTER ZERO CROSSING.
ANALOG SECTION WILL
BE IN AUTOZERO
CONFIGURATION
WF013501

COUNTS
PHASE I

PHASE II PHASE III

-115

32768

32768

65536

-14

8192

8192

16384

Figure 9: Conversion Timing

~167

Note: All typical values have been guaranteed by characterization and are not tested.

.D~DlL

3.... ICL8052/ICL7104
....

-

2 ICL8052 vs ICL8068
W
10

~

S:!

Note: When gain is used in the bUffer. amplifier the
reference capacitor shouldbe,l!ubstantially larger than the
auto-zero ,capacitor. As a. rule of thumb, the reference
capacitor should be approximately the gain times. the value
of the auto-zero capacitor. The dielectric absorption of the
reference cap and auto-zero cap are only important at
power-on or when the circuit is recovering from an overload.
Thus, smaller or cheaper caps can be used here if accurate
readings are not required for the first few seconds of
recovery.

The ICl8052 offers significantly lower input leakage
currents than the ICl8068, and may be found preferable in
systems with high input impedances. However, the ICl8068
has substantially lower noise voltage, and for systems
where system noise is a limiting factor, particularly in low
signal level conditions, will give better performance.

COMPONENT VALUE SELECTION
For optimum performance of the analog section, care
must be taken in the selection of values for the integrator
capacitor and resistor, auto-zero capacitor, reference voltage, and conversion rate. These values must be chosen to
suit the particular application.

Reference Voltage
The analog input required to generate a full scale output
is VIN = 2 VREF.
The stability of the. reference voltage is a major factor in
the overall absolute accuracy of the converter. The resolution of the ICl7104 at 16 bits is one part in 65536, or
15.26ppm. Thus, if the reference has a temperature coefficient of 50ppm/oC (on board reference) a temperature
change of 1 /3°C will introduce a one-bit absolute error.'For
this reason, it is recommended that an external high quality
reference be . used where the ambient temperature is not
controlled or where high-accuracy absolute measurements
are being made.

Integrating Resistor
The integrating resistor is determined by the full scale
input voltage and the output current of the buffer used to
charge the integrator capacitor. This current should be
small compared to the output short circuit current such that
thermal effects are kept to a minimum and linearity is not
affected. Values of 5 to 40J.LA give good results with a
nominal of 20IlA. The exact value may be chosen by
RINT =

DETAILED DESCRIPTION
Digital Section

full scale voltage"
20llA

The digital section includes the clock oscillator circuit, a
16 or 14 bit binary counter with output latches and TTlcompatible three-state output drivers, polarity, over-range
and control logic and UART handshake logic, as shown in
the Block Diagram Figure 10 (16 bit version shown).
Throughout this description, logic levels will be referred to
as "low" or "high": The actual logic levels are defined
under "ICl71 04 Electrical Characteristics". For minimum
power consumption, all inputs should swing from GND (low)
to V + (high). Inputs driven from TTL gates should have
3-5kn pullup resistors added for maximum noise immunity.

"Note: If gain is used in the buffer amplifier thenRINT =

(Buffer gain) (full scale voltage)
20J.LA

Integrating Capacitor
The product of integrating resistor and capacitor is
selected to give 9 volt swing for full scale inputs. This is a
compromise between possibly saturating the integrator (at
+ 14 volts) due to tolerance build-up between the resistor,
capacitor and clock and the errors a, lower voltage swing
could induce due to offsets referred to the output of the .
comparator. In general, the value of CINT is given by
[

MODE Input
The MODE input is used to control the output mode of
the converter. When the MODE pin is connected to GND or
left open (this input is provided with a pulldown resistor to
ensure a low level when the pin is left open), the converter
is in its "Direct" output mode, where the output data is
directly accessible under the control of the chip and byte
enable inp,uts. When the MODE input is pulsed high, the
converter enters the UART handshake mode and outputs
the data in three bytes for the 7104-16 or two bytes for the
7104-14 then returns to "direct" mode. When the MODE
input is left high, the converter will output data in the
handshake mode at the end of every conversion cycle. (See
section entitled "Handshake Mode" for further details).

(32768 for -16)] x 20J.LA x clock period
(8192 for -14)

CINT = - - - - - - - - - - - - - - - - Integrator Output Voltage Swing
A very important characteristic of the integrating capacitor
is that it have low dielectric absorption to prevent roll-over
or ratio metric errors. A good test for dielectric absorption is
to use the capacitor with the input tied to the reference.
This ratiometric condition should read half scale (100
. . . 000) and any deviation is probably due to dielectric
absorption. Polypropylene capacitors give undetectable
errors at reasonable cost. Polystyrene and polycarbonate
capacitors may also be used in less critical applications.

STaTuS Output
During a conversion cycle, the STaTuS output goes high
at the beginning of Input Integrate (Phase II), and goes low
one-half clock period after new data from the conversion
has been stored in the output latches. See Figure 9 for
details .of this timing. This signal may Qe used as a "data
valid" flag (data never changes while STaTuS is low) to
drive interrupts, or for monitoring the status of the converter.

Auto-Zero and Reference Capacitor
The size of the auto-zero capacitor has some influence
on the noise of the system, a large capacitor giving less
noise. The reference capacitor should be large enough
such that stray capacitance to ground from its nodes is
negligible.
6-168

Note: All typical values have been guaranteed by characterization and are not tested.

ICL8052/ICL 7104
eEim

RIER

LB!N

iiiim

7104-16 POL OIR B16 B15 B14 B13 B12 Bll Bl0 B9 B8

B7

B8 B5

B7

B6 B5

RIER
7104-14

B4

B3

B2

Bl

I:RN

POL OIR B14 B13 B12 Bll Bl0 B9

B8

B4 B3

B2 Bl

t--.-t-lI-$RIER
I

I

1ii8Eiii
I

(-16 only)

I
I

I
I
I

COMPOUT
TO AZ
ANALOG { INT
SECTION DEINT(+)
DEINT(-)

1-~-t-l1-$ 00iJ)

I

I
I

2.L ___ J
STaTuS

R/R

CLOCK CLOCK

1

2

CLOCK

MODE

SEND

3
LDO0641I

Figure 10: Digital Section

OPTION
MIN
MAX

INTEGRATOR

OUTPUT

INTERNAL CLOCK

::~1~==

-14
-16
7161 2866S
8185 32761

I

~ETECT~ON
I
~
I

~

I

I

~=-ASE I

I

STATICIN

I HOLD STATE

-'
I
l
1_ _ _
tr '11l.nfl... JU1ItI11lIt. ~
~ ~
I
I
I

INTERNAL LATCH _ _- - - - - - -_ _ _ _ _ _ _ _~n

I

STaTuS OUTPUT

....
...--------'-----------

RUN/HOLD INPUT -------.,i~-----

I

----~I-I
I

&..------1---i

LD006511

Figure 11: Run/Hold Operation
If Run/Hold goes low at any time during Deintegrate
(Phase III) after the zero crossing has occurred, the circuit
will immediately terminate Deintegrate and jump to AutoZero. This feature can be used to eliminate the time spent in
Deintegrate after the zero-crossing. If Run/Hold stays or
goes low, the converter will ensure a minimum Auto-Zero
time, and then wait in Auto-Zero until the Run/Hold input
goes high. The converter will begin the Integrate (Phase II)
portion of the next conversion (and the STaTuS output will
go high) seven clock periods after the high level is detected
at Run/Hold. See Figure 11 for details.

Run/Hold Input
When the Run/Hold input is connected to V + or left
open (this input has a pullup resistor to ensure a high level
when the pin is left open), the circuit will continuously
perform conversion cycles, updating the output latches at
the end of every Deintegrate (Phase III) portion of the
conversion cycle (See Figure 9). (See under "Handshake
Mode" for exception.) In this mode of operation, the
conversion cycle will be performed in 131,072 for 7104-16
and 32768 for 7104-14 clock periods, regardless of the
resulting value.
6-169

Note: All typical values have been guaranteed by characterization and are not tested.

.

! ICL805211CL7104
....
Using the Run/Hold input in this manner. allows an easy
d
::::. "convert on demand" interface to be used. The converter
'

CIt

I

conversion is completed) while MODE pin (pin 27) is high, in
which case entry occurs at the end of the latch cycle; or
secondly, if the MODE pin goes from low to high, when
entry will occur immediately (if new data is being latched,
entry is delayed to the end of the latch cycle). While in the
handShake mode, data latching is inhibited, and the MODE
pin is ignored. (Note that conversion cycles will continue in
the normal manner). This allows versatile initiation of
handshake operation without danger of false data generation; if the MODE pin is held high, every conversion (other
than those completed during handshake operations) will
start a new handshake operation, while if the, MODE pin is
pulsed high, handshake operations can be obtained "on
demand."

may be held at idle in Auto-Zero with RunlHold low. When
RunlHold goes high the conversion is started, and when
the STaTuS output goes low the new data is valid (or
transferred) to the UART - see Handshake Mode). Run/
Hold may now go low terminating Deintegrate and ensuring
a minimum Auto-Zero time before stopping to wait for the
next conversion. Alternately, RunlHold can be used to
minimize conversion time by ensuring that it goes low during
Deintegrate, after zero crossing, and goes high afte':...,the
hold point is reached. The required activity on the RunlHold
input can be provided by connecting it to the CLOCK3 (-14),
CLOCK2 (-16) Output. In this mode the conversion time is
dependent on the input value measured. Also refer to
Intersil Application Bulletin A030 for a discussion of the
effects this will have on Auto-Zero performance.
If the Run/Holdinput goes low and stays low during AutoZero (Phase I), the converter will simply stop at the end of
Auto-Zero and wait for Run/Hold to go high. As above,
Integrate (Phase II) begins seven qlock periods after the
high level is detected.

Direct Mode
When the MODE pin is left at a low level, the data outputs
[bits 1 through B low order byte, see Table 4 for format of
middle (-16) and high order bytes] are accessible under
control of the byte and chip ENable terminals as inputs.
These ENable inputs are all active low, and are provided
with pullup resistors to ensure an inactive high level when
left open. When the chip ENable input is low, taking a byte
ENable input low will allow the outputs of that byte to '
become active (three-stated on). This allows a variety of
parallel data accessing techniques
be used. The timing
requirements for these outputs are shown under AC Characteristics and Table 1.
It should be noted that these control inputs are asynchronous with respect to the converter clock - the data may be
accessed at any time. Thus it is possible to access the data
while it is being updated, which could lead to scrambled
data. Synchronizing the access of data with the conversion
cycle by monitoring the STaTuS output will prevent this.
Data is never updated while STaTuS is low. Also note the
potential bus conflict described under "Initial Clear
Circuitry" .

to

Handshake Mode
The handshake output mode is provided as an alternative
means of interfacing the ICL7104 to digital systems, where
the AID converter becomes active in controlling the flow of
data instead of passively responding to chip and byte
ENable inputs. This mode is specifically designed to allow a
direct interface between the ICL7104 and industry-standard
UARTs (such as the Intersil CMOS UARTs, IM640,2/3) with
no external logic required. When triggered into the handshake mode, the ICL7104 provides all the control and flag
signals necessary to sequence the three (ICL7106-16) or
two (ICL7104-14) bytes of data into the UART and initiate
their transmission in serial form. This greatly eases the task
and reduces the cost of designing remote data acquisition
stations using serial data transmission to minimize the
number of lines to the central contrOlling processor.
Entry into the handshake mode will occur if either of two
conditions are fulfilled; first" if new, data is latched (I.e. a

When the converter enters the handshake mode, or
when the MODE input is high, the chip and byte ENable
terminals become TTL-compatible outputs which provide
the control signals for the output cycle. The Send ENable
pin (SEN) (pin 29) is used as an indication of the ability of
the external device to receive data. The condition of the .line
is sensed once every clock pulse, and if it is high, the next
(or first) byte is enabled on the next rising CLOCK 1 (pin 25)
clock edge, the corresponding byte ENable line goes low,
and the Chip ENablelLoaD pin (pin 30) (CElLO) goes low
for one full clock pulse only, returning high.
On the next falling CLOCK 1 clock pulse edge, if SEN
remains high, or after it goes high again, the byte output
lines will be put in the high impedance state (or three-stated
Off). One half pulse later, the byte ENable pin will be cleared
~h, and (unless finished) the CElLO and the next byte
ENable pin will go low. This will continue until all three (2 111
the case of the 14 bit device) bytes have been sent. The
bytes are individually put into the low impedance state I.e.:
three-stated on during most of the time that their byte
ENable pin is (active) low. When receipt of toe last byte has
been acknowledged by a high SEN, the handshake mode
will be cleared, re-enabling data latching from conversions,
and recognizing the condition of the MODE pin again. The
!.:lyte and chip ENable will be three-stated off, if MODE is
low, but held high by their (weak) pull ups. These timing
relationships are illustrated in Figure 12, 13, and 14, and
Table 2.
Figure 12 shows the sequence of the output cycle with
SEN held high. The handshake mode (Internal MODE high)
is entered after the data latch pulse (since MODE remains
high the CElLO, LBEN, MBEN and HBEN terminals are
active as outputs). The high level at the SEN input is sensed
on the same high to low internal clock edge. On the next to
high interna,1 clock edge, the CElLO and the HBEN outputs
assume a low level and the high-order byte (POL and OR,
and except for -16, Bits 9-14) outputs are enabled. The
CElLO output remains low for one full internal clock period
only, the data outputs remain active for 1-112 internal clock
periods, and the high byte ENable remains low for two clock
periods. Thus the CElLO output low level or low to high
edge may be used as a synchronizing signal to ensure valid
data, and the byte ENable as an output may be used as a
byte identification flag. With SEN remaining high the converter completes the output cycle using CElLO, MBEN and
LBEN while the remaining byte outputs (see Table 4) are
activated. The handshake mode is terminated when all
bytes are sent (3 for -16, 2 for -14).

6-170

Note: All typical values have been guaranteed by characterization and are not' tested.

.•D~Dll

ICL8052/ICL7104

is

I

N
......
~/0CCUR8

INTEGRATOR

OUTPUT

INTERNAL
CLOCIC

INTERNAL

~~~~~~~rLI

LATCH

STATUS
OUTPUT

MODE
INPUT
INTERNAL
MODE

--

MODE HIGH ACTIVAlU

CIlmID. I11III. CBIJI

=.

i

.-_D~

/11

SBI.
INPUT

~

I\

~

1
HIGH BYTE
DATA

---------

J

I\.

\.

- --

f

1)--

J

~&
DI _
_ 12ItD

..

I/'
DATA VALlO

- L:
--r------..

-------

__ _RP.!!I!P.-I!.'!
I/'

LDWBYTE
DATA

-----------

~--

-------- --

DATA VALlO

DATA

-------------------------~----------~

_=DOHTCARE

1'-4 -4~-4_

------

~-.-

-- ----------- ------

,-----

~
LDWBYTE

s::

TERM.....lU

UAllTIIODE

DATA VALlO

---a_-STATE HIGH 1 _

~-~----I

-~-= _-BTATI WITH PULLUP
L0OO6601

Figure 12: Handshake with SEN Held. Positive

6-t7t
Note: All typical values have been guaranteed by characterization and are not tested.

e...2

.o~nlL

7104
;:3 ICL8052/ICL
,
d

i

a

.CLOCIC

LATCH

,v==-f'

I 'DJIOoCIIOI8INQ
DETICTED

n....r--t-r

..J iL r- ~f'1--.r1.,r ~

.

r

'

10-

~r ~

r-u-

ITAlUI

OUTPUT
MODe

INPUT

--

..

INTIIIIW. UART
1I0OI
_INPUT

(UAI\T T8III)

C::

2ltDOUTPUT

_BYTI
DATA

MIDDU!BYTI
DATA

LOWBYTI
DATA

[J':='

~

(UART T8IIL)

-------

~-.-

DATA VALID

------- ~- "'------~,...-

-------•

- ------..,10--

= DON'T CARl

~

,

1\

------ofl--- --

~.

.-

1\
DATAVAUD

------~,.-- ~- ~---..,.--

,

~- ------~,.--

...-

1\

-:- ------...,~-- fo--

-----IJ'

DATA VALID

~-

------

- - - = _-STATE HIGH I~
LO006701

Figure 13: Handshake - Typical UART Interface Timing
TBRE output will now go low, which halts the output cycle
with the HBEN output low, and the high order byte outputs
active. When the UART has transferred the data to the
Transmitter Register and cleared the Transmitter Buffer
Register, the TBRE returns high. On the next ICL7104
internal clock high to low edge, the high order byte outputs
are disabled, and one-half internal clock later, the HBEN
output returns high. At the same time, the CElLO and
MBEN (-16) or LBEN outputs go low, and the corresponding
byte outputs become active. Similarly, when the CElLO
returns high at the end of one clock period, the enabled
data is clocked into the UART Transmitter Buffer Register,
and TBRE again goes low. When TBRE returns to a high it
will be sensed on the next ICL7104 internal clock high to
low edge, disabling the data outputs. For the 16 bit device,
the sequence is repeated for LBEN. One-half internal clock
later, the handshake mode will be cleared, and the chip and
byte ENable terminals return high and stay active (/is long
as MODE stays high).

Figure 13 shows an output sequence where the SEN
input is used to delay portions of the sequence, or
handshake, to ensure correct data transfer. This timing
diagram shows the relationships that occur using an industry-standard IM6402/3 CMOS UART to interface to serial
data channels. In this interface, the SEN input to the
ICL7104 is driven by the TBRE (Transmitter Buffer Register
Empty) output of the UART, and the CElLO terminal of the
ICL7104 drives the TBRL (Transmitter Buffer Register
Load) input to the UART. The data outputs are paralleled
into the eight Transmitter Buffer Register inputs.
Assuming the UART Transmitter Buffer Register is empty, the SEN input will be high when the handshake mode is
entered after new data is stored. The CElLO and HSEN
terminals will go low after SEN is sensed, and the high order
byte outputs become active. When CElLO goes high at the
end of one clqck period, the high order byte data is clocked
into the UART Transmitter Buffer Register. The UART

&-172

Note: All typical values have been guaranteed by characterization and are not tested.

.D~D[b

ICL8052/ICL7104

E

-p
Ul

II)

.......

INTl!RNAL

i

CLOCK

INTERNAL
LATCH _ _....,.._--1~ ~_+-+

_____

~&.!~L..:&......i.~

..~~~~~-.-_-+-j---

'!~P.

STATUS
OUTPUT~
MODE

INPUT

=:':'==:;::1

INTERNAL
MODE ~=--+.f

SEN
INPUT

--illlllll---.. .

RIIIJij _ _ _ _ _

HIGH

g~!

r-- --+---11.

________

~ ~

-----t

1IlIDl _____ r---+-+----J---+-~
MIOOLE :~!

LOwg~!

________
________
•

= OON"T CARE

'----~I-~---f
~ ~-~--...,----

..,~-

...,--------.. .

~-...,---+----

- - - =THREE-STATE HIGH IMPEDANCE

-.&.- = THREE-STATE WITH PULLUP
LD0Q6801

Figure 14: Handshake Triggered By Mode
registers if the supply voltage "glitches" to a low enough
value. Additionally, if the supply voltage comes up too fast,
this clear pulse may be too narrow for reliable clearing. In
general, this is not a problem, but if the UART internal •
"MODE" F/F should come up set, the byte and chip
ENable lines will become active outputs. In many systems
•
this could lead to bus conflicts, especially in non-handshake
systems. In any case, SEN should be high (held high for
non-handshake systems) to ensure that the MODE F/F will
be cleared as fast as possible (see Figure 12 for timing). For
these and other reasons, adequate supply bypass is
recommended.

With the MODE input remaining high as in these examples, the converter will output the results of every conversion except those completed during a handshake operation.
By triggering the converter into handshake mode with a low
to high edge on the MODE input, handshake output
sequences may be performed on demand. Figure 14 shows
a handshake output sequence triggered by such an edge. In
addition, the SEN input is shown as being low when the
converter enters handshake mode. In this case, the whole
output sequence is controlled by the SEN input, and the
sequence for the first (high order) byte is similar to the
sequence for the other bytes. This diagram also shows the
output sequence taking longer than a conversion cycle.
Note that the converter still makes conversions, with the
STaTuS output and Run/Hold input functioning normally.
The only difference is that new data will not be latched
when in handshake mode, and is therefore lost.

Oscillator

Initial Clear Circuitry

The ICL7104-14 is provided with a versatile three termi"
nal oscillator to generate the internal clock. The oscillator
may be overdriven, or may be operated as an RC or crystal
oscillator.

The internal logic of the 7104 is supplied by an internal
regulator between V ++ and Digital Ground. The regulator
includes a low-voltage detector that will clear various
registers. This is intended to ensure that on initial power-up,
the control logic comes up in Auto-Zero, with the 2nd, 3rd,
and 4th MSB bits cleared, and the "mode" F/F cleared (Le.
in "direct" mode). This, however, will also clear these

Figure 15 shows the oscillator configured for RC operation. The internal clock will be of the same frequency and
phase as the voltage on the CLOCK 3 pin. The resistor and
capacitor should be connected as shown. The circuit will
oscillate at a frequency given by f = .45/RC. A 50-100kn
resistor is recommended for useful ranges of frequency. For
optimum 60Hz line rejection, the capacitor value should be
6-173

Note: All typical values have been guarante6d by characterization and are not tested.

.....z ICL80521lCL7104
....

g

chosen such that 32768 (-16), 8192 (-14) clock periods is
close to an integral multiple of the 60Hz. period.

ANALOG AND DIGITAL GROUNDS
Extreme care must be taken to avoid ground loops in the
layout of ICL8068 or ICL8052/7104 circuits, especially in
16-bit and high sensitivity circuits. It is most important that
return currents from digital loads are not fed into the analog
ground line. A recommended connection sequence for the
ground lines is shown in Figure 17.

C\II

I

APPLICATIONS INFORMATION
Some applications bulletins that may be found useful are
listed· here:
A016 "Selecting AID Converters", by Dave Fullagar
A017 "The Integrating AID Converter" , by Lee Evans
A018 "Do's and Dont's of Applying AID Converters", by
Peter Bradshaw and Skip Osgood
A02S "Building a Aemote Data Logging Station", by Peter
Bradshaw
A030 "The ICL71 04 - A Binary Output AID Converter for
Microprocessors", by Peter Bradshaw
ROOS "Interfacing Data Converter & Microprocessors", by
Peter Bradshaw et ai, Electronics, Dec. 9, 1976.

24
CLOCK

1

lose = .45/RC

Figure 15: RC Oscillator
Note that CLOCK 3 has the same output SUPPl.Y
RETURN

+>
..0...

DEVICE PIN

+5V SUPPLY BYPASS CAPACITOR(S)

06016301

Figure 17: Grounding Sequence

6-175
Note: All typical values have' been guaranteed by characterization and are not tested.

Section 7 -

Timer/Counter Circuits

PI

ICM7206
CMOS Touch-Tone Encoder
GENERAL DESCRIPTION

FEATURES

The Intersil ICM720S/ AlB/C/O are 2-of-8 sine wave
tone encoders for use in telephone dialing systems. Each
circuit contains a high frequency oscillator, two separate
programmable dividers, a 0/ A converter, and a high level
output driver.

•
•
•
•
•
•
•
•
•
•
•

Low Cost
Oscillator Uses 3.58MHz Color TV Crystal
High Current Bipolar Output Driver
Low Output Harmonic Distortion
Wide Operating Supply Voltage Range: 3 to 6
Volts
Uses 3 x 4 or 4 x 4 Single Contact Keypad
Low Power ( ::; 5.5mW With A 5.5V Supply)
Single and Dual Tone Capabilities
Multiple Key Lockout
Disable Output: Provides Output Switch Function
Whenever A Key Is Pressed
Custom Options Available

ORDERING INFORMATION
PART
NUMBER

TEMPERATURE
RANGE

PACKAGE

ICM72061PE

-40·C to + 85·C

16 Pin PLASTIC DIP

ICM7206AIPE

-40·C to +85·C

16 Pin PLASTIC DIP

ICM7206BIPE

-40·C to + 85·C

16 Pin PLASTIC DIP

ICM7206CIPE

-40·C to +85·C

16 Pin PLASTIC DIP

ICM7206DIPE

-40·C to + 85·C

16 Pin PLASTIC DIP

ICM7206/D

-40·C to + 85·C

DICE

ICM7206A/D

-40·C to +85·C

DICE

ICM7206B/D

-40·C to +85·C

DICE

ICM7206C/D

-40·C to +85·C

DICE

ICM7206D/D

-40·C to + 85·C

DICE

osc
osc
LPt

voo

lP2

OUTPUT

OUTPUT

ROWt

COlt

ROW 2

COL 2

ROW 3

COL 3

ROW 4

COl4

DISABLE

vss

OSCOUT
OSCIN
CD028111

DISABLE

D5024811

Figure 1: Functional Diagram

7-1
Note: All typical values have been guaranteed by characterization and are not tested.

Figure 2: Pin
Configuration
(Outline Dwg PEl

202100-002

PI

8ft ICM72()6
l"-

I

ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage VOO-VSS (Note 2) ...................... S.OV
Supply Current VSS (terminal 8) ........................ 25mA
Supply Curre'lt Voo (terminal 1S) ...................... 40mA
Disable Output Voltage (term. 7) ....... (Voo-SV) to Voo
Output Voltage (term 15) ..... (VSS-1.0V) to (VOO + 5.0V)
Input Voltage ....................... VSS - O.3V to Voo + O.3V

Output Current (terminal 15) ............................. 25mA
Power Dissipation ................................•........ 300mW
Operating Temperature Range ...... : .... -40°C to +85°C
Storage Temperature Range ............ - 55°C to + 125°C
Lead Temperature (Soldering, 10sec) ................. 300°C

NOTE 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2. The ICM7206 family has a zener diode connected between Voo and Vss having a breakdown voltage between 6.2 and 7.0 volts. If the currents into
terminals 8 and 16 are limited to 25 and 40mA maximum respectively. the supply voltage may be increased above 6 volts to zener voltage. With no
such current limiting, the supply voltage must not exceed 6 volts.

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: VOO = 5.5V, Test Circuit, Vss
SYMBOL

= OV

TA = 25°C unless otherwise specified.

PARAMETER

TEST CONDITIONS

100

Supply Current

Rl disconnected

VSUPPLY

Guaranteed Operating Supply Voltage Range
(Note 3)

-40·C" TA" +85·C

VOUT

THDI

UNIT

450

JJA

3.0

1000
6.0

V
C1, C2 disconnected - Low Band

0.90

1.15

vis

Peak to Peak Output Voltage

Rl = 1kn, no filtering - High Band

1.10

1.40

1.70

RMS Output Voltage

Rl = 1kn, fOUT = 697Hz

Rl = 1kn, fOUT = 1633Hz

Zo

MIN TYP MAX

Skew Between High and Low Band
Output Voltages

RL

Output Impedance

RL = lkn

Total Output Harmonic Distortion

= 1kn,

C2 Only

480

C1 to C2
No filtering

480

C1

490

C1 to C2

580

No filtering

655

490

mV

2.5

3.0

Operating

90

200

Quiescent

25

C1, C2 disconnected

Either Hi or Low Bands

Total Output Harmonic Distortion

VOH

Maximum Output Voltage Level

Val

Rl = lkn, C1 = .002"F
C2

= 0.02"F

20

25

2.3

10

%

fOUT= 697Hz
fOUT

= 1633Hz

1.0

Minimum Output Voltage Level

= lkn
Rl = lkn

0.5
35

10
4.6

RL

RIN

Keyboard Input Pullup Resistors

Terminals 3,4,5,6,11,12,13,14

CIN

Keyboard Input CapaCitance

Terminals 3,4,5,6,11,12,13,14

fose

Guaranteed Oscillator Fequency Range
(Note 4)

3" (VDO-VSS)" 6V

2.0

4.5

4V " (Voo - VSS) " 6V
ICM7206, ICM7206A

2.0

7

Guaranteed Oscillator Frequency Range
ton

System Startup Time on Application of Power
System Startup Time on Application of Power
and Key Depressed Simultaneously

ICM7206B, ICM7206C, ICM7206D

RO

DISABLE Output Saturation Resistance
(ON STATE)

See Logic Table for Input Conditions
Current=4mA

IOlK

DISABLE Output Leakage
(OFF STATE)

See Logic Table for Input Conditions

OsCillator Load CapaCitance

Measured between terminals 9 & 10,
no supply voltage applied to circuit
-40·C" TA" 85·C

Cose

7-2
Note: All typical values have been guaranteed by characterization and are not tasted.

n
kn

No Low Pass Filtering
THD2

dB

100

V

150

kn

5

pF
MHz

10

330

7

7

ms

700

n

10

JJA
pF

ICM7206

n
a:::

ELECTRICAL CHARACTERISTICS (CO NT.)

o

SYMBOL

...
N

PARAMETER

TEST CONDITIONS

fO

Guaranteed Output Frequency Tolerance

Any output frequency
Crystal tolerance ± 60ppm
Crystal load capacitance CL = 30pF

tstart

Oscillator Startup Time ICM7206B,C,D

Voo - VSS

= 3V

MIN TYP MAX

(Note 5)

UNIT

±0.75

%

7

ms

Gl

NOTES: 3. Operation above 6 volts must employ supply current limiting. Refer to 'ABSOLUTE MAXIMUM RATINGS' and the Application Notes
for further information.
4. The ICM7206 family uses dynamic high frequency circuitry in the initial 23 divider resulting in low power dissipation and excellent
performance over a restricted frequency range. Thus, for reliable operation with a 6 volt supply an oscillator frequency of not less
than 2M Hz must be used.
5. After row input is enabled.

TRUTH TABLE
ROWS(1)
LINE ACTIVATED
1

0

2
3

OUTPUT
(TERMINAL # 15)

COLS(2) ACTIVATED

DISABLE
(TERMINAL #7)

COMMENTS

0

Off

Off

1

1

frow +fcol

On

Dual Tone

1

2 or 3 (incl. col #4)

frow

On

Single Tone
Single Tone

Quiescent State

4

2 or 3

1

2 or 3

2 or 3 (excl. col #3)

fcol
D.C. Level

On

5

On

No Tone

6

1

4 or 3 (must excl. col #4)

f row, 50% Duty Cycie

f row , 50% Duty Cycle

frow Test

7

4

1

fcoh 50% Duty Cycle

fcoh 50% Duty Cycle

leol Test

8

0

lor2or30r4

Off

Off

n/a*

9

1

0

On

nJa*

10

2 or 3

0

902Hz + f row
902Hz

On

n/a*

11

4

0

902Hz,. 50% Duty Cycle

902Hz, 50% Duty Cycle

n/a"

12

20r30r4

4

D.C. Level

Indeterminate

Multiple Key Lockout

13

4

20r30r4

D.C. Level

Indeterminate

Multiple Key Lockout

"n/a - not applocable to telephone callong.
NOTES:
1. Rows are activated for the ICM7206/C by connecting to a negative supply voltage with respect to Voo (terminal 16) at least 33% of the value
of the supply voltage (Voo-VSS). For the ICM7206A rows (and columns) are activated by connecting to a positive supply voltage with respect
to VSS (terminal B) at least 33% of the value of the supply voltage WOO - Vss). The rows "nd columns 01 the ICM7206B are activated by
'
connecting to a negative supply v6ltage.
2. Columns (ICM7206) are activated by being connected to a positive supply voltage with respect to VSS (terminal 8) at least 33% 01 the value 01
the supply voltage (Voo - VSS).

OPTIONS

COMMENTS

(For additional information consult the
factory)

All combinations of row and column activations are given
in the truth table. Lines 1 through 7 and 12, 13 represent
conditions obtainable with a matrix keyboard. Lines 8 thru
11 are given only for completeness and are not pertinent to
telephone dialing.
Lines 6 and 7' show conditions for generating 50% duty
cycle full amplitude Signals useful for rapid testing of' the
row and column frequencies on automatic test equipment.
In all other cases, output frequencies on terminal 15 are
single or dual 4 level synthesized sine waves.
A 'DC LEVEL' on terminal 15 may be any voltage level
between approximately 1.2 and 4.3 volts with respect to
VSS (terminal 8) for a 5.5 volt supply voltage.
The impedance of the OUTPUT (terminal 15) is approximately 20k ohms in the OFF state. The 'DISABLE OUTOUT ON and OFF conditions are defined in the TYPICAL
PERFORMANCE CHARACTERISTICS.

Options can be achieved using metal mask additions to
provide the following.
1) The sequence or position of either the row or
column terminals can be interchanged i.e., row 1
terminal 3 could become terminal 11, etc.
2) Any frequency oscillator from approximately 0.5MHz
to 7MHz can be chosen. Note that the accuracy of
the output frequencies will depend on the exact
oscillator frequency. For instance, a 1MHz crystal
could be used with worst case output frequency
error of 0.8%. Or, if high accuracy is required,
±0.25%, oscillator frequencies of 5,117,376Hz or
2,558,688Hz could be selected. ROM's are used to
program the dividers.
3) The 'DISABLE' output may be changed to an
inverter or an uncommitted drain n-channel
transistor.
4) The oscillator may be disabled until a key is
depressed.

7-3
Note: All typical values have been guaranteed by characterization and are not tested.

fII

§

...

.D~DIb

ICM7206

I

C2
(O.02:1,.FI

ROW.

OUTPUT

,.
Rl
ROW2

12
-5.5V

11

ROW 3

ROW.
QUARTZ CRYSTAL PARAMETERS
f
• 3,579.546 Hz

COL 1

COL 2

COL 3

RS": 109H
CM= 200mpf

-s.SV

COL 4

Co .. 4.6 pF
Cl "'30pF

TC031201

Figure 3: Test Circuit (single contact keyboard devices shown)

TYPICAL PERFORMANCE CHARACTERISTICS
SUPPLY CURRENT AS A FUNCTION OF SUPPLY
VOLTAGE

TOTAL HARMONIC DISTORTION AS A FUNCTION
OF LOAD RESISTANCE
16

~
Z
0

;:

a:

0

t;

15
u

Z

0

..
......
:;;

a:
X

-'
0

....
LOAD RESISTANCE (!l)
SUPPl Y VOL TAGE (VDD -

V.s)

0P048eOI

0P048421

7-4
Note: All typical values have been guaranteed by characterization and are not tested.

ICM7206
TYPICAL PERFORMANCE CHARACTERISTICS (CONT.)
OSCILLATOR FREQUENCY DEVIATION AS A
FUNCTION OF SUPPLY VOLTAGE
+1.5

1+

PEAK TO PEAK OUTPUT VOLTAGE AS A
FUNCTION OF SUPPLY VOLTAGE

U5,..---,---,--.,.---,-...,....----,

,..-----r-...,....-.,.....-~_n..__,

TA' 25 C
C~YSTAl

1.0

z

PARAMETERS:

f

'" 3,579,545 Hz

RS

"45~!

t--1Ii----l

1

eM = 20mpF

Q +0.5

~ 1.251----+--+--+_---..~-A--_l
~

Co = 4.5 pF

~

I

~
c

!:i

g

a:

o
~

-0.5

~

-1.0

1.5

1.0

>-

~ O.751----+---h~If---~--+-_l

>-

o" 0.5 1----+~.*-+_--1-----+-_l

t----t---.II'-'--+_-i----+-_l

·1.5 L-.....J.L--'-_..L-_L-.....L_.J
1

SUPPL V VOL TAGE

SUPPL V VOLTAGE
OP048501

!-

KEY
STANDARD TELEPHONE
KEYBOARD
COL 1

ROW 1

ROW 2

ROW 3

ROW 4

OP048701

COL 2

COL 3

1
2
3
4
5
6
7
8
9

COL 4

D 8 D [J
D D 8 G
D 8 [J G
D c:J D G

.
0

#

;

!••- - - - - F U L L

A

KEYBOARD----~.I!

B

C

SC011001

D

LOW BAND
FREQ. Hz

HI BAND
FREQ. Hz

697
697
697
770
770
770
852
852
852
941
941
941
697
770
852
941

1209
1336
1477
1209
1336
1477
1209
1336
1477
1209
1336
1477
1633
1633
1633
1633

Figure 4: Keyboard Frequencies
approximately --3dBV into a 900 ohm termination. The
skew between the high and low groups is typically 2 ..5 dB
without low pass filtering.
The 7206 uses either a 3 x 4 or 4 x 4 single contact
keyboard; the oscillator will run whenever the power is
applied, and the DISABLE output consists of a p-channel
open drain FET whose source is connected to VDD.
The 7206A can also use a 3 x 4 or 4 x 4 keyboard, but
requires a double contact type with the common line tied to
VDD. The oscillator will be on whenever power is applied;
the DISABLE output consists of a p-channel open drain
FET; its source is connected to VDD.
The 7206B requires a 4 + 4 double contact keyboard with
the common line tied to VSS. The oscillator will be on only
during the time that a ROW is enabled, and the DISABLE

DETAILED DESCRIPTION
The reference frequency is generated from a fully integrated oscillator requiring only a 3.58MHz color TV crystal.
This frequency is divided by 8 and is then gated into two
divide by N counters (possible division ratios 1 through 128)
which provide the correct division ratios for the upper and
lower band of frequencies. The outputs from these two
divide by N counters are further divided by 8 to provide the
time sequencing for a 4 voltage level synthesis of each
sinewave. Both sinewaves are added and buffered to a high
current output driver, with provisions made for up to two
external capacitors for low pass filtering, if desired. Typically, the total output harmonic distortion is 20% with no L.P.
filtering and it may be reduced to typically less than 5% with
filtering. The output drive level of the tone pairs will be
7--5

Note: All typical values have been guaranteed by characterizatibn and are not tested.

81CM7206

...

til

I

output consists of an n-channel open drain FET with its
source tied to VSS.
The 7206e uses either a 3 x 4 or 4 x 4 single contact
keyboard; the oscillator will be on o(1ly during the time that a
key is depressed. The DISABLE output consists of an nchannel open drain FET with its source tied to VSS.
The 72060 uses a single .contact 3 x 4 or 4 x 4 keyboard.
The oscillator will be on only during the time that a key is
depressed. DISABLE output consists of a p-channel open
drain FET with its source tied to VOO.

I4pF

OSC IN

<>---+-...,

Figure 6 shows individual currents of a low band and high
band frequency pair into the summing node A (see Figure 7)
and the resul.tant voltage waveform.

DESIRED
FREQUENCY
Hz

14pF

f------....-----1f---- TO-8

FREQUENCY
ACtUAL
FREQUENCY DEVIATION DIVIDE BY N
Hz
%
RATIO

697

699.13

+0.30

770

766.17

-0.50

73

852

847.43

-0.54

66

941

947.97

+0.74

59

1209

1215.88

+0.57

46

1336

1331.68

-0.32

42

1477

1471.85

-0.35

38

1633

1645.01

+0.74

34

O~OUT<>-------------J

0$024701

Figure 5: Schematic Diagram
ICM7206 Oscillator

2.4141

~
l

LOW BAND
SIGNAL

LHI BAND
SIGNAL

-T

HIGH AND LOW

APPROX
2.6Vp-p

_1

FREOUENCI ES
COMBINED

APPROX. 1.2V

REFERRED TO VWF021501

Figure 6

.7-6
Note: All typical values have been guaranteed by characterization and lire not tested.

80

.O~OlL

ICM7206

peak of O.4dB occurs at 1100Hz with sharp attention (12dB
per octave) above 2500Hz. This type of active filter
produces a sharper and more desirable knee characteristic
than would two simple cascaded RC networks.

APPLICATION NOTES

Device Description
The ICM7206 family is manufactured with a standard
metal gate CMOS technology having proven reliability and
excellent reproducability resulting in extremely high yields.
The techniques used in the design have been developed
over many years and are characterized by wide operating
supply voltage ranges and low power dissipation.

r--------------.----.-------------~-QV~

,------t-_QLP 2

To minimize chip size, all diffusions used to define
source-drain regions and field regions are butted up together. This results in approximately 6.3 volt zener breakdown
between the supply terminals, and between ali components
on chip. As a consequence, the usual CMOS static charge
problems and handling problems are not experienced with
the ICM7206.

"'<>_--0 OUT

~~~~--------_oLPl

The oscillator consists of a medium size CMOS inverter
having on chip a feedback resistor and two capacitors of
14pF each, one at the oscillator input and the other at the
oscillator output. The oscillator is followed by a dynamic .;23 circuit which divides the oscillator frequency to 447,
443Hz. This is applied to two programmable dividers each
capable of division ratios of any integer between 1 and 128,
and each counter is controlled by a ROM. The outputs from
the programmable counters drive sequencers (divide by 8)
which generate the eight time slots necessary to synthesize
the 4-level sine waves.

~----~-------4----~--------------__oVSS

09024911

Figure 7

TIME - - - -

voo

The control logic block recognizes signals on the row and
column inputs that are only a small fraction of the supply
voltage, thereby permitting the use of a simple matrix single
contact per key keyboard, rather than the more usual two
contacts per key type having a common line. The row and
column pullup resistors are equal in value and connected to
the opposite supply terminals (lCM7206/C only; for the
ICM7206A all pullup resistors are connected to the VSS
terminal and for the ICM7206B they are tied to the VOO.
Therefore, connecting a row input to a column input
generates a voltage on those inputs which is one half of the
supply voltage.

I
I
I
I
1121314,5,617181

OUTPUT WAVEFORM
WF02141t

The ICM7206 family employs a unique but extremely
simple digital to analog (D to A) converter. This D to A
converter produces a 4 level synthesized sine wave having
an intrinsic total harmonic distortion level of approximately
20%. Figure 8 shows a single channel D to A converter. The
current sources 02 and 03 are proportioned in the ratio of
1:1.414. During time slots 1 and 8 both S1 and S2 are off,
during time slots 2 and 7 only S1 is on, during time slots 3
and 6 only S2 is on, and during time slots 4 and 5 both S1
and S2 are on. The resultant currents are summed at node
A, buffered by 04 and further buffered by R3, R4 and 05.
Switch S3 allows the output to go into a high impedance
mode under quiescent conditions.

Figure 8: 0 to A Converter and Output Buffer

lsao
1400
1300

+25°C

A

.. 1200
1100
1000

.s.

i=

5! 800
~ 800

~

700
~800

VOD :;; 16V

ffisao

-

g400
i<300

Node A is the common summing point for both the high
and low band frequencies although this is not shown in
Figure 8.

....

100

r- t~r

o
o

The synthesized sine wave has negligible even harmonic
distortion and very low values of third and fifth harmonic
distortion thereby minimizing the filtering problems necessary to reduce the total harmonic distortion to well below
the 10% level required for touch tone telephone encoding.
Figure 9 shows the low pass filter characteristic of the
output buffer for C1 = 0.0022J..1F and C2 = 0.022J..1F. A small

VD D -

1

5V

~
~

.v..l!.

2

3

4

5

8

7

8

9

10

TRIGGER AMPLITUDE (VOLTS)
OP04881I

Figure 9: Frequency Attentuation
Characteristics of the Output Buffer

7-7
Note: All typical values have been guaranteed by characterization and are not tested.

a...

I

:§
....2
!:!

ICM7206 "
C~msiderations
Most jllnction isolated CMOS integrated circuits, especially those of moderate.or high complexity, exhibit latchup
phenomena whereby they can be triggered into an uncontrollable. low impedance. mode between the supply terminals. This can be due to gross forward biasing of inputs or
outputs (with respect to the supply terminals), high voltage
supply transients, or more rarely by exceptional fast rate of
rise of supply voltages.

4ltchup

prevents the output going more than 1 volt negative with
respect to the negative supply VSS and the circuit operates
over the supply voltage range from 3.5 volts to 15 volts on
the device side of the bridge rectifier. Transients as high as
100 volts will not cause system failure, although the
encoder will not operate correctly under these conditions.
Correct operation will. resume immediately after the transient is removed.
The output voltage of the synthesized sine wave is
almost directly proportiqnal to the supply voltage
(VDo-VSS) and will increase with increase of supply voltage
until zener breakdown occurs (approximately 6.3. volts
between terminals 8 and 16) after which the output voltage
remains constant.

The ICM7206 family is no exception, and precautions
must b!9 taken to limit the supply current to those values
shown in the ABSOLUTE MAXIMUM RATINGS. For an
example, do not use a 6 volt very low impedance supply
source in an extremely electrically noisy environment
unless a 5000hm current I.imiting resistor' is included in
series with the Vss terminal. For normal telephone encoding applications no problems are envisioned, even with low
impedance transients of 100 volts or more, if circuitry similar
to that shown in the next section is used;

Portable Tone Generator
The ICM7206A1B require a two contact key keyboard
with the common line connected to the positive supply (neg
for ICM7206B) (terminal 16). A simple diode matrix may be
used with this keyboard to provide power to the system
whenever a key is depressed, thus avoiding the need for an
on/off switch. In Figure 11 the tone generator is shown
using a 9 volt battery. However, if instead, a 6 volt battery is
used, the diode D4 is not required. It is recommended th~t a
4700hm resistor still be included in series with a negative
(positive) supply to prevent accidental triggering of latchup.

Telephone Handset
A typical encoder for telephone handsets is shown in
Figure 10. This encoder uses a single contact per key
keyboard and provides all other switching functions electronically. The diode-connected between terminals 8 and 15

Ra

(i)®@
@®@
o---J

MULTIPLEX

OUTPUT

!VDD
~

Vss "Full ,......... on .eM 72!J7A

~:~L.~ '-~
R"ET~'

__________~
80006121

Figure 2: Functional Diagram

202200-002

7-10
Note: All typical values have been guaranteed by characterization and are

n~t

tested.

n

ICM72071A

...
...
.......

I:
N

o

ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VDD - Vss) ................................ 6.0V
Input Voltages ..................... VSS - 0.3V to VDD + 0.3V
Output Voltages:
7207 .......................................... VSS to + 6V
7207A ......................................... VDD to VSS

Output Currents .............................................. 25mA
Power Dissipation @ 25°C Note 1 ................... 200mW
Operating Temperature Range ........... -20°C to +85°C
Storage Temperature Range ............ -55°C to + 125°C
Lead Temperature (Soldering, 10sec) ................. 300°C

~

NOTE 1: Derate by 2mWrC above 25°C.
Absolute maximum ratings refer to values which if exceeded may permanently change or destroy the device. Stresses above those listed under Absolute
Maximum Ratings may cause permanent damage to the device. These are stress ratings only. and functional operation of the device at these or any other
conditions above those indicated in the operation~1 sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
fosc = 6.5536MHz(7207), 5.24288MHz(7207A), VDD = 5V, TA = 25°C, VSS = OV, test circuit unless otherwise specified.
SYMBOL

PARAMETER

TEST CONDITIONS

+ 85°C

Voo

Operating Voltage Range

- 20°C to

100

Supply Current

All outputs open circuit

Rds(on)

Output on Resistances

Output current = SmA
All outputs

10lK

Output Leakage Currents

All outputs (STORE only)

(ROUT)

(Output Resistance
Terminals 12,13,14)

Output current - 50llA, 7207A
only

Ipd

Input Pulldown Current

Terminal 11 connected to VOO

fosc

Oscillator Frequency Range

Note 2

fSTAB

Oscillator Stability

CIN = GoUT = 22pF

rose

Oscillator Feedback
Resistance

Quartz crystal open circuit
Note 3

Input Noise Immunity

MIN

TYP

MAX

V

260

1000

/JA

50

120

n

50

/J A

50

33K

n

200

/JA
% supply voltage

25
2
0.2

3

UNIT

5.5

4

10

MHz

1.0

ppmlV
Mn

NOTES: 2. Dynamic dividers are used in the initial stages of the divider chain. These dividers have a lower frequency of operation determined by
transistor sizes, threshold voltages and leakage currents.
3. The feedback resistor has a non-linear value determined by the oscillator instantaneous input and output voltage voltages and the
supply voltage.

PI

7-11
Note: All typical values have been guaranteed by

character:~ation

and are not tested.

oC
...,.,

S
ell

IC1Vl7207/A

...

•2

CRYSTAL PARAMETERS

!

CtN - <:OUT - 22pF

I

J

1C1I7207
f-6.5631MHz

"'-401)

C,-IS"",F
Co-UpF

ICM7207A

Y

f • 6.24211MHa

'" < 75Il
Co
- 4pF
Coo - IZmpF
CL - 12pF

5CIk'

10k

5CIk'

5CIk'

01--.-----11]
+

TC027401

SWITCHES S,. S2. Sa. S4 OPEN CIRCUIT FOR SUPPLY CURRENT MEASUREMENT.
SWITCH S5 OPEN CIRCUIT FOR SLOW GATING PERIOD.
t SWITCHES S2. Sa. S4 and SDk RESISTORS ARE NOT NEEDED WHEN USING THE ICM72D7A.

Figure 3: Test Circuit

TYPICAL PERFORMANCE CHARACTERISTICS
SUPPLY CURRENT AS A FUNCTION OF
OSCILLATOR FREQUENCY
300

TA-250 C

250

~iu-m5~.lny au.,.. Cry.....

OUTPUT SATURATION RESISTANCES AS A
FUNCTION OF SUPPLY VOLTAGE

1,'"

~ 3OO~--+---+---f70r'12MHz

5
a>
I

'"
150

~
II<

t

~

.,
.... \.
~

100

1:
\

COUT " IOpF
C.N • 10pF

6.5 MHz

,
CoUT"IOpF
3.3 MHz CIN " IOpF
CoUT - 22pF
2 MHz CIN' 22pF

r

--+--1

~CoUT·22pF----~--~--~~

CIN- 22pF
O~3--~--4~-J--_.L.--~--J

o

8
10
OSCILLATOR FREQUENCY MHz

12

SUPPLY VOLTAGE
OP038901

0P03881 I

7-12
Note: All typical values have been guaranteed by characterization and are not tested.

.n~nll

ICM7207/A
TYPICAL PERFORMANCE CHARACTERISTICS (CONT.)
OSCILLATOR STABILITY AS A FUNCTION OF
SUPPLY VOLTAGE

I\,)

SUPPLY CURRENT AS A FUNCTION OF SUPPLY
VOLTAGE
600
TA

E

...

I

>

..

:::;

III

2S0C

I

500 lose .. 6.5 MHz

It +0.51-"=r-=-:;::-:::-t0.0

CaUT' 22pF
CIN" 22pF ,

I

i

!----t:-7''tJ-iIi'f-+--!f----j

;

/

300

e -1.0~---¥:,..q

200

~ -1.S 17'--'1--->--+--+--+---1

100

j

,i

•

i

!
-0.5

o
....
.....

I i
,

ii

~
a:

i....

/

I
~
I I I
!

./
o "

-,z.03
L --"'-------.l.--'---'-----.JS'--.-L---.J

3

•
5
SUPPL V VO!- TAGE

SUPPLY VOLTAGE
0P039001

OP039101

OUTPUT TIMING WAVEFORMS 7207 (7207A)
Crystal Frequency 6.5536(5.24288)MHz

=

1

~Hz or ~I (, ~H.t

1-=-1
MULTIPLIXOUTPOT

.

~----JLrl----JLQ
1

GATINGOUTPUT

or 18t,...)

20 .. 200...

~----lj200or2000mS)

·1

I

-L--...,.--- -~_10 or 100 (100 or 1000) m,

.----lj

----, 1"'---ffiiiiE

U

'----~

WF016801

Figure 4: Output Waveform

DETAILED DESCRIPTION

If a very high quality oscillator is desired, it is recommended that a quartz crystal be used having a tight tuning
tolerance ± 1Oppm, a low series resistance (less than 2Sn),
a low motional capacitance of SmpF and a load capacitance of 20pF. The fixed capacitor CIN should be 39pF and
the oscillator tuning capaCitor should range between approximately 8 and 60pF.

Referring to the Test Circui~ Figure 3, the crystal oscillator
frequency is divided by 21 to provide both the multiplex
frequency and generate the output pulse widths. The
GATING OUTPUT provides a SO% duty cycle signal whose
period depends upon whether the RANGE CONTROL
terminal is connected to VOO or VSS (open circuit).

OSCILLATOR CONSIDERATIONS

Use of a high quality crystal will result in typical oscillator
stabilities of O.OSppm per 0.1 volt change of supply voltage.

The oscillator consists of a CMOS inverter with a nonlinear resistor connected between the input and output
terminals to provide biasing. Oscillator stabilities of approximately 0.1 ppm per 0.1 volt change are achievable at a
supply voltage of S volts, using low cost crystals. The crystal
specifications are shown in the TEST CIRCUIT.

FREQUENCY LIMITATIONS
The ICM7207 / A uses dynamiC frequency counters in the
initial divider sections. Dynamic frequency counters are
faster and consume less power than static dividers but
suffer from the disadvantage that there is a minimum
operating frequency at a given supply voltage.

It is recommended that the crystal load capaCitance (CLl
be no greater than 1SpF for a crystal having a series
resistance equal to or less than 7Sn, otherwise the output
amplitude of the oscillator may be too low to. drive the
divider reliably.
7-13

Note: All typical values have been guaranteed by characterization and are not tested.

PI

ICM72c)1l4
APPLICATION
A PRACTICAL FREQUENCY COUNTER
A complete frequency counter using the ICM7207 I A
together with the ICM7208 Frequency Counter is described
in the ICM7208 data sheet. Other frequency counters using
the ICM7207 I A can be constructed using the ICM7224,
ICM7225, and ICM7236, for LCD, LED and VF displays. The
latter are available as EVIKits also.

SUPPLY
VOLTAGE 3
WINDOW 2

1OKH,

100KHz

1MHz

tOMHz

FREQUENCY'
sc009301

QUARTZ CRYSTAL MANUFACTURERS

Figure 5

The following list of possible suppliers is intended to be of
assistance in putting a design into production. It should not
be interpreted as a comprehensive list of suppliers, nor
does it constitute an endorsement by Intersi!.
a) CTS Knights, Sandwich, Illinois, (815) 786-8411
b) Motorola Inc., Franklin Park, Illinois (312) 451-1000
c) Sentry Manufacturing Co., Chickasaw, Oklahoma
(405) 224-6780
d) Tyco Filters Division, Phoenix, Arizona (602) 272".
7945
e) M-Tron Inds., Yankton, South Dakota (605) 6659321
f)
Saronix, Palo Alto, California (415) 856-6900

For example, if .instead of 6.5MHz, a 1MHz oscillator is
required, it is recommended that the supply voltage be
re~uced to between 2 and 2.5 volts. This may be realized by
~slng a series resistor in series with the 5V positive supply
hne plus a decoupling capacitor. The quartz crystal parameters, etc., will determine the value ofthis resistor. NOTE:
Except for the output open drain n-channel transistors no
other terminal is permitted to exceed the supply voltage
limits.

7-14
Note: All typical values have been guaranteed by characterization and are not te~ted.

ICM7208
7-Digit LED Display Counter
GENERAL DESCRIPTION

FEATURES

The ICM7208 is a fully integrated seven decade counterdecoder-driver and is manufactured using Intersil's low
voltage metal gate C-MOS process.
Specifically the ICM7208 provides the following on chip
functiohs: a 7 decade counter, multiplexer, 7 segment
decoder, digit & segment driver, plus additional logic for
display blanking, reset, input inhibit, and display on/off.
For unit counter applications the only additional components are a 7 digit common cathode display, 3 resistors and
a capacitor to generate the multiplex frequency reference,
and the control switches.
The ICM7208 is intended to operate over a suppJy
voltage of 2 to 6 volts as a medium speed counter, or over a
more restricted voltage range for high frequencyapplications.
As a frequency counter it is recommended that the
ICM7208 be used in conjunction with the ICM7207 Oscillator Controller, which provides a stable HF OSCillator, and
output signal gating.

• Low Operating Power Dissipation < 10mW
• Low Quiescent Power Dissipation < SmW
• Counts and DisplaYs 7 Decades
• ',Wide Operating Supply Voltage Range
2V::; Voo::; 6V
• Drives Directly 7 Oecade 'Multiplexed Common
,
Cathode LED pisplay
• Internal Store Capability
• Internal Inhibi,t to Counter Input
• Test Speedup Point

ORDERING INFORMATION
PART NUMBER

TEMPERATURE
RANGE

PACKAGE

ICM72081PI

-20°C to +85°C

28 Lead
Plastic DIP

ICM72081JI

-20°C to +85°C

28 Lead
CERDIP

ICM7208/D

DICE

C0021111

80006221

Figure 1: Functional Diagram

7-15
Note: All typical values have been guaranteed by characterization and are ,not tested;

Figure 2: Pin Configuration
(Outline Drawing PI)

-002

!('\I Ie,M7208

...

I

ABSOLUTE MAXIMUM RATINGS
Power Dissipation (Note 1) ......... : ........................ 1W
Operating Temperature Range ........... -20·C to +85·C
Storage Temperature Range ............ -65·C to + 150·C
Lead Temperature (Soldering, 10sec) ................. 300·C

Supply Voltage (Note 2) (Voo - Vss) ...................... 6V
Input Voltage Range (any input terminal)
(Note 2) ............. :', ......... :-;. Vss-O.3V to Voo+O.3V
Output Digit Drive Current (Note 3). ~ .......•......... 150rriA
Output Segment Drive, Current •.........•.... ; ...... : ... 30mA

Stresses above those listed under AbS()lute Maximum, Ratings may cause permanent damage to the d9vice. These are stress ratings only, and functiOnal
operation of the device ai these or any bther conditions abOVe th9Se indicated in the operational sections of tlie specifications is not implied. Exposure to
,absolute maximum rating conditiOns for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
SYMBOL

• TEST CONDITIONS

PARAMETER

MIN

TYP

MAX

Quiescent Current

30

300

102

Quiescent Current

All control inputs plus terminal 19 connected
to 1100 except STORE which is connected
to Vss

70

350

1001

Operating, Supply Current

All iinputs connected to VOO, RC multiplexer
osc operating fin < 25kHz

210

500

1002

Operating Supply Current

fin =2MHz

VSUPPLY

Supply Voltege Range

fin::; 2MHz .

ROIG

Digit Driver On Resistance

10lG

Digit Driver Leakage Current

rSEG

Segment Driver On Resistance

ISLK

Segment Driver Leakage Current

R~

Pullup Resistance of RESET
or STORE Inputs

RIN

COUNTER INPUT Resistance

VHIN

COUNTER INPUT HystereSiS
Voltage

UNIT
I

All controls plus terminal 19,'connected to
Voo No multiplex oscillator

101

,

(Voo = 5V, Vss ~ OV, TA = 25·C, display off, unless otherwise specified)

pA

700
3.5
4

5.5

V

12

n

500

pA

500

pA

m

40

100

400
kn
100

Terminal 12 either at Voo or VSS
25

50

NOTES: 1. This value of power dissipation refers to that of the package and will not be obtained under normal operating conditions.

mV

2, The supply voltage must be applied before Or 'at the same time as any input voltage. This poses no problems with a single power
supply system. If, a multiple poWer supply system is used, ,1\ Is mandatory that the supply for the ICM7208 is switched on before the,
other supplies otherwise the device may be permanently damaged.
'
,
3, The output' digit drive current must be limited to 150mA or less under steady state conditions. (Short term transients up to 250mA
will not damage the device.) Therefore, depending upon the LED display and the supply voltage to be used it may be necessary to
include additiOnal segment series resistors to liri\~ the digit currents.

7-16
Note: ,All typical values have been guaranteed by characterization and are not tested.

ICM7208
b

•
c

,.--d

r--e
;--1
r--I

aaaaaa

f!fI
1

2

I

1
1 •
2
3

~

f5.0V

4

5

FUNCTION~I

I.GENERATOR

DISPLAY

~!

My

~

v~o

~

,_

rl~

~

5

3

•

-fJ,- -:

10
11
12
13
14

RESET

COMMDIII CATHODE

2IJ
27

VDD

26-

25
24
.ICM7208 23
22
21

•

STORE
COUNT ENABLE
INHIBIT

7-

VDD
SOl<

20

"llf--

27k
RX

f--

..

171--

"

R. s.

Mux
R.c.
0 SCILLATOR
(APPROx. 1.5kHz)

.o;·~F
ex

lSf--

TC027521

Figure 3: Test Circuit

TYPICAL PERFORMANCE CHARACTERISTICS
SEGMENT OUTPUT CURRENT AS A FUNCTION OF
SUPPLY VOLTAGE

MAXIMUM COUNTER INPUT FREQUENCY.AS A
FUNCTION OF SUPPLY VOLTAGE

30.0

OJ

:z:

!

.

l

u

...Z
...a
...

TA

=125oC

6.0

~

.
II:

/

5.0
4.0

~

iii

3.0

II:
II:

..
..
.

o

1.0

I

20.0

U

~

Q.

15.0

~

0

Z

10.0

:I

III
f/I

V

PI

j

III

c:I

I

/

/
V

~

V

c

:I

2.0

~

/

:I
:I

V

-'

25.0

Z

III

/

~

Q.

!

1
..

7.0

TF~OC I

LED FORWARD VOLTAGE
DROP@ 15 mAo 1.IV
5 SEGMENTS LIT

5.0

V

."

2.0
3.0
4.0
5.0
SUPPLY VOLTAGE (V)

1.0

6.0

2.0
3.0
4.0
5.0
SUPPLY VOLTAGE !VI

6.0

OP03931I

OP039211

7-17
Note: All typical values have been guaranteed by characterization and are not tested.

! ICM72.0$'

...
Ii
('II

g

TYPICAL PERFORMANCE CHARACTERISTICS (CO NT.}
SUPPLY CURRENT AS' A FUNCTION OF SUPPLY
VOI::TAGE
.
300

a~
~

i...
a:
a:

0:)

U

I

I

TA = 25°C

250

'IN

=

G-

o:)

"'

, 600

/
V

25kHz

RC oscill.1or 1.5kHz

200

--c

.

.:

/

150

>oJ

Q.

SUPPLY CURRENT AS A FUNCTION OF COUNTER
INPUT FREQUENCY

100

/

50

./

/

T~ l'ds'd

500

400

z

'"::>

II:
II:

U

/

300

>-

t::>

200

I II

co
100

.r

i.-"

1.6kHz RC MUX OSC

1111

1.~~~' EX~EJJ~~

.~

MUX INPUT'TTii

o
1.0

2.0
3.0
4.0
5.0
SUPPLY VOLTAGE IV)

6.0

0.001

0.01

0.1

1.0

COUNTER INPUT FREQUENCY

OP0394H

OP03951I

TEST PROCEDURES

When driving the input of the ICM7208 from TTL, a
1k-5kil pull-up resistor to the positive supply must be used
to increase peak to peak input signal amplitude.

The ICM7208 is provided with three input terminals 7, 23,
27 which may be used to accelerate testing. The least two
significant decade counters may be tested by applying an
input to the 'COUNTER INPUT' terminal 12. 'TEST POINT'
.terminal 23 provides an input which bypasses the 2 least
significant decade counters and permits an injection of a
signal into the third decade counter. Similarly terminals 7
and 27 permit rapid counter advancing at two pOints further
along the string of decade counters.

Display Considerations
Any common cathode multiplexable LED display may be
used. However, if the peak digit current exceeds 150mA for
any prolonged time, it is recommended that resistors be
included in series with the segment outputs to limit digit
current to 150mA.
The ICM7208 is specified with 5001lA of possible digit
leakage' current. With certain new LED displays that are
extremely efficient at low currents, it may be necessary to
include resistors between the cathode outputs and the
positive supply to bleed off this leakage current.

CONTROL INPUT DEFINITIONS
INPUT

TERMINAL VOLTAGE

FUNCTION

1. DISPLAY

9

Voo
VSS

Display On
Display Off

2. STORE

11

VOO

Counter Information
Latched

VSS

Counter Information
Transferring

3. ENABLE

4. RESET

13

VOO

14

VSS
VOO
VSS

10

"N (MHz)

Display Multiplex Rate
The ICM7208has approximately 0.5/lS overlap between
output drive signals. Therefore, if the multiplex rate is very
fast, digit ghosting will occur. The ghosting determines the
upper limit for the multiplex frequency. At very low multiplex
rates flicker becomes visible.
It is recommended that the display multiplex rate be
within the range of 50Hz to 200Hz, which corresponds to
400Hz to 1600Hz for the multiplex frequency input. For
stand alone systems, two inverters are provided so that a
simple but stable RC oscillator may be built using only 2
resistors and a capacitor.
The multiplex oscillator is eight times the multiplex rate.
Tne frequency is given using the following formulii:

Input to Counter
Blocked
Normal Operation
Normal Operation
Counters Reset

COUNTER INPUT DEFINITION
The internal counters of the ICM7208 index on the
negative edge of the input signal at terminal # 12.

DETAILED DESCRIPTION
Format of Signal to be Counted

1

f=-. 2.2R xCx

The noise immunity of the COUNTER INPUT Terminal is
approximately 1/3 the supply voltage. Consequently, the
input signal should be at least 50% of the supply in peak to
peak amplitude and preferably equal to the supply.
The optimum input signal is a 50% duty cycle square
wave equal in amplitude to the supply. However, as long as
the rate of change of voltage is not less than approximately
1O- 4Vf/.ls at 50% of the power supply voltage, the input
waveshape can be sinusoidal, triangular, etc.

Rs should always be :::: 1Mil and Rs = kR x where k is in the
range 2-10.
An external generator may be used to provide the
multiplex frequency input. This signal, applied to terminal 19
(terminals 16 and 20 open circuit), should be approximately
equal to the supply voltage, and should be a square wave
for minimum of power dissipation.

7-18
Note: All typical values have been guaranteed by characterization and are not lested.

.O~O[l\~

ICM7208
•

"
r--

C

d

,--.
,..---1

r--D

B
d C

7

aaaaaa
5

41

4

I
~5.OV
T

5

DISPLAY

VDD

..:::t::.
0

~0:--1

0-

7

I
10
11
12
13
14

I

I
N.O.

- -

•

-s

lOGIc

~RVDD

I

I

2
3
4

"

INPUT
PROCESSING

2

'.

VDD

_(

3

-r

1-

241J
24125

24
ICM7208 23
22
21
20

"

i
COMMON CATHODE

VDD

27

111718
15r--

...

VDD

lOGIc

-

lOGIc

1

0.01.'

RESET
05021911

Figure 4: Schematic Unit Counter
the counting window. Figure 6 shows the recommended
input gating waveforms to the ICM720S. At the end of a
counting period (50% duty cycle) the counter input is
inhibited. The counter information is then transferred and
stored in latches, and can be displayed. Immediately after
this information is stored, the counters are cleared and are
ready to start a new count when the counter input is
enabled.
.

Unit Counter
Figure 4 shows the schematic of an extremely simple unit
couriter that can' be used for remote traffic counting, to
name one application. The power cell stack should consist
of 3 or 4 nickel cadmium rechargeable cells (nominal 3.6 or
4.S volts). If 4 x 1.5 volt cells are used it is recommended
that a diode be placed in series with the stack to guarantee
that the supply voltage does not exceed 6 volts.
The input switch is shown to be a single pole double
throw switch (SPDT). A single pole single throw switch
(SPST) could also be used (with a pullup resistor), however,
anti-bounce circuitry must be included in series with the
counter input. In order to avoid contact bounce problems
due to the SPDT switch the ICM720S contains an input
latch on chip.
The unit counter updates the display' for each negative
transition of the input signal. The information on the display
will count, after reset, from 00 to 9,999,999 and then reset
to 0000000 and begin to count up again. To blank leading
zeros, actuate reset at the beginning of a ·count. Leading
zero blanking affects two digits at a time.
For battery operated systems the display may be
switched off to conserve power.

Using a 6.5536MHz quartz crystal and the ICM7207
driving the ICM720S, two ranges of counting may be
obtained, using either 0.01 sec or 0.1 sec counter enable
windows.
Previous comments on leading zero blanking, etc., apply
as per the unit counter.
The ICM7207 provides the multiplex frequency reference
of 1.6kHz.

Period Counter
For this application, agopposed to the frequency counter, the gating and the input signal to be measured are
reversed to the frequency counter. The input period is
multiplied by two to produce a single polarity signal (50%
duty cycle) equal to the input period, which is used to gate
into the counter the frequency reference (1 MHz in this
case). Figure S shows a block schematic of the input
waveform generator. The 1MHz frequency reference is
generated by the ICM7209 Clock Generator using an SMHz
oscillator frequency and internally dividing this frequency by
S. Alternatively, a 1MHz signal could be applied directly to
COUNTER INPUT. Waveforms are shown in Figure 7.

Frequency Counter'
The ICM720S may be used as a frequency counter when
used with an external frequency reference and gating logic.
This can be achieved using the ICM7207 Oscillator Controller (Figure 5). The ICM7207 uses a crystal controlled
oscillator to provide the store and reset pulses together with

7-19
Note: All typical values have been guaranteed by characterization and are not tested.

!ft ICM"l208

...

I

B 8- B B B B

•

r-. 8
b

~d

e

'---"

"de

,....,....-'

•

7

5

4

3

2

I

I

I

,

~ •.ov
r--<
VDOo-:r
=:~
DISPLAY

'k

~

L:'1'U

8-4OpF

7

0

h

8

22>;-V';'

OMII

SOk

60k

~

1~ RESET

11

,.

Voo

VDD

17f--

,. I-

'6

1o.47~F

t---

Voo

CRYSTAL PARAMETERS
c\.-uof
CM" , 6mpf
lIS - 6611
CO - 301'

PROC~~

SELECT

COMMON CATHODE

18t--

"'2

~

GATING WINDOW

*

~

'3

~T J
MHz

!

.

28J
27
2
28 f-3
26
4
24
5
8 ICM720823
22
7
2,
9
20 I'0
'9 t--

-.

c>-

'00k

,
ICM
7207

VDD

1-

INPUT

LC017311

Figure 5: Frequency Counter

Note: For a 1 sec count window which allows all 7 digits to be used with a reSOlution of 1Hz. the ICM7207 can be replaced with the .lCM7207A. Circuit details
are given on the 7207A data sheet.
.

1:1

C~---OV

I

COUNT ENABLE INPUT

~COUNTERINPUT~

ENAILEDICOUNTING WINDOW)

lJ
iiEsii'INPUT

COUNTER INPUT

-

PULSE WIDTH NOT
CRITICAL> SO.Sec.

"~SE-=GM=-=EN:-:T=-=D~A-=TA-:ULATCHED

COUNTER RESET

EXTERNAL FREOUENCY TO IE MEASURED
WF016911

Figure 6: Frequency Counter Input. Waveforms

7-20
Note: All typical values have been guaranteed by characterization and are not testad.

.D~OlL

ICM7208

a
.....

N

COUNT ENABLE INPUT

i

~~TERNAL FREQUENCyl

STORE GENERATED BY THE POSITIVE
EDGE OF THE ENAiLi INPUT

STORE INPUT

RESeT INI!UT

=U=RESET

COUNTER INPUT

INPUT IS = 1MHz

--------------------------------------------WF017011

Figure 7: Period Counter Input Waveforms

INPUT

---------f

1 - - -.....- - - - - ENiiLE INPUl

iiEiET INPUT
~---------- STORE INPUT

[

~

ICM7209

r ______'_M_Hz_ COUNTER INPUT

~~~~To~~----L-____~

80008301

Figure 8: Period Counter Input Generator

7~21

Note: All typical values have been guaranteed by characterization and are not tested.

§ ICM7209

,~

Timebase Generator

S:!
GENERAL DESCRIPTION

FEATURES

The Intersil ICM7209 is a versatile CMOS clock generator
capable of driving a number of 5 volt systems with a variety,
of input requirements, When used to drive up to 5 TIL
gates, the typical rise and fall times are 10ns.
The ICM7209 consists of an oscillator, a buffered output,
equal to the oscillator frequency and a second buffered
output having an output frequency one-eighth that of the
oscillator. The guaranteed maximum oscillator frequency is
10MHz. Connecting the DISABLE terminal to the negative
supply forces the +8 output into the '0' state and the output
1 into the '1' state.

•
•
•
•
•
•
•
•

High Freq!lency Operation - 10MHz Guaranteed
Requires Only A Quartz Crystal and Two
Capacitors
Bipolar, CMOS Compatibility
High Output Drive Capability - 5 x TIL Fanout
With 10ns Rise and Fall Times
Low Power-50mW at 10MHz
Choice of Two Output Frequencies - Osc., and
Osc. + 8 Frequencies
Disable Control for Both Outputs
Wide Industrial Temperature Range - 20°C to
+ 85°C

ORDERING INFORMATION
PART
NUMBER

TEMPERATURE
RANGE

ICM72091JA

-20°C to +85°C

8 pin CERDIP

ICM72091PA

-20°C to + 85°C

8 pin PLASTIC

ICM7209/D

-

DICE

PACKAGE

• 4,J.,YOO

styss

1
OSC OUT 0 - - - - - - '

3

OISABLE

0-----------------4-4

5
b----oOUT1

TOPYIEW
CD02B41I

D5025011

Figure 1: Functional Diagram
'Zener Voltage is Typically 6.3 Volts

Figure 2: Pin Configuration
(Outline dwg PAl
Pin 1 Is designated by either a dot
or a notch

7-22
Note: All typical values have been guaranteed by characterization and are not tested.

-002

ICM7209
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................................... 6V
Output Voltages ................... Vss - O.3V to Voo + O.3V
Input Voltages ..................... VSS - O.3V to VDO + O.3V

Power Dissipation (25°C) ................................ 300mW
Storage Temperature .................. , ... -55°C to + 125°C
Operating Temperature Range ........... -20°C to +85°C
Lead Temperature (Soldering, 10sec) ................. 300°C

NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification. is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTiCS
(VOD - Vss

= 5V± 10%,

test circuit,

SYMBOL
100

f05C =

10MHz, T A = 25°C unless otherwise specified.)

PARAMETER

TEST CONDITIONS

Supply Current

Co

Disable Input Capacitance

IILK

Disable Input Leakage

VOL

Output Low State

VOH

Output High State

-- r---'

TYP

MAX

UNIT

11

20

mA

±10

JiA

pF

5

Either '" or '0' state
Either OUT 1 or OUT 0-8
simulated 5 x TTL loads
t::ither OUT 1 or OUT 78
simulated 5 x TIL loads

tR

Output Rise Time (Note 3)

Either OUT 1 or OUT 78
simulated 5 x TIL loads

tF

Output Fall Time (Note 3)

Either OUT 1 or O'UT 78
simulated 5 x TTL loads

fOSC

Minimum OSC Frequency
for +8 Output

Note 2

Output 78 duty cycle

Any' operating frequency
Low state : High state

GM

MIN

Note 1
No Load

0.4

-

I

4.0

V

4.9
10

ns

10
2
MHz
7:9
80

Oscillator Transconductance

200

JiS

of

NOTES: 1. The power dissipation is a function
the oscillator jrequency (1st ORDER EFFECT see curve) but is also effected to a small extent
by the oscillator tank components.
'
2. The 78 circuitry uses a dynamic ,scheme. As with anY dynamic system, information or data is stored on very small nodal
capacitances instoad Of latches (static systems) and there is a lower cutoff frequency of operation. Dynamic dividers are used in the
ICM7209 to significantly improve high frequency performance and to decrease power consumption'.
3. Rise and iall times are defined between the output levels of 0.5 and 2.4 volts.

CRYSTAL PARAMETERS:

c.,- 5mpF
RS -15 ohms
CO= 3pF
CL = 10pF
f= 10 MHz

O.01I.1F

~I----+

OUT+s

rqo31311

Figure 3: Test Circuit

7-23
Note: All typical values have been guaranteed by characterization and are not tested.

81CIII7209

'~

~

.".

' I ,

TYPICAL PERFORMANCE CHARACTERISTICS
SUPPLY CURRENT AS A FUNCTION
OF OSCILLATOR FREQUENCY
15

I

TA - 25°C
.

LOADS AT
OUTPUT 1

j

(

5

"\

TA-25°C

=

LOAD
5x TTL
LOADS
TA= 25°C
fOSC·
10MHz

\

3

V
i"

V

100kHz

V

OUTPUTS D!SABLE;D

.~--4--~;
o~

1MHz
10MHz
FREQUENCY

I

100MHz

SUPPLY VOLTAGE RANGE FOR
CORRECT OPERATION Of ,+8
COUNTER AS A FUNCTION OF
OSCILLATOR FREQUENCY.

'TYPICAL OUT 1 RISE AND FALL
TIMES

4

SIM~LAT~D ~~TTL II

(VDD - Vss = 5V)

o

J
20

40

60

/

J

/

~LYVOLTAGE

\.
80

100

T,IME (ns)

,

f----

/

0P048911

o

LOCI FOR CO~RECT
OPERATION

10kHz 100MHz 1 MHz 10MHZ 100MHz
OSCILLATOR FREQUENCY
'v

0P049001

0P049111

Rise and fall times of OUT +8 are
similar to those Of OUT 1.
store voltage levels instead of latches (which are used in
static dividers). The dynamic divider has advantages in high
speed operation and low power but suffers from limited low
frequency. operation. This results in a window of operation
for any oscillator frequency (see TYPICAL PERFORMANCE
CHARACTERISTICS).

DETAILED DESCRIPTION
OSCILLATOR CONSIDERATIONS
The oscillator consists of a CMOS inverter with a nonlinear resistor connected between the oscillator input and
output to provide D.C. biasing. Using commercially obtainable quartz crystals the oscillator will operate from low
frequencies (10kHz) t010MHz.
The oscillator circuit consumes about 500~ of current
using a 10MHz crystal with a 5 volt supply, and is designed
to operate with a high impedance tank circuit. It is therefore
necessary that the quartz crystal be specified with a load
capacitance (Cl) of 10pF instead of the standard 30pF. To
. maximize the stability of the oscillator as a' function of
supply voltage and temperature, the motional capacitance
of the crystal should be low (5mpF or less). Vsing a fixed
input capacitor of 18pF and a variable capacitor of nominal
value of 18pF on the output will result in oscillator stabilities
of typically 1ppm per volt change in supply voltage.

THE

+8

OUTPUT DRIVERS
The output drivers consist of CMOS inverters having
active pullups and pUlidowns. Thus the outputs can be used
to directly drive TTL gates, other CMOS gates operating
with a 5 volt supply, or TTL compatible MOS gates. The
guaranteed fanout is 5 TTL loads although typical fanout
capability is at least 10 TTL loads with slightly increased
.
output rise and fall. times.

DEVICE POWER CONSUMPTION
At low frequencies the principal component of the power
consumption is the oscillator. At high oscillator frequencies
the major portion of the power is consumed by the output
drivers, thus by disabling the outputs (activating the DISABLE INPUT) the device power consumption can be
dramatically reduced.

OUTPUT

A dynamic divider is used to divide the oscillator frequency by 8. Dynamic dividers use small nodal capacitances to

7-24
Note: All typical values have been guaranteed by characterization and are not tested.

ICM7213
One Second/One Minute
Timebase Generator
GENERAL DESCRIPTION

FEATURES

The. ICM7213 is a fully integrated micropower oscillator
and frequency divider with four buffered outputs suitable for
interfacing with rnostlogic families. The power supply may
be either a two battery stack (Ni-cad, alkaline, etc.) or a
regular power supply greater than 2 volts. Depending upon
the state of the WIDTH, INHIBIT, and TEST inputs, using a
4.194304MHz crystal will produce a variety of output
frequencies including 2048Hz, 1024Hz, 34.133Hz, 16Hz,
1Hz, and 1160Hz (plus composites).
The ICM7213 utilizes a very high speed low power metal
gate CMOS technology which uses 6.4 volt zeners between
the drains and sources of each transistor and also across
the supply terminals. Consequently, the ICM7213 is limited
to a 6 volt maximum supply voltage, although a simple
dropping network can be used to extend the supply voltage
range well above 6 volts (See Figure 7).

•
•

Guaranteed 2 Volts Operation
Very Low Current Consumption: Typ. 1001lA

@

3V
•
•
•
•
•
•

All Outputs TTL Compatible
On Chip Oscillator Feedback Resistor
Oscillator Requires Only 3 External Components:
Fixed CapaCitor, Trim CapaCitor, and A Quartz
Crystal
Output Inhibit Function
4 Simultaneous Outputs: One PulselSec, One
PulselMln, 16Hz and Composite 1024 + 16 + 2Hz
Outputs
Test Speed-Up Provides Other Frequency'
Outputs

ORDERING INFORMATION
PART
NUMBER

TEMPERATURE
FlANGE

ICM72131JD

-20'C to +85'C

14 pin CERDIP

ICM72131PD

-20'C to +85'C

14 pin PLASTIC
DIP

ICM7213/D

-

DICE

PACKAGE

WIDTH

OUT 4

OUT 3

OUT 2

INHIBIT

V..

OUT 1

TEST

OSCOUT

V..

OSCIN
Nie

NIC

COO28511

60012911

Figure 1: Functional Diagram

7-25
Note: All typical values have been guaranteed by characterization and are not tested.

Figure 2: Pin
Configuration
(Outline drawing PO)

202800-002

PI

IC"7213
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Voo - Vss) ................................ 6.0V
Output Current (Any output) .............................. 20l)1A
All Input and Oscillator Voltages (Note 1) •...... ;.' .... 1.; .. :
Vss-O:~Vto Voo+O.3V
All Output Voltages (Note 1) ..............•..... VSS to.6.0V

Operating Temperature Range ........... -20°C to +85°C
Storage Temperature Range, ........... -4;O·C to + 125°C
Power Dissipation (Note 2): .... : ....................... 200mW
Lead Temperature (Soldering, 10sec) ................. 300°C

Stresses above those listed under Absolute Maximum Ratings may 'cause permanent ·damage to ·the device. These are stress ratings only, and functional
operation of the device at theSe or 'any"dther conditions above· those indicated in the operational s9ctions of the specifications is not implied. Exposure to
absolute maximum rating . conditions for· extended periods may· affect device reliability.
NOTE 1: The ICM7213like mdst CMOS devices: may enter a destructive latchup mode if an input or output voltage is applied in excess of those; defined and
there is no 'supply current limiting.
NOTE 2: oerate linearly power rating of 200mW at 25·C to50mW at 70·C.

ELECTRICAL CHARACTERISTICS.
(Voo- Vss = 3 OV , fosc = 4· 194304MHz, Test Circuit TA = 25°C unless otherwise specified)
SYMBO,L

TEST CONDITIONS

PARAMJ:TER

100

Supply Current

VSUPPLY

Guaranteed Operating Supply
Voltage Range (VOO - VSS)

-20·C

IOlK

Output leakage Current

Any output, VOUT = 6 Volts

ROUT

Output Sat. Resistance

Any output, IOlK" 2.5mA

II

Inhibit Input Current

Inhibit terminal connected to VOO

ITP

Test Point Input Current

IW

,

MIN

< TA < 85·C

TYP

MAX

UNIT

100'

140

p.A

4

2

V

10

p.A

120

200

n

10

40

Test pOint terminal connected
to VOO

10

40

Width Input Current

Width terminal' connected to Voo

10

40

gm

Oscillator gm

VOO= 2V

fOSC

Oscillator Frequency Range (Note 3)

fSTAB

Oscillator Stability

ts

Oscillator Start Time

jlA
jlS

100
1

2V

< VOO < 4V

10

MHz

1.0

ppm

0.1

sec.

0.2

Voo.= 2.0 volts

NOTE: 3. The ICM7213 uses dynamic dividers for high frequency division. As with any dynamic system, information is stored on very smail nodal
capacitances instead of latches (static system)', therefore there is a lower frequency.of operation. Dynamic dividers are use;d to improve
the high frequency performance while at the. same time significantly decreaSing power consumption. At low supply voltages, operation at
less than 1MHz is possible. See application notes.

WIDTH

CRYSTAL PARAMETER
f
= 4.194.304 MHz (PARALLEL
RS = 35
RESONANT)

N.O.

n

~-17mpF

Co = 2.5 pF

INHIBIT

T.P.

}--+.---o+
SUPPLY VOLTAGE

TCQ31411

Figure 3: Test Circuit

7-26
Note: All typical values have been guaranteed by characterization alld are not tested.-

ICM7213
TYPICAL PERFORMANCE CHARACTERISTICS
SUPPLY CURRENT AS A FUNCTION
OF TEMPERATURE

I

~

110

Z
w

~100

~

VSUpp=3V
CIN
CO~T 30 pF'OS = 4.1 MHz

=

~

U90

....>-

~

1 250

=

o
9200

!z~150~-+--~~~~~+-~

J

"- ......

::l

tao
il 70

-

,.....

V

a:

a'00~-+--~~--~--+-~

~ 50
AA-

il

-40 -20

0

0

L.....-I._-'----I_....l.._.L.-.....J

3.0
4.0
5.0
SUPPLY VOLTAGE V DD -V••

TEMPERATURE _ °c

+1.5

VOO-VSS=3V
+1.0 CIN. COUT ANO
QUARTZ CRYSTAL
MAINTAINEO AT 25°C
+0.5
fOSC=4.19MHz

.,.,..

L

V

OP049401

OSCILLATOR STABILITY AS A FUNCTION OF
SUPPLY VOLTAGE

~
<
:;
i:

f

w

Q

>

+1

H
5~

/'

-0.5

0.1 0.2 0.3 0.4 0.5 0.6
OUTPUT SATURATION
VOLTAGE (ANY OUTPUT I

OP04931I

OP049201

OSCILLATOR STABILITY AS A'FUNCTION OF
DEVICE TEMPERATURE

o

o

2.0

+20 +40 +60 +80

-1.0

OUTPUT CURRENT AS A FUNCTION
OF OUTPUT SATURATION VOLTAGE

<300r--r-.--.--.--r-~

I I

130

~12O

SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE

0

~$-1

1--+::;;iIooi~+--+7"-I---t
CINI:: COUT = 30 pF

"'<1

~. oc( ~:

I

1

-1.5
-40 -20 0 +20 +40 +60 +80
TEMPERATURE _ ·C

~

2~.O--L-~~--~~~5"".O
SUPPLY VOLTAGE Voo-V..
OP04961I

0P049501

OUTPUT DEFINITIONS
INPUT STATES·
TEST

INHIBIT

WIDTH

L

L

L

L

L

H

L

H

L

L

H

H

H
H
H

L
L
H

L
H

L

PIN 12
OUT 1

PIN 13
OUT 2

PIN 14
OUT 4

PIN 2
OUT 3

+2'8

1024 + 16 + 2Hz
(+2'2+2'8+22') composite

+222

1160Hz, 1 Sec.
+(224 x 3 5)

16Hz

1024 + 16 + 2Hz

1Hz, 7.8ms

1160Hz, 125ms

+2'8

(+2'2+2'8-<-221) composite

+222

16Hz

1024 + 16Hz

OFF

16Hz

1Hz, 7.8ms

x

OFF'

+2 '8

(+2'2+2'8) composite

16Hz

1024 + 16Hz

+2'8

(+2'2+2 '8) composite

ON

4096 + 1024Hz

2048Hi

34_133Hz, 50% D.C.

(+2 ' °+2'2) composite

+2 "

+(2 '3 x 5 x 3)

ON
ON

OFF

S~E

WAVEFORMS

4096 + 1024Hz

2048Hz

34.133Hz, 50% D.C.

(+2 1°+2 12) composite

+2 11

+(2'3 x 5 x 3)

1024Hz

ON

OFF

ON

OFF

+2 12
H

H

H

ON

1024Hz
+2 12

NOTE: When TEST and RESET are connected to ground, or left open, all outputs except for OUT 3 and OUT 4 have a 50% duty cycle.
7-27
Note: All typical values have been guaranteed by characterization and' are not tested.

PI

-I

1-16 Hz

••••••••

OUT 2

I' .

•

.024 Hz

•••

.j

2 Hz

WF021601

Figure 4: Output Waveforms

,
INHIBIT
OUT. 3

C~SE 1l oUT 4
I

'OUT3
CASE 2 ,
(PULSE 3\
COINCIDENT OUT 4
WITH INHIBIT.

I
I

ULJ

I

,
I

.:
I

t

,,
I

I

,

,

I

I

l--t.r

0.75 - 1.0 SliC ,
:- 59~75 to
, 60SECS.

I
I

,..n (""'.
(EFFECT OF .'
WIOTH
OUT 3

..... (ou"

(EFFECT OF
WIDTH 'WIDTH
ON OUT 4)

I

,

I

I

,

,

I

I

,.

I

I

u!
I
I

,,

U

I

I

I'I

~

I

=:t!F=7.8ms

I

r-::u- 7.8m.

,

<7.8ms-:-

OUT 3

WIDTH
ON OUT 4'

--,,

II

i

,

I

,

I

I

I

I

,

,
I

I

n

. I

I

II

I
iI

~

I

I

U:I

U

I

,

I

, , I
, ,
I
I

I

I

I

u
~-.

I

I

I

I

,

I

!
WF021701

Figure 5: Effect of Input Inhibit (Test Connected to Vss or Left Open)
All time scales are arbitrary, and in the case of OUT 3
only the pulses coinciding with the negative edge of OUT 4
are shown, Where time intervals are relevant they are
clearly shown.

"r-

.-

APPLICATIONS

SOPPLY
VOLTAGE

Supply Voltage Considerations
The ICM7213 may be used to provide various precision
outputs with frequencies from 2048Hz to 1160Hz using a
4, 194,304Hz quartz oscillator, and other output frequencies
may be obtained using other quartz crystal frequencies.
Since the ICM7213 uses dynamic high frequency dividers
for the initial frequency division there are limitations on the
supply voltage range depending on the oscillator frequency.
If, for example, a low frequency quartz crystal is selected,
the supply voltage should be selected in the center of the
operating window, or approximately 1.7 volts.

r

OPERATING
WINDOW

3

2

,
'OkHz

'l1lIkHz

' ..Hz

'DOIHz
OP05&701

Figure 6: Window of Correct Operation
The supply voltage to the ICM7213 may be derived from
a high voltage supply by using a simple resistor divider (if
power is of no concern), by using a series resistor for
minimum current consumption, or by means of a regulator.

7-28
Note: All typical values have been guaranteed by characterization. and are not tested.

ICM7213
Oscillator Considerations

EXAMPLE:
f ~ 4.2 MHz
8V 0;;; V 0;;; 12V (10 nom.1
11 ""100IlA
R
1 ""1 mA
2
~2 ""3KOHMS
R1 ""6.8K OHMS

CBYPASS 0.01
11

The oscillator consists of a CMOS inverter and a feedback resistor whose value is dependent on the voltage at
the oscillator input and output terminals and the supply
voltage. Oscillator stabilities of approximately 0.1 ppm per
0.1 volt variation are achievable with a nominal supply
voltage of 5 volts and a single voltage dropping resistor.
The crystal specifications are shown in the TEST CIRCUIT.

Il F

It is recommended that the crystal load capacitance (Cl)
be no greater than 22pF for a crystal having a series
resistance equal to or less than 75 ohms, otherwise the
output amplitude of the oscillator may be too low to drive
the divider reliably.

05025101

11
CBYPASS
0.011lF

+-_ _-,

If a very high quality oscillator is desired, it is recommended that a quartz crystal be used having a tight tuning
tolerance ± 1Oppm, a low series resistance (less than 25
ohms), a low motional capacitance of 5mpF and a load
capacitance of 20pF. The fixed capacitor CIN should be
30pF and the oscillator tuning capacitor should range
between approximately 16 and 60pF.

EXAMPLE:
fOse - 4.2 MHz
svo;;; V 0;;; 12V (10V noml
11 "" 100IlA
R3 = (1().. 31 K OHMS

10- 4

Use of a high quality crystal will result in typical stabilities
of 0.05ppm per 0.1 volt change of supply voltage.

""68l< OHMS

Control Inputs

05025201

Figure 7: Biasing Schemes
with High Voltage Supplies

Logic Family Compatibility

The TEST inRut inhibits the 2 18 output and applies the 29
output to the 221 divider, thereby permitting a speedup of
the testing of the +60 section by a factor of 2048 times. This
also results in alternative output frequencies (see table).

Pull up resistors will generally be required to interface
with other logic families. These resistors must be connected
between the various outputs and the positive power supply.

The WIDTH input may be used to change the pulse width
of OUT 4 from 125ms'to 1 sec, or to change the state of
OUT 4 from ON to OFF during INHIBIT.

7-29
Note: All typical values have been guaranteed by characterization and are not tested.

"C"I ICII7215

. ~ 6-Digit LED Display
.~ 4-Function Stopwatch
GENERAL DESCRIPTION

FEATURES

The ICM7215 is a fully integrated six digit LED stopwatch
circuit fabricated with Intersil's low threshold metal gate
CMOS process. The circuit interfaces directly with a six
digit/seven segment common cathode LED display. The
low battery indicator can be connected to the decimal point
anode or to a separate LED. The only components required
for a complete stopwatch are the display, three SPST
switches, a 3.2768MHz crystal, a trimming capacitor, three
AA batteries and an ON-OFF switch. For a two function
stopwatch, or to add a display off feature, one additional
slide switch is required. The circuit divides the oscillator
frequency by. 215 to. obtain 100Hz, which is fed to the
fractional seconds, seconds and mii1Ujes counters, while an
intermediate frequency is used to obtain the 1/6 duty cycle
1.07kHz multiplex waveforms. The blanking logic provides
leading zero blanking for seconds and minutes independently of the clock. The ICM7215 is packaged in a 24-lead
plastic DIP.

•

Four Functions: Start/Stop/Reset, Split, Taylor,
Time Out
.
.• Six Digit Display: Ranges Up to 5.9 Minutes 59.99
Seconds
• High LED Drive Current: 13mA Peak Per
Segment at 16.7% Duty Cycle With 4.0 Volt
Supply
• Requires Only Three Low Cost SPST Switches
Without Loss of Accuracy: Start/Stop, Reset,
Display Unlock
• Chip Enable Pin Turns Off Both Segment and
Digit Outputs; Can Be Used for Multiple Circuits
Driving One Display
• Low Battery Indicator
• Digit Blanking On Seconds and Minutes
• Wide Operating Range: 2.0 to 5.0 Volts
• 1kHz Multiplex Rate Prevents Flickering Display
• Can Be Used. Easily In Four Different Single
Function Stopwatches or Two Two-Function
Stopwatches: Start/Stop/Reset With Time-out,
Split With Taylor. The Component Count for A
Three- or Four-FunctiQn Stopwatch Will Be
Slightly" Greater
.
•. Retr(lfit to ICM720fj .for Split and/or Taylor
Applications

ORDERING INFORMATION
PART NUMBER

TEMP. RANGE

PACKAGE

ICM72151PG

-20·C to + 70.C

24-Pin PLASTIC

ICM7215/D

DIP

DICE

2INPUTSB-

DIGIT

6 OUTPUTS

OUTPUTS

OSCOUT

~-====r---'

LBIANOOE

voo

Seg •
!leg d

10th.

Sallg

l00th.
VSS

$ega

7 OUTPUTS

Sell b
$eg I
SI
S10

~
~10UTPUT

TEST
START/STOP
MODE
RESET
DISPLAY

Segc
LOW
FREQUENCY
DIVIDER

OSCIN

CHIP ENABLE
Ml0
Ml
CD028721

BD013001

Figure 1: Functional Diagram

Figure 2: Pin Configuration
(Outline dwg PG)

7-30
Note: All typical values have been guaranteed by characterization and are not tested:

-002

ICM7215
ABSOLUTE MAXIMUM RATINGS
Storage Temperature ...................... -55°e to +125°e
Input Voltage ........................ Vss-O.3V to VDD+O.3V
Output Voltage ....................................... VSS to VDD

Supply Voltage (VDD to Vss) .............................. 5.5V
Power Dissipation (Note 1) .............................. O.75W
Operating Temperature ..................... - 20 0 e to + 70 0 e

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. and lunctional
operation 01 the device at these or any other conditions above those indicated in the operational sections 01 the specifications is not implied. Exposure to
absolute maximum rating conditions lor extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS:

(T A = + 25°e, stopwatch circuit, VDD = 4.0V, Vss =

av,

unless otherwise

specified.)
SYMBOL

PARAMETER

TEST CONDITIONS
~

TA

~

VSUPPLY

Supply Voltage (Voo - Vss)

-20·C

100

Supply Current

Display off

ISEG

Segment Current
Peak
Average

5 segments lit
1.8 Volts across display

MIN

+70·C

TYP

2.0
0.6
9.0

MAX

UNIT

5.0

V

1.5
mA

13.2
2.2

Switch Actuation Current

All inputs except CHIP
ENABLE

20

50

Switch Actuation Current

Chip enable

50

200

IOLK

Digit Leakage Current

VOIG = 2.0V

50

ISLK

Segment Leakage Current

VSEG = 2.0V

100

VLBI

Low Battery Indicator
Trigger Voltage

Isw

2.8

2.2

ILBI

LBI Output Current

VOO = 2.0V, VLBI = 1.6V

ISTAB

Oscillator Stability

Voo = 2.0V to Voo = 5.0V

gm

Oscillator Transconductance

VOO = 2.0V

JJ.A

V

2.0

mA

6

ppm

120

JJ.s

30
pF
Oscillator Input Capacitance
COSCI
NOTE: 1. The output devices on the ICM7215 have very low Impedence characteristics, espeCially the digit cathode drivers. II these devices
are shorted to a low impedance power supply, the current could be as high as 300mA.

1:=~

@_

1-8,
7 _d
I ~ ••
5.......
•c
4 _
2 -

d

COMMON CATHODE DISPLAY

b

C
•

D.P.M10

t
14

B. B. B. B. B.
M1

S10

51

lOths

t

t

t

t

13

12

11

18

VOO

QUARTZ CRYSTA
PARAMETERS
I = 3.27S8MHz
RS = 50/1
CM =23mpF
CO = 14pF
CL = 15pF

l00ths

t

17
VOD

~

.l-

PI
SWITCH TRUTH TABLE
SWITCH MODE
POS.
(21)
MODE
START/STOP/RESET
FLOAT
1
SPLIT
2
VDD
TAYLOR
3
vss
TIME-OUT
4
FLOAT

DISPLAY
(19)
FLOAT
UNLOCK
UNLOCK
Vss

N.O. NORMALLY OPEN
_ T O DISPLAY
LC026111

Figure 3: Stopwatch Circuit

7-31
Note: All typical values have been guaranteed by characterization and are not tested.

!...
~

ICM7215
TYPICAL PERFORMANCE CHARACTERISTICS
SEGMENT CURRENT VS SUPPLY VOLTAGE

SUPPLY CURRENT VS VOLTAGE

C

.!20

DISPLAY OFF
TA" +zsoC

L

/

ia:
§

/
V

~

15

V

~ 10

/'

I

3.0

4.0

5.0

~

5

i

0

L

./

:/

3.0

4.0

5.0

SUPPLY VOLTAGE (VI
OP0497Q1

0P04981 I

LOW BATTERY INDICATOR (LBI) TRIGGER
VOLTAGE VS TEMPERATURE

OSC. STABILITY VS'SUPPLY VOLTAGE

I

=2.9

-'

TA = +25°C
COUT =22pF

V
./

V

i'-.
~
11/ 2.7

V

" 1"-

"~

-' 2.5

g

"'" i'--

a:

V

V

L

V
2.0

SUPPLY VOLTAGE

I

I

,/

U

0.0
2.0

TA = +zsoC I
VF(LED) = 1.8V

~2.3

,

I!= 2.1
2.0

3.0

4.0

~

5.0

-10 0

SUPPLY VOLTAGE (VI

10

30

50

TEMPERATURE eC)

0PG49911

OPOSOOOI

,-; -, ,/I,

,-,,-,

L"_'
RESET

START/STOP ... 27.65 lee
ONCE

RESET

MEn

MEn

..

LJl.'

DISPLAY STOPS

CLOCK AND
DISPLAY COUNTING

MEn

,-,,-,

2765

'_'':' -,0

START/STOP
ONCE

START/STOP
ONCE
LD00871'

Figure 4: Start/Stop/Reset Mode
The Start/Stop/Reset mode can be used for single event
timing in a one-button stopwatch; an additional switch can
be used to provide an instant reset. To time another event,
the display must be reset before the start of the event.
Seconds will be displayed after one second, minutes after
one minute. The range of the stopwatch is 59 minutes 59.9,9
seconds, and if an event exceeds one hour, the number of
hours must be remembered by the user. Leading zeroes are
not blanked after orie hour.

DETAILED DESCRIPTION
FUNCTIONAL OPERATION
Turning on the stopwatch will bring up the reset state with
the fractional seconds displaying 00 and the other digits
blanked. This display always'indicates that the stopwatch is
ready to go.
The display can be turned off in any mode by connecting
the CHIP ENABLE input to Voo.

START/STOP/RESET MODE
When the MODE input is floating and the DISPLAY input
is floating or connected to VDD the circuit is in the Start/
Stop/Reset mode. (Figure 4).
.
7-32

Note: All typical values have been guaranteed by characterization' and are not tested.

ICM7215

,-,,-,

2DL:7

ii:J
,_,,
__00
'L'

L'U
RESET

DISPLAY STOPS
CLOCK RESETS
AND STARTS COUNTING

CLOCK AND
DISPLAY COUNTING

PRESS
START/STOP
ONCE

PRESS
START/STOP
ONCE

- - 20.47 _ . - - -..... ~_--12.35

III

L

I

L_--I
rm;-t

'"

'L'

uJ -"'

'L

H

I:'.

LAP 3 '---O-'SP-LA-Y-S-T-O-PS--'

CLOCK AND
DISPLAY COUNTING

I':; _,_,
::JC
IL
DISPLAY STOPS
CLOCK RESETS
AND STARTS COUNTING

PRESS
STARTISTOP
ONCE

PRESS
DISPLAY
UNLOCK
ONCE

_.---_.oo-____ 42.7tHC._ _ __

11,-' }
L"_'
. -

_

.....---R-ES-E-T--.J

CLOCK RESETS

AND STARTS COUNTING
PRESS
START/STOP
ONCE

PRESS

RESET

Figure·5: Taylor or Sequential Mode

,i"

.:"i ,_, 1

"_' iO
"_,

'_'U

,_ L'

I ,

RESET

PRESS
START/STOP
ONCE

"

DISPLAY STOPS
CLOCK CONTINUES COUNTING

CLOCK AND
DISPLAY COUNTING

PRESS
START/STOP
ONCE

DISPLAY STOPS
CLOCK CONTINUES COUNTING

PRESS
START/STOP
ONCE

PRESS
DISPLAY
UNLOCK
ONCE

_ _ _ 20.47 _ . - - -.. _---12.35 H C . _••_ _ _ _ 42.71 _ . , - - - -

UC IIJ

'-' "-'

CLOCK AND
DISPLAY COUNTING

,. I
L' ,

'e c
RESET

DISPLAY STOPS
CLOCK CONTINUES COUNTING
PRESS
START/STOP
ONCE

""

'_'L'

,_, U

PRESS
RESET

LOOO8601

Figure 6: Split Mode

TAYLOR OR SEQUENTIAL MODE

Iy and start counting the next interval. The time displayed is
that elapsed since the last activation of START/STOP. The
display is stationary after the first interval unless the display
unlock is used. by connecting the DISPLAY input to Vss. to
show the running clock•. RESET can be used at any time.

When the MODE input is connected to VSS. the stop·
watch is in the Taylor or Sequential mode. (Figure 5).
Each split time is measured trom zero in the Taylor mode;
i.e.• after stopping the watch. the counters reset momentari·

7-33
Note: All typical values have been guaranteed by characterization and are not tested.

ICM7215

,-,,-,

II,]

RESET

CLOCK AND
PRESS DISPLAY COUNTING
START/STOP
O~E

•

(

20 L:t

00

LII_ _"_,

ULI

2lf:8 b;1

CLOCKANO
DISPLAY COUNTING

PRESS
START/STOP

DISPLAY STOPS
CLOCK STC?PS

PRESS

PRESS

START/STOP

START/STOP

O~E

O~E

20.47 - . - - T I M E OUT _ _ 22.32_.

DD}-

L:279H

'----,----'

DISPLAY STOPS
CLOCK STOPS

.

RESET

PRESS
RESET

O~E

LOOO8801

Figure 7: Time-Out Mode
Taylor mode. The circuit, Figure 8, shows how the user can
obtain lap and cumulative readings of the same event.
SWITCH CHARACTERISTICS
The ICM7215 is designed for use with SPST switches
throughout. On the DISPLAY and RESET inputs the characteristics of the switches are unimportant, since the circuit
responds to a logic level held for any length of time however
short. Switch bounce on these inputs does not need to be
specified. The START/STOP input, however, responds to
an edge and so requires a switch with less than 15ms of
switch bounce. The bounce protection Circuitry has been
specifically designed to let the circuit respond to the first
edge of the Signal, so as to preserve the full accuracy of the
system.

SPLIT MpDE
When the MODE input is connected to VOO the stopwatch is in the Split mode. (Figure 6).
The Split mode differs from the Taylor in that the lap
times are cumulative in the Split mode. The counters do not
reset or stop after the first start until RESET is activated.
Time displayed is the cumulative time elapsed since the first
start after reset. Display unlock can be used, by connecting
the DISPLAY input to Vss, to let the display 'catch up' with
the clock, and RESET can be used at any time.

TIME OUT MODE
When the MODE input is floating and the DISPLAY input
is tied to VSS, the stopwatch is in the Time-out mode.
(Figure 7).
In the Time-out mode the clock and display alternately
start and stop with activations of the START/STOP switch.
RESET can be used at any time. The display unlock button
is bypassed in this mode.

DISP!-AY
TO DISPLAY

TO DISPLAY

APPLICATION NOTES
LOW BATTERY INDICATOR
The on-chip low battery indicator is intended for use with
a small LED or the decimal pOints on a standard LED
display. The output is the drain of a p-channel transistor
two-thirds the size of the segment drivers which will typically
source 2mA of current. The threshold voltage is approximately 2.5 volts at room temperature. Normal AA type
batteries will provide many hours of accurate timekeeping
after the indicator comes on, however the wide voltage
spread between the LBI threshold voltage and minimum
operating voltage is required to guarantee low battery
indication LInder worst case conditions.
CHIP ENABLE
The CHIP ENABLE input is used to disable both segment
and digit drivers without affecting any of the functions of the
device. When the CHIP ENABLE input is floating or
connected to VSS, the display is enabled, and when the tied
to VOO the display is turned off. One example of the many
possible uses of this feature is driving one display from two
ICM7215 devices, one in the split mode and the other in the

ICM7215
24 TAYLOR
15
~~---------~

r--+---i

~------~~

VDO
TAYLOR SPLIT
ALL OTHER SWITCHES COMMON TO BOTH DEYICES
LD00891I

Figure 8
LATCHUP CONSIDERATIONS
Due to the inherent structure of junction isolated CMOS
devices, the circuit can be put in a latchup mode if large
currents are injected into device inputs or outputs. For. this
reason special care should be taken in a system with
multiple power supplies to prevent voltages being applied to
inputs and/or outputs before power is applied to the 7215. If
only inputs are affected, latchup can also be prevented by
limiting the current into the input terminal to less than 1mAo
7-34

Note: All typical values have been guaranteed by characterization and are not· tested.

.U~Dll

ICM7215

series resistance and/or load capacitance should be speci-

OSCILLATOR DESIGN

~d.

The oscillator of the ICM7215 includes all components
on chip except the 3.2768MHz crystal and the trimming
capacitor. The oscillator input capacitance has a nominal
value of 30pF, and the circuit is designed to work with a
crystal with a load capacitance of approximately 15pF. If the
crystal has characteristics as shown in the Typical Performance Characteristics, an 8-40pF trimming capacitor will
be adequate for a tuning tolerance of ±30PPM on the
crystal. If the crystal' s static capacitance is significantly
lower, a narrower trimming range may be selected.
After deciding on a crystal and a nominal load capacitance, take the worst case values of Cin, Cout and Rs and
calculate the gl")1 required by:

TEST
The TEST input is used for high speed testing of the
device. When the input is pulsed low, a latch is set which
speeds up counting by a factor of 32; each pulse on the
TEST input rapidly advances both minutes and seconds in a
parallel mode. To accurately rapid advance the signal
applied to the TEST input must be free of switch bounce.
The circuit is taken out of the test mode by using either
RESET or START/STOP.

?
W"

REPLACING THE ICM7205 WITH THE
ICM7215

Cin = input capacitance

The ICM7215 is designed to be compatible with circuits
using the ICM7205. If the 7205 is used only in the Split
mode no changes are required. If the 7205 is used in the
Taylor mode and the Split-Taylor input (pin 21) is left open,
a jumper from pin 21 to VSS must be added when
converting to the 7215. A jumper may also be needed if the
7205 is used with a Split/Taylor switch. Once the jumper
has been added the board can be used with either device.

Cout = output capacitance
= 21T x

~

Tuning can be accomplished by using the 10th or 100th
seconds with the device reset. The frequency on the
cathode should be tuned to 1066.667Hz, which is equivalent to a period of 937.5 microseconds. Note that a.
frequency counter cannot be connected directly to the
oscillator because of possible loading.

RS = series resistance

w

~

I\)

OSCILLATOR TUNING

[
Co (Cin + Cout) ]2
Cin Cout RS 1 + ....::..-'-''-'--'-':..::.::.
Cin 'Cout
Co = static capacitance

gm =

a

crystal frequency

The resulting gm should be less than half the gm
specified for the device. If it is not, a lower value of crystal

fI

7-35
Note: All typical values have been guaranteed by characterization and are not tested.

S ICM7216A/B/C/D
iii' 8-Digit Multi-Function

.... Frequency CounterITimer

=N

a

G~NERAL DESCRIPTION
The ICM7216A and B are fully integrated Timer Counters
with LED display drivers. They combine a high frequency
OSCillator, a decade timebasecounter, an 8-decade data
counter and latches, a 7-segment decoder, digit multiplexers and 8 segment and 8 digit drivers which directly drive
large multiplexed LED displays. The counter ihputs have a
maximum frequency of. 10MHz in frequency and unit
counter modes and 2MHz in the other modes. Both inputs
are digital inputs. In many applications, amplification and
level shifting will be required to obtain proper digital Signals
for these inputs.
The ICM7216A and B can function as a frequency
counter, period counter, frequency ratio (fA/fs) counter,
time interval counter or as a totalizing counter. The counter
uses either a 10MHz or 1MHz quartz crystal timebase. For
period and time interval, the 1OMHz timebase gives a 0.1 fJ.S
resolution. In period average and time interval average, the
resolution can be in the nanosecond range. In the frequency mode, the user can select accumulation times of 0.01
sec, 0.1 sec, 1 sec and 10 sec. With a 10 sec accumulation
time, the frequency can be displayed to a resolution of
0.1 Hz in the least significant digit. There is O~2 seconds
between measurements in all ranges.
The ICM7216C and 0 function as frequency counters \
only, as described above.
All versions of the ICM7216 incorporate leading zero
blanking. Frequency is displayed in kHz. In the ICM7216A
and B, time is displayed in fJ.S. The display is multiplexed at
500Hz with a 12.2% duty cycle for each digit. The
ICM7216A and C are deSigned for common anode display
with typical peak segment currents of 25mA. The
ICM7216B and 0 are designed for common cathode
displays with typical peak segment currents of 12mA. In the
display off mode, both digit and segment drivers are turned
off, enabling the display to be used for other functions.

FEATURES
ALL VERSIONS:
• Fun(:tions as a Frequency Counter (DC to
10MHz)
• Four Internal Gate Times: 0.01 Sec, 0.1 Sec,
1 Sec, 10 Sec in Frequency Counter Mode
• Directly Drives Digits and Segments of Large
Multiplexed LED Displays (Common Anode and
Common Cathode versions)
• Single Nominal 5V Supply Required
• Highly Stable OSCillator, Uses 1MHz or 10MHz
Crystal
• Internally Generated Decimal POints, Interdigit
Blanking, Leading Zero Blanking and Overflow
Indication
• Display Off Mode Turns Off Display and Puts
Chip Into Low Power Mode
• Hold and Reset Inputs for Additional Flexibility
ICM7216A AND ICM7216B
• Functions Also as a Period Counter, Unit
Counter, Frequency Ratio Counter or Time
Interval Counter
• 1 Cycle, 10 Cycles, 100 Cycles, 1000 Cycles in
Period, Frequency Ratio and Time Interval
Modes
• Measures Period From 0.5fJ.s to 10s
ICM7216C AND ICM7216D
• Decimal Point and Leading Zero Blanking May
Be Externally Selected

ORDERING INFORMATION
PART
, NUMBER

TEMPERATURE
RANGE

ICM7216A1D

-20·C to +85·C

DICE

ICM7216AIJL

-20·C to +85·C

28 pin CERDIP

PACKAGE

ICM7216B/D

-20·C to +85·C

DICE

ICM7216BIPI

-20·C to + 85·C

28 pin PLASTIC DIP

ICM7216BIJL

-20·C to + 85·C

28 pin CERDIP

ICM7216C/D

-20·C to + 85·C

DICE

ICM7216CIJL

-20·C to +85·C

28 pin CERDIP

ICM7216D/D

-20·C to + 85·C

DICE

ICM7216DIPI

-20·C to +85·C

28 pin PLASTIC DIP

ICM7216DIJL

-20·C to +85·C

28 pin CERDIP

7-36
Note: All typical values have been guaranteed by characterization and are not tested.

202815-002

I...

ICM7216A/B/C/D

...0>
II.)

.-

EXT
OIIC
INPUT

~~

DECQOER

SELECT

osc

OUlPUT

3

osc.

OIIC

INPUT

~

....-.-

r---

I

l-

I

,

REFERENCE
COUNTER

IJ-r-

I
I

INPUT

I

II

iJo

OIGIT

DRIVERS

1

r---1

RANGE SELECT
LOGIC

RANGE
CONTROL

~

Q

•
STOREANO
AESET LOGIC

-~

INPUT
CONTROL
LOGIC

INPUT A

-

EN
MAIN
-;- 101 COUNTER

CL

OVERFLOW

ofO , o to t, t'

INPUT 8

OATA LATCHES AND

(NOTE II

OU1PUTMUX

0

STORE!--

I
r---

CONTROL

-

INPUT
CONTROL
LOGIC

~

-'--

RANGE
''''U1

CONTROL

L--EXT
DP.
INPUT
lNOTE 2)

D.P.

f--

r-

'-r-

I...;
DECODER
LOGIC.

r+-

-

CL
MAIN
FF

~

a

f-o INPUT

lOGIC

0

"""01..0

L...

n
......

.LOGIC

r--

OUTPUTS
(81

l....-

'---

6

......

DIGIT

"os

,,040R.,QII } -

iiiiET

--•

.--SEGMENT
DRIVER

fh·

SEGMENT
OUTPUTS
(81

L--MEASURE MENTIN
PROGRESS OUTPUT

1........-

(NOTE 21

r-FUNCTION
INPUT (NOTE 1I

FN

CONTROL
LOGIC

~
HOLO

INPU T

PI

6
NOTES, 1) FUNCTION INPUT AND INPUT B AVAILABLE ON ICM7216A/8 ONLY.
2) EXT D.P. INPUT AND MEASUREMENT IN PROGRESS OUTPUT AVAILABLE ON

---

leM 7216C/D ONLY.
90008801

Figure 1: Functional Diagram

7-37
Note: All typical values have been guaranteed by characterization and are not tested.

D

'.D~DIL

()

""-

ICf.t7216A/B/C/D

iii

'ABSOLUTE MAXIMUM RATINGS

;,..

Maximum Supply. Voltage (VOO-VSS) .................. 6.5V
Maximum Digit Output Current ......................... 400mA
MaximUm, Segment Output Current ..................... 60mA
Voltage On Any Input or
Output Termin,aI[1j ....... Voo+0.3V to Vss-0.3V

~
co

B

Maximum Power Dissipation at·
70·C ............................. 1.0W (ICM7216A & C)
,
0.5W (ICM72168 & D)
Operating Temperature Range ........ ·... -20·C to +85·C
Storage Temperature Rimge ............ -55·C to + 125·C
Lead Temperature (Soldering, 10sec) ................ ;300·0

'Note: 1. The ICM7216 may be triggered into a destructive latchup mode if either input signals are applied before the power supply is applied or if input or
outputs are forced to voltages exceeding Voo to VSs by more than 0,3 volts.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the operational sl'ctions of the specifications is not implied. Exposure to
absolute maximum rating ~onditions for .extended periods may affept device reliability.

CONTROL INPUT

INWT A

CONTROl. INPUT

FUNCTION INPUT

HOLD INPUT
OSCOUTPUT

FUNCTION INPUT

OECIMAL POINT outPUT

OSC INPUT

SEG E OUTPUT
SEG G OUTPUT

EXT OSC INPUT

SEGAOUTPUT
v..

DIGIT 2 OUTPUT
DIGIT 3 OUTPUT

SEG D'OUTPUT
SEGBOUTPUT
SEGCOUTPui

DIGIT 4 OUTPUT
DIGIT 5 OUTPUT
VDD
DIGIT 6 OUTPUT
DIGIT 7 OUTPUT
DIGIT 8 OUTPUT'

SEG F OUTPUT

iiE!n' INPUT
RANGE INPUT

INPUTB
DIGIT 1 OUTPUT

DIGIT 1 OUTPUT

DIGIT 2 OUTPUT
DIGIT 4 OUTPUT
v..
DIGI·T 5 OUTPUT
DIGIT. OUTPUT
DIGIT 7 OUTPUT
DIGIT 8 OUTPUT

iiES£f INPUT
RANGE INPUT
COO2171I

CD021e11

CONTROL INPUT

INPUT A

INPUT A
HOLD INPUT
DSCDUTPUT

MEASUREMENT fA ~
DECIMAL I'OINT OUTPUT
SEG E OUTPUT
SEG G OUTPUT
SEG A OUTPUT
v..
SEGDOUTPUT
SEG8OUTPU~

SEGCOUTPUT
SEGFOUTPUT
iIHlf,NPUT
EX, D.P, INPUT
RANGE INPUT

OSCINPUT
EXT DSC INPLn;

EXT OSC INPUT
DIGIT 1 OUTPUT
DIGIT 2 OUTPUT

DECIMAL POINT OUTPUT
SEGGOUTPUT
SEGEOUTPUT
SEGAOUTPUT
SEGDOUTPUT
vDD

DIGIT 3 OUTPUT
DIGIT 4 OUTPUT
DIGIT 5 OUTPUT

SEG B OUTPUT
SEGcOUTPUT
SEG F OUTPUT

DIGIT 7 OUTPUT
,)IGIT 8 OUTPUT
COO21811

COO2e:311

Figure 2: Pin Configurations
ICM7226AIJL (Common Anode LED Display), a 10MHz
quartz crystal, eight 7 segment 0.3" LED's, P.C. board,
resistors, capacitors, diodes, switches, socket: everything
needed to quickly assemble a functioning ICM7226 Universal Counter System.

EVALUATION KIT
The ICM7226 Universal Counter System has all of the
features of the ICM7216 plus a number of additional
features. The ICM7226 Evaluation Kit consists of the

7-38
Note: All typical values have been guaranteed by characterization and are not tested.

..C~

ICM7216A/B/C/D
ELECTRICAL CHARACTERISTICS (ICM7216A/B)
(VDD = 5.0V ±5%, Vss = 0, T A = 25°C, unless otherwise specified,)
SYMBOL

PARAMETER

N

.'

TEST CONDITIONS

MIN

TYP

MAX

UNIT

2

5

rnA

6.0

V

ICM7216A/B
100

Operating Supply Current

Display Off, Unused Inputs to VSS

Supply Voltage Range (Voo - VSS)

-20'C < TA < + 85'C, INPUT A,
INPUT B Frequency at Imax

4.75

Maximum Frequency
INPUT A, Pin 28

-20'C < TA < +8S'C
4.75 < VOO 5 6.0V, Figure 3,
Function = Frequency, Ratio, Unit
Counter
Function = Period, Time Interval

10
2.5

MHz
MHz

VSUPPlY
IA(max)

Maximum Frequency
INPUT B, Pin 2

-20'C < TA < +BS'C
4.75 < VOO:S 6.0V,
Figure 4

2.5

..MHz

Minimum Separation
INPUT A to INPUT B
Time Interval Function

-20'C < TA < +8S'C
4.75 < VOO :s 6.0V,
Figure 5

250

ns

lose

Maximum Osc. Freq. and Ext.
Osc. Frequency

-20'C < TA < +8S'C
4.75 < VOO :s 6.0V

lose

Minimum Ext. Osc. Freq.

9m
fmux

Oscillator Transconductance

VOO = 4.7SV, TA = + 8S'C

Multiplex Frequency

lose = 10MHz
lose = 10MHz

IB(max)

Time Between Measurements

VINl
VINH
RIN

Input Voltages:
Pins 2,13,25,27,28
Input Low Voltage
Input High Voltage
Input Resistance to VOO
Pins 13,24

IllK

Input Leakage
Pin 27,28,2

dVIN/dt

Input Range 01 Change

10

!n!

MHz
100

-20'C

-"

2000

kHz
/lS

500

Hz

200

ms

< TA < +8S'C
1.0
3.5

VIN = VOO - 1.0V

100

400

kn
20

Supplies Well Bypassed

V
V

/lA

15

mV//ls

ICM7216A

IOH
IOl

Digit Driver:
Pins 15,16,17,19,20,21,22,23
High Output Current
Low Output Current

VOUT=Voo-2.0V
VOUT=VSS+l.0V

-140

-180
+0.3

rnA
rnA

IOl
IOH

SEGment Driver:
Pins 4,5,6,7,9,10,1'1,12
Low Output Current
High Output Current

VOUT= VSS+ I.SV
VOUT = Voo - 2.5V

20

35
-100

rnA

VINl
VINH
RIN

Multiplex Inputs:
Pins 1,3,14
Input Low Voltage
Input High Voltage
Input Resistance to VSS

VIN = VSS+ 1.0V

'/lA
0.8

2.0
50

100

V
V
kn

75
-100

rnA
/lA

ICM7216B

IOl
IOH

Digit Driver:
Pins 4,5,6,7,9,10,11,12
Low Output Current
High Output Current

VOUT = VSS+ 1.3V
VOUT=VoO-2.SV

50

IOH
ISLI(

SEGment Driver:
Pins 15,16,17,19,20,21,22,23
High Output Current
Leakage Current

VOUT = VOO-2.0V
VOUT = Voo - 2.SV

-10

VINl
VINH
RIN

Multiplex Inputs:
Pins 1,3,14
Input Low Voltage
Input High Voltage
Input Resistance to VOO

VIN = VOO - 2.SV

7--39
Note: All typical values have been guaranteed by characterization and are not tested.

Voo-0.8
100

mA

360

10

/lA

VoO-2.0

V
V
kn

PI

~ ICM7216A1B1C/D
.....
II ELECTRICAL CHARACTERISTICS
.....

(ICM7216C/D)

(Voo = 5.0V ±5%, Vss = 0, TA = 25°C,unless otherwise specified.)

=

H
po.

SYMBOL

I!

sa

PARAMETER

TEST CONDITIO"S

MI"

TYP

MAX

UNIT

2

5

mA

6.0

V

ICM7216C/D
100

Operating Supply Current

Display Off, Unused Inputs to 'ISS

VSUPPLY

Supply Voltage Range (Voo": 'Iss)

-20°C < TA < +85°C; INPUT A
Frequency at lmax

IA(max)

Maximum Frequency
INPUT A, Pin 28

_20°C <·TA < + 85°C
4.75 <'100 < 6.0'1, Figure 3

10

lose

Maximum Osc. Freq. and Ext.
Osc. Frequency

_20°C < TA < +85°C
4.75 < '100 < 6.OV

10

lose

Minimum EXt. Osc. Freq.

gm

Oscillator Transconductance

'100 =4.75'1, TA" +85°C

Imux

Multiplex Frequency

lose .. 10MHz

SOO

fJS
Hz

Time Between Measurements

lose·l0MHz

200

ms

VINL
VINH

Input Voltages:
Pins 12,27,28
Input Low Voltage
Input High Voltage

RIN

Input Resistance to '100
Pins 12,24

IILK

Input Leakage
Pin 27, Pin 28

IOL

4.75

MHz
MHz
100

2000

_20°C -- *""A

SIGNAL.

I!>--~'

-,,---,,--''''''0..
-,,WF017401

Figure 3: Waveform for Guaranteed
Minimum fA(max) Function Frequency,
Frequency Ratio, Unit Counter.

=

...

,

1N1,.

v..

T:'
v..
TC027B21

INPUT A OR
INPUT B

4.5V

DEVICE

O.5V

1

2

TYPE

CD4049B Inverting Buffer
CD4070B Exclusive-OR

WF017SOI

Figure 4: Waveform for Guaranteed
Minimum fs(max) and fA(max) for
Function = Period and Time Interval.

Figure 5: Priming Circuit, Signal A&B High
or Low.
Following the priming procedure (when in single event or
1 cycle range input) the device' is ready to measure one
(only) event.
When timing repetitive signals, it is not necessary to
"prime" the ICM7216A1B as the first alternating signal
states automatically prime the device. See Figure 5.
During any time interval measurement cycle, the
ICM7216A1B requires 200ms, following B going low to
update all internal logic. A new measurement cycle will not
take place until completion of this internal update time.

TIME INTERVAL MEASUREMENT
The ICM7216A1B can be used to accurately measure the
time interval between two events. With a 10MHz time-base
crystal, the time between the two events can be as long as
ten seconds. Accurate resolution in time interval measurement is 100ns.
The feature operates with Channel A going low at the
start of the event to be measured, followed by Channel B
going low at the end of the event.
When in the time interval mode anq measuring a single
event, the ICM7216A1B must first be !'primed" prior to
measuring the event of interest. This is done by first
generating a negative going edge on Channel A followed by
a negative going edge on Channel B to start the "measurement intervaL" The inputs are then primed ready for the
measurement. Positive going edges on A and B, before or
after the priming, will be needed to restore the original
condition.

7-42
Note: All typical values have been guaranteed by characterization and are not tested.

n

ICM7216A/B/C/D

...

I:

...N

--0)

~

III

n

FUNCTION:

I t'

TIME INTERVAL

(intern.lon

250rKMIN.

MEASURED
INTERVAL
IFIAST!

I
I--

I
--l

I--

MEASURED
INTERVAL
(LAST)

WF017601

NOTE: IF RANGE IS SET TO 1 .EVENT. FIRST AND LAST MEASURED INTERVAL WILL COINCIDE

Figure 6: Waveforms for Time Interval Measurement
(Others are similar, but without priming phase).

INPUT A

~'00pF

21
27

21

25
24

6
7

FR
TI.
U.C.

••

o.F.

23

1~

EXT

t---~------------------~~~---------------------+~~
D,
INPUT

Z2
21
20

I.

TY'ICAL CRYSTAL SPECS,
F· '0 MHz PARALLEL RESON~NCE
c 22pF
As· <3$0

CL

•• I - -.....

~VDO

17

I

'6
15

RANGE

0,
100m

•

I
.0./1
.1/10
1/'00
'OI1K

LEO

OVERFLOW
INOICATOR

"V

BBBBBBBB
LC02960J

Figure .7: Test Circuit (7216A shown; others similar)

7-43
Note: All typical values have been guaranteed by characterization and are not tested.

.--,

. ~ ICM7216A/B/C/D
ID

C

...
...

G

(II

D
I

~

~

:1

~

LC0178Q1

,

5
6

Overflow will be indicated on the decimal point output of digit e.
A separate LEO overflow indicator can be connected as follows:

S
9
LC017901

ICM7216A1C
ICM7216B/D

CATHODE

ANODE

DEC. PT.
De

De
DEC. PT.

Figure 8: Segment Identification and Display Font

DETAILED DESCRIPTION
INPUTS A and B

VDD. The chip will remain in this "Display Off" mode until
HOLD is switched back to VSS. While in the "Display Off"
mode, the segment and digit driver outputs are open, the
oscillator continues to run with a typical supply current of
1.5mA with a 10MHz crystal, and no measurements are
made. In addition, inputs to the multiplexed inputs will have
no effect. A new measurement is initiated when the HOLD
input is switched to VSS. Segment and Digit Drive outputs
may thus be bussed to drive a common display (up to 6
circuits).
·1 MHz Select - The 1MHz select mode allows use of a
1MHz crystal with the same digit multiplex rate and time
between measurements' as with a 10MHz crystal. The
decimal point is also shifted one digit to the right in Period
and Time Interval, since the least significant digit will be in
ps increments rather than O.lps increments.

INPUTS A and B are digital inputs with a typical switching
threshold of 2.0V at VDD = 5.0V. For optimum performance
the peak-to-peak input signal should be at least 50% of the
supply voltage and centered about the switching voltage.
When these inputs are being driven from TTL logic, it is
desirable to use a pullup resistor. Tt'le circuit counts high to
low transitions at both inputs. (INPUT B is available only on
ICM7216A1B).
Note: The amplitude of the input should not exceed the supply, otherwise,
the circuit may be damaged.

Multiplexed Inputs
The FUNCTION, RANGE, CONTROL and EXTERNAL
DECIMAL POINT inputs are time multiplexed to select the
input function desired. This is achieved by connecting the
appropriate Digit driver output to the inputs. The input
function, range and control inputs must be stable during the
last half of each digit output, (typically 125ps), The multiplex
inputs ai'e. active high for the common anode ICM7216A
and C and active low for the common cathode ICM7216B
and D.

External Oscillator Enable - In this mode the EXTERNAL OSCILLATOR INPUT is used instead of the on-chip
oscillator for Timebase input and Main Counter input in
period and time Interval modes. The on-Chip oscillator will
continue to function when the external oscillator is selected.
The external oscillator input frequency must be greater than
100kHz or the chip will reset itself to enable the on-Chip
oscillator. OSCillator INPUT (pin 25) must also be connected to EXT.OSC. input when using EXT.OSC. input.
External Decimal Point Enable - When external. decimal point is enabled a decimal point will be displayed
whenever the digit driver connected to EXTERNAL DECIMAL POINT input is active. Leading Zero Blanking will be
disabled for all digits following the decimal point (7216C/D
only).

Noise on the multiplex inputs can cause improper operation. This is particularly true when the unit counter mode of .
operation is selected, since changes in voltage on the digit
drivers can becapacitively coupled through the LED diodes
to the multiplex inputs. For maximum noise immunity, a
10kfl resistor should be placed in series with the multiplex
inputs as shown in the application circuits.
Table 1 shows the functions selected by each digit for
these inputs.

RANGE INPUT
The RANGE INPUT selects whether the measurement is
made for 1, 10, 100, 1000 counts ofthe reference counter.
In all functional modes except unit cou~ter a change in the
RANGE INPUT will stop the measurement in progress
without updating the display and then initiate a new
measurement. This prevents an erroneous first reading
after the RANGE INPUT is ,changed.

'CONTROL INPUT Functions
Display Test - All segments are enabled continuously,
giving a display of all 8's with,decimal points. The display
will be blanked if Blank Display is selected at the same time.
Display Off- To disable the drivers, it is necessary to
tie 04 to the CONTROL INPUT and havethe HOLD input at
7-44

Note: All typical valUes have Qaen guaranteed by characterization and are not tested.

ICM7216A/B/C/D
after the decimal point. This input is available on the
ICM7216C and 0 only.
HOLD Input - Except in the unit counter mode, when
the HOLD Input is at VDD, any measurement in progress
(before STORE goes low) is stopped, the main counter is
reset and the chip is held ready to initiate a new measurement as soon as HOLD goes low. The latches which hold
the main counter data are not updated, so the last complete
measurement is displayed. In unit counter mode when
HOLD input is at VDD, the counter is not stopped or reset,
but the display is frozen at that instantaneous value. When
HOLD goes low the count continues from the new value in
the counter.
RESET Input - The RESET input resets the main counter, stops any measurement in progress, and enables the
main counter latches, resulting in an all zero output. A
capaCitor to ground will prevent any hang-ups on power-up.

Table 1: Multiplexed Input Functions
FUNCTION
DIGIT
FUNCTION INPUT Frequency
D1
Pin 3
Period
D8
(ICM7216A & B
Frequency Ratio
D2
Only)
Time Interval
D5
Unit Counter
D4
Oscillator
D3
Frequency
RANGE INPUT
.01 sec/1 Cycle
D1
Pin 14
.1 sec/1 0 Cycles
D2
1 sec/1 00 Cycles
D3
10 sec/1 K Cycles
D4
CONTROL INPUT Blank Display
D4 and Hold
Pin 1
Display Test
D8'
1 MHz Select
D2
External Oscillator
D1
Enable
External Decimal
D3
Point Enable
EXT. D.P. INPUT
Decimal pOint is output for same
Pin 13, ICM7216C digit that is connected to this input
& D Only

DISPLAY CONSIDERATIONS
The display is multiplexed at a SOOHz rate with a digit time
of 244 IJ.S. An interdigit blanking time of 6 J.AS is used to
prevent ghosting between digits. The decimal point and
leading zero blanking assume right hand decimal point
displays, and zeros following the decimal pOint will not be
blanked. Also, the leading zero blanking will be disabled
when the Main Counter overflows. Overflow is indicated by
the decimal point on digit 7 turning on.
The ICM7216A and C are designed to drive common
anode LED displays at peak current of 2SmAi segment,
using displays with VF = 1.8V at 2SmA. The average DC
current will be over 3mA under these conditions. The
ICM7216B and 0 are deSigned to drive common cathode
displays at peak current of 1SmAisegment using displays
with VF = 1.8V at 1SmA. Resistors can be added in series
with the segment drivers to limit the display current in very
efficient displays, if required. The Typical Performance
Characteristics curves show the digit and segment currents
as a function of output voltage.
To get additional brightness out of the displays, VOO may
be increased up to 6.0V. However, care should be taken to
see that maximum power and current ratings are not
exceeded.
The segment and digit outputs in ICM7216's are not
directly compatible with either TTL or CMOS logic when
driving LEOs. Therefore, level shifting with discrete transistors may be required to use these outputs as logic Signals.

FUNCTION INPUT
The six functions that can be selected are: Frequency,
Period, Time Interval, Unit Counter, Frequency Ratio
and Oscillator Frequency. This input is available on the
ICM7216A and B only.
These functions select which signal is counted into the
Main Counter and which signal is counted by the Reference
Counter, as shown in Table 2. In all cases, only 1 ~O
transitions are counted or timed. In time Interval, a flip-flop
is toggled first by a 1 ~ 0 transition of INPUT A and then by a
1 .... 0 transition of INPUT B. The oscillator is gated into the
Main Counter from the time INPUT A toggles the flip-flop
until INPUT B toggles it. In unit counter mode, the main
counter contents are continuously displayed. A change in
the FUNCTION INPUT will stop the measurement in progress without updating the display and then initiate a new
measurement. This prevents an erroneous first reading
after the FUNCTION INPUT is changed.
Table 2: 7216A1B Input Routing
REFERENCE
COUNTER

DESCRIPTION
Frequency (fA)

MAIN COUNTER
Input A

Period (tA)
Ratio (fA/fB)
Time Interval
(A_B)

Oscillator
Input A
Osc.(Time
Interval FF)

Unit Counter
(Count A)

Input A

N'ot Applicable

Osc. Freq.
(fose)

Oscillator

100 ~z (OSCillator
.;. 10 or 104)

100 Hz (Os.f,illator
';'10 5 or 10 )

ACCURACY

Input A
Input B

In a Universal Counter crystal drift and quantization
effects cause errors. In frequency, period and time
interval modes, a Signal derived from the oscillator is used
in either the Reference Counter or Main Counter. Therefore,
in these modes an error in the oscillator frequency will
cause an identical error in the measurement. For instance,
an oscillator temperature coefficient of 20ppm/oC will
cause a measurement error of 20ppmrC.
In addition, there is a quantization error inherent in any
digital measurement of ± 1 count. Clearly this error is
reduced by displaying more digits. In the frequency mode
the maximum accuracy is obtained with high frequency
inputs and in period mode maximum accuracy is obtained
with low frequency inputs. As can be seen in Figure 9, the
least accuracy will be obtained at 10kHz. In time Interval

Time Interval FF

EXTernal DECimal Point INput
When the external decimal point is selected this input is
active. Any of the digits, except 08, can be connected to
this point. 08 should not be used since it will override the
overflow output and leading zeros will remain unblanked
7-45
Note:

All typical values have been guaranteed

by characterization and are not tested,

.·.U~UIl

~ ICM7216A/B/C/D

-=......
......

III

CII

a

measurements there can be an error of 1 count per interval.
As a result there is the same inherent accuracy in ali-ranges
as shown in Figure 10. In frequency ratio measurement
can be more accurately obtained by averaging over more
cycles of INPUT B as shown in Figure 11.

Ii

'~

~

Mlx,MUM TIME

"-

INTERVAL

FOR 103 '/ERjALS

"'- / .----"'-

I

~'ME

MAX;MUM
INTERVAL FOR
'02 '~ERVALS

'""-

MAXIMUM TIME INTERVAL_
fFO~'O IN~ERVAlS
10

102

103

104

105

106

107

10B

'TIME INTERVAL (~.IS)

OP040701

Figure 10: Maximum Accuracy of Time
Interval Measurement Due to Limitations
of Quantization Errors
fREQUENCY 1Hz)
OP040601

Figure 9: Maximum Accuracy of
Frequency and Period Measurements Due
to Limitations of Quantization Errors··

oP040eOI

Figure 11: Maximum Accuracy for
Frequency RatiO Measurement Due .to .
Limitation of Quantization Errors

7-46
Note: All typical values have been guaranteed by characterization and are not tested.

i...

ICM7216A/B/C/D

...
~

Yeo

22M!2

FREQUENCY

PERIOD
FREQUENCV RATIO

TIME INTE RVAl

0,

0,

0.

1OkO 03

0,

0,

0.

O.

28
27
26
25
2.
23
leM 22
72168 21
20
10
19
11
18
17
12
13
16

,.

DRIVERS

Yeo

10k!!

.......
II
.......
n
.......

=
o

10MHz
CRYSTAL

~~D

D.P.
G

10kn

A

0

1--+--4---------------------------~==========~~---_--+

'Ok!!

FREC.

D.

I . COMMON ANODE LED DISPLAV I

PERIOD
FREQ. RATIO

BBBBBBBB.

02'

LED

=~~~~'V

0,

LC018311

Figure 15: 100MHz Multifunction Counter

OSCILLATOR CONSIDERATIONS
The oscillator is a high gain complementary FET inverter.
An external resistor of 10Mn to 22Mn should be connected between the OSCillator INPUT and OUTPUT to provide
biasing .. The oscillator is designed to work with a parallel
resonant 1OMHz quartz crystal with a static capacitance of
22pF and a series resistance of less than 35 oh(11s.

The required gm should nqt exceed 50% of the gm
specified for the ICM7216 to insure reliable' startup. The
OSCillator INPUT and OUTPUT pins each contribute about
5pF to Cin and Couto For maximum stabilitY of frequency, Cin
and Cout should be approximately twice the specified
crystal static' capacitance.
.

For a specific crystal and load capacitance, the required
gm can be calculated as follows:

In cases where non decade prescalers are used it may be
desirable to use a crystal which is neither 10MHz or 1MHz.
In that case both the multiplex rate and time between
measurements will be different. The multiplex rate

gm

= J.

Cin Cout R+ +

~~)2

.

f08c

f05c

isfmux = ---4 for 1OMHz mode and fmux = ---3 for the
2x10
2x10
6
2 x 10
1MHz mode. The time between measurements is - - - in

where CL = (_C.::.in:...C..:o.::ut:... \
Cin+ CouJ

f05c

2x 105
the 10MHz mode and - - - in the 1MHz mode.

Co = Crystal Static Capacitance

f08c

RS = Crystal Series Resistance

The crystal and oscillator components should be located
as close to the chip as practical to minimize pickup from
other Signals. Coupling from the EXTERNAL OSCILLATOR
INPUT to the OSCILLATOR OUTPUT or INPUT can cause
undesirable shifts in oscillator frequency.

Cin = Input Capacitance
Cout = Output Capacitance

w

= 27rf

7-50
Note: All typical values have been guaranteed by characterization and are not tested:

ICM7216A/B/C/D

' ....n
22MSl

24

•

,eM

0,

23
22

0,
0,

n16A 21

O.

I.
I.
20
It

"-

17

0,.0,

"

e"

YIJO

~
0,
10k!!

0,
0,

COMMON ANODE LED DISPLAY

D.

I

BBBBBBBB~
lED OVERFLOW
INDICATOR

~+-~

__

~

____

~

____+-__

~~

__-*____

~

____

0,

~~~

__

~-J

LC029701

Figure 16: 100MHz Frequency, 2MHz Period Counter

~r-------r-------~------,

l'r-------~------~~~----_4

!

~

~

ffi

S
...a:

10~--------t_--------+---------4
fA __ • fa '_I PERIOD.
nME INTERVAL MODES

Voo - Vss (VOLTS)
OP040911

voo
Figure 17: Typical Operating Characteristics
fA(max), fB(max) as a Function of

7-51
Note: All typical values have been guaranteed by characterization and are not tested.

PI

~:.:t~~~/~~:a~~~~rammable
.U~OlL
Up/Down Counter
GENERAL DESCRIPTION

FEATURES

The ICM7217 and ICM7227 are four digit, presettable up/
down counters, each with an onboard presettable register
continuously compared to the counter. The ICM7217 ver, sions are intended for use in hardwired applications where
thumbwheel switches are used for loading data, and simple
SPOT switches, are used for chip control. The ICM7227
versions are for use in processor-based systems, where
presetting and control functions are performed under processor control.
'
These circuits provide multiplexed 7 segment LED dis, play outputs, with common anode or common cathode
configurations available. Digit and segment drivers are
provided to directly drive displays of up to 0.8" character
height (common anode) at a 25% duty cycle. The frequency
of the onboard multiplex oscillator may be controlled with a
single capacitor, or the oscillator may be allowed to free
run. Leading zeros can be blanked. The data appearing at
the 7 segment and BCD outputs is latched; the content of
the counter is transferred into the latches under external
control by means of the Store pin.
The ICM7217/7227 (comll)on anode) and ICM7217A1
7227A (common cathode) versions are decade counters,
providing a maximum count of 9999, while the ICM7217B,
7227B (common anode) and ICM7217C/7227C (common
cathode) are intended for timing purposes, providing a
maximum count of 5959.
These circuits provide 3 main outputs; a CARRY /BORROW output, which allows for direct cascading of counters,
a ZERO output, which indicates when the count is zero, and
an EQUAL output, which indicates when the count is equal
to the value contained in the regi!?ter . .Data is multiplexed to
and from the device by means of a three-state BCD I/O
port. The CARRY/BORROW, EQUAL, ZERO outputs, and
the BCD port will each drive one standard TTL load.
To permit operation in noisy environments and to prevent
multiple triggering with slowly changing inputs, the count
, input is provided with a Schmitt trigger.
Input frequency is guaranteed to 2M Hz, although the
device will typically run with fin as high as 5MHz. Counting
and comparing (EQUAL output) will typically run 750kHz,
maximum.

•

Four Decade, Presettable Up-Down Counter With
Parallel Zero Detect
• Settable Register With Contents Continuously
Compared to Counter
• Directly Drives Multiplexed 7 Segment Common
Anode or Common Cathode LED Displays
• , On-Board Multiplex Scan Oscillator
• Schmitt Trigger On' Count Input
• TTL Compatible BCD I/O Port, Carry/Borrow,
Equal, and Zero Outputs
• Display Blan" Control for Lower Power
Operation; Quiescent Power Dissipation < SmW
• All Terminals Fully Protected Against Static
Discharge
• Single 5V !i)upply Operation

ORDERING, INFORMATION
PART
NUMBER
ICM72171JI

PACKAGE

DISPLAY
OPTION

28 Lead CERDIP Common Anode

COUNT
OPTION
MAX COUNT
Decade/9999

ICM7217AIPI 28 Lead PLASTIC Common Cathode Decade/9999
ICM7217BIJI

28 Lead CERDIP Common Anode

Timer/S9S9

ICM7217CIPI 28 Lead PLASTIC Common Cathode Timer/5959
ICM72271J1

28 Lead CERDIP Common Anode

Decade/9999

ICM7227AIPI 28 Leail PLASTIC Common Cathode Decade/9999
ICM7227BIJI

28 Lead CERDIP Common Anode

Timer/S9S9

ICM7227CIPI 28 Lead PLASTIC Common Cathode Timer/S9S9
ICM7217/D

DICE

ICM7217A/D

DICE

ICM7217B/D

DICE

Common Anode

ICM7217C/D

DICE

Common Cathode Timer/S9S9

ICM7227/D

DICE

Common Anode

ICM7227A1D

DICE

Common Cathode Decade/9999

ICM7227B/D'

DICE

Common Anode

ICM7227C/D

DICE

Common Cathode Timer/S9S9

7-52
Note: All typical values have been guaranteed by characterization and are not tested,

Common Anode

Decade/9999

' Common Cathode Decade/9999
Timer/59S9
Decade/9999
Timer/S9S9

202816-002

ICM7217/ICM7227

----+-01..
ftlilj---+--I ..IIO
uplliii ---+-I'UIO
COUNT -~~+-I

r---1===;r===t~~~!~~~~~~~==~===[CAARY/.ORROW
,.,
2·,

,.,

MUX.

OSCILLATOR

!-----SCA.

D4 D3D2Dl

8DOO9oo1

Figure 1: ICM7217 Functional Diagram

l"iliiS---+--I
COUNT

---+-~

r---!===1===9~~$ij~~~~~g~==~==~~-_CA.RRY/I!IOfl:ROW
w.

L..:======~s

80009101

Figure 2: ICM7227 Functional Diagram

7-53
Note: All typical values have been guaranteed by characterization and are not tested.

.CPtt721711CM7227
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VDD - Vss) ............................... 6V
Input Voltage (any terminal) ....................... VSS +O.3V,
Vss -O.3V Note 2
Power Dissipation (common anode/Cerdip) ... 1W Note 1

Power Dissipation (common cathode/Plastic) ........ O.5W
Note 1
Operating Temperature Range ........... -25°C to +85°C
Storage Temperature Range ............ -55°C to + 125°C
Lead Temperature (Soldering, 10sec) ................. 300°C

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent device failure. These are stress ratings only and functional
operation of the devices at these or any other cond~ions above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may cause device failures.

D1
D2
D3

CARRY/BORROW

%!1m
ImJA[
BCD 1108's

D4

BCD 1/04's

VDD

BCD I/O 8's
BCD 1104's
BCD I/O 2'.
BCD I/O 1's
COUNT INPUT
STORE
UPIDOWN
SC1
SC2
~O·AT¥A
..
TR~A~NwS
..F~E~R

DISPLAY CONT.

22 !1m.
2
20 Vss

srob

!1m.
!lEG,
"-11_ _ _ _ _-

SEGo
SEQb
SEG,
SEGc
VDD
SEG.
SEG.
SEGg
DISPLAY CONT.

!lEGo
!lEG.

Vss
D1
02
03

CWS .........._ _ _ _..t= D4

SEGc
CD021911

CO022011

COMMON ANODE

COMMON CATHODE

Figure 3: Pin Configurations (Outline dwgs JI., PI)

ELECTRICAL CHARACTERISTICS

(VDD

= 5V

±10%, Vss

= OV,

TA = 25°C, Display Diode Drop 1.7V, unless

otherwise specified)
SYMBOL
100

(7217)
100

(7227)

TYP

MAX

UNIT

Supply Current
(Lowest power mode)

PARAMETER

Display Off, LC, DC, UPIDN,
ST, RS, BCD I/O Floating or at Voo (Note 3)

350

500

jlA

Supply current
(Lowest power mode)

Display off (Note 3)

300

500

lOp

Supply Current
OPERATING

. VOO

Supply Voltage

TEST CONDITIONS

Common Anode, Display On, all "8's"
Common Cathode, Display On, all "8' s"

MIN

140

200

IlA
rnA
rnA

50

100

4.5

5

140

200

rnA
peak

-20

-35

rnA
peak

-50

-75

rnA
peak

5.5

V

IOIG

Digit Driver output
current

Common anode, VOUT - Voo -2.0V

ISEG

SEGment driver
output current

Common anode, VOUT =

IOIG

Digit Driver
output current

.Common cathode, VOUT =

ISEG

SEGment driver
output current

Common cathode VOUT = Voo -2V

9

12.5

rnA
peak

Ip

ST,

VOUT=VDD-2V (See Note 3)

5

25

IlA

liN

3 level input impedance

VSIH

BCD I/O input
high voltage

RS, UP/DN input
pullup current

+ 1.5V
+ 1.0V

40
ICM7217 common anode (Note 4) (VOO = 5.0V)
ICM7217 common cathode (Note 4)
ICM7227 with 50pF effective load

VSll

BCD I/O input
low voltage

75

kn

1.5

V

4.40

V

3

V

ICM7217 common anode (Note 4) (VOO = 5.0V)

0.60

ICM7217 common cathode (Note 4)

3.2V

V

1.5

V

ICM7227 with 50pF effective load

7-54
Note: All typical values have been guaranteed by characterization and are not tested.

V

n
a::::

ICM7217/ICM7227
SYMBOL

PARAMETER

TEST CONDITIONS

MAX

UNIT

MIN

TYP

Ispu

BCD 1/0 input
pullup current

ICM7217 common cathode VIN = VOO - 2V (Note 3)

5

25

/lA

Ispo

BCD 1/0 input
pulldown current

ICM7217 common anode VIN = + 2V (Note 3)

5

25

/lA

VOH

BCD 1/0, ZERO, EQUAL Outputs
output high current

IOH = 100/lA

3.5

VOL

BCD 1/0, CARRY IBORROW
ZERO, EQUAL Outputs
output low current

IOL = -1.SmA

fin

Count input frequency
(Guaranteed)

VOO=5V±10%, -20·C 60iJA. A 10kn pull-up resistor
to Voo on the EQUAL or ZERO outputs is recommended
7-56

Nole: All typical values have been guaranleed by characlerization and are not tested.

....~I\)
.......

ICM7217/ICM7227

-i
....
....

I\)
I\)

INTERNAL

[~
_D2~

(SCDAND
SEGMENT
ENABI.E)

EXTERNAL
(COMMON
ANODE)

DIGIT
STROBES

________________________

o.--,~

~

__________________________________________

l-~:......----------!k--!
_D2~

~

--Jr-

INTERDIGIT BLANK
______________________________

o.--,~

____ ____________________
~

~

L
WF017701

Figure 5: Multiplex Timing

SYMBOL
tucs
tUCh
tCUh
tCUI
tCB
tBw
tCEI·
tCZI

DESCRIPTION

MIN

UP/DOWN setup time (min)
UP/DOWN hold time (min)
COUNT pulse high (min)
COUNT pulse low (min)
COUNT to CARRY/
BORROW delay
CARRY/BORROW pulse
width
COUNT to EQUAL delay
COUNT to zrnc5 delay

TYP

MAX

UNIT

300

a

100 250
100 250
750

ns

100
500
300

PI

WF017801

Figure 6: ICM7217/27 COI,jNT and Output Timing

Multiplex SCAN Oscillator

width is used to delay the digit driver outputs, thereby
providing inter-digit blanking which prevents ghosting. The
digits are scanned from MSO (04) to LSO (01). See Figure
4 for the display digit multiplex timing.
Table 1: ICM7217. Multiplexed Rate Control

The on-poard multiplex scan oscillator has a nominal
free-running frequency of 2.5kHz. This may be reduced by
the addition of a single capacitor between the SCAN pin
and the positive supply. Capacitor values and corresponding nominal oscillator frequencies,. digit repetition rates, and
, loading times (for ICM7217 versions) are shown in Table 1
below.

NOMINAL
DIGIT
SCAN CYCLE
TIME
OSCILLATOR REPETITION
SCAN
(4 digits)
RATE
CAPACITOR FREQUENCY

The internal oscillator output has a duty cycle of approximately 25:1, providing a short pulse. occurring at the
oscillator frequency. This pulse clocks the four-state counter which provides the four multiplex phases. The short pulse

None

2.5kHz

625Hz

1.6ms

20pF

1.25kHz

300Hz

3.2ms

90pF

600Hz

150Hz

8ms

7-57
Note: All typical values have been guaranteed by characterization and are not tested.

ICM7217/ICM7227
VDD = IV
SCAN INPUT
ICM7217

SCAN INPUT
ICM7217

••

20KII

c
1MlI

20011

500!!

SCAN INPUT
ICM7217

1M!!
.OlI-'F

08022001

ov
SC009411

Figure 7: Brightness Control Circuits
During load counter and load register operations, the
multiplex oscillator is disconnected from the SCAN input
and is allowed to free-run. In all other conditions, the
oscillator may be directly overdriven to about 20kHz,
however the internal oscillator signal will be of the same
duty cycle and phase as the overdriving signal, and the
digits are blanked during the time the external signal is at a
positive level. To insure proper leading zero blanking, the
interdigit blanking time should not be less than about 2j.1s.
Overdriving the oscillator at less than 200Hz may cause
display flickering.

LOADing the COUNTER and REGISTER
The BCD I/O pins, the LOAD COUNTER (LC), and LOAD
REGISTER (LR) pins combine to provide presetting and
compare functions. LC and LR are three-level inplits, being
self-biased at approximately 1/2VOO for normal operation.
With both LC and LR open, the BCD I/O pins provide a
multiplexed BCD output of the latch contents, scanned from
MSD to LSD by the display multiplex.
When either the LOAD COUNTER (Pin 12) or LOAD
REGISTER (Pin 11) is taken high, the drivers are turned off
and the BCD pins become high-impedance inputs. When
LC is connected to VOO, the count input is inhibited and the
levels at the BCD pins are multiplexed into the counter.
When LR is connected to Voo, the levels at the BCD pins
are multiplexed into the register without disturbing the
counter. When both are connected to VOO, the count is
inhibited and both register and counter will be loaded .
The LOAD COUNTER and LOAD REGISTER inputs are
edge-triggered, and pulsing them high for 500ns at room
temperature will initiate a full sequence of data entry cycle
operations (see Figure 7). When the circuit recognizes that
either or both of the LC or LR pins input is high, the
multiplex oscillator and counter are reset (to D4). The
internal oscillator is then disconnected from the SCAN pin
and the preset circuitry is enabled. The oscillator starts and
runs with a frequency determined by its internal capaCitor,
(which may vary from chip to chip). When the chip finishes a
full 4 digit multiplex cycle (loading each digit from D4 to· D3
to D2 to D1 in turn), it again samples the LOAD REGISTER
and LOAD COUNTER inputs. If either or both is still high, it
repeats the load cycle, if both are floating or low, the
oscillator is reconnecte.d to the SCAN pin and the chip
returns to normal operation. Total load time is digit "on"
time multiplied by 4. If the Digit outputs are used to strobe
the BCD data into the BCD I/O inputs, the input will be
automatically synchronized to the appropriate digit (Figure
8). Input data must be valid at the trailing edge of the digit
output.
When LR is connected to GROUND, the oscillator is
inhibited, the BCD 110 pins gO.to the high impedance state,
and the segment and digit drivers are tu.rned off. Ttlis allows
the display to be used for other purposes and minimizes
power consumption. In this display off condition, th~t
will continue to count, and the CARRY/BORROW, EQUAL,
ZERO, UP/DOWN, RESET and STORE functiOnS operate
as normal. When LC is connected to ground, the BCD I/O
pins arefon,ed to. the high impedance state without
disturbing' the counter or register. See "Control Input

The display brightness may be altered by varying the duty
cycle. Figure 7 shows several variable-duty-cycle oscillators
suitable for brightness control at the ICM7217 SCAN input.
The inverters should be CMOS CD4000 series and the
diodes 'may be any inexpensive device such as IN914.

. Counting Control
As shown in Figure 6, the counter is incremented by the
rising edge of the COUNT INPUT signal when UP/DOWN is
high. It is decremented when UP/DOWN is low. A Schmitt
trigger on the COUNT INPUT provides hysteresis to prevent
double triggering on slow rising edges and permits operation in noisy environments. The COUNT INPUT is inhibited
during reset and load counter operations.
The STORE pin controls the internal latches and consequently the signals appearing at the 7-segment and BCD
outputs. Bringing the STORE pin low transfers the contents
of the counter into the latches.
The counter is asynchronously reset to 0000 by bringing
the RESET pin low. The circuit performs the reset operation
by forcing the BCD input lines to zero, and "presetting" all
four decades of counter in parallel. This affects register
loading; if LOAD REGISTER is activated when the RESET
input is low, the register will also be set to zero. The
STORE, RESET and UP/DOWN pins are provided with
pullup resistors of approximately 75kU.

BCD I/O Pins
. The BCD I/O port provides a means of transferring data
to and from the device~ The ICM7217 versions can multiplex
data into the counter or register via thumbwheel switches,
depending on inputs to the LOAD COUNTER or LOAD
REGISTER pins; (see below). When functioning as outputs,
the BCD I/O pins will drive one standard TTL load.
Common anode versions have internal pull down resistors
and common cathode versions hlilve internal pull up resistors on the four BCD I/O lines as inputs.
7-58

Note: All typical values have been guaranteed by characterization and are not tested.

n
I:

ICM7217/ICM7227
Definitions" (Table 2) for a list of the pins that function as
three-state self-biased inputs and their respective operations.
Note that the ICM7217 and 7217B have been designed
to drive common anode displays. The BCD inputs are high
true, as are the BCD outputs.
The ICM7217A and the 7217C are used to drive common
cathode displays, and the BCD inputs are low true. BCD
outputs are high true.

reliable power-up reset and a fast rise time on the RESET
input is shown below.

--~----~~~------Y~

iiiiiT INPUT
leM'II1?

IKO

--------~~~------Ya

The thumbwheel switches used with these circuits (both
common anode and common cathode) are TRUE BCD
coded; i.e. all switches open corresponds to 0000. Since
the thumbwheel switches are connected in parallel, diodes
must be provided to prevent crosstalk between digits. See
Figure 8. In order to maintain reasonable noise margins,
these diodes should be specified with low forward voltage
drops (IN914). Similarly, if the BCD outputs are to be used,
resistors should be inserted in the Digit lines to avoid
loading problems.

TC02B011

Figure 8
When using the circuit as a programmable divider (+ by n
with equal outputs) a short time delay (about 1/.1s) is needed
from the EQUAL output to the RESET input to establish a
pulse of adequate duration. (See Figure 9)

Output and Input Restrictions

Dc

The CARRYIBORROW output is not valid during load
counter and reset operations.
The EQUAL output is not valid during load counter or
load register operations.
The ZERO output is not valid during a load counter
operation.
The RESET input may be susceptible to noise if its input
rise time (coming out of reset) is greater than about 500/.ls.
This will present no problems when this input is driven by
active devices (i.e., TTL or CMOS logic) but in hardwired
systems adding virtually any capacitance to the RESET
input can cause trouble. A simple circuit which provides a

iC5iJi[

f

YDD
.7",

~,......---~O---

________-o, IIIIIT
TC028111

Figure 9
When the circuit is configured to reload the counter or
re ister with a new value from the BCD lines (upon reaching
E UAL), loading time will be digit "on" time multiplied by
four. If this load time is longer than one period of the input
count, a count can be lost. Since the circuit will retain data
in the register, the register need only be updated when a
new value is to be entered. RESET will not clear the
register.

LOAl> COUNrER
(OR LOAD REGISTER)
·GNO

DO

DO

DO

D1

INTERNAL
OPERAnNG
MODE

INPUT
OUTPUT _ _ _ _....

BCD I/O

-r -

- -

-

• = HIGH IMPEDANCE
THREE-STATE W PULLDOWN
WF01791I

Figure 10: ICM7217 BCD 1/0 and Loading Timing

.7-59
Note: All typical values have been guaranteed by characterization and are not tested, .

-a
N

N
N

N.D.,

Notes on Thumbwheel Switches &
Multiplexing

...
......
...
...

.U~U[b

ICM7217/ICM7227
TO D4 STROBE

TO D1 STAOBE

TOD4STROBE

TO 01 STR08E

IN9'4 OR
EQUIVALENT

,8,

I
TO BCD INPUTS Of 7217, 72178

i

/

TO BCD INPUTS OF 7217A. 7217C
CD022101

Note: If the BCD pins are to be used for outputs a 10kn resistor should be placed in series with each digit line to avoid loading problems through the
switches.

Figure 11: Thumbwheel Switch/Diode Connections
Table 2: Control Input Definitions ICM7217
INPUT

TERMINAL

VOLTAGE

~

9,

UP/DOWN

10

RESET

14

LOAD COUNTER/
I/O OFF

12

LOAD REGISTER/

11

Voo (or floating)
Vss.
Voo (or floating)
VSS
Voo (or floating)
Vss
Unconnected
VOO
Vss
Unconnected
Voo
VSS

OFF

DISPLAY CONTrol
(DC)

23 Common Anode
20 Common Cathode

FUNCTION
Output latches not updated
Output latches updated
Counter counts up
Counter counts down

,

Normal Operation
Counter Reset
Normal operation
Counter loaded with BCD data
BCD.. port forced to Hi Z condition
Normal operation
Register loaded with BCD data
Display drivers disabled; BCD port
forced to Hi Z condition, mpx' counter
reset to 04; mpx oscillator inhibited

Unconnected
Voo
VSS

Normal Operation
Segment drivers disabled
Leading zero blanking inhibited

Table 3: Control Input Definitions ICM7227 '
INPUT

Control
Word
Port

"

TERMINAL

VOLTAGE

DATA TRANSFER

13

Voo
Vss

STORE

9

UP/DCSWN

10

Select Code Bit 1 (SCI)
Select Code Bit 2 (SC2)

11
12

VOO (During
Vss
Voo (During
VSS
VOO="I"
VSS"" "0"

Control Word Strobe (CWS)

14

2"

DISPLAY CONTrol (DC)

23 Common Anode .
20 Common Cathode

FUNCTION
Normal Operation
Causes transfer of data
as directed by select code

CWS

Pul~e)

Output latches updated
Output latches not updated

CWS

Pulse)

Counter counts up
Counter counts down
SCI, SC2 control:00 Change store jIIld
up/down latches. No data
transfer. 01 Output latch
data active
10 Counter to be preset
11 Register to be preset

Voo
Vss

Normal operation
Causes control word. to be
written into control latches

Unconnected
Voo
Vss

Normal operation
Display drivers disabled
l.,eading zero blanking
inhibited

7-00
Note: All typical values have been guaranteed by characterization and are not tested.

ICM7217/ICM7227
. ~-"'"

cws
-

IN"; --..:...I.
&&.iii&iif_

r

INPUT

.1

I

ISCS

;' ""==1

It---IO'.-'r-__~

--!

u

Ise"

~

L-J

,

~'---..-I!I'fM»C*~~Il.i*
I

.

SC1,SC2 LATCHES RESET
U/O

~m~~--T.mm
I SC' IItl

REGISTER WRITE CVC1.E (SC1.SC2

(COUNT,.

1,1)

W.,TE CYCLE IS SIMILA., SC'. sc.

',0)

LSC'=~~I'OO~~~

BCDIIC

.{SC,~~_
sc.

mmE.--t.ma

DATA OUTPUT CYCLE (SCI,se:!: '" 0,1)

"O~mmmmam~~~;~~~m~IC==J\lmaim~:::=:Jmimm~c=::JG~~

OUTPU"Y.
BCD

ITO!

~

'" OONT CARE"

0: CONTROL WORD INPUTS

WF018001

Figure 12: ICM7227 I/O Timing (see Table 4)
The sequence of digits will be D4-D3-D2-D1, i.e. when
outputting, the data from D4 will be valid during the first DT
pulse, then D3 will be valid during the second pulse, etc,
When presetting, the data for D4 must be valid at the
positive:going transition (trailing edge) of the first DT pulse,
the data for D3 must be valid during the second DT pulse,
etc..
At the end of a data transfer operation, on the positive
going transition of the fourth DT pulse, the SC1 and SC2
control latches will automatically reset, terminatirig the data
transfer and reconnecting the multiplex counter clock to the
oscillator. In the ICM7227 versions, the multiplex oscillator
is always free-running, except during a data transfer
operation when it is disabled.
Figure 12 shows the timing of data transfers initiated with
a 11 select code (writing into the register) and a 01 select
code (reading out of the output latches). Typical times
during which data must be valid at the control word and
BCD I/O ports are indicated in Table 4.
Table 4: ICM7227 I/O Timing Requirements

CONTROL OF ICM7227 VERSIONS
The ICM7227 series has been designed to permit microprocessor control of the inputs. BCD inputs and outputs are
active high.
In these versions, the STORE, UP/DOWN, SC1 and SC2
(Select Code bits 1 and 2) pins form a four-bit control word
.input. A negative-going pulse on the CWS (Control Word
Strobe) pin writes the data on these pins into four internal
control latches, and resets the multiplex counter in preparation for sequencing a data transfer operation. The select
code 00 is reserved for changing the state of the Store and/
or Up/Down latches without initiating a data transfer.
Writing a one into the Store latch sets the latch and causes
the data in the counter to be transferred into the output
latches, while writing a zero resets the latches causing them
to retain data and not be updated. Similarly, writing a one
into the Up/Down latch causes the counter to count up and
writing a zero causes the counter to count down. The state
of the Store and Up/Down latches may also be changed
with a non-zero select code.

SYMBOL

ICWS

Writing a nonzero select code initiates a data transfer
operation. Writing select code of 01 (SC1, SC2) indicates
that the data in the output latches will be active and enables
the BCD I/O port to output the data. Writing a select code cif
11 indicates that the register will be preset, and a 10
. indicates that the counter will be preset.

tiCs

IDi'w
tscs
tSCh
tlDs
tlDh
trDacc
trD!

When a nonzero select code is read, the clock of the
four-state multiplex counter is switched to the DATA
TRANSFER pin. Negative-going pulses at this pin then
sequence a digit-by-digit data transfer, either outputting
data or presetting the counter or register as determined by
the select code. The output drivers ofthe BCD I/O port will
be enabled only while DT is low during a data transfer
initiated with a 01 select code.
7-01

Note: An typical values have been guaranteed by characterization and are not tested:

DESCRIPTION
Control Word Strobe Width (min)
Internal Control Set·up (min)
DATA TRANSFER pulse width
(min)
Control to Strobe setup (min)
Control to Strobe hold (min)
Input Data setup (min)
Input Data Hold (min)
Output Data access
Output Transfer to Data float

MIN

TYP MAX

275
2.5
300
300
300
300
300
300
300

UNIT
ns

3

liS
ns
ns
ns
~s

ns
ns
ns

=(II

...
~

i

::::.
...
'P'

...
:Ii
W

S:!

.IIU~UI6

ICM7217/ICM7227
APPLICATIONS·

Voo

FIXED DECIMAL POINT

ICM121718
ICM~IB

In the common anode versions, a fixed decimal pOint may
be activated by connecting the D.P. segment lead from the
appropriate digit (with separate digit displays) through a
39n series resistor to Ground. With common cathode
devices, the D.P. segment ·Iead should be connected
through a 75n series resistor to VDD.
To force the device to display leading zeroes after a fixed
decimal point, use a bipolar transistor and base resistor in a
configuration like that shown below with the resistor connected to the digit output driving the D.P. for left hand D.P.
displays, and to the next least significant digit output for
right hand D.P. display. See Performance Characteristics
for a similarly operating multi-digit. connection.

-t

(ICM 7217 Ale)
(leM 7227 Ale)
DIGIT (S£G)

SEQ (DIGIT)

V58
05022111

Figure 14: Driving High Curr&nt Displays
--------~----------v~

Dt-..v

...

CONTaoL

Oft~'

DIGIT . . . . . .

LCD DISPLAY INTERFACE

01011
LlHI

~

The low-power operation of the ICM7217 makes an LCD
interface desirable. The IntersillCM7211 4 digit BCD to LCD
display driver easily interfaces to the ICM7217 as shown in
Figure 15. Total system power consumption is less than
5mW. System timing margins can be improveq by using
capacitance to ground to slow down the BCD lines. A
similar circuit can be used to drive Vacuum Fluorescent
displays, with the ICM7235.
The 10-20kn resistors on the switch BCD lines serve to
isolate the switches during BCD output.

COMMON ANODE

COIIMON CATHODI
05022211

Figure 13: Forcing Leading Zero Display

DRIVING LARGER DISPLAYS
For displays requiring more current than the ICL7217/
7227 can provide, the circuits of Figure 14 can be used.

VOD" 5V

VOD '" 5V

.... ......
LCO DISPLAV

,.,.,

'.,

28 SEGMENTS
AND BACKPLANE

L

~

J
35

0434

37~

03 33

ICM7211

~

D2 52
D•

~

••

24

083 30
DB2 29
DBl Z8
DIG

I

4 8'.
5 4',

6 2',
7 1',

iiEiET'4

tg'
y
Y Q
~ A~

:4~

~ ~~

~

~ A~

..

D.~.~

ICM7217
IJI
COUNT 8
STORE t
UPlDN 'O

A~ ~ ~

VDD

D1~
D2ff."

g:~

~ A~

, 24 8
C

10-20KU
LC01871I

Figure 15: LCD Display Interface (with Thumbwheel Switches)

7-62
Note: All typical values have been guaranteed by characterization and are not tested.

.U~U[6

ICM7217/ICM7227

a...
......
II)

CARRY
ZERO

......

21-23
25-28

COMMON-CATHODE
LED DISPLAY

leM
7217A

COUNT INPUT 8

n
I:

7 SEGMENTS
_

0

...
...

.

0 " 0

II)
II)

uUOO

24 J-D"-I'""Sp:-L-AY-'--BLA-O:;o

9

20 CONTROL

ISJ-----4

NORMAL
INHIBITLZB

15-18

4 DIGITS
LC018811

Figure 16: Unit Counter

Voo =5VOLTS

3K

10K

p-~______________~9~DD
.047
ICM7555

ICM7217

2TR
8 TH

cv

VIS

INVERTERS: C040108B

COUNT INPUT 0 -_ _ _ _ _ _ _ _ _-----'

NANOS: CD40118

____....1--300••---4===~,;:!'~SE~C:::==:::!·I
GATE

mH

~-----~,,/-'-----

I

"I

U

'/-I-----..,ur-----------J{~;'

____....1-+50. .

--

~--J'~'----------~

~----------~LI-'----WF018411

Figure 17: Inexpensive Frequency Counter
in Figure 17. To provide the gating signal, the timer is
configured as an astable multivibrator, using RA, RB and C
to provide an output that is positive for approximately one
second and negative for approximately 300-500J.lS. The
positive waveform time is given by twp = 0.693 (RA + RB)C
while the negative waveform is given by twn = 0.693 RBC.
The system is calibrated by using a 5Mil potentiometer for
RA as a "coarse" control and a 1kil potentiometer for RB
as a "fine" control. C040106B's are used as a monostable
multivibrator and reset time delay.

UNIT COUNTER WITH BCD OUTPUT
The simplest application of the ICM7217 is a 4 digit unit
counter (Figure 16). All that is required is an ICM7217, a
power supply and a 4 digit display, Add a momentary switch
for reset, an SPOT center-off switch to blank the display or
view leading zeroes, and one more SPOT switch for up/
down control. Using an ICM7217A with a common-cathode
calculator-type display results in the least expensive digital
counter/display system available.

INEXPENSIVE FREQUENCY COUNTERI
TACHOMETER
This circuit uses the low power ICM7555 (CMOS 555) to
generate the gating, STORE and RESET signals as shown
7-63

Note: All typical values have been guaranteed by characterization and are not tested.

ICM7217/ICM7227
COMMON-CATHODe

LID D...... AY
RIEL IWITCH
et..OSEO ONCE/R.V

r~;....l.-,--~:===~~
LD012901

Figure 18: Tape Recorder Position Indicator

.-

v..

2

13

>

•

RUN HRSIMtN I.'

• leM ••

~ih;::::::::f'I 7~'3"
"

...

•
7

•

VDO
C4 VOLTS MAX)

•

"00 L6i6 lit pt.
DtSPU,YO!F'

Voo PRESeT
ReSET

C002231 I

Figure 19: Precision Timer
T"'e ,1Mn resistor and .0047j.1F capacitor on the COUNT
INPUT provide a time constant of about 5ms to debounce
the reel switch. The Schmitt trigger on the COUNT INPUT of
the ICM7217 squares up the signal before applying it to the
counter. This technique may be used to debounce switchclosure inputs in other application~.

TAPE RECORDER POSITION INDICATORI
CONTROLLER
The Circuit in Figure 18 shows an application which uses
the up/down counting feature of the ICM7217 to keep track
of tape position. This circuit is representative of the many
applications of up/down counting in monitoring dimensional
position. For example, ar ICM7227 . as a peripheral to a
processor can monitor the position of a lathe bed or
digitizing head, transfer the data to the processor, drive
interrupts to the processor using the EQUAL or ZERO
outputs, and serve as a numerical, display for the processor.

PRECISION ELAPSED TIME/COUNTDOWN
TIMER
The circuit in Figure 19 uses an ICM7213 precision one
minute/one second timebase generator Lising a 4.1943MHz
crystal for generating pulses counted by an ICM7217B. The
thumbwheel switches allow a starting time to be entered
into the counter for a preset-countdown type timer, and
allow the register to be set for compare' functions. For
instance, to make a 24-hour clock with BCD output the
register can be preset with 2400 and the EQUAL output
used to reset the counter. Note the 10k resistor connected
between the LOAD COUNTER terminal and Ground. This
resistor pulls the LOAD COUNTER' input low when not
loading, thereby inhibiting the BCD output drivers. This
resistor. Should be eliminated and SW4 replaced with an
SPOT center-off switch if the BCD outputs are to be used.

In the tape recorder application, the LOAD REGISTER,
EQUAL and ZERO outputs are used to controlthe recorder.
To make the recorder stop at a particular point on the tape,
the register can be set with the stop point and the EQUAL
, output used to stop the recorder either on fast forward, play
or rewind.
To make the recorder stop before the tape comes free of
the reel on rewind, a leader should be used. Resetting the
counter at the starting point of the t e, a few feet from the
end of the leader, allows the ZER· output to be used to
stop the recorder on rewind, leaving the leader on the reel.

6

7-64
Note: All typical values have been guaranteed by characterization aM are not tested.

ICM7217/ICM7227
COMMON-ANODE

I

,

,-, " "

LED DISPLAYS

,-, ,-,

,-,

"

"--- 1:, CI CI CI

'-, CI CI CI .-/
COUNT INPUT

~CA~.~.Y~D~U!!T::-_t-.f1~'22"'5'2;a.

',DIGITS

•

CARRY/BORROW

DIGITS

BCD OUTPUTS

HIGH ORDER DIGITS
V .. ~OWN

4 4-7 leM 24

7217

.p

7

SEGMENTS

D1 y ..

25-21

2.

HIGH ORDER

SOK!!

COO22401

Figure 20: 8 Digit Up/Down Counter

--~--~----~-1---------~~Y+=5V

22pF

1QAll

BCD OUT

~l

COMMON·ANODE
LED DISPLAY

'CM
7217

COUNT.

CRYSTAL
,
5.24288 MH%
R<; 7St!

STORE

iiEsET

14

INPUT
CD022501

Figure 21: Precision Frequency Counter (MHz Maximum)
This technique may be used on any 3-level input. The
100kn pullup resistor on the count input is used to ensure
proper logic voltage swing from the ICM7213. For a less
expensive (and less accurate) timebase, an ICM7555 timer
may be used in a configuration like that shown in Figure 17
to generate a 1Hz reference.

ICM7227 devices, since the two devices are operated as
peripherals to a processor.

PRECISION FREQUENCY COUNTER/
TACHOMETER
The circuit shown in Figure 21 is a simple implementation
of a four digit frequency counter, using an ICM7207A to
provide the one second gating window and the STORE and
RESET signals. In this configuration, the display reads hertz
directly. With Pin 11 of the ICM7027 A connected to VDD,
the gating time will be 0.1 second; this will display tens of
hertz as the least significant digit. For shorter gating times,
an ICM7207 may be used (with a 6.5536MHz crystal), giving
a 0.01 second gating with Pin 11 connected to VDD, and a
0.1 second gating with Pin 11 open.
To implement a four digit tachometer, the ICM7207A with
one second gating should be used. To get the display to
read directly in RPM, the rotational frequency of the object
to be measured must be multiplied by 60. This can be done
electronically using a phase-locked loop, or mechanically by

8-DIGIT UP/DOWN COUNTER
This circuit (Figure 20) shows how to .cascade counters
and retain correct leading zero blanking. The NAND gate
detects whether a digit is active since one of the two
segments or b is active on any unblanked number. The flip
flop is clocked by the least significant digit of the high order
counter, and if this digit is not blanked, the Q output of the
flip flop goes high and turns on the NPN transistor, thereby
inhibiting leading zero blanking on the low order counter.
It is possible to use separate thumbwheel switches for
presetting, but since the devices load data with the oscilla'
tor free-running, the multiplexing of the two devices is
difficult to synchronize. This presents no problems with the

a

7-65
Note: All typical values have been guaranteed by characterization and are not tested.

...

ICM7217/1CM7227

.....
=
Ii using a disc rotating with the object with the appropriate

!:!
-

t:
~

Ii

g

inverts the data and an ICM7218 Universal Display Driver
stores and displays it.

number of holes drilled around its edge to interrupt the light
from an LED to a photo-dector. For faster updating, use 0.1
second gating, and multiply the rotational frequency by 600.
For more "intelligent" instrumentation, the ICM7227
interfaced to a microprocessor may be more convenient
(see Figure 21). For example, an ICM7207 A can be used
with two ICM7227's to provide an 8 digit, 2M Hz frequency
counter. Since the ICM7207A gating output has a 50% duty
cycle, there is 1 second for the processor to respond to an
interrupt, generated by the negative going edge of this
signal while it inhibits the count. The processor can respond
to the interrupt using ROM based subroutines, to store the
data, reset the counter, and read the data into main
memory. To add simultaneous period display, the processor

.-

AUTO·TARE SYSTEM
This circuit uses the count-up and count·down functions
of the ICM7217, controlled via the EQUAL and ZERO
outputs, to count in SYNC with an ICL7109 AID Converter
as ·shown in Figure 22. By RESETing the ICM7217 on a
"tare" value conversion, and STORE-ing the result of a true
value conversion, an automatic tare subtraction occurs in
the result.
The ICM7217 stays in step with the ICL7019 by counting
up and down between 0 and 4095, for 8192 total counts,
the same number as the ICL7109 cycle. See A047 for more
details.

r:+-

FULLICAa
INPUT

0

-

0

c
is

L...~

~0.~:yorgb
--+- --~ I

I

I

'5V

-

'ONO
2 STATUI

-

.PDL

REF CAl'-.3I

tOR

AEF CAP· 37
REF IN·"II

5812

...n

.......

INT3I
AZ ••

1087

....

•• 83
1582

,1.,

17 TEST
IIIHJij

..
i"-

~

p ..,

tCL7101

osc IN 22

.i-

L..
L--

..

MODE 2' ~+sv

'-.-

-

oa. f - -

5K114

VDO"

OIIP.COHT.II

1K11'

ICM7217

• iTI5iii
'0 upliiOWii

':'

.5V~~

1

10"F

Ia.
vss. f--:
ill

,..

12LOADCTR.

017

C > - - .411D1f

U

·SV

~~7.'

ilaa

11 LOAD RIG .

13 SCAN

~

l.!

OUS I - -

IKII2

lCOUNT

47•

SENO 27 J--+5V
RUN/HOLD 21

CAMYIIIORIlOW

• BIAS
alillllt
4K111

o.l~'ih

v....

~

I

::~

Sa'''''.

:'!~ .~
f- -ff-

Ho.aa..

aUF 30
REF OUT 21

aUF osc OUT 2S
OSC SEL 24
osc OUT 23

.-

'01<

IN HI 35
IN LO 34
COMMON 33

'810
I ..

1285

H'~

VDD 40 ~.5V
REF IN- 31

7

.,..

i,.

e15

TARE
CD02261I

Figure 22: Auto-Tare System for AID Converter

7-66
Note: All typical values have been guaranteed by characterization and are not tested.

ICM7224/ICM7225
4 b-Digit LCD/LED
Display Counter
GENERAL DESCRIPTION

FEATURES

The ICM7224 and ICM7225 devices constitute a family of
high-performance CMOS 4 1/2-digit counters, including
dec~ders, output latches, display drivers, count inhibit,
leading zero blanking, and reset circuitry.
The counter section provides direct static counting,
guaranteed from DC to 15 MHz, using a 5V ±10% supply
over the operating temperature range. At normal ambient
temperatures, the devices will typically count up to 25 MHz.
The COUNT input is provided with a Schmitt trigger to allow
operation in noisy environments and correct counting with
slowly changing inputs. The COUNT INHIBIT, STORE and
RESET inputs allow a direct interface with the ICM7207 I A
to implement a low cost, low power frequency counter with
a minimum component count.
These devices also incorporate several features intended
to simplify cascading four-digit blocks. The CARRY output
allows the counter to be cascaded, while the Leading Zero
Blanking INput and OUTput allows correct Leading Zero
Blanking between four-decade blocks. The BackPlane
driver of the LCD devices may be disabled, allowing the
segments to be slaved to another backplane signal, necessary when using an eight or twelve digit, single backplane
display. In LED systems, the BRighTness input to several
ICM7225 devices may be ganged to one potentiometer.
The ICM7224/1CM7225 family are packaged in a standard 40-pin dual-in-line plastic or CERDIP package, or in
dice.

•
•
•
•
•
•
•
•

•

High Frequency Counting - Guaranteed 15MHz,
Typically 25MHz at 5V
Low Power Operation - Typically Less Than
100llW Quiescent
STORE and RESET Inputs Permit Operation as
Frequency or Period Counter
True COUNT INHIBIT Disables First Counter
Stage
CARRY Output for Cascading Four-Digit Blocks
Schmitt-Trigger On The COUNT Input Allows
Operation In Noisy Environments or With Slowly
Changing Inputs
Leading Zero Blanking INput and OUTput for
Correct Leading Zero Blanking With Cascaded
Devices
LCD Devices Provide Complete Onboard
OSCillator and Divider Chain to Generate
Backplane Frequency, or Backplane Driver May
Be Disabled Allowing Segments to be Slaved to
A Master Backplane Signal
LED Devices Provide BRighTness Input Which
Can Function Digitally As A Display Enable or
As A Continuous Display Brightness Control
With A Single Potentiometer and Directly Drive
Common Anode LED Displays

ORDERING INFORMATION
DISPLAY TYPE

COUNT
OPTION

ICM72241PL
ICM7224AIPL
ICM7224/D
ICM7224A1D
ICM7224AIJL
ICM72241JL

LCD
LCD
LCD
LCD
LCD
LCD

19999
15959
19999
15959
15959
19999

ICM72251PL
ICM7225AIPL
ICM7225/D
ICM7225A1D
ICM7225AIJL
ICM72251JL

LED
LED
LED
LED
LED
LED

19999
15959
19999
15959
15959
19999

PART NUMBER

ICM7224

.. COUNT

(ICM722S)

31 COUNT INHIBIT
10 LZBOUT
It LZBIN

.. fiIiIiY
11H>1G1T

.. F.

2104
24£4
•• DC

-,._ _ _

.. CC
....t~84

CD02341I

Figure 1: Pin Configuration
(Outline dwg PL)

Evaluation Kits, order ICM7224 EV/Kit or ICM7225 EV/Kit

7-67
Note: All typical values have been guaranteed by characterization and are not tested.

-002

= ICM,7224/I()M1225,

...
!
N

::::.

ICM7224(A)

'It

...2~

MSD

LSD
~

H_~wmm

OS

D2
H_~OUTPUTS

HGMI~

OUTPUTS

1M

tl2-OlQIT

H_~OUTPUTS

OUTPUT

.5:!

LEADING

lLAN::----------i

LEADING
ZERO
BLANKING
INPUT

OUTPUt

~~--------------~
COUNT

INPUT

~---------------~----~----~----+---+-~----~----~----~~+-~

60009511

ICM7225(A)

MSD

LSD
01

00

O.

1M

1120010IT

SEGMENT OUTPUTS

SEGMENT OUTPUTS

SEGMENT OUTPUTS

SEGMENT OUTPUTS

OUTPUT

LEADWG

~~---~------------i
~PUT

LEADING

~--~-r~

ZERO
BLANKING
INPUT

~--------------~
COUNT
INPUT
~

______________

-4~

__

~

CARRY
OUTPUT

BRIGHTNESS
80009611

Figure 2: Functional Diagrams

7'-68

Note: All typical values have been guaranteed by characterization and are not tested.

ICM7224/ICM7225

n

ABSOLUTE MAXIMUM RATINGS

~
~

...

~

Supply Voltage Voo - Vss .................................. 6.SV
Input Voltage (Any
Terminal) (Note 2) ........ VOO+O.3V to VSs-O.3V
Power Dissipation (Note 1) .................... O.SW @ 70°C

Operating Temperature Range .... , ...... -20°C to +8SoC
Storage Temperature Range ............ -SSoC to + 12SoC
Lead Temperature (Soldering, 10sec) ................. 300°C

Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. Theses are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating .conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (Voo = SV ±10%, TA = 2S0C, Vss = OV unless otherwise indicated)
ICM7224 CHARACTERISTICS

VSUPPLY

PARAMETER
Operating current

TEST CONDITIONS

MIN

Test circuit, Display blank

Operating supply voltage range
(VOD-VSS)

TVP

MAX

UNIT

10

50
6

IlA
V

±10

IlA

3
±2

10SCI

OSCILLATOR input current

Pin 36

tR, tF

Segment riselfall time

Cload

tR, tF

BackPlane riselfall time

Cload - 5000pF

1.5

IlS

lose

Oscillator Irequency

Pin 36 Floating

19

kHz

fBP

Backplane frequency

Pin 36 Floating

150

Hz

~

0.5

200pF

ICM7225 CHARACTERISTICS
SYMBOL

PARAMETER

ISTBY

Operating current display off

VSUPP

Operating supply voltage range
(VDO-VSS)

TEST CONDIT!ONS

MIN

Pin 5 (BRighTness) at VSS
Pins 29, 31-34 at VOO

TVP

MAX

UNIT

10

50

IlA

6

V

4

100

Operating current

Pin 5 at VOO, Display 18888

ISLK

Segment leakage current

Segment Off

ISEG

Segment on curr'!nl

Segment On, Vout = + 3V

5

8

IH

Half-digit on current

Half-digit on, Vout = + 3V

10

16

200
±0.01

rnA
±1

IlA
rnA

FAMILY CHARACTERISTICS
SYMBOL
Ip

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

Input
Pullup Currents

Pins 29, 31, 33, 34
Vout = Voo - 3V

VIH

Input High Voltage

Pins 29, 3t, 33, 34

VIL

Input Low Voltage

Pins 29, 31, 33, 34

VCT

COUNT Input Threshold

2

VCH

COUNT Input: Hysteresis

0.5

10H

Output High Current

CARRY Pin 28
Leading Zero Blanking OUT Pin 30
Vout = Voo - 3V

350

500

10L

Output Low Current

CARRY Pin 28
Leading Zero Blanking Out Pin 30
Vout = +3V

350

.500

Count Frequency

4.5V

fCOUNT
tS,tR

STORE,

Ri:SE'i'

< VOO < 6V

Minimum Pulse Width

10

7-69

UNIT

IlA

3
1

0
3

Note: All typical values have been guaranteed by characterization ,and are not tested.

...

UI

NOTE 2: Due to the SCR structure inherent in the CMOS process, connecting any terminal to voltages greater than Voo or less than Vss may cause
destructive device latchup. For this reason, it is recommended that no inputs Irom sources operating on a different power supply be applied to the
device belore its supply is established, and that in multiple supply systems, the supply to the ICM7224IJCM7225 be· turned on lirst.

100

a
~
~

NOTE 1: This limit relers to that 01 the package and will not be obtained during normal operation.

SYMBOL

...

-

V

IlA

15

MHz
IlS

S,
"",

ICM7224/ICM7225

Ji. TYPICAL PERFORMANCE CHARACTERISTICS

u

i""

7224 OPERATING SUPPLY'CURRENT AS A
FUNCTION OF SUPPLY VOLTAGE

•

~

I

-.-

..

:;;..o::::.i-r cIIocuIr

..
I

-"

7225 LED SEGMENT CURRENT AS A FUNCTIoN
OF OUTPUT VOLTAGE

..

,

,.J,1A~~o!,

t/'

.L

'/

V' ~
JV ..... rIII IL Ysum.y" 4V

~

IL ~

/. ~
~~~

.,,~~ ~

..

VI,V

io'

r') I

TA-.- 7

~
1'::"-

T,,"'we

,

1J

c

I

J
VlUPft.y-I5Y

r.L

••

•

SUPPLY VOLTAGE lVl

I" IV r- r-

a

I

•

OUTPUT VOLTAGE {VI
O~311

0P042211

7224 BACKPLANE FREQUENCY AS A FUNCTION
OF SUPPLY VOLTAGE

..
..

~~~

7225 OPERATING POWER (LED DISPLAY) AS A
FUNCTION OF SUPPLY VOLTAGE

••

,.

1':
..Y
Caoo ••

~

,.

~.~.I-

, , ,

..:.~

OISPLAY ALL IIGItTI

uo POIIW'AAD VOLTAU DIIOP
¥IUD· t.7V'
...IAT Voo

J

T..,= . .C

l/

V

..
..

..... .....-

V

.....

V'

". I'COso ~

V

...

I'

•

I'"

...

.

Caoo-_

•,

I

, ...

"......-

~

I

•

••

SUPPLY VOLTAGE {VI

•

SUPPLY VOLTAGE {VI
OP04241 I

7224 BACKPLANE FREQUENCY AS A FUNCTION
OF OSCILLATOR CAPACITOR COSC

-

...,"
•
• •
II.

..."

7225 LI'D S.EGMENT CURRENT AS A FUNCTION
OF BRIGHTNESS CONTROL VOLTAGE
a

~~~.

,•

~
~I
'oo I""~
o:e

I
I

~

...

•

,

IL

..

'oo

Cose pF

I

IL

•

~

...

,

••

LL

.L

•

YlUl'Ply.4V~~

3v',. ....

~~!:r oL...J. AT' VOU'[" 3V

i•

~Yv:':'''l5v
v........V"

•
0P042511

/
.L

,~ •

•

•

•

BRIGHTNESS CONTROL VOLTAGE
OP04271I

OP042611

7-70
Note: All typical values have been guaranteed by characteriiation and are not tested.

•

ICM7224/ICM7225
TYPICAL PERFORMANCE CHARACTERISTICS (CONT.)
MAXIMUM COUNT FREQUENCY (TYPICAL) AS A
FUNCTION OF SUPPL Y VOLTAGE

.
.

SUPPLY CURRENT AS A FUNCTION OF COUNT
FREQUENCY

•

....,...'

I- IN WAVE INPUT

IWINGING FUU. lI..ItPly

.
. ..
. ..
.. 'V1/
.

~~
",.

~
!

V

«

~

~~
-aoc

TA

V

".

.....

V

10' ~

rr

,~

1

c i-

1I

4:J.c rT _-

T",a7

C

1

./

•

SUPPLY VOLTAGE (VI

..

1
lltHi

•

.....
1C1kHl

l00kHa

lMMI

1011Hz

INPUT

TERMINAL

Leading Zero Blanking
INput

29

COUNT INHIBIT

31

RESET

33

SiOF!E

34

0P042921

VOLTAGE

FUNCTION
Leading Zero Blanking Enabled
Leading Zeroes Displayed

Voo or Floating
Vss
VOO or Floating
VSS
VOO or Floating
VSS
VOO or Floating
VSS

Counter Enabled
Counter Disabled
Inactive
Counter Reset to 0000
Output Latches not Updated
Output Latches Updated

the number of devices that can be slaved to one master
device backplane driver is the additional load represented
by the larger backplane of displays of more than four digits,
and the effect of that load on the backplane rise and fall
times. A good rule of thumb to observe in order to minimize
power consumption is to keep the rise and fall times less
than about 5 microseconds. The backplane driver devices
of one device should handle the backplane to a display of
16 one-half-inch characters without the rise and fall times
exceeding 5jJs (ie, 3 slave devices and the display backplane driven by a fourth master device). It is recommended
that if more than four devices are to be slaved together, that
the backplane signal be derived externally and all the
ICM7224 devices be slaved to it.
.

CONTROL INPUT DEFINITIONS
In this table, Voo
operating input logic
are specified in the
power consumption,
supply.

10DMHz

fCOUNT
QP042821

and Vss are considered to be normal
levels. Actual input low and high levels
Operating Characteristics. For lowest
input signals should swing over the full
.

DETAILED DESCRIPTION

LCD Devices
The LCD devices in the family (ICM7224 and ICM7224A)
provide outputs suitable for driving conventional 4 Y2-digit by
seven segment LCD displays, including 29 individual segment drivers, backplane driver, and a self-contained oscillator and divider chain to generate the backplane frequency.
The segment and backplane drivers each consist of a
CMOS inverter, with the n- and p-channel devices ratioed to
provide identical on resistances, and thus equal rise and fall
times. This eliminates any D.C. component which could
arise from differing rise and fall times, and ensures maximum display life.
The backplane output devices can be disabled by connecting the OSCILLATOR input (pin 36) to VSS. This
synchronizes the 29 segment outputs directly with a signal
input at the BP terminal (pin 5) and allows cascading of
several slave devices to the backplane output of one
master device. The backplane may also be derived from an
external source. This allows the use of displays with
characters in multiples of four and a single backplane. A
slave device will represent a load of approximately 200pF
(comparable to one additional segment). The limitation on

This external signal should be capable of driving very
large capacitive loads with short (1-2jJs) rise and fall times.
The maximum frequency for a backplane signal should be
about 150Hz, although this may be too fast for optimum
display response at lower display temperatures, depending
on the display used.
The onboard oscillator is designed to free run at approximately 19kHz, at microampere power levels. The oscillator
frequency is divided by 128 to provide the backplane
frequency, which will be approximately 150Hz with the
oscillator free-running. The oscillator frequency may be
reduced by connecting an external capaCitor between the
OSCillator terminal (pin 36) and Voo; see the plot of
oscillator/backplane frequency in "Typical Characteristics"
.
for detailed information.
7-71

Note: All typical values have been guaranteed by characterization and are not tested.

ICM7224/ICM7225
The oscillator may also be overdriven if desired, although
care must be taken to insure that the backplane driver is not
disabled during the negative portion of the overdriving
signal (which could cause a D.C. component to the display).
This can be done by driving the OSCILLATOR input
between the positive supply and a level out of the range
where the backplane disable is sensed, about one fifth of
the supply voltage above the negative supply. Another
technique for overdriving the oscillator (with a signal swinging the full supply) is to skew the duty cycle of the
overdriving signal such that the negative portion has a
duration shorter than about one microsecond. The backplane disable sensing circuit will not respond to signals of
this duration.

----1~--'VDD(Ll!D

, '....".'11"· _

ANODI!a)

:."!:*
TC02821I

Figure 3: Brightness Control

COUNTER SECTION
The devices in the ICM7224/ICM7225 family implement
a four-digit ripple carry resettable counter, including a
Schmitt trigger on the COUNT input and a CARRY output.
Also included is an extra D-type flip-flop, clocked by the
CARRY signal and outputting to the half-digit segment
driver, which can be used as either a true half-digit or as an
overflow indicator. The counter will index on the negative~dge of the signal at the COUNT input, while the
CARRY output provides a negative-going edge following
the count which indexes the counter from 9999 (or 5959) to
10000. Once the half-digit flip-flop has been clocked, it can
only be reset (with the rest of the counter) by a negative
level at the RESET terminal, pin 33. However, the four
decades will continue to count in a normal fashion after the
half-digit is set, and subsequent CARRY outputs will not be
affected.
A negative level at the COUNT INHIBIT input disables the
first divide-by-two in the counter chain without affecting its
clock. This provides a true inhibit, not sensitive to the state
of the COUNT input, which prevents false counts that can
result from using a normal logic gate to prevent counting.
Each decade of counter. drives d,irectly into a four-toseven decoder which develops the seven~segment output
code. The output data is latched at the driver, when the
STORE pin is low, these latches are updated, and when
high or floating, the latches hold their contents.
The decoders also include zero detect and blanking logic
to provide leading zero blanking. When the Leading Zero
Blanking INput is floating or at a positive level, this circuitry
is enabled and the device will blank leading zeroes; when
low, or the half-digit is set, leading zero blanking is inhibited,
and zeroes in the four digits will be displayed. The Leading
Zero -Blanking OUTput is provided to allow cascaded
devices to blank leading zeroes correctly. This output will
assume a positive level only when all four digits are
blanked; this can only occur when the Leading Zero
Blanking INput is at a positive level, and the half-digit is not
set.
For example, in an eight-decade counter with overflow
using two ICM7224/ICM7225 devices, the Leading Zero
Blanking OUTput of the high order digit would be connected
to the Leading Zero Blanking INput of the low order digit
device. This will assure correct leading zero blanking for all
eight digits.,
The STORE, RESET, COUNT INHIBIT, and Leading Zero
Blanking INputs are provided with pullup devices, so that
they may be left open when a positive level is desired; The
CARRY and Leading Zero Blanking OUTputs are suitable
for interfacing to CMOS logic in general, and are specifically
designed to allow cascading of ICM7224 to ICM7225
devices in four-digit blocks.

LED Devices
The LED devices in the family (ICM7225, ICM7225A)
provide outputs suitable for directly driving 4V2-digit by
seven segment common-anode LED displays, including 28
individual segment drivers and one half-digit driver, each
consisting of a low-leakage current-controlled open-drain nchannel transistor.
The drain current of these transistors can be controlled
by varying the voltage at the BRighTness input (pin 5). The
voltage at this pin is tr,msferred to the gates of the output
devices for "on" segments, and thus directly modulates the
transistor's "on" resistance. A brightness ,control can be
easily implemented with a single potentiometer controlling
the voltage at pin 5, connected as in Figure 3. The
potentiometer should be a high value (100kn to 1Mn) to
minimize power consumption, which can be significant
when the display is off.
The BRighTness input may also be operated digitally as a
display enable; when a Voo, the display is fully on, and at
Vss, fully off. The display brightness may also be controlled
by varyi\lg the duty cycle of a signal swinging between the
tw,o supplies at the BRighTness input.
Note that the LED devices have two connections for VSS;
both should be connected. The double connection is
necessary to minimize effects of bond wire resistanpe with
the large total display currents possible.
When operating the LED devices at higher temperatures
and/or higher supply voltages, the device power dissipation
may need to be reduced to prevent excessive chip temperatures. The maximum, power dissipation is 1 watt at 25°C,
derated linearly above 35°C to 500mW at 70°C (15mW/oC
above 3S0C). Pqwer disSipation for the device is given by:
P = (VOO ~ VFLEO) x (ISEG) x (nSEG)
where VFLEO is the LED forward voltage drop, ISEG is
segment current, and nSEG is the number of "ON" segments. It is recommended that if the device is Jo,be
operated at elevated temperatures the segment current be
limited by use of the BRighTness input to keep power
dissipation within the limits described above.

7-72
Note: All typical values have been guaranteed by characterization and are not tested.

.U~UlL

ICM7224/ICM7225
OSCILUTO.
FREQUENCY

n r ' ' ' n n n r' ., n n r'

JU

UUUU

UUU

1 - - - 1 2 1 CYCLES---j

BACKPLANE
INPUT/OUTPUT

-----;1

r--"

I

I

L-.-

S

f

,7/b
d

"""

I\)
I\)

en

:::0

LC019401

WFOl8601

(;

I:

'3
:3-,
,

_I Ie
ON SEGMENTS

....

3
'-:

a

L-

CYCLES--?=: . . CYCLES---l

OFF SEGMENTS-----;t

"""

I\)
I\)

,-,
'-',
,
,?

., n n n r
UUUU

Figure 4: Display Waveforms

-'

(BLANK)
lC020501

+

IV

Figure 6: Segment Assignment
and Display Font

-

.1.1------.

IACH HGMlNT TO
hCII"'- WITH

_

CAPACITOII

COUNT INHIBIT 31 t-.......!-;...
A"'US"'E~
LZB IN 30
(CLOSED)
LZtI OUT 29 .----~'LZ
.... CAiiAi 28:
INHIBIT
(CLOSED)

'---=,,:-::.."'a"'U;;;::ENT=S-;~~
' - -_ _':..:HA=LF...:-D:::IG=-'TC--!37-40

ICU7225+~01

SEGMENT

OUTPUTS I')

I_f-O-+-oICL MAIN

"

~ICD

' - - - - - - - r-----y---;---:--- T-~--

:::T
L_________-----~~~~~','-'--'~-~:
~

i'iiiiNiiiiOci

OU'PUTo---~~I_-----~--+-~

HOI.DINPUT

o-....,.____-"-____

OUTPUTS (4)

--''-~

OUTPUT

80009701

Figure 2: Functional Diagram

7-76
Note: All typical values have been guaranteed by characteriza!ion and are, not tested.

ICM7226A/B
ELECTRICAL CHARACTERISTICS
SYMBOL
100

VSUPPLY

IA(max)

IB(max)

IOSC
gm

fmux
dVin/dt

VIL
VIH

(Voo

= 5.0V,

PARAMETER

TA = 25°C, unless otherwise specified.)

TEST CONDITIONS

Operating Supply
Current

Display Off
Unused inputs to VSS

Supply Voltage Range VOO - VSS

-2SoC < TA < 85°C
Input A, Input B
Frequency at IMAX

Maximum Guaranteed FrequenCy
Input A, Pin 40

-25°C < TA < 8SoC
4.75V < VOO < 6.0V Figure 4
Function = Frequency,
Ratio, Unit Counter
Function = Period, Time Interval

MIN

TYP

MAX

UNIT

2

5

mA

6.0

V

4.75

10
2.5

14

MHz

Maximum Frequency
Input B, Pin 2

-25°C < TA < 8SoC
4.75V < VOO < 6.0V
Figure S

2.5

Minimum Separation
Input A to Input B

-2SoC < TA < 85°C
4.75V < VOO < 6.0V
Figure 6

250

ns

Time Interval Function

Osc. Iraq. and ext. osc.
Ireq. (minimum ext. osc. Ireq.)

-2SoC < TA < 8SoC
4.75V < Voo < 6.0V

10
(0.1)

MHz

Oscillator Transconductance

VOO= 4.75V
TA = +85°C

2000

JJ.s

Multiplex Frequency

lose = 10MHz

SOO

Hz

Time Between Measurements

lose = 10MHz

200

ms

Input Rate 01 Charge

Inputs A, B

15

mV/JJ.S

INPUT VOLTAGES
PINS 2, 19, 33, 39, 40, 35
input low voltage

-2SoC

< TA <

+85°C

input high voltage

1.0

V

20

JJ.A

3.5

IILK

PIN 2, 39, 40 INPUT LEAKAGE, A, B

RIN

Input resistance to VOO
PINS 19,33

VIN = VOO -1.0V

100

400

RIN

Input resistance to Vss
PIN 31

VIN = + 1.0V

50

100

IOL

Output Current
PINS 3,S,6,7,17,18,32,38

VOL

= +O.4V

400

IOH

PINS S,6,7,17,18,32

VOH = +2.4V

100

IOH

PINS 3,38

VOH = Voo-Q·8V

265

Vo = Voo -2.0V

ISO

kn
JJ.A
JJ.A

ICM7226A
IOH
IOL

IOL

PINS 22,23,24,26,27,28,29,30
DIGIT DRIVER
high output current
low output current
SEGMENT DRIVER
PINS 8,9,10,11,13,14,15,16
low output current

IOH

high output current

VIL

MULTIPLEX INPUTS
PINS 1,4,20,21
input low voltage

VIH

input high voltage

RIN

input resistance to VSS

VO= +1.5V

180

mA

-0.3

Vo = + 1.0V

25

Vo = VOO-I.0V

35

mA

100

JJ.A
0.8

2.0
VIN = + 1:0V

7-77
Note: All typical values have been guaranteed by characterization and are not tested.

50

tOO

V

kn

!!. ICM7226A/B

=
...

ELECTRICAL CHARACTERISTICS (CONT.)

ft

SYMBOL

PARAMETER

TEST CONDITIONS

TYP

MIN

MAX

UNIT

ICM7226B
IOL

DIGIT DRIVER
PINS 8,9,10,11,13,14,15,16
low output current

IOH

VO= +1.0V

high output current

IOH

SEGMENT DRIVER
PINS 22,23,24,26,27,28,29,30
high output current

IL

leakage current

50

Vo = Voo-2.5V

Vo = Voo-2.0V

10

75

rnA

100

p.A

rnA

15
10

Vo=Vss

VIL

MULTIPLEX INPUTS
PINS 1,4,20,21
input low voltage

VIH

input high voltage

RIN,

input resistance to Voo

p.A

Voo-2.0
V

Voo-O.B
VIN = VoO-1.0V

100

k!1

360

NOTE: Typical values are not tested.

EVALUATION KIT
An evaluation kit is available 'for the ICM7226A. It
includes all the components necessary to assemble and
evaluate a universal frequency/period counter based on the
ICM7226A. With the help of this kit, an engineer or
technician can have the ICM7226A "up-and-running" in
less than an hour. Specifically,' the kit contains an
ICM7226AIJL, a 10MHz quartz crystal, eight each 7segment 0.3" LEOs, PC board, resistors, capacitors, diodes,
switches and IC socket. Order Number ICM7226AEV /Kit.

TEST

COHTIIOI._
VO .5.011

CRVSTALSPlC'.::;
'0 10.00MHI
Co UpF

UNIII

f

'OOCNOTES
IUS WITH
, COHOUCTOIIIS

..,.

-=

As

3511

~~t£!!..Q.-:t£9.!!1~

KO I OUTPUT :::;::=4=~
leo A OUTPUT ....

OVERFLOW WILL 8. INDICA TID ON THE

DECIMAL POINT OUTPUT Of DiCIT 7
W!!!!I!i
ANODE

,.....,.

filET

1( .. 7221&
leM7Z"

cI.p.

De;

Dt

d.p.

TC028521

Figure 3: Test Circuit

7-7B
Note: All typical values have been guaranteed by characterization and are not tested.

ICM7226A/B
a

'/-;-/b
e/-/e
d ed.p.

0:23""561S9
LC019701

lC019601

LED overflow indicator connections:
Overflow will be indicated on the decimal point output of digit 8.
ICM7226A
ICM7226S

CATHODE

ANODE

d.p.
DB

DB
d.p.

Figure 4: Segment Identification and Display Font

COUNTED

~TR""'SITIDHS

INPUT ..

if't

4.SV----o.sv

50 .. "'N

50

M

MIN

INPUT AOR
INPUT'

•.5V

a.5V

~,.-.-.,-:-1~._-WF026601

Figure 6: Waveform for Guaranteed
Minimum fB(max) and fA(max) for
Function = Period and Time Interval.

WFQ26501

Figure 5: Waveform for Guaranteed
Minimum fA(max) Function Frequency,
Frequency Ratio, Unit Counter.

=

Duri.ng any time interval measurement cycle, the
ICM7226A/B requires 200ms following B going low to
update all internal logic. A new measurement cycle will not
take place until completion of this internal update time.

TIME INTERVAL MEASUREMENT
The ICM7226A1B can be used to accurately measure the
time interval between two events. With a 10 MHz time-base
crystal, the time between the two events can be as long as
ten seconds. Accurate resolution in time interval measurement is 100ns.
The feature operates with Channel A going low at the
start of the event to be measured, followed by Channel B
going low at the end of the event.
When in the time Interval mode and measuring a single
event, the ICM7226A1B must first be "primed" prior to
measuring the event of interest. This is done by first
generating a negative going edge on Channel A followed by
a negative going edge on Channel B to start the "measurement interval." The inputs are then primed ready for the
measurement. Positive going edges on A and B, before or
after the priming, will be needed to restore the original
condition.
Following the priming procedure (when in single event or
1 cycle range input) the device is ready to measure one
(only) event.
When timing repetitive signals, it is not necessary to
"prime" the ICM7226A/B as the first alternating signal
states automatically prime the device. See Figure 7.

DETAILED DESCRIPTION
INPUTS A & B
The signal to be measured is applied to INPUT A in
frequency period, unit counter, frequency ratio and
time Interval modes. The other input signal to be measured
is applied to INPUT B in frequency ratio and time interval.
fA should be higher than fS during frequency ratio.
Both inputs are digital inputs with a typical switching
threshold of 2.0V at VDD': 5.0V and input impedance of
250kn. For optimum performance, the peak to peak input
signal should be at least 50% of the supply voltilge and
centered about the switching voltage. When these inputs
are being driven from TTL logic, it is desirable to use a
pullup resistor. The circuit counts high to low transitions at
both inputs.
Note: The amplitude of the input should not exceed the supply by more
than O_3V otherwise, the circuit may be damaged.

7-79
Note: All typical values have been guaranteed by characterization and are not tested.

7

.O~O[l

~ ICM7226A1B
CD

tJ

~,

~

....

~

H'-.J

Ift5IiI

3OTO_'

1--+_ '
n~-_!_--~

RElET _ _..._ _ _ _...

1-+-

I

_'IOu;g"~---_--",,_G--_I"'-----"EASUREMENTINTERV""

I

UPOATE-

INI'UTA

IM'UTI

I

.......

16OnsMiN.
MEASURED
INTERVAL

,

--4I

t--

_

MEASURED

CFIRS!);

INTERVAL
(LASTI
WF026701· '

NOTE: IF RANGE IS SET TO 1 EVENT, FIRST AND LAST MEASURED INTERVAL WILL COINCIDE.

Figure 7: Waveforms for Time Interval Measurement
(Others are similar, without priming phase)

~I~UT"

SIGNAL 8

'r--l~I~PUT •.

FUNCTION

Voo

N)~lpRI"EI
...:.
........

VDD

,...

I~

,

to.!'

'~T'''''''
'

Va.

Voo

~ l ....
....

to.!

O.'''f

10GppF

Vas
, 05028001

Figure 8: Priming Circuit; Signal A&B
High ()r Low
DEVICE
1
2

",

drivers can be capacitively coupled through thel,.E;D d!odes
to the multiplex inputs. For maximum noise immunity. a
10kn resistor should be placed in seri~s' with the' multiplex
inputs as shown, in the application notes.
Table 1 shows the functions selected by each digit for
these .inputs.
'
Table 1: Multiple Input Control

This can be'easily accomplished with the following circuit:
(Figure 8).
SIGNAL A

.

TYPE

D1
D8
D2
D5
.D4
D3

RANGE; INPUT
PIN 21

D1,
'02
D3
D4
D5

PIN 31

CD4049B 'Inverting Buffer
CD4Q70B Exclusive-OR

0.Q1 Seb/l Cycle
0.1 Sec/10 cycles
1 Sec/l00 Cycles
10 Secll k CyCles
Enable External Range
Input

CONTROL INPUT Display Off
PIN 1
Display Test
lMHz Select
External Oscillator Enable
External'Decimal Point
Enable

MULTI~LEXED INPUTS
The FUNCTION, RANGE. CONTROL and EXTERNAL
DECIMAL POINT inputs are time multiplexed to select the
input function desired. This is achieved by connecting the
appropriate digit driver output to the inputs. The input
function, range and control inputs must be stable during the
last half of each digit output, (typically 125/ls). The multiplex
inputs are active high for the common anode ICM7226A.
and active low for the common cathode ICM7226B.

DIGIT

FUNCTION INPUT Frequency
Pin 4
Period
Frequency Ratio
Time Interval
Unit Counter
Oscillator Frequency

D4 & Hold
D8 .
D2
D1
D3

EXTERNAL DECIMAL Decimal Point is Output for Same
POINT INPUT, PIN
Digit That is Connected to This
20
Input
CONTROL INPUTS
Display Test - All segments are enabled continuously.
giving a display of all 8's with decimal points. The display
will be blanked if display off is selected at the same time.

Noise on the multiplex inputs can cause improper operation. This is particularly true when the unit counter mode of
operation is selected. since changes in voltage on the digit
. 7-80

Note: All typical values have been guaranteed by characterization and are not tested.

.D~DlL

ICM7226A/B
Display Off - To enable the display off mode it is
necessary to tie 04 to the CONTROL input and have the
HOLD input at VDD. The chip will remain in this mode .until
MOLD is switched low. While in the display off mode, the
segment and digit driver outputs are open and the oscillator
continues to run (with atypical supply current of 1.5mA with
a 10MHz crystal) but no measurements are made. In
addition, signals applied to the multiplexed inputs have no
effect. A new measurement is initiated after the HOLD input
goes low. (This mode does not operate when functioning as
a unit counter.)

~

Table 2: Input Routing
DESCRIPTION

REFERENCE
COUNTER

Frequency (fA)

Input A

100 Hz (Oscillator
.;. 105 or 104 )

Period (tA)

Oscillator

Input A

Ratio (fA/fB)

Input A

Input B

Time Interval

Osc ON
.Gate

Osc OFF

(A~B)

, 1MHz Select - The 1MHz select mode allows use of a
1MHz crystal with the same digit multiplex rate and time
between measurements as a 10MHz crystal. The internal
decimal point is also shifted one digit to the right in period
lind time interval, since the least significant digit will be in
1~s increments rather than 0.1 MS.

MAIN COUNTER

Unit Counter
(Count A)

I~put

Osc. Freq.
(fosC>

OscillatOr

A

Gat~,

Not Applicable
100 Hz (Oscillator
.;. 105 or 104 )

EXTERNAL DECIMAL POINT INPUT
When the external deCimal point is selected, this input
is active. Any of the digits, except 08, can be connected to
this point. DB, should not be used .since it will override the
overflow output and leading zeros will remain unblanked
after the decimal point.
HOLD Input - Except in the unit counter mode, when
the HOLD input is at VDD, any meaSurement in progress
(before STORE goes. low) is stopped, the main counter is
reset and ,the chip is held ready to initiate a new measurement as soon as HOLD goes low. The latches which hold
the main counter data are not updated, so the last complete'
measurement is displayed. In unit counter mode when
HOLD input is at VDD, the counter is not stopped or reset,
but the display is frozen at that instantaneous value. When
HOLD goes low the count continue.s from the new value in
the counter.
RESET Input - The RESET Input resets the main counter, stops any meal\urement in progress, and enables the
main counter latches, resulting in an all zero output. A
capacitor to ground will prevent any hang-ups on power_up.
EXTernal'RANGE Input- The EXTernal.RANGE Input
is used to select other ranges than those provided on the
chip. Figure 9 shows the relationship between MEASurement IN PROGRESS and EXTernal RANGE Input

External Oscillator Enable -1r:J this mode, the EXTernal OSCillator INput is used, rather than the on-chip
oscillator, for the Timebase and Main Counter inputs in
period and time interval modes. The on-chip oscillator will
continue to function when the external oscillator is selected;
but have no effect on circuit operation. The external
oscill,....-j,.."9-'~'--~"±~

a

140L120

~

100

~

~- - --i-

r--iJ~iL--+

80
60 ';---II'F-+---+40

SUPPL Y VOLTAGE IV)

TIMING CAPACITOR. C ("FI
OP044401

0P044711

TIMEBASE FREE RUNNING FREQUENCY AS A
FUNCTION OF RAND C

MINIMUM TRIGGER PULSE WIDTH AS A
FUNCTION OF TRIGGER AMPLITUDE
1500
1400
1300
.. 1200
So 1100
i!= 1000

i

III

!l

..."
'"
""...i<
III

900
800
700
800
500
400
300
200
100

0
0
TIME BASE FREOUENCY (HzI

A - +25"C

Voo = 16V

- rtr5~\
Voo =

f

2V ,..,
I

I

J

r

1'0..
5

6

9

10

TRIGGER AMPUTUDE (VOLTS)
0P04451 I

0P045811

7-95
Note: All typical values have been guaranteed by characterization and are not tested.

PI

ICM7240/1CM7250/ICM7260
TYPICAL PERFORMANCE CHARACTERISTICS (CO NT.)
NORMALIZED FREQUENCY STABILITY IN THE
ASTABLE MODE AS A FUNCTION OF
TEMPERATURE

MINIMUM RESET PULSE WIDTH AS A FUNCTION
OF RESET AMPLITUDE
1500
1400
1300

I II

i'
Ei
~

~

I

700

600

~

500

~

a:

I

I

I

TA = 25'C

,VDD=5~
V i +--t---r--~-

I

,

800

~

I

! ,
! T .~
,--r-----t-,

i

1100

1000
900

I

I

1200

i

I

VDO = 2V

1/

I

I

/

400

:VDD = 16V

r«

.,

300

\'

200
100

I

I

--i--

I

!

I

I

'-.L

~-'----'--

0
6

9

7

10

RESET AMPLITUDE IVOL TSI
OP044901

0P0446tl

NORMALIZED FREQUENCY STABILITY IN THE
ASTABLE MODE AS A FUNCTION OF SUPPLY
VOLTAGE

MAXIMUM DIVIDER FREQUENCY VB. SUPPLY
VOLTAGE100M

I

--

~

~

R=I~n~
_

> 10M

.!!!
il.
ff:

C=O.Ip~'"

I

~,c·

~

O.lpF

~

TA =+25·C

_

==

RC.CONNECTED
TO GROUND
_

I

1M

=

ffi

Q

I

;:
is

I

~ lOOK
~

5V" VDD<> ISV

== == ~g~J~':~:)~~~~~~'~~L~-

10K
+25

+50

o

+75

-

-'- NO PROGRAMMING CONNECTIONS

4

8

10

12

14

16

18

20

SUPPL V V9L T AGE IV)

TEMPERATURE I'CI
OP04501 I

0P045201

OUTPUT SATURATION CURRENT AS A FUNCTION
OF OUTPUT SATURATION VOLTAGE

DISCHARGE OUTPUT CURRENT AS A. FUNCTION
OF DISCHARGE OUTPUT VOLTAGE

:(

oS

:(

oS

l-

.

...a:Z

:>

"0z

I-

Z

a:

a:
a:

:>

""z
iii
"
l-

:a

II:

I

!:i

l:

&l

I

J!::>

i5

0
0.1
.01

0.1

TA = +2S'C

0.1

10

10

OUTPUT SATURATION VOLTAGE IV)

DISCHARGE SATURATION VOLTAGE IV)
0P04531 I

OP045111

7-96
Note:, All typical values have been guaranteed by characterization and are not tested.

ICM7240/lCM7250/lCM7260
CIRCUIT DESCRIPTION

RESET AND TRIGGER INPUTS (PINS 10 AND 11)
The circuits are reset or triggered by a positive level
applied to pins 10 and 11, and once triggered they ignore
additional trigger inputs until either .the timing cycle is
completed or a reset signal is applied. If both reset and
trigger are applied simultaneously trigger overrides reset.
Minimum input pulse widths are shown in the typical
performance characteristics. Note that all devices feature
power ON reset.
MODULATION AND SYNC INPUT (PIN 12)
The period, t, of the time base oscillator can be modulated by applying a DC voltage to this terminal. The time base
oscillator can be synchronized to an external clock by
applying a sync pulse to pin 12.
TIMEBASE INPUT/OUTPUT PIN (PIN 14)
While this pin can be used as either a time base input or
output terminal, it should only be used as an input if the RC
pin is connected to VSS.
If the counter is to be externally driven, care should be
taken to ensure that fall times are fast (see Operating Limits
section).
Under no conditions is a 300pF capacitor on this terminal
useful and should be removed if a 7240/50/60 is used to
replace an 8240/50/60 or 2240.
CARRY OUTPUT (PIN 15, ICM7250/60 ONLY)
This pin will go HI for the last 10 counts of a 59 or 99
count, and can be used to drive another 7250 or 7260
counter stage while still using all the counter outputs of the
first. Thus, by cascading several 7250's a large BCD
countdown can be achieved.
The basic timing diagrams for the ICM7240/50/60 are
shown in Figure 4. Assuming that the device is in the
RESET mode, which occurs on powerup or after a positive
level on the RESET terminal (if TRIGGER is low), a positive
level on the trigger input Signal will initiate normal operation,
The discharge transistor turns on, discharging the timing
capacitor C, and all the flip-flops in the counter chain
change states.
Note that for straight binary counting the outputs are
symmetrical; that is, a 50% duty cycle HI-LO. This is not the
case when using BCD counting. (See Figure 6.)

The timing cycle is initiated by applying a positive-going
trigger pulse to pin 11. This pulse enables the counter
section, sets all counter outputs to the LOW or ON state,
and 'starts the time base oscillator. Then, external C is
charged through external R from 20% to 70% of VDD-VSS,
generating a timing waveform with period t, equal to 1Re. A
short negative clock or time base pulse occurs during the
capacitor discharge portion of the waveform. These clock
pulses are counted by the binary counter of the 7240 or by
two casca,ded Binary Coded Decimal (BCD) Counters in the
7250/60. The timing cycle terminates when a positive level
is applied to RESET. When the circuit is at reset, both the
time base and the counter sections are disabled and all the
counter outputs are at a HIGH or OFF state. The carry-out is
also HIGH. Each of the three devices utilizes an identical
timebase, control flip-flops, and basic counters, with the
outputs consisting of open drain n-channel transistors. Only
the ICM7250/60 have CARRY outputs.
In most timing applications, one or more of the counter
outputs are connected back to RESET the circuit will start
timing when a TRIGGER is applied and will automatically
reset itself to complete the timing cycle when a programmed count is completed. If none of the counter outputs
are connected back to the RESET (switch S1 open), the
circuit operates in its astable, or free-running mode, after
initial triggering.

DESCRIPTION OF PIN FUNCTIONS
COUNTER OUTPUTS (PINS 1 THROUGH 8)
Each binary counter output is a buffered "open-drain"
type. At reset condition, all the counter outputs are at a
high, or non-conducting state. After a trigger input or when
using the internal timebase, the outputs change state (see
timing diagram, Figure 4). If an external clock input is used,
the trigger input must overlap at least the first falling edge of
the clock. The counter outputs can be used individually, or
can be connected together in a wired-AND configuration, as
described in the Programming section.

Jl

'--__________

---

1\ I I I I I I I II I

TRIGGER INPUT
(TERMINAL 11)

PROGRAMMING CAPABILITY

TIMEBASE OUTPUT
(TERMINAL 141

The counter outputs, pins 1 through 8, are open-drain Nchannel FETs, and can be shorted together to a common
pull-up resistor to form a "wired-AND" connection. The
combined output will be LOW as long as anyone of the
outputs is low. Each output is capable of sinking ""'5mA. In
this manner, the time delays associated with each counter
output can be summed by simply shorting them together to
a common output. For example, if only pin 6 is connected to
the output and the rest left open, the total duration of the
timing cycle (monostable mode) to would be 32t for a 7240
and 20t for a 7250/60. Similarly, if pins, 1, 5, and 6 were
shorted to the output bus, the total time delay would be
to = (1 + 16 + 32)t for the 7240 or (1 + 10 + 20)t for the
7250/60. Thus, by selecting the number of counter terminals connected to the output bus, the timing cycle can be
programmed from:
11 ~ to ~ 255t (7240)
11 ~ to ~ 99t (7250)
11 ~ to ~ 59t (7260)

- - - - 2 OUTPUT (TERMINAL 1)

_I

2.

I--

.

~
1--- •• ---1

-,

Ir---~

1----..

___..r

L

4 OUTPUT (TERMINAL 2)

-s OUTPUT (TERMINAL 3)

.1

~~~
1--'28'.-J

+256 OUTPUT
fTERMINAL 8; 7240 ONL VI

WF020101

Figure 4: Timing Diagram for ICM7240/50/60
Vss (PIN 9)
This is the return or most negative supply pin. It should
have a very low impedance as the capacitor discharge and
other switched currents could create transients.
7-97

Note: All typical values have been guaranteed by characterization and are not tested.

:aN ICM-1"240/ICM7250/ICM7260'

...

-...

I

51

N

!=::.

!...

I

ICM7260, there are standard BCD thumbwheel switches for
the 0 through 5 digit (twelve position 0 to 5 repeated).

Note that for the 7250 and 7260, invalid count states
(BCD values;::: 10) will not be recognized and the counter
will not stop.
'
The 7240/50/60 can be configured to initiate a controlled
timing cycle upon power up, and also reset internally; see
Figure 5. Applications for this could include lawn watering
sprinkler timing, pump operation, etc.

NOTES ON THE COUNTER SECTION
Used asa straight binary counter (ICM7240), as a +100
(lCM7250), or +60 (ICM7260) all devices are significantly
faster than their bipolar equivalents. However, when using
these devices as programmable counters the maximum
frequency of operation is reduced by more than an order of
magnitude. For any division ratio other than 256 (ICM7240),
100 (ICM7250), or 60 (ICM7260) the maximum input
frequency must be limited to approximately 100kHz or less
(with VDD equal to + 5 volts). The reason for this is two-fold:
a. Since Ripple counters are used, there is a
propagation delay between each individual +2
counter (8 counters for the ICM7240/50 and 7 for
the ICM7260). Outputs from the individual +2,
counters are AND'ed together to provide the output
signal and the RESETITRIGGER Signal.
b; There must be a delay of the positive going output to
RESET, (pin 10) and TRIGGER (pin 11). The RESET
Signal must therefore be generated first, and from
this Signal another signal is obtained through a delay
network. The TRIGGER overrides RESET.
The delay between TRIGGER and RESET is generated
by the Signal RC network consisting of the 56kn resistor
and the 330pF capacitor.
The delay caused by the counter ripple delays can be as
long as 2!JS (5 volt supply), and the delay between RESET
and TRIGGER should be at least 2j.1s. The sum of these two
delays cannot be greater than one-half of the input clock
period for reliable operation. See Figure 7 and 8.

BINARY OR DECIMAL PATTERN
GENERATION
In astable operation, as shown in Figure 5, the output of
the 7240150 appears as a complex pulse pattern. The
waveform of the output pulse train can be determined
directly from the timing diagram of Figure 4, which shows
the phase relations between the counter outputs. Figure 6
shows some of these complex pulse patterns. The pulse
pattern repeats itself at a rate equal to the period of the
highest counter bit connected to the common output bus.
The minimum pulse width contained in the pulse train is
determined by the lowest counter bit connected to the
output.

THUMBWHEEL SWITCHES
While the ICM7240 is frequently hard wired for a particular function, the ICM7250 and' ICM7260 can easily be
programmed using thumbwheel switches. Standard BCD
thumbwh,eel switches have one common and four inputs
(1,2,4 and 8) which are connected according to the binary
equivalent to the digits 0 through 9.
For a single ICM7250 two such switches would select'a
time of 1RC to 99RC. Cascading two ICM7250's (using the
carry out gate) would expand selection to 9999RC. For a

Voo

Voo
10K,

C~VOD

:t

VDO

SO.F

JL

TRIGGER·
5K
OUTPUT
VDD::tr

Vs.:~

I--,!.

S,
PROGRAMMING IY SOLDER CONNECTIONS
OR THUMIWHEEL SWITCHES

*

FOR POWER UP TRIGGERINQ(1w =
AND OMIT EXTERNAL PULSE.

'._1

USE CIRCUIT SHOWN
C0025511

Figure 5: Generalized Circuit for Timing Applications (Switch S1 open for astable operation,
closed for monostable operation)

7-98
Note: All typical values have been guaranteed by characterization and are not tested,

ICM7240/1CM72~O/ICM7260
A

2 PIN PATTERNS

JLJLJUUL JlJlJ1IL-111lIl
,,.1 ~ L
,-J ~ ~8'---1_7,-l
3t

PINS 1 81 2 SHORTED t = Re

B

PINS 1 & 4 SHORTED

3PIN PATTERNS

fo-----211----..J
PINS 1, 3, &- 5 SHORTED

4 PIN PATTERNS

C

~~

----I Ir- --I
3,

_I
1--5t-,

3,

d

1- -

r---21t--

3t

b~
5t

.

3t

~-

1--85t-

PINS 1. 3. 5, & 7 SHORTED
WF020201

Figure 6: Pulse Patterns Obtained by Shorting Various Counter Outputs

CLOSE
TO INHIBIT
INTERNAL
TIMEBASE

~-----------4---_ OUTPUT
CD02561 I

Figure 7: Programming the Counter Section of the ICM7240/50/60

TBSIGNAL

OFF
PIN 1
ON

PlNZ-,

~,----"

PIN3-,

II

~----..

I

L,_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~

---.n

,

I

OFF

~,------------~

n_______

I

OUTPUT IRESET)

FF
rO
~,----"
ON

I

,-------------------J~,

,
TRIGGER

,

f\

~_

~~

-

--i~

RESET TO TRIGGER
RC DELAY

RESET TO TRIGGER
Re DELAY
WF020301

Figure 8: Waveforms for Programming the Counter Section

7-99
Note: All typical values have been guaranteed by characterization and are not tested_

PI

iN ICM7240/ICM7250/1CM7260
".
'
. ,
,.., .
....

:IE APPLICATIONS

u·

::::; GENERAL CONSIDERATIONS

iN

...
3=:::.

!...
:IE

!:!

Shorting the RC terminal or output terminals to VOD may
exceed dissipation ratings and/or maximum DC current
limits (especially at high supply voltages).
There is a limit of 50pF maximum loading on the TB I/O
terminal if the time base is being used to drive the counter
section. If higher value loading is used, the counter sections
may miscount.

ICM7240

For greatest accuracy, use timing component values
shown in the graph under Typical Performance Characteristics. For highest frequency operation it will be deSirable to
use very low values for the capacitor; accuracy will decrease for oscillator frequencies in excess of 200kHz.

ICM1240

• TRIGGERING CAN BE
OBTAINEO FROM A
PREVIOUS STAGE. A
LIMIT SWITCH, OPER-

ATOR SWITCH. ETC.

When driving the counter sectionfrom an external clock,
the optimum drive waveform is a square wave with. an
amplitude equal to supply voltage. If the clock is a very slow
ramp triangular, sine wave, etc.; it \\IiII be necassary to
"square up" the waveform (rise/fall time $ 1/ls); this can
be done by using two CMOS inverters in series, operating
from the same supply voltage as the leM 7240/50/60.

ICM7Z40

ICM724Q

By cascading devices, use of low cost CMOS AND/OR
gates and appropriate RC delays between stages, numerous sequential control variations can be obtained. Typical
applications include injection molding machine controllers,
phonograph record production machines, automatic sequencers (no metal contacts or moving parts), milling
machine controllers, process timers, autornatic lubrication
systems, etc.

ICM7240

By selection of Rand C, a wide variety of sequence
timing can be realized. A typical flow chart for a machine
tool controller could be as follows:

~tl
WAIT
, 5 SEC.

It~
ENABLE
10 SEC.

WAIT
5 SEC.

COUNT
TO 186

ENABLE

5 SEC.
LDO07401

Figure 9

7-100
Note: All typical values have been guaranteed by characterization and are not tested.

ICM7240/lCM7250/lCM7260
VDD-VSS =

QUARTZ XTAL

+ 5 VOLTS DC

VDD

= 32,761 Hz

I.

20MD

8

.".

11

330KD

,4
2

CD40808

10

CD40248

4Hz

RESET

27pF

12

vsso-+-_-'

IPULSE/MIN
IPULSEISEC

START

~:~~~-.____-1~~;;;--------'
11 TRIGGER

VDD 0--0 0-

110 CD-tOOI 8

38K

SOK

10 RESET ICM7250IPE

15K

VDD

54

S5

10K
I=OFF
O=COUNTING

S~
2 DECADE BCD
THUM8WHEEL SWITCHES

o----oVDD

SOK

BUZZER RESET

LC02061I

Figure 10
The circuit operates as tollows:
..
The time base is first selected with. S1 (seconds or
minutes), th~n units 0-99 are selected on the two thumbwheel switches S4 and S5. Finally, switch S2 is depressed
to start the timer. Simultaneously thEiquartz crystal controlled divider circuits are reset, the ICM7250 is triggered
and counting begins. The ICM7250 counts until the preprogrammed value is reached, whereupon it is reset, pin 10
of the CD40828 is enabled and the buzzer is turned on.
Pressing S3 turns the buzzer off.

CMOS PRECISION PROGRAMMABLE
0-99 SECONDS/MINUTES LABORATORY
TIMER
The ICM7250 is well suited as a laboratory timer to alert
personnel of the expiration of a preselected interval of time.
When connected as shown in Figure 10, the timer can
accurately measure preselected time intervals of 0-99
seconds or 0-99 minutes. A 5 volt buzzer alerts the
operator when the preselected time interval is over.

7-101
Note: All typical values have been guaranteed by characterization and are not tested.

fJ

,ICM72401ICM7250/ICM7260 '
I

RI

1 MEG

1.1 MEG

Voo

VDD
INTERRUPT
ONE-SHOT

RESET

VDD

13

10
, ICM7240IPE
CMOS PROGRAMMABLE BINARY TIMER

TRICGER' 11

10.. ,15K

10K

•

J1..'

p~~

"ELAPSED TIME OVER
..
INTERRUPT TO
MICROPROCESSOR

.. CIMOO1B

7

•

21, 31 • • 1.

14 CIMOO1B

•

5

~J"

2 1

~VDD

~

1

$

2

~ 14

9 • 1 11

O.,~ CI

Ca.G18B
OUADSWITCH

Ca.G18B
OUADSWITCH
13

5

8

12

13

5

8

12

5

7

•

11

17

19

21

23

TRIGGER
RESET

1.13

STROBE 2,14

ER
RESET

,.~

Ca.G17B

WR FROM MICROPROCESSOR

.....
....
14CD40001B

3,15
CIiI4S08B
8 BIT LATCH

3

8

'8

'-=k
10 , . 18 20 22

2 417

14

.I

4

DISABLE

II,•

CD4017B
DECADE COUNTER RESE1

,1 .l.a.
-=16

1
3

.001

MSB

,LSB

~

VDD

8 BIT MICROPROCESSOR BUS
lC02071I

Figure 11

LOW POWER MICROPROCESSOR
PROGFtAMMABLE INTERVAL TIMER

latch, the third triggers the ICM7240 to begin its timing cycle
and the fourth resets the decade counter.'
'

The ICM7240 CMOS programmable binary timer can be
configured as a low cost microprocessor controlled interyal
timer with the addition of a few inexpensive CD4000 series
,c;levices.
'

the ICM7240 then counts the interval of time determined
by the R-C value on pin 13, and the programmed binary
count on pins 1 through 8. At the end of the programmed
time interval, the interrupt one-shot is triggered, informing
th~ microprocessor that the programmed time interval is
over.

With the devices, connected as shown in Figure 11, the
sequence of operation is' as follows:
The microprocessor sends out an 8 bit binary code on its
8 bit 1/0 bus (the binary value needed to program the
ICM7240), followed by four WRITE pulses into the
CD40178 decade counter. The first pulse resets the 8 bit
latch, the second strobes the binary value into the 8 bit

With a resistor of approximately 10Mil and capacitor of
0.1/lF, the time base of the ICM7240 is one second. Thus, a
time of 1-255 seconds can be programmed by the microprocessor, and by varying R or C, longer or shorter time
bases can be selected.

7-102
Note: All typical values have been guaranteed by characterization and are not tested.

ICM7241
Timebase Generator
GENERAL DESCRIPTION

FEATURES

The ICM7241 is a fully integrated oscillator, 2 divider and
output driver which efficiency converts 4.194304MHz to
32.768kHz using a minimum of power. Only three external
components are necessary for complete oscillator operation; a 4.194304MHz crystal, a fixed input capacitor, and an
output trimmer capacitor. The output has a low enough
impedance to satisfy most drive requirements.

•
•
•

Single Battery Operation (1.2 -1.8V)
Low Power Consumption-Typo 40j.iA @ 1.5V
Oscillator Biasing Resistor Included On-Chip

ORDERING INFORMATION
PART NUMBER

TEMPERATURE
RANGE

PACKAGE

ICM72411PA

-20·C to + 70·C

B-Lead
Plastic

Vss
7
osc
OUTo-~~~.IYoon~------~------~

ZENER OIOOE HAS TVPICAL
BREAKDOWN VOLTAGE OF &.3 VOLT$.

Vss

Vss

05025311

Figure 1: Functional Diagram

PI

Yss

COUT

UpF
NOMINAL
VALUE

TOP VIEW
COO292l1

VDD
Yss

Figure 2: Pin Configuration
(Outline dwg PAl

32kHz

PJN 1 IS DESIGNATED BY EITHER A DOT OR A NOTCH.

OUTPUT

QUARTZ CRYSTAL PARAMETERS
t • 4.196.304 Hz

Rs·36n

Coo·IOm,_

e.,. 3.Sp'
CL -l2pF

C0029111

Figure 3: Typical Connection

7-103
Note: All typical values have been guaranteed by characterization and are not tested.

-002

i

IC.M724t

too

~

ABSOLUTE MAXIMUM RATINGS
Power Dissipation Output Short Gircuit[21 : .. : ....... 300inW
Supply Voltage (VDo-'VSS) ....... ;'.'.. '..............'.......... 3V
Output Voltage[il ................... Vss-O.3V to VoD+O.3V
[ 1 1 .....................
" VSS-O.3V
.'
Input 'Voltage
to VDD+O.3V

Storage Temperature ......... ; ... '......... -30·e to + 125·e
Operating Temperature ....................... -20·e to 70·e
Lead Temperature (Soldering, 10sec) ................. 300·e

NOTES:
1. All terminals may exceed the supply voltage (2,OV max) by ±0.3 volt provided that the currents in these terminals are limited to 2mA each,
2. This value of power dissipation refers to that of the package and will not be obtained under normal operating conditions.

ELECTRICAL CHARACTERISTICS
(VSS = 1.5V, VSS

= OV,

fosc

SYMBOL

= 4,194,304Hz,

TA = 25·e, unless otherwise specified.)

PARAMETER

TEST CONDITIONS

IDD

Supply Current

VSUPPLY

Guaranteed Operating Voltage Range

- 20·C S to S 70·C

RSAT

P·Ch Output Saturation Resistance

IOUT=·SmA

RSAT

N·Ch Output Saturation Resistance

IOUT=·SmA

fSTAB

Oscillator Stability

1,2V < VDD < 1.6V
CIN = COUT = 15pF

MIN

TYP

MAX

UNIT

40

70

pA

1.8

V

660

2

kf2

240

1

kf2

1.2

1

ppm

Oscillator Start·Up Time
1.0
s
VDD = 1.2V
tsTART
NOTE: Stresses above those hsted under Absolute Maximum RatlOgs may cause permanent damage to the deVice. These are stress ratlOgs only,
and functional operation of the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

TYPICAL PERFORMANCE CHARACTERISTICS
SUPPLY CURRENT VS. SUPPLY
VOLTAGE

I"

OSCILLATOR STABILITY
SUPPLY VOLTAGE

VS.

CURRENT (SOURCE) VS. OUTPUT
SATURATION VOLTAGE

CRYSTAL PARAMETERS
AS SPECIFIED ON PAGE 1.

CRVSTAL PARAMETERS
AS SPECIFIED ON PAGE·1

120

!...
~

II:
II:

100

eo

:0
U

i

8.

.

~

.-

~

20

•

1.2

1.3

1.4

--

1.5

If"..,
~CoUT=22pF

1.8

I

--

-j'...

·2

1.7

1.8

1.2

1,3

1.4

1.5

1.6

1.7

1.8
OUTPUT SATURATION VOLTAGE (YI

SUPPLY VOLTAGE (V)

SUf"PLY VOLTAGE (VI

0P051501
OP051401

OP051301

7-104
Note: All typical values have been guaranteed by characterization arid are' not tested.

ICM7242
Long-Range
Fixed Timer
GENERAL DESCRIPTION

FEATURES

The ICM7242 is a CMOS timer/counter circuit consisting
of an RC oscillator followed by an a-bit binary counter. It will
replace the 2242 in most applications, with a significant
reduction in the number of external components.
Three outputs are provided. They are the oscillator
output, and buffered outputs from the first and eighth
counters.
The ICM7242 is packaged in an a-pin CERDIP.

•
•
•
•
•
•

Replaces The 2242 in Most Applications
Timing From Microseconds to Days
Cascadeable
Monostable or Astable Operation
Wide Supply Voltage Range: 2-16 volts
Low Supply Current: 1151lA @ 5 volts

ORDERING INFORMATION
TEMPERATURE
RANGE

PART NUMBER

-

ICM7242D

DICE"

+

ICM72421PA

-25'C to +85'C

8 pin MINI·DIP

ICM72421JA

-25'C to +85'C

8 pin CERDIP

ICM7242CBA

D'C to + 7D'C

VDDO
..

PACKAGE

TBIIO
RC

+ 2 OUTPUT

2

7

1281256 OUTPUT

3

6

TRIGGER

Vss

4

5

RESET
CD02571I

Figure 1: Pin Configuration
(Outline Drawing JA, PAl

8 pin S.O.I.C.

"Parameter MinIMax Limits guaranteed at 25'C only for DICE orders.

VDD~--~~-------------1
1

__--__~

SOK

86K
RC

o---++-t
'----------------1>__- - - 0 +

2 OUTPUT

2

SOK
'----------------------~

____--o TB 110
8

PI

_4_-------------<1_------+-'

VSS 0 - - -......

8D010711

Figure 2: Functional Diagram

7-105
Note: All typical values have been guaranteed by characterization and are not tested.

. . (If
~ ICM7242

...

>1

ABSOLUTE MAXIMUM RATINGS
Power Dissipation[2] ...................................... 20OmW
Operating Temperature Range ........... -2SoC to +8SoC
Storage Temperature Range ............ -65·C to + 1S0·C
Lead Temperature (Soldering, 10sec) ................. 300·C

Supply Voltage (Voo to Vss) .............................. 18V
Input Voltage[1]
Terminals (Pins 5, 6, 7, 8) (VSS -0.3V) to (VOO +0.3V)
Maximum continuous output current
(each output) ......................................... 50mA

NOTES: 1. Due to the SCR structure inherent in the CMOS process, connecting any terminal to voltages greater than Voo or less than Vss may cause
destructive device latch up. For this reason, it is recommended that no inputs from external sources not operating on the same supply be applied to
the device before its supply is established and, that in mUltiple supply systems, the supply to the ICM7242 be turned on first.

2. Derate at -2mWI"C abOve 25°C.
Stresses above those listed under" Absolute Maximum Ratings" may cause permanent device failure. These are stress ratings only and functional operation
of the devices at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may cause device failures.

ELECTRICAL CHARACTERISTICS
(VOD = SV, TA = +2S·C, R = 10kU, C = 0.1IlF, Vss = OV unless otherwise specified.)
SYMBOL

PARAMETER

Voo

Guaranteed Supply Voltage

100

Supply Current

TEST CONDITIONS

MIt.!

TYP

2
Reset
Operating, R = 10kn, C - O.l/.LF
Operating, R = 1Mn, C = 0.1 /.LF
TB Inhibited, RC Connected to VSS

125
340
220
225

Timing Accuracy

MAX

UNIT

16

V

600
600

pA
pA
pA
pA

5

%

Independent of RC Components

250

ppml"C

ISOURCE = 100pA
ISINK = 1.0mA

3.5
0.40

V
V

tJ.flfn

RC Oscillator Frequency
Temperature Drift

VOTB

Time Base Output Voltage

ITBLK

Time Base Output
leakage Current

25

pA

VTRIG

Trigger Input Voltage

VOO=5V
VOO = 15V

I.S
3.5

2.0
4.5

V
V

VRST

Reset Input Voltage

Voo= 5V
Voo -15V

1.3
2.7

2.0
4.0

V
V

ITRIG,
IRST

Trigger/Reset Input Current

ft

Max Count Toggle Rate

RC = Ground

Voo-2V }
VOO = 5V
Counter/Divider Mode
Voo = 15V
50% Duty Cycle Input with Peak to
Peak Voltages Equal to Voo and vSS

2

10

/.LA

1
6
13

MHz
MHz
MHz

VSAT

Output Saturation Voltage

All Outputs except TB Output
Voo = 5V, lOUT = 3.2mA

0.22

ISOURCE

Output Sourcing
Current 7242

Voo'" 5V
Terminals 2 & 3, VOUT = 1V

300

Ct

MIN Timing Capac"or (Note 1)

Rt

Timing Resistor Range (Note 1)

0.4

pA

10
lK

Voo = 2-1SV

NOTE: 1. For Design only, not 100% tested.

7-1 OS
Note: All typical values have been guaranteed by characterization and are not tested.

V

pF
22M

n

ICM7242
VDD

L--d~"''--;}:}--_ TIMEBASE INPUTIOUTPUT
21 (Rc 2) OUTPUT o - - - - ( ] 2
2B (RC 258) OUTPUT
3

VDD

4

11

11

• TIMEBASE PERIOD = 1.0RC;
1 SEC. = lMO x I.F
TC02971I

NOTE: OUTPUTS +2 ' AND +28 ARE INVERTERS AND HAVE ACTIVE PULLUPS.

Figure 3: Test Circuit

TYPICAL PERFORMANCE CHARACTERISTICS
SUPPLY CURRENT AS A FUNCTION OF SUPPLY
VOLTAGE
260
240
220

1

..

I

,.... I

200

180

0-

z 160

II:
II:

:>

u

~

~

./

140
120
100

40

20

o J
o

V

~

./

.L-!-"'""
TA"'+25 C
Q

1// V-

.

rt/
IV

TA

/

.....r-""

L ...I-/V .".

80

60

I

TA -·20·C

RECOMMENDED RANGE OF TIMING COMPONENT
VALUES FOR ACCURATE TIMING

=+75°C

I

I

1

1

I

I

-

RESETMOOE
1

1

10

12

14

,18

TIMING CAPACITOR, C (}.IF)

SUPPL y VOLT AGE (V)
DIMENSIONS IN INCHES AND MILLIMETERS

0P045401

OP04571 I

TIMEBASE FREE RUNNING FREQUENCY AS A
FUNCTION OF RAND C

MINIMUM TRIGGER PULSE WIDTH AS A
FUNCTION OF TRIGGER AMPLITUDE
1500
1400
1300

TA = +25'C

li'12OO
S 1100
1DOO

i:

j900
~:
~800

VOO = llV

ffi

500
"400

~3OO
200

tr<:r J

5
, "

100 YDO = 2V ,..

o III
o

r

4

,

.......
7

8

9 10

TRIGGER AMPLITUDE (VOLTS)

TIME BASE FREQUENCY (Hz)
QP()45511

0Pn468l1

7-107
Note: All typical values have been guaranteed by characterization and are not tested.

IN

:t...
~TYPICAL PERFOR'MANCE CHARACTERISTICS (C()NT.)
NORMALIZED FREQUENCY STABILITY IN THE
ASTABLE MODE AS A FUNCTION OF SUPPLY
,
VOLTAGE

MINIMUM RESET PULSE, WII)THAS A ,FUNCTION
OF RESET AMPLITUDE
'

,

1500
1400
1300
1200

i
i'

1100
1000

::;

900

i

800

~

~
...

~

'"

+10.0

i!
~

TA -25"C

I

V

700

600
500
400

r<

300
200
100

/

I

I

!

'Voo= 16V

o

3

,0

""

4

~

+4,0

\

,,~

..-

'"

:

j

-6.0

l5

-8.0

-

---

~~

-,

""

I

:::;,

~ ~~ ......

"

R"

"

,':::: ......

,~

~"

'Z

7

9

-10.0
2

10

10

12

''''';

"'~

14

16

'OOM

=

~=-

0

2

I
I

C = 0.1~~"" ____

1

I

MAXIMUM DIVIDER FREQUENCY
VOLTAGE

R=loJn~

2

I

--;.....---,

~

10M

~

1M

5

5V" VOO'; 15V

:Ii

+50

;'"."
-

-

I

1

1

"

"TA - +25"C

j-~ ,RC
cONNEcTEo
TO GROUND, ,

If.- --t-r-I '\ :I i' i,
I

~ lOOK

I
+25

,

SUPPLY

VS.

¥
i

'

I

;;

i

3

!

a:
~

!

!

I

!

H-- -

5w

C=0.1pF

~

20

0P045901

0P04561!

NORMALIZED FREQUENCY STABILITY IN THE
ASTABI.i: MODE AS A FUNCTION O,F
TEMPERATURE'

3

18

SUPPLY VOLTAGE IV)

RESeT AMPLITUDE (VOLTSI

I

_

,000n ,01pF

-4.0

N

!

C
.OO1Io1F--_a ..
l00pF - - - _
.lpF

:~n :~~~F=-:_-:

"-

,

5 \,6

....~t..
0,0

S

I

R
ll1kn
lMn
lkn

+2.0

51

,
I

-'

+6.0

~w

Voo -2V

!

~

!

Q

Voo -5V

I

TA = +25·C

+8.0

,OK

o

+75

i

I

.1

i--f-

1-1
8 ,HI

12

14

16 ,18

20

SUPPLY VOLTAGE W)

TEMPERATURE ("CI

OP046201

0P046011

DISCHARGE OUTPUT CURRENT AS A FUNCTION
'OF DISCHARGE OUTPUT VOLTAGE

OUTPUT SATURATION CURRENT AS A FUNCTION
OF OUTPUT SATURATION VOLTAGE

,0

0.1

OUTPUT SATURATION VOLTAGE (V)

DISCHARGE SATURATION VOLTAGE (V)

0P046311

0P046111

7-108
Note: All typical values have been guaranteed by characterization and are not tested.

ICM7242
OPERATING CONSIDERATIONS
Shorting the RC terminal or output terminals to VDD may
exceed dissipation ratings and/or maximum DC current
limits (especially at high supply voltages).
There is a limitation of 50pF maximum loading on the TB
110 terminal if the timebase is being used to drive the
counter section. If higher value loading is used, the counter
sections may miscount.
For greatest accuracy, use timing component values
shown in the graph under typical performance characteristics. For highest frequency operation it will be desirable to
use very low values for the capacitor; accuracy will decrease for oscillator frequencies in excess of 200KHz.
When driving the counter section from an external clock,
the optimum drive waveform is a square wave with an
amplitudli' equal to supply voltage. If the clock is a very slow
ramp triangular, sine wave, etc., it will be necessary to
"square up" the waveform; this can be done by using two
CMOS inverters in series, operating from the same supply
voltage as the ICM7242.
The ICM7242 is a non-programmable timer whose principal applications will be very low frequency oscillators and
long range timers; it makes a much better low frequency
oscillator/timer than a 555 or ICM7555, because of the onchip 8-bit counter. Also, devices can be cascaded to
.
produce extremely low frequency signals.
Because outputs will not be AND'd, output inverters are
used instead of open drain N-channel transistors, and the
external resistors used for the 2242 will not be required for
the ICM7242. The ICM7242 will, however, plug into a socket
for the 2242 having these resistors.
The timing diagram for the ICM7242 is shown in Figure 4.
Assuming that the device is in the RESET mode, which
occurs on powerup or after a positive signal on the RESET
terminal (if TRIGGER is low), a positive edge on the trigger
input Signal will initiate normal operation. The discharge
transistor turns on, discharging the timing capacitor C, and
all the flip-flops in the counter chain change states. Thus,
the outputs on terminals 2 and 3 change from high to low
states. After 128 negative timebase edges, the +2 8 output
returns to the high state.
To use the 8-bit counter without the timebase, terminal 7
(RC) should be connected to ground and the outputs taken
from terminals 2 and 3.

n
.....

~_,------

_

I I I" I I I I I I I I I
'Ln~,-

tin

-

2!: ~(V+)

s

V4(V+)

CD02S81I

Figure 5: Using the ICM7242 as a Ripple
Counter (Divider)
The ICM7242 may be used for a very low frequency
square wave reference. For this application the timing
components are more convenient than thOSe that would be
required by a 555 timer. For very low frequencies, devices
may be cascaded (see Figure 6).

C00259t1

Figure 6: Low Frequency Reference
(OSCillator)
For monostable operation the +2 8 output is connected to
the RESET terminal. A positive edge on TRIGGER initiates
the cycle (NOTE: TRIGGER overrides RESET).
THE ICM7242 is superior in all respects to the 2242
except for initial accuracy and oscillator stability. This is
primarily due to the fact that high value p - resistors have
been used on the ICM7242 to provide the comparator
timing points.

PI

OUTPUT ....- - - 0

TRIGOER INPUT
(TERMINALS)

~:'=L~~TPUT
+

2 OUTPUT (TERMINAL 2)

+

1281258 OUTPUT

TRIGGER

-11'--__=
-

(TERMINAL 3) (ASTABLE
OR "FREE RUN" MODE)

"L---J
--i

Jl1lIl-

T8 OUTPUT

.... 12a1258 OUTPUT
(TERMINAL 3) (MONOST ABLE

TERMINAL 6

-I

IIIIIII f 1T1="

TERMINAL 8

OR "ONE SHOT" MODE)

!---'28RC

WF020411
.'

TC02981 I

Figure 4: Timing Diagrams of Output
Waveforms for the ICM7242.
(Compare with Figure 8)

Figure 7: Monostable Operation

7-109
Note: All typical values have been guaranteed by characterization and are not tested.

.(\1

.... ICM7242

(\I

1'-.

By selection of Rand C, a: wide variety of sequence
timing can be realized ... A typical flow chart for a machine
tool controller could be as follows:

:IE COMPARING THE ICM7242 WITH THE

2

2242
ICM7242

a.
b.

c.
d.

e.

t.

g.
h.

2242

Operating Voltage
2-16V
4-15V
Operating Temp.
-25·e to + 65·e o·e to +70·e
Range
Supply Current
O.7mA Max.
7mA Max.
VDD= 5V
Pullup Resistors
TB Output
No
Yes
+2 Output
No
Yes
+256 Output
No
Yes
Toggle Rate
3.0MHz
O:5MHz
Resistor to Inhibit
Oscillator
No
Yes
Resistor in Series
with Reset for
Monostable Operation
No
Yes
Capacitor TB
Terminal for
HF Operation
No
Sometimes

leM 7?42

".!!!!!.J t I
WAIT
5 SEC.

leM 7240

leM 7242

I t I
ENABLE
10 SEe.

I.!!!I!:...

WAIT

COUNT

5 SEC.

TO 185

ENABLE
58EC.
LDOO7501

Figure 8
By cascading devices, use of low cost CMOS AND/OR
gates and appropriate RC delays between stages, numerous sequential control variations can be obtained. Typical
applications include injection molding machine controllers,
phonograph record production machines, automatic sequencers (no metal contacts or moving parts), milling
machine controllers, process timers, automatic lubrication
systems, etc.

SEQUENCE TIMING
• Process Control
• Machine Automation

• Electro-pneumatic Drivers
.
• Multi-operation (Serial or Parallel Controlling)

r--

PUSH 51 TO STA.RT SEQUENCE:

--1

TRIGGER

MUST IE SHORTER THAN "ON lime."

5l

L _ _ _ _ _ _ _ _ _ _ _......_ _ _ _ _ _ _ _ _ _
.

.

SELECT AC VALUES TO

DISIREO"ONtime"

FOR EA,CH lCM7242

~'D~~r_-------------------

I

OUTPUT··l

_+-_____,!---'28.C----!j-_ _ _ _ _ _ __
OUTPUT

8"_-+1._______+-______---1!--'28.C-!i-_ _ _ __

OUTPUTC'

LJ

I

I

f---128RC-~

OUTPUTD'-+-I--+----+----;
II
_ _ ON

tilM~

ON timea-----f.oN

I

dm+-~H time0----1
LC020811

•
•

Process Control
Machine Automation

•
•

Electro-Pneumatic Drivers
Multi-OPeration. (Serial or Parallel Controlling)

Figure 9: Sequence Timer

Note: All typical values have been guaranteed by characterization and are rot tested.

ICM7245
Stepper Motor Quartz Clock
GENERAL DESCRIPTION

FEATURES

The ICM7245 is a very low current, low voltage microcircuit for use in analog watches. ·'t consists of an oscillator,
dividers, logic and drivers necessary to provide either
bipolar or unipolar stepper motor drive for minimum-component count watches. The oscillator is extremely stable over
wide ranges of voltage and temperature, and thus combines
high accuracy with low system power. The ICM7245 is
fabricated using Intersil's low threshold metal-gate CMOS
process.
The inverter oscillator contains all components on-chip
except for the tuning capacitor and quartz crystal. The
binary divider consists of 15 stages, the last 5 of which may
be reset. If a reset (stop) occurs during an output pulse, the
duration of the pulse is not affected. When the reset is
released, the first output occurs approximately 1 second
later. For the bipolar version, memory reset logic is included
to make sure the first pulse after a "stop" occurs on the
opposite output from the one just before the "stop".
The bipolar bridge output consists of two large inverters,
normally high. The output ON resistance of the P and N
channel devices in· series is 200n maximum @ 1mAo In
unipolar operation, the output is made up of a single
normally high inverter. The ON resistance of the N-channel
device is 50n maximum @ 3mA.

•

ORDERING INFORMATION

TABLE 1

PART NUMBER

TEMPERATURE
RANGE

-25°C to +85°C 8 pin Plastic DIP

ICM72458IPA

-25°C to + 85°C 8 pin Plastic DIP

ICM7245DIPA

•
•
•
•
•
•
•

PACKAGE

ICM7245AIPA

,

_25°C to + 85°C 8 pin PlastiC DIP

ICM7245FIPA

-25°C to +85°C 8 pin Plastic DIP

ICM7245UIPA

-25°C to + 85°C 8 pin Plastic DIP

DEVICE
NUMBER

IT.

MOTOR2

[I

MOTOR 1

IT

STOP

II

ICM7245

PULSE
WIDTH
(ms)

PULSE
OSCILLATOR
FREQUENCY CAPACITOR

·8

9.7

1Hz

ICM72458

8

7.8

1Hz

C,N

ICM7245D

8

7.8

0.1Hz
(1 pulsel
10 seconds)

COUT

ICM7245E

8

7.8

0.0833Hz
(1 pulsel
12 seconds)

C,N

ICM7245F

8

7.8

0.05Hz
(1 pulsel
20 seconds)

C,N

ICM7245U

U

3.9

1Hz

C,N

~

V·

BIPOLARI
UNIPOLAR

ICM7245A

-25°C to + 85°C 8 pin Plastic DIP

ICM7245EIPA

Very Low Current Consumption: O.4j.tA at 1.55
Volt Typical
32kHz Oscillator Requires Only Quartz Crystal
and Trimming Capacitor
Bipolar Stepper Drive With Low Output On
Resistance: 2000hms Maximum (7245 AlB/D/E/F)
Unipolar Stepper Drive With Very Low Output
On Resistance: 500hms Maximum (7245U)
Extremely Accurate: Oscillator Stability Typically
O.1ppm
STOP Function for Easy Time Synchronization
Wide Temperature Range: -25°C to +.85°C
On Chip Fixed Oscillator Capacitor: 20pF ±200/0

COUT

:Il OSC OUT
2J OSCIN
] ] TEST

~ vCD029311

Figure 1: Pin Configuration (Outline dwg PA)

7-111
Note: All typical values have been guaranteed by characterization. and are not tested.

002

=
ICM:t245
....
Il\I

~

ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Voo-VSS) ............................. , ... 3.0V
Input Voltages ................ , .. Vss-0.3 < VIN < Voo +0.3
Power Dissipation (Note 1) .............................. 25mW

Storage Temperature ... ; .............•.... -60·C to +150·C
Operating Temperature ...................... -25·C. to +85·C
Lead Temperature (Soldering, 10sec) .................. 300·C

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permiment'device failure. These are stress ratings o,lIy and functional
operation of the devices at these or any other conditions above those indicated in the operation sections of this specification is not :implied. Exposure to
absolute maximum rating conditions for extended periods may cause device failures.
Note 1: This value of power dissipation refers to that of the package and will not normally be obtained under normal operating conditions.

ELECTRICAL CHARACTERISTICS (Voo = 1.55V, Vss
unless otherwise stated Numbers are in absolute values)
SYMBOL

PARAMETER

= OV,

fosc

= 32,768Hz,

TEST CONDITIONS

circuit in Figure 2, T A = 25·C,

MIN

TYP

MAX

UNIT

0.4

0.8

pA

100

Supply Current

No Load

VSUPPLY

Operating Voltage (Voo-VSS)

O·C < TA

gm

Oscillator Transconductance

Start-up (Note 1)

15

Cose

Oscillator Capacitance

(Note 1)

16

ISTOP

STOP Input Current

ITEST

TEST Input Current

10

fSTAB

Oscillator Stability

< 50·C

1.2

1.8

V

24

IlS
pF

0.3

pA

20

0.1

100

Supply Current During Stop

Ro

Output Saturation Resistance

Bipolar (N-CH.

RO-p

Output Saturation Resistance P-CH

Unipolar IL = 3mA

200

RO-N

Output Saturation Resistance N-CH

Unipolar IL = 3mA

50

+ P-CH) IL = 1mA

1.0

pA

200

n

NOTE 1: For design reference only, not 100% tested.

I
I

~ 5·25.F
CRYSTAL

8

~ARAMETEAS

f

--'-

-¢

2

7
ICM
72458

3

-.;..STOP

- 32768 Hz

Cl -10 pF
I:M = 2.5 mpF
Rs =20kn

D32768HZ
_TCRYSTAl

4

I.SSV

5

TC09161I

Figure 2: Typical Watch Circuit

7-112
Note: All typical values have been guaranteed by characterization and are· not tested.

IlA
ppm

A(VSUPPL Y) - 0.6V
•STOP' Connected to VOO

n
n

ICM7245
(ICM7245U)

(ICM7245B)

I' 1

MOTOR

SEc

MOTOR'IMOTOR~\

'--U

~

~'SEC-l

STop_---1-----'r-r~ I
~

--------.tr

S \-1

~

U"--.

MOTOR 2

--I1--7.8ms

r~~~--'-SE-C-~~--

STOP

----------~

WF021901

WF02200J

Figure 3: Timing Waveforms

TYPICAL PERFORMANCE CHARACTERISTICS
SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE

BRIDGE OUTPUT CURRENT AS A
FUNCTION OF LOAD VOLTAGE
16

1.6

'---_---1_ _-+__ TA =125°C
1.4
Ri. =

I

.3f----t---t---t----j

_

14

60~!

toUT"" 20 pF

"!

1.2

"
-"

i"
">

t

OSCILLATOR STABILITY AS A
FUNCTION OF SUPPLY VOLTAGE

12
10

1.0
.8

--

ITA" 25'·CJ

.2/---f---f---f----l
V+-V-"'1.8V

............

""
---r-..

~=1.55V

.6

ii!

V· .4
.2
0
1.2

1.4

1.6

1.8

2.0

SUPPLY VOltAGE (VOL lS)

o

o

v-

J

1.2V-

.4

~

.8

"

.~

-.1

"-\ \

-.2/---f---f---f----l

1.6

1.2

f----t---t---t-----/

2.0

1.2

OP051601

1.4

1.6

1.8

2.0

SUPPLY VOLTAGE (VOLTS)

BRIDGE LOAD VOLTAGE (VOLTS)

OP051601

OP051701

where

APPLICATION NOTES
OSCILLATOR
The oscillator of the ICM7245 is designed for low
frequency operation at very low current from a 1.55 volt
supply. The oscillator is of the inverter type, using a nonlinear feedback resistor having maximum resistance under
start-up conditions. The nominal load capacitance of the
crystal should be less than 12pF, with a preferred range of
7-10pF. In specifying the crystal, the motional capacitance,
series resistance and tuning tolerance must be compatible
with the characteristics of the circuit to insure start-up and
operation over a wide voltage range under worst case
conditions.

RS

= Series

Resistance of Crystal

f = Frequency of the Crystal
Llf

= Frequency

Shift from Series Resonance Frequency

Co = Static Capacitance of Crystal
C'N = Input Capacitance
COUT = Output Capacitance

The following expressions can be used to arrive at a
crystal specification:

CL

Tuning Range

= Load

Capacitance

Cm = Motional Capacitance of Crystal

Llf
The gm required for start-up calculated should not
exceed 50% of the gm guaranteed for the device.
TEST POINT
The TEST input, when connected to V-, causes the
ICM7245B/U to speed-up the outputs by 16 times. On long

f

gm required for start-up
gm

= 471"2f2

CO)2
C'N COUT RS ( 1 + CL
7-113

Note: All typical values have been guaranteed by characterization and are not tested.

i
...
I

.U~U[b

ICM7245.····
period output versioris'(12,20.S0sec) the speed-up factor

Will be larger. This allows easy.t8$tillg of the finished watch
inodule. The pulse width is n6t affected by the speed-up of
the pulse frequency.

CUSTOM VERSIONS
The ICM7245 may be modified with alternative metal
. masks to provide different n\lmbeJ of dividers, various pulse
widths, and different output configurations.
In addition, MOS capacitors on-Chip up to a total of 50 pF
may be connected to either the input andlor the output of
the oscillator. Consult your Intersil representative or the
factory for further information. !.

7-114
Note: All typical values have been guaranteed by characterization and are. not tested.

ICM7249

5 h Digit LCD JJ-Pow

Event/Hour Metet

GENERAL DESCRIPTION

FEATURES

The ICM7249 Timer/Counter is intended for long-term
battery-supported industrial applications. The ICM7249 typically draws 1p.A during active timing or counting, due to
Intersil's special low-power design techniques. This allows
more than 10 years of continuous operation without battery
replacement. The chip offers four timing modes, eight
counting modes and four test modes.
The ICM7249 is a 48-lead device, powered by a single
DC voltage source and controlled by a 32.768kHz quartz
crystal. No other external components are required. Inputs
to the chip are TTL-compatible and outputs drive standard
LCD segments. The chip is available in dice and in ceramic
side-brazed packages.

•
•
•
•
•
•
•
•
•
•
•

Hour Meter Requires Only 4 Parts Total
Micropower Operation: < 1/lA at 2.8V Typical
10 Year Operation On One Lithium Cell
2h Year Battery Life With Display Connected
Directly drives 5 h Digit LCD
14 Programmable Modes of Operation
Times Hrs., 0.1 Hrs., .01 Hrs., .1 Mlns.
Counts 1's, 10's, 100's, 1000's
Dual Funtion Input Circuit:
- Selectable Debounce for Counter
- High-Pass Filter for Timer
Direct AC Line Triggering With Input Resistor
Winking "Timer Active" Display Output
Display Test Feature

APPLICATIONS
•
•
•
•

AC or DC Hour Meters
AC or DC Totalizers
Portable Battery Powered Equipment
Long Range Service Meters

ORDERING INFORMATION
1'1IACIIflA1fl

PART NUMBER

TEMPERATURE
RANGE

ICM72491DM

-40°C to + 85°C

ICM7249/D

25°C

PACKAGE
48-Pin Ceramic
Die

CD03300r

Figure 1: Pin Configuration

80014701

Figure 2: Functional Diagram

7-115
Note: All typical values have been guaranteed by characterization' and are not tested.

203500-003

ICM7249,

, .

~J

ABSOLUTE MAX'IMUM RATINGS
Operating Temperature Rang~· ............. "';40·C to 85°C
Storage Temperature Range ............... -65·C to 150·C
Lead Temperature (Soldering, 10sec) .: ............... 300·C

Supply Voltage ................................................... 6V
Input Voltage
Pins 43-48 (Note 1) ......... (VSS-O.3V) to (VDD +O.3V)
Power Dissipation (Note 2) ............................. 200mW

Stresses above those listed under Ab';;'ute Maximum Ratings' may cause permanent damaQe to the de~ice, These are stress ratings only and functional
operation of the device at these or any other conditions atiove those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS Temperature = -40·C to + 85·C, VDD
otherwise noted. Typical specifications measured at temperature = 25·C and VDD

2.2V to 5.5V, VSS = OV, unless
2.8V unless otherwise noted.
LIMITS

SYMBOL

PARAMETER

UNIT

TEST CONDITIONS
MIN

Voo

Operating Voltage

Note 3

100

Operating Current

Note 4, All inputs = Voo or GNO
VOO=2.8V
VOO = 5.5V

liN
Iss
lor
V,L
V,,,
VOL

Input Current:
Co-Ca,

V

1,0
4.0

3.0
10.0

pA
pA

1.5

1
3.0
90

pA
pA
pA

0.3 Voo

V
V

0,8

V

0.8

V

All Inputs VOO or GND
Note 5

Input Voltage:
Co-Ca, DT, SIS
,0.7 VOO
Segment Output Voltage

.IOL= lj.1A
10H = lpA

8ackpl,ane Output Voltage

Voo 0.8

IOL = 10pA
10H = 10pA

VOH

-

MAX
5.5

2.2

SIS
DT

VOH
VOL

TYP

Voo 0.8

Oscillator Stability:
Temp. = 25·C, Voo = 2.2V to 5.5V
Temp, = -40·C to + 85·C,
Voo = 2.2V to 5.5V

V

0.1

ppm

5

ppm

SIS Pulse Width:
THP
TOE
TOE
NOTES:

High-pass Filter (Modes 0-3)
Debounce (Modes 4, 6, 8, 10)
wlo Debounce (Modes 5, 7, 9, 11)

5
10,000
5

10,000

j.lS
j.lS
j.IS

1. Due to the SCR structure inherent in junction-isolated CMOS devices, the circuit can be put in a latchup mode if large currents are
injected into device inputs or outputs. For this reason special care should be taken in a system with multiple power supplies to
prevent voltages being applied to inputs or outputs before poiNer is applied. If only inputs are affected, latchup also can be
prevented by limiting the current into the input terminal to less than 1mAo
2. This limit refers to that of the package and will not occur during normal operation.
3. Internal reset to 00000 requires a maximum Voo rise time of 1j.IS. Longer rise times at power-up may cause improper reset.
4. Operating current is measured with the LCD disconnected and input current ISS supplied externally.
5. Inputs Co-Ca are latched internally and draw no DC current alter switching. During switching, a 90pA peak current may be drawn
for 10 nanoseconds.

7_116
Note: All typical values have been guaranteed by characterization and are not tested.

ICM7249
Table 1. Pin Assignment and Function
PIN

NAME

1

Be/Ce

DESCRIPTION
Half-digit LCD segment output.

PIN

NAME

37

W

DESCRIPTION
Wink-segment output.

2

F5

38

BP

Backplane for LCD reference.

3

G5

39

V+

Positive supply voltage.

4

E5

40

5

D5

41

ascI
ascO

Quartz Crystal
connections

6

Cs

42

GND

Chip GRouND.

7

B5

43

Co

8

A5

44

C1

9

F4

45

C2

10

G4

Mode-select
control inputs.

46

C3

E4

Seven-segment

47

SIS

Start I Stop

12

D4

LCD outputs.

48

DT

Display Test

13

C4

11

14

B4

15

A4

16

F3

17

G3

18

E3

19

D3

20

C3

21

B3

22

A3

23

F2

24

G2

25

E2

26

D2

27

C2

28

B2

29

A2

30

F1

31

G1

32

E1

33

D1

34

C1

35

B1

36

A1

7-117
Note: All typical values have been guaranteed by characterization and are not tested.

Table 2. Mode Select Table·
Control Pin Inputs
Mode

Function
C3

C2

Cl

Co

0

0

0

0

0

1 hour interval timer

1

0

0

0

1

0.1 hour interval timer

2

0

0

1

0

0.01 hour interval timer

3

0

0

1

1

0.1 minute interval timer

4

0

1

0

0

l's counter with debounce

5

0

1

0

1

l's counter

6

0

1

1

0

10' s counter with debounce

7

0

1

1

1

10's counter

8

1

0

0

0

100's counter with debounce

9

1

0

0

1

100' s counter

10

1

0

1

0

1000's counter with debounce

11

1

0

1

1

1000's counter

12

1

1

0

0

Test display digits

13

1

1

0

1

Internal test

14

1

1

1

0

Internal test

15

1

1

1

1

Reset
with an input frequency between 40Hz and 50Hz has an
indeterminate effect on the timing.
The timing intervals are different for each mode. For
example, in Mode 0 the display is incremented every hour,
while in Mode 3 the display is incremented every tenth of a
minute.
While timing is active, the wink·segment output W will
flash, as seen in Figure 1. On the upward transistion of SIS,
the wink output turns off. It remains off for 16 backplane
cycles and turns back on for another 16 cycles. If timing is
still active, the wink segment repeats this process, giving it
a flash rate of 1Hz: otherwise the wink output remains on
until timing begins again. In counting modes 4-11, the count
is registered and latched on each positive transition of SIS.
The display is keyed to the specific counting mode. In the
1's counter mode, the display is incremented for each
count; in the 10's counter mode, the display is incremented
after every count.

DETAILED DESCRIPTION
After power is applied, the ICM7249 requires a rise time
of tR to become active and for oscillation to begin, as seen
in Figure 3. Initially the backplane output BP is a logic '1'
level, but then changes after every 512 crystal oscillation
cycles, giving BP a square·wave frequency of 32Hz. Segments are turned off when the voltage levels of the
segment drive pins are the same as and in phase with BP.
Segments are turned on by having the drive pin voltages out
of phase with BP.
The 16 modes are selected by placing the binary
equivalent of the mode number on inputs C

TIMING

~
INDETERMINATE DURING INTERVAL

__I I-- Thp

SIS
INVALID

-------""f

40Hz < f < 50Hz

1-------

I.- TlMIN,G ACTIVE DURING INTERVAL
--I ~Thp
SIS
VALID - - - - - - -.....
WF023801

Figure 4: Start/Stop Input High-Pass Filtering in Timing Modes

7-119
Note: All typical, values have been guaranteed by characterization and are not tested.

________

~.:;::::::::::::::r~J----n-M-II-G-AC-n-v-E:::::::::::::::::~1--------

SIS
BP

w

01

SEGMEITS
OFF

SEGMEITS
WF027501

Figure 5: Wink Waveforms in Timing Modes

SIS

--~

BP

w
WF027701

Figure 6: Wink Waveforms in Counting Modes
"

"

In counter modes 4. 6, Band 10, the count pulse is
subject to debounce filtering. Figure 7 shows that only
pulses with a frequency of less than 40Hz are valid. Pulses
with a frequency between 50Hz and 120kHz are ignored,
while those with a frequency between 40Hz and 50Hz have
an indeterminate effect on the count.

During counting. the display will wink off at each count
input regardless of whether the display is incremented.
When a count occurs. the wink segment output turns off at
the end of the 16th B!i'cycle and turns back on at the end of
the 32nd BP cycle. creating a half-second wink. as shown in
Figure 6. If counting occurs more frequently than once a
second. the wink output will default to a constant .1 Hz flash
rate.

7-120
Note: All typical values have been guaranteed by characterization. and are not  26_

SIS - - - - - - - . . ,
IIVALID

}-------------COUIT WITHOUT DEBOUICE
UIKIOWI RESULTS WITH DEBOUICE

40Hz

< " < 50Hz
COUIT WITHOUT DEBOUICE
10 COUIT WITH DEBOUICE

SIS _ _ _ _ _ _ _ _..."u
VALID

50Hz s '. < 120Hz
WF027601

Figure 7: Start/Stop Input Debounce Filtering in Counting Modes

BP

I
I

I
DT

~~_____________~________________~:_______________
: ALL SEGMEITS 01

ALL

1

~~::~!! ~""~~~~®""~""_~~o:\\~

: ALL SEGMEITS Off

: DISPLAY RESTORED

"--I : \c/\ fdM$/1WF027801

Figure 8: Display Testing
lithium cell, will operate continuously for 2 Y2 years. Without
the display, which only needs to be connected when a
reading is required, the span of operation is extended to 10
years.
When the ICM7249 is configured as an attendance
counter, as shown in Figure 10, the display shows each
increment. By using mode 2, external debouncing of the
gate switch is unnecessary, provided the switch bounce is
less than 35ms.
The 3V lithium battery can be replaced without disturbing
operation if a suitable capacitor is connected in parallel with
it. The display should be disconnected, if possible, during
the procedure to minimize current drain. The capacitor
should be large enough to store charge for the amount of
time needed to physically replace the battery (At = AVCI
I). A 10llF capacitor initially charged to 3V will supply a
current of 1.01lA for 8 seconds before its voltage drops to
2.2V, which is the minimum operating voltage for the
ICM7249.
Before the battery is removed, the capacitor should be
placed in parallel, across the VDD and GND terminals. After
the battery is replaced, the capacitor can be removed and
the display reconnected.

The display may be tested at any time without disturbing
operation by pulsing DT high, as seen in Figure 8. On the
next positive transition of BP, all the segments turn on and
remain on until the end of the 16th BP cycle. This takes a
half-second or less. All the segments then turn off for an
additional 48 BP cycles (the end of the 64th cycle), after
which valid data returns to the display. As long as DT is held
high, the segments will remain on.
Additional display testing is provided by using mode 12.
In this mode each displayed decade is incremented on each
positive transition of SIS. Modes 13 and 14 are for
manufacturer testing only.
Mode 15 resets all the decades and internal counters to
zero, essentially bringing everything back to power-up
status.

APPLICATION NOTES
A typical use of the ICM7249 is seen in Figure 9, the
Motor Hour Meter. In this application the ICM7249 is
configured as an hours-in-use meter and shows how many
whole hours of line voltage have been applied. The 20Mil
resistor and high-pass filtering allow AC line activation of
the SIS input. This configuration, which is powered by a 3V
7-121

Note: All typical values have been guaranteed by characterization and are not tested.

7

!...

ICM7249

I

!'!"

LCD

/8:8·8:88
.W

BP

A, -

Bo/C.
OSC,

32.768kHz
CRYSTAL

0

ICM7249
OSC.
OT

+3V

Li

~

L -_ _ _ _~--------__~

DISPLAY
TEST
LC02981 I

Figure 9: Motor Hour Meter

LCD

18888
+3V TO +24V DC

GATE

~

,/'

20KO

W

BP

,/'

A, -

i-' 36

B.IC.

SIS

OSC,

ICM7249
DSCo

1100

Vss

H:LLi

c. c, c. c.

32.76akHz
CRYSTAL

..l

9

DT

I

--

....::r:..._
DISPLAY
TEST
AF037711

Figure 10: Attendance Counter

7-122
Note: All typical values have been guaranteed by characterization and are not tested.

ICM7555/ICM7556
General Purpose Timer
GENERAL DESCRIPTION

FEATURES

The ICM7555/6 are CMOS RC timers providing significantly improved performance over the standard
SEINE555/6 and 355 timers, while at the same time being
direct replacements for those devices in most applications.
Improved parameters include low supply current, wide
operating supply voltage range, low THRESHOLD, TRIGGER and RESET currents, no crowbarring of the supply
current during output transitions, higher frequency performance and no requirement to decouple CONTROL VOLTAGE for stable operation.
Specifically, the ICM7555/6 are stable controllers capable of producing accurate time delays or frequencies. The
ICM7556 is a dual ICM7555, with the two timers operating
independently of each other, sharing only V + and GND. In
the one shot mode, the pulse width of each circuit is
precisely controlled by one external resistor and capacitor.
For astable operation as an oscillator, the free running
frequency and the duty cycle are both accurately controlled
by two external resistors and one capacitor. Unlike the
regular bipolar 555/6 devices, the CONTROL VOLTAGE
terminal need not be decoupled with a capacitor. The
circuits are triggered and reset on falling (negative) waveforms, and the output inverter can source or sink currents
large enough to drive TTL loads, or provide minimal offsets
to drive CMOS loads.

•
•
•
•
•
•
•
•
•
•
•
•
•

APPLICATIONS
•
•
•
•
•
•
•

ORDERING INFORMATION
PART
NUMBER
ICM7555CBA
ICM75551PA
ICM75551TV
ICM7555MTV'
ICM75561PD
ICM7556MJD'

TEMPERATURE
RANGE

DOC to
-25°C
-25°C
-55°C
-25°C
-55°C

+7DoC
to + 85°C
to +85°C
to + 125°C
to +85°C
to + 125°C

-

ICM7555/D
ICM7556/D

Exact Equivalent in Most Cases for SE/NE555/
556 or TLC555/556
Low Supply Currenl- 60MA Typ. (ICM7555)
120MA Typ. (ICM7556)
Extremely Low Trigger, Threshold and Reset
Currents - 20pA Typical
High Speed Operation -1MHz Typical
Wide Operation Supply Voltage Range
Guaranteed 2 to 18 Volts
Normal Reset Function - No Crowbarring of
Supply During Output Transition
Can Be Used With Higher Impedance Timing
Elements Than Regular 555/6 for Longer RC
Time Constants
Timing From Microseconds Through Hours
Operates in Both Astable and Monostable Modes
Adjustable Duty Cycle
High Output Source/Sink Driver Can Drive TTL/
CMOS
Typical Temperature Stability of 0.005% Per °C
at 25°C
Outputs Have Very Low Offsets, HI and LO

PACKAGE
8 Lead S.O.I.C.
8 Lead MiniDip
TO-99 Can
TO-99 Can
14 Lead Plastic DIP
14 Lead CERDIP

Precision Timing
Pulse Generation
Sequential Timing
Time Delay Generation
Pulse Width Modulation
Pulse Position Modulation
Missing Pulse Detector

DICE"
DICE"

'Add 18838 to part number if 6838 processing is desired.
"Parameter MinIMax Limits guaranteed at 25"C only for DICE orders.

v' •
OUTPUT
DRIYERS

TWItE$HOLD

.....- - - t - i

,

00-------.
CONTROL

)o.-....r)o>...o-f':_

OUTPUT

VOLTAGE

COMPARATOR

•

80013701

This Functional Diagram reduces the circuitry down to its simplest equivalent components. Tie down unused inputs. R = 100klt. ± 20% typo
o

Figure 1: Functional Diagram

7-123
Note: All typical values have been guaranteed by characterization and are not tested.

PI

!

ICM75551lCM7556

•

ABSOLUTE MAXIMUM RATINGS

()

:::.
10
10
10

...

:Ii

!:!

Supply Voltage ......................................... + 18 Volts
Input Voltage: Trigger,
'
Control Voltage, Threshold, $. V+ + O.3V to 2: V- - O.3V
Reset
Output Current ..............................................1OOmA
Power Dissipation[2) ICM7556 ......................... 300mW
ICM7555 ............................................ 200mW
Storage Temperature ...................... ,..65'C to' +150·C
Lead Temperature (Soldering, 10see) ........ : ..... + 300°C

Operating Temperature Range(2)
ICM75551PA .......................... -25°C to +85°C
ICM75551TV ..................•....... -25°C to + 85°C
ICM75561PD .......................... -25°C to + 85°C
. ICM7555MTV ............. , ......... -55°C to + 125°C
ICM7556MJD ....................... - 55°C to + 125'C

NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure 'to absolute maximum' rating conditions for extended periods may affect device reliability.

v+ AND CASE

(OUTLINE DRAWING TV)

v+
DISCHARGE

OND

Tiiiiiiii

Z

OUTPUT

iiiiiT

7,

DISCHARGE

OUTPUT

•

THRISHOLD
CONTROl.
VOLTAGE

RESET

4

THRESHOLD
CONTROL

VOLTAGE

(OUTLINE DRAWING PAl

COO35701

(OUTLINE DRAWING BA)
OIICHAROE
THftUHOI.D

1
2

CONTROL

v~
OUTPUT

TiiiiiGiii

4

V·
DISCHARGE

1

THRUHOLD

11
10

~&'''l::t
iiiiiT

• TiiiiiGiii
(OUTLINE DRAWING olD. PD)
COO29901

Figure 2: Pin Configuration
(Top View)

7-124
Note: All typical values have been guaranteed by characterization and are not tested.

ICM7555/ICM7556
ELECTRICAL CHARACTERISTICS ICM7555
~YMBOL

. ,+

PARAMETER

TA = 25'C, unless otherwise specified.
TEST CONDITIONS

..

MIN

TYP MAX

UNIT

Static Supply Cuirent

TA = -55'C to 125'C
Voo= SV
VOO = 15V

40
60

Monostable Timing Accuracy

RA = 10k, C = O.I/lF
Voo=5V

2

%

Drift with Temp'

TA - -55 to 125'C
VOO =5V
VOO = 10V
VOO = 15V

150
200
250

ppml'C
ppm/'C
ppml'C

Voo=5 to 15V

O.S

%N

2

%
ppm/'C
ppm/'C
ppm/'C

Drift

w~h

Supply'

Astable Timing Accuracy

RA = RB = 10k, C = 0.1/lF', Voo = 5V

Drift with Temp'

TA = -55'C to. 125'C
Voo=5V
Voo = 10V
Voo = 15V

150
200
250

200
300

pA
p.A

Drift with Supply'

Voo=5to ISV

0.5

%N

VTH

Threshold Voltage

VOO = 15V

67

% VOO

VTRIG

Trigger Voltage

Voo = ISV

32

'TRIG

Trigger Current

Voo = 15V

10

'TH
VCV

Threshold Current

Voo = 15V

10

Control Voltage

VOO = 15V

VRST

Reset Voltage

Voo=2tol5V

IRST

Reset Current

Voo = 15V

lOIS

Discharge Leakage

Voo = 15V

VOL

Output Voltage Drop

Voo= 15V
'sink = 20mA
VOO =5V
Isink = 3.2mA

VOH

Output Voltage Drop

67
0.4

VOO = 15V
lsource

= O.SmA

VOIS

Discharge Output Voltage Drop

V+

Supply Voltage'

tR

Output Rise Time'

tF

fMAX

. Output Fall Time'
Oscillator Frequency'

nA
nA

% VOO
1.0

V

10

nA

10

nA

0.4

1.0

V

0.2

0.4

V

14.3

14.6

V

4.0

4.3

V

,

VOO = 5V
Isource

% Voo

= O.SmA

VOO= 5 to 15V
'sink = 15mA
Functional Oper.

0.2
2.0

0.4
18.0

V
V

RL -10M, CL -10pF.
Voo= 5V

75

ns

RL = 10M, CL = IOIlF,
VOO= 5V

75.

·ns

1

MHz

VOO = 5V RA = 4700hm, RB = 2700hm C = 200pF

• This parameter not tested. The majority of all parts meet this specification .

. 7-125
Note: All typical values have been guaranteed by characterization and are not tested.

.o~nlL

1-ICM755511CM7556
··Ie
~
=::.

!

ELECTRICAL CHARACTERISTICS ICM7556
.

SYMBOL

PARAMETER

1+

~

uhless

T A "" 25°C,

otherwiSe specified.

'

TEST.CONPITIONS

"

TyP MAX

MIN

UNIT.
pA
pA

S'1'tic Supply Current

T - -55°C to 125°C
VOO-5V
VOO=15V

80
120

Monestable Timing Accuracy

RA -10k, C .. 0.11lF
VOO-5V

2

%

Drift with Temp'

T = -55 to 125°C
VOO=5V
VOO = 10V
VOO= 15V

150
200
250

ppml"C
ppml"C
ppml"C

0.5

%/V

Drift with Supply'

Voo-5 to 15V

Astable Timing Accuracy

RA-RS = 10k, C=0.1IlF, VOO=5V

Drift with Temp'

.

400
800

,

2

%

T = -55°C to 125°C
Voo=5V
VOO = 10V
VOO = 15V

150
200
250

ppm/oC
ppml"C
ppml"C

Drift with Supply'

Voo=5to15V

0.5

%V

Threshold Voltage

VOO = 15V

67

% VOO

VTRIG

Trigger Voltage

VOO = 15V

32

ITRIG

Trigger, Current

VOO = 15V

10

ITH

Threshold Current

VOO = 15V

10

Vcv

Control Voltage

VOO = 15V

VRST

Reset Voltage

Voo-2 to 15V

IRST

Reset Curren1

Voo .. 15V

lOIS

Discharge Leakage

VOO = 15V

VOL

OUtPut Voltage Drop

VOO -15V
Isink = 20mA
VOO=5V
Isink .. 3.2mA

VTH

Output Voltage Drop

VOH

Discharge Output Voltage Drop

nA
nA

67
0.4

VOO -15V
lsource .. 0.8mA
VOO=5V
lsource = 0.8mA.

VOIS

. % VOO

% VOO
1.0

V

10

nA

10

nA

0.4

1.0

V

0.2

0.4

V

14.3

14.6

V

4.0

4.3

V

0.2

VOD=5toI5V
Isink = 15mA

0.4

V

V+

Supply Voltage'

F~nctional

IR

Output Rise Time'

RL - 10M, CL - 10pF,
VDO= 5V

75

ns

tF

Output Fall Time'

RL - 10M, CL - 10pF,
VoO=5V '
'

75

ns

Oscillator Frequency'

VOO .. 5V RA - 4700hm, RS = 2700hm C .. 200pF

1

MHz

·fMAX

Oper.

2.0

18.0

V

, This parameter net tested. The majority of all parts meet this specification.

TYPICAL PERFORMANCE CHARACTERISTICS

,..

MINIMUM PULSE WIDTH REQUIRED
FOR TRIGGERING

"

i''''

~

i OOO
:;000

,.

1

Z5~C

TA

. ...7" -c-- --, -

ii

~

...

i ... ~

~

.

i ...

,

o

tv

-1..,..;'
v

5V

T

/,

--

10

~~
v

20

LOWEST VOLT AOE LEVEL OF

~

!

~ r- -

-_.

, - - ,--

".g

140 ~I

.
I
~

I r-T-

iiiGGi"irPULSE

40
(GIoV')

..... 10-'

120

~ 100

".

1

1,0

-"/"

10

40

lIV

30

......
...••• "jg
...'4. ....

...

c,eo

"

VA

y'

1 JOG -

.,..,

f--

J
I.

SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE

20

~ 10-'

,..-

Vt~ l -

f

TA'

V

·20~C

Y

11.

~lc

..

I

•

10

12 '4

"

"

a:
a:

"i".

," ...."
'20

..

,-2

20

SUPPLY VOLTAGE (VOLTS)

0P054901

OP055001

7-126
Note: All typical values have been guaranteed by characterization "and are net tested,

OUTPUT VOLTAGE REFERENCEO TO V'
"1.0
"0.1
'0.01

10

/"/

T,,:. U"C

-

V'~V,;'

z

·25°C

TA

OUTPUT SOURCE CURRENT AS A
FUNCTION OF OUTPUT VOLTAGE

0.'

/'

1/
V· "'"5V

V
?

V" "11V

i I

-

.

,

OPQ55101

i...

ICM7555/ICM7556

QI
QI
QI

TYPICAL PERFORMANCE CHARACTERISTICS (CONT.)
OUTPUT SINK CURRENT AS A
FUNCTION OF OUTPUT VOLTAGE

S

ztoo

f-++-H--j;Y7f'-!+--+-+++H

10.0

II!

s

~

OUTPUT SINK CURRENT AS A
FUNCTION OF OUTPUT VOLTAGE

OUTPUT SINK CURRENT AS A
FUNCTION OF OUTPUT VOLTAGE

'00

'00

T,

Htt-v
I

10.0

::>
u

I

I
•

I

J..rTl

1.0

.iI

I

Vi

.., Vl

V/

~J-

I- ~.

1f'

I

1/

II

•.••:-+ -

:

~

~

::

i ,",,. /

II!a:

B

1 II

H'C

!

!/
:

0.0'

0.1

1.0

10.0

T,

. '.·C

1
II!
~

u

/

,..

I ..,

0.1

l
~
;:
!

~

~

.

T,

•

2

!I • --

.."e:
..
a

~

I
~

2

--

r• r-

...
4

,

,.,n-.,
IU

TA " 2S"C

V'''' IV

II \
~,

If

"

1++
Ae

i'...C, '00.'
I ,

10k!!

f

LI
100.0

....

; . 0.' i\--'-+----'--+-+---'--+--+-i--i
r:;a .0.7 k-':-+--r---+--r--+--+--+--I--i
::>

~

'0.3
'0.2 f-P<~.,...

a

~

I

-0.1

FREE RUNNING FREQUENCY AS A
FUNCTION OF RA. RB and C

o

.5O

20

30

40

TiiGGiii PULSE (.... VO)
OP055701

TIME DELAY IN THE MONOSTABLE
MODE AS A FUNCTION OF RA AND C
1.0F
loomF

'Omf 1o.-+---+--+-4-~--+----I---i

·'OmF

1

..

Ior"!.::~r'~

'n'
,oo"r--r~~~~~~~~~
'••' r--r--+--~r+-~f-\~H!H

·10
OP055901

0P055Bor

7-127
Note: All typical values have been guaranteed by characterization and are not tested.

~

' '
l00nF

U

'OnF

5

';.IF

1n.

/ 1/ 1./ 1/, 'l'"
f / 1/ 1/ 1/

loopF
tOpF

'.'

PI

./ /
././ /
· . . .Z 7' 7' '7
R,
Aotz / / /
V /~~ . / /
1/V V,~ L7

... 100;01'

i

..

T... '" 21°C

'm'

'm'
'OOn'

f-+--...p;w...-+-+--+-j~,"",I--l

10

LOWEST VOLTAGE LEVEL OF

t~mFf-"""'-+--+-4-~--+--+--i

10nF

·20
·40
TEMPERATURE ~c

"/

V,

TA'" .. 25"C
TA - -20°C-

OP055601

'.' Ior"!.::~r'k

....,...--+

~~+-.......

IU

'II

1

'00

O.10.':-.,,..........w.L..='".,,--L...L..u.....,,'=
.•,..........LJU-,~•.•
OISCHARGE LOW VOLT ACE VOL

l .,...."--r-~--'---r--r-r-r-''''''

S -0."

7J

r
TA:'" .. 700C

c
c

0f'055501

i ~:.':

1

0

NORMALIZED FREQUENCY
STABILITY IN THE ASTABLE MODE
AS A FUNCTION OF
TEMPERATURE
~

y' "'IV

.... zoo

I'
\ I

1.0
10.9
SUPPLY VOLTAGE (VOlTS)

I ...
S
.. ...
~
a

10110

~.

r'.fC-111·lriI
AA

Rs

PROPAGATION DELAY AS A
FUNCTION OF VOLTAGE LEVEL OF
TRIGGER PULSE

'00

I-A~

10.'
OPQ66401

DISCHARGE OUTPUT CURRENT AS
A FUNCTION OF DISCHARGE
OUTPUT VOLTAGE
'00 . .T1....".-r-rTTr...,.........

:slb

1.0

OUTPUT LOW VOLTAGe VOL

O~5301

OP055201

f-

[/

1.01

OUTPUT LOW YOLTAGE VOL

NORMALIZED FREQUENCY
STABILITY IN THE ASTABLE MODE
AS A FUNCTION OF SUPPLY
VOLTAGE

I

y' :2V

1/ "/
1/

/

i...
QI

IJ.. I'fVli
po- ~ s.
'/

.2
!i 10.0 f--

I..

~

1

......

/ V V

100

"

1

-..'

10

~.

100

1

10

100

loiS

....

....

""

TillE DELAY

.

10

OP058001

CD

II)
II)

...
~

i

...
II)

~

ICM7555/ICM7556
,

APPLICATI,ON NOTES
GENERAL

OUTPUT DRIVE CAPABILITY

The ICM7555/6 devices are, in most instances, direct
replacements for the NE/SE 555/6 devices. However, it is
possible to effect. economies in the external component
count using the ICM7555/6. Because the bipolar 555/6
devices produce large crowbar currents in the output driver,
it is necessary to, decouple the power supply lines with a
good capacitor close to the device. The 7555/6 devices
produce no such transients: See Figure 3.

The output driver consists of a CMOS inverter capable of
driving most logic families including CMOS and TTL. As
such, if driving CMOS, the, output swing ,at all supply
voltages will equal the supply voltage. At a supply voltage of
4.5 volts or more the ICM7555/6 will drive at least 2
standard TTL loads.

ASTABLE OPERATION
The circuit can be connected to trigger itself and free run
as a multivibrator, see Figure 4. The output swings from rail
to rail, and is a true 50% duty cycle square wave. (Trip
pOints and output swings are symmetrical). Less than a 1 %
frequency variation is observed, over a voltage range of + 5
to +15V.

500

T~ = aee
400

AV

1
f=--

1.4 RC

S E/NESS5

\

MONOSTABLE OPERATION

)\CM755S/511

zoo

400
TIME· nl

,

fore, use high values ,for R and low values for C in Figures 4
and 5.

lOG

In this mode of, operation, the timer functions as a oneshot. Initially the external capacitor (C) is held discharged by
a transistor inside the timer. Upon application of a negative
TRIGGER pulse to pin 2, the internal flip flop is set which
releases the short circuit across the external capacitor and
drives the OUTPUT high. The voltage across the capacitor
now increases exponentially with a time constant t = RAC.
When the voltage across the capacitor equals 2/3 V + , the
comparator resets the flip flop, which in turn discharges the
capacitor rapidly and also drives the OUTPUT to its low
state. TRIGGER must return to a high state before the
OUTPUT can return to a low state.

lOG
OP056101

Figure 3: Supply Current Transient'
Compared with a Standard Bipolar 555
During an Output Transition
The ICM7555/6 produces supply current spikes of only
2-3mA instead of 300-400mA and supply decoupling is
normally not necessary. Secondly, in most instances, the
CONTROL VOLTAGE decoupling capacitors are not required since the input impedance of the CMOS comparators
on chip are very high. Thus, for many applications 2
capacitors can be saved using an ICM7555, and 3 capacitors with an ICM7556.

1= G.69RC

• ~~':::~U)
5

vglJ~GE

'----~

v·

:

OPTIONAL.J..

V':s 18Y

CAPACITOR

J.

*'
CD030101

,Figure 5: Monostable Operation

10K

OUTPUT

<>-.--+--i

CONTROL VOLTAGE
The CONTROL VOLTAGE terminal permits the two trip
voltages for the THRESHOLD and TRIGGER internal
comparators to be controlled. This provides the possibility
of oscillation frequency modulation in the astable mode or
even inhibition of OSCillation, depending on the applied
voltage. In the monostable mode, delay times can be
changed by varying the applied voltage to the CONTROL
VOLTAGE pin.

R

Coo30001

Figure 4: Astable Operation

RESET
POWER SUPPLY CONSIDERATIONS

The RESET terminal is designed to have essentially the
same trip voltage as the standard bipolar 555/6, i.e. 0.6 to
0.7 volts. At all supply voltages it represents an extremely
high input impedance. The mode of operation of the RESET

Although the supply current consumed by the ICM7555/6
devices is very low, the total system supply can be high
unless the timing components are high impedance. There7-128

Note: All typical values have been guaranteed by characterization and are not tested.

ICM7555/ICM7556
function is, however, much improved over the standard
bipolar 555/6 in that it controls only the internal flip flop,
which in turn controls simultaneously the state of the
OUTPUT and DISCHARGE pins. This avoids the multiple
threshold problems sometimes encountered with slow failing edges in the bipolar devices.

V·

.

THRESHOLD

CONTAOl

I.

VOLTAGE
OUTPUT

"ND
lC02830i

Figure 6: Equivalent Circuit

TRUTH TABLE
THRESHOLD
VOLTAGE

TRIGGER
VOLTAGE

RESET

OUTPUT

DISCHARGE
SWITCH

DON'T CARE

DON'T CARE

LOW

LOW

ON

> 2/3(V+)

> 1/3(V+)

HIGH

LOW

ON

< 2/3

VTR> 1/3

HIGH

STABLE

STABLE

< 1/3(V+)

HIGH

HIGH

OFF

VTH

DON'T CARE

NOTE: RESET will dominate all other inputs: TRIGGER will dominate over THRESHOLD.

7-129
Note: All typical values have been guaranteed by characterization and are not tested.

Section 8 -

Display Drivers

.D~DI1.!...

ICM7211/12
4-Digit LCD/LED
Display Driver

II)

.:t.
...
II)

GENERAL DESCRIPTION

ICM7211 (LCD) FEATURES

The ICM7211 (LCD) and ICM7212 (LED) devices constitute a family of non-multiplexed four-digit seven-segment
CMOS display decoder-drivers.
The ICM7211 devices are configured to drive conventional LCD displays by providing a complete RC oscillator,
divider chain, backplane driver, and 28 segment outputs.
The ICM7212 devices are configured to drive commonanode LED displays, providing 28 current-controlled, low
leakage, open-drain n-channel outputs. These devices
provide a BRighTness input, which may be used at normal
logic levels as a display enable, or with a potentiometer as a
continuous display brightness control.
Both the LCD and LED devices are available with
multiplexed or microprocessor input configurations. The
multiplexed versions provide four data inputs and four Digit
Select inputs. This configuration is suitable for interfacing
with multiplexed BCD or binary output devices, such as the
ICM7217, ICM7226 and ICL7135. The microprocessor versions provide data input latches and Digit Address latches
under control of high-speed Chip Select inputs. These
devices simplify the task of implementing a cost-effective
alphanumeric seven-segment display for microprocessor
systems, without requiring extensive ROM or CPU time for
decoding and display updating.
The standard devices will provide two different decoder
configurations. The basic device will decode the four bit
binary inputs into a seven'segment alphanumeric hexadecimal output. The "A" versions will provide the "Code B"
output code, i.e., 0-9, dash, E, H, L, P, blank. Either device
will correctly decode true BCD to seven-segment decimal
outputs.
Devices in the ICM7211 17212 family are packaged in a
standard 40 pin plastic dual-in-line package and all inputs
are fully protected against static discharge.

•
•
•
•

•

•

Four Digit Non-Multiplexed 7 Segment LCD
Display Outputs With Backplane Driver
Complete Onboard RC Oscillator to Generate
Backplane Frequency
Backplane Input/Output Allows Simple
Synchronization of Slave-Devices to a Master
ICM7211 Devices Provide Separate Digit Select
Inputs to Accept Multiplexed BCD Input (Pinout
and Functionally Compatible With Sillconix
DF411)
ICM7211M Devices Provide Data and Digit
Address Latches Controlled by Chip Select
Inputs to Provide a Direct High Speed Processor
Interface
ICM7211 Decodes Binary Hexadecimal; ICM7211A
Decodes Binary to Code B (0-9, Dash, E, H, L,
P, Blank)

ICM7212 (LED) FEATURES
•
•
•

28 Current-Umlted Segment Outputs Provide 4Digit Non-Multiplexed Direct LED Drive at > SmA
Per Segment
Brightness Input Allows Direct Control of LED
Segment Current With a Single Potentiometer or
Digitally as a Display Enable
ICM7212M and ICM7212A Devices Provide Same
Input Configuration and Output Decoding
Options as the ICM7211

ORDERING INFORMATION
PART NUMBER

TEMPERATURE
RANGE

ICM7211M/D

-

ICM7211/D

PACKAGE

PART NUMBER

TEMPERATURE
RANGE

PACKAGE

DICE

ICM7212A1D

-

DICE

ICM7212AIJL

-40·C to + 85·C

40 Pin CERDIP
40 Pin PLASTIC

DICE

ICM7211 AIJL

-40·C to + 85·C

40 Pin CERDIP

ICM7212AIPL

- 40·C to + 85·C

ICM7211 AMIJL

-40·C to + 85·C

40 Pin CERDIP

ICM7212AM/D

-

ICM72111JL

-40·C to + 85·C

40 Pin CERDIP

ICM7212AMIJL

- 40·C to + 85·C

40 Pin CERDIP

DICE

ICM72111PL

-40·C to + 85·C

40 Pin PLASTIC

ICM72121JL

-40·C to + 85·C

40 Pin CERDIP

ICM7211 AIPL

-40·C to + 85·C

40 Pin PLASTIC

ICM72121PL

-40·C to + 85·C

40 Pin PLASTIC

ICM7211AMIPL

-40·C to + 85·C

40 Pin PLASTIC

ICM7212MIJL

-40·C to +85·C

40 Pin CERDIP

ICM7211 MIPL

-40·C to + 85·C

40 Pin PLASTIC

ICM7212MIPL

-40·C to +85·C

40 Pin PLASTIC

ICM7211 MIJL

-40·C to + 85·C

40 Pin CERDIP

ICM7212AMIPL

-40·C to +85·C

40 Pin PLASTIC

ICM7212AEV/KIT

ICM7211AEV/KIT

-

EVALUATION KIT

ICM7212/D

-

DICE

8-1

Note: All typical values have been guaranteed by characterization and are not tested.

-

EVALUATION KIT

-002

!; ICM1211/12 .
;:
\"I

IIg

ICM7211 (A)
1M
siGIMHT OUTPUTS '

D.

DO

SEGMENT OUTPUTS

SEGMINT OUTPUTS

••

SEGMENT OUTPUTS

OSCILLATOR
INPUT

B0015801

ICM7212 (A)
D4

03

IlEGUENT OUTPUTS'

02

01

SEGMENT OUTPUTS

SEGMENT OUTPUTS

SEGMENT OUTPUTS

BRIGHTNESS

80015901

Figure 1: Functional Diagrams

8-2
Note: All typical values have been guaranteed by characterization and are not lested.

n

ICM7211/12

I:

....N

1M
SEGMENT OUTPUTS

oa

SEGMENT OUTPUTS

D2
SEGMENT OUTPUTS

D1
SEGMENT OUTPUTS

DATA
INPUTS

2-8IT

DIGfT ADDRESS

INPUT

CHIP SELECT 1

CHIP SELECT 2

OSCILLATOR
18KHz
FREE-

.;-,28

aACKPUNE
DRIVER

RUNNING

OSCILLATOR

ENABLE

INPUT

ap~~T

BD016001

ICM7212(A)M
1M

_our.vra

-

-

DATA

80016101

Figure 1: Functional Diagrams (Cont.)

8-3
Note: All typical values have been guaranteed by characteri28tion and are not tested.

......
...

ICM7211(A)M

N

.U~UIl

ICM7.211/12
ABSOLUTE MAXIMUM RATINGS

Operating Temperature Range ........... -40~C to +85·C
Storage Temperature Range ............ - 55°C to + 125°C
Lead Temperature (Soldering, 10sec) ................. 300°C

Power Dissipation (Note 1) ....................... O.5W@ 70·C
Supply Voltage (Voo - Vss) ................................ 6.5V
Input Voltage (Any Terminal) (Note 2) ...................... ..
. VSS - O.3V to VOO + O.3V

NOTE 1: This limit refers to that of the package and will not be realized during normal operation.
NOTE 2: Due to the SCR structure inherent in the CMOS process, connecting any terminal to voltages greater than Voo or less than Vss may cause
destructive device latchup. For this reason, it is recommended that no inputs from external sources not operating on the seme power supply be
applied to the device before its supply is established, and that in multiple supply systems, the supply to the ICM7211/1CM7212 be turned on first.
Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods 'may affect device reliability.

Voo, •

.....
..
.
••

l

G'

,

., ~.-v- "0',

voo

... ••..
.. D'

F••

--

c••

7211M
7211AM

7211
7211,\

0' •

,

GO"
' l 12

.,

aMplMKl2
~

....

e, •

0' •

Ja Di;;tAdchu1iC2
31 DiIk AddreM lit 1
. . .3
H

,

.3 •

...

F'

e) "
D. Ii

"o.
E'
DO
22 C4

..

e ••

'3 It

, O.

II C4

7212
72120\

13 ,.

,•
• ____r-' ..

"Vss

G211
'2 '2

::)0.. .....
oo

I:' '4

c.

G'

~

,

.••.

...,.,

" c•

C0034611

C003451I

" .... 0..'
~V~
~

»03
02 .....
3. 01 tftIIvb

! ., .....
13

~'OO
•• I -

r:

II! F,

J2~
21~

CO03471 I

C003481I

Figure 2: Pin Configurations (Outline Drawing PL)

ELECTRICAL CHARACTERISTICS
ICM7211 CHARACTERISTICS (LCD) Voo = 5V ±10%, TA = 25°C, Vss = OV unless otherwise specified.
SYMBOL
VSUPPLY
100

PARAMETER

TEST CONDITIONS

Operating Supply Voltage Range
(Voo-Vss)
Operating Current

MIN
3

Test circuit, Display blank

TYP

MAX

UNIT
V

5

6

10

50
±10

p.A

10SCI

Oscillator Input Current

Pin 36

±2

tA, tF

Segment RiselFall Time

CL = 200pF

0.5

tA, tF

Backplane RiselFall Time

CL = 5000pF

1.5

IlS

fOSC

Oscillator Frequency

Pin 36 Floating

19

kHz

fBP

Backplane Frequency

Pin 36 Floating

150

Hz

ICM7212 CHARACTERISTIC~ (COMMON ANODE LED)
SYMBOL
VSUPPLY

PARAMETER

TEST CONDITIONS

Operating Supply Voltage Range
(Voo-Vss)

ISTBY

Operating Current
Display Off

MIN
4

Pin 5 (Brightness),
Pins 27-34-VsS

100

Operating Current

Pin 5 at Voo, Display all 8's

ISLK

Segment Leakage Current

Segment Off

ISEG

Segment On Current

Segment On. Vo = + 3V

8-4
Note: All typical values have been guaranteed by characterization and are not iested.

TYP

MAX

UNIT

5 .

6

V

10

50

IlA

200
±0.01
5

8

mA
±1

p.A
mA

n

ICM7211/12

YIH

PARAMETER

TEST CONDITIONS

MIN

Logical "I" input voltage

TYP

MAX

UNIT

I

Y

±I

p.A

±I

/lA

N

4

YIL

Logical "0" input voltage

IILK

Input leakage current

Pins 27-34

±.Ol

CIN

Input capacitance

Pins 27-34

5

ISPLK

BP/Brightness input leakage

Measured at Pin 5 with Pin 36 at YSS

±.Ol

CSPI

BP/Brightness input capacitance

'All Devices

200

pF
pF

AC CHARACTERISTICS-MULTIPLEXED INPUT CONFIGURATION

,I

twH

Digit Select Active Pulse Width

tos

Data Setup Time

500

tOH

Data' Hold Time

200

tlOS

Inter·Digit Select Time

AC CHARACTERISTICS -

Refer to Timing Diagrams

/lS
ns

2

/lS

MICROPROCESSOR INTERFACE

tWL

Chip Select Active Pulse Width

other Chip Select either held active, or
both driven together

200

tos

Data Setup Time

100

tOH

Data Hold Time

10

tiCS

Inter·Chip Select Time

2

ns
0
/lS

+

----------,

=lJ
~

ICM7211 (A)(M)

EACH SEGMENT
TO BACKPlANE
WITH 200pF

CAPACITOR

OSC 36
VSS 35
DIGIT/CHIP

S~~~~
DATA
INPUTS

N

INPUT CHARACTERISTICS (lCM7211 AND ICM7212)
SYMBOL

...
.........

I:

{ra

Voo ( MICROPROCESSOR)
VERSIONS

32

r 29

1127

VSS ( MULTIPlEXED)
VERSIONS
VOO

.&1

...
2_0_ _ _ _
2..

u-------.:.----- J
CD034401

Figure 3: Test Circuits

8-5
Note: All tvoical values have been auaranteed bv characterization and· are not tested.

ICM721'1/t2
TYPICAL PERFORMANCE CHARACTERISTICS
ICM7211 OPERATING SUPPLY
CURRENT AS A FUNCTION OF
SUPPLY VOLTAGE

ICM7211 BACKPLANE FREQUENCY
AS A FUNCTION OF SUPPLY
VOLTAGE

30

..

'80

t.:~e:'::N~EsT

CIRCUIT

I

PIN 38 OPEN

II

20
TA'

,

V

1

•

i

/

.2.

I

/

~

3

1"-

..

~

.6 ~ r"~
, r

,/

... .... '"

.... '"

J.
il

••

YO (VOlTS)
0P061211

ICM7212 OPERATING POWER (LED DISPLAy) AS A
FUNCTION OF SUPPLY VOLTAGE
.800
LED DEVICES

DISPLAY ALL EIGHTS
LED FORWARD VOLTAGE DROP

'500

V

Jflr.Ai·~DO

/

T~=25-c

/

'200

J

/

V

/

10'

'/

V

/

-",,""

/

•

•

00

4

I

~....,

V

-

OP061101

~.J., O!rrPII~ AT ~ 3' I

D

~

,VIUPP. BV

Vsupp- 4V

YSUpp (VOLT$)

ICM7212 LED SEGMENT CURRENT AS A
FUNCTION OF BRIGHTNESS CONTROL VOLTAGE
t

1/

II /
'/

"""";j-ev I-- I-J

/ /'

. / VcOSC.22pF

QP061001

.2

,;

---

3

""

/

••

Coac=22OpF

••

-I--

cosc-o

30

4

PI!6A~....!

TA'"'JrC

(PIN 36 OPEN) _

TA'1O"C

Vsupp (VOLTS)

.

1

/
/

VJ/.,

•

y

.50

-2O"?"J I
If '/

f A - 25

),

LbDDkJs

r-TA-2SOC

ICM7212 LED SEGMENT CURRENT
AS A FUNCTION OF
OUTPUT VOLTAGE

300

"

/
2

3

•

•

VOLTAGE ON BRT PIN 5 (VOLTS)

VSUPP (VOLT$)

0P061301

0P061401

INPUT DEFINITIONS
In this table, VDD and Vss are considered to be normal operating input logic levels. Actual input low and high levels are
specified under Operating Characteristics. For lowest power consumption, input signals should swing over the full supply.
INPUT

TERMINAL

TEST CONDITIONS

FUNCTION

27

Voo = Logical One
Vss = Logical Zero

Ones (Least Significant)

28

VOO = Logical One
VSS = Logical Zero

Twos

B2

29

Voo - Logical One
Vss = Logical Zero

Fours

B3

30
36

BO

B1

OSC
(LCD Devices Only)

Voo = Logical One
Vss = Logical Zero
Floating or with external capacitor to Voo
Vss

Data Input Bits

Eights (Most significant)
Oscillator input
Disables BP output devices, allowing segments to be
synchronized to an external signal input at t~e BP terminal (Pin 5)

Note: All typical values have been guaranteed by characterization and are not tested.

i1CM7211/12
ICM721111CM7212 MULTIPLEXED-BINARY INPUT CONFIGURATION
INPUT

TERMINAL

D1

31

D2

32

D3

33

D4

34

TEST CONDITIONS

FUNCTION
D1 Digit Select (Least significant)

voo ~ Active

D2 Digit Select

VSS ~ Inactive

D3 Digit Select
D4 Digit Select (Most significant)

ICM7211MIICM7212M MICROPROCESSOR INTERFACE INPUT CONFIGURATION
INPUT

DESCRIPTION

TERMINAL

DA1

Digit Address
Bit 1 (LSB)

31

DA2

Digit Address
Bit 2 (MSB)

32

CS1

Chip Select 1

33

~

Chip Select 2

34

TEST CONDITIONS
VOO ~ Logical One
VSS ~ Logical Zero

When both CS1 and ~ are taken low. the data at the Data
and Digit Select code inputs are written into the input latches.
On the rising edge of either Chip Select. the data is decoded
and written into the output latches.

VOO ~ Inactive
VSS ~ Active

The backplane output devices can be disabled by connecting the OSCillator input (pin 36) to VSS. This allows the
28 segment outputs to be synchronized directly to a signal
input at the BP terminal (pin 5). In this manner, several slave
devices may be cascaded to the backplane output of one
master device, or the backplane may be derived from an
external source. This allows the use of displayS with
characters in multiples of four and a Single backplane. A
slave device represents a load of approximately 200pF
(comparable to one additional segment). Thus the limitation
of the number of devices that can be slaved to one master
device backplane driver is the additional load represented
by the larger backplane of displays of more than four digits.
A good rule of thumb to observe in order to minimize power
consumption is to keep the backplane rise and fall times
less than about 5 microseconds. The backplane output
driver should handle the backplane to a display of 16 onehalf-inch characters. It is recommended that if more than
four devices are to be slaved together, that the backplane
signal be derived externally and all the ICM7211 devices be
slaved to it. This external Signal should be capable of driving
very large capacitive loads with short (1-2j.1S) rise and fall
times. The maximum frequency for a backplane signal
should be about 150Hz although this may be too fast for
optimum display response at lower display temperatures,
depending on the display used.

...

OtOITULECT

WF02991r

Figure 4: Multiplexed Input Timing Diagram

Cii
(ca)

FUNCTION
DA 1 & DA2 serve as a two bit Digit Address Input
DA2. DA 1 ~ 00 selects D4
DA2. DA 1 ~ 01 selects D3
DA2. DA 1 ~ 10 selects D2
DA2. DA 1 - 11 selects D1

~~------------~~

Cii

eel')

DATA AND
DIGIT
ADDRESS
. . = DONi CARE

WF030001

Figure 5: Microprocessor Interface Input
Timing Diagram

OSCILLATOR

DESCRIPTION OF OPERATION
LCD DEVICES

FREQUENCY

n r "n
nnr " n nr
UUUU UUU

JU

"UUUU
nnnr

1'----128 CYCLES---!

BACKPlANE

INPUT/OUTPUT

The LCD devices in the family (lCM7211. 7211 A. 7211 M,
7211AM) provide outputs suitable for driving conventional
four-digit, seven-segment LCD displays. These devices
include 28 individual segment drivers, backplane driver, and
a self-contained oscillator and divider chain to generate the
backplane frequency.

-----II

: - - 64 CYCLES

The segment and backplane drivers each consist of a
CMOS inverter, with the n- and p-channel devices ratioed to
provide identical on resistances, and thus equal rise and fall
times. This eliminates any DC component, which could arise
from differing rise and fall times, and ensures maximum
display life.

I

-t--

I

I...--

64 CYCLES

-1

L-

OFF SEGMENTS-----II

I

ON SeC'MENTS

"'---_....1
WF017301

Figure 6: Display Waveforms
The.onboard oscillator is designed to free run at approximately 19kHz at microampere power levels. The oscillator
8-7

Note: All typical values have been guaranteed by characterization and are not tested.

~ ICM7211/12

....
~

~

frequency is divided by 128 to provide the backplane
frequency, which will be IiPproximately 150Hz with the
oscillator free-running; the' oscillator frequency may be
reduced by connecting an external capacitor between the
OSCillator terminal and Voo.

- - -.......---vDo (LED ANODES)
l00i

,:::;
0

"

.J

-

,b'd

E

,-

(BLANK)

::,-

Ii
,
'-

,'::J
reOOO701

These devices are actually mask-programmable to provide any 16. combinations of the seven segment outputs
decoded from the four input bits. For large quantity orders
custom decoder options can be arranged. Contact the
factory for details.
The ICM7211, ICM7211A, ICM7212. and ICM7212A
devices are designed to accept multiplexed binary or BCD
input. These devices provide four separate digit lines (least
significant digit at pin 31 ascending to most significant digit
at pin 34), each of which when taken to a positive level

P = (Vsupp - VFLEO)(ISEG)(nSEG)
where VFLEO is the LED forward voltage drop, ISEG is
segment current, and nSEG is the number of "on" segments. It is recommended 'that if the device is to be
operated at elevated temperatures the segment current be
limited by use of. the BRighTness input to keep power
dissipation within the limits described above.

8-8
Note: All typical values have been guaranteed by characterization and are not tested,

ICM7211/12
APPLICATIONS

decodes and stores in the output latches of its respective
digit the character corresponding to the data at the input
port, pins 27 through 30.
The ICM7211M, ICM7211AM, ICM7212M, and
ICM7212AM devices are intended to accept data from a
data bus under processor control.
In these devices, the four data input bits and the two-bit
digit address (OA 1 pin 31, OA2 pin 32) are written into input
buffer latches when both chip select inputs (CS1 pin 33,
CS2 pin 34) are taken low. On the rising edge of either chip
select input, the content of the data input latches is
decoded and stored in the output latches of the digit
selected by the contents of the digit address latches.
An address of 00 writes into 04, OA2 = 0, OA 1 = 1 writes
into 03, OA2 = 1, OA 1 = 0 writes into 02, and 11 writes into
01. The timing relationships for inputting data are shown in
Figure 5, and the chip select pulse widths and data setup
and hold times are specified under Operating Characteristics.

8CO,.,NAAV_4_L-l-W.+-'=====:f-tt-H......

-.J

DATA

0IGIT1~~bdlli

SELECTS

1M

D.

02
01

LC03021I

Figure 9: Ganged ICM7211's Driving 8-Digit
LCD Display

LC019401

Figure 8: Segment Assignment

8-0IG1T
LCD~Y

r:::

_IV

I

l

-.h~:!:-:~I":"_-_.,
•
. .VIS
.
vee
¥DO
anAL1

UTAU

~7"'.
~

PM t7
..

s.

BBBBBSBBI

HIGH OIIDEII DIGITS

~

..
:

i.A......- .iiiiii
-.:

1CII721111
"'5"...- 115 VDD
V
-::sa

I/O _

1


Del

T'

liT

De7

r'

ALE IIIIIR PROG ""

lID

I'

~

~

f1!-

•

Vss

-

f--

r--

ICM721IC1D

7 (INPUT D.P.)

"7

01'

LI.
10 •

GNDI.

VDD
DIGITI

• OA'

..

+svl,

1

_ _ NTS

5-

JDO

DO

DO

Of

~11I

0110 12

P23

ETC.

01

'-

P01 ..

E.

I' 121

D.

.........
........ :...... '
... ~
"7

•1iIOC35

r'

I I.

01'

... 27

lIT....

R

•

...,

XTAL,l

1741

Me...!

D"

01'

•

13 ID1

~

,----l!

+5~ HEXAICOOE 81
SHUTDOWN

WiiiTE

r

I

ODD

10'

102

'DO

+S....! HEXAICODE 81
SHUTDOWN

Wiiiii

I'
LC029911

Figure 11: 16 Digit Display

8-19

Note: All typical values have been guaranteed by characterization and are not tested.

~ICM7231-ICM7234

C'oI

... NumericlAlphanumeric· Triplexed
LCD Display Driver
....

¥
...:Ii!'"C'oI
S:!

GENERAL DESCRIPTION

FEATURES

The ICM7231"7234 family of integrated circuits are designedto generate the voltage levels and switching waveforms' required to drive triplexed liquid-crystal displays.
These chips also include input buffer and digit address
decoding circuitry and contain a mask-programmed ROM
allowing six bits of input data to be decoded into 64
independent combinations of the output segments of the
selected digit.
The family is designed to interface to modern high
performance microprocessors and microcomputers and
ease system requirements for ROM space and CPU time
. needed to serVice a display.

•
•
•
•
•
•
•
•
•
•

ICM7231: Drives 8 Digits of 7 Segments With
Two Independent Annunciators Per Digit
Address and Data Input in Parallel Format
ICM7232: Drives 10 Digits of 7 Segments With
Two Independent Annunciators. Per Digit
Address and Data Input in Serial Format
ICM7233: Drives 4 Characters of 18 Segments
Address and Data Input in Parallel Format
ICM7234: Drives 5 Characters of 18 Segments
Address and Data Input in Serial Format
All Signals Required to Drive Rows and Columns
of Triplexed LCD ·Display Are Provided
Display Voltage Independent of Power Supply
On-Chip Oscillator Provides All Display Timing
Total Power Consumption Typically 200/-lW,
Maximum 500/-lW at 5V
Low-Power .Shutdown Mode Retains Data With
5JJ.W Typical Power Consumption at 5V, 1/-1W at
2V
Direct Interface to High-Speed Microprocessors

ORDERING . INFORMATION
PART NUMBER

TEMPERATURE
RANGE

PACKAGE

PART NUMBER '

TEMPERATURE
RANGE
-

PACKAGE

ICM7231AFIJL

- 25°C to + 85°C 40 pin CERDIP

ICM7232CR/D

ICM7231AFIPL

- 25°C to + 85°C 40 pin PLASTIC Dip

ICM7232CRIJ)..

-25°C to +85°C 40 pin CERDIP

DICE

ICM7231BFIJL

-25°C to + 85°C 40 pin CERDIP

ICM7232CRIPL

-25°C to + B5°C 40 pin PLASTIC Dip

ICM7231 BFIPL

-25°C to + 85°C 40 pin PLASTIC Dip

ICM7233AEVIKIT

ICM7231 CFIJL

-25°C to +85°C 40 pin CERDIP

ICM7233AF/D

ICM7231CFIPL

-25°C to + 85 0 C 40 pin PLASTfc Dip

ICM7233AFIJL

-25°C to + 85°C 40 pin CERDIP
- 25°C to + 85°C 40 pin PLASTIC Dip

Evaluiation Kit.

-

DICE

ICM7232AFIJL

-25°C to + 85°C 40 pin CERDIP

ICM7233AFIPL

ICM7232AFIPL

-25°C to +85°C 40 pin PLASTIC Dip

ICM7233AF/D

ICM72328FIJL

-25°C to + 85°C 40 pin CERDIP

ICM7234AFIJL

-25°C to +85°C 40 pin CERDIP

ICM7232BFIPL

-25°C to + 85°C 40 pin PLASTIC Dip

ICM7234AFIPL

-25°C to + 85°C 40 pin PLASTIC Dip

-

DICE

:,."

8-20

Note: All typical values have been guaranteed by characterization and are not tested.

203299-002

ICM7231-ICM7234
DO

D7

X V Z

X V Z

DO
X

V Z

DO
X V Z

DC
X

V Z

02

D2
X V

Z

X

V

D.
Z

X V Z

Voe

VH

:~!~

VL

GENERATOR

VOLTAGE
LEVEL

OUTPUT
LATCHES
8 WIDE

v....
H+--,o....:cPlN 2 (INPUT)

COM.

COMMON

O~:~~R

COM 2

'--_~r- COM 3

8ooo9B11

Figure 1: ICM7231 Functional Diagram

QtO

DO

X V Z

X V Z

DO
X V Z

07
X V

Z

DO

DO

X V Z

X V Z

os

1M
X

V Z

x

V

z

D2

o.

X Y Z

x y z

Voo

YH

:'~
VOLTAGE

LEVEL

outPUT
LATettES

VL

GENERATOA

I WIDE
H+"V-"-=-PlN2 flMlUTI

COMMON
LINE
DRivERS

COM'
COM 2
COM 3

""

/

SHIFT RECISTER
SHIFTS RIGHT TO LEFT
ON RISING EDGE OF DATA CLOCK

DATA DATA

Wi!iift

INPUT CLOCK

IWUT

'M'UT

DATA
ACCEPTED
OUTPUT
60010011

Figure 2: ICM7232 Functional Diagram

8-21

Note: All typical values have been guaranteed by characterization and are not tested.

.D~D[l

ICM7231-ICM7234
CHAR.

CHAR 3

UVWXYZ

UVWXYZ

CHAR 2
UVWXVZ

CHAR 1

UVWXYZ

SEGMENT
LINE
DRIVERS

VDD

'WIDE

ON CHIP

OUTPUT

VH

LATCHES
1aWIDE

1.

DISPLAY
VOLTAGE
LEVEL
GENERATOR

HH-_....V.::D:::...
~ PIN 2 (INPUT)
18

COM 1
COM 2
COMJ

I

jCS1,CS2,

ASCII DATA
INl'UTS

CHIP SELECT
INPUtS
80009911

Figure .3: ICM7233 Functional Diagram

c;HAR 5

UVWXYZ

CHAR.
UVWXYZ

CHAR 3
UVWXVZ

CHAR'

CHAR 1

UVWXYZ

UVWXYZ

SEGMENT
LINE
DRIVER

Vo.

• WIDE

DNCHIP
OUTPUT

V"

LATCHES
18 WIDE
18

18

DISPLAY
VOLTAGE
LEVEL
Q(NERATDR

VL

VOl.

PIN, (INPUT)

18

COM 1
COMMON
LINE
DRIVERS

COM 2
COM 3

SHIFT REGISTER

DATA
INPUT

SHIFTS RIGHT TO LEFT

ON RISING EDGE OF OAT A CLOCK..

OATA WR'ift: DATA
CLOCK INPUT ACCEPTED
INPUT
OUTPUT
B0010111

Figure 4: ICM7234 Functional Diagram

8-22
Note: All typical values have been guaranteed by characterization. and are not tested.

ICM7231-ICM7234
ABSOLUTE MAXIMUM RATINGS
Power Dissipation!l] ............................. 0.5W @ 70·C
Operating Temperature Range ........... -25·C to +85·C
Storage Temperature Range ............ -65·C to + 150·C
Lead Temperature (Soldering, 10sec) ................. 300·C

Supply Voltage (Voo - Vss) ................................ 6.5V
Input Voltage!2] ........................... VSS-0.3 ::; VIN ::; 6.5
Display Voltage!2] ....................... -0.3 ::; VOISP ::; + 0.3

NOTE: Stresses above those listed under AbsolL,te Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Notes: 1. This limit refers to that of the package and will not be obtained during normal operation.
2. Due to the SCR structure inherent in these devices, connecting any display terminal or the display voltage terminal to a voltage outside the power
supply to the chip may cause destructive device latchup. The digital inputs should never be connected to a voltage less than - 0.3 volts below
round, but ma be connected to volta es above V
but not more than 6.5 volts above V .
.

Ci
V_

co...
COM2
COld

...

,......

OATACLOC«

a:,

v..

v....

1iIIITI,,,,UT

VDI..

A'

COM'
COM2

DATA INPUT
DATA ACCEPTED

COM,

v..

COM'

v..

.
A:l

OUTOUT

,Z

IID3

1Y

102
10'

,X

10Z IX

2Z

IX 7Z

ZV

800
AN2

2V

tV 7Y

ZX

AN'

zx

tIZ 7X

2Z

..

,.

11&

,V

D4

IX

D3

,w

Da

COM2

'OR
tOY IV

.

DATACLQCI(

A'

..."

v..

v....

iiIiiTf 'NPUT

COM'

OATAINIVJ

,.

v..

COMS

5U

,V

5V

....

'X

,w

5x

,V

Dl

IV

5V

IU

DO

IU

5Z

2Z

ou

zz

4U

4.

...

av

4V

3Z

IX

3Z

IX R

IV

IV

IV

IV IV

IX

IZ

IX

IZ IX

zv

4Z

7X

4Z

7X IZ

2X

"

IV

7Y tV

2W

ex

2W

IV

DATA ACCEPTED
OUTPUT

COMa

v..

COMI

1Z
,V

,x

v..
eli,

...

ax

""

ox

7i

4X

7Z IX

2V

4V

2V

4V

5Z

IX

4Z

3Z

3U

IX

R

IX

IZ 10X

:IV

IV

AFIIF CR

.

4Z

IV

IX ,IZ
IV 10V

2U

IV

I.
5V

3X

I

I

CD024111

au

3U

3Z

IV

3X

SIll

:IW

CD02421I

COO24411

CD024311

Figure 5: Pin Configuration (Outline dwg PL)

ELECTRICAL CHARACTERISTICS (v+ =5V±10%, Vss= OV, TA=-25·C to +85·C unless otherwise specified)
SYMBOL

PARAMETER

TEST CONDITIONS/DESCRIPTION

VOO

Power Supply Voltage

VOO

Data Retention Supply Voltage

Guaranteed Retention at 2V

100

Logic Supply Current

Current from VOO to Ground excluding
Display. VOISP ~ 2V

Is

Shutdown Total Current

VOISP Pin 2 Open

VOISP

Display Voltage Range

VSS ~ VOISP ~ VOO

IOISP

Display Voltage Setup
Current

VOISP ~ 2V Current from VOO to
VOISP On·Chip

ROISP

Display Voltage Setup Resistor Value

One of Three Identical Resistors in String

DC Component of Display Signals

(Sample Test only)

fOISP

Display Frame Rate

See Figure 7

Vil

Input Low Level

VIH

Input High Level

ICM7231, ICM7233
Pins 30·35, 37·39, 1

IllK

Input Leakage

GIN

Input Capacitance

VOL

Output Low Level

Pin 37, ICM7232, ICM7234, IOl = lmA,

VOH

Output High Level

VOO

Top

Operating Temperature Range

Industrial Range

4.5V, IOH

= -500JJA

8-23
Note: All typical values have been guaranteed by characterization and are not tested.

TYP MAX

V

100

JJA

1

10

JJA
V

15

VOO
30

>4

2

1.6
30

0

40

V

75

JJA
kU

14

1

90

120

Hz

0.8

V

1

JJA
pF

004

V

+85

·C

2.0

% (VDO - VOISP)

V
0.1
5

4.1
-25

UNIT

5.5

4.5

60

ICM7232, ICM7234
Pins " 38, 39 (Note 1)

~

MIN

V

AC CHARACTERISTICS

(VDD = 5V±100/0 Vss = OV, -20·C S TA S +85·C)
PARAL LEL INPUT (I CM 7231; ICM7233 ) See Fi ure 13
TEST CONDITIONS

MIN

TYP

~cs

SYMBOL

ehip Select Pulse Width

PARAMETER

(Note 1)

500

350

tds

Address/ Data Setup Tim,,!

(Note 1)

200

idh

Address/Data Hold Time

(Note 1)

0

tics

Inter-Chip Select Time

(Note 1)

3

MAX

UNIT
ns
ns

-20

ns
IlS

SERIAL INPUT ICM7232, ICM7234) See Figures 16, 17, 18
SYMBOL

PARAMETER

TYP

MAX

TES'r CONDITIONS

MIN

ICi

Data Clock Low Time

(Note 1)

350

UNIT
ns

tel

Data Clock High Time

(Note 1)

350

ns

ids

Data Setup Time

(Note 1)

200

tdh

Data Hold Time

(Note 1)

0

-20

twp

Write Pulse Width

(Note 1)

500

350

twll

Write Pulse to Clock at Initialization

(Note 1)

1.5

ns
ns
ns

!-IS

todl

Data Accepted Low Output Delay

(Note 1)

200

400

ns

Iodh

Data Accepted High Output Delay

(Note 1)

1.5

3

j.IS

lews

Wr~e

(Note 1)

Dralay After Last Clock

350

ns

NOTE 1: For design reference only. not 100% tested.

TABLE OF FEATURES
TYPE NUMBER

OUTPUT CODE

ICM7231AF

Hexadecimal

ICM7231BF

CodeB

ICM7231CF
ICM7232AF

ANNUNCIATOR
LOCATIONS

INPUT

OUTPUT

Both Annunciators
on COM3

Parallel Entry
4 bit Data

6 Digits
plus

2 bit Annunciators

16 Annunciators

Code B

1 Annunciator COMI
1 Annunciator COM3

3 bit Address

Hexadecimal

Both Annunciators
on COM3

Serial Entry
'4 bit Data

10 Digits
plus

2 bit Annunciators
4 bit Address

20 Annunciators

Parallel Entry
6 bit (ASCII) Data

Four
Characters

ICM7232B

Code B

ICM7232CR

Code B

1 Annunciator COMI
1 Annunciator COM3

ICM7233AF

64 Character
(ASCII)
16 Segment
(Half width numbers)

No Independent
Annunciators

ICM7233BF

64 Character
(ASCII)
16 Segment
(Full width numbers)

No Independent
Annunciators

Parallel Entry
6 bit (ASCII) Data

ICM7234AF

64 Character
(ASCII)
16 Segment
(Half width numbers)

No Independent
Annunciators

Serial Entry
6 bit (ASCII) Data

ICM7234BF

64 Character
(ASCII)
16 Segment
(Full width numbers)

No Independent
Annunciators.

Serial Entry
6 bit (ASCII) Data

2 bit Address
Four
Characters

2 bit Address
Five'
Characters

3 bit Address

3 bit Address

6-24
Note: All typical values have been guaranteed by characterization and are not tested.

Five
Characters

ICM7231-ICM7234
TERMINAL DEFINITIONS
ICM7231 PARALLEL INPUT NUMERIC DISPLAY

,

TERMINAL

PIN
NO.

ANI
AN2

30
31

Annunciator 1 Control Bit
Annunciator 2 Control Bit

High =ON
Low = OFF

BOO
BDI
BD2
BD3

32
33
34
35

Least Significant}

4 Bit Binary
Data Inputs

Input
Data
(See Table 1)

AO
Al
A2

37
38
39

Least Significant}

3 Bit Digit
Address Inputs

Input
Address
(See Table 2)

CS

1

Data Input Strobe/Chip Select (Note 3)

NOTE: 3.

DESCRIPTION

Most Significant

Most Significant

FUNCTION
See Table 3

HIGH = Logical One (1)
LOW = Logical Zero (0)

Trailing (Positive going) edge latches data, causes
data input to be decoded and sent out to
addressed digit

CS

has a special" mid-level" sense ci rcuit that establishes a test mode if it is held near 3V for several msec. Inadvertent triggering of
this mode can be avoided by pulling it high when inactive, or ensuring frequent activity.

ICM7233 PARALLEL INPUT ALPHA DISPLAY
TERMINAL

PIN
NO.

DO
01
02
03
04
05

30
31
32
33
34
35

Least Significant

AO
Al

37
38

Least Significant
Most Significant J

39
1

Chip Select Inputs
(Note 3)

1

FUNCTION

DESCRIPTION

Most Signoflcant

I
1-

6 Bit (ASCII)
Data Inputs

Address Inputs

Input
Data
HIGH = Logical One (1)
LOW = Logical Zero (0)

See
Table 4
Input Add.
See Table 5

Both inputs LOW load data into input latches.
Rising edge of either input causes data to be
latched, decoded and sent out to addressed
character.

NOTE: {5S1 has a special "mid-level" sense circuit that establishes a test mode if it is .held near 3V for several I1)sec. Inadvertent triggering of
this mode can be avoided either by pulling it high when inactive, or ensuring frequent activity.

ICM7232 and ICM7234 SERIAL DATA AND ADDRESS INPUT
TERMINAL

PIN
NO.

DESCRIPTION

FUNCTION

Dafa Input

38

Data + Address Shift Register Input

HIGH = Logical One (1)
LOW = Logical Zero (0)

WRi'fE

39

Decode, Output, and Reset Strobe

When DATA ACCEPTED Output is LOW, positive
going edge of WRITE causes data in shift
register to be decoded and sent to addressed
digit, then shift register and control logiC to be
reset. When DATA ACCEPTED Output is HIGH,
positive going edge of WRITE triggers reset only.

Data Clock
Input

1

Data Shift Register and Control
Logic Clock

Positive going edge advances data in shift
register. ICM7232: Eleventh edge resets s!Jift
register and control logiC. ICM7234: Tenth edge
resets shift register and control logic.

DATA
ACCEPTED
Output

37

Handshake Output

Output LOW when correct number of bits entered
into shift register; ICM7232 8, 9 or 10 bits
ICM7234 9 bits

Input

8-25
Note: All typical values have been guaranteed by characterization and are not tested.

'lilt

'"

·CII

ICM7231"1CM7234

& ALL DEVICES

()

...
'..."
7

CII

a

TERMINAL
Display
Voltage VOISP

PIN
NO•
2

Common
Line Driver
Outputs

3,4,5

Segment
Line Driver
Outputs

6-29
6-35

FUNCTION'

DESCRIPTION
Negative end of on-chip resistor
string used to generate intermediate
voltage levels for display.
Shutdown Input.

Display voltage control. When
open (or less than 1V from VOO)
chip is shutdown; oscillator stops,
all display pins to VOO.
Drive display commons, or rows.

(On ICM7231/33)
(On ICM7232/34)

Voo

40

Chip Positive Supply

VSS

36

Chip Negative Supply

Drive display segments, or columns.

The degree of polarization of the liquid crystal material
and thus the contrast of any intersection depends on the
RMS voltage across the intersection capacitance. Note
from Figure 4 that the RMS OFF voltage is always Vp/3 and
that the RMS ON voltage is always 1.92 Vp/3.

ICM7231 FAMILY DESCRIPTION
The ICM7231 drives displays with 8 seven-segment digits
with two independent annunciators per digit, accepting six
data bits and three digit address bits from parallel inputs
controlled by a chip select input. The data bits are subdivided into four binary code bits and two annunciator control
bits.

For a 1/3 multiplexed LCD, the ratio of RMS ON to OFF
voltages is fixed at 1.92, achieving adequate display contrast with this ratio of applied RMS voltage makes some
demands on the liquid crystal material used.

The ICM7232 drives 10 seven-segment digits with two
independent annunciators per digit. To write into the
display, six bits of data and four bits of digit address are
clocked serially into a shift register, then decoded and
written to the display.

Figure 10 shows the curve of contrast versus applied
RMS voltage for a liquid crystal material tailored for
Vp = 3.1V, a typical value for 1/3-multiplexed displays in
calculators. Note that the RMS OFF voltage Vp/3'"'1V is
just below the "threshold" voltage where contrast begins to
increase. This places the RMS ON voltage at 2.1V, which
provides about 85% contrast when viewed straight on.

The ICM7233 has a parallel input structure similar to the
ICM723t, but the decoding and the outputs are organized
to drive four 18-segment alphanumeric characters. The six
data bits represent a 6-bit ASCII code.
The ICM7234 uses a serial input structure like that of the
ICM7232, and drives five 18-segment characters. Again, the
input bits represent a 6-bit ASCII code.

All members of the ICM7231/ICM7234 family use an
internal resistor string of three equal value resistors to
generate the voltages used to drive the display. One end of
the string is connected on the chip to Voo and the other
end (user input) is available at pin 2 (VOISP) on each chip.
This allows the display voltage input (VOISP) to be optimized
for the particular liquid crystal material used. Remember
that Vp = VOO - VOISP and should be three times the
threshold voltage of the liquid crystal material used. Also it
is very important that pin 2 never be driven below VSS. This
can cause device latchup and destruction of the chip.

Input levels are TTL compatible, and the DATA ACCEPTED output on the serial input devices will drive one LSTTL
load. The intermediate voltage levels necessary to drive the
display properly are generated by an on-chip resistor string,
and the output of a totally self-contained on-chip oscillator
is used to generate' all display timing. All devices in this
family have been fabricated using Intersil's MAXCMOS@
process and all inputs are protected against static discharge.

TRIPLEXED (1/3 MULTIPLEXED) LIQUID
CRYSTAL DISPLAYS

y

z

1B'.~

Figure 6 shows the connection diagram for a typical 7segment display font with two annunciators such as would
be used with an ICM7231 or ICM7232 numeric display
driver. Figure 7 shows the voltage waveforms of the
common lines and one segment line, chosen for this
example to be the "Y" segment line. This line intersects
with COM1 to form the "a" segment, COM2 to form ,he "g"
segment and COM3 to form the" d" segment. Figure 7 also
shows the waveform of the "Y" segment line for four
different ON/OFF combinations of the "a", "g" and "d"
segments_ Each intersection (segment or annunciator) acts
as a capacitance from segment line to common line, shown
schematically in· Figure 8. Figure 9 shows the voltage
across the "g" segment for the same four combinations of
ON/OFF segments in Figure 7.

lH

RH

SEGMENT LINE CONNECTION

COMMON LINE CONNECTION

COO24501

Figure 6: Connection Diagrams for
Typical 7-Segment Displays

8-26
Note: All typical values have been guaranteed by characterization and are not tested.

ICM7231-ICM7234
I .,1.2! .31 ",.1 "2'1.3'1

q---_-_-----r::
COM'T-- r-1T~ ~

-R-,-

D

"LLOFF

v+ - VOISP

Vp ..
=

. - - - - - - - - - - - - - +v,

-,

'-r-T
- n~
.J
__LJ_
LJ _
.0

COMMON AND

SEGMENT PEAK TO
PEAK VOLTAGE

Yf •VAMSOFF

YAMS'

--..,...,--------VDD

COM

zU-1- -r--w. - ,........, ·__.--_~_-1.:t---~:~.
V"

I I ~I I I I I VDD
COM3"T - - -~Vo
-' - - -

-

-

. -=-

- . . -",VL
.- _________
.J.......J._

I I- - I- - I- - I- - I- -I. VDD

.- bSEGMENT
LINE

3F::=::::::=~l:===::£
~

COMMON LINE

• SEGMENT
ON

",OFF

-

ALLaN

-

-

-

.-----

-

-

-

-

-

-

Vo

-'-_ _ _....&. - -

-

-

-

-

-

---Vp

_

-

-

-

-

-

-

-

-

-

-+Vp

"'VAMSOFF

-

-

-

-

-

-

-

-

-

-

-

-

. -Vp

:~~~~¢~-~ ~ ~~,--

-_"
"NZ

INPUT

TYPICAL

SEGMENT LINE

I I I I I I I

WAVEFORMS
(SEGMENT
LINE ''V'')

~,~ ~-=-=~=-=-=r2q~(,_.;; 'f.'-~~------------~'VP

-t

- -

_

I I I I I I I

J
- -- - -~~~ISP
I I I- ,I V
I D
I D
I
· -- - ""'---T! ----- -

l ---

-

-

-15K"

-g----~~:D

- ; . .-: r : = : : l - -= = -

-

__ -

-_"

D

V

VDD
----~VH
-

-

~

V3

- V .....

±::Ot--------C~.
I I I I I I I
· -

••,ON
dOFF

-

_

ONCIIIP
RESISTOR STRING

YL

I I I I I I I

-

I II I I I I

- -

ALL OFF

-

-

WAVEFORMS

VO
-VL
V ....

I

I

I

I

I

I

I

WF019301
WF019211

Figure 9: Voltage Waveforms on
Segment g(Vg}

Figure 7: Display Voltage Waveforms
NOTE:3-COMMON HIGH WITH RESPECT TO
SEGMENT.

VOLTAGE CONTRAST RATIO

= VRMS

3'-COMMON LOW WITH RESPECT TO
SEGMENT.

ON
VRMSOFF

= VTI = 1,92

va

COM 1 ACTIVE DURING 3-COMMON HIGH WITH RESPECT TO
SEGMENT.

COM 2 ACTIVE DURING 3,-COMMON LOW WITH RESPECT TO
SEGMENT,

COM 3 ACTIVE DURING 3 AND 3'

COM 1 ACTIVE DURING 3 AND 3'

Z_SEOMENT

I
I

I'
I
I
: RH

I
05022301

Figure 8: Display Schematic

8-27
Note: All typical values have been guaranteed by characterization and are not tested.

I

ICM7231.i.ICM7234

8

seriously degrading display contrast. Some displays also
use sealing materials unsuitable for high temperature use.
Thus, when specifying displays the following must be kept
in mind: liquid crystal material, polarizer, and seal materials.
A more important effect of temperature is the variation of
threshold voltage. For typical liquid crystal materials suitable for multiplexing, the peak vOltage has a temperature
coefficient of - 7 to-14 mVl'C. This means. that as
temperature rises, the threshold voltage goes down. Assuming a fixed value for Vp, when the threshold voltage
drops below Vp/3 OFF segments begin to be visible. Figure
11 shows the temperature dependence of peak voltage for
the same liquid crystal material of Figure 10.
For applications where the display temperature does not
vary widely, Vp may be set at a fixed voltage chosen to
make the RMS OFF voltage, Vp/3, just below the threshold
voltage at the highest temperature expected. This will
prevent OFF segments turning ON at high temperature (this
at the cost of reduced contrast for ON segments at low
temperatures).
For applications where the display temperature may vary
to wider extremes, the display voltage VDI8P (and thus Vp)
may require temperature compensation to maintain sufficient contrast without OFF segments becoming visible.

T

'...""w"
:E

2

90
90
70

~

90

I:

f---+--tT

20

10

_LIED VOLTAGE CV AMS I
OP043801

Figure 10: Contrast vs. Applied RMS Voltage

DISPLAY VOLTAGE AND TEMPERATURE
COMPENSATION

•

These circuits allow control of the display peak voltage by
bringing the bottom of.the voltage divider resistor string out
at pin 2. The simplest means for generating a display
voltage suitable to a particular display is to connect a
potentiometer from pin 2 to V88 as shown in Figure 12. A
potentiometer with a maximum value of 200 kn should give
sufficient range of adjustment to suit most displays. This
method for generating display voltage should be used only
in applications where the temperature of the .chip and
display won't vary more than ±5'C (±9'F), as the resistors
on the chip have a positive temperature coefficient, which
will tend to increase the display peak voltage with an
increase in temperature. The display voltage also depends
on the. power supply voltage,leading to tighter tolerances
for wider temperature ranges.

I I I I

I I I I I

6

~E~vbLT~GE ._~

...

4

FOR"" CONTRAST

~lON!

--

I I I T r-I I

1

o

-1p

r- -

PEAK VOLTAGE
FOR 1011 CONTRAST

r-

I cnll j

""

10

" I II
L
30

20

40

.90

AMBIENT TEMPERATURE C"CI
0P043901

OI'IlN

Figure 11: Temperature Dependence
of LC Threshold

2 v",.

TEMPERATURE EFFECTS AND
TEMPERATURE COMPENSATION

~

f10nF

40

31

~

ICM

. 7231-·

7234

The performance of the IC material is affected by
temperature in two ways. The response time of the display
to changes in applied RMS voltage gets longer as the
display temperature drops. At very low temperatures
( - 20'C) some displays may take several seconds to
change a new character after the new information appears
at the outputs. However, for most applications above O'C
this will not be a problem with available multiplexed LCD
materials, and for low-temperature applications, high-speed
liquid crystal materials are available. One high temperature
effect to consider deals with plastiC materials used to make
the polarizer. Some polarizers become soft at high temperatures and permanently lose their polarizing ability, thereby

TC029011

Figure 12: Simple Display
Voltage Adjustment
Figure 13(a) shows another method ot setting up a
display voltage using five silicon diodes in series. These
diodes, 1N914 or equivalent, will each have a forward drop
of approximately 0.65V, with approximately 20/lA flowing
8-28

Note: All typical values have been guaranteed by characterization and are not tested.

ICM7231-ICM7234
through them at room temperature. Thus, 5 diodes will give
3.25V, suitable for a 3V display using the material properties
shown in Figures 10 and 11. For higher voltage displays,
more diodes may be added. This circuit provides reasonable temperature compensation, as each diode has a
negative temperature coefficient of - 2 mV 1°C; five in
series gives -10 mVrC, not far from optimum for the
material described.
The disadvantage of the diodes in series is that only
integral multiples of the diode voltage can be achieved. The
diode voltage multiplier circuit shown in Figure 13(b) allows
fine-tuning the display voltage by means of the potentiometer; it likewise provides temperature compensation since
the temperature coefficient of the transistor base-emitter
junction (about - 2 mVrC) is also multipled. The transistor
should have a beta of at least 100 with a collector current of
10 pA. The inexpensive 2N2222 shown in the figure is a
suitable device.

2 Vow

+5V

GND

DATA.US
AF031911

Figure 14: Flexible Temperature
Compensation

~I---+Ii

35t-----,
ICM
72317234

1GnF

TC029111

Figure 13(a): String of Diodes

2GOIcll
POTENTIOMETER

2.7110

!eM
72317234

TC029211

Figure 13(b): Transistor-Multiplier
Figure 13: Diode-based Temperature
Compensation

8-29
Note: All typical values have been guaranteed by characterization and are not tested.

.D~DlL

ICM7231-iCM7234

\

ti2

INPUT

/

~--~--~~----~$l~------------~--~
~

_ _-.,.1

...

~

I

CIl

INPUT

DATA
ADDRESS

INPUT

DO NOT CARE

PARALLEL INPUT T!MING ICM7233
(lCM1Z31 HAS ONLY ONE CHIP SELECT. IT APPEARS AT PIN 1.)

WF019401

Figure 15: Parallel Input Timing

DATA

CLOCK
IM'Ul
(PER8IT
OFOATAI

1£ ! I

--+: ...
I

I
I

I

I t--Idh

I

DATA
ACCEPTED

I
I

OUT'UT

---t r--'wtl

t-twp...,

l

WlIiTr1---K=
INPUT

I

,

\'.-:::::J

»

lIB

RESETS SHIFT REGISTER _____ - - AND INPUT CONTROL
LOGtC WHEM DATA
ACCEPTED HIGH

DO NOT CARE

WF019601

Figure 16: ICM7232 One Digit Input Timing Diagram, Writing Both Annunciators
For battery operation, where the display voltage is
generally the same as the battery voltage (usually 3-4.5V),
the chip may be operated at the display voltage, with VDISP
connected to VSS. The inputs of the chip are designed such
that they may be driven above VDD without damaging the
chip. This allows, for example, the chip and display to
operate at a regulated 3V, and a microprocessor driving its
inputs to operate with a less well controlled 5V supply. (The
inputs should not be driven more than 6.5V above GND
under' any circumstances.) This also allows temperature
compensation with the ICL7663, as shown in Figure 14.
This circuit allows independent adjustment of both voltage
and temperature compensation.

DESCRIPTION OF OPERATION
PARALLEL INPUT OF DATA AND ADDRESS
(ICM7231; ICM7233)
The parallel input structure of the ICM7231 and ICM7233
devices is organized to allow simple, direct interfacing to all
microprocessors, (see functional diagrams Figures 1 and 3).
In the ICM7231, address and data bits are written into the
input latches on the rising edge of the Chip Select input. In
the ICM7233, the two Chip Selects are equivalent; when
both are low, the latches are transparent and the data is
latched on the rising edge of either Chip Select.

8-30
Note: All typical values have been guaranteed by characterization and are not tested.

ICM7231-ICM7234

1-", -1-"'--'
I

DATA _ _ _.,1
CLOCK
INPUT

DATA
ACCEPTED
OUTPUT

-..;
WIim -,.
INPUT

--I

1--"'''

I

w...........

I

tcwl~

!r RESETS SHIFT REGISTER

L...,J.- AND CONTROL LOGIC
,

I
I

WHEN DATA ACCEPTED
IS HIGH

DO NOT CARE

WF019701

Figure 17: ICM7232 Input Timing Diagram, Leaving Both Annunciators Off
The rising edge of the Chip Select also triggers an onchip pulse which enables the address decoder and latches
the decoded data into the addressed digit/character outputs. The timing requirements for the parallel input devices
are shown in Figure 15, with the values for setup, hold, and
pulse width times shown in the AC Characteristics section.
Note that there is a minimum time between Chip Select
pulses; this is to allow sufficient time for the on-chip enable
pulse to decay, and ensures that new data doesn't appear
at the decoder inputs before the decOded data is written to
the outputs.
SERIAL INPUT OF DATA AND ADDRESS (ICM7232,
ICM7234)
The ICM7232 and ICM7234 trade six pins used as data
inputs on the ICM7231 and ICM7233 for six more segment
lines, allowing two more 9-segmen~ digits (ICM7232) or one
more 18-segment character (ICM7234). This is done at the
cost of ease in interfacing, and requires that data and
address information be entered serially. Refer to functional
diagrams, Figures 2 and 4 and timing diagrams, Figures 16,
17 and 18. The inte.rface consists of four pins: DATA Input,
DATA CLOCK Input, WRITE Input and DATA ACCEPTED
Output. The data present at the DATA Input is clocked into
a shift register on the riSing edge of the DATA CLOCK Input
signal, and when the correct number of bits has been
shifted into the shift register (8 in the ICM7232, 9 in the
ICM7234), the DATA ACCEPTED Output goes low. Following this, a low-going pulse at the WRITE input will trigger the
chip to decode the data and store it in the output latches of
the addressed digit/character. After the data is latched at
the outputs, the shift register and the control logiC are reset,
returning the DATA ACCEPTED Output high. After this
occurs, a pulse at the WRITE input will not change the

outputs, but will reset the control logic and shift register,
assuring that each data bit will be entered into the correct
position in the shift register depending on subsequent
DATA CLOCK inputs.
The shift register and control logic will also be reset if too
many DATA CLOCK INPUT edges are received;. this
prevents incorrect data from being decoded. In the
ICM7232, the eleventh clock resets the shift register and
control logic, while in the ICM7234 it is the tenth.
The recommended procedure for entering data is shown
in the serial input timing diagram, Figure 16. First, when
DATA ACCEPTED is high, send a WRITE pulse. This resets
the shift register and control logic and initializes the chip for
the data input sequence. Next ,clock in the appropriate
number of correct data and address bits. The DATA
ACCEPTED Output may be monitored if desired, to determine when the chip is ready to output the decoded data.
When the correct number of bits has been entered, arid the
DATA ACCEPTED Output is low, a pulse at WRITE will
cause the data to be decoded and stored in the latches of
the addressed digit/character. The shift register and control
logiC are reset, causing DATA ACCEPTED to return high,
and leaving the chip ready to accept data for the next digiti
character.
Note that for the ICM7232 the eleventh clock resets the
shift register and control logic, but the DATA ACCEPTED
Output goes low after the eighth clock. This allows the user
to abbreviate the data to eight bits, which will write the
correct character to the 7-segment display, but will leave
the annunciators off" as shown in Figure 17.
It only AN2 is to be turned on, nine bits are clocked. in; if
AN1 is to be turned on, ali·ten bits are used.
8-31

Note: All typical values have been guaranteed by characterization and are no! tested.

ICM7231-ICM7234

TENTH CLOCK
WITH NOMOn:
PULSE RESETS

SRANDLOGle

,

DATA

CLOCK
INPUT

\..-

DATA
ACCEPTED
OUTPUT

=

_i

I-twfl

I

--l ..... i--

tcws--l

D-RE-SE-TS-SH-,F-T-.-EG-,ST-E-R-------~
I

I :~;:J:"~~~~~';:H

WF0198(l1

WRITE ORDER

Figure 18: ICM7234 One Character Input Timing Diagram
TABLE 1. BINARY DATA DECODING (ICM7231/32)

In the ICM7234, nine bits are always required; the control
logic is similar, but allowsonly a WRITE (DATA ACCEPTED
Low) with nine bits entered in the shift register, as shown in
Figure 18.
The DATA ACCEPTED Output will drive one low-power
Schottky TTL input, and has equal current drive capability
pulling high or low.
Note that in the serial input devices, it is possible to
address 'digits/characters which don't exist. As shown in
Tables 2 and 5, when an incorrect address is applied
together with a WRITE pulse, none of the outputs will be
changed.

CODE
INfUT
SO

so

DISPLAY
OUTPUT

SO SO

3

2' 1

0

0

0

0

0

o :0

0

1

0

0

l'

0

0

0

I

I

0

I

0

0

DISPLAY FONTS AND OUTPUT CODES

0

I

0

1

The standard versions of the ICM7231 and ICM7232
chips are programmed to drive a 7-segment display plus
two annunciators per digit. See Table 3 for annunciator
'
input controls.
The "A" and "s" suffix chips place both annunciators on
COM3. The display connections for one digit of this display
are shown in Figure 19. the "A" devices decode the input
data into a hexadecimal7:segmerit output, while the "S"
devices supply Code S outputs (see Table 1).
The "C" devices place the left hand annunciator, on
COM1 (AN2) and the right hand annunciator (usually a
decimal point) on COM3 (AN1). (See Figure 20). The "C"
devices provide only a "Code S" output for the 7-segments.
The ICM7233 and ICM7234 are supplied in "A" and "S"
versions. Soth versions decode an ASCII 6-bit subseUo an
l8-segment display, with 16 "flag" segmen~,.and ,two
"dots". The "A" devic.es have numbers which are half
width and the "s" devices have full width numbers. The
layout for a single character is shown in Figure 21 with
output decoding shown in Table 4.

0

I

I

0

0

I

I

I

I

0

0

0

I

0

0

I

. I

0

I

0

I

0

I

I

0

I

I

0

I

I

0

1

I

1

I

0

I

I

I

I

HEX

COOE
S

I:'

CO

,-, ,-,
'-',, '-',,
;)

:=!

1:-

-,,

-' -'
1""!'1
,- ,-'-I
,-:' CI,-:'
-I

1:1 E:

-',-,:1 '3

,-, ,,,-b :-l':
,
.:' ,,

'E P
F

BLANK
T8000801

8-32
Note: All typical values have been guaranteed by characterization and are not tested.

ICM7231-ICM7234
TABLE 2. ADDRESS DECODING (ICM7231132)

help of such a kit, an engineer or technician can have the
system "up and running" in about half an hour.
The ICM7233EV IKIT contains the appropriate ICs, a
circuit board, a Multiplexed LCD display 16/18 segment,
passive components, and miscellaneous hardware.

DISPLAY
OUTPUT

CODE INPUT
ICM7232
ONLY
A3

A2

A1

AO

DIGIT
SELECTED

0

0

0

0

01

0

0

0

1

02

0

0

1

0

03

0

0

1

1

04

0

1

0

0

05

0

1

0

1

06

0

1

1

0

07

0

1

1

1

08

1

0

0

0

09

1

0

0

1

010

1

0

1

0

NONE

1

0

1

1

NONE

1

1

0

0

NONE

1

1

0

1

NONE

1

1

1

0

NONE

1

1

1

1

NONE

x

COM1~
COM2~
COM

AN AN
2
I

:~ cr .DcplJ 9 A~
COMMON LINE CONNECTIONS

SEGMENT LINE CONNECTIQNS

80TH ANNUNCIATORS
ON COMMON #3
(AT BOTTOM OF CHARACTER)
'''A'' AND "8" SUFFIX VERSIONS)
LC019BOI

Figure 19: ICM7231 and ICM7232
Display Fonts ("A" and "B"
Suffix Versions)

~.z
lf1:i1H _.

TABLE 3. ANNUNCIATOR DECODING

COOE
INPUT

y

DISPLAY OUTPUT
ICM7231C
ICM7231 AlB
ICM7232 AlB
ICM7232C
LH
BOTH
!ANNUNCIATORS ANNUNCIATOR
COM I
ON COM 3
RH
ANNUNCIATOR
COM 3

F:

COM3'--~-~--~-

SEGMENT LINE CONNEI':TIONS

+

.. ANNUNciATORS CAN BE: ~ • [§QI ,.l::J..
-ARROWS
THAT POINT TO INFORMATION PRINTED AROUND THE DISPLAY
OPENING, ETC., WHATEVER THE DESIGNER CHOOSES TO INCORPORATE
IN THE LIQUID CRVSTAL DISPLAY.

:=:
F:

0

0

0

I

I

0

.1='
I-I
I:',

':::

I

I

.EI.

'r::.

COMMON LINE CONNECTIONS
LH ANNUNCIATOR ON COMMON # 1 (TOPI fAN 2)
RH ANNUNCIATOR ON COMMON #3IBOTTOMI (AN 11
"C" SUFFIX DEVICES

LC019901

Figure 20: ICM7231 and ICM7232 Display
Fonts ("C" Suffix Versions)

T8000901

COM 1'--,---,-,---r-,.--

EVALUATION KITS
After purchasing a sample of the ICM7231 132/33/34,
the majority of users will want to build a sample display. The
_parts can then be evaluated against the data sheet specifications, and tried out in the intended application. However,
locating and purchasing even the small number of additional components required, then wiring a breadboard, can
often cause delays of days or sometimes weeks. To avoid
this problem and facilitate evaluation of these unique
circuits, Intersil is offering kits which contain all the necessary components to build 8 character displays. With the

COM.

c~,--~-~--­

SEGMENT LINE CONNECTIONS

COMMON LINE CONNECTIONS
lC020001

Figure 21: ICM7233 and ICM7234 Display
Font (18-Segment Alphanumeric)

8-33
Note: All typical values have been guaranteed by characterization and are not tested.

''''ICM7'231-ICM7234/
....
COMPATIBLE DISPLAYS
's
()
Compatible displays are manufactured by:
....T G.E, Displays Inc., Beechwood, OhiO
.(1)

:s
...
C\I

~

(216)831·8100 (#356E3R99HJ)
Epson America Inc., Torrance CA
(Model Numbers LDB726/7/8).
Seiko Instruments USA Inc., Torrance CA
(Custom Displays)
Crystaloid, Hudson, OH
TABLE 4. DATA DECODING 6-BIT ASCII_ 18 SEGMENT
(lCM7233/34l ,
DISPLAV OUTPUT

CODE INPUT

r;:-ra-

06,04
03 02 0'

DO

0,0

O. ,

0

0

0

0

~

p

0

0

0

0

0

0

o.

0

o.
0
0

,
,

,

,

0

0

0

',0

R LI
B R

I

I

I

2 2
:; I 3 3
/I

, , [
,
I1 T Cfi Y Y
, , E
% 5 5
, , • F- U
V jj Ib 5
0

, ,

0

0

0

0

G hi
H X
, 1- y

I

".1

*

0

0
0

0

1 1

< tJ tJ
> 9 9

0

,
, , , KJ Z[ +
, ,
L \
, , , M
, , , N ?J
, , , , [J ( I
,

1,1,'

0 0

0

I

0

0

I

L

-,

?
TBO01001

TABLE 5. ADDRESS DECODING (ICM7233/34)
CODE
INPUT

DIGIT
SELECTED

ICM7234
ONLY

A1
0

AO

0

0

01

0
0
0
1
1
1
1

0
1
1
0
0
1
1

1

D2
03
04
05

A2

0
1
0
1
0
1

NONE
' NONE
NONE

8-34
Note: All typical values have been guaranteed by characterization and are not tested.

.U~UIL

ICM7231-ICM7234

I\)

TYPICAL APPLICATIONS

CoJ

J.

a
...

-

MICROCOWUHR

I\)

vool lvee
21

""

40

~VIS

20pF

·-0
-r
II

}w~

"0 27
I
I

20SC1

~

I
I
I
I

30SC2 "730

"2OpF

~--Hf';"i~--

'20 2'

"'"23
22

4 RESET
7 EA

V'- silli

-=

I~UTS{= liNT

24

IlOl'OAn

/\
27

27

'28~

r-

DBO 12
I
I

' TO

aus :

38T1

I
I

VDD

r

I
3-29

VDD

"II'

Vas

3IIOND
00 -------06 AO A1

2

VD,..

ICM7233A

caCS1

30 ---------36 37 38 38 ,

.. V'

Vas

300ND

VDIll'

20Ckn

Yo..

ICM7233A

ADJ.

30 -------- 35 37 38 31 1

1

2N2222

2

00--------06 AOA1Cs2CS1

I

1

3-29

YDD

36

'2738

TEMPE MATURE
COMOENSATiON

I

J*F -=

l~ro

EXTERN AL
MEMOR V AND
OTHER PERIPHERALS

08719

11 9 2S 108
ALE

I ~J

a...
.

line

'ROG

.

ViR
·PULL·UP RECOMMENDED ON CSl. SEE. NOTE 3.

VDD

1M!!
AF032011

Figure 22: 8048/1M80C48 Microcomputer with 8 Character 16 Segment
ASCII Triplex Liquid Crystal Display.
The two bit character address is merged with the data and written to .the display driver under the
control of the WR line. Port lines are used to .either select the target driver, or deselect all of them
for other bus operations.

6-35
Note: All typical values have been guaranteed by characterization. and are oot te.sted.

CoJ

,.

-."'--.

IlJTEF~SIL
27

27

V'

.MQ

w-___

1l1li

ISEE NOTE 31
~-_

OntER 110

•

-=

-

ROM-IIO-TtMEill
LC020211

Figure 23: MC6802 Microprocessor with 16 Character 16 Segment
ASCII Liquid Crystal Display.
The peripheral ~evlce provides ROM and Timer functions In addition to port line control of the
display bank. Individual character locations are addressed via the address bus. Note that VMA is not
decoded on these lines, which could cause problems with the TST· Instruction.

8-36
Note: All typical values have been guaranteed by characterization and are· not tested.

ICM7231-ICM7234

fIlfllfllfllfllfllfllfll

r

lJ

I

II

ICM7233

CS2

CS1

ICM7233

Ao DC)·DS

A1

CS2

CS1

A1

AO

DC).DS

6

.A

8

+SV

r

!l

TOQ60N
EPROM 1k

~

75Ok1l

~

~ ~

VOO
RC

o'1I'F~

11-

2
4

ICM7240

8

~

8 x 100kll

....... ....
...

16

f

+SV- TRIG
RESET

VSS

32

MC14049B
OR
CD4049B

.........

........

64

I

128

AS

-1
A4

A3 A2 A1

\All

A7

As

,r-

F

RC
ICM7240

1
2

Oe~

E1

+5V

TBIIO

IM66S4

Ao 00·05

mi

4

+SV- TRIG
RESET
VSS
80010211

Figure 24: EPROM-Coded Message System.
This circuit cycles through a message coded in the EPROM, pausing at the end of each line, or
whenever coded on Q6.

8-37

Note: All typical values have been guaranteed by characterization and are not tested.

·D~UIL
+

~,1'E1IIOO

I

i"INTERVA\'

t

,~[!!EJ

I FR.~.fI4'IO I

"1

FRIEQUEJtCy

I

9. 8.
I 9. 9. B~ B.B.
. '" B.

"'.,

I, ~,

. lOVER

RANGE

~

J='~ 1'~
TC029301

Figure. 25: .10MHz Frequency/Period Pointer with LCD Display.
The annunciators show function and the decimal pOints indicate the range of the current operation.
The system can be efficiently battery 'operated.

08

CJ

07

06

o.

04

03

0'

0'

B.. B.. B.. B. ~B..B. ~B..B.

COM 1
COM.
COM'

ICM7231AF/BF

TOP VIEW

COO24601

Figure 26: "Forward" Pin Orientation and Display Connections

Note: All typical values have been guaranteed by characterization and are not tested,'

ICM7231-ICM7234
01.

DO

01

DO

05

D3

D2

01

B. 8. B. B. B. B. '8. B. B. 8.

COM 1

COM'
COM.

'-----}.,-

PCB TRACES UNOER PACKAGE

COO24701

Figure 27: "Reverse" Pin Orientation and Display Connections

ICM7233AFfO

w
v

v~U-'--T"""'T"'--_}._

L - -_ _
V'::-:::-::-x
----,W

LCD

DIE MOUNTS UNDER lCD

TOP VIEW (BOTH DIE AND lCDI

CD024BOI

Figure 28: "Forward" Die Pad Orientation and Typical Triplex
Alphanumeric Display Connections

8-39
Note: All typical values have been guaranteed by characterization and are not tested.

~

ICM7235

,~ 4-Di9~t Vacuum

g Fluorescent Display Driver
GENERAL DESCRIPTION

FEATURES

The ICM7235 family of display driver circuits provides the
user with a single chip interface between digital logic or
microprocessors to non-multiplexed 7-segment vacuum
fluorescent displays.
'
The chips provide 28 high voltage open drain P-channel
transistor outputs organized as four 7-segment digits. The
devices are available with two input configurations. The
basic devices provide four data-bit inputs and four digit
select inputs. This configuration is suitable for interfacing
with multiplexed BCD or binary output devices such as the
IntersillCM7217, ICM7226 and ICL7135. The ~icroproces­
sor interface devices (suffix M) provide data input latches
and digit address latches under control of high-speed chip
select inputs. These devices simplify the task of implementing a cost-effective alphanumeric 7-segment display for
microprocessor systems, without requiring extensive ROM
or CPU time for decoding and display updating.
The standard devices available will provide two different
decoder configurations. The basic device will decode the
four bit binary input into a seven-segment alphanumeric
hexadecimal output (0-9, A-F). The "A" versions provide
the Code "B" output (0-9, dash, E, H, L, P, blank). Either
device will correctly decode true BCD to seven-segment
decimal outputs.
'

•

VDD

,,~ 4ii

El
Gt

~

Ff
Fa
Fl F.

DISPLAY ON/oFF

rt
't
'fa
'TI

01
Cl

~

81
AI

:!

~

ICM
7235135A

34
'E

ORDERING INFORMATION
.ORDER PART
NUMBER

~
Ts

-20'C to + 85'C

40 Pin CERDIP

-20'C to + 85'C

40 Pin CERDIP

ICM7235MIPL

-20'C to + 85'C

40 Pin PLASTIC

ICM7235AIJL

-20'C to +85'C

40 Pin PLASTIC

ICM7235AIPL

-20'C to + 85'C

40 Pin PLASTIC

ICM7235AMIJL

-20'C to +85'C

40 Pin CERDIP

ICM7235AMIPL

-20'C to + 85'C

40 Pin PLASTIC

ICM7235/D

DICE

ICM7235A/D

DICE

ICM7235AM/D

DICE

ICM7235M/D

DICE

DISPLAYONIQFF

~ 140

!iii

DSI Inputs

!

G3~

~D4

~ F4
25 G4
~E4

F3~
A4~

~ C4
~B4

~ Vss
~ VDD
34
ICM
7235M/35AM

FIT

lit

83}
B2 Data
81 Inputs
27 SO

C3~
D3 16
E3~

~

Fa

D1
C1

~81
~ AI

A2~

82 7
C2
D21i"
E2 ~
G2
F2

DS4}
DS3 Oigit

PACKAGE

ICM7235MIJL

Ff
Ff

~ DS2 Select

'TI

TEMPERATURE
RANGE

ICM7235IPL

~

G2
F2 ~
A3
83 1.

~

•
•

VDD " .
E1
G1
Fl

Vss
~ VDD

A2,;
B2 7
C2
D2
E2

~

•
•
•

28 High Voltage Output8 Drive Four 7-Segment
Digits
Multiplexed BCD Input (7235)
High Speed Processor Interface (7235M)
7-Segment Hexadecimal or Code-B Output
Versions Available
Display Blanking Input
Low Power Operation

A3~

iii
F,i

~
~

'TI

Ijij
~
~

83
C3
D3Fii'

I¥,

Fii

IB

E3~

G3
F3Fi'i
A4 ~

~
~
~
~

]1

:

32
31
30
26
2S
27
F4
G4
E4
D4
C4
84

~~I CHIP SELECT INPUTS

ilA21 DIGIT ADDRESS
DAI

83 }
82 DATA INPUTS
Bl

BO

C0033711

Coo33601

Figure 1: Pin Configurations

8-40
Note: All typical values have been guaranteed by characterization and are. not teSted.

-002

ICM7235
ABSOLUTE MAXIMUM RATINGS
Power Dissipation (Note 1) ................. O.5W @ + 70 0 e
Supply Voltage (Voo-VSS) ........................... 6.5 Volts
Input Voltage (Note 2) ........... VSS -O.3V to Voo+O.3V
Output Voltage (Note 3) ............................. VoO-35V

Operating Temperature Range ........... -20 o e to + 85°e
Storage Temperature Range ............ -55°e to + 125°e
Lead Temperature (Soldering. 10sec) ................. 300 o e

. Stresses above listed under" Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation
of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

04

03

SEGMENT OUTPUTS

SfGMENT OUTPUTS

0'

D'

SEGMENT OUTPUTS

SEGMENT OUTPUTS

OATA
INPUTS

DIGIT

SElECT
INPUTS
80010301

Figure 2: ICM7235/35A Functional Diagram

D4
SEGMENT OUTPUTS

03

02

SEGMENT OUTPUTS

SEGMENT OUTPUTS

01
SEGMENT OUTPUTS

DISPLAY
01 Off

DATA
INPUTS

2·81T
DIGIT ADDRESS

CHIP SELECT 1

cAip SELECT 2

BD01540l

Figure 3: ICM7235M/35AM Functional Diagram

8-41
Note: All typical values have been guaranteed by characterization and are not tested.

glCM7235

...

~

ELECTRICAL CHARACTERISTICS (All parameters measured with VOO = 5V±10%, VSS = av, TA = 25°C,
unless stated otherwise).
P~RAMETER

SYMBOL

TEST CONDITIONS

Operating Supply Voltage Range (Voo - VSS)

ISTBY

Supply Current

100

Supply Current

Measured Voo to Display

Segment OFF Output Voltage

ISLK = 101lA

Segment OFF Leakage Current

VSEG = Voo-30V

Segment ON Current

VSEG = Voo-2V

VSEG
ILS
ISEG

MIN

TYP

4

VsuPP

Measured VOO to VSS
Test circuit; display blank or OFF

10

MAX UNIT
6

V

50

IlA

100

rnA

10

IlA

30

V
0.1

1.5

2.5

rnA

MIN

TYP MAX UNIT

INPUT CHARACTERISTICS
SYMBOL

PARAMETER

TEST CONDITIONS

VIH

Logical "1" Input Voltage

Referred to VSS

3

VIL

Logical "0" Input Voltage

Referred to VSS

V

IILK

Input Leakage Current

Pins 27-34

±0.1

CIN

Input Capacitance

Pins 27-34

5

IILK(ON/OFF)

ON/OFF Input Leakage

All Devices

±0.1

CINtON/OFF.l

ON/OFF Input Capacitance

All Devices

200

1.5

V

±1

IlA

±1

IlA

pF
pF

AC CHARACTERISTICS - MULTIPLEXED INPUT CONFIGURATION
twH
tos

1

IlS

Data Setup Time

Digit Select Active Pulse Width

500

ns

tOH

Data Hold Time

200

ns

IIOS

Inter-Digit Select Time

2

IlS

200

ns

AC CHARACTERISTICS - MICROPROCESSOR INTERFACE
Other Chip Select either held active,
or both driven together

twL

Chip Select Active Pulse Width

tos

Data Setup Time

100

tOH

Data Hold Time

10

tiCS

Int,!r-Chip Select Time

2

ns
0

ns
Ils

NOTES: 1. This limit refers to that of the package and will not be realized during normal operation.
2. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any input terminal to a voltage
in exeessof Voo or VSS may cause destructive device latch-up. For this reason, it is recommended that inputs from external
SQurces operating on a different power supply be applied only after the device's own power supply has been established, and that
on multiple supply systems the supply to the ICM7235 be turned on first.
3. This value refers to the display outputs only.

INPUT DEFINITIONS
In this table, Voo and Vss are considered to be normal operating input logic levels. Actual input low and high levels are
specified under Operating Characteristics. For lowest power consumption, input signals should swing to either VDO or VSS.
INPUT
BO

TERMINAL
27

TEST CONDITIONS

FUNCTION

Voo = Logical One
VSS = Logical Zero

Ones (Least Significant)

28

Voo = Logical One
VSS = Logical Zero

Twos

B2

29

Voo - Logical One
VSS = Logical Zero

Fours

B3

30

VOO = Logical One
VSS = Logical Zero

Eights (Most Signijicant)

Bl

5

ON/OFF

Data Input Bits

Voo = OFF,
Vss=ON

Display ON/OFF Input

ICM7235, ICM7235A MULTIPLEXED-BINARY INPUT CONFIGURATION
INPUT

TERMINAL

01

31

02

32

03

33

04

34

TEST CONDITIONS

FUNCTION
01 Digit Select (Least Significant)

VOO = Active
VSS = Inactive

02 Digit Select
03 Digit Select
04 Digit Select (Most Significant)

8-42
Note: All typical values have been guaranteed by characterization .and are not tested.

ICM7235
ICM7235M, ICM7235AM MICROPROCESSOR INTERFACE INPUT CONFIGURATION
INPUT

DESCRIPTION

TERMINAL

DAI

Digit ADDRESS
Bit 1 (LSB)

31

DA2

Digit ADDRESS
Bit 2 (MSB)

32

CS1

Chip Select 1

33

(;S2

Chip Select 2

34

TEST CONDITIONS

FUNCTION
DA2 & DA 1 serve as a two bit Digit Address Input
DA2, DA 1 = 00 selects D4
DA2, DAI = 01 selects D3
DA2, DA 1 = 10 selects D2
DA2, DA 1 = 11 selects Dl

VOO = Logical One
Vss = Logical Zero

When both CSI and CS2 are taken to VSS the data at
the. Data and Digit Address inputs are written into the
input latches. On the rising edge of either Chip Select, the
data is decoded and written into the output latches.

Voo = Inactive
VSS = Active

OPEN·DRAIN HIGH·VOLTAGE P-CHANNEL TRANSISTOR OUTPUTS

\

10-3QY ~---""~----If'35\\~~~~flm
-=-=ICM7235

DEP~~ING
ON

+

+

UY

VDD

_

DISPLAY

_Vss
36

PHOSPHOR·COATED
/.,

ANODES

[~~hrG1-_+~-_f~-_-+~c-_+~:....._-t_':'~-_-1L..r~-_f~'-~7'2~""i<_"h/~'~~==L~~:~gE
DC FILAMENT
DISPLAY

r+

III

F

l<

;!:2.5~
DEPENDING ON
DISPLAY
LD012601

Figure 4: ICM7235 Typical DC Vacuum Fluorescent Display Connection
VACUUM FLUORESCENT DISPLAYS (4 DIGIT) AVAILABLE FROM:
N.E.G. Electronics, Inc.
Models FIP4F8S and FIP5F8S

CIRCUIT DESCRIPTION

Input Configurations and Output Codes

Each device in the ICM7235 family provides signals for
directly driving the anode terminals of a four-digit, 7segment non;multiplexed vacuum fluorescent display. The
outputs are taken from the drains of high-voltage, lowleakage P-channel FETs. Each is capable of withstanding
> -35V with respect to VOO. In addition, the inclusion of an
ON/OFF input allows the user to disable all segments by
connecting pin 5 to Voo; this same input may also be used
as a brightness control by applying a signal swinging
between Voo and VSS and varying its duty cycle.

The standard devices in thelCM7235 family accept a
four-bit true binary (i.e., positive 'level = logical one) input at
pins 27 through 30, least significant bit at pin 27 ascending
to the most significant bit at pin 30. The ICM7235 and
ICM7235M decode this binary input into a 7-segment
alphanumeric hexadecimal output, while the ICM7235A and
ICM7235AM decode the binary input into the same 7segment output as the ICM7218 "Code B," i.e., 0~9, dash,
E, H, L, P, blank. These codes are shown explicitly in Table
1. Either decoder option will correctly decode true BCD to a
7-segment decimal output.

The ICM7235 may also be used to drive nonmultiplexed
common cathode LED displays by connecting each segment output to its corresponding display input, and tying the
common cathode to VSS. Using a power supply of 5V and
an LED with a forward drop of 1.7V results in an "ON"
segment current of about 3mA, enough to provide sufficient
brightness for displays ,of up to 0.3" character height.

These devices are actually mask-programmable to provide any 16 'combinations of the 7-segment outputs decoded from the four input bits. For larger quantity orders,
(10K pcs. minimum) custom decoder options can be
arranged. Contact your Intersil Sales Office for details.
The ICM7235 and ICM7235A devices are intended to
accept multiplexed binary or BCD output. These devices
provide four separate Digit select lines (least significant digit
at pin 31 ascendingta most significant digit at pin 34). Each
Digit Select line when taken to a positive level decodes and
stores in its respective output latches the character corresponding to the data at the input port, pins 27 through 30.

Note that these devices have two Voo terminals, and
each should be connected to thE! positive supply voltage.
This double connection is necessary to minimize the effects
of bond wire resistance, which could be a problem due to
.
the high display currents.
8-43

Note: All typical values have been guaranteed by characterization and are not tested.

= .CM7235

...&'II

~

The ICM7235M and 7235AM devices are intended to
accept data from a data bus. under processor control.
In these devices,the four data input bits and the2-bit
Digit Select code (OAl pin 31, OA2 pin 32) are written into
input buffer latches when both Chip Select inputs (CSfpin
33, CS2 pin 34) are taken to VSS. On the rising edge of
either Chip Select input, the content of the data input
latches is decoded and stored'in the output latches of the
digit selected by the contents of the select code latches. A
select code of 00 writes into 04, 01 writes into 03,10 writes
into 02 and 11 writes into 01. The timing relationships for
inputting data are shown in Figure 7, and the chip select
pulse widths and data setup and hold times are specified
under Operating Characteristics.

~~~-'~--------------------------~-

",,' .I=:L:.~
.:

VAOUo~

,

'

~DON'fCAFIE.
WF019,931,

Figure 6: Multiplexed Input Timing Diagram

•v

...

~

.ml~·
DATA AND " ' " " ' ' ' ' " " " " "

,.:~~

tow

ItIS
VALID

.

,

YAUD

r
VDO SEGMENTS OfF
Vss '" SEGMEN!S ON

~DOH'TCARE

v ..

WF020031

v "
DlGITICHIP

SElECT
INPUTS

I"
:13

\

Figure 7: Microprocessor Interface Input
Timing Diagram

Veo MICROPROCESSOR
YER~ONS

32

Vss MUL TlPLEliED VERSIONS

3t

TABLE 1: Output Codes
voo

..

BINARY

2'
TC02941t

Figure 5: Test Circuit

TYPICAL PERFORMANCE
CHARACTERISTICS
- to

-

-

-

-

•
J
II,

=,v

VSupp

=,.5

vJPP 1sv
VS~

! tV
'-4-f

. vsJPP

--

.... ~

",

f-"

-~

~

1/

L

JIll

•

'~r
~

CI /

i-- ~

~

B1

BO

0
0
0
0
0

0
0

0
0

0

0

1

0

0

0

1

0
0

1

1

0
0

1
0
0
1
1
0
0
1
1
0
0
1
1

1
1
1
1
1
1

~r
VSUPP

B2

.1

Voo - VOUT

- 12

B3

2

1

1

0

0
1
' 1

1
1

HEXADECIMAL CODE B
ICM7235A
ICM7235
ICM7235M
ICM7235AM

a

a

1

1
2
3

1
2
3

0

4

4

1

0

5
6
7
8

5
6
7
8

1
0

9
A

-

1

0
1

9

1

b

E

0

C

1

d
E
F

H
L

0
1

P
(BLANK)

....
•IOu,
•

•
LC02030t

Figure' 8: Segment Assignment

•

OP04401I

8-44
Note: All typical values, have been guaranteed by characterization and are not tested.

ICM7243
8-Character LED
IlP-Compatible Display Driver
GENERAL DESCRIPTION

FEATURES

The ICM7243 is an a-character alphanumeric display
driver and controller which provides all the circuitry required
to interface a microprocessor or digital system to a 14- or
16-segment display. It is primarily intended for use in
microprocessor systems, where it minimizes hardware and
software overhead. Incorporated on-chip are a 64-character
ASCII decoder, a x 6 memory, high power character and
segment drivers, and the multiplex scan circuitry.
Six-bit ASCII data to be displayed is written into the
memory directly from the microprocessor data bus. Data
location depends upon the selection of either Serial
(MODE = 1) or Random (MODE = 0). In the Serial Access
mode the first entry is stored in the lowest location and
displayed in the' 'left-most" character position. Each subsequent entry is automatically stored in the next higher
location and displayed to the immediate "right" of the
previous entry. A DISPlay FULL signal is provided after a
entries; this signal can be used for cascading. A CLeaR pin
is provided to clear the memory and reset the location
counter. The Random Access mode allows the processor
to select the memory address and display digit for each
input word.
The character multiplex scan runs whenever data is not
being entered. It scans the memory and CHARacter drivers,
and ensures that the decoding from memory to display is
done in the proper sequence. Intercharacter blanking is
provided to avoid display ghosting.

.14- and 16-Segment Fonts With Decimal Point
• Mask Programmable For Other Font-Sets Up to
64 Characters
• Microprocessor Compatible
• Directly Drives Small Common Cathode Displays
• Cascadable Without Additional Hardware
• Standby Feature Turns Display Off; Puts Chip in
Low Power Mode
• Serial Entry or Random Entry of Data Into
Display
.
• Single + 5V Operation
• Character and Segment Drivers, All MUX Scan
Circuitry, 8 x 6 Static Memory and 64-Character
ASCII Font Generator Included On-Chip

ORDERING INFORMATION
PART
NUMBER

TEMPERATURE
RANGE

PACKAGE

ICM7243AIJL

-20·C to +85·C

CERDIP

ICM7243BIJL

-20·C to + 85·C

CERDIP

ICM7243B EV/KIT
ICM7243BIPL

-20·C to +85·C

-

ICM7243B/D
ICM7243BCPL

CHAR.

o·C

PLASTIC
DICE

to +70·C

PLASTIC

-""==...r"
CD0261U

CD026011

Figure 1: Pin Configurations

8-45
Note: All typical values have been guaranteed by characterization. and are not tested.

-002

.U~U[l

:(II ICM7243
" ,

&'ABSOLUTE MAXIMUM RATINGS

'!:!

"

Operating Temperature Range (I) ....... -25°C to +85°C
(C) ..... ; ....... O°C to 70°C
Storage Temperature Range ............ : -55°C to + 125°C
Lead Temperature (Solder.ing, 10sec) ...... ; .......... 300°C

Supply Voltage (Voo - VSS) .................................. 6V
CHARacter Output Current ..............................300mA
SEGment Output Current ......................... : ....... 30mA
Input,Voltage (Any Terminal) (Voo+ O.3V) to (VSS-O.3V)
Power Dissipation ....•....•.................................... 1W

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are-stress ratings only and-functional
operation of the device at these or any otller condnions above those indicated in the operational sections of the specifications is not implied. Exposllre to
absolute maximum rating conditions for extended periods may affect device reliability.

SEGMENT
DRIVERS

4-

SEGMENT OUTPUTS
SEC.
-

CHAn..
CHARACTER OUTPUTS

I

I
AoISEN _ _

11

SEL

SEL

• ICM72UA HAS ONLV ONE CSAND
NO CS.ICM72'3B HAS 15 SEGMENTS
ADDRESS
MULTIPLEXER
AND
DECODER

,,'OISP FULL 4---+

INTER·CHARACTER BLANKING

80010801

Figure 2: Functional Diagram

DC ELECTRICAL CHARACTERISTICS

(Voo = 5V, Vss = OV, TA = 25°C unless otherwise stated)
LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
MIN
4.75

Vsupp

Supply Voltage (Voo - VSS)

100

Operating Supply Current

~Supp

VSUPP - 5.25V, OSC/~ Pin

ISTBY

Quiescent Supply Current

VIH

Input High Voltage

VIL

Input Low Voltage

liN

Input Current

ICHAR

CHARacter Drive Current

ICHLK

CHARacter Leakage Current

ISEG

SEGment Drive Current

- 5.25V, 10 Segments ON, All 8 Characters

< 0.5V,

TYP

MAX

5.0

5.25

180

CS = Vss

30

250

2

140

0.8

V

+10

p.A

190

mA
100

VSUPP = 5V, VOUT = 2.5V

8-46
Note: All typical values have been guaranteed by characterization and are not tested. -

14

p.A
V

-10
VSUPP = 5V, VOUT = 1V

V
mA

19

/lA
mA

ICM7243
DC ELECTRICAL CHARACTERISTICS (CO NT.)
PARAMETER

SYMBOL
ISlK

SEGment Leakage Current

VOL

DISPlay FULL Output Low

IOl = 1.6mA

VOH

DISPlay FULL Output High

IIH

Ids

Display Scan Rate

= 5V.

MIN

TYP

MAX

0.01

= 100/J.A

UNIT

10

/J.A

0.4

V
V

2.4

Hz

400

AC ELECTRICAL CHARACTERISTICS
VOD

LIMITS

TEST CONDITIONS

(Drive levels O.4V and 2.4V. timing measured at O.8V and 2.0V.

T A = 25°C unless otherwise stated).

SYMBOL

TEST CONDITIONS

PARAMETER

TYP

MIN

\wPI

WR. CLeaR Pulse Width Low

250

\wPH
tOH

WR, CLeaR Pulse Width High (Note 1)

250

Data Hold Time

0

-100

tos

Data Setup Time

250

150

tAH

Address Hold Time

125

tAS

Address Setup Time

40

tes

CS, ~ Setup Time

0

tT

Pulse Transition Time

!sEN

SEN Setup Time

0

-25

tWOF

Display Full Delay

600

480

MAX

UNIT

ns
15
100

CAPACITANCE
SYMBOL
CIN

TEST

MIN

TYP

Input Capacitance (Note 2)

Output Capacitance (Note 2)
Co
"Not tested. (Guaranteed)
NOTES: 1. In Serial mode WR high must be ::: TSEN + TWOF.
2. For design reference only, not 100% tested.

MAX

UNIT

5

pF

5

pF

TYPICAL PERFORMANCE CHARACTERISTICS
SEGment Current

VB

Output Voltage

30

,

CHARacter Current

I

1

r--

--

1

.~5.0V

I

~.5V

10

.~.

o

Output Voltage

500

VDD·6.5V

20

VB

I
I

P

100

o

SEGment Voltage (V)

If'!'.

voo·

5.~~_

"':.- ~Y

.' •.5Y-

3

2
CHARacter Voltage (V)
OP04651I

OP04641J

6-47
Note: All typical values have been guaranteed by characterization and are not tested.

.D~DIl

ICM7243
ICM7243A/B DISPLAY FONT AND SEGMENT ASSIGNMENTS
Note: Some display manufacturers use different designations for some of the segments. Check' data sheets carefully.

" "

'f;S ~
•

b

~~J
I

J

C

d

d2

d1

DISPLAY

o
0..0.

0
1
1

0

C? RB

C]]

EF GH IJ I-
1 0 12 3Y S.5 l8 g
I

0

0

o
o

0

0

1

1

1

0

1

0

D, 0

0

0. 0
D, 0

Do 0

o

0

0

1

1

1

0

0

1

1

0

0

~

/

,?

L

/

1 '1

1

1

1

o

0

o

0

1

o

0

1

1

1

0

1

0

1

0

1

1

1

1

1

1

1

1

o

0

1

1

1

0

1

_ _ _ tJpJ
SEGMENT LEOs

VIS
08022411

Figure 5: Segment and Character
Drivers Output Circuit

TBOO11QI

Figure 3: ICM7243A 16-Segment
Character Font with Decimal Point

ca _ _"1

•
,r~
g,

~

b

.~ ~c
d

0

0.. 0.'

0
1
1

oc? R B C]] EF GH ItJ I-< LM N 0
lP Q R 5T U VW Xy Z ~ \ ~ 7'
0

1
":±! CJJ~ .& 1 <>
12 3Y S.5 l8 g

*+

10
0, 0 0

0

0

0

0

0

0

1

1

1

0, 0

0

0

0

1

1

1

1

0

0

0

0, 0

0

1

1

0

0

1

1

0

0

1

0, 0

1

0

1

0

1

0

1

0

1

0

/

-

./

L-

~?

1

1

1

1

1

0

1

1

1

1

1

0

0

1

1

1

0

1

0

1

/

TBOO1201

WF020511

Figure 6: Random Access Timing

NOTE: Segments a and d appear as 2 segments each, but both
halves are driven together.

Figure 4: ICM7243B 14-Segment
Character Font with Decimal Point

8-48

Note: All typical values have been guaranteed by characterization and are not tested.

ICM7243
WR

SEN

DISPLAY FULL

~-------------------Figure 7: Serial Access Mode Timing (Mode

=1)

WF03011I

TABLE 1: PIN DESCRIPTIONS, ICM7243A(B)
SIGNAL

PIN

FUNCTION

00- 0 5

10-15
(8-13)

Six-Bit ASCII Data input pins (active high).

CS, CS

16
(14-16)

Chip Select for decoding from I'P address bus, etc.

WR

17

WRite pulse ine!!!..Pin (active low). For an active high write pulse, CS can
be used, and WR can be used as C§.

MODE

31

Selects data entry MODE. High selects Serial Access (SA) mode where
first entry Is displayed in "leftmost" character and subsequent entries
appear to the "right". Low selects the Random Access (RA) mode
where data is displayed on the character addressed via Ao - A2 Address
pins.

AO/SEN

30

In RA mode it is the LSB of the character Address. In SA mode it is used
for cascading display driver/ cI:mtroliers for displays of more than 8
characters (active high enables driver controller).

A1/a:eaFi

29

In RA mode this is the second bit of the address. In SA mode, a low input
will CLeaR the Serial Address Counter, the Data Memory and the display.

A2/DISPlay FULL

28

In RA mode this is the MSB of the Address. In SA mode, the output goes
high after eight entries, indicating DISPlay FULL.

OSC/5FF

27

OSCillator input pin. Adding capacitance to VOO will lower the internal
oscillator frequency. An external oscillator is also applied to this pin. A low
puts the display controller/driver into a quiescent mode, shutting OFF the
display and oscillator but retaining data stored in memory.

SEG a - SEG m, D.P.
CHARacter 1 - 8

2-9 (7),
32-40

SEGment driver outputs.

18-21,
23-26

CHARacter driver outputs.

8-49
Note: All typical values have been guaranteed by characterization and are not tested.

17
SEGMENTS

~'---Fil-m-llJ-llJ-llJ-FlI-FlI-FlI
CHAR 1

2

3

5

6

7

8

8 CHARACTERS'

SEGMENTS

__-=----"-"'-"-'---+-_---''---- DISPLAY FULL OUTPUT

o--voo
y:>-~ HC (FOR SA MODE)

TC02291I

Figure 8: Test Circuit
edge of WR (or its equivalent). Subsequent changes on the
Address lines will not affect device, operation. This allows
use of a multiplexed 6-bit bus controlling both address and
data, with timing controlled by WR.

DETAILED DESCRIPTION
WR, cs; CS. These pins are immediately functionally
ANDed, so all actions described as occurring on an edge of
WR, with CS and CS enabled, will occur on the equivalent
(last) enabling or (first) disabling edge of any of these
inputs. The delays from CS pins are slightly (about 5ns)
greater than from WR or
due to the additional inverter
required on the former.

Serial Access Mode. If the internal latch is set for Serial
Access (SA), (MODE latched high). the Serial ENable input
on SEN will be latched on the falling edge of WR (or its
equivalent). The CLR input is asynchronous. and will force·
clear the Serial Address Counter to address 000 (CHARacter 1). and set all Data Memory contents to 100000 (blank)
at any time. The DISPlay FULL output is always active in SA
mode also, and indicates the overflow status of the Serial
Address Counter. If this output is low, and SEN is (latched
as) high, the contents of the Counter will be used to
establish the Data Memory location for the Data input. The
Counter is then incremented on the rising edge of WR. If
SEN is low, or DISPlay FULL is high. no action will occur.

es

MODE. The MODE pin input is latched on the falling edge
of WR (or its equivalent. see above). The location in Data
Memory where incoming data will be placed is determined
either from the Address pins or the Serial Address Counter.
under control of this latch. which also controls the function
of AO/SEN, A1/CLR, and A2/DISPIay FULL.
'
Random AccesS Mode. When the internal mode latch is
set for Random Access (RA) (MODE latched low), the
Address input on AO. A1 and A2 will be latched by the falling
8-50

Note: All typical values have been guaranteed by" characterization and are not tested.

.U~Ulb
This allows easy "daisy-chaining" of display drivers for
multiple character displays in a Serial Access mode.
Changing Modes. Care must be exercised in any application involving changing from one mode to another. The
change will occur only on a falling edge of' WR (or its
equivalent). When changing mode from Serial Access to
Random Access, note that A2/DISPlay FULL will be an
output until WR has fallen low, and an Address drive here
could cause a conflict. When changing from Random
Access to Serial Access, A1/CLR should be high to avoid
inadvertent clearing of the Data Memory and Serial Address
Counter. DISPlay FULL will become active immediately
after the falling edge of WR.
Data Entry. The input Data is latched on the rising edge
of WR (or its equivalent) and then stored in the Data
Memory location determined as described above. The six
Data bits can be multiplexed with the Address information
on the same lines in Random Access mode. Timing is
controlled by the WR input.
OSC/OFF. The device includes a one-pin relaxation
oscillator with an internal capacitor and a nominal frequency
of 200kHz. By adding external capacitance to VDD at the
OSC/OFF pin, this frequency can be reduced as far as
desired. Alternatively, an external signal can be injected on
this pin. The oscillator (or external) frequency is pre-divided
by 64, and then further divided by 8 in the Multiplex Counter,
to drive the CHARacter strobe lines (see Display Output),
An intercharacter' blanking signal is derived from the predivider. An additional comparator on the OSC/OFF input

detects a level lower than the relaxation oscillator's range,
and blanks the ,display, disables the DISPlay FULL output (if
active), and clears the pre-divider and Mutliplex Counter.
This puts th,e circuit in a low-power-dissipation mode in
which all outputs are effectively open circuits, except for
parasitic diodes to the supply lines. Thus a display connected to the output may be driven by another circuit (including
another ICM7243) without driver conflicts.
Display Output, The address output of the Multiplex
Counter is multiplexed into the address input of the Data
Memory, except during WR operations (in Serial Access
mode, with SEN high and DISPlay FULL, low), to control
display operations. The address decoder also drives the
CHARacter outputs, except during the inter-character
blanking interval (nominally about 5f.1s). Each CHARacter
output lasts nominally about 300f.ls, and is repeated nominally every 2.5ms, i.e., at a 400Hz rate (times are based on
internal oscillator without external capacitor).
The 6 bits read from the Data Memory are decoded in the
ROM to the 17 (15 for ICM7243B) segment signals, which
drive the SEGment outputs. Both CHARacter and SEGment
outputs are disabled during WR operations (with SEN high
and, DISPlay FULL Low 'for Serial Access mode). The
outputs may also be disabled by pulling OSC/OFF low.
The decode pattern from 6 bits to 17 (15) segments is
done by a ROM pattern according to the ASCII font shown.
Custom decode patterns can be arranged, within these
limitations, by consultation with the factory.

APPLICATIONS
8 CHARACTER lED DISPLAY

*',-,:::I_
'LI:

T~-JI:
I
,_

•

1

CLR

CHAR
SEG
DlSP FULL

+5V_ SEN
+5V_ MODE

r--- WR

r~-5

DATA
BUS

-",.

...

T/\ \JITEF~5TI
.J..l
I
.J..L

.

"

8

-

LClR

-

CHAR
SEG
DlSPFULL

SEN
+5V_ MODE

VOS?,

r--- WR

r~-5

CS

I

.

•

CS. (WR)
FIRST 8 CHARACTERS

SECOND 8 CHARACTERS
'17

rr--

CHAR
SEa
DlSPFULL

1-----

+5
VDO i+-+ 5V
VOS?,

'.

'6

6

8 CHARACTER LED DISPLAY

-

VDO _+5V
CS

8 CHARACTER LED DISPLAY

VDO
CS

+5V

Vos

-------- .111 8 CHARACTERS

'or 'CM72.3A. 15 lor ICM72<13B
AF032111

Figure 9: Multicharacter Display using Serial Access Mode

8-51
Note: All typical values have been guaranteed by characterization and are not tested.

a....

!:
"

.D~UIl.

ilCM7243

...~

APPLICATIONS (CONT.)

--+

RBR8H~~~

RRI

c::::l

RBR7H.....~~

ETC.

1M8403
UART

RB R,-e......,,.;;-;;,;;.;...;;;..;;.;;.._..,
DR

DRR

+sv
OUT

ICL7565
DELAY

ETC.

200pF

AF032201

Figure 10: Driving Two Rows of Characters from a Serial Input.
UART converts data stream to parallel bytes. Bit 7 of each word sets which row data will be entered
into. Bit 8 will blank and reset whole display if low. Each MODE pin should be tied high. ICM7243A
can also be used, with inverter on RSR7 for one· row.

COMP.ONENT SELECTION

Texas Instruments Inc., Dallas, Texas (214) 995-6611
(part # HDSP6508)

Displays suitable for use with the ICM7243 may be
obtained from the following manufacturers; among others:
Hewlett Packard Components, Palo Alto, California (415)
857-6620 (part #HDSP6508, HDSP6300)
General Instruments Inc., Palo Alto, California (415) 4930400 (part #MAN2815)

A.N.D., Burlingame, California (415) 347-9916 (part
#AND370R)
lEE Inc., Van Nuys, California (213) 787-0311 (part
#LR3784R)

8-52
Note: All typical values have been guaranteed by characterization ·and are not tested.

.U~UlL

ICM7243

wwwmmmmmmmoooommmoowwmmmmmmoomm~moom~

I

1CM7243AIII
CS Ai AI Ao Ow

I'zI
Pz1

IMIOC35
IMIOC4I

... ~

I
1

.t:.

I

ICM7243AIII
i
AI
Ow WR

Viii Cs Ai
I I

r~

i.o

4i!.

1

I

::..

ICM7243AIII
i
CS Ai AI Ao Ow WR

1

I

ICM7243A/lJ
CS Ai AI Ao Ds-o Wii

~~1

;4i!.

I

i.e;' ';::..

'*7
Dee

D8w

8-BlTBUS

WR

I
AF03231I

Figure 11: Random Access 32-Character Display in IM80C48 system.
One port line controls A2. other two are CS lines. 8-bit data bus drives 6 data and 2 address lines.
MODE should be GrouNDed on each part.

+5V

I
I

+5V

+5V

+5V

+5V

I

I

1.4 AMP PEAK

I
I
I

1k

I
I
1000

1000 :

I

I

ICM7243

:300II
I
I

I
I

(l00mA PEAK)

1k

':" GND
05022601

05022501

(Sa.) Common Cathode Displays
(5b.) Common Anode Displays
Figure 12: Driving Large Displays.
The circuits of Figures 12a and 12b can be used to drive 0.5" or larger alphanumeric displays, either common cathode (12a) or common anode (12b).

8-53
Note: All typical values have been guaranteed by characterization and are not tested.

i....

..,
t

IICM7·280

.... Dot Matrix LCD
~ ControllerIRow Driver
.GENERAL DESCRIPTION

FEATURES

The ICM72BO is designed to provide a complete microprocessor interface for an BO-character alphanumeric LCD
.display system. It includes a character generator, c!isplay
voltage generator and resistor string, row drivers, an9
control circuitry. Interface to a host microprocessor is
achieved through either a multiplexed or non-multiplexed
parallel bus.
The ICM72BO is designed to offload all display-related
tasks from the host microprocessor and to provide an easyto-program software interface. Since the internal circuitry
operates at full microprocessor speeds, there is no waiting
for completion of internal operations. Testing ofa "Busy"
flag, when characters or commands are written, is not
required.
Character data can be loaded with an auto-incremented
CUrsor or in a random-access mode. Versatile control
functions allow all or selected portions of the display to be
underlined, blinked, blanked, or displayed in reverse video.
Display start offset and power-down features are provided,
and both an underline and a blinking-box cursor are
available.
The ICM7280 can display four user-defined characters in
addition to the standard 96 ASCII upper and lower-case
characters and 14 European and graphics characters.

•
•
•
•
•
•

80 Character Wide Display Memory
- Directly Drives 10 ICM7281 Column Drivers
High Speed iJP Intertace
.
-ICM7280A: Intel, Zllog Compatible
-ICM7280B: Motorola, Rockwell Compatible
120 Character Font With Multiple Attributes
- Underline, Cursor, Blinking, Reverse
4 User Definable Characters
Versatile Character Font Matrix
- 5 or 6 Columns By 7 to 10 Rows
High Speed Internal Architecture
- No Busy Flag Needed

APPLICATIONS
•
•
•
•

Battery Hand-Held Terminals
Portable Computers
Instrument Control Panels
LCD Display Modules

ORDERING INFORMATION
PART
NUMBER
ICM7280AIPL
ICM7280AIJL
ICM7280AlD
ICM7280BIPL
ICM7280BIJL
ICM72809/D

TEMPERATURE
RANGE
-40°C to +85°C
-40°C to + 85°C

-40°C to +85°C
-40°C to +85°C

-

. PACKAGE
40-Pin Plastic DIP
40-Pin CEADIP
DIE
40-Pin Plastic DIP
40-Pin CEADIP
DIE

CD033801

PART
#
7280A
72809

PIN
29
AD
E

PIN
30
WA

PIN
31
ALE

A/W

AS

Figure 1: Pin Configuration

8-54
Note: All typical values have been guaranteed by characterization and are not tested.

301689-004

ICM7280
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range ........... -40 oe to +85°e
Storage Temperature Range ............ -ssoe to + 125°e
Lead Temperature (Soldering, 10sec) ................. 300 oe

Supply Voltage (VDD - VSS) ............................ +6.5V
Display Voltage (VDD - VDISP) ......................... + 12V
Input Voltage ........................ VSs-O.SV to VDD+O.5V
Power Dissipation ............................. SOOmW @ 70 0 e

Note: Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute. maximum rating conditions for extended periods may affect device reliability.

ANNUNCIATOR
RAM

2

1

'I'
/

/7

1/8

I

I .......

AD·AI

4x10x 5

SERCLK

FONT
RAM

I---

80 CHARACTER
RAM

DATA OUT
SERIAL
INTERFACE

120.10.5

00·117

FONT
ROM

I~

AD

I::
1/
,

r

INTERFACE

ATTRIBUTE
INFO & TIMING

CONTROL
REGISTERS

Wii

t

&
CONTROL LOGIC

DISPLAY
CONTROL

~

cs

'/

DATA LATCH

r-----

ALE

pP

~

~

•

I,
1""'-

osc

•
•

DISPLAY
VOLTAGE
GENERATION
ROM & TIMING

CLOCK

LCD
ROW
OUTPUTS

~

,

80015511

Figure 2: Functional Diagram

ELECTRICAL CHARACTERISTICS
'AC CHARACTERISTICS
(VDD = S.OV±10%, TA = -40 to +8soe, VDISP = VDD
SYMBOL
IlL

PARAMETER

-8V, VSS

= OV,

unless otherwise specified.)

TEST CONDITIONS

Input Leakage

Address/Data pins high impedance
0< VIN < Voo

MIN
-10

TYP

MAX

UNIT

+10

I1A

ISS

Supply Current

Osc open ckt,' VIL = OV, VIH = VDO

2.5

mA

ISlBY

Shutdown Current

VIL = OV, VIH = VDO

100

IJA

VSUPP,

Operating Voltage Range

lose

Osc. Frequency

Osc., open ckt.

4.5

5.5

V

0.2

l:b

MHz

1.0

V

Serial Outputs
VOL

Output Voltage, Low

IOL = lmA

,8-55
Note: All typical values have been guaranteed by characterization and are not tested.

i ICM7280·
....
a
(II

ELECTRICAL CHARACTERISTICS (CONT.)
SYMBOL

PARAMETER

Data 110, p.P Interlace Inputs

MIN

TEST CONDITIONS

Output Voltag~. High

.VOH

TYP

MAX

UNIT

V

Voo-l.0

;IOH=.lmA
.

. u

VOL

Output Voltage, Low

IOL = 1.6mA

VOH

Output Voltage, High

IOH =400j.iA

VIL

Input Voltage, Low

VIH

Input Voltage, High

0.4

V
V

2.4

V

0.8

V

3.0

Row Driver Outputs

RON

Output Resistance, ON

DCONT high, Vo = VOISP + 0.5V
DCONT low, Vo = -0.5V

ROFF

Output Resistahce, OFF

DCONT high, Vo = V4±.5V
DCONT low, liD = Vl±0.5V

VI

DCONT high

V2, V3
V4

.

DOONT low

1

kSl

2.5

kSl

-1.5

-1.0

0.5

V

0.5

1.0

1.0

V

2.5

3.0

3.5

V

AC CHARACTERISTICS (See Timing Diagram)
(VDD ... 5.0V± 10%, VDISP = OV, VSS = OV, TA =; -40 to
.. SYMBOL

PARAMETER

+ a5·C,

CL

= 1~OpF.

TEST CONDITIONS

unless otherwise specified.)
MIN

TYP

MAX

UNIT

200

ns

400

ns

Serial Output Timing
Prop.D~lay SCLK to
DLAT
Prop Delay SCLK to
Tscdo
DOUT
Microprocessor Interface

Tscdl

TLL

ALE! AS Pulse Width.
High

55

ns

TAL

Address to ALE Setup
time

30

ns

Tla

Address to ALE Hold
Time

30

ns

IntellZllog Option (ICM7280A)

Tad

Address Setup Time

50

ns

Tah

Address Hold Time

30

ns

Twi

WRITE Pulse Width,
Low

100

ns

Tdw

Data to WRITE Setup·
Time

··150

ns

30

ns

Twd

Data to WRITE Hold
. Time

Trd

READ to Valid Data

Trx

READ to Data Hold
. Time

TBsd

ALE Setup Time

550

ns

150

ns

60.

ns

ns

MotoroI8/R~e" Option (lCM7280B)

Tad

Address to E· Setup
Time

50

Tah

Address to E Hold
TIme

30

Note: All typical val\l8s have been guaranteed by characterization and· are not tested.

!

ns

n
.u~nlL !I

ICM7280

....

N

AC CHARACTERISTICS (See Timing Diagram) (CONT.)
SYMBOL

PARAMETER

TEST CONDITIONS

Q)

MIN

TYP

MAX

UNIT

Tee

E Pulse Width, High

200

ns

Tdw

Data to E Setup Time

100

ns

TWd

Data to E Hold Time

30

Trd

E to Valid Data

Trx

E to Data Hold Time

Tasd

E to AS Setup Time

WRITE CYCLE TIMING (RD

Tee = 400ns
60

ns
550

ns

'150

ns
ns

= 1")
II

00-D7, AO-A6

WF031501

READ CYCLE TIMING (WR = "1")

WF031601

Figure 3: ICM7280A Timing Diagrams (Multiplexed Operation)

8-57
Note: All typical values have been guaranteed by characterization and· are not tested.

0

:1...°ICM7280:
2,

S:!

WRITE CYCLE, TIMING (RD

='~1") (ALE = "1")

ADDRESS VALID

AO-A6

DO-D7

I.--~--Tad----+l'

,.--~--

WF031301

READ CYCLE TIMING (WR = "1")

cs.

AO-A6

DO-D7

WF031401

, Figure 4: ICM7280A Timing Diagrams (Non-Multiplexed Operation)

8-58
Note: All typical values have been guaranteed by characterization and are not, tested.

ICM7280
WRITE CYCLE TIMING (AS = "1")

WF03170!

READ CYCLE TIMING (AS = "1")

WF031801

Figure 5: ICM7280B Timing Diagrams (Non-Multiplexed Operation)

8-59
Note: All typical values have been guaranteed by characterization and are not tested.

.iICM1'280
':&\1
:...,
,Iii

.!

WRITE CYCLE TIMING

WF031001

READ CYCLE TIMING

AS

DO-D7. AO-A6

E

~--+-~~-+---------Tqc----------------------~

RiW.
WF031101

Figure 6: ICM7280B Timing Diagrams (Multiplexed Operation)

Note: All typical values have been guaranteed by characterization and are not tested.

ICM7280
J

SelK

T.....

j

~

i . - - T.....

~

'-1

DLAT

/

~

J

DOUT

~t
WF029801

Figure 7: ICM7280 Serial Output Timing Diagram

Microprocessor Bus Interface

Table 1: Pin Descriptions
SIGNAL

ROW10-1

PIN

DESCRIPTION

1-10
11

Serial data

12

Negative LCD supply voltage

°OUT
VOISP
V2, V3

13, 14

OCONT

15

Column driver control output

SCLK

16

Serial data clock output

OLAT

17

Row data latch output

VINV

18

Negative voltage generator
clock

OSC

19

Oscillator input

VSS
00-07

20
28-21

LCD column voltage

Digital ground

To use the ICM7280 on a multiplexed bus, tie the AO-A6
lines to the DO-06 lines and ALE/AS driven with the system
address latch enable or strobe signal. For a non-multiplexed
bus, AO-A6 should be connected to the least significant
address lines, 00-07 connected to the data bus and ALE/
AS tied high. The only external circuitry needed is a chip
select or address decoder. The ICM7280 uses an address
space of 128 bytes.

Data 1/0

ICM7281 Data Interface

Address inputs

The ICM7280 Row Drivers require ICM7281 Column
Drivers to operate an LCD display. Three lines are used to
load data serially into the ICM7281 column drivers, DOUT,
SCLK, and DLAT. The data is latched and shifted with each
negative going edge of SCLK, and the data is transferred
from the ICM7281 shift register to its latches with the
negative going edge of DLAT. The frequency of the SCLK is
set by the oscillator frequency of the ICM7280 and is
normally about 600kHz.

Positive digital and LCD supply
voltage

Oscillator

RO(7280A)
E(7280B)

29
29

Read input
Enable input

WR(7280A)
R/WFi(7280B)

30
30

Write input
Read/w.rite input

ALE(7280A)
AS(7280B)

31
31

Address latch enable
.Address strobe

32

Chip select input

~

AD-AS
VOO

39-33
40

There are two versions of the ICM7280. The ICM7280A
has WR and RD pins, as well as ALE and CS. This version
can be interfaced to standard multiplexed or non-multiplexed data buses of parts such as the 8085, Z80, 8088 and
other microprocessors. The ICM7280B has R/W, E and AS
pins instead of WR and RD and ALE. The ICM7280B is
intended for use on 6800 and 6500 family buses.

LCD row drivers

The ICM7280 oscillator will free run at 600kHz in die
form, when not loaded with any capacitance. With 15pF of
external capacitance at pin 19, the frequency will be about
250kHz. Figure 8 shows the relationship between oscillator
period and the value of Cexternal. Table 1 shows the
relationship between the oscillator frequency and various
display system Signals and features. Standard CMOS logic
gates can be used. to overdrive the oscillator to control
frequency. A suitable frequency can also be derived by
dividing down the host processor's clock.

DETAILED DESCRIPTION

Hardware Interface
Figure 1 is a simplified block diagram of the ICM7280. It is
a dedicated hardware IC and the speed of data entry and
command processing is limited only by gate delays. Unlike
other display controliers, the ICM7280 will not "go busy" for
milliseconds at a time while processing data or commands.

8-61
Note: All typical values have been guaranteed by characterization and are not tested.

iICM'7280··
C\I
1&

Table 2: ICM7280 Display System Frequencies

2

SIGNAL NAME

COMMENTS

FREQUENCY

SCLK

OSC

Sets data transfer rate to ICM7281 column drivers

DLAT
Display Control

OSC/M
OSC/M

Once per row multiples period.

LCD Multiplex Freq.

OSC/(NxMx2)

Should be above 30Hz to avoid flicker.

Blink Rate

OSC/(NxMx64)

Blink rate for blinking cursor and blinking characters

VINV

OSC

AC waveform for generating a negative voltage for VDISP

Where N = number of rows - 7, 8, 9, or 10.
M = 80 x number of columns (5 or 6) per character. Add 14 if annunciators enabled.

NOTES:

Table 3: ICM7280 Memory Map
ADDRESS
FUNCTION
DECIMAL

HEX

0-79

00H-4FH

Character RAM. Loaded with ASCII data characters to be
displayed. Address 0 is the leftmost character (assuming the
Preset Display Position Register is 0.)

80-119

50H-77H

Font RAM. Holds bit pattern for ,four user-definable characters. See
Table 4.

120

78H

Instruction register 0 (lRO)

121

79H

Instruction register 1 (IR1)

122

7AH

Instruction register 2 (IR2)

123

7BH

Cursor Register (IR3)

124

7CH,

Preset Display Position Register (IR4)

125

7DH

Annunciator Register 1 (AR1)

126

7EH

Annunciator Register 2 (AR2)

127

7FH

Cursor-Addressed Entry Register

NOTE: See Table 6 for more detail about addresses 120-127 (78H-7FH).

Display Interface

TI....

The ICM7280 will support a dot matrix LCD display which
has 7,8,9, or 10 rows, and either evenly-spaced columns
or a space after every fifth column. If the display has evenlyspaced columns, then 6 columns per characte~ should be
selected and the sixth column is always blank. If the display
provides a blank after every fifth column, then 5 columns
per character should be selected .. The character font is
automatically changed to take advantage of all rows. The
ICM7280 will automatically use one of the 6 evenly-spaced
columns for a' space.

.....

"

./
,/

1./

/

1/

'"

V

The ICM7280 can drive LCD displays with threshold
voltages up to 2.5 volts. There is no minimum display
threshold voltage since VDISP can be above VSS'

'"
"

20

"

..

S8

--

The ICM7280 also has 10 onboard row drivers deSigped
to handle large dot ml:!trix displays. These drivers provide
fast slew rates, and have a minimum offset voltage.

6U

c....,..IIpFI
0P057401

Figure 8: The Relationship Between
.Oscillator Period and Cexternal.

8-62
Note: All typical values have been guaranteed by characterization and are not tested.

ICM72QO
Vall (+5V)

i

UllV
,4

R3
150K

4.111

!

TAiT

100"A

0.1,4

411
Vall
-I,

H2

1.5M

R,
10011

b(

ICM7280
+5V

Ibsp

11.,4

TO

ICM7281

4

-=

R4
1011

COLUMI
ORIVliR

-=
VIIV

1011

18

1bsP'f'~2

________________________________________

~

20

L0012501

Figure 9: ICM7280 VOISP Temperature Compensation Circuit

Display Voltage Generator

ators or flags, 40 bytes for storing 4 user-programmable
characters, 5 bytes for control registers, and one dummy
address to identify cursor-addressed character entry.

The ICM7280 not only has an onboard resistor string to
generate the required V" V2, V3, and V4, but also has an
output that assists in generating a negative voltage for
VDISP. The VINV pin is a loW-impedance output that swings
from VDD to VSS at the oscillator frequency. The circuit of
Figure 9 connected to the VINV pin generates a temperature-compensated VDlSP. Diodes 0, and 02, with capacitors C, and C2 form a charge-pump negative voltage
generator. The ICl7611 CMOS op-amp and its associated
circuitry form an adjustable temperature compensated voltage source that provides VDISP to the ICM7280, as well as
the ICM7281 column drivers. Temperature compensation
for VDISP is necessary because the threshold voltage of
LCD fluids have a pronounced negative tempco.

Character RAM
Data may be entered in a random-access mode by simply
writing to the desired character address. Address 0 corresponds to the leftmost character of the display, and address
79 corresponds to the rightmost character (assuming the
Preset Display Position register has been loaded with a 0).
Block moves or other high-speed data transfers can be
used to move data from the host system's RAM or ROM to
the ICM7280's character RAM. Character data format is
standard ASCII for the 96 upper and lower case characters,
with the eighth data bit ignored. As shown in Figure 10, the
ICM7280 Character Font Table, the display controller also
recognizes three special control characters and 14 additional European and graphics characters. The characters 08
through .17 are alternate lower case characters that are
used with 8, 9, and 10 row displays.

SOFTWARE INTERFACE
Table 3 provides a memory map of the ICM7280. The
ICM7280 uses 128 bytes of memory space: 80 bytes for
character data storage, 2 bytes for 14 independent annunci-

8-63

Note: All typical values have been guaranteed by characterization and are not tested.

8

~ ICM7'280··

.O~OIL

~ ~-~~--'----~
:Ii

g

III1I1III1IIIII1
III11IIIII1IIIII
III1IIIIIIIIIIII
III1IIIII11I1III
IIIIIIIII11I1III
IIIIIIIIIIIIIII1
III11I1II111IIII .
III1IIIIII1IIIII
M •• U

UM

wn

"K

n.

U.

M.

~

un

DU

NU

nu

au

"K

uw

UU

»w

~

Ra

an

an

~ft

~u

un

UK

UR

~ft

uu

n

uu

nK

MR

••• a

UM

.H

UX

••

hK

au

A

~U

.~

.N

ron

nu

nu

nu

uu

n~

n~n~

n~

H

au

AM

M"

ny

M"

~N.

UY

nM

§.

~~

n~

un

M~

§

.. 13

•

14

1,110 15

101"

102 17

104 lit

105 &A

108 &I

107 IC

'08 80

101 IE

110 I5f

111

"$ 74

116 15

117 11

"1

120 7.

121 lA

122 71

123 7C

124 70

125 7E

'" 7f

127

U

.m

nu

ftN

AM

M ••••

d

u"

nn

uu

HM

au

nu

a

an

un

un

UN

an

»

un

UU

Mn

hM

~

M~

.u

HU

M

.n

hR

110

II 11

97 12

71

112 71

.
111 7t

114 13

n

103.

I

n

119 71

HEX DECIMAL

KEY
TBOO2201

Figure 10:ICM7280 Character Font

8--64

.

Note: All typical values have been guaranteed by characterization and are not tested.

ICM7280
Table 4: Font RAM for User-Definable Characters
ROW

ASCII CHARACTER 0
FONT ADDRESS

ASCII CHARACTER 1
FONT ADDRESS

ASCII CHARACTER 2
FONT ADDRESS

ASCII CHARACTER 3
FONT ADDRESS

Decimal

Hex

Decimal

Hex

Decimal

Hex

Decimal

Hex

80

50H

90

5AH

100

64H

110

-

-

-

-

-

-

6EH
-

-

106

6AH

116

6DH

-

Row 1 (top row)

-

-

-

-

Row 10 (bottom row)

-

-

86

56H

96

-

-

-

89

59H

-

-

-

-

-

Row 7

-

-

-

99

-

-

-

60H
63H

Font RAM

-

109

-

-

-

-

119

74H

-

77H

Table 5: ASCII Character 0 Example

In addition to the 120 characters available in the built-in
character ROM, 4 characters may be user-defined. Table 4
shows the mapping between the Font RAM and the userdefined character font. An example of an additional character is provided in Figure 11. Note that addresses 80-119
(50H-77H) hold 5 bit words that correspond to the bit
pattern of the four user-definable characters, such that
each 5 bit word defines the pattern for one row of the
character. The LSB corresponds to the right-hand dot. Each
character uses 10 words, with the lowest address representing the top row. Once defined, these characters are
treated the same as the predefined characters from the
Font ROM. Enter ASCII data 0, 1, 2, or 3 into Character
RAM to call up one of those characters.

Row
1
2
3
4
5
6
7
8
9
10

Font Address
Decimal
Hex
80
81
82
83
84
85
86
87
88
89

50H
51H
52H
53H
54H
55H
56H
57H
58H
59H

Data
Decimal
Hex
5
14
21
14
21
14
21
4

4
14

05H
OEH
15H
OEH
15H
OEH
15H
04H
04H
OEH

The starting point of the display can be offset by
changing the value stored inlR4, the Preset Display
Position Register, at address 124 (7CH). The number in this
register (usually 0) specifies the address of the character in
character RAM that will appear at the leftmost position on
the display. For example, a 5 in this register causes the sixth
character in the RAM to be displayed at the left end of the
display. The Preset Display Position Register can be loaded
with a value, or it can be incremented and decremented by
writing to bits 2 and 3 of IR2, address 122 (7 AH). The Preset
Display Position Register will automatically wrap around
from 79 to 0 when incremented, and wrap around from 0 to
79 when decremented past O.

I

TB002111

Figure 11: An Example of a User-Defined
Character

CAUTION: If a number greater than 79 is loaded into the
Preset Display Position Register, display multiplexing stops.
The LCD can be damaged if left in this condition for an
extended period of time.

Instruction and Annunciator Registers
Table 5 details the bit assignments of the control
registers. All registers are write-only registers.

The Cursor Register determines the location of the cursor
on the display, depending upon value in the Preset Display
Position Register. If for example, the Cursor Register is set
to 5 and the Preset Display Register is set to 0, the cursor
will then be displayed in the 6th character of the display. If,
however, the Cursor Register is set to 14 and the Preset
Display Position Register is also set to 14, then the cursor
will be displayed in the leftmost character position. If data is
written to address 127 (7FH), the data is entered at the
current location of the cursor and the cursor position is
incremented. The cursor position may be directly set by
writing to Cursor Register address 123 (7BH). The cursor

Attributes are enabled by bit 5 of Instruction Register IR2,
at address 122 (7AH). Blinking, underlined, and reverse
video characters are controlled by attribute characters in
the character RAM. These attribute characters are displayed as blanks, but signal the ICM7280 that the characters to the right of the attribute character are to be displayed
with one of the three attributes (5 = underline, 6 = reverse
video, and 7 = blinking). Each attribute is cancelled by a
second occurence of the attribute character. The entire
display can be blinked or blanked by setting the appropriate
bits in IRO.
8-65

Note: All typical values have been guaranteed by characterization and are not tested.

I .1'CM,7280
...

~

may also be incremented or decremented by writing the
appropriate instructions to IR2 at address 122 (7AH). The
cursor location will wrap around from ,79 to 0 or vice versa
when incremented or decremented. A number greater than
79 written to the Cursor Register causes no cursor to be
displayed, but the ICM7280 will otherwise function normally.
If bit 4 of IR1 at address 121 (79H) is at "1", then all
characters to the right of the cursor are blanked but the
data in the character RAM is retained.
The IRO r.egister is a bit set/reset register. The MSB
selects either set (1) or reset (0) operation. A "1" in any
other bit position selects that bit to be set! reset. For
example, a bit pattern of 10011001 will set bits 0,3 and 4,
while a bit pattern of 00010000 will clear bit 4. Unselected
bits are not affected.
The Annunciator Registers are bit set!reset registers that
operate similarly to IRO. When used with the ICM7281
column drivers, bit 0 of Annunciator Register 1 will be the
last bit shifted out, and will appear at the column 1 output of
the ICM7281. Bit 6 of Annunciator Register 2 is the first
annunciator bit to be shifted out, andwill appear on column
14 of the ICM7281. The annunciator outputs, if enabled,
appear on all rows in columns 1-14. Annunciators are
enabled by bit 7 at IR1.
Bit 6 of instruction register 2 resets all instruction
registers and annunciator registers, as well as the Cursor
Register and Preset Display Position Register. Bit 6 of
Instruction Register 2 also resets and stops the display
multiplex and blink counters.
All register bits except bit 6 of IR2 are reset upon powerup. Since bit 6 of IR2 is indeterminate at power-up, and the
instruction registers cannot be written to while bit 6 is set,
the initialization routine should first clear bit 6 before the
other registers of the ICM7280 display controller, are
accessed. When normal operation resumes after bit 6 of
IR2 is cleared, the attributes will be off, the cursor will be
present at 0, and the 5 x 7 character format will be engaged.

CAUTION: The ICM7280 should not be left in the reset
mode for extended periods, because in this condition there
is a DC bias on .the liquid crystal display which can
permanently damage it.

80 CHARACTER· LIQUID CRYSTAL
DISPLAYSYSTEM

a

Figure 10 shows
complete 80 character IntellZilog
compatible display system without annunciators. The
ICM7280A receives ASCII character data from the hOlilt
microprocessor, converts it to a serial data stream for the
ICM7281 column drivers, and provides the row drive
voltages and overall display system timing and control. The
power consumption of this display system is typically 6
milliwatts during normal operation and 5 microwatts when
shutdown (but retaining data and control setup).
If less than 80 characters are desired, the ICM7281, s that
would normally drive the right-hand characters of the
display may be left out. This means that an 80 character
display module and a module with fewer characters can
have exactly the same hardware and software interface,
except that extra ICM7281's are miSSing from the module
with fewer characters.
The Preset Display Position Register is most useful when
the LCD system has fewer than 80 characters. For example, if.the display has only 16 characters, all 80 characters
stored in RAM can be displayed by first setting the Preset
.Display Position Register to 0, waiting 2 seconds, setting it
to 16, waiting 2 seconds, and so forth, on up through a
character preset of 64. The host processor would need to
do just one write of the data and then use one command to
write to the Preset Display Position Register. This requires
much less time than shifting all pf the data around byte by
byte. Another use of the preset display feature is to
implement a character-by-character scroll. Each time the
Preset Display Position Register is incremented by one, the
displayed characters will shift left one character position.

Note: All typical values have been guaranteed by characterization and are not tested.

ICM7280

ICM
7280

ROW
DRIVE
RI-l0

1-

MICROPROCESSOR
TO

ALE
7

8

~o

AO-6
10
00-7
RD

SClK

WR

DOUT
DATA
lATCH
DISPLAY
CONTROL
V2

Cs"

V3

+5

LCD DISPLAY
7-10 ROWS, UP TO 480 COLUMNS

10

Vee

V01SP

ClK

r---

---

ClK

DATA IN COl ~ DATA IN COL
40
DATA
DATA
40
lATCH
lATCH
DISPLAY
DISPLAY
CONTROL
CONTROL
V2
V2
V3
VOISP

Vss

ICM7281
#1

Jr

r--

V3
V01SP
ICM7281
#2

••••

1---1---1---1---1---1---1---••••

10
ClK
DATA IN
DATA
lATCH
DISPLAY
CONTROL
V2
V3
VDlSP
ICM7281
#12

1
V01SP
GENERATOR

LC0Q4401

Figure 12: SO-Character LCD Display System

8-67

Note: All typical values have been guaranteed by characterization and are not tested_

Table 6: Instruction and Annunciator Registers
120 Decimal
78 Hex
07
06
05
04
03
02
01
DO
121 Decimal
79 Hex
07
06
05
04
03
02
01. DO

Instruction Register 0
IRO
1 = SET 0 = RESET
1 = Blank Display
1 = Blink Display
1 = Cursor' Enabled
1 = Power Down Mode
unassigned, set to 0
SET to 0
o = Normal Operation, 1 = Test Mode
Instruction Register 1
IRI
' 1 = Enable Annunciators
1 = Blinking Box Cursor 0 = Underline Cursor
1 = Blank characters to the right of the cursor
1 = 6 columns per character 0 = 5 columns per character
1 = All on test mode. All dots and annunciators turned on.
unassigned, set to 0
Controls number of rows per character, according to the following table:
01 Do Character Size

-

0
0
1
1
122 Decimal
7A Hex
07
06
05
04
03,02

Instruction Register 2
IR2
Production test mode only. Must be set to O.
1 = Resets all registers. See test on previous page.
1 = Enable Attributes
unassigned, set to 0
Preset Display Position Increment/Decrement
03 02 Control Bit Designators

-

01, DO

0 7 Rows/ character
' 1 . BRows/character
0 9 Rows/character
1 10 Rows/character

0
0
1
1
See
01'

o
1
o

No operation
Decrement Preset Display Position Register
Increment Prei;let Display Position Register
1 Increment Preset Display Position Register
the following table:
Do Control Bit Designators

-0
0
1
1

0
1
0
1

No operation
Decrement Cursor Register
Increment Cursor Register
Increment Cursor Register

123 Decimal
Cursor Register
78 Hex
IR3
This register specifies the address of the cursor using a 7 bit value in the range of 0-79 decimal, 0-4F hexadecimal. The location of
the cursor on the display is determined by both the Cursor Register and the Preset Display Position Register. The eighth bit is
ignored.
124 Decimal
7C Hex

Preset Display Position Register
IR4

The Preset Display Position Register is normally set to O. If set in the range of 0 to 79, the character at that address appears in the
leftmost location on the display.
125 Decimal
Annunciator Register 1
70 Hex
AR1
126 Decimal
Annunciator Register 2
7E Hex
AR2
The 7 LSBs of each annunciator register (00-06) each control one annunciator. To set, write a 1 to the MSB and a 1 to the bits to
be set. To clear, write a 0 to the MSB and a 1 to the bits to be cleared. The annunciators will appear left to right AR1 :00 to 06 then
AR2:DO to 06.
127 Decimal
Cursor-Addressed Entry
7F Hex
When character data is written to this address, the data is loaded into the character RAM using the Cursor Register as a pointer
and the Cursor Register is incremented.

8-68
Note: All typical values have been guaranteed by characterization and are not tested.

ICM7281
40-Column LCD Dot Matrix
Display Driver
GENERAL DESCRIPTION

FEATURES

The ICM7281 LCD Dot Matrix Column Driver is designed
to convert a serial data stream into drive signals for a
multiplexed dot matrix LCD. Easily cascadable, up to 16
ICM7281's can be driven by one ICM7280 Intelligent Row
Driver to make an 80 character dot matrix display.. The
ICM7281 also serves as both a Row Driver and Column
Driver in LCD dot matrix graphics displays. The low output
resistance and the 15V drive capability make it well suited
for graphics displays with up to 256 x 256 dots (with 1OpF /
dot capacitance).
The ICM7281 consists of a 40 bit shift register, a 40 bit
latch and 40 level-shifters/drivers. The 4 display drive
voltages are generated externally, usually by a Row Driver.
A serial data interface is used to minimize the number of
pins needed for digital interfacing. A data Carry Output is
·included for cascading several ICM7281's to drive large
LCD displays.

•
•

ORDERING INFORMATION

•

PART
NUMBER

TEMPERATURE
RANGE

ICM72811PL
ICM72811JL
ICM7281/D

-40°C to + 85°C

•
•
•

40 High Voltage LCD Column Drive Outputs
Easy Interface
- Serial Input Shift Register with Parallel Latch
and Carry Outputs
Directly Compatible with ICM7280 Row Driver
- Up to 16 ICM7281's can be Driven by an
ICM7280 with No External Components
Low Resistance Outputs
- Can Drive Both Columns and Rows of LCD
Graphics Displays
Will Drive 1.5V Threshold LCDs with Only Single
5V Supply
- Can Drive Up to 4.5V Threshold LCDs with
15V VOISP

APPLICATIONS
•

PACKAGE

•

40:Pin PLASTIC DIP

•

Column Drivers For Dot Matrix Alphanumeric
Displays Using ICM7280 Row Driver
Rowand Column Drivers For LCD Dot Matrix
Graphics Displays
Segment Driver For LCD Bargraphs and
Annunciators
Serial Input I/O Expander

40-Pin CERDIP
DICE

40 DtSPLAY CONTROL

......- - ••• - - - i

1-+-- ••• ----ef

COLUMN 40

CARRY OUTPUT

DATA INPUT S

36 CARRY OUTPUT

COWIIN30

1 - - -••• ----ef

I - - - ••• - - - i
I - - - ••• - - - f
I - - - ••• - - - f
DiSPLAY
CONTROL
COL 40
80015311

CD03351!

Figure 1: Functional Diagram

8-69
Note: All typical values have been guaranteed by characterization and are not tested.

Figure 2: Pin Configuration
(Outline dwg. PL)
-002

,..
":1.... ICM7281

~

ABSOLUTE MAXIMUM RATINGS

Supply Voltage (Voo - VSS) .................................. 6V
Display Voltage (Voo - VOISP) ............................. 18V
V2, V3· .. ···· ... ···· ... ··· .... ·.· ..... ·· ..... · ....... VOISP to VOO
Input Voltage (Note 1) .... ~.(VSS -O.3V) to (Voo +O.3V)

Power Dissipation (Note 2) ................. O.3W @ + 85·C
Operating Temperature Range ........... -40·C to +85·C
Storage Temperature Range ..... ,' ...... ...,65·C to +150·C
Lead Temperature (Soldering, 10sec) ........ ~ ........ 300·C

Stresses above those listed under" Absolute Maximum R'aiings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods ,may affect device reliability.
NOTE 1: Due to the SCR structure inherent in any junction isolated CMOS device, connecting an input to any voltage greater than Voo or less ihan VSS may
cause destructive device latch-up. If the input voltage can exceed the recommended range, the input should be limited to less than 1mA to avoid
latch-up.
NOTE 2: This limit refers to that of the packag,e and will not occur during normal operation.

ELECTRICAL CHARACTERISTICS, (Voo = 5V,
VSS =OV, TA = -40'C to
SYMBOL

+85·C.

VOISP = -10V, V2 = 1/3 (VOO - VOISP). V3

=2/3

(VOO - VOISP),

Unless otherwise specified.)

PARAMETER

TEST CONDITIONS

MIN

TYP
5.0

MAX

UNIT

SUPPLY CHARACTERISTICS

VSUPP

Operating Supply Range

4.5

VOISP

Display Voltage

-10

ISTBY

Supply Current
Quiescent
Dynamic

100

V
V

.'

.1
500

FCLK = 0
FCLK = 500kHz

5.5
VOO
"

10
1000

IJ.A

INPUT CHARACTERISTICS

VIH

Logic 1 Input Range

DATA INPUT, DATA LATCH,
CLOCK and DISPLAY CONTROL

VIL

Logic 0 Input Voltage

DATA INPUT, DATA LATCH,
CLOCK and DISPLAY CONTROL

liN

Input Current

DATA INPUT, DATA LATCH,
CLOCK and OISPLAY CONTROL
0< VIN :~6L
t---"V2
Va t - - -..... Va

+S

DATAIN COL
DATA
40
LATCH
DISPLAY
CONTROL

V2

VOISP . ......,.-. . V01SP

VOO
Vss

ICM7281
•1

ICM7281

.2

••••

ICM7281
.12

VDISP
GENERATOR

80015201

Figure 5: Alphanumeric LCD Display System

6-72
Note: All typical values have been guaranteed by characterization and are not tested.

ICM7281
VooROW/COL

DISPLAY VOLTAGES ROW
24140

SUPPLY

64 x 64 DOT
LCD DISPLAY

DISPLAY VOLTAGES ROW
SUPPLY
ROWDc;.~~TROrL_ _ _ _ __
24140

40

VOISP ROW/COL
ICM7281

1 LATCH
1 DATA IN
1
DISPLAY CONTROL

GRAPHICS

DATA INPUT

CHIP

DC~----~~~~~~~~ CONTROLLER

DATA

DL~____~__~D~A~T~A~L~A~T~C~H~-t
CLOCK
CLOCK

DISPLAY
VOLTAGES
COLUMN

1'2
DISPLAY SUPPLY
VOLTAGES
COLUMN
LD012411

Figure 6: ICM7281 Column Driver. Used in a Graphics Application

C,

R~2K~

-COLI

I
V2
V3

>
>

L---- COL 1 DATA

0
R - 2000

0

•
•

A

1'....---+--1

·C

R

VOISP>

0
R - 200U

Voo>

TRUTH TABLE
COLUMN DATA
o
1

DISPLAY
CONTROL

0

~ 2K~ N
I

L---

B

r----~

I
I
I

-COL "N" DATA

•
•

>- ___ ...1

•
~40

R - 2KO

DISPLAY
CONTROL 0 t-~-+"":::::'-I

_ COL "N"

I
I

•

COL 40

L---- COL 40 DATA
AF03791I

Figure 7: Column Output Multiplexer and Truth Table

8-73
Note: All typical values have been guaranteed by characterization and are not tested.

i....

~

·ICM7281
applied RMS voltage gets longer as the display temperature
drops. At very low temperatures some displays may take
several seconds to change to a new character after the new
information appears at the LCD driver outputs. However, for
most applications above O·C this will not be a'problem, and
for low temperature applications, high-speed liquid crystal
materials are available. High temperature operation is
generally limited by long term degradation of the polarizer
and the sealing materials above + 70·C or + 85·C.

LCD MULTIPLEXING
Multiplexing Schemes
The goal in LCD multiplexing is to increase the number of
segments a given number of column lines can drive, while
not unacceptably degrading the viewability of' the LCD
display. Increasing.the number of rows driven by a column
decreases the ratio between the voltage across an ON
segment and the voltage across an OFF segment. This
ON/OFF voltage ratio is critical since the contrast of an
LCD segment is determined by the RMS voltage across that
segment. Figure 8 shows a typical curve of contrast vs.
RMS voltage. For an acceptable display, the RMS OFF
voltage must be below the 10% con~rast point and the RMS
ON voltage must be above the 50·/0 contrast point. The
RMS on voltages for different multiplex ratios are also
shown in Figure 8. Note that as the number of rows or
backplanes goes up, the RMS ON voltage decreases.
The ICM7281 can drive either columns or rows using the
modified Alt and Pleshko waveforms as shown in Figure 9.
The ON/OFF voltage ratio formula and the calculated
values for common multiplex ratios are shown in Table 1.
Table II shows the optimum voltages for V1 to V5 for
different multiplex ratios.

The temperature effect most important in the 0-70·C
range is the variation of threshold voltage with temperature.
For typical liquid crystal materials, the threshold voltage,
VTHRESH, has temperature coefficient of - 7 to -14mV I·C.
Since the VOISP is 3.27 times VTHRESH (for 7 row multiplex,
see Table 1), the VOiSP has a tempco of about -25 to
-50mV I·C, depending on LCD fluid tempeo. As can be
seen in Figure 8, for optimum viewability and contrast ratio,
the driving voltage must be accurately matched to the LCD
threshold voltage. If a Significant variation in temperature is
expected, a method of adjusting the VOISP must be
provided. Figure 10 is a typical Temperature Compensation
circuit USing an ICL7660 negative voltage converter to give
the required VOISP' range, .if necessary.
With the fluids now available for 32 and 64 multiplex
operation it is quite common to have a "Contrast" adjustment accessible to the user. This "Contrast" adjustment
varies the VDISP to compensate for both temperature
variations and for variations in the viewing angle.

Temperature Effects and Temperature
Compensation of VOISP
The performance of LCD fluids is affected by temperature
in two ways. The response time of the display to changes in

100

~

80

8

80

V

N

w

=5

V

= 4.10

= 2.75

~

5w

40

Ifl.

20

N=7 V =2.53

CONTRAST VERSUS VOLTAGE

ac

0t=~~~

__L-~__~-7,,-~~~-L~
4.0
6.0
DRIVE VOLTAGE VRMS
SC011401

Figure 8: C()ntrast Versus RMS D.rive Voltage

&-74

Note: All typical values have been guaranteed by characterization' and are noltested.

ICM7281

Table 1: Optimum Multiplex Drive
ROWS

VON/OFF

4
7
8
9
10
12
14
16
32
64

1.73
1.488
1.447
1.414
1.387
1.346
1.315
1.290
1.196
1.134

I

ICM7280/ICM7281
VOO - V DISPLAY /VT

ALT AND PLESHKO
VOO-V DISPLAY/VT

4
4.74
4.97
5.20
5.41
5.81
6.18
6.532
8.817
12.01
TabIe 2:

optlmum
.

3
3.27
3.37
3.46
3.56
3.74
3.917
4.08
5.19
6.804

D'
I
rive Votages

N

Vl

V2

V3

V4

"5

ON/OFF
VOLTAGE
RATIO

4
5
6
7
8
9
10
11
12
16
20
24
30
32
40
48
54
64

1.000
0.951
0.919
0.897
0.879
0.866
0.855
0.846
0.838
0.816
0.802
0.793
0.782
0.779
0.771
0.764
0.761
0.756

2.000
1.902
1.838
1.793
1.759
1.732
1.710
1.692
1.677
1.633
1.605
1.585
1.564
1.559
1.541
1.529
1.522
1.512

1.000
1.176
1,332
1.476
1.608
1.732
1.849
1.960
2.066
2.449
2.786
3.090
3.502
3.629
4.103
4.332
4.830
5.292

2.000
2.127
2.252
2.372
2.488
2.598
2.704
2.806
2.904
3.266
3.589
3.883
4.284
4.409
4.874
5.296
5.590
6.047

3.000
3.Q78
3.171
3.269
3.367
3.464
3.559
3.652
3.743
4.082
4.3!;l1
4.676
5.066
5.188
5.645
6.061
6.351
6.803

1.732
1.618
1.543
1.488
1.447
1.414
1.387
1.365
1.346
1.291
1.255
1.23
1.203
1.196
1.173
1.156
1.147
1.134

8-75
Note: All typical values have been guaranteed by characterization and are not tested.

.O~D(L

MODIFIED ALT & PLESHKO

T01 T11T21Tal T41TSlTelT11T21Tal
VSV4 ROW2

I

ROW

~::I

~~

3x5DISPLAY

1 2 3 4 5

V,-

COLUMN
TBOO1301

Vo-

WITH

VO=O

VSV4-

V1 =V(3
V2= 2V(3
V3=Va- V (3
V4=Va

VaCOL2 V2-

V,-

VO-

V5
VS. V4-

= VOl SPLAY = Va+ V (3
.~

v'KTI

2(K-1)

2

COL3 V2-

V, VO-

VTH = THRESHOLD VOLTAGE OF LCD

V",-

4
AF038001

Figure 9: ICM7281 Display Multiplexing Scheme

8'-76
Note: All typical values have been guaranteed by characterization and are not tested.

.U~UlL c;
~

ICM7281

..
~

N

IX)

VOISP ADJUST
Voo

10,.F

R3
lOOK

Kv

0.1,.

-I,
100K
VDISP

IN914

ASSUMING

R4

R,
R3 = Ai!
DS02S101

Figure 10: Temperature Compensated VOISP Generator

Multiplex Rate and Maximum Drive
.
Capability

than ~ OOOpF capaCitance per 40 columns (each ICM7281
drives 40 columns).

The minimum multiplex rate is determined by the response time of the LCD. To avoid flicker, the multiplex rate
should be above 30Hz. The maximum multiplex rate is
determined by power dissipation limits and the drive capability of the ICM7281.

POWER DISSIPATION
The power dissipation of a display system driven by the
ICM7281 has several components:
1) Quiescent or DC power dissipation of the ICM7281
2) Dynamic or AC power dissipation of the ICM7281
3) .. Power ,consumed in driving the LCD display.

The drive capability of the ICM728f indirectly sets the
upper limit of the multiplex rate. The absolute maximum limit
of DC voltage across an LCD is usually specified as 50mV.
As the multiplex rate increases, any asymmetry in the rise
and fall times will cause a DC offset, in addition to any offset
caused by V2 and V3 not being exactly symmetrical with
respect to VDISP and VDD. The ICM7281 was designed to
have equal rise and fall times, as well as low resistance
drivers which make the rise and fall times short. This allows
the ICM7281 to drive over 2000pF at multiplex rate of
100Hz. Normally an LCD dot matrix display will have less

ICM7281 Power Dissipation
The quiescent current of the ICM7281 is very low,
typically less than 1/lA, and can generally be ignored. The
dynamic current is proportional to the clock frequency, with
a .typical value of 1.0mA per MHz. This means that at a
500kHz clock the dynamic current will be 0.5mA.

LCD Display Drive Dissipation
Since the LCD has very low leakage currents, most of the
power used to drive the LCD is used to charge and
discharge the LCD capacitance. The power is
6-77

Note: All typical values have been guaranteed by characterization and are not tested.

used to generate the row and column data that is serially
transferred into the ICM7281's. (See Figure 6).
Thadisplay drive voltages are generated in a resistor
divider network. The optimum voltages for V1 through V5
can be calculated using the ,equations of Figure 9. Optimum
voltages for common multiplex ratios are shown in Table 2.
. The LCD shown in Figure 6 is a 32 row display, divided
Into two sections of 16 rows to increase the ON/OFF RMS
voltage ratio, thereby improving the contrast of the display.
As LCD fluids improve it will become practical to use 32 or
64 row multiplexing, reducing the number of column drivers
by a factor of 2 or 4.
As the number of rows increases, the VOISP required by
the ICM7281's modified Alt and Pleshko multiplex scheme
. increases less than the VOISP required by a classic Alt and
Pleshko multiplex scheme. For example: a 64 row display
with a 1.45V threshold would require +5V and -12.4V
supplies using standard Alt and Pleshko multiplexing. The
ICM7281 would require only +5V and -4.9V to drive this
same display with 64 row multiplexing. The negative voltage
could easily be generated using a charge pump such as the
ICL7660. (See Figure 10).

Where:
PLeo is the power dissipated in driving the display
C is the display capacitance
V is Voltage across the display
fEFF is the effective multiplex frequency
The effective multiplex frequency ranges from fMUX to
N x fMUX, where fMUX is the multiplex rate and' N is the
number of rows. The actual effective multiplex frequency Is
dependent on which characters or bit pattern is being
displayed and is typically about N/3 x fMUX

Low Power Shutdown
If the data clock is stopped and the voltages across the
LCD are not changing, the power consumption will drop to
the 5 to 50 microwatt range. Set VOISP, V2 and va equal to
VOO to prevent permanent damage to the LCD display by a
DC bias.

APPLICATIONS
Alphanumeric Display Using ICM7280
In~elligent Row Driver

Serial Input 1/0 Expander

The ICM7280 Intelligent Row Driver is specifically designed to drive multiple ICM7281 LCD Column Drivers.
Figure 5 shows a typical 80 character display. The ICM7280
and ICM7281's will drive either 7,8,9 or 10 row displays,
. with the characters having either 5 or 6 columns. The Row
Driver receives ASCII data, converts that data to bit-by-bit
column data for the ICM7281's and serially shifts data into
the ICM7281's. This process is repeated for each phase of
the multiplex cycle.
Temperature compensation and generation of VOISP for
the ICM7280/81 system is shown in Figure 10. For further
details refer to the ICM7280 Intelligent LCD Row Driver data
sheet.

In addition to driving LCD's, the ICM7281 can be used as
an 110 expander as shown in Figure 11. In this case, the
data can be serially entered into the IcM7281 shift register
using the 80C51 serial port. The 80C51 then transfers the
data to the output latch by pulSing the DATA LATCH input
with an I/O port line. Note that multiple ICM7281 's can be
cascaded to get more than 30 output lines. This cascading
does not require any additional logic since the ICM7281
CARRY OUTPUTs are used.
DISPLAY CONTROL is tied to VDD so that the data on
the column outputs is the same as the data that was
entered. If DISPLAY CONTROL is grounded, the column
outputs will be inverted data. with V3 grounded, the logic
lev~1 .at the column outputs will be CMOS compatible,
sWinging from ground to VDD. The output resistance of the
column outputs is about 2k ohms

LCD Graphics Display
In this circuit, ICM7281's are used to drive both the rows
and columns of the LCD dot matrix. An external controller is

P3.2

8051 P3.1

DL
P3.0

+5V

-r:

CLK

DATA
110.

I

I·

OR
8OC51

CARRY

ICM 7281

DC

1·.·30

COL

Va Va VDtSP

COL

,ru ....

DATA

+sv--r:

DL

CLK

CARRY

+sv-r:

ICM 7281

110.

COL
DC
Va VaVDtSp

DATA

COL

1···30

p ....

110.

DL

r

CLK

CARRY

TO
NEXT
ICM7281

r-

ICM 7281

DC
COL
COL
Va Va VDISP 1 • • • 30

,ru

....
8D014811

Figure 11: Ser,lal 1/0 Expander Using ICM7281

8--78

Nole: All typical values have been guaranteed by characterization and are not tested.

ICM7283
LCD Dot Matrix
Controller/Row Driver
GENERAL DESCRIPTION

FEATURES

The ICM7283 is designed to provide a complete microprocessor interface for an 2 line by 40-character alphanumeric LCD display system. It includes a character generator, display voltage generator and resistor string, row
drivers, and control circuitry. Interface to a host microprocessor is achieved through either a multiplexed or nonmultiplexed parallel bus.
The ICM7283 is designed to offload all display-related
tasks from the host microprocessor and to provide an easyto-program software interface. Since the internal circuitry
operates at full microprocessor speeds, there is no waiting
for completion of internal operations. Testing of a "Busy"
flag, when characters or commands are written, is not
required.
Character data can be loaded with an auto,incremented
cursor or in a random-access mode. Versatile control
functions allow all or selected portions of the display to be
underlined, blinked, blanked, or displayed in reverse video.
Power-down features are provided, and both an underline
and a blinking-box cursor are available.
The ICM7283 can display four user-defined characters in
addition to the standard 96 ASCII upper and lower-case
characters and 14 European and graphics characters.

•

•
•
•
•
•

Two Lines by 40 Characters Wide Display
Memory
- Directly Drives up to 6 ICM7281 Column
Drivers
High Speed /.IP Interface
- ICM7283A: Intel, Zilog Compatible
- ICM7283B: Motorola, Rockwell Compatible
120 Character Font With Multiple Attributes
- Underline, Cursor, Blinking, Reverse
4 User Definable Characters
Versatile Character Font Matrix
- 5 or 6 Columns By 8 Rows
High Speed Internal Architecture
- No Busy Flag Needed

APPLICATIONS
•
•
•
•

Battery Hand·Held Terminals
Portable Computers
Instrument Control Panels
LCD Display Modules

ORDERING INFORMATION
PART
NUMBER

TEMPERATURE
RANGE

ICM7283AIDM

-40°C to + 85°C

ICM7283A1D
ICM7283BIDM
ICM7283B/D

-40°C to + 85°C

-

PACKAGE
48-Pin Side Braze
Ceramic
DIE
48-Pin Side Braze
Ceramic
DIE

CD03491t

PART

PIN

PIN

'"

33

34

PIN

35

7283A

AD

WR

ALE

72838

E

R/W

AS

Figure 1: Pin Configuration

8-79
Note: All typical values have been guaranteed by characterization and are not tested.

301691-001

C')

...
=
a

.O~OIL

ICM7283

, ,.

'

ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range ........... -.40 o e to + 85°e
Storage Temperature Range ............ -55°e to + 125°e
Lead Temperature (Soldering, 10se6) ................. 300 o e

Supply Voltage (Voo - Vss) ............................ + 6.5V
Display Voltage (VOO - VOISP) ................••........ +12V
Input Voltage ........................ VSS-0.5V to Voo+0.5V
Power Dissipation ...... ; ..................... : 500mW @ 70 0 e

Note: Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other· conditions above those indicated· in the operational sections of the specifications is not implied.
Exposure to absolute maximum ratinfj conditions for' extended periods may· affect device reliability.

VA

>
>

ANNUNcIATIOR

RAIl

!

/7

4x 8x5
FONT
RAM

2 UNES 8Y

AD-A8

40 CHARACTERS

RAIl

1/8
/

12Ox8x5
FONT
ROM

OD·117
ALE

.p
RD

INTERFACE

t

i

CONTROL
REGISTERS

.

\Vii

SERIAL
INTERFACE

ATTRIBUTE
INFO .. TIMING

t

CONTROL LOGIC

~
~
~

J

DCONT

Cs

~
DISPLAY
VOLTAGE
GENERATION.
ROW TIMING

CLOCK

OSC

LCD
ROW
DRIVERS

~

VDISP

•
•
•

ADw.

0 UTPUTS

~
V

V
80016211

Figure 2: Functional Diagram

ELECTRICAL CHARACTERISTICS
AC CHARACTERISTICS
(Voo = 5.0V±10%, TA = -40 to +85°e, VOISP = Voo
SYMBOL

PARAMETER

-8V, VSS

= OV,

unless otherwise specified.)

TEST CONDITIONS
Address/Data pins high impedance
0< VIN < Voo

MIN
-10

TVP

MAX

UNIT

+10

p.A

IlL

Input Leakage

100 '

Supply Current

Osc open okt, VIL = OV, VIH = Voo

2.5

mA

ISTBY

Shutdown Current

VIL = OV, VIH = Voo

100

p.A

VSUPP

Operating Voltage Range

VIL = 0.4V, VIH

lose

Osc. Frequency

Pin 23 open okt.

= 2.4V

4.5

5.5

V

0.2

1.0

MHz

1.0

V

Serial Outputs
VOL

Output Voltage, Low

IOL = lmA

!HlO
.Note: All typical values have been guaranteed by characterization and are not tested.

ICM7283
ELECTRICAL CHARACTERISTICS (CONT.)
SYMBOL
VOH

PARAMETER

TEST CONDITIONS

Output Voltage, High

IOH

= 1mA

MIN

TYP

MAX

UNIT
V

VOO-1.0

Data I/O, /lP Interface Inputs
VOL

Output Voltage, Low

IOL = 1.6mA

VOH

Output Voltage, High

IOH

VIL

Input Voltage, Low

VIH

Input Voltage, High

0.4

= 400/lA

2.4

V
V

0.8
3.0

V
V

Row Driver Outputs
RON

Output Resistance, ON

DCONT high, Vo = VOISP + 0.5V
DCONT low, Vo = -0.5V

ROFF

Output Resistance, OFF

DCONT high, Vo = V4±·5V
DCONT low, Vo = V,±0.5V

V,

kS1

2.5

kS1

-1.0

DCONT high

V2, Va
V4

1

DCONT low

V

1.0

V

3.0

V

AC CHARACTERISTICS· (See Timing Diagram)
(VDD = S.OV± 10%, VDISP
SYMBOL

= OV,

TA

= -40°C

PARAMETER

to

+ 85°C,

CL = 150pF, unless otherwise specified.)

TEST CONDITIONS

MIN

TYP

MAX

UNIT

200

ns

400

ns

Serial Output Timing
Prop. Delay SCLK to
DLAT
Prop Delay ScLK to
Tscdo
DOUT
Microprocessor Interface
Tscdl

Tw

ALE I AS Pulse Width,
High

55

ns

Tal

Address to ALE Setup
time

30

ns

Tla

Address to ALE Hold
Time

30

ns

ns

IntellZIIog Option (ICM7280A)
Tad

Address Setup Time

50

Tah

Address Hold Time

30

ns

Twl

WRITE Pulse Width, Low

100

ns

Tdw

Data to WRITE Setup
Time

150

ns

TWd

Data to WRITE Hold
Time

30

ns

Trd

READ to Valid Data

Trx

READ to Data Hold
Time

.

ALE Setup Time
Tasd
Motorola/Rockwell Option (ICM7280B)

550

ns

150

ns

60

ns

50

ns

Tad

Address to E Setup
Time

Tah

Address to E Hold Time

30

ns

Tee

E Pulse Width, High

200

ns

8-81
Note: All typical values have been guaranteed by characterization and are not tested.

: ICM7283, .

...

'-.
(II

()

AC CHARACTERISTICS (See Timing Diagram) (CO NT.)
SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Tdw

Data to E Setup Time

150

ns

TWd

Data to E Hold Time

30

ns

Trd

E to Valid Data

Trx

E to Data Hold Time

Tasd

E to AS Setup Time

Tee = 400ns

60

550

ns

150

ns
ns

WRITE CYCLE TIMING (RD = "1")

WF030201

READ CYCLE TIMING (WR

="1")

WF03031I

Figure 3: ICM7283A Timing Diagrams (Multiplexed Operation)

8-82
Note: All typical values have been guaranteed by characterization and are not tested.

ICM7283
WRITE CYCLE TIMING (RD

="1") (ALE = "1")

READ CYCLE TIMING (WR

="1") (ALE = "1")

WF030401

AO-A6

00-07

WF030501

Figure 4: ICM7283A Timing Diagrams (Non-Multiplexed Operation)

8-83
Note: All typical values have been guaranteed by characterization and are not tested.

i

i

ICM72S:3
WRITE CYCLE TIMING (AS = "1")

AD-AS

ADDRESS VALID

00-07

E

WF030601

READ CYCLE TIMING (AS

="1")

ADDRESS VALID

00-07

E

f+----Tad----+l~

WF030701

Figure 5: ICM7283B Timing Diagrams . (Nol1~Multiplexed Operation)

Note: All typical values have been guaranteed by characterization and are not tested.

ICM7283
WRITE CYCLE TIMING

AS

----",

DD·D7. AD·A6

-+__+-+-______

E ____________

~

WFOS0601

READ CYCLE TIMING

AS

----,

•

RNl~

Teye

~T.I T~~
~/#~oW$$$#I?·

W///#r0:·
.

•

.I

WF030901

~____________F_i9_U_~__6._~_'C_M_7~2_83_B__T_im_'_ng__D_ia_g_ra_m_S__(M_u_lt_iP_'e_x_e_d_o_p_e_r_at_io_n_)__________~ ~

8-85
Note: All typical values have been guaranteed by characterization and· are not tested.

SelK

DOUT

--_----'4-_ _ _-.-+_-+I.------i---.£---

DLAT

______~~_~-----t~dl-WF029201

IC~7283

Figure 7;

Serial Output Timin9 Diagram
other display controllers, the ICM7283 will not "go busy" for
milliseconds at a time while processing data or commands.

Table 1: Pin Descriptions
SIGNAL
ROW1-16

PIN
10-1,
48,47

DESCRIPTION

"'

15

Serial data

VOISP
V2, V3

16

Negative LCD supply voltage

17, 18

DCONT

19

Column driver contr.ol .output

SCLK

20

Serial data cicek .output

DLAT

21

R.ow data latch .output

VINV

22

Negative v.oltage generlilt.or
cl.ock

OSC

23

Oscillat.or input

VSS

24

Digital gr.ound

DO-D7
RD(7280A)
E(7280B)

LCD c.olumn v.oltage

Data I/O

R/W(7280B)

Write input ,
Read/write input

ALE(7280A)
AS(7280B)

37
37

Addr!lss latch ~nable
'Address strobe

38

Chip select input

CS
AO-A6
VOO

39-45
46

To use the ,ICM7283 on a multiplexed bus, tie the AO-AS
. lines tO,the DO-0.6 lines and ALE/AS driven with the system
address latch enable .or strobe signal. For a non-multiplexed
bus, AO-A6 should be connected to the least Significant
address lines, 00-07 connected to the data bus and ALE/
·AS tied high. The only external circuitry needed is a chip
select or address decoder. The ICM7283 uses an address
sPaC;e of 1,2/J. bytes. '

ICM7281 Data Interface

Read input
Enable input .

35
35
36
36

W~7280A)

There are two versions of the ICM7283. The ICM7283A
has WR and RD pins, as well as ALE and CS. This version
can be interfaced to standard multiplexed or n.on-multiplexed data buses of parts such as the 8085, Z80, 8088 and
.other microprocessors. The ICM7283B has R/W, E and AS
pins instead of WR and RD and ALE. The ICM7283B is
intended for use on 6800 and 6500 family buses.

".

Dou':··

25-29
32-34

Microprocessor Bus Interface

LCD r.ow drivers

The 'ICM7283 RO'N Drivers require ICM7281 Column
Drivers to operate an LCD display. Three lines are used to
load data serially into thelCM7281 column drivers, DOUT,
SCLK, and DLAT. The data is latched and shifted with each
negative going edge of SCLK, and the data is transferred
from the ICM7281 shift register to its latches with the
,negative going Eldge of DLAT. The frequency of the SCLK is
set by the oscillator frequency of the ICM7283 and is
normally about 600kHz.

Address inputs
P.ositive digital and LCD supply
v.oltage

Oscillator
The ICM7283 oscillator will free run at 600kHz in die
form, when not loaded with any capaCitance. With 15pF of
external capaCitance, the frequency will be about 250kHz.
Figure 8 shows the relationship between oscillat.or peri.od
and the value of Cexternal. Table 1 shows the relationship
between the oscillator frequency and various display system Signals and features. Standard CMOS logic gates can
be used to overdrive the oscillator to control frequency. A

DETAILED DESCRIPTION
Hardware Interface
Figure 1 is a simplified block diagram .of the ICM7283. It is
a dedicated hardware IC and the speed of data entry and
command processing is limited only by gate delays. Unlike
8-86

Note: All typical values have been guaranteed by characterization and are not tes\ed.

ICM7283
suitable frequency can also be derived by dividing down the
host processor's clock.

Table 2: ICM7283 Display System Frequencies
SIGNAL NAME

FREQUENCY

COMMENTS

SCLK

asc

Sets data transfer rate to ICM7281 column drivers

DLAT
Display Control

OSC/M

Once per row multiples period.

LCD Multiplex Freq.

OSC/(NxMx2)

Blink Rate

OSC/(NxMx64)

Blink rate for blinking cursor and blinking characters

OSC

AC waveform for generating a negative voltage for VDISP

VINV
NOTES:

OSC/M
Should be above 30Hz to avoid flicker.

Where N = number of rows - I.e. 16.
M = 40 x number of columns (5 or 6) per character. Add 14 if annunciators enabled.

Table 3: ICM7283 Memory Map
ADDRESS

FUNCTION

DECIMAL

HEX

0-79

00H-4FH

Character RAM. Loaded with ASCII data characters to be
displayed. Address 0 is the upper leftmost character and Address
40 (28H) is the lower leftmost character.

80-119

50H-77H

Font RAM. Holds bit pattern for four user-definable characters. See
Table 4.

120

78H

Instruction register 0 (IRO)

121

79H

Instruction register 1 (IR1)

122

7AH

Instruction register 2 (IR2)

123

7BH

Cursor Register (IR3)
Unassigned
Annunciator Register 1 (AR1)

124

7CH

125

7DH

126

7EH

Annunciator Register 2 (AR2)

127

7FH

Cursor-Addressed Entry Register

NOTE: See Table 6 for more detail about addresses 120-127 (78H-7FH).

Display Interface

rlpa,

The ICM7283 will support a dot matrix LCD display which
has 16 rows, and either evenly-spaced columns or a space
after every fifth column. If the display has evenly-spaced
columns, then 6 columns per character should be selected
and the sixth column is always blank. If the display provides
a blank after every fifth column, then 5 columns per
character should be selected. The character font is automatically changed to take advantage of all rows. The
ICM7283 will automatically use one of the 6 evenly-spaced
columns for a space.

I"

10

/

V

V

V

./

V

/'

10

l/

20

The ICM7283 can drive. LCD displays with threshold
voltages up to 2.5. volts. There is no minimum display
threshold voltage since VDISP can be above VSS.

30

40

50

-

The ICM7283 also has 16 onboard row drivers designed
to handle large dot matrix displays. These drivers provide
fast slew rates, and have a minimum offset voltage.

60

CllItenII!flFI
OP057401

Figure 8: The Relationship Between
OSCillator P·eriod and Caxternal-

/HI7
Note: All typical values have been guaranteed by characterization and are not tested.

I.

Voo(+5V)

116v

+6.8""

4.3K

TAIIT

·3

15011

~ 1OllIlA ,

0.1""

46
Voo

-I,

R2

,.,

1.5M

lOOK

VoF(

ICM7283

111914

+5V

4

-=-

R4
10K

\UsP
TO
ICM7281
COLUM.
DRIVER

-=VIIV

22

~Sp,~1~6~

10K

- -3.IV

________

~

____

~

__________

~

__________________

24

AF038101

Figure 9: ICM7283, VOISP Temperature Compensation Circuit
, character data storage, 2 bytes for 14 independent annunciators or flags, 32 bytes for storing 4 user-programmable
characters, 4 ,bytes for control registers, and one dummy
address to identify cursor-addressed ,character entry.

Display Voltage Generator
The ICM7283 not only has an onboard resistor string to
generate the required V" V2, Va, and V4, but also has an
output that assistS in generating a negative voltage for
VOISP. The VINV pin is a low-impedance output that swings
from VOO to VSS at the oscillator frequency. The circuit of
Figure 9 connected to the VINV pin generates a temperature-compensated VOISP. Diodes 0, a,nd 02, with capacitors C, and C2 form ,a charge-pump negative voltage
generator. The ICl7611 CMOS op-amp and its associated
circuitry form an adjustable temperature,compensatedvoltage source ,that provides VOISP to the ICM7283, as well as
the ICM7281 column drivers. Temperature, compensation
for VOISP is necessary because the threshold voltage of
LCD fluids have a pronounced negative tempco.

Character RAM
Data may be entered in a random-access mode by simply
writing to the desired character address. Address 0 corresponds to the upper leftmost character of the display, and
address 79 corresponds to the lower rightmost character.
Block moves or other high-speed data transfers can be
used to move data from the host system's RAM or ROM to
the ICM7283's character RAM. Character data format is
standard ASCII for the 96 upper and lower case characters,
with the eighth data bit ignored. As shown in Figure 10, the
ICM7283 Character Font Table, the display controller also
recognizes three special eOntrol characters and 14 additional European and graphics characters. The characters 08
through 17 are alternate lower case characters.

SOFTWARE INTERFACE
Table 3 provides a memory map of the ICM7283. The
ICM7283 uses 128 bytes of memory space: 80 bytes for

6-88
Note: All typical values have been guaranteed by characterization and are not tested,

11•••11•••••••••

III1IIIIIIIII1I1
m

Rn

D~

MD

DU

.5

va

.~

••• a

uu

~n

a~

~m

Qa

.W

Q

.1111••••ill.ll•
• I.ililillllili.
Ililll••• I.lllil
•••11••••11•••••
10

IBll

17 12

1113

11154

100 &l5

10166

102 &7

103 18

104 &9

105 SA

10161

lG71e

1011D

101 IE

no

IF

",

iii.ii.i.i••••••
7G

11271

11372

"473

11514

11115

117 76

11877

III 18

12019

12171

12218

123 7C

124 7D

125 7E

1281F

127

I

rI

HEX DECIMAL

KEY
TBOO191I

Figure 10: ICM7283 Character Font

8-89
Note: All typical values have been guaranteed by characterization and are not tested.

a
ICM7283
...
~

. Table 4: Font RAM for User-Definable Characters
ROW
Row 1 (top row)

-

-

Row 8 (bottom row)

ASCII CHARACTER 0

ASCII CHARACTER 1

ASCII CHARACTER 2

ASCII CHARACTER 3

FONT ADDRESS

FONT ADDRESS

FONT ADDRESS

FONT ADDRESS

Decimal

Hex

Decimal

Hex

Decimal

Hex

Decimal

Hex

80

SOH

90

5AH

100

64H

110

6EH

-

-

-

-

-

'-

87

57H

-

-

--

-

97

Font RAM

-

-

-

-

61H

107

-

-

-

-

68H

117

-

-

-

75H

second occurence of. the attribute character. The entire
display can be blinked or blanked by setting the appropriate
bits in IRO.

In addition to the 120 characters available in the built-in
character ROM, 4 characters may be user,defined. Table 4
shows the mapping between the Font RAM and the userdefined character font. An example of an additional character is provided in Figure 11. Note that addresses 80-119
(50H-77H) hold 5 bit words that correspond to the bit
pattern of the four user-definable characters, such that
each 5 bit word defines the pattern for one row of the
character. The LSB cor~esponds to the. right-hand dot. Each
character uses 8 words, with the lowest address represent·ing the top row. Once defined, these characters are treated
the same as the predefined characters from the Font ROM.
Enter ASCII data 0, 1, 2, or 3 irt9 Character RAM to call up
one of those characters.

Table 5: ASCII Character 0 Example

Row
1
2
3
4
5
6
7
8

Font Address
Decimal
Hex
80'
81
82
83
84
85
86
87

'50H
51H
52H
53H
54H
55H
56H
57H

I

Data
Decimal
Hex
5
14
21
14
21
14
21
4

05H
OEH
15H
OEH
15H
OEH
15H
04H

The CursQr Register determines the location of the cursor
on the display. If data is written to address 127 (7FH), the
data is entered at the current location of the cursor and the
cursor position is incremented. The cursor position may be
directly set by writing to Cursor Register address 123 (7BH).
The cursor may also be incremented or decremented by
writing the appropriate instructions to IR2 at address 122
(7AH). The cursor location will wrap around from 79 to 0 or
vice versa when incremented or decremented. A number
greater than 79 written to the Cursor Register causes no
cursor to be displayed, but the ICM7283 will otherwise
function normaily. If bit 4 of IR1 at address 121 (79H) is at
"1 ", then all characters to the right of the cursor are
blanked but the data in the character RAM is retained.
TBOO2011

The IRO register is a bit setlreset register. The MSB
selects either set (1) or reset (0) operation. A "1" in any
other bit position selects that bit to be set/reset. For
example, a bit pattern of 10011001 will set bits 0,3 and 4,
while a bit pattern of 00010000 will clear bit 4. Unselected
bits are not affected.

Figure 11: An Example of a User-Defined
Character

Instruction and Annunciator Registers
Table 5 details the bit assignments of the control
registers. All registers are write-only registers.
Attributes are enabled by bit 5 of Instruction Register IR2,
at address 122 (7AH). Blinking, underlined, and reverse
video characters are controlled by attribute characters in
the character RAM. These attribute characters are displayed as blanks, but signal the ICM7283 that the characters to the right of the attribute character are to be displayed
with one of the three attributes (5 = underline, 6 = reverse
video, and 7 = blinking). Each attribute is cancelled by a

The Annunciator Registers are bit setlreset registers that
. operate similarly to IRO. When used with the ICM7281
column drivers, bit 0 of Annunciator Register 1 will be the
last bit shifted out, and will appear at the column 1 output of
the ICM7281. Bit 6 of Annunciator Register 2 is the first
annunciator bit to be shifted out, and will appear on column
14 of the ICM7281. The annunciator outputs, if enabled,
appear on all rows in columns 1-14. Annunciators are
enabled by bit 7 at IR1.
8-90

Note: All typical values have been guaranteed by characterization and are not tested.

ICM7283
Bit 6 of instruction register 2 resets all instruction
registers, annunciator registers, and the Cursor Register. Bit
6 of Instruction Register 2 also resets and stops the display
multiplex··and ·blink counters.

2x40 CHARACTER LIQUID CRYSTAL
DISPLAY SYSTEM
Figure 10 shows a complete 2 line by 40 character Intel/
Zilog compatible display system without annunciators. The
ICM7283A receives ASCII character data from the host
microprocessor, converts it to a serial data stream for the
ICM7281 column drivers, and provides the row drive
voltages and overall display system timing and control. The
power consumption of this display system is typically 6
milliwatts during normal operation and 5 microwatts when
shutdown (but retaining data and control setup).
If less than 80 characters are desired, the ICM7281, s that
would normally drive the right-hand characters of the
display may be left out. This means that an 80 character
display module and a module with fewer characters can
have exactly the same hardware and software interface,
except that extra ICM7281's are missing from the module
with fewer characters.

All register bits except bit 6 of IR2 are reset upon powerup. Since bit 6 of IR2 is indeterminate at power-up, and the
instruction registers cannot be written to while bit 6 is set,
the initialization routine should first clear bit 6 before the
other registers of the ICM7283 display controller, are
accessed. When normal operation resumes after bit 6 of
IR2 is cleared, the attributes will be off and the. cursor will be
present at O.
CAUTION: The ICM7283 should not be left in the reset
mode for extended periods, because in this condition there
is a DC bias on the liquid crystal display which can
permanently damage it.

1CM7283
R1-18

1f

TO
MICROPROCESSOR

lCDDISPLAY
18 ROWS. UP TO 240 COLUMNS

18

ALE
7
8

140

AO·6
1)0.7

~iiD

S.ClK

Wii
Cs"

DOUT
DATA
LATCH
DISPLAY
CONTROL
V2

VOD

VDISP

V3

+5

ROW
DRIVE

ClK

f40

r-40 r-r-r-r-r---r--

DATA IN COL
DATA
LATCH
DISPLAY
CONTROL
V2
V3
VDISP

Vss

ICM7281
#1

,h

ClK
D.ATA INC~L
DATA
LATCH
DISPLAY
CONTROL
V2
V3
VDISP
ICM7281
112

••••

t---t----

------

~--...----

---••••

f40
ClK
DATA IN
DATA
LATCH
DISPLAY
CONTROL
V2
V3
VDISP
ICM7281
#8

I
VDISP
GENERATOR

BD015001

Figure 12: 2 Line by 40-Character LCD Display System

8-91
Note: All typical values have been guaranteed by characterization and are not tested.

.:3 ICM7283
....(\I

~

Table 6' instruction and Annunciator Registers
120 Decimal
78 Hex
D7
D6
D5
D4
D3
D2
D1
DO

Instructl!)" Register 0
IRO'
.
1 = SET 0 = RESET
1 = Blank Display
1 = Blink DispllilY
1 = Cursor .Enabled
1 = Power Down Mode
unassigned, set to O.
unassigned, set to O.
o = Normal Operation, 1 = Test Mode

121 Decimal
79 Hex
D1
06
D5
D4
D3
D2, 01, DO
122 Decimal
7A Hex
07
06
.05
D4, 03, 02
D1, DO

Instruction Register 1
IR1
1 = Enable Annunciators
1 =, Blinking Box Cursor 0 = Underline Cursor
1 = Blank characters to the right of the cursor
1 = 6 columns per character 0 = 5 columns per character
1 = All on test mode. Ail dots and annunciators turned on, 0 = Normal Operation
unassigned, set to O.
Instruction Register 2
IR2
Production test mode only. MOst beset to O.
1 = Resets ail registers. See test on previous page.
1 = Enable Attributes
unassigned, set to O.
See the following table:
~ Do Control Bit Designators
0
1
0
1

0
0
1
1

No operation
Decrement Cursor Register
Increment Cursor Register
Increment Cursor Register

123 Decimal
Cursor Register
IR3
78 ...ex
This register specifies the address of the cursor using a 7 bit value in the range of 0-79 decimal, 0-4F hexadecimal. The eighth bit
is ignored.
124 Decimal
7C Hex
125 Decimal
70 Hex
126 Decimal
7E Hex

Unassigned
"

,

Annunciator Register 1
AR1
Annunciator Register 2
AR2
The 7 LSBs of each annunciator register (DO-D6) each control one annunciator. To set, write a 1 to the MSB and a 1 to the bits to
be set. To clear, write a 0 to the MSB and a 1 to the bits cleared. Then annunciator will appear left to right AR1 :DO to D6 then
AR2:DO to D6.
.
127 Decimal
Cursor-Addressed Entry
7F Hex
When character data is written to this address, the data is loaded into the character RAM using the Cursor Register as a pOinter
and the Cursor Register is incremented.

8-92
Note: All typical values have been guaranteed by characterization and are 'not tested.

Section 9 - Microcontrollers,
Microperipherals, Memory

ICM7170
MP-Compalible
Real-Time Clock",':".
""1&

GENERAL DESCRIPTION

FEATURES

The ICM7170 real time clock is a microprocessor bus
compatible peripheral, fabricated using Intersil's silicon gate
CMOS LSI process. An S-bit bidirectional bus is used for the
data I/O circuitry. The clock is set or read by accessing the
S internal separately addressable and programmable counters from 1/100 seconds to years. The counters are
controlled by a pulse train divided down from a crystal
oscillator circuit, and the frequency of the crystal is selectable with the on-chip command register. An extremely
stable oscillator frequency is achieved through the use of
an on-chip regulated power supply.
The device access time (tacd of 300ns eliminates the
need for any microprocessor wait states or software overhead. Furthermore, the ALE (Address Latch Enable) input is
provided for interfacing to microprocessors with a multiplexed address/data bus. With these two special features,
the ICM7170 can be easily interfaced to any available
microprocessor.
The ICM7170 generates two types of interrupts. The first
type is the periodic interrupt (i.e., 100Hz, 10Hz, etc.) which
can be programmed by the internal interrupt control register
to provide 7 different output signals. The second type is the
alarm interrupt. The alarm time is set by loading an on-chip
51-bit RAM that activates an interrupt output through a
comparator. The alarm interrupt occurs when the real time
counter and alarm RAM time are equal. A status register is
available to indicate the interrupt source.
An on-chip Power-Down Detector eliminates the need for
external components to support the battery back-up function. When a power-down or power failure, occurs, internal
logic switches the on-chip counters to battery back-up
operation. Input/output and read/write functions become
disabled and operation is limited to time-keeping and
interrupt generation, resulting in low power consumption.
Internal latches prevent clock roll-over during a read
cycle. Counter data is latched on the chip by reading the
100th-seconds counter and is held indefinitely until the
counter is read again, assuring a stable and reliable time
value.

•
•
•
•
•
•
•
•
•
•
•
•

8-Bit /lP Bus Compatible
- Multiplexed or Direct Addressing
Binary Time Data Format Lowers Software
Overhead
Time From 11100 Seconds to 99 Years
Software Selectable 12/24 Hour Format
Latched Time Data Ensures No Roll-Over During
Read
Full Calendar With Automatic Leap Year
Correction
On-Chip Battery Backup Switchover Circuit
Access Time Less Than 300ns
4 Programmable Crystal Oscillator Frequencies
On-Chip Alarm Comparator and RAM
Interrupts from Alarm and 6 Selectable Periodic
Intervals
Standby Micro-Power Operation: 2p.A Typ. at
3.0V and 32kHz Crystal

APPLICATIONS
•
•
•
•

Portable and Personal Computers
Industrial Control Systems
Data Logging
Point Of Sale

ORDERING INFORMATION
PART
TEMPERATURE
NUMBER
RANGE
PACKAGE
ICM7170lPG
ICM7170lJG

-40·C to +85°C
-40·C to + 85·C

WR
ALE

24-PIN PLASTIC DIP
24-PIN CERDIP

Rii
Voo

cs

07

A4

06

A3

05

A2

04

AI

03

AO

02

OSC OUT

01

OSCIN

00

INT SOURCE
INTERRUPT

VBACKUP
Vss (GNO)

Figure 1: Pin Configuration

9-1

Note: All typical values have been guaranteed by characterization and are not tested.

301680-005

I

.~

... '<*1110'
~

ABSOLUTE MAXIMUM RATINGS
Supply Voltage ...•..• ; .•..•....•..••••••.••••••••...•.•.••.•.•... 8V

Operating Temperature """,,,,.,.,, ••• ,,.-40'C to +85'C
Storage Temperature ...• " •..•••••.••.•••• .,.65'C to + 150·C
Lead Temperature (Soldering, 10sec) ..•••..••..•.•.•• 300·C

Power Dissipation (Note 1)".""."""."".""."" 500mW
Input Voltage (Any Terminal)
(Note 2) """"""".""."". VOD+O.3V to VSS -O.3V
NOTE 1: TA = 25°C.

NOTE 2: Due to the SCR structure inherent in the CMOS process, connecting any terminal at voltages greater than VDD or less than Vss may cause
destructive device latchup. For this reason, it is recommended thai no inputs from external sources not operating on the same power supply be applied to the
device before its supply .is established. and. that .in multiple supply systems, the supply to the ICM7170 be turned on first
Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

OSCILLATOR
CRYSTAL

INTERRUPTS

INT
11 SOURCE

VnD
VuACKUP

Vss
DATA 110
00.0,

ADDRESS}
INPUTS
Ao·A, .

Figure 2: Functional Diagram

ELECTRICAL CHARACTERISTICS
D.C. CHARACTERISTICS (TA = -40'C

to

+ 85·C,

VDD = +5V ±10%, VSACKUP = Voo,Vss

OV unless otherwise
specified)

SPECIFICATION
SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
MIN

vpo

2.6

voo Supply Range (32kHz/4MHz)

ISTBY(I)

Standby Current

ISTBY(2)

Standby Current

100(1)

Operating Supply Current

TYP

FXTAl - 32kHz
Pins 1-8,15-22 & 24 = Voo
VOO = VSS; VBACKUP = VOO-3.0V
FXTAl = 4MHz
Pins 1-8,15-22 & 24 = VDD
Voo = VSS; VBACKUP = VoO-3.0V
FxrAl = 32kHz
Read/Write Operation at 100Hz
FXTAl = 32kHz
Read/Write Operation at 1MHz

100(2)

Operating Supply Current

Vil
VIH

Input low voltage
Input high voltage

Voo= 4.5V
Voo-4.5V

VOL

Output low voltage except INTERRUPT

IOl-I.6mA

MAX
5.5

V

2.0

20

p.A

20

150

p.A

0.3

1.2

mA

1.0

2.0

mA

0.8

V
V

0.4

V

3.5

9-2
Note: AU typical values have been guaranteed by characterization and are not tested.

,

ICM7170
ELECTRICAL CHARACTERISTICS (CONT.)
PARAMETER

SYMBOL
VOH
IlL
IOL
VBAITERY
VBAITERY
VOL

Output high voltage except 1i\li'E:RRUPT
Input leakage current
Tristate leakage current (00-07)
Backup Battery Voltage
Backup Battery Voltage
Output low voltage INTERRUPT

IOL

Leakage current INTERRUPT

SPECIFICATION
TEST CONDITIONS
IOH -400"A
VIN - VOO or VSS
Va - VOO or VSS
FXTAL -1, 2, 4MHz
FXTAL - 32kHz
IOL = 1.6mA
liNT SOURCE
connected
Va = VOO or VSS
to VSS

UNIT
MIN
2.4
-10
-10
2.6

TYP

MAX

0.5
0.5

+10
+10
3.2
3.2
0.4

V

2.0

I

10

"A

IlA
V
V
V

IlA

AC CHARACTERISTICS

(TA= -40·8 to +85·C, VDD= +5V ±10% Do-D7 VBACKUP= VDD Load
Capacitance = 150pF, VIL = O.4V, VIH = 3.5V unless otherwise specified)

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

'170
200

250
300

ns
ns
ns

65
ADDRESS to READ set up time'.
100
ADDRESS HOLD time after READ'
0
READ pulse width, loW'
0.25
'Guaranteed Parameter by Design (Not 100% Tested)

100

ns
ns
ns

9,000'

IlS

MAX

UNIT

READ CYCLE TIMING
trd
tacc
Icyc
trx
tas
tar
trl

READ to DATA valid
ADDRESS valid to DATA valid
READ cycle time
RD high to bus tristate

400

WRITE CYCLE TIMING

MIN

tad
twa

ADDRESS valid to WRITE strobe
ADDRESS hold time for WRITE

twl

WRITE pulse width, low

Idw

DATA IN to WRITE set up time

100

twd

DATA IN hold time after WRITE

30

Icvc

WRITE cycle time

400

MULTIPLEXED MODE TIMING

MIN

TYP

ns

100
0
"

ns
ns

100

ns
ns

10

ns

TYP

MAX

UNIT

til

ALE Pulse Width, High

50

ns

tal
tla

ADDRESS to ALE set up time

30
30

ns

ADDRESS hold time after ALE

9-3

Note: All typical values have been guaranteed by characterization and are not tested.

ns

.O~DI6
" READ CYCLE TIMING FOR NON·MULTIPLEXED BUS (ALE = "1"; WR= 1)

ADDRESS VALlD,CS LOW

~------~------~

Do-D7

--'--

I-----t_------I
Wf"02820\

\'IiRITE CYCLE TIMING FOR NON·MULTIPLEXED BUS (ALE = "1", RD= 1)

ADDRESS VALlD,CS LOW

r

tw1

~----~----'~--------~.....~

00-07

_____

~"'::::::::::_fdw-I.:P:UT:D:A:TA:V:;A-L1-D---'

3 _.. :. __ "- ~ __

d

_fw_

WF028301

Figure 3: Timing Diagrams -

Nonmultiplexed Bus

Note; All typical values have been guaranteed by characterization and are not tested.'

ICM7170
READ CYCLE TIMING FOR MULTIPLEXED BUS (WA

Ao-A4. Do-DJ

= 1)

OUTPUT DATA VALID

CS - - 1-01----111----+1
ALE
~---~I---~~

WF028001

WRITE CYCLE TIMING FOR MULTIPLEXED BUS (RD = 1)

Ao-A4. Do-D7

a - - \

twd

1--'----111 - ALE

14----101 ---+i

WF028101

NOTE: The AO to A4 aridress inputs may be connected to the DO to D4 data lines when a multiplexed bus is used.

Figure 4: Timing Diagrams -- Multiplexed Bus

Note: All iypical values have been guaranteed by

charact"riza~on

and .l!'e not tested.

\

2
,""...
~

'ICM7170
Table 1
SIGNAL

PIN

WR

1

Write input

ALE

2

Address latch enable input

3

Chip select bar input

CS
A4-AO

4-8

The 4000Hz signal is divided down further to 100Hz,
which is used as the clock for the counters. Time and
calendarinformation is provided by 8 consecutive addressable, programmable counters: 100ths of seconds, seconds,
'minutes, hours, day of week, date, month, and year. The
data: is in binary format and is configured into 8 bits per digit.
See Table 4 for address information. Any unused bits are
held at logic "0" during a read and ignored during a write
operation.

DESCRIPTION

Address inputs

OSC OUT

9

Oscillator output

OSC IN

10

Oscillator input

INT SOURCE

11

Interrupt common

INiERRUj5T

12

Interrupt output

VSS(GND)

13

Digital common

VBACKUP
DO-07

14

Battery negative side

Compare Interrupts
On the chip are 51 bits of Alarm Compare RAM grouped
into, words of different lengths. These are used to store the
time, ranging from 100ths of seconds to years, for comparison to the real-time counters. Each counter has a corresponding RAM word. In the Alarm Mode an interrupt is
generated when the current time is equal to the alarm time.
The RAM contents are compared to the counters on a word
by word basis. If a comparison to a particular counter is
unnecessary, then the appropriate 'M' bit in Compare RAM
should be set to logic "1".

15-22 Data 1/0

Voo
RD

23

Positive digital supply

24

Read input'

DETAILED DESCRIPTION
Oscillator

The 'M' bit, referring to Mask bit, causes a particular RAM
word to be masked off or ignored during a compare. Table 4
shows addresses and Mask bit information.

This circuit uses a standard CMOS Pierce oscillator, for
maximum accuracy, stability, and 'low-power consumption.
Externally, one crystal and two capacitors are required. One
of the capacitors is variable and is used to trim or tune the
oscillator output. Typical values for these capacitors are
C'N = 18pF and COUT = 10 - 35pF, or approximately double the recommended CLOAD for the crystal being, used.
Both capacitors must be connected from the respective
oscillator pins to VDO for maximum stability.
The oscillator output is divided down to 4000Hz by one of
four selected ratios, via a variable prescaler. The ICM7170
can use anyone of four different low-cost crystals:
4.194304MHz, 2.097152MHz, 1.048576MHz, or 32.768kHz.
The command register must be programmed for the frequency of the crystal chosen, and this in turn will determine
the prescaler's divide ratio.
Command Register frequency selection is written to the
DO and 01 bits at address 11 H and the 12 or 24 hour format
is determined by bit 02, as shown in Table 4.

Periodic Interrupts
The interrupt output can be programmed for 6 periodic
signals: 100Hz, 10Hz, once per second, once per minute,
once per hour, or once per day. "The 100Hz Interrupt,
10Hz Interrupt and the hundreths of a second counter
have instantaneous errors of ± 2.5%, ± 0.15% and
± 2.5% respectively; the time average, however, is zero."
These can occl,Jr concurrently and in addition to Alarm
Interrupts. Both the Periodic and the Alarm Interrupts are
controlled by the Interrupt Mask Register. The desired
interrupt is enabled by writing a logic "1" to the appropriate bit, as shown in Table 5.
The Interrupt Status Register, when read, indicates the
cause of the interrupt and resets itSelf on the trailing edge of
the read pulse. Once one or more bits have been set in the
Mask Register, a roll-over in a corresponding counter will
strobe the appropriate bit in the Interrupt Status Register.
The interrupt pin (# 12) is then pulled to the potential of the
interrupt source pin ( # 11) through an internal open-drain Nchannel MOSFET. This facilitates wire-ORing the ICM7170
with other interrupt generators that must be connected to
the system MPU.

Table 2: Command Register Format
COMMAND REGISTER ADDRESS (10001b, 11h) WRITE-ONLY

I
I

D7

nla

De

nla

I
I

'

I
I

D5
Test

D4
In!.

I
I

03
Run

I
I

02
12/24,

I
I

01
Freq

I
I

DO
Freq

Table 3: Command Register Bit Assignments
01
0

DO
0

CRYSTAL
FREQUENCY

02

24/12 HOUR
FORMAT

03

RUN/STOP

INTERRUPT
ENABLE

05

TEST BIT

0

Normal
Mode

1

Test Mode

32.768kHz

0

12 hour mode

0

Stop

0

Interrupt
disabled

1

24 hour mode

1

Run

1

Interrupt enable

0

1

1.048576MHz

1

0

2.097152MHz

1

1

4.194304MHz

9-6
Note:

04

All typical values have been guaranteed by characterization and are not tested.

.U~U(b

ICM7170
Table 4: Address Codes and Functions
ADDRESS
A3

A2

A1

AO

HEX

0
0

0
0

0
0

0
0

0
1

00
01

0
0
0
0
0
0
0
0

0
0
0
0
0
0
1
1

0
0
1
1
1
1
0
0

1
1
0
0
1
1
0
0

0
1
0
1
0
1
0
1

02
03
04
05
06

0
0
0
0
0
0

1
1
1
1
1
1

0
0
1

0
1
0
1
0
1

OA
OB
OC
00

1
1

1
1
0
0
1
1

1

0

0

0

0

10

1

0

0

0

1

11

NOTES:

1

VALUE
07

Counter-l/100 seconds
Counter-hours
12 Hour Mode
Counter-minutes
Counter-seconds
Counter-month
Counter-date
Counter-year
Counter-day of week
RAM-l/100 seconds
RAM-hours
12 hour Mode
RAM-minutes
RAM-seconds
RAM-month
RAM-date
RAM-year
RAM-day of week
Interrupt Status
and Mask Register
Command register

07

06
09

OE

OF

-

.

-M

.

06

05

04

-

-

_.

-

-.

M

-

M

-

M
M
M
M
M
M

-

-

-

-

-

-

03

02

01

DO
0-99
0-23
1-12
0-59
0-59
1-12
1-31
0-99
0-6
0-99
0-23
1-12
0-59
0-59
1-12
1-31
0-99
0-6

-

-

-

-

-

+

-

-

Address 10010 to 11111 ( 12h to lFh) are unused.
'+' Unused bit for Interrupt Mask Register, MSB bit for Interrupt Status Register.
'-' Indicates unused bits.
'., AMIPM indicator bit in 12 hour format. Logic "0" indicates AM, logiC "1" indicates PM.
'M' Alarm compare for particular counter will be enabled if bit is set to logic "0".

Table 5: Interrupt and Status Registers Format
INTERRUPT MASK REGISTER ADDRESS (10000b, 10h) WRITE·ONLY
07

I

06

I

05

I

04

I

03

I

02

I

01

I

DO

nla

I

Day

I

Hour

I

Min.

I

Sec.

I

1110 sec.

I

11100 sec.

I

Alarm

07

I

06

I

05

I

04

I

03

Inl.

I

Day

I

Hour

I

Min.

I

Sec.

INTERRUPT STATUS REGISTER ADDRESS (10000b, 10h) READ·ONLY

I
I.

02
1110 sec.

I
I

01

I

DO

11100 sec.

I

Alarm

If standby battery operation is not required the VBACKUP
. should be connected to Voo.

Interrupt Operation
The interrupt output N-channel MOSFET is active at all
times when the Interrupt Enable bit is set (bit 4 of the
Command Register), and operates in both the standby and
.
battery backup modes.
Since system power is usually applied between Voo and
VSS, the user can connect the Interrupt Source (pin" 11) to
VSS. This allows the Interrupt Output to turn on only while
system power is applied and will not be pulled to VSS during
standby operation. If interrupts are required only during
standby operation, then the interrupt source pin should be
connected to the battery's negative side (VBACKUP). In this
configuration, for example, the interrupt could be used to
turn on power for a cold boot.

APPLICATION NOTES
Time Synchronization
Time synchronization is achieved through bit 03 of the
Command Register, which is used to enable or disable the
100Hz clock from the counters. A logic "1" allows the
counters to function and a logic "0" disables the counters.
To accurately set the time, a logic "0" should be written into
03 and then the desired times entered into the appropriate
counters. The clock is then started at the proper time by
writing a logic "1" into D3 of the Command Register.

Latched Data

Power-Down Detector

To prevent ambiguity while the processor is gathering
data from the registers, the ICM7170 incorporates data
latches and a transparent transition delay circuit.
By accessing the 100ths of seconds counter an internal
store signal is generated and data from all the counters is
stored into a 36-bit latch. A transition delay circuit will delay
a 100Hz transition during a READ cycle until the internal
store operation is completed. The data stored by the
latches is then available for further processing until the
100ths of seconds counter is read again.

The ICM7170 contains an on-chip power-down detector
that eliminates the need for external components for the
battery back-up function. Whenever the voltage from the
VBACKUP pin to the VSS pin is less than approximately
1.0Volt, the chip automatically switches to battery backup
operation. Until power is restored, operation is limited to
time counting and interrupt generation only. All other
functions are disabled to achieve micropower standby
power and to preserve time integrity.

9-7
Note: All typical values have been guaranteed by characterization and are not tested.

...........
o

DATA
FUNCTION

44

i

2 ICM7170
,..

...

sU
_

+5V

25--~----------------~------------------~~~-----,

RIW"

18

11674HC04

WR
ALE

24
23

110 SELECT 1

CS

A4

6

Ali

4

A3

5

A3

A2

4

A2

Al

Al

5
6
7

AD

AD

8

OSC OUT
DICRYSTA:r
COUT
lD-35pF
IRQ

elN

18pF

21

ICM7170

iiii
Vou
07

42

07

06

43

06

05

44

05

04

45

04

03

46

03

47
48

02

49

DO

26

GNO

9

02
01

OSCIN

10

DO

INT SOURCE

11

INTERRUPT

12

01

30
+

Figure 5: Apple " Plus Board Schematic

Control Lines

2) Connect a fixed capaCitor from OSC IN to VOO.
3) Connect a variable capaCitor from OSC OUT to Voo.
In cases where the crystal selected is. a 32kHz
Statek type (Cl = 9pF), the typical value of
.CIN = 18pF and COUT = 10-35pF.
4) Place a 5Kn resistor from the '"IN1'iT""E"'R;;=R;oUii'P;TT pin to
Voo, and connect the INT SOURCE pin to VSS.
5) Apply 5V power and insure the clock is not in
standby mode.
6) Write all O's to the Interrupt Mask Register, disabling
all interrupts.
7) Write to the Command Register with the desired
oscillator frequency, Hours mode (12 hour or 24
hour), Run = "1", Interrupt Enable = "1", and
Test = "0".
8) Write to the Interrupt Mask Register, enabling onesecond interrupts only.
9) Monitor the INTERRUPT output pin with a precision
period counter and trim the OSC OUT capacitor for a
reading of 1.000000 seconds. The period counter
must be triggered on the falling edge of the interrupt
output for this measurement to be· accurate.
10) Read the Interrupt Status Register. This action
resets the interrupt output back to a logic" 1" level.
11) Repeat steps 9 and 10 with a software loop: A
suitable computer should be· used.

The RD, WR, and CS signals are active low inputs. Data
is placed on the bus from counters or registers when RD is
a logic "0". Data is transferred to counters or registers
when WR is a logic "0". RD and WR must be accompanied
by a logical "0" CS as shown in Figures 3 and 4.
With the ALE (Address Latch Enable) input, the ICM7170
can be interfaced directly to microprocessors that use a
multiplexed address/data bus by connecting the address
lines AO-A4 to the data lines 00-04. To address the chip,
the address is placed on the bus and ALE is strobed. On the
falling edge, the address and CS information is read into the
address latch and buffer. RD and iNA are used in the same
way as on a non-multiplexed bus. If a non-multiplexed bus is
used, ALE should be connected to Voo.

Test Mode
The test mode is entered by setting 05 of the Command
Register to a logic" 1". This connects the 1OOHz pulse train
to the seconds counter, and speeds up the counting
functions.

Oscillator Tuning
Oscillator tuning should. not be attempted by direct
monitoring of the oscillator pins, unless very specialized
equipment is used. External connections to the oscillator
pins cause capacitive loading of the crystal, and shift the
oscillator frequency. As a result, the precision setting being
attempted is corrupted. One indirect method of determining
the oscillator frequency is to measure the period between
interrupts on the Interrupt Output pin (#12). This measurement must be relative to the falling edges of the INTERRUPT .pin. The oscillator set-up and tuning can be performed .as follows:
1) Select one of 4, readily-available oscillator
frequencies and place the crystal between OSC IN
(pin #10) and OSC OUT (pin #9).

CIRCUIT APPLICATIONS.
Apple II Plus ~eal~Time Clock
C

Figure. 5 shows the schematic. of a board, using the
ICM7170, that has been fabricated to plug into a slot.in an
Apple II Plus microcomputE1r. Very few external components
are ne,eded on the board to provide an interface to the
Apple's 6502 MPU.
9-8

Note: All typical values have been guaranteed by characterization and are not tested.

IM4702/4712
Baud Rate Generator
GENERAL DESCRIPTION

FEATURES

The IM4702/12 Baud Rate Generators provide necessary clock signals for digital data transmission systems,
such as UARTs, using a 2,4576MHz crystal oscillator as an
input. They control up to 8 output channels and can be
cascaded for output expansion.

•
•
•
•
•
•

Output rate is controlled by four digital input lines, and
with the specified crystal, is selectable from "zero" through
,9600 Baud. In addition, 19200 Baud is possible via hardwiring.

•
•

Multi-channel operation is facilitated by making the clock
frequency and the +8 prescaler outputs available externally.
This allows up to eight simultaneous Baud rates to be
.generated.

Provides 14 Most Commonly Used BAUD Rates
On-Chip Oscillator Requires Only One External
Part (lM4712)
Controls Up to Eight Transmission Channels
TTL Compatible Outputs Will Sink 1.6mA
Uses Standard 2.4S76MHz Crystal
Low Power Consumption: S.SmW Guaranteed
Maximum Standby
Pin and Function Compatible With 4702B and
HD-4702
Inputs Feature Active Pull-Ups

PIN DESCRIPTION

The IM4712 is identical to the IM4702 with the exception
that the IM4712 integrates the oscillator feedback resistor
and two load capacitors on-chip.

ORDERING INFORMATION

SIGNAL

PIN

0 0- 0 2

1,2,3

ECP

4

CP

5

External Clock Input

Ox

6

Crystal Output

Ix

7

Crystal Input

VSS

8

Negative Supply

Co

9

Clock Output

Z

10

SO-S3

14-11

DESCRIPTION
Prescaler Outputs
External Clock Enable Input

ORDER
NUMBER

TEMPERATURE
RANGE

PACKAGE

IM47021JE

-40°C to +85°C

16-pin CERoIP

IM47021PE

-40°C to + 85°C

16-pin PLASTIC

IM47121JE

-40°C to + 85°C

16-pin CERDIP

1M

15

Multiplexed Input

IM47121PE

-40°C to +85°C

16-pin PLASTIC

VOO

16

Positive Supply

Baud Rate Output
Baud Rate Select Inputs

:r------,
c::t.: r----------------r-------,
I

COUNTU NETWOM

I

:

: ....... .,lal

L

: . ;
;
I

:

!I

I I
I
I
I

1c'-1r---~-LJ

IIUL'N'C.EIIU

, I I

00

: H-t-H+t++==~
I
I

:tHttHit:===-~~

I
I

I

1·-----------

VDO

0,.

1M

cq

So

Ec,

St

CP
Ox

Sz
Sa

Ix
Vss

CO

Z

I
I

,

" ",:I-+-DIO>-1"""O>-'

:~

I

:

o. f :
l"!'!~

MAX

UNIT
V

70% Voo
-1.0

10% VOO

V

1.0

IlA
V

+ 0.01

V

ICC

Power Supply Current Standby

VIN = VSS or Voo

500

IlA
IlA

Icc

Power Supply Current IM6402A

fcrystal - 4MHz

9.0

mA

ICC

Power Supply Current IM6403A

Icrystal = 3.58MHz

13.0

mA

CIN

Input CapaCitance [1] [3]

TA = 25°C

7.0

8.0

pF

Co

Output CapaCitance [1] [3]

TA = 25°C

8.0

10.0

pF

-1.0

1.0
5.0

NOTE: 1. Except IM6403 XTAl input pins (i.e. pins 17 and 40).
2. VOO = 5V, T A = 25°C.
3. These parameters are guaranteed but not 100% tested.

AC ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

Ic

Clock Frequency IM6402A

Icrystal

Crystal Frequency IM6403A

tpw

Pulse Widths CRl,

tmr

Pulse Width MR

tds

Input Data Setup Time

Idh

Input Data Hold Time

ten

Output Enable Time

Dm'i,

(Voo = 10.0V ±5% Vss = OV, CL
TEST CONDITIONS

= 50pF,
MIN

TA = Operating Temperature Range)
TYp2

D.C.

TIiR[

MAX

UNIT

4.0

MHz

6.0

MHz

100

40

ns

See Timing Diagrams

400

200

ns

(Figures 4,5,6)

40

0

ns

30

30
40

9-19
Note: All typical values have been guaranteed by characterization and are not tested.

ns
70

ns

.O~DIL

S IM64021lM8403

:!

.ft

!!

(IM6402-11/1M, IM6403-1111M)
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Voo-Vss) ..••••..........•....••••.•.. +8.0V
Voltage On Any Input or Output Pin ..••••••• (VSS -0.3V)
to (VOO + 0.3V)

Operating Temperature Range
IM6402-11/03-11. .••••••.....•••...•.. -40·C to +85·C
IM6402-1M/03-1M .••............. -55·Cto +125·C
Storage Temperature Range ..........•• -65·C to + 150·C
Lead Temperature (Soldering, 10sec) ..•....••........ 300·C

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent device failure. These are stress ratings only and functional
operation of the devices at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may cause device failures.

DC ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

(Voo

= 5.0

±10% VSS

MIN

TEST CONDITIONS

VIH

Input Voltage High

Vil

Input VOltage Low

III

Input

VOH

Output Voltage High

VSS :5 VIN :5 Voo
IOH= -0.2mA

VOL

Output Voltage Low

IOl = 2.0mA

IOlK
Icc

Output Leakage

Vss :5 VOUT:5 VOO

Power Supply Current Standby

ICC

Power Supply Current IM6402 Dynamic

VIN = Vss or Voo
fe = 2M Hz

Lea~age

= OV,TA = Operating

Temperature Range)

TYp2

MAX

[1 )[3]

UNIT
V

VOO-2.0
-1.0

0.8

V

1.0

pA

2.4

V

-1.0
1.0

0.45

V

1.0

pA

100

pA

1.9 ,

mA

5.5

ICC

Power Supply Current IM6403 Dynamic

CIN

Input Capacitance 11) [3)

'Crystal = 3.58MHz
TA = 25'C

7.0

8.0

mA
pF

Co

Output Capacitance [1] [3)

TA = 25'C

8.0

10.0

pF

NOTE: 1. ExceptlM6403 XTAL input pins (i.e. pins 17 and 40).
2. VOO = 5V, TA = 25'C.
3. These parameters are guaranteed but not 100% tested.

AC ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

(voo = S.ov ± 10% VSS
TEST CONDITIONS

IM6402~1

fe

Clock Frequency

ferystal
tpw

Crystal Frequency

tmr

Pulse Width MR

Ids
Idli
len

Input Data Setup Time

Pulse Widths CRL,

= OV,

CL = SOpF, TA - Operating Temperature Range)
MIN

Typ2

D.C.

IM640~-1

DF!R,

T!lR[,

See Timing Diagrams
(Figures 4,5,6)

Input Data Hold Time

MAX

UNIT

2.0

MHz

3.58

MHz

150

50

ns

400

200

ns

50

20

ns

60

40

Output' Enable Time

80

ns
160

ns

TIMING DIAGRAMS
CLSI. CLS2, SSS, PI, EPE

WF009201

Figure 4:

Da~

WFOO9301

Input Cycle

Figure 5: Control Register Load Cycle

9-20
Note: All typical values have been guaranteed by characterization and are not tested.

IM8402/IM8403
SFDDR RRD

\
STATUS OR
RBAl· RBR8

PIN

SYMBOL

DESCRIPTION

15

OE

A high level on OVERRUN
ERROR indicates the data
received flag was not cleared
before the last character was
transferred to the receiver buffer
register. The Error is reset at the
next character's stop bit if DRR
has been performed (i.e.. DRR:
active low).

16

SFD

A high level on STATUS FLAGS
DISABLE forces the outputs PE.
FE. OE. DR". TBRE" to a high
impedance state. See Block
Diagram and Figure 6.

V"

)

VALID
DATA

~t.nWFOO9401

Figure 6: Status Flag Enable Time
or Data Output Enable Time

" IM6402 only.

Table 1: IM6402/3 Pin Description
PIN

SYMBOL

1

VOO

2

IM6402-N/C
IM6403-Control

17 IM6402-RRC
IM6403-XTAl

DESCRIPTION

Positive Power Supply
'No Connection
Divide Control
High: 24 (16) Divider
low: 211 (2048) Divider

3

VSS

Negative Supply

4

RRD

A high level on RECEIVER
REGISTER DISABLE forces the
receiver holding rellister outputs
RBR1-RBR8 to a high impedance
state.

5

RBR8

The contents of tne RECEIVER
BUFFER REGISTER appear on
these three-state outputs. Word
formats less than 8 characters
are right justified to RBR1.

6

RBR7

See Pin 5 - RBR8

7

RBR6

See Pin 5-RBR8

8

RBR5

See Pin 5 - RBR8

9

RBR4

See Pin 5 - RBR8

10

RBR3

See Pin 5 - RBR8

11

RBR2

See Pin 5 - RBR8

12

RBR1

See Pin 5 - RBR8

13

PE

A high level on PARITY ERROR
indicates that the received parity
does not match parity
programmed by control bits. The
output is active until parity
matches on a succeeding
character. When parity is
inhibitec;l. this output is low.

14

FE

A high level on FRAMING
ERROR indicates the first stop bit
was invalid. FE will stay active
until the next valid character's
stop bit is received.

The RECEIVER REGISTER
CLOCK is 16X the receiver data
rate.

18

DAR'

A low level on DATA RECEIVED
RESET clears the data received
output (DR), to a low level.

19

DR

A high level on DATA RECEIVED
indicates a character' has been
received and transferred to the
receiver buffer register.

20

RRI

Serial data on RECEIVER
REGISTER INPUT is clocked into
the receiver register.

21

MR

A high level on MASTER RESET
(MR) clears PE. FE. OE. DR. TRE
and sets TBRE. TRO high. less
than 18 clocks after MR goes low.
TflE returns high. MR does not
clear the receiver buffer register.
and is required after power-up.

22

TBRE

A high level on TRANSMITTER
BUFFER REGISTER EMPTY
indicates the transmitter buffer
register has transferred its data to
the transmitter register and is
ready for new data.

23

TBRl

A low level on TRANSMITTER
BUFFER REGISTER lOAD
transfers data from inputs TBR1TBR8 into the transmitter buffer
register. A low to high transition
on TBRl requests data transfer
to the transmitter register. If the
transmitter register is busy.
transfer is automatically delayed
so that the two characters are
transmitted end to end. See
Figure 4.

24

TRE

A high level on TRANSMITTER
REGISTER EMPTY indicates
completed transmission of a
character including stop bits.

9-21

Note: All typical values have been guaranteed by characterization and are not tested.

§IM6402/IM6403

I:::.

!!

TRANSMITTER OPERATION

Tabl, 1: IM6402/3 Pin De$cription
(CONT.)
PIN

SYMBOL

DESCRIPTION

25

TRO

,Character data, start data and
stop bits. appear serially at the,
TRANSMITTER REGISTER
OUTPUT.

26

TBRt

5-8 DATA BITS

orART

I

Character data is loaded into the
TRANSMITTER BUFFER
REGI,STER via inputs TBRtTBRS. For character formats less
than a-bits, the TBRB, 7, and 6
Inputs are ignored corresponding
to tl)e programmed word length.

TBR2

2B

TBR3

See Pin 26-TBRt

29

TBR4

'See Pin 26 -TBRt '

30

TBRS

See Pin 26 - TBRt

3t

TBR6

See Pin 26 - TBRt

32

TBR7

See Pin 26 - TBRt

33

TBRB,

See Pin 26 - TBRt

34

Cfll

A high level on CONTROL
REGISTER LOAD loads the
control register. See Figure S.

35

PI"

A high level on PARITY INHIBIT
inhibits parity generation, parity
checking and forces PE output
low.

I

36

SBS'

A high level on' STOP BIT
SELECT selects 1.5 stop bits for
a.5 character format and 2 stop
bits for other lengths.

37

ClS2*

These inputs program the
CHARACTER LENGTH
SELECTED. (CLS1 low CLS2 low
5-bits)(ClS1 high CLS2 low 6bits)(CLS1 low CLS2 high 7bits)(ClSt high ClS2 high B-bits)

3B

CLS1'

See Pin 37 - CLS2

39

EPE'

When PI is low, a high level on
EVEN PARITY ENABLE
generates and checks even
parity. A low level selects odd
parity.

1,11/2 OR 2 STOP BITS

.IT~ ~I::;=;:::;::;:':::;~:;:::;:~'-f'~I;:;:+,_
ILSS!
!M.. ! \1

U.L

.

L!PARITV

·.F ENABLED
AF021101

Figure 7: Serial Data Format
Transmitter timing is shown in Figure 8. Data is loaded
into the transmitter buffer register from the inputs TBR1
through TBRS by a lo,gic low on the TBRload input. Valid
data mUst be present at least tDS prior.to and tOH following
the riSing edge ofTBRL. If words less than 8 bits are used,
only the least significant bits are used. The character is right
justified into the least significant bit, TBR1. The rising edge
of TBRl clears TBREmpty. 0 to 1 clock cycles later, data is
transferred to the transmitter register, TREmpty is cleared
and transmission starts. TBREmpty is reset to a logic high.
Output data is clocked by TRClock, which is 16 times the
data rate. A second pulse on TBRLoad loads data into the
transmitter buffer register. Data transfer to the transmitter
register is delayed until transmission of the current character is complete. Data is automatically transferred to the
transmitter register and transmission of that character

See Pin 26-TBRt

27

40 IM6402-TRC
IM6403-XTAL

The transmitter section accepts parallel data, formats it
•and transmits it in serial form (Figure 7) on the TROutput
terminal.

begin~.

A

D

\'NDO'
LAST
STOP BIT
WF009501

Figure 8: Transmitter Timing (Not to Scale)

The TRANSMITTER REGISTER
CLOCK is 16X the transmit data
rate.

".,.

'See Table 2 (Control Word Function)

9--22

Note: All typical values have been guaranteed by characterization and are not. tested.

,IM640211M6403
Table 2· Control Word Function
CONTROL WORD
CLS2

CLSl

PI

EPE

SB~

L
L
L
L
L
L
L
L

L.

L

L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H

L
L
L
H
H
L
L
L
L
H
H
L
L
L
L
H
H
L
L
L
·L
H
H

L
L
H
H
X
X
L
L
H
H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

L~

L
L
L
H
H
H
H
H
H
H
H
H
H
H
H

X
X
L
L
H
H

X
X
L
L
H
H

X
X

DATA BITS

PARITY BIT

STOP BIT(S)

5

ODD
ODD
EVEN
EVEN
DISABLED
DISABLED
ODD
ODD
EVEN
EVEN
DISABLED
DISABLED
ODD
ODD
EVEN
EVEN
DISABLED
DISABLED
ODD
ODD
EVEN
EVEN
DISABLED
DISABLED

1
1.5
1
1.5
1
1.5
1

5
5
5
5
5
6
6
6
6
6
6
7
7
7
7
7
7
8
8
8
8
8
8

2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

1
2

x = Don't Care

RECEIVER OPERATION
Data is received in serial for,." at the RI input. When no
data is being received, RI input must remain high. The data
is clocked by the RRClock, which is 16 times the data rate.
.Receiver timing is shown in Figure 9.

BEGINNING OF FIRST STOP BIT~' ~7 1/2 CLOCK CYCLES
RR I

I

I

DATA

RBR1-8.0 E. PE

~~
DR

logic high on FError indicates an invalid stop bit was
-received. The receiver will not begin searching for the next
start bit until a stop bit is received.

START BIT DETECTION
The receiver uses a 16X clock for tirning. (See Figure 10.)
The start bit (A) could have occurred as much as one clock
cycle before it was detected, as indicated by the shaded
portion. The center of the start bit is defined as clock 'count
7'1;2. If the receiver clock is a symmetrical square wave, the
center of the start bit will be located within ± 112 clock cycle,
± 1/32 bit or ±3.125%. The receiver begins searching fOr
the next start bit at the center of the first stop bit.

I

FE
A

---

B

CLOCK
_ 1 CLOCK
CYCLE

--rn

C

RRIINPUT

WF009601

I..

Figure 9: Receiver Timing (Not to Scale)

14.

COUNT
"-=-- CENTER
OF

71/2
DEFINED

START

START BIT

71/2 CLOCK CYCLES---j
81/2 CLOCK CVCLES----!
WF009701

A low level on DRReset clears the DReadyline. During
the first stop bit, data is transferred from the receiver
register to the RBRegister. If the word is less than' 8 bits, 'the
unused most significant bits will be a logic low.' The output
character is right justified to the least significant bit RBR1. A
logic high on DError indicates an overrun which occurs
when DReady has not been cleared before the present
character was transferred to the RBRegister. A logic high
on PError indicates a parity. error. 1/2 clock cycle later,
DReady is set to a logic high and FError is evaluated, A

Figure 10: Start Bit Timing

TYPICAL APPLICATION
Microprocessor systems, which are inherently parallel in
nature, often require an asynchronous serial interface. This
function can be performed easily with the IM6402/03
UART. Figure 11 shows how the IM6402 can be interfaced
to an IM80C48 microcomputer system.
9-23 ,

Note: All typical values have been guaranteed by characterization and are not tested.

i IM6402/IM6403
I

I

assure that a slow rising capacitor voltage does not retrigger RESET. A long reset pulse after power-up (-20ms)
is required by the processor to assure that the on-board
crystal oscillator has sufficient time to start.

I

If parity is not inhibited, a parity error will cause the PE pin
to go high until the next valid character is received.

In this example the characters to be received or transmit...... ted will be eight bits long (ClS 1 and 2: both HIGH) and
(II
transmitted with no parity (PI:HIGH) and two stop bits
(SBS:HIGH). Since these. control bits will not be changed
_ during operation, Control Register load (CRl) can be tied
high. Remember, since the IM6402/03 is a CMOS device,
all unused inputs should be tied to either VOO or VSS
The baud rate at which the transmitter and receiver will
operate is determined by the IM4702 Baud Rate Generator.
To ensure consistent and correct operation, the IM64021
'03 must be reset after power-up. The Master Reset (MR)
pin is active high, and can be driven reliably from a Schmitt
trigger inverter and R-C delay: hi this example, the IM80C48
is reset through still another inverter. The Schmitt trigger
between the processor and R-C network is needed to

A framing error is generated when an expected stop bit is
not received. FE will stay high after the error until the next
complete character's stop bit is received.
The overrun error flag is set if a received character is
transferred to the RECEIVER BUFFER REGISTER when
the previous character has not been read. The OE pin will
stay high until the nex1 received stop bit after a DRR is
performed.

XTAL

l-

XTAL

eo
+5

t il i t
~r---~------------------~ SFD

CLIo

+5

CAL

+5

WRr---f:,-------------I TiRL
TBRE

IMIOC48

TRO

DR

i>" 1-----,"----------4_-1 iiiiii
RRD

+5
2
22IIK

•

TBR, ..

•

RBR,..
MR

1RRI

TRANSMIT
DATA

RECEIVE
DATA

10,.1
...
OS028301

Figure 11: IM80C48 Interface to IM6402

9-24
Note: All typical values have been guaranteed by characterization and are' not tested:

IM6653/IM6654
4096-Bit CMOS UV EPROM
GENERAL DESCRIPTION

FEATURES

The Intersil IM6653 and IM6654 are fully decoded 4096
bit. CMOS electrically programmable ROMs (EPROMs)
fabricated with Intersil's advanced CMOS processing technology. In all static states these devices exhibit the microwatt power dissipation typical of CMOS. Inputs and threestate outputs are TTL compatible and allow for direct
interface with common system bus structures. On-chip
address registers and chip select functions simplify system
interfacing requirements.
The IM6653 and IM6654 are specifically designed for
program development applications where rapid turn-around
for program changes is required. The devices may be
erased by exposing their transparent lids to ultra-violet light,
and then re-programmed.

•

.Organization -

•
•

Low Power High Speed
- 300ns 10V Access Time For IM6653/54 AI
- 450ns 5V Access Time For IM6653/54-1I
Single + 5V Supply Operation
UV Erasable
Synchronous Operation For Low Power
Dissipation
Three-State Outputs and Chip Select for Easy
System Expansion

•
•
•
•

IM6653: 1024 x 4
IM6654: 512 x 8
770fJ.W Maximum Standby

ORDERING INFORMATION
PART
NUMBER

TEMPERATURE
RANGE

PACKAGE

IM6653/41JG

-40 c C to +85 c C

24-Pin CERDIP

IM6653/4-1IJG

-40 c C to + 85 c C

24-Pin CERDIP

IM6653/4AIJG

-40 c C to + 85 c C

24-Pin CERDIP

IM6653/4MJG*

-55 c C to +125 c C

24-Pin CERDIP

IM6653/ 4AMJG *

-55 c C

24-Pin CERDIP

to +

125 c C

• Add /HR for HiRel processing

..
.
A,

A,
A,

E,

A,

.
A,

A,

.,
V..

PROGRAM

AS

..

Vee

A,
A,

E,

A,

vc•

A,

PROGRAM

..

a.

COO0551I

COOO56l1

80002411

Figure 1: Functional Diagram

Figure 2: Pin. Configurations.

9-25
Note: All typical values have been guaranteed by characterization and are not tested.

002

!

-I
I

-

I"'S853/IM,86!S4

ABSOLUTE MAXIMUM RATINGS (IM6653/54 I, -11, M)

Supply Voltages
,
voo-vss ................................. : ... : ..... +8.0V
vee-vss ........................................ : •. +8.0V
Input or Output Voltage .... (Vss -O.3V) to (Voo +O.3V)

Operating Range Range (TAl
Industrial. .............................. -40·C to +85'C
Military ............................... -55'C to + 125'C
Storage Temperature Range ............ -65'C to + 150'C
Lead Temperature (Soldering, 10sec) ................. 300·C

NOTE: Stresses above those Usted under Absolute Maximum Ratings may cause permanent damage tothe de~ce. These are stress ratings only. and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the specHications is not implied.
Exposure'to absolute maximum rating conditions for extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS
(Vee = VOO = 5V ±10% VSS = OV, TA = Operating Temperature Range)
SYMBOL

PARAMETER
Logical "1" Input Voltage

VIH
VIH

JM6653/541, -11, M

TEST
CONDITIONS

UNIT
MIN

MAX

~1. S

Voo-2.0

Address Pins

2.7

V

0.8

Logical "0" Input Voltage

VIL

GND ~ VIN ~ Voo

'-1.0

VOH

Logical "1" Output Voltage

IOH- -0.2mA

2.4

VOL
IOLK

Logical "0" Output Voltage

IOL=2.0mA

Output Leakage

ISTBY

Standby Supply Current

VIN=VOO

100
40

Operating Supply Current (1)

VIN =VOO
f-1MHz

Input Leakage

II

1.0

IlA

V
GND~VO~Vcc

Icc
100

0.45
-1.0

1.0

p.A

6

CI

Input Capacitance

Note 1

7.0

Co

Output CapaCitance

Note l'

10.0

rnA
pF

Note: 1. For design reference only, not 100% tested.

AC ELECTRICAL CHARACTERISTICS
(Vee = Voo

= 5V

SYMBOL

±10% Vss

= OV,

CL = 50pf, TA = Operating Temperature Range)
IM6653/54-1I

IM6653/54 I

IIM6653/54 M

MIN

MIN

MIN

PARAMETER

UNIT
MAX

MAX

MAX

TEILOV

Access 'Time From ~ 1

450

550

TSLOV·

Output Enable Time

110

140

150

TE1HOZ

Output Disable Time

110

140

150

TE1HE1L

~1 Pulse Width (POSitive)

130

150

150

TE1LE1H

E1 Pulse Width (Negative)

450

550

600

TAVEIL

Address Setup Time

0

0

0
100

600

TE1 LAX

Address Hold Time

80

100

TE2VE1L

Chip Enable Setup Time (6654)

0

0

0

TE1LE2X

Chip Enable Hold Time (6654)

80

100

100

9-26
Note: All typical values h,ave bee,n guaranteed by characterization and are not tested.

ns

IM6653/IM6654

i0)

ABSOLUTE MAXIMUM RATINGS (IM6653/54AI, AM)

,Co)

0)

Supply Voltages
Voo '-vss ............. · ........ · ........ · ..... · ... + 11.0V
Vee-Vss ......................................... +11.0V
Input or Output Voltage .... (Vss -O.3V) to (Voo +O.3V)

CIt

......

Operating Temperature Range
Industrial ............................... -40°C to + 85°C
Military ............................... -55°C to + 125°C
Storage Temperature Range ............ -65°C to + 150°C
Lead Temperature (Soldering. 10sec) ................. 300°C

NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS
= Voo = 4.5V to 10.5V Vss = OV. TA = Operational Temperature Range)

(Vee

IM6653/54AI. AM
SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
MIN

VIH

logical "1" Input Voltage

Vil
II
VOH

1:1•

S

Voo-2.0

Address Pins

VIH

MAX
V

VOO-2.0

Logical "0" Input Voltage

0.8

Input leakage

GND S VIN S Voo

logical "I" Output Voltage

lOUT

VOL

logical "0" Output Voltage

IOlK

Output Leakage

ISTBY

Standby Supply Current

a (Note
lOUT ~ a (Note
~

-1.0

1)
1)

-1.0

VSS S Vo SVCC
VIN

I'A

Vss + 0.01

V

1.0

~VOO

!1A

100

VIN ~VOO

ICC

1.0

Vee-om

40

lob

Operating Supply Current

f~IMHz

12

CI

Input Capacitance

Note 1

7.0

Co

Output Capacitance

Note 1

10.0

mA
pF

Note: 1. For design reference only. not 100% tested,

AC ELECTRICAL CHARACTER1STICS
(Vee = Voo = 10V ±5% Vss '" OV. CL = 50pf. TA = Operating Temperature Range)
IM6653/54 AI
SYMBOL

IM6653/54 AM

PARAMETER

UNIT
MIN

MAX

MIN

MAX

TEllQV

Access Time From El

300

350

TSLQV

Output Enable Time

60

70

TE1 HQZ

Output Disable Time

60

TE1HEll

1:1 Pulse Width (Positive)

125

125

TEllE1H

1:1 Pulse Width (Negative)

300

350

TAVEll

Address Setup Time

a

0
60

70

TEl LAX

Address Hold Time

60

TE2VEll

Chip Enable Setup Time (6654)

0

a

TE1LE2X

Chip Enable Hold Time (6654)

60

60

9-27
Note: All typical values have been guaranteed by characterization and are not tested. ,.

ns

i0)

,d)

:

.
In

IM6853/IM6654

2

PIN ASSIGNMENTS

co
co

::::.
C')
In

CO
CO

!

PIN

SYMBOL

1-8,23

Ao-A7,Ae

9-11, 13-17

00-07
00-03

12
18

VSS
Program

19

VDD

20
21

E1
S

22

~g

.•U~OIl
ACTIVE
LEVEL
Data Out lines, 6654
Data Out lines, 6653
Negative Supply
Programming pulse input
Chip positive supply, normally tied to VCC

E2

24

DESCRIPTION
Address Unes

L

Strobe line, latches both address lines and, for 6654, Chip enable E2

L

Chip select line, must be low for valid data out

L

Additional address line for 6653
Chip enable line, latched by Chip enable E1 on 6654
Output buffer positive supply

VCC

READ MODE OPERATION
In a typical READ operation address lines and chip
enable E2· are latched by the falling edge of chip enable E1
(T = 0). Valid data appears at the outputs one access time
(TElQV) later, provided level-sensitive chip select line S is
low (T = 3). Data remains valid until either E1 or S returns to
a high level (T = 4). Outputs are then forced to a high-Z
state.
Address lines and E2 must be valid one setup time before
(TAVEL), and one hold time after (TElAX), the falling edge
of E1 starting the read cycle. Before becoming valid, Q
output lines become active (T = 2). The Q output lines
return to a high-Z state one output disable time (TE1 HQZ)
after any rising edge on 1:1 or S.
.
The program line remains high throughout the READ
cycle.

-At 1Me8&3 only. it ...... only

Chip enable line E1 must remain high one minimum
positive pulse width (TEHEl) before the next cycle can
begin.

WFOO9801

Figure 3: Read Cycle Timing

FUNCTION TABLE
INPUTS

TIME
REF

E1

E2

5

A

OUTPUTS
Q

-1

H

X

X

X

Z

DEVICE INACTIVE

0

-"-

L

X

V

Z

CYCLE BEGINS; ADDRESSES, E2 LATCHED·

1

L

X

X

X

Z

INTERNAL OPERATIONS ONLY

2

L

X

L

X

A

OUTPUTS ACTIVE UNDER CONTROL OF E1, S

3

L

X

L

X

V

OUTPUTS VALID AFTER ACCESS TIME

4

_F

X

L

X

V

READ COMPLETE

5

H

X

X

X

Z

CYCLE ENDS (SAME AS -1)

NOTES

9-28
Note: All typical values have been guaranteed by characterization and are not tellted.

IM6653/IM6654

r.

t----tEl<

-:==:::::

+

....

--~

I-TPlPH ....I

.-----------------------1
-----IlEAD-----_.I. .
1...

u-,-

~ ------t~

DATAOUT}

\~_____________
.I_.____

- - - - P R O G R A M - -_ _

READ_---_

WFOO9901

Figure 4: Read and Program Cycle Timing

DC CHARACTERISTICS FOR PROGRAMMING OPERATION
(Vee = VOO = 5V ±5% VSS = OV, TA = 25°C)

SYMBOL

PARAMETER

IpROG

Program Pin Load Current

VPROG

Programming Pulse Amplitude

IcC

Vee Current

IDD

VDD Current

VIHA

Address Input High Voltage

VILA

Address Input Low Voltage

VIH

Data Input High Voltage

VIL

Data Input Low Voltage

TEST
CONDITIONS

MIN
-38

TYP

MAX

UNIT

80

100

mA

-40

-42

V

0.1

5

40

100

mA

VDD-2.0
0.8
V

VDD-2.0
0.8

AC CHARACTERISTICS FOR PROGRAMMING OPERATION
(Vee = Voo = 5V ±5% Vss = OV, TA = 25°)

SYMBOL
TPLPH

PARAMETER
Program Pulse Width

TEST
CONDITIONS

MIN

TYP

MAX

UNIT

tose = tlaU = 51's

18

20

22

ms

Program Pulse Duty Cycle

75%

TDVPL

Data Setup Time

TPHDX

Data Hold Time

TE1HE1L

Strobe Pulse Width

TAVEIL

Address Setup Time

0

TE1LE1 X

Address Hold Time

100

TE1LQV

Access Time

9
9

I'S

150
ns
1000

be set at Voo -2V minimum. Low logic levels must be set
at Vss + O.BV maximum. Addressing of the desired location
in PROGRAM mode is done as in the READ mode. Address
and data lines are set at the desired logiC levels, and
PROGRAM and chip select (8) pins are set high. The
address is latched by the downward edge on the strobe line
(E1). During valid DATA IN time, the PROGRAM pin is
pulsed from VDO to -40V. This pulse initiates the program-

PROGRAM MODE OPERATION
Initially, all 4096 bits of the EPROM are in the logiC one
(output high) state. Selective programming of proper bit
locations to "O"s is performed electrically.
In the PROGRAM mode for all EPROMs, Vee and Voo
are tied together to a + 5V operating supply. High logic
levels at all of the appropriate chip inputs and outputs must
9-29

Note: All typical values have been guaranteed by characteriiation and are not tested.

: IM6853/1M8854

I

:::::.

:g'"
In

!

ming of the device to the levels set on the data outputs.
Duty cycle limitations are specified from chip heat dissipation considerations. PULSE RISE AND FALL TIMES MUST
NOT BE FASTER THAN 5j.Ls.

3.

Intelligent programmer equipment with successive
REAO/PROGRAM/VERIFY sequences is recommended.

4.

ERASING PROCEDURE

PROGRAMMING SYSTEM
CHARACTERISTICS
1.

During programming the power supply should be
capable of limiting peak instantaneous current to
100mA.

2.

The programming pin is driven from VOO to -40
volts (±2V) by pulses of 20 milliseconds duration.
These pulses should be applied in the sequence
shown in the flow chart. Pulse rise and fall times of
10 microseconds are recommended. Note that any
individual location may be progr~mmed at any time.

Addresses and data should be presented to the
device within the recommended setup/hold time
and high/low logic level margins. Both "A" (10V)
and non "A" EPROMs are programmed at Vee.
Voo of 5V ±5%.
Programming is to be done at room temperature.

The IM6653/54 are erased by exposure to high intensity
short-wave ultraviolet light at a wavelength of 2537 A. The
recommended integrated dose (i.e .• 'UV intensity x exposure
time) is 10W sec/cm 2 . The lamps should be used without
short-wave filters. and the IM6653/54 to be erased should
be placed about one inch away from the lamp tubes. For
best results it is recommended that the device remain
inactive for 5 minutes after erasure. before reprogramming.
The erasing effect of UV light is cumulative. Care should
be taken to protect EPROMs from exposure to direct
sunlight or fluorescent lamps radiating UV light in the 2000A
to 4000A range.

9-30

Note: All typical values have been guaranteed by characterization and are not tested.

IM66531lM6654

LD003101

Figure 5: Programming Flow Chart

9-31

Note: All typical values have been guaranteed by characterization and are not· tested:

AF021411

Figure 6: IM6653 CMOS EPROMS as External Program Memory with the IM80C35
••v

-Ii
....J.

0=r=

, osc,

GN.

GN.

b"t
Voo

VS&

P,o
PII
P12
PI3
PI<
PIS
P16

3
OSC2

-If----! iImT
7

E.

~

Vee

--tfi,

P20

21

P21

~

P23

-!-

P25

-!-

IM8OC48

~

8
7

•

:!

*l!...
•

'0
II
13
I<

...... "

.-.! iN'!'

15

"16

. . . 17

16

II

PRoo

AI

AO

IM6654
512 .. ,

080"
081 14

TI

'JftJi

A3

CMOS EPAOM

12

TO

ALE

.7
'8
AS

·...,
3

P24~
P28

INPU{

23

....g..

Ii

Wii ii6

v"

v"

, '8
,
,

"
~
-¥.-l!-

~
.a

P27

..-.+

?

017

L

h"

Vee

~

17

087 "

I' I" 1 I'

00
0'
0'
03
O.
O.
O.
07

E,

lI"

E,

I" I"

10

20

lSOO1001

Figure 7: Using IM6654 CMOS EPROM To Extend Program Memory

9-32
Note: All typical values have been guaranteed by characterization and are not. tesled.

IM80C48/49/35/39
CMOS Microcontroller
GENERAL DESCRIPTION

FEATURES

The IntersillM80C48 family of CMOS microcontrollers
combines the speed of the industry standard NMOS8048
with the low power consumption of CMOS. In addition to the
low operating current, the IM80C48 family has three versatile power-down modes that reduce power dissipation even
further. The HALT mode, entered by software command,
shuts down selected portions of the CPU to reduce power
;, consumption while retaining rapid response time to an
interrupt or reset. The STandBY and STOP modes shut
. down all but the onboard RAM, reducing the supply current
to typically 1 microamp.
The IM80C48 family microcontrollers include 27 I/O
lines, RAM, and an 8-bit timer/counter on-chip, and are well
suited for control applications. The low power consumption
, of the IM80C48 makes it particularly desirable in applications that require battery operation or long term battery
backup of on-Chip RAM during AC power interruptions.

•
•
•

•
•
•

Industry Standard NMOS 8048 Family Compatible
Expanded Instruction Set Includes Software
STandBY
Ultra Low Power Consumption
- Operating Supply Current: 3mA at 6MHz
-IDLe Supply Current: 8001lA at 6MHz
-STandBY and STOP Modes: 1j.LA
Wide Operating Voltage Range - 3.5V to 6V
Compatible with 8048/80/85 Peripherals
4 Standard ROM and ROM-Less Versions

APPLICATIONS
•
•
•
•

Portable Instrumentation
Telecom
Industrial Control
Battery Operated Equipment

ORDERING INFORMATION
INTERNAL
MEMORY

SUFFIX
BASIC
PART NUMBER

TEMP. RANGE:
O°C to +70°C

TEMP. RANGE:
-40°C to +85°C

ROM

RAM

40-PIN
PLASTIC

40-PIN
CERDIP

40·PIN
PLASTIC

40,PIN
CERDIP

IM80C48

CPL

CJL

IPL

IJL

1K x 8

IM80,C49

CPL

CJL

IPL

IJL

2K

IM80C35

CPL

CJL

IPL

IJL

NONE

64 x 8

IM80C39

CPL

CJL

IPL

IJL

NONE

128

ALE
)(TAL>
)(TAL>

+"'"------------,
_L.r----'
. . ._ _.....

~

TO - - ' - - - - - - -

POWER { Vee
40
SUPPLY
Vss ..:20~_ _...

12-19
DBO-DB7

21-24,35-38
P20-P27

27-34
P10-P17

Figure 1: Functional Diagram

9-33
Note: All tvoical values have been Quaranteed bv characterization and are not tested.

x

8

64
128

x8
x8
x

8

--=

IM80C-4e/4$135/3.9

10

(I')

I
~

!

ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin ............ (VSS-0.3V) to (Vee+0.3V)
Supply Voltage ................................ (Vee - VSS) + 8V
Storage Temperature (Plastic) .......... -65°C to + 150°C

Operating Temperature Range:
IM80CXXCXL ............................ O·C to + 70°C
IM80CXXIXL ................. ., ....... -40°C to +85°C
Lead Temperature (Soldering, 10see) ................. 300°C

Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
Test Conditions: Vce = 5V± 10% Vss = OV, TA = -40°C to + 85°C
LIMITS
SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
MIN

TYP

MAX

VIL

Input Low Voltage
(All Except XTAL1)

VILI

Input Low Voltage
XTALI

VIH

Input High vOI~ge
(All Except RE ET, XTAL1,
Voo/STOP)

VIHI

R S

VOL

Output Low Voltage

IOL=2mA

VOH

Output High V~I~N
BUS, ~, ~,
, ALE

IOH = -100pA

2.4

V

VOHI

Output High Voltage
All Other Outputs

IOH = -50pA

2.4

V

IILP

Input Pullup Current
Port I, Port 2

VIN S VIL

-150

-300

IJ.A

IlL

!!!!lut P~IUP Current
SS, RE ET

VIN SVIL

-20

-40

pA

IlL

Input Le~e Current
Tl, EA, IN

VsssVee

0

±1

pA

IOL

Output Leakage Current
Bus, TO-High Impedance

Vss S VIN S Vcc

0

±1

pA

ICC

Total Supply Current

TA = 25'C, 6MHz

3

8

rnA

0.8

2.0

rnA

1

20

pA

-0.3

Vec-2V

In~uk~i9h Voltage

Vee- 0.5V

,XTAL1, XTAL2, Voo/STOP

ICCI

IDLE Power Supply Current

6MHz.

ICC2

STandBY and STOP Modes Supply Current

VIN = Vcc

0.8

V

Vee- 0.8

V

Vce

V

Vee

V

0.45

V

AC CHARACTERISTICS
PORT 2 TIMING
Test Conditions: Vec = 5V±10% Vss = OV, TA
PARAMETER

SYMBOL

= -40°C

to + 85°C, fCLK = 6MHz
LIMITS

TEST CONDITIONS

(Note 1)

UNIT
MIN

TYP

MAX

tcp

Port Control Setup Before Falling
Edge of ,PROG

110

nS

tpc

Port Control Hold after Falling
Edge of~

140

nS

j5RQG to Time Port 2 Input Dat,a

810

nS

IpR

must be valid

top

Output Data Setup Time

220

tpo

Output Data Hold Time

65

tpF

Input Data Hold Time

0

tpp

j5RQG Pulse Width

1200

ns

tPL

Port 2 I/O Data Setup

350

ns

tLP

Port 2 I/O Data Hold

150

ns

Note 1: Inputs are driven to 0.45V and 2.4V. Output timing measurements are made at 0.8V and 2.0V.
9-34
Note: All typical values have been guaranteed by characterization and are not tested.

ns
ns
150

ns

IM80C48/49/35/39
READ, WRITE AND INSTRUCTION FETCH - EXTERNAL DATA AND PROGRAM MEMORY
Test Conditions: Vcc

= 5V±10%

Vss

= OV,

TA = -40·C to + 85·C, fCLK

LIMITS

TEST CONDITIONS

PARAMETER

SYMBOL

= 6MHz

(Note 1)

UNIT
MIN

TYP

MAX

tLL

ALE Pulse Width

400

ns

tAL

Address Setup before ALE Falling

120

ns

tLA

Address Hold from ALE Falling

BO

ns

tcc

Control Pulse Width (PSEN, RD, WR)

700

ns

tow

Data Setup before WR Rising
Data Hold after WR Rising

500

ns

two

Icv

Cycle Time

tOR

Data Hold

tRO

~,

tAW

Address Setup before

tAD
tAFC

Address Setup before Data in
Address Float to RD, ~

RD

CL = 20pF

ns

120
2.5

150

0
to Data in Valid

WR

200

IlS
ns

500

ns

230

ns
950

0

ns
ns

Note 1: For Control Outputs CL = BOpF, for Bus Outputs CL = 150pF. Inputs are driven to 0.45V and 2.4V. Output timing measurements are made
at O.BV and 2.0V.

ROM CODE DATA ENTRY
Intersil can accept customer ROM codes in a variety of
media, including standard byte-wide EPROMs (2176, 2732,
2764, 27C16, 27C32, etc,) or (8048, 8748, 8049, 8749)
microcomputers.
Contact GE-Intersil sales office for other formats.
EnF.RNAl
ACCESS

--+

ROM CODE VERIFICATION (IM80C48/49)

IM80C4a
IM80C3S
!~80CG9

The IM80C48/49 ROM code can be verified by applying
negative 5V to the EA pin while RESET is low. The address
is then applied to DBO-DB7 and P20-P22. Bringing RESET
high will internally latch the address and cause the ROM
content for that address to appear on DBO-DB7, This verify
cycle can then be repeated by returning RESET low and
applying the next address to DBO-DB7 and P20-P22; then
bringing RESET high to read the ROM content. To exit the
verify mode first set RESET low then return EA to OV.

IMMe39

LSOOO701

Figure 3: Logic Symbol

ALE

EXPANDER

PORT

PCH

OUTPUT

EXPANDER

PORT
INPUT

PCH

---,pp---WF02280!

Figure 4: Port 2 Timing

9-35
Note: All typical values have been guaranteed by characterization and are not tested.

:1 IM80C48/49/35/39

-:;n
f)

I

~-B_ICY_~

!

WF02291I

Figure 5: Read From External Data Memory

BUS~~.
WF02301I

Figure 6:. Write to External Data Memory

ALE

!----------ICY--------.j
WF02311I

Figure 7: Instruction Fetch From External Program Memory

9-36
Note: All typical values have been guaranteed by characterization and are .not tested.

IM80C48/49/35/39
sv

REm
ov
ov

EA
-sv
SV
DBO-DB7
OV
SV
P20-22
OV

-------'"
\

,------

I

~---I~'--------~/

(

I

ADDRESS

)(~__________________D_A_TA___________________

{

ADDRESS
WF02321I

Figure 8: Verify Mode Timing
Table 1: Pin Description
PIN
NAME

TO

PIN

FUNCTION

1

An input pin that is tested by the
conditional jump instructions JTO and
JNTO. This pin can be designated as a
clock outplot using the ENTO ClK
instruction.

XTAL1

2

Connected to one side of the crystal
for internal oscillator operation. Also
used as the external clock input when
using an external oscillator.

XTAl2

3

Connected to one side of the crystal
when using the internal oscillator.
leave open when using an external
oscillator.

RESET

4

Active low input used to reset the
microcomputer. A capacitor from this
pin to ground will automatically reset
the device on power-up.

SS

5

Single-Step input, active low, that can
be used in conjunction with ALE to
single-step the processor through
each instruction.

INT

6

INTerrupt input, active low. Initiates an
interrupt if external interrupt is
enabled.

EA

7

External Access input, active high, is
used to force all program memory
accesses to reference external
memory.

RD

8

This output, active low, is used by
external devices to place data onto the
bus during a bus read operation.

~

9

Program Store ENable. This output,
active low, occurs only during fetches
to external program memory. The
system uses this signal to strobe
external program memory.

PIN
NAME

PIN

FUNCTION

WR

10

This output, active low, is used to
strobe data into external devices
during a bus write operation.

ALE

11

Address latch Enable. This output,
active high, occurs once during each
cycle. The falling edge of this timing
signal, is used to strobe the address
bits appearing on the data bus.

DBODB7
(Bus)

VSS
P20P27

12-19 Data Bus. These eight lines form a true
bidirectional port which can store data
as a latched output port or serve as a
non-latching input! output port.
20

Circuit GND potential.

21 -24 Port 2. Identical to Port 1 except that
35-38 P20 - P23 contain the four high-order
program' counter bits during external
program memory fetches. If IM82C43
1/0 Expanders are being used in the
system, they communicate with the
IM80C46 through these four lines.

PROG

25

Output strobe for IM82C43 1/0
Expander.

Voo'

26

Used to select low power hardware
STOP mode.

SiQj5

P10PH

27-34 Port 1. An 8-bit quasi-bidirectional port.
The 110 structl!re on these eight lines
allows each to be used separately as
an input or output.

T1

39

An input pin tested by the conditional
jump instructions, JT1 and JNT1. The
pin can also be programmed as the
input to the counter.

Voo

40

Main power supply.

9--37

Note: All tYPical values have been guaranteed by characterization and are not tested.

:: eIMaOC48/49/35/39

"-!!
'11)

41

•
:co
.......

"
o

CD

!

Table 2. Instruction Set by MnemoniC (Cont.)

Table 2. Instruction Set by Mnemonic
Accumulator
Mnemonic

Subroutine
Description

Add register to A
Add .data. memory to A
Add immediate to A
Add register with carry
Add data memory with'
carry
ADDC A, " data Add immediate with carry
ANl A, R
And register to A
ANl A, @R
And data memory to A
And immediate to A
ANl A, " data
ORl A, R
Or register to A
ORl A, @R
Or data memory to A
Or immediate. to A
ORl A, " data
XRl A, R
Exclusive or register to A
XRl A, @R
Exclusive or data
memory to A
Exclusive or immediate
XRl, A, " data
to A
INC A
Increment A
DEC A
Decrement A
Clear A
ClR A
CPl A
Complement A
DA A
Decimal adjusl A
SWAP A
Swap nibbles of A
Rl A
Rotate' A left
Rotate A left through
RlC A
, carry
Rotate A right
RR A
RRC A
Rotate A right through
carry

ADO A, R
ADO A, '@R
ADD A, II data
ADDC A, R
ADDC A, @R

Input/Output
Mnemonic
IN A, P
OUTl P, A
ANl P, " data
ORl P, " data
INS A, BUS
OUTl BUS, A
ANl BUS, " data
ORL BUS, " data
MDVD A, P
MOVD P, A
ANlD P, A
ORLD P, A

Description
Input port to A
Output A to port
And immediate to port
Or immediate to port
Input BUS to A
Output A to BUS
And immediate to BUS
Or immediate to BUS
Input expander port to A
Output A to expander
port
And A to expander port
'Or A to expander port .

Registers
Mnemonic

Description

INC R
INC @R
DEC R

Increment register
Increment data memory
Decrement register

Branch
Mnemonic

Description

JMP'addr
JMPP @A
DJNZ R, addr
JC addr
JNC addr
JZ addr
JNZ addr
JTO addr
JNTO addr
JTl addr
JNTl add,
JFO add,
JFl add,
JTF addr
JNI addr
JBb addr

Jump unconditional
Jump indirect
Decrement register and
skip
Jump on carry = 1
Jump on carry = 0
' Jump on Z zero
Jump on A not zero
Jump on TO= 1
Jump on TO=O
Jump on T1 = 1
Jump on T1 =0
Jump on FO = 1
Jump on Fl = 1
Jump on timer flag
Jump on INT .. 0
Jump on accumulator bit

....

Mn~monic

Description
Jump to subroutine
Return
Return and restore' status

Bytes

Cycles

1
.1
2
1
1

1
1
2
1
1

CAll addr
RET
RETR

Flags
Mnemonic

Description

2
1
1
2
1
1
2
1
1

2
1
1
2
1
1
2
1
1

ClR
CPl
ClR
CPl
ClR
CPl

Clear carry
Complement carry
Clear flag 0
Complement flag 0
1
Complement flag 1

2

2

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

MOV
MOV
MOV
MOV
MOV
MOV

1
1

1
1

Bytes

Cycles

1
1
2
2
1
1
2
2
1
1

2
2
2
2
2
2
2
2
2
2

1
1

2
2

Bytes . Cycles
1
1
1

1
1
1

Bytes

Cycles

2
1
2

2
2
2

2
2
2
2
2
2
2
2
2
2
2
2

2
2
2
2
2
2
2
2
2
2
2
2
2

2

C
C
FO
FO
Fl
Fl

Data Moves
Mnemonic

Description

A, R
A, @R
A, " data
A, A
@A, A
A " data

Move register to A
Move data memory to A
Move immediate to A
Move A to register
Move A to data memory
Move immediate to
register
MOV @R, " data Move immediate to data
memory
Move PSW to A
MOV A. PSW
MOV PSW, A
Move A ·to PSW
XCH A, R
Exchange. A and register
XCH A, @A
Exchange A and data
memory
XCHD A, @A
Exchange nibble of A
and register
MOVX A. @A
Move external data
memorY to A
MOVX @A, A
Move A to external data
memory
MOVPA, @A
Move to. A from current
page
MOVP3 A, @A
Move to A from page 3

Timer/Collnter
Mnemonic
MOV A. T
MOV T, A
STRT T
STAT CNT
STOP TCNT
EN TCNTI
DIS TCNTI

Control'
Mnemonic

Description
Aead timer/counter
load time, / counter
Start timer
Start counter
Stop timer/counter
Enable timer/counter
interrupt
Disable timer/counter
interrupt

Description

EN I
DIS I
SEl RBO
SEl RB1.
SEl MBO
SEl MBl
ENTO ClK

Enilble external interrupt
Disable external interrupt
Select register bank 0
Select register 'bank 1
Select memory bank 0
Select memory bank 1
Enable clock output on
TO

Mnemonic

Description

NOP
IDl

No operation
low power Mode,OSC.
on
low power Mode, OSC...
off

STBY'

Note: All typical values have baen guaranteed by characterization and are not tested.

.Bytes Cycles·
2
1

1

2
2
2

Bytes

Cycles

1
1
1
1
1
1

1
1
1
1

Bytes

Cycles

1
1
2
1
1
2

1
1
2
1
1
2

2

2

1
1
1
1

1
1
1
1

1

1

1

1

2

1

2

1

2

1

2

Bytes

Cycles

1
1
t
1
1
1

1
1
1

1
1
1

1

1

Bytes

Cycles

1
1
1
1
1
1
1

1
1
1
1
1
1
1

Bytes

Cycles

1
1

1
1

1

1

.D~nlL i

IM80C48/49/35/39

I

Power consumption drops to less than 1mW. Either a
RESET or external INTerrupt will terminate the IDLE mode. _
A RESET will start execution from address OOH. An external INTerrupt will start execution from 03H if iNTerrupt is :
enabled, or start execution from the next sequential instruction following the IDLE instruction if the iNierrupt is UI
disabled.

LOW POWER MODES
The Intersil IM80C48 family incorporates IDLE and
STandBY instructions as well as the hardware STOP mode.
The IDLE instruction, opcode 01 H, operates as shown in
Figure 1. Execution of opcode 01 H disables the internal
clock and timing circuits while leaving the oscillator running.

W
W
CD

OSC RUNS

BUT INTERNAL
CLOCK OISABLED
POWER CONSUMPTION

.1mW

Figure 9: IDLe Mode

CPU

INT EXECUTE

_____IlJlLfL___ .
INTERNAL
CLOCK

HAlT FIF

INT
WF023301

Figure 10: IDLe Mode

9-39
Note: All typical values have been guaranteed by characterization. and are not tested.

= .MaOC4S/49/35/39
:=
.....
:.....
.....

I-

Figure 11 illustrates the STOP mode. To enter the STOP
mode, first take RESET low, then pull Voo/ STOP .Iow. The
STOP mode, like the ·STandBY mode, shuts down the
oscillator and causes the device to draws less than 1pA of
current. To exit the STOP mode, take Voo~~TOP high, wait
for the oscillator to stabilize, then pUll HE T high. Execution starts at address OOOOH.
Since the power consumption of the IM80C48 is directly
proportional to the clock frequency, significant power savings can be achieved by selecting the lowest clock frequency that provides sufficient processing power for the specific
application. For example, while operating with a 32.768kHz

clock, the IM80C48 will typically draw less, than. 2j.1A of'
current.
.
. Figure 13 shows the operation of the STandBY instruction, opcode 63H. This instruction is similar to IDLE except'
that the oscillator is also turned off, reducing current' drain
to less than 1pA. A RESET or INTerrupt will restart the
oscillator and execution will resume after the oscillator startup time,plus a delay of 2-3 instruction cycles that allows the
oscillator to stabilize. The start-up time of the oscillator,
which depends on the operating voltage and the crystal
parameters, is normally 5-50msec. The address at which
execution resumes is the same as for the IDLe instruction.

STOP MODE
osc DISABLED
POWER CONSUMPTION
<1~W

LD010901

Figure 11: STOP Mode

9-40
Note: All typical values have been guaranteed by characterization and are not tested;

IM80C48/49/35/39

osc

OSCSTARTS

JlJ1.___ _

____ fL

INTERNAL
CLOCK

CPU
BUS _ _ _ _1

..._ _ _ __

AORS 00Il0(H)
WF023401

Figure 12: STOP Mode

• IV

GN•

U

.•...
... 1-'
....
a

....

INI'UT
OUTPUT

22

•a

':"

11

.
."
..
»

,.
11

17

Me
LD011001

1-'
1--

....

INPUT

OUTPUT

INPUT

AN.

OUTPUT

Me
LS000811

Figure 14: Stand Alone System

Figure 13: STANDBY Mode

9-41

Note: All typical values have been guaranteed by characterization and are not tested.

IIII80C4'8/4.9/35/39
.. SY

0,.0

b2t!.

Vee VDD VIS'

P'O ~
PII
P1a
P••

OSC.

~

.i

OSC2

,

PIS

iiEiET
€A

Vcc--r! Ii

~

... •
r¥.... r.!!~~

At Vee

-P21
I'U
P23

...

r-;::.:=

P2S

•

INPUT {

~

-

P27

TO

DI3 15

II i

I" "

AU

0,
0•
0.

A,

012 ,.

iHf

Do

...
...
.........

D80 .2
011 13

T'

bT

h-.T
§

P17

Voo

Vee v.. IGIOD

ONO

...

••

-

r-;:==

=
•

Do

0,
0,

-

r-- 0.

...
...
.........

lie ...

EPROM

lit ••

EPROM

A,

A.

A.

0 •• 1
De5 .7
DM II
087 t

8

...

:II

A,

A,

I i,

ViR iiii

I

I ,

In 1·0 It

I

1

i,

I
LSOOO911

Figure 15: IM6653 CMOS EPROMSs As External Program Memory with The IM80C35
-capacitance values dependent on package type

USING IM6654 CMOS EPROM TO EXTEND PROGRAM MEMORY

tlt
-H~

~~
-l~

,

-=-

h.

*"
:~~ ~

'00 ...

..c,

.~

Pl0

P13~

OSC2

P14 .;;-

:::~
li.

.....

P17

..

:~~
::!~

IM8Oc48

'",,{

D86

"

, .,

AO

-..
512.,

·

"

13

:15
011,,"

10
11

00
01

13

02

14

03

OK l'
01718

16
H

!)as

n

3

o• A3
..

CMOS EPROM

otl,.

" '"~:

17

r I" I" I'
PROG

1.1

o

:: 1t
.-....: "
~"...
.--:
RlN

!

::~

Vcc--": 1!

ALE

I.e

.
·..

23

~

L

'n

'"

Wfi Jm

01

'.

I"

r

~

"

"

LSO01001

Figure 16: Using IM6654 CMOS EPROM to Extend Program Memory

9--42

Note: All typical values have been guaranteed by characterization· and are not tested.

IID~DIL iIII

IM80C48/49/35/39

~It

-Co)

CII

Co)

CO

IM8OC48/9

P.OG~-------------4~-------------4---------------4~------------~
AF034601

Figure 17: Using IM82C43 1/0 Expanders, This Five Chip System Has 80 I/O Lines
'Capacitance values dependent on package type

9-43
Note: All typical values have been guaranteed by characterization and are not tested.

:: IM80C48/49/35/39
.....
ID

!!.

:.....

I
!

Table 3: Instruction Summary By Hexadecimal Opcode
HEX

MNEMONIC

HEX

HEX

MNEMONIC

HEX

MNEMONIC

00
01
02
03

30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3Ei
3F

XCHO A,@RO
XCHO A,@Rl
JBl
undefined
CAll (page 1)
DIS TCNTI
JTO
CPl A
undefined
OUTl Pl,A
OUTl P2,A
undefined
.MOVO P4,A
MOVO PS,A
MOVO P6,A
MOVO P7,A

70
71
72
73
74
75
76
78
79.
7A
7B
7C
70
7E
7F

AOOC A,@RO
AOOC A,@Rl
JB3
undefined
CAll (page 3)
ENTO ClK
JFl
RR A
AOOC A,RO
AODC A,Rl
AODC A,R2
AODC A,R3
AODCA,R4
AODC A,RS
AOOC A,R6
AOOC A,R7

AO
Al
A2
A3

05
06
07
08
09
OA
OB
OC
00
OE
OF

NOP
10l
OUTl BUS,A
ADD A,#data
JMP (p~ge 0)
EN I
undefined
DEC A
undefined
INA,Pl
IN A,P2
undefined
MOVO A,P4
MOVO A,P5
MOVO A,P6
MOVO A,P7

AB
AC
AD
AE
AF

MOV @RO,A
MOV @Rl,A
undefined
MOVP A,@A
JMP (page 5)
ClR Fl
undefined
CPl C
MClV RO,A
MOV Rl,A
MOV R2,A
MOV R3,A
MOV R4,A
MOV R5,A
MOV R6,A
MOV R7,A

10
11
12
13
14
lS
16
17
18
19
lA
lB
lC
10
lE
IF

INC @RO
INC@Rl
JBO
AOOC A,#data
CAll (page 0)
DIS I
JFT
INC A
INC RO
INC Rl
INC R2
INC R3
INC R4
INC R5
INC R6
INC R7

40

ORl A,@RO
ORl A,@Rl
MOV A,T
ORl A,#data
JMP (page 2)
STRT CNT
.JNTI
SWAP A
OAl A,RO
ORl A,Rl
ORl A,R2
ORl A,R3
ORl A,R4
ORl A,RS
ORl A,RS
ORl A,R7

80
81
82
83
84
85
86
87
88
89
8A
8B
8C
80
8E
8F

MOVX A,@RO
MOVX A,@Rl
undefined
RET
JMP (page 4)
ClR FO
JNI
undefined
ORl BUS,#data
ORl Pl,#data
ORl P2,#data
undefined
ORlO P4,A
ORlO P5,A
ORLO PS,A
ORlO P7,A

BO
Bl
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BO
BE
BF

MOV @RO,#data
MOV @Rl,#data
JB5
JMPP @A
CPl Fl
CPl Fl
JFO
undefined
MOV RO,#data
MOV Rl,#data
MOV R2,#data
MOV R3, # data
MOV R4,#data
MOV R5,#data
MOV R6, # data
MOV R7,#data

20
21
22
23
24
25
2S
27
28
29
2A
2B
2C
20
2E
2F

XCH A,@RO
XCH A,@Rl
undefined
MOV A,#data
JMP (page 1)
EN TCNTI
JNTO
CLR A
XCH A,RO
XCH A,Rl
XCH A,R2
XCH A,R3
XCH A,R4
XCH A,R5
XCH A,RS
XCH A,R7

50
51
52
53
54
5S
56
57
58
59
5A
SB
5C
50
5E
SF

ANL A,@RO
ANl A,@Rl
JB2
ANl A,#data
CAll (page 2)
STRT T
JT 1
OA A
ANL A,RO
ANl A,Rl
ANl A,R2
ANl A,R3
ANl A,R4
ANl A,RS
ANL A,R6
ANL A,R7

CO
Cl
C2
C3

undefined
undefined
undefined
undefined
JMP (page S)
SEL RBO
JZ
MOV A,PSW
DEC RO
DEC Rl
DEC R2
DEC R3
DEC R4
DEC RS
DEC R6
DEC R7

EO
El
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF

undefined
undefined
undefined
MOVP3 A,@A
JMP (page 7)
SEL MBO '
JNC
RL A
OJNZ RO,addr
OJNZ Rl,addr
OJNZ R2,addr
OJNZ R3,addr
OJNZ R4,addr
OJNZ RS,addr
OJNZ R6,addr
DJNZ R7,addr

60
61
62
63
64
6S
66
67
S8
S9
SA
6B
6C
60
SE
6F

ADD A,@RO
ADD A,@Rl
MOV T,A
STBY
JMP (page 3)
STOP TCNT
undefined
RRC A
ADD A,RO
ADD A,Rl
ADD A,R2
ADD A,R3
ADD A,R4
ADD A,R5
ADD A,R6
ADD A,R7

90
91
92
93
94
9S
96
97
98
99
9A
9B
9C
90
9E
9F

MOVX @RO,A
MOVX @Rl,A
JB4
RETR
CALL (page 4)
CPl FO
JNZ
ClR C
ANL BUS,#data
ANL Pl,#data
ANL P2,#data
undefined
ANLO P4,A
ANLO PS,A
ANLO P6,A
ANLO P7,A

XRl A,@RO
XRL A,@Rl
JB6
XRl A,#data
CAll (page 6)
SEl RBl
undefined
"MOV PSW,A
XRl A,RO
XRl A,Rl
XRl A,R2
XRl A,R3
XRL A,R4
XRl A,RS
XRl A,R6
XRl A,P7

FO
Fl
F2
F3
F4
FS
FS
F7
F8
F9
FA
FB
FC
FO
FE
FF

MOV A,@RO
MOV A,@Rl
JB7
undefined
CAll (page 7)
SEl MBl
JC
RlC A
MOV A,RO
MOV A,Rl
MOV A,R2
MOV A,R3
MOV A,R4
MOV A,RS
MOV A,R6
MOV A,R7

04

41
42
43
44
45
46
47
48
49
4A
4B
4C
40
4E
4F

MNEMONIC

77

C4
CS

C6
C7

C6
C9
CA
CB
CC

CD
CE
CF

DO
01
02
03

D4
05
OS

07
08
09
OA
DB
DC
DO
DE
OF

Note: All typical values have been guaranteed by characterization and are, not tested.

A4
A5
AS
A7
A8
A9

AA

IM82C43
CMOS 1/0 Expander
DESCRIPTION

FEATURES

The Intersil IM82C43 is a CMOS input/output expander
equivalent to the NMOS 8243. It is designed to provide I/O
expansion for the CMOS IM80C48 and NMOS 8048 families
of single-chip microcomputers.
The 24-pin iM82C43 provides four 4-bit bidirectional 1/0
ports: 8048/41 instructions control bidirectional transfers
between thelM82C43 and the 8048 family microcomputers,
and can execute logical ANDIOR operations directly on the
data contained in the IM82C43 ports.

•
•

•
•
•
•
•

8048/41 Compatible I/O Expander
CMOS Pin-For-Pin Replacement for Standard
NMOS 8243
Low Power Dissipation - Maximum 25mW Active
Four 4·8it 1/0 Ports in 24-Pln DIP
Logical ANDIOR Directly to Ports
High Output Drive
Single + 5V Supply

ORDERING INFORMATION
PART NO.

TEMP. RANGE

PACKAGE

IM82C43CJG

O°C to + 70°C

24 PIN CERDIP

IM82C43CPG

O°C to + 70°C

24 PIN PLASTIC

IM82C431JG

-40°C to +85°C

24 PIN CERDIP

IM82C431PG

-40°C to + 85°C

24 PIN PLASTIC

PORT 4

PORTS

PORT 2

PORT 6

PROG

PSO

voo

P40

PSI

P4'

P52

P42

P53

P43

P60

cs

P61

PiiOO

P62

P23

P63

P22

P73

P2'

P72

P20

P71

vss

P70
CD033201

PoRT 7

AF038201

Figure 2: Pin Configuration
(Outline dwgs JG, PG)

Figure 1: Functional Diagram

9-45
Note: All typical values have been guaranteed by characterization and are not tested.

002

§co IM82C43
!

ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Voo - VSS) ............................... + 8V
Voltage on Any Pin ............ (VSS-O.5V) to (VoO+O.5V)
Power Dissipation .............................................. 1W
Operating Temperature (C) ................... O'C to + 70'C
(I) ................. -40'C to + 85'C

Storage Temperature ...................... -65'C to + 150'C
Lead Temperature (Soldering, 10sec) ................. 300·C

NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS (TA = Operating Temperature Range, Voo=5V±10%, Vss = OV)
SYMBOL

PARAMETER

VIL

Input Low Voltage

VIH

Input High Voltage

TEST CONDITIONS

-0.5

Output Low Voltage Ports 4-7
VOL

VoO=4.5

2.0

VOO= 5.S

2.4
0.4
O.B

IOL= 1.6mA

Output High Voltage Ports 4-7

IOH= 3.2mA

VOH2

Output Voltage Port 2

es, PROO

0.4

IOH= 1.6mA

2.B

VIN = VOO to VSS

-10

Supply Current

ISTBY

Standby Current

VIN = 0 or Voo,
All outputs open

~IOL

Sum of all ICL from 16 Outputs

SmA each pin average

·AC ELECTRICAL CHARACTERISTICS
SYMBOL

(TA

= Operating

PARAMETER

1.6

es = Voo,

TEST CONDITIONS

MIN

BOpF Load

tb

Code Valid After

20pF Load

60

Ie

Data Valid Before ~

BOpF Load

140

Icj

Data Valid After ~

20pF Load

20

th

Floating After

tk

PROO

Code Valid Before

PROO

20pF Load

Ie.

es Valid

Ports 4-7 Valid After

tip

Ports ·4-7 Valid Before/After

tacc

Port 2 Valid After PROG

Before/After

p.A

5.0

rnA

100

/lA

80

rnA

PROO
PROO

0

MAX

UNIT

150

ns

SO
100pF Load

PROO

700
0

BOpF Load

9--46
Note: All typical values have been guaranteed by characterization and are not tested.

= OV)

100

700

Negative Pulse Width

tpo

10

Temperature Range, Voo = 5V±10%, Vss

PROO
PROO

ta

V

2.B

WRITE mode,
All outputs open,
tk = 700ns

100

UNIT

O.B

IOL =20mA
Output Low Voltage Port 2

Input Leakage Ports 4-7, Port 2,

MAX

10L= lOrnA

VOH1
IILK

TYP

MIN

650

IM82C43

PORT 2

FLOAT

(WRITE
OPERAnONI

~-----~----~~

PORT 2

(READ
OPERAnONI

PREVIOUS OUTPUT VALID

PORTS 4-7

OUTPUT
VALID

tip

PORTS 4-7

INPUTVAI.ID

WF02950J

AC TEST CONDITIONS
VIH = 2.BV
INPUT RISE AND FALL TIMES: 5ns (10% TO 90%)
INPUT AND OUTPUT TIMING VOLTAGE REFERENCE LEVELS: O.BV AND 2.0V

Figure 3: Timing Diagram

9-47
Note: All typical values have bean guaranteed by characterization and are not tested.

3 IM82C43
Write Modes

iPIN DESCRIPTIONS
Designator

Pin
Number

PROG

7

Strobe input; The falling edge of
PRO~ implies valid address and
control information on P20-P23,
while the rising edge implies valid
data on P20:-P23.

CS

6

Chip select input. When HIGH,
it disables PROG, thus inhibiting
change in output or internal
status.

The device has three niodes. MOVD P,A directly writes
new data into the selected port with old data being lost;
ORLO P,A ORs the new data with the old data and writes it
to the port; and ANLO P,A ANDs new data with old data ancj
writes it to the selected port.
After the designated operation is performed, the data is
latched and directed to the port. The old data remains
latched until the new data is written by the rising edge of
PROG.

Function

P20-P23

8-11

Four bit directional port,
carrying address and control bits
on the falling edge of PROG and
1/0 data on the rising edge of
PROG.

P40-43
P50-P53
P60-P63
P70-P73

2-5
1,21-23
17-20
13-16

Four bit bidirectional 1/0
ports. May be configured for
input, tri-state output (READ
mode) or latched output. Data on
pins P20-23 may be directly
written. ANDed, or' ORed with
previous data.

Vss

12

Circuit ground potential

Voo

24

Posit,ive supply.

Read Mode
The device has one read mode. The command and port
address are latched from port 2 on the high-to-Iow transition
of the PROG pin~ As soon as the read operation and port
address are decoded, the designated port output buffers
are disabled and the input buffers enabled. The read
operation is terminated by the low-to-higt) transition of the
PROG pin. The port selected is switched to the high
impedance state while port 2 is returned to the input mode.
Normally a port will be in an output mode (write) or input
mode (read). The first read of a port, following a mode
change from write to read should be ignored; all following
, reads are valid. This is to allow the external driver on the
port to settle after the first read instruction removes the low
impedance drive from the IM82C43 output. A read of any
port will leave that port in a high impedance state.

1/0 Expansion
The Use ot. a single

IM82C43 with an 8048 or 8021 is
shown in Figure 4. I'f more ports are required, more
IM82C43s can be added as shown in Figure 5. Here, the
upper nibble of, port 2 is used to select one of the
IM82C43s. Two lines could have been decoded but that
would require additional hardware. Assuming that the leftmost IM82C43 chip select is connected to P24, the
instructions to select and de-,select would be:

DETAILED DESCRIPTION,
The IM82C43 has four 4-bit 1/0 ports, which are ad, dressed as, Ports 4 thru 7 by the processor. The following
operations may be performed on these ports:
• Transfer accumulatqr to pol1 (write)
• Transfer port to accumulator (read)
• AND accumulator to port
'. OR accumulator to port
All communication between the microcomputer and the
IM82C43 occurs over Port 2 (P20-P23) with timing provided
by an output pulse on the PROG pin of the processor. Each
data transfer consists of two 4-bit nibbles:
• The first contains the port address and command to
the IM82C43. This is latched from Port 2 during the
high-to-Iow transition of PROG and is encoded as
shown in the table on page 3.
• The' second contains the four bits of data
associated with the instruction. The low-to-high
transition of' PROG indicates the presence of data.

P22

0
0

0

1
1

0

1
1

INSTRUCTION
CODE
Read
Write
ORlO
ANlO

P21

P20

0
0

0

1
1

0

1
1

MOV A, #OFFH
OUTl P2, A

Disable All
Send it

Initial application of power to the device forces ports 4, 5,
6, and 7 to the high impedance state, Port 2 will be in an
input state if PROG or CS are high when power is applied.
The first high-to-Iow transition of PROG causes the device
to exit the power-on mode. The power-on sequence is
initiated if VOO drops below one volt.

ADDRESS
CODE
Port
Port
Port
Port

P24 =0
Enable IM82C43

Power On Initialization

Port Address And Command Format
P23

MOV A, #OEFH
OUTl P2, A

4
5
6
7

9-48

Note: All typical values have been guaranteed by characterization and are not tested.

IM82C43
TYPICAL APPLICATIONS

n

cs

-PROG

PROG

8021
OR
8OC4B

P4

4

P5

4

P6

4

P7

4

IM82C43
.A

P20-P23

.

4

v

I/O

>

I/O

110

DATA IN
P2

I/O
v
AF038401

Figure 4: Expander Interface
Nole: The IM82C43 does not have the same quasi-bidirectional port structure as Pl/P2 of the 8048. When a "1" is written to P4-7 of the IM82C43 it is a
"hard 1" (low impedance to + 5V) which cannot be pulled low by an external device. All 4 bits of any port can be switched from output mode to input mode by
executing a dummy read which leaves the port in a high impedance (no pullup or pulldown) state.

4

1M80C48

~~--------------~----------------~----------------+---------------~
AF038301

Figure 5: Using Multiple IM82C43s

9-49
Note: All typical values have been guaranteed by characterization and are not tested.

Section 10 - High Reliability /
Military Products and Ordering
Information

DIE .& WAFER ORDERING INFORMATION

FET, MOSFET, AND DUAL
TRANSISTOR CHIPS
INTRODUCTION
Intersil recognizes the increasing need for transistors and
FETs in die form. To fulfill this need, Intersil offers a full line
of JFETs, MOSFETs, and dual transistors in die form.
Die sales do, however, present some unique problems. In
many cases the chips cannot be guaranteed to the same
electrical speCifications as the packaged part. This is due to
the fact that leakage, noise, AC parameters and temperature testing cannot be tested to the same degree of
accuracy for dice as it can for packaged devices. This is due
to equipment limitations and handling problems.

•

•

PURCHASE OPTIONS

Small Signal Devices

Intersil offers dice which are delivered in a number of
forms:
• Chips which have been electrically probed, inked,
visually inspected and diced.
• Wafers which have been electrically probed, inked,
scribed, and mounted on rings with adhesive tape.
• Wafers which have been electrically probed, inked,
and visually inspected only.

•

•

GENERAL PHYSICAL INFORMATION
•

•

Consult individual product information sheets for
dimensions. Except for the aluminum bonding pads,
the chips are completely covered with vapox (silicon

WAFER
PROCESSING

Chips are available with exact length X width
dimensions plus tolerance (see individual data
sheets). Chip height ranges from .003" to .006".
To facilitate die attaching, chips are gold backed.
Approximate thickness is 1000 angstroms. In
general, dice should be attached to gold, platinum,
or palladium metallization. Thin-film gold, moly-gold
and most of the thick-film metallization materials are
compatible.
All chips have aluminum metallization and aluminum
bonding pads. Typical aluminum thickness is 12,000
angstroms.

QC

ELECTRICAL
INSPECTION

VISUAL
INSPECTION

WAFER
LASSIFICATION
AND
ALLOCATION

QCsample
assembled for

I--+---!~ .pecial testing

BACKUP
AND
BACKMETAL

r - - -

100%
ELECTRICAL
PROBE

dioxide). This minimizes damage to the chip caused
by handling problems.
Dice are 100% tested to D.C, +25°C electrical
specifications, then visually inspected. When wafers
are ordered, dice which fail the electrical test are
inked out.
Generally the minimum size of the die-attaching pad
metallization should be at least 5 mils larger (on
every edge) than the chip dimensions. For example,
a 15 mil chip should be attached on at least a 25
mil pad.

I

.

I
:

....._.,..._..1

when required

WAFERS"

I

QC

VISUAL
INSPECTION

:
I

L _ _ _ _ _ _ .J

PACKING AND SHIPPING
LOO10601

Figure 1: Chip and Wafer Processing Flow Chart

10-1

DIE &'WAFER ORDERING lNFORMATION
RECOMMENDED DICE ASSEMBLY
PROCEDURE

FETS'
Breakdown voltage

CLEANING
Dice supplied in die form do not require cleaning prior to
assembly. Dice supplied in wafer form should be cleaned
after scribing and breaking. Freon TF in a vapor deg~easer
is the preferred cleaning method. However, an alternative is
10 boil the die in TCE for five minutes with a rinse in
isopropyl alcohol for 1·2 minutes.

0-20V

VGS(th)

0-5

rOS(on)

5 !2min.@ VGS = 0 (VGS = 30
MOSFETs)

@

~

@
~

1nA

10 iJA

loSS

100mA max.

gfs

20,000 p.MHOS max.

10(011), IS(oll), IGSS

DIE ATTACH:
The die attach operation should be done under a
gaseous nitrogen ambient atmosphere to prevent oxidation.
A preform should be used if the mounting sur/ace has less
than 50 microinches of gold and the die should be handled
on the edges with tweezers. Die attach tel1)perature should
be between 385°C and 400°C with eutectic visible on three
sides of the die after attachment.

100V max.. @ 1 iJA

Pinch-off voltage

100pA min.
5mV min.

VGS1-VGS2
Electrical testing is guaranteed to a 10% LTPD. AC
parameters such as capitance and switching time
cannot be tested in wafer or dice form.

STANDARD DIE CARRIER PACKAGE
•
•

BONDING:
Thermocompression gold ball or aluminum ultrasonic
bonding may be used. The gold ball should be about 3 times
the diameter of the gold wire. The ball should cover the
bonding pad, but not excessively, or it may short out
surrounding metallization. 1-mil aluminum wire may be used
on most dice, but should not be used if the assembled unit
will be plastic encapsulated.

•
•
•
•
•
•

HANDLING OF DICE:
All dice shown in this catalog are passivated devices and
Intersil warrants that they will meet or exceed published
specifications when handled with the following precautions:
• Dice should be stored in a dry inert-gas
atmosphere.
• Dice should be assembled using normal
semiconductor techniques.
• Dice should be attached in a gaseous nitrogen
spray at a temperature less than 430°C.

•

Easy to handle, store and inventory.
100% electrically probed dice with electrical rejects
removed.
100% visually sorted with mechanical and visual
rejects removed.
Easy visual inspection - dice in carriers, geometry
side up.
Individual compartment for each die.
Carriers usable in customer production area.
Carrier may be storage container for unused dice.
Carriers hold 25, 100, or 400 dice, depending on
die size and quantity ordered.
Part numbers shown in this catalog are for carrier
packaging.

COMPARTMENTED
TRAY

ELECTRICAL TEST LIMITATIONS

DICE

DUAL BIPOLAR TRANSISTORS
LVCEO
BVCBO
BVEBO
hFE
VCE(sat)
ICBO
VBE1-VBE2
IB1-IB2

100V max. @ ";:1 mA
100V max. @ .~1 iJA
100V max. @ ";:10 mA
";:1000 @ ~10 iJA
~10 mV @ ";:10 mA
~100 pA @ ";:100V
~1 mV @ ~10 iJA
~2 nA

CLEAR AMBER COVER

CT006201

Figure 2

10-2

DIE & WAFER ORDERING INFORMATION
OPTIONAL WAFER PACKAGE

SUMMARY

•
•

Of the 14 items specified for the package part, onlyB can
be tested and guaranteed in die form. It is to be noted that
those specifications which cannot be tested in die form can
be sample tested in package form as an indicator of lot
performance. Many of the tests, however, such as capacitance tests, are design parameters.
The above electrical testing is guaranteed to a 10%
LTPD. However, there are occasions where customer
requirements cannot be satisfied by wafer sort testing
alone. While the previously described tests will be done on
a 100% basis, Intersi! recognizes the need for additional
testing to obtain confidence that a particular customer's
needs can be met with a reasonably high yield. Toward this
end Intersi! has instituted a dice sampling plan which is twofold, First, random samples of the dice are packaged and
tested to assure adherence- to the electrical specification.
When required, wafers are identified and wafer identity is
tied to the samples. This tests both the electrical character
of the die and its ability to perform electrically after going
through the high temperature dice attachment stage. Second, more severe testing can be performed on the packaged devices per individual customer needs, When testing
is required other than that called out in the data sheet,
Intersi! issues an ITS number to describe the part. Examples of tighter testing which can be performed on packaged
samples is shown as follows:
FET & DUAL FET PAIRS
1. Leakages to 1 pA (lGSS)
2. ROS(on) to as low as 3 ohms
3. IO(off) to 10 pA
4. lOSS to 1 amp (pulsed)
fS. gfs to 20,000 Ilmho
6. 90S to 1 Ilmho
7. en noise to 5 nVlVRZ at frequencies of 10Hz to
100Hz
8. CMRR to 100dB
9. Ll(VGS1-VGS2)/LlT down to 10llVrC to an LTPD
of 20%
10. gm match to 3%
11. loss match to 3%
TRANSISTOR PAIRS
1. Leakages to as low as 1pA
2. Beta with collector current up to 50mA and as low as
100nA
3. tr up to 500MHz with collector currents in the range
of 101lA to 10mA
4. Noise measurements as low as 5nV / VRZ from
10Hz to 100kHz
5. Ll(VBE1- VBE2)/ LlT to 10IlV JOC to an LTPD of 20%
VISUAL INSPECTION
Individual chips are 100% inspected to MIL-STD-750,
Method 2072 or, as an option, MIL-STD-B83, Level B.
Inspection is done to an LTPD of 20%. As an option, Intersi!
offers S.E.M. capability on all wafers.

100% electrically probed - rejects inked.
10% extra good dice included (no charge) to cover
possible breakage and/or visual rejects.
Preferred for production quantities.
Lowest cost.
Wafer is supplied unscribed.
For wafer package - replace "D" in catalog
number with "W", e.g.: 2N4416/D (2N4416 dice in
carrier) becomes 2N4416/W (2N4416 dice in wafer).

•
•
•
•

FOAM
MYLAR
FILTER PAPER
.~_

..._

FILTER PAPER

CTOO64ot

NOTE:'lntersil reserves the right to improve device geometries and
manufacturing _processes as required. These improvements may
result in slight geometry changes. However, they will not affect the
electrical limits, basic pad layouts or maximum die sizes in this
catalog.

Figure 3

ELECTRICAL TEST CAPABILITY
As an example of how to use the capability chart to see
what Intersil actually guarantees and tests for, on a 100%
basis, compare the 2N4391 in a TO-1 B package to the
2N4391 delivered as a chip
ELECTRICAL
TEST SPEC.

2N4391 IN A
TO-1S

2N4391 CHIP

IGSS @ 25C

100pA max,

100pA max.

BVGSS
10(011) @ 25C

40V min.

40V min.

100pA max.

100pA max.

VGs(forward)

See note 1

IV max.

VGS(oll) or Vp

4V to 10V

4V to 10V

lOSS

50 to 150mA

50 to 150tnA

VOS(on)

O.4V max.

0.4 max.

rOS(on)

30n max.

30n max.

Ciss

14pF max.

Guaranteed by Design

Crss

3.5pF max.

Guaranteed by Design

id

15ns max.

Guaranteed by Design

tr

5ns max.

Guarantee!! by Design

loft

20ns max,

Guaranteed by Design

tf

15ns max.

Guaranteed by Design

NOTE 1. ThIS parameter IS very dependent upon quahty of metahzation to which chip is attached.

10-3

rr.

~

DIE' & WAFER ORDERING INFORMATION
CMOS INTEGRATED CIRCUIT CHIPS
INTRODUCTION

•

In addition to discrete device chips, Intersil also offers a
full line of metal gate CMOS integrated circuits in die form.
Die sales, however, present. some unique problems: In
many cases, chips cannot be guaranteed to the same
electrical specifications as can the packaged parts. This is
because leakage, noise, AC parameters and temperature
testing cannot be guaranteed to the same degree of
accuracy for di.ce as for packaged devices.

•
•
•

Dice are 100% tested to DC electrical
specifications, at 25·C then visually inspected
according to, MIL-STD-883, Method 2010.2, condition
B, with modifications reflecting CMOS requirements.
Bonding pad dimensions are 4.0 x 4.0 mils minimum.
Storage temperature is -40·C to + 150·C.
Guaranteed AQL Levels:
2.0%
Visual
1.0%
functional electrical testing
4.0%
Parametric DC testing

GENERAL PHYSICAL INFORMATION
•

Chips are available with precise length and width
dimensions, ±2 mils in either dimension.
• Chip thickness is 9 to 20 mils, depending on device
type.
• Bonding pad and interconnected material is
aluminum, 10K to 15K A thick.
• Each die surface is protected ,by planar passivation
and additional surface glassivation except for
.bonding pads and scribe lines. The surface
passivation is removed from the bonding pad areas
by anHF etchan1;. bonding pads may appear
discolored at low magnification due to surface
roughness of the aluminum caused by the etchant.

•

WAFER
PROCESSING
~-----VISUAL
INSPECTION

•

OC
ELECTRICAL
INSPECTION

+

CARRIER
LOADING

t

t

WAFER
CLASSIFICATION
& ALLOCATION

SCRIBE
&
FRACTURE

PACKING
&
SHIPPING

100%

100%

ELECTRICAL
PROBE

CLEAN

,
I

+

Ii
'---

+
100%

VISUAL

+
QC

VISUAL

--

QCsampie
assembled for
spec:ial testing
whanrequi.....

I
LOO10701

Figure 4: CMOS Integrated Circuit Chip Processing Flow Chart

10-4

DIE & WAFER ORDERING INFORMATION
RECOMMENDED DICE ASSEMBLY
PROCEDURES

STANDARD DIE CARRIER PACKAGE
•
•

CLEANING
Dice supplied in die form do not require cleaning prior to
assembly. However, if cleaning is desired, dice should be
subjected to freon TF in a vapor degreaser and then vapordried.

•
•

RECOMMENDED HANDLING

•
•
•

Intersil recommends that dice be stored in the vacuumsealed plastic bags which hold the dice carriers. Once
removed from the sealed bags, the dice should be stored in
a dry, inert-gas atmosphere.
Extreme care should be used when handling dice. Both
electrical and visual damage can occur as the result of an
unclean environment or harsh handling techniques.

•
•

DIE ATTACH
The die attach operation should be done under a
gaseous nitrogen ambient atmosphere to prevent oxidization. If a eutectic die attach is used, it is recommended that
a 98% gold/2% silicon preform be used at a die attach
temperature between 385°C and 435°C. If an epoxy die
attach is used, the epoxy cure temperature should not
exceed 150°C. If hermetic packages are used, epoxy die
attach should be carried out with caution so that there will
be no "outgassing" of the epoxy.

Easy to handle, store and inventory.
100% electrically probed with electrical rejects
removed.
100% visually sorted with mechanical and visual
rejects removed.
Easy visual inspection - dice are in carriers,
geometry side up.
Individual compartment for each die.
Carriers usable in customer production area.
Carrier may be used as storage contained for
unused dice.
. Carriers hold 25, 100 or 400 dice, depending on die
size and quantity ordered.
Packing of integrated circuit dice in carriers is
identical to illustration shown earlier for discrete
device, except that IC chips are not available in vial
packs or in wafer form.

CHANGES
Intersi'I reserves the right in improve device geometries
and manufacturing processes without prior notice. Although
these improvements may result in slight geometry changes,
they will not affect dice electrical limits, pad layouts,or
maximum die sizes.

USER RESPON$IBILITY
Written notification of any non-conformance by IntersH of
IntersH's dice specifications must be made within 75 days of
the shipment date of the die to the user. Intersil assumes no
responsibility for the dice after 75 days or after further u~er
processing such as, but not limited to, chip mounting or wire
bonding.

BONDING
Thermocompression gold ball or aluminum ultrasonic
bonding may be used. The wire should be 99.99% pure gold
and the aluminum wire should be 99% aluminum/1 %
silicon. In either case, it is recommended that 1.0 mil wire be
used for normal power circuits.

10-5

HIGH-RELIABILITY/MILITARY·PRODUC1S
100% INTEGRATED CIRCUIT PROCESSING

38510
Per MIL-M-38510
Slash Sheet

Intersil is committed to build and process integrated
circuits for the Military/High-Rei market segments in conformance with MIL-STD-883 and MIL-M-38510. Any customer
drawing which specifies testing as set forth in these
documents will be automatically processed to the latest
revisions of MIL-STD-883 and MIL-M~3851 0, unless specific
requests are made to. the contrary.
.

HI·REL PROCESS OFFERINGS
38510 PRODUCTS
Intersil holds QPU status on a number of JAN MIL-M38510 products as listed herein .. As required by JAN
specifications, these products are fabricated, assembled,
and 100% processed within the United States and are fully
compliant with all the requirements, procedures, and methods as given in MIL-M-38510 Revision F and MIL-STD-883
Revision C.

883B PRODUCTS
The 8838 flow diagram represents product processed in
accordance with Method 5004 and Method 5005 of MILSTD-883 Rev. C, 'Glass 8. Most products listed as /8838
herein are availilble as compliant to paragraph 1.2 of MILSTD-8838 Rev. C while others are available only as noncompliant at this time (Allowances for sale of non-compliant
/8838 products are covered in nOtice 3 of MIL-STD-883
Rev. C). Check with Intersil Custom!lr Service as to the
compliant status of individual product offerings at any point
in time.
.

HR PRODUCTS
The HR flow diagram, newly offered by Intersil, represents high reliability hermetic product utilizing many, but not
necessarily all, of the test methods and requirements of
MIL-STD-883 Rev. C, to be used in high reliability applications where some deviations from Rev. C may be justified
and economic advantages realized. Such product may not
be branded /8838 but may be branded /HA or a special
brand as required as purchase order.

FH'lal Elec.tfleal per Apphcable Device
SpeCification
Static, DynamIC, FunChonal, & SWltchmg

BR PRODUCTS

@25-C
SlatlC @ Mall Operatmg Temperatur.

The 8A flow diagram, newly offered by Intersil, represents hermetic or plastic encapsulated product intended for
application in the computer, industrial, or hi-rei commercial
marketplace. In addition to. 100% burn-in, many other
reliability processing steps are included to enhance quality
levels on shipped parts and to improve long term reliability
characteristics. Such product may be branded /8A or as
required by purchase order.
Contact Product Marketing for availability and pricing on
8838, HA and 8A products not listed here.

SIaliC @ Mm. Operating Temperature

Quahty Conformance Inspection per Method

5005
Group A" Table I, Each lot per Applicable

Device Specification

SUBaR'

-

100% DISCRETE DEVICE PROCESSING

,,
1

·••

- 7
- 8
--I.

•

Intersil also offers several QPL-approved discrete products carrying the JANTX deSignation, which are screened
and qualified to the latest revisions of MIL-STD-750 and
MIL-S-19500.

-11

TEST
Sialic

TEMP
25'C

SIalic

Mall.

Stallc
DynamiC

2S"C

DynamiC

Max.

DynamiC
Func
Func

Mm.lMa-..

M,.
M,.

,.·C

SWitch

,.·C

SWitch
Switch

Max.

M,.

Group B: Table liB, Each Inspection 1..01.
Gl"OIJpC: Table Ill, 3 Mo. Periodic
Group D: Table IV, 6 MOo Periodic

10-6

LTPO

HR (1, 2, 4)
In-House Hi Rei Processing
Flows Performed 100% Unless
Otherwise Noted Applies to
IC's and Hybrids

18838 (1, 2, 4)
Per MIL-STD-883
Rev. C, Class 8
Screening per Method 5004
lracsability to Wafer & 'nspec. Lots

Internal Visual

Method 2010, Condo B

I

I
I

Internal Visual
Method 2010, Cond B

Stabilization Bake
Method 1008, Condo C

I

Stabilization Bake
Method 1006, Condo C

Temperature Cycle
Meth~

I

I

Temperature Cycle
Method 1010. Condo C

Constant Acceleration
Method 2001, Condo E, 30 k.g

I

I

Constant Acceleration
Method 2001, Condo E, 30 kg

Hermeticity
Fine & Gross, Method 1014

I

I

Hermeticity

Fine & Gross, MethOd 1014

Initial (Pre-B.!.) Elec. Parameters per
Applicable Device Specification

I

I

Initial (Pre-a.L) Elee Parameters per

Burn-In Test
160Hrs. Min., TA = -t12Sacor Equiv.

Applicable Device Speciitcallon

~

I

I

Burn-In Test

~ ____ •______
M_"h~Ord~lO_15________~

Elec Test/Applicable DevicQ Spec. (3)

I

I

Intenm (Post B.I.) Elee. Parameters
per Applicable Devic;e Specification
5% Defective Allowable (POA) Unless

QA Acceptance Sample per Applicable
Device S~c. (3)

Otherwise Specified.

DC@MaxOC

I

DC@Min"C
Func. @"25OC

Func.·@MinfMaxo
AC@25OC

I

External Visual per Jnste1siJ Spac.

I

QCIData
Group B "" 6 Weeks
Group C .. 12 Months
Group 0 ",·12 Months

Quality Conformance Inspec. per
Method 5005 Group A: Table I,
Ea. Lot per Applicable Oevice Spec
-t

-2
-3
-4
.- 5
-6
-7

-.
-to
-11

tEST
Static
StatIC
Static
Dynamic
Dynamic
DynamiC

TEMP
250C
Male.

Func
Func

250C
Min.lMax
250C
Male.
Mm.

Min.

250C

Ma><.

Mm.

Switch
SWitch
Switch

LTPO .. 5
lTPO = 7
lTPD .. 7
LTPD = 5
LTPD.10
LTPD = 5

DC@2S"C.:

Final Elect. per Applicable Dalliee
Specification, Stalic, Dynamic,
Functional, & SWitchmg@25"C
Stalic@Max.OperatingTemperature
Slatlc@Min.OperatingTemperature

SUBGRP

1010, Condo C

I

LTPD
2

Device Marking
InterSlI Logo
Product Code fHR
a_Code

3
5
2

3
5
2
5
2

3
5

Group B: Tabie liB, Ea. Inspection Lot
Group C' Table III, Twelve Mo. Periodic
Group D. Table IV, Twelve Mo. Periodic

I

External Visual

Method 2009

I

Device Mark./ng
Intersil Logo
Product Code 1883B
Date Code

10-7

BR (1,2)

BI (1,2)

Performed 100%·Unless Otherwise Noted

Performed tOO% Unless Otherwise Noted

APPLIES TO IC'S AND HYBRIDS

APPLIES TO IC'S ANY HYBRIDS' AND TRANSiStORS

\

FOOTNOTES:
(1)

Governing Document, Order of Precedence
A. Purchase Order Contract

e, Detail Specification
C, This Flow
(2)
(3)
(4)

Where test methods are indicated, the test will be performed to MIL-STD-883.
With exception of parameters guaranteed by basic design, not tested.
Does not apply to plastic packages.

(5)

May be performed any time after encapsulation.

(6)

For Plastic 12 Hr. @ 140·C± 10·C.
Weekly Reliability Monitor.
For Plastics-Thermal Shock Method 1011.

(7)
(8)

10-8

.O~OIb
Standard Product (1, 2)

Performed 100% Unless Otherwise Noted
APPLIES TO IC'S AND HYBRIDS AND TRANSISTORS

FOOTNOTES:
(1) Governing Document, Order of Precedence
A. Purchase Order Contract
B. Detail Specification
C. This Flow
(2)

Where test methods are indicated, the test will be performed to MIL-ST0-883.

(3)

With exception of parameters guaranteed by basic design, not tested.

(4)

Does not apply to plastiC packages.
May be performed any time after encapsulation.
For Plastic 12 Hrs @ 140·C ± 10·C.
Weekly Reliability Monitor.
For Plastics-Thermal Shock Method 1011.

(5)

(6)
(7)
(8)

10-9

.D~DIL

High-ReliabilityIMilitary Products
Discrete Products. JA.NTXV, 'JANTX and JAN
Per MIL-S-19500and MIL-STD-750
Performed 100% unless otherwise noted
JANTXV

JAN

10-10

HIGH RELIABILITY PROCESSING
PROCESS FLOW SELECTION GUIDE
-STANDARD IC PROCESS FLOWS38510
JAN
ON-SHORE BUILD
WAFER LOT TRACEABILITY
PRE-CAP VISUAL M2010B
STABILIZATION BAKE
TEMPERATURE CYCLE
CENTRIFUGE
HERMETICITY
ELECTRICAL TEST
BURN-IN
ELECTRICAL TEST
POST BURN-IN PDA
D.C. ELECT. @ 3 TEMPS.
A.C. ELECT. @ 25°C
GROUP A SAMPLE INSPECTION
GROUP B EAC INSP. LOT
STRICT DOCUMENTATION
GROUP C & D INSPECTION

X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
S

883B
REV. C.

X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
S

HR

BR

X
X
X
X
X
X
X

X

X
X
X
S
X
X
X
X

X
X
S

X
S

G

G

m

COMMERCIAL

NOTES

2
X

X
S
S
S

S
S
S

3

X
X
X

X

X

X

5

S

3

3

NOTES:
1. ONLY MAJOR IC PROCESSING DIFFERENCES ARE SHOWN HERE. SEE DETAIL FLOWS ON FOLLOWING PAGES FOR MORE SECIFIC
DATA. CHART IS FOR HERMETIC PACKAGES. ONLY MINIMUM REQUIREMENTS ARE SHOWN. 38510 IS CLASS B.
2. WAFER LOT TRACEABILITY MAINTAINED AND AVAILABLE AT EXTRA CHARGE FOR OTHER PRODUCTS.
3. S = SAMPLE TEST ON REGULAR BASIS.
X = PERFORMED 100%.
G = GENERIC DATA.
4. INTERSIL ALSO OFFERS "SPECIALS" TO SPECIFIC CUSTOMER SCD'S. SPECIALS ARE AVAILABLE WITH ANY OF THE ABOVE
PROCESSING PLUS SEM, PIND, ETC.

HIGH RELIABILITY PROCESSING
PROCESS FLOW SELECTION GUIDE
-STANDARD TRANSISTOR PROCESS FLOWS-

ON-SHORE BUILD
INSPECTION LOT TRACEABILITY
PRE-CAP VISUAL
STABILIZATION BAKE
TEMPERATURE CYCLE
CENTRIFUGE
HERMETICITY
ELECTRICAL TEST
BURN-IN
ELECTRICAL TEST
POST BURN-IN PDA
D.C. ELECT. @ 25°C
A.C. ELECT. @ 25°C
GROUP A
GROUP B EACH INSP. LOT
STRICT DOCUMENTATION
GROUP C INSPECTION

JANTXV
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X
S

JANTX

JAN

X
X
X
X
X

X
X
X

X

X

X
X
X
X
X
X
X
X
X
S

m

CQMMERglAL

NOTES
2

X

X

S
S
S

S
S
S

3

X
X

X
X
X
S
X
S

X
X
X
G

X
X
X
G

3

NOTES:
1. ONLY MAJOR TRANSISTOR PROCESSING DIFFERENCES ARE SHOWN HERE. SEE DETAIL FLOWS ON FOLLOWING PAGES FOR MORE
SPECIFIC DATA. CHART IS FOR HERMETIC PACKAGES. ONLY MINIMUM REQUIREMENTS ARE SHOWN.
2. WAFER LOT TRACEABILITY MAINTAINED AND AVAILABLE AT EXTRA CHARGE FOR OTHER PRODUCTS.
3. S = SAMPLE TEST ON REGULAR BASIS.
X = PERFORMED 100%.
G = GENERIC DATA.
4. INTERSIL ALSO OFFERS "SPECIALS" TO SPECIFIC CUSTOMER SCD'S. SPECIALS ARE AVAILABLE WITH ANY OF THE ABOVE
PROCESSING PLUS SEM, PIND, ETC.

10-11

MIL~STD·883

'REV. C, CLASS B

'"

I

I

GROUP A
ELECTRICAL TESTS

I

SUBGROUP 1

SUBGROUP 3

SUBGROUP 4

SUBGROUPS

SUBGROUP 7

SUBGROUP 9

SUBGROUP 11

STATIC (DC)
TESTS@

25°C

STATIC (DC)
TESTS@
MIN. TEMP.

DYNAMIC
TESTS@
25'C

DYNAMIC
TESTS@
MIN. TEMP.

FUNCTIONAL
TESTS
@25'C

SWITCHING
(AC) TESTS
@25'C

SWITCHING
(AC) TESTS @
MIN. TEMP.

LTPD=2

LTPD=5

LTPD=2

LTPD=5

LTPD=2

LTPD=2

LTPD=5

SUBGROUP 2

SUBGROUP 5

SUBGROUP 9

SUBGROUP 10

STATIC (DC)
TESTS@
MAX. TEMP.

DYNAMIC
TESTS@
MAX. TEMP.

FUNCTIONAL
TESTS@
MAX. & MIN.
TEMPS.

SWITCHING
(AC) TESTS @
MAX. TEMP.

LTPD=3

LTPD=3

LTPD=5

LTPD=3

Notes:

1. The specific parameters to be included for 1ests In each. subgroup shall be specified in the applicable procurement document. Where no parameters have been Identified in a particular subgroup or test within a

2.

~U~~~~~a~p~~: ~et~:~~~~ ~~~i~~~of~~ :::t\~~.b~~~~ ;q~~!d size exceeds the lot size, 100 a)g inspec-

tion shall be allowed.
3. Maximum accept number is 2.

I

GROUP B

I

SUBGROUP 1

SUBGROUP 3

SUBGROUP 5

SUBGROUP 7

METHOD201S
PHYSICAL
DIMENSIONS

METHOD 2003
SOLDERABILITY

METHOD 2011
BOND
STRENGTH

' METHOD 1014
FINE'AND
GROSS LEAK

LTPD=15

LTPD=5

LTPD,,15

OTY=2(O)

SUBGROUP 2

SUBGROUP 4

METHOD 2015
RESISTANCE
TO SOLVENTS

METHOD 2014
INTERNAL VISUAL
AND
MECHANICAL

OTY = 4(0)

OTY = 1(0)

Notes:
1. Required only if package contains a desiccant.
2. Where no LTPD IS shown, OTY

=sample size and f#) =maximum allowed rejects,
10'...12

SUBGROUP 6
[METHOD 1018
INTERNAL
WATER·VAPOR
CONTENT
OTY = 3(0)
• (NOTE 1)

.n~nll

I

GROUP C

I

J

SUBGROUP 1

SUBGROUP 2

METHOD 1005
STEADY STATE
LIFE TEST

METHOD 1010
TEMPERATURE
CYCLING

LTPD=5

METHOD 2001
CONSTANT
ACCELERATION
METHOD 1014
SEAL
LTPD=15

I

GROUP D

I

SUBGROUP 1

SUBGROUP 3

SUBGROUP 5

SUBGROUP 7

METHOD 2016
PHYSICAL
DIMENSIONS

METHOD 1011
THERMAL
SHOCK

METHOD 1009
SA.LT
ATMOSPHERE

METHOD 2025
ADHESION OF
LEAD FINISH

LTPD=15

METHOD 1010
TEMPERATURE
CYCLING

METHOD 1014
SEAL

LTPD=15

LTPD=15

METHOD 1004
MOISTURE
RESISTANCE

SUBGROUP 2
METHOD 2004
LEAD INTEGRITY

METHOD 1014
SEAL
LTPD=15

METHOD 1014
SEAL
LTPD=15

SUBGROUP 4

SUBGROUPS

SUBGROUP 8

METHOD 2002
MECHANICAL
SHOCK

METHOD 1018
INTERNAL
WATER·VAPOR
CONTENT

METHOD 2024
LID TOROUE

METHOD 2007
VARIABLE
FREQUENCY
VIBRATION
METHOD 2001
CONSTANT
ACCELERATION
METHOD 1014
SEAL
LTPD=15

Notes:

1. APplies it package has a Frit·SeaI.
2. Where no LTPD is shown, arv = sample size and (I) = maximum allowed rejects.

10-13

[

OTY = 5(0)

QTY=3(O)
(NOTE 1)

Ordering Information for
MIL-S-19500 Processed Devices
The following Intersil devices are available asa standard Processed
to MIL-S-19500. To order, order by the part number as shown
below:
Part Number
2N3821 JAN
2N3821JTX
2N3821JTXV
2N3823JAN
2N3823JTX
2N3823JTXV
2N4091 JAN
2N4091JTX
2N4091JTXV
2N4092JAN
2N4092JTX
2N4092JTXV
2N4093JAN
2N4093JTX
2N4093JTXV
2N4856JAN
2N4856JTX

MIL-8-19500
Slashsheet
MIL-S-19500/375
MIL-S-19500/375
MIL-S~19500/375

MIL-S-19500/375
MIL-S-19500/375
MIL-S-19500/375
MIL-S-19500/431
MIL-S-19500/431
MIL-S-19500/431
MIL-S-19500/431
MIL-S-19500/431
MIL-S-19500/431
MIL-S-19500/431
MIL-S-19500/431
MIL-S-19500/431
MIL-S-19500/385
MIL-S-19500/385

Part Number
2N4856JTXV
2N4857JAN
2N4857JTX
2N4857JTXV
2N4858JAN
2N4858JTX
2N4858JTXV
2N5114JAN
2N5114JTX
2N5114JTXV
2N5115JAN
2N5115JTX
2N5115JTXV
2N5116JAN
2N5116JTX
2N5116JTXV

MIL-8-19500
Slashsheet
MIL-S-19500/385
MIL-S-19500/385
MIL-S-19500/385
MIL-S-19500/385
MIL-S-19500/385
MIL-S-19500/385
MIL-S-19500/385
MIL-S-19500/476
. MIL-S-19500/476
MIL-S-19500/476
MIL-S-19500/476
MIL-S-19500/476
MIL-S-19500/476
MIL-S-19500/476
MIL-S-19500/476
MIL-S-19500/476

Ordering Information for
MIL-M-38510 Slash Sheet Processed Devices
The following Intersil devices are available as a standard processed
to the 38510 Slash Sheets. To order, use the part number as shown
below:
.
Part Number
JM38510/11101BAC
JM38510/11101BCC
JM38510/11101BIC
JM38510/11102BAC
JM38510/11102BCC
JM38510/11102BIC
'JM3851 0/111 03BAC
JM38510/11103BEC
JM38510/11104BAC
JM38510/11104BEC
JM38510/11105BAC
JMs8510/11105BCC
JM38510/11105BIC
JM3851 0/111 06BAC
JM38510/11106BCC
JM38510/11106BIC
JM38510/11107BAC
JM38510/11107BEC
JM3851 0/111 08BAC
JM3851 0/111 08BEC
JM3851 0/ 12704BVC

Generic NUmber
(DG181AL)
(DG181AP)
(DG181AA)
(DG182AL)
(DG182AP)
(DG182AA)
(DG184AL)
(DG184AP)
(DG185AL)
(DG185AP)
(D~187AL)

(DG187AP)
(DG187AA)
(DG188AL)
(DG188AP)
(DG188AA)
(DG190AL)
(DG190AP)
(DG191AL)
(DG191AP)
(AD7541TD)
10-14

Ordering Information for
DESC Drawing Processed Devices
The following Intersil devices are available as a standard processed
to the DESC Drawings. To order, use the part number as shown
below:
Part Number

Generic Number

Part Number

Generic Number

DESC770S2-01 EB
DESC770S2-01 EX
DESC770S3-01 EB
DESC770S3-01 EX
DESCS1 00S-01 AC
DESCS100S-01AX
DESCS1 00S-01 EB
DESCS1 00S-01 EX
DESCS100S-02AC
DESCS100S-02AX
DESCS100S-02EB
DESCS100S-02EX
DESCS100S-02IC
DESCS100S-02IX
DESCS100S-03AC
DESCS100S-03AX
DESCS100S-03EB
DESCS100S-03EX
DESCS100S-04AC
DESCS100S-04AX
DESCS100S·04EB
DESCS100S·04EX

(IHS10SMJE)
(IHS10SMJE)
(DG201AK)
(DG201AK)
(lHS040MFD)
(IHS040MFD)
(IHS040MJE)
(IHS040MJE)
(IHS041 MFD)
(IHS041 MFD)
(IHS041 MJE)
(IHS041 MJE)
(IHS041 MTW)
(IHS041 MTW)
(IHS042MFD)
(IHS042MFD)
(IHS042MJE)
(IHS042MJE)
(IHS043MFD)
(IHS043MFD)
(IHS043MJE)
(IHS043MJE)

DESCS100S-0SAC
DESCB 1OOS-OSAX
DESCB 1OOS-OSEB
DESCS100S-0SEX
DESCB 1OOS-OSAC
DESCS100S-0SAX
DESCS100S-0SEB
DESCS100S-0SEX
DESCS1 00S-07AC
DESC81 00S-07AX
DESCS100S-07EB
DESCS100S-07EX
DESCS100S-0SAC
DESCS100S-0BAX
DESCS1 OOS~OSEB
DESCS100S-0SEX

(IHS044MFD)
(IHS044MFD)
(IHS044MJE) .
(IHS044MJE)
(IHS04SMFD)
(IHS04SMFD)
(IHS04SMJE)
(IHS04SMJE)
(IHS04SMFD)
(IHS04SMFD)
(IHS04SMJE)
(IHS04SMJE)
(IHS047MFD)
(IHS047MFD)
(IHS047MJE)
(IHS047MJE)

10-15

HIOM 'RELIABILITY PROCESSING
GLOSSARY OF MII,.ITARY/AEROSPACE
HI-REL DEFINITIONS/TERMINOLOGY ..
GROUP B ~ For Integrated Circuits, Package-Related Environmental Tests are performed for Class B. Products per
MIL-STD-883, Method 5005 (For Revision Products) or per
the "HR" program. For Class S, GroupS includes Additional Processing, including steady state life test.

ACCELERATED BURN-IN - Same as ."Burn-In", except
that testing is carried out at an increased temperature
(nominally 150°C) for reduced' ewell' time. Accelerated
testing is not .permissible for .Class·S devices.
ATTRIBUTES DATA - Go-No-Go data. Strictly pass/fail
and number of rejects recorded. A typical requirement for
post burn-in electrical tests on Class B devices.
BASELINE - Technique used to define manufacturing and
test processes at time of order placement. Baselining
usually involves development of a Program Plan and an
Acceptance Test Plan which include flow charts, specification identification/revision letters,.QA procedures; and actual specimens of certain' important specifications. During
subsequent manufacture and testing of parts, it is not
permissible to make revisions or changes to any of the
identified specifications, unless prior notification and possible customer approval occurs.
BURN-IN - A screening' operation. Devices are subjected
to high temperature (typically 125°C) and normal power/
operation for 160 hours (Class B devices) or 240 hours
(Class S devices).
CLASS SAND B INTEGRATED CIRCUITS - These classes set forth the screening, sampling and document control
requirements for IC testing. Terminology is defined in MILM-38510 and in Test Methods 5004 and 5005 of MIL-STD883. Classes, Sand B are sometimes referred to as "Levels
S and B." The Classes cover:
CLASS S - For space and satellite programs.
Includes Condition A Precap, SEM, 240 hour burn-in,
PIND test and elaborate qualification and quality
conformance testing. Normally requires extensive
data, documentation; and program planning.
Formerly referred to as Class A. Class S devices are
quite expensive.
.
CLASS B - For manned flight, and includes most
frequently-procured military integrated circuits. Used
for all but highest reliability requirements. Class B
uses burn-in, pre-cap visual, etc.
CORRECTIVE ACTION - Those actions which a given
supplier (or user) agrees to perform so that a detected
problem does not reoccur.
DESC - Defense Electronic Supply Center, located in
Dayton, Ohio.
DESC LINE CERTIFICATION - The document which approves a supplier's facilities as an appropriate site to
manufacture JAN parts.
DPA - Destructive Physical Analysis. Finished products
are opened and analyzed, in accordance with customer or
MIL Spec criteria.
'

For Diodes and Transistors, both enviromental and life test
are performed per MIL-S-19500.
GROUP C - For Class B or "HR" program I.Co's, DieRelated Tests are performed. Not required for Class S
I.Co's. Group C includes life testing temperature cycling and
constant acceleration per MIL-M-3851 o. For diodes transistors, Group C includes both environmental and life tests per
MIL-l:?-19500.
. .
GROUP D - Additional Package-Related Environmental
Test for I.Co's for Class B or Class S products or per the
"HR" program.
JAN"":'" "Joint Army Navy", a registered trademark of the
U.S. Government. The JAN marking denotes a device
which is in full compliance to MIL-M-38510 or MIL-S-19500.
JAN TX - A JAN-qualified diode or transistor which has
been subjected to additional screening and burn-in tests.
MIL-S-19500 only.
JAN TXV - A JAN-qualified diode or transistor ~hich, in
additional to burn-in testing, has been subjected to additional screening including pre-cap visual inspection, as witnessed by a government source inspector. Equivalent to
Class B screening for integrated circuits. MIL-S-19500 only.

LTPD-Lot Tolerance Percent Defective is a sampling plan
measurement criteria.
MIL-M-38510 - The general military specification for integrated circuits.
M38510/XXX - Detail specifications (or "slash sheets")
for integrated circuits. For example, the 101 specification
covers Operational Amplifiers, with electrical requirements
for the 741, LM101, 108, 747 types, etc.
MIL-S-19500 - The general military specifications for diodes and transistors.
MIL-S-19500/XXX - Detail specifications (or "slash
sheets" for diodes and transistors.
MIL-STD-750 - Specifies Test Methods for diodes and
transistors, such as burn-in, pre-cap, temperature cycling,
etc.
MIL-STD-883 - Specifies Test Methods for integrated circuits, such as pre-cap, burn-in, hermeticity, storage life, etc.
NPFC - Naval Publications and Forms Center,
Philadelphia Printing and distribution source for military
speCifications.

GENERIC DATA - Data pertaining to a device family; not
necessarily the specific part number ordered by the customer, but representative of parts in the family. Group B, C and
D generic data is frequently requested in lieu of the
performance of special qual tests on a given order.
GROUP A - Sample electrical test which are performed on
each lot. Group A is defined in Test Method 5005 for
integrated circuits and in MIL-S-19500 for diodes and
transistors.

NON-STANDARD PARTS-In government terminology,
refers to non-JAN devices. Non-standard parts are typically
covered· by user Source Control Drawings (SCD).
NON-STANDARD PARTS APPROVAL-Approval by the
government (frequently RADC) of non-JAN parts, typically
on source control drawings, for use in a military system or
program. This approval is essentially a waiver which permits
non-JAN 38510 parts in a system which otherwise mandatorially requires JAN parts only.
10-16

HIGH RELIABILITY PROCESSING
OPERATING LlF£ TEST - Same conditions as burn-in,
biJt duration is usually 1000 hours. This is a sample test
, (Qualification and Quality Conformance).
PCA - Parts Configuration' Analysis. A new term which has
mucn the same meaning as "Baseline".
PDA - Percent Defective Allowable. Criteria sometimes
I
applied to burn-in screening. MIL-STD-883 and MIL-M38510 typically require either a 5% or 10% PDA. A 10%
PDA means that if more Uian 10% of that lot fails.aS a result
of burn-in (as determined by pre- and 'post-burn-inelectrical
tests) the entire lot is considered to have failed.
PDS - Parameter Drift Screening. Measures the changes
(4s) in electrical parameters through burn-in. Common for
Class S devices.
'PIND ...... Particle Impact Noise Detection, This is an audio
screening test to locate and eliminate those parts which
'have loose internal particles. The test can isolate a high
percentage of defectives" even in otherwise gooo lots.
,Repeatability of the tests is que~tionable. Th~s test is one of
the screening .items for Class S integrated circuits.,
'PREPARING ACTIVITY ~ The organizational element of
.the government which writes specifications, frequently
RADC.
PRESEAL VISUAL:- A s,eteiming inspection which in,..valves, observation of a die' through a microscope.
,PROCURING' ACTIV1TY- Per MIL-M-38510, this is the
QrganizationaJ element, in ..the government which contracts
fo,r ar:ticles or services. The Procuring Activity can be a
subcontractor (O",M); providing that the government delega~es this respon'sibility. In such a case, the subcontractor.
does' not have the power 'to grant waivers, unless this
authority has been approved by the government.
PRODUCT RELI~BILITY - Pertains to the level of quality
of a product olier a Period of. time. Reliability is usually
measured or expressed in terms of Failure Rate (such as
"0.002% per 1000 hours) or MTBF (mean time between
failure in hours). MTBF is the reciprocal of Failure Rate.
QPL:-Qualified Products l,.ist. In the case of JAN products, QPLs areideritifi~d as QPL"3851 0 for' integrated
"circuits and QPL~1950,Ofordiodes and transistors. QPL"38510 revisions: o.cc'ur approximately quarterlY and QPL,'. 1950Qrevisions obcur approximately annually, In the inter'1m, thE! government wiU notify suppliers via letter of any new
device qualifications which may have" been granted. Two
'types. of QPLs exist for MIL-M-38510:
, PART U QPL - This is an interim or temporary QPL
'which is grante,d on the basis of having obtained line,
'certific,ation aAd approval of, an Application to
Condvct Qualifipation, Testing. A PART II QPL is
automatically Voided after 90 ,days whenever 'any
,',one supplier is granted a PART I QPL.
PART I QPL - A "permlment" QPL, granted after
all' qualification testing is completed and test data is
approved by the government.
QUALIFYING ACTIVITY - Per MIL-M-38510, the organi, zationaf' element in the government which designate,s
, bertificatiorr (i.e., DESC).

,

QUALIFICATION TESTING -Initial one-time sample tests
which are performed to determine whether device types
and processes are good. For integrated circuits, this usually
means testing to Groups A, B, C and D per MIL~STD-883.
For diodes and transistors, this, usually means testirig to
Groups A, Band C per MIL-STD-750.
QUALITY CONFORMANCE TESTING _ These are sample tests which must be performed at prescribed intervals
per MIL-M-3851 0 or MIL-S-19500, assuring that processes
remain in control and that individual lots are passed.
RADC - Rome Air Development Command, Griffiss AFB,
New York. This is the government organization which
created semiconductor specifications; MIL-M-38510 and
MIL-STD,883 were developed at RADC. This Air Force unit
develops specifications for all U.S. military services. RADC
is frequently involved in granting waivers for non-standard
parts for Air Force systems.
READ AND RECORD DATA;- Same as variable data.
REWORK PROVISION - For semiconductor devices, permissible rework of parts is usually limited to re-testing
(screening), re-marking, and cleaning .
SCREENING - Operations which are per(ormed on devices on a 100% .basiS (not ~mpling).Exampres,include
pre-cap visual, burn~in hermeticityi1OO% electrjeaLtest, etc.
SEM INSPECTION -Inspection:by ScarJflingElect/'on Mi~
croscope. Die sampleS are examined at VI~ry high magnification
for metallization ,defects.
,
, , SERIALIZATION - The marking .of a unique part number
on each part, with assigned numbers marked sequentially/
consecutively.
SCDs - Source Control Drawings. Typically user-generated drawings which require development of internal IC
vendor sheets. Although each drawing may be slightly
different, all will be modelled around MIL-M-38510, MIL-S19500, MIL-STD-883, or MIL-STD-750.
SOURCE INSPECTION - Can be either Customer Source
Inspection (CSI) or Government Source Inspection (<3SI).
Source Inspection is initjated via purchAse order, and,can
typically occur at one or more points: '
• ' Pre-cap Visual. Expensive and adds to throughput
time.
• Final Inspection. '
,TRACEABILiTy - A production and manufacturing,COritrol
system which includes: '.
,..."
• Wafer run identification n u m b e r . ' ,
. ' Date pre-cap visu/ifinspection was performed,
Identity of inspedoT""I:\I1d:specification number a"d

revision.

.

. ,: ". ':.

1-, '.

:.,'

' . .Lot' number and inspection histQry.
• QA Group A electricalrE;iSults.
VARIABLE DATA - Read and recorded electrical measurem'ents (parametriC values); Usually, required for pre- and
post-burn-in electrical tests. Also common for Group C and
D testing.
'

....
lQ-,-17

rr:t
Ira!.

PART NUMBERING SYSTEM
Examples of Intersil Part Numbers
BASIC

ELECTRICAL
TEMF PKG PIN
OPTION

ICH8500

A

ICL8038

C

C'

IH5040

ORDER #

T

V

ICH8500ACTV

C

P

0

ICL8038CCPD

M

0

E

IH5040MDE

ON ALL INTERSIL IC PART NUMBERS. THE LAST
THREE LETTERS ARE TEMPERATURE, PACKAGE, AND
NUMBER OF PINS, RESPECTIVELY.
PACKAGE:

TO-237
Plastic flat-pack
TO-220
o Ceramic dual-in-line
E Small TO-8
F
Ceramic flat-pack
H
TO-66
16 pin (.6 x .7 pin spacing)
I
hermetic hybrid dip
Cerdip dual-in-line
J
K TO-3
Leadless, ceramic
L
Plastic dual-in-line
P
S TO-52
TO-5 type
T
(also TO-78, TO-99, TO-100)
type
u TO-72
(also TO-18, TO-71)
V TO-39
Z
TO-92
IW Wafer
10 Dice

NUMBER
OF PINS:

A

8

P

B

Q

2

F
G

10
12
14
16
22
24

R
S
T
U
V

3
4
6
7
8 (0.200" pin circle,
isolated case)

H
I

42
28

W

10 (0.230" pin circle,
isolated case)

J
K

32
35

Y

8 (0.200" pin circle,
case to pin 4)

L
M

40
48

Z

10 (0.230" pin circle,
case to pin 5)

N

18

A
B
C

C

o
E

20

10-19

\

.O~DIL
.

.,'

'\

\

"

APPLICATION NOTE SUMMARY
The following are brief descriptions of current Intersil
Application notes.
A021

A003 UNDERSTANDING AND APPLYING THE ANALOG

AOO4

AOO5

AOO7

A011

A013

A015

A016

A017

A018

A019

A020

SWITCH
Introduces analog switches and compares them to
relays. Describes CMOS, hybrid (FET + driver), JFET "virtual ground" and J-FET "positive signal"
types. Application information included.
IH5009 LOW COST ANALOG SWITCH SERIES
Compares the members of the IH5009 "virtual
ground" analog switches and provides suggested
applications.
THE 8007 - A HIGH PERFORMANCE FET INPUT
OP AMP
Compares the 8007 with the 741, which is pin
compatible and suggests applications such as
logantilog amplifier, sample and hold Circuit,
photometer, peak detector, 'etc.
USING THE 8048/8049 MONOLITHIC LOGANTILOG AMPLIFIER
Describes in detail the operation of the 8048
logarithmetic amplifier, and its counterpart, the 8049
antilog amp.
A PRECISION FOUR QUADRANT MULTIPLlERTHE 8013
Describes, in detail, the operation of the 8013
analog multiplier. Included are multiplication,
diVision, and square root applications.
EVERYTHING YOU ALWAYS WANTED TO KNOW
ABOUT THE 8038
This note includes 17 of the most asked questions
regarding the use of the 8038.
DESIGN FOR A BATTERY OPERATED
FREQUENCY COUNTER
Describes a low cost battery operated frequencyl
period counter using the 7207A and 7208. Includes
specifications, schematics, PC layout, etc.
SELECTING AID CONVERTERS
Describes the differences between integrating
converters and successive approximation
converters. Includes a checklist for decision making,
and a note on multiplexed data systems.
THE INTEGRATING AID CONVERTER
Provides an explanation of integrating AID
converters, together with a detailed error analysis.
DO'S AND DONT'S OF APPLYING AID
CONVERTERS
.An analysis of proper deSign techniques using DI A
converters.
4Y2 DIGIT PANEL METER DEMONSTRATION I
INSTRUMENTATION BOARDS
Describes two typical PC board layouts using the
8052A17103A 4Y2 digit AID pair. Includes
schematics, parts layout, list of materials, etc. Also
see A028.
A COOKBOOK APPROACH TO HIGH SPEED DATA
ACQUISITION AND MICROPROCESSOR
INTERFACING
Uses the building block approach to design a
complete 12 volt system. Explains the significance
of each component and demonstrates methods for

A022

A023

A026

A027

A028

A029

A030

A031

A032

A046

A047

10-20

microprocessor .in~erfacing,incllldin9 the use of
control. signalS.
POWER D/ACONVERTERS USING THE ICH 8510
Detailed analysis of the 8510. Included area section
describing the linearity of the device and appliCation
notes for driving servo motors, linear and rotary
actuators, etc. Also see A026.
A NEW J-FET STRUCTURE - THE VARAFET
Describes in detail the operation of the varafet, a
standard J-FET with the analog gate interfacing
c;:omponents monolithically built-in.
LOW COST DIGITAL PANEL METER DESIGNS
Provides a detailed explanation of the 7106 and
7107 3Y2 digit panel meter IC's, and describes two
of the evaluation kits available· from Intersil.
DC SERVO MOTOR SYSTEMS USING THE
ICH8510
This companion note to A021 explains the design
techniques utilized in using the ICH8510 family to
drive closed loop servo motor systems.
POWER SUPPLY DESIGN USING THE ICL8211
AND ICL8212
Explains the operation of the ICL8211/12 and
describes various power supply configurations.
Included are positive and negative voltage
regulators, constant current source, programmable
current source, current limiting, voltage crowbarring,
power supply window detector, etc.
BUILDING AN AUTO RANGING DMM WITH THE
ICL7103A18052A CONVERTER PAIR
This companion app note to A019 explains the use
of the 8052A/7103A converter pair to build a ±4Y2
digit auto ranging digital multimeter. Included are
schematiCS, circuit descriptions, tips and hints, etc.
POWER OP AMP HEAT SINK KIT
Describes the heat sinks for the ICH8510 family.
These heat sinks may be ordered from the factory.
THE ICL7104: A BINARY OUTPUT AID
CONVERTER FOR MICROPROCESSORS
Describes in detail the operation of the 7104.
Includes in digital interfacing, handshake mode,
buffer gain, auto-zero and external zero. Appendix
includes detailed discussion of auto-zero loop
residual errors in dual slope AID conversion.
COIL DRIVE ALARM DESIGN CONSIDERATIONS
Explains the procedure used when using watch
circuits to drive piezoelectric transducers .
UNDERSTANDING THE AUTO-ZERO AND
COMMON MODE PERFORMANCE OF THE
I.CL7106/710717109 FAMILY
Explains in detail the operation of the ICL7106/7/9
family of AID Converters.
.
BUILDING A BATTERY OPERATED AUTO
RANGING DVM WITH THE ICL7106
Explains principles of auto ranging, problems and
solutions. Includes clock circuits, power supply
requirements, design hints, schematiCS, etc.
GAMES PEOPLE PLAY WITH AID CONVERTERS
Describes 25 different integrating AID converter
applications. Input circuits, conversion modifications,

display and microprocessor interfaces are shown in
detail.
A050 USING THE IT500 FAMILY TO IMPROVE THE
INPUT BIAS CURRENT OF BIFET OP AMPS
A brief description of a preamplifier for BIFET OP
AMPS.
A051 PRINCIPLES AND APPLICATIONS OF THE
ICL7660 CMOS VOLTAGE CONVERTER
Describes internal operation of the ICL7660.
Includes a wide range of possible applications.
A052 TIPS FOR USING SINGLE CHIP 3Y2 DIGIT AID
CONVERTERS
Answers frequently asked questions regarding the
operation of 3Y2 digit single chip AID converters.
Included are sections on power supplies, displays,
timing and component selection.

A053 THE ICL7650 A NEW ERA IN GLITCH-FREE

CHOPPER STABILIZER AMPLIFIERS
A brief discussion of the internal operation of the
ICL7650, followed by an extensive applications
section including amplifiers, comparators, log-amps,
pre-amps, etc.
'
A054 DISPLAY DRIVER FAMILY COMBINES
CONVENIENCE OF USE WITH
MICROPROCESSOR INTERFACABILITY
Compares and describes the various display drivers.
Includes design examples for 7 segment, Alphanumeric, and bargraph systems.
M011 AVOIDING PROBLEMS IN CMOS MEMORY
OPERATION
Discusses input overvoltage and SCR latchup and
the multiple address access problem in CMOS
RAMs.

10-21

Device Family Prefixes

~o

=

1M
LH

-Microcontroller Ie
'
-National Semiconductor Hybrid Alternate Source

LM

- National Semiconductor Alternate Source

~~~~~~;:i~:n~:~~g;~~ Source
DG ....,.Siliconix Analog Switch Alternate Source
OOM-Monolithlc DG Analog.switch Replacement
ICL -Linear Ie
leM - Microperip.herallC
ICH - Hybrid Ie

~~ :~i~~ey~I!~~e~~:~~~~~r~~h

SE

-Signetics Alternate Source

Electrical OptioniVariation of Basic Device Type Designators
Th~se

designators are datasheet dependent, and are not

~Iways

used.

Temperature Range Designators
C

-Commercial: O·C to + 70 e
-Industrial: Either - 25 C to + 85·C or - 4O"C to + 85"C
G

Q

(Specified on Oalasheet)

M

+ 125"C

- Military: - 55"C to

Package Type Designators
A

B

-TO-237

-Small Outline Ie (SOle)

o

- T0-220
-ceramic Dual·in-line
-SmaIlTO-8

F
H

-Ceramic Flat Pack

I

-16 Pin (.6 x.7 Pin Spacing)
Hermetic Hybrid Dip
- CEAolP Dual-In Line

C

E

J

K
L

P

S
T

u
V
Z
IW
10

-TO-66

-TO-3
..... Leadless, Ceramic
....:... Plastic oual-Io-line

-TO-52

--TO-72
~c;.~ j\'~B, TO-99, TO-1OD)
Type
(Also TO-1B,
-TO-39
-TO-92

T0-7~

-Wafer
-Dice

Part Numbering System
All IntersilIC part numbers consist of a device family prefix, a basic numeric
pari number, and an option suffix. as follows:

1,20r3
Dlg;.t
Prefix

3, 4 or 5 Digit
Un;que Device

---

-Number'

T ""I

30r4
Digit Option
Suffix

X"XxX

High
Reliability
Designator

/XXXX

Lp;nco~~t'

Designator

~ Package
Type
Designator
- - - Temperature Range
Designator
.
- - - - - ElectricafOption
Designator. Only
User if More Than
One Electrical Option
is Available.

- - - - - - - - - - - - Variation 01 Basic
Device Type Designator.
OnlY'Usect il More Than
One Basic Device
Type is Available.
- - - - - - - - 3 or 4 Digit Basic
Device Type
Part Number
~--------

Device Family
Prefix

ORDERING INFORMATION
Pin Count Designator
8

P

V

20
2
3
4
6
7
8 (0.200" pin circle,

42
28

W

10 (0.230'" pin circle

J

K

32
35

Y

8 (0.200" pin circle.
case to pin 4)

L
M

40
48

Z

10 (0.230" pin circle,
case to pin 5)

N

18

A

8

E
F
G

10
12
14
16
22
24

H
I

C

0

a
A

S

T
U

isolated case)

isolated case)

HIGH RELIABILITY DESIGNATOR
/8838 - MIL-STD-8838 Sc""'ned
Device
fHR

-High-Reliability

Device
ISR

-Cost Effective High-

181

- Burn-In Only Process
Flow

ReliabIlity Device

"'" Ttft

Example Part Numbers

.

.-~-..
~:~~~2U.'-'''-Line
D·C to

,"""'IW :::::::::.~",'
- O"C to + 70'C
Temp. Range

+ 70·C Temp. Range

L Type Electrical Option
Basic Part Number:

B Type Device Designator

7129 AlD Converter.

' - - - - - - - - - Basic Part Number:

' - - - - - - - - - - - - Linear '.C Family Device

,""TtF

".-~-.

CEADIP Dual·ln lme Package

..

7134 DIA Converter

__._'.e

' - - - - - - - - - - - - Linear Ie Family Device

51

- 40°C to + 85'C
Temp. Range
Basic Part Number: 7170
Real Time Clock

'-------------Microperipheral
Ie Family Device

IH

I~'L
L

.'~

,

CEROIP Dualln·Line Package

14 Pms on Package

- SS'C to + 125'C
Temp. Range
L -____________________ ~c~~~~~~~

31

· ""J1fT

'--_ _ _ _ _ _ _ _ _ _ _ _ _ Hybrid Ie Family Device

:.::"=....
- 55°e to + 125"C
Temp. Range

B Type Electrical Option

' - - - - - - - - - - Basic Part Number:
5043 Analog Switch

' - - - - - - - - - - - - - Hybrid Ie Family Device

10--23

EvALuatioN

KITS

PRODUCT DESCRIPTION

"

PART NUMBER

CONTENTS
ICH8510i + Socket + Heat Sink
ICH8510 + Socket + Heat Sink
ICH8520i + Socket + Heat Sink
ICH8520M + Socket + Heat Sink
ICH8530i + Socket + Heat Sink
ICH8530M + Socket + Heat Sink

Power Amplifier Kits

ICH8510lEV/KIT
ICH8510MEV/KIT
ICH852011EVIKIT
ICH8520MEV/KIT
ICH853011EVIKIT
ICH8530MEVIKIT

312
312
312

Digit LCD Panel Meter Kit

ICL7106EV/KIT

ICL7106 + PC Card + All Passive Components

Digit LED Panel Meter Kit

ICL7107EV/KIT

ICL7107 + PC Card + All Passive Components

Digit Low Power
LCD Panel Meter Kit

ICL7126EV/KIT

ICL7126 + PC Card

412

Digit AID Converter Kit

ICL7129EV/KIT

ICL7129 + 4Y2 Digit LCD Display + ICL8069 + PC
Card + Active, Passive Components

412

Digit AID Converter Kit

ICL7135EV/KIT

ICL7135 + ICL7660 + ICL8069 + PC Card + Active,
Passive Components

412

Digit LCD Display Driver Kit

ICM7211EV/KIT

ICM7211 + 4 Y2 Digit LCD Display + PC Card + Active,
Passive Components

8 Character Multiplexed LCD
Display Driver Kit

ICM7233AEVIKIT

2 01 ICM7233A + PC Card + 8 Character Triplexed LCD
Display

8 Character Multiplexed LED
Display Driver Kit

ICM7243BEV/KIT

ICM7243B + PC Card + 8 Character LED

+ All

Passive Components

412

Digit LCD Display Co~nter Kit

ICL7224EV/KIT

ICM7224 + ICM7207A + 5.24288MHz Crystal + 4 Y2 Digit
LCD Display + PC Card + Passive Components

412

Digit LED Display Counter Kit

ICM7225EV/KIT

ICM7225 + ICM7207A + 5.24288MHz Crystal + 4Y2 Digit
LED Display + PC Card + Passive Components

412

Digit VF Display Counter Kit

ICM7236EV/KIT

ICM7236 + ICM7207A + 5.24288MHz Crystal + 4Y2 'Digit
VF Display + PC Card + Passive Components

ICM7206EVlKIT
ICM7206AEV/KIT

ICM7206 + 3.579545MHz Crystal
ICM7206A + 3.579545MHz Crystal

ICM7206BEV/KIT

ICM7206B + 3.579545MHz Crystal

8 Digit Frequency/Period Counter
5 Function

ICM7226AEV/KIT

ICM7226A + 10MHz Crystal + PC Card + LEDs + All Passive
Components

Oscillator Controller
For Application as Ireq.
counter with ICM7208

ICM7207EV/KIT
ICM7207AEV/KIT

ICM7207 + 6.5536MHz Crystal
ICM7207A + 5.24288MHz Crystal

Touch Tone Encoder
One contact per key
Two contacts per key, common
to positive supply
Common to negative supply,
oscillator enabled when key
depressed

10-24

'fl
-=+105-

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

1--1

0.178-0.181

0.208-0.219
(5.308-5.583)
0.188-0.210

,•
• I 0.208-0.218
(5.308-5.583)
0.178-0.181 "
0.142-0.150
(4.521-4.851) ~ I (3.507 3.810)

I

I-i--- "-

,I

SEATING PLANEp

y_~

(::~:

(::= IL
0001

MAX
0.018-0.018 __
(0.0408-0.483)

I
II

0.01:~~.019

00

Ii
(0.406-0.483) -11-

0.500
(12.70)
MIN

01
0.500
(12.70)

1_ _ _1

0.050
'I
(1.270)-

:-1
'

-

0.100
(2.540)

POOO1811

PQ001611

TO-18

TO-52 (SQ*, SR)

_'-

I
I

1

'1_

0.209-0.218
(5.308-5.683)

G.178-0." , , _ 0.188-0.210
(4.521-4.851) -I
(4.775-;-5.334)

i

0.178-0.191
, (4.521-4.851)

--7iQJ

SEATING

II__

0.142-0.159
(3.507-4.038)

PLANED_~~

0.::- ~0n11

(~~ mom_l

MAX
0.016-0.019 _
(0.406-0.483)

~'_II

0.208-0.219
(5.308-5.583)

(0.782)
MAX
0.018-0.019
(0.406-0.483)

0.500
(12.70)

I

_1__

W

0.500

(12.70)
MIN

MIN

PQ002111

POOO2011

TO-71

TO-71 LOW PROFILE
SQ" denotes a two lead package; center lead missing.

II
10-25

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

TO-78

TO-72

.021
.016

DIA(3)

.019

DLAj31

r=~_L-==uc6

_J±-=--d:;~
~ 1 to.,
j .
1~

L

l

17ll

.055

.016

... 5

~

,I

I

-0

1 ....
I
t r

.135 MLN

t

,

I

.105

0·'

•
I

.095

I

I

1

.205
.115

PO'

I

-0"

j

I

{~l
.140

500M'.

SEATING PLANE

TO-92

0.335-0.315
(8.509-8.001)
DIA

o.a50-0.370
(I.IIO-Uta)

0010

R-':::::::

Q.315-0.3U

=+±!. . .-..

----

(1n1~

(8.001-8..500)

MAX

DOlo

SEATING

0.185-0.185

L

'91'

PLANE-j

+*,:C:::m;;::;;::;rn;::':J-.1INSULATOR

DlA

,

D....

D.
(12.7)

l~~

~LEADS ~~ ~ ~~ -----+-L-Mt

(.254-1.018)

~--IL
I.

(0.483-0.406)

TO-99 TV

TO-99 TV

10-26

PACKAGE OUTLINES

I"

All dimensions given in inches and (millimeters).

.370-.335

•

I
0.205-0.185
(5.21 -4.85)

I.

.. I

P0Q03011

POO0271I

TO-100 (TW, TX)

TO-237 JEDEC

POO03111

2 LEAD CERAMIC (DH)

10-27

.O~OIl.
PACKAGE OUTLINES

All dimensions given. in inches and (millimeters).

[[]
0.407 (10.338) _

MAX

LJrnt
I_II

0.115.(2.921) . .!!,lli (1.778)
0.060 (1.524)
0.030 (O.~

.

r~~ (5.08)

__

t

~:=I~:~~![

0.060~

+0T25 (3.175)

0.110 (2.794)
0.090 (2.286)
0.023 (0.5841
D.li14 (0.356 -

,---

t

(5.08)

.

I I

il.ii25 (0.6351)

t 0.200

.

...

0.015
(0.381)

I (~:~3) .. Ii

0.320 (8.128) , ..
0290 (7.366)

I

PO003311

8 LEAD CERAMIC (DA)

O ~ ~:f -J i 1'_1 ~".
I

0.045

d1!1..
.090

~

1

(

1-- 0.01 6 '

-i i-

0.271
0.245

F

-~~
,

I
iWM. --I

LO.375

P0004011

8 LEAD CERDIP

10-28

PACKAGE OUTLINES All dimensions given in inches and (millimerters).
~
0.260" 0 . 0 1 0 0
8.35'" .264

-,-

-

(~:~)
1-----+1

0.310 " 0.010
17.87'" .25)

POO04211

8 LEAD PLASTIC (PA)

o.no

i1i.iii

0.344-0.384 ~
/8.74-8.26)

I

I

t~..lSEATING
T

0.480-0.500 - - . (12.18-12.71 ~
(1.02)

PLANE

0.118&-0.100
(2.18-2.64)

TYp-ll-

0500
1.182-1.182
(12.70) R (30.02 30.271
".010
(.254) -

0.188-0.178 RAD
(4.22-4.471
•

POOO4l1l

8 LEAD TO-3 METAL CAN

8 LEAD S.O.l.C.

I

.1502PL

. · _ _ _ _ _ . ___

~

__ L,

.010:t.OO8RTYP

'=====±:-==*==---,'--==
_

.,

_

..I

O"TOSOTYPALLLEADS

1

,014"'IN LENGTH OF FLAT
AREA TYP ALL lEADS

10-29

PACKAGE OUTLINES

All dimensions' given in inches and (millimeters).

MINl

0.750 (19.05)

f-I

0.330 (S.392) - [
D.2iiiI (6.35)

L
L

S[
--J

_ 0.019 (0.483)

D.OiO (0.254)

.1

It!MAX

LO.260 (6.604) 0.055 (1.397)
0.045 (1.143)

---1
1

t

f

0.240 (6.096)
1-il.22ii(S.588)

0.006 (0.152)

0.070 (l.77S)
if.04ij (1.016)

If.liii4 (0.1021

L~!~ (6.6041
0.040 (1.016)

i~O.020(O.SOS)

~ .j
PQ00431 I

10 LEAD FLATPACK (FB)

[[:]3

MAxk. ~:=W::~IC
1 I_
0.200 (5.081
I MAX

_0.710 (lS.034)
0.11512.9211
0.060 1.5241

~

~

0.070 1.77S
0.030 0.752

r

14 ~

H H H

I

0.110 (2.7941_
0.090 (2.2861

~ ~I

0.060 !C1.-=S2:c:
4):----r'-J-r-'i

D.ii25 0.6351]
0.200 (6.08)

ffi5 i3:i751

_~ (0.5841

I

0.014 (0.356)

~1

t

!e:
0.015

I

I'

0.320 (S.1281
0.290 (7.3661 ..

POO0441 I

14 LEAD CERAMIC (DO)

1

,
"I

PACKAGE OUTLINES

All dimensions given in inches and (millimetes).

POO0351 I

14 LEAD CERDIP (JD)

n

0.017 ± 0.002

TYP

;

1

I

I 0.050 f

:===1 T 0.:Js5

L

r

0.056 (0.139)
0.045 (0.114)

II:[I::ilI::=::f.t
c==J

C 0 7 (0.177)
0.004 (0.101)

0.270EJ

0.266 (0.673)
0.250 (0.635)

t
t

Lo.olB (0.457)
o:ii1O

(0.254)

LO.07B

(0.198)
0.066 (0.165)
P0003411

POOO4511

14 LEAD FLATPACK (FD)

14 LEAD FLATPACK

1()"'31

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

--*.' .
.~~,:,::[::::: ]
-r ~
MAX~

-

.770(19.658)

~.310

'" 0.010
7.874 '" 0.254

0.130 '" 0.005
3.302 '" .127

.060 (1.624)

m·Fi----~------,-.-IL ---+-I!F?L'''.~I
,>oJ
.090 (2.286)

l"~1 ~l::= j ~~:_,
.046 (1.143)

.015 (.3810)
POO0361I

14 LEAD PLASTIC

[c::]]

1

-0.810 (20.574) MAX

0.115(2.921)
0.080 (1.524)

!!.:!!Z!!(1.7781_
0.030 (0;762

~~~~~~~~~~.

1
P00037t1

16 LEAD CERAMIC (DE)

10-32

PACKAGE OUTLINES' All dimensions given in inches and (millimeters) ..
16

9

.0.696 )17.653)
il.106 /17.907)
0.790 (20.066)

0.800 r.32O)
.1

8

I.' ~"""~
0.880 /22.362)
0.966 /24.511)
0.975 (24.765)

0.200 MAX (5.080)

0.100 (2.54) . ;
TVP.~

I

I

f-

1_
0.600~1
1(15.240)

I

POO0521!

16 LEAD CERAMIC (IE)

[~~~~]

0.060 (1.5209

L

0.015(0.381)

0.320 (8.128)_r--_ _~
0.290 (7.366)

~'840 MAX~

mIT121.34)

.
~
.

-O.175

-

MAX

-14.451,--.-t...,.......

I

I I

~
0.110 (2.794)
0.090 (2.286)

J~ JI~
1

L
I

'

.

.

0.070 (1.778)
0.030 (0.762)

0.200 (5.08)

0,126 (3.175)
0.023 (0.584)
0.015 (D.3iii)

0.015

J L
I
I

0.008
:g:~~~:

I
I

0.415110.5411
0.33018.382)
P0Q05311

16 LEAD CERDIP (JE)

10·33

.

PACKAGE OUTLINES

All dim~nsions given in inches and (millimeters).

·---l.046~--~'~'

r

0.050
TVP

I

I

I

j t:~

I

I!

,
!
I-

0.016
%

0.002

I I
I ,
. II

I

0.370

t

0.063

"I
0.003

MAX.

--I f-POOO3911

16 LEAD FLATPACK (FE-2)

0.380 (9.662)

D.Jiilj If.i2r

Fl~~ MAX~

-.

.

I'·

(j 290

J

~~(7.366).

I

MAX

.

M!! lo.4831
0.015 0.381

t
~[i~.~~'
~
t
+
-

0.400 MAX

(10.18)

0.066 (U87)

110.280 (7.1l2)

t

*

0.046 (1.143)

.~======~==~~~~.2~(~6.~b=3)~!=.~r-~:~!~~:

L
.

0.006(0.162)
0.003 (0.076)

0.080 (2.032)
Q]4O (1.016)

~
POOO3811

16 LEAD FLATPACK (FE-1)

10-34

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

;':--t=~[:::~::]

I

-

F~MAx~1
I
m.~~r--.
-II--;~·--r-l~8t

0.130,,0.005
3.302 " 0.127

1&.558

.080 (1.524)

',-I

r-l

I

~

:=

:~l~~::

~L

I

r..I I--

~,

.

.160(4.064)
.100!2.54Ol

l

.015(.~1)

.008 (.203)

--..

:::~~: :g~:~

_15°

POO0541 I

16 LEAD PLASTIC (PE)

ir-------------------------------------------------------------__-----------------------,
r-=-0.910(23.114)

,.,AX~

[['-J]~.~

0.110~ I

0.090 (2.286).
L-

t:
.

==
~...~'MAIX'
!!.l!Z!!.
0,030 (0.762)·
(1.7781

J~~r

'..

-.Lffi1--m?:~.
~*:::;"===:;:t=It;:;;-.l:--.l~1

T

0.115 (2.921)
0.080 (1.524)

il

-

f 0.060 (1.524)
t M15 3811_11_(0.203)

-

(0.

O.OOS

..~.. k
.. ' ' "
..

0.023 (0~5Ii41
0.014 (0.356)

T

i 0,?,25 (0.635):
·0.200 15:08)""
I
0.125(3.1751

~

:
I

~
0.320 (8.128! .
0.290 17.366
POOO551 I

18 LEAD CERAMIC (ON)

10-35

IID~DIl,.
PACKAGE OUTLINES

All dimensions given in inches and (millimeters).
~
0.290

•128)
187.386)

[~~~~~]
J..-

Y12.
0.280

!U~:I

.910123.1141 MAX---J

0.060~

o+~u
r¥WWM~¥WW[ rns~
0.200(5.08)

-I~

-! !-

~

(2.794) 0.070 (1.778)
0.090 (2.286) 0.030 (0.7621

0.023 (0.594)
0.015 (0.3811

18 LEAD CERDIP (IN)

PIN ONE INDICATOR

f

M"'J"'' ; ~~~=r=~~~9
-0.050
(1.270)
0.005 ± 0.002
(0.127 ± O,05O

L

TYP~0'315

(8.001)
0.950 t 0.050
(24.130 ± 1.27)

r (g:=)

--.l

REf

~~~:~=a:===c~
P0007511

18 LEAD FLATPACK (FN)*

10-36

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

1-.
I •.310
005

t

'f j

rt=i1

f

WI ==r ~
L'-~

~:=} L ·
.050±.005

1

f L.005~.~
.

,_::=-:j.; V'"

rF'Z?

U

.019
•.002

.230

POOO561 I

18 LEAD FLATPACK .(FN-2)

PIN NUMBER 1

C;

'----1.000-----{2.54}

:-{~::!}l

~

•

11

D

0.01?

ItD:JI~
(0.12?)

L_~~:::J~~i~_~=!
.,-J l
L
0.005
{0.0127}

0.063
(0.160)

0.020
{0.051}

P000761t

18 LEAD FLATPACK (FN-3)

10-37

.U~UIb
PACKAGE OUTLINES

All dimensions given in inches and (millimeters) ..

t

0.310 ± 0.010
7.874 ± 0.264

.

;~:;(::::::]
fl.

.'20MAX .
23.388
.

.

..

I

.130 ± .006

:;:I~r-------------------I--_3~.3~0~2~f~·~12~7~~~

t
0.110 (2.794) 0.0701l.nSI 0.022 (0.669)
0.090 (2.288) 0.030 (0.762) O.OIS (0.467)

U

.160 (4.064)
.100
l2Ji4Oj

rl\-

~ :::'~~:

l

0"_160
P0007911

18 LEAD PLASTIC (PN)

~

[~~~~~~~~J
!---;.025.126.035) MAX--i

.

m~

0.290

r

.!1d!l!

I~::) I

-(6:ilI4i

-L..-

-.~!

r-

0.110 ~ M!9 lh12'!.!
0.090 12.286) 0.030 10.7621

0.023 10.584)
0.015 IO.381f
POOO4711

20 LEAD CERDIP (JP)

10-38

PACKAGE OUTLINES All dimensions given in inches and (millimeters).

---LC--::J

.260:t .010
8.35,. .264

0.310 ± 0.010
1--7.874:t0.264

--

•

-rIO

~.~MAX

.,

26.418

.130", .006
3.302'" .;27

=~::~~I80~12~0.d(1'778) O.=!~) :::l~l ~~I-..j \

~0"-15"

0.090 12.2&8) 0.030 10.782) 0.01810.467)

POO0771 I

20 LEAD PLASTIC (PP)

r

1.100 127.940)

MAX~

[[~~JJ~,~,

~.~~~.=)
•.

t

0.070 10.782}
Il.ns)l
0:000

r-1

_

Jg:~

-Lm1--m~+
!
T
t f
-JI T
il

11
~:~ l~~M·

--".

0.060 11.524)
0.025 (0.635)

0.130 13.302)
0.070 11.nS)

0.200 ~

Q.,ill10;584)
0.014 10.366)

0.12613.175)

mr

i
I

~

i
I

0:420 110::/
0.390 9.

~

POOO4811

22 LEAD CERAMIC (OF)

10-39

PACKAGE OUTLINES

All dimensionS given in inches and(millimeters).

r---------:; 1 i1li 'Ilar
= ,L_-~~
- - .~ l=~r
I
I

I
~:j:WWL ~lfl ~'- -'- '- -'Lo.o,:(:'~\ r

".,. r---

·1.,0(27.94)MA)(

Jl'

!I L
!

0.200 ((6.OS)
0.126 3.115

r-l

0.110 12.194)
0.090 2.286)

I o.oOS (0.203) I
'

.

0.070 (1.ne)
0.030(0.162)

0.023 (0.584)
0.015 (0.381)

I

L

0.S10(12.964J
0.440(11.116)
POOO4911

22 LEAD CERDIP (JF)

~'.290 (32:~) MAX~

0.620 (16.148) ,
__

r

'"'"-o;....-.;,..;;;;;;:;;c;r--

~!ii1mt~-Po:mImm~;1
=r
I

.!!.!1§ (2.921)
0.060 (1.524)

I

I

0.200 (6.08)
MAX

i

!1~~

==

I I . .T.

_11_-

~ (0.5841
0.014 (0.356

y

~

t

I

I

0.015 !0.381)
D.OOi 0.203)

I

I

0.200
I
I
0.125 (3.115)
'0.620 (16.148) ---.l
M§!! (1.624) j1i.69O (iUfili
0.026 (0.636)

POOO5111

24 LEAD CERAMIC (DG)

;

.,'

10-40

PACKAGE OUTLINES All dimensions given in inches and (millimeters).

_

1.290 (32.766) MAX

0.060 (1.524)

O.kOO

-~:~~~ m:~l-

I~~I
,

::~mrIsa

5(Ti
cc

0.o1

~~

1)mr!!'

II!I

0.015 (0.381)
0.008 (0.203)

I!

! !1_ _ _ _ - ,

(5.08)

0.125 (3.1751--\

0.110 (2.794) 0.070 (1,llS)
0.090 (2.286) 0.030 (0.7&2j

0.023 (0.5841
0.015 (0.381) _

0.700 (17.780) _ _
0.630 (16.002)
POO06511

24 LEAD CERDIP (JG)

0.060 (1.524)

0'0I 5(or

~

:~=!~::=]
II
0.5,0 (12.9541

.'76

m JI!
- 1 . 2 9 0 (32.766) MAX

I~:~I

" ,l! ::~mr=t~

i
LL

O.~OO ~ ! 1_
! _ _

-,

0.125 (3.175)--\

0.1'0 (2.794) 0.070 (1.77S)
0.090 (2.286) 0.030 (0.762)

0.016 (0.38,)_.0.008 (0.203)

I!

I

0.023 (0.584)
0.0'5 (0.38,) _

0.700 (17.780) _ _
0.630 (16.0021
POO06a1i

24 LEAD CERDIP WITH WINDOW (JG/W)

,0-4'

PACKAGE OUTLINES

All dimensions-given in inclJesand.(millimeters).

j P· 1MINl
O.750.(19.06)
,0.310

0.380 (9.652)

ii:3iiO

(7.62)

.

9 74
MAX

.

0.019 (0.483) .
'0.015lD.381)

__ --.1

~~==O=,OOS='=(1=·.3=97=)~~
0.280
(7.1'12)
0.245·~

n
. .'
'

f

I

----=r+

~(1~':~)

*

0.045 (1.143)

!~

L'

CO'C06=(0='1~52~)~~0~'0~90~(~2'~28~6=)J~=~Lo.04O
0.003 (0.076)

0.045 (1.143)

(1.016)

0.010 (0.254)
POO0641 I

24 LEAD FLATPACK (FG)
.

.

..

_~[
. . . ~=]."""'" ' ··"·····;6~:!~~4
".a~

"~

•....

Fl'~2~:x------J
;~~~o
~~'r---=r--.,
t==m--m~f ~
~1~L
J L' L,~~+i

.060(1.524)

.015(0.381)

.'

.

II

~

.110 (2.794)
.090(2.286) .

II

A

--

.

J

....

.060 (1.524)
.045 (1.143)

..160. .(4.064)
.100 (2.540)

.015 (o.02032i'.
.008

\

~UO_15C)

.023 (.5842)
.015 (.3810)
POO0671 I

24 LEAD PLASTIC (PG)

','

"

10-'42

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

D ·

--:J0.010
(15.00 ± 0.25)

~__

0.050±0.010

F

1

---I

1 400 0014
0.085 ± 0.009
.
±.
~l2.16±0.231

tt=:= I

"~~mtf;~
~I:J!
~L
h!

0.100 ± 0.005
(2.54 ± 0.13)

I

:::

I_

~~E:

0.610 ± 0.010
~ (15.49 ± 0.25)

0.018 ± 0.002 TYP
(0.46 ± 0.05)

J

0.050 TVP
(1.27)
POOOOSOI

28 LEAD CERAMIC (01)

!M!!!I!Pi'~1
0.570
1 A
0.175
(4.445)

MAX

0.015 !0.J1!

l~--~

ILlmnrJ-rumrr

~I~ J GlL ~ ~
l-JL,
0.110 (2.7

li:iiiii

1

(1.524)

~ ~

0.015 (0.3810)

i
~~

111

L

_
0.880 (17.2721

o:m m:4li4l
28 LEAD CERDIP (JI)

10-43

J

1,:,

.' ,.,

PACKAGE OUTUNES All dimensions given in inches and (millimeters).

~['.

0.536 ± 0.015

".p ";"'

t

.

r.

==]

r-- 0.610 ± 0.010--16.49", 0.25

-- .

-1:470 MAX
37.34

• .155 ± .010

~~::m~f
I

I

r~II~
.11012.794)
.090 12.286)

rrJ~-I-'
.
.150 14.064)
.100 12.540)

.050 11.524)

.0231.5842)
.0151.3810)

.04511.14~)

POO05911

28 LEAD PLASTIC (PI)

~
--! L

2.020 (51.308)
MAX

-

QJ.!!!! 12.540)

"'--C:i~1C

~--r=--- --I·_J.

1.
0,050 11.270

~ 15.050

11~~)

_I I!..-

SQUARE

.

0.165
0.050 14.191)
11.270) MAX.
TYP.

I

+rWW~F~;r
rl!.
I
-I r

0.050 11.270)
, 0.010 liiJli4J

11

-:i-:"0.018 10.;7!

., if.iili2 1.0.

1

I~: :~)

jJ
~:~I~:=I-III

I

0600
1
1--115.240) _ I
I
REF.
I

1

MIN.

P0006011

40 LEAD CERAMIC DUAL-IN-L1NE (DL)

10-44

.D~DIL
PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

[::J
0.060~1

1'-' . . .

I

2.040 (51.816) MAX

~ ~ I ,i":: r~= ~~~:~:l

I

1

1

=L
~(=)

~'"lm--ww--r----l~fl·.----r'-r---i'
P=r-l

0.160 (4.0641
0.100 (2.540)

I"

I

I--

0.110 (2.794)
0.090 (2.268)

~ ~ J~

0.060 (1.524)
0.045 (1.143)

0 . 023
15 «00·.584
38 ,z0»

II

J

II

L

0.680 (17.2721
0.610 (15.4941
POOO6fll

40 LEAD CERDIP (JL)

,

2.000 •.020
(50.8. 0.508)

_

"/

o

nnnnnnn==nnnnnnnn==0--r

I
...............................

_-_

:r.

.600 ••010
254
)

..................................

_--

.136TYP

.060 ••008
L.032. 0.203)

(a4~

~~
J.~~.'a'~~

1------'

.200 (5.08)

(1.27' 0.254)

I

.100'.005
(2.54.0.127)---1

I

I---

.050TYP
(1.27)

--II---

~

.018TYP
(0.457)

I

II---

(15.494)

I

~

.610TYp.

POO07801

40 LEAD CERDIP WITH WINDOW

m
10-45

PACKAGE OUTLINES All dimensions given in inches and (millimeters).
0.480

+.0.010
-0.005

(12.19) f+ 0.254)
( -0.127)

___
,

~..:~~

(11.68)

sa

0.360

-

so -

-==~~

(:to.152)
:!: 0.006

(9.144' sa

('t;' O. fS-2)

1-

-35

11

PINNO.,/INDEX
1.

,.

20

2'
PLATING
TIE BARS

_ .0.040 x9= ~~
(1.016)
(9.144'

-

L

0.020 TYP

(0.508)

~TYP

-(1.016)

===:io.- ___

~~ REF
(2.540)

/

0.025 450 REF
(0.6351

Note 1: Finish: Gold plated 60 micro inches minimum Ihickress over nickel plated.
Note 2: Pin number 1 connected 10 die attach pad ground

40 PIN LEADLESS CHIP CARRIER (LL)

10-46

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

~ ....,....,....,n __ n,...,,.,,...,

•
t-- 0.610 ± 0.010-

(

0.535 ± 0.015
13.59 ± .38

--r-F:~~:=
0.025

62.68

15.49 ± 0.25
.155
± .010

3.94±.25

'+m::ffitt~

JL~
I

0.060 (1.624)
.0.020 (.51)

.-~.. ~

II --li i
"·
rllIi (~~)

0.018 (0.467) TYP.
0.020 (0.508)

0.001 (0.025)

0.100
(2.540)
POO0621I

40 LEAD PLASTIC (PL)

~=r---,t..."

±.006

F$==I---, w.s-;o:16i

NON.ACCUMULATIVE TVP

t
~I
(3.6:!:O.ll!
-'--~~'f---

NOTES:

"

1. PART MUST COMPLY TO SPECIFICATION.
MAX FLA5}ITYP

2. DIMENSIONS IN PARENTHESIS ARE IN MILLIMETERS.
3. PART IS SYMMETRICAL ABOUT THE CENTERLINES (Q,J SHOWN.

44 LEAD PLASTIC FLAT PACK

10-47

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

.1----'-1
'"'T' '

~[gJ--~'"
(

0.590 • 0.010

_

b-~~~~---~~~~~

0.050 ± 0.010
(1.27 ±0.25)

I
r-

2400

+

0024

.'

I

0.085 ± 0.009

(60.~ ~ 0.611 ~_L (2.16 ± 0.23)

*ffifff-JL-ffffl~.
lo.l75 I! !I
(4.46) ..

lj
0.100 • 0.005
(2.54 ± 0.13)

~~:::~ JI

LO.OlO
. ~.~
. - ~
?;~~:e'± ~O~~~)

0.018 ± 0.002,
(0.46 ± 0.05)
TYP

(0.25

)

0.050 TYP
(1.27)

P0007001

48 LEAD CERAMIC (OM)

10-48

.D~DI!.

FIELD SALES OFFICES

ALABAMA

GEORGIA

NEW YORK

3322 S. Memorial Parkway
Holiday Office Center
Suite 17
Huntsville, AL 35801
Tel: (205) 883-5713
FAX: (205) 883-8523

1835 Savoy Dr.
Suite 215
Atlanta, GA 3034 t
Tel: (404) 458-8401
TWX: 810-766-4593
FAX: (404) 458-5838

11 Computer Dr. W.
Albany, NY 12205
Tel: (518) 454-2576
FAX: (518) 454-2580

ARIZONA

ILLINOIS

5320 North 16th St.
PhoeniX, AZ. 85016
Tel: (602) 241-7224
FAX: (602) 241-7266

2860 South River Road
Suite 400
Des Plaines, IL 60018
Tel: (312) 827-9100
FAX: (312) 827-9064

CALIFORNIA
21201 Victory Blvd.
Suite 245
Canoga Park, CA 91303
Tel: (818)'884-4911
FAX: (818) 884-2283
4063 Birch St.
Suite 130
Newport Beach, CA 92660
Tel: (714) 852-9030
FAX: (714) 852-9035
1054 Saratoga-Sunnyvale Rd.
Suite 100
San Jose, CA 95129
Tel: (408) 255-5800
FAX: (408) 255-4693

CONNECTICUT
270 Farmin9ton Avenue
Suite 326
Farmington, CT 06032
Tel: (203) 677-7876
FAX: (203) 677-7015

FLORIDA
700 W. Hillsboro Blvd.
Suite 207, Bldg. 4
Deerfield Beach, FL 33441
Tel: (305) 429-0440
TWX: 510-953-7634
FAX: (305) 426-2696

INDIANA
2200 Lake Ave.
Lakeside 1 Office Bldg.
Suite 225
Ft. Wayne, IN 46805
Tel: (219) 422-8551
FAX: (219) 380-3309
6321 La Pas Trail
P.O. Box 68543
Indianapolis, IN 46268
Tel: (317) 298-5317
FAX: (317) 298-5374

MASSACHUSETTS
5 Militia Dr.
Lexington, MA 02173
Tel: (617) 861-6220
TWX: 710-326-0887
FAX: (617) 861-7130

MINNESOTA
4600 W. 77th St.
Suite 201
Minneapolis, MN 55435
Tel: (612)835-2550
FAX: (612) 830-8297

5794 Widewaters Parkway
Dewitt, New York 13214
Tel: (315)445-4780
FAX: (315)445-4709

NORTH CAROLINA
2105 Enterprise Rd.
P.O. Box 9476
Greensboro, NC 27408
Tel: (919) 379-8474
FAX: (919) 379-8478

OHIO
26250 Euclid Ave.
Suite 521
Cleveland, OH 44132
Tel: (216) 266-2900
FAX: (216) 266-2951

TEXAS
4099 McEwen
Suite 360
Dallas, TX 75244
Tel: (214) 661-8582
TWX: 910-997-0742
FAX: (214) 661-8212

VIRGINIA
503 Faulconer Dr.
Suite 9A
CharlottsvWe, VA 22901
Tel: (804) 978-5040
FAX: (804) 971-8350

NEW JERSEY
1600 St. Georges Ave.
Rahway, NJ 07065
Tel: (201) 381-4210
FAX: (201) 381-0990

FOR POWER MOS PRODUCT INFORMATION CONTACT:
Oanaral Elactrlc Powar Elactronlc. Samlconductor Dapartmant
West Genessee Street, Mail Drop 44
Auburn, NY 13021
Tel: (315) 253-7321

FOR BOARD LEVEL PRODUCT INFORMATION CONTACT:
OE Data'
11 Cabot Boulevard
Mansfield, MA 02048

Tel: (617) 339-9341

.U~O[lDOMEST'IC SALES,
REPRESENTATIVES
ALABAMA

GEORGIA

MICHIGAN

NEW YORK (cont.)

CSR Electronics
303 Williams Ave.:Suite 931
Huntsville, AL 35801
Tel: (205) 533-2444
TWX: 510-600-2831
FAX: (205) 536-4031

CSR Electronics
1651 ML Vernon Road
Suite 200
Atlanta, GA 30338
Tel: (404) 396-3720
TWX. (510) 600-2162
FAX: (404) 394-8387

Giesting & Associates

S-J Associates
148-05 Archer Ave.
Jamaica, NY 11435
Tel: (718) 29,1-3232
FAX: (718) 297-5885

ARIZONA
Shetler-Kahn
2017 N. 7th St.
Phoenix, AZ 85006
Tel: (602) 257-9015
TWX: 910-951-0659
FAX: (602) 252-3431

CALIFORNIA
ADDEM S.D.
Suite D-3
1015 Chestnut Ave.
Carlsbad, CA 92008
Tel: (619) 729-9216
Telex: 754078
H-Technical Sales, Inc.
12453 Louis St.. '101
Garden Grove, GA 92640
Tel: (714) 740-0161
(714) 740-2139
Ewing-Foley, Inc
895 Sherwood Ave.
Los Altos, GA 94022
Tel: (415) 941-4525
TWX: 910-370-6000
Ewing-Foley, Inc.
120 South Lincoln
Roseville, CA 95678
Tel: (916) 969-2672

COLORADO
Thorson Rocky Mountain, Inc.
7076 S. Alton Way
Bldg. D
Englewood, CO 80112
Tel: (303) 779-0666
TWX: 910-935-0117
FAX: (303) 773-2854

ILLINOIS
D. Dolin Sales, Co.
609 Academy Drive
Northbrook, IL 60062
Tel: (312) 498-6770
TWX: 910-686-4909
FAX: (312) 498-4885

INDIANA
Giesting Associates
101 E. Carmel Drive
Suite 210
Carmel. IN 46032
Tel: (317) 844-5222

Giesting Associates
4407 DeRome Driye
Ft. Wayne, IN 46815
Tel: (219) 486-1912

21999 Farmington Road
Farmington Hills, MI 48024
Tel: (313) 478-8106
FAX: (313) 477-6908

MINNESOTA
PSI
7732 West 78th Street
Minneapolis, MN 55435
Tel: (612) 944-8545
TWX: 910-576-3483
FAX: (612) 944-6249

MISSOURI
Kebco, Inc.
75 Worthington Drive
Suite 101
SL Louis, MO 63043
Tel: (314) 576-4111
TWX: 910-764-0826
FAX: (314) 576-4159

NEW JERSEY

J.R. Sales Engineering, Inc.
1930 SL Andrews NE
Cedar Rapids, IA 52402
Tel: (319) 393-2232
TWX: 910 525·1365

Gomtek, Inc.
Plaza Office Center
SUite 404 East
Route 73 and Fellowship Rd.
ML Lauiel, NJ 08054
Tel: (609) 235-8505
TWX: 710·897-0 t 50
FAX: (609) 235-5805

KANSAS
Kebco. Inc.
10111 Santa Fe Drive
Suite 13
Overland Park, KS 66212
Tel: (913) 541-8431
FAX: (913) 888-1036
Kebco, Inc.
16047 East Kellog
Wichita, KS 67230
Tel: (316) 733·1301.

MARYLAND

Advanced Components Sales
1 Prestige Drive
Meriden, CT 06450
Tel: (203) 238-6891
FAX: (203) 634-3964

Robert Electronics
5525 Twin Knolls Road
Suite 331
Columbia, MD 21045
Tel: Ball. (301) 995-1900
Wash. (30t) 982-1177
TWX: 710-862-2879
FAX: (301) 964-3364

EIR, Inc.
1057 Maitland Center Common
Maitland, Florida 32751
Tel: (305) 660-9600
FAX: (305) 660-9091

Giesting & Associates

IOWA

CONNECTICUT

FLORIDA

5654 Wendzel Dr
Coloma, MI 49038
Tel: (616) 468-4200

MASSACHUSETTS,
Advanced Tech. Sales, Inc.
50 Mall Road, Suite 602
Burlington, MA 01803
Tel: (617)272-0100
FAX: (617) 272-1515

NEW MEXICO
'Shetler-Kahn
2709-J Pan American Freeway,
N.E_
Albuquerque, NM 87107
Tel' (505) 345'3591
FAX: (505) 345-3593

NEW YORK
Ossmann Component Sales
Corp_
280 Metro Park
Rochester, NY 14623
Tel: (716) 424-4460
TWX: 510-253-7685
FAX .. (716) 427 -2861

Ossmann Component Sales
Corp
6666 Old Collamer Rd.
East Syracuse, NY 13057
Tel: (315) 437-7052
TWX: 710-541-1523

Ossmann Component Sales
Corp.
300 Main Street
Vestal, NY 13850
Tel: (607) 754-3264
TWX: 510-252-1987

NORTH CAROLINA
CSR Electronics,
5880 Faringdon Place
Suite 2
Raleigh, NC 27609
Tel- (919) 878-9200
TWX: 510-600-2709
FAX. (919) 878-91 17

OHIO
Gjesting & AssocIates
P.O. Box 39398
2854 Blue Rack Road
Cincinnati,OH 45239
Tel' (513) 385-1105
TLX: 214-283
FAX: (513) 385-5069

Glesting & Associates
26250 Euclid Avenue
SUite 525
Cleveland, OH 44132
Tel: (216) 261-9705
FAX: (216) 266-2951

G,€s1tng & Asso.ciates
8843 Washington Colony Dr.
Dayton, OH 45459 .
Tel: (513) 433-5832

OKLAHOMA
Bonser-Phf'lhdwer Sales
4614 S. KnoXVille Avenue
Tulsa, OK 74135
Tel (918) 744-9964

OREGON
LD Electronics
P.O. Box 626
Beaverton, OR 97075
Tel: (503) 649-8556
(503) 649-6177
TWX: 910-467-8713
FAX: (503)642-1518

PENNSYLVANIA
Giesting & Associates
411 Walnut Street
Pittsburgh, PA 15238
Tel: (412) 963-0727

TEXAS
Bonser-Philhower Sales
8200 Mopac, Suite 120
Austin, TX 78"159
Tel: (512) 346-9186
TWX: 910-997-8141

.o~ou.. DOMESTIC

SALES
REPR'ESENTATIVES

TEXAS (cont.)

VIRGINIA

WISCONSIN

CANADA (cont.)

Bonser-PhIlhower Sales

Robert Electronics

11321 Richmond Avenue
SUite 100A
Houston, TX 77082
Tel: (713) 531-4144
TWX: 910-350-3451

7641 Hull Street
Suite 101
Richmond, VA 23235
Tel: (804) 276-3979
FAX: (804) 745-5343

D. Dolin Sales Co.
131 W. Layton Ave.
Milwaukee, WI 53207
Tel: (414)482-1111
TWX: 910-262-1139
FAX: (414) 482-2033

Bonser-Philhower Sales.
689 West Renner Road
Suite C
Richardson, TX 75080
Tel: (214) 234-8438
TWX: 910-867-4752
FAX: (214) 437-0897

Gldden·Morton Assoc., Inc.
3860 Cote Vertu
Suite 221
SI. Laurent, Quebec
Canada H4R 1V4
Tel: (514) 335-9572
FAX: (514) 335-9573

WASHINGTON

UTAH
Thorson Rocky Mountain, Inc.
Bank of Utah, Suite A
2309 S. Redwood Rd.
West Valley City, UT 841 t9
Tel: (801) 973-7969
TWX: 910-925-5826

LD Electronics
7410 77th Ave., S.E.
Snohomish, WA 98290
Tel: (206) 568-0511
LD Electronics
East 12607 Guthrie Dr.
Spokane, WA 99216
Tel: (509) 922-4883

CANADA
Access Electronics
Suite 101
3570 East Hastings SI.
Vancouver, B.C.
Canada V5K 2A7
Tel: (604) 299-3556
FAX: (604) 299-4622

Gidden-Motron Assoc., Inc.
7548 8ath Road
Mississauga, Ontario
Canada L4T 1L2
Tel: (4t6) 671-2225
(416)671-8111

Gidden-Morton Assoc ..
301 Moodie Drive
Suite 101

Nepean, Ontario
Canada K2H 9C4
Tel: (613) 726-0844
Gidden-Morton Assoc., Inc.
605 Rue Filiatault
SI. Laurent, Quebec
Canada H4L 3V3
Tel: (514) 747-1770

.ll~O1l. AUTHORIZED DISTRIBUTORS
.,

':'

,

".',

' . '

ALAIiAMA

CALIFORNIA (cont.)

CAL·'FORNIA (cont.)

COLORADO

Arrow Electronics
1015 Henderson Road
Huntsville, AL 35806
Tel: (205)837.6955.
Hamilton/Avnet Electronics
4940A Research Drive
Huntsville, AL 35805
Tel: (205) 837-7210
TWX: 810-726·2162

Arrow Electronics
2961 Dow Ave.
Tustin, CA 92680
Tel: (714) 8~8-5422
Avn ..t Electronics
20501 Plummer S1.
Chatsworth', CA 91311
Tel: (818) 700-2600
Avnet Electronics
350 McCormick Avenue
Costa Mesa, CA 92626
Tel: (714) 754-6111

Schweber Electronics
1225 West 190 Stree.t
Suite 360
.Gardena, CA 90248
Tel: (213) 327-8409
Schweber Electronics
17822 Gillette Ave.
Irvine, CA 92714
Tel: (714) 863-0200
TWX: 910-595-1720

Arrow Electronics
1390 South Potomac Street
Suite 136
Aurora, CO 80012
Tel: (303)696·111 t
Hamilton Avnet Electronics
8765 E. Orchard Rmid
Suite #708
Englewood, CO 80111
Admin: (303) 779-9998
Sales: (303) 740-1000
Kierulff Electronics
7060 S. Tucson Way
Englewood, CO 80112
Tel: (303) 790-4444
TWX: 910-931-2026.

Kierulff Electronics
2225 Drake Ave.
Suite 14
Huntsville, AL 35805
Tel: (205) 883-6070
Schweber Electronics.
2227 Drake Ave. SW
Suite 19
Huntsville, AL:35805
Tel: (20,5) 882-2200

ARIZONA
Arrow Electronics
2127 West 5th Place
Tempe. lIZ 85281
Tel: (602) 968-4800
Hamilton/Avnet Electronics
505 S. Madison Dr.
Tempe, AZ 85281
Tel: (602) 231-5100
Kierulff Electronics
4134 E. Wood S1.
Phoenix, AZ 85040
Tel: (602) 437-0750
TWX: 910-951-1550
Schweber Electronics
11049 N. 23rd Drive
Suite 100
Phoenix, lIZ 85029
Tel: (602) 997-4874
Wyle DistributiOn Group
17855 No. Black Canyon Hwy.
Phoenix, AZ 85023
Tel: (602) 866-2888
TWX: 910-951-4282

CALIFORNIA
Arrow Electronics
19748 Dearborn S1.
Chatsworth, CA 91311
Tel: (818) 701-7500
TWX: 910:483-2086
Arrow Electronics
1502 Crocker Avenue
Hayward, CA 94544
Tel: (415) 487-4600

Arrow Electronics
1808 Tribute Road
SuiteC
Sacramento, CA 95815
Tel: (916) 925-7456
Arrow Electronics
9511 Ridgehaven C1.
San Diego, CA 92123
Tel: (619) 565-4800
TLX: 888064
Arrow Electronics
521 Weddell Ave.
Sunnyvale, CA 94086
Tel: (408) 745-6600
TWX: 910-338-0266

Hamilton Avnet
3002 E. "G" S1.
Ontario, CA 91764
Tel: (714) 989-9411
Hamilton Avnet
4103 Northgate Blvd.
Sacramento, CA 95834
Tel: (916) 925-2216
Hamilton Avnet
4545 Viewridge Ave.
San Diego, CA 92123
Tel: (619) 571-7500
Hamilton Avnet
1175 Bordeaux Dr.
Sunnyvale, CA 94089
Tel: (408) 743-3355
Hamilton Electro Sales
9650 DeSoto Ave.
Chatsworth, CA 91311
Tel: (818) 700-6500
Hamilton Electro Sales
Orange County
3170 Pullman Street
Costa Mesa, CA 92626
Tel: (714) 641-4100
Hamilton Electro Sales
10950 Washington Blvd
Culver City, CA 90230
Tel: (213) 558-2121
Kierulff Electronics
Corporate Marketing
10824 Hope Street
Cypress, CA 90630
Tel: (714) 220-6300
Kierul!f Electronics
5650 Jillson
Los Angeles, CA 90040
Tel: (213) 725-0325
TWX: 910-580-3106
Kierulff Electronics
8797 Balboa Ave.
San Diego, CA 92123
Tel: (619) 278-2112
Kierulff Electronics
1180 Murphy Ave.
San Jose, CA 95131
Tel: (408) 971-2600
Kierulff ElectroniCS
14101 Franklin Ave.
Tustin, CA 92680
Tel: (714) 731-5711
TWX: 910-595·2599
Schweber Electronics
21139 Victoiy Blvd.
Canoga Park, CA 91303
Tel: (213) 999-4702

Schweber Electronics
1771 Tribune Rd.
Suite B
Sacramento, CA 95815
Tel: (916) 929-9732
Schweber Electronics
6750 Nancy Ridge Drive
Suites 0 and E
San Diego, CA 92121
Tel: (619) 450-0454
Schweber Electronics
90 East Tasman Drive
San Jose, CA 95134
Tel: (408) 946-7171
TWX: 910-338-2043
Wyle Distribution Group
124 Maryland S1.
EI Segundo, CA 90245
Tel: (213) 322-8100
TWX: 910-348-7140
Wyle Distribution Group
17872 Cowan Ave.
Irvine, CA 92714
Tel: (714) 863-9953
TLX: 3719599
Wyle Distribution Group
11151 Sun Center Dr.
Rancho Cordova, CA 95670
Tel: (916) 638-5282
Wyle Distribution Group
9525 Chesapeake Dr.
San Diego, CA 92123
Tel: (619) 565-9171
TWX: 910-335-1590
Wyle Distribution Group
3000 Bowers Ave.
Santa Clara, CA 95051
Tel: (408) 727-2500
TWX: 9 t 0-338-0296
Wyle Laboratories
26560 Agoura Rd.
*203
Calabasas, CA 91302
Tel: (818) 880-9001
Wyle Military
18910 Teller Ave.
Irvine, CA 92715
Tel: (714)851-9953
TWX: 910-595-2642

Schweber EI,ectronics
8955 E. Nichols Ave., Suite 200
Englewood, CO 80112
Tel: (303) 799-0258
Wyle Laboratories
451 E. 124th Ave.
Thornton, CO 80241
Tel: (303) 457-9953
TWX: 910-936-0770

CONNECTICUT
Arrow Electronics
12 Beaumont Rd.
Wallingford, CT 06492
Tel: (203).265-7741
TWX: 710-476-0162
Hamilton/Avnet Electronics
Commerce Industrial Park
Commerce Drive
Danbury, CT 06810
Tel: (203) 797-2800
Kierulff Electronics
10 Capital Drive
Wallingford, CT 06492
Tel: (203) 265-1115

Lionex Corporation
170 Research Parkway
Meriden, CT 06450
Tel: (203) 237-2282
Schweber Electronics

Finance Drive
Commerce Industrial Park
Danbury;CT 06810
- Tel: (203) 748·7080
TWX: 710-456-9405

FLORIDA
Arrow Electronics
350 Fairway Drive
Deerfield Beach, FL 33441
Tel: (305) 429-8200
TWX: 510-955-9456
Arrow Electronics
1530 Bottle Brush
Palm Bay, FL 32905
Tel: (305) 725-1480
TWX: 510·959-6337
Hamilton/Avnet Electronics
6801 N.w. 15th Way
FI. Lauderdale. FL 33309
Tel: (305) 971-2900
Hamilton/Avnet Electronics

3197 Tech Drive North
SI. Petersburg, FL 33702
Tel: (813) 576-3930
Hamilton/Avnet Electronics
6947 University Blvd.
Winter Park, FL 32792
Tel: (305) 628-3888

.O~OIL.

AUTHORIZED DISTRIBUTORS

FLORIDA Icont.)

ILLINOIS Icont.)

MARYLAND Icont.)

MICHIGAN Icont.)

Kierulff Electronics
5410 NW. 33rd Ave.
Ft. Lauderdale, FL 33319
Tel: (305) 486-4004

Schweber Electronics
904 Cambridge Drive
Elk Grove Village, IL 60007
Tel: (312) 364-3774
TWX: 910-222-3453

Hamilton/Avnet Electronics
6822 Oak Hall Lane
Columbia, MD 21045
Bait. Sales: (301) 995-3500
Wash. Sales: 301-621-5410
Klerulff Electronics
825 D. Hammonds Ferry Road
Linthicun, MD 21090
Tel: (301) 636-5800
TWX: 710-234-1971

Hamilton/Avnet Electronics
32487 Schoolcraft Road
Livonia, MI48150
Tel: (313) 522-4700
Schweber Electronics
12060 Hubbard Ave.
Livonia, MI 48150
Tel: (313) 525-8100
TWX: 810-242-2983

Kierulff Electronics
3247 Tech Drive North
St. Petersburg, FL 33702
Tel: (813) 576-1966
TWX: 810-863-5625
Schweber Electronics
181 Whooping Loop
Altamonte Springs, FL 32701
Tel: (305) 331-7555
Schweber Electronics
2830 N. 28th Terrace
Hollywood, FL 33020
Tel: (305) 921 -0301
TWX: 510-954-0304

GEORGIA
Arrow Electronics
3155 Northwoods Parkway
Suite A
Norcross, GA 300?1
Tel: (404) 449-8252
TWX: 810-757-4213
Hamilton/Avnet Electronics
5825 D. Peachtree Corners E.
Norcross, GA 30092
Tel: (404) 447-7500
Kierulff Electronios
5824 Peachtree Corners E.
Norcross, GA 3.0092
Tel: (404) 447-5252
Schweber Electronics
303 Research Drive
Suite 210
Norcross, GA 300SQ
Tel: (404) 449-9170

ILLINOIS
Arrow Electronics
2000 Algonquin
Schaumburg, Il60195
Tel: (312) 397-3440
TWX: 910-291-3544
Hamilton/Avnet Electronics
1130 Throndale Aye.
Bensonville, IL 60106
Tel: (312) 860-7700
Kierulff Electronics
1140 Wesl Throndale
Itasca, IL 60143
. Tel: (312) 250-0500
.Newark Electronics
4801 North Ravenswood
Chicago, IL 60640
Tel: (312) 784-5100
TWX: 910-221-0268
Newark Electronics
5308 West 124th St.
AlSip, IL 60658-3295
Tel: (312) 371-9000

INDIANA
Advent Electronics
8446 Moller Rd.
Indianapolis, IN 46268
Tel: (317) 872-4910
TWX: 810-341-3228

Arrow Electronics
2495 Directors Row
Suite H
Indianapolis, IN 46241
Tel: (317) 243-9353
Hamilton/Avnet Electronics
485 Gradle Dr.
Carmel, Indianna 46032
Till: (317) 844-9333

IOWA
Advent Electronics
682 58th Avenue
Court SW.
Cedar Rapids, IA 52404
Tel: (319) 363-0221
TWX: 910-525-1337

Arrow Electronics
375 Collins Road N.E.
Cedar Rapids, IA 52402
(319) 395-7230
Hamilton/Avnet Elec'tronics
915 33rd Avenue SW.
Cedar Rapids, IA 52404
Tel: (319) 362-4757
TWX: 910-525-1316
Schweber Electronics

5720 N. Park Place N.E.
Cedar Rapids, IA 52402
Tel: (319) 373-14-17

KANSAS
Hamilton/Avnet Electronics
9219 Quivira Road
Overland Park, KS S62 t 5
Tel: (913) 888-8900

Schweber Electronics
10300 W. 103rd
Suite'103
Overland Park, KS 66214
Tel: (913) 492-2922

MARYLAND
Arrow Electronics
8300 GUilford Road
Suite H
Columbia, MD 21046
Tel: (301) 995-0003
TWX: 710-236-9005

Lionex Corp.
9020 Mendell Hall Court
Columbia, MD 21045
Tel: (301) 964-0040
Schweber Electronics
9330 Gaither Rd.
Gaithersburg, MD 20877
Tel: (301) 840-5900
TWX: 710-828-9749

MASSACHI,ISETTS
Arrow ElectroniCS
Arrow Drive
Woburn, MA 01801
Tel: (617) 933-8130
TWX: 71D-393-6770
Gerber Electronics

128 Carnegie Row
Norwood, MA 02062
Tel: (617) 769-6000
TWX: 710-336-1987

HamiltontAvnet Electronics
50 Tower Office Park
Woburn, MA01801
Tel: (617) 273-7500
Kierulff Electronics
13 Forturn Dr.
Billerica, MA 01821
Tel: (617) 667-8331
TWX: 710-390-14.49
Lionex Corporation
36 Jonspin Rd.
Wilmington, MA 01887
Tel: (617) 657-5170
Schweber Electronics
25 Wiggins Ave.
Bedford, MA 01730
Tel: (617) 275-5100
TWX: 710-326-0268

. MICHIGAN
Arrow Electronics
755 Phoenix Drive
Ann Arbor, MI 48104
Tel: (313) 971-8220
TWX: 810-223-6020
Arr-:.:Jw Electronics
3510 Roger Chaffee Blvd .. S.E.
Grand Rapids, MI 49508
Tel: (616) 243-0912
Hamilton/Avnet Electronics
2215 29th St" S.E.
Space A-5
Grand Rapids, MI 49508
Tel: (616) 243-8805

MINNESOTA
Arrow Electronics
5230 W. 73rd Street
Edina, MN 55435
Tel: (612) 830-1800
TWX: 910-576-3125
Hamilton/AI/net Electronics
10300 Bren Rd., East
Minnetonka, MN 55343
Tel: (612) 932-0600
Kierulff Elec'tronics
7667 Cahill Road
Edina, MN 55435
Tel: (612) 941-7500
TWX: 910-576-2721
Schweber Electronics
7424 W. 78th Slreet
Edina, MN 55435
Tel: (612) 941-5280
TWX: 910-576-3167

MISSOI,IRI
Arrow Electronics
2380 Schuetz Rd.
St. Louis, MO 63416
Tel: (314) 567-6888
TWX: 910-764-0882
Hamilton/Avnet Electronics
13743 Shoreline Court East
Earth City, MO 63045
Tel: (314) 344-1200
Kierulff Electronics
2608 Metro Boulevard
Maryland Heights, MO 63043
Tel: (314) 739-0855
Schweber Electronics
502 Earth City EXpwy.
Suite 6203 .
Earth City, MO 63045
Tel: (314) 739-0526

NEW HAMPSKIRE
Arrow Electronics
Three Perimeter Road
Manchester, NH 03103
Tel: (603) 668-6968
TWX: 710-220-1684
Hamllton/Avne! Electronics
444 E. Industrial Park Drive
Manchester, NH03104
Tel: (603) 624-9400
Schweber Electronics
Bedford Farms, Bldg. 2
1st Floor
Kitton & South River Rd.
Manchester, NH 03102
Tel: (603) 625-2250
TWX: 710-220-7572

.B~Dll ,AUTHORIZED,DISTRIBUTORS
NIWJIRSIY

NEW YORK ,oo"t.)

Arrow Electronics
2 Industrial Road
Fairfield, NJ 07006
Tel: (201) 575-5300
TWX: 71'0-734-4403

Arrow Electronics
25 Hub Drive
Melville, NY 11747
Tel: (516) 391-1300
TV>!X: 510-224-6126

Arrow Electronics
6000 Lincoln Drive East
Marlton, NJ 08053
Tel: (609) 596-8000
TWX: 710·897-0829

Arrow Electronics
3375 Brighton Henrietta
Townline Road
Rochester, NY 14623
Tel: (716) 427-0300
TWX: 510-253-4766

Hamilton/Avnet Electronics
1 Keystone Ave,
Bldg, #36
Cherry Hill, N,J, 08003
Tel: (609) 424-0110
Hamiiton/AvnetElectronics
10 Industrial Rd,
Fairfield, N,J, 07006
Tel: (201) 575·3490
(201) 575-3390
Kierullf Electronics
37 Ku!ick Road
Fairfie,ld, NJ 07006
Tel: (201) 575·6750
TWX: 7;0·734-4372
Kierullf Electronics
520 Fellowship Road
Suite A 106
Mt Laural, NJ 08054
Tel: (609) 235-1444

Lionex
311 AI, 46 West
Fairfield, NJ 07006
Tel: (201)227·7960
Schweber Electronics
18 Madison Rd,
Fairlield, NJ 07006
Tel: (201) 227-7880
TWX: 710-734-4305

N.W ••XICO

Avnet, Inc,
767 Fifth Avenue
New York, NY 10153
Tel: (212) 644-1050
Hamilton Avnet
933 Motor Parkway
Hauppauge, NY 11787
Tel: (516) 231-9800
Hamilton/Avnet Electronics
103 Twin Oaks Drive,
Syracuse, NY 13214
Tel: (315) 437·2641
Hamilton/Avnet Electronics
333 Metro Park
Rochester, NY 14623
Tel: (716) 475·9130
Hamilton/Avnet Export
1065 Country Road
Suite 211A
Westbury, NY 11590
Tel: (516) 997-6868
Lionex Corporation
400 Oser Ave,
Hauppauge, LI, NY 11787
Tel: (516) 273-1660
Rome Electronics
216 Erie Blvd" E,
Rome, NY 13440
Tel: (315) 337·5400

NORTH CAROLINA 10.l'It.) OHIO Icont.)
' Hamilton/Avnet Eleetronics
3510 spnn~ Forest Road
Raleigh, N' 27604
Tel: (919) 878-08)0
Kierullf Electronics
1 North Commerce Center
5249 North Boulevard
Raliegh, NC 27604
Tel: (919) 872-8410
Schweber Electronics
1 Commerce Center
5285 North Blvd,
Raleigh, NC 27604
Tel: (919) 876·0000

Arrow Electronics
4719 S, Memorial
Tulsa, OK 74145
Tel: (918) 665-7700

OHIO
Arrow Electronics
7620 McEwen Road
Centerville, OH 45459
Tel: (513) 435-5563
TWX: 810-459-1611

Norvell Electronics
12210 E, 52nd Sf.
Suite 105UB5
Tulsa, OK 74146
Tel: (918) 254-8606

Arrow Electronics
1040 Crupper Avenue
Columbus, OH 43229
Tel: (614) 885·8362
Arrow Electronics
6239 Cochran
Solon, OH 44139
Tel: (216) 248·3990
TWX: 810-427-9409

Schweber Electronics
4815 S, Sheridan Road
Suite #109
Tulsa, OK 74145
Tel: (918) 622·8000

Electronics Marketing

Corporation
17 Alpha Park
Highland Heights, OH 44143
Tel: (216)442·3441,
Electronics Marketing
Corporation
1150 W, 3rd Ave,
Columbus, OH 43212
Tel: (614) 299·4161
Eleclronics Marketing
Corporation
4660 Gateway Circle
Kettering, OH 45440
Tel: (513)439-471,1

~~~U&~~~:5_~~g7106

Schweber Electronics
Jericho Turnpike
Westbury, NY 11590
Tel: (516) 334·7474
TWX: 510·222·3660

Hamilton/Avnet Electronics
4588 Emery Industrial Parkway
Cleveland"OH 44128
Tel: (216) 831-3500

NIWYORK

NORTH CAROLINA

Arrow Electronics
155 Sherwood Ave,
Farmingdale, NY 11735
Tel: (516) 293-6363

Arrow Electronics
5240 Greens Dairy Rd,
Raleigh, NC 27604
Tel: (919) 876·3132

Arrow Electronics
20 Oser Ave,
Hauppauge, NY 11787
Tel: (516) 231·1000
TWX: 510·227·6623

Arrow Electronics
938 Burke SI.
Winston-Salem, NC 27102
Tel: (919) 725·8711
TWX: 510-931-3169

Arrow Eleclronics
7705 Ma~lage Dr.
Liverpool, NY 13088
Tel: (3.15) 652-1000
TWX: 710·545-0230

Electronics Marketing
Corporation
19251·85 South
Charlotte, NC 28208
Tel: (704) 394-6195

Hamilton/Avnet Electronics
2524 Baylor S,E,

OKLAHOMA

Kierulff Electronics
12318 E, 60th SI.
Tulsa, OK 74145
Tel: (918) 252·7537
TWX: 910-845-2150

Schweber Electronics
4 Townl/ne Circle
Rochester, NY 14623
Tel: (716) 424-2222

Arrow Electronics
2460 Alamo Avenue, S.E.
Albuquerque, NM 87106
Tel: (505) 243·4566
TWX: 910-989-1679

Schweber Electroryics
7865 Paragon Road
Suite 210
Dayton, OH 45459
Tel: (513) 439-1800

Hamilton/Avnet ElectroniCS
954 Senale Drive
Dayton, OH 45459
Tel: (513) 433-0810
Hamilton/Avn.l ElectroniCS
777 Brooksedges Boulevard
Westerville, OH 43081
Tel: (614) 882-7004
Kierulff Electronics
23060 Miles Rd,
Bedford Heights, OH 44128
Tel: (216) 587·6556
TWX: 810-427-2282
Kierullf Electronics
476 Windsor Park Drive
Dayton, OH 45459
Tel: (513) 439-0045
Schweber Electronics
23880 Commerce Park Rd,
Beachwood, OH 44122
Tel: (216) 464-2970

OREOON
Arrow Electronics
10260 SW, Nimbus Avenue
Suite M3
Tigard, OR 97223
Tel: (503) 684-1690
Hamilton/Avnet Electronics
6024 SW, Jean Rd,
Bldg, C, Suite 10
Lake Oswego, OR 97034
Tel: (503) 635·8157
Kierulff Electronics
14273 NW, Science Park Dr.
Portland, OR 97229
Tel: (503) 641·9150
TWX: 910·467-8753
Wyle Distribution
5289 N,E, Elam Young Pkwy,
Bldg, El00
Hillsboro, OR 97123
Tel: (503) 640·6000'
TWX: 910·460-2203

"NNSYLVANIA
Arrow ElectroniCS
650 Seco Rd,
Monroeville, PA 15146
Tel: (412) a56·7000
TWX: 710-797 -3894
Hamiiton/AvnEit Electronics
2800 Liberty Avenue
Building E
Pittsburgh, PA 15222
Tel: (412) 281-4150
TWX: 710·670·1127
LionexCorp,
101 Rock Road
Horsham, PA 19044
Tel: (215) 443-5150

.O~OIL

AUTHORIZED DISTRIBUTORS

PENNSYLVANIA (cont.)

TEXAS (cont.)

WASHINGTON

Schweber Electronics

Norvell Electronics

Arrow Electronics

Hamilton Avnet Electronics

Prudential Business Campus

5800 Corporate Dr.
SUite C5
Houston, TX 77036
Tel: (713) 777-1666

14320 Northeast 21 st Street
Bellevue, WA 98007
Tel: (206) 643-4800

6845 Redwood Road, Unit 3, 4, 5

Schweber Electronics

14212 N.E. 21st SI.
Bellvue, WA 98007
Tel: (206) 643-3950

231 Gibraltar Road
Horsham, PA 19044
Tel: (215) 441-0600
TWX: 510-665-6540

Schweber Electronics
1000 RIDC Plaza Suite #203
Pittsburg, PA 15238
Tel: (412) 782-1600

6300 La Calma Dr.
Suite 240
Austin, TX 78752
Tel: (512) 458-8253

TEXAS

Schweber Electronics

Arrow Electwnics
2227 West Braker Lane
Austin, TX 78758
Tel: (512) 835-4180
TWX: 910-874-1348

Arrow Electronics
3220 Commander Drive
Carrollton, TX 75006
Tel: (214) 380-6464
TWX: 910-860-5377

Arrow Electronics
10899 Kinghurst Dr.
Suite 100
Houston, TX 77099
Tei: (713) 530-4700

Hamilton/Avnet Electronics
2401 Rutland Dr.
Austin, TX 78758
Tel: (512) 837-8911

Hamilton/Avnet Electronics
8750 Westpark Dr.
Houston, TX 77063
Tel: (713) 780-1771

Hamilton/Avnet Electronics
2111 West Walnut Hili Lane
Irving, TX 75062
Tel: (214) 659-4100

Kierulff Electronics
3007 Longhorn Blvd.
Suite 105
Austin, TX 78758
Tel: (512) 835-2090
TWX: 910-873-1359

Kierulff Electronics
9610 Skillman Ave.
Dallas, TX 75243
Tel: (214) 343-2400
TWX: 910-861-2150
Kierulff Electronics
10415 Landsbury Dr.
Suite 210
Houston, TX 77099
Tel: (713) 530-7030
TWX: 910-880-4057

Norvell ElectroniCS
8705 Shoal Creek Blvd.
Suite 105
Austin, TX 78758
Tel: (512) 458-8106

Norvell Electronics
14410 Midway Rd.
P.O. Box 801207
Dallas, TX 75380
Tel: (214) 233-0020

4202 Beltway
Dallas, TX 75234
Tel: (214) 661-5010
TWX: 910-860-5493

Schweber Electronics
10625 Richmond Ave.
Suite #100
Houston, TX 77042
Tel: (713) 784-3600
TWX: 910-881-4036

Hamdton/Avnet Electronics

2795 Rue Halpern
Ville SI. Laurent, Montreal
Canada H45 1P8
Tel: (514) 335-1000

WISCONSIN

2550 Boundary Rd.
Suite 115
Burnaby, B.C.
Canada V5M 3Z3
Tel: (604) 437-6667

Arrow Electronics
200 North Patrick Blvd.
Brookfield, WI 53005
Tel: (414) 792-0150

2236 W. Bluemound Rd.
Waukesha, WI 53186
Tel: (414) 784-8160
TWX: 910-265-3653

1515 W. 2200 South
Salt Lake City, UT84116
Tel: (801) 972-0404
Hamilton/Avnet Electronics
1585 West 2100 South

~;:~ (~~~) ~~t~:2~6t4119
Kierulff ElectronIcs
2121 South 3600West
Salt Lake City, Utah 841.19
Tel: (801) 973-6913
TWX: 910-925-4072
Wyle Distribution Group
1959 S. 4130 West, Unit B
Salt Lake City, UT 84104
Tel: (801) 974-9953

VIRGINIA
Arrow Electronics
Kroger Executive Park
8002 Discovery Drive
Campbell Bldg., Suite 214

Richmond, Virginia
Tel: (804) 282-0413
TWX: 710-956-0169

190 Colonnade Road

Nepean, Ontario

Wyle Distribution Group
1750 132nd Ave., NE
Bellevue, WA 98005
Tel: (206) 453,8300
TWX: 910-443-2526

Wyle Distribution Group
11001 S Wilcrest
Suite 100
Houston, TX 77099
Tel: (713) 879-9953

UTAH

Hamilton Avnet Electronics
Canada K2E 7L5
Tel: (613) 226-1700
TLX 053-4971

2975 S. Moorland Rd.
New Berlin, WI 53151
Tel: (414) 784-4518

Arrow Electronics

Mississauga,Ontano
Canada L4V 1R2
Tel (416) 677-7432
TWX: 610-492-8867

Kierulff Electronics
19450 68th Ave. S.
Kent, WA 98032
Tel: (206) 575-4420

Wyle Distribution Group
2120 W_ Breaker Lane
Suite F
Austin, TX 78758
Tel: (512) 834-9957
TWX: 710-378-7282

Wyle Distribution Group
1810 N. Greenville Avenue
Building A
Richardson, TX 75081
Tel: (214) 235-9953
TWX: 310-378-7663

CANADA (cont.)

Hamilton/Avnet Electromcs

Kierulff Electronics

Marsh Electronics
1563 S. 101 SI.
Milwaukee, WI 53214
Tel: (414) 475-6000

Hamilton Avnet International

HamIlton Avnet Electronics

Zentronics
8 Tilbury Court

Bramptan, Ontario
Canada L6T 3T4
Tel: (416) 451-9600
TLX: 06-97678

Zentronics
3300-14 Ave N.E.'
Calgary, Alberta
Canada T2A 6J4
Tel: (403) 272-1021

Zentron;cs
155 Colonnade Rd.
Unit 17 & 18

Schweber E!ectronics

Nepean, Ontario

150 Sunnyslope Road
Suite 120
Brookfield, WI 53005
Tel: (414) 784-9020

Canada K2E 7K 1
Tel: (613) 226-8840 .

CANADA
Canadian GE-ECO
189 Duffenn SI.

Zentronics
108-11400 Bndgeport Road
Richmond, BC
Canada V6X 112
Tel: (604) 273-5575

Toronto, Ontano

Zentronlcs

Canada M6K 1Y9
Tel: (416) 530-2895
TLX: 06-23238

SL Laurent, Quebec

Canadian GE·ECO
203 Colonnade Rd.

Nepean, Ontario
Canada K2E 7K3
Tel: (613) 723-0336

Electro Sonic
1100 Gordon Baker Rd.
Willowdale, Ontaflo
Canada M2H SB2
Tel: (416) 494-1555
TLX: 065-25295

Hamilton Avnet Electronics
2816 21st Street N.E ..
Calgary, Alberta
Canada T2E 6Z2
Tel: (403) 230-3586
TWX: 038-27642

505 Locke Street
Canada, H4T tX7
Tel: (514) 735-5361
TLX: 05-827535

Zentronics
564 Weber SI. N.
Unit 10

Waterloo, Ontario
Canada N2L 5C6
Tel: (519) 884·5700

Zentronics
590 Berry Street

Winnipeg, Manitoba
Canada R3H OS 1
Tel: (204) 775-8661

Zentronics
#210-3501 8th SI. East

Saskatoon, Saskatchewan
Canada, S7H OW5
Tel: (306) 955-2202

.D~Dlb INTERNATIONAL SALES OFFICES
INTERNATIONAL
MARKETING
HEADQUARTERS

FRANCE

UNITED KINGDOM

Intersillnc
10600 Ridgeview Court
Cupertino CA 95014

HONG KONG

RG21 2YS

USA
Tei (408) 996-5000
TWX 91 O~338~Oo33
(INTRSLINT ePTOI

EUROPEAN
HEADQUARTERS

G

WEST GERMANY

ITALY

JAPAN
3rd FI

SPAIN
KOREA
BENELUX
ASIA AND PACIFIC
HEADQUARTERS
SWEDEN
DIVISion

SINGAPORE
of G E

.D~DIl.

INTERNATIONAL
DISTRIBUTOR OFFICES

AUSTRALIA

HONG KONG

ITALY Icont.)

MALAYSIA

R&D Electronics Pty.. Ltd.
4 Florence Street Po. Box 206
Burwood, Vic·toria 3125
Australia
Tel: 288·8911/8232/8262
TLX: RADET AA 33288

Conmos Products, Ltd.
11th Fir. Hay-Nien Building
#1 Tai Yip SI.
Kwun Tong, Kowloon
Hong Kong
Tel: 3·7560103·8
TLX: 85448 CMOS HX

Eledra 3S SPA
Via Turazza, 32/41
35100 Padova
Italy
Tel: (49) 655488-655749
TLX: 430444

NIE Electronics (M) SDB BHD
P.O.Box 12167 Lot 2.22 2nd Floor

R&D Electronics Pty., Ltd.
133 Alexander SI.
PO. Box 57
Crows Nest NSW 2065
Sydney
Australia
Tel: 439·5488
TLX: SECCO AA25468

Electrocon Products. Ltd.
Rm 603. 6th Floor
Perfect Commercial Bldg.
20 Austin Avenue, TSimshatsui
Kowloon
Hong Kong
Tel: 3-687214-6
TLX: 39916 EPLET HX

EUrelletronica
Via Mascheroui, 19
20125 Milano
Italy
Tel: 4981851
TLX: 332102

Pantronic
Via Mattia Battistini. 212A
00167
Roma
AUSTRIA
Italy
Transistor Vertriebsges m.b.H. & INDIA
Tel: 6273909
Co.. KG.
Kaytronics Electronics Engineer TLX: 612405
204, 2nd Fl.. Karan Centre
Auhofstrasse 41 A
A-1130 Vienna
P.B. No. 45, Sarojini Revi Rd.
JAPAN
Austria
Seconuderabad 500 003
Internix, Inc.
Tel: (0222) 829401·0
India
Shinjuku Hamada Bldg.
TLX: 133738 TVGWN A
Tel: 77924
(7th Floor)
TLX: 155 6707
7·4·7 Nishi Shinjuku
BELGIUM
ShinfUku-Ku
INDIA-U.S.
OFFICE
Master Chips SPRL
Tokyo 160.
Blvd. SI. Lazare 4
Fegu Electronics
Japan
1210 Brussels
2584 Wyandotte SI.
Tel: (03) 369-1101
Belgium
Mountain View, California 94043 TLX: INTERNIX J26733
Tel: (02) 219.58.62
U.SA
Intern ix, Inc.
(02) 219.14.84
Tel: (415) 961-2380
TLX: 62500 MASTER B
TLX: 176572 FEGU ELEC MNTV Arai Bldg
5·3·36 Tokiwagi
Uedashi, Nagano 386
DENMARK
ISRAEL
Japan
E.V. Johanssen Eleclronik AS
Vectronics, Ltd.
Tel: (0268) 25·1610
15, Titangade
60 Medinat Hayehudim SI.
Internix. Inc.
DK-2200 Copenhagen N
P.O. Box 2024
Sobajima Daini Noritake Bldg.
Herzlia B 46120
Denmark
1·9-9 Noritake
Tel: 45·1-839022
Israel
Nakamura-Ku. Nagoya 453
TLX: 16522 EVICAS DK
Tel: (052) 556070
Japan
TLX: 342579 VECO IL
Tel: (052) 452·8841
FINLAND
Nabla Elektronlikka Oy
P.O. Box 3
SF-02101 Espoo 10
Finland
Tel: 90462829 or 4552955
TLX: 124270 NABLA SF

FRANCE
C.C.1.
Zone Industrielle
5, Rue Marcelin Berthelot
92160 Antony

France
Tel: (1) 666.21.82
TLX: 203881 F
C.C.1.
67, Rue Bataille
69008 Lyon

France
Tel: (78) 742375
TLX: 375456
Tekelec-Airtronic
BP. No.2
Cite des Bruyeres

Rue Carle·Vernet
92310 Sevres
France

Tel: (1) 534'.75.35
TLX: TKLEC A 204552F

ITALY

Eledra 3S S.P.A.
Viale Elvezia. 18
20154 Milano
Italy
Tel: (2) 349 751
TLX: 332 332
Eledra 3S S.PA
Via Paolo Galdano, 141/D
10137 Torino
Italy
Tel: (11) 3099111·2·3
TLX: 210632
Eledra 3S S.PA
Via G. Valmarana, 63

00139 Roma
Italy
Tel: (6) 8110151
TLX: 612051
Eledra 3S S.P.A
Via Zaccherini AlVIS!, 6
40138 Bologna
Italy
Tei: (51) 307781·340999
TLX: 213406

Internix. Inc.
Takahashi Bldg. (Nishikan)
4·4·13 Nishi-Tenma, Kita-Ku
Osaka 530
Japan
Tel: (06) 364-5971

Komplex Setangor Jatan Sultoan

Kuala Lumpur
Malaysia
Tel: 03-224344
TLX: NIE MA 31231
NIE Comptronics SDN BHD
14 Jalan Pahang, Penaog
MalaYSia
Tel: 362118 362200 362194
TLX: NIECOM MA 40608

NETHERLANDS
Auriema Nederland B. V.
Doornakkersweg 26
5642 MP Eindhoven
Netherlarids:.
Tel: 040-816565
TLX: 51992 AURI NL,

NEW ZEALAND
Delphi Industries. Ltd.
27 Ben Lomond Crescent
Pakuranga, Auckland
New Zealand
Tel: 563-259
TLX: DELPHIC NZ21992

NORWAY
Hans H. Schive AIS
P.O. Box 15
Holmengt. 28
N·1360 Nesbru

Norway
Tel: (02) 84-51-60
TLX: 19124 SKIVE N

PORTUGAL
Decada Espectral
de Electronica e
Cie~tlficos. SARL
Av. Bombeiros Voluntarios. Lote
102B
Mirafiores/Alges
1495 Lisboa
Portugal
Tel: 2-103420
TLX: 15515 ESPEC P
Eq~ipamentos

Internix, Inc.
Hachioji Technical Center
SOUTH AFRICA
2-5-1 Ouwada·cho Hachioji 192
Electronic Bldg. Elements Pty.. Ltd.
Japan
P.O. Box 4609
Tel: (0426) 44-8671
Pretoria 0001
Intern ix, Inc.
Republic of South Africa
Sunlife Dai-san Bldg.
Tel: 46-9221/7
2-5-19 Hakataeki-Higashi
TLX: 20723 SA
Hakata-Ku, Fukuoka 812
22786 SA
Japan
Tel: (092) 472-7716
SOUTH AMERICA-

KOREA
Duksung Trading Co.
Room 301 Jinwon Bldg.
507·30 Sinrim 4·Dong
Gwanak·Ku, Seoul
Republic of Korea

Tel: 856·9764
TLX: DUKSUNG K23459

U.S. OFFICE
Intectra
2629 Terminal Blvd.
Mountain View, California 94043
U.S.A.
Tel: (415) 967-8818
TLX: 345·545 INTECTRA MNTV

.D~DlL INTERNATIONAL
DISTRIBUTOR OFFICES
SPAIN

UNITED KINGDOM

WEST GERMANY (cont.)

AmitronS.A
Avemda Valiadolid, 47-A
28008 Madrid
Spain
Tel: (01) 247931312479332
TLX. 45550 AMIT E

Farnell Electronic'Components,

B!lronic GrrlbH
Sommerfield ring 35
1000 Berlin 39

Ltd.
'Canal Road
Leeds, LS12 2NE
England
Tel (0532) 636311
TLX: 55147 FEC G

SWEDEN
Svensk Teleimport AB
Box 5071
S'I62 05 Valiingby
Sweden

Tel: 08-890265
TLX: 15372 TIMP S

SWITZERLAND
Laser & Electronic Equipment

Hawke Elect., Ltd

Amotex House
45, Hanworth Rd.
Sunbury on Thames
Middx
England
Tel: (01979) 7799
TLX: 923592

West Germany

Tel 0 3018 05 25 26
Bltronic GmbH
Hanauer Str. 39
6360 Friedberg
Frankfurt
West Germany

Tel: 06031/9047
TLX: 4184050 BIT D
Speziai-Electronic KG
Hermann-Linggstr. 16
8000 Muenchen 2

Jermyn Distribution, Ltd.

West Germany

8053 Zurich

Vestry Estate
Seven Oaks

Tel: 891530387
TLX 5212176 SPEZ D

Switzerland

Kent
England
Tel: (0732) 450144
TLX: 95142

Kreuzbreite 14
3062 Bueckeburg

Eierbrechtstrasse 47

Tel 01 55 33 30
TLX: 52124 LASEQ CH

, Laser & Electronic Equipment
Bureau Suisse Romande
1 Avenue Industrielie
1227 Carouge-Geneve
Switzerland
Tel' 022 425 677
TLX: 421 343

TAIWAN
Galaxy Far East Corp.
Room 4, 2nd FI., No. 312
Sec. 4 Chung Hsaio East Rd.
P.O. Box 36-12 Taipei
Taiwan, R,O.C.
Tel: (02) 7811895-7
Cable: GALAXYER
TLX: 26110 GALAXYER

THAILAND
Grawlnner Company limited

226127 Phahonyothln Rd.
Phyathai Bangkok 10400
Thailand
Tel 278-3411
TLX: 87155 GWN TH

TURKEY
Turkelek Elektronlk, Ltd
Hatay Sokak #8
Ankara

Turkey
Tel: 41-2521091189483
TLX 42120 TRKL TR
Turkelek Elektronik, Ltd

West Germany

Macro-Marketing, .Ltd.
Burnham Lane

Slough, Berks SL1 6LN
England
Tel: (06286) 4422,
TLX: 847945 MACRO G

Tel: (05) 722 2030
TLX: 971624 SPEZ D
Spezial-Electronlc KG
Magdeburgerstrasse 15

7090 Ellwangen
West Germany
The RadiO Resistor Co
Tel. (07) 961 4047
Cambridge Road, S1. Martin's Way TLX: 74712 SPEZ D
Bedford
England
Spezial-Electronic KG
Tel' (0234) 47211
Hanauer Str. 4
TLX: 82651
6360 Friedberg
West Germany

Trident Microsystems, Ltd.
Trident House
53 Ormside Way
Redhlli, Surrey RH1 2LS
England
Tel: (0737) 69217
TLX: 8953230 TRELEC G

WEST GERMANY
Bitronic GmbH
Dingolflnger Strasse 6
8000 Muenchen 80
West Germany

Tel: 089149160101
TLX: 5212931 BIT D
Bitronic GmbH
Dieselstrasse 30

7016 Gerlingen
West Germany

Kemeralti Cad. Tophane Ishanl Tel: 0 71 56124051

406
Istanbul
Turkey
Tel: 1-143126811434046
TLX 22036

Spezial-Electronic KG

TLX: 7266743 BIT D
BitronlC GmbH
Karl-Marx-Strasse 59

4600 Dortmund 1
West Germany
Tel: 02 31152 82 93
TLX 822 664 BIT D

Tel: (06) 031 4634
TLX: 4184025 SPEZ D



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