1986_Intersil_Component_Data_Catalog 1986 Intersil Component Data Catalog

User Manual: 1986_Intersil_Component_Data_Catalog

Open the PDF directly: View PDF PDF.
Page Count: 1098

Download1986_Intersil_Component_Data_Catalog 1986 Intersil Component Data Catalog
Open PDF In BrowserView PDF
-UU:I
Component Data
Catalog

1986

CAUTION: Intersil's products are not intended for use as components in any life support or other medical
devices intended for surgical implant into the human body,
Intersil cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an Intersil product. No circuit patent
licenses are implied. Intersil reserves the right to change the circuitry and specifications without notice at any time.
Printed in U.S.A. © Copyright !985, Intersil, Inc., All Rights Reserved

@isaregisteredtrademarkOfGeneral Electric Company, U.S.A.

Table of Contents
Description

Page

Section 1

Selector Guides .................................................................... 1-1

Section 2 -

Discretes

2N2607 P-Charinel JFET General Purpose Amplifier ....................................................... 2-1
2N2608 P-Channel JFET General Purpose Amplifier ....................................................... 2-1
2N2609 P-Channel JFET General Purpose Amplifier ........................................................ 2-1
2N2609JAN P-Channel JFET General Purpose Amplifier .................................................. 2-1
2N3684 N-Channel JFET Low Noise Amplifier ........................ , ...................................... 2--2
2N3685 N-Channel JFET Low Noise Amplifier ......................... ~ ..................................... 2-2
2N3686 N-Channel JFET Low Noise Amplifier ............................................................... 2-2
2N3687 N-Channel JFET Low Noise Amplifier ............................................................... 2-2
2N3810/A Dual Matched PNP General Purpose Amplifier ................................. ~ ............... 2-3
2N3811/ A Dual Matched PNP General Purpose Amplifier ................................ ; ................. 2--3
.2N3821 N-Channel JFET High Frequency Amplifier ........................................................ 2-5
2N3821JAN N-Channel JFET High Frequency Amplifier .................... ~ ............................... 2-5
2N3821JTX N-Channel JFET High Frequency Amplifier .................................................... 2-5
2N3821JTXV N-Channel JFET High Frequency Amplifier .................................................. 2-5
2N3822 N-Channel JFET High Frequency Amplifier ........................................................ 2-5
2N3822JAN N-Channel JFET High Frequency Amplifier ............... : ............ : ...................... 2-5
2N3822JTX N-Channel JFET High Frequency Amplifier .................................................... 2-5
2N3822JTXV N-Channel JFET High Frequency Amplifier ........•.................. , ...................... 2--5
2N3823 N-Channel JFET High Frequency Amplifier ........................................................ 2-7
2N3823JAN N-Channel JFET High Frequency Amplifier ................................................... 2-7
2N3823JTX N-Chan.nel JFET High Frequency Amplifier .................................................... 2-7
2N3823JTXV N-Channel JFET High Frequency Amplifier ......... , ..... , .......•.......................... 2-7
2N3824 N-Channel JFET Switch ........................................... , ..................................... 2-8
2N3921 Dual N-Channel JFET (3eneral Purpose Amplifier ................................................ 2-9
2N3922 Dual N-Channel JFET General Purpose Amplifier ................................................ 2-9
2N3954 Dual N-Channel JFET General Purpose Amplifier ............................... , ............... 2 -11
2N3954A Dual N-Channel JFET General Purpose Amplifier ............................................. 2-11
2N3955 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-11
2N3955A Dual N-Channel JFET General Purpose Amplifier., ........................................... 2-11
2N3956 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-11
2N3957 Dual N-Channel JFET General Purpose Amplifier ., .......................... , .................. 2-11
2N3958 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-11
2N3970 N-Channel JFET Switch ...........................................................'..................... 2-13
2N3971 N-Channel JFET Switch ................................................................................ 2-13
2N3972 N-Channel JFET Switch ................................................................................ 2"': 13
2N3993 P-Channel JFET General Purpose Amplifier/Switch ..................... , ...... : ................ 2-15
2N3994 P-Channel JFET General Purpose Amplifier/Switch ............................................. 2-15
2N4044 Dielectrically Isolated Dual NPN General Purpose Amplifier ................................... 2-17
2N4045 Dielectrically Isolated Dual NPN General Purpose Amplifier ................................... 2-17
2N4100 Dielectrically Isolated Dual NPN General Purpose Amplifier ................................... 2-17
2N4878 Dielectrically Isolated Dual NPN General Purpose Amplifier ................................... 2-17
2N4879 Dielectrically Isolated Dual NPN General Purpose Amplifier .................................... 2-17
2N4880 Dielectrically Isolated Dual NPN General Purpose Amplifier ................................... 2 -17
ITE4091 N-Channel JFET Switch ............................................................................... 2-19
2N4091 N-Channel JFET Switch ................................................................................ 2-19
2N4091 JANTX N-Channel JFET Switch ...................................... , .............................. 2-19

Table
. of Contents
,

Page

Description

Section 2

Discretes (Cont.)

ITE4092 N-Channel JFET Switch ........................ '....................................................... 2-19,
2N4092 N-Channel JFET Switch ............................................................... " ............... 2-19
2N4092 JANTX N-Channel JFET Switch ..................................................................... 2-19
ITE4093 N-Channel JFET Switch ....................................................... , ....................... 2-19
2N4093 N-Channel JFET Switch ................................................................................ 2-19
2N4093 JANTX N-Channel JFET Switch .................. : .................................................. 2-19
2N4117 N-Channel JFET General Purpose Amplifier ...................................................... 2-21
2N4117A N-Channel JFET General Purpose Amplifier .................................................... 2-21
2N4118 N-Channel JFET General Purpose Amplifier ...................................................... 2;...21
2N4118A N-Channel JFET General Purpose Amplifier .................................................... 2-21
2N4119 N-Channel JFET General Purpose Amplifier ...................................................... 2-21
2N4119A N-Channel JFET General Purpose Amplifier .................................................... 2-21
2N4220 N-Channel JFET General Purpose Amplifier/Switch ............................................ 2-22
2N4221 N-Channel JFET General Purpose Amplifier/Switch ............................................ 2~22
2N4222 N-,Channel JFET General Purpose Amplifier/Switch ............................................ 2-22
2N4223 N-Channel JFET High Frequency Amplifier ....................................................... 2-23
2N4224 N-Channel JFET High Frequency Amplifier ....................................................... 2-23
2N4338 N-Channel JFET Low Noise Amplifier .............................................................. 2-24
2N4339 N-Channel JFET Low Noise Amplifier ...... ~ ....................................................... 2-24
2N4340 N-Channel JFET Low Noise Amplifier ..•......... ; ................................................. 2-24
2N4341 N-Channel JFET Low Noise Amplifier .............................................................. 2-24
.2N4351 N-Channel Enhancement Mode MOSFET General Purpose Amplifier/Switch ............. 2-25
ITE4391 N-Channel JFET Switch ............................................................................... 2-26
2N4391 N-Channel JFET Switch ................................................................................ 2-26
ITE4392 N-Channel JFET Switch ............................................................................... 2-26
2N4392 N-Channel JFET Switch ............................................................... ; ................ 2-26
ITE4393 N-Channel JFET Switch ............................................................................... 2:"26
2N4393 N-Channel JFET Switch .............................................•.................................. 2-26
ITE4416 N-Channel JFET High Frequency Amplifier ....................................................... 2-28
2N4416/A N-Channel JFET High Frequency Amplifier .................................................... 2-28
2N4856N-Channel JFET Switch ................................................................................ 2-30
2N4856JAN,JTX,JTXV N-Channel JFET Switch ....................................... ; ...................... 2..:30
2N4857 N-Channel JFET Switch ................................................................................ 2-30
2N4857JAN,JTX,JTXV N-Channel JFET Switch ............................................................. 2-30
2N4858 N-Channel JFET Switch ............................... '................................................. 2-30
2N4858JAN,JTX,JTXV N-Channel JFET Switch .................. , ................................ , ......... 2-30
2N4859 N-Channel JFET Switch ................................................................................ 2-30
2N4860 N-Channel JFET Switch ................................................ : ............................... 2 -30
2N4861 N-Channel JFET Switch.: .............................................................................. 2-30
2N4867/ AN-Channel JFET Low Noise Amplifier ........................................................... 2-32
2N4868/ A N-Channel JFET Low Noise Amplifier ........................................................... 2-32
2N4869! A N-Channel JFET Low Noise Amplifier ........................................................... 2-32
2N5018 P-Channel JFET Switch .: .............................................................................. 2-34
2N5019 P-Channel JFET Switch .......................................................................... ; ..... 2-34.
2N5114 P-Channel JFET Switch ................................................................................ 2-'36
2N5114JAN,JTX,JTXV P-Channel JFET Switch .............. ~ ............................................... 2-36
2N5115 P-ChannelJFET Switch .......................................................... : ..................... 2-36
2N5115JAN,JTX,JTXV P-Channel JFET Switch .................. ; .................................. ; ........ 2-36
2N5116 P-Channel JFET Switch ................................................................................ 2-36

2

Table of Contents
Description

Section 2 -

Page

Discretes (Cont.)

2N5116JAN,JTX,JTXV P-Channel JFET Switch .............................................................. 2-36
2N5117 Dielectrically Isolated Dual PNP General Purpose Amplifier ................................... 2-38
2N5118 Dielectrically Isolated Dual PNP General Purpose Amplifier ................................... 2-38
2N5119 Dielectrically Isolated Dual PNP General Purpose Amplifier ................................... 2-38
2N5196 DualN-Channel JFET General Purpose Amplifier ............................................... 2~40
2N5197 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-40
2N5198 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-40
2N5199 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-40
2N5397 N-Channel JFET High Frequency Amplifier ....................................................... 2-42
2N5398 N-Channel JFET High Frequency Amplifier ....................................................... 2-42
2N5432 N-Channel JFET Switch ................................................................................ 2 -44
2N5433 N-Channel JFET Switch ................................................................................ 2-44
2N5434 N-Channel JFET Switch ........................................................ ; ....................... 2-44
2N5452 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-46
2N5453 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-46
2N5454 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-46
2N5457 N-Channel JFET General Purpose Amplifier/Switch ............................................ 2-48
2N5458 N-Channel JFET General Purpose Amplifier/Switch ............................................ 2-48
2N5459 N-Channel JFET General Purpose Amplifier/Switch ............................................ 2-48
2N5460 P-Channel JFET Low Noise Amplifier ........................................................... ; .. 2-49
2N5461 P-Channel JFET Low Noise Amplifier .............................................................. 2-49
2N5462 P:...Channel JFET Low Noise Amplifier .............................................................. 2-49
2N5463 P-Channel JFET Low Noise Amplifier .............................................................. 2-49
2N5464 P-Channel JFET Low Noise Amplifier .............................................................. 2-49
2N5465 P-Channel JFET Low Noise Amplifier ............................................................... 2-49
2N5484 N-Channel JFET High Frequency Amplifier ....................................................... 2-50
2N5485 N-Channel JFET High Frequency Amplifier ....................................................... 2-50
2N5486 N-Channel JFET High Frequency Amplifier ........................................................ 2-50
2N5515 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-52
2N5516 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-52
2N5517 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-52
2N5518 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-52
2N5519 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-52
2N5520 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-52
2N5521 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-52
2N5522 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-52
2N5523 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-52
2N5524 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-52
2N5638 N-Channel JFET Switch ................................................................................ 2-54
2N5639 N-Channel JFET Switch ................................................................................ 2-54
2N5640 N-Channel JFET Switch ................................................................................ 2-54
2N5902 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-56
2N5903 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-56
2N5904 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-56
2N5905 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-56
2N5906 Dual N-Channel JFET General Purpose Amplifier .......................................... ; .... 2-56
2N5907 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-56
2N5908 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-56
2N5909 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-56

3

Table of Contents
'Oescription

Section 2 -

Page

Discretes (Cont.)

2N5911 Dual N-Channel JFET High Frequency Amplifier ............•.............•..................... 2-58
IT5911 Dual N-Channel JFET High Frequency Amplifier: .............'..•...•...............'....... , ....... 2-58
2N5912 Dual N-Channel JFET High Frequency Amplifier ................................................ 2-58
IT5912 Dual N-Channel JFET High Frequency Amplifier ............................................... , .. 2-58
2N6483 Dual N-Channel JFET Low Noise Amplifier ................•...................................... 2:...60
2N6484 Dual N-Channel JFET Low Noise Amplifier ...........•........................................... 2-60
2N6485 Dual N-Channel JFET Low Noise Amplifier ....... : ............................. , ................. 2-60
IMF6485 Dual N-Channel JFET Low Noise Amplifier ....... ; .. , ........................................... 2-62
3N161 Diode Protected P-Channel Enhancement Mode MOSFETGeneral Purpose Amplifier/
Switch ............................................................................................................. 2-64
3N163 P-Channel Enhancement Mode MOSFET General Purpose Amplifier/Switch .............. 2-65
3N164 P-Channel Enhancement Mode MOSFET General Purpose/Switch ........................... 2-65
3N165 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier ................. 2-67
3N166 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier ................. 2-67
3N170 N-Channel Enhancement Mode MOSFET Switch ................................................. 2-69
3N171 N-Channel Enhancement Mode MOSFET Switch ...... , .......................................... 2-69
3N 172 Diode Protected P-Channel Enhancement Mode MOSFET General Purpose Amplifier /
'
.Switch .............................................................. , ............................................. 2-7.1
3N173 Diode Protected P-Channel Enhancement Mode MOSFET General Purpose Amplifier/
Switch ............................................................................................................ 2-71
3N 188 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier ................. 2 - 72
3N189 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier ................. 2-72
3N 190 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier ................. 2 - 72
3N191 Dual P--Channel Enhancement Mode MOSFETGeneral Purpose Amplifier ................. 2-72
ID100 Dual Low Leakage Diode ................................................................................ 2-74
ID101 Dual Low Leakage Diode ................................................................................ 2-74
IT100 P-Channel JFET Switch ............................................ : ...................................... 2-76
IT101 P-Channel JFET Switch ................. '.................................................................. 2-76
IT120 Dual NPN General Purpose Amplifier .................................................................. 2-77
IT120A Dual NPN General Purpose Amplifier ................................................................ 2:... 77
IT121 Dual NPN General Purpose Amplifier .................................................................. 2- 77
IT122 Dual NPN General Purpose Amplifier .................................................................. 2-77
IT124 Dual Super-Seta NPN General Purpose Amplifier ................................... : .............. 2 -79
IT126 Dual NPN General Purpose Amplifier .................................................................. 2-81
IT127 Dual NPN General Purpose Amplifier .................................................................. 2-81
IT128 Dual NPN General Purpose Amplifier .................................................................. 2-81
IT129 Dual NPN General Purpose Amplifier .................................................................. 2-81
IT130 Dual PNP General Purpose Amplifier ................................................................... 2-83
IT130A Dual PNP General Purpose Amplifier ........................................ , ....................... 2-83
IT131 Dual PNP General Purpose Amplifier .................................. , ................................. 2-83
IT132 DualPNP General Purpose Amplifier .................................'..........................•...... 2-83
IT136 Dual PNP General Purpose Amplifier ................................................................... 2-85
IT137 Dual PNP General Purpose Amplifier .................................................................. 2-85
IT138 Dual PNP General Purpose Amplifier ........................................................ , .......... 2-85
IT139 Dual PNP General Purpose Amplifier .................................................................. 2-85
IT500 Dual Cascoded N-Channel JFET General Purpose Amplifier .................. : ................. 2-87
·IT501 Dual Cascoded N-Channel JFET General Purpose Amplifier ..........................•......... 2 .... 87
1T502 Dual Cascoded N-Channel JFET General Purpose Amplifier .................................... 2-87
IT503 Dual Cascoded N-Channel JFET General Purpose Amplifier .................................... 2-87

4

Table of Contents
Description

Section 2 -

Page

Discretes (Cont.)

IT504 Dual Cascoded N-Channel JFET General Purpose Amplifier .................................... 2-87
IT505 Dual Cascoded N-Channel JFET General Purpose Amplifier .................................... 2-87
IT550 Dual N-Channel JFET Switch ........................................................................... 2-90
IT1700 P-Channel Enhancement Mode MOSFET General Purpose Amplifier ........................ 2-92
IT1750 N-Channel Enhancement Mode MOSFET General Purpose Amplifier/Switch .............. 2-93
J105 N-Channel JFET Switch ................................................................................... 2-94
J106 N-Channel JFET Switch ................................................................................... 2-94
J107 N-Channel JFET Switch ................................................................................... 2-94
J111 N-Channel JFET Switch ................................................................................... 2-95
J112 N-Channel JFET Switch ................................... '........................................... : .... 2-95
J113 N-Channel JFET Switch ................................................................................... 2-95
J 174 P-Channel J FET Switch .................................................................................... 2 -97
J175 P-Channel JFET Switch ......................................................................... .' ..... : .... 2-97
J176 P-Channel JFET Switch .................................................................................... 2-97
J177 P-Channel JFET Switch .................................................................................... 2-97
J201 N-Channel JFET General Purpose Amplifier .......................................................... 2-99
J202 N-Channel JFET General Purpose Amplifier ......................................................... ;2-99
J203 N-Channel JFET General Purpose Amplifier ...................................... , ................... 2-99
J204 N-Channel JFET General Purpose Amplifier .......................................................... 2-99
J308 N-Channel JFET High Frequency Amplifier ... , ..................................................... 2-100
J309 N-Channel JFET High Frequency Amplifier ..... : ........................................ : .......... 2-100
J310 N-Channel JFET High Frequency Amplifier ....................................... ; ............ : .... 2-100
LM114/H Dual NPN General Purpose Amplifier ........................................................... 2-102
LM114A1AH Dual NPN General Purpose Amplifier ....................................................... 2-102
M116 Diode Protected N-Channel Enhancement Mode MOSFET General Purpose Amplifier. 2 -104
U200 N-Channel JFET Switch ................................................................................. 2-105
U201 N-Channel JFET Switch ................................................................................. 2-105
U202 N-Channel JFET Switch ................................................................................. 2-105
U231 Dual N-Channel JFET General Purpose Amplifier ................................................ 2-106
U232 Dual N-Channel JFET General Purpose Amplifier ................................................ 2-106
U233 Dual N-Channel JFET General Purpose Amplifier ................................................ 2-106
U234 Dual N-Channel JFET General Purpose Amplifier ................................................ 2-106
U235 Dual N-Channel JFET General Purpose Amplifier ................................................ 2-106
U257 Dual N-Channel JFET High Frequency Amplifier ......................... , ................... : .... 2-108
U304 P-Channel JFET Switch ................................................................................. 2-109
U305 P-Channel JFET Switch ................................................................................. 2-109
U306 P-Channel JFET Switch ................................................................................. 2-109
U308 N-Channel JFET High Frequency Amplifier ......................................................... 2-111
U309 N-Channel JFET High Frequency Amplifier ......................................................... 2-111
U310 N-Channel JFET High Frequency Amplifier ...................... : .................................. 2-111
U401 Dual N-Channel JFET Switch ............................... , ............................. , ............ 2 -113
U402 Dual N-Channel JFET Switch .......................................................................... 2-113
U403 Dual N-Channel JFET Switch .......................................................................... 2-113
U404 Dual N-Channel JFET Switch .......................................................................... 2-113
U405 Dual N-Channel JFET Switch .......................................................................... 2-113
U406 Dual N-Channel JFET Switch .......................................................................... 2-113
U1897 N-Channel JFET Switch ............................................................................... 2-115
U1898 N-Channel JFET Switch ............................................................................... 2-115
U1899 N-Channel JFET Switch ..................................... ;;'....................................,.... 2-115

5

Table of Contents
Page

Description

Section 2 -

Discretes (Cont.)

VCR2N Voltage Controlled Resistors ..........................................•.............................. 2-117
VCR3P Voltage Controlled Resistors ......................................................................... 2-117
VCR4N Voltage Controlled Resistors ............................... , ............... ~ •........................ 2-117
VCR7N Voltage Controlled Resistors ........................ ; ................................................ 2-117
VCR11N Voltage Controlled Resistors ....................................................................... 2-120

Section 3 -

Analog Switches and Multiplexers

D123 SPST 6-Channel JFET Switch Driver ......................................... , ......................... 3-1
D125 SPST 6-Channel JFET Switch Driver ................................................................... 3-1
D129 4-Channel Decoded JFET Switch Driver ............................................................... 3-6
DG118 SPST 4-Channel Driver With Switch ................................... ; .............................. 3-8
DG123 SPST 5-Channel Driver With Switch .................................................................. 3-8
DG125 SPST 5-Channel Driver With Switch .................................................................. 3-8
DG126 Dual DPST 80 Ohm JFET Analog Switch .......................................................... 3-12
DG129 Dual DPST 30 Ohm JFET Analog Switch .......................................................... 3:...12
DG133 Dual SPST 30/35 Ohm JFET Analog Switch ...................................................... 3-12
DG134 Dual SPST 80 Ohm JFET Analog Switch .......................................................... 3-12
DG140 Dual DPST 10/15 Ohm JFETAnalog Switch ...................................................... 3-12
DG141 Dual ~PST 10 Ohm JFET Analog Switch .......................................................... 3-12
DG151 Dual SPST 15 Ohm JFET Analog Switch .......................................................... 3-12
DG152 Dual SPST 50 Ohm JFET Analog Switch .......................................................... 3-12
DG153 Dual DPST 15 Ohm JFET Analog Switch .. , ....................................................... 3-12
DG154 Dual DPST 50 Ohm JFET Analog Switch .......................................................... 3'-12
DG139 DPDT 30 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG142. DPDT 80 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG143 SPDT 80 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG144 SPDT 30 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG145 DPDT 10 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG146 SPDT 10 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG161 SPDT 15 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG162 SPDT 50 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG163 DPDT 15 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG164 DPDT 50 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG180 Dual SPST 10 Ohm High-Speed Driver With JFET Switch ..................................... 3-22
DG181 Dual SPST 30 Ohm High-Speed Driver With JFET Switch ..................................... 3-22
DG 182 Dual SPST 75 Ohm High-Speed Driver With JFET Switch ..................................... 3 -22
DG183 Dual DPST 10 Ohm High-Speed Driver With JFET Switch ..................................... 3-22
DG184 Dual DPST 30 Ohm High-Speed Driver With JFET Switch ..................................... 3-22
DG185 Dual DPST 75 Ohm High-Speed Driver With JFET Switch ...................................... 3-22
DG186 SPDT10 Ohm High-Speed Driver With JFET Switch ............................................ 3-22
OG187 SPDT 30 Ohm High-Speed Driver With JFET Switch ............................................ 3-22
DG188 SPDT 75 Ohm High-Speed Driver With JFET Switch ............................................ 3-22
DG189 Dual SPDT10 Ohm High-Speed Driver With JFET Switch ..................................... 3:"'22
DG190 Dual SPDT 30 Ohm High-Speed Driver With JFETSwitch ..................................... 3-22
DG191 Dual SPOT 75 Ohm High-Speed Driver With JFET Switch ..................................... 3-22
DG200 Dual SPST CMOS Analog Switch ..• ; ................................................................. 3-27
IH5200 Dual SPST CMOS Analog Switch ..................................................................... 3-27
DG201 Quad SPST CMOS Analog Switch .................................................................... 3-32

6

Table of Contents
Description

Section 3 -

Page

Analog Switches and Multiplexers (Cont.)

IH5201 Quad SPST CMOS Analog Switch ................................................................... 3-32
DG211 SPST 4-Channel Analog Switch ....................................................................... 3-36
DG212 SPST 4-Channel Analog Switch ....................................................................... 3-36
DGM181 Dual SPST 50 Ohm High-Speed CMOS Analog Switch ...................................... 3-39
DGM182 Dual SPST 50/75 Ohm High-Speed CMOS Analog Switch .................................. 3-39
DGM184 Dual DPST 50 Ohm High-Speed CMOS Analog Switch ...................................... 3-39
DGM185 Dual DPST 50/75 Ohm High-Speed CMOS Analog Switch .................................. 3-39
DGM187 SPOT 50 Ohm High-Speed CMOS Analog Switch ............................................. 3-39
DGM188 SPOT 50/75 Ohm High-Speed CMOS Analog Switch ......................................... 3-39
DGM190 Dual SPOT 50 Ohm High-Speed CMOS Analog Swi.tch ...................................... 3-39
DGM191 Dual SPOT 50/75 Ohm High-Speed CMOS Analog Switch .................................. 3-39
G115 6-Channel MOSFET Switch .............................................................................. 3-45
G123 4-Channel MOSFET Switch .............................................................................. 3-45
G116 5 Channel MOSFET Switch .............................................................................. 3-48
G118 6 Channel MOSFET Switch ..................................... " ....................................... 3-48
G119 6 Channel MOSFET Switch .............................................................................. 3-48
IH311 High Speed SPST 4-Channel Analog Switch ....................................................... 3-52
IH312 High Speed SPST 4-Channel Analog Switch ....................................................... 3-52
IH401 QUAD Varafet Analog Switch ........................................................................... 3-59
IH401A QUAD Varafet Analog Switch ............................................................ , ............ 3-59
IH5009 Quad 100 Ohm Virtual Ground Analog Switch ................................................ : .... 3-65
IH5010 Quad 150 Ohm Virtual Ground Analog Switch .............................................•...... 3-65
IH5011 Quad 100 Ohm Virtual Ground Analog Switch .................................................. ~. 3-65
IH5012 Quad 150 Ohm Virtual Ground Analog Switch .................................................... 3-65
IH5013 Triple 100 Ohm Virtual Ground Analog Switch ....... " ........................................... 3-65
IH5014 Triple 150 Ohm Virtual Ground Analog Switch .................................................... 3-65
IH5015 Triple 100 Ohm Virtual Groung Analog .Switch .................................................... 3-65
IH5016 Triple 150 Ohm Virtual Ground Analog Switch ..................................................... 3-65
IH5017 Dual 100 Ohm Virtual Ground Analog Switch , .................................................... 3-65
lH5018 Dual 150 Ohm Virtual Ground Analog Switch ..................................................... 3-65
IH5019 Dual 100 Ohm Virtual Ground Analog Switch ..................................................... 3-65
IH5020 Dual 150 Ohm Virtual Ground Analog Switch ..................................................... 3-65
IH5021 Single 100 Ohm Virtual Ground Analog Switch ................................................... 3-65
IH5022 Single 150 Ohm Virtual Ground Analog Switch ................................................... 3-65
IH5023 Single 100 Ohm Virtual Ground Analog Switch ................................................... 3-65
IH5024 Single 150 Ohm Virtual Ground Analog Switch ................................................... 3-65
IH5025 Quad 100 Ohm Positive Signal Analog Switch ........... , ........................................ 3-71
IH5026 Quad 150 Ohm Positive Signal Analog Switch .................................................... 3-71
IH5027 Quad 100 Ohm Positive Signal Analog Switch .................................................... 3 - 71
IH5028 Quad 150 Ohm Positive Signal Analog Switch .................................................... 3 - 71
IH5029 Triple 100 Ohm Positive Signal Analog Switch .................................................... 3-71
IH5030 Triple 150 Ohm Positive Signal Analog Switch .................................................... 3-71
IH5031 Triple 100 Ohm Positive Signal Analog Switch .................................................... 3-71
IH5032 Triple 150 Ohm Positive Signal Analog Switch .......................,............................. 3-71
IH5033 Dual 100 Ohm Positive Signal Analog Switch ..................................................... 3-71
IH5034 Dual 150 Ohm Positive Signal Analog Switch ..................................................... 3-71
IH5035 Dual 100 Ohm Positive Signal Analog Switch ..................................................... 3-71
IH5036 Dual 150 Ohm Positive Signal Analog Switch ..................................................... 3-71
IH5037 Single 100 Ohm Positive Signal Analog Switch .......... : ........................................ 3-71

7

Table of Contents
Description

Page

Section 3 -Analog Switches and Multiplexers (Cont.)
IH5038 Single 1'50 Ohm Positive Signal Analog Switch ..................................................... 3-71
IH5040 SPST 75 Ohm High-Level CMOS Analog Switch ....... , .........................................,3-.79
IH5041 Dual SPST 75 Ohm High-Level CMOS Analog Switch .......................................... 3-79
IH5042 SPOT 75 Ohm High-Level CMOS Analog Switch ............. ; ......................... , ....... ,. 3-79
IH5043 Dual SPOT 75 Ohm High-Level CMOS Analog Switch ............................... , ......... , 3-79
IH5044 DPST 75 Ohm High-Level CMOS Analog Switch .............................. ; ....... , .......... 3-]9
IH5045 Dual DPST 75 Ohm High-Level CMOS Analog Switch .......................................... 3-79
IH5046 DPDT 75 Ohm High-Level CMOS Analog Switch ........................................' .......... 3-79
IH5047 4PST 75 Ohm High-Level CMOS Analog Switch ....... ; ..... : .................................... 3-79
IH5048 Dual SPST 35 Ohm High-Level CMOS Analog Switch ........................................... 3-88
IH5049 Dual DPST 35 Ohm High-Level CMOS Analog Switch .......................................... 3-88
IH5050 SPOT 35 Ohm High-Level CMOS Analog Switch ................................................. 3-88
IH5051 Dual SPOT 35 Ohm High-Level CMOS Analog Switch ......................" ................... 3-88
IH5052 QUAD CMOS Analog Switch ........................................................................... 3-93
IH5053 QUAD CMOS Analog Switch ........................................................................... 3-93
IH5108 8-Ch~nnel Fault Protected Analog Multiplexer ............................................. , ....... 3-99
IH5116 16-Channel Fault Protected Analog Multiplexer .............. 01 . . . . . . . . . . . . . , " . . . . . . . . . . . . . . . . . . . 3 -1 07
IH5140 SPST High-Level CMOS Analog Switch ..................................... ; ................ ; .... 3-110
IH5141 Dual SPST High-Level CMOS Analog Switch ..................................................... 3 -110
IH5142 SPOT Hig~-Level CMOS Analqg Switch ................................................ ; .... , ..... 3-110
IH5f43 Dual SPOT High-Level CMOS Analog Switch .................................................... 3-110
IH5144 DPST High-Level CMOS Analog Switch ................................ ; .......................... 3-110
IH5145 Dual DPST High-Level CMOS Analog Switch ............................... , ..................... 3-110
IH5148 Dual SPST High-Level CMOS Analog Switch ...................... : ..... ; ....................... 3-119
IH5149 Dual DPST High-Level CMOS Analog Switch ........................ , .. , ...... , .................. 3-119
IH5150 SPOT High-Level CMOS Analog Switch .......................,.................................... 3-119
IH5151 Dual SPOT High-Level CMOS Analog Switch ........ , ........................................... 3-119
IH5208 4-Channel Differential Fault Protectbu Analog Multiplexer .................................... 3-127
IH52168-Channel Differential Fault Protected Analog Multiplexer •........• ~ ......................... 3-135
IH5341 Dual SPST CMOS RFlVideo Switch ............... : ................................................ 3-1.38
IH5352 QUAD SPST CMOS RFlVideo Switch ............................................................. 3-144
IH6108 8-Channel CMOS Analog Multiplexer ................................... , .......................... 3-149
IH6116 16-Channel CMOS Analog Multiplexer ................................ ; ............. ; ............. 3-155
IH6201 Dual CMOS DriverlVoltage Translator ........................... ; ................................. 3-162
IH6208 4-Channel Differential CMOS Analog Multiplexer ............................................... 3-166
IH6216 8-Channel Differential CMOS Analog Multiplexer ............. ; ................................. 3-172
MM450 Dual Differential High Voltage Analog Switch .................................................... 3-178
MM550 Dual Differential High Voltage Analog Switch ................................................... 3-178
MM451 Four Channel High Voltage Multiplexer ............................................................3.-178
MM551 Four Channel High Voltage Multiplexer ........................................................... 3-178
MM452 Quad SPST High Voltage Analog Switch ............ "................... : ........................ 3-178
MM552 Quad SPST High Voltage Analog Switch .......................................................... 3-178
MM455 Three SPST High Voltage Analog Switch ..,...................................................... 3-178
MM555 Three SPST High Voltage Analog Switch ........................................................ :)-178

Section 4 -

Amplifiers -

Operational and Special Purpose

ICH8500/ A Ultra Low Input-Bias Operational Amplifier ..................................................... 4-1
ICH8510 Power Operational Amplifier ........................................................................... 4-7

8

Table of Contents
Description

Section 4 (Cont.)

Page

Amplifiers -

Operational and Special Purpose

rCH8520 Power Operational Amplifier ........................................................................... 4-7
ICH8530 Power Operational Amplifier ........................................................................... 4-7
ICH8515 Power Operational Amplifier ......................................................................... .4-16
,ICL7605 Commutating Auto-Zero (CAZ) Instrumentation Amplifier ...................................... 4-23
ICL7606 Commutating Auto-Zero (CAD) Instrumentation Amplifier ...................................... 4-23
ICL76XX Series Low Power CMOS Operational Amplifiers .............................................. .4-34
ICL7650 Chopper-Stabilized Operational Amplifier .......................................................... 4-50
ICL7652 Chopper-Stabilized Low-Noise Operational Amplifier ........................................... 4-57
ICL8007 JFET Input Operational Amplifier .................................................................... 4-65
ICL8021 Low Power Bipolar Operational Amplifier .......................................................... 4-69
ICL8022 Dual Low Power Bipolar Operational Amplifier ....................................... : .......... .4-69
ICL8023 Triple Low Power Bipolar Operational Amplifier .................................................. 4-69
. ICL8043 Dual JFET Input Operational Amplifier ............................................................ .4-74
ICL8048 Logarithmic Amplifier .................................................................................... 4-82
ICL8049 Antilog Amplifier ......................................................................................... 4-82
ICL8063 Power Transistor Driver/Amplifier ................................................................... .4-90
LH2108 Dual Super-Beta Operational Amplifier ............................................................ .4-99
LH2308 Dual Super-Beta Operational Amplifier ............................................................ .4-99
LM108/A Super-Beta Operational Amplifier ................................................................ 4-102
LM308/A Super-Beta Operational Amplifier ................................................................ 4-102
NE/SE592 Video Amplifier ................................................................................ ; ..... 4-106

Section 5 -

Special Analog Functions

AD590 2-Wire Current Output Temperature Transducer .................................................... 5-1
ICL7660 CMOS Voltage Converter ............................................................................... 5.,.12
ICL7662 CMOS Voltage Converter .............................................................................. 5-20
ICL7663 CMOS Programmable Micropower Positive Voltage Regulator ............................... 5-27
ICL7664 CMOS Programmable Micropower Negative Voltage Regulator .............................. 5-27
ICL7665 Micropower Under/Over Voltage Detector ......................................................... 5-39
ICL7667 Dual Power MOSFET Driver .......................................................................... 5-47
ICL7673 Automatic Battery Back-up Switch .................................................................. 5-55
ICL8013 Four Quadrant Analog Multiplier ..................................................................... 5-63
ICL8038 Precision Waveform Generator/Voltage Controlled Oscillator ................................. 5-72
ICL8069 Low Voltage Reference ................................................................................ 5-81
ICL8211 Programmable Voltage Detector ..................................................................... 5-83
ICL8212 Programmable Voltage Detector ..................................................................... 5-83
IH5110 General Purpose Sample & Hold ..................................................................... 5-94
IH5111 General Purpose Sample & Hold ..................................................................... 5-94
IH5112 General Purpose Sample & Hold ..................................................................... 5-94
IH5113 General Purpose Sample & Hold ..................................................................... 5-94
IH5114 General Purpose Sample & Hold ..................................................................... 5-94
IH5115 General Purpose Sample & Hold ..................................................................... 5-94

Section 6 -

Data Acquisition

AD7520 10/ 12-Bit Multiplying D/ A Converter ................................................................. 6-1
AD7521 10/12-Bit Multiplying D/ A Converter ........................................................ ; ........ 6-1

9

Table of Contents
Page

Description

Section 6 -

Data Acquisition (Cont.)

AD7530 10/12-Bit Multiplying D/A Converter ................................................................. 6-1
AD7531 10/12-Bit Multiplying D/ A Converter ............................ ; .................................•.. 6-1
AD7523 8-Bit Multiplying D/ A Converter ....................................................................... 6-7
AD7533 10-Bit Multiplying D/ A Converter ................. , .........................................', ........ 6-11
AD7541 12-Bit Multiplying D/A Converter .................................................................... 6-16
ADC0802 8-Bjt J,LP-Compatible AID Converter ............................................................... 6-22
ADC0803 8-Bit J,LP-Compatible AID Converter .. ; ............................................................ 6-22
ADC0804 8-Bit J,LP-Compatible AID Converter ................................................................6-22
ICL7106 3 Y2-Digit LCD Single-Chip AID Converter ....................................................... 6-37
ICL7107 3 Y2-Digit LED Single-Chip AID Converter ....................................................... 6-37
ICL7109 12-Bit J,LP-Compatible AID Converter ............................................................... 6-48
ICL7115 14-Bit High-Speed CMOS J,LP-Compatible AID Converter .................................... 6-66
ICL7116 3 Y2-Digit with Display Hold Single-Chip AID Converter ........................................ 6-78
ICL7117 3 Y2-Digit with Display Hold Single-Chip AID Converter ...................................... 6-78
ICL7126 3 Y2-Digit Low-Power Single-Chip AID Converter .............................................. 6-88
ICL7129 4 Y2 Digit I.CD Single-Chip AID Converter ....................................................... 6-98
ICL7134 14-Bit Multiplying J,LP-Gompatible D/A Converter .............................................. 6-109
ICL7135 4 Y2-Digit BCD Output AID Converter ............................................................ 6-121
ICL7136 3 Y2-Digit LCD Low Power AID Converter ...................................................... 6-132
ICL71373 Y2-Digit LED Low Power Single-Chip AID Converter ...................................... 6-142
ICL8018A 4-Bit Expandable Current Switch ................................................................ 6-151
ICL8019A 4-Bit Expandable Current Switch ................................................................ 6-151
ICL8020A 4-Bit Expandable ~urrent Switch ................................................................ 6-151
ICL7104/ICL8052 12/14/16-Bit J,LP-Compatible 2-Chip AID Converter ................... " ......... 6-157
ICL7104/1CL8068 12/14/16-Bit J,LP-Gompatible 2-Chip AID Converter ............................. 6-157
.

Section 7 -

(

Timer/Counter Circuits

ICM7206 CMOS Touch-Tone Encoder .......................................................................... 7-1
ICM7207/A CMOS Timebase Generator ....................................................................... 7 -10
ICM7208 7-Digit LED Display Counter ......................................................................... 7 -15
ICM7209 Timebase Generator ................................................................................... 7 -22
ICM7213 One Second/One Minute Timebase Generator ................................................. 7 -25
ICM72Hi 6-Digit LED Display 4-Function Stopwatch ...................................................... 7 -30
ICM7216A 8-Digit Multi-Function Frequency Counter/Timer .............................................. 7-36
ICM7216B 8-Digit Multi-Function Frequency Counter/Timer .............................................. 7-36
ICM7216C 8-Digit Multi-Function Frequency Counter/Timer .............................................. 7 -36
ICM7216D 8-Digit Multi-Function Frequency Counter/Timer ............................................. 7-36
ICM7217 4-Digit LED Display Programmable Up/Down Counter ........................................ 7 -52
ICM7227 4-Digit LED Display Programmable Up/Down. Counter ........................................ 7 -52
ICM7224 4 Y2-Digit LCD/LED Display Counter .......................... ; ................................... 7 -67
ICM7225 4 Y2-Digit LCD/LED Display Counter .............................................................. 7 -67
ICM7226A1B 8-Digit Multi-Function Frequency Counter/Timer .......................................... 7-75
ICM7236 4 Y2-Digit CounterlVacuum Fluorescent Display Driver ........................................ 7-88
ICM7240 Programmable Timer ................................................................................... 7 -93
ICM7250 Programmable Timer ...................................... , .......................................... ;. 7-93
ICM7260 Programmable Timer ................................................................................... 7-93
ICM7241 Timebase Generator ............................ , .................... : ............................... 7-103
ICM7242 Long-Range Fixed Timer ........................................................................... 7-105

10

Table of Contents
Page

Description

Section 7 ICM7245
IGM7249
ICM7555
ICM7556

Stepper Motor Quartz Clock ....................................................................... 7 -111
S-Y2 Digit LCD J..!-Power Event/Hour Meter .................................................... 7-115
General Purpose Timer .............................................................................. 7 -123
Dual General Purpose Timer ..................................... ,.................................. 7-123

Section 8 ICM7211
ICM7212
ICM7218
ICM7231
ICM7232
ICM7233
ICM7234
ICM7235
ICM7243
ICM7280
ICM7281
ICM7283

Timer/Counter Circuits (Cont.)

Display Drivers

4-Digit LCD/LED Display Driver ..................................................................... 8-1
4-Digit LCD/LED Display Driver ........................ ; ............................................ 8-1
8-Digit LED Multiplexed Display Driver ............................................................ 8-1 0
Numeric Triplexed LCD Display Driver ............................................................ 8-20
Numeric Triplexed LCD Display Driver ............................................................ 8-20
Alphanumeric Triplexed LCD Display Driver ...................................................... 8-20
Alphanumeric Triplexed LCD Display Driver ...................................................... 8-20
4-Digit Vacuum Fluorescent Display Driver ...................................................... 8-40
8'-Character LED J..!P-Compatible Display Driver ................................................ 8-45
Dot Matrix LCD Controller/Row Driver ............................................................ 8-54
40-Column LCD Dot Matrix Display Driver ....................................................... 8-69
LCD Dot Matrix Controller/Row Driver ............................................................ 8-79

Section 9 -

Microcontrollers, Microperipherals, Memory

ICM7170 J..!P'-Compatible Real-Time Clock ..................................................................... 9-1
IM4702/4712 Baud Rate Generator ............................................................................. 9-9
IM6402 Universal Asynchronous Receiver Transmitter (UART) .......................................... 9-16
IM6403 Universal Asynchronous Receiver Transmitter (UART) .......................................... 9-16
IM6653 4096-Bit CMOS UV EPROM .......................................................................... 9-25
IM6654 4096-Bit CMOS UV EPROM .......................................................................... 9-25
IM80C35 B-Bit CMOS Microcontroller .......................................................................... 9-33
IM80C39 B-Bit CMOS Microcontroller .......................................................................... 9-33
IM80C48 B-Bit CMOS Microcontroller .......................................................................... 9-33
IM80C49 B-Bit CMOS Microcontroller .......................................................................... 9-33
IM82C43 CMOS I/O Expander ..........................•....................................................... 9-45

Section 10 - High Reliability/Military Products and Ordering
Information .................................................................................................... 10:"1

11

Alphanumeric Index
2N2607 P-Channel JFET General Purpose Amplifier ....................................................... 2-1
2N2608 P-Channel JFET General Purpose Amplifier .............................................• , ... ; .... 2-1
2N2609 P-Channel JFET General Purpose .Amplifier ....................................................... 2-1
2N2609JAN P-Channel JFET Gen.eral Purpose Amplifier ............................................ , ...".2-'1
2N3684 N-Channel JFET Low Noise Amplifier ............................................................... 2-2
2N3685 N-Channel JFET Low Noise Amplifier ............................................................... 2-2'
2N3686 N-Channel JFET Low Noise Amplifier ............................................................... 2-2
2N3687 N-Channel JFET Low Noise Amplifier ............................................................... 2-2
2N3810/A Dual Matched PNP General Purpose Amplifier ................................................. 2-3
2N3811 / A Dual Matched PNP General Purpose Amplifier ................................................. 2-3
2N3821 N-Channel JFET High Frequency Amplifier ............................................... ; ....../.2-5
2N3821JAN N-Channel JFET High Frequency Amplifier ................................................... 2-5
2N3821 JTX N-Channel JFET High Frequency Amplifier ...... : ............................................. 2-5
2N3821JTXV N-Channel JFET High Frequency Amplifier ........ ~ ......................................... 2-5
2N3822 N-Channel JFET High Frequency Amplifier .................... : ................................... 2-5
2N3822JAN N-Channel JFET High Frequency Amplifier ................................................... 2-5
2N3822JTX N-Channel JFET High Frequency Amplifier .................................................... 2-$
2N3822JTXV N-Channel JFET High Frequency Amplifier .................................................. 2-5
2N3823 N-Channel JFET High Frequency Amplifier ........................................................ 2-7
2N3823JAN N-Channel JFET High Frequency Amplifier ................................................... 2-7
2N3823JTX N-Channel JFET High Frequency Amplifier .................................................... 2..., 7
2N3823JTXV N-Channel JFET High Frequency Amplifier .................................................. 2-7
2N3824 N-Channel JFET Switch .................... ~ ............................................................ 2-8
2N3921 Dual N-Channel JFET General Purpose Amplifier ................................................ 2-9
2N3922 Dual N-Channel.JFET General Purpose Amplifier ..................................... , .......... 2-9
2N3954 Dual N-Channel JFET General Purpose Amplifier ............................................... 2 -11
2N3954A Dual N-Channel JFET General Purpose Amplifier ..... ; ....................................... 2-11
2N3955 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-11
2N3955A Dual N-Channel.JFET General Purpose Amplifier ............................................. 2-11
2N3956 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-11
2N3957 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-11
2N3958 Dual N-Channel JFET General Purpose Amplifier ...................... , ....................;.... 2-11
2N3970 N-Channel JFET Switch ................................................................................. 2-13
2N3971 N-Channel JFET Switch ................................................................................ 2-13
2N3972 N-Channel JFET Switch ................................................................................ 2-13
2N3993 P-Channel JFET General Purpose Amplifier/Switch ............................................. 2-15
2N3994 P-Channel JFET General Purpose Amplifier/Switch ............................................. 2-15
2N4044 Dielectrically Isolated Dual NPN General Purpose Amplifier ................................... 2-17
2N4045 Dielectrically Isolated Dual NPN General, Purpose Amplifier ................................... 2-17
2N4091 JANTX N-Channel JFET Switch ..................................................................... 2-19
2N4091 N-Channel JFET Switch ................................................................................ 2-19
2N4092 JANTX N-Channel JFET Switch .......................... : .......................................... 2-19
2N4092 N-Channel JFET Switch ........................................................... '..................... 2-19
2N4093 JANTX N-Channel JFET Switch ..................................................................... 2-19
2N4093 N-Channel JFET Switch ................................................................................ 2-19
2N4100 Dielectrically Isolated Dual NPN General Purpose Amplifier ................................... 2-17
2N4117 N-Channel JFET General Purpose Amplifier ...................................................... 2-21
2N4117A N-Channel JFET General Purpose Amplifier .................................................... 2-21
2N4118 N-Channel JFET General Purpose Amplifier ...................................................... 2-21
2N4118A N-Channel JFET General Purpose Amplifier .................................................... 2-21
2N4119 N-Channel JFET General Purpose Amplifier ...................................................... 2-21
2N4119A N-Charinel JFET General Purpose Amplifier .................................................... 2-21
2N4220 N-Channel JFET General Purpose Amplifier/Switch ............................................ 2-22
2N4221 N-Channel JFET General Purpose Amplifier/Switch ............................................ 2-22

12

Alphanumeric Index

(Continued)

2N4222 N-Channel JFET General Purpose Amplifier/Switch ............................................ 2-22
2N4223 N-Channel JFET High Frequency Amplifier ....................................................... 2-23
2N4224 N-Channel JFET High Frequency Amplifier .................................................... : .. 2-23
2N4338 N-Channel JFET Low Noise Amplifier .............................................................. 2-24
2N4339 N-Channel JFET Low Noise Amplifier .............................................................. 2-24
2N4340 N-Channel JFET Low Noise Amplifier .............................................................. 2-24
2N4341 N-Channel JFET Low Noise Amplifier .............................................................. 2-24
2N4351 N-Channel Enhancement Mode MOSFET General Purpose Amplifier/Switch ............. 2-25
2N4391 N-Channel JFET Switch ................................................................................ 2-26
2N4392 N-Channel JFET Switch ................................................................................ 2-26
2N4393 N-Channel JFET Switch ................................................................. , .............. 2-26
2N4416/A N-Channel JFET High Frequency Amplifier .................................................... 2-28
2N4856 N-Channel JFET Switch ................................................................................ 2-30
2N4856JAN,JTX,JTXV N-Channel JFET Switch ............................................................. 2-30
2N4857 N-Channel JFET Switch ................................................................................ 2-30
2N4857 JAN,JTX,JTXV N-Channel JFET Switch ............................................................. 2-30
2N4858 N-Channel JFET Switch ................................................................................ 2-30
2N4858JAN,JTX,JTXV N-Channel JFET Switch ............................................................. 2-30
2N4859 N-Channel JFET Switch ................................................................................ 2-30
2N4860 N-Channel JFET Switch ................................................................................ 2-30
2N4861 N-Channel JFET Switch ................................................................................ 2-30
2N4867/ A N-Channel JFET Low Noise Amplifier ........................................................... 2-32
2N4868/ A N-Channel JFET Low Noise Amplifier ........................................................... 2-32
2N4869/ A N-Channel JFET Low Noise Amplifier ........................................................... 2-32
2N4878 Dielectrically Isolated Dual NPN General Purpose Amplifier ......................... ; ......... 2-17
2N4879 Dielectrically Isolated Dual NPN General Purpose Amplifier ................................... 2-17
2N4880 Dielectrically Isolated Dual NPN General Purpose Amplifier ................................... 2-17
2N5018 P-Channel JFET Switch ................................................................................ 2-34
2N5019 P-Channel JFET Switch ................................................................................ 2-34
2N5114 P-Channel JFET Switch ...................................................................... :·, ........ 2-36
2N5114JAN,JTX,JTXV P-Channel JFET Switch ........................ ; ..................................... 2-36
2N5115 P-Channel JFET Switch ................................................................................ 2-36
2N5115JAN,JTX,JTXV P-Channel JFET Switch .............................................................. 2-36
2N5116 P-Channel JFET Switch ................................................................................ 2-36
2N5116JAN,JTX,JTXV P-Channel JFET Switch .............................................................. 2-36
2N5117 Dielectrically Isolated Dual PNP General Purpose Amplifier ................................... 2-38
2N5118 Dielectrically Isolated Dual PNP General Purpose Amplifier ................................... 2-38
2N5119 Dielectrically Isolated Dual PNP General Purpose Amplifier ................................... 2-38
2N5196 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-40
2N5197 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-40
2N5198 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-40
2N5199 Dual N-Channel JFET General Purpose Amplifier ........................................... : ... 2-40
2N5397 N-Channel JFET High Frequency Amplifier ....................................................... 2-42
2N5398 N-Channel JFET High Frequency Amplifier ....................................................... 2-42
2N5432 N-Channel JFET Switch ................................................................................ 2 -44
2N5433 N-Channel JFET Switch ................................................................................ 2 -44
2N5434 N-Channel JFET Switch ................................................................................ 2-44
2N5452 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-46
2N5453 Dual N-Channel JFET General Purpose Amplifier .............. : ................................ 2-46
2N5454 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-46
2N5457 N-Channel JFET General Purpose Amplifier/Switch ............................................ 2-48
2N5458 N-Channel JFET General Purpose Amplifier/Switch ............................................ 2-48
2N5459 N-Channel JFET General Purpose Amplifier/Switch ............................................ 2-48
2N5460 P-Channel JFET Low Noise Amplifier .............................................................. 2-49

13

Alphanumeric Index

(Continued) -

2N5461 P-Channel JFETLow Noise Amplifier ...................•. ; ................... :., .•...•............ 2 ...,49
2N5462 P-Channel JFET Low Noise Amplifier ....... ~.~, .," .•............................................... 2-:49
2N5463 P-Channel JFET Low Noise Amplifier ........................... : .................................. 2 ...049
2N5464 P-ChanneIJFET Low Noise Amplifier ............... : .............................................. 2;,..49
2N5465 P-Channel JFET Low Noise Amplifier ............... : ............ : ................................. 2-49
.2N5484 N-Channel JFET High Frequency Amplifier ..... : .............. '.........................,........... 2-50
2N5485 N,..channel JFET High Frequency Amplifier ..... ; ... ~ ........... ,.: ................. , ............. 2:..,50
2N5486 N-Channel JFET High Frequency Amplifier ... '..............•........................ : ............. 2-.50
2N5515 Dual N-Channel JFET Low Noise Amplifier ........................................-............... 2-,52
2N5516 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-52
2N5517 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-52
2N5518 Dual N-Channel JFET Low Noise Amplifier .... ~ ........................... : ... : .................. 2-52
2N5519 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-52
2N5520 Dual N-Channel JFET Low Noise Amplifier ........................................................ 2 .... 52
2N5521 Dual N-Channel JFET Low Noise Amplifier ........................................................ 2-52
2N5522 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-52
2N5523 Dual N-Channel JFET Low Noise Amplifier ........................................................ 2-52
2N5524 Dual N-Channel JFET Low Noise Amplifier ................................................... : ... 2-52
2N5638 N-Channel JFET Switch ................................................................................ 2-54
2N5639 N-Channel JFET Switch ....,............................................................................ 2..,.54
2N5640 N-Channel JFET Switch ............. : .....................................................••........... 2-54
2N5902 Dual N-Channel JFET General Purpose Amplifier .. , ....... : .................................... 2-56
. 2N5903 Dual N-Channel JFET G~neral Purpose Amplifier. .............................................. 2-56
2N5904 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-56
2N5905 Dual N-Channel JFET General Purpose Amplifier .. , ............................................ 2-56
2N5906 Dual N-Channel JFET General Purpose Amplifier ......... , ..................................... 2-56
2N5907 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-56
2N5908 Dual N-Channel JFET General Purpose Arnplifier .................. : ............................ 2-56
2N5909 Dual N-Channel JFET General Purpose Amplifier ............................................... 2-56
2N5911 Dual N-Channel JFET High Frequency Amplifier .................. : .............................. 2-58
2N5912 Dual. N-Channel JFET High Frequency Amplifier ........................... : ..................... 2-58
2N6483 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-60
2N6484 Dual N-Channel JFET Low Noise Amplifier ....................................................... 2-60
2N6485 Dual N-Channel JFET Low ,N9ise Amplifier ....................................................... 2-60
3N161 Diode Protected P-ChannelEnhancement Mode MOSFET General Purpose Amplifierl
.
Switch ..................................... ::.....•....•....•..,........................................................... 2-64
3N163 P-Channel Enhancement Mode MOSFET General Purpose AmplifierlSwitch .............. 2-65
3N164 P-Channel Enhancement Mode MOSFET General Purpose/Switch ........................... 2,..65
3N165 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifie~ ................. 2-.67
3N166 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier ................. 2-67
3N170 N-Channel Enhancement Mode MOSFET Switch ................. : ......... , ..................... 2-69
3N171 N-Channel Enhancement Mode MOSFET Switch .................................................. 2-69
3N172 Diode Protected P-Channel Enhancement Mode MOSFET General Purpose Amplifierl
Switch ..................................• : ......................................................_.................... 2-71
3N173 Diode Protected P-Channel ~nhancement Mode MOSFET General Purpose Amplifierl
Switch .......................................................................... : ................................... 2-71
3N188 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier .................. 2,.. 72
3N189 Dual P-Channel Enhancement Mode MOSFET General Purpose Amplifier ................. 2-72
3N190 Dual P-Channel Enhancement Mbde MOSFET General Purpose Amplifier ................. 2-72
3N1.91 Dual P-Channel Enhancemel1tMo.d.EI: MPSFET General Purpose Amplifier ................. 2-72
AD590 2-:Wire Current Output Temperature TransdUcer .................... : ............................... 5-1
AD7520 10/12-8it Multiplying D/A·Cqhyerter .....• : .......... : .............. ~ ................................ 6-1
AD7521 10/12-8it Multiplying D/A C6nverter: ................................................................ 6-1
AD7523 8-8it Multiplying 01 A Converter ............................................,........................... 6-7

14

Alphanumeric Index

(Continued)

AD7530 10/12-Bit Multiplying DI A Converter .. , .............................................................. 6-1
AD7531 10/12-Bit Multiplying DI A Converter .......................................................... : ...... 6-1
AD7533 10-Bit Multiplying DI A Converter .................................................................... 6-11
AD7541 12-Bit Multiplying DI A Converter .................................................................... 6-16
ADC0802 8-Bit /lP-Compatible AID Converter ............................................................... 6-22
ADC0803 8-Bit /lP-Compatible AID Converter ............................................................... 6-22
ADC0804 8-Bit /lP-Compatible AID Converter ............................................................... 6-22
D123 SPST 6-Channel JFET Switch Driver ................................................................... 3-1
D125 SPST 6-Channel JFET Switch Driver ................................................................... 3-1
D129 4-Channel Decoded JFET Switch Driver ............................................................... 3-6
DG118 SPST 4-Channel Driver With Switch .................................................................. 3-8
DG123 SPST 5-Channel Driver With Switch .................................................................. 3-8
DG125 SPST 5-Channel Driver With Switch .................................................................. 3-8
DG126 Dual DPST 80 Ohm JFET Analog Switch .......................................................... 3-12
DG129 Dual DPST 30 Ohm JFET Analog Switch .......................................................... 3-12
DG133 Dual SPST 30/35 Ohm JFET Analog Switch ...................................................... 3-12
DG134 Dual SPST 80 Ohm JFET Analog Switch .......................................................... 3-12
DG139 DPDT 30 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG140 Dual DPST 10/15 Ohm JFET Analog Switch ...................................................... 3-12
DG141 Dual SPST 10 Ohm JFET Analog Switch ........................ ; ................................. 3-12
DG142 DPDT 80 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG143 SPDT 80 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG144 SPDT 30 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG145 DPDT 10 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG146 SPDT 10 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG151 Dual SPST 15 Ohm JFET Analog Switch .......................................................... 3-12
DG152 Dual SPST 50 Ohm JFET Analog Switch .......................................................... 3-12
DG153 Dual DPST 15 Ohm JFET Analog Switch .......................................................... 3-12
DG154 Dual DPST 50 Ohm JFET Analog Switch .......................................................... 3-12
DG161 SPDT 15 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG162 SPDT 50 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG163 DPDT 15 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG164 DPDT 50 Ohm Differentially Driven JFET Switch ................................................. 3-17
DG180 Dual SPST 10 Ohm High-Speed Driver With JFET Switch ..................................... 3-22
DG181 Dual SPST 30 Ohm High-Speed Driver With JFET Switch ..................................... 3-22
DG182 Dual SPST 75 Ohm High-Speed Driver With JFET Switch ..................................... 3....,22
DG183 Dual DPST 10 Ohm High-Speed Driver With JFET Switch ..................................... 3,...22
DG184 Dual DPST 30 Ohm High-Speed Driver With JFET Switch ..................................... 3-22
DG185 Dual DPST 75 Ohm High-Speed Driver With JFET Switch ..................................... 3-22
DG186 SPDT 10 Ohm High-Spee~ Driver With JFET Switch ............................................ 3-:22
DG187 SPDT 30 Ohm High-Speed Driver With JFET Switch ............................................ 3-22
DG188 SPDT 75 Ohm High-Speed Driver With JFET Switch ................................ ; ........... 3-22
DG189 Dual SPDT 10 Ohm High-Speed Driver With JFET Switch ....... ; ............................. 3-22
DG190 Dual SPDT 30 Ohm High-Speed Driver With JFET Switch ..................................... 3-22
DG191 Dual SPDT 75 Ohm High-Speed Driver With JFET Switch ..................................... 3-22
DG200 Dual SPST CMOS Analog Switch ..................................................................... 3-27
DG201 Quad SPST CMOS Analog Switch .................................................................... 3-32
DG211 SPST 4-Channel Analog Switch ....................................................................... 3-36
DG212 SPST 4-Channel Analog Switch ....................................................................... 3-36
DGM181 Dual SPST 50 Ohm High-Speed CMOS Analog Switch ...................................... 3-39
DGM182 Dual SPST 50175 Ohm High-Speed CMOS Analog Switch .................................. 3-39
DGM184 Dual DPST 50 Ohm High-Speed CMOS Analog Switch ...................................... 3-39
DGM185 Dual DPST 50175 Ohm High-Speed CMOS Analog Switch .................................. 3-39
DGM187 SPDT 50 Ohm High-Speed CMOS Analog Switch ............................................. 3-39

15

Alphanumeric Ind.x

(Continued)

OGM188 SPOT 50/75 Ohm High-Speed CMOS AnalogSwitch ........ i ....... , ..........•........... ; .. 3-"'39
DGM190 Dual SPOT 50 Ohm High-Speed .CMOS Analog Switch .......... ,; .......................... 3-'39
DGM191 Dual SPOT 50/75 Ohm High-Speed CMOS Analog Switch ......... ;." ...................... 3..;39
G115 6-Channel MOSFET Switch ........................................... ; ..... : ..:.•.... ; .................... :.3-45
G.116 5 Channel,MOSFET Switch .................................... :· ........... '...... ; ....................... 3-48
G118 6 Channel MOSFET Switch ............................................................................... 3-48
G119 6 Channel. MOSFET. Switch ........................... ; ...'............................., ................... 3-48
G123 4-Channel MOSFET. Switch ..................................................................... , ........ 3-45
lCH85001 A Ultra Low Input-Bias Operational Amplifier .... ; ............. : .............'..................... 4-1
ICH8510 Power Operational Amplifier ............................................................................ 4-7
ICH8515 Power Operational Amplifier ................................... ; ........................... , ......... , 4~ 16
ICH8520 Power Operational Amplifier ............................ ; .......................... , .. : .... , ...... , .... 4-'7
ICH8530 .Power Operational Amplifier ........................................................................... 4-7
ICL76XXSeries Low Power CMOS Operational Amplifiers .............................................. .4-34
ICL7104/1CL8052 12/14/16-Bit j.LP-Compatible 2-Chip AID Converter .... .'........................ 6-157
ICL7104/1CL8068 12/14/16-Bit /o1P-Compatible 2-Chip AID Converter ............................. 6-157
IGL7106 .3 }'2-Digit .LCD Single-Chip AID Converter ....................................................... 6-37
ICL7107 3 }'2-Digit LED Single-Chip AID Converter ....................................................... 6-37
ICL7109 12-Bit /o1P-Compatible AID Converter .............................................................. 6-48
ICL7115 14-Bit High..cSpeed CMOS /o1P-Compatible AID Converter .................................... 6-66
ICL71163 }'2-Digit with Display Hold Single-Chip AID Converter ........................................ 6-78
ICL7117. 3}'2-Digit with Display Hold Single-Chip AID Converter ...................................... 6-78
ICL7126 3 Y.2-Digit Low-Power Single-Chip AID Converter ............................................... 6-88
ICL7129 4 Y2 Digit LCD Single-Chip AID. Converter ....................................................... 6-98
ICL7134 14-Bit Multiplying /o1P-Compatible D/A Converter .............................................. 6-109
ICL7135 4 }'2-Digit BCD Output AID Converter ........................................................... 6-121
ICL7136 3 }'2-Digit LCD Low Power AID Converter .................... : ......................... '........ 6-132
ICL71373 }'2-Digit LED Low Power Singl9-'-Chip AID Converter ...................................... 6-142
ICL7605 Commutating Auto-Zero (CAZ) Instrumentation Amplifier ................. : .. : ................ .4-23
ICL7606 CommutatingAuto-Zero (CAD) Instrumenta:tion Amplifier .': .... ; .............................. .4-23
ICL7650 Chopper..cStabilized Operational Amplifier ............. ; ........................................... .4-50
ICL7652 Chopper..cStabilized Low-Noise Opera:tiona:IAmplifier .......................................... .4-57
ICL7660 CMOS Voltage Converter ................•..... ; ....................................................... 5-12
ICL7662 CMOS Voltage Converter ....•......................................................................... 5-20
ICL7663 CMOS Programmable Micropower Positive Voltage Regulator ..................... , ........... 5-27
ICL7664 CMOS Programmable MicrOpower Negative Voltage Regulator ......... : ..... ; .............. 5-27
ICL7665 Micropower Under/Over Voltage Detector .......................................................... 5-39
ICL7667 Dual Power MOSFET .Driver ............................................................................5-47
ICL7673 Automatic Battery Back-up Switch .................................................................... 5-55
ICL8007 JFET Input Operational Amplifier! .................... ; .... :.\ ........................... , ............ 4-65
ICL8013 Four Quadrant Analog Multiplier ..................................................................... 5-63
ICL8018A 4-Bit Expandable Current Switch ........ : .......................................... , ............ 6-151
ICL8019A 4-Bit Expandable Current Switch ................................................................ 6-151
ICL8020A 4-Bit Expandable Current Switch ...... '.; ........ : ........................... ; .... ; .............. 6-151
ICL8021 Low Power Bipolar Operational Amplifier ... , .................. " .................................. 4-69
ICL8022 Dual Low Power Bipolar Operational Amplifier ................................................... .4-69
ICL8023 Triple Low Power Bipolar Operational Amplifier ................ , ........... , .................... .4-69
ICL8038 Precision Waveform GeneratorlVoltage Controlled Osc;iIIat9r ........................•........ 5-72
ICL8043 Dual JFET Input Operational Amplifier ................................ ; ............................. 4-74
ICL8048 Logarithmic Amplifier ............................... ~ ....................... ; ............................ .4:-82
ICL8049 Antilog Amplifier ........................................................................................ .4-82
ICL8063 Power Transistor Driver I Amplifier ............ ",'" ................ ~ .... ,; .... "...................... .4-90
ICL8069 Low Voltage Reference ............•• ; ...... ;......•.................... :; .. ; ............................. 5-81
.ICL8211 Programmable Voltage Detector ..................................................................... 5-,83

16

Alphanumeric Index

(Continued)

ICL8212 Programmable Voltage Detector ..................................................................... 5-83
ICM7170 I.LP-Compatible Real-Time Clock ..................................................................... 9-1
ICM7206 CMOS Touch-Tone Encoder .......................................................................... 7-1
ICM7207 / A CMOS Timebase Generator ....................................................................... 7 -10
ICM7208 7-Digit LED Display Counter ......................................................................... 7 -15
ICM7209 Timebase Generator ................................................................................... 7 -22
ICM7211 4-Digit LCD/LED Display Driver ..................................................................... 8-1
ICM7212 4-Digit LCD/LED Display Driver ..................................................................... 8-1
ICM7213 One Second/One Minute Timebase Generator ................................................. 7 -25
ICM7215 6-Digit LED Display 4-Function Stopwatch ...................................................... 7 -30
ICM7216A 8-Digit Multi-Function Frequency Counter/Timer .............................................. 7-36
ICM7216B 8-Digit Multi-Function Frequency Counter/Timer •............................................. 7 -36
ICM7216C 8-Digit Multi-Function Frequency Counter/Timer .............................................. 7 -36
ICM7216D 8-Digit Multi-Function Frequency Counter/Timer ............................................. 7-36
ICM7217 4-Digit LED Display Programmable Up/Down Counter ........................................ 7 -52
ICM7218 8-Digit LED Multiplexed Display Driver ............................................................ 8-1 0
ICM7224 4 1'2-Digit LCD/LED Display Counter .............................................................. 7 -67
ICM7225 4 1'2-Digit LCD/LED Display Counter .~ ............................................................. 7 -67
ICM7226A1B 8-Digit Multi-Function Frequency Counter/Timer .......................................... 7 -75
ICM7227 4-Digit LED Display Programmable Up/Down Counter ........................................ 7 -52
ICM7231 Numeric Triplexeq LCD Display Driver ............................................................ 8-20
ICM7232 Numeric Triplexed LCD Display Driver ............................................................ 8-20
ICM7233 Alphanumeric Triplexed LCD Display Driver ...................................................... 8-20
ICM7234 Alphanumeric Triplexed LCD Display Driver .........•.............................. ; ............• 8-20
ICM7235 4-Digit Vacuum Fluorescent Display Driver ...................................................... 8-40
ICM7236 4 1'2-DigitCounterlVacuum Fluorescent Display Driver. ....................................... 7-88
ICM7240 Programmable Timer ................................................................................... 7 -93
ICM7241 Timebase Generator ................................................................................. 7 -103
ICM7242 Long-Range Fixed Timer ........................................................................... 7 -105
ICM7243 8-Character LED I.LP-Compatible Display Driver ................................................ 8-45
ICM7245 Stepper Motor Quartz Clock ... ; ................................................ ~ ........... , ...... 7 -111
ICM7249 5-1'2 Digit LCD I.L-Power Event/Hour Meter .................................................... 7-115
ICM7250 Programmable Timer ................................................................................... 7 -93
ICM7260 Programmable Timer ................................................................................... 7-93
ICM7280 Dot Matrix LCD Controller/Row Driver ............................................................ 8-54
ICM7281 40-Column LCD Dot Matrix Display Driver ....................................................... 8-69
ICM7283 LCD Dot Matrix Controller/Row Driver ............................................................ 8-79
ICM7555 General Purpose Timer ..............................•............................................... 7 -123
ICM7556 Dual General Purpose Timer ....................................................................... 7 -123
10100 Dual Low Leakage Diode ................................................................................ 2-74
10101 Dual Low Leakage Diode ................................................................................ 2-74
IH311 High Speed SPST 4-Channel Analog Switch ....................................................... 3-52
IH312 High Speed SPST 4-Channel Analog Switch ....................................................... 3-52
IH401 QUAD Varafet Analog Switch ........................................................................... 3-59
IH401A QUAD Varafet Analog Switch ......................................................................... 3-59
IH5009 Quad 100 Ohm Virtual Ground Analog Switch .................................................... 3-65
IH5010 Quad 150 Ohm Virtual Ground Analog Switch .................................................... 3-65
IH5011 Quad 100 Ohm Virtual Ground Analog Switch .................................................... 3-65
IH5012 Quad 150 Ohm Virtual Ground Analog Switch .................................................... 3-65
IH5013 Triple 100 Ohm Virtual Ground Analog Switch .................................................... 3-65
IH5014 Triple 150 Ohm Virtual Ground Analog Switch .................................................... 3-65
IH5015 Triple 100 Ohm Virtual Groung Analog Switch ........... ; ........................................ 3-65
IH5016 Triple 150 Ohm Virtual Ground Analog Switch .................................................... 3-65
IH5017 Dual 100 Ohm Virtual Ground Analog Switch ..................................................... 3-65

17

Alphanumeric Index
IH5018
IH5019
IH5020
IH5021
IH5022
IH5023
IH5024
IH5025
IH5026
IH5027
IH5028
IH5029
IH5030
IH5031
IH5032
IH5033
IH5034
IH5035
IH5036
IH5037
IH5038
IH5040
IH5041
IH5042
IH5043
IH5044
IH5045
IH5046
IH5047
IH5048
IH5049
IH5050
IH5051
IH5052
IH5053
IH5108
IH5110
.IH5111
IH5112
IH5113
IH5114
IH5115
IH5116
IH5140
IH5141
IH5142
IH5143
IH5144
IH5145
IH5148
IH5149
IH5150
IH5151
IH5200

(Continued)

Dual 150 Ohm Virtual Ground Analog Switch ....... : .................. ; .................. ; ...... ,30-65
f"'ual 100 Ohm Virtual Ground Analog Switch ..................................................... 3-65
Dual 150 Ohm Virtual Ground Analog Switch ................ : ......................•............. 3-65
Single 100 Ohm Virtual Ground Analog Switch , ............. ; .................................... 3-65
Single 150 Ohm Virtual Ground Analog Switch ................. ; ................................. 3-65
Single 100 Ohm Virtual Ground Analog Switch .................................. ; .... , .......... ;.3-65
Single 150 Ohm Virtual Ground Analog Switch ................................................... 3-65
Quad 100 Ohm Positive Signal Analog Switch .........................................,............ 3-71
Quad 150 Ohm Positive Signal Analog Switch ..................................................... 3-71
Quad 100 Ohm Positive Signal Analog Switch .................................................... 3-71
Quad 150 Ohm Positive Signal Analog Switch ..................................................... 3-71
Triple 100 Ohm Positive Signal Analog Switch ............ ; ....................................... 3-71
Triple 150 Ohm Positive Signal Analog Switch .................................................... 3-71
Triple 100 Ohm Positive Signal Analog .Switch .................................................... 3-71
Triple 150 Ohm Positive Signal Analog Switch .................................................... 3- 71
Dual 100 Ohm Positive Signal Analog Switch ........... : ......................................... 3-71
Dual 150 Ohm Positive Signal Analog Switch ..................................................... 3-71
Dual 100 Ohm Positive Signal Analog Switch ..................................................... 3-71
Dual 150 Ohm Positive Signal Analog Switch ..................................................... 3-71
Single 100 Ohm Positive Signal Analog Switch ................................................... 3-71
Single 150 Ohm Positive Signal Analog Switch ................................................... 3-71
SPST 75 Ohm High-Level CMOS Analog Switch ................................................. 3-79
Dual SPST 75 Ohm High-Level CMOS Analog Switch .......................................... 3-79
SPOT 75 Ohm High-Level CMOS Analog Switch ................................................. 3-79
Dual SPOT 75 Ohm High-Level CMOS Analog Switch .......................................... 3-79
DPST 75 Ohm High-Level CMOS Analog Switch ................................................. 3-79
Dual DPST 75 Ohm High-Level CMOS Analog Switch .......................................... 3-79
DPDT 75 Ohm High-Level CMOS Analog Switch ............................................ , .... 3-79
4PST 75 Ohm High-Level CMOS Analog Switch ...............•................................. 3-79
Dual SPST 35 Ohm High-Level CMOS Analog SWitch .......................................... 3-88
Dual DPST 35 Ohm High-Level CMOS Analog Switch .......................................... 3-88
SPOT 35 Ohm High-Level CMOS Analog Switch ................................................. 3-88
Dual SPOT 35 Ohm High-Level CMOS Analog Switch .......................................... 3-88
QUAD CMOS Analog Switch ........................................................................... 3 .... 93
QUAD CMOS Analog Switch ........................................................................... 3-93
8-Channel Fault Protected Analog Multiplexer ..................................................... 3-99
General Purpose Sample & Hold ..................................................................... 5-94
General Purpose Sample & Hold ..................................................................... 5-94
General Purpose Sample & Hold ..................................................................... 5-94
General Purpose Sample & Hold .................................. ; .................................. 5-94
General Purpose Sample & Hold ..................................................................... 5-94
General Purpose Sample & Hold ..................................................................... 5-94
16-Channel Fault Protected Analog Multiplexer ........... "..................................... 3-107
SPST High-Level CMOS Analog Switch ........................................................... 3-110
Dual SPST High-Level CMOS Analog Switch .................................................... 3-110
SPOT High-Level CMOS Analog Switch ........................................................... 3'-110
Dual SPOT High-Level CMOS Analog Switch .................................................... 3-110
DPST High-Level CMOS Analog Switch ........................................................... 3-110
Dual ,DPST High-Level CMOS Analog Switch .................................................... 3-110
Dual SPST High-Level CMOS Analog Switch .................................................... 3-119
Dual DPST High-Level CMOS Analog Switch .................................................... 3-119
SPOT High-Level CMOS Analog Switch ... ; ............ : .......................................... 3-119
Dual SPOT High-Level CMOS Analog Switch .................................................... 3-119
Dual SPST CMOS Analog Switch ................. ,' .................................................. 3-27

18

Alphanumeric Index

(Continued)

IH5201 Quad SPST CMOS Analog Switch ................................................................... 3-32
IH5208 4-Channel Differential Fault Protected Analog Multiplexer .................................... 3-127
IH5216 8-Channel Differential Fault Protected Analog Multiplexer .................................... 3-135
IH5341 Dual SPST CMOS RFlVideo Switch ............................................................... 3-138
IH5352 QUAD SPST CMOS RFlVideo Switch ............................................................. 3-144
IH6108 8-Channel CMOS Analog Multiplexer .............................................................. 3-149
IH6116 16-Channel CMOS Analog Multiplexer ............................................................ 3-155
IH6201 Dual CMOS DriverlVoltage Translator ............................................................. 3-162
IH6208 4-Channel Differential CMOS Analog Multiplexer ............................................... 3-166
IH6216 8-Channel Differential CMOS Analog Multiplexer ............................................... 3-172
IM80C35 8-8it CMOS Microcontroller .......................................................................... 9-33
IM80C39 8-8it CMOS Microcontroller .......................................................................... 9-33
IM80C48 8-8it CMOS Microcontroller .......................................................................... 9-33
IM80C49 8-8it CMOS Microcontroller .......................................................................... 9-33
IM82C43 CMOS I/O Expander .................................................................................. 9-45
IM4702/4712 8aud Rate Generator ............................................................................. 9-9
IM6402 Universal Asynchronous Receiver Transmitter (UART) .......................................... 9-16
IM6403 Universal Asynchronous Receiver Transmitter (UART) .......................................... 9-16
IM6653 4096-8it CMOS UV EPROM .......................................................................... 9-25
IM6654 4096-8it CMOS UV EPROM .......................................................................... 9-25
IMF6485 Dual N-Channel JFET Low Noise Amplifier ...................................................... 2-62
IT100 P-Channel JFET Switch ................................................................................... 2-76
In01 P-Channel JFET Switch ................................................................................... 2-76
IT120 Dual NPN General Purpose Amplifier .................................................................. 2-77
IT120A Dual NPN General Purpose Amplifier ................................................................ 2 - 77
IT121 Dual NPN General Purpose Amplifier .................................................................. 2-77
IT122 Dual NPN General Purpose Amplifier .................................................................. 2-77
IT124 Dual Super.,..8eta NPN General Purpose Amplifier .................................................. 2-79
IT126 Dual NPN General Purpose Amplifier .................................................................. 2-81
IT127 Dual NPN General Purpose Amplifier .................................................................. 2-81
IT128 Dual NPN General Purpose Amplifier. ................................................................. 2-81
IT129 Dual NPN General Purpose Amplifier .................................................................. 2..,81
IT130 Dual PNP General Purpose Amplifier ......., .......................................................... 2-83
IT130A Dual PNP General Purpose Amplifier ................................................................ 2-83
.IT131 Dual PNP General Purpose Amplifier .................................................................. 2-83
IT132 Dual PNP General Purpose Amplifier ... ; .............................................................. 2-83
IT136 Dual PNP General Purpose Amplifier .................................................................. 2-85
IT137 Dual PNP General Purpose Amplifier .................................................................. 2-85
IT138 Dual PNP General Purpose Amplifier ............................................................ , ..... 2-85
IT139 Dual PNP General Purpose Amplifier .................................................................. 2-85
IT500 Dual Cascoded N-Channel JFET General Purpose Amplifier .................................... 2-87
IT501 Dual Cascoded N-Channel JFET General Purpose Amplifier .................................... 2-87
IT502 Dual Cascoded N-Channel JFET ~eneral Purpose Amplifier .................................... 2-87
IT503 Dual Cascoded N-Channel JFET General Purpose Amplifier .................................... 2-87
IT504 Dual Cascoded N-Channel JFET General Purpose Amplifier ....... : ............................ 2-87
IT505 Dual Cascoded N-Channel JFET General Purpose Amplifier .................................... 2-87
IT550 Dual N-Channel JFET Switch ........................................................................... 2-90
IT1700 P-Channel Enhancement Mode MOSFET General Purpose Amplifier ........................ 2-92
IT1750 N-Channel Enhancement Mode MOSFET General Purpose Amplifier/Switch .............. 2-93
IT5911 Dual N-Channel JFET High Frequency Amplifier .................................................. 2-58
IT5912 Dual N-Channel JFET High Frequency Amplifier .................................................. 2-58
ITE4091 N-Channel JFET Switch ............................................................................... 2..,.19
ITE4092 N-Channel JFET Switch ............................................................................... 2-19
ITE4093 N-Channel JFET Switch ............................................................................... 2-19

19

Alphanumeric Index

(Continued)

ITE4391 N-Channel JFET Switch .................................... ; ... :; ..... : ................ : ............. 2....:26
ITE4392 N-Channel JFET Switch ............. : .. ;;' ............. : . .'. .' .......•.... , ..... : ....................... 2-26
ITE4393 N-Channel JFET Switch .............................................................................. 2-26
ITE4416 N-Channel JFET High Frequency Amplifier ............................ ~, ......................... 2-28
J105 N-Channel JFET Switch .................................... : ................... : ......... ,................. 2-94
J106 N-Channel JFET Switch ................................................................................... 2-94
J107 N-Channel JFET Switch ............................................................ : ...................... 2-94
J 111 'N-Channel JFET Switch ................................................................................... 2 - 95
J112 N-Channel JFET Switch ................................................................... : ............... 2-95
J113 N-Channel JFET Switch .................................................................................. :2-95
J174 P-Channel JFET Switch ................................................................................ ; ... 2-97
J175 P-Channel JFET Switch ................................................................................... :2-97
J176 P-Channel JFET Switch .........................................................·............................ 2-97
J177 P-Channel JFET Switch .................................................................................... 2-97
J201 N-Channel JFET General Purpose Amplifier ...................................... , ................... 2-99
J202 N-Channel JFET General Purpose Amplifier .......................................................... 2-99
J203 N-Channel JFET General Purpose Amplifier ........................................................... 2-99
J204 N-Channel JFET General Purpose Amplifier .......................................................... 2-99
J308 N-Channel JFET High Frequency Amplifier ......................................................... 2-100
J309 N-Channel JFET High Frequency Amplifier ....................................... ; ................. 2-100
J310 N-Channel JFET High Frequency Amplifier ........ ! ................................................ 2-100
LH2108 Dual Super-Beta Operational Amplifier ................................. ; ........................... 4-99
LH2308 Dual Super-Beta Operational Amplifier ............................................................. 4-99
LM1 081 A Super-Beta Operational Amplifier ................................................................ 4-102
LM114/H Dual NPN General Purpose Amplifier ........................................................... 2-102
LM 114A1 AH Dual NPN General Purpose Amplifier ............... ; ................ : ...................... 2 -102
LM308/A Super-Beta Operational Amplifier ................................................................ 4-102
M116 Diode Protected N-Channel Enhancement Mode MOSFET General Purpose Amplifier. 2-104
MM450 Dual Differential High Voltage Analog Switch ................................................... 3-178
MM451 Four Channel High Voltage Multiplexer ........................................................... 3-178
MM452 Quad SPST High Voltage Analog Switch ......................................................... 3-178
MM455 Three SPST High Voltage Analog Switch ....................... ~ ................................. 3-178
MM550 Dual Differential High Voltage Analog Switch ................................................... 3-178
MM551 Four Channel High Voltage Multiplexer ...................... ; ........... : ........................ 3-178
MM552 Quad SPST High Voltage Analog Switch ......................................................... 3 -178
MM555 Three SPST High Voltage Analog Switch ........................................................ 3-178
NE/SE592 Video Amplifier ................................................................................. , .... 4-106
U200 N-Channel JFET Switch ..................................................................... : ........... 2-105
U201 N-Channel JFET Switch ..........................................'....................................... 2-105
U202 N-Channel JFET Switch ................................................................................. 2-105
U23.1 Dual N-Channel JFET General Purpose Amplifier ................................................ 2-106
U232 Dual N-Channel JFET General Purpose Amplifier ................................................ 2-106
U233 Dual N-Channel JFET General Purpose Amplifier ................................................ 2-106
U234 Dual N-Channel JFET General Purpose Amplifier ................................................ 2-106
U235 Dual N-Channel JFET General Purpose Amplifier ........... : .................................... 2-106
U257 Dual N-Channel JFET High Frequency Amplifier .................................................. 2-108
U304 P-Channel JFET Switch ................................................................................. 2-109
U305 P-Channel JFET Switch .......................................................... ; ....... ~ .............. 2-109
U306 P-Channel JFET Switch ............................................................................ : .... 2-109
U308 N-Channel JFET High Frequency Amplifier ......................................................... 2-111
U309 N-Channel JFET High Frequency Amplifier ......................................................... 2-111
U310 N-Channel JFET High Frequency Amplifier ......................................................... 2-111
U401 Dual N-Channel JFET Switch .......................................................................... 2-113
U402 Dual N-Channel JFET Switch ........................................................................... 2-113

20

Alphanumeric Index

(Continued)

U4o.3 Dual N-Channel JFET Switch .......................................................................... 2-113
U404 Dual N-Channel JFET Switch .......................................................... ; ................ 2-113
U4o.5 Dual N-Channel JFET Switch .......................................................................... 2-113
U4o.6 Dual N-Channel JFET Switch ...................................... ; ................................... 2-113
U1897 N-Channel JFET Switch ............................................................................... 2-115
. U1898 N-Channel JFET Switch ........................................................................ ~ ...... 2-115
U1899 N-Channel JFET Switch ............................................................................... 2-115
VCR2N Voltage Controlled Resistors ......................................................................... 2-117
VCR3P Voltage Controlled Resistors ......................................................................... 2-117
VCR4N Voltage Controlled Resistors ......................................................................... 2-117
VCR7N Voltage Controlled Resistors ......................................................................... 2-117
VCR 11 N Voltage Controlled Resistors ....................................................................... 2 -120.

21

IIO~OIl.

,408-996-5000
TWl<;" 91'0-338-2014

10600'Ridgeview Court, Cupertino, CA 95014

ALPHANUMERIC CROSS REFERENCE
ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

-ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

103M

2N5458
2N3684
2N5686
2N5457
2N5457

2N2606
2N2607
2N2608
2N2609
2N2609JAN

2N2607
2N2607
2N2608
2N2609
2N2609JAN

2N3331
2N3332
2N3333
2N3334
2N3335

2N5270
2N5268
1T132
1T132
ITr32

1035
104M
105M
105U
106M

2N5459
2N5458
2N5459
2N434O
2N5485

2N2639

1T120
ITI22

1Tl22
1T120
1Tl22

2N3336
2N3347
2N3348
2N3349
2N3350

1T132

2N2640

2N2641
2N2642
2N2643

107M

2N5485
2N3685
2N3686
'2N4339
2N3822

2N2644
2N2652
2N2652A
2N2720
2N2721

IT122
1Tl20
1T120
1Tl20
ITI22

2N3351
2N3352
2N3365
2N3366
2N3367

1T138
1Tl39
2N434O
2N4338
2N4338

2N3821
2N3822
2N4341

2N2722
2N2802
2N2803
2N2804
2N2805

1Tl20
\ln39
'Tl39
1Tl39
1T139

2N3368
2N3369
2N3370
2N3376
2N3378

1284A
1285A
1286A
130U

2N4340
2N4222
2N3821
2N4220
2N3687

2N2806
2N2807
2N2841
2N2842
2N2843

1T139
1Tl39
2N2607
2N2607
2N2607

1325A
135U
14T
155u
1714A

2N4222
2N4339
2N4224
2N4416
2N434O

2N2844
2N2903
2N2903A
2N2910
2N2913

1825
1835
1975
1985
1995

2N4391
2N3823
2N4338
2N434O
2N4341

2N2914
2N2915

2oo0M
2001M
2005
200U
2015

2N3823
2N3823
2N4392
2N3824
2N4391

2025
2035
2045
2078A
2079A

1005
100U
102M
1025

IIDU
120U
125U
1277A
1278A
1279A
1280A
1281A
1282A
1283A

SD:~:,=~;~'i,CT

INTERSIL
EQU,IVALENT,

2N3814
2N381,5
2N3816
2N3816A
2N3817

ITI32
1T132
1T130'
ITI30A
1T130

2N3817A
2N3819
' 2N3820
2N3821
2N3822

lT1aOA
2N5484
2N2608
2N3821
2N3822

2N3823
2N3824
2N3907
2N3908
2N3909

2N3823
2N3824
1T120
1T120
2N2609

2N4341
2N4339
2N4338
2N2608
2N2608

2N3909A
2N3921
2N3922
2N3949
2N3950

2N2609
2N3921
2N3922
1T132
1Tl32

2N3380
2N3382
2N3384
2N3386
2N3409

2N2609
2N3994
2N3993
2N5114
1Tl22

2N3954
2N3954A
2N3955
2N3955A
2N3956

2N395'
2N3954A
2N3955
2N3955A
2N3956

2N2607
ITI22
1Tl20
1T122
1Tl22

2N3410
2N3423
2N3424
2N3425

1Tl22
1Tl22
1Tl22
1T122
1T122

2N3957
2N3966
2N3967
2N3967A
2N3968

2N3957
2N4416
2N4221
2N4221
2N3685

1Tl20
1Tl20
1Tl20
1Tl20
ITI20

2N3436
2N3437
2N3438
2N3452
2N3453

2N4341
2N434O
2N4338
2N4220
2N4338

2N3968A
2N3969
2N3969A
2N3970
2N3971

2N3685
2N3686
2N3686
2N3970
2N3971

2N2917
2N2918
2N2919
2N2919A
2N2920

1Tl22
1Tl20
1T120
2N2920

2N3454
2N3455
2N3456
2N3457
2N3458

2N4338
2N4340
2N4338
2N4338
2N4341

2N3972
2N3993
2N3993A
2N3994
2N3994A

2N3972
2N3993
2N3993
2N3994
2N3994

2N4392
2N3821
2N3821
2N3955
2N3955

2N2920A
2N2936
2N2937
2N2972
2N2973

2N2920
1Tl20
1T120
1T122
1T122

2N3459
2N3460
2N3513
2N3514
2N3515

2N4339
2N4338
ITl22
1T122
1T122

2N4009
2N4010
2N4011
2N4015
2N4016

ITI32
1T132
1T132
1T139
1T137

2N3821
2N4224

2N2915A

2N2916
2N2916A

2N3411

ITI22

ITl37

1T138
1T139
1T137

I

2080A
2081A

2N3955A

2093M
2094M
2095M

2N3687
2N3686
2N3686

2N2974
2N2975
2N2976
2N2977
2N2978

1T120
1T120
ITl20
1T120
1T120

2N3516
2N3517
2N3521
2N3522
2N3574

ITi22
1T122
1T122
1T122
2N2607

2N4017
2N4018
2N4019
2N4020
2N4021

1T139
1T139
1T139
ITl39

2098A
2099A
210U
2130U
Z132U

2N3954
2N3955A
2N4416
2N5452
2N3955

2N2979
2N2980
2N2981
2N2982
2N3043

1T120
1T121
1T122
1T122
1T121

2N3575
2N3578
2N3587
2N3608
2N3680

2N2607
2N2608
1T122
3N172
1Tl20

2N4022
2N4023
2N4024
2N4025
2N4026

ITl39
1T137
ITl37 '
ITI37
3N163

2134U

2N3956

2N3955A

11139

2136U

2N3957

2138U
2139U
2147U

2N3958
2N3958
2N3958

2N3044
2N3045
2N3046
2N3047
2N3048

ITI22
1T122
1T121
1T122
1T122

2N3684
2N3684A
2N3685
2N3685A
2N3686

2N3684
2N3684
2N3685
2N3685
2N3686

2N4038
2N4039
2N4065
2N4066
2N4067

2N4351
2N4351
3N163
3N166
3N166

2148U
2149U
2315
2325
2335

2N3958
2N3958
2N3954
2N3955
2N3956

2N3049
2N3050
2N3051
2N3052
2N3059

1T139
1Tl39
1Tl39
1T129
1Tl39

2N3686A
2N3687
2N3687A
2N3726
2N3727

2N3686
2N3687
2N3687
1T131
1T130

2N4082
2N4083
2N4084
2N4085
2N4091

2N3954
2N3955
2N3954
2N3955
2N4091

2345
2355

2N3957
2N3958
2N4869
2N4091
2N4392

2N3066
2N3067
2N3068
2N3069
2N3070

2N4340
2N4338
2N4338
2N4341
2N4339

2N3728
2N3729
2N3800
2N3801
2N3802

ITI22
1T121
1T132
1T132
1T132

2N4091A

2N409IJAN,
2N409IJANTX
2N409IJANTXV
2N4092

2N4091
2N409IJAN
2N409IJANTX
2N409lJANTXV
2N4092

2N2060
2N2060A
2N20608
2N2223
2N2223A

1T120
1T121
ITl22
ITl21

2N3071
2N3084
2N3085
2N3086
2N3087

2N4338
2N4339
2N4339
2N4339
2N4339

2N3803
2N3804
2N3804A
2N3805
2N3805A

1Tl32
1T13O
1T130A
ITl30
1T130A

2N4092A
2N4092JAN
2N4092JANTX
2N4092JANTXV
2N4093

2N4092
2N4092JAN
2N4092JANTX
2N4092JANTXV
2N4093

2N2386
2N2386A
2N2453
2N2453A
2N2480

2N2608
2N2608
1Tl22
1Tl21
1T122

2N3088
2N3088A
2N3089
2N3089A
2N3113

2N4339
2N4339
2N4339
2N4339
2N2607

2N3806
2N3807
2N3808
2N3809
2N3810

ITI22

2N4093A

1T122
1T122
1Tl22
2N3810

2N4093JAN
2N4093JANTX
2N4093JANTXV
2N41oo

2N4093
2N4093JAN
2N4093JANTX
2N4093JANTXV
2N4100

2N2480A
2N2497
2N2498
2N2499
2N2500

ITl21
2N2608
2N2608
2N2609
2N2608

2N3277
2N3278
2N3328
2N3,329
2N3330

2N2606
2N2607
2N5265
2N5267
2N5268

2N3812
2N3813

2N381OA
2N3811
2N3811A
1T132
1T132

2N4117
2N4117A
2N4118
2N4118A
2N4119

2N4117
2N4117A
2N4118
2N4118A
2N4119

241U

250U
251U

1T12l

"CONSULT FACTORY

2N3810A

~~~mA

22

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRO~UCT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

2N4119A
2N4120
2N4139
2N4Z20
2N4220A

2N4119A
3N163
2N3822
2N4220
2N4220

2N5045
2N5046
2N5047
2N5078
2N5090

2N5453
2N54S4
2N5454
2N5397
1T122

2N5484
2N5485
2N5486
2N5515
2N5516

2N5484
2N548S
2N5486
2N5515
2N5516

2N6484
2N6485
2N6502
2N6503
2N6550

2N6484
2N648S
ITl22
ITl22
2N4868A

2N4221
2N4221A
2N4222
2N4222A
2N4223

2N4221
2N4221
2N4222
2N4222
2N4223

2N5103
2N5104
2N5105
2N5114
2N5114JAN

2N4416
2N4416
2N4416
2NSl14
2NSl14JAN

2N5517
2N5518
2NS519
2N5520
2N5521

2N5517
2N5518
2N5519
2N5520
2N5521

2N6568
25C294
25Jll
25J12
25J13

2N5432
1T122
2N2607
2N2607
2N5270

2N4224
2N4267
2N4268
2N4302
2N4303

2N4224
3N163
3N161
2N4302
2N5459

2N5114JANTX
2N5114JANTXV
2N5115
2N5115JAN
2N5115JANTX

2N5114JANTX
2N5114JANTXV
2N5115
2N5115JAN
2N5115JANTX

2N5522
2N5523
2N5524
2N5545
2N5546

2N5522
2N5523
2N5524
2N3954
2N3955A

25J15
25J16
25J47
25J48
25J49

2N2607
~~2607

2N4304
2N4338
2N4339
2N4340
2N4341

2N5458
2N4338
2N4339
2N4340
2N4341

2N5115JANTXV
2N5116
2N5116JAN
2N5116JANTX
2N5116JANTXV

2N5115JANTXV
2N5116
2N5116JAN
2N5116JANTX
2N5116JANTXV

2N5547
2N5549
2N5555
2N5556
2N5557

2N3955
2N4093
J310
2N3685
2N3684

25J50
25J78
25J79
25J80
25Kll

2N4342
2N4343
2N4351
2N4352
2N4353

2N5461
2N5462
2N4351
3N163
3Nl72

2NSl17
2NSllB
2N5119
2N5120
2N5121

2NS117
2N5118
2N5119
1Tl31
1T132

2N5558
2N5561
2N5562
2N5563
2N5564

2N3684
U401
U402
U404
IT550

25K12
2SK13
25K132
25K133
25K134

2N4360
2N4381
2N4382
2N4391
2N4392

2N5460
2N2609
2N5115
2N4391
2N4392

2N5!22
2NS123
2N5124
2N5125
2N5158

1Tl32
1T131
1Tl32
1Tl32
2N5434

2N5565
2N5566
2N5592
2N5593
2N5594

IT550
IT550
2N3822
2N3822
2N3822

2SK135
25KI5
2SK17
25K178
2$K179

2N4393
2N4416
2N4416A
2N4417
2N4445

2N4393
2N4416
2N4416A
2N4416
2N5432

2NS159
2N5163
2N5196
2N5197
2N5198

2N5433
2N3822
2N5196
2N5197
2N5198

2N5638
2N5639
2N5640
2N5647
2N5648

2N5638
2N5639
2N564O
2N4117A
2N4117A

25K18
25K180
2SK19
25K23
25K30

ITE4416
2N5459
2N5458

2N4446
2N4447
2N4448
2N4856
2N4856A

2N5434
2N5432
2NS434
2N4856
2N4856

2N5199
2N5245
2N5246
2N5247
2N5248

2N5199
ITE4416
2N5484
2N5486
2N5486

2N5649
2N5653
2N5654
2N5668
2N5669

2N4117A
,2N5638
2N5639
2N5484
2N5485

25K32
25K33
25K34
25K37
2SK41

2N3822
2N5397
2N3822
2N5484
2N5459

2N4856JAN
2N4856JANTX
2N4856JANTXV
2N4857
2N4857A

2N4856JAN
2N4856JANTX
2N4856JANTXV
2N4857
2N4857

2N5254
2N52S5
2N5256
2N5257
2N5258

ITI32
1Tl32
1Tl30
2N5457
2N5458

2NS670
2N5793
2N5794
2N5795
2N5796

2N5486
1T129
1Tl29
ITl39
1Tl39

2SK42
25K43
25K44
25K46
25K48

2N3822
ITE4092
ITE4416
2N5459
2N3821

2N4857JAN
2N4857 JANTX
2N4857JANTXV
2N4858
2N4858A

2N4857JAN
2N4857JANTX
2N4857 JANTXV
2N4858
2N4858

2N5259
2N5265
2N5266
2N5267
2N5268

2N5459
2N2607
2N2607
2N2608
2N2608

2N5797
2N5798
2N5799
2N5800
2N5801

2N2608
2N2608
2N2608
2N2608
2N4393

25K49
25K50
25K54
25K55
25K56

2N5484
ITE4416
2N3822
2N3822
2N5459

2N4B58JAN
2N4858JANTX
2N4858JANTXV
2N4859
2N4859A

2N485BJAN
2N4858JANTX
2N4858JANTXV
2N4859
2N4859

2N5269
2N5270
2N5277
2N5278
2N5358

2N2609
2N2609
2N4341
2N4341
2N4220

2N5802
2N5803
2N5843
2N5844
2N5902

2N4393
2N4392
1Tl30
ITl30
2N5902

2SK61
25K65
25K66
25K68
2SK72

2N5397
J201
2N3821
2N3822
2N5196

2N4859JAN
2N4859JANTX
2N4860
2N4860A
2N4860JAN

2N4856JAN
2N4856JANTX
2N4860
2N4860
2N4857JAN

2N5359
2N5360
2N5361
2N5362
2N5363

2N4220
2N4221
2N4221
2N4222
2N4222

2N5903
2N5904
2N5905
2N5906
2N5907

2N5903
2N5904
2N5905
2N5906
2N5907

3G5
3N145
3N146
3N147
3N148

2N3821
3N163
3N163
3N189
3N189

2N4860JANTX
2N4861
2N4861A
2N486IJAN
2N4861JANTX

2N4B57 JANTX
2N4861
2N4861
2N4858JAN
2N4858JANTX

2N5364
2N5391
2N5392
2N5393
2N5394

2N4222
2N4867A
2N4B68A
2N4869A
2N4869A

2N5908
2N5909
2N5911
2N5912
2N5949

2N5908
2N5909
2N5911
2N5912
2N5486

3N149
3N15O
3N151
3N155
3N155A

3Nl61
3N163
3N190
3N163
3N163

2N4867
2N4867A
2N4868
2N4868A
2N4869

2N4867
2N4867A
2N4868
2N4868A
2N4869

2N5395
2N5396
2N5397
2N5398
2N5432

2N4869A
2N4869A
2N5397
2N5398
2N5432

2N5950
2N5951
2N5952
2N5953
2N6085

2N5486
2N5486
2N5484
2N54B4
1Tl22

3N156
3N156A
3N157
3N157A
3N158

3N163
3N163
3N163
3N163
3N163

2N4869A
2N4878
2N4879
2N4880
2N4937

2N4869A
2N4878
2N4879
2N4880
1n31

2N5433
2N5434
2N5452
2N5453
2N5454

2N5433
2N5434
2N5452
2N5453
2N5454

2N60B6
2N6087
2N6088
2N6089
2N6090

ITI22
1T121
ITI21
ITI22
1Tl21

3N158A
3N160
3N161
3N163
3N164

3N163
3N161
3N161
3Nl63
3N164

2N4938
2N4939
2N494O
2N4941
2N4942

ITI32
IT132
IT132
1T131
1Tl32

2N5457
2NS458
2N5459
2N5460
2N5461

2N5457
2N5458
2N5459
2N5460
2N5461

2N6091
2N6092
2N6441
2N6442
2N6443

1T121
1T121
ITl22
1Tl22
ITl22

3N165
3N166
3N167
3N168
3N169

3N165
3N166
3N161
3N161
3N170

2N4955
2N4956
2N4977
2N4978
2N4979

1Tl22
1Tl22
2N5433
2N5433
2N4859

2N5462
2N5463
2N5464
2N5465
2N5471

2N5462
2N5463
2N5464
2N5465
2N5265

2N6444
2N6445
2N6446
2N6447
2N6448

IT122
ITl21
ITl21
1Tl21
1T121

3N170
3N171
3NI72
3N173
3N174

3N170
3N171
3N172
3NI73
3N163

2N5018
2N5019
2N502O
2N5021
2N5033

2N5018
2N5019
2N2843
2N2607
2N5460

2N5472
2N5473
2N5474
2N5475
2N5476

2N5265
2N5265
2N5265
2N5265
2N5266

2N6451
2N6452
2N6453
2N6454
2N6483

U310
U310
U310
U310
2N6483

3N175
3N176
3N1n
3N178
3N179

3N170
3N170
3N171
3NI72
3N172

"CONSULT FACTORY

I
23

....
..

......

2N5457
2NS457
~~5457

....
..
..

2N4868
2.~5484

2.~3821

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE

SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALT£RNATE
SOURCE PRODUCT

INTEIISIL
EQUIVALENT

ALT.ERNATE
SOURCE PRODUCT '

, INTERSIL
EQUIVALENT

3NI80 '
3NI81
3NI82
3NI83
3NI88

3NI72
3NI61
3NI61
3NI61
3NI88

AD7520KD
AD7520KN
AD7520LD
AD7520LN
AD7520SD

AD7520KD
AD7520KN
AD7520LD
AD7520LN
AD7520SD

AH0139D/883
AHOI4OCD
AHOl4OD
AH0140D/883
AHOl41CD

DG I 39AK/883B
DGl40BK
DGI40AK
DG 140AKl883B
DGI41BK

BF801
BF802
BF804
BF805
BF806

2N4867
2N4338
2N4338
2N4869
2N4869

3NI89
3NI90
3NI91
3N207
3N208

3NI89
3NI9O
3NI91
3NI90
3NI88

AD7520TD
AD7520UD
AD752lJD
AD752lJN
AD7521KD

AD7520TD
AD7520UD
AD7521JD
AD752lJN
AD7521KD

AHOl41D
AH0141D/883
AHOl42CD
AHOl42D
AH0142D/883

DGI41AK
DGI41AKl883B
DGI42BK
DGI42AK
DG142AK/883B

BF808
BF810
BF811
BF815
BF816

2N4868
2N4858
2N4858
2N4858
2N4858

3SK22
3SK23
3SK28
42T
4360TP

2N5486
2N5397
2N5397
2N4392
2N5462

AD7521KN

BF817

AD7521lD

DG143AK

BF818

AD7521LN
AD7521SD
AD752lTD

AD7521LN
AD7521SD
AD752ITO

AHOl43CD
AH01430
AH0143D/883
AHOl44CD
AHOl44D

DGI43BK

A07521LD

DG143AK/883B
DGI44BK
DGI44AK

BFSIO
BF II
BF 12

2N4858
2N4858
U401
U401
U402

5033TP
588U
58T
59T
703U

2N5460
2N4416
2N5457
2N4416
2N4220

AD7521UD
AD7523AD
AD7523BD
AD7523CD
AD7523JN

AD7521UD
AD7523AD
AD7523BD
AD7523CD
AD7523JN

AHOI44D/883
AHOl45CD
AHOl45D
AH0145D/883
AHOI46CD

DG144AK/883B
DGI45BK
DGI45AK
DG I 45AK/883B
DGI45BK

BFQI3
BFQI4
BF l5
BFS 16
BF 23

U406
IT5912

704U
705U
707U
714U
734EU

2N4220
2N4224
2N4860
2N3822
2N4416

AD7523KN
AD7523SD
AD7523TD
AD7523UD

AD7523KN
AD7523LN
AD7523SD
AD7523TD
AD7523UD

AHOl46D
AHOI46D/883
AHOl51CD
AH0151D/883
AHOl52CD

DGI46AK
DG146AK/8838
DGI5IBK
DGl5IAK/883B
DGI52BK

BF 44
BFr
BF 45
BF 49A
BF 49B

IT5912
2N3055
2N3958

734U
751U
752U
753U
754U

2N5516
2N434O
2N434O
2N4341
2N434O

AD7530JD
AD7530JN
AD7530KD
AD7530KN
AD7530LD

AD7530JD
AD7530JN
AD7530KD
AD7530KN
AD7530LD

AHOl52D
AH0152D/883
AHOl53CD
AHOl53D
AH0153D/883

DGI52AK
DG I 52AK/883B
DGI53BK
DGI53AK,
DG I 53AKlS83B

BFQ49C
BFS21
BFS21A
BFS67
BFS67P

2N3958
2N5199
2N5199
2N3821
2N5459

755U

2N4341
2N434O
ITE4416
ITE4416
2N4416

AD7530LN

DGI54BK

AD753lJN
AD7531KD
AD7531KN

AD7530LN
AD753lJD
AD753lJN
AD7531KD
AD7531KN

AHOl54CD

AI90
AI91
AI92
AI93
AI94
AI95
AI96
AI97

2N5484
2N5484
2N5484
ITE4416
ITE4391

AD7531LD
AD7531LN
AD7533AD
AD7533BD
AD7533CD

AD7531LD
AD7531LN
AD7533AD
AD7533BD
AD7533CD

AI98
AI99
A5T382I
A5T3822
A5T3823

ITE4392
ITE4393
2N5484
2N5484
2N4416

AD7533JN
AD7533KN
AD7533LN
AD7533SD
AD7533TD

AD7533JN
AD7533KN
AD7533LN
AD7533SD
AD7533TD

A5T3824
A5T5460
A5T5461
A5T5462
ADI08

2N4341
2N5460
2N5461
2N5462
LMI08

AD7533UD
' AD754IAD,
AD7541BD
AD754lJN
AD754IKN

AD30B
AD3954A
AD3955
AD3956

LM308
2N3954
2N3954A
2N3955
2N3956

AD3958
AD503
AD589
AD590
AD5905

AD7521KN

A07523LN

U403
U404
U405

U403
lT5912

AH0154D

DG154AK

AHOI54D/883
AHOl55D
AHOl61CD

DGI43AK/883B
DGI5IAK
DGI61BK

BFS68
BFS68P
BFS70
BFS71
BFS72

2N3823
2N4416
2N3821
2N3822
2N3823

AHOl61D
AHOl61D/883
AHOl62CD
AHOl62D
AHOI62D/883B

DGI61AK
DGI61AKl883B
DGI62BK
DGI62AK
DG 162AK/883B

BFS73
BFS74
BFS75
BFS76
BFS77

2N3821
2N4856
2N4858
2N4859

AHOl63CD
AHOl63D/883
AHOl64CD
AHOl64D

DGI63BK
DGI63AK
DG I 63AK/883B
DGI64BK
DGI64AK

BFS78
BFS79
BFS80
BFTIO
BFTlI

2N4860
2N4861
2N4416A
2N5397
2N5019

AD7533UD
AD754IAD
AD7541BD
AD754lJN
AD7541KN

AHO 1640/883
AH5009CN
AH50IOCN
AH5012CN
AH5013CN

DG I 64AK/883B
IH5009CPD
IH50lOCPD
IH5012CPE
IH5013CPD

BFWIO
BFWII
BFWI2
BFWI3
BFW39

2N3823
2N3822
2N4416
2N4867
1Tl29

AD7541SD
AD754lTD
AD810
AD811
AD812

AD7541SD
AD754lTD
2N4878
2N4878
2N4878

AH5014CN
AH5015CN
AH5016CN
AM50llCN
BC264

IH5014CPD
IH5015CPE
IH5016CPE
IH50llCPE
2N5458

BFW39A
BFW54
BFW55
BFW56
BFW61

ITi20
2N3822
2N3822
2N4860
2N4224

2N3958
AD503
ICL8069
AD590
2N5905

AD813
AD814
AD815
AD816
AD818

2N4878
1T124
1Tl24
1Tl20A
1Tl4O

BC264A
BC264B
BC264C
BC264D
BCY87

2N5457
2N5458
2N5458
2N4416
1Tl21

BFXII
BFX.15
BFX36
BFX70

ITl32
1Tl22
1Tl31
ITi22
ITl22

AD5906

2N5906

AD5907

2N5907

2N5908
AD5908
2N5909
AD5909
AD7506/COM/CHIPS IH6116C/D

AD820
AD821
AD822
AD830
AD831

ITl32
1Tl30A
1Tl30A
2N552O
2N5521

BCY88
BCY89
BF244
BF244A
BF244B

1Tl22
1Tl22
2N5486
2N5484
2N5485

BFX78
BFX82
BFX83
BFX99

AD7506/MIUCHIPS
AD7506JD
AD7506JD/883B
AD7506JN
AD7506KD

IH6116M/D
IH6116CJI
IH6116CJI/883B
IH6116CPI
IH6116CJI

AD832
AD833
AD833A
AD835
AD836

2N5522
2N5523
2N5524
2N3954
2N3955

BF244C

BF245
BF245A
BF245B
BF245C

2N5486
2N5486
2N4416
2N4416
2N4416

AD7506KD/883B
AD7506KN
AD7506SD
AD 7506SD/883B
AD7506TD

IH6116CJI/883B
IH6116CPI
IH6116MJI
IH6116MJI/883B
IH6116MJI

AD837
AD838
AD839
AD840
AD841

2N3955
2N3956
2N3957
2N5520
2N5521

BF246
BF246A
BF246B
BF246C
BF247

2N5485
2N5639
2N5638
2N5638
2N4091

BFV85

ITI22

BFY86
BFY91
BFY92
BN209

1T122
ITI22
1Tl22
1Tl22

AD7506TD/883B
AD7507/COM/CHIPS
AD7507/MIUCHIPS
AD7507JD
AD7507JD/8838

IH6116MJI/883B
IH6216C/D
IH6216M/D
IH6216CJI
IH6216CJI/883B

AD842
AHOl26CD
AHOl26D
AHOl26D/883
AHOl29CD

2N5523
DGI26BK
DGI26AK
DG I 26AK/883B
DGI29BK

BF247A
BF247B
BF247C
BF256
BF256A

2N4091
2N4091
2N4091
2N5484
2N5484

BSV22
BSV78
BSV79
BSV80
BSX82

2N4416
2N4856A
2N4857A
2N4858A
2N3822

AD7507JN
AD7507KD
AD7507KD/883B
AD7507KN '
AD7507SD

IH6216CPI
IH6216CJI
IH6216CJI/883B
IH6216CPI
IH6216M/D

AH0129D

DG129AK

AHOI29D/883
AHOl33CD
AHOl33D
AHOl33D/883

DGI29AK/883B
DGI33BK
DGI33AK
DG 133AKl883B

BF256B
BF256C
BF320
BF320A
BF320B

2N4416
2N4416
2N5461
2N5460
2N5461

C21
C2306
C38
C413N
C610

2N5196
2N4338
2N5434
2N4392

AD7507SD/8838
AD7507TD
AD7507TD/883B
AD7520JD

IH6216MJI/8838
IH6216MJI
IH6216MJI/883B
AD7520JD
AD7520JN

AHOl34CD
AHOl34D
AH0134D/883,
AHOl39CD
AHOl39D

DGI34BK
DGI34AK
DG I 34AKl883B
DGI39BK
DGI39AK

BF320C
BF346
BF347
BF348
BF800

2N5462
ITE4392
J201
J310
2N4867

C611
C612
C613
C614 '
C615

2N4221
2N4221
2N4221
2N4220
2N4221

756U

AD3954

A07520JN

··CONSULT FACTORY

AD7531JO

AH0163D

24

BFX71
BFX12

BFY20
BFY81
BFY82
BFY83

BFY84

2N4857

ITl22
2N5397
2N5019
2N5019
1T120A
1T122
1T122
ITI22
1T122
1T122

2N3821

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

C620
C621
C622
C623
C624

2N4220
2N4220
2N4220
2N4220
2N4220

01202
01203
0123AL
D123AP
DI23BP

2N3821
2N4220
0123AL
0123AK
01238K

DG151BP
OGI52AL
DG152AP
OGI52BP
OGI53AL

DG1518K
OGI52AL
DG152AK
OG152BK
DG153Al

OGI88BP
DG189Al
OGI89AP
OGI89BP
OGI90AL

OGI88BK
DG189Al
OGI89AK
OG189BK
OGMI90AL

C625
C650
C651
C652
C653

2N4220
2N4220
2N4220
2N4220
2N4220

DI23SP
0125AL
0125AP
OI25BP
0129Al

0123BJ
0125AL
0125AP
D125BK
O129Al

DG153AP
DG153BP
OGI54AL
OGI54AP
OGI54BP

OGI53AK
OGI53BK
OGI54AL
OG154AK
OGI54BK

OGI90AL
OGI90AP
OGI90AP
DG190BP
OGI90BP

OGI90AL
OGMI90AK
OGI90AK
OGMI9DCJ
OGM190BK

C6690
C6691
C6692
C673
C674

2N4341
2N4341
2N4339
2N4341
2N4341

0129AP
0129BP
01301
01302
01303

D129AK
0129BK
2N4222
2N4220
2N4220

DG161Al
DG161AP
OGI6lBP
DG162Al
OGI62AP

OG161AL
OG161AK
OG161BK
OG162Al
OG162AK

OG190BP
OG191AL
0G191AL
OGI91AP
0G191AP

OG190BK
OGM191Al
OGI91AL
OGM191AK
OGI91AK

C680
C680A
C681
C681A
C682

2N4338
2N4338
2N4338
2N4338
2N4339

01420
01421
01422
02T2218
02T2218A

2N4868
2N3822
2N4869
ITl29
ITI29

OG162BP
DGI63Al
OGI63AP
OGI63BP
OGI64AL

OG162BK
OGI63AL
OGl63AK
OG163BK
OGI64AL

OGI91BP
DG191BP
0G191BP ,
OG200AA
OG200AK

OGMI91CJ
OGM191BK
OG191BK
OG200AA
OG2ooAK

C682A
C683
C683A
C684
C684A

2N4339
2N4339
2N4339
2N4220
2N4220

D2T2219
02T2219A
D2T2904
02T2904A
02T2905

ITl29
ITl29
IT139
ITl39
ITl39

DG164AP
DG164BP
DGl80AA
DG180Al
OGI80AP

DG164AK
OG164BK
OG180AA
OGI80AL
OGl80AK

DG200Al
OG200AP
OG200BA
OG2ooBK
OG200BP

OG200AL
OG200AK
OG200BA
OG200BK
OG200BK

C685
C685A
COO
C81
C84

2N4220
2N4220
2N4338
2N4338
2N4338

02T2905A
02T918
OA102
DA402
DAClO20lCD

1T139
ITI29
2N5196
2N5196
A07520lD

OGI80BA
OGI80BP
OGI81AA
DG181AA
DG181Al

OGl80BA
OGl80BK
DGM181AA
OG181AA
OGM181AL

OG200CJ
OG201AK
OG201AP
OG201BK
OG20lCJ

OG200CJ
OG20lAK
OG20lAK
OG20lBK
OG201CJ

C85
C91
C92
C93
C94

2N4338
2N4858
2N4091
2N4393
2N5457

OAC1020lD
OAC1021lCO
OACI021LD
OAC1022LCO
DAC1022lD

AD7520UD
A07520KO
A07520TD
AD7520JD
A07520SD

DG181Al
OG181AP
OGI81AP
OG181BA
OGI81BA

OG181AL
OGMI81AK
OGI81AK
OGMI81BA
OGI81BA

DG210BP
OG281AA
OG281AP
OG281BA
OG281BP

OG201BK

IHI82CTW
IH182CJO

C94E
C95
C95E
C96E
C97E

2N5457
2N5457
2N5459
2N5484
2N3822

OACI218LCO
OAC1218LCN
OACI218LCN
OAC1219LCO
OACI219LCN

A07541BD
A07541LN
A07541KN
AD7541AD
AD754lJN

OG181BP
OGI81BP
OG181BP
OGI82AA
OGI82AA

OGMI81CJ
OGMI81BK
OG181BK
OGMI82AA
OGI82AA

OG284AP
OG284BP
OG287AA
OG287AP
OG287BA

IHI85MJE
IHI85CJE
IHI88MTW
IHI88MJO
IHl88CTW

C98E
CA308
CC4445
CC4446
CC697

2N3822
LM308
2N5432
2N5434
2N4856

OAC1220LCO
OACI220LD
OACI221LCO
OAC1221LO
OAC1222LCO

AD7521LD
A07521U0
A07521KO
A0752\T0
A0752lJD

DG182Al
OG182AL
OGI82AP
OGI82AP
OGI82BA

DGM182AL
OGI82AL
OGM182AK
OGI82AK
OGMI82BA

OG287BP
OG290AP
OG290BP
OG381AA
OG381AK

IHl88CJO
IH191MJE
IHI9ICJE.
OGM182AA
OGMI82AK

COnoolH
C022015E
CF2386
CF24
CFM 13026

ICMI424C
ICM7051A
2N5458
2N3824
2N4858

OACI222LO
OGI23AL
OGI23AP
OGI23BP
0G125AL

A0752150
OG123AL
OG123AK
OG1238K
OG125AL

OGI82BA
OGI82BP
OGI82BP
OGI82BP
OGI83AL

OGI82BA
OGMI82CJ
OGMI82BK
OGI82BK
OGI83AL

OG381AP
OG381BA
OG381BK
OG381BP
OG381CJ

OGMI82AK
OGM181BA
OGM181BK
OGMI81BK
OGM181CJ

CM600
CM601
CM602
CM603
CM640

2N4092
2N4091
2N4091
2N4091
2N4093

OG125AP
OGI25BP
OGI26AK
OGI26AL
OG126BP

DG12SAK
OGI258K
OGI26AK
OG126AL
OGI26BK

OGI83AP
OGI83BP
OGI84AL
OGI84AL
OGI84AP

DG183AK
OGI83BK
OGM184AL
OGI84AL
OGM184AK

OG384AK
OG384AP
OG384BK
OG384BP
OG384CJ

DGM185AK
OGMI85AK
DGM184BK
OGMI84BK
OGMI84CJ

CM641
CM642
CM643
CM644
CM645

2N4093
2N4093
2N4092
2N4092
2N4092

OGI29AL
OGI29AP
OGI29BP
OG133AL
OG133AP

OG129AL
DG129AK
OGI29BK
OG133AL
OGI33AK

OG I84AP
OGI84BP
OGI84BP
OGI84BP
OGI85AL

OGl84AK
OGM184CJ
OGM184BK
OGl84BK
OGMI85AL

DG387AA
OG387AK
OG387AP
OG387BA
OG387BK

OGMI88AA
OGMI88AK
OGMI88AK
OGMI87BA
OGMI87BK

CM646
CM647
CM650
CM651
CM652

2N4092
2N4091
2N5432
2N5433
2N5432

OGI33BP
OG134AL
OGI34AP
OGI34BP
OGI39AL

OGI33BK
DG134AL
DG134AK
OG134BK
OG139AL

OGI85AL
OGI85AP
0G185AP
OGI85BP
OGI85BP

OGI85AL
OGM185AK
OG185AK
OGM185CJ
OGM185BK

DG387BP
OG390AK
OG390AP
OG390BK
OG390BP

DGM187BK
OGMI91AK
OGMI91AK
OGM190BK
OGMI90BK

CM653
CM697
CM8DO
CM856
CM860

2N5433
2N5433
2N5433
2N5433
2N4868A

OG139AP
OGI39BP
OGI40AL
OGI40AP
OGl40BP

OG139AK
OGI39BK
OGI40AL.
OGI40AK
OGI40BK

OGl858P
OGI86AA
OGI86AL
OGI86AP
OGI86BA

OG185BK
OG186AA
OG186AL
OGI86AK
OGl86BA

OG390CJ
OG503
OG5040AK
OG5040AL
OG5040CJ

OGMI9DCJ
A0503
IH5040MJE
IH5040MFD
IH5040CPE

CMX740
CP640
CP643
CP650
CP651

2N5432
2N4091
2N5434
2N5432
2N5433

OG141AL
OGI41AP
OG141BP
OGI42AL
OG142AP

OG141AL
OG141AK
OG141BK
OG142AL
OGI42AK

OGI86BP
OGI87AA
OGI87AA
OGI87AL
OGI87AL

OGI86BK
OGM187AA
OGI87AA
OGMI87AL
OGI87AL

OG5040CK
OG5041AA
OG5041AK
OG504IAL
OG5041CJ

IH5040CJE
IH5041MTW
IH504IMJE
IH504IMFO
IH5041CPE

CP652
CP653
01101
01102
01103

2N5433
2N5433
2N3821
2N3821
2N4338

OGI42BP
OG143AL
OGI43AP
OG143BP
OGI44AL

OG142BK
OG143AL
OGI43AK
OG143BK
OG144AL

OGl87AP
OGI87AP
OGI87BA
OGI87BA
OGI87BP

OGMI87AK
OGI87AK
OGM187BA
OGI87BA
OGMI87BK

OG5041CK
OG5042AA
OG5042AK
OG5042AL
OG5042CJ

IH5041CJE
IH5042MTW
IH5042MJE
IH5042MFO
IH5Q42CPE

01177
01178
01179
01180
01181

2N3821
2N3821
2N4338
2N3822
2N4338

OGI44AP
DG144BP
OG145AL
OG145AP
OG145BP

OGl44AK
DG144BK
OGI45AL
OGI45AK
OGI45BK

OGI87BP
OGI88AA
OGI88AA
OGI88AL
OG188AL

OGI87BK
OGMI88AA
OGI88AA
OGMI88AL
OGI88AL

OG5042CK
OG5043AK
OG5043AL
OG5043CJ
OG5043CK

IH5042CJE
IH5043MJE
IH5043MFO
IH5043CPE
IH5043CJE

01182
01183
01184
01185
01201

2N4338
2N4341
2N4340
2N4339
2N4224

OGl46AL
DG146AP
OGl46BP
OG151AL
OGI51AP

OGI46AL
OGl46AK
OGI46BK
DG15lAl
OGI51AK

OGl88AP
OGI88AP
OG188AP
OG188BA
OGI88BA

OGMI88BK
OGMI88AK
OGI88AK
OGMI88BA
OGI88BA

OG5044AA
OG5044AK
OG5044AL
OG5044CJ
OG5044CK

IH5044MTW
IH5044MJE
IH5044MFO
IH5044CPE
IH5044CJE

"CONSULT FACTORY

25

:m~~~j~

,' .. ".'
ALTERNATE
SOURCE P,!ODUC.T

'..

..........

""

INTERSIL
EoUIVALE"lT

DG5045AK
OG5045AL

IH5045MJE
IH5045MFD

DG504SCJ
DG5045CK

IH5045CPE
IH5045CJE

DG506J\~

IH6116MJI

DG506BR

IH6116CJI

DG506CJ
OG507AR.
DGS07BR

IH6116CPI
IH6216MJI
IH6216CJI
IH6216CPI

ALTERNATE
SO""I:E. PIIO!)UCT

:

INTERSIL
EQUIVAL:ENT

E212
E230
E231
E232

2N5397
2N5397
2N4867
2N4868
2N4869

E270
E271
£300
E304
E30S

J270
J27\
2NS397
2NS486
2NS464

E308
E309
E310
E311
E312

J308
J309
J310
J310
2NS397

IH6208CPE
DGlllAL
DGlllAK
DGlllBK
2N3821

E400
E401
E402
E410

DN3067A
DN3068A

2N4338

DN3069A

2N3822
2N3821

£412
E413
E414

DG507CJ

DG508AP
DGSOBBP
DG508CJ

DGS09AP
DGS09BP
DGS09CJ

DGMlllAL
DGMlllAP
DGMUlBP
DNJa66A

DN3070A
DN3071A

ON336SA
ON336SB
DN3366A'
DN3366B
DN3367A
DN3367B

IH610BMJE

IH6108CJE
IH6108CPE
lHS20BMJE

IH6208CJE

2N4338

E211

E411

HIl-0506A-2
HII-OS06A-5
HII-0506A-8

IH5116MJI
lHS116UI
IHS116MJI/883B

ESM4445
ESM4446

2NS432
2N5434
2N5432
2NS434

G116AL
G116AP
G116BP

HII-OS09-2
HIl-OS09-S

GII6AK

2N4386
2NS4B5

Gl17Al
GllBAL
G118AP

2N4341

-H1OOA

2N3821
2N3821

2~4222

FEI02

2N4119

2N4339
2N4220

FE102A

2N4119
2N4118
2N4118
2N4092

FEI04
FEI04A

G1l68P

G119AL
GI23AL
Gl23AP
GET54S7

GETS458
GETS4S9
HA2720

2N3821

IH6216MJI

HII-0507A-2
HIl-0507A-5

IH6216MJII883B
IH5216MJI
IH5216UI

2N5460

HIl-OS07A-8
HIl-OS08-2

IHS216MJI/883B
IH6108MJE

HIl-OS08-5

IH6!08CJE
IH6108MJE/883B
tH5108MJ£
IH5108UE
IHSI08MJE/883B

G116AL

IH6208CJE
IH6208MJE/8838
IHS208MJE

HII-OS09A-S

IHS208IJE

G1l7Al
GllBAL

Hll-OS09A-8

HIl-5040-2

IHS208MJE/883B
IHS040MJE

Gl18AK
Gll9AL

HIl-5040-5

IHS040CJE

HII-5040-8

IHS040MJEI883B

G123Al

HIl-504l-2

GI23AK

HIl-5041-5
" HIl-S041-8

IHS041CJE
IHS041MJEI883B

HI 1-5042-2

IH5042MJE
IH5042CJE
IHS142MJE/8838

2NS4S7
2N5458

2N54S9
ICL8021

2N3821

HA7807
HA7809

ITI32
tTI32

HD43871

ICM70S0H
ICM70S0G
3NI63

FE3819
FE4302

2NS484
2NS4S7
2NS4S9
2NS4S8
2N4416

HEP801
HEP802

2N3822

HEP803
HEPFOO21
HEPFlO35

2NSOl9
2NS484
JI76

2N4416

2N4416
2N4339

2NS398
2N5458

J204
2NS4S7
2NS459

FE4303
FE4304

FES245
FES246
FES247

FES4S7
FE5458
FES4S9

2NS486
2N54S7

FE5484

2N5484

FES48S

J107

FE5486

2NS48S
2N5486

JlOS
JI06

FMllOO

El12A

JI12
JI13
JI13

JIll
ICMl115A
J11l

JI12

J204

ICMI1l5B

FF400

2N5457
2N39S4A

HI0-OS07-6

2N5906
2NS906

HIO-OS07 A-6
HI0-OS08-6

2N3954

FMIl02A
FMl103

2NS906
2N39SS

HIO-OS08A-6
HI0-0509-6
HI0-0509A-6

FMllOM
FMll04
FMll04A
FMll05
FMll05A

2NS908

HIO-S040-6

2N39S7

2N5909
2N3954A
ITSOO

HI0-5041-6
HI0-S042·6
HI0-S043-6 .
HI0-S044-6

FMll06
FMII06A

2N3954A
1T500

HIO-S04S-6
H10-5046-6

2N3954
ITSOO
2N39S5

HI0-5047-6
HI0-5049-6
HI0-SOSO-6

IT502
2N3957
ITS03
2N39SS
2NS908

HI0-SOSI-6
HII-0200-2
HII-020D-4
HIl-0200-S
HIl-0200-6

ICM7050U

EI7S
EI76

J175
J176
JI77

FMl107
FMll07A

J201
J202
J203
J204
2NS397

FMll08A

"CONSULT FACTORY

HI0-0387-6
HI0-0390-6
HI0-OS06-6
HI0-OS06A'6

FMllOOA
FMllOIA
FMll02

EI426
El74

Jl74

HI0-0201-6
"10-0381'6
HI0-0384-6

2NS4S8
2NS4S9

JIOS
J106

JI07

HEPF2004
HEPF200S

2NS484

FMll08
FMl109

FMll09A
FMIIIO
FMIIIOA

26

IH6208MJE

G116BK
G116BJ

2N3822
2N3821
2N3821

ICl7667
2NS397

IH6216CJI

HIl-OS09-8
HII-0509A-2

FE204

HDIGl030

DGM190BK

HII-OS07-8

FE300
FE302
FE304

HD43871

DGM188AK

HIl-OS07-2
HIl-OS07-5

2N5486

2N4338

2N3821

DGMI8SAK/883B
OGMI87BK
DGMI88AK/883B
DGMI91AK

2NS486
2N4221
2N4221

2N4869
2N4868

EllO
[Ill
Ell15
ElllA
E112

E204
E210

2N4339
2N4340

HIl-OS08A-8

FE202

E20l

FP4339

Gl1S8J

2N4338

E202
E203

2N3956
2N39S7

GllSBK

DNX2

El77

IT5911

G1l58P

FEI600
FE200

EII3A
E114
EllSI

2N39S7

FM39S8

FM39S6

GlISBP

2N4338

E1l3

FM39S7

2N5454

2N5458

2N4338
2N4220

E109

ITS911

ESM4304

DN3460A
DN34608
ONXI

E"IOS

HII-OS06-8

DGM191AK/8838
IH6116MJI
IH6116CJI
IH6116MJI/883B

HIl-0506-5

HIl-0508-8
HIl-0508A-2
Hll·0508A-S

FEiOO

EI06
El07
El08

HIl-0390-S
HI 1-0390-8
HIl-OS06-2

3NI63
GllSAK

FE0654B

DU4340
ElOO
EI0l

2N3954
2N39S4A
2N39SS
2N39S5A'
2N39S6

FM3954A
FM3955
FM3955A

HI 1-0390-2

FT703
FT704
GllSAP

FE06S4A

El02
El03

FM3954

HIl-0387-8

2N4093
2NS457
2NS4S9

2N4338

DGM182AK/883B
DGM185AK

'DGM184BK

2N39SS
2N39SS
2N39S7
2N39SS
IT5911

2N3955A

ESM4093
ESM4302
ESM4303

2N4220

DGMI82AK
DGMI81BK

2N3954

2N5019

2N4339

DG201AK
DG201BK

DG20lBK
DG20lAK/883B

2N39S5
2N39S5A
ITS911

2N5019
3N161

DN34378
ON3'438A
DN3438B
DN34S8A
DN3458B

DG200AKI.883B

FM1207
FM12Q8

FT3820

ESM4447
ESM4448

INTERSIL
EQUIVALENT

FMI209
FMl210
FM12I1

FT3909

2N4340

2N4338

HIl-0384-S

2N4091
2N4092

DN3437A

DNXl

HIl-0384-S
HIl-0387-2
HIl-0387-S

HIl-0384-2

ESM4091
ESM4092

2N4341
2N4222

DNXB

HIl-0381-2
HIl-0381-5
HIl-0381-8

E431
ESM2S
ESM2SA

2N3686
2N4Q91

DN3436A
DN3436B

DNX9
DS0026
DU4339

2N3954
2N3955A
2N39SS
2N3954
2N3954

FT0654C
FT0654D
H3820

2N4338
2N4338

DNXS
DNX6

HI1~0201-8

J309(X2)
J310(X2)
U401
U401

2N4339
2N4220

ONX3
ONX4

FM1206

HIl-0200-8
HIl-0201·2
HIl-0201-4
HIl·0201-5

FT06S4B

DN3370A
DN3370B

DN34S9B

FM1202
FMI203
FMI204
FMI20S

2N3957
2N5909
2N5196
2N3954
2N3954

ALTERNATE
SOURCE PRODUCT

IT5912

E421
E430

DN3368A
ON3368B
DN3369A'
DN3369B

DN34S9A

FMllll

FMIlllA
FMII12
FM1200
FM1201

INTERSIL
EQUIVALENT

1T5911

E41S
E420

2N4220
2N4091

2N4091
2N4341
2N4221

ALTERNATE
SOURCE PRODUCT

FP4340
FT0654A

2N4338

2N3687

,".

2NS484

HIl-5042-5
HII-5042-8
HIl-S043-2

IHS041MJE

IHS143MJE
IH5143CJE

HIl-S043-S
HII-5043-8

IHS143MJEl883B

HIl-S044-2
HIl-S044-S

IH5144MJE
IHSJ44CJE

HII-5044-8
HII-S045-2
HIl-504S-S

IH5144MJE/883B
IHSI4SMJE

HIl-5045-S

IH514SCJE
IHS14SMJE/8838

HIl~5046-2

IHS046MJE

HIl-5046·S
HIl-S046-8
HIl-5047-S

IHS046CJE
IHS046MJEl8838
IHS047MJE
IHS047CJE

DGM184C/O

Hll·5047~8

IHS047MJEl883B

OGM187C/D

HIl-5049-2
HIl-S049-S
HIl-5049-8
HIl-5050-2

IHS149MJE
tHS149CJE
IH5149MJEt,8838

2NS484

2NS4S9
OG20lCID
OGMI81C/O

DGMI90C/D
IH6116C/O
IH5116C/O
IH6216C/O

HII-S047-2

Hil-SOSO-S

IH51S0MJE
IH51S0CJE

IH5216C/D

HIl-SOSO-8

IH5150MJEJ8838

IH6108C/D
IHSI08CID
IH6208C/D

HIl-SOSI-2
Hil-SOSI-S

IHSISIMJE

HU-5051-8

IHSI51MJE/883B

IHS20BC/D

HI2-0200-2

OG200AA

IH5140C/D
IHS141C/O
IH5142C/O

HI2-0200-4

DG200BA
OG200BA
OG200AAI883B

IHSlS1CJE

IHSI43C/D

HI2-0200-S
HI2-0200-8
HI2-0381-2

IHS144C/D

HI2-0381-S

DGMI81BA

IHS145C/O

OGM18lAA/883B

IHS046C/D

HI2-0381-8
H12-0387-2

IH5047C/D
IH5149CI.D
IH5150C/O

HI2-0387-S
H12-0387-8
HI3-0200-S

OGMI88AAl883B
DG200CJ

IHSOSICID
DG200AK
DG200BK
DG200BK
OG200C/D

HI3-0201-S
HI3-0381-5
H13-0384-S
HI3-0390-S
HI3-0506-5

DG20lCJ
OGMI81CJ
DGMI84CJ
DGMI90CJ
IH6116CPI

OGM182AA

DGMI88AA
DGM1878A

ALTERNATE
SOURCE PROOUCT

INTERalL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE

SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

HI3-0506A-5
HI3-0507-5
HI3-0507A-5
HI3-0508-5
HI3-0508A-5

IH5116CPI
IH6216CPI
IH5216CPI
IH6108CPE
IH5I0SCPE

ITC4023
ITC4024
ITC4025
1TE2453
11E2639

ITI37
ITI37
ITI37
ITI20
ITl20

J109
JI09-18
J110
J110-18
J111

JI06
JI06
JI07
JI07
Jill

J4393
J4416
J4856
J4857
J4858

ITE4393
ITE4416
ITE4856
ITE4857
ITE4858

HI3-0509-5
HI3-0509A-5
10100
10101
IMF3954

IH620BCPE
IH5208CPE
10100
10101
2N3954

ITE2640
ITE2641
11E2642
11£2643
ITE2644

ITI22
11122
ITl20
ITl22
ITl22

Jill-IS
JlllA
Jll1A-18
J112
Jl12-18

Jll1
Jill
Jll1
J112
J112

J4859
J4860
J4861
J4867
J4867A

ITE4859
ITE4860
ITE4861
2N4867
2N4867A

IMF3954A
IMF3955
IMF3955A
IMF3956
IMF3957

2N3954A
2N3955
2N3955A
2N3956
2N39S7

ITE2720
11£2721
ITE2722
11£2903
ITE2913

1T120
ITl22
1Tl20
ITI22
ITI22

JI12A
J112A-18
J113
J113-18
J113A

J112
J112
J113
J113
J113

J4867RR
J4868
J4868A
J4868RR
J4869

2N4867
2N4868
2N4868A
2N4868
2N4869

IMF3958
IMF5911
IMF5912
IMF6485
IT 100

2N3958
IMF5911
IMF5912
IMF6485
1Tl00

ITE2914
11£2915
ITE2916
ITE2917
ITE2918

ITI22
IT120
ITI20
1Tl22
1Tl22

Jl13A-IS
J114
J1401
JI402
JI403

Jl13
2N5555
IT501
IT502
IT503

J4869A
J4869RR
J5103
J5104
J5105

2N4869A
2N4869
2N5484
2N5485
2N5486

ITIOI
ITlO8
ITI09
ITI20
ITI20A

ITIOI
ITE4416
ITE4416
IT120
ITl20A

ITE2919
ITE2920
ITE2936
ITE2937
ITE2972

1Tl20
1Tl20
1Tl20
ITI20
ITl22

J1404
JI405
JI406
JI74
J174-18

IT503
IT504
IT505
JI74
JI74

J5163
K114-18
K210-18
K211-18
K212-18

2N5486
2N5555
2N5397
2N5397
2N5397

ITI21
ITI22
!TI24
ITI26
ITI27

ITl21
\T122
ITI24
1T126
ITI27

ITE2973
11£2974
ITE2975
ITE2976
ITE2977

ITl22
ITI20
ITl20
1Tl20
1Tl20

JI75
J175-18
JI76
J176-18 '
JI77

JI75
JI75
J176
J176
JI77

K300-18
K304-18
K305-18
K308-18
K309-18

2N5397
2N5486
2N5484
J308
J309

ITI28
1Tl29
ITI30
ITI30A
ITI31

IT128
ITl29
!TI30
1Tl30A
ITI31

ITE2978
ITE2979
ITE3066
ITE3067
ITEJ068

1Tl20
1Tl20
2NJ685
2N3686
2N3687

JI77-18
J201
J201-18
J202
J202-18

JI77
J201
J201
J202
J202

K310-18
KE3684
KE3685
KE3686
KEJ687

J310
2NJ684
2N3685
2NJ686
2N3687

IT132
ITl36
ITI37
11138
1T139

1T132
1T136
ITI37
1T13S
ITI39

ITE3347
11E3348
ITE3349
ITE3350
ITE3351

1Tl37
1Tl38
ITl39
1T137
1Tl38

J203
J203-18
J204
J204-18
J210

J203
J203
J204
J204
2N5397

KE3823
KE3970
KE3971
KE3972
KE4091

2N3823
ITE4391
ITE4392
ITE4393
ITE4091

ITl40
1T1700
1T1701
1T1702
ITl750

1T140
1Tl7oo
3NI72
3NI63
IT1750

ITE3680
ITE3800
ITE3802
ITE3804
ITE3806

1Tl20
ITI32
ITI32
1T130
1T132

J211
J212
J230
J231
J232

2N5397
2N5397
2N4867
2N4868
2N4869

KE4092
KE4093
KE4220
KE4221
KE4222

ITE4092
ITE4093
2N5457
2N5459
2N5459

IT2700
IT2701
IT400
IT500
IT500P

3NI65
3NI65
2N4392
IT500
IT500

ITE3807
ITE3808
ITE3809
ITE3810
ITE381\

ITI32
1T132
ITI32
1T130
1Tl30

J270
J270-18
J271
J271-18
J300

J270
J270
J271
J271
2N5397

KE4223
KE4391
KE4392
KE4393
KE4416

J204
ITE4391
ITE4392
ITE4393
ITE4416

IT501
1T501P
lT502
IT502P
IT503

IT501
1T501
IT502
IT502
IT503

ITE3907
ITE3908
ITE4017
ITE4018
ITE4019

1T120
1T120
1T139
1T139
1Tl39

J304
J305
J308
J309
J310

2N5486
2N5484
J308
J309
J310

KE4856
KE4857
KE4858
KE4859
KE4860

ITE4391
ITE4392
ITE4393
ITE4391
ITE4392

IT503P
IT504
IT505
IT550
IT5911

IT503
IT504
IT505
IT550
IT5911

ITE4020
ITE4021
IT£4022
ITE4023
11£4024

1T139
1Tl39
ITI39
1T137
1T137

J315
J316
J317
J3970
J3971

2N5397
U309
U310
ITE4391
ITE4392

KE4861
KE510
KE5103
KE5104
KE5105

ITE4393
ITE4393
J204
ITE4416
ITE4416

IT5912
ITC2972
ITC2973
ITC2974
ITC2975

IT5912
IT122
1T122
ITI20
1T120

ITE4025
ITE4091
ITE4092
ITE4093
IT£41\7

1Tl37
ITE4091
ITE4092
ITE4093
2N41\7

J3972
J401
J402
J403
J404

ITE4393
IT501
IT502
IT503
IT503

KE511
KH5196
KH5197
KH5198
KH5199

ITE4392
2N5196
2N5197
2N5198
2N5199

ITC2976
ITC2977
ITC2978
ITC2979
ITC3347

1T120
1T120
1T120
ITI20
ITl37

ITE41\8
ITE4119
ITE4338
ITE4339
ITE4340

2N4118
2N41\9
2N4338
2N4339
2N4340

J405
J406
J4091
J4092
J4093

IT504
IT505
ITE4091
ITE4092
ITE4093

KS5183
KS5240BOIH
KS5240BOIJ
KS5240BIOH
KS5240BI2H

ICM7269
ICM7245B
ICM7245A
ICM7245D
ICM7245E

ITC3348
ITC3349
ITC3350
ITC3351
ITC3352

ITl38
ITI39
1Tl37
1T138
ITI39

ITE4341
IT£439I
ITE4392
ITE4393
ITE4416

2N4341
ITE4391
ITE4392
ITE4393
11£4416

J410
J41\
J412
J420
J421

IT502
IT503
IT503
IT591\
IT5912

KS5240B20H
KS5240UOIE
LDF603
LDF604
LDF605

ICM724SF
ICM7245U
2N4221
2N4221
2N4221

ITC3800
ITC3802
ITC3804
ITC3806
ITe3807

ITI32
ITI32
1T130
1T132
1T132

ITE4867
ITE4868
ITE4869
JlOO
JIOI

2N4867
2N4868
2N4869
2N5458
2N4338

J4220
J4221
J4222
J4223
J4224

J204
J202
J203
J202
J202

LFl I 201D
LFI\ 201 0/883
LF1\202D
LF 1\ 2020/883
LFl,IS080

IH202MJE
IH202MJE/883B
IH6108MJE

ITC3808
ITC3809
ITC3810
ITC3811
ITC4017

ITl32
1T132
ITI30
1T130
1T139

JI02
JI03
JI05
JI05-18
JI06

2N5457
2N5459
JI05
JI05
JI06

J430
J4302
J4303
J4304
J431

J309(X2)
2N4302
2N5459
2N5458
J310(X2)

LFI\ 5080/883
LF1\5090
LFI\509D/883
LFl320lD
LFl320lN

IH6108MJE/883B
IH6208MJE
IH6208MJE/883B
DG20lBK
DG20lCJ

ITC4018
ITC4019
ITC4020
ITC4021
ITC4022

1T139
ITI39
1T139
ITl39
In39

JI06-18
JI07
J107-18
Jl08
JI08-18

JI06
JI07
J107
J105
JI05

J433
J4338
J4339
J4391
J4392

2N5457
2N5457
2N5457
IT£439I
ITE4392

LF\3202D
LFI3508D
LF13508N
LFl3509D
LF13509N

IH202CJE
IH6108CJE
IH6108CPE
IH6208CJE
IH6208CPE

"CONSULT FACTORY

27

~~gl~~883B

."0,-

•

. A!LTEIINATE
SOURCE PRODUCT·

_.

!.INTERS.L
EQUIVALENT

. .ALTERNjl.TE
.
SOURCE PRODUCT

·"iTER.IL
EQUIVALENT

ALtEIlNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTEIISIL
EQUIVALENT

LH0042
LH210B
LH230B
LM105
LMlOB

LH0042
lH2108
LH2308
LM105
LM.l08

LTCI044
LTC1052
LTC7652
M103
MlO4

ICLl660
ICL7650
ICL7652
3N161
3N161

MDlOO3A
M07003B
M07004
M07007
M07007A

ITI32
1Tl32
1Tl29
1Tl29
ITI29

MEM807A
MEM814
MEM816
MEM817
MEM823

3Nl72
3N161
3Nl72
3N172
MFE823

LMl13
LM114
lM114AH
LM114H

ICL8069
!TI20
1Tl20A
ITI20A
1Tl20.

MlO6
M107
M108
Ml13
Ml14

3N166
3N189
3N191
3N161
3N161

M07007B
M0708
M0708A
M0708B
.M08001

1Tl29
1Tl29
1Tl29
IT129
ITI20

MEM954
MEM954A
MEM954B
MEM955
MEM955A

3N188
3N188
3N188
3N190
3N190

lM115
LMIlSA
LM115AH
LM1l5H
LM194

1T120
1Tl20A
1Tl20A
1Tl20
ITI20A

MIl6
Ml17
M119
M163
M164

MIl6
2N4351
3N161
3N163
3N164

MD8002
M08003
M0918
M0918A
MD918B

!TI20
1Tl22
1T122
ITI22
1Tl22

MEM95.5B
MF510
MFB03
MF818
MFE2000

3N190
2N4092
2N4338
2N4858
2N4416

LM305
LM308
LM394
LM4250
LS3069

LM305
LM308
1Tl20A
LM4250
2N5458

M5001
M511
M511A
M517
M58434P

ICM7269
3Nl72
3N172
3N163
ICM70380

M0982
M0984
MEFl03
MEFlO4
MEF3069

1Tl39
1Tl39
2N5457
2N5459
2N4341

MFE2001
MFE2004
MFE2005
MFE2006
MFE2007

2N4416
2N4093
2N4092
2N4091
2N4860

LS3070
LS3071
LS3458
LS3459
LS3460

2NS4S8
2N5458
J204
J204
J204

M58435P
M58436-001P
M58437-001P
MAl807
MA7809

!CMll15B
ICM7050G
ICM7070L
1Tl32
1Tl32

MEF3070
MEF3458
MEF3459
MEF3460
MEF3684

2N4339
2N4341
2N4339
2N4338
2N3684

MFE2008
MFE2009
MFE2010
MFE2011
MFE2012

2N4859
2N4859
2N4859
2N5433
2NS434

LS3684
LS3685
LS3686
LS3687
LS3819

2N3684
2N3685
2N3686
2N3687
2N5484

MAT-QIAH
MAT-01FH
MAT-01GH
MAT-QIH
MB101

ITI40·
1Tl40
1Tl40
1T140
ICM7245B

MEF3685
MEF3686
MEF3687
MEF3821
MEF3822

2N3685
2N3686
2N3687
2N3821
2N3822

MFE2012
MFE2093
MFE2094
MFE2095
MFE2133

2N5433
2N4338
2N4339
2N4340
2N4860

lS382 I
LS3822
LS3823
LS3921
LS3922

2N54S7
2NS458
2N5458
2N3921
2N3922

MBI03
MBlO5
MBlO7
MB108
MB143

ICM7245E
ICM7245U
ICM72450
ICM7245E
ICM7245A

MEF3823
MEF3954
MEF3955
MEF3956
MEF3957

2N3B23
2N3954
2N3955
2N3956
2N3957

MFE2912
MFE3002
MFE3003
MFE3020
MFE3021

2N5433
3N170
3N164
3N166
3N166

LS3966
LS3967
LS3968
LS3969
LS4220

ITE4416
ITE4416
ITE4416
ITE4416
J204

MB144
MB510
MB511
MB512
MB513

ICM7245F
ICMll15B
ICM7050H
ICM7050H
ICM7050G

MEF3958
MEF4223
MEF4224
MEF4391
MEF4392

2N3958
2N4223
2N4224
ITE4391
ITE4392

MFE4007
MFE4008
MFE4009
MFE4010
MFE4011

2N3686
2N3686
2N3685
2N2608
2N2608

LS4221
LS4222
LS4223
LS4224
LS4338

J202
J203
J202
J202
2N5457

MB521
MB522
MB531
MB533
M8541

ITS9068
ITS9068
ICM7050H
ICM7050H
ICM7052

MEF4393
MEF4416
MEF4856
MEF4857
MEF4858

ITE4393
ITE4416
2N4856
2N4857
2N4858

MFE4012
MFE823
MHW590
MJ41
MJ6

2N2609
ITI700
AD590
ICM1424C
ICM7220

LS4339
LS4340
LS434f
LS4391
LS4392

2NS457
2N5457
2N5458
ITE4391
ITE4392

MB542
M8le
MCC14440
MCC14483
M01l20

ICM7052
ICM7245U
ICM1424C
ICM72lO
1Tl22

MEF4859
MEF4860
MEF4861
MEF5103
MEF5104

2N4859
2N4860
2N4861
ITE4416
ITE4416

MKlO
MM450H
MM451H
MM4520
MM452F

2N4416
MM450H
MM451H
MM452J
MM452F

LS4393
LS4416
LS4856
LS4857
LS4858

ITE4393
ITE4416
ITE4091
ITE4092
1TE4093

M01l21
MOl122
MOl123
MOl129
M01l3Q

1Tl22
ITI22
1Tl39
1Tl29
1Tl39

MEF5105
MEF5245
MEF5246
MEF5247
MEF5248

ITE4416
ITE4416
2N5484
2N5486
2N5486

MM455H
MM550H
MM551H
MM5520
MM552F

MM455H
MM550H
MM5S1H
MM552J
MM552F

LS4859
LS4860
LS4861
LS5103
LS5104

ITE4091
ITE4092
ITE4093
2N5484
2N5485

M02218
M02218A
M02219
M02219A
M02369

1Tl29
1Tl29
tTI29
1Tl29
1Tl29

MEF5284
MEF5285
MEF5286
MEF5561
MEF5S62

2N5484
2N5485
2N5486
U401
U402

MM555H
MMFl
MMF2
MMF3
MMF4

MM555H
2N5197
2N3921
2N5198
2N3922

LS5105
LS5245
LS5246
LS5247
LS5248

2N5486
ITE4416
2N5484
2N5486
2N5486

M02369A
M02369B
M02904
M02904A
M02905

1T129
ITI22
1Tl39
In39
1Tl39

MEF5563
MEM511
MEM511A
MEM511C
MEM517

U403
3N172
3Nl72
3Nl72
3Nl72

MMF5
MMF6
MMT3823
MN6091
MN6092A

2N5199
2N3955A
2N3823
ICM7038B
ICM7038E

LS5358
LS5359
LS5360
LS5361
LS5362

J204
J204
J202
J202
J203

M02905A
M02974
M02975
M02978
M02979

1Tl39
1Tl20
1Tl20
1T120
1Tl20

MEM517A
MEM517B
MEM517C
MEM550
MEM550C

3Nl72
3Nl72
3N172
3N189
3N189

MN6093
MN6252
MP301
MP302
MP303

ICM70S1A
ICM7050G
ITl24
ITl24
ITI24

LS5363
LS5364
LS5391
LS5392
LS5393

J203
J203
2N4867A
2N4868A
2N4869A

M03008
M03250
M03250A
M03251
M03251A

1Tl20
1Tl32
1Tl31
1Tl32
ITl31

MEM550F
MEM551
MEM551C
MEM556
MEM556C

3N189
3N190
3N189
3Nl72
3Nl72

MP310
MP311
MP312
MP313
MP318

2N4045
2N4045
2N4044
1Tl24
ITI20A

LS5394
LS5395

LS5458

2N4869A
2N4869A
2N4)!6.9A
2NS457 .
2N5458

MD3409
M03410
M03467
M03725
M03762

1Tl29
1Tl29
ITl39
1Tl29
ITl39

MEM560
MEM560C
MEM561
MEM561C
MEM562

3N161
3Nl61
3N163
3N163
2N4351

MP350
MP351
MP352
MP358
MP360

ITI32
ITI30
1Tl30
1Tl30A
ITI32

LS5459
LS5484
LS5485
LS5486
LS5556

2N5459
2N5484.
2N5485
2N5486
2N3685

MD4957
MD5DOO
MD5DOOA
MD5DOOB
M07000

1Tl32
1Tl32
1Tl32
1Tl32
1Tl29

MEM562C
MEM563
MEM563C
MEM711
MEM712

2N43S1
2N4351
2N4351
M1l6
M1l6

MP361
MP362
MP3954
MP3954A
MP3955

ITl30A
1Tl30A
2N3954
2N3954A
2N3955

LS5557
LS5558
LS5638
LS5639
LS5640

2N3684
2N3684
2N5638
2N5639
2N5640

M07001
MD7002
M07002A
MD7002B
MD7003

1Tl39
1Tl22
1Tl22
1Tl22
ITl32

MEM712A
MEM713
MEM806
MEM806A
MEM807

M1l6
3N170
3N163
3N163
3Nl72

MP3956
MP3957
MP3958
MP5905
MP5906

2N3956
2N3957
2N3958
2N5905
2N5906

LM114~

tm~~.

"CONSULT FACTORY

..

,

28

INTEASIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

MPS907
MP5908
MPS909
MP5911
MP5912

2N5907
2N5908
2N59a9
2N5911
2N5912

NF4303
NF43a4
NF4445
NF4446
NF4447

2N5459
2N5458
2N5432
2N5433
2N5433

PF511
PF5301
PF5301-1
PF5301-2
PF5301-3

2N5114
2N4118A
2N4117A
2N4118A
2N4118A

SG3D5

5G308
5G4250
SG733
SI7135CPI

LM305
LM308
LM4250
UA733
ICl7135CPI

MP7520JD
MP7520JN
MP7520KD
MP7520KN
MP7520lD

AD7520JD
AD7520JN
AD7520KD
AD7520KN
AD7520lD

NF4448
NF500
NF501
NF506
NF5101

2N5433
2N4224
2N4224
2N4416
2N4867

PU091
PlI092
PlI093
Pl1094
PM308

2N3823
2N3823
2N3823
2N3823
LM308

517660
517661
5JM181BCC
SJMIBIBIC
5JM182BCC

ICL7660
ICL7662
JM38510/11101BCC
JM38510/11101BIC
JM38510/11102BCC

MP7520lN
MP7520SD
MP7520TD
MP7520UO
MP7521JO

AD7520lN
A0752050
AD7520TD
AD7520UD
AD752IJD

NF5102
NF5103
NF511
NF5163
NF520

2N4867
2N4867
2N4860
2N4341
2N3684

PN3684
PN3685
PN3686
PN3687
PN4091

2N3684
2N3685
2N3686
2N3687
ITE4091

5JM182BIC
SJM184B£C
5JM185BEC
5JM187BCC
SJM18781C

JM385101l1I02BIC
JM3851O/ll103BEC
JM38510/11104BEC
JM38510/11105BCC
JM38510/11105BIC

MP752lJN
MP7521KD
MP7521KN
MP75211D
MP7521LN

AD752lJN
AD7521KD
AD7521KN
AD7521LD
AD75211.N

NF521
NF522
NF523
NF530
NF5301

2N3685
2N3686
2N3865
2N4341
2N4118A

PN4092
PN4093
PN4220
PN4221
PN4222

ITE4092
ITE4093
J204
J202
J203

5JM188BCC
5JM188BIC
5JM190BEC
SJM191BEC
SL301AT

JM38510/11106BCC
JM38510/11106BIC
JM38510/11107BEC
JM3851O/ll108BEC
1Tl29

MP7521SD
MP752lTD
MP7521UO
MP7523JN
MP7523KN

AD7521SD
AD7521TD
A07521U0
A07523JN
AD7523KN

NF5301-1
NF5301-2
NFS301-3
NF531
NF532

2N4117A
2N4118A
2N4118A
2N4339
2N4341

PN4223
PN4224
PN4342
PN4360
PN4391

J204
J202
2N5461
2N5460
ITE4391

SL30IBT
5L301CT
5L301ET
SL360C
5L362C

1T129
1Tl29
ITl29
1T129
ITl29

MP7523LN
MP7621AD
MP7621BO
MP762lJN
MP762J KN

AD7523LN
AD7541AD
AD7541BD
AD754IJN
AD7541KN

NF533
NF5457
NF5458
NF5459
NFS484

2N4339
2N5457
2N:;458
2N5459
2N5484

PN4392
PN4416
PN4856
PN4857
PN4858

ITE4392
ITE4416
2N48S6
2N4857
2N4858

5M5011
5M5510
SM5530B
5U2000
5U2020

ICM7050G
ICMll15B
ICM7070P
2N4340
2N3954

MP7621S0
MP7621TD
MP804
MP830
MP831

AD7541SD
AD7541TO
2N5520
2N5520
2N5521

NF5485
NF5486
NF5555
NF5638
NF5639

2N5485
2N5486
2N5484
2N5638
2N5639

PN4859
PN4860
PN4861
PN5033
PTC151

2N4859
2N4860
2N4861
2N5460
2N5484

5U2021
5U2022
SU2023
SU2024
5U2025

2N3954
2N3954
2N3954
2N3954
2N3954

MP832
MP833
MPS35
MP836
MPS37

2N5522
2N5523
2N3954
2N3955
2N3955

NF5640
NF5653
NF5654
NF580
NF581

2N5640
2N4860
2N4861
2N5432
2N5432

PTC152
51424
SA2253
SA2254
SA2255

2N5485
ICM1424C
ITl22
ITl22
1T122

5U2026
5U2027
SU2028
5U2029
5U2029

2N3954
2N3954
2N3954
2NSI97
2N3954

MP838
MP839
MP840
MP841
MP842

2N3956
2N3957
2N5520
2N5521
2N5523

NF582
NF583
NF584
NF585
NF6451

2N5433
2N5434
2N5433
2N4859
U310

SA2644
SA2648
SA2710
SA271!
SA2712

1Tl20
ITI20
1T120
ITI20
1Tl21

5U2030
5U2030
SU2031
5U2031
5U2032

2N3955
2N3954
2N5198
2N3954
2N3954

MPFl02
MPFI03
MPFI04
MPF105
MPFl06

2N5486
2N5457
2N5458
2N5459
2N5485

NF6452
NF6453
NF6454
NKT80111
NKT80112

U310
U310
U310
2N4220
2N4220

SA2713
SA2714
SA271S
5A2716
SA2717

IT121
ITl22
1Tl20
ITl20
ITl21

SU2033
5U2034
5U2034
5U2035
5U2035

2N3954
2N3955
2N3954
2N3955
2N3954

MPFl07
MPFI08
MPFI09
MPFlll
MPF112

2N5486
2N5486
2N5484
2N5458
2N5458

NKT80113
NKT80211
NKT80212
NKT80213
NKT80214

2N3821
2N4339
2N4339
2N4339
2N4339

SA2718
SA2719
SA2720
5A2721
SA2722

ITl22
11120
11121
IT122
IT120

SU2074
5U2075
5U2076
SU20n
5U2077

2N3954
2N3954
2N3954
2N395S
2N3954

MPFl61
MPF208
MPF209
MPF256
MPF4391

2N5398
2N3821
2N3821
ITE4416
ITE4391

NKT80215
NKTS0216
NKTB0421
NKT80422
NKTB0423

2N4339
2N4339
2N4220
2N4220
2N4220

SA2723
SA2724
SA2726
SA2727
SA2738

1T121
ITI22
11122
11122
11120A

5U2078
SU2079
SU2080
5U2081
SU2098

2N3955
2N3955
U404
U404
2N5197

MPF4392
MPF4393
MPF820
MPF970
MPF971

ITE4392
ITE4393
J310
J175
J175

NKT80424
NPCI08
NPC211N
NPC212N
NPC213N

2N4220
2N5484
2N4338
2N4338
2N4338

SA2739
5CL54301
SClS478
50Flool
SDFlD02

1Tl20
ICM1424C
ICM7269
2N5432
2N5433

5U2098A
5U20988
SU2099
5U2099A
5U2365

2N5197
2N5196
2N5197
2N5197
2N3954

MPS5010
M5M5OOl
MSM5011
MSMS977
MTF}Ol

ICLB069
ICM7269
ICM1424C
ICM1424C
2NS484

NPC214N
NPC215N
NPC216N
NPD5564
NPD5565

2N4339
2N4339
2N4339
IT550
IT550

SOFlOD3
SOF500
SDF501
50F502
SOF503

2N5434
2N5520
2N5520
2N5520
2N5520

SU2365A
5U2366
5U2366A
5U2367
5U2367A

2N3954
2N3955
2N3955
2N3955
2N3955

MTFI02
MTFI03
MTFlO4
N05700
ND5701

2N5484
2NS4S7
2N5459
ITl20A
11120.!\

NP05566
NP08301
NP08302
NPD8303
OT3

IT550
2N3954
2N3955
2N3956
2N4338

SDFSQ4
SOF50S
50F506
SDF507
50F508

2N5520
2N5520
2N5520
2N5520
2N5520

5U2368
5U2368A
5U2369
5U2369A
5U2410

2N3956
2N3956
2N3957
2N3957
2N5907

ND5702
NDF9401
NDF9402
NDF9403
NDF9404

1Tl20
IT500
IT501
1T502
IT503

PlOO4
PlOO5
P1027
PI028
P1"029

2N5116
2N5115
2N5267
2N5270
2N5270

50F509
SOF51O
SDF512
SOF513
SDF514

2N5520
2N3954
2N3954
2N3954
2N3954

SU2411
5U2412
5U2652
5U2652M
5U2653

2N5908
2N5909
U401
U401
U401

NOF9405
NDF9406
NDF9407
NDF9408
NDF9409

IT504
IT500
IT501
1T502
IT503

PI069E
Pl086E
PI087E
P1117E
P1118E

2N2609
2N5115
2N5516
2N5640
2N5641

SDF661
50F662
SOF663
SES3819
SFT601

1Tl22
ITl22
11122
2N5484
2N4338

5U2653M
5U2654
SU26S4M
5U2655
5U2655M

U401
U401
U401
U402
U402

NDF9410
NE590
NE592
NF3819
NF4302

IT504
AD590
NE592
2N5484
2N5457

Pll19E
PF510
PF5101
PF5102
PF5103

2N5640
2N5115
2N4867
2N4867
2N4867

SFT602
SFT603
SFT604
5G105
5Gl08

2N4338
2N4339
2N4339
LM105
LMI08

5U2656
5U2656M
5X3819
5X3820
TC803lP

U404
U404
2N5484
2N260B
ICM7038A

"CONSULT FACTORY

29

':LTERNATE
SOURCE PRODUCT

IriTERSIL
EQUIVALENT

ALTERNATE
80URCE PRODUCT

'INTI!R8IL
EQUIVALENT

ALTERNATE
80URCE PRODUCT

INTER81L
I;QUIVALENT

ALTERNATE
80URCE PRODUCT

INTf;RSIL
EQUIVALENT

TC8032P

ICM7038F

T0710

1T122

U112

TC8051P
TC8052P
TC8056PA
TC8057P

ICM7038B
ICM7038E
ICMI115B
ICM70380

T0711
T07l3
TIS14
TlS25

1Tl22
ITl22
2N434O
2N3954

~m

Ul177
U1178

2N2608
2N2608
2N2608
2N4220
2N3821

U285
U290
U291
U295
U296

2N5454
2N5432
2N5434
2N5432
2N5434

TOl00
TOI0l
TOI02
T02CO
T0201

1Tl29
1Tl29
ITl29
1T129
1T129

TIS26
TIS27
TI534
TIS41
TlS42

2N3954
2N3955
2N5486
2N4859
2N4393

U1179
U1180
U1181
U1182
U1277

2N3821
2N4221
2N4220
2N3821
2N3684

U300
U3000
U3001
U3002
U301

2N5114
2N4341
2N4339
2N4338
2N5115

TD202
T02219
T0224
T0225
T0226

ITl29
1T129
ITl22
1Tl22
1T122

TI558
TIS59
TIS68
TlS69
TIS70

2N5484
2N5486
2N3955A
2N3955A
2N3956

U1278
U1279
U1280
U1281
U1282

2N3685
2N3686
2N3684
2N3822
2N4341

U3010
U3011
U3012
U304
U305

2N4341
2N4340
2N4338
U304
U305

T0227
T0228
T0229
T0230
T0231

ITl22
ITI22
ITl22
ITl21
1T121

TIS73
TIS74
TI575
TIS88
TIS88A

ITE4391 '
ITE4392
ITE4393
2N4416
2N4416

U1283
U1284
UI285
U1286
U1287

2N434O
2N4341
2N4220
2N4341
2N4092

U306
U308
U309
U310
U311

U306
U308
U309
U310
U310

T0232
T0233
T0234

TIXS33

T0236

ITl22
1T122
ITl22
ITl22
1T122

TIXS42

2N4392
2N4857
2N4391
2N4859
2N5639

Ul321
U1322
U1323
U1324
U1325

2N4860
2N3822
2N3822
2N3687
2N3686

U312
U314
U315
U316
U317

2N5397
2N5555
2N5397
U309
U310

T0237
T0238
T0239
T0240
T0241

1T122
1Tl22
1T122
1T121
1Tl21

TIXS59
TIXS78
TIXS79
TU82CL
TU82CN

2N5459
2N4341
2N4341
OGM182BA
OGM182CJ

U133
U1420
U1421
U1422
U146

2N2608
2N3821
2N3822
2N3822
2N2608

U320
U321
U322
U328
U329

2N5433
2N5434

T0242
T0243
T0244
T0245
T0246

ITl20A
1Tl20A
1Tl29
1Tl29
1Tl29

TL1821L
TU821N
TU82ML
TU85CJ
TU85CN

DGM182BA

OGM182CJ
OGM182AA
IH5045CJE
IH5045CPE

U147
U148
U149
U168
U1714

2N2608
2N2608
2N2609
2N2609
2N4340

U330
U331
U350
U401
U402

U401
U402

T0247
T0248
TD250
T02905
T0400

1Tl29
1T129
IH20A
In39
11139

TU851J
TU851N
TU85MJ
TUBSCL
TU88CN

IH5045CJE
IH5045CPE
IH5045MJE
IH5042CTW
IH5042CPE

U1715
U182
U183
U1837E
UI84

2N4340
2N4857
2N3824
2N5486
2N5397

U403
U404
U405
U406
U410

U403
U404
U405
U406
2N3955

T0401

TD402
TOSOO
T0501
T0502

ITl39
1Tl39
1Tl39
1T139
1Tl39

TU881L
TUBSIN
TU88ML
TLl91CJ
TU91CN

IH5042CTW
IH5042CPE
IH5042MTW
IH5043CJE
IH5043CPE

U1897E
U1898E
UI899E
UI97
UI98

U1897
U1898
U1899
2N4338
2N4340

U411
U412
U421
U422
U423

2N3956
2N3958
2N5908
2N5908
2N5909

T0509
T0510
T05l!
T0512
T0513

1Tl32
1T132
1T132
1Tl32
1Tl32

TU911J
TU911N
TU91MJ
Tl503
TL592

IH5043CJE
IH5043CPE
IH5043MJE
A0503
NE592

UI99
UI994E
U200
U20\
U202

2N4341
2N4416
2N4861
2N4860
2N4859

U424
U425
U426
U430
U431

2N5908
2N5908
2N5909
J309(X2)
J310(X2)

T0514
T0517
T0518
T0519
T0520

1T132
1T132
1Tl32
1T132
1T139

TlC555
TN4117
TN4117A
TN4118
TN4118A

ICM7555
2N4117
2N4117A
2N4118
2N4118A

U2047E
U221
U222
U231
U232

2N4416
2N4391
2N4391
U231
U232

U440
U441
UA105
UAI08
UA305

IT5911
IT5912
LMI05
LM108
LM305

T0521
T0522
T0523
T0524
T0525

1Tl39
1T139
ITl39
1T139
1T132

TN4119
TN4119A
TN4338
TN4339
TN4340

2N4119
2N4119A
2N4338
2N4339
2N4340

U233
U234
U235
U240
U241

U233
U234
U235
2N5432
2N5433

UA308
UA733
UCl00
UCIIO
UC115

LM308
UA733
2N3684
2N3685
2N434O

T0526
T0527
T0528
T05432
T05433

ITl32
1T131
ITl31
2N5432
2N5433

TN4341
TN5277
TN5278
TP5114
TP5115

2N4341
2N4341
2N4341
2N5114
2N5115

U242
U243
U244
U248
U248A

2N5432
2N5433
2N5433
2N5902
2N5906 '

UCI20
UCI30
UC155
UCI700
UC1764

2N3686
2N3687
2N4416
3N163
3N163

T05434
T0550
T05902
T05902A
T05903

2N5434
1T129
2N5902
2N5902
2N5903

TP5116
TSC426
TSC7106CJL
TSC7106CPl
TSC7106RCPL

2N5116
ICL7667
ICl7l06CJL
ICl7l06CPL
ICL7106RCPL

U249
U249A
U250
U250A
U251

2N5903
2N5907
2N5904
2N5908
2N5905

UC20
UC200
UC201
UC21
UC210

2N3686
2N3824
2N3824
2N3687
2N4416

T05903A
T05904
T05904A
T05905
T05905A

2N5903
2N5904
2N5904
2N5905
2N5905

TSC7107CJL
TSC7107CPL
TSC7107RCPL
TSC7109CPL
TSC7109IJL

ICL7107CJL
ICL7107CPL
,ICL7107RCPL
ICL7109CPL
ICL7109IJL

U251A
U252
U253
,U254
U255

2N5909
IT5911
IT5912
2N4859
2N4860

UC2130 '
UC2132
UC2134
UC2136
UC2138

2N5452
2N5453
2N5454
2N5454
2N5454

T05906
T05906A
T05907
T05907A
T05908

2N5906
2N5906
2N5907
2N5907
2N5908

TSC7109MJL
TSC7116CJL
TSC7116CPL
TSC7117CJL
TSC7117CPL

ICL7109MJL
ICL7116CJL
ICL7116CPL
ICL7117CJL
ICL7117CPL

U256
U257
U257/T0·71
U266
U273

2N4861
U257
U257/TO·71
2N4856
2N4118A

UC2139
UC2147
UC2148
UC2149
UC220

2N3958
2N3958
2N3958
2N3958
2N3822

T0590BA
T05909
T05909A
T05911
T059\1A

2N5908
2N5909
2N5909
IT5911
IT59\1

TSC7126CJL
TSC7126RCPL
TSC7135CJI
TSC7135CPI
TSC7650

ICL7126CJL
ICL7126RCPL
ICL7135CJI
ICL7135CPI
ICL7650

U273A
U274
U274A
U275
U275A

2N4118A
2N4119A
2N4119A
2N4119A
2N4119A

UC240
UC241
UC250
UC251
UC2766

2N4869
2N4869
2N4091
2N4392
3N166

T05912
TD5912A
T0700
T0701
T0709

IT5912
IT5912
1T122
ITl22
ITI22

TSC7660
TSC9491
TI·590
U110
U\lI

ICL7660
ICL8069
A0590
2N2608
2N2608

U280
U281
U282
U283
U284

2N5452
2N5453
2N5453
2N5453
2N5454

UC300
UC310
UC320
UC330
UC340

2N2608
2N2607
2N2607
2N2607
2N2607

TD235

"CONSULT FACTORY

TlXS35
TIXS36
TIXS41

30

2~5433

..
....
..

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

UC40
UC400
UC401
UC41
UC410

2N2608
2""5270
2N5116
2N2608
2N5268

UC420
UC450
UC451
UC588
UC703

2N5267
2N5114
2N5116
2N4416
2N4220

UC704
UC705
UC707
UC714
LJC714E

2"'14220
2N4224
2N4860
2N3822
2N4341

UC734
UC734E
UC751
UC752
UC753

2N4416
2N4416
2N4340
2N4340
2N4341

UC754
UC755
UC756
UC805
UC807

2N4340
2N4341
2N4340
2N5270
2N5115

UC814
UC851
UC853
UC854
UC855

2N5270
2N2608
2N2608
2N2608
2N2609

UCN-4111M
UCN-4112M
UCN-4113M
UHP-503
UPDl952P

lCM7038C
ICM7051A
ICM70388
AD503
ICM7220MFA

UPD1962C
UPD1963C
UPD815C
UPD816C
UPD820C

ICM7050G
ICM7050
ICM7038E
ICM70388
ICMl115B

UPD833G
UTlOO

ICM7223

unOI

ALTERNATE
SOURCE PRODUCT

INTERSIL
.EQUIVALENT

ALTERNATE
SOURCE PRODUCT

2N5397

UXC2910
VCRION

2N5397
1T126
2N4869

VCRllN
VCR12N
VCR13N
VCR20N
VCR2N

VNRllN
2N3958
2N3958
2N4341
VCR2N

VCR3P
VCR4N
VCR5P
VCR6P
VCR7N

VCR2P
VCR4N
VCR5P
VCR6P
VCR7N

VF28
VF811
YF8l5
VFW40
VFW40A

2N4392
2N4858
2N4858
lT122
1T120

YR-8069
W245A
W2458
W245C
W300

ICl8069
ITE4416
IT£4416
ITE4416
2N5398

W300A
W300B
W300C
W300D
WG-8038

2N5397
2N5397
2N5397
2N5398
ICl8038

WK5457
WK5458
WK5459
XR8038
ZD140

2N5457
2N5458
2N5459
ICl8038
1Tl29

ZDT41
ZDT42
ZOT44
ZDT45

IT129
1Tl29
1Tl29
1Tl29

"CONSULT FACTORY

31

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

Section 1 - Selector Guides

2.DISCRETES
Switches-Junction FET
N Channel
PART
NUMBER PACKAGE

rOS(ON)
n
Max

Vp
v
Min

IGSS

BVGSS

ID(OFF)

loSS

tap

Crss

ClsS

Max

pA
Max

V
Min

pA
Max

rnA
Min

ns
Max

pF
Max

pF
Max

-4.0
-2.0

8.0
-10.0
-5.0

-100
-250
-250

-50
-40
-40

250
250

50
25

150
75

6
25
25

High Isolation
High Isolation
High Isolation

-0.5

-3.0

-250

-40

250

5

30

50
90
180

3
6
6
6

25

High Isolation

-10.0
-10.0
-7.0
-7.0
-5.0
-5.0

-200
-40
-200
40
-200
40

-40
-50
-40
-50
-40
-50

200
200
200
200
200
200

30
30
15
15
8
8

65
65
95
95
140
140

5
5
5

5

16
16
16
16
16
16

High
High
High
High
High
High

55
75
100

3.5
3.5
3.5

14
14
14

High Isolation
High Isolation
High Isolation

34
60
120
34
60
120

8
8
8
8
8
8

18
18
18
18
18
18

High
High
High
High
High
High

Max

COMMENTS

2N3824
2N3970
2N3971
2N3972

TO-72
TO-18
TO-18
TO-18

250
30
60
100

" 2N4091
2N4091A
" 2N4092
2N4092A
" 2N4093
2N4093A

TO-18
TO-18
TO-18
TO-18
TO-18
TO-18

30
30
50
50
80
80

-5.0
-5.0
-2.0
-2.0
-1.0
-1.0

2N4391
2N4392
2N4393

TO-18
TO-18
TO-18

30
60
100

-4.0
-2.0
-0.5

-10.0
-5.0
-3.0

-100
-100
-100

-40
-40
-40

100
100
100

50
25
5

2N4856
2N4857
2N4858
2N4859
2N4880
2N4861

TO-18
TO-18
TO-18
TO-18
TO-18
TO-18

25
40
60
25
40
60

-4.0
-2.0
-0.8
-4.0
-2.0
-0.8

-10.0
-6.0
-4.0
-10.0
-6.0
-4.0

-250
-250
-250
-250
-250
-250

-40
-40
-40
-30
-30
-30

250
250
250
250
250
250

50
20.
8
50
20

2N4978

TO-18

20

-2.0

-8.0

-500

-30

500

15

55

8

35

Low rOS(ON)

2N5432
2N5433
2N5434

TO-52
TO-52
TO-52

5
7
10

-4.0
-3.0
-1.0

-10.0
-9.0
-4.0

-200
-200
-200

-25
-25
-25

200
200
200

150
100
30

41
41
41

15
15
15

30
30
30

Low rOS(ON)
Low rOS(ON)
Low rOS(ON)

2N5555

T0-92

150

-10.0

-lnA

-25

10nA

15

35

1.2

5

Low Cost

2N5638
2N5639
2N5640
2N5653
2N5654

T0-92
TO-92
T0-92
TO-92
TO-92

30
60
100
50
100

-12.0
-8.0
-6.0
-12.0
-8.0

-lnA
-lnA
-lnA
-lnA
-lnA

-30
-30
-30
-30
-30

lnA
50
lnA25
lnA
5
lnA
40
lnA
15

24
44
63
24
44

4
4
4
3.5
3.5

10
10
10
10
10

Low
Low
Low
Low
Low

ITE4091
ITE4092
iTE4093

TO-92
TO-92
TO-92

30
50
80

-5.0
-2.0
-1.0

-10.0
-7.0
-5.0

-200
-200
-200

-40
-40
-40

200
200
200

30
15
8

65
95
140

5
5
5

16
16
16

Low Cost
Low Cost
Low Cost

ITE4391
ITE4392
ITE4393

TO-92
TO-92
TO-92

30
60
100

-4.0
-2.0
-0.5

-10.0
-5.0
-3.0

-100
-100
-100

-40
-40
-40

100
100
100

50
25
5

55
75
100

3.5
3.5
3.5

14
14
14

Low Cost
Low Cost
Low Cost

Jl05
Jl06
Jl07
Jl08
Jl09
Jll0
Jlll
Jl12
Jl13
Jl14

TO-92
TO-92
TO-92
TO-92
TO-92
TO-92
TO-92
TO-92
TO-92
TO-92

3
6
8
8
12
18
30
50
100
150

-4.5
-2.0
-0.5
-3.0
-2.0
-0.5
-3.0
-1.0
-0.5

-10.0
-6.0
-4.5
-10.0
-6.0
-4.0
-10.0
-5.0
-3.0
-10.0

-3nA
-3nA
-3nA
-3nA
-3nA
-3nA
-lnA
-lnA
-lnA
-lnA

-25
-25
-25
-25
-25
-25
-35
-35
-35
-25

3nA
3nA
3nA
3nA
3nA
3nA
lnA
lnA
lnA
lnA

500
200
100
80
40
10
20
5
2
15

"
"
"
"
"
"

"Also available as JAN/JANTX & JANTXV
""Most TO-92's afe available lead formed to a TO-18 or TO-5 configuration

1-1

8

150
75
30
100
80
100
80

150
75
30

20
20
20
41
41
41
48
48
48
26

5
5

Isolation
Isolation
Isolation
Isolation
Isolation
Isolation

Isolation
Isolation
Isolation
Isolation
Isolation
Isolation

Cost
Cost
Cost
Cost
Cost

Lowest rOS(ON)
Lowest rOS(ON)
Lowest rOS(ON)
Low Cost
Low Cost
Low Cost
Lowest Cost
Lowest Cost
Lowest Cost
Low Cost

2. DISCRETES
Switches .... Junction FET
N Channel
rDS(ON)
PART
NUMBER

PACKAGE

Il
Max

vp.

IGSS'

V

pA

BVGSS

V

ID(017Fl

loss
rnA
Min

tap.
ns
Max

Cras

Clss

pF
Max

pF
Max

15
8

65
95
140

5
5
5

16
16
16

Low Cost
Low Cost
Low Cost

41
41
41

15
15
15

30

Lowest rOS(ON)
Lowest rOS(ON)
Lowest rOS(ON)

8
8

30
30

8

30

Low Cost
Low Cost
Low Cost

5
5
5

16
16
16

Low Cost
Low Cost
Low Cost

Min

Max

Max.

Min

pA
Max

-10.0
-7.0
-5.0

-200
-200
-200

-40
-40
-40

200
200
200

30

PN4091
PN4092
PN4093

10-92
TO-92
TO-92

50
80

-5.0
-2.0
-1.0

PN5432
PN5433
PN5434

TO-92
TO-92
TO-92

5
7
10

-4.0
-3.0
-1.0

-10.0
-9.0
-4.0

-200
-200
-200

-25
-25
-25

200
200
200

150
100
30

U200
U201
U202

TO-18
TO-18
TO-18

150
75
50

-0.5
-1.5
-3.5

-3.0
-5.0
-10.0

-InA
-1nA
-1nA

-30
-30
-30

InA
InA
1nA

3
15

U1897
UI898
UI899

TO-92
TO-92
TO-92

30

-5.0
-2.0
-1.0

-10.0
-7.0
-5.0

-400
-400

-40
-40
-40

200
200
200

30

50
80

-400

'Also available as JAN/JANTX & JANTXV
"Most TO-92's are available lead formed to a TO'18 or TO-5 configuration

1-2

30
30
15

8

Max

25
75
150
65
95
140

30

30

COMMENTS

DlL

2. DISCRETES
Switches-Junction FET
P Channel
PART
NUMBER

PACKAGE

rDS(ON)
fI
Max

Vp

IGSS

BVGSS

'D(OFF)

V
Min

Max

pA
Max

V
Min

pA
Max

loss
mA
Min Max

5.0
5.0
9.5

15nA
15nA
15nA

30
30
30

-2nA
-2nA
-2.5nA

-3-30
-15-30
-15-SO

9.5
5.5

1.2nA
1.2nA

25
25

-1.2nA
-1.2nA

-10
-2

12.0
7.0

2nA
2nA

30
30

-10nA
-10nA

-10

2N3382
2N3384
2N3386

TO·72
TO·72
TO·72

300
lSO

1.0
4.0
4.0

2N3993
2N3994

TO·72
TO·72

lSO
300

4.0
1.0

2NS018
2NS019

TO·18
TO·18

75
150

• 2N5114
• 2N5115
• 2N5116

TO·18
TO·18
TO·18

75
100
150

5.0
3.0
1.0

10.0
6.0
4.0

500
500
500

30
30
30

IT100
IT10l

TO-18
TO-18

75

60

2.0
4.0

4.5
10.0

200
200

J174
J175
J176
Jl77

TO-92
TO-92
TO-92
TO-92

125
2SO
300

5.0
3.0
1.0
0.8

10.0
6.0
4.0
2.25

PN5114
PN5115
PN5116

TO-92
TO-92
TO-92

75
100
lSO

5.0
3.0
1.0

U304
U305
U306

TO-18
TO-18
TO-18

85

5.0
3.0
1.0

180

85

110
175

tap
ns
Max

Crs•
pF
Max

C,••
Max

COMMENTS

16 typ Low rOS(ON)
16 typ Low rOS(ON)
16 typ Low rOS(ON)
4.5
4.5

16
16

-5

100
215

10
10

45
45

Low rOS(ON)
Low rOS(ON)

-500
-500

-30 -90
-15 -60
-5 -25

37
66
102

7
7
7

25
25
25

Low rOS(ON)
Low rDS(ON)
Low rOS(ON)

35
35

-100
-100

-20

12
12

35
35

TIL Compatible
TIL Compatible

lnA
lnA
lnA
lnA

30
30
30
30

-lnA
-lnA
-lnA
-lnA

-20 -100
-7 -60

45

-2 -25
-1.5 -20

90

10.0
6.0
4.0

500

30
30
30

-500
-500
-500

-30 -90
-15 -60
-5 -25

37
68
102

7
7
7

25
25
25

Low Cost
Low Cost
Low Cost

10.0
6.0
4.0

500

30
30
30

-500
-500
-500

-30 -90
-15 -60
-5 -25

70

105

7
7
7

27
27
27

High Off Isolation
High Off Isolation
High Offlsoiation

500

500
500
500

-500

• Also available as JAN/JANTX & JANTXV
"Most TO-92's are available lead formed to a TO-18 or TO-5 configuration

1-3

-10

22

Low Cost
Low Cost
Low Cost
TIL Compatible

70

140

·.·.B··~.·.<.··
.. ··>·.·."'.~.··.··.·:n.';0.,;;;;:"
;. :.:..·."·.·.......
; Stnb

'•
.
~.

2. DISCRETES
Switches and Amplifiers MOSFET
N·Channel
BVoss loss

9,.

loss

rO~ON)

PACKAGE

VGS(TH)
V
Min'

Max

ID(ON)
mA
Min

2N4351

TO-72

1.0

5.0

25

10nA

10

1000

300

3

High Input Z

3N170
3N171

TO·72
TO-72

1.0
1.5

2.0
3.0

25
25

10nA
10nA

10
10

1000
1000

200
200

10
10

. High Input Z
High Input Z

1T1750

TO-72

0.5

3.0

25

10nA

10

3000

50

10

M116
M117

TO-72
TO-72

1.0
1.0

5.0
5.0

30
30

lanA
10nA

100

PARJ
NUMBER

'Max

V
Min

pA
Max

pA
Max

"mho
Min'

ID(ON)
mA.·.
Max

COMMENTS

Low rOS(ON)
Diode Protected
High Input Z

lOQ
100

P·Channel
Generally used where max. isolation between signal.source and logic drive is required: switch "On" resistance varies with signal amplitude.

PART
NUMBER' PACKAGE

9,.

VGS(TH)
V
Min

BVoss
V
Min

loss

MIIIX

pA
Max

IGSS
pA
Max

I'mho
Min

rDS(ON)
0
Max

IIl(ON)
mA
Min

IIl(ON)
mA
Max

COMMENTS

2N4352·

TO-72

-1.0

-5.0

-25

-10nA

10

1000

600

":3

High Input Z

3N155
3N15SA
3N157
3N157A

TO-72
T0-72
TO-72
TO·72

-1.5
-l.S
-1.5
-1.5

-3.2
-3.2

-lnA
-250
-lnA
-250

10
10
10
10

1000
1000
1000
1000

600
300

-5

-5

-3.2

-35
-35
-35
-50

High
High
High
High

3N161
3Nl63
3N164

TO-72
TO-72
TO-72

-1.5
-2.0
-2.0

-5.0
-5.0
-5.0

-25
-40
-30

-10nA
-200
400

-100
-10
10

3500
2000
1000

3N172
3N173

TO-72
TO-72

-2.0
-2.0

-5.0
-5.0

-40
-30

-400

-200

-10nA

-500

IT1700
IT1701

T0-72
T0-72 .

-2.0
-2.0

-5.0
-5.0

-40
-40

200
200

100

-3.2

2000
2000

'-5
-5
-40

Input Z
Input Z
Input Z
Input Z

-3

-120
-30
-30

Diode Protected
High Input Z
High Input Z

250
350

-5
-S

-30
-30

Diode Protected
Diode Protected

400

-2
-2

250
300

-5

400

High Input Z
Diode Protected

Low Leakage Diodes
PART
NUMBER
10100
10101

PACKAGE

'R@ 1V
(PA)
Typ

IR@ 10 V, 125°C
(nA)
Max

BVR@ 1~
(V)
Min

TO-7S
TO-71

0.1
0.1

10
10

30
30

Note 1_ Used to protect the inputs of MOSFETs such as 3NI63, while maintaining input leakage < LM108

ISlAS
(pA Max)

SLEW
RATE
~/,..)

-

GBW
(MHz)

COMPEN·
SATION

VSUPPLY

EXT
INT

:20
:1:18
:1:9

~Mlx)

TEMPERATURE
RANGE
(OC)

Bipolar, Super·Beta
Bipolar, Super·Beta
CMOS, Selectable la

2.0
7.5
2,5,15

2000
50

1.6

1.0
1.0
1.4

•. ICL8007M
• ICL8007C

JFET Input Op-Amp
JFET Inpul Op-Amp

20
50

20
50

6
6

1.0
1.0

INT
INT

:18
:1:18

LH2108
LH2308
ICL7621

Bipolar, Super·Beta
Bipolar, Super·Beta
CMOS, Fixed la

2.0
7.5
2,5,15

2000
7000
50

--

EXT
EXT

0.16

1.0
1.0
0.48

INT

:1:20
:1:18
:1:9

ICL8043M
ICL8043C

JFET Input Op-Amp
JFET Input Op-Amp

20
50

20
50

6
6

1.0
1.0

INT
INT

:18
:1:18

ICL7631

CMOS, Selectable la

5,10,20

50

1.6

1.4

INT

:1:9

1

ICL7641

CMOS, Fixed la

5,10,20

50

1.6

1.4

INT

:1:9

~

VOUT

VSUPPLY

~Min)

~Max)

Vos
(mVMax)

ISlAS
(nA Max)

AVOL
(dB Typ)

TEMPRATURE
RANGE
(OC)

:26
:26

:32
:32

:12
:12

:18
:18

250
250
250

:26
:26

:32
:32
:32
:32

3.0
6.0
3.0
6.0
3.0
6.0
3.0
6.0

100
100
100
100
100
100
100
100

-55 to +125
-25 to +85
-55 to +125
-2510 +85
-55 to +125
-2510 +85
-55 to +125
-25 to +85

..

.!l
·c

g

T
j

Iq

VOS·
(mV MIX)

LM308
ICL7611

..~

AI
.;.fJil

DESCRIPTION

7000

EXT

-55 10 +125

~ to +70
to +70
-55 to +125
-55 10 +125
o to +70

1

-55 to +125
a to +70

1

Oto +70
-55 to +125
-55 to +125
Oto +70
Oto +70
-55 to +125

010 +70
-55 10 +125

Operational Amplifiers: High Output Current

TYPE

!

~

%

(i)

ICH8510M
iCH85101
ICH8515M
ICH85151
ICHB520M
ICHB5021
ICHB530M
ICHB5301

DESCRIPTION

Hybrid Amplifier
Hybrid Amplifier
Hybrid Amplifier
Hybrid Amplifier
Hybrid Amplifier
Hybrid Amplifier
Hybrid Amplifier
Hybrid Amplifier

lOUT
(A Min)
1.0
1.0
1.5
1.25
2.0
2.0
2.7
2.7

:25
:25
1-15

50

250
500
250

500

4. AMPLIFIERS

Operational Amplifiers: Low/Ultra.lowlnputOff$et Voltage

TYPE

e\":i

ICL7650C
ICL76501
ICL7850M

·.·1m

......

."

".

",'

I

DESCRIPTION

Vos
",VMilx)

AVos/AT
"'Vl°C)
(Max)

AVos/At
(ilVlmoiIIh)

(TyP)

(pA Max)

IBIAS

Gaw
(MHz)

VSUPPLY
(V Max)

TEMPERATURE
RANGE
(0C)

::t5
::t5
:1:5

::to.05
::to.05
::to.05

100
100
100

10
10
10

2.0
2.0
2.0

::t9
::t9
::t9

o to +70
-25 to +85
-55 to +125

:1:5
::t5

100
100

30
30
7000

2.0
2.0
1.0
1.0

::t9
::t9
:1:20
::t18

o to +70
-25 to +85
-55 to +125
o to +70

2000
7000

1.0
1.0

::t2O
::t2O

-55 to +125
010 +70

ICL7652C
ICL78521
LM108A
LM308A

CMOS, Chopper·
stabilized
CMOS, Chopperstabilized
Low-noise 7850C
Low-noise 76501
Bipolar, Super·Beta
Bipolar, Super·Beta

500
500

::to.05
::to.05
5.0
5.0

LH2108A
LH2308A

Bipolar, Super·Beta
Bipolar, Super·Beta

500
500

5.0
5.0

-

2000

Operational Amplifiers: Low Input Bias Current
TYPE

DESCRIPTION

IBIAS
(PA Max)

los

GaW
(MHz)

COM PEN·
SATION

VSUPPLY
(V Max)

TEMPERATURE
RANGE
(0C)

(PA Typ)

Vos '
(mV Max)

0.5

2,5,15

0.5
0.5

2,5,15

1.4
1.4

INT
INT

:1:9
::t9

2,5,15

1.4

INT

::t9

0.5

2,5,15

0.48

0.5

2,5,15

0.48

EXT
EXT

::t9

CMOS, Input Protected

50
50
50
,50
50

ICL8007M

JFET Input Op-Amp

20

0.5

20

1.0

INT

:1:18

-55 to +125

ICL8007AM

JFET Inpul, Low Bias

4.0

0.2

1.0

INT

::t18

-55 to +125

ICL8007C

JFET Input Op-Amp

50

0.5

1.0

INT

:l:1j!

010 +70

ICL.8007AC

JFET Input, Low Bias

4.0

0.2

1.0

INT

:1:18

Oto +70

ICH8500
ICH8500A

PMOS Input

0.1

0.7

INT

:1:18

-25 to +85

PMOS Input, Low Bias

0.01

30
50
30
50
50

0.7

INT

:1:18

-25 to +85

'I

ICL7621

CMOS, Fixed Ie

INT

:1:9

0.5

2,5,15
2',5,15

0.48

CMOS, Offset Null Pins

50
50

0.5

ICl7622

0.48

INT

:1:9

Oto +70
-55 to +125

ICL8043M

JFET Inpul Op-Amp

20

0.5

20

1.0

INT

:1:18

-55 to +125

ICL8043C

,JFET Input Op-Amp

50

0.5

50

1.0

INT

:1:18

"a!

ICl7631

CMOS, 'Selectable Ie

5,10,20

1.4

INT

:1:9

CMOS, Selectable Ie

50
50

0.5

ICl7632

0.5

5,10,20

1.4

NONE

:1:9

ICl7641

CMOS, Fixed Ie

5,10,20

1.4

INT

:1:9

CMOS, Fixed Ie

50
50

0.5

ICl7642

0.5

5,10,20

0.044

INT

:1:9

"

ID

fij

,

,

IC,L7611

CMOS, Selectable Ie

ICL7612

CMOS, Extended CMVR

ICL.7613

CMOS, Input Protected

ICL7614

CMOS, Fixed Ie

ICL7615

-

}

.» +~
,-55 to :125

:1:9

','

. "'.",

.".'
III

g

I'

1-16

}

o to +70
}

010 +70
-55 to !125

}

010 +70
-55 to !125

4. AMPLIFrERS

Commutating Auto-Zero (CAl) Instrumentation Amplifiers

TYPE

DESCRIPnON

Vos
{j.V MaX)

'Nos/aT
{j.V/"C)
(Max)

aVos/at
(nV/month)
(Typ)

IBIAS
(pA Max)

SIGNAL
BANDWIDTH
(Hz Max)

TEMPERATURE
RANGE

AVOL
(dB Typ)

(0C)

o

ICL7605C
ICL76051
ICL7605M

CMOS, Compensated
CMOS, Compensated
CMOS, Compensated

5.0
5.0
5.0

0.2
0.2
0.2

40
40
40

1500
1500
1500

10
10
10

105
105
105

to +70
-25 to +85
-55 to +125

ICL7606C
ICL7!l(l61
ICL7606M

CMOS, Uncomp911sated
CMOS, Uncompensated
CMOS, Uncompensated

5.0
5.0
5.0

0.2
0.2
0.2

40
40
40

1500
1500
1500

10
10
10

105
105
105

Oto +70
-25 to +85
-55 to +125

Logl Antilog Amplifiers

TYPE

DESCRIPnON

ICL8048BC
ICl.8048CC

Logarithmic Amplifier,
1V/Decade Output

ICL8049BC
ICL8049CC

. Antilog Ar:npllfler
1V/Decade Input

Vos
(mVMax)

aVOAJtlaT
(mV/"C)
(Typ)

DYNAMIC
RANGE
(dB)

30
60

25
50

0.8
0.8

120
120

±14
±14

±18
±18

10
25

25
50

0.38
0.55

60
60

±14
±14

±18
±18

ABSOLUTE
ERROR
(mVMax)

OUTPUT
SWING
(V Typ)

TEMPERATURE
VSUPPLY
(V Max)

RANGE
(OC)
Oto.+70

o to +70
o to +70
o to +70

Power Transistot Drive Amplifiers

TYPE

ICLB063M
ICL8063C

DESCRIPTION

Bipolar Monolithic
Driver Amplifier

lOUT
(mAMin)

VOUT
(V Min)

Vos
(mVMax)

AYOL
(VN)

+50/-25
+40/-20

±27V

50
75

6
6

IBIAS
Il

Differential
Inputs
~P-Compatlble,

ADC0804

t:

;

ICL711!>J/K

Differential
Inputs

DIGITAL
OUTPUT
FORMAT
8-Blt
Binary
8-Blt
Binary
8-Blt
Binary

~P-Compatlble,

816 Bits

High Speed
Converter

Ao Byte
Enable

INPUT
CONVERSION VOLTAGE OVERALL
SPEED (PS)
RANGE ACCURACY

-

114
(Max)

Oto +5.0V

114
(Max)

Oto +5.0V

-

114
(Max)

Oto +5.0V

-

40
(Max)

0.01% (J)
Oto +5.0V 0.006%(1<)
Oto -5.0V

1-21

TOTAL
. ERROR

GAIN
TEMP.
COEFF.

±'!J LSB

-

(Unadjusted) .
±Y. LSB
(Adjusted)

-

±H.SB
(Unadjusted)

-

+1 LSB

SUPPLY
VSUPPLY/
ISUPPLY

TEMP
RANGE
(0e)

+5V (Typ)
2.5mA(Max)

Oto +70
-40 to +85
-55 to +125

+5V (Typ)
2.5mA(Max)

o to +70
-40 to +85
-55 to +125

+5V (Typ)
2.5mA(Max)

o to +70
-40 to +85
-55 to +125

4 ppml"C +5V (Typ)
5 mA(Typ)

o to

+70

6. DATA ACQUISITION
Dlgltal·ta-Analog Converters (CMOS)
TYPE

I

AD7523

SPECIAL
FEATURES

Blnaryl
pp-Compatlble,
Offset
Low Power
Multiplying CAC Binary
~P-Compatlble,

SUPPLY

GAIN

VSUPPLY

LlNERITY

ISUPPLY

1.5% (Max)

10 ppm/oC
2 ppm/°C

+1SV (Typ)
'1oopA (Max)

o to +70
-25 to +85
-55 to +125

0.2% (J,A,S)
0.1% (I<,B,1)
0.05% (L,C,U)

0.3% (Typ)

10 ppm/°C
2 ppm/°C

+15V(Typ)
2mA(Max)

Oto +70
-25 10 +85
-55 to +125

:l:VREF A
10Kn
(Max)

0.2% (J,A,S)
0.1% (K,B,1)
0.05% (L,C,U)

0.3% (Typ)

10ppm/°C
2 ppm/oC

+15V (Typ)
2 mA(Max)

010 +70
-2510 +85
-55 to +125

:l:VREF A
10Kn
(Max)

0.2% (J,A,S)
0.1% (I<,B,1)
0.05% (L,C,U)

1.4% (Max)

10 ppm/°C
2 ppm/°C

+15V (Typ)
2mA(Max)

Oto +70
-25 to +85
-55 to +125

:l:VREF A
10Kn
(Max)

0.2% (J,A,S)
0.1% (I<,B,1)
0.05% (L,C,U)

0.3% (Typ)

10 ppm/"C
+15V (Typ)
2 ppm/°C , 2mA(Ma~)

010 +70
-25 to +85
-55 10 +125

0.2% (JA,S)
0.1% (K,B,1)
0.05% (L,C,U)

0.3% (Typ)

(Typ)

:l:VREF A
10Kn
(Max)

10 ppm/°C
2 ppm/°C

+15V (Typ)
2mA(Max)

010 +70
-2510 +85
-55 to +125

1,.s
(Max)

:l:VREF A
10Kn
(Max)

0.02% (J,A,S)
O.OW. (K,B,1)
0.01 % (L,C,U)

0.3% (Max)

'2 ppm/°C

+15V (Typ)
2mA(Max)

Oto'+70
-25 to +85
-55 to +125

3,.s
(Max)

:l:VREF A
7KO
(Max)

0.1 % (J,A,S) '0.02% (J)
0.006% (I<,B,1) 0.012% (K)
0.003% (l.,C,U) 0.006% (L)'

5 ppm/°C
1 ppm/°C

+5V (Typ)
0.5 mA (Max)

010 +70
-25 to +85
-55 to +125

200 ns
(Max)

500 ns

AD7530

Blnaryl
Same as '7520
But no leakage Offset
/leed thru specs Binary

500 ns

AD7533

"P-Compatlble,
Lowesl c;osl
1O-blt DAC

Binaryl
Offset
Binary

600 ns

~P-Compatlble,

500 ns

500 ns

8, 9, 10 Bit Lin.
Mulliplylng CAC

Ii

SfABILITY

SETTLING
nME
(TO
0.050/0 FS)

Binaryl
Offset
Binary

i AD7520

~.

DIGITAL
INPUT
FORMAT

i
•••••

Multiplying CAC

Blnaryl
Offsel
Binary

I

AD7531

Same as '7521
But nO leakage
/feed Ihru specs

Binaryl
Offsel
Binary

AD7541

pp-Compatlble,
High performanee CAC

Blnaryl
Offsel
Binary

AD7521

,~,

if AD7134

•••

:~:::

8, 9, 10 BII Lin.

Binaryl
"P-Compatlble,
Low power
2's
Multiplying CAC Complement

(Typ)

(Typ)

(Typ)

(Typ)

OUTPUT
VOLTAGE
CURRENT

NON LIN·
EARITY

GAIN
ERROR

:l:VREF A
10KO
(Max)

0.2% (J,A,S)
0.1% (I<,B,1)
0.05% (L,C,U)

:l:VREF A
10Kn
(Max}

Quad Current Switches For D/A Conversion (Singles or Matched Pairs)
TYPE

DESCRIPTION

ICL8018A

High precision current

ICL8019A

switches for use In
summing D/A converters

ICL8020A

ABSOLUTE
ERROR
(% Max)

ERROR
TEMPCO.
(pPM/"C Max)

:1:0.01
:1:0.10

:1:5
:1:25
:1:50

:1:1.00

1-22

VSUPPLY
(V Max)

ISUPPLY
(rnA Max)

:1:20-

10

:1:25

:1:20
10

:1:20

TEMPERATURE
RANGE
(0C)

~

010 +70

-55 to +125

TEMP
RANGE
(0C)

7. TIMER/COUNTER CIRCUITS
Timer/Counters With Display Drivers
DISPLAY
LED

FUNCTIONS
UNIT
COUNT

LCD VF

UNIVERSAL
COUNTERS

NUMBER
OF
DIGITS

TYPICAL APPLICATIONS
AND COMMENTS

TYPE

ICM7217
ICM7217A

•

ICM72178

•

• • •

•

•

• • •

•••

• •••
•••

2

•••

• • ••

2

•••

•

•

Industrial control: preset/predetermin·
ing counters, sequencers, on/off delay
timers, batch counters. Presets and
loads compare register from
thumbwheel switches

2

!i!
ICM7217C.
••
• ••
••••
2
Q.~---+~~~rr++++++~~~~~~~-------------i
=i
ICM7227
•
••
• •. •
••••
2
Microprocessor compatible interface.
ICM7227A
ICM7227B

I'.

ICM7~7C

•
•
•

ICM7224
ICM7224A

• •

•
•

•
•

•

•

• •••

•••••••
• ••••••

•
•••
•

••

•

2
2

•• ••

15

•

15

••

Industrial control: presel/predetermin.
ing counters, sequencers, onloff delay
timers, batch counters. Presets and
loads compare register from a
microprocessor

2

•

i..~•.t-'C_M_7_225
_ _-+_.+++_t-+-+-'-.+.:...r-t.++-+-++.+.+.+.++-+-+-_15_+.-I
•
!i ICM7225A.
•
•
• • • •
15
ICM7236

•

• ••

•

ICM7236A

•

•

•

•

• •

••••

15.

t------t-t-+-+-+-+-t-t-t-l-l-ll-+-+-+++-+--+-t-t-ll---t-l
!~.

•

ICM7249



CRYSTAL
FREQUENCY

PULSE
WIDTH

OTHER OUTPUTS/COMMENTS

ICM7213

t Pulse/Min

2-4

100

125,1000

4.19 MHz

1 PulseJSec, 2048, 1024, 34.133, 16 Hz

ICM7207A

0.5 Hz

4-5.5

260

1000,
0.391

5.24288 MHz

5 Hz, 1600 Hz (Note 1)

ICM7213

1 Hz

2-4

100

7.B

4.19 MHz

1 Pulse/Min, 2048, 1024, 34.133, 16 Hz

ICM7207A

5 Hz

4-5.5

260

100,0.391

5.24288 MHz

0.5,1600 Hz

ICM7207

5 Hz

4-5.5

260

100,0.312

6.5536 MHz

50 Hz, 1260 Hz

ICM7213

16 Hz

2-4

100

Sq. Wave

4.19 MHz

1 Pulse/Min, 2048, 1024, 34.133, 1 Hz

ICM7207

50Hz

4-5.5 '

260

20,0.312

6.5536 MHz

.5 Hz, 1260 Hz

ICM7213
ICM7213
ICM7207A
ICM7207

1000 Hz
1024 Hz
1260 Hz
1600 Hz

2-4
2-4
4-5.5
4-5.5

100
100
260
260

Sq. Wave
Sq. Wave
Sq. Wave
Sq. Wave

4.096 MHz
4.19 MHz
5.24288 MHz
6.5536 Mhz

2000, 2000 Pulses/Min

1 Pulse/Min, 2048, 34.133, 16, 1 Hz
0.5,5 Hz
5,50 Hz

ICM7213

204s Hz.

2-4

100

Sq. Wave

4.19 MHz

1 Pulse/Min, 1024,34.133,16, 1 Hz

ICM7209

25OkHz- '
10 MHZ

4.s.5.5

11,000

Sq. Wave

1-10 MHz

Note.:
1. Oscillator/controller for frequency counter.
2. Two buffered outputs"":Crystal Frequency and

+

B output. Drives up to 5 TTL loads.

1-24

(Note 2)

8. DISPLAY DRIVER
.

.OF
CHARACTERS
OR DIGITS

'

DISPLAY
TYPE

.

FEATURES AND
COMMENTS

INTERFACE

FONT

.D~D[6

TYPE

ICM7211
ICM7211A
ICM7211M
IGM7211AM

4
4
4
4

ICM7212
ICM7212A
ICM7212M
ICM7212AM

4
4
4
4

ICM7218A
ICM7218B
ICM7218C
ICM721BD
ICM7218E

8 8
8 8
8 8

ICM7231A
ICM7231B
ICM7231C

8 16
8 i6
8 16
10 20
10 20
10 20

ICM7232A
ICM7232B
ICM7232C
ICM7233A
ICM7233B

••
••

B 8
B 8

• ••
•
•

4
4

3
3
3
3
3
3
3
3
3

5
5
4
4
4
4

••

8

ICM7243A
ICM72438

8

•
••
•
•
••
•

•
• ••
••
•
•
••
•• ••
••
••

3

ICM7234A
ICM7234B
ICM7235
ICM7235A
ICM7235M
ICM7235AM

•
••
•

14

SO

7&
10

14

SO

16

200
200

1000
1000
200
200

•
•• •
•
•
•
•

••

•

1000

1000

•
•

•• •
•

•

•
•• • • ••
•• • • ••
• •
• •

550
550
500
500
500
500

Drives Conventional LCD Displays. Includes RC
Oscillator, Divider Chain, latches, Interface and LCD
Drivers. Evaluation Kit Available
Drives Common Anode LED Displays. 28 Current
Controlled Outputs. Includes latches, Interface and
Brightness 'Control. Evaluation Kit Available.
3 Decode Formats Drives UP to 64 Independent LED's .
Includes 8x8 Memory, Multiplexed LED Drivers,
Decoders, Interface and control. Applications Include
Bar Graphs.
'
B Digits, 16 Annunciators on COM 3, Hexadecimal

500
500
.350

B Digits, 16 Annunciators on COM 3, Code B

.350
.350

10 Digits, 20 AnnunCiators on COM 3, Code B

500
500
.350
.350

1000
1000
200
200

• •
• •

-

B Digits, 16 Annunicators on COM 1 + 3, Code B
10 Digits, 20 Annunciators on COM 3, Hexadecimal
10 Digits, 20 Annunciators on COM 1 + 3, Code B
4 Alphanumeric Characters. Evaluation Kit Available
4 Alphanumeric Characters. Full·Width Numbers
5 Alphanumeric Characters. Half·Width Numbers
5 Alphanumeric Characters. Full·Width Numbers
Drives 30 Volt Vacuum Fluorescent Displays Directly.
Includes Latch/Decoder ~P Interface or 4·Bit Inpul.
Hexadecimal or Code B Format Available.

250

8 Alphanumeric Characters + Decimal PI. can be Daisy
Chained or Cascaded. Evaluation Kit Available.

400

lxSO Ch. Dot Matrix LCD Controller' and Row Driver.
Use with ICM7281.

400

2x40 Ch. Dot Matrix LCD Controller and Row Driver.
Use with ICM7281.
Column Driver for use with ICM7280 or ICM7283.

'New Product

1-25

U~UI6

9. MICROCONTROLLERS, MICROPERIPHERALS, MEMORY

Microcontrollers, Microperipherals, Memory
Microcontrollers

8048/80C48 Family Compatible

6
6
6
6

2X the memory of IM80C48
Same as IM80C48 without ROM
Same as IM80C49 without ROM

Microprocessor Peripherals -

INTERNAL
MEMORY

fe ".
MHz

DESCRIPTION

(0C)

ROM

RAM

lK x 8
2Kx8
None
None

64x8
128 x 8
64 x 8
128 x8

PL,
PL,
PI.;
PL,

JL
JL
JL
JL

!

DESCRIPTION

(MHz)
Max

PACKAGE

loMj!Wo~·.".

I'P·Compatible Real·Time Clock, Binary Time
Format, Micropower Standby Operation (2,.A @ 2.8V)

4.19

PG,JG

IM6402
IM6402·1
IM6402A

CMOS' Industry Standard Compatible UART
High·Speed Version of IM6402
10VOperating Version of IM6402

1.0
2.0
4.0

PL
PL, JL
PL,JL'

2.46
3.58
6.0

PL
PL, JL
PL,JL

IM6403
IM6403·1
IM6403A

Like Corresponding IM6402
Device but with On·board Crystal
, Oscillator and Baud Rate Generator

1< 1_C43~"·'

0 - +70
-40 -

+85

CMOS I/O Expander for BOC4B/49 Microcompu.ters

TEMPERATURE
RANGE (OC)
-40 -

PG,JG

.......

IM4702/12

}

See also Display Drivers, Counters, AID, and D/A Converters.

fC

TYPE

TEMPERATURE
' RANGE

PACKAGE

Baud Rale Generator'

3.58

+85

}

-40,... +85

}

-40- +85

}

0- +70

PE,JE

-55 -

-55 -

+125

+125

-40- +85
-40- +85

CMOS EPROMs
ORGANIZATlONI
TYPE

MAX ACCESS
TIME(ns)

Vcc
(VI

IgcMAX(mA)
PERATING

Icc MAX (,.AI
STANDBY

PACKAGE

1024 x 4
IM66531
IM6653M
1M6853-11
IM6853A1
IM6853AM

550
600
450
300
350

5
5
5
10
10

6
6
6
12
12

140
140
140
140
140

JG
JG
JG
JG
JG

-40 -

512x 8
1M68541
IM6854M
IM66M-l I
IM6854AI
IM6854AM

550
600
450
300
350

5
5
5
10
10

6
6
6
12
12

140
140
140
140
140

JG
JG
JG
JG
JG

-40 -

* New Product

1-26

TEMPERATURE
RANGE (OC)

+85
+125
-40 - +85
,..40 - +85
-55 ~ +125

-55 -

-55 -40 -40 -

-55 -

+85
+125
+85
+85
+125

Section 2 -

Discretes

2N2607-2N2609
2N2609JAN
P-Channel JFET
General Purpose Amplifier
APPLICATIONS
•
•
•

CHIP

TOPOGR~PHY

Low-Level Choppers
Data Switches
Commutators

~

Z

(lcr2N2807,8)

5510

~

!

D(2)

l ~FUUR
,-_+-:II
.0017

~1)~~~T

PIN CONFIGURATION
TO·18

.0025 x'OO25

.0035

.0035

1-<0'"

:=

~~~

z

~

NOTE: SUBSTRATE
IS GATE

.013

5503

o

liE':}:,:

S

G,C

PC000111

f----, .016--1

NOTE: ~~i~ATE
CT005811

ABSOLUTE MAXIMUM RATINGS

ORDERING INFORMATION*
TO-18

WAFER

DICE

2N2607/W

2N2607/D

2N2608

2N2608/W

2N2608/D

2N2609

2N2609/W

2N2609/D

2N2607

2N2609JAN

-

(TA = 25°C unless otherwise noted)
Gate-Source Voltage ........... ,.,. , ..... , ................... 30V
Gate-Drain Voltage ............. , ... , .... , .. , ... ,............. 30V
Gate Current ......................... ,." ....... , ......... ", 50mA
Storage Temperature Range ............ -65°C to +200°C
Operating Temperature Range ... "",. -55°C to + 175°C
Lead Temperature (Soldering. 10sec) ..... , .. , ..... +30QoC
Power Dissipation ............. ,."" .. ", ... , ...... " ..... 300mW
Derate above 25°C.""."."""."".""". 2mW/oC

-

'When ordering waler/dice reler to Section 10, page 10-1,

ELECTRICAL CHARACTERISTICS

(@ 25°C unless otherwise noted)
2N2607

SYMBOL

PARAMETER

2N2609
UNIT

MIN

MAX

MIN

MAX

MIN

MAX

vGS - 30V, vos = 0

3

10

30

nA

VGS= 5V, VOS=O, TA=l50°C

3

10

30

p.A

IGSSR

Gate Reverse Current

BVGSS
Vp

Gate·Orain Breakdown Voltage

IG = 1p.A, VOS - 0

Gate·Source Pinch·Off Voltage

VOS=-5V, 10= -1p.A

30

lOSS

Drain Current at Zero Gate
Voltage

VOs= -5V, VGS=O

gl.

Small·Signal Common·SourCe
Forward Transconductance

VOS = -5V, VGS = 0, I = 1kHz

CiS&'

Common·Source Input
CapaCitance

VOS = -5V, VGS = lV, 1= lMHz
(Note I)

Noise Figure (Note 1)

VOS· -5V,
VGS=O,
I = 1kHz

NF

2N2608

TEST CONDITIONS

I RG= 10MU
I RG=lMU

NOTE 1: For design relerence only, not 100% tested.

2-1
Note: All typical values have been guaranteed by characteriZation and are not tested:

30

iJ

30

1

4

1

4

1

4

V

-0.30

-1.50

-0.90

-4.50

-2

-10

rnA

330

1000
10

2500

JJS

17

30

3

3

pF

3
dB

... 2N'3884.,2N3687 .

iz

i
zft

N~Char1nel

"JPET ,,' ,"
Low Noise Amplifier

FEATURES

APPLICATIONS

•
•
•

•
•
•
•

Low Noise
High Input Impedance
Low Capacitance

PIN CONFIGURATION

Low Level Choppers
Data Switches
Multiplexers
Low Noise Amplifiers

CHIP TOPOGRAPHY
5010

TO-72

0(2)

.0013 FULLR
.0017

~1) ~T
•

.0025 x .0025
.0035

~

,0035

:=~

-.l.NOTE: SUBSTRATE
IS GATE

.013

PC000211

CTOOO321

ORDERING INFORM'ATION*
TO-72

,WAFER

DICE

2N3684

2N3684/W

2N3684/D

2N3685

2N3685/W

2N3685/D

2N3686

2N3686/W

2N3686/D

2N3687

2N3687/W

2N36871D

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Gate-Source or Gate-Drain Voltage .................... -sOV
Gate Current , ................................................ 50mA
Storage Temperature Range ............ -65°C to +200°C
Operating Temperature Range ......... -55°C to + 175°C
Lead Temperature (Soidering, 10sec) .............. + 300°C
Power Dissipation .......................................... 300mW
Derate above 25°C .............. ; ........... 2.0mW I"C

'When ordering wafer/dice refer to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS (2S0C unless otherwise noted)
2N3684
SYMBOL

PARAMETER

BVGSS

Gate to Source Breakdown Voltage

Vos = 0, IG = 1.0pA

-50

Vp

Pinch-Off Voltage

VOS = 20V, 10 = O.OOlpA

-2.0

IGSS

Total,'Gate Leakage Current

IVlsl

Forward Transadmitlance

Gos

Common Source Output
Conductance

Ciss

Common

Source Input
CapaCitance

MAX

MIN

-5.0

-1.0

Vos =20V, VGS = 0
f= 1kHz

MIN

_3.5

-0.6

2N3687

MAX

MIN

-2.0

-0.3

-50
-0.1

-0,5
YGS = 0, VOS = 20V

MAX

-50
-0.1

' VGS = -30V, VOS = 0

I,TA = 150'C
Saturation CuO'ent, Drain·te-Source

2N3686

UNIT
MIN

"loss

2N3685

TEST CONDITIONS
-50
-0.1

-0,5

MAX
V

-1.2
-0.1

-0.5

nA

-0.5

pA

2:5

7.5

1.0

3.0

0.4

1.2

0.1

0.5

mA

2000

3000

1500

2500

1000

,2000

500

1500

iJS

50

25

10

5

iJS

4.0

4.0'

4.0

4.0

pF

VOS = 20V, VGS = 0
f=IMHz (Note 1)

1.2

1.2

1.2

1.2

pF
ohms

Crss

Common Source Short Circuit
Reverse Transfer Capacitance

rOS(on)

On Resistance

VOS = 0, VGS = 0

600

800

1200

2400

NF

Noise Figure (Note 1)

f = 100Hz, RG = 10M(/.
NBW = 6Hz, VOS = 10V,
VGS=OV

0.5

0.5

0.5

0.5

NOTE 1: For design reference only, not 100% tested.

2-2
Note: All typical values have been guaranteed by characterization, and are not tested.

dB

,

2N3810/A, 2N3811/A
Dual Matched PNP
General Purpose Amplifier
PIN CONFIGURATION

~

Z

CHIP TOPOGRAPHY

Co»
CD

......

4501
T0-78

~

f-033-1

~
.023

I

......L
EMITIEA
BASE

c,

B,

BASE .0030 )(

.0040

COLLECTOR

.0044
CTOOO4tl

ORDERING INFORMATION*
2N3810

WAFER

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Emitter-Base Voltage (Note 1) ............................. ~5V
Collector-Base or Collector-Emitter Voltage
(Note 1) .................................. , ................. -60V
Collector Current (Note 1) ................................ 50mA
Storage Temperature Range ....... , .... -'65°C to + 175°C
Operating Temperature Range ......... -55°C to + 175°C
Lead Temperature (Soldering, 10sec) .............. + 300°C
ONE SIDE
BOTH SIDES

DICE

2N3810/W

2N3810/D

2N3811/W

2N3811/D

2N3810A
2N3811

.0040

TYP 2 PLACES

PCOOO31 I

TO-78

.0030

TYP 2 PLACES

.0035 x .0034

.0045

E,

E"'TTER .0029 ,.JlO~
.0039
.0039
TVP 2 PLACES

2N3811A
'When ordering waferI dice refer to Section 10, page 10-1.

Power Dissipation .................... .
Derate above 25°C .............. ..

500mW
3.3mW/oC

600mW
4.0mW/oC

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: 25°C Ambient Temperature unless otherwise noted

SYMBOL

PARAMETER

2N3810/A

2N3811/A

MIN

MIN

UNIT

TEST CONDITIONS
MAX

BVceo

Collector-Base Breakdown Voltage

Ic = -10pA, IE = 0

-60

-60

BVCEO

Collector-Emitter Breakdown Voltage
(Note 2)

IC = -10mA, 18 = 0

-60

-60

BVEeO

Emitter-Base Breakdown Voltage

IE = -10pA, IC = 0

-5

-5

lC(off)

Collector Cutoff Current
ITA=+l50'C

IE(off)

hFE

Emitter Cutoff Current

Vce = -50V, IE = 0

Static Forward Current

VCE= -5V

Transfer Ratio
ITA = -55'C
VeE(sa!)

Base-Emitter Saturation Voltage

VCE(sa!)

Collector-Emitter Saturation Voltage

IC = -10pA

100

IC= -l00pA to -lmA

150

Ic = 10mA (Note 2)

125

IC = 100pA

75

V

-10

-10

nA

-10

-10

pA

-20

nA

-20

VeE = 4V, Ic = 0

MAX

225
450

300

900

250
150

VCE = -5V

le= -10pA

-0.7

IC= -100pA

Ie = -100pA

-O.B

-O.B

-0.2

-0.2

Ie = -10pA, Ic = -100pA

(Note 2)

le= -100pA, IC= -lmA

hie

Input Impedance (Note 4)

VCE = -10V

tit.

Forward Current Transfer Ratio (Note 4)

Ic= -lmA

hre

Reverse Voltage Transfer Ratio (Note 4)

f= 1kHz

hoe

Output Admittance (Note 4)

-0.7

-0.25

-0.25

3

30

10

40

150

600

300

900

0.25
5

2-3
Note: All typical values have been guaranteed by characterization and are not tested.

60

V

kn

0.25

5

60

,",S

2

:~

aN3,81o/A,:2N38111A'

=ELECTRICAL
I

,-..
C

o

=
I

CHARACTERISTICS (CONT.)
2N3810/A
,"A~AMETER

SYMBOL

2N3811/A
UNIT

TEST CONDITIONS
MIN MAX MIN MAX

Ihlel

Magnitude 01 small signal

Ilc= -lmA, f= looMHz

VCE= -5V

current gain (Note 4)

I

Ie = - SOOM,

Cobo

Output Capacitance (Note 4)

VCS = -SV, IE * 0, f= lMHz

Cibo

Input Capacitance (Note 4)

VCS

hFE1/hFE2

DC Current Gain Ratio

IVSE1-VSE2 I

Base-Emitter Voltage
Differential

IA devices

= -O.SV,

f = 30MHz

VCE = '-SV, IC - loollA

NF

Base-Emitter Voltage
Differential Gradienl

I A devices

Spot Noise Figure

5

1

4

4

8

0.9

1.0

0.9

8
1.0

0.95

1.0

0.95

1.0
-S

-2.5

-2.5

-3

-3

,-1.5

-l.S

10
5

10
5

VCE - -10V, Ic = -loollA, RG = 3ka,
f - 100Hz, Noise Bandwidth - 20Hz

7

4

VCE - -10V, Ic = -1001lA, RG = 3Ka,
f = 1kHz, Noise Bandwidth = 200kHz

3

1.5

VCE - -10V, Ic = -1001lA, RG - 3ka

2,5

1.5

3.5

2.5

VCE = -SV

I A devices

,n

1

-S

IC= loollA

.6.VSE1- VSE2

5

1

Ie = 0, f = 1MHz

IC = 10pA to, lOrnA

I A devices

1

VeE = -5, Ic

= 100""

f = 10kHz, Noise Bandwidth - 2kHz

(Note 4)

VCE = -10V, Ic = -1001lA, RG = 3ka,
Noise Bandwidth = 15.7kHz (Note 3)

NOTES: 1. Per transIstor.
2. Pulse,width" 3OOjAS, duty cycle" 2.0%.
3.. 3dB down at 10Hz and 10kHz:
4, For design reference only, not 100% tested.

2-4
Note: All typical values have ~n guaranteed by characterization and are not tested. '

pF

mV

pNrc

dB

2N3821, 2N3822,

JAN, JTX, JTXV

N-Channel JFET
High Frequency Amplifier
FEATURES

•
•

CHIP TOPOGRAPHY

Low Capacitance
Up to 6500l-ls Transconductance

2N3821

5010

j

PIN CONFIGURATION

.0013 FULL R
.0011

~1),,~~T

T0-72

.0025 x .0025
00350035

1--

~~~
:::

~

NOTE: SUBSTRATE
IS GATE

.013

5003
2N3822

o

T~._._
1
_

G,C
CTOO6501

.0025

ORDERING INFORMATION*
TO·72

WAFER

1--.016 4

.0025

NOTE: SUBSTRATE
IS GATE
CTOOO521

DICE

2N3821

2N3821/W

2N3821/0

ABSOLUTE MAXIMUM RATINGS

2N3822

2N3822/W

2N3822/0

(TA = 25'C unless otherwise noted)
Gate-Source Voltage ....................................... -50V
Gate-Drain Voltage ......................................... -50V
Gate Current ................................................ , 10mA
Storage Temperature Range ............ -65'C to + 200'C
Operating Temperature Range ......... -55'C to + 175'C
Lead Temperature (Soldering. 10sec) .............. + 300'C
Power Dissipation .. , ............... , .. , ...... ", ... " ..... 300mW
Derate above 25·C .......................... 2,OmW /"C

'When ordering waferI dice refer to Section 10, page 10-1.
tadd JAN, JTX, JTXV to basic part number to specify these devices.

ELECTRICAL CHARACTERISTICS

(25'C unless otherwise noted)
2N3821

SYMBOL

PARAMETER

UNIT
MIN

Gate Reverse Current

VGS = -30V, vos = 0

BVGSS

ITA=150·C
Gate-Source Breakdown Voltage
Gate-Source Cutoff Voltage

IG=-IjJ.A, VOs-O
VOS = 15V, 10 = 0.5nA

-50

VGS(off)

VOS = 15V, 10 = 50jJ.A

-0.5

IGSS

VGS

Gate-Source Voltage

losS

Saturation Drain Current (Note I)

2N3822

TEST CONDITIONS
MAX

2-5
Note: All typical values have been guaranteed by characterization. and are not tested.

0.5

MAX

-0.1

-0.1

-O.t

-0.1

nA
jJ.A

-50

-4
-2

Vos = 15V, 10 = 200jJ.A
Vos = 15V, VGS = 0

MIN

2.5

-6
V
-I

-4

2

10

mA

2Na821,'2N;t8~2, ~AN,

JTX, JTXV

,',

2N3821
SYMBOL

PARAMETER

MIN

MAX

4500

3000

6500

I-1kHz

1500

IYlsl

Common-Source Forward
Transadmittance (Note 2)

1= 100MHz

1500

gos

Common-Source Output
Conductance (Note 1)

C;•• '

Common-Source Input
Capacitance (Note 2)

Crss

Common-Source Reverse Transler
Capacitance (Note 2)

NF

Noise Figure (Note 2)

NOTES:

Vos

s

15V, VGS = 0

1= 1kHz

3000
10

20

6

,'6

3

3

5

5

dB

200

200

nV
-y11z

1. These parameters are measured dunng a 2ms Interval lOOms after DC power IS applied.
2. For design reference only, not 100% tested.

2-6

pF

1= 10Hz

VOS = 15V, VGS = 0,
BW= 5Hz

Note: All typical values have been guaranteed by characterization and 'are not tested.

"

/.IS

1-1MHz
VOS - f5V, VGS = 0,
Rgen - 1meg, BW = 5Hz

"

UNIT,
MAX

Common-Source Forward
Transconductance (Note 1)

Equivalent Input Noise Voltage
(Npte 2)

"

MIN
~

en

2M3822

TEST CONDITIONS

2N3823,JAN, JTX, JTXV

N-Channel JFET
High Frequency Amplifier
FEATURES
•
•
•

CHIP TOPOGRAPHY

Low Noise
Low Capacitance
Transductance Up to 6500MS

.0035 FUlLR

5000

.0025

~- r

T \,

PIN CONFIGURATION

~~~~ T

.017

~

TO-72

,0035 x .0035

:0025 -:oo2s

.0066
NOTE: SUBSTRATE
~0062~
IS GATE

.017

CT00061I

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Gate-Source or Gate-Drain Voltage .................... -30V
. Gate Current ................................................. 10mA
Storage Temperature Range ............ -65°C to +200°C
Operating Temperature Range ......... -55°C to + 175°C
Lead Temperature (Soldering, 10sec) .............. + 300°C
Power Dissipation ......................................... 300mW
Derate above 25°C .......................... 2.0mW 1°C

PCOOO201

ORDERING INFORMATION*

'When ordering wafer/dice refer to Section 10, page 10-1.
tadd JAN,JTX,JTXV to basic part number to specify these devices

ELECTRICAL CHARACTERISTICS
SYMBOL

(25°C unless otherwise noted)

PARAMETER

TEST CONDITIONS

IGSS

Gate Reverse Current

BVGSS

Gate-Source Breakdown Voltage

IG

VGS(off)

Gate-Source Cutoff Voltage

VOS = 15V, 10 = 0.5nA

VGS

Gate,Source Voltage

VOS = 15V, 10 = 400pA
VOS

I

TA=150·C

MIN

VGS = -20V, Vos = 0

= lpA,

UNIT

-0.5

nA

-0.5

pA

-8

V

-30

VOS = 0

= 15V,

MAX

-t.O

=0

-7.5

loSS

Saturation Drain .Current

4

20

Sts

Common-Source Forward
Transconductance (Note 1)

f= 1kHz

3,500

6,500

IVlsl

Common-Source Forward
Transadmittance (Note 2)

f = 100MHz

3,200

gos

Common-Source Output
Transconductance (Note 1)

f= 1kHz

gis.

Common-Source Input
Conductance (Note 2)

goss

Common-Source Output
Conductance (Note 2)

C;ss

Common-Source Input
CapaCitance (Note 2)

Crss

Common-Source Reverse
Transfer Capacitance (Note 2)

NF

Noise Figure (Note 2)

NOTES:

VGS

35

rnA

p.s

800

VOS = 15V, VGS = 0
f

= 200MHz
200
6
pF

f=IMHz
2
VOS = 15V, VGS
RG= lk!1

=0

f= 100MHz

1. These parameters are measured dunng a 2ms ,nterval lOOms after DC power ,s applied.
2. For design reference only, not 100% tested.

2-7
Note: All typical values have been guaranteed by characterization and are not tested.

2.5

dB

!

2,N3824,

N

Switch

"

-; N~hannel JFET
FEATURES
•

rds < 250 Ohms

•

10(Off)

CHIP TOPOGRAPHY
5003

< 0.1nA

PIN CONFIGURATION

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Gate-Source or Gate-Drain Voltage .................... - 50V
Gate Current ................................................. 10mA
Storage Temperature Range ............ -65°C to +200°C
Operating Temperature Range ......... -55°C to + 175°C
Load Temperature (Soldering. 10sec) .............. + 300°C
Power Dissipation ......................................... 300mW
Derate above 25°C ...................... ; ... 2.0mW 1°C

PC000201

ORDERING INFORMATION*

'When ordering waferI dice refer, to Section 10. page 10-1.

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS' 25°C unless otherwise noted
LIMITS
SYMBOL

PARAMETER "

TEST CONDITIONS

,.

I

IGSS

Gate Reverse, Current,

BVGSS

Gate-Source Breakdown Voltage

10(af!)

Drain Cutoff Current

TA = 150·C

VGS

= -30V.

VOS = 0

TA=150·C

VOS = 1.5V. VGS = ,-BV

rds(on)

Drain-Source ON Resistance

VGS=OV.lo=O

CiSS

Common-Source Input Capacitance
(Note 1)

VOS = 15V. VGS = 0

Crss

Commol)-Source Reverse
(Note 1)

f= 1kHz

VGS = -BV. VOS = 0

NOTE 1: For design reference only, not 100% tested.

2~

Note: All typical values have been guaranteed by characterization and are nol tested.

-0.1

nA

-0.1

IJ.A
V

"

0.1

nA

0.1

IJ.A

250

S1

6
f=lMfo!,z

Capacitance

MAX

-50

IG= llJ.A. VOs=O

I
Tran~9r

UNIT
MIN

pF

"

3

2N3921, 2N3922
Dual N-Channel JFET
General Purpose Amplifier
FEATURES
•
•
•

CHIP TOPOGRAPHY

Low Drain Current
High Output Impedance
Matched VGS. AVGS. and gfs

6037

1+--.025--1

PIN CONFIGURATION
TO-71
s,-

.!~itll;; t

D'.~S.
,COPR

__

..

G,

ALL BONO PADS ARE 4 x '" MIL.
CTOOO71!

ABSOLUTE MAXIMUM RATINGS
(TA = 2S0C unless otherwise noted)
Gate-Source or Gate-Drain Voltage (Note 1) ........ -SOV
Gate Current (Note 1) ..................................... SOmA
Storage Temperature Range ............ -6SoC to +200°C
Operating Temperature Range ......... -SSoC to +200°C
Load Temperature (Soldering, 10see) .............. + 300°C
Total Power Dissipation ................................. 300mW
Derate above 2SoC .......................... 1.7mW/oC

PC00051I

ORDERING INFORMATION*
TO·71

WAFER

DICE

2N3921

2N3921/W

2N3921/D

2N3922

2N3922/W

2N3922/D

'When ordering wafer/dice refer to Section 10, page 10--1.

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: (2S0C unless otherwise noted)
PARAMETER

SYMBOL

TEST CONDITIONS

I

IGSS

Gate Reverse Current

BVOGO

Drain-Gate Breakdown Voltage

10=lpA,ls=0

TA -100·C

MIN

VGS = -30V, VOS = 0

VGS(olf)

Gate·Source Cutoff Voltage

VOS = 10V, 10 = InA

VGS

Gate·Source Voltage

VOS = 10V, 10 = 100pA

IG

Gate Operating Current

10S$

Saturation Drain Current (Note 1)

gfs

Common·Source Forward
Transconductance (Note 2)

90S

Common-Source Output Conductance

Ciss

Common·Source Input CapaCitance (Note 3)

Crss

Common·Source Reverse Transfer CapaCitance
(Note 3)

9fs

Common-Source Forward Transconductance

gas.

Common·Source Output Conductance

NF

Spot Noise Figure
(Note 3)

MAX

UNIT

-1

nA

-1

pA

-3

V

50
-0.2

-2.7
-250

I

TA = 100·C

VOG = 10V, 10 = 700pA
Vos -10V, VGS - 0

nA

1

10

rnA

1500

7500

f=lkHz
VOS

= 10V,

pA

-25

35

VGS = 0

!,S

18
pF
f-1MHz

6
1500

VOG = 10V, 10 = 700pA

f= 1kHz

VOS = 10V, VGS = 0

f= 1kHz,
RG = lmeg

2-9
Note: All typical values have been guaranteed by characterization 'and are not tested.

20

!,S

2

dB

·'i

2,N;J921 •.. 2N392~

;

MATCHING CHARACTERISTICS'

tt

;:=z
tt

. .D~DIL
.

2N3921
SYMBOL

PARAMETER

UNIT
MIN

IVGS1- VGS21

Differential Gate-Source Voltage

AlvGS1- VGS2 1

Gate~Source

AT
91.1/9182

Differential Voltage
Change with Temperature

2N3922

TEST CONDITIONS
MAX

MIN

5
VOG= 10V.
10 = 700p.A

TA=O'C
Ts = 100'C
f-lkHz

Transconductance Ratio

NOTES: 1. Per transistor.
2. Pulse test duration =,.2 ms.
3. For design reference ~nly, not 100% tested.

2-10
Note: All typical values have been guaranteed by characterization and are not tested.

10
0.95

1.0

0.95

MAX
5

mV

25

/lVrC

1.0

2N3954-2N3958
2N3954A/2N3955A
Dual N-Channel JFET
G.eneral Purpose Amplifier
FEATURES
•
•
•
•
•

CHIP TOPOGRAPHY

Low Offset and Drift
Low Capacitance
Low Noise
Superior Tracking Ability
Low Output Conductance

N

Z

6037

W
G

!

1·- -.025,,---1

PIN CONFIGURATION

ii
zW

:_'F.l

TO-71

.....

_

G
UI

I:

t

G.

'ALL BOND PADS ARE"

II: "

MIl.

CTOO0811

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Gate-Drain or Gate-Source Voltage .................... -50V
Gate-to-Gate Voltage ................... : .................... ±50V
Gate Current ..................................,' .............. 50mA
Total Device Dissipation 85°C (Each Side) ........ 250mW
Case Temperature
(Both Sides) ........ 500mW
Power Derating (Each Side) ...................... 2.8SmWI"C
(Both Sides) ....................... 4.3mW I"C
Storage Temperature Range ............ -S5°C to +200°C
Lead Temperature (1/1S" from case
for 10 seconds) .......................................... 300°C

PC000501

ORDERING INFORMATION*
TO-71
2N3954

2N3954/W

2N3954A

2N3954A/W

2N3954A1D

2N3955

2N3955/W

2N3955/D

2N3955A

2N3955A/W

2N3955A1D

2N3956

2N3956/W

2N3956/D

WAFER

DICE
2N3954/D

2N3957

2N3957/W

2N39571D

2N3958

2N3958/W

2N3958/D

'When ordering wafer/dice refer to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS
SYMBOL

PARAMETER

(25°C unless otherwise noted)

TEST CONDITIONS

2N3954

2N3954A

2N3955

2N3955A

2N3956

2N3957

2N3958

UNIT

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
Gate Reverse Current
IGSS

BVGSS

VGS = -30V,
I TA = 125°C Vos=O
Gate-Source
Vos-O
Breakdown Voltage
IG = -lIlA

-10

-10

-lOi

-IOi

-10e

-10

-10

pA

-50

-50

-SOi

-50

-5OC

-50

-50

nA

-50

-50

-50

-50

-50

-50

-50

VGS(Off)

Gate-Source Cutoff
Voltage

Vos = 20V,
10= lnA

VGS{o

Gate-Source Forward
Voltage

Vos=O
IG=lrnA

VGS

Gate-Source Voltage

Vos = 20V

Gate Operating Current

Vos = 20V,

-50

-50

-50

-50

-50

-50

-50

ITA = 125°C 10 = 2001lA

-25

-25C

-25C

-25

-25

-25

-25C

nA

5.0

rnA

IG

loss

Saturation Drain
Current

-1.0 -4.5 -1.0 -4.5 -1.0 -4.5 -1.0 -4.5 -1.0 -4.5 -1.0 -4.5 -1.0 -4.5
V
110 = 501lA

Vos = 20V,
VGs=O

110 = 2001lA

2.0

2.0

2.0

2.0

2.0

2.0

2.0

_4.2

-4.2

-4.2

-4.2

-4.2

-4.2

-4.2

-0.5 -4.0 -0.5 -4.0 -0.5 -4.0 -0.4 -4.0 -0.5 -4.0 -0.5 -4.0 -0.5 -4.0

0.5

5.0

0.5

2-11
Note: All typical values have been guaranteed by characterization and are not tested.

5.0

0.5

5.0

0.5

5.0

0.5

5.0

0.5

5.0

0.5

pA

2

j

2Na'5"'2",a9'~ ~":I954A/2N3955A .

'f')

ELECTRICAL .CHARACTERISTICS (CONT.)

:.....

I
C
J

•

I

:IG»

;

i
f')

z
C\I

SYMBOL

' . '

PARAMETER

TEST CONDITIONS

Common-Source Forward

~

Tranaconductance

g""

Coinmon-Source' OutPut
Conductance

q.

Common-Source Input
Capacitance (Note 2)

C...

Common Source Reverse
Transfer Capscitance
(Note 2)

Cdgo

Drain-Gate Capscitance
. (Note 2)

NF

Common-Source Spot .'
Noise Figure .
(Note 2)

lim -la2 1

Differential Gate C~rreni

loss,IIoss2

Drain Saturation
Current Ratio

(Note 2)
Vos = 2OV,
Vas=O

20V,
10 - 200pA
Vos=20V
VGS.=O

Gate-Source Differe.ntial

aT
g';',Ig.",

Voltage Change With
Temperature
Transconductance Ratio

Vas - 20V,
10= 200pA

2N3955A· 2N.395&

2N3957

2N3958

1000

1000

1000

1000

1000

1000

UNIT

1000

I'S
35

35

35

35

35

35

35.

4.0

4.0

4.0

4.0

4.0

4.0

4.0

1.2

1.2

1.2

1.2

1.2

1.2

1.2

1.5

1.5

1.5

1.5

1.5·

1.5

1.5

I = 100Hz

0.5

0.5

0.5

0.5

0.5

0.5

0.5

dB

T -125'C

10

10

10

10

10

10

10

nA

pF

0.95 1.0 0.95 1.0 0.95 1.0 0.95 1.0 0.95 1.0 0.90 1.0 0.85 1.0

IVaS,-vGS2 1 Differential Gate-Source
Voltage

alvGS,-v... 1

2N3955

1-200MHz
1= 1kHz

VDG= 10V,
1.-0

Vos -

2N3954A

I-1kHz

l=lMHz

Vos-20V
V... -O
. Ra=lOMf!

2N3954

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
1000 3000 1000 3000 1000 3000 1000 3000 1000 3000 1000 3000 tOOO 3000

5.0

5.0

10.0

5.0

15

20

25

T=2S'C to
-55'C

0.8

0.4

2.0

1.2

4.0

6.0

8.0

T-25'Cto
125'C
I-1kHz

1.0

0.5

2.5

1.5

5.0

7.5

10.0

0.97 1.0 0.97 1.0 0.97

NOTES: 1. Per Transistor.

.
2. For design reference only, not 100% tested,

2-12
Note: All typiCal values have been guaranteed by characterization and !!fe not tested.

1.0

0.95 1.0 0.95 1.0 0.90 1.0 0.85 1.0

mV

2N3970-2N3972

N-Channel JFET Switch
FEATURES

CHIP TOPOGRAPHY

•
•

Low rDS(on)
ID(OFF) < 250pA

•

Fast Switching

SOOl
.00135 FULL RADIUS
.00l75 (DRAIN)

PIN CONFIGURATION
TO·18

x

I--- --I
.016

.OO3~

.0026

(SOURCE)
CT000911

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Gate-Source or Gate-Drain Voltage .................... -40V
Gate Current ................................................. 50mA
Storage Temperature Range ............ -65°C to +200°C
Operating Temperature Range ......... -55°C to +200°C
Lead Temperature (Soldering. 10sec) .............. + 300°C
Power Dissipation ............................................ 1.SW
Derate above 25°C ........................... 10mW/oC

o
PC000611

ORDERING INFORMATION*
TQ-18

WAFER

DICE

2N3970

2N3970/W

2N3970/D

2N3971

2N3971/W

2N3971 10

2N3972

2N3972/W

2N3972/D

·When ordering wafer I dice refer to Section 10·, page 10-1.

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: 25°C unless otherwise noted
2N3970
SYMBOL

PARAMETER

2N3971

2N3972

TEST CONDITIONS

UNIT
MIN MAX MIN MAX MIN MAX

BVGSS

Gate Reverse Breakdown Voltage

1000

Drain Reverse Current

10(0f!)

Drain Cutoff Current

ITA ~ 150·C
iTA

= 150·C

VOG = 20V, IS = 0
VOG = 20V, VGS = -12V

VGS(Of!)

Gate·Source Cutoff Voltage

Vos = 20V, 10 = lnA

loSS

Saturation Drain Current
(Pulse width 300l'S, duty cycle::; 3%)

VOS = 2OV, VGS = 0

VOS(on)

Drain·Source ON Voltage

VGS=O

-40

-40

IG = -lIlA, VOS = 0

-40
250

2SO

pA

500

500

SOO

nA

250

250

2SO

pA

500

500

nA

-4

-10

-2

-5

-0.5

500
-3

50

150

25

75

5

30

10= 5mA
1.5
30

60

100

30

60

100

25

25

25

6

6

6

RL

10

15

40

450.11

10

15

40

30

60

100

Static Drain·Source ON Resistance

VGS=O, 10= lmA

rels(on)

Drain·Source ON Resistance

VGS=O, 10=0

Ciss

Common·Source Input Capacitance

VOS = 20V, VGS = 0 (Note 1)

Cr••

Common·Source Reverse Transfer
Capacitance

VOS=O, VGS= -12V
(Note 1)

Id

Tum-On Delay Time (Note 1)

1r
loft

Rise Time (Note 1)

Voo = 10V, VGS(on) = 0
10(on) VGS(ofI)
2N3970
20mA -10V
2N3971
2N3972

8SOn
1.6Kn

f= 1kHz

f=lMHz

- 5V
- 3V

NOTE 1: For design reference only, not 100% tested.

2-13
Note: All typical values have been guaranteed by characterization and are not tested.

V

1

rOS(on)

10mA
5mA

V

rnA

2

10= 10mA
lo=20mA

Turn-Off Time (Note 1)

V

250

.11

pF

ns

·..0)~ 2N3.97Q;'2N3972 . ". "
..CO)

.Z .' EL.:ECTRICAL tHARACTERISTICS(CONT.)

,: &\I

~

...

VDD

=

• R _ VDD-VDSlONI

Z

l'

.&\1

D

VIN 0 - -......-

Ra

L -

IDlON)

~VOUT

1_-,

....

;

500

TCO0551I

2-14
Note: All typical '(alues have been guaranteed by characterization and are. not testeP..

.U~UIl.I

2N3993, 2N3994
P-Channel JFET
General Purpose AmplifierISwitch

.~
~

z

FEATURES

APPLICATIONS

•
•

Used in high-speed commutator and chopper applications. Also ideal for "Virtual Gnd" switching; needs no ext.
translator circuit to switch ±10 VAC. Can be driven direct
from TTL or CMOS logic.

Low rOS(on)
High Yfs/Ciss Ratio (High-Frequency Figure-ofMerit)

PIN CONFIGURATION

=

:

CHIP TOPOGRAPHY
5508

TO-72

~Jliil~'-'
.0025

.0027

.016

.0037 x .0035 0

.0027

.0025

=

NOTE: SUBSTRATE IS GATE

CTOO1011

PCO0071I

ABSOLUTE MAXIMUM RATINGS
ORDERING INFORMATION*
TO-72

WAFER

2N3993

2N3993/W

2N3993/D

2N3994

2N3994/W

2N3994/D

'When ordering wafer/dice refer to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS
SYMBOL
BVGSS
lOGO
loSS

10(of!)

@

25°C free-air temperature (unless otherwise noted)

TEST CONDITIONS

PARAMETER
Gate-Source Breakdown Voltage
Drain Reverse Current
Zero-Gate-Voltage Drain Current

Drain Cutoff Current

n

6r~i~-~!:~ ~:::::e ~~~~~i.~~ ~.~~~.~~

..
.................... -25V
Drain-Source Voltage ....................................... -25V ~
Continuous Forward Gate Current .................... -1 OmA
Storage Temperature Range ............ -65°C to + 200°C
Operating Temperature Range ......... -55°C to + 175°C
Lead Temperature (Soldering. 10sec) .............. + 300°C
Power Dissipation ......................................... 300mW
Derate above 25°C .......................... 2.0mWI"C

DICE

(Note 3)

2N3993

2N3994
UNIT

MIN

MAX

MIN

MAX

IG = lIlA.

VOS=O

VOG = -15V,

10=0

-1.2

-1.2

nA

Voo = -15V,

1.-0,
TA = 150'C

-1.2

-1.2

IlA

VOS= -10V,

VGS= 0,
(See Note 1)

Vos= -10V,

VGs=6V

VOS= -10V,

VGS= 6V,
TA = 150'C

VOS= -10V.

VGS -10V

-1.2

VOS= -10V,

VGs=10V,
TA = 150'C

-1

VGS(of!)

Gate-Source Voltage

VOS= -IOV,

10 = -lIlA

rdo(on)

Small-Signal Drain-Source
On-State Resistance

VGS-O,
f= 1kHz

10- 0•

iYf. i

Small-Signal Common-Source
Forward Transfer Admittance

Vos= -IOV,
f= 1kHz,

VGS=O,
(See Note 1)

Ciss

Common-Source Short-Circuit
Input Capacitance (Note 4)

VOS= -10V,
f= IMHz,

VGS=O,
(See Note 2)

2-15
Note: All typical values have been guaranteed by characterization and are not tested.

25

25

-10

4

-2

9.5

12
16

mA
-1.2

nA

-1

IlA
nA

IlA
1

150
6

V

4

5.5

V

300

n

10

/.IS

16

pF

: 2"3,993,·2N3994

iN

:o

ELECTRICAL CHARACTERISTICS (CONT.)
SYMBOL

..

'"

Z
N

TEST CONDITIONS
(Note 3)

PARAMETER

Cr••

Common-Source Short-Circuit
.Reve(VSE1- VSE2)IIL>T

Base Emitter
Voltage Differential
Change with
Temperature

3

S

10

IlVI"C

1L>(lel- ls2)I/L>T

Base Current
Differential
Change with
Temperature

0.3

0.5

1

nAI"C

0.9

le= lallA.
VeE =SV
TA = -S5°C to + 12SoC

1

0.85

1

0.8

1

SMALL SIGNAL CHARACTERISTICS
SYMBOL

PARAMETER

hlb

Input Resistance

hrb

Voltage Feedback Ratio

hie

Small Signal Current Gain

hob

Output Conductance

hie

Input Resistance'

hre

Voltage Feedback .Ratio

hoe

Output Conductance

NOTES:

1.
2.
3.
4.

TYPICAL
VALUE

TEST CONDITIONS

28
Ie ~1 mAo Ves = 5V (Note 4)

43

UNIT
n
x 10- 3

250
Ie = lmA. VeE = SV (Note 4)

.,

60

/lS

9.6

kn

42
12

x

10-~

IlS

Per transistor.
The reverse base-emitter voltage must never exceed 7.0 volts and the reverse base-emitter current must never exceed 101lA.
The lowest 01 two hFE readings is taken as hFEl lor purposes 01 this ratio.
For design relerence only. not 100% tested.

2-18
Note: All typical values have been guaranteed by characterization and are not tested.

ITE4091-ITE4093
2N4091-2N4093
JAN, JTXV, JANTX·
N-Channel JFET
Switch
FEATURES
•
•
•

CHIP TOPOGRAPHY

Low rDS(on)
ID(OFF) < 100pA (JAN TX Types)
Fast Switching

5001

PIN CONFIGURATIONS
TO-18

TO·92

x .0036
.0028
(SOURCE)
CTO05511

ABSOLUTE MAXIMUM RATINGS
G,C

s

o

0

(TA = 25°C unless otherwise noted)
Gate-Source or Gate-Drain Voltage .. , .... , ........... , -40V
Gate Current, ............ ,"',." ........... ,", .. , ..... , ... , 10mA
Storage Temperature Range ............ -65°C to +200°C
Operating Temperature Range ......... -55°C to +200°C
Lead Temperature (Soldering, 10sec) .............. + 300°C
TO-18
T0-92

G

PCOO3711

ORDERING INFORMATION*
TO-92

TO-1St

WAFER

DICE

ITE 4091

2N4091

2N4091/W 2N4091/0

ITE 4092

2N4092

2N4092/W 2N4092/0

ITE 4093

2N4093

2N4093/W 2N4093/0

Power Dissipation".""""""".".
Derate above 25°C"."""""."

Plastic
Storage .............................. " .... -55°C to + 150°C
Operating ............................ " .... - 55°C to + 135°C

tadd JANTX to these part numbers if JANTX processing is desired,
'When ordering wafer/dice refer to Section 10, page 10-1,

ELECTRICAL CHARACTERISTICS

SYMBOL

(25°C unless otherwise noted)

PARAMETER

TEST CONDITIONS

2NIITE
4091

2NIITE
4092

MIN MAX MIN
BVGSS

Gate·Source Breakdown Voltage

IG

= -ljJA,

VOS = 0

(Not JANTX Specified)

200
ITA = 150'C

Voo = 20V, IS = 0

Gate Reverse Current
IGSS
10(OFF)

I(JANTX,

ITE devices only) TA = 150'C

JAN, JTXV; TA = 25'C
Drain Cutoff Current
JAN, JTXV, TA = 150'C

Vp
loSS

VGS = -20V, VOS = 0

~ VOS= 20V

VGS - -12V(4091)
VGS = -8V(4092)
VGS = -6V(4093)

~

Gate·Source Pinch·Off Voltage

VOS - 20V, 10 - lnA

Drain Current at Zero Gate Voltage

VOS - 20V, VGS - 0,
Pulse Test Duraton = 2ms

-5

-40
200

Drain·Source ON Voltage

VGS=O

2-19
Note: All typical values have been guaranteed by characterization and are not tested.

V
200

pA

400

400

400

nA

-100

-100

pA

-200

-200

-200

nA

100

100

100

200

200

200

200

200

200

400

400

400

-10

30

-2

-7

15

-1

-5

pA

nA
V
mA

8
0.2

10 = 4mA
10 = 6.6mA

UNIT

-100

10 = 2.5mA
VOS(ON)

2NIITE
4093

MAX MIN MAX

-40

-40

Drain Reverse Current
1000

360mW
3,3mWrC

1,8W
10mWrC

0.2
0.2

V

2

.O~Dll

ITE4091-ITE4093 .
2N.4091-2N4093 JAN, JTXV, JANTX*
ELECTRICAL CHARACTERISTICS (CONT.)
SYMBOL

PARAMETER

TEST CONDITIONS

2N/ITE

.2NIITE

2""TE

40111

4092

4093

MIN

UNIT

MAX MIN MAX MIN MAX

rOS(on)

Static Drain-Source ON Resislance

VGS=O,10-1mA

30

50

80

rds(on)

Sialic Drain Source
ON Resistance

Vas - 0, 10 = 0, f= 1kHz

30

50

80

Ciss

Common-Source Inpul Capacitance

Vos-20V, VGS-O, f-1MHz

16 .

16

16

IJANTX Only

(Nole 1)

5

5

5

Crss

Common-Source
Reverse Transfer. Capacitance

VOs=O, Vas = -20V, f=1MHz
(Nole 1)

5

5

5

Id(ON)

Turn-ON D.elay TilTle (Nole 1)

Ir

Rise ·Time (Nol", 1)

loft

Turn-OFF Time (Note 1)

VOO =
4091
4092
4093

3~(O~ao(o~~;!
"8lrmA

~

 RL

90%

V'N

V".(ON)

RG

100n

220n

390n

IO(ON)

-15mA

-7mA

-3mA

:

~.~~

_ 6V 10%

t,

90%

10%

510

t--

-12V

-7V

-5V

WF00011I

7.5K.

v

>

t.2K

L-...,.. SAMPLING

~

~-SCOPE-

:

RISE TIME 0.4 ns
INPUT RESISTANCE 10 MHz
INPUT CAPACITANCE 1.5 pF

\ __

~

Ro
v

;.
>
;>

1

SAMPLING SCOPE

12K

~

V'N~

OUTPUT

VIN

?

510

.
510

":"
TCOO171 I

TYPICAL PERFORMANCE CHARACTERISTICS
Vp vs loss

Vp VB rOS(ON)

...
7.0
U
'.0

7.G

4.0

~
>

'.0
2.0

...t.o

7.0

4.0

'\

\.

!

'los = 0.1'1
'los = 0

1\

-'vVas
Ol ""= 020V

2.0

...
...,

4.0

-

3.0

II

1.0

0.&
0..

0..

t.OOO

'0

30

2-37

iPUlood)

...
,.0

.

,
OPOO1211

Note: All typical values have been guaranteed by characterization and are not tested.

Vos "" 20V
Vos'" 0

2.0

_mAl
OPOO1111

I

>

0.&
0.7

OA
0.7

to

'0.0

...
...s.o

U

Vp vs 9fS

......
...s.o
...
~

to.O
1.0

10.0

!...

jJJ

2N5114 = -18V
2N5115= -15V
2N5116 = -15V

Drain Current at Zero Gate Voltage
(Note 1)

tz

OA
0. 7
0.
O.
1,000

••

3,000

10,000

30,000

100,000

• .....Yl
OPOO1311

>

! 2N5117-2N5119

I Dielectrically Isolated Dual PNP
~ General Purpose Amplifier
'P'
'P'

10

I

,FEATURES
•
•
•
•
•

CHIP TOPOGRAPHY

High Gain at Low Current
Low Output Capacitance
Good hFE Match
Tight VBE Tracking
Dlelectrlcally Isolated Matched Pairs for
Differential Amplifiers

4501

1-,033-j

~
.

EMITTER ,1lO29

.0039

.023

L

PIN CONFIGURATION'

EMITTER

x ,1lO29
.0039

TYP 2 PLACES
BASE

COLLECTOR

.ob3o x

.0030

.0040

.0040

TYP 2 PLACES

.0035 x .0034

BASE

..0045

.0044

TYP2PLACES
CT001711

TO-78

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Collector-Base or Collector-Emitter
Voltage (Note 1) ........................................... -45V
Emitter-Base Voltage (Notes 1 and 2) .................. - 7V
Collector-Collector Voltage ................................. 100V
Collector Current (Note 1) ................................ 10mA
Storage Temperature Range ............ -65°C to +200°C
Operating Temperature Range ......... -55°C to +200°C
Lead Temperature (Soldering, 10sec) .............. + 300·C
ONE SIDE
BOTH SIDES

PCOO1101

ORDERING INFORMATION*
TO-78

WAFER

DICE

2N5117

2N5117/W

2N5117/D

2N5118

2N5118/W

2N5118/D

2N5119"

2N5119/W

2N5119/D

400mW
2.3m'l"'oC

Power Dissipation.....................
Derate above 25°C................

750rilW
4.3mW'oC

·When ordering waler/dice reler to Section 10, page la-I,

ELECTRICAL CHARACTERISTICS
SYMBOL

(25°C unless otherwise noted)

PARAMETER

2N5117
2N5118

TEST CONDITIONS

2N5119

UNIT

MIN MAX MIN MAX
hFE

DC Cumint 'Gain
ITA = -55°C

ICBO

Collector Cutoff·Current

IC = lallA. VCE = 5.0V

100

Ic = 500PA. VCE = 5.0V

100

Ic = lallA. VCE

= 5.0V

300

50

30

IE-a. Vce-3OV
,ITA-1S0°C

50
20

0.1

0.1

nA

0.1

0.1

IIA
nA

lEBO

Emitter Cutoff Current

IC = O. VEB = 5.0V

0.1

0.1

IC1,C2
GBW

Coliector·Coliector Leakage

Vcc-l00V

5.0

5.0

Current Gain Bandwith Product (Note 4)

Ie = 5001lA.

100

VCE = 10V

100

COb

Output Capacitance (Note 4)

IE'" 0, Vee = 5.0V. 1= lMHz

Gte

Emiller Transition CapaCitance (Note 4)

IC - 0, VEe

CC1,C2

Coliector·Colleqlor Capacitance (Note 4)

Vee - 0, I = 1MHz

VCEO(sust)

Coliector·Emitter Sustalni,ng Voltage

Ic = 1'.OmA. Ie = 0

NF

Narrow Band Noise Figure (Note 4)

IC = lallA. VCE = 5.0V
BW= 200Hz

BVCBO

Collector Base Breakdown Voltage

Ic = lallA. IE = a

45

45

V

BVEeO

Emitter Base Breakdown Voltage

IE = lallA. Ic = a

7.0

7.0

V

= 0.5V,

0.8

pA
MHz

1= lMHz

I'

2-38
Note: All typical values have been guaranteed by characterization and are not tested.

1.0

0.8

0.8

45
= 1kHz. RG

= 10kO

O.B

1.0
45
4.0

pF
V

4.0

dB

MATCHING CHARACTERISTICS

I
(25°C unless otherwise noted)
2N5117

SYMBOL

PARAMETER

2N5118

~

2N5119

TEST CONDITIONS

UNIT
MIN MAX MIN MAX MIN MAX

DC Current Gain Ratio
hFE1/hFE2

(Note 3)
Base-Emitter Voltage

VSE,-VSE2
Is 1-IS2

Base Current Differential
Base Voltage Differential
Change with Temperature

"(ls 1-ls2)/"T

Base-Current Differential
Change with Temperature

NOTES:

1.
2.
3.
4.

Ie - 10iJA to SOOIlA, VeE

= SV

= 10iJA, VeE = S.OV
Ie = 10iJA to SOOIlA, VeE = SV

0.9

Ie - 10iJA, VeE

= S.OV

0.85

1.0

0.8

1.0
mV

3.0
5.0

5.0

10.0

15

40

nA

TA= -55'Cto + 125'C

3.0

5.0

10

IlV/'C

TA= -55'Cto + 125'C

0.3

0.5

1.0

nAI'C

Per transistor.
The reverse base-la-emitter voltage must never exceed 7.0 volts and the reverse base-to-emitter current must never exceed 101lA.
Lower of two hFE readings is defined as hF E1'
For design reference only, not 100% tested..

2--'l9

Note: All typical values have been guaranteed by characterization and are not tested.

Z

ca

I&)

1.0

Ie

Differential

"(VSE1-VSE2)1 "T

.......
..
N

2N5117-2N5119

i!

2N51'96-2N5199

~
o

Gene·ral· Purpose Amplifier

.!II Dual N-Channel JFET
;;z

PIN CONFIGURATION

"

CHIP TOPOGRAPHY
6037

TO-7,l

0,

ALL80ND PADS ARE 4x 4MIL.
CT000701
PC002501

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Gate-Source or Gate-Drain Voltage (Note 1) ........ -50V
Gate Current (Note 1) ..................................... 50mA
Storage Temperature Range ............ -65°C to +200°(;
Operating Temperature Range ......... ~55°C to + 150°C
Lead Temperature (Soldering, 10sec) .............. + 300°C
ONE SIDE' BOTH SIDES

ORDERING INFORMATION*
T0-71

WAFER

DICE

2N5196

2N5196/W

2N5196/D

2N5197

2N5197/W

2N5197/D

2N5198

2N5198/W

2N5198/D

2N5199

2N5199/W

2N5199/D

Power Dissipation (TA = 85°C) ... .
Derate above 25°C ............... .

250mW
2.6mW/"C

500mW
4.3mW/oC

·When ordering wafer/dice refer to Section 10, page 10-1,

ELECTRICAL CHARACTERISTICS
SYMBOL
IGSS

(25°C unless otherwise noted)
TEST' CONDITIONS

PARAMETER
Gate Reverse Current

MIN

VGS = -30V, Vos = 0
ITA = 150·C

MAX

UNIT

-25

pA

-50

nA
V

BVGSS

Gate-Source' Breakdown )/oltage

IG=-lj.iA, VOS=O

-50

VGS(off)

Gate-Source Cutoff Voltage

VOS = 20V, 10 = lnA

-0.7

-4

VGS

Gate-Source Voltage

-0.2

-3,8

IG

Gate Operating Current

-15

VOG = 20V,Io = 200j.iA
ITA -125·C

lOSS

Saturation Drain Current (Note 2)

VOS = 20V, VGS = 0

Qfs

Common-Source Forward Transconductance (Note 2)

VOS - 20V, VGS

Qfs

Common-Source Forward Transconductance (Note 2)

YOG - 20V, 10 = 200j.iA

gas

Common-Source Output Conductance (Note 2)

VOS = 20V, VGS = 0
VOG = 20V, 10 = 200j.iA

gas

Common-Source Output Conductance (Note 2)

Ciss

Common-Source Input Capacitance (Note 4)

Crss

Common-Source Reverse Transfer Capacitance
(Note 4)

NF

Spot Noise Figure (Note 4)

en

Equivalent Input Noise Voltage (Note 4)

=0
f= 1kHz

pA

-15

nA

0.7

7

rnA

1000

4000

700

1600
50

/J.s

4

6
f=lMHz

pF
2

VOS = 20V, VGS = 0

f = 100Hz,
RG = 10Mn

0.5

dB

f= 1kHz

20

/J.nV

JFIz

2-40
Note: All typical values have been guaranteed by characterization and, are not tested,

Z

VI
CD

ELECTRICAL CHARACTERISTICS (CONT.)
2N5196
SYMBOL

PARAMETER

2N5197

2N5198

2N5199

TEST CONDITIONS

UNIT
MIN MAX MIN MAX MIN MAX MIN MAX

IIG1-IG2 1

Differential Gate Current

VOG =20V,
10 = 2001'ft,

IOSSI/10SS2

Saturation Drain Current Ratio
(Note 2)

VOS = 20V, VGS = OV

9101 / g'02

Transconductance Ratio
(Note 2)

IVGS1-VGS2 1

Differential Gate-Source Voltage

LllvGS1=VGS2 1 Gate-Source Differential Vo~age
Change with Temperature
LIT
(Note 3)
1gOOI-go021

NOTES:

1.
2.
3.
4.

..
~
..
I
N

2N5196-2N5199

125"C

f= 1kHz

Voo = 20V,
10 = 2001'ft,

0.95
0.97

TA - 25"C
TS = 12S"C
TA= -55"C
TR = 2SoC
f= 1kHz

Differential Output Conductance
Per transistor.
Pulse test required, pulsewidth = 300"s, duty cycle
Measured at endpOints TA and T B.
For design reference only, not 100% tested.

5

< 3%.

2-41
Note: All typical values have been guaranteed by characterization and are not' tested.

5

5

1

0.95

1

0.97

1

0.95

1

0.95

5

1

0.95

1

0.9S

nA

1
1

5

5

10

15

5

10

20

40

5

10

20

40

1

1

1

1

mV

",I"C
is

Z

VI

.U~UI6

2N5397, 2N5398

iz

II)

C\I

N~¢hannel JFET
High F~equency Amplifier
FEATURES
G,s = 15dB Minimum (Common Gate) at 450MHz

•
•

,

,

.,

CHIP TOPOGRAPHY
5011

Uw Noise
Low Capacitance

•

" ' " ,

I--- .015---1
I
I

PIN CONFIGURATION

NOTE: SUBSTRATE
IS GATE.

T~.

.012

TO-72

0.0035
.0042
.0025 x -:0032

1

S .0035 x .00405
.0025
.00305 '
CTOO191t

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Drain-Gate Voltage ........................................... 25V
Drain-Source Voltage ............................. : ........... 25V
Continuous Forward Gate Current.. .................... 10mA
Storage Temperature Range ............ -65·C to +200°C
Operating Temperature Range ......... -55°C to + 150°C
Lead Temperature (Soldering, 10sec) .............. + 300°C
Power Dissipation ......................................... 300mW
Derate above 25°C .......................•.. 2.4mW fOC

PCOOO201

ORDERING INFORMATION*
TC>-72

WAFER

DICE

2N5397

2N5397/W

2N5397/D

2N5398

2N5398/W

2N5398/D

'When ordering waferI dice refer to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS

(25°C unless otherwise noted)
2N5397

SYMBOL

PARAMETER

UNIT
MIN

IGSS

2N5398

TEST CONDITIONS

Gate Reverse Current

VGS= -15V, VOS=O
ITA = + 150·C

150·C

MAX

MIN

MAX

-0.1

0.1

nA

-0.1

-0.1

IIA

BVGSS

Gate-Source Breakdown Voltage

VOS=O, IG =

-IlIA

-25

VGS(off)

Gate-Source Cutoff Voltage

VOS = 10V, 10 = InA

-1.0

-6.0

-1.0

-6.0

loSS

Saturation Drain Current (Note I)

VOS = 10V, VOS = 0

10.

30

5

40

rnA

VGS(f}

Gate-Source Forward Voltage

VOS-O,IG-lmA

1

V

Common..source JForward

'-:OS = 10V, 10 = lOrnA

6000

10,000

Transconductance (Note I)

VOS = 10V, VGS = 0

Common..source Output

VOS

Conductance

VOS = 10V, VGS = 0

Common-Source Reverse Transfer

Vos = 10V, 10 = lOrnA

Capacitance (Note 2)

VOS = 10V, VGS = 0

gls
goss
Crs•

= 10V,

10 = lOrnA

VOG = 10V, 10 = lOrnA
Cis.

Common-Source Input CapaCitance
(Note 2)

VOS = 10V, VGS = 0

2-42
Note: All typical values have been guaranteed by characterization and are not tested.

-25

1

f= 1kHz

,

5500

V

10,000

ps

200
400
1.2
1.3

f=IMHz

pF

5.0
5.5

2N5397, 2N5398
ELECTRICAL CHARACTERISTICS (CONT.)
2N5397
SYMBOL

PARAMETER

UNIT
MIN

9iss

9055

Common-Source Input

VOG = 10V, 10 = 10mA

Conductance (Note 2)

VOG = 10V, VGS = 0

Common-Source Output

VOG = 10V, 10 = 10mA

Conductance (Note 2)

VOS = 10V, VGS = 0

Common-Source FOlWard

VOG = 10V, 10 = 10mA
VOS = 10V, VGS

9fs

Transconductance (Note 1, 2)

Gps

Common-Source Power Gain (neutralized)

NF

Common-Source, Spot Noise
Figure (neutralized)

NOTES:

2N5398

TEST CONDITIONS
MAX

MIN

MAX

2000
3000
400
500
f = 450MHz

5500

IlS

9000

=0

5000

10,000

15
dB

VOG = 10V, 10 = 10mA
3.5

(Note 2)

1. Pulse test duration = 2ms
2. For design reference only, not 100% tested.

2-43
Note: All typical values have been guaranteed by characterization and are not tested.

2N5432-2N5434
N-Channel JFET Switch
CHIP TOPOGRA~HY

FEATURES
•

Low rds(on)

.•

Excellent SWitching

•

Low Cutoff Current'

5018

o
.0035 . x .0036

.. if-------::;,,.....,.OO25

PIN CONFIGURATION

.0026

TO-52
NOTE: SUBSTRATE
is GATE

CT0Q2011

PCOO12U

ORDERING INFORMATION·
TO-52

WAFER

2N5432

2N5432/W

2N5432/0

2N5433

2N5433/W

2N5433/0

2N5434

2N5434/W

2N5434/0

ABSOLUTE MAXIMUM RATINGS
(TA = 25·C unless otherwise noted)

DICE

Gate-Source Voltage ....................................... -25V
Gate-Drain Voltage ......................................... -25V
Gate Current .................................. _............. 100mA
Drain Current ............................................... .400mA
Storage Temperature Range ............ -65·C to + 200·C
Operating Temperature Range ......... - 55·C to + 150·C
Lead Temperature (Soldering, 10sec) .............. + 300·C
Power Dissipation ......................................... 300mW
Derate above 25·C ........................ ;. 2.3mW JOC

'When ordering waferI dice refer to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS

(25·C unless otherwise noted)
2N5432

SYMBOL

PARAMETER

2N5433

2N5434

TEST CONDITIONS

UNIT
MIN MAX MIN MAX MIN MAX

IGSS

Gate Reverse Current

BVGSS

Gate Source Breakdown Voltage

ITA = 150·C

VGs= -15V, Vos=O

-200

-200

-200

pA

-200

-200

-200

nA

200

pA

200

nA

-25

IG=-IIlA, Vos=O

-25
200

IO(off)

Drain Cutoff Current

VGS(off)

Gate-Source Cutoff Voltage

VoS = 5V, 10 = 3nA

-4

lOSS

Saturation Drain Current
(Note I)

VOS = 15V, VGS = 0

150

rOS(On)

Static Drain-Source ON Resistance

VoS(on)

Drain-Source ON Voltage

rds(on)

Drain-Source ON Resistance

CiSS

Common-Source Input Capacitance
(Note 2)

Crss

Common-Source Reverse Transfer
CapaCitance (No.te 2)

ITA = 150·C

VoS= 5V, VGS= -IOV

200

2
VGS = 0, 10 = lOrnA
VGS=O, 10=0

f= 1kHz

Vos=O, VGS= -tOY

f=IMHz

2-44
Note: All typical values have been guaranteed by characterization and are not tested..

-10

-25
200.
200

-3

-9

100

-I

V

-4

30

V
rnA

5

7

10

50

70

100

mV

5

.7

10

ohm

30

30

30

15

15

15

Ohm

pF

2N5432~2N5434

ELECTRICAL CHARACTERISTICS (CONT.)
2N5432
SYMBOL

PARAMETER

2N5433

2N5434

TEST CONDITIONS

UNIT
MIN

MAX MIN MAX. MIN MAX

IcJ

Turn-ON Delay Time (Note 2)

VOO= 1.5V,

4

4

tr

Rise Time (Note 2)

VGS(on) = 0,

1

1

1

toff

Turn-OFF Delay Time (Note 2)

VGS(off)= -12V

6

6

6

tf

Fall Time (Note 2)

10(on) = 10mA

30

30

30

NOTES:

1. Pulse test required, pulsewidth 300"s, duty cycle:S 3%.
2. For design reference only, not 100% tested.

Voo

R _ VOo-Vos(ON)
L -

o
VIN

lo(ONI

~VOUT

o---.._-...j-RG

!-

5O1l

TCOO1811

2-45
Note: All typical values have been guaranteed by characterization and are not tested.

4
ns

;Z·2N5452-2N5454

I

Dual N-Channel JFET
, General· Purpose Amplifier
&'4'

!GENERAL DESCRIPTION

I

FEATURES

\ Matched FET pairs for differential amplifiers. This family
of general purpose FETs iscnaracterized for low and
medium frequency differential amplifier applications requiring low drift and low offset voltage.

•
•
•
•

Low
Low
Low
Low

Offset Voltage
Drift
Capacitance
Qutput Conductance

CHIP TOPOGRAPHY

PIN CONFIGURATION

6037
TO-71

0,

ALL BONO PADS ARE 4 x 4 MIL.
CTOOQ701
PC002501

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Gate-Source or Gate Drain Voltage
(Note 1) .................................................... -50V
Gate Current (Note 1).................................... 50mA
Storage Temperature Range ........... -65°C to +200°C
Operating Temperature Range ........ -55°C to + 150°C
Lead Temperature (Soldering, 10sec) ............. +300°C

ORDERING INFORMATION*
TO-71

WAFER

DICE

2N5452

2N5452/W

2N5452/D

2N5453

2N5453/W

2N5453/D

2N5454

2N5454/W

2N5454/D

·When ordering walerI dice reler to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS

Power Dissipation (TC = 85°C) ....
Derate above 25°C................

BOTH SIDES

250mW
2.9mWrC

500mW
4.3mW/oC

(TA = 25°C unless otherwise noted)
2N5452

SYMBOL

ONE SIDE

2N5453

2N5454

TEST CONDITIONS

PARAMETER

UNIT
MIN MAX MIN MAX MIN MAX

VGS = -30V, VOS = 0

-100

-100

~100

pA

-200

-200

-200

nA

-1

-4.5

V

-0.2

-4.2

IGSS

Gate Reverse Current ITA = 150.C

BVGSS

Gate-Source Breakdown
Voltage

Vos=O, IG= -1/'A

-50

VGS(off)

Gate-Source CutoWVoltage

VOS= 20V, 10=lnA

-1

-4.5

-1

-4.5

VGS

Gate-Source Voltage

Vos = 20V, 10 = 50/'A

-0.2

-4.2

-0.2

-4.2

VGS(f)

'Gate-Source Forward Voltage

VOS =0, IG = lmA

lOSS

·Ssturation Drain Current

VOS = 20V, VGS = 0

0.5

5.0

0.5

5.0

0.5

5.0

1000

3000

1000

3000

1000

3000

2

Common-Source Forward
Qt.

Transconductance

I(Note 2)

I
VOS = 20V, VGS = 0

= 1kHz

f= 100MHz

Common-Source Output

gos

Conductance

Ciss

Common-Source Input
CapaCitance (Note 2)

VOS = 20V, 10 = 200p.A

= 20V,

Crss

Common-Source Reverse
Transler Capacitance (Note 2)

VOS

Cdgo

Drain-Gate CapaCitance (Note 2)

VOG=10V, 15=0

-50

1= 1kHz

1000

-50

2

1000

2
rnA

1000

3.0

3.0

3.0

1.0

1.0

1.0

4.0

4.0

4.0

1.2

1.2

1.2

1.5

1.5

1.5

p.s

VGS = 0
1= lMHz

2-46
Note: All typical values have been .guaranteed by characterization and are not tested.

pF

.U~UIL

2N5452-2N5454
ELECTRICAL CHARACTERISTICS (CO NT.)
2N5452
SYMBOL

PARAMETER

UNIT

en

Equivalent Short Circuit
Input NOise Voltage

VOS = 20V. VGS

NF

Common-Source Spot
Noise Figure (Note 2)

VOS = 20V. VGS = 0
RG= 10MS'!

_"-'-'1

=. 0

f= 1kHz
f = 100Hz

wc

1.0

MAX

MIN

20

0.5
0.95

T' 2S"C to -

MIN

20

Vos = 20V. VGS = 0

Gate-Source Voltage

MAX

0.5
0.95

1.0

0.95

MAX
20

-L!L

0.5

d3

5.0

10.0

15.0

0.8

2.0

0.5

1.0

2.5

Differential Change with
"IVGS1-VGS21 Temperature

mV
Vos = 20V. 10 = 200j.tA

9'91/9'92
19091-9092 1
NOTES:

y'1IZ

1.0

0.4

T =2S'C to
+ 125'C

Transconductance Ratio

0.97

Differential Output Conductance

f= 1kHz

1. Per transistor.
2. For desi9n reference only. not 100% tested.

2-47
Note: All typical values have been 9uaranteed by characterization' and are not tested.

1.0
0.25

0.97

1.0
0.25

0.95

1.0
0.25

Z

!
N
I
N

2N5454

TEST CONDITIONS
MIN

IOSSl/IOSS2 Drain Saturation Current Ratio
IVGS1-VGS2 1

2N5453

N

IJS

Z

:

CII
~

! i~N5457.2N5459

IN-Channel JFET
,.... General Purpose Amplifier/Switch
~

10

Z

PJN CONFIGURATION

CHIP TOPOGRAPHY

ft

5010

T0-92

D(2)
.0013 FULLR
.0017

~1) ~T
• .

o

S

.0025

x~

.0036

.0036

:=

~ ~

~
NOTE: SUBSTRATE
IS GATE

.013

G

PCO01311

CT0Q0321

ABSOLUTE MAXIMUM RATINGS

ORDERING INFORMATION*
TO-92

WAFER

DICE

2N5467

2N5457/W

2N5457/D

2N545B

2N5458/W

2N5458/D

2N5459

2N5459/W

2N5459/D

'When

~rda"ing

(TA = 25°C unless otherwise noted)
Drain-Gate Voltage ........................................... 25V
Drain-Source Voltage ......................................... 25V
Continuous Forward Gate Current.. .................... 10mA
Storage Temperature Range ............ -65°C to + 150°C
Operating Temperature Range ......... -55°C to + 135°C
Lead Temperature (Soldering, 10sec) .............. + 300°C
Power Dissipation ......................................... 310mW
Derate above 25°C ........................ 2.82mWrC

waler / dice reler 10 Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
SYMBOL
BVGSS

PARAMETER

TEST CONDITIONS

Gale-Source Breakdown Voltage

IG - -IOpA, Vos - 0

MIN

TYP

-25

-60

Gale Reverse Currenl

VGS(off)

Gale-Source Cutoff Voltage

2N5458

-0.5
VOS=15V,IO=IOnA

2N5459
VGS

Gale-Source Vollage

-8.0
-2.5

VOS = 15V, 10 = 200pA

-3.5

2N5459

VOS = 15V, 10 = 400pA

-4.5

(Nole I)

2N5459

Forward Transler Admittance

2N5458

VOS = 15V, VGS = 0

2N5457
IYlsl

-7.0

-2.0
VOS -15V, 10 = 100pA

2N5458

VOS -15V, VGS = 0, I = 1kHz

2N5459

-200

-1.0

2N5458

Zero-Gale-Voltage Drain Currenl

V
nA

-6.0

2N5457

2N5457
lOSS

.05

VGS = -15V, VOS- 0, TA -IOO'C
2N5457

UNIT

-1.0

VGS - -15V, VOS = 0
IGSS

MAX

V

V

1.0

3.0

5.0

2.0

6.0

9.0

4.0

9.0

16

1000

3000

5000

1500

4000

5500

2000

4500

6000

mA

,,"S

IYosl

Oulpul Admittance

VOSs 15V, VGS-O, I-1kHz

10

50

Ciss

Inpul Capacitance (Nole 2)

VOS=15V, VGS=O, 1=IMHz

4.5

7.0

""

Crss

Aeverse Transler CapaCitance (Nole 2)

VOS = 15V, VGS = 0, 1= IMHz

1.5

3.0

pF

NF

Noise Figure (Nole 2)

VOS -15V, VGS = 0, RG = IMHz
BW -1Hz, I -1kHz

3.0

dB

NOTES:

I. Pulse lest required. PW S 630ms. duty cycle S 10%
2. For deSign relerence only, nol 100% lesled.

2-48
Nole: All typical values have been guaranleed by characterization and are nol lested.

pF

2N5460-2N5465
P-Channel JFET

Low Noise Amplifier
PIN CONFIGURATION

CHIP TOPOGRAPHY
5503

TO·92

q

II'~;}'='=

H

r-

s

0

.016

---i

NOTE: i1U:~i:ATE
CTOO2111

G

PC003111

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Drain-Gate or Source-Gate Voltage
2N5460 - 2N5462 ................................. -40V
2N5463 - 2N5465 ................................. -60V
Gate Current ................................................. 10mA
Storage Temperature Range ............ -65°C to + 150°C
Operating Temperature Range ......... -55°C to + 135°C
Lead Temperature (Soldering, 10sec) .............. +300°C
Power Dissipation ........................................ :310mW
Derate above 25°C ........................ 2.82mWI"C

ORDERING INFORMATION*
TO-92

WAFER

DICE

2N5460

2N5460/W

2N5460/0

2N5461

2N54611W

2N5461/0

2N5462

2N5462/W· 2N5462/0

2N5463

2N5463/W

2N5463/0

2N5464

2N5464/W

2N5464/0

2N5465

2N5465/W

2N5465/0

'When ordering waler/dice refer to Section to, page to-to

ELECTRICAL CHARACTERISTICS
SYMBOL

(25°C unless otherwise noted)

PARAMETER

TEST CONDITIONS

2N5460, 2N5461 , 2N5462
BVGSS

Gate·Source Breakdown Voltage

2N5463, 2N5464, 2N5465

IG = 101lA, VOS = 0

2N5460, 2N5463
VGS(off)

Gate·Source Cutoff Voltage

2N5461, 2N5464

VOS= -15V, 10= 1.011A

2N5462, 2N5465
2N5460, 2N5461, 2N5462
Gate Reverse Current
IGSS
ITA = 100°C

VOs=O

2N5463, 2N5464, 2N5465
2N5460, 2N5461 , 2N5462
2N5463, 2N5464, 2N5465

Zero·Gate Voltage Drain Current

gts

Gate-Source Voltage

Forward Transadmittance

V

0.75

6.0

1.0

7.5

1.8

9.0

IIA

-1.0

rnA

-2.0

-9.0

-4.0

-16

2N5460, 2N5463
2N5461, 2N5464

0.5

4.0

0.8

4.5

2N5462, 2N5465

10 = -O.4mA

1.5

6.0

2N5460, 2N5463

1000

4000

2N5461, 2N5464

1500

5000

2N5462, 2N5465

2000

6000

VOS= -15V

1= 1.0kHz

Output Admittance
Input Capacitance (Note 1)

Crss
NF

Reverse Transler Capacitance (Note 1)

1= lMHz

Common·Source Noise Figure (Note 1)

en

Equivalent Short·Circuit Input
Noise Voltage (Note 1)

I -100Hz
BW= 1.0Hz
RG=I.0MU

VGS= OV

NOTE 1: For deSIgn reference only, not 100% tested.

2-49
Note: All typi"al values have been guaranteed by characterization and are not tested.

V

5.0
1.0
1.0
_5.0

VGS=O
10=0.lmA
10= -0.2mA

VOS = -15V

UNIT

5.0

Ciss

gos

MAX

VGS= 30V
VGS-20V
VGS= 30V

2N5461, 2N5464
2N5462, 2N5465

VGS

TYP

40
60

VGs=20V

2N5460, 2N5463
loss

MIN

75
5.0
1.0

7
2.0

1.0

2.5

60

115

nA

V

IlS
IlS
pF
pF
DB
nV/

.!Hz

II

CD

....CD
10

Z

i
z

(II

2N5484-2N5486

N-Channel ,JFET
'
High Frequency Amplifier
FEATURES

CHIP TOPOGRAPHY

Up. to 400MHz Operation
Economy Packaging
eras < 1.0pF

.0035
.0025 FULL~

PIN CONFIGURATION

.017

•

•

•

5000

T ~. ~:0035

.0025 x .0035
.0025

•_

~ 0(2)1

TO-92

.

I~;[r

~=
~ NOTE: SUBSTRATE
.
IS GATE

q

.017
CTOO221 I

rl

ABSOLUTE MAXIMUM RATINGS
o

S

(TA = 25°C unless otherwise specified)
Drain-Gate Voltage ........................................... 25V
Source Gate Voltage ......................................... 25V
Drain Current ................................................. 30mA
Forward Gate Current ...................................... 10mA
Storage Temperature Range ............ -65°C to + 150°C
Operating Temperature Range ......... -·55°C to + 135°C
Lead Temperature (Soldering. 10sec) .............. + 300°C
Power Dissipation ......................................... 310mW
Derate above 25°C ........................ 2.82mW fOC

Q

PCO0340t

ORDERING INFORMATION*
TO·92

WAFER

DICE

2N5484

2N5484/W

2N5484/D

2N5485

2N5485/W

2N5485/D

2N5486

2N5486/W

2N5486/D

'When ordering waler/dice reler to Section 10. page 10-1.

ELECTRICAL CHARACTERISTICS

(25°C unless otherwise noted)
2N5484

SYMBOL

PARAMETER

2N5485

2N5486

TEST CONDITIONS

UNIT
MIN MAX MIN MAX MIN MAX
-1.0

-1.0

-1.0

-200

-200

-200

IGSS

Gate Reverse Current ITA = l00.C

VGS = -20V. Vos = 0

BVGSS

Gate-Source Breakdown Voltage

IG = -lIlA. VOS - 0

-25

VGS(off)

Gate-Source Cutoff Voltage

VOS - 15V. 10 - 10nA

-0.3 -3.0 -0.5 -4.0 -2.0 -6.0

VOS = 15V. VGS = 0 (Note 1)

loSS

Satliration Drain Current

gts

COmmon-Source Forward
Transconductance

gos

Common-Source Output
Conductance

Re(yta)

Common-Source Forward
Transconductance (Note 2)

Re(yos)

Common-Source Output
Conductance (Note 2)

Re(yis)

Common-Source Input
Conductance (Note 2)

Ciss

Common-Source Input
CapaCitance (Note 2)

1:0

5.0

4.0

nA

-25

-25
10

8.0

20

V
rnA

3000 6000 3500 7000 4000 8000
1= 1kHz
50

VoS=15V. VGS=O

1= 100MHz
1=400MHz
1=,100MHz
I -400MHz
l-l00MHz
1=400MHz

75

60

2500
3000

3500

fJS

75
100

100

100
1000

1000

5.0

5.0

5.0

1.0

1.0

1.0

2.0

2.0

2.0

Common-Source Reverse
Crss

Transler Capacitance (Note 2).

Coss

Common-Source Output
Capacitance (Note 2)

1= lMHz

2-50
Note: All typical velues have been guaranteed by characterization and are not tested.

pF

2N5484-2N5486
ELECTRICAL CHARACTERISTICS (CO NT.)
2N5484
SYMBOL

PARAMETER

2N5485

2N5486
UNIT

TEST CONDITIONS
MIN MAX MIN MAX MIN MAX
vos = 15V, vGS = 0, RG = lM.f!

f= 1kHz

2.5

VOS = 15V, Vo = lmA,
RG= lk.f!
NF

Noise Figure
(Note 2)

f = 100MHz
VOS = 15V, 10 = 4mA,
RG= lk.f!

f = 400MHz

VOS = 15V, 10 = lmA
Gps

NOTES:

Common-Source Power Gain
(Note 2)

16
f = 100MHz

VOS = 15V, 10 = 4mA

1. Pulse test required. Pulse width = 300;. 30V
Crss 0.75pF (Typical)

=

CHIP TOPOGRAPHY

TO·71
TO·78

4000

1-- --1
023

l

CATHODE"

T~
~:~~~~~~~s .0040 x.0040
.017
---.l
~~~~~~!CES ~qQ~DIA
.0030

.0030

.0040

j

ANODEM1

.
CT00331I

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Diode Reverse Voltage ...................................... 30V
Diode to Diode Voltage ....................•............... ±50V
Forward Current ............................................. 20mA
Reverse Current ............................................ 100!-IA
Storage Temperature Range ............ -65°C to + 200°C
Operating Temperature Range ......... -55°C to + 150°C
Lead Temperature (Soldering, 10sec) .............. + 300°C
Power Dissipation ........................ ; ................ 300mW
Derate above 25°C .......................... 2.4mWfOC

PCQ0211 I

ORDERING INFORMATION*

'When ordering wafer/dice refer to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS

(@ 25°C unless otherwise noted)

10100, 10101
SYMBOL

TEST CONDITIONS

PARAMETER

UNIT
MIN TYP MAX

VF

Forward Voltage Drop

IF = lOrnA

0.8

BVR

Reverse Breakdown Voltage

IR=lpA

30

IR

Reverse Leakage Current

VR= 1V

1.1

V
0.1
2.0

I
IiR,-IR2 1
Crss

TA = 125°C

VR = 10V

Differential Leakage Current
Total Reverse Capacitance

VR=10V, f=lMHz (Note 1)

NOTE 1: For design reference only. not 100% tested.

2-74
Note: All typical values have been guaranteed by characterization and are not tested;

V

0.75

pA
10
10

nA

3

pA

1

pF

ID100, ID101
TYPICAL PERFORMANCE CHARACTERISTICS
REVERSE CURRENT vs. VOLTAGE
1.0

11

0.9

."

10

.

_

CAPACITANCE

12

9

.!: •
~

0.8
0.7
0.6

L

--

FORWARD CURRENT

.!'-lmA~

lDO"A
lOjJA •

r-- r-- -- r--

0.3
0.2

/"

hA

0.1

~~

o

10

15

20

25

VOLTAGE

10mA~1I

-

i -t-

VS.

0.4

/1-'"

,/

o

VOLTAGE

0.5

./

t---

f-- f--

"-

VS.

30

00

10

15

VRIVI

25

20

VR (VI

OPOO1811

OP001911

2-75
Note: All typical values have been guaranteed by characterization and are not tested.

30

100 nA

r--r-- - .

"

•

H

o~--'-1.......L..-'.:Jol';-.5-'--'---'-~1';;-.0-'--'--"'-:".4
V F {VI
OPOO201 I

....a
o

2_'
'

1'1100, IT101

P-Channel JFET Switch

8
t GENERAL DESCRIPTION

FEATURES

This P-channel JFET has been designed to directly
interface with TTL logic, thus eliminating the need for costly
drivers, in analog gate circllitry. Bipolar inputs of ±15V can
be switched. The FET is OFF for hi level inputs (+ 5V or
+ 15V) and ON for low level inputs « 0.5 V for
IT100, < 1.5V for 1T101).
'

PIN CONFIGURATION

•
•

Interfaces Directly w/TTL Logic Elements
rOS(on) < 7Sq for SV Logic Drive

•

IO(Ciff)

< 100pA

CHIP TOPOGRAPHY
5514

T()'18

o

G,C

*~---,028 - - - - - I

s

1....

I

PCO0011I

NOTE: SUBSTRATE IS GATE.

CT003411

ORDERING INFORMATION*
TO-18

WAFER

DICE

1T100

IT100/W

1T100/D

1T101

IT10l/W

IT10l/D

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Gate-Source Voltage ......................................... 35V
Gate-Drain Voltage ........................................... 35V
Gate Current ................................................. 50mA
Storage Temperature Range ............ -65°C to +200°C
Operating Temperature Range ......... -55°C to + 150°C
Lead Temperature (Soldering, 10sec) .............. + 300°C
Power Dissipation ......................................... 300mW
Derate above 25°C ......... ; ................ 2.4mW 1°C

'When ordering wafer/dice refer to Section 10, page 10-1,

ELECTRICAL CHARACTERISTICS

(25°C unless otherwise noted)
IT100

SYMBOL

PARAMETER

UNIT
MIN

loss
Vp
BVGSS
IGSS
g15
gos
10(011)

rOS(on)
Ciss
Crss

Drain Current
Pinch Off Voltage
Gate-Source Breakdown Voltage
Gate Reverse Current
Transconductance
Output Conductance
Drain (OFF) Leakage
Drain·Source "ON" Resistance
Input CapaCitance
Reverse Transfer CapaCitance

IT101

TEST CONDITIONS
VGS=O, VDS=-15V
10 = InA, VOS = -15V
IG=lpA, VOs=O
VGS = 20V, VOS = 0

-10
2
35

MAX MIN
-20
4.5

VOS = -10V, VGS = 15V
VGS - 0, VOS - -0, tV
VOG - -20V, VGS - 0 (Note 1)
VOG- -10V, IS-O (Note 1)

NOTE 1: For design reference only, not 100% tested.

2-76
Note: All typical values have been guaranteed by characterization and are not tested.

4

mA
10
V

35
200

8

VGS = 0, VOS'" -15V

MAX

200

pA

1
-100
60
35
12

mS

8

1
-100
75
35
12

pA

n
pF

IT120, IT122
Dual NPN
General Purpose Amplifier
FEATURES
•
•
•
•

CHIP TOPOGRAPHY

High hFE at Low Current
Low Output Capacitance
Good Matching
Tight VBE Tracking

4003
.0045 x .0045
.0035

.0035

·j:---C-O-LL-EC-T-O-RII-,-b. . .=tii;i....,...,,..,..,,=c--ISOLATION
COLLECTOR

PIN CONFIGURATION

/12 TYP 2 PLACES
.0045 x .0045
.0035
.0035
BASE,2 TVP 2 PLACES

.025

I

TO-71
TO-78

~---.,.c..,<--"<-"""
BAse,,1

:~~~ DIAMETER
EMITTER.2
.0040
TYP 2 PLACES .0030

EMITTERlf1

DIAMETER
CTOO3511

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Collector-Base Voltage (Note 1) .......................... 45V
Collector-Emitter Voltage (Note 1) ........................ 45V
Emitter Base Voltage (Notes 1 and 2) .................... 7V
Collector Current (Note 1) ................................ 50mA
Collector-Collector Voltage .................................. 60V
,Storage Temperature Range ............ -65°C to +200°C
Operating Temperatur.e Range ......... -55°C to + 150°C
Lead Temperature (Soldering. 10sec) .............. + 300°C

PCQOO81 I

ORDERING INFORMATION*
TO-78

TO-71

WAFER

DICE

IT120

IT120-T071

IT120/W

IT120/0

TO-78

IT121

IT121-T071

IT121/W

IT121/0

IT122

IT122-T071

IT122/W

IT122/0

ONE
SIDE

PARAMETER

BOTH
SIDES

(25°C unless otherwise noted)
1T120A

SYMBOL

ONE
SIDE

Power Dissipation ........ 250mW
500mW
200mW
400mW
Derate Above
25°C ...................... 1.7mWfOC 3.3mW/oC 1.3mW/oC 2.7mW/oC

'When ordering wafer/dice reler to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS

TO-71

BOTH
SIDES

1T120

IT121

IT122

TEST CONDITIONS

UNIT
MIN MAX MIN MAX MIN MAX MIN MAX

Ie = 101lA, VCE = 5.0V

200

200

80

80

IC = 1.0mA, VCE

225

225

100

100

hFE

DC Current Gain

VSE(ON)

Emitter-Base On Voltage

IC = 101lA, VCE = 5.0V

0.7

0.7

0.7

0.7

VCE(SAT)

Collector Saturation Voltage

IC = 0.5mA, IS = 0.05mA

0.5

0.5

0.5

0.5

1.0

1.0

1.0

1.0

nA

=

5.0V

75

ITA = -55·C

,ICSO

COllector Cutoff Current
ITA = + 150·C

IE=O, VCB= 45V

75

30

30
V

10

10

10

10

/lA

lEBO

Emitter Cutoff Current

IC = 0, VEB = 5.0V

1.0

1.0

1.0

1.0

nA

Cobo

Output Capacitance

IE =0,
VCB =5.0V

2.0

2.0

2.0

2.0

Cte

Emitter Transition
Capacitance

IC=O,
VEB =0.5V

2.5

2.5

2.5

2.5

CC1,C2

Collector to Collector
Capacitance

Vee=O

4.0

4.0

4.0

4.0

IC"C2

COllector to Collector
Leakage Current

Vee = ±60V (Note 3)

10

10

10

10

1=IMHz
(Note 3)

2-77
Note: All typical values have been guaranteed by characterization and are not tested.

pF

nA

2

's

IT120,lr1,22

!: ELECTRICAL cHARACTERISTICS (CONT.)

i

E

1T120A
SYMBOL

PARAMETER

1T120

IT121

IT122
UNIT

TEST CONDITIONS
MIN MAX MIN MAX MIN MAX MIN MAX

VCEO(SUSn

Collector to Emitter
Sustaining Voltage

IC ~ 1,OmA, IB = 0

GBW

Current Gain Bandwidth
Product (Note 3)

Ic
Ic

IVBE1-VBE2 i

Base Emitter Voltage
Differential, .

IIB1-IB21

Base Current Differential

A(VBE1- VBE2)
Ll.T

Base-Emitter

vOltage

Differential

Change with Temperature

=10llA, VCE = 5V
=lmA, VCE = 5V

45

45

45

45

10

10
220

7
180

7

220

V
MHz

180

1

2

3

5

mV

2,5

5

25

25

nA

3

5

10

20

p'vrc

Ic = 10llA, VCE - 5,OV

(Note,3)
TA - -55·C to + 125·C
IC - 10llA, VCE - 5,OV

NOTES: 1, Per transistor.
2. The reverse base-to-emitter voltage must never exceed 7.0 volts and the reverse base-to-emitter current must never exceed 101lA.
3. For deSign reference only, not 100% tested.

2-78
Note: All typical values have been guaranteed by characterization and are not tested.

IT124
Dual Super-Beta NPN
General Purpose Amplifier
FEATURES
•
•
•
•

CHIP TOPOGRAPHY
4003

Very High Gain
Low Output Capacitance
Tight VBE Matching
High GBW

.0045 x .0045
.0035
.0035

-,

COLLECTOR '.1

i:iiiilii=;1i-:::::-:-=:::=-'SOLATION
COLLECTOR
1#2 TYP 2 PLACES
_~ x .0045
.0035
.0035

'l

025

PIN CONFIGURATION

BASE"2 TYP 2 PLACES

~~-

TO-78

DIAMETER

'--- EMITTER'2

.0040

TYP 2 PLACES .0030
DIAMETER
CT003611

ABSOLUTE MAXIMUM RATINGS

ORDERING INFORMATION*

(TA = 25°C unless otherwise noted)
Collector-Base Voltage (Note 1) ............................ 2V
Collector-Emitter Voltage (Note 1) .......................... 2V
Emitter-Base Voltage (Notes 1 and 2) ..................... 7V
Collector-Current (Note 1) ................................ 10mA
Collector-Collector Voltage ................................. 100V
Storage Temperature Range ............ -65°C to + 200°C
Operating Temperature Range ......... -55°C to + 150°C
Lead Temperature (Soldering, 10sec) .............. + 300°C

'When ordering wafer/dice refer to Section 10, page 10-1.

Power Dissipation ...•.................
Derate above 25°C ............... .

E,

e,

c,
PCOOO31 I

TQ.78

ELECTRICAL CHARACTERISTICS

@

ONE SIDE

BOTH SIDES

300mW
2.4mW/oC

500mW
4.0mW/oC

25°C (unless otherwise noted)
LIMITS

SYMBOL

PARAMETER

UNIT

TEST CONDITIONS
MIN MAX
ISOO

Ic = liJA, VCE = IV
hFE

DC Current Gain

IS00

VSE(ON)

Emitter-Base "ON" Voltage

VCE(SAT)

Collector Saturation Voltage

ICBO

Collector Cutoff Current

I
I

TA= -SS·C

600

IC = 10iJA, VCE = IV

0.7
IC = lmA, IB = O.lmA
TA =

+ ISO·C

O.S
100

IE=O, VCB=IV

lEBO

Emitter Cutoff Current

IC = 0, VEB = SV

Cabo

Output Capacitance (Note '3)

IE-O, VCB-IV

Cte'

Emitter Transition Capacitance (Note 3)

IC = 0, VEB = O.SV

CC1 C2

Coilector to Collector Capacitance (Note 3)

VCC=O

IC1C2

Collector to Collector Leakage Current

VCC - ±SOV

Current Gain Bandwidth Product (Note 3)

tv
Ic = 100iJA, VCE = tv

NF

Narrow Band Noise Figure (Note 3)

Ic = IOiJA, VCE = 3V,
f= 1kHz. RG = 10kf!
BW = 200Hz

BVCBO

Collector-Base Breakdown Voltage

BVEBO (Note 2)
VCEO(SUST)

Emitter-Base Breakdown Voltage

IC - 10iJA. IE - 0
IE = 10iJA, IC = 0

7

Collector-Emitter Sustaining Voltage

Ic=lrnA.IB=O

2

IC = 10iJA, VCE =

GBW

'2-79
Note: All typical values have been guaranteed by characterization and are not tested.

I

I

V
pA

100

nA

100

pA

O.B
f= IMHz

1.0

pF

O.B
2S0

pA

10
MHz

100
3

dB

2
V

:

11:124

e MATCHING CHARACTERISTICS

@'

25°C (unless otherwise noted)
LIMITS

SYMBOL

PARAMETER
'.

TEST CONDITIONS
.'

UNIT
TYP MAX

;

IVBE1-VBE2 1

Base Emitter Voltage Differential

IC - 101lA. VCE = 1V

2

5

mV

al(VBE1-VBE?!lt aT

Base Emitter Voltage Differential Change with
Temperature (Note 3)
,

Ic = lallA. VCE = tV
T - -55°C to + 125°C

5

15

p.VI'C

IIB1-IB2 11

Base Current Oifferential

Tc-l01lA. VCE -lV

.6

nA

NOTES:

1. Per transistor..
.
2. The reverse base-to-emitle( voltage must never exceed 7.0 volts and the reverse base-to-emitter current must never exceed lallA.
3. For design releren~e only. not 100% tested.

2,.80

Note: All typical values have 1!een guaranteed by eharacteri:zation and are not tested,

IT126-IT129
Dual NPN
General Purpose Amplifier
FEATURES
•
•
•
•
•

CHIP TOPOGRAPHY
4001

High Gain at Low Current
Low Output Capacitance
Tight Ie Match
Tight VBE Tracking
Dielectrically Isolated Matched Pairs for
Differential Amplifiers

EMln.eR
.0029 )( _.0029_
.0039
.0039
TYP 2 PLACES

PIN CONFIGURATION

BASE
.0030 x -:0030
.0040
.0040
TYP 2 PLACES

EMITTER
BASE

TO·71
TO·78

CTOO371 I

ABSOLUTE MAXIMUM RATINGS
(TA = 25'C unless otherwise specified)
Collector-Base Voltage (Note 1)
IT126, IT127 ........................................... 60V
IT128 .................................................... 55V
IT129 .........................................•.......... 45V

COllect~+;~~:tt~l ~~~~~~~.. ~~~.t~ ..1.~ ........................ 60V
IT128 ..................................................... 55V
IT129 .................................................... 45V
Emitter-Base Voltage (Notes 1 and 2) ................... 7.0V
Collector Current (Note 1) ............................... 1OOmA
Collector-Collector Voltage .................................. 70V
Storage Temperature Range ............ -65'C to + 175'C
Operating Temperature Range ......... -55'C to + 175'C
Lead Temperature (Soldering. 10sec) .............. +300'C

ORDERING INFORMATION*
T078

1°-71

WAFER

DICE

IT126

IT126-T071

IT126/W

IT126/0

IT127

IT127-T071

IT127/W

IT127/0

IT128

IT128-T071

IT128/W

1T128/0

IT129

IT129-T071

IT129/W

1T129/0

T071

PARAMETER

BOTH
SIDES

250mW
1.7
mW/'C

500mW
3.3
mW/'C

IT127

IT128

IT129

TEST CONDITIONS
Ic = 10/'A, VCE = 5V
Ic = LOrnA, VCE = 5V
Ic = lOrnA, VCE = SV
IC = SOmA, VCE = SV
Ic = lmA. VCE = SV
IC = lOrnA, Vce = SV
Ic - SOmA. VCE - SV
IC = lOrnA, Ie = lmA
IC - SOmA, Ie - SmA
Ie = 0, Vce - 4SV, 30V'

hFE

DC Current Gain

VeE(on)

ITA = -SS'C
Emitter·Base On Voltage

VCE(sat)

Collector Saturation Voltage

Iceo

Collector Cutoff Current
ITA - + lS0·C
Emitter Cutoff Current
Ic = 0, VEe = SV

IEeo

ONE
SIDE

(25'C unless otherwise noted)
IT126

SYMBOL

BOTH
SIDES

Total Dissipation at 25'C...... 200mW' 400mW
1.3
2.7
Derating Factor ................... mW/'C mW/'C

'When ordering waferldice refer to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS

ONE
SIDE

Power Dissipation

T078

2-Bt
Note: All typical values have been guaranteed by characterization and are not tested.

UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
150
150
100
70
200 800 200 800 ISO 800 100
170
lIS
230
230
100
100
7S
SO
7S
7S
60
40
0.9
0.9
0.9
0.9
1.0
1.0
1.0
1.0
0.3
0.3
0.3
0.3
1.0
1.0
1.0
1.0
0.1
0.1
0.1
0.1'
0.1
0.1
0.1
0.1'
0.1
0.1
0.1
0.1

V

nA
/'A
nA

r:.
r.-

...~ IT12S-IT129·

.

...t:

···.D~OlL

I,i

.&'<1

'f",1'

ELECTRICAL· CHARACTERISTICS (CONT.)·
IT126
PARAM~T~R

SYMBOL

IT127

IT128

IT129
UNIT

TEST CONDITIONS
MIN MAX MIN MAX MIN MAX MIN MAX

Cobo

output Capacitance (Note 3)

Ie = 0, vcs = 20V

BVC1 C2

Collector to Collector Breakdown
Voltage

IC - ±lpA

Collector to Emitter Sustaining
. Voltage

3

3

3

3

±100

±100

±IQO

?;1?0

Ic=lmA,ls=O

60

60

55

45

BVCBO

Collector Base Breakdown
Voltage

IC = 10pA, Ie = 0

60

60

55

45

BVESO

Emitter Base Breakdown Voltage

IE = 10pA, Ic = 0

7

7

7

7

VceO(sust)

pF

V

MATCHING CHARACTERISTICS
IT126
SYM.BOL

PARAMETER

IT127

IT128

IT129
UNIT

TEST CONDITIONS
MIN MAX MIN MAX MIN MAX MIN MAX

IVSE1-VSE21

Base Emitter Voltage Differential

.1(IVsel·VSE21)

Base Emitter Voltage Differential
Change with Temperature (Note 3)

AT
Ils1-1621

Base Current Differential

IC -lmA, VCE = 5V

1

2

3

5

mV

IC = lmA, VCE = 5V
TA - _55°C to + 125°C

3

5

10

20

,.VfOC

= 5V

2.5

5

10

20

nA

Ic = lmA, VCE - 5V

0.25

0.5

1.0

2.0

pA

Ic = 10pA, VCE

NOTES: 1. Per tnsnsistor.
2. The reverse base-to-emitter voltage must never exceed 7.0 volts and the reverse base-to-emitter current must never exceed 10pA.

3. For design reference only, not 100% tested.

2-132
Note: AU typical values have been guaranteed by characterization and are not tested.

IT130-IT132
Dual PNP
General Purpose Amplifier
FEATURES
•
•
•
•

CHIP TOPOGRAPHY

High hFE at Low Current
Low Output Capacitance
Tight IB Match
Tight VBE Tracking

4503

.0045

x

.0035

.0045

.0035

'!:--------i-_.=iitl--=:c;-;:="""'SOLATION
CgLlECTOR'l f..1
COLLECTOR

PIN CONFIGURATIONS

.2 TYP 2 PLACES

::~

.Of5

TO·71
TO·78

•

x

:~~~

BASE '2 TVP 2 PLACES

~~~

BASE 11

DIAMETER

EMITTER 112
.0040
TVP 2 PLACES .0030'

EMITTER.1

DIAMETER
CTO03811

ABSOLUTE MAXIMUM RATINGS
E,

B,

(TA = 25°C unless otherwise specified)
Collector-Base Voltage (Note 1) .......................... 45V
Collector-Emitter Voltage (Note 1) ........................ 45V
Emitter Base Voltage (Notes 1 and 2) .................... 7V
Collector Current (Note 1) ................................ 50mA
Collector-Collector Voltage .................................. 60V
Storage Temperature Range ............ -65°C to + 175°C
Operating Temperature Range ......... -55°C to + 175°C
lead Temperature (Soldering. 10sec) .............. + 300°C
To-71
T0-78

c,
PC00241 I

ORDERING INFORMATION*
TO-78

TO-71

IT130A

1T130A-T071

WAFER

DICE

IT130AlW

IT130A/D

IT130

IT130-T071

IT130/W

IT130/D

IT131

IT131-T071

IT131/W

IT131/D

IT132

IT132-T071

IT132/W

IT132/D

PARAMETER

BOTH

ONE
SIDE

SIDES

(25°C unless otherwise noted)
IT130A

SYMBOL

SIDES

200mW
400mW
250mW
500mW
Power Dissipation ........ 1.3mW/oC 2.7mWrC 1.7mW/oC 3.3mW/oC

·When ordering wafer/dice refer to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS

BOTH

ONE
SIDE

IT130

1T131

IT132

TEST CONDITIONS

UNIT
MIN MAX MIN MAX MIN MAX MIN MAX

Ic= 10llA, VCE = 5.0V

200

200

80

80

IC = 1.0mA, VCE = 5.0V

225

225

100

100

= 5.0V
= 5.0V

75

hFE

DC Current Gain

VBE(ON)

Emitter·Base On Voltage

IC - 10llA, VCE

VCE(SAT)

Collector Saturation Voltage

IC - 0.5mA, IB = 0.05mA

ICBO

Collector Cutoff Current

ITA = -55·C

ITA =
lEBO
Cob (Note 3)

+ 150·C

IC -101lA, VCE

75

30

30

0.7

0.7

0.7

0.7

0.5

0.5

0.5

0.5

-1.0

-1.0

-1.0

-1.0

nA

-10

-10

-10

-10

IlA

-1.0

-1.0

-1.0

-1.0

nA

= 5.0V

2.0

2.0

2.0

2.0

IE = 0, VCB = 45V

Emitter Cutoff Current

IC - 0, VEB = 5.0V

Output CapacHance

IE = 0, VeB

Gte (Note 3)

Emitter Transition Capacitance

Ic = 0, VEB = 0.5V

2.5

2.5

2.5

2.5

CC1-C2 (Note 3)

Collector to Collector
Capacitance

Vee=O

4.0

4.0

4.0

4.0

IC1-C2

Collector to Collector Leakage
Current

Vee - ±60V

10

10

10

10

VCEO(SUST)

Collector to Emitter Sustaining
Voltage

IC = 1.0mA, IB = 0

GBW

Current Gain
Bandwidth Product (Note 3)

IVBE1-VBE2'

Base Emitter Voltage
Differential

-45

-45

-45

-45

IC = 10llA, VCE = 5V

5

5

4

4

IC = 1mA, VCE = 5V

110

110

90

90

Ic = 10llA, VCE = 5.0V

2-83
Note: All typical values have been guaranteed by characterization arfd' are not tested.

1

2

3

V

pF

nA
V
MHz

5

mV

II

IT130A
PARAMETER

SYMBOL

1T130

IT131

IT132

TEST CONDITIONS

UNIT
MIN MAX MIN MAX MIN MAX MIN MAX

IIB1-IB21

Base Current Differential

IC = 101lA. VCE ~ 5.0V

a(VBE,-VBE2)1 aT

Base-Emitter Voltage Differential
Change with Temperature
(Note 3)

TA = _55°C to + 125°C
Ic = 101lA. VCE = 5.0V

.

NOTES: 1. Per transistor.

2.5

5

25

25

nA

3

5

1Ct

20

,.VloC

,
2. The reverse base-to-emitter voltage must never exceed 7.0V. and the reverse base-to-emitter current must never exceed 101lA.
3. For design reference only. not 100% tested.

2~

Note: All

typic81

values have been guaranteed by characterization and are not tested.

IT136-IT139
Dual PNP
General Purpose Amplifier
FEATURES
•
•
•
•
•

CHIP TOPOGRAPHY

High Gain at Low Current
Low Output Capacitance
Tight Is Match
Tight VSE Tracking
Dielectrically Isolated Matched Pairs for
Differential Amplifiers

4501

R

1- -1
033

EMITTER .0029 ,

PIN CONFIGURATION

EMITTER

.0039

TVP 2 PLACES

.9!l~

I
-L

TO·71
TO·78

.0029

.0039

.023

BASE .

.0040

COLLECTOR

x

-:.9_0~

.0040

TVP 2 PLACES

.09~.~)( _:.~q~

BASE

.0045
.0044
TYP 2 PLACES
CTQ03911

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Coliector·Base Voltage (Note 1)
IT136, IT137 ........................................... 60V
IT138 __ ........ .- ____ ............. __ ... ______ .... __ ... ____ 55V
E.

COllect~~.~~itt~'r' 'v~it~g~" iN~t~' '1'j -- .... -- -- -- --. -- .. -- --. 45V

c,

B.

1T136, IT137.. ________________________________________ . 60V
IT 138 .... ____ . ____ ...... __ ... ______________ ........... __ 55V
IT139 __ ... __ ...... ____ ....... ______ . ________ .......... __ . 45V
Emitter Base Voltage (Notes 1 and 2). ____ .. __ . ______ . __ .7V
Collector Current (Note 1). __ . __ . ____ . ______________ . ____ 100mA
Coliector·Coliector Voltage .. __ . __ ... __ .... ______ .......... __ 70V
Storage Temperature Range __ . ______ ' __ -65°C to + 175°C
Operating Temperature Range ______ . __ -55°C to +175°C
Lead Temperature (Soldering, 10sec) ____ ..... ____ . + 300°C

PC0024U

ORDERING INFORMATION*
TO-78

TO-71

WAFER

DICE

IT136

IT136·T071

IT136/W

IT136/0

IT137

IT137·T071

IT137/W

IT137/0

IT138

IT138·T071

IT138/W

IT138/0

IT139

IT139·T071

IT139/W

IT139/0

TO-71

ONE
SIDE

'When ordering wafer I dice refer to Section 10, page 10-1.

TO·78

ONE

BOTH
SIDES

BOTH
SIDES

SIDE

Power Dissipation ...... __ 200mW
400mW
250mW
500mW
Derate above 25'C ... 1.3mWrC 2.7mW/'C 1.7mW/'C 3.3mWI'C

ELECTRICAL CHARACTERISTICS

(@ 25°C unless otherwise noted)
1T136

SYMSOL

PARAMETER

1T137

IT138

IT139

TEST CONDITIONS

UNIT
MIN MAX MIN MAX MIN MAX MIN MAX

hFE

DC Current Gain
ITA = 55'C

VSE(on)
VCE(sat)

Emitter·Base On Voltage
Collector Saturation Voltage

Ic = 10"A, VCE = 5V

150

Ic = 1.0mA, VCE = 5V

150

= lOrnA,

VCE = 5V

125

Ie = 50mA, VCE = 5V

65

Ic = lmA, VCE = 5V

75

Ic

100

150

800

150

BOO

125

100

70
BOO

70

BO

50

60

40

25

75

60

BOO

40

IC = lOrnA, VCE = 5V

.9

.9

.9

.9

IC = SOmA, VCE = SV

1.0

1.0

1.0

1.0

IC=lmA,IS=·lmA

.3
.6

.3
.6

.3

.3
.6

IC = lOrnA, Is = lmA

2-85
Note: All typical values have been guaranteed by characterization and are. not tested.

.6

V

r:.
r.-

IT136·IT139 ,:
ELECTRICAL CHARACTERISTICS (CO NT.)
IT136
SYMBOL

PARAMETER

IT137

IT138

IT139

TEST CONDITIONS

UNIT
MIN MAX MIN MAX MIN MAX MIN MAX

ICBO

Collector Cutoff Current

lEBO

ITA -' + 150°C
Emitter Cutoff Current

IC = 0, VEB = 5V ,

Cobo

Output Capacitance (Note 3)

IE - 0, VCB - 20V, f -1MHz

BVc,C2

Collector to Collector
Breakdown Voltage

le=±1p.A

VeEO(sust)

Collector to Emit,ter
Sustaining Voltage

BVeBO

Collector Base Breakdown
Voltage

BVEBO
1VBE,-VBE21

0.1

0.1

0.1

0.1"

nA

0.1

0.1

0.1

0.1"

p.A

0.1

0.1

0.1

0.1

nA

3

3

3

3

pF

±100

±100

±100

±100

le=1mA,IB=0

60

60

55

45

Ie = 10p.A, IE = 0

60

60

55

45

Emitter' Base Breakdown
Voltage

IE = 10p.A, Ie = 0

7

7

7

7

Base Emitter Voltage
Differential

Ie = 1mA, VeE = 5V

1

2

3

5

mV

Ic = 1mA, VeE = 5V
TA = _55°C to + 125°C

3

5

10

20

IlV/oC

Base Emitter Voltage Differential
~1(VBE,-VBE2~/~T Change with Temperature
(Note 3) .
,
1IB,-1821

IE'= 0, VCB = 45V, 30V"

Base Current Differential

V

Ie = 10p.A, VeE = 5V

2.5

5

10

20

nA

Ie = 1mA, VeE = 5V

.25

.5

1.0

2.0

p.A

NOTES: 1. Per transistor.
2. The reverse base-to-emitter voltage must never exceed 7.0 volts and the reverse base-to-emitter current must never exceed 10p.A.
3. For design reference only, not 100% tested.

2-86
Note: All typical values have been guaranteed by characterization and' are not tested.

IT500-IT505
Dual Cascoded N-Channel JFET
General Purpose Amplifier
GENERAL DESCRIPTION

FEATURES

A low noise, low leakage FET that employs a cascode
structure to accomplish very low IG at high voltage levels,
while giving high transconductance and very ,high common,
mode rejection ratio.

•

CMRR

•
•
•

IG < 5pA @ 50VDG
Crss < O.5pF
gos > .025/lB

PIN CONFIGURATION

> 120dB

CHIP TOPOGRAPHY
6028

TO·71
low profile
BODY
.00301A

DRAIN 1

-T' ~.I~J·003X'003
ii~I

~~~SOURCE1

~~ '003 ~2~~'iiJ1Ij

003

DRAIN 2
003 x

G,

0,

/11

111111'

033 003
x

~.-r--.J ~~; ~

~

'\

SOURCE 2
.003)( .003

s,

CT00411i

PCOO261 I

ABSOLUTE MAXIMUM RATINGS
(TA ':' 25·C unless otherwise specified)
Drain-Source and Drain-Gate
Voltag~s (Note 1) .................... ; ........................ 60V
Drain Current (Note 1) .................................... 50mA
Gate-Gate Voltage ........................................... ±60V
Storage Temperature .... , ................. -65·C to +200·C
Operating Temperature ................... - 55·C to + 150·C
Lead Temperature (Soldering, 10sec) .............. + 300·C
ONE SIDE
BOTH SIDES

SCHEMATIC DIAGRAM

~~-----+--i-CASE
08000311

Power Dissipation (Note 3) ........
Derate above 25·C................

ORDERING INFORMATION*
To-71
IT500

WAFER
IT500/W

DICE
IT500/D

IT501

IT501/W

IT501/D

IT502

IT502/W

IT502/D

IT503

IT503/W

IT503/D

IT504

IT504/W

IT504/D

IT505

IT505/W

IT505/D

250mW
3.8mWI"C

500mW
7.7mW/oC

NOTE 1. Per transistor.
NOTE 2. Due to the non·symmetrical structure of these devices, the

drain and source ARE NOT interchangeable.
NOTE 3. @ 85°C free air temp.

'When ordering wafer/dice refer to Section 10, page 10-1.

2-87
Note: All typical values have been guaranteed by characterization and are not tested:

·D~Dlb

','

',f

ELECTAICAL CHA'RACTEFUSTIcS (@

25°C

unle~s' otherwise

',.

'.;.

specified)

.,

",

",

.,

,

LIMITS
SYMBOL

CHARACTERISTICS

1EST CONDITIONS

UNIT
MIN MAl!-

=125°C

IGSS

Gate Reverse Current

BVGSS

Gate-Source Breakdown Voltage

VGS(off)

Gate-Source Cutoff Voltage

VGS

Gate-Source Voltage.

IG

Gate Operating Cun:ent

. ITA

YGS = -20V, "DS

.'

=: 0

IG = -l/lA, VOS= 0

-60

VOS = 20V, 10 = lnA

-0.7

-100

pA

-5

nA

-4

V

-0.2. -3.8.

'.

-5

VOG = 50V, 10 = 200/lA
ITA = 125°C
loss

Saturation Drain Cun:ent. (Note 1)

VOS = 20V, VGS = 0

0.7

9fs

Common-Source Forward Tr!\nsconductance
(Note 1) .

VOS = 20V, VGS = 0

1000

9fs

Common-Source Forward Transconductance
(Note 1)

VOG = 20V, 10 = 200/lA

700

pA

-5

nA

7

rnA

4000

-

1600

1= 1kHz
gas

Common-Source 'Out)'rut Conductance

VOS = 20V, VGS" 0

gas

Common-Source' ,Output Conductance

Vos .. 20V, 10 ~ 200/lA

Cg lg2

Gate to Gate Capacitanca (Note 4)

VGI = VG2 = 10V

Cis.

Common-Source Inpul

Crss

Common-Source Reverse Transler Capacitance
(Note 3, 4)

NF

Spot Noise Figure (Not~ 4)

Capactt~nce

/lS
1
0.025
3.5

(Note 4)

1= lMHz

pF

7
pF

0.5
VOS = 2OV; VGS = 0

en

I = 100Hz,
RG = 10Mn

.Equivalent Input Noise. Voltage (Note 4)

IT500
SYMBOL

CHARACTERISTICS

IT501

0.5

dB

1= 10Hz

0.Q35

1= 1kHz

0.010

IT502

IT503

IT504

/lV

.1Hz

IT505

TEST CONDITIONS

UNIT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

IG1-IG2

Differential Gale
Cun:ent

VOG= 20V,
10 = 200/lA

10SSl
-I05S2

Saturation' Drain Cun:ent
Ralio. (Note 1)

VOS = 20V, VGS = OV

9fsl / gis2

Transconductance Ratio
(Note 1)

VGS1-VGS2

Differential Gate-Source
Voltage

AVGS1-VGS2

Gate-Source Differential
Voltage

+ 125°C

f= 1kHz

VOG= 20V
10" 200/lA

5

5

5

5

10

15

0.95

1

0.95

1

0.95

1

0.95

1

0.9

1

0.85

1

0.97

1

0.97

1

0.95

1

0.95

1

0.90

1

0.85

1

5

5

10

15

25.

50

TA = 25"C
Te" 125"C

5

10

20

40

100

200

TA = -55"C
Te=25"C

5

10

20

40

100

200

/mV

/lVrC

AT
Change with Temp.
(Note 2, 4)
Common Mode Rejection
Ratio (Note 4)

CMRR··

A Voo = 10V, 10 = 200/lA

120

120

120

•• CMRR = 20 log10AV001 A [Vgsl-Vgs21, AVOO = 10/-20V

NOTES:

nA

1.
2.
3.
4.

Pulse lest required, pulsewidth = 300j.lS, duty cycle", 3%.
Measured at end points, TA and Te.
With case guarded Crss is typically < 0.15pF.
For design relerence only, not 100% tested.

2-88
Note: All typical values have been guaranteed by characterization and are not tested-

120

120

120

dB

IT500-IT!$05
TYPICAL PERFORMANCE CHARACTERISTICS
OUTPUT CHARACTERISTICS

GATE LEAKAGE

.."
r
i yt
~

IO·~A I--

u

7

_v

r

20"·30

40

SO

-a.tv
vOS·-O.1V
vos·-O.IV
VOS·-UN
VOl- -1.2V

Yos. -ttY
vos' -!.IV

0

o

10

VDII-DRAIN-GATE VOLTAGE - VOLTS

10

0P002211

TYPICAL CAPACITANCE VS. GATEoSOURCE
VOLTAGE

OUTPUT CHARACTERISTICS

10

~ Z.O

1

...

I

1,\

B 1.5
w
:il
~

~

c

~

~

0

1"-.
a

I I I I

.

VD~:~_ l-

f~ •

\

0."

I

~

~

z

r\

~ '0

-0.& -1.0

-1.5

-2.0

=
--

DRAIN TO SOURCE VOLTAGE

0P002111

2.0

I

VOS.

,

1,·0
I 0.0

I

VOS. -D.N

,

1.5

~

10

vo.Jov

~ 2.0

TA· 25~C

o

-2.1

to.

...~
o

-2

-t

...

...

-10

Yos-GATE SOURCE YOLTAGE-VOLTS

Vos-GATE-8OURCE VOLTAGE-VOLTS

OP~1I

OPOO2311

2-89
Note: All typical values have been guaranteed by characterization and are not tested.

PI

JlltS.c);,'
t: Dual N-Channel JFET Switch

~

FEATURES
•
•
•

D~nll:l
.

','

'

.

.

,,

CHIP TOPOGRAPHY

Specified Matching Ch,aracterlstics
High Gain
Low "ON" Resistance,

6033

PIN CONFIGURATION
1'0-71

30

CTOO4011

ABSOLUTE MAXIMUM RATINGS
G.

(25°C Unless otherwise noted)
Gate-Drain crGate-Source Voltage .................... -40V
Gate Current .............. , ............ , ..................... 50mA
Gate-Gate Voltage ................... ;·....................... ±80V
Storage Temperature Range ............. -65°C to +200°C
Operating Temperature Range ......... -55°C to +175°C
Lead Temperature (Soldering; 10sec) .............. +300°C
ONE SIDE
BOTH SIDES

0.
PCOO0511

ORDERING INFORMATION*

Power Dissipation .................... .
Derate above 25°C .............. ..

325mW
2.2mW'oC

650mW
4.3mW'oC

·When ordering wafer/dice refer to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS (25°C unless otherwise noted)
LIMITS
SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
MIN

IGSSR

Gate·Reverse Current

VGS = -20V, Vos = 0
ITA = 150·C

MAX
-100

pA

-200

rnA

-3

V

lOSS

Saturation Drain Current (Note 1)

= -lIlA, VOS = 0
= 15V, 10 = InA
VOS = OV, IG = 2mA
VOS = 15V, VGS = 0

rOS(on)

Static Drain Source ON Resistance

10= 1rnA, VGS=O

gts

Common-Source Forward

gos
Crss

Common-Source Reverse Transfer CapaCitance

f=IMHz

3

Ciss

Common-Source Input CapaCitance

(Note 4)

12

NF

Spot Noise Figure (Note 4)

f=10Hz, Rg =IM

1.0

en

Equivalent Short Circuit Input Noise Voltage
(Note 4)

f= 10Hz

50

BVGSS

Gate-Source Breakdown Voltage

VGS(off)

Gate-Source Cutoff Voltage

VGS(I)

Gate-Source Voltage

IOSS1

-IOSS2

IG

'-40

VOS

-0.5

1.0
5
f= 1kHz

7500

Transconductance (Note 1)

f = 100MHz (Note 4)

7000

Common-Source Output Conductance

f= 1kHz

Saturation Drain Current Ratio (Notes I, 2)

VOG = 15V, 10 = 2mA

VOS

= 15V,

VGS = 0

2-90
Note: All typical values have been guaranteed by characterization, and are' not tested;' ;'

30

rnA

100

n

12,500
I'S

45

0.95

I

pF
dB
nV

-

v'Hz

-

IT550
ELECTRICAL CHARACTERISTICS (CO NT.)
LIMITS
SYMBOL

UNIT'

TEST CONDITIONS

PARAMETER

MIN
IVGS1-VGS2 1
 100dB

CHIP TOPOGRAPHY
4003

TO-71

TO·78

:=x::: . ',

llc---;;CO;;L~LE~C;:;;To;R~'~1:J:i.;:;:I-:o=-""";==-"SOLATION
COLLECTOR
t2 TYP 2 PLACES
.0045 x .0045

.025

.0035

J

.0035

BASE '2 TYP 2 PLACES

: : : OIAMETER
BASEj1
EMITTER It2
.0040
TYP 2 PLACES .0030

EMITTER"1

DIAMETER
CT003511
PCOO081f

ABSOLUTE MAXIMUM RATINGS
(TA = 25·C unless otherwise noted)
Collector-Base Voltage (1) .................................. 45V
Collector-Emitter Voltage (1) ............................... 45V
Collector-Collector Voltage .................................. 45V
Emitter-Base Voltage (1) ...................................... 6V
Collector Current (1) ....................................... 20mA
Storage Temperature Range ............ -65·C to +200·C
Operating Temperature Range ......... -55·C to + 150·C
Lead Temperature (Soldering, 10sec) .............. + 300·C
Power Dissipation (Tc = 25·C) ......................... 800mW
Derate above 25·C ........................... 14mW I"C

ORDERING INFORMATION*
TO-71

T0-78

WAFER

DICE

LM114

LM114H

LM114/W

LM114/D

LM114A

LM114AH

'When ordering wafer/dice refer to Section 10, page lCJ.:-1.

ELECTRICAL CHARACTERISTICS

(NOTE 2)
MAXIMUM LIMITS

PARAMETER

SYMBOL

TEST CONDITIONS

LM114A,
AH

LM114,
H

UNIT

VSEl-2

Offset Voltage

ll1A:$ Ic:$ l0011A

0.5

2.0

mV

IS·2

Offset Current

IC - 1011A

2.0

10

nA

Ie = lIlA

0.5

40

nA

Bias Current
IlVSEIV

Offset Voltage Change

IlVSEIV

Offset Current Change

Ie ~ 1011A

20

Ie -lIlA

3.0

OV:$ VCS :$ VMAX, IC = 1011A

0.2

1.5

mV

1.0

4.0

nA

2-102
Note: All typical values have been guaranteed by characterization and are not tested.

LM114/H, LM114A/ AM
ELECTRICAL CHARACTERISTICS (CONT.)
MAXIMUM LIMITS
SYMBOL

PARAMETER

AVBE/AT

Offset Voltage Drift

AIBl_2/ AT

Offset Current

TEST CONDITIONS

-55·C S TA S + 125·C, Ic = 101lA

AlB/AT

Bias Current

ICBO

Collector-Base Leakage Current

VCB=VMAX

ITA = 125·C (Note 3)
ICEO

Collector-Emitter Leakage Current

VCE = VMAX. VEB = OV

Collector-Collector Leakage Current

Vcc= VMAX

ITA = 125·C (Note 3)
NOTES:

LM114,
10

12

50

60

150

nA

10

nA

50

50
50'
200

50

200

nA

100

300

pA

100

300

nA

1: Per transistor.
2: These specifications apply for TA = + 25·C andOV S VCB S VMAX. unless otherwise specified. For the LM114 and LMI14A.
VMAX = 30V.
3. For desi!!n reference only. not 100% tested.

2-103
Note: All typical values have been guaranteed by characterization and are not tested.

UNIT

H

2.0

10

ITA = 125·C (Note 3)
IC1-C2

LM114A,
AH

,NrC

pA
pA

..... '., '10.'
-.·.S,·'
.'. ····O·.ru
• . .,o~'·.····

, M118
i Diode Protected N-Channel

i.'
.

,.

" .

,

! .,

•

Enhancement· Mode MOSFET
General' "purpose Amplifier
FEATURES

CHIP- TOPOGRAPHY

•

Log IGSS .

•

Integrated Zener

Clamp

1003

for Gate Protection

PIN CONFIGURATION
T0-72

m

G .0025

x .0029

.0035

.0039

.J...L+-'----'\,-'O .0030 , .()()28
IS BODY

.0040

.()()38
CTOO451t

ABSOLUTE MAXIMUM RATINGS

eGo

(TA = 2S0C unless otherwise noted)

PGOO2711

Drain to Source Voltage .................................... 30V
Gate to Drain Voltage ....................................... 30V
Drain Current ................................................. SOmA
Gate Zener Current ..................................... ±0.1 mA
Storage Temperature Range ............ -6SoC to + 200°C
Operating Temperature Range ......... -SsoC to + 150°C
Lead Temperature (Soldering, 10seo) .............. + 300°C
Power Dissipation ......•.................................. 22SmW
Derate above 2SoC .......................... 2.2mWrC

ORDERING INFORMATION*

'When ordering wafer/dice refer to Section 10, page 10-1.

DEVICE SCHEMATIC

tp::
4

0SD00411

ELECTRICAL CHARACTERISTICS

(25°C unless otherwise noted, Vas = 0)
M116

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
MIN MAX

vGS = 2OV, 10 = 100llA, ves = 0

100
I 200

n

rOS(on)

Drain Source ON Resistance

VGS(lh)

Gate .Threshold Voltage

VGS = VOS, 10 = 10llA, VBS = 0

BVOSS.

Drain-Source Breakdown Voltage

10 = lIlA, VGS = VBS· 0

30

BVsos

Source-Drain Breakdown Voltage

IS=lllA, VGO=VBO=O

30

BVGBS

Gate-Body Breakdown Voltage

IG - 10llA, VSB = VOB = 0

30

10(OFF)

Drain Cutoff Current

VOS = 20V, VGS = VBS = 0

10

IS(OFF)

Source Cutoff Current

VSO - 20V, VGO = VBO = 0

10

IGSS
Cgs

Gate-Body Leakage

VGS

=0

100

pA

Gate-Source (Nole 1)

VGe = Voe = Vse = 0, f = 1MHz

Cgd

Gate-Drain Capacitance. (Note 1)

Body Guarded

Cdb

Drain-Body Capacitance (Note 1)

VGe = 0, Voe

2.5
2.5
7

pF

Ciss

Input Capacitance (Note 1)

VGB=O, Voe=10V, Ves-O, f-1MHz

VGS

= 10V,

= 20V,

NOTE 1: For design reference only, not 100% tested.

2-104
Note: All typical values have been guaranteed by characterization and are not tested.

10 = 100llA, Ves = 0

VOS = VBS

= 10V,

f= lMHz.

1

5
V
60

10

nA

U200-U202

N-Channel JFET Switch
FEATURES

APPLICATIONS

•
•

•
•
•

Low Insertion Loss
Good OFF Isolation

PIN CONFIGURATION

Analog Switches
Commutators
Choppers

CHIP TOPOGRAPHY
5001

TO-18
.00135 FULL RADIUS

.00175 (DRAIN)

)(

.oo~

.0026

(SOURCE)
CT000911

o
PC000611

ABSOLUTE MAXIMUM RATINGS
ORDERING INFORMATION*
TO-18
U200

U200/W

DICE
U200/0

U201

U201/W

U201/0

U202

U202/W

U202/0

WAFER

(TA = 25°C unless otherwise noted)
Gate-Drain or Gate-Source Voltage ................. ,,' -30V
Gate Current ......... "., .................................... 50mA ~
Storage Temperature Range ......... , .. -65°C to + 200°C ~
Operating Temperature Range ......... -55°C to + 150°C
Lead Temperature (Soldering. 10sec) "."" ....... + 300°C
Total Device Dissipation (TC = 25°C) " ........ ",,: .... 1.8W
Derate above 25°C ... " ...................... 10mWrC

'When ordering waler I dice rlller to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS

(25°C unless otherwise noted)
U201

U200
SYMBOL

PARAMETER

UNIT
MIN

IGSS

Gate Reverse Current

VGSS = 20V, Vos = 0

ITA = 150'C
BVGSS

Gate-Source Breakdown Voltage

IG = -1jJ.A, VOs=O

-30

VGS(off)

Gate·Source Cutoff Voltage

VOS = 20V, 10 = 10riA

-0.5

10(011)

Drain Cutoff Current

VOS = 10V, VGS = -12V

lOSS

ITA = 150'C
Saturation Drain Current (Note 1)

VOS = 20V, VGS = 0

rds(on)

Drain-Source ON Resistance

VGS = 0, 10 = 0

Ciss

Common-Source Input
Capacitance (Note 2)

VOS = 20V, VGS = 0,

erss

Common-Source Reverse
Transfer Capacitance (Note 2)

VOS=O:
VGS= -12V

NOTES:

U202

TEST CONDITIONS
MAX

MIN

-1

-1

nA

-1

-1

-1

"A

-30
-3

-1.5

25

-30
-5

-3.5

1
15

75

-10

1

1

1
f= 1kHz

MIN .MAX

-1

1

3

MAX

30

1

jJ.A

lPO

rnA
ohm

150

7$

50

30

30

30

8

8

8

f=IMHz

1: Pulse test required, pulsewidth = 300"., duty cycle S 3%.
2. For design reference only, not 100% tested.

2-105
Note: All typical values have been guaranteed by characterization and are not tested.

V
nA

pF

U231-U235,
!=: General
Dual ·N..;ehannel JFET
Purpose Amplifier
fJ

9

FEATURES

APP.LICATIONS

•

•
•

Good Matching Characteristics

PIN CONFIGURATION

Differential Amplifiers
Low and Medium Frequency Amplifiers

CHIP TOPOGRAPHY
6037

·10-71

ALL BOND ~AOS ARE 4)( 4 MIL.
CT004811

ABSOLUTE MAXIMUM RATINGS

ORDERING INFORMATION*

(TA = 25·C unless otherwise noted)
Gate-Source or Gate-Drain Voltage (Note 1) •....... -50V
Gate Current (Note 1) .... ; ........................... : .... 50mA
Storage Temperature Range ............ -65·C to + 200·C
Operating Temperature Range ......... -55·C to + 200·C
Lead Temperature (Soldering, 10sec) .............. +300·C
Power Dissipation ......................................... 300mW
Derate above 25·C .......................... 1.7mWI"C

·When ordering wafer/dice refer to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: 25·C unless otherwise noted.
LIMITS
SYMBOL

PARAMETER

TEST CONDITIONS

UNIT
MIN

-100

pA

-500

nA

-0.5

-4.5

V

-0.3

-4.0

IGSS

Gate Reverse Current

BVGSS

Gale-S()urce Breakdown Vollege

IG -IlIA, VOS = 0

-50

VGS(ofI)

Gate-Source Cutoff Voltege

VOS = 20V, 10 - InA

VGS

Gate-SoUrce Voltage

IG

Gate Operating Current '

loSS

Saturation Drain Current (Note 2)

Vos - 20V, VGS - 0

9fs

Common-Source Forward Transconductance
(Note 1)

Vos = 2OV, VGS - 0

Sf.

Common-Source Forward Transconductance
(Note 1)

Voo = 20V, 10 = 2oo11A

90s
90s

Common-Source Output Capacitance

Vos=20V, VGS = 0

CommOn-SourClil Output Conductance

Voo - 20V, 10 - 2001iA

Q..

Common-Source Input CapaCitance

Crss

Common-Source Reverse Transfer Capacitance

I

TA = 150·C

MAX

VGS =-30V, Vos ··0

-50

en

I

pA

VOG = 20V, 10 - 20011A
-250

nA

0.5

5.0

rnA

f= 1kHz

1000

3000

f-looMHz
(Note 4)

1000

TA = 125·C

/.IS
. 600
f= 1kHz

1600

35
10
6

f-1MHz

2

Vos = 2OV, VGS - 0
Equivalent Short CircuH Input Noise Voltage

(Note 4)

2-106
Note: All typical values have been guaranteed by characterization and are not tested.

f= 100Hz

80

pF
nV

-VHz

.D~OIL

U231-U23S
ELECTRICAL' CHARACTERISTICS:tCONT.)
SYMBOL

MATCHING CHARACTERISTICS

= 20V,

IIGI -IG21

Differential Gate Current (Note 4)

VOG

(10551- 10552)

Saturation Drain Current
Match (Note 2, 4)

V05 = 20V, VG5 = 0

10551
IVG51-VG52 1
6.IVGS1- VG52 1
6.T

-glsl
-1gosl-gos21
NOTES:

1.
2.
3.
4.

10 = 2001lA

Differential Gat&-Source Voltage

125°C

TA = 25°C

1.0

10

10

10

10

nA

5

5

5

10

15

%

5

10

15

20

25

mV

10

25

50

75

100

TA = 25°C
Gate-Source Voltage
Differential Diift (Note 3)

TB-125°C

jJvrc
VOG

(glsl-91s2)

U231 U232 U233 U234 U235
UNIT
MAX MAX MAX MAX MAX

TEST CONDITIONS

= 20V,

10 = 2001lA

f~

Transconductance Match (Note 2)
Differential OUtput Conductance
Per transistor.
Pulse test required, pulse width - 3OOjJs, duty cycle
Measured at end pOints, TA and TB
Eor design reference only, not 100% tested.

TA = -55°C
TB = 25°C

~

3%.

2-107
Note: All typical values have been guaranteed by characterization and are not tested.

1kHz

10

25

50

75

100

3'

5

5

10

15

%

5

5

5

5

5

jJS

'too

I

0287
Dual N-Channel JFET
High Frequency Amplifier

.

FEATURES

.U~UI6
;".;"

•

'...

c','

.

CHIP TOPOGRAPHY

-9'.). 5OO0psFrom DC to 100MHz
-

Matched

Vas.

91. and 90s

'

PIN CONFIGURATION\
T0-99

ABSOLUTE MAXIMUM .RATINGS
(TA .: 2S·C unless otherwise noted)
G,

0,

Gate-Drain or Gate-Source Voltage ·(Note 1) ........ -25V
Gate Current (Note 1) .................•................... 50mA
Storage Temperature Range ............ -65·C to + 200·C
Operating Tempe;ature Range ......... -55·C to + 150·C
Lead Temperature (Soldering, 10sec) .. , ........... +300·C

S,
PC00151i

'ORDERING INFORMATION*

ONE SIDE

Power Dissipation
(TA =85·C) .•.......•............ ,...
Derate above 25·C ...••.•......

·When ordering wafer/dice refer to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS
SYMBOL

250mW
3.8mW

500mW
7.7mWrC

rc

(25·C unless otherwise noted)

PARAMETER

TEST CONDITIONS

Gate Reverse Current

IGSSR

BOTH SIDES

MIN MAX UNIT.

VGS -15V, Vos = 0
jTA = 150°C

;...100

pA

-250

nA

BVGSS

Gate-Source Breakdown Voltage

IG - -lpA, Vos- 0

-25

VGS(off)

Gate-Source Cutoff Voltage

Vos-l0V, io-lnA

-1

-5

5

40

V
loss

Saturation Drain Current (Note 2)

Vos -10V, VGS - 0

91.
91s

Common-Source Forward Transconductance

Vos = 10V, 10 - 5mA

I-1kHz

5000 10,()O(

Coinmon.&>urce Forward Transconductance

Voo - 10V, 10" 5mA

1= 100MHz (Note 3)

5000 10,oo!

gas

Common-Source Output Conductance

Vos = 10V, 10 = 5mA

I-1kHz

150

gOBS

Common-Source Output Conductance

1= 100MHz

150

C;s.

Common-Source Input Capacitance

c,i.

Common.&>urce Reverse Transfer Capacitance

Voo -10V, .10 - 5mA

f-1MHz

e;;

Equivalent Input Noise Voltage

(Note 3)

f-l0kHz

-IO$S2

Drain currerit Retio at Zero Gate Voltage
(Note 2)

VOS" 10V, VGS - 0

IVGS1-VGS2 1

Differllntlal Gate-Source Voltage

9181
9102

T~nsconductance Ratio

1900 1-90021

Differential Output Conductance

IOSS1

mA

jill

5
1,2

nV

30

0.85

0.85
f-lkHz

NOTES: 1. Per transIstor.

2. Pulse test nsquired, pulse width = 300jlll, duty cycle $ 3%.
3. For design reference only, not 100% tested.

2-108
Note: All typical values have been guaranteed by characterization and are not tested.

-

~

1
100

Voo -10V, 10 = 5mA

pF

mV

1

20

jill

.D~DIL

U304-U306

P-Channel JFET Switch
FEATURES

APPLICATIONS

•
•
•

•
•
•

Low ON Resistance
ID(off) < 500pA
Switches directly from TTL Logic (U306)

PIN CONFIGURATION

cCot
o

t

c

I

Analog Switches
Commutators
Choppers

CHIP TOPOGRAPHY

_--.021--_

TO·18

- lJ~111!11~'l=
.0027 (0685)

'~~!':~l 0
x
0037 (.0939)
.0027 (.0685)

I

NOTE: SUBSTRATE IS GATE
CT00491!

o

ABSOLUTE MAXIMUM RATINGS

G.C

(TA = 25·C unless otherwise noted)
Gate-Drain or Gate-Source Voltage (Note 1) .......... 30V
Gate Current ................................................. 50mA
Storage Temperature Range ............ -65·C to + 200·C
Operating Temperature Range ......... -55·C to + 150·C
Lead Temperature (Soldering, 10sec) ................. 300·C
Power Dissipation ......................................... 350mW
Derate above 25·C .......................... 2.8mW

PCOO0111

ORDERING INFORMATION*
To-18

WAFER

DICE

U304

U304/W

U304/D

U305

U30S/W

U305/D

U30S

U30S/W

U30S/D

rc

'When ordering wafer/dice refer to Section 10. page 10-1.

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: 25°C unless otherwise noted.
U304
SYMBOL

PARAMETER

U305

U306

TEST CONDITIONS

UNIT
MIN MAX MIN MAX MIN MAX

laSSR

Gate Reverse Current

Vas = 20V, Vos = 0
ITA = 150·C

Gate·Source Breakdown Voltage

la = lIlA. VOS - 0

VaS(off)

Gate·Source Cutoff Voltage

VOS(on)

Drain·Source ON Voltage

VOS= -15V. 10= -11lA
vas 0, 10
15n:A.. \~~04J,
10 = - 7mA (U30S),
10 = -3mA (U306)

lOSS

Saturation Drain Current (Note 1)

VOS=-15V, Vas=O

Drain Cutoff Current

VOS = -15V, VGS = 12V (U304)
VGS - 7V (U305)
VGS = 5V (U306)

ITA = 150·C
r05(on)

Static Drain·Source ON Resistance

VGS=OV, 10= -1mA

rds(on)

Drain·Source ON Resistance

VGS=OV, 10=0

Ciss

Common·Source Input CapaCitance
(Note 2)

VOS= -15V,
VGS=O

Crss

Common·Source Reverse Transfer
Capacitance (Note 2)

VOS = 0, VGS = 12V
(U304)
Vas = 7V
(U305),
VGS= 5V
(U30S)

500

500

pA

1.0

1.0

1.0

IlA

30

BVass

10(0ff)

500

5

f=1MHz

2-109
Note: All typical values have been guaranteed by characterization and are not testE!(!.

10

3

-1.3
-30

f= 1kHz

30

30
6

1

-0.8
-15

-60

4

V

-0.6
-25

rnA

-500

-500

-500

pA

-1.0

-1.0

-1.0

IlA

85

110

175

85

110

175

n
n

27

27

27

7

7

7

-90

-5

pF

PI

8
'"

.j

:11. D~DlL.

U304--U306
.
.

..

..

.

ELECTRiCAL CHARACTERiStiCS (CONT.)

,'"

=

U304·
SYMBOL

PARAMETER

U304
Turn-ON pelay Time (Nole 2)

Ir

Rise Time (Note 2)

lct(oIf)

Turn-OFF Delay Time (Nole 2)

If

Fall Time (Nole 2)

U306
UNIT

MIN
Id(on)

U305

TEST CONDITIONS
U305

MAX MIN MAX MIN MAX

U306

-6V

-6V

20

25

25

7V

5V

15

25

35

743n

laOOn

10

15

20

0
0
VGS(on) 0
-15mA -7mA -3mA
10(on)

25

,40

60

Voo

-10V

VGS(off) 12V
560n
RL

NOTES: 1. Pulse· tesl pulsewidlh ~ 300jtS, duty cycle S 3%.
2. For design reference only, nol 100% lested.

2-flo
Nole: All typical values have been guaranleed by characterizalion and are nol lested.

ns

.U~UIL!

U308-U310
N-Channel JFET
High Frequency Amplifier

..
Co)

o

FEATURES
•
•
•
•

CHIP TOPOGRAPHY

High Power Gain
Low Noise
Dynamic Range Greater Than 100dB
Easily Matched to 7SU Input

~-1 x .0068 G

.0021

.0058

PIN CONFIGURATIONS
TO-52
NOTE: SUBSTRATE
IS GATE

TYP
0035 x 0035
2 PLACES .00,35
.0025
CT00501I

ABSOLUTE MAXIMUM RATINGS
(TA = 25·C unless otherwise noted)
Gate-Drain or Gate-Source Voltage _______________ •.•.. -25V

o

Gate Current ...............................••......••........ 20mA
Storage Temperature ...................... -65·C to +200·C
Operating Temperature Range ......... - 55·C to + 150·C
lead Temperature (Soldering. 10sec) .............. +300·C
Power Dissipation .....•.•..•.•.•......•....•.•.•.••.•.•.•. 500mW
Derate above 25·C .••••.•••..•.•.•......•.•..• 4mW

S
PC001211

rc

ORDERING INFORMATION*
TO-52

WAFER

DICE

U30S

U30S/W

U30S/0

U309

U309/W

U309/0

U310

U310/W

U310/0

·When ordering wafer/dice refer to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS

(25·C unless otherwise noted)

U30a
SYMBOL

PARAMETER

U310

U309

TEST CONDITIONS
MIN TYP MAX MIN TYP MAX MIN

IGSS
BVGSS
VGS(off)
loSS
VGS(f)
9tg

Gate Reverse Current
trA = 125°C
Gate-Source Breakdown
Voltage
Gate-Source Cutoff Voltage
Saturation Drain Current
(Note 1)
Gat....Source Forward
Voltage
Common-Gate Forward
Transconductance (Note 1)

VGs= -15V
VGS=O

-150

pA

-150

-150

nA

-25

-25

Vos=10V,lo¥lnA

-1.0

-6.0 -1.0

-4.0 -2.5

VOS = 10V, VGS = 0

12

60

10

30

17

-6.0

24

1.0
10

17

10

V

60

rnA

1.0

V

17

iJS

1= 1kHz

Cgd
Cgo

Gate-Source Capacitance

VOS= 10V

1= lMHz
(Note 2)

en

Equivalent Short Circuit
Input Noise Voltage

VOS-l0V,
10-10mA

I-100Hz
(Note 2)

VGS - -10V,

12

1.0

Common Gate Output
Conductance
Drain-Gate. Capacitance

gogo

-150

-150
-25

. VOS=10V,
10= lOrnA

UNIT
MAX

-150

IG = -lILA, Vos =0

IG = lOrnA, VOS = 0

TYP

2-111
Note: All typical values have been guaranteed by characterization and are not tested.

250

250

250

2.5

2.5

2.5

5.0

5.0

5.0

iJS

pF

10

10

10

-nV

v'Hz

IIO~OI6
ELECTRICAL CHARACTERISTICS (CO NT.)
U3d9

U308
SYMBOL

PARAMETER

U310
UNIT

TEST CONDITIONS
MIN TYP MAX MIN TYP MAX MIN T,(P MAX

Common-Gate Forward
Transconductance
91g

Ie 100MHz

15

15

15

1- 450MHz

14

14

14

1= 100MHz

0.18

O.Hi

0.18

,/.IS

Common-Gate Output
Conductance

gog.
Gpg

Common-Gate Power Gain

Vos'= 10V,

1=450MHz

10= lOrnA

I -100MHz

14

16

14

16

14

1=450MHz

10

11

10

11

10

(Note 2)
NF

Noise Figure

0.32

0.32

0.32
16
11

f= 100MHz

1.5

2.0

1.5

2.0

1.5

2.0

f=450MHz

2.7

3.5

2.7

3.5

2.7

3.5

NOTES: 1. Pulse test duration = 2ms.
2. For design reference only, not 100% tested.

2-112
Note: All typical values have been guaranteed by characterization and are not tested.

dB

.U~UI6I

U401-U406
Dual N-Channel JFET Switch
FEATURES
•
•
•
•

CHIP TOPOGRAPHY,

Minimum System Error and Calibration
Low Drift With Temperature
Operates From Low Power Supply Voltages
High Output Impedance

Cb

6037

PIN CONFIGURATION
TO-71

"LL BONO PADS ARE' x • MIL.
CTOOO711

ABSOLUTE MAXIMUM RATINGS
(TA = 25·C unless otherwise noted)
S,

Gate-Drain or Gate-Source Voltage ...................... 50V
Gate Current (Note 1) ..................................... 10mA
Storage Temperature Range ............ -65·C to + 200·C
Operating Temperature Range ......... -55·C to + 150·C
Lead Temperature (Soldering, 10see) .............. + 300·C

PC000511

ORDERING INFORMATION*

ONE SIDE

BOTH SIDES

300mW
2.6mWI"C

SOOmW
SmW/·C

Power Dissipation (TA = 8S·C) ... .
Derate above 2S·C ............... .

'When ordering waler/dice reler to Section 10, page 10-1.

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: 25·C unless otherwise noted.
U401
SYMBOL

PARAMETER

U402

U403

U404

U40S

U406

TEST CONDITIONS

UNIT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

BVGSS

Gate-Source Breakdown
Voltage

Vos - 0, IG = -lIlA

IGSS

Gate Reverse Current
(Note 2)

VOS = 0, VGS = -30V

VGS(off)

Gate-Source Cutoff Voltage

VOS -15V, 10 -InA

VGS(on)

Gata-Source Voltage (on)

VOG

loSS

Saturation Drain Current
(Note 3)

VOS = 10V, VGS = 0

IG

Operating Gate Current

VOG - 15V, 10 = 200jiA

(Note 2)

.1

= 15V,

-50

-50
-25

-50
-25

-50
-25

-50

-50
-25

-25

V
-25

pA

-.5 -2.5 -.5 -2.5 -.5 -2.5 -.5 -2.5 -.5 -2.5 -.5 -2.5
V
-2.3

10 = 200jiA

-2.3

-2.3

-2.3

-2.3

-2.3

0.5 10.0 0.5 10.0 0.5 10.0 0.5 10.0 0.5 10.0 0.5 10.0

TA-125°C

rnA

-15

-15

-15

-15

-15

-15

pA

-10

-10

-10

-10

-10

-10

nA

BVG1-G2

Gate-Gate Breakdown
Voltage

VOS - 0, VGS - 0,
IG - ±ljiA

±50

gfs

Common-Source Forward
Transconductance (Note 3)

VOS· 10V,

2000 7000 2000 7000 2000 7000 2000 7000 2000 7000 2000 7000

gos

Common-Source Output
Conductance

VGS=O

91s

Common-Source Forward
Transconductance

90s

Common-Source Output
Conductance

Voo-15V,

Cis.

Common-Source Input
Capacitance (Note 6)

10 = 2001lA

±50

±50

±50

±50

±50

V

1= 1kHz
20

20

20

20

20

20
I'S

1000 1600 1000 1600 1000 1600 1000 1600 1000 1600 1000 1600
1= 1kHz
2.0

2.0

2.0

2.0

2.0

2.0

B.O

B.O

B.O

8.0

B.O

B.O

I=IMHz
Crss

Common-Source Reverse
Transler capaCitance
(Note 6)

pF
3.0

2-113
Note: All typical values have been 9uaranteed by characterization and are not tested.

3.0

3.0

3.0

3.0

3.0

I U40'.U,~~~

,,' ,'" ;

'4- ELECTRICAL CHARACT':FlISTICS (CONT.)

,i::»

'.
SYMBOL

U401
PARAMETER

U402

'U403

U404

U405

TEST CONDITIONS
MIN MAX MIN MAX MIN MAX ,.IN MAX. MIN

U~

MAX MIN MAX

UNIT

en

Equivalent Short-Circuit
Input Noise Voltage

VOS·15V.
VGS=O

CMRR

Common-Mode Rejection
Ratio

Voo - 10 \0 20V,
10 - 200"" (Note 5, 6)

IVGS1- VGS21

Differential c Gate~$ource
Voltage

Voo = 10V. 10 = 200""

5

10

10

15

20

40

mV

Gate-Sour"". Voltage
Dlfferenti!ll Drift (Not!i 4)

ITA = '-55'C
Voo = 10V. T = +25'c'
10 = 200"" Tg = + 125'(;

10

10

25

25

40

80

pV/'C

""'GS1-VGS21

Ll.T

I

f-10Hz
(Note 6)

20

95

95

NOTES: 1. Per transistor.

2. Approximately doubles for every 10'C increase in TA.
3. Pulse test duration = 300"s; duty cycle :;; 3%.
4. Measured at end points. TA, TB. Tc.
5. CMRR=.20 log10 [

20

. AVoo , ] . AVoo = 10V.
AIVGS1"VG82'

6. For design reference only, not 100% ·tested.

2-114
Note: All typical values have been guaranteed by characterization and are not tested.

20

20

95

20

20

90

.1I5

nV
-VRi
dB

U1897~U1899

N-Channel JFET Switch
FEATURES

APPLICATIONS

•
•

•

Low Insertion Loss
No Error or Offset Voltage Generated By Closed
Switch

PIN CONFIGURATION

Analog Switches, Choppers

CHIP TOPOGRAPHY
5001

TO-92
.00135 FULL RADIUS

q

I
L

:00175 (DRAIN),

0072 NOTE

~

--1

~ .016

o

S

~i'~~:::~ATE

~~
---I

.0025 x .0029
.0035
.0026
(SOURCE)

Cro05,'1

G

PCO01311

ABSOLUTE MAXIMUM RATINGS
ORDERING INFORMATION*
TO-92
U1897

TO-92-18
U1897-18

WAFER
U1897/W

(TA = 25°C unless otherwise noted)
Gate-Drain or Gate-Source Voltage _................... -40V
Forward Gate Current ...................................... 10mA •
Storage Temperature Range ............ -55°C to + 150°C
Operating Temperature Range ......... -55°C to + 135°C
lead Temperature (Soldering, 10sec) .............. + 300°C
Power Dissipation ...................................... ; .. 350mW
Derate above 25°C .......................... 3.2mW fOC

DICE
U1897/D

U1898

U1898-18

U18,98/W

U1898/D

U1899

U1899-18

U1899/W

U1899/D

'When ordering wafer/dice refer to Section 10, page 10-1_

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: 25°C unless otherwise noted
U1897
SYMBOL'

PARAMETER

U1898

U1899
UNIT

TEST CONDITIONS
MIN MAX MIN

BVGSS

Gate-Source Breakdown Voltage

IG = -1 #-lA, VOS = 0

IGSS

Gate Reverse Current

VGS = -20V, VOS = 0

-400

-400

-400

1000

Drain-Gate Leakage Current

VOG = 20V, IS = 0

200

200

200

ISGO

Source-Gate Leakage Current

VSG= 20V, 10=0

200

200

200

10(011)

Drain Cutoff Current

VOS - 20V,
VGS= -12V (U1B97)

200

200

200

ITA = B5'C

-40

MAX MIN' MAX

VGS = -BV (U1B9B)
VGS = -6V (U1B99)

-40

10

10
-7.0-

10
-5.0

nA

VOS = 20V, 10 = lnA

-5.0

lOSS

Saturation Drain Current (Note 1)

VOS - 20V, VGS = 0

30

VOS(on)

Drain-Source ON Voltage

VGS = 0, 10 = 6.6mA (U1897)
10 = 4.0mA (U1898)
10 = 2.5mA (U1899)

0.2

0.2

0.2

V

rOS(on)

Static Drain-Source ON Resistance

10=lmA, VGS=O

30

50

BO

n

Cdg

Drain-Gate Capacitance

VOG

5

5

5

CSg

Source-Gate Capacitance

VSG =20V, 10 = 0

Ciss

Common-Source Input Capacitance

Crss

Common-Source Reverse Transfer
Capacitance

15

-1.0

pA

Gate-Source Cutoff Voltage

Is = 0

-2.0

V

VGS(oll)

= 20V,

-10

-40

B.O

5

5

5

f= lMHz

16

16

16

(Note 2)

3.5

3,5

3.5

VOS = 20V, VGS = 0

2-115
Note: All typical values have been guaranteed by characterization and

are~ot

tested.

V
mA

pF

,

I U1897-U1899
;

:::» ELECTRICAL CHARACTERISTICS (CONT.)

,!

::::»..

U1897
SYMBOL

PARAMETER

U1898

UNIT
MIN MAX MIN MAX

'Id(on)

Tum ON Delay Time (Note 2)

Ir

Rise Time (Note 2)

Ioff

NOTES:

Turn OFF Time (Note 2)

U1899

TEST CONDITIONS
MIN

MAX

Switching Time Test Conditions

15

15

20

U1897 U1898 U1899

10

20

40

40

60

80

3V
Voo
0
VGS(on)
VGS(off) -12V
425n
RL
6.6mA
1010nl

3V
0
-8V

3V
0
-BV
non 1120n
4mA 2.5mA

1. Pulse test pulsewidth - 3001-'s; duty cycle < 3%.
2. For design reference only. not 100% tested.

2-116
Note: All typical values have been guaranteed by characterization and are not tested.

ns

,

.O~OIl.I

VCR2N/3P/4N/7N

Voltage Controlled Resistors

-•
Col

APPLICATIONS
•
•
•
•

.'!
z

CHIP TOPOGRAPHY

-...

VCR2N
5001

Small Signal Attenuators
Filters
Amplifier Gain Control
Oscillator Amplitude Control

.00135 FULL RADIUS

.oom (DRAIN)

Z

PIN CONFIGURATIONS
TO·18

TO-71

r--

• .0036

-:0026

--I

.01.

(SOURCE)
CTOO6BOI

VCR7N
5007

-hD15~

::

G

(3) ,

o
PCOOO611

PC000511

.0025 )( .0025
.0035
.0035

-r

T0-72
(N-Ghannel)

TO·72
(P-Ghannel)

.0013 FULLR
.0017
CTOO69OI

VCR3P

5508

,Rrilm~'='.0025

o

.0027

.016

PC004801

PCOO4701

.0037 x .0035 0
.0025

.0027

ORDERING INFORMATION*

.
.

•

NOTE: SUBSTRATE
IS GATE
CT007001

To-18

TO·72

WAFER

DICE

VCR2N

-

VCR2N/W

VCR2N/O

VCR4N

-

VCR4N/W

VCR4N/O

-

VCR3P

VCR3P/W

VCR3P/O

VCR7N

VCR7N/W

VCR7N/O

VCR4N
5010 (4N)
D(2)

~{Irr~'

'When ordering wafer/dice refer to Section 10, page 10-1.

.0025 • .0025
.0035

.0035

.~:~~~

~

NOTE: SUBSTRATE
IS GATE

.013
CTOO71OJ

VCRllN
6019
0,

--i

G'lf'§§§§~tfeil ~2~~
, { - - .D39

s,
.025 [ll
G, ~. .0037
I _
,.1I
.0027
.0027
..L ____.....
"!-- 0, TYP. 2 PLACES
Sa

~x .0035

.0025

.0025

TYP.2 PLACES
CTOO1201

2-117
Note: All typical values have been guaranteed by characterization and are not tested.

VtR2N/3Pf,4NI7N
, :. ;'.' '0--1-"."0'"

.'OV---i\
TG002501

0,25

WFOOO601

TCOO2601

Circuit Diagrams

Figure 2: Switching Times

TYPICAL PERFORMANCE CHARACTERISTICS
SWITCHING TIMES
VS TEMPERATURE
0123 AND 0125
(SEE NOTES 4 AND 5)

toff(delay) VS IIN(PEAK)

0123
c

1.8

,

1.7

1

1.6

E

:t0

.

1.5

/

N

::; 1.4

c

:I

1.3

Z

1.2

"0

/
1
"
'
/
j

,000

1100

./

L

V

~900

..

VR-O
VEE --20V
V+- ,OV
CCUT-1OpF

:I 700

;:::

V"-O
VEE --20V
V+o < COUT < ,0000F
0< 10UT<4mA

,ov

"Zsoo
~

I-

~300

liN CPEAKI

(mA)

toft (1 mA.

L.-1"'"

."

- --

.......

>800

alOmA

~:;_0_2OV-

~t-...

!

I
-"
1o,,(4mA!/

10.

100

"N

I I

-0

lOUT

.......

i

......
~

~600

V

10" (dellyl

TA·25°C

1.0,

VIN(ON) VS TEMPERATURE
0123

-so

I I
400

75
o 25
TEMPERATURE (OCI

125

-25

25

75

,25

TEMPERATURE tOCI
OPOO2801

OPOO2801

-75

3-3
Note: All typical values have been guaranteed by characterization and are not tested.

OPOIl3OOI

!

1»12311)125';

Q

-TYPICAL' PERFORMANCE CHARACTERISTICS (CONT.)

=

is

liN VS VIN
0123

u
;(

...!

_v.

10'

1.4

!

Vu. • -20V

26'C ~';!- ~

:( 0.3

.;

.,55'C

0.6

V
o

r--+--+--+---I

./

0.21--+--

I

~ 0.2

Vee" 10V

~ 0.4 I--+--+--+-~

126'C i:-'~

U

V, •• 0.5V (0126)
V.·O
V,·4.5V

0.5

I

ffi

IOUT(OFF) VS TEMPERATURE
,0123 ANO 0125'

liN" 1 inA (0123)

-0

VIE .. -20V

II:
0::

....""

VSAT VS TEMPERATURE
0123 ANO 0125

/

r '"""1

10

......-....L.._...J

1

0.1 1=~=.!:IO~Ui!-T,:,·.!.1!mA

I

O'---......-75

0.2
0.4
0.6 0.8
V,. - INPUT VOLTAGE IV)

-25

26

75
TEMPERATURE I'C)

OPOO3101

26

126

45

65

APPLICATIONS
Using INTERSIL'S MOSFET SWITCH, G117, with either
the 0123 or 0125 drivers provides a convenient means of
designing a 5 channel analog multiplexer with a series on/
off switch.

0

f

117

-r

'..

..

I.

I

AFOO0501

Figure 3:

5-Chan~el

105

126

0P003301

QPO07001

r ~~~oo--~----------~
:L~!
-:0 c~o:;j

65

TEMPERATURE I'C)

Multiplexer

Note: All typical valUes have been guaranteed by characterization and are not tested.

D123/D125
APPLICATION TIPS
Interfacing the D123 and D125
In order to meet all the specifications on this data sheet,
certain requirements must be met by the drive circuitry.
The D125 can be turned ON easily, but care must be
exercised to insure turn-off. Keeping VL - VIN S DAV is a
must to insure turn-off. To accomplish this, a shunt resistor
must be added to supply the leakage current (ICES) for DTL
devices. Since ICES = 50pA, a OAV IO.05mA = 8kn or less
resistor should be used. For TTL devices using a 2kn
resistor will insure turn-off with up to 200pA of leakage
current.

Y" ••.•

...

..-

--

D'.

01'L"IIUL"'~

••

110

...... aa

--

~'"

fl'fLI"""'LUIIt

..

-

m._ .........

LD012301

Figure 5: 0125 Interface

Using the ENABLE Control

.

Device pins VR or VL, can be used to enable the D123 or
D125 drivers. For the D123, the enabling driver must sink
IR(ON) X no. of channels used. For the D125, IL(ON) X no. of
channels used must be sourced with a voltage at least + 4V
greater than VIN.

v.

LD012201

Figure 4: 0123 Interface

3-5
Note: All typical values have been guaranteed by characterization and are not tested.

!

8,12'9

" 4-Channel Decoded JFET
Switch Dri,ver
GENERAL DESCRIPTION

FEATURES

The 0129 is a 4-channel driver with binary decode input.
It was designed to provide the DC level-shifting required to
. interface low-level logic outputs' (0.7 to 2.2V) to field-effect
transistor inputs (up to 50V peak-to-peak). For a 5V input
logic supply, the V- terminal can be set at any voltage
between -5V and -30V. The output transistor is capable of
sinking 10mA and will stand-off up to 50V above V- in the
off-state.
The ON state of the driver is controlled by a logic "1"
(open) on all three input logic lines, while the OFF state of
the driver is achieved by pulling anyone of the three inputs
to a logie, "0" (ground).
The 4-channel driver is internally connected such that
each one can be controlled independently or decoded from
a binary counter.
..

•

·Quad Three;;lnputGates Decode Binary Counter
to. Four Lines
• Inputs .Compatible With Low Power TTL and
DTL, IF 200MA Max
• Output Curr.ent Sinking Capability 10mA
-- External Pull-Up Elements Required
• Compatible With G115 and G123 Series
Multichannel MOSFET Switches Which Include
Current-Umiter Pull-Up FETs

=

ORDERING INFORMATION
D129

A,--,--T
-:---'--- - - - - - . , . - - - - - - - - - - - - - 'Package

1

K - 14-pin CERDIP
L - 14-pin' Flat Pak
P - 14-pin Ceramic DIP
(Special Order Only)
Temperature Range
A - Military (- 55·C .to + 125·C)
B - Commercial (,.. 20·C to + 85·C)

~-------------------- Device Chip Type

v'

I.
IN,

13

IN2
12
IN3
IN.
INS

11

IN.

I.
IN,

OUT,

OUl 2

OUT3

OUT4

(eACH DRIVER)

LOOOO701

GNO

vLOOOO601

Flg~re

1: Functional Diagrams (Outline Dwgs DO, FD-2, JD)

Note: All typical values have been guaranteed by characterization and are not tested."

...D

D129

I\)

co

ABSOLUTE MAXIMUM RATINGS
Vo - V- ........................................................ 50V
GND - V- ...................................................... 33V
V+ - GND ....................................................... 8V
VIN - GND ..................................................... ±'6V
Current (any terminal) .....................................:. 30mA

Storage Temperature ...................... -65°C to + 150°C
Operating Temperature ................... -55°C to + 125°C
Power Dissipation (note) ................................ 750mW
Lead Temperature (Soldering, 10sec) ................. 300°C

Note: Dissipation rating assumes device mounted with ali leads welded or soldered to pc board in ambient temperature of 70·C. Derate 1OmW I·C for higher
ambient temperatures,
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure 10
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

Test conditions unless otherwise specified V-

= -20V,

V+

= 5V

MAXIMUM LIMIT

SYM·

PARAMETER

D129M

01291

-5S·C

25°C

85°C

-19.3

-19

-19.8

Va = 10V, VIN = 0.7V

Input Current
Input Voltage High
Input Current
Input Voltage Low

BOL

TEST CONDITIONS

UNIT

12S·C

-20·C

2SoC

-19.3

-19

-19.25

-19.25

-19.8

-19.75

0.1

0.1

20

0.2

0.2

10

VIN = 5V Input Under Test,
VIN = 0 Ali Other Inputs

0.25

0.25

5

1

1

5

VIN = 0, V+ = 5.5V

-250

-200

-160

-250

-225

-200

OUT

VOL

Output Voltage, Low

10= 10mA

VOL

OUtput Voltage, Low

10=lmA

Output Current, High
10H
INPUT
IINH
IINL

.

.

I VIN = 2.2V. V + = 4.5V

V
"A

IlA

TIME

ton

Ioff

Tum-ON Time

I Turn-OFF

I See

Time

0.25
Switching Time Test Circuit

I

I

1.0

0.3

I

I

I

1.5

I

I

SUPPLY

lEE

Negative Supply Current

-2

""

-2.25

IL

LogiC Supply Current

V- = -20V

One Channel "ON"

3

3.3

lEE

Negative Supply Current

V+ = 5.5V

Ali VIN=O,

-10

-25

IlA

Ali Channels "OFF"

0.75

1

mA

Logic Supply Current
IL
• Per gate Input

IN:::::8

-.'OY

.5V

1

ri> I

I

I

-1

r

If''' lOOns
t f .. lOOns
OUT

IN

'Pw. ' ''''

.,~:~
OY

mA

=t-

f .. lOOK Hz

ton~

·'OY - - - - -

OUT

OV - - - - - - - - - -2OV
~90'4
WFOOO701

TCOO2701

Figure 2: Switching Time and Test Circuit

3-7

Note: Ali typical values have been guaranteed by characterization and· are not tested.

; DG11'8IDG123/DG125

Z4

& 5-Channel SPST Driver

c;With Switch
CIt
~

g-.
CD
~

~

g

GENERAL DESCRIPTION

FEATURES

This series includes devices with four and five channel
switching capability. Each channel is composed of a driver
and a MOSFET switch. Two driver versions are supplied for
inverting and noninverting applications. A MOSFET, used
as a current source provides an active pull-up. for faster
.
switching.
An external biasing connection is brought out for biasing,
the current source, for optimization of speed and power.

•

Available With and Without Programmable
Constant Current Pull-up
Zener Protection on All Gates
P-Channel Enhancement-Type MOSFET Switches
Each Switch Summed to One Common Point

•
•
•

ORDERING INFORMATION

TRUTH TABLE

DGl18 A L = K Package

DGl18, DG125

DG123

K - 14-ptn CERDIP
L - 14-pin Flat Package
P - 14-pin Ceramic DIP
(Special Order Only)
Temperature Range
A - Military (- 55°C to + 125°C)
B - Commercial (_20°C to +B5°C)
Device Chip Type

VIN

VR

VIN

VL

L
H
L
H

L
L
H
H

L
L
H
H

H
L
H

OG123

OG125

(One Channel)

(One Channel)

•

v·

"
;t::~:::;~::::::~~3D
,

1

~

I

I

,

:

v·

I•

IN

.,'..., '

.

.."

So"

"

1

1

v'

.

3•
I

I

I

I

I
I
I
I·
I
I

·

___ JI

I
I
I
I
I
I
I

iI

I

I
I
I
I
I
I

..'~2t-------~+-r-~-~

I

I

I1

: !

:

I
I
I

1

_____ JI

1
1

1

1
I.

1
1
1

1
I
I

_____ JI

"

s.~'t====:r;~==Sr3D
sak-

~~'t-------~~r---~
~~3t-------~+-~r_~

I

I
I
I
I
I
I

___ J

1

v-

v-

v.
v'

...

I

OFF
ON
.OFF
OFF

L=OV, H= +V

OGllS

v-

Condo

L

(One Channel)

IN

Switch

_______ JI

1
--_- .. - __ 1

lOOOO201

LDO00101

Figure 1: Schematic & Logic Diagrams (Outline Dwgs DD, FD-2, JD)

3-8
Note: All typical values have been guaranteed by characterization and· are not tested.

lOOO030t

.D~D[6

DG118/DG123/DG125

g

Collector to Emitter (V+ -V-) ............................. 33V
Collector to Pull-up (V + - Vp) .............................. 33V
Drain to Emitter (Vo-V-) .................................. 32V
Source to Emitter (Vs-V-) ................................ 32V
Drain to Source (VO-VS) ................................... 28V
Source to Drain (VS-Vo) ................................... 28V
Logic to Emitter (VL -V-) ................................... 33V
Reference to Emitter (VR-V-) ............................ 31V
Reference to Input (VR - V,N) ................................ 6V

Logic to Input (VL -V,N) ..................................... ±6V
",put to Emitter (V'N-V-) ..................................33V
Current (any terminal) ...................................... 30mA
Storage Temperature ...................... -65°C to +150°C
Operating Temperature ................... -55°C to + 125°C
Dissipation (Note) ......................................... 750mW
Lead Temperature (Soldering, 10sec) ................. 300°C
NOTE: Dissipation rating assumes device is mounted with all leads welded
or soldered to printed circuit board in ambient temperature of 70 o e.
Derate 1OmW I"C for higher ambient temperature.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated' in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
Test conditions unless specified otherwise are as follows: VL = 4.5V, VR
test conditions used for output and power supply specifications.

= 0, V- = -20V, and P = -20V. Input ON and OFF

I

MAX LIMITS

PARAMETER
(NOTE)

TEST CONDITIONS

-55°C

+ 25°C

+ 125°C

UNIT

INPUT

pA

IIN(OFF)

Y,N - O.4V

1

1

100

VIN(ON)

IIN-1mA

1.3

1.0

0.8

V

DG118

IIN(OFF)

VIN - 4.1V

1

1

20

IlA

DG125

IIN(ON)

VIN =0.5V

-0.7

-0.7

-0.7

rnA

DG123

OUTPUT

800

n
n
n

IO(ON)

Vo - 10V. IS(all) - 0

4

4000

nA

IO(OFF)

VS(all)

= 10V.

-4

-4000

nA

-1

-1000

nA

rOS(ON)
All
circuits

IS(OFF)
POWER SUPPLY

All
circuits

100

100

125

Vo = O. Is = -100IlA

200

200

250

Vo - -10V. IS - -1001lA

450

450

Vo = -10V

Vo = 10V. Vs = -10V

ICG(ON)

3
3

rnA

-0.5

rnA

IEE(ON)

-6

rnA

ICC(OFF)

10

pA

IL(OFF)

10

pA

-15

IlA
pA

All
circuits

VO-10V.IS--1mA

IL(ON)
IR(ON)

IR(OFF)

One Channel (ON)

All Channels (OFF)

I t(ON)

circuits

JtlOFFL

rnA

-20

lEE OFF}
SWITCHING TIMES
All

...

CD
.....

ABSOLUTE MAXIMUM RATINGS

DEVICE
NO.

g...

I

See Switching Times

I

I
I

0.3
1

I
I

I
..

NOTE: (OFF) and (ON) subscnpt notation refers to the conduction state of the MOSFET switch for the given test condition .

3-9
Note: All typical values have been guaranteed by characterization and are not tested.

I

p.s
Ils

;;
W

a
I:)

;;
UI

OG'I23

v"

to
I,

01 ,JS
01 tIS

s.
+--,--o'OUT'U1
DG123
OUTPUr

"'p'
TC002301

OG118,125
DG118,125
OUTPUT

oJl..
WFOOO501
OUTPUT

"p'
TCOO2401

i=igure 2: Switching Times

TYPICAL PERFORMANCE CHARACTERISTICS
liN vs VIN
DG123
1.8

i

!

...

..
"

VR- 0
V-'-20V

I.'

,.~

~

,,

II II

1100

!900

...'"

'~:g:NL

~

...u

SWITCHING TIMES vs
TEMPERATURE

-ssoc' ~

II NIl

0.6
0.2

V
0.2

0.4

I
0.6

~

;:

rOS(ON) vs Vo or Vs
IK

VR"'O
v- .. -20V

v+ =

10V

;<;,:~;v3(lpF

--+_1-+--+-/---::1

700

C>

~

I

V
0.8

VIN - INPUT VOLTAGE (VI

z

i

IS'-lmA

Vr:::

~~ ~-55.
_t-t-

' ......

500

u

....
~

300

.......

V+- 10V
-20V
Vp = -20V

v- ..

~~E~

tONr--.....

100

-50

125·_
25·-

o

25

125

10
-10

-10

TEMPE'AATURE (OC)

OP002501

OPO02601

3-10
Note: All typical values have been guaranteed by characterization and are not tested.

OP002701

DG118/DG123/DG125
APPLICATION TIPS
The recommended resistor values for interfacing RTl,
DTl, and TTL logic are shown in Figures 3 and 4.

..

DTL911941

9oI9H'163

TTLS414
TTl9000SEAIES

SU"l

AFOOO21I

Figure 4: DG123 Interface
AFOOO11 I

Figure 3: DG118 and DG125 Interface

Enable Control
The VR and Vl terminals can be used as either a Strobe
or an Enable control. The requirements for sinking current
at VR or sourcing current at VL are: IL(ON) x No. of channels
used, for DG 118 and DG 125, and IR(ON) x No. of channels
used for the DG123 devices. The voltage at VL must be
greater than the voltage at VIN by at least +4V.

3-11

Note: All typical values have been guaranteed by characterization and are not tested.

i~

,DG126,':!,DG129, DG133,
g8 DG134, DG140, DG141,
DG151, DG152', DG153, DG154
DUAL ,JFET Analog Switch
,FEATURES

GENERAL DESCRIPTION
These switching circuits contain two channels in one
package, each, channel conSisting of a driver circuit controlling a SPST or DPST junction - FET switch. The driver
interfaces DTl, TTL or RTl logic signals for multiplexing,
commutating, and Df A converter applications, which permits logic design directly with the switch function. logic "1"
at the input turns the FET switch ON, and'iogic "0" turns it
off.

1

•

Each Channel Complete-:-Interfaces With Most
Integrated Logic
'
' . Low OFF Power DisSipation, 1mW
• Switches Analog Signals Up to 20 Volts Peak-toPeak
• Low rOS(ON). 10 Ohms Max on DG140/A and
DG1411A
• Switching Times Improved 100%-'A' Versions

ORDERING INFORMATION
0126

1A

~

L ___________________

DUAL SPST
00133 (rOS(ON) = 30!'!)
DG134 (rOS(ON) = 80!'!)
DG141 (rOS(ON) = 10!'!)
DG151 (rOS(ON) = 1S!'!)
DG152 (rOS(ON) = 50!'!)

Package
K - 14-pin CEROIP
L - 14-pin Flat Pack
P - 14-pin Ceramic 01 P
(Special Order Only)
Temperature-Range
A - Military (-55'C to +125'C)
B - Industrial (- 20°C to + 80°C)
Device Chip Type

DUAL DPST
DG126 (rOS(ON) = 80!'!)
DG129 (rOS(ON) = 30!'!)
DGI40 (rOS(ON) = 10!'!)
DG153 ('OS(ON) = IS!'!)
DG154 (roS(ON) = 50!'!)

~~_sw,

$W,
SW,
SW,

VIlIENABlE)

lD012101

'0

V.

(ENABLE)
08027401

"

<>:"11-------f.-I~sw,

o-"'j---"! ---+--+-<>sw,

12
VII (ENABLEl
lD012001

Figure 1: Functional Diagrams (Outline Dwgs DO, FD-2, JD)

3-12
Note; All typical values have been guaranteed by characterization and are not tested.

v05027501

DG126, DG129, DG133, DG134, DG140,
DG141, DG151, DG152, DG153,· DG154
ABSOLUTE MAXIMUM RATINGS
Analog Signal Voltage (VA-V- or V+ -VA) ......... 30V
Total Supply Voltage (V + - V-) .......................... 36V
Positive Supply Voltage to Ref. Voltage (V+ - VR) .. 25V
Ref. Voltage to Neg. Supply Voltage (VR - V-) ...... 22V
Power Dissipation (Note) ................................ 750mW

Current (any terminal) ...................................... 30mA
Storage Temperature ...................... -65°C to + 150°C
Operating Temperature ................... -55°C to + 125°C
Lead Temperature (Soldering, 10sec) ................. 300°C

NOTE: Dissipation rating assumes device is mounted with all leads welded or soldered to printed circuit board in ambient temperature below 70'C. For higher
temperature, derate at rate of 1OmW I'C.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (Per Channel)
Applied voltages for all test: DG126, DG129, DG133, DG134, DG140, DG141 (V+ = + 12V, V- = -1BV, VR = 0), and DG151,
DG152, DG153, DG154 (V + = + 15V, V- = -15V, VR = 0). Input test condition which guarantees FET switch ON or OFF as
specified is used for output and power supply specifications
ABSOLUTE MAX LIMIT

SYMBOL
(NOTE)

CHARACTERISTIC

TYPE

TEST CONDITIONS

UNIT

-55°C

25°C

125°C

INPUT
VIN(ON)

Input VOltage-On

V>;.=-12V

2.9 min

2.5 min

2.0 min·

Volts

VIN(OFFI

Input Voltage-Off

V2 = -12V

1.4

1.0

0.6

Volts

IIN(ON)

Input Current

VIN =2.5V

120

60

60

p.A

IIN(OFF)

Input leakage Current

VIN =0.8V

0.1

0.1

2

p.A

80

80

150

n

30

30

50

n

10

10

20

n

15

15

30

n

All .circuits

SWITCH OUTPUT
DG126
DG134
DG129
DG133
rOS(ON)

Drain-Source On Resistance

VIN = (See Note)
Vo = 10V. Is = lOrnA

DG140
DG141
DG151
DG153
DG152
DG154

Vo = 7.5V, IS = lOrnA
50

100

n

VO=VS= -10V

±2

100

nA

Vs = 10V. Vo = -10V

±1

100

nA

Vo=10V, VS=-10V

±1

100

nA

Vo=Vs= -10V

±2

100

nA

Vs = 10V, Vo = -10V

±10

1000

nA

Drain leakage Current

Vo= 10V, VS= -10V

±10

1000

nA

IO(ON) + IS(ON)

Drive leakage Current

Vo=Vs= -7.5V

±2

500

nA

IS(OFF)

Source leakage Current

= - 7.5V

±10

1000

nA

IO(OFF)

Drain Leakage Current

Vo = 7.5V,. Vs = - 7.5V

±10

1000

nA

IO(ON) + IS(ON)

Drive leakage Current

Vo=Vs= -7.5V

±2

500

nA

IS(OFF)

Source leakage Current

Vs = 7.5V, Vo = - 7.5V

±2

200

nA

IO(OFF)

Drain Leakage Current

Vo = 7.5V. Vs = - 7.5V

±2

200

nA

IO(ON) + IS(ON)

Drive leakage Current

IS(OFF)

Source leakage Current

IO(OFF)

Drain Leakage Curr.ent

IO(ON) + IS(ON)

Drive leakage Current

IS(OFF)

Source leakage Current

IO(OFF)

DG126
DG129
DG133
DG134
DG140
DG141

DG151
DG153

DG152
DG154

VIN = (See Note)

Vs = 7.5V, Vo

NOTE: VIN must be a step function with a minimum slew-rate of tV / jJS.

3-13
Note: All typical values have been guaranteed by characterization and are not tested.

50

DG128J DG129, DG133, DG134, DG140,
DG141, DG151, DG152,· DG153, DG154

.:f

.. "
go

ELECTRICAL CHARACTERISTICS (CONT.)

(I) . .

-N
(1)110

"
gg..

SYMBOL
(NOTE)

ABSOLUTE MAX LIMIT
CHARACTERISTIC

TYPE

TEST CONDITIONS

UNIT
25°C

-55"C

125°C

POWER SUPPLY
I, (ON)

Positive Power Supply Drain
Current

12(ON)

Negative Power Supply Drain
Current

IR(ON)

Reference Power Supply
Drain Current

11 (OFF)

Positive Power Supply
Leakage· Current

12(OFF)

Negative Power Supply
Leakage Current

IR(OFF)

Reference Power Supply
Leakage Current

One Driver ON. VIN

= 2.5V

All Circuits

Both Drivers OFF. VIN = O.BV

3

mA

-l.B

mA

-1.4

mA

25

!lA

-25

!lA

-25

!lA

SWITCHING
toN

Turn-On Time

See Below

DG126. DG129. DG133.
DG134. DG152. 00154

600

ns

toFF

Turn-Off Time

See Below

DG126. DG129. DG133.
DG134. DG152. DG154

1.6

p.s

toN

Turn-On Time

See Below

DG140. DG141. DG151. DG153

1.0

p.s

toFF

Turn-On Time

See Below

DG140. 00141. DG151. DG153

2.5

p.s

POWER
PON

ON Driver Power

POFF

OFf Driver Power

175

Both Inputs VIN = 2.5V

I

All Circuits

I Both

Inputs VIN

= 1V

I

NOTE: (OFF) and (ON) subscript notation refers to the conduction state of the FET switch for the given test.

3-14
Note: All typical values have been guaranteed by characterization and are not tested.

I

1

mW

I

I

mW

.O~OIb

DG126, DG129, DG133, DG134, DG140,
DG141, DG151, DG152, DG153, DG154
ELECTRICAL CHARACTERISTICS (CONT.)
DG126, 129, 133, 134, 140, 141

NY:'.

,<0.1"

,,<0.'"

\1 .... _

-

.

DG151, 152, 153, 154

1Wr-------,.
J.MII

.,

.,

""""'

V•• ·?IV

'11'.",.,1'1

WF0269GI

WF026801

.

v.",.O\'

"" •• I:N

'"

INPUI C>-'V1I'rf--""""--'

OUTPUT

TC035201

TC035301

OFF MODEL

OFF MODEL

~OUTPUT

IHPUT

~
A'

m

AI

=

OUTPUT

•

INPUT

TC03550t

TC035401

ON MODEL

ON MODEL

-1'::'

~.n. -c>--t>- -,;
~.::
hVOI,tT
'o,.F
TC035601

1 ='_0

TC035701

Figure 2: Switching Times (at 25°C)

3-15
Note: All typical values have been gualanteed by characterization and are not tested.

DG1'26,DCi29, .DCi33, DG1340,.DG140,
DG141, DGi51, DG152~ DG153,DG154
TYPICAL PERFORMANCE CHARACTERISTICS (per channel)
DG126, 129, 133, 134, 140, 141

DG151, 152, 153, 154

VIN THRESHOLD VII TEMPERATURE

VIN THRESHOLD vs TEMPERATURE

VR =0
V+ = +12V

~~

ON

V-

~

= -12V

VR -0
v+ = +1'5V

2

0
-'
0

~~

%

:

r-

OFF

II:

ON

V- = -12V

-

OFF

%

l-

..

1

I-

::>
~

z

z

:>

:>

o

-15

-26

\

o

126

75

26

-75

-25

TEMPERATURE C'C)

25

OP058101

OP05BOOI

rOS(ON) vsTEMPERATURE
(Normalized to 25'C Value)
2

rOS(ON) vs TEMPERATURE
100

VIN = 2.5V
-VR =0

DGI52.1~

f-V+ = +12V

f-V-

= -lBV

./

1

,

!

-75

..... i-"

10

"

~

iiji;i;;

i,..oo"

1

./

DG151. DGI53

~

."
o

125

75

TEMPE RATURE C'CI

~

1

-25

26

75

-75

125

-26

26

75

126

TEMPERATURE COC)

TEMPERATURE C'c)

QP056301

OP058201

ALL CIRCUITS
ON SUPPLY CURRENT vs
TEMPERATURE
2.6

I--

\000

I
- 1::::-

..

100

I-

z \.8

a:
a:
::>

1.4

OJ

....

> 1.0
-'

Ii!

0.6

0

0.2

-

-

10
;;(

C 2.2 f-- --'

!

~
~

12C~""

;;(
.!;

f-

IRIONI

.E

g

;t;;t;~G'40.
'4'.
151.153

W

w

>
-'
::>

'29.

DGI26.
133.13<4

z

~

0.1

......'"
0

/

om

0.1
TEMPERATURE lOCI

Z

'"'"::>

.

DG152.
1~

25 50 75 100 125

.3
I-

UTf>UT
00142
DG14~

D<3139
DG144
rOS(oNj

Drain-Source On Resistance

DG145
DG146
DG161
DGl63
00162
00164

10(ON) + IS(ON)

Drive 'Leakage Current

IS(OFF)

Source LeBkage Current

10tOFFI

Drain. Leakage Current

10tON) + IStON)'

Orive Leakage Current

00139
D.G142
00143
DG144
DG145
DG146

VO" 10V, IS'" -IOmA
. VIN (See Note)
Vo-l0V, Is= -lamA
VIN (See Note)
VD.= 7.5V,. Is = -HlmA

50

100

n

VO" Vs, -: -10V

2

lOG

nA

Vs';' 10V, VP.'" -10V

1

100

nA

VO=10V, vS.- -10V

1

100

nA

vo=vs= -10V

2

100

nA

VS.-l0V; Vo - -10V

10

1000

nA

lW, Vs = -10V

10

1000

nA

Vo = Vs =·:"7.5V

2·

500

nA

Vs - 7.5V, VD = -7.5V

·10

1000

nA

VIN (see Note)

IS(OFF)

. SOllrce Leakage Currerit

1010FF)

Drain Leakage Current

10(0,,!>-+ IS(ON)

Clm(e Leakage Currerit

IS(OFF)

SOUrce Leakage Current

IO(OFF)

Drain Leakag8 Current

Vo = 1.5V, Vs - -7.5V

10

1000

nA

IO(ON) + IS(ON)

Dilve Leakagli Current

Vp=lIs· -7.5V

2

500

nA

IS(OFF)

Source Leakage Current

Vs-7.5V, 110- -7.5V

2

200

nA

IDlOFFl

Drain Leakage. Current

Vo=7.5V, Vs= -7.5V

2

200

nA

. VO=
00161
00163

00162
00164

NOTE: (OFF) and (ON) subscript notation refers to the oondu.ction state 'of . the FET .switch for the given test.
VIN must be a step function with a minimum slew-rate bf 1VI p.s.
.

3-18
Note: All typicai values have been guaranteed by characterizatkin

and are' not

tested.

.D~[l

DGi3e, DGi42-DGi46, DGi6i-DGi64

UNIT

;
g...

4.0

mA

g

-2.0

mA

-2.0

mA

25

pA

-25

pA

-25

pA

ELECTRICAL CHARACTERISTICS (CONT.)
ABSOLUTE MAX LIMIT

SYMBOL
(NOTE)

PARAMETER

TYPE

TEST CONDITIONS
-55°C

25°C

125°C

11 (ON)
12(ON)

Negative Power Supply
Drain Current

IR(ON)

Reference Power
Supply
Drain Current

I1(OFF)

Positive Power Supply
Leakage Current

12(OFF)

Negative Power Supply
Leakage Current

IR(OFF)

Reference Power
Supply
Leakage Current

VINl =3V
or
VINl =2V
All Circuits

VIN1

= VINE, = O.BV

SWITCHING

toN

Turn-On Time

DG139, DQ142
DG143, OG144
OG162, OG164

See Switching Times

O.B

iJ.S

tOFF

Turn-Off Time

DG139, OG142
DG143,OGt44
DG162, DG164

See

Times

1.6

iJ.S

tON

Turn-On Time

OG145, DG146
OG161, OG163

See Switching Times

1.0

iJ.S

Turn-Off Time

OG145, OG146
DG161, OG163

See . Switching Times

2.5

iJ.S

tOFF

t
I

POWER SUPPLY

Positive Power Supply
Drain Current

;

Sw~ching

NOTE: (OFF) and (ON) subscript notation refers to the conduction state of the FET switch for the given test

3-19
Note: All typical values have been guaranteed by charecterizatiOA and ar& not testeel.·

J
;
!
b
o

...

:

;I)Q13~ 'DG142-DG14,6,.DG181,..DG164

~

i

8

DG139,142, 143, 144, 145, 146'

~."".~.."~~""'f

. •,,01,,$

•

C.' 01/~



--

I uG142. 143

i--"

'i;;;r:r+DG145.146

100

10
E

.!'

I-""

O~

-75

______

-so -25

-L~~~~

0

25

so

1

-75

75 100 125

-so -25

0

25

so

EXCEPT DG145.146

0.1
75 100 125

TEMPERATURE I"C,

TEMPERATURE COCI

~ §§

§~ DG145.146

!

OP003601

25

45

65

85

105

125

TEMPERATURE lOCI
QP003701

OP003801

DG161, 162, 163, 164
VIN1 THRESHOLD vs
TEMPERATURE

RDS(ON) vs TEMPERATURE
100

-

..;::

DG162.164

..,...

~

'"

.£
z

~

10

--

-75

______

-so -25

0

-L~

25

__

so

::

DG161.163

E

O~

looo·em_
IS(OFF) vs TEMPERATURE

~~

1

75 100 125

TEMPERATURE C·CI

-75 -50 -25 0

25

so

75 100 125

TEMPE RATURE I·CI

65

55

105

125

TEMPERATURE C'CI
0f'00400!

OPO03901

45

3-21
Note: All typical values have been guaranteed by characterization and are not tested.·

OPOO4101

iDG180-191

i

High-Speed Driver With

.c; JFET Switch
a

GENERAL DESCRIPTION

FEATURES

The DG180 thru DG191 series of analog gates consist of
2 or 4 N-channel junction-type field-effect transistors (JFED
designed to function as electronic switches. Level-shifting
drivers enable low-level inputs (0.8 to 2V) to control the ONOFF state of each switch. The driver is designed to provide
a turn-off speed which is faster than turn-on speed, so that
break-before-make action is achieved when switching from
one channel to another. In the ON state, each switch
conducts current equally well in both directions. In the OFF
condition, the switches will block voltages up to 20V peakto-peak. Switch-OFF input-output isolation is SOdB at
10MHz, due to the low output impedance of the FET-gate
driving circuit.

•
•

•
•
•
•
•

Constant ON-Resistance for Signals to ±10V
(DG182, 185, 188, 191), to ±7.5V (All Devices)
± 15V Power Supplies
< 2nA Leakage From Signal Channel In Both .ON
and OFF States
TTL, DTL, RTL Direct Drive Compatibility
ton, toff < 150ns, Break-Before-Make Action
Cross-talk and Open Switch Isolation> 50dB at
10MHz (75n Load)
JAN 38510 Approved

ORDERING INFORMATION
PART
NUMBER
DG180
DG181
DG182
DG183
DG184
DG185
DG186
DG187
DG188
DG189
DG190
DG·191

TYPE
Dual
Dual
Dual
Dual
Dual
Dual

SPST
SPST
SPST
DPST
DPST
DPST
SPDT
SPDT
SPDT
Dual SPDT
DuslSPDT
Dual SPDT

o

rOS..l0n)

L

1 1

(M Xl
10
30
75
10
30
75
10
30
75
10
30
75

~ PACKAGE

x

.

A - 10-PIN METAL CAN
L - l4-PIN FLAT PACK
P - CERAMIC DIP
(Special Order Only)
K - CERDIP
.
TEMPERATURE
A - MILITARY (- 55°C to
+ 125°C)
B - INDUSTRIAL (- 20°C to
+ 85°C)

' - - - - - - - DEVICE TYPE
' - - - - - - - - - DRIVER

ONE AND TWO CHANNEL SPDT AND SPST
CIRCUIT CONFIGURATION

TWO CHANNEL DPST CIRCUIT CONFIGURATION

v+

v'

VL

IN

IN

o

II
I I .........' - - - - 4 -........,....J
GNDV-

OG11111871188 SHOWN

ONO

v-

OG1831184/185 SHOWN

LOOO1201

LQOO1301

Figure 1: Functional Diagram (Typical Channel)

3-22
Note: All typical values have been guaranteed by characterization and are not tested.

.n~nll

DG180-191
ABSOLUTE MAXIMUM RATINGS
.
v + -v - ..........................................................
36V

GND-V- ......................................................... 27V
GND-VIN ........................................................ 20V
Current (S or D) See Note 3 ........................... 200mA
Storage Temperature ...................... -65·C to + 150·C
Operating Temperature ................... -55·C to + 125·C
Power Dissipation* ................... 450 (TW), 750 (FLAT),
825(DIP)mW
Lead Temperature (Soldering, 10sec) ................. 300·C

V+ -Vo ........................................................... 33V
Vo-V- ........................................................... 33V
Vo-VS ........................................................... ±22V
VL-V- ............................................................ 36V
VL-VIN ............................................................. 8V
VL-GND ........................................................... 8V
VIN-GND .......................................................... 8V

'Device mounted with all leads welded or soldered to PC board. Derate 6mW;oC (TW); 10mW;oC (FLAT); l1mW;oC (DIP) above 7S"C.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

DUAL SPST (DG180, 181, 182)
Metal Can Package

Flat Package
5,

c:::=====;::;!

CERDIP*

"
r;:=====::I5,
- u - _.. D,

Ne

Ne

Ne

Ne
- - - . .____ IN,

IN'_........ . - - - y+

y,

y-

CDOQ0401

CDOOOSOI

(OUTLINE DWG TO-l00)

(OUTLINE DWG FD-2)

CD000601

(OUTLINE DWG JD)

DUAL DPST (DG183, 184, 185)
Flat Package
54

CERDIP*

C:==:::::::;:;J
D.

D·

INI

y+

"C:=====::J

OND

COOOO701

COOOO801

(OUTLINE DWG FD-2)

(OUTLINE DWG JE)

Figure 2: Pin Configurations and Switching State Diagram

3-23
Note: All typical values have been guaranteed by characterization and are not tested.

...g

?...
...
CD

...,. DG·1·80-191
i..
g

SPOT (OG186, 187, 188)

Metal Can Package

Flat Package

CERDIP'

D,
NC

NC

DtC:::::Jl---,..
5t r--.1. __ .__ --"

VL

IN

NC

v'

v-

COOOO901
cOaOtODI

COOO110J

(OOTLINE DWG FD·2)

(OUTLINE DWG TO·l00)

(OUTLINE DWG JD)

DUAL SPOT (OG189, 190, 191)

Flat Package

CERDIP'

,.
53
D.

NC

v,

Dt

(SUBSTAATE)

" NC

5t

It

INt

vTOP VIEW

OND

CDOO1901

CDOO1201

'Side braze ceramic package available as special order only. Consult factory.
(OUTLINE DWG JE)

(OUTLINE DWG FD·2)

Figure 2: Pin Configurations and Switching State Diagram (Cont.)

ELECTRICAL CHARACTERISTICS (v+
PARAMETER

DEVICE NO.

= + 15V, v-

= -15V, VL = 5V, Unless Noted)

TEST CONDITIONS
(NOTE 1)

A SERIES

B SERIES
UNIT

-SS'C

+2S'C

+ 12S'C

-20'C

+2S'C +8S'C

±1

100

±5

100

SWITCH

IS(off)

IO(olt)

Io(on) + IS(on)

OG181, 182, 184, 185
187, 188, 190, 191
(OG180, 183, 186. 189)

Vs=10V, Vo= -10V, v+ =10V
V- = -20V, VIN = "OFF"

±(10)

(1000)

(15)

(300)

OG181, 184, .187, 190
(OG 180, 183, 186, 189)

Vs = 7.5V, Vo = -7.5V
VIN = "OFF"

±1
±(10)

100
(1000)

±5
(15)

100
(300)

nA

OG182, 185, 188, 191

Vs - 10V, Vo - -10V
VIN="OFF"

.±1

100

±5

100

nA

OG181, 182, 184, 185
187, 188, 190, 191
(OG180, 183,186, 189)

Vs -10V, Vo - -10V, v+ -10V

±1

100

±5

100

±(10)

(1000)

(300)

OG181, 184, 187, 190
(OG180, 183, 186, 189)

Vs = 7.5V, Vo
VIN = "OFF"

±1
±(10)

100
(1000)

(15)
±5
(15)

100
(300)

nA

OG182, 185, 188, 191

Vs = 10V, Vo = -10V
VIN = "OFF"

±1

100

±5

100

nA

OG180, 181, 183, 184
186, 187, 189, 190

Vo = Vs = -7.5V, VIN = "ON"

±2

-200

-10

-200

nA

OG182, 185, 188, 191

Vo-Vs- -10V, VIN-"ON"

±2

-200

-10

-200

nA

nA

nA
V- = -20V, VIN = "OFF"

= -7.5V

3-24
Note: All typical values have been guaranteed by characterization and are not tested.

DG180-191
ELECTRICAL CHARACTERISTICS (CONT.)
PARAMETER

DEVICE NO,

B SERIES

A SERIES

TEST CONDITIONS
(NOTE 1)

-SS'C

UNIT

+12S'C

+2S'C

-20'C

+2S'C +8S'C

INPUT
IINL

I ALL

IINH

All

I

I VIN - OV
I VIN = SV

-2S0

I
I

-2S0

-2S0
10

I

20

I
I

-2S0

I
I

-2S0
10

I
I

-2S0
20

I
I

p.A
p.A

DYNAMIC
ton

Ion Switches

300

30n Switches

ISO

180

2S0

300

2S0

300

7Sn Switches

toff

See switching time test circuit

IOn Switches
30n and 7Sn Switches

CS(off)
CO(ofQ

DG181, 182, 184, 18S,
187, 188, 190, 191
(DG180, 183, 186 189)

CO(on) + CS(on
OFF Isolation

3S0

150

130
9 typical (21 typical)

Vs=-SV, 10=0, f=IMHz
VO- +SV, IS-O, 1-1MHz

6 typical (17 typical)

Vo - Vs - 0, I - 1MHz

14 typical (17 typical)

RL = 7Sn, CL = 3pF

ns

pF

Typically> SOdS at 10MHz (See Note 2)

SUPPLY

1+

1-

DG180, 181, 182, 189
190, 191

I,S

I.S

DG183, 184, 185

0.1

0,1

DG186, 187, 188

0.8

0.8

DG180, 181, 182, 189
190. 191

-S.O

-S.O

DG183, 184, 18S

IL
IGNO

1+

1-

-4.0

-4.0

DG186, 187, 188

-3.0

-3.0

DG180, 181, 182, 183
184, 18S, 189, 190, 191

4.S

4.S

DG186, 187, 188

3.2

3.2

VIN = SV

ALL

-2.0

-2.0

DG180, 181, 182, 189
190, 191

1.5

I.S

DG183, 184, 18S

3.0

3.0

DGI8S, 187, 188

0.8

0.8

DG180, 181, 182, 189
190, 191

-S.O

-S.O

-S.S

-S.S

-S.O

-S.O

DG18S, 184, 18S

VIN = OV

DG186, 187, 188

IL
IGNO

NOTES 1.
2.
S.
.

DG180, 181, 182, 183
184, 18S, 189, 190, 191

4.S

4.S

DG186, 187, 188

3.2

S.2

All

-2.0

-2.0

mA

See SWitching State Diagrams lor VIN " ON " and VIN " OFF " Test Conditions.
Off Isolation typically> SSdB at lMHz for DG180, 18S. 186, 189.
Saturation Drain Current lor DG180, 183, 186, 189 only, typically SOOmA (2ms Pulse Duration). Maximum Current on all other devices
(any terminal) 30mA.

3-2S
Note: All typical values have been guaranteed by characterization and are not tested.

;; D0180-'I91

..g~

a» ELECTRICAL CHARACTERISTICS (CONT.)
DEYICE
NUMBER

CONDITIONS (Note 1)
y+ 15Y, Y- ,.15Y, YL 5Y

=

=

=

vo· -7.5V
Vo- -7.5V

OG180
OG181
OG182
OG183
OGI84
OG185
OG186
OG187
OG188
OG189
OG190
OG191

Vo VoVoVO=
Vo=
Vo'"
Vo =
Vo =
Vo =
VO-

-10V
-7.5V
-7.5V
-10V
-7.5V
-7.5V
-10V
-7.5V
-7.5V
-10V

IS= -10mA
VIN-"ON"

MAXIMUM RESISTANCES (rOS(ON) MAX)
INDUSTRIAL
TEMPERATURE

MILITARY TEMPERATURE
-55°C

+ 25°C

+ 125°C

-20°C

10
30
75
10
30
75
10
30
75
10
30
75

10
30
75
10
30
75
10
30
75
10
30
75

20
60
100
20
60
150
20
60
150
20
60
150

15
50
100
15
50
100
15
50
100
15
50
100

UNIT

+ 25°C + 85°C
15
50
100
15
50
100
15
50
100
15
50
100

25
75
150
25
75
150
25
75
150
25
50
150

n
n
n
n
n
n
n
n
n
n
n
n

APPLICATION HINT (for design only): Normally the minimum Signal handling capability of the OG180 through OG191 family is 20V peak-to-peak
for the 75n switches and 15V peak-to-peak for the Ion and 30n (refer 10 and IS tests above). For other Analog Signals, the following
guidelines can be used: proper switch tum-off requires that V- SVANALOO(peak) -Vp where Vp =7.5V for the Ion and 30n switches and
Vp =5.0V for 75n switches e.g., -10V minimum (-peak) analog Signal and a 75n switch (Vp=5V), requires that V- S -10V -5V= -15V.

logic Input for "OFF" to "ON" Condition (DG180/181/182 Shown)
LOGIC 3V
INPUT
I, <1Ons
If <1Ons

1.SV
SWITCH
OUTPUT

0

A-t-~~---1----~Yo

SWITCH Vs
INPUT
SWITCH
OUTPUT

CL

I30pF

O.9Vo

(REPEAT TEST FOR

0

-15Y ALL CHANNELS)

~

Ion

RL

Yo = Ys RL + FDS(ON)

-=

v-v

Y-

o-

RL

S AL T roS(on)
TC035601

WF027011

Figure 3: Switching Time Test Circuits
output waveform shown for Vs = constant w~h logic input waveform as shown. Note that Vs may be + or.- as per switching time test circuit.
Vo Is the steady state output with switch on. Feedthrough via gate capac~nce may result in spikes at leading and trailing edge of output waveform.
Sw~ch

DUA~

DUAL SPST-DG180/181/182

DPST -DG183/184/185

TEST CONDITIONS

TEST CONDITIONS

00180/181/182
VIN "ON" = O.8V
VIN "OFF" = 2.0V

DG183/184/185

I

.AII Channels
All Channels

. VIN "ON" = 2.0V
VIN "OFF" = O.8V

SWITCH STATES ARE
FOR LOGIC "1" INPUT = 2.0V

DUAL SPOT -DG189/190/191
TEST CONDITIONS

TEST CONDITIONS

DG189/1901191

DG186/187/188
"ON" = 2.0V
"ON" = O.SV
"OFF" = 2.0V
"OFF" = O.SV

All Channels
All Channels

SWITCH STATES ARE
FOR LOGIC "1" INPUT = 2.0V

SPOT-DG186/1871188

VIN
VIN
VIN
VIN

I

Channel
Channel
Channel
Channel

VIN
VIN
VIN
VIN

1

2
2
1

"ON" = 2.0V
"ON" = O.SV
"OFF" = 2.0V
"OFF" = O.8V

Channels
Channels
Channels
Channels

SWITCH STATES ARE
FOR LOGIC "1" INPUT = 2.0V

SWITCH STATES ARE
FOR LOGIC "1" INPUT = 2.0V

3-26
Note: All typical values have been guarantaed by characterization and are not lested.

1
3
3
1

&
&
&
&

2
4
4

2

.U~Ulbi

DG200/lH5200
CMOS Dual SPST
A.nalog Switches

......

i

UI

N

GENERAL DESCRIPTION

FEATURES

The DG200llH5200 solid state analog gates are designed using an improved, high voltage CMOS monolithic
technology. They provide ease-of-use and performance
advantages not previously available from solid state
switches. Destructive latCh-Up of solid state analog gates
has been eliminated by INTERSIL's CMOS technology.
The DG200 is completely spec and pin-out compatible
with the industry standard device, while the IH5200 offers
significantly enhanced specifications with respect to ON
and OFF leakage currents, switching times, and supply
current.

•
•
•
•
•
•
•

8

Switches Greater Than 28Vpp Signals With ±15V
Supplies
Break-Before-Make Switching toff 250ns, ton
700ns Typical
TTL, DTL, CMOS, PMOS Compatible
Non-Latching With Supply Turn-Off
Complete Monolithic Construction
Industry Standard (DG200)
Improved Performance Version (IH5200)

ORDERING INFORMATION
INDUSTRY
STANDARD
PART

IMPROVED
SPEC
DEVICE

DG200AA

IH5200MTW

10-Pin Metal Can

-55°C to + 125°C

DG200AK

IH5200MJD

14-Pin CERDIP

_55°C to + 125°C

DG200AL

IH5200MFD

14-Pin Flat Pak

DG200BA

IH5200lTW

10-Pin Metal Can

TEMPERATURE
RANGE

PACKAGE

55°C to + 125°C
.- 25°C to + 85°C

DG200BK

IH5200lJD

14-Pin CERDIP

- 25°C to + 85°C

DG200BL

IH5200lFD

14-Pin Flat Pak

-25°C to + 85°C

DG200CJ

IH5200CPD

14-Pin Epoxy Dip

CERDIP & EPOXY DUAL-IN-LINE
PACKAGE (outline dwgs JD, PO)

O°C to +70°C

METAL CAN PACKAGE

FLAT PACKAGE

(outline dwg TO-l00)

(outline dwg FD-2)

v+ (SUasTRATI-ANO CASE)

"
I.., 5~~~iF~E'N'

NC

NC

y+

GND

(SUBSTAATE)

NC

Ne

NC

12

Ys~BSTRATE)
'HIe

'" ~~~-.......--~,-- ¥,

'"

y- =~=rr::""::;~E.= D,
V REF

s.

CDOQ1401

TOP VIEW

SWITCH STATES ARE FOR LOGIC
"'" INPUT (POSITIVE LOGIC)
CDOO1501

C0001301

Figure 1: Pin Configurations

3--27

Note: All typical values have been guaranteed by characterization and are not tested.

.•O~OIl

8 DG2001lH5200
(II

10

!

§

"
D

..

.

..

ABSOLUTE MAXIMUM RATINGS
V+-V'- ........................................................ <33V
v+ -Vo ........................................................ < 30V
Vo-V- .........................., .............................. < 30V
Vo-Vs ........................................................ < ±22V
VIN-GND ...................................................... < 20V
Current (Any Terminal) ................................. > 30mA

Storage Temperature ...................... -65'C to + 150'C
Operating Temperature ........•..•....... -55'C to + 125'C
Lead Temperature (Soldering, 10sec) ................. 300·C
Power Dissipation .. : ...................................... 450mW
(All Leads Soldered to a P.C. Board.) Derate 6mW I"C Above 75·C.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. and functional
operation of the device· at thaseor any other Conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

GATE
PROTECTION
RESISTOR
INPUT

LD001501

Figure 2: Functional Diagram (1/2 DG200/1H5200)

DG200 ELECTRICAL CHARACTERISTICS (TA = 25'C, v+ = +15V, v-

MINIMAX LIMITS

PER CHANNEL

SYMBOL

CHARACTERISTIC

= -15V)

TEST
CONDITIONS

MILITARY

COM'LIINDUSTRIAL

UNIT

-55'C

+2S'C

+ 12S'C

+2S'C

+70'C!
+8S'C

±I

±10

±.10

±10

p.A

±IO

±10

I'A

80

100

n

01
-2S'C

IIN(ON)

Input Logic Current

VIN = O.8V See Note I

±10

IIN(OFF)

Input Logic Current

VIN = 2.4V See Note 1

±10

±1

±10

rOS(ON)

Drain-Source On
Resistance

Is=10mA
VANALOG = ±10V

70

70

100

rOS(ON)

Channel-to-Channel
rOS(ON) Match

25
(typ)

30
(typ)

n

VANALOG

Min. Analog Signal
Handling Capability

±tS

±15

V

IO(OFF)

Switch OFF Leakage
Current

VANALOG = -14V to
+14V

±2

100

±5

100

nA

IS(OFF)

Switch OFF Leakage
Current

VANALOG = -14V to
+14V

±2

100

±5

100

nA

200

±10

200

nA

80

IOION)
+ S(ON)

Switch ON Leakage
Current

Vo=Vs= -14V to
+14V

±2

ton

Switch "ON" Time
See Note 1

RL = 1kn, VANALOG
= -10V to + 10V
See Fig. 3

1.0

1.0

I'S

toff

Switch "OFF" Time

RL = 1kn. VANALOG
=-10Vto +10V
See Fig. 3

0.5

0.5

I'S

Q(INJ.)

Charge Injection

See Fig. 4

15

20
(typ)

mV

(typ)

3-28
Note: All typical values have been guaranteed by characterization and are not tested.

DG2001lH5200
PER CHANNEL

SYMBOL

CHARACTERISTIC

MINIMAX LIMITS
MILITARY

TEST
CONDITIONS

-55°C
OIRR

Min. Off Isolation
Rejection Ratio

1= IMHz. RL = 100n.
CL::; 5pF
See Fig. 5 (Note I)

IVI

+ Power Supply
Quiescent Current

VIN =OV or
VIN = 5V

- Power Supply

IV2

COM'L/INDUSTRIAL

+ 125'C

+25°C

01
-2S'C

+2S'C

UNIT

+70'CI
+85'C

50
(typ)

54
(typ)

dB

1000

1000

2000

1000

1000

2000

IlA

1000

1000

2000

1000

1000

2000

IlA

Quiescent Current

CCRR

Min. Channel to
Channel Cross
Coupling Rejection
Ratio

One Channel 011

54
(typ)

dB

50
(typ)

NOTE 1. Pull Down ReSistor must be ::; 2kn
NOTE 2: Typical values are lor design aid only. not guaranteed and not subject to production testing.

IH5200 ELECTRICAL CHARACTERISTICS

(@ 25°C, V+ = +15V, V- = -15VREF open)

PER CHANNEL

SYMBOL

CHARACTERISTIC

MINIMAX LIMITS
TEST
CONDITIONS

MILITARY

COM'L/INDUSTRIAL

-SS'C

+2S'C

+ 125'C

01
-2S'C

+ 25'C

+70'CI
+85'C

UNIT

I'N(ON)

Input Logic Current

Y,N =0.8V

±10

±I

±IO

±10

'±10

p.A

I'N(OFF)

Input Logic Current.

Y,N = 2.4V

±IO

±1

10

±10

±10

p.A

rOS(ON)

Drain·Source On
Resistance

IS·,OmA
VANALOG = ±IOV

70

70

100

80

100

rOS(ON)

Channel·to·Channel
rOS(ON) Match
Min. Analog Signal
Handling Capability

VANALOG

80

"

n

25
(typ)

30
(typ)

n

±15
(typ)

±15
(typ)

V

IO(OFF)

Switch OFF Leakage
Current

VANALOG= -14V to
+14V

±I

50

I

±2

50

nA

IS(OFF)

Switch OFF Leakage
Current

VANALOG= -14V to
+14V

±I

50

I

±2

50

nA

IOION)
+ S(ON)

Switch ON Leakage
Current

Vo=Vs= -14V to
+14V

±1

100

I

±2

100

nA

Ion

Switch "ON" Time
See Note 3

RL = I kn, VANALOG
= -10V to + 10V
See Fig. 3

0.7

0.8

IlS

Ioff

Switch "OFF" Time

RL = Ikn, VANALOG
= -IOV to +IOV
See Fig. 3

0.25

0.4

p.s

Q(INJ.)

Charge Injection

See Fig. 4

5
(typ)

10
(typ)

mV

OIRR

Min. Off Isolation
Rejection' Ratio

1= lMHz. RL = loon.
CL::; 5pF
See Fig. 5

54
(typ)

50

dB

(typ)

IVI

+ Power Supply
Quiescent .Current

Y,N - OV or
Y,N = 5V

IV2

- Power Supply
Quiescent Current

CCRR

Min. Channel to
Channel Cross
Coupling Rejection
Ratio

250

200

150

300

250

200

p.A

10

10

100

10

10

100

p.A

One Channel Off

54
(typ)

3-29
Note: All typical values have bean guaranteed by characterization and are not tested.

50
(typ)

dB

I

gDG200/lH6200
(II

I
::.

8

I

.J

TEST CIRCUITS

WLOGINPUT

w-OINPU'

-:

F"r;;;..

Stu

11.
'
• := -D--\>-W

r~
':'.

m

_OGINNT

LOGIC INPUT

,

CNO~_

It-I

":'

':'

t-~'
'oou

':"

TC003601

TC003701

Figure 3

TC004111

Figure 4

Figure 5

NOTE 3: All channels are turned off by high" 1" logic inputs and all channels are turned on by low "0" inputs; however Q,8V to 2AV describes the min, range
for switching properly, Peak input current required for transition is typically -120/LA,

TYPICAL, PERFORMANCE CHARACTERISTICS
rOS(on) vs VD and Power
Supply Voltage

rDS(on) vs VD
and Temperature
H-+++'
lGO

+.;.
V + = + 15V
' ;' V- =-15V

A-

v· = • 15V. V - = - llV

• - .... :::. • 12Y. V - ::; - 12V
C-Y· ,.10\1.\;-=-1011

__Y_.___.~~,v__-_=_-_._v~

o~_O_-

o~~~~~~~~~

-15-10 -5

0

5

10

15

~

- IS -'0

Yo - DIWH VOLTAGE (VOLTS)

Vo -

5

0

10

OPOO7101

0P003201

IS(off) or lD(off)
vs Temperature·

ID(on)
vs Temperature·

10

15·

DIlAiN VOLTAGE /VOLTS)

aI_

1°~R
~~-+--. ''1

0.1

!':

:

I'

:

I

,...-

,~.~/.~.~'~!~~'~:~~
1,

~: :-: IT---.-++i I
;.

0.01
' i
25 45

I

.1

:

as

as

10S

125

T - TEMPERATURE C·e)
OPOO7201

OPOO7301

3-30
Note: All typical values have been guaranteed by characterization and are not

tested~

DG200/lH5200
APPLICATIONS

V+
Supply
(V)

Using the VREF Terminal
The DG200 has an internal voltage divider setting the
TTL threshold on the input control lines for V + equal to
+ 15V. The schematic shown here with nominal resistor
values, gives approximately 2.4V on the VREF pin. As the
TTL input signal goes from +O.8V to +2.4V, 01 and 02
switch states to turn the switch ON and OFF.

+ 15
+ 12
+ 10
+9
+8
+7

If the power supply voltage is less than + 15V, then a
resistor must be added between V + and the VREF pin, to
restore + 2.4V at VREF. The table shows the value of this
resistor for various supply voltages, to maintain TTL compatibility. If CMOS logic levels on a + 5V supply are being
used, the threshold shifts are less critical, but a separate
column of suitable values is given in the table. For logic
swings of -5V to +5V, no resistor is needed.

TTL
Resistor
(kU)

-

-

-

100
51

-

(34)

34

(27)
18

27
18

V· (+15V)

r-... t--t-::o:-

In general, the "low" logic level should be < O.8V to
prevent Q1 and 02 from both being ON together (this will
cause incorrect switch function). With open collector logic,
and a low value of pull-up resistor, the logic "low" level can
be above O.8V. In this case, INTERSIL can supply parts with
thresholds> 1.5V, allowing the user to define the "low"
as < 1.5V (consult factory). The VREF point should be set at
least 2.6V above this "low" state, or to > 4.1V. An external
resistor of 27kn between V + and VREF is required, for a
+ 15V supply.

}~

GATE
PROTECTION
INPUT RESISTOR

AFOOO6QI

Figure 6.

3-3.1

Note: All typical values have been guaranteed by characterization and are not tested.'

CMOS
Resistor
(kU)

o DO:201/IH5201

i

Quad SPST
~ CMOS Analo~ 'Swi~ch

'

..

g

GENERAL' DESCRIPTION

FEATURES

The DG20111H5201 solid-state analog switches are designed using an improved, high-voltage CMOS monolithic
technology. They provide performance' advantages not
previously available from solid-state switches. Destructive
latch-up .of solid-state analog gates has been eliminated by
INTERSIL's CMOS technology.
The DG201 is completely specification and pin-out com, patible with the industry standard device, while the IH5201
offers significantly enhanced specifications with respect to
ON and OFF leakage currents, switching times, and supply
current.

•
•
•
•
•
•
•

SlIIIltches Greater Than 28Vp_p Signals With ±15V
Supplies
'
.,
Break-Before-Make Switching toff 250ns,
ton Typically 500ns
'
TTL, OTt, CMOS, PMOS Compatible
Non-latching With Supply Turn-Qff
Complete Monolithic .Construction
Industry Standard (OG201)
Improv!td Performance Version IH5201

=

=

ORDERING INFORMATION
INDUSTRY
STANDARD
PART NUMBER

IMPROVED SPEC
PART NUMBER

TEMPERATURE
RANGE

PACKAGE

DG201AK

IHS201MJE

-SS·C to + 12S·C

,16-Pin CERDIP

DG201BK

IHS2011JE

-2S·C to +8S·C

16-Pin CERDIP

DG201CJ

IHS201CPE

O·C to +70·C

16·Pin PlastiC DIP

,

52

V + (SUBSTRATE)

VREF
D3
GATE
PROTECTION

RESISTOR

INPUT

CDOO1601

LOOO1601

Figure 1: Functional Diagram
(1/4 DG201/1H5201)

Figure 2: Pin Configuration
(Outline dwgs JE, PEl
DUAL-IN-LINE PACKAGE

Switch Open For Logic "1" Input

'3-32

Note: All typical values have been guaranteed by characterization and are not tested.

DG201/IH5201

g

ABSOLUTE MAXIMUM RATINGS

......

~
...

V+ to v- .................................................... < 33V
v+ to VD .................................................... < 30V
Vo to v- .................................................... < 30V
VD to Vs ................................................... < ±22V
VREF to v- ................................................. < 33V
VREF to VIN ................................................. < 30V
VREF to GND ............................................... < 20V

VIN to GND ................................................. < 20V
Current (Any Terminal) ................................. < 30mA
Storage Temperature ...................... -65°C to + 150°C
Operating Temperature ................... -55°C to + 125°C
Lead Temperature (Soldering, 10sec) ................. 300°C
Power Dissipation ......................................... 450mW
Derate 6mW rc Above 70°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specificatIons is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

DG201 ELECTRICAL CHARACTERISTICS (TA = 25°C, V+ = + 15V, V- = -15V)
PER CHANNEL

SYMBOL

MINIMAX LIMITS
TEST
CONDITIONS

CHARACTERISTIC

= O.SV
= 2.4V

MILITARY

COMMERCIAL

UNIT

-55'C

+25'C

+ 12S'C

O'C

+2S'C

+70'CI
+85'C

See Note 1

10

±1

10

±t

±1

10

p.A

See Note 1

10

±1

10

±1

±1

10

#LA

80

80

125

100

100

125

51

I'N(ON)

Input Logic Current

Y,N

I'N(OFF)

Input Logic Current

Y,N

ROS(ON)

Drain·Source On
Resistance

IS= 10mA
VANAlOG = ±10V

ROS(ON)

Channel 10 Channel
ROS(ON) Match

25
(typ)

30
(typ)

VANAlOG

Analog Signal
Handling Capability

±15
(typ)

±15
(typ)

IO(OFF)

Switch OFF Leakage
Current

VANAlOG
+14V

= -14V

to

±1

100

±5

100

nA

IS(OFF)

Switch OFF Leakage
Current

VANAlOG
+14V

= -14V

to

±1

100

±5

100

nA

IO(ON)
+IS(ON)

Switch ON Leakage
Current

Vo = Vs = ±14V

±2

200

±S

200

nA

ton

Switch "ON" Time
See Note 2

Rl = 1kn. VANALOG
= -10V to + 10V
See Figure 3

1.0

1.0

p.s

toll

Switch "OFF" Time
See Note 2

Rl = 1kn. VANALOG
= -10V to +10V
See Figure 3

0.5

0.5

p.s

Q(INJ.)

Charge Injection

See Figure 4

15
(typ)

20
(typ)

mV

OIRR

Min. Off Isolation

f = 1 MHz. Rl = 10051.
CL" 5pF
See Figure 5

54
(typ)

50

dB

(typ)

Rejection Ratio

/0

+ Power Supply
Quiescent Current

10

-Power Supply
Quiescent Current

CCRR

Min. Channel to
Channel Cross
Coupling Rejection
Ratio

V,N =OV to 5V

51

"

V

2000

1000

2000

2000

1000

2000

p.A

2000

1000

2000

2000

1000

2000

p.A

One Channel Off

54
(typ)

NOTE 1: Typical values are for design aid only. not guaranteed and not subject to production testing.

3-33
Note: All typical values have been guaranteed by characterization and are not tested.

50
(typ)

dB

i

CII

~
...

o DG201/UtS201
~

110

Z
:::.

g

TEST CIRCUITS

r

m

ANALOG INPUT

g

AHAlOGIMPUT

....

,,-0....,
(Note 2)

J
r~h:

3.
0.I1.

5tU

_

r-'

LOQIC INPUT

(NO~_

= -D-I>-'0'-'1

":'

~-

.

1DOl!

TCOO391 I

TCOO411J

TC004001

Figure 3

-=-

Figure 4.

Figure 5

NOTE 2: All channels are turned off bihigh"1" logic inputs and all channels are turned on by low "0" inputs; however 0.8V to 2.4V describes the min. range
lor switching properly. Peak. input current required lor transition is typically -1201tA.

IH520t ELECTRICAL CHARACTERISTICS

(TA

= 25°C,

V+

PER CHANNEL

SYMBOL

CHARACTERISTIC

= +15V,

V- = -15V)

MINIMAX LIMITS
TEST
CONDITIONS

MILITARY

COMMERCIAL

-55'C

+25'C

+ 125'C

O'C

+25'C

UNIT

+70'CI

+85'C

IIN(ON)

Input Logic Current

VIN =0.8V

1

1

10

1

1

10

p.A

IIN(OFF)

Input Logic Cum;nt

VIN = 2.4V

1

1

10

1

1

10

ROS(ON)

Drain-Source On
Resistance

IS= 10mA
VANALOG = ± 10V

75

75

100

100

100

125

ItA
.11

ROS(ON)

Channel to Channel
ROS(ON) Match

25
(typ)

30
(typ)

.11

VANALOG

Analog Signal
Handling Capability

±15
(typ)

±15
(typ)

V

IO(OFF)'
IS(OFF)

Switch OFF Leakage
Current

VANALOG = -14V to
+14V·

±0.5

50

±2

50

nA

IO(ON)
+IS(ON)

Switch ON Leakage
Current

VO=VS=±14V

±0.5

100

£2

100

nA

ton

Switch "ON" Time
See Note 2

RL = 1kn., VANALOG
= -10V to +10V
See Figure 3

0.7

0.8

p.s

Ioff

Switch "OFF" Time
See Note 2

RL = 1k.l1, VANALOG
= -10V to +10V
See Figure 3

0.35

0.4

p.s

Q(INJ.)

Charge Injection

See Fig. 4

5
(typ)

10
(typ)

mV

OIRR

Min. Off Isolation
Rejection Ratio

1= 1MHz, RL = 100n.,
CL ~5pF
See Figure 5, (Note 1)

54
(typ)

50
(typ)

dB

10

+ Power Supply
Quiescent Current

VIN =OV to 5V

10

- Power Supply
Quiescent Current

CCRR

Min. Channel to
Channel Cross
Coupling Rejection
Ratio

One Channel Off
(Note 1)

1000

750

600

1500

1000

1000

ItA

10

10

100

20

20

200

ItA

54
(typ)

NOTE: Pull Down resistor must be ~ 2k.l1
NOTE: Typical values are lor design aid only, not guaranteed and not subject to production testing.

Note: All typical values have been guaranteed by characterization and are not tested.

50
. (typ)

dB

DG2011lH5201
TYPICAL PERFORMANCE CHARACTERISTICS
I
!

V+=+15V
V-, = -15V

D

100

,\.
C·"

125'C 1-=;;0;

SS'C

t;d...

B

.P

50

25' C 1;:;; ...

'"

A

= +15V. Y- = -15Y
Y+ = +12V. Y- = -12V
C - Y+ +IOY. Y- -lOY
D - Y + = +BV. Y - = -8Y

c-- A - Y+

r- B -

o r-

o

=

=

-15 -10 - 5 0
5 10 15
Vo - DRAIN VOLTAGE (VOLTS)

-15 -10 -5 0
5,10 15
Vo - DRAIN VOLTAGE (VOLTS)

OPOO7401
Temperature

OP007501

~

.s

iiI~

1°BflB

ZIII

~ ~~~~E3~~~~~

f""

I

~!
(,)(,)
Z

I~

-

g~0.111l1.
...

"

.§~

~

0.01

~......-'--'--'--'-"-'--.......

25

45

as

as

105

125
45

T - TEMPERATURE ('C)

as

as

105

125

T - TEMPERATURE ('e)

OPOO7601

0P00'7Ol

y+
Supply
(y)

APPLICATIONS

Using the VREF Terminal
The DG201 has an internal voltage divider that sets the
TTL threshold on the input control lines for V + = 15V. The
schematic is shown here, with nominal resistor values,
giving approximately 2.4V on the VREF pin. As the TTL input
Signal goes from + o.av to + 2.4V, 01 and 02 switch states
to turn the switch ON and OFF.

+15
+12
+ 10
+9
+8
+7

If the power supply voltage· is less than + 15V, then a
resistor needs to be added between V+ and VREF pin, to
restore + 2.4V at VREF. The table shows the value of this
resistor for various supply voltages, to maintain TTL compatibility. If CMOS logic levels with a + 5V supply are being
used, the threshold shifts are less critical, but a separate
column of suitable values is given in the table. For logic
swings of -5V to + 5V, no resistor is needed.

TTL

CMOS
Resistor
(kn)

Re$istor

fie!)

-

100
51
(34)

j

(27)
18

V'(+15VI

In general, the "low" logiC level should be < o.av to
prevent 01 and 02 from both being ON together (this will
cause incorrect switch function). With open collector logic,
and a low value of pull-up resistor, the logiC 'low' level can
be above o.av. In this case, INTERSIL can supply parts with
thresholds > 1.5V(consult factory). The VREF point should
be set at least 2.6V above this" low" state, or to > 4.1 V. An
external resistor of 27kn and VREF is required, for a .+. 15V
supply.

GATE
PROTECl'l011
'"PUT RESISTOR

AFOO070l

Figure 6

3-35
Note: All typical values have been guaranteed by characterization and are not tested,

-

34
27
18

;-1)02'1'1/1)0212
8 SPST 4-Channel Anal
.....

..

...
C\I

g

,. \)C!>,\'l'>

,'

.\.,V"""

,,0"" s·'

GENERAL DESCRIPTION

FEATURES

,.~.

The DG2ll and DG2l2 are low cost.\€~bs monolithic,
QUAD SPST analog switches. The,se can be used in
general purpose switching applications for communications,
instrumentation, process control arid compu~er peripheral
equipment. Both devices provide true bidirectional performance in the ON condition and will block signals to 30V
peak-lo-peak in the OFF condition. The DG2ll and DG212
differ only in that the digital control logic is inverted, as
shown in the truth table.
DG211 and DG2l2 are available in a l6-pin Dual-In-Line
plastic package and are rated for operation over D·C to
70·C.

•
•
•
•

Switches ± 15V Analog Signals
TTL Compatibility
Logic Inputs Accept Negative Voltages
RON. ~ 175 Ohm '

ORDERING INFORMATION
PART NUMBER

TEMPERATURE
RANGE

PACKAGE

DG2llCJ
DG2l2CJ

O·C to +70·C
O·C to +70·C

l6-Pin Plastic DIP
l6-Pin Plastic DIP

DG211

DG212

s,
IN,

S,

Dual·ln·LlRe Package

IN,
0,

0,

S2

S2
IN2

IN2
02

02

S3

S3

1N3

13

V+ (SUBSTRATE)

1N3'
03

'03

S4

S4
IN4

IN4

D4

04
80014301

TOP VIEW
CD032301

80014401

Figure 2. Pin Configuration

Four SPST Switches per Package

Switches Shown for Logic "1" Input
Truth Table

LOGIC

00211

DG212

0
1

ON
OFF

OFF
ON

. Logic "0" ::; 0.8V
Logic "1" 2: 2.4V

Figure 1: Functional Diagrams

:J,-36

Note: All typical values have been guaranteed by characterization and are not tested.

30702Q-<>01

s...

DG211/DG212

.......ICII

ABSOLUTE MAXIMUM RATINGS
V+ to v- ....................................................... 36V
VIN to Ground ............................................ V-, V+
VL to Ground ........................................ -0.3V, 25V
Vs or VD to V+ ......................................... 0, -36V
Vs or VD to V- ............................................ 0, 36V

Peak Current, S or D
(Pulsed at 1msec, 10% duty cycle max) ....... 70mA
Storage Temperature ...................... -65°C to + 125°C
Operating Temperature ........................ O°C to + 70°C
Lead Temperature (Soldering, 10sec) ................. 300°C
Power Dissipation (Package)'
16 Pin Plastic DIP" ................................. .470mW

V + to Ground ................................................. 25V
V- to Ground ................................................ -25V
Current, Any Terminal Except S or D ................. 30mA
Continuous Current, S or D .............................. 20mA

'Device mounted with all leads soldered or welded
to PC board.
"Derate 6.5mW/OC above 25°C

ELECTRICAL CHARACTERISTICS (TA = 25°C)
SYMBOL

TEST CONDITIONS
V1 = + 15V, V2 = -15V,
VL= +5V, GND

PARAMETER

LIMITS
UNIT
MIN1

Typ2

MAX

15

V

115

175

rI

O.ot

5.0

SWITCH
VANALOG

Analog Signal Range

V

ROS(ON)

Drain-Source On Resistance

Vo = ±10V. VIN = 2.4V - DG212
IS=lmA. VIN=0.8V - DG211

= -15V. VL = +5V

-15

IS(off)

Source OFF Leakage Current

10(oft)

Drain OFF Leakage Current

VIN = 2.4V
DG211
VIN =0.8V
DG212

10(ON)

Drain ON Leakage Current3

Vs = Vo = -14V. VIN = 0.8V. DG211
VIN = 2.4V. DG212

VS= 14V. VD= -14V
Vs - -14V. Vo -14V

-5.0

-0.02

-5.0

-0.02

-5.0

-0.15

-10

-0.0004

Vo = 14V. Vs = -14V
VO=-14V. VS=14V

0.01
0.1

5.0
5.0

nA

INPUT
IINH

Input Current With Input
Voltage High

IINL

Input Current With Input
Voltage Low

VIN
VIN

= 2.4V
= 15V

0.003
-1.0

VIN =OV

1.0

p.A

-0.0004

DYNAMIC
Ion

Turn-ON Time

Ioft1
toft2

Turn-OFF Time

CS(oft)

Source OFF Capacitance

Vs = OV. VIN = 5V. f

CO(oft)

Drain OFF Capacitance

Vo = OV. VIN = 5V. f = 1MHz 2

5

Co + S(on)
OIRR

Channel' ON Capacitance

Vo=Vs=OV. VIN=OV. f= lMHz2

16

See Switching Time Test Circuit5
Vs = 10V. RL = lkrl. CL = 35pF

460

1000

360

500

ns

450

OFF Isolation 4
Crosstalk
(Channel to Channel)

CCRR

= 1MHz

2

VIN = 5V. RL = lkrl.
CL = 15pF. Vs = tVRMS. f = 100kHz 2

5
pF

70
dB

90

SUPPLY
1+

Positive Supply Current

1-

Negative Supply Current

IL

Logic Supply Current

NOTES:

VIN

=0

and 2.4V

.1

10

.1

10

.1

10

p.A

1. The algebraic convention whereby the most negative value is a minimum. and the most positive is a maximum. is used in this data
sheet.
2. For design reference only. not 100% tested.
3. 10(on) is leakage from driver into "ON" switch.

~.

4. OFF Isolation = 2010g
Vs =
Vo
5. Switching times only sampled.

i~put to

OFF switch. VD

= oulput.

3-37
Note: All typical values have been guaranteed by characterization and are not tested.

e...
II)

"

DG211/DG212

;:....

Switch output waveform shown for Vs = constant with
logic input waveform as shown. Note the Vs may be + or as per switching time test circuit. Vo is the steady state
output with switch on. Feedthrough via gate capacitance
may result in spikes at leading and trailing edge of output
.
waveform.

I
I
"

+15V
SWITCH

INPUT

SWITCH

5,

OUTPUT

Vs = 'ov o - t - - - - i f

......1-<>_ _>--00 Vo

LOGIC
INPUT
(REPEAT TEST FOR IN2 IN3 ANO IN"

v-

Figure 4: Switching Time Test Circuit

WFQ27301

Figure 3: Switching Time Test Circuit
Logic shown for DG211. Invert for DG212.

+15V

TTL
INQ--'W.......H

-15V

+6V

LD012701

Figure 5: DG212 Schemat.ic (1/4 as shown)

3--38
Note: All typical values have been guaranteed by characterization and are not tested.

DGM181-191
High-Speed
CMOS Analog Switch
GENERAL DESCRIPTION

FEATURES

The OGM181 family of CMOS monolithic switches utilizes
intersil's latch-free junction isolated processing to combine
the speed of the hybrid OG 181 family with the reliability and
low power consumption of a monolithic CMOS construction.
These devices, therefore, are a cost effective replacement
for the OG181 family.
The OGM181 family has a high state threshold of 2.4V;
and a low state of + O.8V.
Very low quiescent power is dissipated in either the ON or
OFF state of the switch. Maximum power supply current is
10IlA from any supply, and typical quiescent currents are in
the 10nA range. OFF leakages are typically less than
200pA at 25°C.

•
•
•
•
•
•
•

Pin and Function Replacement for DG181 Family
Meets or Exceeds All DG181 Family
Specifications With Monolithic Reliability
Low Power Consumption
1nA Leakage From Signal Channel in Both ON
and OFF States
TTL. DTL, RTL Direct Drive Capability
ton. toff < 150ns. Break·Before·Make Action
Crosstalk and Open Load Switch Isolation
> 50dB at 10MHz (75U Load)

ORDERING INFORMATION
TYPE
Dual SPST
Dual DPST
SPOT
Dual SPOT

STANDARD
PART
NUMBER

STANDARD
PART
NUMBER

M X
AT 25°C

DGM161BX
DGM182AX
DGM182BX
DGM184BX
DGM185AX
DGM185BX
DGM187BX
DGM188AX
DGMl88BX
DGM190BX
DGM191AX
DGM191BX

DGMS181BX
DGMS182AX
DGMS182BX
DGMS181BX
DGMS185AX
DGMS185BX
DGMS187BX
DGMS188AX
DGMS188BX
DGMS190BX
DGMS191AX
DGMS191BX

50
50
75
50
50
75
50
50
75
50
50
75

o

ros!on)

M

181

L
A

LPACKAGE
A - lO-PIN METAL CAN
L - 14-PIN FLAT PACK
:
K - CERAMIC DIP
J - EPOXY DIP
TEMPERATURE RANGE
A - MILITARY,.-55°C to
+ 125°C
B - INDUSTRIAL -20°C to
+85°C

L -_ _ _ _ _

DEVICE TYPE

' - - - - - - - - - DRIVER
'------~---- CMOS ANALOG DRIVER

r--~---~--'----~v+

·ud. . t
s
lOO01401

NOTE: 1/2 of DGM182

Figure 1: Functional Diagram (Typical Channel)

3-39
Note: All Iypical values have been guaranteed by characterization and are not tested.

;;
.,.

,..

.

I

I

DUAL SPST (DGM181, 182)
Flat Package (FD-2)

Metal Can Package

C::::====::::;::;J
0,_..........-$,

Dual-In-Line Package

[ :;;::===';:4:3 5,

"'C

"'c

NC

Ne;
IN,

y+

VL

y-

c0000401
COOOOSOI

COOOO601

(OUTLINE DWGS DD, PD)

(OUTLINE DWG TOol00)

SWITCH STATES ARE FOR LOGIC "1" INPUT

DUAL DPST (DGM184, 185)
Flat Package
54

C:::==:::::::;:;;J

Dual-In-Line Package

"

53

D.
0,
5,
IN,

'',

y+

y-

v,

c:::====:J

OND
c0000701

CDOOO801

(OUTLINE DWG FD-2)

(OUTLINE DWGS DE, PEl

SWITCH STATES ARE FOR LOGIC "1" INPUT

Figure 2: Pin Configuration and Switching State Diagram

3-40
Note: All typical values have been guaranteed by characterization and are not tested.

aI:)

DGM181-191

...

I:
CD

SPDT (DGM187, 188)
Metal Can Package

Flat Package (FD-2)

Dual-In-Une Package

I.

NC
NC

NC

0,
52

.NC
VL

v-

V+

GND

COOOO901

COOO1001

c000110J

(OUTLINE DWG TO-100)

(OUTLINE DWGS DD, PD)

SWITCH STATES ARE FOR LOGIC "1" INPUT

DUAL SPDT (DGM190, 191)
Flat Package

Dual-In-line Package
IN,

Ne

v+
(SUBSTRA.TE)

11 Ne

s,

IN,

D,

v+
TOP VIEW
CDOO1201

COOO1301

(OUTLINE DWG FD-2)

(OUTLINE DWGS DE, PEl

SWITCH STATES ARE FOR LOGIC "1" INPUT

Figure 2: Pin Configuration and Switching State Diagram (Cont_)

3-41
Note: All typical values have been guaranteed by characterization and are not tested.

!

!

,......

·.D~

DGM181-f91

co ABSOLUTE MAXIMUM RATINGS
II

g

V+ -v- ............................................................ 36V
:V--VD ........................................................... 33V
VrrV- ............................................................ 33V
. VrrVs ............................................................. ±22V
VL-V- ............................................................ 36V
VL-VIN ............................ , .............................. 30V
VL-VGND ......................................................... 20V
VIN-VGND : ....................................................... 20V
GND-V- ......................................................... 27V

GND-VIN ......................................................... 20V
Current (Any Terminal) .................................... 30mA
Storage Temperature ...................... -65·C to +:150·C
Operating Temperature ................... -55·C to + 125·C
Lead Temperature (Soldering. 10sec) ................. 300·C
Power Dissipation' ................... 450 (TW). 750 (FLAT).
825(OIP)mW
'Device mounted with all leads welded or soldered to PC board. Derate
6mWI'C (TW); 10mWI'C (FLAT); l1mW/'C (DIP) above 7S'C.

. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage·to the ·device. These are stress ratings only. and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
PARAMETER

(v+ = + 15V. v- = -15V. VL = 5V. unless noted)

TEST CONDITIONS
(Note 1)

DEVICE NO.

A SERIES

-55'C

B SERIES

+25'C

+125'C

±1

UNIT

+25'C

+85'C

100

±2.0

200

nA

-20'C

SWITCH
IS(off)

10(011)

= -7.SV

DGMI81, 184. 187, 190

Vs = 7.SV, Vo
VIN-"OFF"

DGM182, 18S, 188, 191

Vs = 10V, VD - -10V
VIN "OFF"

±1

100

±2

200

nA

DGMI81, 184, 187, 190

VS" 7.5V, Vo - -7.5V
VIN-"OFF"

±1

100

±2

200

nA

DGMI82, 185, 188, 191

Vs = 10V, Vo
VIN = "OFF"

±1

100

±2

200

nA

VIN - "ON"

±2

±200

±S

500

nA

-10V, VIN - "ON"

±2

±200

±S

500

nA

20
20

10

20

10

20

IlA
IlA

=

= -10V

= -7.SV,

DGMI81, 184, 187, 190

VO" Vs

DGM182, 18S, 188, 191

Vo

IINL

ALL

VINcOV

±1.0

IINH
DYNAMIC

ALL

VIN-5V

±1.0

DGMI81, 184, 187, 190
DGMI82, 185, 188, 191

See switching time test circuit

10(on) + IS(on)

= VS"

INPUT

Ion

SOO

450

I

250

loll
CS(oll)

ALL
DGMI81, 182, 184, 185,

Vs - -SV, 10 =0, f- lMHz

CO(off)

187, 188, 190, 191

Vo - + SV, IS" 0, f .. 1MHz

6pF typical

Vo=Vs-O, f=IMHz

11 pF typical

COlon) + CS(on)
OFF Isolation

5pF typical

ALL

I

ALL

IL

pF

Typically> SOdS at 10MHz

RL .. 75n, CL = 3pF

SUPPLY
1+

ns

275

10

10

100

10

10

100

100

ALL

10

10

100

100

IGNO
1+

ALL

10

10

100

100

ALL

10

10

100

100

1-

ALL

10

10

100

100

IL

ALL

10

10

100

100

IGNO

ALL

10

10

100

100

VIN - 5V

VIN" OV

Note 1: See Switching State Diagrams for VIN and VIN "OFF" Test Conditions.

3-42
Note: All typical values have been guaranteed by characterization and are not tested.·

100

IlA

DGM181-191
ELECTRICAL CHARACTERISTICS
DEVICE
NUMBER
OGM181
OGM182
OGM184
OGM185
OGM187
OGM188
DGMI90
OGM191

MAXIMUM RESISTANCES rDS(ON)

=

Vo =
Vo=
VoVoVo=
Vo Vo'"
Vo =

=

-55°C

+ 25°C

-

-7.5V
-10V
-7.5V
-10V
-7.5V
-10V
-7.5V
-10V

INDUSTRIAL
TEMPERATURE

MILITARY TEMPERATURE

CONDITIONS (Note 1)
V+ 15V,V- -15V,VL= 5V

Is= -lOrnA
VIN = "ON"

-20°C

+ 25°C

+85°c

-

50
75
50
75
50
75
50
75

50
75
50
75
50
75
50
75

75
100
75
100
·75
100
75
100

-

50
30
50
30
50
30
50

UNIT

+ 125°C

50
30
50
30
50
30
50

75
60
75
60
75
60
75

n
n
n
n
n
n
n
n

APPLICATION COMMENT: The charge iniection in these switches is of opposite polarity to that of the standard OGI80 family, but considerably
smaller.

SWITCHING TIME TEST CIRCuiT
Switch output waveform shown for Vs = constant with
logic input waveform as shown. Note that Vs may be + or
- as per switching time test circuit. Vo is the steady state
output with switch on. Feedthrough via gate capacitance
may result in spikes at leading and trailing edge of output
waveform.
LOGIC
INPUT
tr< 10nl
tf< 10nl

3V--,

SWITCH
INPUT

Vs

SWITCH
OUTPUT

1/
~
J

1.5V~~

0

o.evo

~

..J

J

O.9Vo

O.1VO~
II

ton

toff
WFOO1111

Figure 3: Logic Input for "OFF" to "ON" Condition (DGM1811182 Shown)

SWITCH
INPUT

SWITCH
OUTPUT

SI
O-+--------~-------,

s,'''''+--t-""'; o-------~l-O
,,"o.+--+-~'i ...------+

s.'_'........_'" Oo-----~+~
$,'...'+--t-o"1 - - - -.....
"
"o>--1t--t--+-O"'j
o---t-t.....,

5.0-1---+--+---+--<,..-,
00----.
"
s,O'''+--+-f----t-~-''!

•.'...0+_--..,_+---+_'1

~'oo+--+-+-~-~~_o1
G.

G;

G,
05021001

0S021101

Figure 1: Functional Diagrams and Pin Configurations (Outline Dwgs DO, FD-2, JD, PO)
NOTE: G115 Built-in 16·Pin DIP Only.

3-45
Note: All typical values have been guaranteed by characterization and are not tested.

0115/G123
ABSOLUTE MAXIMUM RATINGS

(25°C)

Source Current (IS) ............... ~ ........................ 100mA
Drain Current (10) ..............•........................... 1OOmA
Gate Current (IG) ......................... : ................... 5mA
Pull-up Control Current (If).: ............................ 100pA
Body to Source (VB-VS .... , ................ -2V to +25V
Body to Drain (VB - Vo) ........................ -2V to + 25V

Body to Gate (VB - VG) ................................... +35V
Body to Pull-up (VB - Vp) ................................. + 35V
Power Dissipation
'
(derate 10mW/oCabove 70°C) .................... 750mW
Lead Temperature (Soldering, 10sec) ................. 300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(per channel unless noted)
LIMITS

DEVICE

PARAMETER

TEST CONDITIONS

ROS(ON)

-20°C

25°C

85°C

125

150

Vso = O. VGO = -30V

Ils=

125

VSO = + 10V. VGO = -20V

limA

250

250

300

500

500

600

VBO= +20V. VGO= -10V

n

Vos= -20V. Vss=VGS=Vps=O

-10

-500

Max

nA

VSO = -20V. VBO = VGO = VPO = 0

-5

-100

Max

nA

IGSS

VGS = -20V. Vos - VSB ~ VPB

=0

-5

-100

Max

nA

VGB = -30V. VPB = -30V. VOS = 0

-0.8

Min

-2.4

Max

mA

-1.5

-1.5

-1.5

Min

VBS= VpS = 0

-4

-4

Max

SVOSS

10 = -101lA. VGB = VSS = VPS = 0

-25

-:4
-25

-25

Min

V

BVsos

IS = -101lA. VGO = VBO = VPO = 0

-25

-25

-25

Min

V

-35

-35

-35

Min

V

-110

-110

-110

Max

V

-35

-35

-35

Min

V

-110

-110

-110

Max

V

Typ

pF

0.4

Typ

pF

18

Typ

pF

9

Typ

pF

3.5

Typ

pF

IS = -101lA. Voo = O.

IG = -101lA. Vos = Vss = VPB

BVGBS
BVpss

=0

Ip = -101lA. Vos = Vss = VGB = 0

GGS. GGO

VGB=O. Vss=O. VOB-O. VPB-O

GOS

f = 1MHz. Body Guarded

3

·

·

G115

.

Max

IS(OFF)

VGS(th)

G123

UNIT

10(OFF)

IG(ON)
G115
and

MINI
MAX

G123

GOB

VOB = -5V. VSB = VGB = VPB = 0
f=IMHz

Both

GSB

VSB = -5V. VOB = O. VGB = VPB = 0
f= lMHz

V

Typical values not garanteed or tested in production

TYPICAL PERFORMANCE CHARACTERISTICS
E

~

10'
VB~" OV

u

10

Z

<[

in

~

15

10'

,-f-'--

....

a:

u

10'

..

50

I

Is"

a:

100~A

Tp. '" 25 C
10



'"

w

>-

.-III p-

~

V SB " VGB,:-O

u

w

0

E

100

..

....
e;

1/

a:

u

::J

~
u
"'z

I-- -

f - ;----I{)
v!'!>

-5

o

V oo - DRAIN BODY VOL TAGE (VI

0P0372Ot

OP037301

3-46
Note: All typical values have been guaranteed by characterization and are not tested.

·
o

0
,3D

>

V(,S

25

20

15

lOO~A

0

-10

GATE SOURCE VOLTAGE (VJ
OP037401

G115/G123·
voltage to be switched (-10V). Therefore, VG should go to
-20V. To insure turn-off VG should not be less than the
most positive voltage to be switched, + 10V. For convenience the same potential as the body could be used.
B-Terminal- This terminal is connected to the body
(substrate) of the chip and must be maintained at a voltage
that is equal to or greater than the most positive voltage to
be switched. This is to ensure that the drain-to-body or the
source-to-body junctions do not become forward biased.
P-Terminal- The potential, with respect to the body, at
this terminal determines the gate-to-source voltage of 01
which determines the amount of drain current available for
driver-collector pull-up. Shorting terminal P to 8 prevents
01 and 03 from conducting, but still allows the body-todrain junction of 01 to act as a forward biased diode for
positive gate voltages, and to act as a Zener diode for
negative voltages which exceed BVOSS (-30 to -90V) for
protecting the gate of 02.
D-Terminal- The common point of the MOSFET
switches (summing point).
S-Terminal- This is the normally-open terminal of the
MOSFET switch and is normally used as the input.

APPLICATION TIPS

Description of Analog Switch
Single Channel

"''":
GATf

SC009201

Figure 3
G-Terminal- This is the control terminal of the switch.
The voltage at this terminal determines the conduction
state of 02. To insure conduction 01 02 when voltages
between ±10V are switched, the gate voltage (VG) should
be at least 10V more negative than the most negative

APPLICATIONS
Dual Current·to·Voltage Converter With Range
Programming

Channel Multiplexer

AF030901

Figure 4

3-47

Note: All typical values have been guaranteed by characterization and are not tested.

AF031001

S! G116,G118,
;; Monolithic
!MOSFET Switch

G119

C5

;. GENERAL DESCRIPTION

FEATURES

;

•
•
•

, These switches may be connected directly to the INTERSIL switch-driver D123 series without need of any interfacing components. These MOSFET switches are inh,~rnally
protected by a Zener diode integrated on the silicon chip. A
MOSFET used as a current source provides an active pullup for' faster switching. The active pull-up FET can be
disabled without sacrificing the Zener protection of the
gates.

r

P-Channel Enhancement-Type MOSFET Switches
Zener Protection on All Gates
With and Without Constant Current Source Pull-,
Up

ORDERING INFORMATION
G116

,~

Package
J - 14·pin Plastic DIP
K - 14-pin CERDIP
L - 14-pin Flat Package
P - 14·pin Hermetic DIP
(Special Order Only)
, L.,"-'- - -_ _ _ _ _ _ _ _ _ _ _
_ _ _ Temperature Range
A - Military (- 55°C to + 125°C)
B - Industrial (- 20°C to + 85°C)
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--,- Device Chip Type
.

~

G116

G118

LD011701

LD011801

G119

LD011901

Figure 1: Functional Diagrams (Outline DwgsPD, JD, FD-2, DO)

3-48
Note: All typical values have been guaranteed by characterization and are not tested,

......
!IJ

t;)

G116, G118, G119

......
~

t;)

ABSOLUTE MAXIMUM RATINGS (25°C)
Source Current (IS) ........................................ 1OOmA
Drain Current (I D) .......................................... 1OOmA
Control Gate Current IG ..................................... 5mA
Pull-Up Gate Current Ip .................................. 100J..lA
Body Voltage (Va) to Any Terminal .......... -2 to + 30V

Power Dissipation (Note) ................................ 750mW
Storage Temperature ...................... -55°C to + 150°C t;)
Operating Temperature ... , ............... -50°C to + 125°C :::
Lead Temperature (Soldering. 10sec) ................. 300°CCG

NOTE: Dissipation rating assumes device is mounted with all leads welded or soldered to printed circuit board in ambient temperature below + 70·C. For
higher temperatures, derate 1OmW I·C.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (Per Channel Unless Noted)
References to pull-up gate P do not apply to G 118.
LIMITS
PARAMETER

rOS(ON)
(Note 1)

TEST CONDITIONS

G116C Series

25°C

25°C

125°C

vso = 0, vGO = -30V, Vps = 0

IS=

100

125

125

VSO = + 10V, VGO = -20V, VPS = 0

-lmA

200

250

250

4S0

600

600

VSO- +20V. VGO= -10V. VPs-O

-O.S

-SOO

-1

G116

-2.S

-2S00

-S

VSO = -20V, VSO = VGO = VPO = 0

IS(OFF)

G116M Series

VOS= -20";
VSO - VGO - VPO = 0
10(OFF)
VG1S to VGSB - 0, VG6S - -30V,
VOS = -20V, VSS = VPS = 0

G116

-3.0

-3000

-6

Gl19

-1.S

-lS00

-3

Gl17

-O.S

-SOO

MINIMAX

UNIT

Max

n

Max

nA

Max

nA

nA

125°C

-1

Max

10 = -10pP., VGS = VSS = VPS = 0

-30

-30

Min

BVSOS

IS = -10pP., VGO = VSO = VpO = 0

-30

-30

Min

BVGSS

IG = -10pP., VPS = VSS = VOS = 0

-30

-30

Min

-110

-110

Max

-30

-30

Min

-110

-110

Max

-1.S

-1.S

Min

-4

-4

Max

-O.S

-0.3

Min

-2

-2.S

Max

BVOSS

Ip = -10pP., VGS = VSS = VOS = 0

BVpSS

/

Is. = -10pP., VOS = -10V, VSS = 0

VGO(th)
IGS(ON)

VGS = -30V, VPS = -30V, VSS = VOS = 0

(Note 2)
IGSS

VGS = -20V, Vos = VSS = VPS = 0

CGO or CGS

Vps = 0, VSS = 0, or VSO = 0

CSO (Note 3)

Body Guarded, f = 1MHz

CSS (Note 3)

VPS = VGS = VOS

= 0,

VpB = VGS = VSS = 0
COG (Note 3)

NOTES:

-1

Max

nA

3

Typ

pF

0.4

0.4

Typ

pF

-3.5

-3.S

Typ

pF

Gl16

18

16
Typ

pF

Typ

pF

VSB = -5V, f = lMHz
Gl18

18

18

G09

10

10

VG6S = -30V, VPB = VSB = 0, VG1S to Gl17
VGSB=O, VOS= -SV, f=lMHz

20

20

VOS = -SV, f = lMHz

rnA

3

-O.S

-500

V

1. For the G 117 this is the resistance from each of the source terminals (S terminals) and the one drain terminal to the internal
junction of the output MOSFETs.
2: Not applicable to G118.
3: Typical values not guaranteed or tested in production.

3-49
Note: All typical values have been guaranteed by characterization' and are not tested.

'G116, G118, G119

,;
;

.. TYPICAL PERFORMANCE CHARACTERISTICS
YD. - ORAIN·BODV VOLTAGE tvl

j

1e,;30 -25 -20

-15 -10

~ ~

~20
~

~~

i

0 100 ~

-5

.9

'-lMHz

w

10

~ ~

/20§

V,. -YG.-O

10

5
5

StNGLE SOURCE.
ALL TYPES

2

VOl· VG• -0

J

~z
~
I

I

1

-30

-25 -20

-15 -10

-5

0

V.. - SOURCE·BODY VOLTAGE (VI
QP057601

OP057701

I
;
i .,.
10'

i

fer'

a,r'
.

~

~::0

c III""

~<

~

~ 1Cf4

0

-10

I

-'0

:§

v•• -GATE-IOURCE VOLTAGE IV}

VG,-GATE·SOURCE VOLTAGE IV!

0P057801

OP0579ot

APPLICATiON TIPS

B-Terminal- This terminal is connected to the body (substrate) of the chip and must be maintained at
a voltage that is equal to or greater than the
most positive voltage to be switched. This is
to insure that the drain-to-body or the
source~to-body junctions do not become forward biased.

Description of Analog Switch

-~:~f[~
~
.

10'

c

.0"

GATE

.

P-Terminal- The potential, with respect to the body, at
this terminal determines the gate-to-source
voltage of Q1 which determines the amount
of drain current available for driver-collector
pull-up. Shorting terminal P to B prevents Q1
and Q3 from conducting, but still allows the
bOdy-to-drain junction of Q1 to act as a
forward biased diode for positive gate voltages, and to act as a Zener diode. for
negative voltages which exceed BVOSS (-30
to -110V) for protecting the gate of Q2.

OOIllAl"
AF037301

Figure 2: Single Channel
G-Terminal- This is the control terminal of the switch; the
voltage at this terminal determines the conduction state of Q2. To insure conduction of
Q2 when voltages between ± 1OV are
switched, the gate voltage (VG) should be at
least 10V more negative than the most
negative voltage to be switched (-1 OV).
Therefore, VG should go to -20V. To insure
turn-off VG should not be less than the most
pOSitive voltage to be switched, + 10V. For
convenience the same potential as the body
could be used.

D-Terminal- The common pOint of the MOSFET switches
(summing point).
S-Terminal - This is the normally-open terminal of the
MOSFET switch and is normally used as the
input.

3-50
Note: All typical values have been guaranteed by characterization and are not tested.

G116, G118, G119
APPLICATIONS

r

........ ~OG

o-:::.t-+---d'f - - - - +

-r::-....-i

O'~~!:\I":':'+-+--+--'f "---4i-*"r...

L

-+---t----~

"",+-+"

..

"'. 1i,_I\I,

AF037501

AF037401

Figure 3: S-Channel Multiplexer
With Series Switch

Figure 4: 3-Channel Differential Multiplexer

3-51
Note: All typical values have been guaranteed by characterization and are not tested.

~ IH3'11/IH312

~

High Speed SPST
; 4-ChannelAnalog S
z

-

"\(>\...

,;;.,v.\;.,/;("l.

GENERAL DESCRIPTION".>""·"

FEAtURES

The IH311 and IH312 are CMO'S;"'<~onolithic, QUAD,
SPST analog switches for use in high-speed switching
applications for communications, instrumentation, process
control and computer peripherals. Both devices provide true
bi-directional performance in the ON condition and will
block signals to 30V peak-to-peak in the OFF condition. The
IH311 and IH312 differ only in that the digital control logic is
inverted, as shown in the truth table.
IH311 and IH312 are available in 16-pin Dual-In-Line
packages and are offered in both military and commercial
temperature ranges.

IH311

•
•
•
•

Switches ± 15V Analog Signals
TTL Compatibility
Logic Inputs Accept Negative Voltages
RON ~ 175 Ohm

ORDERING INFORMATION
PART NUMBER

TEMPERATURE
RANGE

PACKAGE

IH311MJE

-55·C to + 125·C

16 Pin CERDIP

IH311CJE

D·C to +70·C

16 Pin CERDIP

IH311CPE

D·C to +70·C

16 Pin Plastic DIP

IH312MJE

-55·C to + 125·C

16 Pin CERDIP

IH312CJE

O·C to +70·C

16 Pin CERDIP

IH312CPE

O·C to +70OC

16 Pin Plastic DIP

IH312

S1

S1

DUAl·II·LlNE PACKAGE

IN1

IN1
01

01

S2

S2
IN2

IN2

02

02

S3

S3
IN3

IN3
D3

03

S4

S4
IN4

IN4

04

04

TOP VIEW

00035301

CD035401

COO35501

Figure 2: Pin Configuration
(Outline dwgs DE, PEl

Four SPST Switches per Package

Switches Shown for Logic "1" Input
Truth Table
LOGIC

IH311

IH312

0
1

ON
OFF

OFF
ON

Logic "0":0; O.SY
Logic "1" ~ 2.4Y

Figure 1: Functional Diagram

3-52
Note: All typical values have been guaranteed by characterization and are not'· tesled.

307040-001

ABSOLUTE MAXIMUM RATINGS
V+ to V- ............................................... ; ....... 36V
VIN to Ground ........................................... V+, V+
VL to Ground ........................................ -0.3V, 25V
Vs or VD to V + ......................................... 0, -36V
Vs or Vo to V- ............................................ 0, 40V

Peak Current, S or D
(Pulsed at 1msec, 10% duty cycle max) ....... 70mA
Storage Temperature ................... ; .. -65°C to + 125°C
Operating Temperature ................... -55°C to + 125°C
Power Dissipation (Package)"
.
16 Pin Plastic DIP"" ................................. .470mW

V + to Ground ................................................. 25V
V- to Ground ................................................ -25V
Current, Any Terminal Except S or D ................. 30mA
Continuous Current, S or D .............................. 20mA

ELECTRICAL CHARACTERISTICS SYMBOL

"Device mounted with all leads soldered or welded
to PC board.
"·Derate 6.5mWrC above 25°C

MILITARY TEMPERATURE RANGE
TEST CONDITIONS
V1 = + 15V, V2 = -15V
VL=5V, GND

PARAMETER

LIMITS
UNIT
-55°C

+ 25°C

+ 125°C

SWITCH
VANALOG
ROS(ON)

= +5V

Analog Signal Range

V- = -15V, VL

Drain-Source On Resistance

Vo = ±10V, VIN = 2.4V - IH312
IS = lmA, VIN = O.BV - IH311

Source OFF Leakage Current

±15
125

150

±1

100

VS- -14V, VO-14V

±1

100

Vo -14V, Vs - -14V

±1

100

= 14V

±1

100

±2

200

±2

200

IO(off)

Drain OFF Leakage Current

IO(ON)

Drain ON Leakage Current3

Vs = Vo = -14V, VIN
VIN = 2.4V, IH312

Vo - -14V, Vs

= O.BV,

125

V

Vs -14V, Vo = -14V

VIN = 2.4V
IH311
VIN = O.BV
IH312

IS(off)

IH311

n

nA

INPUT
IINH

Input Current With Input
Voltage High

IINL

Input Current With Input
Voltage Low

..-...

.O~Oll ifit

IH311/IH312

= 2.4V

10

±1

10

VIN = 15V

10

±1

10

VIN=OV

10

10

10

VIN

3-53
Note: All typical values have been guaranteed by characterization and are not tested.

p.A

ifit

...
N

.D~OIL
Ion

Tum·ON Time

IotIl

Tum-OFF T'"1e

200

see

Switching Time Test Circuit
Vs = 10V, RL = lkn, CL - 35pF

,1otI2

80

Cs(olf) ,

Source OFF Capacitance
Drain OFF Capacitance

Vs = OV, VIN - 5V, f-1MHz
Vo;'OV, VIN=5V, f= lMHz2

5

CO(oIf)
Co + S(on)
OIRR

Channel ON Capacitance

Vo-VS-OV, VIN-OV, f-1MHz

16

'OFF Isolation4

5

pF

70

VIN = 5V, RL - lkfl,
CL = 15pF" Vs - lVRMS, f = 100kHz 2

Crosstalk
(Channel to Channel)

CCRR

dB

90

"

SUPPLY
1+
1-

Negative Supply, Current

IL

logic Supply Current

NOTES:

ns

"

Positive Supply Current
VIN = 0 and 2.4V'
"

10

1

10

10

1

10

10

1

10

pA

1. The algebraic co,mientionwhereby the most negative value is a minimum, and the most positive is a m'aximum, is used in this data
sheet.
'
2. For design reference, only" not 100% tested.
3. 10(on) is leakage 'from driver into "ON" switch.

4. OFF Isolation - 2010g Vs , Vs = Input to OFF switch, Vo = output.
,VO

3-54
Nota: All typical values have been guaranteed by characterization and are not tested.

~

-......
C')

,IH311/IH312

:z:

...... ABSOLUTE MAXIMUM RATINGS

!

V+ to v- ....................................................... 36V
VIN to Ground ........................................... V+. V+
VL to Ground ........................................ -0.3V. 25V
Vs or VD to V+ ......................................... 0. -36V
Vs or VD to V- ............................................ 0. 40V

Peak Current. S or D
(Pulsed at 1msec. 10o/~ duty cycle max) ....... 70mA
+125°C
storage Temperature ...................... -65°C
Operating Temperature ........................ OOG to + 70°C
Power Dissipation (Package)'
16 Pin Plastic DIP" .................................. 470mW

'0

V + to Ground ................................................. 25V
V- to Ground ................................................ -25V
Current. Any Terminal Except S or D ................. 30mA
Continuous Current. S or D .............................. 20mA

ELECTRICAL CHARACTERISTICS SYMBOL

'Device mounted with all leads soldered or welded
to PC board.
"Derate 6.5mWrC above 25°C

COMMERCIAL TEMPERATURE RANGE
TEST CONDITIONS
V1 = + 15V, V2 = -15V,
VL=5V, GND

PARAMETER

LIMITS
UNIT

+ 25°C

+ 70°C

SWITCH
VANALOG

Analog Signal Range

V- = -15V, VL = +5V

±15

ROS(ON)

Drain-Source On Resistance

Vo = ±10V, VIN = 2.4V - IH212
IS" 1mA, VIN = O.BV - IH211

150

175

Source OFF Leakage Current

±5

100

Vs = -14V, Vo = 14V

±5

100

Drain OFF Leakage Current

Vo -14V, VS'- -14V

±5

100

IO(of!)

VIN = 2.4V
IH311
VIN -O.BV
IH312

Vs -14V, Vo = -14V

IS(oft)

Vo - -,14V, Vs = 14V

±5

100

Drain ON Leakage Currenfl

Vs = Vo = -14V, VIN = O.BV, IH211
VIN * 2.4V, IH212

±5

200

±5

200

VIN = 2.4V

±1

-10

VIN = 15V

±1

10

VIN =OV

±1

-10

IO(ON)

V
n

nA

INPUT
IINH

Input Current With Input
Voltage High

IINL

Input Current With Input
Voltage Low

p.A

DYNAMIC
Ion

Turn-ON Time

Ioft1
10112

Turn-OFF Time

See Switching Time Test Circuit 5
Vs = 10V, RL = 1kn, CL = 35pF

CS(of!)

Source OFF Capacitance

Vs = OV, VIN = 5V, f = 1MHz

5

CO(of!)

Drain OFF capacitance

Vo = OV, VIN = 5V, f = 1MHz2

5

CO+S(on)
OIRR

Channel ON Capacitance

Vo=Vs=OV, VIN-OV, f=1MHz

16

OFF Isolation4
Crosstalk
(Channel to Channel)

CCRR

VIN = 5V, RL = 1kn, CL = 15pF,
.
Vs = 1VRMS, f = 100kHz 2

300
150

ns

pF

70
dB

90

SUPPLY
1+

Positive Supply Current

1-

Negative Supply Current

IL

Logic Supply Current

NOTES:

VIN = 0 and 2.4V

±1

10

±1

-10

±1

10

p.A

1. The algebraic convention whereby the most negative value is a minimum, and the most positive is a maximum, is used in this data
sheet.
2. For design reference only, not 100% tested.
3. 10(on) is leakage from driver into "ON" switch.
4. OFF Isolation = 20log Vs , Vs = input to OFF switch, Vo = output.
Vo
5. Switching times only sampled.

3-55
Note: All typical values have been guaranteed by characterization and are not tested.

Switch output wav!lform shown for Vs = constant with
logic input waveform as shown. Note the Vs may be + or as per switching ~ilT1e test circuit. Vo istl)e 'steady state
output with sWitch on. Feedthroughvia gate bapacitance
may resulUri spikes at leading and trailing' edge of output
waveform. '
, ' , '.
.

f

LOGIC·
INPUT (IN 1) -::\.0

~"'o ~

t,< 20 n5
tf < 20 n5

_ - - - - - - ,~

SWITCH Vs
INPUT

I lof11
_---1~----_-.,.___---J-+--_+_-­
0,9 Vo

SWITCH

OUTPUT (VO) ____~--J
ton

J

'off2

Figure 3: Switching Time Test Circuit
LogiC shown for IH311. Invert for IH312.

Note: All typical values have been guaranteed by characterizatioo:and ·are· noLiested.,:.,." ". "

IID~OIb

IH311/IH312

!

:t

..

I

,(,a

N

+ 15V

+5V
SWITCH
INPUT

Vs

VL

V+
SWITCH
OUTPUT

S1

= 10V D - - t - - - - - - ( y

a-~cr-.--~--o

I

LOGIC
INPUT

Vo

CL
36pF

(REPEAT TEST FOR IN2 IN3 AND IN4)

V-15V
RL

VO=VS
RL

+

rDS(on)

Figure 4: Switching Time Test Circuit

3-57

Note: All typical values have been guaranteed by characterization and are ,not tested..

+16V

TTL
IN~-'W

__r l

+6V

LOO12701

Figure 5: IH311 Schematic (114 as shown)

3-58
Note: All typical values have been guaranteed by characterization and are not tested.

IH4011lH401A
QUAD Varafet Analog Switch
GENERAL DESCRIPTION

FEATURES

The IH401 is made up of 4 monolithically constructed
combinations of a varactor type diode and an N-channel
JFET. The JFET itself is very similar to the popular 2N4391,
and the driver diode is specially designed, such that its
capacitance is a strong function of the voltage across it.
The driver diode is electrically in series with the gate of the
N-channel FET and simulates a back-to-back diode structure. This structure is needed to prevent forward biasing the
source-to-gate or drain-to-gate junctions of the JFET when
used in switching applications.
Previous applications of JFETs required the addition of
diodes, in series with the gate, and then perhaps a gate-tosource referral resistor or a capacitor in parallel with the
diode; therefore, at least 3 components were required to
perform the switch function. The IH401 does this same job
in one component (with a great deal better performance
characteristics).
Like a standard JFET, to practically perform a solid state
switch function a translator should be added to drive the
diode. This translator takes the TTL levels and converts
them to voltages required to drive the diode/FET system
(typically a OV to -15V translation and a 3V to + 15V shift).
With ±15V power supplies, the IH401 will typically switch
18~_p at any frequency from DC to 20M Hz, with less than
30H RDS{on). The IH401A will typically switch 22Vp_p with
less than 50n RDS{on).
.

• . ROS{on) 25n Typical (IH401)
• ID{Off) of 10pA Typical
• Switching Times of 25ns for ton and 75ns for
toff (RL 1kn)
• Built-In Overvoltage Protection (±25V)
• Charge Injection Error of 3mV Typical Into
0.01 IlF Capacitor
• Ciss < tpF Typical
• Can Be Used for Hybrid Construction

=
=

ORDERING INFORMATION
PART NUMBER

PACKAGE

IH401

CERDIP

IH401A

CERDIP

IH401/D

DICE

CD030801

Figure 1: Pin Configuration
(Outline Dwg JE)

3-59
Note: All typical values have been guaranteed by characterization ana,'are.not tested.·

IH401IIH~01A "

Storage Temperature ......................., -65°C to + 150°C
Lead Temperature (Soldering: 10sec) ................. 300°C

Vs to VD .. · ..... ··· .......... · .......................... ,.........,35V
VG to VS, VD ................................................•. 35V
Operating Temperature ................... -55°C to + 125°C

Stresses abQve those listed under Absolute Maximum Ratings may cause permanent damage to the device. Th",se are stress ratings only. and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS AT 25°C/125°C
IH401
SYMBOL

CHARACTERISTIC

UNIT

TEST CONDITIONS
MIN
VORIVE = 15V.
VORAIN = - 7.5V 10 = 10mA

TYP

MAX

20

30

n

ROS(on)

Switch "on" Resistance

Vp

Pinch-Off Voltage

10 = 1nA. VOS = 10V

6

-7.5

V

10(011)

Switch "off" Current
or "off" Leakage

VORIVE = -15V,
VSOURCE = - 7.5V.
VORAIN = + 7.5V

10

±500

pA

10(011)

Switch "off" Leakage
at 125°C

VORIVE = -15V.
VSOURCE = -7.5V.
VORAIN = + 7.5V

0.25

50

nA

IS(oll)

Switch "off" Current

VORIVE = -15V.
VORAIN = -7.5V.
VSOURCE= +7.5V

. 10

±500

pA

IS(off)

Switch "off" Leakage
at 125°C

VORIVE = -15V,
VSOURCE = -7.5V.
VORAIN = + 7.5V

0.3

50

nA·

Vo= Vs = -7.5V.
VO~IVE = + 15V

0.02

±2

nA

Switch Leakage when
10(on) + IS(on) Turned "on"
Vanalog

AC Input Voltage Range
without Distortion

See Figure 3

Vinject

Charge Injection Error
Voltage

See Figure 4

BVdiode

Diode Reverse
Breakdown Voltage. This
Correlates to Overvoltage
Protection

Vo=VS= -V,
10RIVE = 1 jJA.
VORIVE =OV'

BVGSS

Gate to Source or Gate
to Drain Reverse
Breakdown Voltage

lOSS

3

18

Vp_p

3

mVp_p

-30

-45

V

VORIVE = -V.
Vo= Vs = OV.
10RIVE = 1iJA

30

41

V

Maximum Current Switch
can Deliver (Pulsed)

VORIVE = 15V.
VS=OV.
VO=+10V

45

70

mA

fen

Switch "on" time
(Note 1)

See Figure 2

50

,ns

loff

Switch "off" time
(Note 1)

See Figure 2

150

ns

15

NOTE 1: Driving waveform must be > 100ns rise and fall time.

3-60
Note: All typical values have been guaranteed by characterization and are not tested.

IIO~OIlI

IH401/IH401A

...
.....

·5V
+15V

-,s'vSL
STROBE:
INPUT

~

z

'0%

.,5V

SIGNAL

OV

\

-15V

"'"

Your

ton __

-.

",.
loff

-"'" -

-·5V

ton_

TC033601

•

STROBE INPUT

-5V

"'"

lkn

...~

/

OV
i5V SIGNAL

:C---

-5V SIGNAL

10%

(olf - - WF024401

Figure 2: Switching Time Test Circuit and Waveforms

.. 15V

OVLr
-15V

1

C~OOl.1'F

TC033701

TC033801

Figure 3: Analog Input· Voltage Range
Test Circuit

Figure 4: Charge Injection Test Circuit

ELECTRICAL CHARACTERISTICS AT 25°C/125°C
IH401A
SYMBOL

CHARACTERISTIC

TEST CONDITIONS
MIN
VORIVE = 15V.
VORAIN = -10V. 10 = 10mA

UNIT

TYP

MAX

35

50

n

ROS(on)

Switch "on" Resistance

Vp

Pinch-Off Voltage

10 = 1nA. VOS = 10V

4

5

V

10(011)

Switch "off" Current
or "off" Leakage

VORIVE.= -15V.
VSOURCE = -10V.
VDRAIN = + 10V

10

±500

pA

10(011)

Switch· "off" Leakage
at 125°C

VORIVE = ~15V.
VSOURCE = -10V.
VORAIN = + 10V

0.25

50

nA

IS(off)

Switch "off" Current

VORIVE = -15V.
VORAIN = -10V.
VSOURCE = +10V

10

±500

pA

IS(off)

Switch "off" Leakage
at 125°C

VORIVE = -15V.
VSOURCE = -10V.
VORAIN = + 10V

0.3

50

nA

Vo = Vs = -10V.
VORIVE = + 15V

0.02

±2

nA

Switch Leakage when
10(on) + IS(on) Turned "on"
Vanalog

AC Input Voltage Range
without Distortion

See Figure 3

Vinject

Charge Injection
Amplitude

See Figure 4

BVdiode·

Diode Reverse
Breakdown Voltage. This
Correlates to Overvoltage
Protection

VO=VS= -V.
10RIVE = 1/lA.
VORIVE = OV

2

20

-30

3-61
Note: All typical values have been guaranteed by characterization arid are not tested.

22

Vp_p

3

mV p_p

-45

V

',§ . lH4011IH401A
Z
::::.

ELECTRICAL CHARACTERISTICS 'AT 25"C/125°C (tONT.)

~

IH401A
SYMBOL

!

CHARACTERISTIC

UNIT

TEST CONDITIONS
MIN

TYP

MAX
i

BVGSS

Gate to Sowce or Gate
to Drain Reverse
Breakdown Voltage

VORIVE= -V,
Vo=Vs=OV,
,IPRIVE = lIlA

30

41

V

loss

Maximum Current Switch
can Deliver (Pulsed)

VORIVE = 15V,
Vs = OV,
VO=+10V

35

55

~A

ton

Switch "on" time
(Note 1)

See Figure 2

50

ns

toft

Switch "off" time
(Note 1)

See' Figure 2

150

ns

NOTE: Driving waveform must be,

> 1DOns

rise and fall time.

,APPLICATIONS
IH401 Family
In general, the IH401 family can be used in any application formally using a JFET /isolation diode combination
(2N4391 or similar). Like standard FET circuits, the IH401
requires a translator for normal analog switch function. The
translator is used to boost the TIL input signals to the ± 15V
analog supply levels which allow the IH401 to handle ±7.5V
analog signals (or IH401A to handle ±10V analog signalS);
A typical simple PNP translator is shown in Figure 5.
-l!iV

Although this simple PNP circuit represents a minimum of
components, it requires open collector TTL input and t(off)
is limited by the collector load resistor (approximately 1.5J.1s
for 10kn). Improved switching speed can be obtained by
,increasing, the complexity of the translatorl;ltage.
'
A translator which overcomes the problems of the simple
PNP stage is the Intersil IH6201. * This translator driving an
IH401varafet produces the following typical features:
, '. Ion' time of approx. 200ns
• toff time 0.1 approx." 80(1s

• TIL compatible Strobing levels of

IN

L..

,.....,

O.4V...J

L...

• ID(on) +IS(on) typically 20pA up to ±10V analog
signals
• ID(Off) or IS(off) typically 20pA
,. Quiescent current drain of approx. 100nA in either
".on" or "off" case

+15V

,....,

break before
make switch
+2 .• V

ANALOG
SIGNALS

ov...J

J

lQ4(O

FROM TTL
OPEN COLLECTOR

lOGIC

*Th,e IH6201 is a dual translator (two independent
,tran~lators per package) constructed from monolithic
CMOS technology. The schematic of one-half IH6201,
driving one-fourth of an IH401, is shown in Figure 6.

t15V
TC033901

Figure 5

3-62
Note: All typical values have been guaranteed by characterization and are not, tested.

.n~nlb

IH401/IH401A

I...

i

~
.~

r----'

I
I

UV

Uy..r-L.

I
I
I

I

I

IL_v~_J
• I

+I5V

B

+15,r' '.

-15Y~
..
.. I
I

- +15V

I
I

I
I

I

I

B."1..I'
.. -ISV

i

-15Y
05027801

NOTE: Each translator output has a 9 and

11

output.

11

is, just the .inverse of 8 i.e:.

(~ output·is

1sOo
"out of,

Figure 6: IH6201 Driving An IH401

Phas~ with

,.

CD030QOI

NOTE: Either switch is turned on when strobe input goes high.

Figure 7: Dual SPST Analog Switch

Note: AU typical values have been guaranteed by characterization and are not tested.'

respect to 8 output).

+3V

ovs-LT2L1

COO31001

Figure 8: DpDTAnalog :SWltCh

(i§)----<

T2L INPUT 1

'. d ~

liiil---< r2L INPUT 2

COO:J1101

Figure 9: Dual SPDT Analog Switch
A very useful feature of this system is that one-half of an
. IH6201 and one-half of an IH401· can combine to make a
SPOT switch, or an IH6201 plus an IH401 can make a dual
\ SPOT analog switch. (See Figure 9)

.!.j'

00031201

Figure 10: Dual DPST Analog Switch

Note: All typical values have been guaranteed by characterization and IlI"I\ not. tested.,

IH5'009-IH5024
Virtual Ground
Analog Switch
GENERAL DESCRIPTION

FEATURES

The IH5009 series of analog switches were designed to
fill the need for an easy-to-use, inexpensive switch for both
industrial and military applications. Although low cost is a
primary design objective, performance and versatility have
not been sacrificed.
Each package contains up to four channels of analog
gating and is designed to eliminate the need for an external
driver. The odd numbered devices are designed to be
driven directly from TTL open collector logic (15 volts) while
the even numbered devices are driven directly from low
level TIL logic (5 volts). Each channel simulates a SPOT
switch. SPOT switch action is obtained by leaving the diode
cathode,unconnected; for SPOT action, the cathode should
'be grounded (OV). The parts are intended for high performance multiplexing and commutating usage. A logic "0"
turns the channel ON and a logic "1" turns the channel
OFF.

•
•
•
•
•
•

Switches Analog Signals Up to 20 Volts Peak-toPeak
Each Channel Complete - Interfaces With Most
Integrated Logic
Switching Speeds Less Than O.S~
IO(OFF) Less Than SOOpA Typical at 70·C
Effective rds(ON)- sn to son
Commercial and Military Temperature Range
Operation

ORDERING INFORMATION
BASIC
PART NUMBER

CHANNELS

LOGIC
LEVEL

~ACKAGES

IH5009

4'

+15

JD,DD,PD

IH5010

4

+5

JD,DD,PD
JE,DE,PE

IH5011

4

+15

IH5012

4

+5

JE,DE,PE

IH5013

3

+15

JD,DD,PD

IH5014

3

+5

JD,DD,PD

IH5015

3

+15

JE,DE,PE

IH5016

3

+5

JE,DE,PE

IH5017

2

+15

JD,DD,PA

IH5018

2

+5

JD,DD,PA
JE,DE,PA

IH50XX

M

DE

L

Package
PA - 8-PIN PLASTIC DIP
PD - 14-PIN PLASTIC DIP
PE - 16-PIN PLASTIC DIP
DO - 14-PIN CERAMIC DIP
(Special Order Only)
DE - 16-PIN CERAMIC DIP
(Special Order Only)
JD - 14-PIN CERDIP
JE - 1.6-PIN 'CERDIP
' - - - - - - TEMPERATURE RANGE
M = MILITARY (-55°C to
+ 125°C)
C = COMMERCIAL (O°C to
+ 70°C)
L..._ _ _ _ _ _

IH5019

2

+15

IH5020

2

+5

JE,DE,PA

IH5021

1

+15

JD,DD,PA

IH5022

1

+5

JD,DD,PA

IH5023

1

+15

JE,DE,PA

IH5024

1

+5

JE,DE,PA

NOTE: Mil-Temperature range (-55°C to
packages only.

+ 125°C) available in ceramic.

3-65
Note: All typical values have been guaranteed by characterizaijon' and are not tested ..

BASIC PART NUMBER

.~.

·:s.. I H500Q-1tHS024,
. ~,' ... ,..... ,.. ".,': '. . "' ,

'

·.O~1lIL
,

, f i'

:.

.'

"

'. f.~',·

"

~~~';

'I' ABSOLUTE MAXIMUM RATINGS

i
I

Lead Temperature (Soldering, 1O~~~) .......... :: ..... 300·6
Operating Temperature
5009C Series ....... " ........ : ........ :. 0·0' to + 70·0
5009M Series ... :' .......... : ...... :. ":55·C Jo +125·C
Lead Temperature (Soldering/tOsee) ....... : ... , ..... 300·C

Positive Analog Signal Voltage ............................ 30V
Negative Analog Signal Voltage ......................... -15V
Diode Current ......................................... '" ..... 1OmA
Pow~r Dissipation (Note} ......................... ~~ ....• 500mW
Storage Temperature ....... :: ........'..... -65"C to + 150·C

NOTE: Dissipation rating assumes devies is mounted with all leads welded or soldered to printed circuit board in ambient temperature below 75'G. For higher
temperature. derate at rate of 5m/W'G,

.. . . . . . . .

..

Stresses above those listed under Absolute Mllxim~m Ratings may cause permanent damage to the device. These are stress ratings only. ana fu~ctiollal
operation of the device at. these or any other conditions above those indicated in the operational sections of the specificatiQns is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
..,"
.

IH5009 (rOS(ON)::; 100n) IH5010
(rOS(ON)::; 150n) 14 PIN DIP
(OUTLINE DWGS DO, PO, JD)

IH5013 (rOS(ON) ~ 100n) IH5014
. (rOS(ON)::; 150n) 1.4 PIN DIP
(OUTLINE DWGS DO, PE; JE)

IH5011 (rOS(ON)::; 100n) IH5012
(rOS(ON) ::; 150n) 16 PIN DIP
(OUTLINE DWGS DE, PE, JE)

COOO~9Ol

CDOO1801

c0001701

IH5015 (rOS(ON)::; 100n) IH5016
(rDS(ON) ::; 150n) 16. PIN DIP
(OUTLINE DWGS DE, PE, JE)

IH5019 (rOS(ON)::; 100n) IH5020
(rOS(ON) ::; 150n) 8 PIN DIP'
(OUTLINE DWGS DE; PA, JE)

IH5017 (rOS(ON)::; 100n) .1""5018
(rOS(ON)::; 150n) 8 PIN DIP
(OUTLINE DWGS DO: PA, JD)

11 I ~ I;; :~t'-----t:~- r- -'" -:L.~I;~
-'
[1.J
:2

7

:2

10

CDO02101

,'.
7

CDOO2201

c0002001

. IH5023 (rOS(ON)::; 100n) IH5024 (rOS(ON)::; 150n)
8 PIN DIP (OUTLINE DWGS DE, PAl

IH5021 (rDS(ON) ::; 100n) IH5022 (rOS(ON)::; 150n)
8 PIN DIP (OUTLINE DWGS DO, PA, JD)

: I~ 1-~
I

--+-<0.

CDOO2401
CDOQ2301

(Note: Numbers in brackets refer to CERDIP packages.)

Figure 1: Pin Connections

3-66
Note: All typical values have been guaranteed by characterization and are not tested.

IH5009-IH5024
FOUR CHANNEL
IH5009 (rDS(ON):O: 100n) .
IH5010 (rOS(ON):O: 150n)
14 PIN DIP

THREE CHANNEL

IH5011 (rOS(ON):O: 100n)
IH5012 (rOS(ON):O: 150n)
16 PIN DIP

IH5013 (rOS(ON):O: 100n)
IH5014 (rOS(ON):O: 150n)
14 PIN DIP

. IH5015 (rOS(ON):O: 100n)
IH5016 (rOS(ON):O: 150n)
16 PIN DIP

IT
•

3~'

t. b,

8

T.T.

'~8

t. L

,IT.

"~.

t2 b'0

IT

08000801
05016901

05016801

05016701

TWO CHANNEL
IH5017 (rDS(ON):O: 100n)
IH5018 (rOS(ON):O: 150n)
8 PIN DIP

SINGLE CHANNEL

IH5019 (rOS(ON):O: 100n)
IH5020 (rOS(ON):O: 150n)
8 PIN DIP

IH5021 (rOS(ON):O: 100n)
IH5022 (rOS(ON) S 150n)
8 PIN DIP

3~'

"TT!Yr4 31T'

t . .b2
.~.

t.
DSOOO901

IH5023 (rOS(ON):O: 100n)
IH5024 (rOS(ON):O: 150n)
8 PIN DIP

3

,

•

•

2

b7

DSOO3701

08001001

Figure 2: Device Schematics and Pin Connections

ELECTRICAL CHARACTERISTICS

(per channel)
SPECIFICATION LIMIT

SYMBOL
(Note 1)

TEST
CONDITIONS
(Note 2)

TYPE
(Note 4)

-55'e (M)
o'e (e)
MINIMAX

TYP

MINIMAX

+ 125'C (M)
+70'C (C)
MINIMAX

VIN - OV, 10 - 2mA

0.Q1

±0.5

100

p.A

5V Logic Ckts

VIN = +4.5V, VA = ±10V

0.04

±0.5

20

nA

Input Current-OFF

15V Logic Ckts

VIN- +l1V, VA-±10V

0.04

±0.5

20

nA

VIN(ON)

Channel Control Voltage·ON

5V Logic Ckls

See Figure 7, Note 3

0.5

0.5

0.5

.V

1.5

CHARACTERISTIC

IIN(ON)

Input Current-ON

ALL

IIN(OFF)

Input Current-OFF

IIN(OFF)

25'C

UNIT

VIN(ON)

Channel Control Voltage·ON

15V Logic Ckts

See Figure 8, Note 3

1.5

1.5

V

VIN(OFF)

Channel Control Voltage·OFF

5V Logic Ckts

See Figure 6, Note 3

4.5

4.5

V

VIN(OFF)

Channel Control Voltage·OFF

15V Logic Ckts

See Figure 8, Note 3

11.0

11.0

V

10(OFF)

Leakage Current-OFF

5V Logic Ckts

VIN = +4.5V, VA - ±10V

0.02

±0.5

20

nA

10(OFF)

Leakage Current-OFF

15V Logic Ckts

VIN= +11V, VA=±10V

0.02

±O.S

20

nA

IO(ON)

Leakage Current·ON

5V Logic Ckts

VIN = OV, Is = lmA

0.30

±1.0

1000 (M)
200 (C)

nA

±0.5

500 (M)
100 (C)

nA

1.0

10

p.A

2.0

100

p.A

150

385 (M)
240 (C)

n

80

100

250(M)
160 (C)

150

500

= OV, IS = lmA
= OV, Is - 2mA
VIN = OV, IS = 2mA
10 =2mA, VIN = 0.5V

10(ON)

Leakage Current-ON

15V Logic Ckts

VIN

IO(ON)

Leakage Current·ON

5V Logic Ckts

VIN

1[)(ONt

Leakage Current·ON

15V Logic Ckts

rOS(ON)

Drain-Source ON·Resistance

5V Logic Ckts

roo(ON)

Drain-Source ON·Resistance

l(on)

Turn-ON Time

15V Logic Ckts
All

10 = 2mA, VIN = 1.5V

See Figures 5 & 6
3-67

Note: All typical values have been guaranteed by characterization and are not tested.

0.10

150
100

90

n
ns

r&n~Dn

,lflsO09~B5024

_UlNJUl$lJ'I@}UfD

ELECTRICAL CHARACTERISTICS (CONT.)
,

SPECIFICATION LIMIT
SYMBOL
(Note 1)

TEST
CONDITIONS
(Note 2)

TYPE
(Note' 4)

CHARACTERISTIC

-55'C (M)

2S'C

,O'C (C)
MINIMAX

t(off)

Turn-OFF Time
Cross Talk

CT

See Figures 5 & 6
f = 100Hz

All
All

TYP

MINIMAX

300
120

500

,

+12S'C (M)
+,70'e (e)
' MINIMAX

UNIT

ns
dB

NOTES 1: (OFF) and (ON) subscript notation refers to the conduction state of the FET switch for the given ,test.
2: Refer to Figure 2 for definition of terms.
3: V'N(ON) and V'NIOFF) are test conditions guaranteed by the tests of rOSION) and IO(OFF) respectively.
4: "5V Logic CKTS' applies to even-numbered devices. "15V Logic CKTS' ' applies to odd·numbered devices.

TYPICAL PERFORMANCE CHARACTERISTICS
ID(ON) VI. IS AT 25'e

1 1000

1 lOOk

...

....

~

~
I

z

/

Z

0:
0:

i... looo
...0
...
...Z

!='s"mA
f-VA -10V

I

~
c(

c(

I.S
2.0
2.5
. I, - SOURCE CURRENT (mAr

~

10

9

<.> 1.4

~ 1.2
w

-120
-110

25
7S
TEMPERATURE ( Cl

:;
~ 1.0

/'
V

0:

~

...~"
....
c(

I
1

rt ~

:"0.8 ! - ' f-

z

~

cf 0.6

r-o

25
50
75
TEMPERATURE ( CI

100

.

......
c(

/

100

25
50
7S
TEMPERATURE r Ci

"-

-90
-80
-70

10kU

'\.

"- I'\.

a: -60

"-

-so

I' . -

0

t.>

-40
-30
10

100

0P004201

CROSSTALK MEASUREMENT CIRCUIT

.r,

!-100

VI

N

~

'--

~

.'

CROSSTALK AS A
FUNCTION OF FREQUENCY
-130

I /'
Y

':"

1--

0P00e001

RD~ON) VI. TEMPERATURE
(NORMALIZED TO 25'C VALUE)

'"o

(11

':" +iV.'
.15V

...u

OP007911

.N

.

I

R

'.1,0

10D.!>

100

....

~.-

Is

V

I

."

-~~

E::
-~~
t- ;::::

:::> 100

lk

<.>

..."....

I.

.

0:.
0:

:::>

~
c(

g

10k

ID(OFF) VI. TEMPERATURE

0:
0:

a 100

~,

(per channel)

ID(ON) VI. TEMPERATURE

~

v,.

...

-5\1 (5010ETCI
'16VI6008HCI

100
lK
lQK lOOK
FREQUENCY 1Hz.)

OPOO4311

1M

TC004201

OPOO44Q1

DETAILE.D DESCRIPTION
The signals seen at the drain of 'a junction FET type
analog switch can be arbitrarily divided into two categories;
those which are less than ±200mV, and those which are
. greater than ±200mV. The former category iricludesall
those circuits where switching is performed at the virtual
ground point of an op-amp, and it is primarily towards these
applications that the IH5009 family of circuits is directed.

Those devices which feature common drains have another FET in addition to the channel switches. This FET, which
has gate' and source connected' such that VGS = 0, is
intended to compensate for the on-resistance of the switch.
When placed in series with the feedback resistor (Figure 3)
the gain is given by:

By limiting the analog signal at the switching point to
±200mV, no external driver is required and the need for
additional power supplies is eliminated.
Devices are available with both common drains and with
uncommitted drains.

Note: All typical values have been guaranteed by characterization and are nof tested •.

G~N=

10kn + rOS(ON)(compensator)

...

10kn + rOS(switch)

1145009-1115024
SWITCHING CHARACTERISTICS

A.OOO8OI

Figure 3: Use of Compensation FET

TC0G4301

"'"

Clearly, the gain error caused by the switch is dependent
on the match between the FETs rather than the absolute
value of the FET on-resistance. For the standard product,
all the FETs in a given package are guaranteed to match
within son. Selections down to sn are available however.
Contact factory for details. Since the absolute value of
rOS(ON) is guaranteed only to be les$ than 1oon or 1son, a
substantial improvement in gain accuracy can be obtained
by using the compensating FET.

10V

PW-5I,..
tr <0.1/001

.,<0.1".

?5V

7.5V

f1II

10"

OUTPUT

V... ·,OV
f1II
f1II
OUTPUT·~

VA--1OV

WFOO1301

DEFINITION OF TERMS

Figure 5: High Level Logic

Figure 4.
. 'if1N
PW • 5,l1

NOISE IMMUNITY

5 V r - - - -.......
2.5V
Z.5V
toFF

t.--.....-oVOUT

,

ANALOG

OUTNl

,,

,,

__ ...

&!i~T!.L!.A!E

_~

_ _'
lCOOO101

Figure, 7: Interfeclng .wIth

+ 5V Logic

,,',4-+-+-h

,

,

,,r-----'.:..--.,..---,
,,,
,

ANALOG
INPU1Nwtl

:

L ___________

'lSV

1

7

•

I

"

"'~ e~,A.w:TE.ISTtCS4AI" '"

-::.UT " Rn

14

~

-,~'
AF:001001

_LOG

Figure 9

, OUT1'UT

<·'1

,,,
,

,,,
,
:L!~!!~G~T! ____
":' ":'..J
-=-:

..))

,

LCOOO2Ol

Figure 8: Interfec.!ngwlth + 15V Open
Collector Logic

10Kn

,,
I

,
,
,,,
,
,,

I,;

:

ANALOG

INPUTS

,1Gttu

11

I
L -- --, 4

10kn

I

AFOOt1m

Figure, 10
NOTE: Additional applications information is given in Application Bulletins A003 "Understanding and Applying the
Analog Switch" and A004 "The 5009 Series of Low Cost
Analog Switches".

3-70
Note: All typical values have been guaranteed by characterizatiOn, and. are not tested.

, '.

IH5025-IH5038
Positive Signal
Analog Switch
GENERAL DESCRIPTION

FEATURES

The IH5025 series of analog switches was designed to fill
the need for an easy-to-use, inexpensive switch for both
industrial and military applications. Although low cost is a
primary design objective, performance and versatility have
not been sacrificed.
Each package contains up to four channels of analog
,gating and is designed to eliminate the need for an external
driver.
.
The entire family is designed to be driven from TTL open
collector logic (15V), but can be driven from 5V logic if
signal input is less than 1V. Alternatively, 20V switching is
readily obtainable if TTL supply voltage is +25V. Normally,
only positive signals can be switched; however, up to ±10V
can be handled by the addition of a PNP stage (Figure 14)
or by capacitor isolation (Figure 13). Each channel is a
SPST switch. A logic "0" turns the channel ON and a logic
"1" turns the channel OFF.

•
•
•
•
•
•

Switches Up to + 20V Into High Impedance
Loads (i.e. Non-Inverting Input of Operational
Amp.)
Driven From TTL Open Collector Logic
IO(OFF) < 50pA
rOS(ON) < 150n
rOS(ON) Match < 50n Channel to Channel
Switching Speeds < 100ns

ORDERING INFORMATION
BASIC
PART NUMBER

CHANNELS

LOGIC
LEVEL

PACKAGES

IH5025

4

+15

JD,DD,PD

IH5026

4

+5

IH5027
IH5028

4
4

+15
+5

JD,DD,PD
JE,DE,PE

IH5029

3

+15

JD,DD,PD

IH5030

3

+5

IH5031

3

+15

JD,DD,PD
JE,DE,PE

IH5032
IHS033

3
2

+5
+1S

JE,DE,PE
JD,DD,PA

IHSOXX

IHS034

2

+5

2

+15

JD,DD,PA
JE,DE,PA

IHS036

2

+5

JE,DE,PA

IHS037
IH5038

1
1

+15
+5

JD,DD,PA
JD,DD,PA

DE

L

PACKAGE
PA - a-PIN PLASTIC DIP
PD - 14-PIN PLASTIC DIP
PE - 16-PIN PLASTIC DIP
DD - 14-PIN CERAMIC DIP
(Special Order Only)
DE - 16-PIN CERAMIC DIP
(Special Order Only)
JD - 14-PIN CERDIP
JE - 16-PIN CERDIP
L -_ _ _ TEMPERATURE RANGE
M = MILITARY (-SSOC to
+ 12S°C)
C = COMMERCIAL (O°C to
+ 70°C)

JE,DE,PE

IHS03S

M

' - - - - - - - - BASIC PART NUMBER

NOTE: Mil-Temperature range (-5S0C to + 12S°C) available in
ceramic packages only.

IH5025 (rOS(ON) ::; 100n)
IH5026 (rOS(ON)::; 150n)
14 PIN DIP

IH5027 (rOS(ON)::; 100n)
IH5028 (rOS(ON)::; 150n)
16 PIN DIP

IH5029 (rOS(ON):S 100n)
IH5030 (rOS(ON):S 150n)
14 PIN DIP

IH5031 (rOS(ON):S 100n)
IH5032 (rOS(ON):S 150n)
16 PIN DIP

11

4
C0004201

CDOO2501

CDOO2601

Figure 1: Pin Connections

3-71

Note: All typical values have been guaranteed by characterization' and are not tested.

5

12
COOO2701

IH5025-IH5C)38
,
{;

~,

~

IH5033 (rOS(ON) ~ 100.12)
IH5034 (rOS(ON) ~ 150.12)
8 PIN OIP
(3)3

'

IH5037 (rciS(ON)~ 100.12)
IH5038 (rOS(ON) ~ 150.12)
8 PIN DIP

IH5035 (rOS(ON) ~ 100.12)
IH5036 (rOS(ON) ~ 150.12)
8 PIN OIP

6(12)

(3)3

7(15)

(2)2

I
3(3)

(2)2

O-+_4-<~------IHl6(·'4)

4(4)

('3)9-11---<>"1 "'---.--If-Q5(11)

6(14)

'(1)

4(4)

(212

o-j----4'i

5('3)

CDOO2801

CDOO4101

CDOO29()1

NUMBERS )N PARENTHESES INDICATE CERAMIC PACKAGE PIN-OUT

Figure 1: Pin Connections (Cont.)

FOUR CHANNEL
IH5025 (rOS(ON) ~ 100.12)
IH5026 (rOS(ON) ~ 150.12)
14 PIN DIP

THREE CHANNEL
IH5029 (rOS(ON) ~ 100.12)
IH5030 (rOS(ON) ~ 150.12)
14 PIN DIP

IH5027 (rOS(ON) ~ 100.12)
IH5028 (rOS(ON) ~ 150.12)
14PIN DIP

'rr'

'n'

'rr.
'rr"
2

•

,

"

IH5031 (rOS(ON) ~ 100.12)
IH5032 (rOS(ON) ~ 150.12)
~6 PIN DIP

"rr"
10

12

15

13

'rr'
'rr"

"

05001301

2

•

7

•

10

12

DSOQ1401

05001201

05001101

TWO CHANNEL

SINGLE CHANNEL

IH5033 (rDS(ON) ~ 100.12) IH5034
(rOS(ON) ~ 150.12)
8 PIN DIP

IH5035 (rOS(ON) ~ 100.12) IH5036
(rOS(ON) ~ 150.12)
8 PIN DIP

IH5037 (rOS(ON) ~ 100.12) IH5038 .
(rOS(ON) ~ 150.12)
8 PIN DIP

~rr~

5(11)

3(31

'(1)
05001701

6(12)

8(''')
05001501

09001601

Numbers in parentheses indicate CERAMIC PACKAGE LAYOUT

.

Figure 2: Device Schematics

3-72
Note: All typical values have been guaranteed by characterization and are not tested.

i

IH5025-IH5038

§

ABSOLUTE MAXIMUM RATINGS

t

Positive Analog Signal Voltage ............................ 25V
Negative Analog Signal Voltage ..................... -O.5VDC
Drain Current ................................................. 25mA
Power Dissipation (Note) ................................ 500mW
Storage Temperature ...................... -65'C to + 150'C

Operating Temperature
Z
5025C Series ............................ O'C to + 70'C
5025M Series ...................... -55'C to + 125'C to»
Lead Temperature (Soldering, 10sec) ................. 300·C. CD

g

NOTE: Dissipation rating assumes device is mounted with all leads welded
or soldered to printed circuit board in ambient temperature below 7S·C.
For higher temperature, derate at rate of 5m/W·C.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (per channel)
SPECIFICATION LIMIT
SYMBOL
(Note 1)

CHARACTERISTIC

TEST

TYPE

-55'C

CONDITIONS

O·C (C)
IIN(ON)

Input Current·ON

All

UNIT

25'C

(M)
TYP

MINIMAX

0.30

VIN = OV

IIN(OFF)

Input Current-OFF

All

VIN = 15V

VIN(ON)

Channel Control Voltage·ON

All

See Figure 3

1.5

VIN(OFF)

Channel Control Voltage·OFF

All

See Figure 3

14.0

ID(OFF)

Leakage Current·OFF

All

See Figure 5

0.20

+ 125'e (M)
+ 7O'e (e)

1.0

100 (M)
25 (C)

1.0

50 (M)
50 (C)

nA (max)

1.5

1.5

V (max)

nA (max)

14.0

V (min)

0.5

100 (M)
50 (C)

nA (max)
nA (max)

14.0
0.06

MINIMAX

ID(ON)

Leakage Current·ON

Odd Nos.

See Figure 6

1.00

10.0

5000 (M)
250 (C)

ID(ON)

Leakage Current·ON

Even Nos.

See Figure 6

0.10

1.0

500 (M)
25 (C)

nA (max)

100.0

250 (M)
150 (C)

n

(max)

150.0

385 (M)
240 (C)

n

(max)

n

(max)

n

(max)

rDS(ON)
rOS(ON)

Drain·Source ON·Resistance

Drain·Source ON-Resistance

Odd Nos.
Even Nos.

100

VIN = 0.5V, ID = 1rnA
VIN = 0.5V, ID = 1rnA

rDS(ON)

Drain-Source ON-Resistance

Odd Nos.

VIN = 1.0V, ID = lmA

rDS(ON)

Drain-Source ON-Resistance

Even Nos.

VIN-l.0V.ID=lmA

t(oo)

Turn·ON Time

I(off)
Q(INJ)

60.00

150

90.00
85.00

160.0

420 (M)
250 (C)

110.00

200.0

400 (M)
250 (C)

0.2

0.4
0.4

160

All

See Figure 4

0.10

Turn·OFF Time

All

See Figure 4

0.10

0.2

Charge Injection

All

See Figure 5

7.0

20.0

VA(OFF)

Cross Coupling Rejection

All

See Figure 6

0.10

1.0

AraS(ON)

Channel to Channel rDS(ONl Match

All

VIN

= 0.5V.

I1S (max)
mVp•p (max)
mVp. p (max)

n

25.00

ID = 1rnA

1'5 (max)

(max)

Note 1: (OFF) and (ON) subscript notati9n refers to the conduction state of the FET switch for the given test.

+10V~VOU~OSCOftEPA08E
!10XI

VAYl.
. 'vou,

f

10Mu

1'KO

FET "ON" FOR VIN

n

1 K!!

+1SY

OV~LOGtc·

--l
.. r-"
.~:
YOUT

II
II

II
II

tOFF

tON

1.5V

Fer "OFF" FOR VIN ;><.,.14.0V
TC004501

TCOO4601

Figure 3: Test Circuits

Figure 4: Test Circuits

3-=-73
Nole: All typical values have been guaranteed by characterization and are not tested.

OV

+5Y

.oon

~

: ~~y

·,5V

OyJL

.

TCOO4101

1 Ku

'0"",

..•
f.., 1 KC

Figure 5: Test Circuits

+lSV

TCOo4'BOI

t::1gure 6: Test Circuits

TYPICAL PERFORMANCE CHARACTERISTICS (per channel)
IO(OFF) VS. TEMPERATURE

~'"

+10V
lOOnA f-

...

+ , . _. f--

lOOnA

f--

1DnA

..

ii: 10nA r----1

'.

.E

.........,..

~

vP'

+15V

9

./

~

V

InA

.E lOOpA

V
/'

loopA
10pA

IO(ON) VS. TEMPERATURE

/

lDpA

1 pA /

~

/'

tl-

+IOV,::,'
-25

+25

+75

+25

~25

+125

+75

TEMPERATURE (OC)

TEMPERATURE (OC)

OPOO4601

, OPOO4501

CROSS COUPLING REJECTION VS. FREQUENCY
14

~I
I-

::>

~

ROS(ON) Vs. VIN
200

+5V

12

176

10

150

c:

8

6

S

a: 75
4

I

/

125

j'00

-

~io"'"

.,

V

50

25

o L.J::::::t=t=:l::::::L-.L.J
1 KH,

10 KH,

100 KH,

.

+125

OV

1 MH,

FREQUENCY

0.5V

1.0V

1.5V

VIN
OP00471 I

0P004801

3-74
Note: All typical values have been guaranteed by characterization' and are not tested.

LOGIC INTERFACE CIRCUITS

Channel FET has been sel4ilcted betw~en 2.0V and3.9V;
thus with + 15V at the logical.input, and a + 10V signal
input, 1.1 V of margin exists for turn-off. When the IH5025 is
used with 5V TIL logic, a maximum of + 1V can be
switched. The gate of each FET has been brought out so
thaI a "referral resistor" can be placed between gate and
source. This is used to minimize charge injection effects.
The connection, is shown below:

When operating with TIL logic it is necessary to use pUIIup resistors as shown in Figures 6 and 7. This ensures the
necessary positive voltages for proper gating action.

r---------...,...,

TC00400l

LCOOO3OI .

Figure 9

Figure 7: Interfacing with + 5V Logic

For switching levels> + 10V, the + 15V power supply
must be increased so that there is a minimum of 5V of
difference between supply and signal. For example, to
switch + 15V level, + 20V TIL supply is required. Up to
+ 20V levels can be gated.

r--- ---,+,5V
I
I

-

APPLICATIONS

•I
I

I
I

I
I•
I
1..:
_GATE""
_____
"5V_
TTL
."...1I
LC000411

Figure 8: InterfaCing with + 15V Open
Collector Logic
.

THEORY OF OPERATION
The IH5025 series differs from the IH5009 series in that
they may be driven by floating outputs. This family is
generally used when operating into thenon-invertil"lg inpl,rt
of an operational amplifier, while the IH5009series is used
in operations where the output feeds into the inverting
(virtual ground) input.
. The IH5025 model is a basi~ charge. area sViitching _
device, in that proper gating action .depends upon the
.capaoitance vs. voltage· relationship fort"'e diode junctions.
This C vs. V, when integrated, produces total charge Q. It is
Q total which is switched between the series diode and the
gate to source and gate to drain junctions. The charge area
(C vs. V) for the diode has been chosen to be a minimum of
four (4) times the area of the gate to source junction, thus
providing adequate safety margins to insure proper switching action.
If normal logical voltage levels of ground to + 15V (open
collector TIL) are used, only signals which are between OV
and + 10V can be switched. The pinch-off range of the p-

AFOOt2Of

Figure 10: Multiplexer from Positive Output
Transducers

+111,1

ov.fL.
AFOO1301

Figure 11: Sample and Hold Switch

3-75
Note: All typical values have been guaranteed by characterization ",d are not tested.

.~.

"

IIH502.~IiI'038

i
I

APPlJCATIONS:1~.)

!

r - .... - -,,- I

""'--,.211/

I

I

I

I

I

I
I
"lOI/nLGATE
"::"
'''::" J I
L:: ___ "' _____
AFOO1411

flgyre 12: Switching up to +20V $I9".alsYiith TTL

~ogic

r--;---:--':--:-'·"V
:

I"
l~;~

I

. I

TO

:

1'0K1!'
.-~:~~__________J

I

I

eSHIFT· l,O."1OMI
!

.

'";;oJi ~-'

.

~_I"

·

ONO

0,
0,

0,

o•

a~~,2 ~~4 •
SSOO'5Oi

~1401

SWITCH STATES ARE FOR
LOGIC "1" INPUT

I

".'~
.,

ss001201

DUAL DPST IH504S
(rOS(on) < 7SSl)

A

'0/

FLAT PACKAGE.FD-2)

DIP (DE) PACKAGE

OPOT IH5046
(roS(ON) < 7SSl)

,
"o, ",
o,
.. •
'N

v,

v'

Y,o

f·

v,

~

'",-

...,

-

" ......
.~'

GOO

0,

.,

0,

5,

3~DI
,

:.r-- !.o
•

D4

_J

5,

,

v'

f"
I

;-u

I

-v 0 '

"'-:.

II

·
,. · ......

.J..:

_t

b"
v'

o.

.~5

~:'
v'

y"

~J
.NO

88001801

0,

!..,., 03

r-o

D4

88001701

4PST IHS047
(ros (ON) < 7SSl)
v,

,
,
.." •

10 f.
~OI

5,

$,

IN

,4

u!'

5,

~O'l

4~D3,

......

.1

-v 0,

~-.

b"
GNO

,

y"

",

~.,

I

II

" •
o. •

'

1

5,

0,

:-u 0,

•

1

~D.

'foIo!! -Qi>-J

&"

!" !"

v'

ON.

85001801

V'

88001901

Figure 2: Switching. State Diagrams (Cont.),

:Hl2
Note: All typical values have been guaranteed by characterization .and ·are not tested.

TO-l00

i

IH5040~IH504 7
TYPICAL PERFORMANCE CHARACTERISTICS

40

160

I
I
,hv

100

I

'40
'20

+l~~C

10- ~

60

+25"C

+e

0
.,
-10 -5 -25' 0

~

.-1.·e i-= l.·'re

40

·20

S
R

L.-

+25~C

'00

I

25

!

r-- !--+-,12V

50

'15V

S

1? -75

t-+

-10-75

-5 -25

10

'"

0

lk

20

5

0
0

25

5

0
-10 -7.5 -5 -25

7510

I

I
I

',oon

,

L-=-

,

ov..JL ~_
~
SWITCHED
CHANNEL

VOUT

'- -

-

-

-

"

.~

2Vpp
@lMC

-l,oon

5H!'

10k lOOk 1M

OP005201
TCO05301

-12
01"

..
~

~

.

e
,.

-80

l'

1"-1-t--

-60

OFF STATE
~~_
OEPENOS ON PART~-

-40

-2 0

oTHz

~VOUT

l'Do!)

OIRR = 20LOG 2000mVpp
VOUT (mVpp)

TOHz 100Hz lk

2.5

5

7.S

10

OPOO5101

FREQUENCY (Hz)

-100

0

VANAlOG (V)

,

I

,

CCRR = 20LOG 2000mVpp
VOUT (mVpp)

100

~

." :

"'I--

0

10

25

z

~: ~-J¥
3V

1

30

~

>-

I

0

o

I-

g
>
.§.

OPQ05001

1"-",

100

I-""

VANALOG (V)

OPQQ4901

20

l...- ,...-

t5

20 ~ t -

VANALOG (V)

120

,

I

40

15V SUPPLIES

35

i

80

Is!1mA
•

CHARGE INJECTION vs VANALOG
(SEE FIG. B) CL = 10,OOOpF

rOS(on) vs POWER SUPPLY
VOLTAGE

rOS(on) vs VANALOG SIGNAL

80

(Per Channel)

10k lOOk 1M

FREQUENCY (Hz)
TCOO5401
QP005301

3-83
Note: All typical values have been guaranteed by characterization and are not tested.

~i

CIt

!

'*",

I!

~
.1

..

TYPICAL PERFORMANCE CHARACTERISTICS (CONT.)
POWER SlIPPLY QUIESCENT CURRENT
FREQlIENCY RATE

-

l/

/

,,- V
V

.,

V8

LOGIC

V

/

V

1/,

WFQ01601

...

,

LOGIC FREQUENCV@ tO"lo DUTV CYCLE IH~)

0P005401

TEST CIRCUITS

·Jj~-h1.,.

Vour

'tiff

·: rt . m
AlAUlllIIIPUT

AIA~IIPUT

'kO

iU)

OVn~_.
.

1IO.rQ-i>-_'

.

VOUT

'D.oao,F

TC035701

Figure 3

LOGIC IlPUT

~

.,. .,.

f.:~
1010

TC03580t

TC035901

Figure 4

Figure 5

NOTE 1: Some channels are turned on by high "1" logic inputs and other channels are turned on by low "0" inputs; however O.BV to 2.4V describes the min.
range for switching properly. Refer to logic diagrams to see absolute value of logic input required to produce "ON" or "OFF" state.

APPLICATIONS

ANALOG
INPUT

I.""

·3\1

~

> SAMPl E MOOE

ov • > HOLD MODE

AF005BOI

Figure 6: Improved Sample & Hold USing IH5043

3-84

Note: All typical values have been guaranteed by characterization and are' not tested.

IH5040-IH5047
APPLICATIONS (CO NT.)

lOGIC
STROI£

EXAMPLE: If -v ANALOG' -10VOCand +V ANALOG' +10VDC
then Ladder Legs are switched between, 1OVDC. depending upon lIal.
of lotIic Strobe.

JL
r'L
LOGIC
STROlE
2R

AFOO2101

Figure 7: Using the CMOS Switch to Drive an R/2R Ladder Network (2 Legs)

UIOldl

LOPASS
OUTPUT

Constant gain, constant Q. variat>te frequency filter which
provides simultaneous Lowpass. Bandpass, and H ighpass
outputs. With the component values shown, center frequency
will be 235Hz and 23.5Hz for high and low logic inputs
respecti.... ly. Q,. 100, and Gain'" 100.

fn .. Center Frequency'" _,_
21rRC
AFOO2201

Figure 8: Digitally Tuned Low Power Active Filter

3-85
Note: All typical values have been guaranteed by characterization and are not tested.

APPLICATION~

(CONT.)

T'L.r--t.
LOGIC

I
L~2:'~~T~

I
I
I
I
I

LOGIC'
INPUT

~-~6---k:"""--<> +15V

.". I

___ ...J

LCOo0501

Figure 9:. InterfaCing· with TTL Open Collector Logic
(Typ. Example for + 15V Case Shown)

y.
GND

IN

·~--O--4_-o 'VDD

15Y~ y . . . 6Y
IN .. Y- ...16V

LCOOO6OI

Figure 10: Interfacing with CMOS Logic

3-86
Note: All typical values have been guaranteed by characterization and are· hoi· tested. .

·IIIIIU~UI!.I

1H5040-1 H5047
APPLICATIONS (CONT.)
+5V

-..

IN

rrL~

I
I
I

LOGIC

J

~+

I

I

-

+5V

I
":"":" I

.

+ 15V OR + VCc(VI TERMINAL}

1

L~~L~~~ ___ ...J

100
lCOOO711

Figure 11: TTL Logic Interface

3-87
Note: All typical values have been guaranteed by characterization and are nOI tested.

Ii

IH5048~jH5051

I

GENERAL DESCRIPTION

FEATURES

The IH5048 family of analog switches is especiaUymade
,for low charge injection and low leakage. Construction
includes our CMOS high level driver circuitry combined wi~h
unique "VARAFEr' switches.

•
•
•
•
•.
•

I Low Charge Injection

I CMOS Analog Switches
Low· Charge Injection-6mV (Typ.)
Quiescent Current Less Than 1J.LA
TTL, DTL, CMOS, PMOS Compatible
Non-latching With Supply Turn-Off
Low rOS(on) - 3Sn (Typ.)
Pin-Out Compatible With IHS040 Family

.ORDERING INFORMATION
,!g

I

Package
DE -16-Pin Ceramic DIP
(Special Order Only)
FD·2 - l4-Pin Flatpak
JE - l6-Pin CERDIP
PE - l6-Pin Plastic DIP
TW - TO-l00 Metal can
(lHS048, IH5050 Only)
Temperature Range
.
M - Military (- SS"C to + l2S"C)
C - Commercial (O"C to + 70"C)
Basic Part Number

ORDERING INFORMATION
INTERSIL
PART NO.

IH5048 Dual
IHS049 Dual
IHS050
IHS051 Dual

TYPE

'OS(on)

SPST
DPST
SPOT
SPOT

3Sn
3Sn
3Sn
3Sn

NOTE 1. See Switching State diagrams for appHcable package equivalency.

SWITCH STATES ARE FOR
LOGIC '1" INPUT

FLAT PACKAGE (FD-2)

T0-1oo

DIP (DE) PACKAGE

DUAL SPST IH5048
(rDS (ON) < 3Sn)
v,

"

v,

v'
D,
I

'N, "

_J

"

v,

0,

",

-,

..

'N,

v'

'"
D,

0,

","

..

..

",

0,

GNO

.NO
ss00200/

SSOO2101

Figure 1: Switching State Diagrams

Note: All typical values have been guaranteed by characterizatiOri "and are! nortested.,·

v'

v'
$8002201

.D~OIl.

.IH5048-IH5051
SWITCH STATES ARE FOR
LOGIC '1" INPUT

FLAT PACKAGE (FD·2)

DIP (DE) PACKAGE

DUAL DPST IHS049
(rDS (ON) < 3SQ)

T00100

(DG184 EQUIVALENT)

"

v,

s,

D,
D,

S,

..... ,

D,
D,

D,

"
"

OJ

'"
'"

0,
0.

'."

GND

SSOO2301

SS002401

SPOT IHSOSO
(rDS (ON) < 3SQ)

'.

v,

v'

S,

D,

S,

D,
I

_J

v,

v'

"
"

·v·

D,

S,

D,

D,

S,

D,

"
GND

G'D

58002501

S8002601

DUAL SPOT IHSOS1
(rDS (ON) < 3SQ)

ss002701

(DG190 EQUIVALENT)

v.

v,

s,

S,
S,

D,
D,

S,

v'

D,
0,

'"

'N,

'"

D,
D,

D,
D,

GND
GND

ss002801

SS002901

Figure 1: Switching State Diagrams (Cont.)

3-89
Note: All typical values have been guaranteed by characterization and are not tested.

IH5048~IH5051
ABSOLUTE MAXIMUM RATINGS
Current (AnyTermi~al) ............... : .. , .............. < 30mA
Storage Temperature .. : ....... : ........... ..,S.5·C to 150·C
Operating Temperature ................•.. -55~C to + 125·C
Lead Temperature (Soldering. 10sec) ................. 300·C
Power. Dissipation ......................................... 450mW
(All Leads Soldered to a P.C. Board)
Derate SmW I·C Above 70·C

v+ -v- .. ; ....... '......................................... : ... .( 33V
vi' -vo ... :·.: ... : .............................................. < 30V
Vo-V- ........................................................ <30V
Vo-Vs ...................................................... < ±22V
VL-V- ........................................................ < 33V
VL -VIN ....................................................... < 30V
VL -GND ...................................................... < 20V
VIN-GND .................................................... < 20V

+

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
. absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(@ 25·C, V + =

+ 15V, V- = -15V, VL = + 5V)

PER OHANNEL

MINIMAX LIMITS
TEST CONDITIONS

SYMBOL

MILITARY

OHARACTERISTIC
-55·C

IIN(ON)
IIN(OFF}
r05(on)
Ar05(ON)
VANALOG
IO(OFF}'
IsioFFi
I~ON)
+ 5(00)

Ion

+ 125·C

±1

10
10
80

±t
±1

.±1
·40

IS· -10mA
VANALOG - -10V

0
±.1
±1

Vo-VS=-10Vto +tOV

+70·C

±1
±1

10
10
75

45

15
(Typ)
±10
VANALOG = -10V to + 10V

UNIT

+ 25·C

p.A
p.A

n

15
(Typ)
±10

n
V

. ±1

100

±5

100

nA

±2

200

±10

200

nA

'.

RL = lk!1, VANALOG - -.10V

500

1000

ns

to + 10V See Fig. 2

loft

Switch "OFF" Time

Q(lNJ.)
OIRR

Charge Injection
Min. Off Isolation
Rejection Ratio
V + Power Supply

1+ Q

IIIN ~ 2.4V Note t
VIN ~ O.SV Note 1

Input Logic Current
Input Logic Current
Drain·Source On
Resistance
Channel to Channel
rOS(ON) Match
Min. Analog Signal
Handling Capability
Switch OFF Leakage
Current
Switch On Leakage
Current
Switch "ON" Time

COMMERCIAL

+ 25·C

RL=lk!1, VANALOG= -10V
to + 10V See Fig. 2
Sea Fig. 3
f = 1MHz, RL = lOOn, CL S 5pF
Sea Fig. 4, (Note 1)

250

500

.ns

1 (Typ)

2 (Typ)

54
(Typ)

50
(Typ)

mV
dB

1

1

10

10

10

100

p.A

1

1

10

1

1

10

10

10.

100

p.A

10

10

100

p.A

1

10

10

10

100

I'A

Quiescent Current

1- Q
1- LQ

V+ = +'15V, V= -15V, VL= +5V
VL = +5V

V - Power Supply
Quiescent Current
+5V Supply
Quiescent Current

IGNO
CCRR

Gnd SUpply
Quiescent Current
Min. Channel to
Channel Cross
Coupling Rejection
Ratio

1
One Channel Off; Any Other
Channel Switchell as per
Periormance Characteristics (Note 1)

54
(Typ)

50
(Typ)

dB

Note 1: Not tested in production.

TEST CIRCUITS

r , rn
t--

ANALOG IfIIPUT

"'IOV

v1\~-J
~G"
h
INPuT

'

lOpF

J

VO\JT

"'NALOG INPUT

v..n. o---[)---t>--3K

COG'C
INPUT

1D--l>-_

LOGIC INPUT
( N0

1oooo .,F

loon

TC005111

TC005011

Figure 2

":"

~ VOUT

I

":,111,0

"='

5111

Figure 3

TC00411t

Figure 4

NOTE 1: Some channels are tumed on by high "1" logic inputs and other channels are turned on by low "0" inputs; however O.BV to 2.4V describes the min.
range for switching properly. Refer to logic diagrams to see absolute value of logic input required to produce "ON" or "OFF" state.

3-00
Note: All typical values have been guaranteed by characterization arid are not' jested.

.D~Dll

IH5048-IH5051
TYPICAL PERFORMANCE CHARACTERISTICS

(Per Channel)
CHARGE INJECTION vs VANALOG
(SEE FIG. 3) CL = 10,OOOpF

rOS(on) vs POWER SUPPLY
VOLTAGE

roS(on) vs VANALOG SIGNAL

160
100

140

3S

120

80

!

100

60

f

80
60

•

40

..,

0

+121"C

+2I·C

r- r-

.,.·c

0
-10 -5 -25'0

's·1mA
• 1 1SV SUPPLIES
2.5

5

~5

-75

0

T

0
-10 -7.5 -5 -25

10

0

0

25

"ANALOG IV)

100

CHANNEL

iii
<>
0:

~

I

o--f--D---t>--=I
r 1='
I
I
,
I

to-. to-.

I

60
3V

Ov...n..

40

20

o1

CCRR
10

= 2ULOG
100

2000mVpp
Your (mVpp)
lk 10k lOOk 1M

SWITCHED
CHANNEL

I

I
I

loon

L-=-

~.I

~--t~

.10

FREQUENCY (Hz)
TCOO5301

OP005201

-12

0"

-10o

!

-80

ii:"

e -6

0

-40

r-.
r"-"

""""''

0

2.5

5

7.5

10.

OPOO5101

VOU,

to-. "

80

c

>

-7.5· -5 -2.5

"ANALOG (VI

I

OFF

to-. to-.

..

-to

10

r-----7.h

120

;;;

7.5
OPO05021

0P004921

:!.

5

VANALOG IVI

OFF STATE
~
DEPENDS ON PART~-

~VOU'

1

-20

'00n

OIRR = 20LOS 2QOOmVpp
VourfmVDjii
0
1Hz 10Hz 100Hz lk 10k lOOk 1M

TC005401

FREQUENCY (Hz)
OPOO5301

3-91
Note: All typical values have been guarantliled by characterizalion and are not tested.

i

IH6048~IH5051

,

TYPICAL PERFORMANCE CHARACTERISTICS (CO~T;) .

I

. '.'

"IID~

POWER SUPPLY QUIESCENT CURRENTY81.0GIC
FREQUENCY RATE
,"
'000

1
i.-

Ii

i

!i:

j

V
v
/

'DO

/'

10

V'

/'

3V

V

V

V

10

100

1k

'OIl

WFOO1601

lOOk

LOGIC fREQUEN'tV@ 10"10 DUTY CYCLE 1Hz)

OPO05401

3-92
Note: All typical values have been guaranteed by characterization and are not'tested;

1"5052/IH5053

QUAD CMOS Analog Switch
GENERAL. DESCRIPTION

FEATURES

The IH5052/3 analog switches use an improved, high
voltage CMOS technology, which prbvides performance
advantages not previously available from solid state
switches. Early CMOS switches were destroyed when
power supplies were removed with an input signal present.
The INTERSIL CMOS technology has ·eliminated this serious systems problem. Key performance advantages are
TTL compatibility and ultra low-power operation - the quiescen.t current requirEjm~ntis less ,than 10pA. .
The IH5052/3 also guarantees Break-Before-Make
switching. This is accomplished by extending the tON time
(400ns TYP.) such that it exceeds tOFF time (200ns TYP.).
,This insures that an ON channel will be turned OFF before
an OFF channel can turn ON, and eliminates ,the need for
external logic required to avoid channel to channel shorting
during switching. With a logical "0" (0.8V or. less) at ,its
control inputs, the IH5052 switches are closed, while the
IH5053 switches are closed with -a logical "1" (2.4V or
. more) at its control inputs.

•
.•
•.
•
•
•
•
•

Switches Greater Than 20Vpp Signals With ± 15V
Supplies
Quiescent Current Less Than 101lA
Overvoltage Protection to f25V
Break-Before-Make Switching toff 100ns, ton
250ns Typical
TTL, CMOS Compatible
Non-~tchln.9, WIth Supply Turri-Off
.IH50524 Normally Clps,d Switches
IH5053 4 Normally Open Switches

ORDERING ,INFORMATION
IH505X , C

JE,

~

..
. .
~

.

Package

-'

.

JE c 16·Pin CERDIP
DE =·16-Pin 'Ceramic DIP
.
(Special Order Only)
Temperature Range
M - Military
C = Ccmmercial.

' - - - - - - - - Basic Part Number

OUTI,INE DWQS
. 'DE,JE
DUAL-IN-LlNE PACKAGE'
lOb

..
.

D.

D,

v'

ISU. .TIIATEI

II>

a.,TCH STATES AIIII
'0lIl LOQtC ..," tHlI!UT

...

D.

.
.

0;'

v'

VL

Dr

II>

lDOO1801
WF01060t

Figure 1: Functional Diagram

Figure 2: Pin Configurations

3-93
Note: All typical values have been guaranteed by characterization· and, are not tested.

.,,'

Current (Any Terminal) .................... : .• ~._.i.i..:.< 30mA
Storage Tell;lper/iJture ...................... -6S·Cto +1~0·C
Operating, Temperature ....•...........,... _5S·C to +.12S·C
Lead Temperature, (Soldering, 1Osec:) .......••... , ..•• 3!)0·C
Power DissiPation ........................................... 4S0mV'/
(All .Leads Soldered to ,a P.C.,Board)
DElrate 6mW I"C Above 10·C

V+ -V- ............................................ : .......... < 33V
V,+,-Vo •. "........ , •........•.. ,; ..•........•...... , ........... '< 30V
VrrV- •....................................................,... ,~' 30V
VrrVs ................ i ...... ';'; •. t ••••• :; ••• , . . . . . . . . . . . . . , •• ,., <: ±22V

~~=~~.::::::::::::::::::::::::'::::~::::::::,:::::::::::::::::::: ~'~~~

< 20V
,< 20V
Stres$8S above thos~ Iist9d und":' Absolute·M;b.irriuinFiatings 'iIl8Y cause perma~ent damage to the device. These are ~tress ratings"only, and functional
'operation of the device at these1lt'iany otherconditions"aboVethose illdicated in the operational 'sections of the speclficationS'lanet implied, Exposure to
VL-GND ...................................... ; ........ : ......
VIt~-GND ..........•............. ,',... 1 •• ' ......... " ...... '........

$

','

absolute maximum ratirig;,conliJllioA&'for exte'nded periods' may'affect device rellabi!ity.

ELECTRICAL CHARACTERISTICS

'

MINIMAX LIMITS

PER CHANNEL

MiLiTARY

TEST CONDITIONS
SYMBOL

,

(TA =2SoC, V + =+, 15V" V': - ":'1SV, VL -' +.5'.()

CHARACTEFilmC

-55°C

+ 25°C

IIN(ON)

Input Logic Current

VIN - 2.4V (IH5053) = 0.8V (IH5052)

,10

±1

IIN(OFF)

Input, Logic Current

VIN -P.8V (IH5053) - 2.4V (IH5052)

,10

'DS(ON)

Drain-Source On
ResistanCe

IS -lOrnA, Vanalog - -10V to + 10V

75

ArOS(ON)

Channel ,to Channel
'DS(ON) Match

+125°C

,.

,

,COMMERCIAL
0

+ 25°C ,,+70°C

lQ

±10

±1

10

flO

75

100

80

80

100

UNIT

fAA,
,iA'
ri

30
(typ)

.Il

(typ)

±11
(typ)

±10
(typ)

V

25

,

VANALOO

Min. Analog Signal
Handling Capability

IO(OFF) I
IS(OFF)

Switch OFF Leakage'
Current

'\lANALOG= -10V to +10V

±1

100

±5

100

nA

ID(ON)
+IS(ON)

Switch On Leakage
Current'
"

Vo-Vs· -10V to +10V

±2

200

±10,

100

nA

toN

Switch "ON" Time

"RL - lkn, Vanalcg - -10V to + 10V

500

jooo

ns

toFF

Switch "OFF"

250

500

ns

Q(INJ.)

Charge 'i'njection,

15

20
(typ)

mV

(typ)

54
(typ)

'50

dB

(typ)

, See, Fig. 3

TIme

Min, Off IsolatiOn
Rejection Ratio

OIRR
1+

+ Power Supply
Quiescent Current

1-

- Power Supply
Quiescent Current

RL.+lk.ll, VanaIcg- -10V to +10V

See~!"ig. 3

See/Fig. 4
I -lMHz; RL -lOOn, CL'; 5pF
See Fig, 5

V+ - + 15V, V- - -15V, VL= +5V

+5V Supply
Quiescent Current

CCRR

Min, Channel, to ,'Channel One Channel Off
Cross Coupling·· Rejection
RatiO

".

are

10

100

10

10

100

fAA

10

10

100

10

10

100

p.A

10

10

100

10

10,

100

fAA

with GND

IVL

NOTE 1: Typical values

10

54
(typ)

lor design aid only, not guaranteed and not subject to productiOn testing,

I

3-94
Note: All, typical values ha~ been guaranteed by characterization and are notlested,

50
(typ)

dB

IH5052/IH5053
TEST CIRCUITS

rhI ":'

ov.fl. -D-1>--

~
INPUT

VOUT

-D----D-1>--f
r
LOGIC
INPUT

.

.to

TTL
LOGIC INPUT

(NO~_

·

YOUT

"-I

,on

'Opf

m
1:-'

AJW.OG_T

ANALOQINPU'

'":'":"

,oon

TC006121

TCOO6011

TCOO5911

Figure 3

Figure 5

Figure 4

NOTE 1: The 5053 is turned on by high "1" logic inputs and the 5052 is turned on by low "0" inputs; however O.BV to 2.4V describes the min. range for
switching properly. Refer to logic diagrams to see absolute value of logic input required to produce "ON" or "OFF" state.

TYPICAL PERFORMANCE CHARACTERISTICS
ros(ON) vs VANALOG SIGNAL
'00

...

(Per Channel)

ros(ON) vs POWER SUPPLY
VOLTAGE

,.

,.

10

....

+'~·C

",10

·c

+

:::.

J!l

c ..

·Cf=

.

Is = 1111A
@:!:15VSUPP

•

-10 -7.5

-5 -2.5

0

2.5

5

-I.,

7.5

10

.,

I-- e -

....

.

1,..00

:ttl

•

-10 -7.5 -5

-2.5

a

2.5

CHARGE INJECTION vs VANALOG
(SEE Figure 8) CL = 10,OOOpF

4Sr-,..--r-....,..--,.--,-r-'T'""""

-

.. ~+-++-+-l-I-+-~
""r--+-+-+---1r--+-+-+---I

I-"""

5

....

1201-+-+-+-1I--+-+-+-l

1-0

J:t-+-+--+-t-+-+--+--i
,.t-+-+--+-t-+-+--+--i

7.5

': tt~t:t:f:ttj

t.

-'0 -7.5 -5 -2.5

OP005601

OPOO5501

r------.,
I

II

... ~

I

r-..i'o

..
•,

J

".....
TTLLEYELS
C R
,.

fTl

~NEL+D_t>_-I.!

!'or-..
'00

CHANNa.

=I*iOGlv=~':.1
100

tit

10k

,.

~
r.ITofiD

I

*

IiI ,_
I
L -

+cH>--

vour

-r'r-~-.

I

L-----=lJ

1000

111

2.5

I

7.5

to

0P005701

CROSS COUPLING REJECTION vs FREQUENCY

,..

0

VANALOG (II)

"ANALOG (V~

VANALOG (II)

'510

2V""

@1MHz

FREQUENCY (Hz)
OPO05BOI

TC00621 I

CrossCoupling Rejection
Test Circuit

3-95
Note: All typical values have been guaranteed by characterization and. a(Eil. not. tested.

I

1"5052/IH5053

I

TYPICAL PERFORMANCE CHARACTERISTICS (CONT.)

;:,

~

I
;

OFF ISOLATION vs FREQUENCY
-'10

""""
...
"
!
-'00

(

...

~

-40

IV",

@.IIC

'"

-10
OIRR '" 2OLOG

o
1Hz

.UI

.....

v:un::)

10Hz 100Ha tic

,.

,.

,.
TC006301

_auINCY (Hz)
0P005901

Off Isolation Test Circuit
POWER SUPPLY QUIESCENT CURRENT vs LOGIC
FREQUENCY RATE

i''''
,.:

/~

,.~

·
,

too

I~

3.

·
!
•

i!.

~

I

to

a
w

I"

/

§

.1

"

WF001711

101

tic

,.

100II

LOGIC FMOUiNCY @ . . . DUTY CYCLI (Hz)
OPO06001

Logic Input Waveform

r-------~-, ·t5V

I
I
I

....,

(11111 TO

_II)

I

I

IN

I

I
II

V"'"

__

+11V

L..;
__
__
_ _ _ ...... _'--',
'11V
TTL
GATE

LCOOO91 I

Figure 6: + 15V Open Collector TTL Interface to IH5052/5053

r

3-96

Note: All typical values have been guaranteed by characterization and are not tested.

.D~OI1. i

IH5052/IH5053

I

APPLICATIONS

N

PROGRAMMABLE GAIN NON-INVERTING AMPLIFIER WITH SELECTABLE INPUTS

i

!eft
W

.... o--.t---.......

.... -..t---....,""--H
CM,

.... -;;t---.....-r
C'"

.... ---.+---..,...,

u.

C...

.." "

101kU

'101,
'101'
.S!I
AFOO2301

Figure 7: Active Low Pass Filter with Digitally Selected Break Frequency

..

ANALOG IWITCM

OECODUI

VIN'

MUX

SEOUENCE
RATE

VIN2

Do

..

RESET

.~,

D,
VIN4

D,

DUAL

,,-K FLIP ,LOP

I INPUT NAND
Poe'Ia'LlTIEI
TTL - 1 11S IN5410

I'QU'BILlT...
TTL· SNI473
CIIOI - C04027
ENABLE

OUT

CMOS - 1 1/3 CD4023

0----------'
AF002401

TRUTH TABLE (IH5052)
ENABLE

MUX
SEQUENCE
RATE

0
1
1
1
1
1

0
0
1 pulse
2 pulses
3 pulses
4 pulses

SEQUENCER
OUTPUT

SWITCH STATES
(- DENOTES OFF)

2°

21

SW1

SW2

SW3

SW4

0
0
1
0
1
0

0
0
0
1
1
0

ON
-

ON
-

-

-ON

-

ON

Figure 8: 4-Channel Sequencing MUX

3-97
Note: All typical values have been guaranteed by characterization and are not tested.

-

-

,: IM'505211H5053

I

-

:::. A LATCHING DPDT SWITCH
~

I

The latch feature insures positiye switching action in
response to non-repetitive or erratic' commands. The A1
and A2 inputs are normally low. A HIGH input to A2 turns 81
. and $2 ON, a HIGH to A1 turns S3 al)d S4 ON. Desiral:!le for
use with limit detectors, peak detectors, or mechanicalcontact closures.
,

TRUTH TABLE (IHSOS2)
~15V

COMMAND

-sv
So
A,

A2

A1

53 & 54

51 & 52

0
0

0

same
on

same

1
1

A,

OUAO 2 INPUT
NAND GATES

TTL -01l74C1O

OR OM_

.r

STATE OF SWITCHES
AFTER COMMAND

cllas . CD4011

DM74COO

.
AFOO2501

Figure 9: A latching DPOT

3-98
Note: All typical values have been guaranteed by characterization and are not tested.

1
0
1

off
off
on
INDETERMINATE

IH5108
8-Channel Fault Protected
CMOS Analog Multiplexer
GENERAL DESCRIPTION

FEATURES

. The IHS108 is a dielectrically isolated CMOS monolithic
analog multiplexer, designed as a plug-in replacement for
the HIS08A and similar devices, but adds fault protection to
the standard performance. A unique serial MOSFET switch
ensures that an OFF channel will remain OFF when the
input exceeds the supply rails by up to ±2SV, even with the
supply voltage at zero. Further, an ON channel will be
limited to a· throughput of about 1.SV less than the supply
rails, thus affording protection to any following.circuitry such
as op amps, DI A converters, etc.
A binary 3-bit address code together with the ENable
input allows selection of anyone channel, or none at all.
These 4 inputs are all TTL compatible for easy logic
interface; the ENable input also facilitates MUX expansion
and cascading .

•
•
•
•
•
•
•
•

All Channels OFF When Power OFF, for Analog
Signals up to ±2SV
Power Supply Quiescent Current Less Than 1mA
± 13V Analog Signal Range
No SCR LatchliP
Break-Before-Make Switching
Pin Compatible With HI-SOBA
Any Channel Turns OFF If Input Exceeds Supply
Ralls by Up to ± 2SV
TTL and CMOS Compatible Binary Address and
ENable Inputs

.ORDERING INFORMATION
PART NUMBER
IH510BMJE
IH510BIJE,
IH510BCPE

TEMPERATURE RANGE
-55°C to + 125°C
-20°C to +B5°C
O°C to 70°C

PACKAGE
16 pin CERDIP
16 pin CERDIP
16 pin plastic DIP

DECODE TRUTH TABLE

YouT D

A2
X
0
0
0
0

A1
X
0
0

1

1

0
0

1
1

1
1

1
1

Ao
X
0
1
0
1

0
1
0
1

EN
0
1
1
1
1
1
1
1
1

ON SWITCH
NONE
1
2
3
4
5
6
7
B

AO, AI, A2. EN
Logic "1" = VAH::: 2.4V
Logic "0" = VAL ~ O.BV
(outline dwg JE. PEl

Ao

A;

A2

EN (ENABLE INPUT)

3 LINE BINARY ADDRESS INPUTS
(1 0 11 AND EN HI
.
ABOVE EXAMPLE SHOWS CHANNEL. TURNED ON

LOO01901

Figure 1: Functional Diagram

TOPVJEW
CDOO4401

Figure 2: Pin Configuration

3-99
Note: All typical values have been guaranteed by characterization and are not tested.

I .1'11108
,,';;
I A8~OuiTE 'MAXI'M'U~ RATINGS ,.

"

Current (Any Terminal) ....... :;': .................. ~ ....... 20mA
Operating Temperature ......................... -55 to 125·C
Storage Temperature .... ; i-r, ........ ; ......:.... -65 10, .150·C
Lead Temperature (Solderirig, 10sec) .....• ; ........:.• ~OO·C
...................
:'.........; ...
~ .• , .';" f200mW
. POwer Dissipation*
.
'
:::
. ',':

VIN(A, EN) ................................... V- to (V+ -0.05)
VIN(A, EN) to Ground ........................... -15V to 15V
Vs or Vo to V+ ................................ ,. +2SV, '-40V
Vs or Vo ~o V- ...•............. ; ................. -25V, +40V
V+ to Ground ....•................... ~ ....... : ......... : ........ 16V
V- to. Ground •...............•.........................•..... -16V

,

"

"

• All leads soldered or welded 10 PC board: Derale 10tnWI"C above.70·C:

Stresses above Ihoselisled under Absolute Maximum flatings may cause permanenl dama~e 10 Ihe device. These are streSs riltings' only: and l~nctiOnal
operation of Ihe device al lhese or any other conditiOris above Ihose iridicaled in Ihe operational sections· of the specificatioils is' nOI implied: Exposure 10
absolute maximum raling conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(V of; ,= 15V, V- = -15V, VEN = 2.i4V. unless otherwise specified.)
MAX LIMITS

NO
CHARACTERISTIC

MEASURED
TERMINAL

TESTS

. TYP
2$'C

TEST CONDmONS

PER
TEMP

M SUFFIX

CSUFFIX

-55'C

25'C

125'C

~20'CI
G'C

UNIT

25'C

85'CI

-

7O'C

SWITCH
rOS(on)

StoD

8

VO-l0V,
IS--l.0mA

Sequence each
swnch on

700

1000

1000

1500

1200

1200

1800

8

Vo- -10V
IS· -1.0mA

VAL =0,8V,
VAH=2.4V'

500 .

1000

1000

1500

1200

1200

1800

~OS(on)~

'''05(On)

roS(on)max-i'D5(on)min

..,'S'!;.

S

%

rOS(on)avg.
VS-±10V

1S(0II) .

10(011)

S

P

,
10(on)

'0

a..

VS-l0V, VO- -lOY

0,02

iO.S

50

itO

8

VS· -10V, VO= 10V

0,02

iO.5

50

il.0

50

1

VO- 10V, Vs = -IOV

0,02

il.0

100

100

1

VO· -tOV, VS" 10V

O.OS

itO

100

i2.0
±2,0

8

VS(IIIQ = Vo = 10V

Sequence eaCh
switch on

0,1

±2,0

100

i5

100

8

VS(AIQ=VO= -10V

VAL -0.8V,
VAH=2,4V,
VEN=2.4V

0,1

i2,0

100

' i5

100

VEN=0.8V

50
nA

tOO

FAULT
IS with
Power OFF

S

6

VSUpp = OV, VIN - ±2SV,
VEN=VO=OV, Ag, AI, A2=OV

t.O

2.0

5,0

IIS(0ff) with
Ov9fV01lage

S

8

VIN = ±25V, VO· il0V

1.0

5.0

10

AO, At, A21
or,
EN

4

pA

INPUT
IEN(on) IA(on)
or
IEN(Off} IAIOff}
DYNAMIC

I

I

VA =2.4V or OV

0,01

I

I

itO

0.01

it,O
1

ttransition

0

See Figure 3

0.3

IoDen

0

See Figure 4

0.2

IonIEN)

0

See Figure 5

0.6

1,5

ioff(EN)
Ion'foff Break·
Before-Make
Delay Settling
TIme

0

0.4

'I

"OFF" IsolatiOn

D

Cs(oII)

S

VS·O

Coloff}
C05(off}

0

Vo-O

VEN= OV,
I-140kHz

VS-O, Vo=O

to 1 MHz

0

o.to S

I

I

-30

-10

I

-30

,

VA=I5VorOV

8

VEN -

+ SV, Ag, At, A2 Strobed
VIN - ± IOV, Figure 6

VEN-O, RL -200n, CL=3pF, VS-3 YAMS,
f= 500kHz

30

to

I

pA

30

/JS

to

60

dB

5
25
1

pF

3-100
Note: All typical values have been guaranteed by characterization· and are not tested.

,

IH5108
CHARACTERISTIC

MAX UMITS

NO
TESTS
PER
TEMP

MEASURED
TERMINAL

M SUFFIX

TYP
25'C

TEST CONDITIONS

- 55'C

J I
25'C

C SUFFIX

- 2Q'CI

125'C

D'C

I I
25'C

UNIT

85'CI
7O'C

SUPPLY
Supply

1+

Current

I-

1

I

VEN

I

1

~5V

I

All VADD =OV/5V

0.5

0.7

I

0.6

I

0.5

0.02

0.7

I

0.6

I

0.5

I

I

1.0

I

I

1.0

I

Note 1. Readings taken 400rns after the overvoltage occurs.

SWITCHING TIME TEST CIRCUITS
+11SY

V.
tr<100na

V+

"<

~1OV

lOOns

YOUT

Va1:;1; +10V

lISa = -10V
:a:10V
PROBE

-15V

~_""_..._:_:T':.:
..

-

-:t:o

Vour
VS1I= -10V

lISa = +10V

Cp
PROBE IMPEDANCE

~:=
WFOO1801

TC006701

Figure 3: ttransition Switching Test Circuit and Waveforms

+ISV

VOUT ---'¥"'s1'-=_--'fII::..:..._ _ _ _ _ _ _~_
II, ON

SoON

~%

V.

-I tape. 1-

-II... 1WFOO1901

TCOO6801

Figure 4: t open (Break-Before-Make) Switching Test Circuit and Waveforms

+15V

3V

VE.

A2r--'--}-'4>----1-Q VOUT
35pF

WFOO2001
TC006901

Figure 5: ton and toff Switching Test Circuit and Waveforms

3-101
Nole: All typical values have been guaranleed by characterizalion and are nol lesled.

rnA

"~

IMa.s:

It»

!

'SWITCHING TIME TEST CIRCUITS (CaNT.)

lao .ncl1oH OF LOGIC
INPUT s10fta

,

+3V

,

Ao.A,.A•
I-- 4oO-L.I _ _ _S:;EO=.UENCEO

.;;,OV;...._ _...

,I:'

,:

I I

BREAK.BEFORE
MAKEOELAV-V-

II

INPUT

~I '-+1OV

V

:

=-------T----~------

~

BREAK·BEFORE
MAKEOELAV-

IOKn

,
-

-

OV

W

INPUT
--IOV
WFOO2101

TCOO7001

Figure 6: Break-Before-Make Delay Test Circuit and Waveforms
Within the normal analog signal range, the inherent
variation of switch ON resistance will balance out almost as
well as the customary' parallel configuration, but as the
analog signal approaches either supply rail, even for an ON
channel, either the p- or the n-channel will become a source
follower, disconnecting the charmel (Figure 8). Thus protection is provided for any input or output channel against
overvoltage, even in the absence of multiplexer supply
voltages. This applies up to the breakdown voltage of the
respective switches. Figure 9 shows a more de~ailed
schematic of the channel switches, including the back-gate
driver devices which ensure, optimum channel ON resistances and breakdown voltage under the various conditions.

DETAILED DESCRIPTION
The IH5108, like allintersil's multiplexers, contains a set
of CMOS switches that form the channels, and driver and
decoder circuitry to control which channel turns ON, if any.
In addition, the IH5108 contains an internal regulator which
provides a fully TTL compatible ENable input that is
identical in operation to the Address inputs. This does away
with the special conditions that many multiplexer enable
, inputs require for proper'logic swings. The identical circuit
conditions of the ENable and Address lines also helps
ensure the extension of break-before-make switching to
wider multiplexer systems (see applications section).
Another, and more important difference lies in the
switching channel. Previous devices have used parallel nand p-channel MOSFET switches. While this scheme yields
reasonably good ON resistance characteristics and allows
the switching of rail-to-rail input signals; it also has a number
of drawbacks. The sources and drains of the switch
transistors will conduct to the substrate if the input goes
outside the supply rails, and ,even careful use of diodes
cannot avoid channel-to-output and channel-to-channel
coupling in ca!;es of input overrange. The IH5108 uses a
novel series arrangement of the p- and n-channel switches
(Figure 7) combined with a dielectrically isolated process to
eliminate these problems.
'
-15V

+15V

+25YFORCED

-av
OVERVOLTAGE

S

D

S

N-CHAHNELMOSFET-r/JD

ISTURNEDON
BECAUSE Va _ + 25Y

'.CHANNEL

":"

Q

ON.COMMON
OUTPI,IT
LlNEIY

03

Qa

S

Q

TD'"

..l.
':"

EXtE,RNAL

CIRCU1TRY

N-CHANNEL
M08FET IS OFF

MO$FET IS OFF

08001901

(a) OVERVOLTAGE WITH MUX POWER OFF

-l-ll1~
'I-: -~-: ~

-1IV

OVERVOLTl:V
/,

_INPUT~OUTPUT
l~ l~ l~ _
I I T

N-CHANNEL MOSFET
TURNED ON
BECAUSEVoa_ +1OY

as

+--__+-~---="'_.:I

~C~:C:~~AY

, M O S F E T IS OFF
-15VFAOM +15VFROM P.CHANNEL
DRIVERS
DRIVERS MOSFET IS OFF
08002001

(b) OVERVOLTAGE WITH MUX POWER ON

Figure 8: Overvoltage Protection

-15VFROM +15YfROM

DRIVER

DRIVER
08001801

Under some circumstances, if the logic inputs are present
but the multiplexer supplies are not, the circuit will use the
logic inputs as a sort of phantom supply; this could result in
an output up to that logic level. To prevent this from

Figure 7: Series Connection of Channel
Switches

3-102
Note: All typical values have been guaranteed by characterization and are not tested.

IH5108
DETAILED DESCRIPTION (CONT.)
occurring, simply ensure that the ENable pin is LOW any
time the multiplexer supply voltages are missing (Figure 10).
lOOpF

s

08002201

Figure 10: Protection Against Logic Input

MAXIMUM SIGNAL HANDLING
CAPABILITY
The IH510B is designed to handle signals in the ±10V
range, with a typical rOS(on) of 600n; it can successfully
handle signals up to ± 13V, however, rOS(on) will increase to
about 1.Bkn. Beyond ± 13V the device approaches an open
circuit, and thus ±12V is about the practical limit, see Figure
11 .

• '5V

Figure 12 shows the input/output characteristics of an
ON channel, illustrating the inherent limiting action of the
series switch connection (see Detailed Description), while
Figure 13 gives the ON resistance variation with temperature.

0500210)

Figure 9: Detailed Channel Switch Schematic

..

..

t

21<0
"OFf" BEYOND
TIllS VOLTAGE

1.51(0

lK1l

3-103
Note: All typical .values have been guaranteed by characterization and are not tested.

co
....010 IH5i08

is

+1IouT
1.
14
12
10

IIouT

•

VIN

-4

-I
-I
-10
-12
-14

-18
-VOUT
SCOOO201

Figure 12: MUX Output Voltage vs Input Voltage (Channel

Shown; All Channels Similar)

10000

8CIOII

300!1
2OO!l
100II

-SSOC

-25°C

7SOC

125°C

TEMPERATURE
sc000301

Figure 13: Typical rDS(on) Variation With Temperature

3-104
Note: All typical values have been guaranteed by characterization and are not tested.

IH5108
USING THE IH5108 WITH SUPPLIES
OTHER THAN ± 15V
The IH51 08 will operate successfully with supply voltages
from ±5V to ±15V, however rOS(on) increases as supply
voltage decreases, as shown in Figure 14. Leakage currents, on the other hand, decrease with a lowering of supply
voltage, and therefore the error term product of rOS(on) and
leakage current remains reasonably constant. r05(on) also
decreases as signal levels decrease. For high system
accuracy [acceptable levels of rOS(on)] the maximum input
signal should be 3V less than the supply voltages. The logic
levels remain TTL compatible.

FOR

~
s2VSlGNAL5

+lOVSlGNAL
-IOVSlGNAL

APPLICATION NOTES
Further information may be found in:
A003 "Understanding and Applying the Analog Switch,"
by Dave Fullagar
A006 "A New CMOS Analog Gate Technology," by Dave
Fullagar
A020 "A Cookbook Approach to High Speed Data
Acquisition and Microprocessor Interfacing," by Ed
Slieger

zSV

slOV

:t:1SV
SC0Q0401

Figure 14: Typical rDS(on) Variation With
Supply Voltages

IH5108 APPLICATIONS INFORMATION
DECODE TRUTH TABLE
+1&V

-1&V

EN

1-

":'

At
A,

So

5,

+1&V

-15V

At

\'ouT

At

mOR
CMOS
INVERTER

":'

IHI10I

EN

s,.

So

A3

A2

A1

Ao

ON SWITCH

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1

51
52
53
S4
55
56
57

0
1

58
59
S10
511
512
513
514
515
516

AFOO2601

Figure 15: 1 of 16 Channel Multiplexer Using Two IH5108s. Overvoltage Protection Is Maintained
Between All Channels, As Is Break-Before-Make Switching.

3-105
Note: All typical values have been guaranteed by characterization and are not tested.

I
is

1..5108
IH5108 APPLICATIONS INFORMATION (CONT.)
~

T

TTUCMOS INVERTER

:::L>-

Ao

TTUCIIOS NOR GATE

......

IHllOI
10UTOFa
MUX

A.

I

.......

...

I!tI

I

-

I!
•

IH6108

.OUTOFa
MUX

1~

-

'I

•

ANALOG INPUTS

n
J.

'-1
1

IN.

rD-r>i

. . ANALOG INPUTS U

J"

A3

A2

A1

AO

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

(}

0
0
0
1
1
1
1

Jv

AF002701

DECODE TRUTH TABLE

DECODE TRUTH TABLE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0,

S.

i

A4

O.

r--<

....0

.L

J.

>--OVaUT

s!..,.

• OUT OF a
I MUX

'-----ii"

02,

IH5053

IH5101

~

f-D-t>-l
S.

~

~

~

J>'

.~

EN

I

Ih

1

ANALOG INPUTS ..

~
~
I

s.

IN.

IHllOI
10000Fa
MUX

EN

1'17

n
!!!!

~

4...

I

1

j

1 ANALOG INPUTS •

I:

+r

VL

ON SWITCH
81
82
83
84
85
86
87
88
89
810
811
812
813
814
815
816

A4

A3

A2

A1

Ao

ON SWITCH

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
'0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

817
818
819
820
821
5,22
823
824
825
826
827
828
829
830
831
832

Figure 16: 1 Of 32 Multiplexer Using 4 IH5108s and An IH5053 As A Submultlplexer. Note That The
IH5053 Is Protected AgalnstOvervoltages By The IH5108s. Submultiplexlng Reduces
Output Leakage arid Capacitance.

3-106
Note: All typical values have been guaranteed by characterization and are not tested.

IH5116
16-Channel Fault Protec• •
CMOS Analog Multi
GENERAL DESCRIPTION

FEATURES

The IHS116 is a dielectrically
monolithic
analog multiplexer, designed as a plug-in replacement for
the HIS06A and similar devices, but adding fault protection
to the standard performance. A unique serial MOSFET
switch ensures that an OFF channel will remain OFF when
the input exceeds the supply rails by up to ±2SV, even with
the supply voltage at zero. Further, an ON channel will be
limited to a throughput of about 1.SV less than the supply
rails, thus affording protection to any following circuitry such
as op amps, D/A converters, etc. Cross talk onto "good"
channels is also prevented.
A binary 2-bit address code together with the ENable
input allows selection of any channel pair or none at all.
These 3 inputs are all TTL compatible for easy logic
interface. The ENable input also facilitates MUX expansion
and cascading.

•

ORDERING INFORMATION

DECODE TRUTH TABLE

isolat~~r~MOS

PART
NUMBER

TEMPERATURE
RANGE

•
•
•
•
•
•
•
•

PACKAGE

IH5116MJI

-S5°C to + 125°C

28 pin CERDIP

IH5116CJI

O°C to + 70°C

28 pin CERDIP

IH5116CPI

O°C to + 70°C

28 pin Plastic
DIP

'Ceramic package available as special order only
(IHS116MDI/CDI)

All Channels OFF When Power OFF, for Analog
Signals Up to ±25V
Power Supply Quiescent Current Less Than 1mA
±13V Analog Signal Range
No SCR Latchup
Break-Before-Make Switching
TTL and CMOS Compatible Strobe Control
Pin Compatible With HI506A
Any Channel Turns OFF If Input Exceeds Supply
Rails By Up to ±25V
TTL and CMOS Compatible Binary Address and
ENable Inputs

A3

Az

A1

Ao

EN

ON SWITCH

X
0
0
0
0
0
0
0
0

X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

X
0
1
0
1
0
1
0
1
0

0

NONE

1
1
1

1
1

1
1
1

CD031311

Figure 1: Pin Configuration
(Outline dwg JE, PEl

3-107
Note: All typical values have been guaranteed by characterization and are not tested.

1

1

2
3
4
5
6

1
1
1
1
1

1

1
1
1

0
1
0
1
0
1

1
1
1
1
1
1

Logic "1" = VAH 2: 2.4V VENH 2: 2.4V
Logic "0" =' VAL $ 0.8V

TOPYIEW
Y" COMMON TO SUBSTRATE

1

7
8
9

10
11
12
13
14
15
16

!

1ft

1"5110
.\ ,

Z
~
s,~

s.~

s. 0--:---;.
s.~
s.~
s.~
s,~
s,~

VOUT
D

S,C>---+-

S'O~
s,'~

$,,0----'<

s,. o-:----:"'i
s.. ~
s.. ~
S.. ~
TO OEtODE LOGIC
COIiTROlLlIG 10TH
TlElIS OF MUXIfIG

4 LIIIE IIIAR' AOOIIESS IlPUTS
(OGOI) AIIO II • 5V
ABOVE ElWIPlE SHOWS CHAIIIElS I TURNEO 01.
LD011311

Figure 2: Functional Diagram

+15V
+3.0V
VA+~

VOUT
.~~~,

VA

0

O.9~~

~........~~~---r~VO~
35pF

WK'· ;iL.'
open

-t-

-

open

I

Vs
WF00301t

TC038501

Figure 3: t open

(Bre~k·Before-Make)

3-108
Note: All typical values have been guaranteed by characterization and are not tested.

Switching Test

ien

IH5116

......
G»

ABSOLUTE MAXIMUM RATINGS
VIN (A, EN) to Ground ....................... -15V to + 15V
Vs or VD to V+ ............................... +25V to -40V
Vs or VD to V- ................................ -25V to + 40Y

Current (Any Terminal) .................................... 20mA
Operating Temperature ..... :................. -55 to +~25~C
Storage Temperature .......... : .............. -65 to + 150·C
Lead Temperature (Soldering, 10sec) ................. 300·C
Power Dissipation· ...................................... 1200mW

V+ to Ground ................................................. 16V
V- to Ground ................................................ -16V

'Allieads soldered or welded to PC board. Derate 10mW/·C above 70·C.

8tresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (v+
CHARACTERISTIC

= 15V, v- = -15V, VEN = 2.4V, unless otherwise specified.)
MAX LIMITS

NO
MEASURED TESTS
TERMINAL
PER
TEMP

TYP
25·C

TEST CONDITIONS

M SUFFIX

C SUFFIX

UNIT

-55·C

25·C

125·C

G·C

25·C

7G·C

SWITCH
8 to D

ROS(on)

16

VO-l0V,
IS - -1.0mA

Sequence each
switch on

700

1000

1000

1500

1200

1200

lBOO

16

VO= -10V
IS = -1.0mA

VAL = O.BV,
VAH = 2.4V

500

1000

1000

1500

1200

1200

1BOO

LlROS(on)

LlROS(on) -

ROS(on)max""ROS(on)min

5

n

%

ROS(on)avg.
VS=±10V

8

IS(oft)

D

IO(oft)

D

10(on)

16

Vs -10V,
VO- -10V

0.02

±0.5

50

±1.0

50

16

Vs - -10V,
VO= 10V

0.02

±0.5

50

±1.0

50

1

Vo - 10V,
Vs = -10V

0.05

±1.0

100

±2.0

100

0.05

±1.0

100

±2.0

100

0.1

±2.0

100

±4.0

100

100

:1:4.0

100

VEN

= O.BV

1

Vo = -10V,VS = 10V

16

VS(AII) = Vo = 10V

16

VS(AII) = Vo = -10V VAL = O.BV,
VAH = 2.4V

0.1

±2.0

VSUPP = OV, Y,N - ±25V,
VEN = Vo = OV, Ao, A1, A2 = OV or 5V

1.0

2.0

5.0

1.0

2.0

5.0

0.01

-10

-30

-10

-30

O.ot

10

30

10

30

Sequence each
switch on

nA

FAULT
IS with
Power OFF

8

16

IS(off) with
Overvoltage

8

16

A1,
A2, A3
or
EN

4

Y,N = ±25V, Vo

= ±10V

IIA

INPUT
IEN(on) IA(on)
or
IEN(oft) IA(oft)
DYNAMIC

Ao,

VA

4

= 2.4V

or OV

VA = 15V

ttransition

D

0.3

Iopen

D

0.2

Ion(EN)

D

0.6

1.5

toff(EN)

D

0.4

1

Ion-loft BreakBefore-Make
Delay 8ettling
Time

D

"OFF"
Isolation

D

c,,(off)

8

Vs-O

D

Vo=O

CO(off)

16

D to S

COSLoff)
SUPPLY
Supply

I+ I

1+

Current

I- I

I-

Vs

I

IIA

1
ps

VEN - +5V, AD, A" A2 8trobed
Y,N = ±10V.

25

ns

VEN = 0, RL - 2oon, CL - 3pF,
Vs = 3VRM8, f = 500kHz

60

dB

= 0,

Vo = 0

VEN-OV,

5

f= 140kHz

25

to 1 MHz

1

1

I

All VA-OV/5V

0.5

I

I

VEN= 5V

0.02

pF

I

0.6

I

0.6

3-109
Note: All typical values have been guaranteed by characterization and are not tested.

I

I

1.0

I

I

1.0

I

rnA

!z High-Level
IM5140~I'H5145

Family

..

&
... CMOS Analog Switch
10

:!: GENERAL DESCRIPTION

FEATURES

ThelH5140Family of CMOS monolithic switches utilizes
Intersil's latch-free junction isolated processing to build the
fastest switches currently available. These switches can be
toggled at a rate of greater than 1MHz with super fast ton
times (80ns typical) and faster toft times (50ns typical),
guaranteeing break before make switching. This family of
switches combines the speed of the hybrid FET DG 180
family with the reliability and low power consumption of a
monolithic CMOS' construction.
OFF leakages are guaranteed to be less than 200pA at
25°C. Very low quiescent power is dissipated in either the
ON or the OFF state of the switch. Maximum power supply
current is 1pA from any supply and typical quiescent
currents are in the 10nA range which makes these devices
ideal for portable equipment and military applications.
The IH5140 Family is completely compatible with TTL
(5V) logic, TTL open collector logic and CMOS logic. It is pin
compatible with Intersil's IH5040 family and part of the
DG180/190 family as shown in the switching state diagrams.

• . Super Fast Break-Before-Make Switching
• ton 80ns Typ. toft SOns Typ (SPST SWitches)
• Power Supply Currents. Less Than l.pA
• OFF Leakages Less Than 100pA @ 25°C
Guaranteed
• Non-latching With Supply Turn-off
• Single Monolithic CMOS Chip
• Plug-in Replacements for IH5040 Family and Part
of the DG180 Family to Upgrade Speed and
Leakage
• Greater Than 1MHz Toggle Rate
• Switches Greater Than 20Vp-p Signals With ±15V
Supplies
• TTL. CMOS Direct Compatibility

ORDERING .INFORMATION
Order
Function
Part Number
IHSI40
IHSI40
IHS140
IHSI40

MJE
CJE
CPE
MFD

SPST
SPST
SPST
SPST

IHS141
IHS141
IHS141
IHS141
IHS141
IHS141

MJE
CJE
CPE
MFD
CTW
MTW

Dual
Dual
Dual
Dual
Dual
Dual

IHS142
IHS142
'IHSI42
IHS142
IHS142
IHS142

MJE
CJE
CPE
MFD
CTW
MTW

IHS143
IHS143
IHS143
IHS143

Package
CEADIP
CEADIP
Plastic DIP
Flat Pack

-SS'C
O'C to
O'C to
-SS'C

to 12S'C
70'C
70'C
to 12S'C

16 Pin CEADIP
16 Pin CEADIP
16 Pin Plastic DIP
14 Pin Flat Pack
TD·l00
TO·l00

- SS'C
O'C to
O'C to
-SS'C
O'C to
- SS'C

to 12S'C
70'C
70'C
to 12S'C
70'C
to 12S'C

SPOT
SPOT
SPOT
SPOT
SPOT
SPOT

16 Pin CEADIP
16 Pin CEADIP
16 Pin Plastic DIP
14 Pin Flat Pack
TO·l00
TO·l00

-SS'C
O'C to
O'C to
- SS'C
O'C to
- SS'C

to 12S'C
70'C
70'C
to 12S'C
70'C
to 12S'C

MJE
CJE
CPE
MFD

Dual SPOT
Dual SPOT
Dual SPOT
dual SPOT

16
16
16
14

-SS'C
O'C to
O'C to
- SS'C

to 12S'C
70'C
70'C
to 12S'C

IHSI44
IHSI44
IHSI44
IHSI44
IHS144
IHS144

MJE
CJE
CPE
MFD
CTW
MTW

DPST
DPST
DPST
DPST
DPST
DPST

16 Pin CEADIP
16 Pin CEADIP
16 Pin Plastic DIP
14 Pin Flat Pack
TO·l00
TO·l00

- SS'C to 12S'C
O'C to 70'C
O'C to 70'C
- SS'C to 12S'C
O'C to 70'C
- SS'C to 12S'C

IHS14S
IHS14S
IHS14S
IHS14S

MJE
CJE
CPE
MFD

Dual
Dual
Dual
Dual

16
16
16
14

- SS'C to 12S'C
O'C to 70'C
O'C to 70'C
- SS'C to 12S'C

Note:

16
16
16
14
SPST
SPST
SPST
SPST
SPST
SPST

DPST
DPST
DPST
DPST

Pin
Pin
Pin
Pin

Temperature
Range

Pin
Pin
Pin
Pin

Pin
Pin
Pin
Pin

CEADIP
CEADIP
Plastic DIP
Flat Pack

CERDIP
CERDIP
Plastic DIP
Flat Pack

'000

I~T O>-'\/IIIr......."Io--...,

lOOO2001

Figure 1: Functional Diagram Typical Driver!
Gate - IH5142

1. Ceramic (Side braze) d9V1C9S also available; consult factory. .
2. MIL temp range parts also available with MIL-STD-883 proCessing.

3-110
Note: All typical values have been guaranteed by characterization and are not tested ..

IH5140-IH5145
ABSOLUTE MAXIMUM RATINGS
V+ - v- ..................................................... <33V
V+ - Vo ..................................................... < 30V
Vo - V- ..................................................... < 30V
Vo - VS .................................................... < ±22V
VL - V- ...................................................... < 33V
VL - VIN ..................................................... < 30V
VL .............................................................. < 20V
VIN ............................................................. < 20V

Current (Any Terminal) ................................. < 30mA
Storage Temperature ...................... -65·C to + 150·C
Operating Temperature ................... -55·C to + 125·C
Lead Temperature (Soldering 1Osee) .................. 300·C
Power Dissipation ......................................... 450mW
(All Leads Soldered to a P.C. Board)
Derate 6 mWI"C Above 70·C

NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(@ 25·C, v+ =

+15V, v-= -15V, VL= +5V)

PER CHANNEL

MINIMAX LIMITS
TEST CONDITIONS

SYMBOL

CHARACTERISTIC

MILITARY
-55·C

UNIT

COMMERCIAL

+ 25·C + 12S·C

0

+2S·C

+70·C

LOGIC INPUT
IINH

Input Logic Current

VIN = 2.4V Note 1

±1

±1

10

±10

10

IINL
SWITCH

Input Logic Current

VIN = O.BV Note 1

±1

±1

10

±10

10

iJA
iJA

rOS(on)

Drain-Source On
Resistance

IS= -10mA
VANALOG = -10V to +10V

50

50

75

75

100

n

ArOS(on)

Channel to Channel
rOS(on) Match
Min. Analog Signal
Handling Capability

VANALOG

75

30
(typ)

n

(typ)

±11
(typ)

±10
(typ)

V

25

10(011)+
IS(off)

Switch OFF Leakage
Current

Vo= +10V, Vs= -10V
Vo= -10V, Vs= +10V

±.5
±.5

100
100

±5
±5

100
100

nA

10(on)+
IS(on)
CCRR

Switch On Leakage
Current

VO=VS- -10V to +10V

±1

200

±2

200

nA

Min. Channel to
Channel Cross
Coupling Rejection
Ratio

One Channel Off; Any Other
Channel Switches
See Performance Characteristics

ton
toff

Switch "ON" Time
Switch "OFF" Time

See switching time specifications and timing diagrams.

Q(INJ.)

Charge Injection

See Performance Characteristics

OIRR

Min. Off Isolation
Rejection Ratio

f = lMHz, RL = toOn, CL S 5pF
See Performance Characteristics

SUPPLY
1+

+ Power Supply
Quiescent Current

1-

- Power Supply
Quiescent Current

IL

+5V Supply
Quiescent Current

IGNO

Gnd Supply
Quiescent Current

NOTES:

V+ = +15V, V - = -15V,
VL = +5V

54
(typ)

50
(typ)

dB

10
(typ)

15
(typ)

pC

54
(typ)

50
(typ)

dB

1.0

1.0

10.0

10

10

100

iJA

1.0

1.0

10.0

10

10

100

iJA

1.0

1.0

10.0

10

10

100

iJA

1.0

1.0

10.0

10

10

100

IJ.A

See Performance Characteristics

1. Some channels are turned on by high (1) logic inputs and other channels are turned on by low (0) inputs; however O.BV to 2.4V
describes the min. range for switching properly. Refer to logic diagrams to find logical value of logic input required to produce ON or
OFF state.
2. Typical values are for design aid only, not guaranteed and not subject to production testing.

3-111
Note: All typical values have been guaranteed by characterization and are not tested.

=
z
;;

...

.H5140~IMa145
TYPICAL PERFORMANCE CHARACTERISTICS

..• .

~

I

eo
0

S

-

30

+1D

+8

+fS

.'25"C

....

-u·e

20

.'.

I

-r-- t-- i---I'-- r-

40

IH61.'0ATA

I

I

50

-.2OF==:::f:::==:t--T--t-------1

I

! i

eo

1

,

.

I

-20

SOCKn ON CQ'HJt GAOUHDI'lANE JIQ

I
-2

+2

+4

c- ,,,F

~OO=-~~~.~K~~~~.~~-L~UU.OOK~-L~~.~M--~~~,~
...

-10

FREQUENCV (Hzt

ANALOG SIGNAL VOLTAGE (V)
OP006401

0P006201

"OFF" Isolation vs. Frequency

rDS(on) vs. Temp., @ ±15V,
+5V Supplies

ur-~~II~~--r-rT~nn--~,-rr~

... I--------I-----'----l--...:.-...:.~.;.:..~

2~r_----------4_-----------+----------~

.00

\

eo

ul-------I-

eo
§

I

i

--..r-- 1--'

80

"

!

5V, .SV SUPPLIES

r--...i

V

II

I

I

I

50
40

r-

I

30

_~lOV ••SV

TA. '"' +25"C
IH51., DATA

I I T

SUPPLIES--

1

t--...

1%15v. .sv

~IES
T

.'0 +.

20

+&

+4

1'2

OPOO6501

ANALOG SIGNAL, VOLTAGE fV'

Pow.er Supply Currents vs. Logic Strobe
Rate

OPOO6301

rDS(on) vs. Pow.er Supplies

-'20

+.00

I

"I--+-~~=--+--+---

-'00

j

~

~
1

8

.

-

•
-... -eo
>1

4'r_--~~~-+--4---+-

;:

J ....

.\1....(:,

>i _'Oll-;-~:'--+f'--+--+_-+-.::..,t-T:.:.;... ·\1"'11'"' ~

-'00

-VIfW'CT~

r--t--t--t--+--+-+-+-+' .". . .

.ov..
.FRIQuENCY
-V_lOG

-20

c:,
0
100

-'0

-.ERIOO Of 'ULIE REPETITION RATE (101"

-2

+.0

'K

'OK

,-

1M

10M

FREQUENCY ftb)

ANALOG SIGNAL VOLTAGE (V)
OP0111Of

Channel to Channel Cross Coupling
Rejection vs. Frequency

OPOO9601

Charge Injection vs. Analog Signal

3--112
Note: All typical values have .been guaranteed by characterizatioo and are not tested.

.D~DIL

IH5140-IH5145
SWITCHING TIME SPECIFICATIONS
(ton. toft are maximum specifications and ton-toft is minimum specifications)
PART NUMBER

SYMBOL

IH51405141

IH51425143

CHARACTERISTIC

Ion

Switch "ON" time

loff
ton-loff

Sw~ch

Break-belore-make

ton
loff
lon-loff

Switch "ON" time
Switch "OFF" time
Break-belore-make

Ion
toff
ton-loff

TEST
CONDITIONS

COMMERCIAL

MILITARY
-55'C

+ 25'C

+ 125'C

0

+ 25'C

UNIT

+70'C

100

150

75

125

10

5

Figure 3

150
125
'10 (typ)

175
150
5

ns

Switch "ON" time
Switch 'OFF" time
Break-belore-make

Figure 2'

175
125
10

250
150
5

ns

ton
loff
ton-10ft

Switch "ON" time
Switch "OFF" time
Break-belore-make

Figure 3

200
125
'10 (typ)

300
150
5

ns

175

250

125

150

10

5

200

300

125

150

10

5

175

250

125

150

10

5

200
125
'10

300
150
5

Figu;e 2

"OFF" time

ton

Switch "ON" time

10ft

Switch "OFF" time

lon-10ft

Break-belore-make

Ion

Switch "ON" time

10ft

Switch "OFF" time

lon-10ft

Break-belore-make

ton

Switch "ON" time

10ft

Switch "OFF" time

IH5144-

ton-10ft

Break-belore-make

5145

ton
10ft
ton-10ft

Switch "ON" time
Switch "OFF" time
Break-belore-make

Figu;e 4

Figu;e 5

Figu;e 2

Figure 3

ns

ns

ns

ns

ns

I"N_O_T_E_:_S_W_IT_C_H_I_N_G_T_IM_E_S_A_R_E_M_E_A_S_U_R_E_D_@_9_0_%_P_T_S_____'_T_Y.,PicalvaluesIOrdeSign aid only, not guaranteed nor subject to production testing_

fijd

~
"en : ~

NOTE: SWITCHING TIMES ARE MEASURED @ 9O%PT5.

VOUTA

lOpF

,

16

2

15

I~'K!!

ton

:£

lOY

=-i

T 15V

~INPUT l~

13

7

•

i

-=-

.. __

~ .• ~llnAl

1H914

12

~

... UV

~c

~

I I VOUTAORB.
"

I

10%

,I -ISV i" I
~'NPUT
I

9

i :

,

+15v

• ',-"r--'

""f

~'_'OV!~T

11

, ~10V

.lOV@0
-:~ -lOV@ ~

INPUT

IOH

tON

16'1OY

,Op'

..clJ!~

14 -lSY

8

t--

Cotf
-i I--

il

IOV
"

:~-uv

-11Ion

--1:-

TCO0731I

lolf

Figure 4.
TC007111

Figure 2.

I~
VOUTA

lOpF

'"iT" ~I
0.5 •
~

o

.3V

~

-10VL.@

.,v

~
11 ..-,5V

3

--. r0

15

14 -15V

2

lKn

16 :rlOV

1

TTL INPUT

6

TTL INPUT

10
9

z10V

TC00721 I

TC007411

Figure 3.

Figure 5.
3-113

Note: All typical values have been guaranteed by characterization and are not tested.

II

IH5140-IH5145
. FLATPACK (FD-2)

DIP (JE, PEl
VL

12

"

..

ON.

SS00350t

SSOO3601

SPST

IH5140 (rDS(on) < 75U)
FLATPACK (FD-2)

T0-100

DIP (JE, PEl

v'

"

",

o-'-+---<>,-;,,-~.!..o.,

'•• ...,ro.~.....-

_,

GNO
S8003701

ss000901

DUAL SPST
1!'f5141 (rDS(on) < 75U)
FLATPACK (FD-2)

DIP (JE, PEl

T0-100 (00188 EQUIVALENT)

V'

.. o-t---o-o"""'I-<>.'
"

" o-'-l----<>-1r.y8>.,

...

.. o-'--I--""""~""",ro.·,
.. 0::1---<>"---..,..,0.

...

GNO

88004001

SS004201

SSOO410\

SPOT
IH5142 (rDS(on) < 75 U)
FLATPACK (FD-2)

DIP (JE, PEl (D0191 EQUIVALENT)

"
S,
'"
'"

D,
D,

o,
D.

5500<30'

SSOO4401

DUAL. SPDT
IH5143 (ros(OI1) < 75U)

SWITCH STATES ARE FOR LOGIC "1" INPUT

Figure 6: Switching State Diagrams

'3-114
Note: All typical values have been guaranteed by characterization and. are not tested.

iUI

IH5140-IH5145

...

FLATPACK (FD-2)

f

T()..100

DIP (JE, PEl

...2:
UI

'"

"
" <>,-!,..---o'fLf.'-'o D,

UI

',o:.:,l--<>T'4-'<>D,

" o::.l--<>T'4-'-o D,

.. o-=-tl---o~t=<>D.

ON.
8S004501

v-

GND

SSOO46Of

55004601

DPST
IH5144 (ros(on)

< 75Q)

FLATPACK (FD-2)

DIP (JE, PEl (DG185 EQUIVALENT)

" <>"+--<>"""".:.0 .,
13

03

IN,

88004801
55004901

DUAL DPST
IH5145 (roS(on) < 75il)

Figure 6: Switching State Diagrams (Cont.)

TYPICAL SWITCHING WAVEFORMS

SCALE: VERT... 5V10IV. HORIZ.

= 100ns/0IV.

TTL OPEN COLLECTOR LOGfC DRIVE (Corresponds to Figure 8)

+125"C
WFOO4701

WF00220I.

WF002301

TTL OPEN COLLECTOR LOGIC DRIVE (Corresponds to Figure 9)

+25°C

-&SOc
WFOO2401

+12S·C
WF002501

3-115
Note: All typical values have been guaranteed by characterization and are not tested.

WF002601

TYPICAL SWITCHING WAVEFORMS (CONT.)
TTL OPEN COLLECTOR LOGIC DRIVE
(Corresponds to Figure 10)

TTL OPEN COLLECTOR LOGIC DRIVE
(Corresponds to Figure 11)

+25"1:

+25 0 C
WFOO2801

WFOO2701

APPLICATION NOTE

occur. Turning off the supplies would turn off the analog
signal at the same time.
This fault situation can also be eliminated by placing a
diode in series with the negative supply line (pin 14) as
shown in Figure 10. Now when the power supplies are off
and a negative input signal is present this dio(ie is reverse
biased and no current can flow.

To maximize switching speed on the IH5140 family, TTL
open collector logic (15V with a 1kil or less collector
resistor) should be used. This configuration will result in
(SPST) ton and Ioff times of 80ns and 50ns, for signals
between -10V and + 10V. The SPOT and OPST switches
are approximately 30ns slower in both ton and loft with the
same drive configuration. 15V CMOS logic levels can be
used (OV to + 15V), but propagation delays in the CMOS
logic will slow down the switching (typical 50ns -+' 100ns
delays).

I

ANALOG OUT

•

3

•

When driving the IH5140 Family from either +5V TTL or
CMOS logic, switching times run 20ns slower than if they
were driven from + 15V logic levels. Thus Ion is about
105ns, and toff 75ns for SPST switches, and 135ns and
105ns (ton, Iofl) for SPOT or OPST switches. The low level
drive can be made asfa~t as the high level drive if ±5V
strobe levels are I;ISed instead of the usual OV'.... + 3.0V
drive. Pin 13 is taken to -5V instead of the usualGNO and
strobe input is taken from +5V to -5V levels as shown in
Figure 7.

&

l ' ANALOG IN {CHANNEL AI

!

rrL

!iii

.:!!J '

• =
ANALOG, OUT

:

CMOS
LEVEL

IM'UT
STROBE

9

ANALOG IN {CHANNEL 81

AF002801

Figure 7,.

The typical channel of the IH5140 family conslsts of both
P and N-cllimn~1 MOSFETs. The N-channel MOSFET uses
a "Body, Puller" FET'todrive the body to -1SV(±'1Sv
supplies)t6 get good breakdown voltages when the switch
is in the off state (See Fig. 8). This "Body Puller" FET also
allows the N-channel body to electrically float when the
switch is in the on state producing a fair.ly constant
RoS(ON) with different signal voltages. While this "Body
Puller" FET improves switch performance, it can cause a
problem when analog input sigl1als are present (negative
signals only) arid 'power supplies are off. This fault condition
is shown, in Figure 9.

2:.15" FROM

DRIVERS

-16V

AFOO2901

Figure 8.

Current,will flow, from ':'10V analog voltage through the
drain to body junction of Q1, then through the drain ,to body
junction of OS to GNO. This means that there is 10Vacross:
two forward"biased silic,on diodes and current will go to
whatever value', the input signal Source is capable of
supplying. If the ~oalog input $ignal is derived from the
same supplies as the switch this fault condition cannot

AFOO3001

Figure 9.

3-116
Note: All typical values have been guaranteed by characterization: and are not

tes~ed,

IH5140-IH5145
APPLICATION NOTE (CONT.)
'i6

~r:~~UIVALENT

INA

~ PL.IN
... 1
(1.~or-----"f-- -'6V

(,1;)-----.
~
~

+15V

-;;<

IN.

~

,.1

-=1-

. .V

T2LBIN

AF00310l

Figure 10.

APPLICATIONS

+15V
+15V

2

r

3
ANALOG 0--+-"-4
INPUT

6 -+-OOUTPUT

510
-15V
10.000PF
POLY-=- STYRENE

I

LOGIC INPUT

+3V
OV =

IH5143

=> SAMPLE MODE
> HOLD MODE

AFOO3211

Figure 11: Improved Sample and Hold Using IH5143

16
15

+VANALOG

.s-L
TTL

12 "::"
+5V

11

+15V

10

9
2R

R
ETC.

R

LOGIC
STROBE

SL
+VANALOG

TTL

LOGIC
STROBE

R
ETC.
AF003311

EXAMPLE: If - VANALOG - -10VDC and + VANALOG = + 10VDC then Ladder Legs are switched between ± 10VDC, depending upon state of Logic
Strobe.

Figure 12: Using the CMOS Switch to Drive an R/2R Ladder Network (2 Legs)

3-117
Note: All typical values have been guaranteed by characterization and are not tested.

I

·IID~DI6

., I.H5140-IH5145

!z

.,.
j

APPL.ICATIONS (CONT.)
lOOk!)

!

LOGIC
STROBE
AF003401

CONSTANT GAIN, CONSTANT Q; VARIABLE FREQUENCY FILTER WHICH PROVIDES SIMULTANEOUS LOWPASS, BANDPASS, AND HIGHPASS
OUTPUTS. WITH THE COMPONENT VALUES SHOWN, CENTER FREQUENCY WILL BE 235Hz AND 23.5Hz FOR HIGH AND LOW LOGIC INPUTS
RESPECTIVELY, Q = 100, AND GAIN = 100.

fn

= CENTER

.

1

FREQUENCY = 21T RC

Figure 13: Digitally Tuned Low Power Active Filter

3-118

Note: All typical values have been guaranteed by characterization and are not tested.

IH5148-IH5151
High-Level CMOS
Analog Switches
GENERAL DESCRIPTION

FEATURES

The. IH5148 family of solid state analog switches are
designed using an improved, high voltage CMOS technology. Destructive latchup has been eliminated. Early CMOS
switches were destroyed when power supplies were removed with an input signal present; the IH5148 CMOS
technology has eliminated this problem.
Key performance advantages of the 5148 series are TTL
compatibility and ultra low-power operation. RDS(on) Switch
resistance is typically in the 14n To 18n Area, for Signals
in the -10V to + 10V range. Quiescent current is less than
10j.lA. The 5148 also guarantees Break-Before-Make
switching which is logically accomplished by extending the
tON time (200nsec typ.) such that it exceeds toFF time
120nsec typ.). This insures that an ON channel will be
turned OFF before an OFF channel can turn ON. The need
for external logic required to avoid channel to channel
shorting during switching is thus eliminated.
Many of the devices in the 5148 series are pin-for-pin
compatible with other analog switches, and offer improved
electrical characteristics.

•
•
•
•
•
•
•
•

Low RDS(ON) - 25n
Switches Greater Than 20Vpp Signals With ± 15V
Supplies
Quiescent Current Less Than 100j.tA
Break-Before-Make Switching tOFF 120nsec, Typ.
toN 200nsec Typical
TIL, CMOS Compatible
Non-Latching With Supply Turn-Off
Complete Monolithic Construction
±5V to ±15V Supply Range

CMOS ANALOG SWITCH PRODUCT
CONDITIONING
•
•
•
•
•
•
•

The Following Processes Are Performed 100% in
Accordance With MIL-STD-883
Precap Vlsual- Method 2010, Condo B
Stabilization Bake - Method 1008
Temperature Cycle-Method 1010
Centrifuge - Method 2001, Condo E
Hermeticity-Method 1014, Condo A, C
(Leak Rate < 5 x 10- 7 atm ccls)

ORDERING INFORMATION
ORDER PART
NUMBER

FUNCTION

PACKAGE

TEMPERATURE RANGE

HARRIS
EQUIVALENT

IH5148MJE
IHS148CJE
IH5148CPE
IH5148MFD
IH5148CTW
IH5148MTW

Dual
Dual
Dual
Dual
Dual
Dual

SPST
SPST
SPST
SPST
SPST
SPST

16 Pin CERDIP
16 Pin CERDIP
16 Pin Plastic DIP
14 Pin Flat Pack
TO-l00
TO-l00

-SS·C
O°C to
O°C to
- SO°C
O°C to
-SsoC

to 12SoC
lO°C
70°C
to 12S·C
70°C
to 12SoC

HI-5048
HI-S048
HI-S048
HI-5048
HI-S048

IHS149MJE
IHS149CJE
IH5149CPE
IH5149MFD

Dual
DuaL
Dual
Dual

DPST
DPST
DPST
DPST

16
16
16
14

-5S·C
O°C to
O°C to
-SO°C

to 125·C
70°C
70°C
to 12SoC

HI-S049
HI-5049
HI-S049
HI-S049

IHS1S0MJE
IHS1S0CJE
IH51S0CPE
IHS1S0MFD
IH51S0CTW
IHS150MTW

SPOT
SPOT
SPOT
SPOT
SPOT
SPOT

16 Pin CERDIP
16 Pin CERDIP
16 Pin Plastic DIP
14 Pin Flat Pack
TO-l00
TO-l00

-SS·C to 12SoC
O°C to 70°C
O°C to 70°C
-SO°C ,to 12S·C
O·C to 70°C
-SsoC to 12S·C

HI-S050
HI-SOSO
HI-5050
HI-S050
HI-SOSO
HI-5050

IHS1S1MJE
IH51S1CJE
IHS1S1CPE
IHS1S1MFD

Dual
Dual
Dual
Dual

16
16
16
14

-55°C
O°C to
O°C to
-50·C

HI-5051
HI-5051
HI-SOSl
HI-S051

SPOT
SPOT
SPOT
SPOT

Pin
Pin
Pin
Pin

Pin
Pin
Pin
Pin

CERDIP
CERDIP
Plastic DIP
Flat Pack

CERDIP
CEROIP
Plastic DIP
Flat Pack

to 125°C
70·C
lO°C
to 12SoC

HI~S048

NOTES: 1. Ceramic (side braze) devices also available; consult factory.
2. MIL temp range parts also available with MIL-STD-883 processing.

3-119
Note: All typical values have been guaranteed by characterization and are not tested.

304300-002

:.n~oll

i

IH5148.~IH5151·

!I

ABSOLUTE MAXIMuM RATINGS

I

V+, v- ...........................·............................ <3SV
v+, Vo ....................................................... <30V
VO, v- .................................................•...... <;: 30V
Vo, Vs ................................................. : ..... < .±22V
VL,. v- .................................................... :....... < 33V
VL, VIN ............ : .......................................... < 30V
VL ............................. ; ................................. < 20V
VIN................................................: ........... ,. < 20V

'10

Current (Any Terminal) .............................., .. < SOmA
Storage Temperature ...................... -SS·C to + 1S0·C
Operating Temperature ...... ; ..... , ...... -5S·C to . + 12S·C
Lead Temperature (Soldering, 1Qsec) ................. 300·C
Power Dissipation .......... ; .............................. .4S0mW
(All Leads Soldered to a P.C. Board)
Derate SmW I"C Above 70·C

NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions above those indicated in the operational sections. of the spec"ications is not implied.
E~posure to absolute maximum rating conditions for extended periods may affect device reliability.

+15V (vtl

4KO

51(0

16

BD014011

Figure 1: Functional Diagram (Typical SwltchSchematic-IH5150 in 16 pin DIP PKG.)

3-120
Note: All typical values have been guaranteed by characterization and are not tested.

.O~OIL

IH5148-IH5151
ELECTRICAL CHARACTERISTICS

(TA @ 25°C, V+

= +15V,

V-

= -15V,

PER CHANNEL

= +5V)

MINIMAX LIMITS
TEST CONDITIONS

SYMBOL

VL

COMMERCIAL

MILITARY

CHARACTERISTIC

+ 25°C

+ 70°C

IIN(ON)

Input Logic Current

VIN = 2.4V (Note 1)

±1

±1

±10

±1

±10

p.A

IIN(OFF)

Input Logic Current

VIN = 0.8V (Note 1)

±1

±1

±10

±1

±10

p.A

ROS(ON)

Drain-Source On
Resistance

Vo=±10V, 15= -10mA

25

25

50

30

n

-55°C

+ 25°C + 125°C

UNIT

0

AROS(ON)

Channel to Channel
ROS(ON) Match

10
(Typ)

15
(Typ)

n

VANALOG

Min. Analog Signal
Handling Capability

±14
(Typ)

±14
(Typ)

V

Switch OFF Leakage
Current

VANALOG = -10V to + 10V

±0.5

50

±1.0

100

nA

Switch On Leakage
Current

Vo= Vs = -10V to + 10V

±1.0

100

±2.0

100

nA

Q(INJ)

Charge Injection

See Figure 4

(10)
(Typ)

(10)
(Typ)

mV

OIRR

Min. Off Isolation
Rejection Ratio

1= lMHz, RL ~ tOOn, CL:S 5pF
See Figure 5

54
(Typ)

50
(Typ)

dB

IO(OFF)
IS(OFF)
ID(ON) +
IS(ON)

SUPPLY
1+

+ Power Supply
Quiescent Current

1-

- Power Supply
Quiescent Current

IL

+ 5V Supply
Quiescent· Current

IGNO

Gnd Supply
Quiescent Current

CCRR

Min. Channel to
Channel Cross
Coupling Rejection
Ratio

10

10

100

10

p.A

10

10

100

10

p.A

10

10

100

10

p.A

10

10

100

10

p.A

50

dB

VI = + 15V, V2 = -15V.
VL= +5V, VR=O

One Channel Off; Any Other
Channel Swijches as per
Figure B

54
(Typ)

NOTE 1: Some channels are turned on by high "I" logiC inputs and other channels are turned on by low "0" inputs; however O.BV to 2.4V describes the min.
range lor switching properly. ReIer to logic diagrams to lind logical valus 01 logic input required to produce "ON" or "OFF" state.

SWITCHING TIME SPECIFICATION
IH5148 SPST SWITCH
SYMBOL

MAX

UNIT

Ion

Swijch "on" time

PARAMETER

RL=IKn, VANALOG= -IOV

TEST CONDITIONS

MIN

250

ns

loll

Switch "off" time

To + 10V; See Figures 3 and 6

200

ns

IH5149 OPST SWITCH
SYMBOL

MAX

UNIT

ton

Switch "on" time

PARAMETER

RL = 1Kn;· VANALOG = -10V

TEST CONDITIONS

MIN

350

ns

loll

Switch "off" time

To + 10V; See Figures 3 and 6

250

ns

IH5150 & IH5151 SPOT SWITCH
MAX

UNIT

ton

Switch "on" time

RL = lKn, VANALOG = -10V

500

ns

loll

Switch "off" time

To + 10V; See Figures 3 and 6

250

ns

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

NOTE 2: For IH5150 & IH5151 devices, channels which are off lor logic input ~ 2.4V (Pins 3 & 4 on 5150, & Pins 3 & 4, 5 & 6 on 5151) have slower Ion time,
than channels on Pins I, 16, & 8, 9. This is done so switch will maintain break-balora-make action when connected in OT configuration, i.e. Pin 1
connected in Pin 3.

3--121
Note: All typical values have been guaranteed by characterization and are not tested.

...

".U~OIL

10
;; IH5148";I'H5151

;

I

......

' cD

"

SWITCH S1'ATESARE FOR
L()GIC "1" INPUT

DIP (DE) PACKAGE

FLAT PACKAGE

(TW) PACKAGE

10

;

DUAL.SPST IH5148
v,

"

v·

v·
,i

"

I,

.,
.,

0,

I,

0,

I,

.,

v,

II

"

II

I,

0,

.,

.,
lID

v·

..

II

v-

II'

SS007401

•

I,

0,

I,

...

v-

.

v88007601

S$007501

DUAL DPST IH5149
v,

v,

.
.,..
I,

0,
0,

I

_1

..
It

II
lID

.,

.,

.
I,

v·
n

"

..
t,

II
I

0,

,.

...

II

vS5007701

..

V-

55007801

SPDT IH5150

"

,.

"

,.

I,
I,

I,

..

•

,.
V,

n

II

,"

II

I,

..

t,

I,
I,

It

•

•

... .

II
lID

II

V88007901

SSOO8OOI

DUAL SPDTIH5151
v,

,.

.,....
I,

"

OJ

....

..'1
lID

.,

I,
I,

""

II

v·
n
0,

Is

.,

,

....

,.

II
OlD

SSOO82
  • - IOpf I m f:'" _oa ...... :: --D-i>- 1110 ",00000 5.0 LOGIC IUUT tlDro--t>-- ~ 1 '":'":" '000 ":'''':'' TC03681 I ~ TC037011 TC03691 I Figure 3 Figure 4 TYPICAL PERFORMANCE CHARACTERISTICS Figure 5 (Per Channel) ROS(ON) @ ±15V, ±5V SUPPLIES Ros(ON) o 100 90 80 70 60 50 40 30 20 10 ±5V SUPPLIES i@ .,...Er- 't!J A5V SUPPLIEs.. o -12V-l0-8-6 -4 -2 OV 2 +4V 6 8+10V+121 HDS (ON) vs ANALOG INPUT VOLTAGE 0P056911 CROSS COUPLING REJECTION vs FREQUENCY 120 .......... 100 =- ~ ... 80 ec 60 Vi C> II: :> . ~ '~-;¥ ~ ..... I" ..... .... ......... ~ ..... 40 3V INPu.!!"l.- 20 CCRR o 1 10 2oLOG 2000mVpp VOUT (mVpp) 100 1k 10k 100k 1M SWITCHED CHANNEL '" FREOUENCY (Hz) r I I I I I I I I I L"" VOUT 1000 ~I ~-I ~----1'" ~ 510 TC033521 OP056811 CROSS COUPLING REJECTION TEST CIRCUIT 3-123 Note: All typical values have been guaranteed by characterization and are not tested, ;; IIf5148-IH5151 ;; , ! TYPICAL PERFORMANCE CHARACTERISTICS (CONT.) OFF ISOLATION ,...120 ! i" -100 '- ~ ..... ii' -80 ~ ...ei&:" c :» VI FREQUENCY . 510 .... 1"'- ..... -60 -- OFF STATE ~_ OEPENDS ON. PART~ -40 -20 20LOG 2000mVpp VOur(mVpp) 1Hz 10Hz 100Hz lk 10k lOOk 1M = OIRR o l---o . 1 1000 Your .... FREQUENCY (Hz) TC033111 OFF ISOLATION TEST CIRCUIT POWER SUPPLY QUIESCENT CURRENT FREQUENCY RATE :!!i ~ + ffi z: 20 I ~ LOGIC / f = TI ~ ~ !i! ~ / ~ VI I 2 1 V 10 TC033411 100 lk 10k lOOk LOGIC FREQUENCY @ 10% DUTY CYCLE (Hz) OP056711 LOGIC INPUT WAVEFORM TC0367 2.4V VENH > 2.4V Logic "0" = VAL < O.8V v+ Db NC 3 S8b S7. S7b SIb" S8a S5a S4lI S3a S2a Ao A, A2 V+ COMMON TO SUBSTRATE CD035601 Figure 1: Pin Configuration (Outline dwgs JE, PEl 3-135 Note: All typical values have been guaranteed by characterization and are not tested. 1 1 1 1 1 1 1 1 1 2 3 4 5 6 7 8 IIH5216 ! 511 u.o---"'i S30o---"'i S40o---"'i S5ao---"'i ... 0-:--; 57. o---"'i ... 0---"1 Do till SI~ S2~0---"I S3IIo---"I Mo---"I S5IIo---"'i SIll 0---'"< S~O---:J S.o---'"< TO OlCOOl lOGIC COITROIUNG 80TH TIERS Of MUXI!IG 3 UIE "I'RY AOIHIfSS IIIPUTS 110 01 AID Ell • 5V AIOVE EXAMI'U SHOWS CHA.IElS I. 'NO ,_ ON. LD011211 Figure 2: Functional Diagram +15V WK' tIL +3.0V VA+~ .wrr~o~ VOUT 0 ~~~-r~~----~VO~ O.9VO Vo 35pF open - open Vs TC034611 TC038501 Figure 3: t open (Break-Before-Make) Switching Test 3-136 Nole: All typical values have been guaranteed by characterizalion and are nol l'1sled. iUI IH5216 ...N ~ ABSOLUTE MAXIMUM RATINGS VIN (A, EN) to Ground ....................... -15V to + 15V Vs or VD to V+ ............................... +25V to -40V Vs or VD to V- ................................ -25V to +40V Current (Any Terminal) .................................... 20mA Operating Temperature ...................... -55 to + 125·C Storage Temperature ......................... - 65 to + 150·C Lead Temperature (Soldering, 10sec) ................. 300·C Power Dissipation" ...................................... 1200mW V+ to Ground ............................. , ................... 16V V- to Ground ................................................ -16V "All leads soldered or welded to PC board. Derate 10mW/'C above 70'C. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and lunctional operation 01 the device at these or any other conditions above those indicated in the operational sections 01 the specilications is not implied. Exposure to absolute maximum rating conditions lor extended periods may allect device reliability. ELECTRICAL CHARACTERISTICS (v+ CHARACTERISTIC = 15V, v- = -15V, VEN = 2.4V, unless otherwise specified.) MAX LIMITS NO MEASURED TESTS TERMINAL PER TEMP TYP 25'C TEST CONDITIONS M SUFFIX C SUFFIX UNIT -55'C 25'C 125'C G'C 25'C 70'C SWITCH S to D ROS(on) 16 Vo -10V. IS= -LOrnA Sequence each switch on 700 1000 1000 1500 1200 1200 1800 16 Vo - -10V IS= -1.0mA VAL - 0.8V, VAH - 2.4V 500 1000 1000 1500 1200 1200 1800 .:l.Ros(on) ROS(on)max-ROS(on)min .:l.ROS(on) = n % 5 ROS(on)avg. VS=±10V S IS(oll) D 10(otl) D 10(on) 16 Vs -10V, Vo = -10V 0.02 ±0.5 50 ±1.0 50 16 Vs - -10V, Vo = 10V 0.02 ±O.S SO ±1.0 SO 1 Vo -10V. VS= -10V O.OS ±1.0 100 ±2.0 100 0.05 ±1.0 100 ±2.0 100 0.1 ±2.0 100 ±4.0 100 0.1 ±2.0 100 ±4.0 100 VEN =O.8V 1 VO= -10V,VS-10V 16 VS(AIJ) = Vo 16 VS(AIJ) = 10V = Vo = Sequence each switch on -10V VAL - 0.8V, VAH = 2.4V nA FAULT IS with Power OFF S 16 Vsupp = OV, VIN = ±25V, VEN=VO=OV, A(:), AI, A2=OV or SV 1.0 2.0 S.O IS(oII) with OVervoltage S 16 VIN = ±25V, Vo - ± 10V 1.0 2.0 S.O A(j, AI, A2 or EN 4 VA = 2.4V, or OV om -10 -30 -10 -30 4 VA=ISV 0.01 10 30 10 30 p.A INPUT IEN(on) IA(on) or lEN (off} IA(off} DYNAMIC ttransition D 0.3 Iopen D 0.2 Ion(EN) D 0.6 I.S D 0.4 1 \on-loll BreakBelore-Make Delay Settling Time D "OFF" Isolation D VEN = S Vs-O CO(otl) D Vo=O Supply Current D to S 1+ I- 1+ I- At, A2 Strobed VIN = ±10V. VEN = 0, RL = 200n, CL = 3pF, Vs = 3VRMS, I = SOOkHz Cs(otl) CDStoffl SUPPLY +SV,' A(:), Vs = 0, Vo - 0 1 I 1 I 1VEN-OV, 1I = 140kHz 1to 1 MHz p.A 1 IoIl(EN) 16 1 I'S 25 ns 60 dB 5 25 pF 1 1 0.5 I 0.02 All VA = OV/SV VEN=SV 3--137 Note: All typical values have been guaranteed by characterization and are not tested. 0.6 0.6 1 I 1 I 1.0 1.0 1 I mA ; IH5341 ('I) ; Dual SPST CMOS RFIVideo Switch GENERAL DESCRIPTION FEATURES The IHS341 is a dual SPST, CMOS monolithic switch which uses a "Series/Shunt" ("T" switch) configuration to obtain high "OFF" isolation while maintaining good frequency response in the "ON" condition. Construction of remote and portable video equipment with extended battery life is facilitated by the extremely low current requirements. Switching speeds are typically ton = lS0ns and toti = 80ns, and "Break-Before-Make" switching is guaranteed. Switch "ON" resistance is typically 40n-SOU with ± 15V power supplies, increasing to typically 175U for ±5V supplies. The devices are available in TO-l00 and 14-pin epoxy DIP packages. • • • • • • • • • ROS(on) < 75U Switch Attenuation Varies Less Than 3dB From DC to 100MHz "OFF" Isolation> 60dS @ 10MHz Cross Coupling Isolation> 60dB @ 10MHz Compatible With TTL. CMOS Logic Wide Operating Power Supply Range Power Supply Current < 1~ "Break-Before-Make" Switching Fast Switching (80ns1150ns Typ) ORDERING INFORMATION PART NUMBER TEMPERATURE RANGE PACKAGE IH5341 CPO o to +70·C 14-pin PLASTIC DIP IH53411TW -20·C to +85·C 10-pin TO-l00 IH5341MTW -55·C to + 125°C 10-pin TO-l00 s, o--~------<~--------J I ON,D I , I INz TOPYIEW TOI'VIEW COOO3301 LS00781t Figure 1: Functional Diagram (Switches are open for a logical "0" control input, and closed for a logical "1" control input.) Outline dwg: PO Outline dwg: TW Figure 2: Pin Configurations 3-138 Note: All typical values have been guaranteed by characterization and are not tested. 30S528-002 i IH5341 en ...... Col ABSOLUTE MAXIMUM RATINGS v+ to Ground ............................................... + 17V V- to Ground ................................................ -17V VL to Gro.und .......................................... V+ to VLogic Control Voltage ................................ V + to VAnalog Input Voltage ................................. V + to VCurrent (any Terminal) ..................................... 50mA Operating Temperature: (M Version) ......................... -55°C to +125°C (I Version) ............................. -25°C to + 85°C (C Version) .............................. O°C to + 70 0 e Storage Temperature ...................... -65°e to + 150 0 e Lead Temperature (Soldering, 10sec) ................. 300 oe Power Dissipation ......................................... 250mW Derate above 25°C @ ........•............. 7.5mW/oe Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. +15V -15V .......~--+-=-o SWITCH 05002901 Figure 3: Equivalent Schematic Diagram IH53411TW (1/2 of actual circuit on chip shown) 3-139 Note: All typical values have been guaranteed by characterization and are not tested. ; IH5341· :3 ! DC ELECTRICAL CHARACTERISTICS = + 15V, VL = +5V, v- = -15V, ·TA = 25°C unless v+ otherwise specified. M GRADE DEVICE SYMBOL PARAMETER Supply Voltage Ranges Positive Supply Logic Supply Negative Supply V+ VL V- TEST CONDITIONS Switch "ON" Vo = ±5V Resistance (Note 4) IS = lOrnA, VIN Vo-±10V ROS(on) Switch "ON" Resistance On Resistance Match Between Channels dROS(on) -SS·C + 25·C + 12S·C IIC GRADE DEVICE -251 O·C +2S·C +851 , +70·C 4.5> 16 .4.5> V+ -4> -16 (Note 3) ROS(on) TYP V 75 ~ 75 100 75 75 100 2.4V V+ =VL= +5V, VIN = 3V V- = -5V, Vo = ±3V 15= lOrnA IS = lOrnA, Vo = ±5V 125 125 175 150 150 175 250 250 350 300 300 350 VIL 10(011) or 15(011) Switch "OFF" Leakage (Notes 2 and 4) VS/O - ±5V VIN" O.BV VS/O = ±14V ±0.5 50 ±1.0 100 ±0.5 50 ±1.0 100 10(on) + IS(on) Switch "ON" Leakage VS/O =±5V VIN ~ 2.4V VS/O = ±14V ±1 50 ±2 100 liN Input Logic Current VIN 1+ Positive Supply Quiescent Current 1IL NOTES: 1. 2. 3. 4. > 2.4 V < O.B ±1 100 ±2 100 0.1 .±1 ±1 10 ±1 ±1 10 VIN=OVOr +5V 0.1 1 1 10 1 1 10 Negative Supply Quiescent Current VIN =OV or +5V 0.1 1 1 10 1 1 10 Logic Supply Quiescent Current VIN -OV pr +5V 0.1 1 1 10 1 1 10 ~ 2.4V or < OV AC ELECTRICAL CHARACTERISTICS = + 15V, VL = + 5V, v- = OV, TA = 25°C unless SYMBOL p.A otherwise specified (Note 5). PARAMETER TEST CONDmONS MIN TYP MAX UNIT 150 BO 300 150 ns Ion Switch "ON" Time See Figure 4 toll OIRR Switch "OFF" Time "OFF" Isolation Rejection Ratio See Figure 4 See Figure 5 (Note 6) CCRR Cross Coupling Rejection 'Ratio See Figure 6 (Note 6) 60 Switch Attenuation 3dB Frequency See Figure 7 (Note 6) 100 f3dB nA Typical values are not tested in production. They are given as a design aid only.. Positive and negative voltages applied to opposite sides of switch, in both directions successively. These are the operating voltages at which the other parameters are tested, and are not directly tested. The logic inputs are either greater than or equal to 2.4V or less than or equal to O.BV, as required, for this test. V+ NOTES: n 5 Logical "I" Input Voltage Logical "0" Input Voltage VIH UNIT 5. All AC parameters are sample tested only. 6. Test circuit should be built on copper clad ground plane board, with correctly terminated coax leads, etc. 3-140 Note: All typical values have been guaranteed by characterizaiion and, are not tested. 60 dB iCII IH5341 ~ TEST CIRCUITS Tn INPUT +3V ov -""7'50%------'"""" .+1W-T---~~=-----~ YouT 10% VANALOG + SY +:: YouT ov ov----... =rI...!TL IN -+--''F't 10" YOUT RL = VANALOG 1Il00 =- SV __ 1W _____ ~~IO%~~___~ WFOO33(J1 TCOO791 I Note: Only one channel shown. Other acts identically. Figure 4: Switching Time Test Circuit and Waveforms TC008101 TGOOSOOI VIN = ±5V (10Vp_p) @ f = 10MHz VIN VIN OIRR = 20log - - Your = 225mVrms @ f = 10MHz VIN CCRR = 20109 - - vour Note: Only one channel shown. Other acts identically. Figure 5: OFF Isolation Test Circuit Figure 6: Cross-Coupling Rejection Test Circuit RL ATTN: =20 10910---"-ROS(on)+RL Nominally, at DC, this ratio is equal to -4dB. When the attenuatio reaches -1 dB, the frequency at which this occurs is f3dB. TCOO8201 Note: Only one channel shown. Other acts identically. Figure 7: Switch Attenuation Versus Frequency, Test Circuit 3-141 Note: All typical values have been guaranteed by characterization and are not tested. i·IH5341 I TYPICAL PERFORMANCES CHARACTERISTICS ROS(on) Versus Analog Input Level with ±SV POl/ier Supplies Ros(onl Versus Analog Input Voltage w th ± 1SV Power .Supplies 70 PIN 3= +ISIf, PIN 7= -15V PIN.l0= +SV . TA=25·C .: 60 7 'I g i 50 i 40 V V" " PIN 3=PIN 10= +5V PIN 7= -SV fo-160 TA=2S·C ~ ~120 V 80 if S 70 II: II: 80 6 / 50 , 90 80 30 0.1 0 +S ANALOG INPUT VOLTAGE LEVEL (V) 1 10 100 FREQUENCY (MHz) QP006701 CPOO6601 100 '\ 40 80 -s ·c TA= +25 90 / OPOOB801 Typical Switch Attenuation Versus Frequency (RL = 7S0, See Figure 7) CCRR (Cross Coupling Rejection) Versus Frequency (See Figure 6) -3.3 TA=ZSOC T,,-.+2S·C m-3.4 S " -3.5 .2 if 70 S II: II: .; 100 30 -15 -10 -5 0 5 10 15 ANALOG INPUT VOLTAGE LEVEL (V) u u 100 j g140 OIRR (OFF Isolation Rejection) Versus Frequency (See Figure 5) ~ -3.8 S " ~3.7 ' - - 50 ~ -3.8 40 UI ~ 60 :c ~- ~ • -3.9 -4.0 0.1 30 0.1 1 10 100 l}111111 1 10 OPO07801 0P006901 750 ~0--0 DRAIN SWITCH L_ _ _ J (OUT) I +15V SOURCE 0-----<)"'"'1/ ( SWITCH. (IN) CONTROL ~_ r-'\...~o­ IN~ DRIVER TRANSLATOR 100 FREQUENCY (MHz) FREQUENCY (MHz) --'11\'-.....- - . , Vour r------':r; ANALOG ~ INPUT LOOO2201 Figure 8: Internal Switch Configuration DETAILED DESCRIPTION As can be seen in Figure 8, the switch Circuitry is of the so-called "T" configuration, where a shunt switch is closed when the switch is open. This provides much better isolation between the input and the output than single series switch does, especially at high frequencies. The result is excellent performance in the Video and RF region compared to conventional Analog Switches. The input level shifting circuit is similar to that of the IH5140 Series of Analog Switches, giving very high speed and guaranteed "Break-belore-Make" action, with negligible static power consumption and TTL compatibility. 1000pFT CHOLD r--1-+ 3V ...J L-ov TTL. IN ISTROBE) TCO08301 • Adiust pot for OmYpop step @ YOUT with no analog (AC) signal· present Figure 9: Charge Injection Compensation 3-142 Note: All typical values have been guaranteed by characterization and are not tested. .U~OI1. en i IH5341 ! DETAILED DESCRIPTION (CONT.) +5V YoUT DC81AS VOLTAGE --sv o-.J\I..,.,....., ANALOG '--.l INPUT~ ...-......-=f:ll I.F 22I>i'-3SpF CHOto T.... 1000pF + 3V OV :rL TTL CONT~LII'I TC008401 Figure 10: Alternative Compensation Circuit APPLICATIONS Charge Compensation Techniques +,15V-IW-_----. Charge injection results from the signals out of the level translation circuit being coupled through the gate-channel and gate-source/drain capacitances to the switch inputs and outputs. This feedthrough is particularly troublesome in Sample-and-Hold or Track-and-Hold applications, as it causes a Sample (Track) to Hold offset. The IH5341 devices have a typical injected charge of 30pC-50pC (corresponding to 30mV-50mV in a 1000pF capacitor),at VS/O of about OV. This 'Sample (Track) to Hold offset can be compensated by bringing in a signal equal in magnitude but of the opposite polarity. The circuit of Figure 9 accomplishes this charge injection compensation by using one side of the device as a S & H (T & H) switch, and the other side as a generator of a compensating signal. The 1kn potentiometer allows the user to adjust the net injected charge to exactly zero for any analog voltage in the -5V to +5V range. Since individual parts are very consistent in their charge injection, it is possible to replace the potentiometer with a pair of fixed resistors, and achieve less than 5mV error for all devices without adjustment. An alternative arrangement, using a standard TTL inverter to generate the required inversion, is shown in Figure 10. The capacitor needs to be increased, and becomes the only method of adjustment. A fixed value of 22pF is good for analog values referred to ground, while 35pF is optimum for AC coupled signals referred to -5V as shown in the figure. The choice of - 5V is based on the virtual disappearance at this analog level of the transient component of switching charge injection. This combination will lead to a virtually "glitch-free" switch. TCOO8501 Figure 11: Overvoltage Protection Circuit Overvoltage Spike, Protection If sustained operation with no supplies but with analog signals applied is pOSSible, it is recommended that diodes (such as 1N914) be inserted in series with the supply lines to the IH5341. Such conditions can occur if these Signals come from a separate power supply or another location, for example. The diodes will be reverse biased under this type of operation, preventing heavy currents from flowing from the analog source through the IH5341. The same method of protection will provide over ±25V overvoltage protection on the analog inputs when the supplies are present. The schematic for this connection is shown in Figure 11. 3-143 Note: All typical values have been guaranteed by characterization and are not tested. :: .HS35l:·' i QUAD SPST CMOS - RFIVideo Switch ·GENERAL DESCRIPTION ~~ FEATURES cM'os The IH5352 is a QUAD SPST, monolithic vide9 'switch which uses a "Series/Shunt" ("T" switch) configuration to obtain high "OFF" isolation while maintaining good frequency response in the "ON" condition. Construction of remote and portable video equipment with extended battery life is facilitated by the extremely iow current requirements. Switching speeds are typically ton = 150ns and toft = 80ns, and "Break-Before-Make" switching is guaranteed. Switch "ON" resistance is typically 40n-50n with ±15V power supplies, increasing to typically 175n for ±5V supplies. IH5352CPE IH53521JE IH5352MJE TEMPERATURE RANGE Q'C to +70'C ROS(on) • Switch Attenuation Varies Less Than 3dB From DC to 100MHz "OFF" Isolation> SOdB @ 10MHz Cross Coupling I,solation > SOdB @ 10MHz Directly Compatible with TTL, CMOS Logic Wide Operating Power Supply Range Power Supply Current < 1~ "Break-Before-Make" Switching Fast SWitching (80ns/150ns Typ) • • • • • • • APPLICATIONS • • • • • ORDERING INFORMATION PART NUMBER < 7Sn • PACKAGE Video Switch Communications Equipment Disk Drives Instrumentation CATV l6-PIN PLASTIC DIP -25'C to +85°C l6-PIN CERDIP -55'C to + l25'C l6-PIN CERDIP IH5352 s., 0 a"'(o~-----J CD030701 lSOO780l, Figure 1: Functional Diagram (Switches are open for a, logic ",0" control Input, and closed for a logic "1" control input.) Figure 2: Pin C.onfigurations Package Outline Drawing: PE, JE 3-144 Note: All typical values have been guaranteed by characterization amI' are not tested. 305529-003 IH5352 ABSOLUTE MAXIMUM RATINGS (TA = 25'C Unless Otherwise Noted)' y+ to Ground ................................................ + 17Y Y- to Ground ................................................ -17V YL to Ground .......................................... V+ to YLogic Control Yoltage ................................ V+ to VAnalog Input Yoltage ................................. Y + to YCurrent (any terminal) ................................... < SOmA Operating Temperature: (M Version) ......•.................. -55'C to + 125'C (I Version) ............................. -20·C to +85'C (C Version) .............................. O'C to + 70'C Storage Temperature ...................... -65'C to + 160'C Lead Temperature (Soldering, 10sec) ..................................300·C Power Dissipation: CERDIP ............................................ .450mW derate 4mWrC above 25'C Plastic ............................................... 350mW derate 3mWrC above 25°C Stresses above those listed under" Absolute Maximum Ratings" may cause permanent. damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational Sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS y+ = + l5V, Y- = -15Y, YL = +5Y, TA = 25'C unless otherwise noted. MAXIMUM RATINGS SYMBOL PARAMETER TEST CONDITIONS TYP @2S'C M GRADE DEVICE IIC GRADE DEVICE -SS'C +2S'C + l2S'C -2S/0'C . + 25'C V+ Supply Voltage Ranges: Positive Supply VL Logic Supply V- Negetive Supply Sw~ch ROS(on) "ON" Resistance (Note 4) ROS(on) Switch "ON" Resistance AROS(on) On Resistance Match Between Channels VIH Logical "1" Input Voltage VIL 10(off) or 15(011) 10(on) + IS(on) Logical "0" Input VoIlI!ge Switch 'OFF' Leakage (Note 2 and 4) Sw~ch 'ON' Leakage UNIT +851 +70'C 5 to 15 (NoteS) 5 to 15 V -5 to .-15 Is-lOrnA IVo - ±5V 50 75 75 VIN2.4 V <0.6 VS/0-±5V VS/O" ±14V VIN $0.8V ±1.0 50 ±2.0 ±1.0 50 ±2.0 100 VS/0-±5V VS/O - ±14V VIN --~~<:r L__ _ MDEO I.pun DETAILED. DESCRIPTION Figure 3 shows the internal circuit of one channel of the IH5352. This is identical to the IH5341 "T-Switch" configuration. Here, a shunt switch is closed, and the two series switches are open when the video switch channel is open or off. This provides much better isolation between the input and output terminals than a simple series switch does, especially at high frequencies. The result is excellent offisolation in the Video and RF frequency ranges when compared to conventional analog switches. SWITCH O--ODRAlI (VIDEO OUTPun I LOGIC o - - - [ ) 4 - ; > o l COmOL .' - I.PUT .' DIUVER TRA.SLATOR TC032601 The control input level shifting Circuitry is very similar to 'that of the IH5140 series of Analog Switches, and gives very high speed, guaranteed "Break-BefOre-Make" action, low static power consumption and TTL 'compatibility. NOTE: 1 CHANNEL OF 4 SHOWN Figure 3: Internal Switch Configuration 1000 1000 TIL INPUT +3V OV +3.3V 1000 VOUT VANALOG = +5V riv OV 1000 Your VAl!IALOG= --SV -3.3V WF027401 ~S"L LOGIC CONTROL SIGNAl. TC037301 Figure 4: Switching Time Test Circuit and Waveforms 3-146 Note: All typical values heve been guaranteed by characterization and are not tested, 5! CI IH5352 W CI N 750 RG·59 COAX 750 TC037411 VIN OIRR = 20 LOG - VOUT VIN = 5V pn SINEWAVE @ 10MHz Figure 5: Off Isolation Test Circuit IH5352 +5V 2 15 3 14 4 13 +15V VOUT1 750 VOUT2 750 5 -= 750 16 6 750 7 8 -= -= Too37501 CCRR = 20 LOG ~ VOUT VIN = 225mV RMS SINEWAVE @ 10MHz Figure 6: Cross-Coupling Rejection Test Circuit 3-147 Note: All typical values have been guaranteed by characterizatiOn and are not tested. ! .O~OIl IH5352 '10 -z 750 IH53S2 +5V RQ.68COAX NC NC RG·59 COAX . 18 VOUT 2 15 3 14 4 13 5 12 8 11 +15V 750 750 750 ":" -15V 7 NC 8 +5V ":" '::" TC037601 f - 3dB ~ FREQUENCY WHERE DC SWITCH ATTENUATION IS DOWN 3dB VIN = 225mV RMS@ 10-100MHz Figure 7: Switch Attenuation -3dS Frequency Test Circuit 3-148 Note: All typical values have been guaranteed by characterization and are not lested. IH6108 S-Channel CMOS Analog Multiplexer GENERAL DESCRIPTION FEATURES The IH6108 is a CMOS monolithic, one of 8 multiplexer. The part is a plug-in replacement for the DG508. Three line decoding is used so that the 8 channels can be controlled by 3 Address inputs; additionally a fourth input is provided for use as a system enable. When the ENable input is high (5V), a channel is selected by the three Address inputs, and when low (OV) all channels are off. The 3 Address inputs are TTL and CMOS logic compatible, with a "1" corresponding to any voltage greater than 2.4V. • • • • • • • • • Ultra Low Leakage - IO(Off):::: 100pA rOS(on) < 400 Ohms Over Full Signal and Temperature Range Power Supply Quiescent Current Less Than 100jJA ±14V Analog Signal Range No SCR Latchup Break-Before-Make Switching Binary Address Control (3 Address Inputs Control 8 Channels) TTL and CMOS Compatible Strobe Control Pin Compatible With DG508, HI-508 & AD7508 ORDERING INFORMATION PART NUMBER TEMPERATURE RANGE PACKAGE IH6108MJE -SS·C to + 12S·C 16 pin CERDIP IH6108CJE O·C to 70·C 16 pin CERDIP IH6108CPE O·C to 70·C 16 pin plastic DIP Ceramic package available as special order only (IH6108MDE/CDE) DECODE TRUTH TABLE S. 0 CV""""" S. 0 CV""""" 0 CV""""" VOUT D A1 x 0 0 1 1 0 1 1 1 1 1 0 1 Ao x 0 1 0 1 0 1 0 1 EN 0 1 1 1 1 1 1 ON SWITCH NONE 1 2 3 4 S 6 7 8 1 1 AO, A1, A2 EN SWITCH S. ~ A2 x 0 0 0 0 Logic "1" = VAH::: 2.4V VENH::: 4.SV Logic "0" = VAL:::: 0.8V Sa S. ~ S. ~ AD A. A. EN (ENABLE INPUT) c0003411 3 LINE BINARY ADDRESS INPUTS (1 0 1) AND EN @ SV ABOVE EXAMPLE SHOWS CHANNEL 6 TURNED ON' Figure 2: Pin Configuration LDD0231 I Figure 1: Functional Diagram 3-149 Note: All typical values have been guaranteed by characterization and are not tested. 305530-002 IIU~UIl IH61("~ ABSOLUTE MAXIMUM RATINGS VIN (A, EN) to Ground .......................... -15V to 15V Vs or Vo to V+ ......................................... 0, -32V Vs or Vo to V- ..........•................................ 0, 32V V+ to Ground ................................................. 16V V- to Ground ....... ~ . .'...................................... -16V Current (Any Terminal) .................................. ~. 30mA Current (Analog Source or Drain) ...................... 20mA Operating Temperature ......................... -55 to 125°C Storage Temperature .......................... ;·. -65 to 150°C Lead Temp (SOldering, 10sec) .......................... 300°C Power Dissipation (Package)· ....................... 1200mW 'All leads soldered or welded to PC board. Derate 10mW/'C above 70'C. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and lunctional operation 01 the device at these or any other conditions above those indicated in the operational sections 01 the specilications is not implied. Exposure to absolute maximum rating conditions lor extended peri()(js may allect device reliability. ELECTRICAL CHARACTERISTICS V+ = 15V, V - :, ...: 15V, VEN = + 5'1 MEASURED TERMINAL CHARACTERISTIC (Note 1), Ground = OV, unless otherwise specified. MAX LIMITS NO TES!5 TYP PER 25'C TEMP TEST CONDITIONS M SUFFIX C SUFFIX UNIT -SS'C 2S'C 12S'C O'C 2S'C 70'C SWITCH S to D rOS(ON) 8 180 Vo = 10V, Is = -1.0mA Sequence each switch on 8 150 Vo=-10V,IS=-1.0riJA VAL "rOS(on) = 20 arOS(ON) t.rOS(on)min rOS(on)avg. VAH = 2.4V 300 300 400 350 350 450 300 300 400 350 350 450 0.002 Vs = 10V, Vo = -10V ±.5 50 ±1 8 0.002 Vs = -10V, Vo -10V ±:5 50 ±1 50 1 0.03 ±2 100 ±5 100 1 0.03 Vo = -10V, Vs = 10V ±2 100 ±5 100 8 0.1 VS(ALL) - Vo - 10V Sequence each switch on ±2 100 ±5 100 8 0.1 VSIALLl = Vo = -10V VAL = 0.8V, VAH = 2.4V ±2 100 ±5 100 AI or A2 3 0.01 VA - 2.4V or OV -10 -30 -10 -30 Inputs 3 0.01 VA=15V or OV 10 30 10 30 -10 -30 -10 -30 -10 -30 -10 -30 10(OFF) D 1010N) . D Vo = 10V, Vs = -10V VEN =0.8V .11 % Vs = ± 10V 8 S IS(OFF) = 0.8V, 50 nA INPUT Ao, IAN(ON) or IA(on) IAN(OFF) IA(off) Ao, IA p.A AI A2 3 VEN = 5V EN 1 VEN=O All VA = 0 (Address pins) DYNAMIC ttransition D 0.3 See Fig. 1 Iopen D 0.2 See Fig. 2 Ion(EN) D 0.6 See Fig. 3 Ioff(EN) "OFF" Isolation 0 0.4 D 60 VEN = 0, RL = 200.11, CL = 3pF, Vs = 3VRMS, f = 500kHz S 5 Vs=O Cd(off) D 25 Vo=O D to S 1 Supply + v+ 1 40 Current - V- I 2 Standby + V+ 1 1 Current - V- I 1 1.5 p.s 1 Cs(oll) COSloff) SUPPLY 1 dB VEN = OV, I = 140kHz to lMHz pF Vs=O, Vo= 0 VEN = 5V All VA=O or 5V VEN=O NOTE 1: See Enable Input Strobing Levels, in Application Section. 3-150 Note: All typical values have been guaranteed by characterization and are not tested. 200 1000 100 1000 100 1000 100 1000 p.A IM6108 SWITCHING INFORMATION VA tr < l00ne •• < l00nl 3V O.aV----jt---5O'Io---\'-ltrans(8-1) - - -.... +10V Your VSl = +10Y Vs. = -10V ttrans(l-B) i-,..=;.;-9!lV!....._¥ -10V t--S8 ON...-j t--510N---l 1--580N-- l--J.~=T+i9itv;--11+10V trans (1-8) Your' Vs, = -10V Vsa = +10V _ _ _...I-l0V ttrans(8-1) TGOOSeOI WFOO3401 PROBE IMPEOANCE Rp ~ 1Mil Cp $ 30pF Figure 3: ttransltlon Switching Test 3V +15V r--~W!,-",,~--o-2V L-~ VA ____~__J=~=i::~:r~VOUT ~~'00n. ~ If < 100n, O.8V o; ;.a~V \ " '_ _ _ _ Your vs, = -2V 51 ON 35pF TC008701 WF003501 Figure 4: t open (Break-Before-Make) Swltchi!1g Test 3-151 Note: All typical values have been guaranteed by characterization and are not tested. ,,,< YEN 100... If < 100... '+1sv r----.-.j,o.",;l-~~--_o VSI IH6108 L.,....___r-<>-'-r-=-T~Your, O.IV Your OV 35pF VEN rCOO88Ot WFOO3601 Figure 5: ton and toff Switching Test IH6108 APPLICATION INFORMATION ENable Input Strobing Levels The ENable input on the IHp10S requires a minimum of + 4:5V to trigger to the" 1" state and a maximum of + O.SV ~o trigger to the "0" state. If the ENable input is being driven from TTL logic, a pull-up resistor of 1k to 3kn is required from the gate output to + 5V supply. (See Figure 6) +5V lKn DM7404N TTL LOG,IC +3V 11 .2l!I"1... VOUT AFo05101 Figure 6: ENable Input Strobing from TTL Logic When the EN input is driven. from CMOS logic, nopullup is necessary, see ,Fig. 7. 3-;.152 Note: All typical values have been guaranteed by characterization and are not tested. IH6108 IH6108 APPLICATION INFORMATION (CONT.) +5V AFOO520t Figure 7: ENable Input Driven from CMOS Logic supply voltages decrease, however, the multiplexer error term (the product of leakage times rOS(on» will remain approximately constant since leakage decreases as the supply voltages are reduced. The supply voltage of the CD4009 affects the switching speed of the IH6108; the same is true for TTL supply voltage levels. The following chart shows the effect, on ttrans for a supply varying from +4.5V to +5.5V. CMOS OR TTL SUPPLY VOLTAGE +4.5V +4.75V +5.00V +5.25V +5.50V Caution must be taken to ensure that the enable (EN) voltage is at least 0.7V below V + at all times. If this is not done, the Address input strobing levels will not function properly. This may be achieved quite simply by connecting EN (pin 2) to V + (pin 13) via a silicon diode as shown in Figure 8. When using this type of configuration, a further requirement must be met: the strobe levels of AO and A 1 must be within 2.5V of the EN voltage in order to define a binary "1" state. For the case shown in Figure 8 the EN voltage is 11.3V which. means that logic high at AO and A 1 is = +8.8V(logic low continues to be = 0.8V). In this configuration the IH6108 cannot be driven by TTL (+ 5V) or CMOS (+ 5V) logic. It can be driven by TTL open collector logic or CMOS logic with + 12V supplies. TYPICAL ttrans @ 25°C 400ns 300ns 250ns 200ns 175ns The throughput rate can therefore be maximized by using a + 5V to + 5.5V supply for the ENable Strobe Logic. The examples shown in Figures 6 and 7 deal with ENable strobing when expansion to more than eight channels is required. In these cases the EN terminal acts as a fourth address input. If eight channels or less are being multiplexed, the EN terminal can be directly connected to + 5V logic supply to enable the IH6108 at all times. If the logic and the IH6108 have common supplies, the EN pin should again be connected to the supply through a silicon diode. In this case, tying EN to the logic supply directly will not work since it violates the 0.7V differential voltage required between V + and EN, (See Figure 9). A 11lF capaCitor can be placed across the diode to minimize switching glitches. Using the IH6108 with supplies other than ±15V The IH6108 can be used with power supplies ranging from ±6V to ±16V. The switch rOS(on) will increase as the 3,-153 Note: All typical values have been guaranteed by characterization and are not tested. I.... IH610S I - IH&108 APPLICATION INFORMATION (CONT.) AFOO5301 Figure 8: IH6108 Connection Diagram for less than ± 15V Supply Operation 1N914 OR ANY SILICON DIODE CDOO3901 Figure 9: IH6108 C~nnection Diagram with ENable Input Strobing for less than ±15V Supply Operation Peak-to-PeakSignal Handling Capability The electrical specifications of the IH6.108 are guaranteed for ±1OV signals, but the specifications have very minor changes for ±14V signals. The notable changes are slightly lower rOS(on) and slightly higher leakages. The IH6108 can handle input signals up to ± 14V (actually -15V to + 14.3V because of the input protection diode) when using ± 15V .supplies. :r-154 Note: All typical values have been guaranteed by characterization and are not tested. IH6116 16-Channel CMOS Analog Multiplexer 'GENERAL DESCRIPTION FEATURES The IH6116 is a CMOS monolithic, one of 16 multiplexer, The part is a plug-in replacement for the DG506. Four line binary decoding is used so that the 16 channels can be controlled by 4 Address inputs; additionally a fifth input is provided to be used as.a system enable. When the ENable input is high (5V) the channels are sequenced by the 4 line Address inputs, and when low (OV), all channels are off. The 4 Address inputs are controlled by TTL logic or CMOS logic elements with a "0" corresponding to any voltage less than 0.8V and a "1" corresponding to any voltage greater than 2.4V. Note that the ENable input must be taken to 5V to enable the system and less than 0.8V to disable the system. • • • • • • • • • • Pin Compatible With DG506, HI-506 & AD7506 Ultra Low Leakage - 10(Off)::: 100pA ± 11 Analog Signal Range rOS(on) < 700 Ohms Over Full Signal and Temperature Range . Break-Before-lIIIake' Switching TTL and CMOS Compatible Address Control Binary Address Control (4 Address' ,,,,puts Control 16 Channels) Two Tier Submultiplexlng to Facilitate . Expaildability Power Supply Quiescent Current Less Than 1001lA No SCR Latchup ORDERING INFORMATION PART NUMBER IH6116MJI IH6116CJI IH6116CPI TEMPERATURE RANGE -55·C to + 125·C O·C to 70·C O·C to 70·C PACKAGE 28 pin CERDIP 28 pin CERDIP 28 pin Plastic DIP IH6116MDIICDI DECODE TRUTH TABLE EN ON SWITCH A1 Ao X X 0 NONE 1 1 0 0 0 0 1 1 2 0 0 1 0 1 3 0 1 1 1 4 0 0 0 0 1 5 0 1 1 1 0 1 0 6 0 1 0 1 7 1 0 1 1 1 1 8 1 0 0 9 1 0 0 1 1 10 1 0 1 1 0 1 11 0 1 1 1 12 1 0 0 1 13 1 1 0 1 1 1 1 0 14 1 1 1 0 1 15 1 1 1 1 1 16 LogiC "1" = VAH ~ 2.4V VENH ~ 4.5V Logic "0" = '(Al ::: O.SV . A3 X 0 .. h~=LI·· L~~~:fL~. 811~ .12~ . ~ ~. , 'VOU"OI . .,.~ 81$~ SI.~· A2 X 0 y+ He a TO DECODE LOGIC ' CONTROLUNG BOTH TIER,"OF MUXING' ~ ., H" " .. . . .. DeVOUl) 27 N.C 3 V- ... .."...,. .. " , "OS .. 1181 810 " ,. EN SO" , .... GNO 12 .. A, """ 1542 TOPYIEW 4 LINE BINARY ADDRESS INPUTS 0 0 1)ANDENQ.t5V ABOVE EXAMPLE SHOWS CHANNEL' TURNED ON yTCOMMON TO SUBSTRATE (0 C0OO3501 Figure 2: Pin Configuration LOOO2401 Figure 1: Functional Diagram 3-155 Note: All typical values have been guaranteed by characterization and are not t YOUT -15V +15V D2 82 TTL OR -: CMOS 1H6116 INVERTER -: EN V2 -15V VA S32 S" "" -TTL .... 'mu•• ha.,e pullup mlstor 10 + 5V to drive EN Inputs AFOO5601 DECODE TRUTH TABLE A4 A3 A2 A1 Ao 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 DECODE TRUTH TABLE ON SWITCH 81 82 83 54 85 86 87 88 89 810 811 812 813 814. 815 816 A4 A3 A2 A1 Ao ON SWITCH 1 1 1 1 1 1 1 1 1 1 1 1· 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 '1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 Figure 7: 1 Out of 32 Channel Multiplexer U~ing 2 IH6116s; Using 3-159 Note: All typical values have been guaranteed by characterization and are not tested. 0 0 0 0 1 1 1 1 An IH5041 for Submultiplexing C) i IH6116 IH6116 APPLICATIONS (CONT.) V, ~15V i J Ao A, A2 - IHl111 lOUT OF " A3 I I .... , 1 l I '~7 i I" n 41 1,1 1 1 I ~LJoIIIII~Jsl I I I Do ~ ~ 03 I I 11113 ~~ . I IH111. 1 OUT OF " MUX EIilABLE I IH5053 ~ <'2 A3 1 I I 331 I I 1 I ~~LJo IIN~U~sl I I I 1·1 ~ mUI' have ,..I.tor to ctrive EN InpPoIti ....'r..TLuplat. f--O-t>-l J., IH111. 1 OUT OF " MUX A3 j!NA8LE 1 ~ ~lLOGIIIIILU~11 Ao A, A2 I 1 .J IHe11e 1 OUT OF " MUX 111 I I I I 0, I 1111, ....!!! A3 INA... ... S.!-,.I I 11 I I I I JJL~IIN~U~I I I I 1" Ao A, A2 I ~ MUX INAILE I 1M ~" D. JV2 -l$V AFOO5701 Figure 8: 1 Out of 64 Multiplexer Using 4 1/16s and IH5053 As Submultiplexer ~eneral note on expandabillty of IH6116 The IH6116 is a two tier multiplexer, where sixteen input channels are routed to a common output in blocks of 4. Each block of 4 input channels is routed to one common output channel, and thus the submultiplexed system looks like 4 blocks of 4 inputs routed to 4 different outputs with the 4 outputs tied together; Thus 20 switches are needed to handle the 16 channels of information. The advantage of this is lower output capacitance and leakage than would be possible with a system using all 16 channels tied to one common output. Also the expandability into 32, 64, 128, channels etc. is facilitated. Figures 6,7, and 8 show how the IH6116 can be expanded. Figure 6 shows a 1 of 32 multiplexer, using 2 IH6116s. Since the 6116 is itself a 2 tier MUX, the system as shown is basically a 2 tier system. The four output channels of each 6116 are tied together so that 8 channels are tied to the VOUT common pOint. Since only one channel of information is on at a time, the common output will consist of 7 OFF channels and 1 ON channel. Thus the output leakage will correspond to 7 10(ofts) and 1 10(on), or about 1.0nA of typical leakage at room temperature. Throughput speed will be typically 0.81lS for. ton andO.3~s for toft. Throughput channel resistance will be in the 500n area. Figure 7 shows the 1 of 32 MUX of Figure 6, with a third tier of submultiplexing added to further reduce leakage and output capacitance. The IH5041 has typical ON resistances of 50n (max. is 75n) so it only increases thruput channel resistance from the 500 ohms of Figure 6 to about 550 ohms for Figure 7. Throughput channel speed is a little slower by about 0.5~s for both ON and OFF time, and output leakage is about 0.2nA. 3-t60 Note: All typical values have been guaranteed by characterization. and are not test~. .O~OlL IH6116 Figure B shows a 1 of 64 MUXusing 3 tier MUXing (similar to Figure 7). The Intersil IH5053 is used to get the third tier of MUXing. The VOUT point will see 3 OFF channels and 1 ON channel at anyone time, so that the typical leakages will be about 0.4 nA. Throughput channel resistance will be in the 550 ohm area with throughput switching speeds about 1.3J.1s for ON time and O.BJ.IS for OFF time. The IH5053 was chosen as the third tier of the MUX because it will switch the same AC signals as the IH6116 (typically plus and minus 15V) and uses break before make switching. Also power supply quiescent currents are on the order of 1-2/lA, so that no excessive system power is dissipated. Note that the logic of the 5053 is such that it can be tied directly to the ENable input (as shown in the figures) with no extra circuitry being required. the low state. When using TTL logic, a pull-up resistor of 1kn or less should be used to pull the output voltage up to 5V. When using CMOS logic, the high state goes to the power supply so no pull-up is required. If used on high voltage logic supplies, EN should be at least 0.7V below V + at all times. See IH610B data sheet for details. APPLICATION NOTES Further information may be found in: AOO3 "Understanding and Applying the Analog Switch," by Dave Fullagar A006 "A New CMOS Analog Gate Technology," by Dave Fullagar A020 "A Cookbook Approach to High Speed Data Acquisition and Microprocessor Interfacing," by Ed Slieger ROOe "Reduce CMOS Multiplexer Troubles Through Proper Device Selection," by Dick Wilenken Enable input strobing levels The enable input (EN) acts as an enabling or disablihg pin for the IH6116 when used as a 16 channel MUX. However, when expanding the MUX to more than 16 channels, the EN pin acts as another address input. Figures 6 and 7 show the EN pin used as the A4 input. For the system to function properly the EN input (pin 1B) must go to 5V ±5"1o for the high state and less than O.BV for NOTE: This multiplexer does not require external resistors and/or diode.s to eliminate what is commonly known as a latch up or SCR action. Because of this fact, the rOS(ON) of the switch is maintained at specified values. 3-161 Note: All typical values have been guaranteed by characterization and are not tested. i... a g 1'146201 ! Dual CMOS Driver Iyoltag~ .Translator GENERAL DESCRIPTlON FEATURES The IH6201 is a CMOS; Monolithic, Dual Voltage Trarislator; it takes low level TTL or CMOS logic signals and converts them to higher levels (i.e. to ±15V swings). This translator is typically used in making solid stilte switches, or analog gates. Wheli used in conjunction with the IntersillH401 family· of Varafets, the combination makes a complete solid state switch capable of switching signals up to 22Vpp and up to 20MHz in frequency. This switch is a "break·before,make" type (i.e. loft time < Ion time). Tile combination has typical loft "" 80ns and typo ton"" 20()ns fqr signals. up to 20Vpp in amplitude. A TTL "1" input strobe will force. the (J driver output up to V+ level; the lJ output will be driven down .to the V- level. When the TTL input goes to "0", the (J output goes to Valid 'lJ goes to V +; thus (J and lJ are 18Qo out of phase with each other. These complementary outputs can be used to create a wide variety of functions such asSPDT and DPDT switches, etc.; alternatively the complementary outputs can be used to drive Nand P channel MOSFETs, to make a complete CMOS analog gate. The driver typically uses + 5V and ± 15V power supplies, however a wide range of V + and V- is also possible. It is necessary that V + > 5V for the driver to wprk properly, however. • • • -5V DRIVER OUTPUT J---., '---_ii, Driven Direct From TTL or CMOS logic Translates _Logic Levels Up to 30V Levels Switches 20VACPP Signals When Used in Conjunction With Intersil IH401A Varafet (As An ,Analog Gate) • tON::S 300ns & tOFF::S 200ns for ~OV Level Shifts • Quiescent Supply Current::s 1001lA for Any State (D.C.) • Provides Both Normal & Inverted Outputs ORDERING INFORMATION PART NUMBER TEMPERATURE RANGE *IHe201CDE ooe to 70 0 e "IH6201MDE -55°e _ + 125"e IH6201CJE ooe to 70 0 e IH6201MJE -55°e to t25°e IH6201ePE ooe to 70 0 e "SpeCial Order Only ., . " 80000201 Figure 1: Functional Diagram ,. DRIVER OUTPUT • LOGIC STROBE TTL INPUT 1 y- OND +5V 1 rll E:-...J v+ DRIVER OUTPUT • TTL INPUT 2 82 • COOOO601 (Outline dwgs DE,JE,PEl V- Figure 2: Pin Configuration 05003001 Figure 3: Schematic Diagram (One Channel) 3-162 Note: All typical values have been guaranteed by characterization and are not tested: IH6201 ABSOLUTE MAXIMUM RATINGS y+ y+ Yy+ to Y- ....................................................... ................................................................ ................................................................ to YIN ...................................................... 35Y 35Y 35Y 40Y Operating Temperature ............... ,... -55°C to +125°C Storage Temperature ...................... -65°C to + 150°C Lead Temperature (Soldering, 10sec) ....•............ 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions lor extended periods may affect device reliability. ELECTRICAL SPECIFICATIONS y+ = +15Y, v- = -15V, VL= +5V IH6201CDE ITEM 8 or 71 driver output swing IH6201MDE TEST CONDITIONS VIN = OV .I1.. -2S'C +2S'C -SS'C 28 +2S'C UNIT +12S'C 28 Vpp VIN strobe level ("1")lor proper translation 8~ 14V Ii~ -14V 3.0 3.0 3.0 2.4 VO.C. VIN strobe level ("'O")for proper translation 8 ~ -14V 11~ 14V 0.4 0.4 0.4 0.8 Vo.C. liN input strobe current draw (for OV - 5V range) VIN ±1 ±1 10 ton time VIN = OV .I1.. CL = 30pF switching turn-on time lig. 58 400 300 ns toff time VIN = OV .I1.. CL = 30pF switching turn-off time fig. 58 300 200 ns I + (V +) power supply quiescent current.· VIN=OVor +5V 100 100 100 100 100 100 IlA 1- (V -) power supply quiescent current VIN = OV or + 5V 100 100 100 100 100 100 p.A IL (vLl power supply quiescent current VIN=OVor +5V 100 100 100 100 100 100 p.A = OV + 3V Fig. 58 +8S'C or +5V ±1 ±1 10 IlA APPLICATIONS ral" resistor is normally in the 1OOkSl to 1Mil range and is not too critical. Input Drive Capability The strobe input lines are designed to be driven from TTL logic levels; this means O.BV to 2.4V levels max. and min. respectively. For those users who require O.BY to 2.0Y operation, a pull-up resistor is recommended from the TTL . output to + 5V line. This resistor is not critical and can be in the 1kil to 10kil range. , . . - - - - , SIGNAL INPUT +3V ~ When using 4000 series CMOS logic, the input strobe 'is connected direct to the 4000 series gate output and no pull up resistors, or any other interface, is necessary. REFERRAL RESISTOR TTL INPUT ---~ SWITCH OUTPUT RL When the input strobe voltage level goes below Gnd (i.e. to -15Y) the circuit is unaffected as long as y+ to YIN does not exceed absolute maximum rating. TC009201 Figure 4 Output Drive Capability The translator output is designed to drive the Intersil IH401 family of Yarafets; these .are N-channel JFETS with built-in driver diodes. Driver diodes are necessary to isolate the signal source from the driver!translator output; this prevents a forward bias condition between the signal input and the + Yee supply. The IH6201 will drive any JFET provided some sort of isolation is added i.e. Making a Complete Solid State Switch That Can Handle 20Vpp Signals The limitation on signal handling capability comes from the output gating device. When a JFET is used, the pinchoff of the JFET acting with the V- supply does the limiting. In fact max. signal handling capability = 2 (Vp + (V-n Vpp where Yp = pinch-off voltage of JFET chosen. Le. Vp = 7V, V- = -15Y :. max. signal handling = 2 (7Y + (-15Y)) Vpp = 2(7Y-15)pp = 2(-'BVpp) = 16Ypp. Obviously to get;:: 20Ypp, Vp ;:: 5V with Y- = -15Y. Another Simple way to get 20Vpp with Vp=7V, is to increase V- to -17V. In fact using V + = + 12V or + 15V andsatting V - = -1 BV You will notice in Figure 4 that a "referral" resistor has been added from 2N4391 gate to its source. This resistor is needed to compensate for the inadequate charge area curve for isolation diode (Le. if C vs. Y plot for diode ~ 2 [C vs. Y plot for output JFEn switch won't function; then adding this resistor overcomes this condition. The "refer3-163 Note: All typical values have been guaranteed by characterization and are not tested. i I lH8201· APPLICATIONS (CONT.) NOTE: Each translator output has a 8 and II output. 8 is just the inverse of lI. allows one to switch 20Vpp with any member of IH401 family. The advantage of using the Vp = 7V pinch-off (along with unsymmetrical supplies), over the VP"= 5V pinch-off (and ± 15Vsupplies), is that you will have· a much lower ROS(ON) for the Vp = 7 JFET (i.e. for the 2N4391). TOS(ON) ~ 22n, rOS(ON) "~ 35n) Vp '" 7V Vp = 5V A very useful feature of this system is that one-half of an IH6201 and one-half of an IH401 can combine to make a SPOT switch, or an IH6201 plus an IH401 can make a dual SPOT analog switch. (See Figure 8) The IH6201 is a dual translator, each containing 4 CMOS FETs pairs. The schematic of one-half IH6201, driving onequarter of an IH401, is shown in Figure 5A. ,----1 ,. . , ...... L- ';:~:1 INPUT STROlE I I I I I I I .,. DSOO3201 I S Figure 6: Dual SPST Analog Switch I L.!A-"-~E_J GNO , VL +1SV +5V --ov, -15V TRANSLATOR 08003101 Figure 5A 08003301 Figure 7: DPDT Analog Switch NOTE: Either swHch Is turned on when strobe input goes high. . 1 - - - ." - - - I +15V b-15V~ I I I I I I I I T15Y.Lr' -15V. 08000401 Figure 8: Dual SPDT W~I Figure5B 3-164 Note: All typical values have been guaranteed by characterization and" are not tested. IH6201 APPLICATIONS (CO NT.) 08003501 Figure 9: Dual DPST , 3-165 Note: All typical values have been guaranteed by characterization and are not tested. r;! 1"6208 zI 4-Channel Differential "- CMOS Analog Multiplexer GENERAL DESCRIPTION FEATURES ThtllH6208 is a monolithic 2 of 8 CMOS multiplexer. The part is a plug-in replacement for the DG509. Two line binary decoding is used so that the 8 channels can be controlled in pairs by the binary inputs; additionally a third input is provided to use as a system enable. When"the ENable input is high (5V) the channels are sequenced by the 2 line binary inputs, and when low (OV) all channels are off. The 2 Address inputs are controlled by TTL logic or CMOS logic elements with a "0" corresponding to any voltage less than 0.8V and a "1" corresponding to any voltage greater than 2.4V. Note that the ENable input must be taken to 5V to enable the system, and less than 0.8V to disable the system. • • • • • • • • • Ultra Low Leakage - 10(off) ~ 100pA rOS(on) < 400 Ohms Over Full Signal and Temperature Range Power Supply' Quiescent Current Less Than 100pA ±14V Analog Signal Range No SCR Latchup Break-Before-Make Switching Binary Address Control (2 Address Inputs Control 2 Out of 8 Channels) TTL and CMOS Compatible Address Control Pin Compatible With H1509, DG509 & AD7509 ORDERING INFORMATION PART NUMBER TEMPERATURE RANGE PACKAGE IH6208MJE -55°C to + 125°C 16 pin CERDIP IH6208CJE O°C to 70°C 16 pin CERDIP IH6208CPE O°C to 70°C 16 pin Plastic DIP Ceramic package available as special order only (lH6208MDE/CDE) DECODE TRUTH TABLE S1.o--~--.., Al Ao EN ON SWITCH PAIR X X 0 0 1 1 0 1 0 1 0 1 1 1 1 NONE 1a, 1b 2a,2b 3a,3b 4a,4b EN SWITCH I '--~)__.;-:..-0----.1.... D, I I Ao, .--~)__.;-I..-0----.1.... D, Al LOGIC" 1" = VAH ? 2.4V VENH ? 4.5V LOGIC "0" = VAL::; 0.8V S1bo--~---, EN GND v- v+ S1b S2b S4a Ae At EN COO03701 Figure 2: Pin Configuration" 2 LINE BINARY ADDRESS INPUTS (0 0) AND EN "I' SV (EN ...., .. fOR ... 5V. ''0'' FOR 0\11 ABOVE EXAMPLE SHOWS CHANNELS ,. I: 1b ON. LDOO250\ Figure 1: Functional Di~gram 3-166 .. Note: All typical values have been guaranteed by characterization and are not tested. IH6208 ABSOLUTE MAXIMUM RATI,NGS Current (Analog Source or Drain) ...................... 20mA Operating Temperature ......................... -55 to 125'C Storage Temperature ................... , ........ -65 to 150'C Lead Temp (Soldering. 10sec) ...... , ................... 300·C Power Dissipation (Package» ....................... 1200mW VIN (A. EN) to Ground ............................... -15V. V1 Vs or Vo to V+ ......................................... 0. -32V V~ or Vo to V- ............................................ 0. 32V V to Ground ................................................. 16V V- to Ground ................................................ -16V Current (Any Terminal) .................................... 30mA *Allieads soldered or welded to PC board. Derate 10mW/'C above 70·C. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS v+ = 15V. v- = -15V. VEN = +5V (Note 1). Ground = OV. unless otherwise specified. MAX LIMITS NO MEASURED TERMINAL CHARACTERISTIC ~~ TYP 25·C M SUFFIX TEST CONDITIONS TEMP C SUFFIX UNIT - ~'C 25·C 125·C O·C 25·C 70·C SWITCH S to D rOS(ON) 8 180 Vo -10V, Is - -1.0mA!Sequence each switch on 300 300 8 ISO Vo=-10V,ls--l.DmAVAL=0.8V. VAH=2.4V 300 300 20 ArOS(ON) "ros(on) = ''DS(on)max-rOS(on)min 400 400 3S0 3S0 4S0 3S0 350 450 n % Vs = ±IDV rOS(on)aYg· S IS(OFF) 8 0.002 VS-l0V, Vo- -10V ±.S 50 ±1 8 0.002 Vs= -10V, Vo=10V ±.S SO ±1 50 2 0.03 VO-l0V, Vs= -10V ±2 SO ±5 100 ±2 50 ±5 100 VEN -0.8V 50 IO(OFF) D 2 0.03 Vo - -10V, Vs = 10V 8 0.1 VS(ALLj = Vo = 10V Sequence each switch on ±2 50 ±S 100 IOtON) INPUT D 8 0.1 VstALL) - -10V VAL=0.8V, VAH= 2.4V ±2 50 ±S 100 IA(on) 2 0.01 VA = 2.4V or OV -10 -30 -10 -30 IA(off) 2 0:01 VA-15V or OV 10 30 10 30 -10 -30 -10 -30 -10 -30 -10 -30 IA Ao; At EN 2 VEN-SV 1 VEN-O All VA=O (Address Pins) nA p.A DYNAMIC SSe Fig. 3 SSe Fig. 4 SSe Fig. 5 ttransilion D 0.3 \open D 0.2 tEN(on) D 0:6 tEN(off) "OFF" Isolation D 0.4 D 60 VEN - 0, RL f = 500kHz 1 I.S 2OOn, Cs(off) S 5 VS=O Cd(off) D 12 VO-O CIoS 1 Vs - Q, Vo = 0 CdS/offl SUPPLY Supply + v+ 1 40 Current - V- I 2 Standby + v+ 1 1 Current - V- I 1 'j./S t dB ' CL - 3pF, Vs - 3VRMS, VEN lMHz av, f =140kHz to VEN -5V AIIVA=00r5V VEN-O NOTE 1: See Section 1 Enable Input Strobing Levels. 3-167 Nota: All typical values have been guaranteed by characterization and 'are not tested. pF 200 1000 100 1000 100 1000 100 1000 p.A B rH6208 = ! SWITCHING INFORMATION a.ov 1.4V O.IV 1----'1 O~------~--~--------+_--------- Vs,. I - - - - - t VA G.tvs,. 'S4b 10V IH6208 G4-------~~------~--+_~~----- O.tvs. VS4b PROBE IMPEDANCE Ap" lMn CP" 30pF WF0Q4101 ' TC009301 Figure 3: ttrans Switching Test VA ,I .' ______+3.0V §l%_____-'l +15V ~ SWITCH OUTPUT 1 J-, ~~~TFIG.2) ~~'A -::fVs~ ' tope,n ,,'------ ~~~_ 3t r--......"1-~~---2V L""__"'TJ~:Fr.=:l:::VOUT 35pF Tooo9401 WFOO421t Figure 4: t open (Break-Before-Make) Switching Test +15V IEN(oH) ~~--~--~-t---------t---b~---­ G.Wo r - -..............~---o .. V VOUT SWITCH OUTPUT (SEE FIG. a) 35pF TCOO9501 WF004301 Figure 5: ton and toff Switching Test 3,-168 Note: All typical values have been guaranteed by characterization and l\I"e, n,ot tested. IH8208 IH6208 APPLICATION INFORMATION ENable Input Strobing Levels The ENable input on the IH620B requires a minimum of + 4.SV to trigger it into the "1" state and a maximum of + O.BV to trigger it into the "0" state. If the ENable input is being driven from TTL logic, a pull-up resistor of 1k to 3kn is required from the gate output to + SV supply. (See Figure 6). 1K +3V 1~ TC009601 Figure 6: ENable Input Strobing From TTL Logic When the EN input is driven from CMOS logic, no pullup is necessary. (See Fig. 7) +5V TC009701 Figure 7: CMOS Logic Driving ENable Pin 3-169 Note: All typical values have been guaranteed by characterization and are not tested. I IH6208 i IH6208 APPLICATION INFORMATION (CONT.) The supply voltage of the CD4009 affects the switching speed of the IH620S; the same is true for TTL supply voltage levels. The chart below shows the effect on ttrans for a supply varying from +4.5V to +5.5V. CMOS OR TTL SUPPLY TYPICAL ttrans @ 25°C +4.5V +4.75V +5.0V +5.25V +5.50V 400ns 300n5 250ns 200ns 175ns supply voltages decrease, however, the multiplexer, error term (the product of leakage times r05(on») will remain approximately constanf,since leakage decreases as the supply volta,ges are,' reduced. caution must betaken to ensure that the enable (EN) voltage is at least O.7V below V+ at all times. If this is not done the Address Input strobing levels will not function properly. This may be achieved quite simply by cpnnecting EN (pin 2) to V+ (pin 14) via a silicon diode as shown in Figure 8. A further requirement must be met when using this type of configuration; the strobe levels at AO and A1 must be within 2.5V of the EN voltage in order to define a binary "1" state. For the case shown in Figure 8 the EN voltage is 11.3V, which means that logic high at AO and A1 is = + 8.SV (logic low continues to be = O.SV). In this configuration the IH6208 cannot be drivenby TTL (+ 5V) or CMOS (+ 5V) loQic. It can be driven by TTL open collector logic or CMOS logic with + 12V supplies. The throughput rate can therefore be maximized by using a + 5V to + 5.5V supply for the ENable Strobe Logic. The examples shown in Figures 6 and 7 deal with ENable strobing when expansion to .more than four differential channels is required; in these cases the' EN terminal acts as a third address input. If four channel pairs or less are being multiplexed, the EN terminal can be directly connected to + 5V to enable the IH620S at all times. If the logic arid the IH620S have common supplies, the EN pin should again be connected to the supply through a silicon diode. In this case, tying EN to the logic supply directly will not work since it violates the 0.7V differential voltage required between V + and EN (See Figure 9). A 1j.LF capacitor can be placed across the diode to minimize switching glitohes. Using the IH6208 with supplies other than ±15V The IH620S can be used with power supplies ranging, from ±6V to ±16V. The switch r05(on) will increase as the IN.14 +12V ·~'~·-l A CHANNEI.S COMMON DRAIN OUTPUT =0, ).-~,~ 1 • Do ...._ _ _ _ _.. ' =(COMMON) B CHANNEL DRAIN OUTPUT CD003801 Figure 8: IH6208 Connection Diagram for Less Than ± 15V Supply Operation '3-'170 Note: All typical values have been guaranteed by characterization and are not tested. IH6208 IH6208 APPLICATION INFORMATION (CONT.) lN914 EN IH6208 CO004501 Figure 9: IH6208 Connection Diagram With ENable Input Strobing for Less .T~n ± 15V Supply Operation Peak-to-Peak Signal Handling Capability The IH6208 can handle input signals up to ±14V (actually -15V to + 14.3V because of the input protection diode) when using ± 15V supplies. The electrical specifications of the IH6208 are guaranteed for ± 1OV .signals, but the specifications have very minor changes for ±14V signals. The notable changes are slightly lower rDS(on) and slightly higher leakages. 3-171 Note: All typical values have been guaranteed by characterization and are not tested. , IH821:6 (II I S-Channel Differential CMOS Analog Multiplexer GENERAL DESCRIPTION FEATURES The IH6216 is a CMOS monolithic 2 of 16 multiplexer. The part is a plug-in replacement for the DG507. Three line binary decoding is used so that the 16 channels can be controlled in pairs by the binary inputs; additionally a fourth input is provided to use as a system enable. When the ENable input is high (5V) the channels are sequenced by the 3 line binary inputs, and when low (OV), all channels are off. The 3 Address inputs are controlled by TTL logic or CMOS logic elements with a "0" corresponding to any voltage less than O.BV and a "1" corresponding to any voltage greater than 3.0V. Note that the ENable input must be taken to 5V to enable the system and less than O.BV to disable the system. • • • • • • • • • • Pin Compatible With HI507, DG507 & AD7507 ± 11V ..Analog Signal Range rOS(on) < 700 Ohms Over Full Signal and Temperature Range Break·Before·Make Switching TTL and CMOS .Compatlble Address Control Binary Address Control (3 Address Inputs Control 2 Out of 16 Channels) Two Tier Submultlplexlng to Facilitate Expandability Power Supply Quiescent Current Less Than 1001lA No SCR Latchup Very Low Leakage IO(OFF):OS 100pA ORDERING INFORMATION PART NUMBER IH6216MJI IH6216CJ1 IH6216CPI TEMPERATURE RANGE -55°C to + 125°C O°C to 70~C O°C to 70°C PACKAGE 28 pin CERDIP 28 pin CERDIP 28 pin Plastic DIP Ceramic package available as special order only (IH6216MDIICDI) .......,..... .......,..... .,..... ~~ ..........,..... .,..... .,..... :: ~~!T. ...... .,..... ... .,..... DECODE TRUTH TABLE ON SWITCH PAIR X X NONE 0 X 1 1 0 0 0 1 0 1 2 0 1 0 1 3 0 0 1 1 1 4 1 0 0 1 5 0 1 1 6 1 1 1 0 1 7 1 1 1 1 8 LOGIC "1" = VAH > 3V VENH > 4.5V LOGIC "0" = VAL < 0.8V Ail I "00 A1 Ao EN ~ -.,..... TO DECODE LOGIC COHTIIOWNG 10TH TIERS OF MUIING Ao AI A, EN (ENABLE INPun 3 UNE BINARY ADDRESS INPUTS (0 0 0) ANOEN_SV CD004001 ABOVE ElCAMPl.E SHOWS CHANNELS'•• 'b ON. Figure 2: Pin Configuration LOOO2601 Figure 1: Functional Diagram 3-172 Note: All typical values have been guaranteed by characterization and are not tested. I... IH82i8 CI ABSOLUTE MAXIMUM RATINGS VIN (A. EN) to Ground .............................. -15Vo-Vl Vs or Vo to V + ......................................... 0. -32V Vs or Vo to V- ........................................... 0. 32V V+ to Ground ................................................. 16V V- to Ground ................................................ -16V Current (Any Terminal) .................................... 30mA Current (Analog Source or Drain) ...................... 20mA Operating Temperature ......................... -55 to 125'C Storage Temperature ............................ -65 to l50'C Lead Temperature (Soldering. 10sec) ................. 300·C Power Dissipation (Package)" ....................... 1200mW • All leads soldered or welded to PC board. Derate 1OmW I'C above 70'C. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operalion of the device at these or any other conditions above those in~icated in the operational sections of the specifications is not implied. Exposure to. absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS v+ = 15V. v- = -15V. VEN = +5V MEASURED TERMINAL CHARACTERISTIC (Note 1). Ground = OV. unless otherwise specified. MAX LIMITS NO TES,!S TYP PER 2S'C TEMP TEST CONDITIONS C SUFFIX M SUFFIX UNIT -55'C 25'C 12S'C O'C 2S'C 70'C SWITCH S to D rDS(ON) 16 4BO VD = 10V, IS = -lmA Sequence each switch on 600 600 700 650 650 750 16 300 Vo = -10V, .Is = lmA VAL = O.BV,. VAH = 3V 600 600 700 650 650 750 ~rDS(ON) 20 "rOS(on) = rOS(on)max - rOS(-+--i--i-...... ,A I.A ,1 0' OUTLINE DWG. OUTLINEDWG OllTLINE DWGS JE,FD·2 To-l00 To-l00 DS02~301 D$0214Q1 OUTLINE DWG TO·1oo OUTLINE DWGS JE, FD·2 Figure 1: Functional Diagram 3-178 Note: All Iypical.values have been guwantaed by characterization· and arenottestEld. G3 OllTLINEDWG TO·100 08021501 OUTLINE DWG T().100 02 05021601 OUTLINE DWG T().100 IID~DIL MM450/451/452/455 MM550/551/552/555 ABSOLUTE MAXIMUM RATINGS (Note 1) Gate Voltage (VGG) ......................... + 14.5V to -30V Bulk Voltage (VSULK) ...................................... + 14V Analog Input (VIN) ............................. + 14V to -20V Power Dissipation ......................................... 200mW Operating Temperature MM450, MM451 , MM452, MM455 .. - 55·e to + 125·e MM550, MM551, MM552, MM555 .......... o·e to 70·e Storage Temperature...................... -65·e to + 150·e Lead Temperature (Soldering, 10sec) ................. 300·e NOTE 1: Dissipation rating assumes device is mounted w~h all leads welded or soldered to printed circuit board in ambient temperature below 70·C. For higher temperature, derate at rate of 10mWI"C for FD package and 6.5 mWI"C for TW package. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (per channel unless noted) LIMITS SYMBOL CHARACTERISTIC TYPE Analog Input Voltage VIN TEST CONDITIONS All VOG=O Threshold Voltage VGS(Th) All Drain·Source On Resistance All IGSS Gate Leakage Current All Drain Leakage Current 10(OFF) VGS = -25V, VSS = Vos = 0 VOS- -25V MM550, MM551 MM552, MM555 VGS =VSS= 0 MM450, MM451 MM452, MM455 IS(OFF) Source Leakage Current Cos Drain·Body Capacitance NOTE 1: V Max 600 700 Max 200 250 Max n n t5 100 Max nA to.5 200 Max nA Max nA Max nA 100 to.5 400 Max nA 10 Typ pF MM450, MM550 14 Typ pF MM451 , MM551 24 Typ pF MM452, MM552 11 Typ pF 11 Typ pF 13 TY1! Typ pF pF Typ pF Typ pF Typ pF 100 VOS = VGS = VSS = 0 f= lMHz (Note 1) MM455, MM555 8 9 9 All 5 MM452, MM552 Gate·Source Capacitance CGS V Min 125·C All MM450 MM550 MM451, MM551 Gate·Body CapaCitance Max 1.0 VOS -VGS = 0 MM455, MM555 CGS ±10 20 VSS = -25V MM550, MM551 MM552, MM555 Source·Body CapaCitance CSS liD-lornA VS=10V JVGS= -20V VIN= +10V MM450, MM451 MM452, MM455 UNIT 70·C 3.0 10 = 10jJA VIN - -10V ROS(ON) MIN -MAX 25·C Typical characteristics not tested in production TYPICAL PERFORMANCE CHARACTERISTICS RDS(on) VB VGS RDS(on) 10,000~m g VGS VB RDS(on) '11.- .I.~.: 10,000 100.000 V11\I-OV 10" 1 rnA VB DRAIN CURRENT va GATE TO SOURCE VOLTAGE VGS VU C tlOV V, .. • -10'11 10 ! 8.0 1000 10,000 ; I T .. • 2S~C Til· _55°C .~ 1000 ~60~~~~~~~~ ~40~-r4-~~~1-~ ~ o ·s ·s -16 -22 IO~~~~~---'-L~ o -4 -8 -12 -16 -20 100 '-''-'--'-'----'---'---'-' -'6 -II -19 -20 OP036901 3-179 Note: All typical values have been guaranteed by characterization and are not tested. 2.0 H-+-+-+-il-+~+-H o~~~~~-L~LJ o -to -2.0 -3.0 ..... 0 -SO VG5 - GATE TOSOURCi VOLTAGE IVI VGSIYI VGslVI OP036801 _17 'lin-a.... Z T .. " 85"C . ;" 100 ' ",,..."'-=....,.""'=.,.-,r-r-r-r-...... . 10= 1 mA OP037OO1 0P037101 Section 4 - Amplifiers Operational and Special Purpose ICH8500/A Ultra Low Input-Bias Operational Amplifier GENERAL DESCRIPTION FEATURES The ICM8500 and ICH8500A are hybrid circuits designed for ultra low input bias current operational amplifier applications. They are ideally suited for analog and electrometer applications where high input resistance and low input current are of prime importance. Functionlllly, they are pin for pin identical to the popular 741 monolithic amplifier. These amplifiers are unconditionally stable and the input offset voltage can be adjusted to zero with an external 20kil potentiometer. The input bias current for the inverting and noninverting inputs is 0.1 pA maximum for the ICH8500, and 0.01 pA maximum for the ICH8500A and are constant over the operating temperature range of -25°C to +85°C. Pin 8 is connected to the case. This permits the designer to operate the case at any desired potential. This is the key to achieving the ultra low input currents associated with these two amplifiers. Forcing the case to the same potential as the inputs eliminates current flow between the case and the input pins, and leakage currents that may have otherwise existed between any of the other pins and the inputs are intercepted by the case. • • • • • • Input Diode Protection Input Bias Current Less Than O.01pA C8500A) at All Operating Temperatures No Frequency Compensation Required Offset Voltage Null Capability Short Circuit Protection Low Power Consumption APPLICATIONS • • • • • • • Femto Ammeter Electrometers Long Time Integrators Flame Detectors pH Meters Proximity Detector Sample and Hold Circuits ORDERING INFORMATION ICH 12=~~"::9M"" 8500A TV DEVICE TYPE INTERSIL HYBRID '----------CIRCUIT v' CASE (GUARD) CO018801 OFFSET NULL 05019901 Figure 1: Functional Diagram Figure 2: Pin Configuration (Outline dwg TV) 4-1 Note: All typical values have been guaranteed by characterization and are not tested. Cao i ICM850c)1A 10 zCD !:! IID~OIL ABSOLUTE MAXIMUM RATINGS Supply Voltage ................................................ ±18V Internal Power Dissipation (1) ......................... 500mW Differential Voltage ........... ; ............. , ......... , ...... ±O.5V Storage Temperature ...................... -65°C to + 150°C Operating Temperature .............•....... -25°C to +85°C Lead Temperature (Soldering, 10sec) ................. 300°C Output, Short Circuit Duration ........................ Indefinite Note: 1. Rating applies for ambient te":lperature, to + 70·C NOTE: Stresses above those listed u~ "Absolute Maximum Ratings" may cause permanent device failure. These are stress ratings only and functional operation of the devices at these or any other cond~ions above 1hose indicated in the operation sections of this specHication is not implied. Exposure to absolute maximum rating condition~ for extended' periods may cause device failures. ELECTRICAL CHARACTERISTIOS '(TA = 25°C unless otherwise specified, VSUPPLY ICH8500 SYMBOL IBIAS VOS CHARACTERISTICS Input Bias Current (Inverting and Non-Inverting) TEST CONDITIONS ±7S , ±SO mV ±200 ±100 mV ±3.0 ±3.0 mV 75 dB Common Mode Rejection Ratio ± 5 volts common mode voltage Large Signal Voltage Gain pA mV At 2S·C AVOL ±O.o1 +25 to +85·C -2S to +2S·C Long Term Input Offset Voltage Stability Output Voltage Swing UNIT ±50 D.Vos/D.t Common· Mode Voltage Range TYP MAX ±SO D.VoslD.T tNo MIN ±0.1 , 20kn Potentiometer Change in Input Offset Voltage Over Temperature CMVR ICH8500A TYP MAX Input Offset Voltage Offset Voltage Adjustment Range CMRR MIN Case at same potjlntial as inputs = ±15V) 75 RL'" 10kn ±11 ±11 ±10 ±10 20,000 105 20,000 V V 105 - Cfb Feedback Capacitance Case guarded, 0.1 0.1 pF SR Slew Rate RL'" 2kn 0.5 0.5 V/IJS CIN Input CapaCitance Case guarded 0.7 0.7 pF CIN Input CapaCitance Case grounded 1.5 1.5 pF VOLTAGE OFFSET NULL CIRCUIT VOLTAGE FOLLOWER LOW LEVEL CURRENT MEASURING CIRCUIT OUTPUT Yo • 1VOLT IpA = 1012, liN CASE GUARD TCQ281(N LC014701 1.0014801 NOTE: Adjust input offset voltage to OV±10I'V balore measuring leakage. Figure 3: Circuit Notes 4-2 Note: All typical values have been guaranteed by characterization and are not tested. ICH8500/A TYPICAL PERFORMANCE CHARACTERISTICS INPUT VOLTAGE RANGE SUPPLY VOLTAGE OPEN LOOP VOLTAGE GAIN VI. FREQUENCY 106 ;: ~ i w ~ o ~ z o ~ 100 1 Ie. 10k lOOk '" 8'" INPUT OFFSET VOLTAGE SUPPLY VOLTAGE 100 - 4'VSU~LY'+5~ 60 8 9 10 11 12 '. ...::>~ ! I I:;;;;: f-- Tp.."''''aso C - = ~ ~ 80 0 ~ 'j"+25' C ,0 4 13 14 15 16 9 10 1 10 ~~ 0 "~'" \. " 11 12 13 14 15 8 1.6 10 11 12 13 14 15 0P035401 OP035301 INPUT REFERRED NOISE VOLTAGE 500 ~ , I r-" ~ ~ TOO 10 \ I 100 SUPPLY V8. 80 'I o POWER CONSUMPTION VOLTAGE ~s'.!\odn \ 16 SUPPLY VOLTAGE i'V) V8. SUPPLY VOLTAGE ltV} ~~ .. , ...0- ~ OP0352OI ±QUIESCENT SUPPLY CURRENT SUPPLY VOLTAGE ~ .. ~\.. I!:::> SUPPLY VOLTAGE (:tV) SUPPLY VOLTAGE bVI 16 TA"'+25"C o 8 16 ~ i ~ 12 14 OUTPUT VOLTAGE SWING VB. SUPPLY VOLTAGE '" 11 13 0P035101 ~ 90 10 - 5 VOLT COMMON MODE VOLTAGE z ...>w 8 • ~~ ;..;;; SUPPLY VOLTAGE I-V) ±POWER SUPPLY REJECTION RATIO V8. SUPPLY VOLTAGE V8. • 0 ~ ~ OP035001 10 s 70 SUPPLY VOLTAGE (tVI 0P034901 ~ ~ .;.:! 'po 1M FREQUENCY (Hz I :;'" 80 ~ z o 1 10 • o TA· .. 2oC ~ COMMON MODE REJECTION RATIO V8. SUPPLY VOLTAGE ~ V~UI'P .I,lSV l"- :> V8. z \2 Ii: . I ::> '0!1 u i '" ~ ~ lk 10k lOOk FREQUENCY IHzl OP035501 Note: All typical values have been guaranteed by characterization and are not tested, 50 40 30 iff.! 1 ....:: 20 ~ 10 o 8 ?' 9 10 11 .' ~ .....,:" '-- f-- ... ,.. 12 13 14 15 16 SUPPLY VOLTAGE (tVI CP035601 OP035701 i .O~OIL ICH8soO/A I currents that may otherwise exist between the ± 15V input and the inverting input summing junctions. FeedbaCk capacitance" should be kept to minimum in order to maximize the response time of the circuit to step function input currents. The time constant of the circuit is approximately the product of the feedback capacitance Ctb times the feedback resistor Rfb: For instance, the time constant of the circuit in Figure 4 is 1 sec if Cfb = 1pF. Thus, it takes approximately 5 sec (5 time' constants) for the circuit to stabilize to within 1% of its final oiJtput voltage after a step function of input curre~t has been applied. Ctb of less than 0..2 to O.3pF can be achieved with proper circuit layout. A practical pico ammeter circuit is illustrated in Figure 5. APPLICATIONS ;:; ThePICo Ammeter t~rmina,ls A very ~ensitive pico ammeter can be constructed with the ICH850Q. The basic circuit (illustrated in Figure 4) employs the amplifier in the inverting or current summing mode. Care must be taken to eliminate any stray currents from flowing into the current summing node. This can be accomplished by forcing all points surrounding the input to the same potential as the input. In this case the potential of the input is at virtual ground, or O.V.Therefore, the case of the device is grounded to intercept any stray leakage a Rib" loUn CURRENT SOURCE ~U. ENT/ >----'---'--OUTPUT Vo" .IIN SUMMING NODE Atb -·IVOl.T/pA LC014901 Figure 4: Basic Pico Ammeter Circuit .,sv .Ib 10t20: ., t"" IMNT>---~~--~~----~----~~----------_I ----I,. cO ~----_--_--------. OU""'T V•.--I IfW JlIOUSl .. -I VOl.TIpA INTERNAl. olooes 08020001 Figure 5: Pico Ammeter Circuit Note: All typical values have been guaranteed by characterization and are not tested. ICH8500/A .... CAN IE REDUCED TO 10K IF CIRCUIT IS EllPl.OYED AS ANINTEORATOR INPUT TERMINAL If CIRCUIT ASAN::'~:~~~~~ VIN-OTOt'OV CHARGE STORAGe CAPACITOR r--"""-+-----------. / SW2 INPUT ~E~~~~~ AS A'::::tt!~g 111700 • l00ttO >-~Oy.OI/l'....__+-----...;O r-i~--""'--_--O;"""---f HOLD CIRCUn Y,N -OTO:t10V 8 ....._ >.....:~- 1T1100 G OUTPUT +lSV 'Oof v, .-...J'I/I."",......_0_15V IOkn -ISV 'M" .ok" o.c. lERO v, SAMPLE 1T1700 PuLSfOR CAPACITOR OISCHARGE PULSE ADJUST eNULL TO ELIMINATe ANV OUTP\lt OfFSET VOLTAGE DUE TO CHARGE INJECTION t-----------------------~---JF.OMSW2 ,."" ":" -1SV TC0264~ Figure 6: Sample and Hold Circuit or Integrator Circuit The internal diodes CR1 andCR2 together with external resistor R1 protect the input stage of the amplifier from voltage transients. The two diodes contribute no error currents, since under normal operating conditions there is no voltage across them. source, drain and gate of switch SW2 are zero or near zero when the circuit is in the hold mode. Careful construction will eliminate stray resistance paths and capacitor resistance can be eliminated if a quality capacitor is selected. The net result is a low drift sample and hold circuit. As an example, suppose the leakage current due to all sources flowing into the current summing node of the sample and hold circuit is 100pA. The rate of change of the voltage across the 0.01 j.LF storage capacitor is then 1OmV I sec. In contrast, if an operational amplifier which exhibited an input bias current of 1nA were employed, the rate of change of the voltage across CSTO would be 0.1 V Isec. An error build up such as this could not be tolerated in most applications. Wave forms illustrating the operation of the sample and hold circuit are shown in Figure 7. Feedback capacitance is the capacitance between the output and the inverting input terminal of the amplifier. Sample and Hold Circuit The basic principle of this circuit (Figure 6) is to rapidly charge a capacitor CSTO to a voltage equal to an input Signal. The input signal is then electrically disconnected from the capacitor with the charge still remaining on CSTO. Since CSTO is in the negative feedback loop of the operational amplifier, the output voltage of the amplifier is equal to the voltage across the capacitor. Ideally, the voltage across OSTO should remain constant, causing the output of the amplifier to remain constant as well. However, the voltage across CSTO will decay at a rate proportional to the current being injected or taken out of the current summing node of the amplifier. This current can come from four sources: leakage resistance of CSTO, leakage current due to the solid state switch SW2, currents due to high resistance paths on the circuit fixture, and most important, bias current of the operational amplifier. If the ICH8500A operational amplifier is employed, this bias current is almost non-existant « 0.01pA). Note that the VOltages on the The Gated Integrator The circuit in Figure 6 can double as an integrator. In this application the input voltage is applied to the integrator input terminal. The time constant of the circuit is the product of R1 and CSTO. Because of the low leakage current associated with the ICH8500 and ICH8500A, very large values of R1 (Up to 10 12 ohms) can be employed. This permits the use of small values of integrating capacitor (CSTO) in applications that require long time delays. Waveforms for the integrator circuit are illustrated in Figure 8. 4-5 Note: All typical values have been guaranteed by characterization and are not tested .. IIO~DIL ~ ·ICH8500/A 8 ~.------____----__--~ I O....Jr----, ., +5V V,N SAMPLE PULSE 0--1 +I.V~TIME-. bl V, v, bl -f5V ,I ~' V2 V3 ,I V2 , - - -...., .1 STATE OF SW2 II I +'.V~' : ., hI i--CLOSED--I I OUTPUT OP.AMP. ., . STATE OF SWI ~ .000EN "'-=LE 0------- ~ I II 11 II " CLOSED ~Of'EN_jlIHr ...~_ _ Of'EN I, I V3 -15V " CLOSED II INPUT TO +18V - - - - - - - - " " \ SAH -15:~ +15V -15V STATE OF SW' TIME~ +16V~ -15V 0-, -15V dl r--'""'1 •. :.•..•...•• ~ >IV STAn OF SW2 WINDOW _____ "-- 0=S: -----------_______________ ~v--~~------ CLOSED II - I ~OPEN __ Of'EN II ~LOSEO IL.:it: I--CLOSED-t OPEN ~=LEWINDOW 9\ INTE~~:ri~~ 0 ------~---INPUT -lOY hi INTE~~~~~ V,N Vo" - RCSTO 1" 0.1 VOLT/SEC. WF015801 Figure 7: Sample and Hold Circuit Waveforms -~---~------WF015901 Figure 8: Gated Integrator Waveforms Note: All typical values have been guaranteed by characterization and . are nat tested. U~D[61.. ICH8510/8520/8530 Power Operational Amplifier o CD GENERAL DESCRIPTION FEATURES The ICH8510/8520/8530 is a family of hybrid power amplifiers that have been specifically designed to drive linear and rotary actuators, electronic valves, push-pull solenoids, and DC & AC motors. There are three models available for up to + 30V power supply operation: 2.7 amps @ 24 volt output levels, 2 amps @ 24V and 1 amp @ 24V. All amplifiers are protected against shorts to ground by the addition of 2 external protection resistors. For a device operating at lower voltages, see the ICH8515 data sheet. ' The design uses a conventional 741 operational amplifier, a special monolithic driver chip (BL8063), NPN & PNP power transistors, and internal frequency compensating capacitors. The chips are mounted on a beryllium oxide substrate for optimum heat transfer to the metal package. This substrate also provides electrical isolation between amplifiers and metal package. The I.C. power driver chip has built-in regulators that provide the 741 with typically a ±13V supply. • • • • • • • • • Delivers Up to 2.7 Amps @ 24-28V DC (30V Supplies) Protected Against Inductive Kick Back With Internal Power Limiting Programmable Current Limiting (Short Circuit Protection) Package Is Electrically Isolated (Allowing Easy Heat Sinking) Open Loop DC Gain> 100dB 20mA Typical Standy Quiescent Current Popular 8 Pin TO-3 Package Internal Frequency Compensation Can Drive Up to 0.1 Horsepower Motors ORDERING INFORMATION ICH8SXO M KA I T <=-~- ~ KA = 8 lead T0-3 can Temperature Range M - Military -SsoC to I = Industrial - 20°C to + 12SoC + 8SoC Basic Part Number 8S10 = 1A output 8520 = 2A output 8S30 = 2.7A output y+ (TOPYIEW) +----""---l-=-...;. voo-=; '~_-+'W'v-1...;IASC-· c001B901 y- 08020101 FI ure 1: Functional Dia ram Fi ure 2: Pin Confl uration 4-7 Note: All typical values have been guaranteed by characterization and are not tested. i CD &II W o g10' ICtl851Qj852018530 '.;.' . . '.' . , .' ~ AB50LUTEMAXIMUMRATINGS @TA=25·C i...... Operating Temperature Range M ...... -55·C ~ +125·C . I ........ -20·C ~ +85·C Storage Temperature Flange ........ ::.:. -65·C to +150·C Le~d Temperature (Soldering" 1Psec) ...... ,.",..... ,.3qO·p . Max Case Temperature ...... , ~ ................ : .......... 150·C Supply Voltage ............................................ ; .• ~.± 32V Power Dissipation, Safe Operating Area ...... See Curves 0, Differential Input Voltage ...................................±30V 10 Input Voltage ............................ , ........ ±15V (Note 1) CD peak Output Current ................... See Curves (Note 2) Output Short Circuit Duration (to ground) .............................. Continuous (Note 2) .. -lj' Note 1: Rating applies to supply vollSges of ± 15V.For lower supply voltages, VrNMAX ~ Vsupp. Note 2: Ratings apply as long as package dissipation is not exceeded. Device must be mounted on heat sink, see Figures 12 and 16. Stresses above those listed under Absolute' Maximum Ratings may cause permanent damage' to ·the device. These arestrEiss ratings only, and flinctional operation of the device at these or any other conditions above those indicated in the operational sections of the spec~ications is not implied. Exposure to absolute maximum rating conditions for extended; periods may affect device reliability. ELECTRICAL CHARACTERISTICS TA = + 25·C. VSUPPLY = ±30V (unless otherwise stated) SYMBOL .DESCRIPTION TEST CONDITIONS t.VOSIt.Pd Input Offset Voltage Change with Power DiSsipation Mtd on Wakefield 403 Heat Sink Vos Input Offset Voltage RS< 10kll Pd< lW ISlAS Input Bias Current RS< 10kll Pd< lW ICH85101 ICH8510M ICH85201 MIN MIN MIN 4 (Typ.) -6 -3 +6 +3 500 Inpol Offset Current RS< 10kll Pd< lW Large Signal Voltage Gain RL-201l Vo> 2/3 Vsupp VCMR Input Voltage Range Typical CMRR Common Mode Relction Ratio Rs-l0kll PSRR Power Supply RS-l0kll SR 'Slew Rate VOMAX Ou1pol Voltage Swing RL-201l Ay -10 ±26V ±26V IMAX Output Current (3) RL-ell Av-l0 1.0 1.0 10 Power Supply Quiescent Cur:rent RL-X VIN-OV 100 (Typ.) -10 +10 -10 70 (Typ.) CL-3pF, Av-l RL -lOll Vo - 2/3 Vsupp -6 +6 70 (Typ.) -10 MAX ICH65301 -3 +3 70 (Typ.) -6 ICH8530M +6 70 (Typ.) -3 200 100 (Typ.) +10 Mifol 500 100 -10 MAX 4 (Typ.) 250 100 (Typ.) +10 MIN 2 (Typ.) 200 100 (Typ.) +10 MIN 500 100 200 100 (Typ.) MAX 4 (Typ.) 250 lOS Rejection Ratio MAX 2 (Typ.) AVOL NOTE 2: ICH8520M UNIT MAX -10 MAX 2 (Typ.) mV/W +3 mV 250 nA 100 'M dB 100 (Typ.) +10 -10 +10 V dB 70 (Typ.) 70 (Typ.) 77 77 77 77 77 77 (Typ.) (Typ.) (Typ.) (Typ.) (Typ.) (Typ.) 0.5 (Typ.) 0.5 (Typ.) 0.5 (Typ.) 0.5 (Typ.) 0.5 (Typ.) 0.5 (Typ.) VII'S ±26V ±26V ±25V ±25V V 2.0 2.0 2.7 2.7 A (RL (RL - 3011) -30n 125 100 125 100 125 dB 100 mA See Figure 7 if P~r Suplies are less than ± 30V '. ELECTRICAL SPECIFICATIONS TA= -55·C. to +125·C.(M) or TA= -20·C. to +85·C (I). SYMBOL DESCRIPTION TEST CONDITIONS VOs Inpol Offset Voltage PdoI ~igure l.C015001 Figure 3: Maximum Output Current for GlvenRSc 5: Inductive Load (Note catch diode) NOTE ON AMPLIFIER POWER DISSIPATION The steady state power dissipation limit is given by In general, for a given Va, Isc limit, and case temperature TC, Rsc can be calculated from 'the equation below for Va positive, lOUT positive. ' RSC= PO= _ _ T.::,J",,(M;;;,.AX=-.)-_T...;cA.:,.'_ R8JC + RBCH + R8HA where: TJ = Maximum junction temperature TA = Ambient temperature R8JC = Thermal resistance from transistor junction to case of package R8CH = Thermal resistance from case to heat sink R8 HA = Thermal resistance f~om heat ,sink to ambient air And since TJ = 200"C for silicon transistors R8JC 9!; 2.0°C/W for a steel. bottom TO-3 package with die attachment to beryllia substrate header ROCH;>= .045°C/W for 1 mil thickness of Wakefield type 120 thermal joint compound .09°C/W for 2 mil thickness of type 120 .13°C/W for 3 mil thickness of type 120 .17°C/W for 4 mil thickness for type 120 .21°C/W for 5 mil thickness of type 120 .24°C/W for 6 mil thickness of type 120 (20.6VO)" + 680-2.2(TC..,2S0C) ISC(lIMIT) "For Va negative, replace this term with 10.3 (VA - 1.2) For example, for 10 = 1.SA @ Va = 2SV and TC = 2SoC, 119S Rsc = - - = 0.797 1500 Therefore for this application, RsC = 0.820 (closest standard value). When 0.820 is used, ISC @ Va = OV will be reduced to about 1A. Except for small changes in the "±VO(max) Limit" area, the effects of changing Rsc on the lOUT vs VOUT characteristics can be determined by merely changing the lOUT scale on Figure 3 to correspond to the new value. Changes in TC move the limit curve bodily up, and down. This internal current limiting cirCUitry however does not at all restrict the normal use of the driver. For any normal load, the static load line will be similar to that shown in Figure 3. 4-9 Note: All typical values have been guaranteed' by characterization and are not tested. I lCH8smls520/8530 R8HA = The choice of heat sink that a user selects 1'. depends'upbnthe amount of room availablE! mount the'l\eat Sink.. A sample calculation follows: by' choosing a Wa:kefield 403 heat sink,' wlthfree air, natural convection 1no fan). R6HA ~ 2.0·C/W. Using 4 'mil 'joint compound, to Po .. 12001'6_ 2S"C 4. 17°CIW. 42W and @ TA =, 125°C, "200°C -125°C , =18W 200·C- TA ' 200·C- TA .. - - - - ' - ' (2.0 + 0.17 + 2.0)OC/W 4.17°C/W 4. 17ciC!W From Figure 6 the worst case steady state power dissipation 'for an IH8520 (Rsc .'0;62fl) is 'aoout30W and 18W'I"espectively. Thus this heat sink is adequate. ,TYPICAL PERFORMANCE' CHARACTERISTICS tat 1120. lI'Iu111p1f lou• .., .... For ICtIIS30 ICH_ RIC" ...n TCASE HOC Vee ,.~ louT f ..,ua . loUT TeASE '.·C Vee !3IV' For lett.B'G. ......'· Rile = 1.an Source CurNftt ,I on., ......... _c.._ --. -~ ..........1 .... Dt..... LInH... with T."",; '-~~~~~~4-~~~~~~-' __ ..11 ..act . " , ..'0 ... • 10 15 20 H 1DV YOuT . . -25 -21 -15 .. '0 5 -S 10 15 20 25 30 YOUT sc007001 Safe Operating Area; lOUT vs VOUT vs TC 101( 100 " 15 10 II 30 _ _ _ (WI ... :"1.;.; on YIn ~ 10 get ......,... Po'ftf DIu.. tMn.,_IOGo!II''' _ _ ('IOUT·11X'~ sc007101 lC015101 Input ,Offset Voltage vs Power Dissipation ... "':':. LC015201 sc007201 Input .Impedance vs Gain vs Frequency +10 Note: All typical values have been guaranteed by characterizatioll. and .ara not,tastad. ,~ IID~OIL ICH8510 /8520 /8530 TYPICAL PERFORMANCE CHARACTERISTICS (CONT.) •I I ....... +Vee CM' ..Vee t_) ./ .' 40 IK ~ ~ ID ; o GuIeIGHI: c....... IrOIn • .. g 0 LC015301 SCOO7301 Quiescent Current va Power Supply Voltage .. Your _ _ _ Your 2: :tt7'lo Yee 100kHz 1_ ,K 111Hz Vln@f - 100 c:IoMci Iaop ..... 100 ,0 --At IIIClI At IIIn Rf ",on ,.... sc007'" Rt .. 1Kn 1iir LCOt5401 ' Large Signal Power Bandwidth II At c..._ IK ,- Vln@t 1KHI 1OKHI. 100KHI _HlI ':;' LC01 .... SCOO7&Ol Small Signal Frequency Response 4-11 Note: All typical values have been guaranteed by characlellzalion ilhd lil'enot I_tett -::- Rf~1~RI 080202.01 Figure 8: Non-Inverting Amplifier .... . . 0 +15" +10 +11 +100 ..., •. c.o.'T_ CTe)' C·CI , SCOO7601 , Figure 6: Maximum Output Current vs. Case Temperature v'" III 05020301' Figure 9:, Inverting Amplifier ... Power dissipation is another important parameter to consider. The current prptection circuit protects the device against short circuits to ground,,(but only for transients to the oppo~ite supply) provided the, device has adequate heat sinking. A 'curve of power dissipation Viii Vo under short circuit conditions is given in Figure 10. The limiting circuit is more' closely dependent on case temperature than (output transistor) junction temperatures. Although these operating conditions are unlikely to be attained in actual use, they do represent the limiting case a heat sink must cope with. For a fully safe design, the antic1patedrange, of Vo values that could occur;' (steady state, includihgfaults) should be examined for the highes~ power dissipatiOn, and the device provided with a heat 'sio1( that will'keep the junction temperature below 200·C and the case temperature below 150·C with the worst case ambient, t~mperature expected. ... Figure 7: scoonot Maximum Output Current vs. VSUPPLY .,- ,',> APPLICATION' NOTES. :> The maximum input voltage'rang~, for VSUPPLY < ± 15V, is substantially less t~an thcf avail.~bleoi1tput voltage swing. Thus non-inverting amplifiers, as ,in Figure 8, should always be set up witha,gairi greater than iit;out 2.5, (with ±30V supplies), so that the full oiJtput swing is available without hazard to the input. At first sight, it would seem that no restrictions would apply to inverting amplifiers" since the' inputs are virtual ground and ground. However, under fault (output short-circuited) or high slew conditions, the input can be substantially removed from ground. Thus for inverting amplifiers with gains less than about 5, some protection should be provided at this input. A suitable resistor from the input to ground will provide protection, but also increases the effect of input offset voltage at the output. A pair of diodes, as shown in Figure 10, has no effect on normal operation, but gives excellent protection. Source eIIMeIon ....... ' ,. ,(, .,,~"": Pella' . ~r----""'---...!' ,--;ani, For II. ., " " ' " 'lOUT "'_.-. TrinMnts ,,;'-' ,,;' ./ ·YOUT' 30Y 25'1 20V 15Y lOY 5Y sc007601 Figure 10: Power Dissipation under Short Circuit Conditions +-12 Note: All typical values have been guaranteed by characterization aod ,are not teste!!;, ICH8510 /8520 /8530 TYPICAL APPLICATIONS Actuator Driving Circuit (24 .... 28 VDC rated) Obtaining Up To 5 Amps Output Current Capability By Paralleling Amplifiers . . , .... " Actuato, / .... 'on Acht.-tOf /j:::::') YOu' 05020401 Figure 11: Power Amp Driving Actuator The gain of the circuit is set to + 10, so a VIN = +2.4V will produce a +24V output (and deliver up to 2.7 amps output current). To reverse the piston travel, invert VIN to -2.4V and VOUT will go to -24V. Diodes 01 and 02 absorb the inductive kick of the motor during transients (turn-on or turn-off); their breakdown should exceed 60V. SCOO7901 Figure 12: Paralleling Power Amps for .Increased Current Capability This paralleling procedure can be repeated to get any desired output current. However, care must be taken to provide sufficient load to avoid .the amplifiers pulling against each other. Driving A 48VDC .Motor --- --------, _ow I I 1 1 1 1 1 1 I 1 1 __ ____ 1 ~--~~-+~-_~_-_~ ~ .... . ....... = .,.~ 90007801 Figure 13: Power Amp Driving 48 VDC Motor 4-13 Note: All typical values have been guaranteed by characterization and are not tested. I IC"8510/8520/8530 CD 2,I 0' .. :I ~..... .... Precise Rate Control' of an Electronic Valve The circuit presented in Figure 14 is also an excellent way to get a precise power supply voltage; in fact, it is possible to build a preCision variable power supply using a BCD coded DAC with' BCD Thumbwheel switches. There are two methods to get very fine control of the opening of an orifice driven by an electronic valve. 1. Keep the voltage constant, i.e., 24VDC or 12VDC, and vary the time the, voltage is applied, i.e., if it takes five seconds to completely open an orifice at 24VDC, then applying 24V for only 2Y2 seconds opens it only 50%. 2. Simply vary the DC driving voltage to valve. Most valves obtain full opening as an inverse of applied voltage,i.e., valves open 100% in five seconds at 24VDC and in·l0 seconds at 12VDC. A circuit to perform the second method is shown below; the advantage of this is that digit switches can precisely set driving voltage to 0.2% accuracy (S-bit DAC), thereby controlling the rate at which the valve opens. There is great power available in the sub-systems shown in Figures 14 & 15; there the 0/ A converter is shown being set manually (via digit switches) to get a precise analog output (binary #x full scale voltage), then the driver amplifier multiplies this voltage to produce the final output voltage. It seems obvious that the next logical step is to let a microprocessor control the 0/ A converter. Then total; pre-programmable, electronic control of an actuator, electronic valve, motor, etc., is obtained. This would be used in conjunction with a transducer/multiplex system for electronic monitoring and control of any electromechanical function. 'Ok +5" ... lC015601 Figure 14: Digitally Controlled Electronic 4-14 Note: All typical values have been guaranteed by characterization and are net tested. Valu~ ICH8510 /8520/8530 4K .-tIY +5V Nt. -=LC015701 21 22 1 1 1 1 1 0 1 0 0 0 0 0 The power 2° 1 1 0 0 23 24 25 26 27 o BITVout + 25VDC 1 1 1 1 1 1 1- 1 1 1 1 o -25VDC 1 1 0 0 1 1 +15VDC 1 1 0 0 1 o -15VDC +0.098VDC 0 0 0 0 0 1 -0.098VDC 0 0 0 0 0 o supply can be set set Ie ± 0.1 VDC. Figure 15: Digitally Programmable Power Supply HEAT SINK INFORMATION Heat sinks are available from Intersil. Order part number 29-0305 ($10.00 ea.) with a ROHA = 1.3°C/watt. A convenient mating connector is also available. Order part number 29-0306 ($4.50 ea.). Note: This product contains Beryllia. If used in an application where the package integrity may be breached and the internal parts crushed or -machined, avoid inhalation of the dust. APPLICATION NOTES For Further Applications Assistance, See: A021 "Power D/A Converters Using The ICH8510/201 30," by Dick Wilen ken A026 "DC Servo Motor Systems Using The ICH8510/201 30," by Ken McAllister A029 "Power Op Amp Heat Sink Kit," by Skip Osgood 4-15 Note: All typical values have been guaranteed by characterization and are not tested. , ICM8515 iPower Operationa'i ~Amplifier GENERAL DESCRIPTION FEATURES The ICH8515 is a hybrid power amplifier specifically designed to drive linear and rotary actuators, electronic valves, push-pull solenoids, and DC & AC motors. The design uses a conventional 741· operational amplifier, a special monolithic driver chip (BL8063), NPN & PNP power transistors, and an internal frequency compensating capacitor. The chips are mounted on a. beryllium oxide substrate, for optimum heat transfer to the metal package. This substrate provides electrical isolation between the amplifier and the metal package. The 8515 has special SOA (safe operating area) circuitry which allows it to withstand a direct short to ground or to either supply indefinitely. It has been designed to operate with ± 12 or ± 15VDC supplies and will deliver typically 1.5 to 1.8A @ +13V out using ±15V supplies. Internal frequency compensation provides stability down to unity gain (either inverting or noninverting) even when using inductive loads. • • • • • • • • • Delivers Up to 1.5 Amps @ + l2VDC (±15VDC Supplies) Protected Against Inductive Kick Back By Internal Power Limiting Prograinmable Current Umiting (Short Circuit . Protection) Package Is Electrically Isolated (Allowing Easy Heat' ·Sinking) Open Loop DC Gain> 100dB Popular 8 Pin TO-3 Package Internal Frequency Compensation Can Drive Up to 0.033 Horsepower Motors Pin Equivalent to ICH8510/20/30 Family ORDERING INFORMATION PART NUMBER OUTPUT CURRENT TEMPERATURE PACKAGE ICH8515MKA 1,5A -55°C to + 125°C 8·Lead TO-3 ICH85151KA 1.25A -25°C to +85°C 8'Lead TO·3 Y' (TOP VIEW) +----1--:,---..;;' Yo~ .....~~+'IN..,........o5ASC- C1lO19OO1 4 08020501 Figure 1: Functional Diagram 4-16 Note: All typical values have been guaranteed by characterization and· are not tested. Figure 2: Pin Configuration (Outline dwg KA) n z ICH8515 CD ABSOLUTE MAXIMUM RATINGS @ TA ... UI UI = 25°C Supply Voltage ................................................ ±18V Power Dissipation, Safe Operating Area ...... See Curves Differential Input Voltage ................ , .................. ±30V Input Voltage ..................................... ±15V (Note 1) Peak Output Current ................... See Curves (Note 2) Output Short Circuit Duration (to ground) .............................. Continuous (Note 2) Operating Temperature Range M ...... -55°C to + 125°C I ......... -25°C to +85°C Storage Temperature Range ............ -65°C to + 150°C Lead Temperature (Soldering, 10sec) ................. 300°C Max Case Temperature ................................... 150°C Note 1: Rating applies to supply voltages of ± 15V. For lower supply voltages, VINMAX = VSUPPLy. Note 2: Rating applies as long as package dissipation is not exceeded for heat sink attached. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other cond~ions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS OPERATING CHARACTERISTICS TA = + 25°C. VSUPPLY = ±15V (unless otherwise stated) ICH85151 SYMBOL PARAMETER ICH8515M TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX tiVos/tiPd Input Offset Voltage Change with Power Dissipation Vos Input IBIAS Input Bias Current RS S 10kn, Pd < lW 500 250 nA lOS Input Offset Current RS S 10kn, Pd < lW 200 100 nA AYOL Large Signal Voltage Gain VCMR CMRR Off~t Voltage Input Voltage Range Mtd. on Wakefield 403 Heat Sink 4 (Typ.) RS S 10kn, Pd < 1W RL -10n, , Vo > 2/3 VSUPPL Y Typical 1 -6 6 100 (Typ.) -3 0.7 2 (Typ.) mV/W 3 mV 100 (Typ.) -10 +10 dB -10 +10 V Common Mode Rejection Ratio Rs·l0kn 70 (Typ.) 70 (Typ.) dB PSRR Power Supply Rejection Ratio RS= 10n 77 (Typ.) 77 (Typ.) dB SR Slew 'Rate CL = 30pF, Ay = 1, RL=10n Vo ~ 2/3 VSUPP ,RL=10n, Ay=10 0.5 (Typ.) 0.5 (Typ.) VII'S ±1.25 tiVo Output Voltage Swing 10 Output Current RL-5n, Ay=10 IQ Power Supply Quiescent Current RL =00, OPERATING CHA,RACTERISTICS (continued) TA Input Offset Voltage Pd > RL. VIN RIN RL This circuit allows 'precisely set motor drive current with op. amp. feedback accuracy. If RIN = RF = 1kn, and I":" L ______ J -15V 08020601 Figure 9 IL RL = 10n, then - = -0.1' AmpslVolt, and if RL = 1n VIN (use 4W or more). and RF = RIN = 1kn, IL 1 Amp -=-1x1 = - . - . VIN Volt thus if VIN = 1.5V. 1.5 amps will flow thru the motor. Since one side of the motor will. have a 1.5\{ drop (with respect to GND), the Vo point will go to 13.5V and develop 12V acrOS$ motor. HEAT SINK INFORMATION Heat sinks are available from Intersil. Order part number 29-0305 ($10.00 ea.) with a R6HA = 1.3°C/watt. A convenient mating connector is also available. Order part number 29-0306 ($4.50 ea.). NOTE: This product contains Beryllia. If used in an application. where the package integrity may be breached and the internal parts crushed or machined. avoid inhalation of the dust. 4-22 Note: All typical values have been guaranteed by characterization. and are not tested.. , ICL7605/ICL7606 Commutating Auto-Zero (CAZ) Instrumentation Amplifier GENERAL DESCRIPTION FEATURES The ICL7605/1CL7606 CMOS commutating auto-zero (CAZ) instrumentation amplifiers are designed to replace most of today's hybrid or monolithic instrumentation amplifiers, for low frequency applications from DC to 10Hz. This is made possible by the unique construction of this new Intersil device, which takes an entirely new design approach to low frequency amplifiers. Unlike conventional amplifier designs, which employ three op-amps and require ultra-high accuracy in resistor tracking and matching, the CAZ instrumentation amplifier requires no trimming except for gain. The key features of the CAZ principle involve automatic compensation for longterm drift phenomena and temperature effects, and a flying capacitor input. The ICL7605/1CL7606 consist of two analog sectionsa unity gain differential to single-ended voltage converter and a CAZ op amp. The first section senses the differential input and applies it to the CAZ amp section. This section consists of an operational amplifier circuit which continuously corrects itself for input voltage errors, such as input offset voltage, temperature effects, and long term drift. The ICL760511CL7606 is intended for low-frequency operation in applications such as strain gauge amplifiers which require voltage gains from 1 to 1000 and bandwidths from DC to 10Hz. Since the CAZ amp automatically corrects itself for internal errors, the only periodic adjustment required is that of gain, which is established by two external resistors. This, combined with extremely low offset and temperature coefficient figures, makes the CAZ instrumentation amplifier very desirable for operation in severe environments (temperature, humidity, toxicity, radiation, etc.) where equipment service is difficult. • • • • • • • • • Exceptionally Low Input Offset Voltage - 2jl.V Low Long Term Input Offset Voltage DrlftO.2jl.V/Year Low Input Offset Voltage Temperature Coefficient - O.05jl.V rc Wide Common Mode Input Voltage Range - O.3V Above Supply Rail High Common Mode Rejection Ratio-100 dB Operates at Supply Voltages As Low As ±2V Short Circuit Protection On Outputs for ±5V Operation Static-Protected I",puts - No Special Handling Required Compensated (ICL7605) or Uncompensated (ICL7606) Versions AZ -iNPUT -oIFF IN +DIFFIN C3 Co C, C, DR osc v+ (outline cIwg JNI COO14701 Figure 1: Pin Configuration ORDERING INFORMATION Order parts by the following part numbers' PART NUMBER ICL7605CJN ICL76051JN ICL7605MJN ICL7605/D ICL7606CJN ICL76061JN ICL7606MJN ICL7606/D COMPENSATION TEMPERATURE RANGE O·C to +70·C -25·C to + 85·C -S5·C to + 125·C INTERNAL INTERNAL INTERNAL INTERNAL EXTERNAL EXTERNAL EXTERNAL EXTERNAL - O·C to +70·C -25·C to + 85·C -55·C to + 125·C - PACKAGE 18-PIN CERDIP 18-PIN CERDIP 18-PIN CERDIP DICE" 18-PIN CERDIP 18-PIN CERDIP 18-PIN CERDIP DICE" "Parameter MiniMax Limits guaranteed at 2S·C only for DICE orders. 4-23 Note: All typical values have been guaranteed by characterization and are not tested. 301681-002 II ·1 ICJ.,7895/ICL.7808 !:i !:! y+ 10 g !:iu - +01" IN -DIFF IN OUTPUt AZ -INPUT LSOO6901 Figure 2: Symbol r'i I CAZ OP AMP INPUT AZ ANALOG SWITCH SECTION DIFFERENTIAL TO SINGLE ENDED VOLTAGE CONVERTER ANALOG SWITCH SECTION DIFFIN BIAS ~ + ~l RFI R" ~ I CAZ OP AMP OUTPUT ANALOG SWITCH SECTION ::;:-.... 1 C, ~ r- I AZ INPUT i t t oC 0 , LEVEL TRANSLATORS 2 OSC ---o.OUTPUT I ! RC OSCILLATOR I JR DIVISION RATIO I ! LEVEL I TRANSLATORS f STABILIZED POWER SUPPLY 1 '20R .32 DIVIDER NETWORK V· I I i V 80006101 Figure 3: Functional Diagram 4-24 Note: All typical values have beEm guaranteed by characterization and are not tested. .O~O[l ICL7605/ICL7606 !CIt ABSOLUTE MAXIMUM RATINGS Total Supply Voltage (V+ to V-) ........................ 18V DR Input Voltage ................... (V+ -8) to (V+ +0.3)V Input Voltage (C1, C2, Ca, C4 +DIFF IN, -DIFF IN, -INPUT, BIAS, OSC), (Note 1) ......................... (V- -0.3) to (V+ +0.3)V Differential Input Voltage (+ DIFF IN to -DIFF IN) (Note 2) ......................... (V- -0.3) to (V+ +0.3)V Duration of Output Short Circuit (Note 3) ........ Unlimited Continuous Total Power Dissipation (Note 4) ..... 500mW Operating Temperature Range: . ICL7605/1CL7606CJN ..................... 0 to + 70°C ICL760511CL76061JN ............... -25°C to +85°C ICL7605I1CL7606MJN ............ -55°C to +125°C Storage Temperature Range ............ -65°C to + 150°C Lead Temperature (Soldering, 10sec) ................. 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating cond~ions for extended periods may affect device reliabil~. Note 1: Due to the SCR structure inherent in all CMOS devices, exceeding these limits may cause destructive latch up. For this reason, it is recommended that no inputs from sources operating on a separate power supply be applied to the 7605/6 before its own power supply is established, and that when using multiple supplies, the supply for the 7605/6 should be turned on first. Note 2: No restrictions are placed on the differential input voltages on either the + DIFF IN or - DIFF IN inputs so long as these voltages do not exceed the power supply voltages by more than 0.3V. Note 3: The outputs may be shorted to ground (GND) or to either supply (V + or V~). Temperatures and/or supply voltages must be limited to insure that the dissipation ratings are not exceeded. Note 4: For operation above 25°C ambient temperature, derate 4mW/oC from 500mW above 25°C. ELECTRICAL CHARACTERISTICS Test Conditions: SYMBOL Vos v+ = +5V, v- = -5V, TA = +25°C, DR pin connected to V+ (fCOM~160Hz, fCOMl ~80Hz), Cl = C2 = Ca = C4 = 1j.1F, Test Circuit 1 unless otherwise specified. PARAMETER Input Offset Voltage TEST CONDITIONS RsS lkn MIL version over temp. AVOS/AT Average Input Offset Voltage Temperature Coefficient (Note 5) Low or Med Bias Settings AVos/At Long Term Input Offset Voltage Stability Low or Med Bias Settings CMVR Common Mode Input Range CMRR Common Mode Rejection Ratio PSRR Power Supply Rejection Ratio -IBIAS -INPUT Bias Current en(P'P) Equivalent Input Noise Voltage peak·to·peak P ... Low Med High Med VALUE MIN Bias Setting Bias Setting Bias Setting Bias Setting TYP MAX ±2 ±2 ±7 ±5 0.01 0.01 0.05 -55°C> TA > +25°C +25°C > TA > +B5°C + 25°C> TA > + 125°C ,.v ±20 ,.V ,.V ,.V 0.2 0.2 0.2 ,.vrc ,.vrc ,.vrc 0.5 -5.3 ,.V/Year +5.3 Case = 0, DR connected to V +, Ca = C4 = I,.F Cose = I,.F, DR connected to GND, Ca = C4 = I,.F COSC = I,.F, DR connected to GND, Ca = C4 = 10,.F 94 100 104 Any bias setting, fc = 160Hz (Includes charge injection currents) 0.15 Low Bias Mode Med Bias Mode High Bias Mode All Bias Modes en Equivalent Input Noise vollege Band Width 0.1 to 1.0Hz AVOl Open Loop Voltage Gain Rl=10kn ±VO Maximum Output Voltage Swing Rl = lMn Rl = l00kn Rl = 10kn Low Bias Setting Med Bias Setting High Bias Setting Positive Swing Negative Swing GBW Bandwidth of Input Voltage Translator Ca = C4 = I,.F All Bias Modes fCOM Nominal Commutation Frequency Cose- O fCOM1 Nominal Input Converter Commutation Frequency Casc=O VBH VBM VBl Bias Voltage required to set Quiescent Current Low Bias Setting Med Bias Setting High Bias Setting IBIAS Bias (Pin 8) Input Current 90 90 80 V dB dB dB dB 110 Band Width 0.1 to 10Hz UNIT 1.5 nA 4.0 4.0 5.0 ,.V ,.V ,.V 1.7 ,.V 105 105 100 dB dB dB ±4.9 ±4.8 V V V V +4.4 -4.5 10 Hz DR Connected to V + DR Connected to GND 160 2560 Hz Hz DR Connected to V + DR Connected to GND 80 1280 V+ GND Hz Hz y+ -0.3 y- +1.4 Y- -0.3 Y- ±30 4-25 Note: All typical values have been guaranteed by characterization and are not tested. V+ + 0.3 V+ -1.4 V- +0.3 V V V pA P c: - 2 _ .D~DIl !cp ICL7805/ICL7808 a:::. I i ELECTRICAL CHARACTERISTICS (CO NT.) VALUE SYMBOL TEST CONDITIONS PARAMETER UNIT MIN :s YOR :s Y + + 0.3 lOR Division Ratio Input Current y+ -S.O YDRH VORL DR Yoltage require"+1 S~ .:.r -2 ~~0: -3 I\, ~INJi..TING ...... 1000. -5 1000 100 0P618401 ffi 5 .a 4 0: 0: t iil j"-... ....... v+·y- = 10 VOLTS NO LOAD NO INPUT 3 -r- MED BIAS o 10k LOBIAS LOBIAS -50 -25 ~ :a OP018601 "l'oo.. losc - 5.2 k~Z r Fo, Cose ~ 0 pF lk I'-... ~ - 0: ~ r>.. ::1100 -- ~ 10 0 ZS 50 75 100 lZS TA • AMBIENT TEMPERATuRE"C 1 10' 100 0P018eQI FREQUENCY RESPONSE OF THE 10Hz LOW PASS FILTER USED TO MEASURE NOISE (TEST CIRCUIT 2), AMPLITUDE RESPONSE OF THE INPUT DIFFERENTIAL TO SINGLE ENDED VOLTAGE CONVERTER ~ TA - +25°C (V-,V-) = 5 VOLTS C, = C2 = C3 = C. = 1~P. .a " h~!D=B,:Hz 0 I _T~=lzslJ \ \ ~ I II I ~l' I ~IASIN "- : ,REGION 10 1000 COSC· OSCILLATOR CAPACITANCE· pF 0P018701' "- 100 1,000 T TA = 25"C ~ < IV+·V 1< 10 VOLT.S= ~ ........ 2 .-. 246 8 W U " ~ ,Y+.V-, • SUPPLY VOLTAGE· VOLTS OP018S01 % HI'I~ MED BIAS OSCILLATOR FREQUENCY AS A FUNCTION OF EXTERNAL CAPACITIVE LOADING N -J. o lOOk lk 10k RL • LOAD RESISTANCE SUPPLY CURRENT AS A FUNCTION OF TEMPERATURE 6 ~ ... -4 INPUT CURRENT ICOM· COMMUTATION FREQUENCY· Hz ... TA = ZSOC NO LOADNO INPUT TA = ZSoC fIV+ ·V-, = 10V RL C NNECTED TO GND_ ~ ~~-1 100 1 ......HIBIAS " 1/ 0 I!: 0 I) 1/ ~ 10 >+4 J \ V j~-I00 1-50 I II - -+5 I I ~ti-400 t=~-350 0:0: SUPPLY CURRENT AS A FUNCTION OF SUPPLY VOLTAGE 1\ "- , 1\ 10,GOO 2 345 .10 20 304050 100 I • FREQUENCY· Hz I - FREQUENCY - Hz QP018901 QP019001 4-27 Note: All typical values have been guaranteed by characterization and are not tested. INPUT' GND OR VOLTAGE 1 AZ -DIFF IN 11 ,.-----10 -IN +DIFF IN 17 .,e., +DIFFIN BETWEEN (V- +0.3) AND (V- -iI.3) VOLT 1~F 'C. rI I -DrFF IN -1 I I OUTPUT I S~2 6C. 7V- IBIAS OSCll • OUTPUT V- ,. +5V 90006201 Figure 6: Simplified Block Diagram OUTPUT 1M 1K VOLTAGE GAIN = 1000 The ICL760S/ICL7606 have approximately constant equivalent input noise VOltage, CMRR, PSRR, input offset voltage and drift values independent of the gain configuration. By comparison, hybrid-type modules which use the traditional three op. amp configuration have relatively poor performance at low gain (1 to 100) with improved performance above a gain of 100. The only major limitation of the ICL760SIICL7606 is its low-frequency operation.(10 to 20Hz maximum). However in many applications bandVliidth is not the most important parameter. TC024911 Figure 4: Test Circuit 1 CAZ Op Amp Section VOUT Operation of the CAl op-amp section of the ICL760S/ ICL7606 is best iII!Jstrated by referring. to Figure 7. The basic amplifier configuration; represented by the large triangles,. has one more input than does a regular op ampthe AZ; or auto-zero terminal. The voltage on the AZ input is that level at which each of the internal op amps will be auto-zeroed. In Mo<;le A, op amp # 2 is connected in a unity gain mode through on-chip analog switches. It charges external capacitor C2 to a voltage equal to the DC input offset voltage of the amplifier plus the instantaneous lowfrequency. noise voltage. A short time later, the analog switches reconnect the on-chip op amps to the configuration shown in Mode B. In this mode, op amp #2 has capacitor C2 (which is charged to a voltage equal to the offset and noise voltage of op amp #2) connected in series to its non-inverting ( + ) input in such a manner as to null out the input offset and noise voltages of the amplifier. While one of the on-chip op amps is processing the input Signal, the second op amp is in an auto"zero mode, charging a capacitor to a voltage equal to its equivalent DC and low frequency error voltage. The on~chip amplifiers are connected and reconnected at a nite designated as the commutation frequency (feOM), so that at all times one or the other of the on-chip op amps is processing the input Signal, while the voltages on capaCitors Cl and C2 are being updated to compensate for variables such as low frequency noise voltage arid input offset voltage changes due to temperature, drift or supply voltages effects. ,TC025011 Figure 5: Test Circuit 2 DC to 10Hz Unity Gain Low Pass Filter DETAILED DESCRIPTION CAZ Instrumentation Amp Overview The CAZ instrumentation amplifier operates on principles which are very' different from thoSe of the conventional three op-amp deSigns, which must use ultra-precise trimmed resistor networks in order to achieve acceptable accuracy. An important advantage of the ICL760SIICL7606 CAZ instrumenta~ion amp is the provision ·for self-compensation of internal error voltages, whether they are derived from steady-state conditions, such as temperature and .supply voltage fluctuations, or are du~ to long term drift. The CAl instrumentation amplifier is constructed with monolithic CMOS technology, and consists of three distinct sections, two analog and one digital. The two analog sections - a differential to single-ended voltage converter, and a CAZ op amp - have on-chip analog switches to steer the input Signal. The analog switches are driven from a self-contained digital section which consists of an RC oscillator, a programmable divider, and associated voltage translators. A functional layout of the ICL760SIICL7606 is shown in Figure 6. 4-28 Note: All typical values have bean guaranteed by characterization and are not tested. ICL7605/ICL7606 ~ ________~~O~UTPUT .v-r__________~~O~UTPUT 80006301 Figure 7: Diagrammatic representation of the 2 half cycles of operation of the CAZ OP AMP. c, -+------......-------t c, -+-+-----; INFUT FROMFIQ4 AZ OUTPUT NPUT .. (100k!l) -INPUT - - - - ' - - - - ' - - - ' ~ (C._TATION FREQUENCY) er CL DS017401 Figure 8: Schematic of analog switches connecting each Internal OP AMP . to Its inputs and output. 4-29 Note: All tvDical values have been auaranteed bv characterization and are not tested. I ··.D~Dll ICL1605/1CL7606 !:i S:! ! .. r--~-GND -DlFf' IN OR 'REFERENCE VOLTAGE _-+-.... s, '---1 '1M fNquencf.1 wNch ..... A I 8 .... cycled " known .. .... INPUT COMMUTATION FREQUENCV {So '--DS[).17501 Figure 9: Schematic of the differential. to single ended voltage. converter reference voltage to the input of the CAZ instrumentation amp. The output signal of this configuration is shown in Figure 10, where the voltage steps equal the differential voltage (VA-VB) at commutation times a, b, c, etc. The output waveform thus represents all information contained in the input signal from DC up to the commutation frequency, including commutation and noise voltages. Sampling theory states that to preserve the information to be processed, at least, two samples must be taken within a period (1/f) of the highest frequency being sampled. Consequently this scheme preserves information up to the commutation frequency. Above the commutation· frequency, the input signal is translated to a lower frequency. This phenomenon is known as aliasing. Although the output responds to inputs above the commutation frequency, the frequencies of the output responses will be below the commutation frequency. Compared to the standard bipolar or FET input op amps, the CAZ amp scheme demonstrates a number of important .advantages: Effective input offset voltages can be reduced from 1000 to 10,000 times without trimming. Long-term offset voltage drift phenomena can be compensated and dramatically reduced. Thermal effects can be compensated for over a wide operating temperature range. Reductions can be as much as 100 times or better. Supply voltage sensitivity is reduced. CMOS processing is ideally suited to implement the CAZ amp structure. The digital section is easily fabricated, and the transmission gates (analog switches) which connect the on-chip op amps can be constructed for minimum charge injection and the widest operating voltage range. The analog section, which includes the on-chip op amps, contributes performance figures which are similar to bipolar or FET input designs. The CMOS structure provides the CAZ op-amp with open-loop gains of greater than 100dS, typical input offset voltages of ±5mV, and ultra-low leakage currents, typically 1pA. The CMOS transmission gates connect the on-chip op amps to external input and output terminals, as shown in Figure 8. Here, one op amp and its associated analog switches are required to connect each on-chip op amp, so that at any time three switches are open and three switches are closed. Each analog switch consists of a P-channel transistor in parallel with an N-channel transistor. t---1-__ OUTPUT VOLTAGE --~~--1---J.,1 GNDOR -lREFERENCE VOLTAGE INPUT COMMUTATION PERtOD (1IfCOM1) DIFFERENTIAL-TO-SINGLE-ENDED UNITY GAIN VOLTAGE CONVERTER WF014201 Figure 10: Input to Output Voltage waveforms from the differential to single ended voltage converter. For additional information, see frequency characteristics in Amplitude Response of the Input Differential to single ended voltage converter graph on page 5. An idealized schematic of the voltage converter block is shown in Figure 9. The mode of operation is quite simple, involving two capacitors and eight switches. The switches are arranged so that four are open and four are closed. The four conducting switches connect one of the capacitors across the differential input, and the other from a ground or 4-30 Note: All typical values have been guaranteed by characterization and are not tested. ICL7605/ICL7606 'AZ -DIFF IN 10 , - - - - i . -IN ...OIFF IN 17 3C<$ :g; CJ'6 C,13 7 V- DR12 • BIAS 9 ,. ICl7606 g~~: 6 C2 11 '2 OSC11 OUTPUT V' y'10 ,." ,. 15 10k!! 1M!! At 1.5Hz At + A2 Av = -R-,- = 101 TIMES ,. 17 LOW PASS FILTER I . o.'~F 19 _ 20 OSC 140 OSC 2" OSC 3" TEST" REF HI" REF LO" C REF" C REF" COMM" IN HI31 IN LO" AZ" . BUFF" .... lOOk V· V- • INT27 V· .. ICL7I06 " 22 21 -::- } LCD DISPLAY AF028201 Figure 11: 3·1/2 Digit Digital Readout Torque Wrench The vOltage converter is fabricated with CMOS analog switches, which contain a parallel combination of P-channel and N-channel transistors. The switches have a finite ON impedances of 30kn, plus parasitic capacitances to the substrate: Because of the charge injection effects which appear at both the switches and the output of the voltage converter, the values of capacitors .C3 and C4 must be about 1j.lF to preserve signal translation accuracies to 0.01%. The 1j.lF capacitors, coupled with the 30kn equivalent impedance of the switches, produce a low-pass filter response from the voltage converter which is down approximately 3dB at 10Hz. the AID. In order to set the full-scale reading, a value of gain for the ICL7S05/1CL7S0S instrumentation CAZ amp must be selected along with an appropriate value for the rEiference voltage. The gain should be set so that at full scale, the output will swing about 0.5V. The reference voltage required is about one-half the. maximum output swing, or approximately 0.25V. In this type of system, only one adjustment is required. Either the amplifier gain or the reference voltage' must be varied for full-scale adjustment. Total current consumption of all Circuitry, less the current through the strain .ga\lge bridge, is typically 2mA. The accuracy is limited only by resistor ratios and the transducer. APPLICATIONS Using the ICL760511CL7606 to Build a Digital Readout Torque Wrench SOME HELPFUL HINTS Testing the ICL7605/1CL7606 CAZ Instrumentation Amplifier A typical application for the ICL7S05/1CL7S0S is in a strain gauge system, such as the digital readout torque wrench circuit shown in Figure S. In this application, the CAZ instrumentation amplifier is used as a preamplifier, taking the differential voltage of the bridge and converting it to a single-ended voltage referenced to ground. The signal is then amplified by the CAZ instrumentation amplifier and applied to the input of a 3-1/2 digit dual-slope AID converter which drives the LCD panel meter display. The AID converter device used in this instance is the Intersil ICL71 OS. In the digital readout torque wrench circuit, the reference voltage for the ICL710S is derived from the stimulus applied to the strain gauge, to utilize the ratiometric capabilities of Figure 4 and 5 (Test Circuits) provide a convenient means of·· measuring most of the important electrical parameters of the CAZ instrumentation amp. The output signal can be viewed on an oscnloscope after being fed through a low-pass filter. It is recommended that for most applications,a low-pass filter of about 1.0 to 1.5Hz be used to reduce the peak-to-peak noise to about the same level as the input offset voltage. . The output low-pass filter must be a high-input impedance RCtype - not simply a capaCitor across the feedback resistor R2. Resistor and capacitor-values of about 100kn and 1.0j.lF are necessary so that the output load impedance on the CAZ op-amp is greater than 100kn. 4--31 Note: All typical values have been guaranteed by characterization and are not tasted. EI ~ IID~Oll IICL1605tlCL7606 ;;.;, 51! ! 'a GND~ ____ ~ ______ ~ ____ ~r- ____ A.f\ ~ INPUT AC R,ouReE WAVEFORMS OUTPUT VOLTAGE WF014401 WF014301 Figure 12: Effect of a load capacitor on output voltage waveforms. 'Bias Control capacitor produces an area error in the output waveform, and hence an effective gain error. The output low-pass filter must be of a high-impedance type to avoid these area errors. For example, a 1.SHz filter will require a 100kn resistor and a 1.0pF capacitor, or a 1Mn resistor and an 0.1 pF capacitor. The on-chip op amps consume over 90% of the power required by the ICL760~/ICL7606. For this reason, the internal op amps have eXternally~ programmable bias levels. These levels are,set by cOnnecting the elAS terminal to either V + , GND, or V-, for lOW, MEQ or HIGH BIAS levels, respectively. The difference between each "bias setting is about a factor of 3, allowing a 9:1 ratio of quiescent supply current versus bias setting. This current programmability provides the user with a choice of device power dissipation levels, slew rates (the higher the slew rate, the better the recovery from commutation spikes), and offset errors due to "IR" Voltage drops and thermoelectric effects (the higher the power dissipation, the higher the input offset error). In most cases, the medium bias (MED BIAS) setting will be found to be the best choice. Oscillator and Digital Circuitry Considerations The oscillator has been designed to run free at about S.2kHz when the OSC terminal is open circuit. If the full divider network is used, this will result in a nominal commutation frequency of approximately 160Hz. The commutation frequency is that frequency at which the on-chip op amps are switched between the signal processing and the auto-zero modes. A 160Hz commutation frequency represents the best compromise between input offset voltage and low frequency noise. Other commutation frequencies may provide optimization of some parameters, but always at the expense of others. The oscillator has a very high output impedance, so that a load of only a few picofarads on the OSC terminal will cause a significant shift in frequency. It is therefore recommended that if the natural oscillator frequency is desired (S.2kHz) the terminal remains open circuit. In other instances, it may be desirable to synchronize the oscillator with an external clock source, or to run it at another frequency. The ICl760S/ICL7606 CAZ amp provides two degrees of flexibility in this respect. First, the DR (division ratiO) terminal allows a choice of either dividing the oscillator by 32 (DR terminal to V +) or by 2 (DR terminal to GND) to obtain the commutation frequency. Second, the oscillator may have its frequency lowered by the addition of an 8Idernal capacitor connected between the OSC terminal and the V + or system GND terminals; For situations which require that the commutation frequency be synchronized with a master clock, (Figure 13) the OSC terminal may be driven from TIL logic (with resistive pull-up) or by CMOS logic, provided that the V+ supply is +SV (±10.%) and the logic driver also operates from a similar voltage supply. The reason for this requirement is that the logic section (including the OSCillator) operates from an internal -SV supply, referenced to V+ supply, which is not accessible externally. Output Loading (Resistive) With a 10kn load, the output voltage swing can vary across nearly the entire supply voltage range, and the device can be used with I,oads as low as 2kn. However, with loads of less than SOkn, the on-chip op amps will begin to exhibit the characteristics of transconductance amplifiers, since their respective output impedances are nearly SOkn each. Thus the open-loop gain is 20dB less with a 2kn load than it would be with a 20kn load. Therefore, for high gain configurations requiring high accuracy, an output load of 100kn or more is suggested. There is another consideration in applying the CAZ instrumentation op amps which must not be overlooked. This is the additional power dissipation of the ,chip which will result from a large output voltage SWing into a low resistance load. This added power dissipation can affect the initial input offset voltages under certain conditions. Output Loading (Capacitive) , In many applications, it is desirable to include a low-pass filter at the output of the CAZ instrumentation op' amp to reduce' high-frequency noise outside the desired signal passband. An obvious solution when using a conventional op amp would be to place a capacitor across the external feedback resistor and thus produce a low-pass filter. However, with the CAZ op amp concept this is not possible because of the nature of the commutation spikes. These voltage spikes exhibit a low-impedance characteristic in the direction of the auto-zero voltage and a highimpedance characteristic on the recovery edge, as shown in Figure 12. It can be seen that the effect of a large load ThermoelectriC Effects The ultimate limitations to ultra-high-sensitivity DC amplifiers are due to thermoelectric, Peltier, or thermocouple effects in electrical junctions consisting of various metals, (alloys, silicon, etc.) Unless all junctions are at precisely the 4-32 Note: All typical values have been guaranteed by characterization and are not tested. ICL7605/ICL7606 same temperature, small thermoelectric voltages will be produced, generally about 0.1 /lV rc. However, these voltages can be several tens of microvolts per ·C for certain thermocouple materials. switching transients which occur at both the input and output terminals because of commutation effects. These transients have a frequency spectrum beginning at the commutation frequency, and including all of the higher harmonics of the commutation frequency. Assuming that the commutation frequency is higher than the highest inband frequency, then the commutation transients can be filtered out with a low-pass filter. The input commutation transients arise when each of the on-Chip op amps experiences a shift in voltage which is equal to the input offset voltages (about 5-10mV), usually occurring during the transition between the signal processing mode and the auto-zero mode. Since the input capacitances of the on-chip op-amps are typically in the 10pF range, and since it is desirable to reduce the effective input offset voltage about 10,000 times, the offset voltage autozero capaCitors C1 and C2 must have values of at least 10,000 x 10pF, or 0.1/lF each. The charge that is injected into the input of each op amp when being switched into the signal processing mode produces a rapidly-decaying voltage spike at the input, plus an equivalent DC input bias current averaged over a full cycle. This bias current is directly proportional to the commutation frequency, and in most instances will greatly exceed the inherent leakage currents of the input analog switches, which are typically 1.0pA at an ambient temperature of 25°C. The output waveform in Figure 4 (with no input signal) is shown in Figure 14. Note that the equivalent noise voltage is amplified 1000 times, and that due to the slew rate of the on-Chip op amp!!, the input transients of approximately 7mV are amplified by a factor of less than 1000. TTL OR CMOS LOGIC USE RL - 22k1l FOR TTL LOGIC (NOT NEEDED FOR CMOS) LC008101 Figure 13: ICL7605 being c::locked from external logic into the oscillator terminal. In order to realize the extremely low offset voltages which the CAZ op amp can produce, it is necessary to take precautions to avoid temperature gradients. All components should be enclosed to eliminate air movement across device surfaces. In addition, the supply vol.tages and power diSSipation should be kept to a minimum by use of the MED BIAS setting. Employ a high impedance load and keep the ICL7605/1CL7606 away from equipment which dissipates heat. Component Selection The four capacitors (C1 thru C4) should each be about 1.0/lF. These are relatively large values for non-electrolytic capacitors, but since the voltages stored on them change significantly, problerils of dielectric absorption, charge bleed-off and the like are as significant as they would be for integrating dual-slope AID converter applications. Polypropylene types are the best for Ca and C4,although Mylar may be adequate for C1 and C2' Excellent results have been obtained for commercial temperature ranges using several of the less-expensive, smaller-size capaCitors, since the absolute values of the capacitors are not critical. Even polarized electrolytic capaCitors rated at 1.0/lF and 50V have been used successfully at room temperature, although no recommendations are made concerning the use of such capaCitors. OUTPUT VOLTAGE WF014511 Figure 14: Output waveform from Test Circuit 1. Layout Considerations Care should be exercised in positioning components on the PC board particularly the capaCitors C1, C2, Ca and C4, which must all be shielded from the asc terminal. Also, parasitic PC board leakage capacitances associated with these four capaCitors should be kept as low as possible to minimize charge injection effects. Commutation Voltage Transient Effects Although in most respects the CAZ instrumentation amplifier resembles a conventional op amp, its prinCipal applications will be in very low level, low-frequency preamplifiers limited to DC through 10Hz. The is due to the finite 4-33 Note: All typical values have been guaranteed by characterization and are not tested. = ICL76XX ~ ICL76XX, Series Low Power ~ CMOS Operational Amplifiers GENERAL DESCRIPTION FEATURES The ICL761X1762X1763X1764X series is a family of monolithic CMOS operational amplifiers. These. devices provide the designer with high performance operation at low supply voltages and selectable quiescent currents, and are an ideal design tool when ultra low input current and low power dissipation are desired. The basic amplifier ~iII operate at supply voltages ranging from ± 1.0V to ±av, and may be operated from a single Lithium cell. A unique quiescent current programming pin allows settingof.standby current to 1mA, 100,..A, or 10,..A, with no external components. This results in power consumption as low as 201lW. Output swings range to within a few millivolts of the supply voltages. Of particular significance is the extremely low (1 pAl input and 1012n input current, input noise current of .01 pAl impedance.. These features optimize Performance in very high source impedance applications. The inputs are internally protected and require no special handling procedures. Outputs are fully protected against short circuits to ground or to either supply. AC performance is excellent, with a slew rate of 1.6V/ /lS, and unity gain bandwidth of 1MHz at IQ 1mAo Because ot the low power dissipation, operating temperatUres and drift are quite low. Applications utilizing these features may include stable instruments, extended life designs, or high density packages. • • • • • • • • • • Wide Operating Voltage Range ±1.0V to ±8V High Input Impedance - 1012n Programmable Power Consumption - Low As 20llW Input current Lower Than BIFETs-Typ 1pA Available As Singles, Dlj8ls, Triples, and Quads Output Voltage Swings to Within Millivolts Of Vand V+ Low Power Replacement for Many Standard· Op Amps Compensated and Uncompensated Versions Inputs Protected to ±200V (lCL7613/15) Input Common Mode Voltage Range Greater Than Supply RaUs (ICL7612) APPLICATIONS YHz, • • • • • • Portable Instruments Telephone Headsets Hearing Aid/Microphone Amplifiers Meter Amplifiers Medical Instruments High Impedance Bu·ffers = SELECTION GUIDE DEVICE. NOMi:NCLATURE. ICL76XX X x SPECIAL FEATURE CODES xx C E H I L M .L Package Code TV - TO-99, B pin PA - Plastic B pin Minidip PO - 14 pin Plastic Dip PE - 16 pin Plastic Dip JO - 14 pin CERDIP JE - 16 pin CEROIP 10 - Dice L . -_ _ Temperature Range C ~ O"C to 70"C M = -55"C to + 125"C ' - - - - - - V o s Selection A=2mV B=5mV C= 10mV 0= 15mV E = 20mV o P V 4-34 Note: All typical values have been guaranteed by characterization and are not tested. = = = = = = = = INTERNALLY COMPENSATED EXTERNALLY COMPENSATED HIGH QUIESCENT CURRENT (1 mAl INPUT PROTECTED TO ±200V LOW QUIESCENT CURRENT (10jlA) MEDIUM QUIESCENT CURRENT (100jlA) OFFSET NULL CAPABILITY PROGRAMMABLE QUIESCENT CURRENT EXTENDED CMVR 302060-002 ICL76XX ORDERING INFORMATION NUMBER OF OP-AMPS IN PACKAGE,AND SPECIAL FEATURES (SEE ABOVE) BASIC PART NUMBER ICL7611 ICL7612 ICL7613 ICL7614 ICL7615 SINGLE OP-AMP: C, 0, P C, 0, P, V C, I, 0, P E, M, 0 E, I, M, 0 ICL7621 DUAL OP-AMP: C, M ICL7622 DUAL OP-AMP: C, M,O ICL7631 ICL7632 TRIPLE OP-AMP: C, P P(3) ICL7641 ICL7642 QUAD OP-AMP: C, H C, L PACKAGE TYPE AND SUFFIX a-LEAD TO-99 a-PIN MINIDIP a-PIN SOIC PLASTIC DIP (1) O·C to +70·C O·C to +70·C -55·C to + 125·C O·C to +70·C O·C to +70·C ACTV BCTV DCTV AMTV BMTV ACPA BCPA DCPA DCPA DCBA ACTV BCTV DCTV AMTV BMTV ACPA BCPA DCPA CERAMIC DIP (1) O·C to +70·C -55·C to + 125·C DICE DID DID ACPD BCPD DCPD ACJD BCJD DCJD AMJD BMJD CCPE ECPE CCJE ECJE CMJE CCPD ECPD CCJD ECJD CMJD DID E/D E/D NOTES: 1. Duals and quads are available in 14 pin DIP package, triples in 16 pin only. 2. Ordering code must consist of basic part number and package suffix, e.g., ICL7611 BCPA. 3. ICL7632 is not compensatable. Recommended for use in high gain circuits only. "Parameter MiniMax Limits guaranteed at 25·C only for DICE orders. DEVICE ICL7611XCPA ICL7611XCTV ICL7611XMTV ICL7612XCPA ICL7612XCTV ICL7612XMTV ICL7613XCPA ICL7613XCTV ICL7613XMTV DESCRIPTION Internal compensation, plus offset null capability and external 10 control PIN ASSIGNMENTS 8 PIN DIP (TOP VIEW) (outline dwg PAl TO-99 (TOP VIEW) (outline dwg TV) 10 SET OFFSET IQ SET -IN v+ +IN OUT QFFSET v• Pin 7 connected to case. 8 PIN DIP (TOP VIEW) (outline dwg SA) vFigure 1: Pin Configurations 4-35 Note: All typical values have been guaranteed by characterization and are not· tested. ICL76XX DEVICE ICL7614XCPA ICL7614XCTV ICL7614XMTV ICL7615XCPA ICL7615XCTV ICL7615XMTV DESCRIPTION PIN ASSIGNMENTS Fixed 10 (l00IlA), eX1ernal compensation, and offset null capability 8 PIN Dip (TOP VIEW) (outline dwg PAl TO·99 (TOP VIEW) (outline dwg TV) SOI~ COMP COMP OFFSET -IN y• • ,N OUT y. 'Pin 7 connected to ICL7621XCPA ICL7821XCTV ICL7621XMTV Dual op amps with internal compensation; 10 fixed at 10011A Pin compaptible willi Texas Inst. TL082 Motorola MC1458 Raytheon RC4558 case. • PIN DIP (TOP VIEW) (outline dwg PAl TO'99 (TOP VIEW) (outline dwg TV) y' OUT. -IN. +IN. y' OUT. -IN. +IN. y'Pin 8 connected to ICL7822XCPD case. 14 PIN OIP.(TOP VIEW) (outline dwgs JD, PO) Dual op amps with eX1ernal compensation and offset null capability; Ia fixed at 10011A Pin compatible with Texas Insl TL083 Fairchild 1lA747 OFFSET OFFSET. Y' OUT. N/C OUT. Y' OFFSET. 14 Nole: Pins 9 and 13 are internally connected. Figure 1: Pin Configurations (Cont.) 4-38 Note: All typical values have been guaranteed by characterization and are not tested. y. ICL76XX DEVICE ICL7631XCPE ICL7632XCPE DESCRIPTION PIN ASSIGNMENTS 16 PIN DIP (TOP VIEW) (outline dwgs JE, PEl Triple op amps with internal compensation (lCL7631) and no compensation (ICL7632). Adjustable 10 Same pin configuration as ICLB023. I.,. 100 SET y- SET 16 • -INa +fNa OUT. V+ 10(: -INe SET Note: pins 5 and 15 are internally connected. ICL7641XCPD ICL7642XCPD Quad op amps with internal compensation. 10 fixed at lmA (ICL7641) 10 fixed at 1011A (lCL7642) Pin compatible with Texas Instr. TLOB4 National LM324 Harris HM741 14 PIN DIP (TOP VIEW) (outline dwg JD, PO) OUTD -INo +INo V- +INc -INc OUTc 8 U • Figure 1: Pin Configurations (Cont.) 4-37 Note: AU typical values have been guaranteed by characterization and are not tested. +INc OU"",,T STAGE o ONPUT STAGE r--L---o . + ® >--_____.. OFFSET +INPUT .,CD ouv .. '. OUTPUT y- y' o ~INPUT y- r--- --.--- - - - - - - I j ! r TABLE OF JUMPERS leL 7611 ICL.7613 : :~~;:!:. 1 ! I ! 8. F, H B. F. H 8, r.H tel·J6l2 ICI..·7821 leL 7622 ICI..-7631 ICL·7632 ICl·7641 ICL·7642 .1' C.D. E C,D, E E E e. e. a.F," 8.F.H e.G A.E NOTES: oy·--"H....---- .A-" >- ~ i--' I 10 = l00"A 100 () ! ....- 10'" 10;,.A; 10 . .A"" '02 '-10' 'OpA '0 10 12 14 16 +25 +50 +75 FREE·AIR TEMPERATURE SUPPLY VOL T AGE - VOL 15 '000 I ".15 CD - RL:z 10K!! IQ""lmA '0 ~ 0 50 -25 +25 i!: I = - ~ ~ 90 ~ l!! lIS ~ ~> 80 IQ= l()Qs.1A • ~"""A 75 >- 'l ....... 70 65 -75 -so -25 '06 VSUpp·,OV r- ~A 0 +25 r-~~.,~ ~ 'o-'mA r--_~_ 102 r""'" , ~1S .. SO +15 qOQ +125 FREE-AIR TEMPERATURE - C -25 0 +50 +25 +75 +100 +125 0P016701 EQUIVALENT INPUT NOISE VOLTAGE AS A FUNCTION OF t~ 0:. 600 soo ~ > l!l0 400 ~ § g E 200 I!::\.I ' i I: .i '00 11:1 ' I !: ,~ , '0 :: T" ' r-... ,..... ,rv 12 '0 'K 'OK FREQUENCY - Hz - , 0P017001 CPO, .... 4-44 Note: All typicel values have been guaranteed by characterization and are not tested. ~ 1\ TAo • +2S'C I 'o"mA ---'o"OpA •..•• '0 -100"" , , , 1.\ ).\""\ v...,,,,., , \ i v..... o '00 i 'K ,2V . , ~ \ \ \ r,,__ r--,... , t?~'.: ~ I ""\ ~ II r'SV . r--_ )J ,. v.u,;;. .~ I !' '00 , '6 il :! rfFII:: · :I ++- ~ 3V " VsUPP " llV 300 I- I TA "' ....25 C i~! Z :i ~Illli ~.J"ill; Ii iI I- OP016801 PEAK-To-PEAK OUTPUT VOLTAGE AS A FUNCTION OF FREQUENCY FREQ~ENCY "~ ~ ...... -50 ....... ....... r-..... FREE·AlR TEMPERATURE _·C FREQUENCY - Hz ....... ....... +100 +125 OP016501 +75 +100 +125 ---- . - ~ r-.... +75 COMMON MODE REJECTION RATIO AS A FUNCTION OF FREE-AIR TEMPERATURE r- 15 ~~ +50 5 '0r--+-t--+-~~~~~ I ~ a: +26 FREE·AIR TEMPERATURE _·C 70 +50 VSUPP" lOV 96 -25 Co • ~r~~/~S CPO'66OI lo.',mA ,-60 ~ 1~F!~~~~-i--r--t--1 POWER SUPPLY REJECTION RATIO AS A FUNCTION OF FREE-AIR TEMPERATURE '00 ./ _oc TA" +25'C '00 f--+-+--+-4 FREE·AIR TEMPERATURE - C i I 2 o. I a 1/ 1.0 ~ Vsupp '" 10 VOL TS VOUT ., 8 VOL TS I -15 ~ ~ 1~f--+-~~~~-~-+~ I I / ii g~ 104 R L ,.. tOOK!! 'O"OOpA _ l- S > >, z ~ ~ +'00 +126 OP016301 ! v- --SVOLTS 100 a: r- , " tI -- I::!o. 'OOpA :ia: Y'-~5vdTS ~ -NQS'GNAL I ~ ::> ,0' '000 vi - y- ~ '0 vbLTS NOlDAD - r-1o = '.mA INPUT BI.AS CURRENT AS A FUNCTION OF TEMPERAT~RE 'OK ~\ ~ 'OOK 'M 10M FREOU~NCV - Hz OP017101 ICL76XX TYPICAL PERFORMANCE CHARACTERISTICS (CONT.) MAXIMUM PEAK·TO·PEAK OUTPUT VOLTAGE AS A FUNCTION OF SUPPLY VOLTAGE MAXIMUM PEAK·To-PEAK OUTPUT VOLTAGE AS A FUNCTION OF FREQUENCY > > 6 II • ! I 2 II \ 6 , I TA .. +125' 2 0 10K 10~ ~ '0 -Iii II I ~ [""'. a TA, := • ! I " I Ii! ~ lOOK RL = 2 I· ~'IPPl Y 14 0 1/ ,,. 1/ o.01 i , 10 -tOStA I I ! 10 12 14 16 0P017601 > '0'" lmA , 2 TA =.+25 C .< > l00pF INPUT c,. .... ... = l00KU lOOp' = +25 C • 0 > .... " S 0 \ 2 1--1--+--+-+ RL '"~ \ 0 6 " 10K!! 1\ J !oUTPUT , VSUPP ., TOV VSUPf' " lOV R, C, ......z 0 l\. 10 -2 ~ -, 12 -6 ~ 1 mA 20 40 TIME ~ 60 100 120 -"s OPQ19101 0P035801 4--45 Note: All typical values have been guaranteed by characterization and are not tested. 1/ V I 2 0.1 : 1.0 10 100 0P017701 VOLTAGE FOLLOWER LARGE SIGNAL PULSE RESPONSE VOLTAGE FOLLOWER LARGE SIGNAL PULSE RESPONSE a 6 = lQVOlTS TA ,,25 C LOAD RESISTANCE - K!! SUP:Pl y VOLTAGE - VOLTS OP017501 VOLTAGE FOLLOWER LARGE SIGNAL PULSE RESPONSE v· -V- 'V t:=- o 10 16 °c 0 a ! 10 -lOO/.1A Ie;; '~A= SUPPLY VOLTAGE - VOLTS ~ o +}5 +100 +125 2 6 " +50 MAXIMUM PEAK·To-PEAK OUTPUT VOLTAGE AS A FUNCTION OF LOAD RESISTANCE 10 1\ "12 ... 25 OP017401 .1-- .0 10 0 6 I I I -25 FREe.AIR TEMPERATURE _ ~ .1 1/1 l i 0 o-75 -so VOLTAGE - VOL T8 MAXIMUM OUTPUT SINK CURRENT AS A FUNCTION OF SUPPLY VOLTAGE 1---+-- 1/,", 16 0P017301 V 1/ i VSUPP' '" 10 VOL T5 1 10 = 1mA 12 10M MAXIMUM OUTPUTISOURCE CURRENT AS A FUNCTION OF SUPPLY VOLTAGE : i/ f""".. I I OP017201 I I 1'.... 2K!~ I 1M 40 Rl '" 10K!! .......... I ! FREQUENCV - Hz O~ !'--.. a TA "+25 C ;. I II I I ii Ii I ~-\ 30 I RL • TOOK!! 11 -55 C I J\. !\i\ 12 I Vwpp ' "lmA I I 0 MAXIMUM PEAK·To-PEAK VOLTAGE AS A FUNCTION OF FREE-NR TEMPERATURE =lCL78xX' a DETAILED DESCRIJ)TION Static Protection Input Offset Nulling All devices are static protected by the use ,of input diodes. However, strong static fields should be avoided, as it is pos~ible for the strQ,ng fields to cause degraded diode junction characteristics, which may result in increased input' ' leakage currents. For those models provided with OFFSET NULLING pins, nulling may be achieved by conne~ting a 25K pot between the OFFSET terminals with the wiper connected to V + . At quiescent currents of 1mA and 100pA,the nulling range provided is adequate for all Vas selections; however with 10 = 10pA, nulling may not be possible with higher values of Vas· Latchup Avoidance Frequency Compensation Junctioncisolated CMOS circuits employ configurations which produce a parasitic 4-layer (p-n-p-n) structure. The 4layer structure has characteristics similar to an SCR, and under certain circumstances may be triggered into a low impedance state resulting in excessive supply current. To avoid this condition, no voltage greater than 0.3V beyond the supply rails may be applied to any pin. (An exception to this rule concerns the inputs of the ICL7613 and ICL7615, which are protected to ±200V.) In general, the op-amp supplies must be established simultaneously with, or before any input signals are applied. If this i~ not posSible, the drive circuits must limit input current flow to 2mA to prevent latchup. The ICL7611/12/13, 7621/22, 7631, 7641/42 are internally compensated, and are stable for closed loop gains as low as unity with capacitive loads up to 100pF The ICL7614/15 are externally compensated by connecting a capacitor between the COMP and OUT pins. A 39pF capacitor is required for unity gain compensation; for greater than unity gain applications, increased bandwidth and slew rate can be obtained by redUCing the value of the compensating capacitor. Since the gm of the first stage is proportional to ViQ, greatest compensation is required when 10=1 mAo The ICL7632 is not compensated internally, nor can it be compensated externally. The device is stable when lIsed as follows: 10 of 1mA for gains ~ 20 10 of 100pA for gains ~ 10 10 of 10pA for gains ~ 5 Choosing the Proper IQ Each device in the ICL76XX family has a similar 10 set-up scheme, which allows the amplifier to be set to nominal quiescent currents to 10pA, 100pA or 1mA. These current settings change only very slightly over the entire supply voltage range. The ICL7611/12/13 and ICL7631/32 have an external 10 control terminal, permitting user selection of each amplifiers' quiescent current. (The ICL7614/15, 76211 22, and 7641/42 have fixed 10 settings - refer to selector guide for details.) To set the 10 of programmable versions, connect the 10 terminal as follows: High Voltage Input Protection The ICL7613 and 7615 include on-Chip thin film resistors and clamping diodes which allow voltages of up to ±200V to be applied to either input for an indefinite time without device failure. These devices will be useful where high common mode voltages, differential mode voltages, or high transients may be experienced. Such conditions may be found when interfacing separate systems with separate supplies. Unity gain stability is somewhat degraded with capacitive loads because of the high value of input resistors. 10 = 10pA -10 pin to V+ 10 = 100pA -.,. 19, pin to ground. If this is not possible; any -0.8 to V- + 0.8 can be used. voltage from V 10 = 1mA-IO pin to V- Extended Common Mode Input NOTE: The negative output current available is a function of the quiescent current setting. For maximum p-p output voltage swings into low impedance loads, 10 of 1mA should be selected. ~ange The ICL7612 incorporates additional processing which allows the input CMVR to exceed each power supply rail by 0.1 volt for applications where VSUpp ~ ±1.5V. For those applications where VSUpp S ±1.5V, the input CMVR is limited in the pOSitive direction, but may exceed the negative supply rail by 0.1 volt in the negative direction (eg. for VSUpp = ± 1.0V, the input CMVR would be + 0.6 volts to -1.1 volts). Output Stage and ,Load Driving Considerations Each amplifiers' quiescent current flows primarily in the output stage. This is approximately 70% of the 10 settings. This allows output swings to almost the supply rails for output loads of 1Mn, 100kn, and 10kn, using the output stage in a highly iinear class A mode. In this mode, crossover distortion is avoided and the voltage gain is maximized. However, the output stage can also be operated in Class AS for higher output currents. (See graphs under Typical Operating Characteristics). During the transition from Class A to Class S operation, the output transfer characteristic is non-linear and the voltage gain decreases. OPERATION AT VSUPP =±1.0 VOLTS Operation at Vsupp = ± 1.0V is guaranteed at 10 = 10pA only. This applies to those devices with selectable la, and devices that are set internally to 10 = 10pA (i.e., ICL7611, 7612, 7613, 7631; 7632, 7642). OutP!Jt swings to within a few millivolts of the supply rails are achievabl,e for RL ~ 1Mn. Guaranteed input CMVR is ±0.6V minimum and typically + 0.9V to -O.7V at VSUpp = ± 1.0V. For applications where greater common mode range is deSirable, refer to the description of ICL7612 above. A special feature of the output stage is that it approximates a transconductance amplifier, and its gain is directly proportional to load impedance. Approximately the same open loop gains are obtained at each of the 10 settings if corresponding loads of 10kn, 100kn, and 1Mn are used. The user is cautioned that, due to extremely high input impedances, care must be exercised in layout, construction, 4-46 Note: All typical values have been guaranteed by characterization and are not tested. ICL76XX board cleanliness, and supply filtering to avoid hum and noise pickup. APPLICATIONS Note that in no case is 10 shown. The value of 10 must be chosen by the designer with regard to frequency response and power dissipation. DUTYCVCLE _0 VIN-----!+' .....- - - - !>--~-- VOUT Since the output range swings exactly from rail to rail, frequently and duty cycle are virtually independent of power supply variations. Figure 6: Precise Triangle/Square Wave Generator AF028301 Figure 3: Simple Follower* 1M' .-".""'--.-VOH V,. V,N TO SUCCEEDING INPUT STAGE >---+-----f >---......- - - TO CMOS OR VOUT l00k~-_-I LPTTL LOGIC COMMON 1M AF028401 08017601 Figure 7: Averaging AC to DC Converter for A/D Converters Such as ICL71 06, 7107, 7109, 7116, 7117 ·By using the ICL7612 in these applications, the circuits will follow rail to rail inputs. Figure 4: Level Detector* 1M 100k.1% 5QOk,1% lOOk INPUT \loUT 1M, 1% > - -......- - - - V O U T . - - - - - -.... v+ o--"I'>I'Y-_--I 1M AF02B501 08017701 Note that AVOL = 25; single Ni-cad battery operation. Input current (from sensors connected to patient) limited to < 5iJ,A under fault conditions. "Low leakage currents allow integration times up to several hours. Figure 5: Photocurrent Integrator Figure 8: Medical Instrument Preamp 4-47 Note: All typical values have been guaranteed by characterization and are not tested. O,2! r-- ;:> O.1j,lF O.2~F 1M I L--ii-=_.J I 360Ic 'M • OUTPUT I L--H":-c.J AF028601 The low bias currents permit high resistance and low capacitance values )0 be used to achieve low frequency cutoff. fe = 10Hz, AVCL = 4, Passband ripple - O.ldB "Note that small capacitors (25-50pF) may be needed for stability in some cases. Figure 9: Fifth Order Chebyshev Multiple Feedback Low Pass Filter +8V 16k TA '" +125'C l60k 1.5k VOUT LCOO8401 NOTES: 1. For devices with external compensation, use 33pF. 2. For deVices with programmable standby current, connect 10 pin to V- (10 = 1mA mode). AF028701 Q Note that 10 on each amplifier may be different. AVCL = 10, = 100, fo -100Hz. Figure 10: Second Order Biquad Bandpass FiRer Figure 11: Burn-In and Life Test Circuit 4-48 Note: All typical values have been guaranteed by characterization and are riot tested, ICL76XX >----YOUT Y'N>----! I. l00pF .". AL .. 10k FOR '0 '" 1rnA lOOk FOR '0 • l00,.A 1M FOR 10 • lo,.A ·FOR ICL7614115 . LC0085QI Figure 13: Unity Gain Frequency Compensation Figure 12: Vos LCOO83OI Null Circuit 4-49 Note: All typical values have been guaranteed by characterization and are not tested. i D~U16 ICL7650 !:i .Chopper-Stabilized S! Operational Amplifier GENERAL DESCRIPTION FEATURES The ICL7650 chopper-stabilized amplifier is a highperformance device which offers exceptionally low offset voltage and input-bias parameters, combined with excellent bandwidth and speed characteristics. Intersil's unique CMOS approach to chopper-stabilized arnplifier design yields a versatile precision component that can replace more expensive hybrid or monolithic devices.· The chopper amplifier achieves its low offset by comparing the inverting and non-inverting input voltages in a nulling amplifier, null8d by alternate clock phases. Two eXternal capacitors are required to store the correcting potentials on the two amplifier nulling inputs; these are the only external components necessary. The clock oscillator and all the other control circuitry is entirely self-contained, however the 14-pin version includes a provision for the use of an external clock, if required for a particular application. In addition, the ICL7650 is internally compensated for unity-gain operation. • • • • • • • • • • Extremely Low Input Offset Voltage - 2ILV Low Long-Term and Temperature Drifts of Input Offset Voltage Low DC Input Bias Current - 10pA (20pA 7650B) Extremely High Gain, CMRR and PSRR - Min 120dB High Slew Rate - 2.5V1ILS Wide Bandwidth - 2MHz Unity-Gain Compensated Very Low Intermodulatlon Effects (Open Loop Phase Shift < 10·C @ Chopper Frequency) Clamp Circuit to Avoid Overload Recovery Problems and Allow Comparator Use Extremely Low Chopping Spikes at Input and Output ORDERING INFORMATION TEMPERATURE RANGE PACKAGE ICL76S0CPA-1 O·C to +70·C 8-PIN Plastic ICL7650BCPA-1 ICL7650CPD O·C to +70·C O·C to +70·C ICL7650BCPD O·C to +70·C ICL76S0CTV-1 O·C to +70·C PART ICL7650BCTV-1 TEMPERATURE RANGE PACKAGE ICL76S0lJD -2S·C to +8S·C 14-PIN CERDIP 8-PIN Plastic ICL76S0BIJD ICL76501TV-1 - 2S·C to + 8S·C -2S·C to + 8S·C 14-PIN CERDIP 14-PIN Plastic 14-PIN Plastic ICL7650BITV-1 -2S·C to +8S·C 8-PIN TO-99 8-PIN T0-99 ICL7650MJD - SS·C to + 12S·C 14-PIN CERDIP 14-PIN CERDIP PART 8-PIN T0-99 O·C to +70·C 8-PIN TO-99 ICL76S0BMJD - SS·C to + 12S·C ICL76S0IJA-1 - 2S·C to + 8S·C 8-PIN CERDIP ICL76S0MTV-1 -SS·C to + 12S·C a-PIN TO-99 ICL76S0BIJA-1 -2S·C to + 8S·C 8-PIN CERDIP ICL76S0BMTV-1 - SS·C to + 12S·C 8-PIN TO-99 CEXT:~ CeXTA Nc(GUA~: ~ 1• 14 : :~ ~+T eLK OUT 2 +IN ~ 5 10 6 • NC(GUAAD~ [ INJECT t3 EXT eLK IN ~ OUTPUT ~ OUTPUT CLAMP y": [""",_ _.....;:.""J CRETN 14· PIN DIP CEXT:U:· ..·· 7 y+ I CASE ~ ... cu< .. ~A.~K~ -IN 2 ---r--l...-' • OUTPUT +IN 3 ~. ~ ~c 5 OUTPUT CLAMP CR£'N(-') 8 LEAD TO· 99 80006411 c0015721 Figure 1: Functional Diagram Figure 2: Pin Configuration 4-50 Note: All typical values have been guaranteed by characterization. and are not tested. 302061-003 ICL7650 ABSOLUTE MAXIMUM RATINGS Total Supply Voltage (V+ to V-) ................... 18 Volts Input Voltage ................. (V + + 0.3) to (V- - 0.3) Volts Voltage on oscillator control pins ................. V+ to Vexcept EXT CLOCK IN: ... (V + + 0.3) to (V + - 6.0) Volts Duration of Output short circuit ..................... Indefinite Current into any pin ........................................ 10mA -while operating (Note 4) .............................. 100j.tA Cont. Total Power Dissipn (TA = 25·C) CERDIP Package ................................ 500mW Plastic Package .................................. 375mW TO-99 ............................................... 250mW Storage Temp. Range ....................... -65·C to 150·C Operating Temp. Range ........................... See Note 1 Lead Temperature (Soldering, 10sec) ................. 300·C Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and lunctional operation 01 the device at these or any other cond~ions above those indicated in the operational sections 01 the specHications is not implied. Exposure to absolute maximum rating conditions lor extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Test Conditions: V+ = +5V, = -5V, V- TA = +25·C, (unless otherwise specified) LIMITS 7650 SYMBOL PARAMETER UNIT MIN Input Offset Voltage Vos Average Temp. Coefficient AVos LIMITS 7650B TEST CONDITIONS TYP MAX MIN ±5 TYP MAX ±2 ±5 ±10.0 TA= + 25'C -25'C < TA < +85'C -55'Cut 'N~ise. VoltaQ'!.' in.' ,Input NoiSl! Current u~·,G.illri-' ~ildwidth GBW. ., tr V+ to'VISUpp Ich CMVR= -5V to +1.5 -5.0 -5.2 to +2.0 110 120 110 120 120 130 t20 130 Rs-l00n 1=0 to 10Hz I -10Hz ,. ±20 pA pA 5.0 AVOL SR, pV ±75 ±50 1.5 -5.0 -5.2 to +2.0 n I VIV V 1.5 V I ,I dB dB 2 2 0.Q1 0.01 2.0 2.0 pA/v'Hz MHz pVp.p 2.5 2.5 V/IJS 'RisJi> Ti"1e' 0.2 0.2 .Ov& +1 o -1 ~-+--+---+ -2 1--+--+- ----I----i---I • • 10 14 II VOLTS OP020001 l 211 5 0 ~ --I----i--"'1 TOTAL SUPPLY VOLTAGE - OUTPUT WITH· ZERO. INPUT; GAIN =1000;BAI:.ANCED SOURCE IMPEDANCE = 10KO INPUT OFFSET VOLTAGE VI. CHOPPING FREQUENCY INPUT OFFSET VOLTAGE CHANGE VI. SUPPLY VOLTAGE ~ 150 "C 0P019701 i .... I I 01 EACHSUPPLYVOLTAGE(+ AND-I I , I :t-+---+-:7fC-t-+-+-+-t I> \ , I. 211 I o 10 10k tk CHOPPING FlIIOuENcY CCLDCII.()U1) HI 0P02011 I 4-52 Note: All typical values have been guaranteed by characterlzalion and are not tested. 23 .. TlM.E~ .7 • • m. HT000021 ICL7850 TYPICAL PERFORMANCE CHARACTERISTICS (CO NT.) OPEN LOOP GAIN AND PHASE SHIFT VI. FREQUENCY ,.,,. OPEN LOOP GAIN AND PHASE SHIFT VI. FREQUENCY ,. I 1. " 10, "- "§. -tOO , ,'. I' I. • i" RL =, 10k.n. cDj • oj'''' Ut o.t 10 100 10 1 .t: ... , 1. I "- , "°1 I• .. ,.... :\.. 1. " V , ! • -I • • Cr .,'.O~f 100 ./ r---, f-~L = 10k.n. o.t Ut 1 k 10k tOOk tOO 10 10 'I"- 0 1. 10'1 ·i no I ~ ;" tk ,. if I" 10k 100k 'REQUENCY HI ,IIEGUiENCY ... 0PIJ20311 VOLTAGE FOLLOWER LARGE SIGNAL PULSE RESPONSE" i! IIIC ' !:i 0 ~ !; I ...... +2 ~+1 VOLTAGE FOLLOWER LARGE SIGNAL PULSE RESPONSE· ... 'I/;. J CLOCK OUT LOW, -1 I! f/ \. "- V I CLOCK OUT HIGH CLOCK OUT H'GH ..K '\ \\"'- f ~-2 o CLOCK OUT , LOW o.s.1 1.1 T'..E .... 2 o 2.1 1 ~ 0.5 1.5 I . 2 T'''E·~S OP020401 OP020501 • THE TWO DIFFERENT RESPONSES CORRESPOND TO THE TWO PHASES OF THE CLOCK. N-CHANNEL CLAMP CURRENT VI. OUTI'UT , VOLTAGE P-CHANNEL CLAMP CURRENT VOLTAGE ,.,.. VI. OUTPUT 10e,.A tll,oA 111,oA ,,.,. . 110A ii 1G011A 18 1011A 1M 1011A ~! 7 100pA 100pA 1apA tapA tpA +0.1 +0" +0.4 o +0.2 f 1M 1pA f -0.1 -0., -0.4 -0.2 o OUTPUT VOLTAGE ,\V + OUTPUT VOLTAGE AV0P020601 Note: All typical values have been guaranteed by characterization and are not tested. OP0207OI i ICL7650 a Output 'Clamp RZ The OUTPUT CLAMP pin allows reduction of the overload recOvery time inherent with chopper-stabilized amplifiers. When tied to the inverting input pin, or summing jUnction, a current path between this point and the OUTPUT pin occurs just before the device' output saturates. Thus uncontrolled .input differential inputs are avoided, together with the consequent charge build-upon the correctionstorage capacitors. The output swing is slightly reduced. 0 ...........- - · .OUTPUT Clock The ICl7650 has an internal oscillator giving a chopping freqUency of 200Hz, available at the CLOCK OUT pin on the 14-pih devices. Provision has also been made for the use of an external clock in these parts. The INT100 pin has an internal pull-up and may be left open for normal operation, but to utilize an external clock this pin must be tied to V- to disable the internal clock: The external clock signal may then be applied to the EXT. CLOCK IN pin. At low frequencies, the duty cycle of the external clock is not critical, since an internal divide-by-two provides the desired 50% switching duty cycle. However; since the capacitors are charged only when EXT ClK IN is HIGH, a 50-80% positive duty cycle is favored for frequencies above 500Hz to ensure that any transients have time to settle before the capacitor~ are turned OFF. The external clock should swing between V + an~ GROUND for pOwer supplies up to ±6V, and between V and V+ -6V for highl;lr supply voltages. Note that a signal of about 400Hz will be present at the EXT ClK IN pin with INT high or open. This is the internal clock signal before the divider. Ti::025101 Figure 3: I~L7650/B Test Circuit DETAILED DESCRIPTION Amplifier The functional diagram shows the major elements of the ICl7650. There are two amplifiers, the main amplifier, and the nulling amplifier. Both have otfseMull capability. The main amplifier is connected continu,ously from the input to the output, while the nulling amplifier, under the control of the chopping oscillator and clock circuit, alternately nulls itself and the main amplifier. The nulling connections, which are MOSFET gates, are inherently high impedance, and two external capacitors provide the required storage of the nulling potentials and the necessary nulling-loop time constants. The nulling arrangement operates over the full common-mode and power-supply ranges, and is also independent of the output level, thus giving exceptionally high CMRR, PSRR, and AVOL. , . Careful balancing of the input switches, and the inherent balance of the input circuit, minimizes chopper frequency charge injection: at the input terminals, and also the feedforward-typeinjection into the compensation capaCitor, which is the main cause of output spikes in this type of circuit. 1m In those applications where' a strobe signal is available, an ~Iternate approach to avoid capacitor misbalancing during overload can be used; Ita Strobe Signal is connected to' EXT ClK IN so that it is low during the time that the overload signal is applied to the amplifier, neither capacitor will be charged. Since the. leakage at the capacitor pins is quite I.ow at room temperature, the typical amplifier will drift less than 10pV/sec, and relatively long measurements can be made with little change in offset. Intermodulation Previous chopper-stabilized amplifiers have suffered from intermodulation effects between the chopperfrequency and input signals. These arise because the finite AC gain of the amplifier necessitates a lImall AC signal at the input. This is seen by the zeroing circuit as an error signal; which is chopped and fed back, thus injecting .sum and difference frequencies and causing disturbances to the gain and phase vs. frequency characteristics near the' chopping frequency. These effe<;ts are sUbstantially reduced in the ICl7650 by feeding the nulling circuit with a dynamic curre~t, corresponding to the co'1lpensation capacitor current, In such a way as'toJ:ancel that portion of the il1Put signal due to finite AG gain. Since that is the major error contribution to the ICl7650, the intermodulation and gainl phase disturbances are held to very low values, and can generally be ignored. 'BRIEF APPLICATION NOTES Component Selection The two required capacitors, CEx-rA and CEXTB, have optimum values depending on the clock or chopping frequency. For the preset internal clock, the correct value is 0.1pF, and to maintain the same relationship between the chopping frequency and the nulling time constant this value should be scaled approximately in proportion if an external clock is used. A high-quality film-type capacitor such as mylar is preferred, although a ceramic or other lower-grade capacitor may prove suitable in many applications. For quickest settling on initial turn-on, low dielectric absorbtion capacitors (such as polypropylene) should .be used. With ceramic capacitors, several seconds may be required to settle to 1pV. Capacitor Connection Protec~ion All device pins are static-protected by the use of input diodes. However, strong static fields and discharges should be avoided, as they can cause degraded diode. junction characteristics, which may result in increased input-leakage currents. Static The nullistorage capaCitors should be connected to the CEXTA and CEXTB pins, with a common connection to the CRETN pin. This connection should be made directly by either a separate wire or PC trace to avoid injecting load current IR drops into the capacitive circuitry. The outside foil, where available, should be connected to CRETN. 4-54 Note: All typical values ' eve been guaranteed by characterization and are not tested. ICL7650' _....- .- N--· -W~ - NOTE:...!.!J!.1 INVERTING AMPLIFIER FOLLOWER +... -- ' """"'. . .,,0 IXnMAL C .~' :="'''7" ..... 8HOULD •• LOW IMPEDANCE FOIl OP1111U11 GUARDING RETN ~, .0 O~ ?" 8O'n'OII VIEW 80AIID LAYOUT .011......". GUAIQIIIrIO WITH _ _ NON-INVERTING AMPLIFIER .......... SSOO6801 Figure 4: Connection of 'Input Guards Latchup Avoidance Guarding Junction-isolated CMOS circuits inherently include a parasitic 4-layer (p-n-p-n) structure which has characteristics similar to an SCR. Under certain circumstances this junction may be triggered into a low-impedance state, resulting in excessive supply current. To avoid this condi' tion, no voltage greater than 0.3V beyond the supply rails should be applied to any pin. In general, the amplifier supplies must be established either at the same time or before any input signals are applied. If this is not possible, the drive circuits must limit input current flow to under 1rnA to avoid latchup, even under fault conditions. Extra care must be taken in the assembly of printed circuit boards to take full advantage of the low input currents of the ICL7650. Boards must be thoroughly cleaned with TCE or alcohol and blown dry with compressed air. After cleaning, the boards should be coated with epoxy or silicone rubber to prevent contamination. Even with properly cleaned and coated boards, leakage currents may cause trouble, particularly since the input pins are adjacent to pins that are at supply potentials. This leakage can be significantly reduced by using guarding to lower the voltage difference betWeen the inputs and adjacent metal runs. Input guarding of the 8-lead TO-99 package is accomplished by using a 10-lead pin circle, with the leads of the device formed so that the holes adjacent to the inputs are empty when it is inserted in the board. The guard, which is a conductive ring surrounding the inputs, is connected to a low impedance point that is at approximateIy the same voltage as the inputs. Leakage currents from high-voltage, pins are then absorbed by the guard. The pin configuration of tlie 14-pin dual in-line package is designed to facilitate guarding, since the pins adjacent to the inputs are not used (this is different from the standard 741 and 101A pin configuration, but corresponds to that of the LM108). Output Stage/Load Driving The output circuit is a high-impedance type (approximately 18kn), and therefore with loads less than this value, the chopper amplifier behaves in some ways like a transconductance amplifier whose open-loop gain is proportional to load resistance. For example, the open-loop gain will be 17dB lower with a 1kn load than with a 10kn load. If the amplifier is used strictly for DC, this lower gain is of little consequence, since the DC gain is typically ,greater than 120dB even with a 1kn load. However" for wideband applications, the best frequency response will be achieved with a load resistor of 10kn or higher. This will result ,in a smooth 6dB/octave response from 0.1 Hz to 2MHz, with phase shifts of less than 10· in the transition region where the main amplifier takes over from the nU,1I amplifier. Pin Compatibility The basic pinout of the 8-pin device corresponds, where possible, to that of the industry-standard 8-pin devices, the LM741 , LM101, etc. The null-storing external capacitors are connected to pins 1 and 8, usually used for offset null or compensation capaCitors, or simply not connected. The output-clamp pin (5) is similarly used. In the case of the OP05 and OP-07 devices, the replacement of the offset-null pot, connected between pins 1 and 8 and V +, by two capacitors from those pins to V-, will provide easy compatibility. As for the LM108, replacement of the compensation capacitor between pins 1 and 8 by the two capaCitors to Vis all that is necessary. The same operation, with the removal of any connection to pin 5, will suffice for the LM101, jlA748, and similar parts. The 14-pin device pinout corresponds most closely to that of the LM108 device, owing to the provision of ,"NC" pins for guarding between the input and all other pins. Since this device does not use any of the extra pins, and has no provision for Offset-nulling, but requires a compensation capacitor, some changes will be required in layout to convert it to the ICL7650. Thermo-Electric Effects The ultimate limitations to ultra-high precision DC amplifiers are the thermo-electric or Peltier effects arising in thermocouple junctions of dissimilar metals, alloys, silicon, etc. Unless all junctions are at the same temperature, thermoelectric voltages typically around 0.1 jlV but up to tens of jlVrC for some materials, will be generated. In order to realize the extremely low offset voltages that the chopper amplifier can provide, it is essential to take special precautions to avoid temperature gradients. All components should be enclosed to eliminate air movement, especially that caused by power-dissipating elements in the system. Low thermoelectric-coefficient connections should be used where possible and power supply voltages and power dissipation should be kept to a minimum. High-impedance loads are preferable, and good separation from surrounding heat-dissipating elements is advisable. rc, 4-05 Note: All typical values have been guaranteed by characterization and are not tested;' 4 ! .ICL7080 d TYPICAL APPUCATI()NS +7.JV Clearly the appliCations of the ICL7650 will mirror those of other op. amps. A.nywhere that the performance of a circuit can be significantly improved by a reduction of inputoffset voltage and. ~las current, the ICL765Q is the logical choice. Basic non·'nverting and inverting amplifier circuits are shown in FiglJr~iI 5 and 6. Both cire;:uits. can use the output clamping circ:uit to.enhancethe overload recovery performance. The only limitations on the replacement of other op amps by the ICL7650 are the supply voltage (±8V max.) and the output drive capability (10kn load for full swing). Even these limitations can be overcome using a simple booster circuit, as shown in Figure 7, to enable the full output capabilities of the LM741 (or any other standard device) to be combined .with the input capabilities of the ICL7650. The pair form a composite device, so loop gain stability, when the feedback network is added, should be watched carefully. ".",,,,,,.. _ . 10k L-~----t cJl_--_ ..... __ ounvr LCOO8911 , FULL "'-IFFECT , OUT ..,., ~ . > - Figure 8: I,.ow Offset Comparator ... LC008601 Figure 5: Non Inverting Amplifier With (Optional Clamp) NOTE: R,I!R2 INQICATES THE PARALLEL COMBINATION OF R, AND R2 Normal logarithmic amplifiers are limited in dynamic range in the voltage-input mode by their input-offset voltage. The built-in temperature compensation and convenience features. of the ICL804B can be extended to a voltage-input dynamic range of close to 6 decades by using the ICL7650 to offset-null the ICL804B, as shown in Figure 8. The same concept can also be used with such devices as the HA2500 or HA2600 families of op amps to add very low offset voltage capability to their very high slew rates and b!lndwidths. Note that these circuits. will also have their DC gains, CMRR, and PSRR enhanced. LC008701 Figure 6: .Inverting Amplifier With (OptionallClamp NOTE: R,I!R2 lIilDICATES THE PARALLEL COMBINATION OFR, .um R2 . Figure 8 shows the use ·of the clamp circuit to advantage in a zero-offset comparator. The usual problems in using a chopper stabilized amplifier in. this application are aVOided, since the clamp circuit forC8$ the inverting input to follow the input signal. The threshold input must tolerate the output clamp current oto VIN/R without disturbing other portions of the. system. LCOOOOOl Figure 9: ICL8048 Offset Nulled by ICL7650 FOR FURTHER APPLICATIONS ASSISTANCE, SEE A053 AND R017 Note: All typical values heve been guaranteed by characterization and are not testad. ICL7652 Chopper-Stabilized low-Noise Operational Amplifier GENERAL DESCRIPTION FEATURES .The ICL7652 chopper-stabilized amplifier offers exceptionally low input offset voltage and is extremely stable with respect to time and temperature. It is similar to INTERSIL's ICL7650 but offers improved noise performance and a wider common-mode input voltage range. The bandwidth and slew rate are reduced slightly. INTERSIL's unique CMOS chopper-stabilized amplifier circuitry is user-transparent, virtually eliminating the traditional chopper amplifier problems of intermodulation effects, chopping spikes. and overrange lock-up. The chopper amplifier achieves its low offset by comparing the inverting and non-inverting input voltages in a nulling amplifier, nulled by alternate clock phases. Two external capacitors are required to store the correcting potentials on the two amplifier nulling inputs; these are the only external components necessary. The clock oscillator and all the other control Circuitry is entirely self-contained, however the 14-pin version includes a provision for the use of an external clock, if required for a particular application. In addition, the ICL7652 is internally compensated for unity-gain operation. • • • • • • • • • Extremely Low Input Offset Voltage - 10llY Over Temperature Range Ultra Low Long-Term and Temperature Drifts of Input Offset Yoltage (150nVlMonth, 100nVrC) Low DC Input Bias Current - 15pA Extremely High Gain, CMRR and PSRR - Min 110dB Low Input NoiSe Voltage- O.2IlVp-p (DC - 1Hz) Internally Compensated for Unity-Gain Operation Yery Low Intermodulatlon Effects (Open-Loop Phase Shift < 2·@ Chopper Frequency) Clamp Circuit to Avoid OVerload Recovery Problems and Allow Comparator Use Extremely Low Chopping Spikes at Input and Output ORDERING INFORMATION PART NUMBER ICL7652CPD ICL76521JD ICL7652CTV ICL76521TV TEMP. RANGE PACKAGE O'C to +70'C -25·C to +85·C O·C to +70·C -25'C to +85·C 14-pin plastic 14-pin CERDIP 8-pin TO-99 8-pin TO-99 _a-. - I _ - IN o-I----++--o OUTPUT 14 IITJIIT z 1Cl_ 13 __ IXYcura lIT CUI our II II V' " I GUrM IIUIPUr CLAW • V-'"I:.. 7 _ _-..:il!-,Como 14 LEAD (OuOI.o dwg PD, JD) CLAMP -0. V·_.. T ~EXTCl.KIN TOP VIEW ~A'Cl.KOm ---r--L-l +. ..r--l--r-a c.nn l v- ~c TQ.H BD012801 (Oulilno dwg TV) Figure 1: Functional Diagram CD031811 Figure 2: Pin Configuration ..3100 i - !t !; ... CEXT'"'G.1,.F- ! y 10 e +5 ~ Q W II: CEXT=1,.F I:: BROADBAND NOISE o 25 1..., .. 1000 50 75 100 ¥ 125 0 ~ -5 I&. w II: >.. 150 2345878 TIME(ma) TEMPERATURE ("C) TIME(ma) 01'036601 0P036501 4-59 Note: All typical values have been guaranteed by characterization and are not tested. 2345878 0P036701 :1 ICL7652 I» g~ TYPICAL PERFORMANCE CHARACTERISTICS (CONT.) Voltage Follower Large Signal Pulse Response· 3 ~2 c(ock III :I!:l g OUT LOW ~ If 3 t"- ~ III "g~ CLOCK OUT HIGH 0 O~ -2 I IF S AS 0 -1 2 4 6 8 10 12 14 TIME (,.a) 140 2 r- -~LohK OUT ,-- 0 :\ -1 -2 - 2 0 2 ~ z 100 ~ CLOCK e-OUT ~~IG~ - ~ I-- ~ 'I" 4 ~ ij120 l!. f- \LOW -3 -3 -2 0 Open·Loop Gain and Phase Shift vs Frequency Voltage Follower Large Signal Pulse Response· 80 I . 30 IpHkE '- I r\. 80 40 RL=1Ok 20 I o 6 8 10 12 14 TIME(,..) 0.1 1 ........ ~ 50 I 70 ~ \ ~\ 90 110 :!I ! ~. 130 ill ~ 150 j) 10 100 1k 10k 1001< 1M FREQUENCY (Hz) OP037601 0P037501 I 1_ ~ MARGIN-8O" 0P037701 ·The two different responses correspond to the two phases of the clock. N-Channel Clamp Current vs OutPl't Voltage :;- Ii 100,.A a: 1o,.A illa: ! 1"" :) 10nA iii 1nA 100pA u a: iC ~ Z ~ iii z :z: :t 0.8 0.6 11.4 0.2 OUTPUT VOLTAGE jaV-) ~ 3 "~ 2 2 g 0 6 III 100nA 1UnA 1nA ~ 100pA 10pA 1pA ..3 III U A- =s Input Offset Voltage Change vs Supply Voltage P·Channel Clamp Current vs Output Voltage 10pA 1pA -1.0 -0.8 -0.6 -0.4 -Q.2 OUTPUT VOLTAGE (4V+) -2 5 -3 o o 0PQ37901 0P037801 Iii III II: ~ - - I:') ."..,. "" -1 4 - ~ ~ 6 8 10 12 14 111 TOTAL SUPPLY VOLTAGE (V) 0P038001 control of the chopping frequency oscillator and clock Circuit, alternately nulls itself and the main amplifier. The nulling connections, which are MOSFET gates, are inherently'high-impedance, and two external capacitors provide the required storage of the nulling potentials and the necessary nulling-loop time constants. The nulling arrange, rnent operates over the full common-mode and power supply ranges,. and is also independent of the output level, thus giving exceptionally high CMRR, PSRR, and AVOL. Rz 1MO <';"- O-~.OUTPtlT Careful balancing of the input switches, together with the ,inherent balance of the input circuit, minimizes chopper frequency charge injection at the input terminals. Feedforward-type injection into the compensation capacitor is also minimized, which is the main cause of output spikes in this type of circuit. TC028401 Figure 3: Test Circuit Intermodulation Previous chopper-stabilized amplifiers have suffered from intermodulation effects between the chopper frequency and input signals. These arise because the finite AC gain of the amplifier necessitates a small AC Signal at the input. This is seen by the zeroing circuit as an error signal, which is chopped and fed back, thus injecting sum and difference frequencies and causing disturbances to the gain and phase vs frequency characteristics near the chopping DETAILED DESCRIPTION The Functional Diagram (Figure 1) shows the major elements of the ICL7652. There are two amplifiers, the main amplifier, and the nulling amplifier. Both have offset-null capability. The main amplifier is connected continuously from the input to the output. The nulling amplifier, under the 4-60 Note: All typical values have been guaranteed by characterization and are not tested. ICL7652 frequency. These effects are substantially reduced in the ICl7652 by feeding the nulling circuit with a dynamic current, corresponding to the compensation capacitor current, in such a way as to cancel that portion of the input signal due to finite AC gain. Since that is the major error contribution to t!"le ICl7652, the intermodulation and gainl phase disturbances are held to very low values, and can generally be ignored. lower-grade capacitor may prove suitable in many applications. For quickest settling on initial turn-on, low dielectric absorption capacitors (such as polypropylene) should be used. With ceramic capacitors, several seconds may be required to settle to 11lV. . Static Protection All device pins are static-protected by the use of input diodes. However, strong static fields and discharges should be avoided, as they can cause degraded diode junction characteristics which may result in increased input-leakage currents. Capacitor Connection The null-storage capacitors should be connected to the CEXTA and CEXTB pins, with a common connection to the CRETN pin. This connection should be made directly by either a separate wire or PC trace to avoid injecting load current IR drops into the capacitive circuitry. The outside foil, where available, should be connected to CRETN. Latchup Avoidance Junction-isolated CMOS circuits inherently include a parasitic 4-layer (p-n-p-n) structure which has Characteristics similar to an SCA. Under certain circumstances this junction may be trigerred into a low-impedance state, resulting in excessive supply current. To avoid this condition no voltage greater than 0.3V beyond the supply rails should be applied to any pin. In general, the amplifier sllpplies must be established either at the same time or before any input signals are applied. If this is not possible, the drive circuits must limit input current flow to under 1mA to avoid latchup, even under fault conditions. Output Clamp The OUTPUT CLAMP pin allows reduction of the overload recovery time inherent with chopper-stabilized amplifiers. When tied to the inverting input pin, or summing junction, a current path between this pOint and the OUTPUT pin occurs just before the device output saturates. Thus uncontrolled differential input voltages are avoided, together with the consequent charge build-up on the correctionstorage capacitors. The output swing is slightly reduced. Output Stage/Load Driving Clock The output circuit is a high-impedance type (approximately 18kn), and therefore, with loads less than this the chopper amplifier behaves in some ways like a transconductance amplifier whose open-loop gain is proportional to load resistance. For example, the open-loop gain will be 17dB lower with a 1kn load than with a 10kn load. If the amplifier is used strictly for DC, this lower gain is of little consequence, since the DC gain is typically greater than 120dB even with· a 1kn load. However, for wideband applications, the best frequency response will be achieved with a load resistor of 10kn or higher. This will result in a smooth 6dB/octave response from 0.1Hz to 2MHz, with phase shifts of less than 2° in the transition region where the main amplifier ,takes over from the null amplifier. The ICl7652 has an internal oSCillator, giving a chopping frequency of 400Hz, available at the CLOCK OUT pin on the 14-pin devices. Provision has also been made for the use of an external clock in these parts. The INT100 pin has an internal pull-up and may be left open for normal operation, but to utilize an external clock this pin miJst be tied to V- to disable the internal clock. The external ·clock signal may then be applied to the EXT CLOCK IN pin. An internal divide-by-two provides the desired 50% input switching duty cycle. Since the capacitors are charged only when EXT CLOCK IN is high, a 50%-80% positive duty cycle is recommended, especially for higher frequencies. The external clock can swing between V+ and V-. The logic threshold will be at about 2.5V below V + . Note also that a signal of about 800Hz, with a 70% duty cycle, will be present at the EXT CLOCK IN pin with INT /EXT high or open .. This is the internal clock signal before being fed to the divider. In those applications where a strobe signal is available, an alternate approach to a.void capacitor misbalancing during overload can be used. If a strobe signal is connected to EXT ClK IN so that it is low during the time that the overload signal is applied to the amplifier, heither capacitor will be charged. Since the leakage at the capacitor pins is quite low at room temperature, the typical amplifier will drift less than 1OIlV/sec, and relatively long measurements can be made with little change -in offset. Thermo-Electric Effects BRIEF APPLICATION NOTES Component Selection The ultimate limitations to ultra-high precision DC amplifiers are the thermo-electric or Peltier effects arising in thermo-couple junctions of dissimilar metals, alloys, silicon, etc. Unless all junctions are at the same temperature, but up thermo-electric voltages typically around 0.11lV for some materials, will be generated. In to tens of IlV order to realize the extremely low offset voltages that the chopper amplifier can provide, it is essential to take special precautions to avoid temperature gradients. All components should be enclosed to eliminate air movement, especially that caused by power-dissipating elements in the system. low thermoeleCtric-coefficient connections should be used where possible and power supply voltages and power dissipation should be kept to a minimum. High-impedance loads are preferable, and good separation from surrounding heat-dissipating elements is advisable. The required capacitors, CEXTA and CEXTB, are normally in the range of 0.11lF to 1.0IlF. A 1.01lF capacitor should be used in broad bandwidth circuits if minimum clock ripple noise is desired. For limited bandwidth applications where clock ripple is filtered out, using a 0.11lF capacitor results in slightly lower offset voltage. A high-quality film-type capacitor such as mylar is preferred, although a ceramic or other Extra care must be taken in the assembly of printed circuit boards to take full advantage of the low input currents of the ICl7652. Boards must be thoroughly cleaned with TCE or alcohol and blown dry with compressed air. After cleaning, the boards should be coated with epoxy or silicone rubber to prevent contamination. rc rc, Guarding 4-61 Note: All typical values have been guaranteed by characterization and are not tested. i... ..... 2 ICL.7852 ~. Even with properly cleaned and coated boards, leakage currents may cause trouble, particularly since the input pins are adjacent to pins that are at· supply potentials. This leakage Can be significantly reduced by using guarding to lower the voltage difference between the inputs and' adjacent metal runs. Input guarding of the 8 lead TO-99 package is acc9mplished by using a 10 lead pin circle, with , the leads of the device f.ormed so that the holes adjacent to the inputs are empty when it is inserted in the board. The. guard, which is a conductive ring surrounding the inputs, is , connected to a low-impedance point that is at approximately the same voltage as the inputs. Leakage currents from high-voltage pins are then absorbed by the guard. PIN COMPATIBILITY , The, basic pinout of the 8:pin de,vice corresponds, where possible, to that of theindusti"y-standard8-pin devices, the LM741, LM1 01, etc. The null-s~oring external capacitors are connected to pin,S 1 and 8, which are usu,ally used fO,r offsetnull or compensation capacitors. The output~clamp pin (5) is Similarly used. In the case of the OP-05 and OP-07 devices, the replacement of the offset-null pot; connected between pins 1 and 8 and Y + , by two capacitors from those pins 1'0 Y-, will prClvide easy compatibility. As for the LM108, replacement of the compensation capaCitor between pins 1 and 8 by the two capacitors to Y- is all thatis necessary. The same operation, with the removal of any connection to pin 5, will suffice for the LM101, jJA748, lind similar parts. The 14-pin device pinout corresponds most closely to that of the LM108 device, owing to the provision of "NC" pins for guarding between the input and all other pins. Since this device does not use any of the extra pins, and has no provision for offset-nulling, but requires a compensation capacitor, some changes will be required in layout to convert to the ICQ652. . The pin configuration of the 14"pin dual-in-line package is designed to facilitate' guarding, since the pins adjacent to the. inputs. are not used (this is different from the standard 741 and 101A pin configuration; but corresponds to that of the LM108). INPUT~~~-.------~~----~ OUTPUT OUTPUT INPUT ~++--t TC----*-1 OUTPUT yo. lC017701 Figure 6: Inverting Amplifier with (Optional) Clamp Clearly the applications of the ICL7652 will mirror those of other op-amps. Thus, anywhere that the performance of a circuit can be significantly improved by a reduction of input-offset voltage and bias current, the ICL7652 is the logical choice. Basic non-inverting and inverting amplifier circuits are shown in Figures 5 and 6. Both circuits can use the output clamping circuit to enhance the overload recovery performance. The only limitations on the replacement of other op-amps by the ICL7652 are the supply voltage (±8V max) and the output drive capability (10kn load for full swing). Even these limitations can be overcome using a simple booster circuit, as shown in Figure 7, to enable the full output capabilities of the LM741 (or any other standard device) to be combined with the input capabilities of the ICL7652. The pair form a composite device, so loop gain stability, when the feedback network is added, should be watched carefully. AF031201 Figure 8: Low Offset Comparator It is possible to use the ICL7652 to offset-null such high slew rate and bandwidth amplifiers as the HA2500 and HA2600 series, as shown in Figure 9. The same basic idea can be used with low-noise bipolar devices, such as the OP05 and also with the ICL8048 logarithmic amplifier, to achieve a voltage-input dynamiC range of close to 6 decades. Note that these circuits will also have their DC gains, CMRR and PSRR enhanced. More details on these and other ideas are explained in application note A053. Mixing the ICL7652 with circuits operating at ±15V supplies requires the provision of a lower voltage. Although this can be done fairly easily, a highly efficient. voltage divider can be built using the ICL7660 voltage converter circuit "backwards". A suitable connection is shown in Figure 10. Note: All typical values have been guaranteed by characterization and are not tested. :" a ICL7652 TYPICAL APPLICATIONS OUT AFOS1311 HA2500l10/20 HA2600120 OR SIMILAR DEVICE Figure 9: HA2500 or HA2600 Offset-Nulled by ICL7652 2 'r---<+15V ICL7IIO 1--.--+ +7.5V 100F I--+--+ov AF0308CK Figure 10: Splitting + 15V with ICL7660 at > 95% efficiency. Same for -15V FOr further applications a..lstance, _ AOS3 and R017 4-64 Note: All typical values have been guaranteed by characterization and are not tested. ICLa007 JFET Input Operational Amplifier GENERAL DESCRIPTION FEATURES The Intersi! ICLB007 is a low input current JFET input operational amplifier. The ICLB007 A is selected for 4 pA max input current. The devices are designed for use in very high input impedance applications. Because of their high slew rate, high common mode voltage range and absence of "latchup", they are ideal for use as a voltage follower. The Intersil B007 and B007 A are short circuit protected. They require no external components for frequency compensation because the internal 6 dB/roil-off insures stability in closed loop applications. A unique bootstrap circuit insures unusually good common mode rejection for a JFET input op-amp and prevents large input currents as seen in some amplifiers at high common mode voltage. • • • • • • Ultra Low Input Current High Slew Rate - 6VI /J5 Wide Input Common Mode Voltage 1MHz Band Width Excellent Stability Ideal for Unity Gain Applications ORDERING INFORMATION PART NUMBER TEMPERATURE RANGE to +70·C ICL8007CTV ICL8007ACTV O·C ICL8007MTV ICL8007AMTV -55·C ICL8007/D to + 125·C - PACKAGE 8 LEAD TO-99 METAL CAN DICE"· ··Parameter MinIMax Limits quaranteed at 25·C only for DICE orders. ~.----------.--------~----~~o.· ••• ..., L.--+-oOUTPUT Q •• r'O"V'fW, CO01690t TC02590t ICL8007 pin 4 connected to case (TV package) ICL8007A pin 8 connected to case (TV package) Figure 1: Functional Diagram Figure 2: Pin Configuration 4-65 Note: All typical values have been guaranteed by characterization and are not tested. g ICLeoo7 a A'BSOLUTE MAXIM'UM RATINGS Supply Voltage ................................................ ±18V Power Dissipation (Note 1) ............................. 500mW Differential Input Voltage ...................................±30V Input Voltage (Note 2) ...............................'..... :.±15V Storage Temp.erature Range;·........... ~65·C to + 150·C Operating Temperature Range 8007M, 8007AM .................... - 55·C to -+: 125·C 8007C, 8007AC ........................... O·C to + 70·C Lead Temperature (Soldering, 10sec) ................. 300·C Output Short-Circuit Duration (Note 3) ............ Indefinite NOTES: 1. Rating applies lor case temperatures to 12S0C; derate linearly at 6.S mW/oC' lor ambient temperatures above + 7SOC. 2~ For supply voltages less than ± 15V, the absolute maximum input voltage is equal to the supply voltage. 3. Short circu~ may be to ground or e~her supply. Rating applies to + 12SoC case temperature or + 7SOC ambient temperature. 4. For Design only, not 100% tested. ELECTRICAL CHARACTERISTICS CHARACTERISTICS (Vs = ±15V unless otherwise specified) aOO7M TEST CONDITIONS MIN The following specifications apply for T A Input Offset Voltage 8007C TYP MAX 10 20 MIN a007AM & aOO7AC TYP MAX 20 SO MIN MAX 15 30 mV 4.0 pA =25·C: 'Rs ~ 100kn Input Offset Current 0.5 Input Bias Current (either input) 2.0 Input Resistance 106 106 106 Input Capacitance 2.0 2.0 2.0 Large Signal Voltage Gain UNIT TYP RL ~ 2kn, VOUT - ±10V 0.5 20 50.000 3.0 0.2 50 20,000 0.5 pA Mn pF viv 20,000 Output Resistance 75 75 75 n Output Short-Circuit Current 25 25 25 rnA Supply Current 3.4 5.2 3.4 6.0 3.4 6.0 rnA Power Consumption 102 156 102 160 102 180 mW Slew Rate 6.0 Unity Gain Bandwidth 1.0 6.0 1.0 2.S 6.0 VIliS 1.0 MHz Risetime CL ~ 100pF, RL - 2kn 300 300 300 ns Overshoot CL ~ loopF, RL - 2kn 10 10 10 % The following specifications apply for O·C :5 TA :5 (8007M and 8007AM): Input Voltage Range Common Mode Rejection Ratio + 70·C (8007C and 8007AC), and -55·C:5 TA:5 + 125·C ±10 ±12 ±10 ±12 ±10 ±12 V 70 90 70 90 86 95 dB Supply Voltage Rejection Ratio 70 Large Signal Voltage Gain Output Voltage Swing RL ~ RL~ Input Bias Current (either input) TA = + 125°C TA= + 70°C Average Temperature Coefficient 01 Input Offset Voltage 300 25,000 10kn 2kn ±12 ±10 70 600 ±14 ±13 ±12 ±10 ±14 ±13 ±12 ±10 2.0 SO 75 (Note 4) .-----""9"""9--- Your TC026011 Figure 3: Transient Response Test Circuit Note: All typical values have been guaranteed by characterization and are not tested. 70 200 15,000 15,000 75 "VIV VIV ±14 ±13 V V 1.0 30 nA pA 50 "V/oC ICLa007 TYPICAL PERFORMANCE CHARA~TERISTICS 10" 10" ~SII~ ••i&v t-... t\. z 10" C ... 10> ".... 10' I!I ~ g ~!U:";.~'5V 8 T•• +25·C 1\ t\. ""- 10 I 10 100 'I INPUT 7 ~ \ ~ TA =+2&"C RL = 'CIkfi I 1\ OUT..JT i1 I, ~ 10k lOOk 1M 10M lk ~!:,,..! =(±\~~ _ I~ ~ I!I OUTPUT VOLTAGE SWING AS A FUNCTION OF FREQUENCY VOLTAGE FOLLOWER LARGE SIGNAL PULSE RESPONSE OPEN LOOP VOLTAGE GAIN 0'23458781 FIlEQUENCYCHzl 'CIk TIME (~.) '00k 10M 1M FREQUENCY (Hz) QP026001 OP025901 0P025801 INPUT BIAS CURRENT AS A FUNCTION OF TEMPERATURE TRANSIENT RESPONSE OUTPUT SWING AS A FUNCTION OF SUPPLY VOLTAGE 20 28 T.=25"C R L ' 2kn 24 20 90"0 16 ~ I I '2 ,CrJ I o " W i tI< tI< Vs " f- o ~ z 103 ..a ~ ~lSV ~ ~ RISE TIME T.· 25 C RL " 2 kl! CL"loopF 5 1.0 TIME 2.0 1.S .... 1/ 0 ./ 10 /V 10 // ;) ;) V POSIT.VE SWING/ ~ / to' 15 / 5 V V NEGATIVE SWING N :::; 2.5 " ~ ./ 1 20 ~ (ps) 40 60 80 100 120 15 10 5 0 140 SUPPLYV(lTAGE "V) TEMPERATURE C·C) 0P026301 0P026101 0P026201 INPUT VOLTAGE RANGE AS A FUNCTION OF SUPPLY VOLTAGE OPEN LOOP VOLTAGE GAIN AS A FUNCTION OF SUPPLY VOLTAGE QUIESCENT SUPPLY CURRENT AS A FUNCTION OF SUPPLY VOLTAGE 5 20 ~ co z ~ 15 POSITIVE / C tI< ... ...... ~ > ~ ... ;) AI" 10 0 5 ~ I/, V / / V /NEGAT(VE T. "25'C i 4 tI< tI< a> 3 ~ 2 !i ... .... I-- I-- - .... V .0' L-.l-...l-....1..-L-L--l_.l....-J o 5 10 15 0 SUPPL Y VOLTAGE C'V) 10 10 15 SUPPLY VOLTAGE "VI 0P026401 0P026S01 U ...> 2 ~ - -r0- t- ~> oS ... ; 10' ~ ... 0 > ... -15 25 65 105 10' I-- '"~ ' Rs " iu son III 100 lk 10k lOOk FREQUENCY \Hzl TEMPERATURE I'CI OP026701 0 ... - For additional information, see Application Note AO05., 40-68 Note: All typlcal values have been guaranteed by characterization and are not tested. ~~~~001dtz V 8,0.0 Rs" 1 Mn I- 10 100 ~ '0 -55 WIDEBAND NOISE AS A FUNCTION OF SOURCE RESISTANCE INPUT VOLTAGE NOISE AS A FUNCTION OF FREQUENCY QUIESCENT SUPPLY CURRENT AS A FUNCTION OF TEMPERATURE I o.1 100 - ~ ~ =~~~(cHz I I 1 1k 10k 100k 1M 10M , _ SOURCE RESISTANCE (0) OP026911 .U~UlLi... ICL8021/ICL8022/ ICL8023 -I N Low Power Bipolar Operational Amplifier GENERAL DESCRIPTION The Intersil ICL8021 series are low power operational amplifiers specifically designed for applications requiring very low standby power consumption over a wide range of supply voltages. The electrical characteristics of the 8021 series can be tailored to a particular application by adjusting an external resistor, RSET, which controls the quiescent current. This is advantageous because IQ can be made independent of the supply voltages: it can be set to an extremely low value where power is critical, or to a larger value for high slew rate or wideband applications. Other features of the 8021 series include low input current that remains constant with temperature, low nOise, high input impedance, internal compensation and pin-forpin compatibility with the 741. The Intersil 8022 (8023) consists of two (three) low power operational amplifiers in a single 14(16)-pin DIP. Each amplifier is identical to an 8021 low power op amp, and has separate connections for adjusting its electrical characteristics by means of an external resistor, RSET, which controls 'the quiescent current of that amplifier. • • • • • • • VOS = 3mV Max (Adjustable to Zero) ± 1.SV to ± laV Power Supply Operation Power Consumption - 20j.lW @ ±1V Input Bias Current - 30nA Max Internal Compensation Pin-for-Pin Compatible With 741 Short Circuit Protected ORDERING INFORMATION ICLB021 C PART NUMBER TV LpaCkage TV - TO-99 Metal can PA - 8 pin Minidip JD PD - 14 pin CERDIP 14 pin Plastic DIP 8021 only 8022 only JE - 16 pin CERDIP 8023 only PE - 16 pin, Plastic DIP ' - - - - - Temperature C - Commercial - O·C to + 70·C M - Military - -SS·C to + 12S·C ' - - - - - - - - Basic Part Number 8021 - Single 8022 - Dual 8023 - Triple TEMPERATURE RANGE - ICL8021/D ICL8021CJA ICL8021C8A ICL8021 CPA ICL8021CTY ICL8021MJA ICL8021MJD ICL8021MTY O·C O·C O·C O·C -SS·C -SS·C -SS·C ICL8022/D ICL8022CJD ICL8022CPD ICL8022MJD O·C to 70·C O·C to 70·C -SS·C to + 12S·C ICL8023/D ICL8023CJE ICL8023CPE ICL8023MJE O·C to 70·C O·C to 70·C -SS·C to + 12S·C to to to to to to to 70·C 70·C 70·C 70·C + 12S·C + 12S·C +12S·C PACKAGE DICE" 8 Lead CERDIP 8 Lead S.O.l.C 8 Lead MINIDIP 8 Lead Metal Can 8 Lead CERDIP 14 Lead CERDIP 8 Lead Metal Can - DICE 14 Lead CERDIP 14 Lead MINIDIP 14 Lead CERDIP - DICE 16 Lead CERDIP 16 Lead MINIDIP 16 Lead CERDIP "Parameter MinIMax Limits guaranteed at 2S·C only for DICE orders. 4-69 Note: All typical values have been guaranteed by charscterization and are not tested. N FEATURES I fit ICLII021l1CL~022/1CL8023 ABSOLUTE MAXIMUM RATINGS Supply Voltage ................................................ ±18V Differential Input Voltage (Note 1) ....................... ±15V Common Mode Input Voltage (Note 1) ................ ±15V Output Short Circuit Duration .............. , ......... Indefinite Power Dissipation (Note 2) ............................. 300mW NOTE 1: For supply voltages less' than Operating Temperature Range, " 8021M .................... : .......... -55·C to +125·C 8021 C ..................................... O·C to + 70·C Storage Temperature Range , ........... -65·C 10 + 150·C Lead Temperature (Soldering. 10sec) ........ ~ ...... +300·C 'f 15V. the absolute maximum'input voltage is equal to the supply voltage, NOTE 2: Rating applies for case temperatures io + 125'C; derate linearly at 5,6 mW I'C for ambient temperatures above + 95,·C. In Z&KO V' 05026001 Figure 1: Functional Diagram 10 SET 8AL~, -IN 2 ,10 V·'SET 'IN 3· OUT _ '8 7 V-4 sBAL y' (outline dwg PAl (outline dwg TV) CD017501 CD017401 (outline dwg JE, PEl (outline dwg JO, PO) CD017t'101 CO0177ot Figure 2: Pin Configurations 4-70 Note: All typical values have been guaranteed by characterization and are not tested. 1I0~OIb ICL8021/ICL8022/ICL8023 ~ -i ... v' -i N N N Col TC034801 Figure 3: Voltage Offset Null Circuit ELECTRICAL CHARACTERISTICS (VSUPPLY = ±6V, la = 30j.lA, unless otherwise specified.) 8021C 8021M CHARACTERISTICS TEST CONDITIONS MIN TYP MAX MIN TYP UNIT MAX The following specifications apply for TA = 2S·C: 2 3 2 6 mV Input Offset Current .5 7,5 .7 10 nA Input Bias Current 5 20 7 30 Input Offset Voltage RS 5100kn Input Resistance Input Voltage Range Common Mode Rejection Ratio VSUPPLY'" ±15V Rs 510kn 10 3 10 ±13 ±12 ±13 V 70 80 70 80 dB Supply Voltage Rejection Ratio Rs 510kn 30 Output Resistance Open Loop 2 Output Voltage Swing RL <: 20kn, VSUPPLY ~ ± 1'5V ±12 RL<:IOkn, VSUPPLy=±15V· ±II 150 ·±14 ±I3 30 360 VOUT=O Slew Rate (Unity Gain) Unity Gain Bandwidth RL = 20kn, VIN = 20mV Transient Response (Unity Gain) RL'" 20kn, VIN '" 20mV Ri.setime Overshoot Mn 150 IlVN 2 kn .,±12 ±14 V ±II ±13 V ±I3 mA ±I3 Output Short-Circuit Current Power Consumption nA 3 ±12 480 380 600 IlW O.IS 0.16 V/JlS 270 270 kHz 1.3 10 1.3 10 IlS % The following specifications apply for O·C5TA5 +70·C (B021C) and -SS·C5TA5 +12S·C (B021M) Input Offset Voliage RS 5 lOkn Input Offset Current Input Bias Current Average Temperature Coefficient of Input Offset Voltage Average Temperature Coefficient of Input Offset Current RS 5 lOkn . Large Signal Voltage Gain RL = lOkn 50. Output Voltage Swing RL<: 10kn ±to 4-71 Note: All typical values have been guaranteed by characterization and are not ·tested. 2.0 4.0 2.0 7.5 mV 1.0 II 1.5 15 nA 10 32 15 50 nA 5 5 IlV/"C 1.7 0.8 pA/·C 50 200 V/mV ±IO ±IS V 200 ±13 =ICL8021/ICL8022/ICL8023 a II QUIESCENT CURRENT ADJUSTMENT &'II QUIESCENT CURRENT SETTING RESISTOR (PIN a to V-) QUIESCENT CURRENT SETTING RESISTOR (PIN a to V-) 10 Vs 10pA 301lA 1001lA ±1.5 1.5MQ 470kn l50kQ - ±3 3.3MQ 1.lMQ 330kQ lookQ ±6 7.5MQ 2.7MQ 750kQ 220kQ ±9 l3MQ 4MQ 1.3MQ 350kQ £ .t_ 3001lA ±12 laMQ 5.6MQ 1.5MQ 5l0kQ ±15 22MQ 7.5MQ 2.2MQ 620kQ I~ , 10"A 10M!!~IIIII~~~~ '~~ :z> I M!! ~IIIII~'~O~'~'OO~"A~ IQ = 300fjA 1.fI.Jo1"11111 U IIIII 100.) o 2 4 6 8 10 12 14 16 18 5UPPL Y VOLTAGE I· VI OPO.27501 TYPICAL PERFORMANCE CHARACTERISTICS· (TA = + 2SoC, Vs = ±6V, 10 - 30,iA unless otherwise specified.) INPUT BIAS CURRENT VS AMBIENT TEMPERATURE INPUT BIAS CURRENT VS QUIESCENT CURRENT DIFFERENTIAL INPUT IMPEDANCE VS QUIESCENT CURRENT lOll 100 C i ...z.s ~ c c ... w rr: rr: ;:) u 10 B '"c ii ~ iii ... 50 10 10 IQI_~,,! 1 5 i C ! -I- I" - 10 30 lOll ~ I IJ -80 300 -ID"A I I I I I -IOO"A -20 0 20 80 100 140 TEMPE RATURE ( CI QUIESCENT CURRENT ",AI QUIESCENT CURRENT ("AI OP027701 0P027601 0P027801 SLEW RATE VS QUIESCENT CURRENT FREQUENCY RESPONSE VS QUIESCENT CURRENT PHASE MARGIN VS QUIESCENT CURRENT RL ·2011U 'iii' w 5 J . /~ ~ w C ... rr: iI ...... 1/ ~ 4S :l:z: 30 ... V '" ...- .... 13 • rr: V 05 ~IO c/. w -..e..75 z L IL 01 10 30 100 30 300 QUIESCENT CURRENT ("AI 100 300 QUIESCENT CURRENT ("AI 0!' 0 0 ... 40 ~ "'..." 15 > 10 0 z :;) > 2 Z 5 :;) 0 RISE TIME o 4 8 12 ~ "z ~ RL • 20kfl "'" === l- S > I- :;) 100 fI 300 0P028401 EQUIVALENT INPUT NOISE CURRENT VS FREQUENCY ;i ~ 80 > "...c... __ 10 'IOOI~~ 50 , 40 .r---- 0 ... > 30 10 ·30p.A 10' 10 ,.A c/O / .. 30 aUIESCENT CURRENT I,.AI EQUIVALENT INPUT NOISE VOLTAGE VS FREQUENCY ... w ~ I i OP02B301 .!: 10 Ys ' ,6Y 10 16 TIME l,.tlCl OUTPUT VOLTAGE SWING VS SUPPLY VOLTAGE L Vs' 'ISV I OP028201 30 't-.. 5 i rt 0 10 Ik IOU. FREOUENCY IHzI 10 :;) 2 :;) 0I- "'- ... c ~~ 0- ! 50 ...~ I- "I~ .u 0 20 RL • tOka CL'IOOpF I- ~~ 0- > ! ... ~R, "50UI 80 MAXIMUM LOAD VS QUIESCENT CURRENT TRANSIENT RESPONSE 0 20 i 10 ...Z 0- :;) ! 0 '1 ,3 ,6 '10 50 SUPPLY VOL TAGE IVI 100 Ik 50 100 500 Ik FREaUENCY 1Hz, FREQUENCV 1Hz} 0P02a501 *ICL8021 C guaranteed only for O·C ::; T A ::; 500 0P0287Of 0P02II6OI + 70·C 4-73 Note: All typical values have been guaranteed by characterization and are not tested. !i ICL8043 ,3 Dual JFET Input Operational . g Amplifier GENERAL DESCRIPTION FEATURES ThelCL8043 contains two FET input op amps, each similar in performance .to the ICL8007. The inputs and outputs are fully short circuit protected, and no latch-up problems exist.· Offset nulling is accomplished by using a. single pot (for each amplifier) connected to .th!! positive supply voltage~ The devices have excellent common mode . rejection. • • • • • Very Low Input Current - 2pA Typical High Slew Rate - 6VI j.I8 Internal Frequency Compensation Low Power DIssipation - 135mW T.yplcal Monolithic Construction ORDERING INFORMATION PART NUMBER TEMPERATURE RANGE ICL8043MJE - 55°C to 125°C CERAMIC 16 Pin DIP ICL8043CPE O°C,to 70°C Plastic 16 Pin DIP ICL8043CJE O°C to 70°C CERAMIC 16 Pin DIP PACKAGE -... _NUU -IN (outline dwgs JE. PEl c0017901 08018701 Figure 1: Functional Diagram (One Side) Figure 2: Pin Configuration 16 Pin DIP (Top View) 4-74 Note: All typical values have been guaranteed by characterization and are not tested. .O~OIL ICL8043 ABSOLUTE MAXIMUM RATINGS Supply Voltage ................................................ ±18V Internal Power Dissipation (Note 1) .................. SOOmW Differential Input Voltage ................................... ±30V Input Voltage (Note 2) ...................................... ±1SV Voltage between Offset Null and V+ ................. ±O.SV Storage Temperature Range ............ -6S'C to + 150'C Operating Temperature Range 8043M ............................... -5S'C to + 12S'C 8043C ..................................... O'C to + 70'C Lead Temperature (Soldering. 10sec) ................. 300·C Output Short-Circuit Duration ......................... Indefinite Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods m~y affect device reliability. NOTES: 1. Rating applies for case temperatures to 12SoC; derate linearly at 9mWI"C for ambient temperatures above +9SoC. 2. For supply voltages less than ± 1SV, the absolute maximum input voltage is equal to the supply voltage. ELECTRICAL CHARACTERISTICS (VSUPPLY = ± 1SV unless otherwise specified) 8043M SYMBOL CHARACTERISTIC 8043C TEST CONDITIONS UNIT MIN TYP MAX 10 20 MIN TYP MAX 20 50 The following specifications apply for TA = 2SoC: VOS Input Offset Voltage lOS Input Offset Current RS < 100kn 0.5 liN Input Current (either input) 2.0 RIN Input Resistance 106 CIN Ay Input Capacitance RO Output Resistance ISC Output 3.0 20 Current 50 pA Mn 2.0 SO,OOO mV pA 106 2.0 RL> 2kn, You! ~ ± 10V Large Signal Voltage Gain Short-Circu~ 0.5 pF 20,000 VN 75 75 n 25 25 rnA ISUPPLY Supply Current (Total) 4.5 6 4.5 6.8 rnA POISS SR Power Consumption 135 180 135 204 mW Slew Rate 6.0 6.0 V/pB GBW Unity Gain Bandwidth 1.0 1.0 MHz tr Transient Response (Unity Gain) Risetime Overshoot 300 10 300 10 ns % The following specifications apply for O·C t.VIN CMRR CL < 100pF, RL = 2kn < TA < + 70°C (8043C). - SS·C < TA < + 12SoC Input Voltage Range Common Mode Rejection Ratio PSRR Supply Voltage Rejection Ratio Ay Large Signal Voltage Gain t.VO Output Voltage Swing VOS :np\ll Offset Voltage liN Input Current (either input) t.VOSlt.T Average Temperature Coefficient of Input Offset Voltage (8043M): ±10 ±12 ±10 ±12 V 70 90 70 90 dB 70 70 300 25,000 ±12 ±14 ±12 ±14 RL> 2kn ±10 ±13 ±10 ±13 15 30 2.0 15 TA = +70°C 75 (Note 3) NOTE: 3. For Design only, not 100% tested. 4-75 Note: All typical values have been guaranteed by characterization and are not tested. p.VN VN RL> 10kn TA= +12SoC 600 15,000 V V 30 60 mV 50 175 pA nA 75 p'vrc ·S!1 ~:::'~~:RFORMANCE CHARACTERISTICS OPEN LOOP VOLTAGE GAIN AS A FUNCTION OF FREQUENCY 10" 105 ~ ysJ.... = l15Y TA=+U'C l'\.. e--:.. 10 .. ...C '" ~ z ~ r\.. l'\.. OUTPUT VOLTAGE SWING AS A FUNCTION OF FREQUENCY ~ VOLTAGE FOLLOWER LARGE-5IGNAL PULSE RESPONSE· . v.:;.:.. •• 1~~ 1-. 1\ ~ I\.. " .,.~ "II! , 16 00( i'\ 0 Ik 10k lOOk 1M 10M FReQueNCY fHrI OP020901 INPUT CURRENT AS A FUNCTION OF TEMPERATURE OUTPUT SWING AS A FUNCTION OF SUPPLY VOLTAGE 20 - TA 1= I ~li o TL I-- I alc =2Icll POJITIVE SWI, I .5 I- Vsupp = :t15V ~:~ 1.0 1.5 TIME (.0) 2.0 2.5 .0 80 80 100 .120 TEMPERATURE rC) 1.0 o :t5 :tIO :tIS SUPPLY VOLTAGE 0_ 0P030101 OPEN LOOP VOLTAGE GAIN AS A FUNCTION OF SUPPLY VOLTAGE V V" ./V V I-- I-- NEjATtE jWlNj- I-- ~ TA = 25°C ~ i/17 ,/ RISETIME 1/ -8 100 lk 10k lOOk 1M 10M FREQUENCY (HI) TRANSIENT RESPONSE 'OUTPUT -I-i-I- ~- 8 00( ~ r INPUT Q 0P029801 ..• I I Yiu" •• ,5V : I ~~;H: 8 TA • +25°C RL"OkG 32 INPUT VOLTAGE RANGE AS A FUNCTION OF SUPPLY VOLTAGE QUIESCENT SUPPLY CURRENT AS A FUNCTI.ON OF SUPPLY VOLTAGE • 20 :/, T. -'H'C 1/ V I-- i- POSIT/ i/7 l/V - I.- I-'" ~ciATlVE- - ±20 .-- I.-~ V 1~0~~--:t~5-L-:t~10~--:t~15~-:t20~ SUPPLY VOLTAGE o ±5 ±10 ±15 SUPPLY VOLTAGE 0P030401 :t20 OP030501 4-76 Note: All typical values have been guaranteed by characterization and afe not tested. 2 :t5 ±10 ±15 SUPPLY VOLTAGE ±20 ICL8043 TYPICAL PERFORMANCE CHARACTERISTICS (CONT.) TOTAL QUIESCENT SUPPLY CURRENT AS A FUNCTION OF TEMPERATURE INPUT NOISE VOLTAGE AS A FUNCTION OF FREQUENCY WIDEBAND NOISE AS A FUNCTION OF SOURCE RESISTANCE 104 Vs= :t11Y -- r-- .... - -;01000 E .: > ___ BANDWIDTH ,L... 100 _ . 10H, TO 100kH,.T 1"--0 ..~ r-- r RS=1Mtl r--; ~ II~: = SOlI IE - 10.0 i--' c ... 1111 I -15 25 15 TEMP£RATURE COC) 10 105 100 Ik 10k BANDWIDTH • 01 H. T.O 01 FREQUENCY (Hz) OP030701 ::::: Hr':: 100 lOOk ." 1.0 I- ~ >' Ik· 10k lOOk 1M 10M 100M SOURCE RESISTANCE 1m 0P030901 0P030801 v+ 10 LC01170t DS018801 Figure 4: Channel Separation Test Circuit Figure 3: Offset Voltage Null Circuit CHANNEL SEPARATION " 0 Channel separation or crosstalk is measured using the circuit of Figure 4. One amplifier is driven so that its output swings ±10V; the signal amplitude seen in the other amplifier (referred to the input) is then measured. Typical performance is shown in Figure 5. . VOUT (A) Channel Separation = 20 log ( VIN (8) T1~ ~ ·c .... - I R=} I' ~ ) 10 10 '00 ~ 't 'Ok lOOk FREQUENCY (Hz) ,M OP031001 Figure 5: Channel Separation Performance 4-77 Note: All typical values have been guaranteed by characterization and are not tested. .. ICL8043 I APPLICATIONS as a normal amplifier while the voltage necesSlity to zero its offset voltage is stored on the integrator comprised of A2 and Ct. Applications for any dual amplifier fall into two categories. There are those which use the two-in-one package concept simply to save circuit-b9ard space and cost, but more interesting are those circuits whete the two sides of the dual are used to complement one another in a 'subsystem application. The circUits which follow have been selected on this basis. The advantage of .this circuit is that it allows chopper amplifier performance to be achieved at one-tenth the cost. The only limitation is that during the offset nulling mode, A1 is disconnected from the input. However, in most data acquisition systems, many inputs are scanned sequentially. It is fairly simple to synchronize the offset nulling operation so that it does not occur when that particular amplifier is being "looked at". For the component values shown in F;=igure 3, and assuming a total leakage of 50pA at the inverting input of A2, the offset voltage referred to the input of At will drift away from zero at only 40p.V/sec. Thus, the offset nulling information stored on Ct can be "refreshed" relatively infrequently. The measured offset voltage of At during the amplification mode was 11 p.V; offset voltage drift with temperature was less than 0.1 p.V AUTOMATIC OFFSET SUPPRESSION CIRCUIT The circuit shpwn in Figure 6 uses one amplifier (At) as a normal gain stage, whil!3 the other (A2) forms pari of an offset voltage zeroing loop. There are two modes of operation which occur sequentially. First, an offset null correction mode occurs during which the offset voltage of At is nulled out. Following this nulling operation, At is used rc. TC026301 'SW1, SW2, .. SW3 ARE ALL PART OF A SINGLE IH5043 CMOS ANALOG SWITCH CONNECTED AS SHOWN IN FIGURE 6(b) Figure 6(a): Automatic Offset Null Circuit +IV +l1V LOGIC IM'UT CDD18001 Figure 6(b) 4-78 Note: All typical values have been guaranteed by characterization and are not tested. . ICL8043 ..... ~- HORIZONTAL ~ 50MSIDIV ~~ WF015301 Figure 7: Staircase Generator Circuit 1H5042 ,. 1k!1 HORIZONTAl.. '" 2GOmSIDIY VOUT YREF WF015401 Figure 8.: Analog Counter Circuit STAIRCASE GENERATOR ground to assure complete discharge. The upper trip point could then be adjusted independently to determine the pulse count. The circuit shown in Figure 7 is a high input impedance version of the so-called "diode pump" or staircase generator. Note that charge transfer takes place at the negativegoing edge of the input-signal. SAMPLE & HOLD CIRCUIT Two important properties of the 8043 are used to advantage in this circuit. The low input bias currents give rise to slow output decay rates ("droop") in the hold mode, while the high slew rate (6V/IJS) improves the tracking speed and the response time of the circuit. See Figure 6. The ability of the circuit to track fast moving inputs is shown in Figure 10A. The upper waveform is the input (10V/div), the lower waveform the output (5V/div). The logic input is high. Actual sample and hold waveforms are shown in Figure 10B. The center waveform is the analog input, a ramp moving at about 67V!ms, the lower waveform is the logic input to the sample & hold; a logic" 1" initiates the sample mode. The upper waveform is the output, displaced by about 1 scope division (2V) from the input to avoid superimposing traces. The hold mode, during which the output remains constant, is clearly visible. At the beginning of a sample period, the output takes about 81JS to catch up with the input, after which it tracks until the next hold period. The most common application for staircase generators is in low cost counters. By resetting the capacitor when the output reaches a predetermined level, the circuit may be made to count reliably up to a maximum of about 10. A straightforward circuit using a LM311 for the level detector, and a CMOS analog gate to discharge the capacitor, is shown in Figure 8. An important property of this type of counter is the ease with which the count can be changed; it is only necessary to change the voltage at which the comparator trips; A low cost A-O converter can also be designed using the same principle since the digital count between reset periods is directly proportional to the analog voltage used as a reference for the comparator. A considerable amount of hysteresis is used in the comparator shown in Figure 8. This. ensures that the capacitor is completely discharged during the reset period. In a more sophisticated circuit, a dual comparator "window detector" could be used, the lower trip point set close to 4-79 Note: All typical values. have been guaranteed by characterization and are not tested. ~ ICLa043 51! -11V 10 7 ANALOG . OUTPUT 11 INPUT I -11V • • 10.000 pF POLYSTYRENE +av = > IIAIIPLI MODE IH5043 IN = > HOLD MODE LC011801 Figure 9: Sample And Hold Circuit ....... r ....... ........ A. l \ r ....... ....... \ WF015501 r\ \,. ..... ~ r-.... ...... , ~ TOP: INPUT (10V/DIV) BOTTOM: OUTPUT (5V/DIV) HORIZONTAL: 10jlll/QIV ....... -- WF015601 TOP: 2V1DIV CENTER: 2V1DIV BOTTOM: 10VlDIV HORIZONTAL: 10jlll/DIV Figure 10A . 4-80 Note: All typical values have been guaranteed by characterization· and are not tested. Figure 10B . ICL8043 .. INSTRUMENTATION AMPLIFIER A dual JFET-input operational amplifier is an attractive component around which to build an instrumentation amplifier because of the high input resistance. The circuit shown in Figure 11 uses the popular triple op-amp approach. The output amplifier is a High Speed 741 (741 HS, slew rate guaranteed ~ 0.7V/p.s) so that the high slew rate of the 8043 is utilized to the full extent. Input resistance of the circuit (either input, regardless of gain configuration) is in excess of 1012 ohms. For the component values showl), the overall amplifier "R1 + R2 gain is 200 (front end gain = - - - , back end gain, = Rs/R4). R2 Common mode rejection is largely determined by the matching between R4 and R5, and RS and R7. In applications where offset nulling is required, a single potentiometer can be connected as shown in Figure 12. Another popular circuit is given in Figure 13. In this case the gain is 1 + R1/R2, and the CMRR determined by the match between R1 and R4, R2 and R3. For more information on FET input operational amplifiers, see Intersil Application Bulletin A005 "The 8007: A High Performance FET-input Operational Amplifier." AF030211 Figure 13: Modified Instrumentation Amplifier .. .. ... '" AF0300tI Figure 11: Instrumentation Amplifier AF030111 Figure 12: Offset Nulling Both Amplifiers With One Potentiometer Note: All tvDical values have been auaranteed bv characterization and are not tested. ICL8048/1CL8049 Log! Antilog' Amplifier GENERAL DESCR:IPTION FEATURES The 8048 is a monolithic logarithmic amplifier capable of handling six decades of current input, or three decades of voltage input. It is fully temperature, compensated and is nominally designed to provide 1 volt of output for each decade change of input. For increased flexibility, the scale factor, reference current and offset voltage are externally adjustable. . The 8049 is the antilogarithmic counterpart ofthe 8048; it . nominally generates one decade of output voltage for each 1 volt change at the input. • • • • • • 1/2% Full Scale Accuracy Temperature Compensated for O·C t.o + 70·C Operation Scale Factor 1VIDecade, Adjustable 120dB Dynamic Current Range (8048) 60dB Dynamic Voltage Range (8048 & 8049) Dual JFET-Input Op-Amps ORDERING INFORMATION PART NUMBER ERROR (25·C) TEMPERATURE RANGE ICL8048BCJE 30mV O·C to +70·C 16 Pin CERDIP ICL8048BCPE 30mV O·C to +70·C 16 Pin Plastic DIP ICL8048CCJE 60rnV O·C to +70·C 16 Pin CERDIP ICL8048CCPE 60mV O·C to +70·C 16 Pin Plastic DIP ICL8049BCJE 10mV O·C to +70·C 16 Pin CERDIP ICL8049BCPE 10mV O·C to +70·C 16 Pin Plastic DIP ICL8049CCJE 25mV O·C to +70·C 16 Pin CERDIP ICL8049CCPE 25mV O·C to +70·C 16 Pin Plastic DIP PACKAGE .,'NPUT .--r-----t.:"f'I,OOT v,. ~'. \ V,. GAl. At OUTPUT A10UTPUT 05019021 05019121 (ICL8048) (ICL8049) Figure 1: Functional Diagram GROUND' A, INPUT GAIN IREF NO CONNECnoN 3 ,.. NO CONNECTION A1 OFFSET NULL .. 13 A2 OFFSET NOLL A, OFFSET NULL 4 A1 OFFSET NULL 5 11 A2 OFFSET NULL A1 OFFSET NULL A10UTPUT NO CONNECTION , • . 10 vYour A, OUTPUT 7 NO CONNECTION VIN 1 NO CONN~CTION CD018111 GROUND A21NPUT A2 OFFSET NULL 1 A20FFSET NULL v+ o Your • NO CONNECTION CD02081' Figure 2: Pin Configurations (Outline Dwgs, JE, PEl 302800-002 Note: All typical values have been guaranteed by characterization and are not tested. ICL8048/ICL8049 ABSOLUTE MAXIMUM RATINGS (ICL8048) Operating Temperature Range .............. O°C to + 70°C Output Short Circuit Duration ........................ Indefinite Storage Temperature Range ............ -65°C to + 150°C Lead Temperature (Soldering, 10sec) ................. 300°C Supply Voltage ................................................ ±18V liN (Input Current) ............................................. 2mA IREF (Reference Current) ................................... 2mA Voltage between Offset Null and V+ ................. ±O.5V Power Dissipation ......................................... 750mW ELECTRICAL CHARACTERISTICS (ICL8048) Vs = ±15V, TA = 25°C, IREF = 1rnA, scale factor adjusted for 1V1decade unless otherwise specified. PARAMETER 8048BC TEST CONDITIONS MIN TYP 8048CC MAX MIN TYP UNIT MAX Dynamic Range liN (lnA - 1mA) VIN (10mV - 10V) RIN = 10k!1 Error, % of Fu!1 Scale TA = 25°C, liN = InA to lmA .20 0.5 .25 1.0 % Error•. % of Full Scale TA-O°C to +70·C. liN = InA to lmA .60 1.25 .80 2.5 % Error, Absolute Value TA - 25·C, liN -InA to lmA 12 30 14 60 mV Error, Absolute Value TA=O·C to +70·C liN = InA to lmA 36 75 50 150 mV Temperature Coefficient of VOUT liN = InA to lmA O.B 0.8 Power Supply Rejection Ratio R"ferred to Output 2.5 2.5 Offset Voltage (AI & A2) Before Nulling 15 Wideband Noise At Output, for liN = 1COIlA Output Voltage Swing 120 60 dB dB 120 60 mvrc mVIV 15 25 250 50 "V(RMS) V RL -10k!1 ±12 ±14 ±12 ±14 Rl,=2k!1 ±10 ±13 ±10 ±13 Power Consumption Supply Current mV 250 V 150 200 150 200 mW 5 6.7 5 6:7 mA TYPICAL PERFORMANCE CHARACTERISTICS TRANSFER FUNCTION FOR CURRENT INPUTS TRANSFER. FUNCTION FOR VOLTAGE INPUTS SMALL SIGNAL BANDWIDTH AS A FUNCTION OF INPUT CURRENT ..... i ~ IREF-'mAo .... r- -- - i--r- I:I V vt - - -- -- - ~ ~ r--- ---- -- -.- -- -j "'" -- i;1 ~ '0 - 10 11 OP031101 MAXIMUM ERROR VOLTAGE AT THE OUTPUT AS A FUNCTION OF INPUT CURRENT 200 :;: ~ '.i ~ 0 > E I 1 -I I '25 ~ :> so ° 10·' .~ > I ~ . ! '" 804B Be 125"CI 25 J 10-8 10- 7 10-1 1 10'S 10-4 10-':J INPUT CURRENT I"'''PSI 10-5 OP031201 c tI048 Ie IO"C 10 10"CI 8048 cc 125~C) IS 10 7 OPOOl301 ". .so .,. " III I"·N·'O'" .,. 81MB CC fO"C to 1O"el 100 111 I 1111 lll.JJ:8i .00 ,. 8048 cc so ,. ° SMALL SIGNAL VOLTAGE GAIN AS A FUNCTION OF INPUT VOLTAGE FOR RS= 10kn '000 "'" 1011'1'1 III (Rs" 'Olin., n ,ov IV '0 , _0' lmV .o.V'N Iii I -}_. -10mV /ogloe Wi\i'iT" - -. You: "IN :±f 1ft °, INPUT VOLTAGE QPOS140r ~'IIOLTAGE GAIN· 125~CI ~.ct.-;ti l00mY 10-3 INPUT CUARENT IAM'SI MAXIMUM ERROR VOLTAGE AT THE OUTPUT AS A FUNCTION OF INPUT VOLTAGE !:l: 8CM8 CC IO"C 107O"CI .so '00 '" '~" '" I I 17S 10 • INPUT CURRENT I AMPS I INPUT VOLTAGE ,,~v;v I "~ lOOn," " 'ov INPUT VOLTAGE QP031501 4-83 Note: All typical values have baan guaranteed by characterization and are not tested. 0P031601 I ..... n 2 I'" _ CD ICL8048/ICL8049 ABSOLUTE MAXIMUM RATINGS (ICL8049) Supply Voltage ............ '.................•...'; .............. ±18V VIN (Input Voltage) ....•......•........,•..............•...... ±1SV IREF (Reference Current) .............•..................... 2mA Voltage between Offset Null and V+ ..............•.. ±o.SV Power Dissipation .•...•..•................................ 7S0mW Operating Temperature Range .............. O·C to + 70·C Output Short Circuit Duration ........................ Indefinite Storage Temperature Range ............ -6S·C to + 1S0·C Lead Temperature (Soldering, 10soo) ................. 300·C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. and functional operation of the device at these or any other conditions above those Indicated in the operational seclions of the specHications is not implied. Exposure to absolute maximum rating conditions 'for extended periods may affact device reliability. ELECTRICAL CHARACTERISTICS (ICL8049) Vs = ± 1SV, TA = 2S·C, IREF = 1mA, scale factor adjusted for 1 decade (out) per volt (in), unless otherwise specified. 8049BC PARAMETER 8049CC UNIT TEST CONDITIONS MIN TYP MAX MIN TYP MAX Dynamic Range (VOUT) Vour-10mV to 10V Error. Absolute Value TA = 2S·C. OV:S VIN:S 3V 3 10 5 25 mV Error. Absolute Value TA = O·C to + 70·C. OV:SVIN:S3V 20 75 30 150 mV Temperature Coefficient. Referred to VIN VIN ~3V 0.38 0.55 Power Supply Rejection Ratio Referred to Input, for VN-OV 2.0 2.0 60 Offset Voltage (At &: A2) Before Nulling 15 Wideband Noise Referred to Input, for VIN sOV 26 Output Voltage Swing dB 60 25 IS mV 50 26 p.V(RMS) V RL= 10kn ±12 tl4 ±12 ±14 RL=2kn ±IO ±13 ±IO ±13 Power Consumption mVl·C p.VIV V 150 200 150 200 mW 5 6.7 5 6.7 rnA Supply Current TYPICAL PERFORMANCE CHARACTERISTICS TRANSfER FUNCTION (VOUT AS A FUNCTION OF VIN) '0 MAXIMUM ERROR VOLTAGE REFERRED TO THE INPUT AS A FUNCTION OF VIN r-,....,........--..--...-.,............ .0 r--r-..,.....,..--.---r--,,............, .00' L.....L.....I..-L--I--ll.-L...J....JI -4 -3 -2 -1 0 +1 +2 +3 .4 ,,..PUT VOLTAGE (VI INPUT VOLTAGE (VI OP031701 OP031801 4-84 Note: All typical values have been guaranteed by characterization and are not tested. .D~DIl ICL8048/ICL8049 TYPICAL PERFORMANCE CHARACTERISTICS (CONT.) SMALL SIGNAL BANDWIDTH AS A FUNCTION OF INPUT VOLTAGE SMALL SIGNAL VOLTAGE GAIN AS A FUNCTION OF INPUT VOLTAGE -100 I ~ ~ :i IREF"' lmA. -lMr--r~~~-+--+--+~ -:~=-~ - - -- -10 i'\. z C " loo.""I.I',--.f---+~_- - ____ --- I - - - : = -- -' 10' i -23 ,. r--- -- -- w ~g -= I--- -0.0 1 o "f'\ -- -- r- -- -t-- ,J ICL8048 OFFSET AND SCALE FACTOR ADJUSTMENT'" The ICL8048 relies for its operation on the well-known exponential relationship between the collector current and the base-emitter voltage of a transistor: 11 A log amp, unlike an op-amp, cannot be offset adjusted by simply grounding the input. This is because the log of zero approaches minus infinity; reducing the input current to zero starves 01 of collector current and opens the feedback loop around Al. Instead, it is necessary to zero the offset voltage of Al and A2 separately, and then to adjust the scale factor. Referring to Figure 3, this is done as follows: 1) Temporarily connect a 10kU resistor (RO) between pins 2 and 7. With no input voltage, adjust R4 until the output· of Al (pin 7) is zero. Remove RO. Note that for a current input, this adjustment is not necessary since the offset voltage of Al does not cause any error for current-source inputs. 2) Set liN = IREF = lmA. Adjust Rs such that the output of A2 (pin 10) is zero. 3) Set liN = lIlA, IREF = 1mA. Adjust R2 for VOUT = 3 volts (for a 1 volt/decade scale factor) or 6 volts (for a 2 volt/decade scale factor). Step #3 determines the scale factor. Setting liN = lIlA optimizes the scale factor adjustment over a fairly wide dynamic range, from 1mA to 1nA. Clearly, if the 8048 is to be used for inputs which only span the range 100pA to 1mA, it would be better to set liN = 1001lA in Step #3. Similarly, adjustment for other scale fa«tors would require different liN and VOUT values. (1) For base-emitter voltages greater than l00mV, Eq. (1) becomes IC = IseQVBE/kT (2) From Eq. (2), it can be shown that for two identical transistors operating at different collector currents, the VBE difference (~VBE) is given by: = -2.303 xkT - log10 [IC1] IC2 q (3) Referring to Figure 3, it is clear that the potential at the collector of 02 is equal to the ~ VSE between 01 and 02. The output voltage is ~ VSE multiplied by tl1egain of A2: (Rf+R2R2)(kT)109l0 [~] q IREF r-- - -- r- -- 1--- -- I OP032001 ICL8048 DETAILED DESCRIPTION IC = Is[e qVBE/kT - -i'\. - I INPUT VOLTAGE tVI 0P031901 VOUT = -2.303 I -Il 1 INPUT VOLTAGE IV) ~VBE '\ -- -- n (4) "See A053 for an automatic offset nulling circuit. 4t The expression 2.303 x has a numeri~al value of 59mV at 25°C; thus in order to generate 1 volt/decade at the output, the ratio (Rl + R2)/R2 is chosen to be 16.9 For this scale factor to hold constant as a function of temperature, the (Rl + R2)/R2 term must have a l/T characteristic to compensate for kT/q. In the ICL8048 this is achieved by making Rla thin film resistor, deposited on the monolithic chip. It has a nominal value of 15.9kn at 25°C, and its temperature coefficient is carefully designed to provide the necessary compensation. Resistor R2 is external and should be a low T.C. type; it should have a nominal value of 1kn to provide 1 volt/ decade, and must have an adjustment range of ±20% to allow for production variations in the absolute value of R1. 4-85 Note: All typical values have been guaranteed by characterization and are not tested. II ~ 0. ···.lIn~OI1. ICLa048/1C~L8049 -a ! R. GROUNO ,5.111W c. GAIN 15 A.OUTPUT .{ I R. 'I L. _ ""1M- _ ...J 'CJI(O . - (LOW T.c.) ,KO LC028801 Figure 3: ICL8048 Offset and Scale Factor Adjustment ICLB049 DETAILED DESCRIPTION' For voltage references equation 7 becomes The ICL8049 relies on the'sam8 logarithmic properties Of the transistor as the ICL8048; The input voltage forces a specific 6.VSE between .01 and Q2 (Figure 4). This VSE difference is converted into Ii difference of collector currents by the transistor pair. The equation governing the behavior of the transistor pair is derived from (2) on the . previous page and is. as follows: ROUT [ -R2 qVIN] VOUT=VREFX-- exp x-RREF (R1 + R2) kT ICL8049 OFFSET AND SCALE' FACTOR ADJUSTMENT* As with the IQg amplifier, the antilog amplifier requires three adjustments. The first step is to null out the offset voltage of A2. This is accomplished by reverse biasing the base-emitter of Q2. A2 then operates as a unity gain buffer with a grounded input. The second step forces VIN = 0; the output is adjusted for VOUT = 10V.Thls step essentially "anchors" one point on the transfer function. The third step applies a specific input and adjusts the output to the correct voltage. This sets the scale factor. Referring to Figure 4, the exact procedure for 1 deCade/volt is as follows: 1) Connect the input (pin #" 16) to + l5V. This reverse biases the base-emitter of Q2. Adjust R7 for VOUT - OV. Disconnect the input from + l5V. 2) Connect the input to Ground. Adjust R4 for VOUT = 10V. Disconnect the input from Ground. 3) Connect the input to a precise 2V supply and adjust R2 for VOUT -100mV. . The procedure outlined above optimizes the performance over a 3 decade range at the output (i.e., VOUT froml0mV to 10V). For a more limited· range of output voltages, for example 1V to 10V, it would be better to use a precise 1 volt supply and adjust for VOUT = lV. For other scale factors /!.nd/or starting points, different values for R2 and RREF will be needed, but the same basic procedure applies. 'IC1 = exp[q6.VSE] Ic:! . kT When numerical values for q/kT are put into this equation, it is found that a 6.VSE of 59mV (at 25°C) is required to change the collector current ratio by a factor of ten. But for ease of application; it is desirable that a 1 volt cHange at the input'generate a tenfold change at the output. The requited input attenuation is achieved by the network comprising R1 and R2. In order that scale factors other than one decade per volt may be selected, R2 is external to the chip. It should have a value. of 1kn, adjustable ± 20%, for one decade per volt. R1 is a thin film resistor deposited on the monolithic chip; its temperature characteristics are chosen to compensate the temperature dependence of equation 5, as explained on the previous page. The overall transfer function is as follows: lOUT [-R2 qVIN] IREF = exp (R1 + R2) x kT (6) Substituting VOUT = lOUT x ROUT gives: VOUT = ROUT IREF exp [ -R2 qVIN] x-(R1 + R2) kT (8) (7) 'See A053 for an automatic offsel. nulling circuit 4-86 Note: All Iypicel values have been guaranteed by characterization and are' not tested. .U~U[l ICL8048/ICL8049 ,..(Ii . -.p ! .. CD ..... C+1Il/) R. 1OICO .... ... c. . 7 "'pF .... CD 0 CD 1OICO • +- 14~IOUT R• R. _0 R. 11<0 KO .., .... RouT CLOW T.e.) .. _0 R. . 'KO VouT . . y. LC028701 Figure 4: ICL8049 Offset and Scale Factor Adjustment EFFECT OF VARYING "K" ON THE LOG AMPLIFIER APPLICATIONS INFORMATION ICL8048 Scale Factor Adjustment The scale factor adjustment procedures outlined previously for the ICl8048 and ICl8049, are primarily directed towards setting up 1 volt (~VOUT) per decade (~IIN or ~VIN) for the log amp, or one decade (LWOUT) per volt (~VIN) for the antilog amp. This corresponds to K = 1 in the respective transfer functions: log Amp: VOUT = -K log liN 10[-1 IREF . 'REF·'mA ROUT -10kn (9) V - IN Antilog Amp: VOUT = ROUT IREF 10-K (10) INPUT VOLTAGE IV) By adjusting R2 (Figure 3 .and Figure 4) the scale factor "K" in equation 9 and 10 can be varied. The effect of changing Kis shown graphically in Figure 5 for the log amp, and Figure 6 for the antilog amp. The nominal value of R2 required to give a specific value of K can be determined from equation 11. It should be remembered that R1 has a ±20% tolerance in absolute value, so that allowance shall be made for adjusting the nominal value of R2 by ±20%. R2 = 941 (K-.059) n OP032101 Figure 5 EFFECT OF VARYING "K" ON THE ANTILOG AMPLIFIER 12 ~ (11) ~ ....... ~ g ~ Although the op-amps in both the ICl8048 and the ICl8049 are compensated for unity gain, some additional frequency compensation is required. This is because the log transistors inthe feedback loop add to the loop gain. In the 8048, 150 pF should be connected between Pins 2 and 7 (Figure 3). In the 8049, 200 pF between Pins 3 and 7 is recommended (Figure 4). ........ IREF·,rnA "- ~ ~.~ ..... -. ~ .::". L'- ~ Frequency Compensation ~ 10 ~ -r- 6 -2 "- l"11li 10-1010-1 10-1 10-7 10-1 10-5 10-4 10-3 INPUT CURRENT CAMPS) OPOG2201 Figure 6 4-87 Note: All typical values have been guaranteed by characterization and ara not tasted. i1CL8048/ICL8049 d Error Analysis ::::. ! 2_ d_· Performing a meaningful error analysis of a circuit containing log and antilog amplifiers is more complex than dealing with a similar circuit involving only op-amps. In this data sheet every effort has been made to simplify the analysis task, without in any way compromising the validity of the resultant numbers. The key difference in making error calculations in log/ antilog amps, compared with op-amps, is that the gain of the former is a function of the input signal level. Thus, it is necessary, when referring errors from output to input, or vice versa, to check the input voltage level, then determine the gain of the circuit by referring to the graphs given in the Typical Performance Characteristics section. The various error terms in the log amplifier, the ICL8048, are Referred To the Output (RTO) of the device. The error terms in the antilog amplifier, the ICl:.8049, are Referred To the Input (RTI) of the device. The errors are expressed in this way because in the majority of systems Ii number of log amps interface with an antilog amp, as shown in Figure 7. input voltage. This is because the output amplifier, A2, has an offset voltage drift which is directly transmitted to the output. When this error is referred to the input, it must be divided by the voltage gain, which is input voltage dependent. At VIN = 3V, for example, errors at the output are multiplied by 1/.023 (= 43.5) when referred to the input. TRANSFER FUNCTION FOR CURRENT INPUTS ll: ~ ol--"'Ioo.:+-+"""io':: ~-.~+-+""'"~ ~ -4 1---1C---+--+-+="'"40.O-+-~ ~ -.I--I--I--I--I--I--~ ~L-~~~~ 10- 10 lo-t ,0-' __~~~ 10- 7 10-1 10-' 10-4 10-3 INPUT CURRENT IAMI'S) Actual output will Ii. within sheded .... for 8048 BC 8t 25·C OP032301 Figure 8 ERROR OUE TO A IRTO) -.mV It is important to note that both the ICL8048 and the ICL8049 require positive values of IREF,· and the input (ICL8048) or output (ICL8049) currents (or voltages) respectively must also be positive. Application of negative liN to the ICL8048 or negative IREF to either circuit will cause malfunction, 'and if maintained for long periods, would lead to device degradation. Some protection can be provided by placing a diode between pin 7 and ground. LDOO700f Figure 7 It is very straightforward to estimate the system error at node (A) by taking the square root of the sum-of-the squares of the errors of each contributing block. Total Error = v'x2 + y2 + z2 at (A) If required, this error can be referred to the system output through the voltage gain of the antilog circuit, using the voltage gain versus input voltage plot. The numerical values of x, y, and z in the above equation are obtained from the maximum error voltage plots. For example, with the ICL8048BC, the maximum error at the output is 30mV at 25°C. This means that the measured output will be within 30mV of the theoretical transfer function, provided the unit has been adjusted per the procedures described previously. Figl,!re 8 illustrates this point. To determine the maximum error over the operating temperatu~e range, the 0 to 70°C absolute error values given in the table of electrical characteristics should be used. For intermediate temperatures, assume a linear increase in the error between the 25°C value and the 70·C value. For the antilog amplifier, the only difference is that the error refers to the input, i.e., the horizontal axis. It will be noticed that the maximum error voltage of the ICL8049, over the temperature range, is strongly dependent on the SETTING UP THE REFERENCE CURRENT In both the ICL8048 and the ICl8049 the input current reference pin (lREF) is not a true virtual ground. For the. ICl8048, a fraction of the output voltage is seen on Pin 16 (Figure 3). This does not constitute an appreciable error provided VREF is much greater than this voltage. A 10V or 15V reference satisfies this condition. For the ICl8049, a fraction of the input voltage appears on Pin 3 (Figure 4), placing a similar restraint on the value of VREF. Alternatively, IREF can be provided from a true current source. One method of implementing such a current source is shown in Figure 9. LOG OF RATIO CIRCUIT, DIVISION The 8048 may be used to generate the log ofa ratio by modulating the IREF input. The transfer function remains the same, as defined by equation 9: VOUT = -Klog10 [~] IREF (9) Clearly it is possible to perform division using just one ICl8048, folJowed by an ICl8049. For multiplication, it is generally necessary to use two log amps, summing their outputs into an antilog amp. To avoid the problems caused by the IREF input not being a true virtual ground (discussed in the previous section), the circuit of Figure 9 is again recommended if the IREF input is to be modulated. Note: All typical values have been guaranteed by characterization and are not tested, ICL8048/ICL8049 ERROR, % OF FULL SCALE The error as a percentage of full scale can be obtained from the following relationship: .1SY VREFf J ., 100 x Error, absolute value Error, % of Full Scale = -::--:::--=---:-:-:--FuliScale Output Voltage TEMPERATURE COEFFICIENT OF VOUT OR VIN For the ICL804S the temperature coefficient refers to the drift with temperature of VOUT for a constant input current. For the ICL8049 it is the temperature drift of the input voltage required to hold a constant value of VOUT. POWER SUPPL Y REJECTION RA TlO The ratio of the voltage change in the linear axis of the transfer function (VOUT for the ICLS048, VIN for the ICLS049) to the change in the supply voltage, assuming that the log axis is held constant. WIDEBAND NOISE For the ICL804S, this is the noise occurring at the output under the specified conditions. In the case of the ICLS049, the noise is referred to the input. SCALE FACTOR For the log amp, the scale factor (K) is the voltage change at the output for a decade (i. e. 10:1) change at the input. For the antilog amp, the scale factor is the voltage change required at the input to cause a one decade change at the output. See equations 9 and 10. 10----1 2NUII 10"" IREf PIN 18 ON B04B) ( TO TO PIN 3 ON 1041 AF030301 Figure 9 DEFINITION OF TERMS In the definitions which follow, it will be noted that the various error terms are referred to the output of the log amp, and to the input of the antilog amp. The reason for this is explained on the previous page. DYNAMIC RANGE The dynamic range of the ICL8048 refers to the range of input voltages or currents over which the device is guaranteed to operate. For the ICL8049 the dynamic range refers to the range of output voltage over which the device is guaranteed to operate. ERROR, ABSOLUTE VALUE The absolute error is a measure of the deviation from the theoretical transfer function, after performing the offset and scale factor adjustments as outlined, (ICLS04S) or (ICL8049). It is expressed in mV and referred to the linear axis of the transfer function plot. Thus, in the case of the ICL8048, it is a measu,re of the deviation from the theoretical output voltage for a given input current or voltage. For the ICL8049 it is a measure of the deviation from the theoretical input voltage required to generate a specific output voltage. The absolute error specification is guaranteed over the dynamic range. APPLICATION NOTES For further applications assistance, see A007 "The ICL8048/S049 Monolithic Log-Antilog Amplifi- ers", by Ray Hendry ~9 Note: All typical values have been guaranteed by characterization and are not tested. ia ICL8083 Power Transistor DriverlAmplifier - GENERAL DESCRIPTION FEATURES The ICLa063 is a. unique monolithic power transistor driver and amplifier that allows construction of minimum chip power amplifier systems. It includes built in safe operating area circuitry, short circuit protection .and voltage regulators, and i~ primarily intended for driving complementary output stages. Designed to operate with all varieties of operational amplifiers and other functions, two external power transistors, and a to 10 passive components, the ICLa063 is ideal for use in such applications as linear and rotary actuator drivers, stepper motor drivers, servo motor drivers, power supplies, power DACs and electronically controlled orifices. The ICLa063 takes the output levels (typically ± 11 V) from an op amp and boosts them to ±30V to drive power transistors, (e.g. 2N3055 (NPN) and 2N37a9 (PNP». The outputs from the ICLa063 supply up to 100mA to the base leads of the external power transistors. The amplifier-driver contains internal positive and negative regulators, to power an op amp or other device; thus, only ±30V supplies are needed for a complete power amp. • • • • • • Converts ±12V Outputs From Op Amps and Other Linear Devices to ± 30V.. Levels When Used In Conjunction With General-Purpose Op Amps and External Complementary Power Transistors, System Can Deliver> SO Watts to External Loads Built-in &lfe Area Protection and Short-Circuit Protection Produces 2SmA Quiescent Current in Power Output Stage Built-In ± 13V Regulators to Power Op Amps or Other External Functions SOOkn Input Impedance With RBIAS 1Mn = ORDERING INFORMATION PART NUMBER TEMPERATURE RANGE ICL8063MJE -55°C to + 125°C CERDIP ICL8063CJE O°C to +70°C CERDIP ICL8063CPE O°C to +70°C PLASTIC DIP PACKAGE - VREGOUT , '5 INPUT +VREGOUT -ABIA! 2 FREQ. COMPo CAPAC. PNP BASE DRIVE OUTPUT 5 • '2 GND 11 NPN BASE DRIVE OUTPUT 7 • ,. CURRENT COMP. CAPAC. - RSHORT CKT. PROT. OUTPUT • + RSHORT CKT. PROT. CD018211 08019211 Figure 1: Functional Diagram Figure 2: Pin Configuration 4-90 Note: All typical values have been guaranteed by qharacterizalion and are not tested. .D~DIL ICL8063 i ABSOLUTE MAXIMUM RATINGS Supply Voltage ................................................ ±3SV Power Dissipation ......................................... SOOmW Input Voltage (Note 1) ......................................±30V Regulator Output Currents ................................ 10mA Operating Temperature Range ICLS063MJE ........................ -SS'C to + 12S'C ICL8063CPE ............................. O·C to + 70'C ICL8063CJE ............................. O'C to + 70'C Storage Temperature Range ............ -6S'C to + 1S0'C Lead Temperature (Soldering. 10sec) ................. 300·C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. ,These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods 'may affect device reliability. ELECTRICAL CHARACTERISTICS (TA = 2S'C; VSUPPLY = ±30V) MINIMAX LIMITS SYMBOL CHARACTERISTIC TEST CONDITIONS O·C -SS'C +2S·C + 12S·C Max. Offset Voltage See Figure 3 150 50 50 10H Min. Positive Drive Current See Figure 4 ' 50 50 50 loa Max. Positive Output Quiescent Current See Figure 5 500 250 250 10l Min. Negative Drive Current See Figure 4 25 25 25 10l Max. Negative Output Quiescent Current See Figure 6 VREG Regulator Output Voltages Range IREG Regulator Output Current (See Note 2) ZIN A.C. Input Impedance See Figure 8 VSUPPlY Power Supply Range 10 Power Supply Quiescent Currents Range of Voltage Gain VOUT(MIN) Minimum Output Swing IBIAS Input Bias' -Current NOTES: UNIT ICL8063C ICL8063M Vos AV P , +2S'C +70·C 75 mV 40 mA 300 I1A 20 mA 500 250 250 ±13.7 ±1.2V ±13.7 ±I.OV ±13.7 ±1.5V 300 10 10 10 mA 400 ,400 (Typ) kG ±13.7 !I.OV (Typ) ±13.7 ±I.OV ±5 to ±35V I1A ±13.7 ±1.0 V V V 10 6 6 7 mA 6±2 6±2 6±2 8±2 VIV VIN until VOUT flattens ±27 ±27 ±27 ±27 V See Figure 10 100 100 100 100 I1A See Figure 9 VIN=8Vp-p See Figure 9; Increase 1. For supply voltages less than ± 30V the absolute, maximum input voltage is equal ·to the supply voltage. 2. 'Care should be taken to ensure that maximum Power dissipation' is not' exCeeded. 4-91 Note: All typical values have been guaranteed by characterization and are not tested. IIn~nlL ...... +3D¥ tllli ~--"tIOl n2, and Ra for optimum sensitivity. That means making Ra "'I to minimize the voltage drop across Ra (the drop wili b(;, i i.'lrnp x 1 ohm or 1 volt). If 1 amp/volt sensitivity is d{;sirabIE) let R2 = R1 = 10kSlto minimize feedback current '>fmr. Thl111 a ± 1V input voltage will produce a ± 1 amp curr-;,mt through the motor. n Capacitors should be at least 50 volts working voltage c,nd all msistors 1/2W, except for those valued at 0.4 ohms. POI/,mr across Ra = I xV = 1 amp x 1 volt = 1 watt, so at least a 2 watt value should be used. Use large heat sinks for the 2N305G and 2N~791 power transistors. A Delta NC-641 ()1' the equivalent is appropriate. Use a thermal compound when mounting the transistor to the heat sink. (See InterSi! lCH8510 data sheet for further information). ..... .... '" @ow ... ... .". GAn ~1ouT @IW NOW ' : ' "" (-) IbIRt x Ii; LC013201 Figure 17: Constant Current Motor Drive Building A I-ow Cost 50 Watt per Channel Audio Amplifier ' For about $20 per channel, it is possible to build a high fidelity amplifier using the ICL8063 to drive 8 ohm speakers. Note: Ail typical values have been guaranteed by characterization and are' not tested. ICL8063 'A channel is defined here as all amplification between turntable or tape output and power output. (Figure 18) The input 741 stage is a preamplifier with R.IAA. equalization for records. Following the first 741 stage is a 10kU control pot, whose wiper arm feeds into the power amplifier stage consisting of a second 741, the ICL8063 and the power transistors. To achieve good listening results, selection of proper resistance values in the power amplifier stage is important. Best listening is to be found at a gain value of 6 [(5kU + 1kUI 1kU = 6)]. 3 is a practical minimum, since the first stage 741 preamp puts out only ±10 volt maximum signals, and if maximum power is necessary this value must be multiplied by 3 to get ±30 volt levels at the output of the power amp stage. Each channel delivers about 56 volts p-p across an 8 ohm speaker and this converts to 50 watts RMS power. This is derived as follows: Vrms2 56Vp_p Power = - - - , Vrms = - - 8 ohms 2.82 2 = 20V, (20V) = 400V 2 400V2 Power = - - - = 50 watts RMS Power. 8 ohms Distortion will be < 0.1 % up to about 100Hz, and then it increases as the frequency increases, reaching about 1 % at 20kHz. The ganged switch at the input is for either disc playing or FM, either from an FM tuner or a tape amplifier. Assuming DC coupling on the outputs, there is no need for a DC reference to ground (resistor) for FM position. To clear the signal in the FM pOSition, place a 51 kUresistor to ground as shown in Figure 18 (from FM input position to ground)_ ~ "~J ....... "'".........-. _J 90007601 Figure 18: Hi·Fi Amplifier 4--97 Note: All typical values have been guaranteed by characterization and are not tested. I... ICL8063' +'II---+----PIE--''"""~--__I > .1 'C ~r---~--~--~~-__i \ -I ,. ,.. ,. i 1-(111) OP032601 EOUT 050'.501 Figure 19: Typical Performance Curve of - - vs. Frequency· For Typical Circuit Shown VIN -.. , '" \ ..0----'-----. \ ~ \ 0P002701 .. -- ~-~~-~--~~_+----_+~4 050' .... Figure 20: Typical Performance Curve of Input Impedance Versus Frequency for Typical Circuit Shown Note: I"tarsil offers a hybrid power amplifier similar to that shown in Figure 11. See ICH8510/8520/8530 data Note: All typical values have been guaranteed by characterization and are not tested. s~t for details. LH2108/LH2308 Dual Super-Beta Operational Amplifier GENERAL DESCRIPTION FEATURES The lH210BAllH230BA and lH210B/lH230B series of dual operational amplifiers consist of two lM10BA or lM10B type op amps in a single hermetic package. Featuring all the same performance characteristics of the single device, these duals also offer closer thermal tracking, lower weight, and reduced insertion cost. • • • • • Low Offset Current - 50pA Low Offset Voltage-O.7mV Low Offset Voltage LH2108A: O.3mV LH2108: O.7mV Wide Input Voltage Range-±15V Wide Operating Supply Range - ±3V to ±20V ORDERING INFORMATION PART NUMBER TEMPERATURE RANGE LH210BD -55·C to + 125·C LH2108AD PACKAGE -55·C to + 125·C 16-PIN LH230BD O·C to +70·C CERAMIC LH230BAD O·C to +70·C INV INPUT 4 14 2 16 NON.INV 5 INPUT INV INPUT 12 v~ V+ BALANCE OUTPUT COMPENSATION OUTCOMP, OUTPUT SAL/COMP, BALiCOMPENSATION -IN. V· TIN. -OUT, N/C V· BALANCE OUTPUT COMPENSATION BAI.o OUTPUT OUT, NON-INV INPUT '3 BAL/COMPENSATION V+ CD014401 Figure 1: Functional Diagram (outline dwg DE) COO1451t Figure 2: Pin Configuration 4-99 Note: All typical values have been guaranteed by characterization and are not tested. II I !::!. I ;; 3 LH2108/LH~308 ABSOLUTE MAXIMUM RATINGS Operating Temperature Range· LH21 08A1LH21 08 .....•........... -55°C to + 125°C LH2308A1LH2408 ...................... O°C to + 70°C Storage Temperature Range ............ -65°C to + 150°C Lead Temperature (Soldering. 10sec) ................. 300.oC Supply Voltage ................................................±20V Power Dissipation (Note 1) .•..........................• 500mW Differential Input Current (Note 2) .................... ± 1OmA Input Voltage (Note 3) ................... : .................. ± 15V Output Short Circuit Duration ..................... Continuous ELECTRICAL CHARACTERISTICS (LH2108/LH2308) (See Note 4) LIMITS PARAMETER TEST CONDITIONS UNIT LH2108 LH2308 Input Offset Voltage TA = 2SoC 2.0 7.S Input Offset Current TA = 2SoC 0.2 t.O Input Bias Current TA - 2SoC 2.0 7.0 mV Max nA Max Input Resistance (Note S) TA = 2SoC 30 10 Mn Min Supply Current TA = 2SoC 0.6 0.8 rnA Max Large Signal Voltage Gain TA = 25°C VS·±ISV VOUT-±10V, RL~10kn 50 2S V/mV Min Input Offset Voltage 3.0 10 Average Temperature Coefficient of Input Offset Voltage (Note 8) IS 30 Input Offset Current 0.4 I.S nA Max Average Temperature Coefficient of Input Offset Current (Note 6) 2.5 10 pAloC Max Input Bias Current mV Max pvrc Max 3.0 10 nA Max Supply Current TA=+125°C 0.4 - rnA Max Large Signal Voltege Gain Vs=±ISV, VQUT=±10V RL~ 10kn 2S 15 VlmV Min Output Voltage Swing Vs=±15V, RL=10kn ±13 ±13 Input Voltage Range Vs = ±15V ±13.5 ±14 Common Mode Rejection Ratio VS-±15V, VCM-±13.5V 85 80 Supply Voltage Rejection Ratio ±SV to ±20V 80 80 ELECTRICAL CHARACTERISTICS - V Min dB Min LH2108/LH2308 Input Offset Voltage TA = 2SoC O.S 0.5 mV Max Input Offset Current TA = 2SoC 0.2 nA Max Input Bias Current 2.0 Input Resistance TA - 25°C TA - 2SoC '.0 7.0 30 10 Mn Min Supply Current TA = 25°C 0.6 0.8 rnA Max Large Signal Voltage Gain TA=2SoC VS=±ISV Your = ± 10V, RL ~ 10kn 80 80 VlmV Min 1.0 0.73 mV Max 5 S pvrc Max Input Offset Current 0.4 I.S nA Max Average Temperature Coefficient of Input Offset Current (Note 6) 2.5 10 pArc Max Input Offset Voltage Average Temperature Coefficient of Input Offset Voltage (Note 6) Input Bias Current 3.0 10 nA Max Supply Current TA= + 12SoC 0.4 - rnA Max Large Signal Voltage Gain Vs = ±15V, VOUT= ±10V RL~ 10kn 40 60 V/mV Min Output Voltage Swing VS=±15V, RL=10kn ±13 ±13 Input Voltage Range Vs = ±ISV ±13.S ±14 4-100 Nota: All typical values have been guarantaed by characterization and are not tested: V Min LH2108/LH2308 ELECTRICAL CHARACTERISTICS (CONT.) LIMITS PARAMETER TEST CONDITIONS UNIT LH2108 LH2308 96 96 Common Mode Rejection Ratio Supply Voltage Rejection Ratio NOTES: 96 150·C. and that of the LH23081A dB Min 96 85·C. The Ihermal resistance of the 1. The maximum lunctlon temperature of the LH21 081 A IS IS packages is 100·C C/W, junction to ambient. 2. The inputs are shunted with back-to-back diodes for overvoltage protection. Therefore, excessive current will flow if a differential input voltage in excess of 1V is applied between the inputs unless some lim~ing resistance is used. 3. For supply voltages less than ± 15V, the absolute maximum input voltage is equal to the supply Voltage. 4. These specifications apply for ±5V:S Vs S ±20V and - 55·C S TA S 125·C, unless otherwise specified, and the LH2308A1LH2308 for ±5V:S Vs S 15V and O·C:S TA:S 70·C. 5. Input resistance is guaranteed by Input Bias Current test. 6. For DeSign only, not 100% tested. STANDARD COMPENSATION CIRCUIT ALTERNATE" FREQUENCY COMPENSATION Your FEEDFORWARD COMPENSATION VOUT YOUT Ra +YI Cf"~2 ,+ CO-30pF Cf R3 -Improves rejec:ion of power supply noire by • factor often. C2 = SSOO6501 88006601 . Figure 3: Auxiliary Circuit 4-101 Nota: All typical vsiues have been guaranteed by characterization and are not tested. -=- 2"~ R2 fo=3MHz SSOO8701 I ~ c i! D~D[6 LM108/A, LM308/A Super-Beta Operational Amplifier GENERAL DESCRIPTION FEATURES These differential input, precision amplifiers provide low input currents and offset voltages comparable to FET and chopper stabilized amplifiers. They feature low power consl,lmption over,a supply voltage range of > 2V to ±20V. The amplifiers may be frequency compensated with a single external capacitor. The LM108A and LM308A are high performance selections from the 108/308 amplifier family. • • • • • • Input Bias Current - 2nA Max to 7nA Max Input Offset Current - O.2nA Max to 1nA Max Input Offset VOltage - O.SmV Max to 7.SmV Max 1::Nos/AT-SIl,Vrc to 30llVrC Alosl AT-.2.5pArC to 10pArC Pin for Pin Replacement for 101A/301A ORDERING INFORMATION PART NUMBER TO-99 CAN 8 PIN MINIDIP 14 PIN CERDIP 10 PIN FLATPAK LM108A LM308A LM108AH* LM308AH LM308AN LM108AJ LM308AJ LM108AF LM308AF LM108 LM308 LM108H* LM308H LM308N LM108J LM308J LM108F LM308F - ** DICE LM308/D "If 883C processing is desired add 1883C to part number. ""Parametric MinIMax Limits guaranteed at 25°C only for DICE orders. FREa COMPA8FREa COMP'B -IN y+ +IN OUT v- INVERTING INPUT ,. NON 1~~~TlNG 5 NC (outline dwg PAl TOP VIEW COO16101 (outline dwg JD) aJ01S301 NC COMP GUARD COMP -IN v' +IN OUT y- GUARD TOP VIEW (outline dwg FB-') (outline dwg TV) c0016401 , c0016201 Figure 1: Pin Configurations 4-102 NOte: All typical values have been guaranteed by characterization and are not tested. 302030-002 1I0~OIL LM108/A, LM308/A ABSOLUTE MAXIMUM RATINGS Supply Voltage 10B, 10BA ............................................. ±20V 30B, 30BA ............................................. ±1BV Internal Power Dissipation (Note 1) Metal CAn (TO-99) .............................. SOOmW DiP ••.. ;· .............................................. SOOmW Differential Input Current (Note 2) .................... ±10mA Input Voltage (Note 3) ...................................... ±1SV Output Short-Circuit Duration ......................... Indefinite , Operating Temperature Range W 10B, 10BA ........................... -SS·C to + 12S·C 30BAt...... ·R····· ................. ·6..S~C·Ct to++17S0 Storage30TB,empera 0:C C ';;: ure ange ............ 0 , Lead Temperature (Soldering,10sec) ...... , .......... 300·C i ELECTRICAL CHARACTERISTICS (TA =2S·C unless otherwise specified) (Note 4) PARAMETER TEST CONDITIONS 308 MAX Input Offset Voltage 2.0 Input Offset Current 0.2 Input Bias Current 1.5 Input Resistance Note 5 VS-±20V VS=±15V large Signal Voltage Gain Vs - ±15V, Vour= ±10V RL> 10kn 10 108 308A .TVP Supply Current MIN MIN TVP MAX 7.5 0.3 0.5 1.0 0.2 7 1.5 1.0 7 10 40 40 MIN 30 TYP 0.7 25 0.8 0.3 80 300 108A MAX MIN UNIT TVP MAX 2.0 0.3 0.5 mV 0.05 0.2 0.05 0.2 0.8 2.0 0.8 2.0 nA nA Mn mA mA 70 0.3 0.3 30 70 0.3 0.6 0.6 0.8 300 50 80 300 VlmV 300 THE FOLLOWING SPECIFICATIONS APPLY OVER THE OPERATING TEMPERATURE RANGES Input Offset Voltage 10 0.73 3.0 1.0 Input Offset Current 1.5 .1.5 0.4 0.4 nA 1.0 5.0 p'vrc 0.5 2.5 pArC Average Temperature CoefficiEintof Input Offset Voltage Note 6 Average temperature Coefficient of Input Offset Current Note 6 , 8.0 30 1.0 5.0 3.0 2 10 ·2.0 10 0.5 Input Bias Current Large Signal Voltage Gain 10 Vs = ±15V, Vour= ±10V RL ~ 10kn 15 2.5 3.0 10 15 25 60 Vs = ±15V V5=±15V VCM=±13.5V 80 100 96 110 85 100 96 110 dB Supply Voltage Rejection Ratio ±5V to ±20V 80 96 96 110 80 96 96 110 dB ±13 ±14 ±13 ±14 ±13 ±14 ±13 ±14 VS=±15V, RL=10kn TA = + 125·C, Vs = ±20V ±13.5 nA V/mV Input Voltage Range Supply Current ±13.5 3.0 40 mV Common Mode Rejection Ratio Output Voltage Swing ±13.5 ..~ ,. , ±13.5 0.15 0.4 V 0.15 "0.4 V mA NOTES: 1. Derate Metal Can package at 6.8 mWrc for operation at ambient temperatures above 75·C and the Dual In-Line package at 9mWI ·C 'for operation at ambient temperatures above 95°C. 2. The inputs are shunted with back-to-back diodes for over-voltage protection. Therefore, excessive current will flow if a differential input voltage in excess of tV is applied between the inputs unless some limiting resistance is used. . 3. For' supply voltages less than ± 15V, the maximum input voltage is equal to the supply voltage. 4. Unless otherwise specified, these specHications apply for supply voltages from + 5V to ± 20V for the 108, and 100A and + 5V to ± 15V for the 30B and 30BA. 5.. Input· resistance is guaranteed by Input Bias Current test. 6. For' Design only, not 100% tested. . 4--103 Note: All typical values have been guaranteed by characterization and are not tested. !~ LM108/A,LM308/A . ! INPUT CURRENTS C i... !j, . TYPICAL PERFORMANCE CHARACTERISTICS MAXIMUM DRIFT ERROR 2.0 , lk 1. 5 i t",....., N 1.0 I08A/l08 ~ O. 5 a" r--- t-... - "';> O.2S r-I108 308 t---,=- I-I~ w ~ 10 ....,...." - o" "" r-... 308(308A OFFSET ... 0.20 ~ a>;0.15 ii2 Q .108A/\08 0.10 OtSlT -...J.~ o ,.- I I J/JALIAL 308A 108A J; ~ 108/108A, 1.0 lOOk -5S'C < ~. < 12S'C O·C":T.< 10'C 1M 10M INPUT RESISTANCE TEMPERATURE ('CI ,.- ~ i7 FI .... 308/308A, ··55 -35 -15 5 2S 45 65.85 lQ5 12S MAXIMUM OFFSET ERROR . 100M 0P022201 0P022001 100M 1M 10M INPUT RESISTANCE 1m· 1m 0P022101 POWER SUPPLY REJECTION INPUT NOISE VOLTAGE 120 ·1000 jloo ~400 :; .: 280 0 ~ ... ;;: OPEN LOOP VOLTAGE GAIN ..,80 Rs ·1M ~'00 ~ 40 "...>' t 20 a 0 ia>; -20 100 lk 10k lOOk 1M 10M Rs' lOOk Rs'O 40 10 ·10 I 100 lk 10k lOOk 10 FREOUENCY (Hz! FREQUENCY (Hzl 0P022301 OUTPUT SWING 20 15 SUPPLY VOLTAGEltVI OP022511 OP022411 OPEN LOOP FREQUENCY RESPONSE SUPPLY CURRENT 15 VS' t15V I ... ~~~ ~ \ T.· 12S'C. " " " " " f-- --f"~pF d- T~'crCi o I I I It o 2 4 6 . C.'30pF~ I{- L'::T•• 70'C T.r. ~'C II I T... • -55'C 110 C.'IOOpF- :+,c.. GAIN PHASE ___ 8 01'022601 "10: f-- ~c.. :00 pF - OUTPUT CURRENT ('mAI "10: 1 SUPPLY VOLTAGE (tVl OP022701 Note: All typical values have been guaranteed by characterization and are not tested. 10 100 lk .... ;r- 30 pFFe!! o 10k lOOk 1M 10M FREOUENCY IHzI LM108/A, LM308/A TYPICAL PERFORMANCE CHARACTERISTICS (CONT.) CLOSED LOOP OUTPUT IMPEDANCE 1~ r--r--r--r--~-'=-~ ...§,~ r--H~~~--~-4--~ ~ ~10' r-~-'\r-'\-b~+--4--~ ~ ~ 1~ t--t---li7' ~ 10" 10 16 To' '"z ...~ 8 C," 3pF 1\ C.-30~ i-I it lOUT· ±1 mA 10" "'-......__..........__V;.::S.;.·_,';..;;S.;.V--, 10 100 lk 10k lOOk 1M 10M o lk "" 10k r- '1 r-I-\1H-+::.:r',,{- 1 r-HH-t-++--i"'-'U -2 r-HIH-t-+-,h:~j-.--+-- ~ I=t$!=t=~t~t;~t; ~ 1'-0. lOOk r-r-.r-T--.--.--.-,-- 8 I-+-HH......---·+_·+ 6 I-+-HH.......,-l-·_ ..l---+· 4 I - r H H......---{-·--- Vs" :!:15V ~ 4 I----H<---li----+-- 25'(: ~ 12 ~ :::> l!: VOLTAGE FO!JJ(;ii"i!:·.:, ~ PULSE RESP(Wl:",;: LARGE SIGNAL FREQUENCY RESPONSE -10 I-+-HH......-+-: L....L-&....JL....I~_ 1M FREQUENCY IHzl FREQUENCYIHzI 0P02S00l 0P022901 GUARDING Extra care must be taken in the assembly of printed circuit boards to take full advantage of the low input currents of the 108 amplifier. Boards must be thoroughly cleaned with TCE or alcohol and blown dry with compressed air. After cleaning, the boards should be coated with epoxy or silicone rubber to prevent contamination. Even with properly cleaned and coated boards, leakage currents may cause trouble at 125·C, particularly since the input pins are adjacent to pins that are at supply potentials. This leakage can be significantly reduced by using guarding to lower the voltage difference between the inputs and adjacent metal runs. Input guarding of the 8-lead TO-99 package is accomplished by using a 10-lead pin circle, with the leads of the device formed so that the holes adjacent to the inputs are empty when it is inserted in the board. The guard, which is a conductive ring surrounding the inputs, is connected to a low impedance point that is at approximately the same voltage at the inputs. Leakage currents from high-voltage pins are then absorbed by the guard. The pin configuration of the dual in~line package is designed to facilitate guarding, since the pins adjacent to the inputs are not used (this is different from the standard 741 and 101A pin configuration). ., INVl~~~~ _IVAII\'~-I .I IOOpF lC(J<11:;0! Figure 3: Frequency Compensat9()'ls',; e~r;'~"iG'~ ALTERNATE CIRCUIT IMPROVES FiE,i'l,",:-;1l1~/;:! POWER SUPPLY NOISE BY A FACTOi') Oil' Y',',.;,\ A' Co c, lOpF lC02'4OI Figure 2: Frequency Compensation Circuit STANDARD CIRCUIT 4-105 Note: All typical values have been guarenteed by cheracterization and are not tested. =Video NE/SE592 Amplifier 111 (I) I GENERAL DESCRIPTION FEATURES The NE/SE592 is a monolithic, two-stage, differential output, wideband video amplifier. It offers fixed gains of 100 and 400 without eXternal components and adjustable gains from 0 to 400 with one external resistor. The input stage has been designed so that with the addition of a few external reactive elements between the gain select terminals, the circuit can function as a high pass, low pass, or band pass filter. This feature makes the circuit ideal for use as a video or pulse amplifier in communications, magnetic memories, display, video recorder systems" and floppy disc head amplifiers. The NE/SE592 is a pin-for-pin replacement for the jJA733 in most applications. .... 2.4k • • • .• • 120MHz Bandwidth Adjustable Gains From 0 to 400 Adjustable Pass Band No Frequency Compensation Required Wave Shaping With' Mlnlinal· External Components ORDERING INFORMATION BASIC PART NUMBER PACKAGE TEMP RANGE SES92 -SS·C 10 + 12S·C NES92 O·C 10 +70·C 14-PIN PLASTIC 14-PIN CERDIP la-PIN To-l00 8-PIN MINI DIP - SES92F SES92H - NES92N NES92F NES92H NES92N-8 .. , t---+--1-t--+---.i'""""ovt-+-<>OUTPUT1 '----+---"JIIIo-j--+--<>OUTPUT 2 1IIPUT' G •• ... BDOO6OO1 Figure 1: Functional Diagram (Resistor Values Nominal Only) 14-Pln DIP Package (JD, PO Package) 10-Pln To-100 Package (H Package) 8-Pln DIP Package (N-8 Package) Qu,GAIN SELECT INPUT 1 1 G'A GAIN SELECT 2 7 G'B GAIN SELECT Goa"'". SELECT OUTPUll 4 5 OUTPUT2 y- TOP VIEW COO14001 TOP VIEW CD014301 c001~101 Note: Pin 5 connected to case. Figure 2: Pin Configurations 4-106 Note: All typical values have been guaranteed by characterization and are not tested. NE/SE592 ABSOLUTE MAXIMUM RATINGS Supply Voltage ................................................. ±8V Differential Input Voltage .................................... ±5V Common-Mode Input Voltage .............................. ±6V Output Current ............................................... 10mA Operating Temperature Range SE592 ................................ -55·C to +125·C NE592 ..................................... O·C to + 70·C Storage Temperature Range ............ -65·C to + 150 c C Power Dissipation ......................................... 500mW Lead Temperature (Soldering, 10sec) ................. 300·C Stresses above those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions. lor extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS + 25°C, VSUPPLY = ±6V, VCM = 0 unless otherwise specified. Vs = ±6.0V TA = NE592 SYMBOL. PARAMETER Differential Voltage Gain Gain 1 (Note 1) Gain 2 (Note 2) AVOL BW SE592 TEST CONDITIONS RL = 2kU, VOUT = 3Vp-p UNIT MIN TYP MAX MIN TYP MAX 250 80 400 100 600 120 300 90 400 100 500 '110 Bandwidth Gain 1 (Note 1) Gain 2 (Note 2) 40 90 40 90 MHz Rise Time t, Gain 1 (Note 1) Gain 2 (Note 2) (Note 4) Propagation Delay Gain 1 (Note 1) Gain' 2 (Note 2) (Note 4) td VOUT= 1Vp-p VOUT= lVp-p Input Resistance Gain 1 (Note 1) Gain 2 (Note 2) RIN CIN input Capacitance (Note 2) (Note 4) los Input Offset Currant IBIAS Input Bias Currant en Input Noise Voltage II.VIN Input Voltage Range I CMRR 10 Gain 2 10.5 4.5 12 10.5 4.5 10 7.5 6.0 10 7.5 6.0 10 4.0 30 20 2.0 BW= 1kHz' to 10MHz 3.0 9.0 30 9.0 20 12 ±1.0 60 86 60 Supply Voltage Rejection Ratio Gain 2 (Note 2) AVs = ±O.SV 50 70 50 70 Voo Output Offset Voltage Gain 2 (Note 2) RL = 00 VOCM Output Common-Mode Voltage RL = 00 VO(DIFF) Differential Output Voltage Swing RL =2kU Ro 1+ Output Resistance 1. 2. 3. 4. 0.35 0.75 2.4 2.9 3.4 3.0 4.0 20 = 00 Gain select pins G1A and G1B connected together. Gain select pins G2A and G2B connected together. Recommended supply voltage = ± 6V For design reference only, not 100% tested. 4-107 Note: All typical values have baen guaranteed by characterization and are not tested. 18 -dB 0.35 0.75 2.4 2.9 3.4 3.0 4.0 18 V dB V V V 20 24 iJA iJA jJ.V rms 12 ±1.0 RL pF 2.0 0.4 86 60 Power Supply Current (Note 3) kU 5.0 60 PSRR ns 0.4 VCM ±1V, f < 100kHz VCM ~ 1V, f = 5MHz I ns 4.0 30 Common-Mode Rejection Ratio Gain 2 (Note 2) Gain 2 (Note 2) NOTES: VIV U 24 rnA .n~nll :: NE/SE592 i. TYPICAL APPLICATIONS III z Filter Networks SCHEMATIC FILTER Vo (S) TRANSFER VI FUNCTION TYPE LOW PASS 1.4x104 [__ 1_] L $ + R/L HIGH PASS 1.4X104 [ S ] $+ 1/RC R BAND PASS 1.4x104 [ S ] - - L - S2+R/L s+1/LC AF027501 V ~(S) Vi :!! 1.4x104 Z(s) + 2re 1.4x104 :!!--- Z(s) + 32 BAND REJECT NOTE;: In the networks above, the R value used is assumed to include the internal 2re of approximately 32n. Figure 3: Basic Configuration +5V Q i ___ !! ___ -.J AMPUTUDE: FREQuENCY: I READ HEAD - I DIFFERENTIATOR/AMPUFIER "=' ZERO CROSSING DETECTOR AF027611 Figure 4: Disc/Tape Modulated Readback Systems 4-108 Note: All typical values have been guaranteed by characterization and are not tested. NE/SE592 For frequency f1 < < 1/21r(32)C dVj Vo a.1.4x104C d1 AF027101 Figure 5: Differentiation with High Common Noise Rejection 4-109 Note: All typical values have been guaranteed by characterization and are not tested. Section 5 Special Analog Functions AD590 2-Wire Current Output Temperature Transducer GENERAL DESCRIPTION FEATURES The AD590. is an integrated-circuit temperature transducer which produces an output current proportional to absolute temperature. The device acts as a high impedance constant current regulator, passing lilA/oK for supply voltages between + 4V and + 30.V. Laser trimming of the chip's thin film resistors is used to calibrate the device to 298.21lA output at 298.2°K (+ 25°C). The AD590. should be used in any temperature-sensing application between -55°C and + l50.°C (O.°C and 70'°C for TO-92) in which conventional electrical temperature sensors are currently employed. The inherent low cost of a monolithic integrated circuit combined with the elimination of support circuitry makes the AD590. an attractive alternative for many temperature measurement situations. linearization circuitry, precision voltage amplifiers, resistancemeasuring circuitry and cOld-junction compensation are not needed in applying the AD590.. In the simplest application, a resistor, a power source and any voltmeter can be used to . measure temperature. In addition to temperature measurement, applications include temperature compensation or correction of discrete components, and biasing proportional to absolute temperature. The AD590. is available in chip form making it suitable for hybrid circuits and fast temperature measurements in protected environments. The AD590. is particularly useful in remote sensing applications. The device is insensitive to voltage drops over long lines due to its high-impedance current output. Any well-insulated twisted pair is sufficient for operation hundreds of feet from the receiving circuitry. The output characteristics also make the AD590. easy to multiplex: the current can be switched by a CMOS multiplexer or the supply voltage can be switched by a logic gate output. • • • • Linear Current Output: 1pArK Wide Range: -55°C to + 150°C Two-Terminal Device: Voltage In/Current Out Laser Trimmed to to.5°C Calibration Accuracy (AD590M) Excellent Linearity: to.5°C Over Full Range (AD590M) Wide Power Supply Range: + 4V .to + 30V Sensor Isolation From Case Low Cost • • • • ORDERING INFORMATION PART NUMBER/PACKAGE NON-LINEARITY (OC) TO-52 PACKAGE TO-92 PACKAGE ±3.0 ±1.5 ±O.8 ±O.4 ±O.3 AD5901H AD590JH AD590KH AD590LH AD590MH AD590lZR AD590JZR TEMPERATURE RANGE -55°C to + 150°C O,°C to + 70°C DICE" AD590/D DICE ··Parameter MiniMax Limits guaranteed at 25°C only lor DICE ·orders. CASE (outline dwg TO·52) + SUBSTRATE (LEAVE FLOATING) (outline dwg TO·92) PC00421 I 05016601 Figure 1: Functional Diagram Figure 2: Pin Configurations 5--1 Note: All typical values have been guaranteed by characterization and are not tested. 30.0.10.6-00.2 ! ADS,90 .~ ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted) Forward Voltage (v+ to V-) "."""." ....... ,, ....... +44V Reverse Voltage (v+ to V-),,""""""""""""" -20V Breakdown Voltage (Case to V+ or V-) """"".±200V Storage Temperature Range """",," -65°C to + 150°C Rated Performance Temperature Range TO-92 """",,",,",,",,",,"",,",,. O°C to + 70°C TO-52 "" ........ """"" ........ " .,.55°C to+ 15QoC Lead Temperature (Soldering, 10sec) ",,",,""" + 300°C Stresses above thoss listed under" Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the 298.2 a: a: u ...::> ...... ::> 0 218 1/ / L / 21SOK 298.2"K 42aoK ( - 55·C) ( + 2S'C) ( +15O"C) TEMPERATURE OP016201 Figure 8: Simple connection. Output is proportional to absolute temperature. 5-6 Note: All typical values have been guaranteed by characterization and are, not tested. AD590 TYPICAL APPLICATIONS y+ +15V (ADDITIONAL SENSORSt 05017101 Figure 10: Average-temperature sensing scheme. The sum of the AD590 currents appears across R, which is chosen by the formula: 10kn DS01700i Figure 9: Lowest-temperature sensing scheme. Available current is that of the "coldest" sensor. R= n n being the number of sensors. +15V -, I J ~~~~~T J .J A C 0.1% [I ':" 80005701 Figure 11: Single-setpoint temperature controlier. The AD590 produces a temperature-dependent voltage across R (C is for filtering noise). Setting R2 produces a scale-zero voltage. For the Celsius scale, make R 1kn and VZERO 0.273 volts. For Fahrenheit, R 1.8kn and VZERO 0.460 volts. = = = 5-7 Note: All typical values have been guaranteed by characterization and are not tested. = ~. 10 AD590 ICII C ROW COLUMN SELECT +15V SEl.ECT ,....-, ENABLE R (OPTtONALI • 0 5 , 6 2 IH6108 8-CHANNEi. -f-:~~~~~~~~~~~t-~~~~~7 3 MUX '2 • " 5 '0 6 A058O(&I1 ,0Idl 0.1% . ! "OUT I 80005901 Figure 12: Multiplexing sensors. If shorted sensors are possible, a series resistor in series with the D line will limit the current (shown as R, above: only one is needed). A six-bit digital word will select one of 64 sensors. .-----.----------------o+.w 11<0 ZERCSET IOmV/"C 118kO 101<0 0.'% 1000 201<0 FUlL·SCALE ADJUST ~ .01<0 2.13.5V .,.. _I LCOO76Oi Figure 13: Centigrade thermometer (O°C-100°C). the ultra-low bias current of the ICL7611 allows the use of large-value gain-resistors, keeping meter-current error under 1/2%, and therefore saving the expense of an extra meter-driving amplifier. Note: All typical values have been guaranteed by characterization and are not tested. AD590 Y+ SOkIl~+_Vlr-+--""'" (8Yminl Y- LC007701 Figure 14: Differential thermometer. The 50kn pot trims offsets in the devices whether internal or external, so it can be used to set the size· of the difference interval. This also makes it useful for liquid-level detection (where there will be a measurable temperature difference). Y+ r: ----------, 1"A/OK I L: +-__-r_ _- ._ _ _ I I SEEBECK +-<>-I..:::C::::O~EF:.::F~IC~IENT I =4O,.v/oK YI= 10.98mY TYPEK I + Y+ + YoUT I RI 4521!1 Y2=10.98 40.211 j '::" '::" 05017201 Figure 15: Cold-junction compensation for type K th~mocouple. The reference junction(s) should be in close thermal contact with the AD590 case. V must be at least 4V, while ICL8069 current should be set at 1mA - 2mA. Calibration does not require shorting or removal of the thermocouple: set R1 for V2 = 10.98mV.lf very precise measurements are needed, adjust R2 to the exact Seebeck coefficient for the thermocouple used (measured or from table) note V1, and set R1 to buck out this voltage (i.e., set V2 V1). For other thermocouple types, adjust values to the appropriate Seebeck coefficient. = sao,A - :rt:J==xx:)C)( x + ~-r~~~tLCOO7801 Figure 16: Simplest thermometer. Meter displays current output directly in degrees Kelvin. Using the AD590M, sensor output is within ±1.7 degrees over the entire range, and less than ±1 degree over the greater part of it. 5-9 Note: All typical values have been guaranteed by characterization and are not tested. i AD590,' a cc I of I °C v+ A, A. L,...--I--, AEFHI 5 E+-- AEF LO L 9,00 4,02 2.0 12.4 10.0 0 5.00 4.02 2.0 5.11 5.0 11.8 Rn = 28kn nominal n=l All values in kn A A. ICL1106 II< ~_INHI W /,:::1=1 .B ~ f--' The ICL71 06 has a VIN span of ±2.0V. and a VCM rE\nge of (V" -0,5) Volts to (V- + 1) Volts; R is scaled to bring ,each range within VCM while not exceeding VIN- VREF for both scales is 500mV."Maximum reading on the Celsius range is 199.9°C. limited by the (short-term) maximum allowable sensor temperature. Maximum reading on the Fahrenheit range is 199.9°F (93.3°C). limited by the number of display digits. See note next page. -COMMON +-----fINLO yAF027801 Figure 17: Basic digital thermometer, Celsius and Fahrenheit scales y+ 1.5kO REF HI 2.2Il1O AEFLO i5kIl SCALE ADJ 1i5k1l ,_ ICL1106 307 COM IN HI , INLO + A05IO yLCOO7901 Figure 18: Basic digital thermometer, Kelvin scale. The Kelvin scale version reads from 0 to'1999°K theoretically, and from 223°K to 473°K actually. The 2.26kn resistor brings the input within the ICL7106 VCM range: 2 general-purpose silicon diodes or an LED may be substituted. 5-10 Note: All typical values have been guaranteed by characterization and are not tested. AD590 y. 7.5kll ICUOlll 1.235V SCALE REF }DJ HI· REFLD 1kQ,O.1% IClnD8 '5kll 21.'' ' '---JWHH--lCOM IN HI t--------IINLO y- lCOO8OO1 Figure 19: Basic digital thermometer, Kelvin scale with zero adjust. This circuit allows "zero adjustment" as well as slope adjustment. The ICL8069 brings the input within the common-mode range, while the 5kn pots trim any offset at 218°K (-55°C), and set the scale factor. Note on Figure 17, Figure 18 and Figure 19: Since all 3 scales have narrow VIN spans, some optimization of ICL7106 components can be made to lower noise and preserve CMR. The table below shows the suggested values. Similar scaling can be used with the ICL7126/36. SCALE VIN RANGE (V) RIN"rtkn) CAZ(IlFj K C F 0.223 to 0.473 -0.25 to + 1.0 -0.29 to + 0.996 220 220 220 0.47 0.1 0.1 For all: Cose = 100pF Rose = 100kn CREF = O.1p.F CINT = O.221lF 5-11 Note: All typical values have been guaranteed by characterization and are not tested. !~~~!~~age Converter .D~UIl GENERAL DESCRIPTION FEATURES The Intersil ICL7660 is a monolithic CMOS power supply' circuit which offers unique performance advantages over' previously available devices. The ICL7660 performs supply voltage conversion from positive to negative for an input range of + 1.5V to + 10.0V, resulting in complementary output voltages of -1.5V to -10.0V. Only 2 non-critical external capacitors are needed for the charge pump and charge reservoir functions. The ICL7660 can also be connected to function as a voltage doubler and will generate output voltages up to + 1S.6V with a + 10V input. Note that an additional diode is required for VSUPPLY > 6.5V. Contained on chip are a series DC power supply regulator, RC oscillator, voltage level translator, and four output power MOS switches. A unique logic element senses the , most negative voltage in the device and ensures that the output N-channel switch source-substrate junctions are not forward biased. This assures latchup free operation. The oscillator, when unlOaded, o$cillates at a nominal frequency of 10kHz for an input supply voltage of 5.0 volts. This frequency can be lowered by the addition of an external capacitor to the "OSC"terminal, or the oscillator may be overdriven by an external clock. The "LV" terminal may be tied to GROUND to bypass the internal series regulator and improve low voltage (LV) operation. At medium to high voltages (+ 3.5 to + 10.0 volts), the LV pin is left floating to prevent device latchup. • Simple Conversion of +5V Logic Supply to ±5V Supplies ,. Simple Voltage Multiplication (VOUT nVIN) • 99.9% Typical Open Circuit Voltage Conversion Efficiency, • 98% Typical Power Efficiency • Wide Operating Voltage Range 1.5V to 10.0V • Easy to Use - Requires Only 2 External Non-Critical Passive Components =(-) APPLICATIONS • • On Board Negative Supply for Dynamic RAMs Localized /-I-Processor" (8080 Type) Negative Supplies Inexpensive Negative Supplies Data Acquisition Systems • • ORDERING INFORMATION PART NUMBER TEMP. RANGE ICQ660CTV O· to +10·C JCL7660CBA O·C to +70·C ICL7660CPA O· ,to +70·C ICL7660MTV' ICL7660/D PACKAGE TO-99 8 PIN SOIC ',8, PIN MINI DIP _55· to + 125°C TO-99 ' - DICE" • Add' /8,838.to part number if 8838 processing is required. "Parameter min/max limits guaranteed at 25·C only for DICE orders. V+(endCASEI V+ 8 OSC LV VOUT CAPCD035201 C0034111 (Outline Dwg BA) 8 LEAD MiniDIP (Outline Dwg TV) 8 LEAD TO-99 COO35901 (Outline Dwg PAl Figure 1: Pin Configurations 5-12 Note: All typical values have been guaranteed by characterization and are not tested. 302063--003 ICL7660 ABSOLUTE MAXIMUM RATINGS Supply Voltage ............................................... 10.5V LV and OSC Input Voltage (Note 1) ............... -0.3V to (V± +0.3V) for V+ < 5.5V (V+ -5.5V) to (V+ +0.3V) for V+ > 5.5V Current into LV (Note 1) ............... 20j.lA for V+ >3.5V Output Short Duration (VSUPPLY S 5.5V) ...... Continuous Power Dissipation (Note 2) ICL7660CTV ....................................... 500mW ICL7660CPA ....................................... 300mW ICL7660MTV ....................................... 500mW Operating Temperature Range ICL7660M ........................... -55°C to + 125°C ICL7660C ................................. O°C to +70°C Storage Temperature Range ............ -65°C to + 150°C Lead Temperature (Soldering, 1Osee) ...........................................300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings -only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. r-------------~--------------~------~--------------------OV+ ~-----------------oCAP+ r-------------O CAP- Your OSC LV = BD01560r Figure 2: Functional Diagram OPERATING CHARACTERISTICS V + = 5V, TA = 25°C, Case = 0, Test Circuit Figure 3 (unless otherwise specified) LIMITS SYMBOL PARAMETER TEST CONDITIONS UNIT MIN TYP MAX 170 1+ Supply Current RL = 00 500 !lA VH1 Supply Voltage Range - Hi ooe S TA S 70°C, RL = 10kn, LV Open 3.0 6.5 V (Dx out of circuit) (Note 3) -55°C S TA S 125°C, RL = 10kn, LV Open MIN S TA S MAX, .RL = 10kn, LV to GROUND 3.0 1.5 5.0 V 3.5 V vli Supply Voltage Range - Lo (Dx out of circuit) VH2 Supply Voltage Range - Hi (DX in circuit) MIN S TA S MAX, RL = 10kn, LV Open 3.0 10.0 V Vl2 Supply Voltage Range - Lo (DX in circuit) MIN S TA S MAX, RL = 10kn, LV to GROUND 1.5 3.5 V 5-13 Note: All typical values have been guaranteed by characterization and are not tested. i a ICL7660 OPERATING CHARACTERISTICS (CONT.) LIMITS SYMBOL PARAMETER TEST CONDITIONS UNIT MIN TYP MAX 55 lOUT = 20mA, TA = 25°C lOUT = 20mA, O°C::; TA::; + 70°C Output Source Resistance ROUT 100 n 120 n lOUT = 20mA, -55°C::; TA::; + 125°C (Note 3) 150 n V+ =2V, IOUT=3mA, LV to GROUND O°C::;TA::; +70°C 300 n V+ = 2V, lOUT = 3mA, LV to GROUND, -55°C::; T A::; + 125°C, Ox in circuit (Note 3) 400 n . Oscillator Frequency 10 kHz PEl Power Efficiency RL = 5kn 95 98 % VOUT Ef Voltage Conversion Efficiency RL = 97 99.9 % Zose Oscillator Impedance V+ =2 Volts 1.0 Mn V= 5 Volts 100 kn fose 00 Notes: 1. Connecting any input terminal to voltages greater than V + or less than GROUND may cause destructive latchup. It is recommended that no inputs from sources operating from external supplies be applied prior to "power up" of . the ICL7660. 2. Derate linearly above 50°C by 5.5mWrC. 3. ICL7660M only. TYPICAL PERFORMANCE CHARACTERISTICS OPERATING VOLTAGE AS A FUNCTION OF TEMPERATURE (Circuit of Figure 3) OUTPUT SOURCE RESISTANCE AS A FUNCTION OF SUPPLY VOLTAGE '!A-~"'~= ~ 7.oF=;:=;::::=P i OUTPUT SOURCE RESISTANCE AS A FUNCTION OF TEMPERATURE g350 lOUT rJ ... ~ . .. 250 ./ m200 . i,oo ~ i-'"'" I'--. ,. 012345678 TEMPERATUAE(GC) ~ • o • POWER CONVERSION EFFICIENCY AS A FUNCTION OF OSC. FREQUENCY ..I..- Y+""5Y -50" -250 DO +25° +50" +75°+100"+125° TEMPERATURE (·C) SUPPLY VOLTAGE (v+) OPOO1011 - ~~=+zv rJ !i '50 4.ot-- ".. -50 '0 ..• . . " ; SLOPE SSO 7 .. e 20 30 40 50 &0 10 80 LOAD CURRENT !t(m") V ~ 1ft IV f-- V I 20 30 . c:t--J. I I ...... l100 ~ ~ w z 70 so 20.0 1B.O TA=+25D C V1"= '2.ov IV ! ... g:g 12.0 v+:-· 2V .. . __ 20;;: 10 ~ I 40 ~ so \ \ \ \ • 1 -2 ./ J ".. i--" V i--"jPY· 012345878 LOAD CURRENT IL (mA) OPOO0201 NOTE 4. These curves include in the supply current that current fed directly into the load RL from V + (see Figure 3). Thus, approximately half the supply current goes directly to the positive side of the load, and the other half, through the ICL7660, to the negative side of the load. Ideally, VOUT == 2 VIN, Is == 2 IL, so VIN • Is == VOUT • IL· 1 ~ ~, 4.0 2 so ~ 1ft 10.0 ~ .. .. l':/ ffi .. ~ o / u 20 o +- 3O~ OPOO0601 SUPPLY CURRENT & POWER CONVERSION EFFICIENCY AS A FUNCTION OF LOAD CURRENT ffi .. 50 ~ 40 -:;' lOAD CURRENT IL ImA) OPQ00101 TA!~OC 1 TA-=+25°CV+ +5V / 10 2 70 / 50 20 1 80 !( )t-,. ~ 30 ,.,... 3 -4 r I...... ffi .. / ::I-2 .... .. ..iii .. g 1 t-.... !i .. iii .. OUTPUT VOLTAGE AS,A FUNCTION OF OUTPUT CURRENT V 8.0 i 6.0 ~ 4.0 i •z .... 2.0 !: 3JI 4.5 6.0 7.5 LOAD CURRENT IL (mA) 1.5 9.0 OPQO0901 which shows an idealized negative voltage converter. Capacitor C1 is charged to a voltage, V + , for the half cycle when switches 81 and 83 are closed. (Note: 8witches 82 and 84 are open during this half cycle.) During the second half cycle of operation, switches 82 and 84 are closed, with 81 and 83 open, thereby shifting capacitor C1 negatively by V'I- volts. Charge is then transferred from C1 to C2 such that the voltage on C2 is exactly V +, assuming ideal switches and no load on C2. The ICL7660 approaches this ideal situation more closely than existing non-mechanical circuits. Is v+ r--------,-~(+5V) 7 ------l I ,I " I I I I RL ·coscl Ox I~~*,, , :r , .. ~VOUT L __ ..J In the ICL7660, the 4 switches of Figure 4 are M08 power switches; 81 is a P-channel device and 82, 83 & 84 are N-channel devices. The main difficulty with this ap~ proach is that in integrating the switches, the substrates of 83 & 84 must always remain reverse biased with respect to their sources, but not so much as to degrade their "ON" resistances. In addition, at circuit startup, and under output short circuit conditions (VOUT = V +), the output voltage must be sensed and the substrate bias adjusted accordingly. Failure to accomplish this would result in high power losses and probable device latchup. TCOOO301 NOTES: 1. For large values of Case ( > 1000pF) the values of Cl and C2 should be increased 'to 100"F, 2. Ox is required for supply voltages greater than 6.5V @ - 55'e S TA S + 70'C; refer to performance curves for additional information. Figure 3: ICL7660 Test Circuit This problem is eliminated in the ICL7660 by a logiC network which senses the output voltage (VOUT) together with the level translators, and switches the substrates of 83 & 84 to the correct level to maintain necessary reverse bias. DETAILED DESCRIPTION The ICL7660 contains all the necessary circuitry to complete a negative voltage converter, with the exception of 2 external capacitors which may be inexpensive 10IlF polarized electrolytic types. The mode of operation of the device may be best understood by considering Figure 4, The voltage regulator portion of the ICL7660 is an integral part of the anti-Iatchup circuitry, however its inherent voltage drop can degrade operation at low voltages. 5-15 Note: All typical values have been guaranteed by characterization and are not tested. II i a ICL7660 Therefore, to improve low voltage operation the "LV" pin should be connected to GROUND, disabling the regulator. For supply voltages greater than 3.5 volts the LV terminal must be left open to insure latchup proof operation, and prevent device' damage. ENERGY IS LOST ONLY IN THE TRANSFER OF CHARGE BETWEEN CAPACITORS IF A CHANGE IN VOLTAGE OCCURS. The energy lost is defined by: where V1 and V2 are the voltages on C1 during the pump and. transfer cycles. If the impedances of C1 and C2 are relatively high at the pump frequency (refer to Figure 4) compared to the value of RL, there will be a substantial difference in the voltages V1 and V2. Therefore it is not only desirable to make C2 as large as possible to eliminate output voltage ripple, but also to employ a correspondingly large value for C1 in order to achieve maximum efficiency of operation. ' DO'S AND DON'TS 1. 2. TCOO0801 Figure 4: Idealized Negative Voltage Converter 3. THEORETICAL POWER EFFICIENCY CONSIDERATIONS In theory a voltage converter can approach 100% efficiency if certain conditions are met: 'A The drive circuitry consumes minimal power. S The output switches have extremely low ON resistance and virtually no offset. C The impedances of the pump and reservoir capacitors are negligible at the pump frequency. The ICL7660 approaches these conditions for negative voltage conversion if large values of C1 and C2 are used. 4. 5. 6. Do not exceed maximum supply voltages. Do not connect LV terminal to GROUND for supply voltages greater than 3.5 volts. Do not short circuit the output to V + supply for , supply voltages above 5.5 volts for extended periods, however, transient conditions including startup are, okay. When using polarized capacitors, the + terminal of C1 must be connected to pin 2 of the ICL7660 and the + terminal of C2 must be connected to GROUND. Add diode Ox as shown in Figure 3 for high-voltage, elevated temperature ,applications. Add capacitor (~0.1IlF, disc) from pin 8 to ground to limit rate of rise of input voltage to approximately 2V//lS. -v+ ·NOTE: 1. Your = FOR 1.SV :5 V,V:5 6.SV 2. Your = -(v+ -VFOX) FOR 6.5 :5 v+ :5 10.0V Dx ,...-f4--, I ICL7660 I 9----T..------<0 Your· + L _____ J ~ 10j. 10V Current into LV (Note 1) •............... 20IlA for V+ > 10V Output Short Duration ...............•.......•...... Continuous Power Dissipation (Note 2) ICL7662CTY .........•...................•......... 500mW ICL7662CPA .........•.........................•... 300mW ICL7662MTY ........••...............•...•......... 500mW Lead Temperature