1986_MMI_PAL_PLE_Handbook_5ed 1986 MMI PAL PLE Handbook 5ed

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PAL®/PLETM Device
Programmable
Logic Array
Handbook
FIFTH EDITION

Monollthlom
• •morl••
PAL®, HAL®,PALASM®, and SKINNYDIP® are registered trademarks of Monolithic Memories Inc.

PLer'" I MegaPAL"", ZHAL YII , ProPALTM I and SMACTM are trademarks of Monolithic Memories Inc.
Logic Cell ArrayTM is a trademark of XILINX.
@Copyright1978, 1981, 1983, 1985, 1986 Monolithic Memories Inc .
• 2175 Mission College Boulevard. Santa Clara, CA 95054-1592. (408) 970-9700. (910) 339-9220

T~ble

of Contents

PAL® DeVice Introduction ........................... 1·2
PAL®/HAL® Device Specifications .................... 2·1
Table of Contents for Section 2

............................................. , ........... , .. 2-2

PAL/HAL pevices

......... , ............................................2-3

Small 20 Series: 10H8, 12H6, .14H4, 16H2, 16Cl,10L8, ~2L6, 14L4, 16L2 , ....... 2-5
20 (standard) ................................. , .................................................2-8
20-2 (half power) .........................•............................................ : ....... 2-9
Medium 20 Series: 16L8, 16R8, 16R6, 16R4 ............................................ 2-19
20 (standard) •......................... : ...................................................... 2-21
20A (high speed) ............................................................................ 2-22
...................................................... 2-24
20A-2 (high speed and half power)
20A-4 (high speed and quarter power)' .................................................. 2-25
208 (very high speed) .................... : ................................................. 2-26
208-2 (very high speed and half power) ................................................ 2-27
208-4 (very high speed and quarter power) ... ," .......... : ......... c....... ::; ....... 2-28
200 (ultra high speed)· .......................... " .......................................... 2-29
Medium 2QPA Series: 16P8A, 16RP8A, 16RP6A,16RP4A
Lar.ge 20 Series: 16X4, 16A4
Large 20RA: 16RA8

........................... 2-37

................................................................ 2-45

........................................................................... 2-51

Small 24 Series: 12L 10, 14L8, 16L6, 18L4, 20L2, 20Cl
Small 24A Decoder Series: 6L 16A, 8L 14A

.............................. 2-55

.............................................. 2-65

Medium 24 Series:20L8, 20R8, 20R6, 20R4 ............................................ 2-70
24A (high speed) ............................................................................ 2-73
24A-2 (high speed and half power) ...................................................... 2-75
248 (very high speed) ...................................................................... 2-76
Medium 24X Series: 20L 10, 20X10, 20X8, 20X4 ....................................... 2-81
24X (standard) ............................................................................... 2-83
24XA (high speed) .......................................................................... 2-85
Large 24RS Series: 20S10, 20RS10, 20RS8, 20RS4
Large 24RA: 20RA 10
PAL32VX10/A

................................................................................. 2-103

PMS14R21/A

.................................................................................. 2-113

PAL lOH20P8

........................ : .......................................................... 2-115

MegaPAL.devices: 32R16, 64R32
fMAXParameters
Waveforms
Test Load

ii

................................... 2-90

................................ , ......... , ............................... 2-98

........................................................ 2-119

............................................................................. 2-126

.............. , ...................................................................... 2-127
................... : .................................................................. 2-128

Monolithic

m

Memories

Table of Contents

MMI PAL® Device Programmer Reference Guide ...... 3·1
Data 1/0 Corporation
20 Pin Device Families .......................................................................3-3
24 Pin and MegaPAL Device Families .....................................................3-4
Digelec
20 Pin Device Families .......................................................................3-5
24 Pin and MegaPAL Device Families .....................................................3-6
Kontron
20 Pin Device Families .......................................................................3-7
24 Pin and MegaPAL Device Families .....................................................3-8
Micropross
20 Pin Device Families ... , .......................•...........................................3-9
24 Pin and MegaPAL Device Families .................................................... 3-10
Promac
20 Pin Device Families ..................................................................... 3-11
24 Pin and MegaPAL Device Families ................................................... 3-12
Stag Microsystems
20 Pin Device Families ..................................................................... 3-13
24 Pin and MegaPAL Device Families ................................................... 3-14
Storey Systems
20 Pin Device Families ..................................................................... 3-15
24 Pin and MegaPAL Device Families ....................................•.............. 3-16
Structured Design
20 Pin Device Families ............................................................•........ 3-17
24 Pin and MegaPAL Device Families ................................................... 3-18
Valley Data Sciences
20 Pin Device Families ..................................................................... 3-19
24 Pin and MegaPAL Device Families ....................•.............................. 3-20
Varix
20 Pin Device Families ..................................................................... 3-21
24 Pin and MegaPAL Device Families ................................................... 3-22

HAL®/ZHALN Devices . .................... '.' ........ 4-1
ProPAL,TM HAL and ZHAL Devices: The logical Solutions for Programmable
Logic ............................................................................................... .4-3
ZHAL20A Series ZHAL64R32 -

Zero Power CMOS Hard Array Logic

Zero Power CMOS Hard Array Logic

ZHAL24A Series -

...........................4-7

................................ 4-15

Zero Power CMOS Hard Array Logie

........................ .4-24

Logic Cell ArrayN .................................. 5-1
PALASM® Software Syntax . ........................ 6-1

Monolithic

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iii

·Table f)f eontents
PALDevice,Appilcatlons; . .c•••' ••• : •••••••••• : ••• 7·1
PAL20L10; 10-Bit Open Collector Buffer ............................ ; ..•. , ....•........... 7-3
10-Bit Open Collector Inverting Buffer •.......•..••...... , ..................7-5
PA.L;!OX10; 10·Bit Addressable Register .......•.... , .....•......................•........7-7
PAL20L 10; MC6800 Microprocessor Interface ................................... , .... 7-10
PAL14L4; Quad 3:1 Multiplexer ............................................................ 7:13
PAL20X8; 4-Bit Counter With Register .....•... , ..................•.....•.........••.•.. 7-14
PAL20X10; 9-Bit Down Counter .............. : .....................•..• :: ................. 7-16
PAL20X10; Refresh Cloc.k Generator ................................................... 7-18
PAL16R8; Octal.Addressable Register ..................................... : .•......•... 7-21
PAlJ6R8; Octal.Addressable Register WitMlernux/Enables .... ,.................. ; 7-24
PAL16R8; Octal Addressable Register With DemuxlClear .......................... 7.-28
PAL16C1; Rounding-Control Logic ....................................................... 7-31
PAL16R6; 4-Bit Counter With Terminal Cou~t.Lock ...................... : ............ 7-32
PALf8L4;Memory-Mapped 1/0 ................. ~ ......................... : ............... 7-34
PAL16R4; 74S508 Memory Map Interface #1
.................................. :: .... 7"36
PAL16R4; 74S508 Memory Map Interface #2 .................,; ...................... 7-38
',PAL20R4; 16 Input Registered Priority Encoder #1 .................................. 7-39
PAL16C1; 16 Input Priority Encoder Interrupt Flag #2 .................:: ............. 7~41
PAL20R4; 15 Input Registered Priority Encoder ....................... , ............... 7-42
PAl16R4; 8 Input Registered Priority Encoder ........................................ 7-44
PAL16R8;Dual Stepper Motor Controller ............................................... 7-47
PAL20L10; Clean Octal Latch ................ ; .............................\.·: ..... : .... :7-49
PAL16R4; Shaft Encoder #1 ...................................... ; ........ ~·i ............ 7-51
PAL16R8; Shaft Encoder #2 ................................... : .......... ;:; ......... : .... 7-54
PAL20X10; Shaft Encoder #3 ............................................................. 7-57
PAL6L16; Four-to-Sixteen Decoder ...................................................... 7-60
• pAL8L14; PC 110 Mapper ................................................................. 7-61
pAL16C1; Octal Comparator ................................................................ 7-62
PAL16R8; Three-ta-Eight Demultiplexer ................................................ 7-63
PAL16Rp8; Basic Flip-Flops .............................................................. 7-64
pAL20X10; 9-Bit Register ·................................................................... 7-65
pAL20X10; 10-Bit Register ................................................................ 7-66
.' pAL64R32; 16-Bit Barrel Shifter .......................................................... 7~7
PAL32R16; 16-Bit Addressable Register ....................... ; ....i .. ; ............... 7-69
pAL16Rp8; Traffic Signal Controller ..................................................... 7-71
PAL 16Rp6; Memory Handshake Logic .................................................. 7-73
PAL 16RP4; 4-Bit Counter .................................................................. 7-76
pAL20X8; 8-Bit Counter .................................................................... 7-77
pAL20X10; 9-Bit Counter .................................................................. 7-78
pAL20RS10; 10-Bit Counter
.............................................................. 7-79
PAL20RA10, pAL16C1; 5-Bit Up Counter .............................................. 7."'0
pA120RA10;i-Bit i/o Port ............................ : •. : .. : ...................... ;•. : ..... 7-83
pAL.:20FtA~O; SeriarOata Unk ControHer ........ : ... ; ........... ::·: ............. ::·..... :.7-85
pAL20RA10, PAL20L10; Interrupt Controller ........................................... 7-88
PAL;!OL~O;

iv

IIIIonoIlthit:

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Memories

Tabl. of Cont...ts
Logic 1\dorlal ..................................... 8-1
Table of contents for Section 8

............................................................

8·2

1,.0 Boolean Algebra
,1.1 The Language of Logic •••......................•..•.••.... ;..........................
1.2 AND, OR and NOT ......•.•..•......•..•.......••..............•.•..............•.•.. :.
1.3 Precedence .......•..•.••.•....•........ ,...............................................
1.4 Associativity and Commutativity .................................................. "
1,5. Postulates 'and Theorems .......................................................... ..
1.5.1 Duality ............................................................................
1.5.2 Using Truth Tables ........................................................'.....
1.5.3 Complement of a Boolean Function ........................................
1.6,Algebra Simplification.................................................................
1.6.1 Sum·of·Products and ProduCt·of·Sums .....................................
1.6.2 Canonical Forms ................................................................
1.6.3 Conversion Between Canonical Forms .....................................
1.7 Exclusive:OR (XOR) and Equivalence (XNOR) ..................................
1.8 Boolean Operator Summary ................................................,..........

8·3
8·3
8:4
' 8'4
8·4
8·4
8:5
8·5
8·5
8·5
8·5
8-6
8·6
" 8·7

2.0 Binary Systems
2.1 Base Conversion ......................................................'.........'....... ·8-6
2.1.1 Base·2toBase·10Conversion ...............................,...... ;; ........ 8eS
2.1.2 Base·10 to Base-2 Conversion, ... ;; ....... ;; .... ; ............................ 8eS
2.1.3 Base·2 to BaseeS or Base·16 ... ,............................................ . 8eS
2;2 Simplicity of Binary Arithmetic ............................ , .......,.................. ;. 8·8
2.2.11.'sCompl!iment ................................ ; ................ , ..... c.. ; ......' 8-8
2.2.2 Subtraction with 1's. Complement ....................'.... : .... : ..... ;........ 8-8
2.2.3 2's Complement .........................,.................................,...... 8-9
. 2.2.4 Subtraction with 2's Complement .................: .......... : •. :........... 8·9

3.0 Karnaugh MapS

"

.

.

3.1lSarriaogh Map Technique ...... : ........ ,;: ...... : .... : ...............;. .....,... :~ .....
·3.U Karnaugh Map Rellding'Procedure .. , ...... ,................. :..............
3.1.2 KarnaughMap Matrix Uil)elS ... :: •.•.•:.....................: .......... : .... :.
3.1.3 Karnaugh Map Examples .....................................................

4.0 Combinatorial logic;

. . .. '."

"

11.10
8.10
8·10
8·10

'.

4.1 Logill Design Introduction .................................................. :,. ..... .:~ ~~
'4,2 Combinatorial Logic ... : ......... : ................................., •••.• :'......... \..
.
4.3NA~D Gates and NOR Giltes .......... :.;; ..................... ,: .. :.::-.:·.. ,:.u.. a~12

:~i~:=~~~~~~~;~i~;::::::::::::::::::::.::::::::~:::.:.::::::::::::::~:::;:::;::::::::.•. E~:

4.7 ~dder ................................ :: ... : ..............................:.: .......... c..
4.a Unlocked Flip·Flops - Hazards ..................................................

iJ~i7

a·11

" .' •
.
5.0 $equentlal' LogiC
5.1.lntroduction ......................... : .... :....................., .... , .........; .... : ..... '8·21
·~.2 Unclocked Flip-Flops...,. Latches
..........................•................... 'i;.·· 8·21
5.2.1 $-R Latch .... :.................................................................. Ij~2'1
5.2.2 D-Type Latch ........ ;; ..... ; ... : ..... : ...... ;: .... ::.: ...................... :. 8·22
.5.2.3 J.KLatch ; ............. ; ....... : ........... ;,.:: ......; .. ~ ......'\..;: ...... ~ ..' ....::.:,( .. ~8-22.
5.2.4 T·Type Latcl).. ... : ............. : .. ,,: .. , •.,~, ..., ............:: .••~ .•• :,' .... , .• : a-2~.
5.3 Clocked Flip-Rops":" Registers .: ....... ~: ..'............. ::: ...... :: ......... : ... : 8~l!3
5.3.1 Characteristic,Equations .;;'.::·i~:'
\t.;.~.\: .. ;;;: .. " .. ,;.i.:\:>.';).;·.' 8"2$'
5.4 Designing Synchrono~s Sequential Circuits ........ ................... ......... 8.23
5.4.t State Tran.itiOllTables ........... , ................... : ..... :................ 8·24
5.4.2 State Tilbles and State Diagrams .: ............. : ....................... ;. a·24
5.4.3 Design Examples ..............................................................' 8·25
5.5 Counters .................................... ; .................... : ...........~......... a·29·

.. ::..

III

Table of Contents
9-1

PLE'" Devices

Contents for Section 9 . . .. . . . . . .. . . . . . .. . . . . .. . . . . .. . . . . . . . . . . . .. . . . . .. . . . .. . . . . .. .. . . . . . . 9-2
PlE to PROM Cross Reference Guide ................ : .................'............... 9-3
Selection Guide
..........................................................................•. ' 9-4
PLE means Programmable Logic Element .................................,...... ..... 9-5
Registered PLE ............................................................................ , 9-5
PLEASMTM ......... ...... ........... .... ..... .. ........ ..... .. ....... ............ ...... ..... 9-6
Logic Symbols .............................................................................. 9-7
Specifications .. . .. .. .. .. .. .. .. . .. .. .. .. .. .. . .. .. .. .. .. .. .. .. . . .. .. . .. .. . .. . .. .... .. .. .. .. . 9-10
PLE Family ,Block Diagrams ...................................................... ;..... 9-16
PLE Programmer Reference Chart .................................... ; .............,.. 9-20

PLE Circuit Applications ... , .. . .. . . . . .. . . . . . . . . . .. 10-1
10-2

Table of Contents for Section 10

Random Logic Replacement

........................................................... ..

Basic Gates .............................................................................. .
Memory Address Decoder ............................................................. .
6-Bit True/Complement and Clear/Set Logic Functions ....................... ..
Expandable 3-to·8 Demultiplexer .................................................... .
Dual 2:1 Multiplexer ........................................... ; ........................ .
Quad 2:1 Multiplexer with Polarity Cor'ltrol ........................................ ..
Hexadecimal to Seven Segment Decoder ......................................... .
5'Bit Binary to BCD Converter ...................................................... ..
4-Bit BCD to Gray Code Converter ................................................. ..
4-Bit Gray Code to BCD Converter ................................................. .
8-Bit Priority Encoder.. . ................................................................ ..
4-Bit Magnitude Comparator ........................................................ ..
6-Bit Magnitude Comparator ........................................................ ..
4·Bit Magnitude Comparator with Polarity Control ................................ .
8-Bit Barrel Shifter ...................................•..................................
4-Bit Right Shifter with Programmable Output Polarity ......................... ..
8-Sit Two's Complement Conversion ............................. : ................ ..
A Portion of Timing Generator for PAL Array Programming ................ c .. ..
Timing Generator for PAL Security Fuse Programming ........................ ..

Fast Arithmetic Look-up

................................................................ .

4-Bit Multiplier Look-up Table ........................................................ .
ARC Tangent Look-up Table ......................................................... .
Hypotenuse of a Right Triangle Look-up Table ............................ : ...... .
Perimeter of a Circle Look-up Table ............................................... ..
Period of Oscillation for a Mathematical Pendulum Look-up Table
Arithmetic Logic Unit .................................................................. .

Wallace Tree Compression

10-44
10-45
10-46
10-48
H)-51
10-54
10-57

............................................................ . . 10-58

Seven 1-Bit Integer Row Partial Products Adder ................................. .
Five 2-Bit Integer Row Partial Products Adder .................................... .
Four 3-Bit Integer Row Partial Products Adder ...... : ............................ .
Three 4'Bit Integer Row Partial Products Adder ................................. ..

Resldl(e Arithmetic Using PLE Devices

........................................... ..

Distributed Arithmetic Using PLE Devices
Registered j:>LE Devices in Pipelined Arithmetic

vi

10-3
10-4
10-6
10-10
10-12
10-14
10-15
10-17
10-20
10-22
10-23
10-24
10-26
10-27
10-28
10-30
10-33
10-36
10-38
10-41

10-60
10-61
10-62
10-63
10-64
10-70

0_', ." •• )~ •••••••.•••••• .; 0,"" •••••••

Mono/ilhicURMemorles

10-72

Table of Contents
Article Reprints . ................................. 11·1
Table of Contents for Section 11
....................................................... 11-2
Testing Your PAL Devices ................................................................ 11-3
PAL20RA10 Design for Testability ...................................................... 11-8
PAL Design Function and Test Vectors .............................................. 11-10
Metastability .......................................... '" ...................... , " .......... 11-13
High-Speed Bipolar PROMs Find New Applications as
Programmable Logic Elements ........................ , .. " ....................... 11-17
ABEL™ a Complete Design Tool for Programmable Logic ..................... 11-25
CUPL™ the Universal Compiler for Programmable Logic
....................... 11-29

General Information .............................. 12·1
Package Drawings . .............................. 13·1
Representatives and Distributors . ................. 14-1

Monolithic

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vii

PAL@ Device Introduction

The PAL@ Device Concept
Monolithic Memories' family of PAL devices gives designers a
powerful tool with unique capabilities for use in new and
existing logic designs. The PAL device saves time and money
by solving many of the system partitioning and interface
problems brought about by increases in semiconductor device
technology.
Rapid advances in large scale integration technology have led
to larger andlarger standard logic functions; single I.C.s now
perform functions that formerly required complete circuit
cards. While LSI offers many advantages, advances have
been made at the expense of device flexibility. Most LSI
devices· still require large numbers of SSIIMSI devices for
interfacing with user systems. Designers are still fOrced to turn
to random logic for many applications.

The designer is confronted with another problem when a
product is designed. Often the funGtion is well defined and
could derive significant benefits from fabrication as an integrated circuit. However, the design cycle for a custom circuit is
long and the costs can be vel}' high. This makes the risk
significant enough to deter most users. The technology to
support maximum flexibility combined with fast turnaround on
custom logic has simply not been available. Monolithic Memories offers the programmable solution.
The PAL device family offers a fresh approach to using fuse
programmable logic. PAL circuits are a conceptually unified
group of devices which combine programmable flexibility with
high speed and. an extensive selection of interface options.
PAL devices can lower inventol}', cut design cycles and
provide high complexity with maximum flexibility. These features, combined with lower package count and high reliability,
truly make the PAL device a ci(cuit designer's best friend.

Monolithic LJJJ]N/emories

PAL® Device Introduction
The PAL Device New Tricks

Teaching Old PROMs

Figure 1 shows the basic PAL device structure for a two-input,
one-output logic segment. The general logic equation for this
segment is:
Output = (1 1

+ 1";")(T;" + 12)(1 2 + 1;)(1; + 1,;) +

(T;" + ~)(12 + ~) (i"2 +

(11

+ ~)

fa)

where the "f" terms represent the state of the fusible links in
the PAL device AND array. An unblown link represents a logic
1. Thus:
fuse blown, f = 0
fuse intact, f = 1
An unprogrammed PAL device has all fuses intact.

r

\

OUTPUT

Monolithic·Memories developed the modern PROM and introduced many of the architectures and techniques now regarded as industry standards. As the world's largest PROM
manufacturer, Monolithic Memories has the proven technology
and high volume production capability required to manufacture
and support the PAL device.
The PAL device is an extension of the fusible link technology
pioneered by Monolithic Memories for use in bipolar PROMs.
The fusible link PROM first gave the digital systems designer
the power to "write on silicon". In a few seconds he was able
to transform a blank PROM from a general purpose device
into one containing a custom algorithm, microprogram, or
Boolean trans.fer function. This opened up new horizons for
the use of PROMs in computer control stores, character
generators, data storage tables and many other applications.
The wide acceptance of this technology is clearly demonstrat,
ed by today's multi-million doilar PROM market.
The key to the PROM's success is that it allows the designer
to customize the chip quickly and easily to fit his unique
requirements. The PAL device extends this programmable
flexibility by utilizing proven fusible link technology to implement logic functions. By using PAL circuits the designer can
quickly and effectively' implement custom logic varying in
complexity from random gates to complex arithmetic func.
tions.

Figure 1

PAL Device Notation
Logic equations, while convenient for small functions, rapidly
become cumbersome in large systems. To reduce possible
confusion, complex logic networks are generally defined by
logiC diagrams and truth tables. Figure 2 shows the logiC
convention adopted to keep PAL device logic easy to understand and use; in the figure, an "x" represents an intact fuse
used to perform the logic AND function. (Note: the input terms
on the common line with the x's are not connected together.)
The logiC symbology shown in Figure 2 has been informally
adopted by integrated circuit manufacturers because it clearly
establishes a one-to-one correspondence between the chip
layout and the logiC diagram. It also allows the logic diagram
and truth table to be combined. into a compact and easy to
read form, thereby serving as a convenient shorthand for PAL
circuits. The two-input, one-output example from Figure 1,
redrawn using the new logic convention,. is shown in Figure 3.

:~A'B'C

c~

ANDs and ORs
The PAL device implements the familiar sum-of-products logic
by using a programmable AND array whose output terms feed
a fixed OR array. Since the sum-of-products form can express
any Boolean transfer function, the PAL circuit uses are only
limited by the number of terms available in the AND - OR
arrays. PAL devices come in different sizes to allow for
effective logic optimization.

Monolithic

W Me",ories

Figure 2

1·3

PAL@ Device, IntrC)duction
memory address; the output is the content of that' memory
location,

OUTPUT

jv7

n~

i'I

IV

7

~

IV

"OR" ARRAY
(PROGRAMMABLE)

7
r'\

F<
F<
F<

Figure 3

=<
=<

"

=<
=<
=<
=<
=<
=<
=<
=<
F=<

As a simple PAL device example, consider the implementation
of the transfer function:
Output = 11G +1112
The normal combinatorial logic diagram fOr this function is
shown in Figure 4, with the PAL device logic equivalent shown
in Figure 5,

Figure 4

F=<
~

VVVV

"AfjO" ARRAY
(FIXEO)

Figure 6

Figure 5

Using this logic convention it is noYi possible to compa.re the
PAL device structure to the structure of the more familiar
PROM (Programmable Read-Only Memory) and PLA (Programmable Logic Array), The basic logic structure of a PROM
consists of a fixed AND array whose outputs feed a programmable OR array (Figure 6), PROMs are low-cost, easy to
program, and available in a variety of sizes and organizations,
They are most commonly used to store computer programs
and d,ata. In these applications the fixed input is a computer

1-4

The basic logic structure of the PLA consists of a programmableAND array whose outputs feed a programmable OR array
(Figure 7), Since the designer has complete control over ali
inputs and outputs,the PLA provides the ultimate flexibility for
implementing logic functions, They are used in a wide variety
of applications, However, this g'enerIrj-{j
D

b
~

Q

~

II

-

H>

Q

Q

l....-

I I

Figure 12

PAL Device Programming
PAL devices can be programmed in most standard PROM
programmers with the addition of a PAL device personality
card. For details on programming equipment, see the PAL
Device Programmer Reference Guide in this handbook.

PALASM (PAL Device Assembler)
PALASM is the software used to define, simulate, build, and
test PAL device units. PALASM accepts the PAL device
Design Specification as an input file. It verifies the design
against an optional function table and generates the fuse plot
which is used to program the PAL devices. PALASM is
available upon request for many computers.

HAL (Hard Array Logic) Device
The HAL device family is the mask programmed version of a
PAL device. The HAL device is to a PAL device just as a ROM
is to a PROM. A standard wafer is fabricated as far as the
metal mask .. Then a custom metafmask is used to fabricate
aluminum links for a HAL device instead of the programmable
TiW fuses used in a PAL device.

PAL Device Technology
PAL circuits are manufactured using the proven TTL Schottky
bipolar TiW fuse process to make fusible-link PROMs. An NPN
emitter follower array forms the programmable AND array.
PNP inputs provide high impedance inputs (O.25mA max) to
the array. All outputs are standard TTL drivers with internal
active pull-up transistors.

fuse" which can be blown to disable the verification logic. This
provides a significant deterrent to potential copiers, and it can
be used to protect proprietary designs.

PAL Device Part Numbers
The PAL device part number is unique in that the part number
code also defines the part's logic operation. The PAL device
numbering system is shown in Figure 13. For example, a PAL
14L4CN would be a 14-input. term, 4-output term, active-low
PAL device with a commercial temperature range packaged in
a 20-pin plastic DIP.

L

PAL 20 L 8 A ·2 C NS SHRP H01234
PAL = Programmable
Family

~

HAL "" Hard Array
Family

r-;;;;:AITERN NUMBER

.

NUMBER OF _---,-,------'

The Circuitry used for programming and logic verification can
be used at any time to determine the logic pattern stored in
the PAL device array. For security, the PAL device has a "last

MonoJlth/c

O~T~~~A:. ~~~~~~~~~G
Reliability

...

=

Enhanced
Other

ARRAY INPUTS
PACK~GE

OUTPUT TYPE _ _ _----'

H
L
C
P
R
RA
S
X
A

= Active High

,.. Active Low
.,. Complementary
= Programmable

= Plastic DIP

= Flat Pack

= Ceramic DIP

= Registered Asynchronous
= Shared

L

= Leadless

P

"" Pin Grid Array

= Registered

= Exclusive OR Registered

Chip Carrier

= Arithmetic Registered

NUMBEA OF OUTPUTS

A
B
D

N

J
F

NL "" Plastic Leaded
Chip Carrier
NS = prastic SKINNYDIP
JS = Ceramic SKtNNYDIP

L -_ _ _ TEMPERATURE CODE

C = Commercial
M "" Military

= High Speed
= Very High Speed

L-_ _ _ _ POWER

- 2 = Half Power

= Ultra High Speed

- 4 = Quarter Power

Figure 13

1-10

.

xxxx

SPEED _ _ _ _ _ _ __

PAL Device Data Security

...

W Memories

PAL ® Device Introduction

PAL Device logic Symbols

A PAL Device Example

The logic symbols for each of the individual PAL devices gives
a concise functional description of the PAL device logic
function. This symbol makes a convenient reference when
selecting the PAL device that best fits a specific application.
Figure 14 shows the logic symbol for a PAL10H8 array.

As an example of how the PAL device enables the designer to
reduce costs and simplify logic design, consider the design of
a simple, high-volume consumer product: an electronic dice
game. This type of product will be produced in extremely high
volume, so it is essential that every possible production cost
be minimized.
The electronic dice game is simply constructed using a free
running oscillator whose output is used to drive two asynchronous modulo six counters. When the user "rolls" the dice
(presses a button), the current state of the counters is
decoded and latched into a display resembling the pattern
seen on an ordinary pair of dice.
A conventional logic diagram for the dice game is shown in
Figure 15. It is implemented using standard TTL, 551 and M51
parts, with a total I.C. count of eight: six quad gate packages
and two quad D-Iatches. Looks like a nice clean logic design,
right? Wrong!!

PAl10H8

Figure 14

MonolitbicWMemories

1-11

PAL ® Device Introduction
vee
+5V
ROLL

IrD

~

-LJ

01

t:::=:rJ
~

~

J

.~l;f

2K

20K

20K

2K

":"

12011

~
@ i

::r:>
,-L.J"

r K 22N4402

~1~

02

03

J

~ [X

~o-

1

.

rW

IA

12011

1'1
2900

1.11
I~

M

12011

w-vvv-

~

...LJ

05

1

~

~

~

~

~~I

W
--[d

~~
:r
Figure 15

MonoIlthiCW Memories

12011

rW

r

I.A

I.A 120ll
I~

29011

1'1
1.11 12011

~

PAL ® Device Introduction
A brief examination of Figure 15 reveals two basic ,facts: first.
the circuit contains mostly simple. combinatorial logic. and
second. it uses a clocked state transition sequence. Remembering that the PAL device family contains ample provision for
these features. the PAL device catalog is consulted. The
PAL16R8 has all the required functions. and the entire logic
content of the circuit can be programmed into a single PAL
device shown in Figure 16.
.,
In this example. the PAL device effected an eight-to-one
package count repuction and a significant cost savings. This is
typical of the power and, cost-effective performance that the
PAL device family brings to logic design.

vee
ROLL

+5V

..L.

r-------~--~

~------------~

2K

120!l

Figure 16

Monolithic IDJiMemorifls

1-13

PAL® Device Introduction
Advantages of Using PAL Devices

interfaces required by many LSI functions. The combination of
PAL device flexibility and LSI function density makes a powerful team.

Design Flexibility
The PAL device offers the systems logic designer a whole
new world of options. Until now, the decision on logic system
implementation was usually between SSI/MSI logic functions
on one hand and microprocessors on the .other. In many
cases the function required is too awkward to implement the
first way and too simple to justify the second. Now the PAL
device offers the designer high functional density, high speed,
and low cost. Even better, PAL devices come in a variety of
sizes and functions, thereby further increasing the designer's
options.

Space Efficiency
The PAL device has a unique place in the world of logic
design. Not only does it offer many advantages over conventional logic, it also provides I)'lany features not found anywhere
else. Among the benefits of the PAL device family:
• Programmable replacement for conventional TTL logic.
• Reduces IC inventories substantially and simplifies their
control.
• Reduces chip count by at least 4 to 1.
• Expedites and simplifies prototyping and board layout
• Saves space with 20-pin and 24-pin SKINNYDIP packages,
and surface-mount PLCC packages.
• High speed: 10ns maximum propagation delay, on D series.
• Programmed on standard PROM programmers.
• Programmable three-state outputs.
• Special feature eliminates possibility of copying by
competitors.
All of these features combine together to lower product
development costs and increase product cost effectiveness.
The bottom line is that PAL devices save money.

Direct Logic Replacement

By allowing designers to replace many simple logic functions
with single packages, the PAL device allows more compact
P.C. board layouts. The PAL device space-saving 20-pin and
24-pin SKINNYDIP packages help to reduce board area
further while simplifying board layout and fabrication. This
means that many multi-card systems can now be reduced to
one or two cards, and that can make the difference between a
profitable success or an expensive disaster.

Smaller Inventory
The PAL device family can be
used to replace up to 90% of
the conventional TTL family.
This considerably lowers both
shelving
and
inventory
cataloging requirements. In
addition,
small
custom
modifications to the standard
functions are easy for PAL
device users, but not so easy for
standard TTL users.
In both new and existing designs, the PAL device can be used
to replace various logic functions. This allows the designer to
optimize a circuit in many ways never before possible. The
PAL device is particularly effective when used to provide

1·14

Monolithic

IFJ1I Memories

~

- - -.......,~8~~"

PAL® Device Introduction
Secure Data

High Speed

The PAL device family runs faster than or equal to the best of
bipolar logic circuits. This makes the PAL device the ideal
choice for most logical operations or control sequences which
require a medium complexity and high speed. Also, in many
microcomputer systems, the PAL device can be used to
handle high-speed data interfaces that are not feasible for the
microprocessor alone. This can be used to significantly extend
the capabilities of the low-cost, low-speed NMOS microprocessors into areas formerly requiring high-cost bipolar microprocessors.

Easy Programming
The members of the PAL device family can be quickly and
easily programmed using standard PROM programmers. This
allows designers to use PAL devices with a minimum investment in special equipment. Many types of programmable logic,
such as the PLA, require an expensive, dedicated program'
mer.

CD00970M

The PAL device verification logic can be completely disabled
by blowing out a special "last link". This prevents the unauthorized copying of valuable data, and makes the PAL device
perfect for use in any application where data integrity must be
carefully guarded.

Summary
The PAL devicefarnily of logic d.eVices offers logic designers
new options in the implementation of sequential and combinatorial logic designs. The family is fast, compact, flexible, and
easy to use in both new and existing designs. It promises to
reduce costs in most areas of design and production with a
corresponding increase in product profitability.

A Great Performer!

Mono/ithicWMemories·

1·15

PAL ®. Device Introduction

PAL16R6

THE PAL DEVICE
CONNECTION!

PAL 1646 Logic Symbols

PAL 16R6 Logic Diagram
PROGRAMMABLE

CIRCUIT
IDENTIFICATION

OUTPUT
BUFFERS

CURRENT SOURCE
AND PROGRAMMABLE
CIRCUITRY

REGISTERS

MISCELLANEOUS
ANOTESTING
CIRCUITRY

THREE-STATE

1-16

Monolithic WMemorles

PAL®/HAL® Device Specifications

Table of Contents
PAL/HAL Device Specifications

.............................................................2-1

Table of Contents for Section 2

............................................................2-2

PAL/HAL Devices

................................................................................2-3

Small 20 Series: 10H8, 12H6, 14H4, 16H2, 16C', 10L8,12L6, 14L4, 16L2 ........2-5
20 (standard) .............................. , ..•................•.................................2-8
20-2 (half power) ....•...................•.....................................................2-9
Medium 20 Series: 16L8, 16R8, 16R6, 16R4 ............................................ 2-19
20 (standard) ................•................................................................ 2-21
20A (high speed) ..........•................................................................. 2-22
20A-2.(Iligh speed and half power) ..•...........................................•....... 2-24
20A-4 (high speed and quarter power) .................................................. 2-25
20B (very high speed) ..•...............•.............................................•..... 2-26
20B-2(very high speed and half power) ................................................ 2-27
20B-4 (very high speed and quarter power) ............................................ 2-28
20D(ultra high speed) ................................. '" .................................. 2-29

Medium 20PA Series: 16P8A, 16RP8A, 16RP6A, 16RP4A
Large 20 Series: 16X4, 16A4
Large 20RA: 16RA8

........................... 2-37

................................................................ 2-45

........................................................................... 2-51

Small 24.Serles: 12L 10, 14L8, l6L6, 18L4, 20L2, 20C1

SmaJI24A Decoder Series: 6L 16A, 8L 14A

.............................. 2-55

.............................................. 2-65

Medium 24 Series: 20L8, 20R8, 20R6, 20R4 ............................................ 2-70
24A (high speed) ............................................................................ 2-73
24A-2 (high speed and half power) ...................................................... 2-75
24B (very high speed) ...................................................................... 2-76
Medium 24X Series: 20L 10, 20X10, 20X8, 20X4 ....................................... 2-81
24X (standard) ...........•................................................................... 2-83
24XA (high speed) .......................................................................... 2-85
Large 24RS Series: 20S10, 20RS10, 20RSS, 20RS4
Lllrge 24RA:20RA10
PAL32VX10/A

................................................................................. 2-103

PMS14R21/A

.................................................................................. 2-113

PAL10H20P8

................................................................................... 2-115

MegaPAI., devices: 32R16, 64R32
fMAX Parameters

2·2

................................... 2-90

.......................................................................... 2-98

........................................................ 2-119

............................................................................. 2-126

Waveforms

..................................................................................... 2-127

Test Load

......................•............................................................... 2-128

MonoIithlcW Memories

PAL®(Programmable Array Logic) Devices
HAL® (Hard Array Logic) Devices

Features/Benefits
•
•
•
•
•
•

Reduces SSI/MSI chip count greater than 4 to 1
Saves space with SKINNYDIP® and PLCC packages
Reduces IC inventories substantially
Expedites and simplifies prototyping and board layout
PALASM® 2 silicon compiler provides easy design entry
Security fuse reduces possibility of copying by competitors

Description
The PAL device family utilizes. an advanced Schottky TTL
process and the Bipolar PROM fusible link technology to
provide user-programmable logic for replaCing conventional
SSI/MSI gates and flip-flops at reduced chip count.
The HAL device family utilizes standard Low-Power Schottky
TTL process and automated mask pattern generation directly
from logiC equations to provide a semi-custom gate array for
replacing conventional SSI/MSI gates and flip-flops at reduced chip count.
The PAL device lets the systems engineer "deSign his own
chip" by blowing fusible links to configure AND and OR gates
to perform his desired logic function. Complex interconnections which previously required time-consuming layout are
thus "lifted" from PC board etch and placed on silicon where
they can be easily modified during prototype check-out or
production.
The PAL/HAL device transfer function is the familiar sum of
products. Like the PROM, the PAL device has a single array of
fusible links. Unlike the PROM, the PAL device is a programmable AND array driving a fixed OR array (the· PROM is a
fixed AND array driving a programmable OR array).
In addition the PAl/HAL device provides these options:

• Variable input/output pin ratio
• Programmable three,state outputs
• Registers with feedback
• Arithmetic capability
• Exclusive-OR gates
Unused input pins should be tied directly to Vee or GNO.
Product terms with all fuses blown assume the logical high
state, and product terms connected to both true and complement of any single input assume the logical low state. Registers consist of D-type flip-flops which are loaded on the lowto-high transition of the clock. PAL/HAL device Logic Diagrams are shown with all fuses blown, enabling the designer
to use the diagrams as coding sheets. PALASM 2 software
automatically generates a similar diagram, called the fuse plot.
The entire PAL device family is programmed using inexpensive conventional PROM programmers with appropriate personality and socket adapter cards. Once the PAL device is
programmed and verified, two additional fuses may be blown
to defeat verification. This feature gives the user a proprietary
circuit which is very difficult to copy.
To design a HAL, the user first programs and debugs a PAL
device using PALASM 2 software and the "PAL DEVICE
DESIGN SPECIFICATION" standard format. This specification
is submitted to Monolithic Memories where it is computerprocessed and assigned a bit pattern number, e.g., H01234.
Monolithic Memories will provide a PAL device sample for
customer qualification. The user then submits a purchase
order for a HAL of the specified bit pattern. number, e.g.,
HAL18L4 H01234. For details on ordering HAL devices,
please refer to the brochure, ProPAL, HAL, and ZHAL Devices: The LogicalSolutions for Volume Programmable Logic,
available from Monolithic Memories.

TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

Monolithic re'1!n
Memories InJrW
2-3

PAL/HAL Dev.ces
Register Bypass (Mega PAL Devices)
Outputs within a bank must either be all registered or all
combinatorial. Whether or not a bank of registers is bypassed
depends on how the outputs are defined in the equations. A
colon followed by an equal sign [: = 1 specifies a registered
output with feedback which is updated after the low-to-high
transition of the clock. An equal sign [ = 1 defines a combinatorial output which bypasses the register. Registers are bypassed in banks of eight. Bypassing a bank of registers
eliminates the feedback lines for those outputs.

Output Polarity
Output polarity is defined by comparison of the pin list and the
equations. If the logic sense of a specific output in the pin list
is different .from the logic sense of that output as defined by its
equation, the output is inverted or active low polarity. If the
logic sense of a specific output in the pin list is the same as
the logic sense of that output as defined by its equation, the
output is active high polarity. Note that the P, RA, RS, and
MegaPAL devices have programmable output polarity.

Product Term Sharing
(RS, MegaPAL Devices)

TTL-Level Preload Features
(RA, MegaPAL Devices)
Preload pins have been added to enable the testability of
each state in state-machine design. Typically, for a modulo-n
counter or a state machine there are many unreachable states
for the registers. These states, and the logic which controls·
them are untestable without a way to "set-in" the desired
starting state of the registers. In addition, long test sequences
are sometimes needed to test a state machine simply to reach
those starting states which are legal. Since complete logic
verification is needed to ensure the proper exit froln "illegal"
or unused states, a way to· enter these states must be
provided. The ability to preload a given bank of registers is
provided in this device.
To. use the preload feature, several steps must be followed.
First, a high level on an assertive-low output enable pin
disables the outputs for that bank of registers. Next, the data
to be loaded is presented at the output pins. This data is then
loaded into the register by placing a low level on the PRELOAD pin, PRELOAD is asynchronous with respect to the
clock.

The basic configuration is sixteen product terms shared between two output cells. For a typical output pair, each product
term can be used by either output; but, since product term
sharing is exclusive, a product term can be used by only one
output, not both. If equations call for an output pair to use the
same product term, two product terms are generated, one for
each output. This should be taken into account when writing
equations. PAL device assemblers configure product terms
automatically.

Product Term Editing
A unique feature of product term sharing is the ability to edit
the design after the device has been programmed. Without
this feature, a new PAL device had to be programmed if the
user needed to change his design. Product term editing allows
the user to delete an unwanted product term and reprogram a
previously· unused product term to the desired fuse pattern.
This feature is made possible by the product term sharing
architecture. Since each product term can be routed to either
output in a given pair by selecting one of two steering fuses, it
is possible to blow both of the steering fuses thereby completely disabling that product term. Once disabled, that product term is powered down, saving typically O.2SmA. The
desired change may now be programmed into one of the
previously unused product terms corresponding to that output
pair. Additional edits can be made as long as there are
unused product terms for the output in question.

PRESET Feature (PAL64R32 only)
Register banks of eight may be PRESET to all highs on the
outputs by setting the PRESET pin (PS) to a Low level. Note
from the LogiC Diagram that when the state of an output is
High, the state of the register is Low due to the inverting tristate buffer.

:,l-4

Monolithic

Programmable Set and Reset
(RA Family only)
In each SMAC, two product lines are dedicated to asynchronous set and reset. If the set product line is high, the register
output becomes a logic 1. If the reset product line is high, the
register output becomes a logic O. The operation of the
programmable set and reset overrides the clock. Note that set
and reset are in reference to the register, independent of
polarity.

Individually Programmable Register
Bypass (RA Family only)
If both the set and reset product lines are high, the sum-ofproducts bypasses the register and appears immediately at
the output, thus making the output combinatorial. This allows
each output to be configured in the registered or combinatorial
mode.

Programmable Clock (RA Family only)
One of the product lines in each group is connected to the
clock. This provides the user with the additional flexibility of a
programmable clock, so each output can be clocked independently of all the others.
.

W Memories

Small 20 Series
10H8, 12H6, 14H4, 16H2, 16C1, 10L8, 12L6, 14L4, 16L2

Small 20 Series
STANDARD
INPUTS

PAL10H8
PAL12H6
PAL14H4
PAL16H2
PAL16C1
PAL10L8
PAL12L6
PAL14L4
PAL16L2

..

10
12
14
16
16
10
12
14
16

OUTPUTS

POLARITY

8
6
4
2
2
8
6
4
2

HIGH
HIGH
HIGH
HIGH
BOTH
LOW
LOW
LOW
LOW

tpo

HALF POWER

(ns)

Icc
(mA)

(ns)

Icc
(mA)

35
35
35
35
40
35
35
35
35

90
90
90
90
90
90
90
90
90

65
65
65
65
65
65
65
65
65

40
40
40
40
40
40
40
40
40

tpD

Description

Performance

The Small 20 Series is made up of nine combinatorial 20-pin
PAL devices. They implement simple combinatorial logic, with
no feedback. Each has sixteen product terms total, divided
among the outputs, with two to sixteen product terms per
output.

Two performance options are available. The standard series
has a propagation delay (tpd) of 35. nanoseconds (ns), except
for the 16C1 at 40ns. Standard supply current is 90 milliamps
(mA). The half-power version consumes only 40mA, with a
speed of 65ns.

Polarity
Both active high and active low versions are available for each
architecture. The 16C10ffers both polarities of its single
output.

MonoIn,,/c·W Memories

Small 20 Series
.10H8, 12H6, 14H4, 16H2, 16C1, 10L8, 12L6, 14L4, 16L2

DIP Pinouts
10HS/-2

10L8/-2

12H6/-2

16H2/-2

14H4/-2

12L6/-2

14l4/-2

Monolil.ic WMemories

16C1/-2

16L21-2

Small 20 Series
10H8, 12H6, 14H4, 16H2, 16C1, 10L8, 12L6, 14L4, 16L2

PLCC Pinouts
10H8/·2

12H6/·2

10L8/·2

16H2I·2

Monolithic

lUll Memories

2·7

Small 20 Serle.
10H8, 12H6, 14H4, 1.6H2, t6e 1, 10L8, 12L6, 14L4, 16L2

Operating Conditions
MILITARY
SYMBOL,

I
Vee

COMMERCIAL

PARAMETER

,;
"

TA

UNIT
MIN

,

Supply voltage

4.5

Operating' fr.~e-air 't~mperature

-55

TYP

MAX

MIN

TYP

MAX

,5.5

4.75

5

5.25

V

75

°C

5

0

Operating, case temperature

Te

°C

125

,

ElectrJcalCharacterlstics
SYMBOL

Over Operating Conditions

PARAMETER

TYP

MAX

,':"

O.S

V

11 = -lSmA

-O.S

-1.5

V

= 0.4V
VI = 2.4V
VI = 5.5V
IOL = SmA
IOL = SmA
IOH = -2mA
IOH = -3.2mA
Vo = OV

-0.02

-0.25

mA

MIN

TEST CONDITIONS

; 'Low:level i~put voltage

VIL 1
VIHI,

High-level input voltage

Vie

Input clamp voltage

IlL

LoW-level' input ~urrent

IIH

High-level input current

II

Maximum .input current

2

= MIN'
Vee = MAX
Vee = MAX
Vee = MAX

Vee

"c'"

Vee

= MIN

Vee

= MIN

.OUtput short-circuit current

Vee

Supply current

Vee

= 5V
= MAX

; Low-level output voltage

VOL': '
'

,

VOH

High-level output voltage

..

,

IOS2

"

Icc

V

VI

MIL
COM
MIL
COM

UNIT

0.3

2.4

2.S

-30

-70

25

!lA

1

mA

0.5

V

V
-130

mA

90

mA

55

Switching Characteristics
,

,

SYMBOL

tpb
I.
2.

TEST
CONDITIONS

PARAMETER

Input. or
feedback to
output

Exoopt 16C1
16Cl

MILITARY

COMMERCIAL
UNIT

MIN

TYP

R, = 560n
= 1.lkn

R2
:

MAX

MIN

TYP

MAX

25

45

25

35

25

45

25

40

ns

,,-:
These Sre absolute values with respect to the ground pin on the device and include all overshoots due to system andlor tester noise. Do not attempt to test these
values without sunable equipment.
'
No more than o,ne .output should be shorted at a time and duration of the Short circuit should not exceed one second.

2-8

Monolithic WMemor/es

Small 20-2 Seri••
10H8-2, 12H8-2, 14H4-2, 18H2-2, 18C1.2, 10L8-2, 12L8-2, 14L4-2, 18L2-2

Operating Conditions
COMMERCIAL

MILITARY
SYMBOL

UNIT

PARAMETER
MIN
,

Vee

Supply voltage

TA

Operating free-air temperature

Electrical Characteristics
SYMBOL
VIL l

,

TVP

4.5

MIN

TVI'

5.5

4;75

5

126

0

MAX

5

-55

~MAX

5.25

V

75

·C

Over Operating Conditions

PARAMETER

MIN,

TEST CONDITIONS

Low-level ioput voltage

TVp' MAX

UNIT

O.S

,

V

VIH l

High-leVel inplrt voltage

VIC

Input clamp voltage

II = -1SmA

-o.s

-1.5

V

IlL

Low-level input current

Vee - MAX

VI = 0.4V

-0.'02

-0.25

mA

IIH

High-level inplrt current

'Vee = MAX

VI" 2.4V

I,

Maximum input CUfre!!t

,Vee -MIN

VOL

Low-level output voltage

VOH

High"level output voltage

108 2

Output short-circuit current

Icc

Supply current

Switching Characteristics

2

Vee = MAX

""';

Vee =' MIN

,

;

tpD

= 4mA'
= 4mA

10L

Com

10L

Mil

10H'· -1mA

G9m

10H,= -1mA

"ee'= 5V ':
,Vee = MAX

0.3

Vo - OV

. . SO

-70

,

25

p.A

1

mA
V

0.5

V
-,130

mA

45

mA

30
"

'

,MILITARY

COMMERCIAL
UNIT

TEST

MIN'
Input or feedback to output ;

2.S

,

Over Opsratlftg Condlttone

PARAMETER

2.4,

,

"

SYMBOL

VI- 5.5V '

Mil

Vee - MIN

V

TVP

R1 =i 1.12kn
R2 - 2.2kn

45

1

MAX
;

SQ

MIN
"

TYP

MAX

,45

1,(,;,':' 6'0'

,

ns

1. These are absolute values with ",spec! to the ground pin on the d8VIce and Include all oversh~ due to system and/~r teeter noise. Do not attempt to test these
values without suitable equipment.
,
"
, ,
2.' No more 1hen one au""'t should be shorted at a time and, duration of thif short circuit lIhOuld not' exceed one second:
:

~

Small 20.S.ri••'
10H8 Lqic Diagram.

10H8
• 1 2' I

.,

II

1213

•• n

....

"

:r

~

I

'"

1

2
~
·.r

3

~

'.

I
I

I.

...
r

•

....

.>

..

n

-

11

"

~

...

-

~

'5

5

~

r

"

,5

""

.

6
•.
.:,....-.,.....

.."

I
.

-

W"""""o

. .

'4

'

1
r

....
•

\

""""'

13

~

12

...

-----I

.,

II

-

.

t
-----I .

II

...

• 1 2':1

2-10

• &

I •

."

'"
1111

21 ..

....

21213111

Small 20 Series
12H6 Logic Diagram

12H6
1

1123451'

..

I.

1213

.&n

..

.."

24252121

21213031

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M.dlum 20

se,I••

ieLB, ieRB, ieRe, ieR4
Medium 20 Series
OUTPUTS
DEDICATED INPUTS
REGISTERED

COMBINATORIAL
'.

PAL16L8
PAL16R8 .
PAL16R6
PAL16R4

8 (61/0)
0
21/0
41/0

10
8
8

a

Description
The M8dium2o. Series' offers the four most popular PAL
device architectures.. It also provides the Jastest PAL devices
in the industry.
The. MEldium' 20 . Series consists of four devices, eaCh ,with
sixteen array inputs and eight outputs.• T,he devices have
either 0, 4, 6, or 8 registered outputs, with the remaining being
cornf?inatorial. Each o( the registered outputs feeds back into
the. array, fotsequential deSigns. Thecombinatorialoiitputs
also feed back into the array, except for tw:o of the outputs on
the 16L8,.This feedback allows the output to also operate as
an input if the Qutput. is disabled.

Suffix
(standard)
A
A-2
A-4
6 or Bp·
B-2
6-4
D

Polfir:Uy .
.AII oUt.P,tits ~re active low,

.Perforrn8'nce
Sevet~lj~peEld/pow.et.versiOns a~ .available:.
, ,-I~'

•

t,o

Icc

(mA)

(ns)
35
25
35
55
15
25
35
10

180
180
90
50'
180
90
.55
180 .

• contact MonolithIc Memonesfor·(jatasheet
The o Series offers the fastest TTL programmable logic
,de'{ices in the industry, at 10nstPd.,'.

Enable
The combipatorial, outputs ,are enabled by a product term, The
reglsteredoutp~tS areer'iabl",d' by a common enab)epln.

0
8
6
4

Cc'

C

C

Preload and Power:'up' Reset'
TheBP Series offers 'l:I9ister preload for devicetEl!ltability.
The .regiSters can bepieloacied from. the outputs by u,sing
supervoltages (see waveforms at enQ qf seetion) .In ~rder to
Simplify functional testil'lll. The. F'A~OBP SerI~S .also ,OfferS
Power-up Reset,wheretlythe registers poWer W \0< a logiC
r..oW,settirig the active;::loW o~uts; to a'lbgic HIGH."

._cHUm, 20, Ser•••
1SIA,18RS, 1,SRS, 1SR4

DIP Pinouts
181A/AiA~2/A-41
B/B~2/B-4lD(

18R8/A/A-2lA-4I

,;;

B/B-2/B-4lD

18R4/A/A-2/A-4l
B/B-2/B-4ID

""""'.
PLCC'Plnouts
10R8/AIA-21A-41
'81B-21B-41O

18*/AIA~IA-41
B/B-2IB-4/D

CD00512M

Medium 20 Se'I••
i6La,' i6Ra, i6R6, i6R4

Operating Conditions

'"

~

COMMERCIAL1
SYMBOL

PARAMETER

,

low

1w

Width of clock

tau

Set up time from input
or feedback to clock

th

Hold time

TA

Operating free-air temperature

Tc

Operating case' temperature

High
16RB, 16R6, 16R4

,

5.25 e"

35

ns

25,'

0

-15

"·C'

TEST CONDITIONS

'TYP) , >lIn'

MIN
:le

E).B

Vic

Vee = MIN

II = -1BmA

·-O.B

low-level input current

Vee - MAX

VI - 0.4V

-0.02

High-level input cumint

"

VOH

,.'

Vee = MAX

VI = 2.4V

Vee = MAX

VI": 5.5V

lOW-level output voltage

Vee - MIN

Com

10l =24niA

'High-level output voltage

Vee = MIN'

Com

'IOH'" -3.2mA

loil 3
lozR 3

Off-state output current

loS4

Output short,circuitcurrent

,

. Supply current

,

"

.

"

Vee =5V

Vo - OV'

"

,Vee = MAX

tpD

..

ii'i "

:;

2.4

i

,JA
ritA
'V

'25

f
"

.O·r, ,.' a.5.
2.8

V
pA'

-100
"

'...30' '·:';'70,

16R4, 16R6, t6R8, 1618

120

tOO

/lA,

-130

I1lAl
rnA '

1BO'

Over Operating Condltlona

:',,:'

,

.. "',
"

,

"

Vo ;"2.4V

'

i-;

SYMBOL

V"
-0.25 "rnA,

".'"

SwltChlrig Characteristics
;

'Y, ,
--1.5

Vo '" 0.4V

Vee = MAX
,

lee

i,UNlt;
' "V-

2,.,

Maximum input, current

,

,,',

In'put clamp voltage

"

·c

75

','

"

PARAMETER

..

,~ns

low-level input voltage

,

ns

0
"

V

1°"

High-level input voltage

II
VqL

2,

S.
10

ViH 2

IIH 3

3.
4.

4.75

,

MAX

'\lll 2;

IIl 3

1.

TYP

25
~,5

,

Electrical Characteristics
SYMBOL

MIN

..,

Supply voltage

Vee

UNIT

,

PARAMETER

:

.,

" ~

"

tclK

Clock to output or feedback

16R6, 16R4, 16lB

.{-:, .

,

'MIN"

"

"

'Input or feedb8ck to
output

.. COMME~I~L .. -

..
"TEST ,CONDITIONS

MAX

TtP,
2,5'
15

,

.,,'

,

.

'

~,.'~

""n~

'25

..

ns,
ns

0""
'"

tpzx

Pin 11 to output enable except 16LB

,15

25

tpxz

Pin ,11 to output disable except 16lB

R1 - 200n

15

25

ns,

tpzx

Input to output enable

16R6, 16R4, 1616

Rli =S90n

25

35

,ns

tpxz

Input to output disable

16R6, 16R4, 1618

25

35

',ns

tMAX

Maximum frequency

16RB, l6R6, 16R4

16

'

,'"

,"

e'

UNIT

25

MHz

'. ..

The PAL20 Series IS desogned to operate over the full military operating COnditions., For 8V8Ilabilily and .pec~lcaUons. contact Monol~hic Memories., '
These are absolute voltaQes with respect to the groUnd pin on,the device and include all overshoots due to systam and/or testar noise: Do,not allemptto test
theSe values ~hOUj suitable equipment.
"
I/O pill,leaI\age is the worst case of I,L and 1= (ot'I'H and 1Q2H)'
No more then 'one output should be'shorted at a lime and duration of the short circuli should not exceed one seCOnd.

,1

Medium 20A Series
16L8A, 16R8A, 16R6A, 16R4A

Operating Conditions
MILITARY

UNIT
MIN

Vee

MAX
5.25

5

4.75

5

15

10

High

20

10

1.5

10

16R8A. 16R6A. 16R4A

30

15

25

15

-10

Set up time from input
or feedback to clock

th

Hold time

0

TA

Operating free-air temperature

-55

Te

Operating case temperature

V
ns

0

ns

-10

0

ns
75

125

°C
°C

Over Operating Conditions

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX
0.8

Low-level input voltage

UNIT
V

VIH l

High-level input voltage

Vie

Input clamp voltage

Vee = MIN

11 = -18mA

-0.8

-1.5

V

IlL 2

Low-level input current

Vee = MAX

VI = OAV

-0:02

-0.25

mA

IIH2

High-Iel/el input current

Vee = MAX

VI = 2AV

25

/.LA

II

Maximum input current

Vee = MAX

VI = 5.5V

1

mA

VOL

Low-level output voltage

Vee = MIN

VOH

High-level output voltage

Off-state output current

105 3

Output short-circuit current

lee

Supply current

V

2

Vee = MIN

Vee = MAX

IOZH2

2.
3.

5.5

TYP

10

tsu

10ZL 2

1.

MIN

20

Width of clock

SYMBOL

MAX

4.5

lw

Elect,rical Characteristics

TYP

Low

Supply voltage

,

VIL 1

COMMERCIAL

PARAMETER

SYMBOL

Vee =5V

Mil

10L = 12mA

Com

IOL = 24mA

Mil

10H = -2mA

Com

10H = -3.2mA

0.3

204

0.5

2.8

V

V

Vo = OAV

-100

Vo = 2AV

100

/.LA
/.LA

-70

-130

mA

120

180

mA

Vo = OV

Vee = MAX

-30

These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and/or tester ,noise. Do not attempt to test
these values without suitable equipment.
1/0 pin leakage is the worst case of 'll and 'OZL. (or 'IH and 'OZH)'
No more than one output should be shorted at a time and duration of the 'short circuit should not e'xceed one second.

2-22

Monolithic WMemories

Medium 20A Series
16L8A, 16R8A, 16R6A, 16R4A

Sitch"
W
In9 Characteristics over 0 peratl n9 CondHlons
SYMBOL

PARAMETER

tpD

Input or
feedback to
output

tCLK

Clock to output. or feedback

tpzx

Pin 11 to output enable except
16L8A

tpxz

Pin. 11 to output disable except
16L8A

tpzx

Input to
output enable

tpxz
f MAX

TEST
,CONDITIONS

MILitARY

COMMERCIAL
UNIT

MIN

16R6A, 16R4A,
16L8A

TVP

MAX

MIN

TVP

MAX

15

30

15

25

ns

10

20

10

15

ns

10

25

10

20

ns

11

25

11

20

ns

16R6A, 16R4A,
16L8A

10

30

10

25

ns

Input to
output disable

16R6A, 16R4A,
16L8A"

13

30

13

25

ns

Maximum
frequency

16R8A, 16R6A,
16R4A

,

R1
R2

= 2000
= 3900

20

40

'.

28.5

40

MHz

2-23

Medium 20A-2 Series
16L8A.2, 16R8A-2. 16R6A.2, 16R4A-2

Operating Conditions
COMMERCIAL

MILITARY
SYMBOL

UNIT

F'ARAMETER
TYP

MIN
Vee

Width of clock

Is"

Set up time from input
or feedback to clock

4.75

5

25

10

High

25

10

25

10

16R6A-2, 16R4A-2,
16R8A-2

50

25

35

25

-15

0

-15

Hold time

0
-55

5.5

125

V
ns
ns

ns
75

0

°C

Over Operating Conditions

PARAMETER

MIN

TEST CONDITIONS

TVP

MAX

UNIT

VIl 1

Low-level input voltage

VIH 1

High-level input voltage

Vie

Input clamp voltage

Vee = MIN

11 = -18mA

-0.8

-1.5

V

IIl 2

Low-level input current

Vee = MAX

VI = OAV

-0.02

-0.25

mA

IIH2

High-level input current

Vee = MAX

VI = 2AV

25

IJ.A

II

Maximum input current

Vee = MAX

VI = 5.5V

1

rnA

VOL

Low-level output voltage

Vee = MIN

VOH

High-level output voltage

0.8
2

Vee = MIN

Off-state output current

Vee = MAX

IOS3

Output short-circuit current

Vee = 5V

Icc

Supply current

Vee = MAX

Mil

IOl = 12mA

Com

IOl = 24mA

Mil

IOH = -2mA

Com

IOH = -3.2mA

IOZH2

Switching Characteristics
SYMBOL

1.

5.25

5
10

Operating free-air temperature

IOZl 2

2.
3.

MAX

4.5

th

SYMBOL

TYP

25

TA

Electrical Characteristics

MIN

Low

Supply voltage

tw

MAX

V
V

0.3

204

0.5

2.8

V

V

Vo = OAV

-100

Vo = 2AV

100

/lA

-130

rnA

90

mA

Vo

=

-30

OV

-70
60

/lA

Over Operating Conditions

TEST
CONDITIONS

PARAMETER

tpD

Input or
feedback to
output

teLK

Clock to output or feedback

tpxZlZX

Pin 11 to output disable/enable
except 16L8A-2

tpzx

Input to
output enable

16L8A-2, 16R6A-2,
16R4A-2

tpxz

Input to
output disable

16L8A-2, 16R6A-2,
16R4A-2

'MAX

Maximum
frequency

16R8A-2, 16R6A-2,
16R4A-2

MILITARY

COMMERCIAL
UNIT

MIN

TVP

16L8A-2, 16R6A-2,
16R4A-2

MAX

25

50

15
200n

R2 = 390n

-R1

=

14

TYP

MIN I

MAX

25

35

ns

25

15

25

ns

15

25

15

25

ns

25

45

25

35

ns

25

45

25

35

ns

25

I

16

25

MHz

These are absolute voltages with respect to the ground Pin on the device and Include all overshoots due to system andlor tester nOIse. Do not attempt to test
these values without suitable equipment.
110 pin leakage is the worst case of IlL and IOZl (or IIH and IOZH)'
No more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

2-24

Monolithic

W Memories

Medium 20A-4 Serle.
18L8A-4, 18R8A-4, 18R8A-4, 18R4A-4

Operating Conditions
MILITARY
SYMBOL
.

~

Vee

COMMERCIAL
UNIT

PARAMETER
,

MIN

Supply voltage

I Low
I High

lw

Width of clock

t"..

Set up time from input
or feedback to clock

I 16R8A-4, 16R6A-4i
16R4A-4

"

TYP

MAX

MIN

5: '

5.25

5

40

20

30

20

40

20

30

20

90

45

60

45

-15

0

-15

th

Hold time

0

Operating free-air temperature

-55

4.75

MAX

4.5

TA

5.5

TYP

125

V
ns
ns
ns

0

·C

75

',:

Electrical Characteristics
SYMBOL

Over Opl'lratlng Conditions

PARAMETER

Low-level input voltage

VIH I

High-Ievel'input voltage

VIC

,Low-level input current

IIH2

High-level input current

II

Maximum input' current

VO~

Low-level output voltage

VOH

High-level output voltage
,

IOZl2

,

= MIN

,

Icc

'"

. '

-1.5

V

Vee "!',MAX

VI - 0.4V

-0.02

-0.25

mA

Vce" MAX

VI - 2.4V

Vee = MIN

Vee = MAX

PARAMETER

tpXZ/ZX

1.

MH

10H = -lmA

Com

10H = -lmA

2.4

0.5

V

'.'

2.8

V

p.A

V6 = O.4V

-100
100

p.A

-130

rnA

50

mA

-70

-30

Vo':" OV

30

TEST
CONDITIONS

Pin 11 to output disablel enable
- except 16L8A-4

tpzx

16R6A-4,16R4A-4,
16LBA-4

fp~

Inpu~ to
output disable: '.

16R6A-4, 16R4A-4,
16LBA-4

16RBA~4••16R8A;4;
16R4A-4

COMMERCIAL

MILITARY

UNIT
MIN

TYP

MAX

MIN

TYP

I".

Clock to .output or feedback

,Maximum".
frequency

0.3
,"

p.A
mA:

Vo= 2.4V

16R6A-4, 16R4A-4,
16L8A-4

Input to
output enable

~MAx

2.
3.

...

1

Over Operating CondHlonB

""

tclK

10l = 8mA

= 5V

Supply current

Input or
feedback to
output

Com

,

-.1

tpo

Mil

= 5.5V
10l = 4mA

25

VI

Vee = MAX,
Vee

SYMBOL

,:,

Vee = MIN

Output short-circuit current'

Switching Characteristics

V
-0.8

Vee = MAX

Off-stale output current
,

V

II = -18mA

IOZH2
IOS3

UNIT

0.8

2
Vee

IIl2

,MAX

TYP

, '

"'

Input clamp voltage

"

MIN

TEST CONDITIONS

Vil l

R1,=.800n

35

)5

20

45

15

,,40"

.

; R2 ='1.56kn

35

)

,

30

65

30

65

MAX

I

55

ns

20

35

·n$,

15

30

11!1

30

50

ns

30

50

ns

....

.'

,"

8

18

11

18

.MHz

to the gro~nd:. PIn an .lI)e dey,,,,, and ,nclude all ov·
I
No mote than one. output should be shorted at a time and duration. of the short circuit should not exceed one second.

These are absolute voHages with respect
these values without suitable equipment.

to test

2-25

Medium 20B Series
16L8B, 16R8B, 16R6B, 16R4B

Operating Conditions
COMMERCIAL 1
SYMBOL

UNIT

PARAMETER
TYP

MAX

5.25

4.75

5

low

10

6

High

10

5

16RSB
16R6B
16R4B

15

10

Supply voltage

Vee

MIN

~

Width of clock

t.u

Setup time from input
or feedback to clock

th

Hold time

0

-10

TA

Operating free-air temperature

0

25

Electrical Characteristics

V
ns

ns
ns
75

°C

Over Operating Conditions

COMMERCIAL
SYMBOL

TEST CONDITION

PARAMETER

UNIT
MIN

VIl 2
VIH 2

High-level input voltage

Vie

Input clamp voltage

Vee

IIl 3

low-level input current

Vee

High-level input current

Vee

Maximum input current

Vee

VOL

low-level output voltage

Vee

VOH

High-level output voltage

Vee

IIH 3

TYP

low-level input voltage

"-""

II

O.S

Off-state output current

Vee

= MAX

105 4

Output short-circuit current

Vee

lee

Supply current

Vee

= 5V
= MAX

V
V

2

= MIN
= MAX
= MAX
= MAX
= MIN
= MIN

IOZl 3
IOZH 3

Switching Characteristics

MAX

11 = -1SmA

-O.S

-1.5

V

= O.4V
VI = 2.4V
VI = 5.5V
10L = 24mA
10H = -3.2mA
Vo = O.4V
Vo = 2.4V
Vo = OV

-0.02

-0.25

mA

VI

0.3
2.4

25

jJ.A

1

mA

0.5

-100

-30

V
V

2.S

jJ.A

100

jJ.A

-70

-130

mA

120

1S0

mA

Over Operating Conditions

PARAMETER

SYMBOL

TEST
CONDITIONS

COMMERCIAL
UNIT
MIN

TYP

MAX

tpo

16lSB, 16R4B, 16R6B input or feedback to output

12

15

ns

IcLK

Clock to output or feedback except 16lSB

S

12

ns

tpzx

Pin 11 to output enable except 16lSB

Commercial

10

15

ns

tpxz

Pin 11 to output disable except 16lSB

R1 = 200n

10

15

ns

tpzx

Input to output enable

16R6B, 16R4B, and 16lSB

R2

= 390n

12

22

ns

tpxz

Input to output disable

t6R6B, 16R4B, and 16lSB

12

15

ns

16RSB, t6R6B, 16R4B

Feedback

37

45

Maximum frequency

No feedback

50

55

fMAX

MHz

1.

The PAL20B Series is designed to operate over the full military operating conditions. For availability and specifications. contact Monolithic Memories.

2.

These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and/or tester nOise. Do not attempt to test
these values without suitable equipment.
I/O pin leakage is the wOrst case of I'l and 10Zl (or I'H and 10ZH).
No more than one output should be shorted at a time and duration of the short· circuit should not exceed one second.

3.
4.

2-26

MonO/lthlc1FJJl Memories

Medium 20B-2 Series
16L8B-2, 16R8B-2, 16R6B-2, 16R4B-2

Operating Conditions
COMMERCIAL 1
SYMBOL

UNIT

PARAMETER
MIN

Vee

Supply voltage

tw

Width of clock

tsu

Setup time from input or
feedback to clock

TYP

MAX

5.25

4.75

5

Low

15

10

High

15

10

16R8B-2
16R6B-2
16R4B-2

25

15

th

Hold time

0

-10

TA

Operating free-air temperature

0

25

Electrical Characteristics

V
ns

ns
ns
75

°C

Over Operating Conditions

COMMERCIAL
SYMBOL

PARAMETER

UNIT

TEST CONDITION
MIN

TYP

MAX

VIL 2
V IH 2

High-level inpLJt voltage

Vie

Input clamp voltage

Vee = MIN

11 = -18mA

-0.8

-1.5

V

IlL 3

Low-level input current

Vee = MAX

VI = O.4V

-0.02

-0.25

mA

IIH 3

High-level input current

Vee = MAX

VI = 2.4V

25

/lA

II

Maximum input current

Vee = MAX

VI = 5.5V

1

mA

VOL

Low-level output voltage

Vee = MIN

IOL = 24mA

VOH

High-level output voltage

Vee = MIN

IOH = -3.2mA

Off-state output current

Vee = MAX

IOZL 3
IOZH 3

0.8

Low-level input voltage

105 4

Output short-circuit current

Vee = 5V

lee

Supply current

Vee = MAX

Switching Characteristics
SYMBOL

V
V

2

0.3
2.4

0.5

2.8

V
V

Vo = O.4V

-100

!1A

Vo = 2.4V

100

/lA

-250

mA

90

mA

-30

Vo = OV

-100
60

Over Operating Conditions

PARAMETER

tpo

Input or feedback to output 16L8B-2, 16R4B-2, and
16R6B-2

TEST
CONDITIONS

COMMERCIAL
UNIT
MIN

TYP

17

MAX

25

ns

telK

Clock to output or feedback except 16L8B-2

10

15

ns

tpzx

Pin 11 to output enable except 16L8B-2

Commercial

10

20

ns

tpxz

Pin 11 to output disable except 16L8B-2

Rt

11

20

ns

tpzx

Input to output enable 16R6B-2, 16R4B-2, and 16L8B-2

R2

= 200n
= 390n

10 •

25

ns

tpxz

Input to output disable 16R6B-2, 16R4B-2, and 16L8B-2

13

25

f MAX

Maximum frequency 16R8B-2, 16R6B-2, and 16R4B-2

28.5

40

ns
MHz

1. The PAL20B-2 $eries is designed to operate over the full military operating conditions. For availability and specifications, contact Monolithic Memories.
2., These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and/or tester noise. Do not attempt to test
these valUes without suitable equipment.
3. I/O pin leakage is the worst case of I," and 10Zl (or I'H and 10ZH)'
4. No more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

MonolithicWMemOrieS

2·27

Medium 20..48erl••
i6R6..4, 16R4....4

16L88~4,.16Rea-4,

Operating Conditions
COMMERCIAL1
SYMBOL

PARAMETER

UNIT

:
VCc

.

, ::

MIN

4;75

.

; Supply volta:!je
Low

Width· of clock

fw

. High

.Setup time from input or
feedback to clock

tsu:

TYP

····5

?5

10

25

10

..

16RB8·4
16R68·4
16R48·4

MAX

'

35

.

5.25

V
ns

:;!'5

ns

"

~.

Hold time

()

;"';10

ns

TA

Operating free·air temperature

0

'25

·C

Electrical Characteristics

\'

75,

I

Over Operating Conditions,

COMMERCIAL
SYMBOL

,PARAMETER

TEST CONDITION

UNIT
MIN

VIl 2

Low-level input voltage

V2
IH

High-level input voltage
Input clamp voltage

VIC
. '1 IL 3
IIH 3

'.2,'
Vee = MIN
"Icc = MAX

VI" O.4V

High~level input ,current

Vee - MAX

VI - 2.4V

.' .

Maximl,lm input current

Vcc = MAX

VI'" 5.5V

Vee = MIN

10l = SmA

VOH

•High·level output voltage

Vec= MIN

, Off·state' output current

Yec= tiII,AX·

Ol,ltput short-circuit current

Vee

Icc

Supply current

Vec= MAX

,

".5V

25
1

2.4

tpzx

rnA
V;
V

p.A

100

p.A

-250

rnA

55

m.A

',30'

;

p.A

Over Operating Conditions

Clockt~ output;or feedback except .16LB8-4
,i,'

-1Od

-30

Vo - OV

COMMERCIAL

TEST
CONDiTIONS

UNIT
MIN

Or

tell(

2.B
':100

Inpl,lt
feedback to outp~t 16LBa~4, 16R48-4,and '
16R68·4

tpO'

0.5

Vo = 2.4V

. PARAMETER

"~./

V
rnA

0.3

IOii=-1mA'

.

',SYMBOL

-1.5
-0.25

Vo = 0.4V

1004

Switching Characteristics

-1>.B
-0.02

.

Low·level output voltage

V
V

II = -18r\1A

Low,level input current

II'

iOZH 3

: MAX

I, O.B

VOL
IOZl 3

TYP

Pin, 11 to output enableexcept,16LB8.4

TYP

MAX

;0;

,':

"

. c'

tpxz

.

Pi/i11 to ,output disable except 16LB84

fpzx

:'

Inpultooutput enable 16R68-4, 1!)R48-4. arid 16LBS·4'

;

'.'

\pXz

Input to output disable 16R68·4, 16R4B-4,and 16lBS:;.!';:

fMAx

Maximurnfrequency 16RBB·4, 16f!68,-4!and 16R4B-4::

",~5

35

ns;

,:15

25

,ns'

15

25

ns

15

25

ns,

25

35

OS

25

35

','

'R1 =800n "

.',

;'

R2 ";1 ;56Kf!

','
';

,

".

16" .'

,25

.

;.

,ns,
MHz

1, The PAL20B-4Series is desigrred to operate Oller the full mifitaryoperaling con~tio"",'For availability andtapecificalions. ~ M'lnofllhiC Mameri",,;
2. ,These are absOlute voltages with respect to the ground pin on the device' and' Include ail 'Ollershoots doe' to system and/or tes!8rnoise. DO not attempt to test
theSe values without suitable equipment.
3. 1/0 pin leakage is the WOrst case of IlL and IOZL (or 11K ~nd loZli)'
' '"''
4. No more than one output should be shorted at a time aM duration of the short cltcuit should nol ilxceed one second.

Medium 20D Serle.

16L8D, 16R8D,16R6D, 16R4D

Operating Conditions
SYMBOL
,

Vcc

Supply voltage

Iw

Width of clock

tsu

Setup time from input
or feedback to, clock

th

Hold time

TA

Operating' free-air temperature

COMMERCIAL 1,

',,"

"PARAMETER

I Low
I High
1eR8D. 16R6D. 16R4D

UNIT
MIN

TYP

4.75

'5

8

6

8

5

MAX
5.25

V
ns

8

ns

0

-6

ns

0

25

10

.'

75

·C

Electrical Characterlsttes
SYMBOL
V IL2

PARAMETER
"

V IH 2

Low-level input voltage

TEST CONDITION
",

MIN

TYP

MAX
0.8

'.'

2

High-level input voltage

UNIT
.V
V

VIC

Input clamp voltage

Vee -MIN

11 = -18mA

-0.8

-1.5

V

'IL3

loW-level input cllrrent

Vee = MAX

VI = O.4V

-0.02

-0.25

mA

IltP

"

High~levelinput

current

Maximum input current

11

Vee

= MAX

= 2.4V

25

pA

VI - 5.5V

200

pA

0.5

V

VI

Vee· MAX

VOL

Low-level output voltage

Vee = MIN

IOL - 24mA

VOH

High-level output voltage

Vee = MIN

IOH" -3.2mA

,

IOZL3

Off-state output current

IOZH3

1084

Vee = MAX
.'

'.

Output shor1~circuit current

I
I

,Vcc = 5V

2.4

3.4

Vo

= 2.4V

Vo =,OV

Supply current

Vcc" MAX

CIN

Inpill CapaCitance ,.

"'IN = 2.0V@f - 1MHz

COUT

Output Capacitance

CCLK; EN

Clock/Enable Capacitance

= .1MHz

, VCLKEN = 2.0V@f =1MHz

V
-100

Vo = 0.4V

lee

Vour " 2:0V@f

0.3

-30

PA

100

pA

-70

-130

'rnA

120

180

mA

2
4

pF

9
-c-

Medium 20D Series
16L8D, 16A8D, 16A6D, '16A4D

Switching Characteristics
SYMBOL

3.
4.

TEST
CONDITIONS

PARAMETER

COMMERCIAL
UNIT
MIN

TYP

MAX

tpD

Input or feedback to output 16L8D, 16R6D,16R4D

3

8

10

ns

!eLK

Clock to output or feedback except l6L8D

2

6

8

ns

tpzx

Pin 11 to output enable except 16L8D

3

8

10

ns

tpxz

Pin 11 to output disable except 16L8D

R t = 200n

3

8

10

ns

tpzx

Input to output enable 16L8D, 16R6D, 16R4D

R2 = 390n

1

8

10

ns

tpxz

Input to output disable 16L8D, 16R6D, 16R4D

1

8

10

ns

55.5

70

62.5

75

f MAX
1.
2.

Over Operating Conditions

Maximum frequency
l6R8D, l6R6D, l6R4D

I Feedback
I No feedback

MHz

The PAL20D Serie~ is desjg~ned to ope~ate over the full military operating conditions. FQr availability and specifications, contact MonolithiC Memories.
These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and/or tester noise. Do not a~empt to test
these values without suitable equipment.
'
1/0 pin leakage is the worst case of I,l and 10Zl (or I'H and 10ZH).
No more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

Monolithic

m

Memories

Medium 20D Serle.

16L8D, 16R8D, 16R6D, 16R4D

Metastability
Metastability is a condition which can occur in any latch or flipflop if the minimum setup or hold times are violated. In most
cases, the flip-flop will either react to the input or remain in its
current state, both of which are stable results. The flip-flop
can also reach an "in-between" condition called the metastable state, which is stable only if there.is no noise in the system
and the flip-flop is perfectly balanced. This metastable condi-

Metastability Characteristics
SYMBOL

tion lasts until the flip-flop falls into one of its two stable
states, which can take longer than the normal response time.
The PAL20D Series exhibits better metastability characteristics than most other registered devices. It is less likely to enter
the metastable state and recovers faster to a stable state. As
a result, the PAl20D Series can make an excellent synchronizer circuit, and the metastability characteristics have been
specified for designs in which the setup and hold times may
not always be met.

Over Operating Conditions

TEST
CONDITIONS

PARAMETER

P

Poisson process rate

k

MTBF constant

tMET

Minimum recovery time in asynchronous mode

MTBF = 10 years
fd = (1/3)f d = 3

fMET

Maximum frequency in asynchronous mode

MTBF = 10 years
fd = (1/3)f d = 3

Definition of Variables
MTBF (Mean Time Between Failures): the average time
between metastable occurrences that cause a violation of the
device specifications. Metastability characteristics are. calculated at an arbitrary MTBF of 10 years for the convenience of
the user.
p (Poisson process rate): experimentally calculated factor
which determines the slope of the curve of probability of
failure.
k (MTBF constant): experimentally calculated factor which
determines the magnitude of the curve of probability of failure.
tsu (setup time): the specified minimum time interval allowed
between the application of a data signal at a specified device
input pin (pin 9 on the device under te!!t) and a subsequent
clock transition. For the PAl20D Series, tsu is 10 nanoseconds.
tClK (clock to output time): the specified maximum time
interval between a clock transition and the availability of valid
signals at an output pin. For the PAl20D Series, tClK is 8
nanoseconds.
fMAX (maximum frequency): specified maximum frequency
for the device under test. Calculated as 1I (tsu + tClK). For
the PAl20D Series, this calculates to 55.5 Megahertz.
f(clock frequency): actual clock frequency for the device
under test.
f d (data frequency): actual data frequency for a specified
input to the device under test.
d (data ratiO): the ratio of the clock frequency to the data
frequency (f/fd).
t(tlme delay): the additional time allowed per period beyond
that required by the specifications. t is the actual time between
clock transitions beyond the required period of (tsu +tClK).

COMMERCIAL
UNIT
MIN

TYP

0.85

1.05

21

MAX
ns- l

0.8

1.0

/.IS-l

20

30

ns

26

MHz

tMET (metastability recovery time): minimum t required to
guarantee recovery from metastability, with specified test
conditions.
fMET (metastability frequency): maximum f clock frequency
to limit metastability failures, with specified test conditions.

Metastability Equations
MTBF = k (d/3) (1/1)2 e(p/f)
fMAX = 1/(tsu + tClK)
f = 1/(tsu + tClK + t)
f
d (fd)

=

Metastability vs. Clock Frequency
10 YEARS 108

,.'
1 DAY

..
c

z

0

u
w

'(I

,.'
'00

0.1"0

;

10- 2

10-~'::,O::-0---:!lIS::::0--=-1I!;:40,...---:'+-/3.,-0------:-:!1/20
11f-MHz-1

"Normalized to d = 3; multiply by 3/d for other data frequencies.

MonoIithicW Memories

2-31

Medium 2()DSerin
16.L8D,1!6R8D, 16RaD. 16R4D

Metastability Te$t Circuit

Metastability Waveforms

Metastability Test. PatternJ=lIe
cHIp· Metastabil1ty
Test PAL16R4
,
. ' - " , '
CLOCK .,RESET SYNC~OJJE NC NCNe NC NC III g~D
IOE'N'C,NC IERllOR IS IA IQ'NC NC VCC '. "
.",

~

. '

.'

'

,

"

,

EQUATIONS
Q

~~/Q* ~YNC__MdOE!T9GGi.E ~~#:~(),ii~bs

A

:=

+

:0=

lHOI.JJ' A'(IF ,NOT ;ERROR),
lTOGGLE A (IF NOT ERROR)"
;SETA IF'ERROR

A*/Q

+ IA*
+

B

Ilf.Pt1T (TtS'J;S f!1AX)
O*/SYNC_MOOE, ,l,rOGGLE ASYNCliRONOUS IN:PUT (TESTS M,ETA;)
Q

ERROR
B*/Q* IERROR

+ IB*,Q* I;E~OR
ERROR :- IA*/B
+ ,.A* ,B
'+, RESE'J;

L,'
.,

;HOW B IF ~.9T ERROR, OR:~SET
;T,OGGLE B IF NOT ERROR,"OR .RESET ,
~"',C
:';<~.'.:
" . ,,:'. ":;.
)

_,;

,

",..;',

Medium 20 Serie.
16L8 Logic Diagram

16L8
• 1 2 J

.1 • J

1117''''

12111415

•• 1111

,u'2In

Zl21DD

UIIIU'

~

I

••
••

4

I

2'

"

..

...

11

....' I - - -

"-----t

••
"

~.......

~

"
II
II

18

14,
I.

----...

...'

3

,
n

..
\I
I.

'
,

.••
"

.... ::

~"""':'

,

'

"

,

J'--'-

,

..,:...;.;.

33

,

...."

.

7

,

~

I.

"

'",

..~~

41

,S

','

'

....
.'
...."

,

'

"

:,'

.
.

"

i',

I:

I'

,

...,

,
"

I,

'f

"

...

'/;,

f

IC',

' <_.,,'

,11

,/J"":'~"

:

",

" " ' i , '•

'";:.t"':""
'.,~,,'

:
<:-

II
II
"

'"

,

It

'

:~:,; '):

, }i:J

13,

'""'c

"

, ,I"

II

...

"

,....,...~,: ..f..:,

"U:"

t

,

....~

"'",,

"

"

"r

,;

II

i

:

"

12

I

.........

,

"

......••

~

'

,

i"

tIi

......... ~"'''''
"
,..:;...

at"

....

J.

:'

M

•

"~ -:,'

~

.
.. :
."

"

I.

:

~

II
It
It
10

..

,

,

II

i

17

f0- ........, ~"

II
Il
II

....

•

"

, J

\I

"

'i
, .".

'.

,

i

""", ":'",

,"': ..... ,.
,',

',,",

11

'i',

Medium 20 Series
16R8Logic Diagram

,

16R8

....

0123

4511

.9M"

1213MIS

1&171'"

~rinn

~HD27

HHU~

•
I

2
1

:D]~

""'\.

,•
•
Lb••
""
.""
1

3

~

....

./

"

..

....

---t

""
,."
18

"

./

21
22

21

...

4

:D]

~

~

~

~

~

~

~

24

"'"

.

"

21

211

5

""

...

....
32
33
34

6

",.
"
"

.

"

31

...
....

.
...."
.

~

4Z

"

43

,/

"

, ...

....
....

...

~

50

"

""
"

54

55

.....

........
8

...

....

~

~
~

~

~

56

.."
"

~~

51

,

•

j

""
0123

2-34

.5.7

• ''In

12131415

11111111

20212223

Monolithic

24ZUS2J

inU03'

W Memories

"
""

~~

Medium 20 Series
16R6 Logic Diagram

16R6
1

, o,
,,
••
•,

2 3

4 S , 1

• , 1011

12131415

'6111819

202-12223

24252621

2.Hl031

1

~

1

~

1

....

Lb:=:
••

.r - -

"

...

""
"

./

..

"'"
""
""
"
""

Ol

~

./

p

..

~

..

""

5

~~

IS

11

•

;;ar--~

~

11

3

19

""
""
""

'"
....
~

"..
""
"
""

~

t;J..

16

Q

15

~

l2

. ...
~

p

J

..
p

'"
....

...."
..."
"

,
./

....

...

~

so
51

./
""""

"55"
54

e

....

....

.,

,
56

.

.."
II

...

...

~

Q "
rvv-

U

~

>-t1

"
59
so

9

fUl

~

=---t

.~

01'21

4

&.,

,

8.'011

t2131415

llUll11

20212223

ZU5l121

12

L<\,....!!
~

21213031

Monolithic WMemorles

2-35

Medium 20 Series
16R4 Logic Diagram

16R4
I
Oil J

4S61

"1011

lZ13t4H1

16111'19

20212223

242U621

21293031

•,

J

1

·••
1

7

...s - -

.

3--t~

·""•

r-d

10

.
13

---.
3

..

I.

.....

"

18

A

to

"to
18

"

"

./

21

"

21

4

.....

...

""
""
"

"

28

3G
31

5

..

~

JIIO

...
~

"
""

~~

tul

II

,

..

~

"'

38
37
38

"

A

.
......
..

~

fUl

41

42

1

...

.

"'

./

"

...,

..
..

r-J

II
51
12
53

I

....

~

~
r-;J.

15

rvoQ14

~

13

...

.~

II

~

...,"
II
II

12
II

t ..
""-1
• 1 2:1

2-36

'5' 7

. . . . 11

12131411

llnlll.

HZlUZl

ZUS2I21

llZ.lOll

Monolithic WMemOrieS

....~t---

12

~

Medium20PA Series

16P8A, 16RP8A, 16RP6A, 16RP4A

Medium 20PA Series
OUTPUTS

ARRAY INPUTS
PAL16P8A
PAL16RP8A
PAL16RP6A
PAL16RP4A

tpD

.

COMBINATORIAL

REGISTERED

(n5)

8
0
6
4

0
8
2
4

25/30
25/30
25/30

16
16
16
16

25/30

Icc
(mA)

180
180
180
180

• 25ns active low, 30ns active high

Description

Preload and Power-up Reset

The Medium 20PA Series is equivalent to the Medium 20
Series, with the addition of programmable polarity. With programmable polarity unused, these devices are equivalent to
the Medium 20A Series.

Each device also offers register preloac;l for device testability.
The registers can be preloaded from the outputs by~ using
supervoltages (see waveforms at end of section) in order to
simplify functional testing. This series also. offers Power-up
Reset, whereby the registers power up to a logic LOW, setting
the active-low outputs to a logic HIGH.

Polarity
Eacl) of these devices offers programmable polarity on each
output. If the polarity fuse is unused, the output is active low. If
the .polarity fuse is programmed,the output is inverted to
active high.

Performance
Performance varies according to the use of the programmable
polarity. Active low outputs have a tpd of 25ns, while active
high outputs have a tpd of 30ns due to the extra inversion. All
devices consume 180mA maximum ICC.

Monolithic WMemories

Medium 20PASeries

16P8A, 16RP8A, 16RP6A, 16RP4A
DIP Pinouts
16P8A

16RP6A

16RPSA

16RP4A

PLCC. Pinouts
16PSA

18RPSA

16RP4A

2·38

Monolithic

IFJJI Memories

16RP6A

Medium 20PA Series
16P8A, 16RP8A, 16RP6A, 16RP4A
Operating Conditions
COMMERCIAL 1
SYMBOL

UNIT

PARAMETER
MIN

Vcc

4.75

Supply voltage

t,.

Width of clock

tsu

Setup time from input
or feedback to clock

I··. 5

Low

20

14

High

10

6

16RP8A
16RP6A
16RP4A

Polarity fuse intact

25

15

Polarity fuse blown

30

20
-10

MAX

5.25

V
ns

ns

th

Hold time

0

TA

Operating free-air temperature

0

Electrical Characteristics

TYP

ns
75

·C

Over Operating Conditions

COMMERCIAL
SYMBOL

PARAMETER

TEST CONDITION
MIN

Low-level input voltage

VIH 2

High-level input voltage

VIC

Input clamp voltage

Vee = MIN

II = -18mA

-0.8

-1.5

V

IlL 3

Low-level input current

Vee = MAX

VI = 0.4V

-0.02

-0.25

mA

IIH 3

High-level input current

Vee = MAX

VI = 2.4V

25

pA

II

Maximum input· current

Vee'" MAX

VI = 5.5V

1

mA

VOL

Low-level output voltage

Vee = MIN

IOL = 24mA

VOH

High-level output voltage

Vee = MIN

10H = -3.2mA

IOZL 3
IOZH 3

3.
4.

UNIT
MAX

VIL 2

1-'---

1.
2.

TVP

Off-state output current

0.8

V

2

Vee = MAX

IOS4

Output short-circuit current

Vee = 5V

lee

Supply current

Vee

I
I

0.3
2.4

V

0.5

2.8

V
V

Va = O.4V

-100

pA

Va =2.4V

100

pA

-70

-130

mA

120

180

mA

Va = OV

= MAX

-30

The PAL20PA Series is designed to operate over the full military operating conditions. For availability and specifications"contact Monolithic Memories.
These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and/or tester noise. Do not attempt to test
these values without suitable equipment.
110 pin leakage is the worst case of I,l and 10Zl (or lie and 10ZH).
No more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

Monolithic WMemorles

2-39

Medium 20PA Series
16P8A, 16RP8A, 16RP6A, 16RP4A
Switching Characteristics
SYMBOL

tpo

Over Operating Conditions

TEST
CONDITIONS

PARAMETER

Input or feedback to
output 16P8A,16RP6A,
.16RP4A

COMMERCIAL
UNIT
MIN

TYP

MAX

Polarity fuse intact

15

25

Polarity fuse blown

20

30

10

15

ns

10

20

ns

11

20

ns

10

25

ns

13

25

ns

ns

icLK

Clock to output or feedback

tpzx

Pin 1.1 to output enable except 16P8A

R1

tpxz

Pin 11 to output disable except 16P8A

R2

tpzx

Input to output enable

16RP6A, 16RP4A, and
16P8A

tpxz

Input to output disable

16RP6A, 16RP4A, and
16P8A

f MAX

Maximum frequency
16RP8A,16RP6A,
16RP4A

= 200n
= 390Kn

...

Polarity fuse intact

28.5

40

Polarity fuse blown

25

33

MHz

Monolithic

W Memories

Medium 20PA Series
16P8A Logic Diagram

16P8A
oI

2 3

.. 5 8 7

-allIDII

12131415

161718111

20212223

24252827

28293031

0
I
2
3
4

.,~U

s

I
7

2

1....

19

...

...

~

I
9
10

.,~U

1....

"'"~L>

1

\I

12
13
14'
1&

18

3 ..

...

I.
17
18
19
!O
21
22
23

......

17

....

4

24
25
28
27
28

""~L.)

29
30
31

J_
....

16

S
~

32
33
34

33
36
37

.J~L>

38
38

IS

j....

14

....

6 ..

-

40
41

.
42
43

"'.J~U

46

48

47

7

J

.

'"

48

J1>o---J
.

49
10

51·

st

53

54
55

8
51
&7

51

11\

60

.,~U

II
112
13
..

9

...

1

13

12

.......

11

~

0123

4561

811.11

1213141$

16'11181920212223

24ts2627

28283031

Monolithic WMemories

2-41

Medium 20PA Series
16RP8ALogic. Diagram

16RP8A

....

I ....

•

DI2a

• 5• 7

• liD 11

12131416

11S171.il 202U223 2U52U7

28213031

I
2
3

4
5

nl.l
n
n

~L>...

•
7

2 ....

.......
I
8
10

.."
12
13

D

Q

is

~L>...

15

3 ..

..
18
17

""
----, -'

18
20
21
22
23

~L>-

....

4

..

19

....

Q ....

18

~
....

17

24

21

""
/~L>-

27

21
28

30
31

...

5--

.
.
32
34
35

fa
U

~

15

~

14

~

SJ.
......

~

J~fa

SJ.
....

12

~Lr

37
31
31

...

6
411

..

~~

42
43

./ ~L>-

45
48
47

...

1
r

....-

48

•
10

51
Ii2

2~#L.>-

53
54

115

B

n

81
57
81

..

&I

10
12

13

....

.A..

....

...
01 23

2-42

....

I

..

t

=tt.~
....

45.7

,.10 11

12131415 l1U1811

20212223 24252627

282931131

MonolilhicW Memories

II

Medium 20PA Series
16RP6A Logic Diagram

16RP6A

' ....
....

01 !S

4

t. 7

1"011 11111415

11171111

'!'21ZZ,:, 2421i1lZ7 11111111

0

'"'-'

I

--:l

Z

3
4
5

....

•
7

2.."
~

~U

.

II

....

J

I

1
10
II

I--J
:=:; ./ ~U-

II

13
14
15

...

3
II
17
II

~-~L>-

11

20
21

zz

23

....

4 ...

~~

~

0......

17

~

0

16

24

25

~i-.

II'
Z7

!-./~L>-

28
II
30

..

31

5
31
33

Hi-.

34
3Ii

,...-,

38
37

38
311

....

6

. ~

~L>-

...

0 ...

15

40
41

...
42
43

~

~~~U-

45
47

....

7

..

"

ID
51
82

r--~
r-:

SlI

54
16

8 ..
II
51
II

,

iii

10
II
82
fl3
'.'

e ..
aI

Z3

.. 5 • 1

• liD 11

12131415 .1171811

ZOtl2223 242&2121 28213031

MonO/ithif:W Memories

~

pttl
- i j

...

~

~~

~
...

t=JJ....

13

I~

12

I~
....

2-43

Medium 20PA Series
16RP4ALogic Diagram

16RP4A
I

....
01 23

4 II 1

1110

n

12131415

1117111' 111212213 14aZUl 212131131

--'

..,....., .......
--'I

~L>

l.-.,

1
'iB_ _~
"
I
~

~

11
II
13

>----i ~

14
1&

~l..)

18

JI'"

4 ..

5 ..

6 ...

14

7 ..

12

• I 23

• S' 7

.11011

1213.41& 11171811 20212223 24212127 28213031

MonoIithlcWMem",./es

Large 20 Arithmetic Series

16X4, 16A4

Large 20 Arithmetic Series
OUTPUTS
PRODUCT TERMS

ARRAY INPUTS

PAL16X4
PAL16A4

COMBINATORIAL

REGISTERED

4
4

4
4

16
16

Description
The PAL16X4 and PAL16A4 have arithmetic gated feedback.
These are specialized devices for arithmetic applications.

Arithmetic Gated Feedback
The arithmetic functions (add, subtract, greater than, and less
than) are implemented by addition of gated feedback to the
features of the XOR PAL device. The XOR at the input of the
D-type flip-flop allowscarrys from previous operations to be

64
74

XORed with two variable sums generated by the PAL device
array. The flip-flop Q output is fed back to be gated with input
terms A (Figure 13). This gated feedback provides anyone of
the sixteen· possible Boolean combinations which are mapped
in the Karnaugh map (Figure 14). Figure 15 shows how the
PAL device array can be progr~mmed to perform these
sixteen operations. These features provide for versatile operations on two variables and facilitate the parallel generation of
carrys necessary for fast arithmetic operations.

INPUTS. FEEDBACK AND 1/0

.-.

;:::

B

-

T

~

CLOCK

)0-

~

A

l

Figure 13

MonoIltll;cUJ1Memor/e.

2-45

Large 20 Arithmetic, Series

16X4, 16A4

A--~------.---~~---.

B---+~--~r----rr---.

i':f'

r.,~~

'~~r.,-

:r., • •~
~

-x

xx

x-

A+a

A

A+8

}------A:+B
r--7---B

l-----AoB
-x

A+B

A:+:B

AoB

B
r-,----A:+:B

xx

A

Aoa

0

AoB

x-

A+jj

a

Aojj

A:o:B

\-----A+B

\-----A.jj

Figure 14

\-----AoB

}-----Aojj
}-----l!
)----A+l!
A+B

(AB)

A+S
(AB)

'i+e.
(A B)

Figure 15

2-46

MonolithlcWMemoriss

Larg. 20. Arithmetic Series
16X4, 16A4

DIP Pinouts
16X4

16A4

PLCC Pinouts
18A4

18X4

c000560t.j

MonoIithlcW Memo,.ie.'

2-47

Large 20 Arithmetic 5er.ies

16X4, 16A4

Operating Conditions
MILITARY
SYMBOL

UNIT
MIN

Vee

COMMERCIAL

PARAMETER

Supply voltage

I Low
I High

UP

MAX

5.5

MIN

UP

MAX

5.25

4.5

5

4.75

5

25

10

25

10

25

10

25

10

tw

Width of clock

tsu

Set up time from input or feedback to dock

55

30

45

30

th

Hold time

0

-15

0

-15

TA

Operating free-air temperature

Te

Operating case temperature

....

..

-55

V
ns
ns
ns

0

75

125

°C
°C

Electrical Characteristics
SYMBOL

PARAMETER

Vil l
VIH 1

High-level input voltage

VIC

Input clamp voltage

IIl 2

Low-level input current

2

UP

MAX

0.8
2

.

UNIT

V
V

Vee = MIN

11 = -18mA

-0.8

-1.5

V

Vee = MAX

VI = O.4V

-0.02

-0.25

mA

High-level input current

Vee = MAX

V,=2.4V

25

/lA

Maximum input current

Vee = MAX

VI = 5.5V

1

mA

Val

Low-level output voltage

Vee = MIN

VOH

High-level oiJtput voltage

IOZl 2

Off-state output current

IOZH2

.

Vee = MIN

Output short-circuit current

Vee = 5V

Icc

Supply current

Vee = MAX

SYMBOL

Mil

10l = 12mA

Com

IOl=24mA

Mil

10l= -2mA

Com

10l = -3.2mA
Va = O.4V

Vee = MAX

IOS3

Switching Characteristics

2.
3.

MIN

II

IIH

1.

TEST CONDITIONS

Low-level input voltage

0.3

2.4

0.5

2.8

V
-100

...

V

jJ.A

100

jJ.A

-70

-130

mA

16X4

160

225

16A4

170

240

Va = 2.4\1

-30

Va = OV

mA

Over Operating Conditions

PARAMETER

TEST
CONDITIONS

MILITARY

COMMERCIAL
UNIT

MIN

TYP

MAX

MIN

TYP

MAX

tpD

Input or feedback to output

30

45

30

40

telK

Clock to output or feedback

15

25

15

25

ns

tpzx

Pih 11 to output enab.le

15

25

15

25

ns

tpxz

Pin 11 to output disable

15

25

15

25

ns

tpzx

Input to output enable

30

45

30

40

ns

tpxz

Input to output disable

30

45

30

40

ns

f MAX

Maximum frequency

Rl = 200n
R2 = 390n

12

22

14

22

ns

MHz

These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and/ or tester noise. Do not attempt to test
these values without suitable equipment.
I/O pin leakage is the worst case of IlL and IOZl (or 'IH and 'OZH)'
No more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

2-48

Mono/ithlcWMemories

Large 20 Arithmetic Series
16X4 Logic Diagram

16X4
I

,

o1

2 3

4 S 6 1

1"011

1213141S

16111.~

~~un

NHH21

H3~31

,
•,
,

~I

I

3

2

1

...

.r----'

••

r

r-J
~;J

10
11

"
13
t4

3

"

...

...

4

1
~

14

--'"""

.

1r

;}I=>

~~

~I=>

~

~

""
"
""
"

,

-

"

33

=

37

31
It

..

~I=>

6

....

I
[t::!!.
~

..

.....

;::::;

-

41

I

1

t

[ t::!Io;
~

...
so

""53
"

.

9

...

..

II
\1
II

.."

""

rb4 ~
rj>

Q

~t6
. 'J

41

""

....

~
.'

,

"",.

8

18

"11

""
""
""

[ti

19

Q....

,0

..

~b-J~
~

13

',,. I

~Db--J

53

A

-

r

Monolithic WM8mCJries

12

·1>

11

Large 20 Arithmetic Series
16A4 Logic Diagram

16A4

2

1113

.,"

.,.111

taUMt,

U11""

aHUB

KHan • • • ~

• 1 2 I

.. I • 1

......

'U3M1S

1117""

2U'UD

HII2IO

..

.••
.""
11

----.
3

..
.

"

II
17

."
II

."
21

•T

..
."

I

II
II
30
II

5

1I

--"
"
"

.
.
.

17
II

6

I

m_ ...
.
...."

•7

,

tI

- .....
.,"
..
. .
u

I

..

"--t

. ....

•"
••

II
II
II

• • • ,.

MonolllhlcW Memories

Large 20RA Series
16RA8

Large 20RA (PAL 16RA8)
Description

Programmable Polarity

The PAL16RA8 is a 20-pin registered asynchronous PAL
device. It is a 20-pin version of the original asynchronous PAL
device, the PAL20RA to. This versatile device features programmable clock, enable, set, and reset, all of which can
operate asynchronously to other flip-flops in the same device.
It also has individual flop-flop bypass, allowing this one device
to provide any combination of registered and combinatorial
outputs.

Programmable Clock
The clock input to each flip-flop comes from the programmable array, allowing the flip-flops to be clocked independently if
desired.

Programmable Set and Reset
Each flip-flop has a product line for asynchronous set and one
product for asynchronous reset. If the chosen product line is.
high, the flip-flop will set (become a logic HIGH), or reset
(become a logic LOW). The sense of the output pin is inverted
if the output is active low.

Each flip-flop has individually programmable polarity. The
unprogrammed state is active low.

Programmable Flip-flop Bypass
If both the set and reset product lines are high, the flip-flop is
bypassed and the output becomes combinatorial. Thus each
output can be configured to be registered or combinatorial.

Programmable and Hard-Wired
Three-State Outputs
The PAL 16RA8 provides a product term dedicated to output
control. There is also an output control pin (pin 11). The
output is enabled if both the output control pin is low and the
output control product term is high. If the output control pin is
high all outputs will be disabled. If an output control product
term is low, then that output will be disabled.

Register Preload and Power-up Reset
Each device also offers register preload for device testability.
The registers can be preloaded from the outputs by using TTL
level Signals in order to simplify functional testing. This series
also offers Power-up Reset, whereby the registers power up to
a logic LOW, setting the active-low outputs to a logic HIGH.

MonOlithic WMemories

2-51

--...

~

-~

...

-- - - - -

Large 20RA Series
16RA8

DIP Pinout

16RA8

Pi:
10
11

12

13
14
15

16
17

GND

PLCC Pinout
18RA8

3

2-52

2

1

19

Monolithic WMemories

Large 20RA Series
16RA8

Operating Conditions
COMMERCIAL!
SYMBOL

UNIT

PARAMETER
MIN

V

4.75

5

Iw

20

13

ns

tIN!'

Preload pulse width

35

15

ns

tsu

Setup time for input or feedback to clock

20

10

ns

tsup

Preload setup time

25

5

ns

Hold time

10

-2

It,

0

-6

t hP

Preload hold time

25

TA

Operating free-air temperature

0

Te

Operating case temperature

1

Polarity fuse intact

I. Polarity fuse blown

ns
!

ns

5
75

·C
·C

Over Operating Conditions

PARAMETER

TEST CONDITION

VIl 2
V IH 2

High-level input voltage

VIC

Input clamp voltage

Vee

IIl 3

Low-level input current

Vee

IIH 3

High-level input current

Vee

II

Maximum. input current

Vee

VOL
VOH

Low-level output voltage

Vee

High-level output voltage

Vee

IOZ3

Off-state output current

Vee = MAX

105 4

Output short-circuit current

Vee = 5V

Icc

Supply current

Vee

MIN

TYP

Low-level input voltage

Switching Characteristics

MAX
0.8

= MIN
= MAX
= MAX
= MAX
= MIN
= MIN

UNIT
V
V

2
11 = -18mA

-0.8

-1.5

V

= O.4V
VI = 2.4V
VI = 5.5V
10l = 8mA
10H = -3.2mA
Vo = 2.4V1V0 = O.4V
Vo = OV

-0.02

-0.25

mA

VI

0.3
2.4
-30

25

p.A

1

mA

0.5

V

100

p.A

V

2.8

-100

= MAX

-70

-130

mA

135

170

mA

Over Operating Conditions

TEST
CONDITIONS

PARAMETER

SYMBOL

4.

5.25

Supply voltage
Width of clock

SYMB.OL

3.

MAX

Vee

Electrical Characteristics

1.
2.

TYP

tpo

Input or feedback to output

COMMERCIAL
UNIT
MIN

TYP

MAX

1 Polarity fuse intact

20

30

I Polarity fuse blown

25

35

ns

17

ao

ns

22

35

ns

Rt = 560Q

27

40

ns

R2 = 1.lKQ

10

20

ns

Pin 11 to o\ltpul disable

Hi

20

ns

tpzx

Input to output enable

18

30

ns

tpxz

Input to output disable

15

30

ns

f MAX

Maximum frequency

telK

Clock to output or feedback

Is

Input to asynchronous set

tR

Input to asynchronous reset

tpzx

Pin 11 to output enable

tpxz

10

20

.35

MHz

The PAL20RA Series is designed to operate over the full military op~rating conditions. For availability ~nd speqifications, contact Monolithic Memories.
These are absolute voltages with respect to the ground pin on the. device and include all overshoots due to- system and/of-tester noise. Do not attempt to test
these values without suitable equipment.
1/0 pin leakage is the worst case of I'L and 10Zl (or I'H and lazH)'
No more than one output should be shorted at a time and duration of the short Circuit should not exoeed one seoond.

Monolithic

W Memories

2·53

~

Large 20RA Series
16RA8 Logic Diagram

16RA8
1
ell 3

Itl'1'

.. 5,6 J

12131415

KI71'"

Hz,un

MH~21

HHDll

•,

,

I

3

,•

•,

...

...

Lb
••
""..
10

~
~

L

"""

~

L"
.....

.....

[Jl

./

15

....

..

---t
r

""
11

"

"
"
"
20

./

12

!........t...

"'"

..

24

~~

L.......

"'"

11

3

~~

./

n

"

",.
21

5

..

30
31

.c:

~

.

32

,."
"
,."

"

31

6

7

....
..

'---Ir

a

31

...

...
...""••
"

"

./

...

...

"'"

50
51
52

•

.

"'"

.../

.

"

54

...
"",

so

"..

....."

"'"

51

9

..

./

...

'--I

...
01 Z I

2·54

.. i 67

• lIon

12131415

111711't 20212223

"""Ithlc

24252n7

2UUUl

W Memories

"""

~

.

~

~

~

~
.....

~~

L-

•
•
.L

....

-

.....

-

'>

"
"

.... -

,.

-Q-l

22

21

4

-

"

20

5

~

"
"

19

"'1...r

6

"

-O-L

.....

-

....

.....
to<

-

.

..n.

"

.... -

..

.......

....

--

"
"

....

.....

-

..

18

7

J
....-

17

8

9

IS

16

15

10

II

e

123

..

14

./"

~
1811

""

""

MonolIthic WMemories

""

13

lil1l131;

2-59

Small 24 Series
14L8 Logic Diagram

14L8

1

2

.....,...

o

1

2 l

4

~

.,

.,

1611

2021

""

""

~

~

--

..

23

......

-t"S---J .

Of
11

3

-......

"
"
4

,.
"

~

-~

""'-

2•

21

20

~

II

6

-

-......

"

I.

~

..

--

-

18

J

7

--

...

-o-L.

17

8

- --

56

"

•

16

----t~

.
.."

......

-M-j-

-

"

10

~

~

"

~
0'

2-60

2 1

.!I"

••

Ill)

16 U

2021

2.25

""

Monolithic WMemorles

n 13K 15

36

nllll

"

14

13

Small 24 Seri••
18L8 Logic Diagram

•• Z I

.. , . 1

• • ,111

1213

...,

".

16L6

..

2121.31

DUMJi

.J1MJI

23

22

Small 24Serie.
18L4. Logic Diagram

18L4
012 1

•

s .. ,

a

9. '\111

1211141$

1&11

~

""

I

I
2

"""'. .,......

3

23

...

~

4

=-=:J:l

22

21

L

"

"
"",.

20

"

~

.......

,.""
"
..,"
"

7

:ill......

R-l-.

....

-

so

"
""

8

1C:

~

1C:

I

17

16

14

13

...

---I~

o ,

2·62

18

15

~~

11

19

2 3

•

S .. 1

•

t 1011

1213 M IS

II 11

.."

Monolithic WMemories

Small 24 Series
20L2 Logic Diagram

20L2
0123

'511

'11111

121114ts

16171"1

20n22Zl

NZS21Zl

U ZllO 31

D»MJ5

I

~

Jlll3lll

I

~

3

23

...

22

4

A

5

21

20

"
""

}--'

19

35

"
""

r--

..

6

.....

.

18

4J

r-

.."

"
.2-

.A

,

.

8
----!

9

17

16

i
II
II

..

I

I
A

1S

!i
I
10

II,II

1~

.~

"

,
D 1

2:,

..

$

•

1

•

t 1t 11

n

I'M 1S

11 11 III,

ZO 21 U

n

24 25 2t 27

ZI ZlJO 31

,ll 33 M 3i

MonoillhicWMemorles

13

31 3131,31

2-63

Small 24 Serle.
20C 1 Logic Diagram

o
1

I

1 J

,,$'

20C1
7

•

t 1011

12 IS 14·15

11 11 I'

,t

zo

21 II 23

24 H tI U

:rt 21 31 31

3Z 13 M lS

'31 11 3t 31

.......

~

23

3

22

...

4

....
....

21

~

....

20

,......,

""
"

""'>-

""
"
""

~

6

J

...
.,
.
...

~

.l..

19
18

,......,

42

7

1~
,......,

"

17

----t

~

8

16

----t

....

9

10

~

....

15

.....

14

.
.<

II

....
o

I

1 1

,,$

Ii 1

•

t 10

n

11 13 '4 IS'S 11 .. 11

20 :1 U 2l

24 2S H 27

21 2. 10 Jl

l2:n l4 H

MonolithIc IHIFJIMemories

3& 31 31 It

13

Small 24A Decoder Series
6L16A, 8L14A

Small 24A Decoder Series

PAL6L16A
PAL8L14A

INPUTS

OUTPUTS

6
8

16
14

(ns)

Icc
(mA)

25
25

90
90

tpD

Description

Performance

The Small 24A Decoder Series provides a wide number of
outputs, especially useful in decoding applications. These two
parts implement simple combinatorial logic.

These devices offer 25ns speed at only 90mA supply current.

MonolithIC

IFJJI Memo,.ies

2-65

Small 24'A Decoder Series
6L16A, 8L14'A

DIP Pinouts
8L16A

8L14A

PLCC Pinouts
8L16A

INPUT
AND
LOGIC
ARRAY

2-66

8L14A

o
OUTPUT
CELLS 0

OUTPUT
CELLS

0

o

Small 24A Decoder Series

SLiSA, 8Li4A

Operating Conditions
COMMERCIAL1
SYMBOL

PARAMETER

UNIT
MIN

Vee

Supply voltage

4.75

TA

Operating free-air temperature

0

Electrical Characteristics
SYMBOL

TEST CONDITION

VIL 2

Low-level input voltage

VIH 2

High-level input voltage

Vie

Input clamp voltage

Vee = MIN

r-!',I

Low-level input current

Vee = MAX

IIH

High-level input current

Vee

II

Maximum input current

Vee

VOL

Low-level output voltage

Vee

VOH

High-level output voltage

Vee

IOS3

Output short-circuit current

Vee

lee

Supply current

Vee = MAX

SYMBOL

tpD
1.
2.
3.

MAX

5

5.25

V

25

75

·C

Over Operating Conditions

PARAMETER

Switching Characteristics

TYP

MIN

TYP

MAX
O.B

2

= MAX
= MAX
= MIN
= MIN
= 5V

UNIT
V
V

II = -lBmA

-O.B

-1.5

V

= 0.4V

-0.02

-0.25

mA

VI

VI = 2.4V

= 5.5V
10L = BmA
10H = -3.2mA
Vo = OV
VI

0.3
2.4

2.B

-30

-70

25

J.LA

1

mA

0.5

V
V

-130

mA

90

mA

60

Over Operating Conditions

PARAMETER

Input to output propagation delay

TEST
CONDITIONS

R1 = 560n.
R2 = 1..1Kn.

r-'

COMMERCIAL

MIN

UNIT
TYP

15

MAX
25

ns

The PAL24A Decoder Series is designed to operate over the full military operating conditions. For availability and specifications, contact Monolithic Memories.
These are absolute voltages wfth respect to the ground pin on the device and include an overshoots due to system and/or tester noise. Do not attempt to test
these values without suitable equipment.
No more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

MonoIithlcW Memo,.i••

2-67

Small· 24A Decoder. Series
6L 16A Logic Diagram

6L16A
23

61

89

10 II

1213

I

II

•
•
It

•

..
21

•
II

!...

"
1...

...
II

•

.
17

•
"
"
II

14

II

..

2-.68

Monolithic W.Memorles

Small 24A Decoder Serle.
'8L14ALogic Diagram

.,

8L14A

.,

• I

.. "

••

• I

M"

I

,.

,,'

•

.

I

r

",,'

"

•

,e

"

,,'
"':::.,
,

,"".

..

I:·

.:cc
"

',,/:,
,',""

'

'

';

:

1·:",'

,

I

,:,'

•

.

II

",'
,

..

'

:

"

"

,,:,

I,

,',

I,

r

.

",,>

I

..
•

,

-::
,

•

"

-"-

..
.
,

,

It

.

II

I
'

,"

..

"

,

,

I
It

"

"

",
",

'c.

"

II

"

Medium 24 Serle.
20L8,20R8,20R6,20R4

Medium 24 Series
OUTPUTS
DEDICATED INPUTS
COMBINATORIAL

PAL20L8
PAL20R8
PAL20R6
PAL20R4

12
10
10
10

REGISTERED

8 (6 I/O)
0
21/0
41/0

0
8
6
4

Description
(n8)

Icc
(mA)

25
35
15
25

210
105
210
105

tpD

The Medium 24 Series consists of four devices, each with
twenty array inputs and eight outputs. The devices have either
0, 4, 6, or 8 registered· outputs, with the remaining being
combinatorial. Each of the registered outputs feeds back into
the array, for sequential designs. The combinatorial outputs
also feed back into the array, except for two of the outputs on
the 20L8. This feedback allows the output to also operate as
an input if the output is disabled.

• contact Monolithic Memories for datasheet

Enable

Preload and Power-up Reset

The combinatorial outputs are enabled by a product term. The
registered outputs are enabled by a common enable pin.

The B-2 Series offers register preload for device testability.
The registers can be pre loaded from the outputs by using
supervoltages (see waveforms at end of section) in order to
simplify functional testing. The B-2 Series also offers Powerup Reset, whereby the registers power up to a logic LOW,
setting the active-low outputs to a logic HIGH.

Polarity
All outputs are active low.

Performance

Suffix

A
A-2
B
B-2 •

Several speed/power versions are available:

2-70

Monolithic WMemories

Medium 24 Serle.
20L8, 20R8,20R8, 20R4
CMOS ZPALTM 24 Series
Features/Benefits
• CMOS technology provides zero standby· power· .'
• Lowest poWer 2~-pin PAL® device: family; consul11esonly
3mA/MHz
• 35ns maximum propagation delay
• PrqgrammabJe replacement for CMOS/TTL logic
• Reduces chip count by greater than six to one
• Instant prototyping and easier board layout
.
• HC/HCT compatible for use. in CMOS or'TTL systems
• Offered over:;.both the Commercial and Inc:histrial
temperature ranges
• Low-cost; one-time programmable SKINNYDIP® and PLCC
packages save board. space
•
!

D~$~riptlon

"

, t;'

The CMOS 'ZPAL24' Series offers the first family of PAL
devices with tr\le CMOS' power consumption. Uhder standby
con.dltlons (inputs and clock not changing), the devises, consume a maximumcurrent of 100MA, less than 1%th~t of the
quarter-power' PAL devices. This low power consumption
allows the devices to be powered by a battery almost indefinitely.
While operating; the devices consume additional power only
when the :i!lputs~ •. or clock··QIlang,e. Power consumRtiofl:is
directly proPorti~al to the freq~elicy: of change!! .to theilnputs:
IcC is therefore specified as 3mA 'p~r 1M~ ofop9rliting
frequency; starting from 5mA at 1114Hz. Th\l~the' maximum
currimtat
8114Hz would be 5mA +.7x3mA,
O(26mA
..
.,
;
,
~..,'

The devices have HC and HCT compatible inputs and outputs
for use in CMOS and TTL systems. This feature. allows the
ZPAL circuits' to be used for direct replacement of discrete
CMOS as well as TTL logic.

Areas of' Application
•
•
•
•

Portable computerS
BattetY~op~rated instrumentation

LOW-POWer industrial !;Iquipment
.Stand8rd CMOS/TTLIogic replacement

Featl,lre~~'
ThetMOS ;ZPAL24 Series includes the four standard 24-pin
PAL deilice architectUre$. All four d8v1ces have twenty array
inputs and $ight outputs, with varying numbers of registers:
zero' '(20L8). :four (2084), six (20RI); alid eight (20R8). The
combinatorial outputSOfl' the registered devices, and six of the
outpUts ori th.e 20L8,are I/O pins that can beinpividually
progr'am"l1edas inputs.or outputs. Each output register, a Dtype flip-flop, also feeds back intot,l:ie array, tor implementation of; Synchronous state machine·designs. Registered outputs are enabled byari external input,while the. combinatorial
outputs use a product term to control the enable function.
The. basic PAL device architecture is a programmable AND
array feeding a fixed OR array. The programmable AND array
COnsists of a set of cells similar to, those· used in EPROMs.
Erasable by UV light, the FSlls. can be programmed and
erased;in the factory to en'sure :1.00%, programming and
!\lnctional yieiO~.
. ,.' . ,
.'
Windowed p!i,ckages:will be made available in the future,
allowing erasl;lre,jn till! fiell!, Windowed packages allow easy
pro!olYpe testii!g. and t:econfiguration.

2·71

Medium 24 Series
20L8, 20R8, 20R6, 20R4

DIP Pinouts
20RSAIA-2/B

20LBAIA-2/B

2OR6AIA-2/B

2OR4A1A-2/B

PlCC Pinouts

INPUT

AND
OR
LOGIC

ARRAY

2OR6AlA-2/B

2OR8A1A-2/B

2OLSAlA-2/B

110

INPUT
AND

OUTPUTI/o
CELLS

LOGIC

I/O

ARRAY

OR

REG
OUTPUT REG
CELLS
REG

2OR4A1A-2/B

INPUT
AND

OR
LOGIC

ARRAY

2-72

REG
OUTPUT REG
CELLS
REG

MonoilthlcWMemorles

INPUT

AND
OR
LOGIC

ARRAY

REG
OUTPUT REG
CELLS
REG

Medium 24A Series
20L8A,20R8A,20R6A,20R4A

Operating Conditions
MILITARY
SYMBOL

UNIT
MIN

Supply voltage

Vee

t,.

Width of clock

tsu

Set up time from input or
feedback to clock

TYP

MAX

MIN

5.5

5

4.75

5

7

15

7

High

20

7

15

7

20RSA 20R6A 20R4A

30

15

25

15

-10

0

-10

0
-55

Operating case. temperature

IIl 2

°C
°C

Over Operating Conditions

TEST CONDITIONS

MIN

TYP

MAX
O.S

High-level input voltage
Input clamp voltage

ns

125

PARAMETER

Vie

ns

75

0

Low-level input voltage
..

V
ns

Hold time

SYMBOL

5.25

4.5

Operating free-air temperature

V IL 1

MAX

20

th

Electrical Characteristics

TYP

Low

TA
T6

VIHI

COMMERCIAL

PARAMETER

2

UNIT
V
V

Vee = MIN

11 = -lSmA

-O.S

-1.5

V

Low-level input current

Vee = MAX

VI = 0.4V

~0.02

-0.25

mA

IIH2

High'level input current

Vee = MAX

VI = 2.4V

25

IlA

II

Maximum input current

Vee = MAX

VI" 5.5V

1

mA

VOL

Low-level output voltage

Vee = MIN

VOH

High'level output voltage

IOZl2

Vee = MIN

Off-state output current

Vee = MAX

IOZH2
IOS3.

Output short-circuit current

Vee = 5V

Icc

Supply current

Vee = MAX

Mil

IOl = 12mA

Com

IOl = 24rnA

Mil

IOH = -2rnA

Com

10H = -3.2rnA

0.3

2.4

0.5

2.S

V

V

Vo = 0.4V

-100

Vo = 2.4V

100

IlA
IlA

-90

-130

rnA

160

210

rnA

Vo = OV

~30

1.

These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and/or tester noise. Do not attempt to test

2.

these values without suitable e.quipment.
1/0 pin leakage is the worst case of I'L and

3.

No more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

IOZL

(or

I'H

and

IOZH)·

MonolithlcWMemories

2-73

Medium 24A Series
20L8A, 20R8A, 20R6A, 20R4A

SWI'tCh'mg Characteristics
SYMBOL

Over 0 perat"mg Co ndlt"ons
I

TEST
CONDITIONS

PARAMETER

tpo

Input or
feedback to
output

!eLK

Ciock to output or feedback

tpzx

Pin· 13 to output enable except
20L8A

tpxz

Pin 13 to output disable except
20L8A

tpzx

Input to output
enable

tpxz

.
f MAX

COMMERCIAL

MILITARY

UNIT
MIN

TYP

20R6A 20R4A
20L8A

MAX

T't'P

MAX<

30

15

25

ns

20

HY

15

ns

25

10

20

ns

11

25

11

20

ns·

20R6A 20R4A
20L8A

10

30

10

25

ns

Input to output
disable

20R6A 20R4A
20L8A

13

30

13

25

ns

Maximum
frequency

20R8A 20F16A
20R4A

, ....

15

MIN

10
R1
R2

= 200fl

10

= 390fl

Monolithic

20

W Memories

40

...

28.5

40

MHz

Medium 24A·2 Series
20L8A-2, 20R8A·2, 20R6A.2, 20R4A·2

Operating Conditions
COMMERCIAL I
SYMBOL

UNIT

PARAMETER
MIN

Supply voltage

Vee

TYP

MAX

5.25

4.75

5

Low

25

10

High

25

10

20RSA-2, 20R6A-2, 20R4A-2

tw

Width of clock

tsu

Setup time from input or feedback to clock

35

25

th

Hold time

0

-15

TA

Operating free-air temperature

0

25

Electrical Characteristics
SYMBOL

ns
ns
ns
75

°C

Over Operating Conditions

PARAMETER

VIL 2
V IH 2

High-level input voltage

Vie

Input clamp voltage

IlL 3
IIH 3

TEST CONDITION

MIN

TYP

MAX

O.S

Low-level input voltage
2

UNIT

V
V

Vee = MIN

11 = -lSmA

-O.S

-1.5

V

Low-level input current

Vee = MAX

VI = 0.4V

-0.02

-0.25

mA

High-Ieverinput current

Vee = MAX

VI = 2.4V

25

p.A

1

mA

II

Maximum input current

Vee = MAX

VI = 5.5V

VOL

Low-level output voltage

Vee = MIN

10l = 24mA

VOH

High-level output voltage

Vee = MIN

10H = -3.2mA

3

10Zl
IOZH 3

OIl-state output current

Vee = MAX

105 4

Output short-circuit current

Vee = 5V

lee

Supply current

Vee = MAX

Switching Characteristics
SYMBOL

V

I
I

0.3
2.4

V

-100

p.A

2.S

Vo.= O.4V
-30

V

100

p.A

-70

-130

mA

80

105

mA

Vo = 2.4V
Va =OV

0.5

Over Operating Conditions

TEST
CONDITIONS

PARAMETER

MILITARY

COMMERCIAL
UNIT

MIN

TYP

MAX

MIN

TYP

MAX

tpo

Input or feedback to output
20LSA-2 20R6A-2 20R4A-2

25

50

25

35

ns

telK

Clock to output or feedback
except 20LSA-2

15

25

15

25

ns

tpxz/zx

Pin 13 to output disable/enable
except 20LSA-2

Commercial
RI = 200n

15

25

15

25

ns

tpzx

Input to output enable 20L8A-2
20R6A-2 20R4A-2

R2 = 390n

25

45

25

35

ns

tpxz

Input to output disable 20LSA-2
20R6A-2 20R4A-2

25

45

25

35

ns

f MAX

Maximum frequency 20RSA-2
20R6A-2 20R4A-2

14

19

16

19

MHz

3.

The PAL24A-2 Series"i~ des,igne9 to operate.PYa( the full military operating conditions. For availability and specifications, contact MonQlithic Memories.
These are. absolute voltages '!Vith respect to the ground pin on the device and include all overshoots due to system and/or tester noise. 00 not attempt to test
these values without suitaqle equipment.,
I/O pin leakage is the worst case of IlL and 10Zl (or IIH and 10ZH)·

4.

No more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

1.
2.

Monollthm

W Memories

2-75

Medium 24B Series
20L8B, 20R8B, 20R6B,20R4B

Operating Conditions
COMMERCIAL 1
SYMBOL

UNIT

PARAMETER

Vee

Supply voltage

Iw

Width of clock

I
I

MIN

TYP

MAX

4.75

5

5.25

Low

10

6

High

12

B

20RBB, 20R6B, 20R4B

Is"

Setup time from input or feedback to clock

15

th

Hold time

0

-10

TA

Operating free-air temperature

0

25

Electrical Characteristics

V
ns

10

ns
ns
75

°C

Over Operating Conditions

COMMERCIAL
SYMBOL

TEST CONDITION

PARAMETER

UNIT
MIN

TYP

MAX

VIl 2

Low-level. input voltage

VIH 2

High-level input voltage

Vie

Input clamp voltage

Vee = MIN

'I = -1BmA

-O.B

-1.5

V

IlL 3

Low-level input current

Vcc= MAX

VI = O.4V

-0.02

-0.25

mA

IIH 3

High-level input current

Vec= MAX

VI = 2.4V

25

!lA

II

Maximum input current

Vee = MAX

VI = 5.5V

1

mA

VOL

Low-level outPllt voltage

Vee = MIN

IOl = 24mA

VOH
IOZL 3

High-level output voltage

Vee = MIN

IOH= -3.2mA

O.B

Vee = MAX

IOS4

Output short-circuit current

Vee = 5V

Ice

Supply current

Vee = MAX

Switching Characteristics
SYMBOL

0.3
2.4

0.5

100

!lA
!lA

-70

-130

mA

140

210

mA

-100

Vo= 2.4V
-30

Vo = OV

V
V

2.8

Vo = 0.4V

Off-state output current

IOZH 3

V
V

2

Over Operating Conditions

TEST
CONDITIONS

PARAMETER

COMMERCIAL
UNIT
MIN

TYP

MAX

tpD

Input or feedback to output 20L8B, 20R6B, 20R4B

12

15

tcLK

Clock to output or feedback except 20LBB

8

12

ns

tpzx

Pin 13 to output enable except· 20LBB

10

15

ns

tpxz

Pin 13 to output disable except 20LBB

B

12

ns

tpzx

Input to output enable
20R6B •.. 20R4B. 20LBB

12

1B

ns

tpxz

Input to output disable
20R6B,20R4B, 20LBB

12

15

ns

I Feedback
I No feedback

....

f MAX

Commercial
Rl = 200n
R2 = 390n

Maximum frequency
20RBB, 20R6B, 20R4B

..
mlhtary operating

..
conditions.

40

45

50

MHz

1.

The PAL24B-Senes IS deSigned to operate' over the full

2.

These ars absolute voltages with respect to the ground pin on the device and include alt overshoots due to system and/or' tester noise. Do not attempt to test

3.
4.

these values without -suitable equipment.
110 pin leakage is the worst case of 'iland 10Zl (or IIH and 10ZH).
No more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

2-76

For availability-and

..
specifications,

37

ns

MonolithicWMemories

contact' Monohthlc Memories-,

Medium 24 Series
20L8 Logic Diagram

., • •

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45.7

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M.dlum 24X S.rl••
20LtO,20X10,20X8,20X4

Medium 24X Series
.

OUTPUTS
:

PAL20L10
PAL20X10
PAl20X8
PAL20X4

STANDARD

ARRAY INPUTS

..
20
20
20
20

;

COMBINATORIAL

REGISTERED

10
0

0
10
8
4

2
6

(n8)

Icc
(mA)

50

165

tpD

·SO

so
50

Description

Polarity

The,fAL24X Series offers Exclusive-OR (XOR) gates preceding eacfiregister. The XOR gate has as'its inputs two sums,
eachoi two product terms. The XOR. gate is very efficient. for .
couriting applicEitions."
.

All outputs are active low.

Enable

.

The cOmbinatorial outpUts are enabled bY a "product term. The
registered outputs .are enabled by a common enable pin.

180
180
180

HIGHSPE.ED

(ns)

Icc
(mA)

30
30
30
30

165
180
180
180

tpD

Prel9ad. 811d Power-up Re$et
The 24XASeries offers register pr918~d for device testability.
Theregi~ers can I:!epreloaded ftom the outputs by using
supe~oltag9$ (see waveforms at end of section) in order to
simplify functional testing. The 24XA.§eries also offers Powerup Reset, whereby the registers pPwef up to a logic LOW,
setting the "8cDve-low outputs to a h;)gI6 HIGH:
.

2-81

M.d....m 24X .......
20L 10,/ .20X 10,' 20X8.· 20X4

DIP Pinouts
2OL101A

2OX10/A

20XBlA

2OX4/A

PLCC Pinouts
2OL101A

2OX101A

20XBlA

2OX4IA

ilEG

O~REG
REG

2-82

Medium 24X Series
20L10, 20X10,20Xa, 20X4

Operating Conditions
COMMERCIAL

MILITARY
SY.MBOL

UNIT

PARAMETER
MIN

V6c

Willth of clock

tsu

'Setup time from input or
feedback to clock

High

30

10

25

10

20X10. 20X8. 20X4

60

38

50

38

-15

0

-15

5.5

0

Op.erating case temperatur!l

PARAMETER

·C

MIM

TYP

. MAle
0.8

Low-level input current

IIH2

High-level input current

II

Maximum input current

VOL

Low-level output voltage

Vee -MIN

VOH

High-level output voltage

Vee

Vee

= MIN

Vee = MAX

.

-0.8

-1.5

V

VI = O.4V

-0.02

-0:25

mA

= 2.4V

25

p.A

VI = 5.5V

1

mA

Mil

10L -12mA

Com

10L- 24mA

Mil

10H = -2mA

Com

10H =_3.2mA

IOS3

Output short-circuit current

Vee = 5V

lee.

Supply current

Vee -MAX;

20X10

Ice

SUpply' current

Vee· MAX

2OL19

V

11 = -18mA

VI

..

UNIT·

V

2

IlL 2

IOZH2

ns

·C

.....

TEST C.ONDITIONS

= MIN
Vee = MAX
Vee = MAX
Vee = MAX.

Off-state output current

ns

75

input voltage

. Input clamp voltage

V
ns

125

(Over Operating CondIUon.)

Low~level

104:L2

2.
3.

5
20

TA
To

Vie

1.

4.75

35

0

High--Ievel input voltage

5.25

5

":'55

V IL I

MAX

20

Hold time

VIH I

TYP

40

Operating free-air temperature

Electrical Characteristics

MIN

4.5

th

SYMBOL

MAX

Low

.Supply voltage

1w

TYP

0.3

2.4

0.5

2.8

V

V

Vo = O.4V

-100

j.tA

Vo = 2.4N

100

j.tA

,;,70

-130

mA

120

180

mA

90

165

mA

-30

Vo· OV
20X8 ."

20X4

These are absolut.e voltages with respect to the ground ~in on the devic;e and include all overs.hoots due to sys~em and/or tester noise. Do nOtatlempt to lest
these values without sujtable equipment.
.
110 pin leakage Is tI!e worst case of IlL and lOll (or IIH and IOZH)" .
..
. ".
. .
more than one output ahould be shorted at a ti~e and duration of the short circutt shoull! not exceed on.e second.

""0

Medium 24X Serle.
20L10, 20X10. 20X8. 20X4

SW itching Characteristics
SYMBOL

(0ver Operating Conditions)

TEST
CONDITIONS

PARAMETER

MILITARY

COMMERCIAL
UNIT

MIN

TYP

MAX

MIN

TYP

MAX

tpD

Input or feedback to output
20X8, 20X4, 2011 0

35

60

35

50

ns

tCLK

Clock to output or feedback
except 20L10

20

35

20

30

ns

tpxz/zx

Pin 13 to output disable/enable
except 20L 10

R1 = 200.\1

20

45

20

35

ns

tpzx

Input to output enable except
20X10

R2 = 390.\1

35

55

35

45

ns

tpxz

Input to output disable except
20X10

35

55

35

45

ns

f MAX

Maximum frequency
20X10, 20)(8, 20X4

2-84

10.5

Monolithic

W Memories

16

12.5

16

MHz

Medium 24XA Series
20L10A, 20X10A, 20X8A, 20X4A

Operating Conditions
COMMERCIAL 1
SYMBOL

UNIT

PARAMETER
MIN

Vee

Width of clock

!su

Setup time from input or feedback to
clock

MAX

5.25

4.75

5

Low

25

15

High

15

7

20X10A, 20XSA, 20X4A

30

20

Supply voltage

lw

TYP

th

Hold time

0

-15

TA

Operating free-air temperature

0

25

Electrical Characteristics
SYMBOL

V
ns
ns
ns

75

·C

(Over Operating Conditions)

PARAMETER

VIl 2

Low-level input voltage

V1H 2

High-level input voltage

VIC
IIl 3

Input clamp voltage
Low-level input current

IIH 3

High-level input current

II

TEST CONDITION

MIN

TYP

MAX

O.S

UNIT

V
V

2
-1.5

11 = -lSmA

-O.S

Vee = MAX

VI = 0.4V

-0.02 . -0.25

Vee = MAX

VI = 2.4V

25

p.A

Maximum input current

Vee = MAX

VI = 5.5V

1

mA

VOL

Low-level output voltage

Vee = MIN

IOl = 24mA

VOH

High-level output voltage

Vee = MIN

10H = -3.2mA

Vee = MIN

IOZl 3
IOZH 3

Off-state output current

Vee = MAX

105 4

Output short-circuit current

Vee = 5V

Icc

Supply Current

Vee = MAX

Switching Characteristics

0.3
2.4

-100

Vo = 2.4V
-30

-70

mA

V
V

2.S

Vo = 0.4V

Vo = OV

0.5

V

p.A

100

p.A

-130

mA

20Xl0A,20XSA,20X4A

140

lS0

20L10A

11.5

165

mA

(Over Operating Conditions)

COMMERCIAL
SYMBOL

TEST CONDITIONS

PARAMETER

UNIT
MIN

1.
2.
3.
4.

tpD

Input or feedback to output 20L lOA, 20X8A, and
20X4A

!elK

Clock to output or feedback

tpzx

Pin 13 to output enable except 20L10A

Commercial

tpxz

Pin 13 to output disable except 20L 1OA

tpzx

Input to output enable

20XSA, 20X4A, and
20L10A

tpxz

Input to output disable

20XSA, 20X4A, and
20L10A

f MAX

Maximum frequency

20X10A, 20XSA, and
20X4A

TVP

23

MAX

30

ns

10

15

ns

11

20

ns

R1 = 200.1"2

10

20

ns

R2 =360.1"2

19

30

ns

15

30

ns

22.2

32

MHz

The PAl24XA Series is designed to operate over the full military operating conditions. For availability and specifications, contact Monolithic Memories.
These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and/or tester noise. Do not attempt to test
these values without suitable equipment.
I/O pin leakage is the worst case of III and IOZl (or IIH and IOZH)'
No more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

Monolithic

m

Memories

2·85

Medium 24X Series
20L 10 Logic Diagram

20L10

··,

0121

•

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U 131415

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Medium 24X Series
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12131415

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nUll"

MonoIlth/C·WMemories

14

~

13

~

31U1IlI

2·89

Large 24RS .58rle.
20S10; 20RS10,. 20RS8, 20RS4

Large 24RS Series

.

STANDARD

OUTPUTS

ARRAY INPUTS

.

PAL20S10
PAL20RS10
PAL20RS8
PAL20RS4

20
20
20
20

COMBINATORIAL

REGISTERED

10
0
2
6

0
10
8
4

..

..

..

tpo
(ns)

Icc
(rnA)

35/40

240
240
240
240

35

35/40
35/40

35n5 active low, 40n5 actrve high

Description
The Large 24RS Series offers product term sharing, which
allows up to sixteen product terms to be used at a single
output.

Enable
The combinatorial outputs are enabled by a product term. The
registered outputs are enabled by a common enable pin.

Programmable Polarity
Each flip-flop has individually programmable polarity. The
unprogrammed state is active low.

Product Term Sharing

pair has a total of sixteen product terms; thus, one output can
use zero to sixteen terms while the other has sixteen to zero.
Product terms can only be shared mutually exclusively, If both
outputs need the same term, it must be created twice, once
for each output.

Preload and Power-up Reset
·The 24RS Series offers register preload for device testability.
The registers can be preloaded from the outputs by using
supervoltages (see waveforms at end of section) in order to
simplify functional testing. The 24RS Series also offers Powerup Reset, whereby the registers power up to a logic LOW,
setting the active-low outputs to a logic HIGH.

Product term sharing allows each pair of outputs to share its
product. terms with one output or the. other (not both). Each

2·90

Monolithic WMemor/es·

Large 24RS Series
20S10, 20RS10, 20RS8, 20RS4

DIP Pinouts
2OS10

2ORS10

20RSS

2ORS4

PLCC Pinouts

2ORS4

INPUT
AND
OR
LOGIC

ARRAY

REG

OUTPUT
CELLS REG
REG

Mono/itblcWMemortes

2-91

Large 24RS Serle.
20S10, 20RS10, 20RS8, 20RS4
Operating Conditions
MILITARY
SYMBOL

UNIT
MIN

Vee

TYP

MAX

4.75

5

5.25

MAX

MIN

5.5

5

V

Low

20

10

15

10

High

20

10

15

10

20RS10
20RS8
20RS4

40

25

35

25

ns

Hold time

0

-10

-10

ns

TA

Operating free-air temperature

-55

Te

Operating case temperature

ns

lw

Width of clock

tsu

Setup time from input or .
feedback to clock

th

SYMBOL
V IL 1

0
0

75

·C
·C

125

(Over Operating Conditions)

PARAMETER

TEST CONDITION

MIN

TYP

Low-level input voltage

MAX
0.8

UNIT
V

V IH I

High-level input voltage

Vie

InPllt clamp voltage

Vee = MIN

11 = -18mA

-0.8

-1.5

V

IIl 2

Low-level input· current

Vee=MAX

VI = 0.4V

-0.02

-Q.25

mA

IIH2

High-level input current

Vee = MAX

VI =2.4V

25

/JA.

II

Maximum input current

Vee = MAX

VI = 5.5V

1

mA

VOL

Low-level output voltage

Vee = MIN

VOH

High-level output voltage

IOZl 2

V

2

Vee = MIN

Mil

10L = 12mA

Com

IOL= 24mA

Mil

10H = -2mA

Com

10H =-3.2mA

0.3

2.4

Vee = 5V

lee

Supply current

Vee = MAX

Vo = OV

V

100

Vo = 2.4mA
Output short-circuit current

V

-100

Vee = MAX

108 3

0.5

2.8

Vo = 0.4V
Off-state output current

IOZH2

2.
3.

TYP

4.5

Supply voltage

Electrical Characteristics

1.

COMMERCIAL

PARAMETER

-30

/JA

~.70

-130

mA

175

240

mA

These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system andlor tester noise. Do not attempt to test
these values without suitable eqUipment.
110 pin leakage is the worst case of I,l and IOZl (or I'H and 'OZH).
No more than one output should be shorted at a lime and duration of the short circuit should not exceed one second.

2·92

Monolithic WMemor/es

Large 24RS Serle.
20S10, 20RS10, 20RS8, 20RS4
Switching Characteristics
SYMBOL

tpD

(Over Operating Conditions)

TEST
CONDITIONS

PARAMETER

Input or
feedback to
output 20810,
20R88, 20R84

COMMERCIAL

MILITARY

UNIT
MIN

TYP

MAX

MIN

TYP

MAX

Polarity fuse
intact

25

40

25

35

Polarity fuse
blown

30

45

30

40

12

20

12

17

ns

10

25

10

20

ns

ns

tCLK

Clock to output or feedback

Commercial
R1 = 200n
R2 = 390Kn

tpzx

Pin 13 to output enable except
20810

tpxz

Pin 13 to output disable except
20810

11

25

11

20

ns

tpzx

Input to output
enable

20810, 20R88,
20R84

25

35

25

35

ns

tpzx

Input to output
disable

20810, 20R88,
20RP4

13

30

13

25

ns

f MAX

Maximum
frequency

20R810,
20R88, 20R84

Military
R1 = 390n
R2 = 750n

18

Monolithic WMamoria.·

28

20

28

MHz

Large 24RS Series
20S 1 0 Logic Diagram

20S10
'..J'o.

.....
0

·,,

r-H:>-r- '~J...) .l

·

....

~
I"

A

..••
"
"."

~ :-

IS

"
"""
""

•h

0-

~

rr-

It

,

r=
~

v;>~

~D 1
~

22

21

oJ!!
11

....

..

.,

.."
..

~

.....,
os

Ef

~
-

'-

so

~

~

"

""

54

•
~
•

.....

~

..

""
"."
""
",.
"""
"
.. "

·.

.f?o
~
- T
':"

II
11

•

III

...

••

50

17

T

,

..

.."
so

51

....""
..
"....
II

f--

~

':"

... ""
11"
~ "

10

,."
,."
"
"

"

~

15

012 J

4 Ii I J

• t ton

tz1314U

1117181'

1

~r1i

.-

It

2-94

...
':"

-

20unn

Z4UH27

2U.30JI

U3UU5

31313131

MonolithicWMemories

...J!

Large 24RS Series
20RS10 Logic Diagram

20RS10
• too.,
y

• 1 2I

• t tOil

JI"111111111:!~=>t'~n"=i~fD~:
•

4' I 7

lUI ....

111 1 1

.,UZD

2411

f1

••••

••
"
II

"."

""
""
"n
.
"
II

II

". :: .

,.

.
17

II

It

,.

"iIII

,

~

.......
""".

.
tI

:

•
,,"=

..
II

II

,~.

II
~li

"..

It

""
,.""..
11

'"

11

It

Large 24RS Serie.
20RS8Logic Diagram

20RS8

....

'Jo..

•,
.. r
••

• 1.7

• • II

...... ..,,"

"

,

.tuz.

...

II

•• ,ull

"

>.-\~~

*'

I
I

r~

•

po-

ZI

J

~.

..••

"""
M

'D,'Q

:>.1~

~

~.

""
":"
.."R

·.

C\~

-;J. "
...

° '""J
....
_I

..~

"

r~D

I

......"

~

•..

~n

17

<':

D

"
• •
II

,

,

~

.."
ft

~

tf1

.A

r.J. ..
.~

t:;J.

po-

0'

..
a

...
\I

...
.

"

~~

•
•"
.,••

.
•

•
••"
••
•.
••

.
)--

~

II

••
n

.< ••" .

..

~

"
""
"
.Jf'

.
11
11

'

F1~n
¥~

.

..

-"

,

"

.

D Q

<,'

.

:b~"'''';

r

"' ~

, •

• It 7

.... n

Itll ...

• 1111'1

.....

• • • 11 . • • • • ,.'aIIS

s" ••

*. . . 1
'"

r;;-;
r~

~n
.~
,.,

'".

." "
"

~

~

II

•
•

~

*'

.bn

II

. ; . ==

r.J.... .
t;J.

....

"

CJ... ..

Q...

"

"":f>Ot]

J.

.

..!

~

Large 24RS Series
20RS4 Logic Diagram

'

20RS4

.....
...

,,
,,
••

01 :z3

• 5'7

•

'~Il

nQWl5

dlldl'

mhUD

umav

a •

31

annUl

3i17 •

·

~-

~

·.

....

~

~

••

~~l
:r . .

"

II

·•

.

)n~J

.""
""
"
"'""
""

"

~T>Joo.

h

~-I

"

....

.

"

IS

.""

•
1

l'n
1?l}

"
..""
""
""
"

~

D 0

:>.;~

""
51

r-

0 -;J.....
Ltih

...

.

>.-\,,1
:r . .

..".
II

M

"."
••
..,.

~~
~

11

n

.... "

....

~n

·....

~

-;J.

:r

53

~ "
....

Wh

..

.."
..
.."

Q

;:::=

....

~

so

•

ro

,....

"
11

"
"

"
"

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"

,.

·L~~'"

J'

11

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MonoiithlcW Memories

2-97

Large 24RA
20RA10

Large 24RA (PAL20RA10)
Description

Programmable Polarity

The PAL20RA10 is a 24-pin registered asynchronous PAL
device. This versatile device features programmable clock.
enable. set. and reset. all of which can operate asynchronously to other flip-flops in the same device. It also has individual,
flop-flop bypass. allowing this one device to provide any
combination of registered and combinatorial outputs.

Programmable Clock
The clock input to each flip-flop comes from the programmable array. allowing the flip-flops to be clocked independently if
desired.

Programmable Set and Reset
Each flip-flop has a product line for asynchronous set and one
product for asynchronous reset. If the chosen product line is
high. the flip-flop will set (become a logic HIGH). or reset
(become a logic LOW). The sense of the output pin is inverted
if the output is active low.

2-98

Each flip-flop has individually programmable polarity. The
unprogrammed state is active low.

Programmable Flip-flop Bypass
If both the set. and reset product lines are high, the flip-flop is
bypassed and the output becomes combinatorial. Thus each
output can be configured to be registered or combinatorial.

Programmable and Hard-Wired
Three-State Outputs
The PAL20RA10 provides a product term dedicated to output
control. There is also an output control pin (pin 13). The
output is enabled if both the output control pin is low and the
output control product term is high. If the output control pin is
high all outputs will be disabled. If an output control product
term is low. then that output will be disabled.

Register Preload and Power-up Reset
Each device also offers register preload for device testability.
The registers can be pre loaded from the outputs by using TIL
level signals in order to simplify functional testing. This series
also offers Power-up Reset. whereby the registers power up to
a logic LOW. setting the active-low outputs to a logic HIGH.

MonolithlcW Memories

Large 24RA
20RA10

DIP Pinout
2ORA10

PLCCPinout
2ORA10

Monolithic IFIJIMemor/es

2·99

Large 24RA
20RA10

Operating Conditions
COMMERCIAL

MILITARY

UNIT

PARAMETER

SYMBOL

,MIN
Vee

Supply voltage

tw

Width of clock

\vp

Preload pulse width

5.5

MIN
4.75

TYP

MAX

5

5.25

5
13

20

13

25

13

20

13

45

15

35

15

ns

10

20

10

ns
ns

ns

25

tsup

Preload setup time

30.

5

25

5

10

-2

10

-2

0

-6

0

-6

5

I Polarity fuse intact

th

Hold time

t hp

Preload hold time

30

TA

Operating free-air temperature

-55

Te

Operating case temperature

SYMBOL

I Polarity fuse blown

V

4.5
25

Setup time for input or feedback to clock

V IL 1

2.
3.

MAX

tsu

Electrical Characteristics

1.

I Low
I High

TYP

25

ns
ns

5

0

75

·C
·C

125

(Over Operating Conditions)

TEST CONDITION

PARAMETER

MIN

TYP

MAX
O.S

Low-level input voltage

UNIT
V

VIH 1

High-level input voltage

Vie

Input clamp voltage

Vee = MIN

II'" -lSmA

-O.S

-1.5

V

IlL 2

Low-level input current

Vee= MAx

VI = O.4V

-0.02

-0.25

rnA

IIH2

High-level input current

Vee = MAX

VI = 2.4V

25

!lA

II

Maximum input current

Vee = MAX

VI = 5.5V

1

rnA

VOL

Low-level output voltage

Vee = MIN

10L" SmA

VOH

High-level output voltage

Vee"': MIN

10H: MiI-2mA Com-3.2mA

2.4

IOZ2

Off-state output current

Vee = MAX

Vo = 2.4 VIVo = 0.4V

-100

IOS3

Output short-circuit current

Vee = 5V

lee

Supply current

Vee"': MAX

V

2

0.3

Vo= OV

-30

0.5

2.S

V
V

100

!lA

-70

-130

rnA

155

200

rnA

These are absolute voltages with respect to the ground pin on the device'and Inetude all overshoots due to system andlor tester nOise. Do not attempt to test
these values without suitable equipment.
1/0 pin leakage is the worst case of IlL and 'OZl' (or IIH and IOZH)'
No more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

Monolithic

W ••mor/es

Large 24RA
20RA10

Switching Characteristics
SYMBOL

tpD

(Over Operating Conditions)

TEST
CONDITIONS

PARAMETER

Input or
feedback to
output

MILITARY

COMMERCIAL
UNIT

MIN

TYP

MAX

MIN

TYP

MAX

Polarity fuse
intact

20

35

20

30

Polarity fuse
blown

25

40

25

35

ns

tCLK

Clock to output or feedback

17

35

17

30

ns

ts

Input to asynchronous set

22

40

22

35

ns

tR

Inllut to asynchronous reset

27

45

27

40

ns

tpzx

Pin 13 to output enable

10

25

10

20

ns

tpxz

Pin 13 to output disable

10

.25

10

20

ns

tpzx

Input to output enable

18

35

18

30

ns

tpxz

Input to output disable

15

35

15

30

f MAX

Maximum frequency

10

R1 = 560n
R2 = 1.1Kn

16

MonolRhlc WMemorles

35

10

20

35

ns
MHz

2-101

Large 24RA
20RA 1 0 Logic Diagram

20RA10
I

...

....
0

I
II -r.;t:1

2..,

~JF-~

I

.... -

•
II

:J;f"- ~

15

3

4'

..

5

..

:JF-

~

1
.
~
r:r;;1

~.

II

-W
U: ~
r3B

II

r;;t:'I

II

~

32

22

~

~

.

~ IF-- ~ ~
~

"

23

~~

1&

23

1_

1_

21

20

19

:JF- U: ~
RP
~

39

6
40

I
II

1
~
1.
~~
1_

W
J'F- U: ::i~P~
~

41

7,
48

II

~F-U:

65

8
~

156

I;f"

111

9

II

~

17

tr;;l

16

U: ~ ~

W

[1

r;;rJ

1.

It

II

r-r-~ ~~Pl~

II

10

n

~;f"

19

......

\I

o

••

7

a

1112

us

II!!

1928

23241128

Monolithic

3132

353&

39

"""

W MSlDorles

18

I
II

15

~
14

L:: ~ ~
A

'"'"

13

High Speed Programmable Array Logic
PAL32VX10,PAL32VX10A

Ordering Information

Features/Benefits
• Dual independent feedback paths allow buried state
registers or Input registers
• Programmable flip-flops allow J-K, S-R, T or D types for the
most efficient' use of product terms
•
•
•
•

10 input/output macrocells for flexibility
Programmable registered or combinatorial outputs
Programmable output polarity
Global register asynchronous preset/ synchronous reset or
synchronous preset/ asynchronous reset
• Automatic register preset on power up
• Preloadable output registers for testability
• Varied product term distribution
-Up to 16 product terms per output
• High speed
-25ns "A" version
-30ns standard version
• Space-saving 24-pin 300-mil SKINNYDIP® package or 28pin chip carrier
• Pin-compatible functional superset of 22V10

Pin Configurations

12

19

SKINNYDIP Package

11 to/eLK He vee t/01 1/02

110 GND He

111 11010 1/09

Plastic: leaded Chip Carrier

PROGRAMMA::J~~~32VX10A C LNS~.

TDpROCESSING
STD ~ Standard
XXXX ~ Other

ARRAY LOGIC

NUMBER OF
ARRAY INPUTS
OUTPUT TYPE
VX = Varied terms with XOA

'

NUMBER OF OUTPUTS
SPEED
_ _ _ _ _ _ _.J
~

Blank ~ Standard
A
~ High Speed

PACKAGE
NS' Plaatic
SKINNYDIP
JS = Ceramic
SKINNYDIP
FN ~ Pla.tic Leaded
ChlpCorrier
L----TEMPERATURE
RANGE
C ~ O·C 10 7S·C

General Description
The PAL32VX10 is a high-density ProQrammable Array Logic
(PAL®) device which implements a sum-of-products transfer
function via a user-programmable AND logic array and a fixed
OR logic array. Feature.d are ten highly flexible input/output
macrocells which are user-configurable for combinatorial or
registered operation, Each flip-flop can be programmed to be
either a J-K, S-R, T, or D-type' for 'optimal design of state
machines and other synchronous logic; In addition, a unique
dual feedback architecture allows I/O capability . for each
macrocell in both combinatorial and registered configurations.
This can be achieved eVen when register feedback is present,
and allows implementation pf buried flip'fJops while preserving
the external macroceH input; Supplied in space-saving 300-milwide dual in-line packages of 28'pin Chip carriers, the
PAL32VX10 offers a powerful, space saving . alternative to
SSIIMSI logic devices, while providing the advantage of
instant prototyping. Security fuses defeat readout alter programming and make proprietary designs difficult. to copy.
The PAL32VX10 is fabricated using .Monolithic Memories'
advanced oxide-isolated bipolar process for high speed and
low power. TiWfuse .linkS provide high reliability and programming yields. Special on;chip test circuits allow llo!lI AC, DC, and
functional testing before progratnming: Preloadable output
registers facilitate functional testing.
The PAL32VX10 can be programmed on statidard PAL device
programmers, fitted with appropriate programming modules
and configuration software. Design' development is supported
by Monolithic Memories'PALASM-++-

n =8, 10, 12, 14, 16

Figure 4. J-K Flip-FlOp Logie Equivalent;
J and K Can Also be Active-Low

The above discussions have assumed that it was most convenient to "group ones" in the Karnaugh Map. Sometimes it
takes fewer product terms to "group zeros", i.e., implement
the inversion of the desired function. The equations shown in
Table 1 are equivalent and can be interchanged to optimize
product term utilization. This can be readily proved through
logic reductions similar to that above.

(HOLD)
(RESET)

J and K active high

a:

(TOGGLE)

J active high, K active low

a:

J active low, K active high

a:

= a: + :(J*a +
= J*a + K*a
= J*O + K*a

J and K active low

a:

=

Q+

(SET)

Note:

K
n

Figure 3. J-K Flip-Flop Transfer Function

Dropping the ( + ) for simplicity, the equivalent Boolean
expression for a + is:
a: = R*a + J*O
In general, J and K can be sum-of-product expressions which
are provided in the PAL architecture only in active-high form.
Thus, a direct implementation of K expressions must invoke a
DeMorgan transformation, which can use excessive product
terms. This can be avoided by rewriting the equation for a
without inversions on the J or K inputs.
The XOA gate can be used to construct a logically equivalent
expression without any inversions on the J or K inputs. The
rewritten Boolean expression is:
a: = a: + :(J*O + K*a)
To check that these expressions are logically equivalent,
change the XOR to its equivalent sum of products form
(remember A: +: B = A*S + A*B) and reduce (using DeMorgan's theorem):
a: = a*(J*o + K*a)
+9*(J:9 + ~*a)
a: = a*«J + a)*(K +
+a*J*a + a*K*O
a: = a*(J*K + J*o + a*K + 0*0) + J*O
a: = J*R*a + K*a + J*O
which simplifies to
a: = K*a + J*O.

a»

2-106

Monolithic

J

J*a)

a: + :(J*a + K*a)

= sum

of produc:ts J1 + J2 + ,.. + Jm
"" sum of products K1 + K2 + ... + Kn - m
= total number of available product terms for a given macrocell
(8 to 16)

Table 1. J-K Flip-Flop Transfer Functions

S-R Flip-Flop. The S-A flip-flop has a truth table identical to

~

that of the J-K flip-flop, with the exception that the J = K = 1
(toggle) condition is not allowed. The S-A flip-flop implementation is identical to that of the J-K flip-flop, with J-K replaced by
S-R, and the S = A = 1 condition avoided.
T Flip-Flop. A T (toggle) flip,flop either holds its state or
toggles, depending on the logic state of the T input. The T flipflop is a subset of the J-K flip-flop and can be considered
equivalent to a J-K type with J = K. The general transfer
function and its active-low T equivalent are both given in Table
2.

Note: T

-=

a:

=

a:

+:T

a:

=

a:

+ :T

sum of products T1 + T2 + T3

+ ... + Tn

Table 2. T Flip-Flop Transfer Functions

W Memories

High Speed Programmable Array Logic
PAL32VX10,PAL32VX10A

Summary
The.pAL32VX10 can synthesize J-K, S-R, T, and 0 flip-flops,
whichever is most convenient for the application, without
sacrificing product terms. Additionally, the synthesized equations can use the active-high or active-low forms of the inputs,
allowing the designer to minimize product term requirements.

Flip-Flop Bypass
Any output in the PAL32VX10 can be configured to be
combinatorial by bypassing the output flip-flop. This is done by
setting the output multiplexer to the appropriate state. The
multiplexer is controlled by a product term which can be set
unconditionally for a permanent combinatorial (all. fuses
opened, product term high) or registered (all fuses intact,
product term low) output configuration, or can be programmed
to bypass the output flip-flop "on the fly, "allowing signals to
be routed directly to output pins under user-specified conditions.

Varied Product Term Distribution
An increased number of product terms has been provided in
the PAL32VX10 over previous generation PAL devices. These
terms are distributed among the ten macrocells in a varied
manner,rangingfrom eight to sixteen terms per output. The
five output pairs have 8, 10, 12, 14, or 16 product terms
available for the OR gate within each macrocell.ln addition,
each macrocell has one XOR product term and two architecture control productterms.

Programmable 110

to the XOR gate controlling the invert/not invert function. With
all fuses intact, there is no inversion through the XOR gate,
creating an active low output. Opening all fuses forces the
product term high, inverting data and creating an active high
output.
Registered Outputs. Output polarity for registered outputs
can be determined in two ways. For Ootype registered outputs,
polarity can be set by the XOR gate, as is the case with
combinatorial outputs. USing this method to set polarity, preset
and reset will not be affected.
Polarity, as observed from the output pin, can also be determined by the flip-flop output multiplexer. Note that this does
not affect the polarity of the register feedback signal, but does
affect preset and reset. By changing the flip-flop output
multiplexer, the preset and reset functions are exchanged,
relative to the controlling product terms.
With the multiplexer fuse intact, the Q output is routed to the
output pin, configuring an active low output. With the multiplexer fuse opened, Q is routed to the output pin, and
synchronous reset becomes synchronous preset. Similarly,
asynchronous reset becomes asynchronous preset.
Polarity options for J-K, S-R, and T flip'flops have been
discussed in the section on programmable flip-flops.

Power-Up Preset
All flip-flops power up to a logic high for predictable system
initialization. Outputs of the PAL32VX10 witlbe high or low
depending on the state of the register output multiplexers.

Register Preload

Each macrocell has a three-state output buffer with programmabie three-state control. Control is implemented by a single
product term, allowing specification of enable/disable functions controlled by any device input or output. Each macrocell
can be configured as a dedicated input by disabling the· buffer
drive capability, When this is done, the associated register can
still be used as ali input register or buried state register, due
to the independent register feedback path.

The register on the. PAL32VX1 0 can be preloaded to facilitate
functional testing of complex state machine designs. This
feature allows direct loading of arbitrary states, thereby making it unnecessary to cycle through long test vector sequences
to reach a· Qesired. state. In· addition, transitions from illegal
states can be verified by loading in illegal states andobserviligproper recovery,

Programmable Preset and Reset

Security· Fuse

The ten macrocell flip-flops share common programmable
preset and reset controLlor easy system initialization. The Q
outputs of the register will go to the logic low state following a
low-to-high transition on pin .1 (IO/CLK) when the synchronous
reset (SR) product term is asserteQ, The register will.be forced
to the logiC high state independent of the clock. when the
asynchronous preset (AP) product term is asserted.

After programming and verification, a PAL32VX10 design can
be secured by programming . the security fuSes. Once programmed, these fuses defeat readback of the internal fuse
pattern by a device programmer, making proprietary designs
very difficult to copy.

Programmable Polarity

.

The polarity of each macroceli output can be set active high or
active low.
Combinatorial Outputs. The XOR gate provides polarity
control for combinatorial outputs, with the single product term

Quality and Testability
The PAL32VX10 offers a very high level' of bui.lt-in quality.
SpeCial on-Chip test circuitry provides a means of verifYing
performance of all AC and DC parameters prior to programming. In addition, these built-in. test paths verify complete
functionality of each device to provide the highest postprogramming functional yields iii the industry;

MonoiithleWMemor/es

2-107

High. Speed Programmable Array Logic
PAL32VX10,PAL32VX10A

Absolute Maximum Ratings
Operating

Programming

Supply voltage Vee .................................. , .. ,... . .. ....... ................ ......... ...
-0.5V to 7V . ;:.. ...... ... .. -0.5V to 12V
Input voltage ....................................................................................... -1.5V to 5.5V ................ -1.0V to 22V
Off-state output vOltage ......................................... ,............................................ 5.5V ............................ 12V
Storage temperature ........................... :. ....... .. .. ... .... .. . ... .. .. ..... .. .. .. .... ... ... .... .. .. ... .. .. ... .. ... .... .. ... .-65°C to + 150°C

Operating Conditions
COMMERCIAL 1
SYMBOL

PARAMETER

STD
MIN

..

Supply voltage

Vee
tw

Width of clock

Isu

Setup time from input
or feedback to clock

.....
taw

1.
2.

5.25

18

10

High

20

10

18

10

Product terms P1~P n' SR

30

20

25

20

Product term XOR

35

25

30

25

0

V
ns

ns

-10

0

-10

ns

-30

20

25

20

ns

-30

20

25

20

ns

25

20

0

25

tsr

Asynchronous reset recovery time

-30

20

TA

Operating case temperature

0

25

75

ns
75

°C

Over Operating Conditions

PARAMETER

TEST CONDITION

Low-level input voltage

VIH 2

High-level input voltage

Vie

Input clamp voltage

Vee

IlL 3

Low-level input current

Vee';;; MAX

VI

IIH 3

High-level input current

Vee

Maximum input current

Vee

= MAX
= MAX

VI

II
VOL

Low-level output voltage

Vee =MIN

VOH

High-level output voltage

Vee

OIl-state. output current

Vee = MAX

Output short-circuit current

TYP

MAX
•

11 = -18mA

= MIN

V

-0.8

-1.5

V

10l = 16m!\
10H = -3.2mA

I
I

-0.02

"':0.25

rnA

SiJPply.current

Vee = MAX

Input capacitance

VIN

COUT

Output capacitance

VOUT

= 2.0V

0.35

2.4

3.4

pA
pA

0.5

V
V

= O.4V

-:-100
100

/JA

-70

-130

mA

140

.. 1.80

mA

Vo = OV

= 2.0V at 1=

.

25
200

Vo = 2.4V

Vo

Vee = 5V

lee

= 0.4V
= 2.4V

V

VI = 5.5V

= MIN

CIN

..

UNIT

0.8

2

..

IOS4

MIN
...

V IL 2

IOZH3

MAX

5

5

5.25

UNIT

TYP

10

tar

IOll 3

4.75 I

4.75

Asynchronous preset recovery tirne

SYMBOL

MIN

20

. Asynchronous preset width

Electrical Characteristics

MAX

LOw

Hold time

th

TYP

A

..

.

1MHz

at f = 1MHz

-30

6

pA

pF

11

The PAL32VX10/A is designed to operate over the full military operating conditions. For availability and specifications contact Monolithic Memories.
These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and or tester noise. Do not attempt to test these
values without suitable equipment.

3.

1/0 pin leakage is the worst case of III and IOZl (or IIH and IOZH)'

4.

No more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

2-108

MonoIlthlcWMemorles

High Speed Programmable Array Logic
PAL32VX10, PAL32VX10A

Switching Characteristics
"

SYMBOL

Over Operating Conditions

PARAMETER

TEST
CONDITION

STD

A

MIN riP MAX MIN TYP

I Product terms Pt-Pn
I Product term XOR

MA~

15

30

15

25

25

35

20

30

UNIT

tpD

Input or feedback to
output

teLK

Clock to output or feedback

10

15

10

15

ns

tpzx

Input to output enable

20

30

20

25

ns

tpxz

Inpuno output disable

20

30

20

25

ns

tAP

Asynchronous preSet to output

20

30

20

25

ns

teR

Input or feedback ,to registered output
from ,cQmbinatonal configuration

90

75

' 90

ns

90

75

90

ns

Rt = 2000
R2 '" 3900

75
"

Input or feedback to combinatorial output
fromregistered,configuration

tRc
'f

fMAX'

F!ledbliCk

Maxnnum:
frequency

(1/tpt )

I Product terms Pt:Po
I Product term XOR

No feedback (1/t P2 )

ns

75
22.5

35

25

35

20

.30

22.2

30

25

40

27.7

'40

MHz
,.)-

,

SWitching Test Load

S.chematlcof,nputs ar:td:.Outputs
EOUIVALENT INPUT
vcc~----~~----~

8 KUIiOU
Rt
OUTPUT .......--+-,-'-'----r--@.TESTPOINT

NOles:

L !po Js 1 _ with sWitch.8, cIOBed.GL =5QPF 'and measur9d at 1.5V 9utpJJI·~vel., , .
",'
2. !Pzx is measured at the 1.5V output level with Ci, =50pF. 8, ~'Open fo'high impedance 1ll"!.Htesr~nd glOBed for high impedance to "O"test
3 \pxz iBtested with
5pE 8,iS open for "t",,! hj~h impedance.!est. measur"l!",,! VOff-O.~Y:P~,~ lEiv~liS, is closed lor ."0" to high impedance test
. measured at VOL +0.5'1 output I~.
' . . • : ' Y '.....'
, " " ,',,'
": .
'

c.. -

2~10!r

High Speed Programmable Array Logic
PAL32VX10,PAL32VX10A

Switching Waveforms
INPUTS, 1/0,
REGISTERED
FEEDBACK,
SYNCHRONOUS
RESET

~---3V

'-----0 V

-'s,
ClK

ASYNCHRONOUS
PRESET

REGISTERED
OUTPUTS _ _ _LIIlIIIiIIlII'

COMBINATORIAL
OUTPUTS

~

________________ww

Output Register Preload
The preload function allows the register to be loaded from the
output pins. This feature aids functional testing of sequential
designs by allowing direct setting of output states. The procedure is:
1. Raise Vee to 4.5V.
2. Disable output registers by setting pin 2 to V IHH (12V).
3. Apply VllIV IH to all registered output pins. Leave combinatorial outputs floating.
4. Pulse pin 10 to V IHH • then back to OV.
5. Remove VILIV IH from all output registers.
6. Remove high voltage from pin 2.
7. Enable registered outputs per programmed pattern.
8. Verify for VoLIVOH at all registered output pins.

PIN 2

VllIVIH
REGISTERED VIH~
~
OUTPUTS Vll~'---_ _ _ _ _ _

1'--

PIN 10

Note: V'HH - 11.0 (MIN), 11.5 (TYP) and 12.0 (MAX).

Key to Timing Diagrams
WAVEFORM

2-110

INPUTS

OUTPUTS

DON'TCARE:
CHANGE PERMITTED

CHANGING;
STATE UNKNOWN

NOT
APPLICABLE

CENTER liNE IS
HIGH IMPEDANCE STATE

MUST BE STEADY

Will BE STEADY

Monolithic

W Memories

High'Speed Programmabl. Array Logic
PAL32VX10, PAL32VX10A

f MAX Parameters
The parameter fMAX is the maximum speed at which the PAL
device is guaranteed to operate. Because flexibility inherent to
PAL devices allows a choice ,of clocked flip·flop designs, for
the convenience of the user, fMAX is specified to address two
major classes of synchronous designs.
'
The simplest type of synchronous design can be described as
'a data path application. In this case, data is presented to the
data terminal of the flip·flop and clocked through; no feedback

is employed (Figure 1). Under these conditions, the frequency
of operation is limited by' the greater of the data setup time
(tsu) or the minimum clock period (tw high + tw low, or tP2).
This, parameter is designated fMAX (no feedback).
For synchronous sequential designs, i.e., state machines,
where logical feedback is required, inputs to flip·flop data
terminals originate from the device input pins or flip· flop
outputs via the internal feedback paths (Figure 2). Under
these conditions,fMAX is defined as the reciprocal of (tsu +
telK), or tP1, and is designated fMAX (feedback).

~

.......
~

I

~

~

.

Figure 1. Data Path Register Configuration Without Feedback; Q:

=i

"

~

"'"
...

I

.....

il

..

~

Figure 2. State Machine Configuration With Fe8dback, Q:

.l.Dol0B0M

=I + Q

" "T

Use of XOR Product Term
The speed of the PAL32VX10 isspecJfiedaccording to the
use of the Exclusive·OR (XOR) produCt term in the macrocell.
Note that the macrocell data input is a functiOn of the tWo·
input XOR gate,: whose inputs are the OR of the product terms
P1-Pn and the single additional XOR prqduct t~!rn (Figure 3).
The specification for the path through thesingie 'XOR product
term is 5ns slower, than thrqughthe P1.Pn product termS and
the OR gate. As.a result, if,1hE! singfe XOR product' term is,
changing, the macrocell data input will not be available until
5ns later than if Only the P1-Pn product terms were changii'1g.
This difference, between paths affectstPD,tsu, a;tii fMAX
(feedback). As a, result, these three parameters are specified
both for only the 'P1,·Pn product'terms changing ("Pro'duct
terms P1-Pn") and with the single XOR product term ch~i'1~ing
("Product term XOR") (Figure 4). "
'."

PRODUCT

!=~!

XOR~~""
P1

'Pn

. ,

: ' '. '"

,'

','

"", ,

~'",'

D Q

"

.n =8. 10. 12, 14; 16

Flgur,e3,.

,

EXPLANATION

SPECIFICATION
tpD ,

Isu'

'...

f MAX (feedblickj"jproduct'termsP1.Pn
Product term XOR

"

I

'If only the P1-Pn product terms are changing (XOR term is ~otchangingr
If XOR term is changing

,;
,

Figure 4.

High Speed Programmable Array Logic
PAL32VX10,PAL32VX10A
MANUFACTURER

PROGRAMMER CONFIGURATION

Data I/O Corp.
10525 Willows Rd. NE, PO Box 97046
Redmond, WA 98073-9746
(800) 247-5700

System 29A, 29B
LogicPakTM 303A
Adapter 303A-Oll AlB-VOl

Family/Pinout Code:
22-77

Digelec Inc.
1602 Lawrence Ave., Suite 113
Ocean, NJ 07712
(201) 493-2420

Contact manufacturer

Digital Media
11770 East Warner Ave., Suite 225
Fountain Valley, CA 92708
(714) 751-1373

Contact manufacturer

Japan Macnics Corp.
2999 Monterey/Salinas "Hwy.
Monterey, CA 93940
(408) 373-3607

Contact manufacturer

Kontron Electronics Inc.
1230 Charleston Rd.
Mountain View, CA 94039-7230
(415) 965-7020

System EPR-80
Module UPM·B rev. 1.48 or later

Micropross
Parc d'activite des Pres
5, rue Denis-Papin
59650 Villeneuve-d' Ascq
(20) 47.90.40

Contact manufacturer

Stag Microsystems Inc.
528-5 Weddell Dr.
Sunnyvale, CA 94089
(408) 745-1991

Contact manufacturer

Storey Systems
3201 N. Hwy 67, Suite H
Mesquite, TX 75150
(214) 270-4135

Contact manufacturer

Structured Design
988 Bryant Way
Sunnyvale, CA 94087
(408) 988·0725

Contact manufacturer

Valley Data Sciences
Charleston Business Park
2426 Charleston Rd.
Mountain View, CA 94043
(415) 968-2900

Contact manufacturer

Varix Corp.
1210 E. Campbell Rd., Suite 100
Richardson, TX 75081
(214) 437-0777

Contacl manufacturer

MANUFACTURER

SOFTWARE DEVELOPMENT SYSTEM

Monolithic Memories, Inc.
IdeaLogic@ Exchange MIS 0"9-25
2175 Mission College Blvd.
Santa Clara, CA 95054-1592
(800) 247-6527 ext. 6105

PALASM@ 2 Software rev. 2.21 and later

Data I/O Corp.
10525 Willows Rd. NE, PO Box 97046
Redmond, WA 90873-9746
(800) 247-5700

ABEL™ Software -

Contact manufacturer

Personal CAD Systems
Assisted Technology Division
1290 Parkmoor Ave.
San Jose, CA 95126
(408) 971-1300

CUPL™ Software -

Contact manufacturer

IdeaLoglc

IS

a trademark of MonolithiC MemOries.

LogicPak and ABEL are trademarks of Data 110 Corporation.
CUPL is a trademark of Personal CAD Systems.

2-112

Monolithic

m

Memories

PMS14R21/A

Features/Benefits

Description

• llser-programmable synchronous s~te machine
• 25MI;tz maximum frequency for compatibility with 12.5MHz
processors
• 14 inputs (8 external), 8 outputs, 128 states
• PAL@ array optimizes product "terms and states
• Internal feedback adds versatility and Control
• Optimized for four-way branching
"
• User-selectable asynchronous preset or asynchronous
enable function
• Power-up preset for start-up in known state
• Diagnostics-On-Chip™ shadqw register eases chip and
board-level testing
• PfloSETM: deviJ:$software makes it easy to "write your
sequenc;:er in PRO$E"
.

The PMS14R21 programmable sequencer is the first member
of the PROSE (PROgrammable SEquencer) family. The
PMS14R21 is a high-speed, 14-input, 8-output state machine.
It consists of a 128x21 PROM array preceded by a 14H2 PAL
array. The PAL array is efficient for a large number of input
conditions, while the PROM array is 'optimal for a large
number of product terms and states. The combination allows
a very efficient state machine with a large number of inputs
and state bits. The PAL array, with eight product terms per
output, operates' on the eight conditional and six state inputs
to select two control bits to the PROM. Two Exclusive-OR
gates between the two arrays help to minimize product terms
and redundant states. Five lines feed back from the PROM to
form the primary address fOr the next state. The PROM stores
up to 128 statas of eight outputs andthirteen feedback control
signals.'
",

• Programmed on standard logic programmers
• Security fuse prevents pattern "duplication'
• Space-saving 24-pin 300-mH SKINNYDIP@and28-pin
PLCC and LCC packages

Applications
•
•
•
•
•

High speed sequential logic
Peripheral controller
Cache control sequencer
Signal procesSing "sequencer
Industrial control

Block Diagram
DCLK SOl

CLK

10

"
12
13
14
15

•
17

ClK

Deflnlt10n of Signals.
10-17
ao-Q7

PIE

Primary inputs to the PAL array
Outputs from the regiSter '
Pr'ogrammableasynchronouspteset
, asynchrol)Pljs, enable ,(E) .

(P)

or

DCLK
MODE
SOl

500

Clock for output register
Clock for diagnostic register
Selects diagnostic. functions
'Serial data input to shadow register
Serial data output from shadow register

PROSETM and Diagnostics-On.ChipTM are trademarks of Monolithic Memories. Inc.

2~113

PMS14R21/A

Software Support

PROSE Part Numbering System

L

PROSE device software from Monolithic Memories provides
full support for the PMSI4R21. Based on PALASM@2 syntax,
the software automatically converts a state machine description directly into the PAL and PROM array fuse maps, for
downloading to a programmer. The syntax supports both
Mealy and Moore state machine models, and makes optimal
use of the features of the PROSE .device. Simulation support
is also provided, both for design checking and for generation
of test vectors for device testing. Additional support is available from third-party software vendors, including the ABEL™
package from Data I/O.

PMS 14 R21 A C NS STD

PREFIX~

PROCESSING
SrD = Standard
XXXX ... Other

PMS = Programmable
Memory~based

Sequencer

PACKAGE
NS = Plastic SKINNYDIP
JS = Ceramic SKINNYDIP

NUMBER OF
ARRAY INPUTS

NL ... Plastic Leaded
Chip Carrier
L = Leadless Chjp Carrier

OUTPUT TYPE _~_-'
A .. Regj$tere~
NUMBER OF REGISTERS

PERFORMANCE _ _ _ _---'
Blank = standard
"" enhanced
A

' - -_ _ _ OPERATING CONDITIONS
C = O°C to 75°C
M = _55°C to 125°C

Programming
Both the PAL and PROM arrays are programmed on standard
logic programmers using the JEDEC programming format. The
TiW fuses program from the low to the high state. Programming also sets the architectural fuse which selects between
asynchronous preset or asynchronous output enable; the
unprogrammed state is preset. If asynchronous preset is
selected, asserting the pin low will set all outputs and feedback bits high.

Diagnostics-On-Chip Feature
The PMS14R21 is the newest member of the Diagnostics-OnChip family. These devices incorporate a serial shadow register on-chip which facilitates board-level testing. The shadow
register has a Serial Data Input (SDI), Serial Data Output
(SDO) and its own clock (DCLK). The MODE control configures the shadow register either in parallel with the output
register or in serial shift mode (see function table). Other
devices with this feature are listed below.

Power-up Preset
Power-up preset is provided for system start-up in a known
state. It has the same effect as preset; all output register bits
go high.

Diagnostics Family Members
PART
NUMBER

DESCRIPTION

53/63DA441

1K x 4 PROM (async. enables)

53/63DA442

1K x 4 PROM (async/sync. enables)

53/63DA841

2K x 4 PROM

53/63D1641

4K x 4 PROM (async. enable)

53/63DA1643

4K x 4 PROM (async. initialization)

54174S818

8-bit register

Diagnostic Function Table
OUTPUTS

INPUTS

OPERATION
MODE

SOl

ClK

L

X

t

L

X

·

L

X

t

H

X

t

H

L

·

H

H

·

.

OClK

S20 - So

SOO

an +- PROM

HOLD

S20

Load output register from PROM array

t

HOLD

Sn +- Sn_l
So +- SDI

S20

Shift shadow register data

t

.

an +- PROM

Sn +- Sn_l
So +- SDI

S20

Load output register from PROM array
while shifting shadow register data

an +- Sn

HOLD

SDI

Load output register from shadow register

t

HOLD

Sn +- an

SDI

Load shadow register from output bus
and feedback

t

HOLD

HOLD

SDI

t

Q20 - Qo

* Clock must be steady or falling.

t

Reserved operation for 54/745818 8-Bit Diagnostic Register.

2·114

Monolithic WMemories

No operation

PAL10H20P8
Features/Benefits

Features

•
•
•
•
•
•
•
•
•

Each output has a programmable polarity fuse, allowing for
more efficient representation of many logic functions. Each
output is active high with polarity fuse intact, and active low
with the polarity fuse blown.
The programmable AND array contains a total of thirty-two
product terms. Product terms are arranged in groups of eight.
The terms in each group can be shared mutually exclusively
between two adjacent output cells. If a particular product term
is needed for two outputs, then two identical product terms
are generated: one for each output.
A security fuse is provided to help protect the fuse pattern
from unauthorized copying. Once the security fuse has been
programmed, it is no longer possible to verify the contents of
the fuse array electrically. The security fuse has no effect on
functionality.

20 logic inputs: 12 external, 8 feedback
8 outputs with programmable polarity
ECl technology for ultra-high speed - max tpo = 6ns
32 product terms with term sharing
10KH ECl compatible
Fully AC tested
Input pull-down resistors
Voltage compensated
Space-saving 24-pin SKINNYDIP® and 28-pin PlCC
packages
• Programmable using standard TTL programmers with
adapter
• Greater than 99% programming yield
• Security fuse prevents unauthorized copying

Description
The PAl10H20P8 is a 10KH family compatible ECl PAL
device having twelve dedicated inputs and eight outputs with
feedback. A programmable AND array and a fixed OR array
make possible the implementation of a wide variety of logic
functions with far fewer packages than with SSI devices. The
logic is implemented by opening metal fuse connections within
the AND array. Designs can be .specified by using any of a
variety of software packages which accept the. design and
assemble a file that can be downloaded into a device programmer•. Fuses are programmed using any of the qualified
PAL device programmers.
The outputs are equipped with programmable polarity. They
can drive a 50n termination (to Vee - 2.0V). Product term
sharing is provided to allow greater flexibility in assigning
product terms to outputs.
The input pins have 50kninternal pull-down resistors, which
allow u.nused inputs to be left open. Open inputs will assume a
logic low state.

MonoIlthlcfFIJJMemorl••

2-115

~

~

PAL10H20P8
DIP Pinout

PLCC Pinout

COO0880M

MonoIithicm Memories

PAL10H20P8
Absolute Maximum Ratings
These ratings specify the conditionsabove which the device may be permanently damaged. AC and DC specifications are not
necessarily guaranteed over this range.
Supply voltage VEE (VCC1 = VCC2 = VCC3 = OV) ............................................................................. , .......... -8.0V to OV
Input voltage VI (VCC1 = VCC2 = VCC3 =OV) ................................................................................................ OV to VEE
Output current, lOUT
Continuous .............................................. " ........................... ; ............................................................. 35mA
Surge ........ , ............................ :................................................................... ; ........ ; ...,'.: ....................... 100mA
Storage temperature range, Tstg .......................................................................................................-65°C to 150°C

Operating Conditions
COMMERCIAL
SYMBOL

PARAMETER

UNIT
MIN

VEE

Supply voltage (Vcc '= OV)

-5.46

TA

Operating free-air temperature

0

Electrical Characteristics
SYMBOL

Vee

= -5.2V

TYP

MAX

-5.2

-4.94

.

75

V
°C

± 5% (See note 1)

TEST
CONDITIONS

PARAMETER

DoC

25°C

75°C
UNIT

MIN

MAX

MIN

MAX

MlN

MAX

-

210

210

..

210

mA

425

-

265

-

265

pA

0.5

-

0.5

-

0.3

lEE

Power supply current

Inputs VIN = VIH Max

linH

Input current high

VIH Min

linL

Input current low

VIL Min

VOH

High output voltage

(See Note 2)

-1.02

-0.84

-0.98

-0.81

...,0.92 -0.735

Vdc

VOL

Low output voltage

(See Note 2)

-1.95

-1.63

~1.95

-1.63

-'1.95

-1.60

VdC

VIH

High input voltage

(See Note 2)

-1.17

-0.84

-1.13

-0.81

-1.07 -0.735

VdC

VIL

Low input voltage

(See Note 2)

-1.95

-1.48

-1.95

-1.48

-1:95

Vdc

Switching Characteristics

VEE

= -5.2V

< Yin < VIH Max
< Yin < VIL Max

-1.45

p.A

± 5% (See note 2)

DoC
SYMBOL

-

25°~

75°C

PARAIIIIETER

UNIT
MIN

MAX

MIN

MAX

MIN

MAX

tpo

Propagation delay

2.0

6.0

2.0

6.0

2.0

6.0

ns

tR

Rise time (20%-80%)

0.7

2.2

0.7

2.0

0.7

2.2

ns

Fall time (80%-20%)

0.7

2.2

0.7.

2.0

0.7'

2.2

ns

tF
Note:

1. Each Eel 10KH"senes CIrcuit has been deSigned to meet the specifIcations shown in test table after thermal equilibrium has been established.
The circuit is in 'test socket or mounted on a printed board 'and transverse air flow greater than 500 linear- fpm is maintained.
2. qutputs are terminated through a 50n. resistor to Vee - 2.0V. Discrete carbon resistors should be used for terminations. Multiple-resrstor packs and metal
film discrete resistors are inductive and should be avoided. The single-ended nature 'of the outputs demands strict adherence to ground and termination
plane design techniques.
3. If pin 13 (PLCC pin 16) is not used, it should be left open or terminated ,to Vrr ( = Vee - 2.0V). It should not be terminated to VEE'

MonolithIC

W Memories

2-117

PAL10H20P8
Logic Diagram

,

VCC3
IltS

2

>3>
3

24
I 281

121
~

, • 1

•• 1011

lt1SIH5

1fll1,"

lHUH3

patin

ZUUIU!

.SUUl

.373131

~

141

·,,

,

~4:>
~~
~D -pu

·:,

151

5

161

,
'"

I

,

Veel

10
112 1

·

:R

~sD pU
pu

""
""
"

i7I

7

,"

,101•

"

1131

13

,,'

1

:8~
~

:t

""
"

···

'-'

:R~
~

17

~~

I 201

-pu

"'"
"'

18
,111

"

1

VCC2 (231

15

1

·""

~D

··"

-pu
-pu

20

'41

I

21

125>

16
09~

22
1:i61
23

01!1

4$6J

•• 1011

1113141'

'111'1'"

!II'flnn

24!f>'2111

ZI 2UI 31

'3133:M36

3&31.»

127>
12

1t4.~-IJEE

2-118

Monolithic

W Memories

I

MegaPAL Devices

32R16, 64R32

MegaPAL Devices

PAL32R16
PAL64R32

ARRAY INPUTS

REGISTERED OUTPUTS

32
64

16
32

(ns)

Icc
(mA)

40
50

280
640

tpD

Description

Register Bypass

The MegaPAL Devices offer very high density programmable
logic.

Registers in either device can be bypassed in banks of eight,
creating a set of combinatorial outputs.

Programmable Polarity

Reset

Each flip-flop has individually programmable polarity. The
unprogrammed state is active low.

The PAL64R32 also features asynchronous reset (previously
called preset). The reset function sets a bank of eight registers to a logic LOW, setting the output HIGH if active low.

Product Term Sharing
Product term sharing allows each pair of outputs to share its
product terms with one output or the other (not both). Each
pair has a total of sixteen product terms; thus, one output can
use zero to sixteen terms while the other has sixteen to zero.
Product terms can only be shared mutually exclusively. If both
outputs need the same term, it must be created twice, once
for each output.

Register Preload and Power-up Reset
Both devices also offer register preload for device testability.
Th.e registers can be preloaded from the outputs by using TTL
level signals in order to simplify functional testing. This series
also offers Power-up Reset, whereby the registers power up to
a logic LOW, setting active-low outputs tOil logic HIGH.

Monolithic WMemories

~..
....

MegoaPAL Devices
32R16, 64R32

32R16
64R32

Plastic Chip carrier

DIP
32R16

PIutIc Chip carrier
CD0027QM

2-120

MonoIithlcWMemories

MegaPAL Device.
64R32

Testing Conditions
COMMERCIAL
SYMBOL

UNIT

PARAMETER
MIN

TYP

MAX

twp

Preload pulse width

35

ns

tsup

Preload setup time

50

ns

t hp

Preload hold time

5

ns

tpRW

Preset pulse width

25

ns

tpRR

Preset recovery time

35

ns

MonolithIC WMemo,.;e.

2'-t21

MegaPAL Devi.ces
32R16

Operating Conditions
MILITARY
SYMBOL

UNIT
TYP

MIN
Vee

. Supply voltage

4.5

I Low
I High

1w

Width of clock

1wp

Preload pulse width

tsu

COMMERCIAL

PARAMETER

Setup time for input to clock

II Polarity fuse intact
Polarity fuse blown

MAX
5.5

5

MIN

TYP

MAX

4.75

5

5.25

25

20

25

20

45

.35

50

40

Preload setup time

30

Hold time

0

ns
ns

25
-10

0

t hP

Preload hold time

10

5

TA

Operating free-air temperature

-55

0

Tc

Operating case temperature

SYMBOL

ns

40.

th

Electrical Characteristics

ns

50

tsup

V

-10

ns
ns
75

·C
·C

125

(Over Operating Conditions)

TEST CONDITION

PARAMETER

MIN

TYP

MAX

V

Vll '
VIH '

High-level input voltage

Vie
IIl 2

Input clamp voltage

Vee = MIN

11 = -lSmA

-O.S

-1.5

V

Low-level input current

Vee = MAX

VI = O.4V

-0.02

-0.25

mA

IIH2

High-level input current

Vee = MAX

VI = 2.4V

25

jJA

II

Maximum input current

Vee = MAX

VI = 5.5V

1

mA

Val

Low-level output voltage

Vee = MIN

VOH

High-level output voltage

Vee = MIN

Off-state output current

Vee = MAX

IOS3

Output short-circuit current

Vee = MAX

Ice

Supply current

Vee = MAX

lozl 2

O.S

UNIT

Low-level input voltage
2

Mil

10l = SmA

Com

10l = SmA

Mil

10H = -2mA

Com

10H = -3.2mA

IOZH2

Switching Characteristics

tpo

Input to
output

0.3

2.4

0.5

2.S

V

V

Va = O.4V

-100

jJA

Va = 2.4V

100

j1A

-70

-130

mA

200

2S0

mA

-30

Va = OV

(Over Operating Conditions)

TEST
CONDITIONS

PARAMETER

SYMBOL

V

MILITARY

UNIT
MIN

TYP

I Polarity fuse intact
I Polarity fuse blown

telK

Clock to output or feedback

tpzx

Output enable

tpxz

Output disable

fMAX

Maximum frequency

COMMERCIAL

R, = 560n.
R2 = UKn.

MAX

MIN

TYP

MAX

50

40

55

45

30

25

ns

25

20

ns

25
14

20
16

ns

ns
MHz

1.

These are absolute voltages with respect to the ground pin on the device and Include all overshoots due to system and!or tester nOise. Do not attempt to test

2.

these values without suitable equipment.
1/0 pin leakage is the worst case of I'L and 10ZL lor I," and 10Z")·

3.

No more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

2·122

Monolithic

IFJ] Memories

MegaPAL Device.
64R32

Operating Conditions
COMMERCIAL 1
SYMBOL
Vee

UNIT

PARAMETER
Supply voltage

Iw

Width of clock

tsu

Setup time from input to clock

MIN

TYP

MAX

4.75

5

5.25

Low

20

High

20

Polarity fuse intact

40

Polarity fuse blown

40

th

Hold time

0

TA

Operating free-air temperature

0

Te

Operating case temperature

Electrical Characteristics

V
ns

ns
-10

ns
75

°C
°C

(Over Operating Conditions)

COMMERCIAL
SYMBOL

PARAMETER

UNIT

TEST CONDITION
MIN

VIl 2
VIH 2

High-level input voltage

Vie

Input clamp voltage

Vee

IIl 3

Low-level input current

Vee

IIH 3

High-level input current

Vee

II

Maximum input current

Vee

VOL

Low-level output voltage

Vee

VOH

High-level output voltage

Vee

TYP

Low-level input voltage

O.S

V

-O.S

-1.5

V

-0.02

-0.25

mA

2

= MIN
= MAX
= MAX
= MAX
= MIN
= MIN

IOZl 3
IOZH 3

Off-state output current

Vee

= MAX

IOS4

Output short-circuit current

Vee

lee

Supply current

Vee

= 5V
= MAX

Switching Characteristics

MAX

= -1SmA
VI = 0.4V
VI = 2.4V
VI = 5.5V
IOl = SmA
IOH = -O.4mA
Va = O.4V
Vo = 2.4V

V

II

Va = OV

0.3
2.4

25

p.A

1

mA

0.5

2.S

V
-100

-10

V

p.A

100

p.A

-40

-60

mA

400

640

mA

(Over Operating Conditions)

COMMERCIAL
PARAMETER

SYMBOL

TEST CONDITIONS

UNIT
MIN

TYP

I Polarity fuse intact
I Polarity fuse blown

tpo

Input to output

!elK

Clock to output or feedback

tpzx

Output enable

tpxz

Output disable

tpRH

Preset to output

fMAX

Maximum frequency

MAX
50
55

R1 = 560n
R2 = 1.1Kn

16

20

ns

22

ns

30

ns

30

ns

35

ns
MHz

1.
2.

The PAL64R32 Senes IS designed to operate over the full mlhtary operating conditions. For availability and specifications, contact Monolithic Memories.
These are absolute voltages with respect to the ground pin on tl}e device and include all overshoots due to system andlor tester noise. Do not attempt to test

3.

these values without suitable equipment.
1/0 pin leakage is the worst case of I'l and IOZl (or I'H and IOZH).

4.

No more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

MonoIlthlcW·.emorles

2-123

MegaPAL Device.
32R16 Logic Diagram

32R16
(18) (17) (16)
16 NC 15

p
(19) 17

(20) 18

I
I

t

:r

~ ~

~

i i i *vcc*

***

NC(&)

r4-'--

0

127

-.

Wp

~

(15) (14) (13) (12)(11)(10) (9) (8) (7)
14131211109876

UinrtJ::

.~

•

'-n.

15·

'12
j;
~

~

(21) 19

(22)20

I

.c-

~

.r

Im~

L..,""

111

.Jr. ::f'~
t-'

~-'fD

~t:.

L

-.
......
••

r.J.
J
r.J.~

.J;;"

~

~
~

..J

~

16

t:J.

~

-9-~
J
.- dJim
r.L
J

0.....

..~

4 (4)

3(3)

2 (2)

1 (1)

I~

31·

..;;

5 (5)

~

AND

ARRAY
8K
FUSES
(23) 21

.l:""

I""

~

(24) 22

Lf>.

(25)23

(26) 24

(27)25

I
I

~

95

.~

~

~ t-;;1..

~
~

-i>-

32

......

trhrtJ: -.
w~

+

-*80

47*

-"

~

~

79

.~!lJ:
~

~

..

-.

*64

r~
H

~

"'"-

;;

;.;0.

~J

40 (44)

39(43)

~

t.l

~

r-

II

t.l

~.

~

.l

~-m::

~

48

......

t.l

$

~

~

J

~-m::

'J. ,I

~

~

38 (42)

37 (41)

~~

I

(2I)NC

40 PIN DIP
(44P1NLCC)

~ ~

l

~GND~ ~ ~ ~

25 27 28 29 30 31 32 33 34
(29) (30) (31) (32)(33)(34) (35) (38) (37)

~.

35

r

Ne 38

(38)(39) (40)

Lt"",,"

2-124

MonoIlthIcW.emorle.

MegaPAL Devices
64R32 Logic Diagram

64R32
Ne

113112
114113
(15)14
116115

~

ffit:. "ty
~-Bi1

1111}17

v
1
~ ~~

~

16

,~ 1

.. 224+

120119

(21120
(22)21

123122
(24123

125124
(211} 25

~ Kn:.-Bii

~~
Lt>--

~

1'

i

+63

~ ~T

~!

~

-r5 ~
~-

.;L

~ Hb.-1iili1

175

~

-J Hh~b

·95

159

"1

~r-

...

..

~r-

·127

(32)31

-~

144·

112

-J ~ nt;;;;

(33)32-VCC

~v
r ~:m=

~

·111

tl--IlI'i1

-1>--

-tiiI
1 '1g. -rn-

~.

~

l: lin-

(31)30

-~

...

116
...L

.£ tiiLa=1
Hh~b
~l

~

r ~~

.. 180·-

~

(30)29

~ ~-m::

~

~

-r5

..rfI

1 '1g. -rn-

F

~l

143
;.,...

•

.

128·

NC

3334

"i;qt"
1;1" ' " ~ 1;1~1;1
35 3& 'II 3& 39 40 41 42 43 44 46 46 47 48 49 50

1341

135113&1

(37)(311)1391 .... 1411(42)(431(4411461141111471 14111(49)(50)15111521

Monolithic

W Memories

112(651

I~

in*"

80
...L

~r-

(27)28

;
-~

i~~:m=

~

*79

84(67)

-

I~~ 83II1II

....

1

~

l:~.

191

32K
FUSES

~

'J

~

Ir~
'
isr l L

AND
ARRAY

84

67(70)

1~

F

~

~....J

88(71)

-~

1O7
;.,...

48

89(72)

,I

~

••

-~

1.1

T~

.-

""47

r-~

70(73)

~
r ~ ~ 111l1l9I

223

en.

Q

~-

~

f:b-

~~

...

-r§ ~1i
'"
i
1
~~

r~

~~
r
v ~

~

32

119) 18

~ , I 71 (74)

..AI
T 7IciI-l.i

+

"'31

VCC-74(77J

;;;;;

231

J"L

~

NC

T !1G-lli

.-

"1

-J Hh~

17111

7675

73(76)

...

:::

(80)(7111

j~~ 72(l5)

256

W-

"'15

-r5 ~1~

****************

0

"1

~-

117116

181 171 161 (51 141 i3I 121 111 (118)(871 (IIIi)(1I51 18411831111211811
11 7 6543218483 11211180797877

111111111 i91
11 10 9

1121

T'1g.

~
~I... 11111131
6111141

~ 5911121

=fr...

...fI r-:l
i

r~
-~
~

~I.
51 51 53
NC

153115411551

5811111

"V...J

571801

:fr

58(59)

~ 55(51)
- 54(57)

(511)

2·125

fMAl( Parameters

f MAX Parameters
The parameter f MAX is the maximum speed at which the PAL
device is guaranteed to operate. Because flexibility inherent to
PAL devices allows a choice of clocked flip-flop designs, for
the convenience of the user. f MAX for the B-speed devices is
specified to address two major classes of synchronous designs.
The simplest type of synchronous c!esign can be described as
a data path application. In this case, data is presented to the
data terminal of the flip-flop and clocked through; no feedback

is employed (Figure 1). Under these conditions, the frequency
of operation is limited by the greater of the data setup time
(tsu> or the minimum clock period (tv, high + tv, low). This
parameter is designated fMAX (no feedback).
.
For synchronous sequential designs, i.e., state machines.
where logical feedback is. required, inputs to flip-flop data
terminals originate from the device input pins of flip-flop
outputs via the internal feedback paths (Figure 2). Under
these conditions, f MAX is defined as the reciprocal of (Isu +
!eLK) and is designated f MAX (feedback).

IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII~ ~ l[; rFigure 1. No Feedback

IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII~ ~ ~ rFigure 2. Feedback

2-126

Monolllhic

W Memories

Waveforms
Output Register PRELOAD
The PRELOAD function allows the register to be loaded from
data placed on the output pins. This feature aids functional
testing of sequential designs by allowing direct setting of
output states. The procedure for PRELOAD is as follows:

PIN 11

VIL~VIH

OUTPUT VIH
REGISTERS VIL

10

IO~.

------_ _-,-_,.-_ _

Series 20PA
1.
2.
3.
4.
5.
6.
7.

Raise Vee to 4.5V.
Disable output registers by setting pin 11 to VIH .
Apply VILIV IH to all registered output pins.
Pulse pin 8 to VP' then back to av.
Remove VILIV IH from all output registers.
Lower pin 11 to VIL to enable the output registers.
Verify for VoLlVoH at all registered output pins.

Series 24RS/24XA
1.
2.
3.
4.
5.
6.
7.

'0

PlNI V I L - - - - - . . . J

PIN 13

Raise Vee to 4.5V.
Disable output registers by setting pin 13 to VIH.
Apply VILIVIH to all registered output pins.
Pulse pin 1a to Vp' then back to av.
Remove VILIV IH from all output registers.
Lower pin 13 to VIL to enable the output registers.
Verify for VOLIVOH at all registered output pins.

~----------------~
VIH

VIL~IO

OUTPUT VIH

.,--------

REGISTERS V I L ·

_ _- , - _ , . - _ - - '

'0

'0

Power-Up RESET
All devices with this PRELOAD feature also have power-up
RESET. All registers power up to a logic high for predictable
system initialization.

PIN 10 V I L - - - - - . . . J

Switching Waveforms
INPUTSI/O
REGISTERED
FEEDBACK

r---~~~~ll/-----------------------------------------3V

~---J'I~~~~r~--------------~------------------------ov

CK

ASYNCHRONOUS
PRESET

COMBINATORIAL
OUTPUTS _ _ _ _ _ _ _ _ _ _

~WKU7

Notes: I. Input pulse amplHude OV to 3.0V.
2. Input access measured at the 1.5V level.

MonoIlthlcWMemorles

2-127

Test Load
Absolute Maximum Ratings
Operating

Programming

Supply voltage Vee ...............................................................................
-O,SV to 7V ................ -O.SV to 12V
Input voltage ..........................................................................•............ .,.1.SV to S.SV ................ -1.0V to 22V
Off-state output voltage .. ....... .. ....... .. ...... .. ....... ............ .. .. .... ... .. ....... ... .. .. . .. .. ... .. .. S.SV .... ...... ... .. .... ... .. . ... 12V
Storage temperature ................................................................................................•.............. -6S·C to + 1S0·C

Switching Test Load

Schematic of Inputs and Outputs
EQUIVALENT INPUT
VCC~----~------~

8 KllNOM

TYPICAL OUTPUT
------------~~VCC

40 II NOM

Rl
OUTPUT o--t----r-@.TESTPOINT

INPUT ~,,-T--;.t--+--

YH--+---o OUTPUT

R2

Notes:

1. tpo is tested with switch S, closed, CL = 50pF and measured at 1.5V output level.
2. tpzx is measured at the 1.5V output level with CL - 50pF. S, is open for high impedance to "I" test, and closed for high impedance to "0" test.
3. tpxz is tested w~h CL = 5pF. S, is open for "I" to high impedance test, measured at VOH -0.5V output level; S, is closed for "0" to high impedance test
measured at VOL

2-128

+ 0.5V output level.

Monolithic WMemorles

MM. PAL@ Device Programmer Reference Guide

Table of Contents
Data 1/0 Corporation
20 Pin Device Families ....................................................... : ...•.•.........3-3
24 Pin and MegaPAL Device Families .................•.•........•........................3~
Dlgelec
20 Pin Device Families ...........•.............•...•.........................................3-5
24 Pin and MegaPAL Device Families .............................•............... ~ .......3-6
Kontron'
" ,20Pin Device .Families •.........•...•..... , ...••.. :'; .....•,. ........•......... ;; ..............3-7
24 Pin and MegaPAL Device Families •.........•................•.............•........ ;,.3-8

, MlcroprOas
20 Pin 'Device Families ............................................................. 1 ••••••••• 3-9
\ 24 Pi~and MegaPAL De,viceFamilies ......•..•.•.................................•..•.. 3·10
Promac
20 Pin Device Families ..............................................................,....... 3-11
" 24, Pin and MegaPAL Device Families .................................................... 3-12
Stag Mlcroaystams
20 Pin Device Families ................................ ;'......... ; ...... :;-.... : .......•..... 3-13
24 Pin and MegaPAL Device Families .........••....•.............•..................... 3·14
Storey Systams
20 Pin Device Families ..................................................................... 3-15
24 Pin and MegaPAL Device Families ................................................... 3-16
Structured Dealgn
" " 20 Pin Device Families ..................................................................... 3-17
24 Pin and MegaPAL DeviCe FamilieS ................................................... 3-18
Valley Data Sciences
20 Pin Device Families.; ........•...•..........•....•.........•..•......................... 3-19
24 Pin and MegaPAL Device Families ........•.....•••.•...................•............ 3~20
Varix
20 Pin Device Families .......•..•..•..•..•.......•.......•............................•.... 3·21
24 .Pin and MegaPAL DeVice Families •.....•....•....................................... 3-22

3·2

Monolithic

m

IIIIemorIes

MM. PAL® Device .Programmer Reference Guide

Data I/O Corporation

20 Pin Device Families

10525 Willows Road N.E.
PO Box 97046
Redmond, WA 98073-9746
(800) 247-5700

Models 19, 29A, 29B
Model 60

Series

Part Number

System

LoglcPak™

Adapter

Family
Code

Model 60

303A

303A-002-V08

22

PAL10H8/-2

18

PAl10L8/-2

Rev. V05

PAl12H6/-2

303A-011A1B-V01

14
Models

PAl14H4/-2

20

19

PAL14L4/-2

15

29A

PAl16H2/-2

22

29B

PAl16L2/-2

16

PAl16C1/-2
Medium 201
2OA/20A-2/41
20B-2/-4
Sl!lndard

21

PAL 16L81 AI-2/-4/B-2/-4

17

PAL 16R81 AI-2/-4/B-2/-4

24

PAL 16R61 AI-2/-4/B-2/-4

~

PAL 16R41 AI-2/-4/B-2/-4
PAl16L8B/D

Medium
20B/0

PAL16R8B/D
PAl16R6B/D
PAL16R4B/D
PAL16L8BP

Medium
20BP
Sl!lndard

Medium 20PA
Programmable
Polarity

303A-V04

Large 20RA
Asynchronous

30

17

1

24

.22

f
17

PAl16R8BP

67

PAl16R6BP
PAl16R4BP

~

PAl16P8A

30

PAl16RP8A

31

i

PAl16RP6A
PAL16RP4A

Large 20
ArHhmetlc

13
19

PAL12L6/-2
Sm.1120/-2
Combinatorial

Pinout
Code

PAl16X4
PAl16A4
PAl16RA8

...

303A

l

24
30

Note: The software and bardware revisions listed are the earliest revisiOns that support these products.

Later SQjtwere and hardware revisions can also be assumed to support these products.

Monolithic mDMemerles

3·3

MMlPAL® Device ,Programmer ,!R.ferenceGuid.

Data I/O

24 Pin and MegaPALTM Device Families
,

:'"

Family
Code

System

LoglcPak™

Adapter

PAL12L10

Model 60

303A

303A-002-VOB

PAL14lS'

Rev. V05

Part Number

Series

'

'x

303A-011 AlB-V01

PAl16L:6

Models

03,

19

04

29A
.i.

05

"

PAL2OC1

4S
:

Medium 24A1
24A-2/B
Standard

PALSL14A'

49

:PAL20LSAI~2/B

26

PAL20RSAI-2/B

27

:

~

PAL20R6A1-2/B
PAL20R4A1-2/B 1
PAL20L10

Medium 24X
Exclu8lve-OR

06

:'

23

PAL20X10

r"

PAL20XS

l

PAL20X4

J~~

303A-V04

PAL20L10A
Medium 24XA
.,Excluslve-OR

PAL20X10A
:

.,,"

f'·'

'pAL20XSA

; 36

"

l

PAL20X4A

..

PAL20S10
Large 24RS
.PAL20RS10
Shared
",pAC20RSS
Product Terms
PAL20RS4
Large 24A
Registered XOR
·Large24/A
Varied XOR
. Large 24RA
Asynchronous
"

"

12

29B

PAL6L16A

Small24A
DeCoder

:'

02
"

PAL1SL4
,PAL20L2

"

01'::

22
'

Small 24
Combinatorial

Pinout
Code

43

t;

..."":

"

PAL22RXSA

.

44

46
7S

303A-011 AlB-YOl

i"':

I,,;

PAL32VX10/A

/1"
!

PAL20RA10
:PAL1OH20PS1

I',·

,

,PAL32R16

',.

303A-V04

..

:

'.

Model29B

','

350Al-23/A1B

NOTE: The software and hardware revisions listed are the earliest revisions that Sl!pport tflese prod!ICIS.
Later, software and _are revisions can also be _mad to·support tflese produc1ll,
.~,

.

'

.'!..'

"

..:

.. '

45:v
..,42.,.

.'

30~A-08a.A/B

303A
!

.:.>

303A-ECL" ,.

,!>~

77

:

303A-002-V08 : •
303A-011A/B-VO.1

303A
:

'lii0i supported on Model 19

I:":'
,!

I:
1

PAL64R32

. ,',.:!

'47

.",.:
"

:
:

··84
"

".

MMI PAL® Device Programmer Reference Guide

Digelec

20 Pin Device Families

1602 Lawrence Ave.
Suite 113
Ocean, NJ 07712
(201) 493-2420
Series

ISystem UP8031
Part Number

FAM 52 Rev.

Adapter

Adapter Rev.

5.4

DA53

A-3

PAL10H8/-2
PAL 10L8/~2
PAL12H6/-2
PAL12L6/-2

Small 20/-2
Combinatorial

PAL14H4/-2
PAL14L4/-2
PAL16H2/-2
PAL16L2/-2
PAL16C1/-2
PAL16L8/A/-2/-4/8-2/-4

Medium 201

20A/20A-2/4!
208-2/-4

PAL16R8/A/-2/-4/8-2/-4

.'

PAL16R6/A/-2/-4/8-2/-4

Standard

PAL16R4/A/-2/ -4/ 8-2/-4
PAL16L88/0
PAL16R88/0

Medium

208/0

PAL16R68/0
PAL16R48/0
PAL16L88P
PAL16R88P

Medium
20BP
Standard

PAL16R68P
PAL16R4BP
5.4

PAL16P8A
PAL16RP8A

Medium 20PA
Programmable
Polarity

Large ~ORA
Asynchronous

.

PAL16X4

'

.

PAL16A4
PAL16RA8
..
revisions

j

j

PAL16RP6A
PAL16RP4A

Large. 20
Arithmetic

OA53

Under

,4,3

j

Dev~lopment

..
l!\Ited are the earliest reVISions that support these products.

NOTE: The software and hardware
La,ter software and hardware revisions can also be assumed to support these products.

Monolithic

W Memories

3-5

MM. 'PAL@Devic'eProgrammer Reference Guide

J?iselec

24 Pin and MegaPALTM Device Families

Series

Part Numbers
PAL12l10
PAL14L8

Small 24
Combinatorial

PAl18L4
"

PAL20C1
Smal124A
'Decoder

PAL6L16A

Adapter Rev.

DA55

C·1

J

, Under Development

PAL8l14A
PAL20L8A1·2/B

Medium 24AI
24A-21B
Standard

Adapter

5.4

I I

PAL16L6

PAL20L2

FAM 52

DA55

5.4

C-1

PAL20R8A1·2/B
PAL20R6A/·2/B
PAL20R4A/·2/B
PAL20L10

Medium 24X
Excluslve-OR

PAL20X10
PAL20X8
PAL20X4

..... ,..

PAL20L10A
Medium 24XA
Exclualve-OR

PAL20X10A

,

PAL20XBA

,

PAL20X4A

q'

PAL20S10
Large 24RS
Shared
Product Terms

PAL20RS10
PAL20RSB
PAL20RS4

Large 24A
Registered XOR
Large.24/A
Varied XOR

PAL22RXBA
"

Large 24RA
Asynchronous

PAL20RA10

ECL
Combinatorial

PAL10H20P8

MegaPALTM,
Devices '

"

,"

"

PAL32VX10IA

~,

.~

'

.:

'0

PAL32R16

"

Und~r, De,<~I~,pr"eht

PAL64R32
.

".;.

NOTE: The sofIware and hardware '811"1008 Ioslad ara the ,earliest revisions that support th~ products.
,
Later sofIwara and hardware revisions can also be assumed to ~upport these products,

"

.MI.PAL@ Device Programmer Reference Guide

Kontron

20 Pin Device Families

1230 Charleston Road
Mountain View, CA94039-7230
(415) 965-7020
Serlei

System MPP-80S
System EPP-80

Part Number

UPM-B'Rev.

Socket Adapter

PAL10H8/·2

SA·27

.

1.44

PAL10L8/·2
PAL12H6/.2
small 201-2
Combinatorial

PAL12L6/·2
PAL14H4/·2

,

PAL14L4/·2

El

..

PAL16H2/·2
PAL16L2/·2
PAL16C1/·2
PAL16L6/A/·214/B·2/.4

Medium 201

PAL16R8/A/·2/ 4/B·2/·4

20A/20A-2/41
20B-2/-4

PAL16R6/A!·2/ 4/B·2/·4

Standard

"

PAL16R4/A!·214/B·2/ 4
PAL16L8B/D

Medium
20B/D

PAL16R8B/D

Under Development

PAL16R6B/D
~

PAL16R4B/O
Medium
20BP
Standard

,.

<,~

~

,.

'"

"

PAL16L8BP

SA·27

PAL16R8BP

Under Development

,J

PAL16R6BP

".

PAL16R4BP

,

".

,

PAL1.6P8A
Medium 20PA
Programmable
Polarity

....

PAL16~P8A

,"

PAL16RP6A

.

','

,

PAL16RP4A
PAL16X4

Large 20
Arithmetic
Large20RA
Aayflchronou.

'.

,

''c'

'.

pAL16RA8

..
NOTE: The software and hardware revISIOns listed are the earl,est

..

";

PAL16A4

-,'

"'".

,

1.47

...
tevISIOns that support these products.

Later software and hardware revisions can also be assun'iad

to, support these po:oducts.: .

3-1

MMI PAL® Device Programmer Reference Guide

Kontron
Series

24 Pin and MegaPALTM Device Families

Socket Adapter

Part Number
PAL12L10

UPM-B Rev.
1.44

PAL14L8
Small 24
Combinatorial

PAL16L6

SA·27·1

1

PAL18L4
PAL20L2
PAL20C1

Smal124A
Decoder

PAL6L16A

PAL20L8A/·2/B

Medium 24A1
24A-2/B
Standard

Under Development

1.48

SA·27·1

1.44

PAL8L14A

PAL20R8A1·2/B
PAL20R6A1·2/B
PAL20R4A1·2/B
PAL20L10

Medium 24X
Excluslve-oR

PAL20X10
PAL20X8
PAL20X4
PAL20L10A

Medium 24XA
Excluslve-oR

PAL20X10A
PAL20X8A
PAL20X4A
PAL20S10

Large 24RS
Shared
Product Terms

Under Development

PAL20RS10
PAL20RS8
PAL20RS4

Large 24A
Registered XOR
Large 24/A
Varied XOR

PAL22RX8A

Under Development

PAL32VX10/A

1.48

Large 24RA
Asynchronous

PAL20RA10

1.44

ECL
Combinatorial

PAL10H20P8

1.47

MegaPALTM

PAL32R16

Devices

PAL64R32
..

Under Development

..

NOTE: The software and hardware revIsions listed are the ea~lest reVISions that support these products.
Later software and hardware revisions can also be assumed to support these products.

a..8

MonoIlthlcW Memories

MM. PAL ®Device Programmer Reference Guide

Micropross

20 Pin Device Families

Pare d' aetivite des Pres
5, rue Denis-Papin
59650 Villeneuve-d' Aseq
Tel 20479040
Series

ROM 5000
Programmer

Part Number

Rev.

PAL10H8/-2

3.5

PAL10L8/,2
PAL12H6/-2
Small 201-2
Combinatorial

PAL12L6/-2
PAL14H4/·2
PAL14L4/-2
PAL16H2/-2
PAL16L2/-2
PAL16C1/-2

Medium 201
20Al20A-2/41

20B-2/-4
Standard

PAL 16L8/A/-2/ -4/B-2/-4
PAL16R8/A/-2/-4/B-2/-4
PAL 16R6/A/-2/-4/B-2/-4
PAL16R4/A/-2/-4/B-2/-4
PAL16L8B/D

Medium
20B/0

PAL16.R8B/D
PAL16R6B/D
PAL16R4B/D
PAL16L8BP

Medium
20BP
Standard

PAL16.R8BP
PAL16R6BP
PAL16R4BP
PAL16P8A

Medium 20PA
Programmable
Polarity

PAL16RP8A
PAL16RP6A
PAL16RP4A

Large 20
Arithmetic
Large 20RA
Asynchronous

PAL16X4

c

PAL16A4
PAL16RA8

Under Development

..
reVISions

NOTE: The software and hardware
listed are the earliest reVI$lons that support these products.
Later software and hardware revisions can also be assumed to support these products.

Monolithic

W Memories

3-9

..... PAL ® Device Programmer Reference Guide

Micropross
Series

24 Pin and MegaPALTM Device Families

Rev.

Part Number
PAL12L10

3.5

PAL14L8
Small 24
Combinatorial

PAL16L6

1

PAL18L4
PAL20L2
PAL20C1

Small24A
Decoder

PAL6L16A

Under Development

PAL8L14A
3.5

PAL20L8A1-2/B
Medium 24A1
24A-2/B
Standard

PAL20R8A1-2/B
PAL20R6A/-2/B
PAL20R4A1-2/B
PAL20L10

Medium 24X
Exclusive-oR

PAL20X10
PAL20X8
PAL20X4
PAL20L10A

Medium 24XA
Exclusive-OR

PAL20X10A
PAL20X8A
PAL20X4A
PAL20S10

Large 24RS
Shared
Product Terms

PAL20RS10
PAL20RS8
PAL20RS4

Large 24A
Registered XOR
Large 241A Varied
XOR

PAL22RX8A
PAL32VX10/A

Large 24RA
Asynchronous

PAL20RA10

ECl Combinatorial

PAL10H20P8

MegaPAlTM
Devices

.'

PAL32R16

Under Developm",nt

PAL64R32

NOTE: The software and hardware revisions listed are the earliest rsvisions that support thase products.
Later software and hardware revisions can also be assumed to support thase products.

3-10

,

MonoIlthlcWMemor/ea

MMI PAL@ Device Programmer Reference Guide

Promac

20 Pin Device Families

Adams MacDonald Enterprises, Inc.
Promac P3

2999 Monterey/Salinas Highway
Monterey, CA 93940
(408) 373-3607
Series

Programmer

Part Number
PAL10H8/-2

Small 20/-2
Combinatorial

Medium 20/
. 20A/20A-2/ 4/
208-2/-4
Standard

Medium
20B/0

Medium
20BP
Standard

Medium 20PA
Programmable
Polarity

Software Rev.
3.0

Large 20RA
Asynchronous

011

PAL10L8/-2

0/6

PAL12H6/-2

0/2

PAL12L6/-2

0/7

PAL14H4/-2

0/3

PAL14L4/-2

0/8

PAL16H2/-2

0/4

PAL16L2/-2

0/9

PAL16Cl/-2

0/5

PAL 16L81 A/-2/-4/B-2/-4

0/10

PAL l6R81 A/-2/-4/B-2/-4

0/11

PAL 16R61A/-2/-4/B-2/-4

0/12

PAL 16R41 A/-2/-4/B-2/-4

0/13

PAL16L8B/D

5/0

PAL16R8B/D

5/1

PAL16R6B/D

5/2

PAL16R4B/D

5/3

PAL16L8BP

0/10

PAL16RBBP

0/11

PAL16R6BP

0/12

PAL16R4BP

0/13

PAL16PBA

1/0

PAL16RPBA

1/3

.PAL16RP6A

1/2
1/1

PAL16RP4A
Large 20
Arithmetic

Sl/S2

PAL16X4

0/14

PAL16A4

0/15
1/12

PAL16RAB
..
earliest reVISions that

NOTE: The software and hardware reVISionS listed are the
support these products .
Later software and hardware revisions can also be assumed to support these products.

MonoIlthlcWMemorles

3-11

MM. PAL ® Device PrograllJlIJer Reference Guide

Promac

24 Pin and MegaPALTM Device Familie$

Series

Part Number
PAL12L10

Software Rev.

S1/S2

3.0

2/2
2/3

PAL14LB
Small 24
Combinatorial

PAL16L6

2/4

PAL1BL4

2/5

PAL20L2

2/6
2/1

PAL20C1

Smali 24A
Decoder

Medium 24A1
24A-2/B
Standard

Medium 24X
Exclusive-OR

Medium 24XA
Exclusive-OR

large 24RS
Shared
Product Terms
Large 24A
Registered XOR

PAL6L16A

31t1

PAL8L14A

3/10

PAL20L8A1-2/B

2/8

PAL20RBA/-2/B

2/9

PAL20R6A1-2/B

2/10

PAL20R4A1-2/B

2/11

PAL20L10

2/7

PAL20X10

2/12

PAL20X8

2/13

PAL20X4

2/14

F'AL20L1OA

217

PAL20X10A

2/15

PAL20X8A

3/0

PAL20X4A

3/1

PAL20S10

3/5

PAL20RS10

3/6

pAL20RS8

3/7

PAL20RS4

3/8

PAL22RX8A

Under Development

~

Ie

Large 24/A
Varied XOR

PAL32VX10/A

e

Large 24RA
Asynchronous

PAL20RA10

3M

ECl
Combinatorial

PAL10H20PB

Undf;lr Df;lvelopment

MegaPAlTM
Devices

PAL32R16

Under Development
PAL64R32

..

..

NOTE: The software and hardware reVISions listed are the earliest reVISions that support these products .
Later software and hardware revisions can also be assumed to support these products.

3-12

Monolithic WMemor/es

MMI PAL® Device Programmer Reference Guide

Stag Microsystems

20 Pin Device Families

FI

1600 Wyatt Dr. Suite 3
Santa Clara, CA 95054
(408) 988-1118
Series

Small 20/-2
Combinatorial

Medium 20/
20Al20A-2/41
20B-2/-4
Standard

Medium
20B/0

Medium
20BP
Standard

Medium 20PA
Programmable
Polarity
Large 20
Arithmetic
Large 20RA
Asynchronous

~

Code

ZL30 Rev.

ZM2200

PAL10H8/-2

20-20

30-35

14

PAL10L8/-2

20-25

30-39

12

Part Number

PAL12H6/-2

20-21

PAL12L6/-2

20-26

PAL14H4/-2

20-22

PAL14L4/-2

20-27

PAL16H2/-2

20-23

PAL16L2/-2

20-28

pAL16C1/-2

20-24

PAL 16L8/A/-2/ -4/B-2/-4

20-29

PAL 16R8!A/-2/-4/B-2/-4

20-30

PAL 16R6/A/-2/-4/B-2/-4

20-31

PAL 16R4/A-2/ -4/B-2/-4

20-32

PAL16L8B/D

22-29

PAL16R8B/D

22-30

PAL16R68/D

22-31

PAL16R4B/D

22-32

PAL16L8BP

20-29

PAL16R8BP

20-30

PAL16R6BP

20-31

PAL16R4BP

20-32

~

PAL16P8A

20-38

12

PAL16RP8A

20-1.1

PAL16RP6A

20-12

PAL16RP4A

20-13

PAL16X4

20-33

PAL16A4

20-34

PAL16RA8

20-19

1

1

30-35

14.
19

,

..

1

,

14

30-37

12

NOTE: The software and hardware reVISions Usted are the earilest reviSIons that support these products.
Later software and hardware revisions can also be assumed to support these products.

Monolithic

W lIItemories

3·13

MM. PAL ® Device Programmer Reference Guide

Stag Microsystems
Series

Small 24
Combinatorial

Small24A
Decoder

Medium 24A1
24A·2/B
Standard

Medium 24X
Exclusive·OR

Medium 24XA
Excluslve-oR

large 24RS
Shared
Product Terms
Large 24A
Registered XOR
Large 24/A
Varied XOR

Part Number

Code

Zl30 Rev.

PAL12L10

21·50

30·35

PAL14L8

21·51

PAL16L6

21·52

PAL18L4

21·53

PAl20L2

21·54

PAL20C1

21·55

j

14
12

1

Under Development

PAL8L14A
PAL20L8A1·2/B

21·56

PAL20R8A1·2/B

21·57

PAL20R6A1·2/B

21·58

PAL20R4A1·2/B

21·59

PAL20L10

21·60

PAL20X10

21·61

PAL20X8

21·62

PAL20X4

21·63

PAL20L10A

21·60

PAL20X10A

21·61

PAL20X8A

21·62

PAL20X4A

21·63

P~L20S10

21·81

PAL20RS10

21·80
21·79

PAL20RS4

21·78

PAL22RX8A

PAL10H20P8

1

Under Development

~

PAL32VX10/A

ECl
Combinatorial

30·35

30·39

PAL20RS8

PAL20RA10

21·77

30·37

Under Development

PAL32R16
PAL64R32

Under Development

, ,

NOTE. The software and hardware revtSlons listed are the earhest reviSions that support these products.
Later software and hardware revisions can also be assumed to support these products.

3-14

ZM2200

PAL6L16A

Large 24RA
Asynchronous

MegaPAlTM
Devices

24 Pin and MegaPALTM Device Families

Monolithic W.emor/es

12

MMI PAL ® Device Programmer Reference Guide

Storey Systems

20 Pin Device Families

3201 North Hwy. 67
Suite H
Mesquite, TX 75150
(214) 270-4135
Series

P240

Programmer
Part Number

Rev.

PAL10HS/-2

2.0

PAL10LS/-2
PAL12H6/-2
.Small 20/-2
Combinatorial

PAL12L6/-2
PAL14H4/-2
PAL14L4/-2
PAL16H2/-2
PAL16L2/-2
PAL16C1/-2

Medium 201
20Al20A-2/4/
20B-2/-4
Standard

PAL16LS/A/-2/-4/B-2/-4
PAL 16RS/A/-2/-4/B-2/-4
PAL 16R6/A/-2/-4/B-2/-4
PAL16R4/A/-2/ -4/B-2/-4

Medium
20B/0

PAL16LSB/D

4.0

PAL16RSB/D

1

PAL16R6B/D
PAL16R4B/D
PAL16LSBP

Medium
20BP
Standard

2.0

PAL16RSBP
..UnderDevelopment

PAL16R6BP
PAL16R4BP

Medium 20PA
Programmable
Polarity

PAL16PSA

4.0

PAL16RPSA

1

PAL16RP6A
PAL16RP4A

Large 20
Arithmetic
Large ..20RA
Asynchronous

PAL16X4

2.0

PAL16A4

:

4;04

PAL16RAS

..

NOTE: The software and hardware revISions listed ars the earliest r""'Slons that support these products.
Later software and hardware revisions can also be assumed to support these products.

Monolithic WMemorles

3-15

MMI PAL ® Device Programmer Reference Guide

Storey Systems
Series

24 Pin and MegaPALTM Device Families

Part Number

Rev.
2.0

PAL12L10
PAL14L8
Small 24
Combinatorial

PAL16L6

1

PAL18L4
PAL20L2
PAL20C1

Small24A
Decoder

PAL6L16A
Under Development

PAL8L14A
PAL20L8A1·2/B

Medium 24A1
24A-2/B
Standard

2.0

PAL20R8A/·2/B
PAL20R6A/·2/B
PAL20R4A1·2/B
PAL20L10

Medium 24X
Exclusive-OR

PAL20X10
PAL20X8
PAL20X4
PAL20L10A

Medium 24XA
Exclusive-OR

PAL20X10A

Under Development

PAL20X8A
PAL20X4A
PAL20S10

Large 24RS
Shared
Product Terms

PAL20RS10
PAL20RS8
PAL20RS4

Large 24A
Registered XOR

PAL22RX8Aa

Large 241 A Varied
XOR

PAL32VX10/A

Large 24RA
Asynchronous

PAL20RA10

EcL Combinatorial

PAL10H20P8

MegaPALTM
Devices

4.04

PAL32R16

Under Development

PAL64R32
..

NOTE: The software and hardware reVISions listed are the earliest reVISions that support these products.
Later software and hardware revisions can also be assumed to support these products.

3-16

Monolithic WMemories

MMI PAL ® Device Programmer Reference Guide

Structured Design

20 Pin Device Families

1700 Wyatt Drive
Suite 7
Santa Clara, CA 95054
(408) 988-0725
Series

SD 20/24 System
SD 1000 System

Part Number

SO 20/24

SO 1000

1.6

1.05

PAL10H8/-2
PAL10L8/-2
PAL12H6/-2
PAL12L6/-2
Small 20/-2
Combinatorial

PAL14H4/-2

El

PAL14L4/-2
PAL16H2/-2
PAL 16L2/-2
PAL16C1/-2
Medium 201
20Al20A-2/41
20B-2/-4
Standard

PAL16L81 A/-2/-4/B-2/-4
PAL16R81 A/-2/-4/B-2/-4
PAL 16R61 A/-2/-4/B-2/-4
PAL16R41 A/-2/-4/B-2/-4
PAL16L8B/D

Medium
20B/0

PALt6R8B/D

Under Development

PAL16R6B/D
PAL16R4B/D
PAL16L8BP

Medium
20BP
Standard

1.6

1.05

PAL16R8BP
PAL16R6BP
PAL16R4BP

Under Development

PAL16P8A
Medium 20PA
Programmable
Polarity

PAL16RP8A
PAL16RP6A
PAL16RP4A

Large 20
Arithmetic
Large 20RA
Asynchronous

PAL16X4
1.6

PAL16A4
PAL16RA8
..
reVISions

1.05
Under Development

..
listed are the earliest reVISions that support these products•

..

NOTE: The software and hardware
Later software and hardware revisions ,can also be assumed to support these products.

Monolithic

W Memories

3-17

MMI PAL® Device Programmer Reference Guide

StruCfturedDesign
Series

24 Pin and MegaPAL™Oevic.e Families

Part Number
PAL12L10
PAL 14L8

Small 24
Combinatorial

SD 20/24

SD 1000

1.6

1.05

j

PAL16L6
PAL18L4
PAL20L2

j

PAL20C1
Smal124A
Decoder

PAL6L16A
Under Development

PAL8L14A
PAL20L8A1·2/B

Medium 24A1
24A-2/B
Standard

1.05

1.6

PAL20R8A1·2/B
PAL20R6A1·2/B
PAL20R4A/·2/B
PAL20L 10

Medium 24X
Exclusive-OR

PAL20X10
PAL20X8
PAL20X4
PAL20L10A

Medium 24XA
Exclusive-OR

PAL20X10A

.,'

PAL20X8A

r

PAL20X4A
PAL20S10
Large 24RS
Shared
Product Terms

PAL20RS10

Under Development

.

PAL20RS8
PAL20RS4

Large 24A
Registered XOR
Large 24/A
Varied XOR

PAL22RX8A
PAL32VX10/A

Large 24RA
Asynchronous

PAL20RA10

E.Cl
Combinatorial

PAL10H20P8

MegaPAlTM
Devices'"

PAL32R16
PAL64R32
..

..

NOTE. The software and hardware revISIOns listed are the earliest reVISions that support these products.
Later sciftWare and hardware revisions can also
assumed to support, these ,product's.

be

3-18

MonoIlthlcWMemor/es

MMI PAL ® Device Programmer Reference Guide

Valley Data Sciences

20 Pin Device Families

160 Series

Charleston Business Park
2426 Charleston Road
Mountain View, CA 94043
(415) 968-2900
Series

Programmer

Part Number

Rev.
1.03

PAL10HS/-2
PAL10LS/·2
PAL12H6/·2
Small 20/-2
Combinatorial

PAL12L6/-2
PAL14H4/-2
PAL14L4/-2
PAL16H2/-2
PAL16L2/-2
PAL16C1/-2
PAL16LS/A/-2/-4/B-2/-4

Medium 201

20A/20A-2/41
20B·2/·4
Standard

PAL16RS/A/-2/-4/B-2/-4
PAL16R6/A/-2/-4/B-2/-4
PAL16R4/A/-2/-4/B-2/-4
PAL16LSB/D

Medium
20B/0

PAL16RSB/D
PAL16R6B/D
PAL16R4B/D
PAL16LSBP

Medium
20BP
Standard

PAL16RSBP
Under Development

PAL16R6BP
PAL16R4BP

1.03

PAL16PSA
Medium 20PA
Programmable
Polarity

PAL16RPSA
PAL16RP6A

1

PAL16RP4A
Large 20
Arithmetic
Large 20RA
Asynchronous

PAL16X4
PAL16A4

Under Development

PAL16RAS

NOTE: The software and hardware revisions listed are the earliest revisions that support these ,products.
Later software and hardware revisions can also be assumed to support these products.

MonoIlthlcWMemories

3-19

MM. PAL@ Device Programmer Reference Guide

Valley Data Sciences
Series

24 Pin and MegaPALTM Device Families

Part Number

Rev.

PAl12l10

1.03

PAl14L8
Small 24
Combinatorial

PAl16L6

1

PAl18L4
PAL20L2
PAL20C1

Small24A
Decoder

PAL6l16A

Under Development

PAL8l14A
PAL20L8AI ·2/8

Medium 24A1
24A-2/B
Standard

1.03

PAL20R8A1·2/8
PAL20R6AI -2/8
PAL20R4A/-2/8
PAL20X10

Medium 24X
Exclusive-OR

PAL20l10
PAL20X8
PAL20X4
PAL20X10A

Medium 24XA
Exclusive-OR

PAL20L10A
PAL20X8A
PAL20X4A
PAL20RS10

Large 24RS
Shared
Product Terms

PAL20S10
PAL20RS8
PAL20RS4

Large 24A
Reglstllred XOR
Large 241A Varied
XOR

PAL22RX8A
PAL32VX10/A

Large 24RA
Asynchronous

PAL20RA10

ECL
Combinatorial

PAl10H20P8

MegaPALTM
Devices

....
PAL32A16

Under Development
....

PAL64A32

NOTE. The software and hardware reviSions hsted- are the earliest revuuons that support these products.
Later software and hardware'revisions can also be assumed to -support these products.

3-20

1.04 -I: 1.1 Adapter
Under Development

MonoIlthlcWMemor/es

..

MM. PAL@ Device Programmer Reference Guide

Varix

20 Pin Device Families

OMNI

1210 E. Campbell Road
Richardson, TX 75081
(214) 437-0777
Series

Programmer
Part Number

Rev.
3.18

PAL10H8/-2
PAL 10L8/-2
PAL12H6/-2
Small 20/-2
Combinatorial

PAL 12L6/-2
PAL14H4/-2
PAL 14L4/-2
PAL16H2/-2
PAL16L2/-2
PAL16C1/-2

Medium 201
20A/20A-2141
20B-2/-4
Standard

PAL16L81 A/-21 -4/B-2/-4
PAL16R81 A/-21 -4/B-2/-4
PAL 16R61A/-2/-4/B-2/-4
PAL16R41 A/-2/-4/B-2/-4
PAL16L8B/D

Medium
20B/D

PAL16R8B/D
PAL16R6B/D
PAL16R4B/D

Medium
20BP
Standard

PAL16t..8BP

3.18

PAL16R8BP

5.00

PAL16R6BP

~

PAL16R4BP

3.18,

PAL16P8A
Medium 20PA
Programmable
Polarity

PAL16AP8A
PAL16RP6A
PAL16RP4A

Large 20
Arithmetic
Large 20RA
Asynchronous

,

1

PAL16X4
PAL16A4

Under Development

PAL16RA8

NOTE: The software and hardware revisions listed afe the earliest revisions that support these products.
Later software and hardware revisions can also be assumed to support these products.

Monolithic WMemorles

3-21

MMIPAL® Device Programm.r Reference Guide

Varix

24 Pin and MegaPALTM Device Families

Series

Rev.

Part Number
PAL12L10

3.18

PAL14L8
Small 24
Combinatorial

PAL16L6
PAL18L4
PAL20L2
PAL20C1

Smal124A
Decoder

PAL6116A
PAL8L14A
PAL20L8A1·2/S

Medium 24A1
24A-2/B
Standard

PAL20R8A/·2/S
PAL20R6A1·2/S
PAl20R4A1·2/S
PAL20L10

Medium 24X
Exclusive-oR

PAL20Xl0
PAL20X8
PAl20X4
PAL20Ll0A

Medium 24XA
Exclusive-oR

PAL20Xl0A
PAL20X8A

.

PAL20X4A
PAL20S10
Large 24RS
Shared
Product Terms

Under Development

PAL20RS10
PAL20RS8
PAL20RS4

Large 24A
Registered XOR
Large 24/A
Varied XOR

PAL22RX8A
PAL32VX10/A

Large.24RA
Asynchronous

PAL20RA10

ECl
Combinatorial

PAL10H20P8

MegaPALTM
Devices

3.18

Under Development

PAL32R16
PAL64R32

..

NOTE: The software and hardware reviSions listed are the earliest revisions that support these products.
later software and hardware revisions can also be assumed to support these products.

3-22

Monolithic WMemor/es

HAL ® /ZHAL™ Devices

Table of Contents
HAL/ZHAL Devices
ProPAL,TM HAL and ZHAL Devices: The Logical Solutions for Programmable
Logic ................................................................................................4-3
ZHAL20A Series ZHAL64R32 -

ZHAL24A Series -

4-2

Zero Power CMOS Hard Array Logic

Zero Power CMOS Hard Array Logic

.......................... .4-7

................................ 4-15

Zero Power CMOS Hard Array Logic

Monolithic W.emor/es

......................... 4-24

ProPAL™, HAL®, and ZHAL™ Devices:
The Logical Solutions for Volume Programmable Logic

So you have discovered the convenience and flexibility of
designing with PAL® devices from Monolithic Memories. You
have implemented a design using PAL devices, and taken that
design into production. Now may be the time to consider ways
of reducing the efforts you put into programming, testing, and
marking large volumes of PAL devices. Wouldn't it be more
convenient if you could be relieved of the duties and costs of
volume programming and testing and still reap the benefits
afforded by programmable logic?
Or perhaps you are considering a semicustom product, but
you're a little nervous about going to a gate array. Wouldn't it
be preferable if you could find a semicustom product which
allows easy; inexpensive prototyping, provides fast prototype
turnaround, comes fully tested, can have a custom marking,
has low NRE charges, provides design flexibility, and has an
assured second source?
Well, Monolithic Memories, the inventor of the PAL device,
offers the logical solutions. ProPAL, HAL, and ZHAL devices
make the transition from user-programmed devices to customized production-ready devices easy and risk free.

ProPAL Devices
ProPAL (Programmed CPAL) devices are simply PAL devices
that MOnolithic Memories programs and tests for you. CYou
receive a fully functional unit without having to do the programming and testing. But you still have the flexibility to
handle design changes easily.

COO,,""

HAL Devices
HAL (Hard Array Logic) devices areCto PAL devices as ROMs
are to PROMs. Instead of fuses in the logic array; your pattern
is implemented using metal links that are masked in during
wafer fabrication. So your need to program devices iseliminated. And because the devices have their functionality masked
in, Monolithic Memories can provide full functional testing
befor~cshipping the product. You can place the devices in your
boards with a minimum of handling and the highest level of
confidence.
Monolithic Memories offers a HAL device fOr every PAL
device. Any PAL device design you program can be imple-

mented in a HAL version, allowing you to move smoothly into
volume production.
'

CD0100qM

ZHAL Devices
Monolithic Memories now provides a third alternative for the
programmable logic user: new Zero-Standby-Power CMOS
HAL devices.
For the first time there are HAL devices which can implement
any pattern from the Series 20 and Series 24 pAL devices
with the greatly reduced power consumption only CMOS can
offer.
For high complexity designs reaching into the ,thousands of
gates, Zero Power MegaHALTM deVices provide the natural
semicustom VLSI alternative to gate arrays. The MegaPAL™
devices provide the flexibility and fast design turn-around you
need for prototyping. Once you are ready for production, the
CMOS MegaHAL devices provide the same functionality with
Zero Power.
All of the ZHAL devices are fully HC/HCT compatible, making
them easy to use in TTL ,and CIVIOS environments.

Should You Use a PAL, ProPAL, or HAL
Device?
PAL devices offer the flexibility and convenience needed for
prototyping your innovative designs. They provide a means for
designing an efficient system by integrating functions and
saving you board space. For flexible production, it makes
sense to program and test your own PAL devices. This is
especially true if you neec;! low volumes per pattern. You
always have the option of making last minute des.ign tweaks
as you fine tune your system design.,
Once,your production volumes reach amoderat!ilvolume of a
fEllw thousand devi~s peryear for each pattern, you may wish
to dedicate your production resources to Cnewer: designs,
instead of programming and'testing production,volume(\. Yet
in order to be able to make quick design updates,.you might
not want to commit to a J:iAL mask. Pro PAL devices provide
the ideal solution by eliminating programming and testing
needs while retaining enough flexibility to accomn,odate, design changes.
'c
'
,
When you feel th.at your design has st!!bilized and, your
Volume has ramped up to sEllveral thou(land devices per year,
a HAL device becomes tlW m9st' costeffecth!eway to
purchase your programmable logic. By shifting the burdens to
Monolithic Memories, whocM' 'handle large vcilumes easily,
you can concentrate your errergies on more productiveprojects.

How Does MMI Do This?
Monolithic Memories takes' your, proven PAL device tlesign
and e,ither arranges to program ProPAL devices in yOlume; or
generates a custom mask' for a,HALor ZHAL device:~nd all

MonoilthlcW Memories

4-3

ProPALT~, HAL®, and ZHAL™ Devices:
The Logical Solutions for Volume Programmable Logic

without the normal risks inherent in purchasing a semicustom
product. Why? Secause:
• You can prototype your system and initiate production using
standard Monolithic Memories PAL devices. You don't have
to worry about making a mistake that could put your design
schedule in jeopardy.
• The nominal Non-Recurring Engineering (NRE) charges for
ProPAL and HAL devices are far lower than those normally
required for a semicustom qircl.lit. And they can even be
amortized over your first producti9n quantity.
Unit
Volume

/

HAL device

ProPAL device

PAL device

Monolithic Memories
Programmable
Solutions

• You save on the costs of programming devices. This will
also shorten your production cycle, since you can plug the
devices into the socket with no additional processing.
• All of the devices are tested for full functionality before they
leave Monolithic Memories. You save on the costs of
testing and generating test programs.
• Monolithic Memories 'is geared towards providing volumes
of high quality devices. No' one knows how to test
programmable logic as well as Monolithic Memories.
Between" the thorough, efficient testing and marking
capabilities and the option to provide bum-in for extra
reliability, ·you can obtain a higher quality device that if you
did thepr6gramming and testing yourself,
• MMI cah provide' custom marking. This saves you the
added expense of stripping ·the mark from standard devices
and then remarking them with your own mark.
• HAL devices are secure by design. If you prefer ProPAL
devices, they can also be secured for you at the factory.
• ProPAL device lead time is only 1 t6 2 weeks longer than
thatof unprogrammed PAL devices.
• HAL device turn-around time. is a mere 6 to 8 weeks or less
from acceptance of your design package to receipt of first
units.
"Floppy disks are accepted in standard DEC@ AT-II (RXOI) or RSX·IIM@,
files II format, or an IBM pcTM 5-1/4 in. disket1e. IBM' compatible (SOO or 1600
BPI) nipe track magnetic tapes are accepted in unlabeled (card image), files· I I,
or VAY. VMS@ backup formal If magnetic media absolutely cannot be provided,
legible printouts (signed and dated) from PALASM will be accepted. Please note
that magnetic media are required if you have more than 50 vectors.

• If you find yourself with an unexpected demand, you need
not turn away business for lack of HAL device .stock. You
can always use ProPAL devices to make up for any
temporary shortfall.

HOw Can You Tak~ Advantage of This?
The following are some guidelines which you can use to help
convert your designs to ProPAL, HAL or ZHAL devices.
1. Send In Your Design
You will need to provide your logic equations from either
PALASM@; PALASM 2 or ABELTM on magnetic media'.
When Monolithic Memories generates vectors for use in
functionally testing your pattern, "seed" vectors are helpful ,in
providing the foundation upon which the final test vectors will
be based.
A master PAL' device containing your design is needed for
Monolithic Memories to verify that the pattern you submitted
has been correctly processed. If you cannot provide a Monolithic Memories master PAL device, Monolithic Memories will
accept your design inputs and provide ProPAL samples for
your approval.
For your convenience, a checklist is included to help you
prepare all of the necessary materials to be submitted to
Monolithic Memories. This will also help Monolithic Memories
process your design, resulting in smoother and faster turnaround. Copies of this form are available from your Sales
Representative, or you can simply copy the attached form.
2. MMI Will Verify the Design
Upon receiving your design package, Monolithic Memories will
enter your design into their computer and verify that there are
no format or syntax problems. A fuse map will be generated,
and sample Pro PAL devices programmed.
If any questions are encountered at this stage, they will be.
resolvlild with you before any further processing takes place.
3. MMI Will Check the Samples
If you have approved immediate production of your devices,
Monolithic Memories will make a fuse for fuse comparison
between the samples and the master device you provide. If
there are no discrepancies, test generation will be started
immediately (or upon receipt of your purchase order).
If you prefer to see programmed sample ProPAL devices prior
to initiating production, Monolithic Memories can provide them
for your approval before proceeding further. Sample approval
is also needed when no master devices are provided or when
a discrepancy is found during verification.
4. MMI Will Generate Test Vectors
A functional test sequence is generated using TGENTM, a
proprietary software package. Any seed vectors you provide
will be used to help initiate test generation. TGEN will check
for hazards and race conditions, monitor fault coverage and
systematically add vectors until test coverage goals are met.
Monolithic Memories has a test quality standard that sets as a
minimum goal 90% coverage of all stuck-at faults. Lower
coverage patterns can sometimes be processed as HAL
devices, or it is possible to handle them as ProPAL devices
only, but your approval will be needed. If acceptable coverage
cannot be obtained, ways of increasing the testability of the
deSign may have to be considered before· Monolithic Memories can process the pattern.

d

4·4

MonoIlthlcWMemories

ProPAL™,HAL@, and ZHAL™ Devices:
The Logical Solutio'" for Volume Programmable Logic
For more detail on exactly how the test coverage is determined, refer to the article "PAL Design Function and Test
Vectoni" in this Handbook.
When suitable test coverage is obtained, as is normally the
case, there is no need for you to be involved with vector
generation. If, however, you wish to approve the test vectors
before Production units are generated, the vectors will. be
made available to you.
5. MMI Will Generate Productlon Unlta
After an acceptable test sequence has been generated,
Monolithic. Memories will generate the aPpropriate" HAL or
2;HAL mask and build the devic9s. Or, in the case of a ProPAL
del/ice, Mbnolithic Memories will arrange to program' and tast
blank units.
.

HAL AND
ProPALDEVICE
GENERATION FLOW

iF ~PLI' VERIFICATION
REQUESTED

Having' Your 'Devlces Marked
The standard Monolithic Memories· mark consists of the de·
vice type, the package type, the date code, and, the Monolithic
MeniOrles logo.
If you wiSh, you Can have the standard marking replaced by a
custom marking. The logO and date' code arestaridard,·but
any othel' markings can be as you ~re. The character and
line IImita.lions for the most common packages are in Table' 1.
If the package you want is not listed, your local representative
can heip you determine the guidelines you need.
'

Whom

to Contact

When. you are. ready to put. the power of· the Monoli,thic
Memories factory to work for you, just contact YOUr' local
Monolithic Memories sales rapresentative. And .let Monolithic
Memories take care of your ProdUction prOgramming, testing,'
and marking needs.

P~fe
',,':

. 20 pin (300 mil) 2 Iin\ils/13 characters per line
24 pin (300 mil) 2 1in8s/17 charactera per line

20 pin (300 miQ 21ines/16 char:aeters.per,line.24

PLCC

pin (300 mil) 2...I!nes/1.7 ch.raqlers.perllne

20 lead

41ines/11 characterS per line

28 lead

5 Hnesl12 charactets per line
Tllble 1

PAL.. HALanct PALASM.are regIstefad lraderiiarIcs of Mo'n\:>QtI)jC.M~OIieS, Inc.
ProPAt.. ~L, MegaPAL, MegaHAL anct TGEN are lrilderIiart Vee •..............•.................... ·· .•.•.•. .;····· ..........•............................................................................ +20mA
Output diode current, 10K:
Vo < 0 ...............................................................................................................................................-20mA
Vo > Vee· ......................... · .. ··:·····.············· ......................... ; ........•..' .................................................. +20mA
Storage temperature .....................................................................................................................-65°C to 150°C

Operating Conditions
INDUSTRIAL
SYMBOL

COMMERCIAL
UNIT

PARAMETER
MIN

TYP

MAX

MIN

5.5

4.75

TYP

MAX

5

5.25

V

Vee

Supply voltage

4.5

5

Iw

Width of clock

15

10

15

10

ns

tou

Setup time from input or
feedback to clock

20

13

20

13

ns

0

-10

0

25

16R4A, 16R6A, 16R8A,
16RP4A, 16RP6A,
16RP8A

th

Hold time

0

tA

Operating free-air temperature

.,.40

Electrical Characteristics
SYMBOL

TEST CONDITIONS

PARAMETER
Low-level input voltage

VIH 1

High-level input voltage

IlL

Low-level input current

IIH

High-level
input current

Low-level output voltage

VOH

High-level output voltage

VI

= GND

Vee = MAX

VI

= GND

Vee
Vee

= MIN
= 5V

ns
75

?C

Vee

= 5V

Off-state output current

Vee

= MAX

Standby supply currentS

10

V

-1

jJA

10

jJA

1

jJA

1

3.763
4.95

Operating supply current

f

Vo

Monolithic

Vee

10H =' -1jJA

= GND
= Vee

= GND or Vee
10 = OmA, VI = GND

VI

W Memories

or Vee

UNIT

2

= SmA
= 1jJA
IOH = -6mA

Vo

MAX
0.8

0.1

V

0.4
V
0.05

10L

Vee = MIN

= OmA,
= 1MHz,

TYP

0

10L

IOZH4

4-10

85

MIN

= MAX

Vee

IPinS:!
IAll other pins

VOL

lee

25

Over Operating Conditions

VIL l

IOZL4

-10

4.1
V
0

-10

jJA

0

10

jJA

0

100

jJA

2

56

mA

Zero Power CMOS Hard Array Logic
ZHAL™ 20A Serle.

Switching Characteristics
SYMBOL

Over Operating Conditions

TEST
CONDITIONS
(See Test Load)

PARAMETER

tpD

Input or feedback to output
10H8A, 12H6A, 14H4A, 16H2A,
16C1A,10L8A, 12L6A, 14L4A,
16L2A, 16L8A, 16R6A, 16R4A,
16P8A, 16RP6A, 16RP8A

!eLK

Clock to output or feedl:)ack
16R4A, 16R6A, 16R8A,
16RP4A, 16RP6A, 16RP8A

tpzx

Input to output
enal:)le

tpxi

Input to output
disable

tpz/
tpzx

Pin 11 to
output
disable/enable

fMAX

Maximum
frequency

INDUSTRIAL

UNIT
MIN

TYP

RL = 1Kn
CL = 50pF

16L8A, 16R4A,
16R6A, 16P8A,
16RP4A,
16RP6A
16R4A, 16R6A,
16R8A,
16RP4A,
16RP6A,
16RP8A

COMMERCIAL

28.5

MAX

MIN

TYP

MAX

15

25

15

25

ns

10

15

10

15

ns

12

25

12

25

ns

14

25

14

25

ns

12

15

12

15

ns

40

28.5

40

MHz

Notes: Apply to electrical and switching characteristics.
1. These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and/or tester noise; Do -not attempt -to
test these values without suitable equipment.
2. Pin 8 (PRELOAD pin). Applies to all devices whether registered or non-registered.
3. JEDEC standard no. 7 for high·speed CMOS devices.
4. Applies to pins 12 to 19. ..
5. Disable output pins = Vee or GND.
6. Add 3mA per additional 1.0MHz of operation over 1MHz.
7. CL - 5pF:

Monollthii:W'lIIIemories

4·11

Zero Power CMOS Hard Arra, Logic
ZHAL™ 20A Serle.

Switching Test Load

Enable/Disable Delay

H
I

vee

TE5POINT
FROM OUTPUT

UNDER TEST

RL

51

(SEE NOTEeL
1)

OUTPUT
CONTROL
(Low-Ievet

VT

~----:-----'7----- V,L

~abling)

1

~tpZL""""

(SEE NOTE 2)
WAVEFORM 1
(See Note 3)

VT

.-tpZH .....

-::-

"::"

WAVEFORM 2
(See Note 3)

Notes: 1. CL includes probe and iig .capacitance.

VT

2. When measuring tpLZ and tpZ,L' 81 is tied to Vee. When measuring

tpHZ and IpZH' St is tied to ground. Ipzx is measured with CL
50pF. tpxz is measured with CL

=

-

5pF. When measuring

propagation delay times of 3-state outputs. St is open. i.e.. not

Schematic of Inputs and Outputs

connected to Vcc or ground.
3. Waveform 1 is for an output with internal conditiQrls such that the

output is Low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that .the
output is High except when disabled by the output control.

Output Register PRELOADt
The PRELOAD function allows the register to be loaded from
data placed on the output pins. This feature aids functional
testing of state sequencer designs by allowing direct setting of
output states for improved test coverage. The procedure for
PRELOAD is as follows:

~ ••• ~vee

-::~N1

-=-

w---------------:-____
VIH , . - - - - -_ _ _ _ _ _ _'"\

1. Raise Vee to 4.5V.
2. Disable output registers by setting pin 11 to V IH' Set pin 1
to OV.

"I

PIN 11

\

VIL.-../

3. Apply VIL/VIH to all registered output pins.
5. Remove VIL/VIH from all registered output pins.

vp

6. Lower pin 11 to V IL to enable the output registers.
7. Verify for VOL/VOH at all registered outpUt pins.
Note: Only applies to parts with output registers.
Typical tsup = 50ns
I,.p = tOOns
thP = 50ns
I'H = 301lA (Pin 8)

4-12

~

~--.,.--.,...--_>-C

4. Pulse pin 8 to Vp (12V). then back to OV.

t

~rf~

'--8c['"

'sup
PIN 8

ylL------:I

Monolithic WMemorles

I-I-Iw+*hp

ZHAL20A Evaluation #3

Logic Symbol .

Features/Benefits
•
•
•
•
•

Demonstrates all features of ZHAL20A product
4-bit up! down counter with reset
3-bit shifter
25-ns maximum propagation delay
Zerd standby power

ZHAl16R4A

Description
The ZHAL20A Evaluation Pattern is provided as an example
of the features and characteristics of the ZHAL20A Series
products.
This design consists of two functionally independent patterns:
a 4-bit up/down counter and a 3,bit shifter. The 4-bit counter
can count up or count down and has reset capability. These
features are controlled by two control signals: UP and
CNTRSET (Count Reset). When UP is high, the counter
counts up. When UP is low, the counter counts down.
CNTRSET overrides the count function and reSets the counter
to all ones,. synchronous with the clock.
The 3-.bit shifter shifts data bits by 0, 1 or 2 positions. The
three bits of the shifter are enabled when EN (enable) is high,
and are disabled (high-Z) when EN is low.
The PALASM@2 software file and simulation results are
shown on the next page. Below are the function tables that
summarize the functions of the counter and the shifter.

Shifter Function Table

Counter Function Table
OE

UP

CNTRSET ClK

COOl0~

Q3-QO

OPERATION

EN

11

10

Y2

Y1

YO

OPERATION

H

X

X

X

Z

High-Z

L

X

X

Z

Z

Z

High-Z

L

H

L

t
t
t

Q plus 1

Increment

H

L

L

D2

D1

DO

No operation

Q minus 1

Decrement

H

L

H

DO

D2

D1

Shift by one

Reset

H

H

L

D1

DO

D2

Shift by two

L

L

L

L

X

H

High

H=HIGH voltage level
L= LOW voltage level
X=Don't care
Z=High impedance (off) state
f= LOW·lo·HIGH clock transilion

Monolithic WMemories

4-13

ZHAI,.20A. Evaluation

PALASM Design Specification
TITLE
PATTERN
REVISION
AUTHOR
COKPANY
DATE

Simulation File
SIMtJLATlON

POS CONVERSION FILE
EXAMPLE
1. 00
.:rOHN DOE
MO,NOLITHIC MEMORXE"S, INC
9/23/85

TRACE....ON eLI( 10 I l DO 01 02 EN UP CNTRSET 10E Y2 01 02 Q3 QO Yl YO

SETF feLl( fOE lEN
SETF OE EN III /10 /02 JDl /00 Y2 Yl YO CNTRSET

<

CLOCKF eLK

zzz

CHIP

#3

PAL16RP4 eLK 10 I l DO 01 02 EN UP CNTRSET GND
II;XXXXHHHH
CNTRSET XXHHHHLLLL
GND
LLLLLLLLLL
JOE
HHLLLLLLLL
Y2
XZHHHHHHHL
01
ZZXXXHHHLL
Q2
ZZXXXHHHLL
Q)
ZZXXXHHHLL
QO
ZZXXXHHHLL
Yl
XZHHHHHHHL
YO
XZHHHHHHHH
vee
HHHHHHHHHH
<)

eLl(
10

4-14

OE

/CNTRSET UP

CLOCKF CLK
1
09 09c9c9
HLLHLHLHLH
HHLLLLLLLL
LLHHHHHHHH
HHLLLLLLLL
LUlHHHHHHH
HHLLLLLLLL
HHHHHHHHHH
HHHHHHHHHH
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
LLLLHHHHLL
LLLLLLLLHH
LLLLLLL11L
LHHHLLHHLL
LLHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH

c9cgc909c9 cgogcgcgc
LHLHLHLHLH LHLHLHLHL

LLLLLLLLLL
HHHHHHHHHH
LLLLLLLLLL
HHHHHHHHHH
LLLLLLLLLL
HHHHHHHHHH
HHHHHHHHHH
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
LLHHHHLLLL
HHHliHHLLLL
LLLLLLHHHH
HHLLHHLLHH
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH

LLLLLLLLL
HHK8H:HHHH
LLLI.LLLLL
HHHHHHHHH
LLLLLLLLL
HHHHHHHHH
HHlIHHHHHH
LLLLLLLLL
LLLLLLLLL
LLLLLLLLL
LLLLLLLLL
HHHHLLLLH
LLLLHHHHH
HHKHHHHHH
LLHHLLHHL
HHHHHHHHH
HHHHHHHHH
HHHHHHHHH

CHECK 03 102 01 100
SETF OE ICNTRSET UP
CLOCKF CLK

CHECK 03 102 01 00
SETF OE ICNTRSET

CLOCKF eLK

UP

CHECK 03 Q2 101 100
SETF OE ICNTRS£T UP

CLOCKF CLK

CHECK Q3 02 101 QO
SETF OE /CNTRS£T UP

CLOCKF eLl(
CHECK 03 02 01 /00

Zero Power CMOS Hard Array Logic
ZHAL64R32

Features/Benefits
• Cost-effective mask-programmable complement to
PAL64R32 user-programmable device
• CMOS technology provides zero standby power
• High speed with 55ns maximum propagation delay
• High density with 32 highly-flexible macrocells and global
connectivity
• Product term sharing, selectable output polarity, and
register bypass for high logic efficiency
• Individual clocks for 4 banks of 8 registers
• Register preload for easier test generation
• HC/HCT level compatible for use in CMOS/TTL systems

Description
The ZHAL64R32 circuit is a high-density logic device with
thirty-two flexible macrocells. Each macrocell consists of a
registered sum of products with feedback, forming a one-bit
state machine. The PALlZHAL64R32 device can implement
over 1500 equivalent logic gates.
The MegaHALTM circuit (eatures product term sharing between output pairs. This. allows sixteen product terms to be
shared mutually exclusively between outputs. Selectable polarity allows the output to be either active low or active high,
depending on the sense of the equation. Registers can be
bypassed in banks of eight, leaving combinatorial outputs.
Each register bank has its own clock, preset, preload, and
enable controls for independent operation. The register pre-

Pin Configuration -

load pin allows test vectors to be loaded directly into the
registers for control of present state conditions for testing.

Design Procedures
The zero-power ZHAL64R32 device is a CMOS, mask-programmable version of the bipolar PAL64R32 circuit. Prototyping can be done with the user-programmable PAL@ circuit
before committing to a dedicated mask. Thus the MegaPALTM/MegaHAL products combine the instant prototyping of
the PAL circuit with the cost-effective, zero power ZHAL™
circuit.
To initiate a design with the ZHAL64R32 device, the
PAL64R32 circuit is used to program and debug the design
with PALASM@2 software_ The resulting "PAL Device Design
Specification" is submitted to Monolithic Memories, and the
ZHAL Circuit option is produced. A ZHAL32R16 option is also
available. For details contact a Monolithic Memories representative.

Ordering Information
ZHAL

~ z.ro-pOW::JJJr~..
Hard Array
Logic

64 R. 32

ARRAY INPUTS
OUTPUT TYPE

R

=

Registered

NUMBER OF
OUTPUTS
TEMPERATURE
RANGE
C = ooe to 75°C I - -40°C. to ~5°C

r.' I.:

NUMBER
HOC£;T
PATIERN
PROCESSING
STD ~ Standard
XXXX'" Other
PACKAGE TYPE
NL II: Plastic
Leaded Chip
Carrier
p= Pin Grid

Array

PLCC

MonoIlthicWMemorielfl

4-15

a
I

ZHAL64R32
Logic Diagram and Pinout
84 PIN PLCC

(88PGA)

70(731

117116

681711

67 (701
66(691

65(681

64(671

AND
ARRAY
63(681

(24123

62(651

125124

61 (64)

(26125

159
(27)211

58(62)

(28127

58(611

131lI29
(31)30

(33)32-VCC

4-16

Nt

3334

(34)

13511361

....

")',

Monolithic

W Memor/e.

ZHAL64R32
Operating Conditions
INDUSTRIAL

COMMERCIAL
SYMBOL
Vee

Supply voltage

lw

Width of clock
1

UNIT

PARAMETER

I Low
I High

MIN

TYP

MAX

MIN

4.75

5

5.25

20

10

TYP

4.5

5

20

10

ns
ns

Setup time from input or feedback to clock

40

24

45

24

th

Hold time

0

-10

0

-10

TA

Operating free-air temperature

0

25

tsu

Electrical Characteristics
SYMBOL

-40

75

MAX
5.5

V

ns

25

85

TYP

MAX

·C

Over Operating Conditions

TEST CONDITIONS

PARAMETER

MIN

UNIT

V ,L 2

Low-level input voltage

0

0.8

V

V,H 2

High-level input voltage

2

Vee

V

-1

IJA
IJA

I'L 5

Low-level input current

Vee = MAX

V, = GND

I'H 5

High-level input current

Vee = MAX

V, = Vee

VOL

Low-level output voltage

V OH

High'level output voltage

IOZl 5

Off'state output current

= MAX

0.1

10L = 4mA
3.763

10H= -4mA
10H
Vo

= -11JA
= GND

4.1

= .GNDor Vec 4

10 = OmA. V,

10= OmA. V, = GND or Vee

V

V

4.95

Vo = Vee

Standby supply current4

0.4
0.05

10L = llJA

Operating supply .current

Switching Characteristics
SYMBOL

Vee

Vee

10ZH S
lee

Vee

= MIN
= 5V
= MIN
= 5V

Vee
Vee

1

0

-10

0

10

0

100

IJA

See graph on page 4-20

Over Operating Conditions

TEST
CONDITIONS
(See Test Load) .

PARAMETER

COMMERCIAL

UNIT
MIN

TYP

Active
low

tpD 1

Input or feedback to
output

IcLK

Clock to output or feedback

tpzx

Output enable

tpzx

Output disable

tpRH

Preset to output ....

fMAX 1

Maximum frequency.
f = 1/{tsu +teLK)

34

Active
high
RL
CL

= lK.n
= 50pF

..

,

INDUSTRIAL

16

MAX

55

14

22

19

30

18
23
25

MIN

TYP

MAX

34

58

ns

14

25

ns

19

30

ns

30

18

30

ns

35

23

40

ns

..

14

25

MHz

Notes: 1. Maximum 32 In~uts, per, product terro,
2. V1L arid V1H are absolu~e' voltages with re~pect to the ,ground on the .device and includes all overshoots due to system andl or tester noise.
Do' not attempt to test these values without suitable equipment.
3. Per.JEDEe. standard .no. 7 lor high-speed eMOS devices.
4. Disable output pins- Vee or GND.
5. lID pin 'leakage is 'the worst case of lozx or 'IX' i.e., IOZH and IlL'

MonolithiC

W Memories

4-17

ZHAL64R32
Absolute Maximum Ratings
Supply voltage,Vee ...................... , ................................................................................................. -0.5V to 7.0V
DC input voltage; VI ......................................... , ................................................. , .................... -0.5V to Vee + 0.5V
DC output voltage, VO ............................................................................................................. -0.5V to Vee + 0.5V
DC outpulsourcel sink current per output pin, 10 ............................................ , ................................................ ± 35mA
DC Vee or ground current, Icc or IGND ....................................................................................................... ± 100mA
Input diode current, 11K:
VI < 0 ............... , ......... '.............................................................................................. , .......................-20mA
VI > Vee ...... : ....................................................................................................................................+20mA
Output diode current, 10K :
VA < 0 ............. , ................................................................... , .............................................................-20mA
Va> Vee ..... ' .... : ............................................................................................................................... +20mA
Storage temperature, ................................................................................................................. -65°C to + 150°C
Input rise and fall times ........................................................................................................................ 0 to 500ns

Switching Test Load

Enable/DisableDelay
VCC

TESHPOINT
RL'
S1
FROM OUT,PUT
(SEE NOTE 2)
UNDER TEST

CL

(SEE NOTE 1)

I

1

-=

-=

OUTPUT
CONTROL
(Low-level
enabling)

,------V,H
VT
' - - - - - - - - - ' . ' - - - - - - V,L
....-tpZL ......

WAVEFORM 1

VT

(See Note 3)

.-tpZH-+-

WAVEFORM 2
(See Note 3)

VT

Switching Waveforms
INPUTS. UO.
REGISTERED
FEEDBACK
eLK

REGISTERED
OUTPUTS

---------------------~

COMBINATORIAL
OUTPUTS

Schematic of Inputs and Outputs
Notes:

~ •••

-ZVCC

'--Cc['" •~q-'"~'
-=

4-18

-=

1. CL includes probe and jig capacitance.
2. When measuring tpLZ and tpZL' $r is tied to Vee. When measuryng
tpHZ and tpZH ' S1 is tied tp ground. When measuring propagation
delay times of 3-state outputs, 81 is open, i.e., not connected to Vee
or ground.
3. Waveform 1 is for an output, with internal conditions such that the
output is Low except when disabled by the output control. 'Waveform
2 is for an output with internal conditions'such that the ,output is High
except when 'disabled by the output 'control.

MonoIilhiCW Memories

ZHAL64R32
ZHAL64R32 Testability Features
Testing Conditions
COMMERCIAL
SYMBOL

INDUSTRIAL

PARAMETER

UNIT
MIN

TYP

MAX

MIN

TYP

MAX

Iv,p

Preload pulse width

35

45

ns

Isup

Preload setup time

50

60

ns

thp

Preload hold time

5

10

ns

tpRw

Preset pulse width

25

30

ns

Preset recovery time

45

50

ns

tpRR•
• Includes setup tIme for preset data feedback, Maximum 32 inputs per product term.

Preload Feature

Preset Feature

Preload pins are provided to enable the testability of each
state in state-machine design. Typically for a state machine
there are many unreachable states for the registers. These
states, and the logic which controls them, are untestable
without a way to "set-in" the desired starting state of the
registers. In addition, long test sequences are sometimes
needed to test a state machine simply to reach those starting
states which are legal. Since complete logic verification is
needed to ensure the proper exit from "illegal" or unused
states, a way to enter these states must be provided. The
ability to preload each bank of registers independently to any
state is provided in this device.
To use the preload feature, several steps must be followed.
First, a high level on an assertive-low output enable pin
disables the outputs for that bank of registers. Next, the data
to be loaded is presented at the output pins. This data is then
loaded into the register by plaCing a low level on the PRELOAD pin. PRELOAD is asynchronous with respect to the
clock.

Register banks of eight may be PRESET to all highs on the
outputs by setting the PRESET pin (PS) to a low level. Note
from the Logic Diagram that when the state of an output is
high, the state of the register is low due to the inverting threestate buffer.

elK

REGISTERED
OUTPUTS

OE

REGISTERED
OUTPUTS

1I~~rJj~rJj~~

__1TEST DATA
thp

'reload data must be held constant while the PRELOAD pin is low.

MonoiltlllcW Memories

4·19

ZHAL64R32
ICC Characteristics vs. Frequency
Commercial Operating Conditions
400

400

300

100

/
~/
'"

V

/'

1..-........

v--

300

~

1

u200

.9

..-----

........ --

.......

100

",'"

o
o

4

8

(STANDBY)

12

16

FREQUENCY-MHz

('MAX>

-

.,,/ r--

/

£/
'"

00

V

I

~ ..... '"

----

----

..,-

/'"

(STANDBY)

8

16

12

FREQUENCY-MHz

('MAX)

Industrlal Operating Conditions
400

400

I
I
I
I

I

I
I
300

~

100

/

t/

o
o

'"

~

/
V

1, 200

I
I
I

I
...

~.,..----

--1

I

100

I
I
I
I

10-'"

",'"

(STANDBY)

I

300

I
I

",'"

4

I

~

I

8

12

FREQUENCY-MHz

14
('MAX)

o
16

I
////

o

(STANDBY)

I
I
I
I
I

-1-----

- .....
I

I

I
I
I

I
I

8
FREQUENCY-MHz

TA = 8S·C

VALUE

___ = Vee = 5V WITH 32 INPUTS MAX PER PRODUCT TERM

4-20

.......

I

~/

TA = -40·C
_ _ = MAXIMUM

I~

l.,.---~I

MonoIlthlcW.emorie.

12

14
('MAX)

16

ZHAL64R32
ACCharacteristics vs. Loading
Commercial Operating Conditions
70

70

--1

I

=MAXIMUM VALUE

L

60

/

L

r--

60

'so

J

40

40

r-30

o

16

32

48

-

~

16

64

L
32

V
48

64

NO. OF INPUTS/PRODUCT TERM

NO. OF INPUTS/PRODUCT TERM

Industrial Operating Conditions
70

70

60

-V

V

/

~
.60

.
Ii'

J
40

30

o

16

32

64

48

so

V

40

r-----

30

o

16

",

~

32

48

NO. OF INPUTS/PROOUCT TERM

NO. OF INPUTS/PRODUCT TERM

~=wc

~=WC

Monolithic

miD Memories

L

64

4"21

ZHAL64R32
How To Use The PAL/ZHAL64R32
The following description and example demonstrate the functionality of the PAL/ZHAL64R32, using PALASM 2 software.
Conventions for writing equations conform with the PAL Design Specification format. Features to be programmed into the
PAL device are completely specified by the equations and
automatically configured by PAL device assemblers.

Register Bypass
Outputs within a bank must either be all registered or all
combinatorial. Whether or not a bank of registers is bypassed
depends on how the outputs are defined in the equations. A
colon followed by an equal sign [:=] specifies a registered
output with feedback which is updated after the low-to-high
transition of the clock. An equal sign [ = ] defines a combinatorial output which bypasses the register. Registers are bypassed in banks of eight. Bypassing a bank of registers
eliminates the feedback lines for those outputs.

Output Polarity

is different from the logic sense of that output as defined by its
equation, the output is inverted or active low polarity. If the
logic sense of a specific output in the pin list is the same as
the logic sense of that output as defined by its equation, the
output is active high polarity.

Product Term Sharing
The basic configuration is sixteen product terms shared between two output cells. For a typical output pair, each product
term can be used by either output; but, since product term
sharing is exclusive, a product term can be used by only one
output, not both. If equations call for both outputs to use the
same product term, two product terms are generated, one for
each output. This should be taken into account when writing
equations. PAL device assemblers configure product terms
automatically.
This example on the following page uses the 84-pin package.
Four output equations are shown to demonstrate functionality.
Pin names are arbitrary.

Output polarity is defined by comparison of the pin list and the
equations. If the logic sense {)f a specifiq output in the, pin list

4-22

MonoI;thlcW Memor;es

ZHAL64R32
TITLE
PATTERN
REVISION
AUTHOR
COMPANY
DATE

ZHAL64R32 DESIGN EXAMPLE USING PALASM 2
EXAMPLE.PDS
.
PALASM 2 VERSION
NAME
MONOLITHIC MEMORIES, INC.
1986

CHIP FUNCTIONALITY_EXAMPLE PAL64R32
Il 12 13 14 15 16 I7 18 /PL1/PS1 GND CLK1 /OEl
Ql Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Ql0 Qll Q12 Q13 Q14 Q15 Q16
/OE2 CLK2 VCC /PS2 /PL2
19 110 III 112 113 114 115 116 117 118 119 120 121 122 123 124
/PL3 /PS3 GND CLK3 /OE3
Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25 Q26 Q27 Q28 Q29 Q30 Q31 Q32
/OE4 CLK4 VCC /PS4 /PL4 125 126 127 128 129 130 131 132.

COMBINATORIAL/
ACTIVE LOW

EQUATIONS
/Ql
+
+
+
+
Q2

11*12*13
Il1*I27*/I32*Q9
I4*/I9*Ql0
Il*I2*I7*/Q27*Q15*/Q32
18*/Q13*/Q32

:ACTIVE LOW COMBINATORIAL
: OUTPUT. SINCE THE
:REGISTERS ARE BYPASSED
:FOR THIS BANK, THE
:OUTPUTS CANNOT FEED
:BACK INTO THE ARRAY.

11*12*13
:ACTIVE HIGH
+ 127*/Q12
:COMBINATORIAL OUTPUT.
+ I15*/I32*/Q9
:Q2 USES THE REMAINING
+/11*I2*/I3*I4*Q27
:11 PRODUCT TERMS
+ Ql0*Ql1
;AFTER /Ql USED 5.
+/Q32
:NOTE THAT THE FIRST
+ I4*I9*Il1*Q12*/Q27
:PRODUCT TERM IS
+ Q9*Q27*/Q15
:CREATED TWICE.
+ I6*I7*/I:8*/I9*/IlO*/Il2
+ I6*Q12*Q15"
+ Ill*/Q15

/Q9 := I2*/I4*Q15
+/11*14*19*115*132
-Ie Q32*/Q15
+/Q9*13
+ I8*/Q13*/Q32
+ I5*/I6*Ill*/Q15
+ 112*113*127

;ACTIVE LOW REGISTERED
: OUTPUT. SOME OF THE
;OUTPUT SIGNALS ARE FED
:BACK INTO THE ARRAY,
:SINCE THE REGISTER IS
;USED;

COMBINATORIAL/
ACTIVE HIGH

REGISTERED/
ACTIVE LOW

p[

REGISTERED/
ACTIVE HIGH

p[

;ACTIVE HIGH REGISTERED
Q10 := 13*/18
+ I9*Q15*/Q32
;OUTPUT.
+ I7*ra*/I9*/Qll*/Q27*/Q32

MonoillhicW Memories

4-23

Zero Power CMOS Hard Array Logic
ZHALTM24A .Ser.ies

Ordering Information

Features/Benefits
•
•
•
•
•

Zero standby power
Low power operation
High-speed CMOS technology
HCand HCT compatible
24-pin SKINNYDIP® and 28-pin PLCC packages save
space
• Low power alternative for most 24-pin PAL® devices,
including 20L8/20R8/20R6/20R4

Description
This family of Zero Power Hard Array Logic (ZHAL) devices
utilizes a unique architecture that is designed for a high
degree of flexibility in implementing most patterns of the listed
24-pin PAL/HAL ® devices. Prototyping should be done using
standard PAL devices before converting to ZHALcircl.lits for
production. ZHAL devices are fabricated by Monolithic Memories with custom metallization masks defined by a :usersupplied HAL Design Specification.
The ZHAL devices are ideal in low-power applications that
require high-speed operation. These attributes are achieved
through the use of Monolithic Memories' advanced high-speed
CMOS process. Now system designers have the option of
using a ZHAL device that matches fast PAL device speeds,
but with the added feature of zero standby power. These
features are needed in .power-critical areas such as portable
digital equipment or lap-top computers.
The procedures for designing with Monolithic Memories' ZHAL
devices are shown in the flow chart on the next page. The
ZHAL option in the PALASM®2 CAD package will confirm
whether a design specification will fit within the ZHAL architecture. For more information on the ZHAL software, referto the
PALASM2 User Manual.
For evaluation of the ZHAL24A circuit, sample patterns are
available. See the description in this document for details.

OUTPUTS
ARRAY
INPUTS COMB REG

PART NUMBER

PACKAGE

ZHAL12L10A

NS, NL

12

10

ZHAL14L8A

NS, NL

14

8

ZHAL16L6A

NS, NL

16

6

ZHAL18L4A

NS, NL

18

4

-

ZHAL20L2A

NS, NL

20

2

-

ZHAL20C1A

NS, NL

20

2

ZHAL20L8A

NS, NL

20

8

-

ZHAL20R8A

NS, NL

20

-

8

ZHAL20R6A

NS, NL

20

2

6

ZHAL20R4A

NS, NL

20

4

4

ZHAL20L10A

NS, NL

20

10

-

ZHAL20X10A

NS, NL

20

-

10

ZHAL20X8A

NS, NL

20

2

8

ZHAL20X4A

NS, NL

20

6

4

ZHAL20S10A

NS, NL

20

10

-

ZHAL20RS10A

NS, NL

20

-

10

ZHAL20RS8A

NS, NL

20

2

8

ZHAL20RS4A

NS, NL

20

6

4

ZHAL 20 L 10 A C NS STD H01234

ZERO~]fl

POWER
HARD
ARRAY
LOGIC

~~~:~7N~~TS

~

---c..... PATTERN

.

... •

.

..

OUTPUT TYPE
L - Active Low
C ... COmplementary
R ... Registered
X
XOR Registered
S = Shared Terms

NUMBER

p.R.OCESSING

STO

= Standard

XXXX = Other

PACKAGE
NS = Plastic DIP
NL .. Plastic Leaded

Chip Carrier
L.._ _ _ _ _

TE~~E~~6~:~f5~~GE

;0:

RS - Registered.

Shared Terms

I ... _40°C to
A

4-24

MonoIlthlt:WMe",or/es

+ 85°C

'--_ _ _ _ _ _ SPEED
~

High Speed

ZHAL24A Series
ZHAL 24A Device Generation Flow
ZHAL24A DEVICE GENERATION FLOW
CUSTOMER

NO

REARRANGE OUTPUT PINS IN
PAL DESIGN SPECIFICATION
OR REDUCE EQUATION
COMPLEXITY

,---------1
I
I
MONOLITHIC MEMORIES

I
I

~-----+~

I
I
I
I
I
I

I
I

I

I

I
I
I
I
I
I
I
I

I
I
I

I
I
I
IL- _ _ _ _ _

Monolithic

W Memories

I
I

I

-'-~...:...---J

4·25

ZHAL24A Series

Pin Configurations - DIP and PLCC
ZHAL14L8A

ZHAL12L10A

ZHAL12L10A

INPUT
AND
OR
LOGIC
ARRAY

ZHAL14L8A

ACTIVE
LOW
OUTPUT
CELLS

INPUT
AND
OR
LOGIC
ARRAY

4-26

ACTIVE
LOW
OUTPUT
CELLS

ZHAL18L4A

ZHAL16L6A

INPUT
AND
OR
LOGIC
ARRAY

ZHAL18L4A

ZHAL16L6A

ACTIVE
LOW
OUTPUT
CELLS

INPUT
AND
OR
LOGIC
ARRAY

MonoIithicW Memories

ACTIVE
LOW
OUTPUT
CELLS

ZHAL24A Series
Pin Configurations - DIP and PLCC
ZHAL20L2A

ZHAL20C1A

ZHAL20L2A

INPUT
AND
OR
LOGIC
ARRAY

ZHAL20C1A

ACTIVE
LOW
OUTPUT
CELLS

Monolithio

INPUT
AND
OR
LOGIC
ARRAY

W Memories

COMPLEMENTARY
OUTPUT
CELLS

4-27

ZHAL24A Series
Pin Configurations - DIP and PLCC
ZHAL20L8A

ZHAL20R8A

ZHAL20R6A

ZHAL20L8A

INPUT

AND
OR
LOGIC
ARRAY

ZHAL20R8A

I/O

OUTPUT I/O
CELLS
I/O

INPUT

AND
OR
LOGIC
ARRAY

ZHAL20R6A

INPUT

AND
OR
LOGIC
ARRAY

4-28

ZHAL20R4A

REG

OUTPUT REG
CELLS
REG

ZHAL2OR4A

REG

OUTPUT REG
CELLS
REG

INPUT

AND
OR
LOGIC
ARRAY

Monolithic WMemorles

REG

OUTPUT REG
CELLS
REG

ZHAL24A Series
Pin Configurations - DIP and PLCC
ZHAL20L1OA

ZHAL20X10A

ZHAL20X4A

ZHAL20X8A

ZHAL20X10A

ZHAL20L10A

INPUT

AND
OR

LOGIC

OUTPUTREG
CELLS

ARRAY

ZHAL20X4A

ZHAL20X8A

MonoIlthlcWMemor/es

4-29

ZHAL24A Series
Pin Configurations - DIP and PLCC
ZHAL20S10A

ZHAL20RS10A

ZHAL20R'S8A

ZHAL20S10A

ZHAL20RS4A

ZHAL20RS10A

INPUT

AND
OR

REG

OUTPUT
CELLS

LOGIC
ARRAY

ZHAL20RSSA

REG

ZHAL20RS4A

REG

INPUT

REG

AND
OR

outPUT
CELLS

REG

REG

.LOGIC
ARRAY

REG

OUTPUT
CELLS

REG
REG
liD

4-30

MonoIithicWMemories

ZHAL24A Series 12L10A, 14L8A, 16L6A, 18L4A, 20L2A, 20C1A

Operating Conditions
INDUSTRIAL
SYMBOL

COMMERCIAL

PARAMETER

UNIT
MIN

TYP

MAX

MIN

Vee

Supply voltage

4.5

5

5.5

4.75

TA

Operating free-air temperature

-40

25

85

0

Electrical Characteristics
SYMBOL

TEST CONDITIONS

MIN

Low-level input voltage

0

VIH 1

High-level input voltage

2

III

Low-level input cutrent

Vee = MAX

VI = GND

IIH

High-level input current

Vee = MAX

VI = Vee

VOL

Low-level output voltage

VOH

High-level output voltage

Off -state output current

tpD

Operating supply current

°C

Vee =MIN

10H = -6mA

3.76 2

10H .. -1j.LA

4.95

= 5V

10 = OmA, VI
f

= MHz,

= GND

MAX

UNIT

0.8

V

Vee

V

0.4

j.LA
p.A
V

0.05
4.1
V

Vo = GND
Vee = MAX

TYP

= Vee

or Vee

10 = OmA, VI = GND or Vee

0

~10

j.LA

0

10

j.LA

0

100

j.LA

2

55

rnA

Over Operating Conditions

PARAMETER

Input to output

V

75

0.1

10l = 8mA
10l = j j.LA

Vo
Standby supply current4

SYMBOL

5.25

1

Vee = 5V

Vee

Switching Characteristics

5
25

~1

Vee = MIN

IOZH3
Icc

MAX

Over Operating Conditions

PARAMETER

Vilt

IOZl3

TYP

TEST
CONDITIONS
(See Test Load)

INDUSTRIAL

COMMERCIAL
UNit

MIN

TYP

Rl = 1Kn
CL = 50pF

13

MAX
256

MIN

TYP
13

MAX
256

ns

Notes: 1. These are absolute voltages with respect to the the ground pin on the device and includes all overshoots due to system and/ or tester noise.
Do not attempt to test the&6 values without suitable equipment.
2. JEDEe standard no. 7 for high-speed CMOS devices.
3. Applies to pins 14-23 for DIP (pins t7. 18.20-27 for PleC).
4. Disable output pins = V cc or GND.
5. Add 3mA per additional 1.0MHz of operation over 1MHz.
6. For outputs, with more than 12 inputs in a product term, tpD = 30n8.

MonolilhieW Memories

4-31

ZHAL24A Series 20L8A, 20R8A, 20R6A, 20R4A
Operating Conditions
INDUSTRIAL

COMMERCIAL

PARAMETER

SYMBOL

UNIT
MIN

TYP

MAX

MIN

TYP

MAX

5.5

5.25

Vec

Supply voltage

4.5

5

4.75

5

Iw

Width of clock

15

4

15

4

ns

tsu

Setup time from input or
feedback to clock

20 1

11

20 1

11

ns

th

Hold time

0

TA

Operating free-air temperature

-40

Electrical Characteristics
SYMBOL

20R8A,
20R6A,
20R4A

-10
85

25

0

-10

0

25

V

ns
75

°C

Over Operating Conditions

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIL 2
VIH 2

Low-level input voltage

0

0.8

V

High-level input voltage

2

IlL

Low-level input current

Vee
-1

IlA

IIH

High-level
input current

VOL

Low-level output voltage

VOH
IOZl5

IPin 103

I All other pins

High-level output voltage
Off-state output current

VI

= GND

Vee

= MAX

VI

= Vee

Vee

Vee

= MIN
= 5V
= MIN
= 5V

Vee

= MAX

= 8mA
= 1p.A
10H = -6mA
10H = -lIlA
Vo = GND
Vo = Vee

Vee

0.1

10

VI

f

10

= GND or Vee
= OmA, VI = GND

3.764

p.A

1

p.A

0.4

4.1

V
V

4.95
0

-10

p.A

0

10

p.A

0

100
57

mA

2

or Vee

V

30

0.05

10L

Operating supply current

= OmA,
= 1MHz,

8

10L

Standby supply current6

Switching Characteristics
SYMBOL

= MAX

Vee

IOZH5
Icc

Vee

IlA

Over Operating Conditions

PARAMETER

TEST
CONDITIONS
(See Test Load)

INDUSTRIAL

COMMERCIAL
UNIT

MIN

TYP

MAX

MIN

TYP

MAX

tpD

Input or feedback to output
20L8A, 20R6A, 20R4A

13

25 1

13

25 1

ns

!eLK

Clock to output or feedback
20R8A, 20R6A, 20R4A

8

15

8

15

ns

tpzx

Input to output
enable

12

25

12

25

ns

t pxz S

Input to output
disable

12

25

12

25

ns

10

20

10

20

ns

tpzx

Pin 13 (DIP) to
ouutput
disable/ enable

f MAX

Maximum
frequency

t pxz S

20L8A,
20R6A,
20R4A

RL = 1Kn
CL = 50pF

20R8A,
20R6A,
20R4A

28.5

40

28.5

40

Notes. 1. For outputs with more than 12 Inputs In a product term, t:;;u - 25ns and tpD - 30ns.
2. These afe absolute voltages with respect to the ground pin on the device and include all overshoots due to system and! or tester noise.
Do not attempt to test these values without suitable equipment.
3. Pin 10 (PRELOAD pin), pin 13PLCe (PRELOAD pin). Applies to registered devices only.
4. JEDEe standard no. 7 for high-speed eMOS devices.
5. Applies to pins 14-23 for DIP (pins 17. IS, 20-27 for PLeC).
6. Disable output pins = Vee or GND.
7. Add 3mA per additional1.0MHz of operation over 1MHz.
S. eL = 5pF.

4-32

Monolithic

W Memories

MHz

ZHAL24A Series 20L 1 OA, 20X10A, 20X8A,20X4A
Operating Conditions
SYMBOL

INDUSTRIAL

PARAMETER

MIN

COMMERCIAL

MAX

TYP

UNIT

MIN

TYP

MAX
5.25

Vee

Supply Voltage

4.5

5

4.75 .

5

lw

Width of clock

15

5

15

5

ns

t..u

Setup time from
input or feedback to clock

25 1

15

251

15

ns

20X10A,
20X8A,
20X4A

th

Hold time

0

TA

Operating free-air temperature

-40

Electrical Characteristics
SYMBOL

5.5

-10
25

85

0

-10

0

25

PARAMETER

.'.

TEST CONDITIONS

MIN

Low-level input voltage

O'

V IH 2

High-level input voltage

2

IlL

Low-level input current
High-level
input current

I Pin 103
I All. other pins

VOL

Low-level output voltage

VOH

High-level output voltage

IOZL5 .

Off-state output current

Vee = MAX
Vee = MAX

VI = Vee'

Vee = MIN

10L" 8mA

Vee = 5V

10L = 1/lA

Vee = MIN

10H = -6mA

Vee = 5V

loli:=

Vee = MAX

-1/lA

0.1
3.764

.

V

Vee

V

-1

/lA.

30

/lA

1

/lA

0.4

V

4.1

V

4.95

Vo =GND

0

Vo = Vee

O'
0

Operating supply current

f = 1 MHz, 10 = OIliA, VI = GND or Vee

2

Over Operating Conditions

- TEST
CONDITIONS
(See Test Load)'

UNIT

0.8

0.05

10= OmA, VI = GND or Vee

,··PARAMETER

MAX

8

Standby supply currents

Switching Characteristics
SYMBOL

TYP

VI = GND

IOZH5
lee

I1S.

0Q

75

Over Operating Conditions

V IL 2

IIIf

V

...
INDUSTRIAL

-10

/lA

10

/lA

100
57

rnA.

/lA

/

COMMERCIAL
UNIT

MIN

TYP

MAX

MINe

TYP

MAX

,

tpD

Input or feedback to output
-20L10A, 20X8A, 20X4A

13

'251

13

25 1

ns

!eLK

Clock to output or feedback
20X10A, 20X8A, 20X4A

10

15

10

15

ns

tpzx

Input to output
enable

12

25

12 '.

25

ns

t pxz 8

Input to output
disable

12

25

12

25

ns

t pxz 8

Pin 13 (DIP) to
output-disable/
enable

15

20

15

20

ns

tpzx
f MAX
Notes.. 1.
'2.
3.
4.
5.
6.

7.
8.

20L10A,
20X8A,
20X4A

RL = 1KU
C L = 50pF

!

20X10A,
20X8A,
20X4A

.

Maximum
22.2
32
22.2
32
frequency
For outp~ WIth more th", 12 Inputs In a product term, !lou 30ns and !Po 30no.
These are absolute voltages with respect to the. ground pm on the device and include 'all overshoots due to system and/eil' tester noise.
Do not attempt to test these valueswilhout suitable equipment;
.
Pin 10 (PRELOAD pin), pin 13PLCe (PRELOAI':f pin). Applies to registered devices-only.
JEDEC standlird 110. 710r high-speed eMOS devices: .' .
. . •.. Applies to 'pins 14·23 lor DIP (pins 17, 18,20-27 lor PLee).
Disable output pins - Vcc or GND.
.
:.
Add 3mA per add"ional 1.0MHz of operation over 1MHz.
eL - 5pF.

-

-

MHz

4~33

ZHAL24A Series 20S10A, 20RS10A, 20RS8A, 20AS4A

Operating Conditions
COMMERCIAL

INDUSTRIAL
SYMBOL

UNIT

PARAMETER
MIN

TYP

Vee

Supply voltage

4.5

5

'w

Width of clock

15

4

tsu

Setup time for input clock

th

Hold time

TA

Operating free-air temperature

Electrical Characteristics
SYMBOL

20RS10A,
20RSSA,
20S4A

20 1

MAX

MIN

5.5

-40

MAX

4.75

5

5.25

15

4

20 1

11
-10

0

TYP

25

85

11

0

-10

0

25

V
ns
ns

75

°C

Over Operating Conditions

PARAMETER

MIN

TEST CONDITIONS

TYP

MAX

UNIT

V IL 2

Low-level input voltage

0

O.S

V IH 2

High-level input voltage

2

Vee

V

IlL

Low-level input current

-1

J.LA

High-level
input current

30

/JA

IIH

1

J.LA

I Pin 103

I All other pins

VOL

Low-level output voltage

VOH

High-level output voltage

IOZL5

Off-state output current

Vee = MAX

VI = GND

Vee = MAX

VI = Vee

Vee = MIN

10L = SmA

Vee = 5V

10L = 1J.LA

S

0.4
0.05

Vee = MIN

10H = -6mA

3.764

Vee = 5V

10H = -1/JA

4.95

4.1

V

V

Vo = GND

0

-10

J.LA

Vo = Vee

0

10

J.LA

Vee = MAX

IOZH5
lee

0.1

V

Standby supply current6

10 = OmA, VI = GND or Vee

0

100

J.LA

Operating supply current

f = 1MHz, 10 = OmA, VI = GND or Vee

2

57

mA

Switching Characteristics
SYMBOL

OVer Operating Conditions

TEST
CONDITIONS
(See Test Load)

PARAMETER

INDUSTRIAL

COMMERCIAL
UNIT

MIN

TVP

MAX

MIN

TVP

MAX

tpD

Input or feedback to output
20S10A, 20RSSA, 20RS4A

13

25 1

13

25 1

ns

teLK

Clock to output or feedback
20R$10A, 20RSSA, 20RS4A

S

15

S

15

ns

tpzx

Input to output
enable

12

25

12

25

ns

t pxz 8

Input to output
disable

12

25

12

25

ns

t pxz 8

10

20

10

20

ns

tpzx

Pin 13 (DIP) to
output disable/
enable

fMAX

Maximum
frequency

20S10A,
20RSSA,
20RS4A

RL
CL

20RS10A,
20RSSA,
20RS4A

= 1Kn
= 50pF

2S.5

40

2S.5

40

Notes. 1. For outputs with more than 12 Inputs In a product term, t$U .- 2508 and tpD - 30ns.
',
.,
2. These are absolute vOltages with respect to the ground pin on the device and include all overshoots due. to system and!or tester noise.
Do not attempt to test these values without suitable equipment.

3. Pin 10 (PRELOAD pin), pin 13PLee (PRELOAD pin). Applies to registered devices only.
4. JEDEC standard no. 7 for high-speed CMOS devices.

5. Applies to pins 14·23 for DIP (pins 17, 18. 20·27 for PLeC).
6. Disable output pins = Vee or GND.

7. Add 3mA per additional 1.0MHz of operation over 1MHz.

8.

4·34

eL = 5pF.

MonoilthicWMemorles

MHz

ZHAL24A Series
Absolute Maximum Ratings
Supply voltage, Vcc .........•...............................................................• :; ......•..............................•.........•-O.5V to 7V

gg :~~~~~~~:~~V~·::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: =g:~~!~ ~~ :g:~~

DC output source/sink current per output pin, 10 ......................................... , ................................ , ............. ; ... : ± 35mA
DC Vccor groqnd current, lee or IGND ..................................................................................•..•...........•..... ±·100mA
Input diode current, 'n{
.
..
.

.Output
~:; ~t~::::::::::':::~::::::::::::::::::::::::;::::::::::: :::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::·::::::::~~~~1
diode cuttent,.I :
. . ,
OK
Vo < 0 ................... ,., ..................... : •.• , ................................................... ., .•...•..•'., ..........••..... " .. ', ..•..... " ..,..,.20mA
Vo > Vee .. ··.·, .. · .. : ..... ;:.............. , .............................................,.................................. ; ....'....... , .............. ,jo20mA
Storage temperature.; .•• ., ......................................................................... , •.. , ................ ; .............. -.65·Cta 'f:150·C

Switching Test. Load

,

Enable/Disable'Delay

..

vee .'

TES~'POINT
,'.,
. ,
.,

.... RL

FR.
OM OUTPUT
UNDER
TEST .. '. '.

1)1

SI,

. . , .'. . ......

'CL'
(SEE NOTE

'

...

1'.

.'

"(SeE NOTE. 2)

v

-

--=-

Schematic of Input~nmd Outputs

~
INPUT.~'
YN
•

•••

P

.•••

-

'..

·WFOO1_

~"
·,.vee

--I

In<;l~

P

N

. . . . . ' . .... OuTPUT

--I
.

-=-

to:

~

Output Register PRI;LOADt
The,PRELOAD·function allows.tlTe register to be loaded·from
datil placed on thEl output pins. ThisfElature aids fqnctiOrial
testing' ofstatEl sElquElncElr. dElSigns by allowing dirElct sEltting. of
output statEls for improvEld test covElrl\Q9. ThEl procedure for
PRELOAD using DIP pin numbers, is as follOWs:
1. Raise Vee to 4.5V.
2. Disable output registers by setting, pin 13 to V1H . Se.t pin 1
toilV.
3~ Apply V1LIV 1H to all registered outputs.
4. F'ulse pin 10 to Vp.(l2V),.then back to OV.
5. Remove V1LIV1H frorn allregJstered outputs.

PIN 1

Note; Only applies to partswilh oUlJlut registers.
, Typical isup - 50nS
'
Iwp = lOOns
thp - 50ns
IIH

= 30pA (Pin ·10)

of

Q'JI....;.._...;..-,.---_ _...;.._ _ _ _ _ __

.

6. ,Lower pin 13 to V1L'tO enable tl:le outPUt registers..
7. Verify for VollVOH at all registered outputs.

t

~clti.~. . .

Notes: 1. ct
prooeand jig
2. wt:'en m~~ng fuand Ip~. 51' is\i9d,to Vee' When rneasuiing
tpHi andlpzH," SHe ,tiedU> ground: \pzx . is 'measured with
CL ~ SOpF,lpxz 1.rneasuredw~h CL·=·SpF,. . , '
When measuring Propagation delay .timeS three-state OUlpLlts. S1
i~ 1JPlIn; i:e:. O'!t connected \(i5c:' or ~round.. . . ' .
'lVl1vefOrm 1 IS: lot an pulpUt 'Wltliii!tGmaJ Conditio.,,~ such thai the
pulP"! 'is ,LOW ilxeept when JjisSbkldby 'the oulput control.
Wii.vef~ 2 is tOr anoiltpuf Witi1'.lhternal conditions.·such !hat' the
oul!>ut,is'I:tIGHexcept when disabled,bi1h" output control.

PIIII:10
,
VIL.."..'-..--......- J

ZHAL24A Evaluation #4
Logic Symbol

Features/Benefits
• Demonstration pattern for ZHAL24A Series (ZHAL20X8A)
•
•
•
•

ZHAL20X8A

8-bit counter
Three-state output
Expandable in 8-bit increments
Equivalent to 74ACT461

Description
The ZHAL24A Evaluation #4 pattern is provided as an
example of the features and characteristics of the ZHAL24A
Series· products. The design consists of an 8-bit synchronous
counter with parallel load, clear, and hold capability. Two
function select inputs (10, 11) provide one of four operations
which occur synchronously on the rising edge of the clock

DATA

03

DATA

IN

04

OUT

(CK).

The LOAD operation loads the inputs (07-00) into the output
register (07-00). The CLEAR operation resets the output
register to all LOWs. The HOLD operation holds the previous
value regardless of clock transitions. The INCREMENT operation adds one to the output register when the carry-in input is
TRUE(Ci = LOW), otherwise the operation is a HOLD. The
carry-out (CO) is TRUE (CO = LOW) when the output register
(07-00) is all HIGHs, otherwise FALSE (CO = HIGH).
The data output pins are enabled when OE is LOW, and
disabled (HI-Z) when OE is HIGH.
Two or more 8-bit counters may be cascaded to provide larger
counters. The operation codes were chosen such that when 11
is HIGH, 10 may be used to select between LOAD and
INCREMENT as in a. program counter (JUMP/INCREMENT).

Function Table
OE

H
L
L
L
L
L

CK

11

10 CI

t
t

L
L
H
H
H

L
H
L
H
H

07·00

. ... .
t
t

t

X
X
X
H
L

X
X
D
X
X

07·00

OPERATION

Z
L

HI-Z'
CLEAR
HOLD
LOAD
HOLD
INCREMENT

0
0

0

o plus 1

·When DE is HIGH, the three·state outputs are disabled to the highimpedance states; however, sequential operation of the counter is not
affected.
H = HIGH voltage level
L = LOW voltage level
X = Don't care
Z = High impedance (off) state
! = LOW-to-HIGH clock transition

4-36

MonoIlthleWMemor/es

14

co CARRY OUT

ZHAL24A Evaluation #4
Logic Diagram
ZHAL20X8A

Monolithic

W Memories

4·37

ZHAL24A Evaluation ,#4
Title
Pattern
Revision
Author
Company
Oate
CHIP

ZHAL24A Evaluation 4 (74ACT461)
P7023
~
B
Birkner/Kazmi/Blasco
Monolithic Memories, Inc.
19'86

ZHAL24A_Evaluation~4

PAL20X8

CK
IO 00 01 02 03 04 0506 07 Il GNO
JOE /CO Q7 Q6 Q5 Q4 Q3 Q2 Q1 QO /CI VCC
EQUATIONS
/QO

:=

+
:+:

+

/Il*/IO
IO*/QO
I1*/IO*/00
Il* IO* CI

/Q1 :=

/Il*/IO
IO*/Q1
:+: I1*/IO*/01
+
I1* IO* CI*QO

+

/Q2 :=

;CLEAR LSB
;COUNT/HOLO
;LOAO DO (LSB)
; COUNT
; CLEAR
;COUNT/HOLO
;LOAO 01
; COUNT

/Il*/IO
IO*/Q2
Il*/IO*/02
I1* IO* CI*QO*Q1

; CLEAR
;COUNT/HOLO
;LOAO 02
; COUNT

/Il*/IO
IO*/Q3
:+: I1*/IO*/03
+
I1* IO* CI*QO*Q1*Q2

; CLEAR
;COUNT/HOLO
;LOAO 03
; COUNT

+
:+:
+

/Q3 :=

+

/Q4 :-

/Il*/IO
IO*/Q4
Il*/IO*/04
I1* IO* CI*QO*Q1*Q2*Q3

; CLEAR
;COUNT/HOLO
;LOAO 04
; COUNT

/Q5 :=

/Il*/IO
IO*/Q5
I1*/IO*/05
I1* IO* CI*QO*Q1*Q2*Q3*Q4

,;CLEAR
;COUNT/HOLO
;LOAO 05
; COUNT

/Q6 : -

/Il*/IO
IO*/Q6
Il*/IO*/06
I1* IO* CI*QO*Q1*Q2*Q3*Q4*Q5

+
:+:
+

+
:+:
+
+

:+:
+
/Q7 :-

/Il*/IO
IO*/Q7
:+: I1*/IO*/07
+
I1* IO* CI*QO*Q1*Q2*Q3*Q4*Q5*Q6

+

IF (VCC)

CO - CI*QO*Q1*Q2*Q3*Q4*Q5*Q6*Q7

; CLEAR

;COUNT/HOLO
;LOAO 06
; COUNT
;CLEAR MSB
;COUNT/HOLO
;LOAO 07 (MSB)
; COUNT
;CARRY OUT

Logic Cell ArrayTM
Introduction
The Logic Cell Array (LCA)TM is a CMOS integrated circuit
with a flexible, uncommitted architecture and VLSI-Ievel density. The LCA is manufactured on Monolithic Memories' 1.6
micron CMOS process. The device architecture as is shown in
Figure 1, similar to that of a gate array, with an interior matrix
of programmable logic blocks, a surrounding ring of I/O
interface blocks and programmable interconnect used to define the overall device structure.
Unlike gate arrays, Logic Cell Array functionality is defined by
the user simply by loading the internal writable storage cells
with the configuration data. An additional benefit, reprogrammability in system, allows in-circuit-emulation to be used for
design verification.
The M2064 family of Logic Cell Arrays has been developed to
allow Monolithic Memories to offer a device and technology
that offer both the density benefits of gate arrays and the
programmability benefits of user-configurable devices. These
parts have been designed for maximum flexibility. in system
applications and are easy to use.
Using the XACTTM software development system, the designer can define and interconnect logic blocks to build largerscale, multi-level logic functions. These are then connected to
external circuitry. Interconnections throughout the Array are
defined automatically by the development system, unless
otherwise specified by the designer. Because the Logic Cell
Array's logic functions and interconnections are established
with memory cells, the array is never physically altered;
instead it is simply reprogrammed.

XACT Evaluation Kit (LCA-MEK01)
Monolithic Memories offers evaluation software and documentation that will allow a. designer to determine if his or her logic
design fits and assess its performance as a Logic Cell Array.
All that is needed is an IBM PC-XT, AT, or compatible, a
three-button Mouse System or compatible mouse.

XACT Development System
(LCA-MDS21)
The XACT Development System is the "power behind the
machine." It will allow a designer to. sit down with a concept
and walk away with a completely tested, completely finished
part.
The reason is that XACT functions as both a CAE and CAM
system. The CAE part of the system allows the designer to
simply draw out the design using a sophisticated graphicsbased design editor. The CAM part then converts the drawing
to code, similar toa PALASM-generated JEDEC file, that
allows programming with conventional programming hardware
of an EPSOM containing the configuration data for system
phototyping.
The XACT Development System currently has 113 macros
and, in addition, allows the user to define his or her own
macro. To insure that internal timing constraints are satisfied,
a Timing Analyzer is included to calculate propagation delays
along any path within the Array.

As the design is being entered, the Automatic Design Checker
insures that no design rules are violated, and when the design
is completed, a final design rule check is performed.

The XACT Development System
Contents:
•
•
•
•
•
•

Editor
Macro Library
Design Checker
Timing Analyzer
Configuration File Generator
Configuration File Formatter

In-Circuit-Emulator
(LCA-MDS24)
The In-Circuit-Emulator is a software/hardware package that
enables a designer to connect his or her target system to the
work-station where a design has just been completed. The
emulator package allows:
• User control and monitoring of device function
• Interactive or file-driven setup and configuration
• Daisy-chain configuration capabilities for up to seven LCAs
in a chain
• Simultaneous in-circuit emulation of up to four devices
• Single step capability for device clocks
• Readback display of device internal register states
• Dynamic reconfiguration capability.
The In-Circuit-Emulator comes with a single "pod". Up to
three additional pods (LCA-MDS25) may be ordered for each
emulator.

P-SILOS Simulation Package
.
.. .
(LCA-MDS22)
After a design is completed, the next step is to simulate.
Monolithic Memories offers an integrated simulation package
manufactured by Simucad, called P-SILOS.

PART NUMBER
LCA-MEK01

LCA Evaluation Kit

LCA-MDS21

LCA Development system

LCA-MDS22

LCA Simulator-P-SILOS

LCA-MDS24

LCA In-Circuit-Emulator

LCA-MDS25

LCA In-Circuit-Emulator Pod

LCA-MTB01

LCA Demonstration Board
Table 1

The introduction of the Logic Cell Array will allow customers to
reduce inventories of discrete components, reduce the time to
market and development cost for new products, save money
in manufacturing and spare parts inventory management,
reduce test costs and improve system reliability.

TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

5-2

DESCRIPTION

Monolithic ~T!n

Memories Il1Jn.U

Configurable Logic Block

Interconnect

The core of the Logic Cell Array is an 8 x 8 matrix of
Configurable Logic Blocks. Each CLB provides four logic
inputs, a clock input, a combinatorial logic section, two logic
outputs, and a programmable storage element.
The inputs drive a combinatorial logic section that can perform
any logic function from a simple gate to a three-out-of-four
majority decoder.
The combinatorial portion accepts and generates both positive- and negative-true logic, eliminating the need for inverters
or the routing of complementary signals.
The storage element can serve as aflip-flop (D-type) and can
be programmed to have clock enable, synchronous set and
reset, and various gated inputs. In addition, since all these
options can be specified independently for each logic block,
designers can mix asynchronous and synchronous logic in any
combination.

The Array's extraordinary flexibility is also the result of a twolayer metal network of lines that run horizontally and vertically
between the logic and I/O blocks, and a variety of userdefinable interconnection elements.
Definable interconnection points connect the inputs and outputs of logic and I/O blocks to nearby metal lines.
Crosspoint switches and interchanges are clustered at the
intersection of every row and column of logic blocks. They link
horizontal and vertical paths and allow signals to be switched
from one path to another.
Finally, "long lines" run the length and breadth of the chip,
bypassing interchanges but tying into logic blocks and other
lines and distributing clocks and other critical signals with a
minimum ~f propagation delay.
Interchanges and interconnection point assignments, as well
as all routing are handled automatically by the XACT Development System Software. In addition, special graphics-based
deSign tools are included to facilitate any necessary deSigner
interaction.

•• •• •• •• •• •

· ... .ii.

~.=-im=~

•• • • • • ._-•• • •
•• • • • • • • •••
•• • • • • • • • • ••
• • • • • • • •• ••
•• •• •• •• •• •• •• •• •••
•
---

• ••

••• •
••
•••••••••••••••••

Configurable I/O Block
External Signals enter and leave the chip through generalpurpose, user-definable I/O blocks positioned around the
periphery of the array. Each block can be programmed independently to be an input, output or bidirectional pin with a
tristate control on the output. When configured as an input,
the designer can select TIL or CMOS thresholds. In addition,
each I/O bloc contains an input register option whose clock
line is common to all the other I/O blocks along the same
edge of the die.
I/O blocks can also handle more than input and output
functions. For example, the Input registers of unused I/O
blocks can be used for read/write storage registers or as
stages of a shift register.
Figure 1

MonoIllhlcilD.emorles

5-3

Logic Cell ArrayTM
M2064

Features/Benefits
• CMOS programmable Logic Cell Array (LCATM) for
replacement of standard logic
• Completely reconfigurable by the user in the final system
• High performance
• 20M Hz flip-flop toggle rate (-20 speed grade)
• 33MHz flip-flop toggle rate (-33 speed grade)
• 50MHz flip-flop toggle rate (-50 speed grade)
• User-configurable logic functions, interconnect and I/O for
maximum flexibility
• 64 user-Configurable Logic Blocks (CLBs) providing usable
gate equivalency of upto 1500 gates
• 58 individually-configurable I/O pins allowing any mix of
inputs, outputs or bidirectional signals (68-pin package)
• User-selectable TTL or HCMOS input threshold levels
• Multiple configuration modes for greatest flexibility and ease
of use
• Verification feature allows user to check configuration data
• User-selectable security feature prevents read-back of
configuration data
• Read-back of internal register states for system del:)ug
• On-chip clock oscillator and CIO.CK buffer circuits provide
flexible internal and external clocking functions
• Master reset of all internal register elernentsin addition to
user-configurable Reset and/or Set control of individual
CLB storage elements

General Description
The M2064 is the first member of a family of configOrable
Logic Cell Arrays (LCAs) availabla from Monolithic Memori.es.
These general purpose CMOS integrated circuit devices allow
the user to rapidly implement complex digital logic functions
directly without the requirement for masking or other.vend.or
performed programming steps. Unique configuration circuitry
allows complete reconfiguration within a user's. final system to
allow system changes "on-tlw-fly."
User configuration is controlled by internal storage elements.
These are loaded with data bits which control. definition of
logiC functions, configuration of 110 blocks, routing of internal
Signals, and other options. Configuration data. can be loaded
in one of several methods to minimize impact on overall
system design.
CMOS technology optimized for system level performance
provides LS-TTL compatible speeds with. power consumption

less than 10% of equivalent TTL systems. The use ofinnovative 110 buffers providing either TTL or CMOS input switching
levels insures lOwest -possible power consumption in· totally
CMOS systems without any cOmpromise in performance.

M2064'- 20 C NL

=r

PART
NUMBER

SPEED GRADE
- 20 = 20MHz toggle rate
-33 ... 33MHz toggle rate
- 50 = 50MHz toggl~

L

..'
_

e..,,,,m.
,~L:~: ~:~ ~~~ru;.~r~IP
N

Carrier

= 48 Pin Molded Dip

TEMPERATURE RANGE
C = Commercial

PART NUMBER

DESCRIPTION

LCA-MDS21

XACT Development System

LCA,MDS22

P-SILOS Simulation Package

LCA-MDS24

LCA In-Circuit Emulator

LCA-MDS25

In-Circuit Emulator Pod

LCA-MEK01

XACT Evaluation Kit

0

~

~

g g g g

g g

g g

g

RESET
DONE·-PG
ICTAL1-l/0

vo

vo

vo
'10
liD

PWRON

¥:c

g g g
~
~ ~ :;

~

0

~

:c

~ i

~

Portions -of this Data Sheet reproduced with the permission of XIUNX Inc.

TWX, 910'338-2376
21.75 Mission College Blvd. Santa Clara, CA 95054-1592 Tel, (408)970-9700 TWX, 910-338.-2374

5-4

'I

Ordering Information

Mono/ithicm1!n
Memories ·uurw

Logic Cell ArrayTM M2084

PinDescriptlbn
1/0

User-col)figur~lell)putlOutPlJt pins.
-PWRDN

'

"

..'

Input,forCEilsdeviceinto low. power (node; operaticm is suspended,
~o--RT '
Dual function input. During initial Power up; the state of MO
and M 1 determines the configuration mode: After' corifigura~
tion'i.arising'. edgeon~T'il:ritia~es a. configuration read
opera~n;

Dt-~S-I/O

M1-"'flI) , '.,

Multi-~l'I.ction input

DualfunCfloniriput/outPuLDurlrlg'lnitial power up; thEistate of
M1!1hd,t.1l) detEirmihe~ fh~ configuration mode. After boilfiguratjoil"jS'eolnpjete, ~p outputs,;eoofigtJr~tiOn data during ~
c6nfigur'atidri' teadback operation'syrlC:ihrohously With' die
toggling:'of the GCLK Inpljt.
" '
-i!t~ET<
'

I~put. low level on this input after' configurafi~ncauses'~i1
regi:;ter elements internal to the LCA to be forced toO . .!f
asserted prior to the start of configuration, causes the LCA to
remain in the initialization+$te (configuration is not startEKt). If
asserted duringconfigurlllion t~e LCA returns to the initializa'
tion state.

A

Dual function~()utputlinputDuring configurationthe,LCA pulls
DONE low and releases it when cORfig\lration,lsicompIElte
(output isopElodrain). After configlJration iscompletEl. a falling'
edge on ~G inltiatilSs,nLCA programming cycle (if enabled
in thEt currerit configuration). This pin has an i!iternaluser"
enabled pull~uP'Tesi~tor.
'
.'
XTAL1.l/0
Dualfuo9tiOil input~ndI/O; Tllis pin maybe configured liy the
user"to bEl a Rorm!llJ/O pi.n;~quivalent te anyof.the general
purpose,1/0 pins. Alterrtamly; this pin and XTAL2 my be
used to connect a crystal for use with the internal crystal
oscillator cpQfig~ration. .

.,

Dualfunptionoutput a~d VO. Tois pin may QeCOnfrgured by
the user to be a normal tlOpin eqllivale\1~!w,aoy Itf~tle
gemttal.purP()S8<\lQ pins: .A!~r:oativEtly, this pirjuldXT'Al.1
may'!~cu~to.,CQr\necl:apl'ys~lfo~
witll,
cryElta( ~ciIJatQt~nfiQuiaiiqj1:: . ", . . ,.,.. ,.,
.. '., ..

uSe.

~~,!',,~;~." '-<~,:":: ':<~;' <~>«,' '~'~,~~l~'
1\.

,he imQr,oa,t
"} '>"t>

'QQnfigIJratiOJl,'.~·. depjendent!inpllt/Q\ltpIltCClKt .is . the
Ji\1a$ler QbrifiQ,ui'atiiln clockusetHo.•cotlfigur(i ,the, lCA; Insl~
tnodeit is 81'\ input; In.-all oth~;mCldesit.isan OlItput designeQ
to:providetl,leinp\jt, c1~9gof,,;ltdditionaLsiave molledaisy
e;hain COllIi1~ .. :le~,dEll/ices:Al)Ilrir1g, a donfiguratiQnTEi~d
~k operatiOIi'l.~LK.seJ:iteSaJLthe<;lock Input ,uSEid ,.to read
tbe;iitte~nalconjiUUration:.Csata:~',;<" ",(

ooU,-r~I/O ...... .,ii
..,"'."
f)uel (uftCtion·~~tput ariql/O;; S~ralpurp0$6.~ser:configUra-:

bl&, IIPPil1 ~!fl,/iinQ'riorrn8! :o~ratio~,Durfng configuratiOrSthe
'serialdata sl(ea,mElupplied from the first LCAto .LC~ .(fown~
thit'5erfal ttatlYthaih'is Qtitji,4t i>f\.OOUT.
;..'
.

..

"

.,'

.,

'.

aridllp. GenE!r!llp~.rpose u$er-configurable I/O' pinauring norm.al .. oper~,jon, b~ring m~ster mode,
configuration,this' pin is 'bft' 1 of'lha 8~bit parallel inplit data
bus (D1). During peripheral mode configOration,'a lowriivel"on
"WS indicates that. a, wrlte.'Operatiomjs >being perkinned, by
the controlling processor;·,See note;
.
D2~1I0.
.'.
.
, '.
• MtiJtltfunction"iiiptit and I/O;'General purpose'user-eonfig&ab1e.ii'Opin during normal. opei'il.tlori',1)uri'ng h18$termode
corifiguration;''ttiisPin is. bit 2 ofthe .$~bit' parallel input data
bus'(D2); pUring p$riJ)hefal mode' cORfiguratiori,a high 'level
.indicates that a writeoper'ati,0n is being pertormetiby
thEi tcintrollihg prQCEisSor:See note,' ,
'
,

on os

D3,.~£,o.:,,()

DONE-"-9G

~AL2-1I0

-RCLK-IIO
Dual function output and 110. General purpose user-configurable 110 pin during normal operation. During master mode
configuration, a low level outputon-RClKindicates that the
external memory device is 'beilig accesSed.
Do-DIN-I/O
Multi-functien input and 110. General purpose user-configUrable 110 pin during" normal" operation.. During master mode
configuration, this pin is bit l) of the8-bit parallel input data
bus.(Do). buring slave mode or peripheral mode'configuraticin,
this. pin is the sEirial inpUt data pin (DIN). "
,

".. ,.
M~ti"funp#OIl irip\;Jt' aQcl

",i'

119.'Gelleralpurpose user:collfigura~
til~ 1)0 pill dUring'normal'operatibn.;OUripg .master mode
configurlltion" this. pih is bit 30t the 8-bit. parallel input data.
bus (OS). During peripheral mode configuration, a low level on
...q:O ir:idic,8tes'thala writEl'op!lratiOn is being performed bY
thecontrollirig proce~r,,~e note~
D4--CE1~lio, ' " , : ' "
,
Multi·fun9ti~~iinput lind Ilo,Gell~raIPurposa usar-configurable .\lOPil'l&udr1g ,)normal' ope~tlon. , During, master" mode
confiQIJrati
this :pin is bit 4 Of th~ §-~itparaIJel;inpUt data
bus (04). OUringper:iphEiralmodeconfigur&tion,a lowlevel on
-CE1 indicates "that a writeoP"r4tion is being: performed Qy
the contr.olling prqceSsor.· S!,!Ern.ofEi~
.1'
,0.5-1/0, to D7.,.I/Q;\; ''i

on,

Input and IIQ;G~ner§l pUtpe~. USE!I~on'.igu(!lb.le 110 pins
during normal op!ltation., Ouri~ .master. mode., configuration,
these pins are bit~,5through 7~f the ~bit.P8rajjelinput da.~
bus (05-07).
.
"
'.

Ao-II0 .to. A15-liO
.Output and 1/0; General purpose usef-qonfigurablElIIO pins
during i'lorrual.ope~~on, DUrin9,: master. '.~.. ponfiguration
these .pins are.:addressoutpU\ pins (Ab-A15) 'u!ied to address·
the external storage elemen~,used.forconfigutation data.•

~otEt: .~!?~rtRrl!laperip~ei'at.~ode w,rite, :t~,!fOIl9wi~gI99icaf
eoml,)iitationis .n~"Elssal:Y:-WS.~;CE9·.cE'} ," '.' +,

.r:

t:urictt~810is~riPtion" . i'., . ~,. ."
line Mt064il! ,.a. bigh1>ertOrn:lance CMqSLogiCJCeIi·'Ai'tllY
•Provic\iOg" superiOl'systerrLperi0rmanceWith grelllast user,
flexibility ",~rnpreteuSel:;;COllfigur8bUitY provtdes .an ;optimized
solution Ie logie. implementatiOn ,J)roblems. ;.;
Tha'M2064 utltizes.a ),iniqueConfigurabte;L;ogiC Block.{CLB)
structlK8.:as'j1hEl,basic· f.unctionalbuilding 'black 'of ,the ,device;
Ea(lh ~;il!a combination,o#;./I pr()gl'l!lT)irl8ble .1O{jiC.funotiOn

~·,

AfDnatlt.........

s-s

Logie Cell ArrayTIl 112064
and a storage element. The CLB has the capability of performing any function of its inputs with the option of the output of
the storage element included in the input field. User-defined
logic is implemented in.a matrix of sixty-four CLBs which are
interconnected with user-configurable interconnect r\lsources.
Fifty-eight independently configurable I/O Blocks; each of
which can be a direct or latched input, a dir~ct or open drain
output, or a bidirectional I/O buffer; provide the interface to
external circuits. Input voltage levels are user definable and
may be either standard n.L or CMOS for all I/O Blocks,
depending on the user's configuration choice.
lJser-definable path selector or multiplexers are utilized to
select configuration,options for the CLBs and I/O Blocks.
These selectors are set in the desired state by the configuration data loaded into the device upon power up.

Logic
User logic is implemented in one or more CLBs which are
general purpose 4-input, 2-output elements. Figure 1 shows a
block diagram of a single CLB. Each element is composed of
a 4-input cOmbinational logic module with two outputs, a
general purpose storage element, and routing selection logic.
The module can generate any combinational logic function of
the four inputs, or it can generate any two independent
functions of any three of the four inputs. If a function of four
inputs is selected, that same fUnction will be .available on both
of the outputs of the combinational module. The inputs to the
combinational module are three of the four inputs to the CLB
(A, Band C) and either the 0 input to the CLB, or thea output
of the storage element.

x

either the A input to the CLB or from the F output of the
combinational logic module.
Clock for the storage element may be individually enabled or
disabled and can be driven by the clock input, K, to the CLB,
the C input to the CLB, or the G output of the combinational
logic module. Final outputs, X and Y, from the CLB can be
selected to be either of the two outputs, F and G, of the
combinational logic module, or the a output from the storage
element.

1/0 Elements
The M2064 contains fifty-eight user-configurable I/O -blocks
for connection to external circuits. Each block is a general
purpose device containing a three-state output buffer, an input
buffer, and an input flip-flop as shown in Figure 2. The input
buffer always reflects the status of the I/O pin or the contents
of the input flip-flop. If the flip-flop is selected, data present on
the I/O pin will be clocked to the input buffer by the I/O block
clock signal. All I/O blocks on a particular edge of the device
share it common I/O clock Signal. The output buffer may be
enabled, disabled, or under the control of the three-state
connection.
.

t - - - - - - TS

r-.-

DONE--N

.....,-1/0

g g g g

5g

g g g g g g g
M1· RO

110
VII
VII
VII

110
110

vee
VII

vo

_ON

5-1&

MonoIlthlcW"nlOries

PALASM® 2 Software

Introducing PALASM@2 Software
PALASM 2 software is a package that turns PAL device
Design Specification (PDS) files into input files for PAL device
programmers. PDS is a format for specifying a PAL circuit and
for creating inputs to a logic circuit. Using a text editor, you
create a PDS file that describes a PAL circuit. PALASM 2
software accepts the. file as input and performs a number of
functions under your control including:
•
•
•
•

PALASM
#2

o

Assembling PAL Design Specifications.
Generating PAL device fuse patterns in JEDEC format.
Reporting errors in syntax and assembly.
Allowing concise mnemonic names for long, frequently used
logic expressions through string substitution.

o

Functional differences from PALASM 1
PALASM 2 software is quite different from PALASM 1 in
imPlementation. It is composed of several interacting programs coupled by disk files. (Floppy based files slow interaction.· We recommend FlAM or hard disks for production use.)
The principal benefit of the reorganization is the freedom from
fixed limits within the design file.
The syntax of PALASM 2 software is significantly different
from that of PALASM 1. PALASM 2 software allows description of asynchronous devices like the 20RA 10 and devices of
much higher complexity such as MegaPAL devices.
The current version of PALASM 2 software omits several
features provided within PALASM 1. They are:
•
•
•
•
•

Fault coverage prediction for test vectors.
Automatic generation of documentation.
Device signal/pinout display.
Support of the security fuse.
Printing of logic equations for each product term in a fuse
plot.
Some of these omissions represent a change in philosophy;
others will be provided in later versions of the program.

PAL device
Programmer

Figure 1. Typical Computer Configuration

hequired Equipment
T.dS section describes computers and PAL device program-

mers supported by PALASM 2 software and provides information about necessary and optional PALASM 2 software.

r.omputers
PALASM 2 software operates with no user modification on the
following CPUs, provided certain minimum system requirements are satisfied: . It is usually provided as an executable
program, ready to run on any of these systems:
Minicomputers: VAX™ under VMSTM
Microcomputers: IBM-PCTM, _XTTM, _ATTM under MS-DOSTM
(256K RAM)
All systems must have a serial port (RS-232) for communication with the PAL device programmer. We also recommend
that floppy disk based systems be equipped with two disk
drives.

NOTE
Please refer to a PALASM 2 software order form for the
correct part number of the version of PALASM 2 software
deSigned for your CPU.

TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

6-2

Monolithic r!1!n
Memories InJrW

PALASM 2 Software
Software

Files

Following is a summary of all currently available programs.

1.

.PDS

2. PALASM 2

.TRE

3.
4.
5.

6.

.PDF
.XPT
.JED
.HST

7.

.TRF

8.

.JDC

PALASM 1 to PALASM 2 syntax conversion
1. PDSCNVT
2. PALASM 2
PALASM 2 syntax parser
3. XPLOT
PALASM 2 fuse map and JEDEC output
4. SIM
PALASM 2 simulator
5.ZHAL
ZHAL device fit
Supplementary Software
1. MENU
2. PC2
3. VTRACE

Simplified PALASM 2 user interface
Programmer interface program
Graph display simulator trace output

User PALASM 2 PLD design
description
PLO intermediate design
description
PLD architecture description data
Contains PLD fuse map data
Contains PLD fuse JEDEC data
Contains full simulation history
data
Contains user simulation trace
data
Contains both PLD fuse JEDEC
data and JEDEC test vectors

. PAL
PALASM1 input design file

.POS
PALASM2 Input design file

PALASM2. TRE

.XPT
.JEO

.H5T
. TRF
.JOC
Figure 2. PALASM Software Flow

Mono/ilhicWMemor;es

6-3

PALASM 2 Software

PDSCNVT

ZHAL

PDSCNVT allows you to interactively convert PAL "device
design specifications from the PALASM 1 format to PALASM
2 software. Input is a PALASM 1 formatted specification file,
and output is the equivalent design in PALASM 2· software
syntax.

ZHAL makes sure that a PAL device description will fit into the
ZHAL device architecture. ZHAL reads the description that
has been preprocessed by the PALASM 2 software program,
and a YES or NO answer is output. If the design fits, you must
send the PAL device De~ign Specification to Monolithic. Memories for mask processing. Before a description is rejected, the
prograrn will attempt to minimize the input equations to make
use of some sharing features in the ZHAL architecture. ZHAL
will also indicate what the error is before a no fit answer is
output.

PALASM 2
PALASM 2 is the fitst program you will use in the PALASM 2
software suite. It reads and validates your input - a PAL
device design specification - for correct design syntax. If an
error is detected, the program attempts to indicate where in
the input description the error has occurred. Recovery is
attempted after each error in order to catch as many errors as
possible on a single run. Only if no error is detected is an
intermediate specification file generated. This file contains the
input specification in a hierarchically structured form to enable
easy processing by follow-on programs. Further, it is guaranteed to be syntactically correct. This program recognizes input
deSCriptions for all current PAL devices.

XPLOT
XPLOT validates the architectural design of an input PAL
device description and produces fuse maps and JEDEC data
for a specified PAL device. Input is a set of Boolean equations
that has been preprocessed by the PALASM 2 program.
XPLOT checks the equations for consistency among themselves and with the specified PAL device. When an error is
detected, XPLOT attempts immediate recovery. In this way,
XPLOT spots as many errors as possible on each run. Only if
no errors are detected will the output fuse maps and JEDEC
data be generated. The architectural information for each PAL
device is read in from a file containing a profile description for
the specific PAL device.

NOTE
XPLOT will check only valid Monolithic Memories PAL devices.

SIM
SIM checks the functionality of a PAL device design. You will
run this program after XPLOT. If the design is architecturally
correct, however, you can run SIM directly after PALASM 2.
SIM reads a special simulation syntax that has been preprocessed by PALASM 2. It will simulate thE! operation of thePAL
device you specify, calculating the output values based on
input signals through the Boolean equations and any feedback. Output is a history file that traces the values of every pin
through a simulation sequence. A trace file, which is. a subset
of the history file, traces only the pins you specify in the
simulation syntax. If XPLOT has been run. and a JEDEC fuse
address file has been created, then SIM will add test vectors
to the JEDEC file that duplicate the simulation sequence when
the device is tested on a programrner. All JEDEC checksums.
are recalculated.

NOTE
SIM will test only valid Monolithic Memories PAL devices.

6-4

NOTE
ZHAL currently accepts designs only for valid Monolithic
Memories PAL devices.

MENU
MENU is an interactive program designed to simplify user
interface to PALASM 2 software. MENU's multiple choice
selection process offers you a number of options at each
stage. Once you have made a selection, your choice is
automatically executed. MENU makes the modular design of
the PALASM 2 software system invisible to you. All you need
to know is what you want to do, not how-to. For example, if
you select Simulation, the programs PALASM 2, XPLOT and
SIM automatically run in sequence, and your need to understand the functions of the individual programs is greatly
reduced.

PC2
PC2 enables communication .between PLD programmers and
IBMTM PC machines (-PC, -XT, -AT, etc.). It is a menu-driven
multiple-choice program that guides you through various options for programming and checking PLD devices.

VTRACE
VTRACE reads the trace output of the PALASM 2 software
simulator. The text-formatted data of the trace file is converted
into graphic form. VTRACE output looks very much like timing
diagrams of the simulation results.

Software Customization
For software development and user customization of PALASM
2 software, you will need a Pascal compiler/linker and a
second disk drive. These are necessary to create .the executable version of the program. Monolithic Memories recommends the Professional Pascal compiler (Microtek Inc.) which
was used to develop and test the programs on the IBM-PC.
PALASM 2 software is written in nearly ISO Standard Pascal
. to ease porting to many computer systems.
CAUTION

Porting PALASM 2 software to other computer systems will require you to Install and modify the original. source code. Allow at least two to four weeks of
software engineering time to complete this task.
Monolithic Memories makes no guarantee of the
portability of PALASM 2 software, and does not
provide support for such efforts or other user modification.

MonoIlth/CW Memories

PAL Device Applications

E.w

PAL Device Applications

Table of Contents
PAL20Ll0; 10-Bit Open Collector Buffer ..................................................7-3
PAL20L10; 10-Bit Open Collector Inverting Buffer ......................................7-5
PAL20X10; 10-Bit Addressable Register ..................................................7-7
PAL20L10; MC6800 Microprocessor Interface ........................................ 7-10
PAL 14L4; Quad 3:1 Multiplexer ........................................................... 7-13
PAL20X8; 4-Bit Counter With Register ................................................... 7-14
PAL20Xl0; 9-Bit Down Counter .......................................................... 7-16
PAL20Xl0; Refresh Clock Generator ................................................... 7-18
PAL16R8; Octal Addressable Register .................................................. 7-21
PAL16R8; Octal Addressable Register With Demux/Enables ...................... 7-24
PAL16R8; Octal Addressable Register With Demux/Clear .......................... 7-28
PAL16Cl; Rounding-Control Logic ....................................................... 7-31
PAL16R6; 4-Bit Counter With Terminal Count Lock .................................. 7-32
PAL18L4; Memory-MapPed I/O .......................................................... 7-34
PAL16R4; 74S508 Memory Map Interface #1
........................................ 7-36
PAL16R4; 74S508 Memory Map Interface #2 ........................................ 7-38
PAL20R4; 16 Input Registered Priority Encoder #1 .................................. 7-39
PAL16Cl; 16 Input Priority Encoder Interrupt Flag #2 ............................... 7-41
PAL20R4; 15 Input Registered Priority Encoder ....................................... 7-42
PAL16R4; 8 Input Registered Priority Encoder ........................................ 7-44
PAL16R8; Dual Stepper Motor Controller ............................................... 7-47
PAL20L10; Clean Octal Latch ; ........................................................... 7-49
PAL16R4; Shaft Encoder #1 ............................................................. 7-51
PAL16R8; Shaft Encoder #2 ............................................................. 7-54
PAL20Xl0; Shaft Encoder #3 ............................................................ 7-57
PAL6L16; Four-to-Sixteen Decoder ...................................................... 7-60
PAL8L14; PC I/O Mapper ................................................................. 7-61
PAL 16Cl; Octal Comparator .............................................................. 7-62
PAL16R8; Three-to-Eight Demultiplexer ................................................ 7-63
PAL16RP8; Basic Flip-Flops .............................................................. 7-64
PAL20Xl0; 9-Bit Register ...................................... , ..... ,; .................... 7-65
PAL20Xl0; 10-Bit Register ................................................................ 7-66
PAL64R32; 16-Bit Barrel Shifter ............... ; .......................................... 7-67
PAL32R16; 16-BitAddressable Register ............................................... 7-69
PAL16RP8; Traffic Signal Controller ..................................................... 7-71
PAL16RP6; Memory Handshake LogiC .................................................. 7-73
PAL16RP4; 4-Bit Counter .................................................................. 7-76
PAL20X8; 8-Bit Counter ................................. ; .................................. 7-77
PAL20Xl0; 9-Bit Counter ..... ; ............................................................ 7-78
PAL20RS10; 10-Bit.Counter .............................................................. 7-79
PAL20RA10, PAL16Cl; 5-Bit Up Counter .............................................. 7-80
PAL20RA10; 7-Bit I/O Port ................................................................ 7-83
PAL20RA10; Serial Data Link Controller ................................................ 7-85
PA1..20RA10,PAL20L10; Interrupt Controller .................................. ; ........ 7-88

7-2

Monolithic

W Memories

10-Bit Open Collector Buffer

Title

10-BIT OPEN COLLECTOR BUFFER
P7070

Pattern

Revision A
Author

VINCENT COLI
MMI SUNNYVALE, CALIFORNIA
10/21/S1

Company
Date

CHIP 10-BIT_OPEN_COLLECTOR_BUFFER PAL20LI0

lOCI DO Dl D2 D3 D4 D5 D6 D7 DS D9 GND
IOC2 Y9 YS Y7 Y6 Y5 Y4 Y3 Y2 Yl YO VCC
EQUATIONS
IF(OCl*/DO)

/YO

VCC

iYO= DO (TRUE)

IF(OCl*/Dl)

/Yl

VCC

iYl= Dl (TRUE)

IF(OCl*/D2)

/Y2

VCC

iY2= D2 (TRUE)

IF(OCl*/D3)

/Y3

VCC

iY3= D3 (TRUE)

IF(OCl*/D4)

/Y4

VCC

iY4= D4 (TRUE)

IF(OC2*/D5)

/Y5

VCC

iY5= D5 (TRUE)

IF(OC2*/D6)

/Y6

VCC

iY6= D6 (TRUE)

IF (OC2*/D7)

/Y7

VCC

iY7= D7 (TRUE)

IF(OC2*/DS)

/YS

VCC

iYS= DS (TRUE)

IF (OC2*/D9)

/Y9

= VCC

;Y9= D9 (TRUE)

=

;FUNCTION TABLE FOR PALASM 1
ilOC2 /OCI D9 DS D7 D6 D5 D4 D3 D2 Dl DO
;Y9 YS Y7 Y6 Y5 Y4 Y3 Y2 Yl YO

i
i/OC
;2 1

INPUT DATA
DDDDDDDDDD
9S76543210

OUTPUT DATA
YYYYYYYYYY
9S76543210

COMMENTS

LLLLLLLLLL
ZZZZZZZZZZ
ZLZLZLZLZL
LZLZLZLZLZ
ZZZZZLLLLL
LLLLLZZZZZ

TEST
TEST
TEST
TEST
TEST
TEST

;------------------------------------------------------------------LLLLLLLLLL
iL L

;L L
;L L

HHHHHHHHHH

iL L
iH L
iL H

XXXXXLLLLL
LLLLLXXXXX

i

HLHIJILHLHL
LHLHLHLHLH

L'S (TRUE D)
H'S (TRUE D)
EVEN CHECKERBOARD (TRUE D)
ODD CHECKERBOARD (TRUE D)
HI-Z FOR /OC2=H
HI-Z FOR /OCl=H

------------------------~-----------------,----------- ---------------

Monolithic

W MemorieS

7·3

10;oBIt Open Collector Buffer

; DESCRIPTION
; THE 10-BIT OPEN COLLECTOR BUFFER WILL OUTPUT THE INPUT DATA (D). THE
;OUTPUTS (Y) WILL BE EITHER L OR HI-Z.
;CERTAIN OUTPUTS WILL BE HIGH-Z (Y=Z) IF EITHER OUTPUT CONTROL LINE
;IS HIGH (jOC=H) REGARDLESS OF OTHER INPUTS. NOTE THAT OC2 CONTROLS
;OUTPUTS Y9-Y5 AND OCl CONTROLS OUTPUTS Y4-YO. OC2 AND OCl CONTROL
; INDEPENDENTLY.
;OPERATIONS TABLE:
jOC2

JOCl

D9-DO

Y9-Y5

Y4-YO

Z
X

x

D

D

OPERATION

----------------------------------------------------------HI-Z FOR UPPER 5 BITS

7-4

H

X

x

X
L

H
L

X
D

Z

HI-Z FOR LOWER 5 BITS
OUTPUT TRUE (L or HI-Z)

Monolithic WMemor/es

10-Sit Open Collector Inverting Buffer

Title

10-BIT OPEN COLLECTOR INVERTING BUFFER
P7071

Pattern

Revision A
VINCENT COLI
Company MMI SUNNYVALE, CALIFORNIA
Date
10/21/S1

Author

CHIP 10-BIT_OPEN_COLLECTOR_INVERTING_BUFFER PAL20LIO
/OC1 00 01 02 03 04 OS 06 07 OS 09 GNO
/OC2 Y9 YS Y7 Y6 YS Y4 Y3 Y2 Y1 YO VCC
EQUATIONS
IF(OCl* 00)

/YO '" VCC

;YO'" /00 (COMP)

IF(OC1* 01)

/Yl

vce

;Yl= /01 (COMP)

IF(OCl* 02)

/Y2

vce

;Y2'" /02 (COMP)

IF(OCl* 03)
IF(OCl* 04)

/Y3
/Y4

VCC
VCC

;Y3'" /03 (COMP)
;Y4'" /04 (COMP)

IF(OC2* OS)

/YS =

vcc

;YS'" /OS (COMP)

IF(OC2* 06)

/Y6

VCC

;Y6'" /06 (COMP)

IF(OC2* 07)

/Y7

VCC

;Y7", /07 (COMP)

IF(OC2* OS)

/YS

VCC

;YS= /OS (COMP)

IF(OC2* 09)

/Y9

VCC

;Y9= /09 (COMP)

;FUNCTION TABLE FOR PALASM 1
;/OC2 /OC1 09 OS 07 06 OS 04 03 02 01 00
Y9 YS Y7 Y6 YS Y4 Y3 Y2 Y1 YO
;2 1

INPUT OATA
9S76S43210

OUTPUT OATA;/OC
0000000000
9S76S43210
COMMENTS

;L L
;L L

LLLLLLLLLL
HHHHHHHHHH

iL
iL
iH
iL

HLHLHLHLHL
LHLHLHLHLH

ZZZZZZZZZZ
LLLLLLLLLL
LZLZLZLZLZ
ZLZLZLZLZL
ZZZZZLLLLL
LLLLLZZZZZ

YYYYYYYYYY

;-------------------------------------------------------------------L

L
L

H

XXXXXHHHHH
HHHHHXXXXX

TEST L'S (COMP 0)
TEST H'S (COMP 0)
TEST EVEN CHECKERBOARO (COMP 0)
TEST 000 CHECKERBOARO (COMP 0)
TEST HI-Z FOR /OC2"'H
TESTHI-Z FOR jOC1"'H

i--------------------------------------------------------------------

MonoI,"thic

W Memories

10..Bit Open: Collector Inverting Buffer
; DESCRIPTION
iTHE lO-BIT INVERTING OPEN COLLECTOR BUFFER WILL OUTPUT THE
iCOMPLEMENT OF THE INPUT DATA (D). THE OUTPUTS (Y) WILL BE
;EITHER L OR HI-Z.
;CERTAIN OUTPUTS WILL BE HIGH-Z (Y=Z) IF EITHER OUTPUT CONTROL
;LINE IS HIGHi(/OC=H) REGARDLESS OF OTHER INPUTS. NOTE THAT
iOC2 CONTROLS OUTPUTS X9-Y5 AND OCl CONTROLS OUTPUTS Y4-YO.
iOC2 AND OCl CONTROL INDEPENDENTLY.
;OPERATIONS TABLE:
/OC2
H

/OCl

X

X
H

L

L

D9-DO

Y9-Y5

Y4-YO

x

Z

X
D

X

X
Z

/D

/0

OPERATION
HI-Z FOR UPPER 5 BITS
HI-Z FOR LOWER 5 BITS
OUTPUT COMP (L or HI-Z)

Monolithic WMemories

10-Bit Addressable Register
Title
Pattern
Revision
Author
Company
Date

10-BIT ADDRESSABLE REGISTER
P7072 (PMSI407)
A
DANESH TAVANA
MMI SUNNYVALE, CALIFORNIA
04/05/82

CHIP

10-BIT_ADDRESSABLE_REGISTER

PAL20XIO

CLK /CLR /PR ABC D El E2 /E3 DIN GND
/OC Q9
Q8 Q7 Q6 Q5 Q4 Q3 Q2 Ql QO VCC
EQUATIONS
/QO

CLR
+ /PR*/QO
:+: /PR*/CLR* El* E2* E3*/D*/C*/B*/A*/QO* DIN
+ /PR*/CLR* El* E2* E3*/D*/C*/B*/A* QO*/DIN

CLEAR (LSB)
HOLD (lQO)
LOAD ( DIN:+.:/QO) IF /QO=H
LOAD (/DIN:+:/QO) IF /QO=L

/Ql:=
CLR
+ /PR*/Q1 ..
:+: IPR*/CLR* El* E2* E3*/D*/C*/B* A*/Ql* DIN
+ /PR*/CLR* El* E2* E3*/D*/C*/B* A* Ql*/DIN

iCLEAR
iHOLD (lQl)
iLOAD ( DIN:+:/Ql) IF/Ql=H
;LOAD (lDIN:+:/Ql) IF /Ql=L

/Q2:=
CLR
+ /PR*/Q2
:+: IPR*/CLR* El* E2* E3*/D*/C* B*/A*/Q2* DIN
+ /PR*/CLR* El* E2* E3*/D*/C* B*/A* Q2*/DIN

CLEAR
HOLD (lQ2)
LOAD .. ( DIN: +: /Q2) IF /Q2=H
LOADUDIN:+:/Q2) IF /Q2",L

/Q3:=
CLR
+ /PR*/Q3
:+: /PR*/CLR* El* E2* E3*/D*/C* B* A*/Q3* DIN
+ /PR*/CLR* El* E2* E3*/D*/C* B* A* Q3*/DIN

CLEAR
HOLD (lQ3)
LOAD ( DIN:+:/Q3) IF/Q3=H
LOAD (lDIN:+:/Q3) IF /Q3=L

CLR
+ IPR*/Q4
:+: /PR*/CLR* El* E2* E3*/D* C*/B*/A*/Q4* DIN
+ /PR,*/C:LR,* El* E2* E3*/D* C*/B*/A* QH/DIN

CLEAR
HQLD (lQ4)
LOAD ( DIN:+:/Q4) IF. /Q4=H
LOAD (lDIN:+:/Q4) IF /Q4=L

IQ5:=

CLR
+ IPR*/Q5
:+: IPR*/CLR* El* E2* E3*/D* C*/B* A*/Q5* DIN
+ IPR*/CLR* El.* E2* E3*/D* C*/B* A*Q5*/DIN

CLEAR
HOLD (lQ5)
LOAD ( DIN:+:/Q5) IF /Q5=H
LOAD (lDIN:+:/Q5) IF /Q5=L

/Q.6:=
CLR.
+ /FR*/Q6:
:+: /PR*/CLR* El* E2* E3*/D* c* B*/A*/Q6* DIN
.+ IPR*/CLR* El* E2* E3*/D* c* B*/A* Q6*/DIN

CLEAR
HOLD (lQ6)
LOAD ( DIN:+:/Q6) IF /Q6=H
LOAD (jDIN:+:/Q6) IF /Q6=L

/Q7:=
CLR
:+: /PR*/CLR* El* E2* E3*/D* C* B* A*/Q7* DIN
+ /PR*/CLR* El* E2* E3*/D* C* B* A* Q7*/DIN

CLEAR
+ /PR*/Q7
LOAD ( DIN:+:/Q7) IF /Q7=H
LOAD (lDIN:+:/Q7) IF /Q7=L

/Q8:=
CLR
+ IPR*/Q8
:+: IPR*/CLR* El* E2.* E3* D*/C*/B*/A*/Q8* DIN
+ /PR*/CLR* El* E2* E3* D*/C*/B*/A* Q8*/DIN

CLEAR
HOLD (lQ8)
LOAD ( DIN:+:/Q8) IF /Q8=H
LOAD (lDIN:+:/Q8) IF /Q8=L

~';'

IQ4:=

Monolithic WMemorles

7·7

10-Bit Addressable Register
/Q9 :=
CLR
+ /PR*/Q9
:+: /PR*/CLR* E1* E2* E3* D*/C*/B* A*/Q9* DIN
+ /PR*/CLR* E1* E2* E3* D*/C*/B* A* Q9*/DIN

; CLEAR (MSB)
; HOLD (jQ9)
; LOAD ( DIN:+:/Q9) IF /Q9=H
; LOAD (jDIN:+:/Q9) IF /Q9=L

;FUNCTION TABLE FOR PALASM 1
i/OC CLK /CLR /PR /E3 E2 E1 D C B A DIN Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 QO
i

iCONTROL -----FUNCTIONS---i/OC CLK /CLR /PR /E3 E2 E1

---INPUTS-D C B A DIN

-----OUTPUTS------Q Q Q Q Q Q Q Q Q Q
987 654 3 2 1 0

COMMENTS

HHHHHHHHHH
H H H H H H H H H L
H H H H H H H H L L
Hg H H H H H L L L
HHHHHHLLLL
HHHHHLLLLL
H H H H L L L L L L
H H H L L L L L L L
H H L L LL L L L L
H L L L L L L L L L
LLLLLLLLLL
H L L L L L L L L L
H H L L L L L L L L
HHHLLLLLLL
H H H H L L L L L L
HHHHHLLLLL
HHHHHHLLLL
H H H H H H H L L L
HHHHHHHHLL
HHHHHHHHHL
HHHHHHHHHH
H H H H H H H H H H
H H H H HH H H H L
HH H H HH H H H L
HHHHHHHLHL
H H H H HH H L H L
HHHHHLHLHL
H H H H H L H L H L
HHHLHLHLHL
HHHLHLHLHL
HLHLHLHLHL
HLHLHLHLHL
Z Z Z Z Z Z Z ZZ Z

/PR OVRRD ENABLE
LOAD QO WITH DIN
LOAD Q1 WITH DIN
LOAD Q2 WITH DIN
LOAD Q3 WITH DIN
LOAD Q4 WITH DIN
LOAD Q5 WITH DIN
LOAD Q6 WITH DIN
LOADQ7 WITH DIN
LOAD Q8 WITH DIN
LOAD·Q9 WITH DIN
LOAD Q9 WITH DIN
LOAD Q8 WITH DIN
LOAD Q7 WITH DIN
LOAD Q6 WITH DIN
LOAD Q5 WITH DIN
LOAD Q4 WITH DIN
LOAD Q3 WITH DIN
LOAD Q2 WITH DIN
LOAD Q1 WITH DIN
LOAD QO WITH DIN
HOLD STATE
LOAD QO WITH DIN
HOLD STATE
LOAD Q2 WITH DIN
HOLD STATE
LOAD 04 WITH DIN
HOLD STATE
LOAD Q6 WITH DIN
HOLD STATE
LOAD Q8 WITH DIN
HOLD STATE
TEST HI-Z

j------------------------------------------------------------------------------L
L L L L L LL L L L /CLR OVRRD /PR
C
L
L
X X
X
X X X X
X
L
L
L

L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

X

X

X

X X X X

X

L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
H

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
H
H
L
H
L
H
H

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
H
L
H
H
H
H

L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L

L L
L H
H L
H H
L L
L H
H L
H H
L L
L H
L H
L L
H H
H L
L H
L L
H H
H L
L H
L L

L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H

X X X X

X

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L

L L L L

L

X X X X

X

L L H L

L

X X X X

X

L H L L

L

X X X X

X

L H H L

L

X X X X

X

H L L L

L

X X X X
X X X X

X
X

X
X
X X X
X
;~---------------.--------------------------------'--- --------------------------

7-8

Monolithic WMemor/es

10-Bit Addressable Register
; DESCRIPTION
;THE 10-BIT ADDRESSABLE REGISTER IS A SYNCHRONOUS GENERAL PURPOSE ADDRESSABLE
;REGISTER WITH CLEAR, PRESET, AND ENABLE. THE OUTPUT REGISTER (Q) IS SELECTED
;BY THE INPUT ADDRESS PINS (A,B/C,D). THE DATA (DIN) IS LOADED INTO THE
;SELECTED OUTPUT REGISTER ON THE RISING EDGE OF THE CLOCK (CLK) IF THE CHIP IS
;ENABLED (El=HIGH,E2=HIGH,/E3=LOW). ALL OTHER OUTPUTS HOLD THEIR PREVIOUS
;STATES DURING THE LOAD OPERATION. ANY OTHER COMBINATION OF THE ENABLE PINS
;(El,E2,/E3) WILL DISABLE THE REGISTER AND ALL OUTPUTS WILL HOLD THEIR PREVIOUS
;STATES. CLEAR (/CLR) AND PRESET (/PR) ARE ACTIVE LOW PINS WHICH SET THE
;REGISTERS TO ALL HIGH OR LOW RESPECTIVELY.
;CLEAR OVERRIDES PRESET AND ENABLE, PRESET OVERRIDES ENABLE.
;THESE FUNCTIONS ARE EXERCISED IN THE FUNCTION TABLE AND SUMMARIZED IN THE
;OPERATIONS TABLE:
;/OC CLK

/CLR /PR /E3 E2 El

D C B A

DIN

Q9-QO

X

X
X
X
X
DIN
X

x

L
H
Q
Q
Q
DIN
Q
Q

X

Q

OPERATION

i-----------------------------------------------------------------------------H
HI-Z
X
X
X
X X X
X X X X
X
Z
L
L
L
L
L
L
L
L
L
L

C
C
C
C
C
C
C
C
C
C

L
H
H
H
H
H
H
H
H
H

L
L
H
H
H
H
H
H
H
H

X
X
L
L
L
L
H
H
H
H

X
X
L
L
H
H
L
L
H
H

X
X
L
H
L
H
L
H
L
H

X
X
X
X
X
D
X
X
X
X

X
X
X
X
X
C
X
X
X
X

X
X
X
X
X
B
X
X
X
X

X
X
X
X
X
A
X
X
X
X

x

Q

CLEAR
PRESET
HOLD PREVIOUS STATES
HOLD PREVIOUS STATES
HOLD PREVIOUS STATES
LOAD DIN TO ADDRESSED OUTPUT
HOLD PREVIOUS STATES
HOLD PREVIOUS STATES
HOLD PREVIOUS STATES
HOLD PREVIOUS STATES

;---------------------------------------~------------- -------------------------

OUTPUT SELECT TABLE;
D C B A

DIN

Q9

Q8

Q7

Q6

Q5

Q4

Q3

Q2

Ql

QO

LLLH
L L H L
LLHH
LHLL
L H LH
LHHL
LHHH
H L L L
HLLH
HLHL
H L .HH
H H X X

DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN

Q9
Q9
Q9
Q9
Q9
Q9
Q9
Q9
DIN
Q9
Q9
Q9

Q8
Q8
Q8
Q8
Q8
Q8
Q8
DIN
Q8
Q8
Q8
Q8

Q7
Q7
Q7
Q7
Q7
Q7
DIN
Q7
Q7
Q7
Q7
Q7

Q6
Q6
Q6
Q6
Q6
DIN
Q6
Q6
Q6
Q6
Q6
Q6

Q5
Q5
Q5
Q5
DIN
Q5
Q5
Q5
Q5
Q5
Q5
Q5

Q4
Q4
Q4
DIN
Q4
Q4
Q4
Q4
Q4
Q4
Q4
Q4

Q3
Q3
DIN
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3

Q2
DIN
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2.

DIN
Ql
Ql
Ql
Ql
Ql
Ql
Ql
Ql
Ql
Ql
Ql

QO
QO
QO
QO
QO
QO
QO
QO
QO
QO
QO
QO

-------------------------------------------------------L L L L
DIN
Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Ql DIN

_:..._--'--':""- ..... _---------------------------------------------

Monolithic

W Memories

7-9

D

MC6800 Microprocessor Interface
Title
Pattern
Revision
Author
Company
Date

MC6800 MICROPROCESSOR INTERFACE
P7073
A
COLI/SACKETT
MMI SUNNYVALE, CALIFORNIA
O~/l4/82

CHIPMC6800~MICROPROCESSOR_INTERFACE

PAL20LlO

Al5 Al4 Al3 Al2
All
NC
/S
/R
PH2
VMA /ARGND
EN IN EN /IO /RAM4 /RAM3 /RAM2 /RAMl /PROM2 /PROMl /RSET VUA VCC
EQUATIONS

*
*

IF (VCC)

PROMl

Al510 Al410 Al3* Al2

IF (VCC)

PROM2

Al510 Al410 Al31o/A12

IF(VCC)

RAMl

= /Al51o/Al41o/A131o/Al21o/All1o VMA10 PH21o/RSET

;RAMl,

0OOO-07FF

IF (VCC)

RAM2

= /A151o/Al41o/A131o/A121o All10 VMA10 PH21o/RSET

;RAM2,

0800-0FFF

IF (VCC)

RAM3

= /A151o/A141o/A131o A121o/All1o VMA10 PH21o/RSET

;RAM3,

lOOO-17FF

IF(VCC)

RAM4

= /Al51o/A141o/A131o A1210 All10 VMA10 PH21o/RSET

;RAM4,

l800-1FFF

IF(VCC)

IO

;I/O,

D800-DFFF

;PROM1, FOOO-FFFF

VMA10 PH21o/RSET

;PROM2, EOOO-EFFF

Al510 A141o/A131o A1210 All10 VMA10 PH21o/RSET

/PROM11o/PROM21o/RAM11o/RAM21o/RAM31o/RAM41o/I01o VMA1o/RSET ;EN=/VUA

IF(VCC) /EN

ENIN

IF (VCC) /VUA
IF (VCC)

VMA10 PH21o/RSET

RSET

; ASSERTIVE HIGH VUA SIGNAL (INVERT EN FEEDBACK)
;SET
;RESET
;AUTO RESET

S
+ /R * RSET
+ /AR1o RSET

; FUNCTION TABLE FOR PALASM 1
;A15 A14 A13 A12 All/S /R /AR /RSET PH2 VMA /PROMl /PROM2 /RAMl /RAM2 /RAM3
;/RAM4 /IO EN ENIN VUA
;ADDRl S-R
/RE
;54321 /S /R /AR SET

PH2 VMA

PROM
1 2

--RAM-1 2 3 4

I/O

ENABLE
OUT IN VUA

COMMENT

;-------------------------------------------~-------~--------------------------

;HHHHX
;HHHHX
;HHHHX
;HHHHX
;HHHHX
;HHHLX
;LLLLL
.;LLLLH
;LLLHL
;LLLHH
;HHLHH

L
H
H
H
H
H
H
H
H
H
H

H L
L H
L L
L L
L L
L L
L L
L L
L L
L L
L L

L
L
H
H
H
H
H
H
H
H
H

L
L
L
H
H
H
H
H
H
H
H

H
H
H
L
H
H
H
H
H
H
H

H
H
H
H
L
H
H
H
H
H
H

H
H
H
H
H
L
H
H
H
H
H

HHHH
HHHH
HHHH
HHHH
HHHH
HHHH
L HHH
HLHH
HHLH
HHHL
HHHH

H
H
H
H
H
H
H

H
H
L
H
H
H

H

H
H
H
H

H
H
L

H

H
H
L
H
H
H
H
H
H
H
H

L
L
H
L
L
L
L
L
L
L
L

RESET (jS=L)
AUTO-RESET
NO SELECT PH2=L
NO SELECT VMA=L
SELECT PROMl
SELECT PROM2
SELECT RAMl
SELECT RAM2
SELECT RAM3
SELECT RAM4
SELECT 1/0 PORT

;------------------------------------------------------------------------------

7-10

Monolithic

m

Memories

MC6800 Microprocessor Interface
; DESCRIPTION
;THIS PAL20L10 INTERFACES BETWEEN THE MOTOROLA MC6800 MICROPROCESSOR AND ITS
;SYSTEM COMPONENTS ON A SINGLE BOARD COMPUTER. THE FUNCTIONS IT PERFORMS,
;PREVIOUSLY DONE WITH RANDOM LOGIC ARE: ADDRESS DECODING, MEMORY AND I/O
; SELECT, RESET SIGNAL GENERATION, AND CONTROL OF THE BUFFER WHICH INTERFACES
;THE DATA BUS TO OTHER BOARDS IN THE SYSTEM.

MonoiithJcIRlFJl·Memor/es

1·11

MC6800 Microprocessor Interface
;FUNCTION TABLE FOR PALASM 1
;B A lCO lCl· lC2 2CO 2Cl 2C2 3CO 3Cl 3C2 4CO 4Cl 4C2 lY 2Y 3Y 4Y
SEL

------INPUTS------ --OUTPUTS-COMMENTS
lC
2C
3C
4C
B A 012 012 012 012 lY 2Y 3Y 4Y
;--------------------------------------------------~---L L LHH HHH HHH HHH
L H H H
lCO=O
L L HHH LHH HHH HHH
H L H H
2CO=0
L L HHH HHH LHH HHH
H H L H
3CO=0
L L HHH HHH HHH LHH
H H H L
4CO=0
L L HLL LLL LLL LLL
H L L L
lCO=l
L L LLL HLL LLL LLL
L H L L
2CO=1
L L LLL LLL HLL LLL
L L H L
3CO=1
L L LLL LLL LLL HLL
L L L H
4CO=1
L L HHH HHH HHH HHH
H H H H
TOGGLE LINES
L H HLH HHH HHH HHH
L H H H
lCl=O
L H HHH HLH HHH HHH
H L H H
2Cl=0
L H HHH HHH HLH HHH
H H L H
3Cl=0
L H HHH HHH HHH HLH
H H H L
4Cl=0
L H LHL LLL LLL LLL
H L L L
lCl=l
L H LLL LHL LLL LLL
L H L L
2Cl=1
L H LLL LLL LHL LLL
L L H L
3Cl=1
L H LLL LLL LLL LHL
L L L H
4Cl=1
L H HHH HHH HHH HHH
H H H H
TOGGLE LINES
H L HHL HHH HHH HHH
L H H H
lC2=0
H L HHH HHL HHH HHH
H L H H
2C2=0
H L HHH HHH HHL HHH
H H L H
3C2=0
H L HHH HHH HHH HHL
H H H L
4C2=0
H L LLH LLL LLL LLL
H L L L
lC2=1
H L LLL LLH LLL LLL
L H L L
2C2=1
H L LLL LLL LLH LLL
L L H L
3C2=1
H L LLL LLL LLL LLH
L L L H
4C2=1
H L HHH HHH HHH HHH
H H H H
TOGGLE LINES
H H LLL LLL LLL LLL
H H H H
SELECT = 4
HH HHH HHH HHH HHH
H H H H
TOGGLE LINES

;------------------------------------------------------; DESCRIPTION

; THIS IS AN EXAMPLE OF A QUAD 3-TO-l MULTIPLEXER USING A PAL18L4. SELECT
;LINES A,B ARE ENCODED IN BINARY, WITH A REPRESENTING THE LSB. THE OUTPUTS
; (Y) ARE ALL HIGH IF THE SELECT LINES ARE BOTH HIGH (B,A=H).
OPERATIONS TABLE:
INPUT
SELECT
B A

OUTPUTS
Y

---------------L
L
H
H

L
H
L
H

CO
Cl
C2
H

----------------

7-12

TB00510M

Mono/iihicWMemorifl.

Quad 3: 1 Multiplexer
Title
Pattern
Revision
Author
Company
Date

QUAD 3:1 MULTIPLEXER
P7074
A
VINCENT COLI
MMI SUNNYVALE, CALIFORNIA
01/05/82

CHIP QUAD_3:l_MULTIPLEXER PAL14L4
lCO lCl lC2 2CO 2Cl 2C2 3CO 3Cl 3C2 GND
A VCC
4CO 4Cl 4C2 4Y 3Y 2Y lY B
EQUATIONS

+
+

/B*/A * /lCO
/B* A * /lCl
B*/A * /lC2

; SELECT INPUT lCO
; SELECT INPUT lCl
; SELECT INPUT lC2

+
+

/B*/A * /2CO
/B* A * /2Cl
B*/A * /2C2

; SELECT INPUT 2CO
; SELECT INPUT 2Cl
; SELECT INPUT 2C2

+
+

/B*/A * /3CO
/B* A * /3Cl
B*/A * /3C2

;SELECT INPUT 3CO
; SELECT INPUT 3Cl
; SELECT INPUT 3C2

+
+

/B*/A * /4CO
IB* A * /4Cl
B*/A * /4C2

; SELECT INPUT 4CO
iSELECT INPUT 4Cl
; SELECT INPUT 4C2

flY

/2Y

/3Y

/4Y

MonoIlthicWMemories

7-t3

4·Bit Counter With Register

Title
Pattern
Revision
Author
Company
Date

4-BIT COUNTER WITH REGISTER
P7075
A
MIKE VOLPIGNO
MONOLITHIC MEMORIES INC NEWTON, MASSACHUSETTS
11/20/81

CHIP 4-BIT_COUNTER_WITH_REGISTER PAL20X8
CLK DO Dl D2 D3 /RCLR /RLD SEL /CCLR /CLD EP GND
/OC RCO C3 C2 Cl CO R3 R2 Rl RO ET VCC
EQUATIONS
/CO :=

CCLR

;CLEAR COUNTER
; COUNT
; COUNT
;LOAD COUNTER FROM REGISTER

+ /CLD*/CCLR* EP* ET
:+: /CLD*/CCLR*/CO
+
CLD*/CCLR*/RO

/Cl :=

CCLR

;CLEAR COUNTER
; COUNT
; COUNT
; LOAD COUNTER FROM REGISTER

+ /CLD*/CCLR* EP* ET* CO
: +: /CLD*/CCLR*/Cl
+
CLD*/CCLR*/Rl

/C2 :=

CCLR
/CLD*/CCLR* EP* ET* CO* Cl
: +: /CLD*/CCLR*/C2
+
CLD*/CCLR*/R2

;CLEAR COUNTER
; COUNT
; COUNT
;LOAD COUNTEF FROM REGISTER

+

/C3 :=

CCLR

+ /CLD*/CCLR* EP* ET* CO* Cl* C2
: +: /CLD*/CCLR*/C3
+
CLD*/CCLR*/R3

;CLEAR COUNTER
; COUNT
; COUNT
;LOAD COUNTER FROM REGISTER

RCLR
/RCLR*RLD*/SEL*/DO
: +: /RCLR* RLD* SEL*/CO
+ /RCLR* /RLD* /RO

;CLEAR REGISTER
;LOAD REGISTER FROM DATA
;LOAD REGISTER FROM COUNTER'
;HOLD

RCLR
/RCLR* RLD*/SEL*/Dl
:+: /RCLR* RLD* SEL*/Cl
+ /RCLR*/RLD*/Rl

;CLEAR REGISTER
;LOAD REGISTER FROM DATA
;LOAD REGISTER FROM COUNTER
; HOLD

/RO :=
+

/Rl :=
+

/R2 :=

RCLR

+ /RCLR* RLD*/SEL*/D2
:+: /RCLR*RLD* SEL*/C2
+ /RCLR*/RLD*/R2

;CLEAR REGISTER
;LOAD REGISTER FROM DATA
;LOAD REGISTER FROM COUNTER
; HOLD

RCLR
/RCLR* RLD*/SEL*/D3
:+: /RCLR* RLD* SEL*/C3
+ /RCLR* /RLD* /R3

;CLEAR REGISTER
;LOAD REGISTER FROM DATA
;LOAD REGISTER FROM COUNTER
; HOLD

/R3 :=
+

IF (VCC) /RCO

7-14

=

ET* CO* Cl* C2* C3

Monolithic

;TERMINAL COUNT

W Memories

4·Bit Counter With Register
;FUNCTION TABLE FOR PALASM 1
;CLK IRCLR IRLD SEL ICCLR ICLD EP ET D3 D2 D1 DO
;R3 R2 R1 RO C3 C2 C1 CO IRCO

I
R

I

I

C I

C C R S C C

R

L L L ELL E E D--D R--R C--C C
K R D L R D P T 3 0 3 0 3 0 0

COMMENTS

;-------------------------------------------~--------- ---------------

C L X X X X X X XXXX LLLL XXXX X
C H L L X X X X HHHH HHHH XXXX X
C H H X H L X X XXXX HHHH HHHH X
C H H X H H L H XXXX HHHH HHHH H
C H H X H H H H XXXX HHHH LLLL L
C H H X H H H H XXXX HHHH LLLH L
C H H X H H H H XXXX HHHH LLHL L
C H H X H H H H XXXX HHHH LLHH L
C H H X H H H H XXXX HHHH LHLL L
C H H X H H H H XXXX HHHH LHLH L
C H H X H H H H XXXX HHHH LHHL L
CHHXHHHHXXXXHHHHLHHHL
C H H X H H H H XXXX HHHH HLLL L
C H H X H H H H XXXXHHHH HLLH L
C H H X H H H H XXXX HHHH HLHL L
C H H X H H H H XXXX HHHH HLHH L
C H H X H H H H XXXX HHHH HHLL L
C H H X H H H H XXXX HHHH HHLH L
C H H X H H H H XXXX HHHH HHHL L
C H L H H H H L XXXX HHHL HHHL L
C H H X L X X X XXXX HHHLLLLL L

CLEAR REGISTER
LOAD REGISTER HI FROM DATA
LOAD COUNTER FROM REGISTER
ENABLE RCO AND HOLD COUNT
COUNT AND ROLLOVER
INCREMENT COUNTER

"
"
"
"
"
"
"
"
"
"
"
"
"
LOAD REGISTER

FROM COUNTER
HOLD REGISTER, CLEAR COUNTER

i-~--------------------------------------------------- ----------------

;DESCRIP'l'ION
;THIS PAL DESIGN SPECIFICATION DESCRIBES A 4-BIT SYNCHRONOUS COUNTER WITH
;4-BIT REGISTER. DATA CAN BE LOADED TO THE COUNTER FROM THE REGISTER. IT
; CAN ALSO BE SYNCHRONOUSLY CLEARED. THE REGISTER CAN BE LOADED FROM EITHER
;THE COUNTER OR THE DATA INPUTS UNDER CONTROL OF THE SEL INPUT. THE REGISTER
;CAN ALSO BE SYNCHRONOUSLY CLEARED. THE COUNTER AND REGISTER HAVE A COMMON
;CLOCK FOR SYNCHRONOUS OPERATION.

Monolithic WMemorles

7·15

9·Bit Down Counter
Title
Pattern
Revision
Author
Company
Date

9-BIT DOWN COUNTER
P7076
A
BIRKNER/COLI/LEE
MMI SUNNYVALE, CALIFORNIA
01/12/83

CHIP 9-BIT_DOWN_COUNTER PAL20X10
CLK DO D1 D2 D3 D4 DS D6 D7 D8 /LD GND
IOC /BO Q8 Q7 Q6 QS Q4 Q3 Q2 Q1 QO VCC
EQUATIONS

IQO := /LD*/QO
+
LD*/DO
:+: /LD

HOLD QO
LOAD DO (LSB)
COUNT DOWN

/Q1 := /LD*/Q1
+
LD*/D1
:+: /LD*/QO

;HOLD Q1
;LOAD D1
;COUNT DOWN

/Q2 := /LD*/Q2
+
LD*/D2
:+: /LD*/QO*/Q1

;HOLD Q2
;LOAD D2
;COUNT DOWN

/Q3 := /LD*/Q3
+
LD*/D3
:+: /LD*/QO*/Q1*/Q2

;HOLD Q3
;LOAD D3
;COUNT DOWN

/Q4 := /LD*/Q4
+
LD*/D4
:+: /LD*/QO*/Q1*/Q2*/Q3

;HOLD Q4
;LOAD D4
;COUNT DOWN

/QS := /LD*/QS
+
LD*/DS
:+: /LD*/QO*/Q1*/Q2*/Q3*/Q4

;HOLD QS
;LOAD DS
;COUNT DOWN

/Q6 :=

/LD*/Q6
LD*/D6
:+: /LD*/QO*/Q1*/Q2*/Q3*/Q4*/QS

;HOLD Q6
;LOAD D6
;COUNT DOWN

/Q7 := /LD*/Q7
+
LD*/D7
:+: /LD*/QO*/Q1*/Q2*/Q3*/Q4*/QS*/Q6

;HOLD Q7
;LOAD D7
;COUNT DOWN

/Q8 := /LD*/Q8
+
LD*/D8
:+: /LD*/QO*/Q1*/Q2*/Q3*/Q4*/QS*/Q6*/Q7

;HOLD Q8
;LOAD D8 (MSB)
;COUNT DOWN

+

BO:=
+

7·16

/LD* QO*/Q1*/Q2*/Q3*/Q4*/QS*/Q6*/Q7*/Q8
LD*/DO*/D1*/D2*/D3*/D4*/DS*/D6*/D7*/D8

;CARRY OUT (ANTICIPATE COUNT)
;CARRY OUT (ANTICIPATE LOAD)

Monoilthlcm Memories

9·Bit Down Counter
;F
;CLK 10C ILD D8 D7 D6 D5 D4 D3 D2 D1 DO IBO Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 QO
DATA IN
DDDDDDDDD
876543210

; CONTROL
;CLK 10C ILD

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
L
C
C
C
X
i

L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H

L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
H
H
H
H
X

LLLLLLLLL

xxxxxxxxx
LLLLLLLLH
xxxxxxxxx
LLLLLLLHH
xxxxxxxxx
LLLLLLHHH
xxxxxxxxx
LLLLLHHHH
xxxxxxxxx
LLLLHHHHH
xxxxxxxxx
LLLHHHHHH
xxxxxxxxx
LUIHHHHHH
xxxxxxxxx
LHHHHHHHH
xxxxxxxxx
HHHHHHHHH
xxxxxxxxx
HHHHHHHLL
xxxxxxxxx
xxxxxxxxx
xxxxxxxxx
xxxxxxxxx
xxxxxxxxx
xxxxxxxxx

IBO

DATA OUT
QQQQQQQQQ
876543210

COMMENT

L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Z

LLLLLLLLL
HHHHHHHHH
LLLLLLLLH
LLLLLLLLL
LLLLLLLHH
LLLLLLLHL
LLLLLLHHH
LLLLLLHHL
LLLLLHHHH
LLLL.LHHHL
LLLLHHHHH
LLLLHHHHL
LLLHHHHHH
LLLHHHHHL
LLHHHHHHH
LLHHHHHHL
LHHHHHHHH
LHHHHHHHL
HHHHHHHHH
HHHHHHHHL
HHHHHHHLL
HHHHHHLHH
HHHHHHLHH
HHHHHHLHL
HHHHHHLLH
HHHHHHLLL
ZZZZZZZZZ

LOAD (BORROW)
DECREMENT
LOAD
DECREMENT (BORROW)
LOAD
DECREMENT
LOAD
DECREMENT
LOAD
DECREMENT
LOAD
DECREMENT
LOAD
DECREMENT
LOAD
DECREMENT
LOAD
DECREMENT
LOAD
DECREMENT
LOAD
DECREMENT
HOLD
DECREMENT
DECREMENT
DECREMENT
TEST HI-Z

------------------'----------------------------------~ ------------

; DESCRIPTION
;THE 9-BIT SYNCHRONOUS COUNTER HAS PARALLEL LOAD, DECREMENT, AND HOLD
; CAPABILITIES. .DATA (D8-DO) IS LOADED INTO THE OUTPUT REGISTER (Q8-QO) WHE.N THE
;LOAD INPUT IS TRUE. (jLD=L) AND A .POSITIVE EDGE PULSE .IS RECEIVED ON THE CLOCK
;PIN (CLK). THE COUNTER WILL DECREMENT IF A CLOCK PULSE IS RECEIVED WITH THE
;LOAD INPUT BEING FALSE (jLD=H). THE OPERATION IS A HOLD IF NO CLOCK PULSE IS
;RECEIVED REGARDLESS OF ANY OTHER INPUTS.
;THE BORROW OUT PIN (jBO) SHOWS HOW TO IMPLEMEN.T A BORROW OUT USING A REGISTER
;BY ANTICIPATED ONE COUNT BEFORE THE TERMINAL COUNT IF COUNTING AND THE TERMINAL
;COUNT IF LOAPING.
;OPERATIONS TABLE:
10C

CLK

ILD

D8-DO

H

X
L
C
C

x

x

L
L
L

Q8-QO

OPERATION

Z

HI-Z
HOLD
LOAD
DECREMENT

X

x

IQ

L
H

D

D

X
Q MINUS 1
------------------~---------------------------

Monolithic WMemories

7-17

Refresh Clock Generator

Title
Pattern
Revision
Author
Company
Date

REFRESH CLOCK GENERATOR
P7o.77

A
FRANK LEE
MMI SUNNYVALE, CALIFORNIA
0.8/0.3/82

CHIP REFRESH CLOCK GENERATOR PAL2o.Xlo.
CLK /LD F3 F2 F1 Fo. M3 M2·M1Mo. /HOLD GND
/OC RFCK Qo. Q1 Q2 Q3 Q4 Q5 Q6 Q1 /INITVCC
EQUATIONS
INIT

:=

/Qo.

:= /INIT*/Qo.
:+: /INIT*/HOLD

; DECREMENT
;HOLD

/Q1

:= /INIT*/Q1
:+: /INIT*/HOLD*/Qo.

; DECREMENT
; HOLD

/Q2

:=

INIT
+ /INIT*/Q2
:+: /INIT*/HOLD*/Qo.*/Q1

;LOAD IN 0.
; DECREMENT
; HOLD

/Q3

:= /INIT*/Q3
:+: /INIT*/HOLD*/Qo.*/Q1*/Q2

; DECREMENT
; HOLD

/Q4

:=

INIT*/Fo.
/INIT*/Q4
:+: /INIT*/HOLD*/Qo.*/Ql*/Q2*/Q3

;LOAD IN Fo.
; DECREMENT
;HOLD

:=
+

+

/Q7*/Q6*/Q5*/Q4*/Q3*/Q2*/Q1*/Qo.
LD

+

;ENDOF COUNT
; LOAD·

/Q5

INIT*/F1
/INIT*/QS
:+: /INIT*/HOLD*/QO*/Q1*/Q2*/Q3*/Q4

;LOAD IN F1
; DECREMENT
; HOLD

/Q6

:=

INIT*/F2
+ /INIT*/Q6
:+: /INIT*/HOLD*/Qo.*/Q1*/Q2*/Q3*/Q4*/Q5

;LOAD IN F2
; DECREMENT
; HOLD

/Q7

:=
INIT*/F3
+ /INIT*/Q7
:+: /INIT*/HOLD*/Qo.*/Q1*/Q2*/Q3*/Q4*/Q5*/Q6

;LOAD IN F3
; DECREMENT
; HOLD
.

/RFCK

:=
+
:+:
+

; 32 LOW STATES
;16 LOW STATES
; 8 LOW STATES
; 4 LOW STATES

7-18

M3*/Q7*/Q6* Q5
M2*/Q7*/Q6*/Q5* Q4
M1*/Q7*/Q6*/Q5*/Q4* Q3
Mo.*/Q7*/Q6*/Q5*/Q4*/Q3* Q2

MonoIithio

W Memories

Refresh Clock Generator
;FUNCTION TABLE FOR PALASM 1
;CLK IOC ILD IHOLD F3 F2 F1 FO M3 M2 M1 MO IINIT Q7 Q6 Q5 Q4 Q3 Q2 Q1 QO RFCK

I

I
I
N

;L 0 L L FFFF MMMM
;K C D D 3210 3210

R
F
I QQQQQQQQ C
T 76543210 K

COMMEMTS

;C
;C
;C
;C
;C
;C
;C
;C
;C
;C
;C
;C
;C
;C
;C
;C
;C
;C
;C
;C
;C
;C
;C
;C
;C

L
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
Z

READY TO LOAD COUNTER
COUNTER LOADED, READY TO COUNT DOWN
COUNT DOWN
COUNT DOWN
READY TO LOAD COUNTER, COUNT DOWN
COUNTER LOADED
COUNT DOWN
COUNT DOWN
COUNT DOWN
READY TO LOAD COUNTER, COUNT DOWN
COUNTER LOADED
COUNT DOWN
COUNT DOWN
COUNT DOWN
COUNT DOWN
COUNT DOWN, RFCK HIGH
COUNT DOWN, RFCK HIGH
HOLD
COUNT DOWN
COUNT DOWN
COUNT DOWN
COUNT DOWN
COUNT DOWN
COUNT DOWN, READY TO LOAD COUNTER
HIGH IMPEDANCE TEST

;C

I I

H
0

j-------------------------------------------------------------------------;C LLXLLHH LLHH
L XXXXXXXX X
READY TO LOAD COUNTER
LLHLLHH
LHHLLHH
LHHLLHH
LHHLLHH
L L H LLLH
LHHLLLH
LHHLLLH
LHHLLLH
LHHLLLH
L L H LLLH
L H H LLLL
L H H LLLL
L H H LLLL
L H H LLLL
L H H LLLL
L H H LLLL
L H H LLLL
L H L LLLL
L H H LLLL
L H H LLLL
L H H LLLL
L H H LLLL
L H H LLLL
L H H LLLL
H x X XXXX

LLHH
LLHH
LLHH
LLHH
LHHL
LHHL
LHHL
LHHL
LHHL
LHHL
LHHL
LHHL
LHHL
LHHL
LHHL
LHHL
LHHL
LHHL
LHHL
LHHL
LHHL
LHHL
LHHL
LHHL
XXXX

LLHHHLHH
LLHHHLHH
LLHHHLHL
LLHHHLLH
LLHHHLLL
LLLHHLHH
LLLHHLHL
LLLHHLLH
LLLHHLLL
LLLHLHHH
LLLLHLHH
LLLLHLHL
LLLLHLLH
LLLLHLLL
LLLLLHHH
LLLLLHHL
LLLLLHLH
LLLLLHLH
LLLLLHLL
LLLLLLHH
LLLLLLHL
LLLLLLLH
LLLLLLLL
HHHHHHHH
ZZZZZZZZ

X
H
H
H
H
H
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
Z

j--------------------------------------------------------------------

Monolithic WMemories

7-19

Refresh 'ClOck Generator
1DESCRIPTION
1THE REF~S,H~LOCKGENlilRATOR .CAN. GENERATE REFRESH CLOCK (RFCK) FOR THE DYNAMIC.
1RAM CONTROLLERS. THE PERIOD OF RFCK DEPENDS ON F3-FO WHILE THE DURATION OF
1RFCK BEING LOW DEPENDS ON M3-MO.
FFFF
3210
,0000
0001
0010
: 0011"
0100
0101

Olla
0111
1000
1001
1010
1011
1100
1101
1110
1111

RFCK PERIOD
(CYCLES)

MMMM.

3210

12
28.

RFCKLOW .DURATION
(CYCLES)

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

+,

60

16
92
.108
124
140
1!S6
172
188
204
220
236
252

8

12
16
20*

24
28

32
36*
'40*
.44*
48
!S2*
56
60

-----------------------

1*NOT ALLOWED DUE TO BAD WAVEFORMS

7-20

o
4

MonoIIIIJIc WMemer/es

Octal Addressable Register

Title
Pattern
Revision
Author
Company
Date

OCTAL ADDRESSABLE REGISTER
P7078
A
DANESH TAVANA
MMI SUNNYVALE, CALIFORNIA
02/02/82

CHIP OCTAL ADDRESSABLE REGISTER PAL16R8
CLK /CLR /PR ABC El /E2 DIN GND
/OC Q7
Q6 Q5 Q4 Q3 Q2 Ql QO VCC
EQUATIONS
/QO :=
+
+
+
+
+
+
+

/Ql :=
+
+
+
+
+
+
+

CLR
/PR* El* E2*/DIN*/C*/B*/A
A
/PR* El* E2*/QO *
/PR* El* E2*/QO *
B
/PR* El* E2*/QO * C
/PR* El*/E2*/QO
/PR*/El*/E2*/QO
/PR*/El* E2*/QO

iCLEAR (LSB)
:DATA IN ADDRESS 0
;LOAD PREVIOUS STATES
;LOAD PREVIOUS STATES
iLOAD PREVIOUS STATES
iHOLD IF NOT LOADING (El=H,/E2=H)
iHOLD IF NOT LOADING (El=L,/E2=H)
iHOLD IF NOT LOADING (El=L,/E2=L)

CLR
/PR* El* E2*/DIN*/C*/B* A
/PR* El* E2*/Ql *
/A
B
/PR* El* E2*/Ql *
/PR* El* E2*/Ql * C
/PR* El*/E2*/Ql
/PR*/El*/E2*/Ql
/PR*/El* E2*/Ql

;CLEAR·
;DATA IN ADDRESS 1
;LOAD PREVIOUS STATES
iLOAD PREVIOUS STATES
:LOAD PREVIOUS STATES
iHOLD IF NOT LOADING (El=H,/E2=H)
iHOLD IF NOT LOADING (El=L,/E2=H)
iHOLD IF NOT LOADING (El=L,/E2=L)
; CLEAR

/Q2 := ' CLR
+ /PR* El* E2*/DIN*/C* B*/A
A
+ /PR* El* E2*/Q2 *
+ /PR*. El* E2*/Q2 *
/B
+ /PR* El* E2*/Q2 * C
+ /J?R* El*/E2*/Q2
+ /PR*/El*/E2*/Q2
+ /PR*/El* E2*/Q2
/Q3 :=
+
+
+
+
+
+
+

/Q4 :=
+
+
+
+
+
+
+

~DATA

;LOAD
.; LOAD
;LOAD
;HOLD
iHOLD
;HOLD

IN ADDRESS 2
PREVIOUS STATES
PREVIOUS STATES
PREVIOUS STATES
IF NOT LOADING (El=H,/E2=H)
IF NOT LOADING (El=L,/E2=H)
IF NOT LOADING (El=L,/E2=L)

CLR
/PR* El* E2*/DIN*/C* B* A
/A
/PR* El* E2*/Q3 *
/PR* .El* E2*/Q3 *
/B
/PR* El* E2*/Q3 * C
/PR* Elft/E2* /Q3
/PR*/El*/E2*/Q3
/PR*/El* E2*/Q3

; CLEAR
iDATA IN ADDRESS 3
;LOAD PREVIOUS STATES
iLOAD PREVIOUS STATES
iLOAD PREVIOUS STATES
iHOLD IF NOT LOADING (El=H,/E2=H)
;HOLD IF NOT LOADING (El=L,/E2=H)
iHOLD IF NOT LOADING (El=L,/E2=L)

CLR
/PR* El* E2*/DIN* C*/B*/A
A
jPR* El* E2*/Q4 *
B
/PR* El* E2*/Q4 *
/PR*El* E2*/Q4 */C
/PR* El*/E2*/Q4
/PR*/El*/E2*/Q4
/J?R*/El* E2*/Q4

iCLEAR
:DATA IN ADDRESS .4
iLOAD PREVIOUS STATES
iLOADPREVIOUS STATES
i LOAD PREVIOUS STATES
iHOLD IF NOT LOADING (El=H,/E2=H)
;HOLD IF NOT LOADING (El=L,/E2=H)
iHOLD IF NOT LOADING (El=L,/E2=L)

Monolithic

.

m

Memories

7-21

Octal Addressable Register
/Q5 :=
+
+
+
+
+
+
+

CLR
/PR* E1* E2*/DIN* C*/B* A
/PR* E1* E2*/Q5 *
/A
/PR* E1* E2*/Q5 *
B
/PR* E1* E2*/Q5 */C
/PR* E1*/E2*/Q5
/PR*/E1*/E2*/Q5
/PR*/E1* E2*/Q5

; CLEAR
;DATA IN ADDRESS 5
;LOAD PREVIOUS STATES
;LOAD PREVIOUS STATES
;LOAD PREVIOUS STATES
;HOLD IF NOT LOADING (E1=H,/E2=H)
;HOLD IF NOT LOADING (E1=L,/E2=H)
;HOLD IF NOT LOADING (E1=L,/E2=L)

/Q6 :=
+
+
+
+
+
+
+

CLR
/PR* E1* E2*/DIN* c* B*/A
/PR* E1* E2*/Q6 *
A
/PR* E1* E2*/Q6 *
/B
/PR* E1* E2*/Q6 */C
/PR* E1*/E2*/Q6
/PR*/E1*/E2*/Q6
/PR*/E1* E2*/Q6

; CLEAR
;DATA IN ADDRESS 6
;LOAD PREVIOUS STATES
;LOAD PREVIOUS STATES
;LOAD PREVIOUS STATES
;HOLD IF NOT LOADING (E1=H,/E2=H)
;HOLD IF NOT LOADING (E1=L,/E2=H)
;HOLD IF NOT LOADING (E1=L,/E2=L)

/Q7 := CLR
+ /PR* E1* E2*/DIN* c* B* A
/A
+ /PR* E1* E2*/Q7 *
+/PR* E1* E2*/Q7 *
/B
+ /PR* E1* E2*/Q7 */C
+ /PR* E1*/E2*/Q7
+ /PR*/E1*/E2*/Q7
+ /PR*/E1* E2*/Q7

;CLEAR (MSB)
;DATA IN ADDRESS 7
;LOAD PREVIOUS STATES
;LOAD PREVIOUS STATES
;LOAD PREVIOUS STATES
;HOLD IF NOT LOADING (E1=H,/E2=H)
;HOLD IF NOT LOADING (E1=L,/E2=H)
;HOLD IF NOT LOADING (E1=L,/E2=L)

;FUNCTION TABLE FOR PALASM 1
;/OC CLK /CLR /PR /E2 E1 C B A DIN Q7 Q6 Q5 Q4 Q3 Q2 Q1 QO
; CONTROL
FUNCTIONS
INPUTS
OUTPUTS
;/OC CLK /CLR /PR /E2 E1 C B A DIN Q Q Q Q Q Q Q Q
COMMENTS
7 6 5 4 3 2 1 0
j----------------------------------------------------- ----------------~---------

L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
; H

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
X

L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X

L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X

x x
x

X
L H
L H
L H
L H
L H
L H
L H
L H
L H
L H
L H
L H
L H
L H
L H
L H
L H
H H
L H
H L
L H
L

L

L H
X X

xxx

LLH

L L L L L L L L
HHHHHHHH
L HHHHHHHL
L HHHHHHLL
L HHHHHLLL
L H H H H L L L L
L H H H L L L L L
L HHLLLLLL
L H L L L L L L L
L LLLLLLLL
H HLLLLLLL
H HHLLLLLL
H HHHLLLLL
H HHHHLLLL
H HHHHHLLL
H HHHHHHLL
H H H H H H H H L
H HHHHHHHH
L LHHHHHHH
X LHHHHHHH
L LHLHHHHH
X LHLHHHHH
L LHLHLHHH
X LHLHLHHH
L LHLHLHLH

X X X

X

XXX

LLL
LLH
LHL
L H H
H L L
HLH
H H L
HHH
HHH
HHL
HLH
HLL
LHH
LHL
L L H
LLL
HHH
XXX

HLH
XXX

LHH
XXX

X
X

Z Z Z Z Z Z Z Z

CLEAR (OVERRD /PR)
PRESET (OVERRD ENABLES)
LOAD QO WITH DIN
LOAD Q1 WITH DIN
LOAD Q2 WITH DIN
LOAD Q3 WITH DIN
LOAD Q4 WITH DIN
LOAD Q5 WITH DIN
LOAD Q6 WITH DIN
LOAD Q7 WITH DIN
LOAD Q7 WITH DIN
LOAD Q6 WITH DIN
LOADQ5 WITH DIN
LOAD Q4 WITH DIN
LOAD Q3 WITH DIN
LOAD Q2 WITH DIN
LOAD Q1 WITH DIN
LOAD QO WITH DIN
LOAD Q7 WITH DIN
HOLD Q5 WITH DIN
LOAD LINE 5 WITH 0
HOLD Q3 WITH DIN
LOAD LINE 3 WITH 0
HOLD Q1 WITH DIN
LOAD LINE 1 WITH 0
HI-Z

j----------------------------------------------------- -------------~-----------

T8OO670M

7-22

Monolithic

W Memories

Octal Addressable Register
; DESCRIPTION
;THE a-BIT ADDRESSABLE REGISTER LOADS THE DATA (DIN) INTO THE APPROPRIATE
;ADDRESS LINE REGISTER (Q) ON THE RISING EDGE OF THE CLOCK (CLK).
;THE INPUT ADDRESSING PINS (C,B,A) CHANNEL THE D~A (DIN) INTO ITS CORRESPONDING
;OUTPUT REGIST,ER (Q) WHEN THE ENABLE PINS (jE2,El) ARE (LOW, HIGH) RESPECTIVELY;
;ANY OTHER COMBINATION OF INPUTS FOR THE ENABLE PINS HOLDS THE PREVIOUS STATE OF
;THE REGISTERS (Q).
; CLEAR OVERRIDES PRESET, PRESET OVERRIDES LOAD

EN~BLE.

; THESE FUNCTIONS ARE EXERCISED IN THE FUNCTION TABLE AND SUMMARIZED IN THE
; OPERATIONS TABLE:

IOC CLK

ICLR IPR

....

El IE2

C BA

DIN

Q7-QO

X

X
X
X

C BA

D

X.
X

X
X
X

Z
L
H
D
Q
Q
Q

--~---~- ~:---'---------;"---~-

H
L
L
L
L

C
·C

L

.C

L

C

X.

X

C

L
H
H

C

H
: H.

H

X
X

L'
H

H
H
H

X
X
X

X
X
X

H
H
L
L

L
H
H
L

OPERATION

...------:",,-------;,;,,-----.-- ---X

'x

X

HI-Z
CLEAR
PRESET
ENABLE
HOLD
HOLD
HOLD

--------------------------------------------------------

7·23

Octal Addressable Register With Demux/Enables
Title
Pattern
Revision
Author
Company
Date
CHIP

OCTAL ADDRESSABLE REGISTER WITH DEMULTIPLEXER/ENABLES
P7079
A
DANESH TAVANA
MMI SUNNYVALE, CALIFORNIA
02/08/82

OCTAL_ADDRESSABLE_REGISTER WITH_DEMULTIPLEXER/ENABLES PAL16R8

CLK MODE /PR ABC El /E2 DIN GND
/OC Q7
Q6 Q5 Q4 Q3 Q2 Ql QO VCC
EQUATIONS
/QO :=
+
+
+
+
+
+
+

/PR* El* E2*/DIN*/C*/B*/A* MODE
/PR* El* E2*
/C*/B*/A*/MODE
/PR* El* E2*/QO *
A* MODE
/PR* El* E2*/QO *
B
* MODE
/PR* El* E2*/QO * C
* MODE
/PR* El*/E2*/QO
/PR*/El*/E2*/QO
/PR*/El* E2*/QO

;LOAD /QO WITH /DIN (MODE=H)
;LOAD /QO WITH HIGH (MODE=L)
;/QO IS EITHER PREVIOUS STATE OR LOW
i/QO IS EITHER PREVIOUS STATE OR LOW
;/QO IS EITHER PREVIOUS STATE OR LOW
;HOLD IF NOT LOADING (El=H,/E2=H)
;HOLD IF NOT LOADING (El=L,/E2=H)
iHOLD IF NOT LOADING (El=L, /E2=L)

/Ql :=
+
+
+
+
+
+
+

/PR* El* E2*/DIN*/C*/B* A* MODE
/PR* El* E2*
/C*/B* A*/MODE
/PR* El* E2*/Ql *
/A* MODE
B
* MODE
/PR* El* E2*/Ql *
/PR* El* E2*/Ql * C
* MODE
/PR* El*/E2*/Ql
/PR*/El*/E2*/Ql
/PR*/El* E2*/Ql

;LOAD /Ql WITH /DIN (MODE=H)
;LOAD /Ql WITH HIGH (MODE=L)
;/Ql IS EITHER PREVIOUS STATE OR LOW
;/Ql IS EITHER PREVIOUS STATE OR LOW
;/Ql IS EITHER PREVIOUS STATE OR LOW
;HOLD IF NOT LOADING (El=H, /E2=H)
;HOLD IF NOT LOADING (El=L,/E2=H)
;HOLD IF NOT LOADING (El=L,/E2=L)

/Q2 :=
+
+
+
+
+
+
+

/PR* El* E2*/DIN*/C* B*/A* MODE
/PR* El* E2*
/C* B*/A*/MODE
/PR* El* E2*/Q2 *
A* MODE
/PR* El* E2*/Q2 *
* MODE
/B
/PR* El* E2*/Q2 * C
* MODE
/PR* El*/E2*/Q2
/PR*/El*/E2*/Q2
/PR*/El* E2*/Q2

;LOAD /Q2 WITH /DIN (MODE=H)
;LOAD /Q2 WITH HIGH (MODE=L)
;/Q2 IS EITHER PREVIOUS STATE OR LOW
;/Q2 IS EITHER PREVIOUS STATE OR LOW
;/Q2 IS EITHER PREVIOUS STATE OR LOW
;HOLD IF NOT LOADING (El=H,/E2=H)
;HOLD IF NOT LOADING (El=L,/E2=H)
;HOLD IF NOT LOADING (El=L,/E2=L)

/Q3 :=
+
+
+
+
+
+
+

/PR* El* E2*/DIN*/C* B* A* MODE
/PR* El* E2*
/C* B* A*/MODE
/PR* El* E2*/Q3 *
/A* MODE
/PR* El* E2*/Q3 *
* MODE
/B
/PR* El* E2*/Q3 * C
* MODE
/PR* El*/E2*/Q3
/PR*/El*/E2*/Q3
/PR*/El* E2*/Q3

;LOAD /Q3 WITH /DIN (MODE=H)
;LOAD /Q3 WITH HIGH (MODE=L)
;/Q3 IS EITHER PREVIOUS STATE OR LOW
;/Q3 IS EITHER PREVIOUS STATE OR LOW
;/Q3 IS EITHER PREVIOUS STATE OR LOW
;HOLD IF NOT LOADING (El=H,/E2=H)
;HOLD IF NOT LOADING (El=L,/E2=H)
;HOLD IF NOT LOADING (El=L,/E2=L)

/Q4 := /PR* El* E2*/DIN* C*/B*/A* MODE
+ /PR* El* E2*
C* /B* /A* /MODE
A* MODE
+ /PR* El* E2*/Q4 *
B
* MODE
+ /PR* El* E2*/Q4 *
* MODE
+ /PR* El* E2*/Q4 */C
+ /PR* El*/E2*/Q4
+ /PR*/El*/E2*/Q4
+ /PR*/El* E2*/Q4

;LOAD /Q4 WITH /DIN (MODE=H)
;LOAD /Q4 WITH HIGH (MODE=L)
;/Q4 IS EITHER PREVIOUS STATE OR LOW
;/Q4 IS EITHER PREVIOUS STATE OR LOW
;/Q4 IS EITHER PREVIOUS STATE OR LOW
;HOLD IF NOT LOADING (El=H,/E2=H)
;HOLD IF NOT LOADING (El=L,/E2=H)
;HOLD IF NOT LOADING (El=L,/E2=L)

7·24

Monolithic

W Memories

Octal Addressable Register With Demux/Enables
/Q5 :=
+
+
+
+
+

/PR* El* E2*/DIN* C*/B* A* MODE
/PR* El* E2*
C*/B* A*/MODE
/PR* El* E2*/Q5 *
/A* MODE
/PR* El* E2*/Q5 *
B
* MODE
/PR* El* E2*/Q5 */C
* MODE
/PR* El*/E2*/Q5
+ /PR*/El*/E2*/Q5
+ /PR*/El* E2*/Q5

;LOAD /Q5 WITH /DIN (MODE=H)
;LOAD /Q5 WITH HIGH (MODE=L)
;/Q5 IS EITHER PREVIOUS STATE OR'LOW
;/Q5 IS EITHER PREVIOUS STATE OR LOW
;/Q5 IS EITHER PREVIOUS STATE OR LOW
;HOLD IF NOT LOADING (El=H,/E2 ...H)
;HOLD IF NOT LOADING (El=L,/E2=H)
;HOLD IF NOT LOADING (El=L,/E2=L)

/Q6 := jPR* El* E2*/DIN* c* B*/A* MODE
+ /PR* El* E2*
c* B*/A*/MODE
A* MODE
+ /PR* El* E2*/Q6 *
+ /PR* El* E2*/06 * IB * MODE
* MODE
+ /PR* El* E2*/06 */C.
+ /PR* El*/E2*/Q6
+ /PR*/El*/E2*/Q6
+ /PR*/El*E2*/Q6

; LOAD /Q6 WITH /DIN (MODE=H) .
;LOAD IQ6 WITH HIGH (MODE=L)
;/0.6 IS EITHER PREVIOUS STATE OR LOW
, /Q6 IS EITHER PREVIOUS STATE OR LOW
; /Q6 IS EITHER PREVI.OUS STATE .OR LOW
;HOLD IF NOT LOADING (El=H,/E2=H)
;HOLD IF NOT LOADING (El=L,/E2=H)
;HOLD IF NOT LOADING (El=L,jE2=L)

/Q7 := /PR* El* E2*/DIN* Col! B* A* MODE
+ /PR* El* E2*
C* B* A*/MODE
/A* MODE
+ /PR* El* E2*/Q7 *
* MODE
+ /PR* El* E2*/07 *
/B
+ /PR* El* E2.*/Q7 */C
'" MODE
+ Im* El*/E2*/Q'7
+ IPR*/El*/E2*/07,
+jPR*/El* E2*/Q7

; LOAD /Q7 WITH /DIN (MODE=H)
,LOAD /Q1 WITH HIGH (MODE=L)
;/07 IS EITHER PREVIOUS S~ATE OR LOW
;/Q7 IS EITHER, PREVIoqS STATE OR LOW
;/Q7 IS EITHERPREVIOU'S STATE OR LOW
;HOLD IF NOT LOADING (El=a,/E2=H)
;HOI:D IF NOT LOADING (El=L,/E2=H)
;HOLD IF NOT LOADING (El=L,/E2=L)

1-25.

Octal Addressable Register With Demux/Enables
;FUNCTION TABLE
;jOC CLK MODE jPR jE2 El C B A DIN Q7 Q6 Q5 Q4 Q3 Q2 Ql QO

; CONTROL
FUNCTIONS
;jOC CLK MODE jPR jE2 El

INPUTS
C B A DIN

OUTPUTS
Q Q Q Q Q Q Q Q
7 6 543 2 1 0

COMMENTS

------------------------------------------------------------------------------L
C
X
L
X X
X X X X
H H H H H H H H
PRESET (OVERRD ENABLES)
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L

X

L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
H
H

L L L
L L H
L H L
L H H
H L L
H L H
H H L
H H H
H H H
H H L
H L H
H L L
L H H
L H L
L L H
L L L
L L L
L L H
L H L
LHH
H L L
HLH
H H L
H H H

L

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

X

X

X

X

X X X

X

H
X

H
X

L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H

X X X

X
X
X
X
X
X
X
X
X

HLH

L

X X X

X

L H H

L

X X X

X
X
X

L L H

H H H H H H H L
HHHHHH L t..
HHHHHL L L
HHHHLL L L
HHHLLL L L
HHLLLL L L
HLLLLL L L
LLLLLL L L
HLLLLL L L
HHLLLL L L
HHHLLL L L
HHHHLL L L
HHHHHLLL
HHHHHHLL
HHHHHHHL
HHHHHHHH
HHHHHHHL
HHHHHHLH
HHHHHLHH
HHHHLHHH
HHHLHHHH
HHLHHHHH
HLHHHHHH
LHHHHHHH
LHHHHHHH
LHLHHHHH
LHLHHHHH
LHLHLHHH
LHLHLHHH
HHHHHHLH
Z Z Z Z Z Z Z Z

LOAD QO WITH DIN
LOAD Ql WITH DIN
LOAD Q2 WITH DIN
LOAD Q3 WITH DIN
LOAD Q4 WITH DIN
LOAD Q5 WITH DIN
LOAD Q6 WITH DIN
LOAD Q7 WITH DIN
LOAD Q7 WITH DIN
LOAD Q6 WITH DIN
LOAD Q5 WITH DIN
LOAD Q4 WITH DIN
LOAD Q3 WITH DIN
LOAD Q2 WITH DIN
LOAD Ql WITH DIN
LOAD QO WITH DIN
DECODE ADDRESS LINE
DECODE ADDRESS LINE
DECODE ADDRESS LINE
DECODE ADDRESS LINE
DECODE ADDRESS LINE
DECODE ADDRESS LINE
DECODE ADDRESS LINE
DECODE ADDRESS LINE
HOLD PREVIOUS STATE
LOAD Q5 WITH DIN
HOLD PREVIOUS STATE
LOAD Q3 WITH DIN
HOLD PREVIOUS STATE
DECODE ADDRESS LINE
HI-Z

0
1
2
3
4
5
6
7

1

i-----------------------------------------------------------------------------

7-26

Monolithic WMemorles

Octal Addressable Register With Demux/Enables
; DESCRIPTION
;THE 8-BIT ADDRESSABLE REGISTER AND DEMULTIPLEXER PERFORMS TWO FUNCTIONS ON ONE
;MSI PACKAGE. IF MODE=O THE PART PERFORMS A 3 TO 8 DE-MULTIPLEXER FUNCTION WITH
; PRESET, LOAD, AND HOLD; IF MODE=l IT IS AN 8-BIT ADRESSABLE REGISTER WITH
; PRESET , LOAD, AND HOLD.
;WHEN THE CONTROL PINS (/E2,El) ARE (LOW,HIGH) THE UNIT IS ENABLED AND THE INPUT
;ADDRESS PINS (C,B,A) EITHER CHANNEL THE INPUT DATA (DIN) TO ITS APPROPRIATE
;OUTPUT REGISTER (Q) WITH MODE=l, OR SELECT THE ADDRESSED OUTPUT REGISTER (Q)
;WITH MODE=O. ANY OTHER COMBINATION FOR THE INPUT CONTROL PINS HOLDS THE
;PREVIOUS STATE OF THE OUTPUTS.
; PRESET OVERRIDES ENABLE.
; THESE FUNCTIONS ARE EXERCISED IN THE FUNCTION TABLE AND SUMMARIZED IN THE
; OPERATIONS TABLE:
/OC CLK

MODE /PR /E2

El

C B A DIN

X
H
H
L
L
H

X
C
C
X
X
X

Q7-QO

OPERATION

------------------------------------------------------------------XXX
X
Z
HI-Z
H
X
X
X
X
X
L
L
L
L
L
L

C
C
C
C
C
C

X
L
H
X
X
X

L
H
H
H
H
H

X
L
L
H
L
H

X
B
B
X
X
X

X
A
A
X
X
X

X
X
D
X
X
X

H
MUX
REG
Q
Q
Q

PRESET
ADDRESSED OUTPUT=LOW
ADDRESSED OUTPUT=D
HOLD
HOLD
HOLD

-------------------------------------------------------------------

Monolithic

W Memo,./es

7·27

Octal· Addressable Register With Demux/Clear
Title
Pattern
Revision
Author
Company
Date

OCTAL ADDRESSABLE REGISTER WITH DEMULTIPLEXER/CLEAR
P7080 (PMSI002)
A
DANESH TAVANA
MMI SUNNYVALE, CALIFORNIA
04/27/82

CHIP OCTAL_ADDRESSABLE_REGISTER_WITH_DEMULTIPLEXER/CLEAR PAL16R8
EQUATIONS
CLK /CLR /PR ABC MODE /E DIN GND
/OC Q7
Q6 Q5 Q4 Q3 Q2 Ql QO VCC
/QO:= CLR
+ /PR* E*/MODE*/C*/B*/A
+ /PR* E* MODE*/C*/B*/A*/DIN
+ /PR* E* MODE*
A*/QO
+ /PR* E* MODE*
B
*/QO
+ /PR* E* MODE* C
*/QO
+ /PR*/E
*/QO

;CLEAR (LSB)
;DEMULTIPLEX OUTPUT /QO=H
;REGISTER OUTPUT /QO=/DIN
;LOAD PREVIOUS STATE (/QO) OR A LOW
; LOAD PREVIOUS STATE UQO) OR A LOW
;LOAD PREVIOUS STATE (/QO) OR A LOW
;HOLD IF NOT LOADING (/E=H)

/Ql:= CLR
+ /PR* E*/MODE*/C*/B* A
+ /PR* E* MODE*/C*/B* A*/DIN
+ /PR* E* MODE*
/A*/Ql
+ /PR* E* MODE*
B
*/Ql
+ /PR* E* MODE* C
*/Ql
+ /PR*/E
*/Ql

; CLEAR
;DEMULTIPLEX OUTPUT /Ql=H
;REGISTER OUTPUT /Ql=/DIN
;LOAD PREVIOUS STATE (/Ql) OR A LOW
;LOAD PREVIOUS STATE (/Ql) OR A LOW
;LOAD PREVIOUS STATE (/Ql) OR A LOW
;HOLD IF NOT LOADING (/E=H)

/Q2 :=
+
+
+
+
+
+

CLR
/PR* E*/MODE*/C* B*/A
/PR* E* MODE*/C* B*/A*/DIN
/PR* E* MODE*
A*/Q2
/PR* E* MODE*
/B
*/Q2
/PR* E* MODE* C
*/Q2
/PR*/E
*/Q2

; CLEAR
;DEMULTIPLEX OUTPUT /Q2=H
;REGISTER OUTPUT /Q2=/DIN
;LOAD PREVIOUS STATE (/Q2) OR A LOW
;LOAD PREVIOUS STATE (/Q2) OR A LOW
;LOAD PREVIOUS STATE (/Q2) OR A LOW
;HOLD IF NOT LOADING (/E=H)

/Q3 :=

CLR
/PR* E*/MODE*/C* B* A
/PR* E* MODE*/C* B* A*/DIN
/PR* E* MODE*
/A*/Q3
/PR* E* MODe*
/B
*/Q3
/PR* E* MODE* C
*/Q3
/PR*/E
*/Q3

; CLEAR
;DEMULTIPLEX OUTPUT /Q3=H
;REGISTER OUTPUT /Q3=/DIN
;LOAD PREVIOUS STATE (/Q3) OR A LOW
;LOAD PREVIOUS STATE (/Q3) OR A LOW
;LOAD PREVIOUS STATE (/Q3) OR A LOW
;HOLD IF NOT LOADING (/E=H)

CLR
/PR* E*/MODE* C*/B*/A
/PR* E* MODE* C*/B*/A*/DIN
/PR* E* MODE*
A*/Q4
B
/PR* E* MODE*
*/Q4
/PR* E* MODE*/C
*/Q4
/PR*/E
*/Q4

; CLEAR
;DEMULTIPLEX OUTPUT /Q4=H
;REGISTER OUTPUT /Q4=/DIN
;LOAD PREVIOUS STATE (/Q4) OR A LOW
;LOAD PREVIOUS STATE (/Q4) OR A LOW
; LOAD PREVIOUS STATE UQ4) OR A LOW
;HOLD IF NOT LOADING (/E=H)

+
+
+
+
+
+
/Q4 :=

+
+
+
+
+
+

7-28

Monolithic WMemories

Octal Addressable Register With Demux/Clear
/Q5 := CLR
+ /PR* E*/MODE* C*/B* A
+ /PR* E* MODE* C*/B* A*/DIN
+ /PR* E* MODE*
/A*/Q5
+ /PR* E* MODE*
B
*/Q5
+ /PR* E* MODE*/C
*/Q5
+ IPR*/E
.*/Q5

; CLEAR
;DEMULTIPLEX OUTPUT /Q5=H
;REGISTER OUTPUT /Q5=/DIN
;LOAD PREVIOUS STATE (/Q5) OR A LOW
;LOAD PREVIOUS STATE (/Q5)OR A LOW
. ; LOAD PREVIOUS STATE (fQ5) OR A :J:,OW
;HOLD IF NOT LOADING (/E=H)

/Q6:=
+
+
+
+
+
+

CLR
/PR* E*/MODE* c* B*/A
/PR* E* MODE* c* B*/A*/DIN
/PR* E* MODE*
A*/Q6
/PR* E* MODE*
/B
*/Q6
/PR* E* MODE*/C
*/Q6
/PR*/E
*/Q6

; CLEAR
.
; DEMULTIPLEX ..OUTPUT /Q6=H
; REGISTER OUTPUT /Q5=/DIN
;LOAD PREVIOUS STATE (/Q6) OR A LOW
;LOAD PREVIOUS STATE (/Q6) ORA LOW
;LOAD PREVIOUS STATE (/Q6) OR A LOW
;HOLD IF NOT LOADING (jE=H)

/Q7 :=
+
+
+
+
+
+

CLR
/PR* E*/MODE* c* B* A
/PR* E* MODE* c* B* A*/DIN
/PR*E* MODE*
/A*/Q7
/PR* E* MODE*
/B
*/Q7
/PR*E* MODE*/C
*/Q7
/PR*/E
*/Q7

;CLEAR (MSB)
; DEMULTIPLEX OUTPUT fQ7=!!
;REGISTER OUTPUT /Q7=/DIN
;LOAD PREVIOUS STATE (/Q7) OR A LOW
;LOAD PREVIOUS STATE. (fQ7) OR A LOW
;.LOAD PREVIOUS STATE (fQ7) ORA LOW
;HOLD IF NOT LOADING (fE=H)

;FUNCTION TABLE. FORPALASM 1
;/OC CLK /CLR /PR /E MODE C B A DIN Q7 Q6 Q5 Q4.Q3 Q2 Ql.QO
;
~---OUTPUTS~--
;CONTROL--~FUNCTIONS----INPUTS-- Q Q Q Q Q Q Q Q
;/OC eLK /CLR /PR /E MODE C B A DIN 7 6 5 4 3 2 1 0
COMMEN'TS

;

----------------------------------~----.~--:--.----------"":"

L
L
L
L
,L
L
; L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
;. L
L
L
, H

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
X.

..

~"'!"'.~-------------------

L
L
X X
XXX X L L L L L L L L
CLEAR (OVERRD /PR)
H
L
X X
xxx X H H H H.H H H H P~SET(OVERRbENABLES)
H H L H
L. L .L .. L .a H HH H H HL
LOAD QO WITH DIN
H H
L H
L L. a L
H H H H HHL It, LOAD Ql' WITH DIN'
H
H
L H
LH L .' 1.
HH .H HH L L L
LOAD, Q2 .WITaDIN
H H
L H
L 'H.HL
H H'a HL L'L L, LOAD Q3 WITH DIN,
HaL H
H I... L L .H H H L 'L' LL L,' LOAD Q4WITH' DIN
H H L H a L H L .H H LLL LL L
LOi\D Q5 WITH DIN
a
H
L H
H H L ',L
H L iL LL .L L L. LOAD Q6WITH. DIN
a
H
LH
HH H . L
L r~' L L L L. L ..J.,
LOAP Q7WITa DIN
H H
L H
H H H H H LL Lt L'LLLOAD Q7.WITH DIN
H H L H
a.H L H H H L L L L L.L
LOAD Q6 WITH DIN
H H L H
HL a H Ha H L L L L L
LOAD Q5 WITH DIN
H H
L H
H L L H H H aH L L L L
LOADQ4 WITH DIN
H H
L H
L H H H H H H HH L L L
LOAD Q3 WITH DIN
H H L H
L HL H H H H H HaL L
.LOAD Q2.WITH DIN
H H
L H
L L H it
H H H H a HaL
LOAD. Q1WITH DIN
H H
L H
L L L H H H H H H Ha H LQAD. QO WITH DIN
H H
L L
LL L X HH H H H H H L
DECODE ADDRESS LINE 0
H H
L L
L L H X H H H H H H L H DECODE ADDRESS LINE 1
H H
L L
L H L X H H H H H L H H DECODE ADDRESS LINE 2
H H'
L L
f, H H X
H HHHLH H H DECODE ADDRESS LINE 3
H, H
L L
H LL X a H H L H H aH
DECODE ADDRESS LINE 4
H H
L L
H t H X H H L H H H H H DECODE ADDRESS LINE 5
H HL L
H H L X H L H H H HH H
DECODE'ADDRESS LINE 6
H H
L L
H H H X .L H. H H H H H H DECODE ADDRESS LINE 7
H H H X.
X x x X L H H H H H H H HOLD PREvr'OUS. STATE
X X X X
X X xx
Z Z Z Z Z ZZ Z . TESTHI-Z
.

:---------------.----------------------~-~------------ -----.---------------------.

749

~

...

Octal Addressable Register With Demux/Clear
; DESCRIPTION
;THE OCTAL ADDRESSABLE REGISTER AND DEMULTIPLEXER PERFORMS ONE OF TWO MSI
;FUNCTIONS ,DEPENDING ON THE STATE OF THE MODE SELECT PIN. IF MODE=HIGH THEN THE
;PART PERFORMS THE FUNCTION OF AN ADDRESSABLE REGISTER WITH 8 OUTPUTS (Q7-QO)
;AND ONE DATA INPUT (DIN). THE REGISTERED OUTPUT IS SELECTED BY THREE INPUT
;ADDRESS PINS (A,B,C). WITH MODE=LOWCONVERTS THIS CHIP INTO AN ACTIVE LOW
;3-TO-8 DEMULTIPLEXER, WHERE THE ADDRESSED OUTPUT IS LOW AND ALL OTHER OUTPUTS
;REMAIN HIGH. CLEAR (/CLR) AND PRESET (/PR) ARE ACTIVE LOW OUTPUTS WHICH SET
;ALL OUTPUTS TO LOW OR HIGH RESPECTIVELY. WHEN ENABLE (IE) IS HIGH, THE CHIP IS
;DISABLED AND THE OUTPUTS RETAIN THEIR PREVIOUS STATES.
; CLEAR OVERRIDES PRESET AND ENABLE, PRESET OVERRIDES ENABLE.
;THESE FUNCTIONS .ARE EXERCISED IN THE FUNCTION TABLE AND SUMMARIZED IN THE
;OPERATIONS TABLE:

;Ioc

CLK

H
L

X
C

X
L

X
X

L
L
L
L

C
C
C
C

H
H
H
H

L
H
H
H

ICLR

IPR

MODE

C B A

DIN

Q7-QO

X
X

X
X

X XX
X X X

X
X

L

X
L
L
H

X
L
H
X

X X
C B
C B
XX

IE

OPERATION

;-----------------------------------------------------------------------X
A
A
X

HI-Z
CLEAR

Z

X
X
DIN

x

H
MUX
REG
Q

PRESET
ADDRESSED OUTPUT=LOW
ADDRESSED OUTPUT=DIN
HOLD PREVIOUS STATES

;-----------------------------------------------------------------------OUTPUT SELECT TABLE
C B A

DIN

Q7

Q6

Q5

Q4

Q3

LLH
LHL
LHH
H L L
HLH
H H L
H H H

DIN
DIN
DIN
DIN
DIN
DIN
DIN

Q7
Q7
Q7
Q7
07
Q7
DIN

Q6
Q6'
Q6
Q6
Q6
DIN
Q6

Q5
Q5
Q5
Q5
DIN
Q5
Q5

Q4
Q4
Q4
DIN
Q4
Q4
Q4

Q3 Q2
Q3 DIN
DINQ2
Q3 Q2
Q3 Q2
Q3 Q2
Q3 Q2

Q2

Q1

QO

DIN
Q1
Q1
Q1
Q1
Q1
Q1

QO
QO
QO
QO
QO
QO
QO

----------------------------------------------L L L
DIN
Q7 Q6 Q5 Q4 Q3 Q2 Q1 DIN

7·30

Monolithic

m

Memories

Rounding - Control Logic

Title
Pattern
Revision
Author
Company
Oate

ROUNOING-CONTROL LOGIC
P7081
A

VINCENT COLI
MMI SUNNYVALE, CALIFORNIA
03/18/82

CHIP ROUNOING-CONTROL LOGIC PAL16C1
000 001 002 003 004 005 006 007 008 GNO
009 010 011 012 TRU COM NC NC NC VCC
EQUATIONS
COM

+
+
+
+
+
+
+
+
+
+
+

012* 011
011* 010
011
*009
011
* 008
011
* 007
D11
* 006
* 005
011
* 004
011
011
* 003
* 002
011
* 001
011
* 000
011

;FUNCTION TABLE
;012 011 010 009 008 007 006 005 004 003 002 001 000 COM TRU
I

; COM RESULTS HAVE BEEN REMOVEO FROM SIMULATION RESULTS
;0 0 0 0
;12 11 10

0

0

0

0

0

0

0

MonoIflhic

0

0

ROUNO-CONTROL

W Memories

4·Bit Counter With Terminal Count Lock
Title
Pattern
Revision
Author
Company
Date

4-BIT COUNTER WITH TERMINAL COUNT LOCK
P7082
A
COLI/VOLDAN
MMI SUNNYVALE, CALIFORNIA
04/05/82

CHIP 4-BIT COUNTER WITH TERMINAL COUNT_LOCKPAL16R6
CLK NC NC DO D1 D2 D3 CLEAR /LOAD GND
/OC NC /EP Q3 Q2 Q1 QO NC
NC vce
EQUATIONS
/QO:=

CLEAR

+ LOAD*/DO
+ /LOAD*/QO*/EP
+ /LOAD* EP* QO

/Q1:=

CLEAR

+ LOAD*/D1
+ /LOAD*/Q1*/EP
+ /LOAD*/Q1*/QO
+ /LOAD* EP* Q1* QO
/Q2 :=

CLEAR

+ LOAD*/D2
+ /LOAD*/Q2*/EP

+ /LOAD*/Q2*/QO
+ /LOAD*/Q2*/Q1
+ /LOAD* EP* Q2* Q1* QO
/Q3 :=

CLEAR

+ LOAD*/D3
+ /LOAD*/Q3*/EP
/LOAD*/Q3*/QO
/LOAD*/Q3 * /Q1
/LOAD*/Q3*/Q2
/LOAD* EP* Q3* Q2* Q1* QO

+
+
+
+
EP:=

+

7-32

CLEAR
/Q3 + /Q2 + /Q1

~CLEAR QO
~LOAD DO
~HOLD

~COUNT

(LSB)

IF NO EP
IF EP AND QO=H

~CLEARQ1
~LOAD D1
~HOLD IF NO

EP
IF Q1,QO=L
~COUNT IF EP AND Ql,QO=H

~HOLD

Q2
D2
;HOLD IF NO EP
~HOLD IF Q2,QO=L
;HOLD IF Q2,Q1=L
~COUNT IF EP AND Q2,Q1,QO=H
~CLEAR
~LOAD

;CLEAR Q3 (MSB)
;LOAD D3
; HOLD IF NO EP
;HOLD IF Q3,QO=L
;HOLD IF Q3,Q1=L
;HOLD IF Q3,Q2=L
;COUNT IF EP AND Q3,Q2,Q1,QO=H
~IN~TIALIZE REGISTER
~HOLD IF Q3,Q2,Q1=H

4·Bit Counter With Terminal Count Lock
;FUNCTION TABLE FOR PALASM 1
;CLK JOC CLEAR jLOAD jEP D3 D2 D1 DO Q3 Q2 Q1 QO
; CONTROL
;CLK JOC
;

DDDD
3210

QQQQ
3210

COMMENTS
(HEX VALUES)

XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
:·XXXX'.,
XXXX
XXXX
LLLL
LLLH
,LLHL
LHLL
'HLLL
HHLL
HHHL
HHHH

LLLL
LLLH
LLHL
LLHH
LHLL
LHLH
LaHL
LHHH
HLLL
HLLH
HLHL
HLHH
HHLL
HHLH
HHHL
HHHH
HHHH
LLLL
LLLH
LLHL
LHLL
HLLL
HHLL
HHHL
H;lH;H

CLEAR (0)
COUNT (1)
COUNT (2)
COUNT (3)
COUNT (4)
COUNT (5)
COUNT (6)
COUNT (7.)
COUNT (8)
COUNT (9)
COUNT (A.)
COUNT (B.)
COUNT (C)
COUNT (D)
COUNT (E)
COUNT (F)
HOLD AT TERMINAL COUNT
LOAD (0)
toAD (1)\
LOAD (3)
LQAt> (4)
LOAD (8)
LOAD (C)
LOAD (E)
"",
LOAD (F)
TES+' HI~Z

--------------------------------------------.-----------------------

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
',' C
C
: C
C
C
C
X
I

---OPERATION--CLEAR jLOAD jEP

L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H

H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X

H
H
H
H
H
H
H
H
H
H
H
H
.H
H
H
H
H
L
L
L
L
L'
.L
L
L
X

L
L
L
L
L
L
L
L
L
L
L
L
L
L
.L
H
H
X

X
X
X
X
X
X
X
Z

xxXX ·zzzz

..

&I

..

1------------,---~-.;.--·~--~---~·~----~- ;-~_:---~-"';'"-..;,;.--:-.~~.~-~ --~~~--.--

; DESCRIPTION
:'l;'HE 4-BITCOUNTER LOADS
;OFTHE .CLOCK (CLK) ,

DA~A,

INCREMENTS, OR HOLDS ON THE. RISIN(;E:DGE:

NE:kDATk
rTHZCOUNTER WILL. HOLD' WHEN THE TERMINAL COUNT ISREACHJi!P UNTIL
. .,,'.,'
. ' ;>;" .
;IS LOADED OR THE REGISTERS ARE CLEARED:
.
':
~.

~,;;

;THESE OPERATIONS'ARE'EXERCISJi!D IN,. THEtuNCTION TABU: AND
;IN THE OPERATIOt(STABLE:
JOC

eLK

CLEu JLOAD.jEP
-. .

P3-DOQ3-QO.
. '
-.

. , X . 'HX

X

L

.C

X
X
XL

L
L

C
C

L
H
H.

H

ex
L
L
L

X.A
t

. X
X

Z
L
A
Q
,'Q PLUS 1

.:

',.
---.7>·Ht.-Z
CLEAR.
LoAD'
HOLD
INCREMENT

--------------:-----~-----------------.----------'!""'-.---

H
L.

S~IbDthrM

..

-----------------~-----------'-------~-~~~----'-------~~-~

.

•t . .

",.

;,,",

-

'\

Memory Mapped 1/0
Title
Pattern
Revison
Author
Company
Date

MEMORY MAPPED I/O
P70S3
A
VINCENT COLI
MMt SUNNYVALE, CALIFORNIA
04/19/S2

CHIP MEMORY_MAPPED_I/O PAL1SL4
AO Al A2 A3 A4 A5 A6 A7 AS /RD /WR GND
A9 A10 All A12 /READ /WRITE /AUX2 /AUXl A13 A14 A15 VCC
EQUATIONS
READ

= /A15*/A14*/A13*

WRITE

= /A15*/A14*/A13*

A12* A11* A10* A9* AS
* /A7 * A6 * A5 * A4 */A3 * A2 * A1*/AO
* RD

SELECT PORT1
(lF76)
READ STROBE

A12* A11* A10* A9* AS
* /A7 * A6 * A5 * A4 */A3 * A2 * A1* AO
* WR

;

AUX1

/A15*/A14*/A13* A12* A11* A10* A9* AS
* /A7 * A6 * A5 * A4 * A3 */A2 */A1*/AO

;SELECT PORTO
(lF7S)

AUX2

/A15*/A14*/A13* A12* A11* A10* A9* AS
* /A7 * A6 * A5 * A4 * A3 */A2 */A1* AO

;SELECT PORT1
(lF79)

; SELECT PORT1
(lF77)
;WRITE STROBE

;FUNCTION TABLE FOR PALASM 1
;A15 A14 A13 A12 All A10 A9 AS A7 A6 A5 A4 A3 A2 A1 AO /RD /WR
;/READ /WRITE /AUX1 /AUX2
;-ADDRESS INPUTS;111111
STROBES --PORT ENABLE OUTPUTS--;5432109S76543210 /RD /WR /READ /WRITE /AUX1 /AUX2
COMMENT
;-------------~~-------------------------------------- ----------------;LLLLHHHHLHHHHLLL
L
L
H
H
H
TEST OF7S
H
;LLLHHHHLLHHHHLLL
L
H
L
H
H
H
TEST 1E7S
;LLLHHHHHHHHHHLLL
L
L
H
H
H
H
TEST 1FFS
;LLLHHHHHLHHHLLLL
L
L
H
H
H
TEST lF70
H
;LLLHHHHHLHHHLHHL
H
L
H
H
H
TEST 1F76 {NO RD STROBE)
H
;LLLHHHHHLHHHLHHL
L
L
L
H
H
TEST 1F76 (READ ENABLE)
H
;LLLHHHHHLHHHLHHH
L
H
H
H
H
H
TEST 1F77 (NO WR STROBE)
;LLLHHHHHLHHHLHHH
L
L
H
L
H
H
TEST 1F77 (WRITE ENABLE)
;LLLHHHHHLHHHHLLL
L
L
H
H
L
TEST 1F7S (AUX1 ENABLE)
H
;LLLHHHHHLHHHHLLH
L
L
H
H
H
TEST 1F79 (AUX2 ENABLE)
L
; LLLHHHHHLHHHHLHL
L
L
H
H
H
TEST 1F7A
H
;LLLHHHHHHHHHHLLH
L
L
H
H
TEST lFF9
H
H
;LLLHHHHLLHHHHLLH
L
L
H
H
H
TEST 1E79
H
;LLHHHHHHLHHHHLLH
L
L
H
H
H
H
TEST 3F79
;LLLLLLLLLLLLLLLL
L
L
H
H
TEST ALL L'S
H
H
;HHHHHHHHHHHHHHHH
L
L
H
H
H
TEST ALL H'S.
H
; LHLHLHLHLHLHLHLH
L
L
TEST ODD CHECKERBOARD
H
H
H
H
; HLHLHLHLHLHLHLHL
L
L
H
H
TEST EVEN CHECKERBOARD
H
H

i------------------------------------------------------------------------

7-34

MonoIlthlcW Memories

Memory Mapped 1/0
; DESCRIPTION
THIS PAL PROVIDES A SINGLE CHIP DECODER FOR USE IN MEMORY MAPPED I/O OPERATIONS
REQUIRING FOUR ACTIVE LOW PORT ENABLES AND FULL 16-BIT DECODE WITH TWO TWO
STROBE LINES (lRD AND /WR). EQUATION TERMS CAN BE CHANGED TO ACCOMMODATE ANY
16-BIT ADDRESS.
THE PAL WILL MONITOR THE SYSTEM MEMORY ADDRESS BUS (A15-AO) AND DECODE THE
SPECIFIED MEMORY ADDRESS WORD (lF76,lF77,lF78,lF79) TO PRODUCE A PORT ENABLE
FOR READ, WRITE, A

1·35

745508 Memory Map Interface # 1
Title
Pattern
Revision
Author
Company
Date

SNS4/74SS08 MEMORY MAP INTERFACE WITH THE INTEL 808S (DESIGN # 1)
P708S
A
VINCENT COLI
MMI SUNNYVALE, CALIFORNIA
OS/lS/82

CHIP SNS4/74SS08_MEMORY_MAP_INTERFACE_WITH_THE_INTEL_808S_CDESIGN_#l) PAL16R4
eLK ADO AD1 AD2 AD3 AD4 ADS AD6 AD7 GND
IOE IE1 ALE 12 I1 IO /GO E2 E3 VCC
EQUATIONS
;MONITOR ADDRESS/DATA BUS (AD3-AD7)
;MONITOR ENABLES (FROM A8-A1S)
;MONITOR ADDRESSjDATA CONTROL

GO := /AD3*/AD4*/ADS* AD6*/AD7
* E1 * E2* E3
* ALE
lID := JADO

;REGISTER INSTRUCTION INPUT IO

III := jAD1

;REGISTER INSTRUCTION INPUT I1

II2 := /AD2

;REGISTER INSTRUCTION INPUT I2

;FUNCTION TABLE FOR PALASM 1
;jOE CLK ADO AD1 AD2 AD3 AD4 ADS AD6 AD7 jE1 E2 E3 ALE IO I1 12 jGO

,
;/OE CLK

A/D BUS
01234S67

ADD BUS
/E1 E2 E3

ALE

INSTR
012

/GO

XXX
XXX
XXX
XXX
LHH
LHH
LLL
ZZZ

H
H
H
L
L
H
L
Z

COMMENTS
(OCTAL ADDRESS)

;--------------------------------------------------------------------------L
C
XXXLLLLH
L H H
H
XXX
H
(200 TO 207) INACTIVE
L
L
L
L
L
L
L
H

C
C
C
C
C
C
C
X

XXXLLLLH
XXXLLLHL
XXXLLLHL
XXXLLLHL
LHHLLLHL
LHHLLLHL
LLLLLLHL
XXXXXXXX

H
L
L
L
L
L
L

x

H H
L L
H H
H H
H H
H H
H H

x

x

H
H
L
H
H
L
H

x

(100 TO 107) INACTIVE (jE1=H)
(100 TO 107) INACTIVE (E2, E3=L)
(100 TO 107) INACTIVE (ALE=L)
(100 TO 107) (ACTIVE RANGE)
(106) LOAD X
(106) NOP (ALE=L)
(100) LOAD Y
TEST HI-Z

:---------------------------------------------------------------------------

7·36

MonoIlthicm.emories

748508 "emory Map Interface #1
;DESCRIPTION
;THIS PAL PROVIDES THE DECODE LOGIC FOR INTERFACING THE MMI SN54/74S508, 8";BIT
;SEQUENTIAL MULTIPLIER/DIVIDER, WITH THE INTEL 8085 MICROPROCESSOR. - THE PAL16R4
;MONITORS THE LOWER 8 BIT ADDRESS/DATA BUS (ADO-AD7), THE ADDRESS LATCHENAB~
; (ALE), AND THREE OF THE UPPER 8 BIT ADDRE.SS BUS (A8-A15) WHICH IS LABP;LED
;/E1,E2,M THE 8085 IN ORDP;R TO
.
;DECODE AN ACTIVE LOW CHIP-ACTIVATION SIGNAL (/GO) FOR THE 74S508. THP;
;INSTRUCTION LINES AND CHIP-ACTIVATION SIGNAL ARE REGISTERED IN ORDER TO INSURE
;THAT INSTRUCTION INPUTS WILL NOT CHANGE WHEN THE CLOCK IS LOW (CLK=L). BY
;MONITORING THE MACHINE STATUS CYCLE, THE 74SS08 CAN BE ADDRESS . MAPPED BY THE
;8085 AS IF IT WERE AN I/O DEVICE, THUS NOT USING ANY MEMORY MAP ADDRESS SPACE.
;THE MACHINE CYC~ STATUS FROM THE 8085 IS AVAILABLE ON THE FALLING EDGE OF.ALE~
;FOR THIS PARTICULAR DESIGN, THE THREE INSTRUCTION INPUTS TO THE 74S508 (IO-I2)
;ARE ASSIGNED TO THE THREE LSB BITS OFADDRES.S BUS (A8:"A10) ,WHILE THE~INING'
;ADDRESS BITS (All-A15) ARE DECODED BY' THE ,PAL TO DETERMINE IF THE 74S508IS,
; SELECTED. ALSO, ADDRESS 100 TO 107 IS RESERVED FOR THE 74S508. THE ADDRESS
;SPACE CAN BE CHANGED BY SIMPLY EDITING THE LOGIC

748508 1II....ory Map Interface #2
Title SN54/74S508 I/O DEVICE INTERFACE WITH THE INTEL 8085 (DESIGN # 2)
Pattern P7086
Revision A
.
Author' VINCENT COLI
Company 10(1' SUNNYVALE, CALIFORNIA"
Date
05/15/82
CHIP ~N54/7~S508-,I/Q_DEV;tCE~INTERF~CE_WITH_THE_INTEL_8085_tDESIGN_#_2) PAL16R4
CLK A15' A14A1~ A12 All A1C)A9A8 GNP
JOE 10M ALE' 12 11' 10 IGO $1 SQ. ,VCC
EQUATIONS
GO :=. /Al1*/A12*/A13* Al4*/A15
* 'tOJt*/Sl .. SO·

*

.'

/A~
., ~

'" ,

;MQNITOR ADDRESS BUS (All-A15)
; MONITOR MACHINE CYCLE STATUS (I/O WRITE)
; MONITOR ADDRESS/DATA CONTnOL (FALLING EDGE)

110 := IA8

;REGISTER

III :- /A9

;REGISTER INSTRUCTION INPUT 11

112 :- /A10

; REGISTER INSTRUCTION INPUT 12

INS~RUCTIONINPUT

10

;FUNCTION TABLE FOR PALASM 1
flOE CLKA8 A9 A10 All A12 A13 A14 A15 10M Sl so ALE 10 11 12 /GO
;
ADDR BUS
flOE CLK 89012345

MACH STATUS
10M Sl so
ALE

INSTR
012
/GO

COMMENTS
(OCTAL ADDRESS)

;------------------------------------------------------------------------(200 TO 207) INACTIVE
XXX
H
L
H L H
L
C XXXLLLLH
L
L
L
L
L
L
L
H

C
C
C
C
C
C
C
X

XXXLLLLH
XXXLLLHL
XXXLLLHL
XXXLLLHL
LHHLLLHL
LHHLLLHL
LLLLLLHL
XXXXXXXX

H
H
L
H
H
H
H
X

H
H
H
L
L
L
L
X

L
H
H
H
H
H
H
X

L
XXX
L
XXX
H XXX
XXX
L
LHH
L
H LHH
L· LLL
X ZZZ

H
H
H
L
L
H
L
Z

(100 TO 107) I/O REA
(100 TO 107) INTERRUPT ACKNOW
(100 TO 107) INACTIVE (ALE=H)
(100 TO 107) (ACTIVE RANGE)
(106) LOAD X
(106) NOP (ALE=H)
(100) LOAD Y
TEST HI-Z

;-----------------------------------------------------------------------; DESCRIPTION

;THIS PAL PROVIDES THE DECODE LOGIC FOR INTERFACING THEMMI SN54/74S508, 8~BIT .
;SEQUENTIAL MULTIPLIER/DIVIDER, WITH THE INTEL 8085 MICROPROCESSOR. THE PAL16R4
;MONITORS THE UPPER 8 BIT ADDRESS BUS (A8-A15), THE ADDRESS LATCH ENABLE (ALE),
;AND THE THREE MACHINE CYCLE STATUS LINES (IOM,Sl,SO) FRO

16 Input Registered Priority Encoder # 1
Title
Pattern
Revision
Author
Company
Date

16 INPUT REGISTERED PRIORITY ENCODER (CHIP No.1)
P7090 COLI/VOLPIGNO 10/13/82
A
COLI/VOLPIGNO
MMI SUNNYVALE, CALIFORNIA
10/13/82

CHIP 16_INPUT_REGISTERED_PRIORITY_ENCODER_(CHIP_No._1) PAL20R4
CLK 10 Il 12 13 14 15 16 17 18 19 GND
/OC 110 III 112 Q3 Q2 Q1QO 113,114 115 VCC
EQUATIONS
/QO:= /10* Il
+ /10*/11*/12* 13
+ /IO*/Il*/I2*/I3*/I4*I;5
+ /IO*/Il*/I2*/I3*/I4*/I5*/I6* 17
+ /IO*/Il*/I2*/I3*/I4*/I5*/I6*/I7*/I8*I9.
+ /IO*/Il*/I2*/I3*/I4*/I5.*/I6*/I7*/I8*/I9*/llO*ll1
+ /IO*/ll*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/llO*/Ill*/ll2* .ll3
+ /IO*/~1*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/llO*/ll1*/ll2*/IB*/ll4* ll5
/Q1 := /10*/11* 12
+ /IO*/ll*/I2* 13
+ /10*/11*/12*/13*/14*/15* 16
+ /J:0*/ll*/I2*/I3*/I4*/I5*/I6* 17

.'

+nO*/ll*/I2*;13*/I4YI5*/I6*/I7*/I8*/~9*

llO
+ /10*/11*/12*/13*/14*/15*/16*/17*/18*/19*/110* III
+/IO*/ll*/I2*/I3*/I41r/I5*/I6*/I7*/I8*/I9*/IlO*/Ill*/ll2*/ll3* ll4
+ /IO.*/ll*/I2*/I3*/I4*/I5*/I~*/I7*/I8*/I9*/IlO*/lll*/I.l2*/ll3*/I14* Il5
/Q2 := /Io*ill*/t2*/I3* 14
+ /IO*/ll*/I2*/I3*/I4* IS
+ /IO*/ll*/I2*/I3*/I4*/IS* 16
+ /IO*/ll*/I2*/I3*/I4*/IS*/I6* 17
+ /IO*/ll*/I2*/I3*/I4*/IS*/I6*/I7*/I8*/I9*/llO*/Il1* Il2
+ /IO*/Il*/I2*/I3*/I4*/IS*/I6*/I7*/I8*/I9*/IlO*/ll1*/Il2*Il3
+ /IO*/ll*/I2*/I3*/I4*/I5*/I6*/I7*/I8*/I9*/I10*/ll1*/ll2*/ll3* ll4
+ /IO*/ll*/I2*/I3*/I4*/IS*/I6*/I7*/I8*/I9*/llO*/ll1.*/ll2*/ll3*/1l4* ll5
/Q3 := /IO*/ll*/I2*/I3*/I4*/I5*'/16*/I7* 18
+ /IO*/ll*/I2*/I3*/I4*/IS*/:;::6*/l7*/I8* 19
.+ /IO*/ll*/I2*/I3*/I4*/IS*/I6*/I7*/I8*/I9* llO

+
+

/IO*/Il*/I2*/I3*/I4*/IS*/I6*/I7*/I8~/I9*/IlO* Ill,.
/IO*/ll*/I2*/I3*/I4*/I5~;(16*/I,7*/I8*/I9~/llO*/ll1*

1;12

+ /IO*/I!*/I2*/I3*/I4*/I5*/16*/17*/I$YI9*/llO*/Il1*/112* 1;13
+ /IO*/ll*/I2*/I3*/I4*/IS*/I6*/I7*/I8*/I9*/IlO*/ll1*/I12*/ll3* 114
+ /IO*/Il*/I2*/I3*/I4*/IS*/I6*/I7*/I8*/I9*/IlO*/ll1*/ll2*/ll3*/ll4* ll5
.-...

-=-__

16 Input· Registered Priority Encoder # 1
;FUNCTION TABLE FOR PALASM 1
;CLK JOC I15 I14 I13 I12 III Il0 I9 I8 I7 I6 I5 I4 I3 I2 Il IO Q3 Q2 Ql QO
; CHIP
; CONTROL
;CLK JOC

SIXTEEN INPUTS
111111
5432109876543210

OUTPUTS
QQQQ
3210

COMMENTS

i --::;---------.---------------------------------------------------------------

C
XXXXXXXXXXXXXXXH
L
HHHH
IO INTERRUPT (HIGHEST PRIORITY INPUT)
C
L
XXXXXXXXXXXXXXHL
HHHL
Il INTERRUPT
C
XXXXXXXXXXXXXHLL
L
HHLH
I2 INTERRUPT
C
XXXXXXXXXXXXHLLL
L
HHLL
I3
INTERRUPT
C
XXXXXXXXXXXHLLLL
L
HLHH
I4 INTERRUPT
C
L
XXXXXXXXXXHLLLLL
HLHL
I5 INTERRUPT
C
L
XXXXXXXXXHLLLLLL
HLLH
I6 INTERRUPT
C
XXXXXXXXHLLLLLLL
L
HLLL
I7 INTERRUPT
C
XXXXXXXHLLLLLLLL
L
LHHH
I8 INTERRUPT
C
XXXXXXHLLLLLLLLL
LHHL
L
I9 INTERRUPT
C
XXXXXHLLLLLLLLLL
L
LHLH
IlO INTERRUPT
C
LHLL
III INTERRUPT
L
XXXXHLLLLLLLLLLL
C
XXXHLLLLLLLLLLLL
LLHH
L
Il2 INTERRUPT
C
LLHL
L
XXHLLLLLLLLLLLLL
Il3 INTERRUPT
C
XHLLLLLLLLLLLLLL
Il4 INTERRUPT
L
LLLH
C
L
HLLLLLLLLLLLLLLL
LLLL
I15 INTERRUPT (LOWEST PRIORITY INPUT)
X
H
XXXXXXXXXXXXXXXX
ZZZZ
TEST HI-Z
1------------------------------------------------------------~-----------; DESCRIPTION
;THE 16 INPUT REGISTERED PRIORITY ENCODER ACCEPTS SIXTEEN ACTIVE-LOW INPUTS
;(IO-Il5) TO LOAD .THE BINARY WEIGHTED CODE OF THE PRIORITY ORDER INTO THE OUTPUT
;REGISTER (Q3-QO) ON THE RISING EDGE OF THE CLOCK (CLK). A.PRIORITY IS ASSIGNED
;TO EACH INPUT SO THAT WHEN TWO INPUTS ARE SIMULTANEOUSLY ACTIVE, THE INPUT WITH
;THE HIGHEST PRIORITY. IS LOADED INTO THE OUTPUT REGISTER. THEREFORE THE HIGHEST
;PRIORITY INPUT (IO=H) PRODUCES HHHH IN THE OUTPUT REGISTER AND THE LOWEST
;PRIORITY INPUT (Il5=H) PRODUCES LLLL IN THE OUTPUT REGISTER.
;OPERATIONS TABLE
IOC

CLK

H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L

X
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

I15-IO
X
IO =H
Il =H
Il =H
Il =H
Il =H
Il =H
Il =H
Il =H
Il =H
Il =H
Il =H
Il =H
Il =H
Il =H
Il =H
Il =H

Q3-QO
Z
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0

OPERATION
HI-Z
IO INTERRUPT (HIGHEST PRIORITY INPUT)
Il INTERRUPT
I2 INTEAAUPT
I3 INTERRUPT
14 INTERRUPT
I5 INTERRUPT
I6 INTERRUPT
I7 INTERRUPT
IS INTERRUPT
I9 INTERRUPT
IlO INTERRUPT
III INTERRUPT
Il2 INTERRUPT
Il3 INTERRUPT
Il4 INTERRUPT
Il5 INTERRUPT (LOWEST PRIORITY INPUT)

-------------------------------------------------------------------

7-40

Monolithic WMemories

16 Input Priority Encoder Interrupt Flag #2
Title
Pattern
Revision
Author
Company
Date

16 INPUT PRIORITY ENCODER INTERRUPT FLAG (CHIP No.2)
P7091
A

VINCENT COLI
MMI SUNNYVALE, CALIFORNIA
11/13/82

CHIP 16_INPUT_PRIORITY_ENCODER_INTERRUPT_FLAG_(CHIP_No._2) PAL16Cl
IO Il 12 13
14
IS
16 17 18 GND
19 Il0 III 112 POS INT NEG_INT 113 114 I1S VCC
EQUATIONS
NEG_INT = /IO*/Il*/I2*/I3*/I4*/IS*/I6*/I7*/I8*/I9*/IlO*/Ill*/Il2*/Il3*/Il4*/IlS
;FUNCTION TABLE FOR PALASM 1
;I1S 114 113 112 III I10 19 18 17 16 IS 14 13 12 Il IO NEG INT POS_INT
; SIXTEEN INPUTS
; 111111
;S432109876S43210

INTERRUPT
FLAG
NEG POS

COMMENTS

i---------------~---------~--------~------~------~---- ------~-~----------

;XXXXXXXXXXXXXXXH
;XXXXXXXXXXXXXXHL
;XXXXXXXXXXXXXHLL
;XXXXXXXXXXXXHLLL
;XXXXXXXXXXXHLLLL
;XXXXXXXXXXHLLLLL
;XXXXXXXXXHLLLLLL
;XXXXXXXXHLLLLLLL
;XXXXXXXHLLLLLLLL
;XXXXXXHLLLLLLLLL
;XXXXXHLLLLLLLLLL
;XXXXHLLLLLLLLLLL
;XXXHLLLLLLLLLLLL
;XXHLLLLLLLLLLLLL
;XHLLLLLLLLLLLLLL
;HLLLLLLLLLLLLLLL
;LLLLLLLLLLLLLLLL

L
L
L
L
L
L
L
L
L
L
L
L
L
L
L

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

L

H

H

L

IO
Il
12
I3
14
IS
16
I7
18
19
IlO
III
112
Il3
Il4
Il5
NO

INTERRUPT (HIGHEST PRIORITY INPUT)
INTERRUPT
INTERRUPT
INTERRUPT
INTERRUPT
INTERRUPT
INTERRUPT
INTERRUPT
INTERRUPT
INTERRUPT
INTERRUPT
INTERRUPT
INTERRUPT
INTERRUPT
INTERRUPT
INTERRUPT (LOWEST PRIORITY INPUT)
INTERRUPT INPUT

i-----------------------------------------------------------------------

: DESCRIPTION
;THE 16 INPUT PRIORITY ENCODER INTERRUPT FLAG ACCEPTS SIXTEEN ACTIVE-LOW INPUTS
; (IO-IlS) IN ORDER TO GENERATE. AN ACTIVE LOW (NEG_INT) AND ACTIVE HIGH (POS_INT)
;INTERRUPT FLAG.
;UP TO FOUR INTE.RRUP'l' ENABLE PINS OF ANY POLARITY CAN BE ADDED IF A PAL20Cl IS
;SUBSTI'l'UTED.

MonoIlthlc·I!!DMemorles

15 Input Registered Priority Encod.er
Title
Pattern
Revision
Author
Company
Date

15 INPUT REGISTERED PRIORITY ENCODER
P7092 COLl/VOLPIGNO 10/13/82
A
COLl/VOLPIGNO
MMl SUNNYVALE, CALIFORNIA
10/13/82

CHIP 15 INPUT REGISTERED PRIORITY ENCODER PAL20R4

-

-

-

-

CLK 10 II
12 13 14 15 16 17 18 19 GND
/OC 110 III FLAG Q3 Q2 Q1 QO 112 113 114 VCC
EQUATIONS
/QO :=
+
+
+
+
+

/10* II
/10*/11*/12* 13
/10*/Il*/12*/I3*/14* 15
/10*/11*/12*/13*/14*/15*/16* 17
/10*/11*/12*/13*/14*/15*/16*/17*/18* 19
/10*/11*/12*/13*/14*/15*/16*/17*/18*/19*/110* III
+ /10*/11*/12*/13*/14*/15*/16*/17*/18*/19*/110*/111*/112* 113
+ /IO*/I1*/I2*/I3*/I4*/I5*/I6*/17*/18*/19*/110*/Il1*/112*/I13*/Il4

/Q1 := /10*/11* I2
+ /IO*/11*/I2* 13
+ /10*/11*/I2*/13*/I4*/15* 16
+ /10*/11*/12*/13*/14*/15*/16* 17
+ /10*/11*/12*/I3*/14*/I5*/16*/17*/18*/19* 110
+ /IO*/11*/I2*/I3*/14*/15*/I6*/17*/18*/I9*/110* III
+ /IO*/Il*/12*/I3*/14*/15*/16*/17*/18*/19*/IlO*/Ill*/Il2*/Il3* Il4 .
+ /10*/11*/I2*/I3*/I4*/15*/16*/I7*/18*/19*/110*/Ill*/112*/I13*/Il4
/Q2 := /10*/11*/12*/13* 14
+ /10*/11*/12*/13*/14* 15
+ /10*/11*/12*/13*/14*/15* 16
+ /10*/Il*/I2*/I3*/14*/15*/16* 17
+ /10*/Il*/12*/13*/14*/15*/16*/17*/18*/19*/IlO*/I11* Il2
+ /IO*/11*/I2*/13*/I4*/15*/I6*/17*/I8*/19*/II0*/111*/I12* 113
+ /10*/I1*/I2*/13*/I4*/15*/16*/17*/18*/19*/II0*/111*/112*/113* 114
+ /10*/11*/12*/I3*/14*/15*/16*/17*/I8*/19*/II0*/111*/I12*/I13*/I14
/Q3 := /to*/Il*/12*/I3*/14*/15*/I6*/17* 18
+ /10*/11*/12*/13*/14*/15*/16*/17*/18* I9
+ /10*/11*/12*/13*/14*/15*/16*/17*/18*/19* 110
+ /10*/Il*/12*/I3*/14*/15*/16*/17*/18*/I9*/I10* III
+ /IO*/11*/12*/I3*/I4*/15*/I6*/17*/18*/19*/110*/111* 112
+ /10*/11*/12*/I3*/14*/15*/16*/17*/I8*/19*/110*/Il1*/I12* 113
+ /10*/11*/I2*/13*/I4*/15*/16*/17*/18*/19*/110*/111*/112*/113* 114
+ /10*/11*/12*/13*/14*/15*/16*/17*/18*/19*/110*/111*/112*/113*/114
/FLAG

7-42

= /10*/I1*/I2*/I3*/14*/I5*/16*/17*/18*/19*/II0*/111*/I12*/113*/I14

MotIoIlthiaW Memories

15 Input Registered Priority Encoder
;FUNCTION TABLE FOR PALASM 1
;CLK JOC 114 113 112 III 110 19 18 17 16 IS 14 13 12 11 10 Q3 Q2 Ql QO FLAG
; CHIP
; CONTROL
;CLK JOC

FIFTEEN INPUTS
11111
432109876543210

--OUTPUTS-QQQQ
3210
FLAG

COMMENTS

XXXXXXXXXXXXXXH
XXXXXXXXXXXXXHL
XXXXXXXXXXXXHLL
XXXXXXXXXXXHLLL
XXXXXXXXXXHLLLL
XXXXXXXXXHLLLLL
XXXXXXXXHLLLLLL
XXXXXXXHLLLLLLL
XXXXXXHLLLLLLLL
XXXXXHLLLLLLLLL
XXXXHLLLLLLLLLL
XXXHLLLLLLLLLLL
XXHLLLLLLLLLLLL
XHLLLLLLLLLLLLL
HLLLLLLLLLLLLLL
LLLLLLLLLLLLLLL
XXXXXXXXXXXXXXX

HHHH
HHHL
HHLH
HHLL
HLHH
HLHL
HLLH
HLLL
LHHH
LHHL
LHLH
LHLL
LLHH
LLHL
LLLH
LLLL
ZZZZ

10 INTERRUPT (HIGHEST PRIORITY INPUT)
Il INTERRUPT
12 INTERRUPT
I3 INTERRUPT
14 INTERRUPT
IS INTERRUPT;
16 INTERRUPT
17 INTERRUPT
18 INTERRUPT
19 INTERRUPT
IlO INTERRUPT
III INTERRUPT
Il2 INTERRUPT
Il3 INTERRUPT
Il4 INTERRUPT (LOWEST PRIORITY INPUT)
NO INTERRUPT
TEST HI-Z

i--------------------------------------------------------------------------C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
X

i

L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
X

---------------~-------------------------------~------ --------,-------------

; DESCRIPTION
;THE 15 INPUT REGISTERED PRIORITY ENCODER ACCEPTS FIFTEEN ACTIVE-LOW INPUTS
;(10-114) TO LOAD THE BINARY WEIGHTED CODE OF THE PRIORITY ORDER INTO THE OUTPUT
;REGISTER (Q3-QO) ON THE RISING EDGE OF THE CLOCK (CLK). A PRIORITY IS ASSIGNED
;TO EACH INPUT SO THAT WHEN TWO INPUTS ARE SIMULTANEOUSLY ACTIVE, THE INPUT WITH
;THE HIGHEST PRIORITY IS LOADED INTO THE OUTPUT REGISTER. THEREFORE THE HIGHEST
;PRIORITY INPUT (IO=H) PRODUCES HHHH IN THE OUTPUT REGISTER AND THE LOWEST
;PRIORITY INPUT (I14=H) PRODUCES LLLH IN THE OUTPUT REGISTER. THE NON-REGIST;ERED INTERRUPT FLAG (FLAG) GOES HIGH WHEN AN J;NTERRUPT IS PRESENT AND REMAINS
;LOW WHEN THERE IS NO INTERRUPT PRESENT.
;OPERATIONS TABLE

JOC

CLK

Il4-IO

Q3-QO

H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L

X
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

X
L
10 =H
11 =H
12 =H
13 =H
14 =H
IS =H
16 =H
J;7 =H
18 =H
19 =H
IlO=H
Ill=H
Il2=H
Il3=H
Il4=H

Z
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

FLAG

OPERATION

-------------------------------------------------------------------------X

L

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

HI-Z
NO INTERRUPT
10 INTERRUPT (HIGHEST PRIORITY INPUT)
11 INTERRUPT
12 INTERRUPT
I3 INTERRUPT
14 INTERRUPT
IS INTERRUPT
16 INTERRUPT
INTERRUPT
I7
18 INTERRUPT
19 J;NTERRUPT
IlO INTERRUPT
III INTERRUPT
Il2 J;NTERRUPT
Il3 J;NTERRUPT
Il4 INTERRUPT (LOWEST PRIORITY INPUT)

--------------------------------------------------------------------------

MonoIithicWMemorles

7-43

',8

Title
Pattern'.
Revision
Author
Company
Date

Input Registered Priorltv Encoder

8 INPUT REGISTERED PRIORITY ENCODER WITH IN.TERRUPTFLAG
P7093
A
VINCENT COLI
MMI SUNNYVALE, CALIFORNIA
0.6/21/82

CHIP 8":'INPUT_REGISTERED..;..PRIORIT·~CENCODER_WITH_INTERRUPT .FLAG PAL16R4
CLK 10 Il 12 13 14 15 16 17 GN.D
IOC /E4 /E3 Q3 Q2 Q1 QO E2 E1 VCC
EQUATIONS
IO=L
AND I1=H
;DECODE IO-2';"LAND I3=H
; DECODE 10-.4=1. AND 15=H
;DECODE IO-6=LANDI7=H

IQO :=
+
+
+

/10* Il
/10*/11*/12* 13
/10*/11*/12*/13*/14* 15
/IO*/Il*/I2*/I3*/I4*/I5*/I6* 17

;OEC~DE

/Q1 :=
+
+
+

/IO*/Il* 12
/10*/11*/12* 13
/IO*/I1*/I2*/13*/I4*/I5* 16
/IO*/I1*/!2*/I3*/!4*/15*/I6* 17

;DECODE
;DECODE
;DECODE
;DECODE

IO-1=L
IO-2=L
IO-5=L
IO-6=L

;DECODE
;DECODE
;DECODE
;DECODE

IO-3=L AND I4=H
IO-4=L.AND I5=H
IO-5=L AND I6=H
IO-6=L ANDI7=H

/Q2 := /IO*/I1~/I2*/I3* 14
+/10*/11*/12*/13*/14* 15
+ /IO*/Il.*/I2*/I3*/I4*/15* 16

+lIO*/I1*/I2~/I3*/I4*/I5*/I6*

IQ3 :=
+

+

+
+
+
+
+

El*
E1*
El*
E1*
E1*
E1*
E1*
E1*

E2*
E2*
.E2*
E2*
E2*
E2*
E2*
E2*

E3* E4* 10
E3*. E4* Il
~3* E4* 12
E3* E4* 13
E3* E4* 14
E3* E4* 15
E3* E4* 16
E3* E4* 17

17

INTERRUPT
INTERRUPT
. INTERRUPT
INTERRUPT
INTERRUPT
INTERRUPT
INTERRUPT
INTERRUPT

MonoIlthlc.IRMMentorles

AND
AND
AND
AND

FLAG
.FLAG
FLAG
FLAG
FLAG
FLAG
FLAG
FLAG

I2=H
I3=H
I6=H
I7=H

(10)
(11)
(I~)

(Il) .
(14)
(15)
(16)
(17)

8 Input Registered Priority Encoder
iFUNCTION TABLE FOR PALASM 1
iCLK joe E1 E2 jE3 jE4 I7 I6 I5 I4 I3 I2 Il IO Q3 Q2 Q1 QO
; CHIP

; CONTROL
;CLK joe

----FOUR----INPUT ENABLES
E1 E2 jE3 jE4

8 INPUTS

IIIIIIII
76543210

OUTPUTS
Q QQQ
3 210

COMMENTS

i ---------------------------------------------------------':'"'-------------------

C
C
C
C
C
C
C
C
C

C
C
C
C
C
C
C
C
C
C
C

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

C
C
C
X

L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H

L
H
H
H
H
L
H
H
H
H
L.
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
X

H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
X

L
L
H
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
L
L
L
L

H
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
L
L

r..

X

L
L
L
H
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
L
L

L
L
H
L
L
L
L
H
L
L
L
L
H
L
L
X

XXXXXXXH
XXXXXXXH
XXXXXXXH
XXXXXXXH
XXXXXXXH
XXXXXXHL
XXXXXXHL
XXXXXXHL
XXXXXXHL
XXXXXXHL
XXXXXHLL
XXXXXHLL
XXXXXHLL
XXXXXHLL
XXXXXHLL
XXXXHLLL
XXXXHLLL
.XXXXHLLL
XXXXHLLL
XXXXHLLL
XXXHLLLL
XXXHLLLL
XXXHLLLL
XXXHLLLL
XXXHLLLL
XXHLLLLL
XXHLLLLL
XXHLLLLL
XXHLLLLL
XXHLLLLL
XHLLLLLL
XHLLLLLL
XHLLLLLL
XHLLLLLL
XHLLLLLL
HLLLLLLL
HLLLLLLL
HLLLLLLL
HLLLLLLL
HLLLLLLL
LLLLLLLL
XXXXXXXX

H HHH
H HHH
H HHH
H HHH
L HHH
H HHL
H HHL
H HHL
H HHL
L HHL
HHLH
HHLH
HHLH
HHLH
LHLH
H HLL
H HLL
H HLL
H HLL
L HLL
H LHH
H LHH
H LHH
H LHH
L LHH
H LHL
H LHL
H LHL
H LHL
L LHL
H LLH
H LLH
H LLH
H LLH
L LLH
H LLL
H LLL
H LLL
H LLL
L LLL
H HHH
Z ZZZ

INTERRUPT
INTERRUPT
INTERRUPT
INTERRUPT
INTERRUPT
INTERRUPT
INTERRUPT
I l INTERRUPT
I l INTERRUPT
I l INTERRUPT
I2 INTERRUPT
I2 INTERRUPT
I2 INTERRUPT
I2 INTERRUPT
I2 INTERRUPT
13 INTERRUPT
I3 INTERRUPT
I3 INTERRUPT
13 INTERRUPT
I3 INTERRUPT
I4 INTERRUPT
I4 INTERRUPT
14 INTERRUPT
I4 INTERRUPT
I4 INTERRUPT
I5 INTERRUPT
I5 INTERRUPT
I5 ;j:NTERRUPT
I5 INTERRUPT
I5 INTERRUPT
I6 INTERRUPT
I6 INTERRUPT
I.6 INTERRUPT
I6 INTERRUPT
I6 INTERRUPT
I7 INTERRUPT
I7 INTERRUPT
I7 INTERRUPT
I7 INTERRUPT
I7 INTERRUPT
NO INTERRUPT
TEST HI-Z

IO
IO
IO
IO
IO
Il
Il

NOT· ENABLED (E1=L)
NOT ENABLED (E2=L)
NOT ENABLED(jE3=H)
NOT ENABLED(jE4=H)
(HIGHEST PRIORITY)
NOT ENABLED (E1=L)
NOT ENABLED (E2=L)
NOT ENABLED(/E3=H)
NOT ENABLED(/E4=H)
NOT
NOT
NOT
NOT

ENABLED (E1=L)
ENABLED (E2=L)
ENABLED(/E3=H)
El'l'ABLED(/E4=H)

NOT ENABLED (E1=L)
NOT ENABLED (E2=L)
NOT ENABLED(jE3=H)
NOT EN~BLED(jE4=H)
NOT
NOT
NOT
NOT

ENABLED (E1=L)
ENABLED (E2=L)
ENABLED(jE3=H)
ENABLED UE4=H)

NOT
NOT
NOT
NOT

ENABLED (E1=L)
ENABLED (E2=L)
ENABLED(jE3=H)
ENABLED (/E4=H)

NOT
NOT
NOT
NOT

ENABLED (E1=L)
ENABLED (E2=L)
ENABLED(jE3=H)
ENABLED (/E4=H)

NOT ENABLED (E1=L)
NOT ENABLED. (E2=L)
NOT ENABLED(/E3=H)
NOT ENABLED(jE4=H)
(LOWEST PRIORITY)
INPUT (Q3=H)

i ----------------------------------------------------------------------------

Monolithic WMemories

7-45

0

8 Input Registered Priority Encoder
; DESCRIPTION
;THE 8 INPUT REGISTERED PRIORITY ENCODER ACCEPTS SIXTEEN ACTIVE.-LOW INPUTS
;(IO-I7) TO LOAD THE BINARY WEIGHTED CODE OF THE PRIORITY ORDER INTO THE OUTPUT
;REGISTER (Q2-QO) ON .THE RISING EDGE OF THE CLOCK (CLK) PROVIDING THE FOUR
;ENABLE INPUTS ARE TRUE (El=H,E2=H,/E3=L,/E4=L). A PRIORITY IS ASSIGNED TO EACH
;INPUT SO THAT WHEN TWO INPUTS ARE SIMULTANEOUSLY ACTIVE, THE INPUT WITH THE
;HIGHEST PRIORITY IS LOADED INTO THE OUTPUT REGISTER. THEREFORE THE HIGHEST
;PRIORITY INPUT (IO=H) PRODUCES HHH .IN THE OUTPUT REGISTER AND THE LOWEST
;PRIORITY INPUT (I7=H) PRODUCES LLL IN THE OUTPUT REGISTER.
;THE PRIORITY INTERRUPT ENCODER REGISTERS (Q3-QO) ARE UPDATED ON THE RISING EDGE
;OF THE CLOCK (CLK) PROVIDING THE FOUR ENABLE INPUTS ARE TRUE (El=H,E2=H,/E3=L,
; /E4=L). THE PREVIOUS DATA IS HELD IN THE PRIORITY .ENCODER REGISTERS IF ANY OF
;THE ENABLE INPUTS ARE FALSE (El=L,E2=L,/E3=H,/E4=H). REGARDLESS OF CLOCK
;TRANSITIONS. NOTE THAT THE POLARITY OF THE ENABLES CAN BE CHANGED BY MERELY
;EDITING THE LOGIC EQUATIONS.
;OUTPUT Q4 SERVES AS THE INTERRUPT FLAG AND IS TRUE (Q4=L) WHEN ANY OF THE 8
;INPUTS ARE. ACTIVE (I=H) ON THE RISING EDGE OF THE CLOCK (CLK) PROVIDING THE
;FOUR ENABLE INPUTS ARE TRUE (El=H,E2=H,/E3=L,/E4=L). THE INTERRUPT FLAG IS
;FALSE (Q4=H). WHEN ALL INPUTS ARE INACT:):VE (I=L) OR WHEN ANY ONE OF THE FOUR
;ENABLE INPUTS ARE FALSE (El=L,E2=L,/E3=H,/E4=H).
; OPERATIONS TABLE
;/OC

eLK

L
L
L
L
L
L
L
L

C
C
C
C
e
C
e
e
e
C
e
C
C

El E2 /E3 jE4

I7-IO

Q4

Q3-QO

OPERATION

i------------------------------------------------------------------------H
X
X X
X
X
X
Z
Z
HI-Z

L
L
L

L
L

L X
X L
X X
X

x

X
X
H
X

H
H
H
H
H
H
H
H
H

H
L
H
L
H
L
H
L
H
L
H
L
H ·L
H
L
L
H

X
X

X
X

X

X
X

H
L
L
L
L
L

L
L
L
L

L
IO=H
.Il=H
I1=H
I1=H
Il=H
Il=H
Il=H
Il=H

H
H
H
H
H
L
L

Q
Q
Q
Q

L
L

5

L
L
L
L

X

7
6

4

3

:2
1
0

NOT ENABLED (El=L)
NOT ENABLED (E2=L)
NOT ENABLED (lE3=H)
NOT ENABLED (lE4=H)
.NO INTERRUPT FLAG
IO INTERRUPT (HIGHEST PRIORITY)
t l INTERRUPT
12 INTERRUPT
13 INTERRUPT
14 INTERRUPT
15 INTERRUPT
16 INTERRUPT
17 INTERRUPT (LOWEST PRIORITY)

,._--------------------------------------------------------------------------.
.

7-46

Monolithic

W Memories

Dual Stepper Motor Controller
Title
Pattern
Revision
Author
Company
Date

DUAL STEPPER MOTOR CONTROLLER
P7094
A
COLI/SACKETTE
MMI SUNNYVALE, CALIFORNIA
12/07/82

CHIP DUAL_STEPPER_MOTOR_CONTROLLER PAL16R8
CLK /ENA
SETA ROTA MODEA /ENB
SETB ROTB MODEB GND
/OC /SWIB /SW2B /SW3B /SW4B /SW4A /SW3A /SW2A /SWIA VCC
EQUATIONS
SWIA ,:=
+
+
+
+
+

SW1A

*/ENA
*/SW4A* ENA* ROTA*MODEA
SW3A
* ENA* ROTA*/MODEA
/SW2A*/SW3A
* ENA*/ROTA* MODEA
SW4A* ENA*/ROTA*/MODEA
ENA
* SETA
/SW2A

SW2A :=
+ /SWIA
+
+ /SWIA
+

*/ENA
* ENA* ROTA* MODEA*/SETA
SW4A* ENA* ROTA*/MODEA*/SETA
,*/SW4A* ENA*/ROTA* MODEA*/SETA
SW3A
* ENA*/ROTA*/MODEA*/SETA

;,HOLD SW2A
;HALF-STEP
;FULL-STEP
;HALF-STEP
;FULL-STEP

*/ENA
SW3A,
*/SW4A* ENA* RO~A* MODEA
* ENA* ROTA*/MODEA
*/SW4A* ENA*/ROTA* MODEA
* ENA*/ROTA*/MODEA
ENA
* SETA

;HOLD SW3A (DISABLE)
;HALF-STEP MOTOR CW
;FULL-STEP MOTOR CW
;HALF-STEP MOTOR CCW
iFULL-STEP MOTOR CCW
;SET A TO STEP 1

SW2A
'*/SW3A

SW3A :-::;i
+ /SWIA
SW2A
+
/SW2A
+
+ SWIA
+

SW4A :=
+
/SW2A*/SW3A
+ SWIA
+ /SWIA
*/SW3A
SW2A
+
SWIB :=
+
+
+'

SWIB

+
+
SW2B :=

+ /SWIB
+
+ /SWIB
+

SW4A*/ENA
* ENA* ROTA* MODEA*/SETA
* ENA* ROTA*/MODEA*/SETA
* Ell'A*/ROTA* MODEA*/SETA
* ENA*/ROTA*/MODEA*/SETA

ok/ENB
*/SW4B* ENB* ROTB*" MODEB
SW3B
* ENB* ROTB,*/MODEB
/SW2B*/SW3B
* ENB*/ROTB* MODEB
SW4B* ENB*/ROTB*/MODEB
ENB
* SETB

/SW2B

SW2B

;H;OLD SW4A
;HALF-STEP
;FULL-STEP
;HALF-STEP
;FULL-STEP

(DISABLE)
MOTOR CW
MOTOR CW
MOTOR CCW
MOTOR CCW

(DISABLE)
MOTOR CW
MOTOR CW
MO'l'OR CCW
MOTOR CCW

;HOLD SWIB (DISABLE)
;HA~F-STEP MOTOR CW
;FULL-STEP MOTOR CW
; HALF-STEP MOTOR CCW
;FULL-STEP MOTOR CCW
;SET B TO STEP 1

*/ENB
* ENB* ROTB* MODEB*/SETB
SW4B* ENB* ROTB*/MODEB*/SETB
*/SW4B* ENB*/ROTB* MODEB*/SETB
SW3B
* ENB*/ROTB*/MODEB*/SETB

;HOLD SW2B
;HALF-STEP
;FULL-STEP
;HALF-STEP
;FULL-STEP

SW3B

;HOLD SW3B (DISABLE)
;HALF-STEP MOTOR CW
;FULL-STEP MOTOR CW
;HALF-STEP MOTOR CCW
; FULL-STEP MOTOR CCW
;SET B TO STEP 1

*/SW3B

SW3B :=
+ /SWIB
+
SW2B
+
/SW2B
+ SWIB
+

iHOLD SWIA (DISABLE)
;HALF-STEP MOTOR CW
;FULL-STEP MOTOR CW
; HALF,-STEP MOTOR CCW
;FULL-STEP MOTOR CCW
;SET A TO STEP 1

*/ENB
*/SW4B* ENB* ROTB* MODEB
* ENB* ROTB*/MODEB
*/SW4B* ENB*/ROTB* MODEB
* ENB*/ROTB*/MODEB
ENB
* SETB

Monellthlc

W Memories,

(DISABLE)
MOTOR CW
MOTOR CW
MOTOR CCW
MOTOR CCW

7-47

Dual Stepper Motor Controller
SW4B :=
ISW2B*/SW3B
+
+ SW1B
+ ISW1B
*/SW3B
SW2B
+

SW4B*/ENB
* ENB* ROTB* MODEB*/SETB
* ENB* ROTB*/MODEB*/SETB
* ENB*/ROTB* MODEB*/SETB
* ENB*/ROTB*/MODEB*/SETB

;HOLD SW4B
;HALF-STEP
;FULL-STEP
; HALF-STEP
;;FULL-STEP

(DISABLE)
MOTOR CW
MOTOR CW
MOTOR CCW
MOTOR CCW

;FUNCTION TABLE FOR PALASM 1
;CLK IOC lENA SETA ROTA MODEA SW1A SW2A SW3A SW4A IENB SETB ROTB MODEB SW1B
;SW2B SW3B SW4B
CHIP
; CONTROL
;CLK IOC

;

STEPPER MOTOR A

SSSS

wwww

lEN SET ROT MODE 1234

STEPPER MOTOR B

SSSS

wwww

lEN SET ROT MODE 1234

COMMENTS

; -------------,----,----------------------'------------ ------------------------~~

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
X

L
L
·L
L
L
L
L
L
L
L
L
L
L
L
L
H

L
L
L
H
L
L
L
L
L
L
H
L
L
L
L

H
L.
L
L
L
L
L
L
L
L
L
L
L
L
L

X

X

H
H
It
H
H
H
H
H
H
L
L
L
L
L

H
H
H
H
H
H
H
H
H
L
L
L
L
L

X

X

X

X

HLHL
HLLL
HLLH
HLLH
LLLH
LHLH
LHLL
LHHL
LLHL
HLHL
HLHL
LHHL
LHLH
HLLH
HLHL
ZZZZ

L
L
L
H
L
L
L
L
L
L
H
L
L
L
L

x

H
L
L
L
L
L
L
L
L
L
L
L
L
L
L

x

X

X

L
L
L
L
L
L
L
L
L
H
H
H
H
H

H
H
H
H
H
H
H
H
H
L
L
L
L
L

x

x

HLHL
LLHL
LHHL
LHHL
LHLL
LHLH
LLLH
HLLH
HLLL
HLHL
HLHL
HLLH
LHLH
LHHL
HLHL
ZZZZ

SET A AND B Tb STEP 1
FULL STEP A CW, B CCW
FULL STEP A CW, B CCW
HOLD MOTOR POSITION
FULL STEP A CW, B CCW
FULL STEP A CW, B CCW
FULL.STEP A CW, B CCW
FULL STEP A CW, B CCW
FULL STEP A CW, B CCW
FULL STEP A CW, B CCW
HOLD MOTOR POSITION
HALF STEP A CCW, B CW
HALF STEP A CCW, B CW
HALF STEP A CCW, B CW
HALF STEP A CCW, B CW
TEST HI-Z

;---------------------------------------------------------------------------; DESCRIPTION
;CLK IOC lEN
i

SET

ROT

SW1...,SW4

MODE

COMMENTS

-----~--------,--,---------~~_----------------'------- ----------------,-----------

;X

;C
;C
;C
;C
;C
;C

H
L
L
L
L
L
L

x

H
L
L
L
L
L

X
X

H
L
L
L
L

x

x

X
X

X
X

H
H
L
L

H
L
H
L

SW
SW
SW
SW

Z
HOLD
1
PLUS
PLUS
MINUS
MINUS

1
2
1
2

HI-Z
HOLD MOTOR POSITION
SET MOTOR POSITION Tb STEP 1
HALF-STEP MOTOR CLOCKWISE
FULL-STEP MOTOR CLOCKWISE
HALF-STEP MOTOR COUNTERCLOCKWISE
FULL-STEP MOTOR.COUNTERCLOCKWISE

i~--------~--------------------------~---------------- -----------------------r600950M

7-48

Monolithic WMemo,.ies

Clean Octal Latch
Title
Pattern
Revision
Author
Company
Date

CLEAN OCTAL LATCH
P7096
A
VINCENT COLI
MMI SUNNYVALE, CALIFORNIA
03/10/83

CHIP CLEAN- OCTAL- LATCH PAL20L10
G NC DO D1 D2 D3 D4 D5 D6 D7 NC GND
/OC NC Q7 Q6 Q5 Q4 Q3 Q2 Q1 QO NC VCC
EQUATIONS
IF (OC)

/QO

IF(OC)

/Q1

G*/DO
+ /G*/QO
+ /DO*/QO

; LOAD LATCH (QO)
;LATCH OUTPUT
;COVER ALWAYS-HIGH HAZARD

G*/D1

;LOAD LATCH (Q1)
;LATCH OUTPUT
;COVER ALWAYS HIGH HAZARD

+ /G*/Q1
+ /D1*/Q1
IF (OC)

/Q2 =
+

IF(OC)

/Q3

G*/D2
/G*/Q2
+ /D2*/Q2

; LOAD LATCH (Q2.)
;LATCH OUTPUT
iCOVER ALWAYS HIGH HAZARD

G*/D3

;LOAD LATCH (Q3)
;LATCH OUTPUT
;COVER ALWAYS HIGH HAZARD

+ /G*/Q3
+ /D3*/Q3
IF(OC)

/Q4

G*/D4

+ /G*/Q4
+ /D4*/Q4
IF(OC)

/Q5

G*/D5

+ /G*/Q5
+ /D5*/Q5
IF (OC)

/Q6

G*/D6

+ /G*/Q6

+ /D6*/Q6

IF(OC)

/Q7

G*/D7

+ /G*/Q7
+ /D7*/Q7

;LOAD LATCH (Q4)
;LATCH OUTPUT
;COVER ALWAYS HIGH HAZARD
;LOAD LATCH (Q5)
;LATCH OUTPUT
;COVER ALWAYS HIGH HAZARD
;LOAD LATCH "'(Q6)
;LATCH OUTPUT
;COVER ALWAYS HIGH HAZARD
;LOAD LATCH (Q7)
;LATCH OUTPUT
;CbVER ALWAYS HIGH HAZARD

Monolithic

m

Memories

7-49

C'eanOctal Latch
;FUNCTION TABLE FOR PALASM 1
JOC G D7 D6 D5 D4 D3 D2 D1 DO Q7 Q6 Q5 Q4 Q3 Q2 Q1 QO

; CONTROL
;jOC

G

L
L
L
L

H
L
H
L

L

H
L
H
L
X

DDDDDDDD
76543210

QQQQQQQQ
76543210

LLLLLLLL

LLLLLLLL
LLLLLLLL
HHHHHHHH
HHHHHHHH

COMMENTS

j--------------------------------------------------------------

L
L
L
H

XXXXXXXX
HHHHHHHH

XXXXXXXX
HLHLHLHL

XXXXXXXX
LHLHLHLH

XXXXXXXX

xxxxxxxx

HLHLHLHL
HLHLHLHL
LHLHLHLH
LHLHLHLH

ZZZZZZZZ

LOAD ALL ZEROS
LATCH ALL ZEROS
LOAD ALL ONES·
LATCH . ALL ONES
LOAD EVEN CHECKERBOARD
LATCH EVEN CHECKERBOARD
LOAD ODD CHECKERBOARD
LATCH ODD CHECKERBOARD
TEST HI-Z

j-------------------------------~~-------------------- ----------

; DESCRIPTION
;THIS PAL16L8 IMPLEMENTS AN 8-BIT LATCH FUNCTION WITH THREE-STATE. OUTPUTS. THE
;LATCH PASSES EIGHT BITS OF DATA (D7-DO) TO THE EIGHT OUTPUTS (Q7-QO) WHEN LATCH
;ENABLE IS TRUE (G=HIGH). THE DATA IS LATCHED WHEN LATCH ENABLE IS FALSE
; (G=LOW). THE OUTPUTS WILL BE DISABLED (HI-Z) WHEN OUTPUT ENABLE IS TRUE
;(jOC=TRUE) REGARDLESS OF ANY OTHER INPUTS.
;jOC

G

D7-DO

Q7-QO

; L
; L

L
H

X
D

Q
D

COMMENTS

;------------------------------------; H
X
X
Z
HI-Z
LATCH OUTPUT
LOAD LATCH

j-------------------------------------

;THIS DESIGN SHOWS HOW TO IMPLEMENT A 11 CLEAN 11 LATCH SINCE THERE ARE NO OUTPUT
;GLITCHES AS THE DEVICE CHANGES STATE. THE KARNAUGH MAP BELOW FOR 0+
;ILLUSTRATES THIS. THE TWO HORIZONTAL CIRCLES REPRESENT THE "LOAD LATCH" AND
;"LATCH OUTPUT" PRODUCT LINES. THE VERTICAL CIRCLE LINKS TOGETHE~ THE OTHER
;CIRCLES IN ORDER TO COVER A POTENTIAL SWITCHING HAZARD WHICH WOULD OCCUR WHEN
;THE OUTPUTS ARE ALWAYS HIGH.
;G
1- 00
01
11
10
1----1----1----1----1
O! 01 11 1! 01
!-------------------!
1! 0 1 1! 1 1 1.1
I----!----I--~-I~---I

7-50

MonoIlthlcWMemories

Shaft Encoder # 1
Title
Pattern
Revision
Author
Company
Date

SHAFT ENCODER No. 1PAL16R4
P7097
A
WILLY VOLDAN
MMI GMBH MUNICH
09/09/82

CHIP SHAFT- ENCODERNo.
1 PAL16R4
CLK PHIO PHI90 X4 NC NC NC NC /SSET GND
/OC DOWN NC
S4 S3 S2 S1 NC UP VCC
EQUATIONS
/S1 :=

+

/PHIO
SSET

;CHECK FOR PHIO
;INITIALIZE Sl=L

/S2 :=

/Sl
SSET

;CHECK FOR S1
;INITIALIZE S2=L

/S3 :=
+

/PHI90
SSET

;CHECK FOR PHI90
;INITIALIZE S3=L

/S4 :=

/S3
SSET

;CHECK FOR S3
;INITIALIZE S4=L

+

+

IF (VCC) /DOWN

Sl* S2* S3*/S4* PHIO* PHI90

+ /S1*/S2*/S3* S4*/PHIO*/PHI90
+ S1*/S2*/S3*/S4* PHIO*/PHI90
+ /S1* S2* S3* S4*/PHIO* PHI90
IF (VCC) /UP

/S1*/S2* S3*/S4*/PHIO* PHI90

+ S1* S2*/S3* S4* PHIO*/PHI90
+ S1*/S2* S3* S4* PHIO* PHI90
+ /S1* S2*/S3*/S4*/PHIO*/PHI90

PH!O
PHIO
PHIO
PHIO
PHI90
PHI90
PHI90
PHI90

LEADS
LEADS
LEADS
LEADS
LEADS
LEADS
LEADS
LEADS

PHI90
PHI90
PHI90
PHI90
PHIO
PHIO
PHIO
PHIO

;FUNCTION TABLE FOR PALASM 1
;CLK /OC /SSET PHIO PHI90 S4 S3 S2 S1 UP DOWN

MonoIllhlcWMemorles

7-51

Shaft Encoder # 1
;---CONTROLS--;CLK JOC jSSET

--INPUTS-PHIO PHI90

SSSS
4321

OUTPUTS
UP DOWN

COMMENTS

;-----------------------------------------------------------------------------C
CLEAR REGISTERS
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
X

L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L

L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H

L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X

X

X

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L

L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L

X

X

L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L

L
L
L
L
H
H
H
H
L
L
L
L
H
H
H

X

X

H

L
L
L
L
H
H
H
H
L
L

LLLL
LLLL
LLLL
LHLL
HHLL
HHLH
HHHH
HLHH
LLHH
LLHL
LLLL
LHLL
HHLL
HHLH
HHHH
HLHH
LLHH
LLHL
LLLL
LHLL
HHLL
HHLH
HHHH
HLHH
LLHH
LLHL
LLLL
LLLL
LLLL
LLLL
LLLH
LLHH
LHHH
HHHH
HHHL
HHLL
HLLL
LLLL
LLLH
LLHH
LHHH
HHHH
HHHL
HHLL
HLLL
LLLL
LLLH
LLHH
LHHH
HHHH
HHHL
HHLL
HLLL
LLLL
ZZZZ

H
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

x

H
H
H
H
H
H
H

Ii

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X

COUNT UP
COUNT UP
COUNT UP
COUNT UP
COUNT UP
COUNT UP
COUNT UP
COUNT UP
COUNT UP
COUNT UP
COUNT UP
COUNT UP
CLEAR REGISTERS
COUNT DOWN
COUNT DOWN
COUNT DOWN
COUNT DOWN
COUNT DOWN
COUNT DOWN
COUNT DOWN
COUNT DOWN
COUNT DOWN
COUNT DOWN
COUNT DOWN
COUNT DOWN
TEST HI-Z

:------------------------------------------------------------------------------

7-52

MonoilthlcWMemorles

Shaft Encoder # 1
; DESCRIPTION:
;THIS PAL16R4 IMPLEMENTS A TWO CHANNEL SHAFT ENCODER OF THE TYPE USED IN SPEED
;CONTROLLERS AND OPTICAL DEVICES.
;BOTH THE "UP" AND "DOWN" OUTPUTS OF THE PAL ARE NORMALLY HIGH.
;WHEN THE SIGNAL AT THE "PHIO" INPUT LEADS THE
;"DOWN" OUTPUT ALTERNATES BETWEEN HIGH AND LOW
;FREQUENCY RATE. ALSO, WHEN THE SIGNAL AT THE
;THE "PHI90" INPUT, THE "UP" OUTPUT ALTERNATES
;HALF THE "CLK" FREQUENCY RATE.

SIGNAL AT THE "PHI90" INPUT, THE
LEVELS AT HALF THE "CLK"
"PHIO" INPUT LAGS THE SIGNAL AT
BETWEEN HIGH AND LOW LEVELS AT

;THE SHAFT ENCODER FEATURES THE CONFIGURATION AND OUTPUT POLARITY TO DRIVE AN
;74S193 TYPE UP/DOWN COUNTER.
THIS DESIGN WITH GLITCHFREE OUTPUTS WILL BE EXTREMELY USEFUL IN ELECTRICALLY
NOISY ENVIRONMENTS. THE PINNING IS GIVEN AS A FIRST PROPOSAL AND CAN BE
CHANGED ACCORDING TO THE PC-BOARD LAYOUT.

Monolithic WMemorles

7·53

Shaft Encoder #2
Title
Pattern
Revision
Author
Company
Date

8HAFT ENCODER No. 2
P7098
A
WILLY VOLDAN
MMI GMBH MUNICH
09/09/82

CHIP 8HAFT_ENCODER_No._2 PAL16R8
CLK .PHIO.PHI90X4 NC NC NC NC /88ET GND
/OC UD NC S4 53 52 51 NC COUNT VCC
EQUATION8
/Sl

:= /PHIO
+ 85ET

;CHECK FOR PHIO
;INITIALIZE 81=L

/S3

:= /PHI90
+ 58ET

;CHECK FOR PHI90
;INITIALIZE 83=L

/82

:=

+
/S4

:=

+
/COUNT :=

+
+
+
+
+
+
+

IUD

81
55ET

;CHECK FOR /Sl
;INITIALIZE 82=L

S3
S5ET

;CHECK FOR /83
;INITIALIZE 54=L

51* S2*/53* 54
/Sl*/82* S3*/84
/51* 52*/53*/84*
51*/52* 83* 84*
Sl* 82* 53*/84
/81*/82*/83* 54
/51* 52* S3* S4*
Sl*/52*/83*/54*

THI5 OUTPUT ALTERNATE8
BETWEEN HIGH AND LOW WITH
HALF OR QUARTER THE
CLK FREQUENCY

X4
X4
X4
X4

THI5 OUTPUT DETERMINE5
IF 5IGNAL PHIO LEADS
OR LAG5 5IGNAL PHI90

:= /81* 82*/53* 54
+ /Sl* 82* 53* 84
+ /81* 52* S3*/54
+ Sl* 52* 83*/84
+ 51*/S2* 53*/84
+ 51*/52*/83*/84
+ 81*/82*/53* 54
+ /51*/82*/83* 84

TBO\01OM

7-54

Monolithic

W Memories

Shaft Encoder #2
;FUNCTION TABLE FOR PALASM 1
;CLK JOC jSSET PHIO PHI90 X4 Sl S2 S3 S4 COUNT UD
;---CONTROIS--;CLK JOC jSSET

--INPUTS-PHIO PHI90

x

-OUTPUTSSSSS
COUNT UD
COMMENTS
4
1234
;--------------------------------~-------------------- ------------------------C
L
L
X
CLEAR REGISTERS
X
X
LLLL
H
H
C
L
H
L
COUNT UP X4=L
L
L
LHLH
H
H
C
L
H
H
L
L
H
L
HHLH
C
L
H
H
L
L
HLLH
L
H
C
L
H
H
H
H
L
HLHH
L
C
L
H
H
H
L
HLHL
H
H
C
L
H
L
H
L
LLHL
H
L
C
L
H
L
H
L
LHHL
L
H
C
L
H
L
L
L
LHLL
H
L
C
L
H
L
L
L
LHLH
H
H
C
L
H
H
L
L
HHLH
H
L
C
L
H
H
L
L
HLLH
L
H
C
L
H
H
H
L
HLHH
H
L
C
L
H
H
H
L
HLHL
H
H
C
L
H
L
H
L
LLHL
H
L
C
L
H
L
H
L
LHHL
L
H
C
L
H
L
L
H
LHLL
H
L
COUNT UP X4=L
C
L
H
L
L
L
H
H
LHLH
C
L
H
H
L
H
HHLH
H
L
C
L
H
H
L
H
HLLH
L
H
C
L
H
H
H
H
HLHH
H
L
C
L
H
H
H
H
HLHL
L
H
C
L
H
L
H
H
LLHL
H
L
C
L
H
L
H
H
LHHL
L
H
C
L
LHLL
H
L
L
H
H
L
C
L
H
L
L
H
LHLH
L
H
C
L
H
H
L
H
HHLH
H
L
C
L
H
H
L
H
HLLH
L
H
C
L
H
H
H
H
HLHH
H
L
C
L
H
H
H
H
HLHL
L
H
C
L
L
X
X
X
LLLL
H
L
CLEAR REGISTERS
C
L
COUNT DOWN X4=L
H
L
L
L
LHLH
H
H
C
L
H
L
H
L
LHHH
H
L
C
L
H
L
H
L
LHHL
H
L
C
L
H
H
H
L
HHHL
H
L
C
L
H
H
H
L
HLHL
L
L
HLLL
H
L
C
L
H
H
L
L
HLLH
C
L
H
H
L
L
H
L
L
L
L
LLLH
H
L
C
L
H
L
LHLH
L
L
L
C
H
L
L
L
LHHH
L
L
H
L
H
H
C
LHHL
H
L
L
H
L
C
L
H
L
HHHL
H
L
L
H
H
H
C
HLHL
L
L
H
H
L.
C
L
H
L
HLLL
H
L
H
L
L
H
C
L
HLLH
H
L
H
L
H
C
L
COUNT DOWN X4=H
L
H
LLLH
H
L
L
H
C
L
L
L
H
LHLH
L
L
H
L
C
H
L
H
LHHH
L
H
H
C
L
LHHL
L
L
H
L
H
H
C
L
HHHL
H
L
H
H
H
H
L
C
L
L
HLHL
H
H
H
L
H
C

MonoIlthicWMemor/e.

7-55

Shaft Encoder #2
C
C
C
C
C
C
C
C

x

L
L
L
L
L
L
L
L

H
H
H
H
H
H
H
H

H.

X

H
H
L
L
L
L
H
H
X

L
L
L
L
H
H

H
H
X

H
H
H
H
H
H
H
H
X

HLLL
HLLH
LLLH
LHLH
LHHH
LHHL

.HHHL
HLHL

zzzz

H
L
H
L
H
L
H
L

Z

L
L
L
L
L
L
L
L
Z

TEST HI-Z

;------------~----------------------~-~--------------- ------------------------

; DESCRIPTION
;THIS PAL16R8 IMPLEMENTS A TWO CHANNEL SHAFT ENCODER OF THE TYPE USED IN SPEED
;CONTROLLERS AND OPTICAL DEVICES.
;THE "COUNT" OUTPUT OF THE PAL IS NORMALLY HIGH.
;OUTPUT ALTERNATES BETWEEN HIGH AND LOW.

DURING SHAFT ENCODING THIS

;INPUT "X4" SELECTS BETWEEN HALF (X4=H) OR QUARTER (X4=L) CLK FREQUENCY OF THE
;"COUNTER" OUTPUT.
;OUTPUT "UD" DETERMINES WHETHER SIGNAL PHIO LEADS (UD=H) OR LAGS (UD=L) SIGNAL
;PHI90.
;THE SHAFT ENCODER FEATURES THE CONFIGURATION AND OUTPUT POLARITY TO DRIVE AN
;74S697 TYPE UP/DOWN COUNTER.
THIS DESIGN WITH GLITCHFREE OUTPUTS WILL BE EXTREMELY USEFUL IN ELECTRICALLY
NOISY ENVIRONMENTS. THE PINNING IS GIVEN AS A FIRST PROPOSAL AND CAN BE
CHANGED ACCORDING TO THE PC-BOARD LAYOUT.

7-56

Monolithic W.emorles

Shaft Encoder #3
Title
Pattern
Revision
Author
Company
Date

SHAFT ENCODER No. 3 (WITH INTERNAL 4-BIT UP/DOWN COUNTER)
P7099
A
WILLY VOLDAN
MMI GMBH MUNICH
09/09/82

CHIP SHAFT_ENCODER_NO._3_(WITH_INTERNAL_4-BIT_UP/DOWN_COUNTER) PAL20X10
EQUATIONS
CLK PHIO PHI90 X4 /LD NC 03 02 01 DO /SSET GND

IOC DOWN S4 S3 S2 Sl Q3 Q2 Q1 QO UP VCC
IS1 :=
+

/PHIO
SSET

;CHECK FOR PHIO
;INITIALIZE Sl=L

IS2 :=
+

/Sl
SSET

;CHECK FOR Sl
;INITIALIZE S2=L

/S3 :=

/PHI90
SSET

;CHECK FOR PHI90
;INITIALIZE S3=L

/S3
SSET

;CHECK FOR S3
;INITIALIZE S4=L

+

IS4 :=
+

IDOWN :=
Sl* S2* S3*/S4* PHIO* PHI90* X4
+ /Sl*/S2*/S3* S4*/PHIO*/PHI90* X4
:+: Sl*/S2*/S3*/S4* PHIO*/PHI90
+ /Sl* S2* S3* S4*/PHIO* PHI90

PHIO
PHIO
PHIO
PHIO

IUP

:= /Sl*/S2* S3*/S4*/PHIO* PHI90
+
Sl* S2*/S3* S4* PHIO*/PHI90
:+: Sl*/S2* S3* S4* PHIO* PHI90* X4
+ /Sl*S2*/S3*/S4*/PHIO*/PHI90* X4

PHI90
PHI90
PHI90
PHI90

/QO

:=
+
:+:
+

/SSET* LD*/DO
/SSET*/LD*/QO
/SSET*/LD* UP*/DOWN
/SSET*/LD*/UP* DOWN

; LOAD DO (LSB)
;HOLD QO
; DECREMENT
; INCREMENT

IQ1

:=
+
:+:
+

/SSET* LD*/D1
/SSET*/LD*/Q1
/SSET*/LD* UP*/DOWN*/QO
/SSET*/LD*/UP* DOWN* QO

;LOAD 01
;HOLD Q1
; DECREMENT
; INCREMENT

/Q2

:=
+
:+:
+

/SSET* LD*/D2
/SSET* /LD* /Q2
/SSET*/LD* UP*/DOWN*/QO*/Ql
/SSET*/LD*/UP* DOWN*~QO* Q1

;LOAD 02
;HOLD Q2
; DECREMENT
; INCREMENT

IQ3

:=
+
:+:
+

/SSET* LD*/D3
/SSET* /LD* /Q3
/SSET*/LD* UP*/DOWN*/QO*/Q1*/Q2
/SSET*/LD*/UP* DOWN* QO* Q1* Q2

;LOAD 03 (MSB)
;HOLD Q3
; DECREMENT
; INCREMENT

LEADS
LEADS
LEADS
LEADS
LEADS
LEADS
LEADS
LEADS

PHI90
PHI90
PHI90
PHI90

-

COUNT=FREQ/2
COUNT=FREQ/2
COUNT=FREQ/4
COUNT=FREQ/4

PHIO
PHIO
PHIO
PHIO

-

COUNT=FREQ/4
COUNT=FREQ/4
COUNT=FR.EQ/2
COUNT=FREQ/2

""'-

Monolithic WMemories

7-57

&

Shaft Encoder #3
;FUNCTION TABLE FOR PALASM 1
;CLK IOC /SSET ILD X4 PHIO PHI90 Sl S2 S3 S4 UP DOWN 03 02 01 DO Q3 Q2 Q1 QO
;----CONTROLS---- INPUT
;
PHI
SSSS
I /
/
;CLK OC SSET LD X4 0 90 1234

UP DOWN

DODD QQQQ
3210 3210

COMMENTS
(Q HEX VALUE)

;-----------------------------------------------------------------------------C
INITIALIZE REGISTERS (F)
L L X X
XXXX HHHH
X X
LLLL H
H
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

7·58

L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
li
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H

X X
L L
H L
H L
H H
H H
LH
LH
L L
L L
H .L
H L
H H
H .H
LH
LH
LL
L L
H L
H L
H H
HH
LH
L H
L L
L L
H L
H L
H H
H H
LH
LH
L L
X X
L L
LH
LH
H H
H H
H L
H L
LL
L L
LH
LH
HH
HH
H L
H L
L L

XXXX
LLLL
HLLL
HHLL
HHHL
HHHH
LHHH
LLHH
LLLH
LLLL
HLLL
HHLL
HHHL
HHHH
LHHH
LLHH
LLLH
LLLL
HLLL
HHLL
HHHL
HHHH
LHHH
LLHH
LLLH
LLLL
HLLL
HHLL
HHHL
HHHH
LHHH
LLHH
LLLH
XXXX
LLLL
LLHL
LLHH
HLHH
HHHH
HHLH
HHLL
LHLL
LLLL
LLHL
LLHH
HLHH
HHHH
HHLH
HHLL
LHLL

x

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
H
H
L
H
H
H
L
H
H
H
L
H
H
H
L
H

X
H
H
L
H
H
H
L
H
H
H
L
H
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H

Monolithic

HLHL
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX·
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
LHLH
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX

HLHL
HLHL
HLHL
HLHL
HLLH
HLLH
HLLH
HLLH
HLLL
HLLL
HLLL
HLLL
LHHH
LHHH
LHHH
LHHH
LHHL
LHHL
LHLH
LHLH
LHLL
LHLL
LLHH
LLHH
LLHL
LLHL
LLLH
LLLH
LLLL
LLLL
HHHH
HHHH
HHHL
LHLH
LHLH
LHLH
LHLH
LHHL
LHHL
LHHL
LHHL
LHHH
LHHH
LHHH
LHHH
HLLL
HLLL
HLLL
HLLL
HLLH

W Memories

LOAD (A)
HOLD (A)
HOLD (A) PHIO LEADS PHI90
HOLD (A) X4=H - FREQ/4
DECREMENT (9)
HOLD (9)
HOLD (9)
HOLD (9)
DECREMENT (8)
HOLD (8)
HOLD (8)
HOLD (8)
DECREMENT (7)
HOLD (7)
HOLD (7)
HOLD (7)
DECREMENT (6)
HOLD (6) X4=H - FREQ/2
DECREMENT (5)
HOLD (5)
DECREMENT (4)
HOLD (4)
DECREMENT (3)
HOLD (3)
DECREMENT (2)
HOLD (2)
DECREMENT (1)
HOLD (1)
DECREMENT (0)
HOLD (0)
DECREMENT (F) (ROLL UNDER)
HOLD (F)
DECREMENT (E)
LOAD (5)
HOLD (5)
HOLD (5) PHI90 LEADS PHIO
HOLD (5) X4=L - FREQ/4
INCREMENT (6)
HOLD (6)
HOLD (6)
HOLD (6)
INCREMENT (7)
HOLD (7)
HOLD (7)
HOLD (7)
INCREMENT (8)
HOLD (8)
HOLD (8)
HOLD (8)
INCREMENT (9)

Shaft Encoder #3
C
C
C
C
C
C

C
C
C
C
C

C
C
C
C
C

C
C
C
C
C

C
C

L
L
L
L
L
L
L

H
H
H
H
H
H
H

H
H
H
H
H
H
H

H
H
H
H
H
H
H

L H H H
L
L
L
L
L
L
L
L
L
L

H
H
H
H
H
H
H
H
H
H

H
H
H
H
H
H
H
H
L
L

H
H
H
H
H
H
H
H
X
X

L
L
L
L

H
H
H
H

L
L
L
L

X
X
X
X

L H L
L H L
H X X

X
X
X

L L
L H
L H

HH
H H

H L
H L
LL
L L
L H
L H

HH
H H

H L
H L
L L

XX
X X
X X

XX
X X
X X

X X

LLLL
LLHL
LLHH
HLHH
HHHH
HHLH
HHLL
LHLL
LLLL

L
H
L
H
L
H
L
H
L

LLHL

H

LLHH
HLHH
HHHH
HHLH
HHLL.
LHLL

L
H
L
H
L
H
X

xxxx
xxxx x
XXXX x
xxxx x
XXXX
XXXX
XXXX

x
x
x

H
H
H
H
H
H
H
H
H
H
H
H
H

H
H
H
X
X
X

X
X

X
X
X

XXXX
XXXX

xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
XXXX
xxxx
xxxx
XXXX
XXXX

xxxx

XXXX
LLLH
LLHH
LHLH
LHHH
HLLH
HLHH
HHLH
HHHH
XXXX

HLLH
HLHL
HLHL
HLHH
HLHH
HHLL
HHLL
HHLH
HHLH
HHHL
HHHL
HHHH
HHHH
LLLL
LLLL
LLLH
LLLH
LLHH
LHLH
LHHH
HLLH
HLHH
HHLH
HHHH
ZZZZ

HOLD (9)
INCREMENT
HOLD (A)
INCREMENT
HOLD (B)
INCREMENT
HOLD (C)
INCREMENT
HOLD (D)
INCREMENT
HOLD (E)
INCREMENT
HOLD (F)
INCREMENT
HOLD (0)
INCREMENT
LOAD (1)
LOAD (3)
LOAD (5)
LOAD (7)
LOAD (9)
LOAD (B)
LOAD (D)
LOAD (F)
TEST HI-Z

X4=H - FREQ/2
(A)
(B)
(C)
(D)
(E)
(F)
(0) (ROLL OVER)
(1)

xxxx x
ZZZZ Z
Z
j-----------------------------------------------------------------------------C

x

X X
X X

; DESCRIPTION
;THIS PAL20XI0 IMPLEMENTS A TWO CHANNEL SHAFT ENCODER WITH AN INTERNAL 4-BIT
;UP/DOWN COUNTER.
;BOTH THE "UP" AND "DOWN" OUTPUTS OF THE PAL ARE NORMALLY AT HIGH.
;WHEN THE SIGNAL AT THE "PHIO" INPUT LEADS THE SIGNAL AT THE "PHI90" INPUT, THE
;"DOWN" OUTPUT ALTERNATES BETWEEN.HIGH AND LOW LEVELS AND THE COUNTER WILL COUNT
; DOWN. WHEN THE SIGNAL AT THE "PHIO" INPUT LEADS THE SIGNAL AT THE "PHI90"
; INPUT, THE "UP" OUTPUT ALTERNATES BETWEEN HIGH AND LOW LEVELS AND THE COUNTER
;WILL COUNT UP.
;INPUT "X4" SELECTS BETWEEN HALF (X4=H) OR QUARTER (X4=L) CLK FREQUENCY OF THE
;COUNTER OUTPUTS.
;THE INTERNAL 4-BIT SYNCHRONOUS. COUNTER HAS COUNT UP, COUNT DOWN CAPABILITIES.
;ALSO, THE COUNTER CAN PARALLEL LOAD AND HOLD DATA INDEPENDENTLY OF THE SHAFT
;ENCODER SECTION. THE REGISTERS ARE SYNCHRONOUSLY INITIALIZED WHEN /SSET IS HEL
;LOW.
;THE CONTROL INPUTS PROVIDE THESE OPERATIONS WHICH OCCUR SYNCHRONOUSLY AT THE
;RISING EDGE OF THE CLOCK.

MonoIithlcWMemories

7-59

Four-to-Sixteen Decoder
PAL Device Design Specification
Title

4to16 Decoder

Pattern

4-16DEC.PDS

Revision

A

Author
Company

Mehrnaz Hada

Date

1/9/85

Page: 1
9999999999 99

o

A

CHIP Oecoder PAL6L16
00 01 02 ABC D EN1 EN2 03 04 GNO 05
06 07 08 09 010 011 012 Q13 Q14' 015 veC
EQUATIONS
- /O*/C*/B*/A*
.,. /O*/C*/B* A*
- 10*/C* B1ft/A*
/O*/C* S* A*
- /0* C*/B*/A*
... /0* C*/B* A*
... /D* C* B*/A*
- /D* C* B* A*
D*/C*/B*/A*
109 '"' O*/C*/S* A*
/010'" O*/C* S*/A*
/011'" O*jC* 5* A*
/012 0* C*/B*/A*
/013 - D* C*/B* A*
/014... 0* C* 5*/A.
/015 "" 0* C* B* A*

/01
/02
/03
/04
/05
/Q6
/07
/Q8

=

=

EN1*
EN1*
ENl.
EN1*
ENl*
EN1*
EN1*
ENl'It
ENI.
ENl*
EN1*
EN1*
EN1*
ENl*
EN1*
EN1.

EN2
EN2
EN2
EN2
EN2
EN2
EN2
EN2
EN2
EN2
EN2
EN2
EN2
EN2
EN2
EN2

;Decode
iDecode
:Decode
; Decode
;Decode
:Decode
; Decode

0000
0001
0010
0011
0100
0101
0110

SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF

LHHHHHHHLH HM
HLHHHHHLHH
HHHHHHHHHH
HHLHHHLHHH
HHHJiHHHHHH
HHHHHHHHHH
HHHHHHHHHH
HHH!.RLHHHH
HHHHHHHHHH

Q9

HHHHHHHHHH HH

QI0 HHHHHHHHHH HH

011
012
Q 13
014
Q15

HHHHHHHHHH HH
HHHHHHHHHH HH
HHHHHHHHHH HH

HHHHHHHHHH HH
HHHHUfHHHH HH

;Decode 1001
;Decode 1010

iDecode 1011
; Decode 1100
iDecode 1101
iDecode 1110

XPLOT Output

;Decode 1111

Title
Pattern
Revision

4to16 Decoder
4-16DEC~PDS

A

PAL6L16
DECODER
11
0123 4567 8901

/0 /C /S /A EN1 EN2
A
B
C
0
/0
/C
/B
/EN1
EN1 /EN2
/EN1

HH
HH
HH
HH
HH
HH
HM
HH

;Decode 1000

D B C A QO 01 02 Q3 Q4 Q5 Q6 Q7 Q8 Q9 QI0
Q11 012 013 014 015

/A

U1HHHHHHLL LL

QO
Q1
02
Q3
Q4
Q5
Q6
Q7
Q8

:Decode 0111

SIMULATION
TRACE ON
-

LLLI,.HLLLLL LL
LIJiHHHHLLL LL
LLLHHHLLLL LL

B
C

Monolithic Memories, Santa Clara'. CA

/QO

Simulation Results

o -x-x -x-x
l
2
3
4
5

; set outputs to high
; Set outputs to high
;Set outputs to high

The 4 to 16 decoder, decodes four binary decoded inputs
into one of 16 mutually ,exclusive outputs, whenever the
two enable lines ENl and EN2 are hi9.h. When one or both
of the enable lines are low the outputs are: all set to
high values.

X-XX--X
-XX-XXX--X

X-X-X-X
-X-X
X-XX-X6 -X-X X-X7 X-X- -XX8 -XX- -XX9 X--X -XX10 -X-X -XXI I X-X- -X-X

X-X-

x-x-

X-XX-XX-XX-XX-XX-XX-XX-XX-XX-X-

12 X-X- X--X X-X-

U
U

-XX- X--X X-X-X-X X--X X-X-

15 X--X X--X X-X-

TOTAL FUSES BLOWN:

Logic Symbol

as

7-60

Monolithic

W Memories

96

Author
company
Date

Mehrnaz Hada
Monolithic Memories,
1/9/85

PC 1/0 Mapper
PAL Device Design Specification

Simulation Results

Title
PC I/O Mapper
Pattern MemIO.pds
Revision A

page:

Author

A G Gilbert

Company

Monolithic Memories Inc., Santa Clara,CA

Date

1/8/85

AS
A7
A6
AS
A4
A3
AEN
ICSMONOCHRHAD
jCSGAMEIOAD
/CSCOLORAO
ICSPRINTERAD
/CS5FLOPPYAO
ICSRS232AD
ICSNHIMKRG
ICSOMAPGRG
/CSPPICHIP
ICSTIMERCHIP
ICSINTCCHIP
ICSDMACCHIP

qq99999999 99

: Personal computers which are hardware compatible with the
;ubiquitous IBM PC share this 1/0 map.
CHIP PC_IO PAL8L14
Ne Ne A9 AS A7 A6 AS A4 AJ AEN jCSMONOCHRMAP GND

jCSGAMEIOAO /CSCOLORAD jCSPRINTERAD jCS5FLOPPYAD jCSFtS232AD jCSNMIMKRG
jCSDMAPGRG jCSPPICHIP jCST!MERCHIP /CSINTCCHIP jCSDMACCHIP vee

Equations
CSDMACCHIP =

/A9./A8~/A7./A6./A5

... /A4*/AEN

;DHA controller
;Chip select
;HEX address OOO-OOF

CSINTCCHIP = /A9"'jA8*JA7*/A6*A5
... jA4*/A3*/AEN

; Interupt controller
;Chip select
;HEX address 020-021

CSTIMERCHIP '" jA9*jA8*/A7*A6*jA5
... /A4*jA3·jAEN

:Timer
;chip select
;HEX address 040-043

CSPPICHIP ,. JA9*/A8*/A7liA6*AS

; Parallel peripheral interface
;Chip select
;HEX address 060-063

... jA4"/A3*/AEN
CSDMAPGRG = /A9*/A8*A7*/A6*/A5
... /A4*/A3*/AEN

; DHA page reg ister
;Chip select
;HEX address 080·083

CSNMIMKRG = /A9*/AS"'A7.jA6.A5

;NMI mask reqister
;Chip se,lect
; HEX address OAX

• jU·jAEN

1

11.9

CSRS232AD '" A9.AS"'A7.A6"'A5
... A4·AJ·/AEN

;RS 232 I\\oo.ule
;Device select
;HEX address 3FS-3FF

CS5FLOPPYAD = A9"'AS.A7"'A6.A5
• A4"'jA3*/AEN

;5.25 floppy disk module
;Device select
:HEX address 3FO-3F7

CSPRINTERAD .. Ag./AS"'/A7.A6.A5
• A4"'AJ"'/AEN

;Parallel printer module
;Device select
;HEX address 37S-37F

CSCOLORAD = A9.AS.A7.A6./AS
• M,·/AEN

;Color graphics video mocule
;Device select
;HEX addreSs 300-l0F

CSGAMEIOAD '" A9"'/AS*jA7./A6.jA5
• /A4"'/AEN

;Game I/O module
;Oevice select
;HEX address 200-20F

CSHONOCHRMAD .. A9*AS*A7./A6.A5
• A4*/AEN

;Monochrome video module
;Device select
;HEX address 3BO-3BF

SIMUlATION

HHHHHHHHHH HL
HHHHHHHHHH LH

HHHHHHHHHL HH

HHHHHHHHHH HH
HHHHHHHHIJf HH
HHHHHHHLHH HH
HHHHHHHHHH HH
HHHHHHHHHH HH

HHHIJUiHHHH HH

HHHHHHHHHH HH
HRLHHHHHHH HH
HLHHHHHHHH HH

XPLOT Output
':itle
:
Pattern
:
Revision:
At:thor
:
C01l'lpany
:
Date
:

PC 1/0 Mapper
MemIO.pds
A

A G Gilbert
Monolithic Memories Inc
1/S/85

II 1111
01.23 4567 8901 2345

o

XXXX XXXX XXXX XXXX

l -X-x -X-X -X~X ---X
2 XXXX XXXX XXXX XXXX
-X-X

3 -X-X -X-X X--X
4- -X-X -XX- -X-X
5 -x-X -XX- X--X
6 -X-X X--X -X-X
7 -X-X X--X X--X
S X-X- X-X- X-X9 X-X- X-X- X-X10 X--X -xx- X-X11 X-X- X-X- -XX12 X-X- X--X X-X13 X--X -X-X -X-:"X

TOTAL FUSES BLOWNt

TRACE ON A9 AS 1\,7 A6 AS 11,4 11.3 AEN jCSMONOCHRMl-O
jCSGAMEIOAO ICSCQLORAD jCSPRINTERAD /CSSFLOPPYAD
jCSRS232AD ICSNMfMKRG jCSDMAPGRG ICSPPICHIP
ICSTIMERCHIP jCSINTCCHIP ICSOMACCHIP
SETF AEN
SETF lAg 111.8 111.7 IA6 lAS jM 111.3 IAEN
SETF A5
SETF A6
SETF jA5 A7
SETF AS
SETF A4 jA6
SETF A9 All- A7 A6 AS 11.4 ;'.3SETF /A3
SETF 111.5
$ETF IA4 jA6 111.7 JAS
SETF 11.9 A8 A7 /M AS 11,4

XLLLLLlJiRH HH
XLLLLLLHHH LH
XLLLHHHHHH IJf
XLLHHHLHHH LL
XIJfHLHHHHL IJf
XLLLLLHHHH LH
XLLLLLLHLL LL
HLLLLLLLLL LL

-X-X
-X-X
-X-X
---X
X--X
-X-X

X--X
---X
---X
- .. -X

101

Logic Symbol
VCC
CSDMACCHIP
CSINTCCHIP
CSTIMERCHIP

CSPPiCHiP
CSDMAPG.RG
CSNMIMKRG
CSRS232AD
CS5FlOPPYAD
CSPRINTERAD

CSGAMEIOAD

Monolithic WMemories

Octal Comparator
PAL Device Design Specification
Title

octal Comparator

Pattern

octcoiiip.p_~~~~Q~~Q
9876543210
9876543210
Comment
:------------------_::.._----------------:-----------------------

; Control

:/OC eLI<

L
L
L
L
L
L
L
L
; H

C
L
C
L
C
L
C
L
X

LLLLLLLLLL
XXXXXXXXXX
HHHHHHHHHH
XXXXXXXXXX
HLHLHLHLHL
XXXXXXXXXX
LHLHLHLHLH
XXXXXXXXXX
XXXXXXXXXX

LLLLLLLLLL
LLLLLLLLLL
HHHHHHHHHH
HHHHHHHHHH
HLHLHIJiLHL
HLHLHLHLHL
LHLHLHLHUI
LHLHLHUiLH
ZZZZZZZZZZ

Load
Hold
Load
Hold
Lo_ad
Hold
Load
Hold
Test

~all

zeros
all zeros
all ones
all ones
even checkerboard
even checkerboard
odd checkerboard
odd checkerboard
HI-Z

;-----------------------------------------------------------

7=66

Monolithic

W Memo,.ies

16·Bit Barre. Shifter

PAL Device Design Specification
Title

Pattern
Revision

:&arrel Shifter

Barre17pds
A

Author
Company

Mehrnaz Hada

Date

1/1S/85

Monolithic Memorie. Inc. Santa Clara, CA

;The 16-bit barrel shifter will shift 16 bits of data
; (015-00) a number of locations into the output pins, as
:specified by the binary encoded input. A compacted
;equation can be used to specify this design. It can be
;specified as followinq:
;O[J-O •• 15] :OR[K-O •• 1S](O[ (J"K) -«J"K)/l") *16]*BIN[K, I=3 .• 0]. (I) )

;Inputs are shown by D. 51 are shift amount inputs and
:Qj are outputs. 16 product terms in each output pair
;are directed to one output; thus only 16 out of 32

;output pins are used.

CHIP Barre!Shift PAL64R32
07 06 05 04 03 02 01 DO /PLl IPSl GND eLKl

IOCl 00 NC 01 NC 02 NC Q3 HC Q4 HC Qs NC Q"
Ne Q7 He jOC2 CLK2 vee IPS2 /PL2 He He Ne
Ne He 80 81 82 83 NC Ne NC NC Ne NC Ne
/PL3 IPS) GNO CLIO /OCl He Q8 He 09 NC 010
NC 011 Ne 012 Ne 013 NC 014 NC QIS /OC4
eLK4 vec /PS4 /PL4 DIS 014 OIl 012 011 010
09 08

/52.
/82 •
/52.
/82.
82 *
52 *
52 *
82
/82 *
/82 *
/82 *
/52.
52.
52 *
52 *
52 *

/SI
/Sl
51
81
/51
/51
51
81
/81
/81
81
51
151
/Sl
81
51

01 :- /53 *
+ /$3 *
+ /S3 *
+ /S3
+ /53 *
+ /53 *
+ /53.
+ /S3
+
53 *
83 *
53
83
+
83
+
53
53
53

/82
/52
/82
/82
82
82
S2
82
/S2
/S2
/52
/52
52
S2
52
S2

*
*
*
*
*
*

/Sl
/81

*

/82
/52
/82
/82
52
82
S2
52
/82
/52
/82
/52

*

*

*

*
*
*
*
*
*

+
+

+

+
+

+

+

+
+

/53
/S3
/83
/83
/83
53
83
83
83
53

83
53
83

Q3 :- /53
+ /53
+ /53
+ /53
+ /83
+ /S3
+ /53
+ /53
53
S3
+
53
+
S3

04 : ... /S3 *
+ /S3 *
+ /S3
+ /53.
+ /53
+ /53 *
+ /53 *
+ /53 *
53 ..
53 *
+
53 *
+
53"
+
53 *
53 *
53
S3

*
*

*
*
*

*

S2
52
52
82

*
*
*

/52 ..
/52 *
/82 *
/52 *
52 *
52 *
82 *
52
/52 *
/52 *
/52
/52 *
52"
52 *
52 *
S2

*

*
*
*
*

/51
/81
51
SI

*
*
*
*

*
*
*

*
*
*
*
*
*
*

*
*

*
*
*
*
*
*
*
*

*
*
*
*
*
*
*

*

S2

S2
52
82
/S2
/52
/82
/82
82
S2
52
82
/52
/52
/52
/82

*
*
*
*
*
*
*
*

*
*
*
*
*
*
*

*
*

*
*
*
*
*
*
*
*
*
*
*
*
*
*

*
*
*
*
*
*
*

51

81
/81
/51
51
81
/51
/81
81
81
/51
/S1
81
51

*
*
*
*
*
*

*
*
*

*
*
*
*
*
*
*

*

*
*
*
*
*
*
*
*
*

*
*
*
*
*
*
*
*

ISO .'00
SO. 01
/50 • 02
SO * 03
/80 * 04
SO * OS
/50 • 06
SO * D7
/50 * 08
50 * 09
/50 * D10
80 * Dll
/80 • 012
80 * 013
ISO * D14
SO * D15

/50
50
/50
SO
/50
SO
/50
SO
/50
SO
/50
SO
/80
SO
/50
SO

*
*
*

/81 *
/81 *
51 *
51 *
/51 *
/81 *
51
51
/51
/S1 *
51
51..

*
*
*
*

Dl
D2
D3
04
05
06
07

* oa
* 09
* 010
* 011
* 012
* 013
* 014
* 015
* 00
* 02

8hi ft
Shift
Shi ft
8hift
Shi ft
Shift
Shift
Shift
Shift
Shift
Shif~

Shift
8hift
Shift
8hift

1 space
2 spaces
3 spaces
4. spaces
5 spaces
6 spaces
7 spaces
8 spaces
9 spaces
10 spaces
11 spaces
12 spaces
13 spaces
14 spaces
15 space:s

No shift
Shift 1 space
8hift 2 spaces
Shift 3 spaces
Shift 4 spaces
Shift 5 spaces
Shi it 6 spaces
8hift 7 spaces
5hift 8 spaces
Shift 9 spaces
8hift 10 spaces
Shift 11 spaces
Shift 12 spaces
shift 13 spaces
Shift 14 spaces
Shift 15, spao.es

04
05
06
07
08
09
010
011
012
013
014
015
00
01

No shift
Shift 1 space
Shift 2 spaces
Shift 3 spaces
Shift 4 spaces
Shift 5 spaces
Shift 6 spaces
Shift 7 spaces
Shift 8 spaces
Shift 9 spaces
5hi ft 10 spaces
5hift 11 apaces
Shift 12 spaces
Shift 13 spaces
Shift 14 spaces
Shift 15 spaces

ISO
50 *.1)4
ISO * 05
SO
06
ISO
01
80. 08
/80 * 09
SO
010
ISO
011
SO
012
ISO * 013
SO * 014

No shift
Shift 1 space
Shift 2 spaces
Shift 3 space.
Shift ,4 spaces
Shift 5 spaces
Shift 6 spaces
Shift 7 spaces
Shift 8 spaces
Shift 9 spaces
Shift 10 spaces
Shift 11 spaces

/SI
/80
/51
SO
81 *·/SO
51
80
/81 * /50
/81, * SO
81 * ISO
51 * SO
/81 * /8Q
/51
SO
51· * /80
81
80
/Sl • /80
/51 * SO
51
180
81 * SO

*

*
*
*
*
*
*
*

NO shift

*
*
*
*
*
*
*

D3

*
*
*
*
*
*
*'
*
* 03
*
*
*
*
*

Monolithic

/50
80
/50
SO

*

*

*

/50
SO
ISO
SO
/50
80
/50
SO
ISO
SO
ISO
SO
/50
SO
ISO
SO

06 : = /S3 ..
T
/S3"
T
/53"
T
/S3 *
T
/53 *
+ /S3 *
T
/S3 *
T
/S3"
53 ..
53 •
53 *
53 *
53 *
53"
53 *
+
53

/51 *
/51"
81 *
Sl *
/Sl *
/Sl *
51"
81"
/51 *
/Sl *
Sl *
51 *
/Sl *
/51 *
51 *
51 *

ISO
80
/50
SO
/50
SO
/50
80

*

/52 *
/52 *
/52"
/52 *
52 *
52 *
$2"
52 *
/52 ..
/52 ..
/52
/52.
52 *
52 *
52 *
52

Q7 : ... /83 *
+ /53 *
+ /83"
+ /53 *
+ /S3 *
... /53 *
+ /53 *
+ /S3
+
53"
83 ..
+
53. •
+
53 *
+
83"
83 *
53 *
53 *

/92 *
/52 *
/52.
/52 *
S2"
82
52"
S2 *
/82 *
/52
/82
/S2 *
82
S2.
S2 *
52

/Sl
/51

*

/50
SO

*

*

*

*
*
*
*

*

*

ISO

SO
/50
SO
/50
SO
/50
SO

S I . /50

81
/81
/Sl
Sl
51
/51
/81
51
51
/51
/Sl
51
51

*
*

*
*
*

*
*
*

*
*
*
*
*
*
*
*

ISO
SO

*

*
*
*
*
*
*

*

*
*

/82
/52
/52
182
52
82
S2

*
*
*
*
*
*

*

W Memories

*

/Sl
/51
51
Sl
/51
/51
51

*

*
*
*
*
*

04

spaces
spaces
spaces
spaces

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*

05
06
01
08
09
010
011
012
013
014
015
DO
01
02
03
04

No shift
Shift 1 space
Shift 2 spaces
Shift 3 spaces
Shift 4 space.
Shift 5 spaces
Shift 6 spaces
Shift 7 spaces
Shift 8 spaces
Shift 9 spaces
Shift 10 spaces
8hift 11 spaces
Shift 12 spaces
8hift 13 spaces
Shift 14 spaces
Shift 15 spaces

06
07
08
09
010
Dl1
012
013
014
015
00

No shift
Shift 1 space
Shift 2 spaces
Shift 3 spaces
Shift 4 spaces
Shift 5 spaces
5hi ft 6 spaces
5hi ft 7 spaces
Shift 8 spaces
Shift 9 spaces
Shift 10 spaces
Shift 11 spaces
Shift 12 sPaces
Shift 13 spaces
Shift 14 spaces
Shift 15 spaces

OS

*
*
*
*
*
* tn

*
*
*
*
*
*
*

*
*

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*

*
*
*
*
*

D2
03
04
05
07
D8

09

010
011
012;
013
014
DIS
DO

01
02;
03

1)4

05
06
08
D9

010
011
012
013
014
Ol5
00
01
D2
03
04
05
06
07
09
010

* ISO * 011
SO
/50
SO
ISO

12
13
14
15

No shift
Shi ft 1 space
Shift 2 spaces
Shift 3 spac••
Shift 4 spaces
Shift 5 spaces
8hift 6 spaces
Shift 7 spaces
Shift 8 spaces
5hi ft 9 space.
8hift 10 spaces
Shift 11 spaces
Shift 12 spaces
Shift 13 spaces
Shift 14 spaces
Shift 15 spaces

*
*
*

Q9 : - /S3 *
+ /53 *
+ /53 *
+ /53 *
+ /53
+ /53.
... /S3

*
*
*
*
*

*

Shift
Shift
Shift
Shift

06
07
08
09
010
011
012
013
014
015
00
01
02
D3

*

ISO
SO
/80
SO
/50
SO
ISO
SO
/50
SO
/50
SO
/50
SO
/50
SO

*
*
*

015
00
01
02

*
*
*

80 *
ISO *
80"
/50
SO *
/50 *
SO *
ISO
SO
/50
SO *
/50 *
SO *

08 : - /53
/52 * /Sl
+ /5'3 * /82
/51
+ /53 * /52
51
/53 * /82
51
/S3 * 52 * /Sl
+ /S3 *' 82 * /51
+ /83
82 * 51
+ /S3
S2
51
+
53
/52 * /81
+
83 * /52 .. /51 *
+
53 * /82
51 *
+
93 * /52
91"
+
53 * 82
/S1 *
53 * 52
/51 *
53
52
81 *
53 * 52
Sl

*
*
*

*
*
*
*

*

QS : .. /53
/52
/51 *
+ /83 * /52
/Sl *
+ /53 * /52 * Sl *
+ /53
/S2 * Sl
+ /53 * 52 * /51 ..
+ /53 * 52 * /51 *
+ /53 * 52 * 51 *
/53 * 5;2 * 51 *
83 * /52 * /Sl *
53
/52 * /51 *
53 .. /52 * 51 *
s3 * /82" Sl"
S3 * 52 * /81 *
83 * 82 * /51 *
83 * 52 * 51 *
53" S2" 51 *

*

*

/Sl * /50
/51 * SO.
51
/50
81
SO
/51 .. /50
/51 * SO *
81 * /50 *
51 * SO *
/51 * ISO *
/51 * SO *
51
/50 *
51 * 50 *
/Sl * /80 *
/51 * 50 *
51 * ISO *
51 * SO *

*

*

+

.3 *
.3
.3
.3 *

*

EQUATION5
00 := /53
+ /83.
+ /83.
+ /83.
+ /53.
/83.
/83
+ 183.
83 *
53 *
83 •
S3 *
53 *
53 *
53 *
53 *

02 : - /83
+ /83
+ /83

.

012
013
014
DIS

No shift
Shift 1 space
Shift 2 spaces
Shift 3 spaces
Shi ft 4 spaces
Shift 5 spaces
Shift 6 spaces
Shift 7 spaces
Shift 8 spaces
5hi ft 9 spaces
Shift 10 spaces
Shift 11 spaces
Shift 12 spaces
Shift '13 _paces
Shift 14 spaces
Shift 15 spaces

No shift
Shift 1 space
Shift 2 space~
Shift 3 spaces
Shi ft 4 spaces
Shift 5 spaces
Shift 6 spacas
Shift 7 spaces
Shift 8 spaces
Shift 9 spaces
Shift 10 spaces
Shift 11 spaces
Shift 1-2 spaces
$hift 13 spaces
Shi ft 14 spaces
Shift 15 spaces
No shift
Shift 1 space
8hift 2 spac••
Shift 3 spac••
Shift 4. spac••
Shift 5 space.
Shift 6 spaces

7-67

16·Bit Barrele Shifter
+ /S3. S2* 81* SO*DO
+ 83" /82 .- /81. * /80 .. Dl
+
+

+
+

+

.+
+

*

83'
/82. 81" 80 * 04
83" -S2 ~ fSl
ISO
~5
83 * 'S2 • /81.'" so
D6
83
S2" 81
180 .• 07
83::." S2
~l * so. 1)8

*

*
*

*

010 '-/U • /S2 '0 181 *
+ /83, * /82 ~ 181 *
+ /S3 * 182 * 81 *
+ /93' * 182'. 'Sl *
+ IS3 '. 82' /81*
+ IS3 * S2 */81 *
+ /S3' * S2" 81 *
+ ISl'·. ,S2 ,* 'Sl ,ff
+ s:r· ." /82 iii! /Sl •
+
93' * /82 .. /81 *

+
+

+.

+
+
+

Shift
Shift
Shift
s:hitt

83" /S2 ~ /Sl" SO"})2
83 *,82*; 81 */80 *'D3

ISO * 'Olq
80 * ,011
ISO *012
SO'])13
ISO. D14
80 * 015
/SQ, .. DO
SO" bl
ISO .. "02'

80' 03

'*

*.,

*

D4

."D.'os"
07

* 1)8

*

'1)9

Oll ,-/S3 "/82 * ./Sl • /80 * 01~
+ /S3
IS2 '. ISl
SO' D12

+
+

!

+

+
+

+
+
+
+
+
+

+

*
/83" "/82 ~
/S3 '*- 182"

*
81" ISO
81.

*

SO

.. .013
* D14,

,:':' :~ :: ~:~ : /:~ : ,~5
IS3 t:. S2 *."Sl" ISO ·',01
/S3' *: S2
. $1 * SO * D2
83 *, /82
1S1 .. ISO .. 1)3
*, /82 * 181" SO .. D4
~:~

~

>

11!:

~3

83 .*./S2
83.* /S2
83" S2

8) -8).
8) 11!:

*

*'
*,

*

81" ISO
,05
81 *, SO * DS
ISl • /80 • D7

82. /81. 80. '08
S2. 81 * /80 * os
52
81 * 80 * 010

*

012 : .)S) * /S2 .. lSl * ISO * 'D12'
+ IS3
IS2
ISl * SO
D13
+ IS)' /S2" Sl * ISO * D,14
+ IS3 *-/82 * Sl * .so * D15
+ /S3 * S2 * /81 * ISO * DO
+ 183* S2*/81* 80*01
+ /S3 * $2" 91 * ISO * D2
+ /S3*- 82*_81* 80*03
+
83
/S2 .. /Sl * ISO
D4
+
$) * 182 * /81 * SO * .05
+
S3
IS2,~
81
/80 • 1)6
+
8,3 * /82 * 81 * SO * ~7
+ $3* S2*/Sl*/SO*08
+ 83, * 82 * /Sl -* SO * D9
+ 83 *, S2 * Sl * ISO • 010
+ 8) *" S2 *, Sl * SO * 011

*

*

*

*'

*

*

*

Q13 '-/S3 '*. /S2
+ IS3 * /82
+ 183 * '/S2
+ 183 • 182
+ 183 * 82
+ 183 '" S2
+ IS3 '. S2
+ /S3 * S2
+
83' * IS2
+
83 • IS2
+
83 • /82
+
83 * /S2
+
* 'S2
+
83 * S2
83 * S2
+
+
S3 * 82

S,

* /Sl .* ISO' * D13
* 181 * SO * 014
* 81 * 180 * 01.5
81 * SO"; DO
.. /Sl * ISO *. 01
* /Sl * SO • D2
81*/80*03
* 81 * SO • b4
• /S.l * /80 • D5
'-'/Sl'* SO * 06
81*/80*07
* 81 * 80 * D8
/Sl .,. /80 * D9
ISl • ·SO * 010
* Sl * ISO • Oll
Sl * SO * D12

·
"
·
·
,*
*

014 ,'-/S3 • IS2 •
+ IS3. /S2 *
+ IS3. /82 *
+ IS) ·/52
+ 1$3
82 *
+ /S) * 82
+ /S3
82 *
+ ,S3. 82
+
83 * /82 *
+
83
182 *
+ 53 *. /82 *
+ 83 * /S2
+ $3' * S2 *
+ 83 * 82 *
+ $3* 82*
+
S3 * S2.

*
*
*

*
*
*

*

*

015 ,-/S3 *
+ 183 *
+ ,tl3 *
+ /83'*

7-68

ISl * 180 * 014
/81 * 80 * 015
Sl * /80 • DO
81 * SO * D1
/Sl • ISO * D2
/Sl * 80. D3
81
ISO * D4
81 * 80
D5
/81 * ISO * D6
/Sl
80 * 07
81
ISO * D8
81
SO * 09
/81 * ISO * 010
/81 * 80 * 011
81*/80*012
Sl * SO * 013

*

*

*
*
*

/82 * ISl * ISO * 015
182 * /Sl * SO * 00
/S2 * Sl * ISO
oi
/82 * 51 * SO * 02

*

?- spac••
10 spaCes
11 spac.s

Shift 12 spac••
Shift 13 .pic••
Shift. 14 .p~c.s
S~ift ,l!;ii s-paces

*

-83'" /82 *. ~l * ISO *
83
/82
81
SO.
83. S2 * lS,l • ISO
83"" S2 * ISl '. so.
83 * 82
81. ISO
83. S2" 81
SO *

*

Shi~t

*

+
+
+
+
+
+
'+
+

7 spac.s

8 spac••

; No shi(t
; Shift 1. sPac.
t ~bift 2 space.
Sbit.t 3, spac••
Shift 4 spa.,..
Shift -5 spaa.;.
Shift ,6 apaces
8hift 7 spaces
Shift 8, spao.s
,Shift 9.spaces
Shift 10 Sl?aqes
Shift 11 spaces
~hift 12 space.
Shift 13 spaces
Shift ~4 spac,es
Shift 15 spaces
No 'shift
; Shift 1 apace
Shift 2. apace.
: lIhift ) apao..
: Shift " apaCes
; Shift 5 apaces
; Shi~t 6 ...pac.s
~ Shi'f.t 7 apac••
I ,Shift 8 spac••
Shift 9 spac:••
,~ Shift 10 spaces
Shift 1.1 IR>SCes
s:hitt 1:2 apaces
Shi ft 13 spac••
, Shift ;14 spac••
Sh,ift 1~ .pac~.
1

No shift
Sh:ift ,1 space

spac ••
Shift 3 space.•

I Shift 2,
~p.itt

4" spac~
Shift 5 spaces

Shift 6 apac._

Shift 7. ,space.
Shift 8 .pac••
Shift ,9 spac••
Shift 10 apaces
~hif,t 11 ~c;:es
.: Shift 12 spac••
shift 13 spac••
Shift 14 spac_.
~hi~t '15 sp.ces
No shift
Shift 1. spade'
Shift 2, space.
; ,Sl1ift 3 .pac~ •
Shift " .pa~s
'Shift, s: spa<;es
8hift 6 apace.
~J1ift ,7

apaces

Shift 8 spaces
; Shift? space"
; I!hUt io apac.• s
; Shift ~l space.
12 space.
.' Shitt
Shift'13 .pac••
: Shift 14 spaces
Shift 15 ~pac~s
,No shit";

Shift', 1. spaCe
Shi~t '2

:~f~:!

apaces

3::

8hi.tt 5' spaC••
Shi~t , .pac~.
Shift
Shift
Shift
Shift
: Shift
'; Shift
;. Shift
" Shift
Shift

7 ap,a~'8

B:

.pac~.a

9' spac••

10 .~c:es
11 8~C.S
12 8~ces
'13 apac.s
1,4 spac••
~'5 .pa~8

No 8hift
8hift ~ 'spac" ,
Bhift'2 spac••
Shi~t . 3 .pac~.

..

+
+

/S3
153
153
183
83
53
53
93
83
S3
S3
S3

··•
*

,,82,) * /Sl' ~ ISO.
82 *,; l81 .. 'SO

*. 1)3

~,"D4'

52 * Sl*/SO*05
52 * Sl * 80 * D6
* /82 * /Sl * /80 * 07
* /82 * /Sl * 80 * D8
* -182.- S1.* /~(J, * D9
* 182 * Sl * 80 * Dl0
S2 * /Sl * I~O * Dl1
• S2 * /81 * 80 • D12
* 82 •. 81 • ISO * 013
','S2'
* 81 * J~o * Dl'
*

'., ., . Shitt;,,4' ,a"~. :
" ;' Shift's "lIpae.. "
; .,.Shltt·,.,6A'paC••
I Shift:.7 .pace. ,
, 8hift 8 spa...s
Shift,? space.

,,

·

"

:tifi~':=~::

,

Shift· 1.2, ,'.pac.s .
Shif1; 1~ .•paces
"hi~t, '14

Shl~~

apace.

15 !.pac.~_

SIIIULATION

TRACE_ON;~\~~;L;~~/~1 ~i~~ ~!~;'
92 81 50 00 ,01 02 D3' D4' D5 D6 07 DB'
010 Oll 012 013 01' 015
01 02
gi.~~~~5
06
08 Q9 010 Oll 012 013
D9

QO

Q7

5ETF eCl OC2 OC3 ce. IPSl IPS2 /P53 IPS"
IPLl IP1,2 11'1,3 IPL4 IS3 /S2 151 ISO DO
101 102 103 /04 105 I~ /07 IDS 109 ID10
IOll·/D12 1013 1014 1015
'
CLOCRF ,CIJ(l CIJ(2 c1.K3, 'CIJ(4

I Clock

8ETF /S3 1$2 /Sl SO ,
CLDClCF CIJ(l CIJ(Z CLlC3 CIJ(4

, ;Shiftl

SETF IS3 /S2 Sl 180'
CLOCKF eLK1 CLJ(2 eLK3 eLK'

;Shift 2

SETF IS3 IS2 81 SO
CLDCKF CIJ(l CIJ(2 CIJ(3 CIJ('

;Shift 3

SETF /53 S2' /81 /S.O'
CLOCKF CIJ(l CIJ(2. CIJ(~ CIJ('

,"Sltift ,4'

SETF 15l S2 151 SO
,
CLOCRF, .CIJ(l CLR2,. CIJ(3 CIJ(4

:8hitt 5

SETF IS3 52 S.l ISO
CLDcn CIJ(l C;LR2 CIJ(3 CIJ('

';shitt 6

~~~K~~~~ ~k~OCIJ(1

,Shift 7
CIJ(4

SETF 53' /S2 /51 ISO
CLDClC~ CIJ(l CIJ(2 CLK3 CLK4

;Shift 8

;The 16-bit barrel 8h1fter will ,shift U bita of data
; (015-00) a nWllber of locations into the output pins, es
,specifiacLby the binary encoded·input. A compact~
;equation :can be u.~ to specify· this desiqn. It ,can ba
,apacUied ali followinq'
'

,

;0[J-o-".15] ,. , '
; eR[I~..o •• lS.] tD[(J+lC)-( (J+it)/16)'U]*IIIN[K,I=3 •• 0]S(I) )
; Inputs ara iilhewn: by o. sf are Iohiftaloount input" arid
'OJ acre ,output•• 16 product terms ill each output pair
;are 4i,rected to one output, thua only 16 out of' 32
loutput 'pl.na a-re ulled.
'

Simu••Uon ......Its

i6-Bit Addressable Register

PAL Device Design Specification
TITLE

16-BIT ADDRESSABLE REGISTER

'A'!'TERN
REVISION
AUTHOR
COKPJINY
IlATE

ADREG-16.PDS

+

A

John Bir)cner
Monolithic Heaori •• Inc. Santa Clara, CA
2/11/85
The l6-bit addre••able ragiater loads one of 16 registers
••leeted. by ADDR[O •• 31 with data input, DATA.

CHIP ADREG16 PAL32R16
QO Q1 02 QJ /El ~c Ne AD Al vee A2 A3 DATA Ne jPRL02 CLK2
04 Q5 Q6 Q7 Q8 Q9 Q10 all /E2 Ne Ne Ne Ne GNT) Ne Ne Ne Ne /PRLDl eLKI

012 013

au

015

Q15

+

0.2

. A3*QO
:- lAO

+

*01

A!

A2

*01
*01

A3*tll
AO*/Al*/A2*/A3*DATA

AO
/A!
A2

*02
*02
*02
1.3*02

+ 11.0* Al*/A2*/A3*DATA
OJ

:- lAO

+

/A!
A2

*OJ
*OJ
*OJ

A3*tl3
AO* Al*/A2*/A3*DATA
AO

O'

*Q'

Al
/A2

+
O'

Al
/A2

.
+

07

00

O'

/A!

/A2

AO. Al. A2* A3-DATA
SIMOLATION

TRACE ON go Q1 Q2 Q3 04 05 Q6 Q7 as Q9 QID all 012 Q13 QU Q15
AD 11.1 A2 11.3 DATA

SETF 11 12 /DATA jPRLpl /PltLD2

/Al
/A2

;- lAO
A!

A2

*07
*07
*Q7

AO

:- lAO

+

*010
IA3*QIO

*Qll
/Al
A2

*011
*QU

IA3*Ol1
1.0* AH/A2* A3.CATA

012

AO

*012
*012
*012
/A3-012
IAO*/Al* A2* A3-DATA

A!

+
+
Qll

014

/0.2

SETF lAO IAI /A2
CLOcn CLl(1 CI.K2

A3

l"hold
;hold
:hold
:hold.
;load

SETF AD IA1 11.2
CLOCKF CLXI CLX2

1.3

SETF lAO Al IA2
CLOCKF CLKI CLK2·

A3

SETF AD Al IA2
CLOCKF CLRI CLX2

A3

SETP lAO IAI

A2
CLOCKF eLKI CLK2

A3

SET>'

AO IA1 1.2
CLOCKF CLKl CLJ(2

Al

SETF lAO A! A>
CLOCKF" eLKI CLK2

AJ

SETF AO A! 102
Cx..oCKF CLK1 CLlt2

Al

SEU lAO

SET!" lAO IAl A2 IA)
CLOClCF CtJ(1 CLK2
AD IAI A2 IA)
CLOclCF ctJ(l, CLlt2

SETF lAO Al A2 IA)
CLOClCF CtJ(l CIJ(2

;hold
;hold
;hold
;held
; load
;hold
;hold.
;hold
;hold
; load

AO

Al

A2 IA)

cLoCK!' eLKI CLK2

;hold
:hold
;hold
;hold
; load

;hold
;hold
;hold
:hold
; load

Al /A2 /A3

CLOCK!' CLXl CLJ:2

SETF DATA
SETF lAO IAI /A2 IA3
CLOcKF CLKI CLlU

Simulation Results
Page:

1

04.

cj 9 cqcqcq
XXXXLLLLLL
XXXXXXLLLL
XXXXXXXXLL
XJCXXXXXXXX
XXXXXXXXXX

Q5
Q6
Q7

xxxxxxxxxx xxxxLLLl.LL LLLLLLLLLL t.LLLLLL
XXXXXXJOtXX- XXXXXXLLLL I.LI.LLLLLLI. LLt.LLLL
XXXXXXXXXX XXXXXXXXLL LLLLLLLLLL LLLLLLL

QO
Q1
02
03

Cqcgcgcqcq cgcgcgcgC9' cgcgcgc

LLLLLLLLLL
LLLLI.I..LLLL
LLU.LLLLLL
LLU.LLLLLL
XXLLLLLLLL

LLLLLLLLIJ., LULLLH
LLLLLLLLLL LLt.LLLL

I.LLI.LLLLI.L t.LLLL+J..

I.LI.LLLLLLI. LLLLLLL
LLLLLLLLLL LLLLLLL

1J9

XXXXXXXXXX XXXXXXXXXX LLLLLLLLLL LI.LI.LLL
XXXXXXXXXlC XXXXXXXXXX XXLLLLLLLL LLLLLLL

g10

XXXXXXXXXX:axxxxxxxx

Q8

XXXXt.LLLI.L LLLLLLL

xxxxxxr..u;

*013
Al
*013
/102
*013
/A3*<113
AO*/AI* 1.2* A3*DATA

:hold
;hold
;hold
;hold
; load

Q11

XXXXXXXXXX XXXXXXXXXX

012
013

XXXXXXXXXX XXXXXXXXXX XXXXXXXXLL LLLLLLL
xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx LI..LLU.I.

014

XXXXXXXXXX XXXXXXXXXX lOCXXXXXXXX XXLLLLL

XXXXXXXXXX XXXXXXXXXX xxxxxxxxxx XXXXI.LL
XXLUJml.LH HLLHHLLHHL LHHLLHHIJJl HLtKHLL

AO

Ihold.
:hold
;hold

Q15
1.0
A!

IW

XXLLLLL!!\!II BI.I.W!JIHJIL ~ LHJIHHLL
XXLLLLLLLL L!IHHHIDIHHL LI...LLI...LUDI IUUfHHLL

A3

XXt.t..Lt.LLLL LLLLLLI.LLH HHHIIBHHHHH HHHHHLL

:-/AO

+
+

SETF

;hold.
;hold.
;hold
;hold
;load

+ IAO* A1*/A2* A3*DATA
011

:hold
;hold
:hold
;hold
l"loacl

*09
*00
*0·

"'OlD
0.2

SETF

; hold
;hold
;hold
;hold
; load.

·010

IAl

;hold
;hold
;hold
;hold
; load

*00

/A3*09
AO·/Al*/A2* A3*t)ATA

010

SETF AD Al /A2 jAl
CLOCKF CUl CLK2

;hold
;hold
;hold
;hold
;load

+
A!
*08
A2
+
'OS
IA3*Q8
+
+ IAO*/Al*/A.2* A3*DATA
+

:hold
:hold
:hold
;hold
;load

*00
*00
*00

A3"'Q7
AO. A1* A2*/A3*DATA

AO

SET!" AD IAl /A2 fA3
CLOClCP eLKl CLK2

*Q'
*0'
*0'

A3*Q6
lAO. AI. A2./A3*CATA

:- lAO

+
+

;hold
;11014
;hol.d
;10.4

*015
/A3*Q15

:hold
;hold
;hold
;hold
;load

;hold
;hold
1hold
1hold.
; load.

A3*QS
AO*/Al* A2./A3.CATA

0.0

00

*0'
*0'

A3-04
11.0*/1.1* A2*/A3*DATA

:- lAO
+

+
+

;hold

*015

CLOCK!" eLKl CLK2

*00
*00
*00

+ IAO* IAI* IA2* IA3 *DATA

02

:ho!d
;10&4

*015

SET!" lAO IA.l /A2 /A3

0.0
Al

01

/A1
/A2

EQUATIONS

00

/A3*Q14
/11.0* A1* A2* A3-DATA

:- lAO

/A!

IA>

*014*ou
*Ou

DATA LLLI..LLI.LLL

Monollthlt: WMemorieS

LLI.LLI.t.LI.I.

IiLLLLLL

LLLLLLLLLL LLLLLHH

7-69

16..Bi~'Addre...ble Register

XPLOT Output
9 ...._ ............ ----X- ------... ----...--... __.......... _...................- -_ ........- -X--.7 -----............. - -..X............- - --...- ..--- ---...---...... - ...- ...- ...- .---...............--:..

PA1ASII XPLO'l', V2. 0' .. BlTA RELEASE
(C) .. COPYRIGII"l' KOJILI'1'HIC IIEIIOllIES IRC.; 198'

;!:~:rn
aevi.loa

.8
9,
100
101
102
103
104
105
10.
107
108
10'

: ~i,~·~l. h91.ur
I

A

Author
Coapany

: John Birkner
I Nonal1thic"x.orl. . me

Date

: 2/.1,1/15

......,.

'ALU1U'

111111 11112222 22222233 3333333.3 oUt ... "", 44555555 55556
01234567 "012345 57110123 45678.0-1 23.56789 01234567 '90123'5 "890

o -------- .......................... ----- -------- -------- -------- -------- -x---

1 ---............ -------- -------- ----_____ ------.- ""'------- ..............-- ____ _

2
X------- ..........---- ------.-- -------- -------- ----.. --- . .------- ----3 ----x. . . . ------- ------- -------- . _------ -------- -------- -----

.. -x---x-- x........._-- -------- -------- -------- ----...-.........-... ----

5 XXXXXXXX XXXXXXXX xxxxxxxx XXXXXXXX XXXXXXXX
XXXXXXXX Xxxxxxxx XXXXXXXX XXXXlClQCX XXDXXXX
XXXXXXXX
8 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXDXX
9 XXXXXXXX XXXXXDX XXXXXXXX XXXXXXXX XXXXXXXX
10 XXXXXXXX XXXXXXXX XXXXXlCXX XXXXXXXX XXXXXXXX
11 -X---X"'12
13
14 -------- -----.. _- - .. - ...... _- -------- ------15 -------- --......... -- ...... ----- -----__ ------,

7 XXXXXXXX xxXXXXXX xxxxxxxx XXXxxxxx

xxxxxXu:

X--"'X
XXXXXXXX XXXXX

xxxxxxxx XXXXXXXX XXXXX

XXXXXXXX
XXDXXXX
xxkxxxxX
XXXXXXXX

XX)CXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX

XXXXX
XXXXX
XXXXX
XXXXX

-------- -..--..--- '..... -----.. ------.. . . ----..:--- -X--I
-"'--X--- X---------------.. . . . - -----..
-.. . -.......--- --------------:... ---------X-X-------------- -------.................................
-~------ '--x---.------ -------- --x--

16 ---..................-----17 -------- -------18 X........- ..-- ---..---1........-X--- -----..-20 ...X.........X.... X-----......
21 XXXXXXXX XXXXXXXX
22 xxxxxxxx
23 XXXXXXXX XXXXXXXX
24 XXXXXXXX XXXXXXXX
25 XXXXXXXX XXXXXXXX
26 XXXXXXXX XXXXXXXX
27 -X......-X-... X.... -----

xxxxxxxx

~-------

-------- - - -..... ------...----...- ...XXXXXXXX
xxxxxxxx
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
----.....--

----__ ,...'-

~-------

x-x--

---X- -X-----"X

--------, -------- .. --... -~-- -----... x-------- ----..--- ...-----...-, ~,- ..
-------- ..-------. - ...------ ------x---...- ..-- .....---...- .. -----...-- - ...----X--...........-- - ..... --'~ ...... --.... - .................---XXXXXXXlC XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX"XXXXXXXX
XXXXXXXX XXXXXXXX XXXXDXX xxxxxxxx
XXXXXXXX XXXXXXXX XXXXXXXX xxxxxxxx
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX xxxxxxxx xxxxxxxx. XXXXXXXX
--.....---- - ..... --.................- .... -- --------

-----

x---xxxxx
-----

XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
-X---

2. ----X---.. -..
---- -----...........--.. . .--- . . .---.. . .- -----..
- -:...X----X-.. ----.........
-----...............................................................
-----.........
-X----- ----------X------X----- ----x
X---32 ..- ..... - ........ ----...--- - ...--....-- -----.....- --..- .. --- ------X- -..----.. - -x--33 ---... ---- -------- .........----... -------- -------- - .. --...... X- --...---...- ----34 ... X--..-....... -.. ----- . . . .---- -.. ------ ---.. ---- ------X..... --.. . . .-- ----35 - ... -;.-X...... ---......--- - .........---- ...-----......
... - ...-----X- ..::----...-- -----

..X----""'-"X--'"
X......... X-...
XXXXXXXX
XXXXXXXX
XXXXXXXX

:xxxxxxxx

XXXXXXD
XXXXXXD
X..--...X.........-X..- ..
-X----..~10 --.................
111 ---......- ...-

112
113
114
115
116
117
111
119
120
121
122
123
124
125
12'
127

..---......X- ... - ......... - .........................------ ---..........;..........~-- ...-"'---"'-X'" --...- - - -----....................- ... - ...... - ...- ......----...-X---"'-"'- --..- ............ --_..................- - ...----:...... -:------XXXXXXXX XXXXXXXX XXXXXXXX XXXUXXX
XXXXXXXX xxxxxxxx: XXXXXXXX UXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XlCXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXlOOOOCX XXXXXXD ·XXXXXXXX
XXXXXXXX XXXXXXXX.XXXXXXXX XXXXXXXX XXXXXXXX xxxXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
X---............. --......- ...- ......----- - ........- ...- .................-- .....................
--X"-"'-'" ---...--...- ......- ...- - - ...-_ ..................- ......'" ....,...............-X.. --........ --............- --..... _-... ,......................- ...- ....-- - ..- ..--...- ...x.. _-...... ---...---..............--~ '..- .......-...- -.........----. -..................
- ... X...---- -----...-- --............... -----..............- ...- ...- -.-........... - ...

xxxxxxxx xxxxxxxx
XXXXXXXX xxxxxxxx

----...
.....--X-...-JC
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
-X-"X
....-----.. -

---.. -

X---..

.............. X................-- - ..------ - - -......-

- ...------ ----...- ..... ----.....-

-X"'-'"

-X"'---X'"
"'-"'-X"'X'"
X..- ......X......
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
X-..- ... X--

- ............--- -----...- ............ "'---............- ......------ ---------.. - ......- ......------' ......- .............
XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXX:XXXX
XXXXXXXX XXXXXXD XXXXXXXX
XXXXXXXX XXXXXXXX XXXXDXX
XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX
---.....................--..- - - .....- ...- ...

..-_....
--.. _X.........
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
-X-"-

------X- ------- --...-..--- ----- -----...-... -...---....- ...----...-- ........-X
.......--...-- ----..... - ..............- ........---...- ......- .............'" - ..- ..---X..........- ...... --..- ....................-....
XXxxxx:xx nxxxx:xX XXXXDXX
XXXXXXXX ~ xxx:x:x:xxx
XXXDXXX X:lJCOPD(X
DXXXXXX XXXXXXXx XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX XXXXXXXX
X-......--.........-~ ......- .......................

x:xxxxxxx

xxxxxxx:x

-"X-X"'-- ... __..---......- ...--...-- -----...- ........ ---.............--...... -- ..- ..- .... - ... -----XX--"'
-- ....-.. ---- -.. ---.. . . . -.. . --_..- -------.........--.. . -- ----.. . -.. ----x
-----

--X----- -------- --.....---- ------... - -..------ -------- ----.....-...

--X-"'--" - - - -......- - ..- - - -... - .. --.........- ...----...-- ... ---... - .........---......... - X----

OUTPUT PIKS:
111222223334
1234,,,012347810
POlARITY' roSE; ....--......--......- ...--...-

OUTPUT

IAHlCr

rWSH :roSE I
TOTAL roSES 8L011D1:

4-40
X

17-24
X

5008

29
30 ............---- ......--.............-----...- ---...--..- -------- ----...--31 .....................----..-- -----...- ----......- ... ------...- --------

~-

3'
!~

41
42
43
44
45
46
47
41
4'
!l0
51
!l2
!l3
54
55
56
57
51
5'
60
61

::= ::=

==

QO

---~

36 X---X"-- X----...-- --............... - - .........---- ...---...--- -------- _ .....---...- X---X
37 XXXXXXXX XXXXXXXX :xxxxxxxx XXXXXXXX xxxxxxxx XXXXXXXX xxxxxxxx XXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXltXXXXX xxxxx

=~: ~=~~ ~~:r:rx~~ ~~~

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX.XXXX xxxxx
XXXXXXXX XXlCXXXXX ZXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXX
X---X--- X------- -------........----...... ----~-..... -------- ...--...---- -X--X
- ...

---X.....
.----...........
--X""--.-------X---.
. -.. -..
---.---.................
. --.. - . .---.. ----- .--..
---.. - -.--.
. --.. ---. --- .....
X----- .-----.
. -- --------- ... ---.......... ----......-- ......------ --.....---- .....- .........-- ...-X----- 00:----..... - -------.. - ......... - ..........................- .. - - - -------- ---....... -- ...... X----- .:.-.. ----- X----

------X- -...--.. --- ----........- -X---

...--.. - ......- -----.. - ... --... - ......- ...- ..------------ -------- ----...--... - ............--- .......- ...-X- - ..- ..... - ...... -------- ----X

01
02
03

-X---.
. . . . -------.. -.. . ----- --.. ----- ---.. --x- ..------- .....--...... -- ----...
- ... ---X-......- ... - ...--- - .....----................. -- - - -......X- -_...- ..- .... - .. ---......- --.....-

NC

X---X"'-"
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXIXXX
XXXXXXXX
XXXXXXXX
X---x.........
..
..

NC

X...---.........
XXXXXXXX
XXXXXDX
XXXXXXXX
XXXXXXXX
xxxxxxxx
XXXXXXXX
X...--...---

--...- ......XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXDXXX

-------XXXXXXXX
XXXXXXlQC
XXXXXXXX
XXXXXXXX
XXXXXXXX
xxxxxxxx: XXXXXXXZ
............---- ... _--..- ......

xxxxxxxx

......--..... -- --......---xxxxxXxx XXXXXXXX
XXXXXlCXX XXXXXXXX
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
XXXlCXXlCC XXXXXXXX
XXXXXXXX XXXXXXXX
---......--- .........--...-

---X............
. . . .. .-..--.............
--- --X----X-----. . . ---.
--..-.. ....-. -.---.
. -- --.....................
X---.....
.2 .._-..--- -------......---.. -- . . -.. -.. -.. - --X-"-63 .........----- ..... ----......... ---- - ...- ........- -X-----

------.....
XXXXXlPCX
'XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
----........-

X---XXUX
xxxxx
XXXXX
XXXU
XXXIX
XXXXX
-X-"'-

--.
.. ----.
---.. ....-....-.. .--..-- -.-.----..
-..----. ------------X
.----.
.----....- ..--.. -.--..
. -- X----

." ------......---......-- ------..- ------X'" ..- -...---'.'...... _-.......... - ......---..... ~X.. -65 .. -----.........---........- ---.................- ..- ..X~· .:....--....- .. - ... - ..- ....:- - ...;......--.. .;,;....- ..

--x- -....--........ -.. -----.. -....---.....-.. --

•• X......- ....... ------...- - -......- ...- ... --..
.7 --"'-"X- ------...- ---...........- ................X.....- - - -........ - -...... -- -_..- .....-- - ...- ...-

.....X..-X...... X .........---......----........ -----....... - ........- ... - - - - - -... - ...- -..-- X"'--X

. . XXXXXXXX
10 XXXXDXX
71 XXXXIXXX
72 XXXXXXXX
73 XXXDXXX
74 XXXXXXXX
75 ... X.....I--7 ......---X-...

XXXXXXXX
XXXUXXX
XXXXXXXX
XXXXXXxx
XXXXXXXX

XXXXXXXX
XXXXXXXX:
XXXXXXXX;
XXXXXXXX
xxxxxxxx

DXXXXXX
XUXXXXX
XXXXXXO:
XXXXXXXX
'XXXXXXQ

XXXXXXXX XXXXXXXX XXXXXXXX XXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXX
XXXXXXXX XXXXXXXX XXXUXXX XXXXX
XXXXltXXX XXXXXXXX XXXXXXXX XXXXX
XXXXXXXX XXXXXXXX XXXXXXXX 'XXXXX
XXXXXXXX XXXXXXD XXXlQCXXX
-xxXXXXXX xxxxxxxx XXUX
X---~ .. -- ......- ...--...- ...- - - -...- ......---...:-.........- ..---' .............. _-... -X--X
--_........ - --...- - - -

A1

..
II:
W

i!:

II:
CO

':i

t

AND-OR
ARRAV
8K
FUSES

..

II:

~

!§

i

xxxxxxxx

-x---.. . . . . -,----, ----.. . -.. . . ;.----...----

77 X...-_...... -----...- .............- ......-" ...-X...:"''''_- ...-----.. "',..-... ---.. -.;.....--- -----

7' -------- ------.. -, ---....._.. -X"':---- -.....-.. -.. - .............-..... --_ .........79 ......------ ---............ ---... ~ ...-- ...-X...- ..-- ..----'.. - ... -_..... ;.--......-------

-~---

x...---

-----X...... . .-.. _. . . -:--- . . . ----: -.. . . . . .-- ~~--....o--X

80 ......- ..---..... ---...--~~
81 ...... _ .... __ ...--...--.... - ......--... X... -..,.....,........_ ':"'---":'--.....- .........--.. -""......... --82
-~
13 ........ --X...- ................-- .....- .....-X- ;....;.,.......... - --':' ... ~-.. - -----.....- ..--.....--14 "'X--X--- X...--..- ..... , ---_ ..........~..-~,..-.:. ----:---- ---.............. -------85 XXXXXXXX XXXXXXXX xx.xxxxxx XXXXXX;XX XXXXXXXX XXXXXXXlI; XXXXXXXX
86 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX xxxxxxxx: XlCQCXXXX XXXXXXXX
87 XXXXXXXX XXXXXXXX XXXXDXX lQCXXXXXX Xxxxx:xxx. XXlCClXXX XJOQOCXXX
II XXXXXXXX XXXXXXXX XXXXXJCXX xxxxxxxx ~x
XXXXXXXX
89 XXXXXXXX X~ xxxxxxxx: lPC[XXXXX XXXXXQX xxxxxxxx XXXXXXXX
90 XXXXXXXX XXXXXXXX xxxxxxxx ~
XXXXXXXX XXXX~xxx
'1 "'X--X-"''' X..... _ ................---........ ------- - ....---..-- ,.........:....- ...- ---...- ...-92
-X-........................................- ...--;...-...... - ... - ...---...
93
--X-;'-"'- ----~......- - -...---- - .. -~- ...... - - -.........94 - ...- -..-- ----..- ...- .... X................- - -...-- - -...---- - -...---......-----....
,5 ' .....- ...--- --.....................X-..- ... --....---......---......-- - ...... - ...--- --_...---

X. . . ----......-.. . . . --- ------X- ...........- . .---.. . .-- ---...........- .......----- .-"._----nxxxxxx

mxxxxx

---X"'- .------.
.----........
X---...

X---XXXXX
XXXXX
xuxx
XUXX
XXXXX
XXXXX
-X----.. -.....---

"'--X

X----

lBO''''''

Traffic Signal Controller
State Machine Design Example

SEN1'"SEN2

Figure 1 illustrates a simple traffic intersection consisting of
two one-way streets, direction 1 and direction 2. Each direction has a signal consisting of red, yellow, and green lamps
which are activated with appropriately named active high
signals. Also each direction has a sensor which provides an
active high signal indicating the presence of an oncoming
vehicle. Our controller is to manage this intersection with the
sensors as inputs and the lamps as outputs, as shown in
Figure 2.

sw ~w a:~
a: >-

o
lliJ=
o

CI

10001

REDI
YEll
GRNI

SEN2
I

r.l.,
I

I

I

I

I
I

I
I

l_J

r-----,
toI
~---- ....

SENI

Figure 3. State Diagram -

Traffic Signal Controller

Figure 1. Traffic Intersection

Figure 2 also includes the system clock and an initialize (or
reset) signal, which drives the controller to a predefined initial
state. This raises two important issues in designing sequential
logic with PAL devices. First, all circuit implementations of
sequential logic with PAL devices are totally synchronous.
This implies that all state variables (flip-flops) change at the
same time, precisely after the rising edge of the clock.
Second, PAL sequential logic designs should include a means
for initialization to implement test programs and ensure reliable circuit operation. The specifics of the controller operations are detailed with a state diagram shown in Figure 3.
SENI

REDI

SEN2

RED2

INIT

TRAFFIC
SIGNAL
CONTROLLER

Each circle in Figure 3 represents a stable state, i.e. an output
configuration lasting at least one clock cycle. Inside the circles
is the name of the state (SO - S7) and the outputs associated
with that state. For the sake of simplicity in the state diagram,
the transitions involving INIT are omitted; INIT simply drives
the circuit to SO from any state, regardless of other inputs.
Since RED1 = IRED2, RED1 is implemented with one flip-flop
and RED2 with an external inverter.

YEll
YEl2
GRNI
GRN2

ClK

Figure 2

Monolithic WMemories

7-71

Traffic.; Signal Controller
PAL Device Design Specification
TITLE
PATTERN
REVISION'
AUTHOR
COMPANY

TRAFFIC SIGNAL CONTROLLER
TRAFFICl • PDS
A

}(ELVIN CHOW
MONOLITHIC MEKORIES INC., SANTA CLARA
2/28/85

DATE

CHIP TRAFFIC

CLI<
INIT
SENl
SEN'2
Rl

Yl
Gl

PA~16RP8

Y2
G2

CLI< SENl SEN'2 INIT IrC lIc NC NC NC GND
fOE Q2 Ql QO Rl Yl Gl Y2 G2 VCC
STRING
STRING
STRING
STRING
STRING

Simulation .Results
9' Q cq c.
XXHLHIILLIIL
IIIIHIIIIHHLLL
X)QpOOCXLLL
XXXXXXxLLL

9' e.9' cq cq , cq c c c. C'c c

LliLLHLLIILL .RLLIILHLHLH
LLLLLLLLLL LLLLLLLLLL
HHHLLLHHHL I.IIUT,tTTT
LLIJIIIIIHHHL tLHHIIHI/IIIIH
xxxxxLi.LLL LLLLLLLLLL LHIIJiHHHHIIH.
XXXXXLLLLL LLLLLLLLHH HLLLLLLLLL
'XXXXXHHHHH IUIHIIHHHHLI.t TtTTI1JITt
XXJOP(LLLLL tILlII!!!! ~
•. XXXXxLLLLI. LLLL= LHHiIHHHHLL

11 I /SEN1*/SEH2*/INIT '
12 • ISEN1*SEN2*/INIT
13 I SEN1*/SEN2*/INIT '
14 I SEN1*SEN2*/INIT
IS • INIT

STATE

so

= BIIH4] (Rl,Yl,Gl,Y2,G2)

Sl
52
53
54

...
...

85
86

- BIN!.l?] (Rl,Yl,Gl,Y2,G2)
... BIN[17](Rl,Yl,Gl,Y2~,G2)
- B,IN(18] (Rl,Yl,Gl,Y2 I G2)

57

BIN(4J(Rl,Yl,Gl,Y2,G2)
BIN[4](Rl,Yl,Gl,Y2,G2)
BIN(S](Rl,Yl,Gl,Y2,G2)
BIN[17) (Rl,Yl,Gl,Y2,G2)

EQUATIONS
SO
Sl
S2
S3
S4
S5
S6
S7

= I1*81 + I2*52
- I1*52 ... I2*52
... I1*S3 + I2*83
- 11*S4 + I2*S4
= 11.*85 + I2*54
- 11*86 + 12*86
- I1*87 + I2*87
- 11*80 + I2*80

+ I3*50 T 14*81 ... 15*50
+ I3*52 + I4*82 + I5*SO
+ 13*83 + 14*83 .,. 15*SO
+ I3*84 T 14*S4 + 15*50
+ 13*8,6 + 14*55 T 15*50
I4*86

T
T

T

13*86

+

+ I3*87 + I"4*87
+ 1:3*80

T

15*5'0
15*80
3;.4*80 + 15*80

Logic Symbol
eLK
SEN1

SIlIULATION
TRACE_ON CLI< INIT SENl SEN2 Rl Yl Gl Y2 G2
SETF OE INIT
CLOCKF
CLO<;KF
CHECK IRl /Yl Gl IY2 /G2
SETF /INIT /SENl ISEN2
CLOCKF
SETF SENl /SEN2·
CLOCKF
CHECK /Rl /Yl Gl /Y2 IG2
SETF /SE;!Jl SEN2
CLO<;KF
CHECK IRl tyl Gl IY2 /G2

SETF SllNl SEN2
CLOCKF
CHECK IRl 111 jGl /Y2 IG2 .
SETF /SENl /SEN2
CLOClCF
CHECK Rl /Yl IGl /Y2 G2
SETF /SENl SEN2
CLOClCF
CHECK Rl G2
CLOCKF
CHEcK Rl G2
CLOCKF
CHECK Rl

IYl· /Gl Y2 /G2

CLOCKF
CHECK /Rl /Yl Gl /Y2 IG2
CLOCKF
CLO<;KF
CLO<;lU'
CLO<;lU'

, This simula.tion wa.s done using' the alpha release version
, ot Palasm2. sottware.

7·72

MonoIlthloDHlAmorleS·,

~"c

LHLHLHIIL·

LLI=L

LLLU.LLL
IIJiHHHHIIH

LLI,LLI.HH
LLLLHIILL

HHHHu"tiL
~
LLLLLLHH

Memory Handshake Logic
State Machine Design Example
A typical control logic problem is the memory-to-processor
handshake 011 memory transfer used in many computer architectures. The processor makes a transfer request by activating a request line (REO) and specifies a read or write
operation on a Read/Writeline. (R/W).
Duling a:. read. operation. the. processor waits for a Data
Available sign~f at which time the data bus is sampled and the
request line lowered. thus completing the cycle. During a write
operation. the processor places data on the bus .and waits for
a Write Complete signal after the write cycle is finished. Upon

write complete. the request line is lowered. hence completing
the cycle. Table 1 shows the state assignments and the
appropriate outputs. The state diagram is shown in Figure 1.
Also the handshaking operation is illustrated in the timing
diagram of Figure 2.
The memory-board logic to implement this function may· be
designed with gates and edge-triggered flip-flops as· shown Tn
Figure 3. This particular deSign would require about five 5511
M51 packages. but the same deSign can be implemented by a
single PAL16RPS. The PAL design specification using state
equations is. shown on the next page.

STATE

DOUT

DA

WAIT·

0

READ.1

1

READ2
READ3

..

WE

WC

CO

C1

-0

0

0

O.

0

0

0

0

0

0

1

1

0

0

0

0

0

0

0

0:

0

0

COUNT1

0

0

1

0

1

0

COUNT2

0

0

1

0

0

1

COUNT3

0

0

1

0

1

1

WRITE1

0

0

1

0

0

0

WRITE2

0

0

1

1

0

0

WRITE3

0

0

0

1

.0

0

REQoRWoADDIl

. Figure .1. State Diagram - Memory

HandShak;~

logic

1-73

_emory Handshake .Loglc
CK

DATA
OUT

ENABLE

OATA,
!lAILABLE

Figure 2. Memory Handshake Timing ,

Wiiiii
COMPLETE

figure 3. Memory Handshake I-oglc

7·74

Memory Handshake Logic

PAL Device Design Specification
TITLE
PATTERN
REVISION
AUTHOR

COMPANY
DATE

Simulation Results

MEMORY HANDSHAl-high. Else it
icounts up if UP-hiqh and counts- down if UP-low.

TO 5 DO

CLK
THEN

BEGIN

SETF JUP
END
END

CHIP 8Bitcounter PAL20XS
eLK UP 00 01 02 03 04 05 06 07'

UP

; LoacHng some data
;Checking the output
; for the loaded data
:counting up after
; removing HOLD i count
;up 3, cycles, count
;down for 2 cycles.

i.D

GNO

/OC SET 07 06 QS 04 03 02 01 00 CIN VCC
EQUATIONS

/00 :- /SET* LD*/DO

+ jSET*/LD*/QO
:+: /SET*/LD*CIN* UP
+ jSET*/LO*CIN*jUP

/01 :- /SET* LD*/Dl

+

jSET*jLO*/Ql

:+: jSET*jLO*CIN* UP- QO
+ jSET*jLO*CIN*jUP*jQO

;Load DO

;Hold
; Increment
; Decrement
;Load 01

;Hold
; Increment
; Decrement

/02 := jSET* LD*/D2
+ jSET*/LD*/Q2
:+: jSET*jLD*CIN* up. QO* Q1
+ jSET*jLD*,CIN*jUP*/QO*/Ql

;Load 02

/03 : - /SET* LO-/03

;Load 03
;Hold
; Increment
; Decrement

+

jSET*/LD*/03
:+: /SET*/W*CIN* up* QO* Q1* Q2
+ /SET*/LD*CIN*/UP*/QO*/Q1*/Q2

;Hold
; Increment
; Decrement

104 ::c /SET* LD*/D4

;Load 04
+ /SET*/LD*/04
;Hold
:+: /SET*/LD*CIN* UP* QO* Q1* Q2* Q3 ;Increment
+ /SET*/LD*CIN*/UP*/OO*/Q1*/Q2*/Q3 ;Decrement

105 :"" /SET* LD*/D5
+ /SET*/LD*/Q5
:+: /SET*/LD*CIN* UP* QO*, Q1* 02* 03
* 04
+ /SET*/LD*CIN*jUP*jOO*/Ql*jQ2*/Q3
*/Q4

:Load 05
;Hold

/06' : - /SET* LD*/D6
+ /SET*/LD*/Q6
:+: /SET*/LD*CIN* up* 00* Ql* 02* Q3
* Q4 * Q5
+ /SET*/:tD*CIN*/UP*/00*/01*/02*/03
*/04*/05

;Load D6
; Hold

/07 :- /SET* LD*/D7
,+ /SET*/LD*/Q7
:+: /SET*/LO*CIN* UP* 00* 01*' 02* 03
* Q4* 05* Q6
+ /SET*/LD*CIN*/UP*/00*/01*/Q2*/Q3
*/04*/05*/06

;Load D7
;Hold

Simulation Results
Page:
9 egc e -c c e c c c cgc cgcgc c cqc ~
SET HHHHLLLLLL LLLLLLLLLL LLLLLLLLLL LLLLLLLL
LD

XXXXLLLLLL LLLLLULLL LLLLLUIHLL LLLLLLLL

eIN XXXXHHHHHH HHHHHHHHHH HHLLLLHHHH HHHHHHHH
UP

DO
01
02
D3

04
D5

06
07
QO
Q1
02
Q3
04
Q5
Q6

Q7

XXXXHHHHHH HHHHHHHHHH
XXXXXXXXXX XXXXXXXXXX
XXXXXXXXXX XXXXXXXXXX
XXXXXXXXXX >CXXXXXXXXX
XXXXXXXXXX XXXXXXXXXX
XXXXXXXXXX XXXXXXXXXX
XXXXXXXXXX'- XXXXXXXXXX
XXXXXXXXXX XXXXXXXXXX
XXXXXXXXXX XXXXXXXXXX
XXXHHLLHHL LHHLLHHLLH
XXXHHLLLLH HHHLLLLHHH
XXXHHLLLLL LLLaHHHHHH
XXXHHLLLLL LLLLLLLLLL
XXXHHLLLLL LLLLLLLLLL
XX}{HHLLLLL LLLLLLLLLL
XXXHHLLLLL LLLLLLLLLL
XXXHHLLLLL LLLLLLLLLL

; Increment
; Decrement

Logic Symbol
VCC

; Increment

ClK

; Decrement

UP

CIN

DO

00

;,Increment

01

01

02

02

04

Q4

05

05

: Decrement

SIMULATION
TRACE_ON

HHHHHHLLHH HHHHLLLL
XXXXXXHHHH liHHHHHHH
XXXXXXLLLL LLLLLLLL
XXXXXXHHHH HHHHHHHH
XXXXXXLLLL LLLLLLLL
XXXXXXHHHH HHHHHHHH
XXXXXXLLLL LLLLLLLL
XXXXXXHHHH HHHHHHHH
XXXXXXLLLL LLLLLLLL
HLLLLLLHHL LHHLLHHL
HLLLLLLLLH HHHLLHHH
HLLLLLLHHH HHHLLHHH
LHHHHHHLLL LLLHHLLL
LLLLLLUiHH HHHHHHHH
LLLLtLLLLL' ll.LLLLLL
LLLLLLLHHH UHHHHHHH
LLLLLLLLLL LLLLLLLL

03
SET LD elN UP
DO 01 02 0'3 "04 05 -06 D7
00 01 02 O~. 04 05 06 07

S£TF'OC SET
CLOClCF CLK
CHECK 07 06 05 04 Q3' 02 01 '00
SETF JSET UP eIN 'JID

iAll outputs high
;Counting l,lP

FQR 1:"1 TO 9 DO

BEGIN
CLOCKF eLK
IF 1-8 THEN
BEGIN
CHECK /07 /06 /a5 /04 /03, 02 01 00

)Checkinq' after 8
:clock pulses

SET

OC

END
END

SETF JCIK

06
07

;Holding

CLOClCF CLl(

CLOCXP CLK

;The outputs hold to
itheir values

SETP /UP' CIN

;Cou.nting down

MonolithicWMemories

7-77

9·Bit Counter
PAL Device Design Specification
CLOCKF eLl<

Title
9BitCounter
Pattern 9BitCnt.pds
Revision A

; Increment

SETF ILO
CLOCKF CLK

Author

Mehrnaz Hada

Company
Date

Monolithic: Memories Inc •• Santa Clara, CA'
1/28/85

: FUnction Table'

,

;The 9-bit synchronous counter has parallel load, increment,
land hold capabilities. The carry out pin (fCO) shows how to
; implement a carry out using a register by anticipated one
;count before the terminal count if counting and the terminal
:count if loading.

;CLK /OC /LO 08 07 06 05 04 03 02 01 DO
08 07 R6 OS 04 Q3 02 01 90

;operations Table

:

JOC

eLK

Q8-00

operation

x

Z

X
L
H

Q PLUS 1

HI-Z
Hold
Load
Increment

fLD

DB-DO

Q

0

,
,
,
,
,
,
,
,
,
,
,

CHIP 9BitCounter PAL20XIO
eLK

DO 01 02 D3 04 05 06 07 08 fLD GND ",

joe leo

Q8 Q7 Q6 Q5 04 Q3 Q2 Ql

00

/01:'"

ILO.jOl

...

LO·/OI

:'1": fLO. QO

/Q2 :- ILo./a2

;Hold 01
:Load 01

,e

;C,ount
~,;Load

03

; Count

IKold Q4;Load 04

ILO*/04

...

LD*/04
:+: ILD* 00* 01* Q2* 03

; Count

/05 :.,

;Hold OS
;Load 05

106 : ..

;Hold Q6
;Load 06

/LO* 105
+
LO*/05
:+: ILO* 00* 01* 02*,03* 04

; Count

ILD*/Q6

+
LD*/06
: ... : /LO* 00* 01* 02* 03* 04* QS

';Count

;Hold Q7
;Load 07

107 :..

ILO* 107
+
LO*/07
:+: ILO* QO* 01* 02* 03* Q4* QS,," 06

+

:Hold Q8

LO*/08

:+: /LO* QO* Q1* 02* 03* 04* 05.CO :-

+

;Count

lLO*/08
06~ Q7

ILO*/OO* 01* 02* O~* 04* 05* 06* Q7* 08
LO* 00* 01* 02* 03* 04* 05* D6* 07* ,08

;Load 08 (MSB)
; Count

:Carry out (Anticipate
;Carry out (Anticipate

SIMULATION

,

L
C
, C

,e

xxxxxxxxx

L
H
L

LLLLLLU.H
XXXXXXXXX
LLLLLLLHH
XXXXXXXXX
LLLLLlJfHH
XXXXXXXXX
LLLLLHHHH
XXXXXXXXX
LLLlJfHHHH
XXXXXXXXX
LLLHHHHHH
XXXXXXXXX
LIJlHHHHHH
XXXXXXXXX
LHHHHHHHH
XXXXXXXXX

H
L
H
L

H
L
H
L
H
L
H

L
H
L

H
L
H
H
H
H
H

HHHHHHHHH
XXXXXXXXX
HHHHHHHLL
XXXXXXXXX
XXXXXXXXX
XXXXXXXXX
XXXXXXXXX
XXXXXXXXX
XXXXXXXXX

X

SETF LO /08 107 /06 IDS /04 /03 /02 /1',>1 00
CLOCICF eLK

;I.oad

SETF lLO
ClOCICF eLK

; Increment

08
D7
06
05
04
03
02
01
DO

ICO
08
07
Q6
05
Q4
Q3
Q2
Ql
QO

LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
LLLLLLHHHH
XXXHHHHHHH
XXXLLLLLLL
XXXLLLLLLL
XXXLLLLLLL
XXXLLLLLLL
XXXLLLLLLL
XXXLLLLLLL
XXXLLLLLLL
XXXLLLLLLH
XXXLLHHHHL

; Load

SETr /LO
CLOCKF eLK

: Increment

SETr LO /08 /07 106 105 04 03 02 01 DO
CLOCKF eLl<

; Load

04

05
06
07
; Increment

SETF /LD
CLOCKF CLK

08
07

06

05 04 03 02 01 DO

: Load

Ii5
GNO

7-78

Lo ••
Increment

UlHHHHHHH

Lo••

HLLLLLLLL

Increment
Load (Carry out)
Increment (Rollover)

HlDIHlDIHlDI
LLLLLLLLL
HHHHHHHLL
IIHlIHHlDIIJI
IIHlIHHlDIIJI
HHlIHHJlHHL
HHHHHHHHH
LLLLLLLLL
ZZZZZZZZZ

LLLLLLL
LLHHHHH
LLHHHHH
LLHHHHH
HHHHHHH
HHHHHHH
HHHHHHH
HHHHHHH
H8HHHHH
HHHHHHH
LLLLLHH
LLLHHLL
LLLHHLL
LHHKHLL
HLLHHLL
HLLHHLL
HLLHHLL
HHHLLHHLLH HLLHHLL
UlHLLHHLLH HLLHHLL

03

SETF LO 108 107 106 /05 /04 03 02 01 00
CLOCRF eLK

Z

LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLHH
LLLLHHHHHH
HHHHHRHHHH
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLLLL
LLLLLLLHHH
LLLHHHHLLH
LHHLLHHLLH

01

; Increment

LI.LIJ!HHlDI
LLUlLLLLL
LLLHHHHHH.
LIJILLLI.LL
LLHHHHHHH
UlLLLLLLL

Page:
1
9 cgcgcqc gcqogcqj::9,? q090q c
IOC LLLLLLLLLL LLLLLLLLLL LLLLLLL

02

SETF ILD
ClOCKF eLK

H

H
H
H
H
L
H

LLLLLLLlJf Increment
LLLLLLLIJI Lqad
LLLLLLLHL Increment
LLLLLLLHH q q qq qq
HHHHLL/.LLL
00
XZZLLLLI.LL
al ,XZZLLLHIIHH
CLK

q
I,
L
H

g~'~m~~

CHIP IOPOR1' PAL20RAIO
PI. DO Dl D2 D3 D4 D5 D6 CE DCU, CUl'GlID
OE DACK DRDY IIC a6 a5 a4 a3 a2 al ao VCC

a4
as
a6
DCLK

""'

XZZLLLLLLL L
XZZLLLHHIIH H
XZZLLLLLLL L
LLLLLIIHLLL L

DRDY XLZZLIIHHHL L

EQUA1'IOIIS

DACK LLLLLI¥-HH L

ao
go.CLICP
ao.sET!'
QO.1'RS1'

l- DO
- DCLK

al
al.CLICP
al.SB"rF
al.1'RS1'

.- D1
- DCLK

a2
a2.CLICP
a2.SET!'
a2.1'RSl'

.- D2

a3'
a3.CLICP
a3 .. SETF
a3.1'RST

.- D3
- DCLK

a4
Q4.CLICP
Q4.SETF
a4.1'RSl'

:- Dot
- DCLK
- CLK
-CE

as
a5.CLICP
a5.SETF
as.1'RSl'

.- D5
- DCLK

a6
a6.CLICP
a6.SETF
a6.1'RS1'

.- D6
- DCLK
-CLK
-CE

DRDY,
DRDY.CLICP
DRDY.IISTF
DRDY.SB"rF

.- GlID
- DACK
- DCLK
-CLK

DRDY.1'RS1'

• vee

- CUt

-CE

- CUt
-"CE

- DCLK

-cta
- CE'

- CUt
-CE

- CUt
- CE

IIBB of '-bit req8

tE¢.l:nal clock

;Clear register
:Tristate control
IData 1

:!xternal clock
, ela.r register
;Tristate control
;Data 2

,External clock
,Clear reqlster

'T!,i~tat. ~control

;Data 3·

; External clock
;Clear register
:Tristate control
;Data 4

;External clock
;Clear register
;Tristate control

PL

vee

DO

QO

;Data 5

;External clock
: Clear reqister

;Tristate control

01

Q1

02

Q2

;Data ,

;EXternal clock
I Clear req,ister
:Tristate . control
;Hanelshake logic
;Cleared by DACK

; Clear

D3

Q3

D4

Q4

05

Q5

06

as

; A•••rted by DCLK

I (External clock)

SIIIULAl'IOII
TRACE_Oil CUt aO al a2 a3 a4 as as DCLK DRDY DACK

CE

SETF PL ICE IDE 100 Dl ID2 D3 104 DS 106 CLK IDCLK lDACK

;Set input values
;Tristate outputs

sliTI'

CE OE CUt

:Remove the tri-

; states on the

;outputs and clear

; registers

SETF CUt
SETF CUt
SETr lCUt
SETF DCLK
SETr DCLK
SETF'/DCLK
SETF DACK
SET!' DACK
SETF lDACK
SETF llIACK

NI4

OCLl(

NC

DROY

ClR

OACK

GNO

OE

/'
.Clock the data ,

; ••t

DllDY

reqiater

Serial Data Link Controller
Functional Description

Pin Description

Original application was developed by LTT, Conflans Ste.
Honorine, FRANCE. Part of the schematics, reprinted with
courtesy of Ln, is used to control a serial data link based
upon a specialized LSI chip.
Originally designed with six standard SSI/MSI circuits, this
same function can now be implemented, not only into a single
PAL20RA10 device, but with even more features and better
performance. The function can be divided into three subfunctions:
1. Address Decoding
2. Control Flags
3. Transmission Speed Selection
Up to four address lines are allowed (eight were actually
used), plus two extra lines which are special decoding controls
(MEM/IO selection, Enable ControL.). Two flip-flop load flag
conditions, from the address bus (A 1 and A2), providing
handshake between the 6850 UART and the communication
lines. They have a common clock which also serves as Chip
Select (CSO) for the UART.
The UART Transmit clock (TXCLK) can be directly connected
to the Receive Clock (CK or RXCLK) or represents the
Receive Clock value divided by sixteen. This function was
performed by four D-type Flip-Flops connected as a 4-stage
Asynchronous Divider. Since each basic cell, used in a
PAL20RA10 device has four Product Terms available, this
function could be implemented either asynchronously or synchronously. In the PAL Design Specification example, a 4-bit
synchronous divider was used instead of the asynchronous
circuit shown in the schematic.

1.
2.
3.
4.
5.
6.
7.
8.

TEST ................
SYSRESET.........
A2....................
A1 ....................
HDSHAKE..........
CK ...................
E .....................
AUXDECOD........

9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23..
24.

A3....................
A4....................
A5....................
GND.................
IOE..................
A6....................
SPEEDSEL.........
DIV4.................
DIV3.................
DIV2.................
DIV1 .................
CSO..................
BLOCREC ..........
DIR DIV.............
ITPH ................
VCC .................

Monolithic WMemorles

Allows preload function for testing.
Reset line from microprocessor.
Address line from address bus.
Address line from address bus.
Handshake line (CTS/RTS).
External clock.
Enable line from microprocessor.
Extra decoding line
(e.g. board level decoding).
Address line from address bus.
Address line from address bus.
Address line from address bus.
Reference power supply ground.
Output enable line.
Address line from address bus.
Speed selection line.
MSB 4-bit synchronous counter.
3rd stage synchronous counter.
2nd stage synchronous counter.
LSB 4-bit synchronous counter.
UART chip select line (CSO).
Bloc receive line.
Direct or divided clock.
External use flag.
5V power supply.

7·85

Serial Data Link Controller
Before
SVSRESET

,r--------------------------------------------T~

A2
·A1
AI
+5Y
D
(CSO)

0

'i----------'----------------DIR DIY

R °t---r-~~~-------------------BLOCK

A5
A4
A3
AUXDECOD

RiC.
t----t-~~----------------'------HDS~KE

r----+------~---------------------------~

AD

1r=~t===========================================RXD
,-------------------,
TXD
CK

+5Y
E
RIW
TXD
RXCLK

I
I

I
I
I

TXCLK

I

I

I

om

DO
D1
D2
D3
D4
D5
DB
D7

D4

I

D5 8850
DB
D7

L __________________

I
I

~

NOTE: A1yncilronOUl Divider

Figure 6.

After
TEST ~

SVSRESET

~
~
~
~

A2
A1
CK

..

~

AUXDECOD
A3
A4

"..

AS

GND [i)

AO

E: -

~

+5Y

~~

CSO

-C CS1
C§2

RTS
CTS

iR:I5

E
RIW

iiiQ
DO

01
D2
D3
D4
D5
D6
D7

Rfii
IRO
00
D1
D2

03
D4
05
06

~

PAL

2ORA10

T~
DIRDIV
BLOCKREC.

~NC

~NC

~NC
'iii.

..

Ilil/OE

DC6
RXD
TXD

~

8850

D7

Figure 7.

7-86

E:

HDSHAK~

f----J

RXD
TXD
RXCLK
TXCLK

j!YCC

I::

Monolithic

W Memories

Serial Data Link Controller

PAL Device Design Specification
Title

serial Data Link Controller

Pattern
Revision

A

Author

JOB. Juntas / Kelvin Chow

Simulation Result.
page

1

Link. pd.

99

Company

Monolithic Memori•• Inc.

Date

3/1/85

CHIP SE_CH_CNTRL

f

Santa Clara, Ca

EQUATIONS
/TPH
/TPH.CLKF
/TPH.SETF

:- A2
- CSO
- SYSRESET

;Load A2 -as flaq
;eLK WI ACDR. decode

DIRDIV
DIRDIV. CLKF
DIRDIV. SETF

:- Al
- CSO
• /HOSHAKE

; Load speed. ratio

- /DIRDIV

+

HDSHAKE

rqlobal system reset
I eLK

wI

ADDR. decode

; controlled by speed
;option and CTS/RTS
;line
:UART address valid.

:- DIVl

/DIVl
/DIV1- CLKF
/DIV1.SETF
/DIV2
/DIV2 • CLKF
/DIV2.SETF
/DIV3
/DIV3. CLKF
/DIV3.SETF
/DIV4

/DIV4. CLKF
/DIV4.SETF
SPEEDSEL
SPEEDSEL. CUF
SPEEDSEL. SETF

- CK
- /DIRDIV
:- /DIV1*/DIV2
+ DIV1*OIV2
- CK
- /DIRDIV
:- /DIV2*/DIV3
+ /DIV1*/DIV3
+ DIV1*OIV2*DIV3
- CK
- /DIRDIV
:- /DIV3*/DIV4
+ /DIV2*/DIV4
+ /DIV1*/OIV4
+ DIV1*OIV2*OIV3*DIV4
- CK

• /DIRDIV

:- /Al

;4-bit synchronous
;c!ivider LSS
;CLK by CK(external)
leLa by speed option
; 2ND stage of

;divider.
;eLK by CK(external)
;eLR by speed option
; 3RD staqe of
:divider

;eLK by Cl«external)
;eLR by speecl option

XXLLLLLLLL LLLLLLLLLL UtI T I

; 4TH

stage of

; eLK by eK (external)
;CLR by speed option

;Load speed choice

WI

I r. LLLLLLLLLL

SYSRESET HHLLLLLLLL LLLLLLLLLL LU.LLLLLLL IIIITTITTT

/TPH
HDSIIAKE
CSO
SPEEDSEL
DIRDIV

ex

DIVl
DIV2
DIV3
DIV4

Lt.t.LIIHIIIIHH HHHHIIIIHHHH HHHHHHHHHH HHHIIHIIHIIlIH
t.t.HHHHHHHH HHHHIIIIHHHH HHHHHHHHHH HHHHHHHHHH
XlCIIIIHHHHHII HHHHIIIIHHHH HHHHHHHHHH HHHIIHIIHIIlIH
LLLLLLLLLL LLtT T TTl T T LtLLLLLLLL' J ITT n T T T t
LLLLHHHHHH HHHHIIIIHHHH HHHHHHHHHH IIHIIHIIHHHHH
XXXXXHHLIIH LllHLIIHLIIHLHHLllHUlHLH HLHHLIIHLIIH
XLLt.t.LllHHL LLllHHLt.t.HH HtLLllHHt.t.L HHHI.t.t.IIHHL
Xt.t.t.t.t.t.t.LH HHHHH=L LRHHHHHt.t.t. t.t.LllHHHHHL
XLt.t.LLI.t.I.I. LLt.I.t.HHHHH HHHHHHHt.t.t. t.t.LLI.t.I.I.LH
Xt.LLLLLLLL =LLI.t.I.I. LLI.t.t.I.t.HHH. HHHIIHIIHIIlIH

page

9999999
Al

HHHHHHHHHH

A2
A3
A4
AS
A6
E
AUXDECOD
SYSRESET
/TPH
HDSIIAKE
CSO
SPEEDSEL
DIRDIV
CK
DIVl
DIV2
DIV3
DIV4

HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
LLLI.t.I.I.Lt.t.
HHHHHHHHHH
HHHHHHHHHH
L=LLLLL
HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
LLLLLLLLLL
HHHHHHHHHH
LRHLHHLllHL
LLHHHLLLRH
Lt.t.LLIIHHHH
HHHHHHHHHH
HHHHHHHHHH

TEST

- /HDSIIAKE

;CLR by CTS/RTS line

TRACE ON Al,A2,A3,A4,A5,A6,E,

EI

;Siqnals to be

AtJXDECOO,SYSRESET,/TPH,HDSHAKE,

; observed

eso, SPEEDSEL, DlROIV, CK,

VCC

SYSRESET

ADOR. decode

: eLK

A2

DIRDIV

A1

BLOCREC

HDSHAKE

CSO

CK

DIV1

;Reset all regs

CHECK /SPEEDSEL, /DIRDIV, TPH

SETP /SYSRESET,Al,A2,A3,A4,AS,/A6,HDSHAlCE,

E,AUXDECOD

I t

99999'9
HHHHHHHHHH
HHHIIHIIHIIlIH
HHHIIHIIHIIlIH
HHHIIHIIHIIlIH
HHHIIHIIHIIlIH

:divider MSB

• eso

OIV1, DIV2, DIV3, DIV4
SETF SYSRESET,jHDSHAKE

HHHHHHHHHH
HHHHHHHHHH
HHHHHHHHHH
HHIIHIIIIIIIIHH
HHHHHHHHHH

E
XXHHHHHHHH HHHHHHHHHH HHHIIHHHHHH HHHIIHIIHIIlIH .
AUXDECOD XlCIIIIHHHHHII HHHHHHHHHH HHHHHHHHHH HHHIIHIIHIIlIH

SIIIULATION
-

999999999'99999

;eLR by CTS/RTS line

- /A6*AS*A4-A3*AUXDECOO*E

CSO

999

XlCIIIIHHHHHII HHHHHHHHHH
XX!IHIIiIHHHH HIIHHHIIHHHH
XlCIIIIHHHHHII HHHIIHIIHIIlIH
XlCIIIIHHHHHII HHHHHHHHHH.
XXHHHHHHHH HHHHHHHHHH

A6

PAL20RA10

TEST SYSRESET 1.2 Al HDSIIAKE CK E AUXDECOD A3 A4 AS GND
fOE A6 SPEEDSEL DIV4 DIV3 DIV2· DIVl CSO BLOCREC DIRDIV
/TPH VCC

/BLOCREC

Al
A2
A3
A4
AS

;set decode
:condition

E

DIV2

AUXDECOD

DIV3

CHECK /SPEEDSEL, DIRDIV

: Check SPEEDSEL and
; DIRDIV regs

A3

DIV4

FOR 1:-1 TO 15 DO
BEGIN
SETF CK

;This portion
;simulates divide

A4

SPEEDSEL

AS

A6

; by four counter

SETF /CK
END

GND

MonoIlthlc·W . .",orles

7-87

Interrupt Controller
Functional Description
One of the more widely used computer families is the Digital
Equipment Corp.'s PDP-11 series. This family of computers
uses the DEC unibus to communicate between cards. A
specific protocol is required to interface a card to the unibus.
This protocol is described in the available DEC literature.
Since the unibus il! an asynchronous bus, much of the
interface circuitry consists of combinational logic.to generate
specific $ignals and flip-flops which are set and reset as flags.
This tends to use, a lot of SSI a!1d MSI logic packages. Using
Monolithic Memories' PAL devices, much of this logic can be
condensed into a few packages. Figure 2 is the schematic
diagram for an interrupt Controller to be used on the unibus.
(p.6 - 30 of the 1976 DEC PDP-11 Peripherals Handbook.)
Many cards communicate over the bus by taking control of the
unibus with an interrupt request, and then do whatever they
require before releasing control. As can be seen, this interrupt
controller takes six special interface ICs, (380 and 8881 bus

7-88

drivers and receivers) eight MSI, SSIIC, (7400, 740;1 and
7474s) along with some transistors and discrete parts. This
parts count can be considerably reduced by using
PAL20RA10 and PAL20L10 devices.
Figure 1 shows how the circuit with the PAL devices would
look. The two PAL devices allow almost all of the 7400, 7402
and 7474 packages to be removed. (Almost a 4-1 saving in
chip count.) In addition the preload pin (PRLD) on the 20RA10
allows the flip-flops to be easily set to a known state on power
up, or when re-initializing. So the PAL devices reduce the logic
package count from eight chips to three.
This shows that by using PAL devices substantial space and
circuit ,savings can be realized when interfacing to the unibus.
In the schematic shown, there are three VLSI devices, three
MSls and two SSls. Using a PAL20RA10 logic circuit, it is
possible to replace three MSls and one SSI device, thereby
reducing the chip count by a factor of two. The ICs inside the
enclosed loop were replaced.

Monolithic FIJI.itlmorias

Interrupt Controller

INTRAH
INTRAHEN
MCLEARAH
INTRBH
INTRBHEN
MCCLEARBH

:fN~B~~~~~~~BH~----_,

.1
2

3

AINTR

4
NC
ABGIN
FF1RESET

21 FF1RESET
20 NBGINBH

BGINBH

-+---;"'"

21

SSYN

PAL 19 SSYN

BGINAH

VCC
24
FF1
23
FF2
22

PRELOAD

22 ENINTRA

20L 10 EN8881
18
17 ......-++-t-INTRDDNE AH
16
INTRDONE BH

BINTR

15 ......_-r-t--rE-"N7IN'-T~R=B_-t-t-'

NC

20

BUSBBSYL

NFF2
BUSSACKL
FF4

PAL
2ORA10 NFF4
19
FF3
18
BUSBRAL

14 ......_++-t-'-F'-F3=R~E=S=E~T_++-_F~F~3'-R=E~SE'-T~

BUSSSYNL~~-~~

BBGIN 10
BUSBBSYL--4-~~

8881

BUSBRBL

11

NC

10

12

13

MASTERAL

STARTINTRAL-----t---;
MASTERBL
VCC

STARTINTRBL--~_-----

__-

BUS DOSL

BUS 007 L

BUS 006 L

BUS D05 L

Figure 1.

PAL Design Specification
PAL20LIO
INTRPOI
INTERRUPT LOGIC
MONOLITHIC MEMORIES INC., SANTA CLARA, CA
INTRAa INTRAHEN MCLEARAH INTRBH INTRBHEN MCLEARBH BGINBH
BGINAH BUSSSYNL BUSBBSYL STARTINTRAL GND
STARTIHTRBL FF3RESET ENINTRB INTRDONEBH, I~RDONEAH ENeSSI
SSYN NBGINSH FFIRESET ENINTRA NBGINAH vee

DESCR:t:PTION
COMBINATORIAL LOGIC FOR PAL20RAIO INTERRUPT _CONTROLLER
(1ST 'PART OF THE TWO PALS SOLUTION: PAL20L19 & PAL20RA10)
MONOLITHIC MEMORIES INC'., SANTA CLAM, CA
DAN KINSELLA
7/19/84

NOTE: THIS PAL DESIGN SPEC WAS ASSEMBLED oN PALASM VI. 7 •

EQUATIONS

INBGINAH

BGINAH

; FFI eLK CONTROL
i BLOCK A
~SET FFI CONTROL
i BLOCK A
; ENABLE INTERRUPT A

jFFIRESET

-

MCLEARAH+ENINTRA

IENINTRA

.,.

INTRAHEN*INTRAH

JNBGINBH

IENINTRB

iFF3 CLOCK CONTROL
; BLOCI' B
iSYNCHRONIZE FF2 "
; FF4
- S'l'ARTINTRAL*STARTINTRBL
; INTERRUPT BUS
- BUSSSYNL+STARTINTRAL ;SIGNAL INTERRUPT
; DONE,
.. INTRBH*INTRBHEN
; ENABLE INTERRUPT B

IPF3RESET

- MCLEARBH+ ENINTRB

ISSYN

IENSSS1

I INTRDONEAH

IINTROONEBH

BGINBH

=0

BUSSSYNL*BUSBBSYL

; SET FF3 CONTROL
:' BLOCK B
.. BUSSS'\{NL+STARTINTRBL :SIGNAL INTERRUPT
i 'DONE
'

MonoiithlcDJlMemorles

Interrupt Controller

INTRAH

BUSBRAL

INTRENBAH
BUS SACK L
BUSBBSYL
MASTERAL
MASTER
CLEARAH

BGDUTAH

GND~------~~---------=-=-=-===~===

r-----.,..-, i
INSIDE PAL20L10

INTRB H

IBINTR 7400

BUS BRBL

I' ,
INTR ENB B,H I 7400
I
I
I
I

'1

MASTER
CLEAR BH

MASTER B L

I
I
I
I

BGDUTBH

I~

L---:__~--_--_-_-_--_-_-_-_-'-'_-_-_-_-_-_-_-_i~l~.~~.~:..~~N~.: .:.:..,~_;...;'::,::~.,-~..

:,::.,::,.:::.,::,.:::=.;::::,:.,:.:..::.:•.::... ::,:." •.•

I

:~ INSIDE PAL20L 10

BUSSSYNL

INTR DONE B H I
INTRDONEAH
START INTR A L
START INTR B L
VECTOR BIT 2

7400

I

~---------------~

EXT GND (MUST BE GROUNDED)

BUS 006 L
BUS 007 L
BUS 008 L

Figure 2.

7-90

Monolithic W.emorifUI

Interrupt Controller

Simulation Results

PAL Device Design Specification
Title

Paqe:

DIC PDP-ll unibus interrupt controller

Pattern
Revision

control. pd_

Author
Company

Dan Kin•• lla

Monolithic Mamori•• Inc"

Date

3/1/85

qq q
FF3RESET LHHH

Santa Clara, CA

CHIP INTR_CONTROL PAUORA10

PL AINTR KC ABGIN FF1RESET SSYN BINTR NC FF3RESET BBGIN
NC GND
NC OUT4 OUT3 OUT2 OUTl FF3 NFF4 FF4 NFF2 FF2 FFl VCC
EQUATIONS

:Haster control
;block A

/FF1
FF1.SETF
FFl.CLXF

:- /FF1*FF2

FF2
FF2.SETF
FF2.CLXF

:- FFl
- /AINTR
• ABGIN*FF2*/SSYN

:BUS. BUsy siqnal

/NFF2

:- FFl
• /AINTR
- ABGIN*NFF2 *ISSYK

:Bus sack signal

/FF3
FF3.SETF
FF3.CLKF

:- IFF3-FF.

:Mastar control
;block- B

FF4
FF4.SETF
FF4.CLKF

:- FF4
- /BINTR
- BBGIN*FF4*/SSYN

:Bus busy signal

/NFF4
NFF4.SETF
NFF4.CLKF

:- FF3
- /BINTR
• BBGIN*NFF4*/SSYN

;Bus sack siqnal

NFF2.SETF

NFF2.CLXF

- /FF1RESET
- /ABGIN

- /FF3RESET
- /BBGIK

/OUTl

- FF1+FF2

/OUT2

- FF4+FF3

/OUT3

- AINTR

/OUT4

- BINTR

1

FFlRESET LHHII

A

AINTR
SINTR
SSYN
ABGIN
BSGIN
FFl
FF3
NFF2
NFF4
OUTl
OUT2
OUT3

HLLL
HLLL
XXXL
XHHH

OUT4

LHHH

XHHH

LLLL

LLLL
XLLL
XLLL
XHHH
XHHH
LHHII

Pl

FF1

NC

FF2

ABGIN

; Bus request siqnal
;block A
: Bus request siqnal
:block B

VCC

AINTR

FFIRESET
SSYN

NFF2
FF4
NFF4

; Intr. signal for
; bus req. block A
; Intr. 819na1 tor
: bus req. block B

BINTR

FF3

NC

OUT1

FF3RESET

OUT2

BBGIN

OUT3

NC

OUT4

SIMULATION
TRACE ON FF1RESET FF3RESET AINTR SINTR SSYN ABGIN SBGIN
FFl FF3 NFF2 NFF4 OUTl OUT2 OUT3 OUT4
SETF /FF1RESET /FF3RESET AINTR BINTR

;Reset all regs

SETF FF1RESET FF3RESET /AINTR /BINTR
ABGIN SBGIN

;raqs

SETF /SSYN

; Clock FPl and PF3

GND

;Clock NFF and NFF3

NC

;reqs

MonoIltblc

m

Memories

7·91

Notea\··

Logic Tutorial

Table of Contents

8·2

logic Tutorial ...................•....... ................................. ............. .........
Table of Contents for Section 8 .. . . . . .. .. . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. .

8-1
8-2

1.0 Boolean Algebra
1.1 The Language of Logic ..................................... ..........................
1.2 AND, OR and NOT ................... .. .......... .....................................
1.3 Precedence ... ......... .................................................................
1.4 Associativity and Commutativity . .. ............ ........... ..........................
1.S Postulates and Theorems............. .... ...........................................
1.S.1 Duality ..... ...... ......... ......................... ... .. .... ......... .............
1.S.2 Using Truth Tables ................................... ................... •.......
1.5.3 Complement of a Boolean Function
... ....................... .... ..........
1.6 Algebra Simplification ...................................•.... ......... ...... ..... .....
1.6.1 Sum-of-Products and Product-ot-Sums .....................................
1.6.2 Canonical Forms .. ............... ............................ ......... ..........
1.6.3 Conversion Between Canonical Forms ....... ..... ............... ..... .....
1.7 Exclusive-OR (XOR) and Equivalence (XNOR) ..................................
1.8 Boolean Operator Summary .........................................................

8-3
8-3
8-4
8-4
8-4
8-4
8-S
8-5
8-5
8-5
8-5
8-6
8-6
8-7

2.0 Binary Systems
2.1 Base Conversion ....................... ................. .................... ..........
2.1.1 Base-2 to Base-10 Conversion .. . . .. .. . . . . .. . . . . . .. .. . . . . . . •. . . . . . . . . . . ..... .
2.1.2 Base-1 0 to Base-2 Conversion . . . .. . .. . . . . . . . .. . . . . . . . . •. . . . . . . . . . . .. . . . .. .. .
2.1.3 Base-2 to Base-8 or Base-16 . . •. . . . . . . . . . . . . .. . .. . . . . .. . . . . . .. .. .. . . •. . . . . ..
2.2 Simplicity ot Binary Arithmetic ................. ......... .............................
2.2.1 1's Complement . ..... ...................................... ....................
2.2.2 Subtraction with 1's Complement ...........................................
2.2.3 2's Complement ................................................................
2.2.4 Subtraction with 2's Complement ...........................................

8-8
8-8
8-8
8-8
8-8
8-8
8-8
8·9
8·9

3.0 Karnaugh Maps
3.1 Karnaugh Map Technique ..................................................... ;....
3.1.1 Karnaugh Map Reading Procedure ................................... ;....
3.1.2 Karnaugh Map Matrix Labels ...............................................
3.1.3 Karnaugh Map Examples ................... .... ......................... ...

8-10
8-10
8-10
8-10

4.0 Combinatorial Logic
4.1 Logic Design Introduction ..... " ............••.................................. " ..
4.2 Combinatorial Logic .......•................. ...... .................. ........... .....
4.3 NAND Gates and NOR Gates .....................................................
4.4 Multiplexers ...........................................................................
4.5 Decoders ..............................................................................
4.6 Magnitude Comparator .............................................................
4.7 Adder ..................................................................................
4 ..8 Unlocked Flip-Flops -'- Hazards .......................... ........................

8-11
8-11
8-12
8-13
8-14
8·16
8-17
8-17

5.0 Sequential Logic
5.1 Introduction .......................................... .................................
S.2 Unclocked FlipcFlops - Latches ...•.... .........................................
5.2.1 S-A Latch ..........•............ ............... .. ..................... .........
5.2.2 D·Type Latch ..................................................................
5.2.3 J·K Latch . . . . . .. . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . .. . . . . . . . .. . . . . ..
5.2.4 T-Type Latch ..................................................................
5.3 Clocked Flip-Flops - Registers ............ ............ ..........................
5.3.1 Characteristic Equations . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . .. .. . . . . . . . . . ...
5.4 Designing Synchronous Sequential Circuits ....................................
5.4.1 State Transition Tables ......................................................
5.4.2 State Tables and State Diagrams .........................................
5.4.3 Design Examples ............. ................. .. . ......... ........... ........
5.5 Counters . ............... ................ ..............................................

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Logic Tutorial
1. Boolean Algebra
1.1 The Language of Logic
Although you may not be aware of it, you are already an
expert at forming, simplifying and comprehending Boolean
equations and expressions. Boolean algebra, in its most
common application, is concerned with the truth or falsity of
statements. Anytime you describe what circumstances would
make something true or false, you have made a Boolean
equation.
For example, suppose A is true only if Band C are true. These
three letters may represent anything you like - A may be
whether or not you may become president, B mily be whether
or not you are elected, and C may be whether or not you are a
citizen of the U.S.A. You may become president only if you are
elected and you are a citizen of the United States. If we wrote
that statement in equation form, it might look like this:
A = B*C
where.the * is ·a' shorthand notation for the word 'AND'. A, B
and C are all Boolean variables, since they represent some
value. which may be either true or false. You either are a
citizen of the United States, or you are,not.- there is no in
between. Examining the relationship .between these three
.
variables, we find that:
1) if you are elected and you are citizen then you may
become president;
2) if you are elected but you are not a citizen then you cannot
become president;
3) if you are not elected, but you are a citizen, you still can't
become president, and;
4) if you are neither elected nor a citizen, then you definitely
cannot become president.
This same relationship, which may be expressed in terms of
an English sentence, may also be represented by a table of all
the possibilities, called a truth table. If we let "1' stand for
true, and "0' stand for false, we can make the following table:

B

C

0

0

0

0

1

0

1

0

0

1

1

1

Now let's look at the operator 'OR'. Suppose A is true if B or
C.is true. This equation can be written:
A=B+C
Do not confuse the + with the addition sign of arithmetic; in
Boolean algebra, it is shorthand notation for the word 'OR'. A
truth table for. this equation would be:

B

C

A

0

0

0

0

1

1

1

0

1

1

1

1

Figure 1-2. The OR Operator

This table expresses a different relationship between the
variables than AND does; AND requires that both of its
operands be true for the expression to be true. OR only
requires that one of its operands be true for the expression to
be true. From the table above, WEI can see that:
1) if both Band C are false, then A is false:
2) if B is false, and C is true, then A is true:
3) if B is true and C is false, then A is true and:
4) if both B andC are true, then A is true.
Finally, let's look at the operator 'NOT'.. If A equals NOT B,
then the value of Ais the inverse of B.This equation would
be:
.
•

A = IB
Again, the'/' should not be mistaken for the division sign of
arithmetic. It is a shorthand notation for the Boolean operator,
'NOT'. The truth table for this.equation is:

·EEEE····B
o.... .· ....·1A.•...

A

1

.

0

Figure '1-3. The NOT Operator.

Figure I-I. The AND Operator

The table above is a standard way of expressing logical
relationships. Our truth table lists the possibilities one-by-one.
If Band C are false, then A will be false. If B is true and C is
false, then A will still be false. If B is false, and C is true then
A will again be false. However, if Band C are both true, then
A will be true.

which is to say that:
1) if B is false, then A. is .true and:
2) il B. is true then A islalse.
The elementary operators are summarized in Figure 1-4.
OPERATOR
.'

AND

i'

I

NOT

rhe fact is that every time you have an equation of the form:
A = B*C
(OU will have a truth table in the forni of Figure I-I because
:he table and the word 'AND' are just two ways of expressing
:he same relationship between two Boolean variables.

"

*

+

OR

1.2 AND, OR and NOT

SYMBOL

'.

Figure 1-4. Elementary Boolean Operatora

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1.3 Precedence
In arithmetic, the multiplication sign is always evaluated before
the addition sign. For example:
3+4x7
is 31, not 49. Similarly, tn'll AND sign is always evaluated
before the OR sign. Another way to say this is that AND has a
higher precedence than OR.
Of course, in arithmetic, the precedence of operators may be
changed with parentheses. If you wish the expression:
3+4x7
to be evaluated as 49, then you should write it as:
(3

+

4)

x7

The parentheses enclose a subexpression that should be
evaluated before the expression as a whole can be evaluated.
Of the three Boolean operators we .have seen so far, NOT has
the highest precedence, then AND, then· OR.

1.4 Associativity and Commutativity
Both the. AND and OR operators (and, in fact, all binllry
Boolean operators) have the property. of associativity. The
property of associativity says that in an expression with more
than one operator of the same kind, it does. not matter which
you evaluate first. In terms of equatipns, this would be:
B-(e-D) = (B-C)-D
or
B + (C + D) = (B + C) + 0
All binary Boolean operators are. also. commutative. This
means that the order in which the operands. appear is. not
important. In equations, that would be
B-C = CoB
or
B+C=C+B

Theorem 1a: x + x = x
x + x=
=
=
=

(x + xl-True
(x + x)-(x + /x)
x + (x-fx)
x + False

=x

by
by
by
by
by

Postulate
Postulate
Postulate
Postulate
Postulate

1b
2a
4b
2b
1a

1.5.1 Duality
One of the most important properties of Boolean algebra is
the duality principle. This principle states Ihat any algebraic
expression that may be deduced from the postulates of
Boolean algebra has a dual which is also true. The dual of an
expression is obtained by replacing all Trues with Falses, all
Falses with Trues, all ANDs with ORs, and all ORs with AN Os.
For example:
x + True = True
Theorem 2a:
has the dual:
x-False = False
which is theorem 2b. All postulates and theorems listed in
Figure 1'5 are listed as pairs of duals. Of course, any of these
theorems could also be derived without using the duality
principle. For example:
Theorem 2b:
x-False = False
x-False =
=
=
=
=

1.5 Postulates and Theorems
In 1854, the mathematician. and philosopher George Boole
published his book, 'An Investigation of The Laws of Thought',
in which he demonstrated how.classical logic could be defined
with algebraic terminology and operations. Then, in 1938, C.
E. Shannon published his paper "A Symbolic Analysis of
Relay and Switching Circuits", which demonstrated a Boolean
algebra of two values called "switching algebra", which could
be used to represent the properties of bistable electric switching circuits. A minimal set of formal postulates is needed in
order to define this Boolean algebra. Here we will define
Boolean algebra to be an algebra defined over the set B,
where B = (False, True) and over the operators AND (-), OR
(+) and NOT (f), such that:
1) All operators are closed (which means that it is impossible
to create a Boolean expression that has a value other than
True or False),
2) Postulates 1 through 4 in Figure 1~5 are true, and
3) NOT is an operator which, when· applied to a Boolean
variable x, creates its complement such that if x = True
then fx = False, and if x = False then fx = True.
Given this basic set of rules, it is possible to derive any olthe
theorems in Figure 1-5. For example:

False + (x-False)
(x- fx) + (x-False)
x-(lx + False)
x-fx
False

by
by
by
by
by

Postulate
Postulate
Postulate
Postulate
Postulate

Postulate 1

(a) x + False = x
(b) x-True = x

Postulate 2

(a) x + fx = True
(b) x-fx = False

Postulate 3

(a) x + y =y + x.
(b) x-y = y-x

Postulate 4

(a) x-(y + z) = (x-y) + (x*z)
(b) x + (y*z) = (x + y)*(x + z)

Theorem 1

(a) x + x = x
(b) x*x = x

Theorem 2

(a) x + True = True
(b) x-False = False

1a
2b
4a
1a
2b

Theorem 3

f(lx) = x

Theorem 4

(a) x +(y + z) =(x + y) + z
(b) x*(y*z) = (x*y)*z

Theorem 5

(a)f(x + y) = fx*fy
(b)f (x-y) = fx + fy

Theorem 6

(a) x + (x*y) = x
(b) x*(x + y) = x

Theorem 7

(a) (x*y) + (x* fy) = x
(b)(x + y)'(x + fy) = x

Theorem 8

(a) x + (lx'yl = x + Y
(b) x-(lx + y) = x*y

Theorem 9

(x*y) + (lx*z) + (y*z) = (x-y) + (fx*z)

Figure 1-5. Postulates and Theorems of Boolean Algebra

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1.5.2 Using Truth Tables
Finally, theorems may be demonstrated with truth tables. A
theorem always holds true if it holds true for all cases. Since
two variables can only have two values each, there are only
four possible cases, so it is reasonable to look at a theorem
on a case-by-case basis. For example, we can prove Theorem
5a with the following truth table:

obtained by replacing alil's with O's, all O's with l's, all ANDs
with DRs, and all DRs with ANDs.
In fact, the easiest way in which to obtain the complement of
a function is by taking the dual of the function and complementing each individual variable (called a literal). For example,
the complement of:

F = (x + ly)*[W*(x + z)]
can be found by

+ V)

x

V

F

F

T

T

I(x

(lx.IV)

1) taking the dual:

FD = (x'ly)

+ [W + (x'z)]

2) complementing each literal:

F

T

F

F

T

F

F

F

1.6 Algebraic Simplification

T

T

F

F

A literal. is a complemented (Ix) or uncomplernented (x)
variable. A term is asubexpression, often enclosed in paren~
theses. The equa,ion:

IF = (/x·y)

Figure 1·6

+ [IW + (/x'/z)]

F = (x + IY)'/x
It can be seen from Figure 1-6 that, in every case, I(x
equal to (/x*ly).

+ y)

is

1.5.3 Complement ota Boolean Function
A Boolean expression is some mixture of Boolean variables
and operators that has a value. For example:

x + y*zo/a
is a Boolean expression. A Boolean function is a statement in
which two expressions are equated. For.example:
a= b-c
I(c*d) = Ic

+

Id

are. Boolean functions. The difference is the presence of an
equal sign. It is. worth noting that 'eqllals',or equival(;lnce, IS
also a Boolean function,since two expressions either are or
are not equal. However, in this book we will aHemPt to present
only true equations, so the Boolean value of an equal sign
may be ignored in functions.

has three literals and two terms. Simplifying a Boolean equa.
tion is an attempt to minimize the number of literals or the
number of terms in an equation. Unfortunately, in many
situations, one can only be minimized at the expense·of the
other, so it is important to decide from the outset whether you
are minimizing literals or terms. Literals can be minimized by
repeated applications of. the postulat!'ls and. theorems of
Boolean algebra (Table 1-6), but there is no algorithm; it is a
trial and error process, and the result may not be unique. For
example, the equation:

F = (x*/z) + f(x+ y)*/:;:]
may be simplified ttlrough the foll()wing steps:

F = (x-/z) + [(x + y)*/z]
= (/z'x) + [/z'(x + y)]
= Iz*[x + (x + y)]
= Iz'[(x + x) + y]
= Iz-(x + y)

Postulate 3b
Postulate 4a
Theorem 4a
Theorem la

.So far, wel1ave talked. about aBoolean expression's value as
True or False. More frequently; these vafuesare written as 1
and 0, with 1 standing for True, and 0 standing for. False. From
hereon, we will also adopt this standard;

The equation is now simplified because there are no postulates or theorems which, when .applled,will serve to reduce
the number of items further.

The complement of an expression· may be written easily by
placing the NOT operator in front of the enclosed expression:

When an equation is in the form:

lex

+

yl.zo/a),

F=(a*b).+ (c'/a)

but it is also possible to complement a function. The complementofa function is ()btained by complementing both sides of
an equation. For· example, given the. equation:

/a =b*c + 1
the complement would be:

1(/a) = I(boc +1)
which Could be simplified:

a = /(b*c + 1)
a = l(b*c)'/l

1.6.1 Sum-of-Products and Product·otoSums

by Theorem 3
bYTheorem5a
def; of c()mplement
by Theorem 2b

a = Jlb-cl*O
a""O
Note the differences between obtaining the complement of a
lunction, and obtaining the dual ofa function. The complenent is obtained by complementing the entire expression on
)oth sides of the equation, and manipulating it from there with
:he given postulates and theorems. The dual of a function is

+

d

for example, it is sai.d to be in sum .of products Jorm. This is
because the equation is composed of a number of pro(:fuct
terms (AND) .that are summed (ORed) together. The subex"
pre.ssion resulting from two operands being ANDed.together is
referred t() as a product because of the resemblance of the
AND. operator to the multiplication operat()r of arithmetic; the
result of OR is referred to· as. a sum because of the resemc
blanceof the OR operator to. the addition operator of arithmetic.
When an equation is in the form:

F = (a + b)'(a + Ic)
for example, it is said to be in product of sums form, because
it is composed of a number of sum 'terms (OR) that are
ANDedtogether; Both sum ofpr6ducts arid product of sums
forms are called standard forms.

MonoIlthlcWMemories

Logic, Tutorial
~.6.2 Canonical Forms
If an equation has three variables that are complemented or
uncomple(llented, then there are.a limited number of ways in
which these variables can be ANDed or ORed together.
Referring to Figure 1·7, under the column' Minterms', and the
subcolumn 'Term', there are eight different ways in which
three variables could be ANDed together. Each combination
has been given a name: the letter 'm' and a number. For
example, the expression:
(lx-y-z) is m3
while the expression:

Mlnterms
Term

x-/y-/z
x*/y-z
x-y-/z
x-y-z

x-/y-/z
x-/y-z
x-y-/z
x-y-z

Maxterms
Name

ma
m1
m2
ms
m4
m5
me
m7

Term

Name

x+y+z
x + y + Iz
x.+ Iy + Z
x + Iy + Iz
Ix + y + Z
Ix + y + Iz
x + Iy + z
Ix + Iy + Iz

Mo
M1
M2
Ms
M4
M5
Me
M7

Figure 1-7
Using these shorthand notations for expressions, we can refer
to the equation:

F

= (lx-y-/z)

+ (x-/y-/z)

+ (x-/y-z)

as:
F- m2+ m4+ m5
which is much more compact. When an equation is expressed
in terms of these named AND subexpressions, or minterms it
is said to be in sum-of·minterms form.
Similarly, there are eight ways in which three variables may be
ORed together. Such an OR subexpression is called a maxterm. The equation:
F = (x + y + z)-(x + Iy +/z)-(/x + Iy + Iz)
could also be written as:
F - Mo-Ms-M7
since each OR subexpressio'n has been given a name consisting of an 'M' and a number (see the column 'Maxterms' in
Figure 1-7). An equation expressed in this way is said t6' be
written in product-of-maxterms form. Both sum of minterms
and product of maxterms. forms are called canonical forms.
In many equations, not every variable is represented in every
term, but it is still possible to write them in canonical form. A
little algebraic manipulation will produce the missing terms that
are needed. For example, the equation:
F = (x-y-z) + (lx-y)
is missing a 'z' in its second term. In order to write this
equation in sum of minterms form, we must first take the
following steps:

8-6

Postulate 1b
F = (x-y-z) + (lx-y-l)
= (x-y-z) + [/x-y-(z + Iz)]
Postulate 2a
Postulate 4a
= (x-y-z) + (lx-y-z) + (/x-y-/z)
=m2+mS+1'l7
To create a missing variable in a maxterm, use the duals of
the postulates used above. To create more than one missing
variable, expand the equation as many times as is needed by
following the steps above.
1.6.3 Conversion Between Canonical Forms
Canonical forms do not only exist because they are more
compact. With canonical forms, it is a trivial matter to invert an
expression, or to convert between sum-of-product and product-of-sum representations.
Given the equation:
F

= (la-b-/c) + (a-/b-c)
= m2 + m5 + m7

+ (a- b-c)

we can take its complement by forming an equation from all
the minterms that are NOT present in the equation:

IF

= mo + m1 + ms + m4 + me
= (/a-/b-/c) + (la-/b-c) + (/a-b-c) + (a-/b-/c) +

(a-b-/c)
Finally, using the dual/complement method, we can take the
complement again. Of course, by Theorem 3 (Figure 1-5),
anything that is complemented twice returns to its original
value:
F = (a + b + c)-(a + b + Ic)-(a + Ib + Ic)
-(/a + b + c)-(/a + b + Ic)
We have now expressed function F, originally a sum of
products, in product-of-sums form. Any Boolean equation can
be written in either form.
Thus a quick way of doing this conversion is. to write a
product-of-maxterm equation using the maxterm numbers
which did not appear in the original equation. In OUf example,
we used the numbers 2, 5 and 7 for the sum-of-minterms
form. In our product-of-maxterms form, we would use the
maxtermsO, 1, 3, 4 and 6.
F

= Mo-M1-Ms-M4-Me
= (a + b + c)-(a + b

+ Ic)-(a + Ib + Ic)
-(/a + b + c)-(/a + Ib + c)

This works because each maxterm is the dual of the minterm
that has the same number.
Of course, any eql!ation written in the canonical forms can
likely be simplified. After. converting from standard form to
canonical form, then converting from one canonical form to
another, you may wish to simplify your equation.

1.7 Exclusive-OR (XOR) and Equivalence (XNOR)
There are two other frequently used operators which are really
just speCial combinations of the AND, OR, and NOT operators.
The first is the Exclusive OR operator. Its symbol and truth
table is shown in Figure 1-8. Note that the simple OR function
is true even when both conditions are true, which is somewhat
unlike our conversational use of the word 'OR'. The XOR
function is more like our normal use of 'OR': one or the other
condition is true, but not both.

~lthlcmMemOl"l_

Logic Tutorial

1-8 Boolean Operator Summary

The XOR function

X:+:Y

x-t>-F ;=O-F ;:::r:>-F ;:::>D-F

is equivalent to

a.

x*/y + Ix*y.
A

B

A :+: B1

0

0

0

X-l>--F

1

b.NOT
F = Ix

0

1

1

0

1

1

1

0

x

The Equivalence (XNOR) operators, symbols, and truth table
are shown in Figure 1·9. It is true only when both conditions
are the same. Thus XNOR is the complement of XOR
Here x :*: y is equivalent to x*y + Ix*/y.
B

0

0

1

0

1

0

1

0

0

1

1

1

•• OR
F=x+y

F

g.XOR
F = ( x-/y) +' (/x_y)

;=D- :=D- ;=JD-F
F

d. NAND
F = I(x-y)

F

h. XNOR
F .. ( x-v) + (/x_/y)

I. NOR
F=ICx+y)

Figure 1-10. Logic Gates

Figure 1-8. The XOR Operator

A

c. AND
= x_y

BUFFER
F=x

A :*: B

V Fl F2 F3 F4 F5 F6 F7 Fa F9 FlO Fll F12 F13 F14 F15 F16

0 0 0 0 0 0 0 0 0 0 1

1

1

1

0 1 0 0 0 0 1 1 1 1 0

0

0

0

1

1

1

1

0

1

1

0

0

1

1

1

0

1

0

1

0

1

1 0 0 0 1 1

0

0 1 1 0

1 1 0 1 0 1 0 1 0 1 0

0

-

x

Y :+: +

:-: IV

1

IX

1

1

1

1

Figure 1-11 Boolean Operators

Figure 1-8. The XNOR Operator

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2. Binary Systems
Binary numbers utilize a base 2 number system that consists

of two digits: '0' and '1'. This number system is used in
current digital computer systems because the outputs of most
switching circuits can only be in one of two logical states.
Also, when transistor circuits are only operating in one of two
modes greater reliability can be obtained.
>

2.1 Base Conversion
Normally, decimal (base 10) numbers are written using a
positional notation. In other words, the value of the number is
determined by multiplying each digit by an appropriate power
of 10 which is dependent on its relative position to the decimal
point.
Example 2.1
714.02 = 7 x 102 + 1 X 101 + 4 x 100 + 0 X 10- 1 + 2 x 10- 2
2.1.1 888e-2 to Ba8e-10 Conversion
Similarly, binary (base-2) numbers are also position-dependent
relative to the binary point: each binary digit is multiplied by an
appropriate power of 2 in order to obtain the decimal equivalent. The following example shows the conversion from a
base-2 number to a base-10 number.
Example 2.2
101.01 2 = 1 X 22 + 0 X 21 + 1 x 20 + 0 X 2- 1 + 1 X 2- 2
= 4 + 0 + 1 + 0 + 1/4
= 5.25 10
Notice that the binary point separates the positive and the
negative powers of 2. This is similar to the case of the decimal
point separating the positive and negative powers of 10.
2.1.2 Base-10 to Ba8e-2 Conversion
Converting a base-10 integer to a base-2 integer requires
utilizing the division method. To explain, let N represent the
base-10 integer. Divide N by 2, since base-2 is desired. As a
result, there should be a quotient, 0 0, and a remainder, Ro.
Then divide 0 0 by 2 again and continue this process until the
final quotient equals zero. The desired binary digits are the
remainders resulting from each division step; the least significant bit starts with Ro.
Example 2.3
Converts 61 10 to binary:

61/2 = 30
remainder = 1
LSB
30/2 = 15
remainder = 0
15/2=7
remainder = 1
712=3
remainder = 1
3/2= 1
remainder = 1
1/2=0
MSB
remainder = 1
61 10 = 111101 2
Converting decimal fractions to binary requires successive
multiplications by 2. Let F be a decimal fraction. Multiply this
number F by 2 and obtain an integer and a fraction result.
Take the fraction and multiply once again by 2. Continue this
process until the fraction becomes zero, or until a sufficient
number of digits has been reached. The desired digits are the
integer parts that were obtained at each multiplication step.
The most significant digit is obtained first.
Example 2.4
Convert 0.375 10 to binary

8-8

0.375

x

2

0.750

0.750

x

0.500

x

2

MSB

2

1.000

1.500

LSB

0.375 10 = 0.011
Note that if this procedure doesn't terminate, then the result
must be a repeating fraction.
2.1.3 Base-2 to Base-S or Base-i&
To convert binary to octal (base-B) or vice versa is very simple
and can be done by inspection. Each octal digit corresponds
to three binary digits, since it can be in one of eight states (0
to 7). Therefore, the binary number should be divided into
groups of three starting from the binary point. Each group on
both sides of the binary point is replaced by an octal digit
representation.
Example 2.5
101110.011 2 =

101

110

5

6

011

3

8

Similarly, binary to hexadecimal (base-16) and vice versa can
also be done easily. This time, instead of three, the binary
number is broken up into groups of four. The reason is
because a hexadecimal digit can. assume one of sixteen
states (0 to 9, A, B, C, D, E and F). Again starting from the
binary point, each group is replaced by its hexadecimal
equivalent.
Example 2.&
11100101.0011 2 =

1110
E

0101
5

0011
3 16

2.2 Simplicity of Binary Arithmetic
Due to the design of logic networks, it is much easier to do
binary than decimal arithmetic in digital systems. Although
binary arithmetic is implemented in about the same manner,
the addition tables are much easier. Fortunately, numerical
subtractions may be performed by addition operations between numbers. This property is of little use in the decimal
system. However, much can be gained if used in the binary
system. This is mainly due to the fact that in a binary system,
complements of numbers are easily implemented, and the
same hardware can be used for addition and subtraction
operations. This allows for considerable savings in termS of
system hardware design.
2.2.1 1's Complement
Finding the 1'5 complement of a binary number is easily done
by inverting each digit (0 or 1).
Example 2:7
The 1'5 complement of:
01011.1101 = 10100.0010
2.2.2 Subtraction with 1's Complement
To subtract two positive binary numbers X and Y, (X-Y), the
following procedures should be used:
1. Take the 1's complement of Y and add it to X.
2. Check results for overflow carry:
a. If there is an overflow carry, add it to the least
significant digit of the result.
b. If there is no overflow carry, the result is negative.
Then, complement this result and place a minus sign
in front.

MonoIlth/eW Memories

Logic Tutorial
Example 2.8
a) 1010.11

overflow 1

b) 1001.10

-1000.01 =?
1010.11
+0111.10
0010,01
+
1
0010.10

+- l's complement of 1000.01
+- add overflow carry
answer

....

-1100.11 =?

1001.10
+ 0011.00 +- l's complement of 1100.11
no overflow
11.00.10 .... -0011.01 .... answer
2.2.3 2's Complement
The most widely used numbering manipulation technique in
current digital computers is the 2's complement method. This
method is easily implemented with any decent computer
instruction set. Using the same hardware for addition and
subtraction in 2'scomplement makes system design simpler
and can lead to savings in cost.
Finding the 2' s complement of a binary number requires the
following:
1. Take the logical complement by inverting each digit 01 the
binary number.
2. Add 1 to the least significant digit.
Example 2.9
The 2' s complement of 001100.01 is
step (1) 110011.10 +- logical complement of 001100.01
step (2) + ___-'-

110011.11 -+ answer

This technique can also be done by visual inspection. Start
with the least significant. digit of the number and visually scan
to the left. Leave all digits unchanged until the first '1' is
encountered. Then invert all the remaining digits to the left of
this first '1'. Note that the binary point has no effect on this
procedure.
2.2.4 Subtraction with 2's Complement
The steps for subtracting two binary numbers X and Y, (X-V),
areas follows:
1. Add X.to the 2's complement of Y.
2. Check result for overflow carry:
a. If there' is an overflow carry, then throw it out. The
result now represents (X-Y).
b. If there is no overflow carry,the number is negative.
Take the 2's complement of the result and place a
negative sign in front of it.
Example 2.10
a) 1110.11 -1011.10

overflow carry.
throw out 1

=?

1110.11
+0100 ..10 +- 2's complement of 1011.10
0011.01

b) 0001.11 -1000.10

-+ + 0011.01

-+ answer

=?

0001.11
+ 0111.10 +- 2's complement of 1000.10

no overflow
carry
1001.01 -+ -0110.11 -+ answer
Note that in computing systems which need. to represent
negative numbers, the MSBserves asa sign bit. When it is
'1', the number is negative.

~

I

I
I

MonoIithicW.emor/e.

8-9

Logic Tutorial
3. Karnaugh Maps
3.1 Karnaugh Map Technique
There exists a technique that ..allows the logic designer to
minimize Sum of Product terms by utilizingK~m~ugh maps.
The Karnaugh map (sometimes referred to as K-map) graphically displays the implicants (IT!interms) of .any sum-of-products expression in a matrix. It is derived directly from the truth
table of this expression. K-m~s are very useful for minimizing
three, four, five and even six variable functions, but it gets too
complicated beyond six. For expressions with. more than six
variables, the numerical manipulation should be done on a
computer that uses a. method such as the Quine-McCluskey
method. This technique will not be. discussed here.
3.1.1 Karnaugh Map Reading Procedure
Each minterm cell in the K-maphas a value of '1' as
determined by the truth table. Circle those single minterm cells
that will combine with its adjacent cells to form larger groups
of 1, 2, 4, 8, etc. If each single minterm cell is grouped
individually, the map reading process should yield the Original
Sum of Product expression.
However, if two minterm cEllis are grouped together, at least
one variable is dropped.· This is because thethedrem
+ X'/Y = X
has been executed once. If a group of four adjacent minterm
cells have been combined, then the theorem has been executed twice, and two variables are dropped. A group of eight
adjacent cells result in three variables being dropped. Therefore, the main objective is to minimize the number of minterm
cell groupings while maximizing the number of minterm cells in
each grouping. By minimizing the number of cell groupings,
the number of product terms is reduced. On the other hand,
by maximizing the number of cells in each grouping, the
number of literals in each product term is reduced.
For any product term, the variables which are included in the
term are those whose values in the labels of the grouped cells
are constant. The constant values give the polarity of the
variables.
In example 3.1, product term 1 has cells with labels ABC =
010 and 110. Band C are constant here; B is 1 and C is 0,
giving the product term B·/C.
3.1.2 Karnaugh Map Matrix Labels
In labeling the K-m~ matrix, the following rule should be
followed:
Top to bottom or left to right:

x·y

Four-variable
Two-variable Three-variable
Add a '0' MSB and use the
00
000
001
three-variable chart for the first
01
11
half. For the second half, add a
011
'1' MSB and repeat the same
10
010
chart in reverse order.
110
111
101
100
Notice that the number of variables shown above is referring
to one axis only (X or V). However, this technique may be
used for any number of variables that may be desired on each
axis. For any axis greater than one variable, the second-half is

8-10

a mirror image of the first-half with the MSB equal to a '1'.
This can be seen above when comparing the three-variable
list to the two-variable list.
3.1.3 Karnaugh Map Examples
Examples of three- and four-variable K-maps are shown
below. The corresponding truth tables for the examples are
also shown to illustrate the derivation of the K-maps.
Example 3.1
Three-Variable K-map:
B,C

A

B

C

F

0

0

0

0

o 0

0

0

1

1

1

0

1

0

1

0

1

1

1

1

0

0

0

1

0

1

1

1

1

0

1

1

1

1

0

It.

DO

0

01

1
2

Karnaugh Map
product term 1= B./C
product term 2 - IB.C
product term 3 = I A.C

F - B./C + IB.C + IA.C

Truth Table
Example 3.2
Four-Variable K-map:
2

"\

A

B

C

D

F

~

0

0

0

0

1

GO

0

0

0

1

1

01

0

0

1

0

1

11

0

0

1

1

1

10

0

1

0

0

1

.L ...!

0

1

0

1

1

0

1

1

0

0

0

1

1

1

0

1

0

0

0

1

1

0

0

1

1

1

0

1

0

1

1

0

1

1

0

1

1

0

0

1

1

1

0

1

1

1

1

1

0

0

1

1

1

1

0

Truth Table

MonoIllhlcWMemorle.

A,a

1

GO

01

\11

1

1

1

10
1]

1

1

0

0

1

1

0

0

0

1

"}
3

Karnaugh Map

product term 1 = IC
product term 2 - IA./B
product term 3 = IB.C./D
F - IC + I A./B + IB.C./D

Logic Tutorial
4. Combinatorial Logic

INPUTS

4.1 Logic Design Introduction

DECIMAL

Logic design is a combination of analysis, synthesis, minimization and implementation of Boolean functions. Boolean functions must originally come from worded statements. This is a
very important part of logic design because the worded
statement can be ambiguous and imprecise, while the Boolean equation must be unambiguous and exact. The conversion of words to equations is called synthesis. Engineers must
be careful when synthesizing a problem because many times
the originator of a problem is not a· technical person. It is the
responsibility of the logic designer to review the synthesis of
the problem with the originator to make sure the solution is
suitable.

b

c d

e

f

9

0
1
2

0
0

0
0

0
0

0
1

1
1

1
0

1
0

0

1
1

0
1

1
1

1
0

0
0
1

1

0
1

1
0
0

0
0

0
0

1
1
1

3
4

0
1
1

0

0

0
1
0
1

0
1
1

1
1

0
1

1
1
1

0
1

0
1

1
1

1
1

8

0
0
0
1

1
0
0

0

5

1
1
1

1
1

1
1

0
1

0
1

0
1

0
1

9

1

1
1

1

1

0

0

1

1

6

7

4.2 Combinatorial Design
Combinatorial. logic is a network· whose output is solely
dependent upon its inputs. It has no feedback loops or
memory elements.
The .. first step in combinatorial design is to analyze the
problem and then define it in an exact manner. This will make
synthesizing a Boolean equation much easier.
Synthesis usually takes several steps. Using truth tables and
K-maps are commonways of specifying a problem and putting
it in the minimal Boolean form.
Example .4.1
A seven-segment decoder decodes a BCD number and turns
on the appropriate segments of a seven-segment digit. Given
the seven-segment digit in Figure 4-1, develop a minimal
equation for each segment by using a truth table and K-maps.

~

W,X

00

002"

a

1

1

1
0
1

0
0

0
0

0
1

01

11

~

00

01

11

0

1lL!J

00

1

1

1

1

01

1

0

1

0

W,X

10

10

J

01

0

1

1

0

11

X

X

X

X

11

X

X

X

X

10

1

1

X

X

10

1

1

x

xl

~z

W,X

00

01

11

10

00

1

1

1

0

01

1

1

I1

1

11

X

X

X

10

1

1

X

~

w,x

00

b

~

01

11

10

o

ILl

01

0

1

0

1

xJ

11

X

X

X

X

X

10

1

o Irx

x

I

d

~

= /x./z + /x.y + y./z + x.ty.z

~

00

01

11

10

..2..

00

1

0

0

0

1

01

1

1

0'1

X

11

..!.

x

x

X

x

10

1

1

X

X

01

11

10

0

0

01

0

0

0

11

X

X

X

10

11

0

x

W,x

• =/x./z + y./z

f'

~

W,X

00
01

=W + X~/Z+ x./y + /Y./l

00

01

11

0

0

1

1

r;- l '

0

1

11..!..
10

1

10

...!.. x

X

X

X

1

=W + x./y + /x.y + y./z
FlgUI'84-2

MonoIlthlcWMemorhia

00

oo~

00-..0

g

=/X + ty./l + Y.l

W,x

c = ty + x + Z

=orming a truth table from Figure 4-1 is dorie by writing all '1 0' .
)ossible inputs down, then determining which segments
ihould be activated for each input. For example, ·segment 'a'
sactivated whenever; 2, 3, 5, 7, 8, 90r 0 is input to the
lecoder. Once the table is formed, a K-map can be made for
,ach segment. The K-maps are used to derive a Sum of
'roducts logic equation for each segment.
~-maps are an excellent way of forming equations when three
I) six variables are involved in a problem. Either of the .twO
tandard algebJaic forms of the function (sum-of·products or
Iroduct-of'sums) can be derived. A network of AND and OR
lates is obtained directly from either form.

1

=/x./z + w.ty + X.l + /x.y

d

Figure 4·1, Seven-8egment Decoder

OUTPUTS

W X Y Z a

Logic· Tutorial

ROW A B C

MINTERMS

IA-/S-IC = mO

A+S+C=MO

1

0 0 0
1 ...
0 0

IA-/S-C = ml

A + S + IC = Ml

2

0 1 0

IA-S-IC = m2

A + IS + C = M2

3

0 1 1

IA-S-C = m3

A + IS + IC

4

1 0 0

A-/S-IC= m4

"/A+S+C=M4

5

1 0 1

A-/S-C =mS

6

1 1 0

A-S-/e

7

1 1 1

A-S-C = m7

= M5
IA + IS + C = M6
IA+ IB + IC = M7

0

a = ~m (0, 2, 3, 5, 7, B, 9,10,11,12,13,15)
b = ~m (0,1,2,3,4,7, B, 9,10,11,12,15)
c =~m (0, 1, 3, 4, 5, 6, 7, B, 9,11,12,13,14.15)
d = ~ m (0, 2,3, 5, 6, B, 10,11, 13)
e = ~ m(O, 2, 6, B, 10, 14)
f = ~ m (0, 4, 5, 6; B, 9, 10, 11, 12,13,14, 15)
g =' ~m(2, 3, 4, 5, 6,B, 9,10,11,12,13,14,15)
Example 4.3
We can easily rework the first two K-mapsfrom Example. 4•.1
to get a maxterm solution.

MAXTERMS

= M3

IA +S + IC

= m6

~

W,X

00

DO

01

11

10

1

0

1

1

lro

Figure ....3 Mlnterm and Maxterm Expansions for 3 Variablea
01

Since a minterm is a product term, an unminimized sum-ofproducts expression· may also be written wi~h minterms.
Each maxterm is a sum of variables. It is derived by solving a
K-map for the O-terms instead of the 1-terms. Maxterms are
used in a product-of-sums solution.
Example 4.2
Rewriting the Sum of Products equations from example 4.1 in
minterm form can be done by inspecting the truth table or Kmap.

01

1

1

l1W

x

x

10

1

X

1

~

w,x.

DO

01

11

10

00

1

1

1

1

01

1 .

l~

11

X

X

10

1

= X./Z + IW_/X./V.Z

I.

;rol lrol
1

:I!J

x

I~

1

X

X

Ib = X./V + X_/Z
b (IX +Y)-(lX + Z)
b =lI'M (5, 6, 13, 14)

• =(IX + Z).(W+ X + V + 17:)

=

a = 1TM (1, 4, 6, 12, 14)

Given either camonical form, it is a simple matter of converting to the other form, or the inverse of either form.
..

DESIRED FORM
GIVEN FORM

Mlntern
expansion of F

Maxterm
expansion of F

Minterm expansion
of F.

Inverted Mlnterm
expansion of F

Maxterm expansion
of F

Minterm numbers
are those numbers
not on the. maxterm
list for F

Inverted Maxterm
expansion of F

Maxterm numbers
are those numbers
not on the minterm
tist for F

List minterms not
present in F

Maxterm numbers
are the same as
minterm numbers
of F

-

Minterm numbers
are the same as
maxterm numbers
of F

List maxterms not
presem in F

Figure 4-4 Conversion of Forms Table

4.3 NAND Gates and NOR Gates
A set of logic operators is saJd to be functionally complete if
any Boolean function can be expressed in terms of this set of
operations. The set (AND, OR, NOT] is functionally complete.
The NAND and the NOR gates are each functionally complete
by themselves. Therefore they are called universal gates.
Conversion of AND and.OR networks to NAND networks is
carried out by starting with a minimal sum of products expression and then applying the theorem; F = I(lF). This equation
can then be manipulated using DeMorgan's theorem.

.

X

y

Z

x

y

0

0

1

0

0

1

0

1

1

0

1

0

1

.. 0

1

1

1

1

.0

1

0
1 .

0

Z = I(A.B)

Z=/(X+Y)

Figure .... 5. Truth Tables

8-12

/IIfono/ithlt:WMemorJes

Z

0

Logic Tutorial
Example 4.4
From the K·map in Figure 4-6, we can find equations for an
AND-OR, NAND-NAND, OR-NAND and NOR-OR networks.
CD

~

00

00

01

11

10

1

0

1

0

01

1

0

1

0

11

1

1

1

1

10

0

0

0

0

Figure 4-7. Network Conversion
Figure 4-6. Karnaugh Map

4.4 Multiplexers
F = A-B + IA-/C-/D + IA*C*D
= I[/(A-B + IA-/C-/D + IA-C-D)]
= I[/(A-B)-/(/A-/C-/D) + I(/A-C-D))
= 1[/ A + IB)-(A + C + D)-(A + IC + 10))
= I(/A + IB) + I(A + C + D) + I(A + IC + 10)

AND-OR
NAND·NAND
OR·NAND
NOR·OR

In order to get a network of NOR gates we must start with the
minimum product-of-sums form of F.
Example 4.5
From the same K-map. we can also find equations for ORAND, NOR-NOR, AND-NOR and NAND-AND networks.
OR·AND
F = (/A + B)-(A + C + ID)-(A + IC + D)
= I[/(IA + B) + I(A + C + /0) + I(A + IC + D)] NOR·NOR
= I(A-/8 + IA-/C-D + IA-C-/D)
AND'NOR
= I(A*/B)*/(/A-/C*D)*/(/A*C*/D)
NAND·AND
NAND-NAND and NOR-NOR networks are very common in
industry because both the NAND and NOR gates are universal
gates: Thus, these gates are made in great quantities, making
them more available for deSigners.
A NAND-NAND network is made from a Sum of Products
(SOP) solution. The AND and OR gates of the SOP solution
are replaced by NAND gates with all the interconnections
staying the same. Variables that are input directly to the
output gate must be inverted.
A NOR-NOR network is made from a Product of Sums
solution. The OR and AND gates are replaced by NOR gates
with all interconnections staying the same. Any variables that
are input directly to the output NOR gates must be inverted.
An easy way of/orming either a NAND network from a Sum of
Products solution or a NOR network from a Product of Sums
solution is to place two inversion bubbles in series between
the two levels as demonstrated in Figure 4-7.

Multiplexers are circuits which select one of 2" input lines
using n selector lines. For example, an eight-input multiplexer
(often called a 'MUX') selects one of 2 3 input lines using three
select lines.
Example 4.6
Design an 8:1 multiplexer in SOP form by using a truth table.
SELECT

MULTIPLEXER INPUTS

OUTPUT

A

B

C

DO 01 02 03 04 05 06 07

Y

0

0

0

0

0

0

0

0
0

0

X

X

X

X

X

X

0

1

X

X

X

X

X

X

X

1

1

X

0

X

X

X

X

X

X

0

0

1

X

1

X

X

X

X

X

X

1

1

0

X

X

0

X

X

X

X

X

0

0

X

0

1

0

X

X

1

X

X

X

X

X

1

0

1

1

X

X

X

0

X

X

X

X

0

0

1

1

X

X

X

1

X

X

X

X

1

1

0

0

X

X

X

X

0

X

X

X

0

1

0

0

X

X

X

X

1

X

X

X

1

0

1

X

X

X

X

X

0

X

X

1

0

1

X

X

X

X

X

1

X

X

1

1

1

0

X

X

X

X

X

X

0

X

0

1

1

0

X

X

X

X

X

X

1

X

1

1

1

1

X

X

X

X

X

X

X

0

0

1

1

1

X

X

X

X

X

X

X

1

1

I-- 1--

L

1
0

Figure 4-8. Truth Table f.or 8:1 Multiplexer

As can be seen from the truth table A, Band C select one of
the eight multiplexer inpuls to appear on the output, Y. If A, B
and C = 011, then Figure 4-9 shows that the 03 AND. gate will
be enabled while all the other AND gates will be disabled. This
allows 03 to be 'ORed' with seven zeros and thus end up on
the output Y.

MoneIilhlcWMemorles

8-13

Logic Tutorial
A, Band C are used as control inputs to the multiplexer, this
leaves 0 as the only real variable in the problem. The 16square K-map can thus be broken up into eight one-variable
K-maps. Each map is solved for one of the eight data inputs to
the 8:1 multiplexer. The solution is shown in Figure 4-11.

DO

01

)--

02
03

~
y

D4

r-::::::

os
06

07

A

8
C

B

C

0

0

0

0

0

1

11

0

1

0

12= 10

0

1

1

13

10

MULTIPLEXER

0

1

0

0

'-

1

0

1

15

1

1

0

16

1

1

1

17 = 10

10
11

1

i5

12

0

13

0

14
15
16

0

17

=0

14 = 1

::
::-...

8:1

= 10
=1

}--

....

Figure

A

=1
=0

y

OUT

so Sl S2
ABC

Figure 4-11
4~9.

8:1 Multiplexer Circuit

Example 4.7
We will design a dual 8:1 mux in a PAL device. //
When selecting a·PAL device, several things must be considered. Will the design need registers? How many inputs and
outputs are there? Are the outputs active high or active low?
For a dual 8:1 n1ux the select lines will be shared, but the
eight data inputs to each mux are independent. Thus we need
nineteen inputs and two outputs for the design. This narrows
our choices down to one PAL device, the PAL20L2. The
output of the PAL20L2 is active low but this causes no
problems because an active high output will result by simply
inverting all the data inputs. The Boolean equations are shown
below; the complete logic diagram is on the next page.
Multiplexers have been widely used as logic devices as well
as selector circuits. A 4:1 mux can be used to realize any
three-variable function. An 8:1 mux can realize any fourvariable function.
Example 4.8
Solve the K-map in Figure 4-10 and build the circuit with an
8:1 multiplexer.

4.5 Decoders
On a multiplexer with n address lines, one of the 2" inputs is
selected to be output. On a decoder with n address lines, one
of the 2" output lines is forced either high or low, depending
on the design of the decoder. Figure 4-12 shows a truth table
for an active high 3-to-8decoder.
OUTPUT LINES

SELECT LINES

A

B

C

f

9

h

i

J

k

I

m

0

0

0

1

0

0

0

0

0

0

0

0

0

1

0

1

0

0

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

0

1

1

0

1
1
1

I··.

1

0

0

0

1

0

0

0

0

0

0

0

0

0

1

0

0

0

0

1

0

0

0

0

0

1

0

0

1

0

0

0

0

0

0

0

1

0

1

1

0

0

0

0

0

0

0

1

..

. Figure 4-12. Decoder Truth Table

y

Figure 4-10. Eight One-Variable KamaughMaps

8-14

A decoder will have as many outputs as there are possible
binary input combinations. It can be seen from Figure 4-12
that only one output can be equal to 1 at any time. The active
output represents the minterm combination that was input to
the decoder. It can also be noticed from Figure 4-12 that there
is not a combination of inputs that will give all O's on the
outputs. Many designs actually need .to be. able to make all
outputs inactive; this can be done simply by putting an enable
line in all of the output AND gates. The logic design and block
diagram for the 3-bit decoder in Figure 4-12 appears in Figure
4-13.

MonoIlthlcWMeniorles

Logic Tutorial
Logic Diagram
PAL20L2
IJ

I 2 l

4 $ 6 1

8 91011

1213141!!

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r

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....

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8·15

Logic Tutorial

82,81,80
A2, Al,AO

A

3 TO 8 OECODER

9

8
f

h

9

A
C

It

8

j

k
I

C

m

m

(a)

000 001

011

010 110 I~

101

100

1m

1

1

1

1

1

1

1

1

1

1

0

'I

0

0

11
~

0

0

0

0

0

1

0

0

1

rrn

000

0

Ir1

001

0

0

011

0

0

010

0

om

110

0

0

0

111

0

0

101

0

0

100

0

0

1

1

1

1

0

0

(b)

Figure 4-13. (a) Logic Diagram for 3-to-8 Decoder
(b) Block Diagram for 3-to-8 Decoder

B> A

1

1

0

0

0

0

0

1

0

0

rl '1

0

= IA2.82
+ IA2./A1.Bl

+ IA2./A1>/AO.BO
+ IA2./AO·B1>80
+ IA1.82.81
+ I AO.82.81080
+ IAh/AO.82.80

4.6 Magnitude Comparator
A magnitude comparator is combinatorial circuit that compares
two numbers, and puts out one of three signals: A > B, A = B
or A < B.
Example 4.9
We can design a 3-bit mag~itude comparator in a PAL device.

Of course, A

if (lot A < B and not A
(A = B) = /(B <: A)'/(B > A)

= B only

>B

Figure 4-14 (Continued)

82,81,80
A2, Al,AO

110~

111

101

100

000

0

0

0

0

0

0

0

0

001

"

0

0

0

0

0

0

0

~

1

0

~

0

0

0

0

1

t

0

0' ,0

0

0

0

000 001

011
010

011 010

110lnl 1

1

111 mJ)[

1

1 1l[1

101

lJ

1

1

100

1

1

1

0

1

,...o 1fT

[ill

0

1

0

0

1

0

0

!

The six-variable K-maps are used to produce Sum of Product
equations for A > Band B ,< A. These equations are then
used to form the two-level logic diagram of the 3-bit magnitude comparator and the equation for A = B, as shown in
Figure 4-15.

il.!..: ru..
0
L.!..
0

0

A>.
AI

AI

AIJ

A> 8

= A2./B2
+ Al./B2./B1
+ AO·/B2./B1>/BO
+,AhAO./B2·/80
+ A2.A,./Bl
+ A2.A hAO./80
+ A2.AO./B1·/BO

A:oB

.,

82

80

.>A

Figure 4-14

Figure 4-15

8·16

Logic Tutorial
The logic diagram of the 3-bit comparator shows that there
are six inputs and three outputs in the circuit. Each output is
derived from at most seven product terms. This design can fit
into a portion of a PAL16P8, as shown on page 8-18. Note
that 5 outputs· remain, which can be used for some other
functions if needed.

4.7 Adder
A binary adder takes two binary inputs, adds them, and
generates the binary sum. A full adder is the basic building
block of any adding network. A full adder is a l-bit adder with
a carry-in and a carry-out. The truth table is shown in Figure 416. The logic design and block diagram appear in Figure 4-17.

A

B

CaN

y

'IN

BC

BC

~'N
A
00
0

01

11
0

00

10

0

0
0

0

00

01

11

10

0

0

0

lEl

0

1

0

1 1[1]

1

A

10

Y =A./B./C,N + IA./S.C,N
+ A*B*CiN +./A*Bfr/C1N

(a,

A--~------------,

COUT

0

0

0

0

0

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

··0

1

0

0

1

1

0

1

0

1

1

.1

0

0

1

1

1

1

1

1

y

CI:=;:::====i=*=1Q::f:;:=L)

COUT

(b)

CIN

:=$-'

Figure 4'16. Truth Table for Full Adder

The truth table is used. to form K-maps for the outputs Y and
Cin, These simple K-maps are solved to obtain equations for Y
andCin ·

COUT
(e)

Figure 4-17. (a) Karnaugh Maps for .the Full Adder, (b) Logic
Diagram, (c) Block Diagram

A parallel 4-bit adder can be designed using four full adders.

Flgure4-1lr. Parallel 4-Bit Adder

To implement thiS circuit in a PAL device, each carry-out is
directly. input to tM.nextdigit's carry-in. Nine inputs and eight
butputs are needed. Three of the output$ (the first three carryouts) ate only needed so fheycan be fed back into the circuit
as. inputs. A PAL16L8.is the perfect PAL device for this
design. The logic diagram is.shown on page 8-19.

MonolIthic

W Memor/e.

8-17

Logic Tutorial
Logic Diagram
PAL16P8
AO I

'1123

4567

"'011

12'131415

16171119

20212223

24~2Ul,

28293031

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1

,
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1

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2

19

10
11

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12

13

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..
18

11

19

20

~U

""
23

4

J
....

18

1....

11

-

24

""
,.

./

~L>

1....

16

./

~U

1....

15

J....

14

~U

1...

13

~U

J

12

21

28
29
31

-5
32

33
34

"3631
38

BO

6

"
40
41

.....
42

43

" ~U

41

B1

7

..

,

"
"""
50

Sol
16

B2

A>B

-

••

3

1....

8

50

"

50
SI

eo

11
12
13

II

9
0123

MonoIlthIcW.emorl••

B>A

A=B

Logic Tutorial
Logic Diagram
PAL16L8
A3

1
0111

.. $ ,

I

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,,•
••,

1111''''$

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.

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81.

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Logic'Tutorial

4.8 Hazards

CD

Even though a digital network is designed correctly, it still may
have erroneous outputs at times due to hazards. Hazards
exist because physical circuits do not behave ideally. For
example, a D-type flip-flop has two outputs; 0 and 10, which
should always be complements of each other. In the real
world 0 may be switching from 1 to 0 and 10 from 0 to 1.
Unless both 0 and 10 switch at exaCtly the same time, 0 will
equal /0 for some finite amount of time. In some cases this
could cause the network to malfunction. The change in the
flip-flop output may. not· cause the steady-state output of the
network to change, but the transient OUtput may have had a
spurious change due to the non'ideal flip-flop. If, for instance,
the network's output was. the $et line of a latch, the latch
would set due to the hazard.
There are two types of hazards, static and dynamic. Static
hazards occur when the steady-state output ofanetwork is'
not supposed to change due to an input change, but a
momentary change does occur as the inputs change. This is
often referred to ass "glitch." Static hazards are qualified
further as either static 1 hazards or static 0 hazards .. Static 1
hazards exist when the steady,state output is 1, stalicO
hazards exist when the steady-state output is O.

 to <0101 >. If both Band D
changed simultaneously no temporary erroneous pulse would
appear on the output; however in the real world either B or D
would change first. The transient output would have gone to 0
asaresultofbeing momentarily in state <0100> or <0001>.
Looking at the K-map, it is easy to see function static hazards
and funCtion dynamic hazards.
The easiest way to avoid function hazards is by restricting
input changes to one variable at a time. This method is not
always possible though, since the inputs may not be prediCtable.
Logic hazards exist because of the way a function is realized.
Logic hazards can exist even if input changes are restricted to
one variable at a time.
A K-map is a very good way of locating logic hazards. When
trying to locate the static 0 and statiC 1 logic hazards on a Kmap it is only necessary to map the 1-sets orlhe O-sets.
A I-set is a product expression derived from a grouping of 1's
on the l<-map. If there are two adjacent input states that
produce a 1 onthe output. but are not covered by the same 1term, a static logic hazard exists. Logic hazards may be
eliminated by redesigning the circuit so adjacent input states
that produce ones are covered by the same 1-term.
y z

~

Figure 4-20. Dynamic Hazard

01

00

11

10

00

~z

w,X

00

01

11

10

00

if1l

011rl

There are two classifications of hazards: function hazards and
logic hazards.
Function hazards can be present when more than one input
variable changes. It is easy to see from the K-map in
Figure 4-21 why function hazards exist.

0

01

11111

'['l!J

11l!.J

lQ: =

1

10

r,-

Irl
1

10

1

;>;0;;

TBOO16Oh1

(8)

1

~

(b)

Figure 4-22 •. (a) Kamaugh Map with Two logic Hazards
(b) Karnaugh Map with No Logic Hazaf(ls

8-20

MonoilthICWMemorle8

Logic Tutorial
SET~Q

5. Sequential Logic
5.1lntroduction
In the previous section, combinatorial circuits were discussed
- circuits whose. outputs are determined completely by their
present inputs. Outputs of some networks depend not only on
their present inputs but also on the sequence of their past
inputs. These circuits are called sequential switching networks. Sequential networks must be able to remember the
past sequence of their inputs in order to be able to produce
new outputs.
In order for a sequential circuit to remember the previous
inputs, it must retain those values in some memory elements.
The most basic memory element is called a flip-flop. Flip-flops
are bistable devices with one or more inputs that affect their
outputs. The term bistable means that .theoutputs are stable
in .either of two states.
There are two types of flip-flops: unclocked .and clocked.
Unclocked flip-flops are often referred to as latches. Clocked
flip-flops are often grouped into registl[1rs.

5.2· Unclocked .Flip-Flops' - Latches
5.2.1 8·R Latch
The circuit in Figure 5-1 a is called' a SET-RESET or an S-R
latch. An S-R latch has two inputs which are used to control
the state of the latch. The rules for this type of latch are:
1. If SET = RESET = 0, then the latch remains in the same
state, and the output does not change.
2. A'1' on the SET input and a '0' on the RESET input will
make the latch SET to '1'.
3. A 'O'on the SET Input and a '1' on the RESET Input
causes the latch to RESET to '0' state.
and 10 will be. '0' at the
4. If SET = RESET = 1, ..then
same time, which is meaningless. Whe!) designing with an
S-R latch, we should remember that SET = RESET = 1 is
forbidden.
The S-R latch circuit, state table, characteristic equation and
waveforms are shown in figure 5.~1.
Latches can have more than two inputs. In Figure 5-2, we
examine a .latch circuit that has two SET terms instead of one.
The logic diagram and the tranSition table are shown.
In some applications using latches; it is del?/rable for the input
data to be effective only when another signal - usually
referred to as a control signal - is active. For these applica.
tions, the S-R latch could be modified as shown in Figure 503.
It is apparent from Figure 5'3 that tITe values of SET .and
RESET are effective only when the control signal (C) is active.
When C = 0, changes in the SET and. RESET inputs do not
have any effect on the outPUt.
Of courSe in the input of the latch dbesnot affect the output
immediately; there is a short delay for this change to appear at
the .output. ThiS delay, shown in figure 5-3(b), is cauSed
because of the propagation delays of the gales between
inpulsand .OUtputs.

°

~

Rt

at

°t+1

0

0

0

0

0

0

1

1

RESET-0-0

0

1

1

0

(8)

1

0

0

1

1

0

1

1

1

1

0

X

1

1

1

X

~

1

0

S.,R1
00

0

l!.J

01

0

0

11

X

X

10

1

1

(b)

Qt+l = S.

+ Q.*/R.

(where s..R.

= 0)

(e)

s

..

..

Q

(d)

Figure 5·1 •. $oR Latch (a) Lllgic Circuit. (b) Slate Table. (c)
CharacteristIC Equatilln (6) Waveforms

Sl~

~..
R

.• ..•.
.'

U
(a)

'..

81

82

R

°t+1

°t

:.'

0

0

0

1

X

0

Q

X

1.

0

1

0

0

1

0

X

1

t

X

1

X

1

X

1

(b)

Figure 5·2. $oR Latch with twll SET inputs (a) Lllgic diagram (b)
Slate Table

MonoIlthlc,W.Memories

Logic Tutorial
s.:..'--Q

c
R

--lJ---o"-"'"

Dt

C

at + 1

0

1

0

1

1

1

0

0

1

0

at
at

(b)

(8)
(8)

D

R ______

L

C

~r_l~____~

·· ··

Q

c

Q~

(e)

u

Figure 5-4. D-type Latch with Gate (a) Logic Circuit (b) State
Table (c) Wave'orms
(b)

Figure .5-3. 8-R Latch wlth Control (a) Logic Diagram
(b) Waveforms

5.2.2 D-type Latch
Other kinds of latches are used in sequential circuits. One of
the most popular latches is cal,led ,a delay latch, orO-type
latch. An S-R latch is modified to a O~type latch by inserting
an inverter between Sand R, and calling the input "0"
instead of "S". The Ootype latch will take the value of its input
and transfer it to the output. The advantage of the Ootype
latch over the S-R latch is that in the former only one input is
needed and there is no forbidden state. The only disadvantage of the Ootype latch is that it does not have a "no
change" condition. This condition can be provided by inserting
a control signal, C, as an input to the latch (Figure 5-4).
This configuration is probably the most widely used one, with
the control input commonly called the "Gate". Oevices with
active high gates and with active low gates are both commercially available.

5.2.3 J-K Latch
Another useful latch is the J-K latch which is shown in Figure
5-5. This latch consists of an S-R latch with two ANO gates in
front of the inputs. This is most useful be.cause J-K latches act
like S-R latches, and it is permissible to apply '1' to both
inputs simultaneously. The state table and characteristic equation for a J-K latch are also shown in Figure 5-5.

'~,,=::[t

K

R

Q

'-""""OM

(8)

$t

At

at

at + 1

0

0

0

0

.0

0

1

1

0

1

0

0

0

1

1

0

1

0

0

1
1

1

a

1

1

1

0

1

1

1

1

0

Q.+l

=J.fQ + IK.Q

(b)

Figure 5-5. J-K Latch (a) Logic Diagram (b) State Table and
Characteristic Equation

MonoIllhlcWMemor/es

Logic Tutorial
5.2.4 T-type Latch
Another type ()f latch is a triggered latch, or T·type latch,
which has only one input called T. Whenever T is high, the
latch changes state. A T·type latch is realized by connecting
both J and K to one input, T.

T~

~
(81

T

Q

Qt+1

0

0

0

0

1

1

1

0

1

1

1

0

5.3.1 Characteristic Equations
The characteristic equations for various flip-flops are summarized as follows:
= S + /R-Qt
S-R flip-flop
= J*/Qt + /K*Qt
J-K flip-flop
= T + Qt
T-type flip,flop
= D
D-type flip-flop
In the above equations Qt+l is the next state and 0, is the
present state. We can convert one flip-flop to another by
inserting gates between the inputs and the actual flip-flop.
A group of clocked flip-flops forms a register. A register is a
digital device that is used to hold several bits of information. A
register may be a combination of flip-flops and gates. The
gates control how and when the data from the, flip-flops is
transferred.
Qt+l
Qt+l
Qt+l
Qt+l

5.4 Designing Synchronous Sequential
Circuits
0,.,

= /T.O + T_/O
=T:+:O

(b)

Figure 5-6. T-type Latch (a) Logic Diagram (b) State Table and
Characteristic Equation

5~3 Clock,dflip-flops -Registers
In the' previous section, different types of latches were discussed. Clocked flip'fIOps()f the same types are available
(S-R, J-K, D and T), and the state equations are the same,
except that the output change in clocked flip,flops occurs on
the clock edge.
In general, clocked flip-flops', are more common than unplocked flip-flops, SO the word "clocked" is often left out.
Thus a, D-type flip'flopis a clocked element,whereas aD-type
latph is unclocked. Note, however, that this is common usage;
not a definition.
Figure 5-7 illustrates the difference between a D-type latch
and a D-type flip-flop.

DJ

In this section, we will familiarize ourselves with the analysis
and synthesis of synchronous sequential circuits. Analysis will
be covered first, since it will make the understanding of
synthesis easier.
The present states of a sequential circuit depend not only on
the present inputs, but also on the past statas. A sequential
circuit is constructed of flip-flops and gates. The gates form
thacombinatorial part of a sequential circuit; the flip-flops
provide the'memory of past states. A general block diagram, of
a sequential circuit is shown in Figure 5-8.
There are two basic types, ()f sequential circuit: synchronous
and asynchronous. Synchronous circuits are ,controlled by a
common clock; these types of circuits are the, easie,st to
design. Asynchronous circuits have independently clocked
flip-flops whose clock rates maY nol have any relationships to
each other. Such circuits may be faster than sychron()us
circuits, but are much harder to design.
CLOCK (IN SYNCHRONOUS CIRCUITS)

F
L
INPUT

L

o

GI-----I
C

L-____L -__

~~

____

I

P

,L

o
G

I

I OUTPUTS

C

C

r,',

~

,

,

''''''''''"

,,

~------IrFigure 5-7. comparison of a Ootype latch and a positive edge. triggered D,tyP8' flip-flop

MonolithIC

Figure 5-8. Sequential ,Circuit Block Diagram

The input c()mbinatorial logic section receives6xtarnal inputs
and feeds .information to the, flip-flops. The flip'flopshave a
feedback path back to the input combinatorial circuit. At the
rising edge of each clock pulsa the information fromtha input
combinatorial circuit is read into the flip-flops and the new

W Memories

8-23

Logic Tutofial
outputs are generated through the output combinatorial circuit.
The outputs do. not change .until the next clock edge.
Figure 5-9,shows an example of a sequential circuit.
CLOCK-------------,

before, the circuit can have four states: AB = 00. 01, 11 and
10. At this point, we try to cover transitions for one input state.
Suppose the circu.it is in the 00 state. If an X = 0 input is
applied, the next slate will be 00. If an X = 1 is applied, the
next state will be 11. The output for both. cases is Z = O.

z

PRESENT
STATE

x-........--IJ.~
Figure 5-9. Example of a Sequential Circuit

This circuit consists of two J-K flip-flops, an inverter, an AND
gate and an XOR gate. It has an external input, X, and an
external output, Z.
5.4.1 State Transition Tables
The stat~s of a sequential circuit are determined by its inputs,
the outputs and states of the flip-flops. In order to examine
these states, we should determine the input equations to the
flip-flops. From Figure 5.-9. we have:
JA=X:+:B

Z=A

Ja=X*/A

KA=/X
Ks=X
The characteristic equation for a J-K flip-flop gives:
At+l

= JA'/Q + IKA'O
= (X :+: B)'/A + X'A
= (X'/B + IX-B)·/A + X'A
= IA'/B'X +/A*.B./X + A'X

= Js*/Q + IKs·Q
= IA*/B*X + B'/X
These are called the state equations. The corresponding Kmaps are:
Bt+l

x
0

1

00

0

CD

01

1

0

11

1

0

10

0

0

A,B

At.l

At+1 8 t+1

PRESENT
OUTPUT

AS

x=o

X=1

00

00

11

0

01

11

00

0

11

01

10

1

10

00

10

1

Z

Figure 5-10. State Transition Table for Figure 5·9.

5.4.2 State Tables and State Diagrams
We can assign names to the four possible states: So = 00, SI
= 01, S2 = 11 and S3= 10. Using these assignments the
state transition table can be modified to the state table shown .
in Figure 5-11.

PRESENT
STATE

NEXT STATE
X=O

X=1

PRESENT '.'
OUTPUT Z

SO

SO

S2

0

S1

S2

SO

0

S2

S1

S3

1

S3

SO

S3

1

Figure 5·11. St.ate Table for Figure 5-9.

A state diagram can be derived using the state table. A state
diagram shows transitions between states. Each state is
represented by a circle, and the transitions between states are
shown by arrows.
The condition under which a transition occurs. is represented
by X/Z. Applying an input, X, a tra.nsition from one state to the
other takes place, and an output Z will be produced. The state
diagram for the state table in Figure 5-11 is shown in Figure 5·
12.

11,+1

Using these maps, the state transition tables for Figure 5-9
can be derived. There.are only four different combinations that
A and B can have. The next state values are derived using
these four possible combinations.
The. present state is the state of the flip·flop before the clock
pulse; the next state is the state of flip.f1op after the clock
pulse has been applied. The present output; Z, is. the output of
the sequential circuit after the clock pulse... As mentioned'

8-24

NEXT STATE

0/1

DFOOO;!lM

Figure 5-12. State Diagram for Figure 5-9

MonoIlthlcW.emories

Logic Tutorial
We have gone through a complete analysis procedure for the
previous example. This process can be summarized as follows:
1. Using a given network, determine the input equations.
2. Derive the next state equations, using the flip-flop characteristic equations:
D-type flip-flop
T-type flip-flop
+ IK*O
J-K flip-flop
0 1+1 = 8 + IR*O
8-R flip-flop
3. Derive the corresponding K-maps and transition tables.
4. ASSign state names and make the state table.
5. From the state table, draw the state diagram.
The synthesis of a sequential circuit uses the same steps, but
in reverse order. A flow chart of the procedure is shown in
Figure 5-13.
01+1
01+1
01+1

= 0
= T :+: 0
= J*/O

Figure 5-13. Flow Chart of Sequential Circuit Synthesis

5.4.3 Design Examples
Let's look at the procedure for designing sequential circuits in
more detail by analyzing some design problems. The design
steps will follow the flow diagram in Figure 5-13.
Example 5.1
We will design a clocked sequential circuit which receives an
input, X, and will produce an output Z = 1 after it has received
an input sequence of 0010 or 100.

Monolithic

Solution:
The first step is to make a state diagram. The state diagram
will start in a state designated by 80. If X = 0 is input while in
state 80, it could be the start for the 0010 sequence, so we
move to state 81. If a 1 is receive, the circuit will go to state
84, which could be the start for the 100 sequence.
When in the 81 state, Qne of two inputs could be received: X
= 0 or X = 1. If X = 0, then the circuit could still follow the
0010 sequence, because so far it has received the 00
sequence; this takes us to state 82. If X = 1, then the input
sequence would be 01 so far, which cannot follow the 0010
any more, but could be a start for the 100 sequence. Therefore under this condition the circuit would have a transition
from state 81 to 84.
While in the 84 state, if an X = 1 is received, it would stay in
the same state, because this of 11 could start a new 100
pattern. If X = 0 is received, the. 100 pattern could continue,
because 10 follows the 100 pattern.
When in the 82 state, if an X = 0 is received, it will stay in the
82 state; if X = 1, then it will have a transition from the 82 to
the 83 state. While in the 83 state, we will have a transition to
state 84 if X = 1, because the Input sequ(lnce would be 0011,
which cannot follow the 0010 sequence any more, but the 1 at
the end could be a beginning for the 100 sequence. If X =·0 is
received then the 0010 sequence is complete and an output Z
= 1 is generated. At the same time in the 0010 sequence, the
10 at the end could be the start of the 100 seqIJsnce.
Therefore we move from the 83 to the 85 state.
While in the 85 state an X = 1 will transfer the circuit from 85
to 84, and an X = 0 will cause a transition from 85 to 86.
Under this condition a Z = 1 is generated for the output,
because the 100 sequence for the inputs has occurred.
From the 86 state we. will have a transition from 86 to 82 if
X = 0, and a transition to 83 if X = 1. A state diagram of this
design is shown in Figure 5-14a.
By analyzing the state diagram, a state table is generated
(Figure 5-14b). A careful look at the state table will show that
the 82 and the 86 states are equivalent, because under X = 0
they both have a transition to state 82 with Z = 0, and under
X = 1 they would transfer to 83 with Z = O. 80 the state table
can be reduced to Figure 5-14c. After summarizing the state
table, there will be a total of six states left, so at least three
variables will be needed for the state aSSignments (2.3 = 8). In
this case only six aSSignments will be used. The state variables are deSignated by A, Band C.The state assignments
are illustrated in Figure 5-14d.

W.enlorles

8·25

Logic Tutorial
From the assignment table, we derive the K-maps for each
state. In this design the circuit is realized by J-K flip-flops,
therefore two K-maps are needed for each state variable
(shown in Figure 5-15). These can be derived from a K-map of
the transition, and the J and K characteristics in figure 5-15(a).
Q,

....

Q'+1

....
....
....

0 .... 0
1
0
1
0
1
1

0/0

J

K

0
1
X
X

x
X
1
0

(8)

ex
(8)

PRESENT
STATE

50
51
52
53
54
55
56

NEXT STATE
x=o

51
52
52
55
55
56
52

X=1

54
54
53
54
54
54
53

00

01

11

10

00

0

1

1

0

01

0

0

1

1

11

X

X

X

X

10

1

1

1

0

A,B

0'00"""

PRESENT OUTPUT
X=O

X = 1

0
0
0
0
0
0
0

0
0
0
1
0
1
0

.

""""
ex

ex

~

00

01

11

10

00

0

1

1

0

01

0

0

'1"

11

X

X

10

x

(b)

JA

A,B

00

rl
~W

Irx "7

00

01

11

10

X

X

X

X

01

X

X

X

X

11

X

X

X

X

10

0

0

0

1

x

=/B.X + B.e
(b)

ex
00

01

11

00

0

0

0

1

01

1

1

0

0

11

X

X

X

X

10

0

0

0

1

A,B

10

0/0

(e)

PRESENT
STATE

NEXT STATE
X=O

X=1

PRESENT OUTPUT
X=O

A,B

50
51
52
53
54
55

51
52
52
55
55
52

54
54
53
54
54
54

0
0
0
1
0
1

0
0
0
0
0
0

ex

ex

X = 1

00

01

11

10

~

00

01

11

10

X

X

X

X

00

0

0

0

1

00

01

X

X

X

X

01

0

0

1

1

X

X

X

X

X

X

X

X

11

X

X

X

X

11

10

0

0

0

1

10

J

a =e./x

Ka=e

(d)

(e)

Figure 5-14. Example 5.1
(a) State Diagram (b) State Transition Table (c) Reduced State
Diagram (d) Reduced State Transition Table

Figure 5-15. Karnaugh Maps for Example 5.1

8-26

Monolithic

W Memories

Logic Tutorial
cx

X~r1~-r-----------------,

A,B

00

01

11

10

00

1

0

0

0

01

0

1

0

1

11

X

X

X

X

10

1

0

0

0

'cx

~oo
11

ex

01

11

10

~

00

01

11

0

x

X

00

X

X

1

1J

xl x
x I~
x
0
x x

01

X

X

1

0

11

X

X

X

X

10

X

X

1

1

ooW
01

0

1

loB
Jc

z

W

=B.X + IB./C./X

~

10

Kc=/B+X

Figure 5-16. Circuit Diagram for Example 5.1

(d)

cx

~

00

01

11

10

00

0

0

0

0

01

0

0

0

'1

11

X

X

x Ox

10

0

0

0

Z

= A.C./X

~

1

+ B.e./X

(e)

Figure 5-15 (Continued)

Example 5.2
We will derive the state diagram,state transition table, and'
state equations of a sequential circuit which adds five to a
binary number in the range of 0000 to 1010 (decimal 0 to 10).
The inputs and outputs will be serial with the least significant
bit arriving first. This design Y{ill, be realized with J-K flip-flops.
Solution:
In Figure 5-17a, all the possible combinations for the input and
the output are shown. The sequence will start from state A. At
time 10 (when the first input is received), if X = 0, then we look
at the map for all possible combinations and notice that at to
whenever X ,= 0, the output is a 1. Thus, if the present state is
A, under X = the output is, Z = 1. On the other hand, if X = 1
the map shows that t will be a O. At time t 1, if X .;. 0 and the
sequence of the inputs has been 00 then the output would be
a 01. So in this transition Z = O. Likewise, the remaining states
of the state diagram can be derived by inspection of the table
in Figure 5-17a, The state diagram is then completed as in
Figure 5-17b. Note that the states have been labeled arbitrarily and that we have not yet determined how the states will
be implemented.
The state table is determined from the state diagram. Inspecting the state table shows that some of the states are
equivalent. States K, J, I, and H have the same next state
under X = 0 and X = 1, and produce the same outputs;
therefore K = J = I = H, and they can be replaced by the H
state. This allows us to reduce the state table to the table
shown in Figure 5-18b. There are now a total of nine states
used, so four state variables will be needed. The state
variables are called A, B, C and D. A complete state transition
table is shown in Figure 5-18c.
The K-maps are drawn from the state table. The state
equations are derived using the K-maps.

o

The state equations are derived from the K-maps. Using the
state equations, the logic diagram in Figure 5-16 is obtained.
The state equations are summarized as follows.

J A = IB'X + 'B*C

J B = C*/X

Jc

KA=/C*;X

Ks=C

KC,=/B+X

= B-X +

IB-/C-/X

MonoIlthlcW Memories

Logic Tutorial
JA
JB
JC

KA ·,1

- B-{C-O-X
- C + O-X

= B-{X + O-/X + /D-X
J o = IA-/B-/X +B-/C'
Z - IA-{B-C + IB-/O-/ X

Kc

~J~+lO:'

; KJj ~.~flx
,,'

J,

INPUT

','

OUTPUT

X

,

Z
"

X=1

C

1

0

E

0

1

F

..,..

1

-

·0

G

H

1

1

I

J

1

0

F

X=1

A

B

B

0,

C

"

,

..

X=O

X,= 0

,

i:,,' C~/X + /C-X
+ ,'/C-/O./X + Citd

,

Z

NEXT STATE
PRESENT STATE

KB - C +.O-X

t3

t2

t1

I:, to '

13

t2

·t1

to

E

0

0

0

0

,,0

0

1

;0

1,

G

" K
A

L

0

A

0

0

0

0

0

1

0

1

1

: ,0

A

A

1

1

0
0

0

1

"'0'"

0

+

H
'I

A

A

1

1

0

1

,1

1

0

1

0

., 0

0

1

0

1

0

1

1

0

1

1

1

1

.. 0

0

0

1

1

0

1

1.
1
1

1

1

1

0
1

0

1

0

1
1
0
0
1

0

0

,0

1,

1

1

1

,

.',,"

;

l'

,

0

,

1
.. 1

; 1"

"0..
0'

0
0

1
0
1

6

1

0

J
,

,

K

L

A,

t

A

1,

1

A

'-

1

-

(8)

NEXT STATE

1

Z

PRESENT STATE

A

,~,

A

A

B

X=O

X=1

C

1

0

E

0

1

~

1

-

X.= 0

X=1

B
0

C
0

G

H

1

1

E

H

H

1

0

F

F

H

L

0

0

G

A

A

0

0

H

, ',A
A

A

1

1

-

1

-

L

(b)

, F.lgUl'e 5-17. Example 5.2 ta) TnithiTable (b)

SiateDIag~m

PRESENT STATE
ABeD

0000
0001
0010
0011
0100
0101
0110
0111
1000

,

Z

Ni:XT STATE

,',

X=O

X=1

X=O

X=1

0001
0011
0101
0110
0111
0111

0010
0100

0
1

0111
1000
0000
0000

1
0
1
1
1
0
0
1

-

1

0111

0000

0000
0000

1

0
0
0
1

-

(e)

Figure 5-18. Exaniple 5.2 (a) State Tranaltlon Table (b) Reduced
Stete Table (e) Reduced Transition Table

8-28

Logic Tutorial

10

00

A,B

CO

A, ~oo

00

00

01

01

11

11
10

X =011

01
11
10

01

11

X/ X/

x x
xV
X

XVx

x

10

x

X

Yx Yx ;~
x
Yx
Yx
x/x
X/
/X

x x/

X

X =0/1

A,S · 0 0
~

00

5.5 Counters

x = 011

X·OI1
C,O

01

11

Va°VI
0

x
lYx1/"
X x
lXVXV
lYx ~~~

dB

1

X

10

VX

A,S
~
00

x

01

x

11

x

10

VX

= C + O.X

00

01

11

Yx x x

10

X

Yo x '/'XVV
Yx V X /X
Yx x x xX
0
1
/1

1

X

KS

=C + O.X

''''''''''''

TOO0250M

J c = B.IX + .D./X + O.X

Kc =.B + 10

Counters are among the most commonly used sequential
circuits. In the following sections, they are covered in detail.
A register that goes through a predetermine!:! state sequence
upon receiving an input pulse is called a counter. Counters are
one of the simplest sequential circuits, and are found in
almost all equipment containing digital logic. The sequence of
states followed determines the different types of counters
(SCD, binary, etc).
The binary counter is. one of the simplest counters. An n-bit
binary counter is a register with n flip-flops and associated
combinatorial logic that follows the sequence from 0 to 2n-l.
Example 5.3
We will look at the design of a 3-bit up/down binary counter.
There are three outputs from the binary counter: DA, DB and
DC. The input to the counter is X; the counter will increment if
X = 1, and decrement if X '" O. We will use D flip-flops for this
design.
Solution:
This circuit will have eight different states, because the 3-bit
counter cycles through 23 states. The states are called qO, q1,
q2, q3, q4, q5, q6 and q7. If X
1 each state will have a
transition to its next higher state. For example, qO will go to
qt, q1 will go to q2, and so on. If X = 0 then each state wil.1
change to its previous state. For example, q7 will go toqS, q5
to q4, and so on.
The state diagram of this design is shown in Figure 5-22a.
State transition tables, derived from the state diagram, are
shown .in Figure 5-22b. The .K-maps and the state variables
are shown in Figure 5-22c. The state equations are derived
from the K-maps. The equations are summarized as follows:
DA: '" /Ao/S·IC·/X + IA-S-C'X + MS./e + A-/S-X + A*C-/X
DB: = IS'/C-/X + IS-C' X + So/C·X + S-C-/x

=

Dc: '" Ie

A,

J D IA./B./X + B./C

Z

KD ,. B./X + C./X. + IC.X

= IA./B-C + IB.fO./X + IC./O./X + C.O

Figure 5--19. Kamaugh Maps for Example 5.2

MonoIlthIcW.e;"orie.

8·29

L09ic Tutorial

(s)

PRESENT
STATE

PRESENT 'NEXT STATE
STATE
x=o X = 1

NEXT STATE

x=o

X

=1

qO

q7

q1

000

111

001

q1

qO

q2

001

000

010

q2

q1

q3

010

001

011

q3

q2

q4

0,11

010

100

q4

q3

q5

100

011

101

q5

q4

q6

101

100

110

q6

q5

q7

110

101

111

q7

q6

qO

111

110

000

(b)

CX

C

UP

Qn

H

L

L

L

H

L

H

H

NEWQn

11

10

H

H

L

H

0

0

H

H

H

L

Q]

0

0

r""1"'

1

1

01

0

0

11

1

1J

10

o

1[1

Figure 5-21. Carry-In Table

= IA./B./C./X + IA.B.C.X
+ A-B./e + A./B.X + A-C-/X

x

C

x

00

01

11

10

~

00

01

11

00

1

0

1

0

00

1

1

0

0

01

0

1

0

1

01

1

1

0

0

11

0

1

0

1

11

1

1

0

0

10

1

0

1

0

10

1

1

0

0

I~

=IB./C./X + IB.C.X

DC:

10

= IC

+ B.C./X

(e)

Examining the above table, it is easily concluded that:
On : = On :+: carry-into On
On : = On :+: (0n-1·0n-2····00·UP)
Now that we have calculated the equation for the count-up
case, let's look at the count-down case. Borrow-out from On
to 0n-1 will be high if aU the LSBs are low and we are
counting down.
BOUT := Ian - 1*/O n - 2· .. .I00·/UP
Let's look at the following table:
UP

Qn

L

L

L

L

L

L

H

H

L

H

.. L

H

L

H

H

L

Figure 5-20. 3-Blt Up/Down Counter (a) State Diagram (b)
State Transition Tables (e) Karnaugh Maps

8·30

CARRY-IN

01

00

~

De:

CIN := °n-1·0n_2····01·00·UP
Now let's look at the following table:

00Q] 0

A,B

DA:

We can easily implement this counter using a PAL device. The
PAL device for this design will require at least three flip-flops.
Since there is no PAL device available that has only three flipflops, the best PAL device will be the PAL16R4, because it
has four flip-flops and contains the AND-OR gates needed to
realize the combinatorial circuit of the counter. The schematic
of the 3-bit up/down counter using the PAL16R4 is shown on
page 8-31. Note that there are plenty of unused inputs and
outputs for other functions if desired.
Design of a binary counter can be complicated by adding new
features to it. Counters can be made to count up or down,
load new values in, or clear the present state of the counter
and reset to 0' s.
As we try to design bigger counters, using the state tables and
K-maps becomes more difficult. In the design of the .3-bit
counter, K-maps were used. If we try .to design a counter
bigger than this, summarizing the equations will be a very
tedious process. Therefore, we try to find a general solution
for solving the counter design problem. Let's tty to write the
equation for the most significant bit (MSB) of an n-bit binary
counter (0,,).
First we look at the case where the counter is counting up.
The new value of On will depend on the carry-in from bit 0n-1
into On' If all less significant bits (LSBs) are high when we
count up, we will have a carry-in from 0n-1 into On'

Monolithic

BORROW OUT

Figure 5-22. Borrow-out Table

IFIJI Memories

NEW Qn

Logic Tutorial
Logic Diagram
PAL16R4

CLK'

....
.....
Olll

4~"

'91011

111l1.1~

1,,111'19

l021Ull

lUUUI

21111031

illilll,I~lllp~:;1""'llt-~----""

HC

XL~
~---H

:ll···~l
"

~~~____________~18

."
"

HC~'"

I

I

I

::IIR"_IF
I!

I!

I

I

i

I'

I

I

""~--------!-l

"
11

,

,

!

I!

t,

I"
I

I, I

II

,

"

I

+'-r
"'~>-'!,-I
r-1

I __

l:L

-I

HC :..;"

HC

. . . ' L:J

I

DA

v

II I

!1'1111111~")-----b[Jl0" ~DB
::It
.

HC!......t..

,I

I,

HC.!.........j..

I

I

...

~
"III'
IIR~iI'ml'~i1~!'1111~:::>--1~): ~DC
"

,

II

...

HC~'"

HcL;o..

HC

L....tr

MonoIlthlcWMemorlea

8-31

Logic ,Tutorial
So:
Qn := Qn :+: Borrow,out Qn
Qn := Qn :+: (lQn-l'/ On-2···.IQ1·/QO·/LJP)
Therefore:
Qn := Qn :+: (Qn-l ·Qn-2·· .. Q1·QO·QO·UP)
+ Qn :+: (/Qn-l'/ Qn-2 •.. ./Q1./QO/.UP)
Another'way to look at acOuntef is
formulate the followirig
statement about the nth bit of the Ifounter:
'
On should hold UNLESS all lower order bits are HI and.we
are counting UP.
'
The "UNLESS" operation is implemented by an XOR gate.
Thus this statement translates directly into
'

to.

Qn :"=,Qn :+: (Qn-l·Qn-2·.;.Ol·QO~l:JP)
This is, of course, the same equation we obtained,bylopKing
at the truth table. The expression for a. down·counterban be'
found the same way.
This formulation makes it e,asyto combine these two expres·
sions into a single e9uation for an up/downcountElr:
Qn should hold UNLESS:
All lower order bits. are HI and counting UP
OR all lower order bits are LO and NOT counting LJP.
This translates to
Eq.5.1
Qn := Qn :+: (Qn-l·Qn-2· ...• Ql.QO·UP)
+ (On-l·/ Qn-2·····/Q t.l00·/ UP)
Example 5.4
Using the solution diScussed above, let's try to deslg~ an ~-bit·
counter that can count up" cot,lnt down; RESET· and LOAD
new values into the counter. R.ESET overrides LoAD, count
and HOLD. LOAD oVerrides colmt. RESET sets all of the Qs
to O.
.

We will try to generate a general equation ..tharCanbe used for
any bit in the counter. If we take the nth bit, we have. On as
input and On as output. There .. are five operations that can
happen for any given bit: LOAD, HOLD, RESET, count up or
count dciViln.
If RESET is J:l1; then all other. oPerations are overridden.
OvE!rridin!rt~e other . operations ,is ~ufficrent to provide a LO
intothefHl>:ftop.So every prod!ictterm will contain {RESET.
We LOAD the neVil value.:!n thetounter's register if RESET is
OFF (iRESET = H). Sirlee Qn is'replaced by On if (lRESET =
H, LOAD H), the expression lhalwilt allow loading the new
value wm,beIRESET·LOAD*/D~.lnorder to be able to HOLD
the:Qn value, .we should have the following conditions: (RE·
. SEt.;., L," LOAD. = t, HOLD = H). So the expression for
',holding tlle.old value is:', '
'IRESET'/LOAD'/HOLD·Qn
,
There aret'jVo .morefunctions for the. counter; count'up and
count down. T.hese two functions have been calculated in Eq.
5.1. Usin~ this equatien and the calculation for the HOLD and
LoAD cases, the final ,equation for the nth bit Is:

=

Qn =

IRESET'LOAD'Dn

:+: /RESET*/LOAp·HOLD·UP·OO·01· ... Qn-l

+ /RE:SET' /LOAD'HOLO' IUP' IQO' /01' ...IQn-l
Using the above general equation, any largE! counter can be
designed.

Solution:'
The above operations are summarized below.
RE·
SET

LO HOLD UP

0

Q'

H

X

X

X

X

.X

L

L

X

X

0

0

L

H

H

X

X

0

L

H

L

L

X

L

H

L

H

X

8-32

ci plus

OPERA:rION

SefaliLOW
;

{.9ad 0
Hold Q

1

Q minus 1

Eq: 5.2

+ /RESET*ILOAD'/O n

' 'InCrement
Decrement .

MonoIUh/clFlJ) ',."iifor/es

PLETa Device.

Table of Contents
Contents for Section 9 ....................................................................
PLE to PROM Cross Reference Guide .................................................
Selection Guide •.......•......•...............•...........•.......................•........
PLE means Programmable Logic Element ....................•.................•..•..
Registered PLE ..................•.........••..............•.•...•..•••.............. ;......
PLEASMTM ........•.....•....•.........•...................•...•.•..•.•......•..•.....•.....
Logic Symbols ...•••••••••••.••••• ,............................................................
. ,"i; ;Speeifications' ~': .............................................................................
,,.. PLE'famlJYBlockDiagrams .; ......................... ,................................
.P.LE Programmer Reference Chart ....................................................

9·2
9-3
9-4
9-5

9·5
9-6
9-7

9·10
9·16
9·20

PLE™ Devices
PLE to PROM Cross Reference
TEMP.
RANGE

PLE
NUMBER

Mil.

MEMORY
SIZE

PROM
NUMBER

PACKAGE
16N,J,(20),(NL)

PLE5P8C

5

8

Three-State

32 x 8

63S081

PLE5P8AC

5

8

Three-State

32 x 8

63S081A

16N,J,(20),(NL)

Three-State

32 x 16

none

24NS,JS,(28),(NL)
24NS,JS,(28),(NL)

PLE5P16C

Com.

OUTPUT
TYPE

INPUTS OUTPUTS

5

16

PLE6P16C

6

16

Two-State

64 x 16

none

PLE8P4C

8

4

Three-State

256 x 4

63S141A

16N,J,(20),(NL)

PLE8P8C

8

8

Three-State

256 x 8

63S281A

20N,J,NL

PLE9P4C

9

4

Three-State

512 x 4

63S241A

16N,J,(20),(NL)
20N,J,NL

PLE9P8C

9

8

Three-State

512 x 8

63S481A

PLE10P4C

10

4

Three-State

1024 x 4

63S441A

18N,J,(20),(NL)

PLE10P8C

10

8

Three-State

1024 x 8

63S881A

24N,J,NS,JS,(28),(NL)

PLE11P4C

11

4

Three-State

2048 x 4

63S841A

18N,J,(20),(NL)

63S1681A

24N,J,NS,JS,(28),(NL)

PLE11P8C

11

8

Three-State

2048 x 8

PLE12P4C

12

4

Three-State

4096 x 4

63S1641A

20N,J,NL

PLE12P8C

12

8

Three-State

4096 x 8

63S3281A

24N,J,(28),(NL)

PLE9R8C

9

8

Register

512 x 8

63RA481A

24NS,JS,(28),(NL)

1024 x.8

63RS881A

24NS,JS,(28),(NL)

PLE10R8C

10

8

Register

PLE11RA8C

11

8

Register

2048 x 8

63RA1681A

24NS,JS,(28);(NL)

PLE11RS8C

11

8

Register

2048 x 8

63RS1681A

24NS,JS,(28),(NL)

PLE5P8M

5

8

Three-State

32 x 8

53S081

16J,W,(20),(L)

PLE8P4M

8

4

Three-State

256 x 4

53S141A

16J,W,(20),(L)
20J,W,L

PLE8P8M

8

8

Three-State

256 x 8

53S281A

PLE9P4M

9

4

Three-State

512 x 4

53S241A

16J,W,(20),(L)

PLE9P8M

9

8

Three-State

512 x 8

53S481 A

20J,F,L

PLE10P4M

10

4

Three-State

1024 x 4

53S441A

18J,W,(20),(L)

53S881A

24JS,J, W,(28),(L)

PLE10P8M

10

8

Three-State

1024 x 8

PLE11P4M

11

4

Three-State

2048 x 4

53S841A

18J,W,(28),(L),(20);(L)*

PLE11P8M

11

8

Three-State

2048 x 8

53S1681A

24JS,J,W,(28),(L)

PLE12P4M

12

4

Three-State

4096 x 4

53S1641A

20J

4096 x 8

PLE12P8M

12

8

Three-State

53S3281A

24J,W,(28),(L)

PLE9R8M

9

8

Register

512 x 8

53RA481A

24JS,W,(28),(L)

PLE10R8M

10

8

Register

1024 x 8

53RS881A

24JS,J,W,(28),(L)

PLE11RA8M

11

8

Register

2048 x 8

53RA1681A

24JS,W,(28),(L)

PLE11RS8M

11

8

Register

2048 x 8

53RS1681A

24JS,W,(28),(L)

'The PLE11 P4M is available in a 20- or 26-pin Leadless Chip Carrier

Monolithic

m

Memories

9-3

Programmable Logic Element
PLETM Ci~~uit Facility

Ordering ~ Information

Features/Ben,.fits
"
•
•
•

Programmable replacement for conventional TTL logic
Reduces Ie iniieiito/ies and simplifies ttiEiir control
Expedites and simplifies prototypirig and board layout
Saves space with O.3-inch SKINNYDIP@ packages (except
PLE12P8)

• Programmed on standard PROM programmers
• Test and simulatibn made simple with PLEASMTM software
• Low-current PNP inputs
• Thre~·state outputs
• Reliable TiW fuses guarantee >98% programming yeld

PREFIX

PLE

~

~. TJLE5 P

ACN
8

Programmable
logic Elament

1.

STD

L~.ndard
xxxx

~NUMBER OF INPUTS

= Other

PACKAGE TYPE
N - Plastic DIP
NS - Plastic SKINNYDIP
J
= Ceramic DIP
JS - Ceramic SKINNYDIP
F
-. Ceramic Solder Seal
Flat Pack
L
.. Leadless Chip Carrier

OUTPUT TYPE _ _ _--'
P = Non. Registered
A"
-' Registered
RA - Registered
Asynchronous
Enable
RS ,.; Registered
Synchronous
Enable

NL

- Plastic Leaded Ollp

W

... Cerpack

Corrier

NUMBER OF OUTPUTS
PERFORMANCE _ _ _ _- - '
Blank - Standard
A
.. Enhanced

' - -_ _ TEMPERATURE CODE
C= O·C to + 75"0
M - -55"C to + 125"C

PLE Circuit Selection Guide·
PART
NUMBER

. INPUTS

OUTPUTS

PRODUCT
TERMS

OUTPUT
REGISTERS

tpD (ns)

MAX·
25

PLE5P8

5

8

32

PLE5P8A

5

8

32

PLE5P16

5

16

32

PLE6P16

6

16

64

PLE8P4

8

4

256

30

PLE8P8

8

8

256

28

PLE9P4

9

4

512

35
30

15

..

~ ~

18
~

20

PLE9P8

9

8

512

PLE10P4

10

4

1024

35

PLE10P8

10

8

1024

30

PLE11P4

11

4

2048

- 35

PLE11P8

11

8

2048

35

PLE12P4

12.

4

4096

35

PLE12P8

12

8

4096

PLE9R8

9

8

512

8
8

35
15

PLE10R8

10

8~

1024

PLE11RA8

11

8

2048

8

15

PLE11RS8

11

8

2048

8

15

~

15

·Clock to output time for registered outputs.
Note: COmmercial limits specHied.

TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

9-4

. \-

.

"'onollthlc 1I!!.n
"'emorles InJn.U

Programmable Logic Element PLE™ Circuit Family
PLE Means Programmable
Logic Element

Registered PLE Circuits

Joining the world of IdeaLogic™ is a new generation of Highspeed PROMs which the deSigner can use as Programmable
Logic Elements. The combination of PLE circuits as logiC
elements with PAL devices can greatly enhance system speed
while providing almost unlimited design freedom.
Basically, PLE circuits are ideal. when a large number of
product terms is required. On the other hand, a PAL device is
best suited for situations when many inputs are needed.
The PLE circuit transfer function is the familiar sum of products. Like the PAL device, the PLE circuit has a single array of
fusible links. Unlike the PAL device, the PLE circuits have a
programmable OR array driven by a fixed AND array (the PAL
device is a programmed AND array driving a fixed OR array).
PRODUCT TERM AND INPUT LINES

Product Terms
Input Lines

PLE
32 to 4096
5 to 12

PAL
1 to 16
6 to 64

The PLE family features common electrical parameters and
programming algorithms, low-current PNP inputs, full Schottky
clamping and three-state outputs.
The entire PLE family is programmed on conventional PROM
programmers with the appropriate personality cards and socket adapters.

The registered PLE circuits have on-chip "0" type registers,
versatile output enable control through synchronous and asynchronous enable inputs, and flexible start-up sequencing
through programmable initialization.
Data is transferred into the output registers on the rising edge
of the clock. Provided that the asynchronous (EO) and synchronous (ES) enables are Low, the data will appear at the
outputs. Prior to the positive clock edge, register data are not
affected by changes in addressing or synchronous enable
inputs.
Data control is made flexible with synchronous and asynchronous enable inputs. Outputs may be set to the high-impedance state at any time by setting E to a High or if ES is High
when the rising block edge occurs. When Vcc power is first
applied the synchronous enable flip-flop will be in the set
condition causing the outputs to be in the high-impedance
state.
A flexible initialization feature allows start-up and time-out
sequencing with 1:16 programmable words to be loaded into
the output registers. With the synchronous INITIALIZE (is) pin
Low, one of the 16 initialize words, addressed through pins 5,
6, 7 and 8 will be set in the output registers independent of all
other input pins. The unprogrammed state of is words are
Low, presenting a CLEAR with is pin Low. With all is column
words (A3-AO) programmed to the same pattern, the is
function will be independent of both row and column addressing and may be used as a single pin control. With all is words
programmed High a PRESET function is performed.
The PLE9R8 has asynchronous PRESET and CLEAR functions. With the chip enabled, a Low on the PR input will cause
aU outputs to be set to the High state. When the CI:R input is
set Low the output registers are reset and all outputs will be
set to the Low state. The PR and CLR functions are common
to all output registers and independent of aU other data input
states.

AND

OR

PLE

Fixed

Prog

TS, Registered Outputs,
Fusible Polarity

PLA

Prog

Prog

TS, OC, Fusible Polarity

PAL

Prog

Fixed

TS, Registered Feedback 1/0
Fusible Polarity

Monolithic

OUTPUT OPTIONS

W Memories

9·5

Programmable Logic ElementPLE™ Circuit Family
PLEASMTM Software
Software that makes programmable logic easy.
Monolithic Memories has developed a software tool to assist
in designing and programming PROMs as PLE circuits. This
package called "PLEASM" (PLE Assembler) is available for
several computers including the VAXIVMS and IBM PC/DOS.

PLEASM software converts design equation$ (Boolean and
arithmetic) into truth tables and formats .compatible with
PROM programmers. A simulator is also provided to test a
design using a Function Table before actually programming
the PLE circuit.
PLEASM softWare may be requested through the Monolithic
Memories IdeaLogic Exchange.

PLE(PROM)

PAL DevIce

"INPUTS
INPUTS

,

13

V

12

7 '

7~

V

10

11

7

~

13
'OR" ARRAY
(PROGAAMMAIILE)

7

~. V

..

V

12

7

V

10

11

7

7

~

V

~

F<

F=<
F<
F<

~

F<
F<

F<

~
~

F=<

F<

~
~

F<
F=<
F=<
F<
I=<

~
~

I=<

L-I

L-,.f

WQ9

"AND" ARRAY
(PROGRAMMABLE)

03 02 01 00

9-6

"OR" ARRAY
(FIXED)

--_.
F=<
F=<
I=<

=<
F<

NOTE:·
X

~

7

"1=\

=<
=<

"AND" ARRAY
FIXED

~

03 02 01 00

- hardwired connection
= programmable connection

Monolithic.

'VVVy

W Memories

Programmable Logic Element PLET• ClrcuH Famll,
Logic Symbols
PLESP16

PLESP8lA

....

"",

Programmable Logic Element PLE™ Circuit Family

Logic Symbols
PLE10Pl

PLE12P8

9-8

PLE11P8

PLE11P4

PLE9R8

wb.o,lthit;Wi"emorieS

PLE12P4

PLE10RB

Programmable Logic Element PLET.. Circuit Family
Logic Symbols
PLE11RA8

PLE11RSS

COOl$31'"

COOt141M

Absolute Maximum Ratings
Operating

Programming

~~2~1:t~:~~::::::::::::~~r::::::::::::::::':':~~:;:::~::::::::::::::~::~;::::::'::::::::~~J~~.;~::::::::::::::::::::::::::::::::~E
"i;!f .......................,.. ,...................:.........

Storage temperature .................

Operating Conditions

:.-,65 to +J50 C

,

"
, . "
~ ·,'f
: ' i
~",.
't'f>j,,",

iitARAM~TER

SYMBOL

!..

~

.'

'".' "i
•.-1'

::,:,,'

Vee

Supply Voltage;. ,;

Operating free-air,te,mperafu~

j,

..

.

TA

...'

",

~MIN

PARAM~R

NOM

",.. ';

4.75

,.5

'::'

:0

25

,

",.: '
""'"
Electrical CharacterlstlC8':'~~Oper8!!nIlCondltlOll.
,
..
SYMBOL

COMMERCIAL

.. ,..

'

y'

MAX

75' -55

r,·

TEST CONDlllQNS ",

Low-level input vpJlagEi ,:

Gllarant~ logical lowvol~ge for all Inputs

Guarant8ed logical higl:l. voltage, for' all inputs

VIC

Input clamp volt8g'e' .

IlL

Low-level input curr!ilnt

IIH

High-level input current

High-level output voltage

MAX

5

5.5

V

25

125

·C

.,

High-level input vo~ge

VOH

NOM

.'

VIL

Low-level output voltage

UNIT

5.?S' 4.5

V IH

VOL

MILITARY
MIN

MIN

TYpt

MAX
O.S

2

UNIT
V
V

Vee - '-1IN

I; --~8rnA

-1.5

V

Vee - MAX

VI ~ 0.4V

-0.25

mA

Vee - MAX

VI - Vee

Vee - MIN

IOl - 16111A

40

I
I

Com
Mil

Com IOH - -3.2mA

Vee - MIN

0.45

jJA
V

0.5
2.4

V

. Mil IOH - -2mA
IOZl

Off-state .output current

Vee - MAX

IOZH
los

Output short-circuit. current·

Vee -.5V

Vo = 0.4V

-40

Vo - 2.4V

40

Vo - OV
5PS

'Ii

-MAX
AlNnputs
grounded;
all outputs open

lee

Supply current

Vee - MAX
.All inputs TTL;
all outputs open

~

-90
90

125

5PSA

90

125

5P16

140

1S0

6P16

150

190

SP4

SO

130

SPS

90

140

9P4

SO

130

9PS

104

155

10P4

95

140

10PS

92

160

11P4

110

150

11PS

135

1S5

12P4

130

175

12PS

150

190

9RS

130

1S0

10RS

130

180

11RAS

140

1S5

11RSS

140

1S5

t TypIcaIa at 5.OV vee and 25"<: TA.
• Not more than one output should be shorted at a time and duration of the short

-20

should not exceed one second.

jJA
mA

mA

Programmable Logic Element PLE™ Circuit Famll,
Switching Characteristics

Over Commercial Operating Conditions

tpD("8)
PROPAGATION DELAY
MAX

tpzx AND tpxz ("8)
INPUT TO OUTPUT
ENABLE/DISABLE TIME
MAX

5P8AC

15

20

5P8C

25

20

DEVICE TYpE

.'

5P16C

15

18

15

6P16C

20

8P4C

30

8peC

28

25

35

20 ....
25

9P4C

.

.

9P8C
..

10P4C

".
..

30
35

.

'

20

25

30

llP4C

35

25

35

25

35

25

llP8C '.

'.

'.'

12P4C
·c·

12P8C

Switching Characteristics

".

35

..

c

30

Over Military Operating Conditions

"

t pO<"8)
PROPAGAJION .DELAY
MAX

DEVICE TYPE
..

.c

25 i

10P8C

'.'

..

tpzx AND tpXz ("8)
INPUT TO OUTPUT
ENABLE/DISABLE TIME
MAX

5P8M

35

8P4M

40

30
30

8P8M

40

30

9P4M

45

30

9P8M

40

30

10P4M

50

30

10P8M

45

30

llP4M

50

30

11P8M

50

30

12P4M

50

30

12P8M

40

35

~11

PLE9R8
Operating Conditions
COMMERCIAL

MILITARY
SYMBOL

UNIT

PARAMETER
MIN

TYP'

MAX

MIN

TYP'

MAX

Iw

Width of clock (High or low)

20

10

20

10

ns

\prw

Width of preset or clear
(lOW) to Output (High or low)

20

10

20

10

ns

t elrr

Recovery from preset or clear
(lOW) to clock HIGH

25

11

20

11

ns

tsu

Setup time from input to. clock

35

22

30

22

ns

ts(ES)

Setup time from ES to clock

15

7

10

7

ns

th

Hold .time from input to clock

0

-5

0

-5

ns

!t,(ES)

Hold time from ES to clock

5

-3

5

-3

ns

tclrw
tprr

Switching Characteristics

Over Operatllllll Conditions and ueilllll Standard Test Load

MILITARY
SYMBOL

COMMERCIAL
UNIT

PARAMETER
MIN

TYp.

MAX

MIN

TYp.

MAX

!eLK

Clock to output delay

11

20

11

15

ns

tpR

Preset to output delay

15

25

15

25

ns

telR

Clear to output delay

18

35

18

25

ns

tpzx (ClK)

Clock to output enable time

14

30

14

25

ns

tpxz (ClK)

Clock to output disable time

14

30

14

25

ns

tpzx

Input to output enable time

10

25

10

20

ns

tpxz

Input to output disable time

10

25

10

20

ns

• Typical. at 5.0V Vee and 25'C TA.

9·12

Monolithic

IUD lllemoriea

PLE9R8
Definition of Waveforms

I.......

-----)rt·~--_---"--'H \\
~~7- ·h7S.~!1_~I

E_ _ _

..

__f

I
CLK

o
NOTES:

'VOL +0.5 V

I.
2.
3.
4.
5.

Input pulse amplitude OV to 3.0V.
Input rise and fall times 2-5ns from O.BV to 2,OV.
Input access measured at the .1.5V level.
Switch 5, is closed. CL =30pF and outputs measured at 1.5V level for all tests except tpxz and Ipzx.
Ipzx and tpZX(CLKlare measured a~the 1.5V output level with CL = 30pF.5, is open for high impedance to "\" test and closed lor high impedance
to HO" test.

Ipxz and tpXZ(CLK) are tested with CL = 5pF. 5, is open for "I" to high impedance test, measured at VOH - O.SV output level; 5, is closed for "0"
to high impedance test measured at VOL + O.SV output level.

Mono/lthlc.WMemor/es

9-13

PLE 1 OR8,11 RA8, 11 RS8

Operating Conditions
COMMERCIAL

MILITARY
SYMBOL

,

UNIT

PARAMETEA

'

MIN

TYp.

MAX

MIN

TYP·

MAX

Width of' clock (High or Low)

20

10

20

10

Setup time from inplJt to clock. (10R8)

40.

25

30

25

ns

Setup time from input to clock (11 RA8, 11 RS8)

40

28

35

28

ns

ta(ES)

Setup time from ES to clock (except 11 RA8)

15

8

15

8

ns

ta(iS)

Setup time f~om

30

20

25

20

ns

th

Hold time input to clock

0

-5

0

-5

ns

~(ES)

Hold time (ES) (except 11 RA8)

5

-3

5

-3

ns

th(iS)

Hold time (is)

0

-5

0

-.5

ns

\v
.

tsu
tsu

is to clock

Switching Characteristics

ns

Over Operallng Conditions and using Standard Test Load
,

MILITARY

UNIT
MIN

IcLK

COMMERCIAL

PARAMETER

SYMBOL

TYp·

. Clock to output delay

10

MAX

MIN

TYp·
10

20

MAX
15

ns

tpZX(CLK)

Clock to output enable time (except 11 RA8)

18

30

18

25

ns

tpXZ(CLK)

Clock to output disable time (except 11 RA8)

17

30

17

25

ns

tpzx

Input to output enable time (except 11 RS8)

17

30

17

25

ns

tpxz

Input to output disable time (except 11 RS8)

17

30

17

25

ns

• TYpical. at 5.0V Vee and 2S'C TA'

Definition of Waveforms

-______________~i-~_-ti-~-i:l------.-------/·!-=--I~t~1
130
-----J.--t..... .,Of +=1
1
i

I ...

I
I

I

Ir--+-\!--..Jr--tl---.I
CLK

i--'Pxz-l

I+-tpzx-!

~~~___-+rf;nr------~------"r-~--"~~OH-O$V
o _______-Jl'--_ _-JUJr.uv
u..l-_ _ _ _ _ _Ij\-_ _ _
-VOL +UV
--I~

NOTES:

9-14

I. Input pulse amplitude OV to 3.0V.
2. Input rise and fall time. 2-Sns from 0.8V to 2.0V.
3. Input access measured at the I.SV level.
4. Switch 5, is closed. CL - 30pF and outputs measured at I.SV level for all tests except tpzx and tpxz.
S.lpzx and IpZX(CLK) are measured at the I.SV output level with CL - 30pF. 8, is open for high impedance to "1" test and closed for high impedance
to "0" test.
Ipxz and IpXZ(CLK) are tested with CL - SpF.5, is open for "I" to high impedance test, measured at VOH - O.SV output level; 8, is closed for "0" to
high Impedance test measured at VOL + O.SV output level.

MonoIlthlcW MemorlfUI

PLE10R8. 11 RA8,11RS8
Switching Test Load

Definition of Timing Diagram
WAVEFORM

5Y

CtWIQING;

)S1

:rI

.ouTPiJT

.

R1

",...

a.* . ": "

STATE UNKNOWN

R2

MUsT iE STEADY

WILL BE STEADY

........

Definition of Waveforms·

NOTES:

Apply to eleclrlcaland switching characteristics. Typic81at S.OY Vee and 25·CTA- Measimi~~iaaiiSOl~ ~~ r~'~~igraur1!l~'
pin on the device and includes all overshoots due to system and/or tester noise. In.alIPLE.deVIceillmused.lftPUIS must be tied·to iIth8r ground or
Vee. the sedIIl! re.tstor ...q.,iI1Icifor unused Inpule. on standard TTL is NOT required kW PLE deviqes. thus using'leas parts. "Nzx .is measured at th8 1.5V output I8v8I WI1h CL • 3OpF.• 8, is open for hig~-impedanCelo "I" teat and cloSed for hig/1-I~ce 10 "0" tesL'1px2"
Is~ured C~.,:,.~pF. 8, is open for "I" to hlgh-Impedan~ teat. maa~at VOH :; O.!>¥ qUIp,,! level; 8" is closed for "O"'Io~Igh-imj:lell!lnce teal
,inea8Ured at VOl + O.SV output 18v81,
'
. .,1 'd'
•
;'

,

,

"

Block Diagrams
PLEIPIIA

A7
AI
AI
A1

••1
PIIOGItAIIIIULI

AllR4Y

11
1•
17
2

. ,au.,.
PROGRAIIMAIILE
ARRAY

AD

111

A4
A,3

1
2
3
4
I
01 02 01 04 01

•

01

7
07

I
01

........

5
4

AI

II

PI.EIN

101'.
!lOW

~

101'32
ROW
DlCODER

101'.1
COLuMN
DECODIR
A,34

Al7
A1'

AD'

1-18

101'1'

:=

32114
PIIOGIIAMIIA8LE .
ARRAY

PLE 1 OR8, 11 RA8, 11 RS8

Block Diagrams

1.8 ,.
1.7 ,.
",17
AS ,.

AI 22
AI 23
1 1 OF 14
1.7
ROW
2
DECODER
3
AS
4
A4

I4XI4
PROGRAMMABLE
NtfIAy

'"

1.1 2
1.0

1.3

1.4 5
1.3 4

1.2

1.1

1.2 3

, • • 14

PIIOGIIAIIIIMLE
AFIIIAY

5

•
7

08

.....,...
PLE11N

PLE1C1P4

PROGRAMMABLE

1 OF . .
ROW

NtfIAy

DECOOER

I4XI4

1 OF 14

ROW
DECODER

I4X1.

PROGRAMM'IIILE
ARRAY

1.10 ~8'--r_--..,

1.3 4

1OF1.
c:ou.N
DECODER

1.27

1 OF 32
COLUMN

DlCOD£R
1.1 •
1.0_5......._ _ _'"

Ii 10

14
01

13
02

12
03

11
04

Monolithic

IUIlMemeriea

9-17

PLE 1 OR8, 11 RA8, 11 RS8
Block Diagrams
PLE12P4

PLE11P8

A10 21
At 22
At 23
A7
At
M
M

128l!128 '
PROGRAMMAllLE
'ARRAY

A11 17
A10 18
At 19
48 1
A7 2

1 OF 128
ROW
DECODER

A6 :

AS

At
A2
A1
AD

ii
E2
E3

PLE12P8

A11 19
A1021
A9 22 1 OF 128
23
ROW
48 1 DECODER
A7
48 2
M 3

128.251
PROGRAMMAI\LE
ARRAY

L..--_...J

A4..!4Lr---,
A3 5
A2

A1

AD

9·18

MonoIlthlcWMemor/es

128 X 128
PROGRAMMAllLE
ARRAY

PLE 1 OR8, 11 RA8, 11 RS8

Block Diagrams
PLE11RA8

AI 23
A7 1
A8 2
AS 3

1OF32

32X 121
PROGRAMMAIIU!
ARRAY

DE~R

A10

21

A8

AI

22
23

A7

1

ROW

PROO~

A6

2

DECODER

ARRAY

AS

3

A4

4

0iS

20

12k121

1 OF 121

A4 4

A3 .J5Lr---,
A2 6
10F1.
7 COLUMN
• DECODER

A3

A2
Al

AI

CLK --':--;;~--~

E

18

01

PLE11Rsa

PLE10R8

1.10

21

AI
AI

22
23

:: !3

At 22
AI 23

1 OF 121

126 X126

ROW
DECODER

PROGRAMMABLE

AS

A4

4

64X 121

1.7
A8

2

AS

4

PROGRAMMAIIU!

ARRAY

A4

-is

20

9
10 11
13
01 02 Q3 Q4

14

os

15
Q6

,.
17
07 Q8

Monolithic

W Memories

ARRAY

PLE10R8, 11RA8, '11RS8

Monolithic Memories PLE Programmer Reference Chart
Data 1/0 Corp.
10525 Willows Rd.
N.E.
P.O. Box 97046
Redmond
WA 98073..9746

Kontron
Electronics Inc.
1230 Charleston
Rd.
Mountain View
CA 94039..7230

Stag
Microsystems Inc.
528..5 Weddell Dr.
Sunnyvale
CA 94089

Digelec Inc.
1602 Lawrence
Ave.
Suite 113
Ocean
NJ 07712

Varix Corp.
1210 E. Campbell
Rd.
Suite 100
Richardson
TX 75081

Programmer
Model(s)

" Model 19/29A/298
Model 22

Model MMP-80S

Model PPX
Model PPZ

UP803

OMNI

MMI Generic
Bipolar PLE
Personality
Module

UniPak Rev 10
UniPak II Rev 07
(Not all PLE
devices
are supported by
earlier
. UniPak revisionsj

MOD16

Zm 2000

FAM Mod. No. 12

SOURCE
AND
LOCATION

Socket Adapter(s)
and Device Code
PLE5P81
PLE5P8A

F18 P02
Model 22AAdapter 351A-064

SA3

AM110-2
Code 21

DA No. 2 Pinout
1A
Switch Pos. 0-6

63S081

PLE8P4

F18 P01
Model 22AAdapter 351A-064

SA4-2

AM130-2
Code 21

DA No. 1 Pinout

63S141

F18 P03
Model 22AAdapter 351 A-064

SA4-1

PLE8P8

F18 P08
ModeI22AAdapter 351 A-064

SA6-1

Code 21

t

63S281

PLE10P4

F18 P05
ModeI22AAdapter 351A-064

SA4

AM140-2
Code 21

DA No. 3 Pinout
1E
Switch Pos. 0-6

63S441

PLE9P8

F18 P08
ModeI22AAdapter 351A-064

SA6

Code 21

t

63S481

PLE9R8

FECP65
Model 22AAdapter 351A-074

SA31-2

Code 21

Pinout 1H
Switch Pos. 5-14

63RA481

PLE11P4

F18 P06
Model 22A'
Adapter 351A-064

SA4-4

AM140,3
Code 21

DA No. 3 Pinout
1L
Switch 5-14

63S841

PLE10R8

F18P86
Model. 22AAdapter 351A-07;4
(300 mil pkg)

t

Code 21

DA No. 64t
Switch Pos. 0-12

63RS881

PLE12P4

F18 P53
Model 22AAdapter 351 A-064

SA20

AM120-6
Code 21

DA No. 70
Switch Pos. 4-12

63S1641

PLE11RA8
PLE11RS8

F18 PA3

t

Code 21

DA No. 64

63RA1681
63RS1681

PLE11P8

F18P21

SA5-4

AM100"5
Code 21

DA NO.7

63S1681

PLE12P8

F18P63

t

Code 21

DA No., 64 Pinout
47
Switch Pos. 0-4

63S3281

"

PLE9P4

Switch Pos. 0-6
AM130-3
Code 21

DA No. 1 Pinout

63S241

10
Switch Pos. 2-14

.. and programming Information.
t Contact manufacturer for availability

9-20

18

MoneI/thlem.emor/e.

PLE Circuit Applications

Table of Contents
PLE Circuit Applications ................. ......................... ......... ...............
Table of Contents for Section 10 ....................................................•....

10-1
10-2

Random Logic Replacement ... ............... ... ........................................
Basic Gates ....... .............. ...............................•....................... ...
Memory Address Decoder ..............................................................
6-Bit True/Complement and Clear/Set Logic Functions .........................
Expandable 3-to;8 Demultiplexer .. ............... .........•..........................
Du'al 2: 1 Multiplexer . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. . . . . .
Quad 2:1 MultiplexerWith Polarity Control ...............•..........................
Hexadecimal to. Seven Seginent Decoder ..........................................
5-Bit Binary to Bcb Converter .................... .............. ......................
4-Bit BCD to Gray COde Converter ..................................................
4-Bit Gray Code to BCD ,Converter •....... ......... .............. ...................
. 8-BitPriority Encoder ..': ..'...'............................................................
4-Bit Magnitude Comparator ..........................................................
6-Bit flIIagnitude Comparator ...................................................... ....
4·Bit Magnitude Comparator with Polarity Control ............................. . ...
8-Bit Barrel Shifter . . . . . . . . . . . . . . . .. . . . . .. .. . . . . . . . .. . . . . . . . . . . . . .. . . . . .. . . . .. . . .. . . . . . . .
4-Bit Right Shifter with Programmable Output Polarity ...... .....................
8-Bit Two's Complement Conversion .........................•......................
A Portion of TimIng Generator for PAL Array Programming .....................
Timin~Generator for PAL Security Fuse Programming
...•......................

10-3
10-4
10-6
10-10
10-12
10-14
10-15
10-17
10-20
10-22
10-23
10-24
10-26
10-27
10-28
10-30
10-33
10-36
10-38
10-41

Fast Arithmetic Look-up .................................................................
4-Bit Multiplier Look-up Table .. ............ .................................. .........
ARC,T!\ngeritLook-up T!\ble ,.........................................................
Hypotenuse of a Right Triangle Look-up Table ....................................
Perimeter of a Circle Look-up Table .................................................
Period of Oscillation for a Mathematical Pendulum Look-up Table
Arithmetic Logic Unit ...•................... :, ............ :.;.: .................. :.........

10-44
10-45
10-46
10-48
10-51
10-54
10-57

Wallace Tree Compression ......................................................... ....
Seven 1-Bit Integer Row PartialProducts Adder ..............................•...
Five 2-Bit Integer Row Partial Products Adder ............................ :........
Four 3-Bit Integer Row Partial Products Adder ....................... .............
Three4-Bit "Integer Row Partial pr~ucts Adder ............................... :...

10-58
10-60
10-61
10-62
10-63

Residue Arithmetic Using PLE -Device!,

10-64

Distributed Arithmetic Using PLE Devices

10-70

Registered PLE Devices In Plpellned Arithmetic,

10-72

Monolithic WMemoriea

10-2

Random Logic Replacement

Random Logic Replacement
PROMs, as logic elements, have been providing solutions as
replacements of random logic. This is the concept of PROM
as a Programmable Logic Element (PLE) device.
The usages of PLE devices include simple multiplexer/demultiplexer / encoder/decoder, control signal generators, data
communications support like CRC, and arithmetic elements
like ALUs, multipliers, sine and inverse look-up tables, and
applications in signal processing.
The advantages of PLE devices over 551/M51 logic devices
are the lIexibility of design and the fast turnaround time which
non-programmable devices cannot offer. For example, if a
decoder is used to select between memory pages and I/O
ports, once a design is done, it will be fixed - it is not easy to
find a part to be put just in the same place without modification of PC board layout in case the designer wants to expand
the memory or to increase the I/O. For a PLE device, what is
needed is to program another PLE device and place it in the
same socket where the old part was placed. In addition, it can
allow designers to define their logic functions in a component.
The ANO-OR planar structure of the PLE circuit array lends
itself naturally to being viewed as a two-level logic circuit. The
fixed AND plane contains all possible combinations of the
literals of its inputs. Each combination (product term) is fuseconnected to each output in the programmable OR plane.
A common PLE device application in the control path is to
customize logic functions. An n input exclusive OR function is
quite commonly required in comparator and adder circuits. It
contains 2" - 1 product terms, which becomes quite large for
large values of n. Tl)erefore, it is very convenient to implement
'arge XOR functions in PLE devices.
fhe PLE logic circuit implementation of a 4-input XOR is
9hown below.

Although it seems that XOR functions may be replaced by
551s, in most applications, the XOR functions.will. not be alone
by themselves, PLE. circuits can provide ~he flexibility of
adding in additional functions without using additional packages.
.
In the data path, a PLE device can be used to implement
complex functions such as a Pseudo Random Number (PRN)
Generator. Random number sequences are useful in encoding
and decoding of information in signal processing and communications systems. They are used for data encryption, image
quantization, waveform synchronization, and white noise generation, etc.
There are many techniques for generating PRN sequences.
The most common technique, however, is to use'n' stages of
linear shift registers with feedback through a logic function.
The function f is an arbitrary function chosen for a specific
application. A most general linear function is an 'm' input XOR
(m ';;;n).

There are a number of examples in the following session
which shows how a PLE device can be used to replace 551/
M51 logic devices using PLEA5M softwarE!.
"

cd
ab
00

00

01

11

10

0

1

0

1

01

1

0

1

0

11

0

1

0

1

10

1

0

1

0

10~3

Random Logic
PLESP8
PSOOO

PLE CIRCUIT DESIGN SPECIFICATION
VINCENT COLI 10/03/83

BASIC GATES
MMI SANTA. CLARA, CALIFORNIA
.ADD 10 II 12 13 14
.DAT 01 02 03 04 OS 06 Q7 08
01.

10

02 • /10

03·

04

=

10

10

*

II

+ II

*

12

*

13

*

14

BUFFER

IO~01

INVERTER

10--1>0---02

AND GATE

IO~

11

12
13
14

+ 12

+ 13

+ 14

OR GATE

.

.'

03

~~"
~. .

04

14

05 • /10

+ /11

+ /12

+ /13

+ /14

NAND GATE

IO~'
11
12

.

.05

13
14

06

= /10 * /11 * /12 *

/13

*

/14

NOR GATE

IO~
~
11

06

14

07.

10 :+: II :+: 12 :+: 13 :+: 14

EXCLUSIVE OR GATE

11
IO~
12.
13

0--07

14

08

10,.4

=

10 :*: II :*: 12 :*: 13 :*: 14

EXCLUSIVE NOR GATE

Menellthlf:

W Memories

IO~~08

11

12
13
14

Random Logic
FUNCTION TABLE
10 11 12 13 14 01 02 03 04 05 06 07 08
1INPUT
101234

- - OOTPUTS
BUF INV AND

FROM BASIC GATES
OR NAND NOR XOR

XNOR

COMMENTS

--------------------------------------------------------------------LLLLL

L

HHHHH
HLHLH
LHLHL

H
H
L

H
L
L
H

L
H
L

L
H
H

H
L
H
H

ALL ZEROS
ALL ONES
ODD CHECKERBOARD
L
H
L
L
L
EVEN CHECKERBOARD
--------------------------------------.------------------------------H
L
L

L
H
H

L
H
H

DESCRIPTION
THIS EXAMPLE ILLUSTRATES THE USE OF PLE DEVICES TO IMPLEMENT THE
BASIC GATES: BUFFER, INVERTER, AND GATE, OR GATE, NAND GATE, NOR
GATE, EXCLUSIVE OR GATE, AND EXCLUSIVE NOR GATE.
NOTE ALSO THAT THREE-STATE OUTPUTS ARE PROVIDED WITH ONE ACTIVE LOW
OUTPUT ENABLE CONTROL (/E).
PLEASM SOFTWARE GENERATES THE PROM TRUTH TABLE FROM THE LOGIC
EQUATIONS AND SIMULATES THE FUNCTION TABLE IN THE LOGIC EQUATIONS.
BASIC
GATES
PLE5P8

MonoIlthicWMemor/es

Random Logic
PLE8P8
P500l
MEMORY ADDRESS DJ!X:ODER
MHI SANTA CLARA, CALIFORNIA
.ADD All Al2 A13 A14 A15 /MREQ
• OAT /CEl /CE2 /CE3 /CE4 /CE5 /CE6 /CE7 /CE8

PLE CIRCUIT DESIGN SPECIFICATION
ULRIK MUELLER 05/01/84

CEl - /All*/Al2*/Al3*/Al4*/Al5* MREQ

.: SELIOC:TS ADDRESS RANGE OK-2K

CE2 = All*/Al2*/Al3*/Al4*/Ai5* MREQ

SELIOC:TS ADDRESS RANGE 2K-4K

CE3

= /All*

CE4·

A12*/Al3*/Al4*/Al5* MREQ

SELIOC:TS ADDRESS RANGE 4K-6K

All* A12*/Al3*/Al4*/Al5* MREQ

SELIOC:TS ADDRESS RANGE 6K-8K

CE5

= /All*/Al2*

CE6

=

CE7

= /A1l*
= A1l*

CES

A13*/Al4*/Al5* MREQ

SELIOC:TS ADDRESS RANGE 8K-10K

A11*/Al2* Al3*/Al4*/Al5* MREQ

SELIOC:TS ADDRESS RANGE 10K-12K

A12* A13*/Al4*/A15* MREQ

SELIOC:TS ADDRESS RANGE 12K-14K

A12* A13*/Al4*/Al5* MREQ

SELIOC:TS ADDRESS RANGE 14K-16K

FUNCTION TABLE
All A12 A13 A14 A15 /MREQ /CE1 /CE2 /CE3 /CE4 /CE5 /CE6 /CE7 /CE8
ADD LINES
11111
12345

/MREQ

CHIP ENABLES
12345678

COMMENTS

----------------------------------------------------------------------LLLLL
HLLLL
LHLLL
HHLLL
LLHLL
HLHLL
LHHLL
HHHLL
XXXXX

L
L
L
L
L
L
L
L
H

LHHHHHHH
HLHHHHHH
HHLHHHHH
HHHLHHHH
HHHHLHHH
HHHHHLHH
HHHHHHLH
HHHHHHHL
HHHHHHHH

SELIOC:T ADDRESS RANGE 0-2K
SELECT ADDRESS RANGE 2K-4K
SELIOC:T ADDRESS RANGE 4K-6K
SELIOC:T ADDRESS RANGE 6K-8K
SELIOC:T ADDRESS RANGE 8K-10K
SELIOC:T ADDRESS RANGE 10K-12K
SELIOC:T ADDRESS RANGE 12K-14K
SELIOC:T ADDRESS RANGE 14K-16K
NO MEMORY SELIOC:T (/MREQ=H)

-----------------------------------------------------------------------

EIGHT

ACTIVE
LOW
CHIP
ENABLES

10-6

Monolithic

W Memorlea

Random Logic
DESCRIPTION
THIS PLE8P8 PROVIDES A SINGLE CHIP ADDRESS DOCODER FOR USE WITH MANY POPULAR
8-BIT MICROPROCESSORS SUCH AS '!HE Z80 AND 8080. THE FIVE MSB ADDRESS LINES
(All-A15) AND '!HE MEMORY REQUEST LINE (/MREQ) FROM THE Z80 MICROPROCESSOR ARE
DOCODED TO PRODUCE EIGHT ACTIVE LOW CHIP ENABLES (/CE1-/CE8) TO SEr.ECT A RANGE
OF 2K BYTES FROM A BANK OF EIGHT 2Kx8 STATIC RAMS. THIS BANK OF STATIC RAMS
WILL OCCUPY THE LOWEST 16K BYTES OF ADDRESS SPACE LEAVING THE UPPER 48K BYTE
SPACE AVAILABLE. FOR OTHER MEMORIFS AND I/O. THE PLE8P8 HAS THREE ADDITIONAL
INPUTS WHICH CAN BE RFSERVED FOR FUTURE SYSTEM EXPANSION.

MEMORY ADDRESS
DECODER
PLE8P8
VCC

CH

m
CE3
CE4
CE5

CE6

OK

UNUSED

2K
4K

UNUSED

6K

i.iiiE'Q

8K

E2

10K
12K

CE7
14K
CE8

16K

CHIP ENABLE
ADDRESS

MAP

GND

MICROPROCESSOR

Monolithic WMemorles

10·7

Random Logic
PLE8P4
PS029
6809 ADDRESS DECODER
MMI SANTA GLARA, CALIFORNIA
.ADD AS A9AlO All A12 Al3 Al4 A1S
• DAT /DRAM IIO /SRAM /PROM

DRAM = /AS *

+
+
+
+

/A9*

Al2 *
Al2*
/AlO*
A12*
/All * A12 *
/A12*

+
+
10

PLE CIRCUIT DESIGN SPECIFICATION
VINCENT COLI

Al3 * /Al4 *
A13*/Al4*
A13*/Al4*
Al3 * /Al4 *
/Al4
/Al3*/Al4

A1S
A1S
A1S
AlS

10/13/~4

SELECTS ADDRESS RANGE OOOO-BEPF

/AlS
AB* A9* A10* All* A12* A13*/A14* A15

SELECTS ADDRESS RANGE BFOO-BFFF

SRAM

=

/Al3 * Al4 * Al5

SELECTS ADDRESS RANGE COOO-DFFF

PROM

=

Al3* Al4* Al5

SELECTS ADDRESS RANGE EOOO-FFFF

FUNCTION TABLE
A8 A9 A10 All A12 Al3 A14 A15
ADDRESS LINEs
11 111.1
8901 2345

IDRAM

/DRAM

/IO' ISRAM

IIO ISRAM IPROM

IPROM

COMMENTS

------------------------------~----------------------- ----------------------

LLLL LLLL
LLLL HHLH
HHHH HHLH
LLLL LLHH
LLLL HLHH
LLLL LHHH
HHHH HHHH

L
L
H
H
H
H
H

H
H
L
H
H
H
H

H
H
H
L
L
H
H

H
H
H
H
H
L
L

OOXX
BOXX
BFXX
COXX
DOXX
EOXX
FFXX

HEX
HEX
HEX
HEX
HEX
HEX
HEX

SELECTS
SELECTS
SELECTS
SELECTS
SELECTS
SELECTS
SELECTS

DRAMS
DRAMS
I/O PORTS
SRAM
SRAM
PROM
PROM

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - _ _ _ _ _ _0_ _ _ _ _ _ - - - - _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

DESCRIPTION
THIS PLE8P4 PROVIDES A SINGLE CaIP ADDRESS DECODER FOR USE WITH MANY POPULAR
8-BIT MICROPROCESSORS SUCH AS 'l'HE MOTOROLA 6809. THIS PLE DEVICE DECODES THE
EIGHT MSB ADDRESS LINES (AB-Al5) FROM THE MICROPROCESSOR TO PROVIDE FOUR ACTIVE
LOW CHIP ENABLES (/DRAM, 110, /SRAM, AND /PROM).
THE 64K MEMORY MAP OF THE SYSTEM IS DIVIDED UP INTO FOUR SECTIONS: DRAM, IO
PORTS, SRAM, AND PROM. EACH OF THESE FOUR SECTIONS CAN CONTAIN ONE OR K:>RE
BLOCKS OF MEMORY. EACH OF THESE BLOCKS CAN START AND STOP ON ANY 256 BIT
BOUNDARY

10-8

',.",oIltblc

W Memories

Random Logic

6809 Address Decoder

PLE8P4

Block Diagram
16

~:~~ --'""'I"--~'----""ADDRESS
H--t:>-- i5iWi

8

ADDRESS

r-1-,._- iO

DECOOER t--II-I.~- SRAM

System Diagram

CHIP

ENABLES

Memory Map
~-----,64K

PROM

....---..,--t

56K

--,,~==SR=A=M=:::::t :~4K
I/O PORTS

DRAM

L..-_ _ _ _--' 0

MenoIIth/c.m·Memorles

10-9

Random Logic
PLI8P8
PLE CIRCUIT DESIGN SPECIFICATION
PS002
JOEL ROSENBERG 10/26/83
6-BIT 'l'RDB/COMPLBMEN'l' AND CLEAR/SET LOGIC ~TIONS
MMI SANTA CLARA, CALIFORNIA
.ADD 11 12 01 02 03 04 05 06
.OAT Y1 Y2 Y3 Y4 YS .Y6

Yl • /ll*/I2*/D1
+ /ll* 12* 01
+ ll*/I2

OUTPUT /01 (INVERT)
OUTPUT 01 (TRUE)
CLEAR Yl

Y2 .. /ll*/I2*/D2
+ /ll* 12* 02
+ ll*/I2

OUTPUT /02 (INVERT)
OUTPUT 02 (TRUE)
CLEAR Y2

Y3 • /ll*/I2*/D3
+ /ll* 12* 03
+ Il*/I2

OUTPUT /03 (INVERT)
OUTPUT 03 (TRUE)
CLEAR Y3

Y4 .. /Il*/I2*/D4
+ /ll* 12* 04
+ Il*/I2

OUTPUT /04 (INVERT)
OUTPUT 04 (TRUE)
CLEAR Y4

Y5 = /ll*/I2*/D5
+ /ll* 12* 05
+ ll*/I2

OUTPUT/05 (INVERT)
OUTPUT 05 (TRUE)
CLEAR Y5

Y6 .. /ll*/I2*/D6
+ /Il* 12* 06
+ Il*/I2

OUTPUT /06 (INVERT)
OUTPUT 06 (TRUE)
CLEAR Y6

FUNCTION TABLE
11 12 01 02 03 04 05 06 Yl Y2 Y3 Y4 Y5 Y6
,CON'l'ROL
7 LINES

INPUT 0
123456

OUTPUT Y
123456

LL

LHLHLH
LHLHLH

HLHLHL
LHLHLH
HHHHHH
LLLLLL

LH
HL
HH

XXXXXX
XXXXXX

D 6

COMMENTS

INVERT FUN9TION
TRUE FUNCTION
CLEAR FUNCTION
SET FUNCTION

TRUE/COMPLEMENT
AND CLEAR/SET
LOGIC FUNCTIONS

tt

11 12

SELECT 1 :4
FUNCTIONS

10-10

1-7L-H>-;"'-y

Random \ Logic
DESCRIPTION
THIS PLE8P8 IS A 6-BIT TRUE/COMPLEMENT AND CLEAR/SET LOGIC FUNCTIONS. THE
CONTR:>L LINES (n AND 12) SEL!X:T ONE OF FOUR LOGIC FUNCTIONS FOR THE 6-BIT
INPUT DATA (01-06) AND THE 6-BIT OUTPUT FUNCTION (Y1-Y6).
WHEN n IS FALSE (neLOW) THE FUNCTION IS INVERT IF 12 IS FALSE (I2-LOW) OR
TRDE IF 12 IS TRUE (I2=HIGH).
WHEN Il IS TRUE (n=HIGH) THE FUNCTION IS CLEAR IF 12 IS FALSE (I2=LOW) OR SET
IF 12 IS TRUE (I2=HIGH).
THE PLE8P8 ALSO FEATURES THREE-STATE OUTPUTS WITH TWO ACTIVE LOW OUTPUT ENABLE
CONTR:>LS (/El AND /E2).

Il

12

01-06

L
L
H
H

L
H
L
H

0
0

Y1-Y6

FUNCTION

--------------------------------------X
X

/0
0
H
L

INVERT
TRUE
CLEAR
SET

6-BIT TRUE/COMPLEMENT
ZERO/ONE LOGIC FUNCTIONS
PLESP8

Monolithic

W Memories

10-11

Random Logic
PLE5P8
P5003
EXPANDABLE 3-''1'0- 8 Dm.IDLTI PLEXER
lOll SANTA CLARA, CALIFORNIA
.ADD SO S1 S2 DI PO
.DAT YO Y1 Y2 Y3 Y4 Y5 Y6 Y7
po.

YO

Yl

PLE CIRCUIT DESIGN SPECIFICATION
~K LEE 04/15/84

+ /po •
+/po
+/po
+/po

DI • /S2 • /S1 • ISO
DI
• S2
S1
• SO

ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE

HIGH, SELECT 0
LOW, DI INACTIVE
LOW, SELECT 4-7
LOW, SELECT 2,3,6,7
LOW, SELECT 1,3,5,7

PO*
+ /po •
+/po
+/po
+/po

DI • /S2 • /S1 • SO
DI
• S2
SI
• ISO

ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE

HIGH, SELECT 1
LOW, DI INACTIVE
LOW, SELECT 4,5,6,7
LOW, SELECT 2,3,6,7
LOW, SELECT 0,2,4,6

po.

DI • /S2 • S1 • ISO
DI
• S2
• /SI
• SO

ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE

HIGH, SELECT 2
LOW, DI INACTIVE
LOW, SELECT 4-7
LOW, SELECT 0,1,4,5
LOW, SELECT 1,3,5,7

DI • /S2 • S1 • SO
DI
• S2
• /S1
• ISO

ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE

HIGH, SELECT 3
LOW, DI INACTIVE
LOW, SELECT 4-7
LOW, SELECT 0,1,4,5
LOW, SELECT 0,2,4,6

DI • S2 • /S1 • ISO
DI
• /S2
• S1
• SO

ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE

HIGH, SELECT 4
LOW, DI INACTIVE
LOW, SELECT 0-3
LOW, SELECT 2,3,6,7
LOW, SELECT 1,3,5,7

DI • S2 • /S1 • SO
DI
• /S2
• S1
• ISO

ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE

HIGH, SELECT 5
LOW, DI INACTIVE
LOW, SELECT 0-3
LOW, SELECT 2,3,6,7
LOW, SELECT 0,2,4,6

DI • S2 • S1 • ISO
DI
• /S2
• /S1
• SO

ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE

HIGH, SELECT 6
LOW, DI INACTIVE
LOW, SELECT 0-3
LOW, SELECT 0,1,4,5
LOW, SELECT 1,3,5,7

DI • S2 • S1 • SO
DI
• /S2
• /S1
• ISO

ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE

HIGH, SELECT 7
LOW, DI INACTIVE
LOW, SELECT 0-3
LOW, SELECT 0,1,4,5
LOW, SELECT 0,2,4,6

Y2

+ /po •
+/po
+/po
+ /po
po.

Y3

+ /po •
+/po
+/po
+ /po
po.

Y4

+ /po •
+/po
+/PO
+/po
po.

Y5

+ /po •
+/po
+/po
+ /po
po.

Y6

+ /po •
+/po
+/PO
+ /po
po.

Y7

+ /PO •
+/po
+/po
+ /po

10-12

•

•

MonO/ithicWMemories

Random Logic
FUNCTION TABLE
PO DI S2 S1 SO Y7 Y6 Y5 Y4 Y3 Y2 Yl YO

yyyyyyyy

SSS
1PO DI 210

76543210

COMMENTS

-----------------------------------------H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L

XXX
LLL
LLH
LHL
LHH
HLL
HLH
HHL
HHH
XXX
LLL
LLH
LHL
LHH
HLL
HLH
HHL
HHH

L
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L

LLLLLLLL
LLLLLLLH
LLLLLLHL
LLLLLHLL
LLLLHLLL
LLLHLLLL
LLHLLLLL
LHLLLLLL
HLLLLLLL
HHHHHHHH
HHHHHHHL
HHHHHHLH
HHHHHLHH
HHHHLHHH
HHHLHHHH
HHLHHHHH
HLHHHHHH
LHHHHHHH

DATA INPUT = 0
SELECT OUTPUT 0
SELECT OUTPUT 1
SELECT OUTPUT 2
SELECT 'OUTPUT 3
SELECT OUTPUT 4
SELECT OUTPUT 5
SELECT OUTPUT 6
SELECT OUTPUT 7
DATA INPUT
0
SELECT OUTPUT 0
SELECT OUTPUT 1
SELECT OUTPUT 2
SELECT OUTPUT 3
SELECT OUTPUT 4
SELECT OUTPUT 5
SELECT OUTPUT 6
SELECT OUTPUT 7

EXPANDABLE
3-TO-8 DEMULTIPLEXER
PLE5P8

=

-----------------------------------------DESCRIPTION
mIS PLE5P8 IMPLEMENTS AN EXPANDABLE 3-TO-8 DEMULTIPLEXER. THE DEVICE
DEMULTIPLEXES 'lHREE SELECT INPUT SIGNALS (S2-S0) INTO EIGHT OUTPUTS {Y7-YO}
USING THE INPUT DI WITH POLARITY SELECT PO. SINCE THE DEVICE HAS THREE-STATE
OUTPUTS, IT CAN BE EXPANDED USING THE ACTIVE LOW ENABLE PIN L PINS(/J;:l AND IB2).
"
INPO'l'
AS-AO

·~.G()~AIU~ S'.r~S
BS...B9
·SQ':.;"B:. LT .CT'
.
.

O~TION'

'.
"
.
'
------------::-~':".,.-~~~~~.":"":.-~--""'"'-~~~~:,-::~-.;7':'~\;--;:!"":;:-;:~,...7~---.-~----

-, B

B

L

L

A NOT -,B,.

,E!.

R
B

x·.

A
,A

LT

A

GT

8

L

. ~; . L B
.

B.
,L

.(

L,~~,.A.;EQQM'l'OiB
~,~AN9'1' .EQW'Alt. TOB

L'
R

COMPARE A ,LESS TSAN'B
~
'

'

A'GJlBATBR ..TJfAN;8
,

"

",

,":

--------~------~~-,------------~~;--~~::-----:-----:---~----------~-

1ti;.B ,

Random Logic
PLE CIRCUIT DESIGN SPECIFICATION
PLE9P4
OOLI/MUELLER 09/09/84
P5011A
4-BIT MAGNITUDE OOMPARATOR WITH POLARITY CONTROL
HMI SANTA CLARA, CALIFORNIA
.ADD AO Al A2 A3 BO Bl B2 B3 POL
.DAT EQ NB LT GT
Al: * :Bl * POL *
Al:+:Bl*/POL *

AO:*:BO* POL
AO:+:BO*/POL

A EQ B
A /EQ B

NE" A3:+:B3* POL + A2:+:B2* POL + Al:+:Bl* POL +
+ A3:*:B3*/poL + A2:*:B2*/POL + Al:*:B1*/POL +

AO :+:BO* POL
AO: * :BO* /POL

A NEB
A /NEB

EQ= A3:*:B3* POL *
+ A3:+:B3*/poL *

LT ..
+
+
+
+
+
+
+
+

/A3 * B3* POL
A3:*:B3* POL
A3:*:B3* POL
A3:*:B3* POL
A3 */B3*/poL
A3:*:B3*/POL
A3:*:B3*/POL
A3:*:B3*/POL
A3:*:B3*/POL

GT'"
+
+
+
+
+
+
+
+

A3 */83* POL
A3:*:B3* POL
A3:*:B3* POL
A3:*:B3* POL
/A3 * B3*/POL
A3:*:B3*/poL
A3:* :B3*/poL
A3:*:B3*/poL
A3:*:B3*/poL

A2:*:B2* POL *
A2:+:B2*/POL *

* /A2 * B2* POL
* A2:*:B2* POL * /Al * B1* POL
* A2:*:B2* POL * Al:*:B1* POL * /AO * BO* POL
*
*
*
+

A2 */82* /POL
A2:*:B2*/POL * Al */81*/POL
A2:*:B2*/POL * Al:*:Bl*/POL * AO */80* /POL
A2:*:B2*/poL + Al:*:Bl*/poL + AO:*:BO*/POL

*
*
*

A2 */82* POL
A2:*:B2* POL *
A2:*:B2* POL *

Al */81* POL
Al:*:Bl* POL *

AO */80* POL

* /A2 * B2*/POL
* A2:*:B2*/POL * /Al * Bl*/POL
* A2:*:B2*/POL * Al:*:B1*/POL * /AO * BO*/POL
+ A2:*:B2*/poL + Al:* :Bl* /POL + AO:*:BO*/POL

A3
A2
Al
AO
A3
A2
Al
AO
A

LT
LT
LT
LT
/LT
/LT
/LT
/LT
/LT

B3
B2
Bl
BO
B3
B2
Bl
BO
B

A3 GT B3
A2 GT B2
Al GT Bl
AO GT BO
A3 /GT B3
A2 /GT B2
Al /GT B1
AD /GT BO
A /GT B

DESCRIPTION
THIS PLE9P4 OOMPARES TWO 4-BIT NUMBERS (A3-AO AND B3-BO) TO ESTABLISH IF THEY
ARE EQUAL (A EQ B), NOT EQUAL (A NE B), LESS THAN (A LT B), OR GREATER THAN
(A GT B) • THE OOMPARISON STATUS IS REPORTED WITH ACTIVE-HIGH POLARITY (EQ,
NE, LT, GT) WHEN 'mE POLARITY CONTROL INPUT 'IS TRUE (POL=H) AND WITH ACTIVE-LOW
POLARITY (/EQ, /NE, /LT, /GT) WHEN THE POLARITY CONTROL INPUT IS FALSE (POL=L).
THE PLEap4 ALSO FEATURES THREE-STATE OUTPUTS WITH ONE ACTIVE-LOW OUTPUT ENABLE
CONTROL PIN (/E).
OPERATIONS TABLE:
INPUT NUMBERS
A3-AO
B3-BO

POLARITY
POL *

COMPARISON STATUS
EQ NE LT GT

OPERATION

------------------------------------------------------------------------------A
A
A
A

EQ
NE
LT
GT

B
B
B
B

H

H
L
L

H

L

H

H

L
H

H
H

L

L

X
H

X
L
H

L

COMPARE
COMPARE
COMPARE
COMPARE

A
A
A
A

EQUAL TOB
NOT EQUAL TO B
LESS THAN B
GREATER THAN 13

------------------------------------------------------------------------------* COMPARISON STATUS WILL BE ACTIVE-LOW (I.E. , /EQ, /NE, /LT, /GT) WHEN POL=L.

10-28

Monolithic

W llllemories

Random Logic

4-81t Magnitude Comparator
with Polarity Control

PLE9P4

Block Diagram
EQ

-r~

4-B1T
INPUT

NUMBERS

4-BlT
MAGNITUDE
COMPARATOR
WITH
POLARITY
CONTROL

NE
COMPARiSON
STATUS
LT
GT

POL

i

,-

10;.29

Random Logic
PLEllP8
P5013
8-BIT BARREL SHIFTER
MMI SANTA CLARA, CALIFORNIA
.ADO DO 01 02 03 04 05 06 07 SO Sl S2
.OAT 00 01 02 03 04 05 06 07
00

= /SO*/Sl*/S2*

DO
01
02
03
04
05
06
07

SHIFT
SHIFT
SHIFT
SHIFT
SHIFT
SHIFT
SHIFT
SHIFT

0
1
2
3
4
5
6
7

PLACES
PLACES
PLACES
PLACES
PLACES
PLACES
PLACES
PLACES

01
02
03
04
05
06
07
DO

SHIFT
SHIFT
SHIFT
SHIFT
SHIFT
SHIFT
SHIFT
SHIFT

0
1
2
3
4
5
6
7

PLACES
PLACES
PLACES
PLACES
PLACES
PLACES
PLACES
PLACES

02
03
04
05
06
07
DO
01

SHIFT
SHIFT
SHIFT
SHIFT
SHIFT
SHIFT
SHIFT
SHIFT

0
1
2
3
4
5
6
7

PLACES
PLACES
PLACES
PLACES
PLACES
PLACES
PLACES
PLACES

50*/51*/52*
/50* 51*/52*
50* Sl*/S2*
/50*/51* 52*
SO*/Sl* 52*
/50* 51* 52*
50* 51* 52*

03
04
05
06
07
DO
01
02

SHIFT
SHIFT
SHIFT
SHIFT
SHIFT
SHIFT
SHIFT
SHIFT

0
1
2
3
4
5
6
7

PLACES
PLACES
PLACES
PLACES
PLACES
PLACES
PLACES
PLACES

= /50*/51*/52*
+ SO*/Sl*/S2*
+ /50* 51*/52*
+ 50* 51*/52*
+ /50*/51* 52*
+ SO*/Sl* 52*
+ /50* 51* 52*
+ 50* 51* 52*

04
05
06
07
DO
01
02
03

SHIFT
SHIFT
SHIFT
SHIFT
SHIFT
SHIFT
SHIFT
SHIFT

0
1
2
3
4
5
6
7

PLACES
PLACES
PLACES
PLACES
PLACES
PLACES
PLACES
PLACES

+
+
+
+
+
+
+

01

50*/51*/52*
/50* 51*/52*
50* 51*/52*
/50*/51* 52*
50*/51* 52*
/50* 51* 52*
50* 51* 52*

= /50*/51*/52*
+
+
+
+
+
+
+

04

SO*/Sl*/S2*
/50* 51*/52*
50* 51*/52*
/50*/51* 52*
50*/51* 52*
/50* 51* 52*
50* 51* 52*

= /SO*/Sl*/S2*
+
+
+
+
+
+
+

03

SO*/Sl*/S2*
/SO* Sl*/S2*
SO* Sl*/S2*
/SO*/Sl* S2*
50*/51* 52*
/50* 51* 52*
50* 51* 52*

= /50*/51*/52*
+
+
+
+
+
+
+

02

PLE CIRCUIT DESIGN SPECIFICATION
VINCENT COLI 06/12/84

10-30

MonO/lth/cm Memories

Random LogiC
DESCRIPTION
THE 8-BIT BARREL SHIFTER, IMPLEMENTED IN A PLEllP8, ROTATES EIGHT BITS OF DATA
(D7-DO) A NUMBER OF LOCATIONS INro THE OUTPUTS (07-00) AS SPECIFIED BY THE
3-BIT BINARY ENCODED SHIFT CONTROL LINE (S2-S0). THE THREE-STATE OUTPUTS ARE
IN A HIGH-Z STATE WHEN ANY ONE OF THE 'lW0 OUTPUT ENABLE PINS (fEl OR /El) ARE
HIGH.
A POSSIBLE UPGRADE VERSION OF THIS DESIGN IMPLEMENTED IN A'PLE12P8 COULD
INCLUDE A DIRECTION CONTROL LINE. THIS CONTROL LINE PERMITS THE 8-BIT BARREL
SHIFTER ro ROTATE DATA IN EITHER DIRECTION (LEFT OR RIGHT).
8-BIT BARREL SHIFTER
PlE11P8

00-----...---"---00
01~
01
8 BIT

I~~~

02:

8-BIT

:~I~~

D3'

06__

02

8-BIT

g! O~
05

08

07 _ _......,..-,-...,.....-_07

t it

so 5152
-........-,

3-SIT5HIFT
CONTROLUNE

MonoIlthlcWMemorle$

10-31

Random Logic
05 = /SO*/S1*/S2* 05
+ SO*/S1*/S2* 06
+ /SO* S1*/S2* 07
+ SO* Sl*/S2* 00
+ /SO*/S1* S2* 01
+ SO*/S1* S2* D2
+ /SO* S1* S2* D3
+ SO* S1* S2* D4

SHIFT
SHIFT
SHI.FT
SHIFT
5HIFT
SHIFT
SHIFT
SHIFT

0
1
2
3
4
5
6
7

PLACES
PLACES
PLACES
PLACES
PLACES
PLACES
PLACES
PLACES

06 = /SO*/S1*/S2*
+ 50*/51*/52*
+ /SO* 51*/S2*
+ 50* 51*/S2*
+ /SO*/S1* S2*
+ SO*/S1* S2*
+ /SO* S1* S2*
+ 50* S1* 52*

D6
D7
DO
01
D2
D3
D4
05

5HIFT
5HIFT
SHIFT
SHIFT
SHIFT
SHIFT
SHIFT
5HIFT

0
1
2
3
4
5
6
7

PLACES
PLACEs
PLACES
PLACES
PLACES
PLACES
PLACES
PLACES

= /SO*/51*/S2*

D7

SHIFT
5HIFT
SHIFT
SHIFT
5HIFT
SHIFT
SHIFT
SHIFT

0
1
2
3
4
5
6
7

PLACES
PLACES
PLACES
PLACES
PLACES
PLACES
PLACES
PLACES

07

+ SO*/S1*/52* DO

+ /SO* S1*/52*
+ 50* S1*/S2*
+ /50*/51* 52*
+ 50*/51* 52*
+ /SO* S1* S2*
+ SO* S1* 52*

01
D2
03
04
05
D6

FUNCTION TABLE
52 51 SO D7 D6 D5 04 D3 D2 D1 DO 0706 05 04 03 02 01 00
INPUT DATA
DDDDDDDD
76543210

OUTPUT DATA
76543210

COMMENTS

LLH

HLLLLLLL
HLLLLLLL
HLLLLLLL
HLLLLLLL
HLLLLLLL
HLLLLLLL
HLLLLLLL
LHHHHHHH
LHHHHHHH

LHL

LHHHHHHH

LHH
HLL

LHHHHHHH
LHHHHHHH
LHHHHHHH

LHLLLLLL
LLHLLLLL
LLLHLLLL
LLLLHLLL
LLLLLHLL
LLLLLLHL
LLLLLLLH
LHHHHHHH
HLHHHHHH
HHLHHHHH
HHHLHHHH
HHHHLHHH
HHHHHLHH
HHHHHHLH
HHHHHHHL

BARREL
BARREL
BARREL
BARREL
BARREL
BARREL
BARREL
BARREL
BARREL
BARREL
BARREL
BARREL
BARREL
BARREL
BARREL
BARREL

~5HIFT
~

~

55S
210

oooooooo

---------------------------------------------------------------------LLL
HLLLLLLL
HLLLLLLL
LLH

LHL
LHH
HLL
HLH
HHL

HHH
LLL

HLH

HHL
HHH

LHHHHHHH

LHHHHHHH

SHIFT
SHIFT
SHIFT
SHIFT
SHIFT
SHIFT
SHIFT
SHIFT
SHIFT
SHIFT
SHIFT
SHIFT
SHIFT
SHIFT
SHIFT
SHIFT

ONE
ONE
ONE
ONE
ONE
ONE
ONE
ONE
ONE
ONE
ONE
ONE
ONE
ONE
ONE
ONE

HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW

0
1
2
3
4
5
6
7

PLACES
PLACES
PLACES
PLACES
PLACES
PLACES
PLACES
PLACES
o PLACES
1 PLACES
2 PLACES
3 PLACES
4 PLACES
5 PLACES
6 PLACES
7 PLACES

---------------------------------------------------------------------T80._

10-32

Monolithic

un NIemorIea

Random Logic
PLE CIRCUIT DESIGN SPECIFICATION
PLEllP4
PS014
CHRIS JAY 05/30/84
4-BIT RIGHT SHIFTER WITH PROGRAMMABLE OUTPUT POLARI'lY
MMI LTD., FARNBOROUGH, U.K •
• ADD SO SI rNV DO Dl D2 D3 D4 os D6 /EN
.DATOo 01 02 03

00·

DO*/SO*/Sl*/INV* EN
/DO*/SO*/SI* INV* EN
Dl* SO*/SI*/INV* EN
/Dl* SO*/SI* INV* EN
D2*/SO*o.SI*jINV* EN
+ /D2*/SO*SI* INV*EN
+ D.3* SO*S1fr/INV*EN
... /D3* SO*" Sl*INV* . EN

+
+
+
+

rSELl!X:T INPUT
SELl!X:T INPUT
SELl!X:T INPUT
J SELl!X:T' INPUT
SELl!X:T'INPUT
SELl!X:T .INPUT
SELl!X:T INPUT
SELl!X:T INPUT

DO
/DO
Dl
/Dl
D2
/D2
D3
/D3

01- Dl*/SO*/SI*/INV* 'EN
+/Dl*/SO*/S1*- INV* EN
+ D2* SO*/SI*/INV* EN
+ /D2* SO*/sl* INV* EN
+ D3*/SO* SI*/INV*EN
+ /D3*/SO* SI* INV* EN
+ D4* SO*SI*/INV* EN
+ /D4* SO* SI* INV* EN

SELl!X:T
SELl!X:T
SELl!X:T
SELl!X:T
SELl!X:T
SELl!X:T
SELl!X:T
SELl!X:T

02 -

SI*/INV* EN
S1* INV* EN
SI*/INV*EN
S1* INV* EN

SELl!X:T INPUT
SELl!X:T INPUT
SELl!X:T INPUT
SELl!X:T INE\QT
SELl!X:T • INPUT
SELl!X:T .INPUT.
SEL~T INPUT
SELl!X:T INPUT

D2
/D2
D3
/D3
D4
/D4
DS
/DS

D3*/SO*/SI*/INV* EN

J SELl!X:T INPUT

+ /D3*/SO*/SI* INV* EN

SELl!X:T INPUT
SELl!X:T INPUT
SELl!X:TINPUT
SELl!X:T . INPUT
SELl!X:T INPUT
SELl!X:T INPUT
SELl!X:T INPUT

D3
/D3
D4
/D4
DS
/DS
D6
/D6

D2*/SO*/SI*/INV* EN

+ /D2*/SO*/SI* INV* EN
+

D3* SO*/SI*/INV* EN

+ /D3* SO*/SI* INV* EN.
+
+
+
+
03 =

D4*/SO*
/04*/SO*
DS* SO*
/DS* SO*

D4* SO*/S1*/INV* EN
/D4*SO*/SI* INV*EN
+. DS*/SO* SI*/INV* EN
+ /DS*/SO* SI* INV* EN
+ D6* SO* SI*/INV* EN
+ /D6* SO* SI* INV* EN

+
+

J

1

INPUT Dl
INPUT /Dl
INPUT D2
INPUT /D2
INPUT D3
INPUT /D3
INPUT D4
INPUT. /D4

10;.33

Random Logic
FONC'l'ION TABLE

IBN

S1

so

INV D6 D5 D4 »3 D2 D1 DO .0302 01 00

1-coNTROLI
1E S S N
1N 1 0 V

11

- INPUT

DATA-

DDDDDDD

OUTPUTS
0000

6543210

3 2 1 0

COMMENTS

--------------~----~-------------------~---------~-~~--------~--~--~--~~-.
H

L
L
L
L
L
L
L
L

X X
L L
L H
HL
H H
L L
LH
H L
HH

X
L
L
L
L
H
H
H
H

xxxx x x X

L L LHHHH
L LLHHHH
L LLHHHH
L LLHHHH
LLLHHHH
L L.r. H H H H
L. L LHHHH
LLLHHHH

LL L L
H H H H
L H H·H
LLHH
LLLH
L L L L
H L L L
H H L L
H H H L

"TEST ENABLE, OUTPUTS GO· LOW '
SHIFT COUNT '" 0, TRUE' POLARI~
SHIFT COUNT .'. 1, TRUE POLARITY:
SHIFT.COUNT = 2, TRUE POLARITY.'
SHIFT Cot1NT .. 3, TRUE' POLARIT!'
S.HIFT COUNT .. 0, COMPPOLARI~
SHIFT COUNT ... 1, COMPPOLARI~ ,
2, COMP POLARITY
SHIFT COUNT
3, COMP POLARI~ .
SHIFT'COUNT

=
=

=

...

...

=

...

--

------------------------------------------~~ ----~.,..'":'"' ~------- 7"":------.--,-~'~"

11),.34

,.

Random Logic
DESCRIPTION
THIS PLEllP4 IMPLEMENTS A 4-BIT RIGHT SHIFTER WITH PROGRAMMABLE OUTPUT
POlARITY. THE SHIFTER CAN RIGHT SHIFT SEVEN BITS OF DATA, FOUR BITS AT A
TIME. THE SEVEN DATA INPUTS (D6-DO) ARE SHIFTED 0, 1, 2, OR 3 LOCATIONS AS
DETERMINED BY THE 2-BIT SHIFT CONTROL LINE (S1-S0). THE SHIFTED DATA IS THEN
DIRI!X:TED TO THE FOUR OUTPUTS (03-00).
THE OUTPUT DATA IS NONINVERTED (O"D) WHEN INV=L AND INVERTED (O=/X» WHEN
INV=H. THE OUTPUTS ARE FORCED LOW (O=L) WHEN /EN=H RFGARDLESS OF OTHER
INPUTS. THE PLE1;LP4 ALSO FEATURES THREE-STATE OUTPUTS WITH ONE ACTIVE LOW
OUTPUT ENABLE (IE).
A POSSIBLE UPGRADE VERSION OF THIS DESIGN IMPLEMENTED IN A PLE12P4 COULD
INCLUDE A DIRI!X:TION CONTROL LINE. THIS CONTROL LINE PERMITS THE 4-BIT RIGHT
SHIFTER TO SHIFT DATA IN EITHER DIRl!X:TION (LEFT OR RIGHT).
OPERATIONS TABLE:

lEN

INV

S1-S0

D6-DO

03-00

OPERATION

----------~--~-------~-------~--~~--------------~-------~-~~----~----~
X
X
H
X
DISABLE OUTPUTS LOW
L
L
L
N
SHIFT (D)
SHIFT NONINVERTED·· DATA nR- PLACES
D
L
H
N
D
SHIFT (/X»
SHIFT
INVERTED DATA nNw PLACES

,4-BIT RIe'lHT SHIFTER
WITH PROGRAMMABLE

OUTPUT POLARIlY

SEVEN
DATA

I

~__:.-:;,

02..,..--+
03__

SHIFTER
WITH

00)

01

FOUR
DATA

INPUTS 04 _ _ PROGRAMMABLE H-D-02 OUTPUTS

05__

OUTPUT

06__

POLARITY

03

i iso i

-S1

INV

SHIFT
CONtROL
UNE

10·35

Random Logic
PLE8P8

. PS01S
8-BIT 'lWO'S COMPLEMENT CONVERSION
MMI BaM, CALIPORNIA
.ADD DO 01 02 D3 D4 OS D6 D7
.D~ YO Y1 Y2 Y3 Y4 YS Y6'Y7

PLE CIRCUIT DESIGN SPECIFICATION
MIKE VOGEL 11/28/83

YO • DO

CONVERT 1ST BIT (LSB)

Yl • D1 :+: DO

CONVERT 2ND, BIT

Y2 • D2 :+': DO + D1

, CONVERT 3RD BIT

Y3 • D3 :+: DO + D1 + D2

CONVERT 4TH BIT

Y4 .. D4 :+: DO + D1 + D2 + D3

CONVERT 5TH BIT

YS • DS :+: DO + D1 + D2 + D3 + D4

CONVERT 6TH BIT

Y6 • D6 :+: DO + D1 + D2 + D3 + D4 + DS

CONVERT 7TH BIT

Y7 .. D7 :+: DO + D1 + D2 + D3 + D4 +DS + D6

CONVERT 8TH BIT (MSB)

FUNCTION TABLE
D7 D6 DS D4 D3 D2 D1 DO

Y7 Y6 Y5 Y4 Y3 Y2 Y1 YO

,DECIMAL

-----------------------------------------------------------L L L L L L
L L

L L L

L L
L L 8

L
L
L
L

L

L

L
L
L

L

L

8

H
H
H
H
H

B
H
L

H
H
H
H
H
H
L
L

H
H
H
H
H
L
L
L

H
H
H
H
L
L
L
L

H
H
H
L

L
L
L
L

H
H
L
L
L
L
L
L

H 8

L L L

L L

8
8
8
H

8

8
8
H
8
H
L

H
8
H
8

L
L

L
L
L L L
L L L
L L L L

L

L

L

L
L
H
L
L

8

L L L 8 8 H
L L 8 8 8 H
L L H H H H '8

L L H H H H H H
L H H H H H H H
H
H
H
H
H
H
H
B

L L L

8
8
8
8
H
H
H

H

L

L L

L
L
L

L
L
H

L

B
L

8
8
8

L
L
L
L
L

L
L
L
L
L
L

L
H
L
L
L

L
8
L
L
L
L

8
8

0
1
3
7
15.
31
63
127
255
254
252
248
240
224
192
128

8
8
8
H
8
H
H

L
L
L
L
L
L
L L
H L
H L L
L L L
L
L
L
L
L
L
L

L
L

L
L

L
L
L
L

L
L

L
L

------------------------------------------------------------

8-BIT
{
BINARY
NUMBER

10-36

Y

}

TWO'S
COMPLEMENT
REPRESENTATION

Random Logic
DESCRIPTION

THIS PLE8P8 CONVERTS AN 8-BIT BINARY NUMBER (07-00) IN'l'O TWO'S COMPLI!'.MEN'l'
REPRESENTATION (Y7-YO) WHERE 07 AND Y7 ARE THE MSB AND DO AND YO ARE THE LSB.
TWO'S COMPLEMENT REPRESENTATION IS USED IN SIGNED ARITBME'l'IC SYSTEMS.
8-BIT lWO'S COMPLEMENT
CONVERSION
PLE8P8

Monolithic WMembr/e.

10-37

Random Logic
PLBSP8

PLE CIRCUIT DESIGN SPECIFICATION

PS027

.

.

'. . . S . BORIIO 11/29/83

A . JIOR'l'IOR 0'1 TIMIJiG GBNDA'1'OR rCR. PAL. ARltAY.
MMI JAPAN ,',
":. ',,'
,
""
.

PIOGlWIMING"
,

.

• ADDAO Al A2 A3 At
• DAT NAO HAl NA2 NA3 NA. TIALR '1'VCC '1'0..

r NIX'l' ADDRBSS GBNBIIA'l'OR
NAO
NAl

•

/AO

INCREMEH'l'ER (LSB)

•

AO
Al

INCREMEH'l'ER (!WITl.)

:+:
NA2

NA3
NA.

:+:

•

A2
AO* Al

•
:+:

A3
AO* Al* A2

•

:+:

INCR~BR (BIT3)

A.

r INCRBU!N'l'ER

(I~SB)

AO* Al* A2* A3

r TIMING 'WAVEFORMS

*

TIMINGFO~, I,

TIALR • /A. /Al
+ /A.*
/A2*/Al

'1'VCC

r

• /A."'/Al* A2

TIMING FOR

vee

+ /A.* A3*/A2*/Al
'1'0

• /A.* A3*/A2*/Al*/AO

+ /A.*/Al* A2* Al
+ /A.*/Al* A2*

10.38

AO

I TIMING FOR 0

A AND L/R

Random Logic
PUNC'l'ION TABLE

A4 A3 A2 A1 AO NA4 NA3 NA2 NA1 NAO TIALR TVCC TO
,AAAAA

NNNNN
AAAAA

,43210

43210

LLLLL
LLLLH
LLLHL
LLLHH
LLHLL
LLHLH
LLHHL
LLHHH
LHLLL
LHLLH
LHLHL
LHLHH
LHHLL
LHHLH
LHHHL
LHHHH
HLLLL

LLLLH
LLLHL
LLLHH
LLHLL
LLHLH
LLHHL
LLHHH
LHLLL
LHLLH
LHLHL
LHLHH
LHHLL
LHHLH
LHHHL
LHHHH
HLLLL
HLLLH
HLLHL
HLLHH
HLHLL
HLHLH
HLHHL
HLHHH
HHLLL
HHLLH
HHLHL
HHLHH
HHHLL
HHHLH
HHHHL
HHHHH
LLLLL

TIMING WAVEFORMS
TIALR TVCC
TO

, II ,

COMMENTS

---------------------------------------------------------------------

HLLLH

HLLHL
HLLHH
HLHLL
HLHLH
HLHHL
HLHHH
HHLLL
HHLLH
HHLHL
HHLHH
HHHLL
HHHLH
HHHHL
HHHHH

H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L

L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L

L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L

t
L
L
L
L
L
L

01
02
03
04
05
06
07
08
09
10

1

ASSERT TIALR

ASSERT TVCC
ASSERT TO
1

CLEAR TO
CLEAR TIALR , TVCC

11

12
13
14

15
16
17
18
19
20
21
22
23 ;
24
25
1,26
27
28
29
30

.
I

31

32

',.

---------------------------------------------------------------------

MonoIlthlciIM Mem",.l. .

fO-39

Random Logic
DESCRIPTION
THIS LOGIC SPECIFICATION IS A TIMING SIGNAL GENERATOR TO BE USED FOR
ARRAY PK>GlWftING OF PAL DEVICES. A PLESPS FOLLOWED BY AN a-BIT
REGISTER ARE USED TO IMPLEMENT THIS FUNCTION.
THE PLE CONTAINS BOTH S-BIT NEXT ADDRESS AND 3-BIT WAVEFORMS. TIALR
OUTPUT IS A TIMING WAVEFORM FOR I, A, AND L/R SIGNALS, AND TVCC AND
TO OUTPUTS ARE USED FOR VCC AND 0 SIGNALS, RESPECTIVELY.
THE SCHEMATIC IS AS FOLLOWS:

TIALR. TYCC

TO

PLESP8

APPLYING 200KHz CLOCK SIGNAL TO THE CLK INPUT OF THE REGISTER
GENERATES THE FOLLOWING TIMINGS:

1- I, A, AND L/R WIDTH
2. tD2

SO usee
20 usee

3. tD
4. tVCCP
S. 'l'p

30 usee
20 usee

5 usee

BECAUSE THE TIMING PATTERNS ARE S'roRED IN THE PK>M, WE CAN EASILY
CALIBRATE THE RELATIONS AND THE PERIOD AMONG THOSE SIGNALS 'ro MAKE
AN OPTIMUM CONDITION.

A PORTION OF A
TIMING GENERATOR FOR
PAL LOGIC CIRCUIT ARRAY PROGRAMMING

PLE5P8

TB01410M

10-40

Monolithic WMemories

Random Logic
PLE CIRCUIT DESIGN SPECIFICATION
PLBSP8
S. BORIKO 11/29/83
PS028
TIMING GENERATOR FOR PAL DEVICE SECURITY FUSE PROGRAMMING
MMI JAPAN

.ADD AO Al A2 A3 A4
• DAT NAG HAl NA2 NA3 NA4 'l'VCC TP01 TPll
, NEXT ADDRESS GENERATOR
( '!'BB COUN'l'BR LOCKS UP

AT

CO~22

)

NAO

• /A4*
/Al*/AO
+ /A4*
Al*/AO
+ A4*/A3*/A2*
/AO
+ A4*/A3* A2*/Al

INClUJIBN'l'ER
INClUJIBN'l'ER
INClUJIBN'l'ER
INCRl!JmNTER

(LSB)
(LSB)
(LSB)
(LSB)

NAl

• /A4*
/Al* AO
+ /A4*
Al*/AO
+ A4*/A3*/A2*/Al* AO
+ A4*/A3*/A2* Al*/AO

INCRl!JmNTER
INClUJIBN'l'ER
INCRl!JmNTER
INCRl!JmNTER

(BIT1)
(BIT1)
(BIT1)
(BIT1)

I

NA2

• /A4*
A2*/Al
+ /A4*
A2*
/AO
+ fA4*
/A2* A1* AO
+ A4*/A3* A2*/Al
+ A4*/A3*/A2* Al* AO

INCRBMBNTER
INCRl!JmNTER
INCRl!JmNTER
INCRBMENTER
INClUJIBN'l'ER

(BIT2)
(BIT2)
(BIT2)
(BIT2)
(BIT2)

NA3

• /A4* A3*/A2
+ /A4* A3*
/Al
+ /A4* A3*
fAO
+ /A4*/A3* A2* A1* AO

INCRl!JmNTER
INClUJIBN'l'ER
INCRBMENTER
INClUJIBN'l'ER

(BIT3)
(BIT3)
(BIT3)
(BIT3)

NA4

• /A4* A3* A2* A1* AO
+ A4*/A3*/A2
+ A4 */A3 *
fAl

INCRBMENTER (MBB)
INClUJIBN'l'ER (MBB)
INCRl!JmNTER (MSB)

, TIMING WAVEFORMS
/A4
+ A4*/A3*/A2*/Al
+ A4*/A3*/A2*
/AO

TVCC =

'!'POI •
+
+
+

/A4*/A3* A2
/A4*/A3*
Al
/A4*/A3*
AO
/A4* A3*/A2*/Al*/AO

TP11 • /A4* A3* A2
+ /A4* A3*
Al
+ A4*/A3*/A2*/Al

TIMING FOR vec

TIMING FOR PIN 01

TIMING FOR PIN 11

MonoIlthlcW Memories

10.41

Random Logic
PUNC'l'ION TABLE
A4 A3 A2 Al AO HA4 HA3 HA2 HAl HAO· TVCC TPOI TP11
NNNNN

JAAAAA
743210

AAAAA
43210

LLLLL
LLLLB
LLLBL
LLLBB
LLBLL
LLBLH
LLBHL

LLLLH
LLLBL
LLLBB
LLBLL
LLBLH
LLBHL
LLBBB
LBLLL
LBLLB
LBLBL
LBLBB
LBHLL
LBBLH
LBBBL
LHRHH
RLLLL
HLLLH
HLLBL
RLLBH
HLBLL
RLHLH
HLBLH

TIMING WAVEFORMS
'l'VCCP TPOI TP11

7 It J

COMMEN'l'S

01
02
03
1 04
05
06
07
1 08
09
10
11
12
13
14
15
16
17
18
19
20
21
22

ASSERT 'l'VCC, START HERE
ASSERTTPOI

--------------------------------------------------------------------------

LLBBB

LBLLL
LBLLR

LBLBL
LBLBB
LBBLL
LBBLH
LBBRL
LBBRH
BLLLL
BLLLH
BLLHL
BLLHB

RLBLL
RLBLB

H
H
H
H
H
R
R
R
H
H
B
H
H
H
R
H
H
R
R
L
L
L

L
H
H
H
H
H
R
H
H
L
L
L
L
L
L
L
L
L
L
L

L
L
L
L
L
L
L
L
L
L
H
H
R
H
H
R
H
H
L
L

L
L

L

L

CLEAR TPOI
ASSERT TP11

CLEAR TPll
CLEAR 'l'VCC
LOOP HERE UNTIL RESET

--------------------------------------------------------------------------

10·42

Monolithic WMemories

Random Logic
DFSCRIPTION
THIS LOGIC SPECIFICATION IS A TIMING SIGNAL GENERATOR TO BE USED FOR
SECURITY FUSE PROGRAMMING OF PAL DEVICES. A PLE5 P8 FOLLOWED BY AN
8-BIT REGISTER ARE USED TO IMPLEMENT THIS FUNCTION.
THE PLE LOGIC CIRCUIT CONTAINS '1WO FUNCTIONS IN THE SINGLE CHIP. THE FIRST
FUNCTION IS A UNIQUE COUNTER USED FOR NEXT ADDRESS GENERATION. THi COUNTER
INCREMENTS UP. TO COUNT-21 AND THEN LOCKS .. UP THE INCREMENTAL OPERATION AT
COUNT-22. THE SECOND FUNCTION IS A TIMING GENERATOR USED FOR DEFINING
TIMING RELATIONSHIP AMOUNG VCC, POI, AND PH SIGNALS.
THE SCHEMATIC IS AS FOLLOWS:

A(O:4)
PLESP8

~HIS LOGIC OUTPUTS A SEQUENCE.OFTIMING.PATTERNS DURING. THE INCREMENTAL
OPERATION AND THEN HOLDS ALL OUTPUTS LOW UNTIL A .RESET SIGNAL .FOR THE
8-BITREGISTER IS APPLIED.

APPLYING 200 KHz CLOCK SIGNAL TO THE CLK INPUT OF THE REGISTER, THE
FOLLOWING TIMINGS ARE GENERATED:

1. VCCWIDTH

95 usee

2. TPP

40 usee
5 usee

3. to

BY APPLYING THIS DESIGN METHOD, WE CAN EAsILY GENERATE A SEQUENCE OF
UNIQUELY DEFINED PATTERNS EACH TIME THE. RESET PULSE IS APPLIED.
TIMING GENERATOR FOR PAL
SECURITY FUSE PROGRAMMING

PLESP8

.MonoIIthicWMemor/es

10-43

Fast· Arithmetic Look-up

In performing arithmetic operations like trigonometric functions, multiplications and division, in order to reduce the delay,
look-up tables are often used.

sin (X) + sin (XO) + cos (XO) (X - XO)
Since X - XO is represented by only the bits after the more
significant n-bits, and co~ (XO) = sin ('1T12 ~ XO), the implementation will be very simple.

Sine Look-up

Division

For trigonometric functions like sine function, it is very timeconsuming to generate the function using the polynomial
which represents the function. PLE devices can provide avery
good alternative for sine look-up. An example is to use a 2Kx8
PLE device to do a sine look-up of ant1-bit input to 8-bit sine
outputs.
Since sine function has the following property: sin (x) = sin
(11' - x) = -sin (11' + x) = -sin (211' - x) = sin (211' + x), what is
needed is just the sine function for 0 < x < 11'/2; the rest can
be easily calculated using the above relations. In order to fully
utilize the dynamic range, the inputs of the sine look-up PLE
device should be normalized to (1I'/2)/(2n) = 1I'[2n + 1] where
n is the number of address lines to the device.
Since n is fixed for the PLE device chosen, and 11' is a
constant, for the look-up table 1I'/[2n + 1]is a constant.
Therefore, if the sine function of a given x is to be found, x will
first be multiplied by the constant [2n + 1]/11' and sent to the
address of the PLE device to get the final result.
Cos (x) is related to sine function as sin (11'/2 - x). Thus the
cosine function can also be found in the same manner by
using 11'12 - x instead of just x. Other functions like tangent,
secant etc., can also be found as a function of sine.
To increase the dynamic range of outputs, we can just use
another PLE device to generate the less-significant bits of the
sine function.
If a larger dynamic range is needed for the inputs, the result
may be approximated using the Taylor series:
f (X) = f (XO) + f' (XO) (X - XO) + 1/2f" (XO) (X - XO)2 + ...
Where f' and f" are the first and second derivations of f. Since
XO by itself represents a resolution of 2- n, and X is XO
concatenated with the rest of the bits, X - XO must lie
between 0 and 112- n• For f (X) = sin (X),
f (XO) = sin (XO)
f' (XO) = cos (XO)
and f" (XO) = -sin (XO)
So f" (XO) is between -1 and 0 for XO lies between 0 and 11'/2
and X - XO < 2- n. Therefore, the last term will be between
'1/2n and 0, and as long as we do not want to expand the
dynamic range of X beyond 2n-bits, it should be sufficient to
approximate sin (X) in the first two terms:

Division will normally be much slower than multiplication.
There are several ways to perform division. Bit-by-bit division
restoring and nonrestoring algorithms are generally very slow.
Another way is to use several bits at a time division which is
faster than the previous methods. A third way is to multiply the
dividend by the inverse of the divisor. The inverse of the
divisor can be found by getting an approximation followed by
iterations.
The approximation is again given by the Taylor series:
f (X) = f (XO) + f' (XO) (X - XO) + 1/2f" (XO) (X - XO)2 + ...
and f(XO) = 1/XO
f' (XO) = -1/X02
f" (XO) = 2/X03
Say XO is 8-bits long and the first approximation of the inverse
is found using a 256x8 PLE device. The first approximation
can be obtained by subtracting (X - XO)/(X02). Since the first
approximation is limi.ted by an error of approximately (X XO)2/X02, and if XO at least 1, the error is limited by approximately (X - XO)2. Since XO has an S-bit resolution, X - XO is
represented by the rest of the bits. The resolution of the
second approximation Will be about 1f) bits. The thirdapproximation is similarly dedUCed and has a resolution of about 32
bits, and the fourth has a resolution of about 64 bits.
The in'!:;'s'? ~n:.::; 0btained is then multiplied by the dividend to
give the quotiem.
.

Fast Arithmetic Look-up

10-44

Monolithic

Scaling
In arithmetic operations, scaling is sometimes needed. Scaling
normally involves multiplication or division by a constant. Ilthis
constant can be expressed in 2n where n is an integer, then
scaling is simply shifting. Scaling with other constants may
need a multiplier. A multiplier is more expensive and has a
higher pin count than using a PLE device because the
constant that the operand is to be scaled by is not required as
an input as in the case of a multiplier. This will tremendously
, reduce the overhead for data scaling.

Other Applications
Arithmetic look-up are also very useful for arithmetic operations where conventional binary integral arithmetic is not
applicable - like residue arithmetic, and distributed arithmetic.

m

Memories

Fast Arithmetic Look"up
PLE8P8
PS018
4-BIT MULTIPLIER
MHI SAN'l'A CLARA,
.ADD XO Xl X2 X3
.DAT SO Sl S2 S3

PLE CIRCUIT DESIGN SPECIFICATION
VINCBN'l' COLI 12/08/82
LOOK-UP TABLE
CALIFORNIA
YO Y1 Y2 Y3
S4 SS S6 S7

S7,S6,Ss,S4,S3,S2,Sl,S(l .. X3,X2,X1,XO

.*. Y3,Y2,Y1,YO

, S -X

*

Y

FUNCTION TABLE
X3 X2 Xl XO Y3 Y2 Y1 YO S7 S6 S5 S4 S3 S2 Sl SO
,-oPERANDS,XXXX yyyy
:3210 3210

PRODUCTS
SSSSSSSS
76543210

COMMENTS

-----------------------------------------LLLL LLLL
LLLLLLLL
o * 0 .. 0
LLLH

BHHH
HHHH

HHHH
LLLH
HHHH

LLLLHHHH
LLLLHRRR
HHHLLLLH

1
IS
15

* 15 .. 15

*
*

1
15

.. 15
.. 225

DESCRIPTION
THIS PLESP8 PERFORMS 4-BIT LOOK-UP TABLE MULTIPLICATION. THE DEVICE
ACCEPTS TWO 4-BIT OPE.RANDS (X3-XO AND Y3-YO) TO PRODUCE THE 8-BIT
PRODUCT (S7-S0). THE PLE8P8 ALSO HAS THREE-STATE OUTPUTS WITH TWO
ACTIVE-LOW OUTPUT ENABLE CONTROL PINS (/El AND jE2).

x

X3 X2 Xl Xo}
Y3 Y2. Y1YO

S7 S6 S5 S4 53 S2 81 SO

~

.

a-BIT PRODUCT

TWO 4-8IT
OPERANDS

J

4-BIT MULTIPLIER
LOOK-UP TABLE
PLE8P8

x

y

s

Monolithic

IRE! Memories

10-45

Fast Arithmetic Look-up
PLE5P8
P5023
ARC' TANGENT LOOK-UP TABLE
MMI GMBH MUNICH
.ADD AO Al A2 A3 A4
.DAT FO Fl F2 F3 F4 F5 F6 F7
FO

Al *

+
+ AO*/Al*
+ /AO* Al*
+ /AO*/Al*
+ AO*
+
Al*

/A3* /A4
A2*/A3
A3*/A4
/A4
/A3* A4
A2
A2

Fl =
/Al*
A3*/A4
+ AO*
/A3* A4
+
Al*
/A3* A4
+
A2*/A3* A4
+ AO* Al*
/A3
A2*/A3
+ AO*
/A4
+ /AO* Al* A2*
+ AO*
/A2* A3*/A4

PLECIRCUIT DESIGN SPECIFICATION
PETER ZECHERLE 03/06/84

COMPUTE DIGIT FOR 2EXP-7 (0.00078125) (LSB)

COMPUTE DIGIT FOR 2EXP-6 (0.015625)

F2

AO*
/A3*/A4
+
Al*/A2*
/A4
+
A3* A4
+/AO*
A2* A3*/A4
+
/Al* A2* A3*/A4

COMPUTE DIGIT FOR 2EXP-5 (0.03125)

F3

Al*/A2*
/A4
+
/Al* A2*
/A4
+ /AO*
A3*/A4
+
/Al*
A3*/A4

COMPUTE DIGIT FOR 2EXP-4 (0.0625)

F4

/Al*
A3*/A4
+ AO* Al*/A2*
/A4
+
Al* A2*/A3*/A4
+ /AO*
A3*/A4

COMPUTE DIGIT FOR 2EXP-3 (0.125)

F5

AO*/Al*
/A4
+
A2*/A3*/A4
+
/A2* A3*/A4
A3* /A4
+ /AO*

COMPUTE DIGIT FOR 2EXP-2 (0.25)

F6

=

COMPUTE DIGIT FOR 2EXP-l (0.5)

+
+
F7

AO*/Al*/A2*/A3
AO* Al* A2* A3
A4

Al

+
+
+

10-46

COMPUTE DIGIT FOR :2EXPO
A2
A3
A4

Monolithic WMetrJo,.;es

(1)

(MSB)

Fast Arithmetic Look-up

FUNCTION TABLE
J----ANGLE---INTEGER
A4 A3 A2 A1 AO

--------F = ARCTAN(A)-------INTEDER
FRACTIONS
F7
F6 F5 F4 F3 F2 F1 FO

JANGLE

---F = ARCTAN(A)--LOOK-UP CALCULATED

------------------------------------------------------------------------------0.0000
0.0000
L L L L L
L
0
L L L L L L L
L
L
L
L
L
H
H

L
L
L
L
H
L
H

L
L
H
H

L
L
H

L

H

L

H

H

H

L
L

H
H

L

H

H
H
H
H

L
L
L
L

L
L
L
L
H

L
L
H

H
H

H

H
H
L
L

L
L
L
L
H
L
L

L
H
H
H
H

L
L

L
L
L

H
H

L

H
H

H

L
L
H

L
L

L
H

H
H

L
H
H

1
2
4
5
8
16
31

0.7813
1.1016
1.3203
1. 3672
1.4531
1.5078
1.5391

0.7854
1.1071
1. 3258
1.3734
1.4464
1.5084
1.5385

------------------------------------------------------------------------------DESCRIPTION
'mIS APPLICATION ILLUSTRATES THE CALCULATION OF THE ARC TANGENT FUNCTION USING
A PLE5P8 AS A LOOK-UP TABLE. OTHER TRIGONOMETRIC FUNCTIONS (SUCH AS SINE,
COSINE, COTANGENT, SECANT, COSECANT AND THEIR ARC INVERSE EQUIVALENT FUNCTIONS)
OR HYPERBOLIC FUNCTIONS CAN ALSO BE CONSTRUCTED USING PLE DEVICES AS LOOK-UP TABLES.
F

= ARCTAN (A)

EXAMPLE:

WHERE F
A

= ARC

TANGENT OF A
IN RADIANS

= ANGLE

FOR A = 5, F = ARCTAN (5)

= 1.3672

A PLE :)EVICE WITH MORE INPUTS, SUCH AS THE PLEllP8, SHOULD BE USED TO CONSTRUCT. A
LOOK-UP TABLE WHEN ADDITIONAL ACCURACY IS REQUIRED.

~ ------------~t------------

ARCTANGENT
LOOK-UP TABLE

PLE5P8

x
-..it.

2

V

ANGLE

IN
RADIANS

{

A--cr.-.-...
5

=ARCTAN X

F } ARC TANGENT
OFA

Monolithic WMemOrles

10-47

Fast Arithmetic Look-up
PLE5P8
PLE CIRCUIT DESIGN SPECIFICATION
PS024
WILLY VOLDAN 06/02/84
HYPOTENUSE OF A RIGHT TRIANGLE LOOK-UP TABLE
MMI GMBH MUNICH
.ADD AOAI BO 81 B2,
.DAT CO Cl C2 C3 C4 CS C6 C7
CO

AO*/B2* SI

COMPUTE DIGIT FOR 2EXP-5 (0.03125) (LSB)

+ /A1* AO* B2*/Bl
Al*
/B2*
BO
Al*
/B2* Bl
+ Al*/AO* B2*/Bl*/B0
+ Al* AO*
Bl* BO
+
AO*/B2*
B9,
+
+

Cl =
+
+
+
+
+

AO*
Bl*/BO
/Al* AO* B2
Al*/AO*/B2*
BO
Al*/AO* B2*
/BO
AO* B2*
sO
Al* AO*
Bl

COMPUTE DIGIT FOR 2EXP-4 (0.0625)

C2

=
AO*/B2*
BO
+ /Al* AO*/B2* Bl
+ Al*/AO* B2*/Bl
+ Al* AO* B2* Bl
+ Al*
/B2*/Bl* BO

COMPUTE DIGIT FOR 2EXP-3 (0.125)

C3

= /Al*

AO*/B2*/Bl* BO
Al*/AO*
Bl*/BO
Al*/AO* B2
Al*
B2*
BO

COMPUTE DIGIT FOR 2EXP-2 (0.25)

+
+
+

Al*/AO*/B2* Bl
Al* AO* B2*/Bl* BO
Al* AO*
Bl*/BO

COMPUTE DIGIT FOR 2EXP-l (0.5)

+
+

C4

C5 = /Al*
BO
+
AO*/B2*/Bl
+
/AO*
Bl* BO
+
B2*
BO
+ Al* AO*/B2*
/BO
+ Al* AO*
/Bl
C6

= /Al*

Bl
/B2*/Bl
B2* Bl
lAO *
Bl
Bl*/BO

+
+
+
+

A1*

+

Al* AO*

C7

B2

10-48

COMPUTE DIGIT FOR 2EXPO (1)

COMPUTE DIGIT FOR 2EXPl (2)

COMPUTE DIGIT FOR 2EXP2 (4) (MSB)
Bl* BO

MoneilthicW Memories

Fast Arithmetic Look-up
FUNCTION TABLE
1-LENGTH OF SIDESSIDE B
I SIDE A
Al AO
B2 B1 BO

LENGTH OF THE HYPOTENUSE
INTIDER
FRACTION
C7 C6 C5 C4 C3 C2 C1 CO

SIDES
IA B

LENGTH OF HYPOTENUSE
CALCULATED
LOOK-UP

------------------------------------------------------------------------------L L
o0
0.00
0.00
L L L
L L L L L
L L L
L
L
L

L
L
L

L
L
H

L
H
H
H
H
H

H
L

L L
L
L
L H
H L
L H

L
L
H
H

H

L
H
L

H

H
L

L
L

L
L
H

L

L

L

L

L

L

H

L
H
L
L
H
H

H
L
L
H

L

L

L L
L H H

H

H

L H

H

L
L
L
L

L
L
L
L

L L· L L
H L L

H
L
H

H

L

L
L
L
L

L
L
L
L

H

H

H

L' L H
H

H

L
L
L
L
L
H
H
H
H

o1
0 2
04
1 0
2 0
2 2
2 4
3 2
3 7

1.00
2.00
4.00
1.00
1.00
2.78
4.47
3.59
7.47

1.00
2.00
4.00
1.00
1.00
2.83
4.47
3.61
7.62

-------------------------------------------------------------------------------

HYPOTENUSE OF A RIGHT
TRIANGLE LOOK-UP TABLE
PLE5P8

Monolithic WMemories

10-49

Fast Arithmetic Look-up
DESCRIPTION
THE GENERATION OF COMPLEX ARITHMETIC FUNCTIONS SUCH AS THE PYTHAGOREAN
THEOREM IS GENERALLY VERY DIFFICULT TO IMPLEMENT DIRECTLY IN HARDWARE.
HOWEVER,. IMPLEMENTING THE FUNCTION AS A LOOK-UP TABLE USING A PLE GREATLY
SIMPLIFIES THE PROBLEM.
THIS EXAMPLE ILLUSTRATES H)W TO IMPLEMENT A LOOK-UP TABLE IN A PLESP8 WHICH
CALCULATES THE LENGTH OF THE HYP9TENUSE OF A RIGHT TRIANGLE AS A FUNCTION OF
THE LENGTH OF. THE '!WO Rl!MAINING SIDES OF THE TRIANGLE. THE THI!X)REM OF
PATHAGOREAN STATES THAT THE LENGTH OF THE HYPOTENUSE OF A RIGHT TRIANGLE IS
EQUAL 'ro THE SQUARE ROOT .OF THE SUM OF THE SQUARE OF THE OTHER '!WO SIDES OR
C
SQRT(A**2 + B**2). THE INPUTS, nAn AND nB", CORRESPOND'ro THE SIDES
ADJACENT 'ro THE .RIGHT ANGLE (I.E. 90 DE3REEANGLE), WHILE THE OUTPUT, nc",
CORRESPONDS 'ro THE SIDE OPPOSITE TO THE RIGHT ANGLE WHICH IS CALLED THE
HYPOTENUSE.

=

C

= SQRT(A**2

EXAMPLE:

+ B**2)

FOR A

=2

WHERE C = LENGTH OF SIDE C (THE HYPOTENUSE)
A = LENGTH OF SIDE A
B = LENGTH OF SIDE B

AND B = 4, C

= SQRT(2**2

+ 4**2)

4.47

c

10-50

Monolithic WMetrJor/es

Fast Arithmetic Look-up
PLESP8
PLE CIRCUIT DESIGN SPECIFICATION
PS02S
PETER WITTFOTH 06/02/84
PERIMETER OF A CIRCLE LOOK-UP TABLE
MHI GMBH MUNICH
.ADD RO Rl R2 R3 R4
.DAT PO PI P2 P3 P4 PS p6 P7
PO

/Rl* R2*/R3*/R4
+ /RO*/Rl* R2*
/R4
+
Rl* R2*
R4
+
Rl*/R2*/R3
+ RO*/Rl*/R2* R3
+ /RO* Rl*/R2
+
Rl*/R2*
/R4
+
/Rl*/R2*
R4

COMPUTE DIGIT FOR 2EXPO (1) (LSB)

PI

=

COMPUTE DIGIT FOR 2EXPl (2)

RO*

/R2*/R3

+ /RO* Rl* R2*/R3
+ /RO*
/R2* R3
+ RO*
R2* R3
+ /RO*
R2*/R3* R4
+ RO*/Rl* R2*
/R4
+
/Rl* R2* R3*/R4
+ RO* Rl*
R3* R4

P2

P3

RO*/Rl*
/R3*/R4
+ RO* Rl*/R2*/R3* R4
+ /RO* Rl*R2* R3* R4
+ /RO* Rl*/R2*
/R4
+
Rl* R2*/R3*/R4
+ RO* Rl*
R3*/R4
+ /R0*/Rl*/R2*
R4
+
/Rl* 'R2* /R3*, R4
+ RO*/Rl*
R3* R4

COMPUTE DIGIT FOR 2EXP2 (4)

= /RO*

COMPUTE DIGIT FOR 2EXP3 (8)

+
+
+
+
+
+
+
+
+
+

P4

=

Rl*/R2*
/R4
RO*/Rl*/R2* R3
RO*/Rl*/R2*
R4
RO*
/R2* R3* R4
RO*
R2*/R3*/R4
/RO*
R2* R3*/R4
Rl* R2* R3*/R4
/RO*
R2*/R3* R4
Rl* R2*/R3* R4
/RO* Rl* R2*
R4
/RO*/Rl* R2*/R3

RO* Rl*/R2*/R3
+
Rl*/R2*/R3* R4
+ /RO*/Rl* R2*/R3
+ RO*/Rl* R2*
/R4
+
/Rl*/R2* R3
+ /RO* Rl*
R3*/R4
+
Rl* R2* R3*/R4
+
/Rl*
R3* R4
+ /RO*
R2* R3* R4

COMPUTE DIGIT FOR 2EXP4 (16)

MonoIllhlt:W Memories

11).51

Fast Arithmetic Look-up
PS =
+
+
+

R1* R2*/R3*/R4
/R1*/R2* R3*/R4
/R2* /R3* R4
R1*/R2*
R4
/R1* R2* R3* R4
/Ro* R1*/R2* R3
/RO*/R1* R2*
R4
/Ro*
R2* R3* R4

COMPUTE DIGIT FOR 2EXP5 (32)

R3*/R4
= RO* R1*
+ /RO*/R1*
/R3* R4
R2* R3*/R4
+
+
/R2*/R3* R4
+ RO* R1* R2* R3

COMPUTE DIGIT FOR 2EXP6 (64)

=

COMPUTE DIGIT FOR 2EXP7 (126) (MSB)

+
+
+
+

P6

P7

RO*

+
+

R2*
R1* R2*

R4
R4
R3* R4

FUNCTION TABLE
7---RADIUS---INTOOER
R4 R3 R2 R1 RO

-------PERIMETER------MSB
INTEGER
LSB
P7 p6 P5 P4 P3 P2 Pl PO

7RADIUS

PERIMETER OF A CIRCLE
LOOK-UP CALCULATED

-----------------------------------------------------------------------------L L L L L
L L L L L L L L
0
0
0.0
L L L L H
L L L H L
L
L
L
H
H

L
L
H
L
H

L
H
L

L
H

H
L
L
L
H

H
L
L
L
H

L L L L L H H L
L L L L H H L H
L L L H L L H H
L
L
L
H

L
L
H
H

L
H
H
L

H
H
L
L

H

L
L
L

L
L
H
L

L
H
L
H

1
2
3

4
6
16
31

H
L
H
H

6
13

19
25
50
101
195

6.3
12.6
16.6
25.1
50.3
100.5
194.6

-----------------------------------------------------------------------------PERIMETER OF A CIRCLE
LOOK-UP TABLE
PLE5P8

10-52

Monolithic WMemories

Fast Arithmetic Look-up
DESCRIPTION
THIS EXAMPLE ILLUSTRATES HOW TO IMPLEMENT A LOOK-UP TABLE IN A PLE5P8 FOR THE
PERIMETER OF A CIRCLE AS A FUNCTION OF THE RADIUS. THE INPUT PINS (R4-RO),
WHICH REPRESENT THE RADIUS OF A CIRCLE, ARE MULTIPLIED BY 2 TIMES PI IN ORDER
TO CALCULATE THE PERIMETER OF A CIRCLE (P7-PO). THIS LOOK-UP TABLE IS VALID
FOR RADII BETWEEN 0 AND 31. A PLE8P8 SHOULD BE USED INSTEAD IF A LARGER
RADIUS RANGE (BE'lWEEN 0 AND 81) IS REQUIRED.
P

= 2*PI*R

EXAMPLE:

WHERE P = PERIMETER OF THE CIRCLE
PI = 3.1415
R = RADIUS OF THE CIRCLE (BE'lWEEN 0 AND 31)
FOR R = 3, P = 2*PI*3 = 19

C), ..."
P }

Monolithic mMemorieS

PERIMETER.
OF THE
CIRCLE

10-53

Fast Arithmetic Look-up
PLE5P8
PLE CIRCUIT DESIGN SPECIFICATION
PS026
WILLY VOLDAN 06/03/84
PERIOD OF OSCILLATION FOR A MATHEMATICAL PENDULUM LOOK-UP TABLE
MMI GMBH MUNICH
.ADD LO L1 L2 L3 L4
• DAT TO '1'1 '1'2 '1'3 '1'4 '1'5 T6 '1!7
TO

= /L4*
+

+
+

+

+
+

'1'1

/L2*/L1* LO
/L3*/L2* L1*/LO
L3*/L2*
LO
/L4*
L2*/L1*/LO
L4* L3*
LO
L4*/L3*
Ll
L4*/L3* L2*
/LO

COMPUTE DIGIT FOR 2EXP-5 (0.03125) (LSB)

/L2* L1*/LO
LO
/L4* L3*/L2* L1
/L4*
L2*/L1*/LO
L4*/L3*/L2* Ll
/L3* L2*/L1
L4* L3*
/Ll* LO
L4* L3*
L1*/LO

COMPUTE DIGIT FOR 2EXP-4 (0.0625)

+ /L4*/L3* L2*

+
+
+
+
+
+

T2

= /L4*/L3*

Ll*/LO

COMPUTE DIGIT FOR 2EXP-3 (0.125)

+ /L4* L3*/L2*
LO
+ L4*/L3*/L2*/L1*/LO
+ L4*/L3*
L1* LO
+ L4* L3*/L2* L1*/LO
+ L4* L3* L2*/Ll
+ L4*
L2*
LO
+ /L4*/L3*
/Ll* LO
+ /L4*/L3* L2*
/LO

'1'3

= /L4*

L3*

L1* LO

+ L4*/L3*
L1
+ L4* L3* L2*/L1
+
/L3*/L2*/L1*
+
/L3* L2* L1*
+
L3*/L2* L1*
+
L3* L2*/Ll*
+ /L4*
L2*/Ll*

'1'4

= /L4*/L3*
+
/L3*
+ /L4* L3*
+ L4*/L3*
+ L4*
+

10-54

COMPUTE DIGIT FOR 2EXP-2 (0.25)

LO
LO
LO
LO
LO

L1*/LO
L2* L1
L2*/L1
L2
L2* L1
L2* L1*/LO

COMPUTE DIGIT FOR 2EXP-1 (0.5)

Monolithic WMemories

Fast Arithmetic Look-up
T5 .. /L4*
/L2*
/LO
+ /L4*
/L2*/Ll
+
L3*
/LO
+
L3*/L2
+
L3*
/Ll
+ L4* L3

COMPUTE DIGIT FOR 2EXPO (1)

/L4*
/L2* L1* LO
+ /L4* L3*
/LO
+ /L4*/L3* L2
+ /L4*/L3*
/Ll

COMPUTE DIGIT FOR 2EXP1 (2)

T6 ..

T7=
+

L3* L2* L1* LO

COMPUTE DIGIT FOR 2EXP2 (4)

(MSB)

L4

FUNCTION TABLE
:--AMPLITUDE-INTEGER
L4 L3 L2 L1 LO

:

--PERIOD OF OSCILLATION-INTEGER
FRACTION
T7 T6 T5 T4
T3 T2 T1 TO

,AMPLITUDE

PERIOD OF OSCILLATION
LOOK-UP CALCULATED

------------------------------------------------------------------------------L L L L L
L L H L
L L L L
1
2.0000
2.0050
L

L L L
L L H
L H L
L H L L
H L L L

H
L

H

H

L
L

H

H

H

L
L
L

L L
L
L

L
H
H

L
H
H

H
H

L

L
H
L

L
L L L

L

H

H

H

H

L
L
L
L
L

H
H
H
L
H
H

2
3
5

L
H
H
L

H
H
H

L

9

L

L
H

17
32

L

2.8125
3.4375
4.4375
6.0000
8.2500
11.3125

2.8356
3.4728
4.4834
6.0151
8.2670
11.3423

------------------------------------------------------------------------------PERIOD OF OSCILLATION
FOR A MATHEMATICAL PENDULUM
LOOK-UP TABLE
PLE5P8

MonoIilhic

W Memories

10-55

Fast Arithmetic Look-up
DESCRIPTION
THIS PLESP8 IS USED TO IMPLEMENT A LOOK-UP TABLE FOR '!'HE PERIOD OF OSCILLATION
OF A MATHEMATICAL PENDULUM. '!'HE PERIOD OF OSCILLATION FOR MATHEMATICAL
PENDULUM ('1') IS DEPENDENT UPON ITS AMPLITUDE OF SWING (L) AND THE ACCELERATION
DUE TO GRAVITY (G). THE PERIOD OF OSCILLATION IS CALCULATED USING THE
FOLLOWING EQUATION:

=

'1' • 2*PI*SQRT(L/G)

WHERE '1'
PERIOD OF OSCILLATION IN SECONDS
PI = 3.14
L = AMPLITUDE OF SWING IN METERS
G
ACCELERATION DUE TO GRAVITY IN M/S/S
(9.81 M!S/S)

=

EXAMPLE:

FOR L

= 5,

'1' = 2*PI*SQRT(5/G)

= 4.4375

A PLE DEVICE WITH 5 INPUTS CAN BE USED TO CALCULATE THE PERIOD OF OSCILLATION
FOR AMPLITUDES UP TO L = 32 METERS. PLE DEVICE WITH MORE INPUTS SHOULD BE USED TO
CALCULATE LARGER PERIODS OF OSCILLATION.
THIS EXAMPLE DEMONSTRATES HOW EASY IT IS'TO CONSTRUCT LOOK-UP TABLES FOR
COMPLEX ARI'l'HME'l'IC FUNCTIONS USING PLE DEVICES

LENGTH
{
OF PENDULUM

10-56

~
L

PERIOD'OF
OSCILLATION FOR A
MATHEMATICAL'PENDULUM'
LOOK-UP TABLE

Monolithic

...!.L.-

W Memories

- T

}

PERIOD OF
OSCILLATION
IN SECONDS

Fast Arithmetic Look-up
PLE CIRCUIT DESIGN SPECIFICATION
FRANK LEE 10/14/83

PLE12P8
PS017
ARITHMETIC LOGIC
MMI SANTA CLARA,
.ADD AJ A2 Al AO
.DAT C3 C2 C1 CO

UNIT
CALIPORNIA
B3 B2 B1 BO cm I2 Il IO
ZvC

.************************************************
THIS DESIGN IS ~T YET SUPpORTED BY PLEASM *
I.************************************************
I

J*

C,C3,C2,C1,CO

= /S2*/51*

;B - A - 1 + CIN

+

;A .., B-1 + CIN

+
+

+
+
+

50*/AJ,/A2,/Al , /AO
.+. B3, B2, B1, BO.+. cm
/S2* 51*/SO* A3, A2, A1, AO
.+./83,/B2,/B1,/BO.+. cm
/52* Sl* SO* AJ, A2, Al, AO
.+. B3, B2, B1, BO.+. cm
S2*/Sl*/SO*/AJ,/A2,/Al,/AO
:*: B3, B2, B1, BO
S2*/Sl* SO* A3, A2, A1, AO
+ S2*/Sl* SO* B3, B2, B1, BO
S2* Sl*/SO* A3 , A2, A1, AO
* B3, B2, B1, BO
S2* S1* SO

= /C3*/C2*/C1*/CO

Z

;A XOR B

;A + B
;A

*

B

,PRESET
; OVERFLOW

C:+: C3

V

;A + B + CIN

; ZERO

DESCRIPTION
THIS ALU CAN PERPORM 8 FUNCTIONS ON TWO 4-BIT OPERANDS A (A3-AO) AND
B (B3-BO) WITH CARRYIN (cm) AND GIVES A 4-BIT RESULT C (C3-C0) WITH
CARRYOUT (C). IT WILL ALSO GIVE STATUS AS OVERFLOW (V) AND ZERO (Z).
THE FUNCTION IS DETERMINED BY A3-BIT FUNCTION SELECT CODE (S2-S0):
ARITHMETIC LOGIC UNIT

MOOE

S2 S1 SO

FUNCTION

PLE12P8

---------------------------------0
1
2
3
4
S
6
7

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0 CLEAR
1 B - A - 1 +cm
0 A - B - 1 + CIN
1 A + B + cm
0 A XOR B
1 A+B
0 A* B
1 PRESET

vcc

82

ii

AO

---------------------------------A2

AND
OR
GATE
ARRAY

CIN

E1
NC

C2

GND

Monolithic IFIJ) Memories

co

10-57

Wallace

Tree~

Compression

Wallace Tree Compression

The groups are assigned as follows:
G1 :(aO, a1, bO, b1,cO, c1, dO, d1, eO, e1)
G2:(a2, a3, b2, b3, c2, c3, d2, d3, e2,.e3)
G3:(a4, a5, b4, b5, c4, c5, d4, d5, e4, e5)
G4:(a6, a7, b6, b7, c6, c7, d6, d7, e6, e7)
The above groups of bits can be compressed to:
H1:(h1 3, h1 2, h1 t , h1o)
. H2:(h23' h2 2, h2 t , h2o)
H3:(h33, h~, hat, h30)
H4:(h43 , h42' h41, h4o)

In performing arithmetic calculations, it may happen that more
than two numbers are to be added together. Adding two
numbers can be achieved by using a simple adder. If there are
more than two numbers to be summed, several levels of
adders may be needed. This often causes too much delay.
An alternative is to use Wallace Tree Compression. Suppose
there are m numbers each of n·bits wide. Summation over"
these numbers will range from 0 to m x (2 n - 1) which will take
log2[m(2n - 1) + 1] bits (rounded UP to the nearest integer).
For example, if there are five 2·bit numbers, i.e., m = 5, and
n = 2, the sum will be bounded by 5 x (22 - 1) = 15 which will
need a total of 4 bits.
One Wallace Tree Compression by itself will not be very
useful. But consider if five 8·bit integers are added together.
This technique enables vertical compression of these num·
bers in four groups. This type of vertical compression also
eliminates the need of carry propagation. The five numbers
are represented by:
A = (a7, a6, a5, a4, a3, a2, a1, aO)
B - (b7, b6, b5, b4, b3, b2, b1, bO)
C = (e7, c6, c5, c4, c3, c2, c1, cO)
D = (d7, d6, d5, d4, d3, d2, d1, dO)
E = (e7, e6, e5, e4. e3, e2, e1. eO)
where the 7th bits are the most significant; the calculation is
as follows:
G4

+)

G3

G2

G1

a1

aO

=A

b2

b1

bO

=B

c2

c1

cO

=C

d3

d2

d1

dO

=D

e3

e2

e1

eO

=E

a4

a3

a2

b5

b4

b3

c5

.c4

c3

d6

d5

d4

e6

e5

e4

a7

a6

a5

b7

b6

c7

c6

d7
e7

h3 3

h3 2

h41

h40

h23

h22

h3 1

h30

h13

h12

h21

h20

h10

= H1
= H2
= H3

+)

h43

h42

h3 3

h32

h3 t

h30

h13

h12

+)

h4a

h42

h41

h40

h23

h22

h21

h20

510

59

58

57

56

55

54

53

52

10-58

h1 t

= H4

Monolithic WMemorles

h11

51.

~: h10

SO

= result

Wallace Tree Compression
81 and 80 are just h11 and h10' 810-82 can be obtained
through addition of other bits. The hardware implementation is
as follows:

87_ b7-b4

4

Gl

It needs four PLE10P4 devices, two 748381 ALUs and one
748182. An alternative is using ten 748381 ALUs and four
748182 Carry Lookahead Generators.
83-80 b3-1>O

'0"

c7..... cl7-<14

'0"

4

G2

4
G3

4
G4

o

.1008-06

_.1-00
B000070M

.104

17-a4

83-00

A comparison between the two architectures gives the following data:
USING WALLACE
TREE COMPRESSION

USING CONVENTIONAL
ARITHMETIC LOGIC

79
7
128

115
14
264

Delay (ns)
Number of components
Total number pins on the parts
Since Wallace tree compression can be of any configuration,
there is no predefined part available. A PLE device provides
an excellent solution. The designer may define his own
configuration as long as it can be put· in.a .commercially
available PLE device.

Monolithic

IFIJJ Memorle.

10-59

Wallace Tree Compression
PLE CIRCUIT DESIGN SPECIFICATION
PLEBP4
VINCENT COLI 04/06/83
P50l9
SEVEN I-BIT INTmER ROW PARTIAL PRoDUC'l'S ADDER
MMI SANTA CLARA, CALIFORNIA
.ADD ABC D E F G
.DATPO Pl P2
P2,Pl,PO

= A .+.

B .+. C .+. D

.:fo.

E .+. F .+. G

P

= A+B+C+D+E+F+G

FUNCTION TABLE
ABC D E F G p2 Pl PO
;A
L
L
H
H

BCD

E

F

G

L
H
L
H

L
L
H
H

L
H
"L
H

L
L
H
H

L
L
H
H

L
H
L
H

PPP
210

COMMENTS
A+ B+ C + D+ E + F + G

LLL
LHH
HLL

0+0
0+1
1 + 0
1 + 1

HHH

=P

+ 0 + 0 + 0 + 0 + 0 =0
+ 0 + 1 + 0 + 1 + 0
3
+ 1 + 0 + 1 + 0 + 1
4

+ 1 + 1 + 1 + 1 +1

=
=7

DESCRIPTION
THIS PLESP4 PERFORMS PARTIAL PRODUCTS REDUCTION FOR WALLACE TREE
COMPRESSION. SEVEN ROWS OF I-BIT NUMBERS (A, B, C, D, E, F, AND G)
ARE NUMERICALLY SUMMED TO PRODUCE A 3-BIT RESULT (P2-PO).
A
B
C
D
E
F
G

+

--P2 PI PO
3-BIT
RESULT

10-60

SEVEN
l-BIT
INTEGERS

SEVEN 1-BIT INTEGER ROW
PARTIAL PRODUCTS ADDER
PLE8P4

MonolithicW"Memories

Wallace Tree Compression
PLE CIRCUIT DESIGN SPECIFICATION
PLE10P4
PS020
VINCENT COLI 08/22/83
FIVE 2-BIT INTI:X;ERROW PARTIAL PRODUCTS ADDER
MHI SANTA CLARA, CALIFORNIA
.ADD AO A1 BO B1 CO C1 DO D1 EO El
.DAT PO P1 P2 P3

= A1,AO

P3,P2,P1,PO

.+. B1,BO .+. C1,CO .+. D1,DO .+. E1,EO

P -A+B+C+D+E

FUNCTION TABLE
A1 AO B1 BO C1 CO D1 DO E1 EOP3 P2 P1 PO
;M

;10

BB
10

DD
10

CC
10

EE

PPPP

10

3210

COMMENTS
A+B+C+D +E - P

----------------------------------------------------------LL
LL LL
LL
LLLL
LL
0 + 0 + 0 + 0 +0
0
HL

LH
HL

HH

HH

LH

LH
HL
HH

LH
HL

LH
HL

HH

HH

LHLH
HLHL
HHHH

..

1 + 1 + 1+ 1 + 1
5
2 + 2 +2 + 2 + 2 .. 10
15
3 + 3 + 3 + 3 +3

DESCRIPTION
THIS PLEI0P4 PERFORMS PARTIAL PRODUCTS REDUCTION FOR WALLACE TREE
COMPRESSION. FIVE ROWS OF 2-BIT NUMBERS (Al-AO, B1-BO, C1-CO,
DI-DO, AND El-EO) ARE NUMERICALLY SUMMED TOPRODUCEA4-BIT RESUL.T
(P3-PO) •

Al
AO}
Bl:B°
C1 CO

+

FIVE.
2·BIT

Dl DO

INTEG.ERS

E1 EO

.

P3P2 PI PO
'-.-'
4-BIT

.
FIVE2-BIT INTEGER ROW
PARTIAL PRODUCTS ADDER
PLE10P4

RESULT

"',.....

10-61

Wallac•. Tr•• Compr•••ion
PLE CIRCUIT
PLEI2P8
PS021
POOR 3-BIT INTEGER ROW PARTIAL PRODUC'l'S ADDER
MMI SANTA CLARA, CALIFORNIA
.ADD AO Al A2 BO Bl B2 CO Cl C2 DO Dl D2
.DAT pO PI P2 P3 P4

SPECIFICATION
VINCENT COLI 02/10/83

DESIG~

P4,P3,P2,Pl,PO .. A2,Al,AO .+. B2,Bl,BO .+.C2,Cl,CO .+. D2,Dl,DO

P • A+B+C+D

FUNCTION TABLE
A2 Al AO B2 Bl BO C2 Cl CO D2 Dl DO P4 P3 P2 PI PO
BBB
210

CCC
210

DDD
210

PPPPP
43210

COMMENTS
A+B+C+D=

HHH

HHH

LLL
LLB
LHL
LRR
BLL
BHH

LLL
LLB
LHL
LHH
BLL
BRR

LLLLL
LLHLL
LBLLL
LHHLL
BLLLL
HHHLL

o +0

HLL

LLL
LLH
LHL
LHH
BLL

IAAA

1210
LLL
LLH

LHL
LHH

1
2
3
4
7

+
+
+
+
+

1
2
3
4
7

+ 0
+1
+2
+ 3
+ 4
+ 7

+
+
+
+
+
+

P

0 .. 0
1 • 4
2 = 8
3 = 12
4 = 16
7 = 28

DESCRIPTION
THIS PLE12P8 PERFORMS PARTIAL PRODUCTS REDUCTION FOR WALLACE TREE
COMPRESSION. FOUR ROWS OF 3-BIT NUMBERS (A2-AO, B2-BO, C2-CO, AND
02-00) ARE NUMERICALLY SUMMED TO PRODUCE A S-BIT RESULT (P4-PO).

+

,

A2A1AO}
B2 Bl BO
FOUR
C2 Cl CO IN~~S
D2 Dl DO

FOUR 3-BIT INTEGER ROW
PARTIAL PRODUCTS ADDER

-----------~--P4 P3 P2 PI PO
5-81T

RESULT

10-62

MonoIlthlC.mMemorllltl

PLE12P8

Wallace Tree Compression
PLE12P8
PLE CIRCUIT DESIGN SPECIFICATION
P5022
VINCENT COLI 08/10/83
THREE 4-BIT INTEGER ROW PARTIAL PRODUCTS ADDER
MHI SANTA CLARA, CALIPORNIA
.ADD AD A1 A2 A3 BO B1 B2 B3 CO C1 C2 C3
.DAT PO P1 P2 P3 P4 P5

P5,P4,P3,P2,P1,PO .. A3,A2,A1,AO .+. B3,B2,B1,BO .+. C3,C2,C1,CO

1 P .. A+B+C

FUNCTION TABLE

A3 A2Al AD B3 B2 B1 BO C3 C2 C1CO P5 P4 P3 P2 P1 PO
1AAAA
13210

BBBB
3210

CCCC
3210

PPPPPP
543210

LLLH

LHLL
HLLL

LLLH
LLHL
LHLL
HLLL

HHHH

HHHH

LLLH
LLHL
LHLL
HLLL
HHHH

LLLLHH
LLLHHL
LLHHLL
LHHLLL
HLHHLH

COMMENTS
A

+ .B

+ C

..

1
2
4
8
15

+ 0
+ 1
+ 2
+ 4
+ 8
+ 15

+ 0
+ 1
+ 2
+ 4
+ 8
+ 15

0
3
6
=12
= 24
• 45

P.

-----------------------------------------------------.
LLLL
LLLL
LLLL
LLLLLL
0
LLRL

.
=

--------------.---------------------------------------DESCRIPTION
THIS PLE12P8 PERFORMS PARTIAL PRODUCTS REDUCTION POR WALLACE TREE
COMPRESSION. THREE ROWS OF 4-BIT ~MBERS (A3-AO, B3-BO, AND C3-CO)
ARE NUMERICALLY SUMMED TO PRODUCE A 6-BIT RESULT (P5-PO).

+

. A3 A2 A1AO }
B3 B2 Bl. BO
C3· C2 Cl CO

THREE
4-81T
INTEGERS

THREE 4-BIT INTeGER ROW
PARTIAL PRODUCTS ADDER

P5 P4 P3P2 P1 PO

....

.rII

6-81T
RESULT

10-63

Residue Arithmetic using PLE Devices
Residue Arithmetic using PLE Devices
Conventional binary arithmetic. can· be. replaced by another
kind of computational methodology known as the Residue
Number System. The use of this system allows integer arithmetic to be performed by arrays of PLE devices. The idea of
PLE devices as arithmetic elements is simply to store precomputed values of the arithmetic operation in the PLE
memory cells and to use the input variables to the arithmetic
as addresses to the PLE devices. Since we are computing the
results of the arithmetic operations,. the same PLE device
organization may be used for many different functions. As an
example, a 256x8-bit PLE device can be used as a 4 x 4-bit
binary multiplier, or a 4 + 4-bit binary adder with the output
multiplied by any 3-bit constant. It is this flexibility which holds
so much appeal for the use of PLE devices as computational
elements.

m1 = 3, m2 = 4, m3 = 5. The residues of X
shown as xi where i = 1, 2, 3. Thus,

25 will be

X1 = 1251m1 = 12513 = 1
X2 = 1251m2 = 12514 = 1
X3 = 1251m3 = 12515 = 0
In the RNS using the moduli 3, 4,. 5, the number .. 25 is
represented as (1, I, 0).
The number of unique representations for a set of moduli is
the Least Common Multiple (LCM) of the moduli.. The most
efficient set of moduli is one in which all moduli are pairwise
relatively prime.
Tables 1 illustrates an example of a set of moduU(3, 4) which
can represent 12 integers. Note that the representations of 0
and 12 are the same. sinct:! the representation repeats itself
after 12 integers

Introduction
Arithmetic operations often involve carry propagation. This
propagation causes too much delay for high-speed arithmetic.
The Residue Number System (RNS) provides the required
separation property needed for high-speed arithmetic. Each
digit of the RNS representation is coded into a certain number
of bits. In performing the basic operations of addition, subtraction, and multiplication, no information is required to be
passed between the digits. Therefore, the number of bits
required for representing each digit can be partitioned so that
commercially available PLE devices can be used to implement
the arithmetic.

Basics of the Residue Number System
In this section. the elements of performing arithmetic using the
RNS are introduced. The mechanism of coding numbers, t!le
method of performing arithmetic USing the RNS,andfinally
conversion between binary and. RNS are presented.

X

(3)
x1

(4)
x2

0

0

0

1

1

1

2

2

2

3

0

3

4

1

0

5

2

1

6

0

2

7

1

3

8

2

0

9

0

1

Coding of Residue Numbers

10

1

2

In principle, the coding of. R.esidue Numbers is extremely
simple. A residuecdigit is the remainder when the number to
be coded is divided by another number (a modulus). As an
example. the residue of .15 divided by a modulus 7 which
yields 1 as the remainder can be represented bYl15i7 = 1.
If operations are performed on an RNS where only one
modulus is used, it will not be advantageous against a simple
binary scheme atall since no information is encoded. Only the
encoding of the binary numbers will provide the separation
property which will speed up the arithmetic operation. The
advantage of the· RNS accrues when more digits are used.
Another example of encoding a number using 3 moduli to give
a 3-digit RNS represel1tation is as follows: let the moduli be

11

2

3

12

0

0

10-64

=

Table 1. Representation of 0 to 12 In RNS Using Moduli 3 and
4. The Representation Repeats Itself After 12 Integers

In table 2, (4, 6) is the set of moduli uses. Since 4 and 6 are
not relatively prime, the number of integers that can be
represented is not the product of 4 and 6, but instead is the
LCM of 4 and 6 which is 12. Therepresentation again repeats
itself once every 12 integers.

MonoIlthlcm Meinorles

Residue Arithmetic usingPLE Devices

xl

(4)
x2

X

(3)
xl

(4)
x2

0

0

0

0

0

0

1

1

1

1

1

1

2

2

2

2

2

3

3

3

3

0

3

4

0

4

4

1

0

5,

1

5

5

2

1

6

2

0

6

0

2

7

3

1

5

1

3

2

4

2

0

(3)

X

2

8'

0

9

1

3

3

0

1

10

2

4

2

1

2

1

2

3

11

3

5

12 ,,','

0

0

13

1

1

14

2

2

15"

'····3

3

0

4

1&'

;

;;,

17

1

5

18

2

0

19

3,

1

20

0

2
3

21

1

22

2

4

?3

3

5

24

0

0

Table 3. Representation of

~6

to 5 In RNS using Moduli 3 and 4

Arithmetic Using the RNS

.

Table 2. Representation of 0](24 for Moduli 4 and 6. Since 4
and 6 are .Not aelatlvely Prime, and their LCM is Only
12, the Representation Again Repeats Itself Every 12
Integers,

Negative numbers are· formed in the same way negative
numbers are formedin'binary (two's complement) system. To
form the two's complement 6f a number in binary, we subtract
the number 28 whereBis the number .ot bits of the representation. InRNS, we subtract the RNS number from mi to form
the negative. Table 1 can be rewritten as in table 3 for
encoding, of negati~e numbers.

For two RNS numbers, X and Y, the result of the additiol) of
the two numbers, Z, in RNS is given by:
p"-1

PLESP4

r--IX115

1-+4-"7''--1

PLEIP8

rlXI23

PLE10P8

LIXI,1'
! I X I, 3

4 PLE12P4.

or
2PLE12P8s

4

10

I

L-_ _ _S--;':........I>-:;,.<-;~I

'----~4'-----4---_r_----IXI2

Figure 4. Mapping a 16-Blt Integer X to Residues In Modulo 2,
11, 13, 15, and 23 Using Two-Level Mapping. The First
Level Gives Remainders from the More Significant
Twelve Bits, While the Second Level Finds the Final
Residues

In some circumstances, although an N-bit integer only has a
dynamic range of 2N, the intermediate calculations may over-

flow. It is sometimes necessary to add some other moduli to
boost up the dynamic range for the intermediate calculations.

Arithmetic Operations In RNS
The arithmetic operations of the RNS is different from regular
arithmetic in that even simple addition must be performed in
modulo arithmetic. Simple AlU may not be able to handle this
arithmetic. Again, PlE devices are proven to be most useful. A
PlE8P4 device can perform addition, subtraction, or multiplication on two 4-bit residue numbers and give a 4-bit modulo
result.

-c

Figure 5. Calculating C

=A +

B, A - B, B - A x BUsing

PLE8P4

If the modulus is large, say greater than 64, the combined
number of bits for two residues will be greater than the
number of address bits for the largest of the commercially
available PlE device. Of course, more than one device can be
used to deepen the effective address space. In this case, for
every additional bit of a modulus, two more bits of address will
be needed - one for each operand. In other words, for each
additional bit of a modulus the address space of operation will
be quadrupled. It is not very effective when the modulus
grows too large. Fortunately, for both addition and multiplication, there are more efficient procedures.

Large Modulus Addition
Table 5 shows the contents required for the addition operations. in modulus 11. There is a lot ·of redundancy in the table
which can be compressed by reducing what should be eight
bits of inputs to five bits. What we need is just another level of
mapping. There are a total of 121 combinations for a number
of modulus 11 operating on another operand of the same
modulus. In reality, only numbers ranging from 0 to 10 can be
represented in modulus 11. The sum ranges from 0 to 20 (not
in modulus 11). This range can be represented by a new set
of submoduli(3, 7) which is five bits wide. In fact, any new set
of submoduli .which has a dynamic range of at least twentyone can be used. The operands in modulus 11 will be
converted to their representations in submoduli 3 and 7. The
addition is done in the submoduli and the result is reconverted
back to modulus 11 RNS (see Table 6).

Monolithic WMeliror18s

10-67

R••idu.Arithmetlc Using, PLE Circuits

..

,,2 ·3

0

1

4

5

6

7

,8

9

10

0

0

1

2

3

4

5

6

7

8

9

10

1

1

.2

,3

A

5

6

7

8

9

10

0

2

2

3

4

5

6

7

8

.9

10

0

1

3

3

4

5

6

7

8

9

10

0

1

~

4

4

5

6

7

8

9

10

0

1

2

3

5

5

6

7

8

9

10

0

i

2

3

4

6

6

7

8

9

10

0

1

2

.3.

4

5

7

7

8

9, 10

0

' 1

~

3

4

5

6

8

8

9

1

2

3,

4

5

6

7

9

9

10

0

1

2

3

4

5

6

7

8

10

10

0

1

2

3,

4

5

6

7

8

10

0

,

9

" Table 5. AddltjonTabie In Modulo 11 ArIthmetic

0

1

2

3

4

5

6

\x+ y!11' 0

1

2

'3

4

5:

6

.,

Ix + yj7
Ix + YI3

0

1

2

3

4.

5

6

0

0

1

2

0

1

2

0"

1'

x+y

7

8

9

10

11

12

13

14

15

16

17

18

19

20

8

9

10

0

1 '

2

3

4

5

6

7

8

9

1

2

3

4

5

6

0

1

2

3

'4

5

6

2

0

1

2

0

1

2

0

1

2

0

1

2

;

"

Table 8. Conversion Table Batw. .n Modulo 11 ArHh"etlc and ModulO 3 and 7, Arithmetic

FIgure 8. CelCulBtlng

AddItIon of TWo Numbers InModll1o 11, U.lng Subrilodull Opilratlona

Large Modulus' Multiplication
The solution to this problem in multiplication is similar. For
example, if two RNS digits in modulus 91' is to be multiplied,
(7, 13) may be chosen as a set of submoduli. Therepresentation of an RNS digit in modulus 91' needs 7-bits. These 7-bits
are first mapped to two RNS digits - in mOdulo 7 which
needs 3-bits; and in modulo 13 which needs 4-bits. The
representations Of the two operands in the two moduli can
then be multiplied and give the result in modulo 7 and modulo
13. The result Is then converted back to modulo 91. Unfortu.nately, this scheme can be used 'only when th~,modulus can
be expressed as a product to two Integers which are relatively
prime. But, In this Case, the RNS digit may simply be rep~

10-68

sentedas the residue of the two smaller integers'instead of.
using them as submOduli.
.

Figure 7. calculating Multiplication of Two Number. Iii Modulo
91 Ullng Sublilodull Operatlona

Residue Arithmetic UsingPLE Circuits
Suppose another modulus 101 is used. 101 is a prime number
and fiNS in modulus 101 ranges from 0 to 100. The real
dynamic range of the product of two numbers in modulus 101
is 0 to 10000, which is already too large for a PLE address
space. For this modulus, we may use three 4K-deep PLE
devices to deepen the address space. For a modulus like
1001, it may not be too efficient to use this scheme. Instead,
since:
xy = [(x + y)2 - (x - y)2]/4
or

= [x

3. Find X = 1><111 + ~t2 + ... + xn - 1In - 11 M
In hardware implementation, ti's are all known beforehand.
We can map xi's to get the xiti's.Then we may perform
Wallace Tree Compression (see the session on this subject in
this handbook for more information) on the xiti's to give twolevel operands which add to the final sum and divide it by M to
get X. Again, PLE devices provide the best solution for
Wallace Tree Compression.

+ y)2]/4 - [(x - y)2]/4.

we may do x + y and x - y first and then do the squaring of
the sum and the difference scaled by a factor of 4. Since the
final product of two integers must be an integer, the squaring
and scaling may be performed in one operation with the
fractional part discarded. The way to obtain x + y and x - y is
the same as what was discussed earlier in the "Large Modulo
Addition" session.
In any event, operations on residues of large moduli are
slower and involve more hardware and are not recommended.

Figure 9a. Reverse Mapping to Get

XI~

xx •• xxxx.xxxxxx
xxxxxxxxxx.xxxx

wwwwwwwwwwwwwwwwww
wwwwwwwwwwwwwwww

Figure 9b. Modulo M Wallace Tree Compre8slon to Reduce the
Number of Levels fOr Summation to 2 Followed by
an Addition and Division to get X IXlt1 + ... +
xnt"iM

=

Figure 8. Performing Modulo 1001 Multiplication

Conclusion
The Reverse Conversion
The reverse mapping from RNS to integer is not as straightforward as the other way. For an RNS system which has a
total of twelve bits for all the residues, we can still use 12input PLE devices to convert. We may also use several sets of
12-input PLE devices to reverse map the RNS if the integer is
not much longer. But for very long integers, we may need to
use the general algorithm for the reverse map:
1. Find M = ml x m2 x ... xmn _ 1 (where n is the number
of moduli)
2. Find ti = Mimi

Memory elements provide excellent solutions to mapping
functions - for control purposes, for arithmetic operations
and general logic replacements. This paper investigates the
possibility of using PLE devices as arithmetic units. In fact, for
logic like residue number arithmetic, there is no better solution
than to use these devices.

Acknowledgement
Portions of this article were extracted from "Integer Arithmetic
Using PROMs" by Dr. G.A. Jullien of the University of
Windsor, Canada.

MonoIlthlcWMemor/ea

10-69

Disttibut... Arithmetic Using PLE~Devices
Distributecl Arithmetic Using PLE Devices
In digital Sign&! proCessirig;sum:ef~prOducttypEiOf operations
are
often
neCeSsary;
These'
operations
take" the form
of:., '
"
.,.."
-",
,
.. . ,
.'."
.

..

"

'Y'"

¥r

,,1:,
L..,O

'~'

where 8;'s

are

some constants,

If real multiplications are to be p8Hormed on every prOduct
term, it will need a total of M ,multiplications and M-1 additions.
Multiplicationoplwmions nOrmal,lf. taks"mliCh longer than simple addition. An alternative ,to, calculate equations of the above
form is by using distrib~ arithmetic.
Suppose there is an N-bit, int~e.. X· given by:
x = [x(N - 11, x(N-2), .."x(1),x(0)]
or equivalently:'
,:;'jA,
~.'"

x'"

N-1
Z
j ... 0

,:,,' :

M

"

1:

20
H (j)

:E

8;X; (j)

forM .. 20

i .. 1
10
20
= 1: 8;X; (j)
+ E II;xt (j)
1= 1
i'" 11
the20-bit address can be Separated to two 10-bit addresses
and each of them is individually mapped. The two outputs will
then be added together to give H (J). An Implementation of
this mapping Is shown in figure 2.

X(j)2J".

where x(N - 1) is ,the most significant bit The equation:

Y-

address lines if we want to use only PLE mapping. Since' 20
bits of address 'translate to 1M words, and there is no
available 1M-deep PLE device on the market, it is not realistic
to use PLE mapping. Instead, H (j) can be partitioned as
follows:

"

8jXj

XtJ)

'0

X,OcJ)
Xl1 (J)

'0

H(J)

~J)

i- 0
can be expressed as:
y= j

N
j

~ ·.·~·(~=i:~0>2j)'
1

~1

=0

2i

(.~,
1=,1

Figure 2. Mapping the ~ Bit of Each of lIj'. to an L-blt Reeu"
When There Are T~ Many x'. (20 In Thl. Ceae)

8;X1(j))

Now, let:
M

H(j) ...

1:

8jXi(j)

i-1

Since H (j) is independent of ia~d siocJ al's are all constants,
we precompute for every x(j) = [x,(j). x20>"':' xM(j)l the values
[x,(j). x2(j) ..... ~(j)] the values of H 0); Then x6rca" be used
as the address of.PLE:devJces·whose'outputs ar.ethe precomputed result H(j).
;:
X,(J), •.. , l I u ( J ) 4

r

~NG ~ L-IIITRESULT

Figure 1. Mapping the h Bit from Each of the

lIj'. to An L-blt

Reau"

If th,ere are M bits of data and the result is L-bit wide. and if M
is very large, say 20, and L' is 8, Jhen we need 20 bits of

1(10.70

There is another alternative for impl!tme~l)g asum:ef-prOduct
operation: by using a multiplier accumulator (MAC). '
The main, constraint on distributed arithmetic is that one set of
the multiplicands musttle fixed, i.e: ai's in this eSse, for the
sum.of-prOduct mapping whiie, a MAC will allow flexibility. '
There are normally SOme constraints on the width for the data
bus from which the operands are loaded. If all the operands
are new. it will OEIed M cycles to load in the operands anyway,
dis,tributed arithmetic .offers no advantages over MAC, since
distributed arithmetic needs to wait for all the operands to be
loaded in before any operation can start while' MAC can
perform a multiplication and an addition every cycle. M cycles
will be needed anyway for the complete operation using a
MAC while distributed arithmetic may take even longer.
On the other hand, for operations like convolutions where one
set of operands are fixed and only one new variable operand
is needed for every result, distributed arithmetic will be a
better solution since it can give a result in every clock-cycle
while a MAC will need M-cycles (because recalculations of ' all
the prOduct terms are necessary). An implementation for
convolution is shown in Figure 3.

Distributed Arithmetic Using PLE™ Devices
Note that the second term of the last equation means that the
previous result (Yi _ 1) is shifted right one-bit; the last bit of
Yi - 1 is truncated.
The implementation of such a system is shown in Figure 3.
The system consists of a shift register, a mapper (PLE circuits,
or PLE circuits with adders), an accumulator, and an ALU.

INPUT

M-l SHIFT REGISTERS

M

MAPPER

L

Figure 4. A Blt-Serlallzation Implementation for a Distributed
Arithmetic System

RESULT
8000170M

The operations are as follows:

Figure 3. An Implementation of a Distributed ArIthmetic System
for Convolution

1) Load X; onto the load and shift register at clock O.
2) Load H (0). onto accumulator and shift all registers at clock

There is another waY to implement distributed arithmetic
through bit-serialization:
From H (j), the sum-ot-product of y can be obtained as:

1.
3) From clock k (between clock 2 to clock N - I). the content
of the accumulator will be replaced by the sum of H (k-l)
and .the more signifjcantN - 1 bits of the current accumulator value.

N-l

y=

~

2iJOl

i =0
To implement this equation, consider that the least significant
bit of the result is to be used only for rounding purposes only.
Only the more significant bits will be retained. The computation can be performed in the following way:
1) For

i = 0,

4) For clock N, the following are performed:
a) Repeat step 3. At the end of the operation, the accumulator contains the value of the result (scaled by the
number of shifts)
b) Xi + 1 is loaded onto the load and shift register. The
shifting frequency is equal to N times the basic rate.
Due to the fact that there are a number of shift operations
necessary for each data load, this method is recommended
for the following conditions:

Yo = 2oH(0) = H (0)
2) For j= 1 toN-l
Yi = HOl + 1/2H{j - 1)

1) This design is under cost, power dissipation, and board
space constraints.
2) This design is for high M-to-N-ratio array multiplications.

Monolithic

m

Memories

10-71

Registere.d pl.E™ t;)e"ices in Pipelined.Arithm.etic
Registered PLE Devices in Pipelined
Arithmetic
PLE devices are useful as logic elements, and registered
PLEs are excellent media for pipelined arithmetic. Monolithic
Memories supplies a number of registered PLE devices which
•
provide effective solutions to pipelined systems.
A data processing system may have fall-through architecture.
Since many of these operations may take a long. time, it
happens that the devices are not often tied up in operations.
For example, in a system as in .figure I, the operations can be
divided into three functional blocks; When the operands are
loaded in, block 1 will operate first, followed by block 2 .m

(al - 2)

CNE PRDlCl' T!3t: ,1
-P+G

(C*D)

OR G>.m (al - 3)
PlOJl'C'l' TEl'Hl: tl (F), '2 (G)

'l.W)

10

"II+/J+/K

1

.. IM"IN

'1

(II) , t2VJ), t3(/K)

NOR G>.m (EXrS)
CNE PRDlCl' T!3t: 11

R .. P*/Q + IP*Q

LINE M

N1IND.GM'E (l1X2 -4)

I 'D!Rl!Z PRDlCl'TEl'Hl:

o

1
2
3
4
5

INVERIER G>.m (al - 1)
CNE PIOXlCr T!3t: tl (IA)

B

H

LINE
LINE
LINE
LINE
LINE

04/20/83

VJ\FAI

(1M"IN)

GM!: (I1XHi)
'DiO PRDlCl' TEl'Hl: tl(P*/Q), t2(IP*Q)
lIOR

PDNCrICN 'D\BtE

ABCDEPGSIJ1'I:LMNOPQR

IB

III.

xx

xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx

xxx xxx XXXX
xxx xxx .XXXX
xxx XXXX
tu. xxx XXXX
xxx BIB XXXX
xxx IBH XXXX
xxx tu. XXXX
XXX, xxx UIIlIi
xxx xxx BIBB
xxx xxx BHIB
xxx xxx BBHL
xxx xxx XXXX
xxx xxx XXXX
xxx xxx XXXX

BBH

xxx
xxx
xxx
xxx
xxx
xxx
xxx
xxx
xxx
xxx
xxx

xxx
xxx
xxx
xxx
xxx
xxx
xxx
xxx
xxx
xxx
xxx
LIB xxx
HIlI. xxx
xxx BIB

(EXr1,PT-1)
(EXr1,PT-1)
(EXr2,PT-1)
(EXr2,PT-1)
(EXr3,PT-1)
(EXr3,PT-2)
(EXr3,PT-l,2)
(EXr4,PT-1)
(EXr4,PT-2)
(EXr4,PT-3)
(D;r4,PT-1,2,3)
(EXrS,PT-1)
(EXrS,PT-1,2)
(EXr6,PT-1)

SAO
SAl
SAO
SAl
SAO
SAO
SAl
SAO
SAO
SAO
SAl

TEST
TEST
TEST
TEST
TEST
'lEST
'lEST

TEST
TEST'

LINE N

TEST

'lEST
SAO 'lEST
SAl 'lEST
SAO 'l!ST

II!SCMPl'ICN
'mE MI\IN PURPCSE OF 'mIS El!l\MPIE IS '.to !2IMILIARIZE
'mE USER
l'IIAT WI!;' MElIN. BY "PDNCrICN 'D\BtE",
PRDlCl' T!3t(P1') CXl!lERi\GE, S'lUCK-A'l'-O (SAO) AND
sm:K-AT-CNE (SAl) 'l'ESTS.

w:rm

EXAMPLE 5

• Line N the function table which begins with the key word
"FUNCTION TABLE:' It's followed by a pin list which may
be in a different order and polarity from the pin list in line 5.
VCC and GND cannot be listed. The pin list is followed by
dashed line; e.g.; ____ which in turn is fOllowed by a list
of vectors, one vector per line. One state must be specified
for each pin name and optionally separated by spaces. A
vector is a sequence of states listed in the same order as the
pin list and followed by an optional comment.

11-6

The allowabl.e states are H (HIGH LEVEL), L (LOW LEVEL),
X (IRRELEVENT), C (TRANSITION FROM HIGH TO LOW
OR CLOCK PULSE) and Z (HIGH IMPEDENCE). After
preparing the PAL DESIGN SPECIFICATION in the,above
format, PALASM software can be used to simulate and
perform fault testing.

Testing Your PAL Devices
BllSIC GPmS

1 XXXXXXXXXlCccocl
2 XXXXXXXXXXXlCIX

3 llXXXXXXXXXXXXX
4 OOXXXXXXXXXXXXXX
5 XXlOXXXXXXXXXXXIIXX
6: XXOlXXXXXXXXXXXBXX

7 XXOOXXXXXXXXXXXLXXX
8 XXXXXXXXOXl.lBX
9 XXXXXXXXlXOllIXXXXXXl
10
11
12
13
14

XXXXXXXXlXlOllXXXXXXl
XXXXXXXXlXllLXX
XXXXOOXXXXXXXXllXXXXl
XXXXllXXXXXXXXL
XXXXXXlOXXXXXllXXXXXl

1:=1 O=--~--,

~

PASS SDIlIATIQI
PHDlCl':
1 OF EOOATIQI.
PlOXlCl':
2 OF EOOATIQI.
PlOXlCl':
2 OF EClJATIQI.

6: tlN'mSTED(SAl)FAllLT
6: tlN'JES'lm)(SAl)FAllLT }'
6: mm;sTED(SAO)mtlLT

NtJ!BBR OF S'roCIt AT CNE (SAl)

mtIL'l'S ARB"

8

NtJ4B£R OF S'roCK AT ZER) (SAO)

FAm.TS

9

ARB,.

I

.....----1
.

P=*

R=P.Q+P.O EO-6

P*O

.. 85'
FAULT-TESTING
The following information is reported to the user
-

Totat number of SA 1 Faults. (8 in example 5)

-

Total number of detected SAO faults. (9 in example 5)
SA 1 faults + SAO faults
2 * total number of product terms
*100%

-

(~

*100%= 85%ex-5)
2*10
One vector may detect more than one SAO OR SA1
FAULTS (vector # 11 in example 5)
The user is reported with a message which tells him the producttenn for Which it was not tested. (PRODUCT TERM 1 & 2EO 6, in example 5)

The following vectors can be added to the function table in
example 5 in order to achieve 100% fault coverage.
AS CJE FQI IJKL

me

PQR

xx xxx xxx XXXX XXX, LHH
xx xxx xxx XXXX XXX HIlL
PALASM" software has tested the
above function table for example 5,
the result is as follows:

CXHoII!Nl'S (EXlIMPIE 5)

(EXr6:,PT2)'
(EXr6:,Pl'-1,2)

SAO 'lEST
SAl 'l1:ST

BllSIC~

1 XXXXXXXXXXXXXXX1
2 XXXXXXXXXXXXXXX

3 l.l.XXXXXXXXXXX
4 OOXXXXXXXXXXXXXla
5XXlO~

6: XXOlXXXXXXXXXXXBlC

7 XXOOXXXXXXXXXXXLXXX

8

xxxxxXxxoxlllIx

9 XXXXXXXXlXOlBXXXXXXl
10 XXXXXXXXlXl.OBX
11 XXXXXXXXl.Xl.l.
12 XXXXOOXXXXXXXXl!XXXXl

13 XXXXl.lXXXXXXXX
14 XXXXXXlOXXXXXllXXXXXl

15 XXXXXXOlXXXXXllXXXXXl

16 l(XXXXXUXXXXXI.
PASS SDIlLATIQI
NtJ!BBR OE' S'roCIt AT CNE(W) FAIlIll'S ARB .. 10
NtJ!BBR OE" S'roCIt AT ZERl (SAO) FAIlIll'S ARB .. 10
PJ;axa 'mill ~
-100'

PALASM'· is a trademark of Monolithic Memories.

11-7

PAL®20RA10 Design for Testability
Edwin Young

This article is written to help customers of the PAL20RA1
recognize some fundamental design-for-testability issues which
may arise due to the part's unique architecture. Customers
should understand that these issues represent design criteria
which Monolithic Memories will use to accept PAL20RA10
patterns for test generation/fault grading and for estimating the
resource cost to test engineering if accepted. This article does
not address the BUSINESS REQUIREMENTS such as the need
for acceptable test vectors and the acceptability of a particular
pattern for processing as a HAL@ device.

The latch problem described is not unique to the 20RA10 but is
clearly applicable to any PAL with asynchronous outputs with
feedback (e.g., 16R4). The designer should realize, however,
thatfalse latching may occur on a 20RA10 even if all outputs are
registered. Consider the equation setO:= C and D.CLKF = A'B
for a simple registered 20RA10 output. The resulting waveforms
would look similar to those of the previous. asynchronous
example. The important distinction here is that a 20RA10 has
programmable asynchronous clocks rather than a Single 'master
clock' pin which can cause difficulties in testing.

The designer who wishes to use a 20RA10 in his/her design must
bear in mind that although the part has preloadability, certain
designs could diminish the effectiveness of this feature. The
following rules are presented to help establish Test Engineering
acceptance standards for the 20RA10. Additional general guidelines applicable are available in the PAL Handbook article reprint
"Testing Your PAL Devices" by M. Vafai.

The previous two pitfalls were examples of flaky latching due to
glitches during testing. Consider the equation set C := Band
C.CLKF = A for a registered output. The following example
shows a definite positive latching ...but of flaky (skewed) data.

Allow Data to Setup Prior to C,ocking

Avoid False Latching Situations
The equation D = (A'B) + (C+D) and its variants are susceptible
to latching hazards since ATE may have considerable input
skew. Of course, from a testing viewpoint, such implementations
should be avoided. But if they must be implemented, care must
be exercised in developing the function table so as to account
for the possibility of latching. The designer must adopt and stick
to some guideline such as "no more than one input undergoes a
change in logic value per vector" when specifying the function
table.

A

B

A

B

Assume B isaprimary input. Then the timing for situations at far
left and left may be with A as feedback and. as primary input
respectively.
This example illustrates another aspect otthe programmable
asynchronous clock feature of the 20RA20: Clock pulses can
nave critical minimal or no delay relative to data setup time. Note
that all other· registered PAL devices have dedicated common
clock pins to which delayed pulses are applied by the ATE to
allow sufficient data setup time and ATE input skew.

Avoid Unreachable States
o

Assume A, Band C are primary inputs while D is a fed-back
output. The waveforms to the left show two possible outcomes
for output Ddepending on the skew of inputs A and B, which is a
function of tester calibration.

The 20RA10 may be preloaded to any state desired for testing
purposes. Unfortunately, the desired state may not exist long
enough for the..simulator or ATE to use it. With all other
preloadable PALs, any arbitrary state may be preloaded into the
registers on a given test vector and the state will persist into the
next vector providing the required conditions to detect some
faultls:This means .all stuck-at-type faults possibly detectable
can be detected. Witn the 20RA 10, the preloaded state may feed
back to assert state dependent resets or presets on one or more

PAL@ and HAL@) are registered trademarks of Monolithic Memories.

. TWX: 910"~~8-2~76
2176 Mission College Blvd. Santa Clara, CA 96054-1692 Tal: (408) 970-9700 TWX: 910-~~8-2374

11-8

Monollthlem·

Memorl. .

PAL20RA 10 Design for Testability
registers, Consequently, the desired state may last only a few
nanoseconds after the preload vector is complete before changing to some new state. Since the desired state is not stable going
into the vector immediately following the preload vector, the
faults expected to be detected become non-detectable.
Another problem arises whenever output control logic is a
function of state. In this case, assume the desired state for
detecting faults is preload and is stable in the next vector. If this
state provides the conditions necessary to detect faults and also
disables the outputs, then the faults will be effectivley masked
from detection.

A

B

c~

Caution on Individual Register Bypass
Mode

An indeterminate state on the output can occur if both primary
inputs A and B go to logic low on the same vector.

The 20RA 10 allows the designer to permanently and independently bypass any register. Those registers not permanently
bypassed may be bypassed under program control by setting
both SET and RESET nodes to logic high. In this 'bypass mode',
the register's D node is multiplexed to the output rather than its
Q node. There is generally no test problem in going into bypass
mode. The pitfall is .. in returning to 'register mode' operation,
which only the 20RA10 can do. Consider the equation set
C.RSTF = A and C.SETF = B of a simple registered output and

the following possible waveforms. A race condition will occur to
see whether set or reset operation prevails in going from bypass
to register mode, There are two methods bywhich.to get known
states for testing purposes:
1) Clock a known value into the register on the next vector or;
2) Set RESET to logic low on one vector and then SETto low
on the next or vice versa.

MonollthlcUll Memories

11-9

PAL® Design Function and Test Vectors
E. Young

Introduction
This article was written to help customers understand the purpose of seed vectors and provide some general guidelines as to
what elements are important in developing them. It is assumed
that the reader has read the "PALASM'" Manual" and the "PAL@
Handbook" article reprint Testing Your PAL Devices.

The following simple example demonstrates how exercising
seed vectors might be derived from a deSigner's state diagram:

E9

In general, PAL@/HAL@ devices are required to provide a function table or "Seed Vectors" to Monolithic Memories in order to
ensure that parts shipped have a high degree of reliability for the
application intended. Ideally, these vectors should accomplish
three objectives: ,
1) Initialize the PAL device preferably in the same way as in
the actual system;
2) Exercise the customer's functions thoroughly, emulating
actual system operation as closely as possible;
3) Provide a high degree of fault coverage.

Initialization
Seed vectors which initialize the PAL logic circuit consist of one
'or more vectors placed at the very beginning which will bring
both combinatorial and registered outputs to a stable and known
logic state (1 orO). This is necessary in the system also so that its
operation upon power-up is predictable. Furthermore, care
should be taken to ensure that the initialization state is a legal
state of the state machine for which the PAL device is intended.

E4

Assume the following state and edge definitions accompany the
diagram:
STATE 0 = LL
STATE 1 = LH
STATE 2 = HL
(ILLEGAL) STATE 3 = HH

(INITIALIZING)
(INITIALIZING)
(INITIALIZING)
(INITIALIZING)

Exercise Functions
The essential functions for which the PAL device was originally
designed must be exercised fully. This will assure thatthe tested
parts work the way they were intended to. In addition to essential
"designed-for" functions, it is prudent to include general test
exercises such as verifying that outputs don't change in the
absence of clock pulses and checking to see that inputs in the
"don't care" (X) state don't produce adverse responses. General
test exercises help to reinforce the validity of a deSign and can
uncover overlooked design errors. After a set of exercises, has
been decided upon, the next step is to write them in a format
suitable for simulation purposes.
The designer may have originally defined the functions in terms
of equations, state diagrams, truth tables, etc. Truth tables are
readily reformatted to PALASM1 syntax "Function Tables" and
exercises with the simulation option (code=S). State diagrams
can be converted by expressing each state and input edge in
binary vector format and sequencing them according to the
diagram's flow. The customer should become thoroughly
fam iliar with the syntax ofthe function table description (see the
PALASM Manual for a detailed treatment of syntax) before
attempting to translate truth tables, etc.

EDGE

PRESENT STATE

NEXT STATE

AB

CD

CD

HL

XX

LL

HH

LL

HL

LL

HL

HL

LH

HL

LH

LH

LH

LL

LL

LL

LH

LL

LH

HL

TWX: 910-338-2376
2175 MllSlon College Blvd. Sante Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374

11-10

LL
LH
LL
LH
LL
HH
HL
HL
HL
HL

From the above information, it is possible to create the truth
table for the diagram and then the function table representation:

PAL@ and HAL® are registered trademarks of Monolithic Memories.

PALASM''' is a trademark of Monolithic Memories.

EDGE 0 =
EDGE 1 =
EDGE 2 =
EDGE 3 =
EDGE 4 =
EDGES=
EDGE 6 =
EDGE 7 =
EDGE 8 =
EDGE 9 =

MonolIthIc l!T!n
MemorIes InJn.U

PAL Function and Test Vectors

FUNCTION TABLE REPRESENTATION
FUNCTION TABLE
AB

CD

HL

LL

HH

HL

TESTEDGE5

LL

HL

TESTEDGE4

LH

LH

TEST EDGE 3

LH

LL

TEST EDGE 1

LL

LH

TESTEQGEO

LL

HL

TEST EDGE 2

INITIALIZE DEVICE

Fault Coverage
Another criterion for seed vector completeness is "fault coverage".
Fault coverage is an empirical method and is more quantitative
than functional exercising - indeed, no knowledge of the
circuit's intended function is necessary or assumed (although it
could help) while developing fault coverage vectors.
Fault coverage, being an empirical approach to determining a
logic circuit's reliability, uses the concept of "failure models" to
grade the effectiveness of a given set of test .vectors. This is
cal/ed "fault grading". In fault grading a set of vectors, a fault
coverage value is calculated that is simply the ratio of detected
faults to total faults expressed as a percentage.
Test vectors may be graded against one or more failure
models. Some well-known models include single stuck-at-1/
stuck-at-D, pattern sensitivities, shorts and opens and multiple
stuck-at models. Selection of a failure model (or models) for
fault grading fundamentally depends on the model's empirical
effectiveness for screening bad parts and will be affected by a
number of factors including circuit technology and fault simulator
capabilities.
The most common and primary fault coverage failure model
considered by "TGEN" at Monolithic Memories is the classic
single stuck-at-1/stuck-at-O failure model. "TGEN" automatically appends test vectors which testlor the following additional
failure modelS where applicable: 1) Adjacencies, 2) Clock:
3) Tri-state.
"TGEN" has a specified minimum value offault coverage for PAL
and HAL devices based on the single stuck-at failure model. The
minimum values aredetermined by current "TGEN" policy (see
your FAE) and reflect the economic trade-off between acceptable
levels of reliability and the cost of test generation for maximum
coverage. PAL and HAL devices for which the specified minimum
values cannot be attained will require the customer's written
waiver for low coverage prior to production release of the
pattern.

lIIIonoillhIC

The fault coverage percentage determined by "TGEN" is different from the percentage determined by selecting the fault
testing option (code=F) of PALASM1 software. In PALASM1
software fault coverage is based on product term coverage
(PTC). PTC is still the ratio of detected to total faults except that
"detected" and "total" fault sums refer to stuck-at faults on
product term outputs only. PTC ignores stuck-at faults which
occur anywhere else. A more accurate procedure is to calculate
the coverage based on all the circuit nodes where a stuck-at
condition may occur. When every node (fault site or wire) is
considered, the coverage calculated correlates. to the design's
testability better and will generally be a much lower value than
PTC. "TGEN" goes one step further in conservatism by calculating fault coverage on a "collapsed" fault basis. Fault
collapSing simply divides all the stuck-at faults into groups such
that, within a group, if one fault is detected, then all the others in
the group are detected too. The advantage of collapSing it that
only one representative fault in a group needs to be selected for
test generation and if it is detected, then the other "equivalent"
faults are detected by definition. This saves time and effort on
test generation for equivalent faults. Calculations on a collapsed
fault basis treat each group as onefaull.
The following simplified example demonstrates the difference in
fault coverage calculations using a collapsed fault list:

A

B

C
0

E
F
G
H

I

l/SAl

2!SAO

3/SAl

4/SAO

SISAl

6/SAO

7/SAl

SlSAO

9/SAl

10/SAO

11/SAl

l2!SAO

25/SAl

l3!SAl

l4/SAO

lS/SAl

l6/SAO

17/SAl

l8/SAO

26/SAO

J

Note: This example is a simplified one for illustrative purposes only and does
not show the effects of faults normally associated with input or output
buffers. Also, some partial collapsing has already been done (Le., input

faults of "OR" gate are collapsed into output faults of "AND" gates).

Assume the above circuit is to be realized as a PAL or HAL
device. Suppose some seed vectors are provided also, as shown
here:

0

A

B

C

VECTOR 1

H

H

H

L

L

L

l

L

L

VECTOR 2

L

L

L

H

H

H

L

L

L

VECTOR 3

L

L

L

L

L

L

H

H

H

VECTOR 4

L

L

L

L

L

L

L

L

L

mEl Memorle.

E

F

G

H

I

11·11

The seed lisclor$on the previous page .yield various'values for
fault-coverages eorrespooding to the method of calculation,as
shown in· the .table below:
" ,,'e, -,'
...
,',,:
. "",'

,

.

"

L

, P:1:#

'

SUBSETOFTOTAL' ""
FAUL1$ CONSIDERED:'
. FORCALCULA1'IONS
THAT ARE OETECTED.
BY EACH'VECl'OR'
!(SHOWNAt FAR RIGHT)'
TOTAL FAULTS .
'.
CONSIDeRED .FOR
CALCULA~IO"'E! '
PERCENt COVERAGE

•EVERY NODE

,".

,.

20'

2,4,6,20,26

2

Vector 1-

<8,10,12,22

8

Vector 2

"

22"
,.

2.4,

"
'

~~,16;H~,24

14

Vector 3

'19,21,23,25

19

.. Vector4

1,2,3,4,5,6,7,8;9,10,11 ,
.12,13,14,15,16,17,18,
... 19,20,21,22,23,24,25,26

1,2,3,5,7,
8;9,11,13,
14,15,17,1,9

!

1~,21,23

.'

19,20,
·21,22,
23,24
6/6=100%

4/13= 31%

17/26= 65%

seed

can improve the coverage significantly. For theabOlie example,
the reader can verify that the following slight modification ofthe
seed vectors would yield 100% coverage for all calculation
methods:

As can be seentrom the aboveel«lmple, given the same
vectors, PALASM1 softWarewQuld
100% coverage whereas
"TGEN" would show"31% coVerage. Notice'that'the pOor
coverage by "TGEN" is due to none of the input nodes being
tested for stuck-at-f. ·In most histances, better set of test vectors

shov"

a

F

G

H

I

L

L

L

L

L

H

H

i:.

L

L

L

L

H

H

H

L

H

H

L

H

H

H

L

H

H

L

H

H

L

H

H

L

A

B

C

VECTOR 1

H

H

H

L

VECTQR,2

L

L

L

H

VECTOR 3

L.

L. L

L

VECT9R4

L

H

H

VECTOR 5

H

L

H

VECTOR 6

H

H

L

H

Testability
The previous sactions described some essentials for compre"
henslve seed vector set. Variations on how fault coverage is
calculated was covered also. However, no matter how it is
calculated, fault coverage is only as good as the testability ofthe
cirouitpermlts. Using thestuck-aHailure model,thecustomer
must consider both· abSOlute and practical fault coverages'
ach!evable for his PAUHAL logic circuit design. C6rtaintesta-

11-12

COLLAPSED

D

E

bility fac;tors, such as redundancy, number of test points (outputs) ,or reconvergence, affect abSOlute (l.e.,theoreticalmB1'imum) covl!rage. Other factors, including preloadable state
machines, the amount of feedback and overall Controllability,
will affect practical coverage since many faults may be potentially
detectable but uneconomical to detect due to exceSsive VectorS
Ordifficuit to reach states. As testability is improved,abSolute
arid practical fa:iJlt coverage will usually increase.

METASTABILITY
A Study of the anomalous behavior of synchronizer circuits
Danesh M, Tavana

SYNCHRONIZERS
The design of a synchronous digital system is based on the assumption
that the maximum propagation delay ot a flip-flop and any other gates
are known. A digital system is free of hazardous race conditions and
timing anomalies if the maximum propagation delay in the system
does not exceed the clock's period. In systems where an asynchronous
input is intertaced with a clocked device suCh as a tlip-flop, the
maximum specified propagation delay of this device may no longer
be valid if certain electricat parameters are violated. Computer
peripherals, an operator's keyboard, or two independently clocked
subsystems are instances where there is a possibility oj inteliacing an
asynchrono1.)S input which will violate the synChronizer's electrical
parameters.
A populardevioe typically used in synchronized sysletrlS is the
edge-triggered register shown in figure I. The edge" triggered register
will properly synchronize the incoming data to the system's clock as
long as its Operating condHions are satisfied. Table I summarizes these
specilications torMonolithic Memories Inc:s(MMI) 74LS374 register II is
difficult to guaranteesetup and hold time requirements whE!n the data
is asynchronously inteliaced to a register. The ViOlation Of setup or hold
time in a register has a probabtiity of initiating a misbehavior termed
"Metastability:'

SYMBOL

INTRODUcrION
This ,article will surrunarize the results ot the studies performed on
synChrOnizertircults. The lntormation presented may be used by system
designers to gain insight into the anomalous behavior ot edgetriggered tlip-flops, Understanding tlip- flop behavior and applying
some simple design practices can result in an increased reliability ot
any system.

Vee

SupplyVoItage

4.5

fA

Operatinglreeair temp.

a

5

5.5

V

75

°C

t"";

Width 01 clock

15

ns

tsu

Setup time

20

ns

th

Hold time

a

METASTABILITY

ns

---

Table I

In

ihe digHal world a bH represent, the tundamental unit of measure.
The output state of any digital device is either "HIGH" (a voltage level
above V1H) or "LOW" ( a voltage level below V1L) as shown in figure 2
Under the proper operating cor'lditiqns the register in figure 1 outputs a
HIGH ora LOW on the rising edge of the clock within a nominal delay
called the "clock to out" delay If the setup and hold times are violated
the register has a small probapility of entering a third region of
operation called the "metastable" state, Metastable is a Gre"k word
meaning "in between' andH is a state between HIGH and LOW 'Even
though mosl synchronizers snap out of metastability in a short period of
time, theoretically this-state can persist indefinitely Some o.f the registers
built from older technologies had metastable states whiCh lasted as

4

VOLT
2

o
NS

long as a lew microseconds. When the QutputO{ q: de'0-ce goes ~nto
metastability the clock to out delay will be grossly affected. This may
alter the system's worst case propagation delay and potentially lead
to a system crash!
PRESET

p

DATA

COMMERCIAL
UNIT
MIN, TYP. MAX,

PARAMETER

D

Q

CLOCK

OUTPUT

F!gure2
The diagrams in tigure 3 illustrate some examples of waveforms in
the metastable condition. From the Waveforms it Is evident that the
outputs are distorted under metastablE! conditions. Figure 3d,Shows the
output 01 atypical 74LS374 regtstermanuldctured by Monolithic
Memories. Monolithic Memories lamily 01 bipolar deVice~ exhibit
superior metastable hardened performance due to their high.speed
bipolar technoloWdnd advance SchottkyTTL circuit design teChniques.
Most at these devices typically snap out 01 metastqbility in a !lashing 15
nanoseconds,

WHY THE SYNCHRONIZER FAILS
, CLEAR
Figure I

Belore attempting to explain how the synchronizer's Internal circuity
fails.!et's take a look at an interesting problem.
PROBLEM: In the SR type latch shown in figure 4 what happens if the
set (S) and the resel (R) inputs are simultan\30usly raised Irom a LOW
voltage level to a HIGH level?

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Montlllthlclltl.n
MemorIes LnJrW
11-13

Metastability
METASTABLE DETECl'OR

ANSWER: The outputs will be in a stable state of HIGH prior to the RS
transition and will quickly oscillate to a final steady state of either HIGH
or LOW (see figure 3a).1b demonstrate·this result the reader is
encouraged to do this excercise either mentally or to actually build the
circult and view the output on the oscilloscope.

This section will show how to characterize the behavior of an edge
triggered flip-flop with an asynchronous data interiace. If the setup and
hold times of the Dip-flop are satisfied the output behaves properly
(figure 60). One of the four possible events below can take place if the
Dip-flop goes metastable:

I) The output staris to make a transition but snaps back to its original
State (figUre 6b).
'.
,

(SNS/DIv.IV/DIV)

r-"\

\

2) The outputm:ixkes a ccmplefe'transition but ihemaxlrnum propaga:tion del.CI.OCX SAMPLES THE OUTPtrr (Q)AFTERA DELAY!::.

10'

fct.ocx=4MHz

loATA=IMHz

MAX

Figure 7

10'

G
fj!

If the output of the device goes into metastability it will be detected by
the comparator pair (U2) and (U3). The comparators will have complementary outputs if the output (Q) of DUT is anywhere between VIH and
VIL. The outputs of the comparators are latched by a delayed version of
the clock (l>Qock). The EXCLUSNE-NOR gate followed by the register
signal the event of metastability to an external counter.
The variable delay (l» between the two clocks will sample the output
al various locations on the time axis. As this delay is varied the event of
metastability is sampled and counted at these locations by our circuit.
Therefore the output of our Circuit measures the rate of metastability
versus time delay The reat behavior of a metaslable output can thus be
effectively characterized with this scheme. that is. we can determine the
length of time a metastable condition will persist and the density
distribution of the melastable event.
Three 74374 devices and four PAL devices are used in this experiment.
The plots of metastable failure versus time are shown in figures 8a.b. The
next section will discuss in detail the characteristics of these plots.

I
~
~

~

10'

10'

10'

10'
10'

10

Flgure8b

All of the graphs illustrated can be quantified by an equation of the
form:

EXPERIMENTAL RESULTS
Various graphs of metastability failure rate versus delay time are
illustrated in figure 8. We can conclude from these graphs that the rate
of metastability failure decreases as the sample clock ("'CLOCK)
moves farther and farther away from the DUT clock. The piclures shown
in figure 9 have captured repeated events of metastability on the
oscilloscope.
Let·s take a closer look at one 01 the graphs to examine the behavior
01 the devioe. The PALI6R4A-4 device exhibits one count per second H the
delay (<1) ts 60 nanoseconds. As the delay (<1) is decreased. the rate
Increases exponenUally untU the delay Squats 32 ns at which point the
rate fiaUens out and remains fixed. The 32 ns fonns the knee of our
graph and will be referred to as <10. The rate will remain oonstant Uthe
delay (<1) is decreased past the knee of our graph. FUrther reduction in
the delay will place the sampling clock's rising edge prior to data
tronsItions and thus the error rate vanishes to zero. The t1me at which the
rate goes to zero is marked with an (X) on the graphs. By using this l1me
(X). and another location on the graph such as the l1me where orily one
error per second occurs. we can associate an approximate range of
metastability for diUerent devices. This range of metastability is referred
to as the "mean l1me to snaP out of metastability". Prom tlie graph it is
evident that the mean l1me to snap out of metastability lor the PALI6R4A410gtc cJrcuit is the diUerenoe between 60 ns and 25 ns which is 35 ns

log FAILURE = log MAX - b(l> - "'0)
Since a naturallogartthm is a conslant multiple of base 10 logarithm we
can rewrite the above equation as:
a·lnFAlLURE =a'lnMAX-b("'-"'o)
In the above equation the MAX value is representative of the
maximum metastability failure rate in our device. This MAX vatue
is closely related to the frequency at which a metastable condition
may occur in our device. The frequency at which metastability OCcurs
is simply a constant multiple of the product of CLOCK and DATA
frequency
MAX = Kl • fCLOCK' fDATA
SubstituUng this in our ortgtnat equation we get:
a • In FAILURE = a' In(KI'fcLOC!{"fDATA) - b('" - "'0)
In FAILURE = In(KI'!cLOCK ·fDATA) - b/aC'" - l>o)
FAILURE = (KI'!CLOCK'fDATA)e- k2C l>-AO)

MonoIHhlc mMemories

11-15

Metastability
EXAMPLE

PALl6R4

For the hardware implementation in figure 10 determine the maximum clock frequency to give a typical error rate of one failure per year.
We must choose the minimum period to give an error rate of less than

ASYNCHRONOUS

PALI6R4

PALI6R4

DATA
(9.6KHz)

--

CLOCK-.J~==~---_--.J
PALI6R4A

-.Tee = SOns

CLK-OUT= 15ns
Figure

-.-

setup=25ns

10

one fatlure per year From this result we can determine the maximum
clock frequency The time 6 in the equation below will determine the
distance between clock edges. We must determine 6 from the equation
by numerical extrapolation. The system clock's period can be represented as (6 + Tcc + setup). or plugging in the numbers it is 6 + 75.
FAILURE = (Kl' fCLOCK' fDATA) e- K2(£> - £>0)

PALI6R4A·4

and plugging in the appropriate values we have:
3.2EE - B = [(lEE -7) (l/(6+75ns» (9600)Je-[(43)(£>-37)1
Solving for 6, we see that it is approxtmately 43 nanoseconds. The
system period is thus seen to be the sum of 43ns and 75ns or IlBns. The
maximum clock frequency is the inverse of the period or approximately
BMHz.

PALI6R4A·2

CONCLUSION
Synchronization of two independent pulse trains is possible through
the use of edge triggered registers. The electrical characteristics of the
flip-flop are affected when the setup and hold times of the device are
violated. This misbehavior is termed "metastability" and its probability
of occurrence can be derived for a given system. The faclors which
affect this probability and the length of time which a metastable
condition persists are influenced by the technology of the device as well
as by the circuit design techniques.
An imporiant fact which needs to be stressed is that even if a register's
output goes metastable, the system may not necessarily fail if the
regtster snaps out in time to satisfy the system's worst case timing
requirement. The following design praclices are suggested when using
synchronizers:

Figure 9 (2v/DlV, Sns/DIV)

Table 2 gives the three important parameters which can be used by
system designers to fully characterize the metastable behavior of the
mentioned devices. These parameters Can be obtained for different
devices by duplicating this experiment. An example is given below to
show how the information on table 2 may help the designer in the
design of asynchronous systems.

MANUFACl1JRER

DEVICE
PALI6R4

MMI

Kl(SeC) Kz(ns- Z)
I x 10-'
4:3

PAL I 6R4A

I x 10-'

PAL I 6R4A-2

1 x 10-'

4.3

60 (ns)
37
34.5

.64

25
31

PAL I 6R4A-4

I x 10-'

5

7l!LS374

2x 10-'

1.8

27.5

AMD

74LS374

2x 10-'

2.0

34.5-

FAIRCHILD

74F374

2x 10-'

11.5

17.5

1tIble 2

11-16

Monolithic

Try to minimize the number of locations where asynchronous signals
enter your system.
ClOCking the aSynchronous inputs through tWo pipelined registers can
greatly reduce the error rate.
Use a single clock within your local system environment. For multiple
system clocks, derive ail the clock signals from a single source to assure
synchronization between different devices within the system.
When anaiyzing the worst case timing of your system. add the time to
snap out of metastability to any register in an asynchronous data path.
A single PAL' with registers can be your best choice for state machine
analysis of asynchronous events, As the registers have virtually identical
setup times, the simultaneous observation of a metastable event by
different regtster staies are likely to be the same. Contrasted to a
distributed system of observjngregtster states with different setup times,
the PAL system of regtster states with identical setup times is a superior
synchronizer.
Avcid edge sensitive devices on the output paths of the registers
which have asynchronous inputs. The glitch crealed when the synchronizer goes metastable is enough to trigger the edge sensitive deVice,
The use of level sensitive devices is generally a better design practice.
PAL devices can be effective synchronizers where various regtstering
schemes are easily implemented.

!FIJI Memories

High-Speed Bipolar PROMs Find New
Applications As' Programmable Log icElements *
Vincent J. Coli and Frank Lee
Classic applications for bipolar PROMs include instruction
storage for microprogram control store and software for microprocessor programs. However. due to a new design methodolQgy
and state-of-the-art performance, PROMs are finding increasing

*

numbers of applications as Programmable Logic Element
(or PLE) devices. This paper will cover the architecture. applications, and software support for PLE devices.

This paper is a slightly modified version of the 'paper by the same name which appeared in the Conference Proceedings of the 9th West Coast Computer Faire,
pages 40-47; April 1984.

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MOnOllthlem
MemorIes

'Hi91t·SpeedBi~l"r PRQ"';'Fil1dN..w

Applications Asp:rogram...,ableLogic
Elements
VincentJ. Colianct Frank Lee
Classic applications for bipolar PROMs include instruction
storage for microprogram control store and software for microprocessor programs. However, due to a new design methodology and state-of-the-:art performance, PROMs are finding
increasing numbers of applications as Programmable Logic
Element (or PLE) devices. This paper will cover the architecture,
applications, and software support for PLE devices.

where '*' represents the Boolean AND operator and '/' represents the Boolean NOT or inverter operator. The fuses in the
OR-array are programmed to select the desired AND
combinations.

@

PROGRAMMABLE
LOGIC ELEMENT

Fuse-Programmable Logic Families
A typical combinatorial Boolean equation can be written in
sum-of-product form, which consists of several AND gates
summed at an ORgste: In gener~I, a set of combinatorial
Boolean equations with n inputs (10,11, ... , In-1) and m outputs
(00,01, ... , Om,--l) can~e generated through one levelef
AND gates followed by one level ()f OR gates. Custom logic·
functions can be defined using programmable logic.

INPUTS

Fuse-:programmable devices normally consist of two levels of
logic - AND-array and OR-array - as suggested above. There
are three basic types of fuse-:programmable devices - PROM
(Programmable Read Only Memory), PLA (Programmable Logic
Array), and PALl!!> (Programmable Array Logic) devices. Which
arrays are fUSErprogrammable distinguish these three types of
devices.
PLAs offer the greatest flexibility since both the AND and OR
arrays are programmable. This flexibility comes with the cost of
lower performance, higher power dissipation, and generally
higher price.
A PAL device has only the AND-array programmable; the ORarray is fixed. Each output has an OR gate associated with it
which sums a fixed number of product terms (AND combinations). Statistically there is only II limited number of product terms
in any equation. So the flexibility of a PLA is normally not
needed. This is a compromise between flexibility and cost and
performance.
The OR-array is programmable.in a PROM, but the fixed ANDarray consists of all combinations of literals foreach olthe input
variables. For example, there are 32 product terms available in a
PROM with 5 inputs a,b,c,d,e (corresponding to words Othrough
31 in the PROM memory):

a* b* c*/d* e
a*b* c* d*/e
a,* b* c* d* e

11-18

PROGRAMMABLE
LOGIC ARRAY
PROGRAMMABLE
ARRAY LOGIC

PAL

FIXED AND ARRAY
PROGRAMMABLE OR ARRAY
BOTH ARRAYS
PROGRAMMABLE

PROGRAMMABLE AND ARRAY
FIXED OR ARRAY

Figure 2•. Structural Difference Between PLE (PROM), PLA
and PAL Devices. Note thaUhe PAL and PLE Logic
Circuits Complement Each Other. The PAL Device
has Many Input Terms While the PLE Device Is Rich
in Product Terms

OUTPUTS

Figure 1. Structure of Programmable logic Devices

la*/b*/c*/d*/e
la*/b*/c*/d* e
la*Ib*Ic* d*Ie

PLE.
PLA

The'existence otall combinations of literals for all inputs makes it
possible to define functions which cannot be implemented in a
PLA or a PAL device. For example, a 5-input ExciusivErOR
(XOR) function can be implemented using sixteen product
terms. This may exceed the number of product terms available in
a PAL device and will consume too many product terms in a
PLA, but can be constructed quite efficiently in a PROM. It is
important to realize that any combination of inputs can be
decoded in a PROM as long as sufficient input pins are provided
since a PROM provides 2n product terms (where n is the number
of inputs). Another way of looking at this is that PROMs store the
logiC transfer function in a memory. The fixed AND-array (or
ANDCplane) consists fo the row and column decoders while the
fuses in the OR-array (or OR-plane) are the bits in the memory.
In a memory, a fuse blown versus a fuse intact distinguishes a
HIGH from a LOW.

Po
FIXED AND
PLANE
SIZE:n x 2"

I--,-,P2,--,~

PROGRAMMABLE
OR PLANE
SIZE: 2" x m

nxmPROM
2" PRODUCT TERMS.

(Word 0)
(Word 1)
(Word 2)
Figure 3. Block Diagram of a PROM Viewed as PLE Device.
Notice that the PLE Provides Many (2 n , Where n Is
Ihe Number of Inpuls) Product Terms. A By~Product
of this. Is Programmable Output Polarity: Either
Active-High or Active-Low Output Polarities are
Available

(Word 29)
(Word 30)
(Word 31)

/IIIonoIIthh:

IUD Memories

High.Speed Bipolar PROMs Find New Applications as PLE Devices
Due to this special characteristic of abundant product terms,
PROMs are also often used as logic devices. In this paper,
PROMs are referred to as PLE (Programmable Logic Element)
devices.

Advantages of PLE Devices
PLE devices provide a cost-effective solution for many applications. Here are just some, of the advantages of PLE devices:
1) Customizable Logic - The designeer is limited to standard
functions if SSI/MSI devices are used. The deSigner can create
his own logic chips using PLE devices.

Despite the existence of dedicated. encoders and decoders,
many of these functions are application dependent. A standard
3-to-8 decoder/demultiplexer (748138) can be used in decoding
applications. But the decoding scheme may require several
3-to-8 decoder/ demultiplexers and additional SSI OR-gates. On
the other hand, a PLE device can be customized to perform the
required decoding function with no .additional gates. Simple
decoders, such as those used for decoding memory chip selects
from address lines, can be implemented in a PLE device with five
to ten inputs. More complex decoding may require eight to
twelve inputs.

2) Design i=lexibility - Modification of design is possible even
without redesigning the PC board. For example, the address
space of a microprocessor-based system can .be reconfigured
by merely programming a new device if the decoding is
implemented in a PLE device. This feature comes in handy if you
Nant to upgrade a system which originally used 64-K Dynamic
RAMs to now use state-of-the-art 256-K Dynamic RAMs.

DATA BUS
ADDRESS BUS

3) Reduce Errors - Errors are sometimes unavoidable and
)ftentimes quite expensive. Programmable devices make it
~asier and less expensive to correct errors.

PLE~

~)

Reduction of Printed Circuit Board Space-PLE devices save
space. since several SSI/MSI functions can be
ntegrated into a single package.

~Cboard

5) Fast Turnaround Time - With existing commercial pro~rammers and development software support, a prototype of the
:ustom tailored PLE device will be ready in just a few minutes.

A G....eat Performer!

~

I.

6"

o·

-. I

0'

PLE devices also offer a very flexible solution for code conversion
applications. Translations of codeS such as from ASCII to
EBCIDIC. Binary to BCD (Binary Coded Decimal). or BCD to
Gray code can be implemented in PLEs. The 74S184 Binary-toBCD Converter is actually a 32x8 PROM.
1,1./

~ ~ ~~.~ '6 <:>

C~Ic~_
~LE

Figure 4. PLE Address Decoding Application. The P!,.E Device
Selects One Eight 2Kx8 Static RAMs by Decoding
Several Microprocessor Address Lines ..

. .

~~

Applications

leverallevelsof random logic chips can be replaced byone PLE
ogic circuit. As discussed earlier, PLE devices can implement
ogic in sumot products form.

/"":4 1
(

01
02

•

On

An-1

'LE applications include random logiC replacement, decoder/
mcoders, code converters, custom ALUs, error detection and
:orrection, look-up tables (both trigonometric and arithmetic),
lata scaling, compression arithmetic like Wallace Tree adders,
listributed arithmetic, and residue arithmetic.

'l

AO
A1

'-~~l
1:4 CODE {
SELECT

AO
A1
A2
A3

A4

OUTPUT CODE

AS

A6
A7
AS
A9

.....

.. r '~1

~
Figure 5. Two Examples ofPLE Code Converters. The Second
Example Illustrates How to Use Two Inputs as Code
Select Lines so that Four Converters can be Provided
in One PLE Devica

11-19

High-Speed Bipolar PROMs Find New Applications as PLE Devices
Standard ALUs (such as the 74S181) may not provide a very
specailized function which a particular system requires, such as
BCD arithmetic. In this case a PLE device is again a good alternative. Although the PLE device may be slower than a dedicated
ALU,the presence of this specialized function is critical. For
example, a 4-bit ALU can be constructed in a PLE device with
twelve inputs (A3-AO, B3-80, 12-10, Cin) and eight outputs (F3FO,/G,/P, Cout, A =B). Any eight functions can be implemented.
A

DATA

TOTAPI

B

Figure 7. GCR Encoder/Decoder Block Diagram

G
jO---.,P

Exclusive-OR gates, being half adders, are very prevalent in
Error Detection and Correction (EDC) schemes. Many SSI chips
are required to implement this function while PLA and PAL
devices may not provide sufficient productterms. PLE devices
are again an ideal solution.

r---_ COUT

AO~
:
iD--F

F

A3

Figure 6. Block Diagram for a 4·Blt ALU which can be Implementedln a PLE Device
Data scaling is another PLE device application. A dedicated
multiplier is not required if the scaling factor is a constant; the
prescaled result can be stored in a PLE device. Fixed-bit multipliers are typically implemented in PLE devices.

(a)
Ao.Al

Column compression technique (also called Wallace Tree
Compression) is used when expanding an array of several
smaller parallel ml,lltipliers to perform large word length multiplication. These smaller multipliers will generate partial products
(intermediate results) which must be numerically summed
according to bit significance in order to calculate the final wordlength multiplication. Many levels of 2-inpl,lt bus adders can be
used to add these partial products, but the carry propagation
delays may be too long. However, partial product adders implemented in PLE devices can do. compression of many levels
without passing carries. Thus, the summmation will be much
faster.

F=

A o ®Al®A2®A3

00

01

11

10

00

0

(i)

0

(i)

01

0

0

0

+

0

0

0

11

+

10

0

0

At A2 A3 + AD Al A2A3
AD At A2A3 + ADA, A2 A3
AOAl A 2 A3 + AOAI A2 A3

0

0

+

AoA, A2 A3 + AD Al A2 A3

A:c A3

0

0

AO

(c)

(b)
PROGRAMMABLE
OR PLANE

------FIXED AND PLANE

4

5

~

l;-c-

FUSE BLOWN

.

FUSE INTACT

9

10
11

12
13
14

15

'~~'~~yl~

" ... THE '5556, TOGETHER WITH PLEf. ORGANIZED IN A
WALUCE-TREE CONFIGUIlATlON, CAN SAIL RIGHT ALONG AT THE
RATE OF FOUR 56 X 56 MULTIPLICATIONS EVER't
MiCROSECOND ... "
Group Code Recorder (GCR) isan encoding/decoding scheme
used for error detection on tape. During a WRITE operation,
each 8-bit word is divided into two 4-bit nibbles. Both nibbles are
then encoded into 5-bit codes before being recorded onto tape.
Both S-bit codes are decoded back to the original4-bit nibbles
and then combined during a READ operation. PLE circuits are
exceptionally useful in mapping the 4-bit data to theS-bit code
and back.

11-20

I/IonoIHhio

F
A3

A2

Al

AO

UNPROGRA!MED OUTPUT
ALWAYS HIGH

(d)
Figure 8. Exclusive-OR Gates can be Implemented In PLE
Very Elficiently. A4-lnput XO.R Gate (a) Maps into a
Checkerboard Pattern In a Karnaugh Map (b) and
Requires Eight Product Terms (c). The PLE Implementation is Shown In (d). An8-input XOR Gate
Requires Sixteen Product Terms

m

lIIIemo,.les

High.Speed Bipolar PROMs Find New Applications as PLE Devices
In many applications, the speed ofthe converging series used to
generate the trigonometric functions is too slow and the
accuracy obtained by direct table look-up requires too much
hardware. A good compromise between speed and hardware is
to store anapproximation to the function in a PLE device. Then
use this approximation as a starting point for an iterative
algorithm (such as Newton-Raphson) to obtain additional
accuracy. High-Speed division, multiplication, and square-root
calculations can be performed in a similar manner.

INTEGER

INPUT

INTEGER

Figure 10. Architecture 01 a system Based on RNS. An Integer
Number Is Converted to RNS Representallon Using
PLE Devices, Then the RNS Arlthmellc 18 Performed
Using Some Other PLE Dev/ces, and Finally the
RNS Result Is Converted Back to Integer Representation Again Using PLE Devices

CONTROL

OUTPUT

:Igure 9. PLE Look-Up Tables and Iteration Loops can be
Used to Generate Very Accurate Trigonometric and
Arithmetic Functions. ,An Approximation to the Function Is Stored and Additional Accuracy Is Gained
Using Iteration Operations

Restrictions
The basic restrictions for using PLE devices to replace SSI/MSI
parts are:

)istributed arithmetic is used for performing convolution opertions without using multiplier/accumulators. If the coefficients
re constant, a look-up table for convolution can be stored in a
'LE device, thus replacing the multiplier.
tesidue arithmetic (also called Carry-Independant arithmetic)
i a technique used to performvery fast integer arithmetic. High
peed is achieved by using numbers in residue representation
D that the sequential delay of carries on digits of higher
ignificance is eliminated. A Residue Numbering System (RNS)
; determined using an optimum moduli when designing the
(stem. Conversion to and from residue representation are
asic mapping functions which can be conveniently done in a
LE device. Also, since operations in residue arithmetic are
erformed using modulo addition and multiplication without
mies, these operations can also be done using PLE devices. In
eneral, residue arithmetic should only be used for integer
'ithmetic which requires intensive operations.

IIIonoIlthlc

1) Since a memory element has a product term lor every combination of literals of all the input terms, static hazard is normally
unavoidable. For example, there are 5 inputs available in a 32x 8
PROM. In order to generate a function like:
f = a' b'

c' d

The actual implementation inside the PROM will be:
f = a' b' c' dOle + a' b' c' d' e

If a = b = c = d = HIGH,according to the first equation, we shall
expect I to remain HIGH independent of e changing. In the
actual PROM implementaton, there will be no hazard if e stays
either HIGH or LOW. ,But if e changes, depending on whether e
or /e will occur first, there exists the possibility that both product
terms in the second equation will be LOW momentarily, which
may cause a static logic hazard (HIGH to LOW to HIGH) for f.
Thishazard is commonly called a "glitch". Static hazards are not
a problem for many applications, like those offered in this paper,
but extreme care must be taken if the output of a PLE device is
used to strobe another device.

m

Memo,.les

11-21

High-Speed Bipolar PROMs Find New Applications as PLE Devices
PLEASM Software Support

•
-----------------------------0
00
0
0
0
0
0

ADDRESS

01

d

c

b

a

f

0
0

0
0

0
0

0

1

1
0

0

02

oc

0

0
0
1
1

0
1
0
1

0

0
0
0
1
1
1

1
1

1

OD
OB
OF
10
11
12

0

0
1
0

1D
11
lP

1
1
1

1
1
0
0
0

1

1
1

1
1
1
0
0
0

1
1
1

0

1

0
1
1

1
0
1

0

0
0
1
0
0
0

0
0
1

Monolithic Memories has developed a software tool to assist in
designing and programming PROMs as PLE devices. This
package, called "PLEASM" (PLE Assembler), is available for
several computers including the VAXNMS and IBM PC/DOS.
PLEASM converts design equations (Boolean and arithmetic)
into truth tables and formats compatible with PROM programmers. A simulator is also provided to test a design using a
Function Table before actually programming the PLE device.
The PLEASM operators are listed below and the PLEASM
catalog of operations is given on the next page. A sample PLE
Design Specification (source code for PLEASM software) with
PLEASM outputs is given in Figure 12. PLEASM software may
be requested through the Monolithic Memories IdeaLogic
Exchange.

Operators
ADD
OAT

------------------------------

(In hierarchy of evaluation)

Comment follows
Dot operator (pin list or arithmetic operator follows)
Address pins (Inputs)
Data pins (Outputs)
Delimiter, separates binary bits (MSB first)
Equality (combinatorial)

BOOLEAN OPERATORS
Figure 11. This Truth Table Graphically Illustrates the Possible
Glitch (HIGH to LOW to HIGH Hazard) for the
Function f = a* b* c* d Implemented In a 32x8 PROM.
Address OF and 1F ContaIn a 1 while All Other
Locations Contain a 0 for Output f.lf Address Input e
Should Change, the PROM Decoders Could Momentarily Selct a Location Containing a 0

/
•

Complement, prefix to a pin name
AND (product)
+ OR (sum)
: +: XOR (exclusive or)
: .: XNOR (exclusive nor)
ARITHMETIC OPERATORS
. •. Multiply (numeric multiplication)

. +. Plus (numeric addition)
2) Although PROMs are available with registered outputs,
internal feedback from the outputs and buried registers are not
yet available in PROMs. External connections from some
outputs to inputs must be made for applications which require
feedback (such as in state machines). However, Registered
PROMs without feedback are useful for pipelining (dverlap
instruction fetch and execution) in order to increase system
throughput.

11-22

Monolithic Memories PLEASM version 1.2D@ copyright 1984
Monolithic Memories
PLEASM C
E
T
B

PLE Assembler - provides the following options:

Catalog
Echo Input
Truth Table
Brief Table-

Prints the PLEASM catalog of operations
Prints the PLE design specifications
Prints the entire truth table
Prints only used addresses in the truth
table

H Hex Table

-

S Simulate

- Exercises the function table in the
logic equations

I Intel Hex

- Generates INTEL HEX programming
format

A ASCII Hex

- Generates ASCII HEX programming
format

Q Quit

- Exits PLEASM

MonoIHhlcWMemories

Prints the truth table in HEX form

High-Speed Bipolar.PROMs Find New Applications as PLE Devices
PLESP8

PLE DESIGN SPECIFICATION
VINCENT COLI 10/03/82

psoao

BASIC GATES

BASIC GATES
.ADD to Xl X2 I3

MMI SANTA CLARA, CALIFORNIA

. OAT 01 02 ,03 04 05 06 07 08

.ADD 10 11 12 13 14
.OAT 0102 0) 04 05'06 07 08

ADD

01 •

IO

02 .. /10

03 •

IO

O' •

IO

. . · ·
Il

+

11

05 == /10

+ In

06

1>

<2

IIQ

III

12
12

+

13

+

13

+

INVERTER

OR GATE

;

NAND GATE

*/13

1>

I2

I3

/14

07 •

IO

08 =

10 : "': 11 :*: I2 :*: 13 :*: 14

Il

I

;

/12

1
2
3

•
•
•
5

7
8

NOR GATE

14

EXCLUSIVE OR GATE

10
11
12
13

EXCLUSIVE NOR GATE

,.
,.

FUNCTION TABLE

15

10 11 12 13 ·'14 01 02 03 04 05 06 07 08
OUTPUTS
FROM BASIC GATES
- - 1NV
;~~\~~! 8UF
AND OR NAND NOR XOR XNOR
COMMENTS
------------------------,--------------------------------------------LLLLL
ALL ZEROS
HHHHH

17
18

"

20
21
22
23
2.
25
26
27

ALL ONES
ODD CHECKERBOARD
EVEN CHECKERBOARD

BLHtH
LHLHL

HEX DATA

~-

I4

+ /14

1>

BUFFER

; AND GATE

+ /13

REX ADDRESS

------------------ -------------0
000

;

I4

+ /12

"

------------------------------------------------------------- -------DESCRIPTION

2.

THIS EXAMPLE ILLUSTRATES THE USE OF PLEs TO IMPLEMENT THE BASIC, GATES:
BUFFER, INVERTER"AND GATE, OR GATE, NAND GATE, NOR GATE', EXCLUSIVE OR
GATE, AND E:ttCLUSIVE NOR_ GATE.

2.
30
31

NOTE ALSO THAT THREE..,STATE OUTPUTS ARE PROVIDED WITH ONE ACTIVE LOW
OUTPUT ENA'BLE CONTROL (IE) •
PLEASM GENERATES THE PROM TRUTH, TABLE FROM THE LOGIC EQUATIONS" AND
SIMULATES THE FUNCT'ION TABLE IN THE LOGiC EQUATIONS.

Figure 128. PLE Design Specification. This Is the Source Code
for PLEASM Software. PLEASM Software Generates the Truth Table and ProgrammirigFonnats
from the Equations. PLEASM Software Also
Exercises the Function Table in the Equation and
Reports Errors
BASIC GATES

001
002
003
00.
005
00.
007
008
00'

32
D9

,.

DA
DA

19
lA
D'
DA

,.

OOA

lA

008

D9

ooe

000

lA
D'

,.
,.

OOE
OOF

DA

010

DA

on

012
013
01'
015
01'
017
018
01.
OlA

01.

lA
D'
lA
D'
DA

,.
,.
,.

lA

D'

DA

Ole
OlD
OlE

DA

01'

CD

lA

HEX CROCK SUM '"' OOF3C

Figure 12c. Hex Table. PLEASM SoltwareGenerates This
Truth Table in Hexadecimal Fonn for Verification
of Locations In the PLE

32 D9 DA 19 DA 19 1A 09 DA 19 1A 09 lA 09'OA' 19
DA,19 lA D9 lA· 09 CA' 19 lA 09 DA 19 DA 19 1A CD

.ADO III 11.-x2 13 14
.OAT 01 02 03 04,05 06,07 08

OOF3C
ADD

AO Al A'2 A) 'A4

010203,04 05 06 07'68

--------------------------------,--------------0
1
2
3

L
H
L
H
L

5
6
7

H

,
•9

L
H

L
L

•
H
L
L
H

"

L

L
L
L
L
H

H

H
H
L

L

L
H

L
H
H

L

L

R

18

H
L
H
L
H
L

19

ft

20
21
22
23
2'
2S
26
27
28
2.
30
31

L
H
L

L
H
H
L
L
H
H
L
L
H
H
L
L
H
H

10

11
12
13
14
H
16

17

•

L

L
L
H
H

•
L
L
L
L

H
H
H

L

L
L
L
L
L
L
L
H
H

•
H
H
H
H
H
L
L
L
L
L
L
L
L

L
L
L
L
L

L
L
L
L

L
L
L

L
L
L
L

•

L

H
L
H
L
H
L
H
L

•
L
H
L
H
L
H
L
H

L

"
•
L

L
H
L

L
H
L

H

H
H
H
H
H

H

H

L
H
L
H
L
H
L
H
L
H
L
H
L

H

H

L
H

L

••
L

H

L

H

•
H
H
H
H
H
H
H
H
H

H

L
H
L

•
L
H
L

L
L
L H
L H
L H
L H
L H
L ·H
L H
L H
L
H
L H
L
L H
L H
L H
L H
L H
L
L H
L
L H
L H
L .H
L
H
L H
L H
L H

•"
H
H
H
H
H

L
L
L
L
L
L

L
L
L

H

••
H
H
H
H
H

••
• •
H

H
H
H

•
H
H
H

L

L
L
L
L

L
L
L
L
L
L
L
L
L
L

L
H

L

••
H

L

L

H.

H

L
L
H

L
H

H

H

..

L
L
H
L
H
H
L
H
L
L

L
L

L
H
H
L

•
L

L

•

L

H

L
H
H
L
L
H

L
H
H
L
L

H
L.

H
L

L
L

L

•
••
•
------'"----------------..;---------'"--------------"
H
L
H
L

L
L
L

• • " • ••
L

L

L
H

H

H
H
H

H
L

L

L
L

U

H

•• ••
•

..

H

'H

H
L

L

L
L
L
L
L
L

L

H

HEX CffECIC SUM' -,., OOF,)C

'Igure 12b. Truth Table. PLEASM Software GenerateiThis
Truth Table which can be Used for Verifying Your
Design

Figure 12d. ASCII Hex Programming Fonnat. PLEASMSoftware Generates this· ASCII Hex. Programming
Fonnat with Hex Check Sum. Control Characters
are Included so that the Information can be DownLoaded Directly to a PROM Programmer

.l000000032D9DAUDAl9lAD9DAl9lAD91AD9DAl940
.,OOOlOOODAl9lAD9lAD9DAl9lAD9DAl9DAl9lA(D54
: oOOOOOOlFF

Figure 12e. Intel Hex. Programming Format. PLEASM Software Generates .thls Intel H.ex Programming
Fonnat with a Hex Check Sum Following Every
16 Bytes of Data

High-Speed Bipolar PROMs.Find New Applications 88 PLE Devices
PLEFamily
Monolithic Memories carries a family of fast PROMs which can
be used as Memory or PLE devices. Since the critical parameter
for logic applications is speed, our series of fast PROMs have

worst-case memory access times (or propagation delays) ranging from 15 ns for small PROMs to 40 ns for large PROMs. The
Logic Symbols for four of the PLE devices are given in Figure 13
and a summary of the PLE family is given below:

PLE Selection Guide
PART
NUMBER

INPUTS

PRODUCT
TERMS

OUTPUTS

OUTPUT
REGISTERS

tpD (ns)
MAX-

PLE5P8

5

8

32

25

PLE5P8A

5

8

32

15

PLE8P4

8

4

256

30

PLE8P8

8

8

256

28

PLE9P4

9

4

512

35

PLE9P8

9

8

512

30

PLE10P4

10

4

1024

35

PLE10P8

10

8

1024

35t

PLE11P4

11

4

2048

35

PLE11P8

11

8

2048

35

PLE12P4

12

4

4096

35

PLE12P8

12

8

4096

40

PLE9R8

9

8

512

8

15

PLE10R8

10

8

1024

8

15

PLE11RA8

11

8

2048

8

15

PLE11RS8

11

8

2048

8

15

.

*Clock to output time for registered outputs

PLE1OP4

t Preliminary data.

PLE5P8/A

NOTE: Commercial limits specified.

Acknowledgements
Several ofthe designs discussed in this paper were proposed by
our good friend and colleague Ulrik Mueller, who is now stUdying Computer Science in his native country,. Denmark, and our
Monolithic Memories Pal Zahir Ebrahim. Special thanks also go
to Ranjit Padmanabhan for writing the PLEASM simulator.

Summary
There are many interesting applications for high-speed PROMs
used as PLE devices. A software package called "PLEASM"
software is available as a development tool.

PLE12P4
PLE11P4

References
1. "PAL Programmable Array Logic Handbook", 3rd edition,
J. Birkner, V. Coli, Monolithic Memories, Inc.
2. "Systems Design Handbook", Monolithic Memories, Inc;
3. "BlPolar LSI 1984 Databook", .5th edition, Monolithic Memories, Inc.
.
4. "PROMs and PLEs: An Application Perspective", Z. Ebrahim,
Monolithic Memories Application Note AN-126.
5. "An Introduction to Arithmetic for Digital Designers",
S. Waser, M.J. Flynn, Holt, Rinehart & Winston, N.Y., 1982.

11-24

lIIIonoIlthk:

Figure 13. Four Sample PLE LogiC Symbols

m

Memories

ABELTM, A Complete Design Tool
For Programmable Logic
Michael J. Holley
DATA I/O
10525 Willows Rd. N.E.
Redmond, WA 98073-9746

As the use of PAL@ and PLE devices (PROMs) increases. the
need for high-level design tools becomes necessary. Designers
need easier, faster, and more efficient ways to design with such
programmable devices. With the more complex devices currently
being introduced to the market, this need is even greater.
Additionally, a designer should be able to specify logic designs
in a way that makes sense in engineering terms; he or she should
not have to learn a new way of thinking about designs.

6809 MEMORY ADDRESS DECODER
Address decoding is a typical application of programmable
logic devices, and the following describes the ABELTM
implementation of such a design.
A15
ROM 1
A14
ROM2
A13

ABEL'·, a complete logic design tool for PAL devices, PLE
devices and FPLA devices meets these requirements. ABEL'·
incorporates a high-level design language and a set of software
programs that process logic designs to give correct and efficient
designs.
The ABEL 1M design language offers structures familiar to
designers: state diagrams, truth tables, and Boolean
equations. The designer can choose any ofthese structures
or combine them to describe a design. Macros and
directives are also available to simplify complex designs.
The ABELTt. software programs process designs described
with the high-level language. Processing includes syntax
checking; automatic logic reduction, automatic design
simulation, verification that a given design can be
implemented in a chosen device, and automaticgeneration
of design documentation.
To use ABELTr.I, the designer uses an editor to create a
source file containing an ABEL1M design description. He
then pro.cesses the source file with the ABELTM software
programs to produce a programmer load file. The
programmer load file is used by logic and PLE programmers
to program devices. S.everal programmer load file formats
are supported by ABEL1M so that different programmers may
be used;
The source file created by the deSigner must contain test
vectors if simulation is to be performed, Test vectors
describe the desired (expected) input-to-output function of
the de.sign in a truth table format. The ABEL1M simulator
applie.s the inputs contained in the test vectors to the deSign
and checks the obtained outputs against the expected
outputs in the vectors. If the outputs obtained during
simulation do not match those specified in the test vectors,
an error is reported.
Following are two designs described in the ABEL'· design
language. These designs would be processed to verify their
correctness and to reduce the number of terms required to
implementthem. The first design is for a PAL device, the second
fora PLE logic circuil.

10
A12
DRAM
Al1
A10

IROM1IROM2~
FFFF

F800

F000

1/0

E800

DRAM::J

E000

0000

Figure 1. Block Diagram: 6809 Memory Address Decoder

Design Specification
Figure 1 shows a block diagram for the design and a
continuous block of· memory divided into sections
containing dynamic RAM (DRAM), 110 (10), and two sections
of ROM (ROM1 and ROM2). The purpose of this decoder is
tomonitorthe six high-order bits (A 15-A 10) of a sixteen-bit
address bus and select the correct section of memory based
on the value oftheseaddress bits. To perform this lunction,
a simple decoder with six inputs and four outputs is
designed with a 14L4 PAL device.
Table 1 shows the .address ranges associated with each
section of memory. These address ranges can also be seen
in figure 1.

ROMI
ROM2

Address
10
DRAM
Figure 2. Simplified Block Diagram: 6809 Memory Addrass
Decoder

Design Method
Figure 2 shows a simplified block diagram for the address
decoder. The address decoder is implemented with simple

IBEL'· is a trademark 01 DATA liD.
AL@ is a registered trademark of Monolithic Memo'ries.

2175 Mllislon College Blvd. Santa Clara, CA

onollg./o

lWX:'910-338-2376 . •
••

95054-1.59~ Tel: (408) 970-9700 TWX: 910-3;18-2374

mor...

m. ·.
11-25

ABELTM, A Complete Design Tool For Programmable Logic

Boolean equations employing both relational and logical
operators as shown in figure 3. A significant amount of
simplification is achieved by grouping the address bits into
a set named Address. The lower-order ten address bits that
are not used for the address decode are given "don't c.are"
values in the address set. Inthisway, the designer indicates
that the address in the overall design (that beyond the
decoder) contains .sixteen bits, but that bits ()'9 do not affect
the decode of that address. This is opposed to simply
defining the set as, Address = [A15,A 14,A13,A 12,A 11,A 10),
which ignores the existence of the lower-orderbits,
Specifying all 16 address lines as members of the addres.s
set also allows full 16-bit comparisons of the address value
against the ranges shown in table 1.
Test Vectors

In this design, the test vectors are a straightforward listing
of the values that must appear on the output lines for
specific address values. The address values are specified
in hexadecimal notation on the left side of the ".>""
symbol. Input to a design always appear on the left side

Address Range (hex)

Memory Section

OOOO-DFFF
EOOO-E7FF
FOOO-F7FF
FBOO-FFFF

DRAM
I/O
ROM2
ROMi

Table 1. Address Range. fOr 8809 Controller

of the test vectors. The expected outputs are specified to
the right of the "- >" symbol. The designer chose in this case
to use the symbols Hand L instead of the binary values 1
and 0 to describe the outputs. The correspondence between
the symbols and the binary values was defined in the
constant declaration section of the source file, just above
the section labeled equations.

module m6809a
title '6809 memory decode
Jean Designer
Data liD Corp Redmond WA

24 Feb 1984'

U09
device 'P14L4';
A15,A14,A13,A12,All,Al0 pin 1,2,3,4,5,6;
ROM1,IO,ROM2,DRAM
pin 14,15,16,17;
H,L,X
Address

1,0,.X.;
[A15, A14, A13, A12, All, Al0, X, X,

equations
!DRAM
! IO

!ROM2
!ROMl

-

(Address

(=

"hDFFF);

(Address

)=

"hEOOO) & (Address

(Address ) = "'hFOOO)
(Address

)=

&

X, X, X, X,

(Address

..... hF800);

Figure 3. Source File: 8809 Memory Address Decoder

Monolithic W.emorle.

X, X, X, X];

(=

..... hE7FF);

(=

..... hF7FF);

ABELTM, A Complete Design Tool For Programmable Logic
Seven·Segment Display Decoder
This display decoder decodes a four-bit binary number to
display the decimal equivalent on a seven-segment LED
display. The design incorporates the ABELTM truth table
format and is implemented on a RA5PS PLE.
ena

a
b
00

e

01
d

02

e
03
9

a
9

d
Figure 4. Block Diagram: Seven-Segment Display Decoder

I)eslgn Specification

Figure 4 shows a block diagram for the decoder design and
:I drawing of the display with each of the seven segments
abeled to correspond to the decoder outputs. To light up
iny one of the segments, the corresponding line must be
friven low. Four Input lines DO-03 are decoded to drive the
:orrect output lines. The outputs are named a, b, e, d, e,
" and g corresponding to the display segments. All outputs
ire active low. An enable, ena, Is provided. When ena is low,
he decoder is enabled; when ena is high, all outputs are
friven to high impedance.

and OFF are declared so that the design can be described
in terms of turning a segment on or off. To turn a segment
6n, the appropriate line must be driven low, thus ON is
declared as 0 and OFF as 1.
The design is described in two sections: an equations
section and a truth table section. The decoding function is
described with a truth table that specifies the outputs
required for each combination of inputs. The first line of the
truth table (the truth table header) names the Inputs and
outputs. In this example, the inputs are contained in the set
named bed and the outputs are in led. The body of the truth
table defines the input-to-output function. Because the
design decodes a number to a seven-segment display,
values for bed are expressed as decimal numbers, and
values for led are expressed with the constants ON and OFF
that were defined in the declarations section of the source
file. This makes the truth table easy to read and understand;
the incoming value is a number and the outputs are on and
off Signals to the LED.
The input and output values could have just as easily been
described in another form. Take for example the line in the
truth table:
5 ->[ON,OFF,ON,ON,OFF,ON,ON)
This could have been written in the equivalent form:
[0,1,0,1)- > 36
In this second form, 5 was expressed as a set containing
binary values, and the LED set was converted to decimal.
(Remember that ONwas defined as 0 and OFF was defined
as 1.) Either of the two forms is valid, but the first is more
appropriate for this design. The first form can be read as,
"the number five turns on the first segment, turns off the
second, ... " whereas the second form cannot be so easily
translated into terms meaningful for this design.
Test Vectors
The test vectors for this design test the decoder outputs
for the, ten valid combinations of input bits_ The enable is
also tested.by setting ena high for the different
combinations. All outputs should be at high impedance
whenever ena is high. If they are not, an error has occurred.

Summary

ena

)eslgn Method

Two designs described with the ABEL" design language have
been shown. The first design shows how Boolean equations with
logical and relational operators are used to describe an address
decoder. The Second design shows how a truth table describes a
seven~segment display decoder deSign for a PLE logiC circuit. In
both designs,test vectors were written to testthefunction ofthe
design using ABEL"'s simulator. In addition to 'the Boolean
equations and truth table shown in these examples, ABEL"
features a state diagram structure. The state diagram allows the
designer to fUllY describe state machines in terms of their states
and state transitions.

=igures 5 and 6 show the simplified block diagram and the
lource file for the ABELTM Implementation of the display
lecoder. The FLAG statement is used to make sure that the
)rogrammer load file Is in the Motorola Exorciser format.
-he binary inputs and the decoded outputs are grouped into
he sets bed and led to simplify notation. The constants ON

Regardless of the method used to describe logic, ABELTM's
automatic logic reduction and simulation ensure that the
design uses as few terms as possible and that it operates
as the designer intended. The end results are savings in
time, devices, board space, and money.

bed

led

Figure 5. Simplified Block Diagram: Seven-8egment Display
Decoder

IIIIonoIHhlcW Memories

11-27

ABELTM, A Complete Design Tool For Programmable Logic

m.odule
bcd7rom fl<1l!l ' ~dS21
ti.tle 'seven segment display decoder
Data I/O Corp
Redmond WA
1.6 Mar 1984'

a
BCD-1:o-sEwen-segmeYlt decoder simi lar to the 7449
fl

g

Ib

et d

Ie

segment identificatic.n

II

:

....
U6

device

D3,D2,D1,DO
a,b,c,d,e,f,g
ena

'RASPS';
pin 10,11,12,13;
pin 1,2,3,4,S,6,7;
piYI lS;

bcd
led

[D3,D2,Dl,DO];
[a, b,c, d, e, f, g] ;

ON,OFF
L, H, X, Z

0, 1 ;
O,l,.X.,.Z.;

.

for common anode LEDs

truth _table (bcd -) led)
inplJt
out puts
f
b
e
d
e
a
9
-) [ ON,
ON,
ON,
ON, OFF];
0
ON,
ON,
ON,
ON, OFF, OFF, OFF, OFF);
1 -} [OFF,
ON);
-) [ ON,
ON,
ON, OFF,
2
ON, OFF,
ON);
-} [ ON,
ON,
ON,
ON, OFF, OFF,
3
ON];
ON,
4 -} [OFF,
ON,
ON, OFF, OFF,
ON];
ON,
ON,
ON, OFF,
S -) [ ON, OFF,
ON);
ON,
ON,
ON,
ON,
6 -) [ ON, OFF,
ON,
ON, OFF, OFF, OFF, OFF];
7 -) [ ON,
ON);
ON,
ON,
ON,
ON,
ON,
S -) [ ON,
ONJ;
ON, OFF,
ON,
ON,
9 -} [ ON,
Oil!,
-) led)
test _vectors «(ena,bedJ
outputs
" iYlputs
e
b
e
d
a
[L,l)
-} [OFF,
ON,
ON, OFF, OFF,
-} [ ON,
ON,
ON,
ON, OFF,
[L,2J
[L,3)
-) t ON,
ON,
ON,
ON, OFF,
-} [OFF,
[L,4J
ON,
ON., OFF, OFF,
[L,S]
ON,
ON, OFF,
-} [ ON, OFF,
[L,6) . .,-) [ ON, OFF,
ON,
ON,
ON,
[L.7]
-) [ ON,
ON, OFF, OFF,
ON,
-} [ ON,
ON,
[L,SJ
ON,
ON,
ON,
(L,9]
-) [ ON,
ON,
ON, OFF,
ON,
-} [ ON,
ON,
ON,
ON,
ON,
[L, OJ.
-} [
[H,SJ
Z,
Z,
Z,
Z,
Z,
[H,9]
-} [
Z,
Z,
Z,
Z,
Z,
[H,O)
-) [
Z,
Z,
Z,
Z,
Z,
end
bed7rom

f
9
OFF, OFFJ;
ON] ;
OFF,
OFF,
ONJ;
ON];
ON,
ON);
ON,
ON,
ONJ;
OFF, OFF];
ON];
ON,
ON];
ON,
ON, OFF);
Z,
ZJ;
Z] ;
Z,
Z] ;
Z,

Figure 6 •. Source FII.•:. Seven-Segmenl DispllllY Decoder

11-28

Monollth/o W.emorle$

CUPL.:

M

The Universal Compiler
For
Programmable Logic

CUPL is the first software CAD tool designed especially for the support

of all programmable logic devices (PLDs), including PALs and PROMs. It
was developed specifically for YOU, the Hardware Design Engineer. Each
feature of the CUPL language has been chosen to make using programmable
logic easier and faster than conventional TTL logic design.
MAJQR

FEATURES Qf

~

1. UNIVERSAL

a.

PRODUCT SUPPORT:
CUPL supports products from every
manufacturer of programmable logic. With CUPL you are free to
use not only PALS, but also other programmable logic devices.

b.

PALASM CONVERSIONS:
CUPL has a PALASM to CUPL language
translator which al10ws for an easy tQnversion from your
previous PALASM designs to CUPL.

c.

LOGIC PROGRAMMER COMPATIBILITY: CUPL produces a standard JEDEC
download file and is compatible with any logic programmer that
uses JEDEC files.

2. HIGH LEVEL LANGUAGE
High Level Language means that the software has features that allow you
to work in terms that are more 1 ike the way you think than 1 ike the
final PLD programming pattern. Examples of these are:
a.

FLEXIBLE INPUT: CUPL gives the engineer complete freedom in
entering logic descriptions for their design:
- EQUATIONS
- TRUTH TABLES
- STATE MACHINE SYNTAX

b.

EXPRESSION SUBSTITUTION: This allows you to pick a name for an
equation and then, rather than write the equation each time it
is used, you need only use the name. CUPL will properly
substitute the equation during the compile process.

ASSISTED TECH NOLD.C3V
2361 Zanker Rd"Suite 150, San Jose, CA 95131 (408) 942-8787;

11-29

CUPLTM Universal Compiler for Programmable Logic

c.

SHORTHAND FEATURES: Instead of wi: iUng out fully expanded
equations CUPL provides various shorthand capabilities such as:
- LIST NOTATION:

Rather than
[A7,A6,A5,A4,A3,.A2,Al,AO]
CUPL only requires
[A7 •• 0]

- BIT FIELDS: A group of bits may be assigned to a name,
asin F!ELD ADDR= [A7 •• 0]
Then ADDR may· be. used in other expressions
- RANGE FUNCTION:

A15 & lA14 i
A15 & A14 & lAB i
A15 & A14 & A13 & 1A12
ADDR: [8000 •• EFFFl
CUPL only requires

Rather than

- THE DISTRIBUTIVEPROPERTY:
From Boolean Algebra, where
is replaced by

A. & (B i C)
A & B i A & C

- DeMORGAN'S THEOREM:
From Boolean Algebra, where .! (A
is replaced by
!A i

&

B)
!B

3. SELF DOCUMENTING
CUPL provides a template file which provides a standard "fill-in-theblanks" documentation system that is uniform among all CUPL users. Also,
CUPL allows for free form comments through out your work so there can be
detailed explanations included in each part of the project.
4. ERROR CHECKING
CUPL includes a comprehensive error checking capability with detailed
error messages designed to lead you to the source of the problem.
5. LOGIC REDUCTION
CUPL contains the fastest and most powerful minimizer offered for
Programmable Logic equation reduction. The minimizer allows the choice
of various levelS of minimization ranging from just fitting into the
target device to the absolute minimum.
6. SIMULATION
With CSIM, the CUPL Simulator, you can simulate your logic prior to
programming an actual device. Not only can this save devices but it can
help in debugging a system level problem.

11-30

MonollthlcW Memories

CUPLTM Universal Compiler for Programmable Logic

7. TEST VECTOR GENERATION
Once the stimulus/response function table information has been entered
into the simulator,.CSIM will verify the associated test vectors and
append them to the JEDEC file for downloading to the logic programmer.
The programmer w~ll verify not only the fuse map, but also the
functionality of the PLD, giving you added confidence in the operation
of your custom part.
8. EXPANDABILITY
CUPL is designed for growth so as new PALs and other devices are
introduced you will be kept current with updated device libraries and
product enhancements.
DESIGN EXAMPLE

llSlNG.~

In the following design example, a single PAL (or PROM) is used to
replace four TTL. packages on the interface card for an IBM-PC computer.
ThePrototypeIlO Channel Interface Card, as supplied by IBM, uses four
SSI padkages to decode the ten bit I/O address and control the direction
and enable for the bus buffer on the PCB. The PAL approach conserves
real estate and also adds flexibility to decode not only the preassigned address, but the ability to change the board address to any
location in the I/O map by merely replacing the programmable device.
1.

CIRCUIT OPERATION

The inputs to the decoding logiC are the expansion bus addresses AO thru
A9. The logic compares the address on the expansion bus and asserts the
"IO_DECODE" signal when the cor.rect address range of3FO-3FF is seen.
In.addition,. the "ENABLE" signal is also asserted i f either the. I/O READ
or I/O WRITE signals are active during this time. The READ signal,
which controls the direction of the data bus buffer, is asserted
whenever I/O READ is active and AEN, the DMA Address enable signal is
inactive. The AEN signal is negated when the microprocessor has control
of the address bus and is generating an I/O cycle.

IIIIonollthlCW Memories

11-31

CUPLTM Universal Compiler for Programmable Logic

2.

DESIGN METHOD

First, all device pins are assigned in the logic description file (see
figure 1) using CUPL's pin declaration statements. Note the use of
indexed variables for the address bus allows a simple assignment for
pins 1 thru S. The active polarity for input and output pins are made
in these declarations, so the designer need only be concerned with the
logic instead of vol tage levels.
The address bus is assigned a name using the FIELD statement. This lets
the designer then describe the desired address range with the single
equation:
range

= ioadr:

£300 •• 31F] ;

instead of the difficult to understand
range

= a9

& as & !a7 & !a6 & !as ;

This (ange expression is then used in the output equation for IO_DECODE
and ENABLE. Since ENABLE may be asserted whenever lOR or lOW are true,
the int~rmediate variable IOREQ is created to define this condition.
The resultant CUPL equation for ENABLE is simply
enable = range & ioreq ;
Finally, the READ signal is created using the active lOR and the
inactive AEN signals .as follows:
read

= ior

& !aen ;

Note that for a device such as the PAL16LS which has a fixed inverting
buffer on all of its output pins, CUPL will automatically convert the
logic equations when ~n output is desired to be active-level HI, as with
the READ output above.
3•

CUPL OUTPUT FIL·ES

CUPL will create a standard JEDEC output file which is compatible with
most 199ic programmers. A simple serial download link is all that is
usually required to transfer the fuse information to the programmer. In
addition, CUPL generates an extensive documentation file which assists
the d~signer in analyzing his/her design.
Figure 2 shows a small
section of this file, illustrating such features as pin and variable
names, product term utilization, and other information.

11-32

Monolithic WMemories

CUPLTM Universal Compiler for Programmable Logic

PARTNO
NAME
DATE
REV
DESIGNER
COMPANY
ASSEMBLY
LOCATION

P90001234
peIO ;
02114/95 ;

01 ;
Kahl/Osann ;
Assisted Technology
PC Proto Board ;
U2 ;

1********************************************************************1
1* This device provides a cIne-chip 110 interface fc.r an eQ~tivaley,t *1
1* of the IBM-PC proto board. This logic description may be placed *1
1* in either a PROM or PAL without alteration.
*1
1********************************************************************1
1* Allowable Target Device Types: PAL--) PAL16L8, PAL16P8
*1
1*
PROM-) PLE12P4
*1
1********************************************************************1
1**

Inputs

**1

PIN [1. • 8J
PIN 9
PIN 1_7
PIN 18

1**

1*
1*
1*
1*

[a2 •• 9J
ael...
! iot'
! iClw

Oll-t puts

CPU Address bits 0 thrll 9 *1
DMA Address Enable *1
I/O Read Strobe
(act ive La>
lID Write Strobe (active La>

*1
*1

**1

PIN 12:
PIN 13
PIN 1A

t'ead
! er,able
! i CI dece.de

-

1* Direction Control For Bus BufTer *1
I-II- Enable For Bus BufTer *1
1* Dece.ded lID Strobe for Dr, B.::oard Use *1

1** Declarations and Intermediate Variable Definitions **1
field

ioad~'

iot'

1* Name the lID Address Bus "ioadr" *1

ic.w ;

1* Define lID Request *1

ioadr:[300 •• 31FJ & !aen ;

range

1**

"*

[a9 •• 2J

Logic Equations

1* Decoded lID Address Range and *1
1* not DMA cycle *1

**1

enable - range & ioreq

read -

ior & !aen

1* Change the intermediate variable Urange" for other lID Locations *1
Figure 1.

Monolithic WMemories

11-33

CUPLTlo1 Universal Compiler for Programmable logic

2.02a
p1blB DL1B-c-18-5
P90001234
PC10

CUPL
Device
Partr.o
Name
Revision
Date
Designer
Company
Assembly
L.::.cat i c'r.

01
02/14/B5

Kah 1/Osartrt
Assisted Technology
PC Pt'oto Board
U2

====================================================================
Symb.;:.l Tab 1 e
====================================================================

Pol

Ext

Name

a2

a3
a4
a5
ab
a7
aB
a9
aen
.enable
io - decc.de
ioadr
ior
ioreq
iow
rar.ge
read
enable
.ioc...decode
ior
ic.w
read
LEGEND

D
U

.N

Pir.

Type

1
2
3
4
5
b
7
B

V
V
V
V
V
V
V
V
V
V
V
F
V

9

13
14
0
17
0
1B
0
12
13
14
17
1B
12

oe
c·e
Cte

oe
c·e

default var
undefir.ed
node

F
V

M

Max

2

7
7

1

I

2

V
I
V

1
2

D
D
D

1
1

D
D

1
1

7
1
1
1
1

-I : intermediate var
field
X : extended var
var
extended r.c.de

Flgur&2.

11-34

Used

MonbiithiCW Memories

CUPLTM Universal Compiler ·for Programmable Logic

COPL-G'l'S

DRAW LOGIC SCBEMATICS FOR PAL DESIGNS!
In recent years, programs like CUP!. and ABEL have become
available to provide high .leve1 language support for pAL designs.
These languages allow the designer to represent a PAL function in
terms Of high-level equation.s,trutl} table$ .or state machines.
All of these logic description formats are non-graphical in
nature and require a good working knowledge of th~. computer they
run on.
Many l}ardware de$igners, how~ver, a.re most comfortabl.e wi ththe
traditional logic sch~JlIatic and have historicallY had little
reason touse a computet in the design process. Use of .a highlevel PAL design language presents most of us with a variety of
simul taneous unknowns:
1.

2.

The computer and its operating system.
Th~ful1screeneditor

necessary t9 create the logic

description file.
3.

The logic'compiier or assembler

4.

J300lean algebratl}eory.

5 •.
Where ,thiS C;ombinat~()n plaq~s an. unnecessary moQse and a series of pop-upI'\lenus which ease the user's
tas.k.;An.area is provided at the top of the CUP!.,...GTSscre~1) .for.
pr6I11ptingth,~ us.erregardingtl}en~l{toperati.onin a.C;OIJlmanq
sequence. Highlighting ·of .variouselements on the SCreen is
coordinated 'with tl.'l~se,.prompts to enhance their effectiveness.
For,tl}emost;part,tlleuser n~edonly utpize the conventional
keyboardford.~finingsYIJlbolicnaIlles for wires, pins,.objects,
and files.
.
An on-screen HELP faCility is providecl to aidthe user\..d.thCuPLGTS.commands •.. In addition to the basic. set of object types which
can be easily picked. from a pop-upmenu,theabil i ty to call.up
macro-objects is also provided. Th.ese macro-objects have been
previously drawn uSing CtJPL-GTS and stored away on the disk. unde.r
their own' symbolic name.

CUPLl~ Universal COl'l'lpiler>for Programmable Logic

After a logic schematic has been ~ntered, the user may quickly
check to see if.thedesign>fits in a specific PAL. This is done
by selecting the "Translate to PLD" command from the main menu
which automatically invokes the GTS translation programs. These
programs run in an on-screen window which overlays the graphical
information) providing feedback in the form of error messages
dUpl'ay,ed in . this window.
Following the automatic execution. of
these programs, the cursor is r,eturnedto the user who can then
cdntinueto work in the graphics environment without ever having
fully left. In this way many errors can be quickly determined
and remedied without ever having to let go of the mouse.
When the user wishes a hard copy version of a design, the print
command fr.om the main menu may be selected. This causes the GTS
print program to execute in an em-screen window according to the
printer configuration file (PRINTCAP) which is stored on the
disk. The PRINTCAP file allows the user to bonfigure the GTS
print function for any dot.matrix printer they might hav.e.
Often a logic description not fit ina particular PAL due to a
logic capacity (product-term) limitation. Wh~n this occurs, the
universal capability of CUPL-GTS will easily allow the user to
try placing this same lOgic in a different PAL of similar
architecture.
Since CUPL-GTS incorporates CUPL the high lev.el language in its
internal ope.ration, i t alsobenefi ts from CUPL's powerful "Quine
Procedure" logic minimizer •. This is especially advantageous for
CUPL-GTS as logic descriptions showing many lev.els of gates can
be ·verydecepti ve in their ability to consume the logic
capacity of a PAL.
The presence of the logid minimizerGan
el iminate unnecessary. and redundant logical functions, and
maximizes the probabil ity that a design Wi 11 fit in a target PAL.
Also included with CUPL-GTS lathe CUPLsiinulator, CSIM, which
allows the user to simulate a logic design pt'lot to physically
creating a programmedPAL. Not only can thissavedevlces,but
it can help significant.ly in debugging a system level 'problem.
CUP:L--GTSis desingedfdrgtowthandeJ{pandabi,l ity.As . new
logic devic~sare introduced users willbekept
current with updated device librariesandproductenhancements~

programmabl~

Most of us first use PAL devices to replaceTTL'iil order to
shrink a design and/o~add functionality.. The following example·
shows how thesiniple I/O deCOder design previously discussed
would appear on the CUPL-GTS screen prior to translation toa
PAL16!,S, PAL16P8 or PLE12P4.

11-36

Mono'''hlcW""emo('',es'

CUPLTM Universal Compiler for Programmable Logic

I

Help

Select Command From Main Menu

Change Scale
Set Center
Redraw Screen

LS02
READ 12

AddObfect
Add Wire
Add Pin

IOREQ

Change Object

Name/Rename
Mcwe
Delete
Query
Find
Translate To PLD

A8

Load From Disk

8

A9

Save On Disk
Quit
More ..•

A CUPL-GTS Design Screen

Monolithic

m

Memories

Notes

11-38

Monolithic

W Memories

Definition of Terms and Waveforms

Clock Frequency

Output Enable and Disable Time

Maximum clock frequency, f max
The highest rate at which the clock input of a bistable circuit
can be driven through its required sequence while maintaining
stable transitions of logic level at the output with input
conditions established that should cause· changes of output
logic level in accordance with the specification.

Output enable time (of a three-etate output) to high level,
tPZH (or low level, tPZJ
The propagation delay time between the specified reference,
points on the input and output voltage waveforms with the
three-state output changing from a high-impedance (off) state
to the defined high (or low) level.
Output enable time (of a three-state output) to high or low
level, tpzx
The propagation delay time between the specified reference
points on the input and output voltage waveforms with the
three-state output changing from a high-impedance (off) state
to either of the defined active levels (high or low).
Output disable time (of a three-etate output) from high
level, tpHZ (or low level, t pLZ)
The propagation delay time between the speCified reference
points on the input and output voltage waveforms with the
three-state output changing from the defined high (or low)
I$vel to a high-impedance (off) state.
Output disable time (of a three-state, output) from high or
low level, tpxz
The propagation delay time between the specified reference
points on the input and output voltage waveforms with the
three-state output changing from either of the defined active
levels (high or low) to a high-impedance (off) state.
tEA Is the Ol!tput enable acee.. time of memory devices.
tER Is the output disable (enable recovery) time of memory devices.

Current
High-level Input current, IIH
The current into" an input when a high-level voltage is applied
to that Input"
" Hlgh-Ie;,~ out~ufcu,rrellt, IOH
The currentinto~ an output with input conditions applied that
according, to .the product specification wiH e.stabli!3h a high
.
level at the' outpUt.
High-level output current, leEx
The high-Ieveneakage current of an openc;:olleqtoroutput.
LOw-levei,nputcurrertt, IlL
"
The current into" an input when a low-level voltage is applied
to thatilJPuK
l.ow~levet-outlllitcurrent, IOL
The current into" an output with input conditions applied that
accOrding to the product specification will establish a 10\(V level
.
at the output. '
Off-etate (t1l9l:!"lmP~anc..tat.)o'utput currentlof a
three-state o~tput), i~z
The current into· an ,output having three-state capability with
inputconditio~ apPliedt~taccording,.tothe product specification will 'estabiishlhe h19h-impedance state at the output.
Short-cIrcuit output current, los
The current into~ an outpLit when that output is short-circuited
to ground (or ot!)er specified potential) with input conditions
applied tacestabl!sh the output logic level farthest' from ground
potential (or other specified potential).
'
Supply current, Icc
The currentinto· the, Vcc supply terminal of an intagrated
circuit.'
.,
,
·Current out ofa .terminal is givEln 8,S a negative value.

Hold Time
Hold tlmeth
The interval during which a signal is retained at a specifiEld
input tenninal after an active transition occurs at another
specifieqinput tElrminal.
'
NOTES: 1. The hold ,time is the actual time between two
events and. may be insufficient to accomplish the
intended result. A minimum value Is specified that
is the, shortest interval for which corre(lt operation
of the logic element is guaranteEld.
2. The hold time may have a negativ& value in which
case the minimum limit defines the longest interval
(between the release of data and the active transition) for which correct operation .of the logicelement is guaranteed.

12-2

Monolithic

Propagation Time
Propagation delay time, tpD
The time between the specified reference points on the input
and output voltage waveforms with thEl output changing from
one defined level (high or low) to the other defined level.
Propagation delay tlme.,low-to-hlgh-ievel output, IpLH
The time between the specified reference points on the input
and output voltage waveforms with the output changing from
the defined low level to the defined high level.
Propagation delay time, 'hlgh"to-Iow-Ievel output, tpHL
The time between the specified reference points' on the input
and output voltage waveforms with the output changing from
the defined high level to the defined low level.
tM Is the addre.. (to output) acee.. time of memory
devices.

Pulse Width
Pulse width, t..
The time interval between· spepified reference pOints on the
leading and.. trailing ed~s of tfie pulse waveform.

W';""or/ea

•

Definition of Terms and Waveforms
Setup Time

t...

Setup time,
The time interval between the application of a signal that is
maintained at one specified input terminal and a consecutive
active transition at another specified input terminal.
NOTES: 1. The setup time is the actual time between two
events and may be insufficient to accomplish the
setup. A minimum value is specified that is the
shortest interval for which correct operation of the
device is guaranteed.
2.The setup time may have a negative value in which
case the minimum limit defines the longest interval
(between the active transition and the application
of the other signal) for which correct operation of
the device is guaranteed.

Voltage
High-level Input voltage, VIH
An input voltage within the more positive (less negative) of the
two ranges of values assumable by a binary variable.
NOTE: A minimum is specified that is the least positive value
of high-level voltage for which operation of the logic
element within specification limits is guaranteed.
High-level output voltage, VOH
The voltage at an output terminal with input conditions applied
that will establish a high level at the output. The actual input
conditions needed are determined by the individual product
specification.
Input clamp voltage, VIC
An input voltage in a region of relatively low differential
resistance that serves to limit the input voltage swing.
loW-level Input voltage, VIL
An input voltage level within the less positive (more negative)
of the two ranges of values assumable bya binary variable.

Truth Table Explanations
H
L

= high level (steady-state)
= low level (steady-state)
t
= transition from low-to-high level
!
= transition from high·to·low level
x
= don't care (any input, including tranSitions)
= off (high-impedance) state of a three-state output
Z
a ..h - the level of steady-state inputs at inputs A through H
respectively
= level of 0 before the indicated steady-state input
conditions were established
= complement of 0 0 or level of Q before the indicated
steady-state input conditions were established
= level of 0 before the most recent active transition
indicated by ! or t
If, in the input columns, a row contains only the symbols H, L,
and/or X, this means the indicated output is valid whenever
the input configuration is achieved and regardless of the
sequence in whiCh it is achieved. The output persiSts as long
as the input configuration is maintllined.
If, in the input columns, a row contains H, L, and/or X together
with t and/or !, this means the output is valid whenever
the input configuration is achieved and the indicated transition
has occurred (the transition(s) must. occur following the
achievement of the steady·state levels). If the output is shown
as a level (H, L, 0 0 , or 0 0 ), it persists as long as the steadystate input levels and the levels that terminate indicated
transitions are maintained. Unless otherwise .indicated, input
transitions in the opposite direction to those shown have no
effect at the output.

NOTE: A maximum is specified that is the most pOSitive value
of lOW-level input voltage for which operation of the
logic element within specification limits. is guaranteed.
Low-lev,1 output voltage, VOL
The voltage at an output terminal with input conditions applied
that will establish a low level at the output. The actual input
conditions· needed are determined by the individual product
specification.
Negative-going threshold voltage VT_
The voltage level. at an input that causes a transition as the
input voltage falls from a level above the. positive-going
threshold voltllge, VT +.
Positive-going threshold VOltage, Y T +
The voltage level at an input that causes a transition as the
input voltage rises from a level below lhenegative-going
threshold voltage, VT_.

12-3

Package Drawings
Package Drawings
1&1 Ceramic DIP

(5116"x3/4")
MII-M-38510,
Appendix C, 0-2

-11--.en8
±.004
I -:m±.1Di
UNLESS OnEAWlSE SPECIFIED:
ALL DIMENSIONS MIN.-MAX. IN INCHES

ALL DIMENSIONS MIN.-MAX. IN MILUMETERS
ALL TOLERANCES AAE ± .007 INCHES

.311
7.8l1li

~MAX
1.524

.788 ± .G2O

.273 + .D32

.:!1!MIN

.381

3.883 ± .50/1

.011 ± .om
.279 ±.D76

.040±.010

~

t ..
I-

~. .

.~±~

Notes:
1. Specified body dimensions allow for differences b_een 551, M51 and L51 packages.
• ~. Lead material tolerances are for tin plate finish only. Solder dip finish adds 2 - 10 mils thickness to all lead tip dimensions.

13-2

Monolithic

W Memories

~ AE~.

(2)

Package Drawings

Package Drawings
18J Ceramic DIP
(5/16"x3/4")
MII-M-38510,
Appendix C, 0-6

•

20J CeramIC DIP
(5I16"x1")
MH-M-38510,
Appendix C, D-8

~II_ .018 ± .004

.457±.102

UNLESS OTHERWISE SPECIFIED:
ALL DIMENSIONS MIN.-MAX. IN INCHES
ALI. DIMENSIONS M'N.-MAX. IN M'LUMETERS
ALL TOLERANCES ARE ± .007 INCHES

..,ru..j

~.~

.~±~
7.899

---"'- =t::~
1.016

""-'-""-l~.· J~\.t'·.z.;EF.:~
.219 ± .075

~
9.525 ±.635
Notes:
1. Specified body dimensions allow for differences between 551, MSI and LSI packages.
2.,Lead material tol'erances are for tin plate finish only. Solder dip finish adds 2 - 10 mils-,thickness to aU lead tip dimensions.

MonoIlthlcLJIJJ Memo,./es

13-3

Package Drawings
Package Drawings
24JS Ceramic SKINNYDIP
(5116"x1-1/4")
MU-M-38510,
Appendix C, 0-9

24J Ceramic DIP
MII-M-38510,
Appendix C, 0-3

UNLESS OTHERWISE SPECIFIED:
ALL DIMENSIONS MIN.-MAX. IN INCHES
ALL DIMENSIONS MIN.-MAX. IN MILLIMETERS
ALL TOLERANCES ARE ± .007 INCHES

,~.- I'
..:!!!!.MAX

4.064

~~:'!

E
3
~';·1
R,1\''
611

"1.""-

5. 715 MAX

II

-r--. 0 2 5 1
TT

.330 ±
8.3B2±.1135

~-: MAX

.158±.016

2.640

1.016

3.663 _.508

'

.279 ± .076

I --.685 + .030
!-"- 17.339±.71S2

Notes:
t. Specified body dimensions allow for differences between MSI and LSI packages.
2. Lead material tolerances are for tin plate finish only. Solder dip finish adds 2 - 10 mils thickness to all lead tip dimensions.

13-4

Monolithic WMemorles

Package Drawings
Package Drawings
035+.003

~TYP(20)1 ~ ~~~~~'1 r

20L LeadIesa Chip Carrier

MII-M-38510,
Appendix C, C-2

.635 ± .0111

.015

~~ r-'-'"'""',.......,.~ ,~.-:£':ooi
t
v

~MIN

v-V'J.

I

.
~

""T"_....;;;.38,,;;,,1;...,.._

I

[

(

REF

r-u........ r-~--......-'T"'l

t

_

:l~/'::'

t

~

=1
.330

X45'
.m
.508

IDENTIFY

2

[

~

6.350

I

REF

C

~

I

~ ~ I--j~

.350:.008 s o _

5.0B0
BSC

!

x 45'(3)

REF

~
. ~,.....t1
~J L.",..
.075

1

.100

.050 ±.005

um,m

.127i.051

8.B90 _.203

BOTTOM VIEW

UNLESS OTHERWISE SPECIFIED:
ALL DIMENSIONS MIN.-MAX. IN INCHES
ALL DIMENSIONS MIN.-MAX. IN M/WMEnRS

ALL TOLERANCES ARE ± .000INCH1S

28L Leadleas Chip Carrier

MII-M-38510,
Appendix C, c-4

~f~ll~F~X~~~O~~~~~~~~~ f:::
.014 %.008

-.f :3ii±.2ii3
8.38
MAX

1
_

.450 + .008
11.430 ± .203

-I

so_

--'~6

x45'(3)

REF

TYP
TOP VIEW

BOTTOM VIEW

Notes:
1. Solder fillets on lid edges not shown.

Monolithic WMemor/es

13-5

Package Drawln,.
Package Drawings
'lJNI Cerpack

MIl M 38510,
AppendIx C, F-9

.G12+.CI03
_ -.004
+.tnII

•

-;1011

PIN.,

.045

[U43

IDENTIFY

i

I

I

1

L

30

+.aozr

1

MAX

:f 1

.G17
.513 ~ 018

.017
A32 +.061

13.0311 ~ 457

A32

L
10

.j

11

J

l:!!!!

.127

.271:t.ooa 1
~.:: 1~
1 =~--=.J;;;;;;;;;;;;;;;;;;;~====~-tf
___ I
I
_
[~
~
~_---L

.oos +_ .002
.0CI1
.127

MIN

,.. B.883 ± .229

.078 + ,018

I

1.1130 ±.4011

.300 MAX
7.820

.1138 ± .178

(GLASS FLOW)

24WCerpeck

PlNU
IDENTIFY

+.CI03
.012 -.004

a.M-38510.
Appetdx C, F-6

[.-+:f:

t

PIG

1

-r

24

.1-.-

i.OO2·r,·i

.017
.018
.432
15.670 ~ 457

.613 ~

±.OS1

','

~
12

13

=1l.
-l.

.127 ..

.oos
+ .001
. -.002

.127.~= b

r---.'0.G6:t.+.o2oaW4.

~.. '

.412

',.

.o?!£.G15

.:.::::::.:.:.jl
. ~.~~~~~~I=====:Jrt:M5:t.v1

. . . LlI33± .007

&31/±.178

,

.

. .,

I-- 1~

MAX

---I.'

(GI..ASS FLOW)

~s8oTHERWiSe-...m:
.ALL DIMENSIONS ..N....wc. !NINettE.
AU DIMEN$lONSIIIN.·MAX. IN IIIWMnDS
ALL TOLERANCI!~A~ ± .000INCHE~
~

13-6

Package Drawings

Package Drawings
16N Molded DIP
(1/4"x3/4")

PIN NO.1
IDENTIFIER
PIN NO.1
IDENTIFIER

..Ir-~

7.772±.2S4

__.258
__
±_.0_'_2
,..\ -... 5.553 ±._

~_"""'.1+,

r

t

\

1'00TYP

-IU-.~:..

5' -12'

.011 ±.002

.279±.051

(2)

.

,

-

~

.

9.144 ±.635

--~
.457±.102

""",.,.

18N MoICIecI DIP
(1/4"x7/8")

~::::::~I

00::..pt~

PIN No. 1
IDENTIFIER

(EJECTOR
OPTIONAL

PIN NO.1
.
IDENTIFIER'

'l!!!!!!Q!'!!
.130

3.302

~--~r-~
7.772 ±.2B4

~---o.K--

6.:'~.:s

10' TYP

..

5' - 12'

~-+IU
~EF,(2)
.279:t.051
-.

.380±.025
9.144±.635

UNLESS OTHERWISE SPECIF1ED:
AI,!; DI.MENSIONS MIN.-MAlt IN INCHES
ALL DIMENSIONS IIIN.-MAX. IN MILLIMETERS
ALL TOLERANCES ARE ± .007 INCHES
Notes:
1. Lead material tolerances are for tin plate finish only. Solder dip finish adds 2 -,to.dlils-thickness to alnead tip dimensions.
2. Both Version 1 and Version 2 configurations are manufactur
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