1986_Microcommunications_Handbook 1986 Microcommunications Handbook

User Manual: 1986_Microcommunications_Handbook

Open the PDF directly: View PDF .
Page Count: 1395

Download
Open PDF In Browser	View PDF

LITERATURE
To order Intel Literature write or call:
Intel Literature Sales:
(800) 548-4725
Other Inquiries:
(800).538-1876

Intel Literature Sales
P.O. Box 58130
Santa Clara, CA 95052-8130

Use the order blank on the facing page or call our Toll Free Number listed above to order literature.
Remember to add your local sales tax and a 10% handling charge for U.S. customers, 20% for Canadian
customers.

1986 HANDBOOKS
Product Line handbooks contain data sheets, application notes, article reprints and other design
information.

ORDER NUMBER

*PRICE IN
U.S. DOLLARS

COMPLETE SET OF 9 HANDBOOKS
Get a 30% discount off the retail price of $171.00

231003

$120.00

MEMORY COMPONENTS HANDBOOK

210830

$18.00

MICROCOMMUNICATIONS HANDBOOK

231658

$18.00

MICROCONTROLLER HANDBOOK

210918

$18.00

MICROSYSTEM COMPONENTS HANDBOOK
Microprocessor and peripherals (2 Volume Set)

230843

$25.00

DEVELOPMENT SYSTEMS HANDBOOK

210940

$18.00

OEM SYSTEMS HANDBOOK

210941

$18.00

SOFTWARE HANDBOOK

230786

$18.00

MILITARY HANDBOOK

210461

$18.00

QUALITY/RELIABILITY HANDBOOK

210997

$20.00

PRODUCT GUIDE
Overview of Intel's complete product lines

210846

No charge

LITERATURE GUIDE
Listing of Intel Literature

210620

No charge

INTEL PACKAGING SPECIFICATIONS
Listing of Packaging types, number of leads,
and dimensions

231369

No charge

NAME

*These prices are for the U. S. and Canada only. In Europe and other international locations, please
contact your local Intel Sales Office or Distributor for literature prices.

inter
u.s. LITERATURE ORDER FORM
NAME: _______________________________________________________
COMPANY: ___________________________________________________
ADDRESS: _________________________________________________
CITY: ________________________________ STATE: _ _ _ _ ZiP: _____
COUNTRY:
PHONE NO.: (_ _=----_____________________
ORDER NO

TITLE

QTY.

PRICE

TOTAL

__ x __
__ x __
__ x __
__ x __
__ x __
__ x __

_ _ x _ _ = ____

Add appropriate postage
and handling to subtotal
10% U.S.
20% Canada

~------------~~

Subtotal _________
Your Local Sales Tax _________
--------I~~

Allow 2-4 weeks for delivery

Postage & Handling _________
Total _________

Pay by Visa, MasterCard, Check or Money Order, payable to Intel Books. Purchase Orders
have a $50.00 minimum
o Visa 0 MasterCard Expiration Date __________
Account No. ______________________________~------------------Signature: ______________________________________________________
Mall To:

Intel Literature Sales
P.O. Box 58130
Santa Clara, CA
95052-8130

Customers outside the U.S. and Canada should contact the local Intel Sales Office or Distributor listed
in the back of most Intel literature.

Call Toll Free: (800) 548-4725 for phone orders
Prices good until 12131 186.
SourceHB

Mall To:

Intel Literature Sales

P.O. Box 58130
Santa Clara. CA 95052-8130

MICROCOMMUNICATIONS
HANDBOOK

1986

Microcommunications
Intel is generally credited with inventing the microprocessor chip, which
has found its way into many facets of our daily lives from the family
automobile to the personal computer. Micro-chips have traditionally
been associated with computer technology, but a revolution is
underway in the world of communications that will transform this
traditional analog world into a digital one. Integrated Services Digital
Network (ISDN) is the term used to describe the new class of service
soon to be provided by the telephone operating companies, but the
merging of Computers and Communications will certainly find its way
into many other applications. To emphasize the role that this emerging
technology will have on our products, we have coined the term
Microcommunications ... Micro-Chips in Communications.

About Our Cover:
The design on our front cover is an abstract portrayal of the function of Intel
MicroCommunications products, i.e., boards, components and software that facilitate
communications between one computer system to another computer system.

Intel Corporation makes no warranty for the use .of its products and assumes no responsibility for any errors which
may appear in this document nor does it make a commitment to update the information contained herein.
Intel retains all rights to make changes to these specifications at any time. without notice.
Contact your local sales office to obtain the latest specifications before placing your order.
The following are trademarks of Intel Corporation and may only be used to identify. Intel Products:

t.

ICE.
Above. BITBUS. COMMputer. CREDIT. Data Pipeline. GENIUS. i.
iCEL. iCS. iDBP, iDIS. I'ICE. iLBX. im• iMDDX.. iMMX. Insite. Intel. intel.
intelBOS. Intelevision. inteligent Identifier. inteligent Programming. Intelrec.
Intellink. iOSP, iPDS. iPSC. iRMX.iSBC. iSBX. iSDM. iSXM. KEPROM. Library
Manager. MAP-NET. MCS. Megachassis. MICROMAINFRAME. MULTIBUS.
MULTICHANNEL, MULTIMODULE; ONCE. OpenNET, PC-BUBBLE. Plug-ABubble. PROMPT, Promware. QUEST. QueX. Quick-Pulse Programming.
Ripplemode. RMX/BO. RUPI. Seamless. SLD. UPI. and VLSiCEL. and the
combination of ICE. iCS. iRMX. iSBC. iSBX. MCS.' or UPI and a numerical
suffix. 4-SITE.
MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered trademark of
Mohawk Data Sciences Corporation.
.
'MULTI BUS is a patented Intel bus.
Additional copies of this manual or other Intel literature may be obtained from:
Intel, Corporation
Literature Distribution
Mail Stop SC6-59
3065 Bowers Avenue
Santa Clara. CA 95051

@INTEL CORPORATION 1985

10/25/85

Table of Contents
OVERVIEW .............................................................. xvii
CHAPTER 1
INTRODUCTION
1.0
1.0.1
1.1
1.1.1
1.1.2
1.1.3
1.2
1.2.1
1.2.2
1.2.3
1.2.4

Overview ........................................................... 1-1
LAN Requirements .................................................. 1-1
Networking Solutions Via Standards .................................. 1-2
The ISO Model ...................................................... 1-2
The IEEE 802 Committee ............................................. 1-4
Existing and Emerging Medium Access Standards ..................... 1-5
The Intel LAN Solution ............................................... 1-8
A Commitment to Standards ......................................... 1-8
Intel's EthernetlCheapernet Chip Set ................................. 1-8
The 82588 Single~Chip LAN Controller ................................ 1-9
The iNA 960 Transport Software ...................................... 1-10

CHAPTER 2
82586 LAN COPROCESSOR
2.0
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.3
2.3.1
2.3.2
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.5
2.5.1
2.5.2
2.5.3
2.6
2.6. i
2.6.2
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.7.5
2.7.6
2.7.7
2.8
2.8.1
2.8.2
2.8.3
2.8.4
2.8.5
2.8.6

Overview ........................................................... 2-1
Overview of the 82586 LAN Coprocessor ....................... , ...... 2-1
82586 Transmit Function ............................................. 2-3
Framing ............................................................. 2-3
Link Management .................................................... 2-4
Priority Mechanism .................................................. 2-4
Details of the Link Management Algorithms ........................... 2-5
82586 Receive Functions ................ : ............................ 2-6
Frame Reception .................................................... 2-6
Addressing ......................................................... 2-6
82586 Network Management and Diagnostic Functions ................. 2-7
Transmission/Reception Error Reporting ............................. 2-7
Network Planning and Maintenance ................................... 2-7
Station Diagnostics .................................................. 2-8
82586 Self Testing ................................................... 2-8
82586/Host CPU Interaction .......................................... 2-9
Logical Interface ..................................................... 2-9
Hardware Bus Interface .............................................. 2-11
Memory Addressing ................................................. 2-11
Initializing the 82586 ................................................. 2-13
Initialization Root Format ............................................ 2-13
Initialization Process ................................................. 2-13
Controlling the 82586 ................................................ 2-14
System Control Block (SCB) Format .................................. 2-14
Starting and Completing Control Commands .......................... 2~16
Command Unit (CU) Control .......................................... 2-16
Receive Unit (RU) Control ............................................ 2-20
Reset ................................................................ 2-22
Error Statistics Registers ............................................ 2-23
SCB Status Update .................................................. 2-23
Action Commands ........................... ; ....................... 2-24
General Action Command ............................................ 2-25
NOP ................................................................ 2-26
lA-Setup ............................................................ 2-27
Configure ......................................................... , .2-28
MC-Setup ............................................................ 2-30
Transmit ............................................................ 2-31
iii

Table of Contents

(continued)

TDR (Time Domain Reflectometer) .................................... 2-35
2.8.7
Dump ............................................................. ~ .2-36
2.8.8
. Diagnose ........................................................... 2-43
2.8.9
Frame Reception .. '.' ........ '.................................. '...... 2-44
2.9
Receive Frame Area. (RFA) ............................................ 2-44
2.9.1
Frame Descriptor (FD) Format ........................................ 2-44
2.9.2
Receive Buff.er Descriptor Format .; .............. '.................... 2-46
2.9.3
. Initial Structure of the Receive Frame Area ............................ 2-46
2.9.4
Detaiied Operation of Receiving a Frame .............................. 2-46
2.9.5
Bus Interface ........................................................ 2-48
2.10
Memory Addressing and Organization ................. , .............. 2-49
2.10.1
Bus Operation ....................................................... 2-49
2.10.2
Bus Acquisition ...................................................... 2-50
2.10.3
FIFO-Threshold Mechanism .......................................... 2-52
2.10.4
Bus Cycle Interleaving ......................... ; ..................... 2-53 .
2.10.5
CPU/82586 (CA/INn Handshake ...........................•......... 2-54
2.10.6
Network Interface Hardware ......................................... 2-55
2.11'
2.11.1. Encoding/Decoding ... ~ ........................... ',' ................ 2-55
Carrier Sense ....................................................... 2-55
2.11.2
Collision Detection ................................................... 2-56
2.11.3
Serial Link Acquisition ............................................... 2-56
2.11.4
loopback ........................................................... 2-57
2.11.5
2.11.6
Interframe Spacing Timer ............................................ 2-57
2.12
Configuration Parameters ............................................ 2-57
Framing Parameters .................................................. 2-57
2.12.1
2.12.2
link Management Parameters ........................................ 2-58.
2.12.3
Serial Interface Parameters ...................... ; ................... 2-59
Host Interface Parameters ........................................... 2·60
2.12.4
2.12.5
Network Management Parameters .................................... 2·61
2.13'
Internal Architecture .............•................................... 2·61
The Hostlnterface Module ........................................... 2-62
12•13.1
2.13.2
The Channel Interface Module ........................................ 2·63
2.13.3 .The FIFO Module ...................... ~ ............................. 2·63

CHAPTER 3
PROGRAMMING THE 82586
3.0
Introduction ......................... '.' .............. , ............... 3·1
3.1
Fitting the 82586 into a System ....................................... 3·1
3.2
The 82586 Handler ................................................... 3·2
3.2;1
The 82586 Handler as a Standard Device Driver ........................ 3·2
3.2.2
The 82586 Handler as a Special Driver ................................. 3-4'
3.3
Initialization ........ : ................................................ 3·5
3.4
Simple Command Processing .....................•.................. 3·6
3.4.1
Adding CBs to the CBl ............................................... 3·6
3.4.2
Basic Interrupt Service Routine .......... '.' .....................•..... 3·6
3.5
Advanced Command Processing ..................................... 3·7
3.5.1
Adding Command"Blocks to Static and Dynamic Lists .................. 3·8
3.5.2
Static 'List hiterrupts ............................................... '.. 3-8
3.5.3
Dynamic List Interrupts ............................................... 3·8
3.5.4
CU Command Simplification .......................................... 3-11
3.6
Receive Frame Processing ........................................... 3·12
3.6.1
Supplying FDs to the RDl ............................................ 3-12
3.6.2
Supplying FDs to the FBl ............................................ 3·13
iv

Table of Contents
3.6.3
3.6.4
3.6.5
3.7

(continued)

Receive Interrupt Processing ......................................... 3-14
Rules for Starting the RU ............................................. 3-14
Considerations in Using Receive Buffers .............................. 3-15
Combining Receive and Command Processing ........................ 3-17

CHAPTER 4
82586 DATA LINK DRIVER
4.0
Introduction ......................................................... 4-2
4.1
Fitting the Software into the OSI Model ............,................... 4-2
4.2
Large Model. ........................................................ 4-3
The 82586 Handler ................................................... 4-3
4.3
4.3.1
The Buffer Model .................................................... 4-3
4.3.2
The Handler Interface ................................................ 4-4
4.3.3
Initialization ......................................................... 4-6
4.3.3.1 Building the CB and RFA Pools ................................... , ... 4-6
4.3.3.2 82586 Initialization ................................................... 4-6
4.3.3.3 Self Test Diagnostics ................................................ 4-7
4.3.4
Command Processing ............................................... 4-8
4.3.4.1 Accessing Command Blocks ......................................... 4-8
4.3.4.2 Issuing CU Commands ................................. , ............. 4-8
4.3.4.3 Interrupt Service Routine ............................................ 4-9
4.3.4.4 Sending Frames ..................................................... 4-9
4.3.4.5 Accessing Transmit Buffers .......................................... 4-10
4.3.4.6 Multicast Addresses ................................................. 4-10
4.3.4.7 Resetting the 82586 ................................................. 4-11
Receive Frame Processing ........................................... 4-12
4.3.5
4.3.5.1 Receive Interrupt Processing ................................ : ........ 4-12
4.3.5.2 Returning FD and RBD ............................................... 4-12
4.3.5.3 Restarting the Receive Unit .......................................... 4-12
4.4
Logical Link Control .................................................. 4-13
4.4.1
Adding and Deleting LSAPs .......................................... 4-15
4.5
Application Layer .................................................... 4-15
Application Layer Human Interface ................................... 4-15
4.5.1
4.5.2
A Sample Session ................................................... 4-16
4.5.3
Terminal Mode ...................................................... 4-18
4.5.3.1 Sending Frames ..................................................... 4-19
4.5.3.2 Receiving Frames ................................................... 4-19
4.5.4
Monitor Mode ....................................................... 4-19
4.5.5
High Speed Transmit Mode ........................................... 4-20
Appendix A: Compiling, Linking, Locating, and Running the Software
on the iSBC 186/51 Board ........................................... ; ..... 4-21
Appendix B: Listing ofthe Software ........................................... 4-23

CHAPTER 5
APPLICATION EXAMPLES
5.0
Overview ............................................................ 5-1
5.1
Minimum 82586 System Bus Speed ................................... 5~1
5.2
Setting the 82586 FIFO-Threshold .................................... 5-2
5.3
The Minimum Buffer Size ............................................. 5-3
5.4
System Configurations ............................................... 5-4
5.4.1
80186 Elementary Maximum Mode System ............................ 5-4

v

Table of Contents
5.4.2
5.4.3
5.4.4
5.5
5.6
5.6.1
.5.6.2
5.6.3
5.6.4
5.7
5.7.1
5.7.2
5.7.3

(continued)

Stand Alone Multibus System ......................................... 5-5
Dual Port RAM Systems .... ; ................................. ; ....... 5-5.
Multiple Bus Master Systems ......................................... 5-9
Calculating Unique Multicast Addresses ............................... 5-9
A Low Cost Dual Port Memory Design ............. , ................... 5-13
Hardware Design .................................................... 5-13
Application Software ................................................ 5-21
Special Considerations .............................................. 5-58
Conclusion ....................... ~ ...... ; ............................ 5-58
iNA 960 Transport Engine ............................................ 5-58
IntrOduction ......................................................... 5-58
Transport Engine Hardware .......................................... 5-60
Transport Engine Software ........................................... 5-60

82586 TRAFFIC SIMULATOR AND MONITOR STATION PROGRAM
5.8
Introduction .......................................................... 5-63
5.9
Hardware Vehicle for the TSMS Program ~ ............................. 5-63
5.10
LANHIB Hardware Description ........................................ 5-63
5.10.1
82586 (Min Mode) Interface to the 80186 , ............................. 5-63
5.10.2
82586 Address Latch Interface ....................................... 5-64
5.10.3
80186 Address Latch Interface ....................................... 5-64
5.10.4
82586 Memory Interface .........................' ........ , ........... 5-66
5.10.5
80186 Memory Interface ............................................. 5-66
5.10.6
Memory Map ..................... .' .................... ; ............. 5-67
5.10.7
80186110 Interface ............ ; ..................................... 5-67
5.10.7.1 82586 Channel Attention Generation .................................. 5-67
5.10.7.2 82586 Hardware Reset Port .......................................... 5-67
5.10.7.3 82530 Interface ............................ : ................. ,' ....... 5-67
5.10.7.4 82501 Loopback Configuration Port ................................... 5-67
5.10.7.5 On-Board Individual Address Port ........................... '......... 5-67
5.10.8
82586 Ready Signal Generation ....................................... 5-68
5.11
TSMS Program Control Flow ......................................... 5-69
5.11.1
Main Program ........................ , .............................. 5-69
5.11.2
Interrupt Service Routine ............................................ 5-69
5.12
Capabilities and Limits of the TSMS Program .......................... 5-75
5.13
Example Executions of the TSMS Program ............................ 5-76
5.13.1
External LoopbackExecution ........................................ 5-77
5.13.2
Frame Reception in Promiscuous Mode ............................... 5-79
5.13.3
35.7% Network Traffic Load Generation ............................... 5-82
5.14
Programming PROMs to Run the TSMS Program ....................... 5-85
Appendix A: LANHIB Schematic ............................................... 5-87
Appendix B: TSMS Program Listing ............................................ 5-96
CHAPTER 6
82588 REFERENCE MANUAL
6.1
Introduction ........................................ , ................ 6-2
6.2
82588 Internal Architecture ........................................... 6-2
6.~.1
Parallel Section ...................................................... 6-2

vi

Table of Contents

(continued)

6.2.2
Serial Section ....................................................... 6-3
6.3
Working with the 82588 .............................................. 6-4
6.3.1
82588/Host CPU Interface ............................................ 6-4
6.3.2
Transmitting a Frame ................................................ 6-5
6.3.3
Receiving a Frame ................................................... 6-6
6.4
Framing and Link Management ....................................... 6-6
6.4.1
Frame Format ....................................................... 6-6
6.4.2
Frame Boundary Delineation ......................................... 6-6
6.4.3
Addressing ......................................................... 6-7
6.4.4
Error Detection ...................................................... 6-7
6.4.5
Frame Transmission ................................................. 6-8
6.4.6
Link Management .................................................... 6-8
6.4.7
Priority Mechanism .................................................. 6-9
6.4.8
Frame Reception ............ .' ....................................... 6-9
6.4.9
Physical Link Interface ............................................... 6-11
6.5
82588 Network Management and Diagnostic Functions ................. 6-13
6.5.1
Transmission/Reception Error Reporting ............................. 6-13
6.5.2
Network Planning and Maintenance ................................... 6-13
6.5.3
Station Diagnostics .................................................. 6-14
6.5.4
82588 SelfTesting ................................................... 6-14
6.6
Initializing/Configuring the 82588 ..................................... 6-14
6.6.1
Initializing the 82588 ................................................. 6-14
6.6.2
Configuring the 82588 ............................................... 6-14
6.6.3
Configuration Parameters ............................................ 6-15
6.7
ContrOlling the 82588 ................................................ 6-18
6.7.1
The Command Register .............................................. 6-18
6.7.2
The Status Registers ................................................ 6-19
6.7.3
Performing Execution Operations .................................... 6-21
6.7.4
Reception of Frames ................................................ 6-21
6.8
Operations and Status ...................... , ........................ 6-22
6.8.1
Operations .......................................................... 6-22
6.8.2
Illegal Commands ....................................... ; ........... 6-27
6.8.3
Event Status ...................... : ................................. 6-27
6.9
System Interface .................................................... 6-33
6.9.1
Command/Status Transfers .......................................... 6-33
6.9.2
Data Transfer ....................................................... 6-34
6.9.3
Interrupt ............................................................ 6-34
6.9.4
Performance Considerations ......................................... 6-34
6.10
80188 Based System ................................................. 6-36
6.10.1
Link System ......................................................... 6-36
6.10.2
Application .......................................................... 6-36
Appendix A: 82588 Software Drivers ........................................... 6-39

CHAPTER 7
IMPLEMENTING StarLAN WITH THE INTEL 82588 CONTROLLER
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.2
7.2.1
7.2.1.1

Introduction ......................................................... 7-1
StarLAN ............................................................ 7-1
Network Topologies ................................................. 7-1
The 82588 ........................................................... 7-2
Organization ........................................................ 7-2
StarLAN ............................................................ 7-2
StarLAN Topology ................................................... 7-3
Telephone Network .... , ............................................. 7-3
vii

Table of, Contents
7.2.1.2 '
7.2.2
7.2.3
7.2.3.1
7.2.3.2
7.2.3.3
7.2.4 .
7.2.5
7.2.6
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.5.1
7.3.5.2
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10
7.4
7.4.1
7.4.2
7.4.3
7.4.3.1
7.4.4
7.4.5
7.5
7.5.1
7.5.1.1
7.5.1.2
7.5.1.;J
7.5.1.4
7.5.2
7.5.2.1 '
7.5.2.2
7.5.3
7.5.4
7.5.5
7.5.6
7.6
7.6.1
7.6.1.1
7.6.1.2
7.6.1.3
7.6.1.4
7.6.1.5
7.6.1.6
7.6.1.1
7.6.2
7.7

(continued)

StarLAN and Telephone Network ...............................•..... 7·4
StarLAN and Ethernet .........................•....•................. 7·6
Basic StarLAN Components ...................•................•..... 7·6
StarLAN Node Interface .............................................. 7·6
StarLAN HUB .............................•.................. ,'. ; ..... 7·7
StarLAN Cable ..........................•...................... '..... 7·9
Framing .. " .................................................... '...... 7·9
Signal Propagation and Collision ........ ~ ............................ 7·9
StarLAN Network Parameters ................................... , .... 7-10
82588-LAN Controller for StarLAN ..................................,.7·12
IEEE 802.3 Compatibility ............................................ : 7·12
Configurabillty of the 82588 ......................•... ., ............... 7·12
Clocks and Timers ................................................... 7-13
Manchester Encoding and Decoding .................................. 7-13
Detection of Collision Presence Signal .........•........... , .......... 7·13
Collision Detection by Code Violation .......... :..•...... : ............. 7-16
Collision Detection by Signature Comparison .......................... 7·16
Carrier Sensing ....................................................... 7-17
Squelching the Input .................................................7·17
System ,Bus Interface ......... '....................................... 7·17
Debug and Diagnostic Aids ..................' ......................... 7-20
Jitter Performance ....................................... ; ..... : ..... 7·20
Working with the 82588 .............................................. 7·21
Transmit and Retransmit Operations ..........................•....... 7·21
Configuring the 82588 ............................................... 7-22
Frame Reception ............................................'......... 7·22
Multiple Buffer Frame Reception •............................... : ..... 7·22
Memory Dump of, Registers .......................................... 7·23
Other Operations ........................................... '......... 7·23
StarLAN Node for IBM PC ............................................ 7·23
Interfacing to the IBM PC 1/0 Channel ................................. 7·25
Chip Select and bata Bus Interfacing .................................. 7-25
Clock Generation ................................................ '..... 7·26
DMA Interface .................................................'....... 7-26'
Interrupt Controller ................................................... 7·27
Serial Link Interface ................................................. 7·27
Transmit Path ....................................................... 7-27
Receive Path ..................................... '................... 7·28
Cost ...........•.............,............................ '...'........ 7,-29
80188 Interface to 82588 .......•..................................... 7-29
iSBX Interface to StarLAN ............................................ 7·29
Protection Circuits ............................................... '. '... 7·32
StarLAN HUB ........................................... '............. 7·32
The HUB Design ..........................•........................ '.. 7·33
Receiving Circuits and Carrier Sensing ....... : ........................ 7-33
Collision Detection .................................................. 7-33
Collislon'Presence Signal ............................................ 7-33
Signal Retiming .....................•... ;' ........................... 7-36
Designing the Retiming Circuit ......................... ; ............. 7-36
Driver Circuits ....................................................... 7·37
Jabber Function ..................................................... 7-37
HUB Reliability ........................................ " ............. 7-37
82588 Software Driver ............................ : ....... : .......... 7-37
viii

Table of Contents

(continued)

7.7.1
Interfacing to IBM PC ................................................ 7-38
7.7.1.1 Doing I/O on IBM PC ................................................. 7-38
Initialization and Declarations ........................................ 7-38
7.7.2
General Commands .................................................. 7-38
7.7.3
7.7.4
DMA Routines ............ ; ........................................... 7-39
Interrupt Routines ................................................... 7-39
7.7.5
Appendix A: StarLAN Signals .................................................. 7-40
Appendix B: Single DMA Channellnierface ..................................... 7-43

CHAPTER 8
LOCAL AREA NETWORKS
DATA SHEETS
82501 Ethernet Serial Interface ............................................................ 8-1
82502 Ethernet Transceiver Chip .......................................................... 8-15
82586 Local Area Network Coprocessor •.......•..•.....•....... : ......................... 8-27
82588 Single-Chip LAN Controller......................................................... 8-61
LAN ARTICLE REPRINTS
AR-345 Build a VLSI-based Workstation for the Ethernet Environment ..................•.••.• 8-87
AR-346 VLSI Solutions for Tiered Office Networks .......................................... 8-95
AR-342 Chips Support TlNo Local Area Networks ........................................... 8-105
AR-405 Low-cost Dual Port RAM Design Delivers High Performance ...•..•.•.....••..•..•... 8-111
AR-371 Monolithic Controller Builds PC Network Without Toil or Trouble ..................... 8-117
AR-385TlNo Low-speed Nets Race to Link Computers ..................•..•.•..•.•.......•. 8-126
AR-386 Power to the PCs .......................•.....•..•.....•......................... 8-130

CHAPTER 9
GLOBAL COMMUNICATIONS
DATA SHEETS
8251A Programmable Communication Interface ........................................... '.9-1
8273/8273-4 Programmable HDLC/SDLC Protocol Controller ....•..•.•.•..•...........•.... 9-18
8274 Multi-Protocol Serial Controller (MPSC) .......•...•.•.......••.•.•••••..........•.... 9-46
82530/8250-6 Serial Communications Controller (SCC) ..•.................................. 9-83
APPLICATION NOTES
AP-16 'Using the 8251 Universal Synchronous/Asynchronous Receiver/Transmitter ............. 9-111
AP-36 Using the 8273 SDLC/HDLC Protocol Controller ................................•..•. 9-142
AP-134 Asynchronous Communications with the 8274 Multiple Protocol Serial Controller ...... 9-189
AP-145 Synchronous Communications with the 8274 Multiple Protocol Serial Controller ....... 9-226
AP-222 Asynchronous SDLC Communications with 82530 ..........•.•..••.•.........•....• 9-266

CHAPTER 10
OTHER DATA COMMUNICATIONS
DATA SHEETS
8291A GPIB Talker/Listener ..........................•..•.....•••....•.•......•...•...... 10-1
8292 GPIB Controller ............•.••.•....•...•..•..................................•... 10-30
8294A Data Encryption/Decryption Unit ••..........................•...........•...••.••.. 10-45
APPLICATION NOTES
AP-66 Using the 8292 GPIB Controller ..........•..•.•..........•..•..................•... 10,-57
AP-166 Using the 8291A GPIB Talker/Listener ..•....•....•...............................•. 10-114
ARTICLE REPRINTS
AR-208 LSI Transceiver Chips Complete GPIB Interface •....... ~ .••....••.•................ 10-147
AR-113 LSI Chips Ease Standard 488 Bus Interfacing •..•.••........... : ...•................ 10-155
TUTORIAL
Data Encryption Tutorial .............................•.......•.•......••................. 10-165
ix

CHAPTER 11
OpenNETTM PRODUCT FAMILY
ISXM'· 554 MAP Communication Engine .........•..•.......•..••......................... 11-1
MapNET'· Communications Software Member of the OpenNET Product Family ........•...... 11-8
iSBC® 552 And iSMX'· 552 Ethernet Communications Engine Product ...............•.•. ,.... 11-10
iSBC® 186/51 Communicating Computer ..........................•.•..•.. , ... : ........... 11-19
IRMX'" Networking Software-IRMX'"-NET .•..•••..•.............•..... , ................. 11-32
XENIX Networking Software .................................................•............ 11-38
INA 960 li"ansport Software ................•..•....•.......••..•.•...•......•.•..•.•.••.. 11-43

CHAPTER 12
COMMUNICATION CONTROLLER BOARDS
iSBC® 88/45 Advanced Data Communications Processor Board ............................. 12-1
ISBC® 188/48 Advanced Communications Computer ...............••........... ~ .••..•.•.. 12-10
ISBC® 188/56 Advanced Communications Computer .••...............•.................... 12-20
ISBC®534 Four-Channel Communications Expansion Board ................................ 12-29
ISBC®544 Intelligent Communications Controller ..............•.......... : ...•............ 12-33
iSBC®561 SOEMI (Serial OEM Interface) Controller Board •.......•......•.................. 12-40
ISBC® 580 MULTICHANNEL Bus to iLBX Bus Interface ..................................... 12-45
iSBC® 589 Intelligent DMA Controller ...................................................... 12-49

CHAPTER 13
SPEECH PRODUCTS
ISBC® 570,576, 577 Intel Speech Transaction Family ......... : .....................•.•..... 13-1'
ISBC® 570 Speech li"ansactlon Development Set ....•.•.....•..••.•.............•..•....•.. 13~6
iSBC® 576 Speech Transaction Board .•........................•.....................••... 13-9
ISBC® 577 Speech li"ansactlon Recognition Chip Set •.•.............•...........••••.•.••.. 13-14

CHAPTER 14
TELECOMMUNICATIONS
CODEC AND FILTERS
2910A PCM CODEC-p Law ................................................................ 14-1
2911A-1 PCM CODEC-A Law ....••.•.•........................... : ...............••...... 14-15
2912A PCM li"ansmltlRecelve Filter .•.•.......•........................•....,.............. 14-28
Applications Information 2910A/2911A/2912A .................•..•.••••.•......•..•.•.•.... 14-38
2910Al2911A/2912A 0 DBMO Levels .........••••......................................... 14-40
COMBINED SINGLE~CHIP PCM CODE~C AND FILTERS
'
2913 and 2914 ...................................•.••....• :. : ..•.•.••.•....•••..•.•.•..•. 14-41
2916 and 2917 ..•..•.......•..•.•..•...•..•.•............................................ 14-60
29C13 and 29C14 ..•.......•..•.•..•........•.••..............................•.....•.•.. 14-76
29C16 and 29C17 ........................... <••••••••••••••• : •••••••••••••••••••••••••••• 14-95
AP-142 Designing Second Generation Digital Telephony Systems
Using the Intel 2913/2914 CO DEC/Filter COMBOCHIP : ......................•...••.•.•.•... 14-111
IATC ADVANCED TELECOMMUNICATIONS COMPONENTS
FOR ANALOG SWITCHING APPLICATIONS
SLD Interface Specification ..•.•.••......•.•.••.....•.................................... 14-130
iATC 29C51/2952 Feature Control Combo Line Card Controller .•....••...... , .•....•......•. 14-139
IATC 29C50A Feature Control Combo .•......••.•.•.......................•...•........... 14-141
iATC 29C48 Feature Control Combo ..............•.•........•.••.•.•........•..•.•....... 14-160
IATC 2952 Integrated Line Card Controller ..•.••.•.•...•...••••.•..•.•.............•....... 14-180
LCDK-29C51/52 IATC-29C51/52 Line Card Development Kit •.................•...•...•..•..• 14-195
AP-225 Line Balancing Application Brief .•...••. , .................•..•.....•....•.•••..•... 14-201
IATC ADVANCED TELECOMMUNICATIONS COMPONENTS FOR iSDN APPLICATIONS'
iATC 29C53 Digital Exchange Controller Architectural Overview ....•........•.•••.••...•.•.. 14-206
iATC 29C55 Communications Interface li"anscelver/Controller Architectural Overview .. ,....... 14-216
iATC 29C53 Digital Loop Controller .•....•.••.•............................•.•••..•...••.•14-224
OTHER AVAILABLE TELECOMMUNICATION LITERATURE ...............•.•.•••....•••••. 14-239

x

Alpha/Numeric Index
iATC 29C48 ....................................................................... 14-160
iATC 29C50A ...................................................... , .............. 14-141
iATC 29C51 ....................................................................... 14-139
iATC 2952 .................................................................. 14-139, 14-180
iATC 29C53 ............................................................... 14-206, 14-224
iATC 29C55 ....................................................................... 14-216
iNA 960 ................................. , ................................ 1-10, 5-58, 11-43
iRMX™ ............................................................................. 11-32
iSBC® 88/45 ........................................................................ 12-1
iSBC® 186/51 ................................................................. 4-21, 11-19
iSBC® 188/48 ...................................................................... 12-10
iSBC® 188/56 ....................................................................... 12-20
iSBC® 534 ......................................................................... 12-29
iSBC® 544 ......................................................................... 12-33
iSBC® 552 ......................................................................... 11-10
iSBC® 561 ......................................................................... 12-40
iSBC® 570 ..................................................................... 13-1, 13-6
iSBC® 576 ..................................................................... 13-1, 13-9
iSBC® 577 .................................................................... 13-1, 13-14
iSBC® 580 ......................................................................... 12-45
iSBC® 589 ......................................................................... 12-49
iSXM™ 552 ......................................................................... 11-10
iSXMTM 554 .......................................................................... 11-1
LCDK-29C51/52 ................................................................... 14-195
StarLAN ............................. 7-1, 7-2, 7-3, 7-4, 7-6, 7-7, 7-9, 7-10, 7-23, 7-29, 7-32, 7-40
XENIX : ............. : .............................................................. 11-38
2910A .......................................................................... : ..... 14-1
2911A-1 ............................................................................ 14-15
2912A ........................................................................•...... 14-28
2913 ........................................................................ 14-41, 14-111
29C13 ........................................ ; .................................... 14-76
2914 ........................................................................ 14-41, 14-111
29C14 ....................................................' ......................... 14-76
2916 ............................................................................... 14-60
29C16 ............................................................................. 14-95
2917 ............................................................................... 14-60
29C17 .. : .......................................................................... 14-95
8250-6 .............................................................................. 9-83
8251 ............................................................................... 9-111
8251A ....... ~ ....................................................................... 9-1
8253-6 .............................................................................. 9-83
8273/8273-4 .................................................................... 9-18, 9-142
8274 ................................................................... 9-46, 9-189, 9-226
8291A ......................................................................... 10-1, 10-2
8292 ........................................................................ 10-30, 10-57
xi

Alpha/Numeric Index
8294A .............................................................................. 10-45
80186 ........................................................... 5-4, 5-63, 5-64, 5-66, 5-67
80188 ............................................................................ 6-36, 7-29
82501 ................................
8-1
82502, ................................................................................ 8-15
82530 ........•.......................................................... 5-67, ·9-83, 9-226
82586 .................................... 2-1, 2-6, 2-7, 2-8, 2-9, 2-13, 2-14, 2-54, 3-1, 3-2, 4-3,
4-6, 4-11, 5-1, 5-2, 5-63, 5-64, 5-66, 5-67, 5-68, 8-27
82588 ....................... 1-9, 6-2, 6-4, 6-13, 6-14, 6-18, 6-39, 7-2, 7-12, 7-21, 7-29, 7-37, 8-61
i • ••••••••••••••••••••••••••••••••••••••••••••••

xii

CUSTOMER SUPPORT
CUSTOMER SUPPORT

Customer Support is Intel's complete support service that provides Intel customers with Customer
Training, Software Support and Hardware Support.
.
After a customer purchases any system hardware or software product, service and support become
major factors in determining whether that product will continue to meet a customer's expectations.
Such support requires an international support organization and a breadth of programs to meet a
variety of customer needs. Intel's extensive customer support includes factory repair services as well as
worldwide field service offices providing hardware repair services, software support services and
customer training classes.
HARDWARE SUPPORT

Hardware Support Services provides maintenance on Intel supported products at board and system
level. Both field and fac~ory services are offered. Services include several types of field maintenance
agreements, installation and warranty services, hourly contracted services (factory return for repair) and
specially negotiated support agreements for system integrators and large volume end-users having
unique service requirements. For more information contact your local Intel Sales Office.
SOFTWARE SUPPORT

Software Support Service provides maintenance on software packages via software support contracts
which include subscription services, information phone support, and updates. Consulting services can
be arranged for on-site assistance at the customer's location for both short-term and long-term needs.
For complex products such as NDS II or J2ICE, orientation/ installation packages are available
through membership in Insite User's Library, where customer-submitted programs are catalogued and
made available for a minimum fee to members. For more information contact your local Intel Sales
Office.
CUSTOMER TRAINING

Customer Training provides workshops at customer sites (by agreement) and on a regularly scheduled
basis at Intel's facilities. Intel offers a breadth of workshops on microprocessors, operating systems and
programming languages, etc. For more information on these classes contact the Training Center nearest
you.
TRAINING CENTER LOCATIONS

To obtain a complete catalog of our workshops, call the nearest Training Center in your area.
Boston
Chicago
San Francisco
Washington,D.C.
Israel
Tokyo
Osaka (Call Tokyo)
Toronto, Canada

(617) 692-1000
(3 I 2) 310-5700
(415) 940-7800
(301) 474-2878
(972) 349-491-099
03-437-661 I
03-437-661 I
(416) 675-2105

London
Munich
Paris
Stockholm
Milan
Benelux (Rotterdam)
Copenhagen
Hong Kong

xiii

(0793) 696-000
(089) 5389-1
(01) 687-22-21
(468) 734-01-00
39-2-82-44-07 I
(10) 21-23-77
(I) 198-033
5-215311-7

inter
PREFACE
Intel communication products provide complete solutions to a variety of communication needs including data
communications, telecommunications, and speech. These communication products provide vertically integrated
solutions to state-of-the-art applications. Our commitment is to supply our customers with complete hardware and
software .building blocks ranging from components up through complete systems which support industry-wide
standards as well as proprietary designs. In adoition, Intel supports customers with more than 300 field application
engineers, who each have an average of 10 years experience in electronic design.
In the area of data communications, Intel provides a broad range of products including leading-edge components,
communication boards, industry-standard software, and complete OEM systems supporting both Global Area
Networks (GANs) as well as Local Area Networks (LANs). In the GAN area we have both boards and components
supporting such standards as: Async, Bisync, HDLCfSDLC. While in the LAN area we provide components, boards,
software and systems-supporting standards such as: Ethernet/ Cheapernet, IBM PC NET, Star LAN, and MAP as well as
proprietary networks. Since our systems use our software and boards, which in turn use our components, we optimize
our designs from the components on up to provide the highest p.erformance solution at each level of the design.
Intel's speech products: open systems compatible building blocks for RMX-based factory automation systems
requiring human interaction. The speech transaction family provides application and maintenance software tools that
greatly reduce speech 1/ a interaction development time. The speech transaction board implements this result in a
variety of MULTIBUS® I environments.
Intel's broad range of VLSI building blocks cover the voice, data and integrated voice/data/video communications
needs in evolving automated offices and communications networks on a global level. By spearheading international
standards, virtual access and interface of office communication products is achieved in a manner transparent to the
user. Intel supports all levels of networks from the office through world-wide public communications standards.

xv

inter
INTEL DATA COMMUNICATIONS
FAMILY OVERVIEW
Data Communications has become an increasingly
important factor in computer system design with the
evolution of distributed processing and remote, networked peripherals. Intel's data communications product line provides a range of components to satisfy the
broad spectrum of speed, protocol support and protocol
flexibility needs (Figure I).

four more common peripheral functions of a microprocessor based system as well as a full-duplex, double buffered serial asynchronous receiyer/ transmitter with an
on-chip baud rate generator.
The 8273 is a dedicated high level peripheral controller
for SDLCf HDLC protocol support. It provides an high
level of Data Link Control support for IBM-SNA or
CClTT X.25 compatible microcomputer systems. This
device minimizes CPU overhead by supporting a comprehensive frame level operation. The 8273 is compatible
with every telephone network-based communication system due to its speed (up to 64 Kbps) and flexible modem
interface.
.

GLOBAL DATA COMMUNICATIONS:
ASVCHRONOUSANDSYNCHRONOUSPROTOCOLS
Dedicated data communications controllers
For low-to-medium speed (up to 19.2 Kbps), the 8251A
USART (U niversal Synchronous Asynchronous Receiver/
Transmitter) is the industry standard for asynchronous
communications. It can be used in such applications as
personal computers, workstations, word processors, CRT
terminals point-of-sale terminals, banking terminals,
printers, communications processors, data concentra-.
tors, industrial control networks, etc.

Multlprotocol controllers
Multi-protocol controllers bridge the gap between byte
oriented and bit oriented protocols (HDLCf SDLC).
They provide an easy migration path for the user through
a single software reconfiguration. Design of high-level
protocols like X.25 are considerably simplified when they
are coupled with the power of high performance processors such as the iAPX 86/88/ 186, or 188. They are also
used to implement custom high-level protocols on top of
standard bit-synchronous protocols.

The 8256 MUART (Multi-function Universal Asynchronous Receiver/ Transmitter) IS an highly competent
asynchronous communications controller. It considerably minimizes the number of LSI required in a system
. with an asynchronous interface. The 8256 integrates the

The dual-channel 8274 MPSC (Multi-Protocol Serial

SPEED

10Mbps

1 Mbps

e

64 Kpbs

19.2 Kbps

8
ASYNC

e
SOLC/HOLC

MULTI PROTOCOLS;
ASYNC, BYTE SYNC,
BIT SYNC

CSMAICO

FIGURE 1: A Spectrum of Data Communications Solutions

xvii

PROTOCOL
SUPPORT

inter
Controller) provide a solution for Asynchronous, Byte
Synchronous (IBM Bisync) and Bit Synchronous
(HDLC/SDLC) protocols support. It is optimized for
high-speed applications requiring the flexibility of the
protocol support and the integration· of multiple communicatio,!s channels.

The 8291A implements the Talker/Listener functions of
the GPIB.
The 8292 provides the controller functions. Operating in
tandem with the 8291 A, it complements its interface functions to provide a full-capability GPIB interface.

The 82530 SCC (Serial Communications Controller) is
another dual channel multiprotocol controller. It contains new functions including on-chip baud rate generators, digital phase locked loops, various data encoding/ decoding schemes and extensive diagnostic capabilities.
All these added features reduce the need for external logic
and greatly improve the reliability and maintainability of
the system.

The 8293 is a low-power, high-current, HMOS 8-line
transceiver. It provides the electrical interface to the
GPIB.

Local Area Networks
Intel has developed the first complete VLSI solution for
Local Area Networks (LANs) and Ethernet in particular:
the 82586 Local Area Network Coporcessor and the
82501 ESI (Ethernet Serial Interface).

Distributed Intelligence Systems
The 8044 /8744 is a microcontroller with an on chip serial
communication processor. I t simplifies control of remote
subsystems (subsystems that are physically separated
from the host CPU and communicate over a serial link).

Four on chip DMA channels allow the 82586 to operate
as a bus master. The 82586 manages the entire process of
transmitting and receiving frames, thereby relieving the
host p~ocessorof the tasks of managing the communication interface to the network.

The 8044 and 8051. CPUs are identical. The serial communication is handled by an additional processor called
the Seriallnterface Unit (SIU). The SIU operates concurrently with the CPU and offers a high level of intelligence
and performance for HDLCjSDLC based communications. The SIU can handle 2.4 Mbps in Half-Duplex
mode.
.

An extensive set of diagnostic capabilities, implemented
in silicon, simplifies the design of more reliable local
networks and facilitates their maintenance. In order to
take full advantage ofthe LAN concept and CSMA/ CD
access method, the 82586 architecture is software configurable. This allows the 82586 to be "customized" for
other applications including serial backplanes (serial
peripherai interconnection), low cost short distance
LANs; broadband networks and medium speed (1-,-2
Mbps) LANs.

In addition to controlling communications with the host
CPU, the 8044 provides significant peripheral control.
Examples include local keyboard, CRT and printer control as well as design of network for Distributed Intelligence Systems (Medical instrumentation, CATV, PABX,
etc ....)

The 82501 is designed to work directly with the 82586 in
Ethernet applications. The major functions of the ESI are
to generate the 10 MHz transmit clock for the 82586, to
perform Manchester encoding/ decoding oftransmitted/received frames, and to provide the electrical interface to
the Ethernet transceiver cable

Detailed 8044/8744 information is contained in the Intel
Microcontroller Handbook.

Instrumentation
The Intel Data Communications product family provides
a wide range of solutions for the needs of data communications systems.
.

The 8291 A, 8292, and 8293 family of components provide
complete, high-performance support for IEEE-488
(GPIB) standard interface. GPIB is used in instrumenta~
tion applications.

xviii

Introduction

1

CHAPTER 1
INTRODUCTION
tionally, Tier 2 will connect the expensive peripherals,
such as plotters and file servers to the network. A network such as this probably does not exist today but it
may be typical of a departmental network in the near
future.

1.0 OVERVIEW
Through the 1970's, with the evolution of the microprocessor, the concept of distributed processing became
ever more attractive. The ability to integrate the intelligence of yesterday's boards onto todays chips drove the
cost of computing to a point where decentralization of
processing was not only feasible, but practical as well.
In the 1980's, we have seen the advent of engineering
workstations, instrumentation, personal computers,
printers, and much more, all with the capability of performing their respective tasks independently of any supervisory machine. This decentralization of computing
power has brought about the need to interconnect the
different "nodes" in order to fulfill the following requirements. First, by interconnecting, we allow for the
sharing of expensive peripheral resources like printers,
plotters and file servers. Second, we allow for the sharing of information via common data bases. Finally,
high level services, such as electronic mail, are supplied.
Thus was the concept of networking born.

Just as the different tiers have varied requirements, so,
too, will the characteristics of each department's LAN
vary depending on which organization they serve within the company. In general, the different departments
within most companies can be divided into three distinct environments: factory, engineering, and office. On
the factory floor, where a typical application is networking process control stations and robotics controllers, a network must be able to span a large distance
while maintaining a high degree of noise immunity.
Futhermore, the ability for each node to send a message
must be deterministic, in that each must have a chance
to transmit in a given interval of time. For engineering
applications, in which CAD/CAE workstations are interconnected, the required network characteristics are
high throughput over short to moderate distances. Finally, in the office the primary need is the interconnection of personal computers. This application is highly
cost sensitive but doesn't need the same high throughput or distance as in the factory or engineering lab. As
you can see, because of the different applications and
varied requirements of each, no single LAN will be able
to support them all. As such, many LANs have evolved
over the last five to ten years. But, which of these will
be on the market five to ten years from now?

The definition of a network in its broadest sense is a
system of processing units connected by communication lines. This definition can be broken down further
based on the characteristics of a specific network. One
special type of network is a Local Area Network or
LAN. A LAN is defined as being a network supporting
peer-to-peer communication over distances of tens of
meters to several kilometers. Peer-to-peer implies that
each station on the network is its own boss, i.e., there is
no master-slave relationship. This chapter describes Local Area Networks vis-a-vis open system architecture.
Also, a discussion of existing and emerging Local Area
Network standards is presented, followed by an overview of Intel's Local Area Network components and
related products and how they map into the existing
and emerging standards.

There are four attributes that a Local Area Network
must have in order to insure its own longevity. First, it
must be backed by one or more major companies. Not
only will the associated companies add credibility to
the network, but they also provide the capital to cover
developmenfcosts. Second, the existence of VLSI is essential. VLSI reduces cost and simplifies the design.
Standardized software is the third essential ingredient.
It allows for standard interfaces in addition to minimizing time to market. Finally, and most importantly, the
network itself must be an industry standard. The end
user needs to be able to purchase a personal computer
from one company, a file server from a second and a
printer from a third, interconnect them by simply
"plugging them in" and not have to worry about low
level concerns such as protocols or media.

1.0.1 LAN Requirements
At Intel, we have adopted a model of hypothetical Local Area Network implementation (see Figure 1-1). For
this model there are three different "tiers" where each
tier's performance characteristics are application specific. Tier I is the mainframe to mainframe interconnection. This type of network will be called on to transfer
large data bases in an efficient manner so speed
(20-100 Mbps) is essential while cost is not as sensitive.
Tier 3 consists of departmental clusters linking, for example, a group of PCs in the Finance department or
several process control stations on the factory floor.
Providing the interface between various clusters and a
gateway to Tier 1 is the LAN backbone of Tier 2. Addi-

The International Standards Organization (ISO) and
the IEEE have for several years been developing the
models on which networking standards are based as
well as the standards themselves. The next section overviews the activities of these two bodies in generating
networking standards.
1-1

LAN COMPONENTS USER'S MANUAL

TIER 1: COMPUTER - TO - COMPUTER

TIER 2: LAN BACKBONE
TIER 3:
DEPARTMENT
CLUSTERS

~--~---

r--~~~

230814-81

Figure 1-1. The Three-Tiered Networking Model

Open Systems Interconnect (OSI) reference model. In
simple terms, the model logically groups the functions
and sets of rules, called protocols, necessary to establish
and conduct communication between two or more parties. The model consists of seven functions, often referred to as layers. The OSI model describes the functions of each later in broad terms, not specific implementations.

1.1 NETWORKING SOLUTIONS VIA
STANDARDS
Networking is not a new concept, but until recently,
networks have been of a proprietary nature. In the past,
~n end user had to buy all of its computing equipment
from the same vendor in order to interconnect it. This
problem was solved when the concept of "open systems" was developed. An open system is built using
widely accepted standards. Open systems allow the end
user to purchase equipment from several vendors in order to realize an optimal solution for any given application. Note that when a standard becomes widely accepted, it also becomes feasible to implement the standard in VLSI, thereby lowering the overall per node
connection.

This layered model approach affords two key advantages. First, layers allow a clear division of the design
task through modularity making specifications clean.
Second, systems based on a layered architecture are
flexible: Flexibility is achieved-because each layer functions independently of the layer above or below it.
Thus, specific layer implementations can be changed
easily. For example, layers 1 and 2 of a network can be
changed to be either CSMA/CD based (e.g., IEEE
802.3) or token ring based (e.g., IEEE 802.5), without
affecting layers 3 through. 7.

1.1.1 The ISO Model
The International Standard Organization (ISO), in an
effort to encourage "open" networks, developed the

The layer functions of the OSI model are summarized
in Figure 1-2.

1-2

LAN COMPONENTS USER'S MANUAL

LAYER
NUMBER

I~

NETWORK
MANAGEMENT

I
I

FUNCTION

APPLICATION

7

SELECTS APPROPRIATE SERVICE FOR APPLICATIONS

f----

PRESENTATION

6

PROVIDES CODE CONVERSION, DATA REFORMATTING

f----

SESSION

5

COORDINATES INTERACTION BETWEEN
END-APPLICATION PROCESSES

f----

TRANSPORT

4

PROVIDES END-TO-END DATA INTEGRITY
AND QUALITY OF SERVICE

r----

NETWORK

3 SWITCHES AND ROUTES INFORMATION

-

DATA LINK

2 TRANSFERS UNITS OF INFORMATION TO
OTHER END OF PHYSICAL LINK

---

1 TRANSMITS BIT STREAM TO MEDIUM

PHYSICAL

230814-1

Figure 1·2. Layer Functions of the OSI Model
The Physical Layer describes the physical media over
which the bit stream is to be transmitted. This Layer
specifies type of cable (coax, twisted pair, etc.), connectors, signal levels, bit rate, data encoding method, modulation method, and method for detecting collisions in
contention networks. In short, this Layer describes the
actual physical media over which the bit stream is
transmitted and the method of transmission, i.e:, baseband or broadband.

The Session Layer establishes and terminates logical
connections between network entities. This Layer is
also responsible for the mapping of logical names into
network addresses.
The Presentation Layer provides for any necessary
translation, format conversion, or code conversion to
put the information into a recognizable form.
The Application Layer provides network based services
to the end user. Examples of network services are distributed data bases and electronic mail. The Application Layer is not to be confused with the end user application itself.

The Data Link describes the rules for transmitting on
the channel (made up of the encoder/decoder, trans. ceiver cable, and transmission medium). Such items as
the format of the information (frame) and procedures
for gaining control of the channel (access method),
transmitting the frame and releasing the physical media
are specified by the Data Link Layer.

Network. Management is responsible for operation
planning, which includes the gllthering of opera~ional
statistics such as errors and traffic. It is also responsible
for network initialization and maintenance (fault isola.tion). Network Management interfaces to each of the
seven layers.

The Network Layer controls switching between Imks in
a multihop network. The Network Layer is not necessary for a single LAN system because all stations connected onto a LAN share the same channel. This Layer
is critical in gateway, communication server, and dialup-communication applications.

THE OSI MODEL AND NETWORK
IMPLEMENTATIONS

The Transport Layer ensures end-to-end message integrity and provides for the required quality of service for
exchanged information. For example, end-to-end acknowledgements and flow control are performed by the
Transport Layer.

The Physical and Data Link Layers of the OSI model
ensure interconnectability. By implementing a particular physical and data link specification, equipment from
multiple vendors can be physically and electrically con-

1-3

LAN COMPONENTS USER'S MANUAL

nected. The remaining five layers of the OSI model ensure interoperation among the interconnected stations
in an open network.

CSMA/CD

Carrier Sense Multiple Access with Collision Detection
(CSMA/CD) is a simple and efficient means of determining how a station transmits information over common medium that is shared with other stations.
CSMA/CD is the access method defined by the IEEE
802.3 standard.

For example, Intel's NDS-II Multi-User Networked
Microcomputer Development System is a LAN based
system utilizing IEEE 802.3 10Base5 (Ethernet) for
Layers 1 and·2 and Intel Network ArchiteCture (iNA)
for Layers 3 through 7. Non-Intel equipment wishing
to connect to the physical network need only adhere to
the Ethernet specifications to ensure proper interconnection and gain access to the "data highway." In order
to communicate with the system's Network Resource
Manager (for interoperation), the foreign station would
have to conform to the remaining Layers of iNA.

Carrier Sense (CS) means that any station wishing to
transmit "listens" first. When the channel is busy (i.e.,
some other station is transmitting) the station waits
(defers) until the channel is clear before transmitting.
Multiple Access (MA) means that any stations wishing
to transmit can do so. No central controller is needed to
decide who is able to transmit and in what order. The
environment in which all stations on the network are
peers with equal access is commonly referred to as distributed control.

The ISO open system interconnect model has been
adopted by the IEEE standards board for use in defining their standards for the various layers.

1.1.2 The IEEE 802 Committee

Collision Detection (CD) means that when the channel
is idle (no other station is transmitting) a station can
start transmitting. It is possible for two stations to start
transmitting simtiltaneou~ly causing a "collision". In
the event of a collision, the transmitting stations will
continue transmitting for a fixed time to ensure that all
transmitting stations detect the collision. This is known
as jamming. After the jam, the stations stoP. transmitting and wait a random period of time before retrying.
The range of random wait times increases with the
number of successive collisions such that collisions can
be resolved even if a large number of stations are colliding.

The Institute of Electrical and Electronics Engineers
(IEEE), in response to a need for standardization in the
field of Local Area Networks, formed the IEEE 802
standard body. The 802 standards specify the different
protocols,. access methods and their relationship with
the ISO Open System Interconnection (OSI) Reference
Model for Layer 1 and Layer 2 (see Figure 1-3). IEEE
802.1 explains how the different standards relate to
each other and how they map into the OSI model. The
Logical Link Control standard is outlined by IEEE
802.2. IEEE 802.3, 802.4 and 802.5 specify the three
different media access methods; CSMA/CD, token bus
and token ring respectively.

80Z.11
80Z;Z

-

There are three significant advantages to the
CSMA/CD protocol. The first and foremost is that
CSMA/CD is a proven technology. One CSMA/CD
network, Ethernet, has been used by Xerox since 1975.
Ethernet is so well understood and accepted that IEEE
adopted it (with minor changes) as the IEEE 802.3
IOBaseS (10 Mbps, Baseband, 500 meters per segment)
standard. Reliability is the second advantage to the
802.3 protocol. This media access method enables the
network to operate without central control or switching. Thus, if a single station malfunctions, the rest of
the network can continue operation. Finally, since
CSMA/CD networks are of a passive, distributed nature, they allow for easy expansion. New nodes can be
added at any time without reinitializing the entire network.

---DATA LINK
LAYER

1'' '11'' '11'' '1 ,-P_~_~_~I_~R_AL_
230814-82

Figure 1-3. The IEEE 802
Standards Committees

1-4

LAN COMPONENTS USER'S MANUAL

protocol that comes along. As a result, there are certain
medium access control technologies that will be accepted as industry standards for given applications. Described here are the protocols that are already accepted,
as well as those that are emerging, as industry-wide
standards.

TOKEN PASSING PROTOCOLS

The IEEE 802.4 standard outlines the Token Bus media access method. A token is a group of coded bits that
are passed from station to station on the network. The
station that controls or "possesses" the token also controls the right of access to the link. So, as the token is
passed, control' of medium access is also passed. The
link is a physical bus in that all the stations are attached
to a common medium, but the token is passed from
station to station forming a logical ring. For this reason, the token bus protocol has been identified as being
a "logical ring on a physical bus".

ETHERNET/CHEAPERNET

The IEEE 802.3 IOBaseS standard (Ethernet) has
gained wide acceptance by both large and small corporations as a high speed (10 Mbps) Local Area Network.
The Ethernet channel is a low noise, shielded son coaxial cable over which information is transmitted at 10
million bits per second. Each segment of cable can be
up to SOO meters in length and can be connected into
longer network'lengths using repeaters. Repeaters are
responsible for regenerating the signal from one cable
segment on another. At each end of a cable segment a
terminator is attached. This passive device provides the
proper electrical termination to eliminate reflections.

During steady state operation, there are two possible
activities, data transfer and token passing. During the
data transfer phase, a given station possesses the token
and simply transmits data to one or more of the other
stations of the link. Stations not possessing the token do
-not transmit, but listen to transmission for an addre~s
match. After a transmission is complete, the token IS
passed to the next station in the logical ring. This is the
token passing phase.

The transceiver transmits and receives signals on the
coaxial cable. In addition, it isolates the node from the
channel so that a failure within the node will not affect
the rest of the network. The transceiver is also responsible for detecting when two or more stations transmit
simultaneously (collisions). Ethernet transceivers are
connected to the network coaxial cable using a simple
tap, and to the station it serves via the transceiver cable
which can be up to so meters in length.

Although the transmission of data and token passing
are straightforward operations, network maintenance
tasks make the token bus protocol relatively complex.
The functions of network initialization, lost token recovery, adding new stations and general logical ring
housekeeping are difficult to implement. Additionally,
all these functions must be replicated among all the
token using stations on a given network in a prioritized
fashion.

Finally, an Ethernet interface, which includes a serial
interface and a data link controller, provides the connection to the user or server station. It also performs
frame manipulation, addressing, detecting transmission
errors, network link management and enco?ing and decoding of the data to and from the transceiver.

Despite the relative complexity of the token bus access
method, there are two notable features. In general, the
primary advantage to token passing protocols is that
they are deterministic as opposed to probabilistic. What
this means is that every station will have a definite opportunity to transmit within a given. i~terval of ti.n;te.
With CSMA/CD, there is only a statistical probabilIty
that ea~h station will be able to transmit. In addition to
the deterministic feature, token bus networks have the
ability to span large distances, more than 10 kilometers.

Due to its high speed and relatively high cost, Ethernet
is targeted,to be a LAN l;!ackbone for ~e enginee~ng
and office environments. It is also feasible to utilize
Ethernet in engineering workstation and personal computer cluster applications where cost is not a sensitive
issue.

There is a second token passing network that IS emerging. IBM sponsors a token ring protocol as a LAN
backbone. Token ring is similar to token bus except
that in addition to being a logical ring it is also a physical ring. The token ring procotol is governed by the
IEEE 802.S committee. It has similar performance
characteristics as the token bus protocol.

One of the major contributors to the high cost per connection of Ethernet is the cable. Ethernet cable must be
highly immune to noise so that each cable .segment can
be SOO meters in length. In response to thiS drawback,
Cheapernet was developed. Cheapernet is identical to
Ethernet with the following exceptions. First, less expensive RG-S8 CATV coaxial cable is used as the network link. Second, the transceiver function is integrated into the n04e. Consequently each node is connected
to the link via a BNC T-connector. Use of the lower
performance cable limits Cheapernet to 18S meter segments with 30 nodes per segment.

1.1.3 Existing and Emerging Medium
Access Standards
It has been established that no single LAN technology

can satisfy the needs of every application. But, at the
same time, the LAN marketplace cannot support every
1-5

LAN COMPONENTS USER'S MANUAL

Cheape~et preserves the high data transfer rate of
Ethernet, but reduces the per node cost considerably.
For this reason, Cheapernet is optimized for high performance workstation or personal computer. network
clusters.

radius. A key feature of this network is the IBM PC
Network Translator Unit. The Translator Unit provides broadband frequency translation from the return
channel to the forward channel,for a passive IBM PC
Network. For greater capability, the IBM PC Network
can be used in a professionally installed broadband network allowing up to 1000 IBM Personal Computers
within a 5 Km radius of the network translator unit.

OPTIMIZED BROADBAND (IBM PC NETWORK)

In August 1984, IBM announced a new lost cost IBM
PC Network based on single frequency i Mbps
CSMAlCD broadband technology. This network was
proposed to the IEEE 802.3 committee under the name
of Optimized Broadband by Sytek, Intel and General
Instrument. The IBM PC Network uses standard
CATV coaxial cables and hardware connections.

The IBM PC Network can be used as either a Tier 2 or
Tier 3 network. For aTier 2 network the professionally
installed broadband network would be used. This
would have the advantage of covering a large area, such
as a campus, and provide a high degree of connectivity.
In a Tier 3 network the user installable option .would be
chosen, thus keeping the expense of installation at a
minimum.

The IBM PC Network, in a user installable configuration, can handle up to 72 nodes and span 1000 foot
ETHERNET:

TRANSCEIVER
CABLE

ETHERNET CONTROLLER BOARD

COAX CABLE
TRANSCEIVER

230814-5

CHEAPERNET:
CHEAPERNET· CONTROLLER BOARD

l

RG-58
COAXIAL CABLE

230814-B3

Figure 1-4. Ethernet/Cheapernet Configurations
1-6

LAN COMPONENTS USER'S MANUAL

CUSTOM
SERIAL
INTERFACE

CONNECTIONS FOR
EIGHT ADDITIONAL
EIGHT- WAY SPLInERS

BASE
EXPANDER
SYSTEM BUS

MODEM
NETWORK
TRANSLATOR
EIGHT-WAY
SPLInER

SYSTEM
MEMORY
SYSTEM BUS
230814-84

Figure 1-5. Optimized Broadband (IBM PC Network)
Using Both the 82586 and the 82588

There are distinct advantages of going with broadband
technology. CATV cables and connectors are inexpensive and readily available. These cables and connectors
provide the capability for a user installable network as
opposed to a professionally installable network like
Ethernet. Broadband also allows a much greater usable
bandwidth than baseband. Typical usable bandwidth
on a broadband cable is in the range of 400 MHz while
baseband is around 10 MHz. Thus broadband networks
can be expandable utilizing the available bandwidth.
Additional features such as real time voice and real
time video can be integrated into a broadband network.
Broadband networks can cover a larger area than baseband networks such as Ethernet and Cheapernet.
Ethernet can cover a 2.5 Km radius, while IBM PC net
can cover a 5 Km radius.

star-shaped clusters. Each hub serves as the point of
concentration, similar to a telephone wiring closet and
performs two major functions: signal regeneration and·
retiming (for retransmission to other stations and hubs)
and collision detection. When two stations transmit
simultaneously and a collision occurs, the hub will send
a collision presence signal to all receivers. The hubs can
be cascaded up to five levels and each station-to-hub or
hub~to-hub interconnection can be up to 250 meters in
length.
STARLAN was developed for personal computer network clusters and has several features that make it ideal
for this application. Cost is the most sensitive issue in
the personal computer field and the STARLAN hardware and cabling scheme are designed to be inexpensive. The cabling scheme uses standard twisted-pair telephone wiring and is laid out in.a similar fashion where
the STARLAN hub is analagous to a telephone wiring
closet. Todays buildings are designed with this cabling
scheme in mind which means installation, reconfiguring and servicjng will be easy and low cost as well.
Futhermore, most buildings use only about one half of
the existing telephone cabling so the spares can be easily used for a STARLAN network.

STAR LAN

A fourth CSMA/CD network sponsored by the IEEE
802.3 committee is the 1 Mbps baseband standard or
STARLAN. For STARLAN, each station is connected
to a "hub" and each hub can be connected to another
hub in point-to-point fashion. The result is cascaded

1-7

LAN COMPONENTS USER'S MANUAL

~p

CLOCK

230814-85

Figure 1-6. STARLAN Configuration

1.2 THE INTEL LAN SOLUTION

1.2.2 Intel's Ethernet/Cheapernet
ChipSet

1.2.1 A Commitment To Standards

THE 82586 LAN COPROCESSOR

Intel Corporation has been and will continue to be dedicated to driving Local Area Network industry standards. The application base created by a widely accepted standard makes it viable to design and manufacture
VLSI solutions. In tum, VLSI drives down the system
cost which benefits the end user. Against this background, Intel has been deeply involved in the IEEE
LAN standards boards.

The 8258.6 is an intelligent peripheral that completely
manages the processes of transmitting and receiving
frames over a network. The 82586 offioads the host
CPU of the tasks related to managing communication
activities. More importantly, the 82586 does not depend on the host CPU for time critical functions (e.g.,
transmission and reception of frames). Hence, the
82586 is truly a coprocessor.

Today, Intel has the most complete range ofVLSI, software and boards to support the existing and emerging
industry standards for Local Area Networks. The
82586 LAN Coprocessor, the 82501 Ethernet Serial Interface and the 82502 Ethernet Transceiver Chip make
up Intel's three chip set for IEEE 802.3 10 Mbps networks (Ethernet and Cheapernet). For the mid-range
LAN applications, i.e., STARLAN and IBM PC Net,
Intel offers the 82588 Single-Chip LAN Coprocessor.
Finally, iNA960 is Intel's ISO 8073 compatible Transport Layer Software. Intel also supplies several addition
board and software solutions in the networking field.
For information on these product lines, please contact
your local Intel Field Sales representative.

In addition to the high performance of the 82586, it
also features a high degree of flexibility. The 82586's
network parameters are programmable so that LANs
optimized to specific applications can be realized.
When powered up, the chip defaults to the Ethernet/Cheapernet configuration. But when programmed
accordingly, the 82586 can support STARLAN, IBM
PC Net, MIRLAN and a wide range of proprietary
Local Area Networks. Because of its flexibility, the
82586 is also ideal for Serial Backplane applications.
The 82586 interfaces easily to available microprocessors. Systems requiring minimum component count can
1-8

LAN COMPONENTS USER'S MANUAL

take advantage of the 82586's direct interface (no "TTL
glue") to Intel's 80188 (8-bit bus) and 80186 (16-bit)
microprocessors.

• A defeatable Signal Quality Error (SQE) test which
verifies functionality of the collision detection circuitry.
• On-chip precision voltage reference which allows for
relaxed power supply tolerances.
• CHMOS technology which allows the 82502 to run
at very low power consumption levels, thus enhancing reliability.

The 82586 efficiently uses memory through data "buffer chaining." System memory is not wasted because
short frames (75% of network traffic is less than 100
bytes) can be saved in buffers of minimal size, while
long frames are saved by successively chaining buffers
together. The 82586 manages this chaining process
without CPU intervention, thereby maintaining high
system performance.

The 82502 supports Ethernet, Cheapernet and repeater
transceiver applications.

The 82586 provides a rich set of node/network management and maintenance capabilities. Included are:
• Error tallies in system memory to monitor:
- Number of frames incorrectly received due to
CRC errors
- Number offrames incorrectly received due to misaligned frames
- Number of collisions experienced while trying to
transmit a specific frame
- Number of frames lost due to lack of receive buffers
- Number of frames lost due to DMA overrun while
receiving frames
• Monitoring of the node's collision detection failure
reporting mechanism.

1.2.3 The 82588 Single-Chip LAN
Controller
The 82588 is a highly integrated LAN controller targeted for use in cost sensitive CSMA/CD LAN applications, in particular, personal computer interconnection.
The 82588 integrates most of the OSI Layer 1 and 2
functions onto a single chip. Included are a CSMAicD
data link controller, a data encoder and decoder and
two different collision detection mechanisms. This
high-integration allows the system designer to reduce
component count, and thus reduce board space and development time. The functionality of the 82588 is optimized at up to 2 Mbps in either baseband or broadband
networks.
Like the 82586, the network parameters of the 82588
are programmable, providing the flexibility to support
numerous LAN applications. Among the programmable parameters are:
- Framing (end of carrier or SDLC)

The 82586 provides diagnostic capability via internal
and external loopback service. Distance to cable breaks
and shorts is provided by on-chip time domain reflectometry.

THE 82501 ETHERNET SERIAL INTERFACE

The 82501 is designed to work directly with the 82586
in 10 Mbps LAN applications. The primary function of
the 82501 is to perform Manchester encoding/decoding, provide 10 MHz transmit and receive clocks to the
82586, and to drive the transceiver cable. The 82501
provides for fault isolation via an internal loopback.
Continuous transmission (babbling) is prevented by an
on-chip watchdog timer.

Address Field Length
Station Priority
Interframe Spacing
Slot Time
CRC-32 or CRC-16
NRZI or Manchester encoding/decoding

Additionally, the 82588 supports a variety of frame formats and network topologies. The 82588 is compatible
with the STARLAN (1 Mbps baseband) and Optimized
Broadband (IBM PC Network, 2 Mbps Broadband)
networking standards.

The 82501 is compatible with the IEEE 802.3 10 Mbps
standards for Ethernet and Cheapernet.

A major breakthrough of the 82588 are the two methods of logic based collision detection. The Code Violation method detects a collision when a data transition
occurs outside of the specified regions. The Bit Comparison method compares the "signature" of a transmitted frame to the receive frame "signature" while listening to itself.

THE 82502 ETHERNET TRANSCEIVER CHIP

The 82502 rounds out Intel's three chip set for IEEE
802.3 10 Mbps LAN Standards. Transmission of data
onto the network coaxial cable, reception of data from
the coax and collision detection are the three primary
functions of the 82502. Additional features are:
• Anti-jabber watchdog timer to prevent continuous
transmissi<)n by a single station.
1-9

LAN COMPONENTS USER'S MANUAL

SOLUTIONS

STANDARDS

l

J-

APPLICATION

NETWORK
MANAGEMENT

J

I

PRESENTATION

SESSION

rINA960

f---+

TRANSPORT

~

NETWORK

}ISO 8073

TRANSPORT SOFTWARE/NETWORK MANAGER ~

:= ~

82586 LAN COPROCESSOR
AND

DATA LINK

~

82501 ETHERNET SERIAL INTERFACE
AND

'-~

PHYSICAL

}",,~,"

82C502 ETHERNET TRANSCEIVER CHIP
OR
82588 SINGLE CHIP LAN CONTROLLER

230814-86

Figure 1-7. Intel's LAN Component Solutions

Another significant feature of the 82588 is its friendly
system interface. High level commands such as
TRANSMIT and CONFIGURE are used. The 82588
supports the same buffer chaining reception method
used in the 82586 which provides for efficient memory
usage. Finally, the 82588 has a complete set of network
management, maintenance and diagnostic capabilities
that allow the designer to minimize debug· time and
maintain top network efficiency.

1.2.4 The iNA 960 Transport Software
iNA 960 is a general purpose Local Area Network software package that provides the user with guaranteed
end to end message delivery. iNA 960 conforms to the
International Standards Organization'S 8073 specification' for Class 4 transport layer services. iNA 960 also
provides network management functions, and 82586
device drivers.
TRANSPORT SERVICES

The iNA 960 transport layer implements two kinds of
message delivery services: virtual circuits and datagram. Virtual circuits provide a reliable point-to-point
message delivery service ensuring maximum data integrity and are fully compatible with the ISO 8073 Class 4
protocol. In addition to guarantee message integrity;
iNA 960:
• Provides flow control (data rate matching between
sender and receiver).

• Supports multiple simultaneous connections (process multiplexing).
• Handles variable length messages (independently of
physical frame size).
• Supports expedited delivery (to transmit urgent
data).
The datagram option provides "best effort" delivery
service for non-critical messages. The datagram service
does not guarantee message integrity but requires less
channel overhead than virtual circuits.
NETWORK MANAGEMENT SERVICES

The Network Management facility supports the users
of the network in planning, operating, and maintaining
the network by providing network usage statistics, by
allowing the monitoring of network functions and by
detecting, isolating, and correcting network faults.
The Network Management facility also supports upline dumping and down-line loading of data bases or to
boot systems without a local mass storage.
USER ENVIRONMENT

In the iRMX (Intel's real time, multitasking operating
system) environment, both the user programs and iNA
960 run under iRMX 86. The communications software
is implemented as an iRMX 86 job requiring the nucleus only for most operations. The only exception is the
boot server option, which also needs the Basic I/O Sys1-10 /

LAN COMPONENTS USER'S MANUAL

tern. iNA 960 will run in any iRMX environment including configurations based on the 80130 software on
silicon component.

communications tasks is necessary for performance reasons, the user may wish to dedicate a processor for
communication purposes. iNA 960 can be configured
to support such implementations by providing network
services on an 8086, 8088, or 80186 microprocessor.

In those systems where iRMX 86 is not the primary
operating system, or where offloading the host of the

TYPICAL iNA 960
HARDWARE ENVIRONMENTS

ISO MODEL

I

END-USER APPLICATION PROCESS

~
NETWORK
MANAGEMENT

APPLICATION

PRESENTATION
ISBC' 186/51
COMMpuler
BOARD

SESSION

TRANSPORT
IMPLE>-MENTED
BY iNA 96

NETWORK
DATA
LINK
LAYER

tl

o
iSXM 552
COMMenglne
BOARD

DATA LINK INTERFACE

-----------------PHYSICAL DATA LINK
}
PHYSICAL

IMPLEMENTED
BY 82586/82501 182C502
BASEDHARDWARE

230614-6

Figure 1-8. iNA 960 Software

1-11

82586 LAN Coprocessor

2

CHAPTER 2
THE 82586 LAN COPROCESSOR
without losing data, and bus transfer rates as low as 2
megabytes per second. The high performance permits
the 82586 to be used in distributed processing applications such as high speed resource sharing and interprocessor communications.

2.0 OVERVIEW
This chapter describes the features and operation of the
82586 LAN Coprocessor. It is assumed that the reader
is familiar with the basic concepts of Data Communication, Local Area Networks (LAN), and the IEEE 802.3
Standard.

The 82586's programmable network parameters allows
it to serve as controller for a wide range of CSMA/CD
type LAN's. It is compatible with network specifications such as high service (broadband), high performance (short topologies) and low cost (I Mbps) networks. Data rates less than to megabits per second are
supported. Many parameters are configurable including
all framing parameters (i.e. address length, End of Carrier or Bitstuffing frame boundary delineation, etc.),
Slot Time and Interframe Spacing.

This Chapter is divided into three parts, each part covers several sections:
I) A general description of the 82586.
2) A description of the major functions performed by
the 82586 for the user:
• Transmit Functions
• Receive Functions
• Network Management and Diagnostic Functions

Network and station reliability is enhanced by built-in
diagnostic aids, such as Time Domain Reflectometer
(TDR), external and internalloopback, Transceiver integrity verification, internal register dump and a self test procedure.

• Interaction with the Host CPU
3) Detailed instructions on how to use the 82586:
• Initializing the 82586
• Controlling the 82586

The 82586 is contained -in a 48-pin dual i~-line package.
Figure 2-1 shows the pin layout.

• Action Commands
• Frame Reception
• Bus Interface Hardware

Signals in parentheses are available in Minimum mode.

• Network Interface Hardware
A20

Pin functions, electrical and timing characteristics are
located In the 82586 Data Sheet, included as part of this
User's Manual.

A19/S6
AlB

2.1 OVERVIEW OF THE 82586 LAN
COPROCESSOR
The 82586 VLSI chip is an intelligent, high performance, CSMA/CD (Carrier Sense Multiple Access with
Collision Detection) communications controller. The
82586 performs all functions associated with data transfer between user memory and the Network: framing,
link management, address filtering, error detection,
data encoding, network management, Direct Memory
Access (DMA), buffer chaining, and interpretation of
high level commands from the user. Called the LAN
Coprocessor, the 82586 was designed to relieve the host
CPU of most tasks associated with controlling access to
aLAN.
.

A22 (RD)

A17

A23(WR)

A16

BHE

AD1S

HOLD

AD14

HlDA

AD13

51 (DT/Ii)

AD12

SO (DEN)

AD11

READY (ALE)

AD10

Vss

The 82586 meets the performance requirements of the
IEEE 802.3 Standard: to megabits per second bit rate
and 9.6 microseconds Interframe Spacing. In addition
to providing DMA transfers at 4 megabytes per second,
it tolerates local bus latency of over 10 microseconds

Vee
A21

INT
SRDY/ARDY

AD9

Vee

ADB

CA

AD7

RESET

AD6

MN/MX

ADS

ClK

AD4

CRS

AD3

COT

AD2

CTS

ADl

RTS

ADO

TXD

RXC

TXC

Vss

RXD

230814-14

Figure 2-1. The 82586 Pin Configuration
2-1

LAN COMPONENTS USER'S MANUAL

The 82586 has two interfaces: Bus Interface to the local
bus and the CPU; Network Interface to the Serial Interface Unit.

The major application of the 82586 is to serve as the
communication manager in a station connected to a
LAN. Such a LAN station typically consists of a host
CPU, shared memory, an 82586 Local Communication
Controller, Serial Interface Unit, Transceiver, and
LAN link. The '82586's task is to perform functions
associated with transferring data between shared memory and the LAN link. .As an example, Figure 2-2
shows the 82586 in a workstation connected to an
IEEE 802.3 network.

,--------- --

On the Bus side, the 82586 is a 'master' on the 8 or 16bit local bus, and communicates directly with the CPU
via Channel Attention (CA) and Interrupt (INT) signals. It is optimized for operation with the iAPX 186
bus but can be used with other general purpose processors.

--------- ....... _------

1

1

I,

SYSTEM
MEMORY

,I

I

'I

82586

HOST
CPU

LAN
COPROCESSOR

SERIAL
INTERFACE
82501
ETHERNET
SERIAL
INTERFACE
TRANSCEIVER
CABLE

82502
IEEE 802,3 COMPATIBLE
WORKSTATION

ETHERNET
TRANSCEIVER
CHIP

IEEE 802.3/ETHERNET LINK

230814-15

Figure 2-2. An IEEE 802.3 (10BASE5) Compatible Workstation

2-2

LAN COMPONENTS USER'S MANUAL

On the Network side, the 82586 is connected to an
Ethernet Serial Interface that provides Transmit and
Receive Clock and Data, Collision Detect, Carrier
Sense, and Request to Send/Clear to Send signals to the
82586. The Ethernet Serial Interface is connected to the
Transceiver, which is connected to the LAN link. In
the particular case of the IEEE 802.3 (IOBASE5) station, the Ethernet Serial Interface is Intel's 82501 and
the Ethernet Transceiver is Intel's 82502.

Figure 2-3 shows the fields in a frame: the Preamble is
used as a synchronizing sequence for bit decoding, followed by the Start Frame Delimiter Field, SFD. Next,
the Destination Address is the frame target address.
This field is followed by the Source Address (sender's
address). The Length and Data Fields contain user supplied data. The Frame Check Sequence is a Cyclic Redundancy Check, CRC, used in detecting bit errors.
Two optional fields may follow, End of Frame (EOF)
flag and Padding. The latter extends the length of the
frame to ensure minimum frame length.

2.2 82586 TRANSMIT FUNCTIONS

The 82586 handles Frame Boundary Delineation completely transparent to the user. The fields involved in
the Frame Boundary Delineation are: Preamble, SFD
Field, EOF flag and· Padding. The 82586 is configurable to one of two Frame delineation methods: End of
Carrier or Bitstuffing.

The 82586 LAN Coprocessor performs two major
tasks: transmitting data from host memory to the Network and receiving data from the Network and placing
it in memory. This section describes the transmission
process. Reception is described in section 2.3.
The data units handled· by the 82586 are frames. A
frame is a sequence of bits that travels on the link. A
frame is divided into fields: address, data, frame check
sequence, etc. The host CPU prepares a sequence of
frames in shared memory and instructs the 82586 to
start transmission. Frames are transmitted by the
82586 one at a time. The chip resolves access and contention on the link using the Carrier Sense Multiple
Access with Collision Detection (CSMAlCD) Link
Management mechanism.

In the End of Carrier method, the 82586 transmits (depending on the configuration) 8, 24, 56, or 120 Preamble bits of alternating ones and zeros followed by a SFD
field (10101011). The end of frame is indicated by the
carrier going inactive immediately after the Frame
Check Sequence field. This frame boundary delineation
method is compatible with IEEE 802.3.
The Bitstuffing method implements the HDLC zero bit
insertion/deletion meChanism. The 82586 transmits
(depending on the configuration) a Preamble of 8, 24,
56 or 120 alternating ones and zeros followed by an
HDLC Flag (01111110). End of frame is indicated by
an HDLC flag. The 82586 performs HDLC zero bit
insertion (insert 0 after five consecutive 1's) on the
fields between flags (exclusive). The chip can be configured to pad the frame with additional flags so that
frame length becomes longer than Slot Time (see section 2.2.2).

This section presents the framing, link management,
and priority mechanisms.

2.2.1 Framing
Framing has three primary functions: to determine the
beginning and end of the frame (frame boundary delint;ation); to determine the frame's source and destination
(addressing); and to perform error detection. Framing
can be summarized in terms of the generalized frame
format shown in Figure 2-3.

Regardless of the Frame Boundary Delineation method, the two fields following the SFD Field are Destination Address and Source Address. The former· is
fetched from memory and the latter is usually inserted
from the internal Individual Address register (unless
configured not to). The address length can be configured to a value from 0 to 6 bytes. Addresses are sent
with the least· significant byte first. The Destination
Address can be one of three types: Individual Address
(least significant bit is zero), Multicast Address (least
significant bit is one), or Broadcast (all ones). See section 2.3.2 for more details on addressing.

PREAMBLE
START FRAME DELIMITER FIELD
DESTINATION ADDRESS
SOURCE ADDRESS
LENGTH FIELD
DATA FIELD
FRAME CHECK SEQUENCE

The Length Field and Data Field are fetched by the
82586 from memory and transmitted after the Source
Address. The Length Field is 2 bytes long. The 82586
itself places no limit on the Data Field length.

END OF FRAME FLAG (OPTIONAL)
PADDING (OPTIONAL)

Figure 2-3. Frame Fields

2-3

LAN COMPONENTS USER'S MANUAL

After waiting the Backoff time, the 82586 attempts to
retransmit the frame, unless the number of retransmissions has e-

.c:::;~
SHARED MEMORY

INITIALIZATION
ROOT

t

1\

11

SYSTEM CONTROL
BLOCK (SCB):
"MAILBOX"

!

Vt
\[

.~

RECEIVE
FRAME
AREA

COMMAND
LIST

230814-17

Figure 2-4. 82586/Host CPU Interaction

2-9

LAN COMPONENTS USER'S MANUAL

INITIALIZATION ROOT

___COM~ LIST~L)

r- r-----,

COMMAND LIST
POINTER
RECEIVE FRAME
. POINTER·

STATISTICS

I

I
I

L

RECEIVE FRAME AREA (RFA)

'--_ _--' (N)

T

T

-.J
230814-18

Figure 2-5. 82586 Shjlred Memory Structure

82586 exchange control and status information. The
SCB is composed of two parts. First, instructions from
the CPU to the 82586. These include: contt:ol of the CU
and RU (START, ABORT, SUSPEND, RESUME), a.
pointer to the list of commands to execute a pointer to
the Receive Frame Area, and a set of interrupt acknowledge bits. Second, information from the 82586 to
the CPU that includes: state of the CU and RU (e.g.
IDLE, ACTIVEIREADY, SUSPENDED, NO RECEIVE RE~OURCES), interrupt bits (command completed, frame received, CU gone not ready, RU gone
not ready), and statistics. See Figure 2-5. Section 2.7
provides a detailed description of the SCB.

The only hardware signals that connect the CPU and
the 82586, are the INTERRUPT and CHANNEL ATTENTION, see Figure 2-4. The Interrupt line is used
by the 82586 to draw the CPU's attention to a change
.in the SCB. The Channel Attention line is used by the.
CPU to draw the 82586's attention. .

o

2-tO

The Command List serves as a program for the CU.
Individual commands are placed in memory units
called a Command Block, or CB. CBs contain command specific parameters and command specific statuses. Specifically, these commands are called Action
Commands (e.g. Transmit, Configure) and are discussed in detail in section 2.8.

LAN COMPONENTS USER'S MANUAL

A specific command, Transmit, causes transmission of
a frame by the 82586. The Command Block includes
Destination Address, Length Field, and a pointer to a
list of linked buffers that hold the frame to be constructed from several buffers scattered in memory. The
Command Unit performs in parallel, without the CPU
intervention, the DMA of each buffer and the prefetching of references to new buffers. The CPU is notified
only after successful transmission or retransmission.

Similar to the 8086, the 82586 can be pin strapped into
either Minimum mode or Maximum mode. Minimum
mode is used in small systems that do not require external bus controller circuitry. The 82586 provides the
minimum bus control information. Maximum mode is
used in systems that use large memory, and have system peripherals.
The maximum Data Transfer Rate on the bus interface
is 4 megabytes per second. Note that this is significantly higher than required by the IEEE 802.3 (which is
1.25 megabytes per second). This leaves much bus
bandwidth for 82586 buffer, status and control overhead and general application processing. Although the
82586 performs command chaining, frame chaining,
and buffer chaining on the fly, it can operate with buses
that transfer data as slow as 2 megabytes per second
without DMA overruns or underruns.

The Receive Frame Area is a list of Free Frame Descriptors (Descriptors not yet used) and list of buffers
prepared by the user. It is conceptually distinct from
the Command List. Because frames arrive without being solicited by the 82586, the 82586 must be prepared
to receive them even if it is engaged in other activities
and to store them in the Free Frame Area. The Receive
Unit fills the buffers upon frame reception and reformats the Free Buffer List into received frame structures. The frame structure is virtually identical to the
format of the frame to be transmitted. The first frame
descriptor is referenced by SCB.

The 82586 shares the system bus with the host CPU,
and possibly other peripherals. Therefore, there is a delay between the time the 82586 requests the bus and
receives it. This delay is referred to as bus latency. Latency time is typically 1 to 2 microseconds but may
reach about ten microseconds in worst case situations.
Note that 10 microseconds is equivalent to 100 data
bits, or 12.5 bytes. DMA overruns or underruns due to
bus latency is significantly reduced by the 82586's individual on-chip transmit and receive FIFOs. Associated
with the FIFOs is a user programmable threshold
mechanism that improves the bus access efficiency by
making the traffic bursty,

Receive buffer chaining (i.e. storing incoming frames in
a linked list of buffers) improves memory utilization
significantly. Without buffer chaining, the user must
allocate consecutive blocks of the maximumJrame size
(1518 bytes in IEEE 802.3) for each frame. Maximum
frame length buffers are inefficient because 75 percent
of the frames on a network are control (request for
status, message acknowledgement, etc.) frames, which
are typically less than 100 bytes. With buffer chaining,
the user can allocate small buffers and the 82586 uses
only as many as needed. See section 1.3.1.

Section 2.10 provides details on all aspects of the Bus
Interface.

In the past, the drawback of buffer chaining was CPU
processing overhead and the time involved in buffer
switching (especially at 10 Mbps). The 82586 overcomes this drawback by performing buffer management
in hardware, completely transparent to the user.

2.5.3 Memory Addressing
The 82586 accesses memory with 24-bit addresses (in
Minimum mode the two most significant bits are used
as RD and WR lines). The memory structure uses two
types of address representation: Physical (Real) and
Segmented.

Section 2.9 provides details on the format of the Received Frame Area and the algorithms associated with
frame reception.

2.5.2 Hardware Bus Interface
The local bus interface has 24 address lines. The low
order 16 lines are multiplexed with data, and address
line number 19 is multiplexed with status. Like other'
Master peripherals, the 82586 provides all control signals required to handle Direct Memory Access. The
bus interface operates at up to 8 MHz.

A Physical Address is a single 24-bit entity that specifies the physical byte address in memory, The representation of this type of address is in three consecutive
bytes in memory, starting at an even location (see Figure 2-6). It is used for referring to all the buffers as well
as to elements of the Initialization Root. When the chip
is configured to operate with a 16-bit bus, the Physical
Address must be even (least significant bit = 0).
A Segmented Address consists of a base and offset.
The base is a 24 bits long real address and the offset is

2-11

LAN COMPONENTS USER'S MANUAL

15

· 1 . . . . . - - 1_

1 __________ _

_- - - - ,

_h

h_m

__

'I

16

23
PHYSICAL ADDRESS

o

15

OFFSET

230814-19

Figure 2-6. Memory Addressing

OFFFFF6H

OFFFFF8H

OFFFFFAH

OFFFFFCH
OFFFFFEH

BUSY

sca OFFSET

ISCP

ISCP+ 2

ISCP+ 4
SCB BASE
ISCP+ 6

230814-20

Figure 2-7. Initialization Root

2-12

LAN COMPONENTS USER'S MANUAL

16 bits long. The base is setup during the initialization
process and remains the same until the chip is reset.
The base must be even in all cases. The 82586 calculates the physical address by adding the base to the
-offset. The representation of the offset is a word starting on an even byte boundary in memory, (see Figure
2-6). Segmented Addresses are used for referring to
most parts of the memory structure. It must be even in
all cases.

.INTERMEDIATE SYSTEM CONFIGURATION
POINTER (ISCP)

The ISCP is common to the 82586 and all other master
peripherals referring to the same SCPo At the same
time however, information contained in ISCP is specific
to each master peripheral, and the structure contains a
status element. Consequently, ISCP must be located in
RAM, and not in ROM with SCPo This distinction is
the reason for separating SCP and ISCP. The ISCP
includes the following fields:

2.6 INITIALIZING THE 82586

BUSY (8 bits): when set to OlH, indicates that the
82586 is in the initialization process.
The 82586 clears this byte immediately after reading the information contained in ISCP.

After the clocks (System, Transmit and Receive) applied to the 82586 have stabilized and a RESET is issued, the 82586 performs an initialization procedure
that prepares it for normal operation. This section specifies the memory structure involved in the initialization,
how the user must prepare it, and how the chip behaves
during initialization.

SCB-OFFSET: the address offset of the SCB (within
the segment defined by the SCBBASE).

2.6.1 Initialization Root Format

SCB-BASE:

Initialization involves the System Configuration Pointer (SCP) and the Intermediate System Configuration
Pointer (ISCP). Their formats are described in detail
below, and they are shown in Figure 2-7.

a 24-bit value giving the starting address of the 64-kilobyte segment containing SCB and all other control
structures dealing with the 82586.

2.6.2 Initialization Process
SYSTEM CONFIGURATION POINTER (SCP)

The initialization process establishes communication
between" the CPU and the 82586. Without it, no interaction takes place.
-

The SCP is located in the ten bytes from OFFFFF6H to
OFFFFFFH, the highest bytes in the address space.
Note that this is a fixed address, the only one in the
system.

Prior to starting the initialization process, the CPU
must setup the following fields in SCP and ISCP:
• BUS - memory bus width specification.
• IS<;P ADDRESS - physical address of ISCP.
• BUSY - this field in ISCP must be OlH to indicate
that the CPU is ready for initialization. Subsequent
clearing of the field by the 82586, indicates initialization completion.
• SCB BASE - base address of the entire memory
structure.
• SCB OFFSET - offset (from SCB BASE) of SCB.
After completing initialization, all 82586 control is
via SCB.

Only two items of information are present in the SCP,
the system bus width and a pointer to ISCP, the next
structure. ISCP is an arbitrary location in the address
space. The SCP includes the following fields:
OFFFFF6H:
BUS (Bit 0) - This bit specifies the width of the system
bus. It takes the following values:
o 16-bit bus
I 8-bit bus
ISCP ADDRESS: This 24-bit value is the ISCP physical address.

The CPU must reset the 82586. After power-up, this
must be done with a hardware RESET. Subsequently, a
software RESET (specific to the 82586) may be used.
RESET causes all major internal flags to be set to their
inactive states. In particular, CU and RU are set to
IDLE state and configuration parameters are set to
their default values (see section 2.7.5).

The 82586 is indifferent to the remaining SCP contents.
This does not mean that these areas have no function,
they may be meaningful with respect to other peripherals which refer to SCPo Because the SCP and ISCP are
sampled by the 82586 only during initialization, they
may be used at any other time by other peripherals.

2-13

LAN COMPONENTS USER'S MANUAL

8) Raises the INTERRUPT Hardware Signal.

Initialization is triggered by the Channel Attention
(CA) signal from the CPU. Note that initialization can
only occur by issuing the sequence: RESET-CA. After
CA, the 82586 performs the following sequence:-

The chip is now ready to be controlled by the host CPU
via SCB, as described in the next section.

- 1) Re~ds the first word from location OFFFFF6H. The
least significant bit determines bus width of all subsequent memory accesses. Before reading this word,
the system bus ,width is assumed to be 8 bits.
2) Reads the ISCP ADDRESS from
OFFFFFCH and the following word.

2.7 CONTROLLING THE 82586
This section discusses how the CPU controls operation
of the 82586's Command Unit (CU) and Receive Unit
(RU). Operation of the CU and RU themselves, namely
how the 82586 executes Action Commands and receives frames, is discussed in subsequent sections. This
section provides complete explanations 'of the following
functions:
• Starting and Completing Control Commands

location

3) Reads SCB OFFSET from the word following the
one determined by ISCP ADDRESS. SCB OFFSET
is saved for subsequent references to SCB.

,

4) Reads SCB BASE field from the next two words.

• CU Control
• RU Control

5) Clears the BUSY byte. This is done by reading the
word in location ISCP, clearing the least significant
byte, and writing back to the word (with the cleared
'
byte).

• RESET
• Statistics Registers

2.7.1 System Control Block (SCB)
Format

6) The SCB BASE (read in Step 4) is saved internally
to serve as a base for all subsequent references to the
memory structure (excluding data buffers).

The System Control Block is the communication mailbox betwe,en the 82586 and the host CPU. The SCB
format is shown in Figure 2-8.

7) Writes the STATUS word of SCB with CX and
CNA bits set, all remaining fields are cleared (see
section 2.7.1).

o

15
STAT

0

cus

0

RUS

ACK

Iffi

cuc

R
E
S

RUC

o

I I I
0

0

0

V/;J//;J///~

CBLOFFSET

SCB
(STATUS)
SCB+2
(COMMAND)
SCB+4

RFAOFFSET

SCB+6

CRCERRS

SCB+8

ALNERRS

SCB+ 10

RSCERRS

SCB+ 12

OVRNERRS

SCB+ 14

Figure 2·8. System Control Block (SCB) Format

2-14

LAN COMPONENTS USER'S MANUAL

(Bit 14) - Acknowledges that the RU
received a frame.

The host CPU issues Control Commands to the 82586
via the SCB. These commands may appear at any time
during routine operation, as determined by the host
CPU. The CPU informs the 82586 that a control command is ready by issuing a CA signal.

ACK-FR

The SCB is also used by the 82586 to return status
information to the host CPU. After inserting the required status bits into SCB, the 82586 issues an Interrupt to the CPU.

ACK-RNR (Bit 12) - Acknowledges that the Receive Unit left the READY
state.

ACK-CNA (Bit 13) - Acknowledges that the Command Unit left the ACTIVE
state.

CUC

(Bits 8-10)

- (3 bits) this field contains the
command to the Command
Unit. Valid values are:

o

- NOP (doesn't affect current
state of the unit).
- Start execution of the first
command on the Command
List (CBL). If a command is
in execution, then complete it
before starting the new CBL.
The beginning of the CBL is
in CBL OFFSET.
- Resume the operation of the
Command Unit by executing
the next command. This operation assumes that the
Command Unit has been previously suspended.
- Suspend execution of commands on the CBL after current command is complete.

The format is as follows:
STATUS WORD:

Indicates status of the 82586 to the CPU. This word is
modified only by the 82586. Defined bits are:
CX

(Bit 15)

- The CU finished executing an
Action Command with its 'I'
(Interrupt) bit set.

FR

(Bit 14)

- The RU finished receiving a
frame.

CNA

(Bit 13)

- The CU left the ACTIVE
state.

RNR

(Bit 12)

CUS

(Bits 8-10)

- The RU left the READY
state.
- (3 bits) this field contains the
status of the Command Unit.

2

3

Valid values are:

RUS

(Bits 4-6)

o

- IDLE

I

- SUSPENDED

2

- ACTIVE
RUC

3-7 - Not used
- (3 bits) this field contains the
status of the Receive Unit.
Valid values are:
0
- IDLE
I
- SUSPENDED
2
- NO RESOURCES
3
- Not used
4
-READY
5-7 - Not used

4

- Abort current command immediately.

5-7

- Reserved, illegal for use.

(Bits 4-6)

- (3 bits) This field contains the
command to the receive unit.
Valid values are:
- NOP (does not alter current
state of unit).
- Start reception of frames. If a
frame is being received, then
complete reception before
starting. The beginning of the
RF A is contained in the RF A
OFFSET.

o

2

The remaining bits of the status word are always set to
zero by the 82586.

3

COMMAND WORD:

Provides the communication mechanism from the CPU
to the 82586. This word is set by the CPU and cleared
by the 82586. Defined bits are:
ACK-CX

(Bit IS) - Acknowledges that the CU
completed an Action Command.

4

- Abort receiver operation immediately.

5-7

- Reserved, illegal for use.
- Reset chip (logically the same
as hardware RESET).

RESET (Bit 7)
2-15

- Resume frame receiving (only
when in the SUSPEND
state.)
- Suspend frame receiving. If a
frame is being received, then
complete its reception before
suspending.

LAN COMPONENTS USER'S MANUAL

3) ,If the RESET bit is set, it performs the RESET sequence, as described ,in section 2.7.5.

CBL-OFFSET: Gives tJIe 16-bit offset address of the
first command (Action Command) in
the Command List to be executed following CU~START. Thus, the 82586
will read this word only if the CUC
field contains a CU-START Control
Command.

4) Clears the internal INTERRUPT"IS ('In-Service')
flag for each acknowledged interrupt bit
5) If the RUC field is different from zero,an internal
request to theRU to perform a RU command acceptance sequence is issued (see section 2.7.4).

RFA-OFFSET: Gives the 16-bit offset address of the
first Receive Frame. Descriptor in' the
Receive, Frame Area, to be accessed
following a RU-START Control command. Thus, the 82586 will read this
word only if the RUC field contains a
RU-START Control Command.
CRCERRS:

ALNERRS:

RSCERRS:

6) If the CUC field is different from zero, the acceptance sequence for a CU command is performed immediately (see section 2.7.3).
After both CU and R U complete the acceptance sequence, the 82586 performs the Completion of Control
Command, sequence:
'

CRC, Errors' - contains the number of
properly aligned frames received with
a CRC error.

I) If there is any internal interrupt request then it sets
the respective INTERRUPT-IS flag.

Alignment Errors - contains the number of misaligned frames received with
a'CRC error.

2) Update SCB STATUS word, according to internal
CU status, RU status and Interrupt requests.
3) If any INTERRUPT-IS is set then the 82586 sets the
hardware Interrupt signal.

Resource Errors - records the number
, of correct incoming frames discarded
due to lack of memory resources (buffer space or Receive Frame Descriptors).

4) Clears SCB COMMAND word.

2.7.3 Command Unit (CU) Control

OVRNERRS: ,Overrun Errors - counts the number of
received frame sequences lost because
the memory bus was not available to
the 82586 in time to transfer them.

The Command Unit is the logical unit that executes
Action Commands from a list of commands very similar to a CPU program. A Command Block (CB) is associated with each Action Command.

2.7.2 Starting and Completing Control
Commands

This section describes how the CPU controls Action
Command execution, 'namely, how it starts, stops, suspends or resumes the CU. Execution of the Action
Commands themselves, is the subject of the next section.

The' CPU issues Control Commands by writing in the
SCB COMMAND field and issuing Channel Attention
(CA). Acceptance of a Control Command is indicated
by the 82586 clearing the SCB COMMAND field.
Therefore, the CPU must wait for this word to be
cleared before the next Control Command can be issued.

The CU can be modeled as a logical machine that takes,
at any given time, one of the following states:
• IDLE - the CU is not exeCuting a command and is
not associated with a CB on the list. This is the
initial state.
• SUSPENDED - the CU is not executing a command but (different from IDLE) is associated with a
CB on the list.
'

The 82586 does ,not n~cessarily accept the Control
Command immediately after CA is issued; it may be
engaged in higher priority tasks. For example, prefetching new buffers, handling buffer switches, or finishing
frame'reception. When the 82586 becomes available it
performs the Starting of Control Command sequence:

• ACTIVE - the CU is currently executing an Action
Command, and points to its CB:'
"

I) Clears hardware Interrupt signal.
2) Reads the SCB COMMAND word, and analyzes its
fields.

2-16

LAN COMPONENTS USER'S MANUAL

The CPU may affect the CU operation in· two ways:
issuing a CU control Command or setting bits in the
COMMAND word of the Action Command. In general, the CPU can cause the CU to do the following:
• Start executing a list of Action Commands.
• Suspend execution after completing the current Action Command.
• Resume execution if the CU is inthe SUSPENDED
state,

2) If the CU is not in the ACTIVE state, it goes to the
ACTIVE state and requests the beginning of the
next CB.
3) If the CU is in the ACTIVE state, then it does nothing at Acceptance time. Beginning of the next CB
(i.e. the new one) starts after completion time of the
current CB.
CU-SUSPEND

• Abort execution and return to the IDLE state.
• Stop execution after completing a particular Action
Command. This will be the last CB in the list.
• Suspend execution after completing a particular Action Command.
• Have the 82586 issue Interrupts after completing
particular Action Commands.

Suspends operation of the CU after completing the current CB. The 82586 performs the following sequence:
1) If the CU is in the ACTIVE state, it sets the internal
CU-SUSPEND-REQUEST flag. This flag causes
CU to enter the SUSPENDED state at command
completion time.

There are three points in time relevant to the execution
of Action Commands:
• Acceptance time (of a control command)-the time
following a Channel Attention issued by the CPU,
the CU reads the Control Command and takes initial action.
• Beginning of Execution-the time the CU starts executing an Action Command. This may be following
a Control Command or in continuing the list of Action Commands. The details are presented in section
2.8.1.
• Completion of Execution-the time the CU completes executing an Action Command. This is the
decision time for the CU on how to proceed. The
details are presented in section 2.8.1.

2) If the CU is not in the ACTIVE state, it ignores the
CU-SUSPEND command .
CU-RESUME

Resumes CU operation. The 82586 performs the following:
1) If the CU is in the SUSPEND state, it goes to the
ACTIVE state and requests the beginning of the
next CB.
2) If the CU is in the ACTIVE state, it clears internal
CU-SUSPEND-REQUEST to prevent suspension at
command completion time.
3) If the CU is in the IDLE state, it ignores the CURESUME command.

The CU uses 3 internal flags to remember requests
from acceptance time to be acted upon at completion of
execution: CU-START-REQUEST, CU-SUSPENDREQUEST and CU-ABORT-REQUEST.

CU-ABORT

At acceptance Time, after the 82586 has finished higher
priority tasks and a CA is detected, it reads the SCB
command word and analyzes its fields. The higher priority tasks are: receive end of frame processing, receive
or transmit buffer prefetching, retransmission due to
collisions, completion of Action Commands. The CUC
field is one of the following: CU-START, CU-SUSPEND, CU-RESUME or CU-ABORT.

Causes the CU to stop all activity immediately and go
to the IDLE State. The CU performs the following:
1) If the CU is not in the ACTIVE state, it goes to the
IDLE state.
2) If the CU is in the ACTIVE state, it sets the internal
CU-ABORT-REQUEST flag. This flag causes the
CU to go to the IDLE state at command completion
time.

CU-START

The CU ABORT control command causes the immediate termination (at acceptance time) of the transmission
process. The effect on specific Action Commands (see
section 2.8) is as follows:
• NOP, TDR, DUMP and DIAGNOSE commands
are not stopped. Following execution, the CU
switches to its IDLE state.

Starts execution of the first Action Command in the
list. The CU performs the following sequence:
1) Reads CBL OFFSET and saves it as a pointer to the
next CB to be executed.

2-17

LAN COMPONENTS USER'S MANUAL

• IA setup, MC setup, CONFIGURE commands are
always stopped. A command aborted bit is set in the
CB status field. The CPU MUST execute these
commands again since the 82586 may not be properly programmed to continue its operation.
• There is an attempt to abort a TRANSMIT. The
DMA process is stopped. In certain timings, the
Abort attempt may not be successful. The 82586 internally tests for this situation and flags CMD
ABORTED status only if the TRANSMIT is
known to have failed.
.

. SUSPENDING THE CU

The START, SUSPEND, RESUME and ABORT
commands can be given through the SCB command
fields as described above. The Command Block offset
.pointer in the SCB points to the first executable Action
Command (to be discussed in section 2.8). It is sufficient to state here that these Action Commands have a
field for EL and S Bits (see section 2.8.1). The EL, End
of List, bit indicates that the current Action Command
is the last on the Command List. The S Bit indicates
that the user desires the CU to enter into Suspended
state after executing the current command. Tables 2-1
and 2-2 illustrate the state transitions for various conditions.

NOTES ON ABORTED TRANSMISSION:

1)'The CU attempts to stop as soon as possible by stop'
ping DMA and forcing a FIFO underrun.

Thus, there are two mechanisms to suspend the CU:
one through the Suspend Command in SCB, and the
other through the S bit in the Action Command Block.
The Suspend Command in SCB will suspend the CU
after completing the execution of the current command
on the Command List, without knowing exactly which
command the 82586 was executing before execution.
Suspension of CU through Action Command Block
will result in suspension after a specific command is
executed. In both cases, the CU can be activated by
issuing a Resume command.

2) Aborted transmit frames may result in small frames
on the Serial Link. The 82586 sends to the Serial
, Link, the partial frame and appends to it four bytes
of 'All Ones' (jam pattern).
3) Apart from aborted transmit frames and collided
frames, the 82586 appends the jam pattern, also in
the following cases:
• Underrun on transmit buffers.
• Lost Carrier Sense, if programmed to .stop transmission when Carrier Sense is lost.
See Figure 2-9.

Table 2-1. CU ControlCommands: Actions at Acceptance Time
Present
State
Idle
Suspended
Active

Start
Next
State
Active
Active
Active

Resume

Action

Next
State

Action

Set UpCB
SetUpCB
None

Idle
Active
Active

None
SetUpCB
None

Suspend
Next
State

Abort
Next
State

Action

Idle
None
Suspended . None
Request
Active
Suspend

Idle
Idle
Idle

Action
None
None
Abort
DMAICNA
Interrupt

Table 2-2. CU Activities Performed at End of Execution
ELBit

SBit

Request

Next State

0
0

0
0

None
Suspend

Active
Suspended

Set UpCB
CNA Interrupt

0
0

1
1

None
Suspend

Suspended
.Suspended

CNA Interrupt
CNA Interrupt

1
1

0
0

None
Suspend

Idle
Idle

CNA, CX Interrupts
CNA, CX Interrupts

1
1

1
1

None
Suspend

Idle
Idle

CNA, CX Interrupts
CNA, CX Interrupts

Action

NOTES:
1) After a CB with 'I' bit set is completed, CX interrupt is generated.
2) Since the transition ACTIVE to ACTIVE STATE via the START Command is smoothly performed, no interrupt, related to
state transition, is generated and no action is required at the end of Action Command Execution.

2-18

LAN COMPONENTS USER'S MANUAL

NO

CLEAR SCB
COMMAND

NO

ABORT

YES

230814-22

Figure 2-9. CU Abort Flowchart

2-19

LAN COMPONENTS USER'S MANUAL

There are two points in time relevant to frame reception:
• Acceptance time - the time after a Channel Attention is issued by the CPU, the RU reads the Control
Command and takes initial action.
• Completion of Reception - the time the RU ends
receiving or discarding an incoming frame. This is a
decision time for the RU on how to proceed and is
discussed in detail in section 2.9.2.

2.7.4 Receive Unit (RU) Control
The Receive Unit is the logical unit that receives frames
and stores them in memory. The RU uses free (i.e. unused) buffers and descriptors prepared by the CPU.
The details on RU frame reception are presented in
section 2.9.
This section describes how the CPU controls frame reception, namely, how it starts, stops, suspends, or resumes the RD. Reception may also stop due to No Resources.

The RU uses two internal flags to remember requests
from acceptance time to be acted upon at completion of
reception time: RU-START-REQUEST and RU-SUSPEND-REQUEST.

The RU is modeled as a logical machine that takes, at
any given time, one of the following states:
• IDLE - The RU has no memory resources and is
discarding incoming frames. This is the initial RU
state.

At acceptance time, after CU passes the Control Command to the RU and finishes accepting its own Control
Command, the RU starts analyzing its command. The
SCB's RUC field may take one of the following values:
RU-START, RU-SUSPEND, RU-RESUME, or RUABORT.

• NO-RESOURCES - The RU has no memory resources and is discarding incoming frames. This
state differs from the IDLE state in that RU accumulates statistics on the number of frames it had to
discard.

RU-START

• SUSPENDED - The RU has free memory resources
to store incoming frames but discards them anyway.

The RU is made ready to receive frames. At Acceptance time, the RU mayor may not be actively receiving
a frame.

• READY - The RU has free memory resources and
is ready to store incoming frames.
NOTE:
Frames arrive at the 82586 independent of the state of
the RD. The situation that a frame is arriving is referred to as Actively Receiving, even when RU is Not
Ready and the frame is being discarded.

First case - the RU performs the following sequence if
it is actively receiving:

The CPU may affect RU operation in three ways: issuing an RU Control Command, setting bits in the Frame
Descriptor COMMAND word of the frame currently
being received, or setting the EL (End of List) Bit of the
Receive Buffer Descriptor, RBD, of the buffer currently being filled. In general, the CPU may cause the RU
to do the following:

2) Reads the RFA OFFSET word from SCB and saves

1) Clears the internal RU-START-REQUEST and

RU-SUSPEND-REQUEST flag.
it internally as the pointer to th.e next FD.
3) Sets RU-START-REQUEST, thus when the current

frame has been received or discarded, the RU goes to
the READY state and sets up the next FD.
Second case - The RU performs the following sequence
if it is not actively receiving:

• Start frame reception.
• Suspend frame reception (start discarding) after current frame reception is complete.

1) Clears internal RU-START-REQUEST and RU-

SUSPEND-REQUEST flags.

• Resume reception if the RU is in SUSPENDED
state.

2) Reads RFA OFFSET word from SCB and saves it

• Abort reception at once and return to IDLE state.
• Stop reception after a particular FD is filled (frame
received). This FD is referred to as the last FD on
the list.

internally as the pointer to the next FD.
3) If the RU is not in the READY state, or the RU is

in the READY state and assures that DMA did not
transfer any data to the current FD, it does the following: it stops discarding, goes to the READY
state, gives up buffers that have been prefetched (if
any), and sets up a new FD. Setting up a new FD
uses the pointer to the next FD to prepare reception
of the next frame (see section 2.9).

• Suspend reception after· particular FD is filled
(frame received).
• Stop reception after a particular RBD is filled. This
is the last RBD in the list.
NOTE:
The RU issues an Interrupt after every received frame.
2-20

LAN COMPONENTS USER'S MANUAL

4) If the RU is in the READY state and DMA started
transferring data to memory before the RU had the
opportunity to stop it, the following occurs: the RU
goes to the NO-RESOURCES state (without issuing
a RNR Interrupt) and sets the internal RU-STARTREQUEST. Next, (in the particular case where RU
does not manage to stop DMA in time) one frame is
discarded and the user is notified by temporarily being in the NO-RESOURCES state.

RU-SUSPEND

Suspends RU operation after reception of current frame
is complete, or reception of first frame to be received is
complete. The RU performs the following:
1) If the RU is in the READY state, sets internal RUSUSPEND request.
2) If the RU is not in the READY state, ignores the
command.

The CPU must ensure that the 82586 is properly configured before starting the RU. This rule specifically
applies to lA-SETUP, MC-SETUP, CONFIGURE
Action Commands. Failure to perform CONFIGURE
Action Command before stating the RU may result in
unpredictable behavior of the receive process.

RU-RESUME

Resumes frame reception. The RU performs the following sequence:

Failure to perform lA-SETUP before a RU START
may result in a coincidental address match on a received frame. See also section 3.5 for other rules for
starting the RU.

1) Clears RU-SUSPEND-REQUEST.
2) If the RU is in the SUSPENDED state, and not
actively discarding a frame, it goes to the READY
state and sets up a new FD (see section 2.9).

Table 2-3. RU Control Commands - Actions at Acceptable Time
Resume

Start
Present
State
Idle

Next
State
Ready

RU
Ready
No
Resources
Not
Actively
Receiving Suspended Ready

Action
Set Up
FD
SetUp
FD
SetUp
FD
Set Up
FD

Next
State

Action

Suspend
Next
State

Abort

Next
Action
State

Action

None

Idle

None

None
No
Resources

No
None
Resources

Idle

None

Ready

Suspended None

Idle

None

Idle

None

Set Up
FD
None

Idle

Ready

Request Idle
Suspend

Start
Discarding
RNR
Interrupt

Idle

None

Idle

None

No
None
Idle
RU
Resources
Actively
Receiving Suspended Suspended Request Suspended Request Suspended None
Idle
Start
Start
Ready
Ready
Request Ready
Ready
Request Idle
None
Start
Suspend

None

Ready

Idle

Ready

Idle

Request Idle
None
Start
No
No
Request No
None
Resources Resources Start
Resources

2-21

None
Abort
DMA Start
Discarding
RNR
Interrupt

LAN COMPONENTS USER'S MANUAL

Table 2-4. RU Activities Performed at End of Execution
ELBit

S Bit

Request

0
0
0

0
0
0

None
Suspend
Start

Ready
Suspended
Ready

Set Up FD
RNR Interrupt
Set Up FD

0
0
0

1
1
1

None
Suspend
Start

Suspended
Suspended
Suspended

RNR interrupt
RNR Interrupt
RNR Interrupt

1
1
1

0
0
0

None
Suspend
Start

No Resources
No Resources
Ready

RNR Interrupt
RNR Interrupt
Set Up FD

1
1
1

1
1
1

None
Suspend
Start

No Resources
No Resources
Ready

RNR Interrupt
RNR Interrupt
Set Up FD

Next State

Action

NOTE:
After a frame is received, FR interrupt is generated,

3) If the RU is in the SUSPENDED state and actively
discarding a frame, it sets RU-START-REQUEST.

The hardware RESET causes all major hardware control flip flops to be cleared. The CU and RU also clear
their internal flags, they include:

4) If the RU is not in the SUSPENDED state, it ignores the command.

END-OF-LAST-BUFFER = 0
ID-FULL = 0

RU-ABORT

RU-state = IDLE

RU stops reception immediately and goes to the IDLE
state. RU performs the following:

CU-SUSPEND-REQUEST

=

CU-ABORT-REQUEST

0

CU-state

I) If the RU is in the READY state, it requests an
RNR Interrupt.

=

IDLE
=

0

CNA-REQUEST = 0
CX-REQUEST = 0

2) Stops all DMA activity and starts discarding incoming data.

RU-SUSPEND-REQUEST

=

RU-START-REQUEST

0

=

0

3) Changes the RU to the IDLE state.

RNR-REQUEST = 0
PR-REQUEST = 0

2.7.5 Reset

ADDRESS-LENGTH

The 82586 has both a software and hardware RESET.
After power up, a hardware.RESET is required by the
82586. A Channel Attention following this reset will
result in the 82586 accessing the System Control Pointer located at OFFFFF6H. The first access is made on an
8-bit data boundary. Depending on the contents of location OFFFFF6H, the subsequent access will be made
on 8 or 16-bit data boundary.

NOTE:
The System and Transmit· clocks must be stable at
their correct levels and timings before hardware RESET can be issued.

=

6

The CD. performs the following upon recognition of a
software RESET:
I) Terminates DMA activity.

A software RESET is available on the 82586 through
bit 7 of the Control Command word in the System Control Block. It may be used after the 82586 has been
initialized and it has the ISCP and SCP addresses. The
software RESET is intended to operate selectively on a
particular 82586.

2) Writes all zeros to SCB COMMAND word.
3) Triggers a hardware RESET.

2-22

LAN COMPONENTS USER'S MANUAL

NOTE:
A Channel Attention from the CPU must be delayed
for at least 8 clocks after the SCB COMMAND word
(with a RESET) is cleared. Several internal flip flops,
including the internal Channel Attention flip flop, are
cleared 8 clocks after the SCB COMMAND word is
cleared therefore, a premature Channel Attention may
not get recognized.

CRC ERROR COUNTER:

Contains the number of properly aligned frames received with a CRC error. It is incremented by the
82586 for every frame with a CRC error that was targeted for this specific station and was longer than the
Minimum Frame Length.
ALIGNMENT ERROR COUNTER:

2.7.6 Error Statistics Registers

Counts the number of misaligned frames received with
a CRC error. It is incremented by the 82586 for every
misaligned frame with a CRC error that was targeted
for this specific station and was longer than the Minimum Frame Length.

The last four words in the SCB are statistics registers
that accumulate tallies on: CRC errors, Alignment errors, number of frames lost due to No Resources, number of frames lost due to DMA overruns.
The 82586 increments the registers at Completion of
Reception time if the appropriate event happens and
the register has not reached OFFFFH. The registers are
'sticky,' i.e. they do not wrap around from OFFFFH to
zero. The registers can be cleared (or set to any value)
only by the host CPU.

NO RESOURCES ERROR COUNTER:

Records the number of correctly received frames discarded due to the lack of memory resources (buffer
space or received frame descriptors). It is incremented
by the 82586 for every frame discarded due to lack of
memory resources that was targeted for this specific
station and did not experience any error.

The CPU cannot update the register while the 82586 is
incrementing it (restoring the old value plus one) because the 82586 performs the read counter/increment!
write counter operation without relinquishing the bus.
This is done to ensure that no logical contention exists
between the 82586 and the CPU.

OVERRUN ERROR COUNTER:

Counts the number of received frame sequences lost
because the memory bus was not avaialble in time to
transfer them. Note that more than one frame may get
lost due to overrun, and in this case the counter is incremented only once.

In a dual port memory configuration, the CPU should
check the state of the counter immediately after updating it. This practice checks for the case where the 82586
placed into the counter the incremented 'old counter'
value after the CPU has cleared the counter. Because
the 82586 does not write to the counter when OFFFFH
is reached, the CPU may safely reset the counter without this check.

2.7.7 SeB Status Update
The 82586 updates the SCB status word in the following events:

Incrementing the registers does not depend on the state
of the Receive Unit. The CRC, Alignment and overrun
error counters are incremented for each frame that experiences the specific error, was targeted for this specific station, and was longer than the Minimum Frame
Length configuration parameter. The No Resources
counter is incremented when a frame targeted to this
station, has no error, and is lost or partially lost because
there was no room in the memory structure.

1) At the end of the initialization procedure, the 82586
writes SCB status denoting CU IDLE, RU IDLE,
CX interrupt and CNA interrupt.
2) When a control command is accepted, the 82586 updates the SCB status and clears the SCB command
word to denote 'acceptance completed.'
3) After execution of an Action Command. However,
the CX bit setting is directly connected to the I bit.

The counters get incremented during External Loop
Back operation, as well as in normal Transmit and Receive operation.

4) After receiving a frame.

2-23

LAN COMPONENTS USER'S MANUAL

2.8 ACTION COMMANDS

MULTICAST ADDRESS SETUP:

The 82586 executes a 'progran:t' that is made up of Action Commands in the Command List, CBL. As shown
in Figure 2-10, each command contains the command
field, status and control fields, link to the next Action
Command in the CBL, and any command-specific parameters. This command format is called the Command Block.

This command allows the programmer to setup one or
more multicast addresses into the 82586. The multicast
addresses to be setup are located in the parameter field
of the command.
TRANSMIT:

One Transmit command is used to send a single frame.
If more than one frame is to be sent, the host CPU can
link multiple Transmit commands together. The destination address, Length field and pointer to buffers containing the data field are contained in the parameter
field of the Transmit command CAL-LOC = 0).

The 82586 has a repertoire of 8 commands:
NOP

Transmit

Individual Address Setup

TDR

Configure

Diagnose

Multicast Address Setup

Dump

TOR:

This command performs the Time Domain Reflectometry test on the coaxial cable. The TDR command is
used to detect and locate cable faults caused by either
short or open circuits on the coaxial cable.

NOP:

This command results in no action by the 82586 other
than the normal command processing, such as fetching
the command and decoding the command field.

DIAGNOSE:

The Diagnose command puts the 82586 through a selftest procedure and reports on the success or failure of
the internal test.

INDIVIDUAL ADDRESS SETUP:

This command is used to load the 82586's unique address. The unique address is contained in the parameter
field of the command.

DUMP:

This command. causes the 82586 to dump its internal
registers il1to memory. The registers included are those
loaded by the Configure and Address Set-Up commands, plus status and other internal working registers.

CONFIGURE:

The Configure command is used to load the 82586 with
its operating parameters. Upon reset, the 82586 initializes to the IEEE 802.3 based parameters. If the user
wishes to use any other values, the Configure command
is used.

GENERAL FORMAT
15
C

COMMAND SPECIFIC

B

o

r---+---+---Tr"~,,rr~rr'-r7'-~-r"~~rT'-r7'-~-rr---~--~--~(STATUS)

EL

CMD

S

r-__ __ __
~

~

2

-L~~~~~~~~~~~~~~~~~~~~~~__~____L-~(COMMAND)

LINK OFFSET
COMMAND SPECIFIC
11111111111111111111111111111111111111111111111111 6
230814-23

Figure 2-10. General Action Command

2-24

LAN COMPONENTS USER'S MANUAL

Table 2·5. 82586 Action CO.mmand Summary

2.8.1 General Action Command
The format common to all Action Commands and the
algorithms for beginning and completing the execution
(also common to all the commands) is described below.

• NOP, Code = 0
Parameters: None
Action

: None

NOTE:
System and Transmit Clocks must be applied to the
82586 before Action Commands can be executed.

• lA-SETUP, Code =
Parameters: Individual Address
Action
: Setup Individual Address

GENERAL FORMAT

The general format of the Command Block (CB) includes the following fields:
STATUS word (written by the 82586):
C
(Bit 15)
- is always set at the completion of execution.
(Bit 14)
B
- is always set at the beginning
of execution, and reset at
completion of execution concurrently with C bit being set.

• CONFIGURE, Code = 2
Parameters: Byte count and configuration
values list
Action
: Configure the 82586
• MC-SETUP, Code = 3
Parameters: Byte count and Multicast Address list
Action
: Setup Multicast HASH table

NOTE:
The 82586 does not read the B or C bits. If the SCB
pointer points to a CB andC = 1, the 82586 will still
execute the command.

• TRANSMIT, Code = 4
Parameters: Destination Address, Length
Field, linked buffer list holding
the Data Field
Action
: Transmit frame, and in case of
collisions, retransmit

COMMAND word:
EL
(Bit 15)

S

• TDR, Code = 5
Parameters: None
Action
: Perform Time Domain Reflectometry test and return results

(Bit 14)

(Bit 13)

CMD
• DUMP, Code = 6
Parameters: Address of memory location to
write results
Action
: Dump set of internal registers
to memory

(Bits 0-2)

- Indicates that this is the last
Command Block in the command list.
Indicates that the CU should
suspend after completion of
execution of this command.
Indicates that the 82586
should issue an interrupt after
completion of executing this
command.
- Indicates the specific command.

LINK OFFSET: Address of the next command block
in the list.
BEGINNING OF EXECUTION

• DIAGNOSE, Code = 7
Parameters: None
Action
: Perform internal test procedure
and returns results

An Action Command may be started by either the CUSTART or CU-RESUME Control Command, or may
follow a previous Action Command. However, the actual command start may be delayed by RU activity.
The following sequence is performed by the CU at the
beginning of execution of each Action Command:
1) Writes a word whose B bit is set and the remainder
of the field cleared to the STATUS word of the next
CB. The content of the STATUS word is specified
for each Action Command in the description that
follows.
2-25

LAN COMPONENTS USER'S MANUAL

2) The next CB becomes the current CB.

6) Sets hardware Interrupt signal if any INTERRUPT-IS flag is set. The detailed description of
commands is given below.

3) Reads the COMMAND word of the current CB
and saves the following fields for later use: EL, I, S
and CMD.

2.8.2 NOP
4) Reads the LINK OFFSET of the current CB and
makes it the next CB.

This command results in no action by the 82586, except
as performed in normal command processing (section
2.8.1). It is present to aid in CBL manipulation.

5) Performs specific actions according to the Action
Command specified in the CMD field.

NOP COMMAND FORMAT
COMPLETION OF EXECUTION

NOP command includes the following fields:

Command completion time is asynchronous to the beginning of the command. It is determined by the command type, RU activity, CU Control Commands, etc.
The CU is always in the ACTIVE state at this time.
The decision on how to proceed, depends on the following flags: CU-SUSPEND-REQUEST, CU-ABORTREQUEST EL, I, S.

STATUS word (written by the 82586):
C
(Bit 15)
- Command completed (see
section 2.8.1)
B
(Bit 14)
- Busy executing command
OK
(Bit 13)
- Error free compl~tion
COMMAND word:
EL
(Bit 15)
S
(Bit 14)
I
(Bit 13)
CMD (Bits 0-2)

The following sequence is performed by the CU at completion of execution of an Action Command:
1) Writes command specific status to the STATUS
word of the current CB.
2) If I bit is set, sets request for the CX Interrupt.

- End of command list
- Suspend after completion
- Interrupt after completion
-NOP = 0

LINK OFFSET: Address of next Command Block

3) If EL or CU-ABORT-REQUEST is set, the CU becomes IDLE and generates request for CNA interrupt. If Sor CU-SUSPEND-REQUEST is set,. CU
becomes SUSPENDED. Otherwise, requests beginning of next Action Command.

DETAILED OPERATION OF NOP COMMAND

CU performs the following sequence:
1) Starts Action Command (see section 2.8.1).

4) Sets appropriate INTERRUPT-IS flags and clears
all Interrupt request flags.

2) Prepares STATUS ~ord with C= 1, B=O, OK= 1.

5) Updates STATUS word in SCB.

3) Completes Action Command (see section 2.8.1).

o

15
C

B

EL

S

OK
CMD=O

2

~__L-~~~~~~~~~~~~~~~~~~~. .~~~__~__~__~(COMMAND)
~

__________________________Ll_N_K_OF_F_S_ET____________________________~4
230814-24

Figure 2-11. The NOP Command Block

2-26

LAN COMPONENTS USER'S MANUAL

2.8.3 lA-Setup

DETAILED OPERATION OF THE lA-SETUP
COMMAND

This command loads the 82586 with the Individual Address. This address is used by the 82586 for recognition
of Destination Address during reception and insertion
of Source Address during transmission.

The Individual Address is transferred by TX-DMA via
TX-FIFO to Transmit-Byte-Machine. See section 2.13.
The CU performs the following sequence:
1) Starts Action Command.
2) Writes the lA-SETUP command byte to TX-FIFO.
3) Initiates TX-DMA with the address of the first byte
of INDIVIDUAL ADDRESS and byte count according to configured Address Length.
4) Upon completion of DMA, writes the End of Command byte to TX-FIFO.
5) Waits for the Transmit-Byte-Machine to complete
the updating of Individual Address register.
6) If the internal CU-ABORT-REQUEST flag is set,
prepares STATUS word with C = 1, B = 0,
OK = 0, A = 1; otherwise, prepares STATUS
word with C = 1, B = 0, OK = 1, A = O.
7) Completes the Action Command.

lA-SETUP COMMAND FORMAT

The lA-SETUP command includes the following fields:
STATUS word (written by the 82586):
C
(Bit 15)
Command completed (see
section 2.8.1)
(Bit 14)
B
Busy executing command
(Bit 13)
OK
- Error free completion
(Bit 12)
- Command aborted
A
COMMAND word:
EL
(Bit 15)
S
(Bit 14)
(Bit 13)
CMD (Bits .0-2)

End of command list
Suspend after completion
Interrupt after completion
lA-SETUP = 1

The Transmit-Byte-Machine maintains a 48-bit Individual Address register used for Source Address insertion during transmission and for Destination Address
recognition during reception. RESET causes the Individual Address register to be set to all ones.

LINK OFFSET: Address of next Command Block
INDIVIDUAL ADDRESS: Individual Address parameter

After the Transmit-Byte-Machine reads an lA-SETUP
command from TX-FIFO, it reads the following bytes
into the Individual Address register. The expected
number of bytes is determined by the Address length
configuration parameter. If Address length is less than
6 bytes then only part of the register is used. If fewer
bytes than Address length are read from TX-FIFO (in
case of abortion) only that number of bytes is updated.

The least significant bit of the Individual Address parameter must be zero for IEEE 802.3. However, no
enforcement of 0 is provided by the 82586. Thus, an
Individual Address with least significant bit 1, is possible.
The 82586 will read only the number of bytes configured as address length.
15
C

B

EL

S

o

OK

(STATUS)

CMD = 1

4

LINK OFFSET
2ND BYTE

2
(COMMAND)

1ST BYTE
I

INDIVIDUAL ADDRESS

10
NTH BYTE

230814-25

Figure 2-12. The lA-SETUP Command Block
2-27

LAN COMPONENTS USER'S MANUAL

Byte 6-7:

2.8.4 Configure
The CONFIGURE command is used to update the
82586 operating parameters. It allows from 4 to 12 parameter bytes to be updated. Refer to section 2.12 for
details on the configuration parameters.

BYTE CNT (Bits 0-3) - Byte Count, Number of
bytes including this one, holding the parameters to be configured. A number smaller than
4 is interpreted as 4. A number greater than
12 is interpreted as 12.

CONFIGURE COMMAND FORMAT

FIFO-LIM (Bits 8-11) - Value of TX-FIFOThreshold

The CONFIGURE command includes the following
fields:

Byte 8-9:
SRDYI ARDY (Bit 6) - 0 - SRDYI ARDY pin
operates as ARDY (internal synchronization).

STATUS word (written by the 82586):
C

(Bit 15)

- Command completed
section 2.8.1)

B

(Bit 14)

- Busy executing command

OK

(Bit 13)
(Bit 12)

- Command aborted

A

(see

- Error free completion

1 - Received bad frames are saved in memory.
ADDR-LEN (Bits 8- 10) - Number of address
bytes. NOTE: 7 is interpreted as O.

COMMAND word:
EL
(Bit 15)

- End of command list

S

(Bit 14)

- Suspend after completion

(Bit 13)

- Interrupt after completion

(Bits 0-2)

- Configure = 2

CMD

1 - SRDYI ARDY pin operates as SRDY (external synchronization).
SAV-BF (Bit 7) - 0 - Received bad frames are not
saved in memory.

AL-LOC (Bit 11) - 0 - Address and Length Fields
separated from data and associated with
Transmit Command Block or Receive Frame
Descriptor. For transmitted Frame, Source
Address is inserted by the 82586.
1 - Address and Length Fields are part of the
Transmit/Receive data buffers, including
Source Address (which is not inserted by the

LINK OFFSET: Address of next Command Block

82586).

o

15
C

B

OK

00

~--~--+---4r.rr~~rrT7~rrT7~~71~T771~T77J~T771~---r---r--1
EL
~

S

CMD; 2

__L-__L-__~~~~~~~~~~LL~~LL~~~LL~~L---~--L--l

02
(COMMAND)
04

LINK OFFSET

FIFO LIM

(STATUS

06

BYTECNT

08

ADDR LEN
INTERFRAME SPACING

LIN PRIO

10

12

PRM

14

16

230814-26

Figure 2·13. The CONFIGURE Command Block
2-28

LAN COMPONENTS USER'S MANUAL

PREAM-LEN (Bits 12-13) - Preamble Length including Start Frame Delimiter
·00 - 2 bytes
01 - 4 bytes
10 - 8 bytes
11 - 16 bytes
INT-LPBCK (Bit 14) - Internal Loopback
EXT-LPBCK (Bit 15) - External Loopback.
NOTE: Bits 14 and 15 configured to 1, cause
Internal Loopback.

PAD (Bit 7) - Padding
0- No Padding
1 - Perform padding by transmitting flags for
remainder of Slot Time
CRSF (Bits 8-9) - Carrier Sense Filter in bit times
CRS-SRC (Bit 11) Carrier Sense Source
0- Ef(ternal
1 - Internal
CDTF (Bits 12-14) - Collision Detect Filter in bit
times
CDT-SRC (Bit 15) - Collision Detect Source
0- External
1 - Internal

Byte 10-11:
LIN-PRIO (Bits 0-2) - Linear Priority
ACR (Bits 4-6) - Accelerated Contention Resolution
BOF-MET (Bit 7) - Exponential Backoff Method
o - IEEE 802.3
1 - Alternate method
INTERFRAME-SPACING (Bits 8-15) - Number indicating the Interframe Spacing in TxC
period units

Byte 16:
MIN-FRM-LEN (Bits 0-7) - Minimum number
of bytes in a frame
CONFIGURATION DEFAULTS

The default values of the configuration parameters are
compatible with the IEEE 802.3 Standard. RESET
configures the 82586 according to the defaults shown in
Table 2-6:
Table 2-6. 82586 Default Values

Byte 12-13:
SLOT-TIME (L) (Bits 0-7) - Slot Time number,
low byte
SLOT-TIME (H) (Bits 8-10) - Slot Time number,
high bits
RETRY-NUM (Bits 12-15) - Maximum number
of transmission retries on collisions

Preamble Length
Address Length
Broadcast Disable
CRC-16/CRC-32
No CRC Insertion
- Bitstuffing/EOC
Padding
Min-Frame-Length
Interframe Spacing
SlotTime
Number of Retries
Linear Priority
Accelerated Contention Resolution
Exponential Backoff Method
Manchester/NRZ
Internal CRS
CRS Filter
Internal CDT
CDT Filter
Transmit On No CRS
FIFO-Threshold
SRDY/ARDY
Save Bad Frame
Address/Length Location
Internal Loopback
External Loopback
Promiscuous Mode

Byte 14-15:
PRM (Bit 0) - Promiscuous Mode
BC-DIS (Bit 1) - Broadcast Disable
MANCH/NRZ (Bit 2) - Manchester or NRZ encoding/decoding
0- NRZ
1 - Manchester
TONO-CRS (Bit 3) - Transmit on No Carrier
Sense
o - Cease transmission if CRS goes inactive
during frame transmission
1 - Continue transmission even if no Carrier
Sense
NCRC-INS (Bit 4) - No CRe Insertion
CRC-16 (Bit 5) - CRC Type
o - 32 bit Autodin II CRC polynomial
1 - 16 bit CCITT CRC polynomial
BT-STF (Bit 6) Bitstuffing:
o - End of Carrier mode (IEEE 802.3)
1 - HDLC like Bitstuffing mode
2-29

2
6
0
0
0
0
0
64
96
512
15
0
0
0
0
0
0
0
0
0
8
0
0
0
0
0
0

LAN COMPONENTS USER'S MANUAL

After the Transmit-Byte-Machiile reads the CONFIGURE command from TX-FIFOit reads and ignores 2
bytes, reads and updates Configuration registers with
the next 10 bytes, and reads and ignores the remaining
bytes. If less than 12 bytes are read when End of Command is encountered, only part of the Configuration
registers are updated: The Transmit-Byte-Machine notifies CU after completion.

DETAILED OPERATION OF THE CONFIGURE
COMMAND

Some parameters are kept by the CU, the remainder are
transferred by TX-DMA to the Transmit-Byte-Machine via TX-FIFO. The CU performs the following
sequence.
I) Starts the Action Command.
2) Reads bytes 6, 7, 8, and 9, and saves the following:
BYTE-CNT, FIFO-LIM, SRDY/ARDY, SAV-BF,
ADDR-LEN, AL-LOC.
3) Writes the Configure byte to TX-FIFO..
4) Initiates TX-DMA to address of byte 6 and byte
count specified by BYTE-CNT.
5) Upon completion of DMA writes the End of Command byte to TX-FIFO.
6) Waits for the Transmit-Byte-Machine to complete
updating configuration registers.
7) If the internal CU-ABORT-REQUEST flag is set,
prepares STATUS word with C = I, B= 0,
OK = 0, A = I; otherwise, prepares STATUS
word with C = I, B = 0, OK = I, A = 0.
8) Completes the Action Command.

2.8.5 Me-Setup
This command sets up the 82586 with a set of Multicast
Addresses. Subsequently, incoming frames with Destination Addresses from this set are accepted.
MC-SETUP COMMAND FORMAT

The MC-SETUP command includes the following
fields:
STATUS word (written by the 82586):
C
(Bit 15)
- Command completed (see
section 2.8.1)
(Bit 14)
- Busy executing cpmmand
B.
OK
(Bit 13)
- Error free completion
A
(Bit 12)
- Command aborted
COMMAND word:
EL
(Bit 15)
- End of command list
S
(Bit 14)
- Suspend after completion
I
(Bit \3)
- Interrupt after completion
CMD (Bits 0-2)
- MC-SETUP = 3
LINK OFFSET: Address of next Command Block

The Transmit-Byte-Machine maintains 10 bytes of
Configuration registers for determining the 82586's
'personality.' RESET causes Configuration registers to
be set to values specified in Table 2-6 (compatible to
IEEE 802.3).

o

15

c

B

OK

A

o

ZEROS

(STATUS)

LINK OFFSET

4
6

MC-CNT

·1-'-.L..I.-'-L...L...L.-_ _ _ _ _ _ _ _ _ _--._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _. . --MCLlST,

2ND BYTE

1ST BYTE

,
MC-ID,

NTH BYTE
ADDITIONAL MC·ID'S

I

IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIJ"I~'III'II'I"II"I

230814-27

Figure 2-14. The MC-SETUP Command Block

2-30

LAN COMPONENTS USER'S MANUAL

MC-CNT: A 14-bit field indicating the number of
bytes in the MC-LIST field. MC-CNT is
truncated to the nearest multiple of Address
Length (in bytes). Issuing a MC-SETUP
command with MC-CNT = 0 disables reception of any incoming frame with a Multicast Address. The 14 bit field for MC addresses accommodates a maximum of 2730
Multicast Addresses, assuming a 6 byte address length.

HASH table. Transmit-Byte-Machine notifies CU after
completion.

2.8.6 Transmit
The TRANSMIT command causes transmission and if
necessary retransmission of a frame.
TRANSMIT COMMAND BLOCK FORMAT

TRANSMIT CB includes the following fields:
STATUS word (written by the 82586):
C
(Bit 15)
- Command completed (see
section 2.8.1)
(Bit 14)
- Busy executing command
B
- Error free completion
(Bit 13)
OK
, (Bit 12)
- Command aborted
A
(Bit 10)
- No Carrier Sense signal durSIO
ing transmission (between beginning of Destination Address and end of Frame
Check Sequence). On the Bstep this bit will always be
zero when the 82586 is configured with TONO-CRS =
1. All subsequent steppings
S10 will be set if the Carrier
Sense signal is lost, regardless
of the TONO-CRS Configure
bit.
- Transmission
unsuccessful
(Bit 9)
S9
(stopped) due to loss of Clearto-Send signal.
S8
(Bit 8)
- Transmission
unsuccessful
(stopped) due to DMA underrun, (i.e. data not supplied
from the system for transmission).
- Transmission had to Defer to
(Bit 7)
S7
traffic on the link.
- SQE TEST. Indicates that af(Bit 6)
S6
ter the previous transmission
and during the Interframe
Spacing period, the SQE
TEST signal was detected on
the Collision Detect pin. This
bit is meaningful if S5 and
MAX-COLL fields are both
zero, i.e. no collisions occurred during transmission. _
S5
(Bit 5)
- Transmission
attempt
stopped due to number of collisions exceeding the maximum number of retries.
MAX-COLL (Bits 3-0) - Number of Collisions experienced by this frame. S5 = 1
and MAX-COLL = 0 indicates that there were 16 collisions.

MC-LIST: A list of Multicast Addresses to be accepted
by the 82586. Note that the most significant
byte of an address is followed immediately
by the least significant byte of the next address. Note also that the least significant bit
of each Multicast Address in the set must be
a one.
DETAILED OPERATION OF MC-SETUP
COMMAND

TX-DMA transfers the list of Multicast Addresses
from memory to Transmit-Byte-Machine via TXFIFO. See section 2.13. CU performs the following sequence:
1) Starts Action Command.
2) Reads MC-CNT and saves it internally.
3) Writes a MC-SETUP command byte to TX-FIFO.
4) Initiates TX-DMA with the MC-LIST address and
byte count according to MC-CNT.
5) Upon completion ofDMA; writes End of Command
bit to TX-FIFO. '
6) Waits for Transmit-Byte-Machine to complete
HASH table update.
7) If the internal CU-ABORT-REQUEST flag is set,
prepares STATUS word with C = 1, B = 0,
OK = 0, A = 1; otherwise, prepares STATUS
word with C = I, B = 0, OK = 1, A = O.
8) Completes the Action Command.
The Transmit-Byte-Machine maintains a 64-bit HASH
table used for checking Multicast Addresses during reception.
An incoming frame is accepted if it has a Destination
Address whose least significant bit is a one, and after
hashing points to a bit in the HASH table whose value
is one. The hash function is selecting bits 2 to 7 of the
Transmit CRC register. RESET causes the HASH table to become all zeros.
After the Transmit-Byte-Machine reads a MC-SETUP
command from TX-FIFO, it clears the HASH table
and reads the bytes in groups whose length is determined by the ADD~ESS length. Each group is hashed
using CRC logic and the bit in the HASH table to
which bits 2-7 of the CRC register point is set to one.
A group that is not complete has no effect on the
2-31

LAN COMPONENTS USER'S MANUAL

COMMAND word:
EL
(Bit 15)
S
(Bit i4)
(Bit 13)
CMD (Bits 0-2)

-

DETAILED OPERATION OF TRANSMIT
COMMAND

End of command list
Suspend after completion
Interrupt after completion
TRANSMIT = 4

Execution of TRANSMIT Command causes transmission of a frame. If the frame experiences collisions, the
CU retransmits the frame up, to a configurable maximum number of times.

LINK OFFSET: Address of next Command Block

To transmit a frame, the user must setup the following:

TBD OFFSET: Address of the first Transmit Buffer
Descriptor. TBD~OFFSET = OFFFFH indicates that
there is no Data field.

• Command code.
• Destination Address and Length Field in TRANSMIT CB.
• TBD OFFSET should point to the first Buffer Descriptor of the list of buffers that holds the Data
Field. If the frame 'does not include Data,' TBD
OFFSET should be set to OFFFFH.
• For each buffer, BUFFER ADDRESS, ACTUAL
COUNT and NEXT BD OFFSET should be setup.
The EOF flag indicates the last buffer in the list
representing the Data Field.

DESTINATION ADDRESS: Destination Address of
the frame. '
LENGTH FIELD: Length Field of the frame.
TRANSMIT B!JFFER DESCRIPTOR FORMAT

STATUS word:,

Unlike other Action Commands having parameters in
one block in memory, the, TRANSMIT Command may
have parts of the parameters scattered in a linked list of
buffers. The CU prefetches the buffers in'the list on the
fly. If the AL-Location configuration is zero, the Destination Address and Length Field are in the TRANSMIT CB and are treated as the first buffer. The Information Field is in the list of buffers. If the AL-Location
Bit is one, the whole frame is in the buffers. See Figure
2-17.
'

EOF - Indicates that this is the Buffer Descriptor of
the last buffer of this frame's Data Field.
ACT-COUNT (Bits 0-13) - Actual number of data
bytes in the buffer (can
be even or odd).
NEXT BD OFFSET: Points to next Buffer Descriptor
on the list. When the EOF bit is
set, this field is meaningless.
BUFFER ADDRESS: 24-bit absolute address of buffer.

o

15
C

B

EL

S

2ND BYTE

o

MAXCOLL

OK

(STATUS)

CMD=4

LINK OFFSET

4

TBDOFFSET

6
1ST BYTE

I

MC

8

I
DESTINATION ADDRESS

r-__

A

I
~N~T~H~B~Y~T~E______________~__~~~______________________________~B

LENGTH FIELD

C
230814-28

Figure 2-15. The Transmit Command Block

2-32

LAN COMPONENTS USER'S MANUAL

15
ACT COUNT

EOF
~

o
4 (STATUS)

__~~~__~__~__-L__~__~~~~__~__~__~__~__- L_ _-L__- L__

NEXT TBD OFFSET

2

BUFFER ADDRESS

4

6
230814-29

Figure 2-16. The Transmit Buffer Descriptor

SCB

CBLPOINTER
COMMAND LIST
CBl
STATUS
CMD

Lr

CB2
STATUS
TRANSMIT
BDPOINTER

~TBDI

o IACT. COUNT

U'
r--

UI
o

,-

,

TBD2U
ACT. COUNT

NEXTBD
BUFFER
POINTER

NEXTBD
BUFFER
POINTER

1

!

I'"~I

CB N
STAT US
CM D

BUFFER

2

Figure 2-17. The Transmit Command Data Structure

2-33

1 ACT.COUNT

NEXTBD
BUFFER
POINTER

BUFFER

N
230814-30

LAN COMPONENTS USER'S MANUAL

10) If the execution completed with an error (no collision or CU-ABORT-REQUEST); prepares
STATUS word with C = 1, B = 0, OK = 0,
A =
and the remaining bits updated.
11) Completes the Action Command.

While the CU is prefetching the address and byte count
of one buffer, TX-DMA is transferring the previous
buffer to the Transmit-Byte Machine via TX-FIFO.
Completion of buffer transfer by TX-DMA, triggers
the CU to initiate TX-DMA for the next buffer (if already prefetched) and to start the prefetch of the next
buffer. The buffer prefetch/transfer cycle is terminated
when a buffer, whose EOF bit is set, is transferred to
TX-FIFO.

°

Note that transmission is terminated by the CU performing one of the following steps; 7, 8, 9, or 10.
The Chart below summarizes which sequence step listed above the CU performs:

.CU performs the following sequence during transmission:
1) Starts the Action Command.
2) Writes the TRANSMIT Command bit to TXFIFO.
3) Reads BD OFFSET and saves it as the Look
Ahead BD Address.
4) If the ADDRESS/LENGTH LOCATION configuration bit is zero, the 82586 does the following:
If the Look Ahead BD Address is not equal to
OFFFFH, then goes to the buffer prefetch/transfer
cycle (section 2.9.6). Initiates TX-DMA to the address of the first byte of the Destination Address
field in the CB and to the byte count of the Address
length bit plus 2. If the Look Ahead BD Address is
equal to OFFFFH, then after completing DMA of
the Destination Address and Length Field writes
End of Command byte to TX-FIFO.
5) If the ADDRESS/LENGTH LOCATION configuration bit is one, then goes to the buffer prefetch/
transfer cycle and forces one dummy DMA completion.
6) Waits for completion of the TRANSMIT Command. This includes transfer of the whole frame to
the Channel Interface Module and transmission of
the frame by the latter. The command can be completed either with a collision (and not exceeding
maximum collision) or without a collision.
7) If execution completed without a collision and
without an error (regardless of CU-ABORT-REQUEST),
then
prepares
STATUS word
with C = 1, B = 0, OK = 1, A = 0, S6, S7 and
NUM-COLL updated, and remaining bits zero.
8) If execution completed with CU-ABORT-REQUEST (and a collision or error) prepare STATUS
word with C = 1, B == 0, OK = 0, A = 1 and
NUM-COLL = 1.
9) If execution completed with a Collision (and not
exceeding maximum collision), regardless of errors
and without CU-ABORT-REQUEST, writes Retransmit command byte to TX-FIFO and returns
to Step 3 of this sequence. This causes retransmission of the frame.

Collision

Error

no
no
no
yes
yes

no
yes
yes
don't care
don't care

Abort-Request Step

don't care
no
yes
no
yes

7
10
8
9
8

Remarks

normal
error
abort
retransmit
abort

BUFFER PREFETCH/TRANSFER CYCLE

This cycle is called by the sequence-performing
TRANSMIT command execution. Collision detection
(not exceeding the maximum collision) anytime during
this sequence, causes CU to Read BD OFFSET and
save it as the Look Ahead BD Address, write retransmit command byte to TX-FIFO and go to Step 4 of the
TRANSMIT command sequence.
The buffer prefetch/transfer cycle is as follows:
1) Store Look Ahead BD address in Next-BD-Address.
2) Read and save 14-bit ACT COUNT field and EOF
flag.
3) Read NEXT BD OFFSET and save it in Look
Ahead BD Address.
4) Read and save the 24-bit BUFFER ADDRESS field.
5) Wait for completion of TX-DMA (first time initiated in step 4 of transmit sequence).
6) Initiate TX-DMA with address according to BUFFER ADDRESS and byte count according to ACT
COUNT.
.
7) If EOF bit is not set, repeat the cycle.
8) After DMA completion, write the End of Command
byte to TX-FIFO.
FRAMING OPERATION

The Transmit-Byte-Machine maintains the following
registers for construction of frames: Preamble pattern,
SFD Field (pattern determined by End-of-CarrierlBitstuffing configuration parameters), Source Address,
CRC generator, Jam patterns (all ones).

2-34

LAN COMPONENTS USER'S MANUAL

After the Transmit-Byte-Machine reads the TRANSMIT command from TX-FIFO, a frame is constructed
and transferred to the Transmit-Bit-Machine (see section 2.13) for bit transmission. The Transmit-Byte-Machine performs the following sequence:
I) Transfer Preamble bytes according to Preamble
length configuration parameter minus one.
2) Transfer the SFD Field.
3) Start CRC calculation.
4) Read and transfer the Destination Address bytes
from TX-FIFO (number determined by Address
length).
5) If AL-Location configuration parameter is zero,
transfer Individual Address as Source Address. Otherwise, read and transfer Source Address from TXFIFO. If AL-Location = 1 and there are less than
Address-Length bytes in TX-FIFO, a DMA underrun is forced.
6) Read and transfer all remaining bytes from TXFIFO. These are the Length and Information fields.
7) Transfer CRC (calculated according to CRC 16/32
configuration parameter).
8) If the 82586 is configured to Bitstuffing, transfer one
more flag.
9) If the 82586 is configured to Bitstuffing and to padding, transfer flag bytes to cause the number of
transferred bytes (excluding Preamble and SFD
Field) to exceed the configurable Slot Time divided
by 8.
If a collision, underrun, or lost Carrier Sense occurred
during transmission, the Transmit-Byte-Machine completes the transfer of the Preamble and transfers 4 bytes
of the Jam pattern. If there is a collision, the retry
counter will be incremented.

Jamming will not start before completing Preamble
transmission.
If a collision is detected during transmission of the last
11 bits in the frame it will not result in jamming. If the
collision is detected during transmission of the last bit
or later, the collision will not be reported and retransmission does not take place. This may happen for an
invalid frame which is shorter in length than the slot
time.
Note that a DMA underrun cannot logically occur during the preamble because the serial subsystem generates
its own preamble. Also, the 82586 is insensitive to carrier sense during the preamble.
After completing transmission, or collision, the Transmit-Byte-Machine passes bits 0-10 of the STATUS
word to the CU.

2.8.7 TDR (Time Domain
Reflectometer)
This command performs a Time Domain Reflectometer
test on the serial link. By performing the command, the
user is able to identify short or opens and their location.
Along with transmission of 'All Ones,' the 82586 triggers an internal timer. The timer measures the time
elapsed from transmission start until 'echo' is obtained.
'Echo' is indicated by Collision Detect going active or
Carrier Sense signal drop.
TDR COMMAND FORMAT

TDR command includes the following fields:
STATUS word (written by the 82586):
C
(Bit 15)
- Command completed (see
section 2.8.1)
B
(Bit 14)
- Busy executing command
(Bit 13)
OK
- Error free completion

o

15

C

B

OK

ZEROS

0

~__+-__+-~~rr77~rr7F~rT7F~rT"rrT7"rr77~rT7F~r---~--~~(STATUS)
CMD=5
2
S
EL
~__L-__L-~~~~~~~~~~~LL~~~~~~LL~~__~__~__~(COMMAND)
LINK OFFSET

~

__r -__r-~__~~~__________________________________________~4

LNK

OK

~~~~

__

~

__

TIME

~~~

________________________

~

__________

~6

230814-31

Figure 2-18. The TDR Command Block

2-35

LAN COMPONENTS USER'S MANUAL

COMMAND word:
EL
(Bit 15)
(Bit 14)
S
(Bit 13)
CMD (Bits.0-2)

-

should not return Carrier Sense during transmission,
this is normal.
2) The Carrier Sense signal goes active and then inactive before the counter ·expires. For a Transceiver
that should return Carrier Sense during transmission, this means that there is a short on the link.
3) The Collision Detect signal goes active before the
counter expires. This means that the link is not properly terminated (an open).
4) The Carrier Sense signal goes active but does not go
inactive and Collision Detect does not go active before the counter expires. This is the normal case and
indicates that there is no problem on the link.

End of command list
Suspend after completion
Interrupt after completion
TDR = 5

LINK OFFSET: Address of next Command Block
RESULT word:
LNK~OK
(Bit 15) - No link problem identified
XCVR-PRB (Bit 14) - Transceiver Cable Problem
identified (valid only in the
case of a Transceiver that
should return Carrier Sense
during transmission).
ET-OPN
(Bit 13) - Open on the link identified.
ET-SRT
(Bit 12) - Short on the link identified
(valid only in the case of a
Transceiver that should retum. Carrier Sense during
transmission).
- Specifying the distance to a
TIME (Bits 0-10)
problem on the link (if one
exists) in transmit clock cycles.

The distance to the cable failure can be calculated as '
follows:
Distance = TIME X (Vs/(2XFs»
where:
Vs - wave propagation speed on the link (Mis)
Fs - serial clock frequency (Hz)
Accuracy is plus/minus Vs/(2 X Fs)
Upon completion, the Transmit-Byte-Machine passes
the RESULT word to the CU.
Note that the TDR frame does not contain the SFD
field.

DETAILED OPERATION OF TDR COMMAND

2.8.8 Dump

TDR command triggers the Time Domain Reflectometer test to be performed by the Transmit-Byte-Machine,
see section 2.13.

This command causes the contents of over a hundred
bytes of internal registers to be placed in memory. It is
supplied as a self diagnostic tool, as well as to supply
registers of interest to the user.

The CU performs the following sequence:
1) Starts the Action Command.
2) Writes the TDR Command byte to TX-FIFO.
3) Waits for the Transmit-Byte-Machine to complete
TDR test.
4) Writes results to RESULT word.
5) Prepares STATUS word with C
1, B = 0,
OK = 1.
6) Completes the Action Command.

DUMP command includes the following fields:
STATUS word (written by the 82586):
C
(Bit 15)
- Command completed (see
section 2.8.1)
(Bit 14)
- Busy executing command
B
OK
(Bit 13)
- Error free completion

After the Transmit-Byte-Machine reads a TDR command from TX-FIFO, it performs a Time Doman Re- .
flectometer test by transmitting a TDR frame (2048
ones) and monitoring Carrier Sense and Collision Detect signals. When a TDR frame is transmitted, an internal 12-bit counter starts counting.
There are four possible results:
1) The Carrier Sense signal does not"go active before
the counter expires. For a Transceiver that should
return Carrier Sense during transmission, this means
that there is a problem on the cable between the
82856 and the Transceiver. For a Transceiver that

COMMAND word:
EL
(Bit 15)
S
(Bit 14)
I
(Bit 13)
CMD (Bits 0-2)

-

End < ~ lXIX
EKT
LP
BCK

PREAM
LEN

INT
LP
BCK

11

10

9

8

.,

FIFO LIM'
AL
LOC AOOR

LEN

•

COT
SRC

1

NUM

1

1

5

4

3

2

1

0

0

D<

0

0

0

0

0

0

00

SAY
BF ~~~'!/

1

1

1

1

1

1

02

1

LIN

ACR.

.

CRSF

1

1

PAD

BT CRC
STF 16

1 .1

NeRe

TONO

INS

CRS

MIN

0

TX
OK

0

OA

IAR 3

IAR 2

OE

IAR 4

10

0

0

LST LST
CRS CTS

URN TX saET MAX
DEF
COL

C'OLL'NUM

0

12

~

TXCRCR 1

TXCRCR 0

14

TXCRCR 3

TXCRCR 2

16

RXCRCR 1

RXCRCR 0

18

RXCRCR 3

RXCRCR 2

1A

TEMPR 1

TEMPR 0

1C

TEMPR3

TEMPR 2

1E

TEMPR 4

20

RX
OK

1

CRC ALN
ERR ERR

0

aVRN

SHRT NO
FRM EOP

1

1

1

1

1

1

22

HASHR 1

HASHR 0

24

HASHR 3

HASHR 2

26

HASHR 5

HASHR 4

28

HASHR 7

HASHR 6

2A

ET
OPN

ET
SRT

1

1

1

1

0

0

0

0

XCVR

LEN

08

OC

PRB

LNK
OK

06
BC PRM
DIS

IARO

TEMPR 5
1

FRM

MAN
CHI

04

IAR 1

IAR 5
ReNT
COL

PRIO

SLOT TIME (LOW)

SLT>M:[H]

CRS
SRC

qOTF
1

1

6

EBOF
NET

INTER FRAME SPACING
RETRY

7

D< ~IX ~ lXIX IXIXIXIXIX~
X X ~ X ~ ~ ~ X lX X
1

1

0

0

0

0

0

0

0

0

0

0

0

0

2C
2E
30
230814-33

Figure 2·20. The DUMP Area

2-38

LAN COMPONENTS USER'S MANUAL

15141312111098765432

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

32

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

34

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

36

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

38

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

3A

X X X~ C>< X~ ~ XX X [X X ~ X~
0

0

EL

D<

0

0

0

0

0

0

0

0

0

0

ADR LEN

ELlXI

IX!

NXT RB ADR (HIGH)

S

I

42

NXT RB ADR (LOW)

44

CUR RB SIZE

46

LA RBD ADR

48

NXT RBDADR

4A

CUR RBD ADR

4C

CUR RB EBC

4E

NXT FD ADR

50

CUR FD ADR

52

TEMPORARY

54

NXTTB CNT

56

BUF ADR

58

NXTTB ADR

5A

LATBD ADR

5C

NXTTBD ADR
EL

3E
40

NXT RB SIZE

VII I I I I I I I III!II/J

EOF

0

3C

V/i/i/ii/i/i//III/ii/J
NXT CB ADR

5E
OUMPCMD
CODE (110)

60
62
230814-34

Figure 2·20. The DUMP Area (Continued)

2·39

LAN COMPONENTS USER'S MANUAL

1514131211 10

9

7

8

6

5

4

3

2

0

CUR CB ADR

64
66

5CB ADR

68

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

6A

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

6C

0

0

0

0

0

0

0

0

0

0

0

0

0 ·0

0

0

6E

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

70

0

72
74
76
78
7A
7C
7E
80
82
84
86
88
8A
8C
8E
0

0

0

0

0

0

0

BUF

0
ADR

PRT

BUF ADR PTR (HIGH)

90

(LOW)

92

RCV DMA BC

94
230814-35

Figure 2-20. The DUMP Area (Continued)

2-40

LAN COMPONENTS USER'S MANUAL

151413121110987
I

I

BR+ BUF'

I

0

0

0

6

5

3

4

2

0

0

0

0

ADRt H

0

1

•

I

I

0
I

96

I

I

98

RCV DMAADR H

9A

RCV DMAADR L

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

9C

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

9E

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

AO

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

A2

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

SRDYI

AiiiiY

A4

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

A6

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

AS
230814-36

Figure 2-20. The DUMP Area (Continued)

CUR-RBD-ADR:
Current Receive Buffer Descriptor Address. Similar to LA-RBD-ADR, but points
to Nth Receive Buffer Descriptor.
CUR-RB-EBC:
Current Receive Buffer Empty
Byte Count. Let N be the currently· used Receive
Buffer. Then CUR-RB-EBC indicates the Empty
part of the buffer, i.e. the ACT-COUNT qf buffer
N is given by the difference between its SIZE and
the CUR-RB-EBC.
NXT-FD-ADR:
Next Frame Descriptor Address.
Definf! N as the last Receive Frame Descriptor
with bits C = I and B = 0, then NXT-FD-ADR
is the address of N + 2 Receive Frame Descriptor
(with B = C = 0) and is equal to the LINK-ADDRESS field in N + I Receive Frame Descriptor.
CUR-FD-ADR:
Current Frame Descriptor Address. Similar to next NXT-FD-ADR but refers to
NI Receive Frame Descriptor (with B = I,
C = 0).
Bytes 54H to 55H:
Temporary register.
NXT-TB-CNT:
Next Transmit Buffer Count. Let
N be the last transmitted buffer of the TRANSMIT command executed recently, the NXT-TBCNT is the ACT-COUNT field in the Nth Transmit Buffer Descriptor.
EOF - Corresponds to the EOF bit of the Nth
Transmit Buffer Descriptor. EOF = I indicates
that the last buffer accessed by the 82586 during
Transmit was the last Transmit Buffer in the
data buffer chain associated with the Transmit
Command.

BUF-ADR:
Buffer Address. The BUF-PTR field
in the DUMP-STATUS Command Block.
NXT-TB-AD-L:
Next Transmit Buffer Address
Low. Let N be the last Transmit Buffer in the
transmit buffer chain of the TRANSMIT Command performed recently, then NXT-TB-AD-L
are the two least significant bytes of the Nth buffer
address.
LA-TBD-ADR:
Look Ahead Transmit Buffer Descriptor Address. Let N be the last Transmit Buffer in the transmit buffer chain of the TRANSMIT
Command performed recently, then LA-TBDADR is the NEXT-BD-ADDRESS field of the
Nth Buffer Descriptor.
NXT-TBD-ADR:
Next Transmit Buffer Descriptor Address. Similar in function to LA-TBD-ADR
but related to Transmit Buffer Descriptor N-l.
Actually, it is the address of Transmit Buffer Descriptor N.
Bytes 60H, 61H:
This is a copy of the 2nd word in
the DUMP-STATUS command presently executing.
NXT-CB-ADR:
Next Command Block Address.
The LINK-ADDRESS field in the DUMP Command Block presently executing. Points to the next
command.
CUR-CB-ADR:
Current Command Block Address. The address of the DUMP Command Block
currently executing.

2-41

LAN COMPONENTS USER'S MANUAL

SCB-ADR:
(SCB).

Offset of the System Control Block

RCV-DMA-ADR - Receive DMA absolute Address.
This is the next RCV-DMA start address. The value depends on AL-LOCation configuration bit.
1) If AL-LOCation = 0, then RCV-DMA-ADR
is the Destination Address field located in the
next Receive Frame Descriptor.
2) If AL-LOCation = 1, then RCV-DMA-ADR
is the next Receive Data Buffer Address.

Bytes 7EH, 7FH:
RU-SUS-RQ (Bit 4) - Receive Unit Suspend Request.
Bytes 80H, 81H:
CU-SUS-RQ (Bit 4) - Command Unit Suspend Request
END-OF-CBL (Bit 5) - End of Command Block
List. If '1' indicates that DUMP-STATUS is
the last command in the command chain.
ABRT-IN-PROG (Bit 6) - Command Unit Abort
Request.
RU-SUS-FD (Bit 12) - Receive Unit Suspend
Frame Descriptor Bit. Assume N is the Receive Frame Descriptor used recently, then,
RU-SUS-FD is equivalent to the S bit of
N + 1 Receive Frame Descriptor.
Bytes 82H, 83H:
RU-SUS (Bit 4) - Receive Unit in SUSPENDED
state.
RU-NRSRC (Bit 5) - Receive Unit in NO RESOURCES state.
RU-RDY (Bit 6) - Receive Unit in READY state.
RU-IDL (Bit 7) - Receive Unit in IDLE state.
RNR (Bit 12) - RNR Interrupt In Service bit.
CNA (Bit 13) - CNA Interrupt In Service bit.
FR (Bit 14) - FR Interrupt In Service bit.
CX (Bit 15) - CX Interrupt In Service bit.

The following notes apply to all the information of the
dump area:
1) The listed pointers are meaningful only if the 82586
has completed the prefetch.
2) All Transmit Pointers refer to the last executed
TRANSMIT Command.
3) The Receive Pointers are meaningful only if they exist, namely a frame was received into the existing
memory structure.
4) The following nomenclature has been used in the
DUMP table:
The 82586 writes zero in this location.
1 - The 82586 writes one in this location.
X - The 82586 writes zero or one in this location.
/ / /- The 82586 copies this location from the corresponding position in the memory structure.

°-

DETAILED OPERATION OF DUMP COMMAND

Configuration parameters and contents of other registers are transferred from the Channel Interfaced Module via RCV-FIFO by Receive Unit to memory.
The Command Unit performs the following sequence:
1) Starts Action Command.
2) Writes DUMP command byte to TX-FIFO.
3) Waits for completion of DUMP. ,
4) Prepares STATUS word with C= 1, B
0,
OK = 1.

Bytes 90H to 93H:
BUF-ADR-PTR - Buffer pointer is the absolute
address of the bytes following the DUMP
Command block.

5) Completes Action Command.
Bytes 94H to 95H:
The Receive Unit performs the followi!lg sequence.
1) Writes the word with the FIFO-Threshold configuration field to memory.
2) For all data written by the Channel Interface Module to RCV-FIFO: Reads 2 bytes from FIFO, assembles them into a word and writes it to the next location in memory buffer.
3) Writes 64 CU and RU registers to the remaining
space in memory buffer.
4) Notifies CU that DUMP completed.

RCV-DMA-BC - Receive DMA Byte Count. This
field contains number of bytes to be transferred during the next Receive DMA operation. The value depends on AL-LOCation
configuration bit.

°

I) If AL-LOCation = then RCV-DMA-BC
= (2 times ADDR-LEN plus 2) if the next
Receive Frame Descriptor has already been
fetched.
2) If AL-LOCation = 1 then it contains the
size of the next Receive Buffer.
BR

+

BUF-PTR + 96H - Sum of Base Address plus
BUF-PTR field and 96H.

The Channel Interface Module passes 46 bytes of internal registers to RU and notifies CU on completion.
NOTE:
This is the only Action Command involving the RU.
2-42

LAN COMPONENTS USER'S MANUAL

The Channel Interface Module. performs the self test
procedure in two phases: Phase 1 tests the counters and
Phase 2 tests the trigger logic'.

2.8.9 Diagnose
The DJAGNOSE Command triggers an internal self
test procedure of backoff related register and counters.

During Phase 1, Free Run, Exponential Backoff Timeout, Slot Time and Collision Counters are checked.
DIAGNOSE COMMAND FORMAT

The test is performed in the following steps:

The DIAGNOSE command includes the following:

1) All counters are RESET simultaneously.

STATUS word (written by 82586):
C

(Bit 15)

- Command completed
section 2.8.1)

B

(Bit 14)

- Busy executing command

OK

(Bit 13)

- Error free completion

FAIL

(Bit 11)

- Indicates that the self test
procedure failed

2) Start counting.

(see

3) Stop counting when the Free Run Counter (10 bits),
and Exponential Backoff Counter (10 bits), wrap
from 'All Ones' to 'All Zeros.' Simultaneously, the
Slot Time counter switches from 01111111111 to
10000000000, and the collision counter (4 bits)
wraps from 'All Ones' to 'All Zeros.'
4) Phase 1 is successful if the 10 least significant bits
(when applicable), of all four counters are 'all zeros.'

COMMAND word:
EL

(Bit 15)

- End of command list

S

(Bit 14)

- Suspend after completion

I

(Bit 13)

- Interrupt after completion

CMD

(Bits 0-2)

- DIAGNOSE = 7

During Phase 2, the test is performed in the following
steps:
1) Reset Exponential Backoff Shift Register, and all
counters.

LINK OFFSET: Address of next Command Block

2) Temporarily configure internally, Exponential Backoff logic a.ccording to the following:

OPERATION DETAILS OF DIAGNOSE
COMMAND

SLOT-TIME = OBH
LIN-PRIO

= 02H

CU triggers the self test procedure of the Channel Interface Module. It performs the following sequence:

EXP-PRIO

=OlH

BOF-MET

= OOH

I) Starts Action Command.
2) Writes DIAGNOSE command byte to TX-FIFO.
3) Waits for command completion.
4) If diagnose succeeded, then prepares STATUS word
with C = 1, B = 0, OK = 1, FAIL = 0; otherwise,
prepares STATUS word with C = 1, B = 0,
OK = 0, FAIL = 1.
5) Completes Action Command.

3) Emulate internally, transmission and collision.

4) If the most significant bit of Exponential Backoff
Shift Register is 0, then go to step 3.
5) Check Mask Logic output for being 'All Ones' (Free
Run Counter is 'All Ones' at this point and Expo.nential Backoff Shift Register is also 'All Ones').
If Step 5 is successful, then a 'Passed' status is returned
otherwise, 'Failed' status is returned.

o

15

C
B
OK
o
~--+---+---~r7~~~~r7"~77~r77J~77~rr7J~T7~rr--~--~--~(STATUS)
EL

S

CMD=7

2

~__~__~__~~~~~~~~~~~~~~~~~~~~~~__~__~__~(COMMAND)

LINK OFFSET

4

230814-37

Figure 2-21. The DIAGNOSE Command Block

2-43

LAN COMPONENTS USER'S MANUAL

2.9 FRAME RECEPTION

ers are chained via Receive Buffer Descriptors (RBD),
which point to a single buffer.

Section 2.7 described how the user can control frame
reception. This section presents the details of receiving
and storing frames in memory.

Refer to section 5.3 for setting the minimum buffer size.

2.9.2 Frame Descriptor (FD) Format
2.9.1 Receive Frame Area (RFA)

The FD (see Figure 2-23) includes the following fields:

The Receive Frame Area, RFA, is prepared by the host
CPU. The 82586 places data into the RFA as frames
are received. The RFA consists of a list of Receive
Frame Descriptors (FD), each of which is associated
with a frame. The RFA-OFFSET field of the SCB
points to the first FD of the chain; the last FD is identified by the End of List flag (EL). See Figure 2-22.

STATUS word (written by the 82586):
- Completed storing a frame.
C
(Bit 15)
- The 82586 knows about this
B
(Bit 14)
FD and is ready to use it.
(Bit 13)
OK
- Frame received successfully.
If this bit is set, then all others will be reset; if it is reset,
then the other bits will indicate the nature o(the error.
Sl1
(Bit 11)
- The received frame experienced a CRC error.

In general, the incoming' frame length is unknown beforehand. Rather than allocating buffers with a length
greater than the largest expected frame, the 82586
makes it possible to store frames in a sequence of small
buffers, which are chained into complete frames. BuffSCB

TO COMMAND LIST
RFA
POINTER

~

STATISTICS

II

RECEIVE FRAME AREA
FD 2

,

FD 1

-----+

STATUS

-

RECEIVE
FRAME
DESCRIPTORS

,,
I

W

,

--l

1
I
,I

VALID

PARAMETERS

l

RECEIVE
BUFFER
DESCRIPTORS

RBD1

o IACT..,n! r-

--

---

STATUS

1

L

RBD2:
I

I ACT..,n!

.-

-~
I
I

.-

-

EMPTY

EMPTY

RBD3

RBD4

ACT..,n!

ACT..,n!

o

FD4

FD3
STATUS

r""

STATUS

-

r+i

EMPTY

- ro - .
r""

RBDS

01 ACT..,n!

-

,..i

I
!
1
II
I

r--'-RECEIVE
BUFFERS

r--'--

1-

r--'--

r--'--

I

VALID
DATA

'--BUFFER 1

I
I

1
I

'--BUFFER 2

RECEIVE FRAME LIST

I

I
!
- ' 1...

EMPTY

EMPTY

EMPTY

I....--

'---

L.-..BUFFER S

BUFFER 3

>-----

I

r-L..-

BUFFER 4
FREE FRAME LIST

I
I
.. I

230814-38

Figure 2-22. The Receive Frame Area

2-44

LAN COMPONENTS USER'S MANUAL

SlO

(Bit 10)

S9

(Bit 9)

S8
S7

(Bit 8).
(Bit 7)

S6

(Bit 6)

COMMAND word:
EL
(Bit 15)
S
(Bit 14)

RBD-OFFSET (initially prepared by the CPU and later may be updated by the 82586): Address of the first
RBD that represents the Information Field. RBDOFFSET = OFFFFH means there is no Information
Field.

- The received frame experienced an alignment error.
- The RU ran out of resources
during reception of this
frame.
- RCV-DMA overrun.
- The received frame had fewer
bytes than configured Minimum Frame Length.
- No EOF flag detected (only
when configured to Bitstuffing).

DESTINATION ADDRESS (written by the 82586):
Contains Destination Address of received frame. The
length in bytes is determined by the Address Length
configuration parameter.
SOURCE ADDRESS (written by the 82586): Contains
Source Address of received frame. Its length is the same
as DESTINATION ADDRESS.
LENGTH FIELD (written by the 82586): Contains the
2 byte Length Field of the received frame.

- The last FD on the list.
- The RU should be suspended
after receiving this frame.

LINK OFFSET: Address of the next FD on the list.

0

15
C

B

EL

S

0
(STATUS)

LINK OFFSET

4

RBD-OFFSET

6

1ST BYTE

2ND BYTE

10

DESTINATION ADDRESS

12

NTH BYTE
1ST BYTE

2ND BYTE

14
16

SOURCE ADDRESS

18

NTH BYTE
2ND BYTE

8

LENGTH FIELD

1ST BYTE

20

230814-39

Figure 2·23. The Frame Descriptor (FD) Format

2-45

LAN COMPONENTS USER'S MANUAL

• The LINK OFFSET of each FD in the list should
point to the next FD.

2.9.3 Receive Buffer Descriptor
Format

• The EL bit in the last FDshould be set.
• The RBD OFFSET of the first FD in the list should
point to the first RBD in the RBD list. The RBD
OFFSET in the remaining FDs must be OFFFFH; it
will be later loaded by the 82586 with the address
offset of the first RBD assigned to the frame (unless
the No Resources state is reached).
• The NEXT RBD OFFSET of each RBD in the list
should point to the next one.

The Receive Buffer Descriptor (RBD) holds information about a buffer; size and location, and the means for
chaining RBDs (forward pointer and end-of-frame indication).
The Receive Buffer Descriptor contains the following
fields:
STATUS word (written by the 82586):
EOF (Bit 15)
- Last buffer holding the received frame.
- ACT COUNT field is valid.
F
(Bit 14)
ACT COUNT (Bits 0-13) - Number of bytes in the
buffer that are actually occupied.

• The EL bit in the last RBD should be set.
• The BUFFER ADDRESS and SIZE fields in each
BD should indicate the location and available space
. in a buffer.
Refer to section 5.3 for setting the minimum buffer size.

NEXT RBD OFFSET (written by the CPU): Address
of the next BD in the list of BDs.

2.9.5 Detailed Operation of Receiving
a Frame

BUFFER ADDRESS (written by the CPU): 24-bit absolute address of buffer.

The Channel Interface Module selects the frames destined for the 82586 according to the Destination Address of the frames passing on the link. A frame is selected if it is at least 6 bytes long and its address
matches the Individual Address or Multicast Address
or Broadcast Address. It transfers the selected frames,
with their status, to the RCV-FIFO. RCV-DMA transfers the frames from the RCV-FIFO to memory under
control of the Receive Unit.

ELiSIZE (written by the CPU):
EL
(Bit 15)
- Last RBD in the list.
- number of bytes the buffer is
SIZE (Bits 0-13)
capable of holding.

2.9.4 Initial Structure of the Receive
Frame Area

For every frame, the RU sets up a FD and RBDs in
memory. The loading of each buffer is done by RCVDMA in parallel with prefetching the next buffer by
RU. After completing frame reception, the RU closes
the last RBD and the FD, and sets up the structure for
receiving the next frame.

To enable the 82586 to receive frames, the host CPU
must setup the following structure:
• The RFA OFFSET word in SCB should point to the
first FD on the list.

o

15

r-__L-__
EOF

ACT COUNT
~

o

__~__-L__- L__-L__-J__~~~~__L-__~__~__-L__-L__-L__~(STATUS)
NEXT RBD OFFSET

BUFFER ADDRESS

4

A23
SIZE

230814-40

Figure 2·24. The Receive Buffer Descriptor (RBD) Format

2-46

LAN COMPONENTS USER'S MANUAL

SETUP NEXT FD

9) Initiates RCV-DMA with Next Buffer Address and
Next Size as byte count.

The RU performs the following sequence to setup a
FD:

10) If the EL bit is set, sets END-OF-LAST-BUFFER.

1) Writes a word with B = I, and the remaining bits
set to zero, to STATUS word of the next FD.

ll) Repeats the cycle.

2) If AL-Location configuration parameter is zero,
initiates RCV-DMAwith the address of the first
byte of the DESTINATION ADDRESS and a byte
count of twice the Address Length configuration
plus two.

CLOSE FRAME

When the RU reads an End of Frame from RCV-FIFO
(indicating the end of a received or discarded frame), it
performs the following sequence to close the frame:

3) Saves the address ofthe next FD in the current FD.

1) Reads the status (2 bytes) from RCV-FIFO and
saves it internally.

4) Reads COMMAND word of the current FD and
saves EL and S bits internally.

2) If the RU is not in the READY state, it goes
straight to Completion of Reception sequence.

5) Reads LINK OFFSET word of FD and saves it in
the address of NEXT FD.

3) If the frame status indicates that there is ~ error
(including short frame) and the Save Bad Frame
configuration parameter is zero, or ADDRESS and
LENGTH fields in FD are not full, it reuses the
FD; Backs up Current FD to Next FD, discards
pointer to the current RBD, and goes straight to
step 9.

6) If a buffer has been prefetched, writes the offset
part of its address to the RBD-OFFSET field of the
current FD.
7) If a buffer is not available, reads the RBD OFFSET
word from the current FD and saves it in the Look
Ahead RBD address. If it is all ones, sets internal
END-OF-LAST-BUFFER flag.

4) If the frame included only ADDRESS and
LENGTH fields (i.e. no buffers used) writes 'all
ones' to BD-OFFSET of Current FD.

8) If AL-Location is one, forces a RCV-DMA com.
pletion.

5) If the frame filled at least part of a buffer, writes to
STATUS word of the current RBD: EOF = 1,
F = I, and actual byte count.

9) Goes to the buffer prefetch/transfer cycle.

6) If the RU ran out of resources during reception of
this frame, writes to STATUS word of Current FD:
C = 1, B = 0, OK = 0, S9 = 1, and the remaining bits from the Receive-Byte-Machine.

BUFFER PREFETCH/TRANSFER CYCLE

The RU ·prefetches a buffer according to the Look
Ahead BD address. It also maintains two internal flags
for beginning and end of a cycle.

7) If the RU did not run out of resources, write to
STATUS word of current FD: C = 1, B = 0, and
the remaining bits from the Receive-Byte-Machine.

1) If a buffer is already full, writes F = 1 and current
size to STATUS word of current BD.

8) Requests FR interrupt.

2) Save.s address of next RBD in current RBD and
address of the Look Ahead RBD in next RBD.
Saves Next Size in current size. -

9) If there was no RU-START-REQUEST or RUSUSPEND-REQUEST or S bit and the RU did not
run out of resources, it sets up a new FD (see section 2.10.2).

3) If END-OF-LAST-BUFFER is set, go to 7.

4) Reads RBD-OFFSET from Next BD and saves it
in Look Ahead BD address.

10) Goes to complete reception of frame.

5) Reads 24-bit BUFFER ADDRESS from Next BD
and saves it internally:

COMPLETION OF RECEPTION

Reception completion occurs when the RU encounters
an end of frame (after closing it) regardless of its state
(i.e. also when discarding a frame). The decision on
how to proceed is determined by the following: EL bit,
S bit, RU-START-REQUEST, RU-SUSPEND-REQUEST and whether the RU ran out of buffer descriptors.

6) Reads EL SIZE word from Next BD and saves it in
internal EL bit and Next size.
7) Waits for completion of RCV-DMA.
8) IF END OF LAST BUFFER is set, starts discarding incoming frame and quits.
2-47

LAN COMPONENTS USER'S MANUAL

The following sequence is performed by the RU at Re.ception completion:
1) If the RU ran out of buffers or. Frame Descriptors
during current frame reception, then: change state to
NO-RESOURCES, request an RNRinterrupt,.cIear
RU-SUSPEND-REQUEST and (internal) S bit, and
start discarding.
2) If the received frame was longer than the Minimum
Frame Length, update all four statistics registers (see
details in section 2.8.6). Note that the RSCERRS
statistics register is updateq if the RU is in the NORESOURCES state or if it ran out of buffers during
this frame.
3) If the S bit of current frame or RU-SUSPEND-REQUEST is set and RU-START-REQUEST is not,
then: if the RU is in the READY state, request an
RNR interrupt, and change state to SUSPENDED.
4) If RU-START-REQUEST is set and the Sbit not,
then: change the RU state to READY and perform
Setup new FD.
5) If the RU-START-REQUEST is set and also S bit is
set, perform Setup new FD and change state to SUSPENDED:
' '

out affecting the bytes that are already in RCV-FIFO) .
As soon as space is available, new bytes enter RCVFIFO. The Receive-Bit-Machiile strips the CRC and
Padding (if applicable) and prepares the STATUS word
with bits indicating: occurrence of any error, CRC or
alignment error, DMA overrun, frame too short, or absence of EL flag·(in Bitstuffing). The Receive-Byte-Ma- .
chine enters the. STATUS. word in two consecutive
bytes to the RCV-FIFO.

2.10 BUS INTERFACE
The 82586 can operate on the host CPU local bus as a
bus master with shared status lines. Since status lines
are.in common, all local bus resources (Clock Generator, 8288 Bus Controller, Address Latches and Data
Transceivers) can be shared by the CPU and the 82586.
To facilitate minimum component count designs, the
82586 bus interface has been. optimized for use with an
80186 16-bit microprocessor. The 82586 also interfaces
to the 8086/88 and other processors. Dual port memory configurations can be used to minimize the impact of
82586 bus bandwidth requirements on system performance.

6) If the RU state is different from READY, start discarding.
7) If the RU is in the READY state or just exited it,
then perform the following:
a) Set respective INTERRUPT-IS flags.
b) Deactivate hardware Interrupt signal.
c) Clear interrupt request flags.
d) Update SCB STATUS word according to the new·
state and INTERRUPT-IS flags.'
e) Activate hardware Interrupt signal.

When operating in Maximum Mode (MN/MX pin
strapped to logic zero) pins SO and SI are connected to
the 8288 bus controller, which in turn generates all control signals for the system interface. In this case, the full
address range of 16 megabytes is available.
In Minimum Mode (MN/MX ~trapp~ ~ogic
the 82586 generates ALE, DEN, DT/R, RD and
WR signals. An address space of 4 megabytes is available.
.

~,

The system bus is acquired and released using HOLD/
HLDA protocol directly interfaced tothe 80186. Exter~
nal hardware can be used to convert HOLD/HLDA to
RQ/GT protocol suitable for interfacing to the 8086
CPU.

If a command is being executed by tpe serial machine
(e.g. Configure, IA Set-up,. Dump, etc.) it will ignore
incoming frames during command execution. Thus,
frames can be lost during this time. Conversely, if a
frame is being received, the serial machine will wait
until the entire frame has been received before the command is executed. Section 2.10.5 describes simultaneous Transmit and Receive operation.

When interfacing to a 16-bit bus, data is multiplexed
with the 16 lower address pins. Examples of this mode
are systems with 8086, 80186, 80286 or other 16-bit
microprocessors. On an 8-bit data bus, data is multiplexed with the 8 lower address pins. Examples of this
mode are systems with 8080/8085, 8088 or other 8-bit
microprocessors.

OPERATION OF RECEIVE-BYTE MACHINE
DURING RECEPTION

For every frame that arrives from the Receive-Bit-MaAll bus timing and loading specifications are consistent
chine (after it strips the Preamble and detects the SFD
. with those of the 80186 system. Bus timing and loading
field) the Receive-Byte-Machine decides., according to
specifications are given in the 82586 Data Sheet.
the Destination Address, whether to accept the frame
(see section 2.12). If the frame is accepted, the Receive- .
The 82586 CLK signal input must receive MOS level
Byte-Machine trans(ers the Destination Address,
inputs. The 82586 can operate with an 80186 or a 8086Source Address, Length Field and Data field to RCV1 using an 8 MHz 50% Duty CycIe clock (full performFIFO. If it is not accepted, nothing enters RCV-FIFO.
ance), or with a 5 MHz 8086 using a 5 MHz 30% Duty
If RCV-FIFO overruns, the Receive-Byte-Machine
CycIe cIock (reduced performance).
keeps overwnting the input buffer of RCV-FIFO (with2-48

LAN COMPONENTS USER'S MANUAL

The 82586 outputs status (SI and SO) to provide typeof-memory-cycle information to the 8288 Bus Controller in Maximum Mode or in Multibus Configuration.
The 8288 generates memory read and write commands,
and issues control signals to the address buffers and
data transceivers. The 82586 provides RD, WR and
ALE signals for memory transfers in Minimum Mode.
A multi-master system bus can be constructed using the
8289 Bus Arbiter. The key arbiter inputs are the same
as for the 8288: local status lines S1 and SO.

2.10.1 Memory Addressing and
Organization
The 82586 addresses memory as a linear sequence of 16
megabytes. It establishes transfers as l6-bit words when
it is used with an 8086/80186/80286 or as 8-bit bytes
using an 8088 or other 8-bit processors.
As a Master Peripheral with the 8088, the 82586 treats
memory as a single bank (D7-DO) of 1M 8-bit bytes
addressed by address lines AI9-AO. Address lines
A23-A20 are not used, BHE is strapped HIGH.

Operation of the 82586 is structured so that all command, status and data flow is via memory. Therefore,
the 52 status line of the 8086 and 80186 families is not
required and is not provided by the 82586. With the
exception of SCP, which is always read from location
OFFFFF6H, there are no transfers to/from a fixed address system resources (I/O memory).

When operating with the 8086/80186, the 82586 treats
memory as a high bank (DI5-D8) and a low bank
(D7-DO) of 512K 8-bit words addressed in parallel by
AI9-AI. The 82586 performs Reading/Writing from/
to full word locations only. The BHE line is always
LOW. Word transfers are restricted to even addressing,
although the 82586 does not enforce pin AO to LOW.
When attempting to write to an odd location (i.e. when
an odd buffer address is set), the odd address will be
output to the address lines, but a full word will be output to the data lines, in which the low byte will be
undefined. The manner in which line AO being HIGH
is treated is system dependent. The data words flow
through pins DIS-DO.

READ

The read cycle begins at tl by generating the address.
The memory read command signal (MRDC from the
8288) is asserted at t2. This command causes the addressed device to enable its data bus drivers onto the
system bus. Some time later, valid data will drive the
READY line HIGH. The data will be sampled by the
82586 at t4. If the READY line is still LOW in t3, then
tW cycles are inserted between t3 and t4 until the
READY line goes HIGH. When the MRDC signal returns to the HIGH level, the addressed device will
again tri-state its data bus drivers. If a transceiver
(8286/8287) is required to buffer the local bus, the direction (DT/it) and enable (DEN) controls are provided by the 8288 Bus Controller (or from the 82586) ..

The Chart below summarizes the operation of BHE
and AO signals:
BHE

AO

o
o

0 whole word
1 system dependent
o lower byte to/from even address
1 upper byte to/from odd address

WRITE

When operating with the 80286, the full 16 megabyte
address space is available. It has the same characteristics and restrictions as the 8086/80186.

A write cycle begins by generating the address during
t 1. At t2 the processor generates data to be written.
This data remains valid until the middle of t4. During
t2, t3 and tW, the advanced memory write command
(AMWTC) from the 8288 is asserted, while the normal
memory write command (MWTC) is asserted during t3
and tW only. MWTC is used by older memories requiring valid data prior to the write command.

The 82586 accesses all control information from a segmented memory structure. The 16-bit pointers residing
in the various structures are used as an offset to a 24-bit
base location. Hence, all FD, RBD, CB, TBD, SCB
structures must reside in 64K byte boundaries. Data
buffers may reside anywhere in address space, and are
directly addressed as a 24-bit address.

SYNCHRONIZATION WITH LOWER SPEED
MEMORIES

2.10.2 Bus Operation

The 82586 uses the standard READY mechanism to
work with memories having long access times.

Each memory transfer cycle consists of at least four
CLK cycles. These are referred to as tl, t2, t3 and t4.
The address is generated by the 82586 beginning at tl,
and data transfer occurs on the bus during t2 through
t3. In the event that a READY indication is not received from the addressed memory, WAIT states (tW)
are inserted between t3 and t4. Each inserted WAIT
state has the same duration as a CLK cycle.

As bus state t3 is reached, the READY signal is tested.
While the READY signal is LOW, wait states (tW), are
added and all control signals are stretched accordingly.
While in wait states, (tW), the READY signal is tested
at every clock cycle. The first time that READY is
found to be HIGH, state t4 is entered, finishing the bus
cycle.
2-49

LAN COMPONENTS USER'S MANUAL

In a synchronous environment, the user is able to guarantee setup and hold times for the READY signal related to the system clock. Synchronous READY input is
chosen and the number of wait states is predictable.

The 82586 does not hold the bus unless it is doing
memory transfers, with one exception. At the end of a
received frame, the 82586 starts post-frame processing,
which includes posting Status for the recently received
frame and getting ready for the next frame to be received.. All these processes have to be completed such
that Interframe Spacing requirements (9.6 /Ls for IEEE
802.3) are met. To be able to do that,. the 82586 may
hold the bus for 173 clock periods (Typical value for
AL-LOC = 0, SAV-BF = 0). The chip, however, does
not really use the bus for entire 173 clock periods for
post-frame processing. About 66 of the 173 clock periods are not used (no Read or Write operations). The
chip simply holds the bus for 173 clock periods in anticipation of the next frame which may come in after the
IFS time (9.6 /Ls) in the worst case (see Figure 2-25). If
the RU finds that the next frame is not coming in immediately, then the 82586 will release the bus after 173
clock periods. If the next frame is coming in, the chip
will hold the bus even longer and transfer the first part
of the next frame into memory. In this case, receive
data DMA will be 'interleaved with receive control
DMA. The system design must not interpret postframe processing as a fault condition.

For asynchronous environments, the user is not required to provide precise setup and hold times for the
READY signal. A high speed resolution circuit synchronizes the asynchronous READY input internally
to the 82586. Setup and hold times for the asynchronous READY input are not required for correct operation but for recognition at a certain clock. The number
of wait states is therefore not always predictable.
Synchronous READY input is sampled by the 82586 at
the beginning of t3. Setup and hold time requirements
refer to the falling edge of the CLK when entering 13
state.
Asynchronous READY input is synchronized by the
82586 in the middle of t2. Setup and hold times refer to
the rising edge of the CLK while in state t2.
In Minimum Mode, the 82586 has one input READY
pin, SRDY/ARDY. This pin is software programmable to work as either synchronous or asynchronous.
Upon RESET, the 82586 automatically defaults to
asynchronous mode. The CONFIGURE command is
used to program the circuitry to synchronous or asynchronous READY.

The CPU can force the 82586 off the bus by removing
HLDA. The 82586 will complete the current bus transfer and will relinquish the bus within a maximum of
four clock cycles in Word mode or eight clock cycles in
Byte mode, see Figure 2-26. However, if the 82586 still
has some pending transactions, the Hold will be activated again after I clock cycle (minimum hold drop
time is I clock cycle).

In Maximum Mode the SRDY/ ARDY pin behaves exactly as in Minimum Mode. In addition, the READY
pin provides an alternate synchronous READY connection. Internally, the 82586 performs a logic OR
function, between the SRDY/ ARDY pin and the
READY pin.

READY TIMEOUT

2.10.3 Bus Acquisition

The 82586 Ready input is sampled during DMA opera"
tions. If a system error (e.g. RAM error) causes the
Ready to not be returned to the 82586, the 82586 will
indefinitely hold on to the bus. A removal of HLDA
will not make the 82586 release the bus under these
conditions (typically, the 82586 gives up the bus within
3 clock cycles of HLDA. going inactive). The system
designer must incorporate some external logic to detect
the 'Ready Absence' condition and reset the 82586 in
such an event. In addition, the CPU must initiate some
recovery procedures (e.g. RAM test) to isolate the
problem and follow up with remedial procedures.

The system bus is acquired and released by means of
the HOLD/HLDA protocol.
When the 82586 needs the bus, it activates the Hold
signal. Upon receiving the HLDA, it initiates bus transfers. At the end of bus transfers, it relinquishes the bus
by deactivating the HOLD and, subsequently, the host
takes away the HLDA.
Figure 2-25A shows the number of clocks the 82586
requires after getting an HLDA before it starts a bus
transfer.
IF"S TIME (9.6,uSEC)

=
HOLD

~)-----------------------------------FRAME (N)
' ........ __ ........ ~R~~E..~!!J_

...................... .

-f?3

~ __________ /

CLOCK PERIODS (TYPICAL) -

RECEIVE END OF FRAME PROCESSING\

INT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

\

\

\

Lf....!......!-'!

\

\

\

\

FRAME (N) RECEIVED

INTERRUPT

Figure 2·25. Receive End of Frame Processing

2-50

\

230814-16

LAN COMPONENTS USER'S MANUAL

HOLD

HlDA

230814-41

Figure 2·25A. HOLD/HLDA: Bus Transfer Timing
I,

ClK

I,

I, •

,

I:

I

HOLDA--j,--i'1)~I~I~lt'tl~IZI1/Jl~1~1[tr/~IZI1i~I~I~I~7Z717~1~'7~/;~j__-L____
-:

HOLD

:-T16

.

T15--i

I '

~

--------------------------------------~J
T2S-l

r::--

230814-42

Figure 2·26A. 82586 Byte .Mode Bus Relinquish Timing
I,

13

ClK
HOLDA

I

I,
I

I

I

I

-!--"j:~'g:r;Z::
,\7 I JZ1±:
I l l 7cz::~'
I 7 7~~'
7 >!~':--...i__...i_
-l

~T16

T15~ '-

230814-43

Figure 2·26B. 82586 Word Mode Bus Relinquish Timing

IBRQ: Internal Bus Request. Any internal demand to
perform . bus transfers on the bus: Receive or
Transmit DMA, CU or RU_
STD: Special state different from tl, t2, t3, tW and t4,
for which the 82586 masters the bus, but no transfers are performed (ALE, RD, WR are inactive in
Minimum Mode or SO, SI are inactive in Maximum Mode).
SPT4: State prior to t4. May be t3 for zero wait states
or the last tW for any number of wait states.
BM: Configured to 8-bit bus width.
MAO: Memorized AO. AO was true during the last t1
(Odd-Address bus cycle).

DETAILS OF THE HOLD/HLDA PROTOCOL

The state diagram of Figure 2,27 defines the states and
excitations of the bus acquisition protocol.
STATES:
NO BUS REQUEST: The 82586 is not requesting the
bus via HOLD, because Internal Bus Request
(IBRQ) is not pending, or when the IBRQ arrived,
HLDA level was HIGH.
BUS REQUESTED: The 82586 has issued HOLD (bus
request). HLDA is LOW, i.e. bus was not yet
granted.
BUS MASTER/TRANSFERS PERFORMED: The
82586 owns the bus and performs transfers.
BUS MASTER/NO TRANSFERS PERFORMED:
The 82586 owns the bus, but does not use it for
transfers. This is used by the 82586 to lock the bus
for a few system clock cycles for READ/MODIFY/WRITE operations, or when the 82586 knows
that it will need the bus soon (e.g. when buffer
switching occurs).

The following algorithm is followed regarding bus acquisition.
1) RESET sets the 82586 to the NO BUS REQUEST
state.
2) The internal bus request raises HOLD output and
switches the state to BUS REQUESTED. HLDA
input, being LOW, enables this switch of state. The
reason for this condition is to differentiate HLDA
being HIGH as a result of the previous bus cycle
from newly generated HOLD acknowledge.
3) Appearance of HLDA sets the state to BUS MASTER/TRANSFERS PERFORMED. The bus is acquired and read/write operations are started.

EXCITATIONS:
RESET: Software or Hardware Reset initializes the
machine.

2-51

LAN COMPONENTS USER'S MANUAL

HlDAlHOlD

(IBRO + HlDA)/HOi]i

IBRO + HlDAlHOlD (2)
RESET

(1)

HlDAlHOlD

STD + HLDAlHO~D

(SPT4 + 8M + MAO)/HOlD

230814-44

Figure 2-27. The HOLD/HLDA Handshake

4) Prior to entering bus state t4, the 82586 evaluates the
next action: If HLDA input is active and there are
pending internal bus requests, the state remaiJ1s BUS
MASTER/TRANSFER~ PERFORMEp. Back to
back bus cycles result. If HLDA is deactivated or no
more internal bus requests are present, the 82586
switches to NO BUS REQUEST state.
5) State BUS MASTER/NO TRANSFERS· PERFORMED is entered for all cases that no internal
bus request exists but performance considerations require holding the bus until the request shows up.

The transactions involved in bus acquisition and release
imply overhead resulting in losing system clocks due to
signal propagation delays and sample time requirements. For many short DMA bursts, up to 5 clocks are
lost due to this. switching. On the other hand, long
DMA bursts imply that bus Ij1asters, other thllll 82586,
may experience long delays in bus acquisition. Thus, an
optimal FIFO-Threshold setting exists.
The 82586 provides a means for choosing the optimal
setting required by the user's application, using the
FIFO-Threshold configuration parameter. See section
5.2 for guidelines for setting the FIFO-Threshold.

2.10.4 FIFO-Threshold Mechanism
TRANSMIT FIFO OPERATION

The on-chip Receive and Transmit FIFOs proviqe buffering between the serial channel and system bus. On the
system side, data is written into the Transmit FIFO or
read from the Receive FIFO, using the 82586 DMA
data channels. The Transmit DMA bursts fill the
Transmit FIFO at the bus data rate. The 82586 Channel Interface Module pulls bytes of data from the
Transmit FIFO and transmits to the link at the serial
bit rate. The Receive FIFO operates analogously, filled
by the Channel Interface Module and emptied· by
bursts for Receive DMA channel.

Starting from an empty Transmit FIFO, the transmit
DMA starts reading memory locations, and pushing
bytes into Transmit FIFO. The Channel Interface
Module starts transmitting on the link, pulling bytes
from the Transmit FIFO, at the serial bit rate. Because
the data system (byte) rate is faster than the serial's, the
Transmit FIFO will eventually become full. At this
point, the DMA burst stops.

2-52

LAN COMPONENTS USER'S MANUAL

Meanwhile, the Channel Interface Module continues to
transmit, thus emptying the FIFO. When the number
of bytes in the Transmit FIFO equals the configured
FIFO-Threshold, the system bus is requested for a new
DMA burst. If the bus is not acquired fast enough, the
Transmit FIFO will be emptied by the Channel Interface Module and a Transmit FIFO underrun occurs.
The optimal value for the FIFO-Threshold is such that
it guarantees bus acquisition before underrunning the
FIFO, and at the same time provides the longest possible burst.

CA acceptance and SCB status update, CB execution,
TBD prefetch. RU related activities are: CA acceptance, SCB status update, FD setup, RBD prefetch, end
of receive frame processing. In the case that two or
more channels require the system bus simultaneously,
an arbitration mechanism located in the bus interface
unit allocates the channels and determines priority between various requests.

TRANSMIT PROCESS
During Transmit operation, the CU prefetches the next
Transmit Buffer Descriptor while the current data buffer is being read by the Transmit DMA channel. In order to minimize disturbances to the data rate, and to
avoid a Transmit FIFO underrun, any two CU operations are separated by at least two data reads (if requested).

When the bus is acquired, the new Transmit DMA
burst continues until the FIFO is full. This mechanism
can be viewed as an hysteresis process, with the upper
bound Transmit FIFO full and the lower bound the
programmed FIFO-Threshold.

RECEIVE FIFO OPERATION
RECEIVE PROCESS

At the beginning of frame reception, the Channel Inter.
face Module writes into the Receive FIFO.

During reception, the RU prefetches the next Receive
Buffer Descriptor while the current data bUffer is being
written by the Receive DMA channel. As in the case of
transmit, any two RU operations are separated by at
least two data writes. This rule minimizes disturbances
to the data rate and helps to avoid Receive FIFO overruns.

When the number of bytes in FIFO equals 15 minus
FIFO-Threshold, the system bus is requested. This
mechanism allows for a delay in bus acquisition equal
to the number of empty bytes left in the Receive FIFO.
If the bus is not acquired in time, a receive overrun
occurs. The system bus is released when the Receive
FIFO is emptied by the Receive DMA. Further acquisition of the bus starts when the Receive FIFO contains
a number of bytes equal to 15 minus FIFO-Threshold.
The mechanism is analogous to the Transmit FIFO.

SIMULTANEOUS RECEIVE AND TRANSMIT
OPERATION
There are two cases where Transmit and Receive DMA
channels work simultaneously.

NOTE:
In the case of a Receive FIFO overrun, the Charinel
Interface Module keeps overwriting the input buffer to
the FIFO, and the bytes get lost. A special status will
indicate this condition.

In Intemal/Extemal Loopback configuration, both
channels operate simultaneously, on an equal priority
basis. Furthermore, CU or RU memory cycles are also
interleaved with the same priority as Transmit and Receive. Effectively, if three sources compete for the bus,
they operate on an interleaved basis.

2.10.5 Bus Cycle Interleaving
The 82586 has four independent on-chip DMA channels:
• Receive DMA channel. Used for writing received
frames to memory.
• Transmit DMA channel. Used for reading transmit
frames from memory.
• CU input/output channel, used for CU read and
write operations.

The second case of simultaneous Transmit and Receive
occurs when the receive frame arrives whiie the CU is
setting up a transmission. The Transmit process continues simultaneously with Receive until the Transmit
FIFO fills. As in Loopback, Transmit and Receive
DMA prioriiies are equal. As soon as the receive frame
ends, Transmit resumes operation.
The 82586 will interleave command related operations
with receive related operations according to the rules
described below.
• Control transfers (interaction with the System Control Block, Command Blocks, Receive Frame Descriptors and Buffer Descriptors) and data transfers
(interaction with Data Buffers) are interleaved re-

• RU input/output channel, used for RU read and
write operations.
Receive and Transmit DMA channels operate in bursts
controlled by the FIFO-Threshold mechanism. The CU
and RU channels initiate single read, or write operations
as dictated by CU and RU activities. CU related activities are: CU Initialization, SCB processing including
2-53

LAN COMPONENTS USER'S MANUAL

• Transmit or, Receive Buffer Switching; To minimize
the danger of Transmit FIFO underruns or Receive
FIFO overruns.

gardless whether the transfers pertain to command
or received operations. Two data transfers are executed for each control transfer.
• Data transfers to command and receive operations
occur concurrently,' on an alternating basis (one
transfer in each direction).
• Control transfers related to receive operations have
priority over command operations. In other words,
command control transfers are suspended or delayed for as long as necessary to complete pending
receive control transfers.
• Receive data transfers; command data transfers, and
control transfers can occur concurrently. There will
be one data transfer in each direction of each control
transfer.

2.10.6 CPU/82586 {CAli NT)
Handshake·
The INT pin is used to notify the CPU about one or
more of the following events:
• A Command Block with its 'I' bit set was executed
(CX interrupt).
• A frame was received (FR interrupt).
• The CU became Not Active (CNA interrupt).
• The RU became Not Ready (RNR interrupt).

Consider the following example. Assume the 82586 is
in the process of receiving a frame. The CPU wants to
have a frame transmitted and activates Channel Attention.'

82586·INTERRUPT REQUEST SEQUENCE

Once an event requiring an interrupt has occurred, the
following sequence is performed by the 82586:
I) INT pin is set to its low level (inactive).
2) The status word in SCB is written, denoting the
source of the interrupt (CX, FR, CNA or ,RNR,interrupt), together with the states of the CU and RU.
3) INT pi~ is raised (set to active).

While writing the received frame into system memory,
the 82586 will concurrently read the appropriate command control information (SCB, Command Block, aIld
TBD). If the 82586 needs to execute receive control
transfers (beginning-of-frame processing, buffer lookahead, end-of-frame processing), it delays command
control transfers. Two receive data transfers are executed for each (receive or command) control transfer.

82586 RESPONSE TO CA

The CU is responsible for control comlIland acceptance, following the trailing edge on CA input. The CU
will first fmish all its higher priority activities and only
then accept the control commands.

When all control transfers related to the transmit command are completed, the 82586 will begin executing
transmit data transfers. One transmit data transfer will
be e,xecuted for each receive data transfer, a transmit
data transfer and a receive control transfer (not necessarily in that sequence). Transmit data. transfers will
stop when the Transmit FIFO is filled up.

Higher priority CU activities that delay CA aCceptance
are:
a. Transmit Buffer Descriptor prefetch
b. Transmit buffer switching
c. Current Command Block completion

HOLDING THE BUS

In special cases, the 82586 does not release the bus,
even though no specific reads or writes are' executed.
The purpose of this operation is to avoid bus acquisition and release dead tinies if several input/output operations ,are required. Another reason is to guarantee
'82586 performance in critical timing cases.

The 82586 will. accept a CA prior to the setup of the
n~lIt CB in the CBL.

The 82586 holds the bus in the following cases:
• RBD Prefetch. The bus is not released between two
consecutive bus a~sses to minimize prefetch time.
This is important since minimum buffer length is
strongly dependent on the time it takes the 82586 to
prefetch a RBD.
• TBD Prefetch. AnalogoiIs to RBD Prefetch.
• Receive End of Frame Processing. The bus is not.
released throughout this process to ensure only one
bus request.
2-54

The CU recognizes an RU control command and notifies the R U. The R U will firSt finish all its higher priority activities, and only then accept the control command.
Higher priority RU activities that delay CA acceptance
are:
a. Receive Buffer Descriptor prefetch
b. Receive buffer switching
c. Receive end of frame processing
Only after the CU and RU have accepted the control
command, the SCB command word is cleared. At that
time, the CPU may issue the next CA to the 82586.

LAN COMPONENTS USER'S MANUAL

Internally to the 82586, the CA trailing edge is detected
and latched. Prior to reading the SCB control command, the 82586 clears the latch. A new CA, given to
the 82586 before the SCB command word is cleared,
may be lost due to its being cleared before serviced. The
user must refrain from such violations.

same limitation of the clock HIGH time as the Manchester encoded data. When Transmit data is idling, the
TXD pin is held HIGH (logic '1').

Upon detecting a falling edge on its CA input, the
82586 performs the CA acceptance sequence, as follows:
1) Determine which interrupt requests were acknowledged by the CPU. For each of them, clear the corresponding interrupt request bit in SCB status word.
2) Perform the control command acceptance procedure.
3) The INT pin is set LOW.
4) Write the SCB status word indicating the unacknowledged interrupt requests, and newly generated
interrupt requests, together with CU and RU states.
5) If any interrupt request bit is active, set the INT pin
to HIGH.

The Manchester/NRZ configuration parameter does
not apply to the Receive data. The 82586 requires NRZ
Receive data. Manchester data decoding is accomplished externally (the 82501 chip for IEEE 802.3). The
Receive Clock can be presented to the 82586 in two
ways:

The 82586 accepts an external Receive Clock, RXC,
that strobes the incoming Receive Data signal, RXD.

• all the time
• only during the Receive frame
In the case of Receive Clock only during Receive
frame, the RXC pin should be held inactive when no
Receive frame exists.
Receive Clock frequencies can be from 100 KHz to
10 MHz with HIGH time not longer than 1000 nanoseconds.

The 82586 does not wait for reception or transmission
to end in order to process a CA. The SCB related operations will be carried out on an interleaved basis with
the transmission or reception process.

2.11.2 Carrier Sense
Carrier Sense is an indication of activity on the link, i.e.
a signal from a transmitting station has reached this
station. The 82586 can be configured to either accept it
externally, or generate Carrier Sense internally (for Serial Interface Devices that generate Receive clock only
during actual reception). The internally generated Carrier Sense occurs when the Receive Clock is present.

2.11 NETWORK INTERFACE
HARDWARE
The Network interface supports bit encoding, carrier
sense, collision detection, link acquisition, and loopback.

When transmitting, 82586·behavior related to Carrier
Sense is as follows:
• When ready to transmit, and if Carrier Sense is active, the 82586 defers.
• When CRS goes inactive (CRS is synchronized to
the transmit clock), the 82586 sets its Interframe
Spacing (IFS) timer.
• When the IFS timer expires, the 82586 initiates its
transmission regardless of the state of CRS.
• The 82586 will abort transmission if CRS goes inactive anytime after it transmits the preamble. An
override option is available.

NOTE:
.The 82586 Receive-Byte-Machine and Receive-BitMachine are clocked by the Transmit Clock. Thus the
Transmit Clock must be constantly applied to the
82586.

2.11.1 Encoding/Decoding
The 82586 receives an externally generated Transmit
clock at the transmission bit rate. Data is transmitted in
either NRZ (binary) or Manchester encoded form, depending on the chip configuration.

When receiving, the 82586's behavior related toCRS is
as follows:
• The 82586 starts the IFS timer when CRS goes inactive. The receiver is insensitive to external signals
during the time-out.
• Carrier Sense being active any time other than during the IFS time causes the 82586 to sample its Receive Data input at a rate determined by the Receive
Clock.

Due to the semi-static nature of the 82586's internal
circuits, the Transmit clock HIGH time should not be
longer than 1000 nanoseconds. Manchester encoded
data requires 50% clock duty cycle. Therefore, when
the 82586 is configured to' perform Manchester encoding, the Transmit Clock frequency must be between
0.5 MHz and 10 MHz.
In the case of NRZ encoded data, Transmit Clock frequency can be from 100 KHz to 10 MHz, with the

2-55

LAN COMPONENTS USER'S MANUAL

• When receiving, the 82586 samples the data on the
falling edge of the Receive Clock after CRS becomes
active.

2. 11 ~3 C.ollision Detection

Carrier Sense signal going active edge can be asynchronous to both Receive and Transmit Clocks.

Collision detection is usually done external to the
82586, typically by the Transceiver. An internal filtering mechanism prevents acceptance of a Collision Detection signal shorter than a configurable number of
TCLK units (from 0 to 7).

The 82586 requires five bit times from the instant the
CRS pin goes active to achieve internal synchronization
with the received bit stream. The sixth bit is the first bit
sampled as data. In the End of Carrier frame delimiting
method, the 82586 hunts for the SFD field (10101011).
Conversely, if two consecutive '0' bits are detected before the SFD field, the frame is aborted.

The 82586 only looks for collision detect while actively
transmitting, i.e. the first bit of the preamble has been
transmitted. The collision is synchronized and recognized internally within a maximum of 4 Transmit
Clock times after collision detection pin goes active.
The 82586 can be configured to cease transmission
upon active Carrier Sense, instead of Collision Detect.
This capability is called Internal Collision Detect. Internal Collision Detect is useful in two cases:
1) In conjunction with a class of transceiver that generates a Receive Data signal equal to the difference
between the signal carried by the channel and the
transmitted signal.
2) For point-to-point interconnection without using
collision sensing transceivers. For exa,uple, collision
detection could be realized by ANDing the RTS signal of each 82586, the result then tied to CRS of
each 82586.

To have a clean frame closure, CRS signal going inactive edge should be synchronized to Receive Clock.
Carrier Sense can be configured to undergo filtering to
ignore negative going glitches. The filter is programmable to a number of bit times (0-7) that must be exceeded before the signal is considered valid. To be classified
as a glitch, the glitch must meet set-up and hold times.
CRS is synchronized to the Transmit Clock.
Figure 2-28A shows a negative going glitch on CRS. If
the glitch lasts shorter than the filter setting, it will be
filtered, and the IFS timer will not start on the rising
edge rifCRS.

SQE TEST

-.-1/

Some transceivers (IEEE 802.3 compatible) generate
the SignalQualityError Test, SQE TEST, (or 'heart
beat') signal after the completion of each transmission
to indicate proper operation of, the collision deteCtion
circuitry. The SQE TEST signal is issued on the Collision Detect line, and is a 10 MHz signal, 10 ± 5 bit
times in length. The 82586 checks the Collision Detect
line for the SQE TEST for the duration of an Interframe Spacing after completion of transmission. The
status of the next transmitted frame reports on the presence or absence of the SQE TEST.: The SQE TEST
mechanism is only meaningful if the 82586 is configured to external collision detect.

CRS - - - - - \_ _ _ _

230814-45

Figure 2-28A. The CRS Filter Stops Negative
Going Glitches: the IFS Timer
Does Not Become Active

Figure 2-28B shows a positive going pulse, which will
not be filtered. Ai point 1, the CRS inactive will initiate
the IPS timer and the 82586 will not respond to external signals for the IFS period. See section 2.12.3.

See section 2.12.3.

2

2.11.4 Serial Link Acquisition

230814-46

The handshake between the 82586 and the Ethernet
Serial Interface during transmission is accomplished
with 'Request-to-Send' (RTS) and 'Clear-to-Send'
(CTS) signals. RTS provides a means for turning on the
Ethernet Serial Interface prior to actually sending bits.
CTS is the means by which the Ethernet Serial Interface confirms that it is ready. It is also an externai
means for implementing a watchdog timer.

Figure 2-28B. The CRS Filter Passes Positive
Going Glitches: the IFS Timer
Becomes Active at Point 1

Positive going CRS glitches cause the 82586 back off
timer'to start; the 82586 will not respond to any external signal for the IFS period.

2-56

LAN COMPONENTS USER'S MANUAL

Address Checking and Minimum Frame Size Checking
are always performed by the 82586, even in loopback
mode.

When the 82586 is ready to place bits on the serial link
and CRS is inactive, it asserts RTS and awaits CTS.
Actual transmission starts within 1 transmit clock time
after CTS rises. If it loses CTS prior to end of frame,
transmission is aborted and error status is raised. An
Ethernet Serial Interface that does not require this
handshake may ground CTS (Intel 82501). The 82586
deactivates RTS after transmission is completed.

The Intel 82501, Ethernet Serial Interface, has a Loopback (LPBCK) pin which if activated disconnects the
82501 from the Transceiver Link and transmitted data
is fed back to the 82586. This mode enables diagnosing
the 82501 without the Transceiver.

The 82586 can operate with Serial Interface Devices
that either do or do not return Ca~rier Sense during
transmission. The 82586 must be configured to one of
the two cases. If configured to expect Carrier Sense,
then transmission will stop if Carrier Sense goes inactive (and after the preamble). If configured to transmit
on no CRS, then the 82586 is indifferent to Carrier
Sense going inactive.

2.11.6 Interframe Spacing Timer
At the end of a transmission the Interframe Spacing
Timer is triggered by the later of two ·events:
a. The last bit has been transmitted, or
b. Carrier has dropped.

2.11.5 Loopback

This rule applies regardless of whether the entire frame
was transmitted or the transmission was aborted due to
a collision and the jam sent. In the latter case, the
82586 is sensitive to other stations not having completed their transmissions even after the 82586 has completed its jam; the 82586 defers until the channel goes
'not busy' and then sets the IFS timer.

The Loopback Modes are called by setting the respective configuration bits.
If both bits are set, Internal Loopback Mode is valid,
and overrides External Loopback. In Internal Loopback Mode, the 82586 is logically disconnected from
the Serial Interface Unit, therefore, the 82586 does not
monitor link activity. The 82586 connects the Transmit
Data to the Receive Data Signal, and· Transmit Clock
to the Receive Clock. To avoid FIFO overruns and underruns, bit processing is performed at one quarter
TXC frequency. The 82586 divides the Transmit Clock
internally. The Receive Bit machine is clocked by TXC.
During Internal Loopback, NRZ data Encoding Mode
is used regardless of the data encoding configuration
bit. There is no limit to the number of data bytes looped
back.

This rule applies whether or not the 82586 is configured
to expect carrier sense while transmitting; also, whether
or not it is configured for internal collision detection as
discussed in section 2.11.3.

2.12 CONFIGURATION PARAMETERS
The 82586 provides a high degree of flexibility via programmable parameters. This section summarizes the
configuration parameters that may be modified (using
the CONFIGURE command). Refer to section 2.S.4
for a summary of default settings.

Ethernet Serial Interface and Transceiver diagnostics
may be performed by configuring the 82586 to External
Loopback. External Loopback Mode is performed at
full link speed. Therefore, to avoid receive overruns, the
frame length should be limited to a value that is a function of several parameters such as link speed, Preamble
length and transceiver cable length. A frame of 18
bytes, including address type and CRC bytes, is guarante·ed by chip design, not to cause overrun. See section
2.12.5.

2.12.1 Framing Parameters
PREAMBLE LENGTH (2 BITS)

Determines the length, in bytes, of the Preamble (including the SFD field).
00
2 bytes

In external loopback the 82586 can receive a frame
from another station provided the 82586 detects carrier
before it starts executing the Transmit command associated with loopback. The 82586 behaves as in the normal case of a pending transmit while a frame is being
received.

01
10
11

4 bytes
8 bytes
16 bytes

For IEEE S02.3, these bits should be programmed to
lOB (8 bytes). Preamble lengths other than 64 bits may

The 82586 will only be able to receive a frame transmitted to itself (i.e. destination address = source address,
or set to Promiscuous mode) in the loopback mode.

2-57

LAN COMPONENTS USER'S MANUAL

be tailored to particular networks. The preamble length
is determined by the worst-case number of transceivers
a frame passes before it reaches the destination.

In the bitstuffing mode, the 82586 checks for the entire
HDLC flag pattern (01111110), 7EH, before accepting
it as a valid flag. Only one flag is allowed following the
preamble bits. Two consecutive flags will be interpreted
as a beginning and a closing flag to the 82586, i.e. a
frame with no data.

ADDRESS LENGTH (3 BITS)

Determines the length, in bytes, of the address referred
to by the 82586. This parameter applies to Individual,
Source, Destination, Multicast, or Broadcast Addresses. An address length of 7 is treated as zero.

The Bitstuffing/Flag technique offers high reliability,
especially for networks susceptible to line ringing.
PADDING (1 BIT)

NOTE:
The Individual Address is set using the lA-SETUP
command, Multicast addresses are set using the MCSETUP command.

If padding is set, those frames shorter than the Slot
Time will be padded with HDLC flags to the shortest
frame that is longer than Slot Time (during transmission). Valid for Bitstuffing only. In End of Carrier
framing, padding must be provided by user software.
o Frame not padded
Frame padded (only in Bitstuffing)

BROADCAST DISABLE (1 BIT)

Disables reception of frames with a Broadcast destination address or l<1ulticast addresses of 'all ones.' The
Promiscuous Mode setting overrides the Broadcast disable.
o Broadcast enabled
Broadcast disabled

MIN-fRAME-LENGTH (8 BITS)

Specifies the minimum frame size, in bytes. No frame
that is shorter than the minimum will be accepted by
the 82586. The 82586 does not accumulate statistics on
short· frames, and discards them if not configured to
Save Bad Frames. NOTE: apart from this mechanism,
there are other limitations on the minimum frame
length:

CRC-16/CRC-32 (1 BIT)

Specifies which CRC polynomial is used for CRC generation and checking;

o

32-bit Autodin - IICRC
l6-bit CCITT CRC

First, frames that are shorter than 6 bytes (even in Save
Bad Frame Mode, Promiscuous Mode, Address Length
of Zero) are discarded. No status is reported on such
received frames.

The 32-bit Autodin-II polynomial is X 32 + X26 +
X23 +X22 + X16 + Xl2 + Xii + XIO + X8 + X7
+ X5 + X4 + X2 + X + 1.

Second, for AL-LOC = 0 (when Address Control Location implies data separated from control), also frames
shorter than 2 X ADDR-LEN + 2 (not including the
Frame Check Sequence) are discarded.

The l6-bit CCITT polynomial is X16 + XI2 + X5 + 1.
NO CRC INSERTION (1 BIT)

For the IEEE 802.3 specification, this parameter
should be set to 64. Transmission time of the 64 bytes
ensure collision detection.

Specifies whether or not the CRC is inserted after the
information field during transmission. This capability
allows CRC generation external to the 82586, enabling
the user to verify the CRC checking mechanism during
reception. The 82586 always checks for a valid CRC
(CRC check cannot be disabled).
o CRC is inserted
CRC is not inserted

In slower or short topology networks, a shorter minimum frame size may be desirable to reduce channel
overhead.

2.12.2 Link Management Parameters

BITSTUffING/EOC (1 BIT)

INTER fRAME SPACING (8 BITS)

Specifies the frame delineation method.
o End of Carrier Framing (IEEE 802.3 compatible)
Bitstuffing Framing (HDLC like)
1-

Specifies the time period (in TCLK units) that the
82586 must defer after detecting that Carrier Sense is
inactive. The minimum value is 32, any value less than
that defaults to 32.

2-58

LAN COMPONENTS USER'S MANUAL

SLOT TIME (11 BITS)

EXPONENTIAL BACKOFF METHOD (1 BIT)

Specifies Slot Time for the Network (in TCLK units).
Zero is interpreted as 2048. This value is used in calculating Backoff and Linear Priority delays. Itmust be
longer than the maximum round trip time of a frame in
the network plus jam time.

This parameter determines when to start the back off
time out:
o
Immediately after jamming or concurrent
with Interframe Spacing. According to the
IEEE 802.3 specification.
After deferring period expires (short topology).

For IEEE 802.3, Slot Time should be set at 200H corresponding to 51.2 /ks. However, it may be programmed
to any number between I and 211.
The user may change the Slot Time to optimize the
network to specific application environments., For
many applications, like serial backplanes, this number
will be significantly smaller than for IEEE 802.3. Set-'
ting the number to 7FFH allows the 82586 to operate
over distances 8 times longer than specified in the IEEE
802.3 specification.

This capability prevents Inefficiencies and throughput
loss in short topology or low data rate networks where
the Interframe Spacing time may be longer than the
slot time.
If the IEEE 802.3 backoff algorithm were applied to

NUMBER OF RETRIES (4 BITS)

short topology networks where slot time is much smaller than Interframe Spacing, the 82586 would retry over
and over again until the sum of the slot times exceeded
the Interframe Spacing time, these retrys would waste
channel bandwidth. See Figure 2-29.

Specifies the maximum number of transmission retries
(after a collision) that the 82586 performs before transmission is aborted by the 82586.

Linear Priority and Accelerated Contention Resolution
can be combined in the short topology network environment. See Figure 2-30.

LINEAR PRIORITY (3 BITS)

RETRY
NUMBER

Specifies the number of Slot Times periods the 82586
waits after Interframe Spacing or Backoff, before enabling transmission. A high number indicates low priority. Stations configured to zero, the highest priority,
is equivalent to IEEE 802.3.

I--t IFS
FIRST ~---__iSLOTTIME

f--! IFS

ACCELERATED CONTENTION RESOLUTION,
ACR (3 BITS)
,

o

ST
SECOND r_--"-sT=--__i---"s..;.T-__i

This parameter is added to the exponential number
from which the random number is drawn for Backoff.
In essence, ACR increases the range of random numbers to quickly resolve the case of stations contending
for access to the network.

2

~-_S~T~__i-~S~T-~-~S~T-~3

COLLISION

230814-,47

Specifically, let:
ACR - be the ACR priority number
N
- be the number of collisions
r
- be the random number multiplier of the slot
time. r is a random number between 0 and 2
exp (min. [N + ACR, 10]).

Figure 2-29A. IEEE 802.3 Retry Algorithm,
Slot Time (ST) Greater Than IFS

2.12.3 Serial Interface Parameters
MANCHESTERINRZ (1 BIT)

ACR = O,.is equivalent to the IEEE 802.3 exponential
backoff delay.

Specifies the bit encoding scheme used during transmission.
o NRZ encoding (binary)
Manchester encoding

2-59

LAN COMPONENTS USER'S MANUAL

RETRY
NUMBER

CDT (End 01 Jaml

IFS
FIRST

CRS

0

IFS
ST
1-----.......,"-+-"-'-1

_I

BACKOFF
IFS

IFS
IFS

SI •

r

RANDOM
DELAY

-I TRANSMIT
PxST

0
ST
(P = PRIORITYI

IFS ST ST
2
SECONO I-----.......,"-+.:!.:..~:...,
IFS ST 'ST
ST 3

230814-49

Figure 2-30. Combined Linear Priority and
Accelerated Contention Resolution Using
Alternate Backoff Method

230814-48

Figure 2-29B~ Exponential Back Off, Slot Time
(ST) Less Than IFS

CDT-FILTER (3 BITS)

In the Manchester mode the 82586 requires external
Receive clock recovery logic from the Receive data.

Specifies the required width of the external Collision
Detect signal (in TCLK units), before the 82586 recognizes that a collision occurred. Only negative going
glitches are filtered.

INTERNAL CRS (1 Bin

Specifies whether Carrier Sense is generated internally
or externally. External carrier Sense is fed through the
CRS pin. If set, presence of the Receive clock is interpreted as Carrier Sense active. Absence of the Receive
clock means Carrier Sense inactive. This capability is
useful in point-to-point transceiverless networks. See
section 2.11.2.
o External
Internal

TRANSMIT ON NO CRS (1 BIT)

Determines whether transmission, even if no carrier
Sense is returned from the Transceiver, is allowed, This
option is used with Transceivers that do not return Carrier Sense during transmission.
o Stop transmission if Carrier Sense drops
1·
Transmit on no Carrier Sense

2.12.4 Host Interface Parameters

CRS-FILTER (3 BITS)

Specifies the 'required width of the Carrier Sense signal
(in TCLK units), before it is recognized as active. carrier Sense deactivation is recognized immediately, i.e.
only negative going glitches are filtered. This capability
is useful in noisy cable environments. See section
2.11.2.

FIFO-THRESHOLD (4 BITS)

Specifies the point in the FIFO at which the 82586
requests the bus to transfer data to/from its internal
FIFO from/to memory.
The FIFO limit is dependent upon the worst-case time
from bus request to bus grant and serial channel and
system clock rates. See sections 2.10.4 and 5.2.

INTERNAL CDT (1 BIT)

Determines whether Collision Detect is generated internally or externally. External Collision Detect is fed
through the CDT pin. Internal Collision Detect interprets presence.of carrier Sense during transmission as a
collision. If internal Carrier Sense is used with internal
Collision Detect, presence of the Receive clock during
transmission will be interpreted as a collision.
o External Collision Detect
Internal Collision Detect

SRDYI ARDY (1 BIT)

Selects between Synchronous and Asynchronous Ready
function of the SRDY/ARDYpin (active HI). If Asynchronous Ready is selected (SRDY/ARDY bit = 0),
the SRDY/ARDY signal is synchronized internally by
the 82586. If Synchronous Ready is selected (SRDY/
ARDY bit = 1), the SR1JY/ARDY signal is assumed
to have been synchronized externally.

See section 2.11. 3.
2-60

LAN COMPONENTS USER'S MANUAL

When using internal synchronization of the ready signal, one wait state may be added to each cycle, thus
reducing the performance at most by 20%. Full performance systems must implement external ready synchronization. In that case, the SRDY/ ARDY bit will
be set to one and the external Ready signal will be connected to the SRDY/ ARDY input pin.
o Asynchronous Ready
Synchronous Ready

When set, the 82586 disconnects itself from the serial
wire and logically connects TXD to RXD and TXC to
RXC. TXC must still be supplied by the user. Internally, TXC is divided by 4. This slows down the serial bit
rate sufficiently to enable 82586 operation in full duplex. This will alter the effective values of all configure
command parameters that are defined in terms of TxC.
Note that this is purely Internal Loopback capability.
The INT-Loopback bit overrides the EXT-Loopback,
i.e. having an INT-Loopback bit set, at the same time
with EXT-Loopback, causes the 82586 to operate in
Internal Loopback Mode. See section 2.11.5.

SAVE BAD FRAME (1 BIT)

Determines whether erroneous frames (CRC error,
Alignment error, etc.) are to be discarded or saved. Erroneous frames are those where the OK bit in the
Frame Descriptor status field is equal to zero. All
frames are saved regardless of length.

EXTERNAL LOOPBACK (1 BIT)

o

No externalloopback
External loopback
The 82586 will receive and transmit simultaneously, at
full rate, a frame limited to 18 bytes (including the
Frame Check Sequence). This allows checking of external hardware as well as the serial link to the transceiver. For IEEE 802.3 transceivers, since the transmitted
data is fed back via the receive pair, practically nothing
has to be done to perform External Loopback. For other transceiver types, the user is responsible for external
transmit-receive interconnection. See section 2.11.5.
NOTE:
Internal Loopback hit overrides External Loopback
bit.
I

In Save Bad Frame mode, the Frame Descriptor, as
well as the Receive Buffer Descriptors and Receive
Buffers are NOT reused for the next frame. In the complementary mode, .all the descriptors and buffers used
for bad frames will be reused, thus, not leaving any
information about the lost frame except for updating
the SCB statistical tallies.
o Discard erroneous frames
Save erroneous frames
ADDRESS/LENGTH FIELD LOCATION (1 BIT)

PROMISCUOUS MODE (1 BIT)

Specifies the location of the Address and Length fields
in the memory structures, and whether the Source Address is inserted during transmission.
o
Address and Length Fields are located in consecutive bytes in the Frame Descriptor. Source
address is inserted by the 82586 during transmission.
The whole frame is located in the data buffers.
Source Address is not inserted by the 82586.

Determines whether or not the 82586 accepts all frames
regardless of their Destination Address.
o Normal address filtering
I
Promiscuous mode
When Promiscuous mode is set, the optional broadcast
disable is overridden.

2.13 INTERNAL ARCHITECTURE

This capability is useful in address/control schemes
that the 82586 cannot manipulate. It is also helpful for
diagnostics.

The 82586 is divided into three functional modules:
Bost Interface Module, Channel Interface Module, and
FIFO Module. The Host Interface Module communicates with the host CPU and shared memory via the
Bus Interface. It performs direct memory access, buffer
chaining, and interpretation of high level commands.

2.12.5 Network Management
Parameters .

The Channel Interface Module communicates with the
Network via the Network Interface. It performs network related activities: framing, link management, address filtering, data encoding, and network management.

INTERNAL LOOPBACK (1 BIT)

Specifies whether frames are internally looped back or
not.
.

o
I

No internalloopback
Internal loopback

The two units inter-communicate via the FIFO Module
.
that consists of two 16-byte FIFOs.
A block diagram of the 82586 is shown in Figure 2-31.
The three modules are separated by dashed lines.
2-61

LAN COMPONENTS USER'S MANUAL

commands are sent to the Channel Interface Module
via the Transmit FIFO. The Command Unit responds
to the Channel Attention (CA) signal from the host
CPU, and manages the initialization process ..

2.13.1 The Host Interface Module
The Host Interface Module appears on the right side of
Figure 2-31. It consists of separate units for data, address, and control interfacing to the local bus, all under
control of two micro-sequencers (for executing commands and receiving frames, respectively), a micro-instruction ROM, an Arithmetic Logic Unit, and a register file.

The Receive Unit fetches, from shared memory, information defining buffer availability, size, and location,
and controls data transfer to the buffers~ In executing
these tasks, it performs similar functions· as described
above for the Command Unit, with the exception of
initialization and response to Channel Attention.

Communication between units of the Host Interface
Module is by means of an internal 16-bit bus (P-bus),
controlled by the two micro-sequencers: the Command
and Receive Units. Both sequencers operate on microinstructions from a common ROM; each is dedicated to
a separate class of tasks, and has its own program counter and stack. Only one of them can run at any given
moment.

The Micro-Instruction ROM supplies micro-progr~
to the Command and Receive Units. It contains a thousand words, 20-bit long. The Arithmetic Logic Unit is
used by the micro sequencer to perform simple arithmetic and logical operations. The Register File consists
of twenty four 16-bit registers, plus an additional 48
flags. The Register File makes up an internal data storage facility for the Micro-Machine.

The Command Unit fetches commands from shared
memory space, and controls other units of the Host
Interface Module. as necessary for executing the commands. It also receives status signals, processes them,
and updates shared memory as required. The Command Unit controls the DMA machine, loads starting
pointers and byte counts for DMA transfers, triggers
the start of transfers, and aborts them if necessary. It
uses the Arithmetic Logic Unit (ALU) as needed. Its

The DMA Unit is a memory address generator which
operates on starting addresses and byte counts supplied
by the Micro-sequencers to transfer information between the 82586 and shared memory. The unit is com"
posed of four channels. Two channels are designed for
block transfers, one each for transmission and reception; each of these includes a 14-bit byte counter and a

RTS --,~.,...---...,
CTS

m

TXD

TRANSMIT
BIT
MACHINE

TRANSMIT
BYTE
MACHINE

ClK
HOLD
HlDA
INT
CA
RESET_
SRDY/ARDY

BUS
INTERFACE
UNIT

~~
SI~

MNMX

CARRIER

ccf~~~'~N
DETECT

It-------....

lOGIC
A:Z3"

16
EX~:~;~AL . ._ _ _ _ _ _....

-tI

DATA
.".. . . .
INTERFACE"
UNIT

TIMER

A"
BHE

DMA
UNIT

A20

A,oISt;
A16-18

RXD
RXC

RECEIVE
BIT
MACHINE

RECEIVE
BYTE
MACHINE

16

I
I
I

----------------------~!. FIFO
---'MODULE
-----~ ------'- -. HOST
- --- - - ---- - --~
CHANNEL INTERFACE MODULE
INTERFACE MODULE
230814-50 .

Figure 2·31. Block Diagram of the 82586

2-62

LAN COMPONENTS USER'S MANUAL

24-bit absolute address register. The remaining two
channels are-for single word transfers, one for each of
the micro sequencers; each includes a 16-bit address
offset register. The two channels share a common 24-bit
base address register.

Bit Machine. The latter converts the frame into a pulse
train and transmits it to the Network Interface. The
Transmit Bit Machine performs Bitstuffing (if configured to do so).
The Exponential Backoff timer implements Backoff,
Defer, Wait and Priority algorithms and other 82586
timers.

The sixteen lower order lines of the generated addresses
are mUltiplexed with the data lines in Word mode.

The Receive logic consists of the Receive Byte Machine
and Receive Bit Machine. When a frame is received
from the Network, the Receive Bit Machine strips the
Preamble and SFD Field from the frame, and determines the end of the received frame by the occurrence
of either EOF flag or End of Carrier. If Bitstuffing is
active, inserted zeros are deleted, and computes and
verifies the CRC (Cyclic Redundancy Check).

All control signals between the 82586 and the local bus
are generated or received by the Bus Interface Unit
(BIU). The BIU also handles the CA line, used by the
host CPU for the 82586 attention calls, and the INT
line, for the 82586 to request the attention of the host.
CLK is a clock supplied by the host, and is used for all
Host Interface Module and FIFOs timing. Signals that
control the local bus are also defined in terms of CLK.
These signals are optimized for the iAPX 186, 8086,
and 8088 bus.

The Receive-Byte-Machine checks the Destination Address of the received frame to determine if the Individual Address matches the Receiver'S; for Multicast transmissions, it performs the hash filter function to determine whether the frame is directed to this Station.

The Data Interface Unit is a switching matrix which
routes data and status signals to the appropriate destinations by interconnecting input and output as -required. Command data are routed from the P-bus to
the Transmit FIFO; transmit and receive status signals
are sent from the Receive FIFO to the external bus; and
data to be transmitted are routed from the external bus
to the Transmit FIFO. Note that the two FIFOs are 8
bits wide, while the P-bus width is 16 bits. Data packing and unpacking are performed in the Data Interface
Unit as required.

Received data and status signals are relayed through
the Receive FIFO to the Host Interface Module.

2.13.3 The FIFO Module
The 82586 contains two l6-byte FIFO storage arrays
located between the Host Interface Module and the
Channel Interface Module. One FIFO transfers data in
the transmit direction and the other in the receive direction.

2.13.2 The Channel Interface Module
This is the second portion of the 82586, shown on the
left side in Figure 2-3\. It contains separate units that
perform transmission and reception over the Network
Interface.

The FIFOs improve local bus utilization by virtue of
temporary data storage on the way to or from the Network. For continuous transmission in the absence of
the transmit FIFO, the local bus would have to be dedicated to frame transfer during the entire transmission
and the host CPU would be unable to use the bus for
other tasks. The FIFO allows the 82586 to relinquish
the local bus for intermittent intervals during transmission. During these intervals data in the FIFO empties
toward the Network,maintaining transmission until
the bus returns to the 82586 control.

The Transmission logic is composed of three units:
Transmit Byte Machine, Transmit Bit Machine and
Carrier Sense/Collision Detect Logic. The Transmit
Byte Machine interprets commands from the Transmit
FIFO, executes them, and generates appropriate status
signals, which are returned through the Receive FIFO.
During transmission, the Transmit-Byte-Machine assembles data frames, calculates and appends the Frame
Check Sequence, and passes the frames to the Transmit

Similarly, the receive FIFO accumulates incoming
bytes while the bus is otherwise occcupied, reception
continues without data loss.

2-63

Programming the 82386

3

CHAPTER 3
PROGRAMMING THE 82586
3.0 INTRODUCTION

2) The 82586 handler

The 82586 LAN Coprocessor handles most of the functions of the data link and physical link layers of the ISO
Open Systems Interconnect model. It does this with a
minimum amount of supervision by the host CPU and
usually executes concurrently with the host CPU. The
host CPU and the 82586 communicate through a set of
shared memory control structures. The 82586 is a
DMA master which allows it to operate on these control structures as needed to handle commands and
manage its own buffers.

3) Upper Layer Communications Software (ULCS)
4) User application software.
The 82586 is simply the controller itself. Inputs from
the host CPU include Commands, Command Blocks,
FDs, and Receive buffers as well as Channel Attention
signals. Outputs from the 82586 to the host include
completed commands, received frames and interrupts.
The 82586 handler consists of software routines that
actually control the 82586. These routines perform:

The asynchronous nature of data communications and
the autonomous operation of the 82586 requires special
attention to the CPU/82586 software interface. In order to simplify communication between the CPU and
the 82586, a protocol has been defined that must be
used by both units. This chapter discusses the algorithms that the CPU must use in communicating with
82586. Since the 82586 is expecting the CPU to follow
these algorithms, the user must be sure that the CPU
does so. Failure to follow the algorithms may result in
system failure.

•
•
•
•

Generating Channel Attentions to the 82586
Receiving interrupts from the 82586
Reading and writing the 82586 control structures
Giving commands to the 82586 and determining
when they are completed
• providing free (unused) buffers to the 82586 and determining when they have been filled.

This chapter will discuss two basic issues. The first is
how the 82586 can be placed into a variety of operating
system environments. This topic is important because
the 82586 is an intelligent peripheral component: a coprocessor. The second issue is the algorithms by which
the host CPU controls the 82586, that is the details of
device control. To properly use the 82586, the user
must address both sets of issues.

USER APPLICATION
SOFTWARE

UPPER LAYER
COMMUNICATION
SOFTWARE

3.1 FITTING THE 82586 INTO A
SYSTEM
. The first problem to be solved in using the 82586 is to
define how the 82586 fits into the software environment
of a host system. The 82586 is more powerful than most
peripheral components and may present some unique
problems fitting it into a system. The 82586 is more a
coprocessor than it is a peripheral component and must
be treated as such. The 82586 is a coprocessor primarily
due to its buffer management capabilities as well as its
ability to chain commands.

82586
HANDLER

In order to understand how the 82586 might fit into a
system it is helpful to consider a general model of how
distributed systems software might be implemented, see
Figure 3-1.

82586
LAN COPROCESSOR

230814-51

Figure 3·1. Distributed System Software Model

Figure 3-1 shows four distinct entities:
1) The 82586 itself
3-1

LAN COMPONENTS USER'S MANUAL

The ULCS consists of software that provides network
capability for user application software. The ULCS
usually consists of Transport Layer (Layer Four of the
OSI model) software that provides reliable, process to
process delivery service. Such software is required in
one form or another because the CSMA/CD protocols
supported by the 82586 (such as Ethernet and IEEE
802.3) provide only datagram or 'best effort' box to box
delivery service. The Transport layer provides enhanced communication services compared to datagram
based data links. These services include process-toprocess message delivery. This capability is useful since
there are usually several sources, or sinks, of data at a
single node. Also provided is guaranteed end-to-end
message. service. Transport ensures that data is not lost,
duplicated, or delivered out of order. The ULCS interfaces to the 82586 handler when it wishes to transmit a
frame or when the handler pases a received frame to it.

UPPER LEVEL
COMMUNICATION
SOFTWARE

OS INTERFACE

MEMORY
MANAGEMENT

230814-52

Figure 3-2. The 82586 Integrated Into ULCS

3.2.1 The 82586 Handler as a Standard
Device Driver

The User Application Software consists of software'
that uses the communications channel to perform tasks
in a distributed manner. This software uses the ULCS
to 'provide reliable communication path to other processes on the network. This software is usually not aware
of the presence of the 82586.

Most modem operating systems have an I/O system
that can be broken down into three parts (Figure 3-3).
The first part consists of a standard interface used by
all application programs. This interface is used by all
types of devices ranging from disks to line printers. Its
purpose is to make all devices look alike so that application programs can operate in a device independent
manner. The second part consists of I/O service routines that handle particular, types of devices. Usually
two major types of devices are considered, structured
devices such as disk or tape files and nonstructured
devices such as TTY.drivers and line printers. The
third part are the device drivers which are routines that
actually manipulate the hardware such as the disk con"
troller or USART.

The following sections ~ddress the problem of how the
82586 handler fits into a system. This problem involves
two major areas of discussion. The first concerns the
. nature of the interface between the 82586 handler, the
host operating system and the ULCS. That is, how does
the 82586 handler fit into the operating system environment. Before the handler for the 82586 can be written,
there should be clear model in mind for how it will fit
into the system. The second major area concerns buffer
management. That is, how buffers are allocated utilized and moved between the two entities. Unders~and­
ing these issues is the topic of the following sections ..

Device driver interfaces are usually standardized within
an operating system to allow varieties of devices to be
used without rewriting any of the I/O service routines.
The interface is usually faifly simple because its goal is
to allow as many types of devices to be used as possible.

3.2 THE 82586 HANDLER
There are basically two approaches for fitting the 82586
handler into an operating system. The first has the
82586 handler appear as a standard I/O driver. The
second makes the 82586 a special type of device that
bypasses normal I/O conventions. In the latter model,
the 82586 handler would likely be integrated into the
ULCS, see Figure 3-2.

In this type of environment the 82586 handler would fit
into the system as a device driver for an unstructured
device. The user would issue commands to the 82586
via the standard I/O interface which would be relayed
to its device driver (Figure 3-4). In such an environment the ULCS would exist as an application software
routine using a standard interface to the 82586 handler.

The basic issue in the two approach~s is to what extent
will the 82586 be allowed to control the rest of the
system, especially the communications software, in order to allow full use of its capabilities.' If the 82586
must be fitted into existing structures, it is unlikely that
its full power can be utilized .. Alternatively, to extract
the full benefits of the 82586, the designer will have to
stretch the operating system to accommodate the
82586.

There are a number of advantages using this approa~h.
First, it may be the only way to fit the handler into the
system. If the system has memory protection or virtual
memory, being part ofthe I/O. system may be the ouly

3-2

LAN COMPONENTS USER'S MANUAL

(i.e. devices that perform one task at a time, do not
manage their own memory and require constant attention from the CPU). In addition, the buffers that are
passed across such interfaces are usually assumed to be
one large contiguous block of memory. It could be fairly difficult trying to fit the 82586's linked list mechanisms into such a model. In some operating systems,
only one command at a time can be issued across the
interface. Often such an interface is not very good for
asynchronous events (increased probability of losing
frames). In addition, the performance across such an
interface may be slow. Despite these problems, undoubtedly there are many systems in which this is the
best approach. In such situations there are a number of
mechanisms that allow many of the features of the
82586 to be used.

TO APPLICATION PROGRAMS

1/0 SERVICE
ROUTINES:
STRUCTURED
DEVICES

1/0 SERVICE
ROUTINES:
NON-STURCTURED
DEVICES

Looking first at command block handling, a common
model of operation would be one in which an operating
system command block with something like a WRITE
command contained inside it would be passed to the
device driver. There would also be a pointer in this
command block to an area of memory containing data
to be 'written' (a System I/O Buffer). The 82586 device
driver could interpret this WRITE command as being a
TRANSMIT command with the data being the message to be sent. Inside the device driver would be an
82586 Command Block (CB) and a Transmit Buffer
Descriptor (TBD). When the driver receives the operating system request block it will set up its internal CB to
the desired function and its TBD to point to the System
I/O Buffer. The driver then gives the CB and TBD to
the 82586 for execution. When the 82586 has completed processing, the Driver returns completed operating
system command block back to the operating system.
The internal CB and TBD are then freed.

230814-53

Figure 3-3_ Common 1/0 System Structure_

82586 DRIVER

1~~~SE~~ 1----'\:1---'\1
BLOCK

I

I/O SYSTEM
INTERF'ACE

SYSTEM
I/O
BUFFER

I
---+---I

L--_ _ _--J

230814-54

There are a variety of variations on this technique but
all are based upon an internal CB/TBD within the device driver being used to pass the command to the
82586. For example, one might consider passing the
82586 command block and message as part of the data
to 'written'. In. this case the contents of the provided
82586 Command Block would be copied to the internal.
CB and the TBD set·up to the message part of the data.
By having an internal CB and TBD the need for them
to be in the same 64K byte segment as FDs, RBDs, and
the SCB can be easily, met.

Figure 3-4. The 82586 Handler as a Standard
Device Driver

way the handler can get access to user memory or actual physical memory (rather than virtual memory). Second, there would be a reasonable degree of device independence. The ULCS could be written independent of
the 82586 and so other data links could be inserted with
minimum changes to the ULCS. Third, the 82586 handier would not have to reinvent the mechanisms already used by all device drivers, such as interrupt handling, buffer management or fault handling.

Turning to receive handling there are a variety of options. The most simple approach is to reserve a FD,
RBD, and single buffer (long enough to contain the
biggest message that will be received) within the device
driver. When the 82586 receives a frame, it fills the
buffer and passes it back to.the driver. The operating
system would recover the frame by· issuing a READ
with a System I/O Buffer. The received frame would be
copied into the System I/O Buffer and the operating
system READ command returned. While very simple

However, this approach is likely to prevent many of the
high level function capabilities of the. 82586 from being
used. The standard I/O interface and the device driver
interfaces are likely to prevent use of buffer and command block chaining. As· noted above, these standard
interfaces are usually fairly general, and especially at
the device driver level, assume rather simple devices

3-3

LAN COMPONENTS USER'S MANUAL

this approach suffers from possible poor performance
due to lost messages. Lost messages are caused by the
single receive buffer within the device driver being freed
only when -the operating system posts a receive buffer.
There is also the cost of doing the copy into the System
1/0 Buffer.

RBD. Recovering FDs and RBDs simply involves
changing the EL bit from one to zero on the previous
FD and RBDs to the one being recovered.
This circular list approach takes better advantage of the
82586's capabilities in that the 82586 can receive frames
asynchronously to the operating system reading them.
Also, the 82586's buffer chaining capability can be used
to obtain more efficient memory usage.

A variation on this technique that addresses the copy
problem is to move the data directly into the System II
o Buffer by using the buffers supplied by the READ
command. As in the command block case, internal FDs
and RBDs would be used as control structures. With
either approach a frame can get lost if the System 1/0
Buffer is not supplied with new buffers frequently.

3.2.2 The 82586 Handler asa Special
Driver
If the 82586 handler is treated as a standard device
driver, device independence is maintained, but at the
cost of performance. Performance is degraded for two
reasons. First, copies of data must be made between the
System 1/0 Buffer and the driver. Second, frames may
be lost due to a lack of buffers. This suggests that if
possible, another approach be found.

An alternative approach is to reserve a circular list of
FDs, RBDs within the device driver, see Figure 3-5.
The 82586 places received frames into the buffers.
When the operating system issues a READ command,
the 82586 driver copies this information into the supplied System 1/0 Buffer. The device driver reclaims the
old FD, RBD, and buffers.
_

This other approach consists of moving the 82586 handler outside of the 1/0 system and be treated as a special kind of device. In this model, the 82586 handler
would exist as a separate entity, llloSt likely made partof the ULCS routines, see Figure 3-6. The only support
required from the operating system would be interrupt
handling. The ULCS would likely operate on linked
buffer structures and perhaps be -aware of the control
structures of the 82586. The 82586 handler would still
manipulate the control blocks given it by the ULCS
and interface to the 82586, but operate much closer to
the ULCS. In this environement more attention must
be paid to the buffer management model used by' the
82586 and the ULCS. The 82586 can operate with a
variety of buffer models in this type of environment
although there is one that can be considered its 'design
model.' This model and sl)veral others will be discussed
in the following section. _

BEGIN LIST POINTER

~
-

FD

230814-55

Figure 3·5. 82586 Device Driver
Using Circular Lists

The 'Design' memory management model for the 82586
is shown in Figure 3-7. This model assumes an explicit
Transport (and perhaps Network) Layer. Two pools of
memory, one for Transmit (called the CB pool), and
the other for Receive (called the RFA pool) contain
various control blocks needed for 82586 operation. The
CB pool contains CBs, TBDs, and transmit buffers.
The RFA pool contains FDs, RBDs, and receiver buffers. Blocks do not move between pools. These data
structures are 'owned' by the 82586 handler. Usually
these pools are independent of the operating system's
Free Space Manager (it is possible for them to be part
of a system free space manager, but this will significantly increase overhead). Both pools are 'owned' by the
82586 handler or by the 82586 itself. The CBpool belongs to the handler while the RFA pool belongs to the
82586 itself. The RFA pool is basically the memory
pool managed by the 82586 Receive Unit.

The circular list is managed using a FIFO philosophy.
Frames are always processed in the order thl':Y were
received, and processed FDs and RBDs are replaced iii.
order. The links among the FDs on the RDL and the
RBDs on the FBL are never altered. The EL bit is used
to mark the logical end of the list. The 82586 .itself
manages the linking FDs to RBDs as they are needed.
If the 82586 runs out of FDs or RBDs, it enters the No
Resources state. In order to know the logical beginning
of the lists,the devide driver will maintain a pointer to
the 'first' freeFD and RBD. As fralnes are received
The driver will always know which FD is to be used
next. As FDs and RBDs move from the empty to filled
state, the pOinters should be moved to the next FD and

3-4

LAN COMPONENTS USER'S MANUAL

On the receive side, the RFA pool is managed by the
82586 ifse1f. When a frame has been received, the 82586
interrupts the handler. The handler passes the FD,
RBD(s), and receive buffer(s) to the receive side of the
Transport Layer. The Transport Layer extracts what it
needs, and returns the FD, RBD(s), and receive buffers(s) to the handler. The handler reclaims these structures and places them at the end of the Receive Frame
Area managed by the 82586.

SYSTEM
CONTROL
BLOCK
(SCB)

230814-56

Figure 3-6. The 82586 Handler as Part of the
Communications Software

UPPER LAYER COMMUNICATION SOFTWARE

J

SEND

.....

I

,r

CBPOOL

~

CBs
TBD.
TBs

"-

.....

RFAPOOL

7 ......

f'-...'

RECEIVE

?.....
FDs
RBD.
RB.

......

"-

82586 HANDLER

-230814-57

Figure 3-7. 82586 Handler Memory
Management Model

To transmit a Frame, the Transport Layer requests a
buffer from the 82586 handler. This might be done by
making a subroutine call to the handler. The handler
returns a command block and enough buffers (with
TBDs) from the CB pool to the Transport Layer. The
Transport Layer will fill the buffer with some portion
of the user message and initialize the CB to whatever
values are required for the operation desired. The CB
(and buffer) are then returned to the handler where it is
given to the 82586. When the command is executed by
the 82586, the handler will receive an interrupi and will
reclaim the CB and TBD and places them back into the
pool.

As noted above there are a variety of memory management models that the 82586 can operate with besides
the 'design' model. Another model of interest eliminates the copy of ,data from user buffers into transmit
data link buffers and from receive data link buffers to
user buffers. One approach to eliminate copies of data
is to eliminate the transmit buffers from the CB pool
and only provide CBs and TBDs. The Transport Layer
software then sets up pointers to header information
and user data using the TBDs. On receive, the Transport Layer passes on the data link buffers to the user
and returns only the FDs and RBDs (plus new receive
buffers to replace those passed to the user).
This technique eliminates copies of data, it does have
some problems. First, both transmit and receive buffers
must be in 'fast' memory (that is, memory that can be
accessed directly by the 82586 at a minimum of 1.25
Mbytes/sec.). Second, the Transport header may not be
long enough to meet the minimum buffer size required
for the 82586. On receive this problem manifests itself
as to how to handle the transport header information; it
cannot be passed up to the user. Third, care must be
taken to ensure that the memory used in data link buffers is accessible by the user program. If user programs
are restricted to only some memory areas, then the situation may arise in which the user program cannot access a received buffer. In this case a copy would be
required.
As noted above the 82586 was designed to work with
one buffer management model. The 82586 does operate
with other models provided the algorithms in the fol, lowing sections are followed. It is important to recognize that there must be a buffer management .o.odel
present in the system. It should be a model that is chosen upfront in the system design, not after.

3.3 INITIALIZATION OF THE 82586
Initialization of the 82586 occurs in these three phases.
The first phase involves use of the SCP and the ISCP to
locate the SCB and define the bus width. The second
phase involves issuing Configure, Individual Address
Setup and Multicast Address Setup commands. The
third phase involves starting the RU by supplying it
with an initial allocation of FDs and RBDs. This .section addresses only the first two phases; section 3.6 addresses starting the RU. It should be noted that it is

LAN COMPONENTS USER'S MANUAL

important that three phases be done in the order indicated. Starting the RU prior to setting up the individual
address is generally undesireable.

Figure 3-8 illustrates this basic procedure of giving a
new CB to the 82586. Note that the CPU must mask
off interrupts from the 82586 during various parts of
the algorithm. Masking interrupts will ,prevent the interrupt service routine from issuing commands to the
82586 which might overwrite the command just given
to the 82586 by the command processing routine. Overwriting might occur if an interrupt oc.curred between
the recognition that the SCB command field was clear
and the issuing of the CA. Either the command processing routine or the interrupt service routine could
find their command to the 82586 being overWritten by
the other. The result of this race condition would likely
be a system hand up.
',

The SCP and ISCP are designed for maximum flexibility in locating the SCn. Usually in iAPX 86 family systems, the SCP is located in ROM together with the
processor bootstrap routines. The model of operation is
that the SCP will point to the ISCP which is located in
RAM. The address of the SCB can be written into this
RAM location so that it can vary with different system
configurations. The SCP and ISCP will exist only for
initialization purposes. Once the SCB is located, the
SCP and ISCP locations can be reclaimed. The SCB
should be initialized prior to beginning the SCP/ISCP
sequence.
The second phase involves issuing commands that configure the 82586. If the 82586' is userl in -IEEE 802.3
configuration, it is not necessary to issue a configure
command since the 82586 initializes itself as an IEEE
802.3 controller. Otherwise the user must issue the
Configure command. After configuration, the user
should issue an Individual Address Setup command to
load the 82586 with the host address. This procedure
may be followed by the MC Setup command as required. These commands may be chained together or
issued one at a time.
After address setup, the RU can be started and supplierl
with FDs and RBDs, see section 3.6.4.

3.4 SIMPLE COMMAND PROCESSING
With an understanding of how the 82586 handler fits
into a system, the operations to be performed by the
handler can be discussed. This section discusses giving
commands to the 82586 and servicing 82586 interrupts.
Simple command processing in this context means that
the 82586 handler accepts only one command at a time
for the 82586. ULCS is not allowed to give a second
command to the handler before the previous command
has been executed. More complex processing will. be
discussed in section 3.5.

3.4.1 Adding CBs to the CBl
Simple command processing means that coniniands are
issued one at a time to the 82856. The handler is given a
single CB by the ULCS, writes the address of the CB
into the CBL_OFFSET field in the SCB, places a Start
CU command into the SCB, and issues a CA. The
82586 will accept the Start,CU command and clear the
SCB field. It will then execute the CB, update status in
the SCB and generate an interrupt to the handler. The
handler will process the interrupt and then reclaim the
CB for future use. This procedure can be repeated as
required.

230814-58

Figure 3~8. Simple Procedure to Add
a New C@. to the CBl

3.4.2 Basic Interrupt Service Routine
When a command has been completed by the 82586, an
interrupt will be issued to the host CPU (if the I bit was
3-6

LAN COMPONENTS USER'S MANUAL

set in the (CB). Figure 3-9 shows the basic interrupt
service routine. This routine's interrupt acknowledgement sequence will be used over again in the command
and receive interrupt service routines that will be described later. The routine starts by saving CPU context
(this may have already been done by the operating system). The handler then waits for the SCB command
word to clear, which signifies that the 82586 has no
pending control commands. The handler determines
the nature of the interrupt, sets the appropriate ACK
bits in the SCB Command Word, and issues a Channel
Attention (CA) to mark acknowledgement of the interrupt. The handler then waits for the 82586 to accept
confirmation of the interrupt acknowledgement by
clearing the SCB command field and removing the interrupt signal (provided no new events that may generate an interrupt have occurred). The CB is then examined by checking the C bit (command completed bit). If
completed, the CB is returned to the handler for re-use.
If the command was not completed then some error is
likely to have occurred. The routine is exited by issuing
an End of Interrupt, EOI, to the interrupt controller
and restoring interrupt context.
The basic algorithm is referred to by all the following
sections. The only part to change will be the parts that
refer to CB processing.

NO

3.5 ADVANCED COMMAND
PROCESSING
This section primarily is concerned with how commands may be chained together. In practice, it is difficult to chain two or more commands together for two
reasons. First, the 82586 can execute commands much
quicker than most operating systems can prepare the
next command. For example, it takes less than 1 ms to
transmit 1000 bytes at 10 Mbps for IEEE 802.3. Most
operating systems would be hard pressed to prepare
another command before the first was completed. Second, chained commands must be given to the 82586 in
groups. If a single command is given to the 82586 and
the CU is started, the 82586 will not execute the added
CBs. The new CBs are ignored because the 82586 reads
the first CB's EL bit set to one and concluded that
there were no more Command Blocks to be executed.
This behavior will occur' even if the new Command
Block is chained to the first and the EL bit on the first
is reset; once the 82586 has started working on the first
CB it does not reexamine the EL bit. Thus if one wishes
to chain commands it will be necessary to ensure that
the 82586 has at least one unfetched Command Block
present. This rule requires that the 82586 be started
with at least two Command Blocks present.

230814-59

Figure 3-9. Basic Interrupt Service
Routine Sequence

Despite these problems there are situations in which
some form of Command Block chaining might be useful. The first case is where the ULCS may have the
capability to occasionally give the 82586 handler multi3-7

LAN COMPONENTS USER'S MANUAL

CBs on the list and the process proceeds as' in the simple case (Figure 3-8). Begin.CBL and End.CBL are
both set. to the address of the CB. If Begin.CBL is not
OFFFFH, then there are CBs on the list to which the
new CB is to be added. First, interrupts from the 82586
are masked off to prevent race conditions between interrupt service routine and CB chaining procedure. The
new CB is added by inserting its address in the current
last CB's Link field, and the END.CBL pointer is updated. For dynamic lists, the EL bit ofthe formerly last
CB on the list is set to zero. It is important that the EL
bit is not set to zero prior to the Link field being valid.
Otherwise, the 82586 may go off to an invalid address
and never return. For static lists, the EL bit is set for all
CBs.

pie Command Blocks (not at the same time) and some
structure is desired to handle it. In this case the commands are most likely to be executed one at a time by
the 82586 simply because they are given to the handler
one at a time. This case is called static lists. In this
approach Command Blocks are chained together on a
list but only one Command Block is actually given to
the 82586 at a time. Thus the 82586 will execute one
Command Block, halt (the CU goes to the IDLE state),
and interrupt the host CPU. The handler would then
process the completed Command Block and, if another
one is on the list, give it to the 82586 for execution. If
there are no commands, the CU is not restarted. Given
how fast most CPUs can actually prepare request
blocks and the manner in which the 82586 operates
upon lists, static lists are probably the best overall approach.

3.5.2 Static List Interrupts
The second approach is similar to the first except that
the 82586 can be given multiple commands to execute.
This case, called dynamic lists, occurs only if there are
two or more unexecuted commands on the Command
List and the CU is in the IDLE state (requiring it to be
STARTed). If there is only one command on the list (or
the 82586 is on the last Command Block of a list of
commands) then trying to add additional commands
yields nothing. Dynamic lists are an attempt to take
advantage of the fact that the 82586 executes one command at a time and does not look beyond the current
CB being executed (except for the implications of setting the EL bit). Most of the time, dynamic lists will
function as static lists, but occasionally an interrupt
may be saved.

When a single command has been completed, the 82586
will interrupt the host CPU. The interrupt service routine, ISR, for static lists, shown in Figure 3-11, builds
upon the basic interrupt acknowledgement routine described in Figure 3-9. After the basic routine is completed, two sanity checks are performed. First, that
there is a Command Block present (Begin.CBL is not
equal to OFFFFH), and second, that the Command
Block was executed (the C bit is one). If either is not
true, then a serious error has occurred. If there is a
completed CB present, then it is returned to the user. A
search is made for the next CB by checking the Link
field of the current CB. If it is OFFFFH, then there are
no more CBs. Begin.CBL should be set to OFFFFH in
this case and the routine exited. Otherwise SCB.CBL_
OFFSET and Begin.CBL are set equal to the address of
the next CB, START is issued, and the routine is exited. As in the simple CB add case, the last action before
leaving the ISR is to issue an EOI to the programmable
interrupt controller, PIC.

This section discusses both static and dynamic lists.
They share a very similar method of adding Command
Blocks to the end of the CBL. The major difference is
in the interrupt service routine. As a result, the algorithm for chaining commands will cover both cases,
and interrupt processing will be discussed separately.

3.5.3 Dynamic List Interrupts
3.5.1 Adding Command Blocks to
Static and Dynamic Lists

For dynamic lists, the 82586 receives an interrupt after
processing a CB with EL = 1. Figure 3-12 illustrates
the interrupt service routine. First, the basic interrupt
acknowledgement routine is used from Figure 3-9. A
pointer called CB. pointer is defined to track the CB of
immediate interest. CB. pointer is initially set equal to
Begin. CBL. It is then tested for the empty condition
(OFFFFH), and if empty the routine is exited. If not,
the CB itself (pointed to by the CB.pointer) is obtained
and the C bit of the CB is examined for completion of
execution. If set, the CB. pointer is updated with the
location of the next CB (i.e. the CB Link field of the
used CB) and the used CB is returned to the handler.
The process repeats until the end of theCBL is found.
If the C bit was not set, the CU is checked for the
IDLE state, and is restarted if required. In either case,
EOI is executed, and the procedure is exited.

To add a CB to the list, the ULCS will most likely call
a procedure that does it. A procedure for CB chaining
for static and dynamic lists is shown in Figure 3-10.
The handler defines two pointers: Begin.CBL and
End.CBL. Begin.CBL locates the first CB on the list
while End. CBL locates the last CB. If there are no CBs
on the list then Begin.CBL is set to OFFFFH. The
pointers bound the list of CBs as defined by the CPU.
The 82586 will operate on all or some part of the CBs
on the list.
The procedure' shown in Figure 3-10 first clears the
CB's C and B bits, sets the I' and EL bits to one, and
sets the Link field to OFFFFH. It will then examine
Begin.CBL. If Begin.CBL = OFFFFH,. there are no

3-8

LAN COMPONENTS USER'S MANUAL

CB.El ~ 1
CB.C ~ B ~ 0
CB liNK ~ OFFFFH
CB.CMD ~ (DESIRED VALUE)

r---------'--<

BEGIN.CBl ~ OFFFFH?

YES

>----------,
NO

BEGIN.CBl ~ CB ADDRESS
END.CBl ~ CB ADDRESS

NO

230814-60

NOTES:
1. Placement of this statement is critical. For example, if EL is set to zero before CB Link is valid, the 82586 could go to
an invalid CB address.
2. For static lists, EL = 1, and this line is not required.

Figure 3-10. Procedure to Chain CBs: Process One CB at a Time (Static List),
or Multiple CBs (Dynamic List)

3-9

LAN COMPONENTS USER'S MANUAL

>-..:.Y::.E::,S--i~ [ERROR)

>----"N.:..:O~--i~ [ERROR)

YES

BEGIN.CB~

- OFFFFH

230814-61

Figure 3-11. Interrupt Service Procedure for Static Lists (EL Bit Set in all CBs)

3-10

LAN COMPONENTS USER'S MANUAL

YES
>------1
..

EXIT

YES

230814-62

Figure 3·12. Dynamic List Interrupt Service Routine

The major difference between static and dynamic list
interrupt processing is that in the static list case there
will always be exactly one completed Command Block
whenever SCB.CX is one. With dynamic lists there
may be zero, one, or serveral completed commands and
the user must always determine which case applies. In
most systems, it is not worth the additional overhead
trying to handle the processing of dynamic lists when it
is unlikely that multiple Command Blocks will ever be
found on the Command List anyway.

3.5.4 CU Command Simplification
From the discussion above, it was shown that CBs
could be added to the CBL without using the SUSPEND and RESUME commands.
By adhering to the approach set forth above, the programmer can eliminate the complexity of managing 2
additional control commands. No performance pel),alty
is paid because from the software execution viewpoint,
all CU commands are equivalent.

3-11

LAN COMPONENTS USER'S MANUAL

The approach works because when the CU recognizes
an EL = I, it goes directly to the IDLE state without
reading th~ Link field. This rule allows the handler to
specify location OFFFFH as the empty condition,
'
which is helpful in managing CBs.
It will be shown in the next section that RESUME and

the lists that the CPU operates on may contain blocKs
that the 82586 either has already processed or does not
know are present (in the sense of being past the 'last
'block' ,as viewed by the 82586). The BEGIN pointers
are used by interrupt routines for searching purposes.
The END pointers are used to designate a true end of
the RDL and FBL.

SUSPEND are not required to append FDs and RBDs
to the Receive Data and Free Buffer lists.

An interesting problem occurs in receive frame processing that does not occur in CB processing, namely 'orphan Buffer Descriptors.' Consider the case of 20
RBDs, each 128 bytes long, and 3 FDs. If tl:iree short
frames are received, there will be 17 'RBDs' without
any FOs present (they have become 'orphans'). That is,
the RBDs do not have a FD to point to them. The
following algorithms will also deal with this problem by
use of the BEGIN_FBL and END_FBL pointers.

3.6 RECEIVE FRAME PROCESSING
The 82586's automatic receive buffer chaining management capability is one, of its most powerful features.
This capability affords efficient memory usage which in
turn can result in fewer lost frames due to lack of buffers. In order to gain the greatest advantage from this
capability, .the software must be able to dynamically
handle interrupts reclaim and add FDs/RBDs to the
Receive Frame Area, RFA. 'Dynamically' here means
that the CPU need not halt or suspend the RU in order
to add either FDs or RBDs.
'

Before presenting the actual algorithms, it is helpful to
recall how the RU itself operates on the RBL and FBL.
First, the RU never modifies links between individual
FDs and between individual RBDs. Second, the RU
l1pdates the RBD_OFFSET field in the FO to point to
the next free RBD. nird, the RU only reads the
RFA-OFFSET field in the SCB at START; the 82586
never modifies this field.

The RFA can be divided into two lists: the Received
Data List, RDL, and the Free Buffer List, FBL (see
Figure 3-13). The RDL is the list of free FOs while the
FBL is the list of free RBDs. The basiC technique to
make additions to the RDL and FBL is similar to adding CBs as described for dynamic lists in section 3.5. As
before, use of the RU commands SUSPEND and RESUME is not required.

3.6.1 Supplying FDs to the RDL
The first task of concern is how to place free FDs onto
the RDL. Free FOs may be placed on the RDL in two
instances. First, at startup'time when the 82586 is provided with its initial pool of FDs. Second, when the
ULCS is done with a received frame and is returuing
the FDs and RBDs to the handler. A likely method to
give FDs to the handler is to call ,a subroutine. This
routine can be called 'Supply FD.' Supply_FD places
new FOs to the end of the RDL, see Figure 3-14.
SupplyJD first initializes the new FD by setting
EL = 1 and LIN~OFFSET and RBD_OFFSET
= OFFFFH. Setting LINK....:..OFFSET to OFFFFH indicates that the FO is the last block on the RFA insofar
as the CPU is concerned (the 82586 usesEL).
Initializing the RBD OFFSET is critical to avoid sys·
tem hangups. A check is then made to determine if the
RFA is empty (i.e. BEGIN.RFA = OFFFFH). If it is,
the BEGIN and END RFA pointers are set to the address of the FD. The RU is not started because there is
only one FD available to the 82586 (see section 3.6.4).
The routine returns back to the handler.

END_FBL

230814-63

Figure 3-13. The Receive Frame Area
In otder to operate on the RDL and FBL, a pair of
pointers is needed for each list. The pointers BEGiN~
RFA and END~FA are used to indicate the beginning and end of the RFA. The pointers BEGINJBL
and END_FBL are used to indicate the beginning and
end of the FBL. It should be noted that 'beginning' and
'end' here refer to how the CPU views the lists, not the
82586. As in the case of the chained Command Blocks,

If the RFA is not empty, the FD is appended to the end
of the list. First, interrupts from the 82586 are masked
off to prevent an interrupt service routine from modifying the RDL. The last FD.LINK OFFSET (i.e. the FD
that was the last one on the list prior to the subroutine
call) is updated to the address of the FD to be added to
the list. The EL bit of this last FD is set to 0, and the

3-12

LAN COMPONENTS USER'S MANUAL

,------------,

YES
BEGIN.RFA ~ FD ADDRESS
END.RFA ~ FD ADDRESS

REENABLE 82586 INTERRUPTS

230814-64

Figure 3-14. Procedure to Add FDs to the RDL

End RFA pointer is updated to point to the 'new' last
FD. To prevent system failure, the liIik to the new FD
must be established before the EL bit in the 'old' last
FD is set to zero. Finally, interrupts from the 82586 are
unmasked, and the RU may be restarted as described in
section 3.6.4.

If the FBL is not empty, the RBD is appended to the
end of the list. First, interrupts from the 82586 are
masked off to prevent an interrupt service routine from
modifying the RDL. The last RBD.LINK OFFSET
(i.e. the RBD that was the last one on the list prior to
the subroutine call) is updated to the address of the
RBD to be added to the list. The EL bit· of this last
RBD is set to 0, and the End RDL pointer is updated
to point to the 'new' last RBD. To prevent system failure, the link to the new RBD must be established before the EL bit in the 'old' last RBD is set to zero.
Finally, interrupts from the 82586 are unmasked, and
the RU may be restarted as described in section 3.6.4.

3_6.2 Supplying RBDs to the FBL
The process of adding RBDs to the FBL is very similar
to that for adding FDs to the RDL. As with the FDs
there is likely to be a routine called 'Supply_RBD'.
Supply_RBD places new RBDs at the end of the FBL
(see Figure 3-15).

The two routines Supply_FD and Supply~BD were
constructed to illustrate the algorithms. In most real
systems, it is· likely that the actual routines would differ
slightly from the ones discussed. The Supply_FD routine would likely accept FDs with a list of attached
RBDs. Returning linked FDs and RBDs is useful since
most of the time a previously received frame consisting
of one RD and at least one RBD will be returned to the
handler. Likewise the Supply~BDroutine could also
accept a list of RBDs instead of just one. The processing is slightly more complex but takes advantage of ~he
already existing lists instead of first taking the lists
apart and then putting them back together again.

Supply~BD first initializes the new RBD by setting
EL = 1 and LINK OFFSET. Setting LIN~OFF­
SET to OFFFFH indicates that the RBD is the last
block on the FBL insofar as the CPU is concerned (the
82586 uses EL). A check is then made to determine if
the FBL is empty (i.e. Begin FBL = OFFFFH). If it is,
the BEGIN and END FBL pointers are set to the address of the RBD. The RU is not started because there
is only one RBD available to the 82586, (see section
3.6.4). The routine returns back to the handler.

3-13

LAN COMPONENTS USER'S MANUAL

230814-65

Figure 3-15. Procedure to Add RBDs to theFBL
the FD's C bit is set, then the location of the next FD is
taken from the FD,LINK and stored in Begin_RFA.
The new beginning of the FBL is located by examining
the RBD pointed at by the RBD_OFFSET field of the
completed FD. A search is performed by examining.
each RBD until the one with EOF set is found. This
RBD is the last RBD used by the completed FD. The
next RBD (provided that RBD does not also have EL
set) is the new first RBD on the FBL. Its address
should be stored in BegiIL-FBL. When this procedure
is done, the FD and associated RBDs are forwarded to
the user and FD.pointer is set to the next FD. This
process continues until either the end of the RDL is
found or a FD with the C bit not set is located.

3.6:3 Receive Interrupt Processing
The procedure for handling receive frame interrupts is
shown in Figure 3-16. There are basically three phases
to receive. interrupt processing. The first phase is to
acknowledge receipt of the interrupt from the 82586 (as
was done in Figure 3-9). The second phase is to remove
any receiv:ed frames from the RFAand update the
pointers to the RDL and FBL. The third phase is to
restart the RU if it is not in the READY state. The first
phase is described in section 3.4.2.
The second phase begins by examining the FR bit in the
SCB status field. If it is set, then there may be received
frames present. (It should be noted that the word 'mai
is used. Ii is possible that the received frames had been
already removed during previous interrupt service
processing). To locate received frames the following algorithm is used. A Frame Descriptor pointer,
FD.pointer, is defined to access FDs. FD.pointer is initially set to the location of the first knoWn free FD
(contained in Beg~A). This location is first tested
for the empty case (OFFFFH) and if empty, processing
is terminated on the FDL. If a FD is present, then it is
tested to see if reception of th,e frame was completed
(the C bit is checked). If not, the second phase is coinpleted and processing moves on to the third phase. If

The third phase is concerned with restarting the RU if
required. The RU may be in either the IDLE or NORESOURCES state and may need to be restarted. The
rules for doing this are presented in the next' section,
3.6.4.
3.6~4

Rules for Starting theRU

Care must be taken when restarting the RU after adding FDs and RDBs. The following rules are helpful to
ensure smooth processing:
1) It is unnecessary to restart the RU if it is already
.running (i.e. in the READY state).
3-14

LAN COMPONENTS USER'S MANUAL

ISR

>-__Y.:..:E=S'--_ _.EXIT

YES

NO

230814-66

Figure 3-16. Receive Frame Interrupt Processing Routine

2) There should be at least 2. available FDs on the
RDL. For example, if the first FD has EL = 1, then
theRU will ignore all remaining FOs. In this case,
the RU will go into the NO RESOURCES state after a frame is received. If two or more FDs are available, the RU will stay active because it hasn't seen
EL = I.
3) There should be at least 2 RBDs available to the RU
before starting.

3.6.5 Considerations in Using Receive
Buffers

A procedure for starting the RU is shown i~ Figure 317. The procedure begins by checking the rules set
forth above (it is assumed that SUSPEND is not used).
The RBD_OFFSET of the first FD is set to the beginning of the FBL (using the Begin.FBL pointer). The

In using the linked buffer structures present with the
82586 there are several important considerations related to how many receive buffers are required and how
large should they be. Although the ·exact numbers will
depend upon the performance and available memory in

procedure waits for the SCB command field to be zero;
this check ensures that there are no pending commands
to the 82586. The RFA offset in the SCB is set to location of the first FD in the list. The RU is then started.
Channel Attention is given, and the routine is exited.

3-15

LAN COMPONENTS USER'S MANUAL

YES

NO
PROCESS INTERRUPTS, SEE FIGURE 3-9

NO

NO

NO
NO

230814-68
230814-67

Figure 3·17. RU Start Procedure

Figure 3·18. Combined Command and Receive
Interrupt Service Routine

3-16

LAN COMPONENTS USER'S MANUAL

a particular system, there are some general guidelines
that can be established. These guidelines are:
1) The size of the receive buffer should completely contain the usual 'small' message of the network. In
most networks up to 75% of the frames will be
'small'. This number should be determined and the
size of receive buffers set to be slightly greater than·
this value. In many networks, a value of 100 to 128
bytes is adequate. The worst case system bus bandwidth requirements is when every frame received
takes two or more receive buffers.
2) The number of receive buffers depends on the acceptable loss rate of frames due to lack of buffers.
Since the CSMA/CD protocols supported by the
82586 do not offer guaranteed delivery of frames
some loss is inevitable, but if too many are lost there
will be significant network performance degradation.
The minimum number is enough to contain the largest possible frame. The designer must consider the
following questions:
a. How much traffic is going to be received? Obviously a file server will require many more buffers
than a terminal or simple workstation.

3-17

b. How long does it take the processor to process
and return a received frame? For a given level of
performance, the longer the processing time, the
more buffers will be required.
c. What is the maximum number of back to back
frames that can be expected in normal operation
and how big will they be? There should be enough
buffers to contain them.
In trying to determine the optimum number of receive
buffers, it is helpful to use the Resource Error tally in
the SCB. This tally will record the number of frames
lost to insufficient buffer resources. In most systems a
value of five to ten percent of the total received frames
is acceptable.
.

3.7 COMBINING RECEIVE AND
COMMAND PROCESSING
The discussions in section 3.4 and 3.5 assumed that the
Receive and Command interrupt processing were performed in isolation. In practice the two procedures are
combined as shown in Figure 3-18. In the previously
described routines, redundant servicing routines (Save
Registers, Process Interrupts, EOI and Exists) would
be performed only once in the combined case.

82586 Data Link Driver

4

APPLICATION
NOTE

AP-235

September 1985

An 82586 Data Link Driver

CHARLES YAGER

Order Number: 231421-001
4-1

inter

AP-235

• Data Link Driver (OLD): drives the 82586, also
known as the 82586 Handler.
• Logical Link Control (LLC): implements the IEEE
802.2 standard.
• User Application (UAP): exercises the other software modules and runs a specific application.
• C hardware support: written in assembly language,
supports the Intel C compiler for 110, interrupts,
and run time initialization for target hardware.

4.0 INTRODUCTION
This application note describes a design example of an '
IEEE 802.2/802.3 compatible Data Link Driver using
the 82586 LAN Coprocessor. The design example is
based on the "Design Model" illustrated in Chapter 3
of the LAN Components User's Manual, "Programming the 82586". It is recommended that before reading this application note, the reader clearly understands
the 82586 data structures and the Design Model given
in Chapter 3.

Figure 4-1 illustrates how these software modul~ combined with the 82586, 82501 and 82502 complete the
first two layers of the OSI model. The 82502 implements an IEEE 802.3 compatible transceiver, while the
82501 completes the Physical layer by performing the
serial interface encode/decode function.

.Chapter 3 discusses two basic issues in the design of the
82586 data link driver. The first is how the 82586 handler fits into the operating system. One approach is that
the 82586 handler is treated as a "special kind of interface" rather than Ii standard I/O interface. The special
interface means a special, driver that has -the advantage
of utilizing the 82586 features to enhance performance.
However the performance enhancement is at the expense of device dependent upper· layer software which
precludes the use of a standard I/O interface.

The Data Link Layer, as defined in the IEEE 802 stan-'
dard documents, is divided into two sUblayers: the Logical LinkControl (LLC) and the Medium Access Control (MAC) sublayers. The Medium Access Control
sublayer is further divided into the 82586 Coprocessor
plus the 82586 Handler. On top of the MAC is the LLC
software module which provides IEEE 802.2 compatibility. The LLC software module implements the Station Component responses, dynamic addition ~d deletion of Service Access Points (SAPs), and a class I level
of service. (For more information on the LLC sublayer,
refer to IEEE 802.2 Logical Link Control Draft Standard.) The class 1 level of service provides a connectionless datagram interface as opposed to the class 2
level of service which -provides a Connection oriented
level of service similar to HDLC Asynchronous Balanced Mode.

The second issue Chapter 3 discusses is which algorithms to choose for the CPU to control the 82586. The
algorithms used in this data link design are taken directly from Chapter 3. Command processing uses a linear static list, while receive processing uses a linear dynamic list.
.
The application example is written in C and uses the
Intel C compiler. The target hardware for the Data
Link Driver is the iSBC 186/51 COMMputer.

4.1 FITTING THE SOFTWARE INTO
THE OSI MODEL

On top of the Data Link Layer is the Upper" Layer
Comniunications Software (ULCS). This contains the
Network, Transport, Session, and Presentation Layers.
These layers are not included in the design example,
therefore the application layer of this ap note interfaces
directly to the Data Link layer.

The application example consists-offour software modules:

051 REFERENCE
MODEL LAYERS

UAP MODULE
ULCS
LLC MODULE
DLD MODULE

APPLICATION
PRESENTATION

82586

SESSION

USER APPLICAl10N
UPPER LAYER COMMUNlCAl1ON SOnwARE
LOGICAL UNK CONTROL
82586 HANDLER
DATA UNK COPROCESSOR
ENCODE/DECODE (ESI)

TRANSPORT
TRANSCEIVER CABLE
NETWORK
DATA LINK

,

PHYSICAL

HARDWARE CONNECTOR

231421-1

Figure 4-1_ Data Link Driver's Relationship to OSI Reference Mode 1
4-2

intJ

AP-235

) APPLICATION

DATA LINK

T£RMINAL EMULATOR
AND
STATION MONITOR

OLD MODULE

82586

P

rO;AP

I

DATA

I

TAIL

< ........

I SSAP I CONTROL I ~~AI

Description .

LLC Functions

231421-14

Initializes the DSAP
address table and calls
IniL586()
Add_Dsap_
Add a DSAP address to
Address (dsap, pfunc) the active list
dsap - DSAP address
pfunc - pointer to the
SAP function
Delete a DSAP address
Delete-DsapAddress (dsap)
dsap - DSAP address
Recv-Frame (pfd)
Receives a frame from
the 82586 Handler
pfd - Frame Descriptor
Pointer
Station-Component- Generates a response to
Response (pfd)
frame addressed to the
Station Component
pfd - Frame Descriptor
Pointer

IniLLlc()

Figure 4-16. IEEE 802.2 Class 1 Frame Format

From Figure 4-15 it can be seen that there are no LLC
class 1 VI responses because information frames are not
acknowledged at the data link leveL The only command frames that may require responses are Xln and
TEST. If a command frame is addressed to the Station
Component, it checks the control field to see what type
of frame it is. If it's an XIn frame, the Station Component responds with a class 1 XIn response frame. If it's
a TEST frame, the Station Component responds with a
TEST frame, echoing back the data it received. In both
cases, the response frame is addressed to the source of
the command frame.

a

4-14

inter

AP-235

4.4.1 Adding and Deleting LSAPs

Terminal Mode - implements a virtual terminal with
datagram capability (conneci:ionless "class I" service).
This mode can also be thought of as an async to IEEE
802.2/802.3 protocol converter.

When a user process wants to add a LSAP to the active
list, the process calls Add__Dsap_Address(dsap,
pfunc). The dsap parameter is the actual DSAP. address, and the pfunc parameter is the address of the
function to be called when a frame with the associated
DSAP address is received.

Monitor Mode - allows the station to repeatedly transmit any size frame to the cable. While in the Monitor
Mode, the terminal provides a dynamic update of 6
station related parameters.

The LLC module maintains a table of active dsaps
which consists of an array of structures. Each structure
contains two members: stat - indicates whether the address is free or inuse, and (*p_sap_func)() contains
the address of the function to call. The index into the
array of structures is the DSAP address. This speeds up
processing by eliminating a linear search. Delete_
Dsap_Address (dsap) simply uses the DSAP index to
mark the stat field FREE.

High Speed Transmit Mode - sends frames to the cable
as fast as the software possibly can. This mode demonstrates the throughput performance of the Data Link
Driver.
Change Transmit Statistics - When Transmit Statistics
is on several transmit statistics are gathered during
transmission. If Transmit Statistics is off, statistics are
not gathered and the program jumps over the section of
code in the interrupt routine which gathers these statistics. The transmission rate is slightly increase when
Transmit Statistics is off.

4.5 APPLICATION LAYER
For most networks the application layer resides on top
of several other layers referred to here as ULCS. These
other layers in the OSI model run from the network
layer through the presentation layer. The implementation of the ULCS layers is beyond the scope of this
application note, however Intel provides these layers as
well as the data link layer with the OpenNET product
line. For the purpose of this application note the application layer resides on top of the data link layer and its
use is to demonstrate, exercise and test the data link
layer design example.

Print All Counters - Provides current information on
the following counters.
Good frames transmitted:
Good frames received:
CRC errors received:
Alignment errors received:

Out of Resource frames:
Receiver overrun frames:

Each time a frame has been successfully transmitted the
Good frames transmitted count is incremented. The
same holds true for reception. eRC, Alignment, Out of
Resources, and Overrun Errors are all obtained from
the SCB. Underrun, lost CRS, SQE error, Max retry,
and Frames that deferred are all transmit statistics that
are obtained from the Transmit command status word.
82586 Reset is a count which is incremented each time
the 82586 locks up. This count has never normally been
incremented.

There can be several processes sitting on top of the data
link layer. Each process appears as a SAP to the data
link. The UAP module, which implements the application layer, is the only SAP residing on top of the data
link layer in this application example. Other SAPs
could certainly bl! added such as additional "connectionless" terminals, a networking gateway, or a transport layer, however in the interest of time this was not
done.

4.5.1 Application Layer Human
Interface
The UAP provides a menu driven human interface viaan async terminal connected to port B on the iSBC
186/51 board. The menu of the commands is listed in
Figure 4.17 along with a description that follows:
T - Terminal Mode
X - High Speed Transmit Mode
P - Print All Counters
A - Add a Multicast Address
S - Change the SSAP Address
N - Change Destination Node Address
R - Re-Initialize the Data Link

M - Monitor Mode
V - Change Transmit Statistics
C - Clear All Counters
Z - Delete a Multicast Address
D - Change the DSAP Address
L - Print All Addresses'
B - Change the Number Base

Figure 4-17. Menu of Data Link Driver Commands

4-15

AP-235

Clear All Counters - Resets all of the counters.

reinitialized, and the selftest diagnostic and loopback
tests are executed. The results of the diagnostics are
printed on the terminal. The possible output. messages.
from the 82586 selftest diagnostics are:

Add/Delete Multicast Address - Adds and Deletes
Multicast Addresses.
Change SSAP Address - Deletes the previous SSAP
and adds a new one to the active list. The SSAP in this
case is this stations LSAP. When a frame is received,
the DSAP address in the frame received is compared
with any active LSAPs on the list. The SSAP is also
used in the SSAP field of all transmitted frames.

Passed Diagnostic Self Tests
Failed: Self Test Diagnose Command
Failed: Internal Loopback Self Test
Failed: External Loopback Self Test
Failed: External Loopback Through Transceiver Self
Test

Change DSAP Address - Delete the old DSAP and add
a new one. The DSAP is the address of the LSAP
which all transmit frames are sent to.

Change Base - Allows all numbers to be displayed in
Hex or Decimal.

Change Destination Node Address - Address a new
node.

4.5.2 A Sample Session

Print All Addresses - Display on the terminal the station address, destination address, SSAP, DSAP, and all
multicast addresses.

The following text was taken directly from running the
Data Link software on a 186/51 board. It begins with
the. iSDM monitor signing on and continues into executing the Data Link Driver software.

Re-initialize Data Link - This causes the Data Link to
completely reinitialize itself. The 82586 is reset and

iSDM 86 Monitor, Vl.O
Copyright 1983 Intel Corporation
.G DOOO:6
•• ****.** •••••••••••••••• * •• ****.*******************************

• 82586 IEEE 802.2/802.3 Compatible Data Link Driver •

*

•

• *.*.** •••• *************.**.************************.*.*********

Passed Diagnostic Self Tests
Enter the Address of the Destination Node in Hex -> OOAA0000179E
Enter this Station's LSAP in Hex - > 20
Enter the Destination Node's LSAP in Hex - > 20
Do you want to Load any Multicast Addresses? (Y or N) -> Y
Enter the Multicast Address in Hex -> OOAAOOllllll
Would you like to add another Multicast Address? (Y or N) -> N
This Station Host Address is: OOAA00001868
The Address of the Destination Node is: 00AA0000179E
This Station's LSAP Address is: 20
The Address of the Destination LSAP is: 20
The following Multicast Addresses are enabled: OOAAOOllllll
4-16

intJ

AP-235

Commands are:
T - Terminal Mode

M - Monitor Mode

x-

v-

High Speed Transmit Mode

Change Transmit Statistics

P - Print All Counters

C - Clear All Counters

A - Add a Multicast Address

Z - Delete a Multicast Address

S - Change the SSAP Address

D - Change the DSAP Address

N - Change Destination Node Address

L - Print Ail Addresses

R - Re-Initialize the Data Link

B - Change the number Base

Enter a command, type H for Help - > P
Good frames transmit ted:

24

Good frames received:

1

CRC errors received:

0

Alignment errors received:

0

Out of Resource frames:

0

Receiver overrun frames: .

0

82586 Reset:

0

Transmit underrun frames:

0

Lost CRS:

0

SQ,E errors:

9

Maximum retry:

0

Frames that deferred:

4

Enter a command, type H for Help --> T
Would you like the local echo on? (Y or N) --> Y
This program will now enter the terminal mode.
Press hC then CR to return back to the menu
Hello this is a test.
/*AC CR • /
Enter a command, type H for Help --> M
Do you want this station to transmit? (Y or N) --> Y
Enter the number of data bytes in the frame --> 1500
Hit any key to exit Monitor Mode.
of Good
Frames
Transmitted
#

32

#

of Good
Frames
Received

o

CRC
Errors

Alignment
Errors

00000

/* CR • /
Enter a command, type H for Help --> X
Hit any key to exit High Speed Transmit Mode.

/* CR • /
Enter a command, type H for Help --> R
Passed Diagnostic Self Tests
4-17

00000

Receive
No
Resource Overrun
Errors
Errors
00000

00000

inter

AP-235

4.5.3 Terminal Mode
The Terminal mode buffers characters received from
the terminal and sends them in a frame to the cable.
When a frame is received from the cable, data is extracted and sent to the terminal. One of three events
initiate the UAP to send a frame providing there is data
to send: buffering more than 1500 bytes, receiving a
Carriage Return from the terminal, or receiving an interrupt from the virtual terminal timer.
The virtual terminal timer employs timer I in the 80130
to cause an interrupt every .125 seconds. Each time the
interrupt occurs the software checks to see if it received
one or more characters from the terminal. If it did, then
it sends the characters in a frame.

the 8274 transmit interrupt is enabled is when the Receive FIFO has data in it. The receive FIFO is filled
from frames being received from the cable. Each time a
transmit interrupt occurs a byte is' removed from the
Receive FIFO and written to the 8274. When the Receive FIFO empties, the 8274 transmit interrupt is disabled.
The flow control implemented for the terminal interface is via RTS and CTS. When the Transmit FIFO is
full, RTS goes inactive preventing further reception of
characters. If the Receive FIFO is full, receive frames
are lost because there is no way for the data link using
class I service to communicate to the remote station
that the buffers are full. Lost receive frames are accounted for by the Out of Resources Frame counter.

The Async Terminal bit rate sets the throughput capability of the station in the terminal mode because the
bottle neck for this network is the RS232 interface. Using this fact a simple test was conducted to verify the
data link driver's capability of switching between the
receiver's No Resource slate and the Ready State. For
example if station B is sending frames in the High
Speed Transmit mode to station A which is in the TerThe serial I/O for the async terminal interface is always
minal mode, frames will be lost in station A. Under
polled except in the Terminal mode where it is interthese circumstances station A's receiver will be switchrupt driven. The Terminal mode begins by enabling the
ing from Ready state to Out of Resources state. The
8274 receive interrupt but leaves the 8274 transmit insum of Good, frames received plus Out of Resource
terrupt disabled. This way any characters received from
frames from station A should equal Good frames transthe terminal will cause an interrupt. These characters
mitted from station B; unless there were any underruns
are then placed in the Transmit FIFO. The only time
or overruns.
Table 4.1 FIFO State Table
Function
Present State
Next State
Action
FIFO_T_IN().
IN USE
Start Filling Transmit Buffer
EMPTY
IN USE
FULL
ShutOff RTS
FI FO_T_OUT( )
FULL
IN USE
Enable RTS
IN USE
Stop Filling Transmit Buffer
EMPTY
FIFO_R_IN( )
EMPTY
Turn on Txlnt
IN USE
IN USE
Stop Filling FIFO from Receive Buffer
FULL
FIFO_R_OUT( )
Start Filling FIFO from Receive Buffer
FULL
IN USE
Turn Off Txlnt
IN USE
EMPTY

The interface to the async terminal is a 256 byte software FIFO. Since the terminal communication is full
duplex, there are two half duplex FIFOs: a Transmit
FIFO and a Receive FIFO. Each FIFO uses two functions for I/O: Fifo_In() and Fifo_Out(). A block
diagram is displayed in Figure 4-18.

",

T
SEND FRAMES

RECEIVE FRAMES

ASYNC
TERMINAL

231421-15

Figure 4-18
4-18

inter

AP-235

4.5.3.1 SENDING FRAMES

The Terminal Mode is entered when the Terminal_
Mode() function is called from the Menu interface.
The Terminal_Mode() function is one big loop, where
each pass sends a frame. Receiving frames in the Ter·
minal Mode is handled on an interrupt driven basis
which will be discussed next.
The loop begins by getting a TBD from the 82586 handler. The first three bytes of the first buffer are loaded
with the IEEE 802.2 header information. The loop then
waits for the Transmit FIFO to become not EMPTY,
at which point a byte is removed from the Transmit
FIFO and placed in the TBD. After each byte is reo
moved from the Transmit FIFO several conditions are
tested to determine whether the frame needs to be
transmitted, or whether a new buffer must be obtained.
A frame needs to be transmitted if: a Carriage Return is
received, the maximum frame length is reached, or the
send_frame flag is set by the virtual terminal timer. A
new buffer must be obtained if none of the above is true
and the max buffer size is reached.
If a frame needs to be sent the last TBD's EOP bit is set
and its buffer count is updated. The 82586 Handler's
Send_Frame() function is called to transmit the
frame, and continues to be called until the function reo
turns TRVE.
The loop is repeated until a 'C followed by a Carriage
Return is recieved.
4.5.3.2 RECEIVING FRAMES

Vpon initialization the VAP module calls the Add_
Dsap_Address(dsap, pfunc) function in the LLC mod·
ule. This function adds the VAP's LSAP to the active
list. The pfunc parameter is the address of the function
to call when a frame has been received with the VAP's
LSAP address. This function is Recv_Data_l().
Recv_Data_l() looks at the control field of the
frame received and determines the action required.
The commands and responses handled by Recv_
Data_1 ( ) are the same as the Station Component's
commands and responses given in Figure 4·15. One dif·
ference is that Recv_Data_I() will process a VI
command while the Station Component will ignore a
VI command addressed to it.
# of Good

# of Good

Frames
Transmitted

Frames
Received

32

0

Recv_Data_I() will discard any VI frames received
unless it is in the Terminal Mode. When in the Terminal Mode, Recv_Data_I() skips over the IEEE 802.2
header information and uses the length field to deter·
mine the number of bytes to place in the Receive FIFO.
Before a byte is placed in the FIFO, the FIFO status is
checked to make sure it is not full. Recv_Data_l()
will move all of the data from the frame into the Re·
ceive FIFO before returning.
When a frame is received by the 82586 handler an interrupt is generated. While in the 82586 interrupt routine the receive frame is passed to the LLC layer and
then to the VAP layer where the data is placed in the
Receive FIFO by Recv_Data_I(). Since Recv_
Datal() will not return until all of the data from the
frame has been moved into the Receive FIFO, the 8274
transmit interrupt must be nested at a higher priority
than the 82586 interrupt to prevent a software lock.
For example if a frame is received which has more than
256 bytes of data, the Receive FIFO will fill up. The
only way it can empty is if the 8274 interrupt can nest
the 82586 interrupt service routine. If the 8274 could
not interrrupt the 82586 ISR then the software would
be stuck in Recv_Data_I() waiting for the FIFO to
empty.

4.5.4 Monitor Mode
The Monitor Mode dynamically updates 6 station related parameters on the terminal as shown below.
The Monitor_Mode() function consists of one loop.
During each pass through the loop the counters are
updated, and a frame is sent. Any size frame can be
transmitted up to a size of the maximum number of
transmit buffers available. Frame sizes less than the
minimum frame length are automatically padded by the
82586 Handler.
The data in the frames transmitted in the Monitor
Mode are loaded with all the printable ASCII characters. This way when one station is in the Monitor Mode
transmitting to another station in the Terminal Mode,
the Terminal Mode station will display a marching pattern of ASCII characters.

CRC
Errors

Alignment
Errors

No
Resource
Errors

Receive
Overrun
Errors·

00000

00000

00000

00000
I

inter

AP-235

buffer full status, the 8274's receive interrupt is used.
When the Hs_Xmit_Mode( ) function is entered, the
hs_stat flag is set true. If the 8274. receive interrupt
occurs, the hs_stat flag is set false. This way the loop
only has to test the hs_stat flag rather than calling
inb( ) function each pass through the loop to determine
whether a character has been received.

4.5.5 High Speed Transmit Mode
The High Speed Transmit Mode demonstrates the
throughput performance of the 82586 Handler. The
Hs_Xmit_Mode() function operates in a tight loop
which gets a TBD, sets the EOF bit, and calls Send_
Frame(). The flow chart for this loop is shown in Figure 4-19.

The performance measured on an 8 MHz ·186/51 board
is 593 frames per second. The bottle neck in the
throughput is the software and not the 82586. The size
of the buffer is not relevant to the transmit frame rate.
Whether the buffer size is 128 bytes or 1500 bytes,
linked or not, the frame rate is still the same. Therefore
assuming a 1500 byte buffer at 593 frames per second,
the effective data rate is 889,500 bytes per second.

The loop is exited when a character is received from the
terminal. Rather than polling the 8274 for a receive

This can easily be demonstrated by using two 186/51
boards running the Data Link software. The receiving
stations counters should be cleared then placed in the
Monitor mode. When placing it in the monitor mode,
transmission should not be enabled. When the other
station is placed in the High Speed Transmit Mode a
timer should be started. One can use a stop watch to
determine the time interval for transmission. The frame
rate is determined by dividing the number of frames
received in the Monitor station by the· time interval of
transmission.

231421-16

Figure 4-19. High Speed Transmit Mode
FlowChart

4-20

inter

AP-235

APPENDIX A .
COMPILING, LINKING, LOCATING, AND RUNNING THE
SOFTWARE ON THE 186/51 BOARD
*********

Instructions for using the 186/51 board

*********

Use 27128A for no wait state operation. 27128s can be used but wait states will have to be added.
Copy HI.BYT and LO.BYT files into EPROMs
PROMs go into U34 - HI.BYT and U39 - LO.BYT ,on the 186/51 board

JUMPERS REQUIRED

WIRE WRAP

Jumper the 186/51 board for 16K byte PROMs in U34
and U39 Table 2-5 in 186/51 HARDWARE REFERENCE MANUAL (Rev-OOI)

E36-E47IN
E39-E44IN
E79-E45IN

186/51(E5)

E151-E1520UT
E152-E150 IN
E94-E95IN
E100-E1061N
E107-E1131N
E133-E134 IN

186/51 (5)/186/51

E199-E203 OUT
E203-E191 IN
E120-E119IN
E116-E1121N
E111-E1071N
E94-E93IN

USE SDM MONITOR
The SDM Monitor should have the 82586's SCP
burned into ROM. The ISCP is located at OFFFOH.
Therefore for the SCP the value in the SDM ROM
should be:
ADDRESS
FFFF6H
FFFF8H
FFFFAH
FFFFCH
FFFFEH

also change. interrupt priority jumpers - switch 8274
and 82586 interrupt priorities
E36-E44 OUT
E39-E47 OUT
E37-E45 OUT

E43-E50 IN
E46-E47IN
E90-E4BIN

E43-E47 OUT
E46-ESOOUT
E44-E4BOUT

DATA
XXOOH
XXXXH
XXXXH
FFFOH
XXOOH

To run the program begin execution at ODOOO:6H

4-21

inter

AP-235

. I.E. G DOOO:6

GOOD LUCK!
submit file for compiling one module:

**********

run
cc86.86 :F6:%O LARGE ROM DEBUG DEFINE(DEBUG) include(:F6:)

exit
**********

submi t file for linking and locating:

**********

run
link86

:F6:assy.obj, :F6:dld.obj, :F6:11c.obj, &:

:F6:uap.obj, lclib.lib to :F6:dld.lnk segsize(stack(4000h»

notype

10c86 :F6:dld.lnk to :F6:dld.loc&:.
initcode (ODOOOOH) start~begin)
~ddresses(classes(data(3000H),

order(classes(dat~, stack, code»
stack(OCBOOH), code(OD0020H»)

oh86 :F6:dld.loc to :F6:dld.rom
exit
**********

submit file for burning EPROMs uSing IPPS:

ipps
i 86

f :F6:dld.rom (OdOOOOh)
3
2

1

o to :F6:1o.byt
y

1 to :F6:hi.byt
y

t 27128
·9

c :F6:10.byt t p
n

C :F6:hi.byt t p
n

exit

4-22

**********

&:

IPCO/USR/CHUCK/CSRC/DLD.H

1***************************************************** *******************

*
*
82586 Structures and Constants
*
*
*4************************************************************************1
*
1* general purpose constants *1

tldefline
tlili!f'ine
tld,;fine
tldefine
tldefine
tldefine
tldefine

o

INUSE
EMPTY
FULL
FREE
TRUE
FALSE
NULL

1
2
1
1

o
OxFFFF

1* Define Data Structures *1

tldefine
tldefine
tldefine
tldefine

RBUF_SIZE
TBUF_SIZE
ADD_LEN
MULTI_ADDR_CNT

128 1* receive buffer size *1
128 1* transmit buffer size *1
6

16

typedef unsigned short int u_shortl
1* results from Test_Link(): loaded into Self_Test char *1

tldefine
tldefine
tldefine
tldefine
tldefine

PASSED
FAILED_DIAGNOSE
FAILED_LPBK_INTERNAL

0
1
2
FAILED_LPBK~XTERNAL
3
FAILED_LPBK_TRANSCEIVER 4

1* Frame Commands *1
tldefine
UI
Ox03
tldefine
XID
OxAF
tldefine
TEST
OxE3
tldefine
Pf_BIT 0.10
C_R_BIT 0,01
tldefine

1*
1*
1*
1*
1*

Unnumbered Information Frame *1
Exchange Identification *1
Remote Loopback Test *1
Poll/Final Bit Position *1
Command/Response bit in SSAP *1

tldefine

DSAP.:...CNT

8

1* Number of allowable DSAPSl must be a multiple
of 2**N. and DSAP addresses assigned must be
divisible by 2** (8-N l.
(i. e. the N LSBs must be 0) *1

tldefine

DSAP_SHIFT

5

1* DSAP _SHIFTS must equal 8-N *1

tldefine

XID_LENGTH

6

1* Number of Info bytes for XID Response frame *1

1* System Configuration Pointer SCP *1

struct SCP

{
u_short sysbusl 1* 82586 bus width. 0 - 16 bits
1 - 8 bits *1

IPCO/USR/CHUCK/CSRC/DLD.H
u_sho"l't Junk [2JI
u_sho"l't iscplJ
1* 10llle"l' 16 bits of iscp add"l'ess *1
u_sho"l't iscphl
1* uppe"l' 8 bits of iscp add"l'ess *1
)0;

1* Inte"l'mediate System Configu"l'ation Pointe"l' ISCP *1

st"l'uct ISCP -(
u_sho"l't busy,

I*set to 1 by cpu befo"l'e its fi"l'st, CA.
clea"l'ed by 82586 afte"l' "l'eading *1
u_sho"l't offset
1* offset of system cont"l'ol block *1
u_sho"l't basel J 1* base of system cont"l'ol block *1
u_sho"l't base2 J
)0

1

1* System Cont"l'ol Block SCB *1

st"l'uct SCB

-(

u - sho"l't
u sho"l't
u_sho"l't
u_shO"l't
u_sho"l't
u sho"l't
u_sho"l't
u_sho"l't

stat,

1* Status IIIo"l'd *1
cmdi
1* Command IIIo"l'd *1
cbl _offset; 1* Offset of fi"l'st command block in CBL *1
"l'fa_offset; 1* Offset of fi"l'st f"l'ame desc"l'ipto"l' in RFA *1
ere_errs;
1* CRC e"l'"I'o"l's accumulated *1
aln _IP"'1"' 5;
1* Alignment e"l'"I'o"l'5 *1
1'51:_&"1"5;
1* F"I'ames lost because of no Resou"l'ces *1
__ r1'.;
ov"I'
1* Ove"l'fun er"l'o"l's *1

)0,

1*

Command Block *1
st"l'uct

CB

-(

u_sho"l't
u_stio"l't
u_sho"l't
u sho"l't
u_sho"l't
u_sho"l't
u- sho"l't
u sho"l't
u:::sho"l't

'stat,
cmd;
linkJ
pa"l'ml,
pa"l'm2J
pa"l'm31
pa"l'm4J
pa"l'm5J
pa"l'm61

1*
1*
1*
1*

Status of Command *1
Command *1
link field *1
Pa"l'amete"l's *1

)oj

1*

Multicast Add"l'ess Command Block MA_CB *1
U_ShD"I't stat,
1* Status Df Command *1
u_sho"l't cmdl
1* Command ~I
u_sho"l't link;
1* Link field *1
u_sho"l't mc_cnt; 1* Numbe"l' of MC add"l'esses *1
cha"l' mc_add"l' [ADD_LEN*MULTI_ADDR_CNTJI 1* MC add"l'ess
)0;

1* T"I'ansmit Buffe"l' Desc"l'ipto"l' TBD *1

st"l'uct TBD

-C,

4-24

a"l'ea

*1

IPCO/USR/CHUCK/CSRC/DLD.H
u_short act_cnt)
1* Numb&r of bytes in buffer *1
u_short link)
1* offset to next TBD *1
u_short buff_l;
1* lower 16 bits of buffer address *1
u_short buff hI
1* upper 8 bits of buffer address *1
struct TB *buff Jltr;
1* not used by the 586: used by the
software to save address translation
routine.
*1

1* Transmit Buffers *1
.truct TB

{
char data ETBUF_SIZEl;
};

1* Frame Descriptor FD *1
struct

FD

{
u_short stat;
1* Status Word of FD *1
u_short el_s;
1* EL and S bits *1
u_short link)
1* link to next FD' *1
u_short rbd_offset)'
1* Receive buffer descriptor offset *1
char dest_addrEADD_LENl)/*Destination address *1
char src_addrEADD_LENl; 1* Source address *1
u_short length;
1* Length field *1
})

1* Receive Buffer Descriptor RBD *1
struct RBD {

1*
1*
1*
1*
1*
1*

Actual number of bytes received *1
Offset to next RBD *1
Lower 16 bits of buffer address *1
upper 8 bits of buffer address *1
size of buffer *1
not used by the 586: used by the
software to save address translation
routine. *1

u_short act_cnt;
u_sh ort link;
u_"hort buff_l;
u_short buff _hI
u_short size;
struct RB *buffJltr;
};

1* Receive Buffers *1
struct RB

{
char dataERBUF_SIZEJ;
};

struct

FRAME_STRUCT
{

unsigned char
unsigned char
unsigned char

dsap;
ssap;
cmd.i

1* Destination Service Access Point *1
1* Source Service Access Point *1
1* ISO Data Link Command *1

};

1* LSAP Address Table *1
struct

LAT {
char

stat;

1* INUSE or FREE *1

4-25

IPCO/USR/CHUCK/CSRC/DLD,H
int

struct MAT -(
char
char

(*p_sap_func)(),/* Pointer to LSAP function.' associated
~ith dsap address *1

stat.
addrCADDJ.ENJl

1* Multicast Address T~ble *1
1* INUSE or FREE *1
1* actual mc address *1

)0.

1* general purpose flags *1

struct FLAGS
unsign.d
unsigned
unsigned
unsigned
unsigned
unsigned

-(
dias_done
stat_on :
reset_sema:
reset-pend:
Ipbk_test:
Ipbk_mode:

1.
1 •
1 •
1
1 •

1*
1*
1*
1*
1*
1*

diagnose command complete *1
diagnostic statistics onlo"
don't reset when this bit is set *1
reset when this bit i • • et *1
loopback test flag *1
loop'back mode onloff' *1
net~ork

)0 I

1* general purpose bits *1

.define
.define
.define
.define
.define
.define
.define

ELBIT
EOFBIT
SBn
IBIT
CBIT
BBIT
OKBIT

Ox 8000
Ox8000
Ox 4000
Ox2000
Ox 8000
Ox 4000
Ox2000

1* SCB patterns *1

.define
.define
.define
.define
.define
• define
.define
.define
.define
.define
.de'ine

CX
FR
CNA
RNR
RESET
CU_START
RU_START
RU_ABORT
CU_MASK
RU_MASK
RUjREADV

·Ox8000
Ox4000'
Ox2000
Ox 1000
Ox0080 .
OxOl00
Ox0010
Ox0040
Ox 0700
Ox0070
Ox0040

1* 82586 Commands *1

.define
.define
.de'ine
.define
.define
.define
.define
.define

NOP
IA
.CONFIQURE
MC_SETUP
TRANSMIT
TDR
DUMP
DIAGNOSE

OxOOOO
0.0001
0.0002
0.0003
0.0004
0.0005
010006
010007

4-26

*i

IPCO/USR/CHUCK/CSRC/DLD.H

1* 82586 Command and Status Masks *1
*define
*define
*define
*definR
*define
*define
*define
*define
*define

CMD_MASK
Ox0007
NOERRBIT
Ox2000
COLLMASK
OxOOOF
DEFERMASK
Ox0080
NOCRSMASK
Ox0400
UNDERRUNMASK
Ox0100
SGEMASK
Ox0040
MAXCOLMASK
Ox0020
OUT_OF_RESOURCES 0.0200

1* Configure ParamRters *1
Ox0800
1*
*define FIFO_LIM
O.OOOB
*define BYTE_CNT
Ox0040
*define SRDY
Ox0080
*define SAV_BF
ADDR_LEN
Ox0600
*define
1*
Ox0800
*define AC_LOC
0.2000
*define PREAM LEN
1*
Ox4000
*define INT_LPBCK
0.8000
*define EXT_LPBCK
OxOOOO
*define LIN.]>RIO
1*
OxOOOO
*define ACR
BOF
_MET
Ox0080
*define
Ox6000
*define IFS
1*
Ox0200
*define SLOT _TIME
1*
OxFOOO
*define' RETRY_NUM
1*
OxOO01
*define PRM
0.0002
*define BC_DIS
*define MANCHESTER 0.0004
0.0008
*define TONO_CRS
0.0010
*define NCRC_INS
0.0020
*define CRC_16
0.0040
*define BT_STUFF
0.0080
*define PAD
0.0000
*define CRSF
1*
CRS_SRC
0.0800
*define
0.0000
CDTF
*define
1*
0.8000
*define CDT_SRC
*define MIN_FRM_LEN 0.0040
1*
*define MIN_DATA_LEN MIN_FRM_LEN *define MAX_FRAME_SlZE

use FIFO lim of 8 *1

address length of 6 bytes *1
preamble length of 8 bVtes *1
no prioritv *1
IFS time 9.6 usec *1
slot time 51.2 usec *1
retrv number 15 *1

no carrier sense filter *1
no collision detect filter *1
64 bvtes *1
18
1* assumes Ethernet/IEEE 802.3
frames ~ith 6 bvtes of address *1

1500 - 3

4-27

IPCO/USR/CHUCK/CSRC/DLD.C

1************************************************************************

*

*

82586 Handler
*
*
*
**************************************************************************1

I,,:

Define constants for storage area *1

.define
.define
.define
.define

CB_CNT
FD_CNT
RBD_CNT
TBD_CNT

8
16
64
16

1*
1*
1*
1*

Number
Number
Number
Number

of
of
of
of

available
available
available
available

Command Blocks *1
Frame Descriptors *1
Receive Buffer descriptors *1
Transmit Buffer descriptors *1

1* loopback parameters passed to Configure() *1
.define INTERNAL_LOOPBACK
.define EXTERNAL_LOOPBACK
.define NO_LOOPBACK

0.4000
0.8000
OxOOOO

.include "dId. h"

1* 586 Data Structures *1

1* 186 Timer Addresses *1
.define
.define
.define
.define

TIMERl CTL
TIMERl:CNT
TIMER2_CTL
TIMER2_CNT

OxFF5E
OxFF58
OxFF66
OxFF60

1* external functions *1
1* 1/0 *1
int
void
void
void
void

inw();
1*
outw();
1*
init_intv()I/*
enable();
1*
disable();
1*

extern

char

input word: inw(addre55) *1
output word: outw(address. value) *1
initialize the interrupt vector table *1
enable 80186 interrupts *1
diuble 80186 interrupts *1

SEGMT;
*pNULL;

1* Data segment value *1
1* NULL pointer *1

1* Macro 'tvpe' of definitions *1
.define CA

outw(OxC8.0)

1* the command to issue a Channel Attention *1

.define ESI_LOOPBACK outw(OxCB.O) 1* put the ESI in Loopback *1
.define NO_ESI_LOOPBACK outw(OxCB.8) 1* take the ESI out of Loopback *1
.define EOI_80130
outb(OxEO.Ox63)
1* End Of Interrupt *1
.define TIMERl_EOI_80186 outw(OxFF22.0x04) 1* EOI for Timer 1 on the 186 *1
.define TIMER1_EOI_80130 outb(OxEO.Ox64) I*EOI for 186's Timerl on the 130 *1

4-28

IPCO/USR/CHUCK/CSRC/DLD.C

1********

allocation

memory

1*
1*

int Self_Test;
u_short temp;

****************1

used for diagnostic purposes
temporary storage *1

1*

.define LPBK FRAME SIZE
4
char
lpbk_frametLPBK-FRAME_SIZEl
Ox55. OxAA. Ox55. OxAA})
.define whoami io add
OxOOFO
char
whoamitADD_LENl;

1*

1*

loopback frame storage

addre&s of Host Address Prom *1
array where host .address is stored

*1

good_xmi t_cnt;
underrun_cnti
no_cT"s_cnt;
defer cnt)
s'l.e_e:;:-r _tnt)
max_col_cnt;
recv_frame_cnt)
reset_cnt.;

Allocate storage for structures and buffers

*1

struct FLAGS Hags;

1*

586 structures

1*
1*

System Configuration Pointer: Rom Initialization *1
struct SCP scp = {OxOOOO.OxOOOO.OxOOOO.OxlFF6.0xOOOO};

1*

struct ISCP iscp;

struct SCB scb;

*1
*1

Intermediate System Configuration Pointer

1*

System Control Block

*1

*1

struct CB cb[CB CNTl.
1* Command Blocks *1
*cb_tos. *begin::::cbl. *end_cbl;
1* pointer to the beginning of the free
command block list (cb tos) and the
beginning and end ·of the 82586 cbl *1
struct TBD tbd[TBD_CNTl.
*tbd_tosi

1*

struct FD fd[FD_CNTl.
*begin_fd. *end_fd;
struct RBD rbd[RBD_CNTl.

1* Transmit Buffer Descriptor *1
pointer to. the free Transmit buffer
descriptors *1
1*

struct TB tbuf[TBD_CNTl;

1*

Transmit Buffers

*1

1*

Frame Descriptors *1
pointers to the beginning and end of
the free FD list *1

1*

*1

{

1* lID
1* Ram

transmission statistic variables

unsigned long
u short
u::::short
unsigned long
u_short
u short
unsigned long
u_short

*1

Receive Buffer Descriptors

4-29

*1

*1

IPCO/USR/CHUCK/CSRC/DLD.C
1* pOinters to the beginning and the
end of the rbd list *1

struct RB rbuf[RBD_CNTlJ

1* Receive Buffers *1

struct MAT mat[MULTI ADDR_CNTl)
struct MA_CB ma_cbJ

1* Multicast Address Table *1
1* Multicast Address Command Block *1

1* The following 'structure. are used Onlll in Reset_::l86() function *1
struct
CB
res_cb)
1* Temporarll CB for reinitializing the 586 *1
struct
MA_CB
res_ma_cb)
1* Temporary MA_CB for reloading Multicast *1
1*

Hardware Support Functions *1

Enab I e_586_Int (.)
-(

int

Ci

c = inb(OxE2»)
1* read the 80130 interrupt mask register *1
outb(OxE2. OxOOF7 & C)J 1* write to the 80130 interrupt mask register *1
}

-(

int

CJ

c = inb(OxE2»)
outb(OxE2, Ox0008 I clJ
}

-(

outw(TIMER1_CNT, 0»)
outw(OxFF5E, OxE009»)

1* Write a 0 to Timer1 count register *1
1* Set ENable bit in Timer1 Mode/Control register *1

}

Reset_Timeout()
-(

outw(OxFF5E, Ox6009») 1* Reset ENable bit in Timer1 Mode/Control register *1
Init_Timer() 1* 186'5 Timer 2 is a pres~aler for Timer 1. It clocks Timer 1
everv 32.7 m.ec. The deadman timeout is set for 1.25 sec *1
-(

outw(OxFF38, OxOOOC»)
1* Set Timer1 Interrupt Control register *1
outlll(OxFF62, OxFFFF»)
1* set max count register for timer2 to OFFFFH *1
outlll(OxFF5A,
38»)
1* set max count register A for timer 1 *1
outw(OxFF66, OxCOOl)J
1* Set Timer2 Mode/Cpntrol register *1
outlll(OxFF5E, Ox6009)J
1* Set Timer1 ModelControl register *1
outw(OxFF28, (inw(OxFF28) & OxFFEF»J I~ Enable 186 Timerlinterrupt *1
outb(OxE2, (inb(OxE21 & OxOOEF») 1* enable 80130 interrupt from 80186 *1
1* end hardlilare support functions *1

4-30

inter
IPCO/USR/CHUCK/CSRC/DLD.C

<

ac b. c.,.c_e.,..,.s
scb.aln_e.,..,.s
scb . .,.sc_e.,..,.s
scb.ov.,._e.,..,.s

1* clea.,. 586 e"''''o", statistic counte.,.s *1

01
O.
O.
O.

good_xmit_cnt = 01
unde.,..,.un_cnt = O.
no_c.,.s_cnt = 01
def • .,. _cnt = 01
sqe_e.,..,. _cnt = 01
m.ax_col_cnt = O•
.,.ecv_f.,..ame_cnt = 01
.,.eset_cnt = 01

1* init d.ata link statistics *1

}

st.,.uct ISCP *piscpI
u_sho.,.t il
st.,.uct MAT *pmatl
NO..e;SIJ-OOPBACK.

1* Done fa.,. 82l501.
in loopb.ack *1

Inactiv.ates CRS i f pOllle.,.ed up

ES I J-OOPBACKI
1* Initializ.ation DLDs inte.,..,.upt vecto.,.s *1

flags . .,.eset_sem.a
01
flags . .,.esetJend
O.
flags. stat_on
11

1* Initialize Reset Flags *1

=

piscp = OxOOOOFFFO. 1* Initialize the ISCP pointe.,.*1
pi sc p->busy = 1.
piscp->offset
Offset(&scb).
piscp->basei = SEGMT « 41
piscp->base2 = (SEGMT » 12) & OxOOOF I

=

pNULL = Build_Pt.,.(NULL).
1* build a NULL pointe.,. - 8086 type: 32 bits *1
Build_Rfa()1
1* init Receive F.,.ame A.,.ea *1
Build_Cb(). 1* init Command Block list *1
ma_cb. cmd = 01
1* multicast add~ess semapho.,.e init *1
Clea.,. _Cnt().
scb. stat

= O.

CAl

1* lIIait fa.,. the 586 to complete initialization *1

fa.,. ( i

=

01 i

<=

OxFFOOI i++)

4-31

IPCO/USR/CHUCK/CSRC/DLD.C
(CX I CNA»

if (stb.stat
break,

if (i >OxFFOO)
Fatal("DLD: init - Did not get an interrupt after Reset/CA\n");
1* Ack the r.set Interrupt *1
scb. cmd
(CX I CNA);
CA,
Wai t_Scb (),
Enable_586_Int()'

=

scb. cbl_offset
scb.rfa_offset

Offs.t(&cbtOl);

= Offset(&fdtOl);

1* link scb to cb and fd lists *1

1* move the prom bytes into whoami array *1

for (i = 0, i < ADD~ENI i++)
whDamit(ADD_LEN - 1) - il

=

+ i*2)1

inb(whoami~io_add

1* Initialization the Multicast Address Table *1

for (pmat = &mattOll pmat
pmat->stat = FREEl

<=

&mattMULTI_ADDR_CNT

Configure(INTERNAL_LOOPBACK);
SetAddress () I

~

1* Put· 586 in internal loopbac k *1

1* Set up the station .address *1

1* run diagnostics *1

if (Self_Test != PASSED)
return(Self_Test),
Conf'igure(NO_LOOPBACK)I 1* Conf'igur,e the 82586 *1
return(Self_Test),

struct
struct
struct
unsigned

FD
RBD
RB
long

*pfdl
*prbdl
*pbufl
badd,

1* Build a linear linked frame descriptor list *1

for (pfd

&fdtOll pfd

<=

111 pmat++)

&fdtFD_CNT - 111 pfd++) {

=

pfd->stat = pfd->el_s
0;
pfd->link = Offset(pfd+1),
pfd->rbd_offset = NULL,

4-32

IPCO/USR/CHUCK/CSRC/DLD.C

end_fd = --pfd;
1* point to &fdtFD_CNT - 1l *1
pfd->link = NULL;
1* last fd link is NULL *1
pfd->el_s = ELBITI
1* last fd has EL bit set *1
begin_fd = pfd = &fdtOll
1* point to first fd *1
pfd->rbd_oHset = Offset(&rbdtOJ); 1* link first fd to first rbd *1
1* Build a linear linked receive buffer descriptor list *1
for

(prbd

= &rbdtOJ. pbuf
= SEQMT « 41

= &rbuftOJ; prbd <= &rbdtRBD_CNT - 1l;
prbd++. pbuf++) {

badd
badd += Offset(pbuf);
prbd->buff_l = badd;
prbd->buff_h = badd » 16;
prbd->buff-ptr - pbufl
prbd->act_cnt = 0;
prbd->link = Offset(prbd + 1);
prbd->size = RBUF_SIZE;
)

end_rbd = --prbd;
prbd->link a NULLl
prbd->size 1= ELBIT;
begin_rbd

1* last rbd points to NULL *1
1* last rbd has el bit s'et *1

= &rbdtOJI

}

Build _Cb( )

1* Build a stack of free command blocks *1

{

struct CB
struct TBD
struct TB
unsigned

*PCbl
*ptbdl
*pbuf;
long

badd;

for (pcb
&cbtOJ; pcb <= &cbtCB_CNT - 111 pcb++) {
pcb->stat = 01
pcb->cmd = ELBIT;
pcb->link = Offset(pcb + 1);
}

--pcb;
begin_cbl = end_cbl = pNULL;
pcb->link = NULL;
cb_tos = S.cbtOJI
1* Build a stack of transmit buffer descriptors *1

for (ptbd

= &tbdtOJ.

pbuf

= &tbuftOl;

ptbd <= &tbdtTBD_CNT - 1JI
ptbd++. pbuf++) {

ptbd->act_cnt
TBUF _SIZE;
ptbd->link = Offset(ptbd + 1);
badd

= SEQMT «

4;

4-33

inter
IPCO/USR/CHUCK/CSRC/DLD.C
bedd +- Off.et(pbuf)1
ptbd->buff_1 - baddl
ptbd->buff_h • badd » 161
ptbd->buff-ptr - pbufl
--ptbdl
ptbd->Iink - NULL I
tbd_tos ~ .tbdCOll

.truct

<

1* la.t tbd link i. NULL *1
1* Set the Top Of the Stack *1

CB

.truct

CB *PCbl

-=

if (Off.et(pcb .. cb_tos)
NULL)
return(pNULLlI
cb_tos .. (struct CB *) BuildJPtr(pcb->link);
pcb->link .. NULL 1
retu1'n(pcb)1

1* Put a Command Block back onto the '1'eelist *1

st1'uct

<

CB *pcbl

pcb->stat - 01
pcb->link
Off.et(cb_tos);
cb_tos .. pcbl

=

struct TBD

*Get_Tbd()

<

TBD

1* return a pointer to a '1'ee transmit bu"er
descr.iptor *1

*ptbdl

'lags.reset_se.e" 1;
Di.able_586_Int()1
i' «ptbd .. tbd_tos) !- pNULL) <
tbd_tos .. (struct TBD *) BuildJPt1'(ptbd->link);
ptbd->link = NULLI
}

Enable_586_Int();
'lags.1'eset_seme - 01
i' ('lags.reset-pend ... 1)
Rese.t;..586( ),
1'eturn(ptbd)1

Put_Tbd(ptbd)

4-34

inter
IPCO/USR/CHUCK/CSRC/DLD.C

stTUCt

TBP

*ptbdl

{

StTUCt

TBD

*p

I

1* find the end of the tbd list TetuTned. ptbd is the beginning *1
fOT (p = ptbd.

p->link !a NULL.

p->act_cnt = TBUF_SIZE.
p->link
Offset(tbd_tos).
tbd_tos = ptbdl

p = (stTUCt TBD *) Build_PtT(p->link»

1* cleaT EOFBIT and update size on last tbd *1

}

SetAddTess()
{

stTUCt

CB

*pcb.

IIUdef DEBUG

-=

If «pcb = Get_Cb(»
pNULL)
Fatal("dld .. c - SetAddTess - couldn't get a CB\n")1

.else
pcb
.endif

= Get_Cb()1
1* DEBUG *1

bcopy«chaT *)&pcb->paTml. &whoami[OJ. ADD_LEN) I

I*-move the pTom
addTess to IA cmd *1

pcb->cmd = IA I ELBIT,
}

W~it_Scb()

1* wait fOT the scb command wOTd to be cleaT *1·
i.

fOT (stat

stat.

FALSE·,

stat

==

FALSE,

) {

fOT (i=O. i<=OxFFOO. i++)
if (scb. cmd == 0)
bTeak.
if (i > OxFFOO) {
Bug("DLD: Scb command not cleaT\n").
CAl
}

else
stat

TRUEI

}

4-35

IPCO/USR/CHUCK/CSRC/DLD.C

Issue_CU_Cmd(pcbJ 1* Gueue up a command and issue a
othe~ commands .~e queued *1
st~uct
CB *pcb.

st.~t

CU command if no

Disable' 5B6 Int( JI
if Cbegin_cbl
pNULLJ <
1* if the list is inactive sta~t CU *1
begin_cbl = end_cbl
pcb.
scb. cbl_offset ... Offset(pcbJI
Wait_ScbC JI
scb. cmd = CU_STARTI
Set_TimeoutCJI
1* set deadman time~ 'o~ CU *1
CAl

-=

}

else

<
end_cbl->link - OffsetCpcbJI
end_cb 1 ... pcbl

}

Enable_5B6_IntC'1
}
ls~7(

)

(

outb(OxEO. Ox67'1

1* EOI B0130 *1

}
ls~6(

<

)

W~iteC"\nlnte~~upt

outb(OxEO. 0166),

6\n")I'
1* EOI B0130*1

}
Is~5C

)

0(
W~iteC"\nlnte~~upt

outbCOIEO.016S)1

5\n".)1
1* EOI B0130 *1

}

1* Deadman

Time~

Is~_TimeoutC)

1*

Inte~~upt

Int.~~~pt,4

Se~vice

Routine *1

*1

0(

Reset_TimeoutC ),
if C'lags.~eset_sema
else

'lags.~eset-pend

'
Reset_SB6C ),

-=

IJ
... 11

TIMER1_EOI_BOIB6t
TIMER1_EOI_BOI301
}

1*
1*

Inte~~upt
Inte~~upt

0 is
2 is

Ua~t in UAP Module *1
Time~ in UAP Module *1

4-36

IPCO/USR/CHUCK/CSRC/DLD.C
!sri ()
-(

WriteC"\nInterrupt l\n"»)
outb COxEO, Ox611 I
1* EOI 80130 *1
}

1* 586 Interrupt service routine:

Interrupt 3 *1

Isr _586 ( )
-(

u_short
struct CB

stat_scbl

enable C) I

1* nesting

*p~bl

Wait_Scb( »)
scb.cmd = (stat_scb
CAl

onl~

the uart interrupt *1

= scb. stat)

& CCX

I CNA I FR I RNR)1

if (stat_scb & (FR I RNR»
Recv_Int_ProcessingC)1
if Cstat_scb & CNA) -(

1* end of cb processing *1

Reset_TimeoutC) I
1* c lear deadman timer
pcb = Build_Ptr(scb. cbl_offset»)

*1

#Udef DEBUG
if Cbegin_cbl == pNULL)-(
BugC"DLD: begin_cbl == NULL in interrupt routine\n"»)
return;
}

if CCpcb->stat & OxCOOO) != 0.8000)
Fatal< "DLD: C bit not set or B bit set in interrupt routine\n")l
#endif 1* DEBUG *1
switch Cpcb->cmd & CMD_MASK) -(
case TRANSMIT:
if (flags. stat_on

==

1) -(/* if Transmit Statistics are collected do *1

1* if' Sill! bit = 0 and there we.re no collisions -> silO! O!rror
this condition will ocCUr on the first transmission if
there were no collisions, or if the previous transmit
command reached the max collision count, and the current
transmission had no collisions *1

if (Cpcb->stat & (SGEMASK I MAXCOLMASK I COLLMASK»
++5Ile_e1"1" _cnti

if (pcb->stat & DEFERMASK)
++defer _cntl

4-37

== 0)

IPCO/USR/CHUCK/CSRC/DLD.C

if (pcb->stat & NOERRBIT)
++good_xmi t_cntJ
else <
if (pcb->stat & NOCRSMASK)
++no_crs_cntl
if (pcb->stat & UNDERRUNMASK)
++underrun_cntl
if (pcb->stat & MAXCOLMASK)
++milx_col_cntl
)
)

if (pcb->parml !- NULL)
Put_Tbd(Build-Ptr(pcb->parm1»I.
breakl
case DIAGNOSE:
flags. diilg_done - 1J
if «pcb->stat & NOERRBIT)
0)
Self_Test
FAILED-PIAQNOSEJ
·breakl

==

defaul t:
)

1* check to see if ilnother command is /lueued. *1

=-

if (pcb->link
NULL)
begin_cbl - pNULLI
else

< 1* restart the CU and execute the next command on the cbl *1
begin_cbl = Build-Ptr(pcb->link)J
scb. cbl_o"set - pcb->link,
Wait_ScbOJ
scb.cmd = CU_STARTI
CAJ
Wait_ScbOJ
Set_Timeout( ),
, 1* START deadmiln timer *1

)

iF «pcb->cmd & CMD_MASK) -- MC_SETUPl
pcb->cmd = OJ 1* clear MC~SETUP cmd word. this will implement a
lock semephor. so that it won't be reused until
it is completed *1
else
Put_Cb(pcbl, 1* Don't return MC_SETUP cmd block. It's not a
general purpose command block 'rom free CD list *1
)

disable()J
EOI_80130,

1* disable cpu into so that the 586 isr 'will not nest *1

)

4-38

IPCO/USR/CHUCK/CSRC/DLD.C

Recv_Int_Processing()
{

FD
RBD

struct
struct

*pfd;
*q.
*prbd;

1* points to the Frame Descriptor *1
1* points to the last rbd for the frame *1
1* points to the first rbd for the frame *1

for (pfd = begin_fd; pfd != pNULL; pfd = begin_fd)
if (pfd->stat & CBIT) {
begio_fd = (struct FD *) Build_Ptr(pfd->link);
prbd = (struct RBD *) Build_Ptr(pfd->rbd_o.fset);
if (prbd != pNULL) { 1* check to see if a buffer is attached *1
lIifdef DEBUG
if (prbd != begin_rbd)
Fatal("DLD: prbd != begin_rbd in Recv_Int_Processing\n");
lIendif 1* DEBUG *1
for (q = prbd; (q->act_cnt & EOFBITl != EOFBIT;
q = (struct RBD *) Build_Ptr(q-)link»;
begin_rbd = (struct RBD *) Build_Ptr(q->link);
q->link = NULL;
}

if (pfd->stat & OUT_OF RESOURCES)
Put_Free_RFA(pfd);
else {
1* i. the DLD is in a loopback test.
i f (flags. lpbk_mode == 1>
Loopback_Check(pfd);
else

check the 'rame recv *1

1* if it's a multicast address check to see if it's
in the multicast address table, if not discard the frame *1
if ( «pfd->dest_addrrOJ & 01) == 01) && (!Check_Multicast(pfd»)
Put_Free_RFA( p fd);
else
{
Recv_Frame (pfd);
++recv_frame_cnti
}
}

}

else {
Ru_Start();
break;

1* If RU has gone into no resources, restart it *1

}
}

1* Called by Racv_Int_Processing; checks address
and data of potential loop back 'rame *1
struct

FD

'*pfd;

{

struct RBD
struct 'RB

4-39

IPCO/USR/CHUCK/CSRC/DLD.C
if (

bcmp«char *) &pfd->src_addr[Ol. &tllhoamHOJ. ADD_LEN) !'" 0 ) {
Put_Free_RFA( pfd);
return;

)-

prbd = (struct RBD *) Build_Ptr(pfd->rbd_offset); 1* point to receive
buffer descriptor *1
pbuf
(struct RB *) prbd->buff'-ptr; 1* point to receive buffer *1
if

bcmp«char *) pbuf. &lpbk_frame[Ol. LPBKJFRAME_SIZE) != 0) {
Put_Free_RFA(pfd);
return;

)-

flags. Ipbk_test = 11. 1* passed loopback test *1
Put_Free_RFA(pfd)1
)-

Check_Multicast(pfd)
1* returns true if multicast address is in MAT *1
struct
FD *pfdl
{

struct

MAT *pmatl

for (pmat
&mat[OJI pmat <= &mat[MULTI ADDR CNT - ll1 pmat++)
if ( pmat-:>stat "'''' INUSE &&
(bcmp«char *) &pfd->dest_addr[OJ. &pmat-:>addr[Ol. ADD_LEN) == 0»
brea k;
if (pmat :> &mat[MULTI_ADDR_CNT - ll)
return (FALSE) I
returnact_cnt = EOFBIT : LPBK_FRAME_SIZE'
bcopy«char *) ptbd->buff_ptr, &lpbk_frame(OJ, LPBK_FRAME_SIZE),
wh i 1 e ( ! Send_Frame (ptbd, i!cwhoamHO]»,
}

}

Diagnose()
{

struct

CB

lIifdef DEBUG
if «pcb
Get_Cb(» == pNULL)
Fatal("dld - Diagnose - couldn't get a CB\n"),
lIelse
lIendif 1* DEBUG *1
flags. diag_done = 0,
Self_Test = FALSE,
pcb->cmd = DIAGNOSE

while (flags. diag_done

ELBIT,

0)

1* wait for Diag cmd to finish *1

4-41

IPCO/USR/CHUCK/CSRC/DLD.C

Configure(loopflag)
-(

struct

CB

tHf'def' DEBUG
if' «pcb" Qet_Cb(» .... pNULL)
F.tal( "d Id - Configure ~ couldn't get a CB\n") I

*endif' 1* DEBUG *1

1* Ethernet default parameters *1
pcb->parml
0.080CI
pcb->p.rm2
0.2600 I loopflagl
pcb->parm3
0.60001
pcb->parm4
0.F2001
pcb->parm5 .. OXOOOOI
if (loopflag
NO_LOOPBACK)
pcb->parm6 .. 0.00401
else
pcb->parmo .. 0.0006.
1* loopback frame i. less butes than
the minimum fr •• e length *1
pcb->cmd
CONFIGURE
ELBITI

==

=

1* Send a frame to the cable,· pass a pointer to the destination address
and a pointer to the first tr.nsmit buffer descriptor. *1
Send_Frame (ptbd,
struct
TBD
char

padd) 1* returns fal.e if it can't get a Command block *1
*ptbdl
*p.dd.

-(

struct

CB

*pcb.
lengthl

=

-=

if «pcb
Get_Cb(»
pNULL) -(
fl.gs.reset_sema .. 01
if (flags.reset-pend
1)
Reset_S8o() I
return(FALSE)1

-=

pcb->parml .. Off'set(ptbd).

4-42

inter
IPCO/USR/CHUCK/CSRC/DLD.C
1* move destination add~ess to command block *1
bcopl,l CCcha~ *)"pcb->p.~m2. Cch.~ *) p.dd. ADD_LEN).
1* calculate the length field bl,l summing up all the

buffe~s

*1

for Clength = 01 ptbd->link != NULL. ptbd = Build_PtrCptbd->link»
length +- ptbd->act_cntl
length += Cptbd->act_cnt .. Ox3FFF)1
1* check to see if padding is

1* add the last buffer *1

re~uired.

do not do padding on loopback *1

if CClength < MIN_DATA_LEN) .... 1* assumes a 4 bl,lte CRC *1
CbcmpC"lIIhoamHOl. (ch.~ *)padd. ADD_LEN) != 0»
ptbd->act_cnt

MIN-PATA~EN

EOFBITI

1* length field *1

p.cb->parm5 = lengthl
pcb->cmd

I

ELBITI

TRANSMIT

Issue_CU_CmdCpcb)1

=

fl.gs.~eset_sema
01
if Cflags.~eset-pend

1)

Reset_5B6C ) I
retu~nstat == INUSE ....
(bcmp ( "pmat->add~COl. (cha~ *) pma. ADD_LEN) == 0»
retu~n stat
FREE) {
pmat->stat = INUSEI
bcop..,( "pm.t->.dd~[Ol. (char *) pma. ADD_LEN) I

=-

b~eakl

4-43

{

·infef
IPCO/USR/CHUCK/CSRC/DLD.C
}

if (pmat ) &mat[MULTI_ADDR_CNT - 1]) {
flags.reset_s.ma = 01
if (flags.reset-pend -=.1)
Reset_586 ( ) 1
return (FALSE) 1
}

Set_Multicast_Address();
flags.reset_sema = 01
if (flags.reset-pend == 1)
Reset_586( ) I
return(TRUE)1
}

Delete_Multicast_Address(pma)

struct

1* returning false means the multicast address
was not found *1

MAT

for (pmat .. matI pmat <- &mat[MULTI ADDR CNT - 1]1 pmat++)
if ( pmat-)stat == INUSE &&
(bcmp( &pmat->addr[O], (char *) pma, ADD_LEN) == 0»
pmat->stat .. FREEl
break;

{

}

if (pmat > &mat[MULTI_ADDR_CNT - 1]) {
flags.reset_sema" 01
if (flags.reset-pend == 1)
Rese1;_586( )1
return(FALSE)1
}

Set_Multicast_Address();
flags.reset_sema .. 01
if (flags.reset-pend == 1)
Reset_586( );
return(TRUE)1
}

Set_Multicast_Address()
{

struct
struct
u_short
i == 0;

pma_cb = &ma_cb;
while (pma_cb.->cmd != 0) I 1* if the MA_CB is inuse, wait until it's free *1
pma_cb-)link = NULLI

4-44

IPCO/USR/CHUCK/CSRC/DLD.C
for (pmat = mat. pmat <- &mat[MULTI_ADDR_CNT - IJ. pmat++)
if ( pmat->stat -~ INUSE) {
bcopy( &pma_cb->mc_addr[iJ. &pmat->addr[OJ. ADD_LEN).
i += ADD_LEN.
pma_cb->mc_cnt ~ i.
pma_cb->cmd = MC_SETUP I ELBIT.

PutjFree_RFA(pfd)
struct

FD

struct

RBD

1* Return Frame Descriptor and Receive Buffer
Descriptors to the Free Receive Frame Area *1

{

char

*prbd. 1* points to beginning of returned RBD list *1
*Ill
1* points to end of returned RBD list *1
ru_start_flag_fd. 1* indicates whether to restart RU *1
ru_start_flas_rbdl

=

flags.reset_sema
11
ru_start_flag_fd - ru_start_flag_rbd = FALSE.
pfd->el_s = ELBIT.
pfd->stat = O.
prbd = (struct RBD *) BuildJ'tr(pfd->rbd_offset)./* pick up the link to the rbd *1
pfd->link = pfd->rbd_offset = NULLI
1* Disable_586_Int(). this command is only necessary in a multitasking
program. However in this single task environment this routine is originally
called from isr_586(). therefore interrupts are already disabled *1

if (begin_fd -- pNULL)
begin_fd - end_fd = pfd.
else {
end_fd->link - Offset(pfd).
end_fd->el_s - 01
end_fd = pfd,
ru_start_flag_fd = TRUE,
if (prbd !- pNULL) {

1* if there is a rbd attached to the fd then
find the beginning and end of the rbd list *1

for (Il = prbd. Il->link != NULL. Il
Il->act_cnt - 0,

= BUildJ'tr(Il->link»

1* now prbd points to the beginning of the rbd list and
Il points to the end of the list *1

Il->size = RBUF_SIZE I ELBIT,
Il->act_cnt = 0,

4-45

IPCO/USR/CHUCK/CSRC/DLD.C
if'

(begin_l'bd == pNULL) { 1* if--there is nothing on the 'list
create a new list *1
begin_rbd = prbd.
end_rbd = Il'
if' (prbd != III
ru_start~flag_rbd

TRUE. 1* if there is more than one rbd
returned start the RU*I

}

else {
1* if the rbd list alread~ exists add on
the new returned rbds *1
OffsetCprbd).
RBUF_SIZE.

end_rbd->link
end_rbd->size =
end_rbd = III
ru_start_flag_rbd =-TRUE.
}

}

if Cru_start_flag_fd &&
Ru_Start C) I

flags.reset_sema = O.
if Cflags.reset-pend
Reset_586() I

ru_start~flag_rbd)-

'

1)

}

{

if CCscb. stat & RU_MASK)

RU_READY) 1* if the RU is alread~ 'ready'
then return *1

return;

if «begin_fd->stat & CBIT)
return.

==

CBIT)

begin_fd->rbd_off'set = Off'setCbegin_rbd). 1* link the beginning of the rbd
list to the first fd *1
scb. rfa_offset= Offset Cbeg in_fd).
Wai t_Scb C).
scb. cmd
RU_START.
CA.
}

Software_Reset()
{

scb. cmd = RESET.
CA.
Wait_ScbC);
}

IssuejReset_Cmds()
{

Wait_Scb().
scb. cmd
CU_STARTI
CA.

4-46

IPCO/USR/CHUCK/CSRC/DLD.C

outw(OxFF5E. 0) ;
outw(TIMER1_CNT. 0);
outw(OxFF5E. OxC009);

1* shut off timer 1 interrupt *1
1* use timer 1 without interrupt as a deadman *1

while «inw(OxFF5E) & Ox0020)
if «scb. stat & CNA)
break;

==

==

0)

1* if Max Cnt bit is set ~efore CNA
is set. 586 Cmd deadlocked *1

CNA)

if (scb. stat & CNA != CNA)
FataU"DLD: Issue_Reset_Cmds - Command deadlock during reset procedure\n");
Reset_Timeout ();
scb. cmd = CNA;
CAl
Wait_Scb( );

1* Acknowledge CNA interrupt *1

}

1* Execute a reset •. Configure. SetAddress. and MC_Setup. then restart the
Receive Unit and the Command Unit *1
Reset_586( )
{

MAT
ii

++reset_cnti

Disable_586_Int();
ESI_LOOPBACK;
Software_Reset();
scb. stat
CAl

= 0;
1* wait for the 586 to complete initialization *1

for ( i = 0) i <= OxFFOO; i++)
if (scb. stat == (CX l CNA»
break;
if (i )OxFFOO)
Fatal("DLD: init - Did not get an interrupt after Software Reset\n");
1* Ack the reset Interrupt *1
Wait_Scb();
scb. cmd = (CX : CNA.);
CAl
Wait_Scb(»)

!lifdef DEBUG
if ( begin_cbl == pNULL)
Fatal ("DLD: bey in_cb 1
#endif 1* DEBUG *1

NULL in Reset_586")J

4-47

IPCO/USR/CHUCK/CSRC/DLD.C

1*
1*

the 586 *1
default pa~amete~sl

Configu~e

Ethe~net

default
~es_cb.

pa~amete~s

is not

necessa~v ~hen

using

link = NULLI

~es_cb. pa~m1
~.s_cb. pa~m2

~I!s_cb. pa~m3
~es_cb.·pa~m4

~es_cb. pa~m5
~es_cb. pa~m6
~es_cb.

Configu~e

*1

cmd

Ox080C.
Ox2600i
Ox6000.
OxF2001
o X00001
OX00401
CONFIGURE I ELBIT.

Issue_Reset_Cmds()1

1* Set the Individual Add~ess *1
bcopy«cha~

~es_cb

.. cmd

*)

&~es_cb.pa~m1.

&~hoamiCOl.

ADD_LEN) I 1*

~ove

add~ess

= IA

the p~om
to IA cmd *1

I ELBIT.

Issue_Reset_Cmds()1

1* .eload the multicast
i

add~esses

*1

= ~es_ma_cb. stat

~es_ma_cb.

fo~

- 01
link = NULL.

=

(pmat
&matCOll pmat <= &matCMULTI_ADDR_CNT - 111 pmat++)
if ( pmat->stat == INUSE ) {
bcop~( &~es~a_cb.mc_add~Ci]. &pmat->add~COl. ADD_LEN) I
i += ADD_LENI
}

cb.mc_cnt = 11
cmd - MC~SETUP I EL8zT.
scb. cbl_offset
Of'set(&~es_ma_cb. stat).

~es_ma

~es_ma_cb.

1*

Resta~t

the Command Unit and the Receive Unit *1

flags.~eset_sema
flags.~eset-pend

O.
O.

'Recv_IntJP~ocessing()1

scb. cbl_o'fset
Wai t_Scb ().

= begin_cbl.

4-48

IPCO/USR/CHUCK/CSRC/DLD.C
scb. cmd = CU START.
Set_Timeout C).
CA.
Enable_586_IntC).

1* Set Deadman Timer *1

}

1* bcopy -- byte copy routine *1
bcopyCdst, src, nbytes)
char
*dst, *srCi
int
nbytes.
{

while Cnbytes--) *dst++ = *src++.
}

1* bcmp -- byte compare *1
bcmpCs1, s2, nbytes)
char
*sl, *52.
int
nbytes.
{

while Cnbyte5-- && *51++
returnC*--sl - *--s2).

*s2++).

}

4-49

IPCO/USR/CHUCK/CSRC/LLC.C

1*****************************************************************************
**

**

IEEE 802.2 Logical Link Control Layer
(Station Component)

*

*

******************************************************************************1
#include "dId. h"
extern

char

*pNULL,

extern
extern

struct
char

TBD *Get_Tbd(),
*Build_Ptr(),

readonly char
1* DSAP. SSAP.

xid_frameCXID_LENGTHl = { O. O.
XID. xid class 1 response *1

XID.

Ox81. OxOl. O},

struct LAT' latCDSAP _CNTJ,

struct

LAT

*p lat,

for (p lat = &latCOl; plat
plat->stat = FREE,
return(Init_586(»;

<=

&latCDSAP _CNT -

1],

P lat++)

}

1* Function for adding a new DSAP *1
Add_Dsap~Address(dsap.

int dsap.

pfunc) 1* DSAP must be divisible by 2**(8-N). where
2**N
DSAP_CNT. (i. e. N LSBs must be 0).
The function will return FALSE if does not
meet the above requirements. or the Lsap
Address Table is full. or the address .has
already been used. NULL DSAP address i~
reserved for the Station Component *1

=

(*pfunc) (),

{

struct

LAT

*p Iat;

if «dsap « (8-DSAP_SHIFT) & OxOOFF) != 0 :: dsap
return (FALSE),

1* Check for duplicate dsaps. *1
if ( (plat = &latCdsap » DSAP SHIFTl)->.tat
plat->stat = INUSE,
plat->p_sap_func = pfunc,
return (TRUE),

0)

FREE) {

}

else
return(FALSE),
}

1* Function for deleting DSAPs *1
Delete_Dsap_Address(dsap) 1* If the specified connection exists. it is severed.
If the connection does not exist. the command is ignored. *1

4-50

IPCO/USR/CHUCK/CSRC/LLC.C
int dsapl
{

»

latCdsap

DSAP_SHIFTl. stat

FREEl

}

Recv_Frame(pfd)
struct FD
{

struct
struct
struct

= (struct

prbd
pfs

*prbd,
*pfSi
*plati

RBD
FRAME STRUCT
LAT -

= (struct

RBD *) Build_Ptr(pfd->rbd_offset)i
FRAME_STRUCT *) prbd->buff_ptri

if (pfd->rbd_offset != NULL) { 1* There has to be a rbd attached
to the fd. Dr else the frame is
too short. *1
if (pfs->dsap
0) {
1* if the frame is addressed to the Station
Component. then a response may be required *1

==

if ( !(pfs->ssap & C_R_BIT) ) {/* if the frame received
instead of a command. then
Because this software does
DUPLICATE_ADORESS_CHECK.->
frames should' be recv'd *1
Station_Component_Response(pfd);

is a response.
reJect it.
not implement
no response

}
}

1* not addressed to Station Component. *1
1* check to see if the dsap addressed is active *1

else if «pfs->dsap « (B-DSAP_SHIFTl & OxOOFFl
0 &&
(plat
&latt(pfs->dsap) » DSAP_SHIFTl)->stat
INUSE ) {
(*p lat->p_sap_func) (pfd) I
1* call the function assoc iated
with the dsap received *1
return;

=

==

}
}

,Put_Free_RFA(pfdll

1* return the pfd if not given to the user saps *1

}

Station_Component_Response(pfd)
struct

FD

*pfd;

{

struct FRAME STRUCT
struct TBD struct RBD

= (struct

prbd
prfs

= (struct

*prfs. *ptfs;
*ptbd. *begin-ptbd. *ql
*prbdi

RBO *) Build_Ptr(pfd->rbd_offset),
FRAME_STRUCT *) prbd->buff-ptri

switch (prfs->cmd &

~P_F_BIT)

{

case

XIO:

4-51

IPCO/USR/CHUCK/CSRC/LLC.C

while «p~bd = Ge~_Tbd(» == pNULL),
ptbd-:>act_cnt = EOFBIT I XID_LENGTH,
bcopy «char *> ptbd-:>bu~f-ptr, &xid_frame[OJ, XID_LENGTHl,
p~fs = (struct FRAME_STRUCT *l ptbd-:>buH-ptr,
ptfs->cmd = prfs-:>cmd,
ptfs->dsap = prfs-:>ssap

C_R_BIT' 1* return the frame
to the sender *1
ptfs->ssap = 0,
while( !Send_Frame(ptbd, Buildytr(pfd->src __addr»),
break,
TEST:

case

for (prbd

(struct RBD *) Build_Ptr(pfd-:>rbd_offset),
q
begin_ptbd ~ pNULL, prbd != pNULL,
prbd = Build_Ptr(prbd-:>link» {

pNULL> ,
while «ptbd = Get_Tbd(»
i f (q ! = PNULL>
q->link = Offset(ptbd),
else
begin_ptbd = ptbd,
ptbd->act_cnt = prbd-:>act_cnt,
bcopy«char *) ptbd->buff_ptr. (char

.*)

prbd-:>buff _ptr,
ptbd-:>act_cnt & Ox3FFF),

q = ptbd,
}

pHs = (struct FRAME_STRUCT *) begin-ptbd-:>buH._ptr,
ptfs->cmd = prfs->cmd,
ptfs->dsap = prfs->ssap

1* return the frame to
the sender
ptfs->ssap = 0,
while( !Send_Frame(begin-ptbd. Buildytr(pfd-:>src_addr»),
break.

*1

}
}

4-52

IPCO/USR/CHUCK/CSRC/UAP.C

1***************************************************** ***********************

*
*
*

•*

User Application Program
Asvnc to IEEE 802.2/802.3 Protocol Converter

*

•

*

****.*****.***************************.*.************• • **.********.**********1
*include "dld.h"

1* ASCII Characters *1
*define ESC
OxlB
*define LF
OxOA
*define CR
OxOD
*define BS
Ox08
*define BEL
Ox07
*define SP
Ox20
*define DEL
Ox7F
*define CTL_C
Ox03
1* Hardware *1
*define CH B CTL
OxOODE
*define CH-A-CTL
OxOODC
*define CH:B:DAT
OxOODA
*define CH A DAT
OxOOD8
*define UART:STAT_MSK
Ox70
1* Interrupt cases for 8274 *1
*define UART_TX_B
o
*define UART_RECV_B
Ox08
*define UART_RECV_ERR_B OxOC
*define EXT_STAT_INT_B Ox04
*define EXT_STAT_INT_A Ox 14
char
fifo t[25bJ;
char
fifo-r[25bJ;
char
wra[;J. wrb[5J;
uns i gned
char
i n_f i fo_t. out_f i fo_t.
u_short
t_buf_stat. r_buf_stat;
char
char

cbuH80J;
line[81 J;

1*
1*

i n.:..f i fo_r.

Command line buffer *1
Monitor Mode displav line

unsigned
char
dsap. ssap. send_flag.
char
Dest_AddrrADD_LENJ;
char
Multi_Addr[ADD_LENJ;
int tmstat; 1* terminal mode status:
int dhex. monitor_flag. hs_stat;
extern
extern

struct TBD
char

*Get_Tbd (); .
*Build_Ptr( );

extern

struct FLAGS

flags;

extern
extern

char
char

out_f i fo_r.

*1

local_echo;

for leaving terminal mode
1* flags *1

,

xid _frame[J;
whoamitJ;

4-53

*1

ac tua 1;

IPCO/USR/CHUCK/CSRC/UAP,C
extern
extern
extern

struc·t
struct
char

extern
extern
extern
extern
extern
extern
eitern
extern

unsigned long
u_short
u_short
unsigned long
u_short
u_short
unsigned long
u_short

extern

struct

MAT
matrJ.
LAT
latrJ.
*pNULL.

SCB

good_xmi t_cnt.
underrun_cnt.
no_crs_cnti

dei'er_cnt.
sqe_err _cnti
Ina x_c 0 l_cnt.
recv _i'rame_cnt'
reset_cnt,
5cb,

1* Macro 'type' 01' dei'initions

#dei'ine
#deHne
#dei'ine
#dei'ine
#dei'ine
#de/,ine
#de/,ine
#de/,ine
#de/,ine
#deHne
#de/,ine
#de/,ine

~I

RTS_ONB outb(CH_B_CTL.Ox05),outb(CH_B_CTL.wrbr5J=wrbr5JIOx02)
RTS_OFFB outb (CH_B_CTL. Ox05). outb·(CH_B_CTL. wrbr5J=wrb[5J8

0)

--

{

(c

!= LF)

&&

{

--i;

Co(BS),

Co(SP),

Co(8S),

}
}

else

if

>= SP) {
Co (c),
buf[i++]
c,

(c

}

else
if

,,

== CR) , , (c
bufti++]
CR,
b uf [i++] = LF,

« c

LF»

{

}

else CoWELl,
}

Co(CR), Co(LF);
if (i > cnt)
*pact
cnt;
else
*pact
i;
for (i = 0, i -:. *pact
*pmsg++ = bufti],

i++)

4-55

(i

<

198) ,

)

{

IPCO/USR/CHUCK/CSRC/UAP.C
}

unsigned char

i,

Read(&cbufCO], 80, &actual),
i = Skip(&cbufCO]),
return(cbufCi]),
}

Write(pmsg)
char
*pmsg,
{

while (*pmsg != '\0') {
if (*pmsg == '\n')
Co(CR),
Co(*pmsg++),
}
}

Fatal(pmsg) 1* write a message to the screen then stop *1
char
*pmsg'
{

Write(nFatal:
Write(pmsg),
for (; ; )i

n),

}

Bug(pmsg)
char

1* write a message to the screen then continue *1
*pmsg,

{

Write(UBug:

")i

Write(pmsg),
}

Ascii_To_Char(c) 1* convert ASCII-Hex to Char *1
char
C.i
{

if

« '0' <= c) && (c <= '9') )

if

«

return(c 'A' <= c)
return(c
i f « 'a' <= c)
return(c
return (OxFF),

'0');

&& (c
Ox37),
&& (c
Ox57),

<=

'F') )

<=

'f') )

if «'a I <= c) && (c
return(c),
if «'A' <= c) && (c
return(c + Ox20),
return(O),

<=

I

<=

'Z'»

-

}

Lower _Case(c)
c;
char
{
Z ') )

}

4-56

IPCO/USR/CHUCK/CSRC/UAP,C

Char To Ascli(c, ch) 1* convert char to ASCII-Hex *1
unsigned char
c, ch[J,
{

unsigned char

ii

i = (c & OxFO) » 4,
if(i(10)
ch[O]
+ 0.30;
else
ch[OJ
i + 0.37,
i = (c & OxOF) ,
if(i(10)
ch[lJ
+ 0.30,
else
ch[lJ
i + 0.37,
ch[2J = '\0',
}

Skip(pmsg)
char

1* skip blanks *1
*pmsg'

{

int

ii

for (i = 0,
return (il,

*pmsg

';

i++,

pmsg++),i

}

Read Int ( )
{

-

1* Read a 16 bit Integer *1

",d, "'h, ",d 1, ",hL J ,
i, done, hex, dover,

u_shoT't
char

for (done
FALSE, done == FALSE,
Read(&cbuf[OJ, 80, &actual),
i = Skip(&cbuf[OJ),
for

(hex = dover
if

(J

>

hover;

) {

hovel' = FALSE, ",d = "'h = ",d1 = "'hl = 0;
(J = Ascii_To_Char(cbuf[i]» (= 15,
i++)

9)

he. = TRUE,
",d = ",d*10 + J;
"'h = ",h*16 + J'
if (",d ( ",d1)
dover = TRUE,
if (",h ( wh 1)
hovel' = TRUE;
wd1 = ",d, ",h1 = wh;
}

iT (cbuf[iJ

==

'H'

: I cbu-f(iJ

==

'h

I

::

cbuf[iJ

==

CR

cbuf[iJ == LF :: cbuf[iJ
if (cbuf[iJ -- 'H' ,, ,, cbuf[iJ -- 'h ')
hex = TRUE,
if (he. == TRUE && hovel' == FALSE)
done = TRUE,
'if (hex
FALSE && dover -- FALSE)
done = TRUE,

--

4-57

::

== ' ') {

IPCO/USR/CHUCK/CSRC/UAP.C
if' (!done) -(

WT'ite("\n This numb.T' is too big. \n It h.s to b. less than 65536. \n")1
WT'ite("\n Ent.T' numb.T' --> ")1
}
}

else
WT'it.(" Ill.gal Ch.T'act.T'\n Ent.T' a numbeT' -->")1
}

if' (h •• )

T'.tuT'n (lIIh) I
T'.tuT'n (lIId) I
}

ch, lIIidth) 1* conveT't.n int.geT' to .n ASCII stT'ing *1

Int_To_Ascii(v.lue. b •••• Id.
unsigned long
valuel
u_shoT't
bas.. lIIidth.
ch.T'
chtl. Idl
{

=

foT' (i
01 i < lIIidthl i++) {
J .. value X b.s ••
if (J < 10)
chtil
J + 0.301
else chtil .. J + 0.37.
value" value 1 bas.l·

=

}

foT' (i .. lIIidth .;.. 11 chtil ... '0' && i > 01
chti] = Idl
chtlilidth] '" '\0'1
}

WT'it._Long_Int(dlll,
unsigned long
u_shoT't
il

i)
dllli

{

u_shoT't
ch.T'

JI
chtll]'

i f (dhexl

Int_To_Asc iU dill,

16.

'

"

&chtO], 8)1

.ls.
Int_To_Ascii(dlll' 10, ' " &chtO].
foT' (J
01 chtJ] != '\0'1 i--, J++l
lin.[1] .. ch[JlI

=

10)1

}

'WT'it._ShoT't_Int(lII,
u_shoT't III. il

il

-(

.u_shoT't JI
chaT'
cht6]1
unsign.d 10.ng

dllli

dill .. 1111
i f (dhex)
Int_To_AsciUdlll'
else

16.

'0', &ch[O]. 4)1

4-58

i--)

IPCO/USR/CHUCK/CSRC/UAP.C
Int_To_Ascii "),

}
}

Read_Addr(pmsg,

cnt) 1* pmsg - pointer to the output message *1
1* add
pointer to the address *1
1* cnt - number of blltes in the address *1
add[l. cnt,

add.

char

*pmsg.

char

i.

(

for

Ji
)

(

Write(pmsg),
Read(&cb·uf[Ol. 80. &actual),
'01' (J
skip (&cbuf[Ol). i = 0, i ( 2*cnt , i++. J++) {
i f « '0' (= cbuftJl) && (cbuf[JJ <= "1'»
cbuf[il = cbuf[Jl - '0',
else
i. «'A' <= cbu'[JJ) && (cbuf[Jl <- 'F'»
cbuf[il = cbuf[Jl - 0.37,
else
i. « ' a ' (= cbu'[Jl) && (cbuf[JJ <- 'f'»
cbu'[il = cbuf[JJ - 0.57,
else {
Write(" Illegal Character\n"),

=

bTeaki
}

}

i. (i >= 2*cnt break,

1)

}

'01'

(i = 0, i
add[(cnt -

cnt - 1, i++)
1) - il = cbuf[2*i]

(=

«

4

}

Write_Addr(padd. cnt)
char
padd[]' cnt,
{

unsigned char
for ( ,

cnt >0

i.
I

c[3],

cnt--) {

4-59

cbuft2*i + 1],

IPCO/USR/CHUCK/CSRC/UAP.C
i = paddCcnt-1JI
Char_To_Ascii(i, &c[OJ);
Write(&cCOJ),
}

c[O]

=

'\n/i

cC1J = '\0'1
Write(&cCOJ );
}

1* Receives the Frame from the 802.2 module *1
struct

FD

{

struct FRAME_STRUCT
struct TBD
struct RBD
char
int
prbd
prFs

*prfs, *ptfsi
*ptbd, *begin-ptbd, *ql
*prbdl
*prbuf;
cnti

= (struct RBD *) Build_Ptr(pfd->rbd_ofFsetl;
= (struct FRAME_STRUCT *) Build_Ptr(prbd->buff-ptr);

switch (prfs->cmd & ~P_F_BIT)
{
case
UI:
if (monitor_flag)
break;
1* Don't put data in fifo unless in terminal mode *1
prbuf = (char *) prfs;
prbuf += 3/ 1* skip over the header info and point to the data *1
cnt
31
pfd->length -= 3;
for (, prbd != pNULL, cnt ,= 0, prbuf = (char *) prbd->bufi'J'tr){
for ( , cnt < (prbd->act_cnt & Ox03FFF) && pfd->length > 0,
cnt++, prbuf++, pfd->length--l {
while(r_buf_stat == FULLl,
Fifo_R_In(*prbufll

=

}

prbd = Build-Ftr(prbd->link).
lIifdef DEBUG
if (pfd->length == 0 && prbd != pNULL)
Fatal("Uap: Recv_Data_1act_cnt = EOFBIT I XID_LENGTH.
bcopy «char *) ptbd->buff-ptr, &xid_frameCOJ,
ptfs = (struct FRAME_STRUCT *) ptbd->buff-ptrl
ptfs->cmd
prfs->cmd.

XID_LENGTH),

=

ptfs->dsap

= prfs->ssap

C_R_BIT.

1* return the frame
to the sender *1

ptfs->ssap = ssap'
while(!Send-Frame(ptbd, Build_Ptr(pfd->src_addr»).

4-60

IPCO/USR/CHUCK/CSRC/UAP.C
break.
TEST:

case

for (prbd = (struct RBD *) Build_Ptr(pfd->rbd_offset).
q = begin_ptbd = pNULL. prbd != pNULL.
prbd = Build_Ptr(prbd->link» {
while «ptbd = Get_Tbd(» == pNULL).
i f (q != pNULL)
q->link = Offset(ptbd).
else
begin-ptbd = ptbd.
ptbd->act_cnt = prbd->act_cnt.
bcopyC(char *) ptbd->buff_ptr. (char *) prbd->buff_ptr.
ptbd->act_cnt & Ox3FFF).
q = ptbdl
}

pHs = (struct FRAME_STRUCT
ptfs->cmd = prfs->cmd.
ptfs->dsap

~

*)

begin-ptbd->buH-ptr.

prfs->ssap

1* return the frame to
the sender *1

ptfs->ssap = ssap.
while(!Send-FrameCbegin-ptbd. Build_Ptr(pfd->src_addr»).
break;
}

Put_Free_RFA( pfd).

1* return the frame *1

}

1* called by main program *1

Fifo_T_Out()
{

char

c;

Disable_Uart_Int( ).
if (out fifo t == in fifo t)
1* if the fifo is empty *1
t_b;;-f_stat = EMPTY. 1* stop filling Transmit Buffer Descriptors *1
else
1* if the fifo was full and·is now draining *1
if Ct_buf_stat == FULL && out_fifo_t - 80 == in_fifo_t) { 1* turn on
the spigot *1
INUSE.
}

Enable_Uart_lrit().
return(c).
}

Fifo_T_InCc)
char
Ci

1* called by Uart receive interrupt *1

{

fifo_t[in_fifo_t++l = c.
if (t_buf_stat == EMPTY)

4-61

IPCO/USR/CHUCK/CSRC/UAP,C

= INUSE,

1* start filling Transmit Buffer Descriptor *1
turn off the spigot *1
if (t_buf_stat == INUSE ~~ in_fifo_t + 20 == out_fifo_t) {
RTS_OFFB,

t_buf_stat
else

1* if there are only 20 locations left,

}
}

1* called by transmit interrupt *1

Fifo_R_Out()
{

char

c;

if (out_fifo_r

==

in_fifo_r)
1* if the fifo is empty *1
= EMPTY,
else
1* if the fifo was full and is now draining *1
if (r_buf_stat
FULL ~& out_fifo_r - 81
in_fifo_r)
r_buf_stat = INUSE,
return(c)i
r~buf_stat

==

==

}

char

Ci

{

fifo rein fifo r++) = c,
Disable_Uart_Int()'
if (r_buf_stat == EMPTY) {
UART_TX_EI_B'
CD(O);
1* prime the interrupt *1
r_buT_stat = INUSE,
}

1* i f the buffer is full. indicate it *1
if (r_buf_stat == INUSE ~~ in_fifo_r
out_fifo_r)
l ' buf stat = FULL,
Int
(),
_Uart
Enable
else

-

}

Isr _Uart( )
{

stat,

int
char

c,

switch(inb(CH_B_CTL) & OxlC){ 1* read 8274 interrupt vector and service it *1

if (r_buT_stat
EMPTY) {
UART_TX_DI_B'
RESET _TX_INT'

1* iT fifo is empty disable transmitter *1

}

!!lse
outb (CH_B_DAT, Fifo_R_Out(»,
,

brea~

4-62

IPCO/USR/CHUCK/CSRC/UAP.C

outb(CH B CTL. 1); 1* point to RRl In 8274 *1
stat
i"nb(CH_B_CTLl;
outb(CH_B_CTL. Ox30);
if (stat & Ox0010)
Wrlte("\nParlty Error Detected\n");
if (stat & Ox0020)
Wrlte("\nOverrun Error Detected\n");
if (stat & Ox0040)
Write("\nFraming Error Detected\n");
break;

=

if (hs_stat
hs_stat
break;

==

TRUE) {

= FALSE;

1* Flag to terminate High Speed-Transmit mode *1

)0

If (local echo)
Co(c )-;-

==

1* echo the char back to the terminal; could cause
a transmit overrun if Tx interrupt is enabled *1

if (c
CTL C)
tmstat -FALSE;
else
Fifo_T_In(c);
break;

=

outb(CH_B_CTL. Oxl0);
break;

1* reset external status interrupts *1

outb(CH_A_CTL. Ox10);
break;
default:
.}

EOI_80130_8274;
EOI_8274;
}

Isr2( )
{

send_flag = TRUE;
outb (Ox EA. 125);
outb(OxEA. OxOO);
Dutb(OxEO. 0.62);

1* Timer 1 interrupts every . 125 sec *1
1* EOI 80130 *1

}

4-63

IPCO/USR/CHUCK/CSRC/UAP.C
Load_L.ap( )
0(

.

int

Recv_Data_")1

for(; ;) 0(
Read_Addr("\n\nEnter this Station'. LSAP in He. --> ". Srssap. 1)1
if (!Add-psap~ddre •• (.sap. Recv_Data_1» 0(
Write("\n\nError: LSAP Addre •• must be one of the following: \n");
Write("\n
20H. 40H. 6OH. SOH. AOH. COHo EOH \n");
}

el.e breakl
}
}
Load~ultica.t()
0(

for ( ; ; ) 0(
Read_Addr ("\nEnter the Mul tica.t Addre •• in He. --:>'''.
SrMulti_Addr[OJ. ADD_LENll
if «Mu1ti_Addr[0] Sr Ox01) == 0)
.
Write("\nSorrll' the LSB of the Mu1tica.t Address mu.t be l\n");
else 0( if (!Add~ultica.t_Addre •• (SrMulti_Addr[O]» 0(
Write("\n\nSorrll' Multica.t Addre •• Ta.ble i. full !\n"l;
breakl
}

el.e

0(

Write("\n\nWould lIoU like ·to add another Multica.t Addre •• ?")1
Write(" (VOl' N) --> ")1
i f (!VesO)
breakl
}

}
}
}

Remove_Multicast()
0(

for ( ; ; ) 0(
Read_Addr("\nEnter the Multicast Addres. that IIOU want to delete in Hex -->".
SrMulti_Addr[OJ. ADD_LEN);
if «Multi_Addr[O] Sr OxOl)
0)
.
Write("\nSorrlJ' the LSB of the Multicast Address must be l\n")1
else 0( if (!Delete~ulticast_Address(SrMulti_Addr[O]» 0(
Write("\n\nSorrll' that Multicast Address doesn't exist!\n");
break;

==

}

else

0(

Write("\n\nWould 1J0u like to delete another Multicast Address?");
Write(" (VOl' N) --> ")1
i f (!Ves(»
breAk I
}
}

}
}

4-64

IPCO/USR/CHUCK/CSRC/UAP.C

Print_Addresses()
{

struct
int

MAT *pmat.
stat.

Write("\n This Stations Host Address is: ").
Write_Addr(&whoamirOJ. ADD~LEN).
Write("\n The Address of the Destination Node is: ").
Write_Addr(&Dest_AddrrOJ. ADD_LEN).
Write("\n This Stations LSAPAddress is: ").
Write_Addr(&ssap. 1).
Write("\n The Address of the Destination LSAP is: ").
Write_Addr(&dsap. 1).
stat = FALSE I
for (pmat '= &matrOJ. pmat <= &matrMULTI_ADDR_CNT - 1J. pmat++)
if (pmat->stat == INUSE) {
stat = TRUE.
break.
)0

i f (stat)

{
Write("\n The following Multicast Addresses are enabled: ").
for (pmat = &matrOJI pmat <= &matrMULTI_ADDR_CNT - 1J. pmat++)
if (pmat->stat == INUSE) ,{
Write_Addr(&pmat->addrrOJ. ADD_LEN).
W,.ite(1I

It);

)0
)0

else

Write("\n There are no Multicast Addresses enabled. \n").

)0

Init_DataLink ()
{

int

stat,l

if «stat = Init_Llc(» == PASSED)
Write("\n\nPassed Diagnostic Self Tests\n\n\n").
else
if(stat == FAILED_DIAGNOSE)
Write("\n\nFailed: Self Test Diagnose Command\n").
else
'if(stat == FAILED_LPBK_INTERNAL)
Write("\n\nFailed: Internal Loopback Self Test\n").
else
if(stat == FAILED_LPBK_EXTERNAL)
Hrite("\n\nFailed: External Loopback Self Test\n").
else
if(stat == FAILED_LPBK_TRANSCEIVER)
Write("\n\nFailed: External Loopback Through Transceiver 'Self Test\n").
}

outb(OxEO. Ox31).
outb(OxE2. Ox20).

I*initalize 80130 pic - ICW1 *1
1* ICW2 *1

4-65

inter
IPCO/USR/CHUCK/CSRC/UAP.C
autbCOxE2.
autbCOxE2.
autb COxE2.
autbCOxE2.

Oxl01,
OxODh
Oxl011
OxFF),

1*
1*
1*
1*

aut",COxFF20. 01002011

ICW3
ICW4
ICW6
mask

*1
*1
*1
all inte""upts *1

1* set 80186 vecta" base *1

1* Initialize the 80130 time"s fa" Te"minal Made *1

autbCOIEE;
autbCOxE8.
autbCOxE8.
autbCOxEE.
autbCOIEA.
autb COxEA.

01341,
01B81,
OxOB), 1* SVSTICK set fa" 1 msec *1
017011
1251,
OxOOl1 1* Tillie" 1 inte""upts eve,,~ . 125 sec *1

1* Initialize
autbCCH_B_CTL.
autbCCH-A_CTL.
autbCCH_B_CTL.
autbCCH_B_CTL.
autbCCH~_CTL.

the 8274 *1
01101, autbCCH_B_CTL. 0128)1 autbCCH_B_CTL. 0130),
Ox38)1
21, autbCCH_B_CTL. IIIl'b[2]
Ox14),
1)1 autbCCH_B_CTL. IIIl'b[l] = Ox15),
5), autbCCH_B_CTL.· ",,,b[5]
OxEAI,

W" i te C"\n\n\n\n\n\n\n\n\n\n\n\n"),
W"iteC"
******************************************************\n")
WriteC"
* 82586 IEEE 802.2/802.3 Compatible Data Link Driver *\n")
WriteC"
******************************************************\n")
W"ite C"\n\n\n\n\n\n\n") I
Init_DahLinkC )1
dhex '" FALSEI
manita"_flag = TRUEI
Read_Add"C"\n\nEnte" the Add"ess of the Destination Node in Hex --:> ".
&Dest_Add,,[Ol. ADD_LEN I ,
Read-AddrC"\n\nEnte" the Destination Node's LSAP in H". --:> ". I!");

CVesCI)
Laad_MulticastCI,

}

Te"minal_MadeC)
(

int
st"uct
cha"

f"ame_cnt. buf_cnt,
TBD
*ptbd. *q. *begin-ptbdl
*pbuf. c,
.

W"iteC"\n Would you like the local echo an? CV aT' NI--:>")I
ifCVes()I

4-66

IPCO/USR/CHUCK/CSRC/UAP.C
local_echo

TRUE,

local_echo

FALSE,

else
Write("\n This program will now enter the terminal mode. \n\n"I'
Write("\n Press AC then CR to return back to the menu\n\n"I,

1* Initialize Fifo variables *1
in fifo t = out fifo_~ = in_fifo_r
EMPTY, -r_buf_stat = EMPTY,

out_i'i fo_t
t_buf_stat

0,

EOI_B0130_B274,
Enable_Uart_Int(11
Enable_Timer_Int( II
monitor_flag = FALSE,
tmstat = TRUE,
while (tmstat) {

== pNULL), 1* get a xmit buffer from the
data link *1
pbuf = (char *) ·ptbd-:>buffJltr, 1* point to the buffer *1
buf_cnt = 0,

while «ptbd = Get_Tbd(»

0) { 1* if this is the first buffer, add on IEEE B02.2
header information *1
beginJltbd ~ ptbd,
*pbuf++
dsap'
*pbuf++
ssapl
*pbuf++ = UI,
buf_cnt = 31
}

else q-:>link = Offset(ptbd), 1* if this isn't the first buffer
link the previous buffer with the new one *1
1* fill up a data link xmit buffer from async transmit fifo *1
for ( , buf_cnt < TBUF_SIZE && frame_c~t < MAX-FRAME_SIZE,
buf_cnt++, pbuf++, fra~e_cnt++) {
if (frame_cnt != 0 && send_flagl
break,

==

while (t_buf_stat
EMPTY),
1* wait until fifo has data *1
if «c - *pbuf = Fifo_T_Out(» == CR) {
++buf_cnt , ++pbuf' ++frame_cnt'
break,
}
}

if (c == CR :: buf_cnt < TBUF_SIZE I: send_flag) { 1* last buffer in list *1
ptbd-:>act_cnt = buf_cnt I EOFBIT,
send_flag
FALSE,
break,
.

=

}
}

while(!Send-Frame(beginJltbd,

&Dest_Add~[O]»,

}

4-67

1* keep trying until
successful *1

inter
/PCO/USR/CHUCK/CSRC/UAP.C
Disable_Uart_Int().
Disable_Timer_IntC).
monitor_flag
TRUE.

=

}

struct TBD
u_short

*Build-FrameCcnt)
cntl

{

u_~hort

struct
char

buf_cnt. frame~cnt. i.
*ptbd. *~. *begin-ptbdl
*pbuf. .

TBD

for C • •
while

= ptbd) {
CCptbd = Get_TbdC» ==

~

p~ULL).

pbuf = Cchar *) ptbd->buff-ptr.
buf_cnt
O.

=

0) {

=

1* get a xmit buffer from the
data link *1

1* point to the buffer *1

1* if this is the· first buffer.
header information *1

add on IEEE B02. 2

begin-ptbd
ptbd.
*pbuf++
dsapl
*pbuf++
ssap.
*pbuf++ = UI.
buf_cnt = 3 •
.}

else

~->link

= OffsetCptbd).

1* if this isn't the first. buffer
link the previous buffer with the new one *1
1* fill up a data link xmit buffer with ASCII characters *1
for C. buf_cnt < TBUF_SIZE ~~ cnt > O.
i++. buf_cnt++. pbuf++. cnt--. frame_cnt++) {
*pbuf
i.
if Ci > Ox7E)
Ox IF.
}

if Ccnt == 0) { 1* last buffer in list *1
ptbd->act_cnt
buf_cnt : EOFBIT.
breakl
}
}

returnCbegin_ptbd)1
}

Monitor ModeC)
{

-

u_shoT't
xmit, cnt, ii
struct TBD
*Build_Frame(). *ptbd;

Write(" Do you want this station to trarismit? (V or N)
if' CVesC»

4-68

--> ").

IPCO/USR/CHUCK/CSRC/UAP.C
for (xmi t = FALSE, xmi t == FALSE, ) {
Write("\n Enter the number of data bytes in the frame --> "),
cnt = Read Int(),
i f (cnt > 2045)
Write ("'n Sorry. the number has to be less than 2046!\n"),
else
xmit = TRUE,
}

else xmit = FALSE,
Write("\n Hit any key to exit Monitor Mode. 'n'n"),
Wr tel" # of Good
Wr tel"
Frames
Wr tel" Transmitted

# of Good

Frames
Received

Alignment
Errors

CRC
Errors

No

Resource
Errors

Receive\n ll ) ;
Overrun\n");
ErT'ors\n lJ

);

1* "0123456789012345678901234567890123456789012345678901234567890123456789012345678
xx x x
xxxx
xxxx
xxxxxxxxxx
xxxxxxxxxx
xx xx
xxx xxx xx
xxxxxxxx
44
57
25
33
11

for (i = 0, i < 79,
line[i]
0.20,
line[79]
CR,
line[80] = "0',

=

i++)

while «inb(CH_B_CTL) & 1) == 0) {
for (i = 0, i < 72, i++)
line[i] = 0.20,
Wri te_Long_Int (g ood_xmi t_cnt, 11),
Write_Long_Int(recv_frame_cnt. 25),
Write_Short_Int(scb. crc_errs. 33),
Write_Short_Int(scb. aln_errs. 44),
Write Short Int(scb. rsc errs. 57),
Write-Short-Int(scb.ovr-errs. 71),
Write(&line[O]),
.
i f (.mit) {
ptbd = Build_Frame(cnt),
while(!Send_Frame(ptbd. &Dest_Addr[O]»,
}

}

Ci( ),
}

Hs_Xmit_Mode( )
{

struct

TBD

*ptbd,

Write("'n Hit any key to exit High Speed Transmit Mode. 'n'n"),
hs_stat = TRUE,
EOI_80130_8274,
Enable_Uart_Int()'
1* Execute this loop until a recv char interrupt happends at Uart *1

4-69

IPCO/USR/CHUCK/CSRC/UAP.C
while (hs_stat) {
while «ptbd = Get_Tbd(»

1* get
the
ptbd-:>act_cnt := EOFBIT,
1* set the
while( !Send_Frame(ptbd, &Dest_AddrrOl», 1*
pNULL),

a xmit bufrer from
data link *1
End Of Frame bit *1
Send Frame *1

}

}

chUll, base, dwidth,
char
unsigned
long
temp'

width,

i,

(dhexl {
dwidth ~ 0;
width = 4,
base = 16,
}

else {
base = 10,
~Ulidth = 10,
width,::;. 5;
}

Write("\n\n Good 'rames tran.mitted· "),
for ( i = 1; i <:= 11 - dwidth, i++)
Co(SP),
Int_To_Ascii= 0; i--)
Co(chllj),
Write("
Good frames received: 11);
for (i = 1, i <:= 15 - dwidth, i .~ .-t' ,
Co(SP),
Int_To_Ascii(recv_frame_cnt, base, , , , i!= 0, i--)
::..J~ch[iJ);

Write("\n\n ('j'"\C ~""T"ors received: II);
for (i = 1, i <:= 15 - wijt~; i++)
Co(SP),
temp = scb. crc_errs,
Int_To_Ascii= 0, i--)

width),

:o/~hri]);

Write(1I
A.1J.~nme'"t errors received:
II);
1'01' (i = 1,
i <:= 10 - ... dth; i++)
Co(SP),
temp = scb.aln_errsi
c.chlO], width),
Int_To_Ascii(temp, base,
for (i = width - 1; i .>= 0, i--)
Co(chr.iJii

t..e' "\n\n Out or Resource frames: ")i
for (i = 1, i <:= 12 - width, i++)
Co(SP),
temp = scb.rsc_errs,
occhrO], width),
Int_To~scii(temp,
base·

;,,~,

j.

4-70

IPCQ/VSR!(,HUC"/l:I:;RC/UAP.C
for (i = width - 1. i >= O. i--)
Co Cch [ i J).
Wr i te (" Rec e i ver overrun framp,,· '"
far (i = 1; i <= 12 - ItJi~t;f •• 1+'+)
CoCSP).

temp =

~:~.

uvr errs;

int_To_AsciiCt;mp. base. ' '. LchtOJ. width).
for Ci - width - 1. i >= O. i--)
CoCchCiJ ).
WriteC"\n\n 82586 Reset: ",.
for Ii = 1. i <= 23 .. width. i++)
Cc(SP) :
~~mp :
reset_cnt.
Int_To_AsciiCtemp. base. , '. LchtOJ. width).
for Ci = width - 1. i >= O. i--l
CoCchtiJ).
WriteC" Transmit. undel'l·un frames: "I.·
fo.,. (i = I; i ..:= 11 - width. i++)
CoISP).
temp
underrun_cnt.
Int_To_AsciiCtemp. base. ' '. LchtOJ. width);
for Ci
width - 1. i >- O. ;--,
CoCchtiJ).
Writ,,("\n\n Lo~t CRS: "I.
f.oT' (i = 1. i <- 26
width. i++)
CoCSPI.
temp
no_crs_cnt.
Int_To_Asciiltemp, base. ' '. LchtOJ. widthl.
for (i = width - 1. i >= 0, ;.--,
Co I ch t i J).
WriteC" SGE errors: ");
for Ii - 1. i
25 - width. i++)
CoISP).
temp
sqe_err_cnt.
Int_To_Asciiltemp. base. , '. !!-chtOJ. width).
for Ii
width - 1; i >= O. i--)
CoCchCiJ).
~riteC"\n\n Maximum retry:
").
for Ii = 1. i <= 21 - width. i++)
CoISP).
temp
max_col_cnt.
Int_To_Asciiltemp. base. , '. LchtOJ. width).
for Ii = width - 1. i >= O. i--)
ColchtiJ).
WriteC" Frames that deFerred: ").
for Ci = 1. i <= 15 - dwidth. i++)
CoCSPI.
Int_To_Asc iiI defer _cnt. base. ' '. Lch tOJ. dwidth).
for Ci
dw.idth - 1. i >= O. i--)
CD Cc h t i J ).

=

=

=

<:=

=

=

=

=

Write e"\n\n Commands are:\n\n").
Write C" T - Terminal Mode

M - Monitor Mode\n").

4-71

IPCO/USR/CHUCK/CSRC/UAP.C
W,.ite (" X
W,.ite (" P
W,.ite (" A
W",ite (" S
W,.i-te (" N
W,.ite (" R

High Speed T,.ansmit Mode
p,.int All Counte,.s
Add a Multicast Add,.ess
Change the SSAP Add,.ess
Change Destination Node Add,.ess
Re-Ini tiali ze the Data Link

V - Change T,.ansmit Stati~tic5\n");
Clea,. All Counte,.s\n" );
Delete a Multicast Add,.ess\n");
Z
D
Change the DSAP .Add,.ess\n");
L - PT"int All Add,.esses\n" );
Change the numbe,. Base\n");
B
C

}

Main( )
-(

int

c;

Ini t_Uap ();
P"int_Help ();
fo,.

(II)

-(

W,.ite ("\n\n Ente,. a command. type H fo,. Help --:> ");
c = Read Cha,.();
.wi tc h (Lowe,. _Case (c»- -(
case "h';
P"int_Help ();
b,.eak;
case ' m':

Moni to,. _Mode ();
b,.eak;
case 't':

Terminal_Mode( );
b,.eakl
case ' x':
Hs_Xmit_Mode( );
b,.eakl
case 'v':

W,.ite("\n T,.ansmit Statistics a,.e now");
if (flags. stat_on == 1)
W,.ite("on. \n Would you like to change it ? (V 0,. N) --:> ");
else
Write("o.f. \n WDuld you like to change it ? (V 0" N) --:> ");
if· (Ves(»
-(
if (flags. stat_on == 1)
flags. stat_on = 0;
else 'lags. stat_on = 1;
}

b,.eak;
case 'p':

p,.int_Cnt( );
b,.eakl
case 'e':

Clea,. _Cnt ( );
b,.eak;

case 'a':

Load_Multicast();
b,.eak;
case

'x';

Remove_Multicast();
b,.eak;
case

'5':

4-72

IPCO/USR/CHUCK/CSRC/UAP.C
Delete_Dsap_Add~ess(ssap),

Load_Lsap ( ),
b~eak'

case 'd':
Read_Add~(n\n\nEnte~

the Destination Node's LSAP in Hex --:> n,

I!cdsap,

b~eak,

case 'n':
Read_Add~(n\n\nEnte~

the

Add~ess

of' the Destination Node in Hex --:> n,
I!cDest_Add~[OJ,
ADD_LEN),

b~eak,

'1':

case

P~int_Add~esses(),
b~eak,

case 'r':
Sof't.a~e_Reset()'

InitJ>ataLink(

)1

Add_Dsap_Add~ess(ssap,

Recv_Data_l)'

b~eak'

'b':

case

The cu~~ent base is n),
TRUE)
W~ite(nHex. \n Would \Iou like to change it ? (V o~ N) --:> n),

W~ite(n\n

if' (dhex

==

else
W~ite(nDecimal.

i f (Ves(»

{
if' (dhex
dhex
else dhex

\n Would \IOU like to change it ?

== TRUE)
= TRUEI

= FALSE.

)-

def'aul t:
W~ite

(n\n Unkno .. n command\nn).

b~eak,

)-

))-

4-73

(V

O~

N) --:>

n),

1),

IPCO/USR/CHUCK/CSRC/ASSV.ASM
name
stack
stktop
stack

segment stack
label
word
ends

.DLD_DATA
extrn
SEGMT :word
DLD_DATA
UAP _DATA
UAP _DATA

'stack'

segment public

segment pub lic
ends

DLD30DE

'DATA'

extrn
extrn

segment public 'CODE'
Isr_Timeout_:far, 151'_586_: far, Isr7_:far
151'6_: far, 151'5_: far, 151'1_: far
ends

extrn

segment public 'CODE'
Isr_Uart_: far, Isr2_: far,
ends

DLD_CODE

UAP_CODE

segment public
pub lic
pub lic
argl
arg2

'DATA'
data segment address

I

'CODE'

inw_, outw_, init_intv_, enable_, disable_. Build;..PtT'._
Offset_. begin. inb_, outb

equ
equ

[BP + 6J
[BP + 8J

assume
assume

CS:DG_CODE
DS:DLD_DATA

1+

initialization program for the 82586 data link driver
1-

begin:
sti
mov
mov

ax. DLD_DATA 1get base of dgroup and
SEGMT_. ax
"lpass the segment value to the c program

mov

ds,

ax

call Main_
hlt

inb

proc
push
mov
push
mov
in
pop
mov

far·
BP
BP.
DX
DX,
AL.
DX
SP.

)go to the c program

SP
arg1
DX
SP

4-74

inter
IPCO/USR/CHUCK/CSRC/ASSY.ASH

inb
outb_

outb
inlll_

inlll_
outlll_

outlll_

pop
ret
endp

BP

proc
push
mov
push
push
mov
mov
out
pop
pop
mov
pop
ret
endp

far
BP
BP.
DX
AX
DX.
AX.
DX.
AX
DX
SP.
BP

proc
push
mov
pUsh
mov
in
pop
mov
pop
ret
endp

far
BP
BP.
DX
DX.
AX,
DX
sp,
BP

proc
push
mov
push
push
mov
mov
out
pop
pop
mov
pop
ret
endp

far
BP
BP.
DX
AX
DX,
AX.
DX.
AX
DX
SP,
BP

SP
argl
arg2
AL
BP

SP
argl
DX
BP

SP
argl
arg2
AX
BP

Build J'tr
push
mov
mov
mov
mov
pop
ret
Build_ptr

proc
far
BP
BF. SP
DX. DLD_DATA
AX, ·argl
SP. BP
BP

Offset_ proc

far

endp

4-75

inter
IPCO/USR/CHUCK/CSRC/ASSY.ASM

Ol>fset

push
mov
mov
mov
pop
T'et
endp

seT'vl!_int_isT'
push
push
push
push
push
push
push
push

BP
BP. SP
AX. aT'gl
SP. BP
BP

PT'oC
AX
BX
CX
DX
SI
Dl
DS
ES

faT'

mov
mov
mov

AX. DLD_DATA
DS. AX
ES. AX

call

1ST' _586_

pop
pop
pop
pop
pop
pop
pop
pop
iT'et
seT'vl!_int_isT'

ES
DS
Dl
SI
DX
CX
BX
AX

seT've_int_8274
push
push
push
push
push
push
push
push

PT'oC
AX
BX
CX
DX
SI
Dl
DS
ES

endp
faT'

mov
mov
mov

AX. UAP_DATA
DS. AX
ES. AX

call

1sT' _UaT't_

pop
pop
pop
pop
pop

ES
DS
DI
SI
DX

4-76

inter
IPCO/USR/CHUCK/CSRC/ASSV.ASM
pop
pop
pop
iT'Ilt
seT'ye_int_B274

CX
BX

AX
endp

seT'ye_int_timeout
push
AX
push
BX
push
CX
push
DX
push
SI
push
DI
push
DS
push
ES
moy
moy
moy

PT'OC

AX. DLD-PATA
DS. AX
ES. AX

pop
ES
pop
DS
pop
DI
pop
SI
pop
DX
pop
CX
pop
BX
pop
. AX
iT'et
seT'ye_int_timeout
seT'ye_int7 _iST'
push
push
push
push
push
push
push
push
moy
moy
moy

faT'

endp
faT'

PT'OC

AX
BX

CX
DX
SI
DI
DS
ES
AX. DLD-PATA
DS. AX
ES. AX

call

15T'7

pop
pop
pop
pop
pop
pop
pop
pop

ES
DS
DI
SI
DX
CX

-

BX

AX

4-77

IPCO/USR/CHUCK/CSRC/ASSY.ASM
i .... t

s .... v .. _int7_is..
se .. v .. ...;i nt6_i 5 ..
push
push
push
push
push
push
push
push

..ndp
p .. oc

AX
BX
CX
DX
S1
D1
OS
ES

mov
mov
mov

ES,

call

15 .. 6_

pop
pop
pop

ES

p~p

pop
pop
pop
pop

AX, DLD_DATA
DS, AX
AX

DS
D1
81

DX
CX
BX
AX

i .... t

se .. ve_int6_is..
se .. ve_int5_is ..
'push
push
push
push
push
push
push
push

endp
p .. oc

AX
BX
CX
DX
sl
D1

DS
ES

mov
mov
mov

AX, DLD_DATA
DS, AX
ES, AX

call

15 .. 5_

pop

ES

pop

DS

pop
pop
pop
pop
pop
pop

D1

S1
DX
CX
BX
AX

i .... t

se .. ve_int5_is..

endp

4-78

intel®
IPCO/USR/CHUCK/CSRC/ASSY. ASM
serve_int2_isr
push
push
push
push
push
push
push
push

proc
AX
BX
CX
DX

far

51

Dl
DS
ES

mov
mov
mov

AX, UAP _DATA
DS, AX
ES, AX

call

Isr2

pOp
pop
pop
pop
pop
pop
pop
pop
iret
serve int2_isr

ES
DS
Dl
SI
DX
CX
BX
AX

serve_intl_isr
push
push
push
push
push
push
push
push

proc
AX
BX
CX
DX
SI
DI
DS
ES

-

endp
far

mov
mov
mov

AX, DLD_DATA
DS, AX
ES, AX

call

Isrl

pop
pop
pop
pop
pop
pop
pop
pop
iret
serve _intl isT'

ES
DS
Dl

enable

far

proc
sti

51

DX
CX
BX
AX
endp

4-79

inter
IPCO/USR/CHUCK/CSRC/ASSY.ASM
ret
enable_ endp
disable

proe

eli
ret
disable_

endp

init - intv
push
push

proe
DS
AX

xor
mov

far

far

AX, AX
DS, AX

; Interrupt types for the 186/51 COMMputer
mov
mov
mov
mov
mov
mov
mov
mov
mov
mov
mov
mov
mov
mov
mov
mov

DS:lllord
DS:lllord
DS:lllord
DS:lllord
DS:lllord
DS:lllord
DS:lllord
DS:lllord
DS:lllord
DS:lllord
DS:lllord
DS:lllord
DS:lllord
DS:lllord
DS:word
DS:lllord

pop
pop
ret

AX
DS

init - intv -

ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr
ptr

80h,
82h,
84h,
86h,
88h,
8Ah,
8Ch,
8Eh,
90h,
92h,
94h,
96h,
98h,
9Ah,
9Ch,
9Eh,

offset serve - int _8274
DG_CODE
offset,serve_intl_isr
DG_CODE
offset serve - int2 - isT'
DG_CODE
offset serve - int isr
DG_CODE
offset servE!' - int - timeout
DG_CODE
offset serve - int5- is"
DG_CODE
offset serve - int6 - isr
DG_CODE
offset serve - int7 - is,..
DG_CODE

-

int 0
int
int 2
int 3
int 4
int 5
int 6
int 7

endp

DG _CODE ends
end

be-gin, . d's': did_date, 'ss: ,.taC'k: st'ktop

4-80

Application Examples

5

CHAPTER 5
82586 APPLICATIONS
number of wait states (i.e. the additional CPU cycle
times required between memory address to valid data
received), and handling 82586 buffer/status overhead
that can be tolerated before the on·chip FIFOs exceed
their capacity.

5.0 OVERVIEW
This chapter is a collection of brief notes related to
system considerations when using the 82586 LAN Co·
processor. The chapter is based on work performed by
Intel's Data Communications Applicatiori Engineering
staff. This work includes computer simulations and ac·
tual debugged hardware/software designs.

Second, interframe spacing gives additional time for the
82586 to complete placing received data into memory
and handle 82586 buffer/status overhead. Figure 5·1
shows the timing relationship and activities performed
by the serial side and parallel side of the 82586.

5.1 MINIMUM 82586 SYSTEM
BUS SPEED
82586 Bus bandwidth requirements are an important
concern. Parameters that dictate 82586 system bus use·
age are: buffer size, FIFO· Threshold, interframe spac·
ing, serial data rate, wait states, bus latency, and 8 or 16
bit bus width. The relationship between these parame·
ters is complex.

Simulations were performed to provide guidelines to
designers to establish minimum Fs/Fp ratios given var·
ious bus latency, wait state, and interframe spacing
time conditions. The simulations assumed a system us·
ing word mode, and worst case conditions consisting of:
last buffer exactly filled up, next buffer remaining emp·
ty, and prefetch of next buffer descriptor. The most
recently received frame was assumed OK.

A worst case analysis can be done to determine the
minimum bus frequency that the 82586 must have to
receive two or more back to back frames. There are two
variables of concern. First, the ratio of the parallel bus
frequency, Fp, to the serial clock frequency, Fs. The
Fp/Fs ratio affects bus latency (i.e. the time it takes for
the 82586 to acquire control. of the bus),

The results of these simulations are shown in Figure
5·2. Note that various wait state (NW) and bus latency
(Nd environments are represented by sloped lines, ac·
cording to the empirical formula 16 Nw + NL = X
clock cycles.

SERIAL CHANNEL:

2ND FRAME
FILLS THE
TEMP.RG
2ND FRAME
AND THE
-r'::..IF;:,S_ _f...:..P:;.RE:::A::M::;B::L::E:..-_ _+-.:.R:::X:..:.F.::IF.::O=--_+_--i.

•

•

T

I

FIRST PACKET
END

I
I
I

I
I
I
I

1ST FRAME

I REgEA:~ON
I COMPLETION BY
I THERCVDMA

. RU COMPLETION OF 1ST
FRAME RECEPTION RCV
DMA SETUP FOR
2ND FRAME

-r___

PARALLELPROCESSORLI_ _ _ _

~--

__

I
I
I

i

I

I
I

---~I~-~.

T

i

1ST BYTE OF
2ND FRAME DUMPED
FROM RX FIFO

Figure 5-1. Receive to Receive Interframe Spacing Time Relationships
5·1

230814-75

LAN COMPONENTS USER'S MANUAL

The following example illustrates use of Figure 5-2:
Wait states, Nw ~ 0 clock cycles
.
Bus latency, Nt: .= 0 clock cycles
IFS
= 9.6 J.Ls

5.2 SETTING THE 82586 FIFOTHRESHOLD
The 82586 features a programmable FIFO-Threshold,
see section 2.10.4. When the threshold value is reached,
the 82586 attempts to acquire the system bus via the
HOLD/HLDA protocol.

From Table 5-1, the minimum Fp/Fs is 0.58. In other
words, for Fs = 10 MHz, i.e. IEEE 802.3, then Fp can
be as slow as 5.8 MHz.

If the FIFO-Threshold is set too low, the 82586 will be
constantly accessing the system bus, creating system inefficiencies because the CPU and other system peripherals must perform additional overhead duties. related
to relinquishing the bus. If the FIFO-Threshold is set
too high, the 82586 may not acquire the bus before the
FIFO becomes full (or empty), causing received (or
transmit) data to be lost. Thus, an optimal threshold
setting can be found based on the number of times the
82586. accesses the bus, and ensuring that received data
does not get lost.

One can verify that for IEEE 802.3, where Fp/Fs =
0.8 (i.e. Fp = 8 MHz), that the 82586 can handle the
9.6 J.Ls Interframe spacing (IFS) even when the sum of
16 times the number of wait states (Nw) plus bus latency (NL) is equal to 80. For example, a 82586 system of
o wait states, and bus latency of 80 clock cycles can
handle back to back frames, separated by the IFS time.
Table 5-1 summarizes Fp for various bus latency/wait
state conditions for IEEE 802.3 from Figure 5-2.
. Table 5-1: Minimum Bus Frequency
for IFS = 9 6J.Ls
NW(Clock)

NL(Clock)

Fp (Min) MHz

0
0
1
1

0

5.8
5.9
6.2
6.3
6.5
6.8

J

2
2

5
0

5
0

5

The variables of concern to setting the FIFO-Threshold
are parallel bus frequency (Fp), serial clock frequency
(Fs), and the bus latency time (NL)' The ratio fo Fp/Fs '
is important because it quantifies the relationship between how quickly the FIFOs are filled, and.howfast
the FIFOs can be emptied. The latency time quantifies
the amount of time the 82586 must wait before it can
begin to empty the FIFOs.

20
19

~
CI

z

(j

~
II)
w
:;;
«a:
u.
a:
w

RCVTO RCV
18 I - - IFS VS.lslfp
FOR DIFFERENT
17 1---1- 16nw+ n, -

g~~~~-

16

VALUES

15

I

I I I J/
I VI

~~B~~.
,l ,;
e:1/

--.

:t..

T::

.,.

~

t:

1-

t

c:

.,.

J- t -

1-

.t

<:~ <:~ <:~
~ ~ Ie ~/-,..;;

J
I II I II I
...~
I
I I
12
I
I
I
lJ
11
II I
I
10
__
9.6 -j-- -f-l
9
I II 1 II II
8
I 1 / I
I / I / I I
II I I I I , .
,
I 1
I
I I I I I
3
I
I I /
I
/ I I ) j
,
II I II I II
14
13

.!.E.!'~80~3

1.33

1.0

0.8

0.67

0.57

0.5

0.44

0.4

fplls

230814-76

Figure 5-2_ CPU/82586 Parallel Bus Frequency Requirements for given Wait States (Nw)
.
and Bus Latencies (Nd
5-2

LAN COMPONENTS USER'S MANUAL

82586 system simulations were performed to provide a
starting point with which to set an optimal threshold
setting. For an actual system, the FIFO-Threshold setting should be further optimized to accommodate particular application, system and network environments.
The results of the simulations are summarized in Tables
5-2 and 5-3. Table 5-2, the minimum safe FIFO limit
presents guidelines for threshold setting, for a given bus
latency. Table 5-3 takes into account time required for
the 82586 to perform buffer switching. The results from
both tables must be added together to yield the recommended threshold limit.

Table 5-3. FIFO Limit Offset

Consider the following example:
Parallel Bus Frequency, Fp = 8 MHz
Serial Clock Frequency, Fs = 10 MHz
Maximum bus latency, NL = 4 clock cycles
From Table 5-2 (Fp/Fs
safe FIFO limit = 1.

= 0.8, NL = 4), the minimum

NL

Minimum FIFO Limit

0
1
2
3
4
5
8
10
15
20
2!?
30
40
0
1
2
3
4
5
8
10
15
20
25
30
40

1
2
2
2
2
3
3
4
5
6
8

FIFO Limit Offset

0
0
0
5
5
5
10
10
10
20
20
20
40
40
40

6
5
3
8
6
4
10
8
5
13
10
7

-

15
10

The 82586 employs memory buffer· chaining to ensure
efficient use of memory as described in sections 1.3.1,
2.5.1, 2.8.6, and 2.9.
From a network point of view, the minimum buffer size
should be no less than the largest 'short' (control)
frame plus a few bytes. This practice will eliminate unnecessary buffer linking. A minimum of 64 to 128 bytes
is usually sufficient.

Table 5-2. Minimum Safe FIFO Limit
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8
0.8

NL

0.4
0.5
0.8
0.4
0.5
0.8
0.4
0.5
. 0.8
0.4
0.5
0.8
0.4
0.5
0.8

5.3 THE MINIMUM BUFFER SIZE

From Table 5-3 (using NL = 5), the FIFO limit offset
= 4. Taking the sum of the results from Tables 5-2 and
5-3, the FIFO-Threshold setting for preliminary evaluation should be 5.

Fp/Fs

Fp/Fs

From the 82586 point of view, the upper bound of receive buffer size is 11 function of the network environc
ment and system memory constraints; the lower bound
is a function of the 82586'8 ability to prefetch receiVe
buffer. descriptors and· buffer fill time. In· particular,
while the 82586 is filling up a buffer, the 82586 will
prefetch the next receive buffer .descriptor. Thus, the
prefetch must be completed before the current buffer
becomes full.

9

11
0
0
1
1
1
1
1
2
3
3
4
5
6

The variables affected receive buffer fill time, and consequently minimum buffer size, are the parallel bus frequency, Fp, and serial clock frequency, Fs, bus width,
and wait states, Nw. Computer simulations were performed on a· general system to provide designers with
the minimum receive.buffer size. The results are shown
in Table 5-4.
The following example illustrates use of Table 5-4.
Given:
• .Parallel bus frequency, Fp

NOTES:

• Serial clock frequency, Fs,

Fp = Parallel Bus Freq\Jency
Fs = Serial Clock Frequency
NL = Bus Latency (in cycles)

=
=

8 MHz
10 MHz

• Wait states, Nw = 1
• Bus width = 16 bits (word mode)
From Table 5-4, the minimum receive buffer size is 20
bytes.

5-3

LAN COMPONENTS USER'S MANUAL

Note that from Table 5-4 that .the largest minimum is
55 bytes. Thus, it can be concluded that in general receive buffers in excess of 64 bytes are sufficient for the
82586 to handle linked lists in hardware.

5.4 .SYSTEM CONFIGURATIONS
5.4.1 80186 Elementary Maximum
Mode System

Table 5·4. Minimum Buffer Size
NW = 0
Nw = 1
Nw= 2
Fp/Fs

Word
Mode

0.4
0.5
0.8
1

51
47
36
36

Byte
Mode

Word
Mode

26
24
24

55
51
34
34

.

Byte
Mode

Word
Mode

Byte
Mode

•

22
22
22

42
42
30
30

.

SYSTEM INTERFACE
The 82586 does not require any 'TTL glue' to interface
to an 80186 microprocessor bus. Thus, it is highly recommended for minimum compqnent count commurucation systems (see Figure 5-3). The 82586 is configured to Maximum Mode by strapping the MN/MX pin
to ground; in this mode'the 82586 generates status signals that will be used for bus control signal generation.

20
20
20

NOTES:
'Will always underrun or overrun
Fp = Parallel Bus Frequency
Fs = Serial Glock Frequency

The 82586 is clocked by the CLKOUT signal generated
by 80186. Thus, the existing address latches, data transceivers and bus controller can be shared by the CPU
and the 82586.

The minimum transmit buffer size is determined by the ' '
The SO, SI signals of the 80186 and 82586 are wired
same factors as receive buffers plus end-of-frametogether, driving the 8288 bus controller. The .80186
processing (updating status, pointers, BD count, and
and 82586 have internalPullups so no external resistors
statistics; setting up the RU for the next reception;
are required on the SO, SI, S2lines. The 8288's S2 input
etc.). The 82586 can underrun if the values of Table 5-4
is driven only from the 80186; this status is not generatare used for the first transmit buffer of a frame to be
ed by the 82586 because it accesses memory only (no
transmitted: Underruns will occur when the 82586 is
I/O). Tl;1e SO, SI and S2 lines are used by the 8288 to
issued a Transmit command just prior to or during a
generate a full set of standard bus control signals.
receive operation. In this case, during reception the
82586 will fetch the first TBD and fill the Transmit
FIFO. After the completed reception, the 82586 will
The shared data bus of the 80186 and the 82586 is 16
bits wide. The system memory can be accessed either by
start transmission and simultaneously complete end"ofthe 80186 or by the 82586. Bus arbitration is resolved
frame-processing. End-of-frame-processing will delay
by the HOLD/HLDA protocol. The CPU grants the
the prefetch of the second TBD, and cause the underbus to the 82586 by issuing the HLDA high as a rerun. Thus the minimum length of the firSt Transmit
sponse to bus request from the 82586 (HOLD high).
Buffer must be long enough so that the next TBD preThe CPU is able to withdraw its bus grant by dropping'
fetch will ocCur before' the first buffer is transmitted.
HLDA low. In this case the 82586 will release the bus
For systems with Fp/Fs = 0.6 a first transmit buffer in
excess of 75 bytes is usually sufficient to avoid underwithin a maximum four clock cycles in word mode (see
section 2.10.3).
runs; for systems with Fp/Fs = 0.8, the first transmit
buffer should be in excess of 54 bytes. The succeeding
Care must be taken so that the CPU does not take away
transmit buffers for a single frame can follow the recommendations of Table 5-4..
HLDA during transmission or reception because there
will be a high chance of frame abortion by underrun or
overrun respectively.
The 82586 supports simultaneous transmit and end-offrame-processing operations to ensure that the 82586
Communication on the task level between the CPU and
will be able to transmit soon after a receive operation.
the 82586 is accomplished by a shared system memory
Thereby avoiding the case where a receiving station
mailbox, the System Control Block, and the CA/INT
continually gets beaten onto the network by other stations. This case is important in communication intenhandshake.
sive applications like file servers.

5-4

LAN COMPONENTS USER'S MANUAL

It is possible to create a multimaster system by using
the 8289 bus arbiter. It is suggested that in these systems the 82586 communication node is assigned the
highest priority. A high priority will ensure a minimum
bus latency for the 82586 whenever it needs the bus,
thus avoiding waste of bus bandwidth by underrun or
overrun frames.

The 8289 Bus Arbiter is needed to resolve Multibus
arbitration. It is recommended to assign the 82586 system the highest priority in order to efficiently handle
communication tasks. The highest priority interrupt request on the Multibus, INTO, is used to inform the
remote CPU that a communications task was completed.

To realize the IEEE 802.3 standard (i.e. 10 Mbps serial
data rate and 9.6 Iks Interframe Spacing), it is sufficient
to operate at 8 MHz system clock and zero wait state
bus cycles. Also, lower rates and slower memories (that
introduce wait state) are possible in IEEE 802.3 systems, see section 5.1.
'

5.4.3 Dual Port RAM Systems

SYSTEM INTERFACE
The 82586 operating at 10 Mbps serial bit rate, may
utilize a significant percentage of bus bandwidth, thus
leaving insufficient bus bandwidth for other purposes.
When the 82586 bus bandwidth utilization is intolerable, a dual port memory system with one port dedicated to the 82586 is recommended. Figure 5-7 displays a
typical dual port memory based system.

SERIAL INTERFACE
Figure 5-3 displays an 80186 based Elementary Maximum Mode System, containing an Intel 82501 Ethernet
Serial Interface.

The basic building blocks for the dual port RAM system are standard dynamic RAM's and the 8207
DRAM Controller. The 8207 provides not only dynamic RAM refresh, but also arbitrates between each of the
process requests and directs data to or ,from the appropriate port. The 8207 has a LOCK capability that enables the 82586 to lock out CPU accesses while the
82586 finishes descriptor and error tally processing, see
section 2.7.6.

5.4.2 Stand Alone Multibus System

SYSTEM INTERFACE
It is possible for an 82586 CPU system to share a mem-

ory interface via the Multibus as shown in Figure 5-4.
The Multibus is the Intel's standard bus structure
which allows Intel's board products to communicate.
Standard address latches, data transceivers and a bus
controller are needed in order to interface to a demultiplexed Multibus.

5-5

::!!

.

cc
c

RESET

.

II)

MNiMX

C11

~

00

~

00

0)

m
iii

3

II)

::J

(11

S'

80186

HLO

HOLD

HLOA

HlOA

ClKOUT
RESET OUT
INTO

elK
RESET
INT

TXO

rxc
82586

I '"~ ~
LPBK

I ......1.' ...
-

TRMT

~' 11_

-

I

I

1----+--1 "XO
RX·C

cor

Rxe
COT

r~

Z

(')

ETHERNET

I::===:t::~ c'ifs
TEN

~~N
ClS~N

ETHERNET
SERIAL INTERFACE

:::::====1

1:1

o

COAXIAL
CABLE

82501

3:

J

'tI

oZ

ETHERNET
TRANSCEIVER

m
Z

DeCODe

lOGIC

-I

en
c:
en
m
::u

c»~

s:
QI
~.

en

3
3
c

3:

s:

~

z

&.

c:

II)

~

(J)

~
~

r230814-77

, r 1 ~rl

LOOPBACK

0

LJ>Bi( XI

X2

no

TRMT

TiC

TRMT

."

IE'
c

RiC

CD

CRs

Rev

CLSN

i

TEN
CLSN

~

Q)

N
01

~

Q)

a>

MN/MX

(J)

m X[i];
(0 shift the CRC register *)
A[15] ._ A[14] ;
A[14] ._ A[13] ;
A[13] ._ A[12] ;
(* exclusive or 0)
A[12] ._ A[ll] <>FB;
A[ll] ._ A[lO] ;
A[lO] ._ A[9] ;
A[9] := A[8] ;
A[8] := A[7] ;
A[7] := A[6] ;
A[6] := A[5] ;
A[5] := A[4] <> FB;
A[4] := A[3] ;
A[3] := A[2] ;
A[2] .- A[l] ;
A[l] ._ A[O] ;
A[O] := FB;
END

5-10

LAN COMPONENTS USER'S MANUAL

Table 5-5. PROGRAM Hash Calculation (INPUT, OUTPUT) (Continued)

ELSE
BEGIN
FB := A[31]
A[31]
A[30]
A[29]
A[2S]
A[27]
A[26]
A[25]
A[24]
A[23]
A[22]
A[21]
A[20]
A[19]
A[lS]
A[17]
A[16]
A[15]
A[14]
A[13]
A[12]
A[ll]
A[lO]
A[9]
A[S]
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[l]
A[O]
END;
END;

.

( * separate computation for CRC-32 *)

<> X[i] ;

( compute feedback *)
( * shift the CRC register

*)

:= A[30] ;
:= A[29] ;
:= A[2S] ;
:= A[27] ;
:= A[26] ;
:= A[25] <> FB;
:= A[24] ;
:= A[23] ;
:= A[22] <> FB;
:= A[21] <> FB;
:= A[20] ;
:= A[19] ;
:= A[lS] ;
:= A[17] ;
:= A[16] ;
:= A[15] <> FB;
:= A[14] ;
:= A[13] ;
:= A[12] ;
:= A[ll] <> FB;
:= A[lO] <> FB;
:= A[9] <> FB;
:= A[S] ;
:= A[7] <> FB;
:= A[6] <> FB;
:= A[5] ;
:= A [4] <> FB;
:= A[3] <> FB;
:=A[2] ;
:= A[l] <> FB;
:= A[O] <> FB;
:= FB;
( * of CRC calculation *)

(* select the 6 bits out of the CRe register *)
IF A[5] THEN Y := 1 ELSE Y := 0;
IF A[6] THEN Y := Y + 2;
IF A[7] THEN Y := Y + 4;
IF A[2] THEN Y := Y + S;
IF A[3] THEN Y := Y + 16;
IF A[4] THEN Y := Y + 32;
HASH := Y;
(* return the value *)
END; ('of hash function *)

5-11

LAN COMPONENTS USER'S MANUAL

Table 5·5. PROGRAM Hash Calculation (INPUT, OUTPUT) (Continued)

BEGIN
(* main program that interacts with the user *)
WRITELN ('This program calculates the hash function of Multicast addresses') ;
WRITELN ('Type CTRL/Y for exiting the program')'
WRITELN (' ');
WRITE ( 'Enter CRC length (IS for CRC-lS) > > ');
READLN(CRCLength) ;
WRITE ('Enter Address length (in bytes) > > ');
READLN(AddressLength) ;
IF AddressLength>S THEN WRITELN(' Out of range !')
ELSE BEGIN
REPEAT

(*

for each Multicast Address in the set *)

FOR k:=O TO 47 DO MCV[k] := FALSE;

(*

ini tializethe multicast vector

*)

WRITELN('Enter Multicast Address (exactly', AddressLength*2:3,' hexadecimal
digits') ;
. WRITE ( , starting with MOST significant) > > ');
FOR k:= AddressLength*2-1
BEGIN
READ (digi t) ;
IF (48<=ORD(digit))
ELSE
IF (S5<=ORD(digit))
ELSE
IF (97<=ORD(digit))

DOWN TO 0 DO

for all digits *)
read a hexadecimal digit *)
and convert it to binary *)
AND (ORD(digit) <58) THEN numb ._ (ORD(digit)-48)
(*
(*
(*

AND (ORD(digit) <71) THEN numb .- (ORD(digit)-55)
AND (ORD(digit) <103) THEN numb := (ORD(digit)-87);

FOR 1:=0 TO 3 DO
BEGIN

(* convert t~e digit to binary and
insert it to the vector *)
IF ODD (numb) THEN MCV[4*k+l] ._ TRUE ELSE MCV[4*k+l] := FALSE;
numb := numb DIV 2;
END;

END;
READLN ;
(* flush the line
IF NOT MCV[O] THEN WRITELN ('not a multicast address!');

*)

(* call the hash function *)
WRITELN('HASH = ',HASH(AddressLength, CRCLength, MCV);
UNTIL FALSE;
END;
END.

(* for ever *)
(* of loop for specific Multicast Address

5-12

*)

LAN COMPONENTS USER'S MANUAL

5.6 A LOW COST DUAL PORT
MEMORY DESIGN

5.6.1 Hardware Design
The major characteristics of the hardware design are as
follows:

The 82586 is a bus master designed to share the CPU
system bus. The shared bus configuration affords systems that use the fewest components and lower cost.
However, in some applications the bus bandwidth required by the 82586 may seriously degrade system performance. The solution to this problem is a dual port
memory between the host CPU and the 82586. Figure
5-6 illustrates a shared bus system and Figure 5-7
shows a dual port 82586/CPU system configuration.

Dual Port Memory Size
8K bytes
- Static RAM's
Memory Type
CPU
80186
Bus Arbitration Logic
- TTL SSIIMSI chips
82586 Bus Speed
8 MHz
82586 Serial Data Rate
10 Mbps

In 82586 applications the dual port approach is useful
in the following cases:
1) To minimize bus contention between the CPU and
the 82586. The 82586 bus interface design is free of
bus latency concerns. This issue is important in systems where the peripherals attached to the system
bus cause latency that cannot be tolerated by the
82586, or vice versa.
2) To interface to a limited bandwidth bus. The 82586
may consume as much as 2M bytes/s bandwidth
while transmitting or receiving data at 10 Mbps. The
instantarieous bandwidth required to meet the IEEE
802.3 specification is even greater. In a dual port
system the host CPU is able to access memory when
the 82586 is accessing memory, thus high system
performance is maintained. This issue is particularly
important in 8-bit bus systems.
3) To simplify the interface between the 82586 and
non-Intel CPUs.

The objective of this hardware design is to keep the
design simple and inexpensive. Figure 5-8 shows a
block diagram of the hardware. The CPU interface is
general enough to simplify the interface to CPU's with
multiplexed or demultiplexed data/address buses. The
size of the system RAM is a function of the following
factors:
1) Network traffic size.
2) Net traffic pattern (size of frames).
3) Other CPU tasks.
The memory size is 8K bytes to satisfy typical needs.
However, the hardware accommodates expansion of
the dual port RAM. Static RAMs are used to keep the
design simple and low cost.
The 82586 is set to Minimum Mode to keep the chip
count low. The CPU for the example is the 80186. Figure 5-9 shows a general purpose CPU interface.

This section describes an example of dual port design
using the 82586 with an 80186.

!I

+

HLDAHOLD

I

HLDAHOLD
82S86

CPU

II
SHARED
MEMORY

230814-82

Figure 5·6. A Typical Shared Memory Design Using the 82586

5-13

LAN COMPONENTS USER'S MANUAL

BUS
ARBITER
CPU

82586
A.

A-

MULTIPLEXER

"

DUAL PORT
MEMORY

230814-83

Figure 5-7. A Typical Dual Port Memory Design Using the 82586

HOLD/HLDA

READY
ACCESS ENABLE

I

11

ARBITRATION
LOGIC
(WAIT STATE GEN.)

(1)-'

(1)0

CPU

r--

READY ACCESS ENABLE

-'(I)

Ula:
a: I-

0(1)

00

00

a:UI
I-a:

oz

zo



DATA
IN CLUDE ADDRESS LATCH
A NO BUS TRANSCEIVER

INCLUDE ADDRESS LATCH
AND BUS TRANSCEIV ER

~.. co"'.o,
MEMORY

DATA

230814-84

Figure 5-8. Hardware Block Diagram

5-14

LAN COMPONENTS USER'S MANUAL

signal is active. During this period the Ready signal
going to the 80186 Ready generation logic is disabled.

BUS ARBITRATION LOGIC

Bus contention between the 82586 and the 80186 is re-.
solved on the basis of the following principles:
I) When the 82586 is accessing the Dual Port Memory
RAM, the CPU is prevented from accessing the
memory by inhibiting the Ready signal.
2) The CPU can access memory whenever the 82586 is
not accessing it.

The Dual Port RAM generates its own Ready signal
for the 80186. This Ready signal is only generated
when the 80186 accesses the Dual Port RAM and the
82586 HOLD is inactive. Other memory blocks and
peripherals should generate their own Ready signal.
Thus all the Ready signals going to the 80186 can be
ORed together provided that they are normally low.
Asynchronous Ready is used for both 82586 and 80186
for ease of implementation. This design requires zero
wait states for both 82586 and 80186 access. However,
for slower memories, a wait state generator may be
added to the Ready generation logic.

3) The 82586 gains control of the bus within four to

five clocks after a request, and the CPU is put into
the wait mode.
The sequence of events when the 82586 requests the bus
is:

SETTING THE FIFO LIMIT

I) The 82586 requests the bus by activating the HOLD
signal.

When the 82586 needs the bus, it activates its HOLD
signal and waits for the HOLD Acknowledge signal
(HLDA) before starting any memory access cycles. In
the case when the CPU and the 82586 are on the same
bus, the HOLD signal from 82586 will go to the HOLD
input of the CPU. The CPU will eventually grant the
HOLD Acknowledge (HLDA) to the 82586. The time
to grant HLDA is dependent on the CPU and the task
it is executing at the time of the HOLD request. When
HLDA is granted, the 82586 starts its memory access
operations.

2) The HLDA is given to the 82586 after five clocks
max.
3) The Ready signal to the CPU is disabled within one
clock of the 82586 HOLD request.
4) The CPU is isolated from the dual port RAM by
disabling the data buffers within 2 clocks of the
82586 HOLD request.

The 8~586 Receive and Transmit FIFO-Threshold limits are set as a function of the HOLD-HLDA delay.
The following Receive case illustrates how the FIFOThresholds are set. Assume that the Receive FIFO trigger is set at 6. This setting will ensure that the 82586
will make a bus request when 6 bytes have been placed
into the Receive FIFO. Since the FIFO is 16 bytes
deep, the 82586 must start emptying out the FIFO before the FIFO fills up. In this example, the 82586 must
acquire the bus within 10 bytes time (16 - 6 bytes) to
avoid an overrun condition. At 10 Mbps, 10 bytes
equates to 8 microseconds or 64 CPU clocks (assuming
the CPU is running at 8 MHz clock rate). Depending
upon the application environment, granting the bus to
the 82586 in 64 clock times mayor may not be easy to
accomplish.

5) The multiplexer is switched to the 82586 bus.
6) If the CPU is accessing the dual port RAM at the
time of the 82586 bus request, the CPU is either
placed in a wait mode, or it is given enough time to
complete its ·bus cycle.
7) If the CPU has been placed in a wait mode, it remains there until the 82586 is done with the Dual
Port RAM. Then the CPU's data and address buffers are enabled, the Ready signal is enabled and the
multiplexers are switched back to the CPU, thus allowing the CPU enough time to complete its cycle.
The Channel Attention for the 82586 is generated using
a peripheral chip select line of the 80186. In this application, the interrupts from the 82586 are ignored. The
diagnostic software, discussed in section 5.6.2, works
under an interactive polled environment.

The dual port design avoids the problems associated
with bus latency. The HOLD Acknowledge is given to
the 82586 within 5 clock cycles of the HOLD request,
thus allowing for very small HOLD-HLDA delays.

READY GENERATION

The 82586 operates in a burst mode when it is reading
or writing to the memory. The length of the burst is a
function of the number of bytes .in the Receive or
Transmit FIFO at the time the 82586 gets the HOLD
Acknowledge signal. When the 82586 obtains control
of the bus, it empties the entire contents of the FIFOs.

The design adopts a simple scheme to generate the
Ready signal for the 82586 and the 80186. The Ready is
generated when either the Read or Write signal goes
active. The 82586 is given the Ready signal if it is holding the bus (HOLD active) and either Read or Write

5-15

LAN COMPONENTS USER'S MANUAL

ElUS ARBITRATION lOGIC

CPU READY

CPU ACCESS ENABLE

CONTROL

CPU

READY

230814-85

Figure 5-9. General Purpose CPU Interface

5-16

LAN CQMPONENTS USER'S MANUAL

CPU READY CONTROL

:~EWRBHE~ ~
82586
ADO-IS
A16-A21

DTIR

DEN

]
230814-86

Figure 5-9. General Purpose CPU Interface (Continued)

5-17

LAN COMPONENTS USER'S MANUAL

.".

. ....

""

'C~

"

,

l~

RESET
Jo.2(I

FIG 5·12C

5lMiREADT

'"r-

,

PCS61

,

'"
"

,'I"

,,.

,

111

"

Ull

UJ

~

0

'"

J elk

0

a

32

RESET
elK

37

AROYSADY

"

C.

r

AI"

"'

i~

···

'V

~

AD10

"
""

"
"
""
HC'N
..' "
8H ""

.,.

".

HOLD

,---.!!. m

6

I

......'".,,, "
.......,, ""
.., ."

A012
A01,

en

"" "'m"
rn
"" .,.

~

II,

"

'"." "",
."."AI. ,,
'"
AI. ,
,
"013 ,
""
A014

-

~
2

MINMt

AOl5

5

IT2

IIRl

ceo

ULS74

r-

n.

.

0'::It!!

~o

"
"'"' ~lIs ~Ii!iiliil
"

c..:.:.::!l.

516

""'"

.

RC'

" "

rr
J2·'

\

J2-2

~

c,

,

'~".H'

"'
;;c;

,

~.

2

c,

a2SO'

TAMTTiiiii

r

~ C'~~F

_

,, "

CLSN

crm

"

"

~ ~~ ~ p-

J2·1

J2 ...

J2·S

.-----

J2·6

(TRANSCEIVER CONNECTOR,

.,,,,,

FIG S·12e 12516 HLOA

FlO. S-12e 125M

5]U30/'

N!CiR

230814-87

Figure 5-10A. 82586 Dual Port D~sign Schematics

5-18

LAN COMPONENTS USER'S MANUAL

l~
:

00'
0"'
00'
00'
DO.
00'
000
000

0"
0"

rll" Hl-"

~~
~ ft:::
~

J"
00'
00.

0"
Ou
0"
000

DO.

::

~g;
om

11

000

... ,,'

6~ ~
o.

.fr- =:! ...,

.
--7< "

r-~

..l

I..
0"
0"

f!-

U.

J

U]J

uoo

"

cs

"
"'0' "
0'
DO

...

c

>

",

"

19

'1"

.......
....,
..

I ..
0"
0"

00'
00.
00>
00'
DO.

0"
OU
0"

DO'
000

,, ,

"
"
""
"
U

"''''
"'A>

...

,"''',

y,

..

.,
.,.,

T

"

.."

SIMien •
WOI]

.

"
"
.
y,

....

.,

.T

AS

..,,
A3

A>

a,
a,

a.
a,
a•
a.
a,
a•

..."'0''"

YlOID

"

,"'D'
.....
..."'0''"

,"
,"

.aD.

'"'0'

"'00

.0

'"'"'

.:======:t============================:::;-__-:::-_-=
..~HO~L~D
Ol!
fl

1IG.5-12.

1m DJO-:J6
~OE,~"l::=:j'~",,~D
OJO
INTa

JO..:15

_:l1

230814-88

Figure 5-10A. 82586 Dual Port Design Schematics (Continued)

5-19

LAN COMPONENTS USER'S MANUAL

.~

~::::~ ~I
.10·13
JO·16

tl~'1

;

111

.11.24

== : :. i~
=;: i~,

AD"

g!~

.11·23
.11·22
.11·21

,

UI4
DE

~,

K

R~:~

~r.: fli
IE;

::~

' .. DRI

1I.e,,,

US"
U21

111

'\.. •

1H RAM ACe

./
' .. e.~

J1-2G
.II·"
.11·11

FIG.5·12C

Jl·17

II!! ::.:DE' ~~,

"'-1'

U15

Jl·15
.11·14
.11·13

'1',
111
Jl·12
.11-11

I[

.11-10

Jl·9
M

.11-7

Jl·&

Jl·5

Y.

~7

....
U17

DE

--.-J

FIO.S·12D

111

!!
82..

.11.21 - I!lDEM

,.. m;r.

,,~

=

U1I

::

B1

n.

Y.

.101.00LE

_.",,,ml'

230814-89

Figure 5-108. 82586 Dual Port Design Schematics

5-20

LAN COMPONENTS USER'S MANUAL

Thus maximum bus efficiency is achieved when the
82586 acquires the bus with a full FIFO. A very small
HOLD-HLDA delay will allow a high setting of the
FIFO-Threshold. The HOLD-HLDA handshake between the 82586 and the CPU always results in a finite
amount of wasted bus clock cycles due to HOLD and
HOLD Acknowledge synchronization by the 82586
and the CPU, as desqribed in section 2.10.3.

The diagnostic software has the following capabilities.
• Initialize the 82586 by setting up the System Control Pointer, Intermediate System Control Pointer
and System Control Block.
• Create it linked list of 16 Frame Descriptors for receive frames. These Frame Descriptors were linked
to a linked list of 16 Buffer Descriptors, which in
turn pointed to 16 buffers, each of 128 bytes. Figure
5-11 illustrates the memory structure set up.
• The interactive software, package is capable of setting up and executing one or all (through linked
lists) the 82586 Action Commands, namely NOP,
IA SETUP, CONFIGURE, MC SETUP, TRANSMIT, DUMP, TDR, and DIAGNOSE. Additionally, the contents of these commands can be modified
from the console and more than one command may
be executed by linking them onto a linked list.
• The System Control Block commands for the Command Unit, as well as the Receive Unit, can also be
given from the console.
• The Transmit and Receive Frame Descriptors and
buffers can be modified interactively from the console.
• Several commands are available for interactive observation. In particular, the following fields in the
82586 memory structures are available for observation:

In summary, the HOLD-HLDA handshake results in
wasted bus clocks. In order to realize an efficient system, the 82586 must transfer 'the maximum number of
bytes before giving up control of the bus. In the case of
the 82586, these burst sizes should be 16 bytes (Le. the
FIFO size). The objective of the design should be to
have 16 bytes in the FIFO when the 82586 gets the bus,
so that it may empty out the FIFO in a single burst. A
short HOLD-HLDA delay reduces the concern for
DMA overruns; thus a high FIFO-Threshold setting is
possible.
Another advantage of this design is that HLDA is always given to the 82586 between 4 and 5 clock cycles
after a HOLD request. This provides more efficient bus
utilization than with a direct microprocessor interface
where HOLD and HLDA latency will vary much more
than one clock cycle.
The discussion above centered on reception, however
the same arguments are true for Transmission. Recall
from section 2.10.4 that when programming the FIFOThreshold using the CONFIGURE command, the parameter programmed is the threshold point for the
Transmit FIFO. The Receive FIFO-Threshold is sixteen's compliment (15-trigger parameter) of the value
programmed.

1) System Control Block:
• Status field
• Acknowledge bits
• cue, RUC fields
• Error tallies (alignment, CRC, overrun and resource errors)

Hardware schematics are shown in Figure 5-IOA
through 5-IOD.

2) Command Blocks:
• Status field
.. Link field

5.6.2 Application Software
The 82586 dual port hardware design was tested using
an 80186 based board, running at 8 MHz. Two ribbon
cables access the 80186 address, data, and control signals. These signals are brought to the 82586 board via
connectors JO and 11 (see Figure IOE). The 80186
board operated with an Intel iSBC 957B package moni-'
tor program. The 957B monitor was used to debug
82586 hardware and software. For more information
on the 957B monitor, refer to the "iSBC 957BTM iAPX
86/88 User's Guide" (Intel order number 143979-002).
The 82586 diagnostic software allows interactive usage.
The software was developed using an Intel MDS Series
III and downloaded to the 82586 board through the
serial link on the 80186 board.

5-21

• Command related parameters
3) Transmit and Receive Buffers:
• Transmit and Receive Buffer Descriptors and
buffer areas
• Receive Frame Descriptors
Table 5-6 contains the software listings for this application. Figure 5-12A through 5-12K illustrates the flow
for, the software modules.

· LAN COMPONENTS USER'S MANUAL

...,.
,...
,..

..
..,.
,,..
..
..,.,.,.
3.
3.

745251

un
745257

3'

3V
745257

.,

3.

,.,,.,.".
..

74$257

"

,."

745257

"

230814-90

Figure 5-10C. 82586 Dual Port Design Schematics

5-22

LAN COMPONENTS USER'S MANUAL

rn
rn
ffi

rn

ClJJ.2t

OJln

CJ

HOI

QJHl

ffi

OJ),O

IT!

CJ

L:::=c::J

Jl·\g

'"
J)·\b

L:::::::c:i JJ.\~

L:::=c::J
L:::=c::J
L:::::c:i
L:::::c:i
L:::::c:i
L:::=c::J
L:::::c:i

t:::::::::cJ

L:::=c::J

J3·'4
J3·1]
J3·13

J)·12
J3-1\

J3-9

JJ-8

J3·1
JJ·6

t:::::::::cJ
t:::::::::cJ
t:::::::::cJ

J3·17

c:=:::c::i

JJ·25

J3·5

LaS
iJ"BS

J3·18

WE
MRo
MWR

FIG.5-I2A

10 14S08

______________________________________________

~9~8

80186AEAOV

80186

ACID

O

JO-13

FIG. 5.12B

.2586HOLOA

FIG,S'12'"

230814-91

Figure 5-10C. 82586 Dual Port Design Schematics (Continued)

5-23

LAN COMPONENTS USER'S MANUAL

.,.,
.,

..
AS

..

.s
.,

.."..."
"

WI

r---

~l~

~'8

y:~

U35
13

FIG.S·12C

,

Uei

-

2..d. U36

YOp!L-

lA
G

,

"

f

745139

14532

""

r--YJ~

--1.'8

. .
~]

'OS

U36

,

,.

U35

Yl~
Y.~

G!-

Yo

'-tT45139

o.
o.
0"

on

230814-92

Figure 5-100. 82586 Dual Port Design Schematics

5-24

LAN COMPONENTS USER'S MANUAL

.

,
,
•

AI

•
,

A,
A,

·..
..

un

··.
·...
,

AI
A,
A,

I

AI

"

'" "

UH

el

A' WE

I

UlO

.,

1.

~

,

'" "

I

.. ""

2'1~'8·21·41

,~ A,~

"
15

I

I

el

y.

"

.,

I

U..

el

y.

10

T

I

I~

I

el

y" y.

". "

I

~ J3-4t

10J 12

D"

". "

D"

2'1 ... 8·21.41

16 A,
15 A,
"'WE

U..

U02

U"'

C. I

" 'i.

.,

c.

I

.,

'i.

10

.,

U..

e.

y.

'0

I

I~

c•

"

'I" 'I.

D"

D"

D"

:.
,

I

A,

I

·.

A,
,• AI
I A,

,,"
IS""., C. I ,

.

U:.

U..

I,A,

y.

"

·, .
·."
,

AI

•
,

A,
AI

,

A,

I

?14tB-21141

"

1. Al

y.

"
I

I

y.

I

10

C. I

'$,t"

",WE
10

-y.

U5I

c.
'0

y.

I

c•
__

WE

1" y.

t

D.

.

D'

J3-:t1

D'

J3·lQ

"

D'

"

D.

102 13

DI

.,

C. "

DO

y~

y.

U52

e.

"

r·
IOl

USO

.,

D'

..

I

21418-21·41

U..

102 13
I~

., C. I .,
"

D.

U..

U..

c.

". "
'" "

I~

I
..

230814-93

Figure 5-100. 82586 Dual Port Design Schematics (Continued)

5-25

LAN COMPONENTS USER'S MANUAL

JO-CONNECTOR
ll----.---____
82586
BOARD

CPU BOARD
(GSP)

J1-CONNECTOR

- JO, J1 ARE 50 PIN 3-M EDGE CONNECTORS
- JO, J1 PIN ASSIGNMENT

PIN

.

12, 13, 23, 29, 30, 35, 36, 37

{
JO

FUNCTION;

{
J1

PIN

:

FUNCTION:

PCS6, MCS2, ARDY, PCLK,

SHE, INTO, INT1, INT2

5-24, 26, 28, 29, 31, 34, 36
ADO-AD19,

AD, WR, DEN, ALE, DT/R, RES
230814-94

Figure 5-10E. 82586 Dual Port Memory Test Hardware

r--1

RFD (15)

RB(O)
128 BYTES

RB(1)
128 BYTES

RB (15)
128 BYTES

TB(O)
128 BYTES

TB(1)
128 BYTES

TB(15)
128 BYTES

230814-96

Figure 5-11. Memory Map for 82586

5-26

LAN COMPONENTS USER'S MANUAL

Table 5-6. Software Listings
/ ... ****-**************************************""'*************.,.********
*
*
*
*
8258b DUAL PORT MEMORY DESIGN
*
*

*
*
*
*
*
*

INTERACTIVE DIAGNOSTIC SOFTWARE
.JAN.

SNIMH

'84

*
*
*
*
*
*

*********1i**************************************'It*******************/

DIAGN05T I CS$FOR$8258b:

2

DO,

declaT'e MAIN label publici
1* Word Dec lare */

3

literally 'IIHILE 1',

declare FOREVER

1* Constant Declare *1
4

declare CA$PTR
LPBKSONSPTR
LPDI\$OFF$PTR
CMD$START
RCV$START
Cr1D$ADORT
RC"'$ABORT
CMD$SUSPEND
RCV"5USPEr~D

CMD$RESUr1E
RCV$RESUME
CSRES
CR
LF

as
SP
DEL
BEl.
TRUE
FALSE
TRUEW

1 i terally

'700H',

literally '701H',
liteT'ally '702H',
I i t.rall~

'0100H',

literally '0010H',
literally

literally
lite_rally
literally
literally
litera11u
literalI,:!
literally
literally
litel'ally
literally
liteTally

literally
lit.rall~

I i terall~
literally

'0400H',
'0040H',
'0300H',
'OO30H',
'0200H',
'0020H',
'0080H',

'ODH',
'OAH',
'08H',
'20H' ,
'07FH',
'07H',
'OFFH' ,
'OH',
'OFFFFH',

1* Address Declare *1
5
b

7
(I

?

declarE"
declare
dec lare
declare

5CP$OFFSET
ISCPSOFFSET
SCO$OFFSET

RXSOFF5ET
det:lare TXSQFFSET
NOP$OFFSET
IASSETUP$OFFSET
CONFSOFF5ET

16
17

declare
declare
dl?clarl?
declare
declare
dec lare
declare
declare

18

declare

19
20
21

22

declare
declare
declare
declare

23

declare r1SG$PTR

10
11
12
13
14
I~

MC~SETUP$OFFSET

TRANSMITSOFFSET
TDR$OFFSET
DUr1PSSTATSOFFSET
o IIlG$OFFSET
RFO$OFFSET
RBO$OFFSETTBD$OFFSET
DSS3UFFSOFFSET
EXSTRANSMITSOFFSET

t1SG$3UF
INT$PTR

\Alord data (OFFF6H),
data (OFFEOH),
data (OFFDOH),
data (OEOOOH),
data (OE800Hl>
data (OFF70H),
data (OFF76H),
data 
da,ta (OFIOOH),
data (OF400H),
wor~ data (OF500H),

WOT'd
tdDT'd
WDT'd
word
word
WOT'd
word
word
word
word
word
word
word
word
lIJord
WOT'd

based MSG$PTR

(~)

5-27

pointer,
byte,
pointer,

LAN COMPONENTS USER'S MANUAL

Table 5-6. Software Listings (Continued)
CSBUF
(160)
ASCIIS3UF
(2)

by te,
byte,

IfH$OUF

by te,
word,
word,
pointer.

NE:XHCMOSOFFSET
CURRENT$Ct10S0FFSET
Ct10'PTR
OAT bas.d CMO$PTR
ME:SSAGESWORO
MESSAGE.OYTE
MESSAGESSTATUS
Ct10HOP.STATUS

byte.
word.
byte.
byte.
byte,

Cr1D$TOP~OFFSET

24
25

UlOT'di

declare COMMON$BASE
declare SCB$BASE

selector

data (6000H),

word

data (6),

1* System Configuration Pointer *1
2b
27

declare SCP$PTR
declare sep

pointer.
structure

(SYSBUS
DUMMY

28

29

Illord.

ISeP.offset

dword.
word.

iscpSbase

word) at (6FFF6h);

1* Intermediate System Control Pointer *1
de~lare 15CPSPTR
pointer;

declare ISCP

structure

Jr- TRANSt'iIT COMr1AND *1

TX$Cf1D;

106
107
108
109
110

2
2
2

III

2
2
2
2

112
113
114
115
116
117
118

119

2

2

2
2
2

2

procedure;

TRANSMIT. STAT = 0,
TRANSMIT. eMD
OA004H,
TRANSMl T LINK$ADDRESS =OFFFFH;
TRANSMIT. GUF$DESCSPTR = TBD$OFFSET;
TRANSMIT.DEST$ADDRESS (0)
00;
1* TRANSMIT DESTINATION ADDRESS *1
TRANSM IT. DEST$ADDRESS (1) .... OAAHi
1* 6BYTES
... ,
TRANSMIT. DEST$AODRESS (2)
OOi
TRANSMIT.DEST.ADDRESS (3)
00;
TRANSMIT.DEST$ADDRESS (4)
OAH;
TRANSMIT.DEST$ADDRESS (5)
8EH;
TRANSMIT TYPESFIELD = 0;
SCB. CMD = CMD$START;

end TX$CND;

1* EXTRA TRANSMIT COMMAND *1
120
121
122
123
124

125
126
127
128
129
130
131
132
133
134
135
136

procedure;
declare I
do 1 = 0 to 9;

EX$TX$CMO:

2

2
3
3

3
3
3
3
3
3
3
3
3
3
2
2

byte;

EX$TRANSMIT( I) STAT = 0;
EX$TRANSMI T (I). CMD
OA004H;
EXHRANSMIT( I). LINK$ADDRESS = OFFFFH;
EX$TRANSMIT( I >. BD$PTR
TBD$OFFSET;
EXSTRANSMIT(I) DESTSADDRESS(O)
00;
EXSTRANSMIT(I>'DEST$ADDRESS(I)
OAAH;
EXHRANSI1IT( I >. DESHADDRESS(2)
00;
EXSTRANSMIT(I).DEST$ADDRESS(3)
00;
EXSTRANSI1IT (I). DESTSADDRESS( 4)
OAH;
EX$TRANSM]T(I>'DEST$ADDRESS(5)
BEH;
EX$TRANSMIT(I>. TYPE = I;

=

end;
SCB.CND

=

CMD$START;

end EX$TX$CMD;

5-31

LAN COMPONENTS USER'S MANUAL

Table5-S. Software Listings (Continued)
1* TIME DOMAIN REFLECTOMETER TEST COMMAND *1

TDR$CMD:

137
138
139
140
141
142

2
2
2
2

143

2

procedure;

TDR. STAT = 0;
TDR. CMD = OA005H;
TOR. LlNK$AOORESS = OFFFFH;
TOR. TIME = 0;
SCB.CMO
CMO$START;

=

2

end rOR$CMD;

1* DUMP STATUS COMMAND *1
144
145
146
147
148
149
I so

DUHP$STAT$CMO:

2
2
2

DUMP$STAT eMD

= O.
=

QAOQ6H;

=

DUMPSSTAT.LINKSADDRESS
OFFFFH;
DUMPSSTAT BUFSPTR
DSSBUFFsOFFSET;

2
2

2

procedure,

OUMPSSTAT.STAT

SGB.eMD

=

=

1* DUMP STATUS RESULT OFFSET *1

CMD$START,

end DUt1P$STAT$Ct1Di

)* Diagnose Command *1
DIAO$Cf1D:

151

152
153
154

2

ISS

2

156

2

procedure;

=

OIAG. STAT

2
2

=

DIAQ etiD

0,
OA007Hl

DIAG. L1NK$ADDRESS = OFFFFH;
SC.S, CMD
CMDSSTART;

=

end DIAG$Cr1Di

1* Receive Frame Descriptor set up *1
IrHT$RFD:

157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172

procedure.

dec lare I

word.

2
2
2
2
2

RFD (0), STAT = 0,
RFD (Q),L1NKMOORESS

2

dol

call setb(O,@RFDCO),STAT,352);

3
3
3
3

E?nd i
RFD
RFO
RFO
RFO

2
2
2
2

2

=

RFD$DFFSET + off.eUof((!RFD ( I ) ,

RFD (OLBD$PTR = RBDSOFFSET + offset$of(@RBOCO».

end

(15)'
(15)'
(15).
(15).

I),

STAT = 0;
L1NK$ADDRESS
OFFFFH,
eOSPTR = OFFFFHI
EL$S = BOOOH,

=

ItHT$RFDi

1* Receive

--->

=

1 to 14;
RFO (I>' STAT = 0;
RFD ( l l , L1NK$ADDRESS ~ 'RFO$OFFSET + oH.et$of((!RFO(I +
RFD (I), SD$PTR = OFFFFH;

Buffe~

Descriptor set up

: RBD

°

: NDD=RI3(O):

I

RBD(I)

I

EL

=

---> " " " ' "

---)

'RDD(IS)

0

: NBD=RD ( 1 ) I

I NDD= FFFFH I

',1
INIT$RBD:

173
174

2

175
176
177

2
3
3

procedure.

decldre I
do I

=

word;

0 TO 14;
RBD(I), ACT$CDUNT
0,
RBD( I), NEXT$BDSADO ~ RBD$OFFSET + off •• Uof(@RBO(I+I»,

5·32

LAN COMPONENTS USJ;:R'S MANUAL

Table 5·6. Software Listings (Continued)
178
179
IBO
181
182
183

3
3
2

RBDC II. SIZE -

80H,

end I
RBDClS). ACnCOUNT a 0,
R DO C15) . NEXTSBDSADD a OFFFFH,
RODC 151. SIZE a 80BOH,
end IN! TSRnD,

:1

2
2

1* Receive

Buffl~

[NIT$RB:

184

set up *1

procedureJ

185
186
187

2

declare I

2
2

declare VALUE
declare COUNT

188
189
190

2
2
2

VALUE = 0,
COUNT = BOOHI
call setbeVALUE,@RX,COUNT),

191
192
193
194

2
3
3
3

do I

195

2

end INITSRBi

blord.
byte;
word,

1* Full up receive buffer with OOh *1

0 TO 15.

=:I

RBDC II. BUFF.BASE - SCB.BASE,
RBDC!).BUFF$OFFSET a RX.OFFSET

+ off •• t.ofC@RXC!)),

end;

1* Transmit Buffer Descriptor wetup

1{ Setup actual caunt fot" Transmit Buffer Descriptor,
and one frame is transmitted by one TranBmit
command.

2) Setup nelt buffer descriptor address foT' each TaO
in order to lilik with next TDD.

-:-->

--->

I TBD CO)

---> ......... --->

I TOO C1)

I EL = 0

I TBD (15)
I EL = 1

I NOD-Tn CO) I

I NBD=TO(1) I

I NBD= FFFFH I

*1
196

INITSTBD:

pT"D~edul'e;

197

2

declare I

198
199
200
201
202
203

2

do I

:3
:3
:3
2
2

endi

204

2

=

word;

0 TO 14i

TBDCI). ACT$COUNT = BOH;
TBDCq.NEXTSBD$ADD = TBD$OFFSET + offset$Df(@tbdCi +
TBO(15LACT$COUNT = 80eOH;
TBO (15 L :'EXTSBD$ADD = OFFFFH,
end !NIT$TBD,

1* Transmit buffer set up
1.

2.

Set up TED
each TED has o~n transmit buffer
Set up b~te count of each buffer
-

BOh

b~tes

3. Set up buffer data
*1

INITSTE: procedure;

205

206

2

declare I
J

byte.

byte,

NEW$VALUE

b~te.

DEST$ADDR
BYT$CNT
TXB$PTR

pointer.
byte.

pointeY/;

207

2

208
209

3

do ! = 0 TO 15,
TBD(!).BUFF$BASE = SCB$BASE;
TnD(ILOUFF$OFFSET = TX$OFFSET + oHseUDf(@TXC!»);

210

3

end;

:3

5·33

1)),

LAN COMPONENTS USER'S MANUAL

Table 5-6. Software Ustings (Continued)

= OJ

2
2
3
3
3
3

NEW$VALUE = J,
DEST$ADDR = eTX CI ),
call setb(f-IEW$VALUE,DEST$ADDR,BYTSCNT'i

218

3
3

.J = .J + OlHi
end;

219

2

211

212
213

214
215
216

217

J

do I = 0 TO 15,
byt$c:nt = SOh'

1* set up buffer data fa',.
transmission
*1

end INIT$TB;

1* System 110 routine *1

1*

220

221

1
2

Co~sDle

eI:

input routine --- returns to the AL ,..gister an ASCII character
received from the console device.
The AX. ex.
and DX registers and the CPU condition codes
ar. affected by this operation
*1

p,..oc:edure byte extern .. l,
end eli

1* Console output routine

transfers ill character fram the lo~-o,.der byte
of the ~o"d on the top of the stack to the
console device.
The AX. ex, and DX regi&ters

and the CPU condition codes are affected by
this ope~ation.
*1
222
223
224

I

2
2

co:

procedure (CHARACTER)
declare CHARACTER·
end COJ

1* Exit routine

225

I

226

2

227
228
229
230

1
2
2
2

exte~nal;

byte,

causes a Jump to the iAPX 86. 88 monitor command level.
EXIT does not close any files.
*1

'·EXIT: p~ocedu~e external;
end EXIT,.
Retu~n

1* Canriage

CRSLF:

---- Paramete~

none *1

procedu~e;

call COCODH),
call COCOAH),
end

CR$LF,

1* Out string routine ---

transfe~s

st~ing

(Oh) found in the

to console device.
st~ing.

te~minates

Null code
the string

transf.~.

231
232
233

1
2
2

234
235
236
237
238
239
240

2
2
2
3
3
:3
3

241

2

OUTS:

pro'cedu~e;

declaT'e CHAR
declare I
I = 0,
CHAR

= OFFH,

do while CHAR
CHAR

<>

O.

= MSGSBUFCI),

call CO CCHAR),
I = I + 1,
end;
end OUTS,
1* Input string routine --- tT'ansfe~s st~ing from console device.

The input
code of carriage retu~n (CR. ODH) or line feed (L.F.
OAH) causes termination of 'I;il'is routine.
This T'outine supports rub~ut and back space also. *1

5·34

LAN COMPONENTS USER'S MANUAL

Table 5-6. Software listings (Continued)
242
243

244
245
246

247
248
249

1
2
2
2
2
3
3'

250

2
2

251

2

252

3
3
3
4
4
5
5
5
5
5
4
4
3
3

253
254
255
25 ..
257
258
259
2 .. 0
2 .. 1
262

263
264
265

2 ....
267

INS:

procedure.
declal'·e CHAR
declare I
CHAR = 10H,
do I = 0 to 159,
C~DUF ( ! ) = CHAR,
end;

I = 0,
CHAR = 10H,
do while «CHAR <> CR) and
CHAR
CI and 7FH,

=

4

4

end;

else if CHAR
then

end;

else

call COeBEL);

end;
end INS;

INSVES:

3
3
3

procedure

b~te;

declare CHAR
CHAR = 0,
do while «CHAR

2

and (CHAR

byte;

<> 'Y' Dr CHAR <> 'y')
<>' 'N' or CHAR <> 'n'»;

CHAR = CI and 7FH,
c<111 CO(CHAR),
if (CHAR ~ 'V' or CHAR = 'y') then
return TRUE;
else if (CHAR = 'N' or CHAR
'n') then
return FALSE;
else do;
t1SQ$PTR = (!(ODH,OAH,
KEV IN V or N', ODH. OAH, 2AH, 0)
call OUTS;
end.

3

3
3
3

'**

4
4
4
3
2

Soft~are

chip reset
Name:

Input:
Output:

Function:

CHIP$RESET
None

None
This routine performs 82586 chip reset
by software.
It is same as Hardware
RESET.

1
2
2
2

j

end;
end INSVESi
1*

297
298
299
300

LF»

CSBUF( I) = CR;
C$BUF(I + 1) = LF,
I = I + 2.

281

285
286
287
288
289
290
291
292
293
294
295
296

<= 'z'»

than do;

4

2
2

SP

end.
.1 •• if «CHAR = CR) or (CHAR

3
2

282
283
284

>=

do;'

call CO(CHAR);
U= «CHAR >= 'a') and (CHAR
then C$BUF( I)
CHAR - 20H,
.1.e CSBUF(I) = CHAR,
I = 1 + 1.

4
4

<:> 158».

else call COeBEL);
end;

4

3

(1

I = I - 1,
call CO(BS);
call CO(SP);
call CO(BS),

4
3
3

277
278
279
280

LF) and

then do;

4

276

<>

then do;
if I;' 0

4

208

(CHAR

if (char = del) or (CHAR = 25)

4

269
270
271
272
273
274
275

byte;
b"yto;

CH1PSRESET: proc ad Ul'eJ
SCD. CMD = BOH,
call CAi
end CHIPSRESET,

5-35

*1

LAN COMPONENTS USER'S MANUAL

Table 5-6. Software Ustlngs (Continued)
1* System Initialize *1
JNIT$SYS:

301
302
303

2
2

304
305
301>
307
308
309
310
311
312
313
314
315
3.11>
317
318
319
320

2

procedurel

call setbCO,erx,2000h)J

CMDSTOPSSTATUS = FALSE,
1* Painter Declare *1

SCPsPTR = buildspt~ICOMMON$DASE. SCPSOFFSET),
ISCPSPTR = build$pt~ICOMMONSDASE. ISCPSOFFSET),
SCBsPTR = buildSpt~ICOMMON$BASE. SCBsOFFSET),
NOPSPTR = build$pt~ICOMMON$BASE. NOPSOFFSET),
IASSETUPsPTR = build$pt~ICOMMONSBASE. IASSETUPSOFFSET),
CONFSPTR = buildspt~ICOr1MONSBASE. CONFSOFFSET),
.
r1CSSETUPSPTR = b u 11 dSp t~ I COMMON$BASE. MCSSETUP$OFFSET),
TRANSM I T$PTR = b u i I dSp tr I COMMONSBASE. TRANSrllTSOFFSET),
TOR$PTR = buildSptrICOMMONSBASE. TORSOFFSET),
OUMPSSTATSPTR a buildSpt~ICOMMONSDASE. DUMPSSTATSOFFSET),
DIAGSPTR = buildSpt~ICOMMONSBASE. OIAGSOFFSET),
RFDsPTR
buildSpt~ICOMMON$BASE. RFDSOFFSET),
RBO$PTR
build$pt~ICOMMON$BASE. RBDSOFFSET),
RXBSPTR =. buildSp·t~(COMMONSBASE. RXSOFFSET),
TBOSPTR = build$pt~(COMMONSBASE. TBDSOFFSET),
TXB$PTR = buildSpt~(COMMON$DASE. TXSOFFSET),
EXSTRANSMITSPTR = buildSpt~ICOMMON$BASE. EX$TRANSMIT$OFFSET),

:2

2
2

2
2
2

2
2
2

2
2
2
2
2

2
2
1*

3:11

2

sep initialization
SCP.SYSDUS

a

'*1

OH,

1*

S~st.m

bus width - II> bits. *1

3:22

:2

SCPo ISCPSBASE • 6caSSASE,

323

2

SCPo ISCPSOFFSET

1* ISCP etart ad dr ••• 24 -

324

2

ISCP. BUSY - OIH.

325
321>
327

2
2

ISCP.SCBSOFFSET - off •• tSo.ISCD.PTR).
1* SCD It.~t addr.ss of's.t *1
ISCP. SCBSBASEI - OH.
1* Lower wol-d of SCD. b... add res.. *1

= ISCPSOFFSET,

bits */

1* 1SCP initialization *1

1* Thll .. o~d. set b~ CPU to OIH.
82586 cl •• r. it.

2

lSCP.SCSSSASE2 - 06H,

1*

MS-b~t.

*1

of SeD b••• addr.ss. */.

1* SCD initalization *1
328
329
330

2
2
2

1* SCD STATUS word. it should be set to O. *1
6CD. STAT - OH,
SCD. CHO a OH.
1* sca Command ~Drd *1
SCD. CBL'OFFSET • CONFSOFFSET,
1* Command block list offset, the add~ess
of command block list is the summation
of SCD DASE and OFFSET valu.. *1

331
332
333
334
335
331>
337
338
339

340
341
342
343
344
345
341>

2

2
2
2
2

:2
2
:2
2
2
2
:2
2
:2
:2
2

SCB.RFDSOFFSET. off.et$of(RFD$PTR), (* Receiv. f~.m. a~.a off •• t *1
1* CRC E~~o~ counte~ *1
SCB.ALN'ERRS - 0,
1* Alignment error counte~ *1
SCD. RSC.ERRS • 0.,
1* No re.ource er'ror count.~ ct. of frames
"ere last b" no resouTce errors) *1
SCB.OVRN'ERRS a O.
1* DMA DVER-RUN e~T.r counter *1
c.l1 CA,
1* NOP command e.ef.' I.oItion *1
call CHIP'RESET.
1* Chip r.set *1
call ACK,
1* Actnowlidge fo~ Chip ~e5.t *1
call CQt,fF.CMD.
1* Set configuration command parameter *1
CONF. CHO = 0002H;
1* EL = 0, 5 • 0, I • 0, CMD = CONF *1
CONF.LINK'ADDRE66 - IA.SETUP'OFFSET. 1* IA .etup cmd fo~ next cmd block *1
call IA.SETUP.CHD,
1* IA setup cmd parameter .et *1
IA.SETUP.CMD • OA001H,
1* IA command set *1
NEXT'CHDSOFFSET = OFFFFH.
1* Next command offset for last cmd block *1
call CAi
1* Execute them *1

SCD.CRC'ERRS - O.

end INITtSYS,
1* Message for HELP command *1

COMMAND$MSG: procedure.

347
348
349

2

350
351

2
2

2

call CR.LF.
MSQ'PTR - II'NOP ------------------- NOP
INDIVIDUAL ADDR SETUP - IA '. ODH. OAH.
'CONFIGURATION -------- CONF
MULTICAST-ID ---------- MC '. ODH. OAH. 0).
call OUTS.
MSO'PTR - II'TRANSMI" -------------- TX
TDr ------------------- ,DR'. ODH. OAH.
'DUMP STATUS ----------- DS
DIAGNOSE -------------- DIAG'. ODH. OAH. 0),

5·36

LAN COMPONENTS USER'S MANUAL

Table 5-6. Software Listings (Continued)
call OUTS;

352

2

353

2

end COMMANO$MSGi

354
355

I

BD$MSG:

2

pT'ocedurei

t1SG$PTR =

'fiX FRAME DESCRIPTOR --- RFO',OOH.
'RX BUFFER DESCRIPTOR -- RBD

@(

OAH.

RX DUFFER -------------- RD',ODH/OAH,Q>,
356
357

2
2

358

2

call OUTS;
115G$PTR = @I 'TX BUFFER DESCRIPTOR --- THD
TX BUFFER --~----------- TB', ODH. OAH. 0),
end BD$MSG,

1* Message for illigal input *1

359
360
361
362

2
2

2

MSG!5ILL$CMD: procedure;
f1SQSPTR ::::I Q ( ,

<----

1* Integer to ASCII code

INT$TOSASCII:

2

365
366
367
368
369
370

2
2

2
2

2
2

371
372
373
374
375

2
2
2

376

2

OAH.

0),

conversi~n

INTHO$ASCII

Input:

INT$I3UF
Integer buffer (1 byte),;
ASCIIsnUF
ASCII buffer (2 bytes))
INTEGER TO ASCII conversion *1

Function:

363

OOH.

Name:
Output:

364

ILLEGAL INPUT',

call OUTSi
end 11SG$ILL$CMDI

procedure;
byte;

declare TEMP$CHAR

TEI1P$CHAR = INT$BUF,
TEMP.CHAR = TEMP$CHAR ond OFH,
if TEMP$CHAR < 10
then ASCII$OUF(O) = TEr1PSCHAR + 30HI
if 110 <= TEMP.CHAR) and ITEMP$CHAR
then ASCII$BUFIO) = TEMP$CHAR + 37H,

,I.,

<=

TEMP.CHAR = shr(IINHBUF and OFOH). 4),
< 10
then A6C I I .BUF I 1) = TEMP$CHAR + 30H,
else if (10 <= TEMPSCHAR) and (TEt1P$CHAR
then ASCII$BUFII) = TEMP$CHAR + 37H,

2

OFH)

if TEMP$CHAR

2

<"" OFH)

end INTSTO$ASCII,

1* ASCII code to integer value conversion
ASCIIHO$INT

Name:
Input:

ASCI IsBUF

Outp u t:

Function:

377
378

2

379
380
381

2

382

2
2

383
384
385

386
387
388
389
390

2
2

2
2
2
2

2
2
2

391

ASC I I $TO$It~T: proc ad ure;
declare TEMP$CHAR (2)

2

393
394

2
2

by te,

TEt1P$CHAR (0) = ASCII$BUFIO);
if ('0' (= TEt1P$CHARCO»
and (TEMP$CHAR(O) .(= '9')
th en
TEI1P$CHAR (0) = (TEMP$CHAR (0) - 30H),
else'if ('A' <= TEMP$CHAR(O»
and (TEMP$CHAR(O) <= 'F')
then
TEI1P$CHARIO) = TEMP$CHARIO) - 37H,
TEI1P$CHAR (1) = ASC I I$BUF (1),
i f 1'0' <= TEI1P$CHAR I 1)) ond ITEMP$CHAR I 1) <= '9')
th en
TEt1P$CHAR I 1) = TEMP$CHAR I 1) - 30H,
else if ('A' <= TEMP$CHAR(1» and (TEMPsCHAR(l) <= 'F'>
then
TEMP$CHARII) = TEMP$CHARII) - 37H,
INHBUF = ITEMP$CHARIO) and OFH) or shl«TEt1P$CHARI1) and OFH).

end ASCII$TO$INTi
DEC$TO$HEX:

392

(2 bytes)

INT$BUF
II byte)
ASCII to INTEGER conversion *1

procedure(NUMBER) word;

declare NUMBER
decl.are TEMP$WOROO
declare TEMP$WORDl

word;
word.

word;

5-37

4),

LAN COMPONENTS USER'S MANUAL

Table 5-6. Software Listings (Continued)
395

396
397
398
399

400
401·

:;:
2
2
2
2
2
2

402

2

403
404

2
2

405

TEMP$WORDO

shr( (NUMBER and OFOOOH)' 12);

TEMP$WORDI

TEI1P$WORDO

TEMP$1-10RDO

shr(CNUMBER and OFOOH),8);

INPUT$WORD:

IN$l~ORD

dec: 1are

2

declare I

408

2

call INS.

409
410
411
412
413
414
415
416
417
418

2
2
3

*

100);

*

10),

word;
byte;

I, IN$WORD = 0,
do while (I < 4 and C$BUF(I)
ASCII$BUF(O) = C$BUF(I),
ASCII$BUF(1) = 0,
call ASCIIHO$INT,

3
3
3
3
3
2
2

1000,

procedure word.

2

406
407

*

TEr1p$~":ORDl + (TEMP$WORDO
TEt1P$WORDl
TEI1P$WORDO
shr«NUMBER and OFOH),4);
TEt1P$WDRDl
TEMP$~jORDI + 

shl(It>J$WORD,4)

<>

CR and C$BUF(I)

LF)j

or double(INT$BUF);

I = I + I.
end.
return IN$WORDi
end INPUT$t.JORDj

1* Read 1 byte data from Memory
Name:

Input:

Output:
Func t i on:

419
420

1
2

t1EM$BYTE$READ:

MEM$BYTE$READ
CMD$OFFSET

MSQSBUF (console out)
Output one byte data stored in memory to
console
*1

procedure (Ct1D$OFFSET);

declare
CMD$DAT ba.ed CMD$PTR
COUNT
CMD$OFFSET

421
422
423
424
425

Ct1D.PTR = b ui 1 d$p tr (COMMON$BASE, CI1D$OFFSETl,
OAT = CMD$DAT,
INT$BVF = CMD$DAT,
call INTsTOSASCIIl
call CO(ASeI I$BUF( 1»;
call CO(ASCII$BUF KEY IN THE BUFFER DESCRIPTOR NUMBER
)IIODHI OAH,2AH,O);

call OUTS.
call INS;
call CRSLFi
ASCII$BUF(O) = C$BUF(O),
ASCII$BUF(l) = 0;

call ASCIlSTOSINT;
if INT$BUF <= 15 then do;

TEI1P$CMD$OFFSET = RX$OFFSET
do 1 = 0 to 7.
INT$BUF = I,
call INTSTOSASCIII
call CO(C$BUF(Q»,
call CO( ': I)J

5-38

+(

INT$BUF

*

80h),

(0 -

F:

128 byte unit

.LAN COMPONENTS USER'S MANUAL

Table 5-6. Software Listings (Continued)
<140
449
450
451
452
453
454
455
456
457
45B
459
460
461
462
463
464
465
466
46B

4
4

call COCASCII$OUFCOl ,.
call CO('O'),

""5
5

call CO(SP)J
do .J =:I 0 to lSI
call MEMtDVTE.READ(TEMP.CMD.OFFSETl,
call COCSPl,
TEI1P.CMD.OFFSET - TEMP'Cli11.0FFSET + I.

5

end,

5
4

call CR.LF.
endl

"2

end,
else dOl
call MSG'ILLSCMD,

3

3

t1SQSPTR

3

3
3

2
2
2
2

1* DUI1P STATUS

469
470

2

471

2

47~!

2
2
3
3
3.
3
3
3
3

473
474
475
476
477
47B
479
4BO
4BI
4B2
4B3
4B4
4B5
4B6
4B7

I

4
4
4

4
3
3
2

= @(ODH,OAH,

'RXB> KEY IN 0 --- FCH)

!!! I, ODH, OAH, 2AH, 0),

goto LOOPB.
end,
115G'PTR m (i!(ODH.OAH. 'RXB> MORE RXB ? CV or Nl '.ODH.OAH.O!AH.Ol.
call OUTS.
if IN'VE5 then goto LOOP7.
end BUFFER.OI5P,

status d isp la~

DS$BUFF$OISP:

Name:

D5$DUFF.OISP

Input:

C$BUF (console in)

Output:

MSG.DUF (console out)

Function:

DisplalJ DUMP STATUS contents to Console *1

procedul'e,

dec lare TEI1PSCMDSOFF5ET
I
.J
call CRSLF.
TEI1PSCMDSOFFSET = 05.DUFF$OFFSET!
do I = 0 to 10,
IIHSDUF = I.
call INTSTO$ASCII,
call COCASClI$DUFCI) "
call COCA5ClISBUF(Ol "
call COC'O'),
call COC5Pl,
do J :a 0 to 151
call MEMSDVTE.REAO(TEMPSCMOSOFF5ETl,
call CO(SPl,
TEMP'CMO'OFF5ET = TEMP.CMO$OFF5ET + 1.
end,
call CR.LF,
end,
end OS.BUFF.OISP.

1* Transmit data change
t·Jame:

TR AN5111 T$DATASCHANGE

Input:

C$BUF (console in)
Transmi t buffeT'
Determine the tr~n.mit buffer size
(128 bytes unit) and data *1

Output:

Function:

4BB

I

'\89

2
2
2
2

41';"0

491
4q2

493
494

2

495

2

496
497
49B
499

2

2

procedureJ
byteJ
blJte,

TRAN5MITSOATA$CHANGE:

declare I
declare BYTESDATA

declare BUFFERSNUMDER
declare BUFFER'POINTER
declare C$COUNT

declare TEMP
LOOP:

115GtPTR

=

byte,

pointeri
words
lItordJ

(i!(ODH.OAH. 'TXB> DO YOU UANT TO CHANGE THE TRANSMIT DATA?

(Y aT' N)',ODH,OAH.2AH,O)J

O!
2

3

call OUTSi
i f INSVES then
do,
115G$PTR = (!(ODH.OAH. 'TXB> DATA CHANGE:
(0 -

500
501
502

503
504
505
506
507
SOB
509

3
:3
:3
:3

3
:3

3
3
:3

3

F:

l:!:S bgtes unit)/,

KEV IN THE BUFFER NUMDER

ODH,OAH,2AH,O);

call OUTS.
INTSBUF • LOW( INPUT'WOROl,
BUFFER.NUMBER - INl$DUF and OFH,
BUFFER'POINTER - CilTX (BUFFERSNUI1DER ,.
M5G$PTR
IUODH.OAH, 'TXD> KEV IN THE VALUE (00 - FFl '. ODH. OAH. 2AH. Ol,
call OUTS;
INTSBUF = 10.,( II~PUT$WOROl'
call setb (IIHSBUF. BUFFER$POINTER. BOHl,
M5G$PTR = (i!COOH.OAH. 'TXB> DATA WAS WRITTEN', OOH. OAH. Ol.
call OUTS,

=

5-39

LAN COMPONENTS USER'S MANUAL

Table 5-6. Software Listings (Continued)
call CR$LFi
gato LOOP,

510
511
512
513
514

3
3
3
2
3

51S
516

3
3

517
51S
519
520
521
522
523
524
525
526
527
52S
529
530
531

3
3
3
3
3

4

call CR$L.FI

4

MSG$PTR

532
533
534

4
4
3

535

2

end;

else

dOl

t1SGSPTR = Ii!( ODH. OAH. 'TXB> HOW MANV BVTE (S) DO YOU NEED ?'.

0).
call OUTS.
KEV IN THE DECIMAL NUMBER'
I1SGSPTR = @IODH.OAH. '
, ODH, OAH, 2AH, 0) I
call OUTS.
TEMP ICI INPUTSWORD.
CSCOUNT
DECSTOSHEXITEMP).
I
0,
do while ICSCOUNT > SOH and CSCOUNT  204B th.n
do.

:3

~al1

= @('TXB>

endl.

end,
end TRANSI1ITSDATASCHANGE.
/* Di6.play

command ... ord contents

Output:

DISPSCONTENTS
CSBUF (console in)
MSG$BUF (console .out)

Function:

Display the command worJl. cpntents t.o console *1

Name:

Input:

536

DISPSCONTENTS:

537
538
539

2

540

2

541
542

2
2

543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
S68
569
570
571
572
573
574
575
576
577
578
579

2
2

word,

de.:;la,.. J

byte,

if

do;

5
5
5
5
5
5
5
4
5
5
5
5
5
5
5
5
5
5
5
5
5
5

blltei

t1SGSPTR = @IODH.OAH. 'CSEr> DO YOU WANT TO SEE .THE CONTENTS? IV or N)',ODH.
OAH. 2AH. 0),
ca 11 OUTS,
DISPSOFFSET = MESSAGESWORD.

2

5

procedure,

declare DISPSOFFSET
declare BVTESCOUNT

2
3
3
4
4
4
5
5
5
5
5
5
5

BYTE COUNT IS LIMITED UP TO 204B'.ODH.
OAH,O),

OUTS,

IN$YES then

.J = I MESSAGESBVTE - 2112.
do BVTESCOUNT = 0 to .J.
call CRSLF.
iF MESSAGESSTATUS = TRUE then
do.
MESSAGESSTATUS = FALSE.
MSGSPTR = C!('WORD '.0),
call OUTS,
mrsBuF = BVTESCOUNT.
call INUTOSASCII.
call COIASCIISBUFIO)),
call COISP).
call CO( "=');
call COISP).
DISPSOFFSET = MESSAGESWORD + I,
~ a 11 t1Et1SBVTESREAD CDI SPSOFFSET) ,
DISPSOFFSET = DISPSOFFSET - 11
call MEMSBVTESREADIDISPSOFFSET).

call CO( 'H'),
end;

else

dOl

MSQ_PTR = .('WORD ',0);
call OUTS,
INTSBUF a BVTESCOUNT.
call I NTHOSASC I I I
call COIASCIISBUFIO)).
call COISP).

call CO('-='),
call CO(SP),

=

DISPSOFFSET
DISP$OFFSET + 3.
call MEMSBYTE$READ I DISPSOFFSET).
DISPSOFFSET = DISPSOFFSET - i.
ca 11 I1EMSBVTESREAD I DI SPSOFFSET) ,

call CO(-'H')i
end;

5-40

LAN COMPONENTS USER'S MANUAL

Table 5·6. Software Listings (Continued)
590

end;

4

581

3

582

2

end.
end DISP$CONTENTS;

1* SCB STATUS,

ACK field

display

SCB$BITMAP$DISPLAY
SCB.STAT.SCB.CMD
MSGsDUF (console out)
Display the SeB STATUS. ACK field

Name:

Input:
Output:

Function:

v~lue

to console as binaly

SCBSBITMAP$DISPLAY:

*1

procedure;

583
584

2

declare I

by tei

585

2

586
588
589

3
3
3

do I = 0 to 3;
i.r rol(MESSAGEsWORD. I + 1)

then call CO(31H);

590

2

else call CO(30H)i
end;

end SCI3$[HTI1AP$DISPLAYi

1* SCD COt1r1AND/STATUS field display

Output:

SCB$UNIT$DISPLAY
SCB.STAT.SCB.CMD
MSG$BUF (console out)

Function:

Display the CUS, RUS.

Name:

Input:

cue

and

RUe

field

to console as BCD value *1
SCB'$UNITsDISPLAY:

procedure;

591
592

2

declare SHIFTsCOUNT

593
595
596
597
598
599

2
2
2
2
2
2

i f I1ESSAGE$STATUS

600

2

by tel

=

0 th en SHIFT$COUNT
else SHIFT$COUNT = 4;
Ir~T$BUF

=

=

8;

low (shr (MESSAGE$WORD, SHIFT$COUNT) and 7);

cdll INTSTO$ASCII;
call CO(ASCII$BUF(l»;
call CO(ASCII$BUF(O»i

end SCB$UNIT$DISPLAYi

1* Word contents display

WORD$DISP
MESSAGE$WORD
MSG$BUF (console out)
display the word value *1

Name:

Input:
Output:

Function:
601
602

WDRD$DISP:
2

603
604
605
606
607
608
609
610

2

611

2

procedure;
byte;

declare 1

I tH$I3UF = hi 9 h (t1ESSAGESWORD);

"2"

call INT$TO$ASCIl;

2

call INT$TO$ASCII;

call COCASCII$DUF(l»;
call CO(ASCII$BUFCO»,
ItHSBUF = low (MESSAGE$WORD) I

""
"

call eQCASeI !$DUFC 1»;

call CO(ASCII$BUF(O»;
end WDRO$DISP;

I*change the link command condition
Name:

Input:
Output:
Function:

CHANGE:

612

613
614
615
616
617
618

"
""
2

2
2

CHANGE
C$BUF (console in)

Command blocks
Change the command
parameter change

procedure;

declare
declare
declare
declare
declare
declare

CHANGE$DATA$BYTE
CHANGE$PTR
CHANGE$OFFSET
DYTESCOUNT

word,
pointer;
wordl

J

byte;
word;

byte;

TMPsWORD

5-41

linking and command block
~/

LAN COMPONENTS USER'S MANUAL

Table 5·6. Software Listings (Continued)
619
620

621
622

623
624
625

626
627
628
62 DO YOU NEED CHANGE THIS BLOCK? IY or NI',ODH,OAH,2AH,01.
call OUTS.
if

WSYES then
do;

MESSAGESWORD.
MESSAGE.STATUS = FALSE.
do BYTE. COUNT = 0 to IMESSAGESBYTE - 2) by 2.
CHANGE.PTR
bulldSptrICOMMONSBASE,CHANGESOFFSET),
call CRSLF.

CHAt~GESOFFSET

4
4

D

D

MSOSPTR = @( 'WORD ' ,

4
4
4
4
4
4
4
4
4
4

0)1

l:ill1 OUTSJ

INT.BUF = BYTE.COUNT I 2.
call INTSTO$ASCII.
call COIASCIISBUFIO».
call COISP).
call CO('=')J

4

call COISPI.
c a II mov," I CHANGESPTR, @MESSAGESWORD, 1).
call WORDSDISP.
MSQSPTR D &120H, '<--- DO YOU NEED CHANGE THIS WORD?
(Y Dr N)',ODH.OAH,2AH.O),

641
642
643
644
645
646
647
648
649
650
651
652
653

4

call OUTS.

4

i of IN.YES th en

4
5

do.

MSGSPTR
(!(ODH,OAH, 'CSET> WHAT IS THE VALUE?
ODH, OAH, :2AH, 0) ,
call OUTS.
CHANGESDATA.BYTE = INPUTSI~ORD.
D

5
5

call setw(CHANQE$DATASSVTE, CHANGC;$PTR. 1) i

5

5

end;

4

CHANGESOFFSET = CHANGE.OFFSET + 2.

4
3
2
2'

(FOUR DIGITI',

end;
end;

t1ESSAGE$WORD = TMPSWORD.
end CHANGE,
1* Command set

LINKSADDRESSSSET
CURRENTSCMDSOFFSET, NEXTSCMDSOFFSET
CURRENTSCMDSOFFSET, NEXTSCMDSOFFSET

Name:

Input:
Output:

'Function:

654
655
656
657
658
660
661

Set the command link (Max. 2 commands)
this T'outine sets tha following parameter;
a: link address set
~: EL bit of previous command is reset
c: EL bit of next command is set *1

LINKSADDRE!;S$SET: procedure,
2
:2

d.cla~.

TEMPSWORD based TEMPSPTR

2

~.cla,.e

TEMPSOFFSET

2

if CMDSTOPSSTATUS = FALSE then do,
Ct1D$TOPSOFFSET = NEXTSCMDSOFFSET,
CMD$TOPSSTATUS
TRUE,

:3

decla1"e TEMPSPTR

pointer;
word;
wordl

663

3
3
:2

else do;

664
665
666

3
3
3

TEMPSOFFSET = CURRENTSCMDSOFFSET + 4,
TEMPSPTR = bulld$ptrICOMMON'BA5E, TEMPSOFFSET).
TEt1PSWORD = NEXTSCMDSOFFSET.

667
668

3
:3

61.9

3

TEt1P$OFFSET = CURRENTSCMOSOFFSET +2.
TEt1PSPTR = bulldSptrICOMMONSBASE, TEMPSOFFSETl,
TEt1PSI MORE TRANSMIT COMMAND? (V
ODH, OAH, 2AH, 0),
call OUTS,
MESSAGE$WORD = OF500H + 16 * Ii
CURRENHCr1DSOFFSET
NEXT$CMO$OFFSET,
::I
MESSAGESWORO,

=

call LINK .. ADDRESSSSET;'
call CHANGEI
MESSAGE$STATUS = TRUE,
call DISP$CONTENTS,
I = I + I.
gato LOQP61

4
4
4
4

end;
else do;
call CR$LF.
INT$BUF = I + 1i
call I NT$ TQSASe I I ,
call CO(ASCIISDUF(Q)),
MSG$PTR
@(' TRANSMIT COMMAND WERE SET',ODH,OAH,Q),
call OUTS,
end;

4

3
4
4
4
4

=

4
4

3

end)

2

else dOl
EX$TRANSMIT(9).CMO
OA004H,
EX$TRANSMIT(9L LlNMADDRESS = OFFFFH,
EXSTRANSMIT(9L DD$PTR = OFIOOH,

=

MSG$PTR = @(ODH,OAH
I

3
3
2

N)',

NEXTSCf10$OFFSET

4

3
3
3
3

or

if IN$VES then dOl

4
4
4
4

I

714
715
716

proc ed ure,

dec lare I

'TRANSMIT COMMAND LINKS ARE LIMITED UP TO 10 !!!

I

DOH. OAH. 0);

call OUTS;
end i
end TRANSMITSCDMMAND$LINKI

1* Command link check
Input:
Output:

COMMANDSLINK$CHECK
MESSAGE$WORD
L1NK$ADDR

Function:

Check

Name:

the command

link and pass the

comm~nd

link condition to command set routine *1
717
718

p T' 0 C e d Ul' e;
declare TEMP$CMD$OFFSET

cor111AI-.tD$L It~v..$CHECK:

"

TEt1P$CMD$l.JORD

word,
tlJord;

719

2

720
721
722

2

if NEXT$CMD$OFFSET = r1ESSAGE$l..JORD then

2
3

do;

723

3

724
725
726

3

if

3

do;

727
728

4
4

729
730
731

4
3

TEr1P$Cr1D$WORD = MESSAGESWORD,

r1SG$PTR = @.(ODH, DAH. 'CSET:> DO YOU WANT TO EXECUTE THE SAME COMMAND ?

ODH, OAH, 2AH, D),

732
733
734
735
736
737
738
739
740

call OUTS;
It~$YES

end;

else do;
r1SG$PTR = @(ODH,OAH, 'CSEr:> CDriMAND LINK INPUT WAS CANCELLED',
ODH, OAH, 0);
call OUTS;

4

4
4

3
2
3
3
3

then

call LINK$ADDRESS$SET;
CURRENT$Cr10$OFFSET = NEXT$CMD$OFFSET,
NEXHCMD$OFFSET = MESSAGE$WORO,

4

end;
end.

else do;
CURRENT$Cr1D$OFFSET = NEXT$Cr1D$OFFSET,
NEXTSCr1D$OFFSET = MESSAGE$WORO,
call LINK$ADDRESS$SET.

3

end.

2

f1ESSAGE$l.JORD =

TEMP$CMD$WORDi

5-43

(Y or N)

I.

LAN COMPONENTS USER'S MANUAL

Table 5·6. Software listings (Continued)
741

2

742

end COMMANDSLINK$CHECK,

MORE$COMMAND:

743

2

744
745

2
2

pro-cedurei

t1SG$PTR = @ DO YOU WANT MORE COMMAND ?
 WHAT IS THE COMMAND?',ODH,OAH, 'KEY IN H FOR HELP',
ODH, OAH, :2AH, 0),
call OUTS,

call INS;
i f (cmpb (I!C$BUF(O), 1t<'NOP',ODH),
then do;
MESSAGE.STATUS • TRUE,
MESSAGE$WORD • NOP.OFFSET,
MESSAGE$BYTE • 6,
call NOP$CMD,
call COMMAND$LINK.CHECK,
call DISPSCOt4TENTS,
call MORE$COMMAND,
i f IN$YES then goto LOOPl,

.. I.e dOl
i f (cmpb (I!C$BUF(O)' i!('IA',ODH), 3)
then dOl
MESSAOE$STATUS • TRUE,
MESSAGE$WORD • IA$SETUP$OFFSET,
MESSAGE$BYTE • 12,
call IA.SETUP.CMD,
call COMMANDSLINK$CHECK,
call CHANGE,
MESSAGE. STATUS ~ TRUE,
call DI5PSCONTENTS,
call MORESCOMMAND,
i f INSYES thon goto LOOPl,
endi
eo1,. dOl
If (cmpb (G!C$BUF(O)'
then dOl

I!( 'CONF'.ODH),

ME6crAO~.STArUS ~ TRUEJ

5

MESSAGES WORD • CONFSOFFSET,
MESSAGESBYTE - 18.
call CONFSCMD,
ca 11 COMt1AND$LINKSCHECK,
call CHANGE,
MESSAGE.STATUS • TRUE,
call DISPSCONTENTS,
call MORESCOMMAND,
if IN.VES th_n gate LOOPl;

5

6
6
6
I>
I>

6
I>

else

TRUEW)

5) = TRUEW)

dOl

if (cmpb (@C'DUFCO), @('MC',ODH), 3) • TRUEW>
then dOl
MESSAGESSTATUS • TRUE,
MESSAOESWORD - MCSSETUPSOFFSET,
MESSAGESBYTE • 14,
call MC.SETUPSCMD,
c.ll COMMANDSLINKSCHECK,
call CHANGE,
MESSAGESSTATUS • TRUE,

6
6
6
I>

=

endl

5
5
5

TRUEW)

end,

5

4

4)

call DISP$CONTENTS;
ca 11 MORE$COt1t1AND,
if IN$YES then goto LOOP1;

end;

5-44

LAN COMPONENTS USER'S MANUAL

Table 5-6. Software listings (Continued)
809
810
811
812
813
814
815
816
817
818
819
821

5
6
6
7
7
7
7
7'
7
7
7
7

else

822

.. lse do.
if (cmpb
then do.

826
827
828
829
830
831
832
833
834
836

6
7
7
B
B
8
B
B
8
8
8
8
B
B

837
83B
839
840
B41
842
843
844
B45
846
847
84B
B49
851

7
8
8
9
9
9
9
9
9
9
9
9
9
9

else do.
i f (cmpb «!CSBUF(o),
then do;

8S2
853
854
8SS
856
8S7
85B
859
860

8
9

else do;
if (cmpb (@CSBUFCO),
then do;

823
824
825

Sol

862
863
864
866
867
86B
869
870
871
872
873
874
875
876
877

878
879
880
881
B8~

8B3
894
B8S
BB6
B87

<;I

11

11

II
II
II

TRUEW)

MESSAGE.STATUS • TRUE,
MESSAGE.WORD • TRANSMIT.OFFSET,
MESSAGESBYTE = 16,
call TXSCMD,
call EX.TXSCMD,
call TRANSMITSCOMMAND$LINK,
call MORE.COMMAND,
i f INSYES then goto LOOPI,
endl

«!CSBUFCO),

4)

@.('TDR',ODHb

=

TRUEW)

MESSAGES STATUS = TRUE,
MESSAGESWORD = TDRSOFFSET,
I1ESSAGE$BYTE = 8,
call TDR.CMD,
call COMMAND$LINK.CHECK,
call CHANGE,
MESSAGE.STATUS = TRUE,
call DISPSCONTENTS,
call MDRE$COMMAND,
if INSYES then goto L.OOP1,

end,

(!(

'OS', ODH),

3)

TRUEW)

=

MESSAGE.STATUS
TRUE,
MESSAGEiliWORD = DUMPSSTATSOFFSET,
MESSAGESBYTE = 8,
call DUMPSSTATSCMD,
call COMMAND$LINK.CHECK,
call CHANGE,
MESSAGESSTATUS = TRUE,
call DISPSCOIHENTS,
call MORESCOMMAND,
i f Itl$YES then goto LOOPI,
end;

@('DIAG',ODH),

5) = TRUEW)

MESSAGESSTATUS = TRUE,
MESSAGE.WORD = DIAGSOFFSET,
MESSAGESBYTE = 6,
call DIAG.Cr1D,
call COMMANOSLINKSCHECK,
call CHANGE,
MESSAGE.STATUS = TRUE,
call DISPSCONTENTS,
call t10RESCOMMAND,
if INSYES then goto LOOPI,

endl
e1ge dOl
if (cmpb «(!C$BUFCO), ec 'H'. ODH),
then dOl
ca 11 COMI1ANDSMSG,
call CRSLF,

2)

TRUEW)

goto LOOP1,

11

11
10
11

=

if (cmpb (@C$OUFCO), C!('TX'.ODH), 3)
then do;

10
10
10
10
10
10
10
10
10
10
10
9
10
10

dOl

end;

else

dOl

if (cmpb(@CSBUFCO),@('EXIT',ODH),S) = TRUEW)
tt1en call EXIT.
el.e
call 11SQSILLSCMD,

10

endJ

<;I

endJ

8
7
6
5
4

end;

3
2

endi
end COMMAND.SET,

end;
end;
endJ
end;

5-45

LAN COMPONENTS USER'S MANUAL

T~ble

5-6. Software Listings (Continued)

1* SCP,lSCP contents display *1

888
899
990

CPSDISPLAY:

2
:1

891
892
893
894
89:;
996
897
B98
899
900
901
902

2

903
904
905
906
907
908
909
910
911
912
913
914

:2

2
2
;>

2

2
2
2

2
2

2
2

t1SQ$PTR

pl'ocedul'e;

= e(

*** sep ***

I

:2

916
917
918
919
920

2
2
2
2
2
2
2
2

921

2

91S

MSO'PTR = e('
call OUTS,
t1ESSAGESWORD =
call WORD.DISP,
t1SGSPTR
(!(.
call OUTS,
MESSAGE.WORD call WORDSDISP,
MSGSPTR a (!(.
call OUTS,
t1ESSAGESWORD =
call LIORDSDISP,
MSa.PTR = @e /
call OUTS,
MESSAGE'WORD a
call I"ORD'DISP;
MSO.PTR ~ @('
call OUTS,

=

***

ISCP ***',ODH,OAH,O),

ISCP. DUSY,
ISCP BUSY'. ODH. OAH.

SCD OFFSET·.ODH.OAH.O),
ISCP. SCDSBASEI,

SCD BASE L',ODH,OAH,O),'
ISCP.SCDSDASE02,

SCD BASE H', ODH,OAH, 0),

end CPSDISPLAY,

sea information display

Function:

925
926

927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956

scaSSTATUSSDISPLAY:

2
2

2
2

2
2
2
2
2
2
2

2
2
2
2
2
2
2

2
2
2

2
2
2
2
2
2
2

2
2
2
2
2
2

or,

ISCP. SCD'OFFSET,

Name:
Input:
Output:

923
924

J

call OUTS;

1* All of

q22

ODH, OAH, 0)

t1ESSAGESL/ORD = SCPo SYSBUS,
call WORDSDISP,
t1SGSPTR = (!('
SCP SYSDUS·. ODH. OAH. 0),·
call OUTS,
t1ESSAGE$LIORD a SCPo ISepSOFFSET,
call LIORDSDISP,
MSG'PTR = (!(.
ISCP OFFSET·.ODH.OAH.O),
call OUTS.
t'oESSAGE$WORD a SCPo ISCP'DA8E,
cai 1 '''OROSOISP;
t1SQ'PTR :2 @('
ISCP BASE', OOH, OAH, 0),

1* ISCP *1
2
2
·2
2
2
2
2
2

I,

call OUTS,
1* SCP *1

SCDSSTATUSSDISPLAY
SCD

MSO.aUF (console out)

Pass contents of sea information to
SCD' content's' display ,.outine

proCedU1'.i

fiSGSPTR = @('
*** SCD ,***', OOH. OAH, 0) J
call OUTS,
t1ESSAGESWORD = SCD. STAT;
ca II SCDSB ITMAP$DISPLAY,
MSCSPTR = @('9 STATUS', ODH, OAH, 0),
call OUTS;
MESSAGESLlORD = SCB. CMD,
call SCDSDITMAP.DISPLAY,
MSG$PTR a @('B
ACK',ODH,OAH,O)J
call OUTS,
t1ESSAGESWORD
SCD. STAT'
t1ESSAGESSTATUS = 0,
call SCB$UtUTSDISPLAY,
fiSQ$PTR = @('H
CUS',ODH.OAH,O)J
call OUTS,
t1ESSAGESWORD = SCD. STAT,
MESSAGE$STATUS = 1,
call SCB$UNIT$DISPLAY,
tiSQSPTR == @('H
RUS', ODH, OAH, 0),
call OUTS,
MESSAGESL~ORD = SCO. CtiD,
MESSAGESSTATUS = 0,
call SCD.UNIT$DISPLAY,
fiSGSPTR = @('H
cue', ODH, DAH, 0);
call OUTS,
t1ESSAQESWORD a SCD. CMD,
t1ESSAGESSTATUS - I,
call SCD$UNITSDISPLAY,
fiS0.PTR = @('H
RUC',ODH,OAH,O),
call OUTS,
MESSAGESWORD = SCD.COL.OFFSET.
cdl WORD$DISP,
MSGSPTR - (!('H COL OFFSET'. ODH. OAH. 0),
call OUTS,

=

5-46

*1

LAN COMPONENTS USER'S MANUAL

Table 5-6. Software Listings (Continued)
957
958
959
960
961
962
963
964
965
906
967
968
969
970
971
972
973
974
975
976
977

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

'1ESSAGE$I,ORD = SCD. RFD$OFFSET,
call ImRD$DISP,
r1SGSPTR = @:( 'H
RFD OFFSET'. OOH. OAH, 0>.-

call OUTS;
t1ESSAGCi:$IJORD = SCD. CRCSERRS,

call ·UORD!5DISP;
r'iSQSPTR = @('H CRe ERRORS'. OcH, OAH. 0);
call OUTS;
I1ESSAGESIJORD = SCD. ALNSERRS,

call lmROSDISPi
= @.('H ALIGNt1ENT ERRORS', OcH. OAH, 0);
call OUTS;
t1ESSAGEtl-!ORD = SCD. RSCSERRSi
call lmRD$DISP;
11SG.PTR = @C 'H NO RESORCE ERRORS', ODH, OAH, 0),
call OUTS.
11ESSAGE'''ORD = SCD. OVRNSERRS,
t'iSG$PTR

c<>11 "ORDSDrsP,
t1SG$PTR = @('H OVERRUN ERRORS', 0),
call OUTS;
end SCB$STATUSSDISPLAV,

1* Action commands status display
Name:
Input:
Output:
Function:

ACTI ONSC MD$ST ATUSSD I SP LAY

Action commands status word
I1ESSAGEsWORD

Pass the action command status display
parameter to WORD$DISPLAY routine.
This command performs all tha action command

status display at once.
978

ACTION$Ct1D$STATUSSDISPLAV:

979

2

declare

980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001

2
2
2
2
2
2
2
2
2
2
2
2

call CRsLF,

1002
1003
1004
1005
1006
1007
1008
1009
1010

lOll
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
102B

2

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

procedure;

byte;

t1SG$PTR =

«(

I

t.JOP ------------

' , 0);

call OUTS,
NOP. STAT,
t1ESSAGESWORD
call I,ORD$D I SP,
call CDC 'W),
call CR$LF,
t1SGSPTR
@C'IA SETUP ------- ',0),
call OUTS,
t'oESSAGE$WORD
IASSETUP. STAT,
call WORDSDISP,
call CDC 'W),
call CRSLF,
,0),
(!C 'CONFIGURATION
t15GSPTR
call aUTS;
t1ESSAGESWORD
CONF. STAT,
call IIORD$D I SP,
call CDC 'H');
call CRSLF,
t1SGSPTR
Q C't1C SETUP ------- ',0),
call OUTS,
'"ESSAOESI,ORD a MC$SETUP. STAT,
call IJORDSDISP,
call CO( 'H');
call CRSLF,
',0),
I1SQSPTR
@( 'TRANSMIT
c~ll OUTS,
I1ESSAGESWORD a TRANSMIT. STAT,
call "ORD'DISP,
call CDC 'H'),
call CRSLF,
MSO'PTR = @('TDR
" 0).
call OUTS,
MESSAGESI.ORD a TDR. STATI
call "ORDSDISP,

=

=

=

--

=

=

=

=

------------

coe 'H'),

2

call

2

call CRSLF,
MSOSPTR a .('DUMP STATUS ---- ',0).
call OUTS,
MESSAGESWORD - DUMPSSTAT.STAT,
call IlORDSDISP,
call CDC 'H'),
call CRSLF,
',0)1
MSOSPTR
@('DIAGNOSE
,.all OUTS,
I1ESSAGESWORD = DIAG. STAT,
call WORD.DISP,
call COC'H')J
call CRSLF,

2
2

2
2
2
2
2
2

2

2
2
2

=

5-47

*/

LAN COMPONENTS USER'S MANUAL

Table 5-6. Software Listings (Continued)
1029
1030
1031
1032
1033
1034
1035
1031.
1037
103B

2
2
2
3
3
3
3
3

2
2

MSQSPTR - CH 'EXTRA TRAr~SMtT STATUS', ODH. OAH. ODH, OAH, 0),
call OUTS,
do I a 0 to 9,
r1ESSAGESWORD
EXSTRANSMITC I). STAT,
call WORDSDISP,
call CO(/H'»
call'COISP),

=

endJ

call CRSLF,
end ACTION$CMD$STATUSSDISPLAY,
1* Time Domain R.frec;t-meter result display
Name:

Input:
Output:

FUnction:

TDR.RESULT: proceduraJ

1039
1040
1041
1042
1043
1044
1045

TDR'RESULT
TDR. TIME
MESSAGE'WORD
Pass the TDR command execution result to
WORD.DISP routine.
This routine performs TDR result display *1

2
2
2
2
2
2

MESSAGE$WORD - TDR. TIME,
MSOSPTR - @IODH.OAH, 'TOR RESULT a '.0),
call OUTS,
call WORD.DIBP,
call CRSLF,
en d TDR'RESULTr
1* Buffer status display
Name:

Input:
Output:
Function:

1041.

BD$STATUS.DISPLAY
All of buffer descriptors statu. and
actual count field.
MESSAGE'WORD
Pass the parameters of all of buffer descriptors
statu. and actual count to WORD$OI6P routine. *1

BDSSTATUSSDISPLAV: procedurel

1047

2

declare 1

104B
1049
1050
1051
1052
1053
1054

2
2
2
3
3
3
3

MSQ$PTR - ICODH.OAH. '** RFD STATUS'.ODH,OAH,O),
call OUTS,
do I = 0 to 15;
MESSAGE.WORD
RFDII).STAT,

1055
1051.
1057
1058
1059

2
2
2
3
3
3
3

lObO

1061

byteJ

=

cal·1 WORDSDISP,

call COCSP),
, end,
f1SGSPTR

=-

1:(

'**

RFD EL AND S',OOH,OAH,O);

call OUTS,
do I=-O to 15,
r1ESSAGESWORD = RFD I I ). ELSS,
call WORD.DISP,
call CO(SP),

end,

e( ,**

2
2
2
3
3
3
3

MSGSPTR

101.3
1064
101.5
1066
1067
106B

1069
1070
1071
1072
1073
1074
1075

2
2
2
3
3
3
3

MSG.PTR a @I'** RFD BUFFER DESCRIPTOR POINTER'.ODH.OAH,O),
call OUTS,
do I - 0 to 15.
MESSAGESWORD = RFDCI).DD$PTR,
call WORDSDISP,
call COISPI,
end.

1076
1077
107B
1079

2
2
2
3

MSQ$PTR • el'** RFD DESTINATION ADDRESS',ODH.OAH.O),

lOBO
lOBI
IOB2

3
3
3

1062

::a

RFD LINK ADDRESS', OOH, OAH, 0),

call OUTS,
do 1 =tD 15,
r1ESSAGESWORD = RFDII)' LINK.ADDRESS'
call WORD.DISP,
call COCSP),
end,

°

call OUTS.
do I D 0 to 15,

MESSA9E.WORP

D

Ishlldouble .IRFDII)'DEST$ADDREBSI1)).B)' +
daubleIRFDII).DEST.ADDRESSIO))),

call WORD.DlilP,
call COISPI,
end,

5-48

LAN COMPONENTS USER'S MANUAL

Table 5-6. Software listings (Continued)
1083
1084

2
3

dol = 0 to 15.
I1ESSAGE$IJDRD

=

Ishlldouble IRFOI

I).

OEST$AOORESS(3» , 8) +

daub Ie (RFD( I). DEST$ADDRESS(2»)) I
1085
1036
1087
1088
1089

3
3
3

2
3

1090
1091
1092

3
3
3

1093
1094
1095
1096

2
2
2
3

1097
1098
1099
1100
1101

3
3

1102
1103
1104
1105
1106

3
3
3

1107
1108
1109

3
2
3

2

:1

call WOHD$DISP,
call COISP),
end.
do I = 0 TO 15,
I1ESSAGESIJORD

~

Ishlldouble IRFDII). DESnADDRESS(5)),8) +
doublelRFDI I), DEST$ADDRESS(4))),

call WORD.DISP,
call CDISP),
end;

11SG$PTR = I!('** RFD SOURCE ADDRESS',ODH,OAH,O),
ca 11 OUTS,
do I = 0 to 15;
I1ESSAGESIJORD = I shl I doub Ie IRFDI I). SOURCES ADDRESS I 1)),8) +
doub Ie IRFDI I), SDURCESADDRESSIO))),
call WORD.DISP,
call COeSP);
end;
do I = 0 to 151
MESSAGE$IJORD = IshlCdouble IRFDIIl. SOURCESADDRESS(3)),8) +
doubleIRFDII).SOURCESADDRESSI2))I,
call WORDSDISP,

call COISP),
end;
do I

= 0 to 15.
I1ESSAGESWORD = Ishlldouble IRFDII)'SOURCE$ADDRESSI5»,8) +
doubleIRFDII).SOURCESADDRESSI4))I,
call WORDSOlSP,

3

call COISPI,

3
3

end,

2

'"SGSPTR = @C

,** RFD TYPE FIELD' I ODH. OAH, 0) J
call OUTS,
do I = 0 to 151
I1ESSAGESWORD = RFDII I. TYPE$FIEI.D,
call WORDSDISP,
call CoeSP);

1110
1111
1112
1113
1114
1115
1116

2
2
3
3
3
3

1117
1118
1119
1120
1121
1122
1123
1124
1125
1126

2
2
2
2
2
2
3
3
3
3

1127
1128
1129
1130
1131
1132
1133

2
2
2
3

1134
1135
1136
1137
113£l
1139
1140

2
2
2
3
3
3
3

r1SGSPTR = @( '** RBD BUFFER OFFSET,
call OUTS;
do I ::a 0 to 15;

1141
1142
1143
1144
1145

2
3
3
3
3

do I

1146

1147
1148
1149
1150
1151
1152

2
2

t"lSG.PTR = @('** RDD BUFFER SIZE', ODH, OAH. 0);
call OUTS;

2
3
3
3
3

do I = 0 to 15.
MESSAGESWORD = RBDIII. SIZE,
call WORD$DISP,
call COISPI.
end;

1153
1I54
1155

2
2
2

t1SG$PTR = @.( '** TOO ACTUAl: COUNT', ODH, OAH, 0);
call OUTS;
do I = 0 to 15,

:i
3
3

end;

f'lSG$PTR = @(ODH,OAH,' TYPE  TO·CONTINUE',O)I

call OUTS,
call INS,
f1SGSPTR == (!(ODH.OAH,
call OUTS.

do I

,**

RBD ACTUAL COUNT', ODH, OAH, 0)1

0 to 151
MESSAGESWORD ~ RBDCII.ACT$COUNT,
call WORD.DISP,
call COISP).
:=I

end;

11SGSPTI> a I!!I'** RBD NEXT DO ADDRESS',ODH,OAH,OI,
call OUTS,
do I = 0 to 15,
MESSAGE.WORD = RBD I I I. NEXT$BDSADD.
call WORDSDISP,
call CO(SP);
end;

I1ESSAGESI~ORD

= RBDI

I).

BASE', ODH, QAH. 0);

DUFF$OFFSET,

call WORDSDISP'
call COCSP)J

endl

= 0 to 15i
I1ESSAGESWORD
RBD I I l. BUFF$BASE,
call WDRD$DISP,
call CO(SP)i

=

end;

5-49

LAN COMPONENTS USER'S MANUAL

Table 5-6. Software Listings (Continued)
MESSAGE. WORD • TBD( I). ACnCOUNT.
call WORDSDIsP,
call CO(SP),

1156
1157
1159
1159

3
3
3
3

1160
1161

r1sGSPTR = Ii!(

1165
1166

2
2
2
3
3
3
3

1167
1169
1169
1170
1171
1172
1173
1174
1175
1176
1177
1179

2
2
2
3
3
3
3
2
3
3
3
:3

'1SQSPTR =

1179

2

end BDSsTATUsSDISPLAY,

1180
1181
1182

1
2
2

INSSTAT: procedul'e byte;
declar9.CHAR

1162

1163

1164

1183
1184
1185

1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196

3
3
3
3,
3
3
3
3
3

end;.

TDD NEXT DD ADDRESS'. ODH. OAH. 0),

=

MEssAGE.WORD
TBD ( I ). NEXTSBDSADD,
call WORD$DIsP,
call CO(SP),

end;

fie

,**

TOO BUFFER OFFSET,.BASE', QDH, OAH, 0),

call OUTSi
do I = 0 to 151
MESSAGESWORD • TBD(I).BUFF'OFFSET,
call WORDSDISP,
call CO(SP),
endl

do 1

Eli

0 to 1:';

MESSAGE.WORD - TOD 

b~tej

CHAR <> fa') OT'
<> 'b') 01"
or CHAR <> '5'»;

'A'

(CHAR <> 'B'

(CHAR <> '5'
CHAR
CI and 7FH,
call CO(CHAR),

=

01"

OT'

CHAR

if CHAR c 'A' OT' CHAR
then retU'T"n 'A',

=

else if CHAR

CHAR = 'b'

=

'B'

01'

'a'

ttle" return 'B'i
else if CHAR = '5',01" CHAR = '5'
then return'S"
else do;

MSGSPTR = @(ODH,OAH, 'STAT> KEY IN 5, A, 01" B',ODH,OAH.2AH.O)J
call OUTS;
end;

4

4
4
:3
2

'**

call OUTS,
do I :a 0 to 15;

end;
end !l KEY IN CDMr1AND THAT YOU WANT TO SEE IN THE STATUS'.
DOH. OAH. 0),
call OUTS,
r1sGSPTR = e( '5 FOR sCB. A FOR ACTION COI1MANOS. B FOR DUFFER DESCRIPTORS'.
ODH. OAH. 2AH. 0) ,
call OUTS,
MESSAGE$BYTE = IN$STAT,
if MESSAGES BYTE = 'A'then call ACTION$CMD$STATUsSDIsPLAY,
else if MESSAGESBYTE = '9' then call BDSSTATUs$DISPLAY,

else if MESSAGESBVTE

=

'5' then do;
call CP$DISPLAY,
call sCB$sTATUs$DIsPLAY,

end;
end sTATUs$DIsPLAY,

1* Initialize individual block

Name:

INITSCOMMAND

Input:

CSBUF (console in)
None

Output:

5·50

LAN COMPONENTS USER'S MANUAL

Table 5·6. Software Listings (Continued)
InterpT'et thE" kL'Y in command to determine
what should be initialized individuilily.

Function:

This routine is able to initialize
the command block. buffer descriptors and
buffers.
INIT$COMMAr-lD:

1214

I1SG$PTR = @(ODH,OAH, 'INIT> KEY IN YOUR CoMI1AND
ODH. OAH. 2AH, 0);

1215

2

1216

2

ca 11 OUTS,;

1217
1218

2
2'
2
2
2
2
2
2
2
2
2

call

1220
1222
1224
1226
1228
1230

1232
1234

l236
1238
1240
1242

1248

2
2
2
3
3
3
3
3

1249

2

1250

2

1243

1245
1246
1247

1251

1252
1253
1254

1255

1256
1257
1258

1259
1260
1261

1262
126:3
1264

1265
1266
1267
1268

LOOP3:

2

3
3
3
3
3
3
3
3

3
4
4
4

3
2

(H FOR HELP)',

INS;

if (cmpb(@C5BUF(O), @('NOP',ODH), 4) = TRUEl,J) then call NOP$CMDl
else if (cmpb(@C$DUF(O).@('IA',QDH), 3) = TRUEW) then call IA$SETUP$CMD;
else if (cmpb(@C$BUF(O). @( 'COt~F", OOH), 5) = TRUEW) then call CONF$CMDl
else if (cmpbC@C$BUF(O),@C'MC',ODH), 3) = TRUEW) then call MC$SETUP$Ci'lD;
else if (cmpbC@C$BUFCO),@('TX'.OOH), 3) = TRUEW) then call TX$CI1D;
else if (cmpb(@C$BUF(O),@('TOR',ODH), 4) = TRUEW) then call TDR$CMD;
else if (cmpb(@C$BUF(O),@('DS',ODH), 3) = TRUEWl then
call DUI'IP$STA1$CND.
else if (cmpb(@C$DUF(O),@('DIAG',ODH), 5) = TRUEW) then call DIAOSCMDJ
else if (cmpb(@C$BUF(O),@('RFD'.ODH), 4) = TRUEl~) then call INIT$RFDl
else if (cmpb(@C$BUF(O),@('RI3D',ODH), 4) = TRUEW) then call INIT$RDD;
else if (cmpb(@C$I3UFCO),@(;RB',ODHl. 3) = TRUEW)
then call INIT$RE;
else if (cmpb(@C$BUF(O),@('TBD',ODH), 4) = TRUEWl then call INIT$TBD;
else if (cmpb(@C$13UF(O),@(;H',OOH), 1) = TRUEW) then
do; call COMMAND$MSG.
ca 11 BO$MSGi
call CR$LF;
goto LOOP3;
end;
else
call t1SG$ILL$Ct1D;
end

FNIT$COMMAND;

IN$CR:

2
2

1;'/

procedure.

procedure byteJ

declare CHAR
by tel
CHAR = 0;
do while ,«CHAR <> 'e'l or (CHAR <> ',')
(CHAR <> ;R') or CCHAR <> 'r') or
(CHAR <> -'B') or (CHAR <> 'b'»;
CHAR = CI and 7FH;
call CO(CHAR);
if CHAR = 'c' or CHAR
'C'
then return 'C';
else if CHAR = ;R' or CHAR
'r'
then return 'R';
else if CHAR = ;B' or CHAR
'b'
th en return 'E';
else do;
t1SG$PTR = @(ODH, OAH, 1** KEY IN C ,
ca 11 OUTSl
end;
end.,
end IN$CRJ

=

R or D', ODH. DAH. 2AH. 0);

1* Unit control
UN IT$CONTROL

Name:
Input:
Output:
Function:

1269
1270

2

1271

2

1272
1273

2
2

1274

1280

2
;,
3
3
3
3
3

1261

2

1282

2
3
3
3

1275
1276
1277
1278

1279

1283
1284
1285

UNIT'tCONTROL:
declare
11SG$PTR

=

C$BUF (Console)
None
Controls the CU or RU execution.
SCB infol'-mation will be d,isplayed.
This command is used to control CU or RU

P roc ed ure (CONTROL);
CONTROU
bytej
@(OOH, OAH, 'KEY IN

C

DDH, OAH, 2AH, 0);
ca 11 OUTS;
MESSAGE$BYTE

= IN$CR;

if MESSAGE$I3YTE
do
CONTROL;
SCB.CMO

SCB.CMD
SGB. Ct1D

=

'c'

then

CMD$START;

=

CMDSABORT;
CMD$SUSPEND;

SCB. CMD = CMO$RESUI'lE;

end;
else if MESSAGE$BYTE
do caSe CONTROL;
SCB. CMD
SCB.CMD
SCB. CI1D

=

'R' then

RCV$START;
RCV$ABoRT;
RCV$SUSPENO;

5-51

FOR COMMAND,

R

FOR RECEIVE',

*1

LAN COMPONENTS USER'S MANUAL

Table 5·6. Software Listings (Continued)
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300

= RCVSRESUME;
end;
if MESSAGE$BVTE :::I '13' then
SCB, CMD

3
3
2
2
3
3
3
3
3
2
2
2
2
2
2

do case CONTROL;

SeB.CMO
SCB,CMD
SCB. Ct1D
SCB.CMD

=

=

CMOSSTART or RCV$START;
eMDSABORT or RCVSABORT;
CMDSSUSPEND or RCV$SUSPEND;
CMDSRESUME or RCVSRESUME;

end;

call CRSLF;
SCB. CBLSOFFSET = Ct1DHOP$OFFSET;
CMD$TOPSSTATUS = FALSE;
call SCB$STATUS$DISPLAY;
call CAi
end UNIT$CQlHROL;

1* Master help display
Name:

MASTERS HELP

Input:
Output:
Function:

None

MSGSBUF (Console out)
This routine displays help for
master command interpret routine.

1302

1303

*/

MASTERSHELP: procedure;
call CR$LF;

1301
2
2

r1SG$PTR

=

@(

'START THE UNITCRU, CU)

---------- START

ABORT THE UNIT< RU, CU l ---------- ABORT', ODH, OAH,
'SUSPEND THE UNITCRU,CUl ------ SUSPEND
RESUtiE THE UNITCRU, CU) -------- RESUME', ODH, OAH, 0);

call OUTS;

1304
1305

2
2

t1SG$PTR

1306
1307

2
2

t'lSG$PTR

1308
1309

2
2

r1SG$PTR

1310
1311

2
2

=

@C 'COMMAND BLOCK SET UP ------------ CSET
STATUS DISPLAY ------------------ STAT'. DDH, OAH,
, IN I TI ALI ZE ---------------------- I N IT
RECEIVE BUFFER DISPLAY ----------- RXE', ODH, OAH, 0);

call OUTS.

=

@C 'TRANSMIT BUFFER DATA CHANGE :.------ TXB', ODH. OAH.
'EXIT FRcti THIS MONITOR ---------- EXIT
TOR RESULT ---------------------- TRES', ODH, OAH,
'DS RESULT BUFFER DISPLAY ------- DSRES
',0);

call OUTS;

=

@(

'CHIP RESET --------------------- CHRES
'ACKNOWRIGE TO INTERRUPl ---------- ACK

Maste~

Input:
Output:
Func t i on:

1315-

1316
1317
1318
1319
1320
13,21

1322
1323

1324
1325
1326
1327
1328
1329
1330
1331

1332
1333
1334
1335
1336
1337

t1ASTER$CMD:

2
2'
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

3
3

',0);

command interpreter
Name:

1313
1314

OOH. OAH,

end r1ASTER$HELP.l
1*

1312

I,

call OUTS;

LOOP4:

MASTER$CMD
C$BUF (console

in)
None
Interpret the First Level commands.

MSG$PTR

= @CODH, OAH, 'MAIN> KEY IN YOUR COMMAND CH FOR HELP)', ODH, OAH, 2AH, 0);

call OUTS,;
cB11 INS;
if (cmpb (@C$EUFCO),@('START',ODH).

6)

= TRUEW)

then call UNIT$CONTROL(O);
else if (cmpb(@CSBUFCO),@('ABORT'.ODH), 6) = TRUEW)
then call UNIT$CONTROL(!)i
else if (cmpb(@C$!3UF(O),@('SUSPEND'.ODH).

8) =" TRUEW)
then call UNITSCONTROL(2);
else if CcmpbC@C$BUFCO)i@C'RESUME',ODH), 7) = TRUEW)
then call UNIT$CONTROL(3);
else if CcmpbC@C$EUFCO),@C'CSET',ODH), 5) = TRUEW)

thE'n call COMt1AND$SET;
else

if (cmpbC(?:C$BUF(O),@('STAT'.ODH),
then call STATUS$DISPLAY;

else if (cmpb(@C$EUFCO),@('INIT',ODH),

:.;

)

=

TRUEW)

5) = TRUEW)

then call INIT$COMMAND;
else if

*1

procedure;

CcmpbCeC$BUFCO),@C'RXB',ODH),

4)

TRUEW)

then call BUFFERSDISPi
if (cmpb(@C$BUFCO),@('TXB',ODH). 4) = TRUEW)
then call TRANSMIT$DATA$CHANGE.
else if (cmpb(@C$BUF(O),@('H',ODH), 2) :& TRUEW)
then do;
else

c a 11 tiASTER$HELP;
goto LOOP4;

5-52

LAN COMPONENTS USER'S MANUAL

Table 5-6. Software Listings (Continued)
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348

3
2
2
2
2
2
2
2
2
2
2

1349
1350

2
2

end,
else if (cmpb(eCSBUFCO),QC 'EXIT',ODH),

5) = TRUEW)
thon call EXIT.
else if (cmpb(&CSBUFCO),@('TRES',ODH), 5) 1::1 TRUEW)
thon call TORSRESULT,
01 . . if (cmpb(eCSBUF(O)'(!( 'OSRES'.OOH). 5) = TRUEW)
thon call OS.BUFF.OISP.

else if (cmpbCQCSBUFCO),@('CHRES",ODH),
then call CHIP.RESET.
allie if (cmpbC(!CSBUF(O),(1:( 'ACK',ODH),
then call ACK,

MAIN:

2
2
2
2
2

1360
1361
1362
1363
1364
1365
1366

2
2
2
3
3
2
1

b)
1::1

:I

TRUEW)

TRUEW)

el . . call MSGSILL.Cll0.
end MASTER.CMO,

1351
1352
1353
1354
1355
1356
1357
1358
1359

4)

do;

call INITSSYS.

call INIT$RFD;
call INIT$RBD,

call ·Ir.!IT$RBI
call It35 ns

T29

0-60n5

1=

T
20 n: MIN

~

T9
IOns MIN

DATA INTO 82586

I

T40

READ
CYCLE

0-95 os

T40 260 ns MIN

\

RD FROM 82586

r

-o_Tirins-

--

T31

o-60"s

1-85~~tIN T32

Ons MIN

DATA OUT OF 82586

WRITE
CYCLE

T23

0-70n$

ViR

T45 210ns MIN

I

FROM 82586

I
~

124

0-65"5

Figure 5-4. 82586 Memory Interface Timing

5-65

231420-4

AP-234

operation. Command access time for a read cycle is 2 X
Tl - T40 - T8 + n X Tl, which is 135 ns. Time
from the read command going inactive to the next address asserted is T44, which is 85 ns minimum at 8
MHz. Address setup time for a write cycle is TI - T29
- 18 + T23, which is 47 ns minimum.

5.10.4 82586 Memory Interface
The 74LS373 has a delay of 18 ns for input data to
reach the output assuming the latch enable is hi. A
demultiplexed valid address (output of the address
latch), therefore, becomes available after T29 + 18
measuring from the beginning of Tl (Figure. 5-4). The
demultiplexed address remains valid until the ALE of
the next memory access becomes active. Upper address
lines, AI4 through A20, are connected to a 16L8 PAL,
which provides address decode logic for all memory
devices. The PAL has a maximum of 35 ns propagation
delay, so chip selects should become active after 60 +
18 + 35 ns (max.) from the beginning ofTl as indicated in Figure 5-4. Since address decode logic is implemented by a PAL, any memory expansion would only
require a reprogramming of this PAL.

To meet these timing requirements, 2764-20s must be
used for ROM. Static RAM chips, HM6264P-15, offer
very wide timing margins and were selected for this
design.

5.10.5 80186 Memory Interface
Figure 5-5 shows the timing of the 80186 memory interface. By comparing this figure to Figure 5-4, it is
easy to notice that the 80186 offers a little faster bus
interface. TCLRL which is equivalent to T40 (0 to
95 ns) of the 82586 is specified as 10 to 70 ns. Since the
memory choice satisfies the 82586memory timing parameters, it also satisfies the 80186 memory timing parameters.

Address access time is 3 X TI - TI - T29 - 18 T8 + n X TI, where n is the number of wait states.
For 0 wait states operation at 8 MHz, it is 277 ns minimum. Chip select access time is 3 X TI - T29 - 18
- T8 + n X TI - 35, which is 242 ns for 0 wait state

T1

-

T2

T4

T3

Tl

DELAY IN
i--74LS373

--

VALID AO-A19 FROM ADRESS LATCH

TCLAV
5-55ns

-

PAL DECODER
-[ DELAY:5 35 ns

'\

I
TCLDX
10 ns MIN

TCLRL
10-70ns

READ
CYCLE

TRLRH 200 ns MIN

RDFROM 80186
TRHAV _
85 nsMIN

TCLRH
10-55 ns

f--.

I~

TCLDV
10-44ns

TCLDOX
10ns MIN

DATA OUT OF 80186

WRITE
CYCLE

TCVCTV
10-70ns

WR

-

-TWLWH 210ns MIN

-----<0

FROM 80186
tCVCTX
5-55 ns
f

Figure 5-5. 80186 Memory Interface Timing

5-66

231420-5

intJ

AP-234

nection will enable a programmer to implement an
80186 controlled deadman timer for the 82586. Note
that the TSMS program does not make use of this hardware feature.

5.10.6 Memory Map
With 2764-20 EPROMs and 6264P-15 SRAMs, this
board has 32 Kbytes of ROM space and 16 Kbytes of
RAM space. Memory map is given in Figure 5-6. If
27128-20 EPROMs are used, the ROM space becomes
64 Kbytes.

OFFFFF

//////
,

22764

OFFFFF

/

PLUGGED IN/
/

OFCOOO

'////

,

/,

/

427128

'//

V PLUGED IN
~////
22764

/

PLUGGED IN/

//////

OF4000

OFOOOO

82530 interface to the 80186 was derived from the design example presented in the Application Note 222,
order number 231262-001. Only the asynchronous operation of the 82530 is supported in this design. For
more details, please read the Application Note 222.

~
/'

.

OF7FFF

5.10.7.3 82530 INTERFACE

5.10.7.4 82501 LOOPBACK CONFIGURATION
PORT

.

I~

A 74LS74 D-type flip-flop was used for this port. On
power up, it configures the 82501 to Non-Loopback
mode by providing hi to pin 3 (Loopback). The chip
select is generated from the 80186's PCS2 and the synchronized WR command of the 82530 interface. The
least significant bit of I/O output data becomes the
state of the 8250 I 's pin 3.
5.10.7.5 ON-BOARD INDIVIDUAL ADDRESS
PORT

3FFF

3FFF

o

To provide the 82586 a hardware configured host address, a 32 x 8 ROM is connected to the bus. The chip
select for this ROM is generated from the 80186's
PCS3, so that the address for ROM is mapped into the
110 space. Six or two (IEEE 802.3 specified address
lengths) consecutive 110 reads starting from the lowest
address of ROM will transfer the board address stored
in the ROM to an lA-Setup command block of the
82586.

16k BYTE
RAM

16k BYTE
RAM

o
231420-6

Figure 5-6. LANHIB Memory Map

5.10.7 80186 I/O Interface
5.10.7.1

82586 CHANNEL ATTENTION
GENERATION

5.10.8 82586 Ready Signal Generation
82586 asynchronous ready (ARDY) signal is generated
from a shift register. The shift register provides the
82586 a 'normally ready' signal. Only when a wait state
is needed, the ready signal is dropped to the 10 state. As
shown in Table 2, the 82586 can be programmed to
have 0 to 8 wait states by setting the DIP switch properly. Even though the on-board memory devices are
fast enough for 0 wait states operation, this programmable wait state capability was added, so that the effect
of wait states to the 82586 performance can easily be
demonstrated using this feature.

The active low peripheral chip select 0 (PCSO) was used
to generate a channel attention (CA) signal to the
82586. This way of CA generation satisfies the requirement that the width of a CA must be wider than a clock
period of the system clock.
5.10.7.2 82586 HARDWARE RESET PORT

PCSI of the 80186 will reset the 82586 ifany 110 command is executed using this 110 chip select. This con-

5-67

AP-234

CALL INITIALIZATION ROUTINE 'INIT'

CONfiGURE THE ESI TO NON-LOOPBACK

NO

NO

231420-7

Figure 5-7. Main Program

5-68

AP-234

Table 2. DIP Switch Settings for Various Numbers of 82586 Walt States
7

6

5

1
1
1
1
1
1
1
1
0

1
1
1
1
1
1
1
0
0

1
1
1
1
1
1
0
0
0

DIP Switch Setting
4
3

1
1
1
1
1
0
0
0
0

1
1
1
1
0
0
0
0
0

2

1

0

1
1
1
0
0
0
0
0
0

1
1
0
0
0
0
0
0
0

1
0
0
0
0
0
0
0
0

Number of Wait States
the 82586 Inserts

0
1
2
3
4
5
6
7

8

NOTES:

1
o

=
=

Switch Open
Switch Closed
ESI (Ethernet Serial Interface). is configured to NonLoopback mode at this point. If any incoming frames
are qualified to be received, the 82586 will start receiving these frames and the CPU will keep track of how
many good frames are being received.

5.11 TSMS PROGRAM CONTROL
FLOW
The original TSMS software listing is in Appendix B.

5.11.1 Main Program
Flow chart for the TSMS main program is shown in
Figure 5-7. The program starts by calling an initialization routine 'init' (Figure 5-8). In this routine, the CPU
sets up the ISCP (Intermediate System Control Pointer), SCB (System Control Block), and a linked list of
four 82586 commands: Diagnose, Configure, lA-Setup,
and MC-Setup. Busy byte in the ISCP is set. The CPU
also initializes a transmit command (EL = 1, S = 0,
I = 0) if traffic generation is to be performed by this
station. Five RFDs (Receive Frame Descriptors), five
RBDs(Receive Buffer Descriptors), and five receive
buffers are set up. The data structure defined in the
'init' routine is shown in Figure 5·9. The transmit com·
mand is not pointed to by the SCB yet. It will be linked
to the SCB later in the main program after the 82586 is
properly initialized. At the end of 'init' routine, the
very first CA to the 82586 is given. In response to this
CA, the 82586 jumps to address location OFFFF6H
and starts the initialization procedure.

SETUP

ISCP
SCB
DIAGNOSE CB
CONFIGURE CB
lA-SETUP CB
MC-SETUP CB

NO

The main program waits for the 82586 to finish the
initialization procedure by checking 'reset' flag. The
'reset' flag is cleared after a completion of the 82586
reset interrupt (CX = CNA = 1) acknowledgement.
The predefined linked commands pointed already 'by
the SCB: Diagnose, Configure, lA-Setup, and MC-Setup, are executed by a CA after the 'reset' flag is cleared.
Any failures in execution of these commands are indicated on the screen as errors.

231420-8

After successful Diagnose, Configure, lA-Setup, and
MC-Setup commands execution, the RU is started. The

Figure 5-8. 'init' Routine

5-69

AP-234

SCpo
OFFFFF6 .-..- - - ,

ISCP

I
SCB

~

DIAGNOSE

-

~I

CONFIGURE

I

lA-SETUP

MC-SETUP

~

EL=1

TRANSMIT

--,+

EL=1

TBD

BUFF

__

RFD
"
....;'~I.---~:_:--_-:_.~--_-:_.~--_.,+--.Ir---_...,LJ

231420-9

Figure 5-9. 82586 Data Structure after '.init' Routine

5-70

AP-234

If this station is to generate traffic on the network, the
station will start to transmit frames. This is done by
linking the SCB to the transmit command already set
up in the 'init' routine and issuing a CA. Since the
transmit command has its EL-bit set, the 82586 interrupts the CPU with CNA = I after every execution.
The number of good frames transmitted is counted by
the CPU.

The main program gets in an infinite loop after the RU
and CU are defined. The program keeps updating the
frame counters indefinitely in the loop. Within the loop,
the CPU checks if anything has been typed at the keyboard. If any key on the keyboard has been pressed, the
program calls a routine 'getout' (Figure 5-10) and gets
into the interactive command execution mode. In the
interactive command execution mode, any 82586 action
or control command can be set up and executed interactively.

PRINT 'ENTER COMMAND (H FOR HELP) ==>'

NO

)
231420-10

Figure 5-10. 'getout' Routine

5-71

inter

AP-234

ENABLE 82586 INTERRUPT

NO

231420-11

Figure 5-11A. Interrupt Service Routine

5-72

intJ

AP-234

NO

INCREMENT TRANSMIT FRAME COUNTER

231420-12

Figure 5-11 B. Interrupt Service Routine (Continued)

5·73

infef

AP-234

NO

YES

NO

YES

NO

231420-13

Figure 5-11C.lnterrupt Service Routine (Continued)
5-74

AP-234

knowledged. If the received frame is good, the receive
frame counter is incremented. The program exits the
interrupt service routine at this point, so that a new
interrupt, if any, can be processed from the beginning
of the service routine again.
If the FR bit is reset and the CNA bit is set, the CNA
interrupt is acknowledged. After the acknowledgement,
the status word of the transmit command is checked
(Figure 5-11B). If the status indicates a good frame
transmission, the transmit frame counter is incremented. If the station has been programmed to stop transmissions after a known number of frame transmissions,
the transmit frame counter is checked if it has reached
the final value. If it has, then the program exits the
service routine. If the 'station is to transmit more
frames, then the transmit command block status is
cleared and a new transmission is executed. If the transmission is to start after a delay, 'start$timerO' procedure is called to perform a delayed transmission (Figure 5-12).

231420-14

Figure 5-12. 80186 Timer Interrupt

5.11.2 Interrupt Service Routine
The 82586 interrupt service routine in the TSMS program is a reenterrant procedure. It is written in such a
way that the routine itself can be interrupted repeatedly
by its own level or the higher level of interrupts. A
critical region, a section of codes that should not be
interrupted, is constructed by a pair of 'disable' and
'enable' PL/M commands. Each SCB command execution: writing a SCB command, issuing a CA, and waiting for the SCB command word to become zero, is enclosed in this pair, so that overwriting a SCB command
will never occur.

If the transmit command block status indicates a transmission failure, the kind of failure is printed on the
screen and then a retransmission is executed. There are
four kinds of transmission failures: too many collisions,
no carrier sense, lost clear to send, and DMA underrun.
CX and RNR interrupts are acknowledged after the
interrupt is disabled (Figure 5-11 C). At the very end of
the service routine, the 'reset' flag is checked. If it is set
and also the BUSY byte of the ISCP is set, an error
message is printed and a software reset is issued.

The 82586 interrupt is enabled at the beginning of the
interrupt service routine (Figure 5-11A).
Among the 82586 interrupts, the FR (Frame Received)
interrupt is given the highest priority in the service routine. The FR bit in the SCB status word is always
checked first if it is set or not. If it is, interrupt is immediately disabled and the FR interrupt is ac-

This interrupt service routine is verified to be able to
receive back-to-back frames separated by 9.6 microseconds and keep track of correct number of frames received (refer to section 5.12 for limits of TSMS).

**************************** station Configuration ************************
Host Address: 00 AA 00 00 18 60
Multicast Address(es): No Multicast Addresses Defined
Destination Address: FF FF FF FF FF FF
Frame Length: 118 bytes
Time Interval between Transmit Frames: 159.4 microseconds
Network Percent Load generated by this station: 35.7 %
Transmit Frame Terminal Count: Not Defined
82586 Configuration Block: 08 00 26 00 60 00 F2 00 00

40

***************************** station Activities **************************
# of Good
Frames
Transmitted
10130

# of Good
Frames
Received
0

CRC
Errors

Alignment
Errors

0

0

No
Resource
Errors
0

Receive
Overrun
Errors
0
231420-15

Figure 5-13. Continuous Mode Display
5-75

inter

AP-234

Transmit Frame Terminal Count: number of frames
this station will transmit before it stops network traffic load generation. If this station is transmitting indefinitely, this field will be 'Not Defined'.

5.12 CAPABILITIES AND LIMITS OF
THE TSMS PROGRAM
The TSMS program has two modes of operation: Continuous mode and Interactive Command Execution
mode. In the Continuous mode, the software uses the
format shown in Figure 5-13 to display information.
Detailed description of each of these fields is as follows:

82586 Configuration Block: configuration parameters used in the most recently prepared Configure
command. As in the case, of lA-Setup command, the
software simply write the parameters from the Configure command block. The least significant byte
(FIFO Limit) of the configuration parameters is
printed in the most left position.

Host Address: host (station) address used in the most
recently prepared lA-Setup command. The software
simply writes the address stored in the lA-Setup
command block with its least significant bit being in
the most right position. Note that if the lA-Setup
command was just set up and not executed, the address displayed in this field may not be the address
stored in the 82586.

# of Good Frames Transmitted: number of good
frames transmitted. This is a snap shot of the 32-bit
transmit frame counter. It is incremented only when
both C and OK bits of the transmit command status
are set after an execution. The counter is 32-bit wide.

Multicast Address(es): multicast addresses used in
the most recently prepared MC-Setup command. As
in the case of host address, the software simply writes
the addresses stored in the MC-Setup command
block. Note that if the MC-Setup command was just
set up and not executed, the addresses displayed in
this field may not be the addresses stored in the
82586.

# of Good Frames Received: number of good frames
received. This is a snap shot of the 32-bit receive
frame counter. It is incremented only when both C
and OK bits of a receive frame descriptor status are
set after a reception. The counter is 32-bit wide.

CRC Errors: number of frames that had a CRC error. This is a snap shot of the 16-bit CRe counter
maintained by the 82586 in the SCB.

Destination Address: destination address stored in
the transmit command block if AL-LOC = o. If ALLOC = I, destination address is picked up from the
transmit buffer. The least significant bit is in the
most right position.

Alignment Errors: number of frames that had an
alignment error. This is a snap shot of the 16-bit
alignment counter maintained by the 82586 in the
SCB.

Frame Length: transmit frame byte count including
destination address, source address, length, data, and
CRC field.

'No Resource Errors: number offrames that had a no
resource error. This is a snap shot of the 16-bit no
resource counter maintained by the 82586 in the
SCB.

Time Interval Between Transmit Frames: approximate time interval obtainable between transmit
frames (Figure 5-14). The number is correct if there
are no other stations transmitting on the network.

Receive Overrun Errors: number of frames that had
a receive overrun error. This is a snap shot of the 16bit receive overrun error counter maintained by the
82586 in the SCB.

Network Percent Load generated by this station: approximate network percent load that is generated by
this station (Figure 5-14). The number is correct if
there are no other stations transmitting on the network.

1(

TIME FOR ONE FRAME TRANSMISSION (x)

j.

PREAMBLE, DA, SA, TYPE, DATA, CRC

)

TIME BETWEEN
FRAMES (Y)

I

.

c=;
231420-34

Network Percent Load =

~

X+Y

x 100

Figure 5-14. Network Percent Load

5-76

inter

AP-234

If the station is actively transmitting, # of good frames
transmitted should be incrementing. If the station is
actively receiving frames, # of good frames received
should be incrementing. In this continous mode, a user
can see the activities of the network.
Hitting any key on the. keyboard while the program is
running in the Continous mode will exit the mode. The
program will respond with a message 'Enter Command
(H for Help) = = > '. In this Interactive Command
Execution mode, a user can set up anyone of the 82586
action commands and/or execute anyone of the 82586
SCB control commands. Setting up a Dump command .
and executing a SCB Command Unit Start command
will, for example, execute the Dump command. Display commands are also available to see the contents of
the 82586's data structure blocks. A display command
will enable a user to see the contents of the 82586's
dump (see section 5.15.3).
Typing 'E' after 'Enter command (H for help) = = > "
executing a SCB Command Unit Start command with a
transmit command, or executing a SCB Receive Unit
Start command will exit the Interactive Command Execution mode. The program will be back in the Continuous mode. Using this Interactive Command Execution
mode, one can, for example, reconfigure the station and
come back to the Continous mode. Section 5.13 lists
actual example executions of the TSMS program.

The software does not perform extensive loopback tests
and hardware diagnostics during the initialization. A
loopback operation can be performed interactively in
the Interactive Command Execution mode.
The software allows a user to set up only 8 multicast
addresses maximum. It is not possible to set up more
than 8 multicast addresses.
The command chaining feature of the 82586 is not used
in the Interactive Command Execution mode. Each
command setup performed by a'S' command after 'Enter command (H for help) = = > ' will just set up a
command with its EL bit set, I bit reset, and S bit reset.
Diagnose, Configure, lA-Setup, and MC-Setup commands are chained together during the initialization
routine and executed at once with only one CA.
The software sets up 5 Receive Frame Descriptors
linked in a circular list. A user is, therefore, allowed to
see only the last 5 frames the station has received. It
also sets up 5 receive buffers, each being 1514 bytes
long, linked in circle. The station, therefore, never goes
into the NO RESOURCES state.

5.13 EXAMPLE EXECUTIONS OF THE
TSMS PROGRAM .
This section presents 3 example executions of the
TSMS program. When the TSMS program needs a
command to be typed, it asks a question with' = = > '.
Anything after' = = > ' is what a user needs to type in
on the keyboard. To switch from the continuous mode
to the interactive command execution mode, any key
on the keyboard may be pressed.

The TSMS program should be run in an 8 MHz system.
The software running at 8 MHz with a maximum of 2
wait states has been tested and verified to be able to
receive back-to-back frames separated by 9.6 microseconds and still keep track of the correct number of
frames received. This capability, for example, can be
used to find out exactly how many frames a developing
software at a new station in the network had transmitted.

5-77

intJ

AP-234

5.13.1 Example 1: External LoopbackExecution
In this example, 500 external loopback transmissions and receptions are executed (Figure 5-15). In order for the
software to process each loopback properly, a large delay was given between transmissions.

Initialization

b~gun

Configure command is setup for default values.
Do you want to change any bytes? (Y or N) ==> Y
Enter byte number (1 - 11) ==> 4
Enter byte 4 (4H) ==> A6H
Any more bytes? (Y or N) ==> Y
Enter byte number (1 - 11) ==> 11
Enter byte 11'" (BH) ==> 6
Anymore bytes? (Y or N) ==> N
configure the 586 with the prewired board address ==> N
Enter this station's address in Hex ==> 000000002200
You can enter up to 8 Multicast addresses.
Would you like to enter a Multicast Address? (Y or N) ==> N
You entered o Multicast Address(es).
Would-you like to transmit?
Enter a Y or N ==> Y
Enter a destination address in Hex

==>

000000002200

Enter,TYPE ==> 0
How many bytes of transmitdata.?
Enter a number ==> 2
Transmit Data is continuous numbers (0, 1, 2, 3, .;. )
Change any data bytes? (Y or N) ==> N
Enter a delay count ==> 10000000000
The number is too big.,
It has to be less than or equal ~o 65535 (FFFFH).
Enter a number ==>, 60000
setup a transmit terminal count? (y'orNj
Enter a transmit terminal count ==> 500

==>

Y

Destination Address: 00 00 00 00 ,22 00
Frame Length: 20 bytes
Time Interval between Transmit Frames: 30.18 miliseconds
Network Percent Load generated by this station:
.0 %
Transmit Frame Terminal Count: 500
Good enough? (Y or N)

==>

Y

Receive unit is active.
231420-16

Figure 5-15. External Loopback Execution

5-78

intJ

AP-234

---Transmit Command Block--0000 at 033E
S004
FFFF
034E
2200
0000
0000
0000
Hit  to countinue
transmission started!

****************************

Station Configuration

*************************

Host Address: 00 00 00 00 22 00
Multicast Address(es): No Multicast Addresses Defined
Destination Address: 00 00 00 00 22 00
Frame Length: 20 bytes
Time Interval between Transmit Frames: 30.lS miliseconds
Network Percent Load generated by this station:
.0 %
Transmit Frame Terminal Count: 500
825S6 Configuration Block: OS 00 A6 00 60 00 F2 00

*****************************
# of Good
Frames
Transmitted
50Q

# of Good
Frames
Received
500

Station Activities

CRC
Errors

Alignment
Errors

0

0

00

06

***************************
No
Resource
Errors
0

Receive
Overrun
Errors
0
231420-17

Figure 5-15. External Loopback Execution (Continued)

5-79

5.13.2 Example 2: Frame Reception in Promiscuous Mode
The 82586 is configured to receive any frame that exists in the network (Figure 5-16). In this example, the station
received 100 frames.

Initialization begun
Configure command is set up for "default values.
Do you want to change any bytes?" (Y or N) ==> Y
Enter byte number (1 - 11) ==>9
Enter byte 9 (9H) ==> 1
Any more bytes? (Y or N) ==> N
Configure the 586 with the prewired board address ==> Y
You can enter up to 8 Multicast Addresses.
Would you like to enter a Multicast Address? (Y or"N) ==> N
You entered 0 Multicast Address(es).
Would you like to transmit?
Enter a Y or N ==> N
R~ceive

unit is active.

**************************** station Configuration ************************
Host Address: 00 AA 00 00 18 6D
Multicast Address(es): No Multicast Addresses Defined
82586 Configuration Block: 08 00 26 00 60 00 F2

01

00

40

***************************** station Activities **************************
Alignment
Errors

# of Good
Frames
Transmitted

# of Good
CRC
Frames
Errors
Received
o
100
0
Enter command (H for help) ==> D.

o

No
Resource
Errors

o

Command Block or Receive"Area? (R or C) ==> R
Frame Descriptors:
4000 at 036C AOOO at 0382 AOOO at 0398 AOOO at 03AE
0000
0000
0000
0000
03C4
0382
0398
03AE
03F8
03EE
03DA
03E4
2200
2200
2200
2200
2200
2200
2200
2200
0000
0000
0000
0000

Receive
Overrun
Errors

o

AOOO at 03C4
0000
036C
0402
2200
2200
0000
231420-18

Figure 5·16. Frame Reception In Promiscuous Mode

5-80

AP-234

0000
0000
0000
0000

0000
0000
0000
0000

0000
0000
0000
0000

Receive Buffer Descriptors:
C064 at 03DA C064 at 03E4 C064 at 03EE
03F8
03EE
03E4
OFEO
09F6
040C
0000
0000
0000
05DC
05DC
05DC

0000
0000
0000
0000

0000
0000
0000

C064 at 03F8
0402
15CA
0000
05DC

C064 at 0402
03DA
1BB4
0000
05DC

oooq

Display the receive buffers? (Y or N) ==> Y
Receive Buffers:
Receive Buffer 0
002C:014C 00 01
002C:015C 10 11
002C:016C 20 21
002C:017C 30 31
002C:018C 40 41
002C:019C 50 51
002C:01AC 60 61

:
02
12
22
32
42
52
62

03
13
23
33
43
53
63

04 ,05
14 15
24 25
34 35
44 45
54 55

06
16
26
36
46
56

07
17
27
37
47
57

08
18
28
38
48
58

09
19
29
39
49
59

OA
1A
2A
3A
4A
5A

DB
1B
2B
3B
4B
5B

DC OD
1C 1D
2C 2D
3C 3D
4C 4D
5C ,5D

DE
IE
2E
3E,
4E
5E

OF
IF
2F
3F
4F
5F

03
13
23
33
43
53
63

04
14
24
34
44
54

05
15
25
35
45
55

06
16
26
36
46
56

07
17
27
37
47
57

08
18
28
38
48
58

09
19
29
39
49
59

OA
1A
2A
3A
4A
5A

DB
1B
2B
3B
4B
5B

DC
1C
2C
3C
4C
5C

OD
1D
2D
3D
4D
5D

DE
IE
2E
3E
4E
5E

OF
IF
2F
3F
4F
5F

03
13
23
33
43
53
63

04
14
24
34
44
54

05
15
25
35
45
55

06
16
26
36
46
56

07
17
27
37
47
57

08
18
28
38
48
58

09
19
29
39
49
59

OA
1A
2A
3A
4A
5A

DB
1B
2B
3B
4B
5B

DC
1C
2C
3C
4C
5C

OD
1D
2D
3D
4D
5D

DE
IE
2E
3E
4E
5E

OF
IF
2F
3F
4F
5F

03
13
23
33
43
53
63

04
14
24
34
44
54

05
15
25
35
45
55

06
16
26
36
46
56

07
17
27
37
47
57

08
18
28
38
48
58

09
19
29
39
49
59

OA
1A
2A
3A
4A
5A

DB
1B
2B
3B
4B
5B

DC
1C
2C
3C
4C
5C

OD
1D
2D
3D
4D
5D

DE
IE
2E
3E
4E
5E

OF
IF
2F
3F
4F
5F

Hit  to countinue
Receive Buffer 1
002C:0736 00 01
002C:0746 10 11
002C:0756 20 21
002C:0766 30 31
002C: 0776 40 41
002C:0786 50 51
002C:0796 60 61

:
02
12
22
32

42
52
62

Hit  to countinue
Receive Buffer 2
002C:OD20 00 01
002C:OD30 10 11
002C:OD40 20 21
002C:OD50 30 31
002C:OD60 40 41
002C:OD70 50 51
002C:OD80 60 61

:
02
12
22
32
42
52
62

Hit  to countinue
Receive Buffer 3
002C: l30A 00 01
002C:131A 10 11
002C:132A 20 21
002C:133A 30 31
002C:134A 40 41
002C:135A 50 51
002C:136A 60 61

:

02
12
22
32
42
52
62

Hit  to countinue

231420-19

Figure 5-16. Frame Reception in Promiscuous Mode (Continued)

5-81

infef

AP-234

Receive Buffer 4
002C:18F4 00 01
002C:1904 10 11
002C:1914 20 21
002C:1924 30 31
002C:1934 40 41
002C:1944 50 51
002C:1954 60 61

02
12
22
32
42
52
62

03
13
23
33
43
53
63

04
14
24
34
44
54

05
15
25
35
45
55

06
16
26
36
46
56

07
17
27
37
47
57

08
18
28
38
48
58

09
19
29
39
49
59

OA
1A
2A
3A
4A
5A

OB
1B
2B
3B
4B
5B

OC
1C
2C
3C
4C
5C

OD
1D
2D
3D
4D
5D

OE
1E
2E
3E
4E
5E

OF
1F
2F
3F
4F
5F

Hit  to countinue
Enter command (H for help) ==> E

**************************** station Co figuration *************************
Host Address: 00 AA 00 00 18 6D
Mu1tici1-st Address(es): No Multicast Addresses Defined
82586 Configuration Block: 08 00 26 00 60 00 F2

01

00

40

***************************** station Activities **************************
# of Good
Frames
Transmitted
0

# of Good
Frames
Received
100

CRC
Errors

Alignment
Errors

0

0

No
Resource
Errors
0

Receive
Overrun
Errors
0
231420-20

Figure 5-16. Frame Reception in Promiscuous Mode (Continued)

5-82

AP-234

5.13.3 Example 3: 35.7% Network Traffic Load Generation
The station is programmed to transmit 118 bytes long frames with a time interval of 180 microseconds in between
(Figure 5-17). The network load is about 35.7 percents if no other stations are transmitting in the network.

Initialization begun
configure command is set up for default values.
Do you want to change any bytes? (Y or N) ==> N
Configure the 586 with the prewired board address ==> Y
You can enter up to 8 Multicast Addresses.
Would you like to enter a Multicast Address? (Y or N) ==> N
You entered 0 Multicast Address(es).
Would you like to transmit?
Enter a Y or N ==> Y
Enter a destination address in Hex ==> FFFFFFFFFFFF
Enter TYPE ==> 0
How many bytes of transmit data?
Enter a number ==> 100
Transmit Data is continuous numbers (0, 1, 2, 3, ••• )
Change any data bytes? (Y or N) ==> N
Enter a delay count ==> 0
setup a transmit terminal count? (Y or N) ==> N
Destination Address: FF FF FF FF FF FF
Frame Length: 118 bytes
Time Interval between Transmit Frames: 159.4 microseconds
Network Percent Load generated by this station: 35.7 %
Transmit Frame Terminal Count: Not Defined
Good enough? (Y or N) ==> Y
Receive unit is active.
---Transmit Command Block--0000 at 033E
8004
FFFF
034E
FFFF
FFFF
FFFF
0000
Hit  to countinue
231420-21

Figure 5-17. 35.7% Network Traffic Load Generation

5-83

AP-234

transmission started!

**************************** station configuration ************************
Host Address: 00 AA 00 00 18 60
Multicast Address(es): No Multicast Addresses Defined
Destination Address: FF FF FF FF FF FF
Frame Length: 118 byt~s
Time Interval between Transmit Frames: 159.4 microseconds
Network Percent Load generated by this station: 35.7 %
Transmit Frame Terminal count: Not Defined
82586 Configuration Block: 08 00 26 00 60 00 F2 00 00

40

***************************** station Activities **************************
# of Good
CRC
# of Good
Frames
Frames
Errors
Transmitted Received
10459
0
0
Enter command . (H for help) ==> H

Alignment
Errors
0

No
Resource
Errors
0

Receive
Overrun
Errors
0

Commands are:
S - setup CB
o - Display RFOjCB
P
Print SCB
C - SCB Control CMD
ESI Loopback On
N - ESI Loopback Off
L
A
Toggle Number Base
Z
Clear Tx Frame Counter
Y
Clear Rx Frame Counter
E
Exit to continuous Mode
Enter command (H for help) ==> S
Enter command block type
Command block type:
N - Nop
I C
Configure
MTransmit
T
R 0
Diagnose
S H
Print this ,message

-

(H for help) ==> H
IA setup
MA setup
TOR
Dump status

Enter command block type (H for help) ==> S
Enter command (H for help) ==> C
Do you want to enter any SCB commands? (Y or N) ==> Y
Enter CUC ==> 1
Enter RES bit ==> 0
Enter RUC ==>.0
Issued Channel Attention

Enter command (H for help) ==>0
231420-23

Figure 5·17. 35.7% Network Traffic Load Generation (Continued)

5-84

inter

AP-234

Command Block or Receive Area? (R or C)
---Dump status Command Block--AOOO at 0364
8006
FFFF
27D6
Dump status Results
at 27D6
00 E8 3F 26 08 60
AA
00 40 20 00 00
62 63 3F BO 00 00
00 00 00 00 00 00
DC 05 00 00 OC 04
82 03 6C 03 F8 03
06 80 FF FF 64 03
00 00 D6 27 00 01
20 00 40 06 30 01
00 00 6A 03 OE 00
00 00 00 00 00 CO

00
00
00
00
DC
64
00
00
00
6C
00

Enter command (H for help)

FA
00
00
00
05
80
00
28
00
28
00

00
FF
00
00
E4
D6
D2
00
90
00
00

==>

S

00
FF
00
00
03
27
02
00
00
00
00

==>

40
FF
00
00
DA
E8
00
00
10
74

C

FF
FF
00
00
03
21
00
00
01
03

6D
B5
FF
70
DA
FF
00
30
00
00

18
9E
85
03
03
FF
00
26
00
00

00
EE
08
06
78
4E
00
00
6C
00

00
CF
FC
00
05
03
00
00
03
00

Enter command block type (H for help) ==> T
Enter a destination address in Hex ==> FFFFFFFFFFFF
Enter TYPE ==> 0
How many bytes of transmit data?
Enter a number ==> 100
Transmit Data is continuous numbers (0, 1, 2, 3, ..• )
Change any data bytes? (Y or N) ==> N
Enter a delay count

==>

0

setup a transmit terminal count? (Y or N)

==>

N

Destination Address: FF FF FF FF FF FF
Frame Length: 118 bytes
Time Interval between Transmit Frames: 159.4 microseconds
Network Percent Load generated by this station: 35.7 %
Transmit Frame Terminal Count: Not Defined
Good enough? (Y or N)

==>

Enter command (H for help)

Y

==>

C

Do you want to enter any SCB commands? (Y or N)
Enter CUC ==> 1
Enter RES bit ==> 0
Enter RUC ==> 0
Issued Channel Attention

==>

Y

231420-24

Figure 5·17. 35.7% Network Traffic Load Generation (Continued)

5·85

inter

AP-234

**************************** station configuration ************************
Host Address: 00 AA 00 00 18 6D
Multicast Address(es): No Multicast Addresses Defined
Destination Address: FF FF FF FF FF FF
Frame Length: 118 bytes
Time Interval between Transmit Frames: 159.4 microseconds
Network Percent Load generated by this station: 35.7 %
Transmit Frame Terminal Count: Not Defined
82586 configuration Block: 08 00 26 00 60 00 F2 00 00

40

***************************** station Activities **************************
# of Good
Frames
Transmitted
106020

# of Good
Frames
Received

a .

CRC
Errors

Alignment
Errors

a

a

No
Resource
Errors

a

Receive
Overrun
Errors

a

231420-25

Figure 5-17. 35.7% Network Traffic Load Generation (Continued)

and locates the TSMS program and the LANHIB ini~
tialization routine. SBC.CSD compiles, links, and locates the TSMS program and the 10 driver for the
iSBC 186/5L IUPHIB.CSD programs two 2764s for
the LANHIB. IUPSBC.CSD programs two 2764s for
the iSBC 186/51. Therefore, if the TSMS program is to
be run on the LANHIB, steps required are:

A key was hit to enter the Interactive Command Execution mode. In that mode, a Dump command was
executed and the result was displayed. After the Dump
execution, a transmit command was set up again and
the station was put in the Continuous mode.

5.14 PROGRAMMING PROMS TO
RUN THE TSMS PROGRAM

1. submit LANHIB
2. submit IUPHIB

Through Insite, the TSMS program and related submit
files are available. Files that are on the release diskette
are:

If the TSMS program is to be run on the iSBC 186/51,

steps required are:

TSMS.PLM
IO.PLM
INI186.PLM
LANHIB.CSD
SBC.CSD
IUPHIB.CSD
IUPSBC.CSD

1. submit SBC
2. submit IUPSBC
Note that all these files are assumed to be on the diskette in drive 1 (or :Fl:).
The iSDM 86 can be configured to work on the iSBC
186/51 using the configuration file shown in Figure 518. For more information about the iSDM 86, please
refer to 'iSDM 86 SYSTEM DEBUG MONITOR
REFERENCE MANUAL', order number 146165-001.

'TSMS.PLM' is the original TSMS source program.
'IO.PLM' contains the 10 driver needed when the
TSMS program is run on the iSBC 186/51.
INI186.PLM is the LANHIB initialization routine.
LANHIB.CSD is the submit file that complies, links,

5-86

AP-234

$title(iSDM S6 Configuration for the iSBC lS6/51)

*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
title: clS651
Abstract: This module configures the iSDM S6 Monitor to
run on the iSBC lS6/51.

*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*

name
c1S651
$include(:f1:cnfS6.mac)

%cpu(SOlS6)
%iAPX lS6 INIT(y,none,none,SObah,none,003ah)
%SYSTEM_CONFIGURATION_POINTER(O,none,OfffOh)
%TIMER(S0130,OeOh,2)
%PARALLEL PORT(S255a,OaOh,2)
%INTERRUPT_CONTROLLER(S0130,oeOh,2,n)
%BAUD RATE(O,O)
%SERIAL_CHANNEL(S251a,OSOh,2,S253,090h,2,2,S)
Definition of the Serial Channels on an SMHz iSBC lS6/51
%SERIAL CHANNEL(S274,OdSh,2,80186,OffOOh,2,O,Odh)
%SERIAL-CHANNEL(S274,Odah,2,SOlS6,OffOOh,2,1,Odh)
%SERIAL=CHANNEL(S274,Odah,2,S0130,oeOh,2,2,34h)
Definition of the Serial Channels on a 6MHz iSBC lS6/51
;SERIAL CHANNEL(S274,OdSh,2,S0186,OffOOh,2,O,Oah)
;SERIAL-CHANNEL(8274,Odah,2,80186,OffOOh,2,1,Oah)
;SERIAL=CHANNEL(8274,Odah,2,S0130,oeOh,2,2,27h)
%OS SUPPORT(rmxS6)
%NPX SUPPORT
%EEPROM SUPPORT(2S17)
;BOOTSTRAP SUPPORT(manua1)
%END
231420-26

Figure 5-18. iSDM 86 Configuration File for 8 MHz iSBC 186/51

5-87

Note: ISCP is at OFFFOH

inter

AP-234

APPENDIX A
LANHIB SCHEMATIC
80186/82586 High Integration Board
Rev. 2.0.
Ul 74S32
U274LS04
U374LS02
U474LS74
us 74LS74
U6 DS1488
U7 DS1489

+lZV
+5V

GND

I

I

r~' J""'
I

I

I"'"'

Z.ZiLF

-lZV
231420-27

0.1 p,F Capacitor on Each IC

5-88

AP-234

SV

5V

~
r;~~;':~~~':'k~4~__________Jlf'__________-L~~~'7 20ID
' ' ' 'IXXce ------------=t;:lrxc ~H/wx :;

,,,.,,,.,,;; -------------~iffiRTS
7 nco
58STXO ___________

.r

A21

ffi

'-"

~ 40

:~

::: :

;;

A175

18 70

,...

04013 9

cor

30

74LS373

...",=~=~~~=======:::;_t1t-"~1 ','c
AD"~~

31 eRS

586RXD ___________-""15 RXO

5aiCDi

0

r--------------------------I-~. 3'

"DI5~

:=====~'~31~A:'C

5aiCiiS
5i'iiiC

~

A20~

-""I

12.n.o.

A012
A01t

.4.010

10

II

AD7A'''~:t~:~~::~~~~~:::::::~l'
ADS

13

AD6I'~:t:" :~~::~~~~~::::~.....
ADS

AD<

7 AHOY/SRrt(
58OA1iO' ___________-'3"1
45 WR

ALEr.,3,' -

2
~
I

35 CA

BHE

DT/A

_-I--I-H-9__",,3.2. CLK

r-!!

*

DEN;

...-1-++-__..,:3;1" RESET

S:~

"
A'3",~.:tI=:::j~I:t:=:;-]

AD!
Et:tl=:::j~~:l
ADO~2

46 RD

AD
Wi

A021:"

HOLD

~G

~

ri

~

10
20

• 3'
"
"
" eo

FL-_--'
tNT

7'"-5373
\...,I

HLDA

13

50 12

50

6Q 15

17 60

58.~--~4-~-44-------------~~~

10 '
'300 5•
'0 '
70 '6

7D

80 19

I

I~

I~
~

Tz
-f,

62

DROO .......,
OROI
INTO
1NT2/INTAO

5' #Sl #so ~

63 RD

W,

~,
,
.,
~

3

~28

ESlLPBK

CLKOUT

SHE

AI.
AI.

AESET

PcSci

• RO'

ADl'

30 PC$3

;:;oc;

~
~
~
~

~
..g
~

pes,

PCS.

A012

UcS

AD11

LCS

ADIO

wcso

INnt

:i1

l"'5V 4 --~

NCSI

NNI
TWRoun

TWROUTO
21
TWRIN1
20
n.1RINO

1OkQ,

.. '1 ,".
1 J~
lOOkA

47 RES

ti'P
-

20

TEST

"WH_ 58 XI

_.".

18

~X2

2D

65
66

\...,I

10 '
'300 •5
40'

50

5Q 12

6D

60 '5
70 '6
80 .!!...-

7D

~DC

A9

."
"
"

A3

"
AI

.".

1

3

'"
,I<

7

01'

10

'"
"
"
""

12

01.

ADS "
A" ,
AD7 ,
ADO
AD, •
AD,

16

Z

~ NCS3i

5V

~
"

AD14
A013 5

PCSS

NCS'

..'"

A17 67
A16 68

PCSt

29 PCSZ

r-

"
~

7

UI

UAL~
RtsEf

, ID
13• "3'
"
" eo

SRDY
55
ARDY
ALE

,It
'"

74LS373

~G

~
HOLD 1!...-

INil/INTA!

AI<

i---

00-07
08-015

A14

26

A13

2

A12

23

All

21

AID

24

A9

25

A8

3

A7

4

A6

5

AS

6

A4

7

A3

8

A2

9

Al

10
20

~

NC

\....../

A12
All
AID
A9

07

A8

06

A7
A6

05
2764-2

04

AS

03

A4

02

A3

01

A2

00

19
18
17
16
15
13
12
11

015
014
013
012
011
010
A.

DB

Al
AD

A14

26

A13

2

A12

23

All

21

AID

24

A9

25

A8

3

A7

4

A6

5

AS

6

A4

7

A3

8

A2

9

Al

10
20

CE

Y

OE
-

+5V - - 0 PGM

+5V

~

NC

\....../

A12
All
AID
A9

07

A8

06

A7

05

A6

2764-2

04

AS

03

A4

02

A3

01

A2

00

19
18
17
16
15
13
12
11

07
06

as
04
03
010
01

DO

Al
AD

-

CE

-

OE

-PGM

ROMLO
ROMHI

231420-30

5·91

inter

AP-234

.---------------------------------------------------------------------------~

D8- D15

2

A13

23

A12

21

All

24

Al0

25

A9

3

. A8

4

A7

5

A6

6

A5

7

A4

8

A3

9

A2

17

Al

27
WR

20

RAMHI

26

5V
RD

10kn

'-.J

23

A12

All
Al0

108

A9

107

A8

106

A7

105

A6

2

A13

A12

HM6264P

19
18
17
16
15

104

A5

103

A4

102

A3

101

13
12
11

D15

All

D14

Al0

D13

A9

D12

A8

011

A7

Dl0

A6

D9

A5

D8

A4

A2

A3

Al

A2

AO

Al

21
24
25
3
4
5
6
7

8
9
10

-

27

WE

--

20

CSI
26
CS2

5V

22 - OE

10kn

22

\J
A12
All
Al0
A9

108

A8

107

A7

106

A6

HM6264P

105

A5

104

A4

103

A3

102

A2

101

~
~

~
16

D7
D6
05

I - - - 04

~
~
~
~

03
D2
Dl
DO

Al
AO

-

WE

-CSI
CS2

-OE

D7DO

~

ROMlO

\J
14
A5

13

A4

12

A3

11

A2

10

Al

A4

06

A3

05

A2
Al
AO

IAROM

10E>~

0

'"
0

04



ClK

OH

586 ARDY

OH

NC

74lS165
SHIFT/lOAD

586 ALE

231420-32

5-93

AP-234

AO

o

2
1 3

4 6
5 7

8 10
9 11

1214
1315

1618
1719

2022

21 23

2426
2527

2830
2931

0
1

~

34
5
6
7

A14

~

~

11

1314
15

3

16
17
18
19
20
21
22

~

J

23

A16

4

'V
24
25
26
27
28
29
30
~1

A17

32

~

33

.

3B

39
6

'V
40
41
42
43
44
45
46
47

A19

~J

7

'V

...

RAMLO

17

RAMHI

15

14

~~

53
54
55

8

~.~r----'

'V
56
57

~

g~

60
61

62
63

HlDA

~J

~

49
50
51
52

SHE

18

~~

5

34
35
36
37

A18

ROMLO

..::J--

8
9
10

A15

19

9

..::

'V
02
13

46
57

B 10
911

1214
1315

1618
1719

2022
2123

2426
2527

12
ROMHI

11
52

2830
2931

231420-33

5-94

inter

AP-234

Module Addr-dec
Title 'HIB Address Decode Logic
Kiyoshi Nishide
Intel Corp.
"Declarations
PAL1
AD, A14, A15
A16, A17, A18
A19, SHE
HLDA, S2
RAMLO, RAMHI
ROMLO, ROMHI

device
pin
pin
pin
pin
pin
pin

Dec.4,1984'

'P16L8';
1,2,3;
4,5,6;
7,8;
9, 11;
18,17;
19,12;

Equations
!ROMHI = A15 & A16 & A17 & A18 & Al9 &
(HLDA # S2);
!ROMLO = !A15 & A16 & Al7 & Al8 & Al9 &
(HLDA # S2);
!RAMHI = !A14 & !A15 & !A16 & !A17 & !A18 &
!A19 & !BHE & (HLDA # S2);
!RAMLO = !AD & !A14 & !A15 & !A16 & !A17 &
!A18 & !A19 & (HLDA # S2);
End Addr-dec

5-95

APPENDIX B
TSMS PROGRAM LISTING
SERIES-I I I PL/M-86 V2.3 COMPILATIOH OF MODULE TSMS
OBJECT MODULE PLACED IN : f l' TSMS. OSJ
COMPILER INVOKED BY'
PLM86.86 : t'1:TSMS.PLM LARGE f10D1B6 OPTIMIZE(3) SET(S13C18651J

1*****************************************************************************1
*1

1*
/*

Traffic Simulator/Monitor Station Pl'ogram
for 186/586 High Integration Board and
iSDe 186/51

/<
/<
/<

December 17.

1. 0

/<

VeT',

/<
/<
/<

Kiyoshi Nishide

1984

' is added to thp complier call statement.
this source program wl11 be compiled for the i5Be18651.
*1

tsms:
do;
declare main label public •

• IF SBe18651
literally
declare lit
true
lit
lit
false
forever
lit
ISCPSLOCSLO
ISep.LOC$HI
1 it
SeB.BASESLO
1 it
SCnSBASEsHI
lit
lit
eASPORT
BOARD$ADDRESSSBASE 1 it
lit
INTSTYPES5B6
INTSTYPE$TIMERO
lit
INTSeTLsTlMERO
lit
lit
INT$7
PICSMASKS130
lit
PIeSMASK$186
lit
lit
ENABLE$586
ENABLE$5B6$186
lit
lit
PICsEOlS130
lit
EOI$CMDO$130
EOIseMD4S130
lit
PIC$EOI$186
lit
lit
EOI$CMDOS186
lit
PICSYTR$186
lit
TIMEROSCTL
lit
TIMEROSCOUNT
MAX$COUNT$A
I it
C.
lit
ESI$PORT
lit
NO.LOQP3ACK
lit
lit
LOOPBACK

l>'

'literalllj "
'I',
'0',
'while 1',
'OFFFOH' ,

'0',
'0',

'0'.
'OCBH',
'OFOH',
'20H',
'30H',
'OFF32H' ,
'27H',
'OE2H',
'OFF28H' •
'OFEH',
'OEEH'.
'OEOH',
'60H',
'64H',
'OFF22H' ,
'0'.
'OFF20H' •
'OFF56H' •
'OFF50H'.
'OFF52H' ,
'0'.
'OCBH',
'B',
'0';

.ELSE
literally
declare lit
I it
true
lit
false
lit
forever
I5epSLOCSLO
lit
ISepSLOeSHI
1 it
SCnSBASESLO
lit
SCn.SASE$HI
lit
eASPORT
lit
BOARDSADDRESS$nASE lit
INT.TYPES5B6
lit
INTSTYPESTIMERO
lit
INTSeTL$TIMERO
lit
lit
PICSMASKSIB6
ENABLE$SB6
lit
ENABLE$586.186
I it
PIC$EOI$186
1 it
EOI$eMDO$186
lit
EOISCMD4S186
lit
TIMEROSCTL
lit
lit
TIMEROSCOUNT
lit
MAxseOUNTSA
CA
lit
ESlSPORT
lit
NOSLOOP3ACK
lit
LOOPBACK
lit

'1 iterally'.
'1',
'0',
'while
'03FF8H' ,
'0',

",

'0',
'0',
'BOOOH' ,
'Bt80H'.
'12',
'B',
'OFF32H' ,
'OFF28H' ,
'OEFH'.
'OEEH',
'OFF22H' ,
'12'.
'8',
'OFF56H {.
'OFF50H' •
'OFF52H' •
'0',
'8100H',
'I',
'0'.

SEND IF
$IF NOT S3e18651
1* System Configuration POinter *1
declare 5Cp structure
(

slJsbus byte,
unused (,) byte,
iscp$addrSlo word.
iscp$addrSh i lIIord

,

at (OFFFF6H) data (0.

0,

0,

O.

O.

0.

!SCP$LOCSLO,

5-96

ISCP$LOC$HI)i

AP-234

$ENDIF

/* Intermediate System Configuration

Pcint~r

*1

declare isc:pSptr pointer.
lSCp basl!d iscpSptr structure

,

1* set to 1 by CPU before its first CA to 586.
cleOlred by ~86 after reading info from it *1
1* unused *1
scbSo word,
1* offset of system c:ontrol block */
sc:bSb (2) word 1* base of system control block *1

bus" byte.

unused

byte.

),

I . S'I .. tem Control

Block *1

,

declare 5tb structure

status word.
tmd Ulord.
cbl$offset word.
rpa'$offset word.
crc$errg word.
o1lnSeorrs word,
rsc$errs word.
ovrnSerrs word

1* cause(s) of interrupt. CU state, RU state it/
1* int aeks. cu ernd. RESET bit. RU emd */
1* offset of first command block in eEL *1
1* offset of first packet descriptor in RPA *1
1* ere error encQunterd 50 Far *1
1* alignment !!t'roT'S *1
1* no resources *1

1* overrun errors *1

),

1* 82586 Action

Command~

*1

1* NOP *1

,

declare nap structure
status word.
cmd word.
link$offset word
),

1* Individual Address Setup *1

,

declare iaSsetup structure
status word.
cmd word"
linksoffset word,
iasaddre'i'i (6) byte
),

1* Configure *1

,

declare configure structure
status word,
cmd word,
1 ink$offset word.
byte$cnt byte.
info (11) byte

"

1* Multicast Address Setup *1

,

declare mcSsetup structure
status word.
cmd word,
linkSoffset word.
mcsbyte$count word,
mc$address (48) byte

1* only 9 Me addresses are allowed *1

),

1* This transmit command is made of one transmit buffer descriptor and one
1519 bytes long buffer. *1
10

declare transmit structure
'itatus word.
cmd word.
linkSoffset word.
bdSoffset lilaI'd.
destSadr (6) byte,
type word
),

1* Transmit Buffer Descriptor *1

11

,

declare tbd structure
actScount word,
linkSoffset word.
adO word,
ad 1 word

"

1* Transmit Buffer *1
12

declare txsbuffer

(1518)

byte;

1* TOR *1

5-97

inter
13

AP-234

dec la1'e tdl' structuT'1!'
(

status IIIord.
cmd word.

link.offset word.
result WOT'd

I;
1* Diagnose */

declare diagnose stT'Uctur8

14

(

st.tus laIot'd.
crnd word.
!ink$offs.t word
I;

1* Dump Sto1ltUS *1

l'

declare dump structurl!'
(

status ",o1'd.

emd word.
!ink$offs.t 1II0rd.
buff'pt,. IIIo1'd
I;

/* Frame DescriptoT' *1
/* Receive ham. area is made of 5 RFDs.
bufflers. *1

17

5 ABO •• and '0 I:H4 bvtes long

decla"e ,.fd (51 structure
(

status word.
el'. word.
link'offset word.
bd$offllet word.

d.st'.dr (3) 1II01'd.
s!'c'adr (3) word.
tlJpl!' word
I;

1* Receive DuffeT' Descriptor *1

18

d.clare T'bd

(~S>

structurl!'

(

act'count iliaI'd,
nu:t$bdSlink 1II01'd.

adO word,
ild! word,
size word

,;

19

d.c1.,.. rbuf (5) st1'uctU1'1!'
(bufl'fer (1514)

b~hl;

1* global variables *1

declare status 1II0rd.
actual 1II0rd.
c.buf C901 bVh.
dhltx bllte.
ch bllte at (\!ct:buf).
char.count bllte.
rite: e i vlt'count dlllord,
count dlllord.
preamble word.
addnnt:length bvte.
ad.loe: bllte.
crc bvte.
goback bllte.
reset bllte.
delall lIIord.
curt:cb.offst't word.
e:ur..,.ent.frame bllte.
nottransmis1Iion bvte.
stop.count d""ord.
!itop bllt ••
me.count bVtlt.
z bllte.
II bllhl

20

21
22

rltad: procedure Ca. bi c. d.
declin"e 'a. c) 1II0rd.
(b. d. e) pointe'!';
end read;

23
24
25
,.

2

write: proe:edut'e (a. b. c.
declare Ca. c) word.
(b. d) pointer;
end lIIt'ite;

1*
1*
1*
1*

UAA:T status *1
actual number of chars UART transfltrred *1
buffer for aline of chars *1
number base slllitch *1

1*
1*
1*
1*
1*
1*
1*

counter for received f'!'ames *1
counter for transmi tted frames *1
preamble length 1n word *1
address length in hytlt *1
.address loc.ation control of 8259b *1
e:rc length *1
if set. go back to Co'ntinuous Mode *1
re •• t flag *1
delall conunt for tr.anmission delall *1
offset of current command block *1
off'Set of fr.m~ descriptor Just used *1

1*

1*
1*
1*

1* transmit tltrminal 'rame count *1

e) ext.rnall

d) It.ternalJ

5·96

infel®
2.

AP-234

and

C'.it'S!

1* utilit" procedure'5 *1

offset:

2.

procedure (pt!') word;

'* absoluteThis procedure takes
pointer variable (seleeto,,, offset). caluculates an
addTess. subtracts the 82586 sca offset fl'Dm the ab'5olute address.
 to countinue'l. 23. @!ltatusll
call readC1. @c'buf. eo. @actual. @status)j
call cr.lf.

44

46
47

end pause;

4.

skip·

procedur-e by tel

1* This procedure skips all leading blank characters and returns the first
non-blank char-acter.
*1
4.

dec lare i blJte;

50
51
52

i :::: OJ
do whlle (c.buf(i) = • ').
i "" i + 1;

"

end;
return ij

54
55

end skip;

56

read'chal': procedure b .. te.
1* This procedure -reads a line and l'eturns thel' fi-rst non-blank chal'actill'. *1

57

declare i \IIo-rd.

5.
5.
60

call readC!. @c'buf.
i .. skip.
_retul'nC c$buf (i I);

eo.

@actual. @status),

b1

62

read'bit:

procedure b .. te,

1* This procedure reads a bit and l'eturns the value.
63

*1

declare b b .. tei
do forever.
b .. readScharJ
if b '" '1' then l'8turn 1;
else
if b = '0 I then return OJ
else
call writ.fO. (tC' Entel''' 0 01' 1 ....:> '). 20. @status);
end.

64
65
66
6.

••
70

71
72

end read.bit.

73

.. es:

procedure b .. te;

1* This procedure reads a chal'acter and determines if it is

5-99

oil

VC .. > or NCn).

*1

inter

AP-234

7'

2

75
77
79
BO
BI

2
3
3
3
3
3

B2

3

endl

93

2

end ,,_5;

7b

do flor'eveT'1
II • ,. ••• tch.T';
if (b ... 'V') 01" CII .. 'V') then 'I"etu1'n tpue.

e1s.

i'

cha"Stol'nt:

B.

(b •

'N') 01' Cb .. 'n') then ... tu1'n fa1 •• ,

el ••

p,"ace-dure CC)

b"t.,

/. Thh procedure conva,.t" • Itvt. of ASCU int ••• ,. to an int •••r.

.••

B'

2

.9
90
91
92

2
2
2
2
2
2

93

2

*'

if ('0' <.. c) and Cc <- '9') then "eturn Cc: - 30HJI
el ••
ifC'''' ( ... c) and (c <- 'F') then ,..turn (c'- 37H),

.he

if C'.' ( .. c) and (c
els8 ,.eturn OFFHi

<- ',')

then 'return (c - S7H) ,

end ch.-,.Sto"nt,

,.
,_ This procedure converts an interge"

<

OFFFFFFFFH to an .""." of ASCII

cod ••.

Input v."lab 1•• are:

valu"e - integer to be cDnv.,.t.d,
b •••• numbe", b ••• to be us.,d for conve,.sion.
ld • leading chlll,.act.,. to be filled in.
buf.d" .. bu'''e" _ddTes. of the aTTa".
width. sh. of aTTa".

*'

..

2

9b

2

97
99
100
101
102
103
100
10.
lOb
107
lOB

3
3
3
3
3
2
2
3
3
3

109

2

2

d.claTe valul dWOTd.
bufadl' pointeT,
(i. J. ba •• , Id, width) III"t ••
chnl baud buhdl' (1) b'l1h'
do i • 1 to width,
J • valua ",ad bas.;
:if J < 10 then cha,., (width - U • J + 30..41
ah. chaTS (width - U • J + 37H1
value. v.lu. , ba •• ,
end.
i

.0,

do while chaTS (1) • '0' and i
chaT' ( i ) • ldl
1 • i + 1;
and.
chaTtcount • width - i.

<

width - 1;

110

*'

, . An int',.T at (.ahctoT of wtptT): (offs.t of .... ptl' + distancat is pTintad
as a 4 digit he .. d.c i",.1 numbeT.
III

2

112
113

2
2

II"

2

d.elaTa ch .... s{4» b"h,
",.ptT pointaT,
dtst.nce b"t!!.
W based .... ptT

(1)>

WO ... dl

call int'to$asci(IIICdistancet, 16. '0' • • chaTsCOb 4»1
call lI..rit, (0 • • ch."s(O). 4, IIstatu,),

lIl... ita'int: Pl'OC.dUT.(dw. 1:»;

II>
lib

2

117
liB
119
120
121
122

2
2
3
3
3
2

123
12"
12.

3
3
3

126

2

, . An int".T Cd .. » is p"intad in h •• adeci.at
dacl ..... dill dlllo ... d.
chaTS (10) b"t ••
t b"hi

(t

-

1) 0'" in d.ci •• l ct • 0), . ,

:if t than

d.,

call intetoea.ci(d .... 16. O• • ch.".(O). B)i
call ..,.ita(O, IIch.",CS-cha,.ecounU. cha,.ecount • • ,tatus)'

call int.totascUd .... 10. O• •cft.,.sCO), 10).
call ..,.itaCO. Icha,.sCl0-cha"'cDunU. ch.,.ecount, IstatuI"
andl

127

128

2

129
130
131
132

2
2
2
2

d.UaT. dill dwol'd,
call
call
call
call

...,.ih'inttd ..h 0);
w,.ittCO. 11(' ('), a. estatus),
w.,.U •• inttdw. 1 'I
...,.It,CO. e, 'H) '), 2. 'status),

5-100

inter

AP-234

end out.dec.hell

133
13'

'*

This procedure tata. II point.,. variable. converts i t to ..
and prints i t in haxadecimal.
./

dacl.,..

13.

2

••
•

offset.

ward,

Cll11I111'U.(O. 1(' at '), 4, t:st;.tUS)1

of'uUw'ptr)J
clill out'word (lw, 0),

l1li -

call writ.(O. a('

'J, 2. astatUS)1

,.0

end 1III1-th'dfnt,

'"

write •• ddr ••• : procedure

'* Ttlh
proc:adu"e
"lI!'lacto1': off •• t'

(ptT)'

*'

t ....... pointer variable and prints i t 1n th.,

".

dec I.". (pt,.,

fOT'm.t.

ptr'loe)

pointel'.

III b •• ed ptrSloc (2) lIIIordl

•
,'5
'"
•
•
'"

143

2
2

I ••
"7

t~p.

lII'ptr point.,.,
III

13.
137
13.
13.

B2~B6

2

ptr'loe

~

'ptTI

call DutSlllordrl..,(U.

P)'

call writ.,rO. ee': ') • • • • status"
call Dut'lIIordUf:w(Ol. all
call "'rit-·rO, @(' 'J. 1. I!status),

I ••

print'wds:

'* This

pt'ocedu".CIII'pt1", no'lIIords),

procedure prints no'lIIords number 0' words still'rting at w.ptr.

*1

dec hire IIISptt;' p01ntar.
e1. no.word.) bl,ltal

100

i f no.words
d.,

151
I ••
103
IS'
lOS
10.
157
10.
10'
,.0

<) 0 than

call crSUI
do i • 0 to noSUfol'ds - li
call outSwol'dC..,sptl'. 1)1
if i
0 then
call IIIrita"o".at(..,.ptr)1
caU crfolfj
endj

=

,.,

printS'Str: procedure {'Str.ptr.

I ••

1* This

len},

prints len number of buta. starting at 5t,..ptr. *1

a.clare- Clen, it but.,
chari (2) b"te,
t.trSptr pointar.
str basad strSptr (1) byta;

,.3

i f len <> 0 than
do i = 0 to Clan - 1);
call intStotasciClitr(1l, 16. '0', Ichar$(O)' 2)j
call ..,rite(O. Rettar.CO). 2 • • status)i
call writeCO. t!C'
'I. 2. @statu.),
and I

I.'
I.'
I ••
,.7
I ••
I.'
170

171

pro~edure

t:,a11 t:rSl"'l

•

17.

1* Tt\h procedure prints cnt number of buffer contents starting at ptr. *1
173

17.
175
17.
177

17.
17.
,.0

,.,

I ••
,.3
I.'
I ••
,.7
I ••

•
•
2
3
3
4
4
4
4

•

3
3
3
3
2

I ••
,.0

'"

"2

daclara ptr point"",
bt buad ptr (1) byh.
(i, JI buteo
cnt ..,orOj
if cnt )0 16 then
do;
i • • br(cnt. 4) - 11
do J - 0 to iI
call writa •• ddressClbtC16*JIII
call prints.tret!bte16*J)' 16),
i f (J ·201 01' eJ :II 40) 01' (J :II 60) or eJ :II SOl than
call pausa,
andl
i :II t + Ii
if cnt-16*i <> 0 then call writaSaddra.sCltbtCU.*i),.
c .. ll printSstrClbt( 16*1). cnt-16*i II

d.,
call w1'UeS.ddrauC.btCO).
call p1'intS.trelbt(OI. cnt)i

2

5-101

infel®
,.3

AP-234

r.~d$int:

pT'ocedure (limit) dlllord!

1* This procedure ,..ads tnt!'geT' characters and forms an integ"".
If the
i nteg e1' is b 1 gg el' than '1 im! t' or an overf 1 0111 IH"rO,. i ~ ene ountarred. th en
.an rrror mes'5age is printed.
*1
deela,.. (\lid,

'"

11.
2
3,
3
3
3
3
3
0
4
4
0

"5
"6
197
,.8

'"

200
201
202
204
205
207
209

III'd.

IIIh '" OJ

<= 15i
if J :> 9 then hex = true;
i f not dover then
if wd > 429496729 then dove1' ,., true;
else if- (\lid" 429496729) and (J ,. 51 then dover = true;
bid = lIId*10 + Ji
if not hover then if IIIh ,. OFFFFFFFH then hovel' "" true;
IIIh = ",h*16 + Ji
i = i + 1;

I

J = charStoSintlcSbufCi».
eond;
if (leSbufli) <:> 'H') and leSbufti) <> 'h') and IcSbuf(il <> ODH) and
leSbufli) <> OAH) and (cSbufli) <> ' '»
or ( i EI k) then
call writelnlO. (!(ODH. OAH. ' Illegal characteor'), 20, @~tatu!l);
else
do.
if (cSbuf(O .. 'H') or (cSbuf(i) "" 'h') then hex = tT'ue;
if hex then
do.
if not hoveor and (wh <"" limit) then T'eturn whi
end.

220
222
223
224
226
227
228

...

el~e

if not dover ano Cwd <= limit) then return ""d;
call lIIritltInCO. (!CODH. OAH, ' The number is too big. '), 25,
\!status I i
call ",rite-(O. e(' It has to be less than or ellual to 'I, 36.
@statusl;
call outSdecSl\u(limitll
call ",rite-InCO. @('. 'I, 1. (!statusli

230
231
232
233
234
235

lind,

catl IIIrite(O.

@('

Enter a number "'"..> 'I. 20, @status);

endl

236

end readS inti

"

pul;.address:

238

2

declare where pointer,
ei. J. m. err) b"te.
addr b,ned whe-re (1) bvtel

239
240
241
242
243
244
245
246
248

2
3
3
3
3
3
4
4

...

260
261
262
263
26.
26.
266
267

b~te,

J = char.to$intlc.bufli»j

218
219

24'
290
051
253
254
255
256
257
058

hover)

do IIIhile J

210
213
214
215
216
217

237

wh. limit) dlllord.
J. k. done. hex •. dover.

do foreve,.,
call T'eadC1. @c$buf. eo. @actual. IhtatusJ;
i. k "" skip,
hell done. dovel', hover = false;

•
5
5
5

5
5

••

=

end.

if not err then
dOj

m = c$bufeil.
if (m'" OOH) or (m"" OAHI or (m"" 'h') or (m = 'H') or (m '"
then return;
end,
call IIIritelnCO. @IOOH, OAH. ' Illegal character'), 20. @statusJi
call write(O. @C' Enter an address in Hex "'=> 'I. 29, @statusJi

••
•

2

end.
end putSaddress.

percent:

268

in hexadecimal to the specified

do forever;
err = false;
call read(l. @:c$buf. 80. @actual. @statusJ;
i
skip;
m .. address.length,
do IIIhile em <> 0) and not err;
J .. charstoSintCcSbufei»),
if J - OFFH then err" truel
else
do.
addrCm-1) "" shlCJ' 4);
J ." charstosintCc$buf(i+1) I;
iF J "" OFFH then err = truel
else addrCm-l) = addrlm-l) or J;
end;
1 = i + 2;
m "" m - I.

4
3
3
0

3
3
3

procedure(lIIhereli

1* Thi!; pT'oeedure puts an addT'ess typed
location 'where'. *1

pl'ocedure.

1* Tni .. procedure calculates .and prints. network percent load genel'ated

b" this station.
The eq,uation used in this procedure was obtained
from actual measurements. *1
26.

2

270
271
273
27.

2
2
2
2

declare i word.
CJ. k) dword.
pcent (3) b"te.
J = (tbd. act$count and 3FFFHJ*B.
if not adSloe then k = {2*.address$length + 2 + crc .. preamblel*Bi
else k = (crc + preamblel*81
if de-l.a" <) 0 then

.IF NOT SDCIB651

5-102

•

')

AP-234

.ELSE
275

SENDIF
27.
.IF NOT SBC186!H

i

:II

low«(1000*CJ + k)/(1810 + Ie + J)ll

.ELSE
lOIllHIOOO*CJ + 1111/(2026 +

II +

Jlli

sEND IF
call intttoSasciCi. 10. O. @:pcentCQ).
call write CO. @pcentCO), 2. @:'jt.tU~)i
@.. tatus);
1. (!status);
2. (!5tatus);

277
27B
279
2BO
2Bl

3);

call write(O. @(', ' ) , I.
call writeCO. @pcent(2),
call writ.lnCO. l!:(' i:,'),

2B2

end percent;

2B3

printSnetworkSaddr:

procedure Cptr),

1* Thi!l station's address is printed with its least significant bit

in the most right position.

*1

dec lare ptr pointer.

2B4

addr based ptl'

char

(1) byte.

bvte-.

(b)

b",te.
to address.length;
chari i-1) ,. addr(addressSlength-i);
i

2B'
2B.
2B7
'BB

2
3
3
2

do i

.. 1

end;
call printSstr(@chal'(O),

2B9

end print$networkSaddrl

290

printSparameters

addressSlength);

procedurel

1* This procedure prints trOlinsmission parameters.

292
293
294
295

*1

declare w dword.
stgs (6) bVtel

291

2
2
2
2

29.
297
29B
299
300
301
302
303
304

call write(O. !:(' Destination Address: '). 22. @status);
if not adSloc then
call pr i ntSn etwor kSad dr C(!transmi t. destSadr (01 );
el se
call pr i ntSne twor kSad dr (@txSbuffer(O) ) i
if not ad'loc then
w -""
Ctbd. actScount and 3FFFHl + addl'essSlength * 2 + 2 +
else w "" (tbd. act$count and 3FFFHl + crci
call write(O. @(' Frame Llltngth: 'I,
!htatusll
call writeSint(w, 011
call writeinCO, (!(' bytes'), 6. @status);
call write(O, @(' Time Interval between Transmit Frames: ').
if deliilj ()
then
dOi
SIF NOT S3CtB6S1

1'.

°

w = 1810 + Cdouble(delay) -

1)

* ::;;

= 2026 + (doUbleCdelav) -

1)

* ::;;

40.

@statusl;

$ELSE
305

III

SENDIF
call intStoSasci(w, 10, D. @stgs. 611
if w )= 10000 then
dOl
call writetO. @stgs(O)' :0':. I!status)1
call writetO. (!('. ' ) , 1. estatus)i
call write(O, @stgs(2). 2, @status);
call writeinCO, @(' miliseconds'), 12.

30.
307
30B
309
310
311
312
313
314

@status);

do;
315
31.
317
31B
319
320
321

4
4
4
4
4
3

COIill
call
call
call

writeCO. @stgsCO). ::;, @st .. tUS)1
writeCO, @C'. '), 1. estatus);
write(O, I!stgseS), 1. I!status),
writelnCO, @(' microseconds'), 13.

estatus)i

end;
end;
$IF NOT SBCIB651

call writeln(O.

11{' 1:S9.4 micl'oseconds'),

19,

(!status);

172.8 microseconds'),

19.

@status);

$ELSE
call writeln(O,

(!('

SENDIF
322

2

call writwCO.

(!('

Network Percent LOOlid gener.ted bV this station: 'I, 49.
@status),

5-103

intel®

AP-234

323
32'
325
3.7
32B

call ptH'cent;
call IaIriteCO. @(' Transmit F1'ame Terminal Count: '), 32. @statusJI
if' stop then call IIIriteSintCstop$cDunt. dhel)i
else call IIIriteCO. @:('Not Defined'). 11. @:status),
call CT"U,

32.

end

p1'int'~aT'ame'te"si

print$scb:

330

procedurel

1* prints the 5eB *1

331
332
333

call tIIritelnCO.

call
2

OAH.

,***

SY5tem Control Block

*,,*'),

30.

status. 8)1

end p,.int'scbi

waiJ_scb:

334

@(ODH,

pl'intSlllds(~scb.

procedure;

1* This procedu1'l!' pl'ovids a wait loop foT' the Bea command \&lord to
become cleared.
*1

declare i word.

335
336
337
33B
33.
340
341
34.
343
344
345

2
2
3
3
2
2
3
3
3
3

346

2

i = 01
do while ('leb. cmd <> 0) and
i = i + I,
endl
i f 'leb. cmd <> 0 then

d.,

start$timerO:

348

,. Wait Time" '),

15. @:status),

procedure.

end startStimerOI

isr:

"0

BOOOH);

end.

1* 80186 timerO is started. */'
output nIMERO'CTL> '" OEOOOH;

2

<

call IIIriteCO. @(ODH, OAH.
call IIJrite'int(i. 0);
call crslf;

347

34.

(i

procedure interrupt INTtTYPE$586 reentrantl

1* interrupt service routine for 82::58b interrupt *1

301

declare i

bl.1te;

1* Enable 82586 Interrupt *1

$IF SBC18651
352
353

2
2

output (PICSEDJS130) "" EOISCf1DO$130l
enable;

.ELSE
output (PIC'EDl$18b) .. Em'Cf1DO'18b.
enable;
.ENDlF
1* Frame Received Interrupt has the highest priori til */

354
355
356
357
35B

35.

360
3.'
3.2
3.3
3.'
3.6
3.7
3.B

2
2
3
3
3
3
3
3
4
4
4

if (scb. status anti 4000H) ;; 4000H then
ti~;

disable;
5cb. cmd ' c 4000HI
output (CA$PORT) .. CA,
call wait$scb.
if rfdecurrentSframe), status = OAOOOH then
do.

rllcllive$count = receive.count + 1;
current$frame "" current$frame + 1;
if current$frame .. 5 then currE'ntSframe = 0;
end,
return;

4

3
3

3 ••
370
371
372
373
37'
375
370
377
37B
37.
3B1

2
2
3
3
3
3
3
3
3
4
4
4

3B'
3B3
3B4
3BS
3B6
3B7
3BB

5
5
5
6
6
6
6

end;
i f (scb. status and 2000H)
do;

= 2000H then

disable.
seb. emd '" 2000Hi
output(CA$PORT) = CAl
call laIaitSscbl
enable;
if (transmit. status and QAOOOH) '" OAOOQH then
do,
count"" count + 1;
if (stop and (count"" stop'count»
then return!
else
do;
transmit, sta'tU!l .. O.
i f deJall = 0 then
dOl

disable;
scb. cmd .. OtOOHJ
output(C'AtPORTl = CA.
call lIIait'scbj

5-104

@status)j

intel®

AP-234

return,

38'
3.0
3.1

end.
else
do;

390
3.3
3,4
39.
3.0
3.7
3.8
3 ••
400
401
400
403
404
40'
400
407
408
40.
410
411
410
413
414
415
410
417
418
41'
420
421
422
403
424
425
420
427
428
42.
430
431
432
433
434
430
43.
437
438
43'
440
441
442
443
444
445
44'
447
448
44.
4'0

call startstimerOi
T'eturni

0
0

end;

•

4
3
3
4
4
4
4
4
4
4
3
3
4
4
4
4
4
4
4
4
3
3
4
4
4
4
4
4
4
4
3
3
4
4
4
4
4
4
4
4
3
2
2
3
3
3
3
3
2
2
3
3
3
3
3

end;

end,
i f Itt'ansmit. status and 0020H) .. 0020H then
do;

transmit, status'" OJ
disablel

scb. cmd .. DI0CH;
output (CASPORT> .. CAl
call lIIaitSscbi

return.

and,
if

ItT'ansmit. status and 0400H) -

0400H then

do.
call b,lriteIQ. @(ODH • • No Carrier Sense!'. DDH).
transmit. status = 0,
disable.
lOeb. cmd = CI0CH.
output (CA$PDRTI = CA,
call LIIait$scbi

20.

@status);

return;
end.
i f (transmit. 9tatus and 0200Hl = 0200H then
do;
call IlfriteCO. (!IODH. ' Lost Clear to Send!',

DDH),

22.

@statusl;

transmit.statu5 = 0,
disable.
scb, cmd = DIOaH.
output (CA$PORT> '" CAi

call lIlaitSscbi
"etut'n;

end.
i f (transmit. status and DI00H)

= 0100H then

do.
call lIIT'iteCO. @CODH • • ,DMA UndeT'run!',
tT'an~mi t. status = 0,
disable.
5cb. cmd = 0100H.
output (CASPORT) ,. CAt
call lIIait$scb.
T'eturnJ

ODH).

16.

end.
end.
i f Cscb. status and BOOOH) = BOOOH then
do.
disable.
scb. cmd '" BOOOH.
output (CASPORT) = CAl
call waitSscb.
end.
if (scb. status and 1000H) .. 1000H then
do;
disablltj
5cb: cmd = IOOOH.
output eCASPORT) = CAl
call lIIait$scbi
call lIIT'iteCO. @CODH. 'Receive Unit became not readtJ.

@status).

ODH). 33.
@status);

451

end,

452
453
454
4..

if T'eset then
do.
if iscp. bus., then
do;
call writelneO. @(ODH. OAH • • Rl'set failed. 'l. 16. @status);
dhablei
5cb. cmd = OOBOH.
output eCA$PORT) .. CAl
call waitSscb.
output eCA.PORT) = CA.
call lIIritelnCO. @:C' Software Reset EXecuted!'). 25. @:status).
end.
else T'e5et "" false,

45.
457
4 ••
45'
400
401
400
403
404
465

end.

40'

end i5r;

467

txsiST':

procedure interrupt INT$TYPEsTIMERO.

1* interT'upt survice routine for B0186 timer interrupt*1

468
46'
470

2
2
0

sc b. cmd = 0100Hi
DutputCCASPORT) '"" CAt
c~ll waitS5tb;
.. IF SDC18651
DutputCPICSEDU130) = EOUCMD4$130;

471
472
473

enable.
Du~putCPICSEOUI86)

= EOUCMDO$186i

SELSE
Dutput(PICSE01S186) = EOUCMD4S186J
SEND IF
474

2

end t.Sisr;
.IF SBCIS651

5-105

intel®
475

AP-234

iST'S7'

procedure interrupt INT.7;

1* The 80130 generates an interrupt 7 i f the original interrupt "1s not
active an" more when the first interrupt acknowledge is received
*/

call writeCO.

476

i!(ODH.

'Interrupt 7'.

DOH),

13.

(l!status);

end lsT'$7;

477

'ENOIF
read$blJte: procedure (k) byte;
dec: lal'e k word;

478
479

call write(Q. @(ODH. DAH,
call outSdecShelC(k);
call UlriteCO. @(' : = ) ' ) ,
return readSintCOFFH);

480
481
482
483

Enter bllte
5.

'l.

14.

@status);

(!statuslj

end readSbyte;

484

in1tSl86StimerO:

485

procedure;

1* TI'I15 procedure initializes the 80186 timer O.
declare i

486

*1

byt.;

$IF SBC18651
487
488
489
490
491
492
493
494
495
496
497

=

outputONTSCTLSTlMERO)
8;
call writeCO. @eODH. OAH, " Enter a dela., count "':::) 'l, 27, @statusl;
delay c read$int(OFFFFH);
i f (delay < 100) and (delay <> 0) then
do;
call cr$}f;
call cr$lf.
call 100p$char(35, ' . ' ) ,
tall write(O, C!(' WARNING 'I, 9, Itstatusl.
call 100p$char(35. '.'1;
call writeln(O. \!:(OOH, OAH, 'A delay count between 0 and 100 may be very
'dangerous when this station starts'), 80. @status);
call writeln(O, C!( 'to receive many frames separated only by the
'IFS period (9.6 microseconds). , I. 75, C!statusl.
call writeln(O, @('If this station never receives a frame, then
'ignore this warning. ' I. 65, @status);
call loopSchar(79, ' . ' Ii
end.
output(MA)($COUNT'A) "" delay!
call crSlfi
output(PICSMASKS1861 "" 3EH.

2
3
3
3
3
3
3

498
499
500
501
502
503
504

SEISE
output(INTSCTL$TIMERO) '" OCH.
call writeCO, @(OOH. OAH, • Enter a delay count
delay'" readSint(OFFFFHI.
outputCNAX$COUNTSA) '" delay;
call crSlf.
output(PICSMASK$1861 ::I ENABLE$586S186i

"''''> ').

27,

@statusl.

SENOIF
initS186$timerO.

505

end

506
507

setup$iaSparameters:
declare i byte.
call write(O,

508
509
510
511
512
513
514

procedure.

@(OOH. OAH. 'Configure the 586 with the prewired'
, ' board address "'=:> '), 57. @status);
if' yes then
do i = 0 to addrelOsSlength - 1;
iaSsetup. iaSaddress(il
inputC130ARO$AOORESS$I3ASE + 10 - 2
il.
end;
else
do.
call write(O, @(ODH, OAH, 'Enter this station"s address',
, in Hex ==) , l. 43, @status).
call put$address«ha'$setup ia'addresseO) Ji
end;

*

3

515
516
517

end setup$iaSparameters;

518
519

se tup'me'parameters:
declare (J. k. done)

520
521

522
523
524
525
526
527
528
529

530
531
532
533
53'
535

J "" 0;
call writeln(O.

prl'lC edure j
byte;
@COOH,

2
2

done :c false;
call wl'ite(O,

2
3
3
4

do while not done!
if yes then

••

••

dOi

OAH,

'

You can enter up to 8 Multicast Addresses, 'I,
45, @status);

Would you like to enter a Multic:a!lt Address"?',
(Y or N) ==> '), '59. @:status);

@('

*

k = J
addreSs$length;
J = J + I.
call crSlf'.
ifJ=9then
dOl

5

call

~rite(O,

@('

You already entel'ed 8 Multicast addresses. '),
43, @statusl;

done '" tru.i
end;
else

do.

5-106

intel®

AP-234

call write(Q. @(' Enter d f1ulticast Address ===:> '1.31. @statusJ,'
call put$address(@mcSsetup. mc~addre5S (k) I.
call write CO. @(ODH, DAH. ' Mare Multicast Addresses?',
, ty or Nl ==) 'J. 42. @status"

:::36
537
538
end;

53.
540
541
54'
043
545
546
547
548
54.

end.

elsl! done:: tru('i

end.
if J '" q then J '" J - I.
mcScount c addressSlengtll
Ji
mc$setup. mC$byte$count ::: mc$count;
call writeCO. (!(ODH, OAH. ' You entered 'I. 15. @statusl;
call writeSintt J' 0);
call writelntO. @(' Multicast Address(es). 'I, 23. @'itatus);

*

,,0
51! tup$c cnf i!l ur t"$par.1lmeter 50:
dl'clare (k. J) byte;

551
552

configure byteScnt :: 11;
configure, info(O) '" 8;

553
554
555
556
557
558
55.
560
561
562
563
564
565

566
567
568
56'
570
571
572
573
575
576
577
578

57'
580
581
583
584
587
58.
5.0
591
592
593
594
595
596
5.7
598
599
600
601
602
603
60'
605
606
607
608
60.
610
611
612
613
614
61S
616
617
618
619

620
621
622
623
624
625
626
627
628
62.
630

p roc ed ure;

configure Info(l) :::I
configure. info(2J =
configure. info(3) '"
configure. info(4) ~
configure. info(5) ::
configure. 1nfo(6) '"
configure info(7) ::I
configure. inFo(8) ;;
. configure. info(9) =
J = 0,
call writeCO, @(OOH,
, values. " OOH,

2
'3

•

OJ
26H;
OJ
96J

0,
OF2H;
0;

0;
64;

do wh ile yes;
do while J ., 0;
call write{O,

OAH.
OAH.

@(OOH,

Configure command is set up For default',
Do ~ou want to change any b~tes?',
, (VOl' N) ==) ' ) , 9Q. @status);

OAH.

' Enter bl4te number

(1 -

11)

'I, 34,
@statusl;

"'=)

J = read$int(11);
if J = 0 then
call write{O. @(ODH.

OAH, ' Illegal byte number'). 22, @:status);
endJ
if J = 1 then configure. byteScnt : I reaHibyte{J);
ehe configure. info{J - 2) = read$byte(J);
J :: 0;
c:all write(O, \!: 'I. 32,
@:status);
end;
preamble = ~hl(l. shr«configure. info (2) and 30H).
address$length ;;; configure. info(2) and 07H;
iF address$length "" 7 then address$length = 0;
ad$loc = shr{(configure. inFo(2) and 08Hl. 3),
if shr( (configure. info(7) and 20H), 5) then crc = 2;
if shr«configure. info(7) and 10H). 4) then ere = 0,

4)+\);

else crc = 4;

end setup$eonfigure$parameters;
setup$tx$parameters: procedure;
declare (size. i) wordl
do forever;
no$transmission = false;
transmIt. bdSoffset = offset «!tbd. aet$countl,
if not adSloc then
do;
call write(O. @(ODH. OAH.
, Enter a destination address in Hex ==> '), 42. Qstatus);
call put$.ddre'is(E!:transmit. dest$adr{O»;
end;
else call writeln(O, @(' 82586 is conFigured to pick up OA. IA. '.
, and TYPE from TX buffer. 'l. 64. @statusl;
call cr$lf;
if not ad$loc then
do;
call write(O. @(ODH, OAH. ' Enter TVPE =.:(> '), IB, @:statusl;
transmit. type:::; readSint(OFFFFHlJ
end;
c.ll writeln(Q, (!(ODH. QAH, , Ho,,", many byte'i of transmit data?'), 35,
@:status)i
CollI wri,te{Q,  ' l . 20. (!status);
:::I
read$int(1518l,
tbd. aetScount "" size or BOOOH;
if Sill! <:)
then
do;
tbd. link$oHset '" OFFFFH;
tb-:t. adO = offset UttxSbuffer(O»;
tbd. ad1 '" 0;
do i = 0 to 1517.
btbuffer( i ) '" 1;
end;
call writeln(O.
(!(OOH. OAH. ' Transmit Data is continuous numbers CO, 1. 2. 3. '.
,
l'). 57. @:status)'
call write{O. @(' Change any data bytes? (V or N) ==) 'l, 37.


@status);

39.

@status);

end;

else stop = false;
call cr'lf;

cal1 cr'lf';
call printSparametersj
call writelO. (!(ODH, DAH,

' Good enough?

CY or N)

29,
@statu5)j

==)

').

46.

@statusli

23.

@:status);

if yes then return;
end;

651

end setup$tx.parameters;

652
653

loop$char: prOcedUTi! (i.
declare (i. J. k) byte;

J Ii

do k ::: 1 to i ;

654
655
656

call writeCQ.

@J'

1.

@status);

end;

end loop$char;

657

65B

init:

659

declare

procedure;
i

blJtei

call cr.1I;

660
661
662
663

2

2
2

2

call loop'chaT'(13. OAHl;
call loop'cha,,(15. ' 'l;
call 1I.IT'1hlnCO. (!,( 'TRAFFIC SIMULATOR AND MONITOR',
, STATION PROGRAM 'l.
call loop'chad7. OAHl;
call lI.IT'itelnCO, @:(ODH. OAH. ' Initialization begun'l.
call c"Slf;
T'eset "" true;
cu"Scb'offset "" OFFFFHJ
output (ESUPORTl "" NOtLOOPBACKj
output (ESI$PORT l ;:: LOOPBACK;
dhex "" false;
1* set up interT'upt logic *1
call setSinterrupt(INTSTYPE'586. i'sr);
ca 11 setSi nterl' up t (INT$TYPESTIMERO. txsi sr)

672
673

j

SIF SBC 18651
call setSinterrupt(INTS7. is,,7).
output (PICSMASKt130) .. ENABLE$586$l8b;
output (PICtEOIt130l z:;: EOUCMDOS130;
output (PICtEOUI30) "" EOUCMD4s130J
output (PIC$EOU186l ::::< EOUCMDOS186.
output (PICSVTRt186) "" 30H;

67.
675
676
677
67B
679

SELBE
output CPICSEOI$186) "" EOUCMDOS18b;
output (PICSEOIS186l :c: EOI$CMD4S18b;
output (PICSMASK$18bl "" ENABLES58b;
SENOIF
1* locate iscp *1
2

iscpspt"

Cf

ISCPSLOC$LO;

1* set up field!! in ISCP *1
6Bl
6B2
6B3
6B4

49.

call write (D. @IQDH. DAH. ' Enter  'l,
stop.count :: read$intCOFFFFFFFFHlj

64B
650

6BO

'l.

stop::: true;

641
642
643
644
645
646
647

664
665
666
667
66B
669
670
671

CY or N)

i f yes then
do;

2
2

2
2

iscp. bus" "" 1;
iscp.st:babCO) ;:: SCBtBASEtLO;
u(p.ubSbCl) "" SCBSBASE$HII
iscp. scbao
offset «!scb.status)J

=

1* set up SCD *1
6B5
6B6
6B7
6BB
6B9
690
691

2
2
2
2
2
2
2

scb. status s: 0;
5cb. cblSoffset ::: offset (@:diagnose.status);
scb.T'paSof'f'set:: offset (@"f'dCOLstatus);
5cb. crc$errs "" OJ
scb. alnt-err'5
0;
scb. "sc$errs ::: 0;
scb.ovrn$errs :: 0;

692
693
694

2
2
2

diagnose. status
0;
d iagnos('. cmd
7;
diagnose. link'offset :. offset (@conFigul'e. iiitatus);

695
696
697

2

=

1* set up Diagnose command *1

=

=

1* set up CONFIGURE command *1
2
2

configure. status = 0;
configure. cmd .. 2;
configure. linktofFset "" oFfset Uha$setup. status);.

5-108

inter
6 ••

2

AP-234

call setup'configure'parametersJ
1* .et up IA command

*'

la.setup. status = o.
iaS •• tup. c.md '" 1;
i.S.etup. linkSoffsil't '" offset (@mcSsetup. 5t.tu5)'
call setupsiaSpar.ametel's.

700
701
702
703

,*

set up

Me

command

*'

me'setup. status .. 01

704
705
0706
707

IIICS.,tup. cmd '" 8003HI

me.setup. linkSofhet .. OFFFFHI
call setup'me'parameters;

/. set up one transmit cb linked to itself *1
tl'ansmi t. status "" 01
call writ.lnIO. I!(ODH. DAH • • Would ,,",au like to tl'ansmit?'). 30. Clstatusll
call writ.IO • • ,. Enter a Y 01' N =.. > 'I, 20. \!status),

708
70.
710
711
712

if ues then

-

dOi

713'

tr'llnsmit. cmd "" 8004H,
t1'ansmit. link.offset .. OFFFFHI

714
710
716
717
718

tl'an.mit. bdSoffiset -

offset IC!tbd .• ct$countl;

call n'tupstlsparametersi
end;

else no.transmis5ion ... true,
1* initialize receive packet area *1

do i

= 0 to 3;
rfd (i L status::: 0;
rfd(i).elSs" 0;
,.fd(1). link$offset "" offset (8rfdl1+1). Gt.atus);
rfd(1). bd$offset = OFFFFH;
rbd(i). ilct.count ~ OJ
rbd(tLnutSbdSlink = offut (IrbdC1+ILactScDunt);
rbdCiLadO = oflfut (@rbufC1).bufhrCO»J
rbd(iLadl .. 01
rbd(i).lIize :0 1500J

71.
720
721
722
723
724
725
726
727
728
72.
730
731
732
733
734
730
736
737
738
73.

2
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2

end!
rfd(O)'
rfd(4).
r'd(4).
r'd(41.
rfd(41.
rbd(4).
rbdC4J.
rbd(41.
rbdC41.
rbdC41.

740
741
742

2
2
2

count ... 01
receiveScDunt = 0,
current$frame = 0;

2

bdSoffset ... offset (@rbd(OL.ct$counth
status = OJ
el$s = OJ
linkSoffset '" offset C@rfdCO)' status);
bdSoffset ... OFFFFHi
act'count .. 01
nut.bd$link = of-fset UtrbdCOL act$count),
adO = offset «(!rbu,(4L bu'ferJO»;
adl = OJ
5118 ." 1500;

1* initialize counters *1

1* issue the fir5t CA *1
outputICASPORT) '" CAl

743
744

end initi

745

printShelp:

procedure;

7.6
747

2
2

call writelnCO, @:(ODH,
call writRlnlO, @(ODH.

748

2

call writelnCO. @I"' P -

74.

call writelnCO.

@e ' L -

750

call writelnCO.

a(' A -

751
702
753

2

70.

2

755
756

1
2

2
2

call writelnCO. @(' Z call ",ritelnCO. @c' Y call wriceln(O. @(' E -

OAH,
OAH.

'Commands are: '),
' S - Setup CD

@statusli
D - Displillj RFD/CB').
45. (lstatus);
Print SCD
C - sca Control CMD'). 44,
@.statush
ESI Loopbaclt On
N - ESr Loopback Off'). 45.
@status),
Toggle Number Dase'). 23.
@statu'i)1
Clear TI Framlt Counter'), 27. Clstatus);
Clear RI F,.ame Counter'). 27. i!statusl,
elit to Continuous Mode'). 28, @status),
16,

end print.help'

enterSscbScmd: procedurlH
declare i bljtel
1* enter a command into the SCS *1

757
758
75.
760
761
762
763
76'
765
766
767.
768

2
2

2
3
3
3
3
4

•
•
4
4

call cr$l',
if !Dcb. cmd <> 0 then
dOi
call IIIritelnCO. @C· SCS command 1II0rd is not cl_ar_d'i. 32, @statusJ,
call IIIrlte(O, @:(' TrV a Channel Attention? (V 01' NI
'I.
39. @status)'
if ves then
dol'.
output CCASPORT) = CAJ
call IIIriteln(O. @(' Issued channel attention'). 25. @status);
call c".l~;
return.
endi

==>

5-109

intel®

AP·234

end)

7b'
770

3
2

call write-CO.

771
773
77.
775
77b
77B
77.
7BO
781
7B2
7B3
78'

2
2

if! not" ijes then return;
call writeCO. @(ODH. DAH.

2

i '" read$int(4»)
5cb. cmd = 5eb. cmd or shl(double(i), Bl.
if! i '" 1 then 5eb. cbl$offset = cut'$cbSoffset.

2
2
2
2
2
2

call wl'iteCO.
i "" read.bitl

7B5
7Bb
7B7
7BB

2
2
2
2

than goback = I.
call writelnCO. @CODH, OAH.
call cr$lf.
output(CA$PORTJ = CA.

7B'

2

2
2

=

7.,
7'2
7.3
7 ••
7.5
7'b

2
2
2
2
2

7.7

2

2

Do you want to enter an.., SeB commands? .(V or N) =..>
53. @status)l

(!(ODH,

DAH.

' Enter

I

5cb. cmd 01' shiei.

call writeCO.

(!(ODH.

cue "''''>

Enter RES bit

'I,

"''''>

@status);

'I. 21. @status)j

7)j

' Entl!f' Rue ==> 'I,

DAH.

17.

').

17. @status);

i .. read$int(4lj
5eb. cmd = 5eb. cmd or shiei. 4);
if « (5eb. cbI.offset
off5et C@t,.ansllnit. status')
and (Cscb. cmd and OlOOH) • OlOOH»
or «scb. cmd and COIOH) .. DOIOH»
and not «scb. cmd and OOSOH) = OOSOH)

=

' Issued Channel Attention'). 27. @status).

end fmter$scb$cmdl
print$tIJpeShelp:

7.0

call
call
call
call
call
call

procedurel

IIIritelnCO. @(ODH. OAH, OAH, 'Command block tIJpe: 'I, 22. t!statusll
IIIritelnCO. (!(' N - Nop
·1 - IA Setup'). 35, estatus),
IIIritelnCO. @(' C - Configure
M - MA Setup'). 35, @status),
writelnCO. ('!(' T - Transmit
R - TDA'), 30. @statusl,
IIIritelnCO. (!(' D - Diagnose
S - Dump Status'), 38. @status),
IIIritelnCO. (!(. H - Print this message'), 23, @status),

end print$type$help;
OJetupScb: procedure;
declare It, valid) by tel

7.B
7"
BOO
BOI
B02

2
2
3

B03
BO'

3
3

BO'

3

BOb
B07
BOB
ao.
Bl0
Bl1
B12
a13
Bl'
B15
alb
B17
BIB
Bl.
B20
B21
B22
B23
a2'
825
B2b
827
82B
B2'
B30
B31
832
833
83'
835
83.
837
B3a
a3.
840
a41
a42
a43
a4'
a45
a4.
a47
8.8
ao.
850
a.,
a52
a53
a5'
a55
85.
857
a58
859

3
3
3
3
2
2
3
3
3
3
3

BbO
abl

5eb. cmd

@:('

2

2
3·
3
3
3
3
3
2
2
3
3
3
3
3
3
2
2

3
3
3
3
3
3
2
2
3
3
3
3
3
3
2

2
3
3
3
3
3
3
2
2
3
3
3

valid'" false;
do while not validJ
call IIIritelO. @IODH.
t = read$char;
i f ct <> 'H' ) and
ct <> 'N'I and
ct ·0 'D' ) and
ct <> ' I ' ) and
ct <> 'S') and

ct
ct
ct

OAH,

<>
<>
<>
<>
<>

'Enter command block type IH for',
• help) ==) '), 45. C!status);

'tI') and
'n' ) and
'd') and
'i") and

ct
ct
ct
ct

<> 'T')
<> 'A ')
<> 'e ')
<> 'M')

and
and
and
and

ct
ct
ct
ct

<>
<>
<>
<>

't') and
'r'l and
'e'l and

'm') and
It
's') then
ct
coill1 IIIritelO. @(ODH. OAH.
Illegal commilnd block type '), 29,
@status),
else
i f It .. 'H') or It .. 'h'l then call print$typ.$help;
els," valid = true.

end;
if It = 'N') or (t = 'n'l then
do,
cur.cb.offset = oFfset I@nop. status);
nop.5tatus '" 0;
nop. emd "" BOOOH;
nop. link$of'Fset = OFFFFH;
eT" ,;

if It'"" '1'1 or It ... 'i') then
do.
cur.cb'offset .. offset (@ta'setup. status),
ia.setup. status = O.
ia$setup. cmd "" BOOtH.
ia$setup. link.offset = OFFFFH.
call setup$ia'parameters,
end.
if It ... 'C') or It = 'c') then
do,
cur.cb$offset"" offset (@conHgure.status);
c·onfigure. status = O.
configure. cmd ." B002HI
configure. link'o'fset ... OFFFFHl
eal1 setup'cont! i9 ure$parameters;
endJ
if (t = 'M') or (t ... 'm'. then
do;
cur'ell$offset = offset (I:me'setup. '£tatus),
me'setup. 'itatus =' 0;
ml;$utup. c'!'Id ... 8003H,
mc.setup. link$offset - OFFFFHI
cilill setup.mc$parameters;
end.
if It = 'T'l or (t = 't'l then
do.
cur$eb'offset = offset (@trillnsmit. status ••
transmit. status ... 01
transmit. cmd = B004H.
transmit. link.on . . t· ... OFFFFHI
cillli setup$tx.parametersJ
end;
if (t II 'A') or It .. 'r') then
do;
cur$eb'offset .. offset (@tdr. status).
tdr. status = OJ
tdr. emd .. B005H;
Ur. link.offset = OFFFFH;
tdr. resul t = O.
end;
if' (t • 'S') or (t .. 's') then
do,
c.ur'eb.offset - off'£et (edump. status)1
dump. status = OJ
dump. c. md = B006H;

5-110

inter
86.
863
86'
86'
866
867
868
869
870
87'

3
3
3
2
2
3
3
3
3
3

AP-234

dump. link.offset = OFFFFHi
dump. buffsptT' '" 01'5.t (C!dumpSare.COJ)j
endl

if It"" 'D'I or (10" 'd'l then
dOl

curlcbSoffset "" offset (C!ltlagnosa ... tatus);
d fagnose. status ." 0,
d 1agn05 •. emd .. B007Hj

diagn05&.11nklo"s,,1o = OFFFFHi

end,

872

end 5etupScbi

873
87.

d i sp l'II'Sc ommandSb 1 DC II: proced ure;
declare (i. JI byte.
IiIh pointer.
sel sltlector.
w word;
call t"Slf,
i f CUl'ScbSoHset a OFFFFH then
call IIIl'i1oelO. @(- No Command Block to display'), 28. @status);
i f tur$cb'offset = offu·t (@nop.51oatus) then
do;
call writeCa. (i( '---NOP Command Block---'), 23. ChtataJ!;);
call printSwdsllnop. status. 3);

870
876
877
878
879
880
88'
882
883
88'
88.
886
887
888
889
890
89'
89.
893
89'
89.
896
898
899
90'
90.
903
90.
90.
906
907
908
909
9'0
9"
9'.
913
9"
9'5
9'.
9'7
9'8
9'9
920
92'
922
923
92.
925
92.
927
928
929
930
931
932
933
93.
935
936
937
938
930
9.0
9.,
9.2
9'3
9 ••
9.5
9'6
9.7
9.8
9.9
9.0
9"
95.
953
9 ..
9 ..
956

•
2
2
2
2
3
3
3
2
2
3
3
3
2

•
3
3
3

•
2
3
3
3
3
3
3
3
3
3

••
4

•••
•
5
5

••
3

•

2
3
3
3

•
2
3
3
3

•
2
3
3
3
3

••
•
•
4

3
3
2

•
3
3
3
3
4
4
4

•
5
5
4

••
3

endl
i f cur$cbSoffset .. offset

letdr.

1Itatus) then

dOj

call writeCC. etC '---TOR Command 910cll---'), 23. @status).
call print'wds(@tdr. status. 4)1
endl
if cur$cbSoffset .. offset (@diagno .... status) then
do;
call write(O. @('---Diagnose Command 8locll---'I, 28. \!statu")1
call printSwds(@diagnosl!'. status, 3)1
endl
if cut"$cb$offlset .. offset Cl:tran .. mit. statu .. ) then
do,
call write(O. 1:( '---Tt"ansmit Command 910ck---'I, 29, @status)1
if not address.l.ngth then i = addt"ess.lengthi
else i = addt"es;'length + Ii
if adSloc then c:all printSwdsC@transmit. status. 4)1
else call print'lIIdsU!transmit. status. i/2+J)i
c:a11 crSifi
call crSifl
i f transmit. bdtoffut <> OFFFFH then
dOi
call write(O, @('---Transmit Buffer Descriptor---')' 33. @statusli
call printswds(@tbd.actScount. 4).
call wl'ite(O. @(ODH. OAH, OAH.
, Displa~ the transmit buffer? (Y 01" N)
46. @status)i
i f ~.s then
dOi
call c:r.ifi
call ",riteln(O, @(' Transmit Buffet": '), 17, @status)j
III = tbd. acttcount and 3FFFHi
call printsbuffU!txtbuffer(O), W)I
end I
endi
endl
i f cUr$cbtoffset = offset «U .. t.etup. st.tus) then
dOi
call lIIriteeO, @('---IA Setup Command 810cll---'). 28, @statusli
call print.lllds(@iaSsetup. status. 6)i
end;
i f cur$cbSoffset = offset (C!configure. status) th.-n
dOi
.
call IIIrit.-CO. 1:( '---Configure COlllllland Blocll---'), 29. @statusli
call printtlllds(@cohfigure. status. 9)i
.ndl
i f curScb$offset .. offset (@mc.setup. status) then
dOi
c.al1 wriie(O. C!( '---Me Setup ComlRand 010cll---'), 28. C!statuS)i
i = 4 + mcSc ount/2i
if mcScount > 24 then
do;
call print'lIIds(l!mc$setup. status. 161i
call p.ausei
i .. i - 16,
cell print'lIId .. (@mc.setup.mctaddre!\sC8), i).

==> '),

~ndj

~lse call prlnttllldsCC!mc$setup. status.
I)i
endi
if cur$cb.offset
offset Cldump. status) then
dOi
call writ.(O, C!('---Dump Status CDmmand Olock---'), 31. C!status),
call print$wdsU!dump. st.atus, 4)i
i f dump. status'" OAOOOH then
do;
call writ.lnCO, @(OCH. OAH, ' Dump Statu" Results'). 22, @status)i
call IIIri taSoffset (C!dumpSareatO»,
call crSlf;
do i .. 0 to 91
call printS .. tr (.dumpSarea( 16*i h 161,
end;
call print$strCC!duniptarea(160). 10)i
call crSlfi
endl
end;

=

957
958
959

d i sp l.~trec II i YII.area: proc:eduT'ei
declare (i. k. J. 1) blJte.
chars(41 b~tei

5-111

AP-234

960
961
962
963

:2
:2
2
3

call lIIt'itelnCQ.
if ad.loc then

(!(ODH.

OAH,

• Frame Desr:riptors: 'l,

21.

@status)j

dOl

call writelnCQ.

@(ODH. DAH,

' OA. SA,

and TYPE are in buffe". "
DAHl,

96'
965
966
907
96.
969
970
97.
973
97.
970

do i

outSlllord(@:rfdCi).status.

k).

i f k = 0 then call IIIrite$offut(@1'fd(iI.statu'i);
else call loop'char(10. ' ')1

end.
call cr.lf;
IiInd;

call Iln'ttelnCQ.

977

2

978
979
980
982
983
984
985
986

:3

4
4
4
4
3'
3
2

~8?

989
~90

991
992
993
~94

995
996
~'9?

(leOCH.

' Receive Buffer Descl'iptol's: 'J,

:31 •

else call
end;
call c,,$)f;

loop'char(1Q,

'

'),

end;

call IIIrit.CO. @(ODH. OAH, DAH. 'Displ ..... the receive',
, buffers? (VOl' N) ==) '). 46, @status),
if not 'des then rlfturn;
call write-InCa, G!:(ODH, OAH, 'Receive Buffers: 'I. 19. I!status);
do i = a to 4;
call writeCO. @COOH, OAH, ' Receive Buffer 'I, lB, @.. tatus),
call write$int 'I.
47. @status);
1 = readSchaT';
do while (1 <> 'R') and (1 <> '1") and (1 <> 'C') and (i <> 'C')I
call writeln(O. @(OOH, OAH, ' 111e-gal command',. lB. @statu");
call write(O. C!!:(' Enter R or C "'=) ' ) , 19. C!status),
i = react$chari
end;
if (i = 'R') or (1
'1"1 the-n call disPla"'$receive$~real
else- call d1 .. play$command$blockl

call lIfriteCO. @COOH. OAH.

••
3
3
3'

3
2

•

=

1011

e-nd dispIaY$cb$rpai

1012
1013

process$cmd: proce-dure;
declare (b. i) byte;

1014
1015
1016
1017

1018
1019
1021
1022
1023
1024
1025

DDH.

4!s.tatus)l

'" 0 to 4;
call

• 76

1002
1003
1004
1005
1006
100?
1008
1010

36.

end;
else J = addT'essSlength + 41
do k = 0 to Ji

goback = 0;
b .. read$char;
call cr$lf;
'b <> 'H') and 'b ( ) 'h' ) and 'b <> 'S') and 'b
'b <> 'D') and 'b <> 'd') and 'b <> 'P') and 'b
'b <> 'C' ) and 'b <> 'c') and 'b <> 'E') and 'b
'b <> 'L') and 'b <> '1') and 'b <> 'N') and 'b
'b <> 'Z' ) and 'b <> 'z') and Cb ,<> 'V') and 'b
'b <> 'A') and 'b <> 'a' ) then
call write(O, @"
Illegal comm.and' ). 16, I!status);
'b = 'H') or 'b = 'h') then call print$help;
'b = 'A') or 'b = 'a ') then
i f dhex then

"

••
••
2

""

dhex = falsl'i
call write(O,

3

end;
else
dOi

1028
1029

3

1030
1031
1032
1033
1034
1035
1036
103?
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052

3
2

3

•
3
3
3

•
2

3
3
3

••

3
'3
3

••
3

·3
3
3

2

's'l
'p')
'e' )
'n')
'y')

and
and
and
and
and

do,

3

1026
102?

<>
<>
<>
<>
<>

@('

Counters are

dh;pla~ed

in decimal. '). 35,
@:statu!5);

dhex = true;
call write(Q. @(' Counters are

d1spla~ed in hexadecimal. '). 39.
@9tatus);
end/
if (b ;: 'L') or Cb .. ' I ' ) then
do,
output(ESIt:PORTl = LOOPDACK;
call wrUe(O. @(' ESI is in Loopback Mode, '), 2:5. @statu")i
end;
if (b = 'N') or (b = 'n') then
do;
output(ESI$PORTl = NO$LDOPBACK;
call write(O. IU' ESI is NOT 1n Loopback Mode. '), 29, .status),
end;
if (b - 'Z') or (b .. 'z') t'hen
do,
count = Oi
c,1IIl1 write(O. @(' Transmit Frame Counter is cleared. '), 35, @:status}'
en'dl
if Cb = 'V') or (b = '1,1') then
do.
receive$count IZ 01
!fcb. crc$er1'5. !fcb.a)nSer" ... !feb.rscSerrs, scb. oyrn$errs = 0;
ctlll write(O, @(' Receive Fralfte ·Counter is cleared. '), 34, @&tatu,s);
lIndJ
if (b
'C'l or Cb = 'c') then call enter$scb.cmd.

=

5-112

inter
1054

AP-234

1058
1060
1062

if (b
'S')
if (b "" 'P')
if (b "" '0')
if Ib '" 'E')
call C1'$lf.

1063

end processScmdi

1056

1064

gatout:

1065

decl .. ,.e b byte;
b

1066
1067
1068

:c

1073

1074
1075
1077

1080
1081
1082

2

1083

2
2
2
2

1090
1091
1092
1093
1094
10~~

1096
1097

1099
1099

1100
1101
1102
1104
1105
1106
1107
1108
1109
1110

1111
1112

1113

1114

1123

1126
1127
1128
1129
1130
1131
1132

1133
1134
1135
1136
1137

1138
1139
1140

1141
1142
1143

1144
1145
1146

1147

(H for help) ==)

'),

' Enter command CH for help)

34.
@:status)'

""=> '),

34,
(!status) ;

2

2
2
2
2
2
2
2

2
2
3
3
3
3
2
2
2

2
2
2

2
2
2
2
2

call cr$lf!;
call loopscharOO, OAH)i
call loopScharC28, '.');
call writeCO. (!(' Station Configuration '), 23, @status);
call loopSchar(27. '*').
call cr$lf!i
call cr$lfj
call write(O, (!(' Host Address: '), 15, @statusl;
call printsnetlilorksaddrC(!iassetup. i.aSaddress(O) II
i .. 0;
.
call lIlT'iteCO. @(' Multicast Address(es): 'I. 24, (!status);
if mc$sstup. mcSbyteScount .. 0
then call IIlpit.lnCO, @('No Multicast Addresses Defined '). 30, (!statuli)i
else
do IIlhile 1 < mc$setup. mc.bytescountl
call pr i ntSnetlllor k$addr C@mc$setup. mcSaddress Ci ) );
call loopscharC24, • '1.
i

.. i

+ b.

end.
call IIlrite(O. @(ODH). 1, Qstatus);
if not noStranftmission then call printSparameters;
call wrlte(O. @(' 82586 ConfiguT'ation Block: 'I, 28. @statusl.
call printsstrC@confligure. info(O). 10).
call CT'tlf.
call loopSchaT'(29. '*');
call lUT'ite(O. @C' Station Activities 'l, 20, @status);
call 10opSchar(29. ·.'l;
call cr$lf;
call CT'$lf.
call lIlT'iteln(O.
@(' 4t of Good
4t of Good
CRC
Alignment
No
Receive').
73. @status);
call wT'itelnCO,
@(' Framl's
Frames
Errors
Errors
Resource
OVerrun' I.
7:). (htatus).
call IIlriteln(O,
@(. Transmitted
Received
ErroT's
ET'T'ors').
72. @statuS)i

main:

1124
1125

@(ODH.

end getout;
update: procedurel
declare i byte;

1116

1121
1122

' Enter command

read'chari

end updatei

1120

DAH.

call print'5cb;
call displal,t$cb$rpa;
gobact :: Ii

pl'oceduT'l!';

1115

1117
1118
1119

call setup'cbi

end;

1079

tOS7
109B
1089

then
then
thlln
then

end;

1078

10S6

's"
'p')
'd')
'e')

do foreveri
i f csts then
do.
disable;
call processScmd;
enable;
if gobac k then returni
COllI writl'eO. &eOCH, OAH,

1070
1071
1072

10B5

or Ib
or (b

goback .. OJ
call wT'iteIQ.

1069

1094

or Cb
or (b

call init;
enable!
do wll i Ie T'8set;
end;
disablel
licb. cmd '" OIOOH;
output(CASPORTJ = CAi
call wait$scbi
enable;
do while (d1agnose. status and BOOOH) <> 8000Hi
end.
call CT'$lf;
i f diagnose. status <> OAOOOH
then callwriteln(O, @(' Diagnose failed!'). 17, @:status);
i f configure. status <> OAOOOH
then call writelnCO. @(' ConfiguT'e Failed!'), 18. @status);
if ia.setup. status <> OAOOOH
then call writeln(O. @(' IA Setup failed!'). 17, Qstatusl;
if mCSsetup. status <> OAOOOH
then call writeln{O. C!(' MC Setup failed!'). 17. @statusl;
scb. cbl.offset CI oHset (i!transmit. status);
call writeln(O. @(OCH. OAH. ' Receive Unit lS active. 'I. 26, @status).
disable.
scb. cmd = 0010H.
output(CA$PORTl = CA.
call wait"lOcbl
enabl.l
output(ESI$PORTl = NOSLOOPBACK;
call CT'Slf;
if not no$tT'anlOmission then
do.
call writ.(O. C!('---Transmit Command Bloc!c---'). 28. @statUS)i

5-113

AP-234

1148
1149
L

call pl'tnt'wdstlltransmtt. ~tatus, 8);
call t'l'tlfl
eu,.$cb$offset .. o-Ffsf't (t!:tT'ansmit. status);
call pause;

11~2

2
2
2
:!
2

1153

:3

1154
1155
1156
1157
1158
1159
1160
1161

3
2
2
2
2
2
:2
2

1162

:2

11&3
1164

1
1

1165
1166
1167

2
2
:3
4
4
4
4
4
4
4
:3
:3

call IIIrite(O. @(ODH.
do \I '" 0 to 51

:3

e-nd.
iF C'5ts then
do,
disable.
call getoutl
call update I
end.

l1~O

1151

I1b8

1169
1170
1171
1172
1173
1174
1175

1176
1177
1179
1179
1180
I1Bl

its:!
I1B3
1184
1185

do

or:

= 1 to 60;
ciiilll tim.(250),

end;

call writ.lnCO. e(ODH. DAH.

'transmission started! '), 23. estatus>,

call C1'.lF;
diubhl
5tb. cmd .. 0100Hl
output (CA.PORT) co CAl

call wait.5cb,
enable;
end,
cOIoll updatel
do foreve,.!

'

'), 2. @status);

do case \Ii

call w1'1 teSlntccDunt. dh ..:) I
call write$lnt(l'ecelv.SCDunt.

dh.x I

call write.iote.tb. crete"r'h dhe.)
call IIfT'U •• :l.nt(scb. aln."1""5. dhe.)
call wT'U.$:l.nt(sc:b. T'sc'''T'rs. dhul
ca11 IUrite$int(scb. Dyrn$errs. dhe. I
end.
ch .. ,.Scount = 13 - ch .. ,.$caunt.
call loop$chaT'(char$cDunt. ' ').

:2
2
3
3
3
:3
2

end t'5mSI

MDOUL.E INFORMAT ION:
CODE AREA SIZE
c.2451H
CONSTANT AREA SIZE - t077H
VARIABLE AREA SIZE. 265EH
MAXIMUM STACK SIZE .. 0092H
1994 LINES READ
o PROgRAM WARN I NCS
o PROgRAM ERRORS

9297D
4215D
9B22D
146D

DICTIONARY SUJ'lHARY:
47BK8 MEMDRY AVAILABLE
241'.8 MEI'1ORY USED
(5~)
OKB DISK SPACE USED
END OF PL'M-S6 COf1PILATION

5-114

82588 Reference Manual

6

AP-001

September 1985

82588 Reference Manual

Order Number: 231368-002
6-1

82588 REFERENCE MANUAL

with. The 82588 has a high level command interface
(the CPU sends commands such as CONFIGURE or
TRANSMIT) so the designer does not have to bother
with low level software development. This saves on
CPU overhead as well. The 82588 makes efficient use
of the system memory available by employing Multiple
Buffer Reception in which receive frames are saved in
buffers that are chained together in system memory.
This is an important feature for those applications with
limited memory such as personal computers. The 82588
has two independent 16 byte FIFOs (one for reception
and one for transmission) that allows the device to tolerate bus latency. Finally, the 82588 provides an 8-bit
data path that supports up to 4 Mbytes/second using
external DMA. The DMA interface has been optimized
for use with the 80186/80188 microprocessors.

6.1 INTRODUCTION
The 82588 is a highly integrated Local Area Network
(LAN) Controller that lends itself easily to cost sensitive LAN applications such as Personal Computers and
Intelligent Terminals. Because of its high integration,
the 82588 reduces component count which in turn reduces board space and development time. Additionally,
due to the flexibility of the 82588, the system design
engineer can program a variety of device parameters to
a configuration that allows it to be used in the emerging
IEEE 802.3 standards for PCs. The combination oflow
cost and high flexibility makes the 82588 an attractive
solution for the LAN system designer.
The 82588 provides most of the functions of the ISO
Physical and Data Link layers of LAN architecture.
This includes a CSMA/CD controller, two different
collision detect mechanisms, and a data encoder/decoder that supports data transfer rates of up to 2 Mbps.

The 82588 provides a rich set of diagnostic and network management functions that allow the designer to
minimize debug time and maintain top network efficiency. Specifically, the 82588 provides internal and externalloopback capability and network channel activity
indicators, it can capture all frames regardless of address (Promiscuous Mode) and it supports Time Domain Reflectometry for locating shorts and opens in the
transmission cable. There is also a Register Dump command which allows the user to examine the 82588 internal status registers.

As mentioned, the 82588 is programmable which allows it to operate in a variety of LAN environments
including the emerging IEEE 802.3 standards of 1
Mbps baseband (called STARLAN) and 2 Mbps broadband (used in the IBM PC Network). Some of the programmable parameters are:
Framing (End of Carrier or SDLC)
Address Field Length
Station Priority
Interframe Spacing •

The following chapters describe the features and capabilities of the 82588 in greater detail.

Slot Time
CRC-32 or CRC-16
NRZI or Manchester encoding/decoding

6.2 THE 82588 INTERNAL
ARCHITECTURE
There are two major functional blocks of the 82588: a
parallel system interface to the host CPU and a serial
interface to the local area network. Linking these func c
tional blocks are two on-chip, 16-byte FIFOs, one each
for transmitting and receiving (see Figure 6- I).

In addition, the 82588 allows for a variety of frame
formats, network topologies, data encoding and decoding schemes and data transfer rates.
A major innovation of the 82588 is its on-chip logic
based collision detection. So that a high probability of
collision detection can be maintained, two mechanisms
are provided. First, the Code Violation method defines
a collision when a transition edge occurs outside of the
region specified for NRZI or Manchester encoding.
Second, the Bit Comparison method compares the signature of a transmitted frame to the receive frame signature while "listening to itself."

6.2.1 Parallel Section
The parallel system interface consists of a Bus Interface
Unit (BIU) and several registers. The BIU has an 8-bit
data bus, and is responsible for all interfacing to the
system bus. It handles all transfer of data to and from
memory - at speeds of up to 4 Mbytes/second - as
well as issuing CPU commands and interrupts. There
are two DMA channels allowing for simultaneous
transmission and reception. The register section consists of three register sets. The first stores configuration
information, the second is for the posting of commands
and the third contains status information.

The 82588 goes beyond the basic provisions required
for LAN physical interfacing. It also has an extremely
friendly system interface that makes it easy to design

6-2

82588 REFERENCE MANUAL

RXD

REGISTERS
COMMAND
STATUS

CSMA/CD

COLLISION
DETECTION
LOGIC

OATA LINK

TXD
CONTROLLER

RXC
CLOCK GEN.
TIMING

TXC

DATA LINK

SYSTEM INTERFACE

SERIAL INTERFACE

231368-1

Figure 6-1.82588 Block Diagram
The data encoder/decoder of the 82588 can transmit
and receive data in anyone of three formats: Manchester, differential Manchester and NRZI encoding. Data
rates with the internal encoder/decoder, can be up to
2 Mbs. The serial machine is driven by a clock generator using an up to 16 MHz crystal. This clock generator
is for the serial side only; the parallel side receives its
timing from the system clock.

6.2.2 Serial Section
The serial machine of the 82588 employs the IEEE
802.3 CSMA/CD protocol. The serial section is responsible for the following tasks:
converting data from parallel to serial form and
vice versa
formatting the frame per the programmed configuration

COLLISION DETECTION

computing the CRC "signature" and monitoring
for code violations in order to detect collisions

A major breakthrough introduced in the 82588 is the
on-chip logic based collision detection capability. There
are two programmable forms of collision detection. The
"code violation" detection method checks the incoming
bits to see if they violate Manchester or NRZI standards. If a violation does occur, the 82588 assumes a
collision has occurred. The second method is called "bit
comparison.". For this method the 82588 listens to itself
while calculating a signature for both the transmit and
receive data. If the signatures do not match, the 82588
will back-off and retry immediately, without having to
wait for transmission of the frame to be completed. In
this way, total data throughput is increased significantly.

performing carrier sense and deference if the network is busy
calculating random delay time before retransmission in the event of deference or collision
The efficiency of CSMA/CD was demonstrated in a
1979 study of an Ethernet LAN of about 120 host computers and network server devices. The study showed
that a network using collision detection has a throughput rate of 98 percent. This can be compared to the
efficiency rate of 37 percent in networks with collision
avoidance and 18 percent in networks with no collision
regulating provisions. Until recently, the relative sophistication of collision detection schemes such as
CSMA/CD prevented their inclusion in cost effective
LAN components.
6-3

82588 REFERENCE MANUAL

TRANSMIT
FRAME

--+1 .

TX CRC

L
__ _......_

COLLISION
WINDOW
TIMER

L

TRANSMIT

.......~ CHANNEL

0--+

COMPARE

RECEIVED
FRAME
231368-2

Figure 6-2_ Bit Comparison Detect

The parallel and serial section of the 82588 are asynchronous. The interface between them is made up of
two unique FIFOs, one for transmission and one for
reception. The FIFOs are 16 bytes deep and improve
the data transfer rate in two ways. First, DMA requests
to the CPU are minimized by fine tuning the programmable FIFO threshold to match the particular system
bus latencies. Second, the CPU side of the chip does not
have to wait for the network side which transfers data
at a slower rate.

Chip select and Interrupt lines are used to communicate between the 82588 and the host as shown in Figure
6-3. Interrupt is used by the 82588 to draw the CPU's
attention. The Chip Select is used by the CPU to draw
the 82588's attention.
There are two kinds of transfers over the bus: Command/Status and data transfers. Command/Status
transfers are always performed by the CPU. Data
Transfers are requested by the 82588, and are typically
performed by a DMA controller.
The CPU writes to 82588 using CS and WR ~nals.
The CPU reads the 82588 status register using CS and
RD signals.
.
.

6.3 WORKING WITH THE 82588
This section describes how the 82588 interacts ~ith system CPU, and how the 82588 transmits and receives
frames. The emphasis here is not on any particular
commands, but rather on how the 82588 works. The
details on Framing, Network Management, Initializing
the 82588, Configuring the 82588, Controlling the
82588, System Interface, and Link Interface are con-.
tained in the following chapters.
'

To initiate a command like Transmit or Configure, a
Write operation to 82588 is issued by the CPU., A Read
operation from CPU gives the status of the 82588. Although there are four status registers, they' are read
using the same port in a round robin fashion. Section
Eight discusses details on these commands, and the
status registers.
Any parameters or data associated with the command
are transferred between the memory and 82588 using
DMA. The 82588 has two data channels, each having
Request and Acknowledge line. Typically one channel
is issued to receive data and the other to transmit data
and to do all the other initiaIlzation and maintenance
operations like Configure, Address Set-Up, Dump, Diagnose, etc. The two channels are identical and can be
used interchangeably.

6.3.1 82588/Host CPU Interaction
The CPU communicates with the 82588 through the
System's memory and 82588's on-chip registers. The
CPU creates a data structure in the memory, programs
the external DMA controller with the start address and
byte count of the block, and issues the command to the
82588.
The 82588 is optimized for operating with the iAPX
186/188, but due to the very conventional nature of
hardware signals between the 82588 and the CPU, the
82588 can operate easily with other processors. The
data ,bus is 8 bits wide and there is no address bus.

When 82588' requires access to the memory for parameter or data transfer, it activates the DMA request line
and uses the DMA controller to achieve the data transfer. Upon the completion of an operation, the 82588
interrupts the CPU. The CPU then reads results of the
operation and the status of the 82588.
6-4

82588 REFERENCE MANUAL

231368-3

Figure 6-3. 82588/Host CPU Interaction

begins transmitting the preamble and concurrently
fetches the bytes from the Transmit Data Block and
loads them into a 16 byte FIFO to keep them ready for
transmitting. The FIFO is a buffer between the serial
and parallel part of the 82588. If the link is busy, the
82588 fills up the transmit FIFO and defers. The onchip FIFOs help the 82588 to tolerate system bus latency as well as provide efficient usage of system bus bandwidth.

6.3.2 Transmitting a Frame
To transmit a frame, the CPU prepares a Transmit
Data Block in memory as shown in Figure 6-4. Its first
two bytes specify the length of the rest of the block. The
next few bytes (up to 6 bytes long) contain the destination address of the node it is being sent to. The rest of
the block is the data field. The CPU programs the
DMA controller with the start address of the block,
length of the block and other control information and
then issues the Transmit command to the 82588. (Section 6.4 discusses details on the framing).

The destination address is sent out after the preamble.
This is followed by the source or the station individual
address, which is stored earlier on the 82588 using the
lA-SETUP command. After that, the entire information field is transmitted followed by a CRC field calcu-

Upon receiving the command, the 82588 fetches the
first two bytes of the block nsing DMA to determine
the length of the block. If the link is free, the 82588

PREAMBLE

1

GENERATED BY 82588

BLOCK BYTE COUNT

SFD(BOF FLAG)

DESTINATION ADDRESS

DESTINATION ADDRESS

DATA FIELD

SOURCE ADDRESS

I-

FROM 82588
INDIVIDUAL
ADDRESS

TYPE FIELD
CPU GENERATED
DATA STRUCTURE IN MEMORY
(TRANSMIT DATA BLOCK)

\

INFORMATION FIELD
FRAME CHECK SEQUENCE
EOF FLAG (OPTIONAL)
PADDING (OPTIONAL)

l

GENERATED BY 82588

\
231368-4

Figure 6-4. The 82288 Frame Structure and Location of Data Element in System Memory
6-5

82588 REFERENCE MANUAL

lated by the 82588. If during the transmission of the
frame, a collision is encountered, then the transmission
is aborted and a jam pattern is sent out after completion
of the preamble. The 82588 generates an Interrupt indicating the experience of a collision and the frame has to
be retransmitted. Retransmission is done by the CPU
. exactly as the TRANSMIT command except the RETRANSMIT command keeps track of the number of
collisions encountered. When the 82588 gets the Retransmit command and the exponential back-off time is
expired, the 82588 attempts transmitting the frame
again. The transmitted frame can be coded to either
Manchester, Differential Manchester or NRZI methods.

PREAMBLE
SFD (BOF FLAG)
DESTINATION ADDRESS
SOURCE ADDRESS
INFORMATION FIELD
FRAME CHECK SEQUENCE
EOF FLAG (OPTIONAL)
PADDING (OPTIONAL)

Figure 6-5. 82588 Generalized Frame Format

The different fields of the frame are:
- The Preamble which is used as a synchronizing sequence for bit decoding ..
- SFD, Start of Frame Delimiter (for bitstuffing
method, this field is called BOF flag).
- The Destination Address (frame target address).
- The Source Address (sender's address).
- The Information field containing user supplied
data.'
- The Frame Check Sequence (peS): Cyclic Redundancy Check (CRC) used in detecting bit errors.
- The End of Frame (EOF) flag - optional. (For bitstuffing mode.)
- Padding: optional field which extends the length of
the frame to ensure minimum frame length. Optional (for bitstuffing mode).

6.3.3 Receiving a Frame
The 82588 can receive a frame when its receiver has
been enabled. The received frame is decoded by either
on-chip Manchester, Differential Manchester or NRZI
decoders in High Integration Mode or by external decoders in the High Speed Mode. The 82588 checks for
an address match for an Individual address, a Multicast
address or a Broadcast address. In the Promiscuous
mode the 82588 receives all frames. Only when the address match is successful does the 82588 transfer the
frame to the memory using the DMA controller. Before
enabling the receiver, the CPU makes a memory buffer
area available to the Receive Unit, and programs the
starting address of the buffer in the DMA controller.
The received frame is transferred to the memory buffer.

6.4 FRAMING AND LINK
MANAGEMENT
.

• The 802.3 Length Field is included in the Information field.

The data structures handled by the 82588 are called
frames. A frame is a sequence of bits that travels on the
link.

6.4.2 Frame Boundary Delineation

Framing has three primary functions: to determine the
beginning and the end of the frame (frame boundary
delineation); to determine the frame's source and destination (addressing); and to perform transmission error
detection.

The 82588 handles Frame Boundary Delineation transparently to the user. The fields involved in Frame
boundary delineation are: Preamble, SFD (BOF Flag),
EOF flag and Padding. The 82588 is configurable to
one of two Frame delineation methods: End of Carrier
(802.3 compatible) orBitstuffing.

6.4.1 Frame Format

In the End of Carrier method, the .82588 transmits (depending on the configuration) 1,3,7, 15 preamble bytes
of alternating ones and zeros followed by a SFD (BOF
Flag) of pattern 10101011. The end of frame is indicated by the carrier going inactive immediately after the
Frame Check Sequence field. The Carrier is a signal
which informs the 82588 of activity on the link. It can
be internally or externally generated. This frame
boundary delineation method is compatible with IEEE
802.3.

The Frame format supported by the 82588 is shown in
Figure 6-5.

6-6

82588 REFERENCE MANUAL

The Bitstuffing method implements the HDLC zero bit
insertion/deletion mechanism. The 82588 transmits
(depending on the configuration) a Preamble of I, 3, 7
or 15 bytes of alternating ones and zeroes followed by
an HDLC flag (01111110). End offrame is indicated by
a HDLC flag. The 82588 can perform HDLC zero bit
insertion (insert 0 after five consecutive I's) on the
fields between the BOF and EOF flags. The chip can be
configured to pad the frame with additional flags so
that the frame length becomes equal to or longer than
the Slot Time.

MULTICAST ADDRESSING

Frames can be directed to a specific group "of nodes.
This group can have a particular group address called
Multicast Address. A node may belong to several different groups. A one in the least significant bit of the
destination address distinguishes Multicast Address
from Individual Address. MC-SETUP command is
used to program the set of Multicast addresses for a
station by setting up a 64 bit "Hash Table." The 82588
maps and stores every Multicast Address into a single
bit of the Hash table. During reception of a frame
whose Destination Address is a Multicast Address, the
82588" checks whether this address is mapped in the
Hash table. If an address match is determined, the
82588 begins the reception process.

6.4.3 Addressing
Regardless of the Frame Boundary Delineation method, the two fields following the SFD (BOF Flag) are
Destination Address and Source Address.

It is possible for more than one Multicast Address to be
mapped into a given Hash bit. Thus, the host may have
to perform additional checking." If 64 or fewer Multicast addresses are used in a system, it is" possible to
select address values that map into unique bits in the
Hash table. The Hashing function is the CRC polynomial used for bit error detection. The 6 most significant
bits (2-7) are selected from the first byte of the CRC
shift register to index the 64-bit Hash table.

Addressing allows frames to be directed to one or more
specific nodes. The 82588 provides flexible addressing
techniques allowing a frame to be received by a single
node, a group of nodes (multicast addressing), or all
nodes (broadcast addressing).
After initialization, the 82588 is configured with an Individual Address using the lA-SETUP command. The
address length is determined by the Address Length
parameter (0 to 6 bytes). The default c9nfiguration is
an all ones address (Broadcast Address). 6 bytes long.

INFORMATION FIELD

The information field follows the source address field.
It contains the actual data being" transferred in the
frame. Its maximum length is (2 16) - 2 X (address
lel)-gth) - 2 which includes destination and source addresses.

During transmission the 82588 usually inserts its Individual Address from the internal Individual Address
register i~to the Source Address field. The source address insertion canbe overridden when configuring the
chip. During reception, the 82588 compares the incoming Destination Address with its Individual Address,
the programmed multicast set of address and the
broadcast address. If an address match is made (all bits
must be equal) the frame is accepted. A frame whose
address does not match is simply ignored by the 82588
and has no effect on the 82588 nor on any other component of the station.

6.4.4 Error Detection
The Frame Check Sequence (FCS) Field protects
against bit errors in the frame. It is the result of a Cyclic Redundancy Check computed on the Destination
Address, Source Address, and Information Fields. The,
chip can be configured to one of two CRC algorithms:
the CCITT V-41 (HDLC) 16-bit polynomial or the Autodin II (IEEE 802.3) 32-bit polynomial.

INDIVIQUAL ADDRESS

The 82588 is normally configured with a specific Individual Address. An Individual Address must have a
zero in the least significant bit.

The CRC mechanism is transparent to the user. During
transmission, the 82588 calculates and inserts the
Frame Check Sequence. During reception the chip verifies the correctness of the incoming Frame but does not
pass the FCS to memory. The CRC is applied to an
integral number of 8-bit words excluding the potential
residue. CRC insertion can be disabled for diagnostic
purposes. The user should then provide the FCS field
after the data field.
"

BROADCAST ADDRESSING

An address with all l's is the Broadcast Address. Every
station on the link "hears" a Broadcast. A frame may
be targetted to all nodes by using the broadcast address.
The 82588 can be configured to disable reception of
frames with Broadcast Destination Address, e.g., for
stations with limited storage resources.

6-7

82588 REFERENCE MANUAL

The 82588 notifies the user ofa collision and gives an
opportunity to retransmit at the end of the BackotT
time out.

6.4.5 Frame Transmission
The 82588 transfers data from host memory to the network when a CPU issues a TRANSMIT command.
Before instructing the 82588 to start a transmission, the
host CPU prepares the frame in memory. Parts of the
frame such as Preamble Source Address, CRC and
Flags are inserted by the 82588 Data Link Controller.
The 82588 resolves access and contention on the link
using the Carrier Sense Multiple Access with Collision
Detection (CSMA/CD) link Management protocol.
When the transmission is completed, the 82588 updates
a set of status registers and raises its Interrupt signal to
inform the CPU.

The.82588 implements the IEEE 802.3 scheduling of
the retransmission. The controlled randomization process is called "truncated binary exponential backotT." A
retransmission is delayed an integral multiple of slot
times. The number of slot times to delay before the nth
retransmission attempt is chosen as a uniformly distributed random integer in the range 0S;r<2k , where K =
min [n, 10]. The ,number of retransmission attempts is
programmable in the range 0 to 15. The beginning of
the BackotT time is configurable to one of two methods:
If configured to the IEEE 802.3 compatible method,
BackotT starts immediately after the end of the Jam
pattern; if configured to the alternate BackotT method
(designed for lower bit rates and/or shorter topologies),
BackotT starts after the deferring period following collision.

6.4.6 Link Management
The 82588 handles CSMA/CDlink management algorithms according to the IEEE 802.3 standard. 82588
link management algorithms are adaptable to a variety
of network topologies via programmable configuration
parameters. Station priorities are also programmable.

After the backotT time has expired and the CPU has
issued a RETRANSMIT command, the 82588, at~
tempts to retransmit the frame (after deferring to any
traffic on the link) unless the number of retransmissions
has exceeded the maximum allowed

The 82588 constantly monitors link activity. Whenever
it senses activity on the link the 82588 defers to the
passing frame by delaying any pending· transmission.
When there is no more activity on the link, the 82588
continues to defer for Inter Frame Spacing (IFS)' time
(minimum time between two consecutive frame. transmissions). This parameter is configurable from 12 to
255 bit times. If at the end of that time, the 82588 has a
frame waiting to be transmitted, transmission is initiated independently of the link activity.

The 82588 maintains a retry counter that is incremented after each collision. If retransmission is successful,
the user is notified; If the number of retries equals the
programmed maximum, an error is reported. The DUm"
ber of allowed retries is configurable from 0 to 15 attempts. The only ditTerencebetween transmission and
retransmission is tha:t transmission' clears the retry
counter arid retransmission increments it.

Once the 82588 has finished deferring and has started
transmission, it is possible' to experience lip.k contention. This situation is called a collision and is generally
detected and signalled by the transceiver. The 82588
can be programmed to detect collisions internally or
externally via the CDT pin. When the 82588 experiences a collision, it enforces the collision by transmitting a jam pattern of 32 to 48 bits.

Oncompletiori' of transmission and retransmission, the
82588 reports 'the total number of collisions that have
occurred and whether it equalled or 'exceeded the maximum. It also indicates if the 'chip had to defer to passing traffic on its first transmission attempt.
After transmission. has started the 82588 attempts to
transmit the entire frame. In the normal case, frame
transmission is completed and the host is notified
through interrupt and status register. Otherwise, one or
more of the following events causes transmission to terminate prematurely: Clear-to-Send signal goes inactive
during transmission, data transfer rate from memory to
the chip did not keep up with transmission (DMA underrun), Carrier Sense goes inactive during transmission (if the chip is in the mode where carrier sense is
expected during transmission), a collision is detected
via Collision Detect Signal. These events are also reported to the CPU via the status registers.

If a pollision is detected during the Preamble, transmission of the preamble is completed before jamming
starts. The collision enforcement mechanism ensures
detection of the collision by all the stations.
The jam pattern is all ones in all cOlifigurations except
for NRZI encoding, where it is a sequence of all zeros.
(Transition every bit time).
The dynamics of. collision handling are largely determined by the Slot Time. Slot Time is the maximum end
to end round trip delay time of the network plus jam
time. Slot Time is important because it is the worst case
time to detect a collision. The Slot Time is programmable from 1 to 2048 bit times.

The user may attempt to abort transmissions. Upon receipt of the ABORT command, the 82588 transmits a
Jam pattern to cause a CRC mismatch. The chip reports to the host either that the ABORT succeeded or
that the frame transmission was completed before the
ABORT was accepted.
6-8

82588 REFERENCE MANUAL

aligned" (has got residual bits) and a CRC error is detected.

6.4.7 Priority Mechanism
The 82588 implements two different priority mechanisms: linear and accelerated contention resolution. Either may be used to distribute relative priority among
stations.

When configured to Bitstuffing delineation, the 82588
performs zero bit deletion, discards the EOF flag, and
all following bits until end of carrier. Residual bits are
discarded in a manner similar to the End of Carrier
method. An error is reported if the carrier goes inactive
prior to recognition of an EOF flag.

Linear priority determines the number of Slot Times
that the 82588 waits after deferring or after the end of
the Backoff Time (whichever occurs last) before transmitting. If the link becomes busy during the wait period, the process of deferring and waiting starts again.
The Linear priority is programmable from 0 to 7. Zero
provides the highest priority and is IEEE 802.3 compatible.

The minimum frame length is configurable in the range
from 6 to 255 bytes. Any frame containing less than the
minimum (configured) number of bytes is presumed to
be a fragment resulting from a collision or an aborted
transmission. Any frame shorter than 6 bytes is discarded without notifying the user.

Accelerated contention resolution extends the range
from which the random number for backoff is drawn.
The random number for the first Backoff delay is in the
range 0 S r < 2P, where P is configurable from 0 to 7
with 0 providing the highest priority.

SINGLE BUFFER MODE

The received frame is transferred to the memory buffer
in the format shown in Figure 6-6. This method of reception is called "Single Buffer" reception. The entire
frame is contained in one continuous buffer. Upon
completion of reception the total number of bytes written into the memory buffer is loaded into status registers 1 and 2, and the status of the reception itself is
appended to the received frame. An interrupt to the
CPU follows.

6.4.8 Frame Reception
The 82588 receives and passes to memory every frame
whose address matches its individual, multicast or
broadcast address. By configuring the chip to the promiscuous mode, it will receive and pass tomemory all
frames regardless of address.

MULTIPLE BUFFER MODE

The 82588 constantly monitors the serial link activity.
'When the link becomes active, the 82588 starts accepting the incoming bits.

If the frame size is unknown, memory usage is optimized by using "Multiple Buffer" reception. The frame,
as it comes in, is deposited into a series of fixed size
buffers. This way the user does not have to allocate
large memory space for the short frames. Instead, the
82588 can dynamically allocate memory space as it receives frames. This method requires both data channels
alternately to receive the frame. As the frame reception
starts, the 82588 interrupts the CPU and automatically
requests assignment of the next sequential buffer. The
CPU does this and loads the second DMA channel
with the next buffer information so that the 82588 can
immediately switch to the other channel as soon as the
current buffer is full. When the 82588 switches from
the first to the second buffer it again interrupts the
CPU requesting it to allocate another buffer on the other (previous) channel in advance. This process continues until the entire frame is received. The received
frame is spread over multiple memory buffers. The link
between the buffers is easily maintained by the CPU
using a buffer chain descriptor structure in memory
(see Figure 6-7).

The Preamble and SFD (BOF flag) are discarded. The
82588 compares the incoming frame's Destination Address to its own Individual Address. If there is an address match and the frame length equals or exceeds 6
bytes, the 82588 passes the Destination Address,
Source Address, and Information fields to system memory via the DMA controller. The 82588 verifies correctness during reception of the FCS field. If there is no
address match, the 82588 does not request DMA controller's attention and becomes ready to receive the next
frame.
When the reception is completed, the 82588 updates a
set of status registers and raises its Interrupt signal to
inform the cpu. If the received frame has errors (CRC
violation, alignment error, DMA overrun), the CPU
can reclaim the memory used to store that frame. The
next received frame can then be stored in the reclaimed
memory.

This dynamic (pre) allocation of memory buffers results
in efficient use of available storage when handling
frames of widely varying sizes. Since the buffers are
pre-allocated one block in advance, the system is not
time critical.

When configured to IEEE 802.3 End of Carrier delineation, end of frame is indicated by the carrier going
inactive. The number of bits after the BOF flag must be
a multiple of eight. Residual "dribble" bits are discarded, and not included in the Frame Check Sequence. An
alignment error is reported when the frame is "mis6-9

82588 REFERENCE MANUAL

BLOCK LENGTH
BL

DESTINATION
ADDRESS

DESTINATION
ADDRESS

SOURCE
ADDRESS

BLOCK
LENGTH
INFORMATION
INFORMATION

DATA BLOCK IN MEMORY FOR
TRANSMISSION
FRAME STATUS
SINGLE BUFFER RECEPTION

231368-5

Figure 6-6. Single Buffer Reception

DEST ADDR
SOURCE ADDR
@

BUFFER 1

@

BUFFER 2

INFO 1

•••
@

BUFFER #1

BUFFER # 2

INFO 2

BUFFER N

••

0
0
0

BUFFER CHAIN DESCRIPTION
(MANAGED BY CPU)

•
INFO N
BUFFER #N
STATUS

231368-6

Figure 6-7. Multiple Buffer Reception

6-10

82588 REFERENCE MANUAL

tal or the external clock can vary between DC and 16
Mbps. The clock must also be programmed to either
8 X or 16 X of the bit rates. In Mode 1, the 82588
receives externally generated Transmit Clock (TXC)'
and Receive Clock (RXC) at the exact bit rate. This
frequency can vary from D.C. to 5 MHz.

6.4.9 Physical Link Interface
The Physical Link Interface to a CSMA/CD network
includes the following functions: clock generation, data
encoding, data decoding, carrier sensing, collision detection and transceiver handshake. The 82588 can be
programmed to support either of two interfaces. In
Mode it supports a highly integrated interface that
provides most of these functions on chip and requires
minimum external support logic. In Mode 1 it supports
a highly flexible interface, that is identical to the physical inteface of the 82586 and requires external logic in
order to connect to the link. The Physical Link layer
functions are presented below in three groups: clock
generation, data encoding and recovery; detecting carrier and collisions; handshake with the transceiver.

°

ENCODING/DECODING

In Mode 0, the waveforms sent out by the 82588 on the
TXD pin and received on the RXD pin, are programmable to be either Manchester, Differential Manchester
or NRZI encoded. The idle state of the signal is high.
In Mode 1, the 82588 transmits and receives NRZ encoded data, that is synchronized to the respective
clocks. Encoding/decoding to/from different schemes
is done externally. The 82588 can be programmed to
generate Manchester encoded data in this mode (in the
frequency range of 1-5 Mbps).

6.4.9.1 CLOCK GENERATION/ENCODING/
DECODING

In Mode 0, the user can provide the 82588 with an
external sampling clock or provide it with a crystal and
let the 82588 generate the sampling clock. The bit clock
is generated internally from an external clock signal or
from an on chip crystal oscillator that runs at 8 X or
. 16 X the data bit rate. The frequency range of the crys-

Figure 6-8 depicts various kinds of data encoding methods implemented in the 82588.
Figure 6-9 illustrates the encoding rules for these methods.

o

o

o

NRZ

DIFFERENTIAL MANCHESTER

Figure 6-8. 82588 Data Encoding Methods

6-11

231368-7

82588 REFERENCE MANUAL

Encoding Method

Mid Bit Cell Transitions

Bit Cell Boundary Transitions

NRZ

do not exist

identical to original data

NRZI

do not exist

exist only if original data bit
equals O. Dependent on present
encoded signal level:
to 0 if 1
to 1 if·O

MANCHESTER

exist for every bit of the original
data:
from 0 to 1 for 1
from 1 to 0 for 0

exist for consequent equal bits of
original data:
from 1 to 0 for 1 1
from 0 to 1 for 0 0

DIFFERENTIAL
MANCHESTER

exist for every bit of the original
data. Dependent on present
Encoded signal level:
to 0 if 1
to 1 if 0

exist only if original data bit
equals O. Dependent on present
Encoded signal level:
to 0 if 1
to 1 if 0

Figure 6-9. 82588 Data Encoding Rules

back mode). The 82588 can be programmed to detect
collisions internally or to accept it from the outside, via
the CDT # pin. The Collision Detect signal may undergo filtering, similar to Carner Sense.

6.4.9.2 CARRIER SENSE/COLLISION DETECT
CARRIER SENSE

Carrier Sense indicates that there is activity on the link,
i.e., the signal from a transmitting station has reached
the station. that is checking:

COLLISION DETECTION BY CODE VIOLATION

In Mode 0, a collision is detected internally when the
receive data experiences code vrolations (Manchester,
Differential Manchester or NRZI) while the station is
transmitting.

In Mode 0, Carrier Sense signal is generated internally
from the incoming data. In this mode carrier sense is
consider active after detection of 3 consecutive edges.
Carrier is considered productive after:
DIFF/MANCHESTER - 1.5 bit times of high level.
NRZI

- 8 bit times of high level.

In Mode 1, the 82588 can be programmed to either
generate Carrier Sense internally (for transceivers that
generate RXC 'only during actual reception) or accept it
from the outside, via the CRS # pin. The Carrier Sense
may undergo noise filtering, i.e., it must be present for a
programmable number of bit times before it is considered valid.
COLLISION DETECTION

Collision Detect indicates that two or more stations are
transmitting simultaneously. When a collision is detected during transmission, the 82588 jams the link, stops
transmitting and goes into backoff. Jamming will not
start unless preamble transmission is first completed.
Collisions are detected during receptions, causing a receive frame abortion. (Only when not in external loop-

A code violation occurs if any of the following is detected:
X 8 Manchester - Pulse width:
1/8 to 2/8 or 11/8 to 12/8
"0" level for 13/8 or more
Missing mid-bit-cell transition
X 16 Manchester - Pulse width:
1/16 to 5/16 or
11/16 or
21/16 to 24/16
"0" level for 25/16 or more
Missing mid-bit-cell transition
A transition that is 1/4 bit time or
NRZI7
more out of phase. More than two
transitions in half bit cell
COLLISION DETECTION BY BIT COMPARISON

An additional mechanism of bit comparison is provided. This mechanism compares the "signature" of the
transmitted data to the signature of the received data
for the duration ofthe collision window (one slot time).
(Wherever 588 configured to internal collision detection.)
.
6-12

82588 REFERENCE MANUAL

A collision is reported if, after the transmission of the
Opening Flag, any of the following conditions becomes
true:
I. Half a slot-time has elapsed and Carrier Sense did
not go active.
2. Half a slot-time + 16 bit times have elapsed and an
opening flag was not yet recognized (16 bit times are
a margin factor).

DMA underrun occurred because the system bus
did not keep up with the transmission.
The number of collisions equals the maximum allowed.
Any of these events causes the report of an unsuccessful
transmission.
The 82588 checks each incoming frame and reports on
the following errors:

3. Carrier Sense went inactive after an opening flag was
received - Transmit still active.
4. Collision window has elapsed and Transmit signature differs from Receive signature.

CRC error: incorrect CRC in a well aligned frame.
Alignment error: incorrect CRC in a misaligned
frame. A misaligned frame with a correct CRC is
not reported by the 82588. (Considered a good
frame.)
Frame too short: the frame is shorter than the configured value for minimum frame length.
NoEOF flag: valid only in Bitstuffing mode, carrier
went inactive before EOF flag detection.
Overrun: the frame was not completely placed in
memory because the system bus did not keep up
with coming data.

In mode I, internal collision detect works only with
transceivers that do not return the transmitted signal.
In that case, detection of a carrier during transmission
indicates a collision.
NOTE:
For broadband applications the slot time is usually
twice the round trip delay.

6.5 82588 NETWORK MANAGEMENT
AND DIAGNOSTIC FUNCTIONS

The occurrence of any of these events causes the report
of an unsuccessful reception.

The 82588 includes a set of features for improving reliability and testability.

6.5.2 Network Planning and
Maintenance

The 82588 offers four diagnostic services: first, monitoring the transmission and reception of frames; second, gathering statistics and diagnostics about the network; third, diagnostic support for a particular station
on the network; fourth, a means to test the proper operation of the chip itself.

To perform proper planning, operation, and maintenance of a communication network, the network management entity must accumulate information on network behavior. The 82588 provides a rich set of network diagnostics that can serve as the basis for a network management entity. The features include: gathering network activity information, saving all frames that
appear on the link (optional), and locating opens or
shorts on the link.

6.5.1 Transmission/Reception Error
Reporting
The 82588 stores status information after completing
transmission or reception of every frame. If transmission or reception is successful, the OK status bit is set.
If transmission is unsuccessful, the cause is given in the
status registers.

Network activity information is provided in the status
available to the host after each frame is transmitted.
The activity indicators are:
I. Number of collisions: the number of collisions the
82588 experienced in attempting to transmit this
frame.
2. Deferred transmission: indicates if the 82588 had to
defer to. traffic on the link during the first transmission attempt.

The 82588 reports on the following events after each
transmitted frame:
Lost Carrier Sense: Carrier sense signal did not become active or was lost during transmission.
Lost Clear-to-Send: Clear to send signal was removed during transmission.

The 82588 can be configured in the Promiscuous Mode.
In this mode the 82588 captures all frames transmitted
on the network regardless of the Destination Address.
This mode is useful in implementing a monitoring station to capture all frames for network analysis.

6-13

82588 REFERENCE MANUAL

The 82588 is capable of determining if there is a short
or open circuit anywhere in the network using the Time
Domain Reflectometry (TDR) command. When a
TDR command (see section "Controlling the 82588")
is issued, the chip transmits a pulse train and measures
the reflection return time. If the network is properly
terminated, there are no reflections so the timer runs
out and the user is notified that there are no link problems. If a problem is detected, the distance to the reflection source and reason (short or open) are reported.

6.6 INITIALIZING/CONFIGURING THE
82588
6.6.1 Initializing the 82588
A hardware or software reset brings the 82588 to its
initial state where the 82588 is put into the idle state
with the transmitter, receiver clock generator, interrupts, etc., inactive. To use the 82588 it has to be con.
figured with a set of parameters.

6.5.3 Station Diagnostics
To support Station Diagnostics, the 82588 can be configured to External Loopback.
In this mode the 82588 operates full duplex at full
speed. The actual maximum throughput depends on bit
rate and system bus speed. The transmitter to receiver
interconnection can be placed anywhere between the
82588 and the link.

6.5.4 82588 Self Testing
The 82588 provid,es several features for self testing.
The 82588 can be configured to Internal Loopback. In
this mode, the 82588 disconnects itself from the internal or external Serial Interface Units, and any frame
transmitted is received immediately. The 82588 connects the Transmit Data to the Receive Data signal and
the Transmit Clock to the Receive Clock. The 82588
can be configured in the External loopback mode. In
this mode, the Transmitted signal at full data rate
comes out at the TxD pin and can be returned to the
RxD pin through any external circuitry. This works
full duplex at the full data rate. It tests the complete
transmitter, receiver and the external path. Equality between the transmitted and received frames implies that
a large portion of the chip operates correctly. In addition, internalloopback can be used in conjunction with
inhibiting the source address insertion and/or CRC insertion by the chip. For example, in internalloopback,
if a frame is transmitted with an erroneous CRC (using
CRC inhibition), the CRC checking mechanism must
detect a CRC error. In internalloopback the transmission and reception occurs at one fourth the programmed data rate. The Dump Command causes the
82588 to write 63 bytes of its internal registers to memory. This is a very powerful capability that can serve as
the basis for comprehensive diagnostics.
There are parts of the chip, in particular the logic, that
uses the Backoff random number generator that cannot
be checked from the outside. The Diagnose Command
initiates a self test procedure that exercises these otherwise unaccessible registers and counters, and reports
the result.

6.6.2 Configuring the 82588
This is done using the CONFIGURE command. This
command initiates the writing of the configuration pa. rameters into the 82588 using DMA. The configuration
parameters are shown in Figure 6-10.
Configurable
Default Values
Parameters
on Reset
1.
2.
3.
4.
- 5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16,
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.

Serial Interface
Sampling Rate
Oscillator Range
FIFO Limit
Chaining
Buffer Length /
Preamble Length
Address Length
No Source Address Insertion
Promiscuous Mode
Broadcast Disable
CRC-16/CRC-32
No CRC Insertion
Padding
Bitstuffing/EOC
Min Frame Size
Interframe Spacing Time
Slot Time
Number of Retries
Linear Priority
Back-off Method
Manchester/NRZI
Diff. Manch/Manchester
CRS Filter
Internal CRS
COT Filter
CDBBC
Internal COT
INT Loopback
EXT Loopback
Transmit on No CRS
Exponential Priority

0
8
6
0
0
0
0
0
0
0
64
96
512
15
0
0
0
0
0
0
0
0
0
0
0
0
0

'these parameters must be configured after RESET
Figure 6-10. Configuration Parameters
6-14

82588 REFERENCE MANUAL

BIT

5

BYTE

o

I

I

I
I

I
I

4

I

BYTE

COU~T (L.S.B)

I

I

I BYTE
SERIAL
MODE

CHNG

I

3

4

EXT
LP.BCK

5

BOF
METD

6

I~TER

,

,

8

I FRAME

.'

,

RETRY NUMBER

9

PAD

10

COT
SRC

BIT
STUFF

I

11

I

NCRC
INS

CDTF

I
MINIMUM
I

,

I

I
I

I

I

I

I

,

,

I

I.

MAN
/NRZ·

I
FRAME

I
I.

I

S'LOT TIME

CRS
SRC

I

I
I

I

TON
NCRS

I

I

I LIN PRIO I

CDBBC

CRC16

I
I

ADD LEN

SPACING

.'

I
I

I

DIF.MAN
/MAN

I

I

. I

NO SRC
ADD INS

SLOT TIME (L)
I

,I

I
I

I

P~IO

E~P

I

FIFO ILiMIT
I
I

LENGT~

BUFFER
I
I
PREAM LEN
I

INT
LP.BCK

7

I
I

OSC
RANGE

SMPLG
RATE

I

COU~T (M.S.B) I

I
2

o

2

3

LENGTH
I

CONF'G PARAMETER FORMAT

(~)

BC
DIS

I

CRSF

PRM

I

I

I

I

I
231368-8

Figure 6-11. Configuration Block

All but 5 parameters have a default value after reset.
Figure 6-11 shows the configuration block in memory
on issuing the configure command. The first two bytes
contain the number of bytes (byte count) which follow.
Note that all the parameters not having a default value
on reset are contained in the first bytes after the byte
count field. The minimum byte count is 1 and maximum 10 - values greater than 16 are interpreted as
module 16. (Meaning only the 41sb bits are used). After
reset a configure command with byte count of minimum I is essential for the operation of the 82588.

2.

6.6.3 Configuration Parameters
1.

In High Speed Mode, the Clock Generation, Data
Encoding/Decoding, Carrier Sense and Collision
Detect, are generated externally.
o - mode 0, high integration
1 - mode 1, high speed
Default setting: None
Sampling Rate - Byte 2, Bit 5
Valid only in High Integration Mode. It specifies
the ratio between the frequency of the sampling
(serial) clock and the data bit rate:
0·8X
1 - 16X

Serial Interface Mode - Byte 2, Bit 6
This bit selects between high integration (mode 0)
and high speed (mode 1) modes. It also selects the
function of the TXC/xl, RXC/X2 and TCLK/
CRS pins.
In High Integration Mode, the 82588 generates its
Internal clock from the xl, x2 input; encodes/decodes the data waveform (either Manchester, DifferentialManchester or NRZI); generates the Car·
rier Sense and (optionally) the Collision detect
from the incoming RXD signal.

3.

6-15

Default setting: None
Oscillator Range - Byte 2, Bit 4
Valid only in High Integration Mode. It specifies
the frequency range of the sampling (serial) clock:
o . high range (1 - 16 MHz)
1 - low range (DC - 1 MHz)
Default setting: None

82588 REFERENCE MANUAL

4.

FIFO - Limit - Byte 2, Bits 0-3
Specifies the'byte count in the 16 byte FIFOs at
which the 82588 is to resume requests for transfer
of data to/from memory. This parameter is used
for the Transmit FIFO - it's 2's complement is
used for the Receive FIFO.
Default setting: None
- 5. Chaining - Byte 2, Bit 7
If this bit is set, the 82588 switches the DMA during reception -- channel whenever the number of
bytes transferred to memory equals the Buffer
Length parameter.
o - Single Buffer reception
I - Multiple Buffer reception
Default setting: None
6. Buffer Length - ayte 3, Bits 0-7
Specifies the length of the buffer, after which the
DMA channel is switched. This parameter is only
valid when the Chaining bit is set. It is specified in
units of 4 bytes. Buffer length of 0 is interpreted as
1024 bytes.
Default setting: 0 (= 1024 bytes)
7. Preamble Length - Byte 4, Bits 4-5
Selects the length of the Preamble (including the
SFD).
00 - 2 bytes
OJ - 4 bytes
10 - 8 bytes
11 - 16 bytes
Default setting: 10 (= 8 bytes)
8. Address Length - Byte 4, Bits 0-2
Determines the length, in bytes, of the address that
the 82588 refers to. This applies to source, destination, Multicast, and broadcast addresses. Address
length of 7 is treated as zero.
Default setting: 6 bytes
9. No Source Address Insertion - Byte 4, Bit 3
o - Source address is inserted by the 82588 during
transmission
1 - Source address insertion is disabled (source address is provided by the user in the transmit
block)
Default setting: 0
10. Promiscuous Mode - Byte 9, Bit 0
When set, causes 82588 to receive all frames regardless of their destination address.
o - Promiscuous mode off
1 - Promiscuous mode on
Default setting: 0

11. Broadcast Disable - Byte 9, Bit 1
Disables reception of any frame with a broadcast
destination address. Protects against overloading
stations with limited resources. Note that when
promiscuous mode (when set) is on, Broadcast is
always enabled.
o - Broadcast enabled
1 - Broadcast disabled
Default setting: 0
12. CRC-16/CRC-32 - Byte 9 Bit 5
o- 32 bit Autodin - 1l CRC (IEEE 802.3)
1 - 16 bit CCITT CRC (HDLC)
Default setting: 0
13. No CRC Insertion - Byte 9, Bit 4
o - CRC is inserted by the 82588 after the information field
1 - No CRC insertion (CRC is provided by the
user)
Default setting: 0
14. Padding - Byte 9, Bit 7
Valid for bitstuffing only. If padding is set, the
frames shorter than 1 slot time will be padded with
flags to the shortest frame that is longer than 1 slot
time.
o - Padding off
1 - Padding on
Default setting: 0
15. Bitstuffing/EOC - Byte 9, Bit 6
o - End of Carrier Framing (i.e., IEEE 802.3)
1 - Bitstuffing Framing (HDLC, with 01111110
flag and zero bit insertion/deletion)
Default setting: 0
16. Min-Frame-Size - Byte 11, Bit 0-7
The minimum frame size, (not including preamble)
in bytes. The 82588 sets a status bit if a shorter
frame is received. Note that frames shorter than 6
bytes are discarded with no status update.
Default setting: 64 bytes
17. Interframe Spacing - Byte 6, Bits 0-7
Specifies the time period, ,in bit times, that the
82588 must wait after detecting that the Carrier
Sense dropped and before it can begin transmission
or reception of a frame. The minimum value is 12
and any value les~ than that will default to 12.
Default setting: 96

6-16

82588 REFERENCE MANUAL

18. Slot Time - Byte 7, Bits 0-7; Byte 8, Bits 0-2
The slot time for the network, in Bit Times. This
value is used in calculating backoff and Linear Priority delays. It must be longer than the maximum
roundtrip time of a frame in the network plus the
jam time. Zero is interpreted as 2' *11.
Default setting: 512
19. Number of Retries - Byte 8, Bit 4-7
The maximum number of retries, due to collisions,
that the 82588 performs. This information gives
the CPU the choice of aborting transmission after a
programmed number of collisions.
Default setting: 15
20. Linear Priority - Byte 5, Bit 0-2
The number of slot times that the 82588 waits after
Inter Frame Spacing or after Backoff, before enabling transmission. A higher number reduces the
priority.
Default setting: 0
21. BackoffMethod - Byte 5, Bit 7
Determines the method for starting the backoff
timer:
0- According to the IEEE 802.3 standard; immediately
after the end of transmission
1 - After the interframe spacing period expires
Default setting: 0
22. Manchester/NRZ(I) - Byte 9, Bit 2
This bit specifies the data encoding/decoding
method - it is mode dependent:
High Integration
High Speed
oNRZI (*)
NRZ

24. CRS - Filter - Byte 10, Bits 0-2
Specifies the required width of CRS in bit times,
before it is recognized as being active. Carrier sense
deactivation is recognized immediately.
Default setting: 0
25. CRS Source - Byte 10, Bit 3
Valid only in High Speed Mode. Specifies whether
Carrier Sense is to be performed internally or externally (via CRS pin).

26.

27.

28.

29.

Manchester
Manchester (* *)
* Bitstuffi'ng should also be applied
• * Manchester encoding is performed on transmitted data (TXD)
1-

NRZ data should, however, be provided for reception (External Manchester decoding)
23. Differential Manchester/Manchester - Byte 5, Bit
3
Valid only in High Integration Mode provided that
Manchester is set in preceding parameter. This bit
specifies the data encoding/decoding method:

30.

o - Manchester
1 - Differential Manchester
Default setting: 0

6-17

0- External
1 - Internal
Default setting: 0
CDT-Filter - Byte 10, Bit 4-6
Specifies the required width of CDT, in bit times,
before it is recognized that a collision has occurred.
Default setting: 0
CDT Source - Byte 10, Bit 7
Specifies for both High Integration and High Speed
Modes whether Collision Detect is to be performed
internally or externally (via CDT pin):
0- External
1 - Internal
Default setting: 0
CDBBC - Byte 8, Bit 3
Valid only in High Integration Mode. Specifies
whether Collision Detect by Bit Comparison is to
be performed.
0- CDBBC off
1 - CDBBC on
Default setting: 0
INT - Internal Loopback - Byte 4, Bit 6
When set, the 82588 disconnects itselffrom the serial link and logically connects TXD to RXD and
TXC to RXC .
Note: If set, it overrides EXT-Ioopback
o - Internal Loopback off
1 - InternalLoopback on
Default setting: 0
EXT - External Loopback - Byte 4, Bit 7
When set, the 82588 will transmit and receive
simultaneously, at full rate. This allows checking of
external hardware as well as the serial link to the
transceiver interface. The user is responsible for external transmit-receive interconnection. It is overridden by INT-Loopback.
o - External Loopback off
1 - External Loopback on
Default setting: 0

82588 REFERENCE MANUAL

four status registers (STATUS 0 ~ STATUS 3),
which are all read by the CPU, from the same address.
An internai two bit POINTER is used to determine
which register is bei~g read. The pointer is advariced to
the next status register automatically when status is
read. It can also be set explicitly by a field in the. command. Status pointer progress may be disabled by a
command that fixes it to a particular status register and
allows reading of the same' register. Information read
from any of the first 3 status registers is valid provided
Interrupt signal is high or Bit 7 of Status 0. is set. Information of status register 3 is continuously updated, provided the register pointer is not fixed at three.

31. Transmit on No CRS -Byte 9, Bit 3
When set, allows transmission even if there is no
CRS back from the transceiver. Required for transceivers that do not return carrier during transmission.
o - Transmit only when CRS present
1." Transmit only when no CRS present
Default setting: 0
32. Exponential Priority - Byte 5, Bit 4-0
Extends the range from which the random number
fOl: back-off is selected (Le., first collision is biased
to a number different than 0, 1)
Default setting: 0

Status is updated and interrupt raised following an
event only when the interrupt signal is low. When the
interrupt is high, the CPU can read the status. The
interrupt is cleared by a command from the CPU where
the INTERRUPT ACKNOWLEDGE bit is set. Note
that it is the responsibility of the CPU to clear interrupt
in order to prevent a dead lock.

. 6.7 CONTROLLING THE 82588
This .chapter specifies how to control .the 82588, from
the user's point of view. It starts with the definition of
the command and status registers. It then specifies the
behavior of the 82588 during execution of operations
and reception 'of frames. The next chapter provides the
detailed format and meaning of all the operations and
their status.

The 82588 interacts with the DMA controller ,via two
REQUEST/A<;::KNOWLEDGE lines (referred to as
two CHANNELS). The 82588 requests the·.transfer of
bytes, and the DMA performs and acknowledges the
transfer. Frames and parameters are transferred via the
two channels from/to memory. Commands allocate a
specific channel for each operation.

The 82588 performs OPERATIONS, such as transmitting a frame, enabling reception, configuring the chip,
performing diagnostics, or aborting an operation. An
operation is initiated by the CPU, by writing a COMMAND into the command register in the 82588. There
are three groups of operations: EXECUTION, RECEPTION, and STATUS POINTERS CONTROL (in
addition to a Software Reset). The first two groups correspond to two logical units ofthe 82588: the EXECUTION UNIT and the RECEIVE UNIT. The third
group provides control for the status registers.

The 82588 can be configured to support receive buffer.
CHAINING. In this mode, two channels must be allocated to the reception offrames and the 82588 switches
channels when a buffer is full. It issues a "Request Alternate Buffer" interrupt, in order to allow the CPU to
s.et up the alternate buffer 01)0 the other channel.

6.7.1 The Command Register

There is a set of EVENTS that may occur asynchronously in response to commands (typically as a result of '
the behavior of the ,link). These events include: end of
incoming frame, frame aborted, execution of Ii command is completed, execution aborted. The 82588 reports on these events by updating a set of status registers and raising the INTERRUPT signal. There are
Format:
7

5

6

INT.
ACK.

P+R

This section specifies the format of the 82588 command
set. A command is given to the 82588 by writing into
the command register. The command can be issued at
any time, but in case it is not accepted, the operation is
treated like a NOP and will be ignored (although the
INT and the PTR will be updated).

3

4

2

o

CHNL

COMMAND FORMAT

231368-9

6-18

82588 REFERENCE MANUAL

The last operation is software reset:
RESET

6.7.1.1 OPERATIONS (BITS 0-3)
The OPERATION field initiates a specific operation.
There are three groups of operations that can be initiated independently: EXECUTION, RECEPTION, or
STATUS POINTER CONTROL.

RESET can always be issued. It has the same effect as a
hardware reset.
Operations that are not accepted are simply ignored,
(although INT and PTR are updated).

The 82588 implements the following EXECUTION operations (shown with their codes):
NOP
0
1
lA-SETUP
CONRGURE
2
MC-SETUP
3
TRANSMIT
4
TOR
5
DUMP
6
DIAGNOSE
7
12
RETRANSMIT
ABORT
13

6.7.1.2 CHANNEL ALLOCATION (BIT 4)
The CH field selects the channel for the operation that
is requested. Note this field applies only for lA-SETUP, CONFIGURE, MC-SETUP, (RE) TRANSMIT,
DUMP and RCV-ENABLE. If the selected channel is
already allocated the operation is ignored (acts like
NOP).
6.7.1.3 SETTING THE POINTER
The PTR field specifies the new value of the internal
pointer. The pointer selects the next status register to
be read. It is advanced (module 4) automatically when
status is read. Automatic advancement may be disabled
.
by issuing the FIX PTR command.

Execution operations except ABORT are accepted only
when the Execution unit is IDLE. ABORT is only accepted if the Execution unit is active.
Following are the reception operations (and their
codes):
RCV-ENABLE
8
ASSIGN ALT BUF
9
(chaining only)
RCV-DISABLE
10
STOP-RCV
11

6.7.1.4 ACKNOWLEDGING INTERRUPT (BIT 7)
The INT-ACK bit, if set, causes the interrupt hardware
signal and the interrupt bit to be cleared. This is the
only way to clear the interrupt bit and reset the interrupt signal other than by a reset.

RCV-ENABLE is accepted only when the Receive
Unit is IDLE. The other receive operations are only
accepted if the Receive Unit is NOT IDLE.
Status Pointer Control Operation:
FIX PTR
RLS PTR

14

6.7.2 The Status Registers
There are four Status Registers that may be read by the
user. They are numbered 0-3. The register that the
internal pointer points to, is read by doing a "read"
from the 82588. STATUS I and STATUS 2 are also
called "result Registers."

15 (1)
15 (0)

The bit in brackets is Bit #4 of the command (channel
bit).
Format:

STATUS 0 1

STATUS 1 1

STATUS

21

INT.

0

4

7
Rev

EXEC

CHNL

EV~NT

RES~LT 1
RES~LT 2

STATUS 3

231368-10

6-19

82588 REFERENCE MANUAL

The 82588 provides the information about the'last operation that was executed, or the last frame received,
via the first three status registers. The fourth status register provides the state of the chip itself.

6.7.2.1.4 Receive (Bit 6)

The RCV bit indicates that the reception of a frame was
completed, or a ,new buffer is required to allow reception to proceed. Event numbers 8-10 provide the details.

STATUS 0, STATUS I, and STATUS 2 are only updated when INT = O. STATUS 3 is updated whenever
an update is needed. Status register 3 is not updated if
the pointer is pointing to it.

6.7.2.1.5 Interrupt (Bit 7)

The INT bit is set together with the hardware interrupt
signal. Setting the INT bit indicates the occurrence of
an event. This bit is cleared by any command whose
INT-ACK bit is set.

6.7.2.1 STATUS 0

The first status register (STATUS 0) includes the interrupt bit and the cause of the interrupt. Information
about the relevant channel is also provided.

6.7.2.2 STATUS 1/STATUS 2 (RESULT
REGISTERS)

6.7.2.1.1 Event (Bits 0-3)

These registers hold the result of completing an operation. STATUS 1 is the least significant byte and
STATUS 2 is the most significant. The Result Registers
are only updated when any of the following occur:
- TRANSMIT-DONE
TDR-DONE
RETRANSMIT-DONE
END OF FRAME

The event field specifies the reason why the 82588
needs attention of the CPU.
The following events may occur (shown with their
codes):
IA-SET-DONE - 1
CONFIGURE-DONE - 2
MC-SETUP-DONE- 3
TRANSMIT-DONE - 4
TDR-DONE - 5
DUMP-DONE - 6
DIAGNOSE-PASSED - 7
END OF FRAME - 8
REQUEST ALT BUFFER - 9 (chaining only)
RECEPTION ABORTED - 10
RETRANSMIT-DONE - 12
EXECUTION-ABORTED - 13
DIAGNOSE-FAILED - IS

6.7.2.3 STATUS 3

The last status register holds the state of the 82588:
three lower bits for the Execution unit, five higher bits
for the Receiver unit.
6.7.2.3.1 Execution State (Bits 0-1)

The EX-CH field specifies the state of the Execution
Unit. It can take one of the following values:

6.7.2.1.2 Channel (Bit 4)

o - IDLE:

The CH bit indicates which channel was allocated for
the operation that caused the event. Valid for all events
except for Request Alternate Buffer.

2 - ACTIVE:

The Exec Unit is disabled
The Exec Unit is actively executing an
operation

3 -ABORT IN
The execution of an operation was
PROG:
aborted, but the completion event was
not yet issued.

6.7.2.1.3 Execution (Bit 5)

The EX bit indicates the completion of an execution
operation. Event number 13 indicates the abortion of
the operation.

6-20

82588 REFERENCE MANUAL

The parameters (for lA-SETUP, CONFIGURE, MCSETUP, TRANSMIT and RETRANSMIT) are organized in a block that starts with a 16 bit byte-count.
The byte count specifies the length of the rest of the
block. Before beginning the operation, the DMA pointer of the selected channel must point to the first byte of
the byte count. There is no restriction on the memory
structure of the frame as long as for every DMA request from the 82588 it receives the next byte of the
frame. Transferring the bytes is the job of the DMA
controller or the CPU. If the DMA does not keep up
with transmission (i.e., causes an underrun), the transmission is terminated and an underrun is indicated.

6.7.2.3.2 Exec Channel (Bit 2)
The EX-CH bit indicates which channel is allocated for
transferring parameters fromlto memory. It is only valid when the Execution Unit is active, performing a
parametric execution.
6.7.2.3.3 Buffer Chaining - Number of Buffers
(Bit 3-4)
Specifies the number of available buffers for reception,
when configured to "Buffer Chaining." It can take one
of the following values:
o - no buffers are available
I - one buffer is available (automatic on
RCV-enable)
2 - two buffers are available

The 82588 requests the 2 bytes of byte-count on the
allocated channel and determines the length of the parameter block. It then requests the parameters and
starts the executiOil. of the operation.
Upon completion of the operation, (when interrupt is
LOW) the Exec unit does the following: it updates
STATUS 0; updates STATUS I and STATUS 2 (for
TRANSMIT, TDR or RETRANSMIT); raises the interrupt signal; and goes IDLE.

6.7.2.3.4 Receive State (Bits 5-6)
The'RCV-STATE field specifies the state of the Receive Unit. It can take one of the following values:
o IDLE
The Receive Unit is disabled
1
READY
The Receive Unit is set up
for an incoming frame
The Receive Unit is actively
2
ACTIVE
transferring bytes to
memory (provided buffer is
available)
The Receive Unit is active
3 - STOP IN
PROGRESS and will be disabled
following the reception of
current frame

The NOP operation is ignored, exactly like any operation that is initiated during the execution of another
one.
The ABORT operation causes a request for abortion of
the operation that is in progress. In some cases the operation cannot be aborted anymore (e.g., for a Transmit
operation when the whole frame was already transmitted). In these cases, the Abort operation is ignored.
Non-parametric executions like: TDR and DIAGNOSE cannot be aborted.

6.7.2.3.5 Receive Channel (Bit 7)

The DUMP operation causes a set of internal registers
to be written to memory over the allocated channel. It
is completed by updating STATUS 0 and raising the
interrupt.

The RCV-CH bit indicates which channel is allocated
for transferring incoming data to system memory. It is
valid only when the Receive Unit is NOT IDLE. When
configured for Buffer Chaining, at least one buffer
should be available. 82588 assumes that one buffer is
available whenever the receiver is enabled. The DMA
controller must be initialized and ready to transfer data
prior to enabling the receiver.

6.7.4 Reception of Frames
The 82588 receives and passes to memory all frames
whose address matches the individual, multicast or
broadcast address. Reception of frames is pipelined,
i.e., the reception of a frame can start before the end of
frame processing of the previous frame is done. 82588 is
configured to either "chaining" or "consecutive" mode.
In consecutive mode the whole incoming frame is
passed to a single buffer in memory via the allocated
channel. In chaining mode, the frame is received and
deposited in a series of fixed size buffers using the two
available DMA channels alternately. The chained buffer size if configurable in steps of 4 bytes to a maximum
of IK bytes.

6.7.3 Performing Execution
Operations
The 82588 has a repertoire of 11 execution operations.
These operations perform transmission, configuration,
diagnostics and abortion. All the operations are initiated by writing into the Command Register. This causes
the Execution unit to become Active. Some of the operations read parameters from memory.

6-21

82588 REFERENCE MANUAL

byte transfers to memory' continues. If a Disable Receive command is issued then the rest of the frame is
ignored.

6.7.4.1 CONSECUTIVE MODE (SINGLE BUFFER
MODE)

Before the reception starts, the DMA pointer of the
respective channel points to the first byte of the available structure of the frame. Transferring the bytes is the
job of DMA,controller or the CPU.

This process of switching from channel to channel continues until the end of the frame arrives. At this point,
two "frame status" bytes are transferred to memory;
buffer switch occurs; STATUS 0 is updated; the byte
count of the frame is loaded into STATUS 1 and
STATUS 2; if a new buffer is available, then the 82588
is ready to receive the next frame. Otherwise, reception
is suspended. In both cases, and End of Frame event is
issued.

If the receiver is ready and a frame arrives, the 82588
requests the transfer of bytes to memory, using DMA.
Mter transferring all the bytes (addresses, control and
information) the 82588 transfers two "frame status"
bytes to memory. Upon completion of the reception,
and when interrupt is LOW, the Receive Unit does the
following: it updates STATUS 0 with an "end of
Frame" event; loads the frame byte count, which includes the frame status bytes, into STATUS 1 and
STATUS 2; raises the interrupt signal; and goes to
READY state. (The DMA Controller points to the
byte following the frame status.)

If the receiver is not ready, when the first byte of the
frame arrives, then the whole frame is ignored - status
is not updated. Disabling reception after the first byte
was passed to memory causes the rest of the frame to be
ignored, and an interrupt with "Receive Aborted"
event to be issued.
If reception is suspended (Ready, but with no buffers
assigned) when the first byte of the frame arrives, the
receiver interrupts the CPU for a buffer. The user may
provide a buffer or disable Reception.

If the receiver is not ready when the first byte of the
frame arrives, then the frame is not received. No status
is updated. Disabling reception after the first byte has
passed to memory, causes the rest of the frame to be
ignored. An INTERRUPT with "Receive Aborted"
event is issued.

6.8 OPERATIONS AND STATUS

Reception can begin even when the interrupt that indicates the completion of execution or reception is still
pending. This capability allows pipelining of the transfer to memory of a frame by the 82588 and the DMA
controller, with the CPU handling the completion of
the previous execution or reception (including the interrupt latency). The entire frame gets deposited in a single memory buffer of 64K bytes maximum size.

This section specifies all the operations that the 82588
can execute and the events it can generate. The semantics, as well as the format of the parameters, status, and
result, are specified. The 4 bit op-code is shown in parentheses.

6.7.4.2 CHAINING MODE (MULTIPLE BUFFER
MODE)

6.8.1 Operations

The value of byte count (where applicable) does not
include the 2 bytes of the field itself. All shaded areas
mean they are "reserved."

6.8.1.1 NOP (00)

Before the reception starts, the DMA pointer of the
first DMA channel points to the first byte of the available buffer. If receiver is ready (one buffer allocated)
and a frame arrives, the 82588 generates an interrupt
with a "Request Alternate Buffer" event that notifies
the CPU to allocate an additional buffer. Simultaneously, the 82588 requests the transfer of bytes to memory.
Note that if an additional buffer is available when the
first byte arrives, then the "Request Alternate Buffer"
event is not issued. This may happen when more than
one frame is received sequentially.

This operations does not affect the 82588. It has no
parameters and no result.
6.8.1.2 lA-SETUP (01)

This operation sets up the individual address of the
82588. This address is inserted as the source address'
during transmission and used for address filtering during reception. (Both can be disabled via configuration
parameters.) The Byte Count should match the "Address Length" configuration parameter. The length of
the address (in bytes) that is set up is determined by the
minimum of:

When the currently used buffer is full and an additional
buffer is available the 82588 makes it the current one
(i.e., switches buffers) and continues transferring bytes
to memory using the other DMA channel. If an additional buffer is not available, the receiver deasserts the
DMA Request signal and suspends further data transfers to memory. The CPU should then provide another
buffer or disable receive. If a new buffer is provided,

"Address Length" configuration parameter or the value of the Byte Count field.
Only the 4 least significant bits of the byte count are
used.
6-2~

82588 REFERENCE MANUAL

NOTE:
The first bit of the first byte must be a zero.
The format of the parameter is as follows:
I

I

I BYTE

COU~T (L.S.B.) I

.L

L

CaU~T (M.S.B.) :

I

I

I
I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

-'I
I

: BYTE

I

INDIVIDUAL ADDRESS LSB BYTE

.

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I
I

I

I

I
I

I
I

I
I

I
I

I

I

I

I

I

I

I

I

I

INDI~IDUAL ADDIRESS MSB ~YTE
I

I

I

0

I

I

I

I

I

I

231368-11

the byte count. If the byte count is less than 10, then
only part of the parameters are updated. Only the least
significant 4 bits of byte count are used.

An interrupt with the event IA-SETUP-DONE is issued when this operation is done (unless ABORT was
executed in the meantime).

Note that 3 bits (Mode, SMPLG RATE, and OSC
RANGE) have an effect only during the first Configure
command after RESET.

6.8.1.3 CONFIGURE (02)

This operation configures the 82588. The length of the
configurations block that is modified is determined by
The format of the parameters is as follows:
I
I BYTE

BYTE
I

I

SERIAL

CHNG

MODE

I

SMPLG
RATE

I

COU~T (L.s.B)

COU~T (M.S.B) :
I

asc

RANGE

I
I

~UffER

I

I

LENGT~

I

I

I

I

I
EXT
LP.BCK

I

INT
LP.8CK

BOf
METD

PREA~

L

I~TER

OfF. MAN
/MAN·

I fRAME

RETRY

I

I
I

I

I
COBBC

10T TIME

I

I I
CRC16

NCRC
INS

TON

M:NIMUM
I

MAN

NeRS

INRZ'

CRS
SRC

COTF

I

J

I

I
I

I

~UMBER
L

BIT
STUFf

COT
SRC

L

I

SILOT TIME (L)

I

I

PAD

I LIN PRIO I

J

SPACING

I

I

I

I ADD LEN:

ADD INS

P~IO

E!P

I

NO SRC

LEN

I
I

FIFO ILiMIT
I
I

I
I
fRAME I
I

BC
DIS

I

PRM

CRSF

I
I

I
I

I

I

LENGTH

I

6-23

I

(~)

231368-12

82588 REFERENCE MANUAL

The interpretation of the fields is as follows:
Byte 0

FIFO Limit (Bits 0-3)
OSC RANGE (Bit 4)
SMPLG RATE (Bit 5)
MODE (Bit 6)
CHAINING (Bit 7)

FIFO limit
High or low frequency range of oscillator
Sampling rate. 8 X or 16 X external oscillator
High integration or high speed mode
Receive buffer chaining

Byte 1

BUFFER LENGTH

Buffer length used for chaining

Byte 2

ADR LEN (Bits 0-2)
NO SRC AD DR INS (Bit 3)
PREAM LEN (Bits 4-5)
INT LP BCK (Bit 6)
EXT LP BCK (Bit)

Address length
Address control location
Preamble length
Internal Loopback
External Loopback

Byte 3

LIN PRIO (Bits 0-2)
DIF MAN/MAN (Bit 3)
EXP PRIO (Bits 4-6)
BOF METD (Bit 7)

Linear priority
Differential/Manchester Encoding
Exponential Priority
Exponential backoff method

Byte 4

INTER FRAME SPACING

Inter frame spacing

Byte 5

SLOTTM (L)

Slot time, low byte

Byte 6

SLOT TM (H) (Bits 0-2)
CDBBC (Bit 3)
RETRY NUM (Bits 4-7)

Slot time, high part
Collision Detection by bit comparison
Number of transmission retries on collision

Byte 7

PRM (Bit 0)
BC DIS (Bit 1)
MANCH/NRZ (Bit 2)
TON NCRS (Bit 3)
NCRC INS (Bit 4)
CRC-16/CRC-32 (Bit 5)
BIT STF (Bit 6)
PAD (Bit 7)

Promiscuous mode
Broadcast disable
Manchester/NRZ or Manchester/NRZI encoding
Transmit on NO CRS
No CRC insertion
CRCtype
Bit stuffing
Padding

Byte 8

CRSF (Bit 0-2)
CRS SRC (Bit 3)
CDTF (Bits 4-6)
CDT SRC (Bit 7)

Carrier sense filter bits
Carrier sense source
Collision detect filter bits
Collision detect source

Byte 9

MIN FRAME LEN

Minimum frame length

A Configure-Done interrupt is issued when the operation is done (unless ABORT was executed in the meantime).

the "Address Length" configuration parameter and n is
a integer counting from zero.
NOTE:
The least significant bit in the first byte of EACH MC
address must be a ONE.

6.8.1.4 Me-SETUP (03)

This operation clears and sets up a new 64 bit Multicast
Address table. The parameter block may include a
number of MC-addresses. Each contributes one bit to
the Hash Table.

The number of MC addresses that are set up during the
operation is equal to Byte Count divided by AL, rounded down, i.e., if the last MC address is incomplete, it is
ignored.

The first byte of the n-th MC-address in the parameter
block begins at byte number n X AL + 1, where AL is

6-24

82588 REFERENCE MANUAL

The format:
7

4

o

2

BYTE COUNT (LS.B.l

BYTE COUNT (M.S.B.l

-']"m5

' - -_ _- ' -_ _ _.L....-:-_-I._ _ _- ' -_ _- - '_ _ _......._ _......JL-_ _

L-_ _-L_ _ _

~

__

~

MCA:(02 l

___ ___
~.

~

__

~

_ _ __ L _ _

~

] ALBYTES

MC~ (Nl
231368-13

The MC-Setup-Done interrupt is issued after completing this operation (unless ABORT was executed in the
meantime).

• Information-

6.8.1.5 TRANSMIT (04)

·CRC-

This operation transmits one frame. The parameter
block includes the following parameters:
• Destination Address- length determined by the
"Address Length" configuration parameter.
ONLY IF the no source ad• Source Addressdress insertion configuration
parameter is one. The length
is determined by "Address
Length".
7

5

The length is determined by
the Byte Count minus Destination Address Minus Source
Address (if any) minus CRC
(if anYl.
ONLY IF the "No-CRC-insertion" configuration parameter is one. The length is
determined by the "CR,C-16/
32" parameter.

To summarize, the typical transmit operation parameter block includes the Destination Address, and Information fields:

.4

2

3

I

o

I

BYTE COUNT (LS.B.l
BYTE COUNT (M.S.B.l
DA (BYTE 1)

231368-14

6-25

82588 REFERENCE MANUAL

The transmit operation will either complete the execution or be aborted by a specific ABORT operation. A
Transmit-Done or "Execution Aborted" interrupt is issued upon completion of this operation.

6.8.1.11 ReV-ENABLE (8)
This operation enables the reception. It is ignored if the
receive state is already Ready or Active.
The 82588 receives only frames that pass the address
filtering. The frame and its status are placed in memory
(by the DMA Controller or CPU) and the byte count of
the frame is placed in the Result Registers. The completion of frame reception causes an "End of Frame"
event.

6.8.1.6 TDR (05)
This operation activates the Time Domain Reflectometer, which is a mechanism to detect open or short circuits (and their distance from the diagnosing station)
on the link. There are no parameters. A TDR-Done
interrupt is issued upon completion.

6.8.1.12 ASSIGN ALTERNATE BUFFER (9)
6.8.1.7 DUMP (06)

This operation assigns an alternate buffer if reception is
ready (and the chip is configured to chaining mode).
This operation may be issued when an execution is active and the Ex channel is used for transfer of parameters. In this case ASSIGN ALT BUF will cause the
execution to be aborted (the same as ABORT operation). If the on-going execution is thus aborted, an "execution-aborted" interrupt occurs after the reception is
complete. An executing command so aborted can then
be restarted.

This operation causes dumping of a set of internal 'registers. There are no parameters. The 63 registers are
dumped to memory on the assigned channel.
The DUMP operation will either complete the execution or be aborted by a specific ABORT operation. A
DUMP- DONE or "Execution Aborted" interrupt is
issued upon completion of this operation.
'

This operation has no parameters and no results. It is
usually issued by the CPU following a "Request Alternate Buffer" event.

6.8.1.8 DIAGNOSE (07)
The Diagnose Command checks the 82588 timers hardware which includes:
•
•
•
•
•
•
•

Exponential Backoff Random Number Generator.
Exponential Backoff Timeout Counter.
Slot Time Period Counter.
Collision Number Counter.
Exponelltial Backoff Shift Register.
Exponential Backoff Mask Logic.
Time Trigger Logic.

6.8.1.13 ReV-DISABLE (10)
This operation causes the reception to be disabled. If
transfer of a frame to memory has already begun, then
it causes a Reception Aborted event. It has no parameters and no results.
6.8.1.14 STOP-ReV (11)
This operation requests the disabling of reception. If
reception is actually in progress, then it will continue
until the end of the frame. If the reception is not in
progress, then this command acts like the RCV-DISABLE command.

6.8.1.9 RETRANSMIT (12)
This operation is almost identical to the TRANSMIT
operation. The only difference is the RETRANSMIT
does not reset the retry counter and the. exponential
back-off mechanism.

6.8.1.15 RESET (14)
The Retransmit operation will either complete the Execution or be aborted by a specific ABORT operation. A
RETRANSMIT-DONE or "Execution Aborted" is issued upon completion of this operation.

This command resets the chip. It has the same effect as
hardware reset. Note that the reset command does not
reset bits of status registers 0, 1 and 2 other than the
Int. field.

6.8.1.10 ABORT (13)

6.8.1.16 FIX PTR (1, 15)

This operation causes the attempt to abort the completion of an operation under execution. It is valid for: IASETUP,
CONFIGURE,
MC-SETUP,
(RE)TRANSMIT and DUMP. It is ignored for any of
the above, if the transfer of parameters was completed.

This operation stops the cyclic progress of the read
pointer of the STATUS Registers. The pointer is assigned to the register specified in the Pointer Field of
the Command.

6-26

82588 REFERENCE MANUAL

The channel bit must be set to "1". After this command
every read from the status port accesses only the selected (PTR) register. Status 3 register updates stop when
it is selected.

6.8.2.2 ILLEGAL RCV COMMANDS
6.8.2.2.1 Receive Enable

Will be rejected if one of the following exists:
1. Receive Machine is not idle.
2. The RCV Channel equals the Exec Channel and the
Exec Machine already performs a parametric execution.

6.8.1.17 RLS PRT (0,15)

This operation releases the assignment of the read
pointer to a specific status register and restores the cyclic progress mode (any read advances the pointer to
the next register).

6.8.2.2.2 Assign Alternate Buffer

The channel bit must be set to "0". This command with
pointer = 0 is executed automatically on reset.

Will be rejected if one of the following exists:
1. The RCV Machine is not configured for Buffer
Chaining.
2. The RCV Machine is in IDLE state.
3. An alternate buffer is already assigned.

6.8.2 Illegal Commands
6.8.2.1 ILLEGAL EXECUTIONS

6.8.2.2.3 Receive Disable & Stop Receive

6.8.2.1.1 Non-parametric Executions (TDR,
DIAGNOSE, ABORT)

Will be rejected if the RCV Machine is in IDLE state.

TDR, Diagnose will be rejected if the Execution Machine is not idle.

6.8.3 Event Statuses

Abort is rejected if issued when Execution Machine is
not active, or a non-parametric execution is performed,
or transfer of parameters has already been accomplished.

This section specifies all statuses that indicate the occurrence of events This status is always accompanied
by an interrupt bit.

6.8.2.1.2 Parametric Executions

6.8.3.1 IA - SETUP-DONE (01)

Will be rejected if one of the following exists:

This event indicates the completion of an lA-SETUP
operation. ;

1. Execution Machine is not idle.
2. The Exec Channel equals the RCV Channel and the
RCV Machine is not idle, and it is either configured
for Non-chaining Mode or it has at least one channel.
3. The RCV Machine is configured for chaining and it
is either active or has been assigned both channels.

6.8.3.2 CONFIGURE-DONE (02)

This event indicates the completion of a CONFIGURE
operation.
6.8.3.3 MC-SETUP-DONE (03)

This event indicates the completion of an MC-SETUP
operation.

6-27

·82588 REFERENCE MANUAL

The two Result Registers provide information about errors and other diagnostic information. The format of
the Result Registers is as follows:

6.8.3.4 TRANSMIT·DONE (04)

This event indicates the completion of the TRANSMIT
operation..

7
RESUlT1

TX
DEF

RESUlT2

RCNT
COll

6

5

4

3

o

2

UNDER
RUN

TRANSMIT RESULTS FORMAT

231368-15

Where:
NUMBER OF COLL

MAX COLL

HRT BEAT
TX DEF
UNDERRUN (*)

LOST CTS (*)

LOST CRS (*)
Number of collisions the
frame has experienced (modulo 16).
Transmission failed due to a
collision. The configured
number of retries is exhausted.
Collision detect test passed after the previous frame.
Transmit deferred due to link
activity.
Indicates that the DMA did
not keep up with transmission
data rate.
Clear-to-Send lost during
transmission.

7

6

5

RESUlT1

RESUlT2

Carrier Sense lost during
transmission, or not set until
end of preamble.
Transmission executed okay.
The transmission of the last
frame. experienced a collision.

TXOK
COLL (*)

"Number of Collisions" provides redundant information. The setting of one of the bits marked (*) will cause
TX-OK bit to be reset.
6.8.3.5 TDR·DONE (OS)

This event indicates the completion of a TDR operation.
The Result Registers indicate whether there is a problem, which type and where.

4

3

2

o

TOR el)

OK

TOR RESULTS FORMAT

231368-16

Where:
TDR

6.8.3.6 DUMp·DONE (06)

: Twice the radial distance between the 82588
and the location of the problem (in bit times).
SHORT: Indicates there is a short circuit on the
transmission line. (Carrier Sense Signal
dropped)
-

OPEN
XCVR
OK

This event indicates that the DUMP operation is completed. The result registers are not updated. Contents of
63 internal registers are transferred to memory on the
allocated channel.

: Indicates the transmission line is not properly terminated. (Collision Detect went active)
: Indicates a transceiver problem. (Carrier
Sense was inactive for 2048 bit time period)
: Indicates that no problem was found.
6-28

82588 REFERENCE MANUAL

The format of the dumped registers is as follows:
7

5

6

SERIAL
MODE

CHNG

4

SMPlG
RATE

3

I
FIFO LIMIT

I

I

I

I

I
lENGTH

I

I

I
I

I
I

OSC
RANGE
8UFFER

o

2

I

01

I

PREA~ lEN

INT
lP.BCK

EXT
lP.8CK
80F
METD

I
I
EXP

PRIO

I

I
I

I
INTER

I

I

I

I

NO SRC
ADD INS

ADD lEN

DIF.MAN
/MAN

LIN PRIO

FRAME

I

81T
STUFF

COT
SRC

I

CDTF

I

1

1

I
I

I
I

I

I

SllOT TIME

CD88C
TON
NCRS

MAN
/NRZ·

CRS
SRC

I
FRAME

(~)

8t
DIS

06

PRM

CRSF

I

1

03

I
I

05

NCRC
INS

MINIMUM

I

I
I

04

I

CRC16

I

I

I
I

I
I
SLOT TIME (l)

I
I
RETRY NUM8ER

PAD

02

I

SPACING

I

I

00

08

I

I

I

I
09

lENGTH

1

1

1

1

1

lARD

I

I

I

I

I

I

I
I

I
I

I

I

I

I

I

I
I

I
I

I
I

I
I

I
I

I
I

I

I

I

IA~4

I

I

I

I

I

I

I

I

I

I

DC

I
I

00

IAR2

I
I

I
I

I
I

I

I

I

I

I

I

I

I

I
I
IAR3

I

I

I

DE

OF

I
I

I

I

IAR5

I

I

TX
DEF

HRT
BEAT

MAX
COll

0

RCNT
COll

0

TX
OK

0

NUM

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

6-29

12

13

I
I

11
UNDER
RUN

lOST
CTS

TXCRCI

I

10

COLLISIONS

OF
lOST
CRS

0

I

TXCRCO

I

OA

08

I

I
I
IARI

I
I

07

14
231368-17

82588 REFERENCE MANUAL

7

5

6

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I
I

I

I

I

I

I

I
I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I
I

I
I

I
I

I

I

I

I

I
I

I

I

I

16

I

17

RXC~C 0

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I
I

I

I

I

I

I

I

I
I

I

I

I

I

I

I

18

RXC~C 1

T

I

19

RXC~C 2

I

1A

RXe~C 3

I

1B

TM~R 0

I

1C

TM~R 1

I
I

I
I

I

15

TXe~e 3

I

I

I

TXC~C 2

T

I

I
I

I

I

I
I

o

2

3

4

I

I

1D

TM~R 2

I

1E

TM~R 3

I

I

I

I

1

T

I
I

I
I

..

TM~R 4

I

I

I
I

I

I

I

I
I

I
I

1F

T

I

20

TMPR 5

SHRT
FRM

NO
EOF

1

1

1

1

1

1

21

1

a

RX
OK

1

eRC
ERR

ALN
ERR

a

OVER
RUN

22

I

I

I

I

I
I

I
I

I

I

I

I

I
I

23

HAS~R a

I

I

I

I

I

I
I

I
I

I
I

I
I

I

I

I

I

I

I

I

I

I

24

HAS~R 1

I

I

I
I

I

I
I

I
I

1

I

I

I

I

I

I

25

HAS~R 2

I

26

HAS~R 3

I

I

I

I

I

I
I

I
I

I
I

I

I

J

I

I

27

HASHR 4

I
I
I

I
I
I

1

I
I
I

I

.

I

I

HAS~R 5

1

28

j

I

29

HAS~R 6

6-30

231368-18

82588 REFERENCE MANUAL

7

5

6

I

4

I

3

I

I

.

2

I

I

0

I

HASHR 7

2A

">
:>

2B

•....

O.K.

XCVR

OPEN

{:
1

:

.·::1> '/'"
1

1

2C

SHORT

.'

1

1

1

1/

./

2E

2F

STIR 0

I

I

I

I

I

I

I

I

I
STIR 1

I

I

I

I

I

I

I

I
I

~/;//~;

•

I

I

I

I .

I

I

I
I

I
I

I

I
I

I
I

31

I

I

32

//'///-;
~~~.~~FF.~~~;~~)/>: t~:;;;i,~/~

33

I

I

I

BUFF.~NT.(H)
I

I

I

-I

34

I

I

I

I

I

I

I
I

I

I

I

I

35

I

36

RCV BYTE CNT.(H)

0

0

~~
'//'
. :0

1

,

I
I

~/r

RCV BYTE CNT.~L)
I

I

I
I

1

I

I

I
I

STIR 3

/'///
[t~£j:; ;'//:;;::J;:.
/;

I

I
I

30

STI1R 2

I
I

I
I

20

1

1

0

1

37

;;////.~

trans_l en.
out~ord(dma_O_c~)
dma_rx_mode or 0006h;

memor~

*1

1* start DMA channel 0 *1

endi
do;

1* channel 0 , memory to 588 *1
ch_a_588.

out~ord(dma_O_dpl)
out~ord(dma_O_dph)

o.

out~ord(dma_O_spl)

low (buff_ptr_20bit);
high (buff -ptr _20b it);
trans_len;
dma_tx_mode or 0006h;

Dut~ord(dma_O_sph)
out~ord(dma_O_tc)

out~ord(dma_O_c~)

1* start DMA channel 0 *1

end;
end;

do case direction and 00000001b;
do;
~* channell, 588 to memory *1
out~ord(dma_l_dpl)
lo~ (buff-ptr_20bit);
out~ord(dma_l_dph)
high(buff-ptr_20bit);
out~ord(dma_l_spl)
ch_b_588.
out~ord(dma_l_sph)
0;
out~Drd(dma_l_tc)
trans_len.
out~ord(dma_l_c~)
dma_r._mode or 0006h;
1* start DMA channell *1
end;
do;
out~ord(dma_l_dpl)

out~ord(dma_l_dph)

outword(dma_l_spl)
outword(dma_l_sph)
Dutword(dma_l_tc)
outword(dma_l_cw)
end;

=

1* channell. memory to 588 *1
ch_b_588.
O.
low (buff-ptr_20bit).
high (buff -ptr _20bi t);
trans len;

dma_t~_mode or 0006h,

1* start DMA channel I' *1

end;
end;

return;
231368-30

Figure A-S. Loading and Starting the 80186 DMA Controller

6-44

82588 REFERENCE MANUAL

intr _5BB:

procedure interrupt 13,

declare event byte;
call read_status_5BB,
event = status_5BB(0) and 00001111b),

do case event;
event_OO:
event_Ot:
event_02:
event_03:
event_04:

outUJord(dma_l_cUJ)
(dma tx mode or 0004h),
1* stop DMA channel
outUJord (dma_l_cUJ)
(dma::::t x::::mode or 0004h),
1* stop DMA channe I
outUJord(dma_l_cUJ)
(dma_tx_mode or 0004h),
1* stop DMA channel
dOl
1* transmit done *1
outUJord(dma_l_cUJ)
= (dma tx mode or 0004h), 1* stop DMA channel
if (status_5B8(2) and 10000000b) <> 0
1* collision *1
then if (status_5BB(1) and 00100000b) = 0
1* max collision *1
then intr_588_flag = IX';
1* retransmit *1

*1

end;

event_05:
event_06:
event_O?:

(dma rx mode or 0004h);
(dma::::rx::::mode or 0004h);

outUJord(dma_O_cUJ)
outUJord(dma_O_cUJ)

1* stop DMA channel 0 *1
1* stop DMA channel 0 *1

call rev disablei

1* extract the rx_status bytes 0.1 from the received frame *1
1* frame length is in status_588(O & 1) *1
1* multiple buffer scheme is assumed *1

rx_buff_off = shl(double(status_5B8(2».B)
+
double(status 58B(1»
- 2;
rx buff no = IOUJ(rx buff off I-buff len);
rx::::buff::::off = TX_buff _off mod buff_Ten,
1* status 0 *1
r x_stat (0) = read_b y te (@buffer_588(rx_buff_no). r x (r x_b uff _off) ),
rx_buff_off = rx_buff_off + 1;
if rx_buff_off = buff len
1* status across buff boundaries *1
then do,
rx_buff_off = 0,
rx_buff_no = rx_buff_no + 1;
end;
1* status 1 *1
r x_stat (l) = read_byte (@buffer_588(rx_buff_no). r, (rx_b uff _off> ),

end;

event_l0:
event_1! :
event 12:

event 13'

call allocate_buffer(neUJ_buffer),
1* new_burTer is a procedUre returning the pointer to new buffer *1
outUJord (dma_O_cUJ)
= (dma_rx_mode or 0004h),
1* stop DMA channel 0 *1

do;
1* re-transmit done *1
outUJord(dma_l_cUJ)
= (dma_tx_mode or 0004h),
1* stop DMA channell *1
if (status 588(2) and lOOOOOOOb) <> 0
1* collision *1
then if (status_58B(1) and 00100000b) = 0
1* no max collision *1
then intr_5BB._flag = 'X';
1* retransmit *1
end;
do;
1* execution aborted *1
outUJord(dma 1 cUJ)
(dma tx_mode or 0004h),
intr_588_fl;g-= 'X'i
end;

1* stop DMA channel 1 *1

event 14:
event_1S:
end;

outUJord

(eoir_l86)

= BOOOh,

=

lOOOOOOOb,

output (cs_588)

1* non specific EOr to BOIB6 *1
1* intac:k,

*1

return;
end intr _5BB,

231368-31

Figure A·5. Interrupt Service Routine
6-45

82588 StarLAN
Application Note

7

APPLICATION
NOTE

AP-236

September 1985

Implementing StarLAN with
the Intel 82588, Controller

SHARAD GANDHI
SENIOR APPLICATIONS ENGINEER
DATACOMMUNICATION COMPONENTS OPERATION

Order Number: 231422-001
.

7-1

inter
of a node is drastically reduced because of the availability of VLSI LAN controllers like the 82588. StarLAN
uses standard telephone wire for the transmission medium. This cable is either already installed and ready to
use or it is very cheap to install. StarLAN has the backing of most of the major companies in the industry.
And, in addition, since it meets the IEEE 802.3 standards requirements, it is very fast on its way to become
an industry standard.

7.1 INTRODUCTION
The explosive growth of the personal computer market
has placed a PC on almost everyone's desk in the office.
Working in a stand-alone PC environment for a while
automatically generates a need for linking up the PCs
for very basic reasons, like file sharing, automatic backup, disk-less operation and electronic mail. This has led
to a search for a networking scheme for PCs which
costs not more than 10% of the cost of the PC itself. As
of year end 1984, close to 4.5 million PCs were in existence. Only 5% of these had local area network (LAN)
interfaces. Industry forecasts suggest that by 1990,
nearly 20 million PCs wiJI be interconnected through
LANs. To what extent this comes to pass depends on
achieving low cost networking, ease of design, ease of
installation and achievement of industry standards to
enable inter-connectability of equipment from different
vendors. Traditional Local Area Networks (LAN) like
Ethernet and Cheapernet have proved to be too expensive for the office environment. Not only the nodes are
expensive, but also the cabling. A myriad of non-traditional networks have emerged which are cheap. But
none have captured a significant market, due to the
lack of major company backing and also due to lack of
backing from any of the standards bodies like the
IEEE, CCITT or ISO.

7.1.2 Network Topologies
Networks connect nodes so that they communicate.
There are various ways of interconnection or topologies. Figure 7-1 shows the three most commonly used
topologies; bus, ring and star.

a) BUS

Two recently introduced LANs will have a far reaching
impact on PC networil:ing. Based on the CSMA/CD
(Carrier Sense MUltiple Access with Collision Detection) access method, they are both targets of industry
standardization efforts' through the auspices of the
IEEE 862.3 Working Group: .a) PC Network intro- _
duced by IBM and Sytek for 2 Mb/s in broadband over
a coaxial cable and b) StarLAN introduced by AT & T
with a data rate of 1 Mb/s in baseband over unshielded,
twisted pair, telephone grade wiririg. The INTEL
82588 LAN controller was designed to support both
types of networks equally well, being optimized for operation in the 1-2 Mb/s range, with either baseband or
broadband transmission. It is a VLSI device aimed at
low cost, ease of design, a,nd conformance to the anticipated IEEE 802.3 standards.

b) RING

The objective of this Application Note is to ,illustrate
designing with the 82588 through a practical example.
StarLAN was chosen for this purpose due to its overall
simplicity. The Application Note goes beyond the
82588 based StarLAN interface, describing overall operation of the network, and providing an example design of a StarLAN HUB unit.

c) STAR
231422-1

Figure 7-1. Network Topologies

7.1.1 StarLAN
StarLAN overcomes the handicaps of cost and standards. It is very economical to implement; both, due to
the low cost of the node and that of the cable. The cost

7-2

AP-236

In the bus topology, all the nodes are connected to the
same bus or the transmission medium. There are various protocols to determine who can transmit. In the
CSMA/CD (Carrier Sense Multiple Access with Collision Detect) protocol, any node can transmit if there is
silence on the bus for a given time. If two nodes transmit at the same time, they collide. They detect the collision, wait for a random period of time and try transmitting again. Ethernet is an example of a LAN with a bus
topology using the CSMA/CD protocol. No single
node is critical to the network. Each is a peer.

PC using DOS calls. Appendix A shows oscilloscope
traces of the signals at various points in the network.
Appendix B deals with doing DMA in environments
where only one DMA channel is available.

7.1.5 References
For additional information on the 82588, see the LAN
Components User's Manual or the 82588 Reference
Manual. For additional information on StarLAN, see a
draft ofIEEE 802.3 type !BASE5 specifications.

If nodes are connected together to form a ring, there is
generally a token which gets passed from node to node.
Whoever has the token can transmit and then pass the
token to the next node. Token ring network is an example of this topology. Although, Token bus network
physically has a bus topology, the nodes form a virtual
ring around which a token is passed. In a star topology,
as in Star LAN, the nodes are connected to a central
unit called the HUB. The HUB receives and retransmits the frames from each node. It is like a switching
station in a telephone network. Since the HUB sits at a
central place, it can perform functions which are shared
by all nodes. StarLAN also uses a CSMA/CD protocol
like the Ethernet. The HUB in the StarLAN network
primarily aids in resolving collision among the nodes.

7.1.6 Acknowledgements
Intel Corporation gratefully recognizes AT & T Information Systems for the Star LAN concept and their
contributions to the IEEE 802.3 IBASE5 Task Force.
Ideas and cooperation from Bob Galin, Ad; Golbert,
Ariel Hendel, Yosi Mazor and Kiyoshi Nishide have
been very helpful.

7.2 StarLAN
Star LAN is a low cost networking solution aimed at
the office automation, instrumentation and serial backplane applications. It is a 1 Mb/s, IEEE 802.3 compatible CSMA/CD network. It has a star topology with the
nodes connected in a point-to-point fashion to a central
HUB. HUBs can be connected in a hierarchical fashion. Up to 5 levels of HUBs are supported. The maximum distance between a node to the adjacent HUB or
between two adjacent HUBs is 800 ft. (250 meters) for
24 gauge wire and 600 ft. (200 meters) for 26 gauge
wire. Maximum node to node distance with one HUB is
0.5 km, hence IEEE 802.3 calls it a IBASE5 LAN. 1
stands for 1 Mb/s and BASE is for baseband.

7.1.3 The 82588
The 82588 is a single chip LAN controller designed for
CSMA/CD networks. It integrates in one chip all func-

tions needed for such networks. Besides doing the standard CSMA/CD functions like framing, deferring,
backing off on collisions, transmitting and receiving
frames, it performs encoding and decoding the data in
Manchester or NRZI format, carrier sensing and collision detection up to a speed of 2 Mb/s. These functions
make it an optimum controller for a StarLAN node. It
has a very conventional microcomputer bus interface,
further easing the job of interfacing it to any processor.

One of the attractive features of StarLAN is that it uses
telephone grade twisted pair wire for the transmission
medium. In fact, existing, installed telephone wiring
can also be used for StarLAN. Telephone wiring is
probably the cheapest wire. It is also very economical
to install. Although use of telephone wiring is an obvious advantage, for small clusters of nodes the entire
wiring can be done without using building wiring.

7.1.4 Organization of the Application
Note
Section 7.2 of this Application Note describes the
Star LAN network, its basic components, collision detection, signal propagation and network parameters.
Sections 7.3 and 7.4 describe the 82588 LAN controller
and its role in the StarLAN network. Section 7.5 goes
into the details of designing a StarLAN node for the
IBM Pc. Section 7.6 describes the design of the HUB.
Both these designs have been implemented and operated in an actual StarLAN environment. Section 7.7 documents the software used to drive the 82588. It gives
the actual procedures used to do operations like, configure, transmit and receive frames. It also shows how to
use the DMA controller and interrupt controller in the
IBM PC and goes into the details of doing I/O on the

Factors contributing to its low cost are:
a. Use of telephone grade, unshielded, 24 or 26 gauge
twisted pair wire transmission media.
b. Installed base of redundant telephone wiring in most
buildings. Even new installation of telephone wiring
is very economical.
c. Buildings are designed for star topology wiring. They
have conduits leading to a central location.

7-3

inter

AP-236

d. Availability of low cost VLSI LAN controllers like
the 82588.for low cost applications and the 82586 for
high performance applications.
e. Low cost RS-422 drivers/receivers needed for the
physical level interface.

shown in Figure 7-2, where nodes are shown as pes.
the HUB at the base (at level 3) of the tree is called the
Header Hub (HHUB) and others are called 1ntermediate HUBs (IHUB). It will become apparent, later in
this section, that topologically, this entire network of
nodes and .HUBs is. equivalent to one where all the
nodes are connected to a single HUB.

7.2.1 Star LAN Top~logy
7.2.1.1 TELEPHONE NETWORK

StarLAN has (as the mime suggests) a star topology.
The nodes are at the ends of the arms of it star and the
central point is called a HUB. There can be more than
one HUB in a network. The HUBs are connected in a
hierarchical fashion resembling an inverted tree, as

StarLAN is structured to run parallel to the telephone
network in a building. The telephone network has, in
fact, exactly the same star topology as StarLAN. Let us
now examine how the telephone system is laid out in it

HUB LEVEL 1

23t422-2
'Maximum of 5 HUB levels.
'pes or DTEs can connect directly at any level.

Figure 7-2. StarLAN Topology

WIRING CLOSET

~"

BUNDLES OF
- - - 25 - 50 PAIRS
~2 TWISTED PAIRS
24 GAUGE, UNSHIELDED

'---

231422-3

Figure 7-3. Telephone Wiring in a Building

7-4

inter

AP-236

building in the USA. Figure 7-3 shows how a typical
building is wired for telephones. 24 gauge unshielded
twisted pair wires emanate from a room called the Wiring Closet. The wires are in bundles of 25 or 50 pairs.
The bundle is called D inside wiring (DIW) cable. The
wires in these cables end up at modular telephone jacks
in the wall. The telephone set is either connected directly to the jack or through an extension cable. Each telephone generally needs one twisted pair for voice and
one more for auxiliary power. Thus, each modular jack
has 2 twisted pairs (4 wires) connected to it. A 25 pair
DIW cable can thus be used for up to 12 telephone
connections. In most buildings, all pairs in a cable are
not used up. Typically, a cable is used for only 4 to 8
telephone connections. This practice is followed by telephone companies because it is cheaper to install extra
wires once, than to install once again to expand the
existing number of connections. As a result, a lot of
extra, unused wiring exists in a building. The stretch of
cable between the wiring closet and the telephone jack
is typically less than 800 ft. (250 meters). In the wiring
closet the incoming wires from the telephones are routed to another wiring closet, a P ABX or to the central

office through an interconnect matrix. Thus, the wiring
closet is a concentration point in the telephone network. There is also a redundancy of wires between the
wiring closets.
7.2.1.2 StarLAN AND THE TELEPHONE
NETWORK

Does Star LAN need telephone wiring in the building?
Not really. StarLAN does not have to run on the building telephone wiring but the fact that it can, adds to its
attractiveness. Figure 7-4 shows how the Star LAN network fits right on top of the telephone network. Each
node needs 2 twisted pair wires to hook up to the HUB.
The unused wires in the 25 pair DIW cables provide an
electrical path up to the wiring closet, where the HUB
is located. Note that the telephone and the StarLAN
networks are electrically isolated. They only use the
wires in the same DIW cable to reach the wiring closet.
Within the wiring closet, the StarLAN wires go to a
HUB and the telephone wires are routed to a different
channel. Similar cable sharing can occur in going from
one HUB to another. See Figure 7-5 for a typical office
wired for StarLAN through the telephone wiring.

WIRING CLOSET

'\
BUNDLES OF _ _ _~I
- - - 25 - 50 PAIRS
~2 TWISTED PAIRS
24 GAUGE, UNSHIELDED

"'-•

231422-4
'StarLAN and telephones share the same cable, but are electrically isolated.
'StarLAN uses the unused wires in existing cables.

Figure 7-4. Coexistence of Telephone and Star LAN

7-5

AP-236

WIRING CLOSET

ROOM # 1

WIRING CLOSET

•

WIRING CLOSET

TELEPHONE
WIRES TO PBX

ROOM # 2

WIRING CLOSET

ROOM,# 3

231422-5

Figure 7-5. A Typical Office Having StarLAN through Telephone Wiring

7-6

AP-236

tance between any two nodes does not exceed 2.5 kilometers. In StarLAN the maximum distance between two nodes is also 2.5 kilometers. This is
achieved by wiring a maximum of five levels of HUBs
in a hierarchical fashion.

7.2.2 StarLAN and Ethernet
Both StarLAN and Ethernet are CSMA/CD networks
which conform to the IEEE 802.3 requirements. Since
Ethernet has been around longer and is better understood, a comparison of Ethernet with StarLAN can
ease the understanding of StarLAN.
a. Both Ethernet and StarLAN are IEEE 802.3 compatible CSMA/CD networks.
b. Data rate of Ethernet is IOMb/s and that of
StarLAN is I Mb/s.
c. Ethernet has a bus topology where each node is connected to a coaxial cable bus via a 50 meter transceiver cable contaiiIing four shielded twisted pair wires.
StarLAN has a star topology, where each node is
connected to a central HUB by a point to point link
through two pairs of unshielded twisted pair wires.
d. Collision detection in Ethernet is done by the transceiver in the coaxial cable. Electrically, it is done by
sensing the energy level on the coax cable. Collision
detection in StarLAN is done in the HUB by sensing
activity on all the input lines to the HUB.
e. In Ethernet, the presence of collision is conveyed by
the transceiver to the node by a special collision detect (CDT) signal. In StarLAN, it is conveyed by the
HUB using a special collision presence signal on the
receive data line to the node.
f. Ethernet cable segments are interconnected using repeaters in a non-hierarchical fashion so that the dis-

It is interesting to see that topologically, Ethernet looks
similar to a Star LAN, if the length of cable in Ethernet
were to shrink to zero and the length of the transceiver
cables were to grow to 800Tt. (250 meters), as shown in
Figure 7-6.

7.2.3 Basic Star LAN Components
A Star LAN network has three basic components:
a. StarLAN node interface
b. StarLAN HUB
c. Cable

7.2_3_1 A StarLAN NODE INTERFACE
Figure 7-7 shows a typical StarLAN node interface. It
interfaces to a processor on the system side. The processor runs the networking software. The heart of the
node interface is the LAN controller which does the job
of receiving and transmitting the frames in adherence
to the IEEE 802.3 standard protocol. It maintains all

ETHERNET

STAR LAN
231422-6
HUB3 is like a repeater
IF segment length L ~ 0 AND Transceiver Cable length T --+ 800 It.
THEN Ethernet '" StarLAN

Figure 7-6. Ethernet and StarLAN Similarities

7-7

AP-236

PULSE
TRANSFORMER

TELEPHONE
JACK

8 BIT BUS

<

>

82588

TxD

PULSE
~"---f SHAPING

CONTROL

< >

RxD

SYS ClK

SQUELCH

, +
ENABLE
CIRCUITS
231422-7

Figure 7-7. 82588 Based Star LAN Node

the timings-like the slot time, interframe spacing
etc.-required by the network. It performs the functions of framing, deferring, backing-off, collision detection which are necessary in a CSMA/CD network. It
also does Manchester encoding of data to be transmitted and clock separation- or decoding-of the Manchester encoded data that iSTeceived. The signals from
the controller are converted to the differential form by
a RS-422 or RS-485 driver. These signals cannot be
directly sent on the unshielded twisted pair wire because the rise and fall times of the signal are fast and
this causes the undesired effect of cross-talk and radiation. This disturbs other signals, digital and voice, sharing the same cable. Some pulse shaping is therefore
done essentially to increase the rise and fall times
(edges are made to rise and fall slower). The shaped
signal is sent on to the twisted pair wire through a pulse
transformer for DC isolation. The signals on the wire
are thus differential, DC isolated from the node and
almost sinusoidal (due to shaping and the capacitance
of the wire).

7.2.3.2 Star LAN HUB

HUB is the point ofcoricentration in StarLAN.All the
nodes transmit to the HUB and receive from the HUB.
Figure 7-8 shows an abstract representation of the
HUB. It has an upstream and a downstream signal
processing unit. The upstream unit has N signal inputs
and I signal output. And the downstream unit has I
input and N output signals. The inputs to the upstream
unit come from the nodes or from the intermediate
HUBs (IHUBs) and its output goes to a higher level
HUB. The downstream unit is connected the other way
around; input from a upper level HUB and the outputs
to nodes or lower level IHUBs. Physically each input
and output consists of. one twisted pair wire carrying a
differential signal. The downstream unit essentially just
re-times the signal received at the input, and sends it to
all its outputs. The functions performed by the upstream unit are:
a.
b.
c.
d.

The signal received by the node (from the HUB) is
filtered from noise by a squelch circuit. The squelch
circuit prevents idle line noise from affecting the receiver circuits in the LAN controller. The differential signal from the HUB is received using a zero-crossing RS422 receiver. Output of the receiver, qualified by the
squelch circuit, is fed to the RxD pin of the LAN controller. The RxD signal provides three kinds of information.
a. Normal received data, when receiving the frame.
b. Collision information in the form of the collision
presence signal from the HUB. This is used when
transmitting a frame.
c. Carrier sense information, indicating the beginning
and the end of frame. This is useful during transmit
and receive operations.

Collision detection
Collision Presence signal generation
Signal Retiming
Jabber Function

231422-8

Figure 7-8. A StarLAN HUB
7-8

inter

AP-236

IDLE
IDLE

COLLISION PRESENCE
IDLE
IDLE

HUB
VALID
MANCHESTER

IDLE

VALID MANCHESTER

IDLE

VALID MANCHESTER
IDLE
VALID MANCHESTER

COLLISION PRESENCE
IDLE
IDLE

COLLISION
PRESENCE

HUB
COLLISION
PRESENCE

HUB
COLLISION
PRESENCE

VALID MANCHESTER

IDLE

231422-9

Figure 7-9. HUB as a Black Box

TRANSMIT PAIR

#1

~II
~II
TRANSMIT PAIR

+

TO HIGHER
LEVEL HUB

JABBER

#N

RECEIVE PAIR # 1

+-)11

HHUB

I

o
SIGNAL
IHU-B----f . RETIMING

+-)11
RECEIVE PAIR # N

231422-10

Figure 7-10. StarLAN HUB Block Diagram

7-9

inter

AP-236

The collision detection in the HUB is done by sensing
the activity on the inputs. If there is activity (or transitions) OIl more than one input, it is assumed that more
than one node is transmitting. This is a collision. If a
collision is detected, a special signal called the Collision
Presence Signal is generated. This signal is generated
and sent out as long as activity is sensed on any of the
input lines. This signal is interpreted by every node as
an occurrence of collision. If'there is activity only on
one input, that signal is re-timed-or cleaned up of any
accumulated jitter-and sent out. Figure 7-9 shows the
input to output relations for .the upstream part of the
HUB as a black box.
.

Capacitance
Impedance

: 0.1 iJoF/mile
: 92.60., -4 degrees

@

1 MHz

Experiments have shown that the sharing of the telephone cable with other voice and data services does Ilot
cause any mutual harm due to cross-talk and radiation,
provided every service meets the FCC limits.
Although it is not a part of the IEEE 802.3 IBASE5
standard, there is considerable interest in using fiber
optics and coaxial cable for node to HUB or HUB to
HUB links especially in noisy and factory environ~
ments. Both these types of cables are particularly suited
for point-to-point connections. Even mixing of different
types of cables is possible.

If a node transmits for too long the HUB exercises a'
Jabber function to disable the node from interfering
with traffic from other nodes. There are three timers in
the HUB associated with this function and their operation is described in section 7.6.

7.2.4 Framing
Figure 7-11 shows the format of a StarLAN frame. The
beginning of the frame is marked by the carrier going
active and the end marked by carrier going inactive.
The preamble has a 56 bit sequence of 101010 ....
ending in a O. This is followed by 8 bits of start of frame
delimiter (sfd) - 10101011. These bits are transmitted
with the MSB (leftmost bit) transmitted first. Source
and destination fields are 6 bytes long. The first byte is
the least significant byte. These fields are transmitted
with LSB first. The length field is 2 bytes long and gives
the length of data in the Information field. The entire
information field isa minimum, of 46 bytes and a maximum of 1500 bytes. If the dataconte!ltofthe Information field is less than 46, padding bytes are used to
make the field 46 bytes long. The Length field indicates
how much real data is in the Infprmation field, The last
32 bits of the frame is the· Frame Check Sequence
(FCS) and contains the CRC for the frame. The CRC is
calculated from the beginning of. the destination address to the end of the Information field. The generat.
ing polynomial (Autodin II) used for CRC is:

Figure 7-10 shows a block diagram of the HUB. A
switch position determines whether the HUB is an
IHUB or a HHUB. If the HUB isan IHUB, the switch
decouples the upstream and the downstream units.
Header HUB (HHUB) is the highest level HUB; it has
no place to send its output signal, so it returns its output signal (through the switch) to the outputs of the
downstream unit. There is one and only one HHUB in
a StarLAN network and it is always at the base of the
tree. The returned signal eventually reaches every node
in the network through the intermediate nodes (if any).
StarLAN specifications do not put any restrictions on
the number of IHUBS at any level or on number of
inputs to any HUB. The number of inputs per HUB are
typically 10 to 20 and is dictated by the typical size of
clusters in a given networking environment.

7.2.3.3 StarLAN CABLE
Unshielded telephone grade twisted pair wires are used
to connect a node toa HUB or to connect two HUBs.
This is one of the cheapest types of wire and responsible
for bringing down the cost of StarLAN.

X32 + X26 + X23 + X22 +X16 + X12 + Xll +
Xl0 + X8 + X7 + X§ + X4 + X2 + X + 1

The frames can be directed to a specific node (LSB of
address must be 0), to a group of nodes (multicast or
group-LSB of address must be 1) o~ all nodes (broadcast-all address bits must be 1).

Although the 24 gauge wire is used for long stretches,
the actual connection between the node and the telephone jack in the wall is done using extension cable,
just like connecting a telephone to a jack. For very
short StarLAN:configurations, where all the nodes and
the HUB are in the same room, the extension cable
with plugs at both ends may itself be sufficient for all
the wiring.

7.2.5 Signal Propagation and Collision
Figure 7-12 will be used to illustrate three typical situations in a StarLAN with two IHUBs and one HHUB.
Nodes Aand B are conJ1ected to HUBI, nodes C and D
to HUB2 and node E to HUB3.

The telephone twisted pair wire of 24 gauge has the
following characteristics:
Attenuation
: 42.55 db/mile @ 1 MHz
DC Resistance : 823.69 o./mile
Inductance
: 0.84 mH/mile
7-10

AP-236

CARRIER ON

+I

CARRIER OFF
7

PREAMBLE

1

6

6

2

MAX= 1500
MIN = 46

SFO

DA

SA

LEN

INFORMATION

I I I I I

I
4 ..

I I
FCS

I ....
·---FRAME LENGTH-I
MAX = 1518
MIN = 64
Sfd
DA
SA
Len

231422-11

~

Start of Frame Delimiter
~ Destination Address
~ Source Address
~ Length
FCS~ Frame Check Sequence
All numbers indicate field length in octets.

Figure 7-11. Framing

These situations should also illustrate the point made
earlier in the chapter that, the StarLAN network, with
nodes connected to multiple HUBs is, in effect, equiva·
lent to all the nodes connected to a single HUB.

7.2.5.1 SITUATION #1

Whenever node A transmits a frame Fa, it will reach
HUB!. If node B is silent, there is no collision. HUBI
will send Fa to HUB3 after re-timing the signa!. If
nodes C, D and E are also silent, there is no collision at
HUB2 or HUB3. Since HUB3 is the HHUB, it sends
the frame Fa to HUBI, HUB2 and to node E after retiming. HUB I and HUB2 send the frame Fa to nodes
A, Band C, D. Thus, Fa reaches all the nodes on the
network including the originator node A. If the signal
received by node A is a valid Manchester signal and not
the Collision Presence Signal (CPS) for the entire durac
tion of the slot time, then the node A assumes that it
was a successful transmission.
7.2.5.2 SITUATION # 2

If both nodes A and B were to transmit, HUB 1 will
detect it as a collision and will send signal Fx (the Collision Presence Signal) to the HUB3-Note that HUBI
does not send Fx to nodes A and B yet. HUB 3 receives
a signal from HUBI but nothing from node E .or
HUB2, thus it does not detect the situation as a collision and simply re-times the signal Fx and sends it to
node E, HUB2 and HUB!. Fx ultimately reach all the
nodes. Nodes A and B detect this signal as CPS and
call it a collision.
7.2.5.3 SITUATION #3

In addition to nodes A and B, if node C were also to
transmit, the situation at HUBI will be the same as in
situation #2. HUB2 will propagate Fc from C towards
HUB3. HUB3 now sees two of its inputs active and
hence generates its own Fx signal and sends it towards
each node.

7.2.6 StarLAN Network Parameters
At the time of writing (June, 1985 revision of IEEE
802.3·lBASE5 specifications), all the StarLAN network parameters defined, match those of Ethernet.
Some important ones are:
Preamble length (inc!. sfd) .................. 64 bits
. Address length ............................ 6 bytes
FCS length CRC(Autodin II) ................ 32 bits
Maximum frame length ................. 1518 bytes
Minimum frame length .................... 64 bytes
Slot time ............................ 512 bit times
Interframe spacing ..................... 96 bit times
Minimum jam timing .................. 32 bit times
Maximum number of collisions .................. 16
Backoff limit ................................. 10
Backoffmethod ........ Truncated binary exponential
Encoding ...... : ..................... Manchester
Propagation delay between most
distant nodes ...................... 130 bit times
Maximum delay though IHUB .......... 10 bit times
Maximum delay per cable segment ........ 4 bit times
Bits eaten up in the HUB ................... .4 bits
Clock tolerance ......................... ± 0.01 %
Maximum jitter per segment ................ ± 90 ns

7-11

AP-236

'231422-12

Situation # 1. A Transmitting

231422-13

Situation #2. A & B Transmitting

231422-14

Situation # 3. A, B & C Transmitting
HUB1, HUB2 are IHUBs
HUB3 is the HHUB
Fa, Fb, Fe-Frames from nodes A, B & C
Fx-Collision Presence Signal

Figure 7-12. Signal Propagation and Collisions

7-12

intJ

AP-236

Space (IFS) timing, reacting to collision by generating a
jam pattern, calculating the back-off time based on the
number of collisions and a random number, decoding
the address of the incoming frame, discarding a frame
that is too short, etc. All these are performed by the
82588 in accordance to the IEEE 802.3 standards. For
inter-operability of different nodes on the Star LAN network it is very important to have the controllers strictly
adhere to the same standards.

7.3 LAN CONTROLLER FOR StarLAN
One of the attractive features of Star LAN is the availability of the 82588, a VLSI LAN controller, designed
to meet the needs of a Star LAN node. The main requirements of a Star LAN node controller are:
I. IEEE 802.3 compatible CSMA/CD controller.
2. Configurable to Star LAN network and system parameters.
3. Generation of all necessary clocks and timings.
4. Manchester data encoding and decoding.
5. Detection of the Collision Presence Signal.
6. Carrier Sensing.
7. Squelch or bad signal filtering.
8. Fast and easy interface to the processor.

7.3.2 Configurability of the 82588
Almost all the networking parameters are programmable over a wide range. This means that the StarLAN
parameters form a subset of the total potential of the
82588. This is a major advantage for networks whose
standards are being defined and are in a flux. It is also
an advantage in carrying over the experience gained
with the component in one network to other applications, with differing parameters.

82588 performs all these functions in silicon, providing
a minimal hardware interface between the system processor and the Star LAN physical link. It also reduces
the software needed to run the node, since a lot of functions, like deferring, back off, counting the number of
collisions etc., are done in silicon.

The 82588 is initialized or configured to its working
environment by the CONFIGURE command. After
the execution of this command, the 82588 knows its
system and network parameters. A configure block in
memory is loaded into the 82588 by DMA. This block
contains all the parameters to be programmed as shown
in Figure 7-13. Following is a partial list of the parame-

7.3.1 IEEE 802.3 Compatibility
The CSMA/CD control unit on the 82588 performs the
functions of deferring, maintaining the Interframe
4
BYTE

COU~T (L.S.B)

BYTE

COU~T (M.S. B)

I

CHAINING

SERIAL
MODE

SAMPLING
RATE

OSC
RANGE

FIFO LIMIT
I

~UFFER

LENGTH

I

I

EXT LOOP- INT LOOPBACK
BACK

PREA~ LEN

I

BACK OFF
METHOD

E~P

P~IO

I

I

INTER

I FRAME

I

NO SRC
ADD INS

ADD LEN

DIF.MAN
/MANCH.

LINEAR
PRIORITY

I

SPACING

I
S:LOT TIME

(~)

I
RETRY NUMBER

PAD
COT
SRC

BIT
STUFF

COBBC
NO CRC
INSERT

CRC16

SLOT TIME (H)
MANCH.
/NRZI

Tx ON
NO CRS

COT
FILTER
FRAME

I

PRM

CRS
FILTER

CRS
SRC

M:NIMUM

BC
DIS

LENGTH

I

I

Figure 7-13. Configuration Block
7-13

231422-15

inter

AP-236

ters with the programmable range and the Star LAN
value:
Parameter
Preamble length
Address length
CRC type
Minimum frame
length
Interframe Spacing
Slot time
Number of retries
Data encoding
Collision detection

Range
2, 4, 8, 16 bytes

o to 6 bytes
16,32 bit
6 to 255 bytes
12 to 255 bit times
1 to 2047 bi t times
o to 15
NRZI, Man.,
Diff. Man.
Code viol.,
Bit compo

7.3.4 Manchester Data Encoding and
Decoding
.

StarLAN
Value
8
6
32

In Star LAN the data transmitted by the node must be
encoded in Manchester format. Node ·should also be
able to decode Manchester encoded data when receiving a frame-a process also known as clock recovery.
The 82588 does the encoding and decoding of data bits
for data rates up to 2 Mb/s.

64
96
512
15
Manch.

Besides Manchester, the 82588 can also do encoding
and decoding in NRZI and Differential Manchester
formats. Figure 7-14 shows samples of encoding in
these three formats. The main advantage of NRZI 9ver
the other two is that NRZI requires half the channel
bandwidth, for any given data rate. On the other hand,
since the NRZI signal does not haye as many transitions as the other two, clock recovery from it is more
difficult. The main advantage of Differentiai Manchester over straight Manchester is that for a signal that is
differentially driven (as in RS 422), crossing of the two
wires carrying the data does not change· the data received at the receiver. In other words, NRZI and Differential Manchester encoding methods are polarity insensitive.

Code Viol.

Beside these, thc:re are many other options available,
which mayor may not apply to StarLAN:
Data sampling rate of 8 or 16
Operating in Promiscuous mode
Reception of Broadcast frames
Internal loopback operation
Externalloopback operation
Transmit without CRC
HDLC Framing

7.3.5 Detection of the Collision
Presence Signal
In a StarLAN network, HUB informs the nodes that a
collision has occurred by sending the Collision Presence Signal (CPS) to the nodes. The CPS signal is a:
special signal which contains violations in Manchester
encoding. Figure 7-15 shows the CPS signal. It has a 5
microsec. period, looking very much like a valid Manchester signal except for missing transitions (or violations) at periodic intervals. When the 82588 decodes
this signal, it fails to see mid-cell transitions repeatedly
at intervals of 2.5 bit times and hence calls it a code
violation. The edges of CPS are marked for illustration
as a, b, c, d, ... I. Let us see how the 82588 interprets
the signal if it starts calling the edge 'a' as the mid-cell
transition for 'I'. Then edge at 'b' is '0'; Now the 82588
expects to see an edge at ,., but since there is none, it is
a Manchester code violation. The edge that eventually
does occur at 'd' is then used to· re-synchronize and,
since it is a falling edge, it is taken as a mid-cell transition for '0'. The edge at 'e' is for a ')' and then again
there.is no edge at "'. This goes on, with the 82588
flagging code violation and re-synchronizing again every 2.5 bit times as shown in Figure 7-15. When a
transmitting node sees this CPS signal being returned
by the HUB (instead of a valid Manchester signal it
transmitted), it assumes that a collision occurred. The
82588 has two built-in mechanisms to detect collisions.
These mechanisms are very general and can be used for
a very broad class of applications to detect collisions in

7.3.3 Clocks and Timers
The 82588 requires two clocks; one for the operation of
the system interface and another for the serial side.
Both clocks are totally asynchronous to each other.
This permits transmitting and receiving frames at data
rates that are virtually independent of the. speed at
which system interface operates.
The serial clock can be generated on chip using just an
external crystal of a value 8 or 16 times the desired bit
rate. An external clock may also be used.
The 82588 has a set of timers to maintain various timingsnecessary to run the CSMA/CD control unit.
These are timings for the Slot time, Interframe spacing
time, Back off time, Number of collisions, Minimum
frame length, etc. These timers are started and stopped
automatically by the 82588.

7-14

AP-236

DATA

1 1 1 0 1 1 1 1 1 0 1 1 1 0 1 01 0 1 1 1

BINARY
NRZI
MANCHESTER
DIFFERENTIAL
MANCHESTER

Encoding
Method

231422-16

Mid BilCell
Transitions

Bit Cell Boundary
Transitions

Binary

Do not exist.

Identical to original data.

NRZI

Do not exist.

Exist only if original data
bit equals O.
Dependent on present
encoded signal level:
to 0 if 1
to 1 if 0

Manchester

Exist for every bit of
the original data:
from 0 to 1 for 1
from 1 to 0 for 0

Exist for consequent equal
bits of original data:
from 1 to 0 for 1 1
from 0 to 1 for 0 0

Differential
Manchester

Exist for every bit of
the original data.
Dependent on present
Encoded signal level:
to 0 if 1
to 1 if 0

Exist only if original data
bit equals O.
Dependent on present
Encoded signal level:
to 0 if 1
to 1 if 0

Figure 7-14. 82588 Data Encoding Rules

7-15

inter

AP-236

ENCODING
CPS

abc

EDGES:

d

e f

9

h I

k I

i-5JLS PERIOD-I

I 2t I t I . t = 0.5 JLs
• MISSING MID-CELL TRANSITION

82588
DECODING

10·

.II.IL
abc

d

o

1

1...JL.I
d

e f

9
10

•

.IL1L
kim

o

1

1...JL.I
kim

Figure 7~15.82588 Decoding the Collision Presence Signal

7-16

231422-17

intJ

AP-236

a CSMA/CD network. Using these mechanisms, the
82588 can detect collisions (two or more nodes transmitting simultaneously) by just receiving the collided
signal during transmission, even if there were no HUB
generating the CPS signal.

Collision also if:
RxD stays low for 13 samples or more
A mid cell.transition is missing
Sampling rate = 16 (clock is 16x bit rate)
CCCCCSSSSSCLLLLLLLLLCCCC

7.3.5.1 COLLISION DETECTION BY CODE

IIIIIIIIIIIIIIIIIIIIIIIIIII

VIOLATION

o

If during transmission, the 82588 sees a violation in the
encoding (Manchester, NRZI or Differential Manchester) used, then it calls it a collision by aborting the
transmission and transmitting a 32 bit jam pattern. The
algorithm used to detect collision, and even to do the
data decoding, is based on finding the nu'mber of sampling clocks between an edge to the next edge. Suppose
an edge occurred at time 0, the sampling instant of the
next edge determines whether it was a collision (C), a
long pulse (L)-with a nominal width of 1 bit time-or
a short pulse (S)-nominal width of half a bit time. The
following two charts show the decoding and collision
detection algorithm for sampling rates of 8 and 16
when using Manchester encoding. The numbers at the
bottom of the line indicate sampling instances after the
occurrence of the last edge (at 0). The alphabets on the
top show what would be inferred by the 82588 if the
next edge were to be there.

C

S

S

S

L

L

L

L

L

C

2

3

4

5

6

7

8

10 12 14 16 18 20 22 24 26

A single instance of code violation can qualify as collision. The 82588 has a parameter called collision detect
filter (CDT Filter) that can be configured from 0 to 7.
This parameter determines for how many bit times the
violation must remain active to be flagged as a collision.
For Star LAN CDT Filter must be configured to 0that is disabled.

7.3.5.2 COLLISION DETECTION BY SIGNATURE
(OR BIT) COMPARISON

This method of collision detection compares a signature
of the transmitted data with that of the data received on
the RxD pin while transmitting. Figure 7-16 shows a
block diagram of the logic. As the frame is transmitted
it flows through the CRC generation logic. A timer,
called the Tx slot timer, is started at the same time that

C

--+

8

A mid cell transition is missing

9 10 11 12 13

TRANSMITTED
FRAME

6

RxD stays low for 13 samples or more

I I I I I I I I I I I I
o

4

Collision also if:

Sampling rate = 8 (clock is 8x bit rate)
C

2

TX CRC

TR ANSMIT CHANNEL

+
Tx SLOT
TIMER

TX SIGNATURE
LATCH

+
Rx SLOT
TIMER

COMPARE'

RX SIGNATURE
LATCH

t
RECEIVED
FRAME

RX CRC

+ - - R E CEIVE CHANNEL
, MATCH ~ NO COLLISION
NO MATCH ~ COLLISION

Figure 7-16. Collision Detection by Signature Comparison

7-17

231422-18

AP-236

the CRC generation starts. When the count in the timer
reaches the slot time value, the current value of the
CRC generator is latched in as the transmit signature.
As the frame is returned back (through the HUB) it
flows through the eRC checker. Another timer-Rx
slot timer-is started at the same time as the CRC
checker starts checking. When this timer reaches the
slot time value, the current value of the CRC checker is
latched in as the receive signature. If what is received is
same as what was transmitted during the collision window, then it is assumed that there was no collision.
Whereas, if the signatures do not match, a collision is
assumed to have occurred.

RxD remains in idle (high) state for 1.6 bit times. This
carrier sense information is used to mark the start of
the interframe space time and the back off time. The
82588 also defers transmission when the carrier sense is
active.
When operating in the NRZI encoded mode, carrier
sense is turned off if RxD pin is in the idle state for 8 bit
times (instead of 1.6) or more.

7.3.7 Squelching the Input
Squelch circuits are used to filter out bad signal on the
receive data input. Two types of filtering are necessary.
One in the voltage domain-called the voltage squelch,
another in the time domain-called the time squelch.
Squelch improves the reliability of the node and also
the stability of the network.

Note that, even if the collision were to occur in the first
few bits of the frame, a slot time must elapse before it is
detected. In the code violation method, collision is detected within a few bit times. However, since the signature method con:pares the signatures, which are characteristic of the frame being transmitted, it is more robust. The code violation method can be fooled by returning a signal to the 82588 which is not the same as
the transmitted signal but is a valid Manchester signal-like a 1 MHz signal. Both methods can be used
simultaneously giving a combination of speed and robustness.

Voltage quelch is done to filter out signal whose
strength is below a defined threshold (0.6 volts for
StarLAN). It prevents idle line noise from disturbing
the 'receive circuits on the controller. The voltage
squelch circuit is placed right after the receiving pulse
transformer. It enables the input to the RxD pin to the
82588 only when the signal strength is above the
threshold.

7.3.5.3 ADDITIONAL COLLISION DETECTION
MECHANISM

If the signal received has· the proper level but not the
proper timing, it should not bother the receiver. This is
accomplished by the time squelch circuit on the 82588.
Time squelching is essential to weed out spikes, glitches
and bad signal especially at the beginning of a frame.
The 82588 does not turn on its carrier sense (or receive
enable) signal until it receives three consecutive edges,
each separated by time periods greater than '18th bit
times at x16 sampling (and 1/4 bit times at x8 sampling)
but less than 1.6 bit times as shown in Figure 7-17. See
how spikes are filtered out.

In addition to the collision detection mechanisms described in the preceding sections, the 82588 also flags
collision when after starting transmission any of these
conditions become valid:
a. Half a slot time elapse and the carrier sense of 82588
is not active.
b. Half a slot time + 16 bit times elapse and the open,
ing flag (sfd) is not detected.
c. Carrier sense goes inactive after an opening flag is
received with transmitter still active.

The carrier sense activation can be programmed for a
further delay by up to 7 bit times by a configuration
parameter called carrier sense filter. See Figure 7-17.

These add a further robustness to the collision detection mechanism of the 82588. It is also possible to OR
an externally generated collision detect signal to the
internally generated condition.

7.3.8 System Bus Interface
The 82588 has a conventional bus interface making it
very easy to interface it to any processor bus. Figure
7-18 shows that it has an 8 bit data bus, read, write,
chip select, interrupt and reset pins going to the processor bus. It also needs an external DMA controller for
data transfer. A system clock of up to 8 MHz is also
needed. The read and write access times of the 82588
are very short-95 ns-as shown by Figure 7-19. This
further facilitates interfacing the controller to almost
any processor.

7.3.6 Carrier Sensing
StarLAN network is considered to be busy if there are
transitions on the cable. Carrier is supposed to be active
if there are transitions. Every node controller needs to
know when the carrier is active and when not. This is
done by the carrier sensing circuitry. On the 82588 this
circuit is on chip. It looks at the RxD (receive data) pin
and if there are transitions, it turns on an internal carrier sense signal. It turns off the carrier sense signal if

7-18

inter

AP-236

RECEIVED
SIGNAL

....

-.::;;,.'nr:.........

~

CARRIER SENSE
WITHOUT FILTER _ _ _ _ _-'-_ _ _ _---1
CARRIER SENSE
WITH FILTER 4 _ _ _ _ _ _ _ _ _ _ _ _ _--JI

=

1-4-1
BIT TIMES

-11.61BIT TIMES
231422-19

Figure 7-17. Carrier Sensing and Squelch

SERIAL CLOCK
Xl/TxC

X2/RxC

RESET - - - +
STANDARD
BUS
INTERFACE

00-7

RTS

<=>

+ - - CTS
Tx 0

ill
WR

SERIAL
INTERFACE

82588

cs

28 PIN
PLASTIC/CERAMIC

INT

+--RxO
TCLK

(MODE 0)

ORQO
DMA [ OACKO---+
INTERFACE ORQl

CRS} CSMA/CD
INTERFACE
COT

OACKl - - - +

ClK

t
SYSTEM CLOCK

Figure 7-18. Chip Interface

7-19

231422-20

inter

AP-235

.

80ns
(MIN)

.

95ns
(MIN)

I

55ns(MAX)

DATA

I--- 75 ns ---'----"
(MIN)

.

..

,

95ns
(MIN)

I
-ons,~
(MIN)

DATA
231422-21

Figure 7-1.9. Access Times

CONFIGURATION
IA
MULTICAST

READ

WRITE

Tx CRC
Rx CRC

IMPLICIT REGISTERS
(OVER 50 BYTES)
231422-22

Figure 7-20. Register Access

7-20

AP-236

4 Status registers are accessed through one read port
POINTER

L

CD

STATUS 0

t-------I
STATUS 1
STATUS 2

~

I READ PORT

STATUS 3
231422-23

The pointer can be changed using a command or can be automatically incremented.

READ_STATUS_588: PROCEDURE;

/* COMMAND 15 */

OUTPUT (CS_588) = 15;

/* RELEASE POINTER, INITIAL = 00 */

STATUS_588(0)=INPUT (CS_588)

/* REFRESH STATUS REGISTER IMAGE */

STATUS_588(1)=INPUT (CS_588)

/* IN MEMORY.

STATUS_588(2)=INPUT (CS_588)
STATUS_588(3)=INPUT (CS_588)
RETURN
READING 4 STATUS REGISTERS
Figure 7-21. Reading the Status Register

. The 82588 has over 50 bytes of registers, and most are
accessed only indirectly. Figure 7-20 shows the register
access mechanism of the 82588. It has one I/O port and
2 DMA channel ports. These are the windows into the
82588 for the CPU and the DMA controller. An external CPU can write into the Command register and read
from the Status registers using I/O instructions and
asserting chip select and write or read lines. Although
there is just one I/O port and 4 status registers, they
can be read out in a round robin fashion through the
same port as shown in Figure 7-21. Other registers like
the Configuration, Individual Address registers can be
accessed only through DMA. All the internal registers
can be dumped into memory by DMA using the Dump
command. The execution of some of the commands is
described in section 7.4. See the 82588 Reference Manual for details on these commands.

all the internal registers of the 82588 can be dumped
into the memory. The TDR command does Time Domain Reflectometry on the network. The 82588 has two
loopback modes of operation. In the internal loop back
mode the 82588 can receive its own transmitted frame.
This is very useful to test the transmit and receive units
of the chip and also the system interface. The external
loopback can be used to test even the external link at
the full data rate.

,7.3.10 Jitter Performance
When the 82588 receives a frame from the HUB, the
signal has a jitter. The jitter is the shifting of the edges
of the signal from the nominal position due to the
transmission over a length of cable. Many factors like,
intersymbol (resulting due to specific sequence of D's
and 1's) interference, rise and fall times of drivers and
receivers, cross talk, etc., contribute to the jitter. StarLAN specifies a maximum jitter of ± 90 ns whenever
the signal goes from a node/HUB to HUB/node. Figure 7-22 shows that the jitter tolerance of the 82588 is
120 ns for Manchester encoded data at I Mb/s giving
an ample safety margin.

7.3.9 Debug and Diagnostic Aids
Besides the standard functions that can be used directly
for Star LAN, the 82588 offers many debug and diagnostics functions. The DIAGNOSE command of the
82588 does a self-test of most of the counters and timers
in the 82588 serial unit. Using the DUMP command,

7-21

inter
Jitter

=

AP-236

± variation in pulse width

-------!...---,---

Nominal Pulse width

----.J

At the conclusion of transmission the 82588 generates
an interrupt to the CPU. The CPU can read the status
registers to find out if the transmission was successful.
If a collision occurs during transmission, the 82588
aborts transmission and generates the jam sequence, as
required by IEEE 802.3, and informs the CPU by interrupt and the status register. It also starts the back-off
timer.

dW
W

~:::;+=-:-;a;._-,;.-...
l __

I-w-I
231422-24

To re-attempt transmission, the CPU must reinitialize
the DMA controller to the start of the transmit data
block and issue a RETRANSMIT command to the
82588. When the 82588 receives the retransmit com·
mand and the· back-off timer has expired, it transmits
again. Interrupt and the status register contents again
indicate the success or failure of the (re)transmit attempt.

Manchester Encoded Data:
±25% .... , ...................... (23%)
± 125 ns for a 500 ns pulse ......... (120 ns)
± 250 ns for a 1000 ns pulse ........ (240 ns)
NRZI Encoded Data:
±4.2% ........................... (4%)
± 250 ns for a 6000 ns pulse ........ (240 ns)
±25% ........................... (23%)
± 250 ns for a 1000 ns pulse ....... ,(240 ns)

The main difference between transmit and retransmit
command is that retransmit command does not clear
the internal count for the number of collision occurred,
whereas transmit command does. Moreoever, retransmit takes effect only when the back-off timer has expired.

*"'Numbers in parenthesis are practical values.

Figure 7-22. 82588 Jitter Tolerance

7.4 THE 82588
This chapter describes the basic 82588 operations.
Please refer to the 82588 Reference Manual. or the
LAN Components User's Manual for a detailed description. Basic operations like transmitting a frame,
receiving a frame, configuring the 82588 and dumping'
the register contents are discussed here to give a feel for
how the 82588 works.

J. Prepare Transmit Data-Block in Memory
2. Program DMA Controller
3. Issue Transmit Command on the Desired
Channel
BYTE
COUNT
DESTIN.
ADDRESS

7.4.1 Transmit and Retransmit
Operations

INFORMATION

To tr:ansmit a frame, the CPU prepares a block in the
memory called the transmit data block. As shown in
Figure 7-23, this block starts with a byte count field,
indicating how long the rest of the block is. The desti·
nation address field contains the node address of the
destination. Rest of the block contains the information
or the data field of the frame. The CPU also programs
the DMA controller with the start address of the transmit data block. The DMA byte count must be equal to
or greater than the block length. The 82588 is then
issued a TRANSMIT command-an OUT instruction
to the command. port of the 82588. The 82588 starts
generating DMA requests to read i!l the transmit data
block by DMA. It also determines whether and how
long it must defer on the link and when it can, it starts
transmitting with the preamble. The 82588 constructs
the frame on the fly. It takes the destination address
from the memory, source address as its own individual
address (previously programmed), data field from the
memory and the CRC, generated on chip, at the end of
the frame.

U
231422-25

Transmit Data Block

4. Interrupt is received on completion ,of command or if the command was aborted or
there was a collision. The status bytes 1 and
2 indicate the result of the operation.
s
TX
OEF
COll

HRT MAX
BEAT COll
TX

OK

STATUS 1

NUt.!. OF COLLISIONS
I lOST I lOST IUNDER
CRS CTS RUN STATUS 2

231422-26

Transmit & Retransmit Results Format
Figure 7-23. Transmit Operation

7-22

inter

AP-236

RECEIVED FRAME

1. Prepare a Buffer. for Reception
2. Program DMA Controller
3. Issue Receiver Enable Command
When a frame is received, it is deposited in the
memory. Receive status by.tes (2) are appended to
the frame in the memory, byte count written in the
status registers I, 2, and an interrupt is generated.
RECEIVE
STATUS

SRT
FRM

DESTIN.
ADDRESS

SOURCE
ADDRESS

NO
EOF
RCV
O.K.

CRC
ERR

~~\:'~

ALG
ERR

STATUS REG. 1!
STATUS REG. 2

~

INFORMATION

RECEIVE
STATUS

BYTE
COUNT

231422-27

Figure 7-24. Receive Operation (Single Buffer)

If the received frame has errors, the CPU must recover
(or re-use) the buffer. Note that the entire frame is deposited into one buffer.

7.4.2 Configuring the 82588
To initialize the 82588 and program its network and
system parameters, a configure operation is performed.
It is very similar to the transmit operation. Instead of a
transmit data block as in transmit command, a configure data block-shown in Figure 7-13-is prepared by
the CPU in the memory. The first 'two bytes of the
block specify the length of rest of the block, which specify the network and system parameters for the 82588.
The DMA controller is then programmed by the CPU
to the beginning of this block and a CONFIGURE
command is issued to the 82588. The 82588 reads in the
parameters by DMA and loads the parameters in the
on-chip registers.

7.4.3.1 MULTIPLE BUFFER FRAME RECEPTION

It is also possible to receive a frame into a number of
fixed size buffers. This is particularly economical if the
received frames vary widely in size. If the single buffer
scheme were used as described above, the buffer required would have to be bigger than the longest expected frame and would be very wasteful for very short
(typically acknowledge or control) frames. The multiple buffer reception is illustrated in Figure 7-25. It uses
two DMA channels for reception.

Similarly, for programming the INDIVIDUAL ADDRESS and MULTICAST ADDRESSes, the DMA
controller is used to load the 82588 registers.
@BUffER 1
@BUffER 2

7.4.3 Frame Reception

@BUffER 3

·
·

Before enabling the 82588 for reception the CPU must
make a buffer available for the frame to be received.
The CPU must program the DMA controller with the
starting address of the buffer and then issue the ENABLE RECEIVER command to the 82588. When a
frame arrives at the RxD pin. of the 82588, it starts
receiving the frame. Only if the address in the destination address matches either the Individual address,
Multicast address or if it is a broadcast address, is the
frame deposited into memory by the 82588 using
DMA. The format of storage in the memory is shown
in Figure 7-24. At the end, a two byte field is attached
which shows the status of the received frame. If CRC,
alignment or overrun errors are encountered, they are
reported. An interrupt from 82588 occurs when all the
bytes have been transferred to the memory. This informs the CPU that a new frame has been received.

··

@BUffER N

D=
.

. . . .0
"{
~Q""'~'
0

RECEIVED fRAME

Buffer
Poinler
Table
(Managed by CPU)

"""~,

BUffER N

231422-28

Figure 7-25. Multiple Buffer Reception
7-23

AP-236

As in single buffer reception, the one channel, say channel 0, of the DMA controller is programmed to the
start of buffer 1, and the 82588 is enabled for reception
with the chaining bit set. As soon as the first byte is
read out of the 82588 by the DMA controller and written into the first location of buffer 1, the 82588 generates an interrupt, saying that it is filling up its last available buffer and one more buffer must be allocated. The
filling up of the buffer 1 continues. The CPU responds
to the interrupt by programming the other DMA channel-channel I-with the start address of the second
buffer and issuing an ASSIGN ALTERNATE buffer
command with an INTACK (interrupt acknowledge).
This informs the 82588 that one more buffer is available on the other channel. When buffer 1 is filled up
(the 82588 knows the size of buffers from the configuration command), the 82588 starts generating the DMA
requests on the other channel. This automatically starts
filling up buffer 2. As soon as the first byte is written
into buffer 2, the 82588 interrupts the CPU again asking for one more buffer. the CPU programs the channel
o of the DMA controller with the start address of buffer 3, issues an ASSIGN ALTERNATE buffer command with INTACK. This keeps the buffer 3 ready for
the 82588. This switching of channels continues until
the entire frame is received generating an end of frame
interrupt. The CPU maintains the list of pointers to the
buffers used.

For 128 byte buffers it is 128 X 8 = 1024 microseconds or approximately 1 millisec. You get 1 ms to assign a new buffer after getting the interrupt for it.
Hence the process of multiple buffer reception' is not
time critical for the system performance.
This method of reception is particularly useful to guarantee the reception of back-to~back frames separated by
IFS time. This is because a new buffer is always available for the new frame after the current frame is received.
Although both the DMA channels get used up in receiving, only one channel is kept ready for reception
and the other one can be used for other commands until
the reception starts. If an execution command like
transmit or dump command is being executed on a
channel which must be allocated for reception, the
command gets aborted when the ASSIGN ALTERNATE BUFFER command is issued to the channel
used for the execution command. The interrupt for
command aborted occurs after the end of frame interrupt.

7.4.4 Memory Dump of Registers
All the 82588 internal registers can be dumped in the
memory by the DUMP command. A DMA channel is
used to transfer the register contents to the memory. It
is very similar to reception of a frame; instead of data
from the serial link, the data from the registers gets
written into the memory. This provides a software debugging and diagnostic tool.

Since a new buffer is allocated at the time of filling up
of the last buffer. The 82588 automatically switches to
the new buffer to receive the next frame as soon as the
last frame is completely received. It can start receiving
the new frame almost immediately even before the end
offrame interrupt is serviced and acknowledged by the
CPU. If a new frame comes in, and the previous frame
interrupt is not yet 'acknowledged, the interrupt line
goes active again for the buffererd one.

7.4.5 Other Operations
Other 82588 operations like DIAGNOSE, TDR,
ABORT, etc. do not require any parameter or data
transfer. They are executed by writing a command to
the 82588 command register and knowing the results (if
any) through the status registers.

Ifby the time a buffer fills up no new buffer is available,
the 82588 keeps on receiving. An overrun will occur
and will be reported in the received frame status. However, ample time is available for the allocation of a new
buffer. It is roughly equal to the time to fill up a buffer.

PULSE
TRANSFORMER

TELEPHONE
JACK

8 BIT BUS
82588

SYSTEM
BUS

~
SYS ClK
SQUELCH

+
ENABLE
CIRCUITS

231422-29

Figure 7-26. 82588 Based StarLAN Node

7-24

L __

l

5

Ill! S I GHAL CORRECTI OH
16LE:

PAL 16L8 EQUATIOHS ( ABEL FORMAT )
DACK0011< =
DACt:01_ :::
'"

UR_

'" "'1<'1.

CSIli
I;.

+5U

DIR

c~

13

£1-;' C~-IlA:1<1
E I IS C) -DAl..:K3

(
l

~iRll1i

{OPIIi t;.
IORlIi t.

IQU_
IOU_

)

4t
..

T

DACt'l_

+5U

I'HCI~3!01

tQWlIo:

= ! \ !AEU flo !A"3 ;!.., !A4 &. 1015 (, ! ... e.
! A7 ~~ Ae ;).. A8) • (lOR_ t.. 10W_-'
'" lOR:.. '" C[lAC~,ll.: .:. DACV3* t- cs_:o;

LEGEND

"" =

~tII'

OR,

!

•••

SQUELCH

0 2>, 1-'

~

'"""-f'

'

ae0.n.,.

:ItIVERT

cC°

...

.1:

ID

"';"I
N

:""I

sa
III

-...J

N
(11

~
Z
Z

o

c: +RESET

E:<:

Ui;.

BIE..~U6

c-:~~

101
... 2

10$
A7
AS
AS
104
A8

<05

10'

+I'4

c":- +DS

HE.
107
... F.:

c:::;:

+D2
+Ill

c-:- +IIO

H3
>l

6~

10'
Al

BE:

..

U9

>'<22

ID

;,25

n°
UI

T;_:D/:':\.1

0 I

I,S
Dol

R:C

E21712Dl
11 18 13 DO

~;~Llt tVC
ItH

'iSJ:<:q!:5
eLf:,

!

~~'~~~;

,

~.

~

c<~~

:;!B:~~
C>"";:'A'§"

1
"2

+5l.J:e.

8MHz

... 27 c-~
A28 C~+;:j'£N
All ......-..

•

74LSl:..1A
D

I

N

OD

(0)

ENT

c:L'R

en
EtlP

~I-'7_ _ _ _----'

'UtI]

u,

»
"U

Di

10

Ae

I

RECEI VE EHABLE

~~

-;-

"9

3 A7
4 A6
S AS

A2e. C::'+";:N

3

_3_

16L8

en

3

D7
Db

DS
D4

IBM PC

C.

!.

11
'"
12
7
BE. 13
8
1;5 14 :3
$4 15 10
S3 16 i 1

I/O CHAHHEL

ID

g.

.,(1..

PE64352

DF..tJ

E18C::~

,~

2.:

1::14C~---;

/

:1.5
26LS3::

I:13C"~

"TI

"'"c:

n.~/

vV·

."'.

tlOTES

-26LS32
PINS 16.4 ",l)C'::
PHIS 8,12 :GtII'

I,IF.:
-

26LS30

-

PIllS
PHONE-JACK

Pltll

104

l~~~N

+DRQl

'"

+!:;t)

4,S.8 '" Gla,
tItOTTon UIHJ·'

DR')0

ADDRESS DECODE CHI P SELECT
+5l)
<5U

~~.

E:

~ -::-:':~~,14
,

+DRQ3
IIRQ1

l'.o.F

DI---

16MH;!:

CLOCK GEHIlRA'lUR

231422-38

inter

AP-236

of interrupt, 3 channels of DMA control lines and other
control lines to do I/O and memory read/write operations. Figure 7-28 shows the signals and the pin assignment for the I/O Channel.

7.5 StarLAN NODE FOR IBM PC
This chapter deals with the hardware-the StarLAN
board-to interface the IBM PC to a StarLAN Network. This is a slave board which takes up one slot on
the I/O channel of the IBM PC. Figure 7-26 shows an
abstract block diagram of the board. It requires the
IBM PC resources of the CPU, memory, DMA and
interrupt controller on the system board to run it. Such
a board has two interfaces. The IBM PC I/O Channel
on the system or the parallel side and the telephone
grade twisted pair wire on the serial side. Figure 7-27
shows the circuit diagram of the board.

7.5.1.1 CHIP SELECT AND DATA BUS
INTERFACING

The 82588 on our board has to be accessible to the
CPU on the system board. The CPU access the 82588
by I/O instructions. On the StarLAN board, chip select
must be generated to select the 82588 when it is addressed. Figure 7-29 shows the I/O address map for the
Hex Range

7.5.1 Interfacing to the IBM PC I/O
Channel

OOO-OOF
020-021
040-043
060-063
080-083
OAX'
OCX
OEX
200-20F
210-217
220-24F
278-27F
2FO-2F7
2F8-2FF

IBM PC has 8 slots on the system board to allow expansion of,the basic system. All of them are electrically
identical and the I/O channel is the bus that links them
all to the 8088 system bus. The I/O channel contains
an 8 bit bidirectional data bus, 20 address lines, 6 levels
Rear Panel
SIGNAL NAME

GND

..-

81

Al

SIGNAL NAME

,....

1/0 CH CK

+RESET DRV

+D7

+sv

+DS

+IRQ2

+DS

-5VDC

+D4

+DRQ2

+D3

-12V

+D2

-CARD SLCTD

+Dl

+12V

+DO

GND

810 A10

+1/0 CH RDY

-MEMW

+AEN

-MEMR

+A19

-lOW

+A18

-lOR

+A17

-DACK3

+A16

+ORQ3

+A15

-DACKl

+A14

+DRQl

+A13

-DACKO

3AO-3A9
3BO-3BF
3CO-3CF
3DO-3DF
3EO-3E7
3FO-3F7
3F8-3FF

+A12

CLOCK

+Al1

82D A2D

+IRQ6

+Al0

+IRQ7

+A9

+IRQ5

+AS

+IRQ4

+A7

+IRQ3

+AS

-DACK2

+AS

+T/C

+A4

+ALE

+A3

+SV

+A2

+DSC

+Al

GND

300-31 F
320-32F
378-37F
380-38C*'
380-389**

'-"-

\.

831 A31

* At power-on time, the Non Mask Interrupt into the

*.

+AO

'-"-

\

Usage
DMA Chip 8237 A-5
Interrupt 8259A
Timer 8253-5
PP18255A-5
DMA Page Registers
NMI Mask Register
Reserved
Reserved
Game Control
Expansion Unit
Reserved
Reserved
Reserved
Asynchronous Communications
(Secondary)
Prototype Card
Fixed Disk
Printer
SDLC Communications
Binary Synchronous Communication~
(Secondary)
Binary Synchronous Communications
(Primary)
IBM Monochrome Display/Printer
Reserved
Color/Graphics
Reserved
Diskette
Asynchronous Communications
(Primary)

COMP ONENT SIDE

8088 is masked off.
This mask bit can be set and reset through
system software as follows:
Set mask: Write hex 80 to I/O Address hex AO
(enable NMI)
Clear mask: Write hex 00 to I/O Address hex AO
(disable NMI)
SDLC Communications and Secondary Binary
Synchronous Communications cannot be used
together because their hex addresses overlap.

231422-31

Figure 7-29. I/O Address Map
Figure 7-28. I/O Channel Diagram
7-26

inter

AP-236

IBM pc. Address of 300H was chosen for the
StarLAN board. A PAL (16L8) is used to do the control signal interfacing between the 82588 and the I/O
Channel. Signals A3 to A9 and AEN are used to generate the chip select for the 82588:
CS'

~

!(!AEN & !A3 & !A4 & !AS & !A6 & !A7 & AS & A9)
# (lOR' & lOW');

The system clock has to be supplied externally. It can
be up to 8 MHz. This clock runs the parallel side of the
82588. Its frequency does not have any impact on the
read and write access times but on the rate at which
data can be transferred to and from the serial side of
the 82588. For the A-2 stepping, this clock must be a
MOS level signal. For the B-stepping, a TTL level signal (0.8V -2.0V) will suffice.

NOTE:
ABEL PAL programming language is used for PAL
equations in this and the next section. An asterisk (*)
following a signal name indicates that it is active low.
Following operators are used:
!

= invert (complement),

#

= logical OR, & = logical AND

The I/O channel of the IBM PC supplies a 4.77 MHz
signal of 33% duty cycle. This would do for the system
clock. It was decided to generate a separate clock on
the StarLAN board to be independent of the I/O channel clock so that this board can also be used in future
IBM PCs and also in some other compatibles. The 8
MHz clock is converted to MOS level by 74HCOO and
fed into both the system and serial clock inputs.

The data bus DO to D7 is buffered from the 82588 by
74LS245. The transceiver is always kept enabled. The
direction of the transceiver is switched whenever a read
operation is done by the CPU OR THE DMA controller using the equation:
DIR = lOR' # (DACK1' & DACK3' & CS*);

A part of the PAL (first 4 equations) is used to correct
a problem with the timing of WR and DACK signals
which is relevant only to the A-2 stepping of the 82588.
B-step will not require the correction, although it will
also work with this circuit.

7.5.1.3 DMA INTERFACE
The 82588 requires two DMA channels for full operation. In this application, one channel is dedicated for
reception and the other is used to do transmit and the
other commands. Could you get away if you had just
one DMA channel available? Although using the IEEE
802.3 protocol you either transmit or receive but not
both simultaneously, if a channel is not dedicated to
reception, you may lose a frame if you had just one
DMA channel and were about to use it for transmitting. Such a lost frame can only be recovered at a higher level of communications software. So the recommendation is not to .operate with just one DMA channel. It
is, however, possible to operate without losing frames
and using just one DMA channel. Appendix B describes this method.

7.5.1.2 CLOCK GENERATION

The 82588 requires two clocks for operation. The system clock and the serial clock. The serial clock can be
generated on chip by putting a crystal across X I and
X2 pins. Alternatively, an externally generated clock
can be fed in at pin XI (with X2 left open). In both
cases, the frequency must be either 8 or 16 times (sampling factor) the desired bit rate. For StarLAN, 8 or 16
MHz are the correct values to generate I Mbls data

x (MHz)

CI (pI) C2 (pI)
1-8
0-30
0-40
8-16
0
0-10
At 16 MHz, operation with
CI ~ C2 ~ 0 pf show no
problems
Xl

rate. A configuration parameter is used to tell the
82588 what the sampling factor is. An externally supplied clock must have MOS levels (0.6V -3.9V). Specifi·
cations for the crystal and the circuit are shown in Figure 7-30.

The IBM PC system board has one 8237A DMA controller. Channel 0 is used for doing the refresh of
DRAMs. Channels I, 2 and 3 are available for add-on
boards on the I/O Channel. The floppy disk controller
board uses the DMA channel 2 leaving exactly two
channels (1 and 3) for the 82588. The situation is worse
if the IBM PC/XT is used, since it uses channel 3 for
the Winchester hard disk leaving just the channel I for
the 82588. On the other hand, the IBM PCIAThas 5
free DMA channels even after the floppy and the hard
disk consume one each. We will assume that 8237A
DMA channels I and 3 are available for the 82588 as in
the case of the IBM PC.

I---t---,

82588
X2

Recommended Crystal
Fundamental mode operation
231422-32
Max Effective Series Resistance (ESR) ~ 30n
± 0.005% tolerance @ 25 'C
± 0.01 % tolerance for 0-70 'C
Manufacturer CRYSTEK claims to satisfy these specifications.

Since the channel 0 of 8237 A is used to do refresh of
DRAMs all the channels should be operated in single
byte transfer mode. In this mode, after every transfer
for any channel the bus is granted to the current high-

Figure 7-30. Crystal Specs

7-27

intJ

Ap·236

est priority channel. In this way, no channel can hog
the bus bandwidth and, more important, the refresh of
DRAMs is assured every 15 microseconds since the refresh channel (number 0) has the highest priority. This
mode of operation is very slow since the HOLD is
dropped by the 8237A and then asserted again after
every transfer. Demand mode of operation is a lot more
suitable to 82588 but it cannot be used because of the
refresh requirements. Flip-flops are used to interface
the DRQ lines from the 82588 to the I/O channel to
cut off the DRQ'after every transfer. This prevents the
8237A from locking up if the 82588 releases the DRQ
line after the transfer has occurred having held it active
for the duration of the transfer. It also prevents the
interference to the refresh timing if the 8237A were
programmed in the demand inode for the 82588.

telephone modular jack on the StarLAN board and the
other end into a modular jack in the wall. The twisted
pair wiring starts at the modular jack in the wall and
goes to the wiring closet. In the wiring closet, another
telephone extension cable is used to connect to a
StarLAN HUB. The transmitted signal from the 82588
reach the on-board telephone jack through a RS~422
driver with pulse shaping and a pulse transformer. The
received signals from the telephone jack to the 82588
come through pulse transformer, squelch circuit and a
receive enable circuit.

7.5.1.4 INTERRUPT CONTROLLER

The 82588 interrupts the CPU after the execution of a
command or on reception of a frame. It uses the 8259A
interrupt controller on the system board to interrupt
the cpu. There are 6 interrupt request lines, IRQ2 to
IRQ7, on the I/O channel. Figure 7-31 shows the assignment of the lines. In fact, none of the lines are free
for use. To add any new peripheral which uses a system
board interrupt you have to see that the board that
normally uses that interrupt is not being used. It was
decided to use IRQ5 for the 82588. The INT signal
from the 82588 is buffered and connected to IRQ5.
Number

Usage

NMI

Parity
Timer
Keyboard
Reserved
Asynchronous Communications
(Secondary)
SDLCCommunications
SSC (Secondary)
Asynchronous Communications
(Primary)
SDLC Communications
SSC (Primary)
Fixed Disk
Diskette
Printer

0
1
2
3

4

5
6
7

WIRING
PANEL

IN THE WIRING CLOSET
231422-33

Figure 7·32. Path from StarLAN Board to HUB
7.5.2.1 TRANSMIT PATH

The single ended transmit signal on the TxD pin has to
be converted to a differential signal, for noise immunity, and the rise and fall times increased to 150 to 200
nanoseconds before feeding it to the pulse transformer.
Am26LS30 is a RS-422 driver which converts the TxD
signal to a differential signal. It also has slew rate control pins to increase to rise and fall times. A large rise
and fall time is a key requirement for operation at
1 Mb/s on telephone grade wires to cut out cross-talk,
interference and radiation. The 26LS30 converts a
square pulse to a trapezoidal one--see Figure 7-33. The
filtering effect of the cable further adds to reduce the
higher frequency components from the waveform so
that on the cable the signal is almost sinusoidal. The
pulse transformer is for DC isolation. Pulse transformers from Pulse Engineering-type PE 64352-are specially designed for StarLAN. They introduce an additional rise and fall time of about 70-100 ns on the
signal. Dual pulse transformers in 14 pin DIP are manufactured under the part number PE 64382.

Figure 7·31. IBM PC Hardware Interrupt Listing

7.5.2 Serial Link Interface
The StarLAN board is connected to the twisted pair
wiring using an extension cable (up to 8 meters-25
ft.). See Figure 7-32. One end of the cable plugs into the

7-28

AP-236

RTS

82588

II~

TxD

150ns
RISE/FALL
TIMES
231422-34
'Pulse shaping needed to reduce cross-talk, radiation and noise.
'S Volt peak-to-peak voltage at the driver side of the cable.

Figure 7-33. Wave Shaping

and is used to AND the signal from the real zero crossing receiver before feeding it to the RxD pin of the
82588. RxD pin requires a MOS level input for the A-2
stepping of the 82588 hence 74HCOO is used to interface the receive signal to the 82588. For the B-stepping
RxD will be a TTL level input.

7.5.2.2 RECEIVE PATH

The signal coming from the HUB over the twisted pair
wire is received on the StarLAN board through a 1100
line termination resistor and a pulse transformer. The
pulse transformer is of the same type as for the transmit
side and its function is dc isolation. The received signal
which is differential and almost sinusoidal is fed to the
Am26LS32 RS-422 receiver. As seen from the Figure
7-27 the pulse transformer feeds two RS-422 receivers.
The one on the top is for squelch filtering and the one
below is the real receiver which does real zero crossing
detection on the signal and regenerates a square digital
waveform from the sinusoidal signal that is received.
Proper zero crossing detection is very essential; if the
edges of the regenerated signal are not at zero crossings, the resulting signal may not be a proper Manchester encoded signal even if the original signal is valid
Manchester. The resistors in. the upper receiver keep its
differential inputs at a voltage difference of 600 m V.
These bias resistors ensure that the output of the upper
receiver remains high as long as the input signal is less
than 600 mY. It is very important that the RxD pin
remains HIGH (not LOW or floating) whenever the
receive line is idle. A violation of this may cause the
82588 to lock-up on transmitting. Remember, that
based on the signal on the RxD pin, the 82588 extracts
information on the data being received, Carrier Sense
and Collision Detect. This squelch of 600 mV keeps the
idle line noise from getting to the 82588. Figure 7-34
shows that when the differential input of the receiver
crosses zero, a transition occurs at the output. It also
shows that if the signal strength is below 600 mV, the
output does not change. Note that the differential voltage at the lower receiver input is zero when the line is
idle_ The output of the squelch goes to a pulse stretcher
which, as shown in Figure 7-35, generates an envelope
of the received frame. The envelope is a receive enable

..J

~

800

z
w
w

......""
i5

mV

600
400
200

""

0

w .....
~:::>
wa.
<.>z
w-

-200

f

-400

""

FILTERED-OUT
BY SQUELCH

5rj~e:
f5 5
:::>0:::>

g~o

H
VVO
OL

~5

5

iii
:go
Za.

VOH

~f5
o~

f5 t!
N~

VOL

ms
tDlliJJ
I

t

-+___________________________
231422-35

Figure 7-34. Squelch Circuit Output

7·29

AP-236

::Jjll . . _
J

I

300n

COUNTER

300n

CLR

82588

ENb----...

8MHz
RECEIVED DATA --u--LF1ILr--------~

RECEIVE ENABLE

---1

231422-36

·Squelch circuit suppresses noise on an idle line.
'0.6 volt threshold recommended for squelch.

Figure 7-35. Receiver Circuit

ic, wait state generator, ready logic and clock generator
functions on chip. Figure 7-36 shows how the 82588, in
a StarLAN environment interfaces to the 80188. It uses
the clock, chip select logic, DMA channels, interrupt
controller directly from the 80188. The interface between the CPU and the 82588 is totally eliminated.

7.5.3 Cost
The parts needed for the circuit used cost about $70 in
Ik quantity in 1985. It occupies a board area of about 9
sq. inches (60 sq. cm). Beside the 82588, 2 pulse transformers, one receiver, one driver, one PAL and 5 SSI
TTL chips are needed. A telephone modular jack and
some passive components are also needed. Note that 3
of the 5 SSI chips would not be needed if the StarLAN
interface were to sit on the motherboard.

7.5.5 iSBX Interface to StarLAN
Figure 7c37 shows how to interface the 82588 in a
StarLAN environment to the iSBX bus. It uses 2 DMA
channels-tapping the second DMA channel from a
neighboring iSBX connector. Such a board can be used
to make a StarLAN to an Ethernet or a SNA or
DECNET gateway when it is placed on an appropriate
SBC board. It may also be used to give a StarLAN
access to any SBC board (with an iSBX connector) independent of the type of processor on the board.

7.5.4 80188 Interface to 82588
Although the 82588 interfaces easily to almost any
processor, no processor offers as much of the needed
functionality as the 80186 or its 8 bit cousin, the 80188.
The 80188 is 8088 object code compatible processor
with DMA, timers, interrupt controller, chip select log-

7-30

l

4

iii[ SICotlAL CORRECTIOH

-"

lEon

PAL 16L8 EQUATIOHS ( ABEL roRHAT )

!

rsl'•fi"Z""i"'""j(
lllDACKa

DACK8e_ •

(

lOR_ &. lOW_

DACI(0.

DACKe1-

(

lORa

DACK1_

LEGEND:

"1\

mi Fo"~"•• _-+-l-.LI
iW~
RES~~ ~I\
~:~~ ¥.~~ ~~,

I:

Cil

Z!~
(.)

a..

IOU-

SQUELCH

&

'" AND . . . .

OR.

1

~INlJERT

88188

~i

-...I

~

",Ria .. 10l.:a
URa
• URla

CD

':;,' t;

CD

:~~ ~'

AD2 6

CD

ADe 2
25

ADS
ADS

o
....
CD

.... :;

ADI

~

i

15
19

4

CLKDUT 56

300..n.

~121

~: ~::
IN~
6
"1 D?

:t ~~

iTD4
DS

lT
i"~"D2
It1

1

»
R)(Dpi
R"XC .... 1i:
X2

l'
I\)

Co)
0)

N .... C

2:::;;

1

141USS

Ul

TxC

RECEI UE ENABLE

"'xl.~1715,-~_-

CLK.:~~4_ _ _ _ _ -

0'
CD

~

CD
CD
a.a NOTES
-26LS32
-

-

PINS 16. <4 aUeC
PINS 8.12 .. aND
2£LS3e
PIN! '" +5V
PINS 4.5.8 '"' eND
PHONE-JACK
(BOTTOM UIEi.O

4

231422-37

(
iili SIGNAL CORRECTIOH
PAL 16LB EQUATIOMS ( ABEL' FORHAT )

lOR

0;:;

DACK0e. -

(
DACKel_ '" (
WRllll • IOU_
I-IRlII
= URI_

SBX BUS

LEGEND:

+5"
.15-4
(,]4-32)

ORM l!o. IOW_.

OR_ &

IOU_

&. co AND • • '" OR.

)
)

+SV

Ie DACK0w

•

DllIe"1l11

90Q.!L

, "'INVERT

~

'~.

J5-32~

~~=i:

g

SQUELDI

seen

Ig~:T

']5-1S~

~
JS-a4~

:!!

CD
C

...

.16-5
(14-34)

...Q
CD

J5-21

;-I

en

m

~ ><

I\)

a

~
~
J5-19~
~

J5-30
.]5-22

J5-23

~

JS-25
J5-27
J5-29

~
~

TxDI":"

C>--iffiT

.J5-31~


1~"''''~LJ5

SIGNAL

l

CARR I ER SENS I NG

SQUELCH

OD

-=>:..::: ,

RCO

ENP

CRS' En (EA.EE-.EC

Cl:'

ED)

ENT
~nR

lOtttl,l.,. ____

2

U3
U3.

u..
uac
usn

U2AB
U2CD

liOn

~
c

..

~ ::I

•

Rn eRA. R:B. RC Or' RD)

2&LS32

CD-

ONE

";'I

ARH

OF

HUB

~

p

~

-;-J !j;
g:: Z
::J:

c:
m

W
:::T

~
an"
1/1

+5u

(S ..... U4A)

EA:

o:.8/U4B)
(e ..... u4C)

Ell

.
~ ~;~~~~~):~ :

1

~

I

••• HOTES
-

26L5ae
pall

EC~

~~~~;~~) ~~

~

(11/U2CD) RD •

j

GtlD

l'

N

Co)

en
26L532

COLLISION
14
13
~
15
U
2

FLIP-FLOP

q;

26L532

-

CL
U6

e =

~

-

~n
;::::=
i~ }L~J:!I

l>

'" +51)

PINS 4.6.

9
~r:L 11
~
26LS32

PHONE-JACK

CBOTTOM UIEL.D

PAL 16LB EQUATIOHS (ABEL FORHAT>
ENAIL

.. (EA ... Ell: .. EC •

Ell;'

ENABLW

'" IEHABL;
- EHAIIL
EA eo. !EI &.
(!EA &0.
EJ &.
(lEA t.;. IE) 1\0.
(lEA ISo. IE) eo.

lEt &
lEt &

COLL IS

..

,«

COLLI!

~

RCU

-

!COLLIS;
eRA. !EA} l

SIGNAL

.. (ReV

CRt.
(CS

LEGEND:

eo.

~.

EC
lEt

eRI ...

lEC> l (RD ...
! COLlEH) ..

;

6;.
&.

!ED)
!ED)

'ED) •
ED»;

!E2) &
!ED);

COLLEII);

& '" AND •.• '" OR.

I

INVERT

.
231422-41

AP-236

I 2t I t I 2t I 2t It i t =0.5 j.ts
r-Sj.ts PERIOD-I
• MISSING MID-CELL TRANSITION

231422-42

• Collision Presence Signal (CPS) is generated by the HUB when it detects more than one input line active.
• CPS violates Manchester encoding rules-due to missing mid-cdl transitions-hence is detected as a collision by the DTE (82588).
Choice of Collision Presence Signal
• It is a Manchester look-alike signal-edges are 0.5 or 1.0 I-I-s apart.
-Identical radiation, crosstalk and jitter characteristics
-Eases retiming of the signal in the HUB
• It is easy to generate-1.5 TTL pack, or in a PAL
Figure 7-41. Collision Presence Signal
One may wonder why such a strange looking signal. was
selected for CPS. The rationale is that this CPS looks
very much like a valid Manchester signal-edges are
0.5 or 1.0 microsec. apart-resulting in identical radiation, cross-talk and jitter characteristics as a true Man.chester. This also makes the re-timing logic for the signals simpler-it need not distinguish between valid
Manchester and CPS. Moreover, this signal is easy to
generate.

o

o

o
COLLISION

"""--"'1 PRESENCE
SIGNAL
D

Two important requirements for CPS are: a) it should
be generated starting with a low phase and b) once it
starts, it should continue ilntil all the input lines to the
HUB die out. Typically, when the collision occurs, the
multiplexor in the HUB switches from RCV signal to
the CPS. If just, before switching the phase of the RCV
signal is high and if CPS were to start with a high, the
output signal going back to the nodes may remain high
for over 1.5 bit times. This would be interpreted by the
node, according to IEEE 802.3 specifications, as a loss
of Carrier. The restriction a) prevents this. The restriction b) ensures that the CPS is seen by all nodes on the
network since it is generated until every node has finished generating the Jam pattern.
'

Q

231422-43

Figure 7-42. Collision Presence Signal
Generation

'Ro
Rb

CPS is generated using a 4 bit shift register and a flipflop as shown in Figure 7-42. It works off a2 MHz
clock. A closer look at the CPS waveform shows that it
is inverse symmetric within the 5 microseconds period.
The circuit is a 5 bit shift register with a complementary feedback from the last to the first bit. The bits remain in defined states (01100) till collision occurs. On
collision the bits start rotating around generating the
pattern of 0011011001, 0011011001, 00110 ... with
each state lasting for 0.5 microseconds.

ENABL

PREAMBLE
PREAMBLE

JAM
JAM

---II""---------,L-

COLLEN

SIGNAL

I Ro ICOLLISION PRESENCE SIGNAL I
231422-44

Figure 7-43. Collision Scenario at the HUB

Figure 7-43 shows a typical collision scenario at the
HUB. Two nodes A and B with their signal Ra and Rb
collide. Ea and Eb are their carrier sense or enable signals. The output SIGNAL could be ,seen switching
7-36

inter

AP-236

from Ra to the Collision Presence Signal as soon as Ea
and Eb are both active. CPS remains active till COLLEN remains active-i.e. till either Ea or Eb is active.

being pumped into the FIFO. The signal regeneration
unit reads the FIFO and generates the output waveform out of 8 MHz clock pulses based on what it reads:

7.6.1.4 SIGNAL RETIMING

INDAT

Whenever the signal goes over a cable it suffers jitter.
This means that the edges are no longer separated by
the same 0.5 or 1.0 microseconds as at the point of
origin. There are various causes of jitter. Drivers, receivers introduce some shifting of edges because of differing rise and fall times and thresholds. A random sequence of bits also produces a jitter. A maximum of 90
ns of jitter can accumulate in a Star LAN network from
a node to a HUB or from a HUB to another HUB. The
following values are proposals and are not yet finalized
in the !BASES standards draft (June 1985):
Transmitter
± 5 ns peak
Cable Intersymbol
± 20 ns peak
Cable Interference
± 50 ns peak
± 5 ns peak
Receiver
± 10 ns peak
HUB
Total

±90 ns peak

It is important that the signal is cleaned up of this jitter
before it is sent on the next stretch of cable because if
too much jitter accumulates, the signal is no longer
meaningful. A valid Manchester signal would, as a result of jitter, may no longer look like valid Manchester.
The process of either re-aligning the edges or reconstructing the signal or even re-generating the signal so
that it once again "looks new" is called re-timing. Its
also called "dejittering". StarLAN requires that the signal is re-timed after it has travelled on a segment of
cable. In a typical HUB two re-timing circuits are necessary; one for the signals going upstream towards the
higher level HUB and the other for signals going downstream towards the nodes.

OUTDAT

231422-45

SIGNALS DEFINITION
indat

Input data

edd

edge detection pulse, used to load output of pulse descriminator in the fifo,
and to increment the threshold detector.
pulse logic level, input to fifo .

. Ivin
. Isin

pulse long/short descrimination, input
to fifo

frd

fifo read pulse
pulse logic level, output from fifo.

Ivout
Isout

pulse long/short descrimination, output from fifo.

enr

enable pulse regeneration, a function of
fifo threshold.
Figure 7-44. Signal Retiming Circuit

7.6.1.5 DESIGNING THE RETIMING CIRCUIT
FIFO
S,1
S,O
L,O
L,1

The HUB shown in Figure 7-40 does not have a re-timing circuit. However, this section will discuss the principles of designing a re-timing circuit. Figure 7-44
shows the block diagram of a re-timing circuit. The
data coming in is synchronized using an 8 MHz sampling clock. Edges in the waveform are detected doing
an XOR of two consecutive samples. A counter counts
the number of 8 MHz clocks between two edges. This
gives an indication of long (6 to 10 clocks) or short (3
to 5 clocks) pulses in the received waveform. Pulses
shorter than 3 clocks and longer than 10 clocks are
ignored-allowed to pass through. It is assumed that
these conditions occur only during idle state. Every
time an edge occurs, the polarity of the waveform and
the length-(S)hort or (L)ong-of the pulse is fed into
the FIFO. Retiming of the waveform is done by actually generating a new waveform based on the information

Output
1111
0000
00000000
11111111

Example:
Input Waveform ...
001111000000011111111110001111100
Input into
the FIFO

7-37

I I

I <~,O> I

 

AP-236

,  ,, , 
FIFO is regenerated as:
111100000000 11111111 0000 1111

from

(3)- Timer 2 runs out. CPS is stopped. If input(s) not
yet idle, the active inputs are disabled. Timer 3 is
started.
(4)- Timer 3 runs out. Disabled units may be enabled.

the

It could be seen that the output always has edges sepa-

rated by 4 or 8 clock pulses-O.5 or 1.0 microseconds.

The current definitions of the jabber timers Tl, T2 and
T3 are:

The FIFO is primarily needed to account for a difference of clock frequencies at the source and regeneration
end. Due to this difference, data can come in faster or
slower than the regeneration circuit expects. A 16 deep
FIFO can handle frequency deviations of up to 200
ppm for frame lengths up to 1600 bytes. The FIFO also
overcomes short term' variations in edge separation. It
is essential that the FIFO fills in up to about half before
the process of regeneration is started. Thus, if the regeneration is done at a clock slightly faster than the
source clock, there is always data in the FIFO to work
from. That is why the FIFO threshold detect logic is
necessary, which counts 8 edges and then enables the
signal regeneration logic.

Tl: 25-100 ms; 2-8 times maximum frame size
T2: 5-40 ms; 10-80 times slot time
T3: 20-80 times Tl

JT1...J
JT2 _ _ _--'
JT3 _ _ _ _ _ _ _..1

DISABLE
PORT--------~

7.6.1.6 DRIVER CIRCUITS

SEND
CP SIGNAL --------...

The signal coming o~t of the PAL is sent back to the
nodes in a 1 level HUB. The driver circuit used is identical to the one used in the node on the StarLAN board.
Am26LS30 RS-422 driver is used to drive the pulse
transformer. The slew rate capacitors on the drivers
increase the rise and fall times of the pulses to 150 ns as
required by StarLAN to overcome the cross-talk and
radiation problems. The same signal is sent to all nodes
on different drivers, pulse transformers and wires. For
a multi-level HUB, the routing of signals is done as
shown in Figure 7-39.

231422-46

Figure 7-45. Jabber Timing Relations

7.6.2 HUB Reliability

7.6.1.7 JABBER FUNCTION

This design does not implement the jabber unit but it is '
described here for complete~ess. IEEE 802.3 does not
require this feature; it is an option. The jabber function
in the HUB is to deal with abnormally long transmissions on the network by any node. The jabber unit
monitors the time taken by any single transmission. If
this exceeds a time-out value Tl, then the HUB transmits the CPS signal until all inputs become idle. If all
inputs are not idle in time T2, then the Jabber unit
disables (or ignores) the active inputs and treats them
as idle. The Jabber unit can re-enable the disabled inputs after a time T3. These timing relations are shown
in Figure 7-45. It shows the outputs JTl, JT2 and JT3
of the 3 timers needed to implement this function. Instances (1), (2), (3) and (4) show the following events
and actions:
(I)-Start of transmission.
(2)- Jabber Timer 1 times out here, if the input(s) are
active, Timer 2 is started and CPS is generated
and propagated.
7-38

Since the StarLAN HUBs form focal points in the network, it is obviously important that they are very reliable, since it can be single point of failure which can
affect a number of nodes or can even bring down the
whole network. Initial studies done by AT&T on their
20 node HUB have shown that they have a MTBF of 7
years and the most unreliable part is the connector (the
telephone jack). Additional studies done by TANDEM
Computers have shown that a fault tolerant HUB is not
a necessity.

7.7 SOFTWARE DRIVER
The software needed to drive the 82588 in a StarLAN
environment is not different from that needed in a generic CSMA/CD environment. This section goes into
specific procedures used for operations like TRANSMIT, RECEIVE, CONFIGURE, DUMP; ADDRESS
SET-UP, etc. A special treatment will be given to interfacing with the IBM 'PC-DMA, interrupt and I/O.
Since all the routines were written and tried out in
PLM-86 and ASM-86, all illustrations are in these lariguages.

inter

AP-236

call co(CHAR_OUT);
/* to output CHAR_OUT on screen */
call cos(@('THIS IS A MESSAGE.$'»;
/* output string * /
/* note $ terminator * /

7.7.1 Interfacing to IBM PC
The Star LAN board interfaces to the CPU, DMA controller and the interrupt controller on the IBM PC system board. The software to operate the 82588 runs on
the system board CPU. The illustrated routines in this
section show exactly how the software interface works
between the system resources on the IBM PC and the
Star LAN board.

7.7.2 Initialization and Declarations
Figure 7-47 shows some declarations describing what
addresses the devices have and also some literals to help
understand the other routines in this section.

7_7.1.1 DOING 1/0 ON IBM PC

The safest way to use the PC monitor as an output
device and the keyboard as the input device is to usc
them through DOS system calls. The following is a set
of routines which are handy to do most of the I/O:
ks ci co coscis -

to
to
to
to
to

Figure 7-48 shows the initialization routines for the
IBM PC and for the 82588. It also shows some of the
typical values taken by the memory buffers for Configure, lA_Set, Multicast and transmit buffers.

find out if a new key has been pressed
read a key from the keyboard
display a character on the screen
display a character string on the screen
read in a character string from the keyboard

7.7.3 General Commands

The exact semantics and the protocol for doing these
functions through DOS system calls is shown in the
listing in Figure 7-46. Refer to the DOS Manual for a
more detailed description. To make a DOS system call,
register AH of 8088 is loaded with the call Function
Number and then, a software interrupt (or trap) 21 hex
. is executed. Other 8088 registers are used to transfer
any parameters between DOS and the calling program..
The code is written in Assembly language for register
access. Let us take an example of the 'cos' routine:
Ids dx,STRINGJOINTER; load pointer to string in
reg. ds:dx
movah,09h
; 9 = function number
for string o/p
; DOS System Call
int 21h

Examples of using the I/O routines:
=

Example: Configure Command
To configure the operating environment of the 82588.
This command must be the first one to be executed
after a RESET .
call DMA_LOAD(1,1,12,@CONFIG_588);
output (CS_588) = 12h;
The first statement is the prologue to the configure
command to the 82588 which calls a routine to load
and initialize the DMA controller for the desired operation. this routine is described in section 7.7.4. The parameters for DMA_LOAD are:
first parameter = 82588 channel number ( = I)
second parameter = direction ( = I, memory to
82588)
third parameter = length of DMA transfer ( = 12)
fourth parameter = pointer to memory buffer
( = @CONFIG_588)

These procedures are called from another module, written in a higher level language like PLM-86. The parameters are transferred to the ASM-86 routines on the
stack.

KEY _STATUS

Operations like Transmit, Receive, Configure etc. are
done by a simple sequence of loading the DMA controller with the necessary parameters and then writing
the command to the 82588.

ks;

The second statement writes 12h to the command register of the 82588 to execute a Configure command on
channell.

/* inquire keyboard status * /
/* input new key * /

When the command execution is complete (successfully
or not), 82588 interrupts the 8088 CPU through the
8259A, on the system board. This executes the interrupt service routine, described in section 7.7.5, which
takes the epilogue action for the command.

call cis(@LINE_BUFFER);
/* string input * /

7-39

inter

AP-236

Most operations are very similar in structure to Configure. The 82588 Reference Manual describes them in
detail. Figure 7-49 shows a listing of the most commonly used operations like:
CONFIGURE INDIVIDUAL-ADDRESS
(IA)
SET-UP
(MC)
MULTICAST-ADDRESS
TRANSMIT
SET-UP
DIAGNOSE
RECEIVE (RCV)-ENABLE
DUMP
RECEIVE (RCV)-DISABLE
TDR
RECEIVE (RCV)-STOP
RETRANSMIT READ-STATUS

P is in segment:offset form. The first part of, the
DM~LOAD procedure converts this to a linear 20
bit form. The lower 16 bits are loaded into the DMA
Address register (dma_addr) of 8237A in two 8 bit
write operations. The upper 4 bits are loaded into the
Page register (dma_addrh). Note that there is no overflow from the 8237A address register to the page register.
.
Figure 7-51 is a listing of the DMA_LOAD procedure
for the 80188 or 80188 on-chip DMA controller. It has
the same caller interface as the 82371\. based one. .

7.7.5 Interrupt Routine
7.7.4 DMA

The interrupt service routine, 'intr_588', shown in
Figure 7-52, is invoked whenever the 82588 interrupts.
It is basically a reentrant interrupt procedure that starts
with re-enabling the interrupts-to permit a receive interrupt preempt the post transmit interrupt processing.
It takes action based on what event has caused the interrupt. For all the events that use DMA, it disables the
DMA channel. For the transmit and retransmit events,
it increments some statistical data counters based on
the status information. For the receive event, it first of
all extracts the receive status information at the end of
the received fram~ven in case of a multiple buffer
reception-and increments statistical data counters.
This is a dummy interrupt handler. A real interrupt
handler would do functions like buffer release, buffer
acquisition, etc.

Routi~es

DM~LOAD

procedure is used to program the
8237A DMA controller for all the operations requiring
DMA service. It also starts or enables the programmed
DMA channel after programming it. Figure 7-50 shows
the listing of this procedure. It accepts 4 parameters
from the calling routine to decide the programming
configuration for the 8237A. The parameters for
DM~LOAD are C, D, Land P:
first parameter - C - 7"
second parameter- D - =
third parameter - L - =
fourth parameter - P - =

82588 Channel number
Direction
Length of DMA transfer
Pointer to memory buffer

if P = 0 then 8237A channel = 1;
if P = 1 then 8237A channel = 3;

Interrupt service routines should be kept as short as
possible. This is to enable reception of back-to-back
frames and also to transmit frames separated by interframe spacing. .

if D=:O then transfer is from 82588 to memory block
if D = 1 then transfer is from memory bloc~ to 82588
L

> = data block to be transferred

Note that L need not be exactly equal to the length of
the block of data to be transferred. The 82588 stops
. generating DMA requests after it has performed the
required number of data transfers. .

7-40

AP-236

$title(' ••••••... I/O Routines for the IBM PC •.•••.••.•• ')
; Sharad Gan:Ih.i, IXX> Technical Marketin;J, INTEL Corp.

; Routines to do I/O on the IBM PC
Declarations in the call:irq PIM-86 Ra.rtine

,
;ks: procedure byte external;
;errl ks;

1*

;ci: procedure byte external;
;errl ci;

1* console irtp.lt rc::utine *1

key status rc::utine

*1

,
;

;co: procedure(char) external;
;declare char byte;
;errl co;

1* console outp.It routine *1

;cos: procedure(strP.) external;
;declare strytr pointer;
;errl cos;

1* console str:irq output rc::utine *1

;cis: prooedure(strP.) external;
;declare strytr pointer;
;errl cis;

1* console str:irq irtp.lt rc::utine *1

,
,

name pc::io

plblic ks, ci, co, cos, cis
stal sb:uc
old q,l dw ?
old-ipl dw ?
str:::Ptr d::i ?
stal ems
sta2

sb:uc

;stack layout

;stack layout

old q,2 dw ?
old-ip2 dw ?

am:
sta2

db?

eros

a:Jl:O.lP group code

code segment plblic

'code'
Figure 7-46. 11.0 Drivers for IBM PC

7-41

inter

AP-236

assume cs:cgroup

-----Keyl::xlimi s t a t u s ' - - - - - ks

near

proc

lI¥:IV

int

ah, Ol::il
2lh

~
~

~

ret

to chec:k key inpIt status
oos function call
key status in AL register

-----Console

Inp.rt:--------

ci pnx:: near
lI¥:IV

int

ah, OSh
2lh

ret

~
~
~

to get key inpIt fran PC
oos function call
key inAL register

ci endp
----~Console

o.rt:pIt,-------

co proc near
p..lSb. ax
p..lSb. dx
JIrN
dl, [bp] .c:har~ c:haracter fran stack
JIrN
all, 02h ~ aItplt c:haracter to R:
int 2lh
~ oos function call
pcp dx

pcp

ax

ret

2

co endp

Figure 7·46. 1/0 Drivers for IBM PC (Continued)

7-42

inter

AP-236

-----Oonsole string

rut:prt:-----

cos proc near
p.lSh l::p
l::p, sp
p.lSh ds
p.lSh cDc
p.lSh ax

lfOII

lds

cDc, [bp] .strytr
ah,09h ; output character string to PC
2lh
; oos function call

lfOII

int

ax

pop
pop
pop
pop
ret

cDc
ds
l::p
4

-----Oonsole strirg I r I p l t , - - - - -

cis proc near
p.lSh

l::p
l::p, sp

lfOII

p.lSh
p.lSh
p.lSh

ds'
cDc

lds

cDc, [l::p] .strytr
ah, Oah ; frIp..tt d'laracter string fran PC
2lh
; oos function call

JtrN

int
pop
pop
pop
pop
ret

ax

ax
cDc
ds
l::p
4

cis eOOp

Figure 7-46. 1/0 Drivers for IBM PC (Continued)

7-43

AP-236

/*----------------------~--~--------------------------- *1

/* chip

address declarations

declare cs_588

*/

/* 82588

literally '0300h';

~status

*1

declare pic_mask literally '02lh';
declare pic_ ocw2 literally '020h';

1* 8259A interrupt controller */

declare dma req literally 'Oah';
declare dma-lIDde literally 'Obh';
declare dma::::flff literally 'Och';

1*

8237A DMA Controller

*1

declare dma addr 1 literally
'02h';
declare dma-bc: 1-literally
'03h';
declare dma::::addrh...J literally '08Oh';
declare dma addr 3 literally
'06h';
declare ~bc: 3-literally
'07h';
declare dma::::addrh_3 literally '082h';

1*------------------------------------------------------------*1
1* literals *1
declare
declare
declare
declare

dma_on_1 literally 'Olh';
dma_on_3 literally '03h';
dma off 1 literally 'OSh';
dma::::off::::3 literally '07h';

declare enable 588 literally 'llOlllllb'; 1* unmask level 5 */
declare seoi""pIco literally 'Oll0010lb'; /* specific ED! level 101
declare dma_rx_mde_l
literally '0100010lb';
/* sinJle byte, rx mde, channel 1 *1

/* rx c::hannel. # 1 *1

declare dma rx mde 3
literally 'OlOOOlllb';
/* siii]le byti, rx mde, channel 3 *1,

/* rx channel # 3 *1

declare dma_tx_mde_l
literally '0100100lb';
/* sinJle byte, tx mde, channel 1 */

1*

tx channel # 1

*1

declare dma tx mde 3
literally '0100101lb';
1* siii]le byti, tx mde, channel 3 *1

1*

tx c::hannel. # 3

*1

*/

1*-------------------------------------------------------*1
Figure 7-47. Literal Declarations

7-44

infef

AP-236

1*---------------------------------------------------------*1
1* system initialize *1
SYS_init:

prooedure~

call set$interrupt (13,intr 588) ~ 1* base 8, level 5
outpIt(pic_mask) = inp..rt:(pic_mask) am enable_588~
outpIt(pic_0cw2) = seoiJ'ic:o~
intr_588_flag = O~

ern

*1

SYS_4Ut~

1*---------------------------------------------------------*1
1* 82588 init *1
init_588:

prooedure~

config_588(00)
config 588(01)
config-588(02)
config-588(03)
config-588(04)
config-588(05)
config-588(06)
config-588(07)
config-588(08)
config:588(09)
config 588(10)
confi9:588 (11)

= 10~
= OO~
= OOOOlOOOb~
= buff len/4~
= OOlOOIIOb~
= OOOOOOOOb~
= 96~

= O~
= 11IIOOIOb~
= OOOOOlOOb~
= 10001100b~
= 64~

1*

to configure all 10 parameters

1*
1*
1*
1*
1*
1*
1*
1*
1*
1*

oode 0, 8

*1

MHz clock, 1 Mb/s *1
Receive Buffer l~ *1
No l~, a&:h" len = 6, Preamble

Differential Manc:hester
IFS '" 96 'It:Il< *1

= off *1

= 8 *1

Slot tilDe = 512 'It:Il< *1
Max. No. Retries = 15 *1
Manc:hester encod.iIg ·*1
Internal CRS am CDl', CRSF = 4 *1
Min franva len;Jth = 64 bytes = 512 bitS

Figure 7-48. Initialization Routines

7-45

*1

inter

AP-236

ia set buff 588(0) - 6;
ia-set-buff-S88(1)
ia-set-b.iff-S88 (2)
ia- set-:''b.lff-S88 (3)
ia:set:buff:S88(4)
ia set buff 588(5)
izlset-buff-S88(6)
ia:set:buff:S88(7)

...
..
..
..
..
...
=

0;
OOOh;
04lh;
OOOh;
OOOh;
OOOh;
OOOh;

multicast buff 588(00) = 12;
multicast-bufrS88 (01) = OOh;
multicast-blfrS88 (02) .. llh;
multicast-buff-S88(03)
12h;
multicast-buff-S8B(04) = 13h;
multicastbuff-S88 (OS) = 14h;
multicast-buff-S88 (06) = 15h;
multicast-buff-S88(07) = 16h;
multicast-buff-S88(08) = 2lh;
multicast-buff-SB8 (09) ... 22h;
multicast-buff-S88 (10)= 23h;
multicast-bufrS88(1l) = 24h;
multicast-buff-S88(12) ... 25h;
multicast:buff:588(13) = 26h;

=

tx_buffer_588(OO)
tx_buffer_588(01)
tx_buffer_588(02)
tx_buffer_S88(03)
tx_buffer_S88(04)
tx buffer S88(OS)
tx-buffer.S88(06)
tx:buffer:588(07)

tx_frane_len md 256;
tx_frame_len / 256;
01lh;
/* initial destination address .. 11:(1)
0l2h;
013h;
014h;
II: 0l5h;
... 016h;

..
...
..
...
..
...

*/ '

em "init_S88;
/*------------------------------------------------~-------*/

Figure 7-48. Initialization Routines (Continued)

7-46

inter

AP-236

1*'---------------------------------------------------------*1
ia_set: prooedl.lre:
1* command - 01 *1
call dma load(1,1,8,@ia set buff 588):
intr 588-flag = Offh: ootPit (05 588) = 1lh:
1* ia_set to channel 1

retum:

*1

-

I*-------------------------~-----------*I'

cOnfig: procedure:

1*

command - 02

*1

call dma load(1,1,12,@config 588):
intr 588-flag = Offh:
ootPit (05_588) = l2h :
1* configure to channel 1

retum:

*1

em config:

1*------------------------------------*1
multicast: procedure:

1*

ocmmand - 03

*1

call dma load(1,1,14,@nUllticast buff 588):
intr 58S-flag = Offh:
-ootPit (05_588) = 13h: 1* multicast to channel 1

retum:

*1

em multicast:

1*-------------------------------------------------transmit: procedure(buffer_len,bufferJlOinter):

1*

CClIIIIIlaIXl - 04

*1

*1

declare buffer len word:
declare buffer:::pointer pointer;
tx buffer 588(00) = buffer len mel 256:
tx=J:Juff~588(01) = buffer=len I 256:
tx_buffJ'l:r = bufferJlOinter:
call ~load(1,1,1536,tx_buff_Ptr):
intr 588 flag = Offh:
ootPit (05 588) = 14h: 1* transmit to channel 1

retum:

-

*1

em transmit:

1*-------------------------------------------*1
Figure 7-49. General Commands

7-47

intJ

AP-236


*'--.--------------------------------~---------------------*I

tdr: procedure;

1*

ocmmand - 05

1*

tdr ocmmand

*1

intr 588 flag = Offh;

CR.It:plt (Cs_588) = 5;
retum;

*1

em tdr;
1*-----------------------------------------1*

dunp_588: procedure;

command -

06

-----------*/

*1

call dina load(1,0,64,@duxtp buff 588);
intr 588-flag = Offh;
CR.It:plt (Cs_588) = 16h.;
1* dunp to channel 1
retum;

*1

em dunp_ 588;
I*--------------------~------~---------------------------*/

diagnose: procedure;

1*

command - 07

*1

1*

diagnose cammand

intr 588 flag = Offh;

CR.It:plt (Cs_588)
retum;

= 7;

*1

I*--------------------------~-------------------------

rev_enable: procedure(channel,buffer....Ptr);

1*

cammand - 08

*1 _

*1

declare channel byte;
declare buffer....Ptr pointer;
buff alloc = 1;
1* # of buffers allocated
call-dina_load (channel, 0,1536 ,buffer....Ptr) ;
output(cs 588)= 8;

*1

retum; -

I*·----------------------~-----------------------------,

Figure 7-49. General Commands (Continued)

7-48

*1

AP-236

/*---------------------------------------------------------*/
rev_disable: proce:lure
/* command - 10 */
~

oot:p.It(cs 588)=
return~ -

10~

/*--------------- '-----------------'----------*/
rev_stop: procedure ~
output(cs 588)=
return~ -

em

/*

camrnand - 11

*/

11~

rev_stop ~

/*------------------------------------------------------*/
retransmit: proce:lure ~

/*

cammand - 12

*/

call dma_load(I,I,1536,'bU:lIlffytr) ~
intr 588 flag = Offh~
c:utPit (Cs_588) = 16b.~
/* retransmit to channel 1

return;

em

*/

retransmit~

~

~

/*

read_status_588: procedure~

=

return~

em

*/

/* release pointer, initial

oot:p.It (cs_588) = 15~
status 588(0)
input
status=588(1) = input
status 588(2) = input
status-588(3) = inp..Tt

command - 15

= 00

*/

(cs 588)~
(cs=588) ~
(cs 588) ~
(cs-588)~

-

read_status_ 588 ~

/*,------------------------~------------------------------*/
Figure 7·49. General ,Commands (Continued)

7-49

AP-236

/*'-------------------------------------------------------*/
dma_load: procedure (channel ,directian, transJen, ruff-Ptr) reentrant:
declare
declare
declare
declare

/*

channel byte:
channel 1/ */
direction byte:
/* 0 =:tX, 588 -> mem; 1 = tx, mem -> 588
trans len word:
/* byte OCP.lIlt */
ruff..Ptr pointer; /* ruffer pointer in se::r:offset form */

declare ruffytr_20bit dword; /* convert buffytr to 20bit buffytr
declare ptr1 pointer;
declare (wrd based ptr1) (2) word;
ptr1 = @buff~;
/* wrd (0,1) overlaps ruff-Ptr */
buffytr_20b~t = shl«buffytr_20bit := wrd(l» ,4) + wrd(O);
ptr1 = @buffytr_20bit;
/* wrd (0,1) Clll'erlaps b.lffytr_20bit */
do case channel am OOOOOOOlb;
do case direction am OOOOOOOlb;
do;
/* channel 1/ 1 , 588 (0) to memory */
o.rt:p.lt(dma req)
= dma off 1;
output (mna::::flff)
= 0; - 1* clear first/last flip-flop
output (dma lOCIde)
= dma :tX node 1;
o.rt:p.lt(dma=addr_1) = low-(wra(O»;
o.rt:p.lt(dma addr 1) = high (wrd (0) ) ;
o.rt:p.lt(dma=addrli_1) = low (wrd(l»;
output(dma be 1)
= low (trans len);
o.rt:p.lt(dma-be-1)
= high (trans-len) ;
output (dma= reCi>
= dma_on_1; 7* start Dl:A channel # 1
erxi;

*/

*/

do;
/* channel # 1 , memory to 588 (0) */
o.rt:p.lt (dma req)
= dma off 1;
o.rt:p.lt(dma=flff)
0; - 1* clear first/last flip-flop */
o.rt:p.lt (dma lOCIde)
= dma tx node 1;
o.rt:p.lt (dma- addr 1) = low- (wra (0) ) ;
o.rt:p.lt (dma- addr-1) = high (wrd (0) ) ;
o.rt:p.lt (dma- addrli 1) = low (wrd (1) ) ;
o.rt:p.lt(dma-be 1)- = low (trans len) :
o.rt:p.lt(dma-be-1)
= high(trans-len) ;
o.rt:p.lt (dma= reCi>
dma_ on_1; 7* start Dl:A channel # 1 */
erxi;

=

=

erxi;

Figure 7-50. DMA Routine

7-50

*/

*/

.

Ap·236

do case direction

am

OOOOOOOlb;

do;
/* C'llannel *3 , 588 (1) to JTelIDl:Y */
rutpIt(dIna_req)
= dIna_off_3;
cut:p.It(dIna_flff)
= 0;
/* clear fixst/last flip-flop */
cut:p.It (dina_m:xie)
= dina_ rx_m:xie_3 ;
cut:p.It(dIna_addr_3) = la.r (wrd(O»;
cut:p.It(dIna addr 3) = high (wrd (0) ) ;
cut:p.It(dIna-addrh 3) = la.r (wrd(l)};
cut:p.It (dina-be 3) = la.r (trans len) ;
cut:p.It(dIna-be-3)
= high(trans-len) ;
cut:p.It(dIna=reCi)
= dIna_on_3; 7* start IN. C'llannel # 3 */

em;

*

do;
/* C'llannel 3 , JDeIl¥):ty to 588(1) */
cut:p.It(dIna req)
= dina off 3;
.
cut:p.It(dIna=flff)
= 0; - Ii clear fixst/last flip-flop */
cut:p.It (dina m:xie)
= dina tx m:xie 3;
.
cut:p.It (dIna-addr 3) = lc::JW (wid (0) )" ;
cut:p.It(dIna-addr-3) = high(wrd(O» ;
cut:p.It(dIna-addrh 3) = la.r (wrd(l»;
cut:p.It(dIna-be 3)- = la.r (trans len) ;
cut:p.It(dIna-be-3)
= high(trans-len);
cut:p.It (dina= reCi>
= dma_on_3; 7* start IN. channel
3 */

*

em;
em;
em;
retum;.

em dma_load;
/*----------------------~-------------------------------*/

Figure 7·50. DMA Routine (Continued)

7-51

Ap·236

/*------------------------------------~----------------

*/

dma load: procedure (c::hannel, direction, trans_len, buffytr) reentrant;

/*

To load and start. the

~Ol86

I:MA controller for the desired operation

*/

literally' lOlOOOlOOlOOOOOOb'; /* rx channel */
/* s:rO=IO, dest=M(inc), syno=src, '.OC, noint, priority, byte */

declare dma rx node

literally 'OOOlOllOlOOOOOOOb'; /* tx channel */
/* s:rC=M(inc) , dest=IO, sync=dest, '.OC, noint, noprior, byte */

declare dma tx node
declare
declare
declare
declare

channel byte;
direction byte;
trans len word;
buff
pointer;

Ytr

/* channel # */
/* 0 = rx, 588 -> mem; 1 = tx, mem -> 588 */
/* byte count */
/* buffer pointer in .seg:offset fonn */

declare buffytr_20bit dword;
declare ptrl pointer;
declare (wrd based ptrl) (2) word;
ptrl = @buffP;
/* convert buffytr to 20bit buffytr */
buffytr_20bl.t = shl( (buffytr_20bit := wrd(l» ,4) + wrd(O) ;
do case channel and OOOOOOOlb;
do case direction and OOOOOOOlb;
do;
/* channel 0 , 588 to JDeII¥:):ty */
outword(dma_O_dpl) = lCM (buffytr_20bit);
outword(dma_o_<%'h) = bigh(buffytr_20bit);
outword(dma
spl) = ch a 588;
outword(dma-O-SIil) = 0;-outword(dma-o-te) = trans len;
outword(dma-0cw) = dma riC node or 0006h; /* start. I:MA channel 0 */
erxi;
- - -

°

°,

do;
/* channel
JDeII¥:):ty to 588 */
outword(dma
dpl) = ch a 588; .
outword(dma=o:<%'h) = 0;- outword(dma_O_spl) = lCM (buffytr_20bit);
outword(dma_O_SIil) = bigh(buffytr_20bit);
outword (dma 0 te) = trans len;
outword(dma-O-cw) = dma tX node or 0006h; /* start. I:MA channel 0 */
erxi;
- - erxi;

°

Figure 7-51. 80186 DMA Routines

7-52

AP-236

do case direction am 0000000]]:);
do;
/* channel 1 , 588 to JDeI'lDrY */
aJtwrd(dma_l_dpl) II: lCM CWff...,Ptr_20bit);
cut::I..'ord(dma_l_dpl) "" high(blff...,Ptr_2Obit);
cutwom(dma_l_spl) '" aLb_s88;
aJtwrd (dma 1 SIil) = 0;
cutwom(dma":"""l-tc) '" trans len;
cutwom(dma-l-cw) = dma riC m:xle or 0006h; /* start IJ.fA channel 1
end;
- - -:do;
cutwom(dma 1 dpl)
cutwom(dma-l-dpl)
cutwom(dma::::(:spl)
-cutwom(dma_l_SIil)
cutwom(dma 1 tc)
aJtwrd(dma-l-cw)
end;
- end;
end;

/* channel.

1 , me:m:>ry

*/

to 588 */

= ell b 588;
= 0;- = lCM (blff...,Ptr_20bit);
= high(blff...,Ptr_20bit) ;
= trans len;
= dma- ti- m:xle or 0006h; /*

start

IJ.fA channel 1

*/

return;
end dma_load;

/*-------------------------------------------------------'-~
Figure 7-51. 80186 DMA Routines (Continued)

7·53

AP-236

/*---------------------------------------------------------*/
intr_588: procedure interrupt 13 reentrant;
declare event byte;
enable;
call read status 588;
event = status 588(0) am 0000111lb;
if (status 588(0) am 00100000b) <> 0
then intr_588_flag = 0;

/* if execution event */
/* :reset interrupt flag */

do case event;
event 00: ;
event-01: outp..rt(dma req) = dma off 3; /* st:ql rnA channel # 3
event-02: output(c:htIareq) = dma:of(); /* st:ql rnA channel # 3
event-03: outp..rt(dma-req) = dma off 3; /* st:ql rnA channel # 3
event-04: do;
/* transmit done */
-outp..rt(dma req) = dma off 3;
/* st:ql rnA channel # 3
trans coiJnt = trans Ooo..mt + 1;
if (status 588(2) and 0010000Ob) <> 0
then do; good trans COl.Ult = good trans· COl.Ult + 1;
coll-c:nt(O) = coIl c:nt{O) +
end;else do;
if (status 588(2) arxi 10000000b) <> 0/* collision */
then do; intr_588_flag = 'X';
/* retransmit */
coIl c:nt(17) = coll c:nt(17) + 1;
end; end;
end;
event 05: ;
event-06: outp..rt(dma req) = dma_off_3; /* st:ql rnA channel # 3
event-07: ;
event-08: do; /* re-initialize rx dma */
- call rev_disable;

*/
*/
*/
*/

i:

*/

/* detemine receive status */
rx_buff_off = shl(double(status_588(2»,S)
+ double(status 588(1» - 2;
rx_buff_no = lCM(rxJ:uff_off / buff_len);
rx buff off = rx buff off m:xi buff len;
rx-bufroff = rx-bufroff + 1;
i rrx_Mf_off =-bufClen /* status across buff boundaries */
then do;
rx buff off = 0;
rx-buff-no = rx buff no + 1;

end;

-

--

Figure 7-52. Interrupt Service Routine

7-54

Ap·236

1* update network statistics

counters *1
if VbUffer_588(rx_buff-PO).rx(rx~f_off) and OOlOOOOOb)
then bad rev 0CA.lllt .. bad rev 0CA.lllt + 1:
else
reV_0CA.lllt = goOd_
0CA.lllt + 1:

goot

=0

rov_

call rev_enable(0,@buffer_588(0).rx(0»:

ern:

*

event 09:
event=lO:
event 11:
event=12:

call allocate buffer(ne'Wbuffer) :
ootpIt(dma_reCi> = dma_Off_l; 1* Elt:.ql DfA channel
1 *1
:
do: 1* re-transmit done *1
ootpIt(dma~req) = dma_off_3; 1* Elt:.ql DfA channel
3 *1
:retrans 0CA.lllt = :retrans cxmJt + 1;
if (status_588(2) and OOlOOOOOb) <> 0
then do;
gocx:i trans 0CA.lllt '" gocx:i trans 0CA.lllt + 1;
0011-cnt(status 588(1)
Ofh)
= ooIl_cnt(statUs_588(1) and Ofh) + 1;

*

am

ern;

else do;
if (status_588(2) and 10000000b) <> 01* OOl1ision
then do;
intr_588_flag .. 'X'; 1* retransmit *1
0011 cnt(17) .. 0011 cnt(17) + 1;

ern: -

-

i f (status 588 (1) and OOlOOOOOb) <> 0
then do: intr 588 flag .. 0;
OOl1=cnt(16) = CX>ll_cnt(16) + 1;

ern;

*1

1* max 0011. *1

ern;
ern;

event_l3: do; 1* execution aborted *1
ootpIt(dma_req) = dma_off_3;
intr 588 flag '" 'X':

ern; -

1*

Elt:.ql DfA channel

*

3

*1

-

event 14:
event=15:

ern;
ootpIt (CS 588) = 1000000Ob;
ootpIt(pic=0cw2) = seoi""pioo;

1* intac1t, *1
1* specific ED! for 82588 *1

retum;

1*'-----------------------------------------------------------*1

Figure 7·52. Interrupt Service Routine (Continued)

7-55

AP-236

APPENDIX A
StarLAN SIGNALS
ings. It is important that the receiver must generate
edges as close to the zero crossings as possible, otherwise the output of the receiver will have a different high
and low time than the original one.

Figure 7-53 shows the signals at various points on the
StarLAN link as seen on an oscilloscope. The output
from the 82588 (I) is a near perfect waveform with
square edges. After the driver with slew rate control the
rise and fall times increase to about 200 ns (2). After
the pulse transformer, on the cable at the driving end
the signal is almost sinusoidal (3), At the cable, on the
receiving end, the signal is attenuated and slightly distorted (4). However, the zero crossing points are preserved. After passing through a zero crossing receiver
the signal is reconstructed back to look like the original
waveform (5) generating transitions at the zero cross-

Figure 7-54 shows an eye diagram of the signal at the
receiver end for a bit time with the zero-crossing at the
center. It could be seen that around the 0.25 and 0.75
microsec. region, where the signal is sampled, 0.6 volts
threshold for squelch leaves enough noise margin (of
over 0.7 volts).

7-56

inter

AP-236

82588
TXD RTS

(1)-----

5 pF

5pF

(2)---

24 GAUGE
800 FT TWISTED PAIR WIRE
IN 25 PAIR BUNDLE

(.)~

231422-47
231422-55

Figure 7-53. StarLAN Signals

7-57

AP-236

Eye Diagram (5 Bits), DIW Cable
Manchester Encoded Signal
Transmission Distance = 0.8 Kit.
0
0
0
N

0
0
."

0
0
0

>8
..s."
....
en

z

0

!lio
....

'"....co

~o
0

0
>?
0
0
0

.
0
0
."

I
0
0
0
N

I

0.0

0.2

0.6

0.4

O.B

1.0

TIME ()LSEC)

231422-48

Figure 7-54. Received Signal Eye Diagram

intJ

AP-236

APPENDIX B
SINGLE DMA CHANNEL INTERFACE
In a typical system, the 8:;'588 needs 2 DMA channels
to operate in a manner that no received frames are lost
as discussed in section 7.5.1.3. If an existing system has
only one DMA channel available, it is still possible to
operate the 82588 in a way that no frames are lost. This
method is recommended only in situations where a second DMA channel is impossible to get.

If a frame is received, an interrupt for additional buffer

Figure 7-55 shows how the 82588 DMA logic is interfaced to one channel of a DMA controller. Two DRQ'
lines are ORed and go to the DMA controller DRQ
line and the DACK line from the DMA controller is
connected to DACKO and DACKI of the 82588. The
82588 is configured, for multiple buffer reception
(chaining), although the entire frame is received in a
single buffer. Let us assume that channel CH-O is used
as the first channel for reception. After the ENAble
RECeive command, CH-O is dedicated to reception. As
long as no frame is received, the other channel, CH-l,
can be used for executing any commands like transmit,
multicast address, dump, etc., by programming the
DMA channel for the execution command. The status
register should be checked for any ongoing reception,
to avoid issuing an execution command when reception
is active.

OROO
ORal
OACKO
OACKl
82588

OROn

-,

occurs immediately after an address match is established, as shown in Figure 7-56. After this, the received
bytes start filling up the on-chip FIFO. The 82588 activates the DRQ line after IS-FIFO LIMIT + 3 bytes
are ready for transfer in the FIFO (about 80 microseconds after the interrupt). The CPU should react to the
interrupt within 80 fJ-s and disable the DMA controller.
It should also issue an ASSIGN ALTERNATE BUFFER ,command with INTACK to abort any execution
command that may be active. The FIFO fills up in
about 160 fJ-s after interrupt. To prevent an underrun,
the CPU must reprogram the DMA controller for
frame reception and re-enable the DMA controller
within 160 fJ-s after the interrupt (time to receive about
21 bytes). No buffer switching actually takes place, although the 82588 generates request for alternate buffer
every time in has no additional buffer. The CPU must
respond to these interrupts with an ASSIGN ALTERNATE BUFFER command with INTACK. To keep
the CPU overhead to a minimum, the buffer size must
be configured to the maximum value of 1 kbyte.
If a frame transmission starts deferring due to the re-

ception occurring just prior to an issued transmit command, the transmission can start once the link is free
after reception. A maximum of 19 bytes are transmitted
(stored in the FIFO and internal registers) followed by
a jam pattern and then an execution' aborted interrupt
occurs. The aborted frame can be transmitted again.
If the transmit command is issued and the 82588 starts

OACKn

transmitting just prior to receiving a frame then transmit wins over receive-but this will obviously lead to Ii
collision.

OMA
CONTROLLER
231422-49

Note that the interrupt for additional buffer is used to
abort an ongoing execution command and to program
the DMA channel for reception just when a frame is
received. This scheme imposes real time interrupt handling requirements on the CPU and is recommended
only when a second DMA channel is not available.

Figure 7-55. 82588 Using One DMA Channel

7-59

inter

AP-236

REQUEST
ALT Burr
INTERRUPT

82588

82;;;

ASSIGN
ALT Burr
WITH INTACK

1
---.J

1

~---_~80 ----'1
p.S

:----------i.!,----,------

'14
0

1

ADDRESS MATCH
ON rRAME
RECEPTION

1

DMA CONTROLLER
MUST BE DISABLED
PRIOR TO THIS

r

rlro rULL

"'160/:'S--,---------+l.1

1

DMA CONTROLLER
MUST BE PROGRAMMED
rOR RECEPTION AND
ENABLED PRIOR TO THIS
231422-50

Figure 7·56. Timing at the Beginning of Frame Reception for Single DMA Channel Operation

7-60

Local Area Networks
Data Sheets

8

inter

82501 ETHERNET SERIAL INTERFACE
Driving/Receiving IEEE 802.3
• Transceiver
Cable
Fail-Safe Defeatable Watchdog Timer
• Circuit
to Prevent Continuous

Compatible with IEEE 802.3, Ethernet
• and
Cheapernet Specifications
10-Mbps Operation
• Replaces
12 MSI Components
• Manchester8 toEncoding/Decoding
and
• Receive Clock Recovery
• 10-MHz Transmit Clock Generator

•
•

Transmissions
Diagnostic Loopback for Fault
Detection and Isolation
Direct Interface to the 82586 LAN
Coprocessor

The 82501 Ethernet Serial Interface (Esl) chip is designed to work directly with the 82586 LAN Coprocessor in
IEEE 802.3/Ethernet and non-Ethernet 10·Mbps local·area netWork applications. The major functions of the
82501 are to generate the 10 MHz transmit clock for the 82586, perform Manchester encoding/decoding of
the transmitted/received frames, arid provide the electrical interface to the Ethernet transceiver cable. Diagnostic loopback control enables the 82501 to route the signal to be transmitted from the 82586 through its
Manchester encoding and decoding Circuitry and back to the 82586. The combined loop back capabilities of
the 82586 arid 82501 result in efficient fault detection and isolation by providing sequential testing of the
communications interface. An on-chip fail-safe watchdog timer circuit (defeatable) prevents the station from
locking up in a continuous transmit mode..

.....
".FACE

!NT

GND

J

I

TRANSCEIVER CABLE

INTERFACE

,,
,,
\

XCVRCABLE
INTERFACE I
NOISE FILTER

COLLISION·
PRESENCE

GENERATION

I

--

---

,CLSN

,
,,

/
VCC

CARRIER-PRESENCE GENERATION

MANCHESTER
DECODER AND
CLOCK
RECOVERY

..D

~-l

TRMT
LPBK/WDTD

1

/"'-"',

,,
,

XCVRCABLE
INTERFACE AND
NOISE FILTER

,,RCV

3

TXC

RCV
CRS

' .... _../

TRMT
TXD

RCV

6

TEN
Xl

X2
RXD
CLQCIC
GENERATION

.,. 2 COUNTER

TXD

---- f--

MANCHESTER

ENCODER

r---

~.

CLSr~

GND

~ .3i..

C.YSTAl.

X,

231353-2

, ,-, ,,TRMY

TRANSCEIVER
CABLE DRIVER

\,

,

Figure 2. Pin Configuration

I

,--

;'

WATCHDOG TIMER

I

~IWDTD

231353-1

Figure 1.82501 Functional Block Diagram

Intel Corporation assumes no responsibility for the use of any circuitry other than.circuitry embodied in an Intel product. No other circuit patent
licenses are Implied. Information contained herein supersedes previously published specifications on these devices from Intel.
October 1985
@ Intel Corporation. 1985
Order Number: 231353-003

8-1

inter

82501"

Table 1. Pin Description
Pin
No.

Type

16

0

TEN

15

I

TXD

17

I

RXC

8

0

CRS

6

0

Symbol

TXC

\

,
RXD

9

0

COT

7

0

LPBK/WDTD

3

I

Name and Function
TRANSMIT CLOCK: A 1O-MHz clock output with 5

ns

rise and fall
times. This clock is connected directly to the TXCinput of the 82586
for serial transmission.
TRANSMIT ENABLE: An active low, TTL or 0-12V level signal
synchronous to TXC that enables data transmission to the
transceiver cable. If TTL level signal is used, the differential voltage
on the TRMTITRMT output pair at the end of the frame is slowly
reduced to zero volts per the IEEE 802.3 specification. If a 0-12V
level Signal is used, the differential voltage is kept at a logic" 1" for
the entire idle time as specified in Ethernet Rev. 1.0.
TRANSMIT DATA: A TTL-level input signal that is directly .
connected to the serial data output, TXD, of the 82586.·
RECEIVE CLOCK: Clock output with 5ns rise and fall times and
50% duty cycle. This output is connE;lcted to the 82586 receive
clock input RXC. There is a maximum 1.4 ,...s discontinuity at thlil
beginning of a frame reception when the phase-locked loop
switches from the on-chip oscillator to the incoming data. During
idle (no incoming frames) the clock frequency will be half that of the
20 MHz crystal frequency.
CARRIER SENSE: A TTL-level, active low output to notify the
82586 that there is activity on the coaxial cable. This signal is
asserted when valid data or a collision signal from the transceiver is
present. It is deasserted at the end of a frame synchronous with
RXC, or when the end of the collision-presence signal (CLSN and
CLSN is detected, whichever occurs later. CRS connects directly to
the CRS input of the 82586.
RECEIVE DATA: A TTL-level output tied directly to the RXD input
of the 82586 controller and sampled by the 82586 at the negative
. edge of RXC. The bit stream received from the transceiver cable is
Manchester decoded prior to being transferred to the controller.
This output remains high during idle.
COLLISION DETECT: A TTL, active low signal which drives the
COT input of the 82586 controller. It is asserted as long as there is
activity on the collision-presence pair (CLSN and CLSN), and during
SQE test in loopback.
LOOPBACK: A TTL-level control signal to enable the loopback
mode. In this mode, serial data on the TXD input is routed through
the 82501 internal circuits and back to the RXD output without
driving the TRMTITRMToutput pair to the t~ansceiver cable. When
LPBK is asserted, the collision circuit will also be turned on at the
end of each transmission to simulate the collision test. The on-chip
watch-dog timer can be disabled by applying a 12V level through a
4 kG resistor to this pin. LPBK must not be asserted at power up to
ensure proper COT and CRS signals to 82586 at start of operation.

8-2

82501

Table 1. Pin Description (Continued)
Pin
No.

Type

Name and Function

TRMT

19

0

TRMT

18

0

TRANSMIT PAIR: A differential output driver pair that drives the
transmit pair of the transceiver cable. The output stream is
Manchester encoded. If TTL levels are applied to the TEN input, the
differential voltage at the end of a frame is slowly reduced to zero
volts. If 0-12V is applied to the TEN input, a logic '1' remains on the
transmit pair for the entire idle time.

RCV

4

I

RCV

5

I

CLSN

12

I

CLSN

11

I

C1
C2

1.
2

I
I

PLL CAPACITOR: Phase-locked-loop capacitor inputs.

X1
X2

14
13

I
I

CLOCK CRYSTAL: 20-MHz crystal inputs.

Vee
GND

20

POWER: 5 ± 10% volts.

10

GROUND: Reference.

Symbol

RECEIVE PAIR: A differentially driven input pair which is tied to the
receive pair of the Ethernet transceiver cable. The first transition on
RCV will be negative-going to indicate the beginning of a frame. The
last transition should be positive-going, indicating the end of frame.
The received bit stream is assumed to be Manchester encoded.
COLLISION PAIR: A differentially driven input pair tied to the
collision-presence pair of the Ethernet transceiver cable. The
collision-presence signal is a 10 MHz ± 15% square wave. The first
transition at CLSN is negative-going to indicate the beginning of the
signal; the last transition is positive-going to indicate the end of the
signal.

For best operation, the total crystal load capacitance
should be about 20 pF. ConSidering the internal capacitance of the 82501 and board capacitance, a
typical configuration would have a 30-35 pF capacitor connected between the X1 and X2 input and
ground. These capacitors will add up in series to
provide 15-17.5 pF. Stray capacitance of the board
will bring the total series capacitance to 20 pF. The
total length of the line on each side of the crystal
(between X1 or X2, the crystal, and the capacitor)
should be less than one inch.

FUNCTIONAL DESCRIPTION
Clock Generation
A 20 MHz parallel resonant crystal is used to control
the clock generation oscillator, which provides the
basic 20 MHz clock source. An internal divide-bytwo counter generates the 10 MHz ± 0.01 % clock
required by the IEEE 802.3 specification.
It is recommended that a crystal meeting the following specifications be used:
• Quartz crystal
• 20.00 MHz ± 0.002%

@

An external 20 MHz TTL-level clock may be applied
to pin X2, while grounding pin X1.

25·C

• Accuracy ±0.005% over full operating temperature 0-70·C

Manchester Encoder and
Transceiver Cable Driver

• Antiresonant with 20 pF load fundamental mode

The 20 MHZ clock is used to Manchester encode
data on the TXD input line. The clock is also divided
by 2 to produce the 10 MHz clock required by the
82586 for synchronizing its RTS and TXD signals.
See Figure 3. (Note that the 82586 RTS is tied to the
82501 TEN input as shown in Figure 4.)

Several vendors have these crystals available either
off the shelf or custom made. Two possible vendors
are:
1) Crystek Corporation
1000 Crystal Drive
Ft. Myers, Florida 33907
2) M-tron Industries, Inc.
Yankton, South Dakota 57078
8-3

82501

Data encoding and transmission begins with TEN
going low. Since the first bit is a '1', the first transition on the transmit output TRMT is always negative. Transmission ends with the TEN going high.
The last transition is always positive at TRMT and
may occur at the center of the bit cell (last bit = 1)
.or at the boundary of the bit cell (last bit = 0). A
one-bit delay is introduced by the 82501 between its
TXD input and TRMT/TRMT output as shown in Figure 3. If the signal supplied to the TEN pin is TTllevel, the TRMT output is slowly brought to its high
state 200 ns after the last transmit data transition.
The TRMT/TRMT differential voltage will become
less than 40 mV within 8 ,...S after the last data transition. The undershoot for return to idle is less than
100 mV differentially. This mode of operation is compatible with the IEEE 802.3 transceiver and eliminates DC currents in the primary winding o! the
transceiver coupling transformer. See Figure 4.

To protect against overheating if the cable is shorted, an isolation transformer can be used to isolate
the TRMT and TRMT outputs. When an isolation
transformer is used, transmit circuit inductance (including the IEEE 802.3 tranceiver transformers)
should be 19 microhenrys minimum.

Receive Seption
CABLE INTERFACE AND NOISE FILTER
The 82501 input circuits can be driven directly from
the Ethernet transceiver cable receive pair. In this
case the cable is terminated with a 78n resistor for
proper impedance matching. The 82501 has internal
resistors that establish the common mode voltage.
See Figure 4.

If a 0-12V digital signal is applied to the TEN input,
the TRMT output will not become high after a frame
is transmitted, but rather remain low. As a result,
there will be a positive differential voltage for the
entire idle time. This mode of operation is compatible to the Ethernet V1.0. A 0-12V TEN signal can
be generated by an open-collector level shifter with
.
a 4K pull-up to + 12V. See Figure 5.
Immediately after the end of a transmission, all signals on the receive pair are inhibited for 5 ,...S minimum, 7 ,...S maximum. This dead time is required to
block-off spurious transitions which may occur on
the coaxial cable at the end of a transmission and
are not filtered out by the transceiver.

The signal received on the RCV/RCV pair from the
transceiver defines both the RXC and RXD outputs
to the 82586. The RXC signal generated will have a
frequ~ equal to that of the Signal on the
RCV /RCV pair. The jitter with respect to the cycle
time of RXC will be less than ± 5 ns.
The input circuits can also be driven with ECl voltage levels. In either case, the input common mode
voltage must be in the range of O-Vee volts to allow
for wide driver supply variation at the transceiver.
The input termihals have a 16V maximum protection
and additional clamping of low-energy, high-voltage
noise signals.
A noise filter is provided at the RCv/RCV input pair
to prevent spurious signals .from improperly triggering the receiver circuitry. The noise filter has the following characteristics:

An internal watchdog timer is started at the beginning of the frame. The duration of the watchdog timer is 25 ms ± 15%. If the transmission terminates
(by deasserting the TEN) before the timer expires,
the timer is resef(and ready for the next transmission). If the timer expires before the transmission
ends, the frame is flborted. This is accomplished by
disabling the outputtiver for the TRMT/TRMT pair
and deasserting CR . RXD and RXC are not affected. The watchdog timer is reset only when the TEN
is deasserted.

A negative puls~ which is narrower than 5 ns or is
less than - ~ 50 mV in amplitude is rejected during
idle.
At the beginning of a reception, the filter is turned off
by the first negative pulse which is more negative
than -275 mV and is wider than 30 ns.
As soon as the first valid negative pulse is recognized by the noise filter, the data threshold is lowered to 160 niV. The CRS Signal is asserted to inform the 82586 controller of the beginning of a reception, and the RXC will be held low for 1.4.,...s
maximum while the internal phase-locked-loop is acquiring lock.

The cable driver is a differential gate requiring external resistors or a current sink of 20 mA (on both
terminals). In addition, high-voltage protection of
+ 16V maximum and short circuit to ground is provided.

8-4

82501

The frame is ended if no negative transition occurs
within 160 ns from the last positive transition.

The common mode voltage and external termination
are identical to the RCVIRCV input. (See Figure 4.)
The CLSN/CLSN input also has a 16V maximum
protection and additional clamping against low-energy, high-voltage noise Signals.

No inhibit time for CRS is provided after the end of a
frame reception. If there is a negative pulse which is
more negative than - 275 mV and is wider than 30
ns, or an equivalent sized undershoot from the
transceiver, then CRS will be reactivated.

A valid collision-presence signal will assert the
82501 COT output which can be directly tied to the
COT input of the 82586 controller.

MANCHESTER DECODER AND
CLOCK RECOVERY

During the time that valid collision-presence transitions are present on the CLSN/CLSN input, invalid
data transitions will be present on the receive data
pair due to the superposition of signals from two or
~ore stations transmitting simultaneously. It is posSible for RCV /RCV to lose transitions for a few bit
tim.es due to perfect cancellation of the signals,
which may cause the 82501 to abort the reception.
In any case, the invalid data will not cause any discontinuity of RXC.

The filtered data enters the clock recovery and decoder circuits. An analog phase-locked-loop (PLL)
technique is used to extract the received clock from
. the data, beginning from the third negative transition
of the incoming data. The PLL will acquire lock within the first 14 bit times, as seen from the RCV IRCV
inputs. During that period of time, the RXC is held
low. Bit cell timing distortion which can be tolerated
in the incoming signal is ± 15 ns for the preamble
and ± 18 ns for data. This distortion must have less
than ± 5 ns bias distortion. The voltage-controlled
oscillator (VCO) of the PLL corrects its frequency to
match the incoming signal transitions.

When a valid collision-presence signal is present the
CRS signal is asserted (along with COT). However,
if this collision-presence signal arrives within 6.0
± 1.0 J.los from the last transmission only COT is generated, so that the 82586 recognizes the active COT
as a valid SQE (heartbeat) test signal.

Its VCO cycle time stays within 5% of the RXD bit
cell time regardless of the time distortion allowed at
the RCVIRCV input. The RCVIRCV input is decoded from Manchester of NRZ and transferred synchronously with the receive clock to the 82586 controller.

Internal Loopback

At the end of a .frame, the receive clock is used to
detect the absence of RCVIRCV transitions and report it to the 82586 by deasserting CRS while RXD is
held high.

Collision-Presence Section
The CLSN/CLSN input signal is a 10 MHz ± 15%
square wave generated by the transceiver whenever
two or more data frames are superimposed on the
coaxial cable. The maximum asymmetry is the
C.LSN/CLSN signal is 60/40% for low-to-high or
hlgh-to-Iow levels. The signal is filtered for noise rejection in the same manner as RCVIRCV. The noise
filter rejects signals which are less negative than
-150 mV and narrower than 5 ns during idle. It turns
on at the first negative pulse which is more negative
than - 275 mV and wider than 30 ns. After the initial .
turn-on, the filter remains active indicating that a valid collision signal is present, as long as the negative
CLSN/CLSN signal pulses are more negative than
-275 mY. The filter returns to the "off" state if the
signal be.comes less negative than -150 mY, or if
no negative transition occurs within 160 ns from the
last positive transition. Immediately after turn-off, the
collision filter is ready to be reactivated.
8-5

When asserted, LPBK causes the 82501 to route
serial data from its TXD input, through its transmit
logic (retiming and Manchester encoding), returning
it through the receive logic (Manchester decoding
and receive clock generation) to RXD output. The
internal routing prevents the data from passing
through the output drivers and onto the transmit output pair, TRMTITRMT. When in loopback mode, all
of the transmit and receive circuits, including the
noise filter, are tested except for the transceiver cable output driver and input receivers. Also, at the end
of each frame transmitted in loopback mode, the
82501 generates the SQE test (heartbeat) signal
within 1 J.los after the end of the frame. Thus, the
collision circuits, including the noise filter, are also
tested in loop back mode.
The watchdog timer remains enabled in loopback
mode, terminating test frames that exceed its timeout period. The watchdog can be inhibited by connecting LPBK to a 4K resistor connected to 12V
± 3V. The loopback feature can still be used to test
the integrity of the 82501 by using the circuit shown
in Figure 6.

inter

82501

The 82501 operates as a full duplex device, being
able to transmit and receive simultaneously. Combining the internal and external loop back modes of
the 82586 and the internal loopback and normal
modes of the 82501, incremental testing of an
82586/82501-based interface can be performed under program control for systematic fault detection
and fault isolation. LPBK must not be asserted at
power up to ensure proper initialization of the COT
and CRS signals.

Interface Example
The 82501 is designed to work directly with the
82586 controller in IEEE 802.3 10 Mbps as well as
other 10 Mbps LAN applications. The control and
data signals connect directly between the two devices without the need for additional external logic. The
complete 82586/82501/Ethernet Transceiver ca"
ble/82C502 interface is shown in Figure 4. The
82501 provides the driver and receivers needed to
directly connect to the transceiver cable, requiring
only terminating resistors on each input signal pair.

2DMHz INTERNAL CLOCK

(MANCHESTER-ENCODED DATA)

231353-3

Figure 3. Start of Transmission and Manchester Encoding

8-6

l
w,1I-.- - - - - ,

TRANSCEIVER CABLE SHIELD
POWER PAIR

c·
c""

...CD

:~

+5V OV

~

11.4.0.

H I~~~LJ

CII

'"en

CII

en
.....
CII

TXC
RTS
TXD

'"en
....

0
......

CTS

DJ
::s
ex>
I

-s

RxC
CRS
RxD
COT

C/l

n

CD

<

...

161 ___.1,;1,;

26
28
27
29

C1

C1

-;v
31
25
30

-·::-____

2
8
6
9
7

son
ETHERNET
COAX

119

TRMT 118

C2
RxC
CRS
RxD
COT

DD

,

CXTD

~

I
CCI

'"en

15

o....

CD

0

III

0-

iii
.....
CII

82586
CONTROLLER

82501
ESI

'"en

0

82C502
ETC

NC

0

'"
S"

--...
n

CD

[,

HBD

CD

I II

12

CXRD

11

R1

LOOP BACK _ _ _ _ _ _...J
INPUT FROM PROCESSOR
("HI" UPON POWER UP)

C2~

i[""'

~

243n
0.5%

2EJ

IiiiiI
F

231353-4

NOTE:

Cl = 0.022,...F ±10%
C2 = C3 = 30-35 pF

~
~

~

2:eJ
~

82501

+12V

82501
TRANSMIT

TTL-LEVEL _
RTS

~

15

V

+12V

19P~R
TRMT
X
TRMT

4k4
TEN

TEN

18 \J

OV

I

---,---

'-->oooc-.-:::::x:

TRMT
TRMT ,,--

OPEN - COLLECTOR
SIGNAL LEVEL
CONVERTER

-.-

231353-7
231353-6

Figure 5. Optional Decoupllng of TRMTITRMT pair

12V
82501

LPBK/WDTD

WDTD

LPBK

WDTD

1

X

LPBKmode

0

0

Normal mode

0

·1

Normal mode with
watchdow timer disabled

• ::: Open Colleclor

231353-8

Figure 6. Watchdog Timer Disable

8-8

Function·

82501

• Notice: Stresses above those listed under "Absolute Maximum Ratings'~ may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*
Ambient Tempertaure Under Bias .... O°C to + 70°C
Storage Temperature .......... - 65°C to + 150°C
All Output and Supply Voltages ..... -0.5V to + 7V
All Input Voltages ................ -1.0V to + 5.5V
Power Dissipation .......................... 1.5W

NOTICE Specifications contained within the
following tables are subject to change.
D.C. CHARACTERISTICS (TA = 0-70°C , Vee = 5V +10%)
Symbol

Parameter

VIL

Input Low Voltage (TTL)

Min
-0.5

VIH

Input High Voltage (TTL)

2.0

VIDF

Input Differential Voltage

±300

VeM

Input Common Mode Voltage

0

Max

Units

+0.8

V

Conditions

Vee +0.5
±1500

mV

RCV and CLSN

V
V

RCVand CLSN

VOL1

Output Low Voltage TTL

Vee
0.45

V

IOL

VOL2

Output Low Voltage TXC, RXC

0.45

V

VoeM

Common Mode Output

4.5

V

IOL = 2mA
RL = 78n. Differential
Termination and 120n.
Pulldown (TRMD

VOH1

Output High Voltage TTL

2.4

V

VOH2

Output High Voltage TXC

3.3

V

VOH3

Output High Voltage RXC

3.0

VODF

Differential Output Swing

0.6

1.0

V
1.1

V

=

2 mA

= -1.0mA
= -400,...A
IOH = -400,...A
RL = 78n. Differential
IOH
IOH

Termination and 120n.
Pulldown (TRMT)
III

Input Leakage Current (TTL)

CIN

Input Capacitance

COUT

Output Capacitance

,...A
pF

VIN = Vee
f = 1 MHz

20

pF

f

250

mA

120n. Pulldowns

+200
10

Icc

=

1 MHz

Input Current (TTL)
-500
VF = 0.45V
IF
,...A
NOTE:
All specifications are preliminary values and are subject to change without notice. Contact your local Intel Sales Office for
the latest specifications.

c) Differential inputs outputs:
The 50% points of the total swing are used for
delay measurements. The rise and fall times of
outputs are measured at the 20 to 80% points.
The differential voltage swing at the inputs is
at least ± 275 mV with rise and fall times of
3-15 ns measured at ±0.2 volts. Once the
squelch threshold has been exceeded the inputs will detect less than ± 160 mV signals.
III) The AC loads for the various kind of outputs are
as follows:
a) TTL and MOS: a 20 pF Capacitance to GND
including test fixture and probe.
b) Differential: A 10 pF Capacitance from each
terminal to GND and a termination load resistor of 78n. in parallel with a 27 micro-henries
inductor between the two terminals.

A.C. CHARACTERISTICS
A.C. Measurement Conditions
I) TA = O°Cto + 70°C, vee = 5V ±10%
II) The AC measurements are done at the following
voltage levels for the various kinds of inputs and
outputs
a) TTL inputs and outputs: O.8V and 2.0V
The input voltage swing is at least 0.4 to 2.4V
with 3-10 ns rise and fall times.
b) Clock outputs: The rise and fall times are measured between 0.9V and 3.0V points. The high
time is measured between 3.0V points and the
. low time is measured between 0.6V points.
8-9

intJ

82501

TRANSMIT TIMING
Symbol

Parameter

Min

Max

Unit

99.99

100.01

ns

t1

TXC Cycle Time

t2

TXC Fall Time

5

ns

5

ns

t3

TXC Rise Time

t4

TXC Low Time (at 0.9V)

t5

TXC High Time (at 3.0V)

t6

Transmit Enable/Disable to TXC Low

45

ns

t7

TXD Stable to TXC Low

45

ns

,

40

ns

40

ns

t8

Bit Cell Center to Bit Cell Center of Transmit Pair Data

99.5

100.5

ns

t9

Transmit Pair Data Fall Time(1)

1.0

5.0

ns

t10

Transmit Pair Data Rise Time(1)

1.0

5.0

ns

t11

Bit Cell Center to Bit Cell Boundary of Transmit Pair Data

49.5

50.5

ns

t12

TRMT Held Low from Last Positive Transition of
Transmit Pair Data during Idle:

200

t12A

From Last Positive Transition of Transmit Pair Differential
Output Approaches within 40 mV of Zero Volts.

r-

ns
8000

ns

13

~---+--~t---_~-+-'r_~ ~
-1 "~
k

~~-J ~________~/r---~\~~LA~S~T~B=IT~7~-----------------

I

1/0

- - - 1 , " - - - - - - - <.. 1

TRMT,
TRMT (LAST BIT

=

1)

231353-5

NOTE:

1. Measured per 802.3 Para 6.5.1.1
8-10

82501

RECEIVE TIMING
Symbol
t13

Parameter

Min

Receive Pair Signal Pulse Width (at -0.275V) Differential Signal) of First
Negative Pulse for
a) Signal Rejection by Noise Filter,
b) Noise Filter Turn-On in Order to Begin Reception

30

t14

Duration which the RXC Is Held at Low State

t15

Receive Pair Signal Rise/Fall Time at ± 0.2 Volt

t16(1)

t17(1)

Unit

5

ns
ns

1400

ns

20

ns

Receive Pair Bit Cell Center from Crossover Timing Distortion:
In Preamble
In Data

±15
±18

ns
ns

Receive Pair Bit Cell Boundary Allowing for Timing Distortion:
In Data

±18

ns

8

/ks

t1B

Receive Idle Time Before the Next Reception Can Begin in a Transmitting
Station (as Measured from the Deassertion of CRS)

t19

Receive Pair Signal Return to Zero Level from Last Valid
Positive Transition

t20

CRS Assertion Delay from the First Received Valid Negative Transition
of Receive Pair Signal

Symbol
t21

Max

Parameter

160

Min

CRS Deassertion Delay from the Last Valid Positive Transition Received
(when No Collision-Presence Signal Exists on the Transceiver Cable)

ns
100

ns

Max

Unit

300(2)

ns

5.0

ns

t25

RXC Rise/Fall Time

t26

RXC Low Time (at 0.9V)

40

t26A

RXC High Time (at 2.7V)

36

ns

t27

Receive Data Stable before the Negative Edge of RXC

30

ns

ns

t2B

Receive Data Held Valid past the Negative Edge of RXC

30

ns

t29

Carrier Sense Inactive Setup Time to RXC High

60

ns

t29A

Carrier Sense Active Hold Time from RXC High

10

tao

Receive Data Rise/Fall Time

ta1

From the Time CRS Is Deasserted until the Time it can
be Asserted Again for a Transmitting Station

5

ns
10

ns

7

/ks

NOTES:

1. ± 5 ns of bias distortion-the remainder is random distortion.
2. CRS is deasserted synchronously with the RXC. This condition is not specified in the IEEE 802.3 specification.

8-11

intJ

82501

RECEIVE TIMING: START OF FRAME

I

I

I

I

0

~ 139f.:rf.=><

I

I

I

I

·::rf x~

+

~t'6

~h7

1,.-----...1

RXD

231353-9

'This clock pulse may not be a valid clock pulse.

RECEIVE TIMING: END OF FRAME

:~(LASTBIT = 01

+

-

+

-

+
==>QO<;><___
-!:,~:___~
I'
1,·----1
I
I
0

RCV (LAST BIT = 11
RCV

J4-1-- - - - ' - - - I , .

:::x:::=x
:~
r-I"~ .
,r-I21~
I,-------~~----~,--------­

'------

1-----'-13,----<·--11

o
RXD

""""'\.

___
L~~1~~~-----_ .!. . - /
231353-10

'NOTE:
,
CAS can be triggered on again by the collision-presence signal.

8-12

intJ

82501

COLLISION TIMING
Symbol

Parameter

Min

ta2

CLSN/CLSN Signal Pulse Width (at -0.30V Differential Signal) of First
Negative Pulse for Noise Filter Turn-On

30

taa

CLSN/CLSN Cycle Time

86

ta4

CLSN/CLSN Rise/Fall Time at ± 0.2 Volts

ta5

CLSN/CLSN Transition Time

ta6

Max

Unit
ns

118

ns

15

ns

70

ns

CDT Assertion from the First Vallid Negative Edge of Collision Pair Signal

75

ns

ta7

CDT Deassertion from the Last Positive Edge of CLSN/CLSN Signal

200

ns

ta8

CRS Deassertion from the Last Positive Edge of CLSN/CLSN Signal (If no
post-collision signal remains on the receive pair.)

450

ns

35

ta9

CRS Inactive after Collision Setup Time to RXC High

60

ns

ta9A

CRS Active Hold Time from RXC High after Collision

10

ns

~
~ ~133
~

! on this pin
disables the heartbeat circuitry as well as the 6.4 p.s transmit
inhibit timer but keeps the collision circuit enabled for use in
repeater applications.

REXT

1

EXTERNAL RESISTOR: A 243n 0.5% resistor is attached
between REXT and ground (Vss) to provide precision internal
current levels.

.-

Name and Function
TRANSMIT DATA PAIR: A differentially driven input tied to
the transmit pair of the transceiver cable. The transmit pair of
the transceiver cable is driven with 10 Mbps Manchester
encoded data from the serial interface of the data link
(82501). TRMT ITRMT must be isolated from the transceiver
cable by a pulse transformer. The last transition is expected to
be positive indicating end of packet.

NC

13

No connection.

Vcc'

16

POWER: 5

Vss'

8
14

GROUND

Voo'
AVcc'
AVss'

10

9

± 10% volts.

POWER/COAX SHIELD: 10 ± 10% volts.
ANALOG POWER: 5 ± 10% volts. Included to reduce the
effects of the current fluctuations in the Vcc pin.
ANALOG GROUND: Included to reduce the effects of current
fluctuations in the Vss pin.

°NOTE:
.The shield of the coaxial cable of the Ethernet channel (Voo) is connected to earth ground. To simplify annotation, all
voltages are referenced to Vss in this data sheet.

8-16

inter

82502

At the start of a frame transmission two bits maximum of preamble will be received from the TRMT
pair and may not be transmitted onto the coaxial
cable. The first bit transmitted by the 82502 may
contain phase violations, however all successive bits
of the frame will be valid.

FUNCTIONAL DESCRIPTION
Transmit Section
Transmit Pair Receiver

The 82502 receives transmit data from an Ethernet
Serial Interface (ESI) on the TRMT pins and transmits it onto a 500 coax cable (the Ethernet channel). The TRMT pins are connected to the transmit
pair of a transceiver cable through a pulse transformer. The transformer provides the isolation required between the transceiver cable and the coax
cable. The DC bias for the TRMT pins is provided
internally. The 78 ±5% 0 resistor for the TRMT input termination is external to the device.

Watch Dog Timer (Anti-Jabber Function)

The 82502 will inhibit continuous transmissions onto
the coaxial cable of duration greater· than
52 ms ± 18 %. The 52 ms watch dog timer starts
timing when the TRMT squelch is turned off to receive valid transmit data on the TRMT pins. If a
frame transmission is completed within the 52 ms
time slot, the timer is reset 3.2 J.1s after the last bit of
the frame has been transmitted. If a new transmission is started within this 3.2 /Ls, the timer is not
reset. This 3.2 /Ls inhibit period is implemented so
that a short absence of transmit data will not reset
the watch dog timer.

A noise filter (squelch) is provided at the TRMT input
pair to prevent spurious noise signals received on
the pins from being transmitted onto the coaxial cable. The squelch is on during idle and rejects signals
not more negative than -160 mV and/or less than
16 ns wide. The squelch is removed if the signal on
the TRMT pins becomes more negative than
- 225 mV for 38 ns or more.

If the timer times out (Le., transmit packet duration
exceeds 52 ms ± 18%) the transmit section is disabled and the active collision signal is transmitted
out onto the collision pair until valid transmit data
received on the TRMT pair is discontinued. When
the TRMT inputs become idle, the collision signal is
turned off and a 420 ms ± 18% non-triggerable timer is started. During this 420 ms, the transmit section
is disabled. The transmit section is re-enabled after
420 ms.

Once the squelch is removed, the transmit signal
received on the device's TRMT pins measured differentially may be between ± 0.25V minimum and
± 1.2V maximum. The squelch will remain off if the
received signal is not more positive than - 225 mV
or if it is more positive for less than 111 ns. The
squelch will turn back on if the received signal is
more positive than -160 mV for more than 160 ns.
When the squelch turns back on a non-retriggerable
6.4 J.1s transmit inhibit timer is started which disables
the transmitter for a minimum of 5.5 /Ls and a maximum of 8 /Ls.

Receive Section
Coaxial Cable Receiver

The 82502's coaxial cable receive pins "Voo" and
"CXRD" are connected to the coax cable shield and
center conductor, respectively. The linear operating
voltage range of the CXRD pin is OV to -3.50V referenced to the shield (Voo) pin.

The transmit data path through the device consists
of a receiver, rise and fall time control circuitry, and
coaxial cable current driver. The maximum timing
distortion introduced by the device's transmit path is
± 2 ns per data transition edge including timing distortion casued by output rise and fall time difference.
The maximum steady state delay of the transmit
path is 50 ns.

The shunt capacitance measured between the Voo
and CXRD pins is less than 2.0 pF. The shunt resistance is greater than 1 MO. The bias current flowing
into the CXRD pin is between -1 /LA and 1 /LA.
These conditions apply in both the power off and
power on states.

Coaxial Cable Driver

A noise filter is provided at the Voo and CXRD inputs to reject noise signals during idle. Signals received on the coax whose DC component (frequency less than 1 MHz) does not drop below -120 mV
will be rejected. The noise filter will be disabled if the
signal's DC component drops below -200 mV. A

The CXTD pin transmits data onto the coaxial cable
by sinking current from the center conductor of the
coaxial cable. The output current levels are 10 mA
±30% for high level, 72 mA ±4% for low level, and
o to 24 J.1A for idle; where current into the device is
defined as positive current. The output resistance is
9 KO minimum.

8-17

inter

82502

maximum of 5 bits will be received from the coaxial
cable and may not be transmitted onto the RCV pair.
The first bit transmitted may contain phase violations, however all successive bits of the frame will
be valid.
The noise filter will remain off if the received signal's
AC component is not positive for more than 136 ns,
and the DC component remains below - 200 mV.
While the filter is off, the received data will be transmitted onto the RCV pair with less than 50 ns steady
state delay. The timing distortion on the RCV pair
output is less than ± 2 ns per edge for a ± 200 mV
base-to-peak 5 MHz sinusoidal input from the coaxial cable.
The noise filter will turn back on if the received signal's AC component is positive for more than
207 ns, or if the DC component exceeds -123 mV.
Receive Pair Driver

The RCV outputs are connected to the receive pair
of a transceiver cable through a pulse transformer.
The receive pair (RCV IRCV) transceiver cable driver
is a current driver. The output drive currents are as
follows:
State

RCV

RCV

logical "1"
logical "0"
Idle

OmA
34 rnA ±5%
OmA

35mA ±5%
OmA
5.25 rnA

the device to indicate one of three conditions: (1)
there are simultaneous transmission attempts by
two or more stations on the coax, (2) self test after a
transmission proving that the collision circuitry is
functional or (3) a frame transmission time exceeds
the 52 ms watch dog timer time limit. The active collision presence signals is a 10 MHz ECl level square
wave transmitted on the collision pair of the transceiver cable. The duty cycle of the square wave is
50±4%.
The collision threshold level set inside the 82502
corresponds to a DC average of -1.482 ±3% volts
on the coaxial cable. If the DC average signal level
detected on the coaxial cable is more negative than
the threshold, the on-chip oscillator transmits an active collision signal onto the collision pair. The delay
in the device from the moment it detects a collision
on the CXRD pin to the collision presence signal
transmission onto the collision pair is less than 0.9
/Ls. With a 500 meter coaxial cable, it is less than 2.9
/Ls including the propagation delay of the coaxial cable.
.
Self Test

If the HBD input is strapped low, the self test feature
of the 82502 is enabled. After each frame transmission, the device transmits a collision presence signal
(heartbeat) onto the collision presence pair to indicate that the collision circuitry is operational. The
heartbeat begins between 600 ns to 1600 ns following the last positive transition on the transmit pair.
The signal's duration is between 0.5 /Ls and 1.5 /Ls.

Between 200 ns and 325 ns after the last output
data transition on the RCVIRCV pins, the 82502 begins incrementally decreasing the RCV output current until the DC current level reaches 5.25 rnA. The
first step is 17 rnA followed by thirteen 0.9 rnA steps
spaced 408 ns ± 15 % apart.

If the HBD input is strapped high, the self test feature as well as the 6.4 /Ls transmit inhibit timer are
disabled.

The purpose of this stepping sequence is to guarantee that the RCV/RCV differential output signal
(measured with a 78 ±5% terminating resistor in
parallel with a minimum magnetizing inductance of
25 /LH) will remain high for a minimum of 200 ns
following the last output transition, will not undershoot more than 80 mV and will limit the current
stored in the inductor to 4 rnA after 80 bit times.

Figure 3 shows the schematic of an IEEE 802.3,
.Ethernet compatible transceiver based on the
82502. Power to the 82502 is supplied by an isolated DC-to-DC converter which generates + 5V
± 10% and + 10V ± 10%. (These voltage levels are
referenced to Vss; remember that VDD is connected
to earth ground.) Small signal diodes which have
very small capacitance (less than 2 pF at IJd =0)
are connected between the CXTD input pin and the
center conductor to reduce the capacitance load on
the channel. A 100n fusible resistor on the CXRD
pin is to protect the network from being brought
down in the event of a short circuit fault between the
CXRD pin and GND.

Collision Detect Section
The collision presence outputs are connected to the
collision pair of a transceiver through a pulse transformer. The collision presence outputs are used by

Design Example

8-18

inter

82502

POWER PAIR

12V--~~------~----1-~~----------------------,
ISOLATED
POWER

t-+-+-r-----,

OV--~~t_~r_---1~S:U~PP~L~Y-f_1--L-~
, ... .0.

SO.o.
ETHERNET
COAX

8
TRANS ... IT PAIR

:_I:-°-+-__
8 ·. . J~I '- ·. .L-7_8.o.~:

14

VDD~---"'-'

::

sv

82S02

IS

CXTD

ETC

RECEIVE PAIR

~ ----,.~II
:f-----+--+-.

I---. .---+.-+......~

42.0.4
CXRD ..';,;;2:..-_M

___--....
100.0.

'----L....- - - S
t :::

FUSIBLE

lj8W

SV
NC

13

COLLISION PAIR

42.0. 7

_-+...1..---1

•

3~ _

CLSN

11 ,--------,-----.- - - t
6

HBD

11

CLSN
REXT

O.243.0.
S%
231243-6

NOTES:
1. Pulse transformer inductance ~ 50 ",H, typically 75 ",H
2. Isolated power supply: Pulse Engineering Inc. part no. PE·64369

Figure 3. Typical Ethernet transceiver Implementation using the 82502

8-19

inter

82502

Applications
The 82502 is intended for use in high performance,
10 Mbps LAN applications such as IEEE 802.3 10
Base 5 (Ethernet). Ethernet requires that the 82502
transceiver chip be located in a tap box attached
directly to the coaxial cable of the network. A drop
cable up to 50 meters in length connects the tran.sceiver tap box to the data terminal equipment (DTE),
see Figure 4.

In Cheapernet applications, a.k.a. IEEE 802.3 10
Base 2, the 82502 would be located inside the DTE,
and transformer coupled to the 82501, see Figure 5.
In both applications, the IEEE specifications require
that a DC isolated power supply power the 82502.

LOTE

82501
ETHERNET
SERIAL INTERfACE

TRANSCEIVER
TAP BOX

NETWORK COAXIAL CABLE

Figure 4. IEEE 802.310 Base 5 (Ethernet) configuration supports 100 users
per segment, each segment being 500 meters long

8-20

231243-3

intJ

82502

RG-58 COAX

231243-4

Figure 5. IEEE 802.3 10 Base 2 (Cheapernet) configuration supports 30 users
per segment, each segment being 185 meters long.

8-21

inter

82502

• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for
extended periods mayaffect device reliability.

ABSOLUTE MAXIMUM RATINGS*

+ 80·C
+ 150·C
0.5V to + 15V
0.5V to + 11 V

Temperature Under Bias ......... -1 O·C to
Storage Temperature .......... - 65·C to
Voo with Respect to Vss .......... Vcc with Respect to Vss .......... -

All Inpl!t and Output Voltages
(Except CXTD and CXRD) with
Respect to Vss .................. -0.5V to

+ 11V

CXTD Output Voltage with
Respect to Vss .................. -0.5V to

+ 15V

NOTICE Specifications contained within the
following tables are subject to change.

CXRD Input Voltage with
Respect to Voo ..................... OV to -15V,
> OV if ICXRO s 200 mA
Power Dissipation .......................... 1.0W

D.C. CHARACTERiStiCS
Symbol

TA

=

0-70·C, Vcc

=

5V

+
- 10%, Voo = 10V + 10%

Limits

Parameter
Min

Typ

Units

Conditions

Max

VI OF

Transceiver Cable Input
Differential Voltage

±250

±1200

mV

Base to peak

IOLC

Output Low Current CXTD

69.1

74.9

mA

CXTD: 3.3V to 10.3V

IOHC

Output High Current CXTD

7

13

mA

IAVEC

Average Output Current CXTD
(Including the effects
of timing distortion)

37

45

mA

IIOC

Idle Output Current

0

24

p.A

VIC

Coax Receiver Operating
Voltage Range (Linear)

-3.5

0

V

VICAC

Coax Receiver A.C. Voltage

±200

IILC

Input Leakage Current CXRD

IOLT

mV

CXTD: 3.3V to 10.3V

Referenced to Voo
Base to peak

-1

1

p.A

Output Low Current
Transceiver Cable

32.3
0

35.7
0.2

mA
mA

RCVand CLSN
RCVand CLSN

IOHT

Output High Current
Transceiver Cable

0
32.3

0.2
35.7

mA
mA

RCVandCLSN
RCVandCLSN

IIOT

Output Idle Current
Transceiver Cable

5
0

5.5
0.2

mA
mA

RCVandCLSN
RCVand CLSN

Icc

Vce Supply Current

0

21

mA

100

Voo Supply Current

0

30

RI

Shunt Resistance
between Voo and CXRD

1

CI

Shunt Capacitance
between Voo and CXRD

0

mA
Mn

2

8-22

4

pF

f

=

10 MHz

inter

82502

A.C. CHARACTERISTICS
A.C. Measurement Conditions
I. TA = 0 to 70'C, vee = 5V ±10%, VDD = 10V ±10%
II. The A.C. measurements are taken at the following voltage levels for the various kinds of inputs and
outputs:
A. Differential Transceiver Cable Inputs and Outputs:
All delay and timing distortion measurements are referenced to the OV points measured differentially.
Rise and fall times are referenced to the 20% and 80% points. The differential voltage swing at the
inputs is at least ± 250 mV with rise and fall times of 0 to 10 ns.
B. Coaxial Cable Inputs and Outputs:
Delay measurements are referenced to the 50% points of the signals' total swing. VDD is used as the
voltage reference. Rise and fall times are measured at the 10% and 90% points. The differential voltage
swing at the inputs is at least ± 200 mV. The input Signal is either a trapezoidal signal with 25 ± 5 ns
rise/fall times or a sine wave.
III. The A.C. loading for various outputs is as follows:
A. Transceiver cable drive pins:
RCV, RCV, CLSN and CLSN are each loaded with 10 pF to ground and 42D to Vee. A parallel load of 25
~inimum and 78D is connected between RCV and RCV. The same load is present on CLSN and
CLSN.
B. Coaxial Cable Driver Pins:
A 25D resistor is connected between VDD and CXRD. Three small signal diodes are connected in series
between the CXRD and CXTD pins such that they conduct when the 82502 is transmitting.

TRANSMIT TIMING
Symbol

Limits

Parameter

Min

Typ

Max

Units

t1

TRMT /TRMT Input Pulse Width

44

106

ns

t2

Transmit Steady State Delay

0

50

t3

CXTD Output Pulse Width
CXTD Rise Time

t1- 4
20

t1 +4
30

ns
ns

CXTD Fall Time

20

30

ns

Last Data Transition
to CXTD Disabled

0

195

ns

t4
t5
t6

ns

- Oma
- 10ma
- 72ma

231243-7

8-23

inter

82502

RECEIVE TIMING
Symbol

Limits

Parameter

t7

CXRD Input Pulse Width

Min

Typ

18

Units

Max
132 .

ns

ta

RCVIRCV Output Pulse Width

t7+ 4

ns

te

RCVIRCV Rise Time

0

·3

5

ns

t10

RCVIRCV Fall Time

0

3

5

ns

t11

Last RCVIRCV Transition
to Start of A.C. Driver Stepping

t12

R.eceive Steady State Delay

t7- 4

200
0

ns
ns

50

,-----= ~I5V

CXRO

-

-1.av

231243-8

8-24

inter

82502

COLLISION AND HEARTBEAT TIMING
Symbol

Limits

Parameter

Min

Typ

Max

Units

t13'

Delay from Collision on CXRD
to First Negative Transition on CLSN/CLSN

0

900

ns

t14

CLSN/CLSN Cycle Time

86

117

ns

t15

CLSN/CLSN High Time

39

64

ns

t16

CLSN/CLSN Low Time

39

64

ns

t17

CLSN/CLSN Rise Time

3

ns

tIS

CLSN/CLSN Fall Time

3

ns

t19

Delay from CXRD when Signal Level
Exceeds Receive Threshold to Last
CLSN/CLSN Transition

0

1.2

ns

t20

Last CLSN/CLSN Transition to Start
of A.C. Driver Stepping

0

150

ns

t21

Last TRMTITRMT Transition to Start
of Heartbeat Packet

600

1600

ns

Heartbeat Packet Duration

500

1500

ns

t22

..

..

"MInimum Collision Signal Level with 25 ns Rise Time.

COLLISION TIMING

CXRD

~~~~~to~\ ---5- 5-COLLISION /
THRESHOLD

O.69V CLSN O.IV CLSN
-O.69V -

------,

-tI4231243-9

8-25

inter

82502

HEARTBEAT TIMING

TRMT
TRMT

) - - - - ( 5~- - -

~ t 14 ---..

O.69V CLSN O.IV CLSN
. -O.69V-

-----....1
1 - - - - - - \22 - - - - - 1 \ 2 0
231243-10

8-26

82586
LOCAL AREA NETWORK COPROCESSOR
Performs Complete CSMAlCD Data Link
• Functions
without CPU Overhead

Minimum Component Systems
• -Supports
Shared bus configuration

- High level command interface

- No TTL interface to iAPX 186 and
188 microprocessors

Established and Emerging LAN
• Supports
Standards
-

High Performance Systems
• Supports
- Bus master, with on-chip DMA

IEEE 802.3/Ethernet
IEEE 802.3/Cheapernet
IBM PC Network (2 Mbps Broadband)
1 Mbps Networks

- 4 MBytes/second bus bandwidth
- Compatible with dual port meltlory
- Back to back frame reception at
10 Mbps

Memory Management
• -On-Chip
Automatic buffer chaining saves

Diagnostics:
• -Network
Frame CRC error tally

memory
- Reclaim of buffers after receipt of bad
frames
- Save bad frames

- Frame alignment error tally
- Location of cable opens/shorts
- Collision tally
Test Diagnostics
• -SelfInternalloopback

Interfaces to 8-bit and 16-blt
• Microprocessors

- Externalloopback
- Internal register dump
- Backoff timer check

IYSfEM INTERFACE

A20
1
AlIlSI { 2

"'1
A17
A18

3
..
5

AD15
A014

•
7

Yee
A,21
A,22

(iffii

A,23

Inl

iiiiE

HOLD
HLDA

AD13 [ •

II (OTfAI

"D12 [ •

to (MR,

ADU ( 10

READY (ALE,

A010 ( 11
Yss [ 12

AD.

13

ADa

14

AD7

ADe
ADS
AD..
AD3
ADZ
AD1
ADO

m

INT
AROY/SRDY

Yee

CA
RESET
MNfiD
eLK

fiR

an
CTI

iffii
TXD

m

Vss ' - _ - ' AX.

NOTE: THE SYMBOLS IN PARENTHE&I!S

CORRESpOND TO MINIMUM MODE.

Figure 2. 82586 Pinout

Figure 1. 82586 Functional Block Diagram

* IBM is a trademark of International Business Machines Corp.
Intal Corporation Assumes No Rusponsibilty for the Use

"Inlel CORPORATION, 1982

of Any Circuitry Other Than Circuitry Embodied In an Intel Product. No Olh~r Circuit Patent Licenaea a'. Implied.
8-27

September, 1984
Order Number: 231246-003

82586
The 82586 is an intelligent, high performance Local
Area Network coprocessor, implementing the
CSMAlCD link access method (Carrier Sense Multiple Access with Collision Detection).

programmable, eriabling·the user to optimize bus
overhead for a given worst case bus latency.

the 82586 performs a iarge range of link management and channel interface functions including:
CSMAlCD link access, framing, preamble genera-.
tion and stripping, source address generation, destination address checking, CRC generation and
checking. Any data rate Lip to 10 Mb/s can be used.

The 82586 provides a rich set of diagnostic and
network management functions including: internal
. and externalloopbacks, exception condition tallies,
channel activity indicators, optimal capture of all
frames regardless of destination address, optional
capture of errored or collided frames, and time
domain reflectometryfor locating fault points in the
cable.

The 82586 features a powerful host system interface. It automatically manages memory structures
with command chaining and bidirectional data
chaining. An on-chip DMA controller manages 4
channels transparently to the user. Buffers contain~
ing errored or collided frames can be automatically
recovered. The 82586 can be configured for 8-bit or
16-bit data path, with maximum burst transfer rate of
2 or 4 Mbyte/sec, respectively. Memory address
space is 16 Mbyte maximum.

The 82586 can be used in conjunction with either
baseband or broadband networks. The controller
can be configured for maximum network efficiency
(minimum contention overhead) for any length
network operating at any data rate within the
82856's range. The controller supports address
field lengths of 0, 1; 2, 3, 4, 5, or 6 bytes. It can be
configured for either the IEEE 802.3/Ethernet or
HOLC method of frame delineation. Both 16-bit
and 32-bit CRC are supported.

The 82586 provides two independent 16 byte FIFO's,
one for receiving and one for transmitting. The
threshold for block transfer to/from memory is

The 82586 is packaged in a 48 pin DIP and fabricated in Intel's reliable HMOS II 5 volt technology.

Table 1. 82586 Pin Description
Pin No.
48,36
12,24
34

lYpe

TxD

27

0

TxC

26

I

RxD
RxC

25
23

I
I

RTS

28

'0

Symbol
VCC,VCC
VSS,VSS
RESET

I

Name and Function
System Power: +5 volt power supply.
System Ground.
RESET isan active HIGH internally synchronized signal, causing the
82586 to terminate present activity immediately. The signal must be
HIGH for at least four clock cycles. The 82586 will execute RESETwithin
ten system clock cycles starting from RESET HIGH. When RESET
returns LOW, the 82586 waits for the first CA to begin the initialization
sequence.
Transmitted Serial Data output signal. This signal is HIGH when not
transmitting.
Transmit Data Clock. This signal provides timing information to the
internal serial logic, depending upon the mode of data transfer. For NRZ
mode of operation, data is transferred to the TxD pin on the HIGH to
LOW clock transition.
Received Data input signal.
Received Data Clock. This signal provides timing information to the
internal shifting logic depending upon the mode of data transfer. For
NRZdata, the state ofthe.RxD pin is sampled on the HIGH to LOW clock
transition ..
Request To Send. signal. When LOW, notifies an external interface that
the 82586 has data to transmit. It is forced HIGH after a Reset and while
the Transmit Serial Unit is not sending data.

,

8-28

231246-003

inter

82586
Table 1. 82586 Pin Description (Cont'd.)

Symbol

~

Pin No.
29

1\'pe
I

CRS

31

I

CDT

30

I

INT

38

0

CLK

32

I

MN/MX

33

I

ADO -AD15

6-11,
13-22

1/0

A16-A18,
A20-A23

1,3-5,
45-47

0

A19/S6

2

0

HOLD

43

0

HLDA

42

I

Name and Function
Active LOW Clear To Send input enables the 82586 transmitt~o
actually send data. It is normally used as an interface handshake to RTS.
This Sig~Oing inactive stops transmission. It is internally synchronized. If TS goes inactive, mel!!!!:!9 the setup time to 'fXC negative edge,
transmission is stopped and RTS goes inactive within, at most, two
TxC cycles.
Active LOW Carrier Sense input used to notify the 82586 that there is
traffic on the serial link. It is used only if the 82586 is configured for
external Carrier Sense. When so configured, external circuitry is
required for detecting serial link traffic. It is internally synchronized. To
be accepted, the signal must stay active for at least two serial cloc/<
cycles.
Active LOW Collision Detect input is used to notify the 82586 that a
collision has occurred. It is used only if the 82586 is configured for
external Collision Detect. External circuitry is required for detecting the
collision. It is internally synchronized. To be accepted, the signal must
stay active for at least two serial clock cycles. During transmission, the
82586 is able to recognize a collision one bit time after preamble
.transmission has begun.
Active HIGH Interrupt request signal.
The system clock input from the 80186 or another symmetric clock
generator.
When HIGH, MN/MX selects RD, WR, ALE, DEN, DT/Fi (Minimum
Mode). When LOW, MN/MX selects A22, A23, READY,SO,S1 (Maximum
Mode). Note: This pin should be static during 82586 operation.
These lines form the time multiplexed memory address (t1) and
data (t2, t3, tW, t4) bus. When operating with an 8-bit bus, the high byte
will output the address during the entire cycle. ADO-AD15 are floated
after a RESET or when the bus is not acquired.
These lines constitute 7 out of 8 most significant address bits for
memory operation. They switch during t1 and stay valid during the
entire memory cycle. The lines are floated after RESET or when the
bus in not acquired. Address lines A22 and A23 are not available for
use
mode .
... in
_._ .minimum
_.
..... _During t1 it forms line 19 of the memory address. During t2 through t4 it
is used as a status indicating that this is a Master peripheral cycle, and is
HIGH. Its timing is identical to that of ADO - AD15during write operation.
HOLD is an active HIGH signal used by the 82586 to request local bus
mastership at the end of the current CPU bus transfer cycle. or at the
end of the current DMA burst transfer cycle. In normal operation,
HOLD goes inactive before HLDA. The 82586 can be forced off the
bus by HLDA going inactive. In this case, HOLD goes inactive within
four clock cycles in wor<~ mode and eight clock cycles in byte mode.
.

HLDA is an active HIGH Hold Acknowledge signal indicating that the
CPU has received the HOLD request arid that bus control has been
relinquished to the 82586. It is internally synchronized. After HOLD is
detected as LOW, the processor drives HLDA LOW. Note, CONNECTING VCC TO HLDA IS NOT ALLOWED because it will cause a
deadlock. Users wanting to give permanent bus access to the 82586
should.connect HLDA with HOLD.

8-29

231246-003

82586

Table 1. 82586 Pin Description (Cont'd.)
Symbol

PinNa.

Type

Name and Function

CA

35

I

BHE

44

0

The CA pin is a Channel Attention inputused by the CPU to initiate the
82586 execution of memory resident Command Blocks. The CA signal is
synchronized internally. The signal must be HIGH for at least one system
clock period. It is latched internally on HIGH to LOW edge and then
detected by the 82586.
The Bus High Enable signal (BHE) is used to enable data onto the most
significant half of the data bus. Its timing is identical to that of A 16-A23.
With a 16-bit bus it is LOW and with an 8-bit bus it is HIGH. Note: after
RESET, the 82586 is configured to 8-bit bus.

READY

39

I

SRDY/ARDY

37

I

40,41

0

Maximum mode only. These status pins define the type of DMA transfer
<

0

0

0

0

0

0

0

0

0

0

0

NXT RB SIZE

x IX

ADR LEN

3A
3C

3E

40

Figure 19. The DUMP Area

8-46

231246-003

82586

15 14

13 12

11

10

9

8

7

6

III I I I I I I I I lLillil

5

4

3

2

1

0
42

NXT RD ADR CLOW)

rOFIX

LA RBDADR

48

NXTRBDADR

4A

CURRBD ADR

4C

CUR RB EBC

4E

NXT FD ADA

50

CUA FD ADR

52

TEMPORARY

54

NXT T8 CNT

56

aUF ADA

58

NXT TB ADR

SA

LA TBDAOR

5C

NXT TDD ADA
EL

S

I

NXT CB ADR

X

X

X

X IX X X

X

X

X

X

X

X l2S,. 66

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

6A

0

0

0

0

0

0

0

0

0

0

0

0

0

0

6C

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

6E

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

70

I)< Dc( 1)( 1)( 1)( IX XIX X /\ /\ /\IX
X XI)' IX IX IX IX IX XIX IX X IX IX I)<.
X X Xix FIFO LIM 0 ~ 0 0 0 0 0 0

)'
0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

o.

0

0

0

0

0

0

0

0

0

0

0

0

0

CX FR

0
0

0

..

CN. .N.

1)( IX IX IX 1)(

..

:>< .., ~! L~~

Ix IX
01)<

1

0

o~
0

AU

IOL

X X ,/\ /<.

0

0

IN

O'

AU

~

ROY

_SRe:

..

/\IX

0

0

0

X

0

X

X
X

X X
0

0

0

0

0

0

0

I)<
XI)<
Xix
0

0

0

0

0

0

0

0

0

7E

0

0

0

80

RU

0

0

0

0

82

0

0

0

0

:x;x

X

Xix XI)C X
0

BUF

0
ADR

0

86
88

0

0

0

0

0

0

0

(LOW)

92

0

0

0

0

0

0

0

0

96

98

Rev DMAADR H

0

NXT-FD-ADR: Next Frame Descriptor Address.
Define N as the last Receive Frame Descriptor with
bits C=1 and 8=0, thim NXT-FD-ADR is the address
of N+2 Receive Frame Descriptor (with B=C=O) and
is equal to the LINK-ADDRESS field in N+1 Receive
Frame Descriptor.

94

ADA. H

9A

RCVOMAADR L
0

8E

90

RCVDMA BC

BR. aUF

8A

8C

BUF ADR PTR (HIGH)
PRT

CUR-RB-EBC: Current Receive Buffer Empty Byte
Count. Let N be the currently used Receive Buffer.
Then CUR-RB-EBC indicates the Empty part of the
buffer, i.e. the ACT-COUNT of buffer N is given by
the difference between its SIZE and the CURRB-EBC.

84

I)<

I)<
X
)<~ )<12<

CUR-RBD-ADR: Current Receive Buffer Descriptor
Address. Similar to LA-RBD-ADR, but points to Nth
Receive Buffer Descriptor.

7A
7C

0

,21.1':>< Xix X )<~ )<12<

;x 1)' ;x 1)'

78

0

XI:X XI)' X

)' XI)(

NXT-RBD-ADR: Next Receive Buffer Descriptor
Address. Similar to LA-RBD-ADR but points to N+1
Receive Buffer Descriptor.

74
76

'"'
sus

LA-RBD-ADR: Look Ahead Buffer Descriptor, i.e.
the pointer to N+2 Receive Buffer Descriptor.

72

,

IX: IX IX IX IX Ix IX X X IX X X IX IX IX IX
X IX I)<

CUR-RB-SIZE: The number of bytes in the last
buffer of the last received frame. EL - The EL bit of
the last buffer in the last received frame.

68

0

0

NXT-RB-ADR: Let N be the last Receive Buffer used,
then NXT-RB-ADR is the BUFFER-ADDRESS field
in the N+1 Receive-Buffer Descriptor, i.e. the pointer
to the N+1 Receive Buffer.

62

0

o Dc(

NXT-RB-SIZE: Let N be the last buffer of the last
received frame, then NXT-RB-SIZE is the number of
bytes of available in the N+1 buffer. EL- The EL bit of
the Receive Buffer Descriptor.

60

0

Dc(

Bytes 2CH to 2DH: Status bits of the last time TDR
command that was performed.

64

SCBADR

1)( IX IX IX

Bytes 24H to 2BH: HASH TABLE.

5E

VI I I ILLLlLlillLLLLl ~~~:~~~
CURCBAOR

')( X

Bytes 22H to 23H: Receive Status Register. Bits
6,7,8,10,11 and 13 assume the same meaning as
corresponding bits in the Receive Frame Descriptor
Status field.

46

CUR RB SIZE

ELIX]

Bytes 1CH to 21H: Temporary Registers.

..

NXT RB ADR (HIGH)

0

0

0

0

0

0

0

9C

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

9E

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

AO

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

o

....

A2

1

SilO'

A4

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

A6

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

A8

CUR-FD-ADR: Current Frame Descriptor Address.
Similar to next .NXT-FD-ADR but refers to N+1
Receive Frame Descriptor (with 8=1, C=O).
Bytes 54H to 55H: Temporary register.

Figure 19. DUMP Area (con't)
8-47

231246-003

82586

NXT-TB-CNT: Next Transmit Buffer Count. Let N be
the last transmitted buffer of the TRANSMIT command executed recently, the NXT-TB-CNT is the
ACT-COUNT field in the Nth Transmit Buffer
Descriptor. EOF - Corresponds to the EOF bit of the
Nth Transmit Buffer Descriptor. EOF=1 indicates
that the last buffer accessed by the 82586 during
Transmit was the last Transmit Buffer in the data
buffer chain associated with the Transmit Command.

Frame Descriptor used recently, then RU-SUSFD is equivalent to the S bit of N+1 Receive
Frame Descriptor.
Bytes 82H, 83H:

RU-SUS (Bit 4) - Receive Unit in SUSPENDED
state.
RU-NRSRC (Bit 5) - Receive Unit in NO
RESOURCES state.

BUF-ADR: Buffer Address. The BUF-PTR field in
the DUMP-STATUS Command Block.

RU-RDY (Bit 6) - Receive Unit in READY state.
RU-IDL (Bit 7) - Receive Unit in IDLE state.

NXT-TB-AD-L: Next Transmit Buffer Address Low.

RNR (Bit 12) - RNR Interrupt In Service bit.

Let N be the last Transmit Buffer in the transmit
buffer chain of the TRANSMIT Command performed
recently, then NXT-TB-AD-L are the two least significant bytes of the Nth buffer address.

CNA (Bit 13) - CNA Interrupt In Service bit.
FR (Bit 14) - FR Interrupt In Service bit.

,

CX (Bit 15) - CX Interrupt In Service bit.

LA-TBD-ADR: Look Ahead Transmit Buffer Descrip-

tor Address. LEoit N be the last Transmit Buffer in the
transmit buffer chain of the TRANSMIT Command
performed recently, then LA-TBD-ADR is the NEXTBD-ADDRESS field of the Nth Buffer Descriptor.

Bytes 90H to 93H:

NXT-TBD-ADR: Next Transmit Buffer Descriptor
Address. Similar in function to LA-TBD-ADR but
related to Transmit Buffer Descriptor N-t Actually, it
is the address of Transmit Buffer Descriptor N.

Bytes 94H to 95H:

BUF-ADR-PTR - Buffer pOinter is the absolute
address of the bytes following the DUMP
Command block.

RCV-DMA-BC - Receive DMA Byte Count. This
field contains number of bytes to be transferred
during the next Receive DMA operation. The
value depends on AT-LOCation configuration
bit.

Bytes 60H,61H: This is a copy of the 2nd word in the

DUMP-STATUS command presently executing.

1. If AT-LOCation = 0 then RCV-DMA-BC =
(2 times ADDR-LEN plus 2) if the next
Receive Frame Descriptor has already
been fetched.

NXT-CB-ADR: Next Command Block Address. The

LINK-ADDRESS field in the DUMP Command Block
presently executing. Points to the next command.
CUR-CB-ADR: Current Command Block Address.
The address of the DUMP Command Block currently
executing.

2. If AT-LOCation = 1 then it contains the size
of the next Receive Buffer.

SCB-ADR: Offset of the System Control Block

BR+BUF-PTR+96H - Sum of Base Address plus
BUF-PTR field and 96H.

(SCB).

RCV-DMA-ADR - Receive DMA absolute Address. This is the next RCV-DMA start address.
The value depends on AT-LOCation configuration bit.

Bytes 7EH, 7FH:

RU-SUS-RQ (Bit 4) - Receive Unit Suspend
Request.

1. If AT-LOCation = 0, then RCV-DMA-ADR
is the Destination Address field located in
the next Receive Frame Descriptor.

Bytes 80H, 81 H:

CU-SUS-RQ (Bit 4) - Command Unit Suspend
Request

2. If AT-LOCation = 1, then RCV-DMA-ADR
is the next Receive Data Buffer Address.

END-OF-CBL (Bit 5) - End of Command Block
List. If '1' indicates that DUMP-STATUS is the
last command in the command chain.
ABRT-IN-PROG (Bit 6) - Command Unit Abort
Request.
RU-SUS-FD (Bit 12) - Receive Unit Suspend
Frame Descriptor Bit. Assume N is the Receive

8-48

231246-003

82586

15

CMD=7

L-_________________________Ll_NK_0_F_F_SE_T~------------------------~4
Figure 20. The D!AGNOSE Command Block
The following nomenclature ha.s been used in the
DUMP table:

o

-

1

- The 82586 writes one in this location.

x

- The 82586 writes zero or one in this

The 82586 writes zero in this location.

location.

RECEIVE FRAME AREA (RFA)
The Receive Frame Area, RFA, is prepared by the
host CPU, data is placed into the RFA by the 82586
as frames are received. RFA consists of a list of
Receive Frame Descriptors (FD), each of which is
. associated with a frame. RFA-OFFSET field of SCB
points to the first FD of the chain; the last FD is
identified by the End-of-Listflag (EL). See Figure 21.

FRAME DESCRIPTOR (FD) FORMAT
III

- The 82586 copies this location from
the corresponding position in the
memory structure.

The FD includes the following fields:
STATUS word (set by the 82586):

DIAGNOSE
The DIAGNOSE Command triggers an internal self
test procedure of backoff related registers and
counters.

C

(bit 15)

B

(bit 14)

OK

(bit 13)

S11

(bit 11)

S10

(bit 10)

S9

(bit 9)

S8
S7

(bit 8)
(bit 7)

S6

(bit 6)

The DIAGNOSE command includes the following:
STATUS word (written by 82586):
C
B

(bit 15)
(bit 14)

OK

(bit 13)

FAIL

(bit 11)

- Command completed
- Busy executing
command
- Error free
completion
- Indicates that the self
test procedured failed

COMMAND word:
EL
S

(bit 15)
(bit 14)

I

(bit 13)

CMD

(bits 0-2)

- End of cOlrlmand list
- Suspend after
completion
- Interrupt after
completion
- DIAGNOSE = 7

- Completed storing
frame.
- FD was consumed by
RU.
- Frame received
successfully. If this bit is
. set, then all others will
be reset; if it is reset,
then the other bits will
indicate the nature of
the error.
- Received frame
experienced CRC error.
- Received frame
experienced an
alignment error.
- RU ran out of resources
during reception of this
frame.
- RCV-DMA overrun.
- Received frame had
fewer bits than
configured Minimum
Frame Length.
- No EOF flag detected
(only when configured
to Bitstuffing).

COMMAND word:
EL
S

LINK OFFSET: Address of next Command Block

8-49

(bit 15) .
(bit 14)

- Last FD in the list.
- RU should be
suspended after
receiving this frame.
231246·003

82586
LINK OFFSET: Address of next FD in list.

DESTINATION ADDRESS (written by 82586): Contains Destination Address of received frame. The
length in bytes. it is determined by the Address
Length configuration parameter.

RBD-OFFSET (initially prepared by the CPU and
later may be updated by 82586): Address of the first
RBO that represents the Information Field. RBD~
OFFSET =OFFFFH means there is no Information
Field.

L

SCB

r-~FAPOINTE~ f-

STATISTICS
TO

C OMMANiJ
BLOCK
LIST

I.

~
RECEIVE
FRAME
DESCRIPTORS

.-

RECEIVE FRAME AREA
RFD1

-r

STATUS

. STATUS

-U
-~

VALID
PARAMETERS

.L o I

L

RBD2
RBD1
ACT-cnt ,... 1 ACT-cnt

RECEIVE
BUFFER
DESCRIPTORS

-

RECEIVE
BUFFERS

-'--

-'--

VALID
DATA

VALID
DATA

-

BUFFER 1
1-

-

BUFFER 2

RECEIVE FRAME LIST

_

RBD4

r- o

ACT-cnt

STATUS

~"--

'---BUFFER 3

BUFFER 4

ir-

-~
EMPTY

,...

_J

r--"--

-'.,...----

I

-

r-

EMPTY

RBD3

I

. - 0 ACT-cnt

_-W

-

EMP;-~

STATUS

'---

RBDS

.

0

-r

ACT-cnt

-"--

-

BUFFERS

FREE FRAME LIST

I

Figure 21. The Receive Frame Area

8-50

231246-003

inter

82586

EVEN BYTE

C

B

0

•

ZEROS

1--+_+:~'-::::="""'~-'::::=..-J:~~_7--:!:_:::!:o--:::_::::>,,-:::_::::>,,-:::_:;::oot(STATUS)
El
LINK OFFSET

RBO-OFFSET
1ST BYTE

2ND BYTE

MC

•

,.

DESTINATION ADDRESS

NTH BYTE

12

1ST BYTE

2ND BYTE
SOURCE ADDRESS

NTH BYTE
1ST BYTE

LENGTH FIELD

2ND BYTe

,.
,.
,.
2.

Figure 22. The Frame Descriptor (FD) Format
SOURCE ADDRESS (written by 82586): Contains
Source Address of received frame. Its length is the
same as DESTINATION ADDRESS.
LENGTH FIELD (written by 82586): Contains the
2 byte Type Field of received frame.

NEXT RBD OFFSET: Address of next BD in list of
BD's.

RECEIVE BUFFER
DESCRIPTOR FORMAT

ELISIZE·

BUFFER ADDRESS: 24-bit absolute address of
buffer.

The Receive Buffer Descriptor (RBD) holds intormation about a buffer; size and location, and the means
for forming a chain of RBDs, (forward pOinter and
end-of-frame indication).
The Buffer Descriptor contains the following fields:
STATUS word (written by the 82586):
EOF

(bit 15)

F

(bit 14)

ACT
COUNT

EL
SIZE

(bit 15)
- Last BD in list.
(bits 0-13) - number of bytes the
buffer is capable of
holding.

. - Last buffer in received
frame.
- ACT COUNT field is
valid.

(bits 0-13) - Number of bytes in the
buffer that are actually
occupied.

15
EOF

ACT COUNT

o

..1---'_-'---1 (STATUS)
NEXT BD OFFSET

SUFFER ADDRESS

423
SIZE

Figure 23. The Receive Buffer Descriptor (RBD) Format
8-51

231246-003

inter

82586

ABSOLUTE MAXIMUM RATINGS·

'NOTlCE: Stresses above those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended period may affect device reliability.

AmbientTemperature Under Bias ........ O'C to 70'C
Storage Temperature ................. -6S·C to 1S0·C
Voltage on Any Pin With
Respect to Ground : ................. -1.0V to + 7V
Power Dissipation .......................... 3.0 Watts

D.C. CHARACTERISITCS
TA = 0-70°C, Vee = 5V ± 10%, CLK has MOS levels (See VMIL, VMIH, VMOL ' VMOH )' TxC and RxC have
82501 compatible levels (VMIL' VTII~,VRIH)' All other signals have TTL levels (see VIL, VIH , VOL' VOH)'
Symbol

Parameter

Mln_

Max.

Units

VIL

Input Low Voltage (TTL)

-0.5

+0.8

V

VIH

Input High Voltage (TTL)

2.0

VOL
VOH

Output Low Voltage (TTL)

Vee+0.5
0.45

V

IOL;:2.5mA

Output High Voltage (TTL)

2.4

V

low400uA

VMIL ·
VMIH

Input Low Voltage (MOS)

-0.5

0.6

V

Input High Voltage (MOS)

3.9

Vee+0.5

V

VTiL
VRIH
VMOL

Input High Voltage (TxC)

3.3

Vee+0.5

V

Input High Voltage (RxC)

3.0

V

Output Low Voltage (MOS)

Vee+0.5
0.45

VMOH

Output Hi.gh Voltage (MOS)

ILl
ILO

Input Leakage Current
Output Leakage Current

CIN

Capacitance of Input Buffer

COUT

Capacitance of Output Buffer

Icc

Power Supply Current

Test Conditions

V

V

IOL2.5mA

V

low400UA

±10

uA

a::;VIN~Vee

±10

uA

0.45~VoUT~Vee

10.

pF

FC=1MHz

20

pF

FC=1MHz

550
450

mA

TA=O°C
TA=70°C

Vee-0.5

SYSTEM INTERFACE A.C. TIMING CHARACTERISTICS
TA=0~70°

C, Vcc=5V±10% Figure 24 and Figure 25 define how the measurements should be done:

INPUT ANO OUTPUT WAVEFORMS FOR AC TESTS

24
.
. = : ) ( 1 . 5 --TESTPOINTS--1.SX=
0.4S
AC TESTING INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC 1 AND
0.4S FOR A LOGIC O. TRIMMING MEASUREMENTS ARE MADE
AT 1.SV FOR BOTH A LOGIC 1 AND 0

Figure 24. TTL Input/Output Voltage Levels For Tlrning Measurements

8-52

231246-003

82586

MOS 1/0 MEASUREMENTS ARE TAKEN AT
0.1 AND 0.9 OF THE VOLTAGE SWING

Figure 25. System Clock MOS Input Voltage Levels for Timing Measurements

INPUT TIMING REQUIREMENTS (8MHz)*
Symbol

Parameter

Min.

Max.

T1

ClK cycle period
ClK low time at 1.5V

125

2000

55
42.5
55

1000
1000

T2
T3
T4

ClK low time at 0.9V

T5

ClK high time at 1.5V
ClK high time at3.6V

T6

ClK rise time

T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21

ClKfall time

Comments

42.5
15
15

Data in setup time

20

Data in hold time

10
20

Async RDY active setup time

Note 1
Note 2

Note 3
Note 3

Async RDY inactive setup time
Async RDY hold time
Synchronous ready/active setup

35
15

Synchronous ready hold time
HlDA setup time

0
20

Note 3

HlDA hold time
Reset setup time

10
20

Note 3
Note 3
Note 3

Note 3

35

Reset hold time

10

CA pulse width

1 T1

CA setup time

20

Note 3

CA hold time

10

Note 3

8-53

231246-003

inter

82586

OUTPUT TIMINGS (8 MHz)';.
Symbol
T22
T23
T24

Parameter
DT/R valid delay
WR. DEN active delay
WR. DEN inactive delay
Int. active delay

T25
T26
T27

, Int. inactive delay
Hoid active delay

Min.
0

Max.
60

Comments

0

70

0

65

Note 8
Note 8

0

85

Not,e 4

0
0

85
85

Note 4
Note 4

T28

Hold inactive delay

0

85

Note 4

T29

Address valid delay

0

T30

Address float delay

0

T31
T32

Data valid delay
Data hold Time

0
0

55
50
55

Note 7

T33

Status active delay

T34

10
10

60
70

0
0

45

T35

Status inactive delay
ALE active delay

T36

ALE inactive delay

T37

ALE width

T2-10

T38

Address valid to ALE low

T2-30

T39

Address hold to ALE inactive

T4-10

T40
T41

RD active delay
RD inactive delay

0

95
70

RD width

T43

Address float to RD active

T44

RD inactive to Address active

10
T1-40

T45
T46

WRwidth
Data hold after WR

2T1-40
T2-25

T47

Control inactive after reset

0

NOTE liST:
1
2
3
4
5
, 6

7
8 -

0.9V to 3.6V
3.6V to 0.9V
to guarantee recognition at next clock
Cl = 50 pF
Cl = 100 pF
Affects:
MIN MODE: R5, WR. DT/R. DEN
MAX MPDE: SO. 51
High address lines (A16-A24. BHE) become valid
one clock before T1 only on first memory cycle after
the 82586 acquired the bus.
WR from falling edge of ClK
TIElif from rising edge of ClK

Note 5
Note 5
Note 5

10
2T1-50.

T42

• All units are in ns.
··Cl on all outputs is 20-200 pF unless otherwise specified.

45

60

Note 6

CLKi?~
T25

T26

INT

Figure 26. INT Output TimIng

Figure 2l CA Input Timing
8-54

231246-003

82586

ClK
T18_

.... T17

RESET

RD. ViR. DEN. DT/R.

so.Si

Figure 28. RESET Timing

READY SIGNAL
T2'~_ _---..

ClK
80186 OR
82285 OUTPUT

PClK

::5~~

1

INPUT

----~------+-~

SREADY
OR
READY
82586 INPUTS

Figure 29. ARDY and SRDY Timings Relative to ClK

H::

t

t:-------t--tr--------~~------TT2I28f1t_~~--~~--

- -T27

HLDA
BHE ADO-AD15
A16-A23 SO Si
DT/R RD WR
CPU MASTER

T16

1~~~8~2~58~6B-M~A~S~T~E~R~~::--------­
T30

Figure 30. HOlD/HlDA Timing Relative to ClK

8-55

231246-003

82586

~

T1
r--'
T1H

~

'--

vel

T4
~

§1:ISI

T2

T3

T4

rv~~~
t--B1 /

T33 '\,.

-I

!-'-in4

E!.

I;:-

T29-

A16-A18 A2Q-A23

1
A19/86

56

Al'

}- '-~

AlE

I-

T3S ....

ADO -AD15
lID

DT/R

----

/-

iitl
-I-rn -:
T36 ~

~

L

{

I

_T43

T44

T41_
T42

-

-

T23

}

1

l-

I

T40

DEN

T.

TB
DATA IN

AO-A15

T29--

tr--

l:=- 1'---

T32-

-

1--T24

T22

V
I

n

Figure 31. Read Cycle Timing.

~

VCH
tr=--

VCl

--IV7

T1,---, ~6_
'----' --IL
1

TW

I

SlISl

i"---'
j--!L-

~

I'--

/
HT34

x

IffiE: A16-A18 A20-A23

A-"-/S-6+---+-"r~-A-"-+~~--------~~S6~----~~~
-

-T31

T32 -

r,r--.I\

ALE

I--

r--

,r' - -

~~~T~35-+-~~' ~~
r-1T~36~~--------------r---+-+-~--I

~,T31

T32_

f-

~AD~O-~AD~1~5__+-~~~A~0~-A~15r-~~______DA_T_A~OU~T__-+__'-~I~~
I- I
I-no
~I--

T29-

-r3.

~

Dm=_T...;2_3=-=-=t-__.,fll.-

·T45

~T23
1

I-

_ I/T24

Figure 32. Write Cycle Timing

SERIAL INTERFACE A.C. TIMING CHARACTERISTICS
CLOCK SPECIFICATION

Applies for TxC, AXe
for NRZ:
f min =100 kHz ± 100 ppm
f max = 10 MHz ± 100 ppm
for Manchester:
f min = 500 kHz ± 100 ppm
f max '= 10 MHz ± 100 ppm

for Manchester, symmetry is needed:
T51, T52 =

8-56

~f

±5%

231246-003

inter

82586

A.C. CHARACTERISTICS
TRANSMIT AND RECEIVE TIMING PARAMETER SPECIFICATION'

ISymbol I

Parameter

Min.

Max.

Comments

100
100

1000

Notes 14, 2
Notes 14, 3

5
5
1000

Note 14
Note 14

I

TRANSMIT CLOCK PARAMETERS

T48
T48

TxC Cycle
TxC Cycle

T49
T50

TxC Rise Time
TxC Fall Time
TxC High Time @ 3.0V

40

TxC Low Time @ 0.9V

40

T51
T52

Note 14
Notes 14, 4

TRANSMIT DATA PARAMETERS

T53
T54
T55
T56
T57

TxD Rise Time

10

TxD Fall Time
TxD Transition - Transition

10
Min(T51,
T52)-7

TxC Low to TxD Valid

T58

'i'XC Low to TxD Transition
iXC High to TxD Transition

T59

TxC Low to TxD High at the Transmission end

Notes 5, 13
Notes 5,13
Notes 2,5

40
40

Notes 3, 5
Notes 2,5

40

Notes 2,5
Notes 5

40

REQUEST TO SEND/CLEAR TO SEND PARAMETERS

T60
T61

TxC Low to RTS Low. Time to Activate RTS
CTS Valid to TxC Low.CTS Set-Up Time

45

T62
T63

TxC Low to CTS Invalid. CTS Hold Time
TxC Low to RTS High. time to deactivate RTS

20

(

40

Note 6

40

Note 7
Note 6

RECEIVE CLOCK PARAMETERS

T64

Clock Cycle
Rise Time
Fall Time
High Time@ 2.7V

T65
T66
T67

RxC
RxC
RxC
RxC

T68

RxC Low Time @ 0.9V

100
5
36
40

'5
1000

Notes 15, 3
Note 15
Note 15
Note 15
Note 15

RECEIVE DATA PARAMETERS

T69

RxD Setup Time

30

T70
T71

RxD Hold Time'
RxD Rise Time

30

T72

RxD Fall Time

Note 1
Note 1
10

Note 1

10

Note 1

* All units are in ns.

8-57

231246-003

82586

TRANSMIT AND RECEIVE TIMING PARAMETER SPECIFICATION" (cont'd.)

ISymbol

Parameter

Min.

Max.

Comments

I

CARRIER SENSE/COLLISION. DETECT PARAMETERS

T74

COT Valid to TxC High Ext. Collision
Detect Setup Time
TxC High to COT Inactive. COT Hold Time.

T75

COT Low to Jamming Start

T76

CRS Valid to TxC High Ext. Carrier SenseSetupTime
TxC High to CRS Inactive. CRS Hold Time

T73

30

Note 12

20

Note 12

30

Note 12

20

CRS Low to Jamming Start

Note 12
Note 9

T79

Jamming Period

Note 10

T80

CRS Inactive Setup Time to RxC High.
End of Receive Frame

60

T81

CRS Active Hold Time From ~ High

3

T77
T78

Note 8

INTERFRAME SPACING PARAMETERS

I T82

Note 11

Inter Frame Delay

'All units are in ns.
NOTES:
1
2
3
4
5
6
7
8

-

9 -

10 11 -

"12
13
14
15

-

TTL Levels
Manchester only.
NRZ only.
Manchester requires 50% Duty Cycle.
1 TTL Load + 50 pF.
1 TTL Load + 100 pF.
Abnormal End of Transmission. CTS Expires Before RTS.
Programmable value:
T75 = NCDF x T48 + (12.5 to 23.5) x T48 if collision occurs after preamble.
NCDF-The Collision Detection Filter Configuration Value.
Programmable value:
T78 = NCSF x T 48 + (12.5 to 23.5) x T 48.
NCSF-The Carrier Sense Filter Configuration Value.
TBD is a function of Internal/External Carrier Sense Bit.
T79 = 32 x T48.
Programmable value:
T88 = NIFS x T48.
NIFS-the IFS Configuration Value.
To guarantee recognition on the next clock.
Applies to TTL Levels.
82501 Compatible levels, see Figure 34.
82501 Compatible levels, see Fig ure 35.

8-58

231246-003

82586

A.C. TIMING CHARACTERISTICS

INPUT AND OUTPUT WAVEFORMS FOR AC TESTS

2.4==><1.5 - - T E S T POINTS - - 1 . 5
0.45

>C

AC TESTING INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC 1 AND
0.45 FOR A LOGIC O. TRIMMING MEASUREMENTS ARE MADE
AT 1.5V FOR BOTH A LOGIC 1 AND 0

Figure 33. TTL Input/Output Voltage Levels for Timing Measurements

1----

T48

----+I

HIGH LEVELS MAY VARY
WITH VCC

r

'\

..l

I

\

3.3V
3.0V - -

I-

a.9V - 0.6V

Figure 34. TxC Input Voltage Levels for Timing Measurements

1 - - - - T64 - - - - I
I--~--\

~

I- ___ -l

I

3.0V
2.7V - -

0.9V - - 0.6V

HIGH LEVELS MAY VARY
WITH VCC

\

1'-_ _-'

Figure 35. RxC Input Voltage Levels for Timing Measurements

~-----r-+--r---------t1------------7.=

T56
TxD--(NRZI
TxD _ _ _

(MANCHESTERl

Figure 36. li'ansmlt and Control and Data Timing

8-59

231246-003

82586

T~
ii'i'S------

C'fS-----CDT----l-"l

- - -- -

~----I -

--h74

>e==-.r-------

(1~~)

,'---T76

'L _______..,_ ~T77

CFiS-----,

\

/

=~

T55

stfx:=~~~~--~ =~~

TXD
(MANCHESTER)

Figure 37. Transmit and Control and Data Timing· (cont.)

i-----T64-------1

-T6B-~-I

RxD

Figure 38. RxD Timing Relative to RxC

RxC---",

~--------~----+-------'

Figure 39. CRS Timing Relative to RxC

8-60

231246-003

82588
Single Chip LAN Controller
82588: High Integration Mode
82588-5: High Speed Mode
• Integrates ISO Layers 1 and 2
- CSMA/CD Data Link Controller
- On-Chip Manchester, NRZI
Encoding/Decoding
- On-Chip Logic based Collision
Detect and Carrier Sense

• User Configurable
- Up to 2 Mbps Bit rates with on-chip
Encoder/Decoder (High Integration
Mode)
- Up to 5 Mbps with External Encoder/
Decoder (High Speed Mode)

• Supports Emerging IEEE 802.3
Standards
- 2 Mbps Broadband
- 1 Mbps Baseband

•

No TTL Glue required with iAPX 186
and 188 microprocessors

•

Network Management and Diagnostics
- Short or Open Circuit localization
- Station Diagnostics (External
loopback)
- Self test Diagnostics
Internal loopback
User readable registers

• High level command interface offloads
the CPU
• Efficient memory use via Multiple
Buffer Reception

The 82588 is a highly integrated device designed for realizing cost sensitive Local Area Networks applications
such as Personal Workstations.
At data rates of up to 2 Mbps, it provides a highly integrated interface and performs: CSMAlCD Data Link
Control, Manchester, Differential Manchester or NRZI encoding/decoding, clock recovery; Carrier Sense, and
Collision Detection. This mode is called "High Integration Mode." In the 82588 "High Speed Mode", the user
can transfer data at a rate of up to 5 Mbps. In this mode the physical link functions are done external to the
82588.
The 82588 is packaged in a 28 pin DIP and fabricated in Intel's reliable HMOS II 5 volt technology.

27

vee
DACkl

26

INT

25

REseT

24

CRS/TCLK

23

COT

22

CT5

21
CSMAlCD

I r - - - - , RECEIVE

FIFO

DATA LINK

82588

21

fiTS

20

T)(O

19

RXO

,.

OROl

17

DROG

16

RXC/X2

15

TXO/X1

CONTROLLER

1--_....11

TRANSMIT
FIFO

231161-2
SYSTEM INTERFACE

DATA LINK

SERIAL INTERFACE

Figure 2. 82588 Pin
Configuration

231161-1

Figure 1.82588 Block Diagram

Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
October 1985
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intet.
© Intel Corporation. 1985
8-61
Order Number: 231161·002

82588

Table 1. Pin Description
Symbol

Pin No.

Type

D7
D6
D5
D4
D3
D2
D1
DO

6
7
8

I/O

10
11
12
13

RD

5

I

READ: Together with CS, DACKO or DACK1, Read controls
data or status transfers out of the 82588 registers.

WR

3

I

WRITE: Together with CS, DACKO or DACK1, Write
controls data or command transfers into the 82588
registers.

CS

2·

I

CHIP SELECT: When this signal is LOW, the 82588 is
selected by the CPU for transfer of command or status.
The direction of data flow is determined by the RD or WR .
inputs.

CLK

4

I

CLOCK: System clock. TTL compatible signal.

RESET

25

I

RESET: A HIGH signal on this pin will cause the 82588 to
terminate current activity. This signal is internally
synchronized and must beheld HIGH for at ieast four Clock
cycles.

INT

26

0

INTERRUPT: Active HIGH signal indicates to the CPU that
the 82588 is requesting an interrupt.

DRCO

17

0

DMA REQUEST (CHANNEL 0): This pin is used by the
82588 to request a DMA transfer. DRCO remains HIGH as
long as 82588 requires data transfers. Burst transfers are
done by having the sigl1al active for multiple transfers.

DRC1

18

0

DMA REQUEST (CHANNEL 1): This pin is used by the
82588 to request a DMA transfer. DRC1 remains HIGH as
long as 82588 requires data transfers. Burst transfers are
done by having the signal active or multiple transfers.

DACKO

1

I

DMA ACKNOWLEDGE (CHANNEL 0): When LOW, this
input signal from the DMA Controller notifies the 82588 that
the requested DMA cycle is in progress. This signal acts .
like chip select for data and parameter transfer using DMA
channelO.

DACK1

27

I

DMA ACKNOWLEDGE (CHANNEL 1): When LOW, this
input signal from the DMA controller notifies the 82588 that
the requested DMA cycle is in progress. This signal acts
like chip select for data and parameter transfer using DMA
channel 1.
,

Name and Function
DATA BUS: The Data Bus lines are bi-directional three
state lines connected to the system'sCata Bus for the
transfer of data, commands, status and parameters.

9

8-62

intJ

82588

Table 1. Pin Description (Continued)
Symbol

Pin No.

Type

Name and Function
High Integration Mode

X1/X2

15/16

I

OSCILLATOR INPUTS: These inputs may be used to
connect a quartz crystal that controls the internal clock
generator for the serial unit.
X1 may also be driven by a MOS level clock whose
frequency is 8 or 16 times the bit rate of Transmit/Receive
data. X2 must be left floating if X1 has an external MOS
clock.
High Speed Mode

TxC

15

I

TRANSMIT CLOCK: This signal provides timing
information to the internal serial logic, depending upon the
mode of data transfer. For NRZ encoding, data is
transferred to the TxD pin on the HIGH to LOW clock
transition. For Manchester encoding the transmitted bit
center is aligned with the TxC LOW to HIGH transition.

RxC

16

I

RECEIVE CLOCK: This signal provides timing infr:>rmation
to the internal serial logic. NRZ data should be provided for
reception (RxD). The state of the RxD pin is sampled on
the HIGH to LOW transition of RxC.
The operating mode of the 82588 is defined when
configuring the chip.

TCLK/CRS

COT

24

23

I

In High Speed Mode, this pin is Carrier Sense, input CRS,
and is used to notify the 82588 that there is activity on the
serial link.

0

In High Integration Mode, this pin is Transmit Clock, TCLK,
and is used to output the transmit clock.

I

COLLISION DETECT: This input notifies the 82588 that a
collision has occurred. Itis sensed only if the 82588 is
configured for external Collision Detect (external circuitry is
then required for detecting the collision).

RxD

19

I

RECEIVE DATA: This pin receives serial data.

TxD

20

0

TRANSMIT DATA: This pin transmits data to the Serial
Link. This signal is HIGH when not transmitting.

RTS

21

0

REQUEST TO SEND: When this signal is LOW, the 82588
notifies an external interface that it has data to transmit. It
is forced HIGH after a reset and when transmission is
stopped.

CTS

22

I

CLEAR TO SEND: CTS enables the 82588 to start
transmitting data. Raising this signal to HIGH stops the
transmission.
.

VCC

28

POWER:

VSS

14

Ground

8-63

+ 5V Supply

82588

FUNCTIONAL DESCRIPTION
High Integration Mode
The 82588 Single Chip LAN Controller is a highly
integrated device designed for Cost Sensitive LAN
applications such as personal workstation clusters.
Included on the chip is a programmable CSMAlCD
controller, an NRZI and Manchester encoder/decoder with clock recovery, .and two collision detection mechanisms. With the addition of simple transceiver line drivers or RF Modem, the 82588 takes
care of all the major functions of the ISO Physical
and Data Link Layers.

CSMA/CD Controller
The 82588 on-chip CSMAlCD controller is programmable which allows it to operate in II variety of LAN
environments including emerging
IEEE802.3
standards such as 1 Mbps baseband and 2 Mbps
baseband (IBM PC Network). Programmable parameters include:
-

Framing (End of Carrier of SDLC)

-

Address field length

-

Station priority

-

Interframe spacing

-Slot time
-

CRC-32 OR CRC-16

EncoderIDecoder
The on-chip NRZI and Manchester,encoder/decoder supports data rates up to 2 Mbps. Manchester
encoding is often times used in baseband applications and NRZI is used in broadband applications.

Collision Detection
A major innovation with the 82588 is its on-chip logic
based collision detection. To ensure high probability
of collision detection two mechanisms are provided.
The Code Violation method defines a collision when
a transition edge occurs outside the area of normal
transitions as specified by either the Manchester or
NRZI encoding methods. Bit Comparison method
compares the Signature of the transmitted frame to
the receive frame signature (r&-calculated by the
82588 while listening to itself). If the signatures are
identical the frame is assumed to have been transmitted without a collision.

System Interface
The 82588 goes beyond providing the designer with
the functions necessary for interfacing to the LAN. It
has an extremely friendly system interface that
makes it easy to design with. First, the 82588 has a
high level command interface, that is the CPU sends
.the 82588 commands such as Transmit or Configure. This means the designer does not have to write
low level software to perform these tasks, and it offloads the CPU in the application. Second, the 82588
supports an efficient memory structure called Multiple Buffer Reception in Which buffers are chained
together while receiving frames. This is an important
feature in applications with limited memory such as
personal computers. Third, the 82588 has two independent sixteen byte FIFO's one for reception and
one for transmission. The FIFO's allow the 82588 to
tolerate bus latency. Finally the 82588 provides an
eight byte data path that supports up to 4 Mbytes/
second using external DMA.

Network Management & Diagnostics
The 82588 provides a rich set of diagnostic and network management functions including: internal and
external loopback, channel activity indicators, optional capture of all frames regardless of destination
address (Promiscuous Mode), capture. of collided
frames, (if address matches), and time domain reflectometry for locating fault points in the network
cable. The 82588 Register Dump Command ensures
reliable software by dumping the content of the
82588 registers into the system memory.
The next section will describe the 82588 system bus
interface, the 82588 network. interface, and the
82588 internal architecture.

82588/Host CPU Interaction
The CPU communicates with the 82588 through the
system's memory and 82588's on-chip registers.
The CPU creates a data structure in the memory,
programs the external DMA controller with the start
address and byte count, of the block, and issues the
command to the 82588.
The 82588 is optimized for operating with the iAPX
186/188, but due to the small number of hardware
Signals between the 82588 and the CPU, the 82588
can operate easily with other processors. The data
bus is 8 bits wide and there is no address bus.
Chip Select and Interrupt lines are used to communicate between the 82588 and the host as shown in
the Figure 3. Interrupt is used by the 82588 to draw
the CPU's attention. The Chip Select is used by the
CPU to draw the 82588's attention.

inter

82588

There are two kinds of transfer over the bus: Command/Status and data transfers. Command/Status
transfers are always performed by the CPU. Data
transfers are requested by the 82588, and are typically performed by a DMA controller. The table given

in Figure 4 shows the Command/Status and data
transfer control signals.
The CPU writes to 82588 using CS and WR signals.
The CPU reads the 82588 status register using CS
and RD signals.
To initiate an operation like Transmit or Configure
(see Figure 5), a Write operation command from
CPU to 82588 is issued by the CPU. A Read operation from CPU gives the status of the 82588. Although there are four status registers they're read
using the same port in a round robin fashion (Figure
6).
Any parameters or data associated with a command
are transferred between the memory and 82588 using DMA. The 82588 has two data channels, each
having Request and Acknowledge lines. Typically
one channel is used to receive data and other to
transmit data and perform all the other initialization
and maintenance operations like Configure, Address
Set-Up, Diagnose, etc. The channels are identical
and can be used interchangeably.
When the 82588 requires access to the memory for
parameter or data transfer it activates the DMA request lines and uses the DMA controller to achieve
the data transfer. Upon the completion of an operation, the 82588 interrupts the CPU. The CPU then
reads results of the operation (the status of the
82588).

231161-3

Figure 3. 82588/HOST CPU Interaction

Pin Name

Function

CS'

RD

WR

1
0

x

x

1

1

0

0

0

Illegal

0

0

1

Read from status register
Write to Command register

0

1

0

DACKO[DACK1],

RD

WR

1
0

x

x

1

1

• Only one of

CS.

No transfer to/from Command/Status

No DMA transfer

0

0

0

Illegal

0

0

1

Data Read from DMA channel 0 [or 11

0

1

0

Data Write to DMA channel 0 [or 1]

DACKO and DACK1 may be active at any time.

Figure 4. DATABUS CONTROL SIGNALS AND THEIR FUNCTIONS

8-65

inter

82588

6

7

5

3

4

I

INT.
ACK.

.PNTR

I

I

COMMANDS

CHNL

I

COMMANDS
NOP
lA-SETUP
CONFIGURE
MC-SETUP
TRANSMIT
TOR
DUMP
DIAGNOSE
RETRANSMIT

o

2
I

I

I

I

COMMAND REGISTER
COMMANDS
ABORT
RECEIVER-ENABLE
ASSIGN NEXT BUF
RECEIVE-DISABLE
STOP-RECEPTION
RESET
FIXPTR
RLSPTR

VALUE
0
1
2
3
4

5
6
7
12

VALUE
13
8
9
10
11
14

15(CHNL=1)'
15 (CHNL=O)

Figure 5. Command Format and Operation Values

Status 0

7

6

5

4

INT..

RCV

EXEC

CHNL

Status 1

RES~LT 1

Status 2

RES~LT2

Status 3

RCV
CHNL

BUFF
CHNG
NO. OF BUF

RCVSTATE

EVENTS
IA-SETUP-DONE
CONFIGURE-DONE
MC-SETUP-DONE
TRANSMIT-DONE
TOR-DONE
QUMP-DONE
DIAGNOSE-PASSED
END OF FRAME
REQUEST NEXT BUFFER
RECEPTION ABORTED
. RETRANSMIT-DONE
EXECUTION-ABORTED
DIAGNOSE-FAILED

2

3

EV~NT

EXEC
CHNL

VALUE (STATUS 0)
1
2
3
4
5
6
7
8
9
10
12
13
15

Figure 6. Status Registers and Event Values

8-66

1

o

EXEC STATE

inter

82588

generates an Interrupt indicating the experience of a
collision and the frame has to be re-transmitted. Retransmission is done by the CPU exactly as the
Transmit command except the Re-Transmit command keeps track of the number of collisions encountered. When the 82588 gets the Retransmit
command and the exponential back-off time is expired, the 82588 transmits the frame again. The
transmitted frame can be coded to either Manchester, Differential Manchester or NRZI methods.

Transmitting a Frame
To transmit a frame, the CPU prepares a Transmit
Data Block in memory as shown in Figure 7. Its first
two bytes specify the length of the rest of the block.
The next few bytes (Up to 6 bytes long) contain the
destination address of the node it is being sent to.
The rest of the block is the data field. The CPU programs the DMA controller with the start address of
the block, length of the block and other control information and then issues the Transmit command to
the 82588.

Collision Detection
Upon receiving the command, the 82588 fetches the
first two bytes of the block to determine the length of
the block. If the link is free, and the first data byte
was fetched, the 82588 begins transmitting the preamble and concurrently fetches the bytes from the
Transmit Data Block and loads them into a 16 byte
FIFO to keep them ready for transmitting. The FIFO
is a buffer between the serial and parallel part of the
82588. The on-chip FIFOs help the 82588 to tolerate
system bus latency as well as provide efficient usage of system bandwidth.

The 82.588 eliminates the need for external collision
detection logic, in most applications, while easing or
eliminating the need for complex transceivers. Two
algorithms are used for collision detection: Bit Comparison and Code Violation. The Bit Comparison
Method is useful in Broadband networks where
there are separate transmit and receive channels.
Bit Comparison compares the "signature" of the
transmitted data and received data at the end of the
collision window in any network configuration. This
algorithm calculates the CRC after a programmable
number of transmitted bits, holds this CRC in a register, and compares it with received data's· CRC. A
CRC or "Signature" difference indicates a collision.
The code violation is detected if the encoding of the
received data has any bit that does not fit the encoding rules. The code violation method is useful in
short bus topology and serial backplane applications
where bit attenuation over the bus is negligible.

The destination address is sent out after the preamble. This is followed by the source or the station individual address, which is stored earlier on the 82588
using the lA-SETUP command. After that, the entire
information field is transmitted followed by a CRC
field calculated by the 82588. If during the transmission of the frame, a collision is encountered, then
the transmission is aborted and a jam pattern is sent
out after completion of the preamble. The 82588

PREAMBLE
BLOCK BYTE COUNT

BOF FLAG

DESTINATION ADDRESS

DESTINATION ADDRESS

DATA FIELD

SOURCE ADDRESS

CPU GENERATED
DATA STRUCTURE IN MEMORY
(TRANSMIT DATA BLOCK)

I

}
I-

GENERATED BY 82588

FROM 82588
INDIVIDUAL
ADDRESS

TYPE FIELD
/

INFORMATION FIELD

FRAME CHECK SEQUENCE
EOF FLAG (OPTIONAL)
PADDING (OPTIONAL)

t

i

GENERATED BY 82588

231161-4

Figure 7. The 82588 Frame Structure and location of Data element in System Memory

8-67

inter

82588

Receiving a Frame
The 82588 Can receive a frame when its receiver
has been enabled. The received frame is decoded
by either on-chip Manchester, Differential Manchester or NRZI decoders in High Integration Mode and
NRZI in High Speed Mode. The 82588 checks for an
address match for an individual address, a Mulitcast
address or a Broadcast address. In the Promiscuous
mode the 82588 receives all frames. Only when the
address match is successful does the 82588 transfer the frame to the memory using the DMA controller. Before enabling the receiver, the CPU makes a
memory buffer area available to the Receive Unit
and programs the starting address of the DMA controller. The received frame is transferred to the
memory buffer in the format shown in Figure 8. This
method of reception is called "Single Buffer" reception. The entire frame is contained in one continuous
buffer. Upon completion .of reception the total number of bytes written into the memory buffer is loaded
into status registers 1 and 2 and the status of the
reception itself is appended to the received frame.
An interrupt to the CPU follows.

This way the user does not have to allocate large
memory space for short frames. Instead, the 82588
can dynamically allocate memory space as it receives frames. This method requires both DMA
channels alternately to receive the frame. As the
frame reception starts, the 82588 interrupts the CPU
and automatically requests assignment of the next
sequential buffer. The CPU does this and loads the
second DMA channel with the next buffer information so that the 82588 can immediately switch to the
other channel as soon as the current buffer is full.
When the 82588 switches from the first to the second buffer it again interrupts the CPU requesting it to
allocate another buffer on the other (previous) channel in advance. This process continues until the entire frame is received. The received frame is spread
over multiple memory buffers. The link between the
buffers is easily maintained by the CPU using a buffer chain descriptor structure in memory (see
Figure 9).
This dynamic (pre) allocation of memory buffers re-'
suits in efficient use of available storage when handling frames of widely differing sizes. Since the buffers are pre-allocated one block in advance, the syStem is not time critical.

If the frame size is unknown, memory usage can be
optimized by using "Multiple Buffer" reception.

BLOCK LENGTH
BL

DESTINATION
ADDRESS

DESTINATION
ADDRESS

SOURCE
ADDRESS

BLOCK
LENGTH
INFORMATION
INFORMATION

DATA BLOCK IN MEMORY FOR
TRANSMISSION
FRAME STATUS
SINGLE BUFFER RECEPTION

Figure 8. Single Buffer Reception

8-68

231161-5

inter

82588

DEST ADDR
SOURCE ADDR
@

BUFFER 1

@

BUFFER 2

INFO 1

••
•

@

BUFFER #I

INFO 2

BUFFER # 2

BUFFER N

••

o
o
o

BUFFER CHAIN DESCRIPTION
(MANAGED BY CPU)

•
INFO N
BUFFER #N
STATUS
231161-6

Figure 9. Multiple Buffer ReceptIon

80188 Based System

Twisted Pair Connection

Figure 10 shows a high performance, high-integration configuration of the 82588 with the 80188 in a
typical iAPX188-based microcomputer. The 80188
controls the 82588, as well as providing DMA control
services for data transfer, using its "on chip" two
channel DMA controller.

The link consists of a twisted pair that interconnects
the 82588 (See Figure 11). The transmit data pin is
connected via a driver and the receive data pin is
connected via a buffer. The twisted pair must be
properly terminated to prevent reflections.
In the minimum configuration, TxD and RxD are connected to the twisted pair and CTS is grounded. The
82588 may control the driver with the RTS pin. It is
also possible to use external circuitry for performing
collision detection, and feeding it to the 82588
.
through the COT pin.

Link Interface
The Serial Interface Mode configuration parameter
selects either a highly integrated Direct Link interface (High Integration Mode) or a highly flexible
Transceiver Interface (High Speed Mode).

Broadband Conriection
Application

The 82588 supports data communications over a
broadband link in both its modes. Proper MODEM
interface should be provided. Collision Detection by
Bit Comparison, in High Interface Mode, can be applied to transmission over broadband links.

In the High Integration Mode it is possible to connect
the 82588 on a very short "Wired OR" link, on a
longer twisted pair cable, or a broadband connection.

8-69

inter

82588

Cs
RESET
ROM
AD
RD 0(0-7)

0

~

rI
r-

.16 MHz

vec

f1

Xl

X2
UCS

~

lE
RD

A(8-15)

STa

r

~

OE

-

--

WR - . ; . . .
MCSO-3

LATCH

~,-;-

dD~
Rei

r-

8282-0R
8283

-

RD 0(0-7)
WR
PROGRAM
RAM
AD

Cs

Iii'

~

C

I~

I~

II-

RD
WA

-

I---I----

LOW RAM
AD

LCS

I I
I I

I----

CS

AD(O-7)

D(O-7)

80188

-

Vee

-E..-

VV-

ARDY
NMI

HOLD

--,.
DROO
DRQl

rn~rh
Xl
WR
RD

X2

Coi

0(0-7)

RXD
TXD

DRQO
DRQl
DACKO

PCSl
PCS2
RESET

SERI Al
liN K

RTS

ers

DACK1 TClK

J

--

1 0-

tf--

liNE
DRIVERS,
OR
RF
MODEM

~]

RESET

Peso
INT
ClKOUT

Cs
INT
ClK

82588

231161-7

Figure 10_ 80188 Based System

8-70

82588

n
Xl

X2
RTS
CTS

SERIAL
LINK

82588
TXD

RXD

n
Xl

X2
RTS
cfS

82588
TXD

RXD
231161-30

Figure 11. Twisted Pair Connection

8-71

82588

Absolute Maximum Ratings·
Ambient Temperature Under Bias .... O°C to + 70·C
Storage Temperature .......... - 65°C to + 150°C
Voltage on Any Pin With
Respect to Ground ................ -1.0V to 7V
Power Dissipation ...................... 1.7 Watts

"Notice: Stresses above those listed under "Absoiute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

NOTICE SpeCifications contained within the
following tables are subject to change.

D.C. Characteristics (TA = O°C to + 70°C; VCC = + 5V ± 10%)
TxC, RxC have MOS levels (See VMll, VMIH). All other signals have TIL levels (See Vll, VIH, VOL, VOH).
Symbol

Parameter

Min

Max

Units

Test Conditions

Vil

Input low Voltage
(TIl)

-0.5

+0.8

V

VIH

Input High Voltage
(TIL)

2.0

VCC+
0.5

V

VOL

Output low Voltage
(TIl)

0.45

V

IOl = 2.0 rnA

VOH

Output High Voltage
(TTL)

V

IOH = -400 itA

VMll

Input low Voltage
(MOS)

-0.5

0.6

V

VMIH

Input High Volatge
(MOS)

3.9

VCC +
0.5

V

2.4

III

Input leakage Current

+10

itA

0= VIN = VCC

IlO

Output leakage Current

±10

itA

0.45 = VOUT = VCC

ICC

Power Supply Current

380
280

rnA
rnA

TA = O°C
TA = +70°C

Units

Test Conditions

A.C. Characteristics (TA = O°C to + 70°C; VCC = + 5V ± 10%)
System Clock Parameters
Symbol

Parameter

Min

Max

T1

ClK Cycle Period

125

T2

ClKlowTime

53

T3

ClK High Time

53

T4

ClK Rise Time

15

T5

ClKFaliTime

15

ns
1000

8-72

ns

"5

ns

"6

ns

"1

ns

"2

82588

A.C. Characteristics (Continued)

I

Symbol

I

Parameter

Units

Test Conditions

20

ns

·3

4T1

ns

Min

Max

Reset Parameters
T6

Reset Active to
Clock Low

T8

Reset Pulse Width

T9

. Controllnactve
After Reset

T1

ns

Interrupt Timing Parameters
T10

CLK High to Interrupt
Active

85

ns

·4

T11

WR Idle to Interrupt
Idle

85

ns

·4

Write Parameters
T12

CS or DACKO or DACK1
Setup to WR Low

0

ns

T13

WR Pulse Width

95

ns

T14

CS or DACKO or DACK1
Hold After WR High

0

ns

T15

Data Setup to WA High

75

ns

T16

Data Hold After WR High

0

ns

Read Parameters
T17

CS or DACKO or DACK1
Setup to RD Low

0

ns

T18

RD Pulse Width

95

ns

T19

CS or DACKO or DACK1
Address Valid
After RD High

0

ns

T20

AD Low to Data Valid

80

ns

·7

T21

Data Float After
AD High

55

ns

°7

DMA Parameters
T22

CLK Low to DRQO
or DAQ1 Active

85

ns

·4

T23

WR or AD Low to
DRQO or DRQ1 Inactive

60

ns

·4

NOTES:
°1--o.8V-2.0V
°2-2.0V-0.8V
*3-to guarantee recognition at next clock
*4-CL = SO pF

oS-measured at 1.SV
oS-measured at 1.SV
*7-CL = 20 pF-200 pF

8-73

82588

A.C. TESTING INPUT/OUTPUT WAVEFORM
24
.

'
-=X.S_TEST POINTS-1.SX

0.4S

\....._231161-8

AC Testing Inputs are Driven at 2.4V for a logic 1 and 0.45V for a
logic 0 Timing Measurements are Made at 1.5V for Both a logic
1 and 0:
Rise and Fall Time of Input/Output Signals are Measured Between OBV to 2.0V Respectively,

TTL Input/Output Voltage Levels for Timing Measurements

r----~

T3

TS

/------\

--'-------,
/
\

3_SV
3.0V
2_SV
1.SV
1.0V
0.6V

231161-9
Rise and Fall Time of Input Signals are Measured Between 1.0V
to 3.5V Respectively.

Clopks MOS Input Voltage Levels for Timing Measurements

elK

INT

T10

--

Interrupt Timing (Going Active)

8-74

231161-10

82588

cs

'\.

/
7

r17

'\

'\.

WR

}n'i

INT

231161-11

Interrupt Timing (Going Inactive)

elK
T6

-

RESET

T8

- - - - - - - - - - + 1 ..,

I
DRQO,DRQ1

INT
5/18

-

T9

231161-12

Reset Timing

8-75

inter

82588

Serial Interface A.C. Timing Characteristics
High Integration Mode
TFC is the crystal or serial clock input at pin 15 (X1).
TFC Frequency Range:

For OSCillator: Frequency

1 to 16 MHz (Highr

=

xBSampling

For Oscillator Frequency

X16Sampling

0.125":"2 MHz
B x T24
T24 (Typically)
7 x T24 (Typically)

TClK Frequency
T29 = TClK Cycle Time
T30 = TClK High Time
T31 = TClK low time
=

. 62.5 kHz -1 MHz
16 x T24
T24 (Typically)
15 x T24 (Typically)

0 to 1 MHz (Low)·

TClK Frequency
T29 = TClK Cycle Time
T30 = TClK High Time
T31 = TClK low Time

XBSampling

x16Sampling

0-0.125 MHz
T24
T25 (Typically)
7 x T24 + T26 (Typically)

0-6.25 kHz
16 x T24
T25 (Typically)
15 x T24 + T26 (Typically)

8x

• A non-symmetrical clock should be provided so that T25 is less than 1000 ns.
T24 = Serial Clock Period
T25 = Serial Clock High Time
T26 = Serial Clock low Time

High Speed Mode
•

Applies for TxC, AxC
= 5 MHz ±100 ppm
1
For Manchester', symmetry is required: T2, T3 =
± 5%

• .f max
•

it

High Integration Mode

I

Symbol

I

Parameter

Min

Test Conditions

Max

Units
ns

·1

1000

ns

·1, ·14

External (Fast) Clock Parameters
T24

Fast Clock Cycle

T25

TFC High Time

20

T26

TFClowTime

20

ns

·1

T27

TFC Rise Time

5

ns

·1

T2B

TFCFallTime

5

ns

·1

ns

·3, ·12

ns

·3

ns

·3

62.5

Transmit Clock Parameters
T29

Transmit Clock Cycle

T30

TClK High Time

500

·8

T31

TClK low Time

·9

T32

TClK Rise Time

15

ns

·3

T33

TCL~ Fall Time

15

ns

·3

1030

8-76

.

inter

82588

High Integration Mode (Continued)

I

Symbol

I

Parameter

Min

Max

Units

Test Conditions

ns

*12

Transmit Data Parameters (Manchester)
4T24-10

T34

TxD TransitionTransition

T35

TCLK Low to TxD
Transition Half
Bit Cell

*11

ns

*2, *12

T36

TCLK Low to TxD
Transition Full
Bit Cell

, *10

ns

*2, *12

T37

TxD Rise Time

15

ns

*2

T38

TxDFaliTime

15

ns

*2

ns

*12

ns

*2,. *12

Transmit Data Parameters (NRZI)
8T24-10

T39

TxD TransitionTransition

T40

TCLK Low to TxD
Transition

*10

T41

TxD Rise Time

15

ns

*2

15

ns

*2

*10

ns

*3, *12

T42

TxD Fall Time

--

RTS, CTS, Parameters
T43

TCLK Low To RTS Low

T44

CTS Low to TCLK Low
CTS Setup Time

T45

TCLK low to RTS
High

T46

TCLK Low to CTS
Invalid. CTS Hold
Time

T47

CTS High to TCLK
Low. CTS Setup
Time to Stop
Transmission

65

ns
ns

*3, *12

20

ns

*4, *13

65

ns

*4

'10

IFS Parameters
T48

Interframe Delay

*5

ns

Collision Detect Parameter
T49

CDT Low to TCLK
High. External
Collision Detect
Setup Time

50

ns

*13

T50

CDT High to TCLK
Low

50

ns

*13

T51

TCLK High to CDT
Inactive. CDT Hold
Time

20

ns

*13

8-77

82588

High Integration Mode

(Continued)
Test Conditions

Parameter

COT Low to Jamming Start
Jamming Period
Received Data Parameters (Manchester)
T54

RxO TransitionTransition

*12

Received Data Parameters (Manchester)
T55

RxO Rise Time

10

ns

*1

T56

RxOFaliTime

10

ns

*1

ns

*12

ns

*1

ns

·1

Received Data Parameters (NRZI)
T57

RxD TransitionTransition

T58

RxD Rise Time

T59

8T24

10
10

RxOFallTime

'7-T53 = 32 x T29
'S-Depends on T24 frequency range:
, High Range: T24 - 10
Low Range: T25 - 10
'9-T31' = T29 - T30 - T32 -T33
'l0-2T24 + 4.0 ns
·11-6T24 + 40 ns
·12-For x 16 sampling clock parameter minimum value
should be multiplied by a factor of 2. '
·13-To guarantee recognition on the next clock.
·14-62.5 ns minimum in LowRange.

NOTES:
'l-MOS levels,
'2-1 TIL load + 50 pF.
'3-1 TIL load + 100 pF.
"4-Abnormal end to transmission: CTS expires before
RTS.
'S-Programmable value: T4S = NIFS x T29 (ns) NIFSthe IFS configuration value.
If NIFS is less than 12, then it is enforced to 12.
'S-Programmable value:
T52 = NCDF x T29 + (12 to 15) x T29 (if collision occurs aller preamble).

es DACKO
DACK1

-

:

T12

--113-1

I+-

I

r
I

J

WR

00-7

r-

T14

I'''-:'~t

~
I

Write Timing

8-78

VALID

231161-13

intJ

82588

DACKO
K1

--

T17

...I

~

I--

--

00-7

T19

T20

T18--1

-

1
I

--

T21

231161-14

Read Timing

CLK~
-

T22

DRQO DRQ1

231161-15

DMA Request (Going Active)

DRao DRa1

-----...,j

DACKO DACK1
- -.....~
WRRD

...

1-'-T23

-----.I

I
231161-16

DMA Request (Going Inactive)

8-7\9

82588

TFC

~LK~~_n=6_ _=-~~

:~m~

__1~n~

__

41,«

~~=-

____~n

CDT----------------------------~--~~---------------------------------

TXD-----------------L-.

I
I
~--lST BIT CELL ----~

~

TXC

~
~T45~

RTS

-+

,

CTS

I+-T47
::""""!_...I'-T46

COT
TxD
--t::ALF BIT CELL-..I
231161-17

Transmit Timings: Clocks RTS and CTS

r

---1""

~T35_

T36

1

f

TxD

-----

-.

~

I

-T34--1

.1.

DATA BIT CELL

DATA BIT CELL

.-"

-.II.T38

.1
231161-18

Transmit Timings-Manchester Data Encoding

*="'.~F
=-

TCLK~

RTStT47
CTS

CDT-------------------------------------------TXD ____________~I~

______________________

~

231161-19

Transmit Timings-Lost CTS

8-80

inter

82588

r

--f'1

~4~
1

_T40_
TxD

II

1:

1~

DATA BIT CELL

DATA BIT CELL

----I

231161-20

Transmit Tlmings-NRZI Data Encoding

:_---"
__~~~~~_-_-_-_-_-_-_T4~'j-t. . .tMl=
,

c~--------------------~------------~----TXDJ

I

231161-21

Transmit Tlming~Lost CTS

RxD

-t-

T54

----+11=

T56
T55

Receive Data Timings (Manchester)

8-81

231161-22

intJ

82588

RxD

=t_ -

T59
- -----T57 _______J+tfT58
231161-23

Receive Data Timings (NRZI)

TFC
TCLI(

---11-------~f

~s-----tt:~-----~--~U8~~~~~!t::::::~-----~-

Ci'S _ _- - -_ _ _ _--'!

I

CDT

S

TxD

I

S

I

FIRST HERE
DATA BIT
FROM
THE RIGHTTO
231161-24

Transmit Timings-Interframe Spacing

TFC~~
~

S

~~

________

---,n~

____

~S------~S rS--------------~-------'r-

~§------t;.~ ~I- - - - - -

TxD

.A..-1;:=~::Sr52ti==:::;:~~.~S~SI~=======-~\~Ti;53i-===~'C===:)t_

231161-25

Transmit Timings-Collision Detect and Jamming

8-82

82588

High Speed Mode

I

Symbol

I

Parameter

Min

Max

Units

200

Test Conditions

Transmit/Receive Clock Parameters
T60

RxC TxC Cycle

*13

ns

T61

TxC Rise Time

10

ns

T62

TxC Fall Time

10

ns

*1

T63

TxC High

80

1000

ns

*1, *3

T64

TxC Low

80

ns

*1, *3

*1

Transmit Data Parameters
T65

TxD Rise Time

20

ns

*4

T66

TxD Fall Time

20

ns

*4

T67

TxC Low to TxD
Valid

60

ns

*4, *6

T68

TxC Low to TxD
Transition

60

ns

*2, *4

T69

TxC High to TxD
Transition

60

ns

*2, *4

T70

TxD TransitionTransition

T71

TxC Low toTxD High
(At the Transmission End)

*2, *4

70
60

ns

*4

60

ns

*5

RTS, CTS Parameters
T72

TxC, Low to RTS Low
Time to Activate RTS

T73

CTS Low to TxC Low
CTS Setup Time

ns

65

TxC Low to RTS High

T75

TxC Low to CTS Invalid

20

ns

CTS High to TxC Low
CTS Set-up Time to
Stop Transmission

65

ns

*9

ns

T75A

60

ns

T74

*5
*7

Interframe Spacing Parameters
T76

I

Inter Frame Delay

CRS, CDT, Parameters
T77

CDT Low to TxC High
External Collision
Detect Setup Time

45

ns

T78

TxC High to CDT Inactive
CDT Hold Time

20

ns

T79

CDT Low to Jamming
Start

T80

Jamming Period

'11

ns

T81

CRS Low to TxC High
Carrier Sense Setup Time

45

ns

*14

T82

TxC High to CRS Inactive
CRS Hold Time

20

ns

*14

*10

8-83

*14

ns

inter

82588

(Continued)
Parameter

Test Conditions

CRS, COT, Parameters (Continued)
T83

CRS High to Jaming
(Internal Collision Detect)

T84

CRS High to RxC High.
End of Receive Packet

80

ns

T85

RxC High to CRS High.
End of Receive Packet.

20

ns

'12

ns

Receive Clock Parameters
T86

RxC Rise Time

10

ns

'1

T87

RxC Fall Time

10

ns

'1

T88

RxC High Time

80

ns

'1

T89

RxCLowTime

80

ns

*1

RxD Setup Time

45

ns

*1

45

Received Data Parameters
T90
T91

RxD Hold Time

ns

'1

T92

RxD Rise Time

20

ns

'1

T93

RxD Fall Time

20

ns

'1

NOTES:
"1 - MOS levels.
"2 - Manchester only.
"3 - Manchester. Needs 50% duty cycle.
"4 - 1 TIL load + 50 pF.
"5 - 1 TIL load + 100 pF.
"6 - NRZ only.
"7 - Abnormal end to transmissions: CTS expires before RTS.
"S - Normal end to transmission.
"9 - Programmable value.
T76 = NIFS x T60 (ns)
NIFS - the IFS configuration value.
If NIFS is less than 12, then NIFS is enforced to 12.
"10 - Programmable value:
T79 = NCDF x T60 + (12 to 15) x T60 (ns) (if collision occurs after preamble).
"11 - TSO = 32 x T60
"12 - Programmable value:
NCSF x TIRC + (12 to 15) x TIRC
TS3 = NCSF x T60 + (12 to 15) x T60
NCDF - collision detect filter configuration value.
*13 -·2000 ns if configured for Manchester encoding.
"14 - To guarantee recognition on the next clock.

8-84

82588

CRS~

T81

____ _

TxO '::::J.-----r------~

[NRZ]

:ftI-----

TxO

---\-

-~~

-r --'\ _

ro- ,...-----,U r'"\\...J

• __ ~ __ J

r--

_• .J.J

[MANCHESTER)

231161-26

COT --+l'-+--+-I---~
CRS--+i-r--r+----4

(:~~ --ttji:i.~.tr::9;'------V­
TXO

-1It-J!I:r~-~

(MANCHESTER) T68

T68

TTl

Transmit Data Waveforms

8-85

T65 T66

231161-27

inter

82588

231161-28

Receive Data Waveforms (NRZ)

231161-29

Receive Data Waveforms

8-86

ARTICLE
REPRINT

AR 345

Build a VISI-based workstation
'for the EtheITlet environment
In a shared-resources~ distributed-system envirQnment~
you can desi;gn a compact computer system using the
latest chips to keep network node component count
low and ()jJerations at hard-disk speeds.

Michael Webb, Intel Corp
Early distributed minicomputer systems used a variety
of dissimilar networking methods, services and expansion provisions. As jJ.C-based workstations invade the
business environment, the need arises for standardized
local networking that can quickly transfer information
and make optimum use of shared resources. You can
build an Ethernet workstation that's relatively simple
and inexpensive by configuring a network using the
system, hardware and software considerations described in this article.
Choosing Ethernet as the network environment
makes good sense. Fbr example, Ethernet makes it
possible to share large, high-speed, remote file facilities
and thus minimize or even eliminate the need for disk
storage at the workstation. Similarly, you can eliminate
printers at most stations by sharing higher quality
printers that provide automatic print spooling and such
special features as graphics with text and electronic
typesetting.
These remote high-quality services are possible
because Ethernet permits rapid, 10M-bps data transmission with even a large number of network users, and
sharing makes the services cost effective. This shared
approach to overall system configuration allows you to
build a compact, high-performance workstation that is
optimal for a local-area-network (LAN) environment.
Although most major components used in this

workstation are Intel parts, many are available from
second sources. You can substitute other parts with
some design adjustment. Fbr example, you can use a
high-speed 68000 CPU. Its system interface is more
complex, and the total parts count would increase. In
the design described, the total component count can be
fewer than 75 ICs, even with 256k bytes of 64k-bit
dynamic RAM (32 ICs).
A system overview
Fig 1 shows an Ethernet workstation configured
without disk drives or a printer. The two JEDEC
28-pin EPROMs that reside on the system bus store
bootstrap, diagnostic and utility programs. The bootstrap program locates the correct file server on
power-up and downloads the operating system over the
net. File accesses to remote file servers depend on
Ethernet speed to keep performance at the level
experienced when hard disks are dedicated to a single
workstation. With large system memory, say, 256k
bytes with 64k RAMs or 1M byte with 256k RAMs,
large applications programs and data files can reside in
the workstation once loaded over the network.
Of course, to connect to the network, the workstation
needs an Ethernet interface. This formerly required a
board of MSI devices and one or more DMA channels.
Today, a dedicated LAN coprocessor combined with an
Ethernet serial interface chip can provide the complete
Ethernet interface. An 82586 LAN coprocessor, which

EDN FEBRUARY 23, 1984
Reprinted with permission from EON February 23, 1984. Copyright © " von"ers Publishing Co. All rights reserved.

8-87

ORDER NUMBER: 231207-001

Available shared LAN resources
provide lower cost workstations

implements the full Ethernet specification and is
compatible with the IEEE 802.3 LAN standard,
provides buffer management both concurrently and in
real time so that you can take full advantage of
Ethernet performance.
Using a dual-port memory system permits the
various system processors to share as much as 1M byte
of 150-nsec dynamic RAM, which runs at 8 MHz,
without any wait states. One memory port is tied to the
system bus, while the other port is tied to a display
system through a multiplexed blis. Using this dual-bus
arrangement offloads the system bus from such tasks
as screen refresh.
The dual-channel communications controller has two
serial 110 channels, each of which can be configured for
a different protocol; one Of its ports. is used for the'
workstation's keyboard, and the other channel supports
a local modem interface. The keyboard contains a
battery-backed CMOS single-chip microcontroller
(80C51) that controls the keyboard, has an interface for
a mouse or digitizing pad and maintains semipermanent
system configuration and real-time clock information
even when the system is powered down.
The logic needed to read and execute high-level

Ethernet communications tasks is in the LAN coprocessor. It accesses the Ethernet through a serial
interface chip and a transceiver (Fig 2). The interface
between the serial interface chip and the transceiver
requires a crystal clock and a few capacitors and
resistors.
The hardware interface between the LAN coprocessor .and CPU (Fig 3) is even more straightforward,
requiring only an inverter and transistor. The LAN
coprocessor, which has the same pin configuration as
the CPU, resides on the multiplexed CPU bus. To gain
control of this bus, the LAN coprocessor uses its
Hold/Hold Acknowledge (HOLD/HLDA) lines, which
are directly wired to the CPU. The LAN coprocessor
and CPU share a set of octal noninverting address
latches and transceivers, through which they access the
system bus and communicate with system memory. All
commands and status concerning the Ethernet link are
exchanged between the two through this memory.
The dual-port controller, through which system
memory is accessed (Fig 4), gives priority to Port A,
the port shared by the CPU and LAN coprocessor,
thereby minimizing latency when receiving an Ethernet packet. This· arrangement allows time for the

Fig 1-.:consisllng 01 lour main subsections-a network-interface control system, CPU, dual-port memory system and display
controller-this Ethernet workstation relies on VLSI parts for high-speed performance, EPROM memory contains the bootstrap
program that gets the system onto the net at power-up, while the dual-channel controller provides a keyboard interface and modem
communication,

8-88

231207-001

VLSI reduces a board of components
to a single coprocessor chip
.

workstation to receive a maximum-size Ethernet packet, while the text coprocessor, which resides on Port B
of the memory controller, simultaneously fills a display
buffer. By using a dual-port memory controller, you
also shift the overhead incurred in filling a display
buffer away from the main system bus, freeing it for
other application tasks, such as communicating via the
modem.
Because high-quality, low-cost printing is to be a
network resource, your workstation should let you
generate documents with different type fonts and
graphics. A text display of 25 lines x 132 characters and
proportional-spacing capability is suitable for most
business applications. Integrating a text coprocessor
into the display system (Fig 5) makes sense because it
can generate the proportionally spaced text using an
LSI video interface component. Add a character
generator and three latches for synchronization, and
the display interface is complete.

20
26

RTS 28
TXD 27

TO CPU
BUS

16
15

'!'XC

. ETHERNET
TRANSCEIVER
CABLE

,.---------,

10

Vee

I

TXD

!

RCV

6C1rn

RXD

I
I
I
I

1.5k 391 RECEIVER
PAIR

_5

8 Rxe

I

I
I
I
I
82501
ESI

_31
CRS

~!..---+-,

I
I
~
~--.i
~i+---~

17

_23
RXC

TRANSMIT
PAIR

TEN

82586
CONTROLLER

25

Looking at bandwidth realities
Considering the memory-intensive nature of this
design, sufficient bandwidth in the dual-port memory
system is a key factor. There must be sufficient
bandwidth to support the data-rate requirements for
display refresh. At the same time, the LAN coprocessor must be able to access memory frequently enough
during packet reception or transmission to avoid
overrun or underrun in its on-chip FIFO buffers .

OV

5V

TxC

Concurrent display of data from different files in
separate areas of a CRT screen, called windows, has
proven desirable in business applications and should be
part of any modem workstation. In the past, hardware
support for mUltiple windows was available only in
$lO,OOO-and-up workstations. A text coprocessor with
on-chip DMA simplifies list-based manipulation of
multiple overlaid text windows, as used with the Xerox
Star and Apple Lisa workstations.

3.5

A

I

39I>---tHH:__
I

I
I

I

~r---'

I
I
I

CLSN~1~2;__f~IP---+~7r-<~I.---1r_,

9 RXD

30
COT

i:Ooi5liJiCi( INPUT
FROM PROCESSOR

20

~HZ

I POWER
I PAIR

12TO

TT

1~--8E;__f.:1_

'"

>cr

~
ADo-AD,!

PIPELINE
REGISTER

Jo.

~l

;~

1--+

L...-..y'
82730
TEXT
COPROCESSOR

0
:li

OW
PROG

CHARACTER
GENERATOR
LINE ADDRESS

A,,-A23

t--v'
f----J\

~

VIDEOH

CRT

HOOT

~ wo-w'J

f--v'

~

.m

X'I1.
~'6.25MHz

X,~

0 0 -0 15
RRW

Q.

5

CSYN

::>
:li

ATTRIBUTE AND
CONTROL SIGNALS

CHOLD

0

T,

CBLANK

300 nH

CRW
WDEF

r----

0
T,

CCLK

BUS
CONTROL

RCLK

ri/--

TO.

1 "F

1

VT

t

1k ::::
_l~lonF

""-

JO"

100 pF

D = BB505 VARACTOR DIODE OR EQUIVALENT

Fig ~or the CRT subsystem, the 82730 and 82731 convert byles from the workstalion bus to characters on a
25-linex 132-character CRT screen. The text coprocessor also handles multiple windows.

8-91

231207-001

Providing dual-ported memory
oftloads the system bus
available in memory. At the same time, 'AI to 'AI of the
bus bandwidth is still available for the CPU to continue
program execution. In previous systems, program
execution virtually stopped while high-bandwidth peripheralsare using the bus. Because both peripherals
are coprocessors, they run asynchronously and concurrently with other system activity.
With plenty of leftover bandwidth, the two DMA
channels on the CPU can be used to add efficiency and
performance to the dual-channel communications controller. Data from the keyboard-input buffer is transferred to the CPU via DMA, and the other DMA
channel makes possible a 64k-baud synchronous or
HDLC modem link on the communications controller's
other port. Baud-rate timing for the two channels is
generated using two of the CPU's three on-chip timers.
The CPU also directly generates chip selects, channel
attentions and wait states for the system peripherals.
The CPU's on-chip interrupt controller services interrupt inputs from the LAN coprocessor, text coprocessor, communications controller and other peripherals.

mum workstation. Fig 6 shows how the LAN coprocessor interacts with the system from a software point of
view. Receive and Command units are software
constructs rather than physical segments of the LAN
coprocessor; in reality, the same hardware performs
both functions.
As previously noted, all communications between the
CPU and the LAN coprocessor occur in system
memory. The CPU builds a command 'block, stores it in
memory, updates the command-block ljst and then
activates channel attention to get the LAN coprocessor
to look at the command-block list for one or more new
commands. If requested by the command block, the
LAN coprocessor interrupts the CPU on completion of
one or more commands.
The focal point for all, interaction is the system
control block (Fig 7). This data structure contains chip
status, pointers to the command-block list and receiveframe areas, and universal statistics on faults such as
CRC errors and alignment errors.
Both the command-block list and receive-frame area
use the same concept, or model, to manage data buffers
The software relationship
for either transmission or reception. The buffer manMost of the system's hardware relationships are agement model employs one or more arbitrarily sized
easily grasped, but a firm understanding of the buffers to construct each data frame. Pointers control
software architecture is essential to building an opti- and access the buffers, and linked lists manipulate
them.
This model offers distinct advantages over more
primitive approaches. Allowing the physical buffers to
be arbitrary sizes gives the system designer maximum
flexibility in selecting the buffer size and in allocation
methods. Because you can locate the memory for these
, buffers anywhere in the 16M-byte address space, this
SERIAL
buffer management support simplifies the task for the
DATA OUT

y15

CONTROL INFORMATION

STAT

101

CUS

101

RUS

10101010

SCB

ACK

'I ·1

CUC

I~I

RUC

1

SCB

+

COMMAND BLOCK LIST POINTER

SCB

+

4

RECEIVE FRAME AREA POINTER

SCB

+

6

2

CRC ERROR COUNTER

SCB

+8

ALIGNMENT ERROR COUNTER

SCB

+

10

RESOURCE ERROR COUNTER

SCB

+

12

OVERRUN ERROR COUNTER

SCB

+ 14

Fig 7-A speclel memory block, the system control block,
serves as a bulletin board whereby the CPU and LAN.
controller communicate. The system control block holds
control and status information pointers to the commandblock list, where the CPU stores instructions for the LAN
coprocessor, and the receive-frame area, where data from
the Ethernet is stored by' the LAN coprocessor. The block
also contains error information of interest to the CPU.

Fig 6-Seen from e software perapectlve, the LAN
coprocessor looks like Receive and Command units. When
receiving data packets from Ethernet, the coprocessor
converts them from serial form and places them in frame area
locations, it manages within the memory system. The CPU
directs the coprocessor using handshake lines, and messages left In the shared-memory system's command-block list.

8-92

231207-001

The CPU and LAN coprocessor
communicate through shared memory
operating system's dynamic memory-allocation scheme.
Communication buffers for the LAN coprocessor are
dynamic by dl'lfinitlion. .
A buffer needn't be the size of the largest frame ever
expected; it can be any convenient size. If a frame
larger than .the selected size arrives, the LAN
coprocessor automatically allocates as many buffers as
necessary to contain the frame, and updates the
pointers and links to indicate where the frame starts
and which buffers are occupied by the frame.
This flexible buffer size avoids the waste of large,
dedicated buffers for receive frames when most of the
frames actually received are much smaller than the
maximum size (ie, are control frames rather than data
frames). Also, this automatic buffer chaining of receive
data increases communications performance and efficiency; even if several frames arrive before the CPU is
free examine incoming data, the workstation se~dom,
if ever, misses a frame addressed to it.
The effectiveness of this buffer management scheme is

to

L
;-

SYSTEM
CONTROL
BLOCK
SIC

r-RFA POINTER
STATISTICS

TO COMMAND
BLOCK LIST

perhaps best understood by examining what happens
when a packet comes in from Ethernet. The LAN
coprocessor's Receive section handles all frame reception activities. It manages a pool of memory space-the
receive-frame area (Fig B)-using the receive-frame
and free-frame lists.
Within each list are receive-frame descriptors
(RFDs) that contain status data and pointers. The
RFDs in the receive-frame area point both to the first
buffer that has been filled with received data, and to
the first' RFD of the free-frame area. The CPU can
organize the pointers in linear, random or circuhir
fashion. Once a pointer structur.e is adopted, the LAN
coprocessor allocates buffers and maintains the proper
linkage automatically.
When the LAN coprocessor begins receiving a
frame, it uses the first RFD in the free-frame list to
hold status and information concerning the frame, and
then allocates and links in as many free buffers as
necessary to contain the frame data. The linking

I

i"1- . . . . - - - - - - ' - - - ' - - - - - - ~ECEIVE FRAME AREA-,--------:-------'~

I

I

RFDl

t -1

STATUS

I
I
I

1
.1

~

II

1

RBDl

o

--

Lr

RBD2

BUFFE!ll

EMPTY

EMPTY

RBD4

RBD5

o I ACT·CNT

o I ACT·CNT

o IACT-CNT

........ '--

,....-'--

r--'--

EMPTY

EMPTY

EMPTY

""'--

""'--

'---

RBD3

P

1 I ACT·CNT

--

VALID
DATA

-

RFD4

STATUS

EMPTY

-

I ACT·CNT

RFD3

STATUS

e:-

l-

VALID
PARAMETERS

L

RFD2

STATUS

-J -J -U1

I
I

-

BUFFER 2

-J

BUFFER 3

-

BUFFER 4

J

-l1!

BUFFER 5

I

1
I

I

I

11-00_1---- RECEIVE FRAME LlST-----'.~I""1_...._-----FREE FRAME LlST------...,~~1

Fig &-Recelved packets are stored, in a receive-frame area consisting of two linked lists-the receive-frame list and free-frame list.
The LAN coprocessor pulls into the receive-frame list as many buffers of any size as needed to store an incoming packet. Buffers
used are pointed to by receive-frame descriptor (RFD) and receive-buffer descriptor (RBD) blocks. The variable-size message block .
saves memory, with packets stored according to actual size rether than maximum size.

8-93

231207-001

process is accomplished using a receive-buffer des- cally inserts the frame preamble, source and destinacriptor (RBD) to point· to the next buffer containing tion addresses, type field, and CRC during the
transmission process. The CPU can choose to be
contiguous data.
Once frame data is complete, the LAN coprocessor interrupted following the transmission of one frame, or
writes the frame status into the associated RFD and it can link together several transmission requests and
the actual count of valid data into each RBD used by the be interrupted following the final frame
EDII
frame. It then flags the last RBD used to contain the transmission.
frame and updates the first RFD on the free list to
point to the first free RBD. All this is done in time to
References
catch a second frame sent to the workstation address, if
one is transmitted immediately following completion of
1. Metcalf, R M, and Boggs, D R, "Ethernet: Distributed
Packet Switching for Local Computer NetWOrks," Comthe previous frame using Ethernet's 9.6-fLsec minimum
munications of the ACM, Vol 19, No.7, July 1976, pp
frame spacing.
395-403.
In effect, the LAN coprocessor can receive continu2. Shoch, J F, and Hupp, J A. "Performance of an
ous data packets from the network as long as buffer
Ethernet Local Network: A Preliminary Report," Proceedings. of the Local Area Communications Network Sympospace remains available. This is achieved by dedicating
sium, May 1979, pp 113-124.
a complete microcoded machine in the LAN coproces3. Tobagi, F A, "Message-based priority functions in
sor to generating buffer management primitives, and
Multiaccess/Broadcast Communications Systems with
giving this machine DMA control to speed its bus
carrier sense capability," Stanford University Electronic
requests. No DMA setup or control is needed from the
Labs Technical Report, No. 181, October 1979.
4. Digital Equipment Corp, Intel Corp, and Xerox Corp,
CPU, reducing overhead and simplifying the system.
"The Ethernet Specification," Ver 2.0, November 1982.
Data transmission is accomplished in a similar
fashion. To transmit a frame over the Ethernet via the
LAN coprocessor, the CPU constructs a command
block (Fig 9). Included in this command block is a
pointer to ll.buffer descriptor, which points to one or
Author's biography
more buffers containing the data to transmit.
Michael Webb is a regional
If more than one buffer is used, the LAN coprocessor
applications specialist for Intel
automatically links the buffers together as it transmits
Corp (Dallas, TX), where his
the frame. In addition, the LAN coprocessor automatiprimary job is to help custom-

~':::::~
CJB]

ELI

sIJ

EVEN BYTE 0
STATUS

I

I

CMD

A15

LINK ADDRESS TO NEXT COMMAND

AO

A15

POINTER TO TRANSMIT BUFFER DESCRIPTOR

AO

2NDBYTE

1ST BYTE
I
I
DESTINATION ADDRESS

ers define architectures and
designs for distributed systems, such as the Ethernet
system described in this article. No stranger to Ethernet,
Mike previously worked at
Xerox Corp in the Office Products Div where he was engineering manager for Ethernet communications software.
Mike's hobbies include devising game software and
chess.

E

I
NTH BYTE
B15

I
I

TYPE FIELD

INTEL CORPORATION, 3065 Bowers Ave.
Santa Clara, CA 95051; Tel. (408) 987-8080

BO

Fig 9-The system conttol block points at the command
block containing instructions from CPU to LAN controller
concerning a transmission. These include control information, a link to the next command, a pointer to a transmit-buffer
descriptor, the packet's destination address and the type of
field it contains. The command area Is organized similarly to
the receive-frame area.
.

8-94

INTEL INTERNATIONAL CORPORATION Ltd.
Swindon, United Kingdom; Tel. (0793) 488 388
INTEL JAPAN k.k., Ibaraki-ken; Tel. 029747-8511
Printed in U.S.AJD-4043/10K/9-84/SCP/PM
peripherals

231207-001

inter

ARTICLE
REPRINT

AR-346

September 1984

VLSI Solutions for Tiered Office
Networks

BOB DAHLBERG AND CHARLES GOPEN

Order Number: 231194-002

@ Intel Corporation, 1984

8...95

VLSI SOLUTIONS FOR
TIERED OFFICE
NETWORKS

CONTENTS

PAGE
Introduction ................................ 1
The Tiered Network Model ......•.......... 1
Applications and Tiers ...................... 2
Evolution Scenarios ........................ 2
VLSI and the LAN Backbone ............... 4
VLSI for the Human Interface Tier .......... 5
Cheapernet ................................ 5
1 Mbps CSMAlCD LAN .................... 5
Voice/Data PBX ........................... 6
Conclusion ................................. 6
References •................ '............... 6
APPENDIX A
INTEL LAN SOLUTIONS .............; . . A-1
The 82586 LAN Coprocessor ............. A-1
The 82501 Ethernet Serial Interface ...... A-1
iNA Transport Software .................. A-2
Transport Services ....................... A-2
Network Management Services ........... A-2
User Environment ........................ A-2

8...96

231194-002

inter

AR-346

Tier 2, the LAN Backbone, is a high perfonnance tier
generally operating in the 10 Mbps data rate range and
cover a distance sufficient for a single building. An example of this kind of network is the IEEE 802.3/Ethernet. This tier is the main highway over which infonnation travels throughout a building connecting expensive
peripherals (e.g. laser printers and file servers) to end
users located in the clustered tier.

Introduction
Local area networks, or LANs, were developed as a
response to the development of distributed intelligence.
In the past decade the -perfonnance/price ratio of microprocessors has increased well over 1000 fold. It is
these low cost microprocessors that have enabled computational capability fonnerly residing in a centralized
computer to be placed on users' desks. However, the
cost of computer peripherals (such as letter quality
printers, Disk memories, and communication servers)
has not dropped in a similar fashion (because of high
electro-mechanical content). Also, there is an increasing need to share timely and accurate infonnation
among users in a business setting. LAN technology is
the solution to these problems by allowing users to
share the cost of peripherals and access common data
bases.

Tier 3, or the Human Interface tier, is characterized i?y
the clustering of end user workstations. Networking capability in this tier exhibits the most cost sensitivity
because the workstations themselves are numerous and
low cost ($500 for a tenninal to $3000 for a personal
computer). Fortunately humans can tolerate display
screen latencies of 0.5 to 1 second that lower bit rates
provide. These lower bit rates enable low cost networks
to be realized. The need for low cost is the reason why
data rates in this tier are generally 1 Mbps or less. Examples of Tier 3 networks are personal computer networks such as Orvus Systems' Omninet, Orchid Technology's PCnet, Nestar's Plan Series and JEEE 802.3
Star LAN.

As LANs begin to proliferate, it is becoming clear that
no single network type can cost effectively meet all office users' requirements. Some applications require high
data rates; for example, real time graphic display infor,
mation. Other applications require the lowest cost per
connection; for example, data entry tenninals. This fundamental tradeoff between perfonnance and cost drives
the evolution of a tiered network architecture for the
office. A model based on tiered network architecture
predicts that user workstations within a department
will be clustered together, and that these clusters will be
interconnected through a LAN Backbone network.

Voice/data PBXs will play an important role in Tier 3.
Telecommunication suppliers have a-big advantage in
the office in that almost everyone has a phone on his
desk. Today users take advantage of this installed network capability through modems. PBX manufacturers
have already begun to make cluster products available
in the fonn of voice/data PBXs. The data rates offered
are 19.2 to 64 kbps in addition to voice, which is sufficient for terminal applications. These manufacturers
are already reducing the tenninal/station apparatus
footprint size by offering teletenninal (combined tenninal and phone) products.

Today these two types of networks (cluster and LAN
Backbone) can be realized by using available VLSI
technology. Intel's 82586 LAN Coprocessor supports
LAN Backbone technologies such as IEEE 802.3/Ethemet. The 82586 also supports the cluster networks by
realizing 1 Mbps CSMA/CD networks. I Mbps networks are significantly cheaper than LAN Backbone
networks because lower cost cabling and electronics
can be used, and fewer repeaters are required between
cable segments. In the future, PBXs will play an important role in this clustering tier as true two wire voice/
data communication becomes a reality.

A Three Tier Network Office/Commercial

A TIERED NETWORK OPTIMIZES COST
AND PERFORMANCE
nER 1: COMPUTER-TO-COMPUTER
(20-.00_)

TJER 2: LAN BACKBONE
(.... M...)

The Tiered Network Model
An office network can be thought of as consisting of
three perfonnance tiers. End users can optimize their
network cost/perfonnance ratio by building up networks with different perfonnance attributes.
The Three Tier Network Model is shown in Figure 1.
Tier I, the highest perfonnance tier, is referred to as the
Computer-to-Computer tier. A network in this tier is
characterized by a very high data rate, 50 to 100 Mbps.
Solutions for this tier take the fonn of loops or rings
and even fiber optics. An example of this type of network is Network Systems' Hyperchannel.

231194-1

Figure 1. Three Tier Network Model

8-97

231194-002

inter

AR-346

The tiered network model is analogous to a road system. Tier 1 is the 10 lane freeway in a major metropolitan area. This highway is responsible for moving very
large volumes of traffic. This type of highway· is very
expensive to build, but the traffic volume warrants it.
Tier 2 can be thought of as an Interstate Highway in
which a large amount of traffic can be transported over
long distances. Tier 3, or the Human Interface tier, can
be thought of as the streets within a city which interconnect onto the interstate highway. In this scheme, no
single user has a freeway butting up to his driveway; in
a similar fashion no user is connected to a Tier 1 network. This tiered approach maximizes the performance
of Tier 2, because most of the Tier 3 traffic stays within
Tier 3; just as farm tractors primarily stay on dirt
roads, not super highways.
Another way to view the model is to draw an analogy
to microprocessors. To meet the requirements of diverse applications there are 4-bit, 8-bit, l6-bit and 32bit processors available. Nobody questions that a 32-bit
microprocessor is overkill for a microwave oven. In' a
similar fashion no single network can cost effectively
solve the problems of each networking need. It is
through this tiered approach that users achieve the best
cost/performance ratio for moving vehicle traffic.

Applications and Tiers
This model can be mapped into application performance requirements found in the office. Figure 2 shows a
graph of cost and performance for various applications.
Experience has shown that end users are willing to pay
no more than 10 to 15 percent of their system cost in
order to obtain data communication capability; this
percentage is an important assumption.

At the lowest end is the terminal and personal computer requirements. This application space spans a wide
spectrum of performance requirements. At the low end,
data entry can tolerate very low data rates with not
much performance degradation, and consequently is
the most cost sensitive. Using modems as a benchmark,
users are willing to pay upwards to $45.0 for a 1200 bps
serial connection. At the higher end, resource sharing
and graphic requirements for PCs require in the range
of 1 Mbps. Popular personal computer LANs cost $500
to $1000 per connection (not including wiring cost) ..
Networking at Tier 3 provides an overall lower cost
solution because the cost of the network is less than the
cost of each user having his own peripheral. This observation is validated in that a major trend in the market
place today is diskless workstations.
It is the wide range of personal computer and terminal
data rate requirements that· make the Tier 3 the most
interesting. It is possible for a user to spend too much
for performance he will not use. In fact, for personal
computer networks, bit rate is not the major limitation,
rather it is the restrictions of electro-mechanical peripherals such as Winchester disks and software overhead
on the local CPU that cannot keep up. with 1 Mbps
continuous (as opposed to bursty) data rates.

_Evolution Scenarios
Two scenarios have been developed to explain how a
tiered 'network will be realized in the real world. Scenario 1, the local optimization scenario, assumes that
departments within an organization will make their
.
networking decision in .isolation.
In this scenario the particular application requirements
of a department are very well known. -For example, an
Engineering department has very high data rate requirements to support its CAD environment; whereas
Sales has low data rate requirements for their order
entry and order inquiry needs. Because the applications
are well known, a decision can be made quickly on
which network to purchase. Departmental budgets usually can cover the costs of these networks, so approval
of a higher authority is not required. The result is that
each department will develop its own cluster network
(Tied).

Application data rate requirements can be placed into
three groups analogous to the three tiers of Figure 1. At
the very high end is the computer-to-computer communication requirements, in which end users will spend
$50k to $60k per connection.
At the high end is the CAD/CAM user requirements in
which very expensive· peripherals such as electrostatic
plotters and disks need to be shared. The cost of an
Ethernet connection, $lk to 1.5k, is very affordable at
this tier.

8-98

231194-002

inter

AR-346

OFFICE APPLICATION PERFORMANCE
SPECTRUM
TIER 1:
MAINFRAMES

1000X

RELATIVE
NETWORK
CONNECT
COST

100X

10X

TIER 3: PC AND TERMINALS

-DATA INQUIRY

1X~

1K

______

~

10K

______

~

______

100K

~

______

1M

~L-

10M

______~.

100M

BIT RATE (BPS)

Figure 2. Application Performance Spectrum
However, over time many departments will develop
their own cluster tier; each department will realize they
have a need to interconnect among each other. For example, the Marketing department may have to access
cost information from the Finance department as well
as last month's order rate from Sales. When cluster-tocluster communication requirements become important, the company will make a conscious decision to
provide interconnect capability. This interconnect capability is realized through the LAN Backbone. A
growing concern is whether gateways/bridges will exist. This concern leads to Scenario 2.

networking requirements at one time. In this scenario,
the decision is centralized because it impacts the entire
operation or company. The advantage of this approach
is built-in compability to interconnect the users. However, at this time the decision can be very difficult because the technology is not stable, and user requirements are not fully understood.
In this scenario the Tiered Network model predicts that
clustering will occur as well. For example, it will not be
cost effective for each user to connect onto an Ethernet
cable ($1500 cost). Thus, each department will have a
cluster optimized for its particular application interconnecting through a LAN Backbone.

Scenario 2, the global optimization scenario, occurs
when the users make a conscious decision to solve their

8-99

231194-002

inter

AR-346

greater efficiency and bandwidth utilization and
shorter delay in getting the message to its destination.
3. Reliability. The CSMAlCD media access method
enables the network to operate without central con. trol or switching logic. If a station on the network
malfunctions, it does not affect the ability of other
stations to intercommunicate.
4. Easy expansion. The passive, distributed nature of a
CSMAlCD network permits easy expansion. Stations can be added to the existing network without
reinitialization of all the other stations. Such capability supports future growth requirements through
simple expansion of the network.

To summarize, we can see that there is no single network that solves all user problems. Whether a user 0ptimizes locally or globally, clustering is likely to occur.
Each end user group will have a cluster that is optimized for its particular application requirements. It is
through this clustering with interconnection through a
LAN Backbone that end users will realize the most cost
effective network.

VLSI and the LAN Backbone
The IEEE 802.3/Ethemet standard has gained wide acceptance by a number of system suppliers. IEEE
802.3's popularity has been driven primarily by itsacceptance by major minicomputer manufacturers, the
approved IEEE specification itself, and the availability
of low cost VLSI Controller chips. From a technical
viewpoint, the IEEE 802.3 shares the benefits of Carrier Sense Multiple Access/Collision Detection, CSMAI
CD, technology. These benefits are:
1. Proven technology. Ethernet has been in use since
1975 by Xerox. The technology is well-understood,
and has resulted inthe IEEE standard.
2. Performance. E1imination of the centralized (or hierarchical) control network communicatiolis results in

Figure 3 shows the basic building blocks for an IEEE
. 802.3/Ethernet system and how it relates to the International Standards Organization (ISO) Open Systems
Interconnect model for networking. Basic components
consist of a coaxial cable for transmission media, a
transceiver to transmit and receive signals that come
over the media and detect collisions, a transceiver cable
to connect the data terIilinal equipment to the trans~
ceiver which allows flexibility of the location of the terminal, and a controller board.

DATA LINK LAYER

PHYSICAL LAYER

DATA LINK CONTROLLER

I

f--

PHYSICAL CHANNEL

I

ETHERNET CONTROLL!R BOARD

TYPICAL
IMPLEMENTATION

TO 110 BUS ETC.

231194-3

Figure 3. Ethernet Data Link and Physical Links

8-100

231194-002

AR-346

Today, Intel supplies VLSI for the controller board
function. Intel's 82586 LAN Coprocessor perfonns the
IEEE 802.3 data link functions without any CPU in-

While this approach is lower in cost than Ethernet, it
has two limitations. First, the segment length is restricted to 185 meters. For the office this distance limitation
requires the use of repeaters that increase the cost and
reduce system reliability. Second, the cable/tenninal
(ground) isolation scheme is the same as for Ethernet
which requires D.C. isolation between the transceiver
and the tenninal (because of ground). This isolation
scheme limits the potential cost reduction because it
does not allow integrating the transceiver, encoder/decoder and controller functions into a single chip. Ethernet/Cheapernet require DC/DC converters to the
transceiver.

volvement:
• frame assembly/disassembly
• handling of source and destination addressing
• detection of physical channel transmission errors
• CSMA/CD network link management
-collision detection
-backoff and retransmission after a collision
In addition the 82586 supports the designer with dillgnostic capability to make system design easier. For example DMA underrun and overrun errors, frames that
are received in error, and number of deferrals are re, ported. Loopback capability is allowed to facilitate self
diagnostics. These capabilities are perfonned without
any involvement from the host cpu.
Intel's 82501, Ethernet Serial Interface, perfonns Manchester encoding and decoding of the data and timing
information.
'
More details on operation and design support capabilities of the 82586 are included as an appendix to this
paper.

VLSI For The Human Interface Tier
From a technology viewpoint, the Human Interface
Tier is an interesting one. Traditional computer manufacturers and PBX manufacturers are providing solutions that leverage their traditional strengths. Computer manufacturers are providing solutions via LANs
based on their data communications expertise. PBX
manufacturers, on the other hand, are beginning to offer voice/data PBXs. While these are two competing
technologies, both suppliers realize they do not have
the complete solution. Minicomputer and PBX manufacturers have cooperated in developing the standard
"Computer-to-PBX" interface. These technologies are
discussed in greater detail below:

Cheapernet
Within the IEEE 802.3 committee is a subgroup defining a lower cost version of Ethernet called Cheapernet
(also known as Thin Ethernet or Skinny Ethernet).
Cheapernet maintains Ethernet's 10 Mbps data rate, but
cost is reduced through a lower cost cabling scheme.
Ethernet's yellow cable, cable tap box, and transceiver
drop cable are replaced by low cost R058 CATV coaxial cable. The Ethernet transceiver function is located
within the tenninal itself. The coax cable is attached
directly to the tenninal through a T-connector. Installation does not require a specialized craft person to install.

1 Mbps CSMA/CD LAN
Today there are a number of personal computer network products that are unique to a single vendor. These
networks lack the ability to electronically (physical
link) interconnect, much less have compatible software
link among other vendors. These networks are characterized by bit rates in the 1 Mbps area and are generally
of the CSMA variety. In an effort to see a standard
emerge in this area, Intel is working' with AT&T,
Wang, Tandem, Toshiba, and others to arrive at a 1
Mbps standard within the IEEE 802,3 committee.
1 Mbps networks offer a lower cost of connection than
do 10 Mbps networks. First, cabling cost can be reduced by using low cost CATV coax, or twisted pair
wire. Second, the length of cable segments can be much
greater for 1 Mbps than in 10 NI;bps technologies: going
from less than 200 meters in Cheapernet, to 500 meters
for Ethernet to over 1000 meters for I Mbps CSMA/
CD. Longer cable segments mean few repeaters are
needed on the network. Third, is that,l Mbps networks
allow VLSI interface costs to be reduced significantly.
For 1 Mbps networks, it is possible with available technology to cost effectively integrate the controller function with the serial interface function and the transceivers into one chip. This level of integration is not
achieveable in Ethernet/Cheapernet networks because
the transceiver chip and serial interface chip are electrically isolated through transfonners as mentioned
above.
A concern is that 1 Mbps may not offer adequate perfonnance for personal computer applications. The perfonnance of 1 Mbps networks, such as Omninet and
PCnet, is not limited by the serial 'bit rate, but rather
electro-mechanical peripherals, particularly Winchester
disk access time. Network perfonnance (as measured
by the time required for many users to' down load a
common file) can be significantly (3-4X) improved by
using "RAM Disks" within the file server. RAM Disks
are really extensions of the file server's local RAM
memory that can hold commonly accessed files (such as
a spread sheet program or BASIC language). Several
personal computer network vendors already have these
products available.
'

8-101

231194-002

AR-346

1 Mbps CSMA/CD networks can be cost effectively
realized using the. 82586 LAN Coprocessor from Intel.
The 82586 is unique among present LAN controllers in
that data rates and CSMA/CD network parameters
(slot time, back-off priority, framing, etc.) are programmable. This programmability allows the 82586 to be
used as a 1 Mbps controller. The advantage of this approach is that software developed for Ethernet workstations can be immediately transferred to 1 Mbps networks because the system interfaced to the 82586 remains the same. Available 1 Mbps Manchester encoder/decoders and a low cost discrete transceiver complete the 1 Mbps physical interface. Future cost reductions can be realized by integrating the controller and
Manchester encoder/decoder and transceiver functions
onto a single chip.

Intel currently offers a family of components specifically designed to facilitate the design of voice/data PBXs.
At the heart of the ·system is the 2952 Integrated Line
Card Controller. This device supports 8 analog or digital subscribers simultaneously. It includes an.interface
to 2 PCM highways and 1 HDLC control highway.
Analog subscribers interface to the 2952 through the
29C51 high feature CHMOS combo. The combo embodies both PCM codec and anti-alias filter functions
on chip. In addition, integrated signaling· test and line
balancing are performed by the 29C51. Fuiure products
will allow PBX manufacturers to easily upgrade their
2952 based products to include true two wire voice/
data subscribers.

Conclusion
Voice/DataPBX
Many PBX manufacturers are touting voice/data capability. This capability usually takes the form of four
wire systems in which voice and data are carried over
separate twisted wire pairs. The data rates generally are
19.2 kbps or 56 kbps, depending on the asynchronous
and synchronous nature of the data. Fourth generation
PBXs, some using two wires, are beginning to enter the
market now and will continue through the 1980's. Even
these products have data rates ranging from 64 to 128
kbps, although 256 kbps for data is talked about. These
data rates are adequate only for the Human Interface
Tier.
Presently PBX manufacturers are focusing on the terminal application .market as indicated by the numerous
IBM 3270 interfaces offered. A 19.2 kbps data rate is
more than adequate for data entry, data inquiry and
editing applications. It is not clear whether this data
rate is adequate for personal computers. Certainly for a
personal computer working in an editing type environment, this performance is adequate, The PBX may not
be adequate for applications that require heavy use of
file access, file transfers and graphics.

There is no single local area network that meets every
user's needs cost effectively. IEEE 802.3/Ethernet offers users a high performance Local Area Network suitable for a LAN Backbone, but it is too costly for personal computer and terminal networking. 1 Mbps networks and voice/data PBXs solve this problem. At
present, Intel's 82586 LAN Coprocessor is the only
VLSI chip that solves both Ethernet and 1 Mbps LAN
requirements while simultaneously maintaining software compatibility from the system point of view. In
the future it can be expected that LAN controllers optimized for 1 Mbps networks that include on chip encoder/decoder and transceiver functions will appear.
Intel also offers a family of components to facilitate the
realization of voiCe/data PBXs. .
In the long run,.office networks will be stnictured into
department clusters that will be interconnected through
a LAN Backbone or PBX. The ultimate choice will be
related to application performance requirements.

References:
1. LAN Components User's Manual Iniel Corp. Order
Number: 230814-001
2. Telecommunication Products Handbook Intel Corp.
Order Number: 230730-002

8-102

231194-002

inter

AR·346

APPENDIX A
INTEL LAN SOLUTIONS
Intel offers a broad range of products to realize LANs.
These products are in the form of components (82586
and 82501), boards (iSBC 186/51), and network software (iNA 960). See Figure A. A functional summary
of components and software solutions is below:

The 82586 LAN Coprocessor
The 82586 is an intelligent peripheral that completely
manages the processes of transmitting and receiving
frames over a network. It offioads the host CPU of the
tasks .related to managing communication activities.
More importantly, it does not depend on the host CPU
for time critical functions (e.g. transmission and reception of frames) because it contains its own processor
allowing it to be a coprocessor along with the host
CPU.
The 82586 interfaces easily to available microprocessors. Systems requiring minimum component count can
take advantage of its direct interface (no 'TIL glue') to
Intel's 80188 (8-bit bus) and 80186 (16-bit bus) microprocessors.
The 82586 efficiently uses memory through data chaining. System memory is not wasted because short frame

I

NElWORK
MANAGEMENT

(75% of network traffic is less than 100 bytes) can be
saved in minimal size buffers, while long frames are
stored by successively chaining buffers together. It
manages this chaining process without CPU intervention, thereby maintaining high system performance.
The 82586 facilitates network management by maintaining error tallies in system memory to count:
- Number of frames incorrectly received due to CRC
errors
- Number of frames incorrectly received due to misaligned frames
The 82586 counts number of collisions that occurred
while attempting to transmit a specific frame which is
an indicator of traffic loading. It also monitors the
transceiver's collision detection failure reporting mechanism.
The 82586 assists in developing and maintaining LAN
systems by maintaining tallies that count the:
- Number of frames lost due to lack of receive buffers
- Number of frames lost due to DMA overrun while
receiving frames

I

,-

APPLICATION

PRESENTATION

SESSION

INTEL iNA 960,
TRANSPORT SOFTWAREJ
NElWORK MANAGER

INTEL 82586.
LAN CO·PROCESSOR
INTEL 82501. ETHERNET
SERIAL INTERFACE

-{

r--

TRANSPORT

~

NElWORK

--{

~

OATALINK

----[

-----

} - I S O 8073

IEEE 802.31
} - ETHERNET
PHYSICAL

231194-4

Figure A. Intel LAN Solution

8-103

231194-002

inter

AR·346

The 82586 provides diagnostic capability via internal
and externalloopback service. Distance to cable breaks
and shorts is provided by on-chip time domain reflectometry.
The 82586's network parameters are programmable so
that LANs optimized to specific applications can be
realized; for example: broadband networks, short topology networks that require higher throughput than
IEEE 802.3 and low cost (1 Mbps) networks.

Network Management Services
The Network Management facility supports the users
of the network in planning, operating and maintaining
the network by providing network usage statistics, by
allowing the monitoring of network functions and by
detecting, isolating and correcting network faults.
The Network Management facility also supports upline dumping and down-line loading of data bases or to
boot systems without a local mass storage.

The 82501 Ethernet Serial Interface
The 82501 is designed to work directly with the 82586
in 10 Mbps LAN applications. The primary function of
the 82501 is to perform Manchester encoding/decoding, provide 10 MHz transmit and receive clocks to the
82586, and to drive the transceiver cable. The 82501
provides for fault isolation via an internal loopback.
Continuous transmission (babbling) is prevented by an
on-chip watchdog timer.

User Environment
In the iRMX (Intel's real time, multitasking operating
system) environment, both the user programs and iNA
960 run under iRMX 86. The communications software
is implemented as an iRMX 86 job requiring the nucleus only for most operations. The only exception is the
boot server option, which also needs the Basic I/O System. iNA 960 will run in any iRMX environment including configurations based onthe 80130 software on
silicon component.
'

INA 960 Transport Software
iNA 960 is a general purpose Local Area Network software package that provides the user with guaranteed
end to end message delivery. iNA 960 conforms to the
International Standards Organization's 8073 specification including up to Class 4 transport layer services.
iNA 960 also provides 'network management functions,
and 82586 device drivers.

In those systems where iRMX 86 is not the primary
operating system, or where off-loading ihe host of the
communicatons tasks is necessary for performance reasons, the user may wish to dedicate a processor for
communication purposes. iNA 960 can be configured
to support such implementations by providing network
serVices on an 8086, 8088, or 80186 microprocessor.

Transport Services
The iNA 960 transport layer implements two kinds of
message delivery services: virtual circuits and datagram. Virtual circuits provide a reliable point-to-point
message delivery service ensuring maximum data integrity and are fully compatible with the ISO 8073 Class 4
protocol. In addition to guaranteeing message integrity,
iNA 960:
- Provides flow control (data rate matching between
sender and receiver)
- Supports multiple simultaneous connections (process multiplexing)
- Handles variable length messages (independently of
physical frame size)
- Supports expedited delivery (to transmit urgent
data)
The datagram option provides 'best effort' delivery
service for non-critical messages. The datagram service
does not guarantee message integrity but requires less
channel overhead than virtual circuits.
231194-5

Figure S_ Intel LAN Components
8-104

231194-002

inter

ARTICLE
REPRINT

AR·342

September 1984

Chips Support Two
Local Area Networks

BOB DAHLBERG

.LAN Component Product Line Manager

Reprinted with permission from May, 1984 Issue of Computer Design,
Copyright ©, Penn Well Publications

8-105

Order Number: 231208·001

CHIPS SUPPORT TWO
LOCAL AREA NETWORKS
Data communication ICS permit easy implementation of
Ethernet and high level data-link control networks.

by Bob Dahlberg
The main rationale for local networks is resource
sharing. Today, small, powerful computers using
VLSI components sell for less than $2000. Under
the circumstances, companies intending to use
several such systems are reluctant to equip each one
with a disk drive and printer that could more than
double the price per station. Rather, they prefer to
share disks and printers among several systems in
order to spread tlie cost of peripherals across
several users.
By connecting these small computers to a local
area network (LAN), resource sharing with little
degradation in overall system performance
becomes practical. However, if the network interface costs $1000 or more per computer, the
economic advantage of resource sharing wanes.
Thus, network interface cost is a primary criterion
in selection, particularly for low cost computers.
Access methodologies represent another important factor in network selection. And, although an
equal access, first-come, first-served method might
be appropriate for an office system environment, it
could be the curse of a process control system. In
the latter case, a priority-based (or controlled)
access method might be the only realistic choice.
Bob Dahlberg is a product manager responsible for
local area network components at Intel Corp, 3065
Bowers Ave, Santa Clara, CA 95051. He holds a BS in
electrical engineering and computer science from the
University of California, Berkeley, and an MBA from
the University of Chicago.
.

All else being equal, networks supported by available LSI and VLSI components exhibit cost and
development speed advantages over board-based
LANs.Now, available chips support both prioritybased and equal access schemes. One such network
is based on the IEEE 802.3 specification, while
another uses a variety of physical interface schemes
overlaid by high level data-link control/synchronous
data-link control (HDLC/SDLC) protocols.

Costly copper
In short distance networks, one can choose a
serial, two~wire scheme or a parallel, multiwire interface. Parallel bus structures are implicitly faster
than serial structures but tend to be more expensive
and less reliable. The amount and cost of the copper

COMPUTER DESIGN/May 1984

8-106

231208-001

inter

AR·342

(.)

(')

Fig 1 A multidrop configuration is the simplest means of
network expansion (a). Additional stations are connected
directly to the network cable, but some addressing method
must be used to avoid party-line reception by all stations.
HOLC/SOLC protocols provide a controlled-access technique
where a primary station controls all bus access and determines
which secondary stations respond to its commands (b).

wire are much greater, and the number of connections (inversely related to reliability) is also much
greater. Thus, the networks described are both
serial, two-wire types.
A fundamental assumption in data communications is that noise will corrupt the transmitted data.
Error detection schemes can be employed to determine the validity of received data. One common
data error detection method applies a numerical
algorithm to the message bit pattern and produces
a unique sum. This sum is appended to the end of
the message and is used by a receiving system as a
quick check for the proper bit pattern. Called a
cyclic redundancy check (CRC), this process permits'
a receiving station to discard erroneous data and
request retransmission. If the message frames are
sequentially numbered, the retransmission request
can be made specific to that frame to dispense with
the request for a larger group of data. Thus, the
process can be made more efficient.
As needs grow, users may want to add more workstations and intelligent peripherals to a network. It
would be ideal to attach each station to the network by simply connecting the station directly to
the serial network bus cable. This is called a multidrop configuration and it resembles a party line
telephone circuit [Fig l(a)]. As a party line, each
station attached to the cable receives all the data
transmitted on the cable. In, order to route
messages to their intended recipients, the messages
are logic switched, or specifically addressed, to one
or more receiving stations. All others will ignore
the data after learning that no match existed between
their addresses and those of the data being sent.
Each data packet or' frame contains a set of
address bits that determines which stations receive
the data. In a sense, address bits constitute overhead
because they are not part of the information being
sent between stations. Any loss in data transfer

efficiency, however, is made up by the simplicity of
the network expansion interconnect scheme.
The Ethernet specification (a modified version
of which was recently accepted as IEEE standard
802.3) describes its physical link characteristics in
full detail. Coaxial cable is used as the network
cable bus, and each station is connected to that
cable via a transceiver and transceiver cable.
Minimum distance between station transceivers is
2.5 m, and a network segment can extend to 500 m
(and contain up to 200 nodes). Because up to five
segments can be joined using active' repeaters between each segment,the overall Ethernet network
can be 2500 m long and support up to 1000 nodes.
Individual nodes can COnnect to more than one station, and the number of stations connected to an
Ethernet network can exceed 1000.
Data is sent at a 10-Mbitis rate using a selfclocking Manchester encoding format. Only one
data packet can be sent at a time using Ethernet,
and access is on a first-come, first-served basis.
Carrier sense multiple access/collision detection
(CSMAlCO) methodology is used. The maximum
and minimum distances between transceivers are
derived from the CSMAICO requirements based on
interframe-spacing and the collision detection
procedures.
A second alternative requires no specific physical
link. Speed, distance, and cost parameters dictate
actual implementation. The' simplest and least
expensive method is'to drive a twisted-pair cable
with off-the-shelf transceiver chips.
Choosing protocols
Both the IEEE 802.3/CSMA/CO and the HOLC/SOLC
protocols provide logic-switched messaging and
frame-by-frame error detection. IEEE 802.3/Ethernet
treats each station equally and does not permit
priority network access, whereas HOLC/SOLC
enforces a primary/secoridary hierarchy [Fig l(b)].
A primary station controls the overall network by
issuing commands to the secondary stations .. Secondary stations comply with the primary station's
commands and access the bus for retransmitting
data only in response to those commands. Unlike
Ethernet, which is based on probabilistic network
access, HOLC/SOLC provides deterministic (or controlled) access.
SOLC is an IBM standard communication protocol .
and a subset of HOLC, a standard communication
link control established by the International Standards Organization (ISO). HOLC and its subset are
data-transparent protocols, which means the ,arbitrary data streams can be sent without concern that
some of the data might be mistaken for control
characters. Thus," unlike the Bisync protocol and its
controller, an HOLC/SOLC controller need not
detect special characters except for the unique
opening/closing flag' bytes. Moreover, unlike an

COMPUTER DESIGN'May 1984

8-107

231208-001

inter

AR·342

check sequence. The destination
and source fields both contain 6
octets (8 serial bits), for a total of
48 bits. The type field contains 2
CLDSING
ADDRESS CONTROL
INfORMATION
fRAME CHECK
fiELD (A) fiELD (e)
fiELD (I)
fLAG (~
SEQUENCE (fCS)
octets. The data field can have as
VARIABLE LENGTH
few as 46 octets or as many as
(ONLY IN INfORMATION fRAMES)
1,500. Finally, the frame check
sequence consists of 4· octets,
allowing a 32-bit CRC code to be
calculated and appended to the
Fig 2 The prescribed format for HDLC/SDLC frames consists of four basic fields
rest of the frame. The first transbounded by opening and closing fiags. This avoids the need for start/stop bits
mitted
Ethernet frame is preceded
often used in asynchronous protocols.
by a 64-bit preamble, made up of
asynchronous protocol and its controller, the HOLC/ seven groups of 10101010 followed by an eighth
SOLC need not provide start and stop bits.
group of 10101011. The next bit that follows is the
Both HOLC/SOLC and Ethernet protocols specify first bit of the first destination octet.
particular message formats (or frames). The
In the CSMA/CO scheme, a "collision" occurs
HOLC/SOLC protocol consists of five basic fields- when two stations attempt to gain access to the bus
flag, address, control, data, and error detection. at the same time. Thus, it is important that all staEach frame is enclosed by an opening and closing tions on the network are notified of the collision.
flag. Both the opening and closing flags form a This way,· any transmitted data can be flagged as
similar bit sequence-olllilio-that is an indi- invalid. To solve this problem IEEE S02.3/Ethernet
vidual character in SOLC/HOLC. Inserting a 0 in the specifies that, after collision detection, transmitting
informatio~ data flow whenever a sequence .of five stations send a jam signal to ensure that stations on
I s occurs achieves flag character individuality in the network recognize the collision. At the end of
SOLC/HOLC. These inserted 0 bits. are automatically the jam interval, each station delays bus access
stripped out upon reception. For SOLC, the address according to an individually calculated random
field is 8 bits wide, but can be 2 (or more) bytes backoff time interval. Should a collision occur
long in HOLC. Similarly, the control field in SOLe is again when bus access attempts are renewed, the
8 bits wide, but can also be longer in HOLe. The next backoff interval increases in length. Up to 16
SOLe data or information field can contain any repeated attempts can occur before a system fault
number of bytes. However, the. same is true for is automatically assumed. Thus, even during
HOLe in certain instances where the data field must periods of high bus demand, ample bandwidth
end on an 8-bit boundary. Finally, the frame check should be available and delays relatively short.
sequence field contains the 16-bit eRe result for all
It's in the chips
of the bits between flags (Fig 2).
Any of the working LANs can be implemented
Three types of frames are used in HOLe and
SOLe. A nonsequenced frame establishes initializa- using various components. If there is enough time
tion and control of the secondary stations. A and a large budget, custom VLSI chips. can be
supervisory frame handles control, and an information frame is used for data transfers.
PHYSICAL/MUlTICAST BIT
The SOLe protocol appears in low cost asynDESTINATION
60CTETS
chronous modems using nonreturn to zero inverted
(NRZI) coding and decoding. NRZI coding is used at
60CTETS
SOURCE
the transmitter to enable clock recovery from data
OCTETS WITHIN
20CIETS
TYPE
at the receiver terminal. Clock recovery is accomfRAME TRANSMITTEO
TOP TO BOTTOM
plished using a digital phase locked loop technique.
DATA
46 to 1500 OCTE TS
NRZI coding specifies that the signal condition does
not change for transmitting a I, but changes state
fRAME CHECK
whenever a 0 is transmitted. Hence, NRZI coding
SEQUENCE
40CIETS
ensures that an active data line will have a transition at least every 6 bit times (by virtue of the O-bit
LSBIIIIIIIIIMSB
insertion requirement). Both.O-bit insertion and
l OCT:;T;R~~~~:;TEO ...
NRZI coding/decoding maintain the data
lEfT·TO·RIGHT
transparency characteristics of the HOLe protocol
Fig 3 Each Ethernet frame consists of five fields.
and its SOLe subset.
Like HOLe/SOLe, Ethernet specifies a frame for- Destination and source fields indicate where the message is
mat (Fig 3). It .contains a destination field, source going and from which station it originated. The data field
can contain as few as 46 bytes of data and as many as 1500.
field, frame ty~e field, data field, and a frame

1-1 Dcm--i

I

COMPUTER DESIGN/May 1984

8-108

231208-001

AR·342

developed and an elegant solution forged. Most
engineers, however, have neither luxury. For this
reason, the two networks. selected are supported by
off-the-shelf VLSI components.
Intel's 8273 and 8274 data communication controller
ICs offer HOLC/SOLC capabilities. Teamed with a
microprocessor and some random logic ICS, a
capable network data-link controller could be
built. The 8051 single-chip microcontroller has
become a popular component for many terminal
applications because of its high performance 8-bit
cPu, large internal program and data memory
capacity, plus onchip counter timers and interrupt
controllers. In addition, Intel has combined an intelligent HOLC/SOLC controller and 8051 core processor
onto a single chip, the 8044. The resulting singlechip microcontroller with onchip serial communication controller allows low cost network terminal
and peripheral design.

CONTROL
LINES

HOle/SOle
PORT

Fig 4 The 8044 combines an 8051 CPU, program and data
memory, plus HDLC/SDLC controller on a single cbip to build
a simple, low cost network station or peripberal.

Each station would contain an 8044 (with its programmable 110 ports to provide local control) and
serial HOLC/SOLC interface. Thus, to manage the
network interface, 8044-based stations would be
capable of acting as a secondary station within an
HOLC/SOLC network (Fig 4). Since data transfer
speed and electrical characteristics are not specified
for these protocols, the designer has a wide choice
in tailoring the physical link to the application. The
single VLSI device provides local intelligence and
network management, thus permitting low cost network development.
Various Ethernet controllers have been announced, with several already sampled and available. Among these is the 82586 general-purpose
CSMAICO controller. It is designed to come up in
the Ethernet mode on power up, but can be programmed for other parameters as well. A companion chip (the 82501) provides the Manchester
encoding/decoding function between the 82586 and
a transceiver.
This chip pair operates in conjunction with the
iAPX 86 microprocessor family, and is most costeffectively used with the 80186 microprocessor. The
80186 and 82586 have identical bus interface and control signal requirements. Hence, they can be linked
without adding random logic ICs. Essentially, these
three ICs-the 80186, 82586, and 82501-provide the
basis for an Ethernet interface. Therefore, only

some buffer memory and bus interface chips are
additionally required (Fig 5).
A subsystem built using these components provides an intelligent Ethernet interface that can continuously operate at the full lO-Mbitis network
speed. Moreover, these components can implement
a complete computer and communication system.
If is therefore possible to create an appropriate and
usable Ethernet workstation out of these few VLSI
components.
Different strokes

The HOLC/SOLC-based network is intended for
non-Ethernet applications. HOLC/SOLC has
become an accepted standard supported by a variety
of hardware and software products. There is no
specified standard for physical link implementation or for the software layers beyond the data-link
level. Therefore, networks based on these protocols are usually "closed." That is, the vendor
provides all the pieces to the network. Vendors, of
course, are familiar with their own network architecture and are free to provide compatible systems.
But such networks do not encourage others to
develop compatible systems unless the vendor's
market share is large enough and vulnerable
enough to attract competition. The IBM SNA is an
example.
HOLC/SoLC-based LANs are suitable for system
clusters where distances are less than those of
Ethernet, and where priority access is important.
Networks within a box (eg, a copier), and networks
on table-tops (eg, an instrumentation cluster), are
examples. Although there is a parallel bus interface
standard (IEEE 488), an instrumentation manufacturer may want to provide for longer distances using
two-wire cables and simpler protocols.
An HOLC/SOLC LAN cluster could also be used for
process control applications and data acquisition
systems. An example is Intel's recent distributed
control module products for the factory. Again, a
priority bus access capability would be important
in these applications. Office system applications
where Ethernet offers too much performance at too
high a cost (eg, an electronic typewriter networked
to a file server) might use this network as well.
The concept of open-system compatibility comes
from the ISO's Open System Interconnection (OSI)
model. This provides a seven-layer model in which
each layer is characterized by a unique set of functions and a specific interface to adjacent layers.
The goal is to eventually arrive at a set of standards
that would permit systems from several vendors to
communicate with one another through common
physical, data-link, and software layer protocols.
Xerox Corp developed Ethernet as a local network
for its systems, but the company later joined with
Digital Equipment Corp and Intel to develop a set
of specifications for Ethernet that would allow it to

COMPUTER DESIGN/May 1984

8-109

231208-001

AR·342

80186

HOLO ~ HOLO
HOLO A ~ HOLO A
CLOCK OUT
CLOCK
R£S£T OUT
R£m
INTO
PC50

AOOR£SSli

----

----

l}ATA

825B6

INT
CHANNEl
ATT£NTlON

AOOR£ssll

TXO

TXO

TRANSMIT

m

iXf

RXO

RXO

TRANSMIT
R£C£IV£

m

RXC

Wi
C1lS

COT

R£C£IVE
COLLISION

CRS

COlliSION

1m

T£N

82501

TRANSC£IV£R

TO
HH£RNH
CABL£

r--

11

0m

MULTIPL£XfO BUS

n

Aoo11

ADORESS
LATCHES

I l

jaATA
OATA
TRANSC£IVERS

I

n I1
ROM

J
11

1

OATA11
SYSTEM BUS

I

tOOR£SS OAT{

RAM

1I

kESS

Fig 5 A combination of 80186, 81586, and 82501 chips completes the logic needed for a fully functional Ethernet
interface. Data bus interface chips and some memory complete the Ethernet subsystem.

map into the first two layers of the OSI modelphysical and data -link. The IEEE adopted its 802.3
specification as a result of these efforts. Efforts to
develop standards for the other layers continue. An
example is the ISO transport layer' protocol, 8073,
which provides "return receipt" quality communication services.
Today, Ethernet supports OSI physical and data
packet level protocols. It is an emerging technology
that is still closer to the top than to the bottom of
the learning (and pricing) curve. Nevertheless,
many vendors support Ethernet and will no doubt
manufacture products equipped to swap data with
other Ethernet systems.

Open and closed
Office automation constitutes the biggest apparent
application area for Ethernet. The office has tradi.
tionally been a multivendor site in which the computer, copier, and printer are likely to come from
different vendors. An open system appeals to users
seeking vendor independence.
When the LAN concept was first proposed, it was
described as an all-encon;J.passing network, connecting all the intelligent subsystems throughout a
facility. In fact, that is not the way local network
installations have progressed. Instead, clusters of
user stations (typically 10 or so) are cropping up in
various places within a facility. Most analysts expect
local networking to occur in tiers. The cluster tier
provides the lowest cost per connection. An example
is a I.Mbitis CSMA/CD LAN used for personal computers. Clusters would be interconnected through a
longer and faster data highway (called a LAN backbone) such as Ethernet.

Will closed and open networks be able to cooperate and coexist? Quite simply, they have to. Economics will determine the network types used for
connecting the systems within a cluster, and
standardization will drive the methods by which
clusters are ultimately joined.
Closed systems, such as microcontrollers connecting the HDLC/SDLC-based network, represent
the least expensive and most flexible LAN configuration. Open systems, because of the push for standardizationand subsequently larger user base,are
more likely to benefit from future cost reduction
through multiple-sourced VLSI components than
closed systems. Similarly, open systems probably
attract more third-party suppliers and enjoy
greater variety and lower cost software.
Gateways will join closed and. open systems.
These hardware/software intermediaries will pave
the way for data transfer between formerly incompatible networks. By such means, a closed engineering workstation network will gliin access to
information stored in the corporate data base and
be available on the Ethernet data highway.

COMPUTER DESIGN/May 1984

8-110

231208-001

APPLICATION
NOTE

AR-405

"Intel Corporation, 1985
8-111

Order Number: 231309-001

Low-cost, dualdesi de

highpe
tions of the. memory. For example, a LAN coprocessor
can receive a frame from'the network and store it in a
given memory location while the CPU simultaneously
services a request from a graphics controller, operating
on a: different portion of the memory.
You might expect such a dual-port memory architecture to be expensive. Yet the devices used for bus
arbitration in this design include only 10 to 12 SSIIMSI
chips. The circuit, without the CPU card, occupies
approximately 36 in. 2 of board space. The estimated
cost of the board, components, and connectors is less
than $75, not including the cost of the 82586 coprocessor
Sikandar Naqvi, I~tel Corp
and 82501 serial-interface chips.
Although they provide better performance than do
Fig 2 shows a block diagram of the dual-port system
single-iAP systems, conventional shared-memory sys- design. The design incorporates the same dual-procestems offer you a limited choice. One kind of convention- sor 82586 LAN communication processor/80186 CPU
al shared-memory system allows. simultaneous !J.p' ac- architecture that can be used in any conventional
cess to the same RAM location, by using expensive shared-memory design to handle asynchronous serial
arbitration logic to eliminate bus contention. The other data and high bandwidths. The additional logic needed
allows iAP access to the same bank of RAM, but at for bus arbitration, address multiplexers, and data
different times: Only one of the iAPs can operate on the multiplexers may result in a chip count that's slightly
memory at a given instant. This restriction may confine higher than that of a similar shared-memory design,
system throughput to levels that are unacceptable in but this dual-port implementation is still relatively
high-performance workstation applications.
inexpensive. Furthermore, this dual-port design also
eliminates bus-latency problems for the LAN coprocesDual-port architecture
sor(see box, "Intelligent LAN coprocessor").
In any !J.P-based system, the CPU is of' critical
One dual-port design for an Ethernet workstation·
(Fig 1) offers a simple solution to the limitations of importance in determining system performance: The
conventional shared-memory de~igns: It allows the maximum speed at which the CPU performs bus transprocessors to operate simultaneously on different por- actions eventually' affects system throughput. For ex-

This dual-ported RAM design for Ethernet
workstations lets two JJ1's operate
simultaneously on different portions of
system memory. The result is high
performance and low cost in the same
system.

EDN ~uary 24, 1985

8-112

This dual-port design· allows the processors
to operate simultaneously on different
portions of the memory.

TABLE 1- RAM COMPARISON FOR THREE

DUAJ..PORT MEMORY SCHEMES
DYNAIIIC
RAllo

IIOIIOUIHIC

DUAWOIIT
RAllo

STATIC
RAllo

MEDIUM

MEDIUM

ample, an 80186 CPU operating at an 8-MHz clock rate
offers It maximum bus-transaction capacity of 4M bytes
. per second, assuming there are no wait states.
The size of the dual-port memory is a function of the
application it serves. Some of tl)e factors that influence
memory size are serial data load, packet sizes, and the
number of peripherals on the bus. Likewise, your
application determines whether dynamic or static RAM

Ft;l

chips are more cost effective; that is, your choice of
static or dynamic RAM depends largely on the size of
the memory, system-performance requirements, and
cost constraints.
For example,. for system applications requiring large
dual-ported RAM, dynamic RAM chips may be more
cost effective. In such a case, you must use a dynamic
RAM controller (like the 8207, for example) to refresh
the RAM and provide arbitration between the two jIl>s.
Static RAM is faster than dynamic RAM, and it provides better performance, so it's more expensive. However, if you use static RAM, as in this design, you must
use read and write signals for chip-select generation to
avoid bus contention between the chip-select and write
signals. (You must use the signals because static RAM
devices don't have separate output-enable inputs.)
Table 1 compares different kinds of RAM for various
dual-port schemes.
Fig 1 shows the low-cost, high-perforinance dual-port
design in detail. The 80186 is the CPU; the 82586

TAU dJuIl.port de.... uses an 80186 CPU a~ an 8$581t Etlumiet intmface tIw.t 81uJre 8k bytes of statU: RAM.

8-113

EDN .imuary 24, 1986

Intelligent LAN coprocessor
The 82586 is an intelligent, hlghperformance, c8rrier-senSe/multiple-access LAN. coprocessor
with collision detection (CSMAI
CD). The 82586 performs all
functions associated with data
. transfer between user memory
and the network: framing, link
management, address filtering,
error detection, network management, on-chip DMA, command and data chaining, and interpretation of high-level
commands from the host CPU.
Furthemiore,the 82586 interfaces with the 80186 without any
"glue logic."
The 82586 coprocessor relieves
the CPU of most tasks associated with serial link management,such as carrier sensing,
deferring to a passing frame,
starting transmission after wait-

ing for the interframe spacing,
automatically terminating transmission when a collision occurs,
retransmitting data after a collision, and randomly selecting
which data burst will be transmitted after a collision (random
back-off).
The coprocessor also meets
the requirements' of the IEEE
802.3 specification: It performs
bus tl'ansfers at a maximum rate
of 4M bytes per second, and it
can tolerate bus latency of more
than 10 ....sec without losing
data.
Wit1!out sacrificing the device's compliance with IEEE 802.3,
you can program the 82586 for a
wide range of CSMAlCD-type
LANs, such as the 2M-bps
CSMAlCD broadband (for IBM's
PC Network), serial backplanes,

provides the Ethernet interface. (The 82586 is a standard 10M-bps serial interface. Its transmit and receive·
clocks are provided by the 82501 Ethernet serial interface chip, which uses a 2O-MHz antiresonant crystal as
its clock source. The 82501 also provides the Manchester encoder/decoder functions.) The 80186 and 82586
.....Ps share a dual-port memory of 8k bytes of static
RAM. Because the memory is small, the circuit uses·
static RAM instead of. dynamic RAM. Although this
approach-uses more expensive memory components, it
results in a more economical design because you don't
have to refresh the chips as you would if· you used
dynamic RAM. The 8k bytes of RAM should be suffi.
cient for medium- to low-traffic networks; but you can
expand memory easily if you need to.
.
In this highly integrated system, the timers,' DMA,
and interrupt controller on the 80186 CPU are used for
additional UO transactions. The 8-MHz clock output of
the CPU can function as a chip clock for the 82586. The
dual-port design is oblivious to whatever signals are
driving the CPU interface and, in this example, all logic
to the left of the interfacebus (Fig 1) is on another

EDN January 24, 1985

8-114

1M-bps CSMAlCD, and Cheapernet. Because it's easy to program various chip parameters
(such as slot time, addresslength, and interframe spacing),
you'll find this chip useful in a
variety of applications.
The 82586 also features builtin diagnostic and -network-management capabilities. These include a time-domain
reflectometer, internal and externalloopback, transceiver integrity verification, self test and
internal register dump for diagnostics, and fault isolation. One
of the chip's network-management features is its ability to
collect network ~tatisti~, such
as number of collisions experienced, number of overrun errors, and number of alignment
errors.

card. The signals are transmitted via ribbon cable over
the LAN card. You can easily expand existing CPU
cards by sinlply providing a busip.terface to a LAN
card. The dual-port architecture also allows you to
modify this design for 8-bit CPU architectures or for
CPUs that use demultiplexed address and data buses.

Arbitration logic
The design's simple arbitration logic resolves jJ.P
contention for the dual-ported memory. The arbitration
logic operates in this manner:
• When the 82586 is accessing the dual-port memory, it inhibits the ready signal to the CPU by
generating a wait state through the arbitration
logic circuitry, thus preventing the CPU from
access to this portion of memory. However, the
CPU is free to access any other portion of the
system memory.
.
.
• The CPU can access the dual-port memory when
.
the 82586 is not accessing it.
• The 82586 gains control of the bus within foUr to
five clock cycles after a request. If the CPU was

Although the additional bus-arbitration
logic may result in a chip count slightly
higher than that of a similar design, this
design is still relatively inexpensive.

accessing the dual-port memory when the 82586
made the request, the CPU is put into wait mode.
The following shows the sequence of events when the
82586 requests the bus:
• The 82586 requests the bus by activating the hold
signal.
• The hold-acknowledge (HLDA) signal is activated
within five clock cycles.
• The 82586 disables the ready signal to the CPU
card.
• The 82586 disables the data buffers within four
clock cycles of the hold and isolatlls the CPU from
the dual-port RAM.
• The 82586 switches the multiplexer to the 82586
bus.
• If the CPU is accessing the dual-port 'memory
when the 82586 requests the bus, the 82586 gives
the CPU enough time to complete its bus cycle
and then removes the ready signal.
• When the 82586 removes the ready signal, which
places the CPU in the wait state, the CPU
remains in that state until the 82586 releases the
hold signal.
• When the 82586 has completed its bus access, it
restores the CPU ready signal and switches the
multiplexer back to the CPU, allowing the CPU
to resume its access of the dual-port memory.
The 82586 architecture· minimizes the bus-hold time
and improves system performance by writing data into
the system memory in small bursts of approximately 16
bytes each and giving the bus back to the CPU between
memory bursts. The 82586 also minimizes the need for
the CPU to intervene in most of the tasks related to a
serial data interface.
A simple scheme generates a ready signal
The ~esign uses a simple scheme to generate ready
signals. When the 82586 is holding the bus (hold active)
and either the read or the write signal is active, the
82586 ready signal is generated. When the 80186 is
accessing the dual-port memory and the· 82586 hold
signal is inactive, the dual-port memory card generates
the 80186 ready signal. The ready signals from other
memory blocks and peripheral devices are still available
to the 80186, so the 80186 can perform transactions
with other devices or memory on the system bus. In
fact, all the normally low ready signals to ~he 80186 are
connected by disjunctive (OR) logic.
Because the 80186 and 82586 use asynchronous
ready, it's simple to implement and use memories with

Fig Z-A tllPical dual·part sllstem design provides the additional
logic needed for bus arbitration. Although it has a higher chip count
than that of a conventionaI8hared-memory. design, thi8 implementation is relatively inexpensive.

different access times. This design uses zero-wait-state
memories. In the case of slower memories, you can
easily add a wait-state generator.
An important feature of the 82586. chip is that it
provides two 16-byte FIFO huffers: one for data transmission and one for data reception. Remember that
when the 82586 needs the bus, it activates its hold
signal and waits for the hold-acknowledge (HLDA)
signal before starting any memory-access cycles. (The
shared-memory design (Fig 1) shows the HLDA signal
to the 82586 coming from the 80186, the arbitration
logic.) The CPU will activate the HLDA after it completes its current cycle or task. Thus,~the duration of
the HLDA-to-hold delay depends on what activity the
CPU is performing at the time of the hold request.
Because the 82586 is serial and asynchronous, it must
be ready to receive incoming data at all times. The bus
latency (the delay between hold and HLDA) is a function of the bus architecture; an on-chip FIFO buffer
stores the incoming data until the 82586 can store it in
memory. A FIFO trigger mechanism on the chip lets
you program the bus request as you wish.
For example, assume that the receive FIFO trigger
is set at 6. (When the FIFO trigger is set at 6, the 82586
will make a bus request after the receive FIFO re-

8-115

EDN January 24, 1986

The dual-port architecture· also aJluws you
to modify this designfor 8-bit CPU
architectures or for CPUs that use
demultiplexed address and data buses.
ceives 6 bytes.) Because the 82586 must start emptying
the 16-byte-deep FIFO buffer before it is filled, to avoid
overrun the 82586 must acquire the bus within the time
it takes to store 10 bytes--8 l-LBec (or 64 CPU clock
cycles) at 10M bps with an 8-MHz clock rate. Depending on the application environment, it mayor may not
be easy to grant the bus to the 82586 within 64 clock
periods.
Nevertheless, the dual-port design in Fig 1 eliminates this kind of bus-latency problem. In this design,
the 82586 receives the HLDA signal within five clock
cycles of the hold request. This ensures that holdHLDA delays will be very short.
When the 8258~ tinally accesses the bus, it empties
the entire content of the FIFO buffer and stores it in
memory. The length of the burst of data depends on the
number ofbytes that are in the FIFO buffer when the
82586 gets the HLDA signal.' For maximum bus efficiency, the 82586 should acquire the bus with a full
FIFO buffer; the bursts should be 16 bytes long. A low
bus latency will allow you to set thEl FIFO trigger point
very ,high. Setting the FIFO trigger point high minimizes the hold-HLDA handshakes (which is desirable
because any 'hold-HLDA results in wasted bus bandwidth). The transmit buffer functions in much the Same
way as the receive buffer does.
EDII

References
1. "The Ethernet: A Local Area Network, Data Lirik
Layer, and Physical'Layer Specifications, Version 2.0," Digital Equipment Corp, Intel Corp, and Xerox Corp, November 1982.
2; LAN Components User's Manual, Intel Corp, March
1984, Order #230814-001.
3. Microsystems Components Handbook, Intel Corp,
1984, Order #230843-001.
'

Authpr's biography
Sikandar R Naqvi is technical market-,
ing manager for data communications
products at Intel Corp (Santa Clara,
CAJ. He holds an MSEE from Oregon
Strite University and a BSEE from the
Engineering University in Lahore, Pakistan. A member of the IEEE, he
enjoys tennis, raquetball, jogging, and
reading.

Article Interest Quotient (Circle' One)
High 473 Medium 474 Low 475
8-116

AR-371

DESIGN ENTRY
Monolithic controller
builds PC network
without toil or trouble
A controller chip puts CSMAICD within the reach
of personal computer networks, keeping a lid
on parts coun'tand simplifying software development.

O

ffice automation promises to dramatically boost productivity. Personal
computers are a step in that direction,
and a giant one at that, forming a base of
distributed intelligent machines. The next crucial advance is to link them in a network, so
that each machine shares peripherals and
information.
The 82588 is the first single-chip controller
designed to join personal computers over a local
network. Essentially a slave peripheral, the
chip is fitted with a CSMA/CD controller, two
logic-based collision detection mechanisms,
and an encoder and decoder for both nonreturn-to-zero inverted (NRZI)
and Manchester data encoding.
Adding a simple transceiver line

driver or an RF modem lets the controller implementall of the major hardware functions required by a local-area network.
Most of the chip's major duties, such as encoding and collision detection, can be programmed to meet the protocols of a particular
network. And although its flexible system interface allows it to be employed with any popular microprocessor, the controller is optimized
to work with the iAPX-186 and the iAPX-188
without TTL glue.
For the most part, local networks specifically
designed for personal computers suffer from
one of three major deficiencies. First, many are

Joseph Mazor and Robert Galin,
Intel Corp.
Joseph Muzo/' is u desiun malluuer for
local-(I/'eu n('( /i'Drk products ut Intel's
riesiun Clll/tl!/" in HUijll. Israel. He is (I
participatiliU member of the IEEE
110:2.3 1I!0rkinl/ f}l"oupjor J-Mbitls stUI'
net works a nd holds a BSEE ji'om
Technion. The Ismellnstitute oj Techno[ol/Y.
Since mid-1980 Robert Galin has been
planninu strateuy jar Intel's peripheral
components operation in Sunta Clara.
Calii He has (I masta's rief}l"ee in
enuineerinu ji'om the University of
Michiuan.

Reprinted with permission from Electronic Design,

Electronic D••ign • December 13, 1984

Vol. 32. No. 25; copyright Hayden Publishing Co .. Inc., 1984.

8-117

Order Number: 231530-001

intJ

AR-371

DESIGN ENTRY
Cover: PC network controller
proprietary, forcing users tobuy from one manufacturer. Second, with few exceptions, they
lack collision detection, and therefore limit a
network's efficiency for large offices (see "A
LAN for All Reasons," below). Finally, industry-standard networks were originally designed for minicomputers. Thus, they are too
expensive for personal machines. What is specifically lacking is an access scheme that is both
efficient and cost-effective. In the past, carriersense multiple access with collision detection
met the first requirement, but not the second.
Conversely, approaches like collision avoidance
meet the second specification but not the first.

In contrast, the controller was designed with
low-end systems in mind and makes possible inexpensive but efficient local networks in three
ways. For the OEM, it reduces component
count, board space, and development time. For
the end user, its 1- or 2-Mbitls data transfer
rate (lower than that of networks based on
minicomputers) allow the integration of controller, encoder-decoder, and collision detection
functions, which lowers component cost. Also,
lower bit rates imply cheaper, twisted-pair cabling that covers longer distances without expensive repeaters (Fig. 1).
The controller works with emerging stan-

A LAN for all reasons
The recent proliferation of personal computers
in the workplace has led designers to realize that
a single approach to local networks cannot answer
all needs. A network for engineering workstations
would be too expensive for personal computers.
Instead, a network needs to be built as a hybrid,
with portions within individual departments appropriate to the cost and performance needs of the
applications they serve (see the figure).
To that end, there are four separate-though
notcompeting-CSMA/CD network specifications in various stages of development. The first is
Ethernet, which with its 10 Mbits/s data rate is
best suited to local networks built around minicomputers or as a backbone connecting smaller
clusters of networked personal computers. Anoth-

er approach, dubbed Cheapernet, is a reduced-cost
implementation of Ethernet that works well with
personal comptiters in research and engineering
settings where 10 Mbits/s performance is necessary. A third approach, IBM's recently announced
PC network will connect personal computers that
are located up to 5 Km apart. Being a broadband
network, it has the advaritage that it can carry
several services (video and data) over a single
coaxial cable. Finally, Star Ian is a proposed IEEE
802.3 standard that is a 1-Mbitls baseband system.1t inexpensively links devices, such as personal computers, through already installed twisted
pair wires used for telephones. Its major use is for
the office·environment where low cost and ease of
wiring is extremely important.

Tier 1:Computer-lo-computer link
(20-100 MbllS/s)

Tter 2: Local network backbone
(2-10 Mblts/s)
Tier 3:
Workstation
cluster
(64 kbits/s-2 M~it9/s)

EllIClronlc o.llIn • December 13,' 1984

8-118

inter

AR-371

dards for personal computer networks like
American Telephone and Telegraph's StarIan
(I-Mbitls baseband) and the IBM PC network
(2-Mbit/s broadband). The controller also can
be coupled with an off-chip data encoderdecoder to handle up to 5 Mbits/s when higher
throughput is needed.
At your command

The IC communicates with a host using a set
of 16 high-level commands (Fig. 2). The Transmit, Retransmit, Configure, and Diagnose commands free the CPU from oVllrseeing every step
of each task that the controller undertakes. Instead, after the processor invokes a command,
it is free to take on other jobs. The high-level
commands simplify writing and debugging
software for the controller and the network.
Another of the controller's important features is its efficient memory structure for receiving frames. A network carries a large number of relatively short control messages, like
Open, Close, and Acknowledge, that direct its
operation. In fact, typically 75% of all network
messages may be less than 100 bytes long. As a
result, a storage system that breaks memory
down into large, equal-sized blocks would be
vastly inefficient. Each block would be able to
accommodate the largest possible framll but
would .be only partially filled most of the time.
The controller avoids this problem by using a
sophisticated approach that allocates multiple
buffers to a frame.
Rather than retain a frame in a single,
sequential block, the chip stores it in a number
of smaller buffers. A 100-byte buffer, say, could
hold a short frame, and multiple 100-byte buffers could store longer ones. To link individual
buffers; the host processor creates a chained
list of pointers that indicate where in memory
the data is held. This multiple-buffer approach
keeps the amount of memory needed to store
received frames to a minimum, an extremely
important consideration in personal computers, where RAM is at a premium.
Aboard the chip

, The controller itself consists of two main sections: a parallel system interface with the host
and a serial interface to the network. Two builtin 16-byte FIFOs, one for transmitting and one

for receiving,link the two (Fig. 3).
The first block consists of a bus interface unit
and a group of registers. The bus interface contains an 8-bit data bus. It is responsible for all
communications with the system CPU. In conjunction with an external DMA controller, the
new chip takes care of all reading and wri ting to
memory-at up to 4 Mbytes/s-as well as all
CPU interrupts. Two DMA channels are recommended, one for transmitting and the other for
receiving.
The parallel section also comprises three sets
of registers: one for storing configuration information, one for writing commands to, and one
for reporting the chip's status. To make rapid
changes in the controller's operating parameters, the processor enters a block of data into
RAM, and that data is loaded by DMA into the
registers (Fig; 4).
Serial side

The chip's serial interface contains the
CSMA/CD controller and converts parallel
data into serial form, and vice versa. It also assembles each frame as specified by the configuration registers, .computes the cyclic redundancy code (CRC) for each transmission, and

1. The 82588 local-area network controller connects
directly to a network (through a driver or modem)
without the need for an expensive transceiver tap.
Intended for relatively low data rates of 1 to 2
Mbit.,., the chip allows networks to be built with
twi.ted-pair wire. instead of coaxial cl!ble•.

Electronic D••ign • December 13. 1984

8-119

inter

AR-371

DESIGN ENTRY
Cover: PC network controller
backs off and reattempts transmissions iri case
of a collision.
' "
Since most of its major features are completely under user control, theIC's data-link
controller subsection gives an enormous degree
of freedom to the system developer. And the
chip is right at home in a wide variety of nEltworks. For baseband transmission, it handles
end of carrier (IEEE 802.3) framing; for the
IBM PC network it accommodates high-level
data link control (HDLC) framing. Both techniques include a 32-bit CRC for error detection.
The data controller also can be programmed
with the length of the address field, station priority, framing, minimum frame length; spacing
between frames, and slot time.
The two collision detection methods increase
the controller's range of possible applications
as well (see "Collision Insurance," p. 148). The
code-violation detection mechanism is most
InterrupJ
. acknowledge

6

Bit 7

5

pOi;ter

I

,4

3

2

:

IChannel1

--- --- -I

Command

.

1

com~and

0

:- I
I
I

I
Value

I

No operation

0

Set Individual address

1

Configure (initialize and set protocol)

2

Set multicast address

3

Transmit frame

4

Perform time-domain reflectometry

5

Dump status registers

6

Diagnose

7

Enable receiver

8

Assign next buffer

9

Disable receiver

10

Stop reception

11

Retransmit frame

12

Abort command

13

Reset

Fix (channel = 1) or Release (channel

useful in short-topology networks, such as a
serial backplane, The bit-comparison tech~.
nique is employed in systems with separate
channels for transmission and reception,like a
broadband network. Both can be used simultaneously'to ensure reliable operation.
The chip presents a rich assortment of diagnostic and management functions: internal and
external signalloopback paths, channel activity indicators, optional capture of alLframes
(regardless of destination address), and timedomain reflectometry for locating faults in the
network cable. Moreover, the controller's
Dump command gives 'the designer access to
the contents of all of the chip's registers, which
helps debug system software.
'
'
The time is right

,A clock timing generator on the chip's serial
side determines the data rate. It will accept up
to a 16~MHz crystal for data transfers to
2 Mbitsls. (The parallel side has its timing set
by the system's ma,ster clock.) The data encoder
arid decoder, also on the serial side, can transmit and receive information in anyone of three
forinats: Manchester, differential Man\!hester, '
and NRZI. Manchester is used in StarIan. NRZI
encoding is for broadband systems.
The transmit and receive FIFOs enable the
parallel and serial sectionso:t'the' controller to
exchange data. These registers, each 16-bytes
deep, improve data throughput between the
controller and the host CPU. The controller's
programmable FIFO threshold can be finetuned to a particular system's buslatencies.
The con troller and the CPU talk to each other
through 'main memory and the controller's onchip registers. The processor uses the Chip
Select (CS) line-along with the Write or Read
signal-to gain the cOJltroller's attention. Th,e
controller communicates with the CPU over the
Interrupt (INT) line. In addition, the two share
an 8-bit data bus.

14
=

2) pointer

15

2. The controller's command register is fed commands from the host CPU, which the chip executes
for one of its two channels. The pointer field within
the register identifies which status register is to be
read, and the interrupt acknowledge field resets the
controller's interrupt line to the CPU.

Two transfer types

Two types oflransfers can take place'via the
bus. The first is a command and status transfer;
the second, a data transfer. The former is
always performed by the CPU. To initiate a
Transmit or Configure command, for example,
the processor issues the command to the con-

Electronic Delign • December 13, 1984

8-120

AR-371

troller.At the completion of the command the
controller issues an interrupt and the CPU
reads the chip's status.
The host reads each of the four status
registers, from the same port, in round-robin
fashion. Any parameters or data associated
with a command are transferred between the
main memory and the controller using DMA.
Data transfers, unlike command and status
transfers, are requested by the controller and
are most often carried out by an external DMA
controller.
Dual DMA

The controller is fitted out with a pair of
DMA channels, each with a Request and Acknowledge line. Typically, one channel receives
data and the other transmits Lnformation and
carries the chip's initialization and maintenance rO,utines. The channels are identical,

though, and can be used interchangeably. When
the controller needs to transfer data to or from
memory, it activates the DMA request lines and
the DMA controller. When it is finished, it interrupts the CPU, which then reads the status
of the controller to confirm the operation.
In order to transmit a frame, the CPU first
prepares a data block in memory, which contains the network address to which the frame is
to be sent and the information to be transmitted. The CPU programs the DMA controller
with the address of the block, along with other
control information. It then issues a Transmit
command to the controller's command register.
At this point, the controller monitors the network link to determine whether the line is free.
If it is, the IC starts transmitting the frame by
inserting the preamble, beginning-of-frame
flag, and the source address and fetching bytes
from memory, loading them into the FIFO, and

Received Data

8·bit data bus
and control signals

~

t

Data-link

controller
and
CSMAICD
logic
Transmitted
Data

4-bit request
and acknowledge bus

Receive Clock

Transmit Clock

o

Xlal

3. The controller's two main blocks are linked by two 16-byte FIFO registers. The parallel section
comprises a bus interface unit that connects the controller to the host and a register subsection
that accepts 'commands and delivers information on the controller's status. The serial section contains a data-link controller subsection, decoder and encoder circuits, collision detection logic. and
a serial-timing generator.

Electronic Design· December 13, 1984

8-121

AR·371

DESIGN ENTRY
Cover: PC network controller

sending them out over the network. While the
controller is sending the frame, it calculates a
CRC, which it appends to the end of the data
field. If a collision is detected during transmission, the controller sends out a jamming pattern and interrupts the CPU. The processor can
then issue a Retransmit command, which
works in the same way as the Transmit command, except that the chip keeps a record of the
number of collisions that are detected. At the
end of a transmission, the controller updates all
of the status registers and sends an interrupt to
the CPU, indicating that the transmission is
complete.
.When it is not transmitting a frame or doing
housekeeping, the controller continually checks
the network for any messages addressed to it.
Calling all nodes

The controller can be addressed in one of
three ways: individual addresses to one node,
multicast addresses to a group of nodes, and
broadcast addresses to all of the nodes in the
network. Two types of reception are possible as

well. In the "promiscuous" mode, the controller
accepts any frame that is transmitted on the
network regardless of its address. In the other,
the device accepts only multicast and individual
addresses that correspond to its own. The latter
typifies normal operations.
Before enabling the receiver, the CPU makes
a memory buffer available and programs the
DMA controller with the buffer's starting address. The received frame is then transferred to
memory. This is known as single buffer reception, since the entire frame is sent to a continuous buffer.
When a frame is received, the network controller records the number of bytes that were
written into the memory buffer in a status regIster. Also, the controller records the status of
the reception-whether it was successful or
not-and affixes that information to the received frame. Then the controller issues an interrupt to the CPU to indicate that reception is
finished.
In networks where the size of the frame is not
fixed, the controller's multiple-buffer scheme

Event

Status 0

Operation
status

Internal
status

Status 1

Res~lt t

Status 2

·R.S~1t 2

I
I

Status 3

4. The controller's .our status registers .all into two categories. The 'irst, which consiltl o.
three regilters, indicates an operation's statuI. The lecond containl a single register and
keeps tabs on the chip's internal operating activity. The operation status regilters con.irm
that a particular command has been executed and Itore any result, i. one il produced.

Electronic D••ign • December 13. 1984

8-122

AR-371

DESIGN ENTRY
Cover: PC network controller

makes effective use of the memory. In multiple
buffering, the controller alternately receives
the contents of a given frame from one of the
two DMA channels. This dynamic allocation of
memory buffers makes particularly efficient
use of available storage when frames are of
widely differing sizes.
Before multiple-buffered reception begins,
the CPU allots one buffer to the controller. As
the controller starts receiving the buffer's contents, it interrupts the CPU and requests that

Collision insurance
The efficiency of CSMA/CD was demonstrated
in a 1979 study of Ethernet that linked about 120
host computers and network serv~rs. The investigation showed that a network using some
form of collision detection had a throughput of
98%, compared with 37% in systems that deferred
while there was traffic on the channel, and 18% in
those with no collision-regulating provision at all.
Until recently, though, the relative sophistication
of such collision detection schemes as CSMA/CD
precluded them from low-ends networks.
The 82588 can be programmed in two ways to implement CSMA/CD collision detection. Both are
logic-based. In code-violation detection, the controller looks to see if incoming bits violate Manchester or NRZI enoding standards. If that is the
case, they are assumed to have been damaged by a
collision. The second method, bit comparison, is
useful in networks with separate transmission and
reception channels such as Star Ian or the IBM PC
network. In this scheme, the device compares its
transmitted CRC signature with that of the received signal while a transmission is taking place.
Monitoring the network in this manner allows the
chip to immediately backoff and try again when a
collision is detected, without having to wait for an
acknowledgement from the received mode. Hence,
total data throughput is significantly increased.

the next buffer in the sequence be assigned. The
processor responds by loading the second DMA
channel with the information in the next buffer. In this way, the controller can immediately
switch over to the second channel as soon as the
first buffer is full. When channels are swi tched,
the controller again interrupts the CPU to
request another buffer, and information on
that buffer is loaded into the unused channel.
The process of alternating between channels
continues until the entire frame has been loaded. By the time that is accomplished, the received frame has been spread over a number of
buffers, and the CPU has created a description
of the buffer-chain in memory.
Connecting the controller to any of the industry's leading microprocessors is a straightforward task because the chip's system interface adapts easily to any processor that
works with standard data bus and control
signals. The chip works with no wait states on
an 8-MHz system bus. Further, a system based
on the chip and one of the 80188 and 80186 family of microprocessors exacts a minimum component count (Fig. 5).
Easy interface

In a system centered on the 8-bit 80188, for instance, the controller connects directly to the
microprocessor's 8-MHz clock and data bus and
to its Read, Write and Chip Select control
signals. Although the controller needs two
DMA channels to operate, these, too, are supplied directly by the processor. And the CPU's
interrupt controller can service the interrupts
generated by the controller.
The controller's flexibility allows the same
system configuration to be used in a number
of different physical layer interfaces. In a StarIan network or in a serial backplane, the controller would feed a line driver. In an IBM PC
network, the controller would connect to an rf
modem. In terms of hardware, only the actual
physical link to the network need be changed in
order to switch between these applications. All
other necessary variants are easily implemented by commands that can be built into the
system's firmware.
For baseband systems running at 1 Mbitls
and using unshielded twisted-pair or coaxial
cable, the only external components needed are

Electronic Dnign • December 13. 1984

8-123

AR·371

DESIGN ENTRY
Cover: PC network controller
an RS-422 driver and receiver and, possibly, one
or two pulse transformers. The last supplies dc
isolation. Together, these few components can
fit onto an area that is 6 em on a side. In contrast, traditional data-link controllers and
their associated TTL glue and other logic demand an area that is at least 15 em on a side.
In a Starlan configuration, the controller
links to the network through low-cost RS-422
transmitter-receivers, one connected to Transmit Data, TXD, pin and the other to the Receive

Data, RXD, pin. Each transmitter-receiver is
joined to a separate pulse transformer and then
to corresponding transmit and receive twistedpair. Each station is connected to a hub over the
two twisted pair drop cables,up to 800 ft. in
length. Within the hub is a corresponding pair
of transformers and RS-422 receiver-transmitters for each station. Transmitted signals
from a number of nodes are ANDed on a short
(less than 1m) bus and returned back to the controller through the receiver pair. The trans-

Upper Range
Chip Select, UCS

Program

RAM

"'III......Ir-.lt.,rr::"~:::=~~~~~~~~~
WA

Midrange
lE
Chip Select. MCSo-MCS 3 , .

AD I-....-------,-.++-~-I AD

80188

-------.++---1 WR

WR 1-....

microprocessor

Ae- A 15

Lower Range
Chip Select. LCS

o AD 7
AD -

Low-order

RAM

AD

·······IIII......I I I!I .....

141..

82588

elK Out 1-....'--............- -......-'--.,...-1
. . . . . . . . . . .~Do-D7

Collision Detect,

"n·....."q

DMA Request, DROo : -.................................._....-;......",_......'-1 Request (channel A), ARQS

DMA Request. ORQl

Request (channel B), BROS

Peripheral Chip Select, peSt

AACK

Peripheral Chip Select, PCS 2

BACK

Reset

Reset

peso

cs

Interrupt Request

INT

Peripheral Chip Select,

Axe

5. A minimum number of components marks the interface between the controller chip and an 80188 micro·
processor. The controller IC links directly to the processor's a-MHz clock, and Read, Write, and Chip Select
control lines. Even the two DMA channels and the interrupt functions are handled by direct connections between the microprocessor and the LAN controller chip.

Electronic Design· December 13. 1984

8-124

AR·371

DESIGN ENTRY
Cover: PC network controller

mitting controller performs collision detection
on the received data.
For broadband systems, such as the IBM PC
network, NRZI-encoded data passes through an
rf modulator and demodulator. In this case, the
RTS and Clear to Send (CTS) signals from the
controller are modem handshake signals. Here,
the transmit and receive signals are modulated
at different frequencies, or channels. A fre- .
quency translator on the network receives the
signals from all the nodes and retransmits

.*(t::'tT:·~!+~~e~~.~~~l~l;n~;rf;
TRANSMIT: PROCEDURE (CHANNEL,BUFFER-lEN,BUFFERPOINTER):
DECLARE CHANNEL BYTE:
DECLARE BUFFER-LEN WORD:
DECLARE BUFFER-POINTER POINTER:
TlLBUFFER-588(OO) - BUFFER-LEN MOD 256:
, TlLBUFFER-588(01) - BUFFER-LEN' 256:
TlLBUFF_PTR -,
BUFFER-POINTER:
TlLCHANNEL = CHANNEL:
TlLBUFFER-lEN - 2048:

'" TEMPORARYSTORAGE "'

r

MAX. FRAME SIZE ""

CALL DMA..LOAD (TlLCHANNEL,1,TlLBUFFER-LEN,
TlLBUFF_PTR):
OUTPUT (CS_588) - 4 OR SHL (TlLCHANNEL.4):
'" TRANSMIT "'
RETURN:
END TRANSMIT:

RETRANSMIT: PROCEDURE:
'" PARAMETERS FOR THIS COMMAND ARE TAKEN FROM
THE TEMPORARY STORAGE USED DURING THE LAST
TRANSMIT COMMAND "'
CALL llMA-LOAD(TlLCHANNEL, 1,TlLBUFFER-LEN,
TlLBUFF_PTA):
OUTPUT (CS.-588) - 12 OR SHL (TlLCHANNEL,4):
RETRANSMIT "'
RETURN:

r

END RETRANSMIT:

RCV_ENABLE: PROCEDURE(CHANNEl:,BUFFER-PTR):

them at the system's receiving frequency. The
receive and transmit channels of the IBM network each fits into the bandwidth of a 6-MHz
TV channel.
Software for the controller is much simpler
and easier to implement than for traditional
data-communication chips. One reason is the
controller's high-level commands, which speed
software development, as well as offload the
CPU, Another reason is the controller's ability
to handle complete frames without the processor's assistance .
In a PL/M-86-language procedure for transmitting a frame, the CPU prepares a block in
memory by loading the DMA controller with
the starting address of the block and its byte
count (Program 1). The central processor also
enters the DMA parameters into temporary
storage so that they can be reused in case a
collision occurs. After loading the DMA controller, the processor issues the Transmit command to the controller. If the channel is clear,
the frame is sent. Otherwise, the chip automatically defers to any activity on the data link
and then transmits its signal. Ultimately, the
controller interrupts the CPU, which determines from the status register whether or not
the transmission was successful.
If a collision occurs, the CPU invokes the Retransmit procedure (Program 2). In this procedure, the DMA controller is reloaded with the
parameters (taken.from temporary storage)
and the Retransmit command is issued. On receiving it, the controller again attempts to
transmit the frame; but only after a back-off
time (which begins counting on the last collision) has run out.
Finally, to receive a frame, the CPU prepares
a buffer in memory,loads the DMA controller,
and enables the receiver (Program 3). When a
frame arrives, it is deposited into the memory
using a DMA operation. Then the CPU is interrupted,letting it know that it can now determine the length and status of the received
frame. 0

DECLARE CHANNEL BYTE:
DECLARE BUFFER-PTR POINTER:
CALL DMA..LOAD(CHANNEL,O,2048,BUFFER-PTR):
OUTPUT(CS·588) = 8 OR SHL (CHANNEL,4):
RETURN:
END RCV_ENABLE:

Eleclronlc D••i9n ' December 13, 1984

8-125

intJ

AR-385

LOCAL-AREA NETWORKS

TWO LOW·SPEED
NETS RACE TO
LINK COMPUTERS
AT&T's 1-Mb/s and IBM's 2-Mb/slocal-area networks are vying for selection
by the IEEE as standard for personal computers
hile the love affair between business and the perW sonal
computer shows no signs of cooling, users
have complained for a long time about the lack of a way
to share information. The decline in fortunes of the corporate information center, starting in the early 1970s,
coincided with the rise of the personal computer and
soon led to the proliferation of data outside a centrally
controlled environment.
But there is new hope that what management has torn
asunder, technology will reunite. Networking schemes
that were too expensive for all but the largest corporations are dropping in price and are thus becoming attractive to the small and medium-size company. As a result,
the race is on to promote a new standard for a network
that transmits at rates under 10 Mb/s and inexpensively
links personal computers while offering the functionality
found in such big-ticket networks as Ethernet. This is the
goal behind two sharply contrasting proposals for a
small-office network standard being pushed by AT&T
Information Systems, Morristown,' N.J., and IBM Corp.,
Armonk, N.y'~both until .now sleeping, giants in the
business of low-cost local networks.·
The major difference between an Ethernet~type net-

0 by Robert A. Sehr

work and the new generation of low-cost networks is the
rate at which data is transmitted. The proposal from the
Institute of Electrical and Electronic Engineers' 802.3
committee-which issued its standard for carrier-sensingmultiple-access-with-collision-detection, or Ethernet:like,
networks in November.,-specified a IO-Mb/s transmission rate. PC Net, the network protocol that IBM recently licensed from Sytek Inc., Mountain View, Calif., carries data at a relatively slow 2 Mb/s; AT&T Coo's
. proposed StarLan network-which the company admits
is not yet a committed product--carries data at only half
that speed.
Though such slow speeds would be unacceptable for
host-to-host communication, "there is no need for personal computers to communicate at 10 Mb/s," notes
Gregory Ennis, director of systems engineering at Sytek.
But even though both StarLan and·PC Net operate at
,relatively slow speeds, they are designed' and built so
they can be bridged to larger networks. These include
networks such as Ethernet in the case of baseband StarLan, and IBM's forthcoming token-ring network in the
case of PC Net.
The broadband PC Net, which began ,life as' Sytek's

1. Broadband PC Network. A standard 75-fl coaxial cable forms the data highway for clusters of up to 1,000 IBM Corp. Personal Computers
and 3270 PCs. It will also handle voice and video when the backbone token ring becomes available.
ElectronlcsWeek/December 17, 1984
Reprinted frol ELECTRONICS WEEK, December 17, 1984.
Copyright" 1984, McGraw-Hili Inc. All rights reserved.

8-126

Order Number: 231531-001

inter

AR·385

Local Net/PC, uses a standard 75-0 coaxial cable-the
same as is used for cable television-so it can transmit
not only data, but voice and video signals as well. It
supports up to 72 IBM Personal Computers, PCXTs, or
PC ATs within a radius of 1,000 ft. of a node. Using a
custom-installed broadband network and a $695 PC Net
adapter card, up to 1,000 personal computers can be
connected within a 3-mile area (Fig. 1).
Seven-layer tree

PC Net is organized into a hierarchical seven-layer
tree structure following the plan set out in the International Organization for Standardization's reference model
for local-area networks. There is the physical layer,
which contains the electronic and mechanical contents of
the transmission medium; the link layer, which contains
protocol mechanisms; the network layer, which routes
packets between LAN channels or installations; the
transport layer, which is responsible for end-to-end data
transfers; the session layers, which contain user shells;
the presentation layer, which manipulates data into presentation form between points in the network; and the
.
applications layer (Fig. 2).
The net services all but the applications layer, which is
left to the vendor of the host terminal or IBM PC to
customize to a particular application. "The beauty of it is
that it allows for an open concept for applications software," Ennis says. "This is the same philosophy that
allowed the IBM PC to proliferate as much as it did."
With IBM's strong marketing force behind PC Net,
Ennis expects that third-party software writers will rush
to create additional multiuser, multitasking applications,

DISTRIBUTED DATA BASE

TERMINAL EMULATION

ELECTRONIC MAIL

PRINT SERVICE

FilE ACCESS

SYSTEMS·NETWORK·
ARCHITECTURE GATEWAY

ensuring its widespread acceptance. "Up until now, writing a network application program has been kind of
risky," says Leo Nikora, a product marketing manager at
Microsoft Corp., Bellevue, Wash. "There was no single
network standard and no single resource-sharing standard. More important, IBM has indicated that PC Net
will be software compatible with its token-ring network,
which will further increase the market for application
programs, Nikora says.
Though some designers question whether Microsoft's
MS-DOS and Xenix operating systems can operate at 2
Mb/s, Nikora is sure that PC Net will be able to handle
all the traffic that users can throw at it. The reason for
this is that actual throughput decreases the further you
get from the physical or hardware level: when through-,
put proves too much for the operating system to handle,
it can be buffered outside the operating system under
user control.
Below the applications layer are layers of hardware
and software welded together to define PC Net's performance. At the network's hub is the PC Net translator,
which provides single-channel frequency translation for
the network. Up to eight IBM PCs can attach directly to
the translator; by using the base expander, a total of 72
IBM PCs can be hung from a single node.
The translator is linked to the IBM PC by up to 200 ft
of cable, together with an adapter card that slips into a
card slot in the personal computer. At the adapter card's
heart is an Intel 82586 controller chip, an 80188 processor, a fixed-frequency modem (which operates at 50.75
MHz for transmission and 219 MHz for receiving), and a
Sytek custom chip that complements the 82586 to provide CSMA/CD and modified nonreturn-to-zero (NRZI) data coding.
At the link layer, the link-access
protocol provides the CSMA/CD
functions that keep' users who are
seeking the same data on a network
from colliding with each other and
takes care of error detection. The
network level consists of one protocol that is used for packet transfer,
which routes packets between separate link-layer channels. Transportlayer protocols follow the ISO Class
4 transport scheme, with the reliablestream protocol providing a virtualconnection service and the user-datagram protocol providing end-to-end
exchanges of packets with a simple
best effort.
The session-management protocol-which resides in read-only
memory on the network adapter
card-builds stream-oriented sessions
on top of the reliable-stream proto2. Protocol architecture. IBM's PC Network
implements a hierarchical seven-layer tree
architecture providing full network functions
up to the applications layer. It is up to the
systems integrator to design the applications-layer functions.
EleclronicsWeek/December 17, 1984

8-127

intJ

AR-385

col's virtual connections, allowing session participants to
be identified by symbolic names. Users can register these
symbolic names by means of the name-management protocol in the same layer. Also located in the session layer
are the user datagram protocols, which allow users to
send datagrams with symbolic names rather than with
network addresses, together with the diagnostic and monitoring protocol, which gives the network's statistics and
status.
In contrast to the co~plex structure of PC Net, StarLan's heart is a simple I-m bus that connects to each
personal computer by means of twisted-pair wiring
dropped from a building's standard telephone-wiring
closet, where the bus is centered (Fig. 3). The twisted
pairs terminate in RS-422 line drivers and receivers in
the closet. Each hub supports up to 50 users connected
within 600 to 800 ft· of the wiring closet.
Telephone-wire tie-in

In pushing the Star Lan proposal before the IEEE
802.3 committee, AT&T noted that most office buildings
have a standard telephone connection with 25 twisted
pairs, of which only a few are used. As a result, it won't
be necessary to rewire existing buildings-or prewire new
ones-as is required for Ethernet, its RG-58A/U variant
(dubbed Cheapernet), and token-ring networks.
This feature is a major selling point for Star Lan. Because it uses commonly available phone wire; which is
present in every office building, facilities already exist to
tie several hubs together (Fig. 4). Thus, Star Lan can be
bridged to faster transmission backbone networks, such
as Ethernet or Cheapernet.
The worst-case estimate, according to one of the task
forces chartered by the IEEE 802.3 committee, puts StarLan's cost at about $200 per connection, including the
network processor, wiring, installation, and repeaters or
hubs. Some estimates put the cost as low as $50 per
connection, plus installation. In addition, "moving a
computer in the network will be as easy as moving a
telephone," says Timothy A. Rock, a member of the
technical staff at AT&T Information Systems Laboratories, Holmdel, N.J. "It will actually be easier, since lines
in the Star Lan network are individually unique."
Regardless of AT&T's claims for StarLan, so many doubts surfaced over the
capability of twisted pairs that the IEEE
802.3 committee, meeting in Vancouver,
B.C., Canada, in July, formed a task force
to study the matter further, and it reported
back at the October meeting in San Diego.
Among the subjects studied were the effects of distance from the wiring closet and
the reliability of old wiring in existing
buildings compared with new twisted-pair
wiring. Committee chairman Donald
Loughry, of Hewlett-Packard Co., Cuperti-

no, Calif., says that twisted pairs can accept transmissions at the I-Mb/s transmission rate. He adds, however,
that it is "something that merits further testing by an
independent agency."
In addition, others have raised questions about the
advisability of running I-Mb/s transmissions through
twisted pairs. Sytek's Ennis, for one, is skeptical. "I
wonder. if running that kind of transmission through
unshielded twisted pairs meets the Federal Communications Commission's noise requirements," he says. T. A.
Rock, however, says almost every test AT&T has run on
StarLan demonstrates that it can run safely at I Mb/s in
existing wiring in most office buildings. (Ironically, one
of the few buildings that was unable to pass the test was
AT&T's own headquarters.)
The cost of wiring buildings is a significant factor in
the acceptance of LANs, and most observers agree that
the high cost of the heavy-duty yellow Ethernet cableas high as $4 per ft"':""has prevented Ethernet from becoming popular in small and medium-size offices. As a
result, alternative networking schemes using twisted pairs
have been developed-for example, Omninet, spawned by
Corvus Systems Inc., San Jose, Calif. Omninet, however,
does not use collision detection to determine which station gains access to the network. StarLan can detect a
collision on the bus; since the bus in the wiring closet is
so short that it does not allow the signal to weaken, it
enables collision detection to be achieved through logic
rather than through the Ethernet-type transceivers that
look for voltage shifts.
New logic

Further interest in Star Lan focuses on the new generation of logic being evaluated for use in the network. The
controller will be the successor to Intel Corp.'s 82586,
the chip that has been the center of most networking
schemes. Designed for networks with data rates under 2
Mb/s, the new chip will be released in the fourth quarter, although the company has already sent samples to
what it cans "users with systems savvy." Intel, however,
has provided only sketchy details about the new chipother than to say it will combine the functions that now
require two separate chips, as well as add functions that

3. Closeted bus. A 1-m bus in a building's telephone-wire closet forms the heart of AT&T Information Systems' StarLan. The system uses twistedwire pairs that hang off the bus to make the attachment to personal computers and link them in the
network.
ElectronicsWeek I

December

17, 1984

8-128

CARRIER-SENSING
MULTIPLE·ACCESS
BUS WITH COLLISION
DETECTION

HUB

inter

AR·385

4. Cheap wiring. Proponents of Star Lan claim that its use of the ubiquitous four·wire twisted pairs-as found in standard telephone wiring-will
contribute dramatically to the drop in wiring prices of local·area networks.

have never before been present. "We've provided 90% of
StarLan on our new chip," says Robert Galin, Intel's
director of strategic planning.
The new Intel chip at the center of Star Lan provides
collision detection at the chip level, using an exponential
algorithm to reset transmission time after each detection
of a collision. In other words, when two users attempt to
access the same data simultaneously, the user who is
detected first is allowed to proceed; a busy signal is sent
back to the other user or users while the system automat·
ically tries again after a measured period of time that
increases after each attempt (Fig. 5).
The Intel chip looks for a phase shift in the Manchester coding, through which baseband networks such as
Ethernet recognize signals. Manchester coding splits each
bit into a signal and its complement, so that there is
always a zero crossing at the middle of the time slot-or
each bit sent. A collision will cause this crossing point to
Starlan

5. New controller. AT&T Information Systems' Star Lan is being
evaluated with a new-generation controller that detects collisions and
performs retries using internal logic. Bus length in the wire closet is
kept short, enabling the logic to sense a collision.

move outside its time window. The limitation on such a
system is jitter in the signal. According to AT&T, StarLan can tolerate 50 ns of timing jitter.
Intel's chip also will provide data coding in the narrower NRZI coding scheme used by broadband networks, which must be more cautious of bandwidth. As a
result, the new chip will not only benefit Star Lan but
could also be used in IBM's PC Net. "We have tried to
make the chip as versatile as possible. While our competitors were trying to decide between broadband and baseband, we wanted something that would optimize the
environment," says Galin.
The new chip reduces cost not only through its reduced size-which means it needs less silicon-but also
by taking out such devices as the direct-memory-access
controller. The DMA controller restricts the kind of
applications that the chip can run, Galin says. Instead,
the new chip will depend on systems integrators in order
to perform DMA functions.
Sytek's Ennis says the new chip will be a part of PC
Net as soon as it becomes available. He applauds Intel's
flexibility, believing it showed more foresight than the
firm's competitors, which are making more restrictive
networking chips primarily for Ethernet and Cheapernet.
Galin says Intel saw a need for a network that could
transmit at under 2 Mb/s without being bogged down in
specifics. THe firm hedged its bets on various proposals
for low-cost networks by contributing to all of them.
Intel worked with Sytek before the IEEE 802.3 committee and also initiated the task force that began work on
another l-Mb/s LAN based on coaxial cable-the midrange LAN, proposed by NCR Corp., San Diego. That
task force decided that it should concentrate on a single
standard proposal and picked StarLan.
"There really should be more than one," Galin says.
"There are some users who will need the voice, video,
and data transmissions found in PC Net and will be
willing to pay the higher cost. Others won't need it and
will settle on StarLan."
0

Robert A. Sehr is a consultant and writer on network
transmission systems.

8-129

ElectronicsWeekl December 17, 1984

13-130

AR·386

for high data throughput ratesmuch higher than is needed in the office. A cluster of word-processing
work stations can get by handily on a
data transfer rate of I or 2 megabytes
per second. Using a 10 Mbps link
such as Ethernet in many small offices is a bit like using a Mack truck
to pick up the groceries. It's an inappropriate-not to mention expensive-usc of a technology.
o Many PC LANs can function adequately with networks containing
only a few stations-say a dozen or
so. But they grow hopelessly congested when more terminals arc
added. This is a result of using a lessthan-optimal collision avoidance access method. The much more efficient collision detection method
employed by the 82588 was heretofore unavailable for PC-based LAN s
because, in the absence of VLSI, it
was far too expensive to implement
using TTL.

o Many of the inexpensive PC networks
that exist suffer from being proprietary systems that were designed before the adoption of industry-wide
standards. But now, with the market
rapidly coalescing around standards
such as Ethernet, STAR LAN, and
IBM's PC Network, proprietary systems arc likely to lose customer favor.
Enter the 588
What the office LAN market needs,
then, is an inexpensive device that will
operate at acceptable performance levels
while accommodating emerging industry standards. The 82588 was created
with exactly those goals in mind.
The 588 is a "kid sibling" to Intel's
82586 LAN Coprocessor. That latter device has an on-board coprocessor allowing it to handle communications tasks
independently of the host CPU, and is
the industry-leading IC for high-performance networks like Ethernet: More
than 100 companies have designed it

into their products.
Because PC networks tolerate slower
bit rates than those found in Ethernet, a
higher level of integration is possible in
the 82588. The features that require
three ICs in Ethernet-the CSMA/CD
controller, the encoder/decoder functions, and the collision detection circuitry-are all built into the 82588. As a
result, the 82588 need only be joined to
an inexpensive transceiver chip to implement STARLAN, and to an RF modem for IBM's PC Network.
A major technical innovation of the
82588 is its on-chip collision detection
capability. The 588 has two collision detect schemes: first, it checks the message on a bit-by-bit basis and ascertains
that the coding scheme is not violated.
If it is violated, a collision is assumed.
Second, the 588 calculates a signature
of the transmitted data, listens to itself
on the receive channel, and re-calculates the signature. A collision is assumed if the two signatures do not

Intel's tiered network model for LANs shows the underlying order in what at
first appears to be a muddled marketplace. Different LAN approaches co-exist
with each other, to be used at different tiers, depending on
the price and perfonnance requirements of the application.
Tier 1
Computer
10
Computer
'0-100 Mbps)

Tier 2

Lan
:ackbone
·10 Mbps)

1====;===1

JANUARY/FEBRUARY 1985 SOLUTIONS

8-131

inter

AR·386

r-----------"~~
I
I

Most of the office desks in the

\

United States have a 2S:-pair
bundled wire running to them

I

~~/'~

I
I

lor telephones. STARLAN
makes use of two unused pairs,
one set for transmitting, the

I

other for receiving. By
leveraging this instaUed
wiring base, STARLAN keeps
costs down.

match. Both methods
can be used in
STARLAN and the
IBM PC Network.
An Economical Answer
This level of integration
goes a long way in
keeping costs down for
OEMs. The 82588
comes in a 28 pin DIP,
and replaces a whole
board full of TTL. It
also solves a legion of
vexing technical communications problems that the majority
of OEMs do not have the resources to
- answer for themselves. The 82588 enables OEMs to forget about low-level
network complexities such as back-off
algorithms and address filtering. As a
result, designers can concentrate on
high-level features, and introduce their
product with greater speed and less
expense.
There are a number of other ways
that the 82588 helps keep.costs down.
For example, the chip hooks up directly
with Intel's 80186 and 80188 microprocessors-no interleaving TTL glue is
needed. And rather than store data in
inefficient sequential data blocks that
are each designed to store the largest
possible frame, the chip uses a sophisticated buffer-chaining technique that
links small buffers together. That storage technique makes for a prudent use
ot memory space, an important consideration in PCs. Finally, the 82588 has a

I
I
I

II
I
I
I

I

L ______________________________ J

high-level instruction set, meaning
OEMs need not spend long months
writing low-level driver software.
On a board, the 82588 will enable
OEMs to deliver a PC communications
peripheral that should end up costing
the end-user a few hundred dollarscompared to about $800 for Cheapemet
and $1,500 or more for Ethernet. As an
IC that's built into a system, the 82588
gives OEMs a chance to offer customers
a powerful communications capability
at an even lower cost.

states, while still maintaining a transfer rate of up to 4 Megabytes per
second.
The second performance-enhancer of
the 82588 is its high-level command interface. To send a message, the CPU
simply stores the frame in memory and
sends the device a TRANSMIT command. The 82588 will send the date
without constant CPU oversight. That
frees the central processor for other
tasks, and increases the over-all performance of the entire system.

Packing A Performance Punch
The 82588 docs not compromise system performance in achieving its considerable economy.
The chip has a very efficient system
bus interface. Its 16-bit receive and
transmit FIFO buffers allow it to minimize its use of the CPU bus while
sending and receiving frames. It also interfaces to an 8 MHz bus with no wait

Finding the Right Tier
But what good is a great new communications chip if the LAN market is
hopelessly fractured with a number of
LAN options? That certainly seems to
be the case, what with Ethernet, Cheapernet, token ring, token bus ... and
now, STARLAN and IBM's PC Network.
"We think that the confusion in the
LAN marketplace is more supposed

8-132

intJ
than real," says Bob Dahlberg, Intel's
product line manager for LAN components. "What's really happening is that
different products are being developed
for different applications. Most of the
major LAN approaches are complementary to each other, not competitive."
Intel has developed a three-tiered
model that is used to explain the costl
performance trade-offs in a seemingly
chaotic LAN Market.
Tier One is the Mainframe-to-Mainframe Tier, where large machines exchange data at extremely high speeds.
The second level is called the LAN
Backbone Tier. Minicomputer-based
equipment such as CADI CAE stations,
with their high throughput requirements, use Tier Two links, of which
IEEE 802.3 Ethernet is probably the
best-known example.
The third tier is called the Department Cluster Tier. This is the level at
which personal computers are linked
(separate departments are tied together
along the LAN Backbone TierJ. While
the 82586 LAN Coprocessor is used in
Tier Two, the 82588 was designed specifically for Tier Three, for use in networks like STARLAN and IBM's PC
Network.
The Star of STARLAN
Just as Ethernet is the de facto standard
for Tier Two minicomputer applications, STARLAN is expected soon to
play the same role in the office's Tier
Three networks.
STARLAN originated from the realization that there was no standard network tailor-made for office-centered
applications. A number of companiesIntel, AT&TIIS, Hewlett-Packard,
Wang, Tandem, NCR and others-are
working together as a task force within
the IEEE 802.3 subcommittee to fill
that gap. Their objective is to create a
cost-effective network designed first and
foremost for use by personal computers
in the office.
STARLAN's major strength is that it
is the first standardized network in
which attention is paid to the practical
problems involved in wiring a building
for a network. To accomplish that,
STARLAN is designed to make extensive use of the network already in place
in every office: the telephone system.
Telephones are hooked up in a star-or
radial topology-with each phone connected to a device in a central wiring

AR·386

closet. The majority of phones in this
country are attached through a cable
containing 25 twisted-pair wires, but a
number of these wires are available for
uses other than telephone
communication.

The confusion in the
LAN marketplace is
more supposed than real.
Most of the major
approaches are
complementary to each
other, not competitive."

able to use the same basic design simultaneously in several networking
packages.
Says Dahlberg, "That kind of flexibility means an end to a lot of OEM anxiety. They'll be able to gain familiarity
with one chip, and use that knowledge
to move their products from one market
to another. II

it ...

STARLAN uses four of these free
. wires-one pair for transmitting, the
other for receiving. As with telephones,
each network station in STARLAN is
connected to a hub, whicn can be up to
800 feet away. Within the hub is a short
bus that connects the nodes.
STARLAN transmits data at 1 Mbps.
This speed is more than enough to support the needs of the modem office,
where messages are usually relatively
short text files.
STARLAN's use of inexpensive
twisted-pair wires, which for most customers will already be in place, means
very low installation costs. Because it
is a four-wire system, inexpensive
transceivers can be used. A further reduction of system costs is provided by
STARLAN's short bus, which allows
the use of logic-based collision detection that eliminates the need for additional hardware. STARLAN's design
goal is a total cost to the end-users of
$200 per connection.
STARLAN, IBM PC Network ...
And More
The 82588 was designed to be used in
both STARLAN and IBM's PC Network,
but it can also be easily reconfigured
for use in other CSMA/CD networks.
An example of its flexibility: the device
supports both HDLC framing and 2
Mbps NRZI encoding and decoding, as
specified by the IBM PC Network.
OEMs using the 82588 have a highly
adaptable device to work with, and no
worries about being left behind by a
changing marketplace. They'll even be

8-133

And Software to Boot
Of course, LANs don't live by boards
alone, and the specs for STARLAN and
IBM's PC Network only deal with hardware questions. Fortunately, networking
software for PC LANs is on the way.
Intel now sells iNA 960, the industry's only off-the-shelf implementation
of the ISO Transport Layer. It is the job
of iNA 960 to break up a message into
frames, send the frames to the recipient,
and re-assemble the frames on the other
end. Most importantly, iNA 960 guarantees that a message is received correctly; otherwise it notifies the user
that delivery was impossible.
Transport layer software is a key element in any network. But there are still
other software tasks that need tending
to before a network can come alive.
Those other tasks are represented by
Layers Five, Six, and Seven of the ISO
model.
Microsoft Corp. has announced its
"Microsoft Networks" product that addresses those three layers. The software
is available for MS-DOS, • which Microsoft created. And Intel and Microsoft
have announced that they have developed network software protocols (the
basis of Microsoft Networks J that allow
files to be shared concurrently by multiple users on a LAN. These protocols
run under the iRMX'" and XENIX' operating systems.
Reaching The Promised LAN
PCs have already proven themselves to
be powerful tools in the office environment, but as yet only the surface of the
PC's potential has been scratched. The
development of new networking technologies promises to probe the depths of
the PC's abilities, opening up a whole
new bag of tricks for this machine.
The world has been ready for PC
LANs for a long time. Now, with hardware and software in place, PC LANs
0
are finally ready for the world.
• MS-DOS and XENIX arc trademarks of Microsoft
Corp.

intJ
than real," says Bob Daj1lberg, Intel's
product line manager for LAN components. "What's really happening is that
different products are being developed
for different applications. Most of the
major LAN approaches are complementary to each other, not competitive."
Intel has developed a three, tiered
model that is used to explain the cost/
performance trade-offs in a seemingly
chaotic LAN Market.
Tier One is the Mainframe-to-Mainframe Tier, where large machines exchange data at extremely high speeds.
The second level is called the LAN
Backbone Tier. Minicomputer·based
equipment such as C.AD/CAE stations,
with their high throughput requirements, use Tier Two Jinks, of which
IEEE 802.3 Ethernet is probably the
best-known example.
The third tier is called the Department Cluster Tier. This is the level at
which persona!. computers are linked
(separate departments are tied together
along the LAN Backbone Tier). While
the 82586 LAN Coprocessor is used in
Tier Two, the 82588 was designed specifically for Tier Three, for use in networks like STARLAN and IBM's PC
Network.
The Star of STARLAN
Just as Ethernet is the de facto standard
for Tier ,Two minicomputer applications, STARLAN is expected soon to
.play the same role in the office's Tier
Three networks. '
STARLAN originated from the realization that there was no standard network tailor-made for office-centered
applications. A'number of companies'Intel, AT&T/IS, Hewlett-Packard,
Wang, Tandem, NCR and others-are
working together as a task force within
the IEEE 802.3 subcommittee to fill
that gap. Their objective is to create a
cost-effective network designed first and
foremost for use by personal computers
in the office.
STARLAN's major strength is that it
is the first standardized network in
which attention is paid to the practical
problems involved in wiring a building
for a network. To accomplish that,
STARLAN is designed to make extensive use of the network already in place
in every office: the telephone system.
Telephones.are hooked up in a star-or
radial topology-with each phone connected to a device in a ceritral wiring .

AR·386

closet. The majority of phones in this
country. are attached through a cable
containing 25 twisted-pair wires, but a
number of these wires are available for
uses other than telephone
communication.

" ... The confusion in the
LAN marketplace is
more supposed than real.
Most of the major
approaches are
complementary to. each
other, not competitive. "
STARLAN uses four of these free
pair for transmitting, the
other for receiving. As with telephones,
each network station in STARLAN is
connected to a hub, which can be up to
800 feet away. Within the hub is a short
bus 'that connects the nodes.
STARLAN transmits data at 1 Mbps.
This speed is more than .enough to support the needs of the modem office,
where messages are usually relatively
short text files.
STARLAN's use of inexpensive
twisted-pair wires, which for most customers will already be in place, means
very low installation costs. Because it
is a four-wire system, inexpensive
transceivers can be used. A further reduction of system costs is provided by.
STARLAN's short bus, which allows
the use of logic-based collision detec·
tion that eliminates the need for additional hardware. STARLAN's design
goal is a total cost to the end-users of
$200 per connection.
wires~one

STARLAN, IBM PC Network ...
And More
The 82588 was designed to be used in
both STARLAN and IBM's PC Network,
but it can also be easily reconfigured
for use in other CSMA/CD networks.
An example of its flexibility: the device
supports both HDLC framing and 2
Mbps NRZI encoding and decoding, as
specified by the IBM PC Network.
OEMs using the 82588 have a highly
adaptable device to work' with, and no
worries about being left behind by a
changing marketplace. They'll even be.

8-134

able to use the same basic design simultaneously in several networking
packages.
Says Dahlberg, '~That kind of fleXlbility means an end to a lot of OEM anXiety. They'll be able to gain familiarity
with one chip, and use that knowledge
to move their products from one market
to another."
And Software to Boot
Of course, LANs don't live. by boards
alone, and the specs for STARLAN and
IBM's PC Network only deal with hardware questions. Fortunately, networking
software for PC LAN s is on the way.
Intel now sells iNA 960, the industry's only off-the-shelf implementation
of the ISO Transport Layer. It is the job
of iNA 960 to break up a message into
frames, send the frames to the recipient,
and re-assemble the frames on the other
end. Most importantly, iNA 960 guarantees that a message is received correctly; otherwise it notifies the user
that delivery was impossible.
Transport layer software is a key element in any network. But there are still
other software tasks that need tending
to before a network can come alive.
Those other tasks are represented by
Layers Five, Six, and Seven of the ISO
model.'
Microsoft Corp. has announced its
"Microsoft Networks" product that addresses those three layers. The software
is available for MS-DOS, • which Microsoft created. And Intel and Microsoft
have announced that they have developed network software protocols Ithe
basis of Microsoft Networks) that allow
files to be shared concurrently by multiple users on a LAN. These protocols
run under the iRMX'" and XENIX' operating systems.
Reaching The Promised LAN
PCs have already proven themselves to
be powerful tools in the office environment' but as yet only the surface of the
PC's potential has been scratched. The
development of new networking technologies promises to probe the depths of
the PC:s abilities, opening up a whole
new bag of tricks for this machine.
The world has been ready for PC
LANs for a long time. Now, with hardware and software in place, PC LANs
are finally ready for the world.
0
~ MS-DOS

Corp.

and XENIX are trademarks of Microsoft

.

Global Communications
Data Sheets

9

inter

8251 A

PROGRAMMABLE COMMUNICATION INTERFACE
Synchronous and Asynchronous
• Operation
5-8 Bit Characters;
• Synchronous
Internal or External Character

•

•

Synchronization; Automatic Sync
Insertion
Asynchronous 5-8 Bit Characters;
Clock Rate-1, 16 or 64 Times Baud
Rate; Break Character Generation;
1, 1Y2, or 2 Stop Bits; False Start Bit
Detection; Automatic Break Detect
and Handling
Synchronous Baud Rate-DC to
64K Baud

Asynchronous Baud Rate-DC to
• 19.2K
Baud
Full-Duplex,
Double-Buffered
• Transmitter and
Receiver
Error Detection-Parity, Overrun and
• Framing
with an Extended Range
• ofCompatible
Intel Microprocessors
28-Pin DIP Package
• All
Inputs and Outputs are TTL
• Compatible
Available in EXPRESS
• -Standard
Temperature Range
-Extended Temperature Range

The Intel® 8251A is the enhanced version of the industry standard, Intel 8251 Universal Synchronous/
Asynchronous ReceiveriTransmitter (USART), designed for data communications with Intel's microprocessor
families such as MCS-48, 80, 85, and iAPX-86, 88. The 8251A is used as a peripheral device and is programmed
by the CPU to operate using virtually any serial data transmission technique presently in use (including IBM
"bi-sync"). The USARTaccepts data characters from the CPU in parallel format and then converts them into a
continuous serial data stream for transmission. Simultaneously, it can receive serial data streams and convert
them into parallel data characters for the CPU. The USARTwili signal the CPU whenever it can accept a new
character for transmission or whenever it has received a character for the CPU. The CPU can read the
complete status of the USARTat any time. These include data transmission errors and control signals such as
SYNDET, TxEMPTY. The chip is fabricated using N-channel silicon gate technology.

0,

0,

OJ

On

R.O

Vee

GNO

R.e

0,

OTR

0,

RTS

On

OSR

0,

RESET

T.e

eLK

WR

hO

os
C/O

AD
RxRDV

CTS
SYNDET/BO

T.ocRDY

Figure 2. Pin Configuration

Figure 1. Block Diagram

Intel Corporation Assumes No Responsibility for the Use of Any Circuitry Other

TxEMPTY

Than CircUitry Embodied

. INTEL CORPORATION 1984

In

an Inlel Product. No Other Circuit Palent Licenses are.lmplleo .

Seplember 1984

9-1

207780-001

inter

8251A

FEATURES AND ENHANCEMENTS

FUNCTIONAL DESCRIPTION

The 8251A is an advanced design of the industry
standard USART, the Intel® 8251. The 8251A
operates with an extended range of Intel
microprocessors and maintains compatibility with
the 8251. Familiarization time is minimal because of
compatibility and involves only knowing the additional features and enhancements, and reviewing
the AC and DC speci,fications of the 8251A.

General
The 8251A is a Universal Synchronous/Asynchronous Receiver/Transmitter designed for a wide
range of Intel microcomputers such as 8048,8080,
8085, 8086 and 8088. Like other I/O devices in a
microcomputer system, its functional configuration
is progral\1med by the system's software for maximum flexibility. The 8251A can support most serial
data techniques in use, including IBM "bi-sync."

The 8251A incorporates all the key features of the
8251 and has the following additional features and
enhancements:

• In asynchronous operations, the Receiver detects
and, handles "break" automatically, relieving the
CPU of this task.

In a communication environment an interface
device must convert parallel format system data into
serial format for transmission and convert incoming
serial format data into parallel system data for reception. The interface device must also delete or insert
bits or characters that are functionally unique to the
communication technique. In essence, the interface
should appear "transparent" to the CPU, a simple
input or output of byte-oriented system data.

• A refined Rx initialization prevents the Receiver
from starting when in "break" state, preventing
unwanted interrupts from a disconnected USART.

Data Bus Buffer

• 8251A has double-buffered data paths with separate I/O registers for control, status, Data In, and
Data Out, which considerably simplifies control
programming and minimizes CPU overhead.

• At the conclusion of a transmission, TxD line will
always return to the marking state unless SBRK is
programmed.

This 3-state, bidirectional, 8-bit buffer is used to interface the 8251A to the system Data Bus. Data is
transmitted or received by the buffer upon execution
of INput or OUTput instructions of the CPU. Control
words, Command words and Status information are
also transferred through the Data Bus Buffer. The
Command Status, Data-In and Data-Out registers
are separate, 8-bit registers communicating with the
system bus through the Data Bus Buffer.

• Tx Enable logic enhancement prevents a Tx Disable command from halting transmission until all
data previously written has been transmitted. The
logic also prevents the transmitter from turning
off in the middle of a word.
• Wh!'!n External Sync Detect is programmed, Internal Sync Detect is disabled, and an External Sync
Detect status is provided via a flip-flop which
clears itself upon a status read.

This functional block accepts inputs from the system
Control bus and generates control signals for overall
device operation. It contains the Control Word Register and Command Word Register that store the
various control formats for the device functional
definition:

• Possibility of false sync detect is minimized by
ensuring that if double character sync is programmed, the characters be contiguously detected-and
also by clearing the Rx register to all ones
whenever Enter Hunt commanq is issued in Sync
mode.

, RESET (Reset)

• As long as the 8251A is not selected, the RD and
WR. do not affect the internal operation of the
device.

A "high" on this input forces,the 8251 A into an "Idle"
mode. The device will remain at "Idle" until a new set
of control words is written into the 8251 A to program
its functional definition. Minimum RESET pulse
width is 6 tCY (clock must be running).

• The 8251A Status can be read at any time but the
status update will be inhibited during status read.
• The 8251A is free from extraneous glitches and
has enhanced AC and DC characteristics, providing higher speed and better operating margins.

A command reset operation also puts the device into
the "Idle" state.

• Synchronous Baud rate from DC to 64K.
9-2

205222-002

. 8251A

ClK (Clock)

C/D (Control/Data)

The ClK input is used to generate internal device
timing and is normally connected to the Phase 2
(TTL) output of the Clock Generator. No external
inputs or outputs are referenced to ClK but the
frequency of ClK must be greater than 30 times the
Receiver or Transmitter data bit rates.

This input, in conjunction with the WR and RD inputs, informs the 8251A that the.word on the Data
Busis either a data character, control word or status
information.
1 = CONTROL/STATUS; 0 = DATA.

CS (Chip Select)
WR (Write)
A "low" on this input informs the 8251A that the CPU
is writing data or control words to the 8251A.

A "Iow"on this input selects the 8251 A. No reading or
writing will occur unless the device is selected.
When CS is high, the Data Bus is in the float state and
RD and WR have no effect on the chip.

RD (Read)

Modem Control

A "low" on this input informs the 8251A that the CPU
is reading data or status information from the 8251A.

The 8251A has a set of control inputs and outputs
that can be used to simplify the interface to almost
any modem. The modem control Signals are general
purpose in nature and can be used for functions
other than modem control, if necessary.

DSR (Data Set Ready)
The DSR input signal is a general-purpose, 1-bit inverting input port. Its condition can be tested by the
CPU using a Status Read operation. The DSR input
is normally used to test modem conditions such as
Data Set Ready.

DTR (Data Terminal Ready)
The DTR output signal is a general-purpose, 1-bit
inverting output port. It can be set "low" by programming the appropriate bit in the Command Instruction word. The DTR output signal is normally
used for modem control such as Data Terminal
Ready.
/"
INTERNAL

RTS (Request to Send)

DATA BUS

The RTS output signal is a general-purpose, 1-bit
inverting output port. It can be set "low" by programming the appropriate bit in the Command Instruction word. The RTS output signal is normally
used for modem control such as Request to Send.

Figure 3. 8251A Block Diagram Showing Data
Bus Buffer and Read/Write logic
Functions

CTS (Clear to Send)
c/o

RD

WR

0
0

0

1

o·

1

0

0
0
0
0

0
0
X
X

X

X

cs

A "low" OD this input enables the 8251A to transmit
serial data if the Tx Enable bit in the Command byte
is set to a "one." If either a Tx Enable off or CTS off
condition occurs while the Tx is in operation, the Tx
will transmit all the data in the USART, written prior
to Tx Disable command before shutting down.

8251A DATA = DATA BUS
DATA BUS = 8251A OAT...
STATUS = DATA BUS
DATA BUS = CONTROL
DATA BUS= 3·STATE
DATA BUS.= 3·STATE

9-3

205222-002

intJ

8251A

Transmitter Buffer
The Transmitter Buffer accepts parallel data from the
Data Bus Buffer, converts it to a serial bit stream,
inserts the appropriate characters or bits (based on
the communication tf3chnique) and outputs a composite serial stream of data on theTxD output pin on
the falling edge of TxC. The transmitter will begin
transmission upon being enabled if CTS = O. The
TxD line will be held in the marking state immediately upon a master Reset or when Tx Enable or CTS
is off or the transmitter is empty.

Transmitter

Contr~1

The Transmitter Control manages all activities associated with the transmission of serial dat~. It accepts
arid issues sigl)als both externally and internally to
accomplish this function.

TxRDY (Transmitter Ready)
This output signals the CPU that the transmitter is
ready to accept a data character. The TxRDY output
pin can be used as an interrupt to the system, since it
is masked by TxEnable; or, for Polled operation, the
CPU can check TxRDY using a Status Read operation. TxRDY is automatically reset by the leading
edge of WR when a data character is loaded from
the CPU.
Note that when using the Polled operation, the
TxRDY status bit isnot masked byTxEnable, but will
only indicate the Empty/Full Status of the Tx Data
Input Register.

Figure 4. 8251A Block Diagram Showing Modem
and Transmitter Buffer and Control
Functions

TxC. (Transmitter Clock)
The Transmitter Clock controls the rate at which the
character is to be transmitted. In the Synchronous
transmission mode, the Baud Rate (1x) is equal to
the TxC frequency. In Asynchronous transmission
mode, the baud rate is a fraction of the actual TxC
frequency. A portion of the mode instruction selects
this factor; it can be 1, 1/16 or 1/64. the TxC.
For Example:

. TxE (Transmitter Empty)

If Baud Rate equals 110 Baud,
TxC equals 110Hz in the 1x mode.
TxC equals 1.72 kHz in the 16x mode.
TxC equals 7.04 kHz in the 64x mode.

When the 8251 A has no characters to send, the
TxEMPTYoutput will go "high." It resets upon receiving a character from CPU if the transmitter is enabled. TxEMPTY remainshigh when the transmitter
is disabled. TxEMPTY clm be used to indicate the
end of a transmission mode, so that the CPU "knows"
when to "turn the . line around" in the half-duplex
operational mode.

The falling edge of TxC shifts the serial data out of
the 8251A.

In the Synchronous mode, a "high" on this output
indicates that a character has. not been loaded and
the SYNC character or characters are about to be or
are being transmitted automatically as "fillers."
TxEMPTY does not go low when the SYNC characters are being shifted out.

The Receiver accepts serial data, converts this serial
input to parallel format, checks for bits or characters
that are unique to the communication technique
and sends an "assembled" character to the CPU.
Serial data is input to RxD pin, and is clocked in on
the rising edge of RxC ..

Receiver Buffer

205222-002

8251A

Receiver Control

RxC (Receiver Clock)

This functional block manages all receiver-related
activities which consists of the following features.

The Receiver Clock controls the rate at which the
character is to be received. In Synchronous Mode,
the Baud Rate (1 x) is equal to the actual frequency of
RxC. In Asynchronous Mode, the Baud Rate is a
fraction of the actual RxC frequency. A portion' of
the mode instruction selects this factor: 1, 1/16 or
1/64 the RxC.

The RxD initialization circuit prevents the 8251A
from mistaking an unused input line for an active
low data line in the "break condition." Before
starting to receive serial characters on the RxD
line, a valid "1" must first be detected after a chip
master Reset. Once this has been determined, a
search for a valid low (Start bit) is enabled. This
feature is only active in the asynchronous mode,
and is only done once for each master Reset.

For example:
Baud Rate equals 300 Baud, if
RxC equals 300 Hz in the 1x mode;
RxC equals 4800 Hz in the 16x mode;
RxC equals 19.2 kHz in the 64x mode.

The False Start bit detection circuit prevents false
starts due to a transient noise spike by first detecting the falling edge and then strobing the nominal
center of the Start bit (RxD = low).

Baud Rate equals 2400 Baud, if
RxC equals 2400 HZ,in the 1x mode;
RxC equals 38.4 kHz in the 16x mode;
RxC equals 153.6 kHz in the 64x mode.

Parity error dete,ction sets the corresponding
status bit.

Data is sampled into the 8251A on the rising edge of
RxC.
NOTE: In most communications systems, the 8251A
will be handling both the trans!l1ission and reception
operations of a single link. Consequently, the
Receive and Transmit Baud Rates will be the same.
Both TxC and RxC will require identical frequencies
for this operation and can be tied together and connected to a single frequency source (Baud 'Rate
Generator) to simplify the interface.

The Framing Error status bit is set if the Stop bit is
absent at the end of the data byte (asynchronous
mode).
.

RxRDY (Receiver Ready)
This output indicates that the 8251 A contains a character that is ready to be inputto the CPU. RxRDY can
be connected to the interrupt structure of the CPU
or, for polled operation, the CPU can check the condition of RxRDY using a Status Read operation.
RxEnable, when off, holds RxRDY in the Reset Condition. For Asynchronous mode, to set RxRDY, the
Receiver must be enabled to sense a Start Bit and a
complete character must be assembled and transferred to the Data Output Register. For Synchronous
mode, to set RxRDY, the Receiver must be enabled
and a character must finish assembly and be transferred to the Data Output Register.
Failure to read the received character from the Rx
Data Output Register prior to the assembly of the
next Rx Data·character will set overrun condition
error and the previous character will be written over
and lost. If the Rx Data is being read by the CPU
when the internal transfer is occurring, overrun error will be set and the old character will be lost.

Figure 5. 8251A Block Diagram Showing
Receiver Buffer and Control Functions

9-5

205222·002

8251A

SYNDET (SYNC. Detect!
BRKDET Break Detect)

DETAILED OPERATION DESCRIPTION
General

This pin is used in Synchronous Mode for SYN"
DET and may be used as either input or output,
programmable through the Control Word. It is reset
to output mode low upon RESET. When used as an
output (internal Sync mode); the SYNDET pin will go
"high" to indicate that the 8251A has located the
SYNC character in the Receive mode. If the 8251 A is
programmed to use double Sync characters (bisync), then SYNDETwili go "high" in the middle of
the last bit of the second Sync character. SYNDET is
automatically reset upon a Status Read operation.
: .

The complete functional definition of the 8251A is
programmed by the system's software. A set of control words must be sent out by the CPU to initialize
the 8251A to support the des.ired communications
format. These control words.will program the: BAUD
RATE, CHARACTER LENGTH, NUMBER OF ,STOP
BITS, SYNCHRONOUS or ASYNCHRONOUS OPERATION, EVEN/ODD/OFF PARITY,. etc. In. the
Synchronous. Mode, options are: .also provided to
select either internal or external character
synchronization,

When used as an input (external SYNC detect mode),
a positive going signal will cause the 825iA to start
assembling data characters on the rising edge of the
next RxC. On'ce in SYNC, the "high" input signal.c:an
be removed. When External SYNC Detect is pro·
grammed, Internal SYNC Detect .is disabled.

Once programmed, the 8251A is ready to perform its
communication functions. The TxRDY output is
raised "high" to signal the CPU that the 8251A is
ready to receive a data character from the CPU. This
output (TxRDY) is reset automatically when the CPU
writes a character into the 8251 A. On the other hand,
the 8251A receives serial data from the MODEM or
I/O device. Upon receiving an entire character, the
RxRDYoutput is raised "high" to signal the CPU that
the 8251A has a complete character ready for the
CPU to fetch. RxRDY is reset automatically upon the
CPU data read operation.

BREAK (Async Mode Only)
This output will go high whenever the receiver
remains low through two consecutive stop bit sequimces (including the start bits, data bits, and
parity bits). Break Detect may' also be read as a
Status bit. It is reset only upon a master chip Reset or
Rx Data returning to a "one" state.

The 82(51A cannot begin transmission until the Tx
Enable (Transmitter Enable) bit is set in the Command Instruction and it has received a ClearToSend
(CTS) input. The TxD output will be held in the marking state upon Reset.

\

ADDRESS BUS

Ao
CONTROL BUS,

I/O R

1I0W RESET

",

\

(TTL)

DATA BUS

•
c/o

cs

°7-0 0

AD

WA

RESET

ciD'" ,

MODE INSTRUCTION

ciD=

1

SYNC CHARACTER 1

:cio=

1

SYNC CHARACTER 2

C/O= 1

COMMAND INSTRUCTION

CID =0

DATA

·c16"

CLK

8251A

1

CID = 0

CID

= 1

}

SYNC MODE
ONLY·

COMMAND INSTRUCTION

DATA

COMMAND INSTRUCTION

·THE SECOND SYNC CHARACTER 19 SKIPPED IF MODE INSTRUCTION HAS PRO·:
GRAMM ED THE 8251" TO SINGLE CHARACTER SYNC MODE. BOTH SYNC
CHARACTERS ARE SKIPPED'IF MODE INSTRUCTION HAS PROGRAMMED THE
8251ATO ASYNC MODE.

Figure 6. 8251A Interface to 8080 Standard
. .
System Bus

Figure 7. Typical Data Block
9-6

205222·002

8251A

the same package. The format definition can be
changed only after a master chip Reset. For explanation purposes the two formats will be isolated.

Programming the 8251A
Prior to starting data transmission or reception, the
8251A must be loaded with a sei of control words
generated by the CPU. These control signals define
the complete functional definition of the 8251A and
must immediately follow a Reset operation (internal
or external).

NOTE: When parity is enabled it is not considered
as one of the data bits for the purpose of programming the word length. The actual parity bit received
on the Rx Data line cannot be read on the Data Bus.
In the case of a programmed character length of less
than 8 bits, the least significant Data Bus bits will
hold the data; unused bits are "don't care" when
writing data to the 8251A, and will be "zeros" when
reading the data from the 8251A.

The control words are split into two formats:
1. Mode Instruction
2. Command Instruction

Mode Instfuction

Asynchronous Mode (Transmission)

This instruction defines the general operational
characteristics of the 8251A. It must follow a Reset
operation (internal or external). Once the Mode Instruction has been written into the 8251A by the
CPU, SYNC characters or Command Instructions
may be written.

Whenever a data character is sent by the CPU the
8251A automatically adds a Start bit (low level) followed by the data bits (least significant bit first), and
the programmed number of Stop bits to each character. Also, an even or odd Parity bit is inserted prior
to the Stop bit(s), as defined by tlie Mode Instruction. The character is then transmitted as a serial
data stream on the TxD output. The serial data is
shifted out on the falling edge ofTxC at a rate equal
to 1,1/16, or 1/64 that of the TxC, as defined by the
Mode Instruction. BREAK characters can be continuously sent to the TxD if commanded to do so.

Command Instruction
This instruction defines a word that·is used to control
the actual operation of the 8251A.
Both the Mode and Command Instructions must
conform to a specified sequence for proper device
operation (see Figure 7). The Mode Instruction must
be written immediately following a Reset
operation, prior to using the 8251A for data
communication.

When no data characters have been loaded into the
8251A the TxD output reamins "high" (marking) unless a Break (continuously low) has been
programmed.
I

,

6

,

.

I s, I s, I I I I I I I

All control words written into the 8251A after the
Mode Instruction will load the Command Instruction. Command Instructions can be written into the
8251Aatany time in the data block during the operation of the 8251 A. To return to the Mode Instruction
format, the master Reset bit in the Command Instruction word can be set to initiate an internal Reset
operation which automatically places the 8251A
back into the Mode Instruction format. Command
Instructions must follow the Mode Instructions or
Sync characters.

EP

PEN

L,

L,

B,

B,

~f

BAUD RAT[ FACTOR

I

0

I

0

I ~b~CE

I

0

0

1

1

!16XI

164XI

I!lX)

I

CHARACTER LENGTH

o
o

I Bl~S

I
I

I 0
1
I
I 1
1 I
1131~S I BI~S I BI~S I
1

0

PARITY ENABLE
0= DISABLE
1 ~ ENABLE

EVEN PARITY GENERATION/CHee
0"000

1: EVEN

NUMBER OF STOP BITS

Mode Instruction Definition

0
0

The 8251A can be used for either Asynchronous or
Synchronous data communication. To understand
how the Mode Instruction defines the functional
operation of the 8251 A, the designer can best view
the device as two separate components, one
Asynchronous and the other Synchronous, sharing

I
I

IINVALID]

1
0

B~T

I
I
" BI~S I
0

1

1

1

BITS

(ONLY AFFECTS Tx; Rx
NEVER REQUIRES MORE
THAN ONE STOP BI1]

Figure 8. Mode Instruction Format,
Asynchronous Mode

9-7

205222-002

inter

8251A

Asynchronous Mode (Receive)

Synchronous Mode (Transmission)

The RxD line is normally high. A falling edge on this
line triggers the beginning of a START bit. The
validity of this START bit is checked by again strobing this bit at its nominal center (16X or 64X mode
only). If a low is detected again, it is a valid START bit,
and the bit counter will start counting.The bit counter thus locates the center of the data bits, the parity
bit (if it exists) and the stop bits. If parity error occurs, the parity error flag is set. Data and parity bits
are sampled on the RxD pin with the rising edge of
RxC. If a low level is detected as the,'STOP bit, the
Framing Error flag will be set. The STOP bit signals
the end of a character. Note that the receiver requires oillyone stop bit, regardless of the number of
sto'p bits programmed. This character is then loaded
into the parallel I/O buffer of the 8251A. The RxRDY
pin is raised to signal the CPU that a character is
ready to be fetched. If a previous character has not
been fetched by the CPU, the present character
replaces it in the I/O buffer, and the OVERRUN Error
flag is raised (thus the previous character is lost). All
of the error flags can be reset by an Error Reset
Instruction. The occurrence of any of these errors
will not affect the operation of the 8251A.

The TxD output is continuously high until the CPU
sends its first character to the 8251Awhich usually is
a SYNC character. When .the CTS line goes low, the
first character is serially transmitted out. All characters are shifted out on the falling edge ofTxC. Data is
shifted out at the same rate as the TxC.
Once transmission has started, the data stream at
the TxD output must continue at the TxC rate. If the
CPU does not provide the 8251A with a data character before the 8251A Transmitter Buffers become
empty, the SYNC characters (or character if in single
SYNC character mode) will be automatically inserted in the TxD data stream. In this case, the
TxEMPTY pin is raised high to signal that the 8251A
is empty and SYNC characters are being sent out.
TxEMPTY does not go low when the SYNC is being
shifted out (see figure below). The TxEMPTY pin is
internally reset by a data character being written
into the 8251A.
AUTOMATICALLY INSERTED BY USART

TxO

I

DATA

I

DATA

I

I \

SYNC 1

I

SYNC

21

DATA

---

1/0 Capacitance

20

pF

Unmeasured pins returned
to GND '

A.C. CHARACTERISTICS
Bus Parameters (Note 1)

(TA

= o·c to 70·C, Vee = 5.0V±5%, GND = OV)*

READ CYCLE

Symbol

Parameter

Min.

Max.

Unit

Test Conditions

tAR

Address Stable Before READ (CS, C/O)

0

ns

Note 2

tRA

Address Hold Time for READ (CS, C/O)

0

ns

Note 2

tRR

READ Pulse Width

tRO

Data Delay from READ

tOF

READ to Data Floating

250

ns
200

ns

10

100

ns

Min.

Max.

Unit

3, CL

= 150pF

WRITE CYCLE

Symbol

Parameter

tAW

Address Stable Before WRITE

0

ns

tWA

Address Hold Time for WRITE

0

ns

tww

WRITE Pulse Width

250

ns

tow

Data Set-Up Time' for WRITE

150

ns

two

Data Hold Time for WRITE

20

ns

tRY

Recovery Time Between WRITES

6

tey

9-12

Test Condtions

Note 4
205222-002

intJ

8251A

A.C. CHARACTERISTICS (Continued)
OTHER TIMINGS
Symbol

Parameter

Min.

Max.

Unit

tCY

Clock Period

320

1350

ns

~

Clock High Pulse Width

120

tCy-9O

ns

~

Clock Low Pulse Width

90

tR, tF

Clock Rise and Fall Time

20

ns

tOTx

TxD Delay from Falling Edge of TxC

1

/J.s

fTx

Transmitter Input Clock Frequency
1x Baud Rate
16x Baud Rate
64x Baud Rate

DC
DC
DC

64
310
615

kHz
kHz
kHz

Transmitter Input Clock Pulse Width
1x Baud Rate
16x and 64x Baud Rate

12
1

tCY
tCY

Transmitter Input Clock Pulse Delay
1x Baud Rate
16x and 64x Baud Rate

15
3

tCY
tCY

Receiver Input Clock Frequency
1x Baud Rate
16x Baud Rate
64x Baud Rate

DC
DC
DC

Receiver Input Clock Pulse Width
1x Baud Rate
16x and 64x Baud Rate

12
1

Receiver Input Clock Pulse Delay
1x Baud Rate
16x and 64x Baud Rate

15
3

tTPW

tTPO

fRx

tRPW

tRPO

tTxROY

TxRDY Pin Delay from Center of Last Bit

tTxROY CLEAR

TxRDY l from Leading Edge of WR

tRxROY

RxRDY Pin Delay from Center of Last Bit

Test Conditions
Notes 5,6

ns

64
310
615

kHz
kHz
kHz
tCY
tCY
tCY
tCY

,

14

tCY

Note?

400

ns

Note?

26

tCY'

Note?

tRxROY CLEAR

RxRDY l from Leading Edge of RD

400

ns

Note?

tiS

Internal SYNDET Delay from Rising
Edge of RxC

26

tCY

Note?

tES

External SYNDET Set-Up Time After
Rising Edge of RxC

tRPo-tCY

ns

Note?

tTxEMPTY

TxEMPTY Delay from Center of Last Bit

20

tCY

Note?

twc

Control Delay from Rising Edge of
WRITE (TxEn, DTR, RTS)

tCY

Note?

tCR

Control to READ Set-Up Time (DSR, CTS)

tCY

Note?

16tCY

8
20

'NOTE:
1. For Extended Temperature EXP"RESS, use MIL 8251A electrical parameters.

9-13

205222-002

8251A

A.C. CHARACTERISTICS (Continued)
NOTES:
1. AC timings measured VOH = 2.0 Val = 2.0, Val = 0.8, and with load circuit of Figure 1.
2. Chip Select (CS) and Command/Data (C/O) are considered as Addresses.
3. Assumes that Address is valid before RD~.
4. This recovery time is for Mode Initialization only. Write Data is allowed only when TxRDY = 1. Recovery Time between
Writes for Asynchronous Mode is 8 tCY and for Synchronous Mode is 16 tCY.
5. TheTxC and RxC frequencies have the following limitations with respect to ClK: For 1x Baud Rate, fTx or fRx ,,; 1/(30
tCY):
For 16x and 64x Baud Rate, fTx or fRx ,,;1/(4.5 tCY).
6. Reset Pulse Width = 6 tCY minimum; System Clock must be running during Reset.
7. Status update can have a maximum delay of 28 clock periods from the event affecting the status.
8. In external sync mode the tes spec. requires the ratio of the system clock (clock) to receive or
transmit bit ratios to be greater than 34.

TYPICAL L\ OUTPUT DELAY VS. L\ CAPACITANCE (pF)

+20

/

+10

->~
Cl
I-

~

I-

::>

..,

0

-10

-20

-100

/

V

/

V

-50

"SPEC.

+50
~

+100

CAPACITANCE (pFI

A.C. TESTING INPUT, OUTPUT WAVEFORM

A.C. TESTING LOAD CIRCUIT

INPUT/OUTPUT

2'

=:><2.0 >

rEST POINTS

045

0.8

~OUT

<2.0lC

Dt

08

A.C. TESTING: INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC" I" AND 0,45V FOR
A LOGIC "0." TIMING MEASUREMENTS ARE MADE AT 2.0V FOA A LOGIC ''1'
AND O.BV FOR A LOGIC "0."

9-14

205222·002

inter

8251A

WAVEFORMS
SYSTEM CLOCK INPUT

CLOCK ¢

TRANSMITTER CLOCK AND DATA
Tif I " MODE)

T'iil: (lSxMODEI

TIC DATA.

RECEIVER CLOCK AND DATA
RIC DATA

RiC Ib MODE)
RiCC 116 MODEl
tNT SAMPLING
PULSE

WRITE DATA CYCLE (CPU -> USART)
T_ROV

OAT A IN 10.B.I

_ ______~DO~N~.T~C~A~R.~__~~~~~~--~DO~N.!T~CA~R~E--­

ci!!

READ DATA CYCLE (CPU - USART)
R,RDY _______~I

M -----------------~
DATA OUT (0.•. 1 _____...!D!!!A~TA~FL~O~AT!.._____+t~~~~~~~~~

ci!!

---------------~_4------------~-L-----

9-15

205222-002
AFN-01573D

intJ

8251 A

WAVEFORMS (Continued)
WRITE CONTROL OR OUTPUT PORT CYCLE (CPU ~ USART)
D-ffi.R1ffi------~------~--------~~~~r--------­
(NOTE =11

.

~ -1-----

~------------~~~--~--------­
I-"DW -

DATA IN 10.B.1

1-

--I ""A

'AW

Clo _____________-',r,

co

::I1WD

.:.....--------'------:~::t==t:J----"----:----'1\,,___________

_______~I-'~
~lr.1W~A~------________...r:t
\i.~

READ CONTROL OR INPUT PORT (CPU +- USART)

DSR. rn

-------~

Ad

r----------------------------

)\1<----------:-:-------------------l-lOR-I1
-

INOTE -"

~-----------~---------~_Un----I'RR-----I._-----

j\

~Ii'-I_-'-RD---'"
_I .1- 'OF

--------------------1-4=====tj-~:----

CATAOUT
10.•.
)

-'RAr

-I'AR !--

CID _____________-',r,

~

co .:.....-'-_________1'AR I--

- 'RA,t;=---

NOTE #1: Twc INCLUDES THE RESPdNSE TIMING OF A CONTROL BYTE.
NOTE #~: TCA INCLUDes THE ~FFECT O.F CTS ON ~HE TxENBL CIRCUITRY.

TRANSMITTER CONTROL AND FLAG TIMING (ASYNC MODE)

ITxEMPTY

fST~~~';; ---------~

Til A~:~~

-----o$J

CID

TxDATA
DATA CHAR 1

EXAMP~E

DATA CHAR 2

DATA CHAR 3

FORMAT" 7 81T CHARACTER WITH PARITY l!a 2 STOP BITS.

9-16

205222-002

inter

8251A

WAVEFORMS (Continued)
RECEIVER CONTROL AND FLAG TIMING (ASYNC MODE)
fH"~~"..~~~:~T~ --------------------~r---l-I------I_---U...

t~~'UA~~~~?T~ -----------;c:-:=::--------1~1'----I----+--+-------+----

----------~~~r---~=+----~r-~r__r--------~------

CO---!.'A".'

II

f--1 ~
u~--~+-~--+-------,y~

,---------H---~----_H_.

/
",.. L.

~-+--~I~

----_.~.r"n
..T,n","(1,rI,"'f!f!!!!!l~

•• "'"

un

~~

H

TRANSMITTER CONTROL AND FLAG TIMING (SYNC MODE)

EXAMPLE FORMAT. 5 81T CHARACTER WITH PARITY, 2 SYNC CHARACTERS

RECEIVER CONTROL AND FLAG TIMING (SYNC MODE)
SYI--DATA
CHARl

.. 0'1,

t

•

l-!-"AR .,., "G'.'! II I I I I

.. 0 '

AdSVNC
CHARI

wr

I---

L

.1- ........

III

SVNe CHAR

i!

r---

RdDATA

.-----

,,0 ",0 ..

DATA \..

DATA
CHAR 1

DON'TeARE

••

,

11'

CHAR 2

c.,

I"

fu- GHAR,:.

ETC.

:y

BEGINS

EXIT HUNT MODE

SET SYNC DET

RdSTATUS

HO

.1U1

LUll HUNT MOOE

NOTE
NOTE

--

\>1

CHAR I

JU1IU1f

A.CLOCK

I--

RdSTAYUS

RdDATA
CHAR I

ODN',

...

1~·"~'r

(t;:~u,

SfT SVN DET (STATUS BIT!

I

1 INTERNAL SYNC, 2 SYNC CHARACTERS, S BITS, WITH PARITY
2 EXTERNAL SYNC, 5 BITS, WITH PARIT~

9-17

205222-002

8273, 8273-4.
PROGRAMMABLE HDLC/SDLC PROTOCOL
CONTROLLER

•

• Programmable NRZI Encode/Decode
User Programmable Modem
• Two
Control Ports
Digital Phase Locked Loop Clock
• Recovery

CCITT X.25 Compatible

• HDLC/SDLC Compatible
Full Duplex, Half Duplex, or Loop
• SDLC
Operation
Up to 64K Baud Synchronous
• li'ansfers
(56K Baud with 8273-4)
FCS (CRC) Generation and
• Automatic
Checking
Up to 9.6K Baud with On· Board Phase
• Locked
Loop

• Minimum CPU Overhead
Fully Compatible with 8048/8080/80851
• 8088/8086/80188/80186
CPUs

I

• Single +5V Supply

The Intel@ 8273 Programmable HOLC/SOLC protocol Controller is a dedicated device designed to support the 1501
CCITT's HOLC and IBM's SOLC communication line protocols. It is fully compatible with Intel's new hiah performance
microcomputer systems such as the MCS1 88/186'·. A frame level command set is achieved by a unique microprogrammed
dual processor chip architecture. The processing capability supported by the 8273 relieves the system CPU of the low
level real·time tasks normally associated with controllers.

REGISTERS

fIA'ir'D"Ei

PI!;

eLK

'Iii
PlI2

RESET

OBo':"7

T,O

TxDACK

hl

T_ORO
IIiIDICR
AxoRO

iffi

5Pt1
32i'CiK
RTs

Vee

Tx INT

iiii

I'IIj
;rn

I'A;
PA;

fA2
CD

""'NT

en

DBO

T,D

PB, .•

DB.

T,C

ffi

002

RiC

DB4

32iCLK

R,D

Co
~:Z-4

DBS

cs

OPLL

R,D

DB7

A,

GND

Ao

R;c

F'iAGiiET

Figure 2. Pin Configuration

Figure 1. Block Diagram

Intel Corporation Assumes No Responsibility for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses are Implied. Information Contained
Herein Supersedes Previously PUblished Specifications On The Devices From tntel.
NOVEMBER 1983

9-18

©INTEL CORPORATION, 1984

ORDER NUMBER: 210479-002

8273, 8273·4.
types of frames; an Information Frame is used to transfer
data, a Supervisory Frame is used for control purposes,
and a Non-sequenced Frame is used for initialization and
control of the secondary stations.

A BRIEF DESCRIPTION OF HOLC/SOLC
PROTOCOLS
General
The High Level Data Link Control (HOLC) is a standard
communication link protocol established by International
Standards Organization (ISO). HOLC is the discipline
used to implement ISO X.2S packet switching systems.
The Synchronous Data Link Control (SOLC) is an IBM
communication link protocol used to implement the
System Network Architecture (SNA). Both the protocols
are bit oriented, code independent, and ideal for full
duplex communication. Some common applications
include terminal to terminal, terminal to CPU, CPU to
CPU, satellite communication, packet switching and other
high speed data links. In systems which require expensive
cabling and interconnect hardware, any of the two
protocols could be used to simplify interfacing (by going
serial), thereby reducing interconnect hardware costs.
Since both the protocols are speed independent, reducing
interconnect hardware could become an important
application.

Network
10 botti4f!e HOLC and SOLC line protocols, according to a
pre-assigned hierarchy, a PRIMARY (Control) STATION
controls the overall network (data link) and issues
commands to the SECONDARY (Slave) STATIONS. The
latter comply with instructions and respond by sending
appropriate RESPONSES. Whenever a transmitting
station must end transmission prematurely it sends an
ABORT character. Upon detecting an abort character, a
receiving station ignores the transmission block called a
FRAME. Time fill between frames can be accomplished by
transmitting either continuous frame preambles called
FLAGS or an abort character. A time fill within a frame is
not permitted. Whenever a station receives a string of
more that fifteen consecutive ones, the station goes into
an IDLE state.

Frame Characteristics
An important characteristic of a frame is that its contents are made code transparent by use of a zero bit
"nsertion and deletion technique. Thus, the user can adopt
any format or code suitable for his system - it may even
be a computer word length or a "memory dump". The
frame is bit oriented that is, bits, not characters in each
field, have specific meanings. The Frame Check
Sequence (FCS) is an error detection scheme similar to
the Cyclic Redundancy Checkword (CRC) widely used in
magnetic disk storage devices. The Command and
Response information frames contain sequence numbers
in the control fields identifying the sent and received
frames. The sequence numbers are used in Error
Recovery Procedures (ERP) and as implicit acknowledgement of frame communication, enhancing the true fullduplex nature of the HOLC/SOLC protocols.
In contrast, BISYNC is basically half-duplex (two way
alternate) because of necessity to transmit immediate
acknowledgement frames. HOLC/SOLC therefore saves
propagation delay times and have a potential of twice the
throughput rate of BISYNC.
It is possible to use HOLC or SOLC over half duplex lines
but there is a corresponding loss in throughput because
both are primarily designed for full-duplex communication. As in any synchronous system, the bit rate is
determined by the clock bits supplied by the modem,
protocols themselves are speed independent.
A byproduct of the use of zero-bit insertion-deletion
technique is the non-return-to-zero invert (NRZIl data
transmission/reception compatibility. The latter allows
HOLC/SOLC protocols to be used with asynchronous
data communication hardware in which the clocks are
derived from the NRZI encoded data.

References

Frames

IBM Synchronous Data Link Control General Information, IBM, GA27~
3093-1.
Standard Network Accoss Protocol Specification. DATAPAC. TransCanada Telephone System CCGll1
Recommendation X.25, ISO/CCITT March 2, 1976.
IBM 3650 Retail Store System Loop Interface OEM Information, IBM, GA
27-3098-0
Guidebook to Data Communications, Training Manual, HeWlett-Packard
5955-1715
IBM Introduction to Teleprocessing, IBM, GC 20-8095-02
System Network Architecture, Technical Overview, IBM, GA 27-3102
System Network Architecture Format and Protocol, IBM G~ 27-3112

A single communication element is called a FRAME which
can be used for both Link Control and data transfer
purposes. The elements of a frame are the beginning eight
bit FLAG (F) consisting of one zero, six ones, and a zero,
an eight bit ADDRESS FIELD (A), an eight bit CONTROL
FIELD (C), a variable (N-bit) INFORMATION FIELD (I), a
sixteen bit FRAME CHECK SEQUENCE (FCS), and an
eight bit end FLAG (F), having the same bit pattern as the
beginning flag. In HOLC the Address (A) and Control (C)
bytes are extendable. The HOLC and the SOLC use three

OPENING
FLAG (FI

01111110

ADDRESS
FIELD (A)

BBITS

CONTROL
FIELD (C)

SBITS

INFORMATION
FIELD (I)

FRAME CHECK
SEQUENCE (FCS)

CLOSING
FLAG (F)

VARIABLE LENGTH
(ONLY IN I FRAMES)

16 BITS

01111110

Figure 3. Frame Format

9-19

210479-002

inter

8273, 8273-4

Table 1. Pin Description
Symbol
Vcc
GND

Name and Function

Symbol

Pin
No. Type

40

Power Supply: +5V Supply.

32XClK

25

I

20

Ground: Ground.

32X Clock: The 32X clock is used to
provide clock recovery when an
asynchronous modem is used. In'
loop configuration the loop stalion
can run without an accurate 1X clock
by using the 32X ClK in conjunction
with the DPll output. (This pin must
be grounded when not used.)

DPll

23

0

Digital Phase locked Loop: Digital
Phase loc,ked loop output can be
tied to RxC and/orTxC when 1X clock
is not available. DPll is used with
32X ClK.

1

0

Flag Detect: Flag Detect signals that
a flag (01111110) has been received
by an active receiver.

Pin
No. Type

Name and Function

4

I

Reset: A high signal on this pin will
force the 8273 to an idle state. The
8273 will remain idle until a command
is issued by the CPU. The modem
interface output signals are forced
high. Reset must be true for a
minimum of 10 TCV.

CS

24

I

Chip Select: The RD and WR inputs
are enabled by the chip select Input.

DB~-DBo

1912

I/O

Data Bus: The Data Bus lines are bidirectional three-state lines which interface with the system Data Bus.

FLAGDET

10

I

Write Input: The Write signal is used
to control the transfer of either a
command or data ,from CPU to the
8273.

RTS

35

0

Request to Send: Request to Send
signals that the 8273 is ready to trans-

CTS

30

I

Clear to Send: Clear to Send signals
that the modem is ready to accept
data from the 8273.

CD

31

I

Carrier Detect: Carrier Detect signals that the line transmission has
started and the 8273 may begin to
sample data on RxD line.

PA2-4

3234

I

Ganeral purpose Input ports: The
logic levels on these lines can be
Read by the CPU through the Data
Bus Buffer.

PB,_.

3639

0

General purpose output ports: The
CPU can write these output lines
through Data Bus Buffer.

ClK

3

I

Clock: A square wave TTL clock.

RESET

WR

RD

9

I

Read Input: The Read signal is used
to control the transfer of either a data
byte or a status word from the 8273
to the CPU.

TxlNT

2

0

Transmitter Interrupt: The Transmitter Interrupt signal indicates that
the transmitter logic requires service.

RxINT

11

0

Receiver Interrupt: The Receiver
interrupt signal indicates that the Receiver logic requires service.

TxDRQ

,6

0

Transmitter Data Request: Requests a transfer of data between
memory and the 8273 for a transmit
operation.

RxRDQ

8

0

Receiver DMA Request: Requests a
transfer of data between the 8273 and
memory for a receive operation.

TxDACK

5

I

Transmitter DMA Acknowledge:
The Transmitter DMA acknowledge
signal notifies the 8273 that the
TxDMA cycle has been granted.

'RxDACK

7

I

Receiver DMA Acknowledge: The
Receiver DMA acknowledge signal
notifies the 8273 that the RxDMA
cycle has been granted.

A,-Ao

2221

I

Address: These two lines are CPU
Interface Register Select lines.

TxD

29

0

Transmitter Data: This line transmits the serial data to the communication channel.

TxC

28

I

Transmitter Clock: The transmitter
clock is used to synchronize the
transmit data.

RxD

26

I

RxC

27

I

Receiver Data: This line receives
serial data from the communication
channeL
Receiver Clock: The Receiver Clock
is used to synchronize the receive
data.

mitd~ta.

FUNCTIONAL DESCRIPTION
General
The Intel@) 8273 HDLC/SDLC controller is a microcomputer peripheral device which supports the International
Standards Organization (ISO) High Level Data Link
Control (HDLC), and IBM Synchronous Data Link Control
(SDlC) communications protocols. This controller
minimizes CPU software by supporting a comprehensive
frame-level instruction set and by hardware implementation of the low level tasks associated with frame
assembly/disassembly and data integrity. The 8273 can be
used in either synchronous or asynchronous applications.
In asynchronous applications the data can be programmed to be encoded/decoded in NRZI code. The clock is
derived from the NRZI data using a digital phase locked
loop. The data transparency is aChieved by using a zerobit insertion/deletion technique. The frames are automatically checked for errors during reception by verifying the
Frame Check Sequence (FCS); the FCS is automatically
generated and appended before the final flag in transmit.

9-20

210479-002

intJ

8273, ·8273·4

The 8273 recognizes and can generate flags (01111110'
Abort, Idle, and GA (EOP) characters.
The 8273 can assume either a primary (control) or a
secondary (slave) role. It can therefore be readiiy
implemented in an SDLC loop configuration as typified by
the IBM 3650 Retail Store System by programming the
8273 into a one-bit delay mode. In sucha configuration, a
two wire pair can be effectively used for data transfer
between controllers and loop stations. The digital phase
locked loop output pin can be used by the loop station
without the. presence of an accurate Tx clock.

CPU Inte(face

Al

Ao

TxDACK

RxDACK

0
0
0
0

0
0

1
1
1
1

0

1
1
1
1
1
1

0

1
1
I'
1
1
1
1
1
1

1

0'

X
X

1
1
o.
1
1

X
X

f
1

cs

liD

WI!

Register

0
0
0
0
0
0
0
0

1

0

Command
Status
Parameter
Result
Reset
TxlNT Result

1
1

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

-

RxlNT Result
Transmit Data
Receive Data

Register Description

.

The CPU interface is optimized for the MCS-80/85'· bus
with an 8257 DMA controller. However, the interface is
flexible, and allows either DMA or non-DMA data
transfers; interrupt or non-interrupt driven. It further
allows maximum line utilization by providing early
interrupt mechanism for buffered (only the information
field can be transferred to memory) ·Tx command overlapping. It also provides separate Rx and Tx interrupt'
output channels for efficient operation. The 8273 keeps
th~ interrupt request active until all the associated
interrupt results have been read.
The CPU utilizes the CPU interface to specify commands
and transfer data. It consists of seven registers addressed
via CS, AI, Ao, RD and WR signals and two i'ndependent
data registers for receive data and transmit data. AI, ~o are
generally derived from two low order bits of the address
bus. If an 8080 based CPU is utilized, the RD and WR
signals may be driven by the 8228 IIOR and I/OW. The
table shows the seven register select decoding:

Command
Operations are initiated by writing an appropriate
command in the COf11mand Register.,
Parameter
Parameters pfcommands that require additional informa.
tion are written 'to this register.
Result
Contains an immediate result describing an outcome of an
executefl command.
Transmit Interrupt Result
Contains the outcome of 8273 transmit operation
(good/bad completion).
Receive Interrupt 'R,esult'
Contains the outcome of. 8273 receive operation (goodl
bad completion), followed by additional results which detail the reason for interrupt.

REGISTERS

Status
The status register reflects the state of the 8273 CPU
Interface.

DMA Data Transfers

T.O

r;c

The 8273 CPU interface supports two independent data
interfaces: receive data and, transmit data. At high data
transmission speeds the data transfer rate of the 8273 i,s
great enough to justify the use of direct memory access
IDMA) for the data transfers. When the 8273 is configured
in DMA mode, the elements of the DMA interfaces are:
TxDRQ: Transmit DMA Request
Requests a transfer of data between memory and the
8273 for a transmit operation.
TxOACK: Transmit DMA Acknowledge
The TxDACK signal notifies the 8273 that a transmit DMA
cycle has been granted. It is also used with VVR to transfer
data to the 8273 in non-DMA mode. Note: RD must not be
asserted while TxDACK is active.

INTERNAL DATA BUS

CPU INTERFACE

RxORQ: Receive DMA Request

MODEM INTERFACE

Requests a'transfer of data between the 8273 and memo
ory for a receive operation.

Figure 4. 8273 Block Diagram Showing CPU
Interface Functions '
9-21

210479-002

inter
RxDACK:

8273, 8273-4,

Receive DMA Acknowledge

The RxDACK Signal notifies the. 8273 that a receive DMA
cycle has been granted. It is also used with RD to read
data from the 8273 in non-DMA mode. Note: WR must not
be asserted while Rxi5ACK Is active.

REGISTERS

RD, WR: Read, Write
The AD and WR signals are used to specify the direction of
the data transfer.
DMA transfers require the use of a DMA controller such as
. the Intel 8257. The function of the DMA controller is to
provide sequential addresses and timing for the transfer,
at a starting address determined by the CPU. Counting of
data block lengths Is performed by the 8273.
To request a DMA transfer the 8273 raises the appropriate
DMA REQUEST. DMA ACKNOWLEDGE and READ enables DMA data onto the bus (independently of CHIP
SELECT). DMA ACKNOWLEDGE and WRITE transfers
DMA data to the 8273 (indepe~dent of CHIP SELECT).

om

_iiXC'Li
iiTi

PB,-.
ill

It is also possible to configure the 8273 in the non-DMA
data transfer mode. In this mode the CPU module must
pass data to the 8273 in response to non-DMA data requests indicated by the status word.

Modem Interface
The 8273 Modem interface provides both dedicated and
user defined modem control functions. All the control
Signals are active low so that EIA RS-232C Inverting
drivers (MC 1488) and inverting receivers (MC 1489) may
be used to interface to standard modems. For asynchronous operation, this interface supports programmable
NRZI data encode/decode, a digital phase locked loop
for efficient clock extraction from NRZI data, and
modem control ports with automatic CrS, CD monitoring andRTS generation. This interface also allows the
8273 to operate In PRE-FRAME SYNC mode in which the
8273 prefixes 16 transitions to a frame to synchronize
idle lines before transmission of the first flag.

INTERNAL DATA aus

Figure 5. 8273 Block Diagram Showing Control
logic Functions

Port B - Output Port

It should be noted that all the 8273 port operations deal
with logical values. for instance, bit DO of Port A will be a
one when ffi (Pin 30).is a phYSical zero (logical one).

During normal operation. if the CPU sets RTS active. the
8273 will not change this pin; however, ifthe CPU setsRi'S
inactive, the 8273 will activate it before each transmission
and deactivate it one byte time after transmission. While
the receiver is active the flag detect pin is pulsed each time
a flag sequence is detected in the receive data stream.
Following an 8273 reset, all pins of Port B are set to a high,
inactive level.

Port A - Input Port
During operati,on, th~273 interrogates.~ pins ffi
(Clear to Send) and CD (Carrier Detect). CTS is used to
condition the start of a transmission. If during transmission C'fS is lost the 8273 generates an interrupt. During
reception. if CD is iost, the 8273 generates an interrupt.

~

. l
~
...

:

-~

MODEM INTERFACE

CPU INTERFACE

~

~

~

~

1

~

~

~

I·

1

IRTS -

ICTS -.CLEAR TO SEND

REQUEST TO SEND

USER DEFINED OUTPul' Pa.. P83. P82. PBl

CD - CARRIER DETECT

US~~~~~~~D :INP~_P~~ P,-,-A",3.C-'PA~2~_

FLAG DETECT

The user defined input bits correspond to the 8273· PA••
PA. and PA, pins. The 8273 does not interrogate or·manipulate these bits.

9-22

The user. defined output bits correspond to the state of
PB4-PB1 pins. The 8273 does not interrogate or manipulate these bits.
210479-002

8273, 8273·4
Serial Data Logic
The Serial data is synchronized by the user transmit (TxC)
and receive (RxC) clocks. The leading edge of TxC
generates new transmit data and the trailing edge of RxC
is used to capture receive data. The NRZI encoding/
decoding of the receive and transmit data is programmable.

circuitry in place of the RxO pin. thus allowing a CPU to
send a message to itself to verify operation of the 8273.
In the selectable clock diagnostic feature. when the data is
looped back. the receiver may be presented incorrect
sample timing by the external circuitry. The user may
select to substitute the TxC pin for the RxC inpu,t on-chip
so that the clock used to generate the loop back data is
used to sample it. Since TxO is generated off the leading
edge of TxC and RxO is sampled on the trailing edge. the
selected clock allows bit synchronism.

The diagnostic features included in the Serial Data logic
are programmable loop back of data and selectable clock
for the receiver. I n the loop-back mode. the data presented
to the TxO pin is internally routed to the receive data input

TxC

TxD

Axe

RxD

/

/

X

\

X

\

\

\

\

\

X

/

I

X

r-

X

/
I

X

/

I

Figure 6. Transmit/Receive Timing

Asynchronous Mode Inte,rface

Although the 8273 is fully compatible with the HOLC/
SOLC communication line protocols. which are,pri,marily
designed for synchronous communication. the 8273 can
also be used in asynchronous applications by using this
interface. The interface employs a digital phase locked
loop (oPLLl for clock recovery from a receive data stream
and programmable NRZI encoding and decoding of data.
The use of NRZI coding with SOLC transmission

guarantees that within a frame. data transitions will occur
at least every five bittimes - the longest sequence of ones
which may be transmitted without zero-bit insertion. The
OPLL should be used only when NRZI coding is used
since the NRZI coding will transmit zero sequence as line
transitions. The digital phase locked loop also facilitates
full-duplex and half-duplex asynchronous implementation with. or without modems.

9-23

210479-002

inter

8273,·8273·4

Digital Phase Locked Loop
In asynchronous applications, the clock is derived from
the receiver data stream by the use of the digital phase
locked loop (DP!-Ll. The DPLL requires a clock inputat32
times the required baud rate. The receive data (RxO) is
sampled with this 32X CLK and the 8273 DPLL supplies a
sample pulse nominally centered on the RxD bit cells. The
DPLL has a built-in "stiffness" which reduces sensitivity to
line noise and bit distortion. This is accomplished by
making phase error adjustments in discrete increments.
Since the nominal pulse is made to occur at 32 counts of
the 32X CLK, these counts are subtracted or added to the
nominal, depending upon which quadrant ofthe four error
quadrants the data edge· occurs in. For example if an RxD
edge is detected in quadrant A 1, it is apparent that the
DPLL sample "A" was placed too close to the trailing edge
of the data cell; sample "S" will then be placed at T =
(T nominal - 2 counts), = 30 counts of the 32X CLK to move
the sample pulse "S" toward the nominal center ofthe next
bit cell. A data edge occuring in quadrant S1 would cause
a smaller adjustment of phase with T = 31 counts of the
32X CLK. Using this technique the DPLL pulse will
converge to nominal bit center within 12 data bit times,
worst case, with constant incoming RxD edges.

A method cif attaining bit synchronism following a line idle
is to use PRE-FRAME SYNC mode of transmission.

RxD

_----IX'-____---'X'--__

X'-___

.:.-_-J

DPiI

j

SAMPLES

)

-~ I: "·1· "
ADJUSTMENT

-2

J. ·1· ..

-1

+1

:1

+2

Figure 7. DPLL Sample Timing

9-24

210479-002

8273, 8273·4
Synchronous Modem - Duplex or Half Duplex Operation
8273

RxC

AxC
AxO
TxC
TxO

32xCLK

~
,/

A

MODEM

K....

AxO

32xC[K

OPLL

f l

GNO

8273

TxC
TxO

MODEM

DPU:

1 1

N.C.

GNO

N.C.

Asynchronous Modems - Duplex or Half Duplex Operation
fiC
8273

TxO

RxC
AxO

32xCLK

I

I
32x
CLOCK

-

-

MODEM

~

/

~

-V

-MODEM

>--

TxC
TxO

8273

AxC
AxO

OPLL

32xCLK

DPLL

I

f
I

I

I

I

32x
CLOCK

I

Asynchronous- No Modems - Duplex or Half Duplex

8273

8273

9-25

210479-002

intJ

8273, 8273·4

SDLe Loop

The OPLL simplifies the SOLe loop station implementation. In this application, each secondary station on a loop
data link is a repeater· set in one-bit delay mode. The
. signals sent out on the loop by the loop controller (primary
station) are relayed from station to station then, back to
the controiler. Any secondary station finding its address in
the A field captures the frame for action at that station. All
received frames are relayed to the next station on the loop.
Loop stations are required to derive bit timing from the
incoming NRZI data stream. The OPLL generates sample
Rx clock timing for reception and uses the same clock to
implement Tx clock timing.

8273
LOOP
CONTROLLER

RxO 1_------.

,....-.....,.----1TxO

TxC TxO

RxD RiC
8273
LOOP
TERMINAL

8273
LOOP
TERMINAL

TxOt-----ir------t---IRxO

Figure 8. SDLC Loop Application

9-26

210479-002

intJ

8273, 8273·4

PRINCIPLES OF OPERATION
The 8273 is an intelligent peripheral controller which
relieves the CPU of many of the rote tasks associated with
constructing and receiving frames. It is fully compatible
wit~ the MCS-80/85'· system bus. As a peripheral device,
it accepts commands from a CPU, executes these
commands and provides an Interrupt and Result back to
the CPU at the end of the execution. The communication
with the CPU is done by activation of CS, RD, WR pins,
while the Al, Ao select the appropriate registers on the
chip as described in the Hardware Description Section.

YES

The 8273 operation is composed of the following
sequence of events:

CPU WRITES COMMAND AND PARAMETERS INTO THE

8273 COMMAND AND PARAMETER REGISTERS.

NO

THE 8273 IS ON ITS OWN TO CARRY OUT THE COMMAND.
THE 8273 SIGNALS THE CPU THAT THE EXECUTION
HAS FINISHED. THE CPU MUST PERFORM A READ

OPERATION OF ONE OR MORE OF THE REGISTERS.
END OF COMMAND PHASE

The Command Phase
During the command phase, the software writes a command to the command register. The command bytes provide a general description of the type of operation requested. Many commands require more detailed information about the command. In such a case up to four
parameters are written into the parameter register. The
flowchart of the command phase indicates that a command may not be issued .if the Status Register indicates
that the device is busy. Similarly if a parameter is issued
when the Parameter Buffer shows full, incorrect operation
will occur.

YES

The 8273 is a duplex device and both transmitter and
receiver may each be executing a command or passing
results at any given time. For this reason separate
interrupt pins are provided. However, the command register must be used for one command sequence at a time.

Figure 9. Command Phase Flowchart

Bit 6 CBF (Command Buffer Full)
Indicates that the command register is full, it is reset when
the 8273 accepts the command byte but does not imply
that execution has begun.

Status Register
The status register contains the status ofthe8273 activity.
The description is as follows ..
o,DsL\;O.

030..0,

Bit 5 CPBF (Command Parameter Buffer Full)
CPBF is set when the parameter buffer is full, and is reset
by the 8273 when it accepts the parameter. The CPU may
poll CPBF to determine when additional parameters may
be written.

Do

I CBSyl CBF ICPBF ICRBF IRxlNTITxlNTIRxlRAI TxlRA I

Bit 7 CBSY (Command Busy)
Bit 4 CRBF (Command Result Buffer Full)

Indicates in-progress command, set for CPU poll when
Command Register is full, reset upon command phase
completion. It is improper to write a command when CBSY
is set; it results in· incorrect operation.

Indicates that an executed command immediate result is
present in ·the Result Register. It is set by 8273 and reset
when CPU reads the result.

9-27

210479-002

inter

8273,8273-4

BII 3 RxlNT (Receiver Interrupt)

Th. Execution Ph.s.

RxlNT indicates that the receiver requires CPU attention;
It Is identical to RxlNT (pin 11) and Is set by the 8273 either
upon good/bad completion of a specified command or by
Non-DMA data transfer. It is reset only after the CPU has
read the result byte or has received a data byte from the
8273 In a Non-DMA data transfer.

Upon accepting the last parameter, the 8273 enters into
the Execution Phase. The execution phase may consist
of a DMA or other activity, and mayor may not require
CPU Intervention. The CPU 'intervention Is eliminated hi
this phase if the system utilizes DMA for the data transfers, otherwise, for non-DMA data transfers, the CPU Is
interrupted by the 8273 via TxlNT and RxlNT pins, for
each data byte request.

Bit 2 TxlNT (Transmitter Interrupt)
The TxlNT indicates that the transmitter requires CPU
attention. It is identical to TxlNT (pin 2). It is set by 8273
either upon good/bad completion of a specified command
or by Non-DMA data transfer. It is reset only after the CPU
has read the result byte or has transferred transmit data
byte to the 8273 in a Non-OMA transfer.

Th. R.sult Phase
During the result phase, the 8273 notifies the CPU of the
execution outcome of a command. This phase is initiated
by: '

Bit 1 RxlRA (Receiver Interrupt Result Available)
The RxlRA is set by the 8273 when an interrupt result
byte is placed In the RxlNT register. It Is reset after the
CPU has read the RxlNT register.
Bit 0 TxlRA (Transmitter

I~terrupt

1. The successful completion of ari operation
2. An error detected during an operation.

Resull Available)

To facilitate quick network software decisions, two types
of execution results are provided:

The TxlRA Is set by the 8273 whim an interrupt result
byte is placed in the TxlNT register. It is reset when the
CPU has read the TxlNT register.

07

06

I,
D7

,
o _

De

Ds

,

03

D.

05

{
·
Y
I

0,-00 received
Dz-Do received
Os-DO received
D4-Do received

0,

Do

0,

I

I

D7 De

M· _ _
Do received

1. An Immediate Result
2. A Non-Immediate Result

.

Ds

0
0
0 - .0

OS-DO received
De-DO received

0
0
0

*Part181 Byte Received

Da Dz D,
0
0
0

0

•

0
0

D4

0
0
0
0
0
0

0
0
0

0
0

0

A1 match or general receive

Active

A2match

Active

CRe error

Active

0

_Abort detected

0

Idle detect

Active
Disabled
Disabled
Activo
Dlaabled
Disabled
Disabled
Dleabled

0

0
0

,1

0

,
1-

n

0

Receiver Interrupt Ruul' Code Rx StatUI Alllr tNT

,

0

0

0

0
0
0
0
0

Do

EOP detected
Frame IS88 than 32 bits

0

DMA overrun detected

1

Memory buffer ~verflow
carrier detect failure

0

Receive Interrupt overrun

Figure 10. Rx Interrupt Result Byte Format

07

06

Os

0

0

0

D.

0,

0,

03

Do

I,

I

D,

0
0

D.
1

I'

D,

1

D,

I

Do

0

Early transmit interrupt
Frame tr!lnsmit complete
OMA underrun

Clear to Send (eTS) error
Ab~ complete

Figure 11. Tx Interrupt Result Byte Format
9-28

210479-002

8273,8273-4
Immediate result Is provided by the 8273 for commands
such as Read Port A and Read Port B which have
information (CTS, CO, RTS, etc'! that the network
software needs to make quick operational decisions.

condition for the interrUpt and, if required, one or more
bytes which detail the condition.'
,
Tx end Rx Interrupt Reault Reg'ate,.

The Result Registers have a result code, the three high
order bits 07-05 of which are set to zero for all but the
receive command. This command result contains a count
that indicates the number of bits received in the last byte. If
a partial byte is received, the high order bits of the last data
byte are i,ndeterminate.

A command which cannot provide an immediate result will
generate an interrupt to signal the beginning ofthe Result
phase. The immediate results are provided in the Result
Register; all non-Immediate results are available IIpon
device interrupt, through Tx Interrupt Result Register
Txl/R or Rx Interrupt Result Register RxI/R. The result
may consist of a one-byte interrupt code indicating the

All results indicated in the command summary must be
read during the result phase.

I DMA
I MODE

I
I
I

I
I
I

YES

'READ STATUS
REGISTER

DATA REQUEST
NON·DMA MODE
USE iil\CK+iiii OR
Wii TO READ OR
WRITE DATA

(

END)

Figure 12. Result Phase Flowchart-Interrupt Results

9-29

210479-002

8273,8273·4
IMMEDIATE RESULTS

---

AFTER COMMAND PHASE COMPLETION (READ PORT A. PORT B)

READ STATUS
REGlS'TER

READ RESULT

REGISTER

Figure 13. (Rx Interrupt Service)

9-30

210479-002

8273,8273-4
DETAILED COMMAND DESCRIPTION

Initialization Set/Reset Commands

General

These commands are used to manipulate data within the
8273 registers. The Set commands have a single parameter which is a mask that corresponds to the bits to be set.
(They perform a logical-OR of the specified register with
the mask provided as a parameter). The Register
commands have a single parameter which is a mask that
has a zero in the bit positions that are to be reset. (They
perform a logical-ANO of the specified register with the
mask).

The 8273 HOLC/SOLC controller supports a comprehensive set of high level commands which allows the 8273 to
be readily used in full-duplex, half-duplex, synchronous,
asynchronous and SOLC loop configuration, with or
without modems. These frame-level commands minimize
CPU and software overhead. The 8273 has address and
control byte buffers which allow the receive and transmit
commands to be used in buffered or non-buffered modes.

Set One-Bit Delay (CMD Code A4)

In buffered transmit mode, the 8273 transmits a flag
automatically, reads the Address and Control buffer
registers and transmits the fields, then via OMA, it fetches
the information field. The 8273, having transmitted the
information field, automatically appends the Frame Check
Sequence (FCS) and the end flag. Correspondingly, in
buffered read mode, the Address and Control fields are
stored in their respective buffer registers and only
Information Field is transferred to memory.

When one bit delay is set, 8273 retransmits the receivea
data stream one bit delayed. This mode is entered at a
receiver character boundary, and should only be used by
.
Loop Stations.

In non-buffered transmit mode, the 8273 transmits the
beginning flag automatically, then fetches and transmits
the Address, Control and Information fields from the
memory, appends the FCS character and an end flag. In
the non-buffered receive mode the entire contents of a
frame are sent to memory with the exception of the flags
and FCS.

Reset One-Bit Delay (CMD Code 64)

IHDLe Implemenation

The 8273 stops the one bit delaye
2.0

D.S

0.45

x=

<.
2.0

TEST POINTS

A.C. TESTING LOAD CIRCUIT

D.S

.

r-:I.

DEVICE

UNDER
TEST

CL =15DPF

A.C. TESTING: INPUTS ARE DRIVEN AT2.4V FOR A LOGIC "1" AND O.45V FOR
A LOGIC "0:' TIMING MEASUREMENTS ARE MADE AT 2.0V FOR A LOGIC "1"

CL = 150pF
CL INCLUDES JIG CAPACITANCE

AND O.8V FOR A LOGIC "0."

WAVEFORMS
IREAD
J
DACK

"0. A,. CS

----.J.

'
-)

'CD

'DC

I--'CA-I

N.

~

'RO

f--tAC-

1---------

.- -

lAD
t KD ·

J(

J

'RR

DATA BUS

J....

I :--'O'---J

r- --- ---

WRITE

DACK

"0. A,. CS

----X

J(

,

0-

X

~
l - - - ' A c -11

IWW

J--ICA --I

'i

X

DATA BUS

'ow

9-43

f.---'wO~

210479-002

intJ

8273,8273-4

WAVEFORMS (Continued)

ORO

DMA

rI ·=+
\~----~--------------------------__

_---II

ca

~OR~

~L_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~_ _ _ __ _

t

==l

Icy

t=-~L=L~H--r

CHIP CLOCK

___..J1

32XCLOCK

TRANSMIT

TxO

,-----·oCL

j

~

,loCY

.1

'oCH-~

.

,

~

-'To-

RECEIVE

)I----~--'oC-L---rt>---_-_.oCH____on--Rxo----.,.~~JL.. ~---------9-44

210479-002

intJ

8273, 8273-4

WAVEFORMS (Continued)
'DPLL OUTPUT

FLAG DETECT OUTPUT

9-45

210479-002

8274
MULTI-PROTOCOL SERIAL
CONTROLLER (MPSC)
• Byte Synchronous:
- Character Synchronization, Int. or Ext.
- One or Two Sync Characters
- Automatic CRC Generation and
Checking (CRC-16)
-IBM Bisync Compatible

• Asynchronous, Byte Synchronous and
Bit Synchronous Operation
• Two Independent Full Duplex
Transmitters and Receivers
• Fully Compatible with 8048, 8051, 8085,
8088, 8086, 80188 and 80186 CPU's; 8257
and 8237DMA Controllers; and 8089 1/0
Proc.

• Bit Synchronous:
- SDLC/HDLC Flag Generation and
Recognition
- 8 Bit Address Recognition
- Automatic Zero Bit Insertion and
Deletion
- Automatic CRC Generation and
Checking (CCITT-16)
- CCITT X.25 Compatible

• 4 Independent DMA Channels
• Baud Rate: DC to 880K Baud
• Asynchronous:
-5-8 Bit Character; Odd, Even, or No
Parity; 1, 1.5 or 2 Stop Bits
-Error Detection: Framing, Overrun,
and Parity .

• Available in EXPRESS
-Standard Temperature Range
-Extended Temperature Range

The Intel® 8274 Multi-Protocol Series Controller (MPSC) is designed to interface High Speed Communications
Lines using Asynchronous, IBM Bisync, and SOLC/HOLC protocol to Intel microcomputer systems. It can be
interfaced with Intel's MCS-48, -85, -51; iAPX-86, -88, -186 and -188 families, the 8237 OMA Controller, or the 8089
I/O Processor inpolled, interrupt driven, or OMA driven modes of operation.
The MPSC is a 40 pin device fabricated using Intel's High Performance HMOS Technology.

OB O•7

CHANNEL A

RE~~I~iAS

Ir---'L

C L K - -_ _ _-,

I!!!ET _ _ _--,

1<:::;:::==:::;>1
I.....

CHANNEL A
CONTROL
LOGIC

IPIIRxDRQe

iNT_--.q

iPi/RxDRQ e

iNT

Ao---.-J

A,----L_ _.J
cs _ _ _--'
CHANNEL B

IH!------'

SYNDETefRTS e

WII _ _ _ _ _-'

me
RXC e

INTERNAL DATA BUS

SYSTEM INTERFACE

L--_ _ _ _ _

...r~-RxDB

NETWORK INTERFACE

Figure 1. Block Diagram

Figure 2. Pin Configuration

Intel Corporation Assumes No Responsibility for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent licenses are Implied. Information Contained,

Herein Supersedes Previously Published Specifications On The Devices From Intel.
©INTEL CORPORATION, 1984

9-46

170102-001

inter

8274

Table 1. Pin Description
Symbol
ClK

Pin
No.
1

Type
I

m:m

2

I

rn5A

3

I

Rxc.

4

CD.

5

I

CTSe

6

I

TxC.

7

I

I

TxDa

8

0

RxD.

9

I

~

10

lio

iRTS.

Pin
No.
11

Type

DB7

12

1/0

DB6
DB5
DB4
DB3
DB2
DBl
DBO
GND
Vee
CTS.

13
14
15
16
17
18
19
20
40
39

I

RTS.

38

0

TxD.

37

0

TxC.

36

I

RxG"

35

I

RxD.

34

I

SYNDET.

33

1/0

RDY.I

32

0

31

0

Symbol

Name and Function
Clock: System clock, TTL compatible.
Reset: A low signal on this pin will
force the MPSC to an idle state. TxD.
and TxD. are forced high. The
modem interface output signals are
forced high. The MPSC will remain
idle until the control registers are
initialized. Reset must be true for one
complete ClK cycle.
Carrier Detect (Channel A): This·
interface signal is supplied by the
modem to indicate that a data carrier
signal has been detected and that a
valid data signal is present on the
RxD. line. If the auto enable control
is set the 8274 will not enable the
serial receiver until rn5. has been
activated.
Receive Clock (Channel B): The
serial data are shifted into the Re·
ceive Data input (RxD.) on the rising
edge of the Receive Clock.
Carrier Detect (Channel B): This
Interface signal is supplied by the
modem to indicate that a data carrier
signal has been detected and that a
valid data signal is present on the
RxD. line. If the auto enable control
is set the 8274 will not enable the
serial receiver until CD. has been
activated.
Clear to Send (Channel B): This
interface signal is supplied by the
modem in response to an active Ri'S
signal. Ci'S indicates that the data
terminallcomputerequipment is permitted to transmit data. In addition, if
the auto enabie control Is set, the
8274 will not transmit data bytes until
Ci'S has been activated.
11'ansmlt Clock (Channel B):. The
serial data are shifted out from the
Transmit Data output (TxD.) on the
falling edge of the Transmit Clock.
11'ansmlt Data (Channel B): This pin
transmits serial data to the communications channel (Channel B).
Receive Data (Channel B): This pin
receives serial data from the communications channel (Channel B).
Synchronous Detection (Channel B):
This pin is used in byte synchronous
mode as either an internal sync
detect (output) or as a means to
force external synchronization (in·
put). In SDlC mode, this pin is' an
output indicating Flag detection. In
asynchronous mode it is a general
purpose input (Channel B).

RDY.I

0

TxDRO.

RxDRO.
Request to Send (Channel B): General purpose output, generally used
to signal that Channel B is ready to
send data.
SYNDET. or RTS. selection is done
by WR2; 07, (Channel A)

DTR.

9-47

Name and Function
Ready (Channel B)/Transmltler DMA
Request (Channel A): In mode 0 this
pin is ROY. and is used to synchronize data transfers between the
processor and the MPSC (Channel
B). In modes 1 and 2 this pin is
TxDRO. and is used by the Channel
A transmitter to request a DMA
transfer.
Data Bus: The Data Bus lines are bidirectional three state lines which
interface with the system's Data Bus.

Ground.
Power: +5V Supply.
Clear to Send (Ohannel A): This
interface signal is supplied by the
Modem in response to an active Ri'S
signal. CTS indicates that the data
terminallcomputer equipment is permitted to transmit data. In addition, if
the auto enable control is set, the
8274 will not transmit data bytes until
CTS has been activated.
Request To Send (Channel A): general purpose output commonly used
to signal that Channel A is ready to
send data.
Transmit Data (Channel A): This pin
transmits serial data to the communications channel (Channel A).
Transmit Clock (Channel A): The
serial data are shifted out from the
Transmit Data output (TxD.) ori the
falling edge of the Transmit Clock.
Receive Clock (Channel A): The
serial data are shifted into the Receive Data input (RxD.) on the rising
edge of the Receive Clock.
Receive Data (Channel A): This pin
receives serial data from the communications channel (Channel A).
Synchronous Detection (Channel A):
This pin is used in byte synchronous
mode as either an internal sync
detect (output) or as a means to
force external synchronization (input). In SDlC mode, this pin is an
output indicating flag detection. In
asynchronous mode it is a general
purpose input (Channel A).
Ready: In mode 0 this pin is ROY.
and is used to synchronize data
transfers between the processor
and the MPSC (Channel A). In'
modes 1 and 2 this pin is RxDRO.
and is used by the channel A receiver
to request a DMA transfer.
Data Terminal Ready (Channel A):
General purpose output.
170102-001

8274

Thble 1. Pin Description
Symbol
~
TxDROa

IPI/
RxDROa

J1\l't

Pin
No.
30

29

28

1\'pe
0

I/O

0

1\'pe

Jm'A

Pin
No.
27

l:i'm.

26

0

At,

25

I

A,

24

I

~

23

I

I'm

22

I

WR

21

I

Symbol

Name and Function
Interrupt Priority Qutlll'ansmitter
DMA Request (Channel Bl: In modes
o and 1, this pin is Interrupt Priority
Out. It is used to establish a hardware
interrupt prlorlt~cheme with iPi. It
is low only if I P is low and the
controlling processor is not servicing
an interruptfrom this MPSC. In mode
2 It Is TxDROa and is used to request
a DMA cycle for a transmit operation
(Channel B).
Interrupt Priority In/Receiver DMA
ReqUesfpfChannel Bl: In modes 0
and 1, I I is Interrupt Priority In. A
low on IPI means that no higher
priority device is being serviced by
the controlling processor's Interrupt
service routine. In mode 2 this pin is
RxDROa and is used to request a
DMA cycle for a receive operation
(Channel B). In Interrupt mode, this
pin must be tied low.
Interrupt: The interrupt signal indicates thatthe highest priority internal
interrupt requires service (open collector). Priority can be resolved via
an external interrupt controiler or a
daisy-chaln scheme.

I

Name and Function
Interrupt Acknowledge: This Interrupt Ackowledge signal allows the
highest priority interrupting device
to generate an interrupt vector. This
pin must be pulled high (inactive) in
non-vector mode.
Data litrmlnal Ready (Channel Bl:
This Isa general purpose output.
Address: This line selects Channel A
or B during data or command transfers. A low selects Channel A.
Address: This line selects between
data 'or command information transfer. A low means data.
Chip Select: This signal selects the
MSPC and enables reading from or
writing into its registers
Read: Read controls a data byte or
status byte transfer from the MPSC
to the CPU.
Write: Write controls transfer of data
or commands to the MPSC.

RESET

FUNCTIONAL DESCRIPTION

When the 8274 RESET line is activated, both MPSC
channels enter the idle state. The serial output Ii nes are
forced to the marking state (high) and the .modem
interface signals (R'fS, OTR) are forced high. In addition, the pointers registers are set to zero.

Additional information on Asynchronous and Synchronous Communications with the 8274 is available
respectively in the Applications Notes AP 134 and AP
145.
Command, parameter, and status information is stored
in 21 registers within the MPSC 18 writable registers for
each channel, 2 readable registers for Channel A and 3
readable registers for Channel B).

GENERAL DESCRIPTION
The Intel 8274 Multi-Protocol Serial Controller is a
microcomputer peripheral device which supports
Asynchronous, Byte Synchronous (Monosync, IBM
Bisync), and Bit Synchronous (ISO's HOLC, IBM's
SOLC) protocols. This controller's flexible architecture
allows easy implementation of many variations of these
three protocols with low software and hardware
overhead.

In the following discussion, the writable registers will
be referred to as WRO throughWR7 and the readable
registers will be referred to as RRO through RR2.
This section of the data sheet describes how the
Asynchronous and Synchronous protocols are implemented iri the MPSC. It describes general considerations, transmit operation, and receive operation for
Asynchronous, Byte Synchronous, and Bit Synchronous protocols.

The Multi-Protocol Serial controller (MPSC) implements two independent serial receiver/transmitter
channels.
The MPSC supports several microprocessor interface
options: Polled, Wait, Interrupt driven and OMA driven.
The MPSC is designed to support INTEL'S MCS-85
and iAPX 86,88,186,188 families.

9-48

170102·001

8274

ASYNCHRONOUS OPERATIONS

7. Transmitter Enable. The serial channel transmitter
operation may be enabled or disabled by setting or
clearing bit 3 of WR5

TRANSMITTER/RECEIVER INITIALIZATION

8. Interrupt Mode.

(See Detailed Command Description Section for complete information)

For data transmission via a modem or RS-232-C
interface, the following information must also be
specified:

In orderto operate in asynchronous mode, each MPSC
channel must be initialized with the following information:

1. The Request To Send (RTS) (WR5; D1) and Data
Terminal Ready (DTR) (WR5; D7) bits must be set
along with tlie Transmit Enable bit (WR5; D3).

1.. Transmit/Receive Clock Rate. This parameter is
specified by bits 6 and 7 of WR4. The clock rate may
be set to 1,16,32, or 64 times the data-link bit rate. If
the X1 clock mode is selected, the bit synchronization must. be accomplished externally.

2. Auto Enable may be set to allow the MPSC to
automatically enable the channel transmitter when
the clear-'to-send signal is active and to automatically
enable the receiver when the carrier-detect signal is
active. However, the Transmit Enable bit (WR3; D3)
and Receive Enable bit (WR3; D1) must be set in
order to use the Auto Enable mode. Auto Enable is
controlled by bit 5 of WR3.

2. Number of Stop Bits. This parameter is specified by
bits 2 and 3 of WR4. The number of stop bits may be
set to 1, 1 1/2, or 2.
3. Parity Selection. Parity may be set for odd, even, or
no parity by bits 0 and 1 of WR4.

When loading Initialization parameters into the MPSC,
WR4 information must be written before the WR1, WR3,
WR5 parameters commands.

4. Receiver Character Length. This parameter sets the
length of received characters to 5,6,7, or 8 bits. This
parameter is specified by bits 6 and 7 of WR3.

During initialization, it is desirable to guarantee that the
external/status latches reflect the latest interface
information. Since up to two state changes are
internally stored by the MPSC, at least two Reset
External/Status Interrupt commands must be issued.
This procedure is most easily accomplished by simply
issuing thi~ reset command whenever the pointer
register is set during initialization.

5. Receiver Enabl.e. The serial-channel receiver operation may be enabled or disabled by setting or
clearing bit 0 of WR3.
6. Transmitter Character Length. This parameter sets
the length of transmitted characters to 5, 6, 7, or 8
bits. This parameter is specified by bits 5 and 6 of
WR5. Characters of less than 5 bits in length may be
transmitted by setting the transmitted length to five
bits (set bits 5 and 6 of WR5 to 0).

An MPSC initialization procedure (MPSC$RX$INIT)
for asynchronous communication is listed in Intel
Application Note AP 134.

The MPSC then determines the actual number of
bits to be transmitted from the character data byte.
The bits to be transmitted must be right justified in
the data byte, the next three bits must be set to 0 and
all remaining bits must be set to 1. The following
table illustrates the data formats for transmission of
1 to 5 bits of data:

D7
1
1
1
1

0

D6
1
1
1

0
0

D5 D4 D3 D2 D1
1 1 0 0 0
1 0 0 0 c
0 0 0 c c
0 0 c c c
0 c c c c

DO
c
c
c
c
c

TRANSMIT
The transmitfunction begins when the Transmit Enable
bit (WR5; D3) is set. The MPSC automatically adds the
start bit, the programmed parity bit (odd, even or no
parity) and the programmed number of stop bits (1, 1.5
or 2 bits) to the data character being transmitted. 1.5
stop bits option must be used with X16, X32 or X64
clock options only.

Number·of
Bits Transmitted
(Character Length)
1
2
3
4
5

9-49

170102·001

8274

2. Framing. A framing error will occurif a stop bit,is not
detected immediately following the parity bit (if
parity checki ng is enabled) or immediately following
the most-significant data bit (if parity checking is not
enabled). When a Framing Error is detected, the
Framing Error. bit (RR1; 06) is set. The detection of a
Framing Error lldds an additional 1/2 bit time to the
character time so the Framing Error is not interpreted
as a new start bit.

The serial data are shifted <;lut from the Transmit Oata
(TxO) output on the falling edge of the Transmit Clock
(TxC) input at a rate programmable to 1, 1/16th, 1/32nd,
or 1/64th of the clock rate supplied to the TxC input.
The TxO 'output is held high when the transmitter has
no data to send, unless, under program control, the
Send Break (WR5; 04) command is issued to hold the
TxOlow.

3. Overrun. If the CPU fails to read a data character
while more than three characters have been received,
the Receive Overrun bit (RR1; 05) is set. When this
occurs, the fourth character assembled replaces the
third character in the receive buffers. Only the
overwritten character is flagged with the Receive
Overrun bit. The Receive Overrun bit (RR1, 05) is
reset by the Error Reset command (WRO; OS, 04, 03).

If the External/Status Interrupt bit (WR1; 00) is set, the
and SYNDET are monitored and,if
status of et),
any changes occur for a period oftime greater than the
minimum specified pulse width, an interrupt is generated. CTS is usually monitored using this interrupt
, feature (e.g. Auto Enable option).

rn

The Transmit Buffer Empty bit (RRO; 02) is set by the
MPSC when the data byte from the buffer is loaded in
the transmitshi~ register. Oata should be written to the
MPSC orily when the Tx buffer becomes empty to
prevent overwriting.

ExternallStatus Latches
The MPSC continuously monitors the state of five
external/status conditions:
' ,

Receive
The receive function begins when the,Receive Enable
(WR3; 00) bit is se".lf the Auto Enable (WR3: 05)
option is selected, thEm Carrier Oetect (~D) must also
be low. A valid start bit is detected if a low persists for at
least 1/2 bit time on the Receive Oata (RxO) input.

1. CTS - clear-to-send input pin.
2. CO - carrier-detect input pin.
3. SYNOET - sync-detect input pin. This pin may be
used as a general-purpose input in the asynchronous
communication mode.

The data is sampled at mid-bit time, on the rising edge
of RxC, until the entire character is assembled, The
receiver inserts 1's when a character is less than 8 bits.
If parity (WR4; 00) is enabled and the character is less
than 8 bits the parity bit is not stripped from the
character.

4. BREAK - a break condition (series of space bits on
the receiver input pin).
,5. Tx UNOERRUN/EOM - Transmitter Underrun/End
of Message.

Error Reporting
A change of state in any of these monitored conditions
will cause the associated status bit in RRO to be latched
(and optionally cause an interrupt)'.

The receiver also stores error status for each of the 3
data characters in the data buffer. Three error conditions may be encountered during data reception in the
asynchronous mode:

IftheExternal/Status Interrupt bit (WR1; 00) is enabled,
, Break Oetect (RRO; 07) and' Carrier Detect (RRO; 03)
will cause an interrupt. Reset External/Status interrupts
(WRO; 05,04, 03) will clear Break Oetect and Carrier
Oetect bits if they are set.

1. Parity. If parity bits are computed and transmitted
with each character and the MPSC is set to check
parity (bit 0 in WR4 is set), a parity error will occur
whenever the n umber of "1" bits within the character
(including the parity bit) does not match the
odd/even setting of the parity check flag (bit 1 in
WR4). When a parity error is detected, the parity
error flag (RR1; 04) is set and remains set until it is
reset by the Error Reset command (WRO; OS, 04,

03).

9-50

170102-001

8274

Asynchronous Mode Register Setup

07
00
01
10
11

WR3

05

Rx 5 b/char
Rx 7 b/char
Rx 6 b/char
Rx 8 b/char

00 Xl

WR4

06

AUTO
ENABLE

0

0

02

01

00

0

0

Rx
ENABLE

Clock

01 X16 Clock
10 X32 Clock
11 X64 Clock

WR5

03

04

00
01
10
11

DTR

0

0

Tx:55 b/char
Tx 7 b/char
Tx 6 b/char
Tx 8 b/char

01 1 STOP BIT
10 1V2 STOP BITS
11 2 STOP BITS
Tx
ENABLE

SEND
BREAK

0

EVENI
ODD
PARITY

PARITY
ENABLE

RTS

0

SYNCHRONOUS OPERATIONMONOSYNC, BISYNC
General

Transmit Set-Up-Monosync, Bisync

The MPSC must be initialized with the following parameters: odd or even parity (WR4; 01,00), Xl clock
mode (WR4; 07, 06), 8- or 16-bit sync character
(WR4; 05, 04), CRC polynomial (WR5; 02), Transmitter Enable (WR5; 03), interrupt modes (WR1,
WR2), transmit character length (WR5; 06, 05) and
receive character length (WR3; 07, 06). WR4 parameters must be written before WR1, WR3, WR5,
WR6 and WR7.

Transmit data is held high after channel reset, or if
the transmitter is not enabled. A break may be programmed to generate a spacing line that begins as
soon as the Send Break (WR5~04) bit is set. With the
transmitter fully initialized and enabled, the default
condition is continuous transmission of the 8- or
16-bit sync character.

The data is transmitted on the falling edge of the
Transmit Clock, (TxC) and is received on the rising
edge of Receive Clock (RxC). The Xl clock is used
for both transm it and receive operations for all three
sync modes: Mono, Bi and External.

Using interrupts for data transfer requires that the
Transmit InterrupVDMA Enable bit (WR1; bl) be set.
An interrupt is generated each timethe transmit buffer becomes empty. The interrupt can be satisfied

Synchronous Mode Register Setup-Monosync, Bisync

07
WR3

00
01
10
11

06

Rx 5 b/char
Rx 7 b/char
Rx 6 b/char
Rx 8 b/char

WR4

0

WR5

DTR

0

00
01
10
11

05
AUTO
ENABLE

00

SYNC
CHAR
LOAD
INHIBIT

Rx
ENABLE

03

02

ENTER
HUNT
MODE

Rx CRC
ENABLE

0

0

0

EVENI
ODD
PARITY

Tx
ENABLE

1
(SELECTS
CRC-16)

RTS

00 8 bit Sync
01 16 bit Sync
11 Ext Sync
Tx:55 b/char
Tx 7 b/char
Tx 6 b/char
Tx 8 b/char

01

04

SEND
BREAK

9-51

PARITY
ENABLE

Tx CRC
ENABLE

170102-001

intJ

8274

COMMAND/STATUS
POINTER

"'\
D2

D1

o

o

0

o

o

DO

_I W:

O----I~

-I
-I

·1
·1

R :

W

R

W

R

o:

2

R

3

O--_~

W

R

4

-I

W

R

W

R

W

R

-I
-I

I

I

1

1

1MSB

R

R

R

R

R

R

0

2

1

LSB
Read Registers

W

O--_~

1

I

6

1

MSB

LSB
Write Registers

Figure 3. Command/Status Register Architecture (each serial

channel~

After reset, the contents of the pointer registers are
zero. The first write to a command register causes
the data to be loaded into Write Register D (WRD).
The three least significant bits of WRD are loaded
into the Command/Status Pointer. The next read or
write operation accesses the read or write register
selected by the pointer. The pointer is reset after. the
read or write operation is completed.

Command, parameter, and status information is stored
in 21 registers within the MPSC (8 writable registers for
each channel, 2 readable registers for Channel A and 3
readable registers for Channel 8). Theyare all accessed via the command ports.
An internal pOinterregister selects which of the
command or status' registers will be read or written
during a command/status access of an MPSC
channel.

9-52

170102·001

8274

either by writing another character into the transmitter or by resetting the Transmitter Interrupt/OMA
Pending latch with a Reset Transmitter Interrupt/
OMA Pending Command (WRO; 05, 04, 03). If nothing more is written into the transmitter, there can be
no further Transmit Buffer Empty interrupt, but this
situation does cause a Transmit Underrun condition
(RRO; 06).
Oata Transfers using the ROY signal are for software
controlled data transfers such as block moves. ROY
tells the CPU that the MPSC is not ready to accept/
provide data and that the CPU must extend the
output/input cycle. OMA data transfers use the
TxORQ A/B signals which indicate that the transmit
buffer is empty, and that the MPSC is ready to accept
the next data character. If the data character is not
loaded into the MPSC by the time the transmit shift
register is empty, the MPSC enters the Transmit
Underrun condition.
The MPSC has two programmable options for solving the transmit underrun condition: it can insert
sync characters, or it can send the, CRC characters
generated so far, followed by sync characters. Following a chip or channel' reset, the Transmit
Underrun/EOM status bit (RRO; 06) is in a set condition allowing the insertion of sync characters when
there is no data to send. The CRC is not calculated
on these automatically inserted sync characters.
When the CPU detect!! the end of message, a Reset
Transmit Underrun/EOM command can be issued.
This allows CRC to be sent when the transmitter has
no data to send.
In the case of sync insertion, an interrupt is generated only after the first automatically inserted sync
character-has been loaded in the Transmit Shift Register. The status register indicates the Transmit Underrunl
EOM bit and the Transmit Buffer Empty bit are set.
In the case of CRC insertion, the Transmit
Underrun/EOM bit is set and the Transmit Buffer
Empty bit is reset while CRC is being sent. When
CRC has been completely sent, the Transmit Buffer
Empty status bit is set and an interrupt is generated
to indicate to the CPU that another message can
begin (this interrupt occurs because CRC has been
sent and sync has been loaded into the Tx Shift Register). If no more messages are to be sent, the program can terminate transmission by resetting RTS,
and disabling the transmitter (WH5; 03).
Bisync CRC Generation. Setting the Transmit CRC
enable bit (WR5; 00) inaicates CRC accumulation
when the program sends the first data character to
9-53

the MPSC. Although the MPSC automatically
transmits up to two sync characters (16 bit sync), it is
wise to send a few more sync characters ahead of
the message (before enabling Transmit CRC) to
ensure synchronization at the receiving end.
The Transm it CRC Enable bitcan be changed on the
fly any time in the message to include or exclude a
particular data character from CRC accumulation.
The Transmit CRC Enable bit should be in the desired state when the data character is loaded into
the transmit shift register. To ensure this bit in the
proper state, the Transmit CRC Enable bit must be
issued before sending the data character to the
MPSC.
Transmit Transparent Mode. Transparent mode
(Bisync protocol) operation is made possible by the
ability to change Transmit CRC Enable on the fly and
by the additional capability of inserting 16 bit sync
characters. Exclusion of OLE characters from CRC
calculation can be achieved by disabling CRC calculation immediately preceding the OLE character
transfer to the MPSC.
'
In the transmit mode, the transmitter always sends
the programmed number of sync bits (8 or 16) (WR4;
05, 04). When in the Monosync mode, the transmitter sends from WR6 and the receiver compares
against WR7. One of two CRC polynomials, CRC 16
or SOLC, may be used with synchronous modes. In
the transmit initialization process, the CRC
generator is initialized by setting the Reset Transmit.
CRC Generator command (WRO; D7, 06).
The External/Status interrupt (WR1; 00) mode can
be used to monitor the status of the CTS input as
well as the Transmit Underrun/EOM latch. Optionally, the Auto Enable (WR3; D5) feature can be used
to enable the transmitter when CTS is active. The
first data transfer to the MPSC can begin when the
External/Status interrupt occurs (CTS (RRO; 05)
status bit set) following the Transmit 'Enable command (WR5; 03).

Receive
After a channel reset, the receiver is in the Hunt
phase, during which the MPSC looks for character
synchronization. The Hunt begins only when the receiver is enabled and data transfer begins only when
character synchronization has been achieved. If
character synchronization is lost, the hunt phase
can be re-entered by writing the Enter Hunt Phase
(WR3; 04) bit. The assembly of received data continues until the MPSC is reset or until the receiver is
170102-001

intel'

8274

buffer. Errors and Special Receive Conditions generate a special vector if the Status Affects Vector
(WR1 B; 02) is selected. Also the Parity Error may be
programmed (WR1; 04, 03) not to generate the special vector while in the Interrupt On Every Character
mode.

disabled (by command or by CO while in the Auto
Enables mode) or until the CPU sets the Enter Hunt
Phase bit. Under program control, all the leading
sync characters of the message can be inhibited
from loading the receive buffers by setting the Sync
Character Load Inhibit (WR3; 01) bit. After character
synchronization is achieved the assembled characters are transferred to the receive data FIFO. After
receiving the first data character, the Sync Character
Load Inhibit bit should be reset to zero so that all
characters are received, including the sync characters. This is important because the received CRC
may look like a sync character and not get received.
Oata may be transferred with or without interrupts.
Transferring data without interrupts is used for a
purely polled operation or for off-line conditions.
There are three interrupt modes available for data
transfer: Interrupt on First Character Only, Interrupt
on Every Character, and Special Receive Conditions
Interrupt.
Interrupt on First Character Only mode is normally
used to start a polling loop, a block transfer sequence using ROY to synchronizethe CPU to the incoming data rate, or a OMA transfer using the RxORQ
signal. The MPSC interrupts on the first character
and thereafter only interrupts after a Special Receive Condition is detected. This mode can be
reinitialized using the Enable Interrupt On Next Receive Character (WRO; OS, 04, 03) command which
allows the next character received to generate an
interrupt. Parity Errors do not cause interrupts, but
End of Frame (SOLC operation) and Receive.Overrun do cause interrupts in this.mode. If the external
status interrupts (WR1; 00) are enabled an interrupt
may be generated any time the CO changes state.

The Special Receive Condition interrupt can only
occur while in the Receive Interrupt On First Character Only or the Interrupt On Every Receive Character
modes. The Special Receive Condition interrupt is
caused by the Receive Overrun (RR1 ; 05) error condition. The error status reflects an error in the current word in the receive buffer, in addition to any
Parity or Overrun errors since the last Error Reset
(WRO; OS, 04, 03). The Receive Overrun and' Parity
error status bits are latched and can only be reset by
the Error Reset (WRO; OS, 04, 03) command.
The CRC check result may be obtained by checking
for CRC bit (RR1; 06). This bit gives the valid CRC
result 16 bit times after the second CRC byte has
been read from the MPSC. After reading the second
CRC byte, the user software must read two more
characters (may be sync characters) before checking for CRC result in RR1. Also for proper CRC come
putation by the receiver, the user software must reset
the Receive CRC Checker (WRO; 07, 06) after receiving the first valid data.character. The receive CRC
Enable bit (WR3; 03) may also be enabled at this
time.

SYNCHRONOUS OPERATION-SOLC

General
Like the, other synchronous operations the SOLC
mode must be initialized vilith the following parameters: SOLC mode (WR4; OS, 04), SOLC polynomial
(WRS; 02), Request to Send, Oata Terminal Ready,

Interrupt On Every Character mode generates an
interrupt whenever a character enters the receive

Synchronous Mode Register Setup-SOLC/HOLC

07
WR3

00
01
10
11

Rx
Rx
Rx
Rx

0

WR4
WRS

DTR

06
5b/char
7b/char
6b/char
8b/char
0

05

04

03

02

01

00

AUTO
ENABLES

ENTER
HUNT
MODE

Rx
CRC
ENABLE

ADDRESS
SEARCH
MODE

0

Rx
ENABLE

0

0

0

0

RTS

TX'
CRC
ENABLE

1
0
(SELECTS SDLCI
HDLC MODE)

00 Tx ~5b/char
01 Tx 7b/char
10 Tx 6b/char
11 Tx 8b/char

SEND
BREAK

9-54

Tx
eNABLE

0
(SELECTS
SDLCI
HDLC
CRC)

170102-001

intel'

8274

Receive

transmit character length (WRS; D6, DS), interrupt
modes (WR1; WR2), Transmit Enable (WRS; D3),
Receive Enable (WR3; DO), Auto Enable (WR3; DS)
and External/Status Interrupt (WR1; DO).WR4
parameters must be written before WR1, WR3,
WRS, WR6 and WR7.

After initialization, the MPSC enters the Hunt phase,
and remains in the Hunt phase until the first Flag is
received. The MPSC never again enters the Hunt
phase unless the microprocessor writes the Enter
Hunt command. The MPSC will also detect flags
separated by a single zero. For example, the bit pattern 011111101111110 will be detected as two flags.

The Interrupt modes for SDLC operation are similar
to those discussed previously in the synchronous
operations section.

The MPSC can be programmed to receive all frames
or it can be programmed to the Address Search
Mode. In the Address Search Mode, only frames with
addresses that match the value in WR6 or the global
address (OFFH) are received by the MPSC. Extended
address recognition must be done by the microprocessor software.

Transmit
After a channel reset, the MPSC begins sending
SDLC flags.
Following the flags in an SDLC operation the 8-bit
address field, control field and information field may
be sent to the MPSC by the microprocessor. The
MPSC transmits.the Frame Check Sequence using
the Transmit Underrun feature. The MPSC automatically inserts a zero after every sequence of S consecutive 1 's except when transmitting Flags or
Aborts.
.

The control and information fields are received as
data.
SDLC/HDLC CRC calculation does not have an 8-bit
delay, since all characters are included in the calculation, unlike Byte Synchronous Protocols.
Reception of an abort sequence (7 or more 1's) will
cause the Break/Abort bit (RRO; D7) to be set and will
cause an External/Status interrupt, if enabled. After
the Reset External/Status Interrupts Command has
been issued, a second interrupt will occur at the end
ofthe abort sequence.

SDLC-like protocols do not have provision for fill
characters within a message. The M.PSC therefore
automatically terminates an SDLC frame when the
transmit' data buffer and output shift register have
no more bits to send. It does this by sending the two
bytes of CRC and then oneor more flags. This allows
very high-speed transmissions under DMA or CPU
control without requiring the CPU to respond
quickly to the end-of-message situation.

MPSC
Detailed Command/Status Description

After a reset, the Transmit Underrun/EOM status bit
is in the set state and prevents the insertion of CRC
characters during the time there is no data to send.
Flag characters are sent. The MPSC begins to send
the frame when data is written into the transmit buffer. Between the time the first data byte is written,
and the end of the message, the Reset Transmit
Underrun/EOM (WRO; D7, D6) command must be
issued. The Transmit Underrun/EOM status bit (RRO;
D6) is in the reset state at the end of the message
which automatically sends the CRC characters.

GENERAL
The MPSC supports an extremely flexible set of serial and system interface modes.
The system interface to the CPU consists of 8 ports
or buffers:

The MPSC may be programmed to issue a se.nd
Abort command (WRO; DS, D4, D3). This command
causes at least eight 1's but less than fourteen 1'sto
be sent before the line reverts to continuous flags.

CS

A,

A

Read Operation

Write Operation

0
0
0
0
1

0
1
0
1

0
0
1
1

X

X

Ch. A Oala Read
Ch. A Status Read
eh. B Data Read
eh. B Status Read
High Impedance

eh. A Data Write
eh. A Command/Parameter
eh. B Data Write
eh. B Command/Parameter
High Impedance

Data buffers are addressed by A, = 0, and Command
ports are addressed by A, = 1.

9cSS

170102-001

8274

COMMAND/STATUS DESCRIPTION
The following command and status bytes are used
during initialization and execution phases of operation. All Command/Status operations on the two
channels are identical, and independent, except
where noted.

Command 0

NUll-has no effect.

Comrnand 1

Send Abort-causes the generation of eight to thirteen 1's when
in the SOLC mode.

Command 2

Reset External/Status Interruptsresets the latched status bits of
RRO and re-enables them, allowing
interrupts to occur again.

Command 3

Channel Reset-resets the Latched Status bits of RRO, the
interrupt prioritization logic and
all control registers for tile
channel. Four extra system
clock cycles should be allowed
for MPSC reset time before any
additional commands or controls
are written into the channel.

Command 4

Enable Interrupt on Next Receive
Character-if the Interrupt on
First Receive Character mode is
selected, this command reactivates that mode after each complete message fs received to
prepare the MPSC for the next
message.

Command 5

Reset Transmitter Interrupt/DMA
Pending-if
The
Transmit
Interrupt/DMA Enable mode is
selected, the MPSC automatically
interrupts or requests DMA data
transfer when the transm it buffer
becomes empty. When there are no
more characters to be sent,
issuing this command prevents
. further transmitter interrupts or
DMA requests until the next
character has been completely
sent.

Command 6

.Error Re!:let...,...error latches, Parity and Overrun errors in RR1 are
reset.

Command 7

End of Interrupt-resets the
interrupt-in-service latch of the
. highest-priority internal device.
under service.

Detailed Register Description
Write Register 0 (WRO):

COMMAND/STATUS POINTER
REGISTER POINTER

'0

o

NULL CODE
SEND ABORT (SDLC)
RESET EXT/STATUS INTERRUPTS
CHANNEL RESET
ENABLE INTERRUPT ON NEXT R.
CHARACTER
RESET .... INT/DMA PENDING
ERROR RESET
END OF. INTERRUPT

NULL CODE
RESET R. CRC CHECKER
RESET .... CRC GENERATOR
RESET .... UNDERRUN/EOM LATCH

WRO
02,01, DO-Command/Status Register Pointer bits
determ ine which write-register the next byte is to be
written into, or which read-register the nellt byte is to
be read from . After reset, the first byte written into
either channel goes into WRO. Following a read or
write to any register (except WRD) the pointer will
point to WRO.
.

OS, 04, 03-Command bits determine which of the
basic seven commands are to be performed.
9-56

07,06

CRC Reset Code

00

Null-has no effect.

01

Reset Receive CRC Checkerresets the CRC checker to D's. If in
SDLC mode the CRC checker is
initialized to all 1'so
170102-001

8274

10

Reset Transmit CRC Generator
-resets the CRC generator to
O's. If in SDLC mode the CRC
generator's initialized to all 1's.

D1

Transmitter Interrupt/DMA Enable
-allows the MPSC to interrupt or
request a DMA transfer when the
transmitter buffer becomes empty.

11

Reset Tx Underrun/End of Message
Latch.

D2

Status Affects vector-(WR1, D2
active in channel B only.) If this
bit is not set, then the fixed vector,
programmed in WR2, is returned
from an interrupt acknowledge
sequence. If the bit is set then the
vector returned from an interrupt
acknowledge is variable as shown
in the Interrupt Vector Table.

D4, D3

Receive Interrupt Mode

o

Receive Interrupts/DMA Disabled

Write Register 1 (WR1):
LSB

MSB

1 D71 08 1 D51 D4 : 03 1 02 1 01 1 DO 1

'--.,,----I

I

EXT INTERRUPT
ENABLE

TlcINTERRUPTI

0

o

Receive Interrupt on Fi rst Character Only or Special Condition

DMA ENABLE

o
STATUS AFFECTS
VECTOR (CH B ONLY)
(NULL CODE CH A)

1"" VARIABLE
veCTOR
0 FIXED
VECTOR

~

0

0

RxINT/DMA DISABLE

0

1

RxlNT ON FIRST CHAR OR SPECIAL
CONDITION

1

0

INT ON ALL Rx CHAR (PARITY AFFECTS
VECTOR)OR SPECIAL CONDITION

1

1

tNT ON ALL Rx CHAR (PARITY DOES
NOT AFFECT VECTOR) OR SPECIAL
CONDITION

1 == WAIT ON Rx, 0

==

Interrupt on All Receive Characters or Special Condition (Parity
Error is not a Special Receive
Condition).
D5

WAIT ON Tx

MUSTBEZERO

WAIT ENABLE

1

=

ENABLE,O '" DISABLE

WR1

DO

Interrupt on All Receive Characters or Special Condition (Parity
Error is a Special Receive Condition)

External/Status Interrupt Enable
-allows interrupt to occur as the
result of transitions on the CD,
CTS or SYNDET inputs. Also
allows interrupts as the result of a
Break/Abort detection and termination, or at the beginning of CRC,
or sync character transmission
when the Transmit Underrun/EOM
latch becomes set.

9-57

Wait on Receive/Transmit-when
the following conditions are met
the RDY pin is activated, otherwise
it is held in the High-Z state.
(Conditions: Interrupt Enabled
Mode, Wait Enabled, CS = 0,
AO = 0/1, and A1 = 0). The RDY
pin is pulled low when the transmitter buffer is full or the receiver
buffer is empty and it is driven
High when the transmitter buffer is
empty or the receiver buffer is full.
The RDYA and RDY B may be
wired OR connected since only
one signal is active at anyone time
while the other is in the High Z
state.

D6

Must be Zero

D7

Wait Enable-enables the wait
function.

170102-001

8274

WR2

05,04,03

Channel A
01, DO

o

0

o

System Configuration-These
specify the data transfer from
MPSC channels to the CPU, either
interrupt or OMA based.

o

o

X X

Non-vectored interrupts-intended for use with external OMA
CONTROLLER. The Data Bus remains in a high impedence state
during INTA sequences.

o

0

8085 Vector Mode 1-i ntended for
use as the primary MPSC in a daisy
chained priority structure. (See
System Interface section)

o

1

8085 Vector Mode 2-intended for
use as any secondary MPSC in a
daisy chained priority structure.
(See System Interface section)

1 0

8086/88 Vector Mode-intended
for use as either a primary or
secondary in
daisy chained
priority structure. (See System
Interface section)

Channel A and Channel B both use
interrupts
Channel A uses OMA, Channel B
uses interrupt
Channel A and Channel B both
use OMA
Illegal Code

02

Priority-this bit specifies the
relative priorities of the internal
MPSC interrupt/OMA sources.

o

(Highest) RxA, TxA, RxB, TxB
ExTA, ExTB (Lowest)

Interrupt Code-specifies the
behavior of the MPSC when it receives an interrupt acknowledge
sequence from the CPU. (See Interrupt Vector Mode Table).

a

(Highest) RxA, RxB, TxA, TxB,
ExTA, ExTB (Lowest)

Write Register 2 (WR2): Channel A

06

Must be zero.

D7

zero

one
MSB

I 07

Pin 10 = RTSa
Pin 10 = SYNDETa

LSB

: 06

1 05 1 04

1 02 1 01

: 03

'--.,,---J

: 00

I

'--.,,---J
0

0

BOTH INTERRUPT

0

1

A DMA, B INT

1

0

BOTHOMA

1

1

ILLEGAL

1

PRIORI TV RxA

R,B

T,.

T,B

EXTA*

EXTS"

0

PRIORITY RxA

T,'

R,B

T,B

EXTA*

EXTS"

~

0

0

8085 MODE 1

0

1

8085 MODE 2

1

0

8086188 MODE

1

1

ILLEGAL

1
0

VECTORED INTERRUPT
NON VECTORED INTERRUPT
MUST BE ZERO

1

PIN 10

o

PIN 10

SYNDET e

RT5 a

"EXTERNAL STATUS INTERRUPTONLY IF EXT INTERRUPT ENABLE (WR1; 00)15 SET

9-58

170102-001

8274

The following table describes the MPSC's response to an interrupt acknowledge sequence:

05

04

03

IPI

0

X

X

1

0

.1

1

Data Bus

MODE

INTA

X

Non-vectored

Any INTA

High Impedance

0

0

85 Mode 1

1st INTA
2nd INTA
3rd INTA

1
1 0 1
1 1 0 0
V7 V6 V5 V4- V3- V2- Vl VO
0
0 ·0 0
0 0 0 0

0

0

1

85 Mode 1

1st INTA
2nd INTA
3rd INTA

1
1 1 0 0
High Impedance
High Impedance

1

0

0

86 Made

1st INTA
2ndiNTA

V7 V6 V5 V4

1st INTA
2nd INTA
3rd INTA

V7 V6 V5 V4· V3· V2· Vl VO
0 0 0 0
0 0 0 0

1st INTA
2ndiNTA
3rd INTA

High Impedance
High Impedance
High Impedance

1st INTA
2n(lINTA

High Impedance
High Impedance

DO

07

1

0

1

0

85 Mode 2

1

0

1

1

85 Mode 2

1

1

0

1

86 Mode

1

0

1

High Impedance

V3

V2· Vl·VO·

High Impedance

-These bits are variable if the "status affects vector" mode has been programmed, (WRI B, D2).

Interrupt/DMA Mode, Pin Functions, and Priority

Ch.AWR2

Int/OMA
Mode

O2

01

00

CH.A

CH.B

0

0

0

INT

INT

1

0

0

INT

INT

0

0

1

OMA

ROYAl
RxORQA
Pin 32

Pin Functions
IPII
ROYe/·
Rx.ORQ e
TxORQA
Pin 11·
Pin 29

AOYA

1

OMA

- --

-INT
--

0

1

0

OMA

OMA

1

1

0

OMA

OMA

Lowest

iPi.

AOY e

IPO
AxA, AxB, TxA, TxB, EXTA, EXT e
AxA, TxA (OMA)

f-- - - - - - - - - - - - AxOAQA

0

Highest

RxA,TxA,AxB,TxB,EXTkEXTB

--- --INT--

1

Priority

\

IPOI
TxDRQ e
Pin 30

iPi

TxOAQA

AxA 1, AxB, TxB, EXTA' EXT e (INT)

IPO
AxA, TxA (OMA)

f--------------AxA 1, AxB, TxB, EXTA, EXT e (INT)

AxOAQA

TxOAQA

AxA TxA, AxB, TxB (OMA)
AxA \ AxB 1, EXTA, EXTe (INT)
AxOAQe

TxOAQe

AxA, AxB, TxA, TxB, (OMA)
AxA 1, AxB 1, EXTA, EXTe (INT)

lSpecial Aeceive Condition

9-59

170102-001

intJ

8274

Interrupt Vector Mode'Table
8085 Modes,

I 8086/88 Mode

Note 1: Special
Receive Condition=
Parity Error,
Rx Overru n Error,
Ftaming Error,
End oJ Frame (SOLC)

,V4
V2

V3
V1

,

V2

Vo

Channel

0
0
0
0

0
0

0

B

1
1

0

Tx Buffer Empty
Ext/Status Change
Rx Char. Available
Speci'al Rx Condition
(Note 1)

1
1
1
1

0
0

0

A

1
1

0

Tx Buffer Empty
Ext/Status Change
Rx Char. Available
Special Rx Condition
(Note 1)

'

1
1

1
1

Condition

Write Register 2 (WR2): Channel B

WR2 CHANNEL B

MSB

07-00'

LSB

In:w:w:~:~:~: ~:wl

L~

Interrupt vector-This register contains
the value of the interrupt vector piaced
on the data bus during interrupt acknowledge sequences.

Vector

Write Register 3 (WR3):

Rx ENABLE,
SYNC CHAR LOAD INHIBIT
' - - - - ADDR SRCH MODE (SDLC)
' - - - - - - Rx CRC ENABLE
L , - - - - - - - E N T E R HUNT MODE
' - - - - - - - - - - A U T O ENABLES

o ..

Rx 5 BITS/CHAR
Ax 7 BITS/CHAR
Rx 6 BITs/CHAR
Ax 8 BITS/CHAR

9-60

170102-001

inter
WR3
DO

01

8274

Write Register 4 (WR4):

Receiver Enable-A one enables the receiver to begin. This bit should be set only
after the receiver has been initialized.
Sync Character Load Inhibit-A one prevents the receiver from loading sync
characters into the receive buffers. In
SOLC, this bit must be zero.

02

1 '" ENABLE PARITV

o•

1 • EVEN PARITY

o • DDD PARITY

Address Search Mode-If the SOLC mode
has been selected, the MPSC. will receive all frames unless this bit is a 1. If this
bit is a 1, theMPSC will receive only frames
with address bytes that match the global
address (OFFH) or the value loaded into
WR6. This bit must be zero in non-SOLC
modes.
Receive CRC Enable-A one in this bit
enables '(or re-enables) CRC calculation.
CRC calculation starts with the last chC!racter placed in the Receiver FIFO. A zero in
this bit disables, but does not reset, the
Receiver CRC generator.

03

04

Enter Hunt Phase-After initialization, the
MPSC automatically enters the Hunt mode.
If synchronization is lost, the Hunt phase
can bere-entered by writing a one to this
bit.

05

Receive Character length

o

Receive 5 Data bits/character

0

o

9-61

ENABLE SYNC MODES

o

1

1 STOP BIT

1

0

1.5 STDP BITS

1

1

2STOP BITS

8 BIT SYNC CHAR

o

1

18 BIT SYNC CHAR

1

0

SDLClHDLCMODE(Olllll10)FLAG

1

1

EXTERNAL SYNC MODE

0

Xl CLOCK

1

X18CLOCK

1

0

X32 CLOCK

1

1

X84 CLDCK

Parity-a one in .this bit causes a parity
bit to be added to the programmed number
of data bits per character for both the
transmitted and received character. If the
MPSC is programmed to receive 8 bits per
character, the parity bit is not transferred
to the microprocessor. With other receiver
character lengths, the parity bit is transferred to the microprocessor.

01

Even/Odd Parity-if parity is enabled, a
one in this bit causes the MPSC to transmit
and expect even parity, and a zero causes
it to send and expect Odd parity.

03, 02

Stop bits/sync mode

Receive 6 Data bits/character
Receive 8 Data bits/character

0

0

o

Receive 7 Data bits/character

o

o

o

o

WR4
DO

Auto Enable-A one written to this bit causes
CO to be automatic enable signal for. the
receiver and CTS to be an automatic enable
signal for the transmitter. A zero Written to
this bit limits the effect of CD and CTS signals
to setting/resetting their corresponding bits
in the status register (RRO).

07, 06

DISABLE PARITY

170102-001

intJ

8274

00

Selects synchronous modes.

o

Async mode, 1 stop bit/character

o
1

Sync mode select

o

8 bit sync character

o

16 bit sync character

o

o

0

o

01

Request to Send-a one in this bit forces
the RTS pin active (low) and zero in this bit
forces the RTS pin inactive (high).

02

CRC Select-a one in this bit selects the
CRC -16 polynomial (X 16 + X 15 + X2 + 1)
and a zero in this, bit selects the CCITT-CRC
'polynomial (X16 + X12 + X5 + 1). In SOLC
mode, CCITT-CRC must be selected.

03

Transmitter Enable-a zero in this bit
forces a marking state on the transmitter
output. If this bit is set to zero during data
or sync character transmission, the marking state is entered after the character has
been sent. If this ,bit is set to zero during
transmission of a CRC character, sync or
flag bits are substituted, for the remainder
of the CRC bits.

04

Send Break~a one in this bit forces the
transmit data low. Aiero in this bit allows
norrnartransniitter operation.

06, 05

Transmit Character length

o

Transmit 1 - 5 bits/character

SOLC mode (Flag sync)
External sync mode

07, 06

Transmit CRC Enable-:-a one, in this bit
enables the transmitter CRC' generator.
The CRC calculation is done when a
character is moved from the transmit
buffer into the shift register. A zero in this
bit disables CRC calculations. If this bit is
not set when a transmitter underrun
occurs, the CF.lC will not be sent.

Async mode, 1-V2 stop bits/character'
Async mode, 2 stop bits/character

05, 04
0

WR5
DO

Clock mode-selects the clock/data rate
multiplier for both the receiver and the
transmitter. 1x mode must be selected for
synchronous modes. If the 1x mode is
selected, bit synchronization must be done
externally.
Clock rate = Data rate x
Clock rate = Data rate x 16

o

Clock rate = Data rate x 32
Clock rate = Data rate x 64

Write Register 5 (WR5):

RTS

0

o

L -_ _ SDLClCRC-18 (CRC MODE)

Transmit 7 bits/character,

o

' - - - - - ' - ' T x ENABLE

Transmit 6 bits/character

' - -_ _ _ _ _ SEND BREAK

Transmit 8 bits/character
Tx 5 BITS OR LESS/CHAR

Bits to be sent must be right justified least significant
bit first, eg:

Tx 7 BITS/CHAR

Tx 8 BITs/CHAR
Tx 8 BITS/CHAR
L-_ _ _ _ _ _ _ _ _

~R

9-62

07

06

05

04

03

02

01

DO

o

0

B5

B4

B3

B2

B1

BO

170102-001

inter

8274

Five or less mode allows transmission of one to five bits per
character. The microprocessor must format the data in
the following way:
07

0
07

03

02

01

DO

0

0

0

BO

Sends one data bit

0

0

0

B1

BO

Sends two data bits

0

0

0

B2

B1

BO

Sends three data bits

0

0

0

B3

B2

B1

BO

Sends four data bits

0

0

B4

B3

B2

B1

BO

Sends five data bits

06

05

04

Data Terminal Ready--:when set, this bit
forces the OTR pin active (low). When
reset, this bit forces the OTR pin inactive
(high).

Write Register 7 (WR7):

Write Register S (WRS):
MSB

LSB

MSB

·1~:~:~:~:~:M:~:ool

LSB

loo:~:~:~:~:M:~:ool
1Mo., S'gn"'.an'

Least significant
Sync byte (Address

Sync byte (must

in SOLe/HDLe Mode)

be 01111110 In

SOLe/HOLe

WR7
07-00
WRS
07-00

Sync/Address-this register contains the
transmit sync character in Monosync
mode, the low order 8 sync bits in Bisync
mode, or the Address byte in SOLC mode.

9-63

Mode)

Sync/Flag-this register contains the receive sync character in Monosync mode,
the high order 8 sync bits in Bisync mode,
or the Flag character (01111110) in SOLC
mode. WR7 is not used in External Sync
mode.

170102-001

8274

Read Register 0 (RRO):

MS.

LS.

1~1~1~1~lool~I~lool

I

Rx CHAR AVAILABLE
INT IN-SERVICE (CHA only)
Tx BUFFER EMPTY

CARRIER DETECT·
SYNC/HUNT
EXTERNAL STATUS
INTERRUPT MODE

CTS

Tx UNDERRUN/EOM
BREAK/ABORT

RRO
DO

04

Receive Character Available-this bit is
set when the receive FIFO contains data
and is reset when the FIFO is empty.

01

Interrupt In-Service'-If an Internal Interrupt
is pending, this bit is set at the falling edge of .
the second INTA pulse of an INTA cycle. In
non-vectored mode, this bit is set at the falling
edge of RO after pointer 2 is specified. This bit
is reset when an EOI command is issued and
there are no other interrupts in-service at that
time.

02

Transmit Buffer Empty-This bit is set
whenever the transmit buffer is empty
except when CRC characters are being
sent in a synchronous mode. This bit is
reset when ~he transmit buffer is loaded.
This bit is set after an MPSC reset.

03

Carrier Detect-This bit contains the state
of the CO pin atthe time of the last change
of any of the External/Status bits (CD,
CTS, Sync/Hunt, Break/Abort, or Tx
Underrun/EOM). Any change of state of the
CD pin causes the CD bit to be latched and
causes an External/Status interrupt. This bit
indicates current state of the CD pin immediately following a Reset External/Status
Interrupt command.

'This bit is only valid when TPf is active low and is
always zero in Channel B.

9-64

Sync/Hunt-In asynchronous modes, the
operation of this bit is similar to the CD
status bit, except that Sync/Hunt shows the
state of the SYNOET ~Any High-toLow transition on the SYNOET pin sets this
bit, and causes an External/Status interrupt (if enabled). The Reset External/Status
Interrupt command is issued to clear the
interrupt. A Low-to-High transition clears
this bit and sets the External/Status interrupt. When the External/Status interrupt is
set by the change in state of any other input
or condition, this bit shows the inverted
state of the SYNOET pin at time of the
change. This bit must be read ·immediatelt
following a Reset External/Status Interrupt
command to read the current state of the
SYNOET input.
In the External Sync mode, the Sync/Hunt
bit operates in a fashion similar to the
Asynchronous mode, except the Enter
Hunt Mode control bit enables the external
sync detection logic. When the External
Sync Mode and Enter Hunt Mode bits are
set (for example, when the receiver is
enabled following a reset), the SYNOET
input must be held High by the external
logic until external character synchronization is achieved. A High at the SYNOET
input holds the Sync/Hunt status in the
reset condition.
170102-001

inter

8274

When external' synchronization is
achieved, SYNOET must be driven Low on
the second rising edge of RxC after the
rising edge of RxC on which the last bit of
the sync character was received. In other
words, after the sync pattern is detected,
the external logic must wait for two full
Receive Clock cycles to activate the SYNOET input. Once SYNOET is forced Low, it
is good practice to keep it Low until the
CPU informs the external sync logic that
synchronization has been lost or a new
message is about to start. The High-to-Low
transition of the SYNOET output sets the
Sync/Hunt bit, which sets the External/
Status interrupt. The CPU must clear the
interrupt by issuing the Reset External/
Status Interrupt Command.

In the SOLC mode, the Sync/Hunt bit is
initially set by the Enter Hunt mode bit, or
when the receiver is disabled. In any case, it
is reset to D when the opening flag of the
first frame is detected by the MPSC. The
External/Status interrupt is also generated,
and should be handled as discussed
previously.

Unlike the Monosync and Bisync modes,
once the Sync/Hunt bit is reset in the SOLC
mode, it does not need to be set when the
end of message is detected. The MPSC au. tomatically maintains synchronization.
The only way the Sync/Hunt bit can be set
again is by the Enter Hunt Mode bit, or by
disabling the receiver.

When the SYNOET input goes High again,
another External/Status interrupt is. generated that must also be cleared. The Enter
Hunt Mode control bit isset whenever
character synchronization is lost or the end
of message is detected. In this case, the
MPSC again.looks for a High-to-Lowtransition on the SYNOET input and the operation repeats as explained previously. This
implies the CPU should also inform the externallogic that character synchronization
has been lost and that the MPSC is waiting
for SYNOET to become active.

05

Clear to Send-this bit contains the inverted state ofthe CTS pin at the time of the
last change of any of the External/Status
bits (CO, CTS, Sync/Hunt, Break/Abort, or
Tx Underrun/EOM). Any change of state of
the CTS pin causes the CTS bit to be
latched and causes. an External/Status
interrupt. This bit indicates the inverse of
the current state of the CTS pin immediately following a Reset External/
Status Interrupt command.

In the Monosync and Bisync Receive
modes, the Sync/Hunt status bit is initially
set to 1 by the Enter Hunt Mode bit. The
Sync/Hunt bit is reset when the MPSC establishes character synchronization. The
. High-to-Low transition of the Sync/Hunt bit
causes an External/Status interrupt that
must be cleared by the CPU issuing the
Reset External/Status Interupt command.
This enables the MPSC to detect the next
transition of other External/Status bits.

06

Transmitter Underrun/End of Messagethis bit is in a set condition following a reset
(internal or external). The only command
that can reset this bit is the Reset Transmit
Underrun/EOM Latch command (WRD, 0 6
and 0 7 ), When the Transmit Underrun condition occurs, this bit is set, which causes
the External/Status Interrupt which must
be reset by issuing a Reset External/Status
command (WRD; command 2).

When the CPU detects the end of message
or that character synchronization is lost, it
sets the Enter Hunt Mode control bit, which
sets the Sync/Hunt bit to 1. The Low-toHigh transition of the Sync/Hunt bit sets the
External/Status Interrupt, which must also
be 'cleared by the Reset External/Status
Interrupt Command. Note that the SYNOET
pin acts as an output in this mode, and
goes low every time a sync pattern is detected in the data stream.

07

Break/Abort-in the Asynchronous Receive mode, this bit is set when a Break
sequence (null character plus framing
error) is detected in the data stream. The
External/Status interrupt,.if enabled, is set
when break is detected. The interrupt service routine must issue the Reset
External/Status Interrupt command (WRD,
Command 2) to the break detection logic
so the Break sequence termination can be
recognized.

9-65

170102-001

8274

SOLC Residue Code Table (I Field Bits in 2 Previous Bytes)
8 bits/char
RR1
Previous
03,02,01
Byte

7 bits/char

2nd Prevo
Byte

Previous
Byte

6 bits/char

2nd Prevo
Byte

Previous
Byte

5 bits/char

2nd Prevo
Byte

Previous
Byte

2nd Prev
Byte

1

0

0

0

3

0

2

0

1

0

5

0

1

0

0

4

0

3

0

2

0

1

1

1

0

0

5

0

4

0

3

0

2

0

0

1

0

6

0

5

0

4

0

3

1

0

1

0

7

0

6

0

5

0

1

1

0

8

0

-

1

1

1

1

8

-

-

-

-

-

0

0

0

2

8

1

7

0

6

0

The Break/Abort bit is reset when the termination of the Break sequence is detected
in the incoming data stream. The termination of the Break sequence also causes the
External/Status interrupt to be set. The
RElset External/Status Interrupt command
must be issued to enable the break detection logic to look for the next Break sequence. A single extraneous null character
is present in the receiver after the termination of a break; it should be relid and
discarded.

DO

In the SOLC Receive mode, this status bit is
set by the detection of an Abort sequence
(seven or more 1's). The External/Status
interrupt is handled the same way as in the
case of a Break. The Break/Abort bit is not
used in the Synchronous Receive mode.

04

4

All sent-this bit is set when all characters have been sent, in asynchronous
modes. It is reset when characters are in
the transmitter, in asynchronous modes.
In synchronous modes, this bit is always
set.

03, 02, 01 Residue Codes......:bit synchrono'us protocols allow I-fields that are not an integral number of characters. Since transfers from the MPSC to the CPU are character oriented, the residue codes
provide the capability of receiving
leftover bits. Residue bits are right justified in the last two data bytes received.

9-66

Parity Error-If parity is enabled, this bit
. is set for received characters whose parity does not match the programmed
sense (Even/Odd). This bit is latched.
Once an error occurs, it remains set until
the Error Reset command is written.

170102-001

inter

8274

Read Register 1 (RR1): (Special Receive Condition Mode)

MSB

LSB

107 106 1 05 1 04 1 03

: 02 : 0'

1DO 1

~I
~

o

0 0

o

0 ,

o ,

LALLSENT

I FIELD BITS
PREVIOUS BYTE

I FIELD BITS
2ND PREVIOUS BYTE

0

o , ,
,

RESIDUE DATA
8 BITSICHAR. MODE

0 0

,

0

,

,

,

0

,,,
' - -_ _ _ _ _ _ _ _

PAR
TY

ERROR

L . . . . . - - - - - - - - - - R . OVERRUN ERROR
L....._~--------_CRCIFRAMINGERROR

L-_ _ _ _ _ _ _ _ _ _ _ _ _ END OF FRAME (SDLCIHDLC MODE)

05

06

Receive Overrun Error-this bit indicates that the receive FI FO has been
overloaded .by the receiver. The last
character in the FIFO is overwritten and
flagged with this error. Once the overwritten character is read, this error condition is latched until reset by the Error
Reset command. If the MPSC is in the
status affects vector mode, the overrun
causes a special Receive Condition
Vector.

ing error. In synchronous modes, a one
in this bit indicates that the calculated
CRC value does not match the last two
bytes received. It can be reset by issuing
an Error Reset command.

07

CRC/Framing Error-In async modes, a
one in this bit indicates a receive fram-

9-67

End of Frame-this bit is valid only in
SOLC mode. A one indicates that a valid
ending flag has been received. This bit is
reset either by an Error Reset command
or upon reception of the first character
of the next frame.

170102·001

inter

8274

Read Register 2 (RR2):
MSB

LSB

DMA operation is accomplished via an external DMA
controller. When the MPSC needs a data transfer, it
request a DMA cycle from the DMA controller. The
DMA controller then takes control of the bus and
simultaneously does a read from the MPSC and a'
write to memory or vice-versa.
The following section describes the many configurations of these basic types of system interface
techniques for both serial ch'annels.

RR2
07-00

Channel B
Interrupt vector-containsthe interrupt
vector programmed into WR2. If the status
affects vector mode is selected (WR1;' 02), it
contains the modified vector (See WR2). RR2
contains the modified vector for the highest
priority interrupt pending. If no interrupts are
pending, the variable bits in the vector are set
to one.

SYSTEM INTERFACE
General
The MPSC to Microprocessor System interface can
be configured in many flexible ways. The basic interface types are polled, wait, interrupt driven, or direct
memory access driven.
'
Polled operation is 'accomplished by repetitively
reading the status of the MPSC, and making decisions based onthat status, The MPSC can be polled
at any time.
.
Wait operation allows slightly faster data throughput
forthe MPSC by manipulating fhe Ready inputtothe
microprocessor. Block Read or Write Operations to
the MPSC are started at will by the microprocessor
and the MPSC deactivates its ROY signal if it is not
yet ready to transmit ,the new byte, or if reception of
new byte is not completed,

POLLED OPERATION:
In the polled mode, the CPU must monitor the desired conditions within the MPSC by reading the appropriate bits in the read registers. All data available,
status, and error conditions are represented by the
appropriate bits in read registers 0 and 1 for channels A and B.
There are two ways in which the software task of
monitoring the status of the MPSC has been reduced. One is the "ORing" of all conditions into the
Interrupt Pending bit. (RRO;D1 channel A only). This
bit is set when the MPSC requires service, allowing
the CPU to monitor one bit instead offourstatus registers. The other is available when the "statusaffects-vector" mode is selected. By reading RR2
Channel B, the CPU can read a vector who's value
will indicate that one or more of group of conditions
has occurred, narrowing the field of possible conditions. See WR2 and RR2 in the Detailed Command
Description section.
Software Flow, Polled Operation

Interrupt driven operation is accomplished via an
internal or external interrupt controller. When the
MPSC requires service, it sends an interrupt.request
signal to the microprocessor, which responds with
an interrupt acknowledge signal. When the internal
or external interrupt controlier receives the acknowledge, it vectors the microprocessor to a service routine, in which the transaction occurs.

RECEIVE
RRO; DO is

reset automatically when the data is read.

RRO; D2 i,s reset automatically when the data Is written.

170102-001

9-68

8274

Hardware Configuration, Polled Operation

.,. ...

~ ADDRESS BUS

~

(,

DATA BUS
RD

w-

I

''---

p
8205

L

_

P '-:--

~vcc
DBO·7

iNii

Ao

p'--~

MPSC

CS
RD
WR

WAIT OPERATION:
Wait Operation is intended to facilitate data transmission or reception using block move operations. If
a block of data is to be transmitted, for example, the
CPU can execute a String I/O instruction 'to the
MPSC. After writing the first byte, the CPU will attempt to write a second byte immediately as is the
case of block move. The MPSC forces the RDY
signal low which inserts wait states in the CPU's
write cycle until the transmit buffer is ready to accept a new byte. At that time, the RDY signal is high
allowing the CPU to finish the write cycle. The CPU
then attem pts' the thi rd write and the process is
repeated.

instruction (8085 mode) and interrupt vector (8085
and 8088/86 mode) on the data bus.
The MPSC can be programmed to cause an interrupt
due to up to 14 conditions in each channel. The
status of these interrupt conditions is contained in
Read Registers a and 1. These 14 conditions are all .
directed to cause 3 different types of internal interrupt request for each channel: receive/interrupts,
transmit interrupts and external/status interrupts (if
enabled).
This results in up to 6 internal interrupt request
signals. The priority of those signals can be programmed to one of two fixed modes:

Similar operation can be programmed for the receiver. During initialization, wait on transmit (WR1;
D5 = 0) or wait on receive (WR1; D5 = 1) can be
selected.The wait operation can be enabled/
disabled by setting/resetting the Wait Enable Bit
(WR1; D7).
CAUTION: ANY CONDITION THAT CAN CAUSE THE
TRANSMITTER TO STOP (EG, CTS GOES INACTIVE) OR THE RECEIVER TO STOP (EG, RX DATA
STOPS) WILL CAUSE THE MPSC TO HANG THE
CPU UP IN WAIT STATES UNTIL RESET. EXTREME
CARE SHOULD BE TAKEN WHEN USING THIS FEATURE.
INTERRUPT DRIVEN OPERATION:
The MPSC can be programmed into several interrupt modes: Non-Vectored, 8085 vectored, and
8088/86 vectored. In both vectored modes, multiple
MPSC's can be daisy-chained.
In the vectored mode, the M PSC responds to an
interrupt acknowledge sequence by placing a call

Highest Priority

Lowest Priority

RxA RxB TxA TxB ExTA
RxA TxA RxB TxB ExTA

ExTB
ExTB

The interrupt priority resolution works differently for
vectored and non-vectored modes.

PRIORITY RESOLUTION: VECTORED MODE
Any interrupt condition can be accepted internally
to the MPSC at any time, unless the MPSC's internal
INTA signal is active, unless a higher priority interrupt is currently accepted, or if iPf is inactive (high).
The MPSC's internallNTA is set on the leading (failing) edge of the first External INTA pulse and reset
on the trailing (rising) edge of the second External·
INTA pulse. After an interrupt is accepted internally,
an External INT request is generated and the IPO
goes inactive. IPO and TPi are used for daisychaining MPSC's together.

9-69

170102-001

8274

Interrupt Condition Grouping
INTERNAL INTERRUPT
MOOE

CONDITION

RECEIVE CHARACTER ----------4~1

REQUEST

R~~~~::~~~:C~~~S

::~~~i~~~:R~U~N~E~R~R~O~R~~---f-SPEi~r-1

~~~Mci~~:::~~S::D::-LC=-=O"'NL:-:Y=-)::::::~'_"'....._""'...

CHARACTER&w,~~~~~===~O~~~~~::J

FIRST
CHARACTER ISYNC MODES)
FIRST NON-SYNC
DATA
VALID ADDRESS BYTE (SOLe ONLY)

INTERRUPT ON FIRST
RIt CHARACTER

CDTRANSITION~~:~~~~~~~~~~~~~~~~~~~~~~~~~~

eTS TRANSITION
SYNC TRANSITION
Tx UNDERRUN/EOM
BREAKfABORT DETECT

TRANSMIT BUFFER EMPTY

INTERNAL

INTERRUPT
ACCEPTED

LOWER PRIORITY INTERRUPTS NOT ACCEPTED

iNffiiiWPi'

(EXTERNAL)

INTA
(EXTERNAL)

HIGHER

INTA
(INTERNAL)

...+I-_____ NO~~~~~~~~S------I~-I:r~~~~~~SACCEPTED

The MPSC's internallNTA is set on the leading (failing) edge of the first external INTA pulse, and reset
on the trailing .(rising) edge of the second external
INTA pulse. After an interrupt is accepted internally,

9-70

an external INT request is generated and IPO goes
inactive (high). IPO and .IPI are used for daisychaining MPSC's together.

170102-001

inter

8274

In-Service Timing

INTERNAL INTERRUPT
ACCEPTED

INTERRUPT
(EXTERNAL)

\'--_ _---J/

INTA
(EXTERNAL)

INTA
(INTERNAL)

IN·SERVICE
(INTERNAL)

Each of the six interrupt sources has an associated
In-Service latch. After priority has been resolved, the

highest priority In-Service latch is set. After the InService latch is set, the INT pin goes inactive (high).

~~~~ ExternallNT pin Is active and the IPI signal Is pulled Inactive high, the INT signal will also go Inacllve. iPi qualifies ihe ExternallNT Signal.

170102-001

9-71

8274

EOI Command Timing

SERVICE

INTERNAL INTERRUPT
ACCEPTED

ROUTINE

r--------------------------~~ ~----~

J

/

INTERRUPT \ .
(EXTERNAL) _

-

/

\ ' -_ _ _ _ _ _ _ _ _ _ _..J

JIm[
(EXTERNAL)

INTA
(INTERNAL)

/

----'

IN·SERVICE

(INTERNAL)

/

-------'
EOICOMMAND

(INTERNAL)

Lower priority interrupts are not accepted internally
while the In-Service latch is set. However, higher
priority interrupts are accepted internally and a new
external INT request is generated. If the CPU responds with a new INTA sequence, the MPSC will respond as before, suspending the lower priority
interrupt.

9-72

After the interrupt is serviced, the End-of-Interrupt
(EOI) command should be written to the MPSC. This
command will cause an internal pulse that is used to
reset the In-Service Latch which allows service for
lower priority interrupts in the daisy-chain to resume, provided a new INTA sequence does not start
for a higher priority interrupt (higher than the highest under service). If there is no interrupt pending internally, the IPO follows IPI.

170102-001

8274

Non-Vectored Interrupt Timing

SERVICE

ROUTINE
INTERNAL INTERRUPT

):======~~o.W;'."P;.I;O.;'IT~Y;,m;';'••;U"n."NWO~T'~CC.C'~"~'D,-=-=-=-=-=--~

~========~

ACCEPTED

INTERRUPT
(EXTERNAL)

iiii

(EXTERNAL)

INTERNAL POINTER
SETTOAEQ2

IN·SERVICE
(INTERNAL).

EOICOMMAND
(INTERNAL)

PRIORITY RESOLUTION:
NON-VECTORED MODE

In non-vectored mode, the MPSC does not respond
to interrupt acknowledge sequences. The INTA input
(pin 27) must be pulled high for proper operation.
The MPSC should be programmed to the StatusAffects-Vector mode, and. the CPU should read RR2
(Ch. B) in its service routine to determine which interrupt requires service.
'

9-73

In this case, the internal pointer being set to'RR2
provides the same function as the internal INTA
signal in the vectored mode. It inhibits acceptance
of any additional internal interrupts and its leading
edge starts the interrupt priority resolution circuit.
The interrupt priority resolution isended by the leading edge of the read signal used by the CPU to
retrieve the modified vector. The leading edge of
read sets the In-Service latch and forces the external
INT output inactive (high). The internal pointer is
reset to zero after the trailing edge ofthe read pulse.

170102-001

8274

.:L~:>----cs

OMATlming

DRQ"~

\'------X'-__________>C

,
A,. A • c s - - -....

. . ___________JI

~.WR------------ \~

permutations of interrupt, wait, and DMA modes for
channels A and B. Bits D,. 'D o of WR2 Ch. A determine these permutation~.

OMA OPERATION
Each MPSC can be programmed to utilize up to four
DMA channels: Transmit Channel A. Receive Channel A. Transmit Channel B. Receive Channel B. Each
DMA Channel has an associated DMA Request line.
Acknowledgement of a DMA cycle is done via normal data read or write cycles. This is accomplished
by encoding the DACK signals to generate A o. A,.
and CS signals. and multiplexing them with the
normal A o• A,. and CS signals.

Permutation
WR2 Ch. A

0, Do

Channel A

ChannelB

Wait
Interrupt
Polled

Wait
Interrupt
Polled
Interrupt
Polled

00

o1

DMA
Polled

PERMUTATIONS
Channels A and B can be used with different system
interface modes. In all cases it is impossible to poll
the MPSC. The foHowing table shows the possible

1 0

D1, DO

9-75

= 1,1

DMA

DMA

Polled

Polled

is illegal.

,70102-001

inter

8274

DE

~

8282
A,16-A19

DI

ALE

A11S-A19

00

STB

L......-

rlD~

AI-AU

,L--J
8088
8284A

iiD

READY

ViR

I-I--

~

.48-A15

.~CC

f{ ;,

A'~O,~

H1B:~O'~
:3 :I 0, j)-A!
84

.---

.-~

~ O.~

.--DI

I--

00".00, 1
8282 STa

"

.v

~

0.-0,

~

DE DI1""0I,

DB,
DB,

ADSTS

8237 A,-A.

fffiIWA

0

74l$74

eLK

I--

hi

DO-D,

HLDA

[§9
ClA

,1

II

ADD-AD7
HOLD

8274

.-A,

srB
8282

r

DE

eLK
RESET

II

DO

15Xl:K,

l701i

1iACK,

I--

bOA

DRQ,

DRQ 2

I-

~JlDRQ.

eLK
RESET

m H
IiACK'

-----,
l
1k'-MULTIPLEXER

ORQl

IIOW

READY

.-

RxDA

DRQ o

Jm:K,

HLDA
HAO
AEN

I--Ne

J

.....

I

os

(FROM 8205)

1

"....

v

1

1

Tx DR 0,

-

A,
A,

,,,
I
t--t:'------JI
I"

IV::::

I"
I""

es

I

iiD

~

9-76

170102-001

PROGRAMMING HINTS

Transmit Under-run/EOM latch

This section will describe some useful programming
hints which may be useful in program development.

In SOLC/HOLC, bisync and monosync mode, the
transmit under-run/EOM must be reset to enable the
CRC check bytes to be appended to the transmit frame
or transmit message. The transmit under-run/EOM
latch can be reset only after the first character is loaded
into the transmit buffer. When the transmitter underruns at the end of the frame, CRG check bytes are
appended to the frame/message. The transmit underrun/EOM latch can be reset at any time during the
transmission after the first character. However, it should
be reset before the transmitter under-runs otherwise,
both bytes of the CRC may not be appended to the
frame/message. In the receive mode in bisync operation, the CPU must read the CRC bytes and two more
SYNC characters before checking for valid CRC result
in RR1.

Asynchronous Operation
At the end of transmission, the CPU must issue "Reset
Transmit InterrupVOMA Pending" command in WROto
reset the last transmit empty request which was not
satisfied. Failing to do so will result in the MPSC
locking up in a transmit empty state forever.

Non-Vectored Mode
In non-vectored mode, the Interrupt Acknowledge pin
(INTA) on the MPSC must be tied high through a
pull-up resistor. Failing to do so will result in unpredictabl~ response from the 8274.

Sync Character load Inhibit

When receiving data in SOLC mode, the CRC bytes
must be read by the CPU (or OMA controller) just like
any other data field. Failing to do so will result in
receiver buffer overflow. Also, the End of Frame Interrupt indicates that the entire frame has been received.
At this point, the CRC result (RRt06) and residue code
(RR1;03, 02, 01) may be checked.

In bisync/monosync mode only, it is possible to prevent
loading sync characters into the receive buffers by
setting the sync character load inhibit bit (WR3;01=1).
Caution must be exercised in using this option. It may
be possible to get a CRC character in the received
message which may match the sync character and not
get transferred to the receive buffer. However, sync
character load inhibit should be enabled during all
pre-frame sync characters so the software routine does
not have to read them from the MPSC.

Status Register RR2

In SOLC/HOLC mode, sync character load inhibit bit
must be reset to zero for proper operation.

HOlC/SOlC Mode

RR2 contai ns the vector wh ich gets mod ified to ind icate
the source of interrupt (See the section titled MPSC
Modes of Operation). However, the state of the vector
does not change if no new interrupts are generated.
The contents of RR2 are only changed when a new
interrupt is generated. In order to get the correct
information, RR2 must be read only after an interrupt is
generated, otherwise it will indicate the previous state.

EOI Command
EOI command can only be issued through channel A
irrespective of which channel had generated the
interrupt.

Priority in OMA Mode
Initialization Sequence

There is no priority in OMA mode between the following four signals: TxORQ(CHA), RxORQ(CHA),
TxORQ(CHB), RxORQ(CHB). The priority between
these four signals must be resolved by the OMA
controller. At any given time, all four OMA channels
from the 8274 are capable of going active.

The MPSC initialization routine must issue a channel
Reset Command at the beginning. WR4 should be
defined before other registers. At the end of the
initialization sequence, Reset External/Status and Error
Reset commands should be issued to clear any
spurious interrupts which may have been caused at
power up.

9-77

170102-001

8274

ABSOLUTE MAXIMUM RATINGS·
AmbientTemperature
Under Bias ........................ O°C to + 7QoC
Storage Temperature
(Ceramic Package) ............. -65°C to +150°C
(Plastic Package) .............. - 49°C to + 125°C
Voltage On Any Pin With
Respect to Ground .............. -O:5V to +7.0V

D.C. CHARACTERISTICS (T.
Symbol

'NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

= O°C to 70°C; Vee = +5V ±10%)'

Parameter

Min.

Max.

Units

Test Conditions

V IL

Input Low Voltage

-0.5

+0.8

V IH

Input High Voltage

+2.0

VCC +0.5

V

VOL

Output Low Voltage

+0.45

V

IOL = 2.0mA

VOH

Output High Voltage

V

IOH= - 2OO!LA

IlL

Input Leakage Current

±10

!LA

VIN = Vcc to OV

IOL

Output Leakage Current

±10

!LA

VOUT= VCC toOV

ICC

VCC Supply Current

200

mA
.

CAPACITANCE (T.

+2.4 .

V

= 25°C; Vee = GND = OV)

Test Conditions

Max.

Units

C IN

Input Capacitance

10

pF

Ic = 1 MHz;

COUT

Output Capacitance

15

pF

Unmeasured

CliO

Input/Output Capacitance

20

pF

Symbol

Parameter

Min.

pins returned
to GND

9-78

170102-001

A.C. CHARACTERISTICS

Symbol

(TA =

occ to 70 C; Vee
C

= +5V ±100/o)'

Min.

Max.

Units

tCY

CLK Period

Parameter

250

4000

ns

tCl

CLK Low Time

105

2000

ns

tCH

CLK High Time

105

2000

ns

tr

CLK Rise Time

0

30

ns

tf

CLK Fall Time

0

30

ns

tAR

AO. AI Setup to RDj

0

tAD

AO, AI to Data Output Olay

200

ns

tRA

AO, AI Hold After RD)

tRO

RD) to Data Output Delay

tRR

RD Pulse Width

ns

200
250

ns

120

ns

Output Float Delay
CS. AO. AI Setup to WRj

0

ns

tWA

CS, AO. AI Hold after WR)

0

ns

tww

WR Pulse Width

250

ns

tow

Data Setup to WR)

150

ns

two

Data Hold After WR)

0

ns

tpi

ipi Setup to INTA)

0

ns

tiP

IPI Hold after INTA)

10

ns
ns

250

tplPO

I PI j to IPO Delay

100

ns

tiD

INTAj to Data Output Deay

200

ns

tca

Ri5 or WR to ORO)

150

ns

tRV

Recovery Time Between Controls

tcw

CS, AO. Alto ROYA or ROY B Delay

C L=150 pf

ns

tOF

.INTA Pulse Width

C L=150pf

ns

0

tAW

til

Test Conditions

ns

300
140

ns

toCY

Data Clock Cycle

4.5

tcy

tOCl

Data Clock Low Time

180

ns

tOCH

Data Clock High Time

180

ns

tTD

TxCto TxD Delay (xl Mode)

tos

RxD Setup to RxC)

tOH

RxD Hold alter RxC)

t lTO

TxC to INT Delay

4

6

tey

tiRO

RxC to INT Delay

7

10

tey

tpl

CTS, CD,

SYNDET Low Time

200

ns

tpH

CTS, CD, SYNDET H·igh Time

200

ns

tlPO

ExternallNT from CTS, CD, SYNDET

300

ns
ns

0

ns

140

500

ns

Note:
1. For Extended Temperature EXPRESS, use MIL8274 electrical Parameters

9-79

170102-001

8274
(

/

A.C. TESTING LOAD CIRCUIT

A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUT/OUTPUT

~=x
0.45

2.0

>

0.8

< )C
2.0

TEST POINTS

DEVICE
UNDER

lC'~15OPF

TEST

0.8

A.C. TESTING: INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC .. , .. AND O.45V FOR
A LOGIC "0." TIMING MEASUREMENTS ARE MADE AT 2:0V FOR A LOGIC ..,..
AND
FOR A LOGIC "0."

CL;o 150pF·

a.sv

C, INCWDES JIG CAPACITANCE

WAVEFORMS
CLOCK CYCLE

READ CYCLE

Cs'. AO. A1

1+---.••• ----+\

HIGH IMPEDANCE

I+-----IAD------<~I

170102-001

9-80

8274

WAVEFORMS (Continued)
WRITE CYCLE

~>{"'~______
'" ~ ,. :i<

CBo-DBr

INTA CYCLE

IMPEDANCE

IMPEDANCE

DMA CYCLE
ORa

/

~

CB,AO,A1

ADORWA

NOTES:
1. INTA signal acts as RD signal.
2."jj5j signal acts as CS signal.

9-81
170102·001

8274

WAVEFORMS (Continued)
READ/WRITE CYCLE (SOFTWARE POLLED MODE)
Ci,AD,A'

1--------.,,-------1

"------TRANSMIT DATA CYCLE
_ - - -. . . . . . 1

\ o t - - - - - .• "----~'""

L
OTHER

T:'~~;NDET ~.,-------'.,"-'----0-~--.'"----~"".----

l

·"O--Q-I'' ' '-___
9-82

170102-001

82530/82530-6
SERIAL COMMUNICATIONS CONTROLLER (SCC)
•

Two independent full duplex serial
channels

•

On chip crystal oscillator, Baud-Rate
Generator and Digital Phase Locked Loop
for each channel

•

Programmable for NRZ, NRZI or FM data
encoding/decoding

•

Diagnostic localloopback and automatic
echo for fault detection and isolation

•

•

•

Asynchronous Modes
- 5-8 bit character; odd, even or no
parity; 1, 1.5 or 2 stop bits
- Independent transmit and receive
clocks. 1X, 16X, 32X or 64X
programmable sampling rate
- Error Detection: Framing, Overrun and
Parity
- Break detection and generation

•

Bit synchronous Modes
- SDLC Loop/Non-Loop Operation
- CRC-16 or CCITT Generation Detection
- Abort generation and detection
- I-field residue handling
- CCITT X;25 compatible

•

Byte synchronous Modes
...,... Internal or external character
synchronization (1 or 2 characters)
- Automatic CRC generation and
. checking (CRC 16 or CCITT)
- IBM Bisync compatible

System Clock Rates:
-4 Mhz for 82530
-6 Mhz for 82530-6
Max Bit Rate (6MHz)
-' Externally clocked: 1.5 Mbps
Self clocked:
375 Kbps FM CODING
187 Kbps NRZI CODING

•

Interfaces easily with any INTEL CPU,
DMA or I/O processor

The INTEL 82530 Serial Communications Controller (SCC) is a dual-channel, multi-protocol
data communications peripheral. It is designed to interface high speed communications lines
using Asynchronous. Byte synchronous and Bit synchronous protocols to INTEL's microprocessors'based systems, It can be interfaced with Intel's MCS51, iAPX86/88/186 and 188 in
polled, interrupt driven or DMA driven modes of operation,
The SCC is a 40 pin device manufactured using INTEL's high-performance HMOS II technology.

Intel Corporation Assumes No Responsibility forthe Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses
are implied.

@INTEL CORPORATION, 1984

9-83

January 1985
Order Number 230834-002

inter

82530/82530-6

DA'A

DBO-7

BUS

IUFFERS
CHANNEL A

TXD,

BAUD

RATE
GENERATOR

AltO"
TRANSMITTERI

RECEIVER

1IIIil:,

TAil:,

.EAD

FlEGlSTtA&

~...

CONTROL

-

LOGIC

1iTi,
Oft,

WAITE

REGISTERS

IIiT

as,

-.

..0

...

A.D.

1IIIil:.
iiiiC.

1IIii",IIIa,

l!IIYoiIiilI.

CHANNELB

m",tilCI,

lIl'IIoJRmo

~.

All DIIr flV/li1iD

IiTio

SYSTEM INTERFACE

ea.

CT"..

SERIAL COMMUNICAnON
INTERFACE

Figure 1. 82530 Internal Block Diagram

DB1

DB.

DB.

DB'

DB7

DB.

lIlT

RJ)

.EO

I'/ft

.E.

Alii

iIiTA

eli

vee

DIe

Fi15V"rlm:iA
!Wl'Il:.

GND
RDYBtREOa

1IIIil:.

mre.

RItD"

1lTiC.

'Il!ie,

RaDe

mAlMO"

,.,0.

,.,0.
I!B,

TRiC!:e

Dff:I:afREQa

Cfi.

m.

as.

CB.

elK

COB

Figure 2.
9-84

DB.

DB3

Pin configuration
230834-002

82530/82530-6

The following section describes the pin functions
of the
Figure 2 details the pin assignments

sec.

Table 1. Pin Description
Symbol

Pin No. 'TYpe

Name and Function

DBo
DB1
DB2
DB3
DB4
DBs
DB6
DB7
INT

4Q
1
39
2
38
3
37
4

I/O
I/O
I/O
1/0
1/0
I/O
I/O
I/O

Data Bus: The Data Bus lines are bi-directional three-state lines which
interface with the system's Data Bus. These lines carry data and
commands to and from the SCC.

,5

0

lEO

6

C

lEI

7

I

Interrupt Request: The interrupt signal is activated when the SCC
requests an interrupt. It is an open drain output.
Interrupt Enable Out: lEO is High only if lEI is High and the CPU is not
servicing an SCC interrupt or the SCC is not requesting an interrupt
(Interrupt Acknowledge cycle only). lEO is connected to the next lower
priority device's lEI input and thus inhibits interrupts from lower priority
devices.
Interrupt Enable In: lEI is used with lEO to form an interruptdaisyctlEiin
when there is more than one interrupt-driven device. A High lEI indicates that no other higher priority device has an interrupt under service
or is requesting an interrupt.

INTA

8

I

9
10
30

0
0

11
29

110

Vee
.RDYA/REQA
RDYs/Rro s

SYNC A
SYNCs

I/O

Interrupt Acknowledge: This signal indicates an active Interrupt Acknowledge c1£le. During this cycle, the SCC interrupt daisy chain settles.
When RD becomes active, the SCC places an interrupt vector on the
data bus (if lEI is High). INTA is latched by the rising edge of CLK.
Power: +5V Power supply
Ready/Request (output, open-drain when programmed for a Ready
function, driven High or Low when programmed fora Requestfunction).
These dual-purpose outputs may be programmed as Request lines for a
DMA controller or as Ready lines to synchronize the CPU to the SCC
aata rate. The reset state is Ready.
Synchronization: These pins can act either as inputs, outputs or part of
the crystal oscillator circuit. In the Asynchronous Receive modeJ£!ystal
oscillator option not selected), these pins are inputs similar to CTS and
CD. In this mode, transitions on these lines affect the state of the
Synchronous/Hunt status bits in Read Register 0 (Figure 9) but have no
other function.
In External Synchronization mode with the crystal~lator not
selected, these lines also act as inputs. In this mode, SYNC must be
driven LOW two receive clock cycles after the last bit in the synchronous
character is received; Character assembly begins on the rising edge of
the receive clock immediately preceding the activation of SYNC.
In the Internal Synchronization mode (Monosy'nc and Bisync) with the
crystal oscillator not selected, these pins act as outputs and are active
only during the part of the receive clock cycle in which synchronous
characters are recognized. The synchronous condition is not latched, so
these outputs are active each time a synchronization pattern is
recognized (regardless of characters boundaries). In SDLC mode, these
pins act as outputs and are valid on receipt of a flag.
9-85

230834-002

82530/82530-6
Table 1. Pin Description (Cont.)
Pin No.

.'TYpe

RTxC A
RTxC s

12
28

I
I

Recelve/'n'ansmlt clocks: These pins can be prR~rCmmed in several
different modes of operation. In each channel,
x may supply the
receive clock, the transmit clock, the clock for the baud rate generator,
or the clock for the Digital Phase Locked LOop. These pins can be
programmed for use with the respective SYNC pins as a crystal
oscillator. The receive clock may be 1, 16,32, or 64 times the data rate in
Asynchronous modes.

RxDA
RxDs

13
27
14
26

I
I

Receive Data: These lines receive serial data at standard TTL levels.

I/O
I/O

Transmit/Receive clocks: These pins can be programmed in several
different modes of operation. T'RXC may supply the receive clock or the
transmit clock in the input mode or supply the output of the Digital
Phase Locked Loop, the crysta) oscillator, the baud rate generator, orthe
transmit clock in -the output mode.

b

'n'ansmlt Dala: These ouiput signals transmit serial data at standard TTL
levels

Symbol

TRxC A
TRxC s

DTRAREQ A
DTRsREQ s

15
25
16
24

RTSA .
RTS e

17
23

TxDA
TxDA

..

0

Name and Function

0
0

Dala Terminal Ready/Request:. These outputs follow the state programmed into the DTR bit. They can also be used as general purpose
outputs or as Request lines for a DMA controller.

b

Request To Send: When the Request to Send (RTS) bit in Write Register 5
is set (figure 10), the RTS signal goes Low. When the RTS bit is reset in
the Asynchronous mode and Auto Enable is on, the signal goes High

0

afterthetransmitterisempty.ln~hronousmodeorinAsynchronous

mode with Auto Enable off, the RTS pin strictly follows the state of the
RTS bit. Both pins can be used as general-purpose outputs.
CTSA
CTS s

18
22

I
I

Clear To Send: If these pinsare programmed as Auto Enables, a Low on
the inputs enables the. respective transmitters. If not programmed as
Auto Enables, they may be used as general-purpose inputs. Both inputs
are Schmitt-trigger 'bu'ffered to accommodate slow rise-time inputs.
The SCC detects pulses on these inputs and can interrupt the CPU on
both logic level transitions.

CD A
CDs

19
: 21

I
I

Carrier Detect: These pins function as receiver enables if they' are
programmed for Auto Enables: otherwise they may be used as·generalpurpose input pins. Both pins are Schmitt-trigger buffered to accome
modate slow rise time signals. The SCC detects pulses on these pins and
can interrupt the CPU on both logic level transitions.

CLK

20

I

Clock: This is the system SCC clock used to synchronize internal
sighals. eLK is a TTL level signal.

GND

31

D/C

32

I

Data/Command Select: This signal defines the type of information
transferred to or from the see. A High means data is transferred: a Low
indicates a command.

es

33·

1

Chip Select:This signal selects the see for a.read or write operation.

AlB

34

I

Channel A/Channel B Select: This signal selects the channel in which
the read or write operation occurs.

WR

35

I

Write: When the SeCis selected this signal il)dicates a write operation.
The coincidence ofRD and WRis interpreted as a reset.

RD

36

I

Read: This signal indicates a read operation and when the see is
selected, enables the.See's bus driilers. During the Interrupt Acknowledge cycle, this signal gates the interrupt vector.onto the bus if the see
is the highe~t priority device requesting an interrupt.

Ground

230834-002

82530/82530-6

GENERAL DESCRIPTION
The INTEL 82530 Serial Communications Controller (SCC) is a dual-channel, multi-protocol data
communications peripheral. The SCC functions as
a serial-to-parallel, parallel-to-serial converter/controller. The SCC can be software-configured to
satisfy a wide range of serial communications applications. The device contains new, sophisticated
internal functions including on-chip baud rate generators, digital phase locked loops; various data
encoding and decoding schemes, and crystal oscillators that dramatically reduce the need for external
logic.
In addition, diagnostic capabilities.- automatic echo
and local loopback - allow the user to detect and
isolate a failure in the networK. Theygreatly improve
the reliability and maintainability of the system.

The register set for each channel includes ten control (write) registers, two synchronous character
(write) registers, and four status (read) registers. In
addition, each baud rate generator has two (read/write) registers for holding the time constant that
determines the baud rate. Finally, associated with
the interrupt logic isa write register for the interrupt
vector accessible through either channel, a writeonly Master Interrupt Control register and three
read registers: one containing the vector with status
information (Channel B only), one containing the
vector without status (A only), and one containing
the Interrupt Pending bit~(A only).
The registers for each channel are designated as
follows:
WRO-WR15 - Write Registers 0 through 15.
RRO-RR3, RR10, RR12, RR13, RR15 - Read Registers
o through 3, 10, 12, 13, 15

The SCC handles Asynchronous formats, Synchronous byte-oriented protocols such as IBM Bisync,
and Synchronous bit-oriented protocols such as
HDLC and IBM SDLC. This versatile device supports virtually any serial data transfer application
(Terminal, Personal Computer, Peripherals, Industrial Controller, Telecommunication system, etc.).

Table 2 lists the functions assigned to each read or
write register. The SCC contains only one WR2
and WR9, but they can be accessed by either
channel. All other registers are paired (one for
each channel).

The 82530 can generate and check CRC codes in
any Synchronous mode and can be programmed to
check data integrity in various modes. The SCC also
has facilities for modem controls in both channels.
In applications where these controls are not needed,
the modem controls can be used for generalpurpose I/O.

DATA PATH
The transmit and receive data path illustrated in
Figure 3 is identical for both channels. The receiver
has three 8-bit buffer registers in a FIFO arrangement, in addition to the 8-bit receive shift register.
This scheme creates additional time for the CPU to
service an interrupt at the beginning of a block of
high-speed data. Incoming data is routed through
one of several paths (data or CRG) depending on
the selected mode (the character length in asynchronous modes also determines the data path).

The INTEL 82530 is designed to support INTEL's
MCS51, iAPX86/88 and iAPX186/188 families.

ARCHITECTURE
The 82530 internal structure includes two fullduplex channels, two baud rate generators, internal
control and interrupt logic, and a bus interface to a
non-multiplexed CPU bus. Associated with each
channel are a number of read and write registers for
mode control and status information, as well as
logic necessary to interface to modems or other
external devices.

The transmitter has an 8-bit transmit data buffer
register loaded from the internal data bus and a
20"bit transmit shift register that can be loaded
either from the sync-character registers or from the
transmit data register. Depending on the operational mode, outgoing data is routed through one of
four main paths before it is transmitted from the
Transmit Data output (TxD).

The logic for both channels provides formats, synchronization, and validation for data transferred to
and from the channel interface. The modem control
inputs are monitored by the control logic under
program control. All of the modem control signals
are general-purpose in nature and can optionally be
used for functions other than modem control.
9-87

230834-002

82530/82530·6

Table 2. Read and Write Register Functions
READ REGISTER FUNCTIONS
RRO

Transmit/Receive buffer status and
External status

RR1

Special Receive Condition status

RR2

RR3

WRITE REGISTER FUNCTIONS
WRO

CRC initialize, initialization commands for
the various modes, shift right/shift left
command

Modified interrupt vector
(Channel B only)
Unmodified interrupt
(Channel A orily)

WR1

Transmit/Receive interrupt and data
transfer mode definition

WR2

Interrupt vector (accessed through either
channel)

Interrupt Pending bits
(Channel A only)

WR3

Receive parameters and control

WR4

Transmit/Receive miscellaneous parameters and modes

RRB

Receive buffer

RR10

Miscellaneous status

WR5,

Transmit parameters and controls

RR12

Lower byte of baud rate generator time
constant

WR6

Sync characters or SOLC address field

RR13

Upper byte of baud rate generator time
constant

RR15

External/Status interrupt information

WR7

Sync character or SOLC flag

WR8

Transmit buffer

WR9

Master interrupt control and reset
(accessed through either channel)

WR10

Miscellaneous transmitter/receiver control
bits

WR11

Clock mode control

WR12

Lower Byte of baud rate generator time
constant

WR13

Upper byte of baud rate generator time
constant

WR14

Miscellaneous control bits

WR15

External/Status interrupt control

9-88

230834-002

l

CPU 1/0

BR GENERATOR

INPUT

CD

!'!

I\)

U1

IQ

W

C

'P

~

~
Co)

I\)

Q)

CD

U1

C

W

II>

oI
en

iii

'l/

:T

OPlL ----.L_ _ _ _..1
SR GENERATOR OUTPUT

~

RECEIVE CLOCK

DPlL OUTPUT

fiiic-

RTiC

CLOCK
MUX

TRANSMIT CLOCK

. DPlL CLOCK
SR GENERATOR CLOCK

SYNC

(OSCILLATOR)

'"
Co>

o

'"~
b
o

'"

@

inter

82"530/82530-6

FUNCTIONAL DESCRIPTION
The functional capabilities of the SCC can be described from two different points of view: as a data
communications device. it transmits and receives
data in a wide variety of data communications protocols; as a microproceSsor peripheral. it interacts
with the CPU and provides vectored interrupts and
handshaking signals.

end of a received break. Reception is protected from
spikes by a transient spike-rejection mechanism
that checks the signal one-half a bit time after a Low
level is detected on the receive data input (RxD A or
RxD e). If the Low does not persist (as in the case of a
·transient). the character assembly process does not
start.

DATA COMMUNICATIONS
CAPABILITIES

Framing errors and overrun errors are detected and
buffered together with the partial character on
which they occur. Vectored interrupts allow fast servicing of error conditions using dedicated routines.
Furthermore. abulit-in checking process avoids the
interpretation of a framing error as a new start bit: a
framing error results in the addition of one-half a bit
time to the point at which the search for the next
start bit begins.

The SCC provides two independent full-duplex
channels programmable for use in any common
asynchronous or synchronous data-comm unications
protocol. Figure 4 and the following description
briefly detail these protocols.

Asynchronous Modes
Transmission and reception can be accomplished
independently on each channel with five to eight
bits per character. plus optional even or odd parity.
The transmitter can supply on,e. one-and-a-half or
two stop bits per character and can provide a break
output at any time. The receiver break-detection
logic interrupts the CPU both at the start and at the

The SCC does not require symmetric transmit and'
receive clock signals - a feature allowing use of the
wide variety of clock sources. The transmitter and
re.ceiver can handle.data at a rate of 1. 1/16. 1/32. or
1/64 of the clock rate supplied to the receive and
transmit clock inputs. In asynchronous modes. the
SYNC pin may be programmed as an input used for
functions such as monitoring a ring indicator.

MARKING LINE

I

MARKING LINE

. DATA

SYNC

:;
::

I

DATA

CRC,

DATA

CRC,

CRC2

DATA

CRC,

CRC2

CRC,

CRC2

CRC2

I'

MONOSYNC

,

DATA

SYNC

SIGNAL

FLAG

I

ADDRESS

I
I

DATA

BISYNC

;;

EXTERNAL SYNC

INFO:~ATION

FLAG

SDLC/HDLC/X.25

Figure 4•.

see Protocols
9-90

230834-002

inter

82530/82530-6

Synchronous Modes

If a transmit underrun occurs in the middle of a
message, an external status interrupt warns the
CPU of this status change so that an abort may bA
issued. The SCC may also be programmed to send
an abort itself in case of an underrun, relieving the
CPU of this task. One to eight bits per character can
be sent allowing reception of a message with no
prior information about the character structure in
the information field of a frame.

The SCC supports both byte-oriented and bitoriented synchronous communication. Synchronousbyte-oriented protocols can be handled in several
modes allowing character synchronization with a
6-bit or 8-bit synchronous character (Monosync),
any 12-bit synchronous pattern (Bisync), or with an
external synchronous signal. Leading synchronous
characters can be removed without interrupting the
CPU.

The receiver automatically acquires synchronization on the leading flag of a frame in SOLC or tiQ..bQ
and provides a synchronization Signal on the SYNC
pin (an interrupt can also be programmed). The
receiver can be programmed to search for frames
addressed by a single byte (or four bits within a
byte) of a user-selected address or to a global
broadcast address. In this mode, frames not matching either the user-selected or broadcast address
are ignored. The number of address bytes can be
extended under software control. For receiving
data, an interrupt on the first received, character, or
an interrupt on every character, or on special condition only (end-of-frame) can be selected. The
receiver automatically deletes all Os inserted by the
transmitter during character assembly. CRC is also
calculated and is automatically checked to validate
frame transmission. At the end of transmission, the
status of a received frame is available in the status
registers. In SOLC mode, the SCC must be programmed to use the SOLC CRC polynomial, but the
generator and checker may be be preset to all 1s or
all Os. The CRC is inverted before transmission and
the receiver checks against the bit pattern
0001110100001111.

Five- or 7-bit synchronous characters are detected
with 8- or 16-bit patterns in the SCC by overlapping
the larger pattern across multiple incoming syn'
chronous characters as shown in Figure 5.
CRC checking for Synchronous byte-oriented
mode is delayed by one character time so that the
CPU may disable CRC checking on specific characters. This permits the implementation of protocols
such as IBM Bisync.
Both CRC-16 (X'6 + X'5 + X2 + 1) and CCITT (X'S + X '2
+ X5 + 1) error checking polynomials are supported.
Either polynomial may' be selected in all synchronous modes. Users may preset the CRC generator
and checker to all 1s or all Os. The SCC also provi des a feature that automatically transmits CRC
data when no other data is available for transmission.
This allows for high-speed transmissions under
OMA control, with no need for CPU intervention at
the end of a message. When there is no data or CRC
to send in synchronous modes, the transmitter
inserts 6-, 8-, or 16-bit synchronous characters,
regardless of the programmed character length.

NRZ, NRZ I or FM coding may be used in any 1X
mode. The parity options available in asynchronous
modes are available in synchronous modes.

The SCC supports synchronous bit-oriented protocols, such as SOLC and HOLC, by performing
automatic flag sending, zero insertion, and CRC
generation. A special command can be used to
abort a frame in transmission. At the end of a message, the SCC automatically transmits the CRC
and trailing flag when the transmitter underruns.
The transmitter may also be programmed to send an
idle line consisting of continuous flag characters or
a steady marking condition.

The SCC can be conveniently used under OMA
control to provide high-speed reception or transmission. In reception, for example, the SCC can
interruptthe CPU when the first character of a message is received. The CPU then enables the OMA to
transfer the message to memory. The SCC the,n
issues an end-of-frame interrupt and the CPU can

SBITS

SYN~

SYNC

DATA

DATA

DATA

DATA

16
-----------~---------

Figure 5. Detecting 5- or 7- Bit Synchronous Characters
9-91

230834-002

inter

82530/82530-6

check the status of the received message. Thus, the
CPU is freed for other service while the message is
being received. The CPU may also enable the OMA
first and have the SCC interrupt only on end-offrame. This procedure allows all data to be transferred via OMA.

further down the loop with messages to transmit
can then append their messages to the message of
the first secondary station by the same process. Any
secondary stations without messages to send merely
echo the incoming messages and are prohibited
from placing messages on the loop (except upon
recognizing an EOP).

SOLe LOOP MODE

SOLC Loop mode is a programmable option in'the
SCC. NRZ, NRZI, and FM coding may all be used in
SOLC Loop mode.

The SCC supports SOLC Loop mode in addition to
normal SOLC. In an SOLC Loop, there is a primary
controller station thatmanages the message traffic
flow and any number of secondary stations. In
SOLC Loop mode, the SCC performs the functions
of a secondary station while an SCC operating in
regular SOLC mode can act as a controller (Figure 6).

BAUD RATE GENERATOR
Each channel in the SCC contains a programmable
Baud rate generator. Each generator consists of two
8~bit time constant registers that form a ~6-bit time
constant, a 16-bit down counter, and a flip-flop on
the outputproducing a square wave. On startup, the
flip-flop on the output is set in a High state, the value
in the time constant register is loaded into the counter, and the counter starts counting down. The output of the baud rate generator toggles upon reachingzero, the value in the time constant register is
loaded into the counter, and the process is repeated.
The time constant may be changed at any time, but
the new value does not take effect until the next load
of the counter.
The output of the baud rate generator may be used
as either the, transmit clock, the receive clock, or
both. It can also drive the digital phase-locked loop
(see next section).
If the receive' clock or transmit clock is not programmed to come from the'fRX'C pin, the output of
the baud rate generator may be echoed out via the
TRxC pin,

, Figure 6. An SDLe Loop

The following formula relates the time constant to
the baud rate. (The baud rate is in bits/second and
the BR clock period is in seconds.)

A secondary station in an SOLC Loop is always
listening to the messages being sent around the
loop, and in fact must pass these messages to the
rest.of the loop by retransmitting them with a onebit-time delay. The secondary station can place its
own message on-the loop only at specific times. The
controller signals that secondary stations may
transmit messages by sending a special character,
c,alled an EOP (End of Poll), around the loop. The
EOP character is the bit pattern 11111110. Because
of zero insertion during messages, this bit pattern is
unique and easily recognized.

1
baud rate
'
,
,
2 (time constant + 2) x (BR clock period)

When a secondary station has a message to transmit and recognizes an EOP on the line, it changes
the last binary one of the EOP to a zero before
transmission. This has the effect of turning the EOP
into a flag sequence. The secondary station now
places its message on the loop and terminates the
message with an EOP.Any secondary stations

9-92

230834-002

82530/82530-6

encoding, as 1 is represented by no change in level
and a 0 is represented by a change in level. In FM1
(more properly, bi-phase mark) a transition occurs
at the beginning of every bit cell. A 1 is represented
by an additional transition at the center of the bit cell
and a 0 is represented by no additional transition at
the center of the bit cell. In FMo (bi-phase space), a
transition occurs at the beginning of every bit cell. A
o is represented by an additional transition at the
center of the bit cell, and a 1 is represented by no
additional transition at the center of the bit cell. In
addition to these four methods, the sec can be
used to decode Manchester (bi-phase level) data by
using the DPLL in the FM mode and programming
the receiver for NRZ data. Manchester encoding
always produces a transition at the center of the bit
cell. If the transition is 0/1 the bit is a O. If the transition is 1/0 the bit is a 1.

Time Constant Values
for Standard Baud Rates at BR Clock = 3.9936MHz
Rate
Time Constant
(Baud)
(decimal notation)
Error

19200
9600
7200
4800
3600
2400
2000
1800
1200
600
300
150
134.5
110
75
50

102
206
275
414
553
830
996
1107
1662
3326
6654
13310
14844
18151
26622
39934

-

0.12%

0.06%

-

0.04%
0.03%

-

-

-

0.0007%
0.0015%

-

AUTO ECHO AND LOCAL LOOPBACK
The see is capable of automatically echoing everything it receives. This feature is useful mainly in
asynchronous modes, but works in synchronous
and SDLC modes as well. In Auto Echo mode TxD
is RxD. Auto Echo mode can be used with NRZI or
FM encoding with no additional delay, because the
datastream is not decoded before retransmission. In
Auto Echo mode, the eTS input is ignored as a
transmitter enable (although transitions on this
input can still cause interrupts if programmed to do
so). In this mode, the transmitter is actually bypassed
and the programmer is responsibc!{ for disabling
transmitter interrupts and READ 7REQUEST on
transmit.

DIGITAL PHASE LOCKED LOOP
The see contains a digital phase locked-loop
(DPLL) to recover clock information from a datastream with NRZI or FM encoding. The DPLL is
driven by a clock that is nominally 32 (NRZI) or 16
(FM) times the data rate. The DPLL uses this clock,
along with the datastream, to construct a clock for
the data. This clock may then be used as the see
receive clock, the transmit clock, or both.
For NRZI coding, the DPLL counts the 32X clock to
create nominal bit times. As the 32X clock is
counted, the DPLL is searching the in~oming datastream for edges (either 1/0 or 0/1). Whenever an
edge is detected, the DPLL makes a count adjustment (during the next counting cycle), producing a
terminal count closer to the center of the bit cell.

The SCC is also capable of locar loopback. In this
mode, TxD is RxD just as in Auto Echo mode. However, in Local Loopback mode, the internal transmit
data is tied to the internal receive data and RxD is
ignored (except to be echoed out via TxD).' eTS
and eD inputs are also ignored as transmit and
receive enables. However, tr,ansitionson these inputs
can still cause interrupts. Local Loopback works in
asynchronous, synchronous and SDLC modes with
NRZ, NRZI or FM coding of the data stream.

For FM encoding, the DPLLstili counts from 1 to 31,
but with a cycle corresponding to two bit times.
When the DPLL is locked, the clock edges in the
datastream should occur between counts 15 and 16
and between counts 31 and O. The DPLL looks for
edges only during a time centered on the 15/16
counting transition.

SERIAL BIT RATE
To run the 82530 (4Mhz) at 1Mbps the receive and
transmit cl.ocks must be externally generated and
synchronized to the system clock. If the serial
clocks (RTxC and TRxC) and the system clock
(CLK) are asynchronous, the maximum bit rate is
880 Kbps. For self-clocked operation, i.e using the
on chip DPLL, the maximum bit rate is 125 Kbps if
NRZI coding is used,and 250 Kbps if FM coding is
used.

The 32X clock for the DPLL can be programmed to
come from either the Ri'XC input oi'the output of the
baud rate generator. The' DPLL output may be
grammed to be echoed out of the SCC via the TRx
pin (if this pin is not being used as an input).

pre

DATA ENCODING
The see may be programmed to encode and
decode the serial data in four different ways (Figure
7). In NRZ encoding, a 1 is represented by a High
level and a 0 is represented by a Low level. In NRZI

9-93

230834-002

inter

82530/82530-6

o

I

BIT CELL LEVEL:

t--...:......;

I

.-

I

i..----i

NO CHANGE" = 1
CHANGE = 0

BIT CENTER TRANSITION:
TRANSITION = 1
!---~I NO TRANSITION = 0

FMl
(BIPHASE MARK)

FMD
(BIPHASE SPACE)

HIGH = 1
LOW=O

NO TRANSITION = 1
TRANSITION = 0

!-_...;...--!

II

HIGH _LOW = 1
LOW _HIGH = 0

Figure I Data Encoding Methods
Mode
Serial clocks
generated
externally

System
clock

System clock!
Serial clock

Serial bit rate

Conditions

4Mhz

4

1 Mbps

Serial clocks synchronized with
system clock. Refer to parameter #3
and #10 in general timings.

6 Mhz

4

1.5 Mbps

4 Mhz

4.5

880 Kbps

6 Mhz

4.5

1.3 Mbps

Serial clocks synchronized with
system clock. Refer to parameter #3 and:
#10 in general timings.
Serial cloCks and system
clock asynchronous.
Serial clocks and system
cloCk asynchronous

NRZI

4 Mhz
6 Mhz

32
32

125 Kbps
187 Kbps

FM

4Mhz
6Mhz

16
16

250 Kbps
375 kbps

Self-clocked
operation

9-94

230834-002

82530/82530·6

1/0 INTERFACE CAPABILITIES
The sec offers the choice of Polling, Interrupt (vectored or non vectored) and Block Transfer modes to
transfer data, status, and control information to and
from the CPU. The Block Transfer mode can be
implemented under CPU or DMA control.

POLLING
All interrupts are disabled. Three status registers in
the sec are automatically updated whenever any
function is performed. Forexample, end-of-frame in
SDLe mode sets a bit in onecf these status registers.
The idea behind polling is for the CPU to periodically read a status register until the register contents
indicate the need for data to be transferred. Only
one register needs to be read; depending on its
contents, the CPU either writes data, reads data, or
continues. Two bits in the register indicate the need
for data transfer. An alternative is a poll of the Interrupt Pending register to determine the source of an
interrupt. The status for both channels resides in
one register.

INTERRUPTS
VYhen a sec responds to an Interrupt Acknowledge
signal (INTA) from the CPU, an interrupt vector may
be placed on the data bus. This vector is written in
WR2 and may be read in RR2A or RR2B (Figures 9
and 10).

Each of the six sources of interrupts in the sec
(Transmit, Receive and External/Status Interrupts in
both channels) has three bits associated with the
interrupt source: Interrupt Pending (IP), Interrupt
Under Service (IUS), and Interrupt Enable (IE).
Operation of the IE bit is straightforward. If the IE bit
is set for a given interrupt source, then that source
can request interrupts. The exception is when the
MIE (Master Interrupt Enable) bit in WR9 is reset
and no interrupts may be requested. The IE bits are
write-only.
The other two bits are related to the interrupt priority chain (Figure 8). As a peripheral, the sec may
request an interrupt only when no higher-priority
device is requesting one, e.g., when lEI is High. If the
deviceJ!:!. question requests an interruP.h..!!. pulls
down INT. The CPU then responds with INTA, and
the interrupting device places the vector on the data
bus.
In the sec, the IP bit signals a need for interrupt
servicing. When an IP bit is 1 and the lEI input is
High, the INT output is pulled Low, requesting an
interrupt. In the sec, if the IE bit is not set by
enabling interrupts, then the IP for that source can
never be set. The IP bits are readable in RR3A.
The I US bits signal that an interrupt request is being
serviced. If an IUS is set, all interrupt sources of
lower priority in the sec and external to the sec
are prevented from requesting interrupts. The internal interrupt sources are inhibited by the state of the
internal daisy chain, while lower priority devices are
inhibited by the lEO output of the sec being pulled

To speed interrupt response time, the sec can modify three bits in this vector to indicate status. If the
vector is read in Channel A, status is never included'
if it is read in Channel B, status is always included:

scc

scc
HIGHEST PRIORITY

scc

LOWEST PRIORITY

+5V

DBO-DB7
INT
INTA

----~~----------~--------------~--~~------------------~
+5V

Figure 8. Daisy Chaining SCC's
9-95

230834-002

82530/82530-6

Low and propagated to subsequent peripherals. An
~US bit is set during an Interrupt Acknowledge cycle
If there are no higher priority devices requesting
interrupts.

CPUlDMA BLOCK TRANSFER
The SCC provides a Block Transfer 'mOde to accommodate CPU block transfer functions and DMA
controllers. The Block Transfer mode uses the
READY/REQUEST output in conjunction with the
READY/REQUEST bits in WR1.· The READY/REQUEST output can be defined under software con~
trol as a REAm line in the CPU Block Transfer .
mode (WR1; D6=0) orasa request line inthe DMA
Block Transfer mode (WR1; D6=1). To a DMAcontroller, the SCC REQUEST output indicates that
the SCC is ready to transfer . data to or from
memory. To the CPU, the READY line indicates that
the SCC is not ready to transfer data, thereby
reguesting that the CPU extend the ,I/O cycle. The
DTR/REQUEST line allows full-duplex operation
under DMA control.

There are three types of interrupts: Transmit, Receive
~nd External/Status interrupts. Each interrupt type
IS enabled under program control with Channel A
having higher priority than Channel B, and with
Receiver, Transmit and External/Status interrupts
prioritized in that order within each channel. When.
the Transmit interrupt is enabled, the CPU is interrupted when the transmit buffer becomes empty.
(This implies that the transmitter must have had a
data character written into it so that it can become
empty.) When enabled, the receiver can interrupt
.
the CPU in one of three ways:
•

Interrupt on First Receive Character or Special
Receive condition.

•

Interrupt on all Receive Characters or Special
Receive condition.

•

Interrupt on Special Receive condition only.

PROGRAMMING
Each channel has fifteen Write registers that are
individually programmed from the system bus to
configure the functional personality of each channel. Each channel also has eight Read registers from
which ime system can read Status, Baud rate, or
Interrupt information.

Interrupt on .First Character or Special Condition
and Interrupt on Special Condition Only are typically used with the Block Transfer mode. A Special
Receive Condition is one of the following: receiver
overrun, framing error in Asynchronous mode, Endof-Frame in SDLC mode and, optionally, a parity
error. The Special Receive Condition interrupt is
different from an ordinary receive character available interrupt only in the status placed in the vector
during the Interrupt-Acknowledge cycle. In Interrupt on First Receive Character, an interrupt can
occur from Special Receive conditions any time
after the first receive character interrupt.

Only the four data registers (Read, Write forchannels
A and B) are di rectly selected by a High on the D/e
ine!:!t and the appropriate levels on the RD, WR and
AfE3 pins. All other registers are addressed indirectly
by the content of Write Register 0 in conjunction
with a Low ~the D/e inp,!!t and the appropriate
levels on the RD, WR and AlB pins. If bit 4 in WWO is
1 and bits 5 and 6 are 0 then bits 0,1,2 address the
higher registers 8 through 15. If bits 4, 5, 6 contain a
different code, bits 0, 1, 2 address the lower regfsters
o through 7 as shown on Table 3.

The main function of the External/Status interrupt is
to monitor the siglllil tra-nsitions of the CTS, Co, and
SYNC pins; however; an External/Status interrupt is
also caused by a Transmit Underrun condition, or a
zero count in the baud rate generator, or by the
detection of a Break (asynchronous mode), Abort
(SDLC mode) or EOP (SDLC Loop mode) sequence
in the data stream. The interrupt caused by the Abort
or EOP has a special feature allowing the SCC to
interrupt when the Abort or EOP sequence is
detected or terminated. This feature facilitates the
proper termination of the current message, correct
initialization of the next message, and the accurate
timing of the Abort condition in external logic in
SDLC mode. In SDLC Loop mode this feature
allows 'secondary stations to recognize the wishes
of the primary station to regain control of the loop
during a poll sequence.

Writing to or reading from any register except RRO,
WRO and the Data Registers thus involves two·
operations:
First write the appropriate code into WRO,then follow this by a write or read operation on the register'
th us specified. Bits 0 th rough 4 in WWO are automatically cleared after this operation, so that WWO then
points to WRO or RRO again.
Channel AlChannel B selection is.made by the AlB
input (High = A, Low = B)
The system program first issues a series of commands to initialize the basic mode of operation. This
is followed by other commands to qualify condi-

9-96

230834-002

inter

82530/82530-6

TABLE 3. REGISTER ADDRESSING
D/C "Point High"
CodeinWRO

High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low

Either Way
Not True
Not True
Not True
Not True
Not True
Not True
Not True
Not True
True
True
True
True
True
True
True
True

02
01
InWRO

Do

Write
Register

Read
Register

X

X

X

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Data
0
1
2
3
4
5
6
7
Data
S
10
11
12
13
14
15

Data
0
1
2

tions within the selected mode. For example, the
asynchronous mode, character length, clock rate,
number of stop bits, even or odd parity might be set
first. Then the interrupt mode would be set, and
finally, receiver or transmitter enable.

~
(0)
(1 )
(2)
(3)
Data·

-

10
(15)
12
13
(10)
15

The status bits of RRO.and RR1 are carefully grouped
to simplify status monitoring: e.g. when the interrupt vector indicates a Special Receive Condition
interrupt, all the appropriate error bits can be read
from a single register (RR1).

READ REGISTERS

WRITE REGISTERS

The SCC contains eight read registers (actually
nine, counting the receive buffer (RRB) in each
channel). Four of these may be read to obtain status
information (RRO, RR1, RR10, and RR15). Two regis.ters (RR12 and RR13) may be read to earn the baud
rate generator time constant. RR2 contains either
the unmodified interrupt vector (Channel A) or the
vector modified by status information (Channel 8).
RR3 contains the Interrupt Pending (IP) bits (Channel A). FigureS shows the formats. for each read
register.

The see contains 15 write registers (16 counting
WRB, the transmit buffer) in each channel. These
write registers are programmed separately to configure the functional "personality" of the channels .
In addition, there are two registers (WR2,and WRS)
shared by the two channels that may be accessed
through either of them. WR2 contains the interrupt
vector for both channels, while WRS contains the
interrupt control bits. Figure 10 shows the format of
each write register.

S-S7

230834-002

inter

92530/82530-6

Rx CHARACTER AVAILABLE

ALL SENT

ZERO COUNT

RESIDUE CODE 2

......_ _ _ _ Tx BUFFER EMPTY
....._ _ _ _ _ _ CD

' - -_ _ _ RESIDUE CODE 1
' - - - - - - - RESIDUE CODE 0

' -_ _ _ _ _ _ _ _ SYNC/HUNT

' - - - - - - -_ _ PARITY ERROR

' - - - - - - - - - ' - - n. OVERRUN ERROR

' - - - - - - - - - _ CTS
' - - - - - - - - - - - - Tx UNDERRUN/EOM

' - - - - - - - - - - - - - CRe/FRAMING ERROR

' - - - - - - - - - - - - - - BREAKJABORT

' - - - - - - - - - - - - - - END OF fRAME (SOLe)

:I

CHANNEL B EXT/STAT IP'

CHANNEL B Tx 'P'
' - - - : - - - CHANNEL B Rx 'P'

' - - - - - V,

' - - - - - - - V3

'------'-CHANNEL A EXT/SlAT IP'

INTERRUPT VECTOR·

~~:~
'-------------~

' - - - - - - - - - C H A N N E l A Tx 'P'
' - - - - - - - - - - C H A N N E L A Rx Ip·

'-------------0

'---------------------v,

"ALWAYS 0 IN B CHANNEL

'MODIFIED IN B CHANNEL

Tcol

ON LOOP

TC,

TC,

~~:j

'---~----- LOOP SENDING

LOWER BYTE OF
TIME CONSTANT

TC,
TC,

.....- - - - - - - - - - - - TWO CLOCKS MISSING

TC,

' - - - - - - - - - - - - - - ONE CLOCK MISSING

:~:

'-----TC'o
' - - - - - - - Te'l

I

ZERO COUNT IE
' - - - - - - - C D IE

UPPER BYTE OF

TC'2 \ TIME CONSTANT

' - - - - - - - - SYNC/HUNT IE

' - - - - - - - - - - elSIE

' - - - - - - - - - - - TC'3

' - - - - - - - - - - - - Ta UNDERRUN/EOM IE

' - - - . . . . . ; - - - - - - - - - TC'4

' - - - - - - - - - - - - - - BREAK/ABORT IE

' - _ - - - - - - - - - - - - TC15

Figure 9, Read Register Bit Functions

9-98

230834-002

82530/82530-6

WRITE REGISTER 0

I 0,1 0,1 0,

0,

OJ

I

02

0,

0
0

0
0

DO

I
REGISTER

o

0

Rx ENABLE

,.,

1

SYNC CHARACTER LOAD INHIBIT

0

1

0

2.,

10

0
1

1
0

1
0

3.,
4.,

11
12

1

0

1

5.,

13

1

1

0

1

!-oft
I-;-roI-TI-T
1,..;..,--

D.,

0

1

..

,

' - - - - - - Rx CRe ENABLE
' - - - - - - - - ENTER HUNT MODE
' -_ _ _ _ _ _ _ _ AUTO ENABLES
o

14

7.,

1

' - - - - ADDRESS SEARCH MODe (SDLe)

Rx 6 BITs/CHARACTER

1

0

0

0

NULL CODE

0

0

1

POINT HIGH REGIS TER GROU

0
0

1

0

FRESET EXT/STATUS INTERRUPTS

1

1

SENDADORT

1

0

0

ENABLE INT ON NE XT Rx CHARACTER

1

0

1

RESET TIC INT PEND lNG

1

1

ERROR RESET

1

1

0
1

Rx 5 BITS/CHARACTER

Ax 7 BITS/CHARACTER

15

Ax 8 BITs/CHARACTER

WRITE REGISTER.

PARITY ENABLE
PARITY EVEN/ODD

RESET HIGHEST IU
, STOP BIT/CHARACTER

NULLCDDE

111) STOP BITS/CHAR~CTER

RESET Rx CRe CHECKER

2 STOP BIT&'CHARACTER

RESET Tx CRe GENERATOR

REseT Tx UNDERRUN/EOM LArCH

SOLe MODE (01111110 FLAG)
EXTERNAL SYNC MODE
EXT. INT ENABLE

TxlNT ENABLE
L..-----PARITy IS SPECIAL CONDITION

o

Rx INT DISABLE

1 RxlNT ON FIRST CHARACTER OR SPECIAL CONDITION
OINT ON ALL Rx CHARACTERS OR SPECIAL CONDITION
1

Rx INT ON SPECIAL CONDITION ONLY

'-----_READY/DMAAEQUESTON RECEIVEITRANSMIT.
L - - - - - - - R E A D Y / D M A REQUEST FUNCTION
L..-_ _ _ _ _ _ _ _ READY/DMA REQUEST ENABLE

Tx CRC ENABl.E

ATS
' -_ _ _ _ S'6LC/CRC-1•
.....- - - - - - Tx ENABLE

~I

SEND BREAK
Tx 5 BITS (OR LESS)/CHARACTER

.....- - - - V,

.....------v,

Tx 7 BITS/CHARACTER
INTERRUPT VECTOR

Tx 6 BITS/CHARACTER

:: \

Tx 8 BITS/CHARACTER

L..-_ _ _ _ _ _ _ _ _ _ _ V,

L _____________ "

OTR

.'

SVNC7
SYNC1
SYNCT
SYNC3
ADR7
ADR7

SYNC6
SYNCo
SYNC6
SYNCz
ADRe
ADRs

SYNCs
SYNCs
SYNCs
SYNC,
ADRs
ADRs

SYNC4
SYNC4
SYNC4
SYNCo
ADR4
AOR4

SYNC3
SYNC3
SYNC3

SYNCz
SYNCz
SYNCz

SYNC,
SYNC,
SYNC,

1

1

ADR3

ADRz

ADR,

ADRo

X

X

X

X

1

SYNCo
SYNCo
SYNCo

1

MONOSYNC 8 BITS
MONOSYNC 8 BITS
BISYNC 16 BITS
BISYNC 12 BITS
SOLe
SOLe (ADDRESS RANGE)

Figure 10. Write !-leglster Bit Functions

9-99

230834-002

82530/82530-6

SYNC,
SYNCs

SYNC,
SYNC.
SYNC,.
SYMetD
1

SYNC~

,

SYNen

- SYNCS
SYNCl
SYNen

SYNC.
SYNC2

SYNC,

SYNCo

SYNC12

SYNC,

SYNC,
1

SYNC'T

SYHe'D
SYNC,
1

1

SVNe3

SYNC:2

SYNC,.
1

SY~Co

SYNC,

X

SYNC,
SYNCS

SYNC.
SYNC.

o

1

MONOSYNC 8 BITS
MONOSVNC B BITS
BISYNC 16 BITS

BISYNC 12 BITS
SOle

:~:

VIS

NV
.L...._'----0":
_ _ _ _ MIE

' - - - - Te,

I

' - - - - - - Tel

' - - - - - - - S T A T U S HIGH/!l'&'fUi"LOW

Te, \
' - - - - - - - - - Te,

LoweR BYTE OF

TI~E CONSTANT

' - - - - - - - - - - - Te,
L...._ _ _- '_ _ _ _ _ _ _ Te,

FORCE HARDWARE RESET

:~: 1

6 BIT 8 BIT SYNC

' - - - - TCTO
L...._ _ _ _ _ leu

lOOP MODE

UPPER BYTE' OF

T~t2 \TIME CONSTANT

L -_ _ _ ABORTI ..
'LAG...,.,O"'NiTU"'N"'DE"'RIii.U"'N

' - - - - - - - - - Teu

' - - - - - - MARK/FLAG IDLE

L...._ _ _ _ _ _ GO ACTIVE ON ROLL

'_
--_
-_
-_
- le,s
TCt.
L...._
____
_
_

NRZ

NRZI
FMl (TRANSMISSION

II

FMO (TRANSMISSION

0)

L...._ _ _ _ _ _ _ _ _ _ _ CRe PRESETllS
aR GENERATOR ENABLE

BA GENERATOR SOURCE

m

REQUEST .fUNCTION
L...._ _ _- ' - AUTO ECHO
' - - - - - - - LOCAL LOOPBACK

o

a

a

a a
o 1
a
~O/I

TRANSMIT CLOCK • ~ PIN
TRANSMIT CLOCK ~

'i'Ri1! P1N

o

TRANSMIT CLOCK: BR GENERATOR OUTPUT

1

TRANSMIT CLOCK = DPLL OUTPUT

ENTER SEARCH MODE
RESET MISSING CLOCK

f

t
t
,

a

1

NULL COMMAND

DISABLE DPLL
SET SOURCE 3 SA GENERATOR
SETSOUACE:~

t

1
0

1

1

SET NAZI MODE

0

SET FM MOOE

ZERO COUNT IE
' -_ _ _ 0

L....-------..,--_ii'i'iCUALJKoXIil'

L...._ _ _ _ _ CDIE
L...._ _ _ _ _ _ _ SYNC/HUNT IE
L-_ _ _ _ _ _ _ _ CTSI'
L....----------T.UNDEARUNlEOM IE

L------------8AEAKIABORTIE

Figure 10. Write

R~gister

Bit Functions (Cont.)

9-100

230834-002

82530/82530-6

82530 TIMING

Write Cycle Timing

The SCQJlenerates internal control signals from
.WR and RD that are related to ClK. Since ClK has
no phase relationship with WR and RD, the circuitry
generating these internal control signals must provide time for metastable conditions to disappear.
Thisgives risetoa recovery time related to ClK. The
recovery time applies only between bus transactions involving the SCC. The recovery time required
for.Q!!>per~raton is specified from the rising edge
of WR or l1iJ in the first transaction involving the
SCC to the falling edge of WR or 1fD in the second
transaction involving the SCC. This time must be at
least 6 ClK cycles plus 200ns.

Figure 12 illustrates Write cycle timing. Addresses
on AlB" andDiC' and the status on iNTA must remain
stable throughout the cycle. IfCSfalis after WRfalis
or if it rises before WR rises, the effective iNA is
shortened.

Read Cycle Timing
j

Figure 11 illustrates Read cycle timing. Addresses
on AlB and DIG and the status on INTA must remain
stable throughout the cycle. If ~ falls after RD falls
or if it rises before ~ rises, the effective Rri is
shortened.

X

AlB.oie

iNfA

C;

Ri5

DBO-DB7

Interrupt Acknowledge Cycle Timing
Figure 13 illustrates Interrupt Acknowledge cycle
timing. Between the time INTA goes low and the
falling edge ofRD, the internal and externallEI/IEO
daisy chains settle. If there is an interrupt pending in
the SCCand lEI is High when 'Ri5falls, the Acknowledge cycle is intended forthe SCC. In this case, the
SCC may be prog rammed to respond to AD low by
placing its interrupt vector on Do-D7 and it then sets
the appropriate Interrupt-Under-Service internally.

X

AODRESS VALID

=-;

\

/

\
/

\

X

(

DATA VALID

)

Figure 11. Read Cycle Timing
9-101

230834-002

82530/82530~6

X

Alii. DIe

iNTA.

X

ADDRESS VALID

I

Co

\

I

\

DBG-DB7

I

\

WR

(

>

DATA VALID

Figure 12. Write Cycle Timing

INTA~

AD

DBO-DB7

IS
IS

II

I
/

\

<

X

VECTOR

>

Figure 13. Interrupt Acknowledge Cycle Timing

9-102

230834-002

82530/82530-6

ABSOLUTE MAXIMUM RATINGS·
Case Temperature
Under Bias ........................ O°C to + 70°C
Storage Temperature
(Ceramic Package) ............. -65°C to +150°C
(Plastic Package) ............... - 40°C to + 125°C
Voltage On Any Pin With
Respect to Ground .............. -0.5V to + 7.0V

'NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

D.C. CHARACTERISTICS (Tc=O° C to 700 C; Vcc=+5V±10%)
Symbol

Parameter

Min.

Input Low Voltage

-0.3

+0.8

V

VIH

Input High Voltage

+2.4

Vee + 0.3

V

VOL

Output Low Voltage

VO H

Output High Voltage

III

Input leakage Current

IOl

Output Leakage Current

ICC

Vee Supply Current

250

mA

Vil

CAPACITANCE

Max.

Units

Test Conditions

V

IOl

V

10H = -250 p.A.

±10

p.A

0.4to 2.4V

:::10

p.A

0.4 to 2.4V

+0.40
+2.4

=

2.0mA

(Tc=25°; Vcc=GND=OV)
Test Conditions

Max.

Units

C IN

Input Capacitance

10

pF

Ic = 1 MHz;

C OUT

Output Capacitance

15

pF

Unmeasured

CliO

Input/Output Capacitance

20

pF

Symbol

Parameter

Min.

pins returned
toGND

9-103

230834-002

inter

82530/82530-6

A.C CHARACTERISTICS (Tc=O° C to 700 C;

Vcc=+5V

±10%)

READ AND WRITE TIMING
82530 (4MHz)
Number Symbol

1
2
3
4
5
6
7
8
9
10
11
12
13
14
,15
16
17
18
19
20
21
22
24
25
26

82530-6 (6 MHz)

Parameter

Min

Max

Min

Max

tCl

ClK low Time

tCH

ClK High Time

105
105

70
70

tf

ClK Fall Time

tr

ClK Rise Time

tCY

ClK Cycle Time

2000
2000
20
20
4000

1000
1000
10
15
2000

tAW

Address to WR! Setup Time

tWA

Address to WR! Hold Time

tAR

Address to

tRA

Address to RD! Hold Time

tiC

INTA to ClK! Setup Time

tlW

iNTA to iiVRi Setup Time (Note 1)

tWI

iN'i'A to WRi

Hold Time

tlR

i1'JTA to RD!

Setup Time (Note 1)

tRI

INTA to m5'! Hold Time

tCI

INTA to CLK! Hold Time

tClW

Cs low to WR!

tWCS

~ to WA! Hold Time

Ri5i Setup Time

250
80
0
80
0
5
200
0

tCHW

e-s High to WR! Setup Time

tClR

CS low to RD! Setup Time (Note 1)

tRCS

~ to '1m! Hold Time (Note

tCHR

CS High to R"D!Setup Time (Note 1)

200
0
100
0
0
100
0
0
100

tRR

RD Low Time (Note 1)

390

tRDI

AD! to Data Not Valid Delay

tRDV

RD! fo Data Valid Delay

tDF

AD! to Output Float Delay (Note 2)

Setup Time

1)

165
0
0
0
0
5
200
0

250
70

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

55
,0
100
0
0
70
0
0
5
250
0

0

Units

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

180
45

ns
ns

NOTES:
1. Parameter does not apply to Interrupt Acknowledge transactions.
2. Float delay is defined as the time required for a + O.SV change
in the output with a maximum D.C load and minimum A.C load.

'Timings are preliminary and subject to change.

9-104

230834-002

82530/82530-6

A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUT OUTPUT

2.4

2.0

O.

0.45---/

>

<

2.0

TEST POINTS

0.8

A.C. TESTING: INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC ""I AND 0.45V
FOR A LOGIC "0." TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A
LOGIC "1" AND 0.8V FOR A LOGIC 0 .

A.C. TESTING LOAD CIRCUIT

DEVICE
UNDER
TEST

CL=150pF

'1"."""
-=

CL INCLUDES JIG CAPACITANCE

OPEN DRAIN TEST LOAD

+5V

2.2K

SOpF

9-105

I

230834-002

inter

82530/82530-6

eLK

Ali. DIe::)

DBO-DB7

ll(
~~--~(.~~~----r----+--------~~---®9~_~~7{~~~@~o~_--------

~---r---@'----+---~
--------+-"\.vrJ,,...f-iI---+--";;~--+--~"""'lV'---------

~~W~RIT~E -----------~~~,~~--~~--~----_+------r_~~,~-------------RE~~~~EQ

___________+®.;:;19_-.:......l1-"-f1__-.,;1®~1

I-i-®

,

__""'\

f"--

~---+-®)-+----i

~----~----+------------------

R~:gJ~~~Q ----------~-----+t-::---"""":'I®-d-I--.J~
~
REQUEST -

~--~®)~~--~

+-_______

____________--:'______I-________

....J~

I---@-

iIT -----------~----~~\

~----------------

Figure 14. Read and Write Timing

9-106

230834-002

inter

82530/82530-6

INTERRUPT ACKNOWLEDGE TIMING, RESET TIMING, CYCLE TIMING
82530 (4MHz)
Number Symbol

27

tAD

Min

Parameter

Address Required Valid to Read Data

Max

82530-6 (6 MHz)
Min

590

Max

Units

325

ns

Valid Delay
28

TWW

WR Low Time

29
30
31

tOW

Data to WFj! Setup Time

tWD
tWRV

Data to WRf Hold Time
WR! to Ready Valid Delay (Note 4)

32

tRRV

33
34

390

ns

60
0
0

0
0

ns
ns
200

RD! to Ready Valid Delay (Note 4)

240
240

200

ns
ns

tWRI

WR! to READY/REQ Not Valid Delay

240

200

ns

35

tRRI
tOWR

AD! to READY/REa Not Valid Delay
WRf to DTR/REQ Not Valid Delay

240
5 tCY
+ 300

200
5tCY
+250

ns
ns

36

tORD

RDf to DTR /REQ Not Valid Delau

5tCY
+300

5tCY
+250

ns

37

tIID

INTA to RD! (Acknowledge) Delay
(Note 5)

250

250

ns

38

til

RD (Acknowledge) low Time

39

t1DV

RD! (Acknowledge) to Read Data
Valid Delay

40
41

tEl
tiE

lEI to RD! (Acknowledge) Setup Time

42
43

tEIEO

lEI to lEO Delay Time

120

100

ns

ClKf to lEO Delay

250

250

ns

44
45
46

tCEQ
tRII

RD! to INT Inactive Delay (Note 4)

500

500

tRW

RDf to WR! Delay for No Reset

tWR

WRf to RD! Delay for No Reset

47

tRES

WR and RD Coincident low
for Reset

48

tREC

Valid Access Recovery Time
(Note 3)

lEI to RDf (Acknowledge) Hold Time

125

285
190

100

120

100

0

0

30
30

ns

15

ns
ns
ns

ns

30

ns
ns

250

250

ns

6tCY
+ 200

6tCY
+ 130

ns

NOTES:
3. Parameter applies only between transactions involving the SCC.
4. Open-drain output, measured with open-drain test load.
5. Parameter is system dependent. For any SCC in the daisy chain, tiiD must be greater than the sum of tCEQ forthe highest
priority device in the daisy chain, tEl for the SCC and tEIEO for each device separating them in the daisy chain.

'Timings are preliminary and subject to change.

9-107

230834-002

82530/82530-6

ClK
INTA _ _ _ _ _ _ _""\

RD _ _ _ _ _ _

DBO-DB7

~

__

~

__

~~_~

---------+-----___I-+--::::r:-

lEI

lEO

®='~-Figure 1.5. Interrupt Acknowledge Timing

Figure 16. Reset Timing

CS

RDORWR~

Sf

/
@

\

r

S

\

\

Figure 17. Cycle Timing

9-108

230834·002

inter

82530/82530-6

GENERAL TIMING

82530 (4MHz)
Number
Symbol
- _.. _-1
tRCC

Units

100

100

ns

0

0

ns

150

150

ns

0

0

ns

150

150

ns

-200
3tCY
+ 200
10g

-200
3tCY
+ 200
100

ns
ns

RxD to RxC! Setup Time (X1 Mode)
(Note 1)

3

tRCA

AxD to AxC! Hold Time (X1 Mode)
(Note 1)

4

IOAC

AxD to AxCI Setup Time (X1 Mode)
(Notes 1,5)

5

tACO

AxD to AxCI Hold Time (X1 Mode)
(Notes 1,5)

6
7

tSAC
tACS

SYNC to AxCI Setup Time (Note 1)
SYNC to AxC! Hold Time (Note 1)

8

tTCC

9

tTCT

10

!TCD

TxCI to ClK! Setup Time (Notes 2,4)
TxCI to TxD Delay (X1 Mode)
(Note 2)
TxC! to TxD Delay (X1 Mode)
(Notes 2,5)

11

tTDT

TxD to 'FRXC Delay (Send Clock
Echo)

12
13

lOCH
IOCl

ATxC High Time
ATxC low Time

14

IOCY

RTxC Cycle Time

15

tClCl

Crystal Oscillator Period
(Note 3)

16

tACH

17

tACl
tACY

TAxC High Time
TAxC low Time
TAxC Cycle Time (NOTE 6)

tCC
tSS

20

Max

RxC! to ClK! Setup Time (Notes 1,4)

tRRC

18
19

Min

Min

2

(NOTE 6)

Max

82530-6 (6 MHz)

Parameter

300

300

ns

300

300

ns

200

ns

200
180
180
4TCY
250

ns

ns
ns

180
180
4TCY
1000

250

ns
1000

ns

180
4TCY

80
180
4TCY

ns
ns

CD or CTS Pulse Width

200

200

ns

SYNC Pulse Width

200

200

ns

180

ns

NOTES:
1. RxC is RTxC or TRxC, whichever is supplying the receive clock.
2. 'iXC is TRXC or RTxC, whichever is supplying the transmit clock.
3. Both RTxC and SYNC have 30pF capacitors to ground connected to them.
4. Paramete.!.,!!Eplies only if t~ata rate is one-fourth the system clock (elK) rate. In all other cases, no phase relationship
between RxC and ClK or TxC and ClK is required.
5. Parameter applies only to FM encoding/decoding.
"6. Only applies to transmitted receivers. For DPlL and BAND RATE Generator timings Requirements are identical to CHIP PC1K Requirements.
'Timings are preliminary and subject to change.

9-109

230834-002

82530/82530-6

~~--~---1==®~

"J\~---

Figure 18. General Timing

9-110

230834-002

inter.

© Intel Corporation, 1976

APPLICATION
NOTE

9-111

AP-16

Order Number: 231309-001

Using the 8251
Universal Synchronous/
Asynchronous
Receiver/Transmitter

Contents
INTRODUCTION
COMMUNICATION FORMATS
BLOCK DIAGRAM

. Receiver
Transmitter
Modem Control
1/0 Control
INTERFACE SIGNALS

CPU-Related Signals
Device-Related Signals
MODE SELECTION
PROCESSOR DATA LINK
CONCLUSION

APPENDIX A

8251 Design Hints

9-112

231309-001

APPLICATIONS
INTRODUCfION
The Intel 8251 is a Universal Synchronous/Asynchronous Receiver/Transmitter (USART) which is
capable of operating with a wide variety of serial
communication formats. Since many peripheral
devices are available with serial interfaces, the 8251
can be used to interface a microcomputer to a
broad spectrum of peripherals, as well as to a serial
communications channel. The 8251 is part of the
MCS-80™ Microprocessor Family, and as such it is
capable of interfacing to the 8080 system with a
minimum of external hardware.
This application note describes the 8251 as a component and then explains its use in sample applications via several examples. A specific use of the
8251 to facilitate communication between two
MCS-80 systems is discussed in detail from both
the hardware and software viewpoints. The first
two sections of this application note describe the
8251 ·first from a functional standpoint and then
on a detailed level. The function of each input and
·output pin is fully defined. The next section describes the various operating modes and how they
can be selected, and finally, a sample design is discussed using the 8251 as a data link between the
MCS-80 systems.

has to last for the duration of the character (the
next character will contain a new START bit), this
method works quite well assuming a properly
designed receiver. One or more STOP bits are
added to the end of the character to ensure that
the START bit of the next character will cause a
transition on the communication line and to give
the receiver time to "catch up" with the transmitter if its basic clock happens to be running slightly
slower than that of the transmitter. If, on the other
hand, the receiver clock happens to be running
slightly faster than the transmitter clock, the receiver will perceive gaps between characters but·
will still correctly decode the data. Because of this
tolerance to minor frequency deviations, it is not
necessary that the transmitter and receiver clocks
be locked to the identical frequency for successful
asynchronous communication.
The synchronous format, instead of adding bits to
each character, groups characters into records and
adds framing characters to the record. The framing
characters are generally known as SYN characters
and are used by the receiver to determine where
the character boundaries are in a string of bits.
Since synchronization must be held over a fairly
long stream of data, bit synchronization is j1ormally either extracted from the communication
channel by the modem or supplieq from an external source.

COMMUNICATION FORMATS
Serial communications, either on a data link or
with a local peripheral, occurs in one of two basic
formats; asynchronous or synchronous. These formats are similar in that they both require framing
information to be aMed to the data to enable
proper detection of the character at the receiving
end. The major difference between the two formats is that the asynchronous format requires
framing information to be added to each character,
while the synchronous format adds framing information to blocks of data, or messages. Since the
synchronous format is more efficient than the
asynchronous format but requires more complex
decoding, it is typically found on high-speed data
links, while the asynchronous format is used on
lower speed lines.
The asynchronous format starts with the basic data
bits to be transmitted and adds a "START" bit to
the front of them and one or more "STOP" bits
behind them as they are transmitted. The START
bit is a logical zero, or SPACE, and is defined as
the positive voltage level by RS-232-C. The STOP
bit is a logical one, or MARK, and is defined as the
negative voltage level by RS-232-C. In current loop
applications current flow normally indicates a
MARK and lack or-eurrent a SPACE. The START
bit tells the receiver toStart assembling a character
and allows the receiver to synchronize itself with
the transmitter. Since this synchronization only

An example of the synchronous and asynchronous
formats is shown in Figure 1. The synchronous
format shown is fairly typical in that it requires
two SYN characters at the start of the message.
The asynchronous format, also typical, requires a
START bit preceding each character and a single
STOP bit following it. In both cases, two 8-bit
characters are to be transmitted. In the asynchronous mode 1O*n bits are used to transmit n characters and in the synchronous mode 8N + 16 bits are
used. For the example shown the asynchronous
mode is actually more efficient, using 20 bits
versus 32. To transmit a thousand characters in the
asynchronous mode, however, takes 10,000 bits
versus 8,016 for the synchronous format mode.
For long messages the synchronous format becomes much more efficient than the asynchronous
format; the crossover point for the examples
sbown in Figure 1 is eight characters, for which
both formats require 80 bits.
In addition to the differences in format between
synchronous and asynchronous communication,
there are differences with regards to the type of
modems that can be used. Asynchronous modems
typically employ FSK (Frequency Shift Keying)
techniques which simply generate one audio tone
for a MARK and another for a SPACE. The receiving modem detects these tones on the telephone
9-113

231309-001

APPLICATIONS

--r \--

---J f I

I I I I I I I I I I I I I

STOPBIT

DATA

DATA

START BIT

STOP BIT

ASYNCHRONOUS

SYN

DATA

CHAR #2

SYN
CHAR #1

Figure 1. Transmission Formats
.

.

8251 appends I, 1Y2, or 2 STOP bits. Proper framing is checked by the receiver and a status flag set
if an error occurs. In the asynchronous mode the
USART can be programmed to accept clock rates
of 16 or 64 tiines the required baud rate. Isosynchronous operation is a special case of asynchronous with the multiplier rate programmed as one
instead of 16 or 64. Note that X1 operation is only
valid if the clocks of the receiver and transmitter
are synchronized.
The 8251 USART can transmit the three formats
in half or full duplex mode and is double-buffered
internally (Le., the software has a complete character time to respond to a service request). Although.
the 8251 supports basic data set control signals
(e.g., DTR and RTS), it does not fully support the
signaling described in EIA-RS-232-C. Examples of
unsupported signals are Carrier Detect (CF), Ring
Indicator (CE), and the secondary channel signals.
In some cases an additional port will be required to
implement these signals. The 8251 also does not
interface to the voltage levels required by EIARS-232-C; drivers and receivers must be added to
accomplish this interface.

line,. converts them to logical signals, and presents
them to. the receiving terminal. Since the modem
itself is'not concerned with the transmission speed,
it can handle baud rates from zero to its maximum
speed. Synchronous modems, in contrast to asynchronous modems, supply timing information to
the terminal and require data to be presented to
them in synchronism with this timing information.
Synchronous modems, because of this extra clocking, are only capable of operating at certain preset
baud rates. The receiving modem, which has an
oscillator running at the same frequency as the
transmitting modem, phase locks its clock to that
of the transmitter and interprets changes of phase
as data.
In some cases it is desirable to operate in a hybrid
mode which involves transmitting data with the
asynchronous format using a synchronous modem.
This occurs when an increase in operating speed is
required without a change in the basic protocol of
the system. This hybrid technique is known as
isosynchronous and involves the generation of the
start and stop bits associated with the asynchronous format, while still using the modem clock for
bit synchronization.
The 8251 USART has .been designed to me~t a
broad spectrum of requirements in the synchronous, asynchronous, and isosynchronous modes. In
the synchronous mode the' 8251 operates with 5,
6, 7, or 8-bit characters. Even or odd parity can be
optionally appended and checked. Synchronization
can be achieved either externally via added hardware or internally ·via SYN character detection.
SYN detection can be based on one or two characters which mayor may not be the same. The single
or double SYN .characters are inserted into the
data stream automatically if the software fails to
supply. data in time. The automatic generation of
SYN characters is required to prevent the loss of
synchronization. In. the asynchronous mode the
8251 operates with the same data and parity structures as it does in the synchronous mode. In addition to appending a START bit to this data, the

BLOCK DIAGRAM
A block diagram of the 8251 is shown in Figure 2.
.As can be seen in the figure, the 8251 consists of
five major sections which communicate with each
other on an internal data bus. The five sections are
the receiver, transmitter, modem control, read/
write control, and I/O Buffer. In order to facilitate
discussion, the I/O Buffer has been shown broken
down into its three major subsections: the status
buffer, the transmit data/command buffer, and the
receive data buffer.
Receiver
The receiver accepts serial. data on the RxD pin and
converts it to parallel data according to the appropriate format. When the 8251 is in the asynchronous mode and it is ready to accept a character
9-114

231309-001

APPLICATIONS

TRANSMITTER
(P-S)

RESET~

eLK---

TxRDY·
T,E

TRANSMIT
(CONTROLI

T,e

RxRDY
RECEIVER

(CONTROL)
DTR

~_~-L

RECEIVER

SYNDET

f-.---"FW:

f-.---

__~IS~-P~I__J

R,D

Figure 2. 8251 Block Diagram

RxD line one bit at a time. After each bit is received, the receiver register is compared to a register holding the SYN character (program loaded).
If the two registers are not equal, the 8251 shifts in
another bit and repeats the comparison. When the
registers compare as equal, the 8251 ends the
HUNT mode and raises the SYNDET line to indicate that it has achieved synchronization. If the
USART has been programmed to operate with two
SYN characters the process is as described above,
except that two contiguous characters from the
line must compare to the two stored SYN characters before synchronization is declared. Parity is
not checked. If the USART has been programmed
to accept external synchronization, the SYNDET
pin is used as an input to synchronize the receiver.
The timing necessary to do this is discussed in the
SIGNALS section of this note. The USART enters
the HUNT mode when it is initialized into the
synchronous mode or when it is commanded to do
so by the command instruction. Before the receiver
is operated, it must be enabled by the RxE bit (D2)
of the command instructions. If this bit is not set
the receiver will not assert the RxRDY bit.

(Le., it is not in the process of receiving a character), it looks for a low level on the RxD line. When
it sees the low level, it assumes that it is a START
bit and enables an internal counter. At a count
equivalent to one-half of a bit time, the RxD line is
sampled again. If the line is still low, a valid
START bit has probably been received and the
8251 proceeds to assemble the character. If the
RxD line is high when it is sampled, then either a
noise pulse has occurred on the line or the receiver
has become enabled in the middle of the transmission of a character. In either case the receiver
aborts its operation and prepares itself to accept a
new character. After the successful reception of a
START bit the 8251 clocks in the data, parity, and
STOP bits, and then transfers the data on the
internal data bus to the receive data register. When
operating with less than 8 bits, the characters are
right-justified. The RxRDY signal is asserted to
indicate that a character is available.
In the synchronous mode the receiver simply
clocks in the specified number of data bits and
transfers them to tl1(! receiver buffer register,
setting RxRDY. Since the receiver blindly groups
data bits into characters, there must be a means of
synchronizing the receiver to the transmitter so
that the proper character boundaries are maintained in the serial data stream. This synchronization is achieved in the HUNT mode.
In the HUNT mode the 8251 shifts in data on the

Transmitter
The transmitter accepts parallel data from the
processor, adds the appropriate framing information, serializes it, and transmits it on the TxD pin.
In the asynchronous mode .the transmitter always
9-115

231309-001

APPLICATIONS
adds a START bit; depending on how the unit is
programmed, it also adds an optional even or odd
parity bit, and either I, I \12, or 2 STOP bits. In the
synchronous mode no extra bits (other than parity,
if enable) are generated by the transmitter unless
the computer fails to send a character to the
USART. If the USART is ready to transmit a character and a new character has not been supplied by
the computer, the USART will transmit a SYN
character. This is necessary since synchronous
communications, unlike asynchronous communications, does not allow gaps between characters. If
the USART is operating in the dual SYN mode,
both SYN characters will be transmitted before the
message can be resumed. The USART will not
generate SYN characters until the software has supplied at least one character; i.e., the USART will
fill 'holes' in the transmission but will not initiate
transmission itself. The SYN characters which are
to be transmitted by the USART are specified by
the software during the initialization procedure. In
either the synchronous or asynchronous modes,
transmission is inhibited until TxEnable and the
CTS input are asserted.
An additional feature of the transmitter is the ability to transmit a BREAK. A BREAK is a period of
continuous SPACE on the communication line and
is used in full duplex communication to interrupt
the transmitting terminal. The 8251 USART will
transmit a BREAK condition as long as bit 3
(SBRK) of the command register is set.

CE

C/O

READ

WRITE

Function

0

0

0

1

CPU Reads Data from
USART

0

1

0

1

CPU Reads Status from
USART

0

0

1

0

CPU Writes Data to
USART

0

1

1

0

CPU Writes Command to
USART

1

X

X

X

USART Bus Floating
(NO-OP)

and WRITE being a zero at the same time is an
illegal state with undefined results. The Read/
Write Control Logic contains synchronization circuits so that the READ and WRITE pulses can
occur at any time with respect to the clock inputs
to the USART.
The I/O buffer contains the STATUS buffer, the
RECEIVE DATA buffer and the XMIT DATA/
CMD buffer as shown in Figure 2. Note that although there are two registers which store data for
transfer to the CPU (STATUS and RECEIVE
DATA), there is only one register which stores data
being transferred to the USART. The sharing of
the input register for both transmit data and commands makes it important to ensure that the
USART does not have data stored in this register
before sending a command to the device. The
TxRDY signal can be monitored to accomplish
this. Neither data nor commands should be transferred to the USART if TxRDY is low. Failure to
perform this check can result in erroneous data
being transmitted.

Modem Control
The modem control section provides for the generation of RTS and the reception of CTS. In addition, a general purpose output and a general purpose input are provided. The output is labeled
DTR and the input is labeled DSR. DTR can be
asserted by setting bit 2 of the command instruc~
tion; DSR can be sensed as bit 7 of the status
register. Although the USART itself attaches no
special significance to these signals, DTR (Data
Terminal Ready) is normally assigned to the
modem, indicating that the terminal is ready to
communicate and DSR (Data Set Ready) is a signal
from the modem indicating that it is ready for
communications.

INTERFACE SIGNALS
The interface signals of the 8251 USART can be
broken down into two groups - a CPU-related
group and a device-related group. The CPU-related
signals have been designed to optimize the attachment of the 8251 to a MCS-80™ System. The
device-related signals' are intended to interface a
modem or like device. Since many peripherals
(TTY,CRT, etc.) can be obtained with a modemlike interface, the USART has a broad range of
applications which do not include a modem. Note
that although the USART provides a logical interface to an EIA-RS-232 device, it does not provide
EIA compatible drive, and this must be added via
circuitry external to the 8251. As an example of a
peripheral interface application and to· aid in
understanding the signal descriptions which follow,
Figure 3 shows a system configured to interface
with a TTY or CRT.

I/O Control
The Read/Write Control Logic decodes control
signals on the' 8080 control bus into signals which
gate data on· and off the USART's internal bus and
controls the external I/O bus (DBa-DB?). The
truth table for these operations is as follows:
If neither READ or WRITE is a zero, then the

USART will not perform an I/O function. READ
9-116

231309-001

APPLICATIONS

'§ri--'!;~.J:W'-"-~:"f''t''t--,
r--------------------~

i5§

i-;-il

q

--I.lT !":III

""""

a.41(

TN R,

='c=mwn~"£"5
,",,","'neD DATA:

:

T~ ell< !bAT,. TE.RU'L RIH

!~
.: ~7

4

I

,

f'

'0'

,.

II

36

~

~D~

,, ., JOWl
~
~=~
I

P>.~'\.~

•

C

..

.,""

, I

,~

R~

<~.

'1"'''1
_.

R4

II

II

2.1'~

'"

~

Co>

Figure 10. SBe 80/10 Serial I/O

~

Ye:'tI

~

2N~O!!>

CO2

-!2V

~~

o

TTY Tx

~

-1'2....

J,:

~

:.f',oJ

'"

RET

IZ..oa...

OZM,

G

TN RO C.ONTI2.CL
TTY RD CCNTIZOL- RET

o

z
en

~

1'OR.

CDlt.l~"T1ONS

:~)~WO Xiii ......

u~m :~go,,~&~:.

-38

~f"TP~D""I_1
~i!STPT"POU'!f

CCUC:/~

P'TPOVTIt.JT/

iZ.J:lQ.

90&304 MIR.
'Ol.'7~n:olll:.

~ tl""IT !

. 0.,

~ .~
,
~
~:~-;;..

'~, ~,

~
J~.J

':~~ ••• :..
:~
~z ..as CiS "
I

~'"O'S.9;>t
=
c~~~;:;rl/
~

"~~CRT-Z2
~ ':':t"
...
•

z.o

:, .",

........T

•

=T

PTRIUP IUT/ ~

>ZoJ n •• Of!

CRTT. DlTOUT'
LPrcTLI

""

.'

ceT

.-zn, .".

DS"'/

+,zv~N"
~ '-m" ~~R
~?1.----r":

CII(cur.)

3Za!

.11

+s, ,:ruM"", CONFIGURATION. '" ~;;: ~;.:.;;. ~~ ">T ~ ...... ,
{'i'l ~\;3a ~CRT"G.U1>'
r~cn""&U1>'
";2~rt---="""'-.AI..o
. . . . . . . i cn",,""'Al.
"5ZI!ll
_+-_"".--__3
~
~,::" i :
~
_ - L -......__

•

COOT 'U.,.

•

---if----l'-h2)T----.m 1 I..PT CTI..r:./
Yi1

~DATI

I..P"T CTL.I/

TTV Ar::N"£l)~

iZM

C~t.JT/

m
"

""!;"Zs.lO ...T4

C:;

5ZIll

I\)

~~

C1I

'2.'~

~TTV

.
" TTY
~
'w

!2l
"

~

PT~ AD'V

~

t

~'DATZ.

PTIe. OR." L.FT/

P!R.

TXC""TA.

~

CE.Vi!T/

(5

TlC OATA RET

-ICV

"'i"Z.I:..2

~TTYeDIi:.CTL
. . ', I:
~

TTY EIoJ/

~

azg

TTYADV

-I

I !'4 ,~"f I , ,h~.

f,,,,,··

::v

III II J

1 1

U!!..rg~~~

~~

[@TTV~'lCMT

"I~TTY

II<.

47.<>.
-19"
RPI-3

00

Rll CAT

~L.PTtl"'TJ~
IZ1u.

A
•

Z

L.PT

OAT~T"J:.e,'

"'~IoIW2Tb/'IoTf"L.'S/

I

~£O"'" I\b't:H.IEiH-CTL -=====~~~::::=~~

~ ~Jo1"bt.~

~

L.PT ST",T/

>I

_'"

' 1\\,30

1I!id

...

DATf/I/lZ9.~

I

o"'T~1

L.PTST....TI/~

TTY r:>'SJi!J

~ ~~~,

CATl/lZf!.
r:[3J O-'TI!

.1'1

+5V~

IK

C~I..ID STlt.a

~PI:QMW~TtI"'T'"

"'iZRii

IOV

~

s~eST ~

I\U.T/

'"

~TTV'SIGG\.,It:l

SYSe5TI ~
.UTI .... LI ... E/

1"

IS

TTVIIJPI'oJ"T/

..

~

~ ~E::D$T""TU~
~PI!O""l1:.0DAT'"

''''~
J.
.,~~
il

l"e:.o.....

1C~ST,...,

PeOM l!:.Dr»rr1

... ~ P~M=-IGaCiil.lt)l
P20M ~\&G.\JDC.

3ZJ>!
"SZD!

"STTTV'UP/
'r.~T TT¥-OUTI

-,

~
~

I I"""
.~
-

I\)

~

'"

I

Figure 11. MDS Monitor Module

THOU"UT/='"

""
0

!:

DofO"T~

tn

APPLICATIONS
number which specifies how many bytes of data
USER wants transferred. The seventh and eighth
bytes are concatenated and used by USRUN to
count the number. of bytes that have been transferred. When the required number of characters
have been transferred, .or if USRUN terminates a
READ or WRITE due to an abnormal condition,
then USRUN calls a subroutine at an address defined by the ninth and tenth bytes of the command block. This subroutine, which is provided by
USER, must determine the state of the process and
then take appropriate action.

CQMMAND

STATUS
BAD LOW

BADHIOH
ReT LOW
RCTHIGH

CCTLOW
CCTHIGH

eRA LOW
CRAHIGH

I
I

THESE TWO BYTES FORM
'THE BUFFER ADDRESS
THESE TWO BYTES INDICATE

THE NUMBER OF BYTES TO

I

BE TRANSFERRED

T,HESE TWO BVTES INDICATE
THE NUMBER OF BYTES THAT

HAVE BEEN TRANSFERRED

THESE TWO BYTES FORM

THE ADDRESS OF A SUB·
ROUTINE TO BE CALlED
WHEN THE oPERATION
IS TERMINATED

Figure 12. Control Block

Since USRUN must be capable of operation in a
full duplex mode (Le., be able to receive and transmit simultaneously), it keeps the address of two
control blocks; one for a READ operation and one
for a WRITE. The address of the controlling command block is kept in RAM locations labeled .
RCBA for the READ operation and TCBA for the
WRITE operation. If RCBA (Receive Control
Block Address) or TCBA (Transmit Control Block
Address) is zero, it indicates that the corresponding
operation is in an idle status. .
Flowcharts of USRUN appear in Figure 13 and the
listings appear in Figure 14. The first section of the'
flowcharts (Figures 13.1 and 13.2) consists of two
subroutines which are used as convenient tools for
operating on the control blocks. These routines are
labeled LOADA and CLEAN. LOADA is entered
with the address of a control block in registers H
and L. Upon return registers D and E have been set
equal to the address in the buffer which is the
target of the next data transfer (Le., b,E =BAD+
CCT); and CCT (transferred byte count) has then
been incremented. In addition, the B register is set
to zero if the number of bytes that have been
transferred is equal to the number requested (i.e.,
CCT = RCT). CLEAN, the second routine, is also
entered with the address of a command block in
the Hand L registers. in addition, the Accumulator
holds the. status which will be placed in the
STATUS byte of the command block. On exit the
STATUS byte has been updated and the address of
the completion routine has been placed in Hand L.

Figure 13.1. LOADA Subroutine

Upon interrupt, control of the MCS-80 system is
transferred to VECTOR (Figure 13.3). Vector is a
program which saves the state of the system, gets
the status of the USART and jumps to the RISR
(Receive Interrupt Service Routine) or the TISR
(Transmit Interrupt Service Routine), depending
on whicli of the two ready flags is active. If neither
ready flag is active, VECTOR restores the status of
the running program, enables interrupts, and returns. (Interrupts are automatically disabled by the
hardware upon an interrupt.) This exit from VECTOR, which is labeled VOUT, is used from other

Figure 13.2. CLEAN Subroutine

9-126

231309-001

APPLICATIONS
portions of US RUN if return from the interrupt
mode is required.
In addition to handling normal data transfers,
TISR (Figure 13.4) checks a location in memory
named TCMD in order to determine if the receive
program wishes to send a command to the USART.
Since the transmit data and command must share a
buffer within the USART, any command output
must occur when TxRDY is asserted. If TCMD is
zero, TISR proceeds with the data transfer. If
TCMD is non-zero, TISR calls TUTE (Transmit
Utility, Figure 13.5) which, depending on the value

INT

Figure 13.3. Interrupt Entry

Figure 13.4. Transmit tnterrupt Service Routine

Figure 13.5. Transmit Utility Routine

9-127

231309-001

APPLICATIONS
in TCMD, turns off the receiver, turns on the receiver, or clears error conditions. Note that the
error flags (parity, framing, and overrun) are always .cleared by the software when the receiver is
first enabled.
The flowchart of the RISR is shown in Figure
13.6. Note that in addition to terminating when-.
ever the required number of characters have been
received, the RISR also terminates if one of the
error flags becomes set or if the received character
matches a character found in a table pointed to by
the label ETAB. This table, which starts at ETAB
and continues until an all "ones" entry is found,
can be used by USER to define special characters;
such as EOT (End Of Transmission), which will terminate a READ operation. The remainder of Figure 13 (13.7) shows the decoding of the commands
to USRUN. The listings also include a test USER
which exercises USRUN. This program sets up a
256-byte transmit buffer and transfers it to a similar input buffer by means of a local loop. When
both the READ and WRITE operations are complete, the test USER checks to insure that the two
buffers are identical. If the buffers differ, the MDS
monitor is called; if the data is correct, the test is
repeated.
CONCLUSION
The 8251 USART has been described both as a
device and as a component in a system. Since not
only modems but also many peripheral devices
have a serial interface, the 8251 is an extremely
useful component in a microcomputer system. A
particular advantage of the device is that it is capable of operating in various modes without requiring hardware modifications to the system of which
it is a part. As with any complex subsystem, however, the 8251 USART must be carefully applied
so that it can be utilized to full advantage in the
overall system. It is hoped that this application
note will aid in the designer in the application of
the 8251 USART. As a further aid to the application of the 8251, the appendix of this document
includes a list of design 'hints based on past experience with the 8251.

Figure 13.6. Receive Interrupt Service Routine

9-128

231309-001

APPLICATIONS

NO

Figure 13.7. URUN Command Decode

9-129

231309-001

APPLICATIONS
Figure 14. Program Listing

.***1*
,
SYSTEM ORIGIN STATEMENT
j
.*****
,
4000

ORG

4000H

,·****1
DATA STORAGE FOR TEST USER
j
,.1_*14000
4100
4200
4202
4204
4206
4208
420A
420C
420E
4210
4212
4214
4216

5200
0040
FFOO
0000
1742
5700
0041
FFOO
0000
2742
4300
00

BUFIN:
BUFOUT:
RBLOCK:
RBAD:
RRCT:
RCCT:
RCRA:
TBLOCK:
TBAD:
TRCT:
TCCT:
TCRA:
GBLOCK:
FLAG:

DS
DS
DB
DW
DW
DW
DW
DB
DW
DW
DII
DW
DB
DB

100H
100H
'R',OOH
BUFIN
OFFH
OOH
RCR
'w' ,OOH
BUFOUT
OFFH
OOH
TCR
'C',OOH
OOH

jINPUT BUFFER
jOUTPUT BUFFER
jRECEIVE CONTROL BLOCK

jTRANSMIT CONTROL BLOCK

,
.*****
COMPLETION ROUTINES
j
;*****
42.17
4218
421B
421E
4221
.4223
4226
4227
4228
422B
422E
4231
4233
4236

AF
323B42
323C42
3A1642
E60F
321642
C9
AF
323942
323A42
3A1642
E6FO
321642
C9

RC R:

TCR:

XRA
STA
STA
LDA
ANI
STA
RET
XRA
STA
STA
LDA
ANI
STA
RET

A
RCBA
RCBA+l
FLAG
OFH
FLAG
A
TCBA
TCBA+l
FLAG
OFOH
FLAG

jCLEAR A
jTURN OFF RECEIVE
jGET FLAG
jCLEAR UPPER FOUR BITS
jRESTORE FLAG
jCLEAR A
jTURN OFF TRANSMIT
jGET FLAG
jCLEAR LOWER FOUR BITS
jRESTORE FLAG
jTHEN RETURN

9-130

231309-001

APPLICATIONS

,.*****
SYSTEM EQUATES
j
,.*****
00F5
00F5
00F4
00F4
0000
OOFF
0001

USTAT
USCMD
USDAI
USDAO
GSTAT
BSTAT
CEND

EQU
EQU
EQU
EQU
EQU
EQU
EQU

OF5H
OF5H
OF4H
OF4H
00 H
OFFH
01H

jUSART STATUS ADDRESS
jUSART CMD ADDRESS
jUSART DATA INPUT ADDRESS
jUSART DATA OUTPUT ADDRESS
jGOOD STATUS
jBAD STATUS

,.*****
SYSTEM DATA TABLE
j
,.*****
4237
4238
4239
423B
423D

00
00
0000
0000
FF

LCMD:
TCMD:
TCBA:
RCBA:
MTAB:

DB
DB
DW
DW
DB

OOH
OOH
DOH
DOH
OFFH

jCURRENT OPERATING COMMAND
jIF NON ZERO A COMMAND TO BE SENT
jADDRESS OF XMIT CBLOCK
jADDRESS OF RECEIVE CBLOCK
jEND CHARACTER TABLE

9-131

231309-001

APPLICATIONS
•• * ••
LOAD ADDRESS ROUTINE
LOADA IS ENTERED WITH THE ADDRESS OF A CONTROL
BLOCK IN H,L. ON EXIT D,E CONTAINS THE ADDRESS
WHICH IS THE TARGET OF THE NEXT DATA TRANSFER (BAD+CCNT)
AND B HAS BEEN SET TO. ZERO IF THE REQUESTED NUMBER OF
TRANSFERS HAS BEEN ACCOMPLISHED. CCNT IS INCREMENTED
AFTER THE TARGET ADDRESS HAS BEEN CALCULATED .

• ****
423E
423F
4240
4241
4242
42 4 3
4244
4245
4246
4247
4248
4249
424A
4248
424C
4240
424E
424F
4250
4251
4252
4253
4254
4255
4256
4257
4258
4259
425A

23
23
5E
23
56
23
23
23
4E
23
46
EB
09
EB
03
70
2B
71
OB
2B'
7E
90
47
CO
2B
7E
91
47
C9

LOADA:

INX
INX
MOV
INX
MOV
INX
INX
INX
!-IOV
INX
MOV
XCHG
DAD
XCHG
INX
MOV
DCX
MOV
DCX
DCX
MOV
SUB
MOV
RNZ
DCX
MOV
SUB
MOV
RET

H
H
E,M
H
D,M
H
H
H
C,M
H
B,M

jD,E GETS BUFFER ADDRESS

jDONE
jB,C GETS COMPLETED COUNT (CCNT)

jDONE
jD,E GETS BAD+CCNT

B
B
M,B
H
M,C
B
H
A,M
B
B,A

jDONE
jCCNT GETS

INCREME~TED

jDONE
jDOE OLD CCNT=RCNT?

r

jNO-RETURN WITH B NOT ZERO
H
A,M
C
B,A
jRETURN WITH B=O IF RCNT=CCNT

9-132

231309-001

APPLICATIONS

,.*****
CLEAN-UP ROUTINE
CLEAN IS ENTERED WITH THE ADDRESS OF A CONTROL
BLOCK IN H,L AND A NEW STATUS TO BE
ENTERED INTO IT 'IN A. ON EXIT THE ADDRESS OF THE
CONTROL BLOCK IS IN D,E; THE STATUS OF THE BLOCK
HAS BEEN UPDATED; AND THE ADDRESS OF THE COMPLETION
ROUTINE IS IN H,L.

*****
425B
425C
4250
425E
425F
4262
4263
4264
4265
4266
4267

50
54
23
77
010700
09
7E
23
66
6F
C9

CLEAN:

NOV
MOV
INX
MOV
LXI
DAD
MOV
INX
MOV
MOV
RET

E,L
D,H
H
M,A
B,7
B
A,M
H
H,M
L,A

;SAVE THE ADRESS OF THE COMMAND BLOCK
;POINT AT STATUS
;SET STATUS EQUAL TO A
;SET INDEX TO SEVEN
;POINT AT COMPLETION ADDRESS
;GET LOWER ADDRESS
;POINT AT UPPER ADDRESS
; H GETS HIGH ADDRESS BYTE
;L GETS LOW ADDRESS BYTE

;*11***
INTERUPT VECTOR ROUTINE
VECTOR SAVES THE STATUS OF THE RUNNING PROGRAM
THEN READS THE STATUS OF THE USART TO DETERMINE
IF A RECEIVE OR TRANSMIT INTERUPT OCCURRED.
VECTOR THEN CALLS THE APPROPRIATE SERVICE ROUTINE.
IF NEITHER INTERUPTS OCCURRED THEN VECTOR RESTORES
THE STATUS OF THE RUNNING PROGAM. THE SERVICE
ROUTINES USE THE EXIT CODE, LABhED VOUT, TO EFFECT
THEIR EXIT FROM INTERUPT MODE.
;

;*****
4268
4269
426A
426B
426c
426E
4270
4271
4272
4275
4276
4277
427A
427C
427E
427F
4280
4281
4283
4286
4287

F5
C5
D5
E5
DBF5
DBFA
OF
OF
DA8842
07
07
DAD442
3EFC
D3F3
E1
01
C1
3E20
D,3FD
FB
C9

VECTOR: PUSH
PUSH
PUSH
PUSH
IN
IN
RRC
RRC
JC
RLC
RLC
JC
MVI
OUT
VOUT:
POP
POP
POP
MVI
OUT
EI
RET

PSW

;PUSH STATUS INTO THE STACK

B

D

H

USTAT
OFAH
R1SR
TISR
A,OFCH
OF3H
H

o

;GET USART ADDRESS
;MDS-GET MONITOR CARD INT. STATUS
;ROTATE TWO PLACES
;SO THAT CARRY=RXRDY
;IF RXRDY GO TO SERVICE ROUTINE
;IF NOT ROTATE BACK
;LEAVING TXRDY IN CARRY
;IF TXRDY THEN GO TO SERVICE ROUTINE
;MDS-CLEAR OTHER LEVEL THREE INTERUPTS
;MDS
;ELSE EXIT FROM INTERUPT MODE

B

A,20H
OFDH

;MDS-RESTORE CURRENT LEVEL
;MDS
;ENABLE INTERUPTS

9-133

231309-001

APPLICATIONS
j •••••

j

,••••••
4288
428B
428D
428F
4290·
4291
4294
4295
4296
4299
429C
429E
429F
42AO
42A2
42A4
42A7
42A8
42A9
42AC
42AE
42B1
42B2
42B5
42B8

2A3B42
3E82
D3F3
2C
2D
C29942
24
25
CA7E42.
CD3E42
DBF4
12
4F
DBF5
E638
C2B942
04
05
C2BE42
3EOO
217E42
E5
2A3B42
CD5B42
E9

42B9
42BB
42BE
42C1
42C2
42C4
42C7
42C8
42CB
42CC
42CF
42D1

3EFF
C3AE42
213D42
7E
FEFF
CA7E42
B9
CACF42
23
C3C142
3E01
C3AE42

RISR:

RISRB:

RISRA:

RISRE:

RECEIVE INTERUPT SERVICE ROUTINEj
RISR PROCESSES A RECEIVE INTERUPT
AT THE END OF RECEIVE THE USER SUPPLIED
COMPLETION ROUTINE IS CALLED AND THEN AN
EXIT IS TAKEN THROUGH VOUT OF THE
VECTOR
LHLD
MVI
OUT
INR
DCR
JNZ
INR
DCR
JZ
CALL
IN
STAX
MOV
IN
ANI
JNZ
INR
DCR
JNZ
MVI
LXI
PUSH
LHLD
CALL
PCHL

MVI
JMP
EXCHAR: LXI
EXA:
MOV
CPI
JZ
CMP
JZ
INX
JMP
PEND:
MVI
JMP

RCBA
A,82H
OF3H
L
L
RISRB
H
H
VOUT
LOADA
USDA!
D
C,A
USTAT
38H
RISRE
B
B
EXCHAR
A,GSTAT
H,VOUT
H
RCBA
CLEAN

jMDS-CLEAR, RECEIVE INTERUPT
jMDS

jREADY-SET UP ADDRESS
jGET INPUT DATA
jAND PUT IN THE BUFFER
jSAVE INPUT DATA IN C
jGET STATUS AGAIN
jMASK FOR ERROR FIELD
JNOT ZERO-TAKE ERROR EXIT
jB WAS 00 IF DONE

JNOT DONE-EXIT
jA GETS GOOD STATUS
jGET RETURN ADDRESS
jAND PUSH IT INTO THE STACK
jPOINT H,L AT THE CMD BLOCK
jCALL CLEANUP ROUTINE
jEFFECTIVELY CALLS COMPLETION ROUTINE
jRETURN IS TO VOUT BECAUSE OF PUSH H
A,BSTAT jA GETS BAD STATUS
jOTHERWISE EXIT IS NORMAL
RISRA
H,MTAB JTEST CHARACTER AGAINST EXIT TABLE
A,M
OFFH
jEND OF TABLE
VOUT
C
jMATCH-TERMINATE READ
PEND
H
EXA
A,CEND
RISRA

9-134

231309-001

APPLICATIONS
j •••• 11

j

TRANSMIT INTERUPT SERVICE ROUTINE
TISR PROCCESSES TRANSMITTER INTERUPTS
WHEN THE END OF A TRANSMISSION IS
DETECTED THE USER SUPPLIED COMPLETION
ROUTINE IS CALLED AND THEN AN EXIT IS
TAKEN THROUGH VOUT OF VECTOR

j**' ••
42D4
42D7
42DB
42DB
42DD
42DF
42E2
42E3
42E4
42E7
42EB
42E9
42EC
42EF
42FO
42F2
42F3
42F4
42F7
42FA
42FB
42FD
4300
4303

3A3B42
B7
C40443
3E.B1
D3F3
2A3942
2C
2D
C2EC42
24
25
CA7E42
CD3E42
1A
D3F4
04
05
C27E42
217E42
E5
3EOO
2A3942
CD5B42
E9

4304
4306
4309
430B
430E
4310
4313
4314
4311
4319
431C
431F
4321
4323
4324
4327
4329
432C

FE01
CA2443
FE02
CA1443
FE03
CA1C43
C9
3A3742
F604
323142
3A3742
F610
D3F5
C9
3A3742
E6FB
323142
C32143

TISR:

TISRA:

TUTE:

TUTE2:
TUTE3:
TUTE4:
TUTE 1:

LDA
ORA
CNZ
MVI
OUT
LHLD
INR
DCR
JNZ
INR
DCR
JZ
CALL
LDAX
OUT
INR
OCR
JNZ
LXI
PUSH
MVI
LHLD
CALL
PCHL

TCMD
A
TUTE
A,OB1H
OF3H
TCBA
L
L
TISRA
H
H
VOUT
LOADA
D
USDAO
B
B
VOUT
Ii ,·VOUT
H
A,GSTAT
TCBA
CLEAN

CPI
JZ
CPI
JZ
CPI
JZ
RET
LDA
ORI
STA
LDA
ORI
OUT
RET
LDA
ANI
STA
JMP

01
TUTE1
02
TUTE2
03
TUTE3

jGET POTENTIAL COMMAND
jDESIGNATE ON IT
JDO UTILITY COMMAND
jMDS-CLEAR XMIT INTERUPTS
jMDS
jMAKE SURE HAVE VALID CONTROL BLOCK
jGOOD
jNON VALID BLOCK (H,L=O)
jSET UP ADDRESS
jGET DATA FROM BUFFER
jAND OUTPUT IT
jB WAS 00 IF DONE
JNOT DONE-EXIT FROM SERVICE ROUTINE
jSET UP RETURN ADDRESS
jAND PUSH IT INTO THE STACK
jA GETS GOOD STATUS
jPOINT H,L AT COMMAND BLOCK
jCALL CLEANUP ROUTINE
jCALL COMPLETION ROUTINE
jRETURN WILL BE TO VOUT
jRECEIVER OFF
j RECEIV'ER ON
jCLEAR ERRORS

LCMD
04
LCMD
LCMD
10H
USCMD
LCMD
OFBH
LCMD
TUTE4

9-135

231309-001

APPLICATIONS

.*****
I

USART COMMAND BLOCK INTERPRETER
USRUN IS CALLED BY USER WITH THE ADDRESS
OF THE COMMAND BLOCK IN H,L. USRUN EXAMINES
THE BLOCK ANDINTIALIZES THE REQUESTED OPERATION
;

;*****
432F
4330
4332
4335
4337
433A
433c
433F
4340
4341
4342
4344
4346
4348
434A
434C

1A
FE43
CA4043
FE52.
CA5D43
FE57
CA9D43
C9
F3
AF
D3F5
D3F5
D3F5
3E40
D3F5
3E5E

434E
4350
4351
4354
4355
4356
4357
4358
4359
435A
435B
435 C

D3F5
AF
213942
77
23
77
23
77
23
77
FB
c9

435D
4360
4361
4362
4365
4366
43-67
4368
436B
436D
4370
4371
4372
4375
4376

213B42
7E
B7
C26B43
23
7E
B7
CA7743
3EFE
217643
E5
EB
CD5B42
E9
C9

4377
4378
437B
437E
4380
4383

EB
223B42
3A3742
F616
323742
OF

USRUN:

LDAX
CPI
JZ
CPI
JZ
CPI
JZ
RET
UCLEAR: DI
XRA
OUT
OUT
OUT
MVI
OUT
MVI

OUT
XRA
LXI
MOV
INX.
MOV
INX
MOV
INX
MOV
EI
RET

D

'c'
UCLEAR
'R'

UREAD

'w'
UWRITE
A

USCMD
USCMD
USCMD
A, 40H
USCMD
A, 05EH

USCMD
A

H,TCBA
M,A

;GET THE CMD FROM THE BLOCK
;IS IT A CLEAR COMMAND?
;YES GO TO CLEAR ROUTINE
;IS IT ~READ COMMAND?
;YES-OO TO READ ROUTINE
;IS IT A WRITE COMMAND?
;GO TO WRITE ROUTINE
;NOT A GOOD COMMAND-RETURN
;DISABLE INTERUPTS
;CLEAR A
;OUTPUT THREE TIMES TO ENSURE
;THAT THE USART IS IN A KNOWN STATE
;CODE TO RESET USART
;OUTPUT ON CMD CHANNEL
;CE IMPLIES ASYN MODE (X16)
8 DATA BITS
ODD PARITY
1 STOP BIT
;OUTPUT ON CMD CHANNEL
;CLEAR A, SET ZERO
;CLEAR TCBA AND RCBA

H

M,A
H

M,A
H

M,A
;ENABLE INTERUPTS
;AND RETURN TO USER
;

UREAD:

UROUT:

URDB:
URDA:

LXI
MOV
ORA
JNZ
INX
MOV
ORA
JZ
MVI
LXI
PUSH
XCHG
CALL
PCHL
RET
XCHG
SHLD
LDA
ORI
STA
RRC

H,RCBA
A,M

;CHECK READ IDLE

A

UROUT
H

A,M
A

URDA·
A,OFEH
H,lJRDB
H

CLEAN

RCBA
LCMD
16H
LCMD

;READ IS IDLE-PROCEDE
;ALREADY RUNNING-ERROR STATUS
;SET UP RETURN ADDRESS
;PUSH IT INTO STACK
;H GETS COMMAND BLOCK ADDRESS
;CALL CLEANUP ROUTINE
;EFFECTIVELY CALLS ,END ROUTINE
;RETURN TO USER
;H GETS COMMAND BLOCK ADDRESS
;RCBA GETS COMMAND BLOCK ADDRESS
;GET LAST COMMAND
;SET RXE AND DTR AND RESET ERRORS
;AND RETURN TO MEMORY
;SET CARRY EQUAL TO TXE
9-136

231309-001

APPLICATIONS
4384
4387
4389
43BC
438D
438F
4391
4393
4395
4397
4399
439B
439C

D28C43
3E02
323842
07
D3F5
DBF.4
DBF4
3E 82
D3F3
3EF6
D3FC
FB
C9

439D
43AO
43A1
43A2
43A5
43A6
43A7
43AA
43AB
43AE
43B1
43B3
43B6
43B8
43BA
43BC
43BD

213942
7E
B7
C26B43
23
7E
C26B43
EB
223942
3A3742
F6;23
323742
D3F5
3EF6
D3FC
FB
C9

URDC:

JNC
MVI
STA
RLC
OUT
IN
IN
MVI
OUT
MVI
OUT
EI
RET

U\,RITE: LXI
MOV
ORA
JNZ
INX
MOV
JNZ
XCHG
SHLD
LJlA
ORI
STA
OUT
MVI
OUT
EI
RET

URDC
A,2
TCMD
USCMD
USDAI
USDAI
A,82H
OF3H
A,OF6H
OFCH

H,TCBA
A,M
A
UROUT
H
A,M
UROUT
TCBA
LCMD
023H
LCMD
USCMD
A,OF6H
OFCH

jOUTPUT CMD
jCLEAR USART OF LEFT OVER CHARACTERS
jMDS-CLEAR RECEIVE INTERUPT
jMDS
jMDS-ENABLE LEVEL THREE
jMDS
jENABLE INTERUPTS
jRETURN TO USER
jCHECK WRITE IDLE
jBUSY-EXIT
jBUSY-EXIT
jOK-H GETS COt~MAND BLOCK ADDRESS
;TCBA GETS COMMAND BLOCK ADDRESS
jGET LAST COMMAND
;SET RTS,DTR, AND TXEN
MDS-ENABLE LEVEL THREE INTERUPTS
MDS
ENABLE SYSTEM INTERUPTS
AND RETURN

9-137

231309-001

APPLICATIONS

•••••
USER IS A TEST PROGRAM WHICH EXERCISES USRUN
• • • • It

43BE
43CO
43C3
43C6
43C9
43CB
43CE
43CF
43D2
43D5
43D6
43D7
43D8
43DB
43DE
43DF
43EO
43E3
43E4
43E6
43E9
43EB
43EE
43Ef
43F2
43F5
43F8
43FB
43FE
4401
4403
4406
4409
440A
4400
4410
4411
4412
4413
4416
4417
4418
441B
441E
0000

3EC3
321800
216842
221900
3E43
111442
12
CD2F43
=210040
AF
77
2C
C2D 64 3
210041
75
2C
C2DE43
65
2E52
220042
2E57
220A42
6C
220642
221042
110042
CD2F43
110A42
CD2F43
3EFF
32.1 642
3A 1642
B7
C20644
210040
7E
24
BE
C21E44
25
2C
C21044
C3BE43
C7

USER:

COMLP:

COMER:

MVI
STA
LXI
SHLD
MVI
LXI
STAX
CALL
LXI
XRA
MOV
INR
JNZ
LXI
MOV
INR
JNZ
MOV
MVI
SHLD
MVI
SHLD
MOV
SHLD
SHLD
LXI
CALL
LXI
CALL
MVI
STA
LDA
ORA
JNZ
LXI
MOV
INR
CMP
JNZ
DCR
INR
JNZ
JMP
RST

A,OC3H jMDS-SET INTERUPT VECTOR
018H
H,VECTOR
019H
A, 'c'
jSET GENERAL BLOCK TO A 'c'
D,GBLOCK
D
USRUN
H,BUFIN jCLEAR INPUT BUFFER
A
M,A
L
$-2
H,BUF.OUT jINITIALIZE OUTPUT BUFFER
M,L
L
$-2
H,L
jREINTIALIZE CONTROL BLOCKS
L, 'R'
RBLOCK
L, 'w'
TBLOCK
L,H
RCCT
TCCT
D,RBLOCK jSTART READ
USRUN
D,TBLOCK jSTART WRITE
USRUN
A,OFFH jLOOP WAITING COMPLETION
FLAG
JFLAG WILL BE SET BY COMPLETION ROUTINES
FLAG
A
$-4
H,BUFIN JTEST INPUT BUFFER=OUTPUT BUFFER
A,M
H
M
COMER
H
L
COMLP
JGOOD COMPARE-REPEAT TEST
USER
jERROR-RETURN TO MONITOR
0

END

9-138

231309-001

APPLICATIONS
BSTAT
CLEAN
EXCHA
LCMD
RBAD
RCR
RISRB
TBLOC
TCR
TRCT
TUTE3
URDB
USCMD
USRUN
VOUT

OOFF
4"25B
42BE
4237
4202
4217
4299
420A
4227
420E
431C
4376
00F5
432F
427E

BUFIN
COMER
FLAG
LOADA
RBLOC
RCRA
RISRE
TCBA
TCRA
TUTE
TUTE4
URDC
USDAI
USTAT

4000
441E
4216
423E
4200
4208
42B9
4239
4212
4304
4321
43BC
00F4
00F5

BUFOU
COMLP
GBLOC
MTAB
RCBA
RISR
RRCT
TCCT
TISR
TUTE1
UCLEA
UREAD
USDAO
UWRIT

4100
4410
4214
423D
423B
4288
4204
4210
42D4
4324
4340
435D
00F4
439D

9-139

CEND
EXA
GSTAT
PEND
RCCT
RISRA
TBAD
TCMD
TISRA
TUTE2
URDA
UROUT
USER
VECTO

0001
42C1
0000
42CF
4206
42AE
420C
4238
42EC
4314
4377
436B
43BE
4268

231309-001

APPLICATIONS
APPENDIX A
8251 DESIGN HINTS

1. Output of a command to the USART destroys
the integrity of a transmission in progress if
timed incorrectly.
Sending a command into the USART will overwrite any character which is stored in the buffer
waiting for transfer to the parallel-to-serial converter in the device. This can be avoided by
waiting for TxRDY to be asserted before sending a command if transmission is taking place.
Due to the internal structure of the USART, it is
also possible to disturb the transmission if a
command is sent while a SYN character is being
generate,d by the device. (The USART generates
a SYN if the software fails to respond to
TxRDY.) If this occurrence is possible in a system, commands should be transferred only when
a positive-going edge is detected on the TxRDY
line.

characters have been detected and the next character has been assembled and is ready to be read.
3. Loss of CTS or dropping TxEnable will immediately clamp the serial output line.
TxEnable and RTS should remain asserted until
the transmission'is complete. Note that this implies tlIat not only has the USART completed
the transfer of all bits of the last character, but
also that they have cleared the modem. A delay
of 1 msec following a proper occurrence of
TxEmpty is usually sufficient (see item 4). An
additional problem can occur in the synchronous mode because the loss of TxEnable clamps
the data in at a SPACE instead of the normal
MARK. This problem, which does not occur in
the asynchronous mode, can be corrected by an
external gate combining RTS and the serial output data.

2. RxE only acts as a mask to RxRDY; it does not
cohtroUhe operation of the receiver.
When the receiver is enabled, it is possible for it
to already contain one or two characters. These
characters should be read and discarded when
the RxE bit is first set. Because of these extrane.ous characters the proper sequence for gaining
synchronization is as follows:
1. Disable interrupts
2. Issue a command to enter hunt mode, clear
errors, and enable the receiver (EH,ER,RxE=

4. Extraneous transitions can occur on TxEmpty
while data (including USART generated SYNs)
is transferred to the parallel-to-serial converter.
This situation can be avoided by ensuring that
TxEmpty occurs during several consecutive
status reads before assuming that the transmitter
is truly in the empty state.
S. A BREAK (Le., long space) detected by the
receiver results in a string of characters which
have framing errors.
If reception is to be continued after a BREAK,
care must be taken to ensure that valid data is
being received; special care must be taken with
the last character perceived during a BREAK,
since its value, including any framing error associated with it, is indeterminate.

1)

3. Read USART data (it is not necessary to
check status)
4. Enable interrupts
The first RxRDY that occurs after the above
sequence will indicate that the SYN character or

9-140

231309-001

8251 PROGRAMMABLE COMMUNICATION INTERFACE

9-141

231309-001

APPLICATION

Ap·36

NOTE

March 1978

I@

Inlel Corporation, 1978

9-142

Order Number: 231311-001

Using the 8273
SOLC/HOLC
Protocol Controller

Contents
INTRODUCTION
SDLC/HDLC OVERVIEW
BASIC 8273 OPERATION
HARDWARE ASPECTS OF THE 8273
CPU Interface
Modem Interface

SOFTWARE ASPECTS OF THE 8273
Command Phase Software
Execution Phase Software
Result Phase Software

8273 COMMAND DESCRIPTION
Initialization / Configuration Commands
Operating Mode Register
Serial I/O Mode Register
Data Transfer Mode Register
One Bit Delay Register
Receive Commands
General Receive
Selective Receive
Selective Loop Receive
Receive Disable
Transmit Commands
Transmit Frame
Loop Transmit
Transmit Transparent
Abort Commands
Reset Commands
Modem Control Commands

HDLC CONSIDERATIONS
LOOP CONFIGURATIONS
APPLICATION EXAMPLE
CONCLUSION
APPENDIX A

9-143

231311-001

APPLICATIONS
INTRODUCTION

The Intel 8273 is a Oata Communications Protocol Controller designed for use in systems utilizing either SOLC
or HOLC (Synchronous or High-Level Oata Link Control)
protocols_ In addition to the usual features such as full
duplex operation, automatic Frame Check' Sequence
generation and checking, automatic zero bit insertion
and deletion, and TIL compatibility found on other
single component SOLC controllers; the 8273 features a
frame level command structure, a digital phase locked
loop, SOLC loop operation, and diagnostics_
The frame level command structure Is made possible by
the 8273's unique internal dual processor architecture_
A high-speed bit processor handles the serial data
manfpulatlons and character recognition_ A byte processor implements the frame level commands_ These
dual processors allow the 8273 to control the necessary
byte-by-byte operation of the data channel with a
minimum of CPU (Central Processing Unit) intervention_
For the user this means the CPU has time to take on
additional tasks. The digital phase locked loop (OPLL)
provides a rneans of clock recovery from the received
data stream on-chip. This feature, along with the frame
level commands, makes SOLC loop operation extremely
simple and flexible. Oiagnostics il"! the form of both data
and clock loopback are available to simplify ,board
debug and link testing. The 8273 is a dedi,cated function
peripheral in the MCS-80/85 Microcomputer family and
as such, it interfaces to the 8080/8085 system with a
minimum of external hardware.
This application note explaJns the 8273 as ii component
and shows its use in a generalized loop configuration
and a typical 8085 system. The 8085 system was used to
verify the SOLC operation of the 8273 on an actual IBM
SOLC data communications link.
The first section of this application note presents an
overview of the SOLC/HOLC protocols. It Is fairly tutorial
in nature and may be skipped by the more knowledgeable reader. The second section describes the 8273 from
a functional standpoint with explanation of the block
diagram. The software aspects of the 8273, including
command examples, are discussed In the third section.
The fourth and fifth sections discuss a loop SOLC configuration and the 8085 system respectively.

Aside from supporting a large number of configurations,
SOLC offers the potential of a 2 x increase in throughput over the presently most prevalent protocol: BI-Sync.
This performance Increase Is prlmarilyduetotwocharacteristlcs of SOLC: full duplex operation and the implied
acknowledgement of transferred information. The performance increase due to full duplex operation Is fairly
obvious since, In SOLC, both stations can communicate
simultaneously. Bi-Sync supports only half-duplex (twoway alternate) communication. The increase from implied acknowledgement arises from the fact that a station using SOLC may acknowledge previn1lsly received
Information while transmitting different Information. Up
to 7 messages may be outstanding before an acknowledgement is required. These messages may be acknowledged as a block rather than singly. In BI-Sync, acknowledgements are unique messages that may not be
Included with messages containing Information and
each information message requires a separate acknowledgement. Thus the line efficiency of SOLC is superior
to BI-Sync. On a higher level, the potential of a 2 x
Increase in performance means lower cost per unit of
information transferred. Notice that the Increase is not
due to higher data link speeds (SOLC is actually speed
Independent), but simply through better line utilization.
Getting down to the more salient characteristics of
SOLC; the basic unit of information on an SOLC link is
that of the frame. The frame format is shown in Figure 1.
Five fields comprise each frame: flag, address, control,
information, and frame check sequence. The flag fields
(F) form the boundary of the frame and all other fields
are positionally related to one of the two flags. All
frames start with an opening flag and end with a closing
flag. Flags are used for frame synchronization. They'
also may serve as time-fill characters between frames.
(There are no intraframe time-fill characters in SOLC as
there are in Bi-Sync.) The opening flag serves as a reference point for the addrelis (A) and control (C) fields. The
frame check sequence (FCS) Is referenced from the
closing flag. All flags have the binary configuration
01111110 (7EH).
SOLC Is a bit-oriented 'protocol, that is, the receiving
station must be able to recognize a flag (or any other
special character) at any time, not just on an 8-bit
boundary. This, of course, implies that a frame may be
N-bits in length. (The vast majority of applications tend
to use frames which are multiples of 8 bits long,
however.)

SDLC/HDLC OVERVIEW

, SOLC is a protocol for managing the flow of information
on a data communications link. In other words, SOLC
can be thought of as an envelope - addressed"
stamped, and containing an s.a.s.e. - in which information is transferred from location to location on a data
communications link. (Please note that while SOLC is
discussed specifically, all comments also apply to
HOLC except where noted.) The link may be either pointto-point or multi-point, with the point-to-point configuration being either switched or nonswitched. The information flow may use either full or half duplex exchanges.
With this many configurations supported, it is difficult
to find a synchronous data communications application
where SOLC would not be appropriate.

9-144

FRAME
CHECK
OPENING

FLAG

ADDRESS
FIELD If'I

CONTROL
FIELD te)

Figure 1.

INFORMATION SEQUENCE
FIELD (1)
(FCS)

CLOSING
FLAG

sDLe Freme Format
231311-001

APPLICATIONS
The fact that the flag has a unique binary pattern would
seem to limit the contents of the frame since a flag pattern might inadvertently occur within the frame. This
would cause the receiver to think the closing flag was
received, invalidating the frame. SOLC handles this
situation through a technique called zero bit insertion.
This techniques specifies that within a frame a binary 0
be inserted by the transmitter after any succession of
five contiguous binary 1s. Thus, no pattern of 01111110
is ever transmitted by chance. On the receiving end,
after the opening flag is detected, the receiver removes
any 0 following 5 consecutive 1s. The inserted and
deleted Os are not counted for error determination.
Before discussing the address field, an explanation of
the roles of an SOLC station is in order. SOLC specifies
two types of stations: primary and secondary. The
primary is the control station for the data link and thus
has responsibility of the overall network. There is only
one predetermined primary station, all other stations on
the link assume the secondary station role. In general, a
secondary station speaks only when spoken to. In other
words, the primary polls the secondaries for responses.
In order to specify a specific secondary, each secondary
is assigned a unique a-bit address. It Is this address that
is used in the frame's address field.
When the primary transmits a frame to a specific secondary, the address field contains the secondary's address. When responding, the secondary uses its own
address in the address field. The primary is never iden·
tified. This ensures that the primary knows which of
many secondaries is responding since the primary may
have many messages outstanding at various secondary
stations. In addition to the specific secondary address,
an address common to all secondaries may be used for
various purposes. (An all1s address field is usually used
for this "All Parties" address.) Even though the primary
may· use this common address, the secondaries are ex·
pected to respond with their .unique address. The
address field is always the first a bits following the
opening flag.
The a bits following the address field form the control
field. The control field embodies the link-level control of
SOLC. A detailed explanation of the commands and
responses contained in this field is beyond the scope of
this application Mte. Suffice it to say that it is in the
control field that the implied acknowledgement is carried out through the use of frame sequence numbers.
None of the currently available SOLC single chip controllers utilize the control field. They simply pass it to
the processor for analysis. Readers wishing a more
detailed explanation of the control field, or of SOLC in
general, should consult the IBM documents referenced
on the front page overleaf.
In some types of frames, an information field follows
the control field. Frames used strictly for link management mayor may not contain one. When an information
field is used, it is unrestricted in both content and
length. This code transparency is made possible
because of the zero bit Insertion mentioned earlier and
the bit-oriented nature of SOLC. Even main memory core
dumps may be transmitted because of this capability.
This feature is unique to bit-oriented protocols. Like the

control field, the information field is not interpreted by
the SOLC device; it is merely transferred to and from
memory to be operated on and interpreted by the
processor.
The final field is the frame check sequence (FCS). The
FCS is the 16 bits immediately preceding the closing
flag. This 16-bit field is used for error detection through
a Cyclic Redundancy Checkword (CRC). The 16-bit
transmitted CRC is the complement of the remainder
obtained when the A, C, and I fields are "divided" by a
generating polynomial. The receiver accumulates the A,
C, and I field.s and also the FCS into its internal CRC
register. At the closing flag, this register contains one
particular number for an error-free reception. If this
number is not obtained, the frame was received in error
and should be discarded. OiscardinQ the frame causes
the station to not update its frame sequence numbering.
This results in a retransmission after the station sends
an acknowledgement from previous frames. [Unlike all
other fields, the FCS is transmitted MSB (MostSignificant Bit) first. The A, C, and I fields are transmitted LSB
(Least Significant Bit) first.) The details of how the FCS
is generated and checked is beyond the scope of this
application note and since all single component SOLC
controllers handle this function automatically, it is
usually sufficient to know only thatari error has or has
not occurred. The IBM documents contain more detailed
information for those readers desiring it.
The closing flag terminates the frame. When the closing
flag is received, ttie receiver knows that the preceding
16 bits constitute the FCS and that any bits between the
control field and the FCS constitute the information
field.
SOLC does not support an interframe time-fill character
such as the SYN character in Bi-Sync.1f an unusual condition occurs while transmitting, such as data is not
available in time from memory or CTS (Clear-to-Send) is
lost from the modem, the transmitter .aborts the frame
by sending an Abort character to notify therec.eiver to
invalidate the frame. The Abort character consists of
eight contiguous 1s sent without zero bit insertion. Intraframe time-fill consists of either flags, Abort characters, or any combination o.f the two.
While the Abort character protects the receiver from
transmitted errors, errors introduced by the transmission medium are discovered at the receiver through the
FCS check and a check for invalid frames. Invalid
frames are those whi.ch are not bounded by flags or are
too .short, that is, less than 32 bits between flags. All invalid frames are ignored by the receiver.
Although SOLC is a synchronous protocol, it provides
an optional feature that allows its use on basically asynchronous data links NRZI (Non-Return-to-ZeroInverted) coding. NRZI coding specifies that the signal
condition does not change for transmitting a binary 1,
while a binary 0 causes a change of state. Figure 2 illustrates NRZI coding compared to the normal NRZ. NRZI
coding guarantees that an active line will have a transition at least every 5-bit times; long strings of zeroes
cause a transition every bit time, while. long strings of 1S
are broken up by zero bit insertion. Since asynchronous

9-145

231311-001

APPLICATIONS
operation requires that the receiver sampling clock be
derived from the received. data, NRZI encoding plus zero
bit insertion make the design of clock recovery circuitry
easier.
All of the previous discussion has applied to SOLe on
either point-to-point or multi-point data networks, SOLe
(but not HOLe) also includes specification for a loop
configuration. Figure 3 compares these three configurations. IBM uses this loop configuration In its 3650 Retail
Store System. It consists of a single loop controller station with one or more down-loop secondary stations.
Communications on a loop rely on the secondary stations repeating a received message down loop with.a
delay of one bit time. The reason for the one bit delay
will be evident shortly.

DATA

1

BIT SAMPLE

j

o

IIJ I

0

J J

NRZ

NRZI

I

Loop operation defines a new special character:· the
EOP (End-of-PolI) character which consists of a 0 followed by 7 contiguous, non-zero bit inserted, ones. After
the loop controller transmits a message, It idles the line
(sends all 1s). The final zero of the closing flag plus the
first 7 1s of the Idle form an EOP character.; While
repeating; the secondaries monitor their incoming line
for an EOP character. When an EOP is detected, the
secondary checks to see if It has a message to transmit.
If it does, it changes the seventh 1 to a 0 (the one bit
delay allows time for thiS) and repeats the modified EOP
(now alias flag). After this flag is transmitted, the secondary terminates Its repeater function and inserts Its
message (with multiple preceding flags if necessary).
After the closing flag, the secondary resumes its one bit
delay repeater function. Notice that the final zero of the
secondary's closing flag plus the repeated 1s from the
controller form an EOP for the next down-loop secondary, allowing it to insert a message if it desires.

0

J J

One might wonder if the secondary missed any messages from the controller while it was Inserting its own
message. It does not. Loop operation is basically halfduplex. The ·controller walts until it receives an EOP
before it transmits Its next message. The controller's
reception of the EOP signifies that the original message
has propagated around the loop followed by any messages inserted by the secondaries. Notice that secondaries cannot communicate with one another directly, all
secondary-to-secondary communication takes place by
way of the controller.

POINT·To-POINT

LOOP

MULTI-POINT

Flgul8 3. Network Conllgul8tlons

9-146

231311-001

APPLICATIONS
Loop protocol does not utilize the normal Abort character. Instead, an abort is accomplished by simply transmitting a flag character. Oown loop, the receiver sees
the abort as a frame which Is either too short (if the
abort occurred early In the frame) or one with an FCS
error. Either results in a discarded frame. For more
details on loop operation, please refer to the IBM
documents referenced earlier.

BASIC 8273 OPERATION
It will be helpful for the following discussions to have
some idea of the basic operation of the 8273. Each
operation, whether it is a frame transmission, reception
or port read, etc.,. Is comprised of three phases: the
Command, Execution, and Result phases. Figure 5
shows the sequence of these phases. As an illustration
of this sequence, let us look at the transmit operation.

Another protocol very similar to SOLC which the 8273
supports is HOLC (High-Level Oata Link Control). There
are only three basic differences between the two: HOLC
offers extended address and control fields, and the
HLOC Abort character Is 7 contlguous1s as opposed to
SOLC's 8 conilguous 1s.
Extended addressing, beyond the 256 unique addresses
possible with SOLC, is provided by using the address
field's least significant bit as the extended address
modifier. The receiver examines this bit to determine if
the octet should be interpreted as the final address
octet. As long as the bit is 0, the octet that contains It Is
considered an extended address. The first time the bit Is
a 1, the receiver interprets that octet as the final address
octet. Thus the address field may be extended to any
number of octets. Extended addressing is illustrated in
Figure 4a.
A similar technique is used to extend the control field
although the extension is limited to only one extra control octet. Figure 4b illustrates control field extension.
Those readers not yet asleep may have noticed the similarity between the SOLC loop EOP character (a 0 followed by 7 1s) and the HOLC Abort (7 1s). This possible incompatibility is neatly handled by the HOLC protocol
not specifying a loop configuration.
This completes our brief discussion of the SOLC/HOLC
protocols. Now let us turn to the 8273 In particular and
discuss its hardware aspects through an explanation of
the block diagram and generalized system schematics.

FIRST BIT TRANSMITTED (LSB FIRST)
A. HOLe ADDRESS FIELD EXTENSION

Figure 4.

C

FLAG

When the CPU decides it is time to transmit a frame, the
Command phase is entered by the CPU Issuing a Transmil' Frame command to the 8273. It is not sufficient to
just instruct the 8273 to transmit. The frame level command structure sometimes requires more Information
such as frame length and address and control field content. Once this additional information is supplied, the
Command phase is complete and the Execution phase
is entered. It is during the Execution phase that the
actual operation, In this case a frame transmission,
takes place. The 8273 transmits the opening flag, A and
C fields, the specified number of I field bytes, Inserts
the FCS, and closes with the closing flag. Once the closing flag is transmitted, the 8273 leaves the Execution
phase and begins the Result phase. Ourlng the Result
phase the 8273 notifies the CPU of the outcome of the
command by supplying interrupt results. In this case,
the results would be either that the frame Is complete or
that some error condition causes the transmission to be
aborted. Once the CPU reads all of the results (there is
only one for the Transmit Frame command), the Result
phase and consequently the operation, is complete.
Now that we have a general feeling for the operation of
the 8273, let us discuss the 8273 In detail.

EXTENSION BIT 11 MAX)

I ltc, I
A

Figure 5. 8273 Operational Phase.

C2

1'1.. 1'2 I Fes,l FCS21

FLAG

HARDWARE ASPECTS OF THE 8273

8. HDLe CONTROL FIELD EXTENSION

Figure 4b

The 8273 block diagram is shown in Figure 6. It consists
of two major Interfaces: the CPU module Interface and
the modem interface. Let's discuss each Interface
separately.

9-147

231311-001

APPLICATIONS
, . . - - - - ' - - - - - - F L A G DETECT

,..-------00

....------CTS

REGISTERS

....-----iiTs

Txl/R

COMMAND

RxUR

PARAMETER
STATUS'

TEST MODE

RESULT

D80_7

TxDACK

------I
---.01

RxDRO

-~----1

bDRO

1O+----TiC
DATA
TIMING
LOGIC

1----.TxD

10----'- RxC
1-----RxD

' - - - - . , - - - - DPLL
~------32XCLK

CS---.01
Ao----I
Al-----I

RESET----..J
OCLK-----..J
TxlNT _ _ _ _ _----'
RxlNT _ _ _ _ _ _---'
. CPU MODULE INTERFACE

MODEM INTERFACE

figure 6. 8273 Block Dlagrem .

CPU Interface

Command - 8273 operations are initiated by writing
the appropriate command byte Into this register.

The CPU Interface consists of four major blocks: Control/Read/Write logic (C/RIW), internal registers, data
transfer logic, and data bus Duffers.

Parameter - Many commands require more informa·
tion than found in the command Itself. This addi·
tional Information is provided by way of the paramo
eter register.
.

The CPU module utilizes the C/RIW logic to issue commands to the 8273. Once the 8273 receives command
and executes it, it returns the results (good/bad completion) of the command by way of the C/RIW logic. The
C/R/W logic is supported by seven registers which are
addressed via the Ao, AI, RD, and WR signals,ln addition to CS. The Ao and A1 signals are generally derived
from the two low order bits of the CPU module address
bus while RD and WR are the normal I/O Read and Write
signals found on the system control bus. Figure 7
shows the address of each register using the C/RIW
logic. The function of each register is defined as
follows:

a

ADDRESS INPUTS
AO

CS.RD

CS.WR

0
0

0

1
1

0

STATUS
RESULT
TxllR
RxllR

COMMAND
PARAMETER
TEST MODE

1

Transmit Interrupt Result (TxIlR) Results of
transmit operations are passed to the CPU in this
register.'
.
Receiver Interrupt Result (RxIlR) - Receive operation results are passed to the CPU via this register.
Status - The general status of the 8273 Is provided
in this register. The Status register supplies the
handshaking necessary during various phases of the
8273 operation.
Test Mode - This register provides a software reset
function for the 8273.

CONTROL INPUTS

A1

1

Immediate Result (Result) - The completion .information (results) for commands which execute im·
mediately are provided In this register.

figure 7. 8273 Reglstar Selection

-

The commands, parameters, and bit definition of these
registers are discussed in the following software sec·
tion. Notice that there are not specific transmit or
receive data registers. This feature is explained in the
data transfer logic discussion:

9-148

231311-001

APPLICATIONS
The final elements of the C/R/W logic are the interrupt
lines (RxINT and TxINT). These lines notify the CPU
module that either the transmitter or the receiver requires service; I.e., results should be read from the
appropriate interrupt result register or a data transfer is
required. The interrupt request remains active until all
the associated interrupt results have been read or the
data transfer is performed. Though using the interrupt
lines relieves the CPU module of the task of polling the
8273 to check if service is needed, the state of each
Interrupt line is reflected by a bit in the Status register
and non-Interrupt driven operation is possible by examIng the contents of these bits periodically.
The 8273 supports two Independent data interfaces
through the data transfer logic; receive data and transmit data. These interfaces are programmable for either
DMA or non-DMA data transfers. While the choice of the
configuration is up to the system designer, it is based
on the intended maximum data rate of the communications channel. Figure 8 illustrates the transfer rate of
data bytes that are acquired by the 8273 based on link
data rate. Full-duplex data rates above 9600 baud usually require DMA. Slower speeds mayor may not require
DMA depending on the task load and Interrupt response
time of the processor.
Figure 9 shows the 8273 in a typical DMA environment.
Notice that a separate DMA controller, in this case the
Intel 8257, is required. The DMA controller supplies the
timing and addresses for the data transfers while the
8273 manages the requesti ng of transfers and the actual
counting of the data block lengths. In this case,
elements of the data transfer interface are:
TxDRQ: Transmit DMA Request - Asserted by the
8273, this line requests a DMA transfer from memory
to the 8273 for transmit.
TxDACK: Transmit DMA Acknowledge - Returned
by the 8257 in response to TxDRQ, this line notifies
the 8273 that a request has been granted, and provides access to the transmitter data register.

the receiver alleviates the need for the normal transmit
and receive data registers addressed by a combination
of address lines, CS, and WR or RD. Competitive
devices that do not have this "hard select" feature require the use of an external multiplexer to supply the
correct inputs for register selection during DMA. (Do not
forget that the SDLCcontroller sees both the addresses
and control signals supplied by the DMA controller during DMA cycles.) Let us look at typical frame transmit
and frame receive sequences to better see how the 8273
truly manages the DMA data transfer.
Before a frame can be transmitted, the DMA controller is
supplied, by the CPU, the starting address for the
desired information field. The 8273 is then commanded
to transmit a frame. (Just how this is done is covered
later during our software discussion.) After the command, but before transmission begins, the 8273 needs a
little more information (parameters). Four parameters
are required for the transmit frame command: the address field byte, the control field byte, and two bytes
which are the least significant and most significant
bytes of the information field byte length. Once all four
parameters are loaded, the 8273 makes RTS (Request-toSend) active and waits for CTS (Clear·to-Send) to go active. Once CTS is active, the 8273 starts the frame transmission. While the 8273 is transmitting the opening flag,
address field, and control field; it starts making transmitter DMA requests. These requests continue at character (byte) boundaries until the pre-loaded number of
bytes of information field have been transmitted. At this
point the requests stop, the FCS and closing flag are
transmitted, and the TxlNT line is raised, signaling the
CPU that the frame'transmission is complete. Notice
that after the initial command and parameter loading,
absolutely no CPU intervention was required (since
DMA is used for data transfers) until the entire frame
was transmitted. Now let's look at a frame reception.
BOrns

RxDRQ: Receiver DMA Request - Asserted by the
8273, it requests a DMA transfer from the 8273 to
memory for a receive operation.

seclbyle
800

TxDACK: Receiver DMA Acknowledge - Returned by
the 8257, it notifies the 8273 that a receive DMA cycle
has been granted, and provides access to the
receiver data register.

~s

SAUD RATE (bps)

RD: Read - Supplied by the 8257 to Indicate data is
to be read from the 8273 and placed in memory.

Figure 8. Byte Trans'er Rate vs Baud Rate

WR: Write - Supplied by the 8257 to indicate data is
to be written to the 8273 from memory.

To request a DMA transfer the 8273 raises the appropriate DMA request line; let us assume it is a transmitter
request (TxDRQ). Once the 8257 obtai ns control of the
system bus by way of its HOLD and HLDA (hold
acknowledge) lines, it notifies the 8273 that TxDRQ has
been granted by returning TxDACK and WR. The
TxDACK and WR signals transfer data to the 8273 for a
transmit, independent of the 8273 chip select pin (CS). A
similar sequence of events occurs for receiver requests.
This "hard select" of data into the transmitter or out of

AD

WR

lOR
lOW

r-'BUS

~ ~DATABUS
Figure 9. OMA, Interrupi·Orlven System

9-149

231311-001

APPLICATIONS
The receiver operation Is very similar. Like the Initial
transmit sequence, the DMA controller Is loaded with a
starting address for a receiver data buffer and the 8273
Is commanded to receive. Unlike the transmitter, there
are two different receive commands: General Receive,
where all received frames are transferred to memory,
and Seler.live Receive, where only frames having an ad·
dress field matching one of two preprogrammec( 8273
address fields are transferred to memory. Let's assume
for now that we want to general receive. After the
receive command, two parameters are required before
the receiver becomes active: the least significant and
most significant bytes of the receiver buffer length.
Once these bytes are loaded, the receiver is active and
the CPU may return to other tasks. The next frame
appearing at the receiver input is transferred to memory
using receiver DMA requests. When the closing flag Is
received, the 8273 checks the FCS and raises its RxlNT
line. The CPU can then read the results which indicate if
the frame was error·free or not. (If the received frame
had been longer than the pre-loaded buffer length, the
CPU would have been notified of tha.t occurrence earlier
with areceiver error interrupt. The command description
section contains a complete list of error conditions.)
Like the transmit example, after the initial command,
the CPU is free for other tasks until a frame is com·
pletely received. These examples have illustrated the
8273's management of both the receiver and transmitter
DMA channels.
It is possible to use the DMA data transfer interface in a
non·DMA interrupt·driven environment. In this case, 4 in·
terrupt levels are used: one each for TxlNT and RxlNT,
and one each for TxDRO and RxDRO. This configuration
is shown in Figure 10. This configuration offers the
advantages that no DMA controller is required and data
requests are still separated from result (completion) reo
quests. The disadvantages of the configuration are that
4 interrupt levels are required and that the CPU must ac·
tually supply the data transfers. This, of course, reduces
the maximum data rate compared to the configuration
based strictly on DMA. This system could use an Intel
8259 8-level Priority Interrupt Controller to supply avec·
tored CALL (subroutine) address based on requests on
its inputs. The 8273 transmitter and receiver make data
'requests by raising the respective DRO line. The CPU is
interrupted by the 8259 and vectored to a data transfer
routine. This routine either writes (for transmit) or reads
(for receive) the 8273 using the respective TxDACK or
RxDACK line. As in the case above, the DACK lines
serve as "hard" chip selects into and out of the 8273.
(TxDACK + WR writes data into the 8273 for transmit.
RxDACK + RD reads data from the 8273 for receive.)
The CPU is notified of operation completion and results
by way of TxlNT and RxlNT lines. Using the 8273, and
the 8259, in this way, provides a very effective, yet simple, interrupt·driven interface.
Figure 11 illustrates a system very similar to that
described above. This system utilizes the 8273 in a non·
DMA data transfer mode as opposed to the two DMA ap·
proaches shown in Figures 9 and 10. In the non·DMA
case, data transfer requests are made on the TxlNT and
RxlNT lines. The DRO lines are not used. Data transfer
requests are separated from result requests by a bit in
9-150

the Status register. Thus, In response to an interrupt,
the CPU reads the Status register and branches to either
a result or a data transfer routine based on the status of
one bit. As before, data transfers are made via using the
DACK lines as chip selects to the transmitter and
receiver data registers.

WR

01-00

~ ~DATABUS
Figure 10. Interrupt·Based DMA System

lOR
RD

8273
lOW

I-~
BUS

WR

07-00

~ ~DATA.US
Figure 11. Non·DMA Interrupt·Drlven System

Figure 12 illustrates the simplest system of all. This
system utilizes polling for all data transfers and results.
Since the interrupt pins are reflected in bits in the
Status register, the software can read the Status
register periodically looking for one of these to be set. If
it finds an INT bit set, the appropriate Result Available
bit is examined to determine if the "interrupt" is a data
transfer or completion result. If a data transfer is called
for, the DACK line is used to enter or read the data from
the 8273. If the interrupt is a completion result, the appropriate result register is read to determine the goodl
bad completion of the operation.
The actual selection of either DMA ornon·DMA modes
is controlled by a command Issued during Initialization.
This command is covered in detail during the software
discussion.
231311-001

APPLICATIONS
The final block of the CPU module Interface Is the Data
Bus Buffer. This block supplies the trl·state, bldlrec·
tlonal data bus Interface to allow communication to and
.
from the 8273.

reset. (All commands mentioned In this section are
covered In detail later.).

Modem Interface

Elements of the serial data logic section are the data
pins, TxD (transmit data output) and RxD (receive data
Input), and the respective data clocks, TXC and RxC. The
transmit and receive data Is synchronized by the TxC
and RxC clocks. Figure 15 shows the timing for these
signals. The leading edge (negative transition) of TxC
generates new transmit data and the trailing edge
(positive transition) of RxC Is used to capture the
receive data.

As the name implies, the modem Interface Is the modem
side of the 8273. It consists of two major blocks: the
modem control block and the serial data timing block.
The modem control block provides both dedicated and
user·defined modem control functions. All signals sup·
ported by this interface are active low so that EIA
inverting drivers (MC1488) and inverting receivers
(MC1489) may be used to interface to standard modems.
Port A is a modem control input port. Its representation
on the data bus is shown in Figure 13. Bits Do and 0,
have dedicated functions. Do reflects the logical state of
the CTS (Clear·to·Send) pin. [If CTS Is active (low), Do is a
1.1 This signal is used to condition the start of a trans·
mission. The· 8273 waits until CTS is active before It
starts transmitting a frame. While transmitting, if CTS
goes inactive, the frame is aborted and the CPU is inter·
rupted. When the CPU reads the interrupt result, a CTS
failure is indicated.
0 1 reflects the logical state of the CD (Carrier Detect)
pin. CD is used to condition the start of a frame recep·
tion. CD must be active in time for a frame's address
field. If CD is lost (goes inactive) while receiving a frame,
an interrupt is generated with a CD failure result. CD
may go inactive between frames.

The final block to be covered Is the serial data timing
block. This block contains two sections: the serial data
logic and the digital phase locked loop (DPLL).

It is possible to reconfigure this section under program
control to perform diagnostic functions; both data and
clock loopback are available. In data loopback mode, the
TxD pin is Internally routed to the RxD pin. This allows
simple board checkout since the CPU can send an SDLC
message to itself. (Note that transmitted data will still
appear on the TxD pin.)

NC

Ne

NC

_CONTROL

'OR

lOW
WR

07-00

lk1 ~OATA

Port B is a modem control output port. Its data bus
representation Is shown in Figure 14. As in Port A, the
bit values represent the logical condition of the pins. Do
and 05 are dedicated function outputs. Do represents
the Ri'S (Request·to·Send) pin. RTS is normally used to
notify the modem that the 8273 wishes to transmit. This
function is handled automatically by the 8273. If RTS Is
inactive (pin is high) when the 8273 is commanded to
transmit, the 8273 makes It active and then waits for
CTS before transmitting the frame. One byte time after
the end of the frame, the 8273 returns RTS to its Inactive
state. However, if RTS was active when a transmit com·
mand is issued, the 8273 leaves it active when the frame
is complete.

Bits 0 1 thru 0 4 provide four user·defined outputs. Pins
PB 1 thru. PB 4 reflect the logical state of these bits. The
8273 does not interrogate or manipulate these bits. De
and 0 7 are not used. In addition to being able to output
to Port B, Port B may be read using a Read Port B com·
mand. All Modem control output pins are forced high on
9-151

BUS

8273

Bits O2 thru 0 4 reflect the logical state of the PA2 thru
PA 4 pins respectively. These inputs are user defined.
The 8273 does not interrogate or manipulate these bits.
Bits Os, De,and 07 are not used and each is read as a 1
for a Read Port A command.

Bit 05 reflects t~e state of the Flag Detect pin. This pin
is activated whenever an active receiver sees a flag
character. This function is useful to activate a timer for
line activity timeout purposes.

Ne

BUS

Figure 12. Polled Syllem

Figure 13. Port A (Input) Bit Dellnltlon

07

De

Os

04

03

02

01

DO

I~

... ,, I

RTS - REQUEST TO SEND
PBz

.B3

USER· DEFINED OUTPUTS

FLAG DETECT

Figure 14. Port B (Output) Bit Dellnltlon

231311-001

APPLICATIONS
When data loopback is utilized, the receiver may' be
presented Incorrect sample timing (RxC) by the external
circuitry. Clock loopback overcomes this problem by
allowing the internal routing 9f TxC and RxC. Thus the
same clock used to transmit the data Is used to receive
it. Examination of Figure 15 shows that this method ensures bit synchrpnlsm. The final element of the serial
data logic is the Digital Phase locked loop.

DJ5[[ pulse B. The distance from B fo the next pu'lse C Is
Influenced according to which quadrant (A1' B1, B2 , or
A2) the data edge falls In. (Each quadrant represents 8
32 x ClK times.) For example, If the edge Is detected in
quadrant A1, it Is apparent that pulse B was too close to
the data edge and the time to the next pulse must be
shortened. The adjustment for quadrant A1 1s speCified
as - 2. Thus, the ,next DPll pulse, pulse C, Is positioned 32 - 2 or 30 32 x ClK pulses following bj5[[
pulse B: This adjustment moves pulse C closer to the
nominal bit center of the next received data cell. A data
edge occurring In quadrant B2 would have caused the
adjustment to be small, namely 32 + 1 or 33 32 x ClK
pulses. Using this technique, 1he DJ5[[ pulse converges
to the nominal bit center within 12 data tranSitions,
worse case - 4-bit times adjusting through quadrant A1
or A2 and 8-blt times adjusting through B1 or B2'

The DPll provides a means of clock recovery from the
received data stream. This feature allows the 8273 to .Interface withou~ external synchronizing logic to low cost
asynchronous modems (modems which do not supply
clocks). It. also makes the problem of. cloc.k timing in
loop configurations trivial.
To use the DPll, a clock at 32 times the required baud
rate must be supplied to the 32 x ClK pin. This clock
provides the Interval that the DPll samples the received
data. The DPll uses the 32 x clock' and the received
data to generate a pulse at the DPll output pin. This
DPll pulse is. positioned at the nominal ,center of the
received data bit cell. Thus the .DPll output may be
wired to RxC and/or TxC to supply the data timing. The
exact position of the pulse Is varied depending on the
line noise and bit distortion of the received data. The ad·
justment of the DPll position is determined according
to the rules outlined In Figure 16.
Adjustments to the sample phase of DPll with respect
to the received data Is made In discrete Increments.
Referring to Figure 16,following the' occurrence of
DPll pulse A, the DPll counts 32 x elK pulses and ex·
amines the. received data for a data edge. Should no
edge be detected in 32 pulses, the DPll positions the
next DPll pulse (B) at 32 clock pulses from pulse A.
Since no new phase information is contained In the data
stream, the sample phase is assumed to be at nominal
1 x baud rate. Now assume a data edge occurs after

Figura 15. TransmlURecelva TIming , .

1 BIT TIME

RxD

32XCLK

x

x

:x:

~.,.'.""""

NO TRANSITION

lflJlfU1Jlf...

""

..

~

2 4 6 8 10 12 14 16 18 20 22 24 28 28 30 32
32 CLOCKS

DPLL
A

B

I
I
I'
1
1
1
1
1
1
1

I'
QUADRANT 1
ADJUSTMENT 1

30 CLOCKS
I

1
1
1

I

I

I

33 CLOCKS

1
1
1
1

32 CLOCKS

I
1
1

I
1

'I
1
A1
-2 1

B1
-1

1
1
1
1

I

FAL

1

I

I

I

1
B2
+1

I.
1

' A2
+2

I
I

Figura 1.6. D"LL Phase Adjustments

9-152

231311-001

APPLICATIONS
to the CPU. Due to the Internal processor architecture of
the 8273, this CPU-8273 communication Is basically a
form of Interprocessor communication. Such communication usually requires a form of protocol of its own.
This protocol Is Implemented through use of handshaking supplied in the 8273 Status register. The bit definition .of this register Is shown in Figure 18.

When the receive data stream goes Idle after 15 ones,
DPLL pulses are generated at 32 pulse Intervals of the
32x CLK. This feature allows the DPLL pulses to be
used as both transmitter and receiver clocks.
In order to guarantee sufficient transitions of the reo
ceived data to enable the DPLL to lock, NRZI encoding
of the data Is recommended. This ensures that, within a
frame, data transitions occur at least every five bit times
- the longest sequence of 1s which may be transmitted
with zero bit insertion. It Is also recommended that
frames following a line idle be transmitted with preframe sync characters which provide a minimum of 12
transitions. This ensures that the DPLL is generating
DPLL pulses at the nominal bit centers In time for the
opening flag. (Two OOH characters meet this requirement by supplying 16 transitions with NRZI encoding.
The 8273 contains a mode which supplies such a pre·
frame sync.)

CBSY: Command Busy - CBSY indicates when the
8273 is In the command phase. CBSY is set when the
CPU writes a command Into the Command register,
starting the Command phase. It is reset when the last
parameter is deposited In the Parameter register and
accepted by the 8273, completing the Command
phase.
CBF: Command Buffer Full - When set, this bit indicates that a byte Is present In the Command
register. This bit is normally not used.
CPBF: Command Parameter Buffer Full- This bit indicates that the Parameter register contains a
parameter. It Is set when the CPU deposits a
parameter in the Parameter register. It is reset when
the 8273 accepts the parameter.

Figure 17 Illustrates 8273 clock configurations using
either synchronous or asynchronous modems. Notice
how the DPLL output is used for both TxC and RxC In
the asynchronous case. This feature eliminates the
need for external clock generation logic where low cost)
asynchronous modems are used and also allows direct
connection of 8273s for the ultimate In low cost data
links. The configuration for loop applications Is discussed In a following section.

CRBF: Command Result Buffer Full - This bit Is set
when the 8273 places a result from an Immediate
type command In the Result regIster. It is reset when
the CPU reads the result from the Result register.
RxINT: Receiver Interrupt - The state of the RxlNT
pin is reflected by this bit. RxlNT Is set by the 8273
whenever the receiver needs serVicing. RxlNTls reset
when the CPU reads the results or performs the data
transfer.
'

This completes our discussion of the hardware aspects
of the 8273. Its software aspects are no~ discussed.

SOFTWARE ASPECTS OF THE 8273

TxINT: Transmitter Inter;upt - This bit is Identical to
RxlNT except action Is Initiated based on transmitter
.Interrupt sources.
.

The software aspects of the 8273 involve the communication of both commands from the CPU to the 8273 and
the return of results of those commands from the 8273

SYNC
MODEM

-=

NC

SYNCHRONOUS MODEM INTERFACE

32X
CLOCK

ASYNCHRONOUS

MOD~M

INTERFACE

Figure 17. Serial Da'a Timing _Co_n!l.gura'I~!"

9-153

231311-001

APPLICATIONS
RxIRA: ReceIver Interrupt Result Available - RxlRA
Is set when the 8273 places an Interrupt result byte
into the Rxl/R register. RxlRA is reset when the CPU
reads the Rxl/R register.

phase. A detailed description of the commands and
their parameters Is presented In a following section.

TxIRA: Transmitter Interrupt Result· Available TxlRA Is the corresponding Result Available bit for
the transmitter. It Is set when the 8273 places an interrupt result byte In the Txl/R register and reset
when the CPU reads the register.
The significance of each of these bits will be evident
shortly. Since the software requirements of each
8273 phase are essentially Independent, each phase
Is covered separately.

I

I I I I I ~ ~

II~

TxlRA RJ(IRA TIIINT AlltNT -

TIINT RESULT AVAILABLE
AdNT RESULT AVAILABLE
Til INTEflRUPT
All. INTERRUPT

cnBF -

COMMAND RESULT

- BUFFER FULL
CPBF _ COMMAND PARAMETER
BUFFER FULL
caF - COMMAND BUFFER FULL
casy..- COMMAND BUSY

"Figure 18. Status Register Forniaii

C0t:nmand Phase Software
Recalling the Command phase description In an earlier
section, the CPU starts the Command phase by writing a
commanq byte into the 8273 COmmand register. If further information about the command is required by the
8273, the CPU writes this information into the Parameter
register. Figure 19 Is a flowchart of the Command
phase. Notice that the CBSY and CPBF bits of the
Status register are used to handshake the command
and parameter bytes. Also note that the chart shows
that a command may not be Issued If the Status register
indicates the 8273 is busy (CBSY = 1). If a· command is
issued while CBSY = 1, the original command is overwritten and lost. (Remember that CBSY signifies the
command phase Is In progress and not the actual execution of the command..) The flowchart also includes a
Parameter buffer full check. The CPU must walt until
CPBF = 0 before writing a parameter to the Parameter
register. If a parameter Is Issued while CPBF 1, the
previous parameter is overwritten and lost. An example
of command output assembly language software is provided In Figure 20a. This software assumes that a command buffer exists In memory. The buffer is pOinted at
by the HL·register. Figure 20b shows the command buffer structure.

Figura 19. Command Ph••e Flowchar1

,FUNCTION: COMMAND DISPATCHER
,INPUTS, HL - COMMAND BUFFER ADDRESS
,OUTPUTS,. NONE
,CALLS, NONE

,DESTROYS: A,B,H,L,F/P'S
,DESCRIPTION, CMDOUT ISSUES THE COMMAND
,IN THE COMMAND BUfFER POINTED AT. BY HL

,

=

The 8273 Is a full duplex device, i.e., both the transmitter
and receiver may be executing commands or passing Interrupt results at any given time. (Separate Rx and Tx interrupt pins and result registers are provided for this
reason.) However, there Is only one· Command register.
Thus, the Command register must be used for only one
command sequence at a time and the transmitter and
receiver may never be simultaneously In a command

9-154

CMDOUT, LXI
MOV
INX
CMDlI
IN
RLC
JC
HOV
OUT
CHD2.
MOV
ANA
RZ
INX
DCR
CHD3,
IN
ANI
JNZ
MOV
OUT
JMP

+

PARAMETERS

H,CMDBUF,POINT HL AT BUFFER
8,M
,1ST. ENTRY IS PAR. COUNT
H
,POINT AT COMMAND BYTE
STAT73 ,READ 8273 STATUS
,ROTATE CBSY INTO CARRY
CMDl
,WAIT UNTIL CBSY=8
A,M
,MOVE COMMAND BY.TE TO A
COMM73
,PUT COMMAND· IN COMMAND REG
A,B
,GET PARAMETER C;:OUNT
A
,TEST IF ZERO
,IF B THEN Do,NE

H

,NOT ,DONE, SO POINT AT NEXT PAR

B
STAT73
CPSF
CMD3
A,M
PARH73
CMD2

; DEC P~RAMETER COUNT
; READ 8273 STATUS

;TEST cpaF BIT
,WAIT UNTIL CPBF IS B
;GET PARAMETER FaOM BUFFER
,OUTPUT PAR TO PARAMETER REG
,C·HECK IF MORE PARAMETERS

~F1g... lOA. Commend Pha•• Softw.ra

231311-001

APPLICATIONS

+4

PARAMETER 3

+3

PARAMETER 2

+2

PARAMETER 1

+1

COMMAND

CMDBUF:

PARAMETER COUNT

Result register to obtain the Immediate result. The
Result register provides only the results from immediate commands.
Example software for handling Immediate results Is
shown in Figure 21. The routine returns with the result
in the accumulator. The CPU then uses the result as is
appropriate.

-HL

All non-immediate commands deal with either the transmitter or receiver. Results from these commands are
provided in the Txl/R (Transmit Interrupt Result) and
Rxl/R (Receive Interrupt Result) registers respectively.
Results in these registers are conveyed to the CPU by
the TxlRA and RxlRA bits of the Status register. Results
of non-immediate commands consist of one byte result
interrupt code indicating the condition for the interrupt
and, if required, one or more bytes supplying additional
information. The interrupt codes and the meaning of the
additional results are covered following the detailed
command description.

Figure 2OB. Command Bulla, Form.t

Execution Phase Software
During the Execution phase, the operation specified by
the Command phase is performed. If the system utilizes
DMA for data transfers, there is no CPU involvement
during this phase, so no software Is required. If nonDMA data transfers are used, either Interrupts or polling
Is used to signal a data transfer reque,;t.
For interrupt-driven transfers the 8273 raises the appropriate INT pin. When responding to the interrupt, the
,CPU must determine whether it is a data transfer request or an interrupt signaling that an operation is complete and results are available. The CPU determines the
cause by reading the Status register and interrogating
the associated IRA (Interrupt Result Available) bit (TxIRA forTxlNT and RxlRA for RxINT).lf the IRA= 0, the interrupt is a data transfer request. If the IRA = 1, an
operation is complete and the associated Interrupt
Result register must be read to determine the completion status (good/bad/etc.). A software interrupt handler
implementing the above sequence is presented as part
of the Result phase software.
When polling is used to determine when data transfers
are required, the polling routine reads the Status
register looking for one of the INT bits to be set. When a
set INT bit is found, the corresponding IRA bit is examined. Like in the interrupt-driven case, if the IRA = 0, a
data transfer is required. If IRA = 1, an operation is complete and the Interrupt Result register needs to be read.
Again, example polling software is presented in the next
section.

Non-immediate results are passed to the CPU in
response to either interrupts or polling of the Status
register. Figure 22 illustrates an interrupt-driven result
handler. (Please note that all of the software presented
in this application note is not optimized for either speed
or code efficiency. Tiley are provided as a guide and to
illustrate concepts.) This handler provides for interruptdriven data transfers as was promised in the last sec:
tion. Users employing DMA-based transfers do not need
the lines where the IRA bit is tested for zero. (These
lines are denoted by an asterisk in the comments column.) Note that the INT bit is used to determine when all
results have been read. All results must be read. Otherwise, the INT bit (and pin) will remain high and further interrupts may be missed. These routines place the
results in a result buffer pOinted at by RCRBUF and
TxRBUF.
A typical result handler for systems utilizing polling is
shown in Figure 23. Data transfers are also handled by
this routine. This routine utilizes the routines of Figure
22 to handle the results.
At this point, the reader should have a good conceptual
feel about how the 8273 operates. It is now time for the
particulars of each command to be discussed.

Result Phase Software
During the Result phase the 8273 notifies the CPU of the
outcome of a command. The Result phase is initiated by
either a successful completion of an operation or an error detected during execution. Some commands such'
as reading or writing the I/O ports provide immediate
results, that is, there is essentially no delay from the
issuing of the command and when the result is available. Other commands such as frame transmit, take
time to complete so their result is not available immediately. Separate result registers are provided to
distinguish these two types of commands and to avoid
interrupt handling for simple results.
Immediate results are provided in the Result register.
Validity of information in this register is indicated to the
CPU by way of the CRBF bit in the Status register. When
the CPU completes the Command phase of an immediate command, it polls the Status register waiting
until CRBF= 1. When this occurs, the CPU may read the

9-155

FUNCTION: IMDRLT
INPUTS;

NONE

OU'l'PU'l'S: HtSULT REGIS'l'ER IN A
CALLS: hONE
DE5'l'HUYS: A, F IF' 5
DI:.SCkIPTION: IM[)RLT IS CALLED AF'l'ER A CMDOUT FOR AN

IMMI:..LIATE: CUMNAt..u TO READ 'I'HE. RESULT REGISTER
MC.RL'l':

IN
ANI
JZ
IN
1-.1:.'1

STA'I71
CkBF
IMDRL'l'
RESL71
; h.E.TURN

;Ri:.AD 8271 STA'I'US
; Tf:.ST If' RESULT REG R.E:;ADi'

;i'tAIT IF CHBF=0

.

; HeAD RE:SULT REGISTER

Figure 21. Immldlat. R.ault Handle,

231311-001

APPLICATIONS
, FUNCTION. POLOP
,INPUTS, NONE.
,OUTPUTS. C.S CNO STATUS), ·1 CRX COMPLETION),
,
'.2 (TX COMPLETION), -3 (BOTH)
.CALLS: TXI, RXI
,DESTROYS; B,e
,DESCRIPTION. POLOP IS CALLED TO ,POLL THE 8273 FOR
;DATA TRANSFERS AND COMPLETION RESULTS.
THE
;ROUTINES TXI AlIID RXI ARE USED FOR THE ACTUAL
,TRANSFERS AND BUFFER WORK.
POLOP RETURNS
,THE S'I'ATPS OF THEIR ACTION.

,FUNqTION. RXI - INTERRUPT DRIVEN RESULT/DATA HANDLER
,INPUTS: ReRSUF, RCYPNT
.
,CALLS. NONE
, OUTPUTS: RCRBUF, RCVPNT
,DESTROYS: NOTHING
, DESCRIPTION: RXI IS ENTERED AT A RECEIVER INTERRUPT.
,THE INTERRUPT IS TESTED FOR DATA TRANSFER (IRA-e)
,OR RESULT (IRA-!).
FOR DATA TRANSFER, THE DATA IS
!,PLACED IN A BUFFER AT RCVPNT. RESULTS ARE PLACED IN
,A BUFFER AT RCRSUF.
,A FLAGCRXFLAG) IS SET IF THE INTERRUPT WAS A RESULT.
, CDATA TRANSFER INSTRUCTIONS ARE DENOTED SY C*) AND
. rMAYBE ELIMINATED BY USERS VSING OHA.

,

POLOP:

,

RXII

RXIl:

RXI2:

RXI4:
RXIl:

PUSH
PUSH
PUSH
IN
ANI
JZ
LHLD
IN ,
ANI
JZ
IN
ANI
JZ
IN
MOV
INX
SHLD
JMP
SHLD
IN
MOV
INX
JMP
MVI
STA
,POP
POP
POP
EI
RET

"

PSW
S
STAT71
RURA
RXI2
RCRSUF
STAT71
RUNT
RXI4 "
STAT71
RXIRA
RXIl
RXIR71
M,A
H
RCRBUF
RXIl
RCVPNT
RCVDAT
M,A

H
RXIl

A,aIH
RXFLAG

B

',SAVE HL
;SAYf; PSW

,SAVE B
,

C*) READ 8273 STATUS

;

(~)

TEST

I~

BIT

; (*) IF 0, DA1.'A TRANSFER HE-EDED
:GET RESULT BUFFER POINT!::R

;READ 8271 STA'l.'US AGAIN
,TEST INT BIT'

;.IF 0, TH~N DONE
IREAD 5271 5'l'ATUS AGAIN
;TEST IRA AGAIN'
; LOOP ·UN'l.'IL RESULT IS READY
;READY, ·READ RXI/R

,

'l'xI!:

EoI
TX!2:

RET
LHLD
HOV
OUT
INX
SHLD
JMP

C

;SAVE PSW
,CLEAR C ,
,READ 8273 STATUS
;ARE TXINT'OR RXINT SET?
;NO, EXIT
; READ 8273 STATUS
;TI::ST ax INT
; YES, GO SERVICE RX
;MUST BE TX, GO SERVICE IT
;GET' TX FLAG
;WAS IT A COMPLE.TIOH? (0.1)
;NO, SO JUST EXIT
; YES, UPDATE C

C, '
POLOP1

:TRY AGAIN

txtc:

CALL
LDA
CPI
JNZ
INR
JMP

RXI
RXFLAG
UH
PEXIT
C
POLOPl

;GO SERVICE RX
,GET RX FLAG
,WAS IT A COMPLE'I'ION?
,NO, SO JUST EXIT
.;YES, UPDATE C
,TRY AGAlt.!

POP
RE'l'

psw

PEXIT:

,GO BACK TO SEE IF MOI.!' BUFFER
:BUMP RESULT POINTER
,RESTORE BUFFER P,OINTER

, FUNC1'ION: TXI - INTERRUPT DRIVEN RESULT/DATA HANDLER
',INPUTS: 'l'XRBUF., TXPNT, TXFLAG
; OUTPU'l'S; TXRBUF, TXPNT, TXFLAG
, CALLS: NONE
; DESTf(IW¥¥W
l

.

This cemmand Is very similar in eperatien to. Selective
Receive except that One Bit Delay mede must,be set and
that the leep Is captured by placing' transmitter in Flag
Stream mede autematically after an, EOP character Is
detected fellewlng a selectively received frame. The
details ef using the 8273 in leep cenflguratlens is
discussed In a later section so. please held questiens
until then.
'

NOT USED - 00 NOT CHANGE
ONE BIT DELAY ENABLE

Flgu,e 27. ene Bit Delay MOde Reglste,

The handling ef interrupt results Is cemmen ameng the
three cemmands. When a frame is received witheut
errer, i.e., the FCS is cerrect and CD (Carrier Detect) was
active threugheut the frame er no. attempt was made to.
everfill the buffer; the 8273 interrupts the CPU fellewing
the clesing flag to. pass the cempletien results. These
results, In erder, are the receiver Interrupt result cede
(RIC), and the byte length ef the Infermatlen field ef the
received frame (Ro, R,). If Buffered mede is selected, the
address and centrelflelds are passed as two. additienal
results. If Buffered mede is net selected, the address
and centrol fields are passed as the first two. data
transfers and Ro, R, reflect the infermatien field length
plus two..

Figure 28 shews the Set and Reset cemmands asseclated with the abeve registers. The mask which sets er
resets the desired bits is treated as a,slngle parameter.
These cemmands de net interrupt ner previde results
during the Result phase. After reset, the 8273 defaults to.
all ef these bits reset. '

REGISTER
ONE BIT DELAY MODE
DATA TRANSFER MODE
OPERATING MODE
SERIAL 110 MODE

ceMMAND

HEX
CDDE

PARAMETER

SET
RESET
SET
RESET
SET,
RESET
SET
RESET

A4
84
97
57
91
51
AD
60

SET MASK
RESET MASK
SET MASK
RESET MASK
SET MASK
RESET MASK
SET MASK
RESET MASK

Receive Disable
The receiver may also. be disabled usir)g the Receive
Disable cemmand. This cemmand terminates any
receive eperatien immediately. No. parameters are required and no. results are returned.

Figura 28. Inltlallzatlon/Conllguratlon Command Suminary

Receive Commands
The 8273 supperts three receive cemmands plus a
receiver disable functlen.
General Receive
When cemmanded to. General Receive, the 8273 passes
all frames either to. memery (DMA mede) er to. the CPU
(nen-DMA mede) regardless ef the centents ef the
frame's address field. This cemmand is used fer primary
and leep centreller statlens. Two. parameters are required: Bo and B, . These parameters are the LSB and
MSB ef the receiver buffer size. Giving the 8273 this
extra Infermatlenalleviates the CPU ef the burden ef
checking fer buffer everflew. The 8273 will interrupt the
CPU If the received frame attempts to. everfill the
alletted buffer space.

The detailS fer the Receive cemmand are shewn in
Figure 29. The Interrupt result cede key ,Is shewn in
Figure 30. Seme explanatien ef these result cedes is
appreprlate.
The Interrupt result cede is the first byte passed to. the
CPU in the Rxl/R register during the Result phase. Bits
0 4-00 define the cause ef the receiver interrupt. Since
each result cede has speCific impllcatlens, they are
discussed separately belew.

9-158

ceMMAND

HEX
ceDE

GENER,AL RECEIVE
SELECTIVE RECEIVE
SELECTIVE LOOP RECEIVE
DISABLE RECEIVER

CO
Cl
C2
C5

PARAM·
ETERS
BO. Bl

BO, BhA1tA2
BO. Bl.Al.A2
NONE

RESULTSRxllR
RIC. Ro.Rl. A. C
RIC. RD. Rl. A. C
RIC. RD. Rl. A. C
NONE

'A AND C ARE PASSED AS RESULTS eNLY IN BUFFERED MO,DE.

!"gura 28. Receive, Command~ummary

231311-001

APPLICATIONS
RIC
07- 00
00000
00001
00000011
000 00100
000 00101
000 00110
00000111
000 01000
000 01001
000 01010
00001011

rupt one character time later. The Idle Detect result oc·
curs whenever 15 consecutive 1s are received. After the
Abort Detect interrupt, the receiver remains active. After
the Idle Detect Interrupt, the receiver Is disabled and
must be recommanded before further frames may be
received.

R.STATUS
RECEIVER INTERRUPT RESULT CODE

~

AI MATCH OR GENERAL RECEIVE
A2 MATCH
CRC ERROR
ABORT DETECTED
IDLE DETECTED
EOP DETECTED
FRAME < 32 BITS
DMA OVERRUN
MEMORY BUFFER OVERFLOW
CARRIER DETECT FAILURE
RECEIVER INTERRUPT OVERRUN

ACTIVE
ACTIVE
ACTIVE
ACTIVE
DISABLED
DISABLED
ACTIVE
DISABLED
DISABLED
DISABLED
DISABLED

°07- 05

PARTIAL BYTE RECEIVED

III
000
100
010
110
001
101
011

ALL 8 BITS OF LAST BYTE
DO
01-00
02-00
03- 00
040-0
OS-DO
08- 00

If the EOP Interrupt bit Is set in the Operating Mode
register, the EOP Detect result Is returned whenever an
EOP character Is received. The receiver is disabled, so
the Idle following the EOP does not generate an Idle
Detect interrupt.
The minimum number of bits in a valid frame between
the flags is 32. Fewer than 32 bits indicates an error. If
Buffered mode is selected, such frames are ignored, i.e.,
no data transfers or interrupts are generated. In nonBuffered mode, a < 32-bit frame generates an interrupt
with the < 32-blt Frame result since data transfers may
already have disturbed the 8257 or interrupt handler. The
receiver remains active.

:f:lg~'.".30.,Rl'c.lver Interrupt Result Cocle.'(RICi.

The first two result codes result from the error·free
reception of a frame. 'If the frame Is received correctly
after a General Receive command, the first result is
returned. If either Selective Receive command was used
(normal or loop), a match with AI generates the first
result code and a match with A2 generates the second.
In either case, the receiver remains active after the inter·
rupt; however, the internal buffer'size counters are not
reset. That is, if the receive command indicated 100
bytes were allocated to the r~ceive buffer (B o, B1) and an
80·byte frame was received correctly, the maximum next
frame size that could be received without recomman·
ding the receiver (resetting Bo and B1) is 20 bytes. Thus,
it is common practice to recommand the receiver after
each frame reception. DMA and/or memory pOinters are
usually updated at this time. (Note that users who do
not wish to take advantage of the 8273'sbuffer manage·
ment features may simply use Bo, Bl = OFFH for each
receive command. Then frames of 65K bytes may be
received without buffer overflow errors.)
,
'The third result code Is a CRC error. This indicates that
a frame was received in the correct format (flags, etc.);
however, the received FCS did not check.with the inter·
nally generated FCS. The frame should be discarded.
The receiver remains active. (Do not forget that even
though an error condition has been detected, all frame
information up until that error has either been trans·
ferred to memory or passed to the CPU. This informa·
tion should be invalidated. This applies to all receiver
error conditions.) Note that the FCS, either transmitted or
received, is never available to the CPU.
The Abort Detect result occurs whenever the receiver
sees either an SDLC (81s) or an HDLC (7 1s), depending
on the Operating Mode register. However, the interven·
Ing Abort character between a closing flag and an Idle
does not generate an interrupt. If an Abort character
(seen by an active receiver within a frame) Is not pre·
ceded by a flag and is followed by an Idle, an interrupt
will be generated for the Abort, followed by an Idle inter·

9-159

The DMA Overrun result results from the DMA controller
being too slow in extracting data from the 8273, i.e., the
RxDACK signal is not returned before the, next received
byte is ready for transfer. The receiver is disabled if this
error condition 'occurs.
The Memory Buffer Overflow result occurs when the
number of received bytes exceeds the receiver buffer
length supplied by the Bo and Bl parameters in the
receive command. The receiver is disabled.
The Carrier Detect Failure result occurs when the CD
pin goes high (inactive) during reception of a frame. The
CD pin is used to qualify reception and must be active
by the time the address field starts to be received. If CD
is lost during the frame, a CD Failure interrupt is
generated and the receiver is disabled. No interrupt is
generated if CD goes inactive between frames.
If a condition occurs requiring an interrupt be generated
before the CPU has finished reading the previous interrupt results, the second interrupt is generated after the
current Result phase is complete (the RxlNT pin and
status bit go low then high). However, the interrupt
result for this second interrupt will be a Receive Interrupt Overrun. The actual cause of the second interrupt is
lost. One case where this may occur is at the end of a
received frame where the line goes idle. The 8273
generates a received frame interrupt after the closing
flag and then 15-bit times later, generates an Idle Detect
interrupt. If the interrupt service routine is slow in
reading the first interrupt's results, the internal Rxl/R
register stili contains result information when the Idle
Detect interrupt occurs. Rather than wiping out the
previous results, the 8273 adds a Receive Interrupt Overrun result as an extra result. If the system's interrupt
structure is such that the second Interrupt is not
acknowledged (interrupts are still disabled f~om the first
interrupt), the Receive Interrupt Overrun result is read as
an extra result, after those from the first interrupt. If the
second interrupt is serviced, the Receive Interrupt Overrun is returned as a single result. (Note that the INT pins
supply the necessary transitions to support a Program231311-001

APPLICATIONS
mabie Interrupt Controller such as the Intel 821)9. Each
Interrupt generates a positive·going edge on the appro·
prlate INT pin and the high level Is held until the inter·
rupt is completely serviced.) In general, It Is possible to
have interrupts occurring at one character time Inter·
vals. Thus the interrupt handling software must have at
least that much response and service time.

At the end of the frame, the transmitter Interrupts the
CPU (the interrupt results are discussed shortly) and
returns to either Idle or Flag Stream, depending on the
Flag Stream bit of the Operating Mode register. If RTS
was active before the transmit command, the 8273 does
not change It. " it was Inactive, the 8273 will deactivate
It within one character time.

The occurrence of Receive Interrupt Overruns Is an in·
dlcatlon of marginal software design; the system's inter·
rupt response and servicing time Is not sufficient for the
data rates being attempted. It is advisable to configure
the Interrupt handling software to simply read the inter·
rupt results, place them Into a buffer, and clear the inter·
rupt as quickly as possible. The software can then ex·
amine the buffer for new results at Its leisure, and take
appropriate action. This can easily be accomplished by
using a result buffer flag that Indicates when new
results are available. The interrupt handler sets the flag
and the main program resets It once the results are
retrieved. '

Loop Transmit

Both SOLC and HOLC allow frames which are of arbl·
trary length (>32 bits). The 8273 handles this' N·bit
reception through the high order bits (07-051 of the
result code. These bits code the number of valid reo
celved bits In the last received Information field byte.
This coding Is shown In Figure 30. The high order bits of
the received partial btye are indeterminate. [The ad·
dress, control, and Information fields are transmitted
least significant bit (Ao! first: The FCS Is complemented
and transmitted most significant bit first.)
Transmit Commands
The 8273 transmitter Is supported by three Transmit
commands and three corresponding Abort commands.
Transmit Frame
The' Transmit Frame command simply transmits a
frame. Four parameters are required when Buffered
mode Is selected and two when It Is not. In either case,
the first two parameters are the least and the most
significant bytes of the desired frame length (La, L,). In
Buffered mode, La and L1 equal the length in bytes of
the desired Information field, while in the non·Buffered
mode, La and L1 must be specified as the Information
field length plus two. (La and L1 specify the number of
data transfers to be performed.) In Buffered mode, the
address and control fields are presented to the transmit·
ter as the third and fourth parameters respectively. In
non·Buffered mode, the A and C fields must be passed
as the first two data transfers.
When the Transmit Frame command is issued, the 8273
makes RTS (Request·to·Send) active (pin low) if it was
not already. It then waits until CTS (Clear·to·Send) goes
active (pin low) before starting the frame. "the Preframe
Sync bit in the Operting Mode register' is set, the trans·
mltter prefaces two characters (16 transitions) before
the opening flag. " the Flag Stream bit is set in the
Operating Mode register, the frame (including Preframe
Sync if selected) Is started on a flag boundary. Other·
wise'the frame starts on a character boundary.

Loop Transmit Is similar to Frame Transmit (the paramo
eter definition Is the same). But since it deals with loop
configurations, One Bit Delay mode must be selected.
" the transmitter is not in Flag Stream mode when this
command Is Issued, the transmitter waits until after a
received EOP character has been converted to a flag
(this is done automatically) before transmitting. (The
one bit delay Is, of course, suspended during transmit.)
" the transmitter Is already in Flag Stream mode as a
result of a selectively received frame during a Selective
Loop Receive command, transmission will begin at the
next flag boundary for Buffered mode or at the third flag
boundary for non·Buffered mode. This discrepancy Is to
allow time for enough data transfers to occur to fill up
the internal transmit buffer. At the end of a Loop Trans·
mit, the One Bit Delay mode Is re·entered and the flag
stream mode Is reset. More detailed loop operation Is
covered later.
Transmit Transparent
The Transmit Transparent command enables the 8273 to
transmit a block of raw data. This data is without SOLC
protocol, i.e., no zero bit insertion, flags, or FCS. Thus It
Is possible to construct and transmit a BI·Syncmessage
for front·end processor switching or to construct and
transmit an SOLC message with incorrect FCS for dlag·
nostic purposes. Only the Lo and L1 parameters are used
sin'ce there are not fields in this mode. (the 8273 does
not support a Receive Transparent command.)
Abort Commands
Each of the above transmit commands has an associated Abort commant!. The Abort Frame Transmit command causes the transmitter to send eight contiguous
ones (no zero bit insertion) Immediately and then revert
to either Idle or flag streaming based on the Flag Stream
bit. (The 8 1s as an Abort character is compatible with
-both SOLC and HOLC.)
For, Loop Transmit, the Abort Loop Transmit command
causes the transmitter to send one flag and then revert
to one bit delay. Loop protocol depends upon FCS
errors to detect aborted frames.
The Abort Transmit Transparent simply causes the
transmitter to revert to either idles or flags as a function
of the Flag Stream mode specified.
The Abort commands require no parameters, however,
they do generate an interrupt and ,return a result when
complete.
A summary of the Transmit commands is shown in
Figure 31. Figure 32 shows the various transmit Interrupt result' codes. As in the receiver operation, the
transmitter generates Interrupts based on either good

9-160

231311-001

APPLICATIONS
completion of an operation or an error condition to start
the Result phase.

writing of the 01 and the 00. The action taken Is the
same as If a hardware reset Is performed, namely:

The Early Transmit Interrupt result occurs after the last
data transfer to the 8273 If the Early Transmit Interrupt
bit is set In the Operating Mode register. If the 8273 Is
commanded to transmit again within two character
times, a single flag will separate the frames. (Buffered
mode must be used for a single flag to separate the
frames. If non-Buffered mode is. selected, three flags
will separate the frames.) If this time constraint is not
met, another interrupt is generated and multiple flags or
idles will separate the frames. The second interrupt is
the normal Frame Transmit Complete interrupt. The
Frame Transmit Complete result occurs at the closing
flag to signify a good completion.

1. The modem control outputs are forced high
Inactive).
2. The 8273 Status register is cleared.
3. Any commands in progress cease.
4. The 8273 enters an idle state until the next command Is Issued.
Modem Control Commands

The modem control ports were discussed earlier in the
Hardware section. The commands used to manipulate
these ports are shown in Figure 33. The Read Port A and
Read Port B commands are immediate. The bit definition for the returned byte is shown in Figures 13 and 14.
00 not forget that the returned value represents the
logical condition of the pin, i.e., pin active (low) = bit
set.

The OMA Underrun result is analogous to the OMA Overrun result in the receiver. Since SOlC does not support
intraframe time fill, if the OMA controller or CPU does
not supply the data in time, the frame must be aborted.
The action taken by the transmitter on this error is automatic. It aborts the frame just as if an Abort command
had been issued.

PORT

Clear-to-Send Error result is generated if CTS goes inactive during a frame transmission. The frame is aborted
as above.

A INPUT
BOUTPUT

The Abort Complete result is self-explanatory. Please
note however that no Abort Complete interrupt Is
generated when an automatic abort occurs. The next
command type consists of only one command.

PARAMETERS'

TRANSMIT FRAME
ABORT

CB
CC

LO. Ll. A. C
NONE

TIC
TIC

LOOP TRANSMIT
ABORT
TRANSMIT TRANSPARENT
ABORT

CA
CE

LO. Ll. A. C
NONE

TIC
TIC

CO
CD

LOt L1
NONE

TIC
TIC

HEX
CODE

PARAMETER

REG
RESULT

22
23

NONE

PORT VALUE

READ

NONE

PORT VALUE

SET

A3

SET. MASK

NONE

RESET

63

RESET MASK

NONE

READ

Figure 33. Modem Control Command Summary

The Set and Reset Port B commands are similar to the
Initialization commands in that they use a mask parameter which defines the bits to be changed. Set Port B
utilizes a logical OR mask and Reset Port B uses a
logical ANO mask. Setting a bit makes the pin active
(low). Resetting the bit deactivates the pin (high).

RESULTS
Txl/R

HEX
CODE

COMMAND

COMMAND

To help clarify the numerous timing relationships that
occur and their consequences, Figures 34 and 35 are
provided as an illustration of several typical sequences.
It is suggested that the reader go over these diagrams
and re-read the appropriate part of the previous sections
if necessary.

'A AND C ARE PASSED AS PARAMETERS IN BUFFERED. MODE ONLY.

Figure 31. Transmllter Command Summary

HLDC CONSIDERATIONS
TIC

07- 0 0
000
000
000
000
000

01100
01101
01110
01111
10000

TRANSMITTER INTERRUPT RESULT CODE

Tx STATUS
AFTER INT

EARLY Tx INTERRUPT

ACTIVE

FRAME Tx COMPLETE

IDLE OR FLAGS

DMA UNDERRUN
CLEAR TO SEND ERROR
ABORT COMPLETE

The 8273 supports HDLC as well as SOLC. Let's discuss
how the 8273 handles the three basic HOLC/SOLe differences: extended addressing, extended control, and
the 7 1s Abort character.

ABORT
ABORT
IDLE OR FLAGS

Figure 32. Transmitter Interrupt Result Codes

Reset Command

The Reset command provides a software reset function
for the 8273. It is a special case and does not utilize the
normal command interface. The reset facility is provided
in the Test Mode register. The 8273 is reset by simply
outputting a 01 H followed by a OOH to the Test Mode
register. Writing the 01 followed by the 00 mimicks the
action required by the hardware reset. Since the 8273 requires time to process the reset internally, at least 10
cycles of the "ClK clock must occur between the

9-161

Recalling Figure 4A, HOLC supports an address field of
indefinite length. The actual amount of extension used
is determined by the least significant bit of the characters immediately following the opening flag. If the LSB
is 0, more address field bytes follow. If the LSB is 1, this
byte is the final address field byte. Software must be
used to determine this extension.
If non-Buffered mode is used, the A, e, and I fields are in
memory. The software must examine the initial characters to find the extent of the address field. If Buffered
mode is used, the characters corresponding to the
SOLC A and e fields are transferred to the CPU as interrupt results. Buffered mode assumes the two characters
following the opening flag are to be transferred as interrupt results regardless of content or meaning. (The 8273
231311-001

APPLICATIONS
does not know whether it Is being used in an SOLC or an
HOLC environment.) In SOLC, these characters are
necessarily the A and C field bytes, however in HOLC,
their meaning may change depending on the amount of
extension used. The software must recognize this and
examine the transferred results as possible address
field extensions.
Frames may stili be selectively received as is needed for
secondary stations. The Selective Receive command is
still used. This command qualifies a frame reception on
the first byte following the opening flag matching either
of the A1 or A2 match byte parameters. While this does
not allow qualification over the complete range of HOLC
addresses, it does perform a qualification on the first
address byte. The remaining address field by tes, if any,
are then examined via software to completely qualify
the frame.
Once the extent of the address field is found, the following bytes form the control field. The same LSB test used
for the address field is applied to these bytes to determine the control field extension, up to two bytes maximum. The remaining frame bytes in memory represent
the information field.
The Abort character difference is handled in the
Operating Mode register. If the HOLC Abort Enable bit is
set, the reception of seven contiguous ones by an active
receiver will generate an Abort Detect interrupt rather
than eight ones. (Note that both the HOLC Abort Enable
bit and the EOP Interrupt bit must not be set simultaneously.)
Now let's move on to the SOLC loop configuration
discussion.

CARRIER DETECT

LOOP CONFIGURATION

Aside from use in the normal data link applications, the
8273 is extremely attractive in loop configuration due to
the speCial frame-level loop commands and the Digital
Phase Locked Loop. Toward this end, this section
details the hardware and software considerations when
using the 8273 in a loop application.
The loop configuration offers a simple, low-cost solution for systems with multiple stations within a small
physical location, i.e., retail stores and banks. There are
two primary reasons to consider a loop configuration.
The interconnect cost is lower for a loop over a multipoint configuration since only one twisted pair or fiber
optic cable is used. (The loop configuration does not
support the paSSing of distinct clock signals from station to station.) In addition, loop stations do not need
the intelligence of a multi-point station since the loop
protocal is simpler. The most difficult aspects of loop
station design are clock recovery and implementation of
one bit delay (both are handled neatly by the 8273).
Figure 36 illustrates a typical loop configuration with
one controller and two down-loop secondaries. Each
station must derive its own data timing from the
received data stream. Recalling our earlier discussion of
the OPLL notice that TxC and RxC clocks are provided
output. The only clock required in the
by the
secondaries is a simple, non-synchronized clock at 32
times the desired baud rate. The controller requires both
32 x and 1 x clocks. (The 1 x is usually implemented by
dividing the 32 x clock with a 5-bit divider. However,
there is no synchronism requirement between these
clocks so any convenient implementation may be used.)

DPtt

=...J

\'---

RxD

Rx COMMAND

r

I

A

DR

Ic

111

~~~:~N;~~~~~~~----------------7I--1--71' - - - . ; . . . . - - - - - - - - NON·BUFFERED
MODE

I

FRAME
COMPLETE

I

POSSIBLE
IDLE INT

'N~~~~~~i~---------------"""':------':"':'="::":'::'--",,;,;'=';;;'
A. ERROR·FREE FRAME RECEPTION

CARRIER DETECT

=...J

\\\\\\\\\\\\

RxD

Rx COMMAND

I

CD

CD

FAILURE __
LURE
IN~~~~~~i~ _______~..!:F=AI::::!!:....!..1
--!_.!........:........:..~_.!.......:..._-..:.....:..;=.:.::...
B. CARRIER DETECT FAILURE DURING FRAME RECEPTION

Figure 34. Sample Receiver Timing Diagrams

9-162

231311-001

APPLICATIONS

Tx COMMAND!

L
L

RTS~
CTS - - - - - - - '

I

I

A
C
1'1
1'2
.oR 1~~~fN~~~~~~~~------,--i--i--------------------------

I-

NON·BUFFERED

IN~~;~~~~~-------M-O-O-E--------------_-----....;.-F-RA-M-E_C_O_M_P_LE_TE
A_ ERROR-FREE FRAME TRANSMISSION
2ND FRAME

1ST FRAME

I

Tx COMMAND'l

I

I I

I

I I I I I

RTS~

CTS~

I

I

I

OR1~~~~~~~~~~~~--------....;.-11------------------11---'2--_ _~
tEARLYTx

IN~~;~~~~~-----------------------------------B. DIAGRAM SHOWING Tx COMMAND CUEING AND EARLY Tx INTERRUPT

(SINGLE FLAG BETWEEN FRAMES) BUFFERED MODE IS ASSUMED.

Tx COMMAND

I

L
CTS-------'

OR1~~~fN~~~~~~~~-----....;.I-A--~I-c--~1-11--~1-12--~I-'3--

_ _ _ _ _ _ _ _ _ _ ___

I

CTS

iN~;~~~~~---------------------:O:::R:-A-:-~::'~::-R;.:O;.:.R:.....------­
C. CTS FAILURE (OR OTHER ERROR) DURING TRANSMISSION

IN~~;~~PT

Figure 35. Sample Transmitter Timing Diagrams

9-163

231311-001

APPLICATIONS
the secondary terminates Its repeater function and Inserts its response frame (with multiple preceding flags
if necessary). After the closing flag of the response, the
secondary re-enters Its repeater function, repeating the
up-loop controller 1s. Notice that the final zero of the
response's closing flag plus the repeated 1s from the
controller form a new EOP for the next down-loop
secondary. This new EOP allows the next secondary to
Insert a response if ~It desires. This gives each secondary a chance to respond.

1xLOOP
OSCILLATOR
OR
DIVIDER ~

RxD

RxC

TxC

Back at the controller, after the polling frame has been
transmitted and the continuous 1s started, the controller waits until it receives an EOP. Receiving an EOP .
signifies to the controller that the original frame has
propagated around the loop followed by any responses
Inserted by the secondaries. At. this pOint, the controller
may either send flags to Idle the loop or transmit the
next frame. Let's assume that the loop is implemented
completely with the 8273s and describe the command
flows for a typical controller and secondary.

TxD

8273
8273
LOOP
TxD 1---;-1---1 RxD
LOOP
TERMINAL
TERMINAL

Figure 38. SOLC Loop Application

A quick review of loop protocol is appropriate. All communication on the loop Is controlled by the loop controller. When the controller wishes to allow the secondaries to transmit, It sends a polling frame (the control field contains a poll code) followed by an EOP (Endof-Poll) character. The secondaries use the EOP
character to capture the. loop and insert a response
frame as will be discussed shortly.
The secondaries normally operate In the repeater mode,
retransmitting rece.lved data with one bit time of delay.
All received frames are repeated. The secondary uses
the one bit time of delay to capture the loop:
When the loop Is Idle (no frames), the controller transmits continuous flag characters. This keeps transitions
on the loop for the sake· of down-loop phase locked
loops. When the controller has a non-polling frame to
transmit, it simply transmits the frame and continues to
send flags. The non-polling frame is then repeated
around the loop and the controller receives it to signify a
complete traversal of the loop. At the particular secondary addressed by the frame, the data is transferred to
memory while being repeated. Other secondaries simply
repeat It.

The loop controller Is Initialized with commands which
specify that the NRZI, Preframe Sync, Flag Stream, and
EOP Interrupt modes are set. Thus, the controller encodes and decodes all data using NRZI format. Preframe
Sync mode specifies that all transmitted frames be
prefaced with 16 line transitions. This ensures that the
minimum of12 transitions needed by the DPLLs to lock
after an all 1s line have occurred by the time the secondary sees a frame's opening flag. Setting the Flag Stream
mode starts the transmitter sending flags which idles
the loop. And the EOP Interrupt mode specifies that the
controller processor will be interrupted whenever the
active receiver sees an EOP, Indicating the completion
of a poll cycle.
When the controller wishes to transmit a non-polling
frame, it simply executes a Frame Transmit command.
Since the Flag Stream mode is set, no EOP is formed
after the closing flag. When a polling frame is to be
transmitted, a General Receive command is executed
first. This enables the receiver and allows reception of
all incoming frames; namely, the original polling frame
plus any response frames inserted by the secondaries.
After the General Receive command, the frame is transmitted with a Frame. Transmit command. When the
frame Is complete, a transmitter interrupt is generated.
The loop controller processor uses this interrupt to
reset Flag Stream mode. This causes the transmitter to
start sending all 1s. An EOP is formed by the last flag
and the first 7 1s. This completes the loop controller
transmit sequence.

If the controller wants to poll the secondaries, it
transmits a polling frame followed by all1s (no zerO bit
insertion). The final zero of the closing frame plus the
first seven 1s form an EOP. While repeating, the secondaries monitor their incoming line for an EOP. When an
EOPis received, the secondary checks If it has any
response for the controller. If not, it simply continues
repeating: If the secondary has a response, It changes
the seventh EOP one into a zero (the one bit time of
delay allows time for this) and repeats it, forming a flag
for the down-loop stations. After this flag Is transmitted,

9-164

At any time following the start of the polling frame
tranSmission the loop' controller receiver will start
receiving frames. (The exact time difference depends, of
course, on the number of down-loop secondaries due to
each inserting one bit time of delay.) The first received
frame is simply the original polling frame. However, any
additional frames are those inserted by the secondaries.
The loop controller processor knows all frames .have
been received when it sees an EOP Interrupt. This interrupt is generated by the 8273 since the EOP.lnterrupt
mode was set during Initialization. At this pOint, the
transmitter may be commanded either to enter Flag

231311-001

APPLICATIONS
Stream mode, idling the loop, or to transmit the next
frame. A flowchart of the above sequence Is shown In
Figure 37.
The secondaries are initialized with the NRZI and One
Bit Delay modes set. This puts the 8273 into the repeater
mode with the transmitter repeating the received data
with one bit time of delay. Since a loop station cannoi
transmit until it sees and EOP character, any transmit
command is queued until an EOP is received. Thus
whenever the secondary wishes to transmit a response,
a Loop Transmit command is issued. The 8273 then
waits until it receives an EOP. At this pOint, the receiver
changes the EOP into a flag, repeats it, resets One Bit
Delay mode stopping the repeater function, and sets the
transmitter into Flag Stream mode. This captures the
loop. The transmitter now inserts its message. At the
closing flag, Flag Stream mode Is reset, and One Bit
Delay mode is set, returning the 8273 to repeater func·
tion and forming an EOP for the next down-loop station.
These actions happen automatically after a Loop
Transmit command is issued.

When the secondary wants Its receiver enabled, a Selective Loop Receive command is issued. The receiver then
looks for a frame having a match in the Address field.
Once such a frame is received, repeated, and transferred to memory, the secondary's processor is interrupted with the appropriate Match interrupt result and
the 8273 continues with the repeater function until an
EOP is received, at which point the loop is captured as
above. The processor should use the interrupt to determine if it has a message for the controlier. If it does, It
simply issues a Loop Transmit command and things
progress as above. If the processor has no message, the
software must reset the Flag Stream mode bit in the
Operating Mode register. This will inhibit the 8273 from
capturing the loop at the EOP. (The match frame and the
EOP may be separated in time by several frames depending on how many up-loop stations inserted messages of their own.) If the timing is such that the
receiver has already captured the loop when the Flag
Stream mode bit is reset, the mode is exited on a flag
boundary and the frame just appears to have extra closing flags before the EOP. Notice that the 8273 handles
the queuing of the transmit commands and the setting
and resetting of the mode bits automatically. Figure 38
illustrates the major points of the secondary command
sequence.

INITIALIZE -

SET NRZI. FLAG STREAM
PREFRAME SYNC. EOP
INTERRUPT MODES

INITIALIZE SET NRZI. ONE
BIT DELAY MODES

o
c::J

o

DENOTES COMMAND

DENOTES COMMANDS

c:::) DENOTES INTERRUPT CODES

DENOTES INTERRUPT CODE

FIgure

37. _Loop C_onlro"e~ Flowchart

FIgure 38. Loop Secondary Flowchart_

9-165

231311-001

APPLICATIONS
When an off-line secondary wishes to come on-line, It
must do so In a manner which does not disturb data on
the loop. Figure 39 shows a typical hardware interface.
The line labeled Port could be one of the 8273 Port Boutputs and is assumed to be high (1) initially. Thus up-loop
data Is simply passed down-loop with no delay; however, the receiver may still monitor data on the loop. To
come on-line, the secondary is initialized with only the
EOP Interrupt mode set. The up-loop data Is then monitored until an EOP occurs. At this pOint, the secondary's
CPU Is Interrupted with an EOP Interrupt. This signals
the CPU to set One Bit Delay mode In the 8273 and then
to set Port low (active). These actions switch the secondary's one bit delay into the loop. Since after the EOP
only 1s are traversing the loop, no loop disturbance occurs. The secondary now walts for the next EOP, captures the loop, and Inserts a "new on-line" message.
This signals the controller that a new secondary exists
and must be acknowledged. After the secondary receives its acknowledgement, the normal command flow
Is used.
It is hopefully evident from the above discussion that
the 8273 offers a very simple and easy to Implement
solution for designing loop stations whether they are
controllers or down-loop secondaries.

••DI------...-----UP.LOOP DATA
8273

DOWN·LOOP DATA

T.DI---+-----f,
PORT

1----'--1:>0---'

Figure 39. Loop Interlace

APPLICATION EXAMPLE
This section describes the hardware and software of the
8273/8085 system used to verify the 8273 implementation of SDLC on an actual IBM SDLC Link. This IBM link
was gratefully volunteered by Raytheon Data Systems In
Norwood, Mass. and I wish to thank them for their
generous cooperation. The IBM system consisted of a
370 Mainframe, a 3705 Communications Processor, and
a 3271 Terminal Controller. A Comlink II Modem supplied the modem interface and all communications took
place at 4800 baud. In addition to observing correct
responses, a Spectron 0601 B Datascope was used to
verify the data- excnange-s. A block dlagralll or tne
system is shown In Figure 40. The actual verification
was accomplished by the 8273 system receiving and
responding to polls from the 3705. This method was
used on both point-to-point and multi-point configurations. No attempt was made to implement any higher
protocol software over that of the poll and poll responses since such software would not affect the verification of the 8273 implementation. As testimony to the
ease of use of the 8273,the system worked on the first
try.

3"

MAINFRAME

3705

COMM.
PROCESSOR

Figure 40. Raytheon Block Diagram

An SDK-85 (System Design Kit) was used as the core
8085 system. This system provides up to 4K bytes of
ROM/EPROM, 512 bytes of RAM, 76.110 pins, plus two
timers as provided in two 8755 Combination EPROMII/O
devices and two 8155 Combination RAMII/O/Tlmer
devices. In addition,. 5 interrupt Inputs are supplied on
the 8085. The address, data, and control buses are buffered by the 8212 and 8216 latches and bidirectional bus
drivers. Although It was not used in this application, an
8279 Display Driver/Keyboard Encoder Is Included to interface the on-board display and keyboard. A block
diagram of the SDK-85 is shown in Figure 41. The 8273
and associated circuitry was constructed on the ample
wire-wrap area provided for the user.
The example 8273/8085 system is Interrupt-driven and
uses DMA for all data transfers supervised by an 8257
DMA Controller. A 2400 baud asynchronous line, Implemented with an 8251A USART, provides communication
between the software and the user. 8253 Programmable
Interval Timer is used to supply the baud rate clocks for
the 8251 A and 8273. (The 8273 baud rate clocks were
used only during initial system debug. In actual operation, the modem supplied these clocks via the RS-232 Interface.) Two 2142 1Kx 4 RAMs provided 512 bytes of
transmitter and 512 bytes of receiver buffer memory.
(Command and result buffers, plus miscellaneous
variables are stored in the 8155s.) The RS-232 interface
utilized MC1488 and MC1489 RS-232 drivers and
receivers. The schematic of the system Is shown in
Figure 42.
One detail to note is the DMA and Interrupt structure of
the transmit and receive channels. In both cases, the
receiver Is always given the higher priority (8257 DMA
channel 0 has priority over the remaining channels and
the 8085 RST 7.5 interrupt Input has priority over the
RST 6.5 Input.) Although the chOice Is arbitrary, this
technique minimizes the chance that received data
could be lost due to other processor or DMA commitments.
Also note that only one 8205 Decoder is used for both
the peripherals' and the memorys' Chip Selects. This
was done to eliminate separate memory and 110
decoders since it was known beforehand that neither
address space would be completely filled.
The 4 MHz crystal and 8224 Clock Generator were used
only to verify that the 8273 operates correctly at that
maximum spec speed. In a normal system, the 3.072
MHz clock from the 8085 would be sufficient. (This fact
was verified du~ing initial checkout.)

9-166

231311-001

APPLICATIONS
FlOMIIO IUS~)
E~ROMIIOI'165)

RAMIIDICOUNTf.1I
AODRESS

DATA

FIELD

FIElD

:;r:,:I)
L __ ..J

8

DATA

'"

1--1
I 8213
L __ ..J

1--1

3x1218 !¢4CCNTROl

CONTROLc::::====t:==::±======~=====:j::==========t:=~L __ ..J
BUS

:

rL -___
- -..,J

I

I

I

O",S

I

OPTIONAL. A PLACE HAS BEEN PMVIDEn ON THE PC IOARD FOil THE OEVICI!.IUT THE
DEVICE IS NOT INCLUDED

Figure 41. SDK·85 Funcllonal Block Diagram

O,~·--2·~'~~~----------------------------------------------------------r-----------rfOR

SDK·85

'"'

Figure 42. 8273JSDK·85 System

9-167

231311-001

APPLICATIONS
The software consists of the normal monitor program
supplied with the SDK-85 and a program to input commands to the 8273 and to display results_ The SDK-85
monitor allows the user to read and write on-board RAM,
start execution at any memory location, to single-step
through a program, and to examine any of the 8085's in·
ternal registers. The monitor drives either the on-board
keyboard/LED display or a serial TTY interface. This
monitor was modified slightly in order to use the. 8251 A
with a 2400 baud CRT as opposed to the 110 baud normally used. The 8273 program implements monitor-like
user interface. 8273 commands are entered by a twocharacter code followed by any parameters required by
that command. When 8273 interrupts occur, the source
of the interrupt is displayed along with any results
associated with it. To gain a flavor of how the user/program interface operates, a sample output is shown in
Figure 43. The 8273 program prompt character is a "- "
and user inputs are underlined.
The "SO 05" implements the Set Operating Mode command with a parameter of 05H. This sets the Buffer and
Flag Stream modes. "5501" sets the 8273 in NRZI mode
using the Set Serial I/O Mode command. The next command specifies General Receiver with a receiver buffer
size of 0100H bytes (Bo= 00, B1 = 01). The "TF" command causes the 8273 to transmit a frame containing an
address field of C2H and control field of 11H. The information field is 001122. The "TF" command has a special
format. The Lo and L1 parameters are computed from the
number of information field bytes entered.
After the TF command is entered, the 8273 transmits the
frame (assuming that the modem protocql is observed).
After the closing flag, the 8273 interrupts the 8085. The
8085 reads the interrupt results and places them in a
buffer. The software examines this buffer for new
results and if new results exist, the source of the interrupt is displayed along with the results.

Figures 44 through 51 show the flowcharts used for the
8273 program development. The actual program listing
is included as Appendix A. Figure 44 is the main status
poll loop. After all devices are initialized and a prompt
character displayed, a loop is entered at LOOPIT. This
loop checks for a change of status in the resu It buffer or
if a keyboard character has been received by the 8251 or
if a poll frame has been received. If any of these conditions are met, the program branches to the appropriate
routine. Otherwise, the loop is traversed again.
The result buffer is implemented as a 255-byte circular
buffer with two pointers: CNADR and LDADR. CNADR is
the console pointer. It pOints to the next result to be
displayed LDADR is the load pointer. It points to the
next empty position in tlie buffer into which the interrupt handler places the next result. The same buffer is
used for both transmitter and receiver results. LOOPIT
examines these pointers to detect when CNADR is not
equal to LDADR indicating that the buffer contains
results which have not been displayed. When this occurs, the program branches to the DISPLY routine.
DISPLY determines the source of the undisplayed
results by testing the first result. This first result is
necessarily the interrupt result code. If this result is
OCH or greater, the result is from a transmitter interrupt.
Otherwise it is from a receiver source. The source of the
result code is then displayed on the console along with
the next four results from the buffer. If the source was a
transmitter interrupt, the routine merely repoints the
pointer CNADR and returns to LOOPIT. For a receiver
source, the receiver data buffer is displayed in addition
to the receiver interrupt results before returning to
LOOPIT.

START

In this example, the ODH result indicates a Frame Complete interrupt. There is only one result for a transmitter
interrupt, the interrupt's trailing zero results were included to simplify programming.

CMDREC

LOOPIT

The next event is a frame reception. The interrupt
results are displayed in the order read from the 8273.
The EOH indicates a General Receive interrupt with the
last byte of the information field received on an 8-bit
boundary. The 03 00 (Ro, R1) results show that there are
3H bytes of information field received. The remaining
two results indicate that the received frame had a C2H
address field and a 34H control field. The 3 bytes of information field are displayed on the next line.

8273 MONITOR V1.2

-

SO 05
5501
GR 00 01
TF C2 11 00 11 22

TxlNT

-

RxlNT FF EE DO

00 00 00 00 00
EO 03 00 -C2 34

Figure 43. Sample 8273 Monitor I/O

Figure 44. Main Status Poll Loop

9-168

231311-001

APPLICATIONS

Figure 47. TF Subroutine
READ AND DISPLAY
REMAINING
RESULTS

Figure 45. DISPLY Subroutine

Figure 48. ToPOL Subroutine

PARAMETER #2
PARAMETER *1
COMMAND

B-1

rFigure 48.

4*

OF PARAMETERS

I

Figure 49. COMM Subroutine with Command Buffer Format

GETCMD Subroutine;

9-169

231311-001

APPLICATIONS
the Poll-Response mode is selected, the prompt
character is changed to a '+'. If frame is .received
which contains a prearranged poll con.trolfleld, the
memory location POLIN Is !)'lade nonzero by the rece.iver
Interrupt handler. LOOPIT examines this location and If
it is nonzero, causes a branch to the TxPOL routine. The
TxPOL routine clears POLIN, sets a pointer to a special
command buffer at CMDBUF1, and Issues the command
by way of the COMM2 entry in the COMM routine. The
special command buffer contains the appropriate
response frame for the poll frame received. These actions only occur when the Z command has changed the
prompt to a '+ '. If the prompt Is normal' -', polling
frames are displayed as normal frames and no response
Is transmitted. The Poll-Response mode was used durIng the IBM tests.

a

CHECK IF RESULTS
WILL FILL RESULT
BUFFER

EXIT TO
MONITOR

Figura 50. Txl (Transmitter Intenupt) Routine

If the result buffer pointers .In·dlcate an empty buffer, the
8251A is polled for a keyboard character. If the 8251 has
a character, GETCMD is called. There the character Is
read and checked If legal. Illegal characters simply
cause a reprompt. Legal characters indicate the start of
a command Input. Most commands are organized as two
characters signifying the command action; i.e., GR General Recei.ve. The software recognizes the two character command code. and takes the appropriate action.
For non·Transmit type commands, the hex equivalent of
the command is placed in the C register and the number
of parameters associated with that command Is placed
In the B register. The program then branches to the
COMM routine.

EXITTO
MONITOR

READ RESULTS AND
PLACE IN RESULT
BUFFER

The COMM routine builds the command buffer by
reading the required number of parameters from the
keyboard and placing them at. the· buffer pointed at by
CMDBUF. The routine at COMM2 then issues this command buffer to the 8273.
If a Transmit type command Is specified, the command
buffer is set up similarly to the the COMM routine;
however, since the Information field data is entered
from. the keyboard, im intermediate routine; TF, is
called. TF loads the transmit data buffer pointed at by
TxBUF. It counts the number of data bytes entered and
loads this number Into the command buffer as Lo,
L1• The command is then issued to the 8273 by jumping
toCMDOUT.
. One command does not directly result In a command beIng issued to the 8273. This command, Z, operates a
software flip-flop which selects whether the software
will re.spondautomatlcally to received polling frames. If

Figura 51. Rxl (Recevler Intenupt) Routine .

9-170

231311-001

APPLICATIONS

APPENDIX A

9-171

231311-001

APPLICATIONS
The final two software routines are the transmitter and
receiver interrupt handlers. The transmit interrupt
handler, Txl, simply saves the registers on the stack and
checks if loading the result buffer will fill it. If the result
buffer will overfill, the program is exited and control is
passed to the SDK·85 monitor. If not, the results are
read from the Txl/R register and placed in the result buf·
fer at LDADR. The DMA pointers are then reset, the
registers restored, and interrupts enabled. Execution
then returns to the pre·interrupt location.

special command buffer is loaded and the poll indicator,
POLIN, is made nonzero. If no match occurred, no action
is taken. Finally, the receiver DMA buffer pOinters are
. reset, the processor status restored, and interrupts are
enabled. The RET instruction returns execution to the
pre·interrupt location.

The receiver interrupt handler, Rxl, is only slightly more
complex. As in Txl, the registers are saved and the
possibility of overfilling the result buffer is examined. If
the result buffer is not full, the results are read from
Rxl/R and placed in the buffer. At this point the prompt
character is examined to see if the PolI·Response mode
is selected. If so, the control field is compared with two
possible polling control fields. If there is a match, the

This application note has covered the 8273 in some
detail. The simple and low cost loop configuration was
explored. And an 8273/8085 system was presented as a
sample design illustrating theDMAIinterrupt·driven in·
terface. It is hoped that the major features of the 8273,
namely the frame·level command structure and the
Digital Phase Locked Loop, have been shown to be a
valuable asset in an SDLe system design.

This completes the discussion of the 8273/8085 system
design.
CONCLUSION

9-172

231311·001

APPLICATIONS
APPENDIX A
ASf180 :Fl: RAYT71 SRC

~10DULE

1515-II 8988/9085 MACRO ASSEMBLER, )/i9a

LOC 09J
!!OOIl
0009

0999

SEQ

PAGE

1

SOURCE STATEMENT
1 $N()PAGING 110D85 NOCOND
2 TRUE
EQU
eeH
3;
4 TRUE1
5;

" DE~1
7.
8 ;

;ee FOR RAYTHEON
; FF FOR SELF-TEST

EQU

eeH

EQU

00H

; 00 FOR NORMAL RESPONSE
; FF FOR LOOP RESPONSE
. 00 FOR NO DEMO

..FF FOR i.l9'10

,

q •

"

10 ; GENERAL 8273 MON IiOR

~!liH

RAYTHEON POLL MODE ADDED

11 ;
17 ;
18.
19 ; COMMANOSiJPPORTED ARE: RS - RESET SERIAL 1/0 MODE

20
21
22
23
24

;
;
;
.'
;

SS
RO
SO
RD
GR
SR
TF
AF
SP
RP
RB
S8
5L
TL
Z

27 ;
28 ;

29;
30 ;
31 i

32 j
33 ;
24 ;
38 .•
39
40
41
42
41

-

SET SERIAL 1/0 MODE
RESET OPERATING MODE
SET OPERATING MODE
RECEIVER DISABLE
GENERAL RECE lliE
SaECTIIIE RECEIVE
TP.ANSt1IT FRAf1E

ABORT FRAME
SET PORT B
RESET PORT B
RESET 9NE BIT DELAY (PAR

SET ONE BIT DELA'~ (PAR
SELECTIVE LOOP RECEI\'E
TRANSMiT LOOP
CHANGE .MODES FliP/FLOP

= 7F)
= 80)

**************,***********************>1<********************-**-**

i ",..

.'
; NOTE:
,
;

44 ;

'SET' CQMMANDS If1PLENENT LOOICAL 'OR' FUNCTIONS
'RESET' COMMANDS IMPLEMENT LOOlCAL 'AND" FUNCTIONS

*********"'****..************-*********-****************-**-

45 .
46 ; BUFFERED MODE MUST BE SELECTED WHEN SELECTIVE RECEIVE 15 USED.

47 ;
48 .' CONNAN£> FORMAT IS: ''CO~Il'1AN£> (2 LTRS)" 'PAR. !Ii' 'PAR. 112' ETC.
49 .
5~ ! THE TRANSMIT FRAME COti~1AND FORl'1AT is: 'TF' 'A"e' 'BUFFER CONTENTS' .
.51 ;
NO LENGTH COUNT IS NEEDED. BUFFER CONTENTS IS ENDED WITH A CR.

'52 ;

53 ; .•****~************..************..***********************-*****-.......***
54 .•
55 j POLLF.£1 MOL':: WHEN POLLEt' MODE IS SELECTED (DENOTED BI' A +' .PROI'fT). IF
f

9-173

231311-001

.APPLICATIONS
56;

A SNRI'I-P OR RR(0)-P IS RECEII/ED, A RESPONSE FRAME OF NSA-F
OR RR(0H IS TRANSMITTED. OTHER COItlANDS OPERATE NORMALLY.

57 ;

62;
63 ; ********************-*******"'*****************************************
64;
11890
0090
0091
0091
0092
11893
0092
0020
01184
01188
0001
0@e2

65
66
67
68
69
70
71
72
73
74
75
76
77
78

; 8273 EQUATES
;
STAm EQU
90H
COMH73 EQU
90H
PARM73 EQU
91H
RESL73 EQU
91H
TXIR73 EQU
92H
RXIR73 EQIJ . 93H
mm EQU 92H
CPBF
EQlI
20H
TXINT EQU
04H
RXINT , EQI)
BSH
!XI RA EQU
91H
RXiRA EQU
02H

; STATUS REGISTER
; cdMi1AND REGISTER
; PARAMETER REGISTER
; RESULT REGI STER
; TX INTERRUPT RESULT REGISTER
; Rli INTERRUPT RESULT REGISiER
; TEST MODE REGISTER
; PARAMETER BUFFER FULL BIT
; TX INTERRUPT BIT IN STATUS REGISTER
; RX INTERRUPT BIT IN STATUS REGISTER
; TX I NT RESULT AliA ILABLE BIT
; RX INT RESULT AVAILABLE BIT

79;
II89B
009C
009D

I189E
0eec
0036

0086
2917
2£118

sa ; 8253 EQUATES
81 ;
82 MODE53 EQU
9BH
83 CNT053 EQlJ
9tH
B4 CHT153 EQU
9DH
85 CNT253· EQU
9EH
EQU
86 COBR
e00CH
87 MDCNT0 EQU
36H
0B6H .
813 .MDCNT2 EQU
89 LKBR1 EQU
2017H
90 LKBR2 EQU
2018H
91 ;
92 ; BAUD RATE TABLE:
.93 ;
·94 ;
95 ;
96;
97 ;
98;
99 ;
100 ;
101;
1132 ; S~7 EQUATES

; 8253 HODE WORD REGISTER
. ; COUNTER 0 REGISTER
; COUNTER 1 REGISTER
; COUNTER 2 REGISTER
; CONSOLE BAUD RATE (2400)
; MODE FOR COUNTER £I
; MODE FOR COUNTER 2
; 8273 BAUD RATE LSB ADR
; Bm BAUD RATE M58 ADR
BAUD RATE

. ****"'****
9600

LKBRi

"'****
*"'***
2E
00
5C
B9
72
E5
C9

4800

··2400
1290
600
390

LKBR2

90
00
01

02
05

103.i
00AS
eeA0
e0Al
00fI2
00A3
£leAS
·8208
8008

0862
41FF

0063
8061
81FF

1134 MODES7
1135 CHeADR
106 CHeTC
107 CH1ADR
1M CH1TC
109 STAT57
110 RXBUF
111 TXBIJF
112 DRDI'1A
113 RXTC
114 ENDMA
115.DTDMA
116 TXTC
117;

EQIJ
EQll
EQU
E~I.I

EQU
EQIJ

EQU
EQU
·EQU
EQU
EQIJ
EI)U
EQU

0ASH
0A0H
0A1H
0A2H
0f13H
eA8H
8290H
8000H
62H
41FFH
63H
61H
B1FFH

; B257 I'!ODE PORT
; CH0 (Rii) ADR REGISTER
! CHe TERMINAL COUNT REGISTER
; CHi (T~) ADR REGISTER
; CH1 TERMINAL COUNT REGISTER
; STATUS REGISTER
; RX BUFFER START ADDRESS
; TX BUFFER START ADDRESS
; DISABLE RX DMA CHANNEL, TX STILL ON
; TERMINAL COUNT AND MODE FOR RX CHANNEL
! ENABLE BOTH TX AND RX CHANNELS-EXT. WR, TX STOP
; DISABLE TX DMA CHANNEL, RX STILL ON
.; TERMINAL COUNT AND MODE FOR TX CHANNEL

9-174

23131 H)01

APPLICATIONS

0089
0389

13088
€t0S8

00CE
ee2?
3002

1~61F

05FB
075E
05B8
• 0:)5E8
@6C7

118
119
120
121
122
12]
124
125
126
127
128
129
B0
Hl
:132
1~1

134
135
136
137

i

8251A EQUATES

i

CNfL)l EW
89H
3mTS1 EQ:J
89H
n~[!5l
EQto
:38H
R:,;r.51 EG!li
88H
MC'E)1 EOU
0CEH
mD51 EQU
2iH
RD'T
EOI.'
02H
;
.: MONITOR 5lIBROIJTiNE EQUATES
:
GETCH EOLI
061FH
ECHO
EOt!
05F8H
VALDG EOU
075EI-I
GNVBN EGU
05BBH
CRLF
EQU
05EBH
N~lGIJT
EQIJ
06C7H
;
; msc EQUftTES

CONTROL flORD REGISTER
; STATUS REGiSTER
; T;~ DATA REGISTER
.: RX DATA REG! STER
. ~10DE 16X, 2 STOP, NO PARITY
; COMMAND, ENABLE TX&RX
; RXRD'I BiT

i

; GET CHR FRO~l KEYBOARD, ASCII IN CH
; ECHO CHR TO DISPLAY
; CHECK IF VALID DIGIT, CARRY SET IF VALID
; CONVERTS ASCI I TO HEX
.: DISPLAY CR, HENCE LF TOO
; CONVERT BYTE TO 2 ASCII CHR AND DISPLAY

138 .:
2eC0
000$
eee8
21300
2020
000D
fl00A
2004
28CE

2[0\113
20B

28013
0093

eeu
90??
131311
2015
2016
2027

139
1413
141
142
143
144
145
146
147
148
149

154
155
156
157
161

STKSRT
CNTLe
MONTOR
CHDBIJF
Ct1DBFl
CR
LF
R5T75
RST65
LCoADR
CNADR
RESBUF
SNRMP
RR0P
NSAF
RR0F
PRMPT
POLIN
DEMODE
;

162
163
164
165

;
;
; RAM STORAGE DEFINITIONS:
;
LOC
DEF

1513
151
152
153

EOU
Eau
Eau
EQU
EOU
EilU
EQU
EG!lJ
EQU
EQU
EQU
EQU
EI~U

EblU
EQU
EQU
EQU
EQU

EQU

20C0H
03H
e008H
20e0H
2020H
I3DH
BAH
20D4H
20CEH
2010H
2013H
280fJH
93H
11H
73H
l1H
2015H
2e16H
21327H

; STACK START
; CNTL-C EQUIVALENT
.; MONITOR
i START OF COMMAND BUFFER
; POLL MODE SPECIAL TX COMMAND BUFFER
; ASCII CR
;ASCII LF
; RST7. :5 .JUMP ADDRESS
; RST6. 5 JU~lP ADDRESS
; RE5lIL T BUFFER LOAD POINTER STORAGE
; RESULT BUFFER CONSOLE POINTER STORAGE
; RESLIL T BUFFER START - 255 BIITES
; SNRIH CONTROL CODE
i RR(0)-P CONTROL CODE
; NSA-F CONTROL CODE
; RR(0)-F CONTROL CODE
; PRMPT STORAGE
; POLL tl0DE saECTION INDICATOR
; DEMO MODE INDICATOR

*********************************************************"'*****************

166 ;
167
168
169
170

;
;
;
;

171 ;
172
173
177
179
180
181

;
;
;
i

;

2000-200F
2010-2011
2013-2014
21315
21316
2017
2018
2019
2020-2026
2B00-28FF

COMMAND BUFFER
RESULT BUFFER LOAD POINTER
RESULT BUFFER CONSOLE POINTER
PROMPT CHARACTER STORAGE
POLL ~lODE INDICATOR
BAUD RATE LSB FOR saF-TEST
BAUD RATE MSB FOR SELF-TEST
SPARE
RESPONSE COMMAND BUFFER FOR POLL MODE
RESULT BUFFER

i

182 ;

***"'****************************************"'***"'****************"'*******"'*
9-'175

231311-001

APPLICATIONS
183 .•
184 .: PROC-RAM START,
IS5 i
186 .' INITIALIZE 9253, B257, 8251A, AND RESET 9273187 i ALSO SET NORt1AL ~lODE, ANr. PRINT SIGNON MESSAGE
188.'
. ORG
189
B00H

0800

190
ewe 31CB20
e8e3386
8805 DJ9B
e887 JA172B
0BBA
080C 3R1820
080F D39C
0811 CD1AeB
0814 CD3ses
08li 3Ee1
0819 0392
081B 3E09
081!) r(~92
081F 3E2D
0821121520
0824 3E0e
13826 321620
0829 322729
9B2C 21R3ec
e82F CD920C

rmc

0832 21D420
0835 01egec
0838360
B8JA 21
083B 71
0S3C 23
ealD 713
e83E 21CE20
13841 91CEec
9844 36C3
9846 23
984771
9848 23
9849713
9B4A 3EiS
984C 30
984D FB

984E 219t!2B
9851221320
9S54 221020

191 START:

LXI

192
193

MVI
OUT

194

LDA

195
196
197
198
199

OUT
LDR
OUT
CALL
CALL

200

·MVI

291
292
203
204
285

OIJT
i'lVI
OUT
MYI
STA
Mill
SiR
STA

296
207
208
212

213

L;~I

CALL

SF, STK5RT
A, MOCNT0
MODE53
LKBR1
CNTBS3
LKBR2
CNT053
RXN1R
r.~m1A

.: INITIALIZE SP
.: 8253 MOf)E 5ET
.: 8253 MODE PORT
.: GET 8273 BAUD RATE LSB
; USING COUNTER 0 AS BAUD RRTE GEN
.: GET 8273 BIJRD RRTE MSS
.: COUNTER 0
; 1NITIALIZE 8257 RX DriA CHANNa
; IN ITIAl! ZE 8257 r..: DrlfI CHANIIEL
.: OUTPUT 1 FOLLOWED BY A
.' TO TEST MOr.E REGISTER
.: TO RESET iHE 8273

°

A,e1H
TEST73
A,00H
TESm

A, "-'
P~lPT

A,OOH
POLIN
DEMODE
H.• SIGNON
T'r'MSG

.' NORMAL MODE PROMPT CHR
.: PUT IN STORAGE
.: TX POLL RESPONSE INDICATOR
; 0 MEANS NO SPECIAL Til
.: CLEAR DE\'10 MODE
.: SIGNON MESSAGE ADR
.: DISPLAY SIGNON

214 .:
215 .' MONITOR USES JUMPS IN RAM TO DIRECT INTERRUPTS
216.'
H, R5T75
217
LXI
.: R5T7. 5 JUMP LOCATION USED BY MONITOR
LXI
S,RiiI
; ADDRESS OF RX INT ROUTINE
.218
M.• BGH
.: LORD 'JMP I OPCODE
219
MYI
; INC POINTER
229
INX
H
M,G
MOil
221
.' LORD Rill LSB
IN~:
H
; INC POINTER
222
M,B
223
MOil
.: LORD Rill MSB
224
LXI
H,RST65
i R5T6. 5 JUMP LOCATION IJ5ED BY MONITOR
B, IXI
225
LXi
.: ADDRESS OF TX INT ROUTINE
Mill
M,9C3H
.' LORD JMP' OPCODE
226
227
INX
H
.: INC POINTER
M,C
228
MOY
.: LOAD IXI LSB
INX
H
229
.' INC POINTER
M,S
230
MOil
; LOAD TXI 1'158
A,18H
231
MVI
.' GET SET TO RESET INTERRUPTS
SIM
.: RESET INTERRUPTS
232
; ENABLE INTERRUPTS
233
EI
234;
235 .: INITIALIZE BlJFFER POINTER
236 ;
I

237;
2..<8
239
240

un
SHL!)
SHLD

H,RESBUF
CNfIDR

LDADR

; SET RESIJLT BUFFER POINTERS
; RESlJLT CONStU POINTER
; RESlJLT LOfID POINTER

241 i
242 ; MAIN PROGRAM LOOP - CHECKS FOR CHANGE IN RESULT POINTERS, LlSRRT STRTUS,
OR POLL STRTUS
243.:

9-176

231311-001

APPLICATIONS

BS57
085A
0850
085E
0861

CDEBe5
3A1520
4F
CDF805
2A1320

13864 7(,
0865 2A1B20
0868 BD
0869 C2390A
e86C D889
086E E602
08713 C2iD0e
0871 3A1620
0876 A7
08,7 C24C139
1387A C36108

08?D CDm16
08813 CDF8e5

244 i
245 CHDREC: CALL
246
LDA
247
rl01!
248
CALL
249 LOOPIT: LHLD
250
f101/
251
LHLD
CMP
252
253
JNZ
259
IN

260

A~H

261

-INZ
LDA
ANA
JHZ
Jt'IP

262
263
264

265
266
267
268
269
270
271

.

.,~~

(~

13883 79

2i~

0884
0886
\:l88S
0888
OS8E
08913

274
275
276

@895
0898
089A
0890
089F
08A2
08A.1
(l8A?
eSA9
e8AC

FE52
CAAF0S
FE52
CAD70S
FE.17
CAFF98
FE54
CAOE09
FE41
(A2209
FE5A
CA3109
FE0:;
rABSeO
0m
CDF80'3
C35708

08AF
eSB2
0885
08B6

GDiF06
W=805
79
FE4F

;B93

0888 CR5N19
0888 FE5?
08S('
B8C€!
138(2
08C5
~8C7

tlBeA
Bece
08CF
08rJ1

CA6709
FE44
CA7l€!9
FE50
CADS09
FE52
CA000B
FE42
Cil7809

CRLF
PRMPT
C,A
ECHO
CNADR
A,L
LDADR
L
DISPY
STAT51
RDII
GEW1D

POLIN
A
T~;POL

LOOPIT

; DISPLAY CR
i GET CURRBH PROMPT CHR
.: l'IOVE TO C
,: ()! SPLAY IT
i GET CONSOLE PO INTER
.: SAllE POINTER LSB
; GET LOAD POINTER
.: SArlE LSB?
i NO, RESULTS NEED DISPLAYING
illES, CHECK KEYBOARD
i CHR RECEIVED?
; rlUST BE CHR SO GO GET IT
; GET POLL MODE STATUS
;IS IT 0?
; NO, THEN POLL OCCURRED
iIiES.• TRII AGAIN

i
;
i COtlHAND RECOGNIZER ROUTINE
;
;
GEW1D: CRLL
GETCH
ECHQ
CALL
A.. C
HOIl

T~

-"

278
279
280

CPI
JZ
CPI
JZ
CPI
JZ

SDWN

i GET CHR
.: ECHO IT
.; SETUP FOR COMPARE
; R?
i GET ti0RE
.;5?
; GET MORE

"13"
GDWN

; GET MORE

iR'
RDWN
-'5"

;G?

CPI

'r

;T?

281
282
283
284

J2
CPI
,]2
CPj

TDWN

285
290
291

JZ

Crl0DE

CPI
JZ

rl0NiOR

; GET MORE
;A?
; GET t10RE
.: Z?
; 'IES, GO CHANGE rIO[JE
; CNTL-C?
; E;m TO rlONITOR
.' PRINT?
.' DI SPLAY IT
.' LOOP FOR CONI1AND

292 ILLEG
293
294
295
2'''6 RDWN:

"W
ADWN

. z,.

WILe

Wll

C, /.;,,'

CALL
IN?

ECHO
i]'lDP.EC

CALL
CALL
MOil
CPI
J2

;ETCH
i::CHO
A,C
'0-Rome-

101

CPI

'5'

],02

..Ii:
CPI
JZ
CPI

R~CI'ID

; GET NE~';T CHR
,ECHO Ii
.; SETUP FOR CONPARE
;O?
; RO COt,lr'R/'ID
; S?
; RS COt1MAND

"[).'

;[)?

P.DCtlD
'p ..

: RD COMliAND
; P?
: RP COt'U1AND
;R?
; START OVER
:8?
. RB COMt'lANII

297
298
299
208

203
3@4

305
306

12

307
30E:

CPI
E

3t)9

CPI

310

JZ

RPCtlC'
"R'
START
'8/
RBCt1D

9-177

231311-001

APPLICATIONS
9SD4 ClA7es
esi>7
0BDA
0BDD
1l8DE
esEIl
9SEJ
B8E5
1l8E8
08EA

CD1F96
CDFS05 .
78
FE4F .
CAA609

FE53

88EF
esF2
Il13F4
0SF7
esF9
08FC

CAB009
FEs2
CABA09
FE50
CAE209
FE42
CAB509
FE4C
CABF99
GA7es

IlBFF
0902
9905
9906
0908
0geB

CD1F96
COF805
78
FE52
CAC409
C1A79S

08EP

311
312
:$13 SOWN:
314
315
316
317
318
319
320

321
322
323
324
325
326
327
328

JMP

ILLEG

i ILLEGAL, TRY AGAIN

CALL
CALL
MOY
CPI
JZ
CPI
JZ
CPI
JZ
CPI
JZ
CPI
JZ
CPI
JZ
JMP

GETCH
ECHO
A,B
'0,'
SOCI'ID

"'pl
SPCMD
'B'
saCI'ID
'L'
SLCMD
ILLEG

i GET NEXT CHR
iECHO IT
; SETUP FOR COMPARE
iO?
i SO COftIAND
is?
i sS cOI1I1AiID
iR?
; SR COI'If'IAND
iP?
i SP COMMAND
iB?
i sa COMI1AND
iL?
; SL COI'll1AND
; ILLEGAL, TRY AGAIN

CALL
CALL
MOV
CPI
JZ
JMP

GETCH
ECHO
fl..B
'RJ'
GRCI'ID
ILLEG

; GET NEXT CHR
i ECHO IT
.; SETUP FOR CO!1PARE
;R?
.' GR COI'II1ANO
; ILLEGAL.· TRY AGAIN

CALL
CALL
MOil
CPI
JZ
CPI
JZ
JNP

GETCH
ECHO
A,B
'F'.
TFCI'ID

; GET NEXT CHR
; ECHO IT
; SETUP FOR COMPARE
,:F?
.:TFCOMMAND
iL? '
,: TL· CONMAND
.: ILLEGAL, TR~' AGAIN

CALL
CALL
MOil

GETCH
ECHO
fl,.S

cpr

iF'

JZ
JMP

AFCI'ID
ILLEG

'5'
SSCI'ID

'R'

SROO

329
339 GOWN:
331

332
3JJ

334

:ns
336

090E
0911
0914
0915
0917

CD1FB6
C[)F8il5
78
FE46
CAEC09
~9ifl FE4C
~1C CA9909 •
1il91F C3A708
0922
0925
0928
0929
092B
992E

CMFB6
C[)FS0S
78
FE46
CACE09
GR79S

0931 F3
0932 3A1520
0935 FE2D
8937 C24309
093A 3E2B
093C 121520
093F FB
0949 CJ5708
1l94:1 3E2D
0945 321520
0948 FB
9949 C3570S

:m

TOWN:

33S

:m
349
341
342
34J
344
345
346 ADWN:
347
348
349
359
351
352 ;
353 ,: RESET
354 ;
355. COODE.
356
357
358
359
369
365

366
367 514:

3613
369
370
371-

'V
TLCMD
ILLEG

; GET NEXT CHR
;ECHO IT
; SETUP FOR COMPARE
iF?
; AF COI'll1AND
i ILLEGAL TRY AGAm

POLL MODE RESPONSE - CHANGE PROMPT CHR AS INDICATOR

DI
LDR

PP.~lPT

JNZ

S;!
A, '+'
PRMPT

cpr

~1I/1

STA
EI
.]HP
Mill
STR
EI
Jf1P

~-

•.

CfIDP£C
A, ,-,'
PR~IPT

CMDREe

,: &ISABLE INTERRUPTS
; GET CURRENT PROMPT
i NORNAL MOVE?
; NO, CHANGE IT
; NEW PROMPT
; STORE NB~ PROMPT
; ENABLE INTERRUPTS
.: RETURN TO LOOP
.: NEW PRO~IPT CHR
; STORE IT
; ENABLE INTERRUPTS
; RETURN TO LOOP

:m;

9-178

231311-001

APPLICATIONS
373 ; TRANSMIT ANSWER TO POLL SETUP

374
094C
094E
0951
0954
13955
0957
095A

3E00
321620
216108
E5
13604
212020
C3FF9A

i

382 TXPOL: HI! I
A, BBH
384
STA
POLIN
385
LXI
Hi LOOPIT
386
PUSH
H
B, B4H
387
Mill
388
L:~I
H, CMDBFl
:;;89
J~fP
COMM2
390 ;
391,:
392 ;
393 ; COt-1MAND IMPLEI-1ENTING ROUTINES

; CLEAR POLL INDICATOR
; INDICATOR ADR
; SETUP STACK FOR COMMAND OUTPUT
; PUT RETURN TO CMDREC ON STACK
; GET i OF PARAMETERS READY
; POINT TO SPECIAL BUFFER
; JU~lP TO COMMAND OUTPIJTER '

394 i

095D
095F
13961
0964

13967
0969
0968
096E

0971
0973
0975
e978

06131
13E51
CDE50A
C5708

0601
0E60
CDE50A
C5708

0600
OEC5
CDE50A
C5708

097B e6~3i
097D 13E64
097F CDE513R
0?82 (35708

0985
13987
g989
0?8C

0601
0EA4
CfoE50A
C:;57e:3

.398F 0604

0991 0EC2
8992 Ci)E50A
0996 C357ti8

395,:
396 ; RO - RESET OPERATING 110DE
397 ;
B,01H
398 ROCI1C': Mill
(,51H
399
~lVI
4130
COMI-1
CALL
401
JMP
CI'IDREC
402,:
403 ; RS - RESET SER I AL IiO NODE
404 ;
405 RSCMD: MVI
8.- 01H
406
MVI
C,-60H
407
CALL
C01'1H
408
JI1P
CI1DREC

; # OF PARAMETERS
,: COt1MAND
; GET PARA~lETERS AND ISSlJE COMt1AND
; GET NEXT CO~l~IAND
CON~lAND

;!I OF PARAMETERS
; COMMAND
; GET PARAMETERS AND ISSUE
,: GET NEXT COMMAND

COI~MAND

489.:
. 410 "RD - RECEIVER DISABLE comlANr,
411 ,:
412 RDCt1D: Mill
B, B0H
OF PARAMETERS
4B
MI/I
C,-0e5H
.: CO~1t'1AND
414
COl-1M
CALL
,: ISSIJE COMI1AND
415
J1'lP
UIDREC
; GET NEXT Cot-1I'1AND
416 ;
417 .: RB - RESET ONE BIT [RAY COfiMAND
418 ,:
419 RBC~ID: MVI
B,01H
,: # OF PARAt-1ETER5
420
~IVI
C,64H
.: COMMAND
421
CALL
COl'1fl
.: GET PARAMETER AND ISSUE COl11iAND
CM[!PEC
422
JMP
.: GET NEi;T COliHAND
42} .:
424: SB - SET ONE BIT D&AY COt1~IANr,
425 ;
B,01H
426 SBCNO: t'1V I
,: i OF PARAMETERS
427
~IVI
C,- 0A4H
.: COM~IAND
(01111
.: GET PARAI'1ETER AND ISSIJE CO~1t-1AND
428
CALL
429
J~IP
CNDREe
.: GET NEXT COMMAND
43ti ;
4]1: SL - SELECTIVE LOOP RECEIVE COMI-1RNf,
432 j
431 SlC11r,: MVI
B, B4H
.: II OF PARA~IETERE5
434
I-IVI
C, BC2H
; COMMAflD
435
CALL
COMN
i GET PARAMETERS AND ISSLIE Cot1MAND
436Jto!P
CMDREC
,: GET NEXT COflMAt'ID

,: *

437

i

';38 ; iL - TRAN51HT LOOP CO/-IMAND

9-179

231311-001

APPLICATIONS
439 ;

0999 219929
999C 0602
099E J6CA
/ 09A9 21132213
09A3 C}F6B9

B9A6
09A8
@9AA
09Ar.·

0601
BE91
CDES0A
C35708

09B0 0601
B9B2 0EA0
0984 CDE50A

0967 (35708

09BA 06@4

09BC BEei
09BE CDE50A
139C1 C35708

09C4 0602
09C6 0EC(J
09C8 CDE50A
09C8 C15708

09CE
09[)0
09D2
@9D5

136013
0EeG
CDE50A
CJ570B

B9D8 0601
09llA om
09DC CDE5€lA
09DF (357138

09E2
09E4
09E6
09E9

0601
0EA3
Cl,ESOA
C35708

440 TLCMD: LX I

441
442

MVI
MVI
LXI
JMP

H, CMDBUF
B, B2H

M, OCAH

; SET COMMAND· BUFFER POINTER
; LOAD PARAMETER COUNTER
; LOAD COMMAND INTO BUFFER
; POINT AT ADR AND CNTL POSITIONS
; FINISH OFF COMMAND IN TF ROUTINE

H, CMDBUF+2
443
444
TFC~tD1
445 ;
446: 50 - SET OPERATING MODE COMMAND
447 ;
B.,a1H
448 SOCMD: Mill
.: II OF PARAMETERS
C,91H
; COMMAND
449
MVI
COtlli
.: GET PARAtiETER AND ISSUE COMMAND
450
CALL
.IMP
451
CMDREC
; GET NEXT COI1I1AND
452 ;
453 ; S5 - SET SERIAL 1/0 COMMAND
454 ;
B.,01H
455 55ntD: MVI
OF. PARA~tETER5
456
C, 0AeH
.: COMMAND
Mill
; GET PARAt,tETER AND ISSUE CO~tMAND
457
CALL
COM~t
JMP
CMDREC
.: GET NEXT cot'tMAND
458
459 ;
460 ; SR - SELECTiVE RECEIVE Cot1MAND
461 ;
B,@4H
462 5RnID: ~t\!l
; # OF PARA~tETERS
~1I!I
C,Be1H
;COt1tolAND
463
464
.: GET PARRt1ETERS ANc. ISSUE CO~lI"1AND
CALL
COMM
465
JMP
CMDREC
; GET NEI~T COt1MAND
466 ;
467 .' GR - GENERAL RECEiVE COM~IAND
468 i
469 GRCt'I[): MVI
B. 02H
; NO PARAtofETERS
~!Vl
C.• 0C0H
4713
.: COMMAND
471
; ISSUE CONtiAND
CALL
COt'IM
.mp
472
: GET NE'AT CO~R1AND
Ct1DREC
473 j
474: AF -'ABORT FRAt'tE CONt1AND
475 ;
B,0eH
; NO PARAMETERS
476 AFCMD: Mill
C,OCCH
477
; COMMAND
tm
478
CALL
COrfto1
.: ISSUE COMMAND
Jt,tP
; GET NEXT COMMAND
479
CMCoF.:EC
480 .:
481 ; RP - RESET PORT COI'lt'lAND
482.:
8. 01H
; # OF PARRMETERS
483 RPCMD' rWI
C,63H
484
; Cot1MAND
t'WI
485
CALL
; GET PARANETER AND ISSUE COM~lAND
Cot1M
486
J~IP
CNDREC
; GET NEXT COMMAND
487 ;
488 ; 5P - SET PORT COt'IMAND
489 ;
490 speND: t1IJI
B,01H
; # OF PARAi'tETERS
C, (lA3H
ttVl
491
.: COMMAND
492
CALL
CONN
; GET PARAMETER AND ISSLIE COt'l~tAND
493
: GET NEI~ CONMAND
JMP
ct1DREC

.: *

494 ;
495 .: TF - TRANSMIT FRAME COMMAND

496 ;

9-180

231311-001

APPLICATIONS
09EC
09EF
09F1
09F]
09F6
09F7
09F8
B9FB
99FE
0AB1
0A02
0At31
0A04

210020
0602
]6(8
2102213
78
A7
CR0i0R
CDRDBA
DAA708
2]
05
77
C3F609

BA07
BRBA
BABD
0A@E
I)Al1
BAi5
BR16
0A17
0R18
eRI8
13AW
eA2(l
0A21
0A24
OA25
OA28
0R29
0A2A
0A28
OA2D
0A30
OA]1
eRn
eRB
0A36

210080
010900
C5
CVADeA
DR180A
77
21
(1
03
DOlleA
FEaL'
CA240R
(1
GA7eS
(:1
210120
71
23
70
0604
21360A
C5
E3
C5
C3FB0A
G5708

eR::<9
0A3B
0A3E
0A3F
0A40
eA42
0A44
BA47
0A4A
BA4D
0A4E
BA4F

1605
2AB20
E5
7E
E61F
FE0C
DA620A
21C3eC
CD92BC
E1
7E
CDC706

@AH

497 TFeND:
498
499
51;10
5€11 TFCr'lr,l:
592
50]
504
505
506
507
508
509
51B
511 TBlIFL:

L~:r

11\:,1
MVI
L;';I
l'lOV
ANR
JZ
CALL
JC
INX
DCR
t10V
JI1P
L:~I

512
L~:I
513 TBUFL1: PUSH

H.• CMDBUF
B. 02H
1'l.0C8H
H. CI1C'BUF+2

A, B
A
TBLIFL
PARIN
ILLEG
H
B
11 . A
TFCi'ti)i

H, TXBUF
8, OBeaH
B

; SET CONr1AND BUFFER POINTER
.; LOAO PARAMETER COUNTER
i LORD cor1NAND mTO BUFFER
i POINT AT ADR AND CNTL POSITIONS
.' TE5T PARAMETER COUNT
'IS IT ~p
.: 'rES. LOAD TX DATA BUFFER
.' GET PARAr1ETER
; ILLEGAL CHR REnJRNED
.; INC COMMAND BUFFER POINTER
i DEC PRRAt'lETER COUNTER
.; LOAD PARAt1ETER INTO COl'1t'lAND BUFFER
.; GET NEXT PARANETER
.; LOAD Tii DATA BUFFER POINTER
; CLEAR BC - BYTE COUNTER
; SAVE BYTE COUNTER
"GET DATA, ALIAS PARAMETER
; NA'r'BE END I F ILLEGAL
i LOAD DATA BVTE INTO BUFFER
.; INC BUFFER POINTER
; RESTORE BYTE COUNTER
, INC S'r'TE COUNTER
; GET NEXT DATA
i RETURNED ILLEGAL CHR CR?
; YES, THEN TX BUFFER FULL
,; RESTORE B TO SAVE STACK
; ILLEGAL CHR
; RESTORE BYTE (:OlJl-ITER
; PO I NT I NTO COMMAND BUFFER
.: STORE BYTE COUNT L5B
; INC POINTER
.; STORE B'rTE COUNT ~lSB
; LOAD PARAMETER COUNT INTO B
; GET RETURN ADR FOR THIS ROUTINE
i PUSH ONCE
,; PUT RETURN ON STACK
; PiJSH Ii 50 CMDOiJT CAN USE IT
.; 155UE CONMAND
; GET NEXT COt·1t1AND

PAR IN
514
CALL
515
JC
ENCoCHK
NOV
t·l . A
516
INX
517
H
518
POP
B
519
INX
B
520
.J~lP
TBUFLi
521 ENDCHK: CP I
CR
522
JZ
iBIJFFL
POP
523
B
524
Jt1P
ILLEG
52S TBUFFL: POP
B
L;,:r
526
H, CHDBlIF+l
r10V
527
t1..C
528
H
INI':
529
t'IOV
t1..8
B,04H
53i.l
MVI
H, TFRET
531
L:~I
532
PUSH
B
53J
XTHL
534
PUSH
B
Jt1P
G1DOUT
535
536 TFP.ET: Jt1P
Gl'lDREC
537 .'
539 i
539 ; ROUTINE TO DISPLAY RESULT IN RESULT BUFFER WHEN LOAD AND CONSOLE
5413 ; PO I HTERS ARE DIFFEP..ENT.
541 .'
542;
D,.aSH
543 DISPY: ~1YI
,; D IS RE5ULT COUNTER
544
LHLD
CNADR
; GET CONSOLE POINTER
545
PUSH
H
.: SAllE IT
A,M
546
; GET RESULT IC
MOV
547
ANI
; LIMIT TO RESULT CODE
1FH
548
CPI
eCH
; TEST IF RX OR TX SOURCE
; CARRY, THEN RX SOURCE
549
.JC
RXSORC
H, TXlfo15G
550 TXSORC: LXI
i TX INT MESSAGE
CALL
; DISPLAY IT
551
TYMSG
; RESTORE CONSOLE POINTER
552 DI5PY2: POP
H
553 DI5PY1: ·t101/
A,M
; GET RESULT
CALL
; CONVERT AND DI5PLAY
554
NMOUT
9-181

231311-001

APPLICATIONS
0A52
0A54
\lAS7
BA58
0AS9
!:lA5C
0R5F

IJE20
CDF8li5
2C
15
C24E0A

0A62
0A65
eA6S
0A69
0A6A
\lAm
tlR6F
OA72
0A73
0A74
13A75
OA77
13A?A
!lA7C
0A7F
0A80
BAR?
0A86
0A89
0Ase
0A8D
eASE
0A8F
0A92
0A93
BA94
BR9?
0A99
0A9C
\lA9r.
BA9E
0A9F

21BBec
CD920C
El
7E
CDC706
0E2@
CDF805
2C
15
7A
FE04
CAA20A
FEIB
CAA7BA
A7
C2690A
221320
CDEBB5
210082
C1
78
B1
CA570S
7E
C5
CfoC706
@E20
CDF805
C1
138
23
C381J0A

22me

cmes

0AA2 4E
BAA] C5
0AA4 C37FfJA
13AA7
13RA8
0AA?
BAAA

C1
46
C5
C37F0A

555
556
557

558
559

~1I/I

f'-,' .'

CALL
INR
DCR
JNZ
SHLD

ECHO
L
D
DISP'I1
CNADR

I

; SP CHR
; DISPLAY IT
,: INC BUFFER POINTER
; DEC RESULT COUNTER
,: NOT DONE
,: UPDATE CONSOLE POINTER
; RETURN TO LOOP

560
561
J~lP
C~lDREC
562 ;
563 ;
564 ; RECEIVER SOURCE - DISPLA'I RESULTS AND RECEYIEBUFFER CONTENTS
565 ;
566 ;
567 RXSORC: LXI
H, RXHISG
,: RX INT MESSAGE ADR
568
CALL
TI'MSG
,:D rSPLA'I MESSAGE
569
POP
H
i RESTORE CONSOLE POINTER
A,M
57!HXS1:
MOV
; RETRIEVE RESULT FROM BUFFER
571
CALL
NMOUT
; CONVERT AND DISPLAY IT
CI !
572
till I
"ASCII 5P
GALL
573
ECHO
i DISPLAY IT
574
IfIR
; INC CONSOLE POINTER
L
, C,CR
575
D
; DEC RESULT COUNTER
MOV
A. D
~76
; GET· SET TO TEST COUNTER
cpr
577
04H
; I S THE RESULT RIP
578
JZ
R0PT
; YES, 00 SAVE IT
e]H
579
CPI
; IS THE RESULT RP
58e
JZ
R1PT
.: YES.. 00 SAVE IT
581 RiiS2:
ANA
A
; TEST RESULT COUNTER
582
JNZ
RX51
.: NOT DONE
GET NEXT RESULT
Sin
SHLD
CNADR
; DONE" SO UPDATE cm50LE POINTER
584
CALL
CRLF
" DI SPLA'r' CR
585
m
H. RXBUF
"POINT AT RX BUFFER
586
POP
B
.: RETRIEVE RECEIVED COUNT
587 RXS3: MOl!
A,B
.: IS COUNT 0?
588
ORA
C
589
JZ
CMDREC
; YES.. GO BACK TO LOOP
590
~10V
A. M
; NO, GET CHR
591
PUSH
B
; SAVE BC
592
NMOUT
CALL
; CONYERT AND DISPLAY CHR
593
MYI
; ASCII SP
c. ' "
594
CALL
ECHO
,: DI SPLAY IT TO SEPARATE DATA
595
POP
B
; RESTORE Be
596
DeX
B
; DEC COUNT
597
INX
H
; INC POINTER
598
RXS3
IMP
; GET NEXT CHR
599
6!3e RBPT:
~lOV
C. M
; GET RB FOR RESULT BUFFER
601
PUSH
B
; SAVE IT
,:RETURN
602
niP
RXS2
603
604 R1PT: POP
j GET R0
B
B,M
605
MOV
; GET R1 FOR RESULT BUFFER
6e6
PUSH
B
j SAVE IT
607
JI'1P
RXS2
"

'Tn

613a ;
699 ;
6113 ;
611 ,; PARAMETER INPUT - PARAMETER RETURNED IN E REGISTER

612

j

9"182

231311-001

APPLICATIONS
0AAD C5
t1AAE 1601
eABe CD1Fe6
BAB: C[fS€lS
BAB6 7~
eAB7 me
0AB9 C2E00A
BABG CD1F06
0ABF CDFS05
0AC2 CD5E07
eACS D2Ee0A
€lACe (DBBeS
eACS 4F
BAee 7A
OACV Ar
BACE CADCOM
BAD1 1S
0AD2 AF
ilA(o:$ 79
0AD4 17
0A[:'5 17
BA[,'; 17
BAD? 17
BANl5F
9AD9 C3BC0A
€lADe 79
0ADD B3
!lADE (1
0ADF C9
9AE0 79
eAE1 37
0AE2 C1
0AEJ C9

€lAE4 CF

9AE5 219020
0AEB C5
0AE9 71
0AEA 79
0AEB A7
0ftEC CAFBIIA
9AEF CDAD0A
0AF2 DAA711S
9AF5 23
IIAF6 05
9AF777
SAF9 C3EA0A
SAFB 218828
8AFE C1

613 ;
614 PARIN:

PUSH
B
615
MVI
D,elH
616
CALL
GETCH
6i?
CALL
ECHO
A,e
618
liO\l
619
CPI
620
JNZ
PARINi
621 PARIN3: CALL
GETCH
622
CALL
ECHO
623
CALL
VALOG.
JNC
PARINi
624·
625
CALL
CNVBN
C,A
626
MOil
A,D
627
MOY
628
ANA
A
629
JZ
PARIN2
630
OCR
D
6~1
XRA
A
A,C
6~2
MOil
m
RAL
634
RAL
RAL
635
636
RAL
637
MOIi
Ed'!
JI4P
PARIN3
638
A,C
639 PARIN2: MOV
646
CPR
E
~41 .
POP
B
642
RET
A,C
643 PARIN1: MOil
644
STC
POP
B
6~5
646
RET
647;
648.'
649 ; JUMP HERE IF BUFFER FULL
650 ;
651 BUFFUl: DB
8CFH
652.'
653 ;
654 .' COMI'IAN[l DISPATCHER
655 ;
656 ;
657 COrtr: LXI
H.• CI'IDBUF
659
PUSH
B·
tI,e
659
MOY
A,B
660 COHM1: MOY
661
ANA
A
662
JZ
CMOOUT
663
PRRIN
CALl
664
JC
ILlEG
H
665
INX
666
OCR
B
M,A
.667
t1011
JI1P
668
COMtI1
669 CI1DOlJT: LX'I
It CI1DBUF
POP
B
678

9-183

; SAVE Be
; SET CHR COUNTER
; GET CHR
; ECHO IT
; PUT CHR IN A
;SP?
; NO, ILLEGAL, TRY AGAIN
; GET CHR OF PARAMETER
i ECHO IT
.; IS IT A VALI& CHR?
; NO, TRY AGAIN
; CONVERT IT TO HE:~
; SAVE IT IN C
; GET CHR COUNTER
;IS IT 8?
i YES, DONE WITH THIS PARAMETER
; DEC CHR COUNTER
i CLEAR CARRY
i RECOVER 1ST CHR
i ROTATE LEFT 4 PLACES

i SAllE IT IN E
; GET NElIT CfiR
;200 CHR IN A
; COI1BINE BOTH CHRS
i RESTORE BC
; RETURN TI). CAll ING PROGRAtI
i PUT ILLErA CHR IN A
; SET CARR\, AS I LlEGAL STATUS
;RESTORE BC
; RETURN TO CALl ING PROGRAI'!

; EXIT TO MONITOR

; SET POINTER
iSAVE Be
i LOAD COItIAND INTO BUFFER
; CHECK PARAMETER COlMER
; IS IT II?
; YES. GO ISSUE COIIIfN)
; GET PARAl'lETER
; IllEGAL CHR RETURNED
; INC BUFFER POINTER
; DEC PARAMETER cOuNTER
; PARAI'IETER TO BLfFER
; GET NEXT PARAMETER
; REPOINT POINTER
; RESTORE PARAtlETER cw.r

231311-001

APPLICATIONS
IlfFF DB90
0B81 87
. 2 DAFF0fI

9B95 7E
8B86 DJ98

eees 7S

9B99 A7
8B0fICB
0B8B 23
9BOC 95
0B0D DB99
8B0F E628
8811 C2OO8B
9814 7E
!!Bi5D191
!!B17 C30S0B

!!BiR lE62
!!BiCDlAS
!!BiE .810082
8821 79
!1822 D3R0
!!B24 78
!!B25 D3A!!
ee27 01FF4i
!!B2A 79
!!B2B D3A1
ee2[1 7S
!!B2E D3A1
!!Bse lE6l
8832DlAS
!!B34 C9

8815 lE6i
0937 D3R8
!!B~ e108S0
0B3C 79
!!B1D DlA2
!!B3F 7S
8940 D3A2
11842 01FF81
11845 79
IlB46 DJAJ
!!B48 7S
8849DJAJ
IIB4B lE6J
IIB40 D3A8
!!B4F C9

671 COI1PI2:

672

m

IN
RLC
JC
I10V
OUT
I'IOY

674
675
676 PARi:
67i
RNA
. RZ
678
INX
679
6se
DCR
681 PAR2:
IN
682
ANI

683
6S4

1HZ
I10V

6B5

OUT

686
687
688
689
698
691
692
693
694
695

JI'IP

STAm

COIM2
A,i'!
COI'II'In
A,B
A
H

B
STAm
CPBF·
PAR2

R,W
PARK7l
PARi

; READ 8273 STATUS
i ROTATE CBSY INTO CARRY
; WAIT FOR OK
; OK, IIOYE COltlflM) INTO A
; OUTPUT COIIIfH)
; GET PARAIIETER COIJIT
;ISI18?
.; YES, DOt£, RETURN
; INC COfIIIANI) BUFFER POINTER
; DEC PARRltETER COUNT
.i READ STATUS
; IS CPBF BIT SET?
; IlAIT TIL ITS e
; OK, GET PARAIIETER FROtI Bf.fFER
; OUTPUT PRRAIIETER
i GET NEXT PARAI1ETER

i

;
; IN rTIALIZE AND ENABlE RX DKA CHANNEL
;
;
A, DRDI'IA
RXDIIA: t1YI
; DISABLE RX DKA CHAIf£L
OUT
HOOE57
i 8257 PIJDE PORT
B, RXI3I.F
LXI
• RX BUFFER START FH>DRESS
R,C
!'lOY
; RX BUFFER LS8
OUT
CH!!ADR
; CHI.! ADR PORT
MO\I
R.B
i RX BUFFER "58
OUT
CHeADR
i CIIIl ADR PORT
B,RXTC
LXI
i RX CH TEERI'IINAL COUNT
A,C
I'lO\l
i Rli TER"INAL COUNT LSB
OUT
CHllTC
; CIIIl TC PORT
!tOy
A,B
; RX TERI'IIIR. COUNT KSB
;CHI) TC PORT
OUT
CIIIlTC
!'IVI . A,ENDM
i ENABLE DKA IllRD
; 8257 /lODE PORT
OUT
I1ODE57

696
697
698
699
7ee
781
782
783
7!!4
785
706
RET
le7 ;
708 ;
799 ; INITIALIZE IN)
710.
711 ;
712 TliOIIA: 11'11
713
OUT
714
LXI
715
KOY
716
OUT
717
"OY
7tS
OUT
719 TXDIIA1: LXI
720
i'IOY
721
OUT
722 '
IKIY
723
OUT
724
Ift'I
725
OUT
726
RET
727 ;
728 ;

;RETlJRN

EffIBlE TX DItA CHAIIEL
A,DTDKA
KODE57

B, TliBlf

R.C

CH1ADR
f!.B
CH1fI)R

B.TXTC
/!.C

CHiTC
A,B

CHiTC
f!.ENltIR
IIOOE57

; DISABLE TX DI1A CHIHIEI..
; 8257 IO)E PORT
; TX BUFFER START ADDRESS
; TX IIlfFER LSB
; CHi ADR PORT
;TX BlfFER i'ISII
; CHi AM PORT
; TX CH TERltIIR. ctIIMT
; TX TERltIrR. COUNT LSB
.CHi TC PORT
; TX TERltIIIIL COUNT i'ISII
;CHi TC PORT

; ER.E DIll

QI)

; 8257 IIOOE PORT

!RETURN

9-184

231311-001

APPLICATIONS

acee

0eoa E5
eC01 F5
0C02 C5
acm D5
0ce4 3E62
0C06 D3AB
13C08 3E1B
oe0A 30
BceB 1604
0C0D 2A1020
0W3 E5
13C11 E5
0C12 45

eCB 2AB20
aC16 04
OCl? 78
OC1S SD
eC19 CAE40A
0Cle 15
aC1D C2160C
eC20 1605
13C22 E1
0C23 DB90
0C25 EG08
13(:27 CA390C
QC2A DB90
0C2(: EGfJ2
€tC2E CA230C
0G1 DB93
0en 77
0C42C
00515

006 G3230C
13C9 7A
0C3A
GCB
00E
0(40
OC41
0C42
0C45
I3C48
0C4B
OC4D

A7
CA450C
3600
2C
15
C3390C
2211320
3A152fl
FE2D
CAS5ec

0C50 E1
0C51 7E

729 ; INERRUPT PROCESSING SECTION
ne;
731
ORG
aceSH
732 ,:
7Il i
734 ; RECEIVER INTERRUPT - RST 7. 5 (LOC 3CH)
735;
736 RXI:
PUSH
; SAllE HL
H
737
PUSH
; SAVE PSW
PSW
PU5H
73B
B
; SAVE BC
739
PUSH
; SAllE DE
D
740
A, DRD~IA
; DISABLE R~: DMA
t'I'v'I
741
OUT
MODES?
; 8257 MODE PORT
742
tWI
A,18H
; RESET RST7. 5 FIF
743
sm
744
D.,04H
; D IS RESULT COUNTER
t1111
745
LHLD
; GET LOAD POINTER
LDADR
746
PUSH
H
; SAVE IT
747
PUSH
H
i SAVE IT AGAIN
folO','
B,L
748
; SAVE LSB
749
,: GET CONSOLE PO INTER
LHLD
CNADR
750 RXI1:
INR
B
i BUMP LOAD PO INTER LSB
A,S
751
~10V
.: GET SET TO TEST
752
.: LOAD=CON50LE?
UIP
L
i','E5, BUFFER FULL
753
BUFFiJl
JZ
754
; DEC COUNTER
DCR
D
755
i NOT DONE, TRI' AGAIN
mz
RXI1
D,05H
756
~IVI
i RESET COUNTER
757
POP
H
i RESTORE LOAD PO INTER
,
758 RXI2.
STAm
; READ STATUS
IN
759
RXINT
.: TEST Rg INT BIT
ANI
760
i [lONE., GO FINISH UP
JZ
RXE
761
; READ STATUS AGAIN
IN
STAm
762
ANI
RXIRA
; IS RESULT READY?
;ND., TEST AGAIN
763
JZ
RXI2
764
; YES, READ RESIJLT
IN
RXIR7:1
765
N,A
t10V
i STORE IN BUFFER
766
INR
.: I NC BUFFER PO INTER
767
OCR
,: DEC COUNTER
C'
768
JMP
RXI2
; GET MORE RESULTS
A, r,
769 R:m: t'10',,..
; GET SET TO TEST
770
ANA
A
.' ALL RESULTS?
R;~I4
; I'ES, 50 FINISH UP
771
JZ
t'1.,00H
772
~1VI
.:NO. LOAD 0 TIL DONE
(I
INR
,: BUt'IP POINTER
L
774
DCR
i DEC COIJNTER
D
irS
,: GO AGAIN
J~IP
RXI3
776 RXI4:
,: UPDATE LOflD POINTER
5HLD
LDADR
777
LDA
PRMPT
.' GET MODE !ND I CATOR
.'_"
778
CPI
i NORMAL MODE?
779
; YES, CLEAN UP BEFORE RETURN
RinG
JZ
780 i
781 i
POLL t'10DE 50 CHECK CONTROL BI'TE
782 ;
IF CONTROL IS A POLL SET UP SPECIAL TX CONMAND BUFFER
783 ,:
AND RETURN ~HTH POLL INII I CATOR NOT 0
?N ,:
785
POP
H
i GET PREVIOUS LOAD AeR POINTER
A, t1
786
MOV
i GET Ie Bm FROM BUFFER
...,.,~.

~

9-185

231311-001

APPLICATIONS
9C52 E61E
9C54 C289IIC
9C572C
9CSS 2C

FE11

1'97

ANI
JNZ
INR
INR
INR
MOY
INR
/'IOV
CPI
JZ
CPI

C28~

79EI

JNZ

ec592C
0C5A 56
0C5B 2C

8C5C7E
8CSD
9C5F
9C62
9C64
OC67
9C69

787

m3
CA6COC

1E11
C36EOC

octm
8C6E 212828
0C71361:9
23
8C74 3688
0C7623
8C77 3698
8C79 23
8C7A 72
9C7B 23
9C7C 73
9C7D 3E81
OC7F 321620
0C82 C3890C

8m

788
789

790

m

792

793
194
195

1'''

m

i'lYI
JI1P
!11 U:
i'lYI
se2 TXRET: LXI
9116
i'lYI
INX
809
Mill
810
INX
811
i'lYI
812
INX
813
/'IOV
814
INX
815
.MOil
816
/'IYI
STA
il17
818
J/'IP

see

•

; LOOK AT GOOD FRAtIE BITS
; IF NOT 8, INTERRUPT WASN'T FROI'I A GOOD FRfII£
; BYPASS Re fIN) R1 IN BUFFER

1EH
RXI5
L
L
L
D,i'!
L
A,i'!
SNR/1P

; GET ADR BYTE

SAYE IT IN D

i GET CNTL BIITE FROI'I BUFFER
i WAS IT SNRI1-P?
i lIES, GO SET RESPONSE

U
RR8P
RXI5
E.RR!!F
TXRET
E,NSAF
H,CI!I)BF1
i'!,9C8H
H
M,OOH
H
/'I,08H
H
M,D
H
i'!,E
A,01H
POI,.IN
RXI5

ANI)

; WAS IT RR(8)-P?
; lIES, GO SET RESPONSE, OTHERWISE RETtRN
. ; RR(8)-P· SO SET RESPONSE TO RR(8)-F
i GO FINISH LORI)ING SPECIAL BUFFER
i SNRI1-P SO SET RESPONSE TO NSA-F
; SPECIAl. BUFFER ADR
i LOAO IX FRAi'IE COMI1AND
; INC POINTER
iL8=8
; INC POINTER .
iL1=!!
i INC POINTER
; LORI) RCVD ADR BYTE
; INC POINTER
; LORI) RESPONSE CNTL BYTE
; SET POLL INDICA~ NOT 8
i LOAD POLL INDICATOR
iRETURN

819
0CS5 E1
9C86 elM

828 RXI6:
821

POP
JI1P

H
I1XI5

i CLEAN

823 RXI5:
824
825

CALL
POP

RXD/'IA
D
B

.; RESET D/'IA CHANNEL
i RESTORE REGISTERS

926

POP
POP
EI
RET

UP STACK IF NORt1AL MODE
; RETURN

S22
OCS9 CDt.

ecsc

D1

OC8D C1
8esE F1
9C8F E1
OC9B· Fe
8C91 C9

8C93 7E
0C94 23
9C95FEFF
8C97 CAR19C
8C9A 4F
9C9B CDF805
0C9E C3939C
OCA1 C1
OCA2. C9

PSW

827
H
; ENABLE INTERRUPTS
828
.;RETURN
829
830.;
831 ;
832 ; t1ESSAGE TYPER - AS5lIt1ES i'IESSAGE STARTS AT HL

833
834
0C92 C5

POP

835
836
837
838
839
840
841
842
843
844
845
846
. 847
848

i
i

TVI'ISG: PUSH
TYMSG2: /'lOy
INX
CPI
JZ
I'IOY
CALL
JI'IP
TVI'I5G1: POP
RET

; SAVE BC
; GET ASC II CHR
; INC POINTER
i STOP?
; lIES, GET SET FOR E',.(IT
i SET UP FOR DISPLAY
i DISPLAII CHR
; GET NEXT CHR
iRESTORE BC
; RETURN

B
A,M
H
8FFH
TYMSG1

C, A
ECHO
TYMSG2

B

i

;
; SIGNON MESSAGE
;
9-186

231311·001

APPLICATIONS
eCA:? 0D
0CA438323m
OCAS 204D4F4E
BeAG 49544F52
~CBg 2e205631
0C84 2E?1
13CB6 00
eCB7 FF

eCBS
0CB9
eGBD
eeCl
0CC2

9D
52582049
4E54202D
2e
FF

849 SIGNON: DB

CR, '8273 110NITOR V1. 1', CR, eFFH

sse i
851 .:
S52 ;
S53 ; RECEIVER INTERRUPT MESSAGES
854 ;
855.:
856 RXH1SG: DB
CR.. 'RX INT - ',9FFH

857 ;
858 ; TRANSMITTER INTERRUPT MESSAGES

859
OCC3OO
0CC4 54582049
!:lCCS 4E54202D
!:lcce 29
eCCD FF

ecCE ES
BeCF F5
BCDe C5
BCD1 D5
em2 3E6l
0CD4 D3A8
ecD61694
OCOO 2A1920
0CDB ES
BCDC 45
0CDD 2A1329
0CE0 04 .
OCE1 78
0CE2 BD
OCE3 CAE40A
BCE6 15
eCE? C2E0eC
9CEA E1
eCEB 0892
0CED 77
0CEE 2C
0CEF 3690
0CF1 2C
9CF2 3699
9CF42C
0CFS 3609

0CF72C

i

860 TXIMSG: DB

CR, 'TX INT - " I!FFH

861;
862 i
863 ; TRANSI'1ITTER INTERRUPT ROUTINE
864 ;
PUSH
865 TXI:
H
iSAVE HL
. ,SAVE PSW
PUSH
866
PSW
,SAVE Be
867
PUSH
B
,SAVE DE
'PUSH
868
D
A,DTDI'IA
869
HVI
i DISABLE TX DI'IA
, 8257 MODE PORT
879
OUT
!'lODES?
, SET COUNTER
D,94H
871
"VI
872
LHLD
LDADR
i GET LOAD POINTER
,SAVE IT
PUSH
873
H
, SAVE LSB IN. B
874
1'10\1
B.L
, GET CONSOLE POINTER
875
Uti!
CNADR
876 TXI1: INR
B
i INC POINTER
A,B
871
1'10\1
i GET SET TO TEST
i LOAD=CONSOLE?
87S
CMP
L
; YES, BUFFER FULL
879
12
BUFFUL
, NO, TEST NEXT LOCATION
880
DCR
D
JNZ
TXI1
iTRY AGAIN
881
882
POP
H
i RESToRE LOAD POINTER
, READ RESULT
TXIR73
883
IN
M,A
HO\I
884
i STORE IN BUFFER
885
INR
i INR POINTER
L
M,99H
, EXTRA RESULT $POTS II
886
HVI
887
INR
L
1I,99H
888
MVI
889
INR
L
H,99H
IIVI
899
891
INR
L

9-187

231311-001

APPLICATIONS

9CF8
9CFA
9CFS
9CFE
1ID01
0002
0093
0094
0005
9D96

J600
2C
221020
CD350B
D1
C1
F1
E1
FB
C9

892
893
894
899
900
901
902
903
904
905
906
907
952
953
954

MYI
INR
SHLD
CALL
POP

pop
pop
POP
EI
RET

11,09H
L
LDADR
TXDMA
D
B
PSW
H

i UPi)f!TE LOAD POINTER,
; RESET DMA CHANNEL
iRESTORE DE
;RESTORE BC
; RESTORE PSW
; RESTORE HL
; ENABLE INTERRUPTS
; RETURN

;
;
i
)
END

PUBLIC SYMBOLS

EXTERIIAL SY/'1BOLS

USER SYMBOLS
ADIIN A 0922
CH051 A 0027
cNT053 A 009C
com A 9AE5
DEM
A 0000
ECHO A 05F8
ILLEG A 08A7
,HOCNT2 A 90B6
PARi A0B88
POLIN A 2916
ROY
A 9002
RSCHI) A 9967
RXI1 A 0C16
RXINT fi 0008
RXTC A41FF
SPCHf) A 99E2
STKSRT A 20C9
TEST73 A 0092
TXBlIF A 89119
TXINT A 0094
T'!'I1SG A 0C92

AFCHI)
CHI)BF1
CHT153
COt1t11

A 09CE
A 2020
A 0090
A 9AEA
DEMO~ 6 2027
ENDCHK A eA1B
LDADR A 2010
"DES1 A 99CE
PAR2 A 0BeD
PRtIPT A 2015
RESBI.JF A 28911
RST65 A 20CE
RXI2 A 0C23
RXIR73 A 0093
SBCI1D A 89B5
SRCf'II) A 99BA
sw A 0943
TFCMDA 09EC
0051 A 9988
TXIR73 A 9092
TYMSG1 A 0CA1

ASSEKBLI' COt1PLETE.

BliFFUL A 0AE4
CMDBUF A 2000
CNT253 A Il09E
COMM2' A 0AFF
DISPI' A eA39
ENDI'IA A 0063
LF' 'A 99eA
HOOE53· A 909B
PARIN A ~
RePT A 8AA2
RESL 73 A 9091
RST75 A 2004
RXI3 A 9C39
RXIRA, A 99112
SDWN A 98D7
SSCI'ID A 9989
T1
A 9C6C
TFCMD1 A 99F6
TXDMA A 9B35
TXIRA A ~991
TI'I1SG2 A 9C93

CH9ADR
CMOOlIT
CNTL51
COMI'I73
DISPI'1
GD/oIN

A 09A0
A 0AFB
A 0089
A 9090
A 9A4E
A 0BFF
I:KBRi ' A 2917
M0DES7 A 9eA8
PARIN1 A 0AE0
R1PT A 9AA7'
RQCHI) A 9951)
RXBUF A 8200
RXI4 A 0C45
RXS1 A 9A69
SIGNON A 9CA3
stART A 9890
TBUFFL .A 0A24
TFRET A 9A36
TXDI1A1 A 0842
TXPOL ,A 994C
YFILOO A 975E

CHeTC
CMDREC
CNTLC
CPBF
DISPI'2
GETCH
LKBR2
MONTOR
PAR IN2
RBCMD
RPCMD
RXDS1
RXIS
RXS2
SLCMD
STATS1
TBliFL
TLCHI)
TXI
TXRET

A'00A1
A 0857
A 000J
A 0020
A 0A4D
A061F
A 2918
A eees
A 9ADC
A 9978
A 99D8
A 0088
A0C89
A eA7F
A 898F
A 0089
A 9A07
A 9999
A eccE
A 9C6E

CH1ADR A 00A2.
Ct100E A 1m1
CNYBN. A Il5BB
A II1I9I)
CR
DRDPIA A ,1l062
GETCMD A 1l87D
LOOP IT A 0861
NI'1OUT A 96C7
PARINJ A,0ABC
RDCIII) A 9971
RR0F A 0011
RXDHA A tIB1A
RXI6 A 0C85
RXS3 A IlA8D
5NRIIP A, 9093
STATS? A 09A8
TBUFL1 A 0AIII)
TRlIE A 0090
TXIi' A 0CE9
TXSORC A 0A47

CH1TC
CNADR
COBR
CRlF
DTDMA
GRCMD
MDCNT0
NSAF
PAR1'173
ROlIN
RR0P
RXI
RXII1SG
RXSORC
SOOO
STAm

A 00A3
A 2013
A eooc
A 05EB
A 9961
A 09C4
A 0036
A 91173
A 9091
A98AF
A 0011
A 9C99
A 0CB8
A 9A62
A 09A6
A 1!990
IDWN A990E
TRlIEi A 9080
TXIMSG A 9CC3
A B1FF

mc

NO ERRORS

9-188

231311-001

intJ

APPLICATION
NOTE

AP-134

October 1981

@INTElCORPORATlON,l981

9-189

Ordor numbor: 210311-001

AP·134

Normally the data link is in an idle or marking state,
continuously transmitting a "mark" (binary 1). When a
character is to be sent, the character data bits are immediately preceded by a "space" (binary 0 START bit).
The mark-to-space transition informs the receiving system that a character of information will immediately
follow the start bit. Figure 1 illustrates the transmission
of a 7-bit ASCII character (upper case S) with even
parity. Note that the character is transmitted immediately following the start bit. Data bits within the character are transmitted from least-significant to
most-significant. The parity bit is transmitted immediately following the character data bits and the STOP
framing bit (binary 1) signifies the end ofthe character.
Asynchronous interfaces are often used with human
interface devices such as CRT/keyboard units where
the time between data transmissions is extremely
variable.

Characters

This framing method ensure~ that the receiving system
can easily synchronize with the start and stop bits of
each character, preventing receiver synchronization errors. In addition, this synchronization method makes
both transmitting and receiving systems insensitive to
possible time delays between character transmissions.

iii

Ii:

~
~
----.
CHARACTER

"

t

.
~

t:t:

0.1;;

..

~~
I

t

.. .

....

t:

I

Character framing is accomplished by the START and
STOP bits described previously. When the START bit
transition (mark-lo-space) is ~etected, the receiving
system assumes that a character of data will follow. In
order to test this assumption (and isolate noise pulses
on the data link), the receiving system waits one-half bit
time and samples the data link again. If the link has
returned to the_ marking state, noise is assumed, and the
receiver waits for another START bit transition.
When a valid START bit is detected, the receiver
samples the data link for each bit of the followirig character. Character data bits and the parity bit (if required)
are sampled at their nominal centers until all required
characters are received. Immediately following the
data bits, the receiver samples the data link for the
STOP bit, indicating the end of the character. Mostsystems permit spedfication of 1, 1\12, or 2 stop bits.

Timing

In asynchronous mode, characters may vary in length
from five to eight bits. The character length depends on
the coding method used. For example, five-bit charac"ters are used when transmitting Baudot Code, seven-bit
characters are required for ASCII data, and eight-bit
characters are needed for EBCDIC and binary data. To
transmit messages composed of multiple characters,
each character is framed and transmitted separately
(Figure 2).

iii

Framing

..

t:

t:

~

-

I

CHARACTER CHARACTER

iii

I;;

~

~

CHARACTER

••

iii

iii

Ii:

~
~
.....-CHARACTER
os

FIgure 2. MultIple Character TransmIssIon

The transmitter and receiver in an asynchronous datalink arrangement are clocked independently. Normally,
each clock is generated locally and the clocks are not
synchronized. In fact, each clock may be a slightly
different frequency. (In practice, the frequency difference should not exceed a few percent. If the transmitter
and receiver clock rates vary substantially, errors will
occur because data bits may be incorrectly identified as
START or STOP framing bits.) These clocks are designed to operate at 16,32, or 64 times the communications data rate. These clock speeds allow the receiving
device to correctly sample the incoming bit stream.
Serial-interface data rates are measured in bits/ second.
The term "baud" is used to specify the number of times
per second that the transmitted signal level can change
states. In general, the baud is not equal to the bit rate.
Only when the transmitted signal has two states
(electrical levels) is the baud rate equal to the bit rate.
Most point-to-point serial data links use RS-232-C, RS422, or RS-423 electrical interfaces. These spedfications call for two electrical signal levels (the baud is
equal to the bit rate). Modem interfaces, however, may
often have differing bit and baud rates.
While there are generally no limitations on the data
transmission rates used in an asynchronous data link, a
limited set of rates has been standardized to promote
equipment interconnection. These rates vary from 75
bits per second to 38,400 bits per second. Table 1 illustrates typical asynchronous data rates and the assodated clock frequendes required for the transmitter
and receiver circuits.
9-190

210311-001

AP-134

INTRODUCTION
The 8274 Multiprotocol serial controller (MPSC) is a
sophisticated dual-channel communications controller
that interfaces microprocessor systems to high-speed
serial data links (at speeds to 880K bits per second)
using synchronous or asynchronous protocols. The
8274 interfaces easily to most common microprocessors (e.g., 8048, 8051, 8085, 8086, and 8088), to DMA
.controllers such as the 8237and 8257, and to the 8089
I/O processor. Both MPSC communication channels
are completely independent and can operate in a fullduplex communication mode (simultaneous data transmission and reception).

Communication Functions
The 8274 performs many communications-oriented
functions, including:
-Converting data bytes from a microprocessor system
into a serial bit stream for transmission over the data
link to a receiving system.
-Receiving serial bit streams and reconverting the
data into parallel data bytes that can easily be processed by the microprocessor system.
-Performing error checking during data transfers. Error checking functions include computingl
transmitting error codes (such as parity bits or CRC
bytes) and using these codes to check the validity of
received data.
.

4. WAIT Mode. The MPSC ready signal is used to
synchronize processor data transfers by forcing the
processor to enter wait states until the 8274 is ready
for another data byte. This feature enables the 8274
to interface directly to an 8086 or 8088 processor by
means of string I/O instructions for very high-speed
data links.

Scope
This application note describes the use of the 8274 in
asynchronous communication modes. Asynchronous
communication is typically used to transfer data
to/from video display terminals, modems, printers, and
other low-to-medium-speed peripheral devices. Use of
the 8274 in both interrupt-driven and polled system
environments is described. Use of the DMA and WAIT
modes are not described since these modes are
employed mainly in synchronous communication systems where extremely high data rates are common.
Programming examples are written in PLlM-86
(Appendix B and Appendix C). PLlM-86 is executed by
the iAPX-86 and iAPX-88 processor families. In addition, PLlM-86 is very similar to PLlM-80 (executed by
the MCS-80 and MCS-85 processor families). In addition, Appendix D describes a simple application example using an SDK-86 in an iAPX-86/88 environment.

SERIAL-ASYNCHRONOUS DATA LINKS
A serial asynchronous interface is a method of data
transmission in which the receiving and transmitting
systems need not be synchronized. Instead of transmitting clocking information with the data, locally
generated clocks (16, 32 or 64 times as fast as the data
transmission rate) are used by the tralTSmitting and
receiving systems. When a character of information is
sent by the transmitting system, the character data is
framed (preceded and followed) by special START and
STOP bits. This framing information permits the receiving system to temporarily synchronize with the data
transmission. (Refer to Figure 1 during the following
discussion of asynchronous data transmission.)

-Operating independently of the system processor in a
manner designed to reduce the system overhead involved in data transfers.

System 'Interface
The MPSC system interface is extremely flexible,
supporting the following data transfer modes:
1. Polled Mode. The system processor periodically
reads (polls) an 8274 status register to determine
when a character has been received, when a character is needed for transmission, and when transmission errors are detected.

I

2. Interrupt Mode. The MPSC interrupts the system
processor when a character has been received, when
a character is needed for transmission, and when
transmission errors are detected.
3. DMA Mode. The MPSC automatically requests data
transfers from system memory for both transmit and
receive functions by means of two DMA request
signals per serial channel. These DMA request signals may be directly interfaced to an 8237 or 8257
DMA controller or to an ·8089 I/O processor.

TIME---+I
I
I

I

__1 _ 0

I

I

1

I

1

I

Q

I

0

DAr.:A~;I~:'LE S1~:T ~

I

1

I

0

I

1

I

0

I

1_1 __

iPARITYS~~P D~~A~;I~~~LE
PARITY

CHARACTER (UPPER CASE S·S3H)
1 0 1

0 0 1

1

Figure 1. Transmission of a 7-Bit ASCII Character
with Even Parity
9-191

210311-001

AP·134

software control, the 8274 can initiate·a I?reak.sequence
when transmitting data and detect a break sequence
when receiving data.

Table 1. Communication Data Rates and
Associated Transmitter/Receiver
Clock Rates

75
150
300
600
1200
2400
4800
9600
19200
38400

MPSC SYSTEM INTERFACE

Clock Rate (kHz)

Data Rate (bits/second)

X16

X32

X64

1.2
2.4
4.8
9.6
19.2
38.4
76.8
153.6
307.2
614.4

2.4
4.8
9.6
19.2
38.4
76.8
153.6
307.2
614.4

4.8
9.6
19.2
38.4
76.8
153.6
307.2
614.2

-

Hardware Environment
The 8274 MPSC interfaces to the system processor over
an 8-bit data bus. Each serial I/O channel responds to
two I/O or memory addresses as shown in Table 2. In
addition, the MPSC supports vectored and daisychained interrupts.

-

The 8274 may be configured for memory-mapped or
I/O·mapped operation.

Parity

Table 2. 8274 Addressing

In order to detect transmission errors, a parity bit may
be added to the character data as it is transferred over
the data link. The parity bit is set or cleared to make the
total number of "one" bits in the character even (even
parity) or odd (odd parity). For example, the letter "A"
is represented by the. seven·bit ASCII code 1000001
(4tH). The transmitted data code (with parity) for this
character contains.eight bits; 01000001 (41H) for even
parity and 11000001 (OCIH) for odd parity. Note that a
single bit error changes the parity of the received character and is therefore easily detected. The 8274 supports both odd and even parity checking as well as a
parity disable mode to support binary data transfers.

CS

A,

A

Read Operation

Write Operation

0
0
0

o.

0
1
0
1

0
0
1
1

1

X

X

Ch. A Data Read
Ch. A Status Read
Ch, B Data Read
Ch. B Status Read
'High Impedance

Ch. A Data Write
Ch. A Command/Parameter
Ch. B Data Write
Ch. B Command/Parameter
High Impedance

The 8274-processor hardware interface can be configured in a flexible manner, depending on the operating
mode selected-polled, interrupt-driven, DMA, or
WAIT. Figure 3 illustrates typical MPSC configurations
for use with an 8088 microprocessor in the polled and
interrupt-driven modes.

Communication Modes
All serial-to-parallel conversion, parallel-to·seria! conversion, and parity checking required during
asynchronous serial I/O operation is automaticillly performed by the MPSC.

Serial data transmission between two devices can oc~ur in one of three modes. In the simplex transmission
mode,.a data link can transmit data in one direction
only. In the half-duplex mode, the data link can transmit
data in both directions, but not simultaneously.. In the
full-duplex mode (the mo~t common), the data link can
transmit data in both directions simultaneously. The
8274 directly supports the full-duplex mode and will
interface to simplex and half-duplex communication
data links with appropriate software controls.

Operational Interface

BREAK Condition
Asynchronous data links often include a special sequence known as a break condition. A break condition
is initiated when the transmitting device forces the data
link to a spacing state (binary 0) for an extended length
of time (typically 150 milliseconds). Many terminals contain keys to initiate a break sequence. Under

Command, parameter, and status information is stored
in 22 registers within the MPSC (8 writable registers
and 3 readable registers for each channel). These regis·
ters are all accessed by means of the command! status
ports for each charmel. An internal pointer register
selects which of the command or status registers will be
written or read during a command/status access of an
MPSC channel. Figure 4 diagrams the command/status
register architecture for each serial channel. In the
following discussion, the writable registers will be
referred to as WRO through WR7 and the readable registers will be referred to as RRO through RR2.

9-192

210311-001

AP·134

a) Polled Configuration

..,. ...

~ ADDRESS BUS

j)

~ DATA BUS

1)

RD
WR

'--

8205

---

P

P
~

'---

~

DBO-7.

INTA

Ao
A,

Vcc

1

~

MPSC

CS
RD
WR

b) Daisy-chained .Interrupt Configuration
Vee

INTHf
INTA

);

CPU
INT

~

),
INT

INTA

IPO

IPI

IPI

IPO
MPSC

MPSC

INT

INTA

HIGHEST PRIORITY

IPI

6

INTA

IPO

MPSC
LOWEST PRIORITY

Figure 3. 8274 Hardware Interface for Polled and Interrupt-driven Environments

The least-significant three bits of WRO are automatically loaded into the pointer register every time WRO is
written. After reset, WRO is set to zero so that the first
write to a command register causes the data to be
loaded into WRO (thereby setting the pointer register).
After WRO is written, the following read or write accesses the register selected by the pointer. The pointer is
reset after the read or write operation is completed. In
this manner, reading or writing an arbitrary MPSC
channel register requires two I/O accesses. The first
access is always a write command. This write command
is used to set the pointer register. The second access is
either a read or a write command; the pointer register
(previously set) will ensure that the correct internal
register is read or written. After this second access, the
pointer register is automatically reset. Note that writ·
ing WRO and reading RRO does not require presetting of
the pointer register.

During initialization and normal MPSC operation,
various registers are read and/or written by the system
processor. These actions are discussed in detail in the
following paragraphs. Note that WR6 and WR7 are not
used in the asynchronous communication modes.

RESET
When the 8274 RESET line is activated, both MPSC
channels enter the idle state. The serial output lines are
forced to the marking state (high) and the modem inter·
, face signals (RTS, DTR) are forced high. in addition,
the pointer register is set to zero.
9-193

210311-001

Ap·134

COMMAND/STATUS
POINTER

02

01

DO

0

0

0

.1

w:

R

-I

w

R

-I

w

R

-I

W

R

-I

w

R

-I

w

R

w

R

w

R

-I
-I

:::

r

"'

1

1 1

II

R

R

R

R

R

R

1 1MSB

I

LSB

Read Registers

7'

1

MSB

LSB
Write Registers

Figure 4. Command/Status Register Architecture (Each Serial Channel)

External/Status Latches
The MPSC continuously monitors the state of four external/ status conditions:
1. CTS-clear-to-send input pin.

4. BREAK-a break condition (series of space bits on
the receiver input pin).
A change of state in any of these monitored conditions
will cause the associated status bit in RRO (Appendix A)
to be latched (and optionally cause an interrupt).

2. CD-carrier-detect input pin.

Error Reporting

3. SYNDET-sync-detectinput pin. This pin may be
used as a general-purpose input in the asynchronous
communication mode.

Three error conditions may be encountered during data
reception in the asynchronous mode:
9-194

210311-001

AP-134

all remaining bits must be set to 1. The following
table illustrates the data formats for transmission of
I to 5 bits of data:

1. Parity. If parity bits are computed and transmitted
with each character and the MPSC is set to check
parity (bit 0 in WR4 is set), a parity error will occur
whenever the number of "1" bits within the character (including the parity bit) does not match the
odd/even setting of the parity check flag (bit 1 in
WR4).

Number of
Bits Transmitted
07 06 05 04 03 02 01 00 (Character Length)

2. Framing. A framing error will occur if a stop bit is
not detected immediately following the parity bit (if
parity checking is enabled) or immediately following
the most-significant data bit (if parity checking is not
enabled).
3. Overrun. If an input character has been assembled
but the receiver buffers are full (because the previously received characters have not been read by the
system processor), an overrun error will occur.
When an overrun error occnrs, the input character
that has just been received will.overwrite the immediately preceding character.

Transmitter/Receiver Initialization
In order to operate in the asynchronous mode, each
MPSC channel must be. initialized with the following
information:
1. Clock Rate. This parameter is specified by bits 6 and
7 .ofWR4. The clock rate may be set to 16, 32, or 64
time,s the data-link bit rate. (See Appendix A for WR4
details.)

2. Number of Stop Bits. This parameter is specified by
bits 2 and 3 of WR4. The number of stop bits may be
set to 1, Ij,2, or2. (SeeAppendixAforWR4details.)
3. Parity Selection. Parity may be set for odd, even, or
no parity by bits 0 and 1 of WR4. (See Appendix A
for WR4 details.)
4. Receiver Character Length. This parameter sets the
length of received characters to 5, 6, 7, or 8 bits. This
parameter is specified by bits 6 and 7 of WR3. (See
Appendix A for WR3 details.)
5. Receiver Enable. The serial-channel receiver operation may be enabled or disabled by setting or clearing bit 0 ofWR3. (See Appendix A forWR3 details.)

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

c

c
c

c
c
c

c
c
c
c

c
c
c
c
c

2

4
5

7. Transmitter Enable. The serial channel transmitter
operation may be enabled or disabled by setting or
clearing bit 3 of WR5. (See Appendix A for WR5
details.)
For data transmissions via a modem or RS-232-C interface, the following information must also be specified:
1. Request-to-SendlData-Terminal-Ready. Must be
set to indicate status of data terminal equipment.
Request-to-send is controlled by bit 1 of WRS and
data terminal ready is controlled by bit 7. (See Appendix A for WR5 details.)

2. Auto Enable. May be set to allow the'MPSC to
automatically enable the channel transmitter when
the c1ear-to-send signal is active and to automatically enable the receiver when the carrier-detect
signal is active. Auto Enable is controlled by bit 5 of
WR3. (See Appendix A for WR3 details.)
During initialization, it is desirable to guarantee that the
external! status latches reflect the latest interface information. Since up to two state changes are internally
stored by the MPSC, at least two Reset External/Status
Interrupt commands must be issued. This procedure is
most easily accomplished by simply issuing this reset
command whenever the pointer register is set during
initialization.
An MPSC initialization procedure (MPSC$RX$INIT)
for asynchronous communication is listed in Appendix
B. Figure .5 illustrates typical MPSC initialization
parameters for use with this procedure.

6. Transmitter Character Length. This parameter sets
the length of transmitted characters to 5, 6, 7, or 8
bits. This parameter is specified by bits 5 and 6 of
WR5. (See Appendix A forWR5 details.) Characters
of less than 5 bits in length may be transmitted by
setting the transmitted length to five bits (set bits 5
and 6 of WR5 to 1).
The MPSC then determines the actual number of
bits to be transmitted from the character data byte.
The bits to be transmitted must be right justified in
the data byte, the next three bits must be set to 0 and

call MPSC$RX$INIT(41,

1,1,0,1,

3,1,1,

3,1,1,0,1);

initializes the 8274 at address 41 as follows:
X16 clock rate
1 stop bit
Odd parity
8·bit characters (Tx and Rx)

Enable transmitter and receiver

Auto enable set
OTR and RTS set
Break transmission disabled

Figure 5 .. Sampie 8274 initialization Procedure
for Polled Operation

9-195

210311-001

AP-134

Polled Operation
In the polled mode, the processor must monitor the
MPSC status by testing the appropriate bits in the read
register. Data available, status, and error conditions are
represented in RRO and RRI for channels A and B. An
example ofMPSC-polled transmitter/receiver routines
are given in Appendix B. The following routines are
detailed:
I. MPSC$POLL$RCV$CHARACTER-This procedure receives a character from the serial data iink.
The routine waits until the character-available flag in
RRO has been set. When this flag indicates that a
, character is available, RRI is checked for errors
(overrun, parity, or framing). If an error is detected,
the character in the MPSC receive buffer must be
read and discarded and the error routine
(RECEIVE$ERROR) is called. If no receive errors
have been detected, the character is input from the
8274 data port and returned to the calling program.
MPSC$POLL$RCV$CHARACTER requires
three parameters-the address of the 8274 channel
data port (data$port), the address of th~ 8274 channel command port (cmd$port), and the address of a
byte variable in which to store the received character (character$ptr).,
2. MPSC$POLL$TRAN$CHARACTER-This pro, cedure transmits a character to the serial data link.
Theroutine waits until the transmitter-buffer-empty
flag has been set in RRO before writing the character
to the 8274.
,
MPSC$POLL$TRAN$cHARACTER requires
three parameters-the address of the 8274 channel
data port (data$port), the address ofthe 8274 channel command port (cmd$port), and the character of
data that is to b,e transmitted (character).
3. RECEIVE$ERROR-This ,procedure processes
receiver errors.' First, ~ Error Reset command is
written to the affected channel. All additional error
processing is dependent on the specific application.
For example, the receiving device may immediately
request retransmission of the character or wait until
a message has been completed.
RECEIVE$ERROR requires two parametersthe address of the affected 8274 command port
(cmd$port) and the error status (status) from 8274
register RR1.
'

the character from the MPSC data buffer and clear the
current interrupt. During transmission, the system processor starts serial 110 by writing the first character of a
message to the MPSC. The MPSC interrupts the system'
processor whenever the next character is required (i.e.,
when the transmitter buffer is empty) and the processor
responds by writing the next character of the message
to the MPSC data port for the appropriate channel.
By using interrupt-driven 110, the MPSC proceeds in"
dependently of the system processor, signalling the
processor only when characters are required for transmission, when characters are received from the data
link, or when errors occur. In this manner, the system
processor may continue execution of other tasks while
serial 110 is performed concurrently.

Interrupt Configurations
The 8274 is desigried to interface to 8085- and 8086-type
processors in much the, same manm~r as the 8259A is
designed. When operating in the 8085 mode, the 8274
causes a "call" to a prespecified, interrupt-service
routine location. In the 8086 mode, the 8274 presents
the processor with a one-byte interrupt-type number.
This interrupt-type number is used to "vector" through
the 8086 interrupt service table. In either case, the
interrupt service address or interrupt-type number is
speCified during MPSC initialization.
To shorten interrupt latency, the 8274 can be programmed to modify the prespecified interrupt vector so that
no software overhead is required to determine the
cause ofan interrupt. When this "status affects vector"
mode is enabled, the following eight interrupts are differentiated automatically by the 8274 hardware:
1. Channel B Transmitter Buffer Empty.
2. Channel B External/Status Transition.
3. Channel B Character Available.
4. Channel B Receive Error.
5. Channel A Transmitter Buffer Empty.
6. Channel A External/Status Transition.
7. Chaimel A Character Available.
8~ Channel A Receive Error.

Interrupt-driven Operation

Interrupt Sources/Priorities

In an interrupt-driven environment, aU receiver
operations are reported to the system processor by
means of interrupts. Once a char,acter has been
received and assembled, the MPSC interrupts the system processor. The system processor must then read

The 8274 has three interrupt sources for each channel:
I. Receiver (RxA, RxB). An interrupt is initiated when
a character is avlillable in the receiver buffer or when
a receiver error (parity, framing, or overrun) is
detected.
9-196

210311-001

AP-134

2. Transmitter (TxA, TxB). An interrupt is initiated
when the transmitter buffer is empty and the 8274 is
ready to accept another character for transmission.

DMA operation for both channels, and c) DMA
operation for channel A, interrupt-driven operation
for channel B. The system configuration is specified
by means of bits 0 and 1 of WR2 (channel A). (See
Appendix A for WR2 details.)

3. ExternallStatus (ExTA, ExTB). An interrupt is initiated when one of the external/status conditions
(CD, CTS, SYNDET, BREAK) changes state.

7. Interrupt Priorities. The 8274 permits software
specification ofreceiveltransmit priorities by means
of bit 2 of WR2 (channel A). (See Appendix A of
WR2 details.)

The 8274 supports two interrupt priority orderings
(selectable during MPSC initialization) as detailed in
Appendix A, WR2, CH-A.

Interrupt Initialization
In addition to the initialization parameters required for
polled operation, the following parameters must be supplied to the 8274 to specify interrupt operation:

8. Interrupt Mode. Specifies whether the MPSC is to
operate in a non-vectored mode (for use with an
external interrupt controller), in an 8086-vectored
mode, or in an 808S-vectored mode. This parameter
is specified through bits 3 and 4 ofWR2 (channel A).
(See Appendix A for WR2 details.)

1. Transmit Interrupt Enable. Transmitter-bufferempty interrupts are separately enabled by bit 1 of
WRI. (See Appendix A for WRI details.)
2. Receive Interrupt Enable. Receiver interrupts are
separately enabled in one of three modes: a) interrupt on first received character only and on receive
errors (used for message-oriented transmission systems), b) interrupt on all received characters and on
receive errors, but do not interrupt on parity errors,
and c) interrupt on all rec!!ived characters and on
receive errors (including parity errors). The ability
to separately disable parity interrupts can be extremely useful when transmitting messages. Since
the parity error bit in RRI is latched, it will not be
reset until an error reset operation is performed.
Therefore, the parity error bit will be set if any parity
errors were detected in a multicharacter message. If
this mode is used, the serial 110 software must poll
the parity error bit at the completion of a message
and issue an error reset if appropriate. The receiver
interrupt mode is controlled by bits 3 and 4 of WRI.
(See Appendix A for WRI details.)

Table 3. MPSC-generated Interrupt Vectors in
"Status Affects Vector" Mode
V7 V6 V5 V4 V3 V2Vf VO

V7 V6 V5 V4 V3 V2 V1 VO

Original Vector
(specified during
Initialization)
Interrupt
Condition

8085
Interrupt Location

8086
Interrupt Type
V7 V6 V5 V4 V3

0 0 0

V7 V6 V5

o

0 0 VI VO

Channel B Transmitter

V7 V6 V5 V4 V3

0 0 I

V7 V6 VS

o

0 I VI VO

Channel B External/Status
Change

V7 V6 V5 V4 V3

0

I

0

V7 V6 V5 0

I

o

V7 V6 V5 Y4 V3

0

I

I

V7 V6 V5 0

I

I VI VO

o

0 VI VO

Buffer Empty

VI VO

Channel B Receiver
Character Available

Y7 V6 V5 V4 V3

I

0 0

V7 V6 V5

I

V7 V6 V5 V4 V3

I

0

I

V7 V6 V5

I 0 I VI VO

V7 V6 V5 V4 Y3

I

I 0

V7 V6 V5

I

I

o

V7 V6 V5 V4 V)

I

I

V7 V6 V5

I

I

I VI VO

Channet B Receive Error
Channel A Transmillcr

Buffer Empty
Channel A Exlernal/Status
Change

I

VI VO

Channel A Receiver
Character Available
Channel A Receive Error

An MPSC interrupt initialization procedure
(MPSC$INT$INIT) is listed in Appendix C.

3. Externall Status Interrupts. Externall Status interrupts can be separately enabled by bit 0 of WRI.
(See Appendix A for WRI details.)

Interrupt Service Routines

4. Interrupt Vector. An eight-bit interrupt-service
routine location (8085) or interrupt type (8086) is
specified through WR2 of channel B. (See Appendix
A for WR2 details). Table 3 lists interrupt vector
addresses generated by the 8274 in the "status affects vector" mode.

Appendix C lists four interrupt service procedures, a
buffer transmission procedure, and a buffer reception
procedure that illustrate the use of the 8274 in interruptdriven environments. Use of these procedures assumes
that the 8086/8088 interrupt vector is set to 20H and
that channel B is used with the "status affects vector"
mode enabled.

5. "Status Affects Vector" Mode. The 8274 will autom~tically modify the interrupt vector if bit 3 ofWRl
is set. (See Appendix A for WRI details.)
6. System Configuration. Specifies the 8274 data transfer mode. Three configuration modes are available:
a) interrupt-driven operation for both channels, b)

1. TRANSMIT$BUFFER-This procedure begins
serial transmission of a data buffer. Two parameters
are required-a pointer to the buffer (buf$ptr) and
the length of the buffer (buf$length). The procedure
first sets the global buffer pointer, buffer length, and
9-197

210311-001

AP-134

initial index for the transmitter-interrupt service
routine and initiates transmission by writing the first
character of the buffer to the 8274. The procedure
then enters a wait loop until the I/O completion
status is set by the transmit-interrupt service routine
(MPSC$TRANSMIT$CHARACTER$INT).
2. RECEIVE$BUFFER-This procedure inputs a line
(terminated by a line feed) from a serial I/O port.
Two parameters are required-a pointer to the input
buffer (buf$ptr) and a pointer to the buffer length
variable (buf$length$ptr). The buffer length will be
set by this procedure when the complete line has
been input. The procedure first sets the global buffer
pointer and initial index for the receiver interrupt
service routine. RECEIVE$BUFFER then enters a
wait loop until the I/O completion status is set by the
receive interrupt routine (MPSC$RECEIVE$CHARACTER$INT).
3. MPSC$RECEIVE$CHARACTER$INT -This
procedure is executed when the MPSC Tx-bufferempty interrupt is acknowledged. If the current
transmit buffer index is less than the buffer length,
the next character in the buffer is written to the
MPSC data port and the buffer pointer is updated.
Otherwise, the transmission complete status is
posted.
4. MPSC$RECEIVE$CHARACTER$INT - This
procedure is executed when a character has been
assembled by the MPSC and the MPSC has issued a
character-available interrupt. If no input buffer has
been set up by RECEIVE$BUFFER, the character
is ignored. If a buffer has been set up, but it is full, a
receive overrun error is posted. Otherwise, the
received character is read from the MPSC data port
and the buffer index is updated. Finally, if the
received character is a line feed, the reception complete status is posted.
5. RECEIVE$ERROR$INT-This procedure is executed when a receive error is detected. First, the
error conditions are read from RRI and the character currently in the MPSC receive buffer is read and
discarded. Next, an Error Reset command is written
to the affected channel. All additional error procession is application dependent.
6. EXTERNAL$STATUS$CHANGE$INT -This
procedure is executed when an external status condition change is detected. The status conditions are
read from RRO and a Reset External/Status Interrupt command is issued. Further error processing is
application dependent.

DATA LINK INTERFACE
Serial Data Interface
Each serial I/O channel within tlie 8274 MPSC interfaces to two data link lines-one line for transmitting
data and one for receiving data. During transmission,
characters are converted from parallel data format (as
supplied by the system processor orDMA device) into
a serial bit stream (with START and STOP bits) and
clocked out on the TxD pin. During reception, a serial
bit stream is input on the RxD pin, framing bits are
stripped out of the data stream, and the resulting character is converted to parallel data format and passed to
the system processor or DMA device.

Data Clocking
As discussed previously, the frequency of data transmission/reception on the data link is controlled by the
MPSC clock in conjunction with the programmed clock
divider (in registerWR4). The 8274 is designed to permit
all four serial interface lines (TxD and RxD for each
channel) to operate at different data rates. Four clock
input pins (TxC and RxC for each channel) are available
for this function. Note that the clock rate divider specified in WR4 is used for both RxC and TxC on the
appropriate channel; clock rate dividers for each channel are independent.

Modem Control
The following four modem interface signals may be
connected to the 8274:
1. Data Terminal Ready (DTR). This interface signal
(output by the 8274) is software controlled through
bit 7 of WR5. When active, DTR indicates that the
data terminal/computer equipment is active and
ready to interact with the data communications
channel. In addition, this signalprepares the modem
for connection to the communication channel and
maintains connections previously established (e.g.,
manual call origination).

2. RequestTo Send (RTS). This interface signal (output
by the 8274) is software controlled through bit 1 of
WR5. When active, RTS indicates that the data terminal/computer equipment is ready to transmit
data.
3. ClearTo Send (CTS). This interface signal (input to
the 8274) is supplied by the modem in response to an
active RTS signal. CTS indicates that the data terminal/computer equipment is permitted to transmit
9-198

210311-001

Ap·134

data. The state of CTS is available to the programmer as bit 5 of RRO. In addition, if the auto enable
control is set (bit 5 ofWR3), the 8274 will not transmit data bytes until RTS has been activated. If CTS
becomes inactive during transmission of a character,
the current character transmission is completed
before the transmitter is disabled.

addition, if the auto enable control is set (bit 5 of
WR3), the 8274 will not enable the serial receiver
until CD has been activated. If the CD signal becomes inactive during reception of a character, the
receiver is disabled, and the partially received character is lost.

4. Carrier Detect (CD). This interface signal (input to
the 8274) is supplied by the modem to indicate that a
data carrier signal has been detected and that a valid
data signal is present on the RxD line. The state of
CD is available to the programmer as bit 3 ofRRO. In

In addition to the above modem interface signals, the
8274 SYNDET input pin for channel A may be used as a
general-purpose input in the asynchronous communication mode. The status of this signal is available to the
programmer as bit 4 of status register RRO.

9-199

210311-001

AP·134

APPENDIX A
COMMAND/STATUS DETAILS FOR ASYNCHRONOUS
COMMUNICATION
Command 3 Channel Reset-resets the Latched
Status bits of RRO, the interrupt
prioritization logic and all control registers for the channel. Four extra system
clock cycles should be allowed for MPSC
reset time before any additional commands or controls are written into the
channel.

Write Register 0 (WRO):

COMMANO/STATUS POINTER
REGISTER POINTER

r0

o1

NULL CODE
NOT USED IN ASYNCHRONOUS MODES
RESET EXT/STATUS INTERRUPTS
CHANNEL RESET
ENABLE INTERRUPT ON NEXT RI
CHARACTER
RESET TIINT PENDING
ERROR RESET
END OF INTERRUPT

NOT USED IN ASYNCHRONOUS MODES

02,01,00

05,D4,03

Command/Status Register Pointer bits
determine which write-register the next
byte is to be written into, or which readregister the next byte isto be read from.
Mter reset, the first byte written into
either channel goes into WRO. Following
a read or write to any register (except
WRO) the pointer will point to WRO.

Command 4 Enable Interrupt on Next Receive
Character-if the Interrupt-on-FirstReceive Character mode is selected, this
command reactivates that mode after
each complete message is received to prepare the MPSC for the next message.
Command 5 Reset Transmitter Interrupt Pending-if
The Transmit Interrupt mode is selected,
the MPSC automatically interrupts data
when the transmit buffer becomes empty.
When there are no more characters to be
sent, issuing this command prevents further transmitter interrupts until the next
character has been completely sent.
Command 6 Error Reset-error latches, Parity and
Overrun errors in RRI are reset.
Command 7 End ofInterrupt-resets the interrupt-inservice latch of the highest-priority internal device under service.
DO

External/Status Interrupt Enableallows interrupt to occur as the result of
transitions on the CO, CTS or SYNOET
inputs. Also allows interrupts as the
result of a Break/ Abort detection and termination, or at the beginning of CRC, or
sync character transmission when the
Transmit Underrun/EOM latch becomes
set.

01

Transmitter Interrupt/OMA Enable
-allows the MPSC to interrupt or request a OMA transfer when the transmitter buffer becomes empty.

02

Status Affects Vector-(WRI, 02 active
in channel B only.) If this bit is not set,

Command bits determine which of the basic seven commands are to be performed.

Command 0 Null-has no effect.
Command 1 Not used in asynchronous modes.
Command 2 Reset External/Status Interruptsresets the latched status bits of RRO and
reenables them, allowing interrupts to occur again.

9-200

210311-001

AP-134

High-Z state. (Conditions: Interrupt Enabled Mode, Wait Enabled, CS =0,
AO=O/ I, and A I =0). The RDY pin is
pulled low when the transmitter buffer is
full or the receiver buffer is empty and it
is driven High' when the transmitter buffer is empty or the receiver buffer is full.
The RDYA and RDYB may be wired or
connected since only one signal is active
at anyone time while the other is in the
High Z state.

Write Register 1 (WR1):
LSB

MSB

I

07

1

0

I

05

1 04

: 03

I

02

1 01 I

~

I

DO

I

EXT INTERRUPT

ENABLE

TxlNTERRUPTI
DMA ENABLE

1 - VARIABLE
STATUS AFFECTS

VECTOR

VECTOR (CH B ONt V)
(NULL coDe CH A)

o -=

FixeD

D6

Must be Zero.

D7

Wait Enable-enables the wait function.

VECTOR

~
RxlNTIDMA DISABLE
0
0

Write Register 2 (WR2): Channel A

RxlNT ON FIRST CHAR OR SPECIAL

MSB

CONDITION

rwToT~T~~ooloolm~ool

0

1

1

0

INT ON ALL Ax CHAR (PARITY AFFECTS
VECTOR) OR SPECIAL CONDITION

1

1

INT ON ALL Ax CHAR (PARITY DOES
NOT AFFECT VECTOR) OR SPECIAL
CONDITION

1

~

~

~
0

0

BOTH INTERRUPT

0

1

A OMA'. B INT

1

0

BOTH DMA

1

1

ILLEGAL

WAIT ON Rx, 0 - WAIT ON Tx
MUST BE ZERO

WAIT ENABLE

1 -" ENABLE,O

~

DISABLE

1 = PRIORITY AxA>RxS>TxA>
TIB >eXTA"> EXTS'

o-

then the fixed vector, programmed in
WR2,is returned from an interrupt acknowledge sequence. If the bit is set, then
the vector returned from an interrupt acknowledge is variable as shown in the
Interrupt Vector Table.
D4,03

PRIORITY RxA >TxA >RxB

Receive Interrupt Mode.

>

TIIS >eXTA' >eXTS"

~
0

0

8085 MODE 1

0

1

8085 MODE 2

1

0

8086/88 MODE

1

1

ILLEGAL

1 - VECTORED INTERRUPT

0- NON VECTORED INTERRUPT

00

Receive Interrupts/DMA Disabled.

01

Receive Interrupt on First Character
Only or Special Condition.

10

Interrupt on All Receive Characters of
Special Condition (Parity Error is a Special Receive Condition).

I I

Interrupt on All Receive Characters or
Special Condition (Parity Error is not a
Special Receive Condition).

D5

Wait on Receive/Transmit-when the
following conditions are met, the RDY pin
is activated, otherwise it is held in the

MUST BE ZERO

1

PIN 10

o

= SYNDET 6

PIN 10

= RTS a

'EXTERNAL STATUS INTERRUPT·
ONLY IF EXT INTERRUPT ENABLE (WR1: DO)IS SET

DI,DO

00

9-201

System Configuration-These specify
the data transfer from MPSC channels to
the CPU, either interrupt or DMAbased.

Channel A and Channel B both use
interrupts.

210311-001

AP-134

01

Channel A uses DMA, Channel Busses
interrupt.

10

Channel A and Channel Bboth use DMA.

I I

Illegal Code.

D2

Priority-this bit specifies the relative
priorities of the internal MPSC interrupt/DMA sources.

o

(Highest) RxA, TxA, RxA, RxB,
TxBExTA, ExTB (Lowest).

D7-DO

Write Register 3 (WR3):
MSB

oX X

LSB

Rx ENABLE

(Highest) RxA, RxB, TxA, TxB, ExTA,
ExTB (Lowest).
D5,D4,D3

Interrupt vector-this register contains
the value of the interrupt vector placed on
the data bus during acknowledge
sequences.

L..-_ _ _ _ NOT USED IN

ASYNCHRONOUS
MODES

Interrupt Code-specifies the behavior
of the MPSC when it receives an interrupt
acknowledge sequence from the CPU.
(See Interrupt Vector Mode Table).

' - - - - - - - - - - A U T O ENABLES

Rx 5 BITSfCHAR

Non-vectored interrupts-intended for
us'e with an external interrupt controller
such as the 8259A.

Rx 7 BITS/CHAR
Rx 6 BITS/CHAR

100

8085 Vector Mode I-intended for use as
the primary MPSC in a daisy-chained
priority structure.

I0I

8085 Vector Mode 2~intended for use as
any secondary MPSC in a daisy-chained
priority structure.

I I 0

8086/88 Vector Mode-intended for use
as either a primary or secondary in a
daisy-chained priority structure.

D6

Rx 8 BITS/CHAR

DO

Receiver Enable-A one enables the
receiver to begin., This bit should be set
only after the receiver has been
initialized.

D5

Auto Enables-A one written to this bit
causes CD to be an automatic enable signal for the receiver and eTC to be an
automatic enable signal for the transmitter. A zero written to this bit limits the
effect of CD and CTS signals to setting/resetting their corresponding bits in
tlie status register (RRO).

D7,D6

Receiver Character length.

00

Receive 5 Data bits/ character.

01

Receive 7 Data bits/character.

10

Receive 6 Data bits/character.

I I

Receive 8 Data bits/character.

Must be Zero.

D7

o

Pin 10 = RTS B .
Pin 10 = SYNDETB .
Write Register 2 (WR2): Channel B
MSB

LSD

In:~:~:~:~:~! ~:~I

,

L,
Vector

210311-001

AP·134

Write Register 4 (WR4):

1

co

o '--

EVEN PARITY

00

Clock rate

=

Data rate x 1.

01

Clock rate

=

Data rate x 16.

10

Clock rate = Data rate x 32.

11

Clock rate

=

Data rate x 64.

Write Register 5 (WR5):

ODD PARITY
LSB

o a

ENABLE SYNC MODES

o

1

1 STOP BIT

1

0

1.5 STOP BITS

1

1

2 STOP BITS

NOT USED IN
ASYNCHRONOUS MODES

RTS
NOT USED IN
ASYNCHRONOUS MODES

NOT USED IN ASYNCHRONOUS MODES

~----TlC

o
o

~

0

X1 CLOCK

1

X16 CLOCK

o

X32 CLOCK

ENABLE

_ _ _ _ _ _ SEND BREAK

Tx 5 BITS OR LESS/CHAR

Tx 7 BITSfCHAR
X64 CLOCK
Tx 6 BITS/CHAR

DO

Parity-a one in this bit causes a parity
bit to be added to the programmed number of data bits per character for both the
transmitted and received character. If the
MPSC is programmed to receive 8 bits
per character, the parity bit is not transferred to the microprocessor. With other
receiver character lengths, the parity bit
is transferred to the microprocessor.

Dl

Even/Odd Parity-if parity is enabled, a
one in this bit causes the MPSC to transmit and expect even parity, and zero
causes it to send and expect odd parity.

D3,D2

Stop Bits.

00

Selects synchronous modes.

o1

Async mode, 1 stop bit/character.

10

Async mode, 116 stop bits/character.

11

Async mode, 2 stop bits/character.

D7,D6

Clock mode-selects the clock/data rate
multiplier for both the receiver and the
transmitter. If the Ix mode is selected, bit
synchronization must be done externally.

Tx 8 BITS/CHAR
' -_ _ _ _ _ _ _ _ _ _ _ DTR

Dl

Request to Send-a one in this bit forces
the RTS pin active (low) and zero in this
bit forces the RTS pin inactive (high).

D3

Transmitter Enable-a zero ill this bit
forces a marking state on the transmitter
output. If this bit is set to zero during data
or sync character transmission, the marking state is entered after the character has
been sent. If this bit is set to zero during
transmission of a CRC character, sync or
flag bits are substituted for the remainder
of the CRC bits.

D4

Send Break-a one in this bit forces the
transmit data low. A zero in this bit allows
normal transmitter operation.

D6,D5

Transmit Character length.

00

Transmit 5 or less bits/character.

01

Transmit 7 bits/character.

10

Transmit 6 bits/character.

9-203

210311-001

Ap·134

I I

Transmit 8 bits/ character.

D4

SYNDET-In asynchronous modes, the
operation of this bit is similar to the CD
status bit, except that it shows the state of
the SYNDET input. Any High-to-Low
transition on the SYNDET pin sets this
bit, and causes an External/Status interrupt (if enabled). The Reset External/Status Interrupt command is issued
to clear the interrupt. A Low-to-High
transition clears this bit and sets the External/Status interrupt. When the External!Status interrupt is set by the change
in state of any other input or condition,
this bit shows the inverted state of the
SYNDET pin at time of the change. This
bit must be read immediately following a
Reset External/ Status Interrupt command to read the current state of the
SYNDET input.

D5

Clear to Send-this bit contains the inverted state of the CTS pin at the time of
the last change of any of the External!Status bits (CD, CTS, Sync/Hunt,
Break/Abort, or Tx Underrun/EOM).
Any change of state of the CTS pin causes
the CTS bit to be latched and causes an
External!Status interrupt. This bit indicates the inverse of the current state of
the CTS pin immediately following a
Reset External/Status Interrupt
command.

D7

Bits to be sent must be right justified; least-significant
bit first, e.g.:
D7 D6 D5 D4 D3 D2 DI DO
0 B5 B4 B3 B2 B I BO

o

Read Register 0 (RRO):

T)I BUFFER EMPTY

CARRIER DETECT

)

' - -_ _ _ _ SYNDET

L:_-_-_-_-_-_-_-_-_-_-_- ;;~~~~~~~OUS MODES

L.._

L.._ _ _ _ _ _ _ _

~.l';i:.:'.:~TsJ~b~S

BREAK

DO

Receive Character Available-this'bit is
set when the receive FIFO contains data
and is reset when the FIFO is empty,

DI

Interrupt Pending-This InterruptPending bit is reset when an EOI command is issued and there is no other
interrupt request pending at that time. In
vector mode, this bit is set at the falling
edge of the second INTA in an INTA
cycle for an internal interrupt request. In
non-vector mode, this bit is set at the
falling edge of RD input after pointer 2 is
specified. This bit is always zero in
Channel·B.

D2

Transmit Buffer Empty-This bit is set
whenever the transmit buffer is empty
except when CRC characters are being
sent in a synchronous mode, This bit is
reset when the transmit buffer is loaded.
This bit is set after an MPSC reset.

Break-in the Asynchronous Receive
mode, this bit is set when a Break sequence (null character plus framing error)
is detected in the data stream. The External/Status interrupt, if enabled, is set
when break is detected. The interrupt service routine must issue the Reset External/Status Interrupt command (WRO,
Command 2) to the break detection logic
so the Break sequence termination can be
recognized.

D3

Carrier Detect-This bit contains the
state of the CD pin at the time of the last
change of any of the External! Status bits
(CD, CTS, Sync/Hunt, Break/ Abort, or
Tx Underrun/EOM). Any change ofstate
of the CD pin causes the CD bit to be
latched and causes an External/Status interrupt. This bit indicates current state of
the CD pin immediately following a Reset
External/Status Interrupt command.

The Break bit is reset when the termination of the Break
sequence is detected in the incoming data stream. The
termination of the Break sequence also causes the External/Status interrupt to be set. The Reset External/Status Interrupt command must be issued to enable
the break detection logic to look for the next Break
sequence. A single, extraneous null character is present
in the receiver after the termination of a break; it should
be read and discarded.

9-204

210311-001

AP-134

ged with this error. Once the overwritten
character is read, this error condition is
latched until reset by the Error Reset
command. If the MPSC is in the "status
affects vector" mode, the overrun causes
a special Receive Error Vector.

Read Register 1 (RR1)
MSB

LSB

10'1 105 1
D.

D.

I03 : 02 : 0' I I

,

L

DO

ALLs

NT
,

NOTU SED IN ASYNCHRONOUS MODES
PARITY ERROR

. Framing Error-in async modes, a one in
this bit indicates a receive framing error.
It can be reset by issuing an Error Reset
command.

D6

RI OVERRUN ERROR
CRe/FRAMING ERROR
END OF FRAME(SDLCIHDLC MODE)

Read Register 2 (RR2):

DO

Msa

All sent-this bit is set when all characters have been sent, in asynchronous
modes. It is reset when characters are in
the transmitter, in asynchronous modes.
In synchronous modes, this bit is always
set.

LSB

1 va; vs :
V1 :

V4' : V3' >2-; Vl'

L.:';;,:n'::;"':..:'":::,p,=--_ _ _
Vector

D4

D5

Parity Error-if parity is enabled, this bit
is set for received characters whose
parity does not match the programmed
sense (Even/Odd). This bit is latched.
Once an error occurs, it remains set until
the Error Reset command is written.

>0,1
~::~••b~~~ct.
Vector Mode (WA1; 02)

RR2

Channel B

D7-DO

Interrupt vector-contains the interrupt
vector programmed into WR2. If the
"status affects vector" mode is selected,
it contains the modified vector. (See
WR2.) RR2 contains the modified vector
for the highest priority interrupt pending.
If no interrupts are pending, the variable
bits in the vector are set to one.

Receive Overrun Error-this bit indicates that the receive FIFO has been
overloaded by the receiver. The last character in the FIFO is overwritten and flag~

9-205

210311-001

AP·134

APPENDIX B
MPSC-POLLED TRANSMIT/RECEIVE CHARACTER ROUTINES
.
MPSC$RX$INiT: procedute (cmd$port,
clock$rate,stop$bits,parity$type,parity$enable,
rx$char$length,rx$enable,auto$enable,
tx$char$length, tx$enable ,dtr, brk, rts) ;
declare cmd$port
clock$rate
stop$bits
parity$type
parity$enable
rx$char $leng th
rx$enable
auto$enable
tx$char$length
tx$enable
dtr
brk
rts

output(cmd$port)=30H;

byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte;

/* channel reset */

output(cmd$port)=14H;
/* point to WR4. */
/* set clock rate, stop bits, and .parity information */
output(cmd$port)=shl(clock$rate,G) or shl(stop$bits,2) or shl(parity$type,l)
or parity$enable;
output(cmd$port)=13H;
/* point to WR3 */
/* set up receiver parameters */
output(cmd$port)=shl(rx$char$length,6) or rx$enable or shl(auto$enable,5);
output(cmd$port)=15H;
/* point to WR5 */
/* set up transmitter parameters */
output(cmd$port)=shl(tx$char$length,5) or shl(tx$enable,3) or shl(dtr,7)
or shl(brk,4) or shl(rts,l) I
.
end MPSC$RX$INIT;

9-206

210311-001

Ap·134

~IPSC$POLL$RCV$CHARACTER:

declare data$port
cmd$port
character$ptr
character
status
declare char$avail
rcv$ er ror

procedure (da ta$por t, cmd$por t, char acter $ptr) byte;

byte,
byte,
pointer,
,based character$ptr byte,
byte;
literally '1',
literally '70H';

1* wait for input character ready */
while (input(cmd$port) and char$avail) <> 0 do; end;

1* check for errors in received character *1

output(cmd$port)=l;
1* point to RRl *1
if (status:=input(cmd$port) and rcv$error)
then do;
1* read character to clea~ MPSC,*I
character=input(data$port) ;
1* clea~ receiver errors *1
call RECElVE$ERROR(cmd$port,sta'tus);
1* error return - no character avail
return 0;
end;
else do;
character=input(data$port) ;
1* good return - character avail *1
return OFFH;
end;

*1

end MPSC$POLL$RCV$CHARACTER;

MPSC$POLL$TRAN$CHARACTER: procedure(data$port,cmd$port,character);
declare data$port
cmd$port
character

byte,
byte,
byte;

declare tx$buffer$empty literally '4';

1* wait for transmitter buffer empty *1
while not (input(cmd$port) and tx$buffer$empty) do; end;
1* output character *1
output(data$port)=character;
end MPSC$POLL$TRAN$CHARACTER;

RECElVE$ERROR: procedure(crnd$port,status);
declare crnd$port
status

byte,
byte;

output(cmd$port)=30H;

1* error reset *1

1* *** other application dependent

error processing should be placed here

*** *1

end RECElVE$ERROR;

9-207

210311-001

AP·134

TRANSMIT$BUFFER: procedure(buf$ptr,buf$length)
declare
buf$ptr
buf$length

pointer,
byte;

/* set up transmit buffer pointer and buffer length in global variables for
interrupt service */
tx$buffer$ptr=buf$ptr;
transmit$length=buf$length;
/* setup status for not complete */
/* transmit first character */
/* first character transmitted */

transmit$status=not$complete;
output(data$port)=transmit$buffer(O) ;
transmit$ihdex=l;

/* wait until transmission complete or error detected */
while transmit$status = not$complete do; end;
if transmit$status <> complete
' '
then return false;
~lse return true;
end TRANSMIT$BUFFER;

RECEIVE$BUFFER: procedure (buf$ptr,buf$length$ptr);
declare
pointer,
buf$ptr
buf$length$ptr pointer,
buf$length
based buf$length$ptr byte;

/* set up receive buffer pointer in global variable' for interrupt service */
rx$b'uffer $ptr=buf$ptr;
receive$index=O;
receive$status=not$complete;

/* set status to not complete '*/

j* wait until buffer received */

while receive$status = not$complete do; end;
buf$length=receive$leng th ;
if receive$status = complete
then return true;
else return false;

end RECEIVE$BUFFER;

9-208

210311-001

AP-134

MPSC$RECEIVE$CHARACTER$INT: procedure interrupt 22H;

/* ignore input if no open buffer */
if receive$status <> not$complete then return;

/* check for receive buffer overrun */
if receive$index = 128
then receive$status=overrun;
else do;
/* read character from MPSC and place in buffer - note that the
parity of the character must be masked off during this step if
the character is less than 8 bits (e.g., ASCII)
*/
receive$buffer (receive$index) ,character=input (data$port) and 7FH;
receive$index=receive$index+l;
/* update receive buffer index */

/* check for line feed to end line */
if character = line$feed
then do; receive$length=receive$index; receive$status=complete; end;
end;
end MPSC$RECEIVE$CHARACTER$INT;

MPSC$TRANSMIT$CHARACTER$INT: procedure interrupt 20H;

/* check for more characters to transfer */
if transmit$index < transmit$length
then do;
/* write next character from buffer to MPSC */
output(data$port)=transmit$buffer(transmit$index) ;
transmit$index=transmit$index+l;
/* update transmit buffer index */
end;
else transmit$status=complete;
end MPSC$TRANSMIT$CHARACTER$INT;

RECEIVE$ERROR$INT: procedure interrupt 23H;
declare
temp

byte;

output(cmd$port)=l;
receive$status=input(cmd$port) ;
temp=input(data$port) ;
output(cmd$port)=error$reset;

/* temporary character storage */
/* point to RRl */

/* discard character */
/* send error reset */

/* *** other application dependent
error processing should be placed here

*** */

end RECEIVE$ERROR$INT;

EXTERNAL$STATUS$CHANGE$INT: procedure interrupt 21H;
transmit$status=input(cmd$port)
output(cmd$port)=reset$ext$status;

/* input status change information */

/* *** other application dependent
error processing should be placed here

*** */

end EXTERNAL$STATUS$CHANGE$INT;

9-209

210311-001

AP-134 .

APPENDIX.C
INTERRUPT-DRIVEN TRANSMIT/RECEIVE SOFTWARE
declare
1* global variables for buffer manipulation

*1

pointer,
/* pointer to receive buffer */
rx$buff\'!r$ptr
receive$buffer based rx$buffer$ptr(128) byte,
/* indicates receive buffer status *1
byte initial(O),
receive$status
byte,
1* current index into receive buffer *1
i:eceive$index
/* length of final receive buffer *1.
byte,
rece~ve$length
pointer,
/* pointer to transmit buffer *1
tX$buffer$ptr
transmit$buffer based tx$buffer$ptr(128) byte.,
byte initial(O),
1* indicates transmit buffer status *1
transmit$status
/* current index into transmit buffer */
byte,
transmit$index
/* length of buffer to be transmitted */
transmit$length
byte,
cmdSport

datC\$po~t

a$cmd$port
b$cmd$port
line$feed
not$complete
complete
overrun
channel$reset
error$reset
reset$ext$status .

literally
literally
literally
literally
literally
literally

~43H~,
~ 4lH~

literal~y

literally

~OFFH~,
~l~,

1 terally
1 terally
1 terally

~18H~,
~30H~,
~lOH~l

,

~42H~,
~43H~,
~OAH~,
~O~,

9-210

210311-001

AP-134

MPSC$INT$INIT: procedure (clock$rate,stop$bits,parity$type,parity$enable,
rx$char$length,rx$enable,auto$enable,
tx$char$length,tx$enable,dtr,brk,rts,
ext$en,tx$en,rx$en,stat$affects$vector,
config,priority,vector$int$mode,int$vector);
declare
clock$rate
stop$bits
parity$type
parity$enable
rx$char$length
rx$enable
auto$enable
tx$char$length
tx$enable
dtr
brk
rts
ext$en
tx$en
rx$en
stat$aff$vector
con fig
priority
vector$int$mode
int$vector

byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte;

output(b$cmd$port}=channel$reset;

/* 2-bit code for clock rate divisor */

/*
/*
/*
/*
/*

/*

/*
/*
/*

/*
/*
/*
/*

/*
/*
/*

/*
/*
/*

2-bit
i-bit
i-bit
2-bit
l-bit
i-bit
2-bit
i-bit
i-bit
i-bit
i-bit
i-bit
l-bit
2-bit
l-bit
2-bit
i-bit
3-bit
8-bit

code for number of stop bits */
parity type */
parity enable */
receive character length */
receiver enable */
auto enable flag */
transmit character length */
transmitter enable */
status of DTR pin */
data link break enable */
sta tus of RTS pin */
external/status enable */
Tx interrupt enable */
Bx interrupt enable/mode */
status affects vector flag */
system config
int/DMA */
priority flag */
ihterrupt mode code */
interrupt type code */

-

/* channel reset */

output(b$cmd$port}=14H;
/* point to WR4 */
/* set clock rate, stop bits, and parity information */
output(b$cmd$port}=shl(clock$rate,6} or shl(stop$bits,2} or shl(parity$type,l}
or parity$enable;
output(b$cmd$port)=13H;
/* point to WR3 */
/* set up receiver parameters */
output(b$cmd$port}=shl(rx$char$length,6) or rx$enable or shl(auto$enable,5);
output(b$cmd$port)=15H;
/* point to WR5 */
/* set up transmitter parameters */
output(b$cmd$port)=shl(tx$char$length,5) or shl(tx$enable,3) or shl(dtr,7)
or shl(brk,4) or shl(rts,l);
output(b$cmd$port}=12H;
/* set up interrupt vector */
output(b$cmd$port)=int$vector;

/* point to WR2 */

output(a$cmd$port}=12H;
/* point to WR2, channel A */
/* set up interrupt modes */
output(a$cmd$port)=shl(vector$int$mode,3) or shl(priority,2) or config;
output(b$cmd$port)=llH;
/* point to WRl */
/* set up interrupt enables */
output(b$cmd$port)=shl(rx$en,3} or shl(stat$aff$vector,2) orshl(tx$en,l)
or ext$en;
end MPSC$INT$INIT;

9-211

210311-001

AP-134

APPENDIX D
APPLICATION EXAMPLE USING SDK-86

This application example shows the 8274 in a simple
iAPX-86/88 system. The 8274 controls two separate
asynchronous channels using its internal interrupt controIler to request all data transfers. The 8.274 driver ..
software is described which transmits and receives data .
buffers provided by.the CPU. Also, status registers are
maintained in system memory to allow the CPU to
monitor progress of the buffers and error condition.s.

THE HARDWARE INTERFACE.
Nothing could be easier than the hardware design of an
interrupt-driven.8274 system. Simply connect the data
bus lines, a few bus coritrollines, supply a timiI1:g clock
for baud rate and, voila, it's done! For this example, the
ubiquitous SDK-86 is used as. the host CPU system. The
8274 interface is constructed on the wire-wrap area
provided. While discussing the· hardware' interface,
please refer to Diagram 1.
.
Placing the 8274 on the lower 8 bits of the 8086 data bus
allows byte-wide data transfers at even I/O .addresses.
Fotsimplicity, the 8274's CSt input is generated by .
combining the M-IO/ select line with address lineA7 via
a 7432.This places the 8274 address range in mUltiple
spots within the 8086 I/O address space. (While fine for
this example, a more c9mplete address decoding i.s
recommended for actual prototype systems.) The
8086's A I and A2 address lines are connected to the AO
and Al 8274 register select inputs respectively. AIthoug!I other port assignments are possible because of
the overlapping address spaces, the following I/O port
assigriments are used in this example:

Port Function
Data channel A
Command/status A
Data channel B
Command/status B

I/O Address
OOOOH
... 0002H
0004H
0006H

To connect the 8274's interrupt controller into the system an inverter and pull-up resistor are 'needed to convert the 8274's active-low, interrupt-request output,
IRQ, into the correct polarity for the 8086's INTR
interrupt input.' The 8274 recognizes interruptacknowledge bus cycles by connecting the INTA
(INTerrupt Acknowledge) lines of the 8274 and 8086
together.

The 8274 ReaD and WRite lines directly connect to the
. ·respective 8086 lines. The RESET line requires an inverter. The system clock for the 8274 is provided by the
PCLK (peripheral clock) oiJtput of the 8284A clock
generator.
. On the 8274's serial side, traditional 1488 and 1489
RS-232 drivers and receivers are used for the serial
interface. The onhoard baud rate generator supplies the
channel baud rate timing. In this example, both sides of
both channels operate at the same baud rate although
this certainly is not a requirement. (On the SDK-86, the
baud rate selection is hard-wired thrujumpers. A more
flexible approach would be to incorporate an 8253 Programmable Interval Timer to allow .softwareconfigurable baud rate selection.)
That's all there is to it. This hardware interface is
completely general-purpose and supports all ofthe 8274
features except the DMA data trll1lsfer mode which
requires an external DMA controller. Now let's look at
the software interface.

SOFTWARE INTERFACE
In this example, it is assumed that the 8086 has better
things to do rather than continuously run a serial channel. Presenting the software as a group of callable procedures lets the designer include them in the main body
of another program. The interrupt-driven data transfers
give the effect that the serial channels are handled in the
background while the main program is executing in the
foreground. There are five basic procedures: a serial
channel initialization routine and buffer handling
routines for the transmit and receive data buffers of
each channel. Appendix D-l shows the entire software
listing. Listing line numbers are referenced as each
major routing is discussed.
.
The channel initialization routine (INITIAL 8274),
starting witltline #203, simply sets-each channel into a
particular operating mode by loading the command registers of the 8274. In normal operation, once these
registers are loaded, they are rarely changed. (Although
this example assumes a simple asynchronous operating
mode, the concept is easily extended for the byte" and
bit-synchronolJ.s modes.)

9-212

210311-001

Ap·134

CONTROL
LINES

CONNECTOR

ADDRESS
BUS EXPANSION
CONNECTOR

.' (FOR DETAILED DESCRIPTION ON SDK-IItI, REFER TO SDK..S MCB-aS SYSTEM DESION KIT
. ASSEMBLY MANUAL.)

SDK. .

5V

EXPANSION
BUS

40

3a

28

iiii

48

22

iiii

WR

48

21

Wii

INl'A 50

27

INTA

iiC[R

RST
D7

3S

I.

13
I.

D4

D3
D2
Dl

AiDA

tNTA

"

18
17
18

,.

CHANNEL
A

eTSA

CDA

RESeT

12

D. 12
10

DB

RTSA

ClK

3.
18

TxOA

iNT

DB7

DTRA

DB.

751489

8...

DB.

Tx08

DB.

RTSi

DB3
DB2

RxDB

DBI

CTSB

CHANNEL

8

DBO

C5i

cs

DTRB

AO

TiCA

AI

RiCA

'fiC!I
Rxes

iPi
2.

OND
20

PI~Z:""------'---------'

Figure D-1. 8274/SDK-86 Hardware Interface

9-213

210311-001

Ap·134

I

After returning to the main program, all transmitter
data transfers are handled via the transmitter-interrupt'
service routines starting at lines #360 and #443. These
routines start by issuing an End~Of-Interrupt command.
to the 8274. (This command resets the internalinterrupt controller logic ofthe 8274 for this particular
vector and opens the logic' for other internal interrupt
requests. The routines next check the length count. If
the buffer is completely transmitted, the transmitter
empty flag, TX_EMPTY_CHx, is set and a command is
issued to the 8274 to reset its interrupt line. Assuming
that the buffer is not completely transmitted, the next
character is output to the transmitter. In either case, an
interrupt return is executed to return to the main CPU
program.

The channel operating modes are contained in two
tables'Starting with line #163. As the 8274 has only one
command register per channel, the remaining seven
registers are loaded indirectly through the WRO (Write
Register 0) register. The first byte of each table entry is
the register pointer value which is loaded into WRO and
the second byte is the value for that particular register.
The indicated modes. set the 8274 for asynchronous
operation with data, characters 8 bits long, rio parity,
and 2 stop bits. An X 16 baud rate clock is assumed. Also
selected is the "interrupt on all RX character" mode
with a variable interrupt vector compatible with the
8086/8088. The transmitters are enabled and all model
control lines are put in their active state.
In addition to initializing the 8274, this routine also sets
up the appropriate interrupt vectors. The 8086 assumes
the first 1K bytes of memory contain up to 256 separate
interrupt vectors. On the SDK-86 the initial2K bytes of
memory is RAM and therefore must be initialized with
the appropriate vectors. (In a prototype system, this.
initial memory is probably ROM, thus the vector set-up
is not needed.) The 8274 supplies up to eight different
interrupt vectors. These vectors are developed from
internal conditions such as data requests, status
changes, or,error conditions for each channel. The initialization routine arbitrarily assumes that the initial
8214 vector corresponds to 8086 vector location 80H
(memory location 200H). This choice is arbitrary since
the 8274 initial vector location is programmable.
Finally, the initialization routine sets up the status and
flag in RAM. The meaning and use ofthese locations are
'
discussed later.
Following the ini,tialization routi~e are tho~e for the
transmit commands (starting with line #268). Tltese
commands assume that the host CPU has initialized the
publically declared variables for the transmit buffer
pointer, TX_POINTER_CHx, and the buffer length,
TX_LENGTH_CHx. The transmit coinmand routines
simply clear the transmitter ~mpty flag, TX EMPTY
CHx, and load the first character of the buffer intothe
transmitter. It is necessary to load the first character in
this manner since transmitter interrupts are generated
only when the 8274's transmit data buffer becomes
empty. It is the act of becoming empty which generates
the interrupt not simply the buffer being empty, thus the
transmitter needs one character to start.

The receiver commands start at line #314. Like the
transmit commands, it is assumed that the CPU has
initialized the receive-buffer-pointer public variable,
RX_POINTElLCHx. This variable points to the first'
location in an empty receive buffer. The command
routilles clear the receiver ready flag, RX_READY_CHx, and then set the receiver enable bit in the 8274
WR3 register. With the receiver now enabled, any'
received characters are 'placed in .the receive buffer
using interrupt-driven data transfers.
The received data service routines, starting at lines.
#402 and #485, simply place the received character in
the buffer after first issuing the EOI command. The
character is then compared to an ASCII CR. An ASCII
CR causes the routine to set the receiver ready flag,
RX_READY _CHx, . and . to disable the receiver. The
CPU can interrogate this flag to determine when the'
buffer contains a new line of data. The receive buffer
'pointer, RX_POINTER_CHx, points to the last
received character and the receive counter, RX_COUNTER_CHx, contains the length.
That compietes our discussion of the command routines
and their associated interrupt service, routines. Although not used by the commands, two additional service routines are included for completeness. These
routines handle the error and status-change interrupt
vectors.
The error service routines, starting at lines #427 and
#510, are vectored to if a special receive condition is
detected by the 8274. These special receive conditions
include parity, receiver overrun, and framing errors.
When this vector is generated, the error condition is;
indicated in RRI (Read Register 1). The error service
routine issues an E01 command, reads RR1.and places
it in the ERROR_MSG_CHx variable, and then issues

The host CPU ~an monitor the transmitter empty flag,
TX_EMPTY_CHx, in order to determine wheri transmission of the buffer is complete. Obviously, the CPU
should only .call the command routine after' first checking that the empty flag is set.
9-214

210311-001

inter

AP-134

a reset error command to the 8274. The CPU can monitor the error message location to detect error conditions. The designer, of course, can supply his own error
service routine.

read RRO, place its contents in the STATUS_MSG_CHx variable and then issue a reset external status
command. Read Register 0 contains the state of the
modem inputs at the point of the last change.

Similarily, the status-change routines (starting lines
#386 and #469) are initiated by a change in the modemcontrol status lines CTS/, COl, or SYNDET/. (Note
that WR2 bit 0 controls whether the 8274 generates
interrupts based upon changes in these lines. OurWR2
parameter is such that the 8274 is programmed to ignore
changes for these inputs.) The service routines simply

Well, that's it. This application example has presented
useful, albeit very simple, routines showing how the
8274 might be used to transmit and receive buffers using
an asynchronous serial format. Extensions for byte- or
bit-synchronous formats would require no hardware
changes due to the highly programmable nature of the
8274:s serial formats.

8274 APPLICATION BRIEF PROGRAM
MCS-86 I'IACRO ASSEIfBlER

AS'INCB

ISIS-II I1CS-86 I'IACRO ASSEMBlER Y2.1 AS5EI1Bl.Y OF PIOOllE AS'OCB
OBJECT I'IOOUlE PLACED IN :FLASYNCB. OBJ
ASSEMBLER INYOKED B'I: A5II86: F1: ASYNCB. SRC
LOC OBJ

LINE
1
2

j

*********************~*****************

;*

3

;*

4
5
6
7
8

;*
;*
;*

9
19
11

12
13

14
15

16
17

18

19
29
21

22
23
24
25
26

27
29
29
39

•••• I I I I 11 I I I II , ....

8274 fIPI'llCRTIOO BRIEF PROGRRI'I

*

*

;* THE 8274 IS

INITIALIZED FOR SIIf'tE ~ SERIAL
;. FORI'JAT AND VECTORED INTERRUPT-DRlYEN DATA TRfI6FERS.
;* THE INITIALIZRTIoo RWTII£ ALSO LOf()S THE 8886'S INTERRlPT
;* VECTOR TOOLE FROPI THE COOE SEGI£NT INTO L(Jj RAI1 00 11£
;* SDK-86. THE TRIII5IIITTER AND RECEIVER 1ft: LEFT ENfRED.

i*

;* FOR TRfIISItIT, 11£ CPU PASSES IN I1EI«lRi' THE POINTER OF A
;* BtfFER TO TRANSI1IT AND 11£ BYTE LEI«lTH OF THE BIfFER.
;* THE DATA TRANSFER PROCEED USING INTERRUPT-DRlYEN TRfI6FERS.

;* R STATUS BIT IN IEIO!Y IS SET Ii£N IF IIlfFERS 15 Elf'TY.
;*
;* FOR RECEIVE, THE CPU PASSES 11£ POINTER OF R BUFFER TO FlU.
;* THE BlfFER IS FIUED LtlTIL R 'CR..CIf/' CHARf(;TER IS RECEIVED.
;* R STRTUS BIT IS SET AND 11£ CPU lIlY READ THE RX POINTER TO
;* DETERlfII£ THE lOCRTIOO OF THE lAST CIflRA::TER.
;+
;* fU RWTlNES fft AS5MD TO EXIST IN 11£ SAI'IE COOE SEGIENT.
;* CALL'S TO 11£ SERVICE RWTII£~ ARE AS5MD TO BE 'SHORT' OR
;* INTRASEGI£NT (OOlY 11£ RETIRI ~S IP IS 00 11£ STooO.

*
*
..
*
*
*

*
..
*
*
*
*
..

•

*

*
*
*
*
;****111 ..... 1111111111 ....... 111111111 ....... 111111111111111111 ....

9-215

210311-001

AP·134

1ICS-86 IfICRO RS5EI1BLER

RSI'IO!
LIJ£
31
32
33
34

; PlRIC DECLARATIONS FtJlCOItIfHl ROUTlJ£S

35

36
37
38
39

48
41
42
43
44
45

46
47
48
49
50
51
52
53
54
55
56
57
58
59
68
61
62
63
64
65
66
67

68
69
70
71
72
73
74
75
76
i7
78
79

ae

81
82
83
84

PlRIC
PlRIC
PlRIC
PlRIC
PlRIC

INlTlfL8274
TJLCOlt'ftl>-CHS
TJLCOItIfHl_CIIA
RlLCOI1IRI>-Illl
RlLCOltlANILCIIA

; INITIALIZATION ROUTINE
; TX BlfFER rotIfIII) CHAlH:L
; IX BUFFER COI1IIAIf) CHANNEL
; RX BlfFER COI1I1ANO CHANNEL
; RX SUFFER COItflNO ClMEL

B
A
B
A

; PlRIC DEClARATIONS FOR STATUS VARIABLES
PlRIC
PlRIC
PlaIC
PUBLIC
PlaIC
PlaIC
PlRIC
Pt!IlIC
PUBLIC
PUBLIC.

RlLREIDY-CHB
Rll.REID'''-CHA
Tx...EllPTY-CHB
Tx..EI1PTY_CIIA
Rll.COIJILCHS
RlLCOIJNLCHA
ERRtJ/_I15G_CHB
ERROR..I15G_CHA
STATUS_II5G..CH8
STATU5JISG..CIIA

; RX REIDV FLAG CIIl
; RX REIDY FLAG CHA
; IX EMPTY FLIVi CHB
; TX EIf'TY FLIVi CHA
; RX IllFFER COltHER CHB
; RX IllFFER COIJNTER CIIA
; ERROR FLAG CHB
; ERRtJI FLIVi CHA
; STATUS FLfKl CHB
; STATUS FLfKl CIIA

; PUBLIC DECLARATIONS FOR VARIABLES PASSED TO TI£ TRANSI1IT
; Ali) RECEIVE COI'iI'IAM)S.
PUBLIC
PUBLIC
PlalC
PUBLIC
PlRIC
PLeLIC

Tli..POINTER..CHB ; IX
IX_LENGTlLCHB ; IX
TJLPOINTEILCIIA ; TX
TlLLEHGTlLCIIA ; TX
Rli..POINTEILCHB ; RX
RlLPOINTER_CHA·; RX

BUFFER
LENGTH
SUFFER
LENGTH
SUFFER
BLfFER

POINTER FOR CHB
OF BUFFER FOR CHB
POINTER FOR CIIA
OF BUFFER FOR CIIA
POINTER. FOR CHB
POINTER FOR CHA

; 110 PORT ASSIGNIIENTS
; CIfIHl A PORT RSSIGNI'IENTS

DATfLPORLCIIA
COIII1ANO_PORLCHA
STATUS_PORI-GIIA

DATA 110 PORT
PORT
; STATUS PORT

i

; COM/IAN[)

; CHRNNEl B PORT ASSIGNI'IENTS
DATfLPORLCHB
COI9IAIf.l..PORT_CHB
STATUS~PORT _CHB

EIlU
EIlU
EIlU

4
6
COI1P1AIID_PORLCHB

OOH
200H
500H

; ASCII CR CHARACTER CODE
; INT. VECTOR SASE fWRESS
; START LOCATION FOR CODE

; DATA I/O PORT
; COI1MAND PORT
; STATUS PORT

; ~ISC. SYSTEI1 E{lIATES

CR_CHR
EIlU
INT_TABLE_SASE EIlU
CODE_START
EQU

85 +1 $EJECT
86
87
; RAM ASSSIGNI'IENTS FOR DATA SEGMENT
88
~
DATA
SE~NT·
ge

9-216

210311-001

AP-134

I1CS-86 t1ACRO ASSEHBLER

AS'lNCB

LOC OBJ

LINE

9200
9200 eeeo
0202 9888
9294 9888
0206 0009
9200 eeeo
928A 0000
a20C eooe
028E 8880
8218 0088
0212 eooe

91
92
93
94
95
%
97

; VECTOR INTERRIJ>T TABLE - ASSLtlE INITIAL 8274 INTERRUPT
; VECTOR 15 NiJI3ER Il9 (@200ID. FOR EACH VECTOR, THE TABLE
; CONTAINS START LOCATION All) COllE SE~NT REGISTER YfiLUE.
; THE TABLE IS LOADED FROH PROM.

9B

TX_VECTOR-CHB
TX_CS_CHB

99
100
191
192
183
194
185
186
187
109
189
118
111
112

8214 8809

113

8216 8889

114
115
116
117
118
119

9218 9090
821A 9909
821C 0900
821E eeeo

SOURCE

120

ORG

INLTABLUlASE
0
9

i

TX INTERRUPT YECTOR FOR CHB

011

STS_VECTOR_CHB 011
STS_CS_CHB
011

9
8

i

STATUS INTERRUPT

RX..VECTOR_CHB
RX..CS_CHB

a
a

; RX INTERRUPT" VECTOR FOR CHB

DW

ERR_VECTOIUHB 011
ERR_CSJ:l1l
011

8
9

; ERROR INTERRUPT VECTOR FOR CHB

TlLVECTOIUHA
TlLC5..Cffi

011
011

8
8

; TX INTERRtPT VECTOR FOR CHA

STS_VECTORJ:I~ DW
STS_CS_CHA
DW

8
9

; STATUS INTERRUPT VECTOR FOR CHA

RX..VECTOR_CHA

011

ow

8
9

; RX INTERRUPT YECTOR FOR CHR

RX..CSJ:I~

ERIU'ECTOR..CHA 011
ERR..CS_CHA
011

9
8

; ERROR INTERRUPT VECTOR FOR CHA

OW

OW

VEcn~

FOR CHB

121
122

i

MISC RfI1 LOCATIONS· FOR CHANNEL STATUS AND POINTERS

i

CHANNEL B POINTERS fill STATUS

123
8229
8222
8224
8226
822B
9229
822A
822B

9989
0900
9899
9989
ee
99
ee
ee

124
125
126
127

128
129
139
131
132

133

TXJ'OINTER_CHB
TX_LENGTH_CHB
RX..POINTER..CHB
RX..CWlLCHB
TX..£IfPTY-CHB
RlLREAW_CHe
STATUS_HSG_CtIl
ERROR-l'lSG..CHB

011

ow
ow
011
DB
DB
DB
DB

8
8
9
8
9

9
8
8

; TX BUFFER POINTER FOR CHB
i TX BUFFER LENGTH FOR CHB
i RX BUFFER POINTER FOR CH8
i RX LENGTH COlRITER FOR CHB
; TX DONE FLAG
; READY FLAG <1 IF CR-CHR RECEIVED, ELSE 8)
i STATUS CHANGE MESSAGE
; ERROR STATUS LOCATION (8 IF NO ERROR)

134

135
822C
822E
0238
0232
8234
0235
9236
8237

8809
BB88

eeee

BBB8
89
09
00
ee

136
137
138

; CHANNEL A POINTERS AND STATUS
TX_POINTER_CHA
TUENGTH_CHA
RX..POINTER..CHA
RlLCOUNT _CIlA
TX_EMPTY_CHA
RX..READY_CHA
STATUS-"SG..CHA
ERROR..HSG..CHA

139
148
141
142
143
144
145
DATA
146
147
148 +1 $EJECT

011
DW

011
011
DB
DB
DB
DB

8
8
8
8
a
8
8

e

; TX BUFFER POINTER FOR CHA
i TX BUFFER LENGTH FOR CHA
; RX BUFFER POINTER FOR CHA
i RX LENGTH CClJNTER FOR CHA
; TX DONE FLAG
; READY FLAG (1 IF CR-CHR RECEIVED, ELSE 8)
; STATUS CHANGE HESSAGE
; ERROR STATUS LOCATION <8 IF NO ERROR)

ENDS

9-217

210311-001

AP-134

HCS-86 MACRO ASSEMBlER

ASYNCB

LOC OBJ

LINE

SOIJRCE

149
150
151

ABC

SEG1'1EIff

ASSUI'IE CS:ABC, DS:DATA, 55: DATA
DRG
COOLSTART

152
153

154
155

i

****.+:***********************************************************
*

i*

156

;*

157
158
159

;*

160

PARAI1ETERS FOR CHfHlEL INITIALIZATION

;****************************************************************
. ; CHAIflEL B PARAMETERS

161

162
0500'01
050116
050202
0503 80
05e403

163

; WR1 - INTERRl.f'T ON ALL RX CHR, YARIABLE INT VECTOR, TX INT ENABLE
CMDSTRB DB
1, 1611

164
165

DB

166
167

; WR3 - RX 8 BITSlCIfOINTER-CHS, AND THE BUfFER LENGTH, TUENGTH_CHB,
MUST BE INITIALIZED BY THE CAlLING PROGRAlt
BOTH ITEMS ARE WORD YARIABLES,

'•
•

'*

i*

;****************************************************************
TX-IXII1HfHUHB :
PUSH
AX
,SAYE REGISTERS
PUSH
DI
PUSH
DX
I'IOV
TX_EPlPTY_CHB, 9, CLEAR EI'IPTY FLAG
HOY ,OX, DATA_PORLCHB
,SETUP PORT POINTER

272
273
274

HOv

275

I10Y

276
277
279

OUT

POP
POP
POP
RET

279
280

DI, TX-POINTER_CHB
,GET TX BUFFER POINTER CHS
AL [D I J
,GET FIRST CHARACTER TO TX
DX, AL
; OUTPUT IT TO 8274 TO GET IT STARTED
OX
01
AX
; RETURN

281

282
283

284
285
286
287
288

Il5C8
Il5C8
esc1
B5C2
esc3

59
57
52
C606340200

escs BAOOOO
escs 883E2CB2

289
290
291
292
293
294
295
296
297
298

05CF 8A05
0501 EE
95D25ft

300

95D3 51'
85D4 58
95D5 C3

303

*****************************~********************************
'"

i

;*
"
;'
,"

•

*

"
"
;"****************************************************************

•

TX_COI'IflID_CHA:
PUSH
PUSH
PUSH
HOY
I10V

I10V
I10V
OUT
POP
POP
POP
RET

299
301
382
394
385

306
307
300
309
310

TX CHANNEL A COt1I1AND ROUTINE - ROUTINE 15 CALLED TO
TRANSIIIT A BUFFER, THE BUFFER STARTING ADDRESS,
TllPOINTER-I;HfI, AND THE BUFFER LENGTI{. TX-LENGTH_ClIA,
I'IUsT BE INITIALIZED BY THE CALL ING PRorJRAH.
BOTH ITEMS ARE IotORO VARIABLES,

j

AX
; SAVE REGISTERS
DI
DX
TX..EMPTY-Illft, 9 ; CLEAR EMPTY FLAG
DX, DATfLPORLCHA
; SETUP PORT POINTER
01, TXJ>OINTER_CHA
,; GET TX BUFFER POINTER CHA
AL, [DIl
,GET FIRST CHARACTER TO TX
DX, AL
,OUTPUT IT TO 8274 TO GET IT STARTED
DX
DI
AX

; RETURN

*..*******************************.*****************************
*

;*

,*
,•
"

RX COI1t1AND FOR CHfH£L B - THE CALLING ROUTINE MUST
INITIALIZE RllPOINTER_CHB TO POINT AT THE RECEIIIE
BUFFER BEFORE CALLING THIS ROUTINE,

9-220

., *

210311-001

AP-134

IICS-86 NflCRO flSSEt1BLER

ASYNCB

LOC DB]

LINE

851)6

50

8507 52
8508 .C686..'>982oo
8500 C79626020000
85E3 BAe600
85E6 B003
85£8 EE

95E9 SOCl
85EB EE
85EC SA
95EO 58
85EE C3

;
.' ****************************************************************

314
315
316
317
318
319
328
321
322
323
324
325
326
327

RX_COIU1AND_CHB :
PUSH
AX
; SAVE REGISTERS
PUSH
OX
RX_REAOY-CHB, 0 ; CLEAR RX READY FLAG
IflY
RX_COLlNLCHB, a ;CLEAR RX COUNTER
f10II
OX, CO/1I1f\'ID_PORT_CHB
; POINT fiT C0I1MANO PORT
IIOY
AL, 3
; SET UP FOR WR3
HOY
OX, AL
OUT
AL OC1H
; WR:l - B SlT5/CHR, ENABLE RX
MOIl
Ox, AL
OUT
OX
POP
POP
AX
; RETURN
RET

328

;;*****************************************************************

329
338

85Ef
85EF 58
85F0 52

85F1
85F6
85FC
85FF
8681
0682
e6e4

C6e63S0200
C706320200ae
BAe2BB

331
332
333
334
335
336
337
338
339

;*
;*
;*
j

EE
SOC1
EE
06e5 SA
06e6 58
8687 C3

348

RX COI1IfI/f) FOR CHANNEL A - THE CALLING ROUTINE ~IUST
INITIALIZE RX_POINTER_CHA TO POINT fiT THE RECEIVE
BUFFER BEFORE CALLING THIS ROllTlNE.

*

***************************.************************************

RlLCOlftlANILCHR :
PUSH
fIX
PUSH
OX
f10II
RX_READY _CHIt

348

341
342
343
344
345
346
347

B003

*

311
312

313
851)6

S~CE

RlL~LCHR,

MOIl
MOY

Ox,

f10II

AL, 3

OUT
MOIl
OUT
POP
POP

OX, AL
AL, 0C1H
OX, AL
OX

; SAVE REGI STERS

a ;CLEAR RX READY FLAG
8 ; CLEAR RX COUNTER

C~_PORT _CHA

; POINT AT CottlAND PORT

; SET UP FOR WR3

; WR3 - 8 BITs/cHR, EtflSLE RX

AX

RET;RETLIRN

349
3S0 +1 $EJECT
351
352
i ****************************************************************
353
;*
354
START Of INTERRUPT SERVICE ROUTII£S
355
;*

;*

356

357
358
359

;****************************************************************
; CHAtf£L B TRANSIIIT DATA SERVICE ROUTINE

86e8 52

368

XHTINB: PUSH

8689 57
868A 50

361

869B
06eE
8612
8616
8618
0618
061F
0621

362

PUSH
PUSH

E8e201
FF862BB2
FF1lE2202
7411E
BA8400

363

CALL

8B3E2802

368

8Ae5

369
378

EE

364
365

366
367

INC
DEC
JE
MOIl

IIOV
f10II

ooT

DX
; SAllE REGISTERS
DI
AX
EOI
; SEND EOI COItIAND TO 8274
TX_POINTEILCHB ; POINT TO NEXT CHARACTER
TlLLENGTH_CHB ; DEC LENGTH COUNTER
XIB
; TEST IF DONE
DX, DATA_PORT_CHB
; NOT DONE - GET NEXT CHARACTER
DI, TX.J'OINTER_CHB
AL, [D I J
; PUT CHRRACTER IN AL
DX, AL
; OUTPUT IT TO 0274

9-221

210311-001

Ap·134

II:S-86 IR:RO ASSEI1IUR

ASYNC8

UX: IlIJ

LII£

8622 58
862l5l'
11624 SA
8625 CF
8626 BA86tI8
862!) 8828

371
372
373
374
375
376
377

862Il EE
862C C6862S8281

863158
8632 51'
9633 SA
9634 CF

9635 52
9636 57

9637 58
9638 E8D588
9638 BR86Il8

963E EC
963F A22!I82
9642 8819
9644 EE
964558

964651'
9647 SA
9648 CF

9649
964R
9648
964C
964F
9653

52
57
59
E8C198
8B3E2482
BR9499

9656 EC

9657 8895
9659 FF962482
8651) FF962692
9661 3C9D

389
3B1
382
383
384
385
386
387
388
389
399

; R£ru;!N TO FIllEGROOIII
ox, COIfHLPOU..CIII
; ALL CIIlRACTERS 11M BEEN SOO
; RESET TRANSIUTTER INTERRlPT f'EII)lNG
fL28H

STAIIII: PUSH
PUSH
PUSH
CR.L

lIllY
IN

IIOY
1m

OOT
PCf

POP

397
398

POP

RCYINB: PUSH
PUSH
PUSH

CALL
I10V
/I0Il
IN

498
499

HOY

419
411
412

421
422
423
424
425
426
427
428
429
439

OX
01
AX
EOI
Ox,

; SAVE REGISTERS

; SEll)

EOI

COItfRII)

TO 8274

COIfH)J'(~LCHB

.·;RERD RR8.
fL OX
STATUS..HSG.-CHB. ill
; PUT RR8 IN STATUS I£SSRGE
; SEll) RESET STATUS INT cotIfKI TO 8274
RL. 1911
DX, IlL
; REST(J1E REGISTERS
AX
DI
DX

;CHfH£L B RECEIYEl)"DATA.SERYICE ROUTII£

494
495
496
, 407

429

1X.B'IPTY_CHB. 1 ; 00£ - SO SET TX EItPTY FLAG CHB
; REST(J1E REGISTERS
AX
01
OX
; RE'I'mI TO FOREGROlJI)

IRET

:m

493

Dx.RL

; CIRf£L B STATUS CIflNlE SERVICE ROOTII£

396

414
415
416
417
418
419

52
59
E89498
BA9698

IRET
1m
IIOY

IRET,

393
394
395

413

9677
9678
9679
967C

AX
01
DX

POP
POP
PCf

m

499
491
482

; RESTIIIE REGISTERS

PCf
PCf
PCf

OOT
IIOY

391

9663 759E

966D 8903
966F EE
9678 Bec9
9672 EE
9673 58
967451'
96755A
9676 CF

XIB:

378
379

9665 C696299201
966A BA9699

5W!CE

INC
INC
ClIP
mE
I10Y
IIOV
I10Y

OUT
RIB:

;SAVE REGISTERS
OX
DI
AX
; SEND EOI C(HIfN) TO 8274
EOI
DI. RXJ>OINTER-CHB
; GET RX CHB BUFFER POINTER
DX, DATR-"ORLCHB
AL. OX
)READ CHARACTER
[DIJ. ill
;STORE IN BUFFER
RXJ>OINTER_CHB ; BltIP THE BUFFER PO INTER
RX_COI.RiT _CHS
; IlUtI' THE COUNTER
fLCR-CHR
; TEST IF LAST CHARACTER TO BE RECEIVED?
RIB
Rl'_RERDY~CHB. 1; YES. SET READY FLAG'
ox, COItlANILPORLCHB
; POINT AT COI1MAIt) PORT
AL, 3 '.
; POINT AT WR3

ox, AL

HOY

AL 0C9H

;OISABLE RX

OUT

OX, ill
AX
01

; EITHER WAY, RESTORE REGISTERS

POP
POP
POP

DX

IRET

) RETURN TO FOREGROIJND

; CHANNEL B ERROR SERYICE ROUTINE
ERRINB: PUSH
PUSH
CALL
HOY

• SAVE REGISTERS
AX
; SEND EOI COtlMAND TO 8274
EOI
OX, COIt1fIN[l_PORLCHB

OX

9-222

210311-001

AP·134

1IC5-86 mo RS5EIIIlER

ASYOCB

LOC OOJ

LItE

867F B891

431
432

8681
8682
8683
11686
8688
8689
II68A
8688

EE
EC
A22S82
8838
EE
58
5A
CF

5WICE

433
434

435
436
437
438
439

lIlY
OOT
IN
lIlY
lIlY
OOT

ERROR../1SG..CIe. fl
; SRYE IT IN ERROR FLAG
fl.. 38H
; SE/I) RESET ERROR COIt1fIID TO 8274
Ox. II.

PIP
PIP

AX
OX

fL1
Ox. fl
fLOX

;POINT AT RR1
,iRER)

RR1

; RESTORE

REGISTERS

; RETmI TO FOREGRO\JjI)

IRET

448
868C
II68D
968E
868F
8692
8696
86911
869C

52
57
58
E87E99
FF862C82
FFIlE2E82
748E
BA8IlIl8

869F 883E2C82
86A3 8A95
86A5 EE
Il6A6 58
86A75F
86A8 5A
86A9 CF
86AA BA9299
8611) B828
86AF EE
86B8 C686348291
9685 58
11686 5F
9687 5A
96B8 CF

441
442
443
444
445
446
447

448
449
458
451
452
453
454
455
456
457
458
459
460
461
462
463
464

465

52
57
58
E85199

466
467
46B
469
479
471
472

96BF BA9288

473

96C2
86C3
96C6
96C8
86C9
86CA
86CB
96CC

474
475
476
477
479
479
488
481
482
483
484
485
486
487
488
489
499

9689
86BA
8688
96BC

86CD
86CE
86CF
96D8
9603
96D7

EC
R23692
8819
EE
58
5F
5A
CF

52
57
58
E830ge
8838992

BfI9999

; CIRf£I. A TRANSIIIT DATA SERVICE ROUTlt£

XllTIIfl: PUSH
PUSH
PUSH
Cfl.L
INC
DEC

JE
HOY
HOY
110\1
OUT
POP
POP

XI~:

OX

; SRYE REGISTERS

01
AX
EOI
; SEND EOI COI'IIRII) TO 8274
TX.POINTER.CHA ; POINT TO NEXT CHARACTER
TlLLENGTlLCifl ; DEC LENlTH COIJITER
XIA
;TESTIFOONE
Ox. DATILPORT_CHA
; NOT OONE - GET NEXT CHARACTER
01. 1XJ>OINTER...CHA
AL. [OIl
; PUT CHfRIl:TER IN fl
Ox. AI.
i OOTPUT IT TO 8274
AX
; RESTORE REGISTERS

01

PIP

OX

IRET
IIOV
HOY
ruT
PfOV
POP

; RETURH TO FOREGROOND
OX. COItIAND-PffiLCHA
; fU CHARACTERS fflYE BEEN SEND
. ; RESET TRfIiSI1ITTER INTERRUPT PEN>ING
fl. 28H
OX. AL
TlLEIf>TY_CHA. 1; OONE - SO SET TX EHPTY· FLAG CH8
AX
; RESTORE REGISTERS
DI
OX
; REMN TO FOREGROUND

PIP
POP
IRET

; CHAIf£1. A STATUS CHANGE SERVICE ROUTINE

STAIIfl: PUSH
PUSH
PUSH
Cfl.L
It)V
IN

HOY
HOY
OUT
POP
POP
POP
IRET

DX
; SAVE REGISTERS
DI
AX
EOI
; SEND EOI COIt1flN!) TO 8274
Ox. COI1I1AND_PGRLCHA
fl. OX
;READ RR8
STATUS_"SG_CHfI, II.
; PUT RR9 IN STATUS MESSAGE
fl. 19H
; SEND RESET STATUS INT CIXtIAND TO 8274
Ox. AL
AX
; RESTGRE REGISTERS

01 .
OX

; CHrtNl£L A RECEIVEO DATA SERVICE ROUTINE
RCVIIIA: PUSH
PUSH
PUSH

OX

; SAVE REGISTERS

01
AX

CALL

EOI

MOV
HOY

01. RX-POINTER_CHA

; SEND EOI CO!tffiD TO 8274
i GET RX CHA BUFFER POINTER
Ox. DATA_PGRT_CHA

9-223

210311-001

AP-134

.,;s-86 II\CRO ASSEIIBI.ER

fISYNC8

LOC 08J

UI£

86DR
86IlIl
8600
86E1
II6E5
86E7
96E9
86E£
96F1

EC
8885
FF863882
FF8632e2
JC8I)

75eE
C686358281
BA8288

B883

ClRlACTER

IN

fLDX

492
493
494
495
496
497
498
499

~

[011 fl
; ST!IlE IN IIlfFER
RX.POINTER..CIfI ; BIJI1P TI£ 1IlfFER, POINTER
RlLcruiT_CHA
; BlJ1P 11£ cruiTER
fl,CR.£IIl
; TEST IF LAST ~ TO BE RECEIVED?
RIA
RX..REJt)Y..CHA, 1; YES, SET REIYJY Am
Ox, CM1fH)_PORT-CHR
; POINT AT COIfIFIf) PORT
;POINT AT 1IR3
fL 3·
Ox, fl
fl, 8C8H
; DimE Rli"
Ox, II..
; E1TI£R lilY, RESTORE REGISTERS
AX
01
ox
; RETIRN 10 FOREGROUNI)

see

96F4 B8C8
96F6 EE

5e1

96F8 51'
96F9 SA
86FACF

swa

491

96Fl EE

86F7 58

,--

582
583
584
5Il5
586
587
598

It«:
It«:
CItP
JI£
~

t10Y
~

RIA:

ruT
lIlY
ruT
PfI'
PfI'

Plf
IRET

; R£AI)

; CIRf£l. A ERRoR SERYICE RruTil£

5119
86FB 52

518

96FC 59

511
512

86FI) £81ge9

8789 BA8288
8m B881

8785 EE
8786 EC

8787 ft23782
878R 8818
878C EE '
8780 59
87IIE SA

878FCF

871858
8711 52
8712 BA8288
8715 B838

8717
8718
8719
871R

EE
SA
58
C3

ERRINR: PU5N
PU5N
CAlL

513

lIlY
lIlY
ruT

514
515
516
517
518

IN

519

lIlY
lIlY
ruT

52Il
521
522

PfI'
POP
IRET

OX

DX
; RETlJIN TO

i~-IN1ERRU'T

525

;

526
527
52Il
529
538
531
532

EOI:

537
538
539

RSSEIEl.Y CIJfI.ETE, t«I ERRORS

i

RruTINE -

5EN)5

EOI

F!IlEGRO.JI)

COIMf)

/lIST fl.IIRYS TO ISSlEO ON

TO 8274.

CIfH£J. A.

; SAVE REGiSTERS

PU5N

AX

PUSH

DX

lIlY
lIlY
ruT

Ox, COIIIN)_PORT_CIfI

PfI'
PfI'
RET

m

514
515
516

CM1RIt)

SRYE REGISTERS

; SEND EOI COIMf) TO 8274
EOI
Ox, coiMf>_PORLCIfI
fl,1
; POINT AT RR1
Ox, fl
i REfII) RR1
fLDX
ERRORJ1SUIII, fl
;SAVEIT IN ERROR Am
fL38H
; SEND RESET ERROR COllIN) 10 8274
Ox, AL
AX
i RESTORE REGISTERS

52l
524

THIS

i

AX

; fI..IIIYS FOR CNRIHl. A !!!

fL38H
ox, RL
OX
AX

END OF CODE RruTII£

fEe
END

005

Fruf)

9-224

210311-001

inter

AP-134

REFERENCES

3. Telecommunications and the Computer, J. Martin,
Prentice-Hall, New Jersey, 1976.

1. 8274 Multiprotocol Serial Controller (MPSC) Data
Sheet, Intel Corporation, California, 1980.

4. Technical Aspects of Data Communications, J.
McNamara, DEC Press, Massachusetts, 1977.

2. Basics of Data Communication, Electronics Book
Series, McGraw-Hili, New York, 1976.

5. Miscellaneous Data Communications Standards
-EIA RS-232-C, EIA RS-422, EIA RS-423, EIA
Standard Sales, Washington, D.C.

9-225

210311-001

inter

APPLICATION
NOTE·

AP-145

June 1982 .

@ INTEL CORPClRAnON. 1182

9-226

ORDER NUMBER:· 210403-001

inter

AP-145

INTRODUCTION:
The INTEL 8274 is a Multi-Protocol Serial Controller,
capable of handling both asynchronous and synchronous
communication protocols. Its programmable features allow it to be configured in various operating modes, providing optimization to given data communication
application.
This application note describes the features of the MPSC
in Synchronous Communication applications only. It is
strongly recommended that the reader read the 8274 Data
Sheet and Application Note APl34 "Asynchronous Communication with the 8274 Multi-Protocol Serial Controller" before reading this Application Note. This
Application note assumes that the reader is familiar with
the basic structure of the MPSC, in terms of pin descrip-

OPENING
FLAG
BYTE

ADDRESS'
FIELD(A)

tion, Read/Write registers and asynchronous communication with the 8274. Appendix A contains the software
listings of the Application Example and Appendix B
shows the MPSC Read/Write Registers for quick
reference.
The first section of this application note presents an overview of the various sysnchronous protocols. The second
section discusses the block diagram description of the
MPSC. This is followed by the description of MPSC interrupt structure and mode of operation in the third and
fourth sections. The fifth section describes a hardware/
software example, using the INTEL single board computer iSBC88 / 45 as the hardware vehicle. The sixth section
consists of some specialized applications of the MPSC. Finally, in section seven, some useful programming hints are
summarized.

CONTROL"
FIELD (C)

Figure 1.

DATA
FIELD

FRAME·
CHECK
SEQUENCE

CLOSING
FLAG
BYTE

HOLC/SOLC Frame Format

• Extendable to 2 or More Bytes
•• Extendable to 2 Bytes

SYNCHRONOUS PROTOCOL OVERVIEW

ZERO BIT INSERTION

This section presents an overview of various synchronous
protocols. The contents of this section are fairly tutorial
and may be skipped by the more knowledgeable reader.

The flag has a unique binary bit pattern: 7E HEX. To
eliminate the possibility of the data field containing a 7E
HEX pattern, a bit stuffing technique called Zero Bit Insertion is used. This technique specifies that during transmission, a binary 0 be inserted by the transmitter after any
succession of five contiguous binary 1'so This will ensure
that no pattern of 0 1 1.1 11 lOis ever transmitted between flags. On the receiving side, after receiving the flag,
the receiver hardware automatically deletes any 0 following five consecutive 1's.The 8274 performs zero bit insertion and deletion automatically in. the SDLC/HDLC
mode. The zero-bit stuffing ensures periodic transitions in
the data stream. These transitions are necessary for a
phase lock circuit, which may be used at the receiver end
to generate a receive clock which is in phase to the received data. The inserted and deleted O's are not included
in the CRC checking. The address field is used to address
a given secondary station. The control field contains the
link-level control information which includes implied acknowledgement, supervisory commands and responses,
etc. A more detailed discussion of higher level protocol
functions is beyond the scope of this application note. Interested readers may refer to the references at the end of
this application note.

Bit Oriented Protocols Overview
Bit oriented protocols have been defined to manage the
flow of information on data communication links. One of
the most widely known protocol is the one defined by the
International Standards Organization: HDLC (High
Level Data Link Control). The American Standard Associations' protocol, ADCCP is similar to HDLC. CCITT
Recommendation X.25 layer 2 is also an acceptable version of HDLC. Finally, IBM's SDLC (Synchoronous
Data Link Control) is also a subset of the HDLC.
In this section, we will concentrate most of our discussion
on HDLC. Figure 1 shows a basic HDLC frame format.
A frame consists of five basic fields: Flag, Address, Control, Data and Error Detection. A frame is bounded by
flags - opening and closing flags. An address field is 8 bits
wide, extendable to 2 or more bytes. The control field is
also 8 bits wide, extendable to two bytes. The data field or
information field may be any number of bits. The data
field mayor may not be on an 8 bit boundary. A powerful
error detection code called Frame Check Sequence contains the calculated CRC (Cycle Redundancy Code) for
all the bits between the flags.

The data field may be of any length and content in
HDLC. Note that SDLC specifies that data field be a
multiple of bytes only. In data communications, it is gen9-227

~

210403-001

AP-145

.

,

eraily desirable to transmit data which may be of any content. This requires that data field should not contain
characters which are defined to assist, the transmission
protocol (like opening flag.:7EHin HOLC/SOLC cOmmunications). This property is referred to as "data transparency". In HOLC/SQLC, this code transparency is
made po~sible by Zero Bitinsertion discussed earlier and
the bit orientated nature of the protocol.
s!

. '

.

'.':',

The last field is the FeS (Frame Check Sequence). The
: FCS uses the error detecting techniques called Cyclic Redundancy Check. In SOLC/HDLC, the CCITT-CRC
must be used.
NON-RETURN TO ZERO iNVERTED (NRZI)
"

. ..

..

,

NRZI is a method of clock and data encoding that is well
suited to the HOLC protocol. It allows HOLC protocols to
be used with low cost asynchronous modems. NRZI coding is done at the transmitter to enable clock recovery
from the data at the receiver terminal by using standard
digital phase IOckCdloop techniques. NRZI coding speci~
fiesthat the signal condition dO!ls not change for transmitting a I, while Ii 0 causes a change of state. NRZI coding
ensures that an active data line will have transition at least
every 5-bit times (recaJI Zero Bit insertion), while contiguous O's will cause a change of state. Thus, ZBI and NRZI
encoding makes it possible for a phase lock circuit at the
receiver end.to derive a receive clock (from received data)
which is synchronized to the received data and at the same
time ensure data transparency.
'
'

Byte Synchronous COn1~unication
As the name implies,Byte Synchronous Communication
is a synchronous communication protocol which means
that the transmitting station is synchronized to the receiving station through the recognition of a special sync character or characters: Two examples of Byte Synchronous
protoCol are the IBM Bisync and Monosync. Bisync has
two starting sync characters per message while monosync
has only one sync character. Forthe sake of abrevity, we

HEADER

will only discuss Bisync here. All the discussion is'valid for
MonOsync also. Any exceptions will be. noted. Figure 2
shows atypical Bisync message format;
.
The Bisync protocol is defined for halfdl.!plex communi"
cation between two or more stations ,over pointto point or
multipoint communication lineS. Special characters controllink access, transmission of. data and termination of
transmission operations for the system. A detailed discu$sion of these special control characters (SYN, ENQ,
STX, ITB; ETB, ETX, OLE, SOH; ,6.CKO, ACKl,
WACK, NAK and EOT, etc) is beyond the scope of this
Application Note. Readers interested in more detailed
discussion are directed to the references listed at the end 9f
this Application Note.
As showri in Figure 2, each message is preceded by two
sync characters. Since the sync characters are defined at
the beginning of the message only, the transmitter must
insert fill characters (sync) in order to maintain synchronization with the receiver when no data is being
transmitted.
.
TRANSPARENT TRANSMISSION

Bisync protocol requireS special control characters to
maintain the communication iink over the line. If the data
is EBCDIC encoded,then transparency is ensur~ by the
fact that the data field will not contain any of the bisync
control characters. However, if data does not conform to
,standard character encoding techniq~es, transparency in
bisync is achieved by inse~ting a special character OLE
(Oata Link Escape) before and after a string of characters
which are to be transmitted transparently. This ensures
that any data charaters which match any of the special
characters are not confused for special characters. An example of a transparent block is shown in Figure 3.
In a transparent mode, it is required that the CRC(B~C)
is not performed on special characters. Later on, we will
show how the 8274 can be used to achieve transparent
'
transmission in Bisync mode. '

STXTEXT

ETXOR ETB

Figure 2., Bisync Message Format

DLE

STX

Enter transparent mode

TRANSPARENT TRANSMISSION

DLE

ETX

BCC

return to normal mode
Figure 3. Bisync Transparent Format
9-228

210403-001

Ap·145

BLOCK DIAGRAM

CPU Interface

This section discusses the block diagram view of the 8274.
The CPU interface and serial interface is discussed separately. This will be followed by a hardware example in the
fifth section, which will show how to interface the 8274
with the Intel CPU 8088. The 8274 block diagram is
shown in Figure 4.

The CPU interface to the system interface logic block utilizes the AO, AI, CS, RD and WR inputs to communicate
with the internal registers of the 8274. Figure 5 shows the
address of the internal registers. The DMA interface is
achieved by utilizing DMA request lines for each channel:
TxDRQA' TxDRQB' RxDRQA' RxDRQB' Note that

TxDA

CHANNEL A
TRANSMITTER

DIIQ·7
L...-'--'"

TxCA

CHANNEL A
WRITE
REGISTERS
DCDA

CLK
RESET
RDYB/TxDROA

I

!1

k~;::====~~

CTSA
CONTROLA
CHANNEL
LOGIC

RTSA
SYNDETA

RDYA/RxDROA

~

-

<

IPO/TxDRQa
IP1/RxDROB
INT

~

SYSTEM
INTERFACE
CONTROL
, LOGIC

DTRA

,-"--"-....... CHANNEL A
READ
REGISTERS

 OFFH,
OUTPUT (COMMAND_B_74 I
TABLE_74_B(CI'
C=C+l,
OUTPUT (COMMAND_B_74 I = TABLE_74_B(CI'
C=C+l,
END,
C=O,
DO WHILE TABLE_74_A(CI <> OFFH,
OUTPUT (COMMAND_A_74 I
TABLE_74_A(CI'
C=C+l;
OUTPUT (COMMAND_A_74 I
TABLE_74_A(CI'
C=C+1i

END,
RETURN,
END INITIALIZE_B274'
Figure 18.

Typical MPSC SOLC Initialization 'Sequence

9-241

210403-001

inter

AP-145

Interrupt Routines

For this application, the CPU is run at 8 MHz. The board
is configured to operate the 8274 in SDLC operation with
the data transfer in DMA mode using the 8237 A. 8274 is
configured first in non-vectored mode in which case the
INTEL Priority Interrupt Controller 8259A is used to re, solve priority betweeenvarious interrupting sources on the
board and subsequently interrupt the CPU. However, the
vectored mode of the 8274 is also verified by disabling the
8259A and reading the vectors from the 8274. Software
examples for each case wilJ be shown later.
The application example is interrupt driven and uses
DMA for all data transfers under 8237A control. The
8254 provides the transmit and receive clocks for the
'8274. The 8274 was run at 400K baud with a local loopback, Uumper wire) on Channel A data.The board was
also run at 800K baud by modifying the software as wilJ be
discussed later in the Special Applications section. One
detail to note is that the Rx Channel DMA request line
from the 8274 has higher priority than the Tx Channel
DMA request line. The 8274 master Clock was 4.0 MHz.
The on-board RAM is used to define transmit and receive
data buffers. In this application, the data is read from
memory location 800H through 810H and transferred to
memory location 900H to 910H through the 8274 Serial
Link.The operation is full duplex. 8274 modem control,
pins, CTS and CD have been tied low (active).

The 8274 interrupt routines will be discussed here. On an
8274 interrupt, program branches offtolhe "Main Inter~
rupt Routine". In main interrupt routine, status register
RR2 is read. RR2 contains the modified vector. The cause
of the interrupt is determined by reading the modified bits
of the vector. Note that the 8274'has been programmed in
the non-vectored mode and status affects vector bit has
been set. Depending on the value of the modified bits, the
appropriate interrupt routine is called. See Figure 19 for
the flow diagram and Figure 20 for the source code. Note
that an End of Interrupt Command is issued after servicing the interrupt. This is necessary to enable the lower pri~
ority ~nterrupts.
Figure 21 shows all the interrupt routines called by the
Main Interrupt Routine. "Ignore - Interrupt" as the name
implies, ignores any interrupts and sets the FAIL flag.
This is done because this program is for Channel A only
and we are ignoring any Channel B interrupts. The important thing to note is the Chamiel A Receiver Character
available routine. This routine is called after receiving the
first character in the SDLC frame. Since the ,transfer
mode is DMA, we have a maximum of three character
times to service this interrupt by enabling the DMA
controller.

Software
The software consists of a monitor program and a pro~
gram to exercise the 8274 in the SDLC mode. Appendix A
contains the entire program listing. For the sake of clarity,
each source module has been rewritten ina simple lan- '
guage and will be discussed here individually. Note that
some labels in the actual listings in the Appendix will not
match with the labels here. Also the listing in the Appendix sets up some flags to communicate with the monitor.
Some of these flags are not explained in detail for the reason that they are not pertinent to this discussion. The monitor takes the command from a keyboard and executes this
program, logging any error condition which might occur.

8274 Initialization
The MPSC is initialized in the SDLC mode for Channel
A. Channel B is disabled. See Figure 18 for the initialization routine. Note that WR4 is initialized before setting
up the transmitter and receive parameters. However, it
may also be pointed out that other than WR4, all the other
registers may be programmed in any order. Also SDLCCRC has been programmed for correct operation. An incorrect CRC selection will result in incorrect operation.
Also note that receive interrupt on first receive character.
has been programmed although Channel A is in the DMA
mode.
9-242

IF V2V1VO
IF V2V1VO
IF V2V1VO
IF V2V1VO
IF V2V1VO
IF V2V1VO

0, CALL IGNORE - INTERRUPT
1, CALL IGNORE - INTERRUPT
2, CALL CHB Rx CHAR
3, CALL IGNORE - INTERRUPT
4, CALL IGNORE - INTERRUPT
5, CALL CHA - EXTERNAL CHANGE
INTERRUPT
IF V2V1VO - 6, CALL CHA Rx CHAR
IF V2V1VO - 7, CALL CHA Rx SpECIAL

Figure 19. Interrupt Response Flow Diagram
210403-001

AP-145

1**************************1

1* MAIN INTERRUPT ROUTINE *1

1**************************1
OUTPUT (COMMAND_B_74 I = 2.
TEMP = INPUT (STATUS_B_74 I AND 07H.

1* SET POINTER' TO 2*1
1* READ INTERRUPT VECTOR *1
1* CHECK FOR CHA INT ONLY*I

1* FOR THIS APPLICATION CH B INTERRUPTS ARE IGNORED*I
DO CASE TEMP.
IGNORE_INT.
CALL
1* V2V1VO = 000*1
CALL
IGNORE_INT.
1* V2V1VO = 001*1
CALL
CHB_RX3HAR.
1* V2V1VO
010*1
IGNORE_INT.
CALL
1* V2V1VO = 011*1
IGNORE_INT.
CALL
1* V2V1VO = 100*1
CHA_EXTERNAL_CHANGE.
CALL
1* V2V1VO
101*1
CHA_R X_CHAR.
CALL
1* V2V1VO = 110*1
CALL
CHA_RX_SPECIAL.
1* V2V1VO = 111*1
END.
OUTPUT (COMMAND_A_74 I =3BH.
1* END OF INTERRUPT FOR B274 *1
RETURN.
END INTERRUPT_B274.

Figure 20. Typical Main Interrupt Routine
1******************************************************1

1* CHANNEL A EXTERNAL/STATUS CHANGE INTERRUPT HANDLER *1

1******************************************************1
CHA_EXTERNAL_CHANGE: PROCEDURE.
TEMP = INPUT (STATUS_A_74 I.
1* STATUS REG 1*1
IF (TEMP AND END_OF_TX_MESSAGEI
END_OF_TX_MESSAGE THEN
TXDONE_S=DONE,
ELSE DO.
TXDONE_S=DONE.
RESUL TS_S=FAIL.
END.
OUTPUT (COMMAND_A_74 I = 10H.
1* RESET EXT/STATUS INTERRUPTS '*1
RETURN.
END CHA_EXTERNAL_CHANGE.
1**********************************************************1
1* CHANNEL A SPECIAL RECEIVE CONDITIONS INTERRUPT HANDLER *1
1*******************************************************~**I

CHA_RX_SPECIAL: PROCEDURE,
OUTPUTICOMMAND_A_74I .. 11
TEMP = INPUT(STATUS_A_741.
IF (TEMP AND END_OF_FRAMEI = END_OFJFRAME THEN
DO.
IF(TEMP AND, 040Hl = 040H THEN
RESULTS_S a FAIL.
1* CRC ERROR *1
RXDONE_S = DONE,
OUTPUT (COMMAND_A_74 I = 30H. I*ERROR RESET*I
END.
ELSE DO.
IF (TEMP AND 20Hl = 20H THEN DO.
RESULTS S = FAIL.
. 1* RX OVERRUN ERROR*I
RXDONEji = DONE.
OUTPUT(COMMAND~A_741 = 30H.
I*ERROR RESET*I
END.
END.
RETURN.
END CHA_RX_SPECIAL,
1*****************************************1

1* CHANNEL A RECEIVE CHARACTER AVAILABLE *1

1*****************************************1
CHA_RX_CHAR: PROCEDURE,
OUTPUTCSINGLE_MASKI = CHO_SEL,
I*ENABLE RX DMA CHANNEL*I
RETURN.
END CHA_RX_CHAR.

Figure 21. 8274 Typical Interrupt Handling Routines
9-243

210403-001

inter

AP·145

It may be recalled that the receiver buffer is three bytes
deep in addition to the receiver shift register. At very high
data rates, it may not be possible to have enough time to
read RR2, enable the DMA controller without overrunning the receiver. In a case like this, the DMA controller
may be left enabled before receiving the Receive Character Interrupt. Remember, the Rx DMA request and interrupt for the receive character appears at the same time. If
the DMA controller is enabled, it would service the DMA
request by reading the received character. This will make
the 8274 interrupt line go inactive. However, the 8259A
has latched the interrupt and a regular interrupt acknowledge sequence still occurs after the DMA controller has
completed the transfer and given up the bus. The 8259A
will return Level 7 interrupt since the 8274 interrupt has
gone away. The user software must take this into account,
otherwise the CPU will hang up.
The procedure shown for the Special Receive Condition
Interrupt cheeks if the interrupt is due to the End of
Frame. If this is not TRUE, the FAIL flag is set and the

program aborted. For a real life system, this must be followed up by error recovery procedures which obviously are
beyond the scope of this Application Note.
The transmission is terminated when the End of Message
(RRO, D6) interrupt is generated. This interrupt is ser-,
viced ill the Channel A External/Status Change interrupt
procedure. For any other change in external status condi7
tions, the program is aborted and a FAIL flag set.

Main Program
Finally, we will briefly discuss the main program. Figure
22 shows the source program. It may be noted that the
Transmit Under-run latch is reset after loading the first
character into the 8274. This is done to ensure CRC transmission at the end of the frame. Also, the first character is
loaded from the CPU to start DMA transfer of subsequent data, This concludes our discussion on hardware
and software example. Appendix A also includes the software written to exercise the 8274 in the vectored mode by
, disabling the 8259A.
'

CHA_SDLC_TEST: PROCEDURE BYTE PUBLIC,
CALL
ENABLE_INTERRUPTS_S. I
INIT_8274_SDLC_S.
CALL
ENABLEI
OUTPUT(COMMAND_A_74I = 28H, 1* RESET TX INT/DMA
*1
OUTPUT (COMMAND_B_74) = 28H, 1* BEFORE INITIALIZING '8237*1
CALL
INIT _8237 _S,
OUTPUT (DATA_A_74) = 55H,
I*LOAD FIRST CHARACTER FROM *1
I*CPU *1

1* TO ENSURE CRC TRANSMISSION. RESET TX UNDER RUN LATCH
OUTPUT (COMMAND_A_74) = OCOH.
RXDONE_S.TXDONE_S=NOT_DONE, 1* CLEAR ALL FLAGS'
RESULTS_S=PASS,
1* FLAG SET FOR MONITOR
DO WHILE TXDONE_S=NOT_DONE. 1* DO UNTIL TERMINAL COUNT
END.

pO

WHILE(INPUT(STATUS~_74)

AND 04H)

*1
*1
*1
*1

<> 04H.

1* WAIT FOR CRC' TO GET TRANSMITTED *1
1* TEST FOR TX BUFFFER EMPTY TO VERIFY THIS*I

END.
DO WHILE RXDONE_S=NOT_DONE.
END.
CALL
STOP 8237 S,
END CHA_SDLC_TEST,

1* DO UNTIL TER,MINAL COUNT

*1

Figure 22. Typical 8274 Transmit/Receive Set-Up in SOLe Mode

9-244

210403-001

inter

AP-145

Vee

CPU

INTr-o(J-~--------~--------------~---------------INTAP---------~----t_----------_r--_+----------------



BOB5 CPU

BOB5 INTERRUPT
MODE 1

IAPX·BB/B6
CPU

BOBB/86
INTERRUPT MODE

Figure 23.

BOB5 INTERRUPT
MODE 3
BOBB/B6
INTERRUPT MODE

BOBB/B6
INTERRUPT MODE

8274 Daisy Chain Vectored Mode

the call vector irrespective of the state of IPI pin. Once a
higher priority MPSC generates an interrupt, its IPO pin
goes inactive thus preventing lower priority MPSCs from
interrupting the CPU. Preferably the highest priority
MPSC should be programmed in 8085 Mode I. It may be
recalled that the Priority Resolve Time on a given MPSC
extends from th falling edge of the first INTA pulse to the
falling edge of the second INTA pulse. During this period,
no new internal interrupt requests are accepted. The
maximum number of the MPSCs that can be connected in
a daisy chain is limited by the Priority Resolution Time.
Figure 24 shows a maximum number of MPSCs that can
be connected in various CPUsystems. It may be pointed
out that IPO to IPI delay time specification is lOOns.

SPECIAL APPLICATIONS
In this section, some special application issues will be discussed. This will be useful to a user who may be using a
mode which is possible with the 8274 but not explicitly explained in the data sheet.

MPSC Daisy Chain Operation
Multiple MPSC can be connected in a daisy-chain configuration (see Figure 23). This feature may be useful in an
application where multiple communication channels may
be required and because of high data rates, conventional
interrupt controller is not used to avoid long interrupt reo
sponse times. To configure the MPSCs for the daisy chain
operation, the interrupt priority input pins (IPI) and inter·
rupt priority output pins (IPO) of the MPSC should be
connected as shown. The highest priority device has its IPI
pin connected to ground. Each MPSC is programmed in a
vectored mode with status affects vector bit set. In the
8085 basIc systems, only one MPSC should be pro·
grammed in the 8085 Mode I. This is the MPSC which
will put the call vector (CD Hex) on the data bus in reo
sponse to the first INTA pulse (See Figure 15). It may be
pointed out that the MPSC in 8085 Mode I will provide

Bisync Transparent Communication
Bisync applications generally require that data transparency be established during communication. This requires
that the special control characters may not be included in
the CRC accumulation. Refer to the Synchronous Proto·
col Overview section for a more detailed discussion on
data transparency. The 8274 can be used for transparent
communication in Bisync communications. This is made

System
Configuration

Priority Resolution Time

Min (ns)

Number of 8274s Daisy Chained
(Max)

8086·1
8086·2
8086
8088
8085-2
8085A

400
500
800
800
1200
1920

5
8
8
12
19

4

Note: Zero wait states have been assumed.

Figure 24. 8274 Daisy Chain Operation

9-245

210403-001

AP-145

possible by the capability of the MPSC to selectively turnon/turnoff the CRC accumulation while transmitting or
receiving. In bisync transparent transmit mode, the special characters (DLE, DLE SYN etc) are excluded from
CRC calculation. This can be easily accomplished by
turning off the transmit CRC calculation (WR5: D5=0)
before loading the special character into the transmit
buffer. If the next character is to be included in the CRC
accumulation, then the CRC can be enabled (WR5:
D5= I). See Figure 25 for atypical flow diagram.

Figure 26.

Figure 25.

Transmit in Bisync transparent Mode

During reception, it is possible to exclude received character from CRC calculation by turning off theReceiveCRC
after reading the special character. This is made possible
by the fact that the received data is presented to receive
CRC checker 8 bit times after the character has been received. During this 8 bit times,the CPU must read the
character and decide if it wants it to be included in the
CRC calculation. Figure 26 shows the typical flow diagram to achieve this.

It should be noted that the CRC generator must be enabled during CRe reception. Also, after reading the CRC
bytes, two more characters (SYNC) must be read before
checking for CRC check result in RRI.
'

Auto Enable Mode
In some data communication applications, it may be required to enable the transmitter ot the receiver when the
CTS or the DCD lines respectively, are activated by the
modems. This may be done very easily by programming
the 8274 into the Auto Enable Mode.The auto enable
mode is set by writing a 'I' to WR3,D5. The function of
this mode is to enable the transmitter automatically when
CTS goes active. The receiver is enabled when DCD goes
active. An in-active state of CTS or DCD pin will disable
the transmitter or 'the receiver respectively. However, the
Transmit Enable bit (WR5:D3) and Receive Enable bit

Receive in Bisync Transparent Mode

(WR3:DI) must be set in order to use the auto enable
mode. In non-auto mode, the transmitter or receiver is enabled if the corresponding bits are set in WR5 and WR3,
irrespective of the state CTS or DCD pins. It may be recalled that any transition on CTS or DCD pin will generate External/Status Interrupt with the corresponding bits
set in RRI. This interrupt can be cleared by issuing a Reset External/Status interrupt command as discussed earlier.
Note that in auto enable mode, the character to be transmitted must be loaded into the transmit buffer after the
CTS becomes active, not before. Any characte~ loaded
into the transmit buffer before the CTS became active will
not be transmitted.

High Speed DMA Operation
In the section titled Application Example,the MPSC has
been programmed to operate in DMA mode and receiver
is programmed to generate an interrupt on the first receive
character. You may recall that the receive FIFO is three
bytes deep. On receiving the interrupt on the first receive
character, the CPU must enable the DMA controller
within three received byte times to avoid receiver over-run
condition. In the application example, at 400K baud, the
CPU had approximately 60 itS to enable the DMA controller to avoid receiver buffer overflow. However, at higher baud rates, the CPU may not have enough time to
enable the DMA controller in time. For example, at 1M
baud, the CPU should enable the DMA controller within
approximately 24 itS to avoid receiver buffer overrun. In
most applications, this is not sufficient time. To solve this
problem, the DMA controller should be left enabled before getting the interrupt on the first receive character
(which is accompanied by the Rx DMA request for the
appropriate channel). This will allow the DMA controller
to start DMA transfer as soon as the Rx DMA request becomes active without giving the CPU enough time to re9-246

210403-001

intJ

AP-145

spond to the interrupt on the first receive character. The
CPU will respond to the interrupt after the DMA transfer
has been completed and will find the 8259A (See Application Example) responding with interrupt level 7, the lowest priority level. Note that the 8274 interrupt request was
sa tisfied by the D MA controller, hence the interrupt on
the first receive character was cleared and the 8259A had
no pending interrupt. Because of no pending interrupt, the
8259A returned interrupt level 7 in response to the INTA
sequence from the CPU. The user software should take
care of this interrupt.

Initialization Sequence
The MPSC initialization routine must issue a channel Reset Command at the beginning. WR4 should be defined
before other registers. At the end of the initialization sequence, Reset External/Status and Error Reset commands should be issued to clear any spurious interrupts
which may have been caused at power up.

Transmit Under-run/EOM Latch

At the end of transmission, the CPU must issue "Reset
Transmit Interrupt/DMA Pending" command in WRO to
reset the last transmit empty request which was not satisfied. Failing to do so will result in the MPSC locking up in
a transmit empty state forever.

In SDLC/HDLC, bisync and monosync mode, the transmit underrun/EOM must be reset to enable the CRC
check bytes to be appended to the transmit frame or transmit message. The transmit under-run/EOM latch can be
reset only after the first character is loaded into the transmit buffer. When the transmitter under-runs at the end of
the frame, CRC check bytes are appended to the frame/message. The transmit under-run/EOM latch can be
reset at any time during the transmission after the first
character. However, it should be reset before the transmitter under-runs otherwise, both bytes of the CRC may not
be appended to the frame/message. In the receive mode in
bisync operation, the CPU must read the CRC bytes and
two more SYNC characters before checking for valid
CRC result in RRl.

Non-Vectored Mode

Sync Character Load Inhibit

In non-vectored mode, the Interrupt Acknowledge pin
(INTA) on the MPSC must be tied high through a pull-up
resistor. Failing to do so will result in unpredictable response from the 8274.

In bisync/monosync mode only, it is possible to prevent
loading sync characters into the receive buffers by setting
the sync character load inhibit bit (WR3:D1 = 1). Caution must be exercised in using this option. It may be possible to get a CRC character in the received message which
may match the sync character and not get transferred to
the receive buffer. However, sync character load inhibit
should be enabled during all pre-frame sync characters so
the software routine does not have to read them from the
MPSC.

PROGRAMMING HINTS
This section will describe some useful programming hints
which may be useful in program development.

Asynchronous Operation

HOLC/SOLC Mode
When receiving data in SDLC mode, the CRC bytes must
be read by the CPU (or DMA controller) just like any other data field. Failing to do so will result in receiver buffer
overflow. Also, the End of Frame Interrupt indicates that
the entire frame has been received. At this point, the CRC
result (RR1:D6) and residue code (RR1:D3, D2, D1)
may be checked.

Status Register RR2
RR2 contains the vector which gets modified to indicate
the source of interrupt (See the section titled MPSC
Modes of Operation). However, the state of the vector
does not change if no new interrupts are generated. The
contents of RR2 are only changed when a new interrupt is
generated. In order to get the correct information, RR2
must be read only after an interrupt is generated, otherwise it will indicate the previous state.

In SDLC/HDLC mode, sync character load inhibit bit
must be reset to zero for proper operation.

EOI Command
EOI Command can only be issued through channel A irrespective of which channel had generated the interrupt.

Priority in OMA Mode
There is no priority in DMA mode between the following
four
signals:
TxDRQ(CHA),
RxDRQ(CHA),
TxDRQ(CHB), RxDRQ(CHB). The priority between
these four signals must be resolved by the DMA controller. At any given time, all four DMA channels from the
8274 are capable of going active.

9-247

AP-145

APPENDIX A
APPLICATION EXAMPLE: SOFTWARE LISTINGS

9-248

210403-001

intJ

Ap·145

P~/M-86

COMPI~ER

iSBC 88/4' 8274

CHANNE~

A

SD~C

TEST

°

SERIES-I II

P~/M-86 V2.
COMPI~ATION OF MODU~E INn _8274_S
OB~ECT MODU~E P~ACED IN :Fl:SINI74.0B~
COMPILER INVOKED BY: PLM86.86 :Fl:SINI74.PLM TITLE(iSBC 8B/4~ 8274 CHANNEL
A SDLC TEST) COMPACT NOINTVECTOR ROM

1*************************************************1
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*

*1
*1
*1
*1
*1
*1
*1
*1
*1
*1

INITIALIZE THE B274 FOR SDLC MODE
1. RESET CHANNEL
2. EXTERNAL INTERRUPTS ENABLED
3. NO WAIT
4. PIN 10 = RTS
5. NON-VECTORED INTERRUPT-B086 MODE
6. CHANNE~ A DMA. CH B INT
7. TX AND RX .. B BITS/CHAR
9. ADDRESS SEARCH MODE
10. CD AND CTS AUTO ENAB~E
11. Xl CLOCK
12. NO PARITY
13.SD~C/HD~C MODE
14.RTS AND DTR
15. CCITT - CRC
16. TRANSMITTER AND RECEIVER ENABLED
17.7EH .. FLAG

*,

*1
*1
*1
,*1
*1
*1
*1
*1
*1

1*************************************************1

INIT _B274_S: 001
$INCLUDE (:Fl:PORTS.PLM)
1*********************************************1
1*
1*
1*

ISBC BB/45 PORT ASSIGNMENTS

*1
*1
*1

1**********************************************1
2

3

DECLARE LIT

~ITERALLY

1* B237A-5

PORTS *1

'LITERA~LY'1

DECLARE CHO_ADDR
CHO_COUNT
CH1_ADDR
CH1_COUNT
CH2_ADDR
CH2_COUNT
CH3_ADDR
CH3_COUNT
STATUS_37
COMMAND_37
REGUEST_REG_37
SINGLE_MASK
MODE_REG_37

PL/M-86 COMPILER

LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT

'oaOH',
'081H',

'082H',
'OB3H',
'OB4H',

'OB5H'.
'OB6H',
'087H',

'OBBH',
'oeSH',
'089H',

'OSAH',
'08BH',

iSBC 8B/45 8274 CHANNEL A SDLC TEST
CLR_BYTEJ'TR_37
TEMP_REG_37
MASTER_CLEAR_37
ALL_MASK_37

LIT
LIT
LIT
LIT

'OBFH'J

LIT
LIT
LIT

'091H',
'092H',

'oeCH',
'08DH',

'08DH',

1* B254-2 PORTS *1

4

DECLARE CTR_OO
CTR_Ol
CTR_02

9-249

'090H',

210403-001

AP-145

CONTROLO_54
STATUSO_54
CTR 10
CTR:ll
CTR12
CONTROL1_54
STATUS1_54

LIT
LIT
LIT
LIT
LIT
LIT
LIT

'093H',
'093H',

'09BH',
. '099H',
'09AH',
'09BH' ,
'09BH';

1* 8255 PORTS *1
DECLARE PORTA_55
PORTB 55
PORTC:55
CONTROL_55

LIT
LIT
LIT
LIT

'OAOH',

'OA1H',
'OA2H',

'OA3H',

1* B274 PORTS *1
6

DECLARE DATA_A_74
DATA B 74
STATUS:A_74
COMMAND _A_7 4
STATUS_B_74
COMMAND_B_74

LIT
LIT
LIT
LIT
LIT
LIT

'OOOH',

'OD1H',
'OD2H',
'OD2H',
'OD3H',

'OD3H',

1* B259A PORTS *1
7

DECLARE STATus_paLL_59
ICW1_59
OCW2_59
OCW3_59
OCW1_59
ICW2_59
ICW3_59
ICW4_59

LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT

'OEOH',
'OEOH',
'OEOH',

'OEOH',
'OEIH',
'OEtH',
'OEIH',

'OE1H',

1* 8274 REGISTER BIT·ASSIGNMENTS *1
1* READ REGISTER 0 *1
B

DECLARE RX_AVAIL
INT-PENDING
TX EMPTY
CARRIER DETECT
SYNC_HUNT
CLEAR_TO_SEND

PL/M-B6 COMPILER

LIT
LIT
LIT
LIT
LIT
LIT

'OtH',
'02H',

'04H',
'OBH',
'10H',
'20H',

iSBC BB/45 8274 CHANNEL A SDLC TEST
END_OF_TX_MESSAGE LH
BREAK_ABORT
LIT

'40H',
'SOH';.

1* READ REGISTER 1 *1
9

DECLARE ALL SENT
PAR I TY _ERROR
RX_OVERRUN
CRC ERROR
END:OF]RAME

LIT
LIT
LIT
LIT
LIT

'OtH',
'10H',
'20H',
'40H',
'SOH';

LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT

'OOH',
'OlH',
'02H',
'03H',
'04H',
'OSH',
'06H',
'07H'J

1* READ REGISTER 2 *1

10

DECLARE TX_B_EMPTY
EXT B -CHANGE
RXj3j~VAIL
RX_B_SPECIAL
TX_A_EMPTY
EXT _A_CHANGE
RX A AVAIL
RX:A:SPECIAL

9-250

210403-001

AP-145

1* 8237 BIT ASSIGNMENTS *1

DECLARE CHO_SEL
CHl _8EL
CH2 SEL
CH3:SEL
WRITE_XFER
READ_XFER
DEMAND_MODE
SINGLE_MODE
BLOCK_MODE
SET_MASK

11

12
13
14
15
16
17
18

1
2

DELAY_S: PROCEDURE PUBLIC,
DECLARE D WORD,

2
2
3

D=-O;

2

DO WHILE D<800H,
D=D+1,
END;
END DELAY _S,

2

DECLARE C

3

19
20

LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT

'OOH',

'01H' ,
'02H',
'03H',
'04H',
'OSH',
'OOH',
'40H',
'BOH',
. i04H'J

PROCEDURE PUBLIC;
BYTE,

$E.JECT

PL/M-86 COMPILER

iSBC 88/45 B274 CHANNEL A SDLC TEST

1* TABLE TO INITIALIZE THE 8274 CHANNEL A AND B *1
1*
1*

FORMAT IS: WRITE REGISTER, REGISTER DATA
INITIALIZE CHANNEL ONLY

*1
*1

21

2

DECLARE TABLE_74_A(*) BYTE DATA
(00H,1BH,
1* CHANNEL RESET *1
OOH, BOH,
1* RESET TX CRC *1
02H, 1lH,
1* PIN 10-RTSB, A DMA, B INT *1
04H,20H,
1* SDLC/HDLC MODE, NO PARITY *1
07H,07EH,
1* SDLC FLAG *1
01H,OBH,
1* RX DMA ENABLE *1
05H,OEBH,
1* DTR, RTS, 8 TX BITS, TX ENABLE, TX CRC ENABLE *1
'06H,55H,
1* DEFAULT ADDRESS *1
03H,OD9H,
1* B RX BITS, AUTO ENABLES, HUNT MODE, *1
1* RX CRC ENABLE *1
OFFH) ,
1* END OF INITIALIZATION TABLE *1

22

2

DECLARE TABLE_74_B(*) BYTE DATA
1* INTERRUPT VECTOR *1
(02H,00H,
1* STATUS AFFECTS VECTOR *1
01H, lCH,
OFFH) ,
1* END *1
1* INITIALIZE THE B254 *1

23
24
25

2

26
27
2B
29
30
31
32

2
2

2

2

OUTPUT (CONTROLO_54) =36H;
OUTPUT(CTR_OO) • LOW(20),
OUTPUT (CTR_OO) a HIGH(20),

1* BAUD RATE
1* BAUD RATE

400K_BAUD*1
400K_BAUD*1

1* INITIALIZE THE B274 *1

3

3
3
3
3

C=O,
DO WHILE TABLE_74_B(C) <> OFFH.
OUTPUT(COMMAND_B_74)
TABLE_74_B(C);
C~C+l'

OUTPUT (COMMAND_B_74) = TABLE_74_B(C),
C=C+l,
END,

9-251

210403-001

inter

AP-145

REFERENCES
1. IBM Document No. GA27-3004-2: General Informiztion - Binary Synchronous Communications
2.

Application Note AP134: Asynchronous Communication with the 8274 Multiple Protocol Serial Controller. Intel Corp., Ca.

3. 8274 MPSC Data Sheet, Intel Corporation, Ca .
. 4.

iSBC 88/45 Hardware Reference Manual, Intel
Corp., Ca.
.

5.

Computer Networks and Distributed Processing by
James Martin. Prentice Hall, Inc., N.J.

9-252

210403-001

AP-145

33
34
35
36
37
38
39
40

2
2
3
3
3
3
3
2

CaO,
DO WHILE TABLE_74_A(C) <> OFFH,
OUTPUT(COMMAND_A_74) '" TABLE_74_AIC),
C-C+l,
OUTPUT (COMMAND_A_74) .. TABLE_74_A(C),
C=C+l,
END,
DELAY_S,
CALL

41
42
43

2

RETURN,
END INIT_8274_SDLC_S,
END INIT_8274_S'

2
1

PL/M-86 COMPILER

iSBC 88/45 8274 CHANNEL A SDLC TEST

MODULE INFORMATION:
CODE AREA SIZE
CONSTANT AREA SIZE
VARIABLE AREA SIZE
MAXIMUM STACK SIZE
213 LINES READ
o PROGRAM WARNINGS
o PROGRAM ERRORS

=
..
..

00A8H
OOOOH
0003H
0006H

168D
OD
. 3D
6D

END OF PL/M-86 COMPILATION

PL/M-86 COMPILER

iSBC 88/45 8274 CHANNEL A SDLC TEST

SERIES-III PL/M-86 V2.0 COMPILATION OF MODULE INIT_8237_CHA
OBJECT MODULE PLACED IN :Fl:SINI37.0BJ
COMPILER INVOKED BY: PLM86.e6 :F1:SINI37.PLM TITLE(iSBC 88/458274 CHANNEL A SDLC
TEST) COMPACT NOINTVECTOR ROM

1************************************************************************1

1*
1*
1*

8237

INITIALIZATION ROUTINE

FOR DMA TRANSFER

*1
*1
*1

/***~********************************************************************1

$NOLIST
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

2
2
2
2
2
2
2
2

2
2
2
2
2

2

OUTPUT (MASTER_CLEAR_37)-0,
OUTPUT(COMMAND_37) .. 20H,
1* EXTENDED WRITE *1
OUTPUT(ALL_MA8K_37) - OFH,
1* MASK ALL REOUESTS *1
OUTPUT(MODE_REG_37) = (SINGLE_MODE OR WRITE_XFER OR CHO_SEL),
OUTPUT(MODE_REG_37) ., (SINGLE_MODE OR READ_XFER OR CH1_SEL),
OUTPUT(CLR_BYTE_PTR_37) ., 0,
OUTPUT(CHO_ADDR) .. 00,
1* RECEIVE BUFF AT 900H *1
OUTPUTlCHO_ADDR) .. 09H,
OUTPUT (CHO_COUNT) ., OH,
OUTPUT(CHO_COUNT) .. 01,
OUTPUT(CH1_ADDR) .. 00,
1* TRANSMIT BUFF AT 800H *1
OUTPUT(CH1_ADDR) - 08H,
OUTPUT (CH1_COUNT) = 010H,
OUTPUT (CH1_COUNT) .. OOH,
9-253

210403-001

inter

Ap·145

1* ENABLE TRANSFER *1
OUTPUTCSINQLEjMASK) • CH1_SEL.
RETURN.
'

27
2S

1* ENABLE TX DMA *1

1* TURN OFF THE 8237 CHANNELS 0 AND 1 *1
30
31
32
33
34
35

1
2

2
2
2
1

STOP_8237_S: PROCEDURE PUBLIC.
OUTPUTCSINQLE_MASK) a CH1_SEL OR SET_MASK.
OUTPUT( S I NQLE_MASK) - CHO _SEL OR SET _MASK.
RETURN.
END STOP_S237_S.
END INIT_8237_CHA.

MODULE INFORMATION:
CODE AREA SIZE
• 004CH
CONSTANT AREA SIZE a OOOOH
VARIABLE AREA SIZE
OOOOH

PL/M-8b COMPILER

7bD
00
00

iSBC 88/45 8274 CHANNEL A SDLC TEST

MAXIMUM STACK SIZE • 0002H
lb3 LINES READ
o PROGRAM WARNINGS
o PROGRAM ERRORS

2D

END OF PL/M-8b COMPILATION
PLfM-86 COMPILER

iSBC 88/45 8274 CHANNEL A SDLC TEST

SERIES-III PL/M-86 V2.0 COMPILATION OF MODULE INTR 8274_S'
OBJECT .MODULE PLACED IN :Fl:SINTR. OBJ
COMPILER INVOKED BY: PLM86.86 :Fl:SINTR.PLM TITLEC;SBC 8S/45 S274 CHANNEL
A SDLC TEST) COMPACT NOINTVECTOR ROM

1******************************************1

1*
*1
1*
S274 I.NTERRUPT ROUTINE
*1
1*
1******************************************1

INTR 8274 S: DO;
$NOLIST DECLARE TEMP BYTE.
DECLARE (RESULTS~S,TXDONE_S,RXDONE S) BYTE EXTERNAL.
DECLARE INT_VEC POINTER AT (140).
DECLARE INT_VEC_STORE POINTER.
DECLARE MASK_59 BYTE.
'OFFH',
DECLARE DONE
LIT
'OOH',
NOT_DONE
LIT
'OFFH',
PASS
LIT
'OOH';
LIT
FAIL

12
13
14
15
16
17

, 1****************************1
1*

IGNORE INTERRUPT HANDLER

*1

1****************************1

IGNORE_INT: PROCEDURE.

IS
19
20
21

2
2
2

RESUL TS._S = FAIL.
RETURN.
END IGNORE_INT.

9-254

210403-001

inter

Ap-145

1******************************************************1
/* CHANNEL A EXTERNAL/STATUS CHANGE INTERRUPT HANDLER */
1******************************************************1
22
23
24
25
26
27
28
29
30
31
32

CHA_EXTERNAL_CHANGE: PROCEDURE,
2
2
2
2
3
3
3
2
2
2

TE'MP = INPUT(STATUS A 74),
/* STATUS REG 1*/
IF (TEMP AND END OF-TX MESSAGE) ~ END_OF_TX_MESSAGE THEN
TXDONE_S=DONE, - ELSE DO,
TXDONE_S=DONE,
. RESUL TS_S=FAIL'
END,
OUTPUT(COMMAND A 74) = 10H, /* RESET EXT/STATUS INTERRUPTS */
RETURN,
- END CHA_EXTERNAL_CHANGE'
$EJECT

PL/M-86 COMPILER

iSBC 88/45 8274 CHANNEL A SDLC TEST

1**********************************************************1
/. CHANNEL A SPECIAL RECEIVE CONDITIONS INTERRUPT HANDLER *1
1**********************************************************1
33
34
35
36
37
38
39
40
41
42
43
44
46
47
48
49
50
51
52

2
2
2
2
3
3
3

3
3
2
3
4
4
4
4
3
2
2

OUTPUT(COMMAND_A_74) = I,
TEMP = INPUT (STATUS_A_74),
IF (TEMP AND ENO_OF_FRAME) = END_OF-FRAME THEN
DO,
IF(TEMP AND 040H) = 040H THEN
RESUL TS_S = FAIL,
1* CRC ERROR *1
RXDONE_5 = DONE,
OUTPUT (COMMAND_A_74) = 30H, I*ERROR RESET*./
END,
ELSE DO,
IF (TEMP AND 20H)
20H THEN DO,
RESULTS S = FAIL,
1* RX OVERRUN ERROR*I
RXDONEji = DONE,
OUTPUT (COMMAND_A_74)
30H, I*ERROR RESET*I
END,
END,
RETURN,
END CHA_RX_SPECIAL,

1********.*********************************1
1* CHANNEL A RECEIVE CHARACTER AVAILABLE *1
I******************~**********************I

53
54
55
56

1
2
2
2

CHA_RX_CHAR: PROCEDURE,
OUTPUT 04H.
1* WAIT FOR CRCTO GET TRANSMITTED *1
1* TEST FOR TX BUFFFER EMPTY TO VERIFY THIS*I
END.
DO WHILE RXDONE_S=NOT_DONE.
1* DO UNTIL TERMINAL COUNT*I
END.

=

47

2

CALL

STOP _8237 _5.

48

2

CALL

DISABLE_INTERRUPTS_S.

49

2

CALL

50

2

RETURN RESULTS_S.

51
52

2
1

1* DO UNTIL TERMINAL COUNT*I

END CHA_SDLC_TEST.
END STEST,

MODULE INFORMATION:
CODE AREA SIZE
0063H
CONSTANT AREA SIZE = OOOOH
VARIABLE AREA SIZE
0003H
MAXIMUM STACK SIZE
0004H
198 LINES READ
o PROGRAM WARNINGS
o PROGRAM ERRORS

99D
OD
3D
4D

END OF PL/M-86 COMPILATION
PL/M-86 COMPILER

iSBC 88/45 8274 CHANNEL A SDLC TEST

SERIES-III PL/M-86 V2.0 COMPILATION OF MODULE VECTOR_MODE
OB.JECT MODULE PLACED IN :F1:VECTOR.OB.J
COMPILER INVOKED BY: PLM86.86 :F1:VECTOR.PLM TITLE(iSBC 88/45 8274 CHANNEL A SDLC TEST)

1*******************************************************************1
1*
1*
1*

8274 INTERRUPT HANDLING ROUTINE FOR
8274 VECTOR MODE
STATUS AFFECTS VECTOR

*1
*1
*1
*/
*/

1*
1*
1*******************************************************************1

9-258

210403-001

inter

AP-145

/*
/*
/*
/*
/*
/*

THIS IS AN EXAMPLE OF HOW 8274 CAN BE USED IN VECTORED MODE.
THE iSBC88/45 BOARD WAS REWIRED TO DISABLE THE PIT 8259A AND
ENABLE THE 8274 TO PLACE ITS VECTOR ON THE DATABUS IN RESPONSE
TO THE INTA SEGUENCE FROM THE 8088. OTHER MODIFICATIONS INCLUDED
CHANGES TO 8274 INITIALIZATION PROGRAM (SINI74) TO PROGRAM 8274
INTO VECTORED MODE (WRITE REGISTER 2A 05=1).

*1

*/
*/
*/
*/
*/

VECTOR_MODE: DO,
SNOLIST
12

DECLARE TEMP BYTE,
DECLARE (RESULTS_S,TXDONE,RXDONE) BYTE EXTERNAL,
DECLARE DONE LITERALLY 'OFFH',
NOT_DONE LITERALLY 'OOH',
PASS
LITERALLY 'OFFH',
FAIL
LITERALLY 'OOH',

13

14

1***********************************************************************1
/*
/*

TRANSMIT INTERRUPT CHANNEL A INTERRUPT WILL NOT BE SEEN IN THE */
DMA OPERATION.
*/

1***********************************************************************1
15
16
17
18

TX_INTERRUPT_CHA:PROCEDURE INTERRUPT 84,
OUTPUT(COMMAND_A_74) = 00101000B,
OUTPUT(COMMAND_A_74) a 00111000B,
END TX_INTERRUPT_CHA'

1
2
2

2

/*RESET TXINT PENDING*/
/*EOI*/

1***********************************************************************1

/*
/*
1*

/*
/*

EXTERNAL/STATUS INTERRUPT PROCEDURE: CHECKS FOR END OF MESSAGE
ONLY. IF THIS IS NOT TRUE THEN THE FAIL, FLAG IS SET. HOWEVER,
A USER PROGRAM SHOULD CHECK FOR OTHER EXT/STATUS,CONDITIONS
ALSO IN RRI AND THEN TAKE APPROPRIATE ACTION BASED ON THE
APPLICATION.

*/
*/

*1

*/
*/

1***********************************************************************1
19
20
21
22
23
24

1

2
2
2
2
3

EXT_STAT_CHANGE_CHA:PROCEDURE INTERRUPT 85,
TEMP = INPUT(STATUS_A_74),
IF (TEMP AND END OF TX MESSAGE) = END_OF_TX_MESSAGE THEN
TXDONE
DONE~ ELSE DO,
TXDONE
DONE,

PL/M-86 COMPILER
25
26
27
28
29
30

iSBC 88/45 8274 CHANNEL A SDLC TEST
FAIL,

3

3
2
2
2

OUTPUT(COMMAND A 74) = 00010000B,
OUTPUT (COMMAND_A_74) = 00111000B,
RETURN,
END EXT_STAT_CHANGE_CHA'

/*RESET EXT STAT INT*/
/*EOI*/

1***********************************************************************1

1*
1*
1*
/*

RECEIVER CHARACTER,AVAILABLE INTERRUPT WILL APPEAR ONLY ON FIRST*I
RECEIVE CHARACTER. SINCE DMA CONTROLLER HAS BEEN ENABLED BEFORE *1
THE FIRST CHARACTER IS RECEIVED, THE RECEIVER REGUEST IS
*1
SERVICED BY THE DMA CONTROLLER.
*1

1************************************************************.***********1
31

1

32

2
2
2

33
34

RX_CHAR_AVAILABLE_CHA:PROCEDURE INTERRUPT 86,
OUTPUT(COMMAND_A_74) = 00111000B,
I*EOI*/
RETURN,
END RX_CHAR_AVAILABLE_CHA'
$EJECT

9-259

210403-001

AP-145

PL/M-86 COMPILER

iSBC 88/45 8274 CHANNEL A SDLC TEST

1***********************************************************************1
1*
SPECIAL RECEIVE CONDITION INTERRUPT SERVICE ROUTINE CHECKS FOR *1
1*
END OF FRAME BIT ONLY. SEE SPECIAL SERVICE ROUTINE FOR NON*1
1*
VECTORED MODE FOR CRC CHECK AND OVERRUN ERROR CHECK.
*1
1***********************************************************************1
35
36
37
38
39
40
41
42
43
44
45
46
47

SPECIAL_RX_CONDITION_CHA:PROCEDURE INTERRUPT 87,
2

OUTPUT (COMMAND_A_74) • 1,
I*POINTER 1*1
TEMP = INP.UT(STATUS_AJ4),
IF (TEMP AND END_OF_FRAMEI = END~OF_FRAME THEN
RXDONE = DONE.
ELSE DO,
RXDONE = DONE,
RESULTS_S ~ FAIL.
END.
OUTPUT (COMMAND_A_74) = 00110000B.
I*ERROR RESET*I
OUTPUT (COMMAND_A_74) - 00111000B.
I*EOI*I
RETURN.

2
2

:2

2
3
3
3
2
2
2
:2

END

48
49
50
51
52
53
54

1
2
2
2
2

55

2

ENABLE~INTERRUPTS:PROCEDURE PUBLIC,
DISABLE.
CALL SETSINTERRUPT(84.TX_INTERRUPT_CHA),
CALL SETSINTERRUPT(85.EXT_STAT_CHANGE_CHA),
CALL SETSINTERRUPT(86.RX_CHAR_AVAILABLE_CHA),
CALL SETSINTERRUPT(87.SPECIAL_RX_CONDITION_CHA).
RETURN.
END ENABLE_INTERRUPTS,

56

:2
2

SPECIAL~X_CONDITION_CHA'

END VECTOR_MODE,
1***************************************************************************1
1***************************************************************************1

MODULE INFORMATION:
CODE AREA SIZE
= 012EH
CONSTANT AREA SIZE - OOOOH
VARIABLE. AREA SIZE - 0001H
MAXIMUM STACK SIZE D 001EH
226 LINES READ
o PROGRAM WARNINGS
o PROGRAM ERRORS

302D
OD
1D
30D

END OF PL/M-86 COMPILATION

9-260

210403-001

inter

AP·145

APPENDIX B
MPSC READ/WRITE REGISTER DESCRIPTIONS

9-261

210403-001

inter

AP-145

·
r

WRITE REGISTER 0 (WRO):
MSB

LSB

1071061051041031021011001
L.OMMANO STATUS POINTER
REGISTER POINTER

o

o
o
o
1
1
1
1

o
1
o
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

NULL CODE
SEND ABORT (SOLC)
RESET EXT S1'ATUSINTERRUPTS
CHANNEL RESET
ENABLE INTERRUPT ON NEXT RX CHARACTER
RESET TXINT OMA PENDING
ERROR RESET
END OF INTERRUPT

NULL CODE
RESET RX CRC CHECKER
RESET TX CRO GENERATOR
RESET TX UNOERRUN·EOM LATCH

WRITE REGISTER 1 (WR1):
MSB

I

LSB

1071061051041031021011001

.

o
o
1
1

I :-1:!l:~~::RUPT
L

OMAENABLE
STATUS AFFECTS VECTOR 1 VARIABLE VECTOR
' - - (CHB ONLY)
0 FIXED VECTOR
(NULL CODE CH A)

0 RxlNT/OMA DISABLE
1 RxlNT ON FIRST CHAR OR SPECIAL CONDITION
OINT ON ALL Rx CHAR (PARITY AFFECTS VECTOR) OR
SPECIAL CONDITION
liNT ON ALL Rx CHAR (PARITY DOES NOT AFFECT
VECTOR) OR SPECIAL CONDITION

' - - 1 WAIT ON Rx, 0 WAIT ON Tx
-

MUST BE ZERO

' - - WAIT ENABLE, 1 ENABLE, 0 DISABLE

210403-001

inter

AP-145

WRITE REGISTER 2 (WR2): CHANNEL A

I

MSB

LSB

107101051041031021011001

o

o
1
1

0
1
0
1

'---.r---'

o
o
1
1

0
1
0
1

BOTH INTERRUPT
AOMABINT
BOTH OMA
ILLEGAL

'- J ~~:g~:~ ~:~~~;:~~:~~~::~~~~~:~m::
BOBS MOOE 1
BOBS MOOE 2
BOBS/BB MOOE
ILLEGAL

- J ~~~T~:go~Jg7~~:.rRUPT
' - - MUST BE ZERO
' - 1 PIN 10 SVNiil:TS
PIN 10RTSB

o

• EXTERNAL STATUS INTERRUPT ONLY IF EXT
INTERRUPT ENABLE IWR1:DO) IS SET

WRITE REGISTER 3 (WR3):

WRITE REGISTER 2 (WR2): CHANNEL B
MSB

LSB

1~IWI~I~I~I~I~IWI

AOOR SRCH MOOE (SOLC)
_

Rx CRC ENABLE

INTERRUPT
VECTOR

ENTER HUNT MOOE
AUTO ENABLES

o
o

Rx5 BITS/CHAR
Rx7 BITS/CHAR
Rx6 BITS/CHAR
RxB BITS/CHAR

9-263

210403-001

AP·145

WRITE REGISTER 4 (WR4):

WRITE REGISTER 5 (WR5):

1 ENABLE PARITY
',0 OISABLE PARITY

Tx CRC ENABLE

EVEN PARITY

o
o
1
1

o
o
1
1

o

o
1
1

o
1
o
1

o
1
o
1

RTS

'---- rgk8~~gE~s

0

1
0
1

' - - - - - - Tx ENABLE

S BIT SYNC CHAR
16 BIT SYNC CHAR
SOLC/HOLC(01111110)FLAG
1 EXTERNAL SYNC MOOE

'-~----- SENO BREAK

o
o

XI CLOCK
XIS CLOCK
X32CLOCK
X64 CLOCK

1

1

0
1

0
1

Tx5
Tx7
Tx6
TxS

BITS OR LESS/CHAR
BITS/CHAR
BITS/CHAR
BITS/CHAR

OrR

WRITE REGISTER 8 (WR8):
MSB

LSB

1071081051041031021011001

"

L~

SI:NIFI~ANT

,LEAST
'
SYNC BYTE (AOORESS
IN SOLC/HOLC MODE)

,WRITE REGISTER 7 (WR7):
MSB

LSB

1071 Osl 051 041 031 021 011 001

,

L' ~OST SI~IFIC~NT
SYNC BYTE (MUST
BE 01111110 IN
sDLe/HOLC MOOE)

9-264

210403-001

intJ

Ap·145

READ REGISTER 0 (RRO):
MSB

LSB

L

1071 DSI DSI 041 031021 011 DOl
Rx CHAR AVAILABLE
INT PENDING (CHA ONLY)
Tx BUFFER EMPTY
CARRIER DETECT
SYNC/HUNT

m
Tx UNDERRUN/EOM}

EXTERNAL
flTATUS
INTERRUPT MODE

BREAK/ABORT

READ REGISTER 1 (RR1):
(SPECIAL RECEIVE CONDITION MODE)
MSB

LSB

X

ID7IDsIDsID4ID3JD21D1D~
LALLSENT

I FIELD BYTE '
PREVIOUS BYTE

o
o
o

0 0
0 1
1 0

o 1 1
1 0 0
1 0 1
1 1 0

2
0
0
0
0
0
0

1 1

1

1

I FIELD BYTE
2ND PREVIOUS BYTE

!}
3
7

RESIDUE DATA
BITS CHAR
MODE

5
8

' - - PARITY ERROR
~

Rx OVERRUN ERROR

' - - CRC/FRAMING ERROR
' - - END OF FRAME (SDLC HDLC MODE)

READ REGISTER 2 (RR2):
MSB

I

,

V71 vsl vsl

Wi

LSB
v3·1 V2-!v1'1 vo·1

.

I

T'.

INTERRUPT
VECTOR

9-265

'VARIABLES IN
STATUS AFFECTS
VECTOR MODE

210403-001

APPLICATION
NOTE

AP-222

November 1984

Asynchronous and SOLe
Communications with 82530

SHARAD GANDHI

. @ Intel Corporation, 1984

Order Number: 231262-001

9-266

ASYNCHRONOUS
ANDSDLC
COMMUNICATIONS WITH

82530

CONTENTS
INTRODUCTION
1. SCC Port Definition
2. Accessing the SCC Registers
3. Initialization fo ASYNC Operation
4. ASYNC Communication in Polling
Mode
'
5. ASYNC Communication in Interrupt
Mode
6. Initialization for SDLC
Communication
7. SDLC Frame Reception'
8. SDLC Frame Transmission
9. SDLC Interrupt Routines
CONCLUSIONS
REFERENCES
APPENDIX A-82530-BAUD RATE
GENERATQRS
APPENDIX B-MODEM CONTROL
PINS ON THE 82350
APPENDIX C-INTERFACING 82530
TO 80186

9-267

231262-001

intJ

AP-222

INTRODUCTION

I. SCC Port Definition

INTEL's 82530, Serial Communications Controller
(SCC), is a dual channel, multi-protocol data communications peripheral. It is designed to interface to high
speed communications lines using asynchronous, byte
synchronous and bit synchronous protoc:ols. It runs up to
1.5 Mbitsl sec, has on-chip baud rate generators and
on-chip NRZI encoding and decoding circuits - very
useful for SOLe communication. This application note
shows how to write II o drivers for the 82530 to do initialization and. data links using asynchronous (ASYNC) and
SOLC protocols. The appendix includes sections to show
how the on-chip baud rate generators could be programmed , how the modem control pins could be used and
how the 82530 could be interfaced to INTEL's 801861 188
processors.

The Figure'l shows how the 4 ports (2 per channel) of
. the SCC can be defined. Note that the sequc:nce of ports
in the ascending order of addresses· is noithe one that is
normally expected. In the ascending order it is: command (B), data (B), command (A) and data (A). In an
80186 - 82530 system, the interconnection is as follows:

This article deals with the software for the following:

The SCC has 16 registers on each of the channels (A
and B). For each channel there is only one port, the
command port, to access all .the registers. The register
;110 can be always accessed directly through the command port. All other registers are accessed indirectly
through register ;110. First, the number of the register to
be accessed is written to the register ;110 - see the statement, in Figure 2: 'output (eLL-command) = re~
no and Ofh·. Then, the desired register is written to or
read out of the register ;110. The Figuie 2 shows 4 procedures: rra and wra, for reading and writing channel A
registers; rrb and wrb, for reading and writing channel
B registers. The read procedures are of the type 'byte' they return the contents of the register being read. The
write procedures require two parameters - the register
number and the value to be written.

1.
2.
3.
4,
5.
6.
7.
8.
9.

SCC port definition
Accessing the SCC registers
Initialization for ASYNC communication'
ASYNC communication in polling mode
ASYNC communication in interrupt mode
Initialization for SOLC communication
SOLC frame reception
SOLC frame transmission
SOLC interrupt routines

The description is written around illustrations of the
actual software written in PLM86 for a 80186 - 82530
system.

80186 pins

PCSn
A1
A2.

CS
D/C
AlB

RD

RD

WR

WR

82530 pins

2. Accessing the SCC Registers

. 1*----..--.. --.. ------. ---------. ---._--.... ---.--------.----. ------------------------ *1
declare ch_b_command literally 'pcs5 + 0', 1*
channel_b command word*;
ch_b_data
literaU", 'pcs5 + 2', 1* sec channel_b data word *1
ch_a_command literall", 'pcs5 + 4'. 1* scc
command word *1
c:h_a_data
i;CC

channel_~

literall", 'pcs5 + 6'1 1* scc channel_a data word *1

1*--------------------------------------------------_·----------------------_*1
231262-1
Figure 1. see Port Definition

9-268

231262-001

inter

AP-222

1*---------------------------------------------------------------------------*1
1* read selected sec
1'1'3:

regi~ter

*1

procedure (reg_no) byte;
dec la1'e reg_no byte.
if (reg_no and Oi'h) () 0
then output(ch_a_commann)
return input(ch_a_command);

reg. __ no and Of'h;

end i"'rai

,orb:

procedure Cre9 __ no) by~e.
declare reg_no byte.

if (reg_"o and O.fh) <:> 0
then output (ch_b_command)
return input(ch_b_command);
end rrb;

1*

wrIte selected sec register

wra:

*1

procedure (reg_no. value);
declare reg_no byte;
declare value byte;

if (reL.no and Ofh) C-' 0
then outPllt (ch_a_commIT"
TRANSMIT
CLOCK

0

TRxC OUT = BR GENERATOR OUTPUT

1

TRxC OUT

= DPLL OUTPUT

TRxC 011
...!.~ TRANSMIT CLOCK

=

...!.r!- TRANSMIT CLOCK
...!...r!!- TRANSMIT CLOCK
...!.....!... TRANSMIT CLOCK

= TRxC PI.N

=

RTxC PIN
DR GENERATOR OUTPUT

= DPLL OUTPUT

r!!-r!!- RECEIVE CLOCK = RTxC PIN
r!!-r!- RECEIVE CLOCK = TRxC PIN

.

..!.~ RECEIVE CLOCK

= BR GENERATOR OUTPUT

...!..J....

=

RECEIVE CLOCK

L -______________

DPLL OUTPUT

RTxCXTAUNOXTAL

231262-10

Figure 1. Write Register 11

9-277

231262-001

inter

Baud
Rate

AP·222

9600
4800
2400
1200
600
300

1
206.333
414.667
831.333
1664.667
3331.333
6664.667

Table 1 BRTC· Baud Rate Time Constant
Baud Rate Factor
16
32
11.021
4.510
24.042
11.021
50.083
24.042
102.167
50.083
206.333
102.167
414.667
206.333

Since only integers can be written into the registers
WRI2/WRI3 this will haye to be rounded off to II
and it will result in an error of:

'071061051041031021011 Do'
' ~I
L

~

fraction
_ 0.021
100 - 0 19bt
- - - X 100 - - - X
- . 70
BRTC
11.021

,

This error indicates that the baud rate signal generated
by the BRG does not proyide the exact frequency required by the system. This error is more serious for
smaller baud rate factors. For asynchronous systems,
errors up to 5% are considered acceptable.

0
0
0
0
1
1
1

0
0
1
1
0
0
1
1 1

Table I shows the BRTC for a 4 MHz serial clock with
yarious baud rates on the Y-axis and baud rate factors
on the X - axis. The constant that is really programmed
into registers WRI2/WR13 is the integer closest to the
BRTC yalue shown in the table.

Register WR 14 is used to select the input clock to the
BRG. See Figure 2.

0
1
0
1
0
1
0

BR GENERATOR ENABLE
BR GENERATOR SOURCE
DTR/REQUEST FUNCTION
AUTO ECHO
LOCAL LOOPBACK

NULL COMMAND
ENTER SEARCH MODE
RESET MISSING CLOCK
DISAB,LE OPLL
SET SOURCE = BR GEN,ERATOR

=

SET SOURCE
RTxC
SET FM MODE
1 SET NRZI MODE

, 231262-11

Figure 2. Write Register 14

Step 2: BRG Output

Step 3: BRG Source Clock

,L

,

Note that for BRTC = 0, BRG output frequency = 1/4 x
Serial Clock Freq.
'

The output of the BRG can be directed to the ReceiYer,
Transmitter and the TRxC output. This is programmed
by setting bits D6 D5, bits D4 D3, and bits Dl DO in
register WRll to 10. See Figure 1. The output of the
BRG can also be directed to the Digital Phase Locked
Loop (DPLL) for the on-chip decoding of the NRZI
,encoded receiyed data signal. This is done by, writing
100 into bits D7 D6 D5 of register WR14 as shown in
,Figure 2.

64
1.255
,4.510
11.021
24.042
50.083
102.167

WRI4 I bit DI = b -+ Clock comes from pin
RTxC
WR14 I bit Dl = 1 -+ Clock comes from System
Clock (PCLK)
On RESET WRI4 I bit Dl = O.
It should be noted that for the case of Bit D I = 0, the
dock comes either :from:
a. Clock on pin RTxC - if WRII I D7 = 0
or b. Crystal on pins RTxC & SYNC
-ifWRll ID7 = I
Step 4: BRG Enable

This is the last step where bit DO of WR 14 is set to start
the BRG. The BRG can also be disabled by resetting
this bit.

9-278

231262-001

intJ

AP·222

APPENDIX B
MODEM CONTROL PINS ON THE 82530
bits for COl and/or CTSI must also be set in WRl5
for the interrupt to be enabled.

Introduction
This article describes how the CTSI and COl pins on
the 82530 behave and how to write software to service
these pins. The article explains when the External
Status Interrupt occurs and how and when to issue the
Reset External Status Interrupt command to reliably
determine the state of these pins.
Bits 03 and 05 of register RRO show the inverted state
of logic levels on COl and CTSI pins respectively. It is
important to note that the register RRO does not always
reflect the current state of the COl and CTSI pins.
Whenever a Reset External Status Interrupt (RESI)
command is issued, the (inverted) states of the COl
and the CTSI pins get updated and latched into the
RRO register and the register RRO then reflect the inverted state of the COl and CTSI pins at the time of
the write operation to the chip. On channel or chip
reset, the inverted state of COl and CTSI pins get
latched into RRO register.
Normally, a transition on any of the pins does not necessarily change the corresponding bites) in RRO. In certain situations it does and in some cases it does not. A
sure way of knowing the current state of the pins is to
read the register RRO after a RESI command.
There are two cases:
I. External Status Interrupt (ESI) enabled.
II. Polling (ESI disabled).

Case I: External Status Interrupt (ESI) Enabled
Whenever ESI is enabled, an interrupt can occur whenever there is a transition on COlor CTSI pins - the IE

In this case, the first transition on any of these pins will
cause an interrupt to occur and the corresponding bit in
RRO to change (even without the RESI command). A
RESI command resets the interrupt line and also latches in the current state of both the COl and the CTSI
pins. If there was just one transition the RESI does not
really change the contents of RRO.
If there are more than one transitions, either on the
same pin or one each on both pins or mUltiple on both
pins, the interrupt would get activated on the first transition and stay active. The bit in RRO corresponding
only to the very first transition is changed. All subsequent transitions have no effect on RRO. The first transition, in effect, freezes all changes in RRO. The first
RESI command, as could be expected, latches the final
(inverted) state of the COl and CTSI pins into the
RRO register. Note that all the intermediate transitions
on the pins are lost (because the response to the interrupt was not fast enough). The interrupt line gets reset
for only a brief moment following the first RESI command. This brief moment is approximately 500 ns for
the 82530. After that the interrupt becomes active
again. A second RESI command is necessary to reset
the interrupt. Two RESI commands resets the interrupt
line independent of the number of transitions occurred.

Whenever operating with ESI enabled, it is recommendable to issue two back-to-back RESI commands
and then read the RRO register to reliably determine
the state of the COl and CTSI pins and also to reset
the interrupt line in case multiple transitions may have
occurred.

SUBSEQUENT
TRANSITIONS

RESET

231262-12

State Diagram

9-279

231262-001

inter
Case II: Polling RRO for COl and CTSI Pins

CONCLUSIONS

If RRO is po.lIed fo.r determining the state o.f the CD/

Register RRO do.es no.t always reflect the current (inverted) state o.f the CD/ and CTS/ pins. The mo.st reliable way to. determine the state o.f the pins in interrupt
Dr po.lling mDde is to' issue two. back-to.-back RESI co.mmands and then read RRO. While po.lling, the seco.nd
RESI is redundant but harmless. When issuing the
back-to.-back RESI co.mmands to. 82530 no.te that the
separatiDn between the twO. write cycles sho.uld be at
least 6 CLK + 200 ns; o.therwise the seco.nd RESI will
be igno.red.

and CTS/ pins, then the External Status Interrupt
(ESI) is kept disabled. In this case the bits in RRO may
nDt change even fo.r the first transitio.n. The best way to.
handle this case to. always issue a RESI co.mmand befo.re reading in the RRO register to. determine the state
Df CD/ and CrS/ pins. NDte, hDwever, if two. back-to.back RESI cDmmands were to. be issued every time befo.re reading in the RRO register, the first subsequent
transitio.n will change the co.rrespDnding bit in RRO.
The state diagram abo.ve iIIustrates'ho.w each transitiDn
o.n CD/and CTSI pinsam:6t the 82530 and what effect
the RESI command has.

State 0
It is entered o.n reset. No. ESI due to. CTS/ Dr CD/
are pending in this state. Any transitio.n Dn CTS/ Dr
CD/ pins lead to. the state 1 accompanied by an immediate change in the RRO register.

State 1
Interrupt is active (if enabled). If a RESI co.mmand
is issued, state 0 is reached where interrupt is again
inactive. HDwever, a further transitio.n'o.n CTS/ Dr
CD/ pin leads to. state 2 without an immediate
change in RROregister.

State 2
Interrupt is active (if enabled). Any further. transitiDns have no. effect. A RESI co.mmand leads to.
state I, tempo.rarily making the interrupt inactive.

9-280

231262-001

AP-222

APPENDIX C.
Interfacing 82530 to 80186
INTRODUCTION

FOUR TTL PACKAGE INTERFACE

The 82530 is Intel's new sophisticated dual channel
multiprotocol serial communications controller. It can
run up to 1.5 Mb/s in synchronous mode. It has useful
features like on-chip baud rate generators and oscillators. It can be operated in polled, interrupt, half-duplex
DMA, or full-duplex DMA modes. It is also capable of
supplying its own interrupt vector during INTA cycles
(like the 8274).

A method of interfacing the 82530 to the 80186 CPU
with four 14-pin TTL packages is described in this application note. The circuitry is shown in Figure 2. The
TTLs are 74LS04, 74LS74, and 74LS08.
. The interface supports the following operational modes:

Interfacing the 82530 to the 8086/88 and 80186/188
processors requires the external logic shown in Figure 1.

1)
2)
3)
4)
5)

Polled
Interrupt in vectored mode
Interrupt in non-vectored mode
Half-duplex - DMA on both channels
Full-duplex - DMA on one channel

--------,

80186

A

D
D
,
D
D
~

)I

.~

A

K
~

~

,

82530

L. ________

TTL Glue
(74LS04, 74LS08, 74/-$14)
231262-13

Figure 1.80186/82530 Interface

9-281

231262-001

l

00-7

RD
74LS04
RESET

1
74LS04

~

~3

1

~8

21U2~

2

12 74LSOB

4

13

U2 J
--

U3
74LS74
_
WR

2
74LS04

"TI

IS'
c

a;

a

,.

1

!"

:Ir(XI

N
Ut

<0
I
I\.)
(Xl
I\.)

CLKOUT

(0)

0
(XI

5

3

0

a
6

~

5

5

H

6

U2 J

Q
U4 _ I.. 6
CLR Q ~

I

U3

4 74LS08

PR

0
6

4

-

1

Al
PCS6

10

~8

PCS5

9

-I

8

74LS74 0 4
2
PR
Q

U2
-.-

.....-=-i 0

INTAO

~

3

Q

CLR

....
0

5

rl

74LS740 10
PR
Q

~

..,-- 0

~

11

I

9

CD

,_
H

:::.
III
n

l1i[?

74LS04
13
12

::;

n

U3

;:;:

TxOA ~
RxOA
TRxCA"'-.!!
RliCA ~

r-¥.

SY~CA ~ Cha~, el
RTSA
CTSA

~
CDA~

a

I

6

2
5
3

D/C

~

0

INTA

ro-

H

A1~

_

30
7
6

25

RTXODBB

x

f7
~

TRxCB ~
RllcCB
SYNCB ~

o¥s
Channel

~~

RDY/REQA
RDY/REQB
lEI
lEO
CLK

CTSB
DCDB
OTRlREQB

B

~

~_
a

GND

U5

9

5V

ri

~31

74LS04
, ..... 8

p.!-

U3

CLR

~74LS04

'1113
ORQl

11

INTO

10
U3

DRQO

CLOCK

NOTES:

GENERATOR

~

!
9

-

D

= PULLED HIGH THROUGH lK OHM

1.

-

H

3.
4.
5.

U2 = 74LS08
U3 = 74LS04
U4 = 74LS74

....

):.

"'D

•

N
N
N

~

vee ~

9

f-"-

~

DTR/REQA 1O-'1~6_--,

lliL

E2
74LS74n 10
12
PR
~ 0
Q
U4
11
0

CD

c

~

~

r __________-t______.:...-__________________-o E1

0

~

5
8

H

Q jo.!.

CLR
V 13

1

-

OB7
DB6
DB5
DB4
DB3
DB2
DBl
DBO

32
33

--

:;-

4
37
3
38
2
39
1
40

35
~------------~----~3~4~W~

A2

(XI
0)

11

231262-14

AP-222

WR signals, as shown in Figure 3, is equivalent to a
hardware reset of the 82530. This requires ORing of
RESET with RD and WR signals to the 82530.
B) Write
The falling edge of WR should not occur before the
data (to be written to the 82530) is valid (see Figure
4). Nor should the rising edge of WR occur after
the data becomes invalid. This means. that the WR
active phase should occur entirely during the time
when the data is valid. The WR signal from 8086/
88/186/188 goes active before the data is valid. A
D flip-flop and two inverters are used to delay the
WR going to 82530 so that it becomes active after

PRINCIPLES AND CIRCUIT
DESCRIPTION
The principles shown can be used easily to extend full
duplex DMA to both channels. This can in fact be done
using the same 4 TTL packages if an 8288 were also
used in the system-more of that later. The reason why
TTL interfacing is necessary and how it is done is now
described.
A) Reset
The 82530 does not have an explicit hardware reset
input; however, simultaneous activation of RD and

,'--_---1/
r--- ----.j

WR

250 ns

=R=D-------------"'""'"'I\

- - - - - - NO RESET

min

------l.~I""'.

/

\-------11

~I. .

I - - - - RESET - -....

f - - - - - NO RESET - - - - 231262-15

Figure 3. RESET Timing

DATA

DATA VALID
'DW

= 0 min

'WD = 0 min

'wpmln
390 ns
(250 n8 lor -6)
231262-16

Figure 4. WR Signal Timing

9-283

231262-001

AP-222

1~~~--

__________ __
~

~800n.

iNiA
from

80186

INTA
to
82530

U1
PInS

RD to
82530
231262-17

Figure S.INTA Signal Processing

the data is valid. Note that if an 8288 is used to
generate the IOWR signal (as in all big systems),
then the flip-flop and inverters are not required
since IOWR from the 8288 is compatible with the
82530 timing requirements.
C) DMA
The 82530 has two types of DMA request outputs;
also, it has no DACK inputs. This means that the
82530 requires either a two cycle type of DMA
transfer (a la 80186/88 or 8089), or DACK from
the DMA controller (e.g. 8237A) has to be used to
generate CS, AlB, and Die signals.
The first type of DMA request is RDY IREQ. It
can be programmed to function as RDY or
DMAREQ (WR1: Bit 6). It can further be programmed as DMAREQ for transmit or for receive
(WRl: Bit 5). This enables using just one signal for
both the receive and· transmit functions--ideal for
half-duplex operation. This signal needs just an inversion to be fed into the DRQ input of the 80186.
The second DMA request signal is DTR/REQ. It
can be programmed to function as DTR (Data Terminal Ready) or as DMAREQ for transmitter (active on transmitter buffer empty) in WRI4: Bit 2.
Thus, full-duplex DMA is possible by using DTRI
REQ as TxDRQ and RDY/REQ as RxDRQ.

DTR/REQ requires a little over 5 CLK cycles to
become inactive. This would cause the DMA controller to run multiple DMA cycles, causing loss of
data. A flip-flop is set by DTR/REQ whose output
is DRQI to the 80186. The response of the 80186 to
DRQl is a read or write at PCS5 address to do the
DMA TRANSFER. This resets the flip-flop cutting off the DMA request to the 80186 which prevents false DMA transfer.
The DMA configurations supported by the interface
are:
• Half-duplex on Channel A and Channel B
• Full-duplex on Channel A and no DMA on Channel B
D) INTA Processing
80186 generates 2 back-to-back INTA cycles in response to an interrupt and expects to read the interrupt vector on the second cycle. Two flip-flops (Ul)
are used to convert these two cycles to one INTA
cycle and a RD pulse as required by the SCC. See
timing diagram in Figure 5. SCC requires that the
RD pulse is contained within the INTA pulse. This,
alon~ith the pulse width requirements for INTA
and RD signals are easily met.

9,..284

231262-001

AP-222

WAIT STATE REQUIREMENTS
The 82530 requires wait states in a normal single buffered system, as shown in Figure 6. They arise primarily
due to the WR pulse width (= 390 ns) and its timing
with respect to data valid as shown in Figure 4.
SCC·
82530
(4 MHz)

82530-6
(6 MHz)

enabling the DMA Channel 1. This resets the DRQI
flip-flop. A block for clock generator is also shown-although it is not considered a part of the CPU interface.
It may be easily derived from CLKOUT.
The 4 TTL pack interface presented here covers all features of the SCC usage. In many cases the interface
n~ed not be as extensive as shown here and results in
saving board space. Two cases where considerable saving is achieved are:
Case 1: System Using 8288

If the system uses an 8288 bus controller for 80186,
80186-6
(6 MHz)

2

1

80186
(8 MHz)

3

2

pre-processing of WR input is not necessary and the •
IOWC output of 8288 can be fed directly to pin 5 of U2 j
(74LS08). This is because IOWC signal meets the timing requirements of the SCC. Also note, that the interface circuit is then totally independent of the 80186
clock.

Processor

Case 2: System Using Non-Vectored Interrupt
Mode for SCC

Such a system will not need the component UI
(74LS74) nor the AND gate U2 ~s II, 12, 13). Pin 3
of U2 can be fed directly to the RD input of SCC.

Figure 6. Walt State Requirements

It is assumed in this interface design that the 80186
generates the chip seiects and the appropriate number
of wait states. In an 8086/88 system, chip select and
wait states must be generated externally just as for all
other peripheral components attached to the CPU.
The PCS6 chip select output from the 80186 is used to
select the 82530 for all operations except to service
DMA on Channell of the 80186 when PCS5 is used.
Note that it is necessary to pulse PCS5 signal before

CONCLUSION
This four TTL package interface solution is low cost
and compact (1.2 sq; inch). It should satisfy 82530 interfacing for almost all applications. In fact, as already
mentioned, many applications may require only 2-3
TTL packages for interfacing the 82530 to 80186 or to
other INTEL processors.

9-285

231262-001

Other Data Communications
Data Sheets

10

8291 A
GPIB TALKER/LISTENER
• Designed to Interface
Microprocessors (e.g., 8048/49, 8051,
8080/85, 8086/88) to an IEEE Standard
488 Digital Interface Bus
• Programmable Data Transfer Rate
• Complete Source and Acceptor
Handshake

• 1-8 MHz Clock Range
• 16 Registers (8 Read, 8 Write), 2 for
Data Transfer, the Rest for Interface
Function Control, Status, etc.
• Directly Interfaces to External
Non-Inverting Transceivers for
Connection to the GPIB
• Provides Three Addressing Modes,
Allowing the Chip to be Addressed
Either as a Major or a Minor Talker/
Listener with Primary or Secondary
Addressing
• DMA Handshake Provision Allows for
Bus Transfers without CPU
Interven,ion
• Trigger Output Pin
• On-Chip EOS (End of Sequence)
Message Recognition Facilitates
Handling of Multi-Byte Transfers

• Complete Talker and Listener
Functions with Extended Addressing
• Service Request, Parallel Poll, Device
Clear, Device Trigger, Remote/Local
..
Functions
• Selectable Interrupts
• On-Chip Primary and Secondary
Address Recognition
• Automatic Handling of Addressing and
Handshake Protocol
.
• Provision for Software Implementation
of Additional Features

The 8291A is an enhanced version of the 8291 GPIB Talker/Listener designed to interface microprocessors to
an IEEE Standard 488 Instrumentation Interface Bus. It implements all of the Standard's interface functions
except for the .controller. The controller function can be added with the 8292 GPIB Controller, and the 8293
GPIB Transceiver performs the electrical interface for Talker/Listener and Talker/Listener/Controller
configurations.

I8291A
I
I
I

8291A

Vee

I

GPIB DATA
INTERFACE
FUNCTIONS

SH

TO NON·INVERTING

AH

BUS TRANSCEIVERS

TE
LE
SR

I

r/R CONTROL

ATN
jffij

iFC
RS2

Figure 1. Block Diagram

Figure 2. Pin Configuration

Intel Corporation Assumes No Responsibllty for the US8 of Any Circuitry Other Than Circuitry Embodied in an Intet Product. No Other Circuit Patent Licenses .,.Implied.

20,5248-002

©INTEL CORPORATION. 1981.

10-1

8291A

8291A FEATURES AND IMPROVEMENTS

7. To avoid confusion between holdoff 'on DAV versus RFD if a device is readdressed from a talker
'to a listener role or vice-versa during a holdoff,
the "Holdoff on Source Handshake" has been
eliminated. Only "Holdoff on Acceptor Handshake" ,is availa,ble.
'
, '

The 8291A is an improved design of the 8291 GPIB
Talker/Listener. Most of the functions are identical to
the 829,1, and the pin configuratio~ is unchanged.

8. The rsv local message is cleared ~utomatically
upon exit frorriSPAS if (APRS:STRS:SPAS) occurred. The automatic resetting ,of the bit after,
the serial poll is complete simplifies the service
request software.
'

The 8291A offers the following improvements to the
8291 :

9. The SPASC interrupt on the 8291 has been
replaced by the SPC (S~rial Poll Complete) interrupt on the 8291A. SPC interrupt is set on exit
from SPAS if APRS:STRS:SPAS occurred, indicating that the controller has read the busstatus
byte after the 8291A requested service. The
SPASC interrupt was ambiguous because a
controller could enter SPAS and exit SPAS generating two SPASC interrupts without reading
the serial poll status byte. The SPC interrupt also
simplifies the CPU's software by eliminating the
interrupt when the serial poll is half way done.

1. EOI is active with the data as a ninth data bit
rather than as a control bit. This is to comply
with some additions to the 1975 IEEE-488 Standard incorporated in the 1978 Standard ..
2. The BO interrupt is not asserted until RFD is
true. If the Controller, asserts A'fiiJ
synchronously, the data is guaranteed to~
transmitted. If the Controller assert,s ATN
asynchronously, the SH (Source Handshake)
will return to SIDS (Source:ldle State), and the
output data will be cleared. Then, if ATN is
released while the 8291A is addressed to talk, a
new BO interrupt will be generated. This change
fixes,8291 problems which caused data to be
lostor repeated and a problem with the RQS bit
(sometimes cannot be asserted while talking).
3. LLOC and REMC interrupts are setting flipflops
rather than toggling flipflops in tlJe intl:lrrupt
backup register. This ensures that the CPU
knows that these state changes have occurred.
The actual state can be determined by checking
the LLO and REM status bits in the upper nibble
of the Interrupt Status 2 Register.

4. DREQ is cleared'by DACK (RD :1- WR). DREQ on
the 8291 was cleared only by DACK which is not
compatible with the .8089 I/O Processor.
5. The INT bit in Interrupt Status 2 Register is duplicated in bit 7 of the Address 0 Register. If
software polling is used to check for an interrupt, INT in the Address 0 Register should be
polled rather than the Interrupt Status 2 Register. This ensures that no interrupts are lost due
to asynchronous status reads and interrupts.

10. The rtl Auxiliary Command in the' 8291 has been
replaced by Set and Clear rtl Commands in'the
8291A. Using the new commands, the CPU has
the flexibility to extend the length of local mode
or leave it as a short pulse as in the 8291,"
11. A holdoff RFD on GET, SOC, arid DCl feature
has been added to prevent additional busactivity while the CPU is responding to any of
these commands. The feature is enabled by a
new bit (B4) in the Auxiliary Register B.
12. On the 8291, BO could cease to occur upon IFC
going false if IFC 'occurred asynchronously. On
the 8291 A, BO continues to occur after IFC has
gone false even i,f it arrived asynchronously.
13. User's software can distinguish between the
8291 and the 8291A as follows:
a) pon (OOH to register 5)
b) .RESET (02H to register 5)
c) Read Interrupt Status 1 Register. If BO interrupt is set, the device is the 8291. If BO is clear,
it is t,he 8291A.

6. The 8291A's Se'nd EOI Auxiliary Command

This can be used to set a flag in the user's
software which will permit special routines to be
executed for each device. It could be included
as part of a normal initialization procedure as
the first step after a chip reset,.

works on any byte including the first byte of a
message. The 8291 did not assert EOI after this
command for a one byte message nor on two
consecutive bytes.
10-2,

205248-002

'

8291A

Table 1. Pin Description
Pin
No.

Type

Name and Function

0 0 -0,

12-19

I/O

Data Bus Port: To be con·
nected to microprocessor
data bus.

RSo-RS,

21-23

I

Register Select: Inputs. to
be connected to three nonmultiplexed microprocesS'or address bus lines.
Select which of the 8 internal read (write) registers
will be read from (written
into) with the execution of
RO(WR.)

Symbol

CS

8

I

Symbol

Type

Name and Function

I

Reset Input: When high.
forces the device into an
"idle" (initialization) mode.
The device will remain at
"idle" until released by the
microprocessor. with the
"Immediate Execute pon"
local message.

010,-010, 28-35

I/O

8-Blt GPIB Data Port: Used
for bidirectional data byte
transfer between 8291A
and GPIB via non-inverting
external lir)e transceivers.

OAV

36

I/O

Data Valid: GPIB handshake control line. Indicates the availability and
valid!.!,Lof information--.£l:l
the 010,-010, and EOI
lines;

NRFD

37

I/O

Not Ready for Data: GPIB
handshake control line. Inc
dicates the condition of
readiness ofdevice(s) connected to the bus to accept
data.

NOAC

38

I/O

Not Data Accepted: GPIB
handshake control line. Indicates the condition of acceptance of data by the
device(s) connected to the
bus.

RESET

Chip Select: Whl;ln low.
enables reading from or
writing into the register selected by RSo-RS,.
Read Strobe: When low
with CS or DACK low. selected register contents
are read.

-Pin
No.
4

RO

9

I

WR

10

I

Write Strobe: When low
with CS or OACK low. data
is written into the selected
register.

INT (INT)

11

0

Interrupt Request: To the
microprocessor. set high
for request and cleared
when the appropriate register is accessed by the
CPU. May be software configured to be active low.

OREO

6

0

DMA Request: Normally
low. set high to indicate
byte output or byte input in
DMA mode; reset by OACK.

ATN

26

I

Attention: GPIB command
line. Specifies how data on
010 Ii nes are to be i nterpreted.

OACK

7

I

DMA Acknowledge: When
low. resets OREO and
selects data in/data out
register for OMA data
transfer Ectual transfer
done by RD/WR pulse).

IFC

24

I

Interface Clear: GPIB
command line. Places the
interface functions in a
known quiesc'ent state.

SRO

27

0

REN

25

I

Service Request: GPIB
command line. Indicates
the need for attention and
requests an interruptiori of
the current sequence of
events on the GPIB.
Remote Enable: GPIB
command line. Selects (in
conjunction with other
messages) remote or local
control of the device.

EOI

39

I/O

Must be high if OMA is not
used.
TRIG

CLOCK

5

3

0

I

Trigger Output: Normally
low; generates atriggering
pulse with 1 JLsec min.
width in response to the
GET bus command orTrigger auxiliary command.
External Clock: Input.
used only for T,delay
generator. May be 'any
speed in 1-8 MHz range.

10-3

End or Identify: GPIB command line. Indicates the
end of a multiple byte
transfer sequenQ!LQr. in
conjunction with ATN. addresses the device during a
polling sequence.

205248-002

8291A

Table 1. Pin Description (Continued)
Symbol
T!R1

Pin
No.

Type

Name and Function

1

0

External Transceivers
Control Line: Set high to
indicate output data!
signa~n the DIO,-DIO~
and DAV lines and input
signals on the NRFD and
NDAC lines (active source
handshake). Set low to indicate J.!lQ.ut ....9.!ta!signals
on the DIO,-DIO. and DAV
lines and output signals on
the NRFD and NDAC lines
(active acceptor handshake).

Pin
No.

Type

Name and Function

T!R2

2

0

Vee

40

PS.

GND

20

P.S.

External Transceivers
Control Line: Set to indicate output signals on the
EOlline. Set low to indicate
expected input signal on
the EOlline during parallel
poll.
Positive Power Supply:
(5V:±:10%).
Circuit Ground Potential.

Symbol

NOTE:
All signals on the 8291 A pins are specified with positive logic.
However, IEEE 488 specifies negative logic on its 16 signal lines.
Thus, the data is inverted once from 0 0-0, to 0100-010, and
non-inverting bus transceivers should be used.

Figure 3. 8291A System Diagram
IEEE-488 Standard except for the controller function. If an implementation of the Standard's Controller is desired, it can be connected with an Intel® 8292
to form a com plete interface.

THE GENERAL PURPOSE INTERFACE
BUS (GPIB)
The General Purpose Interface Bus (GPIB) is
defined in the IEEE Standard 488-1978 "Digital Interface for 'Programmable Instrumentation."
Although a knowledge of this standard is assumed,
Figure 4 provides the bus structure for quick reference. Also, Tables 2 and 3 reference the interface
state mnemonics and the interface messages
respectively. Modified state diagrams for the 8291A
are presented in Appendix A.

The 8291A handles communication between a microprocessor-controlled device and the GPIB. Its
capabilities include data transfer, handshake
protocol, talker/listener addreSSing procedures,
device clearing and triggering, service request, and
both serial and parallel polling. In most procedures,
it does not disturb the microprocessor unless a byte
has arrived (input buffer full) or has to be sent out
(output buffer empty).

General Description
The 8291A is a microprocessor-controlled device
designed to interface microprocessors, e.g.,
8048/49, 8051, 8080/85, 8086/88 to the GPIB. It implements all of the interface functions defined in the

The 8291A architecture includes 16 registers. Eight
of these registers may be written into by the microprocessor. The other eight registers may be read by
the microprocessor. One each of these read and
10-4

205248-002

8291A

write registers is for direct data transfers. The rest of
the write registers control the various features of the
chip, while the rest of the read registers provide the
microprocessor with a monitor of GPIB states, various bus conditions, and device conditions.

I I I I I I II f

DEVICE A.
ABLE TO

TALK. LISTEN.
AND
CONTROL

==

DATA BUS

le!)catcLllollorl

GPIB Addressing
DEVICE B
ABLE TO
TALK AND

Each device connected to the GPIB must have at
least one address whereby the controller device in
charge of the bus can configure it to talk, listen, or
send status. An 8291A implementation of the GPIB
offers the user three alternative addressing modes
for which the device can be initialized for each application. The first of these modes allows for the device
to have two separate primary addresses. The.second
mode allows the user to implement a single
talker/listener with a two byte address (primary address + secondary address). The third mode again
allows for two distinct addresses but in this instance,
they can each have a ten-bit address (5 low-order
bits of each of two bytes). However, this mode requires that the secondary addresses be passed to
the microprocessor for verification. These three
addressing schemes are described in more detail in
the discussion of the Address ~egisters.

LISTEN

~

(e.g.lloppy

DATA BYTE

disk)

r-

t---

TRANSFER
CONTROL

DEVICE C
ONL Y ABLE

TO LISTEN
le·II"gnal

==
GENERAL

\ll!ne.alo,)

INTERFACE
MANAGEMENT

(
DEVICE 0
ONLY ABLE

TO TALK

==

(e.gcounle,1

__~==}DI01

--

8

OAV
NRFO

NDAC

lFe
ATN
S.O
.EN
EOI

Ftgure 4. Interface Capabilittes and Bus Structure
.---_ _ _r -_ _ _ _ _ _..:.T=a=-bl:..:e..:,2::.:....:I:..:E:..:E:..:E::...4.:.;8:.;8:,cI:.::.;nterface

State Mnemonics

Mnemonic

State Represented

Mnemonic State Represented

ACDS
ACRS
AIDS
ANRS
-APRS

Accept Data State
Acceptor Ready State
Acceptor Idle State
Acceptor Not Ready State
Affirmative Poll Response State

PACS
PPAS
PPIS
PPSS
PUCS

Parallel
Parallel
Parallel
Parallel
Parallel

REMS
RWLS

Remote State
Remote With Lockout State

SACS
SDYS
SGNS'
SIAS
SIDS
SIIS
SINS
SIWS
SNAS
SPAS
SPIS
SPMS
SRAS
SRIS
SRNS
SROS
STRS
SWNS

System Control Active State
Source Delay State
Source Generate State
System Cantrall nterface Clear Active State
Source Idle State
System Control Interface Clear Idle State
System Control Interface Clear Not Active State
Source Idle Wait State
System Control Not Active State
Serial Poll Active State
Serial Poll Idle State
Serial Poll Mode State
System Control Remote Enable Active State
System Control Remote Enable Idle State
System Control Remote Enable Not Active State
Service Request State
Source Transfer State
Source Wait for New Cycle State

TACS
TAOS
TIDS
TPIS

Talker
Talker
Talker
Talker

AWNS
CACS
CADS
CAWS
CIDS
CPPS
CPWS
CSBS
CSNS
CSRS
CSWS

L~T~~ _
DCAS
DCIS
DTAS
OTIS

_A.<:.c:.p.:.o~ ~~t~o~ ~":. ~y':l:' ~~e__ -,
Controller Active State
I
Controller Addressed State
I
Controller Active Wait State
I
Controller Idle State
I
Controller Parallel Poll State
I.
Controller Parallel Poll Wait State
:
Controller Standby State
I
Controller Service Not Requested State I
Controller Service Requested State
I
Controller Synchronous Wait State
I
£~t':'OI~r:_,T!:.a.!2.s~r ~t~t':.. ______
Device Clear Active State
Device Clear Idle State
Device Trigger Active State
Device Trigger Idle State'

*

J

LACS
LADS
LI OS
LOCS
LPAS
LPIS
LWLS

Listener Active State
Listener Addressed State
Listener Idle State
Local State
Listener Primary Addressed State
Listener Primary Idle State
Local With Lockout State

NPRS

Negative Poll Response State

Poll
Poll
Poll
Poll
Poll

Addressed to Configure State
Active State
Idle State
Standby State
Unaddressed to Configure State

Active State
Addressed State
Idle State
Primary Idie State

"The Controlier function IS Implemented on the Intel® 8292.

10-5

205248-002

8291A

Table 3. IEEE 488 Interface Message Reference List
Mnemonic

Message

,Interface Functlon!s)

LOCAL MESSAGES RECEIVED (By Interface Functionsl
'gts
ist
Ion
Ipe
nba

go to standby
individual status
listen only
local poll enable
new byte available

C
PP
L, LE
PP
SH

pon
rdy
'rpp
'rsc
rsv

power on
ready
request parallel poll
request system control
request service

rtl
tsic
'sre
'tca
'tcs
ton

return to local
send interface clear
send remote enable
take control asynchronously
take control synchronously
talk only

,'SH,AH,T,TE,L,LE,SR;RL,p,P,C
AH
,.',,'

C
C
SR
RL
C

C
C
AH, C
T, TE

REMOTE MESSAGES RECEIVED
ATN
DAB
DAC
DAV
DCL

Attention
Data Byte
Data Accepted
Data Vaiid
Device Clear

SH,AH,T,TE,L,LE,PP,C '
,iVia L, LEI
'
SH
AH
DC

END
GET
GTL
IFC

End
Group Execute Trigger
Go to Local,
Identify
Interface Clear

(via L, LEI
DT
RL
L,LE,PP
T,TE,L,LE,C

LLO
MLA
MSA
MTA
OSA

Local Lockout
My Listen Address
My'Secondary Address
My Talk Address
Other Secondary Address

RL
L,LE,RL,T,TE
TE,LE,RL
T,TE,L,l.E
TE

OTA
PCG
2PPC
2[PPDl
2[PPEl

Other Talk Address
Primary Command Group
Parallel Poll Configure
Parallel Poll Disable
Parallel Poll Enable

T,TE
TE,LE,PP
PP
PP
PP

'PPR N
2PPU'
, REN
RFD
ROS

Parallel.Poll Response N
Parallel Poli Unconfigure
Remote Enable
Ready for Data
Request Service

(via CI
PP
RL
SH
(via L, LEI

[SDCl
,SPD
SPE
'SOR
STB

Select Device Clear
Serial Poll Disable
,Serial Poll Enable
Service'Request
Status Byte

DC
T, TE
T, TE
(via CI
(via L, LEI

'TCT or [TCTl
UNL

Take Control
Unlisten

C
L, LE

IDY

NOTE:
r, These messages are handled only by Intel's 8292.
2. Undefined commands which may be passed'to the microprocessor.

10-6

205248-002

intel

8291A

Table 3. (Cont'd)
IEEE 488 Interface Message Reference List
Message

Mnemonic

'Interface Functlon(s)

REMOTE MESSAGES SENT
ATN
DAB
DAC
DAV
DCL

Attention
Data Byte
Data Accepted
Data Valid
Device Clear

C
(via T, TEl
AH
SH
(via CI

END
GET
GTL
lOY
IFC

End
Group Execute Trigger
Go to Local
Identify
Interface Clear

(via TI
(via CI
(via CI
C
C

LLO
MLA or [MLA[
MSA or [MSA[
MTAor [MTA[
OSA

Local Lockout
My Listen Address
My Secondary Address
My Talk Address
Other Secondary Address

(via
(via
(via
(via
(via

CI
CI
CI
CI
CI

OTA
PCG
PPC
[PPD[
[PPE[

Other Talk Address
Primary Command Group
Parallel Poll Configure
Parallel Poll Disable
Parallel Poll Enable

(via
(via
(via
(via
(via

CI
CI
CI
CI
CI

PPRN
PPU
REN
RFD
RQS

Parallel Poll Response N
Parallel Poll Unconfigure
Remote Enable
Ready for Data
Request Service

PP
(via CI
C
AH
T, TE

[SDC[
SPD
SPE
SRQ
STB

Selected Device Clear
Serial Poll Disable
Serial Poll Enable
Service' Request
Status Byte

(via
(via
(via
SR
(via

TCT
UNL

Take Control
Unlisten

(via CI
(via CI

CI
C)
C)
T, TEl

NOTE:

3. All Controlier messages must be sent via Intel's 8292.

8291A Registers

Data Registers

I017 10161 015 1014 1013 1012 1011 I 010 I

A bit-by-bit map of the 16 registers on the 8291 A is
presented in Figure 5. A more detailed explanation
of each of these registers and their functions follows. The access of these registers by the
microprocessor is accomplished by using the es,
RO, WR, and RS o-RS 2 pins.

DATA-IN REGISTER (OR)
100710061005100410031002100110001
OATA-OUT REGISTER (OW)

Register
All Read Registers
All Write Registers
High Impedance

CS

RD

0
0

0
d

WR

0
d

RSo-RS2

The Oata-In Register is used to move data from the
GPIB to the microprocessor or to memory when the
8291A is addressed to listen. Incoming information
is separately latched by this register, and its contents are not destroyed by a write to the data-out

eee
eee
ddd
10-7

205248-002

intel'

8291A

register. The RFD (Ready for Data) message \s held
false until the byte is removed from the d.ata in regi~­
ter, either by the microprocessor or by DMA. The
8291 A then completes the handshake automatically.
In RFD holdoff mode (see Auxiliary Register A), the
handshake i5 not finished until a command is sent
telling the 8291A to release the holdoff.ln this way,
the same byte may be read several times, or an over
anxious talker may be held off until all available data
has been processed.

Interrupt Registers

When the 8291A is addressed to talk, it uses the
data-out register to move data onto the GPIB. After
the BO interrupt is received and a byte is written to
this register, the 8291A initiates and completes the
handshake while sending the byte out over the bus.
In the BO interrupt disable mode, the user should
wait until BO is active before writing to the register.
(In theDMA mode, this will happen automatically.) A
read of the Data-In Register does not destroy the
information in the Data-Out Register.

I CPTIAPT I GET END

I

ICPTIAPTIGETIEND DEC

I ERR I BO I BI

INTERRUPT STATU,S 1 (1R)
[INTISPASILLOIREMI SPC I LLOclREMCIADScl
INTERRUPT STATUS 2 (2R)

I

I DEC

I ERR I 'BO I BI I

INTERRUPT ENABLE 1 (1W)

10

I

o I DMAO IDMAllsp'cILLOcIREMCIADSC I
I!IITERRUPT ENABLE 2 (2W)

I INTI DTOIDLO IAD5-oIAD4-oIAD3- oIAD2-oIAD1-0 I
ADDRESS

°

REGISTER.

,Figure 5. 8291A Registers
READ REGISTERS

REGISTER SELECT ,"
CODE
RS2

I I
017

016

015

I

014

013

I

Dl2

011

I 010

I

0

RS1

WRITE REGISTERS

RSO

I. DO? I DOG I 005 I 004 I DOli 002 I DO' I 000

O.

DATA IN

[CPT 1 APT

1

DATA OUT

GET 1 END 1 DEC 1 ERR 1 BO

.1

BI

1

0

1,CPT I APT I ryND I DEC I ERR I BO I BI

INTERRUPT STATUS 1

liNT

I

SPAS

I

,LLC

I

REM

I

ILLOC

SPC

INTERRUPT ENABLE 1

I

REMCj

.,

ADScl

o

I

,0

I o·

DMAOj OMAII

INTERRUPT STATUS 2

1 S8

I SROsl

ton

Ion

S6 I SS I s. I S3 I 52 IiiJ 0
EOI

I

LPAS

I

TPAS

I

LA

I TA I MJMNI

0' I.TO I lO

1

ADSC

I

I0

I o· I 01 0 1ADM,I, ADMOI
ADDRESS MODE'

, I CNT21 cNnl

COMMAND PASS THROUGH

CNTOI COM41 COM31 COM21 COM,I COMol
AUX MODE

o 1ARS I DT I .Dl I ADS I AO' I AD3 I AD2 I AD' ,I

liNT I DTO .1 DlO I ADS,ol AD"ol AD3,01 A02-01AD,.ol
ADDRESS 0'

I on

I REMCI

SERIAL POLL MODE

I CPT11 CPT61 CPTsl CPT. I CPT31 cpn I cpnl CPTO I '

X

LLOC

, 1S8 I '" I S6 1SS I S4 I S3. I S2 ; I s,

ADDRESS STATUS

,I

I

INTERRUPT ENABLE 2

SERIAL POLL STATUS·

I

SP~

ADDRESS 011

Dl' 1ADS·,I AD.·,I AD3·,1 AD2·,1 AD"+- ., .

, 1 EC7 I EC6

A'DDRESS1

ECS 1EC4 1 EC31 eC2 I Eel I'ECO
EOS

10-8

205248-002

8291A

The 8291A can be configured to generate an interrupt to the microprocessor upon the occurrence of
any of 12 conditions or events on the GPIB. Upon
receipt of an interrupt, the microprocessor must
read the Interrupt Status Registers to determine
which event has occurred, and then execute the
appropriate service routine (if. necessary). Each of
the 12 interrupt status bits has a matching enable bit
in the interrupt enable registers. These enable bits
are used to select the events that will cause the INT
pin to be asserted. Writing a logic "1" into any of
these bits enables the corresponding interrupt
status bits to generate an interrupt. Bits in the Interrupt Status Registers are set regardless of the states
of the enable bits. The Interrupt Status Registers are
then cleared upon being read or when a local pon
(power-on) message is executed. If an event occurs
while one of the Interrupt Status Registers is being
read, the event is held until after its register is
cleared and then placed in the register.

The mnemonics for each of the bits in these registers and a brief description of their respective functions appears in Table 4. This tables also indicates
how each of the interrupt bits is set.
NOTE: The INT bit in the Address 0 Register Is a duplicate of the
INT bit in the Interrupt Status 2 Register. It is only a status
bit. It does not generate interrupts and thus does not have
a corresponding enable bit.
.
The BO and BI interrupts enable the user to perform
data transfer cycles. BO indicates that a data byte
shouid be written to the Data Out Register. It is set by
TACS . (SWNS + SGNS) . RFD .. lt is reset when the
data byte is written, ATN is asserted, or the 8291A
exits TACS. Data should never be written to the Data
Out Register before BO is set. Similarly, BI is set
when an input byte is accepted into the 8291A and
reset when the microprocessor reads the Data In
Register. BO and BI are also reset by pon (power-on
local message) and by a read of the Interrupt

Table 4. Interrupt Bits

Indicates Undefined Commands

CPT

An undefined command has been received.

Set by (TPAS + LPAS).SCG.ACDS.MODE 3

APT

Set by DTAS
Set by (EOS + EOI).LACS

GET
END

A secondary address must be passed throu9h
to the microprocessor for recognition.
A group execute trigger has occurred.
An EOS or EOI message has been received.

Set by DCAS
Set by TACS.nba.DAC.RFD

DEC
ERR

Device Clear Active State has occurred.
Interface error has occurred; no listeners
are active.

TACS.(SWNS + SGNS)
Set by LACS.ACDS

80

A byte should be output.
A byte has been input.

Shows status of the INT pin

81

INT

The device has been enabled for a serial poll
The 'device is in local lock out state.
(LWLS+RWLSI

SPAS
LLO

The device is in a remote state.
(REMS+RWLSI

REM

SPAS ---SPAS if APRS:STRS~SPAS was true
LLCNO LLO

SPC
LLOC

These are status only. They will not generate
interrupts, nor do they have corresponding
mask bits.

Serial Poll Complete interrupt.
Local lock out change interrupt.

RemotQ.ocal

REMC

Remote/Local change interrupt.

AddresseUnaddressed

ADSC

Address status change interrupt.'

NOTE: 'In ton (talk-only) and Ion (listen-only) modes, no ADSC interrupt is generated.

""
10-9

205248-002

8291A

Status 1 Register. However, if if is so desired, data
transfer cycles may be performed without reading
the Interrupt Status 1 Register if all interrupts except
for BO or BI are disabled; BO and BI will automatically reset after each byte is transferred.

If the 8291A is used in the interrupt mode, the
INT and DREO pins can be dedicated to data input
and oiJtput interrupts respectively by enabling BI
and DMAO, provided'that no other interrupts are
enabled. This eliminates the need to read the interrupt status registers if a byte is'received or
transmitted.

The ERR bit is set to indicate the b,us error condition
when the 8291A is an active talker and tries to send a
byte tqthe GPIB,but there are no active listeners
(e.g., all devices on the GPIB are in AIDS). The logical equivalent of (nba . TACS . DAC . RFD) will set
this bit.

The DEC bit is set whenever DCAS has occurred.
The user milst define a known state to which all
device functions will return in DCAS. Typically this
state will be a power-on state. However, the state of
the device functions at DCAS is at the designer's
discretion. It should be noted that DCAS has no
effect on the interface functions which are returned
to a known state by the IFC (interface clear) message
or the pon local message.

The END interrupt bit may be used by the microprocessor to detect that a multi-byte transfer has been
completed. The bit will be set when the 8291A is an
active listener (LACS) and either EOS (provided the
End on EOS Received feature is enabled in theAuxil'iary Register A),or EOI is received. EOS will generate
,an interrupt when the byte in the Data In Register
matches the byte in the EOS register. Otherwise the
interrupt will be generated when a true input is
detected on EOL

The GET interrupt bit is used by the microprocessor
to detect that DTAS has occurred. It is set by the
8291A when the GET message is received while it is
addressed to listen. The TRIG output pin of the
8291 A fires when the GET message is received.
Thus, the basic operation of device trigger may be
started without microprocessor software intervention.

The APT interrUpt bit indicates to the processor that
a secondary address is available in the CPT register
for validation; This interrupt will only occur if
Mode 3 addressing is in effect. (Refer to the section
on addressing.) In Mode 2, secondary addresses will
be recognized automatically on the 8291 A. They will
be ignored in Mode 1.

The CPT interrupt bit flags the occurrence of an
undefined command and of all secondary commands following an undefined command. The Command Pass Through feature is enabled by the BO bit
of Auxiliary RegisterS.Any message not decoded'by
the 8291A (not included in the state diagrams in
Appendix B) becomes an undefined command. Note
that any addressed command is automatically ignored when the 8291A is not addressed.

Undefined commands are read by the CPU from the
Command Pass Through register of the 8291A. This
register reflects the logic levels present on the data
lines at the time it is read. If the CPT feature is
enabled, the 8291A will hold off the handshake until
this register is read.

An especially useful feature of the 8291Ais its ability
to generate interrupts from state transitions in the
interface functions. In particular, the lower 3 bits of
the Interrupt Status 2 Register, if enabled by the
corresponding enable bits, will cause an interrupt
upon changes in the fOllowing states as defined in
the IEEE 488 Standard.

Bit 0 ADSC
Bit 1 REMC
Bit 2 LLOC

change in LIDS or TIDS or MJMN
change in LOCS or REMS
change in LWLS or RWLS

The upper4 bits of the Interrupt Status 2 Register
are available to the processor as status bits. Thus, if
one of the bits 0-2 generates an interrupt indicating
a state change has taken place, the corresponding
status bit (bits 3-5 may be read to determine what
the new state is. To determine the nature of a change
in addressed status (bit 0) the Address Status Register is available to be read. The SPC interrupt (bit 3 in
Interrupt Status 2) is set upon exit from SPAS if
APRS:STRS:SPAS occurred which indicates that the
GPIB controller has read the bus serial poll status
byte after the 8291 A requested service (asserted
SRO). The SPC interrupt occurs once after the controller reads the status byte if service was requested.,
10-10

205248-002

intel

8291A

The controller may read the status byte later, and the
byte will contain the last status the 8291A's CPU
wrote to the Serial Poll Mode Register, but the SRQS
bit will not be set and no interrupt will be generated.
Finally, bit 7 monitors the state of the 8291 A INT pin.
Logically, it is an OR of all enabled interrupt status
bits. One should note that bits 3-6 of the Interrupt
Status 2 Register do not generate interrupts, but are
available only to be read as status bits by the processor. Bit 7 in Interrupt Status 2 is duplicated in Address Register, and the latter should be used when
polling for interrupts to avoid losing one of the interrupts in Interrupt Status 2 Register.

°

Bits 4 and 5 (DMAI, DMAO) of the Interrupt Mask 2
Register are available to enable di rect data transfers
between memory and the GPIB; DMAI (DMA in)
enables the DREQ (DMA request) pin of the 8291A to
be asserted upon the occurrence of BI. Similarly,
DMAO (DMA out) enables the DREQ pin to be asserted upon the occurrence of BO. One might note
that the DREQ pin may be used as a second interrupt
output pin, monitoring BI and/or BO and enabled by
DMAI and DMAO. One should note that the DREQ
pin is not affected by a read of the Interrupt Status 1
Register. It is reset whenever a byte is written to the
Data Out Register or read from the Data In Register.
To ensure that an interrupt status bit will not be
cleared without being read, and will not remain uncleared after being read, the 8291A implements a
special interrupt handling procedure. When an
enabled interrupt bit is set in either of the Interrupt
Status Registers, the input of the registers are
blocked until the set bit is read and reset by the
microprocessor. Thus, potential problems arise
when interrupt status changes while the register is
being blocked. However, the 8291A stores all new
interrupts in a temporary register and transfers them
to the appropriate Interrupt Status Register after the
interrupt has been reset. This transfer takes place
only if the corresponding bits were read as zeroes.

The Serial Poll Mode Register determines the status
byte that the 8291A sends out on the GPIB data lines
when it receives the SPE (Serial Poll Enable)
message. Bit 6 of this register is reserved for the rsv
(request service) local message. Setting this bit to 1
causes the 8291A to assert its SRQ line, indicating its
need for attention from the controller-in-charge of
the GPIB. The other bits of this register are available
for sending status information over the GPIB.
Sometime after the microprocessor initiates a request for service by setting bit 6, the controller of the
GPIB sends the SPE message and then addresses
the 8291A to talk. At this point, one byte of status is
returned by the 8291A via the Serial Poll Mode Register. After the status byte is read by the controller,
rsv is automatically cleared by the 8291A and an SPC
interrupt is generated. The CPU may request service
again by writing another byte to the Serial Poll Mode
Register with the rsv bit set. If the controller performs a serial poll when the rsv bit is clear, the last
status byte written will be read, but the SRQ line will
not be driven by the 8291A and the SRQS bit will be
clear in the status byte.
The Serial Poll Status Register is available for reading the status byte in the Serial Poll Mode Register.
The processor may check the status of a request for
service by polling bit 6 of this register, which corresponds to SRQS (Service Request State). When a
Serial Poll is conducted and the controller-incharge reads the status byte, the SRQS bit is
cleared. The SRQ line and the rsv bit are tied
together.

Address Registers'
I ton lion I EOII LPASITPAS I LA I TA I MJMN I
ADDRESS STATUS (4R)
liNT I DTOI DLOIAD5-0IAD4-0IAD3-0IAD2-0IAD1-0 I
ADDRESS

Serial Poll

R~gisters

x

°

(6R)

I

I DT11 DL11 AD5- 11AD4- 11AD3- 11AD2- 11AD1-1
ADDRESS 1 (7R)

IS8/SRQS/S6/S5/S4/S3/S2/S1/

/ TO / LO / 0

SERIAL POLL STATUS (3R)

I S8 I rsv I S61

S5

/

°

0

/

°/

ADM1/ADMO /

ADDRESS MODE (4W)

I ARS I DT

I S4 I S3 I S2 I S 1 I

SERIAL POLL MODE (3W)

/ DL / AD5 / AD4 / AD3 I AD2

I AD1

/

ADDRESS 0/1 (6W)
10-11

205248-002

intel

8291A

The Address Mode Register is used to select one of
the five modes of addressing available on the 8291 A.
It determines the way in which the 8291A uses the
information in the Address 0 and Address 1
Registers.
-In Mode 1, the contents of the Address 0 Register
constitute the "Major" talker/listener address while
the Address 1 Register represents the "Minor"
talker/listener address. In applications where only
one address is needed, the major talker/listener is
used, and the minor talker/listener should be disabled. Loading an address via the Address 0/1 Register into Address Registers 0 and 1 enables the major
and minor talker/listener functions respectively.

Setting the LO bit generates the local Ion (Iistenonly) message and sets the 8291A to a listen-only
mode. This mode allows the device to operate as a
listener in an interface system withouta controller.
The above bits may also be used by a controller-incharge to set itself up for remote command or data
communication.

-In Mode 2 the 8291A recognizes two sequential
address bytes: a primary followed by a secondary.
Both address bytes must be received in order to
enable the device to talk or listen. In this manner,
Mode 2 addressing implements the extended talker
and listener functions as defined in IEEE-488.
To use Mode 2 addressing the primary address must
be loaded into the Address 0 Register, and the Secondary Address is placed in the Address 1 Register.
With both primary and secondary addresses residing on chip, the.8291A can handle all addressing
sequences without processor intervention.
-In Mode 3, the 8291A handles addressing just as it
does in Mode 1, except that each Major or Minor
primary address must be followed by a secondary
address. All secondary addresses must be verified
by the rTlicroprocessor when Mode 3 is used. When
the 8291 A is in TPAS or LPAS (talker/listener primary
addressed state), and it does not recognize the byte
on the 010 lines, an APT interrupt is generated (see
section on Interrupt Registers) and the byte is available in the CPT (Command Pass-Through) Register.
As part of its interrupt service routine, the microprocessor must read the CPT Register and write one of
the following responses to the Auxiliary Mode
Register:
1. 07Himplies a non-valid secondary address
2. OFH implies a valid secondary address

Setting the TO bit generates the local ton (talkonly) message and sets the 8291A to a talk-only
mode. This mode allows the device to operate as a
talker in an interface system without a controller.
10-12

The mode of addressing implemented by the 8291A
may be selected by writing one olthe following bytes
to the Address Mode Register.
Register Contents
10000000
01000000
11000000
00000001
00000010
00000011

Mode

Enable talk only mode (ton)
Enable listen only mode (Ion)
The 8291 may talk to itself
Mode 1, (Primary-Primary)
Mode 2 (Primary-Secondary)
Mode 3 (Primary/APT-Primary/APT)

The Address Status Register contains information
used by the microprocessor to handle its own
addressing. This information includes status bits
that monitor the address state of each talker/
listener, "ton" and "Ion·' flags which indicate the
talk and listen only states, and an EOI bit which,
when set, signifies that the END message came with
the last data byte. LPAS and TPAS indicate that the
listener or talker primary address has been received.
The microprocessor can use these bits when the
secondary address is passed through to determine
whether the 8291A is addressed to talk or listen. The
LA (listener addressed) bit will be set when the
8291A is in LACS (Listener Active State) or in LADS
(Listener Addressed State). Similarly, the TA (Talker
Addressed bit) will be set to indicate TACS or TAOS,
but also to indicate SPAS (Serial Poll Active State).
The MJMN bit is used to determine whether the
information in the other bits applies to the Major or
Minor talker/listener. It is set to "1" when the Minor
talker/listener is addressed. It should be noted that
only one talker/listener may be active at anyone
time. Thus, the MJMN bit will indicate which, if
either, of the talker/listeners is addressed or active.
The Address 0/1 Register is used for specifying the
device's addresses according to the format selected
in the Address Mode Register. Five bit addresses
may be loaded into the Address 0 and Address 1
Registers by writing into the Address 0/1 Register.
The ARS bit is used to select which of these registers
the other seven bits will be loaded into. The OT and
OL bits may be used to disable the talker or listener
function at the address signified by the other five
205248-002

intel"

8291A

bits. When Mode 1 addressing is used and only one
primary address is desired, both the talker and the
listener should be disabled at the Minor address.

the CPT Register. In either case, the 8291 A will holdoff the handshake until the microprocessor reads
this register and issues the VSCMD auxiliary
command.

As an example of how the Address 0/1 Register
might be used, consider an example where two primary addresses are needed in the device. The Major
primary address will be selectable only as a talker
and the Minor primary address will be selectable
only as a listener. This configuration of the 8291A is
formed by the following sequence of writes by the
microprocessor.

Operation

Data

RS2-RSo

1. Select addressing Mode 1 0

1

0

00000001

100

2. Load major address into 0
Address 0 Register with
listener function disabled,

1

0

001AAAAA

110

3, Load minor address into
Address 1 Register with
talker function disabled,

1

0

110BBBBB

110

CS RD WR

0

The CPT and APT interrupts flag the availablility of
undefined commands and secondary addresses in
the CPT Register. The details of these interrupts are
explained in the section on Interrupt Registers.
An added feature of the 8291A is, its ability to handle
undefined secondary commands following undefined primaries. Thus, the number of available
commands for future IEEE-488 definition is increased; one undefined primary command followed
by a sequence of as many as 32 secondary commands can be processed. The IEEE-488 Standard
does not permit users to define their own commands, but upgrades of the standard are thus provided for.

At this point, the addresses AAAAA and BBBBB are
stored in the Address 0 and Address 1 Registers respectively, and are available to be read by the microprocessor. Thus, it is not necessary to store any
address information elsewhere. Also, with the information stored in the Address 0 and Address 1
Registers, processor intervention is not required to
recognize addressing by the controller. Only in
Mode 3, where secondary addresses are passed
through, must the processor intervene in the
addressing sequence.

The recommended use of the 8291A's undefined
command capabilities is for a controller-configured
Parallel Poll. The PPC message is an undefined pri~
, mary command typically followed by PPE, an undefined secondary command. For details on this procedure, refer to the section on Parallel Poll Protocol.

Auxiliary Mode Register

~NT2ICNT1ICNTOICOM4ICOM3ICOM2ICOM11 COMO I
AUX MODE (SW)

The Address 0 Register contains a copy of bit 7 of the
Interrupt Status 2 Register (INT). This is to be used
when polling for interrupts. Software should poll
register 6 checking foriNT (bit 7)to beset. When INT
is set, the Interrupt Status Register should be read to
determine which interrupt was received.

CNTO-2:CONTROL BITS
COMO-4:COMMAND BITS
The Auxiliary Mode Register contains a three-bit
control field and a five-bit command field. It is used
for several purposes on the 8291A:

Command Pass Through Register
ICPT71cPT61CPTSICPT41 CPT31CPT21CPT11CPTO I
COMMAND PASS THROUGH (SR)
The Command Pass Through Register is used to
transfer undefined 8-bit remote message codes
from the GPIB to the microprocessor. When the CPT
feature is enabled (bit BO in Auxiliary Register B),
any message not decoded by the 8291 A becomes an
undefined command. When Mode 3 addressing is
used secondary addresses are also passed through

1. To load "hidden" auxiliary registers on the
8291A.
2. To issue commands from the microprocessor to
the 8291A.
3. To preset an internal counter used to generate
T1, delay in the Source Handshake function, as
defined in IEEE-488.
Table S summarizes how these tasks are performed
with the Auxiliary Mode Register, Note that the three
control bits determine how the five command bits
are interpreted.

10-13

205248-002

8291A

Table 5
CODE
CONTROL COMMAND
BITS
BITS

000

OCCCC

001

ODDDD

100
101
011

COMMAND

0100-Trigger: A "Group Execute Trigger" is forced
by this command. It has the same effect·asa GET
command issued by the controller-in-charge of the
GPIB, but does not cause a GET interrupt.

Execute auxiliary command

0101, 1101-Clear/Set rtl:These commands correspond to the local rtf message as defined by the
IEEE-488. The 8291A will go into local mode when a
Set rtl Auxiliary Command is received if local
lockout is not in effect. The 8291A will exit local
mode after receiving a Clear rtl Auxiliary Command
if the 8291A is addressed to listen.

ecce

Preset internal counter to
match external clock
frequency of DODD MHz
(DODD binary representation
of 1 to 8 MHzl
DDDDD Write DDDDD into auxiliary
register A
DDDDD Write DDDDD into auxiliary
register B
USP3P2P, Enable/disable parallel poll
either in response to remote
messages (PPC followed by
PPE or PPD) or as a local
Ipe message. (Enable if U = 0,
disable if U = 1.)

AUXILIARY COMMANDS

Auxiliary commands are executed by the 8291A
whenever OOOOCCCC is written into fhe Auxiliary
Mode Register, where CCCC is the 4-bit command
code.
OOOO-immediate Execute pon: This command
resets the 8291A to a power up state (local pon
message as defined in IEEE-488).
The following conditions constitute the power up
state:
1. All talkers and listeners are disabled.
2. No interrupt status bits are set.
The 8291A is designed to power up in certain states
as specified in the IEEE-488 state diagrams. Thus,
the following states are in effect in the power up
state: SIDS, AIDS, TIDS, LIDS, NPRS, LOCS, and
PPIS.
The "0000" pon is an immediate execute command
(a pon pulse). It is also used to release the "initialize"
state generated by either an external reset pulse or
the "0010" Chip Reset command.
0010-Chip Reset (Initialize): This command has the
same effect as a pulse applied to the Reset pin.
(Refer to the section on Reset Procedure.)

0110-Send EOI: The EOlline of the 8291A may be
asserted with this command. The command causes
EOI to go true with the next byte transmitted. The
EOI line is then cleared upon completion of the
handshake for that byte.
0111, 1111-Non ValidNalid Secondary Address or
Command (VSCMD): This command informs the
8291A that the secondary address received by the
microprocessor was valid or invalid (0111 = invalid,
1111 = valid). If Mode 3 addressing is used, the
processor must field each extended address and
respond to it, or the GPIB will hang up. Note that the
COM3 bit is the invalid/valid flag.
The valid (1111) command .is also used to tell the
8291A to continue from the command-passthrough-state, or from RFD holdoff on GET, SDC
or DCl.
1000-pon: This command puts the 8291A into the
pon (power on) state and holds it there. It is similar to
a Chip Reset except none of the Auxiliary Mode
Registers are cleared. In this state, the 8291A does
not participate in any bus activity. An Immediate
Execute pon releases the 8291A from the pon state
and permits the device to participate in the bus
activity again.
0001, 1001-Parallel Poll Flag (local "ist" message):
This command sets (1001) or clears (0001) the parallel poll flag. A "1" is sent over the assigned data line
(PRR = Parallel Poll Response true) only if the parallel poll flag matches the sense bit from the Ipe local
message (or indirectly from the PPE message). For a
more complete description of the Parallel Poll
features and procedures refer to the section on Parallel Poll Protocol.
INTERNAL COUNTER

The internal counter determines the delay time allowed for the setting of data on the DIO lines. This
delay time is defined as T, in IEEE-488 and appears
in the Source Handshake state diagram between the

0011-Finish Handshake: This command finishes a
handshake that was stopped because of a holdoff
on RFD. (Refer to Auxiliary Register A.)

10-14

205248-002

intel

8291A

SDYS and STRS. As such, DAV is asserted T, after
the DIO lines 'are driven. Consequently, T, is a major
factor in determining the data transfer rate of the
8291A over the GPIB (T, = TWRDV2-TWRD15).

Auxiliary Register, it is loaded with the data
A.A3A2A,Ao. Setting the respective bits to "1"
enables the following features.

When open-collector transceivers are used for connection to the GPIB, T, is defined by IEEE-488 to be
2lLsec. By writing 0010DDDD into the Auxiliary Mode
Register, the counter is preset to match a fc MHz
clock input, where DDDD is the binary representation of NF [1.;;N F.;;8, NF=(DDDD).]. When NF = fc, ,a
2ILsec T, delay will be generated before each DAV
asserted.

Ao- RFD Holdoff on all Data: If the 8291A is listening, F.lFD will not be sent true until the "finish handshake" auxiliary command is issued by the
microprocessor. The holdoff will be in effect for each
data byte.

A,-RFD Holdoff on End: This feature enables the
holdoff on EOI or EOS (if enabled). However, no
holdoff will be in effect on any other data bytes.

T1(ILSeCI = 2fNF + tSYNC , 1.;;NF.;;8
c
.

A 2-End on EOS Received: Whenever the byte in the
Data In Register matches the byte in the EOS Register, the END interrupt bit will be set in the Interrupt
Status 1 Register.

tSYNC is a synchronization error, greater than zero
and smaller than the larger of T clock high and T
clock low. (For a 50% duty cycle clock, tSYNC is less
'
than half the cloc~ cycle).

A3-Output EOI on EOS $ent: Any occurrence of
data in the Data Out Register matching the EOS
Register causes the EOI line to be sent true along
with the data.

If it is necessary that T, be different from 2lLsec, NF
may be set to a value other than fc. In this manner,
data transfer rates may be programmed for a given
system. In small systems, for example, where transfer rates exceeding GPIB specifications are required, one may set NF
2.0

0.8

0.45

<

:c,

2.0

TEST POINTS

DEVICE
UNDER
TEST

0.8

i}CL"'50 PF

A C. TESTING' INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1 AND 0 45V FOR
A LOGIC O· TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A LOGIC 1
AND 0 BV FOR A LOGIC a

GPIB TIMINGS'
Symbol

Parameter

Max.

Units

Test Conditions

TEOT13'

EOI,/, toTRli

135

nsec

PPSS, ATN=0.45V

TEOD16

EOI,/, to DIOValid

155

nsec

PPSS, ATN=0.45V

TEOT12

EOlitoTRll

155

nsec

PPSS, ATN=0.45V

TATND4

ATNL to NDAC!

155

nsec

TACS, AIDS

TATT14

ATNLtoTR1L

155

nsec

TACS, AIDS

TATT24

ATNL toTR2L

155

nsec

TACS, AIDS

TDVND3-C

DAVL to NDAct

650

nsec

AH,CACS

TNDDVl

NDAct to DAVi

350

nsec

SH,STRS

TNRDRl

NRFDi to DREQi

400

nsec

SH

TDVDR3

DAV L to DREQi

600

nsec

AH, LACS, ATN=2.4V

TDVND2-C

DAVi to NDACL

350

nsec

AH, LACS

TDVNR1-C

DAVi to NRFDi

350

nsec

AH, LACS, rdy=True

TRDNR3

RD,/, to NRFDi

500

nsec

AH, LACS

TWRD15

WRi to 010 Valid

280

nsec

SH, TACS, RS=O.4V

TWRE05

WRi to EOI Valid

350

nsec

SH, TACS

TWRDV2

WRito DAVj,

830 + t SYNC

nsec

High Speed Transfers Enabled,
NF = fc, t SYNC = 1/2'fc

NOTES:
1. All GPIB timings are at the pins of the 8291 A.

2. The last number in the symbol for any GPIB timing parameter is chosen according to the transition directions of the reference
signals. The following table describes the numbering scheme.
ito t
ito t
t to i
ho t
Ito VALID
t to VALID

1

2
3
4
5
6

10-24

205248-002

8291A

APPENDIXA
MODIFIED STATE DIAGRAMS
Figure A-1 presents the interface function state
diagrams. It is derived from IEEE Std. state diagrams, with the following changes:

A. The 8291 A supports the complete set of IEEE-488
interface functions except for the controller. These
include: SH1, AH1, T5, TE5, L3, LE3, SR1, RL 1, PP1,
DC1, DT1, and CO.

B. Addressing modes included in T,L state
diagrams.

Level

Logic

0
1
0
1
0'
1

T
F
T
F
T
F

Convention
IEEE-488
Intel
DAV
DAV
NDAC
NDAC
NRFD
NRFD

DAV
DAV
NDAC
NDAC
NRFD
NRFD

Consider the condition when the Not-Ready-ForData signal (pin 37) is active. Intel indicates this
active low signal with the symbol NRFD (VOUT:5VOL for
AH; V'N:5V'L for SH). The IEEE-488-1978 Standard, in
its state diagrams, indicates the active state of this
signal (True condition) with NRFD.
D. All remote multiline messages decoded are conditioned by ACDS. The multiplication by ACDS is not
drawn to simplify the diagrams.

Note that in Mode 3, MSA, OSA are generated only
after secondary address validity chec,k by the microprocessor (APT interrupt).

E. The symbol

indicates:
C. In these modified state diagrams, the IEEE-4881978 convention of negative (low true) logic is
followed. This should not he confused with the Intel
pin- and signal-naming convention based on positive logic. Thus, while the state diagrams below carry low true logic, the signals described elsewhere in
this data sheet are consistent with Intel notation and
are based on positive logic.

1. When event X occurs, the function returns to
state S.
2. X overrides any other transition condition in
the function.
Statement 2 simplifies the diagram, avoiding the
explicit use of X to condition all transitions from S to
other states.

r----l
I
ISH

I
I

IL _ _ _ _ ..JI

pon

NDAC

ATN + fi
(WITHIN t21

DAV

F1 = lACS + SPAS

Figure A·1. 8291A State Diagrams (Continued next page)
10-25

205248-002

8291A

r - - - --,

NRFD

:
I

AH

:
I

L ____ J

-THIS TRANSITION WILL NEVER
OCCUR UNDER NORMAL OPERATION.

oon---",

tTOELAV IS ABOUT 300 NS
FOR DEBOUNCING DAV.

F2'" ATN + LACS + LADS
F3 '" ATN +rdy
T3':T3·CPT·,Aji'f
END IF (EOI

+

EOS) RECEIVED

r-----,
I
I
I
TE
I
IL. _ _ _ _ JI

pon---+\

STB AND ROS AVAILABLE
TOSH

IFC

(WITHIN t41

F4 '" OTA + (OSA' TPAS + MSA ~ LPAS)'
MODE 1 + MLA. M9DE 1
EOIIF DAB = EOS

r-----I

iiQs IN

STB

I
I
I

I
SRO

I
I

L.. _ _ _ _ J

oon---",

ROS IN STB
IFC

(WITHIN t41

Figure A-1. 8291AState Diagrams (Continued next page)
10-26

205248-002

8291A

r----..,
I

I

LE

I

r----'

I

pon---+I

I
I

RL

IL

____

I
I

r

J

pon---.-f

pon---+I

F5'" (MLA· MODE 1 + LPAS· MSA· MODE' I

r-----,
I

I
I

I

PP2

L ___

I
I

'_J

pon---+I

*IDV" ATN . EOI

r----'

I

I

r----'

I

DC

I
I

I

I

DT
I
IL ____ J I

IL ____ JI

F6'" Del + SOC· LADS

Figure A·1. 8291A State Diagrams

10·27

205248-002

8291 A

APPENDIX B
Table B-1. IEEE 488 Time Values
Time Value
Identifier'

Funclion (Apl'lIes 10)

Tl

SH

t2

LC,iC,SH,AH,T,L

T3

AH

t4

T,TE,L,LE,C,CE

ts

PP

Description

Value

Settling Time for Multiline Messages

2:

Response to A TN

:5 200ns

Interface Message Accept Time 3

> O'

2p.s'

Response to IFC or REN False

< 100p.s

Response to ATN+EOI

:5 200ns

,Ts

C

Parallel Poll Execution Time

2:

2p.s

T7

C

Controller Delay to Allow Current Talker
to see A TN Message

2:

500 ns

Ts

C

Length of IFC or REN False

Tg

C

Delay for EOI'

> 100p.s
2: 1.5p.s·

NOTES:
'Time values specified by a lower case t indicate the maximum time allowed to make a state transition. Time values specified by an
upper case T indicate the minimum time that a function must remain in a state before exiting.
'If three-state drivers are used on the 010, DAY, and EOllines, T, may be:
1. '''' 1100 ns.
2. Or'" 700 ns If It is known that within the controller ATN is driven by a three-state driver.
3. Or", SOOns for all subsequent bytes following the first sent after each false transition of ATN (the firSt byte must be sent in accord'
ance with (1) or (2).
4. Or", 350n5 for all subsequent bytes following the first sent after each false transition of ATN under conditions specified in Section
5.2.3 and warning note. See ,IEEE Standard 488.
'Time required for interface functions to accept; not necessarily respond to Interface messages.
'Implementation dependent.
'Delay required 'for'EOI, NOAC, and NRFO signal lines to indicate valid states.
0", 600 ns for three-state drivers.

10-28

205248-002

intel'

8291A

APPENDIXC
THE THREE-WIRE HANDSHAKE

n

TWRDI5

I

I

YALID

!4T1.

NOTYALID

I
~9c
YALID

~TWRDY2

!+-TNDDY1--+I-TDYNR1--OO

,

+I-TRDNR3_

Ft M

_TDYND3_

,f-

..f

DREQ(SH)

~TDYDR3
DREQ(AH)

It-

..
Figure C-1. 3-Wlre Handshake Timing at 8291A

10-29

205248-002

8292
GPIB CONTROLLER
• Complete Implementation of Transfer
Control Protocol

• Complete IEEE Standard 488 Controller
Function
• Interface Clear (IFC) Sending Capability
Allows Seizure of Bus Control and/or .
Initialization of the Bus
• Responds to Service Requests (SRQ)
• Sends Remote Enable (REN), Allowing
Instruments to Switch to Remote
Control

• Synchronous Control Seizure Prevents
the Destruction of Any Data
Transmission in Progress
• Connects with the 8291 to Form a
Complete IEEE Standard 488 Interface
Talker/Listener/Controller

, The 8292 GPIB Controller Is a microprocessor-controlled chip designed to function with the 8291 GPIB Talker/Listener
to implement the full IEEE Standard 488 controller function, Including transfer control protocol. The 8292 Is a preprogrammed Intell!> 8041A.

IF.CL

Xl

8292

GPIB
CONTROLLER

X2

REN

RESET

OAV

VCC

IBFI

Cs

OBFI

GND
IU)

Tiiii

Vcc
COUNT

EOI'
SPI

AD

TCI

WR

CIC

SYNC

NC

DO

ATNO

01

NC

02

CLTH

03

VCC

04

NC.

05

SYC

De

IFC

D7

IITNI

VSS

SRO

GENERAL PURPOSE INTERFACE BUS

Figure 2_ Pin C0rlflguration _

Figure 1. 8291, 8292 Block Diagram

Intel

Corpor8tio~ Assumes No Responsibility for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Pate~i-Llc~nses are implied.

©INTEL CORPORATION 1984

10-30

SEPTEMBER 1984
ORDER NUMBER 231322-001

8292
Table 1. Pin Description
Symbol
IFCL

Pin
No.

Type

Name and Function

1

I

IFC Received (Latched): The 8292
monitors the IFC Line (when not
system controller) through this pin.

X"X2

2,3

I

Crystal Inputs: Inputs for a crystal,
LC or an external timing signal to
determine the internal oscillator
frequency.

RESET

4

I

Reset: Used to initialize the chip to
a known state during power on.

CS

6

I

Chip Select Input: Used to select
the 8292 from other devices on the
common data bus.

RD

8

I

Read Enable: Allows the master
CPU to read from the 8292.

Ao

9

I

Address Line: Used to select between the data bus and the status
register during read operations and
to distinguish between data and
commands written into the 8292
during write operations.

WR

10

I

Write Enable: Allows the master
CPU to write to the 8292.

SYNC

11

0

Sync: 8041A instruction cycle synchronization signal; it is an output
clock with a frequency of XTAL -i15.

Do-D-r

12-19

I/O

Data: 8 bidirectional lines used for
communication between the central processor and the 8292's data
bus bullers and status register.

Vss

7,20

SRO

21

ATNI

22

Pin
No.

Type

Name and Function

5,26,40

P.S.

Voltage: +5V supply input :!:10%.

COUNT

39

I

Event Count: When enabled by the
proper command the internal
counter will count external events
through this pin. High to low transition will increment the internal
counter by one. The pin is sampled
once per three internal instruction
cycles (7.5I'sec sample period
when using 5 MHz XTAL). It can be
used for byte counting when connected to NDAC, or for block counting when connected to the EOI.

REN

38

0

Remote Enable: The Remote Enable bus signal selects remote or
local control of the device on the
bus. A GPIB bus management line,
as defined by IEEE Std. 488-1978.

DAV

37

I/O

Data Valid:
poll to force
parallel poll
used during

IBFI

36

0

Input Buffer Not Full: Used to
interrupt the central processor
while the input buffer of the 8292 is
empty. This feature is enabled and
disabled by the interrupt mask
register.

OBFI

35

0

Output Buffer Full: Used as an
interrupt to the central processor
while the output bullerof the 8292 is
full. The feature can be enabled and
disabled by the interrupt mask
register.

E012

34

I/O

End Or Identify: One of the GPIB
management lines, as defined by
IEEE Std. 488-1978. Used with ATN
as Identify Message during parallel
poll.

SPI

33

0

Special Interrupt: Used as an interrupt on events not initiated by the
central processor.

TCI

32

0

Task Complete Interrupt: Interrupt
to the control processor used to indicate that the task requested was
completed by the 8292 and the information requested is ready in the
data bus buffer.

CIC

31

0

Controller In Charge: Controls the
SIR input of the SRO bus transceiver. It can also be used to indicate that the 8292 is in charge olthe
GPIB bus.

Symbol
Vee

P.S. Ground: Circuit ground potential.
I

I

Service Request: One of the IEEE
control lines. Sampled by the 8292
when it is controller in charge. If
true, SPI interrupt to the master will
be generated.
Attention In: Used by the 8292 to
monitorthe GPIB ATN control line. It
is used during the transfer control
procedure.

IFC

23

I/O

Interlace Clear: One of the GPIB
management lines, as defined by
IEEE Std. 488-1978, places all devices in a known quiescent state.

SYC

24

I

System Conroller: Monitors the
system controller switch.

CLTH

27

0

Clear Latch: Used to clear the IFCR
latch after being recognized by the
8292. Usually low (except after
hardware R~, it will be pulsed
high when IFCR is recognized by
the 8292.

ATNO

29

0

Attention Out: Controls the ATN
control line of the bus through external logic for tcs and tca procedures. (ATN is a GPIB control line, as
defined by IEEE Std. 488-1978.)

10-31

Used during parallel
the 8291 to accept the
status bits. It is also
the tcs procedure.

231322-001

inter

8292
Interrupt Status Register

FUNCTIONAL DESCRIPTION
The 8292 is an Intel 8041A which has been programmed
as a GPIB Controller interface element. It is used with
the 8291 GPIB Talker/Listener and two 8293 GPIB Transceivers to form a complete IEEE-488 Bus Interface for a
microprocessor. The electrical interface is performed by
the transceivers, data transfer is done by the talker!
listener, and control of the bus is done by the 8292.
Figure 3 is a typical controller interface using Intel's
GPIB peripherals.

GPIB .

TO
PROCESSOR
BUS

TO
PROCESSOR
BUS

GPIB

Figure 3. Talker/Listener/Controller Configuration

The .internal RAM in the 8041A is used as a special
purpose register bank for the 8292. Most of these
registers (except for the interrupt flag) can be accessed
through commands to the 8292. Table 2 identifies the
registers used by the 8292 and how they are accessed.

I

SYC

I

ERR

I

SRO

I

IFCR

EV

IBF

OBF

00

The 8292 can be configured to interrupt the microprocessor on one of several conditions. Upon receipt of the
interrupt the microprocessor must read the 8292
interrupt status register to determine which event
caused the interrupt, and then the appropriate subrou·
tine can be performed. The interrupt status register is
read with Ao high. With the exception of OBF and IBF,
these interrupts are enabled or disabled by the SPI
interrupt mask. OBF and IBF have their own bits in the
interrupt mask (OBFI and IBFI). I
OBF

Output Buffer Full. A byte is waiting to be read by
the microprocessor. This flag is cleared when the
output data bus buffer is read.
IBF
Input Buffer Full. The byte previously written by
the microprocessor has not been read yet by the
8292. If another byte is written to the 8292 before
this flag clears, data will be lost. IBF is cleared
when the 8292 reads the data byte.
IFCR Interface Clear Received. The GPIB system
controller has set IFC. The 8292 has become idle
and is no longer in charge of the bus. The flag is
cleared when the lACK command is issued.
EV
Event Counter Interrupt. The requested number
of blocks or data bytes has been transferred. The
EV interrupt flag is cleared by the lACK
command:
SRQ Service Request. Notifies the 8292 that a service
request (SRQ) message has been received. It is
cleared by the lACK command.
ERR Error occurred. The type of error can be determined by reading the error status register. This
interrupt flag is cleared by the lACK command.
SYC System Controller Switch Change. Notifies the
processor that the state of the system controller
switch has changed. The actual state Is contained in the GPIB Status Register. This flag is
cleared by the lACK command.

Table 2. 8292 Registers
WRITE TO 8292

READ FROM 8292
INTERRUPT STATUS
SYC

ERR

I SRO

EV

IBF

IIFCR
I

I

INTERRUPT MASK

AO

07

1

OBF I

SPI

TCI

SYC

I

x

X
I

I USER I

X

CSBS

CA

REN

OAV

I

x

x

I

SYCS

I

1TOUT, I

o·

0

X

I I
SYC

IFC

REN

I

I

D

I

SRO

I o·

I

I
I I
I I I I I I I EJ o·
I I I I I I
I o·
1

c

OP

I

c

c

I

C

I

ANTI

SRO

0

0

I o·

0

D

0

0

0

0

0

0

D

0

0

0

0

TIMEOUT

D

I

I

EVENT COUNTER

IFC

I
I I I I I I I
0

I TOUT3 I TOUT2 I TOUT1

I
COMMAND FIELD

EVENT COUNTER STATUS

0

0

I USER

I

GPIBIBUSj STATUS
EOI

I

00

CONTROLLER STATUS

I I

iBFf

ERROR MASK

I TOUT31 T()UT2

I

I

AO
I SRO

07

00
ERROR FLAG

I

I OBFI

I

I

o·

D

0

I

TIME OUT STATUS

0

D

0

D

0

D

D

0

I o·
10-32

Note: These registers are accessed by a special utility command,
see page 6.

231322-001

inter

8292
Event Counter Register

Interrupt Mask Register

I I

SPI

I I
TCI

SYC

OBFI

SAO

iBFI

DO

The Interrupt Mask Register Is used to enable features
and to mask the SPI and TCI Interrupts. The flags In the
Interrupt Status Register will be active even when
masked out. The Interrupt Mask Register Is written
when Ao Is low and reset by the RINM command. When
the register is read, Dl and D7 are undefined. An inter·
tupt is enabled by setting the corresponding register bit.
SRQ

Enable interrupts on SRQ received.

IBFI

Enable Interrupts on Input buffer empty.
Enable Interrupts on a change In the system
controller switch.

TCI

Enable Interrupts on the task completed.

SPI

Enable Interrupts on special events.

NOTE: The event counter Is enabled by the GSEC
command, the error Interrupt Is enabled by the error
mask register, and IFC cannot be masked (it will always
cause an interrupt).
Controller Status Register

I I
CSBS

CA

Ix I

I

SYCS

AEN

IFC

SAO

The Controller Status Register is used to determine the
status of the controller function. This register Is
accessed by the RCST command.
SRQ

Service Request line active (CSRS).

REN

Sending Remote Enable.

IFC

Sending or receiving interface clear.

SYCS System Controller Switch Status (SACS).
CA

06

I

05

I

DO

04

The Event Counter Register contains the Initial value for
the event counter. The counter can count pulses on pin
39 of the 8292 (COUNT). It can be connected to EOI or
NDAC to count blocks or bytes respectively during
standby state. A count of zero equals 256. This register
cannot be read, and is written using the WEVC
command.
Event Counter Status Register

I OJ I ~ I ~ I ~ I ~

OBFI Enable Interrupts on output buffer full.
SYC

I OJ I

Controller Active (CACS + CAWS + CSWS).

CSBS Controller Stand· by State (CSBS, CAl =(0,0) Controller Idle

This register contains the current value in the event
counter. The event counter counts back from the initial
value stored in the Event Counter Register to zero and
then generates an Event Counter Interrupt. This register
cannot be written and can be read using a REVC
command.
Time Out Register

The Time Out Register is used to store the time used for
the time out error function. See the individual timeouts
(TOUT1, 2, 3) to determine the units of this counter. This
Time Out Register cannot be read, and it is written with
the WTOUT command.
Time Out Status Register

This register contains the current value in the time out
counter. The time out counter decrements from the
original value stored in the TimeOut Register. When
zero is reached, the appropriate error interrupt is gen·
erated.,lf the register is read while none of the time out
functions are active, the register will contain the last
value reached the last time a function was active. The
Time Out Status Register cannot be written, and It is
read with the RTOUT command.
Error Flag Register

GPIB Bus S,tatus Register

I I
AEN

OAV

I I
EOI

x

SYC

IFC

ATNI

SRO

I

x

OJ

I

x

I

USEA

I

x

I

X

I

TOUT3

I

TOUT2

I

TOUT1

~

DO

This register contains GPIB bus status Information. It
can be used by the microprocessor to monitor and
manage the bus. The GPIB Bus Register can be read
using the RBST command.
Each of these status bits reflect the current status of
the corresponding pin on the 8292.
SRQ

Service Request

ATNI Attention In
IFC

Interface Clear

SYC

System Controller Switch

EOI

End or Identify

DAV

Data Valid

REN

Remote Enable

Four errors are flagged by the 8292 with a bit In the Error
Flag Register. Each of these errors can be masked by
the Error Mask Register. The Error Flag Register cannot
be written, and it is read by the lACK command when the
error flag in the Interrupt Status Register is set.
TOUT1 Time Out Error 1 occurs when the current con·
, troller has not stopped sending ATN after
receiving the TCT message for the time period
specified by the Time Out Register. Each count
in the Time Out Register is at least 1800 tCY'
After flagging the error"the 8292 will remain in a
loop trying to take control until the current
controller stops sending ATN or a new command is written by the microprocessor. If a new
command is written, the 8292 will return to the
loop after executing it.

231322-001

inter

8292
,

TOUT2 Time Out Error 2 occurs when the transmission
between the addressed talker and listener has
not started for the time period specified by the
Time Out Register. Each count in the Time Out
Register is at least 45 tCY' This feature is only'
enabled when the controller is in the CSBS
state.

F2 -

TOUT3 Time Out Error 3 occurs when the handshake
signals are stuck and the 8292 is not succeed·
ing in taking control synchronously for the time
period specified by the Time Out Register. Each
count in the Time Out Register is at least 1800
tCY' The 8292 will continue checking ATNI until
it becomes true or a new command is received.
After performing the new command, the 8292
will return to the ATNI checking loop.
USER

F3 -

F4 -

I

00

The Error Mask Register is used to mask the interrupt
from a particular type of error. Each type of error interrupt is enabled by setting the corresponding bit in the
Error Mask Register. This register can be read with the
RERM command and written with Ao low.
Command Register

c

c

D7

Commands are performed by the 8292 whenever a byte
Is written with Ao high. There are two categories of
commands distinguished by the OP bit (bit 4). The first
category is the operation command (OP 1). These
commands initiate some action on the interface bus.
The second category is the utility commands (OP = 0).
These commands are used to aid the communication
between the processor and the 8292.

=

OPERATION COMMANDS
Operation commands initiate some action on the GPIB
interface bus. It is using these commands that the
control functions such as polling, taking and paSSing
control, and system controller functions are performed.
FO - SPCNI -

F1 - GIDL -

Reset Interrupts

GSEC -

Go To Standby, Enable Counting

EXPP -

Execute Parallel Poll

This command initiates a parallel poll by asserting EOI
when ATN is already active. TCI will be set at the end of the
command. The 8291 should be previously configured as a
listener. Upon detection of DAV true. the 8291 enters
ACDS and latches the parallel poll response (PPR) byte
into its data in register. The master will be interrupted by
the 8291 BI interrupt when the PPR byte is available. No
interrupts except the IBFI will be generated by the 8292.
The 8292 will respond to this command only when it is the
active controller.
F6 -

GTSB -

Go To Standby

If the 8292 is the active controller, ATNO will go high
·then TCI will be generated. If the data transmission does
not start, a TOUT2 error will be generated.
F7 -

SLOC -

Set Local Mode

If the 8292 is the system controller, then REN will be asserted false and TCI will be set true. If it is not the system
controller. the User Error bit will be set in the Error Flag
Register.

Stop Counter Interrupts

This command disables the internal counter interrupt so
that the 8292 will stop interrupting the master on event
counter underflows. However, the counter will continue
counting and its contents can still be used.

RSTI -

The function causes ATNO to go high and the counter
will be enabled. If the 8292 was not the active controller,
this command will exit immediately. If the 8292 is the
active controller, the counter will be loaded with the
value stored in the Event Counter Register, and the
internal interrupt will be enabled so that when the
counter reaches zero, the SPI interrupt will be gener·
ated. SPI will be generated every 256 counts thereafter
until the controller exits the standby state or the SPCNI
command is written. An initial count of 256 (zero in the
Event Counter Register) will be used if the WEVC
command is not executed. If the data transmission does
not start, a TOUT2 error will be generated.
F5 -

OP

Reset

This command resets any pending interrupts and clears
the error flags. The 8292 will not return to any loop it was
in (such as from the time out interrupts).

Error Mask Register
! TOUT3! TOUT2 ! TOUT,

RST -

This command has the same effect as asserting the
external reset on the 8292. For details, refer to the reset
procedure described later.

User error occurs when request to assert IFC or
REN was received and the 8292 was not the
system controller.

USER

procedure while transferring control to another controller. The 8292 will respond to this command only if it
is in the active state. ATNO will go high, and CIC will be
high so that this 8292 will no longer be driving the ATN
line on the GPIB interface bus. TCI will be set upon
completion.

F8 -

SREM -

Set Interface To Remote Control

This command will set REN true and TCI true if this 8292 is
the system controller. If not. the User Error bit will be set in
the Error Flag Register.

Go To Idle

This command is used during the transfer of control

10-34

231322-001

8292
F9 -

ABORT - Abort All Operation, Clear Interface

This command will cause IFC to be asserted true for at
least 100 !lsec if this 8292 is the system controller. If it Is
in CIDS, it will take control over the bus (see the TCNTR
command).
FA - TCNTR -

Take Control

The transfer of control procedure is coordinated by the
master with the 8291 and 8292. When the master
receives a TCT message from the 8291, it should issue
the TCNTR command to the 8292. The following events
occur to take control:
1. The 8292 checks to see if it is in CIDS, and if not, it
exits.
2. Then ATNI is checked until it becomes high. If the
current controller does not release ATN for the time
specified by the Time Out Register, then a TOUT1
error is generated. The 8292 will return to this loop
after an error or any· command except the RST and
RSTI commands.
3. After the current controller releases ATN, the 8292
will assert ATNO and CIC low.
4. Finally, the TCI interrupt is generated to inform the
master that it Is in control of the bus.

wait for at least 1.5 !lsec. (T10) and then ATNO will go
low. If DAV does not go low, a TOUT3 error will be
generated. If the 8292 successfully takes control, it sets
TCI true.
FE -

STCNI -

Start Counter Interrupts

This command enables the internal counter interrupt.
The counter is enabled by the GSEC command.

UTILITY COMMANDS
All these commands are either Read or Write to registers
in the 8292. Note that writing to the Error Mask Register
and the Interrupt Mask Register are done directly.
E1 -

WTOUT -

Write To Time Out Register

The byte written to the data bus buffer (with Ao; 0)
following this command will determine the time used
for the time out function. Since this function is implemented in software, this will not be an accurate time
measurement. This feature Is enable or disable by the
Error Mask Register. No interrupts except for the IBFI
will be generated upon completion.

FC - TCASY - Take Control Asynchronously
TCAS transfers the 8292 from CSBS to CACS indepen·
dent of the handshake lines. If a bus hang up is detected
(by an error flag), this command will force the 8292 to
take control (asserting ATN) even if the AH function is
not in ANRS (Acceptor Not Ready State). This command
should be used very carefully since it may cause the
loss of a data byte. Normally, control should be taken
synchronously. After checking the controller function
for being in the CSBS (else it will exit immediately),
AiiiJLj will go low, and a TCI interrupt will be generated.
FD - TCSY -

E2 - WEVC - Write To Event Counter
The byte written to the data bus buffer (with Ao; 0)
following this command will be loaded into the Event
Counter Register and the Event Counter Status for byte
counting or EOI counting. Only IBFI will indicate
completion of this command.
E3 -

REVC -

Read Event Counter Status

This command transfers the contents of the Event
Counter into the data bus buffer. A TCI is generated
when the data is available in the data bus buffer.

Take Control Synchronously

There are two different procedures used to transfer
8292 from CSBS to CACS depending on the state of
8291 in the system. If the 8291 is in "continuous
cycling" mode (Aux. Reg. AO; A1; 1), then
following procedure should be followed:

the
the
AH
the

1. The master microprocessor stops the continuous AH
cycling mode in the 8291;
2. The master reads the 8291 Interrupt Status 1
Register;
3. If the END bit is set, the master sends the TCSY
command to the 8292;
4. If the END bit was not set, the master reads the 8291
Data In Register and then waits for another BI
interrupt from the 8291. When it occurs, the master
sends the 8292 the TCSY command.
If the 8291 is not in AH cycling mode, then the master
just waits for a BI interrupt and then sends the TCSY
command. After the TCSY command has been issued,
the 8292 checks for CSBS. If CSBS, then it exits the
routine. Otherwise, it then checks the DAV bit in the
GPIB status. When DAV becomes false, the 8292 will

10-35

E4 -

RERF -

Read Error Flag Register

This command transfers the contents of the Error Flag
Register into the data bus buffer. A TCI .is generated
when the data is available.
E5 -

RINM -

Read Interrupt Mask Register

This command transfers the contents of the Interrupt
Mask Register into the data bus buffer. This register is
available to the processor so that it does not need to
store this information elsewhere. A TCI is generated
when the data is available in the data bus buffer.
E6 -

RCST -

Read Controller Status Register

This command transfers the contents of the Controller
Status Register into the data bus buffer and a TCI interrupt is generated.
E7 -

RBST -

Read GPIB Bus Status Register

This command transfers the contents of the GPIB Bus
Status Register into the data bus buffer, and a TCI
interrupt is generated when the data is available.

231322-001

8292
E9 - RTOUT -

Read Time Out Status Register

This command transfers tlie contents of the Time Out
Status Register Into the data bus buffer, and a TCI
interrupt Is generated when the data is available.
EA -'- RERM -

Read Error Mask Register

With the first group, the TCI interrupt will be used to
indicate that the required response is ready In the data
bus buffer and the master may continue and read it.
With the second group, the interrupt will be used to
indicate completion of the required task, so that the
master may send new commands.

This command transfers the contents of the Error Mask
Register to the data bus buffer so that the processor
does not need to store this information elsewhere. A TCI
interrupt is generated when the data is available.

The SPI should be used when immediate information or
special events is required (see the Interrupt Status
Register).

Interrupt Acknowledge

When interrupt based communication is not desired, all
interrupts can be masked by the interrupt mask register.
The communication with the 8292 is based upon
sequential poll of the interrupt status register. By
testing the OBF and IBF flags, the data bus buffer
status is determined while special events are determined by testing the other bits.

SYC

ERR

SRO

EV

IFCR

I

Each named bit in an Interrupt Acknowledge (lACK)
corresponds to a flag In the Interrupt Status Register.
When the 8292 receives this command, it will clear the
spj and the corresponding bits in the Interrupt Status
Register. If not ail the bits were cleared, then the SPI will
be set true again. If the error flag Is not acknowledged
by the lACK command, then the Error Flag Register will
be transferred to the data bus buffer, and a TCI will be
generated.
NOTE: XXXX1X11is an undefined operation or utility
command, so no cO(1flict exists between the lACK
operation and utility commands.

"Polling Status" Based Communication

Receiving IFC
The IFC pulse defined by the IEEE·488 standard is at
least 100 joIsec. In this time, all operation on the bus
should be aborted. Most Important, the current controller (the one that Is in charge at that time) should stop
sending ATN or EOI. Thus, IFC must externally gate CIC
(controller in charge) and ATNO to ensure that this
occurs.
Reset and Power Up Procedure
After the 8292 has been reset either by the external reset
pin, the device being powered on, or a RST command,
the following sequential events will take place:

SYSTEM OPERATION
8292 To Master Processor Interface
Communication between the 8292 and the Master
Processor can be either interrupt based communication
or based upon polling the interrupt status register in
predetermined intervals.
Interrupt Based Communication
Four different interrupts are available from the 8292:
OBFI
IBFI
TCI
SPI

Output Buffer Full Interrupt
Input Buffer Not Full Interrupt
Task Completed Interrupt
Special Interrupt

Each of the interrupts is enabled or disabled by a bit in
the Interrupt mask register. Since OBFI and IBFI are
directly connected to the OBF and IBF flags, the master
can write a new command to the input data bus buffer
as soon as the previous command has been read.
The TCI interrupt is useful when the master is sending
commands to the 8292. The pending TCI will be cleared
with each new command written to the 8292. Commands
sent to the 8292 can be divided into two major groups:
1. Commands that require response back from the 8292
to the master, e.g., reading register.
2. Commands that initiate some action or enable
features but do not require response back from the
8292, e.g., enable data bus buffer interrupts.

10-36

1. All outputs to the GPIB interface will go high (sru:i,
ATNI, IFC, SYC, CLTH, ATNO, CIC, TCI, SPI, EOI,
OBFI, 1BFf, IDW,REVj.
2. The four interrupt outputs (TCI, SPI, OBFI, IBFI) and
CLTH output will go low.
3. The following registers will be cleared:
Interrupt Status
Interrupt Mask
Error Flag
Error Mask
Time Out
Event Counter (= 256), Counter is disabled.
4. If the 8292 is the system controller, an ABORT
command will be executed, the 8292 will become the
controller in charge, and it will enter the CACS state.
If it is not the system controller, it will remain in

cms.
System Configuration
The 8291 and 8292 must be interfaced to an IEEE·488
bus meeting a variety of specifications including drive
capability and loading characteristics. To interface the
8291 and the 8292 without the 8293's, several external
gates are required, using a configuration similar to that
used in Figure 5.

231322-001

8292

GPla

TRANSCEIVERS

r------,~E~0~1--------~N~O~TE~1------------~------------~

3a

EOI

3b

ATN

3c

NOA

3d

NRFD

2.

ATN

1d

EOI

101

IFe

BUS

PROCESSOR

INTERRUPT WR jijj RST CLK ADO DATA

j

TIJf,

I-I--

f------<~IRS,

I--

f-----<~IRS2

f-----<~ICLOCK

-- I--

r---

I--

f-----<~IRESET

I-I--

f-----<~Ijijj
f-----<~I

-WR

I-- f - - - - ; I N T

cs

I--

,-,---+--11-

k-

I--

I--

~~

CLTH

-

'--_ _-,/1 DATA

1-t-----IAo
Iot------ICS
TCI

t---

jijj

'-----t---------------.·I~WI~RI
'--_______________ 1RESET

I-~S~P~I_~

8292

SYC

~

REN
NOTES:
1. CONNECT TO NDAC FOR
BYTE COUNT OR TO EOI
FOR BLOCK COUNT.
2. GATE ENSURES OPEN
COLLECTOR OPERATION
DURING PARALLEL POLL.

r----;EA

"*T

SRO

'-----Iss

1c

T,J-=CO==U"'N""T------'
IFCL

~__~T~o~~--------~
SYSTEM
CONTROLLER
SWITCH

SRo

14.7K

ON~

OFFl

Figure 4. 8291 and 8292 System Configuration
10-37

231322-001

8292

-----rETO MICROPROCESSOR

~
~
~
16
17
18
19
21
22
23

9
10
4
TO
MICROPROCESSOR

6
7
8
3

11

DO

DI01

01

0102

02

0103

03
0104

04
05

0105

06

0106

07
RSO

0107

8291

RSI

Dii58
TJR1

RS2

DAV

Ali
WR

EOI

'l'ESET

ATN

oREO

SRO

DACK

IFC

Cs

NoAC

CLOCK

NRFD

INT

TIR2

GPIB
TRIGGER
OUTPUT

5

TRIG

REN

28

25

29

23

30

10

31

9

32

8

33

7

34

6

35

5

1

0101

24

39

3

26

4

E.

0105

.!!..
0103" .l'!...
0104" .1!...
0105" .l'!...

0106

OIOS· ~

0102"

0103

0104

0107·

0107

Dl08

1

36

DI01-

0102

8293

0108"

TO
IEEE·488
BUS

.!!..
E-

Tfib
DAV· ~

oAV
EOI
ATN

27
24
38
37

~

2

..3§..

.2..

I-

OPTA E-VC

ATNO

OPTB

IFCL

1!.. Vc

MODE 3

c.E..

DO

oAV

~ 01

'-----....!!.

4
10

~ 03

9

17
18
19
9
8
10

"
-'"

4
6
32

TO

33

MICROPROCESSOR

35
36

11

VCC~

15.25PF

--.!. TiR1

02

16

OSCILLATOR
OUTPUT

.E...

t

04
06

SRO

07

REN

AO

Ali

8292

IFC
ATNO

WR
RESETtt

COUNT

Cs

EOl2

TCI

ATNI

21

8

38

6

23

5

2.

23

39

3

34

7

22

11

NoAC

.l'!...

NFRo

NRFo

.1!...

SRO

SRQ"

.l'!...

REN

REN-

~

T/R2

IFC

8293

ATNO
EOI

IFC"

E-

ATN"

..!!.

EOI"

~

TO
I EEE·488
BUS

EOl2

ATNI

SPI
OBFI

IBFI
SYNC

SS

~

X,!

~

EA

~.1

2

05

ATN
NoAC

IFC,
CIC

X2!

CLTH
SVC

1

25

31

24

27

21

24

22

U~

ON

.i

0FF

• =GPIB BUS TRANSCEIVER

IFCL
CIC
OPTA E-VS

CLTH
SVC

OPTa

1!.. v c

MODE2
SYSTEM

CONTROLLER
SWITCH

'=SEE 8041A DATA SHEET FOR ALTERNATE
CRYSTAL CONFIGURATIONS
tt =CAN CONNECT TO SYSTEM RESET SWITCH,
SEE 8041A DATA SHEET

Figure 5. 8291, 8292, and ,8293 System Configuration

10-38

231322-001

8292
'NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ......... O'C to 70'C
Storage Temperature ............. -65'C to +150'C
Voltage on Any Pin With Respect
to Ground ........................... 0.5V to + 7V
Power Dissipation ......................... 1.5 Watt

D.C. CHARACTERISTICS

(TA

= O'C to 70'C,

Vss

= OV: 8292, Vee = ~5V

~10%)

Min.

Max.

Unit

V ILl

Input Low Voltage (Ail Except Xl> X2, RESET)

-0.5

0.8

V

V IL2

Input Low Voltage (Xl, X2, RESET)

-0.5

0.6

V

V IH1

Input High Voltage (Ail Except Xl, X2, RESET)

2.2

Vcc

V

3.8

Parameter

Symbol

Test Conditions

VIH2

Input High Voltage (Xl> X2, RESET)

Vcc

V

Vall

Output Low Voltage (Do-D7)

0.45

V

IOL=2.0 mA

VOL2

Output Low Voltage (Ail Other Outputs)

0.45

V

10L= 1.6 mA
10H= -400 I'A

V OH1

Output High Voltage (Do-D7)

2.4

V

VOH2

Output High Voltage (Ail Other Outputs)

2.4

V

IlL

Input Leakage Current (COUNT, IFCL, RD, WR, CS, Ao)

±10

10H= -50 I'A

I'A

Vss'; VIN'; Vcc
Vss + 0.45.; V IN .; Vcc

laz

Output Leakage Current (Do-D7' High Z State)

±10

I'A

ILI1

Low Input Load Current (Pins 21-24, 27-38)

0.5

mA

VIL=0.8V

0.2

mA

VIL=0.8V

ILl2

Low Input Load Current (RESET)

Icc

Total Supply Current

125

mA

Typical = 65 mA

IIH

Input High Leakage Current (Pins 21-24, 27-38)

100

/LA

\1N

CIN

Input Capacitance

10

pF

CliO

I/O Capacitance

20

pF

A.C. CHARACTERISTICS

(TA

= Vee

= O°C to 70'C. Vss = OV: 8292, Vee = +5V ~10%)

DBB READ
Symbol

Min.

Parameter

Max.

Unit

Test Conditions

tAR

CS, Ao Setup to RDJ.

0

ns

tRA

CS, Ao Hold After RDt

0

ns

tRR

RD Pulse Width

tAO

CS, Ao to Data Out Delay

225

ns

CL= 150 pF

tRo

RDJ. to Data Out Delay

225

ns

CL= 150 pF

tOF

RDt to Data Float Delay

100

ns

tCY

Cycle Time

2.5

15

1'5

Min.

Max.

Unit

250

ns

DBBWRITE
Symbol

Parameter

tAw

CS, Ao Setup to WRJ.

0

ns

tWA

CS, Ao Hold After WRt

0

ns

tww

WR Pulse Width

250

ns

tow

Data Setup to WRt

150

ns

two

Data Hold After WRJ.

0

ns

10-39

Test Conditions

231322-001

8292
COMMAND TIMINGS[1.3)
Nlmo

Execution
Time

IBFII

E1

WTOUT

63

24

E2
E3

WEVC

63

24

AEVC

24

E4

AEAF

E5

AINM

C~e

TCIIZI

SPI

ATNO

CIC

161

161

1179

1174

iFC

REN

EOI

DAV

Commenls

51

E6

ACST

71
67
69
97

24

77

E7

RBST

92

24

72

24

47

24

49

E8
E9

ATOUT

69

24

49

EA

AEAM

69

24

49

FO

SPCNI

24

F1

GIOL

53
88

F2

AST

94

24

F2

AST

214

24

Count Stops After 39

24

F3

ASTI

61

24

F4

GSEC

125

24

F5

EXPP

75

24

F6

GTSB

118

24

70
152
192

152

Not System Controller

107

198

100

191

F7

SLOC

73

24

55

SREM

91

24

73

F9

155

24

133

FA

ABOAT
TCNTA

108

24

88

1120
171

FC

TCAS

92

24

67

155

91

180

FD

TCSY

115

24

STCNI

59

24

PIN

AESET

29

X

lACK

116

System Controller

153
159

F8

FE

1101

155
157

146
1115

164
142

168

Starts CQunt After 43

-

17

-

17

Not System Controller

173
198

If Interrupt Pending

Notes:
1. All times are multiples of tCY Irom the 8041A command Interrupt.
2. Tel clears alter 7 tCY on all commands.
3. 1 Indicates a level transition from low to high, I indicates a high to low transition.

A.C. TESTING INPUT, OUTPUT WAVEFORM

A.C. TESTING LOAD CIRCUIT

INPUT/OUTPUT

. ?
"=>(
2.0

0.8

0.45

<

2.0

TEST POINTS

0.8

>C

DEVICE
UNDER
TEST

'Icc

A.G. TESTING: INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC" 1'- AND 0.45V FOR
A LOGIC "0." TIMING MEASUREMENTS ARE MADE AT 2.QV FOR A lOGIC 1,.
AND BV FOR A LOGIC '0

a

, CL INCLUDES JIG CAPACITANCE

231322-001

8292
CLOCK DRIVER CIRCUITS
CRYSTAL OSCILLATOR MODE

< 15 pF

DRIVING FROM EXTERNAL SOURCE

r-----tj

:

16 mHz

I

(INCLUDES XTAl,

~

SOCKET. STRAY)

I

+ 5V
470Q

XTAll

~

l>---+------'-lXTALl

+ 5V

I

L_____
15 - 25 pF
(INCLUDES SOCKET,

STRAV)

3

XTAl2
470~~

I-=-

'---~---''i

XTAL'

BOTH XTAl1 AND XTAL2 SHOULD BE DRIVEN.
CRYSTAL SERIES RESISTANCE SHOULD 8E
<7SQ AT 6 MHz; <1BOQ AT 3.6 MHz.

RESISTORS TO Vee ARE NEEDED TO ENSURE VtH

=3.SV

IF TTl CIRCUITRY IS USED.

LC OSCILLATOR MODE
20 pF
120 ... H

20pF

;~~~rnz. '

~C
-=-

C,_~+3Cpp

XTAl1

l

-

,

C

~~P~~I~;~6~ PIN·la·PIN

3 XTAl2

EACH C SHOULD BE APPROXIMATELY 20 PF,INCUJDlNG STRAY CAPACITANCE.

WAVEFORMS
READ OPERATION-DATA BUS BUFFER REGISTER
CS OR Ao
(SVSTEM'S
ADDRESS BUS)

AD
(READ CONTROL)

_ l A O -IRO

~~':r:~~

~

_'OF_~

__________-.or----D-A-T-A-VA-L-ID----""o...._ _ _ _ _ _ _ _ __
~----------------~

r
'w_W~~~~~~~-...

WRITE OPERATION - DATA BUS BUFFER REGISTER
(SVSTEM'S
CSORA0=1

ADDRESS BUS)

(WRITE

CONTR~~

~ 'AW -11"--_______

1...-------------------

'i.

_
--tow-

V

-

Iwo

V

~~
~
~
(INPUT) _ _ _ _M_A_Y_C_H_A_NG_E_ _ _-J/I.,...__D_A_T_A_V_AL_I_D_ _'f"~'__ _ _..;M;;:.A;,,;V..,;C..,;H;,.;A;,,;NG;;;E;;...._ _ __

10-41

231322-001

inter

8292

APPENDIX
The following tables and state diagrams were taken
from the IEEE Standard Digital Interface for Program-

mabie Instrumentation, IEEE Std. 488-1978. This document Is the official standard for the GPIB bus and can be
purchased from IEEE, 345 East 47th St., New York, NY
10017.

C MNEMONICS
Messages

Interface States

pon = power on
rsc
request system control
rpp
request parallel poll
gts
go to standby
take control asynchronously
tca
take. control synchronously
tcs
send Interface clear
sic
sre
send remote enable

CIOS
CADS
CTRS
CACS
CPWS
CPPS

=
=
=
=
=
=
=
IFC =interface clear
ATN =attention

CSBS
CSHS
CAWS
CSWS
CSRS
CSNS
SNAS
SACS
SRIS
SRNS
SRAS
SIIS
SINS
SIAS

TCT = take control

~

=controller idle state
= controller addressed state
= controller transfer state
= controller active state
= controller parallel poll walt state
= controller parallel poll state

=controller standby state
=controller standby hold state
=controller active wait state
=controller synchronous wait state
=controller service requested state
=controller service not requested state
= system control not active state
= system control active state
= system control remote enable Idle state
= system control remote enable not active state
= system control remote enable active state
= system control Interface clear Idle state

=system control interface clear not active state

= system control Interface clear active state

=accept data state (AH function)

(ANRS) = acceptor not ready state (AH function)
(SOYS) = source delay state (SH function)
(STRS) = source transfer state (SH function)
(TAOS)

pon _

+
e

CillID

=talker addressed state (T function)

e

SRC

~Q

elDS I~.>----"'="--- eTRS

iFCA~/

(WI~::~) ~

A TeT A

~I

O~

TeT AA@@

I~I

@ill

ATN

1CS/\~

rpp"~A~

 1.5 ~"C

t THE MICROPROCESSOR MUST WAIT FOR THE 80
INTERRUPT BEFORE WRITING THE GTSB OR GSEe
COMMANDS TO ENSURE THAT (ftlm"mvs)
IS TRUE.

Figure A.1. C State Diagram
10-42

231322-001

8292
REMOTE MESSAGE CODING
Bus Signal Llne(s) and Coding That
Asserts the True Value of the Message
T

C
L

P
E

S
S

M
U

AC
UC
DO

Y 0 0 0 X X X X
X X X X X X X X

HS
HS
UC
ST
DO

X X X X X X X X
XXXXXXXX
Y 0 0 1 0 1 0 0
X X X X X X X X
E E E E E E E E
876 5 4 3 2 1
Y 0 0 0 1 0 0 0
Y 0 0 0 0 0 0 1
X X X X X X X X
X X X X X X X X
Y 0 1 X X X X X
Y 0 0 1 0 0 0 1
Y 0 1 L L L L L .

Y
Mnemonic

Message Name

A

DONN
I
lORD
o
0 AFA
8 7 8 5 4 3 2 1 VOC

A E SIR
TOR F E
N I Q C N

ACG
ATN
DAB

Addressed Command Group
Attention
Data Byte

DAC
DAV
DCL
END
EOS

Data Accepted
Data Valid
Device Clear
End
End of String

GET
GTL
lOY
IFC
LAG
LLO.
MLA

Group Execute Trigger
Go to Local
Identify.
Interface Clear
Listen Address Group
Local Lock Out
My Listen Address

(Note 3)

M

AC
AC
UC
UC
AD
UC
AD

MTA

My Talk Address

(Note 4)

M

AD

Y

MSA

My Secondary Address

(Note 5)

M

SE

y

X X X X

NUL
OSA
OTA
PCG
PPC
PPE

Null Byte
Other Secondary Address
Other Talk Address
Primary Command Group
Parallel Poll Configure
Parallel Poll Enable

M

DO

o

X X X X

(Note 6)

PPD

Parallel Poll Disable

(Note 7)

PPR1
PPR2
PPR3
PPR4
PPR5
PPR6
PPR7
PPR8
PPU.
REN
RFD
ROS
SCG
SOC
SPD
SPE
,SRO
STB

Parallel Poll Response 1
Parallel Poll Response 2
Parallel Poll Response 3
Parallel Poll Response 4
Parallel Poll Response 5
Parallel Poll Response 6
Parallel Poll Response 7
Parallel Poll Response 8
Parallel Poll Unconfigure
Remote Enable
Ready for Data
Request 'Servlce
Secondary Command Group
Selected Device Clear
Serial Poll Disable
Serial Poll Enable
Service Request
Status Byte

TCT
TAG
UCG
UNL
UNT

Take Control
Talk Address Group
Universal Command Group
Unlisten
Untalk

M

(Notes 1, 9)

U

U
M
U
(Notes 2, 9)

M
M
M
U
U
·M

M.

XXX
XXX
XXX
XXX
XXX
XXX
XXX

1
1
X
X

o

X X X X
X X X X
1 X X X
X X 1 X
t X X X X
1 X X X X
1'XXXX

0 T T T T T

XXX

X X X X

5 4 3 2 1

M
M

SE

Y

U
U
U
U
U
U
U
U
M
U

ST
ST
ST
ST
ST
ST
ST
ST
UC
UC
HS
ST
SE
AC
UC
UC
ST
ST

U
U

M
M

M
M
U
M

M

(Note 11)

XXX-XX
X X X X X
1 X X X X
o1 X X X
X X X X

AC
SE

M

(Notes 8, 9)

XXO
1XX
XXX
XXX
XXX

S S S S S XXX
5 4 321
0 0 0 0 0 0 0 XXX X
(OSA = SCG A MSA)
(OTA=TAG AMTA)
(PCG = ACG v UCG v LAG v
Y 0 0 0 0 1 0 1 XXX 1
Y 1 1 0 S P P P XXX 1

M

(Note 9)

0 0 0 0 0 0 0

1 X X X X
1 X X X X
0 X X X X

5 4 3 2 1

M SE
M AD

(Note 10)

o

8 7 6 5 4 3 2 1

XXX
XXX
XXX

M
M
M
M

AC
AD
UC
AD
AD

X
X
X
X
X
X

o

X
X
X
X
X
X

X
X
X
X
X
1

X
X
X
X
1

X

4
X
X
X
1
X
X

3 2 1
0 0 0
3 2 1

XXX

X
X
1
X
X
X

XXX
XXX
XXX
XXX
XXX
XXX

X
1
X
X
X
X

1
X
X
X
X
X

X 1 XXXXXX

xxx

1 X X X X X X X
Y 0 0 1 0 1 0 1
XXXXXXXX
XXXXXXXX
X 1 X X X X X X
Y11XXXXX
Y 0 0 0 0 1 0 0
Y 0 0 1 100 1
Y 0 0 1 100 0
XXXXXXXX
S X S S S S S S
8
6 5 4 321
Y 0 0 0 1 001
Y 1 0 X X X X X
Y 0 0 1 X X X X
Y0111111
Y1011111

XXX
XXX
XXX
XOX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX

TAG)
X X X X
X X X X
X X X X
X
X
X
X

X
X
X
X

X
X
X
X

X X X
X X X

X X X
1
X
X

o

1
1
1
1
X

o

1
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
~ X
X 1
X X

X
X
X
X
X
X
X
X
X
X
X

X
X
1
X
X
X
X
X
X
X
X

X
X
X
X
X

X
X
X
X
X

X
X
X
X
X

X
X
X
X
X

The 1/0 coding on ATN when sent concurrent with multiline messages has been added to this revision for interpretive convenience.

10-43

231322-001

8292

NOTE5:
1.
2.
3.
4.
5..
6.

01-0B specify the device dependent data bits.
E1-EB specify the device dependent code used to indicate the E05 message.
L1-L5 specify the device dependent bits of the device's listen address.
T1-T5 specify the device dependent bits of the device's talk address.
51-55 specify the device dependent bits of the device's secondary address.
5 specifies the sense of the PPR.
Response = 5 EEl 1st

P1-P3 specify the PPR message to be sent when a parallel poll Is executed.
P3

o

P2
0

P1
0

PPR Message
PPR1

PPRB
7.

01-04 specify don't-care bits that shall not be decoded by the receiving device. It is recommended that all zeroes
be sent.
B. 51-56, 5B specify the device dependent status. (0107 Is used for the RQ5 message.)
9. The source of the message on the ATN line Is always the C function, whereas the messages on the 010 an!! EOI
lines are enabled by the function.
.
10. The source of the messages on the ATN and EOI lines is always the C function, whereas the source of· the
messages on the 010 lines Is always the PP function.
11. This code is provided for system use, see 6.3.

r

10-44

231322-001

8294A
DATA ENCRYPTION/DECRYPTION UNIT
Certified by National Bureau of
• Standards

• 7·Bit User Output Port

•
Data Encryption Using 56·Bit
• 64·Bit
Key

Compatible with iAPX-86,88,
• Fully
MCS-85™, MCS-8o.™, MCS·51TM, and

40.0. Byte/Sec Data Conversion Rate

• DMA Interface
3 Interrupt Outputs to Aid in Loading
• and
Unloading Data

• Single 5V :!:

10.% Power Supply

MCS-48™ Processors
Federal Information
• Implements
Processing Data Encryption Standard

• Encrypt and Decrypt Modes Available

The Inteli!!> 8294A Data Encryption Unit (DEU) is a microprocessor peripheral device designed to encrypt and decrypt 64-bit
blocks of data using the algorithm specified in the Federal Information Processing Data Encryption Standard. The DEU
operates on 64-bit text words using a 56-bit user-specified key to produce 64-bit cipher words. The operation is reversible:
if the cipher word is operated upon, the original text word is produced. The algorithm itself is permanently contained in the'
8294A; however, the 56-bit key is user-defined and may be changed at any time.
The 56-bit key and 64-bit message data are transferred to and from the 8294A in 8-bit bytes by way of the system data bus. A
DMA interface and three Interrupt outputs are available to minimize software overhead associated with data transfer. Also,
by using the DMA interface two or more DEUs may be operated in parallel to achieve effective systElm,conversion rates
which are virtually any multiple of 400 bytes/second. The 8294A also has a 7-bit TTL compatible output port for
user-specified functions.
Because the 8294A implements the NBS encryption algorithm it can be used in a variety of Electronic Funds Transfer
applications as well as other electronic banking and data handling applications where data must be encrypted.

NC
Xl
X2
RESET
Vee

DATA
BUS

cs

AD

Ao

AD

SRO

iVA

CAV
ceMP
PO·P6

.~~

01
02
03
04

SYNC

x,

X2
.'V-POWER-'_
GNO-_

SYNC
DO

TIMING

05
06
07
GNO

INTERNAL
BUS

Figure 1. Block Diagram

VCC
NC
OACK
DAD
SAO
OAV
NC
P6
P5
P4
P3
P2
Pl
PO
VOO
Vee
eCMP
NC
Ne
NC

Figure 2. Pin Configuration

Intel Corporation Assumes No Responsibility for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses ale Implied. Information Contained
Herein Supersedes Previously Published Specifications On The Devices From Intel.
SEPT 1984
©INTEL CORPORATION, 1964
ORDER NUMBER: 210465·003

10-45

8294A

Table 1. Pin Description
Pin
Symbol No. Type

NC

39

I

Crystal: Inputs for crystal. LCC or exter·
nal timing signal to determine internal
oscillator frequency.

DACK

38

I

I

Raut: A low signal to this pin resets the
8294A.

DMA Acknowledge: Input signal from
the 8257 DMA Controller acknowledging that the requested DMA cycle has
been granted.

DRO

37

0

DMA Request: Output Signal to the
8257 DMA Controller requesting a DMA
cycle.

SRO

36

0

Service Request: Interrupt to the CPU
indicating that the 8294A is awaiting
data or commands at the Input buffer.
SRQ=1 implies IBF=O.

OAV

35

0

Output Available: Interrupt to the CPU
indicating that the 8294A has data or
status available in its output buffer.
OAV=1 Implies OBF=1.

NC

34

P6
P5
P4
P3
P2
P1
PO

33
32
31
30
29
28
27

0

Output Port: User output port lines.
Output lines available to the user via a
CPU command which can assert sel~
ected port lines. These lines have nothing to do with the encryption function.
At power-on. each line is in a 1 state.

Voo

26

1

X1
X2

2
3

RESET

4

Vee

5

CS

6

GND

7

RD

8

I

Read: An active low read strobe at this
pin enables the CPU to read data and
status from the internal DEU registers.

1.0

9

I

Address: Address input used by the
CPU to select DEU registers during read
and write operations.

No Connection.

P_ar: Tied high.
I

Chip Select: A low signal to this pin
enables reading and writing to the 8294A.
Ground: This pin must be lied to
ground.

WR

10

I

Write: An active low write strobe at this
pin enables the CPU to send data and
commands to the DEU.

SYNC

11

0

Sync: High frequency (Clock.,. 15) out·
put. Can be used as a strobe for external
circuitry.

Do
D,
D.
D3
D,
Ds
D6
D7

12
13
14
15
16
17
18
19

I/O .Data Bus: Three-state, bl·dlrectlonal'
data bus lines used to transfer data be·
tween the CPU and the 8294A.

GND

20
40

Name and Function

No Connection.

NC

Vcc

Pin
Symbol No. Type

Name and Function

No Connection.

Power: +5V power input. (+5V ±10%)
Low power standby pin.
Power: Tied high.

Vcc

25

CCMP

24

Ground: This pin must be lied to
ground.

NC

23

No Connection.

NC

22

No Connection.

Power: +5 volt power input: +5V ±
10%.

NC

21

No Connection.

1Q-46

0

Conversion Complete: Interrupt to the
CPU indicating that the encryptionl
decryption of an 8-byte block is complete.

210465-004

inter

8294A

FUNCTIONAL DESCRIPTION

IBF

Input Buffer Full; A write to the Data Input Buffer
or to the Command Input Buffer sets IBF = 1 The
DEU resets this flag when it has accepted the
input byte. Nothing should be wnllen when
IBF = 1.

DEC

Decrypt; indicates whether the DEU is in an en·
crypt or a decrypt mode. DEC = 1 implies the
decrypt mode. DEC 0 implies the encrypt
mode.

OPERATION
The data conversion sequence is as follows:

1. A Set Mode command is given, enabling the desired
interrupt outputs.
2. An Enter New Key command is issued, followed by 8
data inputs which are retained by the DEU for encryp·
tion/decryption. Each byte must have odd parity.
3. An Encrypt Data or Decrypt Data command sets the
DEU in the desired mode.
After this, data conversions are made by writing 8 data
bytes and then reading back 8 converted data bytes. Any
of the above commands may be issued between data
conversions to change the basic operation of the DEU;
e.g., a Decrypt Data command could be issued to
change the DEU from encrypt mode to decrypt mode
without changing either the key or the interrupt outputs
enabled.

=

After 8294A has accepted a 'Decrypt Data' or
'Encrypt Data' command, 11 cycles are required to
update the DEC bit.
CF

Completion Flag; This flag may be used to indio
cate any or all of three events in the data transfer
protocol.
1. It may be used in lieu of a counter in the
processor routine to flag the end of an 8·
byte transfer.
2. It must be used to indicate the validity of
the KPE flag.
3. It may be used in lieu of the CCMP interrupt
to indicate the completion of a DMA oper·
ation.

INTERNAL DEU REGISTERS
Four internal registers are addressable by the master
processor: 2 for input, and 2 for output. The following
table describes how these registers are accessed.
RD

WR

CS

Ao

1

0
1

0
0
0

0
0

o

o

o

o
X

X

X

Key Parity Error; After a new key has been
entered, the DEU uses this flag in conjunction
with the CF flag to indicate correct or incorrect
parity.

KPE

Register
Data input buffe'r
Data output buffer
Command input buffer
Status output buffer
Don't care,

The functions of each of these registers are described
below.
Data Input Buffer - Data written to this register is inter·
preted in one of three ways, depending on the preceding
command sequence.
1. Part of a key.
2. Data to be encrypted or decrypted.
3. A DMA block count.

COMMAND SUMMARY
1-

Enter New Key

a P co DE:

1'--0""'1""""11-0"1-0'-10-'1-0'-10-'1-'01
MSB

2-

Encrypt Data

OP CODE:

'10--'1-01'1"1-1'I0-'1-0'-10'1-'01
MSB

Data Output Buffer - Data read from this register is the
output of the encryption/decryption operation.

LSB

This command puts the 8294A into the encrypt mode.
3-

Command Input Buffer - Commands to the DEU are
written into this register. (See command summary
below.)

LSB

This command is followed by 8 data byte inputs which
Ire retained in the key buffer (RAM) to be used in
encrypting and decrypting data. These data bytes must
have odd parity represented by the LSB.

Decrypt Data

oP COD E:

r-,0" 0',-1,r-o"0',-0" 0"'0,
MSB

LSB

This command puts the 8294A into the decrypt mode.
Status Output Buffer - DEU status is available in this
register at all times. It is used by the processor for poll·
driven command and data transfer operations.

4 -

Set Mode

OP CODE:

FUNCTION:

OBF

10 1010101A IB 1C 1OJ
MSB

STATUS BIT:

x

x

KPE

CF

DEC

IBF

LSB

where:

=

Output Buffer Full; OBF 1 indicates that output
from the encryption/decryption function is
available in the Data Output Buffer. It is reset
when the data is read.

A
B
C
D

10-47

is the OAV (Output Available) interrupt enable
is the SRQ (Service Request) interrupt enable
is the DMA (Direct Memory Access) transfer enable
is the CCMP (Conversion Complete) interrupt enable
210465-004

intJ

8294A

This command determines which interrupt outputs will
be enabled. A "1" In bits A, B, or D will enable the OAV,
SRO, or CCMP Interrupts respectively. A "1" In bit C will
allow DMA transfers. When bit C is set the OAV and
SRO interrupts should also be enabled (bits A,B= 1).
Following the command In which bit C, the DMA bit, is
set, the 8294 will expect one data byte to specify the
number of 8·byte blocks to be converted using DMA.
5-

After the Enter New Key command is issued, 8 data bytes
representing the new key are written to the data Input
buffer (most significant byte first). After the eighth byte is
entered into the DEU, CF goes true (CF=1). The CF bit
goes false ,again when KPE is valid. The CPU, can then
check the KPE flag. If KPE= 1, a parity error has been
detected and the DEU has not accepted the key. Each byte
is checked for odd parity, where the parity bit is the LSB of
each byte.

Write to Output Port

'-',C-P-6 ,...,P-S ,-P4"",-P-3" P-2"-P,',-po"",

OP CODE:

Since CF=1 only for a short period of time after the last
byte is accepted, the CPU which polls the CF flag might
miss detecting,CF=1 momentarily. Thus, a counter should
be used, as 'in Figure4, to flag the endofthe new key entry.
Then CF is used to indicate a validKPE flag.

T

r-,

MSB

LSB

This command causes the 7 least significant bits of the
command byte to be latched as output data on the 8294
output port. The initial output data is 1111111. Use of
this port Is independent of the encryption/decryption
function.

PROCESSOR/DEU INTERFACE PROTOCOL
ENTERING A NEW KEY
The timing sequence for entering a new key is shown in
Figure 3. A flowchart showing the CPU software to
accommodate this sequence' is given in Figure 4.

(lFENAB~:

LJUL __ J-lL.______

DATA REGISTER

1 BYTE OF KEY

1-1+1
CF

OJ

L

KPE _ _ _ _ _ _'_NV_A_LlD
_____

NO

~

··-.fL-l..J-Lr--.:..L.f-----~rL
CHECKLr
KPE

WR 1Jl.E:1E:----U
KEY

KEY

KEY

DATA

DATA

DATA

8

NEW
KEY
COMMAND

Figure 4. Flowchart for Entering a New Key

Figure 3. Entering a New Key

10-48

210465-004

intJ

8294A
USING SOFTWARE COUNTER

ENCRYPTING OR DECRYPTING DATA

Figure 5 shows the timing sequence for encrypting or
decrypting data. The CPU writes a d'lta bytes to the
DEU's data input buffer for encryption/decryption. CF
then goes true (CF = 1) to indicate that the DEU has
accepted the a·byte block. Thus, the CPU may test for
IBF = 0 and CF = 1 to terminate the input mode, or it
may use a software counter. When the encryption/·
decryption is complete, the CCMP and OAV interrupts
are asserted and the OBF flag is set true (OBI" = 1). OAV
and OBF are set false again after each of the converted
data bytes is read back by the CPU. The CCMP interrupt
is set false, and remains false, after the first read. After
a bytes have been read back by the CPU, CF goes false
(CF = 0). Thus, the CPU may test for CF = 0 to terminate
the read mode. Also, the CCMP interrupt may be used to
initiate a service routine which performs the next series
of a data reads and a data writes.

DATA REGISTER-l DATA BYTE

"-1+1

NO

NO

n

CCMPi

(IF ENABLED)

SR°LrL

(IF ENABLED)

18'

_

n

-.lLJl_--.ll

OAV

IF ENABLED)

08.

c.]

I

RIi

lLJ1_lL
ILJ1 lL
I
lJL.f-LJ

USING CF FLAG

WR~-LJ
8 DATA WRITES

20

ma -

MAXIMUM

8 DATA REAOS

IBF =o?

TYES

I

DATA REGISTER-1 DATA BYTE

L-_ _ _....!!N~OI'

CF = 1? )
YES

Figure 5. Encrypting/Decrypting Data

(

Figure 6 offers two flowcharts outlining the alternative
means of implementing the data conversion protocol.
Eitl'ler the CF flag or a software counter may be used to
end the read and write modes.

. SRQ= 1 implies IBF=O, OAV= 1 implies OBF= 1. This
allows interrupt routines to do data transfers without
checking status first. However, the OAV service routine
must detect and flag the end of a data conversion.

10-49

I_ _ _ _-"N~O(

CF=O?

I NO

?-8

OBF=1? )

!YES
I

I

READ 1 CODED DATA BYTE

I

I

Figure 6. Data Conversion Flowcharts
210465·004

·m~r
I.I-e-

8294A

USINGDMA

The timing sequence for data conversions using DMA is
shown in Figure 7. This sequence can be better
understood when considered in conjunction with the
hardware DMA interface in Figure 8. Note that the use of
the DMAfeature requires 3 external AND gates and 2
DMA channels (one for input, one for output). Since the
DEU hasonly one DMA request pin, the SRO and OAV
outputs are used in conjunction with two of the AND
gates to create separate DMA request outputs for the 2
DMA channels: The third AND gate combines the two
active·low DACK inputs.
ceMP - - ,

CF

=rI'---~-------l1
n

SRO ---,
I.FEN"eLEIlI

r

-l

IIFENA8LED'_-1I_ _ _--'-_ _ _ _ _ _ _ _ _ _ _

U

r I r--l
U
U
1..._ _ _ _ _ _ __

To initiate a DMA transfer, the CPU must first initialize
the two DMA channels as shown in the flowchart in
Figure 9. It must then issue a Set Mode command to the
DEU enabling the OAV,SRO, and DMA outputs. The
CCMPinterrupt may be enabled or disabled, 'depending
on whether that output is desired. Following the Set
Mode command, there must be a data byte giving the
number of 8·byte blocks of data (n<256) to be converted.
The DEU then gener!ltes the required number" of DMA
requests to. the 2. DMA channels wi,th no f.urther CPU
intervention. When the requested number of blocks
has been converted, the DEU will set CF and assert the
CCMP interrupt (if enabled). CCMP ttien goes IIllse
again with the next write to the DEU (command or data).
Upon completion of' the conversion, the DMA mode is
disabled and the DEU returns' to the encrypt/decrypt
mode. The enabled. 'Interrupt outputs; however,' will
remain enabled until another Set Mode 'conimand' is
issued.
'

r
1" IL_.Jr IL-

DAV

IIFI!N"8L!DI _ _ _ _ _ _ _ _ _ _

ORQ~-Lrl __

om

Wo

JL

---U--lJU--ULJ--Lr

USING DMA

.7

1J1fU--lJ
Jl .
lS-lI-LJ-l[--USET'

DMA
MODE

DMA

INITIALIZE DMA READ CHANNEL POINTEA

---

8 DMA WRITES
BLOCK
8 DMA READS
COUNT (n) _ _ _ _ _ _ _ _ _ _- '

INITIALIZE OMA WRITE CHANNEL POINTER

REPEATED n TIMES

AO

Figure 7. DMA Sequence

,

8257

Figure 9. DMA .Flowchart
SINGLE BYTE COMMANDS

iNT----_---'~,--_~3

XTAL 2

FOR THE 8294A XTAl2 MUST BE HIGH
35-65% OF THE PERIOD
RISE AND FALL TIMES MUST
NOT ExceED 10

n.

RESISTOR TO Vee IS NEEDED
TO ENSURE VIH = 3.0v IF TTL
CIRCUITRY IS USED

Figure 18. Recommended Connection for External Clock Signal

ABSOLUTE MAXIMUM RATINGS·

'NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

Ambient Temperature Under Bias ...... " O'C to 70'C
Storage Temperature, , , , , , , ' .. " - 65'C to + 150'C
Voltage on Any Pin With
Respect to Ground""" .. "" .... -0.5V to +7V
Power Dissipation

., .... ,., .... , ............. 1.5 Watt

D,C. AND OPERATING CHARACTERISTICS
Symbol

Parameter

(TA

= O'C to

Limits
Typ.

=

+5V

=10%, Vss = oY)

Max.

Unit

VIL

Input Low Voltage (All
Except X1, X2, RESET)

-0.5

0,8

V

VIL1

Input Low Voltage (X 1, X2,
RESET
Input High Voltage (All
Except X1, RESET)

-0,5

0.6

V

2.0

Vee

V

3,5

Vee

V

2.2

Vee
0.45

V

IOL = 2.0 rnA

0.45

V

IOL = 1,6 rnA

V IH

VIH2

Input High Voltage (X 1,
RESET)
Input High Voltage (X2)

VOL

Output Low Voltage (0 0-0 7)

VO L1

Output Low Voltage (All
Other Outputs)

VIH1

Min.

70'C, Vee

Test Conditions

V

VOH

Output High Voltage (00-07)

2.4

V

IOH=-400p.A

VOH1

Output High voltage (All
Other Outputs)

2.4

V

IOH=-50p.A

IlL

Input Leakage Current
(RO, WR, CS, Ao)

± 10

p.A

Vss:;;; VIN:;;; Vee

IOFL

Output Leakage Current
(0 0-0 7, High Z State)

± 10

p.A

Vss + 0.45:;;; VOUT :;;; Vee

100
100

+ lee

III
ILl1
IIH

Voo Supply Current

5

20

rnA

Total Supply Current

60

135

rnA

0,3

rnA

V IL = 0.8V

0,2

rnA

V IL = 0.8V

100

p.A

VIN = Vee

Low Input Load Current
(Pins 24, 27-38)
Low Input Load Current
(RESET)
Input High Leakage Current
(Pins 24, 27-38)

CIN

Input Capacitance

10

pF

CliO

I/O Capacitance

20

pF

10-53

210465-004

i~

8294A

A.C. CHARACTERISTICS

(TA = O'C to 70'C, VCC = VOD = +5V ± 10%, Vss =OV)

DBB READ
Symbol

Parameter

Min.
~

tAR

05, Ao Setup to RD

tRA

CS, Ao Hold After 1m t
Fm Pulse Width

tRR

Max.

Unit

0

Test Conditions

ns

0

ns

160

ns

tAD

05, Ao to Data Out Delay

130

ns

CL = 100 pF

tRO

110 ~ to

130

ns

CL -100 pF

1.25

85
15

fls

Min.

Max.

Unit

Data Out Delay

tOF

Fm t to Data Float Delay

tCY

Cycle Time

ns
1-12 MHz Crystal

DBB WRITE
Symbol
tAW

Parameter

es, Ao Setup to WR ~

tWA

CS, Ao Hold After WR

tww

WfiPulse Width

tow

Data Setup to WR

two

Data Hold toWfi

0

t

t

0

ns

160
130

ns
ns

0

ns

t

Test Conditions

ns

DMA AND INTERRUPT TIMING
Symbol

Parameter

Min.

t ACC

DACK Setup to Control

0
0

tCAC

DACK Hold After Control

tACO

bACK to Data Valid

tCRQ
tCI

Max.

Unit

Test Conditions

ns
ns

Control L.E. to ORO T.E.

130
110

ns

ns

Control T.E. to Interrupt T.E.

400

ns

CL =100 pF

CLOCK
8042
Symbol

8742

tCY

Parameter
'CycleTime

Min.
1.25

Max.
9.20

Min.
1.25

tCYC

Clock Period

83.3

613

83.3

tPWH
. tPWL

Clock High Time

33

38

Clock Low Time

~3.

38

Max•.
9.20

Units
flS [l]

613

ns
ns
ns

tR

Clock Rise Time

10

10 '

tF

Clock Fall Time

10

10

ns
. ns

NOTES:
1. ICY = lS/f(XTAL)

A.C. TESTING INPUT, OUTPUT WAVEFORM'

INPUT/OUTPUT

2.'
2.D

>

TEST POINTS

0.45

D.8

<

2.D

D.8

10-54

210465-004

8294A

WAVEFORMS
READ OPERATION-OUTPUT BUFFER REGISTER
CSORAo

]

K

.

-IAR-I

_IRA_

IRR

'2

"\

~~
(OUTPUT)

(SYSTEM'S
ADDRESS BUS)

-tRD-

\.
-IDF-

l

-IAD_

-------------

WRITE OPERATION-INPUT BUFFER REGISTER

1

S OR Ao _ _ _....oJ

+-IAWl

r<
r~~IWW
d~_~I~A+

(SYSTEM'S
ADDRESS BUS)

_

' - - - -

-IDW
DATA BUS
DATA
(INPUT) ______ MAY CHANGE

(WRITE CONTROL)

-IWD

V

V

~~~~

DATA

_ _ _ _J /l-DATA VALlD- { \ ________ MAY CHANGE
~

~~~~

_ _ _ _ _ __

DMA AND INTERRUPT TIMING

--

'\ -tAce-

'\..

RDorWR

'\

r'\.

/

tCAe

/

DRQ
-tCRQtACD

DATA BUS

\
/

K

VALID

OAVorSRQ

-TCI-

10-55

210465-004

intel'
CLOCK TIMING

2.4Y- - XTAL2

1.6Y _ _ _
.4SY _ _ _

1-------'CyC------r

10-56

210465-004

APPLICATION
. NOTE

AP-66

January 1980

©INTElCORPORATICN.19ao

Order Number: 231324-001

10-57

Using the 8292
GPIB Controller

Contents
INTRODUCTION
GPIB/IEEE 488 OVERVIEW
HARDWARE ASPECTS OF THE SYSTEM

829.1 Talker/Listener
8292 Controller
8293 Bus Transceivers
ZT7488/18 GPIB Controller
8292 CONJMAND DESCRIPTION
SOFTWARE DRIVER OUTLINE

Initialization
Talker/Listener
Send Data
Receive Data
Transfer Data
Controller
Trigger
Device Clear
Serial Poll
Parallel Poll
Pass· Control
Receive Control
Service Request
System Controller
Remote
Local
Interface Clear/Abort
INTERRUPT AND DMA CONSIDERATIONS
APPLICATION EXAMPLE
CONCLUSION

APPENDIX A
Source Listings
APPENDIX B

Test Cases for the Software Drivers
APPENDIX C

Remote Message Coding

10-58

231324-001

APPLICATIONS
Based on this experience, Hewlett-Packard began to
define a new interconnection scheme. They went
further than that, however, for they wanted to
specify the typical communication protocol for
systems of instruments. So in 1972, HewlettPackard came out with the first version of the bus
which since has been modified and standardized by a
committee of several manufacturers, coordinated
through the IEEE, to perfect what is now known as
the IEEE 488 Interface Bus (also known as the HPIB, the GPIB and the lEe bus). While this bus
specification may not be perfect, it is a good
compromise of the various desires and goals of
instrumentation and computer peripheral manufacturers to produce a common interconnection
mechanism. It fits most instrumentation systems in
use today and also fits very well the microcomputer
I/O bus requirements. The basic design objectives
for the GPIB were to:

INTRODUCTION

The Intel® 8292 is a pre programmed UPI'"-4IA that
implements the Controller function of the IEEE Std
488-1978 (GPIB, HP-IB, IEC Bus, etc.). In order to
function the 8292 must be used with the 8291
Talker / Listener and suitable interface and transceiver logic such as a pair of Intel 8293s. In this
configuration the system has the potential to be a
complete GPIB Controller when driven by the
appropriate software. It has the following capabilities: System Controller, send IFC and Take
Charge, send REN, Respond to SRQ, send Interface
messages, Receive Control, Pass Control, Parallel
Poll and Take Control Synchronously.
This application note will explain the 8292 only in
the system context of an 8292, 8291, two 8293s and
the driver software. If the reader wishes to learn
more about the UPI-4IA aspects of the 8292, Intel's
Application Note AP-41 describes the hardware
features and programming characteristics of the
device. Additional information on the 8291 may be
obtained in the data sheet. The 8293 is detailed in its
data sheet. Both chips will be covered here in the
details that relate to the G PIB controller.
The next section of this application note presents an
overview of the GPIB in a tutorial, but comprehensive nature. The knowledgable reader may wish
to skip this section; however, certain basic semantic
concepts introduced there will be used throughout
this note.

1. Specify a system that is easy to use, but has all of
the terminology and the definitions related to
that system precisely spelled out so that everyone uses the same language when discussing the
GPIB.
2. Define all of the mechanical, electrical, and functional interface requirements of a system, yet not
define any of the device aspects (they are left up
to the instrument designer).
3. Permit a wide range of capabilities of instruments
and computer peripherals to use a system simultaneously and not degrade each other's performance.
4. Allow different manufacturers' equipment to be
connected together and work together on the
same bus.
5. Define a system that is good for limited distance interconnections.
6. Define a system with minimum restrictions on
performance of the devices.
7. Define a bus that allows asynchronous communication with a wide range of data rates.
8. Define a low cost system that does not require
extensive and elaborate interface logic for the
low cost instruments, yet provides higher capac
bility for the higher cost instruments if desired.
9. Allow systems to exist that do not need a central
controller; that is, communication directly from
one instrument to another is possible.

Additional sections cover the view of the 8292 from
the CPU's data bus, the interaction of the 3 chip
types (8291, 8292, 8293), the 8292's software
protocol and the system level hardware/software
protocol. A brief description of interrupts and
DMA will be followed by an application example.
Appendix A contains the source code for the system
driver software.

GPID/IEEE 488 OVERVIEW
DESIGN OBJECTIVES
What is the IEEE 488 (GPIB)?

The experience of designing systems for a variety of
applications in the early 1970's caused HewlettPackard to define a standard intercommunication
mechanism which would allow them to easily assemble
instrumentation systems of varying degrees of complexity. In a typical situation each instrument designer designed his/ her own interface from scratch.
Each one was inconsistent in terms of electrical
levels, pin-outs on a connector, and types of connectors. Every time they built a system they had to
invent new cables and new documentation just to
specify the cabling and interconnection procedures.

Although the GPIB was originally designed for
instrumentation systems, it became obvious that
most of these systems would be controlled by a
calculator or computer. With this in mind several
modifications were made to the original proposal
before its final adoption as an international standard. Figure I lists the salient characteristics of the
10-59

231324-001

APPLICATIONS
GPIB as both an instrumentation bus and .as a
computer I/O bus.

Data Rate
1M bytes/s, max
250k bytes/s, typ
Multiple Devices
. 15 devices; max (electrical limit)
a devices, typ (interrupt flexibility)
Bus Length
20 m, max
. 2 m/device, typ
Byte Oriented
a·bit commands
a·bit data
. Block Multiplexed
Optimum strategy on GPIB due to
setup overhead for commands
Interrupt Driven
Serial polJ (slower devices)
Parallel poll (faster devices)
Direct Memory Access
One DMA facility at controller
serves all devices on bus
Asynchronous
One talker
}
.
Multiple listeners
3·wlre handshake
I/O to I/O Transfers
Talker and listeners need not
include microcomputer/controller
Figure 1. Major Characteristics of
GPIB as Microcomputer 1/0 Bus

The bus can be best understood by examining each
of these characteristics from the viewpoint of a
general microcomputer I/O bus.
Data Rate - Most microcomputer systems .utilize
peripherals of differing operational rates, such as
floppy discs.at 31k or 62k bytes/s (single or double
density), tape cassettes at 5k to 10k bytes/s, and
cartridge tapes at 40k to 80k bytes/so In general, the
only devices that need high speed I/O are 0.5" (1.3cm) magnetic tapes imd hard discs, operational at
30k to 781k bytes/s, respectively. Certainly, the
250k-bytes/s data rate that can be'easily achieved by
the IEEE 488 bus is sufficient for microcomputers
and their peripherals, and is more than needed for
.typical analog instruments that take only a few readings per second. The I M-byte/ s maximum data rate
is not easily achieved on the GPIB and requires
special attention to considerations beyond the scope
of this note. Although not required, data buffering
in each device will improve the overall bus per-

formance and allow utilization of more of the bus
bandwidth.
Multiple Devices - Many microcomputer systems
used as computers (not as components) service from
three to seven peripherals. With the GPIB, up to 8
devices can be handled easily by I controller; with
some slowdown in interrupt handling, up to 15
devices can work together. The limit of 8 is imposed
by the number of unique parallel poll responses
available; the limit of 15 is set by the electrical drive
characteristics of the bus. Logically, the IEEE 488
Standard is capable ofaccommodating more device
addresses (31 primary, each potentially with 31
secondaries).
.

Bus Length - Physically, the majority of microcomputer systems fit easily on a desk top or in a
standard 19" (48-cm) rack, eliminating the need for
extra long cables. TheGPIB is designed typically to
have 2 m of length per device, which accommodates
most systems. A line printer might require greater
cable lengths, but this can be handled at. the lower
speeds involved by using extra dummy terminations.
Byte Oriented - The 8-bit byte is ~Imost universal
in I/O applications; even 16-bit and 32-bit computers use byte transfers for moSt peripherals. The 8bit byte matches the ASCII code for characters and
is an integral submultiple' of most computer word
sizes. The GPIB has an 8-bit wide data path that may
be used to transfer ASCII or binary data, as well as
the necessary status and control bytes.
Block Multiplexed - Many peripherals are block
oriented or are used in a block mode. Bytes are
transferred in a fixed or variable length group; then
there is a wait before another group is sent to that
device, e.g., one sector of a floppy disc, one line on a
printer or tape punch, etc. The GPIB is, by, nature, a
block multiplexed bus due to the overhead involved
in addressing various devices to talk and listen. This
overhead is less bothersome if it only occurs once for
a large number of data bytes (once per block). This
mode of operation matches the needs of microcomputers and most of their peripherals~- Because of
block multiplexing, the bus works best with buffered
memory devices.
Interrupt Driven - Many types ofinterrupt systems
exist, ranging from complex, fast, vectored/priority
networks to simple polling schemes. The main
tradeoff is usually cost versus speed of response. The
GPIB has two interrupt protocols to help span the
range of applications. The first is a single service
request (SRQ) line that may be asserted by all
interrupting d,evices.· The controller then polls all
devices to find· out which wants service. The polling
mechanism is well defined and can be easily
231324-001

10-60

APPLICATIONS
automated. For higher performance, the parallel
poll capability in the IEEE 488 allows up to eight
devices to be polled at once - each device is
assigned to one bit of the data bus. This mechanism
provides fast recognition of an interrupting device.
A drawback is the frequent need for the controller to
explicitly conduct a p'arallel poll, since there is no
equivalent of the SRQ line for this mode.
Direct Memory Access (DMA) - In many applications, no imediate processing of 1/ 0 data on a byteby-byte basis is needed or wanted. In fact,
programmed transfers slow down the data transfer
rate unnecessarily in these cases, and higher speed
can be obtained using DMA. With the GPIB, one
DMA facility at the controller serves all devices.
There is no need to incorporate complex logic in
each device.

3-wire handshake that allows data transfers from
one talker to many listeners.

I/O To I/O Transfers - In practice, I/O to I/O
transfers are seldom done due to the need for
processing data and changing formats or due to
mismatched data rates. However, the GPIB can
support this mode of operation where the microcomputer is neither the talker nor one of the
listeners.
GPIB SIGNAL LINES
Data Bus
The lines DWI through Di08 are used to transfer
addresses, control information and data. The
formats for addresses and control bytes are defined
by the IEEE 488 standard (see Appendix C). Data
formats are undefined and may be ASCII (with or
without parity) or binary. DIOI is the Least Significant Bit (note that this will correspond to bit 0
on most computers).

Asynchronous Transfers - An asynchronous bus is
desirable so that each device can transfer at its own
rate. However, there is still a strong motivation to
buffer the data at each device when used in large
systems in order to speed up the aggregate data rate
on the bus by allowing each device to transfer at top
speed. The GPIB is asynchronous and uses a special

1111 I III

DEVICE A
ABLE TO

TALK, LISTEN,
AND
CONTROL

Management Bus
A TN -:- Attention

This signal is asserted by the
Controller to indicate that it is placing an address or
control byte on the Data Bus. ATN is de-asserted to
allow the assigned Talker to place status or data on
the Data Bus. The Controller regains control by reasserting ATN; this is normally done synchronously
with the handshake to avoid confusion between
control and data bytes.

f

==

DATA BUS

EOI - End or Identify This signal has two uses as
its name implies. A talker may assert EO! simultaneously with the last byte of data to indicate end of
data. The. Controller may assert EO! along with
ATN to initiate a Parallel Poll. Although many
devices do not use Parallel Poll, all devices should
use EOI to end transfers (many currently available
ones do not).

(e.g. computer)

DEVICE B
ABLE TO
TALK AND
LISTEN

~

(e.g. digital
mullimeter)

DATA BYTe

TRANSFER
CONTROL.

OEVICE C

ONLY ABLE
TO liSTEN
(e.g. signal

~

generalor'

SRQ - Service Request
This line is like an
interrupt: it may be asserted by any device to request
the Controller to take some action. The Controller
must determine which device is asserting SRQ by
conducting a Serial Poll at its earliest .convenience.
The device deasserts SRQ when polled.

GENERAL

INTERFACE
MANAGEMENT
DEVICE 0
ONLY ABLE
TO TALK

1==

(e.g. counter)

I Fe - Interface Clear This signal is asserted only
by the System Controller in order to initialize all
device interfaces to a known state. After deasserting
IFC, the System Controller is the active controller of
the system.

~}DI01..·(1DATA
NPUT/OUTPUT)
I...----

DAV (DATA VALID)
NRFD (NO T READY FOR DATA)
NDAC (NO T DATA ACCEPTED)

IFC (INTER FACE CLEAR)
ATH (ATTE NTION)
SRQ (SERVICE REQUEST)
AEN (REM OTe ENABLE)
eOI (END- OR-IDENTIFY)

REN - Remote Enable This signal is asserted
only by the System Controller. Its assertion does not
place devices into Remote Control mode; REN only
enables a device to· go remote when addressed to
listen. When in Remote, a device should ignore its
front panel controls.

Figure 2. Interface Capabilities and Bus Structure

231324-001

10-61

APPLICATIONS
bytes, The latter is called an extended Talker.
4. L - Listener (section 2.6) This function allows
a device to receive data when addressed to listen.
There can be extended Listeners (analogous to
extended Talkers above).
5. SR - Service Request (section 2.7) This function allows a device to request service (interrupt) the Controller. The SRQ line may be
asserted asynchronously.
6.' RL - Remote Local (section 2.8) This function
allows a device to be operated in two modes:
Remote via the GPIB or Local via the manual
front panel controls.
7. PP - Parallel Poll (section 2.9) This function
allows a devicetopresent one bit of status to the
Controller-in-charge. The device need not be
addressed to talk and no handshake is required.
8. DC - Device Clear (section 2.10) This function
allows a device to be cleared (initialized) by the
Controller. Note that there is a difference
between DC (device clear) and,the IFC line
(interface clear).
9. D T - Device Trigger (section 2.11) This function allows a device to have its basic operation
started either individually or as part of a group.
This capability is often used to synchronize
several instr:uments.
10. C - Controller (section 2.12) This function
allows a device to send addresses,. as well as
universal and addressed commands to other
devices. There may be more than one controller
on a system, but only one may be the controllerin-charge at anyone time.

Transfer Bus
NRFD - Not Ready For Data This handshake
line, is asserted by a listener to indicate it.is not yet
ready for the next data or control byte. Note that the
Controller,will not see NRFD deasserted (Le., ready
for data) until all devices have deasserted NRFD.
NDAC - Not Data Accepted This handshake
line is asserted by a Listener to indicate it has not yet
accepted the data or control byte on the DIO lines.
Note that the Controller will not see NDAC
deasserted (Le., data accepted) until all devices have
deasserted NDAC.
DA V - Data Valid
This handshake line is
asserted by the Talker to indicate that a data or
control byte has been placed on the DIO lines and
has had the minimum specified settling time.

-f...._ _ _......~---(...____...~-

DID

HDAV

LNRFD:

=---1I....._____...

n L_ __

.....I(lL___.....;._1l

NDAC : - _ _ _

Figure 3.'GPIB Handshake Sequence

GPIB INTERFACE FUNCTIONS

. At power-on time the controller that is hand wired to
be the System Controller becomes the active
controller-in-charge. The System Controller has
several unique capabilities including the ability to
send Interface Clear (IFC - clears all device
interfaces and returns control to the System
Controller) and to send Remote Enable (REN - ,
allows devices to respond to bus data once they are
addressed to listen). The System Controller may
optionally Pass Control to another controller, if the
system software has the capability to do so.

There are ten (10) interface functions specified by
the IEEE 488 standard. Not all devices will have all
functions and some may only have partial subsets.
The ten functions are summarized below with the
relevant section number from 'the IEEE document
given at the beginning of each paragraph. For
further information please see the IEEE standard.
1. SH - Source Handshake (section 2.3) This
function provides a device with the ability to
properly transfer data from a Talker to one or
more Listeners using the three handshake lines.
2. AH - Acceptor Handshake (section 2.4) This
function provides a device with the ability to
properly receive data from the Talker using the
three handshake lines. The AH function may
also delay the beginning (NRFD) or end
(NDAC) of any transfer.
3. T - Talker (section 2.5) This function allows a
device to s,end status and data bytes when addressed to talk. An address consists of one
(Primary) or two (Primary and Secondary)

GPIB CONNECTOR
The GPIB connector is a standard 24-pin industrial
connector such as Cinch or Amphenol series 57
Micro-Ribbon. The IEEE standard specifies this
connector, as well as the signal connections and the
mounting hardware.
'
The cable has 16 signal lines and 8 ground lines. The
maximum length is 20 meters with no more than two
meters per device.
10-62

231324-001

APPLICATIONS
DA TA - Transfer a block of data from device A to
devices B, C ...
I. Device A Primary (Talk) Address
Device A Secondary Address (if any)
2. Universal Unlisten
3. Device B Primary (Listen) Address
Device B Secondary Address (if any)
Device C Primary (Listen) Address
etc.
4. First Data Byte
Second Data Byte

@J
i
t

GNO

REN
OIOS

0107
0106
0105

SHIELD
ATN
SRO
IFC
NOAC
NRFO
DAY
EOI

0104
0103
0102
0101

Last Data Byte (EOI)
5. Null

TRIGR - Trigger devices A, B, ... to take action
I. Universal Unlisten

2. Device A Primary (Listen) Address
Device A Secondary Address (if any)
Device B Primary (Listen) Address
Device B Secondary Address (if any)
etc.
3. Group Execute Trigger
4. Null

Figure 4. GPIB Connector

GPIB SIGNAL LEVELS
The GPIB signals are all TTL compatible, low true
signals. A signal is asserted (true) when its electrical
voltage is less than 0.5 volts and is deasserted (false)
when it is greater than 2.4 volts, Be careful not to
become confused with the two handshake signals,
NRFD and NDAC which are also low true (i.e.
> 0.5 volts implies the device is Not Ready For
Data).
The Intel 8293 GPIB transceiver chips ensure that all
relevant bus driver/receiver specifications are met.
Detailed bus electrical specifications may be found
in Section 3 of the IEEE Std 488-1978. The Standard
is the ultimate reference for all GPIB questions.

PSCTL - Pass control to device A
I. Device A Primary (Talk) Address
Device A Secondary Address (if any)
2. Take Control
3. Null
CLEA R - Clear all devices
I. Device Clear
2. Null
REMAL - Remote Enable
I. Assert REN continuously
GOREM - Put devices A, B, ... into Remote
I. Assert REN continuously
2. Device A Primary (Listen) Address
Device A Secondary Address (if any)
Device B Primary (Listen) Address
Device B Secondary Address (if any)
etc.
3. Null

GPIB MESSAGE PROTOCOLS
The GPIB is a very flexible communications
medium and as such has many possible variations of
protocols. To bring some order to the situation, this
section will discuss a protocol similar to the one used
by Ziatech's ZT80 GPIB controller for Intel's
MULTIBUSTM computers. The ZT80 is a complete
high-level interface processor that executes a set of
high level instructions that map directly into GPIB
actions. The sequences of commands, addresses and
data for these instructions provide a good example
of how to use the GPIB (additional information is
available in the ZT80 Instruction Manual). The
'null' at the ena of each instruction is for cosmetic
use to remove previous information from the DIO
lines.

GOLOC - Put devices A, B, ... into Local
I. Device A Primary (Listen) Address
Device A Secondary Address (if any)
Device B Primary (Listen) Address
Device B Secondary Address (if any)
etc.
2. Go To Local
3. Null
LOCAL - Reset all devices to Local
I. Stop asserting REN
10-63

231324-001

APPLICATIONS
LLKAL - Prevent all devices from returning to
Local
I. Local Lock Out
2. Null
SPOLL - Conduct a serial poll of devices A, B, ...
I. Serial Poll Enable
2. Universal Unlisten
3. ZT 80 Primary (Listen) Address
ZT 80 Secondary Address
4. Device Primary (Talk) Address
Device Secondary Address (if any)
5. Status byte from device
6. Go to Step 4 until all devices on list have been polled
7. Serial Poll Disable
8. Null
PPUAL - Unconfigure and disable Parallel Poll
response from all devices
I. Parallel Poll Unconfigure
2. Null
ENA PP - Enable Parallel Poll response in devices

-Service Request, Parallel Poll, Device Clear, Device Trigger, Remote/Local functions
-Programmable data transfer rate
-Maskable interrupts
-On-chip primary and secondary address recognition
-1-8 MHz clock range
-16 registers (8 read, 8 write) for CPU interface
-DMA handshake provision
- Trigger output pin
-On-chip EOS (End of Sequence) recognition
The pinouts and block diagram are shown in Fig. 5.
One of eight read registers is for data transfer to the
CPU; the other seven allow the microprocessor to
monitor the GPIB states and various bus and device
conditions. One of the eight write registers is for data
transfer from the CPU; the other seven control
various features of the 8291.
The 8291 interface functions will be software
configured in this application exampie to the
following subsets for use with the 8292 as a
controller that does not pass control. The 8291 is
used only to provide the handshake logic and to send
and receive data bytes. It is not acting as a normal
device in this mode, as it never sees A TN asserted.
SH I
Source Handshake
Acceptor Handshake
AH I
T3
Basic Talk-only
LI
Basic Listen-only
SRO
No Service Requests
RLO
No Remote/Local
PPO
No Parallel Poll response
DCO
No Device Clear
DTO
No Device Trigger

A, B, ...
I. Universal Unlisten

2. Device Primary (Listen) Address
Device Secondary Address (if any)
3. Parallel Poll Configure
4. Parallel Poll Enable
5. Go to Step 2 until all devices on list have been
configured.
6. Null
DISPP - Disable Parallel Poll response from devices A, B, ...
I. Universal Unlisten
2. Device A Primary (Listen) Address
Device A Secondary Address (if any)
Device B Primary (Listen) Address
Device B Secondary Address (if any)
etc.
3. Disable Parallel Poll
4. Null

If control is passed to another controller, the 8291
must be reconfigured to act asa talker / listener with
the following subsets:
Source Handshake
SH I
AH I
Acceptor Handshake
T5
Basic Talker and Serial Poll
L3
Basic Listener
SR I
Service Requests
RLI
Remote/Local with Lockout'
PP2
Preconfigured Parallel Poll
DC I
Device Clear
DTi .
Device Trigger
CO
Not a Controller
Most applications do not pass control and the controller is always the system controller (see 8292
commands below),
.

This Ap Note will detail how to implement a useful
subset of these controller instructions.

HARDWARE ASPECTS OF THE SYSTEM
8291 GPIB TALKER/LISTENER
The 8291 is a custom designed chip that implements
many of the non-controller GPIB functions. It provides hooks so the user's software can implement
additional features to complete the set. This chip is
discussed in detail in its data sheet. The major features are summarized here:
-Designed to interface microprocessors to the GPIB
-Complete Source and Acceptor Handshake
-Complete Talker and Listener Functions with extended addressing

8292 GPIB CONTROLLER
The 8292 is a preprogrammed Intel® 8041A that
provides the additional functions necessary to
10-64

APPLICATIONS
PIN CONFIGURATION

RESET

BLOCK DIAGRAM

4

TRIG

DREQ

GPIB CONTROL

TO NON· INVERTING

BUS TRANSCEIVERS

I

TIA CONTROL

DO

07

Vss

_-_...

......

Figure 5. 8291 Pin Configuration and Block Diagram

Interrupt Mask, Error Mask, Event Counter or
Time Out.

implement a GPIB controller when used with an
8291 Talker/Listener. The 8041A is documented in
both a user's manual and in AP-41. The following
description will serve only as an outline to guide the
later discussion.
The 8292 acts as an intelligent slave processor to the
main system CPU. It contains a processor, memory,
I/O and is programmed to perform a variety of tasks
associated with GPIB controller operation. The onchip RAM is used to store information about the
state of the Controller function, as w¥ll as a variety
of local variables, the stack and certain user status
information. The timer/counter may be optionally
used for several time-out functions or for counting
data bytes transferred. The I/O ports provide the
G PIB control signals, as well as the ancillary lines
necessary to make the 8291, 2, 3 work together.
The 8292 is closely coupled to the main CPU
through three on-chip registers that may be
independently accessed by both the master and the
8292 (UPI-4IA). Figure 6 shows this Register
Interface. Also refer to Figure 12.
The status register is used to pass Interrupt Status
information to the master CPU (AO = I on a read).
The DBBOUT register is used to pass one of five
other status words to the master based on the last
command written into DBBIN. DBBOUT is accessed
when AO =0 on a Read. The five status words are
Error Flag, Controller Status, GPIB Status, Event
Counter Status or Time Out Status.
DBBIN receives either commands (AO = I on a
Write) or command related data (AO = 0 on a write)
from the master. These command related data are

CPU

CS

AO

RO

Wi!

0
0
0
0

0

0
0

1
1

1

1
1

X

X

0
0
X

1

1
0

REGISTER
READ DBBOUT
READ STATUS
WRITE D881N (DATA)
WRITE D881N (COMMAND)
NO ACTION

Figure 6. UPI-41A Registers

8293 GPIB TRANSCEIVERS
The 8293 is a multi-use HMOS chip that implements
the IEEE 488 bus transceivers and contains the
additional logic required to make the 8291 and 8292
work together. The two option strapping pins are
used to internally configure the chip to perform the
specialized gating required for use with 8291 as a
device or with 8291/92 as a controller.
In this application example the two configurations
used are shown in Fig. 7a and 7b. The drivers are set
to open collector or three state mode as required and
the special logic is enabled as required in the two
modes.
10-65

231324-001

APPLICATIONS
8291/2/3 CHIP SET
Figure 8 shows the four chips interconnected with
the special logic explicitly shown.
The 8291 acts only as the mechanism to put
commands and addresses on the bus while the 8292
is asserting ATN. The 8291 is tricked into believing
that the ATN line is not asserted by the A TN2
output of the ATN transceiver and is placed in Talkonly mode by the CPU. The 8291 then acts as though
it is sending data, when in reality it is sending
addresses and / or commands. When the 8292
deasserts ATN, the CPU software must place the
8291 in Talk-only, Listen-only or Idle based on the
implicit knowledge of how the controller is going to
participate in the data transfer. In other words, the
8291 does not respond directly to addresses or
commands that it sends on the bus on behalf of the
Controller. The user software, through the use of
Listen-only or Talk-only, makes the 8291 behave as
though it were addressed.
Although it is not a common occurrence, the GPIB
specification allows the Controller to set up a data
transfer between two devices and not directly
participate in the exchange. The controller must
know when to go active again and regain control.
The chip set accomplishes this through use of the
"Continuous Acceptor Handshake cycling mode"
and the ability to detect EOI or EOS at the end of the
transfer. See XFER in the Software Driver Outline
below.

Figure 7a. 8293 Mode 2

If the 8292 is not the System Controller as
determined by the signal on its SYC pin, then it must
be able to respond to an IFC within 100 usec. This is
accomplished by the cross-c()Upled NORs in Fig. 7a
which deassert the 8293's internal version of CIC
(Not Controller~in-Charge). This condition is latched
until the 8292's firmware has received the IFCL
(interface clear received latch) signal by testing the
IFCL input. The firmware then sets its signals to reflect the inactive condition and clears the 8293's latch.

In order for the 8292 to conduct a Parallel Poll the
8291 must be able to capture the PP response on the
DIO lines. The only way to do this is to fool the 8291
by putting it into Listen-only mode and generating a
DA V condition. However, the bus spec does not
allow a DA V during Parallel Poll, so the back-toback 3-state buffers (see Fig. 7b) in the'8293 isolate
the bus and allow the 8292 to generate a local DA V
for this purpos,e. Note that the 8291 cannot assert'a
Parallel Poll response. When the 8292 is not the
controller-in-charge the 8291 may respond to PPs
and the 8293 guarantees that the DIO drivers are in
"open collector" mode through the OR gate (Fig.
7b).

Figure 7b. 8293 Mode 3

10-66

231324-001

APPLICATIONS
+5

MODE 3
ATNO
IFCL

ms;v

OAV

-~

'f

-t>--K
~~

T/R1

T/R1

rrnW-iI

DiOl

REN

j)j()2

EOi

0103

T/R2

Di04

1FC

0105

~-

NRFO

0106

NOAC

0107

tH
tH

V

EOI

01

01

~-

01 03*

~

0108

OAV*

tR~

tR-

8291

A'fN

U

OPTA

OPTB

01

01 05*

I-- 01 06*
I-- 01 07*
I-- 01 08*

A'i'N

SRQ

MODE 2

-

NOAC

~

OAV

IiiRFD

1

T!R1
IFC

IFC

V

SYC

SYC
REN

I

REN

8292

SRQ

SiW

A'fjijj

ATNI
ATN

EOi2

EOl2
ATNO

ATNO
COUNT

EOI

SIR

,

IFCL

CLTH
CIC

CLTH
CIC

TIC

HSIR

OPTA
OPTB

NOAC*
NRFO*
IFC*
REN*

SRQ*

Tiel--- ATN*

~~T

'pH=
SIR

T/R2

IFCL

TIC

~

t

Ii

SIR

]n7

EOI*

TIC

~

Figure B. Talker/Listener/Controller

10-67

231324-001

APPLICATIONS
ZT7488/18 GPIB CONTROLLER
Ziatech'sGPIB Controller, the ZT7488/ 18 will be.
used as the controller hardware in this Application
Note. The controller consists of an 8291, 8292, an 8
bit input port and TIL logic equivalent to that
shown in Figure 8. Figure 9 shows the card's block
diagram. The ZT7488/ 18 plugs into the STD bus,.a
56 pin 8 bit microprocessor oriented bus. An 8085
CPU card is also available on the STD bus and will
be used to execute the driver software.
The 8291 uses I/O Ports 60H to 67H and the 8292
uses I/O Ports 68H and 69H. The five interrupt lines
are connected to a three-state buffer at. 1/ 0 Port

6FH to facilitate polling operation. This is required
for the TCI, as it cannot be read internally in .the
8292. The other three 8292 lines (SPI, IBF, OBF)
and the 8291's INT line are also connected to
minimize the number of I/O reads necessary to poll
the devices.
NDAC is connected to COUNT on the 8292 to allow
byte counting on data transfers. The example driver
software will not use this feature, as the software is
simpler and faster if an· internal 8085 register is used
for counting in software.

.....

ADDRPS

...

CLOCK·

wr

IO!XP"
IORO'

....,
.....

ADDRns

ADDRESS

Figure 9. ZT7488/18 GPIB Controller

READ REGISTERS

PORT #

lool~I~I~I~lml~l~

~

WRITE REGISTERS

I=I-I~I~I~I~I~I~I
DATA OUT

DATA IN

I CPT I APT I GET I END I DEC I ERR I BO I B'

.'H I CPT IAPT I GET IEND I DEC IERR I BD IB'
INTERRUPT MASK 1

INTERRUPT STATUS 1

I 'NT I SPAS I LLO I REM I SPAScl LLDC I REMCI ADSC I

62H

I. I. I DMADIOMA'I SPAscl "DC I REMCI ADSC I

63H

I 58 I", I 56 I55 I 54 I 53 I 52 I 51

INTERRUPT MASK 2

INTERRUPT STATUS 2

I 58 I SRDSI 56 I S. I 54 I 53 I 52 I5' I

SERIAL POLL MODE

SERIAL POLL STATUS

I ". I'D. I ED' I LPAS I TPAS ILA I TA I MJMNI

64H

I TO I LO I 0 I. I. I.

I ADM,I ADM·I

ADDRESS MODE

ADDRESS STATUS

AUX MODE

COMMAND PASS THROUGH'

I x I DTO I OLD I AD'·3 AD··.I AD3·'1 A02.01 AD'·3

86H

I ARS I DT I DL I AD5 I AD' IAD' I AD2: I AD' I

67H

I EC' I EC6 I EC' I EC' I EC' IEC2 I EC' I ECO

ADDRESS 011

ADDRESS 0

I x lOT' I DLI I ADS·,I A04·,I.D3·,1 AD2·,I·D,·,1
ADDRESS 1

EOS

Figure 10. 8291 Registers

10-68

231324-001

APPLICATIONS

RD

1

r-:~

__________________________________________________--,

n ::A'~O~~--~M~E~M~W----+-------------+---~----------------_+-----------+-,
O.IH-H-.....::mw:.::....----+-~----------+t--------------------_+.....,
.3

WR

011~____~VHm~~

Aa...
1lm
~~O.!~____~~____~____________~--------------------,
31T

.~
T_

IOII!.-----'

REaET-----I---+r++++-------......-+--+---IV

IN~.:
INn~=t====~~~=======E:t=l==~=======l~J_----------------L_l_1_----,

-

07·00

l

,1:1~i!I~~~~~~}~~~~~~~,B~~T

RaT RD W
Rb
INTI-----1
J. ..5J1..5"
,.----<'ICS AD

--,. 07·00

DROO - - - - OREO
DACK 0 >-----< DACK
HOLDHLDACLK-

I--

TCI

AEN

t-- HRO
h::- HLDA
1"'1:. ROY
CLK
I!!
z
..

'i U

8291

~ r-r--

r--

RS'
RSI
RSO

I ClK
1

CS

.

REN

IFC R O E G S R O
IFC
S
••9.
NDAC
COUNT
ATN
CIC
~
EOI
EOI.
DAY
DAY
ATNI
~:: ,Lt--< ATNO
IFCL
~~~: I-'r-HI-+H-I-+++-h
r;:: ~~~H CS AO-

J

I

1

1

CS

07·00 \r-

NRFD

••57-5

~ .14.

R';;""';

~:tl RD WR

~'14'
CS

'(

~~~~~~~82~~~~~~~
. nO
-0.
B2~3

AD
AI5·M=-________

~

MODE.

'1Ull
cqmo-t::a

Z-ZD

GPIB

0

C

.C .C

1
~

________________________________________________________________

~

Figure 11. DMAllnterrupt GPIB Controller Block Diagram

The application example will not use DMA or
interrupts; however, the Figure II block diagram
includes these features for completeness.
The 8257-5 DMA chip can be used to transfer daia
between the RAM and .the 8291 Talker/Listener.
This mode allows a faster data rate on the GPIB
and typically will depend on the 8291's EOS or EOI
detection to terminate the transfer. The 8'259-5
interrupt <;ontroller is used to vector the five possible
interrupts for rapid software handling of the various
conditions.

8292 COMMAND DESCRIPTION

of each register. Note the two letter mnemonics to Qe
used in later discussions. The CPU must not write
into the 8292 while IBF (Input Buffer Full) is a one,
as information will be lost.
DIRECT COMMANDS
Both the Interrupt Mask (1M) and the Error Mask
(EM) register may be directly written with the LSB
of the address bus (AO) a "0". The firmware uses the
MSB of the data written to differentiate between 1M
and EM.
Load Interrupt Mask
This command loads the Interrupt Mask with
D7-DO. Note that D7 must be a "I" and that
interrupts are enabled by a corresponding '~I" bit in
this register. IFC interrupt cannot be masked off;
however, when the 8292 is the System Controller,
sending an ABORT command will not cause an IFC
interrupt.

This section discusses each command in detail and
relates them to a particular GPIB activity. Recall
that although the 8041A has only two read registers
and one write register, through the magic of on-chip
firmware the 8292 appears to have six read registers
and five write registers. These are listed in Figure 12.
Please see the 8292 data sheet for detailed definitions
10-69

APPLICATIONS
WRITE TO 8292

PORT #

READ FROM 8292
INTERRUPT STATUS
I SYC I ERR I SRO I

EV

I .X

COMMAND FIELD

IIFCR I IBF

I

X

I USER I

X

I

X

I OP I

Do

ERROR FLAG'
X

B9H

OBF

C

I'

C

C

C

0

ISRO I

INTERRUPT MASK

I TOUT31 TOUT21TOUT1 I

SPI

BSH

TCI I SYC I OBFII

fBFl

1

Do
.CONTROLLER STATUS'
I

X

I CSBS I .CA

X

ERROR MASK

I SYCS I IFC

REN I SRO I

0

BSH

I USER I

GPIB (BUS) STATUS'
1 REN 1 OAV 1 EOI

1

X

1 SYC 1

0
1

0
1

0
1

I

IFC·I ANTI 1 SRO ,I

0

0

I

0

,ITOUT4ITOUT3ITOUT11

EVENT COUNTER'
BSH

0

.1

0

1

0

1

EVENT COUNTER STATUS'
0

0

1

0

1

01

0

1

0

1

0

1

TIMEOUT'

I

0

I

0
1

BSH

0

1

0

0
1

1

0

0
1

I

0

I

0

1

0
1

TIME OUT STATUS'
0

I

0

0
1

0
1

I

0

0
1

0
1

BSH

0
1

1

'Note: These registers are accessed by a special utility command,

,

Figure 12. 8292 Registers

counter is incremented on a high to low transition of
the COUNT (Tl) input. In this application example
NDAC is connected to count. The counter is an 8 bit
register and therefore can count up to 256 bytes
(writing 0 to the EC implies a count of 256). Iflonger
blocks are desired, the main CPU must handle the
interrupts every 256 counts and carefully observe the
timing constraints.
Because the counter has a frequency range from 0 to
'133 kHz when using a 6 MHz crystal, this feature
.may not be usable with all devices on the GPIB. The
8291 can easily transfer data at rates up to 250 kHz
,and even faster with. some tuning of the system.
There is also a 500 ns minimum high time
requirement for .COUNT which can potentially be
violated by the 82Q I in continuous acceptor
handshake mode (i.e., TNDDVI + TDVND2-C =
350 + 350 =700 max). When cable delays are taken
into consideration, this problem will probably never
occur.
When the 8292 has completed the command, IBF
will become a "0." and will cause an interrupt if
.
.
masked on.

Load Error Mask
This command loads the Error Mask with D7-DO.
Note that D7 must be a zero and that interrupts are
enabled by a corresponding "I" bit in this register.

UTILITY COMMANDS
These commands are used to read or write the 8292
registers that are not directly accessible. All utility
commands are written with AO =1, D7 = D6 =D5 = I,
D4 =O. D3- DO specify the particular command. For
writing into registers the, general sequence is:
1. wait for IBF =0 in Interrupt Status Register
2. write the appropriate command to the 8292,
3. write the desired register value to the 8292 with
AO = I with no other writes intervening,
4. wait for indication of completion from 8292
(lBF = 0).
For reading a register the general sequence is:
1. wait for IBF = 0 in Interrupt Status Register
'2. write the appropriate command to the 8292
3. wait for a TCI (Task Complete Interrupt)
4. Read the value of the accessed register from the
8292 with AO = O.
WEVC - Write to Event Counter
(Command =OE2H)
The byte written following this command will be
loaded into the' event counter register and event
counter status for byte counting. The internal

WTOUT - Write to Time Out Register
.
.(Command =OEIH)

The byte written following this. command, will be
used to determine the number of increments used for
the time out functions. BecausetheTegister is.8 bits,
the maximum time out is 256 time increments. This
10-70

231324-001

APPLICATIONS
is probably enough for most instruments on the
GPIB but is not enough for a manually stepped
operation using a GPIB logic analyzer like Ziatech's
ZT488. Also, the 488 Standard does not set a lower
limit, on how long a device may take to do each
action. Therefore, any use of a time out must be able
to be overridden (this is a good general design rule
for service and debugging considerations).
The time out function is implemented in the 8292's
firmware and will not be an accurate time. The
counter counts backwards to zero from its initial
value. The function may be enabled/ disabled by a
bit in the Error mask register. When the command is
complete IBF will be set to a "0" and will cause an
interrupt if masked on.

REVC - Read Event Counter Status
(Command =OE3H)
This command transfers the content of the Event
Counter to the DBBOUT register. The firmware
then sets TCI = .) and will cause an interrupt if
masked on. The CPU may then read the value from
the 8292 with AO =o.
RINM - Read Interrupt Mask Register
(Command =OE5H)
This command transfers the content of theInterrupt
Mask register to the DBBOUT register. The
firmware sets TCI =I and will cause an interrupt if
masked on. The CPU may then read the value.
RERM - Read Error Mask Register
(Command = OEAH)
This command transfers the content of the Error
Mask register to the DBBOUT register. The
firmware sets TCI =I and will cause an interrupt if
masked on. The CPU may then read the value.
RCST - Read Controller Status Register
(Command =OE6H)
This command transfers the content of the Con- '
troller Status register to the DBBOUT register. The
firmware sets TCI = I and will cause an interrupt if
masked on. The CPU may then read the value.
RTOUT - Read Time Out Status Register
(Command = OE9H)
This command transfers the content of the Time Out
Status register to the DBBOUT register. The
firmware sets TCI = I and will cause an interrupt if
masked on. The CPU may then read the value.
If this register is read while a time-out function is in
process, the value will be the time remaining before
time-out occurs. If it is read after a time-out, it will
fie zero. If it is read when no time-out is in process, it
will be the last value reached when the previous
timing occurred.
10-71

RBST - Read Bus Status Register
(Command = OE7H)
This command causes the firmware to read the
GPIB management lines, DA Vand the SYC pin and
place a copy in DB BOUT. TCI is set to "I" and will
cause an interrupt if masked on. The CPU may read
the value.
RERF - Read Error Flag Register
(Command =OE4H)
This command transfers the content of the Error
Flag register to the DBBOUT register. The firmware
sets TCI =I and will cause an interrupt if masked on.
The CPU may then read the value.
This register is also placed in DBBOUT by an lACK
command if ERR remains set. TCI is set to "I" in
this case also.
lACK - Interrupt Acknowledge
(Command =AI A2 A3 A4 I A5 I I)
This command is used to acknowledge any combinations of the five SPI interrupts (AI-A5): SYC,
ERR, SRQ, EV, and IFCR. Each bit AI-A5 is an
individual acnowledgement to the corresponding bit
in the Interrupt Status Register. The command
clears SPI but it will be set again if all ,of the pending
interrupts were not acknowledged.
IfA2 (ERR) is "I", the Error Flag register is placed
in DBBOUT and TCI is set. The CPU may then read
the Error Flag without issuing an RERF command.
OPERATION COMMANDS
The following diagram (Fig. 13) is an attempt to
show the interrelationships among the various 8292
.Operation Commands. It is not meant to replace the
complete controller state diagram in the IEEE
Standard.

RST - Reset (Command = OF2H)
This command has the same effect as an external
reset applied to the chip's pin #4. The 8292's actions
are:
I. All outputs go to their electrical high state. This
means that SPI, TCI, OBFI, IBFI, CLTH will be
TRUE and all pther GPIB sigrials will be FALSE.
2. The 8292's firmware will cause the above mentioned five signals to go FALSE after approximately 17.5 usec. (at 6 MHz).
3. These registers will be cleared: Interrupt Status,
Interrupt Mask, Error Mask, Time Out, Event
Counter, Error Flag.
4. If the 8292 is the System Controller (SYC is
TRUE), then IFC will be sent TRUE for approximately 100 usec and the Controller function will
end up in charge of the bus. If the 8292 is not the
231324-001

APPLICATIONS
and TCI TRUE. Otherwise it only sets the User
Error Flag.
SLOC - Set Interface to Local Mode
(Command =OF7H)
If the 8292 is the System Controller, it will set REN
FALSE and TCI TRUE .. Otherwise, it only sets the
User Error Flag.
EXPP - Execute Parallel Poll
(Command = OF5H)
If not Controller-in-Charge, the 8292 will treat this
as a NOP and does not set TCI. If it is the Controller-in-Charge then it sets IDY (EOI & ATN) TRUE
and generates a local DA V pulse (that never reaches
the GPIB because of gates in the 8293). If the 8291 is
configured as a listener, it will capture the Parallel
Poll Response byte in its data register. TCI is not
generated, the CPU must detect the BI (Byte In)
from the 8291. The 8292 will be ready to accept
another commandbefote the BI occurs; therefore
the 8291's BI serves as a task complete indication.

(RST + ABORT) • Bye

RST.

iVC

IDLE

,--------------,

I
~REM I
I
IABORT' sye - - - - + IL _ _ _ _
I
_ _ _ _ --.J
RST'!.....-

LOCAL

. SLoe

REMOTE

-!Y!!!!~ONTR.!!!:.L~

Figure 13. 8292 Command Flowchart

System Controller then it will end up in an Idle
state.
5. TCI will not be set.
RSTI - Reset Interrupts (Command = OF3)
This command clears all pending interrupts and
error flags. The 8292 will stop waiting for actions to
occur (e.g., waiting for ATN to go FALSE in a
TCNTR command or waiting for the proper
handshake state in a TCSY command). TCI will not
be set.
ABORT - Abort all operations and Clear Interface
(Command = OF9H)
If the 8292 is not the System Controller this
command acts like a NOP and flags a USER
ERROR in the Error Flag Register. No TCI will
occur.
If the 8292 is the System Controller then IFC is set
TRUE for approximately lOOf,Lsec and the 8292
becomes the Controller-in-Charge and asserts ATN.
TCI will be set, only if the 8292 was NOT the CIC.
STCNI - Start Counter Interrupts
(Command = OFEH)
Enables the EV Counter ·Interrupt. TCI will not be
set. Note that the counter must be enabled by a GSEC
command.
SPCNI - Stop Counter Interrupts
(Command .= OFOH)

GTSB - Go To Standby (Command = OF6H)
If the 8292 is not the Controller-in-Charge, it will
treat this command as a NOP and does not set TCI
TRUE. Otherwise, it goes to Controller Standby
State (CSBS), sets ATN FALSE and TCI TRUE.
This command is used as part of the Send, Receive,
Transfer· and Serial Poll System commands (see
next section) to allow the addressed talker to send
datal status.
If the data transfer does not start within the specified
Time-Out, the 8292 sets TOUT2 TRUE in the Error
Flag Register and sets SPI (if enabled). The
controller continues waiting for a new command.
The CPU must decide to wait longer or to regain
control and take corrective action.
GSEC - Go to Standby and Enable Counting
(Command =OF4H)
This command does the same things as GTSB but
also initializes the event counter to the value previously stored in the Event Counter Register (default
value is 256) and enables the counter. One may wire
the count input to NDAC to count bytes. When the
counter reaches zero, it sets EV (and SPI if enabled)
in Interrupt Status and will set EV every 256 bytes
thereafter. Note that there is a potential loss of
count information if the CPU does not respond to
the EV I SPI before another 256 bytes have been
transferred. TCI will be set at the end of the
command.

The 8292 will not generate an EV interrupt when the
counter reaches O. Note that . the counter will
continue counting. TCI will not be set.
SREM - Set Interface to Remote Control
(Command =OF8H)
If the 8292 is the System Controller, it will set REN

TCSY - Take Control Synchronously
(Command = OFDH)
If the 8292 is not in Standby, it treats this command
as a NOP and does not set TCI. Otherwise, it waits
10-72

231324·001

APPLICATIONS
should not be changed after Power-on in any system
- it adds unnecessary complexity to the CPU's
software.
In order to use polling with the 8292 one must enable
TCI but not connect the pin .to the CPU's interrupt
pin. TCI must be readable by some means. In this
application example it is connected to bit 1 port 6FH
on the ZT7488/ 18. In addition, the other three 8292
interruptiines and the 8291 interrupt are also on that
port (SPI-Bit 2, IBFI-Bit 4, OBFI-Bit 3, 8291 INTBit 0).

for the proper handshake state and sets ATN
TRUE. The 8292 will set TOUT3 if the handshake
never assumes the correct state and will remain in
this command until the handshake is proper or a
RSTI command is issued. If the 8292 successfully
takes control, it 'sets TCI TRUE.
This is the normal way to regain control at the end of
a Send, Receive, Transfer or Serial Poll System
Command. If TCSY is not successful, then the
controller must try TCAS (see warning below).
TCAS - Take Control Asynchronously
(Command = OFCH)

These drivers assume that only primary addresses
will be used on the GPIB. To use secondary
addresses, one must modify the test for valid
talk/listen addresses (range macro) to include
secondaries.

If the 8292 is not in Standby, it treats this command
as a NOP and does not set TCI. Otherwise, it
arbitrarily sets ATN TRUE and TCI TRUE. Note
that this action may cause devices on the bus to lose
a data byte orcause them to interpret a data byte asa
command byte. Both Actions can result in anomalous behavior. TCAS should be used only in
emergencies. If TCAS fails, then the System
Controller will have to issue an ABORT to clean
things up.

INIT

INITIALIZATION

Talker/Listener
SEND
RECV
XFER

GIDL - Go to Idle (Command ~ OFIH)
If the 8292 is not the Controller in Charge and
Active, then it treats this command as a NOP and
does not set TCI. Otherwise, it se~s ATN FALSE,
becomes Not Controller in Charge, and sets TCI
TRUE; This command is used as part of the Pass
Control System Command.
TCNTR - Take (Receive) Control
(Command = OFAH)
If the 8292 is not Idle, then it treats this command as
a NOP and does not set TCI. Otherwise, it waits for
the current Controller-in-Charge to set A TN
FALSE. If this does not occur within the specified
Time Out, the 8292 sets TOUT! iIi the Error Flag
Register and sets SPI (if enabled). it will not proceed
until ATN goes false or it receives an RSTI
command. Note that the Controller in Charge must
previously have sent this controller (via the 829l's
command pass through register) a Pass Control
message. When ATN goes FALSE, the 8292 sets
CIC, ATN and TCI TRUE and becomes Active.

SEND DATA
RECEIVE DAT)\.
TRANSFER DATA

Controlier
TRIG
DCLR
SPOL
PPEN
PPDS
PPUN
PPOL
PCTL
RCTL
SRQD

GROUP EXECUTE TRIGGER
DEVICE CLEAR
SERIAL POLL
PARALLEL POLL ENABLE
PARALLEL POLL DISABLE .
PARALLEL POLL UNCONFIGURE
PARALLEL POLL
PASS CONTROL
RECEIVE CONTROL
SERVICE REQUESTED

System Controlier
REME
LOCL
IFCL

REMOTE ENABLE
LOCAL
. ABORT/INTERFACE CLEAR

Figure 14. Software Driver.Routlnes

SOFTW ARE DRIVER OUTLINE

INITIALIZATION

The set of system commands dhicusst;d below is
shown in Figure 14. These commands are implemented in software routines executed by the main
CPU.

8292 - Comes up in Controller Active State when
SYC is TRUE. The only initialization needed is to
enable the TCI interrupt mask. This is done by
writing OAOH to Port 68H.
8291 - Disable both the major and minor addresses
because the 8291 will never see the 8292's commands/addresses (refer to earlier hardware discussion). This is done by writing 60H and OEOH to
Port 66H.

The following section assumes that the Controller is
the System Controller and will not Pass Control.
This is a valid assumption for 99+% of all
controllers. It also assumes that no DMA or
Interrupts will be used. SYC (System Control Input)
10-73

231324-001

APPLICATIONS
Set Address Mode to Talk-only by writing 80H to
Port 64H.

No interrupts will be enabled now. Each routine will
enable the ones it Tleeds for ease of polling operation.
The INT bit maybe read through Port 6FH. Clear
both interrupt mask registers.

Set internal counter to 3 MHz to match the clock
input coming from the 8085 by writing 23H to Port
65H. High speed mode for the handshakes will not
be used here even though the hardware uses threestate· drivers.

Release the chip's initialization state by writing 0 to
Port 65H.

!NIT:
.
Enable-8292
Enable TCI
Enable-829I
Disable major address
Disable minor address
ton
Clock frequency
All interrupts off
Immediate execute pan

;Set up Int. pins for Port 6FH
;Task complete must be on
;In controller usage, the 8291
;Is set to talk only and / or listen only
;Talk only is our rest state
;3 MHz in this ap note example
;Releases 8291 from init. state

TALKER/LISTENER ROUTINES
Send Data
SEND < listener list pointer>   
always sends Universal Unlisten. If it is desired to
send data to the listeners previously addressed, one
could add a check for a null list and not send UNL.
Count must be 255 or less due to an 8 bit register.
This routine also always uses an EOS character to
terminate the string output; this could easily be
eliminated and rely on the count. Items in brackets
( ) are optional and will not be included in the actual
code in Appendix A.
.

This system command sends data from the CPU to
one or more devices. The data is usually a string of
ASCII characters, but may be binary or other forms
as well. The data is device-specific.
My Talk Address (MT A) must be output to satisfy
the GPIB requirement of only one talker at a time
(any other talker will stop when MT A goes out). The
MT A is not needed as far as the 8291 is concerned _
it will be put into talk-only mode (ton).
This routine assumes a non-null listener list in that it
SEND:
Output-to-829l MTA, UNL
Put EOS into 8291
While 20H ::; listener ::; 3EH
output-to-829l listener
Increment listen list pointer
Output-to-8292 GTSB
Enable-829I
Output EO! on EOS s~nt
If count < > 0 then
While not (end or count =0)
(could check tout 2 here)
Output-to-8291 data
Increment data buffer pointer
Decrement count
Output-to-8292 TCSY
(If tout3 then take control async)
Enable 8291
No. output EOI on EOS sent
Return

;We will talk, nobody listen
;End of string compare character
;GPIB listen addresses are
;"space" thru " >" ASCII
;Address all listeners
;8292 stops asserting ATN, go to standby
;Send EO! along with EOS character
;Wait for EOS or end of count
;Optionally check for stuck bus-tout 2
;Output all data, One byte at a time
;8085 CREG will count for us
;8292 asserts ATN, take control sync.
;If unable to take .control sync.
;Restore 8291 to standard condition

10-74

231324-001

APPLICATIONS

CONTROLLER
8291,8292
LSTN
"I"

CTLR

TALK

"0"

TALK
"R"

DEVICE

~
I

LSTN
"+"

a· 40H\1 - - - 1

TALK
"K"

TALK
"N'

Figure 16. SEND 10 "1", "2", ">"; "ABCD"; EOS

Figure 15. Flowchart For Receive Ending Conditions

="0"

Receive Data
RECV < talker> < count> < EOS > < data buffer pointer>

facilitate analysis by a GPIB logic analyzer like the
Ziatech ZT488. Otherwise, the bus would appear to
have no listener even though the 8291 will be
listening.

This system command is used to input data from a
device. The data is typically a string of ASCII
characters.
This routine is the dual of SEND. It assumes a new
talker will be specified, a count of less than 257, and
an EOS character to terminate the input. EOI
received will also terminate the input. Figure 15
shows the flow chart for the RECV ending
conditions. My Listen Address (MLA) is sent to
keep the GPIB transactions totally regular to

Note that although the count may go to zero before
the transmission ends, the talker will probably be
left in a strange state and may have to be cleared by
the controller. The count ending of RECV is
therefore· used as an error condition in most
situations.
10-75

APPLICATIONS
RECV:

Put EOS into 8291

.

If 40H ~ talker ~ 5EH then

Output-to-8291 talker
Increment talker pointer
Output-to-8291 UNL, MLA
Enable-8291
Holdoff on end
End on EOS received
lon, reset ton
Immediate execute pon
Output-to-8292 GTSB
While not (end'or count =0 (or tout2))
Input-from-8291 data
Increment data buffer pointer
Decrement count
(If count = 0 then. error)
Output-to-8292 TCSY
(If Tout3 then take control async.)
Enable-8291
No holdoff on end
No end on EOS received
ton, reset Ion
Finish handshake
Immediate execute pon
Return error-indicator

;End of string compare character
;GPIB talk addresses are
;"@" thru "II" ASCII
;Do this for consistency's sake
;Everyone except us stop listening
;Stop when EOScharacter is
;Detected by 8291
;Listen only (no talk)
;8292 stops asserting ATN, go to standby
;wait for EOS or EOI or end of count
;optionally check for stuckbus-tout2
;input data, one byte at a time
;Use 8085 C register as counter
;Count should not occur before end
;8292 asserts ATN take control
;If unable to take control sync.
;Put 8291 back as needed for
;Controller activity and
;Clear holdoff due to end
;Complete hold off due to end, if any
;Needed to reset Ion

CONTROLLER
8291,8292

TALK

LSTN

"A" .

"I"

eTLR

DEVICE
TALK

LSTN
"1"

"0"

LSTN
"2"

DEVICE
LSTN

TALK
"K"

DEVICE
LSTN

">"

TALK
"1\"

Figure 17. RECV from "R"; EOS = ODH

Figure 18. XFER from" II" to "1", "2", "+"; EOS = ODH

10-76

231324-001

APPLICATIONS
Transfer Data
XFER  
This system command is used to transfer data from a
talker to one or more listeners where the controller
does not participate in the transfer of the ASCII
data. This is accomplished through the use of the
8291's continuous acceptor handshake mode while
in listen-only.

This routine assumes a device list that has the ASCII
talker address as the first byte and the string (one or
more) of ASCII listener addresses following. The
EOS character or an EOI will cause the controller to
take; control synchronously and thereby terminate
the transfer.

XFER:
Output-to-8291: Talker, UNL
While 20H :5 listen :5 3EH
Output-to-8291: Listener
Increment listen list pointer
Enable-8291
lon, no ton
Continuous AH mode
End on EOS received
Immediate execute PON
Put EOS into 8291
Output-to-8292: GTSB

;Send talk address and unlisten
;Send listen address
;Controller is pseudo listener
;Handshake but don't capture data
;Capture EOS as well as EOI
;Initialize the 8291
;Set up EOS character
;Go to standby
;8292 waits for EOS or EOI and the,n

Upon end (or tout2), then
Take control synchronously
Enable-829I
Finish handshake
Not continuous AH mode
Not END on EOS received
ton
Immediate execute pon
Return

;Regains control
;Go to Ready for Data

CONTROLLER
Group Execute Trigger
TRIG < Listener list>
This system command causes a group execute
trigger (GET) to be sent to all devices on the listener

TRIG:
Output-to-829l UNL
While 20H :5 listener :5 3EH
Output-to-829l Listener
Increment listen list pointer
Output-to-8291 GET
Return

list. The intended use is to synchronize a number of
instruments.

;Everybody stop listening
;Check for valid listen address
;Address each listener
;Terminate on any non-valid character
;Issue group execute trigger

10-77

APPLICATIONS

CONTROLLER

CONTROLLER
8291,8292

8291.8292
LSTN
"I"

CTLR

TALK

LITN
"I"

"A"

CTLR'
~~~

TALK

"A'"

TALK

TALK

"Q"

"Q"

TALK

TALK

"R"

"R"

DEVICE
LSTN

TALK
"K"

DEVICE

DEVICE
LITN

u>"

Figure 19. TRIG "1",

TALK
"K"

"+"

TALK
"1\"

"+"

LITN

TALK

">"

"A"

Flgure'20. DCLR "1", "2"

Device Clear
DCLR < Listener list>
This system command causes a device clear (SDC)
to be sent to all devices on the listener list. Note
that this is n,ot intended t.o clear the GPIB interface

of the device, but should clear, the device-specific
logic.

DCLR:
Output-to-829l UNL
While 20H :5 Listener :5 3EH
Output-to-829l listener
Increment listen list pointer
Output-to-8291 SDC
Return

;Everybody stop listening
;Check for valid listen address
;Address each listener
;Terminate on any n'on-valid character
;Selective device clear

Serial Poll
SPOL 
This system command sequentially addresses the
designated devices and receives one byte of status
from each. The bytes are stored in the buffer in the

same order as the 'devices appear on the talker list.
MLA is output for completeness.,

10-78

231324-001

APPLICATIONS
SPOL:
Output-to-8291 UNL, MLA, SPE

;Unlisten, we listen, serial poll enable
;Only one byte of serial poll
;Status wanted from each talker
;Check for valid transfer
;Address each device to talk
;One at a time

While 40H :5 talker :5 5EH
Output-to-8291 talker
Increment talker list pointer
Enable-8291
lon, reset ton
Immediate execute pon
Output-to-8292 GTSB
Wait for data i~ (81)
Output-to-8292 TCSY
Input-from-8291 data
Increment buffer pointer
Enable 8291
ton, reset Ion
Immediate execute pon
Output-to-8291 SPD
Return

;Listen only to get status
;This resets ton
;Go to standby
;Seria1 poll status byte into 8291
;Take control synchronously
;Actually get data from 8291

;Resets Ion
;Send serial poll disable after all devices polled

CONTROLLER

CONTROLLER

8281.8292

8291.8292
TALK

"A"

LSTN

TALK

"I"

"A"

DEVICE
LSTN

TALK

""1"

"0"

LSTN

. TALK

"2"

"R"

LSTN

TALK

"+"

"K"

LSTN

TALK
"1\"

">"

Figure 22. PPEN "2"; IP,P.P, = 01118

Figure 21. SPOL "Q", "R", "K"," fI"

Parallel Poll Enable
PPEN  
This system command configures one or more
devices to respond to Parallel Poll, assuming they
implement subset PPI. The configuration information is stored in a buffer with one byte per device
in the same order as devices appear on the listener
10-79

list. The configuration byte has the format
XXXXIP3P2Pl as defined by the IEEE Std. P3P2Pl
indicates the bit # to be used for a response and I
indicates the assertion value. See Sec. 2.9,3.3 of the
Std. for more details.
231324-001

APPLICATIONS
PPEN:
Output-to-8291 UNL
While 20H :5 Listener :5 3EH
Output-to-8291 listener
Output-to-8291 PPC, (PPE or data)
Increment listener list poihter
Increment buffer pointer .
Return

;Universal unlisten
;Check for valid listener
;Stop old listener, address new
;Send parallel.poll info
;Point to next listener
;One configuration byte per listener

Parallel Poll Disable
PPDS 
This system command disables one or more devices
from responding to a Parallel Poll by issuing a

PPDS:
Output-to-8291 UNL
While 20H :5 Listener :5 3EH
Output-to-8291 listener
Increment listener list pointer
Output-to-8291 PPC, PPD
Return

Parallel Poll Disable (PPD). It does not dec onfigure the devices.

;Universal Unlisten
;Check for valid listener
;Address listener
;Disable PP on all listeners

CONTROLLER

CONTROLLER

8291,9292

8291,8292
LSTN

"'"

TALK
"A"

DEVICE

I>.
LSTN
"1"

TALK
"Q"

DEVICE
LSTN
"2"

TALK
"Q"

DEVICE

"LSTN
"2"

TALK
"R"

DEVICE

I>.

v

TALK
"K"

TALK
"R"

TALK
"K"

LSTN

" .....

DEVICE

"V

TALK
"A"

LSTN

">"

Figure 23. PPDS "1", "+", ">"

. TALK.
"A"

Figure 24. PPUN

10-80

231324-001

APPLICATIONS
Parallel Poll Unconfigure

PPUN
This system command deconfigures the Parallel Poll
response of all devices by issuing a Parallel Poll
Unconfigure message.

PPUN:
Output-to-8291 PPU
Return

;Unconfigure all parallel poll

Conduct a Parallel Poll

PPOL
This system command causes the controller to conduct a Parallel poll on the GPIB for approximately
12.5 usee (at 6 MHz). Note that a parallel poll does
not use the handshake; therefore, to ensure that the
device knows whether or not its positive response

was observed by the controller, the CPU should
explicitly acknowledge each device by a devicedependent data string. Otherwise, the response bit
will still be set when the next Parallel Poll occurs.
This command returns one byte of status.

PPOL:
Enable-829I
Ion
Immediate execute pon
Output-to-8292 EXPP
Upon BI
Input-from-8291 data
Enable-8291
ton
Immediate execute pon
Return Data (status byte)

;Listen only
;This resets ton
;Execute parallel poll
;When byte is input
;Read it
;Talk only
;This resets Ion

Pass Control

PCTL 
This system command allows the controller to
relinquish active control of the GPIB to another
controller. Normally some software protocol should
already have informed the controller to expect this,
and under what conditions to return control. The

8291 must be set up to become a normal device
and the CPU must handle all commands. passed
through, otherwise control cannot be returned (see
Receive Control below). The controller will go idle.

PCTL:
If 40H $ talker $ 5EH then
if talker < > MTA .then
output-to-8291 talker, TCT
Enable-829I
not ton, not Ion
Immediate execute pon
My device address, mode I
Undefined command pass through
(Parallel Poll Configuration)
Output-to-8292 GIDL
Return

;Cannot pass control to myself
;Take control message to talker
;Set up 8291 as normal device
;Reset ton and Ion
;Put device number in Register 6
;Required to receive control
;Optional use of PP
;Put controller in idle

10-81

231324-001

APPLICATIONS

CONTROLLER

CONTROLLER

8291,8;292

8291.8292

~
,

LSTN
"I"

"A"

"I"

l&i~

DID 1

I

DEVICE
LSTH

TALK

"1"

"0"

DIO 2

:M

DID 3,

LSTH

TALK
"R"

TALK
"0"

"1"

I

DEVICE
LSTN
"2"

DEVICE

DEVICE
LSTN

TALK

"2"

"R"

DEVICE

DEVICE

LSTN

TALK

"+"

"K"

LSTH

DEVICE

TALK
"K"

DEVICE

(,
.,,)

LSTN

">"

.;.:;

TALK
"A"

LSTN
"II"

Figure 25. PPOL

Receive Control
RCTL
This, system command is used to get control back
from the current controller-in-charge if it has passed
control to this inactive- controller. Most GPIB
systems do not use more than one controller and
therefore would not need this routine.
To make passing and receiving control a manageable event, the system designer should specify a

RCTL:
Upon CPT
If (command=TCT) then
If TA then
Enable-8291
Disable, major device number
ton
Mask off interrupts
Immediate execute pon '

U;TN

">"

eTLR

Figure

TALK
"A"

26. P~TL "e"

protocol whereby the controller-in-charge sends a
data message t6 the soon-to-be-active controller.
This message should give the current state of the
system, why control 'is being passed, what to do,
and when to pass control back. Most of these issues
are beyond the scope of this Ap Note.

;Wait for command pass through bit in 8291
;If command is take control and
;We are talker addressed
;Controller will use ton and Ion ;Talk only mode

10-82

APPLICATIONS
;Take (receive) control

Output-to-8292 TCNTR
Enable-829I
Valid command
Return valid
Else
Enable-829I
Invalid command
Else
Ena ble-829I
Invalid command
Return invalid

;Release handshake

;Not talker addr. so TCT not for us
;Not TCT, so we don't care

SYSTEM
CONTROLLER
8291.8292
LSTN

LSTN

"'"

"'"

1m

TALK
"A"'

zw

'"

DEVICE

DEVICE
lSTN
"1"

TALK
"0"

LSTN
"1"

TALK
"R"

LSTN
"2"

TALK
"K"

LSTN

TALK

"0"

DEVICE
DEVICE
LSTN
"2"

TALK

"R"

DEVICE
DEVICE
LSTN

,,

DEVICE
LSTN

">"

lSTN

TALK
"K"

"+"

,

DEVICE

. ,,"

TALK

LSTN

">"

TALK
"A"

"#"

CONTROLLER

Figure 27. RCTL

Figure 28. REME

SRQD
This system command is used to detect the occurrence of a Service Request on the GPIB. One or
more devices may assert SRQ simultaneously, and

the CPU would normally conduct a Serial Poll
after calling this routine to determine which devices
are SRQing.

Service Request

10-83

APPLICATIONS
SRQD:
If SRQ then
Output-to-8292 IACK.SRQ
Return SRQ
Else return no SRQ

;Test 92 status bit
. ;Acknowledge it

SYSTEM CONTROLLER
Remote Enable
REME
This system command asserts the Remote Enable
line (REN) on the GPIB. The devices. will not go

REME:
Output-to-8292 SREM
Return

remote until they are later addressed to listen by
some other system command.

;8292 asserts remote enable line

Local
LOCL
This system command deasserts the REN line on the
GPIB. The devices will go local immediately.>

LOC£:
Output-to-8292 SLOC
Return

;8292 stops asserting remote enable

SYSTEM
CONTROLLER

SYSTEM
CONTROLLER

8291,8~92

LSTN

TALK

"I"·

"An

LSTN
"I"

m

TALK
"A"

g

I~

DEVICE

DEVICE
LSTN

TALK

"1"

"Q"

LSTN
"1"

TALK
"R"

LSTN

TALK

'.'2"

"R"

TALK
"K"

LSTN
"of"

DEVICE

DEVICE
LSTN

"Q"

DEVICE

DEVICE
LSTN
"2"

TALK

DEVICE

DEVICE
LSTN

TALK

">"

"1\"

LSTN

">"

TALK
"A"

Figure 30. IFCL

Figure 29. LOCL

10-84

231324-001

APPLICATIONS
Interrace Clear/Abort
IFCL
This system command asserts the GPIB's Interface
Clear (lFC) line for at least 100 microseconds.
This causes all interface logic in all devices to go to
a known state. Note that the device itself mayor

may not be reset, too. Most instruments do totally
reset upon IFC. Some devices may require a DCLR
as well as an IFCL to be completely reset. The
(system) controller becomes Controller-in-Charge.

IFCL:
Output-to-8292 ABORT
Return

;8292 asserts Interface Clear
;For 100 microseconds

INTERRUPTS AND
DMA CONSIDERATIONS

In, etc. The only difficulty lies in integrating these
various interrupt sources and their matching
routines into the overall system's interrupt structure.
This is highly situation-specific and is beyond the
scope of this Ap Note.

The previous sections have discussed in detail how
to use the 8291, 8292, 8293 chip set as a GPIB
controller with the software operating in a polling
mode and using programmed transfer of the data.
This is the simplest mode of use, but it ties up the
microprocessor for the duration of a GPIB transaction. If system design constraints do not allow this,
then either Interrupts and/ or DMA may be used to
free up processor cycles.

The strategy to follow is to replace each of the WAIT
routines (see Appendix A) with'a return to the main
code and provide for the corresponding interrupt to
bring the control back to the next section of GPIB
code. For example WAITO (Wait for Byte Out of
8291) would be replaced by having the BO interrupt
enabled and storing the (return) address of the next
instruction in a known place. This co-routine
structure will then be activated by a BO interrupt.
Fig. 31 shows an example of the flow of control.

The 829.1 and 8292 provide sufficient interrupts that
one may return to do other work while waiting for
such things as 8292 Task Completion, 8291 Next
Byte In, 8291 Last Byte Out, 8292 Service Request

MAIN COOE

INTERRUPT CODE

GPIB SUBROUTINE
SEND:

USER:

ACTIVATE

_
(WAIT 0)

SEND •

~

INT:

~ G~O?-----__

~

===
.

.
(WAIT 0)
__

.--INT: _

_=

GP
BBo?-----------------

..

(WAIT 0)

.--INT:=
~
GPIBBO?
•

(WAITT)

=..~INT:GPIBBO~
GPIB TCI?

ETC.

_

ETC.

Figure 31. GPIB Interrupt & Co-Routine Flow of Control

10-85

APPLICATIONS
DMA is also useful in relieving the processor if the
average length of a data buffer is long enough to
overcome the extra time used to set up a DMA chip.
This decision will also be a function of the data rate
of the instrument. The best strategy is to use the
DMA to handle only the data buffer transfers on
SEND and RECV and to do all the addressing and
control just as shown in the driver descriptions.
Another major reason for using a DMA chip is to
increase the "data rate and therefore increase the
overall transaction rate. In this case the limiting
factor becomes the time used to do the addressing
and control of the GPIB using software like that in
Appendix A. The data transmission time becomes
insignificant at DMA speeds unless extremely long
buffers are used.
Refer to Figure II for a typical DMA and interrupt
based design using the 8291, 8292, 8293. A system
like this can achieve a 250K byte transfer rate while
under DMA control.

tude. It will then tell the counter to measure the
frequency and Request Service (SRQ) when complete. The program will then read in the data. The
assembled source code will be found at the end of
Appendix A.

ZT7488/18

CONTROLLER
LSTN
"I"

CTLR

TALK
"A"

HP 5328A
COUNTER
TALK

LSTN

" "Q"

"1"

APPLICATION EXAMPLE

HP 3325A
FUNCTION
GENERATOR
LSTN
TALK
''2''
"R"

This section will present the code required to operate
a typical GPIB instrument set up as shown in Fig.
32. The HP5328A universal counter and the
HP3325 function generator are typical of many
GPIB devices; however, there are awide variety of
software" protocols to be found ort the GPIB. The
Ziatech ZT488 GPIB analyzer is used to single ~tep
the bus to facilitate debugging the system. It also
serves as a training/familiarization aid for newcomers to the bus:
This example will set up the function generator to
output a specific waveform, frequency a:nd ampli-

ZT488

GPIB ANALYZER

Figure 32. GPIB Example Configuration

SEND
LSTN: "2", COUNT: 15, EOS: ODH, DATA: "FUlFR37KHAM2VO (CR)"
;SETS UP FUNCTION GEN. TO 37 KHZ SINE, 2 VOLTS PP
;COUNT EQUAL TO# CHAR IN BUFFER
;EOS CHARACTER IS (CR) = ODH = CARRIAGE RETURN.
SEND
LSTN: "I", COUNT: 6, EOS: "T" DATA: "PR4G7T"
;SETS UP COUNTER FOR P:INITIALIZE, F4: FREQ CHAN A
G7:0.l HZ RESOLUTION, T:TRIGGER AND SRQ
;COUNTIS EQUAL TO # CHAR
WAIT FOR SRQ
SPOL TALK: "Q", DATA: STATUS 1
"
;CLEARS THE SRO-IN THIS EXAMPLE ONLY FREQ CTR ASSERTS SRQ
RECV TALK: "Q", COUNT: 17, EOS: OAH,
DATA: " +
37000.0E+0" (CR) (LF)
;GETS 17 BYTES OF DATA FROM COUNTER
;COUNT IS EXACT BUFFER LENGTH
;D~ T A SHOWN IS TYPICAL HP5328A READING THAT WOULD BE RECEIVED

10-86

231324-001

APPLICATIONS
CONCLUSION
This Application Note has shown a structured way
to view the IEEE 488 bus and has given typical code
sequences to make the Intel 8291, 8292, and 8293's
behave as a controller of the GPIB. There are other
ways to use the chip set, but whatever solution is
chosen, it must be integrated into the overall system
software.

The ultimate reference for GPIB questions is the
IEEE Std 488, -1978 which is available from IEEE,
345 East 47th St., New York, NY, 10017. The ultimate reference for the 8292 is the source listing for it
(remember it's a pre-programmed UPI-41A) which
is available from INSITE, Intel Corp., 3065 Bowers
Ave., Santa Clara, CA 95051.

APPENDIX A
ISIS-II 8~80/80B5 MACHO ASSEMBLER, V3.0
GPIB CONTROLLER SUBROUTINES
LOC

OBJ

LINE

SOURCE STATEMEN'f

1 S'fI'rLE ('GPIB CON'fROLLER SUBROU'rINES')
2

GPIB CONTROLLER SUBROUTINES

3
4
5
6
7
8
9
10

for Intel 8291, 8292 on ZT 748R/18
Bert Forbes, Ziatech Corporation
2413 Broad Street
San Luis Obispo, CA, USA 934"1

11

General Definitions & Equates
8291 Control Values

12
13

14
15
16
17 PRT91
18
19 ;
20 DIN
21 DOUT

·

22
~061

~061
~0B2
~0~1

"'Bl~

B080

0~64

038,0
B34~

30C0
0031
036,4
0020
B002
0031
11065
0~23

23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

ORG
EQU

; For ZT7488/lB w/8385
fillH

;8291 Base Port

Reg .0 Data in & Data.out
EQU
PRT91+0 191 Data in reg
EQU
PRT9l+0 ;91 Data out reg

·

INTI
IN'fMl
BOM
BIM
ENDMK
CPT

Reg • 1 Interrupt 1 Constants
EQU
PRT91+1 ;INT Reg I
PRT91+1 ;IN'f Mask Reg. 1
EQU
EQU
02
;91 BO INTRP Mask
I'll
EQU
;91 Bl INTRP Mask
EQU
HIH
;91 END INTRP Mask
EQU
B0H
;91 command pass thruint bit

·

Reg .2 Interrupt 2
EQU
PRT91+2

INT2
;

ADRMD
TON
LON
TLON
MODEl
;

ADRST
EOIS~'

TA
LA
;

AUXMD
CLKRT

Reg .4 Address Mode Constants
EQU
PRT91+4 191 adrtress mode register #
EQU
80H
;91 talk only mode & not listen only
EQU
40H
;91 listen only & not ton
EQU
0C0H
;91 talk & listen only
01
,;mode 1 addressing for device
EQU
Reg .4
EQU
EOU
EQU
EQU,

(Read) Address Status Register
PRT91+4 ; reg #4
20H

Reg .5
EQU
EQU

(Write) AuxilIary Mode Register
PRT91+5 ;91 auxilIary mode register
23H
;91 3 Mhz clock input

2
1

; 11 stener active

10-87

231324-001

APPLICATIONS
lIBB3
119116'
lI081l
IIlIl!!
111602
0903
1l1l04
91198
IlIlIlF

1l01l7
I!II'lAI'l
091H
1l~65

51l
51
52
53
54
55.
56
57
58
59
Gil

FNHSK
SDEOI
AXRA
HOHSK
HOEND
CAHCY
EDEOS
EOIS
VSCMD
NVCMD
AXRB
iiI CPTEN
62
63 ;
'i4 CPTRG

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU'
EQU
EQU
EQU

03
116
83H
1
2
3
4
8
0FH
1l7H
IlA0H
91H

Reg '5
EQU

(Read)
PRT91+5

EOU

1;5

66 ;

Reg
EQU
EQU
EQU

,I;

;91 fininsh handshake command
;91 send EOI with next byte
;91 aux. reg A pattern
;91 hold off handshake on ~ll'bytes
;91 hold off handshake on .nd
;91 continuous AH cycling
;91 end on EOS received
;91 output EOI on EOS sent
;91 valid command pass through
;91 invalid command pass through
;Aux. reg. B pattern
;command pass thru enable

. Add ress 11/1. reg. constan ts'
PRT91+6
6l1H
;Disable major talker & listener
3EIlH
;Disable minor talker & listener

0066
1l06!1
.!lIIEII

67 ADRlll
68 D'rDLl
69 DTDL2

0067

72 EOSR

Reg #7
EQU

eos

73
74
75
76

8292

CONTROL VALUES

PRT92

EQU

PRT91+8 ;8292 Base· Port t

INTMR
INTM

EQU
EQU

PRT92+1'1 ;92 INTRP Mask Reg
{lA0H
;TCI

EQU
EQU.
EQU
EQU
EQU
EQU

PRT92+0
01
02
04
PRT92+II'
PRT92+1I

CMD,92

EQU

PRT92+1 ;92 Command Register

INTST
EVBIT
IBFBT
SRQBT

EQU
EQU
EQU
EQU

PRT92+1 ;92 Interrupt Status Reg
.;Event Counter Bit
;Input Buffer Full Bit
J!2
;Seq bit
2AH

EQU
EQU
EQU
EQU
EQU

PRT92+0
PRT92+9
PRT92+11
'PRT92+0
PRT92+0

8292

OPERATION COMMANDS

EQU
EQU
EQU
EQU
EQU
EOU
EQU
EOU
EQU
EOU
EQU
EOU
EOU
EOU

9F9H
9F1H
0F2H
IIF3H
IIF4H
IIF5H
IIF6H
IIF7H
0F8H
0F9H
0FAH
0FCH
0FDH
IIFEH

UJ ;
71 ;

77

1I!l68
111668
9 II AI!
9068
0~1l1

0111'l2
0BI'l4
""68
~llfj8

0069
"069

"'01!J112
"HI
0112"
""68
11068
11068
11068
""68

78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
95
97
98
99

,

Character Register

PRT9l+7

,
,

(CS7)

;

ERRM
TOUTI
TOUT2
TOUT3
EVREG
TOREG

;92
;92
; 92
;92
; 92
;92

Error Mask Reg
Time Out for Pass Control
Time Out for Standby
Time Out for Take Control Sync
Event Counter Pseudo Reg
Time Out P.seudo Req

;

,

UH

;

ERFLG
CLRST
1IU, BUSST
ll'll EVCST
1112 TOST
Hl3

104

;92
;92
;92
;92
;92

Error Flaq Pseudo Reg
Controller Status Pseudo Reg
GPIB (Bus) Status Pseudo Reg
Event Counter Status Pseudo Reg
Time Out Status Pseudo Reg

IllS
""JFIl

1I11F!

IlJIlJF2
I'l"F3
91'lF4
1I9F5
"9FG_
9"F7
""F8
00F9
91l~'A

01lFC
99FD
I'l"FE

1l'l6
107
1118
109
110
111
112
113
114
115
116
117
118
119
l21l
121
122

;
SPCNI
GIDL
RSET
RSTI
GSEC
EXPP
GTSB
SLOC
SREM
ABORT
TCN'rR
TCASY
TCSY
STCNI

;Stop Counter Interrupts
;Go to idle
;Reset
,Reset Interrupts
;Goto standby, enable counting
;Execute par~llel poll
;Goto standby
;Set local.mode
;Set interface to remote
;Abort all operation, clear interface
;Take control (Receive control)
;Take control asyncronously
;Take control syncronously
';Start counter interrupts

10-88

231324-001

APPLICATIONS

IIIIEI
II liE 2
II11E3
II11E4
liliES
IIIIE6
II11E7
IiIIIE9
II ilEA
II !Ii Ila

123
124
125
126
127
128
129
1311
131
132
133
134
135
136
137
138

,
,
WOUT
WEVC
REVC
RERF
RINM
RCST
RBST
RTOUT
RERM
lACK
,

8292

UTILITY COMMANDS

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

IIElH
8E2H
IIE3H
8E4H
1lE5H
IiE6H
8E7H
IIE9H
IIEAH
IIBH

;Write to timeout reg
;Write to event counter
,Read event counter status
;Read error flag reg
;Read interrupt mask reg
;Read controller status reg
;Read GPIB Bus status reg
;Read timeout status reg
;Read error mask reg
;Interrupt Acknowledge

PORT F BIT ASSIGNMENTS

139

"1I6F
1111"'2
11111'14
11''''18
"'HII
iii II II 1

1111111
111141
111121
I1II3F
31138
1111114
111118
""19
AIIIlJ5
Ill! 711
1111611
111115
1111119

1411 ,
141 ;
142 PRTF
143 TCIF
144 SPIF
145 OBFF
146 IBFF
147 BOF
148
149
159 ;
151 MDA
152 MTA
153 MLA
154 UNL
155 GET
156 SOC
157 SPE
158 SPD
159 PPC
1611 PPD
161 PPE
162 PPU
163 TCT
164
165
166
167 .
168 ,
169 SETF
1711
171

EQU
EQU
EQU
EQU
EQU
. EQU
GPIB

PRT91+IIFH
;ZT7488 port 6F for interrupts
"'2H
;Task complete interrupt
.
114H
;Special interrupt
118H
;92 Output (to CPU) Buffer full
111H
;92 Input (from CPU) Buffer empty
IIlH
;91 Int line (BO in this case)
MESSAG~S

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

(COMMANDS)

1

MDA+4IIH
MDA+2IlJH
3FH
118
114H
18H
19H
115
711H
611"
ISH
119

;My device address is 1
;My talk address is 1 ("AO)
;My listen address is 1 (",")
;Universal unlisten
;GroupExecute Trigger
;Device Clear
;Serial poll enable
;Serial poll disable
;Parallel poll configure
;Parallel poll disable
;Paral1el poll disable
;para1lei poll unconfigured
;'take'control (pass control)

MACRO DE FIN I'rIONS

MACRO
ORA
ENDM

;Sets flags on A register

...

172 ;

173
174
175
176
177
178
179
1811
lSI
lS2
183
184
185

WAITO
WAITL:

;
WAITI
WAITL:

Hi6

187
188 ;
189 WAITX
190
191 WAITL:
192
193
194
195

I~ACRO

LOCAL
IN
ANI
JZ
ENDM

WAITL
INTI
BOM
WAITL

MACRO
LOCAL
IN
MOV
ANI
JZ
ENDM

WAITL
INTI
B,A
BIM
WAITL

MACRO
LOCAL
IN .

ANI

JHZ
ENDM

WAITL
PRTF
TCIF
WAITL

10-89

;Wait for last 91 byte to be done
;Get IntI status
;Check for byte out
;If not, try again
iuntil it is
;Wait for 91 byte to be input
;Get INTI status
;SAve status in B
;Check for byte in
;If not, just try again
;until it is
;Wait for 92's TCI to go false

231324-001

APPLICATIONS
196 WAITT
197
198 WAITL:
199
201!J
2111
21!J2
21!J3 RANGE
204
'21!J5
2116
207
208
21!J9
2111

211
212
213
214
215 ;
216 CLRA
217
218
219
221!J
221
222
223
224
225

MACRO
LOCAL
IN
ANI
JZ

232

Hlllil 3EMI

1Il1!J2
11!J1!J4
11!J06
11!J1!J8
HIllA
II!JI'lC
HII!JE
lIlHl
1012

D368
3EGII
D366
3EEI!J
D356
3E80
D364
3E23
D365

11114
Hl15
1Il17
11!J19
11l1B

AF
D361
D362
D355
C9

;Get task complete int,etc.
;M"sk it
; wi! i t fo r task to b,e, complete

ENDM
,MACRO

MOV
CPI,
JM
CPI
JP
ENDM
MACRO
XRA
ENDM

LOWER,UPPER,LABEL
;Checks for value in r,ange
;branches to label if not
lin range. Fails through if
;lower<= ( (H) (L) ) <= upper.
;Get next byte.
A,M
LOWER
LABE;L
UPPER+l
LABEL

'A

;1'1 XOR A =0

All of the following routines have these common
assumptions about the state of the 8291 & 8292 upon entry
to the routine and ,will exit the routine, in an identical state.
82~1:

226

227
228
229
231!J
231

WAITL
PRTF
TCIF
WAITL

, 8292:

BO is or, has been set;
All int~rrupts are masked off
TON mode, not LA
No holdoffs in effect or enabled
No holdoffs waiting for finish 'command
ATN asserted (active controller)
note: Rc'rL is an exception--- it expects
to not be active controller
Any previous task is complete & 92 is
ready to receive next command.
Pointer registers (DE,HL) enrl one
beyond last legal entry

233
234
235
236
8"85:,
237 ;
238 ;*****************.*******************~********~****** **
239
240
241
INITIALIZATION ROUTINE
242
243; INPU'rS:
None
244 ;OU'rpUTS:
None
245 ;CALLS:
None
246 ;DESTROYS:
A,F
'247 ,
248 INIT:
MVI
A,INTM ;Enahle TCI
'INTMR
ou'r
249
;Output to ,92's intr. mask reg
251!J
MVI
A,DTDLI ;Disable major talker/listener
'ou'r
ADRI'll
251
252
MVI
A,DTDL2 ;Disable minor talker/listener
ou'r
ADRl!Jl
253
MVI
A,TON
254
;Talk onl y mode
255
ou'r
ADRMD
25~
MVI
A,CLKRT ;3 ,'1HZ for 'delay, timer
257
ou'r
AUXMD
258
CLRA
'A
XRA,
259+
;A ,XOR A =I!J
oO'r
260
INTI
261
OUT
INT2
;Disable all 91 mask bits
262
OUT
AUXMD
;Immediate execute PON
RET
263
264
265 ***.*** •• ***************~*~**************************
266
267
268
SEND ROU'rINE
269

10-90

231324-001

APPLICATIONS

HllC 3E41
1~lE:

D3~~

H12~ D861
11:122 E6~2
11124 CA2011l
11127 3E3F
1~29 D360
11"26 78
102C D357

102£
102F
1031
1034
11l31i

7E
FE20
FA4711l
~'E3F

F24710

1039 DB61
1~3B E602
103D CA3910
1040 7E
1~41 D360
1043 23
1044 C 32£ 10
1047 DB61
1049 E602
11l4B CA4710
1041':
10S0
10S2
10S4

3EFo
D369
3E88
D365

10S<; DB6F
HlS8 E602
HISI'. C2S~10
10SD DB6F
10S~' E602
11161 CASDlll

11164 79
1065
11165
1069
11l5A
lllliC

B7
CA8811l
II'.
D3<;0
B8

270
271
272
273
274
27S
270
277
278
279
280
281 ,
282 SEND:
283
284

INPu'rs:

OU'fPUTS:
CALLS:
DESTROYS:

HL
DE
C
b

listener list pointer
data buffer pointer
count--" will cause no data to be sent
EOS character-- software detected

none

none
A, C, DE, HL,

F

MVI
A,MTA
; Send ."1TA to turn a ff any
OU'f
DOUT
;previous talker
WAlTa
28S+??1l0~1 :
IN
IN'fl
;Get IntI status
280+
ANI
80M
;Check for byte out
287+
JZ
??01Hll
;If not, try again
288
MVI
A,UNL
;Senn universal un1isten
DOU'j'
Ito stop previous listeners
289
ou'r
29~
;Get EOS character
'
MOV
A,B
291
EOSR
;Output it to 8291
ou'r
292
;while listener •••••
RANGE:
20H,3EH,SEND2
;Check next listen address
293 SENDl:
294+
;Checks for value in range
29.S+
;branches to label if not
2%+
lin range. Falls through if
297+
; lower (= ( (H) (L) ) (= upper.
298+
;Get next byte.
299+
MOV
A,M
300+
CPI
20H
301+
SEND2
JM
302+
3E:H+l
CPI
31l3+
SEND2
JP
304
'.AITO
;Wait for previous listener sent
3IlS+??0~1l2:
IN
IN'fl
;Get IntI status
306+
ANI
BaM
;Check for byte out
307+
JZ
??0002
;If not, try again
;~OV
A,M
308
;Get this listener
ou'r
DOUT
3119
;Output to GPIB
H
311l
INX
;Increment listener list pointer
SENDI
JMP
311
;Loop till non-valid listener
312
;Enable 91 ending conditions
313 SEND2: WAITO
;Wait for Istn addr accepted
IN
INTI
;Get IntI status
314+??fl0~3 :
315+
BOM
;Ch~ck for byte out
ANI
316+
;Ifnot, try again
JZ
??001l3
317
;WAITO required for early versions
318
;of 8292 to avoid GTSfl before DAC
MVI
319
A,GTS8
;Goto standhy
320
ou'r
CMD92
;
MVI
A,AXRA+EOIS
;Send EOI with EOS character
321
OU'f
AUXMD
322
WAITX
;Wait for Tel to go false
323
PRTF
324+??0~1l4: IN
TCIF
ANI
325+
??91~04
326+
JNZ
;Wait for TCI on GTS~
327
WAITT
PRTF
;Get task complete int,etc.
IN
328+??00~5:
;Mask it
329+
TCIF
ANI
;Wait for task to he complete
??i;l~05
.JZ
330+
331
delete next 3 instructions to make count of 0=2Sry
332 ;
333 ;
,..,ov
;Get count
334
A,C
;Set flags
SETF
335
330+
ORA
A
;If count=0, send no data
SENDI)
337
JZ
;Get data hyte
338 SEND3:
LDAX
D
;Output to GPIB
339
DOU'r
OUT
;Test EOS ••• this is faster
340
CMP
8
land uses less code than usinq
341
;91's END or EOI hits
342

10-91

231324-001

APPLICATIONS
1050

CA7~'H'

1070
1072
1074
1077
1078
1079
107C
107F
1080

0661
E6~2

CA7010
13
0D
C26910
C3881l!
13
0D

,1081 DB61
lIl83 ~602
11185 CA811"
11188 3~~'0
108A D369
108C 3£80
108E 1)365
1090 DBfiF
1092 £<;02
1094 C29010
1IJ97
1099
109B
109E

D86F
E602
CA9710
C9

109F 78
10M D3(,7

10A2
l0A3
1 0A 5
l0A8
10AA

7E
FE40
F A3 911
FE5F
F23911

lOAD D360
10AF 23
11180
1082
l0B4
10B7
1089

D861
Er,02
CAB010
3~3F

D31;0

10813 DB61
108D 8602
10BF CAB8le

343
344 SEND4:
345+770006:
346+
347+
348
349
350
351
352 SENDS:
353
354

~OS

JZ
WAITO
IN
ANI
JZ
INX
DCR

SENDS

;If char =

INT1

J:~Z

SEND3
SENDS

;Get Int1 status
;Check for byte out
;If not, try again
;Increment buffer pointer
;Decrement count
;If count < > 0, go send
;E1se go finish
; fo r consi stency

J!>IP

INX
DCR
WAITO

130M

770006
D

C

D
C

;

II

, go finish

"

;This ensures that the standard entry
;Get Int1 status
;Check for byte out
;If not, try again
;assumptions for the next subroutine are met
;Take control syncronously

355+770007:
IN
INT1
356+
ANI
BOM
357+
.JZ
770007
358
MVI
A,TCSY
359 SEND6:
OU'f
CI~D92
360
MVI
A,AXRA ;Reset send EOI on EOS
361
OUT
AUXi~O
362
WAITX
363
;Wait for TCI false
3<;4+770008: IN
PRTF
Alii I
365+
TCIF
36S+
JNZ
770008
31;7
WAIT'f
;Wait for TCI
368+770009: IN
PRTF
;Get task complete int,etc.
ANI
;Mask it
369+
TCIF
370+
JZ
770009 ;Wait for task to be complete
RET
371
372 ;*********************************************************************
373 "
374
RECEIVE ROUTINE
375
376 ,
377 ; INPUT:
HL talker pointer
378
D~ nata buffer pointer
379
C count (max buffer size) 0 implies 256
380
B EOS character
3B1 ;OUTPUT:
Fills buffer pointed at by DE
382 ;CALLS:
None
383 ; DESTROYS:
A, BC, DE, HL, F
3R4
385 ;RETURNS:
A=0 normal termination--EOS detected
386
A=40 Error--- count overrun
A<40 or A)5EH Error--~ bad talk address
387
388
389
A,B
;Get EOS character
390 RECV:
MOV
OU'f
EOSR
;Output it to 91
391
R.l\NGE
40H,5EH,RECVfi
392
;Checks for value in range
393+
;branches to label if not
394+
;in range. Falls through if
395+
; lower <= i (H) (L) ) <= upper.
3%+
;Get next byte.
397+
A,M
398+
MOV
40H
CPI
399+
400+
JM
RECV6
401+
CPI
5EH+l
RECVr,
402+
.1P
;va1id if 40H<= talk <=5EH
403
OUT
DOU'f
;Output talker to GPIB
404
INX
;Incr pojnter for consistency
405
H
'NAI'fO
406
407+770010 :
IN
IN'rl
;Get Int1 status
;Check for byte out
ANI
408+
BOM
,}Z
409+
770010 ;If not, try again
;Stop other listeners
410
MVI
A,UNL
DOUT
411
OUT
412
'NAITO
IN
INTI
413+770011:
;Get Int1 status
I\N1
BOM
414+
;Check for byte out
JZ
7?00,11 ;If not, try again
415+

10-92

APPLICATIONS
lIlC2
lIlC4
l11CG
leC8

3E:21
D3"';1I
3E:86
0365

lfiICA
ncc
l11CE:
I11Dl
HID3

DB61
E:6A2
CACAl"
3E:41l
D364

1IID5
lIlD6
I"D8
lIIDA

AF
D355
3EFIi
03<;9

HlDC OB6F
HIDE: E:61l2
10E:II C2DCn
llilE:3
l11E:5
l11E:A
l11E:C
lIiIE:D
lIlE:F
lIlF2
I11F3
UF5
HlF8
lIlFA
lIIFB
If1lFC
I11FD
111111
11112

DB6F
E:lill2
DB51
47
E:6111
C21!511
78
E:6111
CAEAl11
DB60
12
13
liD
C2EAl11
116411
C31711

111lS
11116
11118
11IilB
ll11D
1111l
1112
1113
1114
1115

78
E6111
C211111
DB61
C311611
DB61l
12
i3
IlD
06"0

1117 3EFD
1119 D369
I11B DB6F
111D E6112
11IF C21Bll
1122 DB6F
1124 E6112
1126 CA2211

1129
ll2a
112D
112F
1131
1133

3E81l
D365
3E811
D364
3EIl3
D365

1135
1136
1138
1139

AF
D365
78
C9

"IVI
416
A,MLA
;For completeness
OUT
DOUT
417
MVI
418
A, AXRA+HOENO+EDEOS
;En~ when
419
AUXMD
lEaS or EOI , Holdoff
ou'r
420
WAlTa
42l+??lilll12, IN
INTI
;det IntI status
422+
ANI
BOOI
;Check for byte out
423+
JZ
??1I1l12 ;If not, try again
424
MVI
A,LON
;Listen only
425
ADRMD
ou'r
426
CLRA
;Immediate XEQ PON
XRA
427+
A
;A XOR A =11
428
OUT
AUXMD
MVI
429
A,GTSB ;Goto standby
CMD92
4311
ou'r
WAITX
431
;Wait for TCI=1lJ
PRTF
432+??III113, IN
TCIF
433+
ANI
JNZ
434+
niHil 3
435
WAITT
;Wait for TCI=1
436+??AIl14: IN
PRTF
;Get task complete int,etc.
437+
ANI
TCIF
;Mask it
INTI
439 RECVl, IN
;Get 91 Int status (END &/or BI)
4411
MOV
B,A
;Save it in B for BI check later
ANI
ENDMK
441
;Check for EOS or EOI
442
JNZ
RECV2
;Yes end--- go wait for BI
MOV
A,B
443
;NO, retrieve status &
ANI
444
BIM
;check for BI
JZ
RECVl
445
;NO, go wait for either END or BI
445
IN
DIN
;YES, BI--- get data
447
STAX
D
;Store it in buffer
INX
448
D
;Increment buffer pointer
449
DCR
C
;Decrement counter
4511
JNZ
RECVl
;If count < > " go back & wait
451
MVI
8,411H
;Else set error indicator
452
JMP
RECV5
;And go take control
453 ;
454 RECV2: MOV
A,B
;Retreive status
455 RECV3: ANI
BIM
;Check for BI
456
JNZ
;If BI then go input data
RECV4
457
IN
INTI
;Else wait for last BI
458
JMP
RECV3
;In loop
459 RE:CV4: IN
DIN
;Get data byte
4611
STAX
;Store it in buffer
D
461
INX
D
;Incr data pointer
462
DCR
,C
;Decrement count, but ignore it
463
MVI
B,1l
;Set normal completion indicators
464 ;
465 RECV5, MVI
A,TCSY ;Take control synchronously
466
ou'r
CMD92
467
WAI'rx
;Wait for TCI=" (7 tcy)
468+??IIII15, IN
PRTF
469+
ANI
TCIF
4711+
JNZ
??I!!!l5
471
WAITT
;Wait for TCI=1
472+nllU6: IN
PRTF
;Get task complete int,etc.
473+
ANI
TCIF
;Mask it
474+
JZ
??31116 ;Wait for task to be complete
475 ;
470 ;if timeout 3 is to be checked, the above WAITT should
477 ;be omitted & the appropriate code to look for TCI or
47B ITOUT3 inserted here.
'
479
4BII
MVIA,AXRA ;Pattern to clear 91 END conditions
481
ou'r
AUXMD
,
482
foIVI
A,TON
;This bit pattern already in "AM
483
OUT
ADRMD
;Output TON
484
MVI
A,FNHSK ;Finish handshake
485
OUT
AUXMD
486
CLRA
487+
XRA
;A XOR A =fIl
A
488
AUXMD
;Immediate execute PaN-Reset LON
ou'r'
489
I~OV
A,B
;Get completion character
49{1) RECV6, RET

10-93

231324-001

113A
1138
113D
1140
1142
1145
1147

7E

1148
114A
114C
114F
1151

DB61
E602
CA4811
3E3F
D360

1153
1154
1156
1159
115B

7E
FEUI
FA6C11
FE3F
F26C11

115E
1160
1162
1165
1166
1168
1169

OB61
£602
CA5E11
7E
D360
23
C35311

116C
116E
1170
1173
1175
1177
1179

DB61
E602
CA6C11
3£87
D365
3£40
D364

1178
117C
117E
117F
1181
1183

!IF

FE40
FABB 11
FE5F
F28B11
D360
23

D365
78
D367
3EF6
D369

491
492 ****.*.*********,**********.**** •••• ***.*.******.****.********
493
XFER ROU'fINE
494
495 ,
4% ;INPU'fS:
HL device list pointer
497 ;
B EOS character
None
498 ;OU'fPUTS:
499 ;CALLS:
None
500 ;DESTROYS:
A, HL, F
A=0
normal, A ( > 0 bad talker
5111 ;RETURNS:
502
5f,J3 ,
504 ;NOTE:
XFER will not work if the talker
uses EOI to terminate the transfer.
535
506
Intel will be making hardware
537
modifications to the 8291 that will
5118
correct this problem. Until that time,
509
only EOS may be used without possible
5U ;
loss of the last data byte transfered.
511 XFER:
RANGE
4IlH,SEH,XFER4
;Check for valid talker
512+
;Checks for value in range
513+
;branchas to label if not
514+
lin range. Falls through if
515+
; lower <= ( (H) (L) ) (= upper.
51fi+
;Get next byte.
517+
MOV
A,~
CPI
518+
41lH
519+
JM
XFER4
520+
CPI
Sr;H+l
521+
JP
XFER4
OUT
DOUT
;Send it to GPIB
522
INX
523
H
;Incr pointer
If/AlTO
524
525+??0017:
IN
INTl
;Get IntI status
ANI
BOM
526+
;Check for byte out
JZ
527+
??0~17
;If not, try again
I~VI
A,UNL
528
;Universal unlisten
OUT
DOUT
529
530 XFERl: RANGE
20H,3EH,XFER2
;Check for valid listener
531+
;Checks for value in range
;branches to label if not
532+
lin range. Falls through if
533+
; lower ,(= ( (H) eL) ) (= upper.
534+
;Get next byte.
535+
MOV
A,M
536+
CPI
20H
537+
XFER2
JM
538+
3EH+l
CPI
539+
XFER2
JP
540+
WAITO
541
INTI
;Get IntI status
542+??"018: IN
BOM
ANI
543+
;Check for byte out
544+
71:0018 ;If not, try again
JZ
545
A,~
MOV
;Get listener
546
DOUT
OU'f
H •
547
INX
;Incr pointer
548
JMP
XFERl
;Loop until non-valid listener
549 XFER2: WAITO
550+??0019: IN
INTI
;Get IntI status
ANI
551+
, BOM
;Check for byte out
552+
JZ
??0019 ;If not, try again
MVI
A,AXRA+CAHCY+EDEOS
;Invisible handshake
553
AUX'lD
;Continuous AH mode
OUT
554
555
A,LON
;Llsten only
MVI
ADRMD
556
ou'r
CLRA
557
;A XOR A =0
A
XRA
558+
AUXMD
; Immed. XEQ PON
559
OUT
A,B
;Get EOS
5fi0
MOV
EtlSR
;Output it to 91
561
ou'r
A,!iTSB ;Go to standby
MVI
562
OUT
CMD92
563

10-94

231324-001

APPLICATIONS
1185 OB6F
1187 E602
1189 C28511
ll8C
118E
1190
1193
1195
1197
119A
119C

OB6F
E:602
CA8C11
OB61
Efiil'
CA9311
3EFO
0369

119E OB5F
11M E6~2
11A2 C29E:11
11A5
11A7
11A9
11AC
11AE
11BI!
11B2
11B4
11B6

DB6F
E602
CAA511
3E80
0365
3E03
0365
3E80
0364

1188 AF
11B9 0355
11BB C9

564
565+171'1020:
566+
567+
568
569+??0021:

WAITX
IN
ANI
JNZ
WAI'!"r

PRTF
TCIF
170020

HI

PRTF

571H

ANI
JZ
IN
ANI
,JZ
MVI

TCU'

571+
572 XFER3:
573
574
575
576
577
578+??0022:
579+
580+
581
582+??0023:
583+
584+
585
586
587
588
589
590
591
592+
593
594 XFn4:
595 ,

ou'r

WAI'!,X

170021
IN'rl

ENDMK
XFP.R3
A,TCSY
C"1092

IN

PRTF

ANI
JNZ
WAITT

TCU'

IN

PRTF

ANI
JZ
!'lVI
OU'I'
MVI
OU'!,
"1 VI
OUT
CLRA
XRA

ou'r

,Wait for TCS
;Get task complete int,etc.
;Mask it
;wait for task to be complete
;Get END status bit
;Mask it
;'rake control syncronous1y

??0322
;Wait for
;Get task
;Mask it
;Wait for
;Not cont

'rcU'

TCI
complete int,etc.

task to be complete
??0023
A,AXRA
AH or END on EOS
AUXMD
A,FNHSK ;Finish handshake
AUXMD
A,TON
;Ta1k only
ADRMD
;Normal return A=A
A
;A XOR A =0
AUXMD
;Immediate XEQ paN

RET

596 ;***************************************************

11BC 3E3F
11BE 0350

11CI!
11Cl
11C3
11C6
11C8

7E
FE20
FA0911
FE3F
F20911

11CB
llCD
llCF
1102
1103
1105
1106

OB61
E602
CACB11
7,;
0360
23
C3C011

11D9
llOB
llDD
11E0
l1g2

OB61
g<';02
CAD911
3E08
D3~0

l1g4 0861
l1gfi E602

597
598
599
TRIGGER
600
601 ,
602 I INPu'rs:
6113 ;OUTPU'tS:
1;04 ; CALLS:
61!5 ;DESTROYS:
li0fi
1;37 ,
MVI
608 'rRIG:
609
au'!'
fi10 TRIG1: RANGE
611+
612+
613+
614+
fi15+
I>lfi+
MOV
617+
CPI
JM
618+
CPI
619+
JP
620+
WAI'I'O
621
1;22+??0024: IN
623+
ANI
JZ
fi24+
625
"10V
OU'!,
626
INX
627
JMP
628
629 TRIG2: WAITO
631!+??0025: IN
ANI
631+
JZ
632+
;~VI
633
OUT
634
\~AITO
635
(,36+170026: IN
ANI
fi37+

ROUTINE
HL listener list pointer
None
None
A, HL, F
A,UNL
,
OOUT
;S.end universal unlisten
20H,3EH,TRIG2
;Check for valirl listen
;Checks for value in range
;branches to label if not
; in range. Falls through if
; lower (= ( .!
.,VI
913
A,EXPP ,Execute parallel poll
914
ou'r
CMD92
915
WAUl
,Wait for completion= BI on 91
916+??II049: IN
INTI
,Get INTI status
917+
MOV
8,A
;Save status in B
918+
ANI
BIM
;Check for byte in
919+
JZ
??0049 ;If not, jtist try again
920
I~VI
A,TON
,Talk only
ou'r
921
ADRMD
CLRA
922
,Immediate XEQ PON
923+
XRA
A
,A XOR A =0
. 924
ou'r
AUX.,D
,Reset LO>/
IN
925
DIN
,Get PP byte
926
RET
927
928 **********************************************
929 PASS CONTROL ROU'rINE
930
931 INPUTS:
HL pointer to talker
932 OUTPUTS:
None
o

0

10-99

231324-001

APPLICATIONS

1344
1345
1347
134.0.
134C
134F
1351
1354

7E
FE41/J
FAsA13
FE5F
F28A13
FE41
CA8A13
D361/J

1356
1358
135A
135D
135F

DB61
EGl!l
CA5613
3EB9
D3611l

1361
1363
1365
131;8
131;.0.

DB61
E6Q12
CA6113
3EI/Jl
D364

136C AF
136D D365
136F 3ui
1371 D366
1373 3EAl
1375 D365
1377 3EFl
1379 0369
ij7B DB6F
137D E61/J2
137F C27B13
1382
1384
1385
1389
138.0.

'DB6F
Enlil2
C!\.8213

23
C9

138B D851
i38D EG81/J
138F CACF13
1392 OB65
1394 FEIl9

None
933 ;CALLS:
934 ; DESTROYS:
A, HL, F
935 PCTL:
RANGE
411lH,5EH,PCTLl
;Is it'a valid talker?
936+
;Checks for value in range
;branches
to label if not937+
938+
lin range. ,Falls through if
939+
;lower <= ( (H) (L) ) <= upper.
949+
;Get next byte.
941+
MOV
A,M
CPI
411lH
942+
J,"I
943+
PCTLI
944+
CPI
5EH+I
945+
JP
PCTLI
,Is it my talker address
946
CPI
MTA
947
JZ
,PCTLI
;Yes, just return
948
DOUT
;Send on GPIB
OUT
949
WAlTO
951i1+??1iI351!: IN
INTI
;Get Intl status
ANI
BOM
951+
;Check for byte out
952+
JZ
;If not, try again
~?IIlIlS0
MVI
953
A,TCT
;Take control message
OU'f
DOUT
954
WAlTO
955
956+??1/J1Il51 : IN
INn
iGet IntI status
ANI
BOM
,Check for. byte out
957+
JZ
??9I'lSI ;Ifnot, 'try again
958+
A,MODEI
MVI
;Not talk only or listen only
959
961/J
OU'f
ADRMD
;En~ble 91 address mode 1
9til
CLRA
9"i2+
XRA
A
;A XOR A =11
,
963
OUT
AUXMO
;Immediate XEQ PON.
, 91;4
MVI
A,MDA
;My device address
965
QU'f
ADR!!l
;enabled to talk and listen
965
MV~
A,AXRB+CPTEN
,Command pass thru enable
OUT
AUXMD
967
968 ; .······optional, pp configuration goes here •••• •• ••
91;9
MVI
A,GIDL ;92 go idle command
OU'f
CMD92
971i1
WAITX
971
PRTF
972+??IiI"52 : IN
973+,
TCIF
ANI
, 974+
??1Il1/J52
JNZ
;Wait for TCI
975
WAITT
976+??1Il1l53 : HI
,Get task complete int,etc.
PRTF
ANI
;Mask it
977+
TCIF
978+'
JZ
;niHl53 ;Wait for task to be complete
INX
979
H
981i1 PCTLl:- RET
981
9fl2 i

•• *********.********.**

983

,~***************~*

984
985
986
987
988
989
99'"
991
992
993
994
995
996
997
998
999

;
;RECEivE CONTROL ROUTINE
,
None,
; INPUTS:
None
;OU'fPUTS:
;CALLS:
None
;DESTROYS:
A" F
0= invalid (not take control to us or CP'f bit not on)
;RETURNS:
< > iii = valid take,control-- 92 will now be in control
;
THIS CODE MUST BE TIGHTLY INTEGRATED IWrO ANY USEq
;NOTE I
SOFTWARE THA'f FUNCTIONS \~ITH THE 8291 AS A DP.VICE.
NORMALLY 'SOME ADVA~CE WARNING OF IMPENDING PASS
CONTROL SHOULD BE GIVEN 'ro US BY 'fHE CONTROLLER
WITH OTHER, USEFUL INFO. THIS PROTOCOL IS SITUATION
SPECIFIC AND I..rILL NOT BE COVERED HERE.

1""'
;
11101" RCTL:

1 ~rll2

IN

INn

ANI

11/J1Il3
111l(»4
lI/JIIl5

JZ

CPT
RC'fL2
CPTRG
TCT

IN

CPI

;Get INTI re'l (i.e. CPT, etc.)
; Is command pass thru ,on ?
;No, invalid-- go return
;Get command
;Is it take control?

10-100

231324-001

APPLICATIONS
1396
1399
139B
1390
13A0
13A2
13M
13AG

C2CA13
OB64
E602
CACA13
3E8~

1006
1307
1008
1009
1010
1011
1012

03';4

1~13

13A8
13.0.9
13AB
13.0.0
13AF
13Bl
1363
13B5

AF
0361

1014
1015+
1016
1017

3E6~

035!;

03~2

0365
3EFA
0369
3E0F
D3';5

13B7 OB'iF
13B9 E61l2
13BB C2B713
13i:lE
13C0
13C2
13C5
13C7
13CA

OB6F
Efj02
CABE13
3E09
C3CF13
3EeF
l3ec 0365

l3CE AF
13CF C9

.1NZ
IN
ANI
.JZ

MVI
OUT
MVI
OU'I'
CLRA
XRA
OUT
OU'I'
OU'I'
MVI

RCTLI
AORST
'I'A
RCTLI
A,OTOLI
AOR01
A,TON
AORMD

;No, go return invalid
;Get address status
;Is TA-on ?
rNo -- go return invalid
;Oisable talker listener
;Talk only

;A XOR A =0
IN'rl
;Mask off INT bits
INT2
U118
AUXMO
1019
A, TCN'I'R ;Take (receive) control 92 command
CM092
1020
Qu'r
1021
MVI
A,VSCMD ;Valid command pattern for 91
AUXMO
1022
ou'r
H123 ;******** optional TOUT 1 check could be put here ********
','lAITX
1024
1025+??0054: IN
PRTF
ANI
1026+
TCIF
JNZ
1027+
??~054
1028
'tiAITT
;Wait for TCI
1029+??0~55: IN
;Get task complete int,etc.
PRTF
1030+
ANI
TCIF
;Mask it
1031+
JZ
;Wait for task to be complete
??0~55
1032
MVI
A,TC'!'
;Va1id return pattern
1033
J'IP
BC"rL2
;Only one return per routine
1034 RCTL1: MVI
A, VSCfoID ;Acknowledge CPT
1035
OU'I'
AUXMO
1036
CLRA
;Error return pattern
1037+
;.0. XOR A =0
XR."
1038 RCTL2: RET
1039 ,
A

1040 ;*************************************************

1300
1302
1304
1307
13D9
1309
1300
130F
13E2

Oflfi9
E620
CAE213
~'60B

0369
OB69
E602
CAOB13
C9

13E3 3EF8
13E5 0369
13E7 OBnF
13E9 EI\02
13EB C2E713
13EE OB6F
13F0 E1502
13F2 CAEE13

1041
1042
SRO ROU'I'INE
1e43
None
1044 ; INPUTS:
None
1045 ; OU'I'PU'I'S:
None
H46 ;CALLS:
1047 ; RE'I'URNS:
.0.= 0 no SRO
1048
A < > 0 SRQ occured
1049
1050
IN
INTST
;Get 92's I~TRQ status
1051 SRQD:
ANI
;Mask off SRQ
1052
SRQ!:!T
'1053
,JZ
SRQD2
;Not set--- go return
;Set--- must clear it with lACK
1054
ORI
lACK
1055
OU'I'
CMD92
;Get IBF
1056 SRQDl: IN
HI '!'s 'I'
1057
ANI
IBFRT
;Mask it
,]Z
1058
SRQDl
;W~it if not set
1059 SRQ02: RET
106\! ,
lC61' ;********************************************
leli2 ,
1063 ;REMOTE ENABLE ROUTINE
1064 ,
1055 ; INPUTS:
None
None
10% ;OU'I'PU'I'S:
NONE
101\7 ;CALLS:
1068 ; DESTROYS:
A, F
1069 ,
1070 REME:
MVI
A,SREM
OU'I'
CMD92
;92 asserts remote enable
1071
WAI'I'X
;Wait for TCI = 0
1372
1073+??U{15'i : IN
PRTF
ANI
1074+
'l'CIF
1075+
JNZ
WAIT'!,
1076
;Wa i t fo r TCI
1077+??00 57: IN
PRTF
;Get task complete int,etc.
ANI
TCIF
;Mask it
1078+
1 (!79+
??~(l57
JZ
;Wa i t fo r task to be complete

10-101

APPLICATIONS
13F5 C9

RET

lIl8'"

HlIH ;

lA82 ;***.*** •• ** ••• ****** •••• ********* ••• ******
lIl83 ;
11'184 ;LOCAL ROUTINE
1085
11186

13F6 3EF7
13F8 0369
13FA DB6F
13FC E632
13FE C2FA13
14"1
14"3
l4filS
141118

OB6F
E602
CA"114
C9

141119 3EF9
1411lB D3~9
1411lD DaliF
1411lF E5fil2
1411 C20D14
1414 DBIiF
1416 E602
1418 CA1414

1418 C9

,

111187 ; INPU'l'S:
None
None
111188 ;OUTPUTS:
None
Hl89 ;CALLS:
A, F
!A9fil ; DESTROYS:
Hl91 I
MVI
A,SLOC
111192 LOCL:
OUT
CMD92
;92 stops asserting remote enable
1993
WAITX
,Wait for TCI =11
111194
PR'l'F
1Il9S+??1Il11l 58: IN
lfil96+
ANI
TCIF
lfil97+
??0115A
JNZ
,Wait for TCI
111198
WAIT'r
,Get task complete int,etc.
11199+??AI'I591 IN
PRTF
,Mask it
IHlIll+
TCIF
ANI
11111+
??01159 ,Wait for task to be complete
JZ
11112
RE'r
11113 /
111114 ; ••••••• *.*******.*.**.*************.*********.
11115 ;
11116 / INTERFACE CLEAR I AIlOltT Rou'rINE
11117 ;
111118 ';
None
11119 / INPu'rs:
None
11111 ,ou'rpUTS 1
None
1111 ; CALLS:
1112 ,DESTROYS:
A, F
1113
1114 ,
1115 IFCL:
MVI
A,ABORT
1116
OUT
CMD92
,Send IFC
1117
WAITX
;Wait for TCI =1'1
1118+??1'I1'I6fil: IN
PRTF
1119+
ANI
TCIF
1120+
JNZ
??~0Iig
1121
WAITT
,I4a i t fo r TCI
.
PRTF
;Get task complete int,etc.
1122+??Afil61: IN
1123+
ANI
TCIF
,Mask it
1124+
JZ
??1'I061 ;Wait for task to be complete
1125 ,Delete both WAITX & WAITT i f this routine
1121i lis to be called while the 9292 is
1127 /Controller-in-Charqe. If not C.I.C. then
1128 ;'rCI is set, else nothing is set (IFC is sent)
1129 land the WAIT'S will hang forever
1130
RET
.
1132 I

10-102

231324-001

APPLICATIONS

0032
~~31

'''''51
01iJliJD
~00A
1iJ0~'F

0040
141C
1420
1424
1428
142A

46553146
5233374B
48414032
564F
00

00~F

142B 50463447
142F 3754
00~6

1431
1432
1433
1434
1435
1431i

31
FF
32
FF
51
FF

1437
1439
143B
143E
1441

0fi0D
0E0F
l11C14
213314
CD1C10

1444 0~54
1446 0E06
1448 112B14

144B 213114
144E CDIC10

1451 CD0013
1454 CAS114

1457
145A
1450
1460
1461
,14fi2
1464

1467
1469
146B
14'6E
1471
1474

11003C
213514
CD1C12
1B
1A
E640
CA7714

1iJ60A
"'Ell
213514
11Bl3C
CD9F10
C27714

1477 00
3C0'"
3C00
0011

1133
1134
1135
1136
1137
1138
1139
1141'1
1141
1142
1143

;APPLICATrON eXAMPLE CODE FOR

,

'2'
'1'

EQU
EQU
EQU
EQU
EQU
EQU
EQU

'Q'
0DH

DB

'FUlFR37KHAM2VO',CR

;Data to set up func. gen

1144 LIMI
EQU
1145 FCDATA: DB

15
'PF4G71"

;Buffer length
;Data to set up freq ctr

1146 LIM2
1147 LLl:

EQU
DB'

Ii

FCDNL,LEND

;Buffer lenqth
,L~sten list for freq ctr

1148 LL2:

DB

FGDNL, LEND

iListen list for func. gen

1149 TLl:

DB

FCONT,LENO

;Talk list for freq 6tr

1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
11611
1161
1162
1163
1164
11 liS
, 1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1181;
1187
1188
1189
1191!
1191
1192
1193
1194
1195
1195
1197

FGDNL

8~85

~'CDNL

FCDNT
CR
LF
LEND
SRQM

,Func gen device num "2" ASCII,lstn
;Freq ctr device num "I" ASCII,lstn
;Freq ctr talk address
;ASCII carriage return
;ASCII line feed
;List end for Talk/Listen lists
;Bit indicating device sent SRO

~AH
~n'H

41'1H

;
~'GDA1'A:

,

,SETUP FUNCTION
MVI
MVI
LXI
LXI
CALL

GENERA'rOR
B,CR
;EOS
C,LIM1 ;Count
D,FGDATA
;Oata pointer
H,LL2
;Listen list pointer
SEND

;

,SETUP FREQ COUNTER
MVI
MVI
LXI
L~I

CALL

B,'T'
;EOS
C,LIM2 ,Count
D,FCDATA
;Data pointer
H,LLI
;Listen list pointer
SEND

;

;WAIT FOR SRQ FROM FREQ CTR

,

LOOP:

CALL
JZ

;Has SRQ occurred?
;No, .wait for it

SRQD
LOOP

;

;SERIAL POLL TO CLEAR SRQ
LXI
LXI
CALL
OCX
LDAX
ANI
JZ

O,SPBYTE
H,TLl
SPOL

o

o

SRQM
ERROR

;Iluffer pointer
;Talk ~ist pointer
;Backup buffer pointer to ctr byte
;Get status byte
;Oid ctr assert SRQ ?
;Ctr should have said yes

;

;RECeIVE READING FROM COUNTER

,

MVI
MVI
LXI
,LXI
CALL
JNZ

B,LF
;EOS
C,LIM3 ,Count
H,TL1
;Talk list pointer
O,PCDATI
;Data in buffer pointer
RECV
ERROR

;******* rest of user processing goes here *****

,

Nap
ETC.
ORG
3C00H
SPBYTE: OS
LI",3
EQU

;User dependant error handling

ERROR:

,

1

17

;Location for serial poll byte
;Max freq counter input

10-103

231324-001

APPLICATIONS
3CIIJI

1198 FCDATI: DS
1199
END

;Freq ctr input buffer

LIM3

PUBLIC SYMBOLS
EXTERNAL SYMBOLS
US Elt SYMBO~S
ABOIlT A 00F9
81M
A 00Al
C~ItST
A 006B
DCLR
A 11EC
EDEOS A 0904
ERROR " 1477
t"CDNL A 0031
A 90F4
GSEC
IFCL
A 1489
IN'rST A 0069
LLI
A 1431
MODEl A 9901
ppo.
A 007R
PPEN2 A 12DB
RANGE + B005
RECVl A 10EA
RER~"
A 00£4
SDEOI A 0006
SENo.6 A 1088
SPIF
A 9004
SRQDl
A 13o.B
'rCNTR II 90FA
TOST
A 0068
UNL
A 903F
wou'r
A 09Bl
ASSEI~BLY

ADRB!
80F
CMD92
DC~Rl

ENDMK
EvaIT
FCON'r
GTSB
INIT
LA
LL2
MTA
PPo.S
PPOL
RSST
RECV2
RERM
SEND
SETF
SPO~

SRQD2
TCSY
Tou'rl
VSCMD
XFER

COI~PLETE,

A 0Bfi~
A 0AAI
A 0069
A 11FA
0AlA
A AnA
A 0051
A BAF6
A 1009
A 0901
A 1433
A 0341
11 12E9
A 1327
A BAE7
A 1195
A B0EA
A U1C
+ 0Bn.
1\ 121C
A 13E2
A 09FD
A AB91
1\ 00aF
A 113A

"

ADR.~D

BOM
CPT
OCLR2
EOIS
EVCST
FGDATA
HOENO
INTI
LEND
LOCL
NVC~D

PPDSI
PPU
RCST
RBCV3
REVC
SENDI
SLOC
SPOLI
SROM
'rCT
TOUT2
WAITI
XF.ERI

A
A.
A
A
A
A
A
A
A
1\
A
A
A
A
A
1\
A
A
A
A
A
A
A

+
A

0A~4
0~A2

AAPA
1209
9908
996A
141C
A9A2
0A<1
9AFF
13F<
RR07
12E4
9915
0DE~

11n~

90E3
192E
09F7
12lD
0040
0999
A0.2
B992
1153

A A~<4
A Aa<~
A AOA1
DI~
A 9A<~
EOIST A 0A2"
EVREG
0A6A
FGONL A 0A32
HOHSK A AAAI
INT2
A 99<2
LF
A BAAl'.
LON
A A049
OBFF
A AR~a·
PpDS2 A 12FD.
PPUN
A' 1318
RCTL
1\ 139B
RECV4 A, 11lA
RINM
A •• ES
SEND2 A 1047
SPBYTE A 3CBD
SPOL2 A 1294
STCNI A A9FP.
'rLl
A 1435
TOUT3
A ".A4
WAITO + A9nl
XFER2 A ll~C

ADRST
BUSST
CPTEN

"

AUX~D

CAHCY
CPTRG
DOUT
EOSR
EXPP
FNHSK
lACK
INTM
LIM1
LOOP
PCTL
PPE
PRT91
RCTLI
II~CV5

RSBT
SEND3
SPCNI
SRE~

TA
TLO'l
'rRIG
WAITT
XFER3

A
A
A
A
A
A
A
A
A
A
A
A
A
II
A
A
A
A
A
A
A
A
II

AA<~

AXRA

AAAl

C~KRT

9A<~

CR
DTOLI
ERFLG
FCDATA
GET
IBFBT
INTMI

A~ 8291A GPIB
(General Purpose Interface Bus) Talker/Listener as a
component, and shows its use in GPIB interrace design
tasks.

DEVICE A
ABLE TO
TALK, LISTEN,
AND
CONTROL

The first section cif this note presents an overview of IEEE
488 (GPIB). The second section introduces the Intelill>
GPIB component family. A detailed explanation of the
8291A follows. Finally, some application examples using
the component family are presented.

IIIII III f
-'---<
DATA BUS

(-

(e.g. calculator)

DEVICE B
ABLE TO
TALK AND
LISTEN

i-=--

(e.g. digital
muilimeler)
DATA BYTE
TRANSFER
CONTROL

(~IDEVICE C
ONlY ABLE
TO LISTEN

r--

(e.g. signal
generator)

(
DEVICE 0
ONLY ABLE
TO TALK

GENERAL
INTERFACE
MANAGEMENT

IJ

I---

(e.g. counler)

}DI01 •••

Figure 1.

a

Data InpuV·Output .

DAV

Data Available

NRFD
NDAC

Nol Ready lor Data
Not Data Accepted

IFC
ATN
SRQ

Inlerlace Clear
Ailenlion
Sorvl ce Requesl

REN

Rem ole Enable

EOI

End or Identlly

Interface Capabilities and Bus Structure

10-115.

230832-001

inter

. AP-166

OVERVIEW OF IEEE 488/GPIB
The GPIB is a parallel interface bus with an asynchronous interlocking data exchange handshake mechanism. It is designed to provide a common communication
interface among devices over a maximi um distance of 20
meters at a maximum speed of I Mbps. Up to 15 devices
may be connected together. The asynchronous interlocking handshake dispenses with a common synchronization
clock, and allows intercommunication among devices
capable of running at different speeds. During any
transaction, the data transfer occurs at the speed of the
slowest device involved.

ATN (attention) is used.by the Controller to indicate that
it (the controller) has access to the aPlB and that its
output on the data lines is to be interpreted as a
command. ATN is· also used by the controller along with
EOI to indicate a parallel poll.
SRQ (service request) is used by a device to request
service from the controller.
REN (remote enable) is used by the controller to specify
the command source of a device. A device can be issued
commands either locally through its front panel or by the
controller.

The GPIB finds use in a diversity of applications
requiring communication among digital devices over
short distances. Common examples are: programmable
instrumentation systems, computer to peripherals, etc.

EOI (end or identify) may be used by the controller as
well as a talker. A controller uses EOI along with ATN to
demand a parallel poll. Used by a talker, EOl indicates
the last byte of a data block.

The interface is completely defined in the IEEE
Std.-488-l978.

IFC (interface clear) forces a complete GPlB interface to
the idle state. This could be considered the GPIB's
."interface reset." GPlB architecture allows for more than
one controller to be connected to the bus simultaneously.
Only one of these controllers may be in command at any
given time. This device is known as the controller-incharge. COIitrol can be passed from one controller to
another. Only one among all the controllers present on a
bus can be the system controller. The system controller is
the only device allowed to drive IFC.

A typical implementation consists of logical devices
which talk (talker), listen (listeners), and control GPlB
activity (controllers).

Interface Functions
The interface between any device and the bus may have a
combination of several different capabilities (called
'functions'). Among a total of ten functions defined, the
Talker, Listener, Source Handshake, Acceptor Handshake and Controller are the more common examples.
The Talker function allows a device to transmit data. The
Listener function allows reception. The Source and
Acceptor Handshakes, synchronized with the Talker and
Listener functions respectively, exchange the handshake
signals that coordinate data transfer. The Controller
function allows a device to activate the interface functions
of the various devices through commands. Other interface
functions are: Service request, Remote local, Parallel
poll, Device clear and Device trigger. Each interface may
not contain all these functions. Further, most of these
functions may be implemented to various levels (called
'subsets') of capability. Thus, the overall capability of an
interface may be tailored to the needs of the communicating device.

DAV (data valid) is driven by a talker and indicates that
valid data is on the bus.

Electrical Signal Lines

The asynchronous 3-wire handshake flowchart is shown
in Figure 2. This is a concept fundamental to the
asynchronous nim::..; of the aPlB and is reviewed in the
following paragraphs.

As shown in Figure I, the GPIB is composed of eight data
lines (D08-DOI), five interface management lines
(IFC, ATN, SRQ, REN, EOI), and three transfer control
lines (DAV, NRFD, NDAC).
The eight data lines are used to transfer data and
commands from one device to another with the help of
the management and control lines. Each of the five
interface management lines has a specific function.

Transfer Control Lines
The transfer control lines conduct the asynchronous
interlocking three-wire handshake.

NRFD (not ready for data) is driven by the listeners and
indicates that not all listeners are ready for more data.
NDAC (not data accepted) is used by the listeners to
indicate that not all listeners have read the GPIB data
lines yet.

Assume that a talker is ready to start a data transfer. At
the beginning of the handshake, NRFD is false indicating
that the listener(s) is ready for data. NDAC is true
indicating that the listener(s) has not accepted the data,
since no data has been sent yet. The talker places data on
the data lines, waits for the required settling time, and
then indicates valid data by driving DAV true. All active
listeners drive NRFD true 'indicating that they are not

10-116

230832-{)Ol

inter

AP-166

NRFD SIGNAL LINES GOES HIGH

YES

r---..L.";';;~.., ONLY WHEN ALL ACCEPTORS ARE READY

DATA IS VALID AND MAY
NOW BE ACCEPTED

DATA IS NOT TO BE CONSIDERED
VALID AFTER THIS TIME

FLOW DIAGRAM OUTLINES SEQUENCE OF EVENTS DURING TRANSFER
OF DATA BYTE. MORE THAN ONE LISTENER AT A TIME CAN ACCEPT
DATA BECAUSE OF LOGICAL CONNECTION OF NRFD AND NDAC
.INES.

Figure 2.

Handshake Flowchart

10-117

230832-001

AP-166

ready for more data. They then read the data and drive
NDAC false to indicate acceptance. The talker responds
by deasserting DAY and readies itself to transfer the next
byte. The listeners respond to DAY false by driving
NDAC true. The talker can now drive the data lines with
a new data byte and wait for NRFD to befalse to start the
next handshake cycle.

Bus Commands
When ATN and DAY are true data patterns which have
been placed by the controller on the GPIB, they are
interpreted as commands by the other devices on the
interface. The GPIB standard contains a repertory of
commands such as MTA (My ll!lk Address), MSA (My
Secondary Address), SPE (Serial Poll Enable), etc. All
other patterns in conjunction with ATN and DAY are
classified as undefined commands and their meaning is
user-dependent.

Addressing Techniques
To allow the controller to issue cOQ1mands selectively to
specific devices, three types of addressing exist on the
GPIB: talk only/listen only (ton/Ion), primary, and
secondary.
Ton/Ion is a method where the ability of the GPIB
interface to talk or listen is determined by the device and
not by the G PIB controller. With this method, fixed roles
can be easily designated in simple systems where reassignment is not necessary. This is appropriate and convenient
for certain applications. For example, a logic analyzer
might be interfaced via the GPIB to a line printer in order
to document some type of failure. In this case, the line
printer simply listens (0 the logic analyzer, which is a
talker.
The controller addresses devices through three commands, MTA (my talk address), MLA (my listen address),
and MSA (my secondary address). The device address is
imbedded in the command bit pattern. The device whose
address matches the imbedded pattern is enabled. Some
devices may have the same logical talk and listen
addresses. This is allowable since the talker and listener
are separate functions. However, two of the same functions cannot have the same address.
In primary addressing, a device is enabled to talk (listen)
by receiving the MTA (MLA) message.
Secondary addressing extends the address field from 5 to
10 bits by allowing an additional byte. This additional
byte is passed via the MSA message. Secondary addressing can also be used to logically divide devices into
various subgroups. The MSA message applies only to the
device(s) whose primary address immediately preceed it.

INTEL'S® GPIB COMPONENTS
The logic designer implementing a G PIB interface has, in
the past, been faced with a difficult and complex discrete
logic design. Advances in LSI technology have produced
sophisticated microprocessor and peripheral devices
which combine to reduce this once complex interface task
to a system consisting of a small set of integrated circuits
and some software drivers. A microprocessor hardware/
software solution and a high-Ievcllanguagc source code
provide an additional benefit in end-product maintenance. Product changes are a simple matter of revising
the product software. Field changes are as easy as
exchanging EPROMS.
Intel® has provided an LSI solution to GPIH interfacing
with a talker/listener device (829IA), a controller device
(8292), and a transceiver (8293). An interface with all
capabilities except for the controller function can be built
with an 8291A and a pair of 8293's. The addition of the
8292 produces a complete interface. Since most devices in
a GPIB system will not have the controller function
capability, this modular approach provides the least cost
to the majority of interface designs.

Overview of the 8291A
GPIB Talker/Listener
The Intel® 8291 A GPIB Talker'! Listener operates over a
clock range of I to 8 M Hz and is compatible with the
MCS-85, iAPX-86, and 8051 families of microprocessors.
A detailed description of the 8291 A is given in the data
sheet.
The 8291 A implements the following functions: Source
Handshake (SH), Acceptor Handshake (AH), Talker
Extended (TE), Service Request (SRQ), Listener Extended (LE), Remote/Local (RL), Parallel Poll (PP2),
Device Clear (DC), and Device Trigger (DT).
Current states of the 8291 A can be determined by
examining the device's status read registers. In addition,
the 8291A contains 8 write registers. These registers are
shown in Figure 3. The three register select pins RS3RSO are used to select the desired register.
The data ~ in register moves data from the GPIB to the
microprocessor or to memory when the 8291 A is
addressed to listen. When the 8291 A is addressed to talk,
it uses the data - out register to move data onto the G PIB.
The serial poll mode and status registers are used to
request service and program the serial poll status byte.
A detailed description of each of the registers, along with
state diagrams can be found in the 8291 A data sheet.

10-118

230832-001

AP-166

READ REGISTERS

WRITE REGISTERS

REGISTER SELECT
CODE
RS2

I 017 1 Dial 015 1 014 1 Dr31 012 1 011 I 010 I 0

RS1

0

RSO

a I 007 1 Doal 005\ 004 1 003\ 002 1 001

I

CPT I APT I GET

I

END I DEC I ERR

I

BO

BI
I

0

0

1

I

I I I

GET I END I DEC I ERR I BO

CPT APT

INTERRUPT ENABLE 1

0
INTERRUPT STATUS 2

S8 ISRQSI sa

SS
S3
S1
S4
S2
I
I
I
I
I
SERIAL POLL STATUS 2

ton

\

Lon
I

I

BI
I

INTERRUPT STATUS 1

I

I 000

I

DATA OUT

DATA IN

EOI I LPAS I TPAS I LA

0
I

TA IMJMNI

0

I
ADDRESS STATUS

I

0

I

S8

I

TO

I

IDMAOIDMAII SPC I LLOC IREMC I ADScl
I
INTERRUPT ENABLE 2

I RSV I

0

LO
I

sa

I

I

S3
SS
S4
I
I
SERIAL POLL MODE

0

I I I 0
ADDRESS MODE

S2
I

I

S1
I

IADM1 IADMO\

COMMAND PASS THROUGH

ADDRESS 0/1

1 I EC7IEca\ECS\ EC41 EC31 EC2 I EC1
ADDRESS 1

I

ECO I

EOS

Figure 3.

8291A REGISTERS

10-119

230832-001

inter

AP-166

Address Mode
The address mode and status registers are used to
program the addressing modes and track addressing
states. The auxiliary mode register is used to select a
variety of functions. The command pass through register
is used for undefined commands and extended addresses.
The address 0/ I register is used to program the addresses
to which the 8291A will respond. The address 0 and

J. MODE:

address I registers allow reading of these programmed
addresses plus trading of the interrupt bit. The EOS
register is used to program the end of sequence character.
Detailed descriptions of the addressing modes available
with the 8291A are described in the 8291A data sheet.
Examples of how to program these modes are shown
below.
-

- Talker has single address of 01 H
- Listener has single address of 02H

CPU WRITES TO:

PATTERN

COMMENT

Address Mode Register
Address 0/1 Register
Address 0/1 Register

00000001
00100001
1100 0010

Select Mode I Addressing
Major is Talking. Address =01 H
Minor is Listener. Address =02H

2. MODE:

- Talker has single address ofOIH
- Listener has single address of 02H

CPU WRITES TO:
Address Mode Register
Address 0/1 Register
Address 0/1 Register

PATTERN

COMMENT

00000001
0100 0010
1010 0001

Select Mode I Addressing
Major is Listener. Address =02H
Minor is Talking~ Address =OIH

Note that in both of the above examples, the listener will respond to a MLA message with five least significant bits equal
to 02H and the talker to a 01 H.
3. MODE:

- Talker and listener both share a single address of 03H.

CPU WRITES TO:

PATTERN

COMMENT

Address Mode Register
Address 0/1 Register
Address 0 fI Register

00000001
00000011
11100000

Selects Mode I Addressing
Talker and Listener Address = 03
Minor Address is disabled

4. MODE:

- Talker and listener have a primary address of 04H and a secondary address of 05H

CPU WRITES TO:

PATTERN

Address Mode Register
Address 0/1 Register
Address 0/1 Register

00000010
00000100
10000101

5. MODE:

COMMENT
Selects Mode 2 Addressing
Primary Address = 04H
Minor Address is disabled

- Talker has a primary address of 06H. Listener has a primary address of 07H

CPU WRITES TO:
Address Mode Register
Address 0/1 Register
Address 0/1 Register

COMMENT

PATTERN
00000011
0010 0110
1100 0111

Select Mode 3
Talker Address = 06
Listener Primary = 07

The CPU will verify the secondary addresses which could be the same or different.

10-120

230832--001

AP-166

not respond to the My Listen Address (MLA) message
from the controller. The sequence of events is as follows:

APPLICATION OF THE 8291A
. This phase of the application note will examine programming of the 8291A, corresponding bus' commands and
responses; CPU interruption, etc. for a variety of GPIB
activities. This should provide the reader with a clear
understanding ofthe role the 8291A performs in a GPIB
system. The talker function, listener function, remote
message handling, and remote / local operations including
local lockout, are discussed.

I) The Interrupt Enable registers are programmed.
2) Lon is selected.
3) EOS characted is programmed.
4) "Pon" local message is sent.
5) CPU waits for BI and reads the byte from the
data-in register.
Note that enabling both ton and Ion can create an internal
loopback as long as another listener exists.

Talker Functions
TALK-ONLY (ton). In talk only mode the 8291A will not
respond to the MTA message from a controller. Generally, ton is used in an environment which does not have a
controller. Ton is also employed in an interface that
includes the controller function.
When the 8291A is used with the 8292, the sequence of
events for initialization are as follows:
I) The Interrupt/ Enable registers are programmed.
2) Ton is selected.
3) Settling time is selected. .
4) EOS character is loaded.
5) "Pon" local message is sent.
6) CPU waits for Byte Out (BO) and sends a byte to
the data out register.

Addressed Talker (Via MTA Message)
TheGPIB controller will direct the 8291A to talk by
sending a My Talk Address (MTA) message containing
the 8291A's talk address. The sequence of events is as
follows:
I) The interrupt enable and serial poll mode registers
are programmed.
2) Mode I is selected.
3) Settling time is selected.
.
4) Talker and listener addresses are programmed.
5) Power on (pon) local message is sent.
6) CPU waits for an interrupt. When the controller has
sent the MTA message for the 8291A an interrupt
will be generated if enabled and the ADSC bit will
be set.
7) CPU reads the Address Status register to determine
if the 8291A has been addressed to talk (TA = I).
8) CPU waits for an interrupt from either BO or
ADSC.
9) When BO is set, the CPU writes the data byte to the
data out register.
10) CPU continues to poll the status registers.
II) When unaddressed ADSC, will be set and TA reset.

LISTENER FUNCTIONS
. LISTEN-ONLY (Ion). In listen-only mode the 8291A will

Addressed Listening
(Via the MLA Message)
The GPIB controller will direct the 8291A to listen by
sending a MLA message containing the 8291A's listen
address. The sequence of events is as follows:
I) The Interrupt Enable registers are programmed.
: 2) The serial poll mode register is loaded as desired.
3) .Talker and listener addresses are loaded.
4) "Pon" local message is sent
5) The CPU waits for an Interrupt. When the controller
has sent the MLA message for the 8291A, the
ADSc: bit will be set.
6) The CPU reads the Address Status Register to
determine if the 8291A has been addressed to listen
(LA = I).
7) CPU waits for an interrupt for BI or ADSC.
8) When BI is set, the CPU reads the data byte from
the data-in register.
9) The CPU continues to poll the status registers.
10) When unaddressed, ADSC will be set and LA reset.

Remote/Local and Lockout
Remote and local refer to the source of control of a device
connected to the GPIB. Remote refers to control from
the GPIB controller-in-charge. Local refers to control
from the device's own system. Reference should be made
to the RL state diagram in the 8291A data sheet..
Upon "pon"the 8291Ais in the local state. In this state the
REM bit in Interrupt Status I Register is reset. When the
GPIB controller takes control of the bus it will drive the
REN (remote enable) line true. This will cause the REM
bit and REMC (remote/local change) bit to be set. The
distinction between remote and local modes is necessary
in that some types of devices will have local controls
which have functions which are also controlled by remote
messages.
In the local state the device is allowed to store, but not
respond to, remote messages which control functions
which are also controlled by local messages. A device

10-121

230832-001

AP-166

Polling

which has been addressed to listen will exit the local state
and go the the remote state if the REN message is true and
the local rtl (return to local) message is false. The state of
the "rtl" local message is ignored and the device is
"locked" into the local state if the LLO remote message is
true. In the Remote state the device is not allowed to
respond to local message which control function that are
also controlled by remote messages. A device wil exit the
remote state and enter the local state when REN goes
false. It will also enter the local state if the GTL (go to
local) remote message is true 'and the device has been
addressed to listen. It will also enter the local state if the
rtl message is true and the LLO message is false or ACDS
is inactive.

Serial Poll

A device will exit the remote state and enter R WLS
(remote with lockout state) if the LLO (local lockout)
message is true and ACDS is active. In this mode, those
local message which control functions which are also
controlled by remote messages are ignored. In other
words, the "rtl"; message is ignored. A device will exit
R WLS and to to the local state if REN goes false. The
device will exit RWLS and go to LWLS if the GTL
message is true and the device is addressed to listen.

When the controller performs a Serial Poll, each slave
device sends back to the controller a Serial Poll Status
Byte. One of the bits in the Serial Poll Status Byte
indicates whether this device requested service or not.
The remaining 7 bits are user defined, and they are used
to indicate what type of service is required. The IEEE-488
spec only defines the service request bit, however HP has
defined a few more bits in the Serial Poll Status Byte.
This can be seen in figure 4.

rl
8

7

L.-_ _

I

1
:

6

SERVICE REQUESTED'

•

•

•

•

DEVICE DEPENDENT STATUS BITS

110:
7

These two methods are called Serial and Parallel Poll.
The controller performs one of these two polli.ng methods
after a slave device requests service. As implied in the
name, a Serial Poll is when the controller sequentially
asks each device if it requested service. In a Parallel Poll
the controller asks all of the devices on the GPIB if they
requested service, and they reply in parallel.

0: SERVICE NOT REQUESTED

TYPICAL HP U~ 1:

8

The IEEE-488 standard specifies two methods for a slave
device to let the controller know that it needs service.

•

~

SERVICE REQUESTED
SERVICE NOT REQUESTED

6

NOT USED

5

4

Y

•

•

L
·

DEVICE DEFINED
1: OPERATION COMPLETE
0:

11:

L..-------i

0:

Figure 4.

•

BUSY
ERROR
NORMAL

The Serial Poll Status Byte

10-122

230832-001

AP-166
When a slave device needs service it drives the SRQ line
on the GPIB bus true (low). For the 8291A this is done by
setting bit 7 in the Serial Poll Status Byte. The CPU in the
controller may be interrupted by SRQ or it may poll a
register to determine the state of SRQ. Using the 8292 '
one could either poll the interrupt status register for the
SRQ interrupt status bit, or enable SRQ to interrupt the
CPU. After the controller recognizes;l service request, it
goes into the serial poll rQutine.
The first thing the controller, does in the serial poll routine
is assert ATN. When ATN is asserted true the controller
takes control of the GPIB, and all slave devices on the
bus must listen. All bytes sent over the bus while ATN is
true are commands. After the controller takes control, it
sends out a Universal Unlisten (UNL), which tells all
previously addressed listeners to stop listening. The controller then sends out a byte called SPE (Serial Poll
Enable). This command notifies all of the slaves on the
bus that the controller has put the GPIB in the Serial Poll
Mode State (SPMS). Now the, c;ontroller addresses the
first slave device to TALK and puts itself in the listen
mode. When the controller resets ATN the device,
addressed to talk transmits to the controller its Serial
Poll Status Byte. If the device just polled w~s the one
requesting'service, the SRQ line on the GPIB goes false,
and bit 7 in the serial poll status byte ofthe 8291A is reset.
If more than one device is requesting service, SRQ,
remains low until all of the devices requesting service
have been polled, since SRQ is wire-ored. To continue the
Serial Poll, the controller asserts ATN, addresses the next
device to talk then reads the Serial Poll Status Byte.
When the controller is finished polling it asserts ATN,
sends the universal untalk command (UNT), then sends
the Serial Poll Disable command (SPD). The flow of the
serial poll can be seen from the example in figure 5.
O. DEVICE A REQUESTS SERVICE (SRQ)
1. ASSERT ATN
2. UNIVERSAL UNLISTEN (UNL)
3. SERIAL I8PLL ENABLE (SPE)
4. DEVICE A TALK ADDRESS (MTA)
5. RELEASE ATN
6. DEVICE A STATUS BYTE (STB) (RQS SET)
7. ASSERT ATN
8. DEVICE B TALK ADDRESS (MTA)
9. RELEASE ATN
O. DEVICE B STATUS BYTE (STB) (RQS CLEAR)
1. ASSERT ATN
2. DEVICE C TALK ADDRESS (MTA)
3. RELEASE ATN
4. DEVICE C STATUS BYTE (STB) (RQ~ CLEAR)
5. ASSERT ATN
6. UNIVESAL UNTALK (UNT)
7. SERIAL POLL DISABLE (SPD)
8. GO PROCESS SERVICE REQUEST

FIgure 5.

Serial Polllng

The following section describes the events which happen
in a serial poll when'8291A and 8292 are the controller,
and another 8291A is the slave device. While going
through this section the reader should refer to the register
diagrams for the 8291A and 8292.

A. DEVICE A REQUESTS SERVICE
(SRQ BECOMES TRUE)
The slave devices rsv bit in the 8291A's serial poll mode
register is set.

B. CONTROLLER RECOGNIZES SRQ
AND ASSERTS ATN
Thf 8292's SPI pin 33 interrupts the CPU. The CPU
reads the 8292's Interrupt status register and finds the
SRQ bit set. The CPU tells the 8292 to 'Take Control
Synchronously' by writing a OFDH to the 8292's command register.

C. THE CONTROLLER SENDS OUT THE
FOLWWING COMMANDS: UNIVERSAL
UNLISTEN (UNL), SERIAL POLL ENABLE
(SpE), MY TALK ADDRESS (MTA).
(MTA is a command which tells one of the devices on the
bus to talk.)
The CPU in the controller waits for a BO (byte out)
interrupt in the 8291 A's interrupt status I register before
it writes to the Data Out register a 3FH (UNL), 18H
(SPE), OIOXXXXX (MTA). The X represents the programmable address of a device on the GPIB. When the
8291A in the slave device receives its talk address, the
ADSC bit in the Interrupt Status register 2 is set, and in
the Address Status Register TA and TPAS bits are set.

D. CONTROLLER RECONFIGURES ITSELF
TO LISTEN AND RESETS ATN
The CPU in the controller puts the 8291A in the listen
only mode by writing a 40H to the Address Mode register
ofthe 8291A, and then a OOH to the Aux Mode register.
The second write is an 'Immediate Execute pon' which
must be used when switching addressing modes such as
talk only to listen only. To reset ATN the CPU tells the
8292 to 'Go To Standby' by writing a OF6H to the command register. The moment ATN is reset, the 8291A in
the slave device sets SPAS in Interrupt Status 2 register,
and transmits the serial poll status byte. SRQS in the
Serial Poll Status byte of the 8291 A slave device is reset,
and the SRQ line on the GPIB bus becomes false.

E. THE CONTROLLER READS THE SERIAL
POLL STATUS BYTE, SETS ATN,
THEN RECONFIGURES ITSELF TO TALK
The CPU in the controller waits for the Byte In bit (BI) in
the 8291 A's Interrupt Status I register. When this bit is set
the CPU reads the Data In register to receive the Serial
Poll Status Byte. Since bit 7 is set, this was the device
which requested service. The CPU in the controller tells
the 8292 to 'Take Control Synchronously' which asserts
ATN. The moment ATN is asserted true the 8291A in the
slave device resets SPAS, and sets the Serial Poll Com-

10-123

230832-001

AP-166

plete (SPC) bit in the Interrupt Status 2. register. Th.~
controller reconfigures itself to talk by settmg the TO bit
in the Address Mode register and then writing a OOH to
the Aux Mode register.
F, THE CONTROLLER SENDS THE

COMMANDS UNIVERSAL UNTALK (UNT),
AND SERIAL POLL DISABLE (SPD) THEN
RESETS THE SRQ BIT IN THE 8292
INTERRUPT STATUS REGISTER
The CPU in the controller waits for the 80 Interrupt
status bit to be set in the Interrupt Status I register of the
8291A before it writes 5FH (UNT) and 19H (SPD) to the
Data Out register. The CPU then writes a 28H to the
8292's command register to reset the SRQ status bit in the
Interrupt Status register. When the 8291A in the slave
device receives the UNT command the ADSC bit in the
Interrupt Status 2 register is set, and.the TA and TPAS
bits in the Address Status register will be reset. At this
point the controller can service the slave device's request.
Note that in the s~ftware listing of AP-66 (USING THE
8292 GPIB CONTROLLER) there is a bug in the serial
poll routines. In the 'SRQ ROUTINE' when the CPU
finds that the SRQ bit in the interrupt status register is
set, it immediately writes the interrupt Acknowledge
command to the 8292 to reset this bit. However the SRQ
GPIB line will still be driven true until the slave device
driving SRQ has been polled. Therefore, the SRQ status
bit in the 8292 will become set and latched again, and as a
result the SRQ status bit in the 8292 will still be set after
the serial poll. The proper time to reset the SRQ bit in the
8292 is after SRQ on the GPIB becomes" false.

Parallel Poll
The 829lA supports an additional method for obtaining
status from devices known as parallel poll (PPOL). This
method limits the controller to a maximum of8 devices at "
a time since each device will produce a single bit response
on the GPIB data lines. As shown in the state diagrams,
there are three basic parallel poll sates: PPIS (parallel poll
idle state), PPSS (parallel poll standby state), and PPAS
(parallel poll active state).
In PPIS, the device's parallel poll function is in the idle
state and will not respond to a "parallel poll. PPSS is the
standby state, a state in which the device will respond to a
parallel poll from the controller. The response is inititated
by the controller driving both ATN and EOI true
simultaneously.
The 829lA state diagram shows a transition from PPIS
to PPSS with the "lpe" message. This is a PP2 implementation fora parallel poll. This "Ipe" (local poll enable)
local message is achieved by writing 01lUSP3P 2P 1to the
Aux Mode Register with U=O. The S bit is the sense bit. If
the "ist" (individual status) local message value matches
the sense bit, then the 8291 A will give a true response to a

parallel poll. Bits P 3-P I identify which data line is used for
a response.
For example, assume the programmer decides that the
system containing the 8291A shall participate in parallel
poll. The programmer, upon system initialization would
write to the Aux Mode Register and reset the U bit and
set the S bit plus identify a data line (PrP I bits). At "pon,"
the 829lA would not resond true to a parallel poll unless
the parallel poll flag is set (via Aux Mode Register
command).
When a status condition in the user system occurs and the
programmer decides that this condition warrants a true
response, then programmers software should set the
parallel poll flag. Since the S bit value matches the "ist"
(set) condition a true response will be given to all parallel
polls.
An additional method of parallel polling reading exists
known as a PPI implementation. In this case the
controller sends a PPE (parallel poll enable) message:
PPE cont ains a bit pattern similar to the bit pattern used
to program the "lpe" local message. The 8291A. will
receive this as an undefined command and use It to
generate an "lpe" message. Thus the "controller is specifying the sense bits and data lines for a response. A PPD
(parallel poll disable) message exists which clears ~he bits
SP3P 2P 1 and sets the U bit. This also will be received by
the 829lA and used to generate an "lpe" false local
message.
The actual sequence of events is as follows. The controller
sends a PPC (parallel poll configure) message. This is an
undefined command which is received in the CPT register
and the handshake is held off. The local CPU reads this
bit pattern, decodes it, and sends a VSCMD message to
the Aux Mode Register. The controller then sends a ppe
message which is also recieved as a undefined command
in the CPT register. The local CPU reads this,"decodes it
clears the MSB, and writes this to the Aux Mode Register
generating the "Ipe" message.
The controller then sends ATN and EOI true and the
8291 A drives the appropriate data line if the "ist" (parallel
poll flag) is true. The controller will then send a PPD
(paralh~1 poll disable) message (again, an undefined
command). The CPU reads this from the CPT register
'and uses it to write a new "Ipe" message (this "lpe"
message will be false). The' controller then sends a PPU
(parallel poll unconfigure) message. Since this is also an
undefined command, it goes into the CPT register. When
the local CPU decodes this," the CPU should clear the ,
"ist" (parallel poll flag).

APPLICATION EXAMPLES
In the course of developing this application note, two
complete and identical GPIB systems were built. The

10-124

230832-001

AP-166

schematics and block diagrams are contained in Appendix I. These systems featu~ an 8088 CPU, 8237 'DMA
controller,serial I/O (8251A and 8253),RAM, EPROM,
and a complete GPIB 'talker/ listener controller. Jumper
switches were provided to select between a controller
function and a talker/listener function. This systeni
design is based on the design ofIntel'sSDK-86 prototyp~
ing kit and thus shares "the same I/O and memory
addresses. This system uses the same download software
to'transfer object files from Intel developmen(systems.

Two Software Drivers
Two software drivers were developed to demonstrate a
ton/Ion environment. These two programs (BOARD I
and BOARD 2) are contained in Appendix 2.
In this example, one of the systems (BOARD I) initially is
programmed in talk-only mode and synchronization is
achieved by waiting for the listening board to become
active. This is sensed by the lack of a GPIB error sinc~ a
condition of no active listener produces an ERR status
condition. Board I upon detecting the p,resence of an
active listener transmitts a block of 100 bytes from a
PROM memory across the bus. The second system
(BOARD 2) receives this data and stores it in a buffer,
EOI is sent true by the talker (BOARD I) with the last
byte of ditta. Upon detectign of EOI, BOARD 2 switches
to the talk only mode while BOARD I upon terminal
count switches to the listen orily mode. BOARD 2 then
detects the presence of an active listener and transniitts
the contents of its buffer back to BOARD I which stores
this data in the buffer. EOI again is sent with ,the last byte
and BOARD 2 switches back to listen-only. BOARD I
upon detecting EOI then compares the contents of its
buffer with the contents of its PROM to erisure that no
data transmission errors occured. The process then
'
repeats itself.

8291 A with HP 9835A
An example of the 8291 A used in, conjunction with a b,us
controller is also included in this application note. In this
example, the 8291A system used in previous experiments
was connected via the G PIB to a Hewlett-Packard 9835A
desktop computer. This' computer contains, in addition
to a GPIB interface, a black a.nd white CRT, keyboard,
tape drive for high quality data cassettes, and a calculator
type printer. The software for' the HP 9835A is shown in
Appendix 3. The user should refer to the operation manuals for the HP 9835A for information on the features
and programming methods for the HP 9835A.
In this example, the 8292 was removed from its socket
arid the OPTA and OPTB pins of the two 8293 transceiver reconfigured to modes 0 and I. Optionally, the
mode pins could have been left wired for modes, 2 and 3
and the 8292 left in its socket with its SYC pin wired to
ground. This would have produced the same effect.

The first action performed is sending IFC. Generally, this
is done when a controller first comes on line. This pulse is
at least 100 us in duration as specified by the IEEE-488
standard.
The software checks to see if active listeners are on line.
For demonstration purposes, the HP 9835A will flag the
operator to indicate that listeners are on line.
The HP 9835Ath~nconfigures and performs a parallel
poll (PPOL). The parallel poll indicates I bit of status of
each device in a group of up to ~ devices. Such information could be used by an application program to determine whether optional devices are part of a system configuration: Such optional devices might include mass
storage devices, printers, etc. where the application software for the controller might need to format data to
match each type of device. Once the PPOL sequence is
finished, the HP 9835A offers the user the opportunity to
execute user commands from the keyboard. At this time
the HP 9835A sits in a loop waiting for an SRQ condition. When the operator hits a key on the keyboard, the
HP 9835A processor is, interrupted and vectors to a
service routine where the key is read and the appropriate
routine is executed. The H P 9835A will then return to the
loop checking for SRQ true. For this application, the
valid keys are G,D,R,H,and X. Pressing the "G" key
causes the GET command to be sent across the bus. A
message to this effect is printed in the CRT and the HP
9835A returns. The "D" key causes the SDC message to
be sent with the 8291A being the addressed device. Again,
an appropriate message is output on th HP 9835A CRT.
The "R"keycauses the GTLmessage to be sent. The CRT
displays "REMOTE MESSAGE SENT." The "H" key
causes a menu to be displayed on the HP 9835A CRT
screen. This menu lists the allowed commands and their
functions. NO GPIB commands are sent. The "X" key
allows the operator to send one line of data across 'the
bus. The line of data is terminated by a carriage return
and line feed produced by pressing the "CONTINUE"
key on the HP 9835A.
The characters are stored in the sequence entered into a'
buffer whose maximum size is 80 characters. Pressing the
"CONTINUE" key terminates storing characters in the
array and all characters including the carriage return and
Iindeed are sent. EOI is then sent true with a false byte of
OOH. This false byte is due to the 1975 standard which
allows asyncronous sending and reception of EOL (The'
8291 A supports the later 1978 standard which eliminates
'
this false byte).
After any key command is serviced control returns to the
loop which checks for SRQ active. Should SRQ be
active, then the keyboard interrupt is disabled and a
message printed to indicate that SRQ has been received
true.
The controller then performs

a parallel'poll.

This is an example of how parallel poll may be used to

10-125

230832-001

AP-166

quickly check which group of devices contains a device
sending SRQ. The eight devices in a group would, of
course, have software drivers which allow a true response
to a PPOL if that device is currently driving SRQ true.
This would be a valuable method of isolation of the SRQ
source in a system with a large number of devices. In this
application program, only the response from the 8291A
is of concern and only the 8291 A's response is considered.
It does, however, demonstrate the technique employed. If
a true response from the 8291A is detected, then a message to this effect is printed on the HP 9835A CRT
screen. From this process, the controller has identified the
device requesting service and will use a serial poll(SPOL)
to determine the reason for the service request. This
method of using PPOL is not specifically defined by the
IEEE-488 standard but is a use of the resources provided.
The controller software then prints a message to indicate
that it is about to perform a serial poll. This serial poll will
return to the controller the 'current status of the 8291A
and clear the service request. The status byte received is
then printed on the CRT screen of the HP 9835A. One of
the 8291 A status bits indicates that the 8291A system has
a field (on line or less) of data to transfer to the HP
9835A. If this bit is set, then the HP 9835A addresses the
8291A system to talk. The data is sent by the 8291A
system is then printed on the CRT screen of the HP
9835A. The HP 9835 then enables the keyboard interrupts
and goes into its SRQ checking loop.
Appendix 4 contains the software for the 8291A system
which is connected to the HP 9835A via the GPIB. This
software throws away the first byte of data it receives
since this transfer was used by the HP 9835A to test when
the 8291A system came on line.
Next, both status registers are read and stored in the two
variable STAT I and STAT 2. It is necessary to store the
status since reading the status registers clears the status
bits.
Initially, six status bits are evaluated (END, GET, CPT,
DEC, REMC, ADSC). Some of these conditions require
that additional status bits be evaluated.
If END is true, then the 8291A system has received a
block from the HP 9835A and the contents of a buffer is
printed on the CRT screen. Next, the CPT bit is checked.
PPC and PPE are the only valid undefined commands in
this example.

Address Status 'Change (ADSC) is checked to see if the
8291A has been addressed or unaddressed by the con-,
troller. If ADSC is false, then the software checks the
keyboard at the CRT terminal. If ADSC is set, then the
TA and LA bits are read and evaluated to determine
whether the 8291 A has been addressed to talk or listen.
The DMA controller is set to start transfers at the start of
the character buffer and the type oftransferis determined
by whether the 8291A is in TADS or LADS. We only
need to set up the DMA controller since the transfers will
be transparent to the system processor. The keyboard
from the CRT terminal is then checked. If a key as been
hit, then this character is stored in the character buffer
and the buffer printer set to the next character location.
This process repeats until the received character is a line'
feed. The line feed is echoed to the CRT, the serial poll
status byte updated and the SRQ line driven true. This
allows the 8291A system to store up to one line of characters before requesting a transfer to the controller. Recall
that upon receiving an SRQ, the controller will perform a
serial poll and subsequently address the 8291 A to talk.
The 8291 A system then goes back to reading the status
register thus repeating the process.

CONCLUSION
This application note has shown a basic method to view
the IEEE 488 bus, when used in conjunction with Intel's®
8291A.
The main reference for GPIB questions is the IEEE
Standard 488 - 1978. Reference 8291 A's data sheet for,
detailed information on it.
Additional lntel® GPIB products include iSBX-488,
which is a multimode board consisting of the 8291A,
8292, and 8293.

REFERENCES
8291A Data Sheet
8292 Data Sheet
8293 Data Sheet
Application Note #66 "Using the 8292 GPIB Controller"
PLM-86 User Manual
HP 9835A User's Manual
IEEE-488-1978,Standard

Next, the GET bit is examined and if true, the CRT
soreen connected to the serial channel on the 8291A
system prints a message to indicate that the trigger command has been received. A similar process occurs with
the DEC and REMC status bits.

10-126

230832-001

~

APPENDIX 1
SYSTEM BLOCK DIAGRAM WITH 8088

CLOCK
GEN.

CPU

:.-

~

~

~

.!.o.

en
en

I\)
-..j

GPIB

~

~

'l'

~

inter

Ap·166

APPENDIX 2
SOFTWARE DRIVERS FOR BLOCK DATA TRANSFER

PL/M-86 COMPILER

BOARD I

ISIS-II PL/M-86 VI.
CoMPILATIUN OF MODULE BOARD 1
OBJECT MODULE PLACED IN
Fl.
BRDI
OB~
COMPILER ItNoKED SY:
PU186.
F1:
BRDl.
SRC SYMBOLS MEDIUM
1*
1*
1*
1*
1*
l*
!*

1*
;1*
1*
1*
1*
1*
1*
1*

BOARD
TPT PROGRAM
*1
THIS BO~RD TALKS TO THE OTHER BOARD BY *;
TRANSFERRING A BLOCK OF DATA VIA THE 8237 *1
COUPLED WITH THE 8291A
THE 8291A IS PROGRAM- *1
MED TO SEND EOI WHEN RECOGNIZING THE LAST
*1
DATA BiTE'S BIT PATTERN.
I~HILE DATA IS BEING *1
TRANSFERRED. THE PROCESSOR PERFORMS liD READS *1
OF THE 8237 COUNT REGlSTERS TO SIMULATE BUS
*1
ACTIVITv'. AND TO DE1ERMINE WHEN TO TURN THE
.,
LWE AROUND. Ar.-TER THE 8237 HAS REACHED .,.;
TERMINAL COUNT, THE 8291A IS PROGRAMMED TO
*1
THE LlSTEt.ER STATE At.D WAITS FOR THE BLOCK
*1
TO BE TRANSMITTED PACK FROM THE SECOND BOARD *1
THIS DATA IS PLACED IN A SECOND BUFFER AND
*1
ITS CONTENTS COMPARED WITH THE ORIGINAL DATA *1
TO CHECK FOR INTERFACE INTEGRITY.
*1

BOARD 1 :
DO;
1* PROCEDURES *1

2
3

4
5
6
7

CO:
2

;2

3
2
2

PROCEDURE (XXX)
DECLARE XXX BYTE,
SER$STAT LITERALLY
·OFFF2H'.
SER$DATA LITERALLY
'OFFFOH',
TXRDY
LITERALLY
'OIH',
DO I~HILE (INPUT
LSTN
POINTER;

14

DECL/,RE
LITERALLY '48H',
RD$TRANSFER
LITERALLY '44H',
WR$TRANSFER
LITERALLY '20H',
NORM$TIME
LITERALLY 'OFFH',
TC$LOl
LITERALLY 'OOH',
TC$HI t
LITERALLY '99D',
TC$L.02
LITERALLY 'OlH',
TC
BYTE,
I

15

1* 100 XFERS

*1

DECLARE
Dt1A$~mD$T",U<'
Dt1A$l~RO$LSTN

(2)

(2)

l~ORD

HORD

AT
AT

(@DMA$ADR$TALK ) ,
(@DMA$ADR$LSTN) ;

1* 8291A PORT ADDRESSES *1

16

DECLARE
PORT$OUT
PORT$IN
STATUS$l
STATUS$2
ADDR$STATUS
COt1MAND$t10D
ADDR$O
EOS$REG

l.ITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY

10-129

'OFFCOH' ,
'OFFCOH'
'OFFC1H' ,
'OFFC2H' ,
'OFFC4H' ,
'OFFC5H' ,
'OFFC6H',
'OFFC7H' ,

1* DATA OUT*I

I*INTR STAT 2iU
1* INTR STAT 2 *1
1·"CI'1D PASS THRU *1
1*

EOS REGISTER *1

230832-001

inter

AP-166

/* 8291A COMMAND

PL/M-86 COMPILER

- DATA BYTES */

BOARDI
DECL,\RE

17

'B8H',
END$EOI
LITERALLY
'IOH' ,
DNE LITERALLY
'DOH',
PON LITERALLY
'02H',
RESET
LITERALLY
'OOH'I
CLEAR
LITERALLY
'10H' ,
DMA$REQ$L LITERALLY
'20H / ,
DMASREG$T LITERALLY
'80H',
MOD1$TO
LITERALLY
MODI$LO
LITERALLY
'40H "
'ODH' ,
EOS LITERALLY
'23H' ,
PRESCALER LITERALLY
'OA4H',
HIGH.SPEED LITERALLY
'OFFFFH' ,
OKAY
LITERALLY
XYZ BYTE,
MATCH
\~ORD,
'02H',
BO
LITERALLY
'OlH' ,
B1
LITf::RALLY
'04H' ;
ERR L.ITERALLY

1* CODE ,BEGINS *1
18

START91:
OUTPUT

(STATUS$2)

=CLEAR;

1* SHUT-OFF OMA REG BITS TO *1
1* PREVENT EXTRA DMA REGS *1
/*FROM 8291A

1* MANIPULATE DMA ADDRESS VARIABLES */

DMA$ADRSYALK
=(@BUFF1);
DMA$ADR$LSTN
=(@BUFF2);
OMA$WRD$TAU, ( 1 ) =SHL (DMA$WR D$ TALK ( 1 ), 4);
Dr1A$WRO$TALK (0) -DMA$\~RD$TALK (0) + OMA$WRD$TALK (1);
DMA$WRO$LSTN(I)=SHL (DMA$WRD$LSTN (1), 41;
DMASWRO$LSTN(OI=DMA$WRD$LSTN (01 +OMA$WRO$LSTN (II;

19
20

21
22

23
24
25

INIT3Ti .

I- INIT 8237 FOR TALKER FUNCTIONS *1
26
27
2a
29

30
31
32
33
PL/M-86 COMPILER

OUTPUT
(CLEAR$FF)
OUTPUT
(CMD$37)
OUTPUT
(SET$MODE)
OUTPUT
(SET$MASK)
OUTPUT
(START$O$LOI
DMA$\4RO$TALK (0)
OUTPUT
(START$O$HI)
OUTPUT
(O.COUNT$LOI
OUTPUT
(O.COUNT$HI)
/- INIT 8291A FOR TALKER

=CLEAR;/* TOGGLE MASTER CLEAR *1
=NORM$TIME;
=RD$TRANSFER;
-CLEAR;
=DMA$WRD$TALK (Oli
=SHR (Dt1A$WRD$TALK (0), ali
=DMA$WRD$TALK (01;
=TC$L02;
=TC$HI2;
FUNCTIONS -/

BOARD1

10-130

230832-001

inter

AP-166

OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

34
35
36
37
38
39
40
41
42
43
44
45
46
47

DO I~HILE (INPUT
CSTATUS$l) AND So)
END;
1* WAIT FOR ao INTR *1
OUTPUT
(PORT$OUT)
= OAAH;

2

3
2
2

OUTPUT

,:.,TATUS$2)

=D~lA$RE(l$T;

DO WHILE
(INPUT
(CMD$37)
1* WAIT FOR TC = 0 *1
END.

49
2

ENAaLE Dt~A REGS *1

i*

AND TC)

OUTPUT
/ ..

TC,

(STATUS$2)

=CLEAR.

I'~

DISABLE DMA REGS *1

INIT 8237 FOR L.ISTENER FUNCTIONS *1

OUTPUT
(CLEAR$FFI O=CL~ARi !.
TOGGLE MASTER RESET *1
OUTPUT
(CMD$37)
=NORM$TIME,
OUTPUT
(SET$MODE)
=I.R$TRANSFER,
OUTPUT
(SET$MASK)
=CLEAR.
OUTPUT
(SlART$O$LO)
=DMA$WRD$LSTN (0),
DMA$WRD$LSTN (0)
=SHR (DJ1A$WRD1LSTN (0). 8).

2

OUTPUT
59
60

(START $O$HI)
=DMA$WRD$LSTN (0),
OUTPUT
(o"COUNT$LO)
=TC$LO 1;
OUTPUT
(O$COUNT~HI)
=TC$HI1;

1* INIT 8291A FOR LISTENER FUNCTIONS
OUTPUT
OUTPUT
OUTPUT

61
62
63
64
65
66

C>

INIT37L,

51

52
53
54
55
56
57
58

=0;

DO WHILE
(INPUT
(STATUS$l) AND, ERR) = ERR;
DO I.HILE
(INPUT
(STATUS$1)
AND ao) =' 0,
END,
1* I~AIT FOR ao ItHR *1
OUTPUT
(PORT$OUT)
=OAAH,
END;

1

2

48

50

(EOS$REG)
=EOS;
=END$EOL 1*
EOI ON EOS SENT *1
(Cot1MAND$MOD)
=MOD1$TO; 1* TALK ONLY *1
(ADDR$STATUS)
=PRESCALER.
(C ot1MAND$MOD)
( Cot1t1Ar~D$t10D )
"HIGH$SPEED;
(C OMMAt-JD$MOD)
=PON,

1
2
1

(COMMAND$MOD)
(ADDR$STATUS)
(COMMAND$r10D)

=RESET.
=MOD1$LO,
=PON,

1*

DO WHILE (INPUT
(STATUS$l)
AND aI)
END,
1* WAIT FOR aI INTR *1
XYZ
INPUT (PORT$IN),
(STATUS$2)

=DMA$REG$L,

1*

*1
LISTEN ONLY *1

=0,

67

OUTPUT

68

bo WHILE
(INPUT
(STATUS$l)
AND DNE)(>
1* WAIT FOR EOI RECEIVED *1

10-131

ENAaLE DMA REGS

''''1

ONE,

230832-{)Ol

AP-166

PL/M-86 COMPILER

70

BOARD

CMPBLI',E;·
i*

CC!~Pp.RE

11ATCH=CMPB
71

IF t1ATCH
!#

73
74
75

MODULE

THE HJO BIJFFERS CONTENTS *1
(@BUFF1.

100»)

OKAY THEN GOTO START91)

SEND ERROR MESSAGE IN BUFFER 3

DO 1=0 TO 16)
CALL CO
(BUFF 3
END;

1
2
2

@BUFF2.

76

GOTO START91;

77

Et,lD;

( II

*/

);

It~FORMATION:

CClDE AREA SIZE
CONSTANT AREA SIZE
VARIABLE AREA SIZE
MAXIMUM STACK SIZE
243 LINES READ
o PROGRAM ER~OR (8)
END OF PL/t1-86

=OlDBH

4750

=0075H
=0070H

1170
1120

=OOO4!lH

60

COMPILATION

10-132

J

230832-001

inter.

AP-166

PL/M-86 COMPILER

BOARD2

ISIS-II PL/M-86 VI. 1 CDr1PILATION OF MODULE BOARD2
OBJECT MODULE PLACED IN
Fl: BRD2, OBJ
PLM86 :Fl:
BRD2, SRC
COMPILER INVOKED· BY:
I~
I~

1*
1*
1*
1*
,1*
1*
1*

BOARD 2 TPT PROGRAM
*1
*1
THIS BOARD LISTENS TO THE OTHER BOARD (1)
*1
AND DMA'S DATA INTO A BUFFER, WHILE WAITING *1
FOR THE END INTERRUPT BIT TO BECot1E ACTIVE *1
UPON END ~\CTIVE, THE DATA IN THE BUFFER IS *1
SENT BACK TO THE FIRST BOARD VIA THE GPID
*1
WHEN THE BLOCK IS FINISHED THE 8291A IS *1
PROGRAMMED BACK INTO THE LISTENER MODE
*1

BOARD2:
DO;

1* 8237 PORT ADDRESSES *1
2

DECLARE
CLEAR$FF
START$O$Lo
START$O$HI
O$COUNT$LO
O$COUNT$HI
SET$MODE

LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY

Ct1D$.37

SEHMASK

1* 8237 CUMMAND
3

- DATA BYTES

I*MASTER CLEAR *1

*1

DECLARE
RD$TRANSFER
l_lTERALLY
WR$,TRANSFER
LITERALLY
ADDR$lA
LITERALLY
ADDR$lB
LITERALLY
NORf1$TIME
LITERALLY
TC$LOI
L_ITERALLY
l_ITERAlLY
TC$HII
l_ITERALLY
TC$L02
TC$HI2
LITERALLY
IOlH
LITERALLY
TC
1* 8291A

4

'OFFDDH' ,
'OFFDOH' ,
'OFFDOH', '
"OFFDIH" ,
'OFFDIH' ,
'OFFDBH' ,
'OFFD8H' ,
'OFFDFH' ,

'48H",
'44H "
'DOH',
I01H "
'20H "

'OFFH' ,
'OOH' ,
'99D',
'OOH',
I J

PORT ADDRESSES *1

DECLARE
PORHOUT
PORHm
STATU~3$1

STATUS$2
ADDR$STATUS
CDr1t1AND$t10D

LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY

10-133

'OFFCOH' ,
'OFFCOH',I* DATA IN *1
'OFFCIH', 1* INTR STAT 1 *1
'OFFC2H', 1* INTR STAT 2 *1
'OFFC4H', 1* ADDR STAT
*1
'OFFC5H', 1* tMD PASS THRU *1

230832-001

•"n+_I®
•• 'eII

AP-166

PL/M-86 COMPILER

BOARD2
ADDR$O
EOS$REG
/~

8291A

'OFFC6H' ,
'OFFC7H', 1*

LITERALLY
LITERALLY

EOS REGISTER *1

COMMAND - DATA BYTES *1

DECLARE

5

'BSH' ,
END$EOI
LITERALLY
'10H' ,
DNE L ITER ALL Y
Por~
LITERALLY
'OOH' .
'02H' J
RESET
LITERALLY
'~OH' ,
CLEAR
lITERALLY
'10H' ,
DMA$REG$L LITERALLY
'20H J ,
DMA$REG$T LITERALLY
'SOH' ,
MOD1$TO
LITERALLY
'.40
MOD1.LO
lITERALLY
'ODH' ,
EOS LITERALLY
PRESCALER LITERALLY
'23H "
'A4H',
HIGH.SPEED LITERALLY
XVZ
BYTE,
130
LITERALLY '02H',
131
LITERALLY 'OlH' ,
ERR
LITERALLY '04H',
I I'

START91.

6

OUTPUT

(STATUc';$2)

=CLEAR:

I,,,

END INITILIZATION STATE *1

1* IN1T 8237 FOR LISTENER FUNCTION

INIT37L;

7

OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPLUT

8
9
10

11
12

13
14

1*

15
16
17
18
19
20

21

*1

2

(CLEAR$FF) =CLEAR; 1* TOGGLE MASTER RESET *1
(CI10$37 )
=NORM$TII'lE;
( SET$t10DE ) =WR$TRANSFER;
1* BLOCK XFER MODE *1
(SET$MASK) =CLEAR.
(START$O$LO)
=ADDR$lA;
(START$O$HI)
=ADDR$lB.
(O$COUNT$LO)
=TC$LOL
(O$COUNT$HI)
=TC$HI 1;

INIT 8291A

FOR LISTENER FUNCTIONS

OUTPUT
(COMMAND$MOD)
=RESET;
OUTPUT
(ADDR$STATUS)
=MOD1$LO;
OUTPUT
(COMMAND$110D)
=PON;
DO I~HILE (INPUT (STATUS$l) AND Bn
END;
1*
WAIT FOR BI INTR *1
XYZ= INPUT (PORT$IN).
OUTPUT
(STATUS$2)
=Dt1A$REG$L;

*1

=0;

1* WAIT UNTIL EOI RCUD AND END INTR-BIT SET

22

DO IJHILE

(mpUT

(STATUS$1)

10-134

AND DNE )

*1

<>

DNE;

230832-001

AP-166

PLlM··86

COMP I LER

END;

23

INIT37T,
1* INIT8237 FOR TALKER FUNCTION

24

OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

25
26
27
28
29
30
31
32

output
OUTPUT

1*

38

42
43
44
45
46

(EOS$REG)
=EOS;
(COMMANDSMOD)
U\DDR$STATUS)
i C OMMAt~D$MOO)
(C OMt1ANO$t10D)

(COMMAND$MOO)

*i

=ENOSEOI;/* EO! ON EOS SENT
=t10D1 STO; 1* TALK ONLY *1
=PRESCALER;
-HIGH$SPEED;
=PON;

*1

=0)

(INPUr (STATUS$ll AND ERR)
-ERR;
DO I~HILE
(INPUT (STATUSS1)
AND Bo)
=0.
END.
1* WAIT FOR ~O INTR *1
OUTPUT (PORT$OUT) -OAAH;
END;

D.o.I~HILE

2
3
2
2

OUTPUT (STATUS$2)
-OMASREG$T.
l* I~AIT FOR TC=O *1
DO I~HILE
END;

2

(Ct1DS37)

( INPUT

AND TC)

<>

Te;

GOTO START91;

50

51

FOR TALKER FUNCTION

DO WHILE (INPUT (STATUSS1)
AND EO)
END;
1* WAIT FOR BO INTR *1
OUTPUT (PORT$OUT)
=OAAH;

1

2
1

47
48
49

*l

(STATUSS2) ~CLEAR;
1* CLEAR 8291A ORQ *1
(CLEARSFF) =CLEAR;
(CMD$37)
=NORM$TIt1E;
1* BLOCK XFER MODE *1
(SET$MODE) =RD$TRANSFER;
(SET$MASK) =CI.EAR;
(START$O$LO)
=ADDR$lA;
(STARTSOSHI)
=ADDR$lB;
(OSCOUNt$LO)
-TCSL02;
(O$COUNT$HI)
=TC$HI2;

INIT 8291A

OUTPUT
OUTpUT
OUTPlJT
OUTPUT
OUTPUT
OUTPUT

33
34
35
36
37
39
40
41

BOARD2

END;

MODULE INI"ORMATION
CODE AREA SIZE
CONSTANT AREA SIZE
YARIABLE AREA SIZE
MAXIMUM STACK SIZE
152 LINES READ
o PROGRAM ERROR (S)

=0122r!
-OOOOH
=OOOlH
"'OOOOH

2900

ob
10
00

1()"135

230832-::f er =1:: I t·iAt·i

PF.:lt~~T

II

..

710
PF~ I t~T "COt'H1
At-HI =?
(HIT
"H" FOF.: LIST)"
72(1 F.:ETUF.:t·i
73(1 Ilec.:
F~ESET
704
740 PRINT CHR$(
12), "SELECTIVE D
EV I CE CLEAR ~;EtH

= ";

IF D::~3
GOTO F.:c.1.}r·
530 GOTO Keye-n
531 -Rcvr':
REt'l R
EADY TO RCV CHAR
S FROM GPIB
540 DIM G$[S0J
550 ENTER 704 U
SING %, T" ;G$
560 PRINT CHR$(
12) , G$
570
F'R I NT "COMM
AtHI
?
(HIT
"H'- FOR LIST)"
580 GOTO Keyen
590 REM INTERRlI
PT SERVICE ROUTI
NES
600
REt'1 GET KE\,
BOARD IIATA
E,l0 ~Jhat ke':"-:
DI
M K$[80]
f2(1
K$=rE:D$
E,:;:(1
IF K$="G" T
HEt-i GOTO Get640
IF ~~$="D" T
HEt-i GOTO Dec
65(1
IF'K$="R" T
HEt~ G01.O Rer",
6E,0
IF K$="H" i
HEt·i GOTO Helr;'
670 IF K$="X" T
HEN GOTO Xrtl it
680 Get,:
TF~IG!:E
52(1

THEt-~

"

75(1
7E.(1

PRINT it
PR ItH "COr'1to1
At~D = t")
(HIT
"H'- FOP LIST)"
770
F.:ETURt·i
78[1 F.: t?r'-, :
LOCAL
704
790 PR HH CHR$ (
12),"REMOTE MESS
AGE SE.NT"
800 PF.: I NT 810 PRINT "CO~1t1
AND = t")
(HIT
"H-' FOF.: LIST)
82(1 RETUF.:t·i
830 Helr;':
PRINT
CHR$(12)
840
PF~ I NT
@@@
@ OPERATOR ALLOl~
AE:LE COMMANDS @@

II

=

II

II

II

U

II

@@

850

II

key

860

PRINT

II

PRINT"
G
S,end GET rl ,

e;:· so_ ge."
870 F'RINT"

10-137

hit

result"

II

230832-001

AP-166

:::~~}

P~:

ItH "

•
Send
OC I"',e::.::.o.·~e"
:::9(1
P~: an

94~J

~:Et'1.··L

r' d

j

n r.o l~ t

II H1 A

F'F.: ItH CHF.:$ (
12), "Ent.er· do.t.o.
t. (I ::.end (l.nd hit.
COtH I flUE"
960
H~PUT A$
9 7 f10 UT F' U T 7 (14 ;
A$
971
EOl 7;0
980
PRINT "COMM
AtHI
(H 1.T
"H'" FOF.: LIST)"
990
~:ETU~:t'i
10f1(1 Et'H!

95~}

"
o

.:••J.

:: AND SRGS)"SRGSI
ENOl

13

2

OUTPUT (SPOLL$STAT)=NO$RSV.

14

2

END REGSER.

15
16

1
2

17
18
19
20
21
22
23
24
25

2

DO WHILE (INPUT (SER$STAT) AND TXRDV)<>TXRDV,

:3

END,

2
2
1
2
3
3
2

2
2
3
3
3
3
3
3
3
3
3
4
5
4
4
3
3
2

PROCEDURE.
IF (INPUT (SER$STAT) AND RXRDV)=RXRDV THEN
DO,
1=0,

2

CHAR$COUNT=O,
CHAR=(INPUT (SER$DATA) AND 7FH).
CHAR$COUNT=CHAR$COUNT+l,
CALL CO (CHAR),
CHARS( I )=CHAR,
1=1+1 ;
IF CHAR <> CRLF THEN
DO.
DO WHILE (INPUT (SER$STAT) AND RXRDV) <>RXRDV,
END,
GOTO STORESCHAR.
END;
CALL REGSER;

STORESCHAR:

END,
END ell
TALKSEXEC:

45
46

OUTPUT (SER$DATA)=XXXI
END COl
HUH:
PROCEDURE,
DO 1=0 TO 10.
CALL CO (HUH$MSG(I»,
END,
END HUH.
CI :

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

CO: PROCEDURE(XXX).
DECLARE
XXX
BVTE,

PROCEDURE;

OUTPUT (STATUSS2)=CLEAR.
1*,

manipulate address bits for DMA controller
*1

47
48
49

2
2
2

DMA$ADR$TALK=(@CHARS),
DMA$WRD$TALK(1)=SHL(DMASWRDSTALK(1),4),
DMA$WRD$TALK(O)=DMA$WRD$TALK(O)+DMA$WRD$TALK(l),

50

2

OUTPUT (CLEARSFF)=CLEAR.

10-141

230832-001

AP-166

PL/M-86 COMPILER
51

2

52

2

53
54

2
2

HPIB

55

2

56
57
58

2
2

2

OUTPUT (CMD37)=NORM$TIME.
OUTPUT (SET$MODE)=RD$XFER.
OUTPUT (SET$MASK)=CLEAR.
OUTPUT (START$LO)=DMA$WRD$TALK(O).
DMA$WRD$TALK(0)=SHR(DMA$WRD$TALK(0).8).
OUTPUT (START$HI )=DMA$WRD$TALK(Oll
OUTPUT (COUNT$LO)=CHAR$COUNT.
OUTPUT (COUNT$HI)=O.

59
60

2
2

OUTPUT (EOSSREG)=EOS.
OUTPUT (COMMANDSMOD)=ENDSEOI.

61
62
63

2
3
2

DO WHILE (INPUT (STATUS$l) AND BO)=O.
END.·
OUTPUT (PORTSOUT)=OAAH.

64
65
66
67
68
69

2
3
4
3
3
2

DO WHILE (INPUT .(STATUSS1) AND ERR)=ERR.
DO WHILE (INPUT (STATUS$l) AND BO)~O.
END.
OUTPUT (PORT$OUT)=OAAH.
END.
OUTPUT (STATUSS2)=DMASREQST.

70

2

END TALKSEXEC;

71

LISTENSEXEC:

PROCEDURE.

72
73
74
75
76

:2

77

:2

78
79
80
81
82
83
84
85

2
2
2
2
2
2
2
2

OUTPUT (STATUSS2)=CLEAR;
OUTPUT (CLEARSFF)=CLEAR;
OUTPUT (CMDS37)=NORMSTIME;
OUTPUT (SETSMODE)=WRSXFER;
OUTPUT (SETSMASK)=CLEAR;
DMA$ADRSLSTN=(@CHARS);
DMASWRDSLSTN(1)=SHL(DMASWRDSLSTN(1).4);·
DMASWRDSLSTN(O)=DMASWRDSLSTN(O)+DMASWRDSLSTN(l);
OUTPUT (STARTSLO)=DMASWRD$LSTN(O).
DMASWRD$LSTN(0)=SHR(DMASWRDSLSTN(O).8);
OUTPUT (STARTSHI)=DMASWRD$LSTN(O);
OUTPUT (COUNT$LO)=TCSLO;
OUTPUT (COUNT$HI)=TCSHI;
OUTPUT (STATUSS2)=DMA$REQ$L;

86

2

END LISTEN$EXEC;

2
2
2
2

87

PRINTER:

PROCEDURE.

88

2

1=0;

89
90
91
92
93

2
3
3
3
:2

DO WHILE PRI$BUF(I) <>CRLF;
CALL CO (PRI$BUF(I».
1=1+1.
END;
CALL CO (PRISBUF(I»;

94

2

END PRINTER.

230832-001

inter

AP-166

PL/M-86 COMPILER

HPIB

ADSC.EXEC:

9.5

PROCEDURE;

962

TA.OR.LA=INPUT (ADDR$STATUS);

97
98

2
2

99

2

100

2

IF (TA.OR.LA AND TALK)=TALK THEN
CALL TALK$EXEC;
IF (TA$OR.LA AND LISTEN)=LISTEN THEN
CALL LISTEN$EXEC;

101

2

END ADSC$EXEC;

102
103
104
105
106

1
2
3
3
2

GET$EXEC:

107
108
109

1
2

DEC$EXEC:

110
111
112
113

3
3

2
1
2

114

3

li5

3
2

116

PROCEDURE;
DO 1=0 TO 10;
CALL CO (GET$MSG(I»;
END;
END GET.EXEC;
PROCEDURE;
DO 1=0 TO 15;
CALL CO (DEC.MSG(I»;
END;
END DEC$EXEC;

REMC$EXEC:

PROCEDURE;
DO 1=0 TO 9;
CALL CO (REMC$MSG(I~);
END;
END REMC.EXEC;

PPOLL$CON:

117

PROCEDURE;

118

2

OUTPUT (COMMAND$MOD)=PPOLL$CNFG$FLAG;

119

2

END PPOLL$CON;
PPOLL$EN:

120

PROCEDURE;

121

2

122

2

PPOLL$EN$BVTE=(UDC AND 6FH);
OUTPUT (COMMAND$MOD)=PPOLL$EN$BVTE,

123

2

END PPOLL$EN;

124
125
126

1
2
3

127

3

PROCEDURE;
DO 1=0 TO 21;
CALL CO (CPT.MSG(I»;
END;

128
129
130
131

2
2
2
2

UDC-INPUT (CPT.REG);
UDC-(UDC AND 7FH);
IF (UDC AND PPC)=PPC THEN
CALL PPOLL.CON;

132

2

133

2

IF (UDC AND PPE$MASK)=PPE$MASK THEN
CALL PPOLL.EN;

CPT$EXEC:

10-143

230832-001

inter

AP-166

PL/M-86 COMPILER

134

HPIB

END CPTSEXEC.

2
1*

BEGIN CODE
*1

INIT:

135
136
137
138
139
140

OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

141

LISTENERS:

(CLEAR$FF) =CLEAR.
(COMMAND.MOD)
aRESET.
(ADDR$STATUS)
.. MODE.l.
(ADDR$O)
=MLA.
(STATUS$2) =NO.DMA.
(COMMAND.MOD)
-PON.

1* response to listeners check *1

142

DO WHILE (INPUT (STATUS.l) AND BI)-O.
END.

143
144

XVZ-INPUT (PORT.IN).
XVZ-INPUT (STATUS.2).
CMD:

145

RDSTAT:

1* read status registers and interpret command *1

STAT1=INPUT (STATUS$l).
STAT2=INPUT (STATUS$2).

146
147
148
149
150
151

152
153

154
155
156

157
158

159
160
161
162

163
164
165

1
1
1
1
2
2

2
1
1
2
2
:2
1
1
2

2
2
1
1

166

2

167

168

2
2

169

1

IF (STATl AND DNE)-DNE THEN
CALL PRINTER.
IF (STATl AND CPT)=CPT THEN
DO.
CALL CPT$EXEC.
STAT2=(STAT2 AND OFEH).
END.
IF (STATl AND GET)=GET THEN
DO.
CALL GET$EXEC.
STAT2=(STAT2 AND OFEH).
END.
IF (STATl AND DEC)=DEC THEN
DO.
CALL DEC.EXEC.
STAT2=(STAT2 AND OFEH).
END.
IF (STAT2 AND REMC)=REMC THEN
DO.
CALL REMC$EXEC.
STAT2=(STAT2 AND OFEH).
END.
IF (STAT2 AND ADSC)=ADSC THEN

10-144

230832-001

"Info_F
•• 'eII

AP~166

PL/M-B6 COMPILER
170
171
172
173

HPIB

1
2

001

CALLADSC.EXEC;
STAT2-(STAT2 AND 'OFEH)I
ENOl

2

2

174

CALL CII

179

GOTO CMDI

176

ENOl

MODULE INFORMATION:
CODE AREA SIZE
CONSTANT AREA SIZE
VARIABLE AREA SIZE
MAXIMUM STACK SIZE
349 LINES READ
o PROGRAM ERROR(S)

=
=
-

0475H
OOOOH
0061H
OOOAH

11410
00

970
100

·uND OF-PL/M-B6 COMPILATION

10-145

230832-001

ARTICLE
REPRINT

AR-208

June 1982

Reprinted with permission from COMPUTER DESIGN, March 1982.

Order Number: 210404-001

.10-147

SPECIAL REPORT ON DESIGNING WITH ADVANCED SYSTEM ICs

LSI TRANSCEIVER CHIPS
COMPLETE GPIB
INTERFACE
A GPIB interface meeting
only three or four chips!

IEEE 488

standards can be built with

Integration benefit

by Pradip Madan and
Jim Frederick
he decision to support the IEEE 488 standard with
integrated circuits was based on the potential
popularity of the interface standard and its applications potential. Although a serial ,interface supports
many system throughput requirements, a parallel interface over short distances can provide much higher data
transfer rates, yet remain economical despite the extra
interconnection copper required.
The IEEE 488 standard is for a parallel interface
designed to operate over a limited distance. Its general
purpose nature makes the general purpose interface
bus (GPIB) attractive for a variety of systems, and also
allows manufacturers to design their equipment interfaces to a common standard. As a result, users can mix
equipment from different manufacturers without having to adapt the interfaces for compatibility. To date
the GPIB has been incorporated in computer peripherals,
such as printers, but the most applications have been in
programmable instrumentation systems. Other GPIB
applications include camera' control in computer controlled studios, electronic surveillance, peripheral control, modular add-ons to photocopiers, and so forth.

Shortly after, the IEEE
committee had put the
final touches on its standard specifications,
engineers began building
GPIB interface subsystems. Because the
standard had just been
defined, there were no
large scale integration
(LSI) chips available.
Therefore, the first GPIB
implementations were
board level designs
replete with small scale
integration (SS!) and
medium scale integration
(MSI) logic chips. A typical effort included four or five
rows of ten chips each.
With the advent of integrated circuit GPIB chips, chip
counts dropped dramatically, reliability improved; and
space requirements shrank. Consequently, the price
range of systems for which GPIB had become practical
began to decrease. A fully functional GPIB subsystem
can now be constructed with less than one-tenth the
number of chips formerly required. In fact, the complete

PradipMadan is the product manager for
microprocessor peripheral components at Intel Corp,
2625 Walsh Ave, Santa Clara, CA 95051, where he
has been employed for 2 years. He has a BSEE, an MS
in computer science, and an MBA in finance.

Jim Frederick is a microcomputer design engineer at
Intel Corp. Since joining the company in 1974, he has
been inv,olved in several different projects. Mr
Frederick has studied at the College of San Mateo,
and the University of Santa Clara.

T

10-148

210404-001

AR-208
. talker/listener/controller mode logic resides in four LSI
chips: one Intel 8291A talker/listener, one 8292
controller, and two 8293 transceivers. All these LSI,
including the transceiver, are implemented in metal
oxide semiconductor (Mas) technology.
Unlike the controller or talker/listener functions
which could be integrated routinely in N-channel MaS
(NMOS) technology, the transceiver posed special
problems in MaS integration.

A conventional MaS transistor capable of supplying
48 rnA at 0.5 V would have been physically too large.
HMOS technology, however, permits such a device to be
fabricated in an area of less than 150 mil2 (97 mm 2).
Furthermore, the low speed/power product of HMOS
allowed a multi-stage design so that, like transistor-transistor logic (TIL) circuitry, natural hysteresis could be
built into the receivers.

The chip's size includes a 7-mil ground
line and two ground pads in order to
handle the 432-mA current.

IEEE 488

The standard calls for the transceiver circuitry to be
able to drive each of the 16 bus lines with a nominal
48 rnA of current. In addition, it specifies a minimum
required input hysteresis and places a limit on propagation delays. Driving relatively high currents quickly was
not a familiar province of MaS tecijnology. Certainly
the garden variety NMOS lacked the necessary speedpower product to handle the task.
However, progress in NMOS technology has produced
the high speed, densely integrated high performance
MaS (HMOS) technology which has the necessary
characteristics to meet the current drive and propagation speed requisites.

DEVICE A
ABLE TO
TALK. LISTEN.
AND
CONTROL

Dasigning tha 8293 transc!livar
Although the .48-mA drive required by the 16 OPIB lines
had only been implemented with bipolar technology
before, HMOS technology-with its reduced gate
lengths, smaller size, and lower parasitic capacitance-looked like it could handle the job. Architecturally, the 8293 contains nine transceiver circuits which
can.be configured for data or interface management line
transceivers. Nine open collector or 3-state line drivers
that could sink 48 rnA, in addition to twelve· Schmitttype line receivers, were used to implement the nine
transceivers. Fig f is a schematic representation of one
of these 3-state drivers.
Additional logic was addeli for decoding the transmit/receive mode control of each of the transceivers.
The 8293 was conceived as operating in four distinct
modes: talker/listener control transceiver, talker/listener/controller control transceiver, talker/listener data
transceiver, and/or talker/listener/controller data
transceiver. Thus, a 2-pin select scheme allows a user to
select the desired operating mode.

Choosing appropriata actin davicas
All of the 8293's functional elements required only four
different types of active field effect transistors (FETs).
Low threshold enhancement type devices show good
high output voltage characteristics, and were used as
output pullup devices in push-pull 3-state drivers.
Enhancement type FETs were also used for fast
switching and low leakage: depletion type devices were
used for resistive pullup in buffering. Depletion type
FETs also played an important role in meeting the
hysteresis specifications of the IEEE 488 standard.
Finally, higher threshold depletion type devices were
used to prevent the bus .lines from being disturbed on
power-up and power-down.

Interface standard

ttllt ltll
t:::::

DEVICE B
ABLE TO
TALK AND
LISTEN

==

DEVICE C
ONLY ABLE
TO LISTEN

==

DEVICE 0
ONLY ABLE
TO TALK

=

DATA

DATA BYTE
TRANSFER
CONTROL

GENE.RAL
INTERFACE
MANAGEMENT

~IDlO L.8
oAV
NRFo
NoAC
IFC
ATN
SRQ
REN
EOI

The IEEE 488 interface standard specifies an a-bit
parallel, bidirectional data bus with eight additional
lines for data-byte transfer control and general interface management. The three data-byte.transfer lines
are data valid (DAV), not ready for data (NRFD), and not
data acceptad (NDAC). States of thase three lines
detarmine when data on the a-bit data bus are valid,
ready to be received, I!nd received, respectively.
General interfl!ce mangement lines are interfaca clear
(IFC), attention (ATN), sarvicB request (SRO) , remote
enable (REN), and end or identify (EOI). These lines are
used to clear the bus and establish control, initiate
polling, pass control from a controller to another controller or the front panel, and indicate the end of a
transfar sequence.

10-149

210404-001

AR-208
Special layout techniques
The transceiver was implemented using new layout techniques aimed at reducing the series resistance in the
polysilicon gate structures of the large transistors, and
routing ac signal paths over metal interc,onnects in order
to reduce capacitance and series resistance. Chip size,
188 x 156 mils (5 x 4 mm), includes a 7-mil (0.2-mm)
ground line and two ground pads in order to handle the
432-mA current generated when all drivers are on.
Power consumption is 300 mW, typically, with driver or
receiver speeds of 20 ns under light loads and speeds of
85 ns under the maximum load of 4500 pF.

j-r----i~/ m~~:
DATA
OUTPUT

Signaling a new trend?
Until the advent of the 8293, complex MOS chips relied
on bipolar drivers to handle the heavy bus loading
found in complex systems. The 8293 could point the way
to future microprocessors and controllers that include
their own MOS drivers. Such a scheme would significantly reduce the time lost by going through external
buffers. It would also provide all the other benefits of
system integration.
The 8293 is essentially a non inverting buffer chip
capable of driving high currents. The 8291A talker /listener chip and 8292 GPIB controller chip are designed to
interface with the 8080, 8085, iAPX 86, iAPX 88, and
8048/8051 microprocessors and single-chip microcomputers. However, the 8291A and 8292 cannot electrically
drive a standard IEEE 488 bus by themselves. Thus, the
8293 was designed to interface between the GPIB and a
single 8291A or a combination of the 8291A and 8292. (See
Fig 2.)
The chip is divided into nine distinct transceivers.
Each one's characteristics, such as 3-state or opencollector outputs, and transmit or receive modes of
operation, are determined by internal logic control. (See
Fig 3.) Thus, in mode 0 talker/listener control configuration the attention (ATN) transceiver is forced into an
input-only mode with respect to the bus's ATN line. The
end or identify (EO!) transceiver, on the other hand, is
either a transmitter or receiver depending on the state of
the transmit/receive (T/R2) line. Its interface to the GPIB
is 3-state because of the fixed 5 V logic on the EO!
transceiver's output control. In mode 1, the talker/listener data configuration, the 8293 is a true transceiver
with its operations mode controlled by the state of the
T/RI line and its output characteristics (3-state or opencollector) determined by the states of the ATN and EO!
lines. (See Fig 3.)

W·TYPE

N·TYPE

D-TYPE

l·TYPE

Fig 1 3-state driver schematic. Nine such open collector
drivers are used in the interface.

GPIB

TO
PROCESSOR
BUS

GPIB
(a)

GPIB

19
TO
PROCESSOR
BUS

B291A

TO
PROCESSOR
BUS

GPIB
(b)

Fig 2 8239 is designed for use in talker/listener
implementation (a), or for talker/listener/controller
interface (b).

10-150

210404-001

AR-208

MODE 0

MODE I
OPTA
OPTB
3·STATE ONLY

GIOI

GIOI'

DAV

TlRIOI
3·STATE ONLY

GIOZ

GIOZ'
0101

TlRI02
INPUT ONLY

ifC

IFe·
OIOZ

INPUT ONLY

REN

REN0103

INPUT ONLY

Affi

OPEN·COLLECTOR
OUTpUT ONLY

SRQ

ATN*
0104
SRQ'
0105

3·STATE ONLY

Wi

EOI'
0106

TlRZ
NRFD'

NRFO

0107
NDAC'

NDAC

~108

TlRI

TIC I

0
SIR I

0

Affi
Wi

3·STATE
-.I=5V
OPEN COLLECTOR
SEND TO GPIB
.,; = OV
RECEIVE FROM GPIB
IEEE 488 BUS NON INVERTING DRIVER/RECEIVER

(b)

(a)

Fig 3 Internal logic controls for each transceiver will be either fixed or subject to control via
external logic. In mode 0, chip Is set up for control, thus some transceivers are fixed In transmit or
receive mode only. In mode I, chip is configured as true transceiver-all nine transceivers can
transmit or receive depending on state of TIKI pin. In (a) is talkerllistener control configuration,
and In (b), talkerllistener data configuration.

The talkerIlistener I controller control configuration,
mode 2, is a full transceiver mode but the operation
mode of the transceivers is determined by more complex
combinational logic. (See Fig 4.) The fourth mode
(mode 3), which is the talker llistener I controller data
configuration, is again a true transceiver whose mode of
operation is controlled by the state of the TiRol line. In

this mode, some additional interval combinational logic
is enabled to permit the 8293 to support the 8292 in taking
bus control synchronously.

... complete talker/listener!controller
mode logic resides in four LSI chips.
The 8293'5 overall mode (mode 0, I, 2, or 3) is determined by the state on the option pins 26 and 27. For example, if both pins are tied low (0 V), the chip is in
mode O. If both are high (5 V) it is in mode 3. The particular state of these pins will determine the
characteristics of the other 26 pins. (See the Table. "8293
Mode Selection Pin Mapping.")

Talkar/listanar only
If the IEEE 488 is to be implemented in a system that is
able to talk and listen (eg, a digital multimeter), only
talk (eg, a counter), or only listen (eg, a signal generator),
10-151

210404-001

AR·208

MODE 3

MODE 1
OPTA

ATNO

OPTB

im

NOAC

NOAC'

NRFO

NRFD<>

OPTA
OPTB

iiAV
Tliil

DiOi
Tliil

IFe"

TFC

0101

SYC

ill

REN'

SRQ

SRQ'

0104

ATNI

ATN'

0105

£01'

0106

0103

Alii
lOll

ATNO
0107

fOi
Tliil

0108

£OJ

iffL

Alii

CLTH

CiC

(b)

(.1

Fig 4 Mode 21s control configuration. Operating nodes of individual transceivers are controlled by
external signals and internal combinational logic. Chip in mode 3 acts like true transceiver, as in
mode I, except some extra functions have been included in order to support controller function. In
(II), talkerllistener/controller configuration is for control, and in (b), for data.

then the entire interface can be built with a single
8291A and a pair of 8293s. (See Fig 5.) In this configuration, one 8293 handles the eight data lines DIOI to 0108
and the other handles the data-byte transfer handshake
lines and general interface management lines. Both
transceivers are connected to the 8291A's ATN, and EOI,
and Tlih lines.
Talker/listener/controller
For an IEEE 488 controller (like the HP 85 or Tektronix
4051), the system must be able to take control of the bus
or delegate it to another controller. Such an interface
scheme can be implemented using an 8291A, an 8292, and
a pair of 8293s. (See Fig 6.) The arrangement is similar to
that of a talker/listener interface; one 8293 handles the
0101 through 0108 bus data lines and the other handles
the data byte transfer handshake and general interface
management lines. The difference is that pins 26 and 27
have been selected for modes 2 and 3 and several addi-

tional control functions have been added. The attention
in (ATNI) lines and attention out (ATNO) lines permit the
8292 to monitor the GPIB's ATN line and take control of
the bus. In conjunction with the ATN line, the E0I2line is
used by the 8292 to initiate a polling sequence.

The chip is divided into nine distinct
transceivers and each one's
characteristics are determined by
internal logic.
Lastly, the system controller line (Syc) enables the
control function. If it is low, the 8292 is prevented from
acting as a controller. If it is switched high, the 8292 can
act as a controller. In essence, the SYC controls the
direction of the interface clear (IFC) and remote enable
(REN) signals.

10-152

210404-001

AR·208

25

8293

iiiOi
tii02

.0101"

Di04

0104"

23
10 !ii1jj
9

--'1.
....ll
...!i
.J1

8291A

iiiOi

DO

6iii2

DI
02
03'

TO
MICROPROCESSOR
INTERFACE

2

9

~
-==.

GPIB TRIGGER OUTPUT

0104

31
32

24

33
34

4
3

DIDa

a

DAY

Ill!

Tliil

,.

:\'II'::""','"

.-!.! lIlT
..J. .tI.QCII

-1

30

iiiOi
,:6i07

.J! b1

-

RES~

---1 DREQ
-1 DAti
---1 TRIG
I

(.'

6
5

:0i03

m

~ D4
....!L 05
.J! 06,

8
7

28
29

',Alii
EOI

I

35
36

m:

Dl03"

It
.!t.
18

17

~
~
~106"
~
DI,07"
~
0108"
DAY" ~

m

0105"

5W6

6m
Drn1

jjf

TO
IEEE 488
BUS

tv

OPTA t-- Vee
GND

Till'

AlIi

':OPTS

toi

"

~

MODE I

I
26
39

3

2
TIR2
38
NOAC.
37
NRFD
27
SiiQ
25

REN

D102"

I

24'

"GPIB TRANSCEIVER

EO.I~

m

AUI",

NDAC

" NIiAc<

'4
I
Tliil
2
TIR2
10
9

,

.819$

EOI,

~.FD"

N!!fD

8
6

.iRQ.

5

iff

t#r!L-

TO
IEEE 488
BUS

$RQ" r!L
-, , :R£N.~.
r!L

mi,

I',,··

r!L
r!i-

IFCo' ~

oPTA' ~ GND
J.

,:O~

MOD~:O

,

pL

GNO

"

Fig 5 Tl\Ikerlllstener only Implementation can be built using JUBt three cblps-s1ngle Il9IA and a
pair ol,l293S. Fint (upper) transceiver cIilp Is used for bidirectional data Dow on DIal to DUll data
Dnes. Lower am bandies some of data byte transfer control Dnes and general Interface management
Dnes.
'

8293 MODE SELECTION PIN MAPPING

Vee
OPTA
OPTB
OATAIO
OATA9
OATA8
BUS9
BUSS
GND
BUS7
BUS6
BUS5
BUS4
BUS3

"These pins a~ the lEU U8 bus non inverting driver/receivers. They include all the bus terminations
required by the standard, and connect directl, to the CPtB connector.

10-153

210404-001

AR·208

TO MICROPROCESSOR
~

..g. 00
-#01
402
403
16 04
17 05
18 06
19 01
1+++-H+lH-2~1 RSO
-t-H+lH-t+t+-H"",2~2 RSI
3 RS2
-+-H+lH-t+t+-H....:2*i

I~

TO
MICROPROCESSOR

Rii

H-++++++-H-t-'fl WR
H-++++++-H-H--"'1! RESET
-+-H-hH-++++-H~7 DREQ
-+-H-+-1H-+++++I---i:-l
B ~CK
-+-H-I-H-++++-H~3 CS
-+-H-I-H-++++-H--'I'"'!I

TRI~m

8291A

5 0101
0101 f-;2'87-_ _ _ _ _ _ _ _---:;2:-t
0102 29
23 Iiiiii
0103 30
10 iiI1i3
0104 31
9 Iii04
0105 32
8 0105
7 0106
0106 33
0107 34
6 0107
Di08 35
5 0108
TlRI I
I Tliil
IiAV 36
24 DAY
EOi 39
3 EOi
iii'N 26
4 iii'N
SRQ 1"2"-IH _ _ _--,
24

OIOI',R
0102'
0103'
0104'

elii#r!L
0105'~
0106' eli8293

0101'
0108'

r!L

TO
IEEE 488
BUS

r!t

DAV'~

m:

NOAC 1-'3~8+-1,---_---,
NRFO 1"3,,-7H----,
Tlii2 1"2'-+-1---.

;~~CK

REN'rll-

5 TRIG
-t-HH-H-t+++-H---"i

OUTPUT

OPTA
OPTB

E.. Vee
1L Vee

NRFD
NOAC

.!Z...
.!LJ

MOOE 3

r-l

,-¥:OO

~Ol
~02

---M03
16 04
17, 05
18 06
19 07
9 AO
'--_ _ _ _-"i

I~

L-[)

:

Rii

WR

I!!SET

32 ~~I
TO { -'-_ _ _ _ _ _-::3,,3 SPI
MICROPROCESSOR
35 OBFI
_ _ _ _ _ _ _-::3"-16 IBFI
OSCILlATOR _ _ _ _ _ _ _-'Iii; SYNC

2

OUTPUT

Vee
~ XI

~

15 TO 15 PF

J4:-::-r
_ -b

3 'X2

SRQ
liEN
8292

m:

iii'Nil

COUNT
[012
ATNI

Tliil

4 iii'N
'--H--t--c=-t
'-t-+-_-+-+-"'IIO NOAC
,---++-_-+-+-",9 NFRO
2 Tlii2
'---+-If--+--If--4
~2,-1-1-+---+'+--++-"18 SRQ
38
6 REN
23
29
13 ATNO
39
3 EOi'
34
7 E0I2
22
II ATNI

5m:

8293

SRQ' .!L
R'EN' .!L
IFC'#ATN' .!!.
EOI' ,Jl..

TO
IEEE 488
BUS

5 IFCL
iFCi ""1,-_ _ _-.,.-_ _ _-4-:2"i
Cit 31
24 CiC
CLTH 27

I L _ _ _ _ _S_YC...J24

:; CLTH

I

v~eON

~

SYSTEM
CONTROLLER
SWITCH'

OPTA 1L GNO

SYC
OPTB 1L vee
'--_..:.:M:::;OO::E..:2_---'
'GPIB TRANSCEIVER

Fig 6 FuDy functional talker/llstener/controller Interface can ~ buUt with only four LSI chips; the
8291A. nn, and a pair of 8293S. Like simpler talker /listener only case, one 8Z93 handles data
transceiver functions whUe other handles data byte transfer control and general Interface
management. There are additional control lines enabled which support the controller (8zn) activity.

Summary
Before the advent of integrated solutions for IEEE 488
implementation, it usually took forty to fifty SSI and
MSI chips to build this interface. A large portion of
those were eliminated by controllers .and interface chips
like the 8291A and 8292. Now, with the last part of the
interface available in LSI, a fully functional interface
can be built using only four LSI chips. The cost of the
original design was typically $400 to $SOO. A set of the
three chips, the 8291A, and two 8293s (for a
talker/listener function) allows a IS-fold reduction in
cost. The power dissipation of a 4O-chip interface was in

the vicinity of 10 W. The power dissipation of the 4-chip
approach is a mere 1.5 W. The size of the PC board is
considerably smaller, too, and, that lowers the manufacturing costs' and improves reliability.

10-154

210404-001

intel~

ARTICLE
REPRINT

AR·113

January 1980

""NTEL CORPORATION, 1110

Reprinted with permission of Computer Design Magazine,
October 1979 Issue.

10-155

231320-001

LSI CHIPS EASE STANDARD 488
BUS INTERFACING
Time and cost disadvantages of interfacing to the IEEE Std 488
bus are overcome with a dedicated LSI chip set that incorporates
most of its functional and electrical specifications

Ronald M. Williams

Intel Corporation, Santa Clara, California

Historically, interface techniques proliferated as
designers evolved customized links among instruments,
controllers, and processors for realtime test measure·
ments . or data communications, resulting in excessive
and expensive codes, formats, signal levels, and timing
factors. Obviously, interface standardization was manda·
tory to save design costs for engineers, development
costs for manufacturers, and system· integration costs
for users. Thus, IEEE Standard 488·1978 (a revision of
ANSI/IEEE Std 488.1975) offers a universal instrumenta·
tion system approach to automatic operating measure·
ment configurations that provides compatibility, versa·
tility, and flexibility. This system approach establishes

a suitable standard bus for interfacing programmable
devices from different manufacturers. Outstanding ad·
vantages of the standard bus include byte serial, bit
parallel digital data handling, synchronized communi·
cation among devices at varying data rates, and hard·
ware interchangeability and interconnection in daisy·
chained fashion. However, some restrictive disadvantages
that have hindered implementation are highly com·
plex logic protocol, time consuming design analysis,
and lack of low cost components to perform the intri·
cate logic control functions. To overcome these draw·
backs, a large scale integrated (LSI) chip set has been
designed with built·in IEEE Std 488 logic controls. Thus,

1IH56

231320-001

interfacing has been significantly simplified for proper·
ly connecting processor buses and programming system
protocols.

ment. Bus functions 'encompass 16 active signal lines,
10 interface functions, the protocol by which inter·
face functions send and receive messages, and logical
and timing relationships between signal states.
Functional requirements of the standard can be in·
corporated in either" hardware, software, or a com·
bination of both. Some designers have chosen the hard·
ware approach to incorporate 'all the interface func·
tions, using about 200 medium scale integrated (MSI)
and small scale integrated (SSI) packages. 'This tech·
nique costs about $1000 for a complete interface
board. As a result, many cost sensitive implementa.
tions of the bus interface use only a subset of its
functions custom tailored to the requirements of the
devices involved, thereby red~cing package count and
expense by curtailing the interchangeability advantages.
"Other designers have selected the software" approach
to implement the bus' interface. One disadvantage of
this approach is that programming is an expensive and
extended project; another is that a subroutine" has to
be executed with each transferred byte. This overhead
not only burdens the microprocessor within a device,
, but also reduces the overall speed of the bus. This
approach costs about $200 for' the interfacing functions.

Interfac:e Overview
The IEEE Standard 488·1978 bus interface includes
'electrical, mechanical, and functional specifications * "
for interconnecting both programmahle and non pro·
grammahle electronic measuring apparatus with other
apparatus and accessories necessary to assemble in·
strumentation systems. The functional specifications
occupy about 80% of the document and involve a
proportional amount of system design time to imple.
"This article deals with the functional aspecls (interface sisnals
that exist on the physical bus) of IEEE Std 488-1978, and is not
intended as a complete dissertation on the major elements of the
standard. For detailed definitions of the mechanical (physical
cable connections), electrical (timing, voltages, lUId 'currents),
and operational (application software routines) technicalities,
interested readers should consult the IEEE Standard Digital
Interlace lor Programmable I"'trumelllation, IEEE Std 488·1978,
Institute of Electrical and Electronics Engineers, Inc, New York,
NY 10017, Nov 30, 1978-Ed.

DATA BUS LINES

•••ii~~R•••~r-

CONTROL
INTERFACE
LINES FOR
MANAGEMENT

Fig 1 IEEE Std <188 active signal lines'
for multiple devices. Peripheral devices
of different characteristics can be easily
connected to standard bus Interface.
Controlier (or processor), such as minicomputer, enables and disables talkers
and listeners and manages overali bus
activity. Bubble memory functions as
both talker and", listener. As listener,
printer receives characters to be printed.
As talker, counter transmits measurements to both controlier and listeners

INPUT/OUTPUT)
1·8

10-157

231320-001

Combinational hardware/software approaches, although faster than direct software implementations,
still require enormous design time and cost about $1000
for a typical interface board.
.
With a recent alternative approach, however, the
bus interface is easier and less expensive to incorporate
in instrument designs. LSI circuit chips now include as
built-in capabilities most of the functional and some
of the electrical portions of the Standard's specifications, significantly reducing design time and costing
about $50 for bus interfacing. Additionally, Intel's
8291/8292 General Purpose Interface BUB (CPIB)
peripheral chip set also incorporates capabilities for
bus monitoring, data rate manipulation, and addressing to further simplify bus interface designs.

Bus Signal Definitions
The IEEE Std 488 signals are defined as negative true,
'Where the high state (0 = false, ~2.0 V) and the
low state (1 = true, :5:0.8 V) are based on standard
transistor-transistor logic (TTL) levels. Of the 16 active
signal lines, 8 are data lines, 5 are interface -manage-

~

1
DAV
ITALKER)

.

r==s----1r--

-li----41

'C"1

ment lines, and 3 are handshake lines (Fig 1). Data
input/output lines (D101.D108) carry AScII-coded information, as well as device addresses, universal commands, or program instructions. Interface management
lines help to supervise the data lines. The primary
management line-Attention (ATN)-determines how
data lines are processed. When ATN is true, data lines
are interpreted as addresses or universal commands
by all bus connected devices. When ATN is false,
only those devices addressed can use the data lines;
in this case, data transmitted are typically devicedependent. With another management line, Interface
Clear (IFC), the bus controller returns the system to
a known quiescent state. The Service Request (SRQ)
line can be used by any device on the interface bus
when it has data to send (talker) or needs to receive
data (listener). The Remote Enable (REN) line determines whether the system is under front panel or
program control. The End Or Identify (EOI) line can
be used as a delimiter by a talker (sending) device
to indicate an end of message, or by the controller
as a polling line.
Handshake lines control the timing relationship of
the interface bus (Fig 2). The Data Valid (DAV) line

TALKER LETS DAV GO HIGH TO ACKNOWLEDGE
{ THAT DATA HAVE SEEN ACCEPTED; TALKER CAN
NOW CHANGE DATA.
TALKER SEES THAT ALL LISTNERS HAVE
{ ACKNOWLEDGED THAT DAV IS HIGH; IT HAS
CHANGED THE DATA AND PULLS DAV LOWTO
TELL LISTENERS THAT THE NEW DATA ARE vALID
DATA VALID

~

ND".C - n lLI--+---'1~~..L.--f
Ii:
ILiSTENERS)
FIRST LISTENER TO ACKNOWLEDGE DAV HIGH
.PULLS NDAC LOW
LAST LISTENER HAS FINALLY ACCEPTED DATA
I
I
I
AND RELEASED NDAC.

I

rL,,

:I,

i

I

NRFD
ILiSTENERS) - - - L I I - - l

I

-!----i---- (

I

"

i

~I

I

U

. L

,

'-----

FIRST LISTENER TO ACKNOWLEDGE DAV LOW
AND ACCffi' DATA PULLS NRFD LOW

( LAST LISTENER HAS FINALLY SEEN DAV HIGH
AND RELEASES NRFD
( WHEN IT SEES _lOW AND HAS ACCEPTED

~~~L~~eci'~~N::L~~~~A~W AND

( WHEN IT SEes DAV HIGH. EACH LISTENER PULIS

Fig 2 Three-wire handshaking
between single talker and several
listeners. Before transfer begins,
listener indicates It Is ready by
asserting 'Ready For Data (RFD)
message to' true. Talker then
drives all eight data inputloutput
lines. Following settling time
specified by standard, talker asserts Data Valid (DAV) message
to true. While data are. being
read, 'RFD message is asserted to
false 'since device Is unable to
receive additionai data. As each
listener completes its read, it
indicates acceptance by asserting Data Accepted (OAC) message to true; DAC is 'not sensed
true by talker until all listeners
have completed read. After each
device indicates acceptance, it
Indicates readiness for data by
asserting RFD to true. New cycle
begins when 'all devices have
asserted RFD 10 true

NDAC LOW AND SIMULTANEOUSLY RELEASES NRFD

10-158

231320-0(11

Vee

EO!
NiiAC
Nifi'ii
OAV

DiOi
0107

Di06
Di06

GPIB LINES

0104

I

0103

00

ffi02

01

Oi01

D.

SRC

03

MICROPRO'CESSOR

DATA LINES

ATN

1

.- --- ---

04

REN
IFC

06.

RS2

07

RS1

VSS

RSO

----

} ADDRESS INPUTS
FROM MICROPROCESSOR

--- --- -...,
I

TO
NONINVERTING
BUS TRANSCEIVERS

L

____________________

~

Fig 3 GPIB talker/listener chip. 8291 chip c;:onnects 8·bit microprocessor to noninverting 'bus transcelvers, which, In turn, connect to IEEE Std 488 bus. Microprocessor manipulates data bytes after
receipt or 'before transmission, and monitors talker/listener status. Single chip handles all IEEE Std 488
interface functions, except controller functions

10-159

231320-001

A-CAPABILITY DEFINED BY 488-1978 STANDARD
B -CAPABILITY DEFINED BY DESIGNER
I -INTERFACE BUS SIGNAL LINES
2 - REMOTE INTERFACE MESSAGES TO AND FROM INTERFACE FUNCTIONS
J - DEVICE DEPENDENT MESSAGES TO AND FROM DEVICE FUNCTIONS
4· STATE LINKAGES BETWEEN INTERFACE FUNCTIONS

5 - LOCAL MESSAGES BETWEEN DEVICE FUNCTIONS AND INTERFACE FUNCTIONS
(MESSAGES TO INTERFACE FUNCTIONS ARE DEFINED; MESSAGES FROM INTERFACE
FUNCTIONS EXIST ACCORDING TO DESIGNER
6 - REMOTE INTERFACE MESSAGES SENT BY DEVICE FUNCTIONS WITHIN CONTROLLER (8292)

Fig 4 Bus Interface functlons_ Messages received from Interface bus can cause state transitions, Just
as state transitions can cause messages to be sent on bus (1 and 2). Device dependent data are transferred automatically to microprocessor, without affecting state transitions (3). State changes In one function can cause state changes in another function, resulting In message to be sent (4). Microprocessor
can also send local messages to interface functions (5) or remote messages to interface (6)

10-160

231320-001

is used by a talker device to indicate that data are
ready to transmit. The Not Ready For Data (NRFD) and
Jlfot Data Accepted (NDAC) lines are used by a listener
to indicate readiness to receive data and receipt of
data, respectively. As a result, a talker knows when
all listeners on the bus have received an 8·bit byte
of information. Thus, the transmission rate of the bus
is only as fast as the slowest listener.
Messages conveyed by all 16 lines are true or false,
depending on the states of 10 interface functions. The
standard defines each of these interface functions with
state diagrams. A function's state can be changed by
a controller, another device on the bus, or a state
change in another function within a device. Of the
10 interface functions, four provide basic communica·
tion capabilities: Source Handshake (SH), Talker (T),
Acceptor Handshake (AH), and Listener (L). These
functions affect the three handshake lines (DAV, NRFD,
and NDAC), eight data lines (DIol.DI08), and EOI man·
agement line. The Device Clear (DC) and Device Trigger
(DT) interface functions are used to initialize and to
trigger a device, respectively. The Parallel Poll (pp)
functibn acts with the EOI line to send a single bit
of status information. The Service Request (SRQ) func·
tion controls the SRQ management line. The Remote
Local (RL) interface uses the REN management line in
conjunction with front panel control. The Controller
(C) function, which is active in only one device on
the bus at a time, determines which device talks or
listens.
.
To date, these 10 interface fun~tions and their intri·
cate interrelationship and timing factors have required
difficult and time consuming efforts when designing
the interface bus into a digital system.

Talker/Listener Chip Capabilities
The 8291 GPIB talker/listener chip, a 40·pin LSI device
(Fig 3), performs the inversion necessary to connect
an 8·bit microprocessor bus to the negative tru~ IEEE
Std 488 bus. In addition, this chip implements most
of the Standard's required functions. The microprocessor
sets the talker/listener chip to an initial state, manipu·
lates bytes before or after transmission, performs inter·
rupt service routines, causes state changes,' monitors
other state changes, and enables and disables chip
capabilities.
Without ,microprotessor involvement, the talker/
listener chip implements all interface functions, ex·
cept controller performance, such as handling data
transfers, handshake protocols, listener/talker address
procedures, device clearing and triggering, service
requests, and parallel and serial polling schemes
(Fig4).
Within the chip architecture are eight read (output)
and eight write (input) registers. One input register
holds the data that are to be moved from the bus
to the microprocessor when a device is listening. An
output register holds the data byte that is to be

10-161

transferred to the bus when a device is ready to
talk. The other seven write and seven read registers
control various chip functions.
Interrupt status registers 1 and 2 store 12 different
interrupt flags. For example, one bit in the Interrupt
Status 2 register reflects changes in a device's ad·
dressed state. The microprocessor can poll both regis'
ters to determine which flag, caused the interrupt, and
can then branch to the appropriate service routine.
Two corresponding interrupt mask registers allow de·
signers. to mask any interrupt. A 'serial poll status
register holds device status information, and a serial
poll mode register is available so that the micro·
processor can verify ,this status. An address mode
register contains a device's addressing mode, as de·
termined by the microprocessor. An address status
register monitors the address status (ie, active talker
or active listener) of a device.
Two address registers store the assigned device ad·
dresses. An End.Of·Sequence (EOS) register contains
a designer specified end of string code for delimiting
data block transfers by flagging the last byte with
EOI. A command' pass.through register feeds non·GPIB
commands to the microprocessor. An auxiliary mode
register holds local messages to control reset, power
on, etc.
Among the chip's capabilities are a programmable
data transfer rate from 62k to 525k bytes/s, three
addressing modes, and an EOS message recognition.
With a programmable data transfer rate, the designer
controls the handshake rate of the interface to match
the data transfer rate to the devices on the bus.
The three addressing modes permit flexibility in
designating talkers/Iisteners. The dual primary address
mode, for example, allows both a talker and a listener
address to be assigned to a device. With the primary/
secondary address mode, multiple devices of the same
type can have the same primary address, but a different
secondary address. In the third addressing mode, de·
vices can have both dual primary and dual secondary
addresses.
Data block transfers are made easier with the EOS
register. This register holds the character that signals
an end·of·block transfer., When a data byte loaded
into the data·out register matches the byte in the EO/;
register, the talker/Iistener chip asserts the EO! line,
signaling an end of transfer.

Controller Chip Capabilities
The 8292 controller chip (Fig 5) implements the con·
troller function of the Standard. In conjunction with
the 8291,' the controller forms a complete standard
interface, including the capability of handling the
transfer control protocol. This ability gives the designer
an option to accommodate multiple controllers on a
single bus.
Additionally, the, 8292 performs all the tasks neces·
sary in a complete controller design; It responds to

231320-001

I - - - - - - READ REGISTERS I
INTEERRR~:~~~~US
I
I
cg~~:~~LS~~:Z~J~S

-

-

-

-

-

-

-

-

-

-

-

I

I
I

I
I
I
I

EVE~~~~U:rT;:A~~~TUS

I
I REN

WRITE REGISTERS

MICROPROCESSOR

SYSTEM
INTERFACE

DAv
fBFl

INTERRUPT MASK
ERROR MASKCOMMAND FIELD
EVENT COUNTER

OBF1

SYC
IFC

TIME OUT

CIC
ATNO

CLTH

--IFeR

Vee

x,

COUNT

X,

REN

RESET

DAV

Vee

lBFI

cs

OaFI

GND

EOI

R-O

SPI

Ao

TCI

VIA

efe

SYNC

NC

Do

ATffil

0,

NC

0,

CLTH

OJ

Vee

0,

NC
SYC

IFe

ATNI
SAO

Fig S GPIB controller chip. 8292 chip workll In conjunction with 8291 to perform GPIB con1roller Interface
functions. It Implements local control commands from microprocessor according to IEEE Std 488 protocol.
Additionally, It proceaaes such Inputs from bus as SRQ and EOI. Furthermore, It can send the lull repertoire
of GPIB control messages, Including REN, IFe, ATN, and EOI

10-162

231320-001

~~

________

GPIS
TRANSCEIVERS

~~~~

________________________

~'~~IEOI

~~-----------t~t---~----------------+---~~(~0~ATN

PROCESSOR

INTERRUPT WR AD RST elK

ADD

~~~~----~~-rt----r----~~----t-------i~~~~~NOAC

~~~------+-rt-r-----------------r+------t~?illh~INRFD

rt~-------r-------i;~~~~ATN

NOTES:
1. CONNECT TO NDAC FOR
BYTE COUNT OR TO EOI
FOR BLOCK COUNT.
2. GATE ENSURES OPEN
COLLECTOR OPERATION
DURING PARALLEL PULL.
J. THE TRANSCEIVER AND
GATING FUNCTIONS WILL

BE INCORPORATED IN A
FUTURE CHlP FROM INTEL.

Fig '6' System configuration using chip set. In, conjunction with 8291, 8292 performs complete controller function.
Together with shared bus transceivers, chip set forms a complete IEEE Std 488 interface. In addition, DMA interface may be implemented through 8291 with 8237 DMA controller

10-163

231320-001

service requests (SRQS), configures other devices on the
bus for remote control by sending Remote Enable
(REN), and sends Interface Clear (IFC) , allowing for
control seizure to reinitialize the bus. More important.
ly, the qontroller chip can take control of the bus
synchronously with the handshake, preventing the de·
struction of any data transmission in progress.
Internally, the controller chip has 10 dedicated
registers for programming and for monitoring status.
Through the use of the Interrupt Status and Interrupt
Mask registers, the designer can configure the con·
troller to interrupt the microprocessor on selected
events. An Event Counter and a corresponding status
register are available to monitor and control either
byte counts or block counts. A Time·Out register may
be set by the designer to program a time-out error
function; a corresponding status register contains the
current value' in the time-out counter. In conj unction
with these registers, error control can be programmed
with the Error Flags and Error Mask registers. Finally,
Controller and GPIB" Status registers are available. Each
of these registers is read or programmed through a
dedicated command buffer.
given GPIB system are handled by processor software.
For example, the processor is responsible for knowing
which device on the bus corresponds to which device
address. The processor then uses the 8291 to transmit
coded Controller commands as the 8292 asserts ATN.

Chip Set Application
The talker/listener and controller chips connect to the
standard interface bus through noninverting bus transceivers (Fig 6). These transceivers provide the 48-mA
bus drive capability needed to meet the electrical portion of the IEEE Std 488 specification-not directly possible with existing metal oxide semiconductor (MOS)
parts. The talker/listener chip can interface directly
to microprocessor memory through a direct" memory
access (DMA) controller, such as an 8237.
The microprocessor drives the talker/listener with a
short stored program (see Table), containing initialization
conditions, such as data transfer rate, address mode,
and other designer requirements. Microprocessor data
handling is limited to taking bytes off the bus after
they arrive or putting bytes of data on the bus. Inter·
rupt service routines are necessary for each unmasked
interrupt. Although 12 interrupts are available, not all
have to be used. All other standard bus functions are
handled by the 8291.
To send a byte of data, the microprocessor writes
the bYte into the talker/listener data-out register. The
chip then transmits the data byte over the bus lines
in . conj unction with the handshake lines. Next, the
NRFD line is checked to see if it is ready for data.
If a ready for data message is detected, the talker/
listener sends a DAV signal until it receives a data accepted message from the interface's NDAC line. The
8291 also generates a Byte Out (BO) interrupt, setting
the BO flag in the interrupt status register. When its
interrupt pin is activated, the microprocessor reads the
interrupt status register and responds to the interrupt
with an appropriate service routine.
The 8292 handles all hardware aspects of the con·
troller function: SRQ input, ATN, IFC, EOI, and REN
outputs. Meanwhile, the designer defined aspects of a

Summary

10-164

Bus" interface designs that previously required 150 or
200 MSI/SSI chips may now be implemented with a
GPIB peripheral chip set. For designers, this hardware
set means less design time and cost, resulting in increased reliability and versatility in IEEE Std 488 bus
interfaces custom programmed for dedicated applica.
tions.

Bibliography
S. C. Baunach, "Design Advantages and Limitations in Connect..
ing Computational and Readout Equipment to the cpm,"
Western Electronic Show and Convention, "Sept 1976
A. Karninker and A. Men.chern, "LSI Facilitates GPm Implementation,tt IEEE Proceedings on Microcomputer Based Instrumentation, June 1978
D. C. Loughry and M. S. Allen. "IEEE Standard 488 and Microprocessor Synergism," Proceedings oj the IEEE, Feb 1978

Ronald M. Williams Is a product manager for peripheral controllers in Intel's
Microcomputer Components Division.
In addition to GPIB devices, he has
been involved in Introductions of dynamic RAM and CRT controllers. He
holds a BS degree from Trinity College,
an MS degree from Rensselaer Polytechnic Institute, and an MBA degree
from the University of Chicago.

231320-001

inter
DATA ENCRYPTION
TUTORIAL
The proliferation of electronic data processing (EDP)
applications that involve the storage and the distribution
of potentially sensitive information have demonstrated
the need for mechanisms to insure data privacy and
security. As society becomes increasingly dependent on
computers and data communications networks, this need
becomes even more acute.
Cryptography

The most efficient technique of providing data security is
cryptography: the transformation of datil via a secret
code into a form which is useless to anyone but authorized recipients.
A cryptographic algorithm can'be presented as a sequence
of mathematical transformations. Each transformation
has it's unique inverse operation that changes the
encrypted data back into the original plain text. In conventional cryptosystems, a set of specific parameters
called a key is supplied along with the plain text/ cipher
text as an input to the enciphering/ deciphering algorithm. The key is specified by the user. The transformation of the plain text and the cipher text depends on the
key as well as the enciphering and deciphering algorithms. In fact the algorithms themselves can be made
public, because the security of the system depends
entirely on the secrecy of the key.
The initial interest in encryption for commercial applications came from financial institutions, most notably
banks that are heavily involved in Electronic Fund
Transfer (EFT). The American banking system alone,
moves more than $400 billion between computers every
day. The rapid rise of personal computers, workstations
and the use of electronic mail and information retrieval
services have spread the need for insuring data privacy
and security to many other applications.
The DES

In response to the growing commercial need, the National
Bureau of Standards has adopted in 1977 a standard
algorithm know as the Data Encryption Standard (DES).
The DES, originally developed by IBM, is designed for
use with sensitive but unclassified information. The

National Bureau of Standards requires that the DES be
implemented in system hardware. The standardization
insures that certified hardware from different suppliers
are compatible.
The DES specifies a method for encrypting 64 bit blocks
of clear data into corresponding 64 bit blocks of cipher
text using a56 bit key user specified. The 56 bit key (64 bit
with parity) gives the user a total of 256 (seventy quadrillion) possible keys. Because the DES algorithm key is so
,long, a state of the art computer would take years to
explore all possible permutations required to break the
code. The most critical factor in protecting the data is
guaranteeing the secrecy of the key.
Intel Data Encryption Product Line

Intel offers two peripherals supporting the DES algorithm: the 8294A Data Encryption Unit (DEU) and the
82538 Data Ciphering Processor (DCP).
The 8294A -a preprogrammed 8042- can encrypt and
decrypt data at a rate up to 400 Byte/ Sec. The 8294A is
very well suited for data file protection, off line data
encryption prior to transmission and phone line
applications.
The 82538 is a much faster device: 1.5 Mbyte/ Sec. This
encryption rate is needed in satellite communications
systems, data storage onto hard disks, high performance
data communications networks like Ethernet. This rate is
high enough to accomodate on the fly encryption in most
of the communications systems and eliminate the need
for buffers and interfacing circuitry. High encryption and
decryption speed is not the only feature ofthis device. The
82538 supports bi-directional, half-duplex operations at
its top speed. It contains three separate write only registers for encryption, decryption and master keys improving system's security and throughput. The DCP can also
be configured in any of the three encryption/ decryption
modes recommended by the NBS (ECB, CBC or CFB).
The Intel Data Encryption product line solves the, need
for a broad range of applications. Security features can
now be economically designed in data entry terminal as
well as in satellite communications systems.

Intel Corporation Assumes No Responsibility for the Use of Any Circuitry Other Than CIrcuitry Embodied in an Intel Product. No Other Circuit Patent
Licenses are Implied. Information Contained Herein Supersedes Previously Published Specifications On The Devices From Intel.
©INTEL CORPORATION, 1964,

10-165

JANUARY 1_984
ORDER NUMBER: 231031·001

OpenNETTM
Product Family

11

intJ
iSXMTM 554 MAP COMMUNICATIONS ENGINE

•

•

•
•
•
•

Provides Networking Capability for
MULTIBUS@ Based Systems Running
Under any Operating System
Serves as a Complete Front End
Communication Engine With the
Capacity to Provide MAP Layers 1
Through 7 Capability for MULTIBUS@
Based Hosts

•

Runs Intel's Proven iNA 961 Rei 2.0
Providing the ISO 8073 Transport
Software and ISO 8473 Internet
Software for IEEE 802.4 LANs

•
•

On Board Diagnostic and Boot
Firmware

•
•

8 MHz 80186 Processor
256 Kaytes of RAM of Which 128
KBytes are Dual Portable
10 Mbps IEEE 802.4/Token Bus
Interface
Sockets for up to 4 JEDEC 28 Pin
Memory Devices, up to Maximum of
160 KBytes EPROM Storage
One iSBXTM Bus Connector for I/O
Expansion Capability
Can Be Configured as Either a Master
or a Slave in MULTIBUS@

Supported by Intels' Implementation of
MAP Software for Layers 5-7 Which
Can Be Run on Board

The iSXM 554 COMMengine product is designed to fit into front end LAN Communication processor applica·
tions. It allows the connection of MULTIBUS-based systems onto a MAP/IEEE 802.4 (Token Bus) LAN.
COMMengines are dedicated communication processor boards. They allow the host processor board to off·
load LAN communication r$lated tasks onto the front end COMMengine. Therefore the host has more processing capability for user applications or other tasks. COMMengines also allow the networking of existing
systems without forcing a redeSign of the entire system architecture.
The iSXM 554 board can be used as a front end COMMengine for a MULTIBUS-based host running any
operating system. This is because the on board software provides a high level interface to the host (e.g.,
transport level commands). This results in a powerful system building block which enables an OEM to connect
MULTIBUS-based systems onto IEEE 802.4 10 Mbps LANs. Applications for the iSXM 554 include networked
iRMXTM-based systems for real time applications and networked XENIX· systems for laboratory and data
base application. The iSXM 554 is preconfigured to run iNA 961 R2.0 transport and network software. iNA 961
R2.0 is a preconfigured version for the iSXM 554 of Intel's iNA 960 LAN software which implements the ISO
8073 Class 4 transport protocol and the ISO 8473 internet network layer· ·protocol.
The iSXM 554 has the processing and memory capacity to accommodate an on board implementation of the
MAP software for layers 3 through 7 of the ISO OSI model. Intel will provide an implementation of the MAP
layers 5 through 7 as a product. This will be available in a version preconfigured to run on the iSXM 554. The
iSXM 554 coupled with iNA 961 R2.0 (layers 3 and 4) and the MAP layer 5-7 software will be an ideal turn key
solution for OEMs requiring a 7 layer MAP specification communication. engine.

iSXMTM 554 FUNCTIONAL DESCRIPTION
The iSXM 554 board is a preconfigured MAP Communication Engine with boot firmware and 256K bytes of
RAM. The iSXM 554 board is offered for use with iNA 961 R2.0 preconfigured ISO 8073 transport plus ISO
8473 network layer software. The iSXM 554 firmware provides the capabilities to load iNA 961 R2.0 onto the
iSXM 554 from either a buffer in the local host or remotely from another Token Bus station. It also performs a
variety of on-board diagnostics.
.

'XENIX is a trademark of Microsoft Corporation.

Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
August 1985
@ Intel Corporation, 1985
Order Number: 231594-001

11-1

inter

iSXMTM 554

The iNA 961 R2.0 software and the iSXM 554 board
together provide the functionality of a preconfigured
OS independent transport engine. In addition to
transport services, iNA 961 R2.0 software also includes ISO 8473 Internet network layer, extensive
data link and network management facililty services.
Figure 1 shows the configuration of iNA 961 R2.0.
Table 1 shows some examples of functions provided
by iNA 961 .R2.0. iNA 961 R2.0 is a preconfigured
version of iNA 960. Refer to the iNA 960 data sheet
for more iNA 961 R2.0 information.

Intel will also provide an implementation of the MAP
software for layers 5 through 7 as a product. Refer
to the MAP version 2.1 specification for more information. This implementation of layers 5 through· 7
will run on the iSXM 554 along with iNA 961 R2.0.
The iSXM 554 coupled with the software packages
will be a high performance, 7-layer communication
engine (see Figure 1).

"OPEN SYSTEMS"
ISO MODEL

I

n'N'rnvORK
MNGT.

I

END USER
APPLICATION
PROCESS

I

(COMMUNICATION)
APPLICATION

7. ]

PRESENTATION

6

SESSION

5

OR

MAP
LAYERS 5·7
ON BOARD
'

HOST
PROCESSOR

" '. TRANSPORT

0,..,// ,.- ',' " , '
~NF'~.~,Rt( ,~

~,~
DATA
,/

LINK':
.

:

iNA 961/iSXMTM 554

SYSTEMS

.

~TOKENB~~~
PHYSICAL' /"

231594-1

Figure 1. INA 961 Configuration on ISXMTM 554 Board
Table 1.INA 961 R2.0 Services

!

Transport

Virtual circuit
open: establish a virtual circuit database
send connect: actively try to establish a virtual connection
await connect: passively awaits the arrival of a connection request
send: send a message
receive: post a buffer to receive a message
close: close a virtual circuit
Datagram
send: send a datagram message
receive: post a buffer to receive a datagram message

Network

Internetworking
routing between multiple lans
segmentation/reassembly
user defined routing tables
Multiple subnets supported
user supplied
802.3, 802.4

11-2

inter

ISXMTM 554

Table 1.INA 961 R2.0 Services (Continued)
Data Link

Transmit: transmit a data link packet
Receive: post a buffer to receive a data link packet
Connect: make a data link logical connection (link
service access point. IEEE802.4)
Disconnect: disconnect a data link logical connection
Change token bus address
Add multicast address
Delete multicast address
Configure TBH

Network
Management

Read/Clear/Set network objects (local/remote):
read/clear/set local or remote iNA 960 network parameters
Read/Set network memory (local/remote):
read/set memory of the local or a remote station
Useful in network debug process
Boot consumer: requests a network boot server to
load a boot file into this station
Echo: Echo a packet between this station and
another remote station on the network
second quadrant is memory mapped Token Bus
Handler address. The third quadrant (512-768K
Byte) maps into two MULTIBUS windows (128K
Byte each). These windows allow the iSXM 554
board to access the total 16M Byte of MULTIBUS
memory in 128K Byte segments. The fourth quadrant (768-1 M Byte) is local ROM which contains the
80186 firmware, the Token Bus station address, and
relocated 80186 internal registers.

ARCHITECTURE DESCRIPTION
The iSXM 554 board consists of the following major
architectural blocks (see Figure 2): an 80186 processor running at 8 MHz, the Token Bus channel
based on the Token Bus Handler chip set and the
Token Bus Modem, the on·board memory consisting
of ROM and RAM, the iSBX interface, and the
MULTIBUS interface.

The two 128K Byte MULTIBUS windows each start
on 64K Byte boundaries anywhere in the 16M Byte
MULTIBUS memory. The starting location of either
window is determined by writing to a local I/O
mapped latch.

PROCESSOR
The iSXM 554 board contains an 80186 processor
operating at 8 MHz. It is responsible for implement·
ing the intelligent interface between the iSXM 554
board and a host processor. The 80186 processor
runs the iNA 961 R2.0 transport software and the
data link software needed by the Token Bus Handler
chip set. It is responsible for the delivery of data
between user buffers in MULTIBUS memory and
iNA buffers on the iSXM 554 board. The iNA software is responsible for the reliable transfer of information across the Token Bus LAN.

Options on t~e iSXM 554 allow up to 128K Byte of
RAM to be accessible by the host. This dual port
RAM is jumper selectable to appear anywhere in the
MULTIBUS 16M Byte memory space on 128K Byte
boundaries. The dual port RAM memory is a data
link between the on board 80186, the token bus controller, and the bus master (if any) managing the systems functlbns. This shared dual port RAM can be
used to transfer command, status and data between
the on board 80186 processor and the host. This
feature minimizes the necessity for the 80186 to access MULTIBUS while acquiring shared information.
This has a direct positive effect on performance,
serving to eliminate bus contention.

MEMORY
The one megabyte address space of the 80186 is
divided into four quadrants (see Figure 3). The first
quadrant (0-256K Byte) is local RAM memory. The

11-3

intJ

ISXMTM 554

ISBX™
INTERFACE

B01B6

INTERNAL BUS

TOKEN
BUS
MODEM

TOKEN BUS
HANDLER

TOKEN BUS
CONNECTION

MULTIBUS@SYSTEM BUS

231594-2

Figure 2. ISXMTM 554 Architectural Blocks

MULTIBUSa!>
SYSTEM BUS

100000(H)

FFFFFF(H)

FFFFF(H)

80186
ADDRESS SPACE

EPROM-MEMORY
SPACE

EOOOO(H)
DBOOO(H)

EPROM / EEPROM

DOOOO(H)

STATION ADDRESS

C8000(H)

NOT USED

COOOO(H)
128K

128K

f.-ANY 128K BLOCK

~

I--- ANY

TWO
128 K BYTE
- - - -MULTIBUS ®
WINDOWS

--

128K BLOCK

80000(H)
40500
40400

MEM BYTE
SPACE

40000(H)

NOT USED
-------80186 REGISTERS
------------TOKEN BUS HANDLER

RAM MEMORY
SPACE

OOOOOO(H)

_

OOOOO(H)
231594-3

Figure 3. ISXMTM 554 Memory Configuration

11-4

intJ

iSXMTM 554

For those applications requiring processing capacity
and the benefits of multiprocessing (Le., several
CPUs andlor controllers logically sharing system
tasks through the communication of the system
bus), the iSXM 554 provides full MULTIBUS arbitration control logic.

TOKEN BUS INTERFACE
The Token Bus interface on the iSXM 554 is implemented by the Token Bus Handler (TBH) chip set
and the Token Bus Modem (TBM). Data is transferred between the on-board memory and the TBH
by the TBH initiated DMA. The TBH will then pass
data, operating according to the IEEE 802.4 Token
Bus Specification, to the TBM which handles the
physical interface to the Token Bus.

iSBXTM INTERFACE
One 8/16 bit iSBX MULTIMODULETM connector is'
provided on the iSXM 554. Through this connector,
additional on-board 1/0 functions may be added.
iSBX MULTIMODULE boards optimally support
functions provided by VLSI peripheral components
such as additional parallel and serial 1/0, analog
1/0, small mass storage device controllers (e.g.,
cassettes and floppy disks) and other custom interfaces to meet specific needs. By mounting directly
on the iSXM 554, less interface logic, less power,
simpler packaging, higher performance, and lower
cost results when compared to other alternatives
such as MULTIBUS form factor compatible boards.
The iSBX connector on the iSXM 554 board provides all signals necessary to interface to the local
on-board bus, including 16 data lines for maximum
data transfer rates. iSBX MULTIMODULE boards
designed with 8-bit data paths and using the 8-bit
iSBX connector are also supported on the iSXM
554. A broad range of iSBX MULTIMODULE options
are available in this family from Intel. Custom iSBX
modules may also be designed for use on the iSXM
554 boards. An iSBX bus interface specification and
iSBX connector documentation are available from
Intel.

Each iSXM 554 board is manufactured with a unique
default Token Bus network address stored in an address PROM. This address PROM is protected by
checksum and can be read by utilizing the on board
1/0.
MULTIBUS@ INTERFACE
The iSXM 554 board can access the MULTIBUS
with an 8- or 16-bit data path and can support up to
24 address bits. The internal 80186 registers are relocated into the local memory map to avoid conflicts
with MULTIBUS 1/0 during 80186 internal register
accesses. The iSXM 554 is capable of accessing the
MULTIBUS I/O from 384-64K (180H-FFFFH) Byte
of 1/0 space locations.
A host processor in a system communicates with the
iSXM 554 board via a flag byte port in the MULTIBUS interface. The flag byte port is presented as a
MULTIBUS 1/0 port to the host processor. The location of this 1/0 port on the MULTIBUS is configurable on the iSXM 554. To the 80186 processor on the
iSXM 554 board, the flag byte is in a local 1/0
mapped location.
The flag byte port is used by the host processor. to
reset the iSXM 554 board, to interrupt the 80186
processor and to reset a MULTIBUS interrupt generated by the iSXM 554 board. The iSXM 554 uses the
flag byte to set or clear an interrupt to the MULTIBUS, or clear an interrupt from the MULTIBUS (Table 2).
Table 2. Flag
Value Written
to Flag Byte Port

Source

1

iSXMTM 554

2

3

ISlCMTM 554 USER INTERFACE
The iSXM 554 board commu~icates with a host
processor through a handshake of interrupts. The
host processor can generate flag byte interrupts to
the 80186 on the iSXM 554. The iSXM 554 can generate MULTIBUS interrupts to the host processor.
The host processor and the iSXM 554 can also comByte Ports
Actions
Clears interrupt to the MULTIBUS@

MULTIBUS@

Resets iSXMTM 554 board

iSXMTM 554

Sets interrupt to the MULTIBUS@

MULTIBUS®

Sets interrupt to the iSXMTM 554 board

iSXMTM 554

Clears interrupt to the iSXMTM 554 board

MULTIBUS®

Clears interrupt to the MULTIBUS®

11-5

ISXMTM 554

col between MULTIBUS processors. An implementation. of the MIP protocol is provided on the iSXM
554 for communication with the host. The corresponding IYIIP protocol implementatio·n will have to
be provided by the user on the host side for communicating with the iSXM 554. Figure 4 illustrates how·
this message delivery functions. Commands are
passed between the iSXM 554 and the host proces,
sor in the form of request blocks. A request block is
a buffer that contains a command specification and
the command parameters. Each request block (or
equivalently, each command) is reliably delivered
from the host processor to iNA 961 R2.0 via the MIP
facility. iNA 961 R2.0 will extract the command information and carry out the command. After a command is done, iNA 961 R2.0 will use the MIP facility
to return the command result to the user program.

municate through shared MULTIBUS system memory. As much as 128K byte of the on-board RAM on
the iSXM 554 is accessible to the host processor
and the iSXM554 can read and write all of the 16M
byte of MULTIBUS system memory.

OPERATING ENVIRONMENTS
The iSXM 554 is designed to function in any MULTIBUS system as a communication processor. It can
function as both a MULTIBUSbus master or a slave.
As a MULTIBUS master, it can access up to 16M
Byte of host memory and 64K byte of 1/0 address.
As a MULTIBUS slave, it occupies one location reserved for the flag byte.

iI,

INA 961 R2.0 USER INTERFACES

iNA 961 R2.0 request blocks are
the same formats as iNA 960 commands. Refer to the iNA 960
data sheet and reference manuals for more details
on the iNA 961 R2.0 software.

User programs give .iNA 960 commands to the iNA
961 R2.0 software on the iSXM 554 board via the
MULTIBUS Interface Protocol (MIP). MIP is an Intel
reliable process to process message delivery proto-

INA
961 MIP
DRIVER

USER

USER'
MIP
PROGRAM 1+---4 DRIVER

1

iNA 961
sorTWARE

TRANsrER or
REQUEST BLOCKS
(COMMANDS)

S
y
S
T

E
M

B

HOST PROCESSOR

U

iSMXTM 554/iNA 961 R2.0

SOARD SOFTWARE

S

231594-4·

Figure 4. INA 961 MIP Interface

11-6

inter

ISXMTM 554

processor, the memory (EPROM and RAM), and the
Token Bus Interface are functioning properly.

OPERATING SYSTEMS
ENVIRONMENT
The iSXM 554 board and iNA 961 R2.0software can
function in any MULTIBUS environment. The communication between the iSXM 554 and the host
processor is entirely independent of any host operation systems. iNA 961 R2.0 uses the MIP protocol to
interface with the host processor. iNA 961 R2.0 can
service multiple processes utilizing its services at the
same time.

ORDERING INFORMATION
Part Number Modem Frequencies/Channel Pairs
SXM 554-1 Transmit: 59.75 to 71.75 MHz/Ch. 3
and 4
Receive: 252·to 264 MHz/Ch. P and

a

A host processor passes iNA 961 R2.0 commands
and buffers in the MULTIBUS system memory to the
iNA 961 R2.0 software. iNA 961 R2.0 is responsible
for updating the response fields of these commands.
It is responsible for copying the user send buffer in
MULTIBUS system memory into its on board buffers
for transmission and for copying received messages
to user buffers in MULTIBUS system memory.

SXM 554-2

Transmit: 71.75 to 83.75 MHz/Ch. 4A
and 5
Receive: 264 to 276 MHz/Ch. Rand

SXM 554-3

Transmit: 83.75 to 95.75 MHz/Ch. 6
and FM1
Receive: 276 to 288 MHz/Ch. T and U

S

SPECIFICATIONS

iSXMTM BOOT FIRMWARE USER
INTERFACE
.

Network Interface
Compatiblity/
IEEE 802.4, Token Bus 10 Mbps
Conformance
Broadband
Cable Connection 750 Output on Type F Female
Connector
Head End
Operates with Remodulator Head
End

The iSXM 554 boot firmware is used to load iNA 961
R2.0 or other software onto the 554 from either local
MULTIBUS memory or a remote network station.
The firmware performs a number of local and network diagnostics.
The iSXM 554 boot firmware commands fully support the initialization of the MIP interface. The MIP
interface is used by the host processor to communicate with the iNA 961 R2.0 once it is loaded and
started.

Host Interface
MULTIBUS@ Interface Conforms to All AC and DC
Requirements of the Intel
MULTIBUS SpeCification
DC Power Required
(Maximum Excluding
iSBX)

DIAGNOSTICS
The iSXM 554 board offers a range of power up diagnostics designed to ensure that the 80186

+ 5 VDC + 12 VDC

5.5A
-0.3A
-12 VDC -0.15A

Environmental
Temperature 0° to 60°C Operating
-40° to + 85°C Storage
Humidity • 5 to 95%, Non-Condensing, for Both
Operating and Storage

11-7

.MAP-NETTM COMMUNICATIONS SOFTWARE
MEMBER OF THE OpenNETTM PRODUCT FAMILY
• Supported by OpenNEPM-MAP hardware and software:
- iSXM™ 554 Token Bus Board
- iNA 961 Communication Software
• Implements ISO/OSI layers 5-7, as
specified 'o..1J MAP version 2.1

•

Provides MAP 2.1 ISO FTAM, Session,
CASE, Network Management/Directory
Services

• Pre-configured to [un on Intel's iSXM
554 MAP Board

The Intel MAP-NET software is a ready-to,use software building block for OEM suppliers of networked systems
and implements ISOIOSllayers 5-7, as specified by MAP version 2.1. The MAP,NET software is available preconfigured to run on the Intel iSXM 554 board which provides the IEEE 802.4 token bus connection for
Multibus® based systems. MAP-NET is designed to use the services and interface provided by Intel's iNA 961
Rei 2.0 Software package. iNA 961 Rei 2.0 provides the ISO 8473 networ~ layer, and .ISO 8073 transport. iNA
961 Rei 2:0 includes a version of this software pre-configured to run on the iSXM™ 554 board. MAP-NET can
run on top of iNA 961 Rei 2.0 on the iSXM 554 board. Together the board and software modules provide a
complete MAP solution for industrial OEM's.

7

APPLICATION

6

PRES!"NTATION

5

SESSION

4

[£J [£J
[i]

MAP-NET
SOTWARE

MAP-NETTM
SOFTWARE

TRANSPORT

3

NETWORK

2

DATA LINK

iNA 961 R 2.0
SOFTWARE

PHYSICAL
231372-2

Figure 1. ISOIOSI Reference Model MAP·NET

11-8

231666-001

inter
MAP·NET FUNCTIONAL DESCRIPTION
The Intel MAP-NET software provides the following
services specified by MAP 2.1; the session service,
network management, FTAM and CASE. These services fit into the upper 3 layers of the ISOIOSI 7 layer
model.
Using the Services of MAP-NET, users can initiate
communications with other users on a MAP LAN access information regarding resources available ~n a
LAN, transfer files across a LAN and address other
users on the LAN by logical names rather than
numbered addresses.
MAP-NET SESSION SERVICES

provides name-to-address translation for the user. By
the use of the CASE service, a process can make a
connection request to a remote process by using only the names of the processes. CASE takes these process names supplied by the user and "resolves these
names into network addresses and identification utilizing the services provided by the MAP-NET Directory
Service.
This greatly increases the ease-of-use of network
Services provided by the underlying layers.
MAP-NET FILE TRANSFER
ACCESS MANAGEMENT

The MAP-NET Session software implementation provides the Session services specified in the MAP version 2.1 specification. The session service is built on
top of the iNA 961 transport service. iNA 961 provides
the class 4 services of the ISO transport specification and the ISO internetwork specification. The Session service supports all of the services provided by
the underlying transport layer. Besides, the session
layer also provides a 'graceful close' service. This service enables a user to release a session connection
without the loss of any outstanding requests. The
'graceful close' feature is in addition to the 'abort'
method of close provided by transport.

The FTAM Software provides remote file transfer
capability. This capability is provided by the implementation of file request 'Initiator' module and a file request 'Responder' module. The Initiator intercepts file
commands from the local user and transmits them
across the LAN to the Responder at the node where
the target file resides. The Responder receives, interprets, and executes the command acting as a user
on its local node. File transfer between nodes is made
possible by the implementation of a common set of
file transfer protocols defined by the ISO FTAM
Specification.

MAP-NET DIRECTORY SERVICES

1)
2)
3)
4)

The MAP-NET Directory Services software maintains
a database of network objects such as node names,
user names, etc... , and related properties. For example, the directory services can be used to store the
name of a Iletwork user and his network addresses
as the properties associated with his name. A network
user or application can query the directory service to
retrieve information from this database. Users can also
add or delete objects and properties from this
database.
MAP-NET CASE
The MAP-NET Common Application Service Elements
(CASE) is built on top of the MAP-NET Session
Service.
CASE is designed to support all the services provided by the lower ISO layers. In addition, MAP 2.1 CASE

MAP-NET FTAM allows a user to:
Create files on a remote node.
Write into files on a remote node.
Read files on a remote node.
Delete files on a remote node.

To perform the above functions the Initiator module
should be configured in the user's node and the
Responder should be configured in the remote target
node. MAP-NET FTAM implementation allows a node
to be 1) a file Initiator only, 2) a file Responder only
and 3) both a Initiator and Responder.
SUMMARY
Coupled with the iSXM 554, iNA 961; MAP-NET provides a complete 7 layer solution based on open
standards for the OEM. MAP-NET is another of the
OpenNET products and therefore is a continuing commitment by Intel to the Open Systems for LAN's
strategy.

11-9

inter

iSBC® 552 AND iSXMTM 552 ETHERNET
COMMUNICATIONS ENGINE PRODUCTS
MEMBE,RS OF THE OpenNETTM PRODUCT FAMILY

• Provides networking capability for all
MULTIBUS@ systems regardless of the
operating system of the host
• Supports XENIX*- and RMX-Network
File Service (XNX-NET and RMX-NET)
products
• Available In two versions
, - Turn-key controller Implementing
ISO 8073 Class 4 Standard Transport
functionality (ISXMTM 552 board) on .
IEEE 802.3 LANs
- Flexible, Intelligent communications
controller for ISBC@ 552 board for
custom configurations on IEEE 802.3
LANs

• ISXMTM 552 board Is fully qualified as
system extension module for the
86/310,286/310,86/380 and 286/380
Intel systems
• Resident network software can be
down loaded (SXM) or stored In onboard PROMs (SBC)
• Runs INA 960 and INA 961 (SXM)
transport software
• On-board diagnostic and boot firmware
(SXM)

The iSBC 552 and iSXM 552 COMMengine products are designed for communications front end processor
applications connecting MULTIBUS systems onto IEEE 802.3/Ethernet LANs. COMMengines are dedicated
to the communications tasks within a system allowing the host to spend more time processing.user applica·
tions. A major advantage of COMMengines is that they can be used to network existing systems and estab·
lished designs without forcing the redesign of the entire system architecture.
The iSBC and iSXM 552 boards can be used with any operating system because they require only a high level
interface to communicate with the host '(ego transport commands in case of the iSXM 522 board). The result
is a powerful system building block which enables the OEM to connect MULTIBUs.based systems with different
operating systems to the same network. Applications for the 552 products include networked multiuser XENIX
286 based systems for the office and iRMX-based systems for real time applications. The iSXM version is a
transport engine complete with on board RAM and ROM memory preconfigured to run iNA 961 transport software.
iNA 961 software is a version of Intel's iNA 960 LAN software implementing the ISO 8073 Class 4 protocol
specifically configured to support the iSXM 552 board. ThelSBC 552 board is a "de-bundled" version of· the
iSXM 552 board; it comes without memory and software allowing greater flexibility for the user to adapt the board
for his special requirements.

Intel Corporation assumes no responsibility for the use of any circuitry other than .cIrcuitry embodied In an Intel product. No other circuit patent
licenses are Implied, Information contained herein supersedes previously published specifications on these devices from Intel. February 1885
@ Intel Corporation, 1985
·XENIX Is a trademark of MICROSOFT CORP.

11-10

ISBC 552 /lSXM 552

The ISBC® Board vs. the iSXMTM 552
Board
The fundamental difference between the two versions
is the iSBC 552 board offers the hardware necessary
for the user to construct an Ethernet front-end processor for his unique requirements and the iSXM 552
board provides full ISO standard transport services
ready to plug in and to be used without any additional
configuration effort. The SXM version is arrived at by
populating the iSBC 552 board with 16K bytes of ROM
and 80K bytes of iRAM, and by providing iNA 961, a
directly downloadable transport software module. The
iSXM 552 board is configured for Intel's 861286-310
systems and fully qualified to run in these systems.
iSXM 552 customers receive the iNA software with the
purchase of the iNA 961 license which is an integral
part of the SXM offering.

ory and iNA960/961 buffers on the iSBC and iSXM
552 boards. iNA 960 and 961 software is responsible for the reliable transfer of information across
Ethernet.
The 80186 and 82586 both use asychronous ready
logic. The 80186 chip select lines are used to select
memory' mapped I/O locations.
The 80186 supplies the timers and the interrupt controller on iSBC 552. The interrupt controller is used
in the fully nested mode. The inputs and the outputs
of the 80186 timers are not connected to external
sources and destinations. Timer clocking and timer
interrupts are generated internally in the 80186.

Memory
The one megabyte address space of the 80186 is
divided into four quadrants (see Figure 2). The first
(0-256K Byte) and the last (768-1000K Byte) quadrants are reserved for local memory. The second
quadrant (256-512K Byte) is used for memory
mapped I/O. The iSBC 552 board is totally memory
mapped. The third quadrant (512-768K Byte) maps
into a 256K Byte MULTIBUS window. This window
allows the iSBC 552 board to access a total of 16M
Byte of MULTIBUS memory in 256K Byte segments.
The iSBC 552 board does not contain any memory
which is accessible from MULTIBUS.

ARCHITECTURE DESCRIPTION

The 256K Byte MULTIBUS window starts on 64K
Byte boundaries anywhere in the 16M byte MULTIBUS memory. The starting location of this window is
determined by a memory mapped I/O latch described in "iSBC 552 User Interface" section.
231356-1

Figure 1.
The iSBC and iSXM 552 boards consist of the
following major architectural blocks (see Figure 1): an
80186 processor running at 6 MHz, the Ethernet 110
channel based on the 82586 LAN coprocessor and the
82501 Ethernet serial interface, the on-board memory
consisting of ROM and iRAM, and the MULTIBUS
interface.

Local memory on the iSBC 552 board (quadrants
one and four) is made up of twelve 28-pin memory
sockets. Either EPROM (2764, 27128), Intel iRAM
(2186) or equivalent static RAM memory can occupy
these sockets. The only limitations are that the lowest pair of sockets corresponding to the bottom
memory location must be RAM and the highest pair
of sockets corresponding to the top memory location must be EPROM or ROM. The intermediate
pairs of sockets can be jumper-configured to be either RAM Dr EPROM.

Processor
The iSBC 552 board contains an 80186 processor
operating in the maximum mode at 6 MHz. It is responsible for implementing the intelligent interface
between the iSBC 552 board and a host processor.
The 80186 processor runs the iNA 961 (iSXM 552)
and iNA 960 (iSBC 552) transport software and delivers data between user buffers in MULTIBUS mem-

11-11

Memory mapped I/O locations are selected by the
PCS and the MCS control lines of the 80186 processor. Functions controlled by memory mapped I/O
are discussed in "iSBC 552 User Interface" section.

Ethernet Interface
The Ethernet Interface on the iSBC 552 is implemented by the 82586 LAN Coprocessor and the 82501
Ethernet Serial Interface. Data is transferred be-

inter

ISBC 552 IISXM 552

MULTIBUS®
SYSTEM BUS
rrrrrr(H)

100000(H)
rrrrr(H)

_.

80186
ADDRESS SPACE
EPROM-MEMORY
SPACE

EBOOO(H)
NO
MEMORY
D7FFF(H)
COOOO(H)

256K

EPROM-MEMORY
SPACE

256K BYTE
MULTIBUS®
WINDOW

+-- ANY 256K BLOCK

80000(H)

ON-BOARD
MEMORY
MAPPED 1.0.
16M BYTE
SPACE
40000(H)
3FFFF(H)
IRAM-MEMORY
ADDRESS SPACE
28000(H)
NO
MEMORY
17rrr(H)
IRAM-MEMORY
ADDRESS SPACE
00000 (H)

OOOOOO(H)

Figure 2. ISBC 552 Memory Configuration

11-12

231356-2

intJ

iSBC 552 liSXM 552.

tween the on-board memory of the iSBC 552 board
and the 82586 controller by 82586 initiated DMA.
The 82586 initiates the DMA cycles by activating the
HOLD signal to the 80186 processor. The DMA cycle begins when the 80186 processor activates the
HOLD ACKNOWLEDGE signal.
The 82501 performs Manchester encoding and decoding of the transmit and receive frames. It also
provides the electrical interface to the Ethernet
transceiver cable.
Each iSBC 552 board is manufactured with a unique
default 48-bit Ethernet network address stored in an
address PROM. This address PROM is protected by
checksum and can be read by utilizing the on board
memory mapped lID. The 82586 can be programmed to have this or any other Ethernet
address.

MULTIBUS® Interface
The iSBC 552 board can access the MULTIBUS with
an 8~ or 16-bit data path and can support up to 24address bits. An lID operation by the 80186 on the
iSBC 552 board normally accesses the 110 ports on
the 80186 that control!> the processor's interrupt
controller and timers. MULTIBUS lID is disabled in
this normal operation. iSBC 552 MULTIBUS I/O operations can be enabled or disabled by writing to
memory mapped lID control locations (Table 2).
When the MULTIBUS lID is enabled, the" iSBC 552
board can write or read the complete 64k bytes of
lID space locations.

ISBC® AND ISXM™
552
BOARDS

BASE I/O PORT.
ADDRESS +4

.

I/O WRITE

SCP2

"'""

SCPl

./
SCPO
FLAG BYTE

BASE I/O PORT
ADDRESS

Table 1.
Value written
to Flag byte port
1
2

4

Action
Resets iSBC 552 board
Interrupts 80186 on Interrupt
Levell
Clears a MULTIBUS interrupt
previously generated by the
iSBC 552 board

A host processor in a system communicates with the
iSBC 552 board via a flag byte port and three other
byte registers in the MULTIBUS interface. These
registers are called the "System Configuration Pointer" registers (SCPO-SCP2). The flag byte port and
the SCP registers are presented as 4 consecutive
MULTIBUS lID ports to the host processor. The locations of these lID ports on the MULTIBUS are
configurable on the iSBC 552 (Figure 3). To the
80186 processor on the iSBC 552 board, the three
SCP registers are memory mapped locations.
The flag byte port is used by the host processor to
reset the iSBC 552 board, to interrupt the 80186
processor and to reset a MULTIBUS interrupt generated by the iSBC 552 board (Table I). SCPO-SCP2
are general purpose registers that the host processor can lID write to and the iSBC 552 board can
read from. SCPO can also be preset by hardware
jumpers.

iSBC® 552 FUNCTIONAL
DESCRIPTION
The iSBC 552 board is a high performance general
purpose Ethernet COMMengine, designed to offload
a host processor in a system from transport layer
communication processing. The board supports user
written communications software for unique applications or it can run Intel's iNA 960 transport software
in standard applications. When running iNA 960 software, the iSBC 552 board provides the host processor with reliable process to process message delivery. User messages to be sent are copied by iNA
960 software into iSBC 552 board local memory for
transmission. Packets r.eceived from the network are
first buffered and reassembled into messages on the
iSBC 552 board. These received messages are then
delivered to the user.

231356-3
Base 1/0 port address = conligurable. II 8 bit 1/0 iii used, base
port address is configurable Irom O-OFCH. II 16 bit 1/0 is used.
base port address is conligurable Irom O-OFFFCH.
Flag byte: see Table I.
SCPO-SCP2: 1/0 written bY host processor and read by 80186
on iSBC and iSXM 552 SCPO can be jumper preset.

Figure 3. ISBC@ 552 MULTIBUS@
Communication Interface

The iSBC 552 board makes use of the functions on the
82586 and 82501 to implement a number of network
functions. These functions include reprogramming the
iSBC 552 station address, Multicast packet reception
filtering. Time Domain Reflectometer tests and Loopback
diagnostics. The 82586 also records a number of network statistics information. Information stored include the
number of CRC and alignment errors, the number of

11-13

inter

Isac 552 IISXM 552

occurrences of no receive buffer resources and the
, number of DMA overruns/underruns.
The iSBC 552 can be configured to have a range of
local memory configurations, from 16K Byte RAM
(160K Byte EPROM/ROM) to 80K Byte RAM (16K
Byte EPROM/ROM).
The iSBC 552 board and iNA 960 software combination offers a flexible 'and configurable transport
COMMengine, and allows a user to optimally config~
ure his system for highest performance. The iSXM
552 and iNA 961 combination offers a preconfigured
turn-key solution. In both cases, iNA 960 software
and the 552 significantly reduces the design cycle
involved in designing ,and implementing a transport
.
COMMengine.
.'/-.

ISBC® 552 User Interface
The iSBd:S52,board communicates with a host
processor through a handshake of interrupts. The
host processor can generate flag byte interrupts to
the 80186 .on the iSBC 552 and the iSBC 552 can
generate MULTIBUS interrupts to the host processor. The host processor and the.iSBC 552 can'also
communicate through shared MULTIBUS system
memory. None of the on-board buffer on the iSBC
552 is accessible to the host processor but the iSBC
552 can read and write all of 16M byte of MULTIBUS
~ystem memory.
The host proceSsor and the iSBC 552 board further
communicate through the SCP registers. These byte
registers can be 1/0 written by the host and can be
read through memory mapped 1/0 by the iSBC 552
processor.
:The 80186 processor controls the iSBC 552 through
memory mapped 1/0. Functions that are controlled
are listed in Table 2.

OPERATING ENVIRONMENTS
The iSBC 552 is designed to function in any
MULTIBUl? systems as a communications processor. It can function as both a MULTIBUS bus master
or a slave. As a MULTIBUS master, it can access up
to 16M byte of host memory and 64K byte of 1/0
address. As a MULTIBUS slave,it occupies four
consecutive 1/0 locations on the MULTIBUS. These
locations are reserved for the flag byte and the three
SCP registers.

iSXMTM 552 FUNCTIONAL
DESCRIPTION
The iSXM 552 board is a preconfigured iSBC 552
with 16K Bytes of boot firmware and 80K Bytes of
iRAM. The iSXM 552 board is offered with iNA 961
preconfigured ISO 8073. transport software. The
iSXM 552 firmware provides the capabilities to load
iNA 961 onto the 552 from either a buffer in the local
host or remotely from another Ethernet station. It
also performs a variety of Ethernet and on-board diagnostics (see sections on iNA 961 User Interfaces and Operating Systems Environment).
iNA 961 software and the iSXM 552 board together
provide the functionality ofa preconfigured operating system independent transport engine. In addition
to transport services, iNA 961 software also includes
extensive Data Link and Network Management Facility services. Figure 4 shows the configuration of
iNA 961. Table 3 shows some examples of functions
provided by.iNA 961. iNA 961 is a preconfigured version of iNA 960. Refer to the iNA 960 data sheet for
'
more iNA 961 information.
User programs that use iNA 960 and the iSBC
186/51 board'can be run ona host processor with
iNA 961 and iSXM 552 as a transport engine. The
user programs will. require minimal changes.in most
cases.

Table 2. ISBC'" 552 Memory Mapped Functions
80186 Chip
Select Lines

ReadlWrlte
by 80186

MCS

R

MULTIBUS'" Interface registers
(System Configuration Pointer registers,
see "MULTIBUS'" Interface")

PCS

W

Channel Attention to 82586
Reading iSBC'" 552 Ethernet Address PROMS
Controlling loopback of 82501
Disabling and Enabling MULTIBUS'" 1/0
Generating and Clearing iSBC'" 552
interrupts to the MULTIBUS'" System Bus
Controlling the on-boarCi LED
Latches the MULTIBUS'" window segment
(8 most significant bits of 24 bit address)

R

W
W
W
W
W

Functions

11-14

,

Isec@ 552/ISXMTM 552

"OPEN
ISO

SYSTE~S"
~ODEL

HOST PROCESSOR

iNA 961 /ISXN TW 552
SYSTENS

231356-4

Figure 4. iNA 961 CONFIGURATION ON iSXM

552 Board

Table 3. iNA 961 Services
Transport

Virtual circuit
open: establish a virtual circuit database
send connect: actively try to establish a virtual connection
await connect: passively awaits the arrival of a connection request
send: send a message
receive: post a buffer to receive a message
close: close a virtual circuit
Datagram
send: send a datagram message
receive: post a buffer to receive a datagram message

Data Link

Transmit: transmit a data link packet
Receive: post a buffer to receive a data I;nk packet
Connect: make a datil link logical connection (link
service access point, IEEE802.3/802.2)
Disconnect: disconnect a data link logical. connection
Change Ethernet address: change the Ethernet address
Add multicast address: add a multicast address
Delete multicast address: remove a multicast address
Configure 82586: configure the 82586 controller

Network
Management

Read/Clear/Set network objects (local/remote):
read/clear/set local or remote iNA 960 network parameters
Read/Set network memory (local/remote):
read/set memory of the local or a remote station.
Useful in network debug process.
Boot consumer: requests a network boot server to
load a boot file into this station
Echo: Echo a packet between this station and
another remote station on the network

11-15

intJ

iSBC 552 /iSXM 552

iSXMTM Boot Firmware User Interface

iNA 961 User Interfaces

The iSXM 552 boot firmware is used to load iNA 961
or other software onto the 552 from either local
MULTIBUS m~mory or a remote network station.
The firmware performs a number of local and network diagnostics. Table 4 describes the functions of
the boot firmware.

User programs give iNA 960 commands to the iNA
961 software on the iSXM 552 board via the MULTIBUS Interface Protocol (MIP). MIP is an Intel reliable
process to process message delivery protocol between MULTIBUS processors. Figure 5 illustrates
how this message delivery functions. Commands are
passed between the iSXM 552 and the host processor in the form of request blocks. A request block is
a buffer that contains a command specification and
the command parameters. Each request block (or
equivalently, each command) is reliably delivered
from the host processor to'iNA 961 via the MIP facility. iNA 961 will extract the command information
and carry out the command. After a command is
done, iNA 961 will use the MIP facility to return the
command result to the user program.

The iSXM 552 boot firmware interfaces with the host
processor through a configurable command buffer
location in MULTIBUS memory. This location can be
either jumper or program configured. The host processor updates the command byte in the command
buffer and expects the firmware to update the response byte when the command is done. The host
processor signals to the firmware to examine this
command buffer by writing a 2 to the flag byte port.
The firmware will update the response byte when
the command is completed.
The iSXM 552 boot firmware commands fully support
the initialization of the MIP Interface. The MIP interface is used by the host processor to communicate
with the iNA 961 once it is loaded and started. (See
section "iNA 961 User Interfaces" for details.)

iNA 961 request blocks are in the same formats as
iNA 960 commands. Refer to the iNA 960 data sheet
and reference manuals for more details on iNA 961
software.

Table 4. ISXMTM 552 Boot Firmware Commands
Function

Command
Presence

This command will indicate that the boot firmware is functional by returning the
version number of the firmware, the power on diagnostic result, and the default
Ethernet address of the iSXM 552.

Load

Load a program from MULTIBUS memory into a designated location in the
iSBC 552 memory.

- Start
-

a

Load program from .MULTlBUS bus memory into a designated location in
the iSXM 552 memory. Proceed to start this program once it is loaded. This
command also initializes the MIP interfaCe on the iSXM 552 board.

Echo

Echo a packet between this iSXM 552 board and another station on the
network.

Remote Boot

This command requests a remote boot server station to download software
onto the iSXM 552.

and start
MIP initialize

Used after a remote boot. This command initializes the MIP interface on the
iSXM552 and then start the software loaded by the remote boot command.

11-16

inter

ISBC 552 llSXM 552

Operating Systems Environment
The iSXM 552 board and iNA 961 software can function in any MULTIBUS environment. The communication between the iSXM 552 and the host processor is entirely independent of any host operating
systems. iNA 961 uses the MIP protocol to interface
with the host processor. The MIP is a reliable, host
operating system independent, process to process
communication scheme between any processors on
the MULTIBUS System Bus. iNA 961 can service
multiple processes utilizing its services at the same
time.
A host processor passes iNA 961 commands and
buffers in the MULTIBUS system memory to the iNA

USER
PROGRAM

+---1

961 software. iNA 961 is responsible for updating
the response fields of these commands. It is responsible for copying the user send buffer in MULTIBUS
system memory into its on board buffers for transmission and for copying received messages to user
buffers in MULTIBUS system memory.

Diagnostics
The iSXM 552 board offers a range of power up diagnostics designed to ensure that the 80186 processor, the memory (EPROM and iRAM), and the
Ethernet serial interface are functioning properly.
Table 5 describes these diagnostics.

USER
MIP
DRIVER

INA
961 MIP
DRIVER

1

INA 961
SOFTWARE

TRANSFER OF
REQUEST BLOCKS
(COMMANDS)

S
Y

S
T
E
M
B
U

HOST PROCESSOR

™

iSXM
552/iNA 961
BOARD SOFTWARE

S

231356-5

Figure 5. INA 961 MIP Interface

11-17

inter

Isec 552 llSXM 552

Table 5. Functions Checked by
ISXMTM 552 Diagnostics

ORDERING INFORMATION

.1. Insufficient RAM
2. Ram match pattern test
3. Ram ripple data test
4. Boot firmware PROM checksum
5. Address PROM checksum
6. 80186 interrupt controller

82586
82586
82586
82586

CRC check.
broadcast packet recognition
external loopback
individual address recognition

13. 82586 multicast address recognition

Description

SXM 552
SBC552

Ethernet Transport Engine
Ethernet COMMengine

. SPECIFICATIONS
MULTIBUS Interface
The iSBC 552 and iSXM 552 boards conform to all
AC and DC requirements outlined in the Intel
MULTIBUS Specification, Order Number 142686-002
with the following exceptions:
Signal
Specification
DATO-DAT?: IIH=180pA,IIH=125pA

7.80186 timer controller
8. 82586 initialization
9.
10.
11.
12.

Part Number

Transceiver Interface
IEEE 802.3 compatible

DC Power Requirements

14. 82586 reset
15. 82586 diagnose check

All voltages supplied by the MULTIBUS Interface
+ 5.0V ± 5%, 5.9A maximum
+ 12.0±5%, 0.5A maximum

Environmental

DEVELOPMENT ENVIRONMENT
The iSXM 552 board is a turn-key product that allows a user to emphasize the development of high
level software. such as a network file server. The
iSXM 552 board and iNA 961 software together form
a transport COMMengine that integrates into any
MULTIBUS system. iNA 961 is supplied in a boot
loadable file format. This file can be loaded into the
iSXM 552 by a host processor or through a remote
boot server. The boot firmware on the iSXM 552
supports both functions.
The iSBC 552 allows a user to fine tune iNA 960 and
put the software on the board. Both iNA 960 and the
iSBC 552 can be flexibly configured to best meet the
users' requirements. An Intel development system,
together with an Intel 121CE or equivalent product is
usually needed if the user desires to do extensive
development work on the iSBC 552. Intel also supplies a wide range of host processor boards and systems (such as the iSBC 286/10 and system 310)
that will function well both with the iSBC 552 or the
iSXM 552.
iNA 960 can be put into PROMs and run on the iSBC
552.
.

11-18

Temperature

O°C to 55°C Operating
- 40°C to 65°C Non-Operating

Humidity

5% to 90% Operating
5% to 95% Non-Operating

inter
iSBC® 186/51
COMMUNICATING COMPUTER
MEMBER OF THE OpenNETTM PRODUCT FAMILY

• 6 MHz iAPX 186 Microprocessor
• 128K Bytes of dual·ported RAM
expandable on·board to 256K Bytes
• 82586 Local Area Network Coprocessor
for CSMA/CD applications and 82501
Ethernet serial interface for
Ethernet/IEEE 802.3 specifications
• Two serial interfaces, RS·232C and
RS·422A1RS·449 compatible
• Sockets for up to 192K Bytes of JEDEC
28 pin standard memory devices

• Supports transport layer software
(iNA 960) and higher layer communications
software (such as RMX·NET)
• Two iSBXTM bus connectors
• 16M Bytes address range of MULTIBUS®
• MULTIBUS® interface for multimaster
configurations and system expansion
• Supported by a complete family of
single board computers, peripheral
controllers, digital & analog 110,
memory, packaging and software

The iSBC@ 186/51 COMMUNICATING COMPUTER, THE COMMputer™, is a member of Intel's OpenNET
family of products, and supports Intel's network software. The COMMputer utilizes Intel's VLSI technology to
provide an economical self·contained computer for applications in processing and local area network control.
The combination of the iAPX 186 Central Processing Unit and the 82586 Local Area Network Coprocessor/82501
Ethernet Serial Interface makes it ideal for applications which require both communication and processing
capabilities such as networked workstations, factory automation, office automation, communications servers,
and many others. The CPU, Ethernet interface, serial communications interface, 128K Bytes of RAM, up to 192K
Bytes of ROM, 1/0 ports and drivers and the MULTIBUS interface all reside on a single 6.75"x12.00" printed
circuit board.

Intel Corporation Assumes No Responsibility for the Use of Any Circuitry Other Than Circuitry Embodied in an Intei Product. No Other Circuit
Patent Licenses are Implied. Information Contained Herein Supercedes Previousiy Published Specifications On These Devices From intei.

© INTEL CORPORATION 1985

11-19

ISBC
231372-7

Figure 6. Distributed Name Server Scheme

11-37

XENIX* NETWORKING SOFTWARE
MEMBER OF THE OpenNET PRODUCT FAMILY
•

Transparent Network File Access
Allows Existing Applications to be
Distributed without Change

•

Interoperation between iRMXTM, XENIX
'and MS/DOS' Based Systems over a
Local Area Network (LAN).
-Interoperation between XENIX and
DOS by Rei 1.0
-Interoperation between XENIX and
iRMX by Rei 1.1

•

Runs under XENIX 3.0 on 286/310 and
286/380 Systems

•

Supports OpenNETTM Hardware and
Software
- iSXMTM 552 Ethernet COMMengine
- iNA 961 Transport Software

•

Supports File Server Applications

XENIX Networking software is a part of. Intel's OpenNET Product Family which provides transparent file access between iRMX, XENIX and MS/DOS systems across a LAN, Users can use local file systems commands to read, write,
open, close, etc. files residing at remote iRMX, MSIDOS and XENIX systems, The XENIX Networking Software implements the \Jpper layer protocols used by Microsoft Networks, Interoperation among these systems is supported
by Intel's OpenNET LAN product line including the iSXM 552 Transport Engine, iNA 961 (a preconfigured version of
iNA 960 transport software), the iSBC® 186/51 COMMputer ™ and the iNA 960 Transport software, Networked
XENIX systems serve in a wide range of applications, such as distributed data processing, development, scientific
and engineering applications, and graphics, Below is a diagram of the OpenNET Local Area Network,

231380-1

• XENiX and MS/DOS are trademarks of Microsoft Corporation,
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on t~ese devices from InteL
February 1985
~ Intel Corporation, 1985

11-38

XENIX
in conjunction with the transport service and Ethernet hardware provides complete seven layer functionality and serves as the fundamental building
block for the development of other services such as
m~il and remote execution (see Figure 1).

XENIX-NETWORKING FUNCTIONAL
DESCRIPTION
The XENIX Networking software provides transparent remote file access capability through a file consumer and a file server module. The consumer intercepts file commands from the local user application
and transmits them across the LAN to the server at
a network system or node where the target file resides. The server receives, interprets, and executes
the command acting as a user to its local file system. The user has the option of configuring either or
both the consumer and server in his target system.

TRANSPARENT REMOTE FILE
ACCESS
XENIX Networking provides transparenl remote file
access at the application interface level. This means
that all XENIX 3.0 applications written using operating system file access commands can be used without change in a networked environment where the
referenced files may reside at other nodes of the
network.

The XENIX Networking Software also includes a
name server which allows a logical name to be used
to refer to remote nodes instead of the physical LAN
address.
The capabilities allow XENIX systems to interoperate over the LAN with RMX systems (with release
1.1) configured with RMX Networking software or
MS/OOS systems (with release 1.0) using Microsoft
Networks. This interoperation entails accessing data
and loading programs through the network. sharing
common servers, and communication between
users.

With release 1.0 of the XENIX Networking software,
the user (file consumer) can transparently access
files resident at remote systems configured with
XENIX or MS/OOS file servers. While a XENIX file
server supports remote nodes configured with both
XENIX and Microsoft Networks and file consumers.
For a table showing the combinations supported
with the initial Open NET product line, please refer to
.
Figure 2.

The XENIX Networking Software requires the sup:
port of an underlying ISO 8073 compatible transport
service provided in the iNA 960 network software
running on the iSXM 552 Transport Engine. In terms
of the ISO OSI reference model, XENIX Networking

Transparent remote file access enables the user to
manipulate and use remote files as if they were local. This capability is used for key network services,
such as r:nail, print server, and remote execution on
other XENIX nodes.

7

APPLICATION
PRESENTATION
SESSION
TRANSPORT
NETWORK
DATA LINK
PHYSICAL

1
}
}

CLJ

I

iNA961

~

I

XENIX NETWORKING
SOFTWARE

ISO TRANSPORT
SOFTWARE

iSXMTMSS2
ETHERNET COMMENGINE

T
231380-2

Figure 1. OpenNETTM Product Offerings

11-39

XENIX

Consumer

Server

Protocol
Used

Supported
In

iRMXTM
iRMXTM
XENIX
XENIX
XENIX
MS/DOS
MS/DOS
MS/DOS

iRMXTM
XENIX
iRMXTM
XENIX
MS/DOS
iRMXTM
XENIX
MS/DOS

EXT.
EXT.
EXT.
EXT.
CORE
CORE
CORE
CORE

R1.0
R1.1
RU
R1.0
R1.0
R1.0
R1.0
MICROSOFT
NETWORKS

The core and. extended protocols are in public domain and can be implemented under other operating
systems, thus enabling a host of otherwise incompatible systems to share data resources and to communicate across the network.

Figure 2. Interoperatlon

NETWORK FILE ACCESS
PROTOCOLS
File sharing, among different operating systems
acro~s the network is made possi~le through implementing a common set of file access (or file sharing)
protocols under these operating systems. Network
file sharing protocols are a set of rules governing the
interaction between a file consumer and a file server
on the same local area network. The file access protocols used by the OpenNET product line were jointly developed by Intel, Microsoft, and IBM.
Since the file systems of DOS, XENIX, and iRMX are
not identical, two protocol sets have devised to support transparency in the. various server-consumer
combinations. The core protocols support transparent file access between a MS/DOS consumer and
remote server. The "extended protocols" support
transparent file access between RMX and XENIX
nodes. The extended protocols contain the core protocols as a subset. See Figure 3 for an illustration.

Figure 3. Network File Access Protocols

NETWORK HIERARCHICAL FILE
SYSTEM
The file. sharing protocols implemeted in a network
extend the file systems of the individual nodes irrto a
hierarchical file system. Within a network any user
can access each of the "public" files through a
unique path of the network directory. For an illustration of the latter, refer to Figure 4. Within a network
hierarchical file system the same access right options are available as under XENIX 3.0, that is a remote file can be read only, written into or searched if
the requesting user has the appropriate permissions.

NETWORK

231380-4

Figure 4. Network Hierarchical File System

11-40

inter

XENIX

I'
I'..

-

.......

-

XENIX 3.0 OS

XENIX' 3.0 OS

LOCAL
FILE
SYSTEM

"'-

USER APPLICATION

USER APPLICATION

CONSUMER

~

SERVER

CONSUMER

iSXMTM552
RUNNING iNA961

~I

I

.......

~

~
LOCAL
FILE
SYSTEM

SE.RVER

iSXM™552
RUNNING iNA961

ETHERNET

r

'-~

~J
231360-5

Figure 5. XENIX Networking Consumer/Server·

IMPLEMENTATION

SYSTEM ENVIRONMENT

The XENIX Networking software implements file access across the network through enhancing the file
naming syntax. The logical name associated with a
remote system (or node) is appended by the user to
the path name of the required file. This nomenclature is distinguished from normal path names by a
double slash (1/). A similar technique is used for
MS/DOS and RMX.

The XENIX Networking software can be used on any
system running Intel's XENIX 3.0. This includes the
286/310 and 286/380 systems. Since networking
"hooks" are already included in the operating System nothing other than loading the XENIX Networking software onto the local system is necessary.
Special network utilities are'included for building and
maintaining the network configuration files so that
the network can be tailored to meet each customers
needs.

// < node name> / < path name
Hooks have been imbedded in the standard XENIX
3.0 Operating System offered by Intel which detect
remote file accesses. XENIX Networking consists of
a consumer task and server task. All local commands referencing remote files are intercepted at
the kernel level and are redirected through the consumer software to the network.

The network supports a Single community of users
which means that a user name is unique across the
network and therefore users can log-in at any system on the network.

The server software receives the command from the
network and forwards it to the local operating system acting as a user for the local file system. For an
implementation block diagram see Figure 5.
The consumer includes a name server module
which is configured to run with the iNA 961 Transport Software and is operating system independent.
The name server accesses a local file which keeps
track of valid node names and their physical LAN
address.

11-41

File security is provided by the standard XENIX 3.0
file protection of owner, group, and other access. A
loca( node can restrict local access for remote users
by allowing all, none, or a selected few remote
nodes.

USING XENIX NETWORKING
When the networking software and configuration
files are located in each node, all each node has to
do is start the consumer and/or start its server to
make its files available to other network systems to
start referencing remote files immediately. Each
node can talk to as many as 20 other nodes at

XENIX
the same time. This is dynamic and !l node can
switch to any other nodes at any time as long as it
doesn't exceed 20. This limit is only for consumer
tasks talking to server tasks and vice versa and in no
way limits the number of users at a node whiclYcan
have remote file access, i.e., all user requests from
a single node are multiplexed through a single
consumer.

ORDERING INFORMATION
XNX-NET-NSO

XNX-NET-961-NSU

The standard XENIX 3.0 mail works via XENIX Networking across the LAN as well as remote execution
pn XENIX 3.0 systems via the AT command.
XNX-NET-KIT-NRI
As a consumer to RMX servers there are a few limitations to transparency, for example, the "LOCK"
and "LINK" XENIX commands are not supported
under RMX. As a file server to a RMX consumer,
XENIX Networking does provide full transparency.
XNX-NET-RO

SPECIFICATIONS
-Code size:

....,..about 60 KB
plus 40 K for buffers

XNX-NET-RF
XNX-NET-NSR

-System requirements -XENIX 3.0

-

-iNA 961
XENIX Networking along with the iNA 961 software and the iSXM 552 have been qualified for
the 286/310-17,286/310-41, and 286/380 systems.

iNA-961~RO

iSXM 552

SYS 310-41XN

SYS.310-17XN

iMDX 457
iMDX 3015
iMDX 3016-1
iDCM 911-1

XENIX Networking Software
(both 8' and 5 v.. "double sided,
double density) plus rights for
eight copies
XENIX Networking and iNA
961 Object Software (both 8"
and 5%" double sided, double density) plus rights for 8
copies
XENIX Networking and iNA
961 Object Software (both 8"
and 5114" double sided,· double density) plus iSXM 552
Transport Engine for pass
through use
XENIX Networking and iNA
961 Object Software (both 8"
and 5%" double sided, double density) plus license rights
Software Incorporation Fee
Machine Readable source
code for the XENIX Networking Software. (both 8" and
5%" double sided, double
density)
iNA 961 Transport Software
plus license rights
Ethernet Transport Engine
plus one iNA 961 Software Incorporation Fee
XENIX System 286/310-41
with Xenix Networking Software, iNA961 Transport Software and iSXM 552 Transport
Engine
XENIX System 286/310-17
with Xenix Networking Software, iNA 961 Transport Software and iSXM 552 Transport
Engine
Ethernet Transceiver Cable
Ethernet Transceiver
Ethernet Cable
,lntellink™

Ethernet hardware and software for the IBM Personal Computer is available from Ungermann Bass, Inc.

11-42

iNA 960 TRANSPORT SOFTWARE
MEMBER OF THE OpenNET™ PRODUCT FAMILY
•

-Collection of network usage
statistics
-Setting and inspecting of transport
and data link parameters
-Fault isolation and detection
-Boot Server

ISO Transport (8073) Class 4 services
-Guaranteed message integrity
-Data rate matching (flow control)
-Multiple connection capability
- Variable length messages
-Expedited delivery
-Negotiation of virtual circuit
characteristics during opens

•

Compatible with multiple system
environments
-Runs as an iRMX '". 86 job
-Supports host operating system
independent designs based on 8086,
8088 or 80168 and 82586 components .

•

Additional functionality
-Connection less transport
(Datagram)
-External Data Link

•

IEEE 802.3 Data Link protocol
(CSMA/CD) supported

•

Runs on ISB0I>186151 COMMputer™

•

Comprehensive Network Management
services

•

Preconflgured version runs on SXM 552
Transport Engine

Board

iNA 960 is a general purpose local area network software package implementing the class 4 services of the
ISO transport specification and network management functions in system designs based on the 8086, 8088
and 80186 microprocessors and the 82586 communications co·processor. iNA 960 also supports Intel's bo!!rd
level LAN products, the iSSC'" 552, iSXMTM 552, and the iSSC"'186/51. Combined with these board products
iNA 960 provides a cost effective, high performance industry standard transport capability supporting the
OpenNET higher layer software or other user application.
iNA 960 is a ready-to-use software building block for OEM suppliers of networked systems for both technical
and commercial applications. Examples for such applications include networked design stations, manufacturing process control, communicating word processors, and financial services workstations. Using the iNA
960 software the OEM can minimize development cost and time while achieving compatibility with a growing
number of equipment suppliers adapting the IEEE and ISO standards.

ISO MODEL

TYPICAL INA 960
HARDWARE ENVIRONMENTS

END· USER APPLI·
CATION PROCESS

82586

l
APPLICATION

PRESENTATION

SESSION

TRANSPORT

DATA
LINK

LAYER

t

NETWORK

[.~~T.A_~I~~ ~~~E..R.."~::__

I

PHYSICAL OATA LINK
PHYSICAL

NETWORK

.1

MANAGEMENT

801S6

~IIIIIIIIIIIIIIII~ {ff/i{}

~

.sac

18651

COMMputer

BOARD

~;~J!~6

t'"'"

}

IMPLEMENTED
BY 8258682501
BASED HARD WARe

Figure 1.

11-43

ISBC"o,.
ISXMTM 552
ETHERNET
CONTROLLER

iNA 960

FUNCTIONAL OVERVIEW

dedicated 8086, 8088 or 80186 processor coupled
with an 82586 to provide a communications front end
processor.

The iNA 960 design is a standard implementation of
the Class 4 transport protocol defined by the ISO OSI
model. The Transport Layer provides a reliable fullduplex message delivery service on top of the "best
effort" IEEE 802.3 standard packet delivery service
implemented by the 82586 (or equivalent) physical
and data link functions.

The software also includes a Network Management
service. This facility enables the user to monitor and
adjust the network's operation in order to optimize its
performance.

Consisting of linkable modules, the software can be
configured to implement a range of capabilities and
interface protocols. In addition to reliable process-toprocess message delivery, the capabilities include a
datagram service, a boot server, a direct user access
to the Data Link Layer, and a comprehensive network
management' facility.

a

The current release of iNA 960 includes "null" Network Layer supporting the Data Link and Transport
Layers without providing internetwork routing service. This capability will be implemented in later
releases of iNA 960.
For a conceptual block diagram of iNA 960, refer to
Figure 2.

iNA 960 can be configured to run under iRMX 86
along with the user software. or to run on top of a

I

J

-.

CLIENT

l
IRMXTM 86 OR
REMOTE HOST
INTERFACE

TRANSPORT LAYER
ISO DP 8773

I

I

,

,

INTERFACE MODULE

t

DATAGRAM

1

VIRTUAL CIRCUIT

I
t .

I

>"z
o:W

-r

NETWORK
LAYER

DATA LINK
LAYER

I

NULL LAYER

Y

1

EXTERNAL
DATA
LINK

~

o:li
;:~

I

I-

>-ct
Wz
Zct
:Ii

0:

>-W

DATA LINK
INTERFACE

I

t-

o>
00:

lDW

t
DATA LINK AND
PHYSICAL LAYERS

l

I

} HARDWARE

NETWORK

Figure 2_ iNA 960 Conceptual Block Diagram

11-44

(/)

iNA 960

inter

iNA 960

TRANSPORT LAYER
The Transport Layer provides message delivery
services between client processes running on computers (network "hosts" or "nodes") anywhere in the
network.
Client processes are identified by a combination of a
network address defining the node and a transport
service access point defining the interface point
through which the client accesses the transport
services. The combined parameters. called the
transport address, are supplied by the user for both
the local and the remote client processes to be
connected.
The iNA 960 transport layer implements two kinds of
message delivery services: virtual circuit and
datagram. The virtual 'circuit provides a reliable pointto-point message delivery service ensuring maximum data integrity, and it is fully compatible with the
ISO 8073 Class 4 protocol. The datagram service
provides a best effort message delivery' between
client processes requiring less overhead and
therefore allowing higher throughput than virtual
circuits.
Both the datagram and the virtual circuit services are
optional and can be included when configuring
iNA 960.

Virtual Circuit Services
-Reliable Delivery: Data is delivered to the destination in the exact order it was sent by the source.
with no errors, duplications or losses. regardless of
the quality of service available from the underlying
network service.
-Data Rate Matching (flow control): The Transport
Layer attempts to maximize throughput while
conserving communication subsystem resources
by controlling the rate at which messages are sent.
That rate is based on the availablity of receive buffers at the destination and its own resources.

-Expedited Delivery (optional). With this service the
client can transmit up to 16 bytes of urgent data
bypassing the normal flow control. The expedited
data is guaranteed to arrive before any normal data
submitted afterward.

Connectionless Transport
(Datagram) Service
The datagram service transfers data between client
processes without establishing a virtual' circuit. The
service is a "best effort" capability anq data may be
lost or misordered. Data can be transferred at one
time to a single destination or to several destinations
(multicast).

NETWORK MANAGEMENT FACILITY (NMF)
The network management facility provides the users
of the network with planning, operation, maintenance
and initialization services described below ..
-Planning: This service captures network usage
statistics on the various layers to help plan network
expansion. Statistics are maintained by the layers
themselves and are made available to users via an
interface with the NMF.
-Operation: This service allows the. user to monitor
network functions and to inspect and adjust network parameters. The goal is to provide the tools
for performance optimization on the network.
-Maintenance: This service deals with detecting
isolating and correcting network faults. It also provides the capability to determine the presence of
hosts and the viability of their connection tei the
network.
-Initialization: NMF provides initialization and remote
loading facilities ..

-Multipie Connection Capability (Process Multiplexing): Several processes can be simultaneously
using the Transport Layer with no risk that progress or lack of progress by one process will interfere with others.

Network management provides distributed management of the network; the user can request.any of the
services to be performed on a remote as well as a
local node. The NMF interfaces to every other network layer both to utilize their services and to access
their internal data bases.

-Variable Length Messages: The client software
can submit arbitrarily short or long messages for
transmittal without regard lor the minimum or maximum .network service data unit (NSDU) lengths
supported by the underlying network services.

In support of the above services, the NMF capabilities
include layer management, echo testing, limited
debugging facilities, and the ability to down line load
and dump a remote system.

11-45

iNA 960

~ayer management deals with manipulating the in~
ternal database of a layer. The elements of these data
bases are termed objects. Some examples for objects
are the number of collisions, retransmission time-out
limit, the number of packets sent, and the list of nodes
to boot. NMF can examine and modify objects in a
layer's data base.

An echo facility is provided. Using this facility the host
can determine if a node is present on the network or
not, test the communication path to that node and
determine whether the remote node is functional.
NMF enables the user to read orwrite memory in any
host present on the network. This feature is provided as an aid to debugging.
NMF can down line load any system present on the
network. A simple Data Link protocol is used to ensure reliability. This facility can be used to load
databases, to boot systems without local mass
storage or to boot a set of nodes remotely, thus ensuring that they have the same version of software,
etc.
Dumping is an operation equivalent to memory read
from the user's standpoint; however, dumping uses
the Data Link facilities while memory read uses the
transport facilities.

EXTERNAL DATA LINK (EDL)
The External Data Link option allows the user to access the functionalities of the Data Link Layer directly
instead of having .to go through the network and
transport layers. This flexibility is useful when the
usernee.ds custom higher layer software. or does not
need the Network Layer and Transport Layer
services (e.g .. when sending "best effort" messages,
or running customer diagnostics).
Through the EDL the capabilities supporting the
lower layers in iNA 960 are made directly available to
the user. EDL enables the user to establish .and
delete data link connections, transmit packets to individual and multiple receivers, and configure the data
link' software to meet the requirements of the given
network environment:

USER ENVIRONMENT
iNA 960 is designed to run on hardware based on the
8086, 8088 or 80186 microprocessors and the 82586
LAN Coprocessor. The'software can be configured to
run under iRMX 86 or on a dedicated 8086, 8088 or
80186 processor separately from the host. The following section describes these two operating
environments ..

IRMXTM .Environment
In this configuration, both the user program and iNA
96Q are running under iRMX 86. The communications software is implemented as an iRMX 86 job
requiring. the nucleus only for most operations. The
only exception is the boot server option which also
needs the Basic I/O System. iNA 960 will run in any
iRMX environment including configurations based on
the 80130. See Figure 3 and 4 for an illustration of iNA
960 running under iRMX 86.

Operating System/Processor
Independent Implementation
In those systems where iRMX 86 is noi the primary
operating system, where off-loading the host of the
communications tasks is necessary for performance
reasons, or where an existing communications frontend processor configuration is being upgraded, the
user may wish to dedicate a processor for communications purposes. iNA 96Qcan be configured to support such implementations by providing network
services on an 8086, 8088 or 80186 processor. Fig"
ure 5 depicts the conceptual block diagram of this
configuration. The SBC & SXM 552 are
MULTIBUSI!l implementations of this architecture.

This approach provides the component and system
designer with an ISO standard communications software building block that can be adapted to his system's needs with a minimum interfacing effort. For
added flexibility, iNA 960 provides the user with the
alternative of using the included interface module or
writing hil! own module, if necessary.

11-46

iNA 960

Figure 3. As an iRMX " job, iNA 960 uses nucleus calls and, when the Boot Server is present,
BIOS calls.

11-47

inter

iNA 960

NETWORK

1S80"188151
WITH IRMl$ TM 86

AND INA 960

Figure 4. Configuration using iSBC®186151, iRMX™ 86 and iNA 960.

-'1
(

~

1-

NETWORK

_______ --*- --------.. .

MEMORY
(iNA 960 PLUS
LOCAL
RAM ROM)

82586

8086 OR
80186

SYSTEM
BUS
INTERFACE

DEDICATED
COMMUNICATIONS
PROCESSOR

')

I

I
I

I
I
I,

Figure 5. In the operating system/processor independent implementation iNA 960 is running on a
dedicated 8086, 8088 or 80186 processor.

11-48

inter

iNA 960

USER INTERFACE
iNA 960 is designed to run both under iRMX 86 and
on a dedicated communications front end processor
separately from the host. In both environments. the
interface is based on exchanging memory segments
called request blocks between iNA 960 and the
client. The format and contents of the request blocks
remain the same in both configurations; only the request block delivery mechanism changes. See Figure 6 for a simplified interface diagram.
Request blocks are memory segments containing the
data to be passed from the user to iNA 960
(commands). or from iNA 960 to the user
(responses). The iNA 960 request blocks consist of
fixed format fields identical across all user commands and argument fields unique to the individual
commands. Refer to Figure 7 for the standard request block format.

CLIENT

iNA 960

Figure 6.

Issuing an iNA 960 command consists of filling in the
request block fields and transferring the block to iNA
960 for execution. After processing the command.
iNA 960 returns the request block with one of the
pre-defined response codes placed in the response
code field of the request block. The response code
indicates whether the command was executed successfully or whether an error occurred. By examining
the response code. the user can take appropriate
action for that command.
For iRMX users. iNA 960 also provides a procedural
interface option to simplify writing the application
software interface. In this case. the allocation and
formatting of request blocks are replaced by a procedure call with parameters that specify the user's command options. The procedure execution will create a
request block and fill in the appropriate fields from the
user's parameter list.
For component users the request block delivery
mechanism is the means by which the host processor
and the communications processor running iNA 960
software exchange the request blocks. iNA 960 provides three such mechanisms: the MIP (Multibus
Inter-process Protocol). the BCB (Base Control BlOCk)
and a user-defined mechanism. The MIP interface is
included for use in systems already supporting this
protocol; the BCB is a simple interface for single host
environments. and the user-defined interface accommodates unique application requirements.

WORD/BYTE
Reserved (2)
Length
User 1.0.
Response Port
Return Mailbox Token
Segment Token
Subsystem
Opcode
Response Code

WORD
BYTE
WORD
BYTE
WORD
WORD
BYTE
BYTE
WORD

Arguments

BYTE

FIXED FORMAT
FIELDS
(same for all
commands)

ARGUMENTS
(changes by
command)

Figure 7. iNA 960 Request Block Format

11-49

iNA 960

. Transport Layer User Interface
.. The 'following table summarizes the user commands and the corresponding transport layer responses.

Function

Command
1.

OPEN

Allocates memory for the connection data base of a virtual CirCUit (or
connection) to be established The connection database contains
data concerning the connection.

2

SEND CONNECT
REQUEST

Requests connection to a fully speCified remote transport address
USing speCified ISO connectIOn negotiation options.

3.

AWAIT CONNECT
REQUEST TRAN

Indicates that the transport client.lS willing to conSider incoming connection requests based on pre-established a~ceptance critena.

4.

AWAIT CONNECT
REQUEST USER

Indicates that the transport client IS willing to conSider incoming connection requests. If the request meets the address and negotiation
option cntena, It IS passed· to the client for further consideration.

S.

ACCEPT CONNECT
REQUEST

Indicates that the connection requested by a remote transport service IS accepted by the client.

6.

SEND DATA or
SEND EOM DATA

With thiS command, the client requests the transmission of the data
In the buffers uSing the normal delivery service of the speCified
connection
The SEND EOM DATA command Signals that the end of the data
marks the end of the transport service da:a unit.

RECEIVE DATA

Posts normal receive data buffers for a specifiC connection or for a
buffer pool used by a class of connections.

8. SEND EXPEDITED

Transmits up to 16 bytes of data uSing the expedited delivery service ..
The expedited data IS guaranteed to arrive at the destlnallon before
any normal data submitted afterward.

7.

·DATA

9. RECEIVE EXPEDITED
DATA

10. CLOSE

'11. AWAIT CLOSE

Posts receive data buffers for expedited delivery for a specific connectlon or for a pool of buffers used by a class of connections.
Terminates an eXisting connection or rejects an Incoming connection
request. Any normal or expedited data queued up to be sent Will not
be sent.
Requests notification of the client of the termlnallon of a speCified
connection

12. SEND DATAGRAM

Requests transmission of the datd In the buffers uSing the transport
datagram service

13. RECEIVE DATAGRAM

Posts a receive buffer for a speCifiC receiver or a class of receivers to
receive data from a transport datagram.

11-50

inter

iNA 960

Network Management Layer User Interface
Command

Function

1.

READ OBJECT

F\eturns the value of the specified object to the client.

2.

SET OBJECT

Sets the value of an object as specified by the client.

3.

READ AND CLEAR
OBJECT

Returns the value of the specified object to the client then clears the
object.

4.

ECHO

This function is used to determine the presence of a node, to test the
communication path to the node and to ascertain the viability and
functionality of the remote host addressed.

5.

UP LINE DUMP

Requests a remote node to dump a specified memory area.

6.

READ MEMORY

Reads memory of the specified network node.

7.

SET MEMORY

Sets memory of the specified network node.

8.

FORCE LOAD

Causes a node to attempt a remote load from another node.

External Data Link Interface
Command

Function

1.

CONNECT

With this command the client establishes a data link connection.

2.

DISCONNECT

Eliminates a previously established connection.

3.

TRANSMIT

Transmits data contained in buffers specified by the cliEm!.

4.

POST RECEIVE PACKET
DESCRIPTOR

Allocates memory for maintaining records on receive data buffers.
Also may be used to allocate memory for tiuffering receive data.

5.

POST RECEIVE BUFFER

Allocates memory for buffering receive data.

6.

ADD MULTICAST
ADDRESS

Adds an address to the list of data link multicast addresses.

7.

REMOVE MULTICAST
ADDRESS

Removes an address from the list of data link multicast addresses.

8.

SET DATA LINK 1.0.

Sets up a unique data link I.D. for the station.

11-51

inter

iNA 960

CONFIGURING iNA 960
In order to adapt iNA 960 to his specific application,
the user must configure the software to define the
desired functions, to select the appropriate interface,
to set. the layer parameters ar'ld to set up for the
required hardware configuration.
There are a number of capability combinations the
user may elect to implement in his application, At the
transport layer level the options are: virtual circuit service with or without expedited delivery, or datagram
service, or both. At the data link level, the user may
include or exclude the External Data Link interface.
The Network Management Facility is also opti~mal.

HARDWARE
REQUIRED:

When it is configured in, the user may also include
the boot server module, These capabilities can be
made available simply by linking in the corresponding
software modules. The interface options are also implemented in a modular fashion: the user links in the
desired module to set up for the iRMX 86 or the
operating system independent configurations.
Layer parameters .and confiuration options are first
edited into layer configuration files, then assembled
and linked into iNA 960. Layer parameters adjust the
network's operation to match the usage pattern and
the available resources. For example, within the
Transport Layer, the· flow control parameters, the
retransmission timer parameters, the transport data
base parameters, etc. can be set via this process,

INPUTS

•
•
•
•

OPTIONAL FUNCTIONS
USER ENVIRONMENT
LAYER PARAMETERS
H W CONFIGURATION

-MDS SERIES III
OR
-86300 AND
iRMX 86
-UNIVERSAL PROM
PROGRAMMER
IF USER SYSTEM
IS IN FIRMWARE

SOFTWARE
UTILITIES
REQUIRED:
- TEXT EDITOR
-ASM 86
-LINK 86
-LOC.86

Figure 8. The Configuration Process for iNA 960

11-52

inter

INA Q60

The user also sets up for the. required hardware con·
figuration, such as port addresses and interrupt
levels, during this process. For the flow diagram of
configuring iNA 960, refer to Figure 8.

Available Literaturel
Reference Materials:
-iNA 960 Programmer's Reference Manual (11 83)
-iSBC 186151 Data Sheet (Now)
-iSBC 186151 Hardware Reference Manual (11 83)

SPECIFICATIONS
ORDERING INFORMATION
Hardwarl~

Supported:
-iSBC 186/51 Communicating Computer
-SBC 552 COMMengine
-SXM 552 Transport Engine (runs with
preconfigured transport software)
'-Custom designs based on 8086, 8088 and 80186
microprocessors and the 82586 Local Communi·
cations Controller.
Typical. Throughput at transport:
Environments:
186 51 and
iRMX 86
Dedicated 80186
82586 COMMengine

50K to 200K bytes sec

The following is a list of ordering options for the iNA 960
Transport Software. All options include a full year of update service that provides a periodic NEWSLmER,
Software Problem Report Service, and copies of
system updates that occur during this period. All of the
object code options listed are available on either ISIS or
RMX compatible double density diskettes.
As with all Intel software, purchase of any of these
options requires the execution of a standard Intel
Master Software License. The specific rights granted
to users depend on the specific option and the
License signed.

100K to 300K bytes sec

Memory Requirements: (In bytes)
Base System

Normal Virtual
Circuit Option
Expedited Delivery Option
Datagram Option
Net Management Option
External Data Link Option
Boot Server Option

12K plus con·
figurable Buffer
Memory
18K plus con·
figurable Buffer
Memory
2K
3K plus Data Base
Memory
1K t05K
5K
5K

11-53

inter

iNA 960

Order Code

Description
-

iNA 960 YRO

OEM object code license requiring the payment of incorporation
fees for each derivative work based on iNA 960; ISIS and RMX
formatted diskettes

iNA 960 YST

Object code license to use the product at a second site or
ISIS and RMX formatted diskettes

iNA 960 YBY

Object code buy-out license requiring no further payment of incorporation fees; ISIS and RMS formatted diskettes

iNA 960 YSU

Object code single use license only; ISIS and RMS formatted
diskettes

iNA 960 ESR

License for machine readable source code if iNA 960. RMX and 51V
formatted diskettes

iNA 960 L$T

Source listing of iNA 960 provided on microfiche under a special
source code license agreement

iNA 960 RF

Order code for the payment of incorporation fees

11-54

f~cility;

Communication
Controller Boards

·12

intel'
iSBc®a8145
ADVANCED DATA COMMUNICATIONS
PROCESSOR BOARD
• Three H OLC/SOLC halflfull·duplex
communication channels - optional
ASYNC/SYNC on two channels

• iAPX 88/10 (8088·2) Microprocessor
operates at 8 MHz
• iSBC@ 337 Numeric Data Processor
option supported

• Supports RS232C (including modem
support), CCITT V.24, or RS422A1449
interfaces

• 16K bytes static RAM (12K bytes
dual'ported)

• On·board OMA supports 800K baud
operation

• Four 28'pin JEOEC sites for
EPROM/RAM expansion; four additional
28'pin JEOEC sites added with iSBC@
341 board

• Self·clocking NRZI SOLC loop data
link interface
- polnt·to·point
- multidrop

• Two iSBX™ bus connectors

• Software programmable baud rate
generation

• MULTIBUS@ interface supports
Multimaster configuration

The iSBC 88/45 Advanced Data Communications Processor (AOCP) Board adds 8 MHz, iAPX 88/10 (8088·2)
8·bit microprocessor-based communications flexibility to the Intel line of OEM microcomputer systems.
The iSeC 88/45 AOCP board offers asynchronous, synchronous, SOLC, and HOLC serial interfaces for
gateway networking or general purpose solutions. The iSBC 88/45 AOCP board provides the CPU, system
clock, EPROM/RAM, serial I/O ports, priority interrupt logic, and programmable timers to facilitate higherlevel application solutions.

The IOllowlng are lrademarks 01 Inlel Corporation and may be used only 10 describe Inlel prOducts Intel. CREDIT, Indel, Ins lIe. Inlellec Library Manager MegachasslS
Mlqomap. MUL TIBUS. PROMPT. UPJ, ",Scope, Promware. MeS. ICE. IRMX. ISSC, ISex, MULTIMODUlE and les Intel Corporation assumes no responSibility lor Ihe us€' 01 any
"Clrcullry other than ClrCullry embodied In a;, Intel product No other ClfCUl1 patent licenses are Implied .

INTEL CORPORATION. 1982

12-1

OCTOBER 1984
ORDER NUMBER: 210372'()02

iSBC@ 88145

plemented by the user include SNA terminal interfaces to IBM systems.

FUNCTIONAL DESCRIPTION
Three Communication Channels

On· Board DMA

Three programmable HOLC/SOLC serial interfaces
are provided on the iSBC 88/45 AOCP board. The
SOLC interface is familiar to IBM system and terminal equipment users. The HOLC interface is
known by users of CCITT's X.25 packet switching
interface.

For high-speed communications, one MPSC channel has a OMA capacity to support an 800K baud
rate. The second channel attached to the MPSC is
capable of simultaneous 800K baud operation
when configured with OMA capability, but is connected to an RS232C interface which is defined as
20K baud maximum. Figure 2 shows an RS422A1449
multidrop application which supports high-speed
operation.

One channel utilizes an Intel 8273 controller to
manage the serial data transfers. Accepting the
8-bit data bytes from the local bus, the 8273 controller translates the data into the HOLC/SOLC format. The channel operates in half/full-duplex mode.

Interfaces Supported

In addition to the synchronous mode, the 8273
controller operates asynchronously with NRZI encoded data which is found in systems such as the
IBM 3650 Retail Store System. An SOLC loop configuration using iSBX 352 and iSBC 88/45 products
is shown in Figur.e 1.

The iSBC 88/45 AOCP board provides an excellent
foundation to support these electrical and diverse
software drivers protocol interfaces. The control
lines, serial data lines, and signal ground lines are
brought out to the three double-edge connectors.
Figure 3 shows the cable to connector construction. Two connectors are pre-configured for
RS422A/449. All three channels are configurable
for RS232C/CGITT V.24 interfaces as shown in
Table 1.

The two additional channels utilize the Intel 8274
Multi-Protocol Serial Controller (MPSC). The MPSC
provides two independent half/full-duplex serial
channels which provide asynchronous, synchronous, HOLC or SOLC protocol operations. The
sync and async protocol operations are commonly
used to communicate with inexpensive terminals
and systems.

Table 1. ISBC@ 88/45 Supported Configurations

The three serial channels of the iSBC 88/45 AOCP
board offer communications capability to manage
a gateway application. The gateway application,
as shown in Figure 1, managesdiverse protocol requirements for data movement between channels.
Typical protocol management software layers im-

It

;58X

0

352,1
~I

Asynchronous

Synchronous
Connection

Modem Direct Modem·

pOint-to,point

X' •

X

multidrop

X

X

N.A.

N.A.

loop

X
X
C
(only)

Direct
X
X
C
(only)

• Modem should not respond to break.
•• Channels A, S, and C denoted by X.

8

_______I

~I

______~

iSBC' 88/45

HOST
CPU

• 19.2K BAUD
SYNC

Figure 1. iSBC' 88/45 Gateway Processor Example
12-2

210372-002

intel

iSBCtiJ 88145

CONNECTOR

JI

MASTER

TT
SD
RT
ISBC' 88/45
BOARD

RD
TR
DM
CONNECTOR

JI

I

TR

CONNECTOR

JI
DM

SD

"

RD

RT

I

TR

DM

SD

TT

iSBC' 88/45
BOARD

iSBC' 88145

SLAVE A

SLAVE B

RD

RT

BOARD

NOTE: The last slave device in the system must contain termination resistors on all signal lines received by the slave board.
The master device contains bias resistors on all signal lines.

Figure 2. Synchronous Multidrop Network Configuration Example - RS422A

--=--0-.. _

--.-

CONNECTOR PIN 1

Figure 3. Cable Construction and Installation for RS232C and RS422A/449 Interface

12-3

210372'()02

il1tel

Isec'

88/45

illustrated in Figure 6. The microprocessor archi·
tecture is designed to effectively execute the ap·
plication and networking software written in
higher·level languages.

Self Clocking Point-To-Point Interface
The iSBC 88/45 ADCP board is used in an asyn·
chronous mode interface when configured as
shown in Figure 4. The point·to·point RS232C ex·
ample uses the self·clocking mode interface for
NRZI encoding/decoding of data. The digital
phase·lock loop allows operation of the interface
in either half/duplex or full/duplex implementation
with or without modems.

CONNECTOR
J1. J2 OR J3

hC

The stack·oriented architecture readily supports
Intel's iRMX executives and iMMX multiprocessing
software. Both software packages are deSigned
for modular application programming. Facilitating
the fast inter·module communications, the 4·byte
instruction queue supports program constructs
needed for real·time systems.

CONNECTOR
J1. J2 OR J3

rxp

R.C
R.O

RTS

RTS

iSBC' 88145 CTS

SpARD

This architectural support includes four 16·bit byte
addressable data registers. two 16·bit memory
base pointer registers and two 16·bit index regis·
ters. These registers are addressable through 24
different operand addressing modes for compre·
hensive memory addressing and for high·levellan·.
guage data structure manipulation.

CTS

.sac· 88/45

Rxe

TxC

B9ARD

R.O

hO

'OTR

OSR

OSR

OTR

Since programs are segmented between pure pro·
cedure and data, four segment registers (code,
stack,data, extra) are available for addressing 1
megabyte of memory space. These registers con·
tain the offset values used to address a 64K byte
segment. The registers are controlled explicitly
through program control or impliCitly by high·level
language functions and instructions.

Figure 4. Self-Clocking or Asynchronous Point·to·
Poi.,t Modem· Interface Configuration
Example - RS232C

Synchronous Point-To-Point Interface

The real·time system software can also utilize the
programmable timers as shown in Table 2 and var·
ious interrupt control modes available on the
ADCP board to have responsive and effective ap·
plication solutions.

Figure 5 shows a sychronous point·to·point mode
of operation for the iSBC 88/45 ADCP board. This
RS232C example uses a modem to generate the reo
ceive clock for coordination of the data transfer.
The iSBC 88/45 ADCP board generates the trans·
mit sychronizing clock for synchronous transmis·
sion.

Table 2. Programmable Timer Functions
Function

CONNECTOR
J1. J2 OR J3
RTS
CTS

isec' 88145
BOARD

T_O

Interrupt on
Terminal
Count

CONNECTOR
J1. J2 OR J3
RTS
'CTS

Rate
Generator

AxO iSBC' 88145

AxO

T.O

OTR
OSA

OSA

BOARD

OTR

Square Wave
Generator
Figure 5. Synchronous Point-to· Point Modem
Interface Configuration Example RS232C

Software
Triggered
Strobe

Operation

An interrupt is generated on
terminal count being reached.
This function is useful for gener·
ation of real·time clocks.
Divide by N counter. Based on
the input clock period, the output
pulse remains low until the count
is expired.
Output remains high for one·half
the count, goes low for the reo
mainder of the count.
Output remains high until count
expires, then goes low' for one
clock period.

Central Processing Unit
The central processor for the iSBC 88/45 Advanced
Data Communications Processor board is Intel's
8088 microprocessor operating at 8 -MHz. The
microprocessor interface to other functions is

Numeric Data Processor Extension
The 8088 instruction set includes 8·bit .and 16·bit
signed and unsigned arithmetic operators for bi·

12-4

210372.Q02

ISBC@ 88/45

Interrupt Capability

nary, BCD, and unpacked ASCII data. For enhanced numerics processing capability, the iSBC
337 MULTIMODULE Numeric Data Processor extends the BOBB architecture and data set'.

The iSBC BB/45 ADCP board provides nine vectored interrupt levels. The highest level is the NMI
(Non-Maskable Interrupt) line. The additional eight
interrupt levels are vectored via the Intel B259A
Programmable Interrupt Controller (PIC). As shown
in Table 3, four priority processing modes are
available to match interrupt servicing requirements. These modes and priority assignments are
dynamically configurable by the system software.

The extended numerics capability includes over
60 numeric instructions offering arithmetic, trigonometric, transcendental, logarithmic, and exponential instructions. Many math-oriented applications utilize the 16-, 32-, and 64-bit integer, 32- and
64-bit floating point, 1B-digit packed BCD, and
BO-bit temporary data types.
'

Table 3. Programmable Interrupt Modes

16K Bytes Static Ram

Mode

The iSBC BB/45 ADCP board contains 16K bytes of
high-speed static RAM, with 12K bytes dual-ported
which is addressable from other MULTlBUS devices. When coupled with the high-speed DMA
capability of the iSBC BB/45 ADCP board, the dualported memory provides effective data communi·
cation buffers. The dual-ported memory is useful
for interprocessor message transfers.

Operation

Nested

Interrupt request line priorities fixed;
interrupt 0 is the highest and 7 is the
lowest.
The interrupt priority rotates; once an
interrupt is serviced it becomes the
lowest priority.
System software assigns lowest level
priority. The other levels are sequenced
based on the level assigned.
System'software examines priority in·
terrupt via interrupt status register.

AutoRotating
Specific
Priority
Polled

, The iSBC 337 board requires the iSBC 88/45 ACDP board be
iumpered to provide 4 MHz operation

ADDRESS

~.u"e.

.

:'_B~

'.'_3_____yl

___

1>"---~=c:-::cc:-;:c:-::-----1'J MUl TIBUS'

'-r_.-"'Ao"'o"'.e"'ss"'R:.:::AO"'R::.A''--_--v/1 INTERFACE
RDO·RD7 DATA

1'-----1
E)(~~~~~ON

,---'--'----,

I

(lSDC' 341

BOARD,

EPROM

64K BYTES
_

8237A S

OMA

~~T~

_

I
~

STATIC

RAM

2461T
SLAVE

12K DUAL PORT

ADDRESS
. DECODE

41(.lOCAL

,, _ _-'/,

oBO·081

MULTIBUS
ADDRESS BITS

AOA14,·ADR11

CHANNel C

ICONNECTOA J1J

Figure 6. Block Diagram of the iSBC" 88/45 ADCP Board
12-5

210372-002

intel

iSBC® 88/45

puter. The iSBX connectors provide the necessary
signals to interface to the local bus.

Interrupt Request Generation
Listed in Table 4 are the devices and functions
supported by interrupts on the iSBC 88/45 ADCP
board. All interrupt signals are brought to the interrupt jumper matrix. Any pf the 23 interrupt sources
are strapped to the appropriate 8259A PIC request
level. The PIC resolves requests according to the
software selected mode and, if the interrupt is un·
masked, issues an interrupt to the CPU.

In addition to specialized or custom designed
iSBX boards, the customer has a broad range of
Intel iSBC MULTIMODULEs available, including
parallel 1/0, analog 1/0, IEEE 488 GPIB, floppy disk,
magnetic bubbles, video, and serial 1/0 boards.

EPROM/RAM Expansion
In addition to the on-board RAM, the iSBC 88/45
ADCP board provides four 28'pin JEDEC sockets
for EPROM expansion. By using 2764 EPROMs,
the board has 32K bytes of program storage. Three
of the JEDEC standard sockets also support byte·
wide static RAMs or iRAMs; using 8K x 8 static RAMs·
provides an additional24K bytes of RAM.

The serial 110 MULTIMODULE boards include the
iSBX 351 (one ASYNCISYNC serial channel) the iSBX
352 (orie HDLCISDLC serial channel) and the iSBX
354 (two SYNCIASYNC, HDLCISDLC serial channels)
boards. Adding two iSBX 3p2 MULTIMODULE boards
to the iSBC 88145 ADCP provides a total of five
HDLCISD.LC channels.
.

MUl TIBUS® Multimaster Capabilities
OVERVIEW

iSBX™ MUl TIMODUlE™ Expansion

The MULTI BUS system is Intel's Industry standard
microcomputer bus structure. Both 8· and 16-bit
single board computers are supported on the
MULTIBUS structure with 24 address and 16 data
lines. In addition to expanding functions con·
tained on a single board computer (e.g., memory
and digital 110), the MUL TIBUS structure allows
very powerful distributed processing configurations with multiple processors, intelligent slaves,
and peripheral boards.

Two 8-bit iSBX MUL TlMODULE connectors are
provided on the iSBC 88/45 microcomputer.
Through these connectors, additional iSBX functions extend the 1/0 capability of the microcom-

The iSBC 88/45 ADCP board provides full
MUL TIBUS arbitration control logic. This control

Inserting the optional iSBC 341 MUL TIMODULE
EPROM expansion board onto the iSBC 88/45
ADCP board provides four additional 28-pin JEDEC
sites. This expansion doubles the available program storage or extends the RAM capability by
32K bytes.

Multimaster Capability

Table 4. Interrupt Request Sources
Device
MULTI
BUS' Interface
,
8273 HDLe/SOLC
Controller
8274 HOLC/SOLC
SYNC/ASYNC Controller
8254·Timer
iSBX™ Connectors
Bus Fail Safe Timer
Power Line Clock
Bus Flag Interrupt
iSBC' 337 Board
8237A·5

Function
Select 1 interrupt from MULTI BUS' resident peripherals or other
CPU boards
Transmit buffer empty and receive buffer full

No. of
Interrupts
8
2

.

Software examines register for status of communication operation

1

Counter 2 of both PIT devices
Function determined by iSBX™ MULTIMOOULE™ Board (2 inter·
rupts per socket)

2

Indicates MULTI BUS' addressed device has not responded to
command within 4 msec
Source of 60 MHz signal from power supply

1

4

1

Flag interrupt in byte location 1000H signals board reset or data
handling request

2

Numeric Oata Processor generated status information
Signals end of 8237 OMA operation

1
1

12-6

210372-002

iSBC@ 88/45

logic allows up to three iSBC 88/45 ADCP boards or
other bus masters, including iSBC 286, iSSC 86 and
iSBC 86 family boards to share the system bus using
a serial (daisy chain) priority scheme. By using an external parallel priority decoder, the MULTIBUS system
bus could be shared among sixteen masters.

The ICE·88 In·Circuit Emulator provides a link be·
tween the Intellec system and the target iSSC
88/45·based system for code loading and execu·
tion. The ICE·88 package assists the developer
with the debugging and system integrating pro·
cesses.

The Intel standard MULTIBUS Interprocessor Pro·
tocol (MIP) software, implemented as the Intel
iMMX 800 package for iRMX 86 and iRMX 88 RealTime Executives, fully supports multiple 8-and 16-bit
distributed processor functions. The software
manages the message passing protocol between
microprocessors.

Run-Time Building Blocks

System Development Capabilities
The application development cycle for an iSSC
88/45 ADCP board is reduced and simplified
through the usage of several Intel tools. The tools
include the Intellec Series Microcomputer Devel·
opment System, the ICE·88 In·Circuit Emulator,
the iSDM 86 debug monitor software, and the iRMX
86 and iRMX 88 run-time support packages.

Intel offers run·time foundation software to sup·
port applications which range from general pur·
pose to high·performance solutions. The iRMX 88
Real·time Multitasking Executive provides a multi·
tasking structure which includes task scheduling,
task management, intertask communications, and
interrupt servicing for high·performance applica·
tions. The highly configurable modules make the
system tailoring job easier whether one uses the
compact executive or the complete executive with
its variety of peripheral devices supported.

The Intellec Series Microcomputer Development
System offers a complete development environ·
ment for the iSSC 88/45 software. In addition to the
operating system, assembler, utilities and applica·
tion debugger features provided with the system,
the user optionally can utilize higher·level Ian·
guages like PUM, PASCAL, and FORTRAN.

The iRMX 86 Operating System provides a very
rich set of features and options to support sophis·
ticated applications solutions. In addition to sup·
porting real·time requirements,the iRMX 860per·
ating System has a powerful, but easy·to·use
human interface. When added to the sophisticated
1/0 system, the iRMX 86 Operating System is readi·
Iy extended to support assembler, PUM, PASCAL,
and FORTRAN software development environ·
ments. The modular building block software lends
itself well to customized application solutions.

SPECIFICATIONS

On·Board RAM" -

Word Size

K Bytes

Instruction - 8, 16, 24, or 32 bits
Data - 8 or 16 bits

Hex Address
Range

16 (total)

OOOO·3FFF

12 (dual·ported)

1000·3FFF

• Four iSBC 88145 EPROM sockets support JEDEC 2412B,pln
. standard EPROMs and RAMs (3 sockets): ISBC 34 t 14 sockets)

System Clock
BMHz- ±0.1%
NOTE: Jumper selectable for 4 MHz operation with ISBC 337
Numeric Data Prpcessor module or ICE·BB product.

Environmental Characteristics

Cycle Time

Temperature - 0·55 'C, free moving air across the
base board and MULTIMODULE board

Basic Instruction Cycle at B.OO MHz - 1.25 Jlsec,
250 nsec (assumes instruction in the queue)

Humidity - 90%, non·condensing

NOTE: BasIc instruction cycle IS defined as the fastest Instruc·
tlon time (i.e .. two clock cycles).

Physical Characteristics

Memory Cycle Time
RAM - 500 nsec (no wait states)
EPROM - jumper selectable from 500 nsec to 625
nsec.
12-7

Width

- 30.48 cm (12.00 in)

Length

-

17.15 cm (6.75 in)

Height

1.50 cm (0.59 in)

Weight

6.20 gm (22 oz)
210372·002

iSBC® 88/45

Memory· Capacity/Addressing

Electrical Characteristics
DC Power Dissipation -

Orr· Board EPROM· Total
K Bytes

Hex Address
Range.

8

FEOOO·FFFFF

2732A

16

FCOOO·FFFFF

2764

32

F8000·FFFFF

27128

64

FOOOO·FFFFF

Device
2716

With optional
ISSC'" 341 MUL TIMODULETM EPROM -

Hex Address
Range

2716

16

FCOOO·FFFFF

2732A

32

F8000·FFFFF

64

FOOOO·FFFFF

128

EOOOO·FFFFF

Device

2764
27128

DC Power Requirements Configuration

.

Total
K Bytes

without EPROM'

5.1A

with 8K EPROM
(using 2716)

+ 0.14A

-

-

with 16K EPROM
(using 2732A)

+0.20A

-

-

with 32K EPROM
(using 2764) .

+ 0.24A

-

-

with 64K EPROM
(using 27128)

+0.24A

-

-

20 rnA

20 rnA

Serial Communication Characteristics
Channel Device

Supported
Interface

Max. Baud
Rate

B.OO MHz ± 0.1 %
A

8274'

RS442A/449 800K SOLC/HOLC
RS232C
125K Synchronous
50K Asynchronous
CCITTV.24

B

8274

RS232C
CCITT V.24

C

8273 3 RS442A/449 64K SOLC/HOLC3
RS232C
9.6K SELF CLOCKING
CCITTV.24

Inte{faces
iSBXTM Bus - All signals TTL compatible
Serial RS232C Signals CTS
CLEAR TO SEND
DSR
DATA SET READY
DTE TXC TRANSMIT CLOCK
DTR
DATA TERMINAL READY
FG
FRAME GROUND
RTS
REQUEST TO SEND
RXC
RECEIVE CLOCK
RXD
RECEIVE DATA
SG
SIGNAL GROUND
TXD
TRANSMIT DATA

125K Synchronous'
50K Asynchronous

NOTES:
1. 8274 supports HOLC/SOLC/SYNC/ASYNC multlprolocol
2. Exceed RS232C/CCITT V.24 rating of 20K baud
3. 8273 supports HOLC/SOLC

BAUD RATE EXAMPLES (Hz)
8254
Timer Divide
CountN

Serial RS422A1449 Signals CS
OM
RC
RO
RS
RT
SC
SO
SG
TR
TT

Current Requirements
(all voltages:!: 5%)
-12V
+5V
+12V

NOTE 1: AS SHIPPED- no EPROMs in sockets, no iSBC 341
module. Configuration includes lerminators for two
RS422A/449 and one RS232C channels.

• Four iSSC 88/45 EPROM sockets support JEDEC 24128-pin standard
EPROMs and RAMs (static and iRAM, 3 sockets); iSSC 341 sockets
also support EPROMs and RAMs.

Timer Input Frequency -

28.3 Watts

10
26
31
52
104
125
143
167
417
833
EQUATION.

CLEAR TO SEND
DATA MODE
RECEIVE COMMON
RECEIVE DATA
REQUEST TO SEND
RECEIVE TIMING
SEND COMMON
SEND DATA
SIGNAL GROUND
TERMINAL READY
TERMINAL TIMING

12-8

Synchronous
KBaud
800
300
256
154
76.8
64
56
.48
19.2
.9.6
8,000,000
N

Asynchronous
+16 +32 +64
K.Baud
50.0
19.2
16.1
9.6
4.8
4.0
3.5
3.0

500K

25.0
9.6
8.06
4.8
2.4
2.0
1.7
1.5

12.5
4.8
4.03
2.4
1.2
1.0
.87
.75

-

250K

125K

I'J I'J

I'J

210372'()()2

ISBC@ 88/45

SERIAL INTERFACE CONNECTORS
Interface

MULTIMODULETM
Edge Connector

Mode'

Cable

Connector

RS232C

DTE

26·pin 4 , 3M·3462·0001

3M2·3349/25

25·pin6 ,3M·3482·1000

RS232C

DCE

26·pin 4 ,3M·3462·0001

3M2·3349/25

25·pin 6 ,3M·3483·1000

RS449

DTE

40·pin 5 , 3M·3464·0001

3M3·3349/37

37·pin',3M·3502·1000

RS449

DCE

40·pin5, 3M·3464·0001

3M3·3349/37

37·pin',3M·3503·1000

NOTES:
I. DTE - Dala Terminal Equipment mode (male connector); DCE - Data Circuit Equipment mode (female connector) requires line
swaps.
2. Cable is tapered at one end to fit· the 3M·3462 connector.
3. Cable is tapered to fit 3M·3464 connector.
4. Pin 26 of the edge connector is not connected to the flat cable.
5. Pins 38, 39, and 40 of the edge connector are not connected to the flat cable.
6. May be used with the cable housing 3M·348S·1000.
7. Cable housing 3M·348S·4000 may be used with' the connector.

Line Drivers (supplied)

Reference Manual

Device

Characteristic

Qty

Installed

1488

RS232C

3

1

1489

RS232C

3

1

3486

RS422A

2

2

3487

RS422A

2

2

143824 - iSBC 88/45 Advanced Data Communica·
tions Processor Board Hardware Reference Man·
ual (no~ supplied).
Reference manuals may be ordered from any Intel
sales representative, distr.ibutor office or from Intel
Literature Department, 3065 Bowers Avenue, Santa
Clara, CA 95051

ORDERING INFORMATION
Part Number

Description

SBC 88/45

8·bit 8088·based Single Board
Computer with 3 HDLC/SDLC
serial channels

12-9

210372·002

intel~
iSBC@ 188/48 ADVANCED

COMMUNICATING COMPUTER

•

iSBC@ Single Board Computer or
Intelligent Slave Communication·
board

•

MULTIBUS@ Interface for system
expansion and Multimaster
configuration

•

8 Serial Communications channels,
expandable to 1 2 channels on a
single.MULTIBUS@ board

•

2 is BX ™ connectors for low cost
I/O expansion

•
•

6 MHz 80188 Microprocessor

•

64K Bytes Dual-ported RAM
expandable to 192K Bytes with Parity
using the iSBC@ 307 RAM
MULTIMODULETM board

•

2 28-pin JEDEC PROM sites
expandable to 6 sites with the iSBC@
341 MULTIMODULETM board for a
maximum of 192K Bytes EPROM

•

Resident firmware to handle up to 1 2
RS232C Async lines

Supports RS232C interface on 6
channels, RS422A/449 or RS232C
interface configurable on 2 channels

•

Supports Async,. Bisync
HOLC/SDLC, on-chip baud rate
generation, half/full-duplex, NRZ,
NRZI or FM encoding/decoding

•

7 on-board DMA channels.for serial
I/O, 2 80188 DMA channels for
iSBX™ MULTIMODULE™ board

The iSSCI!> 188/48 Advanced Communicating Computer (COMMputer™) is an intelligent 8-channel single board
computer. This iSBC board adds 6MHz 80188 microprocessor-based communications flexibility to the Intel line
of OEM microcomputer systems. Acting as a stand-alone CPU or intelligent slave for communication expan. sion, this board provides a high performance, low-cost solution for multi-user systems. The features of the iSBC
188/48 board are uniquely suited to manage higher-layer protocol requirements needed in today's data
communications applications. This single board computer takes full advantage of Intel's VLSltechnology to
provide state-of-the-art, economic, computer-based solutions for OEM communications-oriented applications.

Intel Co~rationassumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product No other circuit patent licenses
are implied. Information contained herein supersedes previously published specifications on these devices from Intel.

© INTEL CORPORATION. 1983

12-10

SEPTEMBER, 1984
ORDER NUMBER: 230890-004

inter

ISBCI!!> 188/48

can be serviced in multi-user or cluster applications by adding two iSBX 354 MULTIMODULE
boards. The dual-port RAM provides a large onboard buffer to handle incoming and outgoing
messages at data rates up to 19.2K Baud. Two
channels are supported for continuous data
rates greater than 19.2K Baud. Each serial channel can be individually programmed for different
Baud rates to allow system configurations with
differing terminal types. The firmware supplied
on the iSBC 188/48 board supports up to 12
asynchronous RS232C serial channels, provides
modem control and performs power-up
diagnostics. The high performance of the onboard CPU provides intelligence to handle protocols and character handling typically assigned
to the system CPU. This distribution of intelligence results in optimizing system performance
by releasing the system CPU of routine tasks.

OPERATING ENVIRONMENT
The iSBC 188/48 COMMputer™ features have
been designed to meet the needs of numerous
communications applications. Typical applications Include:
1. Terminal/cluster controller
2. Front-end processor
3. Stand-alone communicating computer

Terminal/cluster controller
A terminal/cluster controller concentrates communications in a central area of a system. Efficient handling of messages coming in or gOing
out of the system requires sufficient buffer
space to store messages and high speed I/O
channels to transmit messages. More sophisticated applications, such as cluster controllers,
also require character and format conversion
capabilities to allow different types of terminals
to be attached.

Front-end Processor
A front-end processor off-loads a system's central processor of tasks such as data manipulation and text editing of characters collected from
the attached terminals. A variety of terminals require flexible terminal interfaces. Program code

The iSBC 188/48 Advanced Communicating
Computer is well suited for multi-terminal systems (See Figure 1). Up to 12 serial channels

ISBX·· 354 ISBX·· 354
BOARD
BOARD
[==:::J

c:::::::::J

ISBC·188/48
BOARD

ISBC· 88/30 BOARD

,-----,,---,
FIRMWARE

II
SYSTEM
PROCESSOR
MUL TlBUS· SYSTEM BUS

Figure 1. Terminal/Cluster Controller Application
12-11

230890-004

Isacl!> 188/48
Is often dynamically down-loaded to the frontend processor from the system CPU. Downloading code requires sufficient memory space for
protocol handling and program code. Flow control and efficient handling of interrupts require
an efficient operating system to manage the
hardware and software resources.
The iSeC 188/48 board features are designed to
provide a high performance solution .for frontend processor applications (see Figure 2). A
large amount of random access memory is
provided for dynamic storage of program code.
In addition, local memory sites are available for
storing routine programs such as X.25, SNA or
bisync protocol software. The serial channels
can be configured for links to mainframe
systems, point-to-point terminals, modems or
multi-drop configurations.
STAND·ALONE COMMputer™ APPLICATION
A stand-alone communicating computer is a
complete computer system. The CPU is capable
of managing the resources required to meet the
needs of multi-terminal, multi-protocol applications. These applications typically require

multi-terminal support, floppy disk control, local
memory allocation, and program execution and
storage.
To support stand·alone applications, the iSeC 188/48
COMMputer board uses the computational
capabilities of an on·board CPU to provide a high·
speed solution controlling 8 to 12 channels of serial
I/O (see Figure 3). The local memory available is large
enough to handle special purpose code, execution
code and routine protocol software. The MULTleUS
interface can be used to access additional system
functions. Floppy disk control and graphics capability
can be added to. the iSeC stand·alone computer
through the iSeX connectors.

ARCHITECTURE
The four major functional areas are Serial I/O, CPU,
Memory and DMA. These areas are illustrated in
Figure 4.

Serial 1/0
Eight HDLC/SDLC serial interfaces are provided
on the iSeC 188/48 board. The serial interface
can be expanded to 12 channels by a'dding 2

ISBX'· 354
BOARD

ISBX'· 354
BOARD

c:=:::J

c=:=::J

ISBC·188/48
BOARD

ISBC' 86/30 BOARD

Ffl
FIRMlr RE

SYSTEM
PROCESSOR
MUL TIBUS· SYSTEM BUS

Figure 2. Front·end Processor Application

12·12

230890-004

Isec@ 188/48
iSBX 354 MUL TIMOOULE boards. The
HOLC/SOLC interface is compatible with IBM
system and terminal equipment and with
CCITT's X.25 packet switching interface.
Four 82530 Serial Communications Controllers
(SCC) provide eight channels of halflfull duplex
serial 1/0. Six channels support RS232C
interfaces. Two channels are RS232C/422/449
configurable and can be tri-stated to allow multidrop networks. The 82530 component is designed to satisfy several serial communications
requirements: asynchronous, byte-oriented synchronous, and bit-oriented synchronous (HOLCI
SOLC) modes. The increased capability at the
serial controller point results in off-loading the
CPU of tasks formerly assigned to the CPU or its
associated hardware. Configurability of the
82530 allows the user to configure it to handle
all asynchronous data formats regardless of
data size, number of start and stop bits, or parity
requirements. An on-chip Baud rate generator
allows independent Baud rates on each channel.
The clock can be generated either internally with the
SCC chip, with an external clock or via the NRZ1 clock
encoding mechanism.

All eight channels can be configured as Data
Terminal Equipment (OTE) or Data Communication Equipment (OCE). Table 1 lists the interfaces supported.

Central CPU
The 80188 central processor component provides
high performance, flexibility and powerful processing
power. The 80188 component is a highly integrated
microprocessor with an 8-bit data bus interface and
a 16-bit internal architecture to give high performance.
The 80188 is upward compatible with 8086 and 80186
software.
The 80188/82530 combination with on-board
PROM/EPROM sites, and dual-port RAM provide the
intelligence and speed to manage multi-user, mUltiprotocol communications operations.

Memory
There are two areas of memory on-board: dualport RAM and universal site memory. The iSBC
188/48 board contains 64K bytes of dual-port

4P
~

STAND-ALONE
PROCESSOR

MUL TIBUS~ SYSTEM BUS

Figure 3. Stand-alone COMMputer™ Application

12-13

230890-004

ISBC@188/48

RAM that is addressable by the 80188 on-board. The
dual-port memory is configurable anywhere in a 16M
Byte address space on 64K Byte boundaries as addressed from the MULTIBUS port. Not all of the 64K
bytes are visible from the MUL TIBUS side. The
amount of dual-port memory visible to the MULTlBUS
side can be set (with jumpers) to none, 16K bytes, or
48K bytes. The on-board RAM is expandable to a total
of 192K bytes with parity by adding the iSBC 307
MULTIMODULE board. In a multiprocessor system
these features provide local memory for each
processor and shared system memory configurations
where the total system memory size can exceed one
megabyte without addressing conflicts.

first socket contains an EPROM for the resident firmware, the second must also contain an EPROM with the
same pinout). Up to 32K bytes can be addressed per
socket giving a maximum universal site memory
size of 64K bytes. By using the iSBC 341 MULTIMODULE board, a maximum of 192K bytes of universal site memory is available. This provides sufficient memory space for on-board network or
resource management software.

Table 1. ISBC ~ 188/48 Interface Support

Connection

Synchronous
Modem or Direct

Asynchronous
Modem or Direct

X"
Channels
Oand 1

X
Channels
Oand 1

X

N/A

Point-to-point

The second area of memory is universal site
memory providing flexible memory expansion.
Two 28-pin JEDEC sockets are provided. One of
these sockets is used for the resident firmware as
described in the FIRMWARE section on Page 7.

Multidrop
LO(jQ

.. All 8 channels are denoted by X.

The default configuration of the board supports
16K Byte EPROM devices such as the Intel 27128
component. However, these sockets can contain
ROM, EPROM, Static RAM, or EEPROM. Both sockets
must contain the same type of component (i.e. as the

On-Board DMA
Seven channels of Direct Memory Access (DMA)
are provided between serial 1/0 and on-board

MULTlBUS·
INTERFACE

MLiL TIBUS· SYSTEM BUS

Figure 4. Block Diagram of ISBC 188/48 Board
12-14

230890-004

inter

ISBC@ 188/48

dual-port RAM by two 8237-5 components. Each
of channels 0,1, 2, 3, 5, 6, and 7 is supported by
their own DMA line. Serial channels 0 and 1 are
configurable for full duplex DMA. Configuring
the full duplex DMA option for Channels 0 and 1
would require Channels 2 and 3 to be interrupt
driven or polled. Channel 4 is interrupt driven or
polled only.
Two DMA channels are integrated into the iAPX
188 processor. These additional channels can
be connected to the iSBX interfaces to provide
DMA capability to iSBX MULTIMODULE boards
such as the iSBX 218A Floppy Disk Controller
MULTIMODULE board.

OPERATING SYSTEM SUPPORT
Release 6 of the iRMX 86 Operating System provides a rich set of features and options to support sophisticated stand-alone communications
applications on the iSBC 188/48 Advanced Communicating Computer. In addition to supporting
real-time requirements, the iRMX 86 Operating
System Release 6 has a powerful, yet easy to
use human interface. Services provided by the
iRMX 86 Operating System include facilities for
executing programs concurrently, sharing
resources and information, servicing asynchronous events and interactively controlling system
resources and utilities. The iRMX 86 Operating
System is readily extended to support assem'bier, PLlM, PASCAL, and FORTRAN software development environments. The modular building
block software lends itself well to customized application solutions. If the iSBC 188/48 is acting
as an intelligent slave in a system environment,
an iRMX 86 driver resident in the host CPU can
be written by following the examples in Application Note 86, "Using the iRMX86 Operating
System".
TheiSDMTM 86 System Debug Monitor supports
target system debugging for the iSBC 188/48
Advanced Communicating COMMputer board.
The monitor contains the necessary hardware,
software and documentation required to interface the iSBC 188/48 target system to an Intel
Microcomputer Development System for debugging application software.

iSBC 188/48 board (and up to two iSBX354 Multimodule Boards) acting as an intelligent slave
for multi-user applications requiring multiple
persons running independent, terminal-oriented
jobs. Example applications include distributed
data processing, business data processing, software development and engineering or scientific
data analysis. XENIX 286 Release 2 Operating
System services include device independent
I/O, tree-structured file directory and task
hierarchies, re-entrantlshared code and system
accounting and security access protection.

FIRMWARE
The iSBC 188/48 Communicating COMMputer
board is supplied with resident firmware that
supports up to 12 RS232C asynchronous serial
channels. In addition, the firmware provides a
facility for a host CPU to download and execute
code on the iSSC 188/48 board. Simple powerup confidence tests are also included to provide
a quick diagnostic service. The firmware converts the iSSC 188/48 COMMputer to a slave
communications controller. As a slave communications controller, it requires a separate MULTISUS host CPU board and requires the use of a
MUL TISUS interrupt line to signal the host processor. Table 2 summarizes the features of the
firmware.

INTERRUPT CAPABILITY
The iSSC 188/48 board has two programmable
interrupt controllers (PICs). Onp. is integrated
into the 80188 processor and the other in the
80130 component. The two controllers are configured with the 80130 controller as the master
and the 80188 controller as the slave. Two of the
80130 interrupt inputs are connected to the
82530 serial controller components to provide
vector interrupt capablities by the serial
controllers. The iSBC 188/48 board provides 22
interrupt levels. The highest level is the NMI
(Non-Maskable Interrupt) line which is directly
tied to the 80188 CPU. This interrupt is typically
used for signaling catastrophic events (e.g.
power failure). There are 5 levels of interrupts internal to the 80188 processor. Another 8 levels

The XENIX· 286 Operating System, Release 2, is
a fully-licensed adaptation of the Bell Laboratories System III UNIX· Operating System. The
XENIX system is an interactive, protected, multiuser, multi-tasking operating system with a
powerful, flexible,human interface. Release 2 of
XENIX 286 includes a software driver for the

·UNIX is a trademark of Bell Laboratories.

12-15

230B9D-004

iSBC~

188/48

Table 2. Features of the ISBell> 188/48 Firmware
Description

Feature
Asynchronous Serial
.Channel Support

Supports the serial channels in asynchronous ASCII mode. Parameters
such as baud rate, parity generation, parity checking and character
length can be programmed independently for each channel.

Block Data Transfer
(On Output)

Relieves the host CPU of character-at-a-time interrupt processing. The
iSBC 188/48 board accepts blocks of data for transmission and
Interrupts the processor only when the entire block is transmitted.

Limited Modem Control

Provides software c.ontrol of the Data Terminal Ready (DTR) line on all
channels. Transitions on the Carrier Detect (CD) line are sensed and
reported to the host CPU.

Tandem Mode Support

Transmits an XOFF character when the number of characters in its
receive buffer exceeds a threshold value and transmits an XON
character when the buffer drains below some other threshold.

Download and
execute capability

Provides a capability for the host CPU to load code anywhere in the
address space of the iSBC 188/48 bo~rd and to start executing at any
address in its address space.

Power Up
Confidence Tests

On board reset, the firmware executes a series of simple tests to
establish that crucial components on the board are functional.

of interrupts are available from the 80130
component. Of these 8, one is tied to the programmable interrupt controller (PIC) of the
80188 CPU. An additional 8 levels of interrupts
are available at the MUL TIBUS interface. The
iSBC 188/48 board does not support bus vectored interrupts. Table 3 lists the possible interrupt sources.

SUPPORT FOR THE 80130 COMPONENT

site memory can be expanded to six sockets by
adding the iSBC 341 MUL TIMODULE board for a
maximum total of 192K bytes of universal site
memory. The 64K bytes of on-board dual-port
RAM can be expanded to a maximum total of
192K bytes b'Y adding the iSBC 307 MUL TIMODULE board. The iSBC 307 MUL TIMODULE
board also provides parity for all 192K bytes of
on-board RAM.

ISBXTM MULTIMODULETM Expansion

Intel does not support the direct processor execution
of the iRMX nucleus primitives from the 80130
component. The 80130 component provides timers
and ,interrupt controllers only.

EXPANSION
EPROM/RAM Expansion
Memory may be expanded by adding Intel compatible memory expansion boards. The universal

Two 8-bit iSBX MULTIMODULE connectors are
provided on the iSBC 188/48 board. Using iSBX
modules additional functions can be added to
extend the 1/0 capability of the board. In addition
to specialized or custom designed iSBX boards,
there is a broad range of iSBX MUL TIMODULE
boards from Intel including parallel 1/0, analog
1/0, IEEE 488 GPIB, floppy disk, magnetic
bubbles, video and serial 110 boards.
The serial I/O MULTIMODULEboards available
include the iSBX 354 Dual Channel Expansion

, 12-1 Q

230891).004

iSBC@ 188/48

MUL TIMODULE board. Each iSBX 354 MUL TIMODULE board adds two channels of serial 1/0
to the iSBC 188/48 board for a maxmimum of
twelve serial channels. The 82530 serial communications controller on the MUL TIMODULE
handles a large variety of serial communications
protocols. This is the same serial controller as is
used on the iSBC 188/48 board to offer directly
compatible expansion capability for the iSBC
188/48 COMMputer board.

MULTIBUS@INTERFACE
The iSBC 188/48 Advanced COMMputer board
can be a MUL TIBUS master or intelligent slave

in a multimaster system. The iSBC 188/48 board
incorporates a flag byte signalling mechanism
for use in multiprocessor environments where
the iSBC 188/48 board is acting as an intelligent
slave. This mechanism provides an interrupt
handshake from the MUL TIBUS System Bus to
the on-board processor and vice-versa.
The Multimaster capabilities of the iSBC 188/48
board offers easy expansion of processing
capacity and the benefits of multiprocessing.
Memory and 1/0 capacity may be expanded and
additional functions added using Intel MULTIBUS compatible expansion boards.

Table 3. Interrupt Request Sources
Device

Function

Number of
Interrupts

MULTIBUS@ Interface
INTO-INT7

Requests from MUL TIBUS resident peripherals or other
CPU boards.

82530 Serial Controllers

Transmit buffer empty, receive buffer full and
channel errors 1 and external status

Internal 80188
Timer and DMA

Timer 0,1,2 outputs and 2 DMA channel interrupts

80130 Timer Outputs

Timer 0,1',2, outputs of 80130

Interrupt from Flag
Byte Logic

Flag byte Interrupt set by MULTlBUS master
(through MULTIBUS@I/OWrite)

1

Bus Flag Interrupt

Interrupt to MULTIBUS@ (Selectable for INTO to
I NT7) generated from on-board 80188 1/0 Write

1

iSBXTM connectors

Function determined by iSBXTM MUL TIMODULETM
board
DMA interrupt from iSBXTM(TDMA)

iSBXTM DMA

8

8per 82530
Total = 32
5

·3

4 (Two per
connector)
2

Bus fail-safe timeout
Interrupt

Indicates iSBC@ 188/48 board timed out either
waiting for MUL TIBUS@ access 9r timed out from no
acknowledge while on MUL TlBUS System Bus

1

Latched Interrupt

Converts pulsed event to a level interrupt.
Example: 8237A-5 EOP

1

OR-gate Matrix

Concentrates up to 4 interrupts to 1 interrupt
(selectable by stake pins)

1

Ring Indicator
Interrupt

Latches a ring indicator event from serial
channels 4,5,6, or 7

1

NOR-Gate
Matrix

Inverts up to 2 interrupts into
1 (selectable by stake pins)

1

12-17

230890-004

ISBC tl 188/48

.1/0 Capacity

SPECIFICATIONS
Word Size

Serial - 8 programmable lines using 482530
components
.

Instruction - 8, 16, 24 or 32 bits
Data Path - 8 bits

iSBXTM MULTIMODULETM Board - 2 iSBXTM
single-wide
boards

Processor Clock 82530 Clock
4.9152 MHz
6 MHZ

DMA Clock
3 MHz

Serial Communications Characteristics
MEMORY CAPACITY1ADDRESSING

Synchronous -

Internal or external character
synchronization on one or
two synchronous characters

Dual-Port RAM
ISBC"188/48 Board - 64K bytes
As viewed from the IAPX 188 - 64K
As viewed from the MULTIBUS" System Bus Choice: 0, 16K or 48K

Asynchronous- 5-8 bits and 1, 1112 or 2 stop
bits per character; programmable clock factor; break
detection and generation;
parity, overrun, and framing
error detection

EPROM

Baud Rates
Synchronous
X1 Clock

Using:
iSBC"
188/48
Board

Size

On Board
Capacity

Address Range

2732
2764
27128
27256

4K
8K
16K
32K

8K
16K
32K
64K

FEOOO-FFFFFH
FCOOQ-FFFFF H
F800Q-FFFFF H
FOOOQ-FFFFF H

Baud Rate
64000
48000
19200
9600
4800
2400
1800
1200
300

Memory Expansion
1. Ram Memory - with iSBC 307 Board
Total Capacity - 192K

2732
2764
27128
27256

Total
Capacity

Address Range

24K
48K
96K
192K

F8000-FFFFFH
FOOOO-FFFFFH
EOOOO-FFFFFH
COOOQ-FFFFFH

36
49
126
254
510
1022
1363
2046
8190
Asynchronous
X.18 Clock

As viewed from the MULTIBUS"
System BusChoice: 0, 16K or 48K Public
16K to 192K Private
64K or 192K Total
2. EPROM with
ISBC"
board using:

82530 Count Value
(Decimal)·

12-18

Baud Rate

82530 Count Vahle
(Decimal)

19200
9600
4800
2400
1800
1200
300
.110

6
14
30
62
83
126
510
1394
230890-004

iSBC@ 188/48

INTERFACES

ENVIRONMENTAL CHARACTERISTICS

iSBXTM Bus

Temperature - 0 to 55 0 C, at 200 Linear
Feet/Min. (LFM) Air Velocity

The iSBC 188/48 board meets iSBX compliance
level 08/8 DMA

Humidity - to 90%, non-condensing (25°C to 70°C)

MULTlBUS@ System Bus
The iSBC 188/48 board meets MUL TlBUS compliance level Master/Slave 08 M24116 VO EL
Serial RS232C Signals

CD
CTS
DSR
DTETXC
DTR
RTS
RXC
RXD
SG
TXD
RI

Carrier Detect
Clear to Send
Data Set Ready
Transmit Clock
Data Terminal Ready
Request to Send
Receive Clock
Receive Data
Signal Ground
Transmit Data
Ring Indicator

RS422A/449 Signals

RC
RD
RT
SO
TT

PHYSICAL CHARACTERISTICS
Width:

30.48 cm (12.00 in)

Length:

17.15 cm (6.75 in)

Height:

1.04 cm (.41 in)

Weight:

595 gm (21 ounces)

ELECTRICAL CHARACTERISTICS
The power required per voltage for the iSBC
188/48 board is shown below. These numbers
do not include the current required by universal
memory sites or expansion modules.

Receive Common
Receive Data
Receive Timing
Send Data
Terminal Timing

Voltage
(Volts)

+

5

+12
-12

Current
(Amps) typo
4.56A
.12A
.11A

Power
(Watts) typo
22.8W
1.5W
1.3W

ORDERING INFORMATION

REFERENCE MANUAL

Part Number

Description

iSBC 188/48

8-Serial Channel
Advanced Communicating
Computer

iSBC 188/48 Advanced Communications
Computer Reference Manual
Order Number 146218-002

12-19

230890-004

inter
iSBC® 188/56 ADVANCED
COMMUNICATING COMPUTER
• iSBC® Single Board Computer or
Intelligent Slave Communication
Board

• 7 On-board DMA Channels for Serial
110, 2 80188 DMA Channels for the
iSBXTM MULTIMODULETM Board

• 8 Serial Communications Channels,
Expandable to 12 Channels on a
Single MULTIBUS® Board

• MULTIBUS® Interface for System
Expansion and Multimaster
Configuration

• 8 MHz 80188 Microprocessor

• Two iSBX Connectors for Low Cost
110 Expansion
• 256K Bytes Dual-ported RAM On-board

• Supports RS232C Interface on 6
Channels, RS422A/449 or RS232C
Interface Configurable on 2 Channels

• Two 2S-pin JEDEC PROM Sites
Expandable to 6 Sites with the iSBC
341 MULTIMODULE Board for a
Maximum of 192K Bytes EPROM

• Supports Async, Bisync
HDLC/SDLC, On-chip Baud Rate
Generation, Half/full-duplex, NRZ,
NRZI or FM Encoding/decoding

• Resident Firmware to Handle up to 12
RS232C Async Lines

The iSBC 188/56 Advanced Communicating Computer (COMMputer™) is an intelligent 8-channel single board
computer. This iSBC board adds the 8 MHz 80188 microprocessor-based communications flexibility to the Intel line of OEM microcomputer systems. Acting as a stand-alone CPU or intelligent slave for communication
expansion, this board provides a high performance, low-cost solution for multi-user systems. The features of
the iSBC 188/56 board are uniquely suited to manage higher-layer protocol requirements needed in today's
data communications applications. This single board computer takes full advantage of Intel's VLSI technology
to provide state-of-the-art, economic, computer-based solutions for OEM communications-oriented applications.

Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses
are implied. Information contained herein supersedes previously published specifications on these devices from Intel. Specifications to change without
notice.

© INTEL CORPORATION. 1985

12-20

SEPTEMBER, 1985
ORDER NUMBER: 280715-001

ISBC® 188/56

OPERATING ENVIRONMENT
The iSBC 188/56 COMMputer™ features have been
designed to meet the needs of numerous communications applications. Typical applications include:
1. Terminal/cluster controller
2. Front-end processor
3. Stand-alone communicating computer

Terminal/Cluster Controller
A terminal/cluster controller concentrates communications in a central area of a system. Efficient handling
of messages coming in or going out of the system requires sufficient buffer space to store messages and
high speed I/O channels to transmit messages. More
sophisticated applications, such as cluster controllers,
also require character and format conversion
capabilities to allow different types of terminals to be
attached.
The iSBC 188/56 Advanced Communicating Computer is well suited for multi-terminal systems (See
Figure 1). Up to 12 serial channels can be serviced in
mUlti-user or cluster applications by adding two iSBX
354 MULTIMODULE boards. The dual-port RAM provides a large on-board buffer to handle incoming and

ISBC~

outgoing messages at data rates up to 19.2K baud.
Two channels are supported for continuous data rates
greater than 19.2K baud. Each serial channel can be
individually programmed for different baud rates to
allow system configurations with differing terminal
types. The firmware supplied on the iSBC 188/56
board supports up to 12 asynchronous RS232C serial
channels, provides modem control and performs
power-up diagnostics. The high performance of the
on-board CPU provides intelligence to handle protocols and character handling typically assigned to the
system CPU. The distribution of intelligence results
in optimizing system performance by releasing the
system CPU of routine tasks.

Front-end Processor
A front-end processor off-loads a system's central processor of tasks such as data manipulation and text
editing of characters collected from the attached terminals. A variety of terminals require flexible terminal
interfaces. Program code is often dynamically downloaded to the front-end processor from the system
CPU. Downloading code requires sufficient memory
space for protocol handling and program code. Flow
control and efficient handling of interrupts require an
efficient operating system to manage the hardware
and software resources.

ISBX'" 354
BOARD

ISBX'" 354
BOARD

c::::::::::J

c::::==::J
r---"r---,

ISBC" 188156
BOARD

86130 BOARD

FIRMWARE

"

SYSTEM
PROCESSOR
MUL TIBUS·! SYSTEM IBUS

Figure 1. Terminal/Cluster Controller Application
12-21

280715·001

iSBC® 188/56

system functions. Floppy disk control and graphics
capability can be added to the iSBC stand-alone computer through the iSBX connectors.

The iSBC 188/56 board features are designed to provide a high performance solution for front-end processor applications (see Figure 2). A large amount of
random access memory is provided for dynamic
storage of program code. In addition, local memory
sites are available for storing routine programs such
as X.25, SNA or bisync protocol software. The serial
channels can be configured for links to mainframe
systems, point-to-point terminals, modems or mUltidrop configurations.

ARCHITECTURE
The four major functional areas are Serial I/O, CPU,
Memory and OMA. These areas are illustrated in
Figure 4.

Serial 1/0

Stand-Alone COMMputer™ Application

Eight HOLC/SOLC serial interfaces are provided on
the iSBC 188/56 board. The serial interface can be expanded to 12 channels by adding 2 iSBX 354
MULTIMOOULE boards. The HOLC/SOLC interface
is compatible with IBM· system and terminal equipment and with CCITT's X.25 packet switching
interface.

A stand-alone communicating computer is a complete
computer system. The CPU is capable of managing
the resources required to meet the needs of mUltiterminal, multi-protocol applications. These applications typically require multi-terminal support, floppy
disk control, local memory allocation, and program execution and storage.

Four 82530 Serial Communications Controllers (SCC)
provide eight channels of half/full duplex serial 1/0. Six
channels sUPPort RS232C interfaces. Two chal:mels
are RS232C/422/449 configurable and can be trislated to allow multidrop networks. The 82530 component is designed to satisfy several serial
communications requirements; asynchronous, byteoriented synchronous (HOLC/SOLC) modes. The
increased capability at the serial controller point
results in off-loading the CPU of tasks formerly

To support stand-alone applications, the iSBC 188/56
COMMputer board uses the computational
capabilities of an on-board CPU to provide a highspeed system solution controlling 8to 12 channels of
serial 110 (see Figure 3). The local memory available
is large enough to handle special purpose code, execution code and routine protocol software. The
MULTIBUS interface can be used to access additional
'IBM is a registered trademark of International Business Machines

•

o
o

ISBX'" 354

ISBX'" 354

BOARD

BOARD

c:=:::::J c:=:::::J
ISBC~ 188/56
r---rr----.

BOARD

FIRMWARE

II
MULTIBUS@!SYSTEMIBUS

Figure 2. Front-end Processor Application
12-22

280715-001

iSBC® 188/56

assigned to the CPU or its associated hardware. Configurability of the 82530 allows the user to configure
it to handle all asynchronous data formats regardless
of data size, number of start or stop bits, or parity
requirements. An on-chip baud rate generator allows
independent baud rates on each channel.

Central CPU
The 80188 central processor component provides
high performance, flexibility and powerful processing.
The 80188 component is a highly integrated
microprocessor with an 8-bit data bus interface and
a 16-bit internal architecture to give high performance.
The 80188 is upward compatible with 86 and 186
software.

The clock can be generated either internally with the
SCC chip, with an external clock or via the NRZ1 clock
encoding mechanism.

The 80188/82530 combination with on-board
PROM/EPROM sites, and dual-port RAM provide the
intelligence and speed to manage multi-user, multiprotocol communications operations.

All eight channels can be configured as Data Terminal
Equipment (DTE) or Data Communications Equipment (DCE). Table 1 lists the interfaces supported.
Table 1. ISBC@ 188/56 Interface Support

Connection
Point-to-polnt
Multidrop
Loop

Synchronous
Modem or Direct

Memory

Asynchronous
Modem or Direct

X"

X

Channels
Oand 1

Channels
Oand 1

X

N/A

There are two areas of memory on-board: dual-port
RAM and universal site memory. The iSBC 188/56
board contains 256K bytes of dual-port RAM that is addressable by the 80188 on-board. The dual-port
memory is configurable anywhere in a 16M byte address space on 64K byte boundaries as addressed
from the MULTIBUS port. Not all of the 256K bytes are
visible from the MULTIBUS bus side. The amount of

.. AilS channels are denoted by X.

~

~
r~/Wli

ROUTINE
PROGRAMS

80188

D

L....lL...J

EXECUTION
CODE

STAND·ALONE
PROCESSOR

MULTIBUS· SYSTEM BUS

Figure 3. Stand·alone COMMputer™ Application
12-23

280715·001

Isac@ 188/56
dual-port memory visible to the MULTIBUS side can
be set (with jumpers) to none, 16K bytes, or 48K bytes.
In a multiprocessor system these features provide
local memory for each processor and shared system
memory configurations where the total system
rriemory size can exceed one megabyte without addressing conflicts.
.
The second area of memory is universal site memory
providing flexible memory expansion. Two 28-pin
JED.EC sockets are provided. One of these sockets is
used for the· resident firmware as described in the
FIRMWARE section.
.
The default configuration of the boards supports 16K
byte EPROM devices such as the Intel 27128 component. However, these sockets can contain ROM,
EPROM, Static RAM, or EEPROM. Both sockets must
contain the same type of component (I.e. as the·first
socket contains an EPROM for the resident firmware,
the second must also contain an EPROM with the
same. pinout). Up to 32K bytes can be addressed per
socket giving a maximum universai.site memory size
of 64K bytes. By using the iSBC 341 MULTIMODULE
board, a maximum of 192K bytes of universal site
memory is available. This provides sufficient memory
space for on-board network or resource management
software.

On-Board DMA
Seven channels of Direct Memory Access (DMA) are
provided between serial 1/0 and on-board dual port
RAM by two 8237-5 components. Each of channels 0,
1, 2, 3, 5, 6, and 7 is supported by their own DMA line.
Serial channels 0 and 1 are configurable for full duplex
DMA .. Configuring the full duplex DMA option for
Channels 0 and 1 would require Channels 2 and 3 to
be interrupt driven or polled. Channel 4 is interrupt
driven or polled only.
Two DMA channels are integrated in the 80188 processor. These additional channels can be connected
to the iSBX interfaces to provide DMA capability to
iSBX MULTIMODULE boards such as the iSBX 218A
Floppy Disk Controller MULTIMODULE board.

OPERATING SYSTEM SUPPORT
Intel offers run-time foundation software to support applications that range from general purpose to highperformance solutions.
. Release 6 of the iRMX 86 Operating System provides
a rich set of features and options to support sophisticated stand-alone communications applications on
the iSBC 188/56 Advanced Communicating Computer. In addition to supporting real-time require-

SERIAL
COMMUNICATIONS
CONTROLLERS
SCC(4)

CHANNEL
1-0
RS232CI
4221449

256KRAM

MULTIBUS·
INTERFACE

MULTIBUS"SYSTEM BUS

Figure 4. Block Diagram of ISBee!> 188/56 Board
12-24

280715.001

iSBC 188/56 Firmware
Feature

Description

Asynchronous Serial
Channel Support

Supports the serial channels in asynchronous ASCII mode. Parameters
such as baud rate, parity generation, parity checking and character
length can be programmed independently for each channel.

Block Data Transfer
(On Output)

Relieves the host CPU of character-at-a-time interrupt processing. The
iSBC 188/56 board accepts blocks of data for transmission and
interrupts the processor only when the entire block is transmitted.

Limited Modem Control

Provides software control of the Data Terminal Ready (DTR) line on all
channels. Transitions on the Carrier Detect (CD) line are sensed and
reported to the host CPU.

Tandem Modem Support

Transmits an XOFF character when the number of characters in its
receive buffer exceeds·a threshold value and transmits an XON
character when the buffer drains below some other threshold.

Download and
execute capability

Provides a capability for the host CPU to load code anywhere in the
address space of the iSBC 188/56 board and to start executing at any
address in its address space.

Power Up
Confidence Tests

On board reset, the firmware executes a series of simple tests to
establish that crucial components on the board are functional.

·UNIX Is a trademark of Bell laboratories
·XENIX is a trademark of Microsoft Corporation

12-25

280715-001

ISBC@ 188/56

INTERRUPT CAPABILITY
The iSBC 188/56 board has two programmable interrupt controllers (PICs). One is integrated into the
80188 processor and the other in the 80130 component. The two controllers are configured with the
80130 controller as the master and the 80188 controller as the slave. Two of the 80130 interrupt inputs
are connected to the 82530 serial controller components to provide vector interrupt capabilities by the
serial controllers. The iSBC 188/56 board provides 22

interrupt levels. The highest level is the NMI (NonMaskable Interrupt) line which is directly tied to the
80188 CPU. This interrupt is typically used for
signaling catastrophic events (e.g. power failure).
There are 5 levels of interrupts internal to the 80188
processor. Another 8 levels of interrupts are available
from the 80130 component. Of these 8, one is tied to
the programmable interrupt controller (PIC) of the
80188 CPU. An additional 8 levels of interrupts are
available at the MULTIBUS interface. The iSBC
188/56 board does not support bus vectored interrupts. Table 3 lists the possible interrupt sources.

Table 3. Interrupt Request Sources
Function

Device

Number of
Interrupts

MULTIBUS@ Interface
INTO-INT7

Requests from MUL TIBUS resident peripherals or other
CPU boards.

82530 Serial Controllers

·Transmit buffer empty. receive buffer full and
channel errors 1 and external status

Internal 80188
Timer and DMA

Timer 0,1,2 outputs and 2 DMA channel interrupts

5

80130 Timer Outputs

Timer 0,1,2, outputs of 80130

3

Interrupt from Flag
Byte Logic

Flag byte interrupt set by MULTIBUS master
(through MULTIBUS@I/OWrite)

1

Bus Flag Interrupt

Interrupt to MULTIBUS@ (Selectable for INTO to
INT7) generated from on-board 801881/0 Write

1

iSBXTM connectors

Function determined by iSBXTM MUL TlMODULETM
board
DMA interrupt from iSBXTM(TDMA)

8

8per 82530
Total = 32

,

iSBXTM DMA

4 (Two per
connector)
2

Bus fail-safe timeout
Interrupt

Indicates iSBC@188/48board timed out either
waiting for MULTIBUS@ access or timed out from no
acknowledge while on MUL TlBUS System Bus

1

Latched Interrupt

Converts pulsed event to a level interrupt.
Example: 8237A-5 EOP

1

OR-gate Matrix

Concentrates up to 4 interrupts to 1. interrupt
(selectable by stake pins)

1

Ring Indicator
Interrupt

Latches a ring indicator event from serial
channels 4,5,6, or 7

1

NOR-Gate
Matrix

Inverts up to 2 interrupts into
1 (selectable by stake pins)

1

12-26

280715-001

ISBel!> 188/56

SUPPORT FOR THE 80130
COMPONENT
Intel does not support the direct processor execution
of the iRMX nucleus primitives from the 80130 component. The 80130 component provides timers and
interrupt controllers only.

EXPANSION
EPROM Expansion
Memory may be expanded by adding Intel compatible memory expansion boards. The universal site
memory can be expanded to six sockets by adding the
iSBC 341 MULTIMODULE board for a maximum total
of 192K bytes of universal site memory.

iSBXTM MULTIMODULETM
Expansion Module
Two 8-bit iSBX MULTIMODULE connectors are provided on the iSBC 188/56 board. Using iSBX modules
additional functions can be added to extend the 1/0
capability of the board. In addition to specialized or
custom designed iSBX boards, there is a broad range
of iSBX MULTIMODULE boards from the Intel including parallel 1/0, analog 1/0, IEEE 488 GPIB, floppy
disk, magnetic bubbles, video and serial 1/0 boards.

The serial I/O MULTIMODULE boards available include
the iSBX 354 Dual Channel Expansion MULTIMODULE
board. Each iSBX 354 MULTIMODULE board adds two
channels of serial 110 to the iSBC 188/56 board for a
maximum of twelve serial channels. The 82530 serial
communications controller on the MULTIMODULE
board handles a large variety of serial communications protocols. This is the same serial controller
as is used on the iSBC 188/56 board to offer directly
compatible expansion capability for the iSBC 188/56
COMMputer board.

MULTIBUS® INTERFACE
The iSBC 188/56 Advanced COMMputer board can
be a MULTIBUS master or intelligent slave in a
multimaster system. The iSBC 188/56 board incorporates a flag byte signalling mechanism for use in
multiprocessor environments where the iSBC 188/56
board is acting as an intelligent slave. The mechanism
provides an interrupt handshake from the MULTIBUS
System Bus to the on-board-processor and vice-versa.
The Multimaster capabilities of the iSSC 188/56 board
offers easy expansion of processing capacity and the
benefits of multiprocessing. Memory and 1/0 capacity
may be expanded and additional functions added
using Intel MULTIBUS compatible expansion boards.

Memory Expansion

SPECIFICATIONS
Word Size
Instruction-8, 16, 24 or 32 bits
Data Path-8 bits
Processor Clock
8 MHz

82530 Clock
4.9152 MHz

DMAClock
4MHz

Dual Port RAM

EPROM with
ISBC@
Board using:

Capacity

Address Range

2732
2764
27128
27256

24K bytes
48K bytes
96K bytes
192K bytes

F8000-FFFFFH
FOOOO-FFFFFH
EOOOO-FFFFFH
COOOO-FFFFFH

iSBC 188/56 Board-256 bytes

1/0 Capacity

As viewed from the 80188-64K bytes

Serial-8 programmable lines using four 82530
components

As viewed from the MULTIBUS System BusChoice: 0, 16K or 48K

iSBX MULTIMODULE-2 iSBX single-wide boards

EPROM

Serial Communications Characteristics

ISBCI!> 188/56
On Board
Board using: Size Capacity Address Range
2732
2764
27128
27256

4K 8K bytes
8K 16K bytes
16K 32K bytes
32K 64K bytes

FEOOO-FFFFFH
FCOOO-FFFFFH
F8000-FFFFFH
FOOOO-FFFFFH

Synchronous-Internal or external character
synchronization on one or two synchronous
characters.
Asynchronous-5~8

bits and 1, 1Vz, or 2 stop bits per
character; programmable .clock factor; break
detection and generation; parity, overrun, and
framing error detection.

12-27

280715-001

ISBCI!) 188/56

Baud Rates

SERIAL RS232C SIGNALS
Synchronous
X1 Clock

Baud Rate

82530 Count Value
(Decimal)
36
49
126
254
510
1022
1363
2046
8190

64000
48000
19200
9600
4800
2400
1800
1200
300
Asynchronous
X 16Clock

CD
CTS
DSR
DTE TXC
DTR
RTS
RXC
RXD
SG
TXD
RI

Carrier Detect
Clear to Send
Data Set Ready
Transmit Clock
Data Terminal Ready
Request to Send
Receive Clock
Receive Data
Signal Ground
Transmit Data
Ring Indicator

RS422A/449 SIGNALS
RC
RD
RT
SO
TT

Receive Common
Receive Data
Receive Timing
Send Data
Terminal Timing

Environmental Characteristics

Baud Rate

82530 Count Value
(Decimal)

19200
9600
4800
2400
1800
1200
300
110

6
14
30
62
83
126
510
1394

Temperature-o to 55°C at 200 Linear FeeUMin.
(LFM) Air Velocity
Humidity-to 90%, non-condensing (25°C to 70°C)

Physical Characteristics
Width-30.48 cm (12.00 in)
Length-17.15 cm (6.75 in)
Height-1.04 cm (.41 in)
Weight-595 gm (21 oz)

Electrical Characteristics
The power required per voltage for the iSBC 188/56
board is shown below. These numbers do not include
the current required by universal memory sites or
expansionmoduies.

Interfaces
iSBXTM BUS
The iSBC 188/56 board meets iSBX compliance
level 08/8 DMA

Voltage
(Volts)

MULTIBUS@ SYSTEM BUS

+5
+12
-12

The iSBC 188/56 board meets MULTIBUS compliance level MasterlSlave 08 M24116 VO EL

Current
(Amps) typo
4.56A
.12A
.11A

Power
(Watts) typo
22.8W
1.5W
1.3W

ORDERING INFORMATION

Reference Manuals

Part Number

Description

iSBC 188/56 Advanced Communications Computer
Reference Manual Order Number 148209-001

iSBC 188/56

8-Serial Channel Advanced
Communicating Computer

12-28

280715-001

iSBC@534
FOUR CHANNEL COMMUNICATION EXPANSION BOARD
• Serial 110 expansion through four pro·

• Jumper selectable interface register
addresses

grammable synchronous and asyn·
chronous communications channels

• 16·bit parallel 110 Interface compatible
with Bell 801 automatic calling unit

• Individual software programmable
baud rate generation for each serial
110 channel
• Two Independent programmable 16·bit
interval timers
• Sixteen maskable interrupt request
lines with priority encoded and pro·
grammable Interrupt algorithms

• RS232C/CCITT V.24 interfaces plus
20 mA optically isolated current loop
interfaces (sockets)
• Programmable digital loop back for
diagnostics
• Interface control for auto answer and
auto originate modems

The iSBC 534 Four Channel Communication Expansion Board is a member of Intel's complete line of memory and //0
expansion boards. The iSBC 534 Interfaces directly to any single board computer via the MULTI BUS to provide expan·
slon of system serial communications capability. Four fully programmable synchronous and asynchronous seriai channels with RS232C buffering and provision for 20 mA optically isolated current loop buffering are provided. Baud rates,
data formats, and Interrupt priorities for each channel are individually software selectable. In addition to the extensive
complement of EIA Standard RS232C Signals provided, the ISBC 534 provides 16 lines of RS232C buffered programmable parallel //0. This interface Is configured to be directly compatible with the Bell ModelBOl automatic calling unit.
These capabilities provide a flexible and easy means for interfacing IntellSBC based sys,tems to RS232C and optically
Isolated current loop compatible terminals, cassettes, asynchronous and synchronous modems, and distributed pro·
cessing networks;

12-29

AFN·OO280A

iSBC® 534

FUNCTIONAL DESCRIPJ"ION
Communications Interface
Four programmable communications interfaces using
Intel's 8251A Universal Synchronous/Asynchronous
Receiver/Transmitter (USART) are contained on the
board.' Each USART can be programmed by the system
software to individually select the desired asynchronous
or synchronous serial data transmission technique (including IBM Bisync). The mode of operation (i.e., synchronous or asynchronous), data format, control
character format, parity, and baud rate are all under program control. Each 8251A provides full duplex, double
buffered transmit and receive capability. Parity, overrun,
and framing error detection are all incorporated in each
USART. Each set of RS232C command lines, serial data
lines, and signal ground lines are brought out to 26-pin
edge connectors that mate with RS232C flat or round
cables.

16·Bit Interval Timers
The iSBC 534 provides six fully programmable and in·
dependent BCD and binary 16-bit interval timers utiliz·
ing two Intel 8253 programmable interval timers.' Four
timers are available to the systems designer to generate
baud rates for the USARTs under software control.
.Routing for the outputs from the other two counters is
jumper selectable. Each may be independently routed
to the programmable interrupt controller to provide real
Jime clocking or to the USARTs (for applications requir·
ing different transmit and receive baud rates). In utiliz·
ing the iSBC 534, the systems designer simply con·
figures, via software. each timer independently to meet
system requirements. Whenever a given baud rate or

AS2J2C
COMPATIBLE

DIEVICE

TO FAD ..

SERIAL AS n2C
BUFFERS

time delay is needed, software commands to the programmable timers select the desired function. Three
functions of these timers are supported on the iSBC
534, as shown in Table I. The contents of each counter
may be read at any time during system operation.
Table 1. Programmable Timer Functions
Function

Operation

Interrupt on ter·
minal count

When terminal count is reached
an interrupt request is generated.
This function is 'used for the generation of real-time clocks.

Rate generator

Divide by N counter. The output
will go low for one input clock cy·
cle and high for N - 1 input clock
periods.
Square wave rate Output will remain high for one·
half the count and low for the
generator
other half of the count.

Interrupt Request Lines
Two independent Intel 8259A programmable interrupt
controllers (PIC's) provide vectoring for 16 interrupt
levels.' As shown in Table 2, a selection of three priority
proceSSing algorithms is available to the system
designer. The manner in which requests are serviced
may thus be configured to match system requirements.
Priority assignments may be reconfigured dynamically
via software at any time during system operation. Any
combination of interrupt levels may be masked through
storage, via software, of a single byte to the interrupt
mask register of each PIC. Each PIC's interrupt request

CUIlRENT

CURRENT

RS2J2C

lOOP
DEVICE

DEVICE

""

COMP"T!BLE
DEVICE

.

CURIlENl
LOOP
DEVICE

AS

~l2C

COMPATIBLE
DEVICE

CUAMHT

"0'

DEVIC(

.

INTERRUPT

INTERRUPT

Ri~~::T

REOUEST

LINES

IFIIOfIIUSAATSl

Figure 1. iSBC ® 534 Four Channel Communications Expansion Board Block Diagram

12-30

AFN·00280A

iSBC® 534
Table 3. Interrupt Assignments

output line may be Jumper selected to drive any of the
nine interrupt lines on the MULTIBUS.
Table 2. Interrupt Priority Options
Algorithm
Fully
nested
Auto·
rotating
Specific
priority

Interrupt
Request
Line
0
1
2
3
4
5
6
7

Operation
Interrupt request line priorities fixed at 0
as highest, 7 as lowest.
Equal priority. Each level, after receiving
service, becomes the lowest priority level
until next interrupt occurs.
System software assigns lowest priority
level. Priority of all other levels based in
sequence numerically on this assign·
ment.

PIC 0
PORT 0 Rx
PORT 0 Tx
PORT 1 Rx
PORT 1 Tx
PORT 2 Rx
PORT 2 Tx
PORT 3 Rx
PORT 3 Tx

PIC 1
ROY
ROY
ROY
ROY
ROY
ROY
ROY
ROY

PIT 1 counter 1
PIT 2 counter 2
Ring indicator (all ports)
Present next digit
Carrier detect port 0
Carrier detect port 1
Carrier detect port 2
Carrier detect port 3

Interrupt Request Generation - As shown in Table 3, In·
terrupt requests may originate from 16 sources. Two
jumper selectable interrupt requests (8 total) can be
automatically generated by each USART when a
character is ready to be transferred to the MULTIBUS
system bus (i.e., receive buffer is full) or a character has
been transmitted (transmit buffer is empty). Jumper
selectable requests can be generated by two of the pro·
grammable timers (PITs), and six lines are routed directly
from peripherals to accept carrier detect (4 lines), ring in·
dlcator, and the Bell 801 present next digit request lines.

mabie peripheral interface (PPI) configured to operate in
mode O. * These lines are configured to be directly com·
patible with the Bell 801 automatic calling unit (ACU).
This capability allows the iSBC 534 to Interface to Bell
801 type ACUs and up to four modems or other serial
communications devices. For systems not requiring in·
terface to an ACU, the parallel 110 lines may also be used
as general purpose RS232C compatible control lines in
system Implementation.

Systems Compatibility

• Complete operational details on the Intel 825t A USART. the Intel 8253
Programmable tntervat Timer. the intel 8255A Programmable Peripheral In·
terface. and the Intel 8259A Programmable Interrupt Controller are contained
in the Intel Component DatB Catalog.

The ISBC 534 provides 16 RS232C buffered parallel 110
lines Implemented utilizing an Intel 8255A program·

SPECI FICATIONS

Interval Timer and Baud Rate Generator
Frequencies

Serial Cornmunications Characteristics
Synchronous - 5·8 bit characters; internal or external
character synchronization; automatic sync insertion.
Asynchronous - 5·8 bit characters; break character
generation; 1, 1 v., or 2 stop bits; false start bit detec·
tion.

Input Frequency (On·Board Crystal Oscillator) - 1.2288
MHz±0.1% (0.813I's period, nominal)
Single Timer

Function
Real·Time
Interrupt
Interval

Sample Baud Rates 1
Frequency2
(kHz, Software Seleclable) Synchronous

Beud Rale (Hz)

16

+

153.6
76.8
38.4
19.2
9.6
4.8
6.98

-

38400
19200
9600
4800
6980

Rate Generator
IFrequency)

Asynchronous .

9600
4800
2400
1200
600
300

-

+

DuallTlmer Counter
(Two Timers Cascaded)

Min

Max

Min

Max

1.63""

53.3ms

3.26"s

58.25
minutes

18.75 Hz

614.4 kHz

0.0029 Hz

307.2 kHz.

64

2400
1200
600
300
150
75
110

Note.:
1. Baud rates shown here are only a sample subset of possible
software·programmable rates available.Any frequency from 18.75 Hz to
614.4 kHz may be generated utilizing on·board crystal osciliator and
l6·bit programmable interval timer-fused here as frequency divider).
2. Frequency selected by I/O writes of appropriate 16·bit frequency fac·
tor to Baud Rate Register.

Interfaces - RS232C Interfaces
EIA Standard RS232C Signals provided and supported:
Carrier detect
Receive data
Ring indicator
Clear to send
Secondary receive data
Oata set ready
Secondary transmit data
Oata terminal ready
Request to send
Transmit clock
Transmit data
Receive clock
Parallel 110 - 8 input lines, 8 output lines, all signals
RS232C compatible
Bus - All signals MULTlBUS system bus compatible

12-31

AFN.(J0280A

inter

ISBC® 534

I/O Addressing

Physical Characteristics

The USART, interval timer, interrupt controller, and
parallel Interface registers' of the iSBC 534 are con·
figured as a block of 16 1/0 address locations, The loca·
tion of this block is jumper selectable. to begin at any
16·byte 1/0 address boundary (i.e., OOH, 10H, 20H, etc.).

Width - 12.00 In. (30.48 cm)
Height - 6.75 in. (17.15 cm)
Depth - 0.50 in. (1.27 cm)
Weight - 14 oz (398 gm)

Electrical Characierlstlcs

I/O Access Time
400
400
400
400

Average DC Current

nsUSART registers
ns Parallel 1/0 registers
ns Interval timer registers
ns Interrupt controller registers

Voltage

Compatible Connectors
Interface

Bus

Pins Centers
(qty.) (In.)
86

Serial and
26
parallel 110

With
Opta-Isolators'

Vce = +5V

1.9 A. max

1.9 A, max

VOD = + 12V'

275 rnA, max

420 rnA, max

VAA = -12V

250 rnA, max

400 rnA, max

Note

Mating Connectors

1. With four 4N33 and lour 4N37 apla·isalalar packages Installed in
sockets provided to implement four 20 rnA current loop interfaces.

0.156

Viking 2Klj43/9 AMK12

0.1

3M 3462-0001 or
TI H312113

Environmental Characteristics
Operating Temperature - 0 'C to + 55 'C

Compatible Opto-Isolators
Function

Without
OptOolsolators

Supplier

Reference Manual
502140-002 - iSBC 534 Hardware Reference Manual
(NOT SUPPLIED)
Reference manuals are shipped with each product only
If deSignated SUPPLIED (see above). ManualS may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051.

Part Number

Driver

Fairchild
General Electric
Monsanto

4N33

Receiver

Fairchild
General Electric
Monsanto

4N37

ORDERING INFORMATION
Part Number

Description

SBC 534

Four·Channel Communication Ex·
pansion Board

12-32

AFN·002BOA

ISBC@544
INTELLIGENT COMMUNICATIONS CONTROLLER
• iSBC®Communications Controller acting
as a single board communications
computer or an intelligent slave for
communications expansion

• Ten programmable parallel I/O lines
compatible with Bell 801 Automatic
Calling Unit

• On-board dedicated 808SA Microprocessor providing communications
control and buffer management for
four programmable synchronousl
asynchronous channels

• Twelve levels of programmable
interrupt control
• Individual software programmable baud
rate generation for each serial 1/0
channel

• Sockets for up to 8K bytes of EPROM
• 16K bytes of dual port dynamic readl
write memory with on-board refresh
• Extended MULTIBUS ®addressing
permits iSBC 544 board partitioning
into·16K-byte segments in a 1-megabyte
address space

• Three independent programmable
· interval timer/counters
• Interface control for auto answer and
auto originate modem

The iSBC 544 Intelligent Communications Controller is a member of Intel's family of single-board computers, memory,
I/O, and peripheral controller boards. The iSBC 544 board is a complete communications controller on a single
6.75 x 12.00 inch printed circuit card. The on-board 8085A CPU may perform local communications processing by
directly interfacing with on-board read/write memory, nonvolatile read only memory, four synchronous/asynchronous
serial I/O ports, RS232/RS366 compatible parallel 110, programmable timers, and programmable interrupts.

12-33

AFN·01271A

inter

ISBC® 544
to coordinate up to four serial channels. Using the iSBC
544 as an intelligent slave, multichannel serial transfers
can be managed entirely on-board, freeing the bus
master to perform other system functions.
.

FUNCTIONAL DESCRIPTION
Intelligent Communications Controller
Two Mode Operation - The ISBC 544 board Is capable
of operating in one of two modes: 1) as single board
communications computer with all computer and communications interface hardware on a single board; 2) as
an "intelligent bus slave" that can perform communications related tasks as a peripheral processor to one or
more bus masters_ The iSBC 544 may be configured to
operate as a stand-alone Single board communications
computer with ali MPU, memory and 1/0 elements on a
single board. In this mode of operation, the iSBC 544
may also interface with expansion memory and 1/0
boards (but no additional bus masters). The iSBC 544
performs as an intelligent slave to the bus master by
performing all communications related tasks. Complete
synchronous and asynchronous I/O and data
management are controlled by the on-board 8085A CPU

a

,----

Architecture - The iSBC 544 board is functionally partitioned into three major sections: 110, central computer,
and shared dual port RAM memory (Figure 1). The 1/0
hardware is centered arou"nd the four Intel 8251 A USART
devices providing fully programmable serial interfacing.
Included here as well is a 10-bit parallel interface compatible with the Bell 801 automatic calling unit, or equivalent. The 1/0 is under full control of the on-board CPU
and is protected from access by system bus masters.
The second major segment of the intelligent communications controller is a central computer, with an 8085A
CPU providing powerful processing capability. The
8085A together with on-board EPROM / ROM, static
RAM, programmable timers/coullters,' and program-

SEiiiALiiO -

-

-

- - SERiALiiO - - -:- -

PARAillLiio -

-,

I
I

I
I
INPUT

I

I
I

I
I

I
I
I

,-

PROGRAMMABLE 1/0

-r -

----

I

• INTERRUPTS:
RECEIVER READY
TRANSMlnER READY

I
I
I
I
I

• INTERRUPTS:
RING INDICATOR
CARRIER DETECT

i

-------1

I

I

18K.S

I

DYNAMIC
RAM

I
I
I

I

I

I

I
I

I
I

I

r-------J

I
I

I
I

I

LCE~R~~~U~E~

I

I __
...l.

______ _

DUAL PORT RAM
MEMORY !
________
----.....I

MULTIBUS

Figure 1. ISB.C

.R,

544 Intelligent Communications Controller Block Diagram

12-34

AFN·O'27'A

ISBC® 544
mabie interrupt control provide the intelligence to manage sophisticated communications operations on-board
the iSBC 544 board. The timer/counters and Interrupt
control are also common to the 110 area providing pro·
grammable baud rates to the USARTs and prioritizing
interrupts generated from the USARTs. The central computer functions are protected for access only by the onboard BOB5A. likewise, the on-board BOB5A may not gain
access to the system bus when being used as an intelligent slave. When the iSBC 544 is used as a bus
master, the· on-board BOB5A CPU controls complete
system operation accessing on-board functions as well
as memory and 110 expansion. The third major segment,
dual port RAM memory, is the key link between the iSBC
544 intelligent slave and bus masters managing the
system functions. The dual port concept allows a common block of dynamic memory to be accessed by the
on-board BOB5A CPU and off-board bus masters. The
system program can, therefore, utilize the shared dual
port RAM to pass command and status information
between the bus masters and on-board CPU. In addition,
the dual port concept permits blocks of data
transmitted or received to accumulate in the on·board
shared RAM, minimizing the need for a dedicated
memory board.

Central Processing Unit
Intel's powerful B-bit n·channel 8085A CPU, fabricated
on a Single LSI chip, is the central processor for the
iSBC 544. The BOB5A CPU is directly software compatible
with the Intel BOBOA CPU. The BOB5A contains six 8-blt
general purpose registers and an accumulator. The six
general purpose registers may be addressed individually
or in pairs, providing both single and double precision
operators. The minimum instruction execution time Is
1.45 microseconds. The BOB5A CPU has a 16-blt program
counter. An external stack, located within any portion of
iSBC 544 read/write memory, may be used as a last-in/
first-out storage area for the contents of the program
counter, flags, accumulator, and all of the six general
purpose registers. A 16-bit stack pointer controls the addreSSing of this external stack. This stack provides subroutine nesting bounded only by memory size.

EPROM/ROM Capacity
Sockets for up to BK bytes of nonvolatile read only memory are provided on the iSBC 544 board. Read only memory may be added in 2K-byte increments up to a maximum of 4K bytes using Intel 2716 EPROMs or masked
ROMs; or in 4K-byte increments up to BK bytes maximum
using Intel 2732 EPROMs. All on-board EPROM/ROM
operations are performed at maximum processor speed.

Serial I/O
Four programmable communications interfaces using
Intel's B251A Universal Synchronous/Asynchronous
Receiver/Transmitter (USART) are contained on the
board and controlled by the on-board CPU in combination with the on-board interval timer/counter to provide
all common communication frequencies. Each USART
can be programmed by the system software to individually select the desired asynchronous or synchronous
serial data transmission technique (including IBM
Bisync). The mode of operation (I.e., synchronous or
asynchronous), data format, control character format,
parity, and baud rate are all under program control. Each
B251A provides full duplex, double-buffered, transmit
and receive capability. Parity, overrun, and framing error
detection are all incorporated in each USART. Each
channel is fully buffered to provide a direct interface to
RS232C compatible terminals, peripherals, or synchronous/asynchronous modems. Each channel of
RS232C command lines, serial data lines, and signal
ground lines are brought out to 26-pin edge connectors
that mate with RS232C flat or round cable.

Parallel I/O Port
The iSBC 544 provides a 10-bit parallel 110 interface controlled by an Intel B155 Programmable Interface (PPI)
chip. The parallel 110 port is directly compatible with an
Automatic Calling Unit (ACU) such as the Bell Model
B01, or equivalent, and can also be used for auxiliary functions. All signals are RS232C compatible, and the interface cable signal aSSignments meet RS366 specifications. For systems not requiring an ACU interface, the
parallel 110 port can be used for any general purpose
Interface requiring RS232C compatibility.

12-35

RAM Capacity
The iSBC 544 contains 16K bytes of dynamic read/write
memory using Intel 2117 RAMs. Power for the on·board
RAM may be provided on an auxiliary power bus, and
memory protect logic is included for RAM battery backup requirements. The iSBC 544 contains a dual port controller, which provides dual port capability for the onboard RAM memory. RAM accesses may occur from
either the on-board BOB5A CPU or from another bus
master, when used as an intelligent slave. Since onboard RAM accesses do not require the MULTI BUS, the
bus is available for concurrent bus master use. Dynamic
RAM refreSh is accomplished automatically by the iSBC
544 for accesses originating from either the CPU or from
the MULTI BUS.
Addressing - On board RAM, as seen by the on-board
BOB5A CPU, resides at address 8000wBFFFH' On-board
RAM, as seen by an off-board CPU,may be placed on
any 4K-byte address boundary. The iSBC 544 provides
extended addressing jumpers to allow the on-board
RAM to reside within a one megabyte address space
when accessed via the MULTIBUS. In additon, jumper
options are provided which allow the user to protect 8Kor 12K-bytes on-board RAM for use by the on-board
8085 CPU only. This reserved RAM space is not accessible via the MULTIBUS and does not occupy any system
address space.
Slatic RAM - The iSBC 544 board also has 256 bytes of
static RAM located on the IntelB155 PPI. This memory is
only accessible to the on-board 80B5A CPU and is located
at address 7FOO H-7FFF H.
AFN·O'27'~

iSBC® 544

Programmable Timers

Table 1. Programmable Timer Functions

The iSBC 544 board provides seven fully programmable
and independent interval timer/counters utilizing two
Intel 8253 Programmable Interval Timers (PIT), and the
Intel 8155. The two.lntel8253 PITs provide six independ·
ent BCD or binary 16·bit interval timer/counters and the
8155 provides one 14·bit binary timer/counter. Four of
the PIT timers (BDGO-3) are dedicated to the USARTs
providing fully independent pro-grammable baud rates.

When terminal count
Interrupt on
Terminal Count is reached, an interrupt request is gener(Mode 0)
ated. This function is
useful for generation
of real-time clocks.
. Rate Generator Divide by N counter.
(Mode 2)
The output will go low
for one input clock
cycle and high for N-1
input clock periods.

Three General Use Timers - The fifth timer (BDG4) may
be used as an auxiliary baud rate to any of the four
USARTs or may alternatively be cascaded with timer six
to provide extended interrupt intervals. The sixth PIT
timer/counter (TlNT1) can be used to generate interrupt
intervals to the on-board 8085A. In addition to the timer/
counters on the 8253 PITs, the iSBC 544 has a 14-bit
timer available on the 8155 PPI providing a third general
use timer/counter (TINTO). This timer output is jumper
selectable to the interrupt structure of the on-board
8085A CPU to provide additional timer/counter capability.

Square-Wave
Output will remain
Rate Generator high until one-half the
(Mode 3)
TC has been completed, and go low for
the other half of the
count. ThiS is the primary operating mode
used for generati ng a
Baud rate clocked to
the USARTs.

Timer Functions - In utilizing the iSBC 544 board, the
systems designer simply configures, via software, each
timer independently to meet systems requirements.
Whenever a given baud rate or interrupt interval is
needed, software commands to the programmable
timers select the desired function. The on-board PITs
together with the 8155 provide a total of seven timer/
counters and six operating modes. Mode 3 of the 8253 is
the primary operating mode of the four dedicated USART
baud rate generators. The timer/counters and useful
modes of operation for the general use timer/counters
are shown in Table 1.

Interrupt Sources - The 22 interrupt sources originate
from both on-board communications functions and the
Multibus. Two interrupts are routed from each of the
four USARTs (8 interrupts total) to indicate that the
transmitter and receiver are ready to move a data byte to
or from the on-board CPU. The PIC is dedicated to
accepting these 8 interrupts to optimize USART service
request. One of eight interrupt request lines are jumper
selectable for direct interface from a bus master via the
system bus. Two auxiliary timers (TINTO from 8155 and
TINT1 from 8253) are jumper selectable to provide
general purpose counterltimer interrupts. A jumper
selectable Flag Interrupt is generated to allow any bus
master to interrupt the iSBC 544 by writing into the base
address of the shared dual port memory accessable to
the system. The Flag Interrupt is then cleared. by the
iSBC 544 when the on-board processor reads the base
address. This inierrupt provides an interrupt link between

When the TC is loaded,
the counter will begin.
On TC the output will
go low for one input
clock period.

Software
Triggered
Strobe
(Mode 4)
Single Pulse
Repetitive
Single Pulse

Interrupt Capability
The iSBC 544 board provides interrupt service for up to
21 interrupt sources. Any of the 21 sources may interrupt
the intelligent controller, and all are brought through the
interrupt logic to 12 interrupt levels. Four interrupt levels
are handled directly by the interrupt processing capability of the 8085A CPU and eight levels are serviced
from an Intel 8259A Programmable Interrupt Controller
(PIC) routing an interrupt request output to the INTR
input of the 8085A (see Table 2).

Operation

Function

,

Single pulse when TC
reached.
Repetitive single pulse
each time TC is
reached until a new
, command is loaded.

Counter

8253
TINT1

8253
BDG4*

8253
BDGO-4
TINT1

8253
BDG4*
TlNT1

8155
TlNTO

8155
TlNTO

,

• BDG4 is jumper selectable as an auxiliary baud rate generator to the
USARTs or as a cascaded output to·lINTl. BDG4 may be used in modes
2 and 4 only when configured as a cascaded output.

Table 2. Interrupt Vector Memory Locations
Interrupt
Source

Vector
Location

Interrupt
Level

Power Fail

TRAP

8253 TINT1
8155 TINTO
Ring Indicator (1)
Carrier Detect

RST7.5

24H
3C H

2

1

RST6.5

34 H

3

RST5.5
Flag Interrupt
INTO/-INT7/ (1 of 8)
INTR
RXRDYO
TXRDYO
RXRDY1
TXRDY1
RXRDY 2
TXRDY2
RXRDY3
TXRDY3

2C H

4

Programmabie

5-12

(1) Four ring indicator interrupts and four carrier detect interrupts are
summed to the RST 6.5 input. The 8155 may be interrogated to inspect
anyone of the eight Signals.

12-36

AFN·01271A

ISBC® 544
a bus master and Intelligent slave (See System Programmlng)_ Eight Inputs from the serial ports are monitored
to detect a ring indicator and carrier detect from each of
the four channels. These eight interrupt sources are
summed to a single interrupt level of the 8085A CPU. If
one of these eight interrupts occur, the 8155 PPI can then
be interrogated to determine which port caused the
Interrupt. Finally, a jumper selectable Power Fail Interrupt is available from the Multibus to detect a power
down condition.
8085 Interrupt - Thirteen of the twenty-two interrupt
sources are available directiy to four interrupt inputs of
the on-board 8085A CPU. Requests routed to the 8085A
interrupt inputs, TRAP, RST 7.5, RST.6.5 and RST 5.5
have a unique vector memory address. An 8085A jump
instruction at each of these addresses then provides
software linkage to interrupt service routines located
independently anywhere in the Memory. All interrupt
inputs with the exception of the TRAP may be masked
via software.
8259A Interrupts - Eight interrupt sources signaling
transmitter and receiver ready from the four USARTs are
channeled directly to the Intel 8259A PIC.' The PIC then
provides vectoring for the next eight interrupt levels.
Operating mode and priority assignments may be reconfigured dynamically via software at any time during
system operation. The PIC accepts transmitter and receiver interrupts from the four USARTs. It then
determines which of the incoming requests is of
highest priority, determines whether this request is of
higher priority than the level currently being serviced,
and, if appropriate, issues an interrupt to the CPU. The
output of the PIC is applied directly to the INTR input of
the 8085A. Any combination of interrupt levels may be
masked, via software, by storing a single byte in the
interrupt mask register of the PIC. When the 8085A
responds to a PIC interrupt, the PIC will generate a
CALl instruction for each interrupt level. These addressses are equally spaced at intervals of 4 or 8 (soft,
ware selectable) bytes. Interrupt response to the PIC is
software programmable to a 32- or 64-byte block of
memory. Interrupt sequences may be expanded from
this block with a single 8085A jump instruction at each
of these addresses.
Interrupt Output - In addition, the iSBC 544 board may
be jumper selected to generate an interrupt from the onboard serial output data (SOD) of the 8085A. The SOD
signal may be jumpered to anyone of the 8 MULTIBUS
interrupt lines (INTO/-INT7/) to provide an interrupt signal
directly to a bus master.

Power-Fall Control
Control logic is also included to accept a power-fail
Interrupt in conjunction with the AC-Iow signal from the
iSBC 635 Power Supply or equivalent.

Expansion Capabilities
When the iSBC 544 board is used as a single board communications controller, memory and 1/0 capacity may be
expanded and additional functions added using Intel
MULTIBUS™ compatible expansion boards. In this

mode, no other bus masters may be configured in the
system. Memory may be expanded to a 65K byte
capacity by adding user specified combinations of RAM
boards, EPROM boards, or combination boards. Inputl
output capacity may be increased by adding digital 1/0
and analog 1/0 expansion boards. Furthermore, multiple
iSBC 544 boards may be included in an expanded
system using one iSBC 544 board as a single board communications computer and additional controllers as
intell igent slaves.

System Programming
In the system programming environment, the iSBC 544
board appears as an additional RAM memory module
when used as an intelligent slave. Tt]e master CPU communicates with the iSBC 544 board as if it were just an '
extension of system memory. Because the iSBC 544
board is treated as memory by the system, the user is
able to program into it a command structure which will
allow the iSBC 544 board to control its own 1/0 and
memory operation. To enhance the programming of the
iSSC 544 board, the user has been given some specific
tools. The tools are: 1) the flag interrupt, 2) an on-board
RAM memory area that is accessible to both an offboard CPU and the on-board 8085A through which a
communications path can exist, and 3) access to the
bus interrupt line.
Flag Interrupt - The Flag Interrupt is generated anytime a write command is performed by an off-board CPU
to the base address of the iSSC 544 board's RAM. This
interrupt provides a means for the master CPU to notify
the iSSC 544 board that it wishes to establish a communications sequence. In systems with more than one
intelligent slave, the flag interrupt provides a unique interrupt to each slave outside the normal eight
MULTISUS interrupt lines (INTOHNT7/).
On-Board RAM - The on-board 16K byte RAM area that
is accessible to both an off-board CPU and the on-board
8085A can be located on any 4K boundary in the system.
The sel!lcted base address of the iSBC 544 RAM will
cause a flag interrupt when written into by an off-board
CPU.
Bus Access - The third tool to improve system
operation as an intelligent slave is access to the Multibus interrupt lines. The iSSC 544 board can both respond to interrupt signals from an off-board CPU, and
generate an interrupt to the off-board CPU via the
MULTISUS.

System Development Capability
The development cycle of iSSC 544 board based products may be significantly reduced using the Intellec
series microcomputer development systems. The Intellec resident macroassembler, text editor, and system
monitor greatly simplify the design, development and
debug of iSSC 544 system software. Ar optional ISIS-II
diskette operating system provides a linker, object code
locater, and library manager. A unique in-circuit
emulator (ICE-85) option provides the capability of
developing and debugging software directly on the iSSC
544 board.

12-37

AFN·01271A

iSBC® 544

SPECIFICATIONS

On·Board Dynamic RAM (MUL TIBUS access) - any 4K
increment OOOOO·FFOOO which is switch and jumper
selectable. 4K· 8K· or 16K·bytes can be made available
to the bus by switch selection.

Serial Communications Characteristics
Synchronous -

5-8 bit characters; automatic sync
insertion; parity.

Asynchronous -

5-8 bit characters; break character
generation; 1, 1V2, or 2 stop bits;
false start bit detection; break
character detection.

110 Capacity
Serial - 4 programmable channels using four 8251A
USARTs.
Parallel - 10 programmable lines available for Bell 801
ACU, or equivalent use. Two auxiliary jumper selectable
signals.

Baud Rates
Frequency (KHz)'
(Software Selectable)

Baud Rate (Hzj2
Asynchronous
Synchronous
~

--

153.6
76.8
38.4
19.2
9.6
4.8
6.98

--

38400
19200
9600
4800
6980

16

+64

9600
4800
2400
1200
600
300

2400
1200
600
300
150
75
110

--

Notes:
1) Frequency selected by 1/0 writes of appropriate 16·bit frequency factor
to Baud Aale Aegisler.
2) Baud rates shown here are only a sample subset of possible software
programmable rates available. Any frequency from 18,75 Hz to 614.4
KHz may be generated utilizing on·board crystal oscillator and l6·bit
Programmable Interval Timer (used here as a frequency divider).

8085ACPU
Word Size -

8,16 or 24 bitslinstruction; 8 bits of data

Cycle Time -1.45/usec ± .1 % for fastest executable
instruction; i.e. four clock cycles.
ClockRate-2.76MHz ±.1%

1/0 Addressing
On· Board Programmable I/O
Port

Data

Control

USAATO
USAATI
USAAT2
USAAT3
8155 PPI

DO
02
04
06
E9(Port A)
EA(Port B)
EB(Port C)

01
03
05
07
E8

Interrupts
Addresses for 8259A Registers (Hex notation, I/O ad·
dress space)
E6
E6
E7
E6
E7
E6

Interrupt request register
In·service register
Mask register
Command register
Block address register
Status (polling register)

Note: Several registers have the same physical address: Sequence of
access and one data bit of the control word determines which register
will respond.

Interrupt levels routed to the 8085 CPU automatically
vector the processor to unique memory locations:
24
TRAP
3C RST7.5
34
RST6.5
2C RST5.5

System Access Time
Dual port memory - 740 nsec
Note: Assumes no refresh contention

Memory Capacity

Timers

On·Board ROM/PROM - 4K, or 8K bytes of user installed
ROM or EPROM.

Addresses for 8253 Registers (Hex notation, I/O address
space)

On·Board Static RAM - 256 bytes on 8155.

Programmable Interrupt Timer Orie
D8
Timer 0
BDGO
D9
Timer 1
BDGl
DA
Timer 2
BDG2
DB
Control register

On· Board Dynamic RAM (on·board access) - 16K bytes.
Integrity maintained during power failure with user·
furnished batteries (optional).
On·Board Dyanmic RAM (MUL TlBUS access) - 4K, 8K,
or 16K·bytes available to bus by switch selection.

Memory Addressing
On·Board ROM/PROM - O·OFFF (using 2716 EPROMs or
masked ROMs); 0-1 FFF (using 2732A EPROMs)
On·Board Static Ram - 256 bytes: 7FOO-7FFF
On·Board Dynamic RAM (on·board access) - 16K bytes:
8000·BFFF.

, 12-38

Programmable Interrupt Timer Two'
DC
Timer 0
BDG3
DD
Timer 1
BDG4
DE
Timer 2
TINTl
DF
Control register
Address for 8155 Programmable Timer
E8 Control
ED Timer (LSB) TlNTO
EC Timer (MSB) TINTO
AFN·01271A

iSBC® 544
Input frequencies - Jumper selectable reference
1.2288 MHz± .1% (.814 usec period nominal) or 1.843
MHz ± .1 % crystal (0.542 usec period, nominal)
Output Frequencies (at 1.2288 MHz)
Single timer/counter

Dual timer/counter

Function

Memory Protect
An active·low TTL compatible memory protect signal is
brought out ,on the auxiliary connector which, when
asserted, disables read/write access to RAM memory on
the board. This input is provided for the protection of
RAM contents during the system power·down sequences.

(two timers cascaded)
Min

Max

Min

Max

Real-time
interrupt interval

1,63 usec

53.3 usee

3.26 usee

58,25 min

Rate Generator
(frequency)

18,75 Hz

614,4 KHz

0,00029 Hz 307,2 KHz

Bus Drivers
Function

Characteristic

Sink Current (rnA)

Data

Tri-slate

50

Address

Tri-state

15

Commands

Tri-state

32

Interfaces
Serial 1/0 - EIA Standard RS232C signals provided and
supported:
Receive Data
Carrier Detect
Ring Indicator
Clear to Send
Secondary Receive Data·
Data Set Ready
Secondary Transmit Data·
Data Terminal Ready
Request to Send
Transmit Clock
Receive Clock
Transmit Data
DTE Transmit Clock
• Optional if paratlell/O port is not used as Automatic Calling Unit.

Note: Used as a master in the single board communications computer
mode.

Physical Characteristics
Width:
Depth:
Thickness:
Weight:

30.48 cm (12.00 inches)
17.15 cm (6.75 inches)
1.27 cm (0.50 inch)
3.97 gm (14 ounces)

Electrical Characteristics
DC Power Requirements

Parallel 1/0 - Four inputs and eight outputs (includes
two jumper selectable auxiliary outputs). All signals
compatible with EIA Standard RS232C. Directly compat·
ible with Bell Model 801 Automatic Calling Unit, or
equivalent.

Current Requirements
Configuration

MUL TIBUS - Compatible with iSBC MULTlBUS.

Wlth4K
EPROM
(using 2716)

On· Board Addressing

Without
EPROM
RAM only 11)

All communications to the parallel and serial I/O ports,
to the timers, and to the interrupt controller, are via read
and write commands frolll the on·board 8085A CPU.

Vee= +5V
:!: 5% (max)
ICC = 3 4 max

Voo= :!:12VI Vee= -5V(3) VAA= -12V
:!: 5% (max)
:!: 5% (mal)
:!: 5% (mal)

100 = 350mA jISS::= 5mA max

3.3A max

350 mA max

390 rnA max

176 mA max

I
I

5 mAmax

390 mA max

20 mA max

J

5 mA max

RAM(2)
refresh only

IAA

=200mA

ma>

5 mAmax

200 rnA max

Notes: 1 For operational RAM only. for AUX power supply rallng
2 For RAM refresh only Used for battery backup reqUirements No RAM

Auxiliary Power

accessed
3 VSS IS normally derived on·boar[j Irom VAA- eliminating the need for a

An auxiliary power bus is provided to allow separate
power to RAM for systems requiring battery backup of
read/write memory. Selection of this auxiliary RAM
power bus is made via jumpers on the board.

Environmental Characteristics

Connectors

Operating Temperature: O°C to 55°C (32°F to 131°F)
Relative Humidity: To 90% without condensation

Interface

Pins
(qty)

Centers

Mating Connectors

(In.)

Bus

86

0.156

Viking 2KH43/9AMK12

Parallel 110

50

0,1

3M 3415·000 or
AMP 88083·1

Serial 110

26

0.1

3M 3462-000 or
AMP 88373·5

VSS supply tf It IS deSired to suppl,' VSS from the bus

the current

requirement IS as sho .... n

Reference Manual
502160 - iSBC 544 Intelligent Communications Con·
troller Board Hardware Reference Manual (NOT SUPPUE~
.
Reference manuals are shipped with each product only
if designated SUPPLIED (see above), Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department. 3065 Bowers
Avenue, Santa Clara. California 95051,

ORDERING INFORMATION
Part Number

Description

iSBC544

Intelligent Communications
Controller

12-39

AFN-01271A

iSBC® 561
SOEMI (Serial OEM Interface)
CONTROLLER BOARD
• Dedicated 110 controller provides a
direct connection of MULTIBUS@-based·
systems to an IBM 4361 Mainframe host
via IBM's SOEMI (Serial OEM Interface)
protocol
• Physical interface is via IBM 3270 coax
with a maximum distance of 1.5 km
• Maximum transmission rate of
2.36 Megabits/second
• Dual I/O processors manage both SOEMI
and MULTIBUS@ interfaces

• Includes a SMC-to-BNC cable assembly'
to attach into the IBM 3270 Information
Display.System
• On-board diagnostic capability provides
operational status of board function and
link with the Host
• Supported by a complete family of single
board computers, memory, digital and
analog I/O, peripheral and graphics controllers' packaging and software

The Intel iSB~ 561 SOEMI (Serial OEM Interface) Controller Board is a member of Intel's family of single board
computers, memory, 1/0, peripheral and graphics controller boards. It is a dedicated intelligent 1/0 controller
on a MULTIBUS form-factor printed circuit card. The board allows OEMs of MULTIBUS-based systems a direct,
standard link to an IBM System 4361 environment via the SOEMI (Serial OEM Interface). The iSBC 561 Controller also provides 4361 users access to the broad range of applications supported by hundreds of MULTIBUS vendors.
The SOEMI interface is comprised of an IBM System/370 programming interface and a 3270 coax interface.
It Is a flexible, high speed, point-to-point serial interface offered as a standard feature on the 4361 processor
family. The iSBC 561 SOEMI Controller Board contains two processors and provides the necessary intelligence
for conversion, control functions, and buffer management between the IBM mainframe and the MULTIBUS system. This board allows an IBM user to distribute control and information to MULTI BUS compatible systems for
a variety of applications including factory automation, data acquisition, measurement, control, robotics, process
control, communications, local area networking, medical instrumentation, and laboratory automation.

'IBM is a trademark of International Business Machine Corp.
lIitel Co~ration assumes no responsibility for the use of any circuhry other than circuitry embodied in an Intel product. No other circuit patent licenses
are implied. Information contained herein supersedes previously published specifications on these devices from Intel.

© INTEL CORPORATION, 1985

12-40

APRIL,1985
ORDER NUMBER: 280114·001

iSBC® 561 SOEMI Controller Board

The System/370 Programming Interface provides the
standard System/370 I/O instructions for exchanging
data between the host and the MULTIBUS-based system. System/370 applications see MULTIBUS system
memory as one or more entities called "spaces." The
4361 host system program writes to and reads from
these spaces. The user can define the number of
spaces or the layout of fields in the SOEMI interface
at his discretion and as required by the application and
the MULTIBUS system configuration.

SOEMI INTERFACE OVERVIEW
The Serial OEM Interface (SOEMI) is a new means of
connecting Original Equipment Manufacturer (OEM)
MULTI BUS-based systems and subsystems to an
IBM 4361 mainframe. Previously, the only low-cost
way to attach non-IBM equipment into the IBM mainframe environment was to use 3270 emulation software and hardware adaptors. This type of interface is
low-speed (approx. 19.6K bits/sec.) and not very flexible as to the type and format of data that can be transferred. The 3270 emulators must mimic the device
formats of the displays and printers that are typically
attached on this interface; stripping out command
characters, carriage return and line feed characters,
etc. The SOEMI Protocol is much faster and more flexible, in that any type of raw data or formatted data may
be sent across the connecting coax cable.

The 3270 coax interface provides the physical connection between the OEM MULTIBUS system and the
IBM 4361 host. The coax cable (type RG62AU) can
operate over a distance of 1.5 kilometers at a maximum
transfer rate of 2.3587 Mbits/second. The distance of
1.5 kilometers can be increased to a maximum of 3
kilometers by installing an 16M 3299 Terminal Multiplexer (repeater) between the IBM 4361 and the
MULTI BUS system. The protocol at the coax interface
includes a polling mechanism, a set of Write and Read
commands, and requires a buffer with an address
register at the OEM controller end'.

The SOEMI attachment into the MULTIBUS system
architecture, via the iSBC 561 SOEMI Controller
Board, extends the attachment capabilities of the
IBM 4361 to a variety of systems, boards, and I/O
devices provided by other manufacturers. Figure 1 is
an example of the variety achievable on Intel's MULTIBUS (IEEE 796) system architecture.

The actual connection to the IBM 4361 is made via the
IBM 3270 Information Display System's Display/
Printer Adapter (DPA) and/or Work Station Adapter
(WSA) coax ports. TheDPA can drive up to sixteen
3270/S0EMI coax ports, and is the standard configuration. The WSA is an optional add-on to the IBM
4361 that increases the total number coax ports
supported to 40. A typical 4361 configuration can support an aggregate data rate of approximately 45K
Bytes/second (approx. 360K bits/second).

The SOEMI interface utilizes the System/370
Programming Interface on the IBM 4361 to create the
protocols and formats required by a given application
for connection to and communication with virtually any
type of OEM device.

MULTIBUS" (IEEE 796)

8086
186,286, etc.
iRMX'· OPERATING
SYSTEM
XENIX'

RAM
ROM
EPROM
BUBBLES

• XENIX is a trademark of MICROSOFT

ETHERNET
IEEE 488
RS 232
MAP
ANALOG I/O
DIGITAL 1/0
OTHER INTERFACES

DEVICES
DISK
DISKETTE
PRINTER
DISPLAY (ASC II)

Figure 1. IBM 4361-to-MULTIBUS® Attachment Capability Block Diagram
12-41

Order Number: 280114-001

ISBC@ 561 SOEMI, Controller Board

OPERATING ENVIRONMENT
The iSBC 561 board functions as a slave to the host
mainframe, reacting and executing under System/370
program control as a,mainframe resource. In addition,
it has a full multimaster MULTIBUS interface that allows the board to arbitrate for bus ownership, generate bus clocks, respond to and generate interrupts,
etc. With the iSBC 561 controller connected to the
4361 mainframe, all MULTIBUS system resources are
available to the IBM host program/controller. From the
IBM 4361 side, the mainframe is capable of accessing the entire 16 MBytes of MULTIBUS system
memory, 64K Bytes of 110 space, and all on-board
resources of the iSBC 561 board. Other intelligent
MULTIBUS boards access iSBC 561 controller services through normal interrupt mechanisms. .

Using the SOEMI interface in a relatively low-level
application may simply require the user to write System/370 application control programs that reside in
the IBM 4361 mainfram~. A more elaborate implementation would also involve application programs that reside in the MULTIBUS system under its "native"
operating environment (i.e., iRMX or XENIX operating systems) and an end-ta-end protocol that ties both
sets of application programs together.

ARCHITECTURE
The iSBC 561 board is functionally partitioned into
three major sections: the front-end section, the common section, and the back-end section (see Figure 2).

r----------------------~

I
I
I
I
I
I
I
I
I FRONT-END,

_
'
1 ____

L.:_
I SECTION

I

ICOMMON
SECTION
I

MULTI BUS" I SYSTEM BUS

Figure 2, ISBCI!I S~1 SOEMI (Serial OEM Interface) Controller Board Functional Block Diagram

12-42

Order Number: 280114-001

iSBC® 561 SOEMI Controller Board

Front-end Processor Section:
IBM 4361 Interface

The control program for this high-speed, back-end
processor is resident in two local ROM sites. The
processor also has access to 16K bytes of static RAM
for local data storage.

The front-end section of the iSBC 561 Controller board
interfaces with the IBM mainframe via the IBM 3270
Information Display System, and consists of an 8X305
Signetics microcontroller, the 8X305 instruction
memory, and the coaxial interface. The 8X305 executes the coax commands and places the structured
field's instructions in shared memory buffers for subsequent execution by the back-end processor. The
front-end instruction memory consists of three 2K x 8
bit PROMs which provide the instruction code for the
8X305 processor and the information needed to
generate the various control signals required by the
8X305 to elicit system functions. The information contained in each PROM is not modifiable by the user.
The coaxial interface is based on a DP8340 transmitter component that converts 8-bit parallel data
received from the front-end processor to a 12-bit serial
stream, and a DP8341 receiver component, that converts a 12-bit serial stream of data from the mainframe
to parallel data with separated command and parity
bits.

The back-end section interfaces to other MULTIBUS
boards through two bus controllers, a bus arbiter, and
the address, data, and command buffers for access
over the 24 address lines and 16 data lines of the
MULTIBUS system bus.

OPERATION FLOW
The commands and information passed along the
coax by the IBM 4361 host to the iSBC 561 controller
represent what is known as a "structured field." The
iSBC 561 front-end processor strips out the 12-bit protocol header deposits the remaining structured field(s)
in the shared memory buffer, and notifies the backend processor. The back-end processor then processes these structured fields in order to access the proper
MULTIBUS memory space and 1/0 ports. It then
deposits the information or task in the space and notifies the Ml.)LTIBUS subsystem master that a transfer
has occurred and is awaiting service.

Common Section:
Shared Memory Buffer
The common section of the iSBC 561 board consists
of two 8 bit, bi-directional message registers and a
16K x 8 bit static RAM shared buffer. This shared
memory buffer between the front-end processor and
the back-end processor is the resource for transfer- .
ring information and control messages between. the
IBM 4361 host and the MULTIBUS system.

Back-end Processor Section:
MULTIBUS® Interface
The back-end section of the board provides an intelligent interface to the MULTIBUS system bus, and
consists of the 8086-2 microprocessor, local memory,
bus interface circuitry, and memory-mapped logic.
The 8086 processor is capable of either retrieving information the 8X305 placed in the shared buffer, or
placing information in the shared buffer, depending
on the direction of the transfer and type of operation
or task to be performed. The information is stored in
the shared buffer as a set(s) of structured fields. The
back-end processor transfers this information by performing 8- or 16-bit data transfers to or from the
MULTIBUS system bus, the shared buffer, and the
local memory.

When requiring service, the MULTIBUS system application sends an interrupt to the iSBC 561 board. The
board then issues an attention to the mainframe. At
this point, the 4361 is under no obligation or time constraint to service the interrupt, and its response is
application dependent.
The mainframe issues commands to service the interrupt. The information concerned with the interrupt is
then passed through the shared memory and serialized by the iSBC 561 board before being sent to the
mainframe. The exact communications protocol used
for this end-to-end transfer is defined by the user
application programs running in both operating
environments.

Interface Connector/Cable Assembly
The cable assembly used to connect the iSBC 561
SOEMI Controller Board to the IBM mainframe cable
assembly consists of RG180 type cable having an
SMC connector on one end (which mates to the iSBC
561 board right angle SMC connector) and a BNC
connector on the other end (which mates to the IBM
mainframe cable assembly connector).

12-43

Order Number: 280114·001

iSBC® 561 SOEMI Controller Board

SPECIFICATIONS

Cable Characteristics

Operational Characteristics

Impedance:

Back-end processor - Intel 8086-2/5 MHz
- 20-bit address path; 8/16-bit
data path

Capacitance: 35 pF/ft

Front-end processor - Signetics 8X305/8 MHz
- 16-bit instruction path; 8-bit
data path
Serial Transfer Rate -

2.3587 Mbits/second (max.
bit rate)
- 360K bits/second (approx.
aggregate throughput)

Serial Transfer
Rate

- Binary dipulse (with 12-bit
serial stream)

Propagation: 1.6 nslft

Environmental Characteristics
Operating Temperature:
Operating Humidity:

Shock:

Common memory -

Vibration:

8086-2 memory
8X305 memory

Physical Characteristics
Width:
Height:
Depth:
Weight:

10 to 85% non-condensing
(0° to 55°C)
- 40° to 75°C

30G for a duration of 11 ms with 1/2 sinewave
shape.
0 to 55 Hz with 0.0 to 0.010 inches peak
to peak excursion.

Reference Manuals
147048-001 - iSBC 561 SOEMI (Serial OEM
Interface) Controller Board Hardware
Reference Manual (NOT SUPPLIED)
Reference manual may be ordered from any Intel
sales representative, distributor office, or from Intel
Literature Department, 3065 Bowers Avenue, Santa
Clara, California 95051.

30.48 cm (12.00 in)
17.15 cm (6.75 in)
1.78 cm (0.70 in)
510 gm (18 oz)

Electrical Characteristics
DC Power Requirements:
Voltage + 5V
Current (Max) 6.28A
Current (Typ) 5.46A
Power Dissipation (Max)-

0° to 55°C at 200 LFM
air velocity

Non-Operating Temperature:

Memory Capacity - All iSBC 561 controller board
memory is available to on-board
firmware only.
16K Bytes of Shared Buffer .
memory (SRAM @ 0 wait state
access)
- 16K Bytes of EPROM;
16K Bytes of SRAM
-4K Bytes of Instruction memory
(EPROM)
,
- 2K Bytes of Control memory
(EPROM)

coax connector - 50 ohms (nominal)
external cable (user furnished)95 ohms (nominal)

35.5VA

GA33-1585-0 (File No. S370-03) - IBM Serial OEM
Interface (SOEMI) Reference Manual
(NOT SUPPLIED)
Reference manual may be ordered from IBM Advanced Technical Systems; Dept. 3291, 7030-16;
Schoenaicherstr. 220; .7030 Boeblingen. Federal
Republic of Germany.

ORDERING INFORMATION
Part Number
iSBC 561

Description
SOEMI (Serial OEM Interface)
Controller Board

12-44

Order Number: 280114-001

iSBC® 580 MULTICHANNEI!M BUS
TO iLBX™ BUS INTERFACE
• MULTICHANNELTM I/O bus 16·bit
Talker/Listener interface

• Data rates up to 5.3 megabytes per
second

• iLBXTM bus master interface (primary or
secondary)

• Addresses up to 16 megabytes of
iLBXTM bus memory

• Supports MULTIBUS® interrupts

• MULTIBUS®forlTl factor

The iSBC@ 580 Interface Board is a member of Intel's complete line of MULTIBUS'" microcomputers which maximize system performance by using separate optimized buses for intra-system communication (MULTIBUS system
bus), high speed I/O (MULTICHANNEL™ DMA I/O bus), expansion I/O (iSBX™ I/O expansion bus) and high-speed
memory expansion (iLBXTM execution bus). The iSBC 580 board provides a key element in the enhanced MULTIBUS
system architecture by implementing a MULTICHANNEL I/O bus to iLBX bus interface on a single 6.75 x 12.00 inch
printed circuit board. Using an LSI state machine with standard on-chip firm"Yare to maximize ihroughput, the on-board
Intel@8048 Single Component Microcomputer transfers data between a MULTICHANNEL Controller, device and up
to 16 megabytes of iLBX bus resident memory at rates up to 5.3 megabytes per second. Acting as a MULTICHANNEL
Talker/Listener, the iSBC 580 board increases the system's overall performance by transferring data between the
.MULTICHANNEL I/O bus and system memory without using the MULTIBUS system bus. As shown in Figure 1, this
allows other system tasks to utilize MULTIBUS resources while high-speed I/O block transfers are occurring simultane:ously. The board's high throughput and independence from MULTIBUS activities make it an ideal solution for applications that must transfer large amounts of data in and out of a MULTIBUS system, such as MULTIBUS to host computer
links and mass storage, graphics display and high-speed data acquisitioF1 subsystem interfaces.

12-45

"m_l®
II I'ell

iSBC@580

FUNCTIONAL DESCRIPTION
MULTICHANNELTM Interface Capabilities
Tht! MULTICHANNEL I/O bus is designed to provide a
general purpose, high-speed data path between a
microcomputer system and up to 15 block transfer devices. Using a 16-bit wide data bus and a simple asynchronous handshaking scheme, the MULTICHANNEL
bus can operate over distances up to 15 meters (50 feet)
with a maximum burst throughput of 8 megabytes/second. The bus consists of 16 address/data lines, 6 control lines, 2 'interrupt lines, parity lines and reset. Via
these signals; a MULTICHANNEL Supervisor or Controller may configure and then initiate a block data
transfer with any other device on the bus.

580 device registers (see Table 2) are 8-bit only. Register
Write operations use only the low order 8-bits (ADO-AD?).
Register Read operations place the data on the low order
data lines of the MULTICHANNEL I/O bus and set the
high order data lines to FFH.
Command
Code (Hex)
0
1

2
3

4

5

The iSBC 580 board acts as a 16-bit only Talker/Listener
device on the MULTICHANNEL I/O bus. As a Talker/
Listener, the board will respond to' Register Read or
Write and DMA requests iS,sued by the MULTICHANNEL
SupefVisor (typically an iSBC 589 board) or by a MULTICHANNEL Controller device.
The iSBC 580 board implements 32 MULTICHANNEL
Device Registers. The first three registers are the standard STO Status, SRC Status and SRC Mask Registers,
as defined by the MULTICHANNEL Bus Specification.
The remaining registers are used to communicate with
the on-board firmware and for user data storage. The
firmware operations which'may be initiated by writing
to the Command Register are listed in Table 1. The
iSsC 580 board always sends and receives a 16-bit
word on the MULTICHANNEL interface but, the iSBC®

6

7
8
9

A
B

C
D,E

F
10
11-lF

Operation
No Operation
Go off line forever
STO poll (diagnostic)
SRQ poll (diagnostic)
Set on-board timer
Read on·board timer
Start on·board timer
Stop on-board timer
G,enerate Task Complete
interrupt
Perform checksum on firm·
ware (diagnostic)
Turn on·board LED on
Turn on·board LED off
Reset
Reserved
Set interrupt mask
Read interrupt mask
Reserved

Table 1. iSBC® 580 Firmware Commands

MULTIBUS' SYSTEM BUS

Figure 1. iSBC®580 board, configured as an iLBXTM Bus Primary Master, transfers data between iLBXTM
memory and MULTICHANNEI!M devices without using the system bus. The ISBC®589 board
acts as the MULTICHANNEl!u Supervisor and performs data transfers between
MULTIBUS®memory and MULTICHANNEI!M devices.
12.46

iSBC®S80

The iSBC 580 board can generate maskable MULTICHANNEL. STO interrupts when the board detects a
parity error in incoming MULTICHANNEL data, when
the board attempts to address non-existent iLBX memory
or when the board detects a MULTI BUS interrupt from
the system in which it resides. The last type of interrupt
allows a single board computer to send an interrupt via
the iSBC 580 board to the MULTICHANNEL Supervisor
located in another MULTIBUS system. The board can
also generate a number of SRO interrupts on the MULTICHANNEL bus as shown in Figure 2.

x

x

X

X
:
LM :
TOM:
PEM:
MIM:
FPE:

LM

TOM

PEM

MIM

FPE

I.

Don't care
ILBX ™ locklmask
Time out mask (STO)
Parity error mask (STO)
MULTIBUS® Interrupt mask (STO)
Forced Parity Error mask

ter that requires only occasional or non-concurrent access to iLBX resources. The iLBX bus, with 16 data
lines, 24 address lines plus control, parity and interrupt
signals, utilizes all the pins on the P2 connector except
the four pins dedicated to the high-order apdress lines
of the MULTI BUS interface. The non-multiplexed address and data lines provide access to up to16 megabyles of iLBX bus resident memory, on up to 4 separate
expansion boards, at speeds comparable to that of a
single board computer's on-board resources.
The iSBC 580 board is configurable as either a Primary
or a Secondary Master on the iLBX bus. Figure 1 shows
a typical system configuration, with an iSBC 580 board
acting as a Primary Master. The board can access up
to 16 megabytes of iLBX memory. Supporting 16-bit
transfers on the MULTICHANNEL bus, the board accesses memory as 16-bit words on even byte iLBX address boundaries. To increase the performance of iLBX
memory read operations, the iSBC 580 board prefetches data from memory while the current data word
is being transferred over the MULTICHANNEL I/O bus.

Figure 2. iSBC®S80 Interrupt Mask Register (14H)

iLBXTM Bus Interface Capabilities
Used in conjunction with the MULTIBUS interface, the
iLBX bus is designed to provide off-board memory and
I/O expansion for single board computers while maintaining on-board performance. The iLBX bus provides
high-speed access to compatible expansion boards by
granting privileged use of the bus to a single Primary
Master. The bus also provides limited access to iLBX
bus expansion boards for, at most, one Secondary Mas-

Address

STO Status

DOH

SRO Status

01H

SRO Mask

02H

RESERVED

03H-OFH

General Purpose Registers

10W-1FH

• NOTE: 10H used as Command Register.

Table 2. iSBC®S80 MULTICHANNEL™ Device
Register Set

SPECIFICATIONS

Addressing - 16 megabytes on even byte boundaries
only

MULTICHANNELTM Bus
Interface -

Register

Signal Level - TTL compatible

Basic Talker/Listener

Transfer Mode Device Address and OEH

16-bit

MULTIBUS® Interface

Jumper selectable between DOH

Data - None
Addressing -

Registers - STO status, SRO status, SRO mask plus
device specific registers
Signal Level - TTL compatible

None

Interrupts - Jumper configurable to use any 1 of the 8
MULTIBUS interrupt lines. Interrupts are edge triggered.
Signal Level -

TTL compatible

iLBXTM Bus
Interface -

Throughput

Primary or Secondary (default) Master

Transfer Mode -

16-bit

5.3 megabytes/sec (2.65 megatransfers) max.
12-47

iSBC®S80

Environmental Characteristics

Connectors
iLBX™ BUS INTERFACE
Double-Sided Pins -

60

0.100 in.

Centers -

Mating Connectors' -

60

Centers -

0.100 in.

Mating Connectors' - 3M 3334-6000
Berg 65949-960
• Connectors compatible with those listed may also be used.

Physical Characteristics
Width -

12.00 inches (30.5 cm)

Height -

6.75 inches (17.1 cm)

Depth -

0.60 inches (1.5 cm)

Weight -

Relative Humidity -

0° to 55°C

to 90% (without condensation)

DC Power Requirements
Kelam RF30-2803-5
T&B Ansley A3020
(609-6025 modified)

MULTICHANNEL'"M BUS INTERFACE
Pins -

Operating Temperature -

12 ounces (340 gm)

Voltage -

Reference Manuals
144457-001 - iSBC 580 MULTICHANNEL to iLBX Bus
Interface Board Hardware Reference Manual (NOT
SUPPLIED)
143269-001 - Intel MULTICHANNEL Bus Specification (NOT SUPPLIED)
144456-001 -Intel iLBX Bus Specification (NOT SUPPLIED)
.
142996-001 - iSBC 589 Intelligent DMA Controller
Board Hardware Reference Manual (NOT SUPPLIED)
Manuals may be ordered from any Intel sales representative. distributor office or from Intel Literature Department. 3065 Bowers Avenue. Santa Clara. CA 95051

ORDERING INFORMATION
Part Number

Description

SBC 580

MULTICHANNEL to iLBX Bus
Interface Board

+ 5 volt only ± 5%

Current - 2.5 amps (typical)

12-48

iSBC®S89
INTELLIGENT DMA CONTROLLER
• Configurable as either an intelligent
slave or MULTIBUS® master
• 5 MHz 8089 I/O Processor
• MULTICHANNEL" DMA I/O bus inter·
face with Supervisor, Controller or
Basic Talker/Listener capabilities
• Two 8/16·bit iSBX™ bus connectors
• DMA transfer rates up to 1.25
megabytes per second

• User Command Interface Firmware
Package provides high level I/O
commands
• 8K bytes of high·speed dual· ported
static read/write memory
• Sockets for up to 32K bytes of read
only memory or additional byte·wide
static RAMs
• Three programmable timers

The iSBC 589 Intelligent DMA Controller is a member of Intel's complete line of MULTIBUS microcompter systems
which take full advantage of VLSI technology to provide economical computer based solutions for OEM applica·
tions. The iSBC 589 board is a general purpose, programmable, high·speed DMA controller on a single 6.75 x
12.00 inch printed circuit board. Using the board's dual·port RAM and standard EPROM resident firmware, the
on· board Intel 8089 1/0 Processor can perform memory to memory block transfers and complex 1/0 operations
via two iSBX connectors and the MULTICHANNEL I/O bus at DMA transfer rates up to 1.25 megabytes per second. Acting as an intelligent slave to one or more iSBC 286, iSBC 186, iSBC 86, iSBC 88 or iSBC 80, single board
computers, the iSBC 589 board enhances the sytem's overall performance by relieving the host CPU of time consuming I/O operations. The board's unique combination of performance, on-board intelligence and flexible hardware 1/0 interfaces make the iSBC 589 board the ideal solution for applications with specialized I/O requirements,
such as high-speed data acquisition, graphics, instrument automation and SPecialized peripheral control, that
previously would have necessitated an expensive custom designed 1/0 controller.

The !oHowing are trademarks 01 Intel Corporation and may be used only to describe Inlel products: Inlel, CREDIT, Index, Insile, Intel lee, Library Manager, Megachassis,
Micromap, MULTIBUS, PROMPT, UPI, "Scope, Prom ware, MeS, ICE, iRMX, iSBG, iSBX, MUL TIMODULE and iCS, Inlel Corporation assumes no responsibility lor the use of any
circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied.
'C)

INTELCORPQRATION, 1982

12-49

February, 1982
Order Number: 210354·001

iSBC@589

FUNCTIONAL DESCRIPTION
Two Modes of Operation .
The iSBC 589 Intelligent DMA Controller is capable of operating either as a stand-alone, highspeed data acquisition controller or as an intelligent slave. In stand-alone mode, external requests
cause the Intel 8089 1/0 Processor to execute 1/0
programs contained in its on-board memory. As an
intelligent slave to one or more Intel single board
computers, the lOP can perform sophisticated
DMA operations in response to high level commands issued by the host processor. While operating in either mode, the iSBC 589 board may act as a
MULTIBUS master to access any system memory
or 1/0 resources.

proach to DMA vastly simplifies the bus timings
and enhances compatibility with memory and peripherals, in addition to allowing operations to be
performed on the data as it is transferred. Operations can include such constructs as translate,
where the 8089 automatically vectors through a
lookup table and mask compare, both on the "fly".
This DMA capability includes flexible termination
conditions (such as external terminate, mask compare, single transfer and byte count expired).
The 8089 lOP supports two logically and physically
separate 1/.0 channels. The lOP maintains separate
register sets for each 1/0 channel which allows the
processor to alternate operation between the two
channels without incurring context switching
overhead delays.

Input/Output Processor
The iSBC 589 board contains a 5 MHz Intel 8089
HMOS 1/0 Processor, whose architecture and instruction set have been optimized for performing
DMA operations. The DMA function of the 8089
lOP uses a two cycle approach where the information actually flows through the 8089 lOP. This ap-

DMA Capabilities
The iSBC 589 board supports both individual byte
or word data transfers and DMA block transfer operations among its MULTICHANNEL interface, two
iSBX connectors, on-board RAM and the MULTI BUS
interface. Each of these devices may be combined

MULTICHANNEL
BUS

MULTIBUS' .
INTELLIGENT
SLAVE/MULTIMASTER
INTERFACE

. MULTIBUS' SYSTEM BUS

12-50

210354-001

iSBC®589

with any other as the source and destination for a
DMA operation. The same firmware commands are
used for all of the DMA source and destination
combinations.

MULTICHANNEL Capabilities
The MULTICHANNEL bus provides a high-speed
8-bit or 16-bit wide data path for block data transfers between external devices, such as instruments, peripherals and other computers, and the
iSBC 589 board. The iSBC 589 board can access up
to 15 other devices on the MULTICHANNEL bus at
distances of up to 15 meters and has the ability to
address up to 16 megabytes of memory and 16
megabytes of I/O on each device.
The iSBC 589 Intelligent DMA Controller can interface to the MULTICHANNEL bus in one of three
modes: as a Basic Talker/Listener, a Controller,
and a Supervisor. In Basic Talker/Listener Mode,
the iSBC 589 board monitors the MULTICHANNEL
for requests from a Controller or the bus Supervisor to perform a read or a write operation, but it
has no bus control capabilities. In Controller
Mode, the board can request temporary control of
the MULTICHANNEL bus from the bus Supervisor
and thus initiate data transfer operations. In its
MULTICHANNEL Supervisor configuration, the
iSBC 589 has the capability to initiate data
transfers on the bus, program other devices on the
MULTICHANNEL bus, resolve and grant bus priority to other devices, monitor bus status, handle bus
interrupts/ and control the MULTICHANNEL bus
reset line. All of these functions are maintained by
the on-board firmware based on parameter inputs
from the host. Please refer to the MULTICHANNEL
. BUS SPECIFICATION for detailed descriptions of
these modes.

iSBX™ Bus Capabilities
The iSBC 589 Controller contains two iSBX connectors which can support either 8-bit or 16-bit
MULTIMODULE boards. The iSBX connectors are
situated so that either two single-wide modules or
one single-wide and one double-wide MULTIMODULE board may be installed. A wide variety of
standard peripheral controllers and analog and
digital I/O MULTIMODULE boards are currently
available. In addition, the iSBX connectors provide
an opportunity to add over 30 square inches of
user designed hardware to the iSBC 589 board
which can be used to implement specialized I/O interfaces. For more information on specific iSBX

MULTIMODULE boards, consult the Intel OEM
Microcomputer System Configuration Guide.

MU LTIBUS® Capabilities
MULTIBUS system memory and I/O resources may.
be used as the source or the destination for an
iSBC 589 board transfer operation. The iSBC 589
DMA Controller may also be used as a high-speed
data mover to transfer blocks of data from one
MULTIBUS system RAM area to another. MULTI BUS
system memory may also be used to store Parameter Blocks to be executed by the on-board firmware package. The iSBG 589 board, acting as a
MULTIBUS Master, can access up to 16 megabytes
of MULTIBUS memory and up to 64K MULTI BUS
I/O locations_
Two MULTI BUS transfer modes are available.
Selection of the desired mode is done via the
Parameter Block. Transfer rates of up to 900K
bytes per second may be achieved in shared bus
mode, where the iSBC 589 board requests access
to the system bus for 1.4 microseconds to transfer
one byte or word to or from memory. In BUSLOCK
mode, the iSBC 589 is established as the sole
master which may access the system bus for the
duration of the block data transfer. In BUSLOCK
mode, the iSBC 589 board can transfer up to one
megabyte per second.

User Command Interface
Firmware Package
The iSBC 589 board is supplied with a firmware
package contained in two Intel 2732A EPROMs
that greatly simplifies programming by providing a
high level software interface to the on-board
resources .. In the majority of applications, the
board may be programmed entirely via the firmware and without writing any 8089 lOP assembly
language code. The firmware package supports
the two channel operation of the 8089 lOP. Each
channel has its own Parameter Block area containing the required information for independent chan.
nel operation.
To invoke an I/O operation, the user creates one or
more Parameter Blocks in memory which describe
the desired operation. The firmware, which consists of a series of 8089 lOP assembly language
task programs, will interpret the Parameter Blocks
to configure the board's interfaces or to perform
byte, word or DMA block transfers. Each Parameter Block consists of a command byte, status.
byte, data source and destination pOinters and
12-51

210354-001

iSBC®S89

other information as shown in Table 1. Commands
recognized by the firmware package are listed in
Table 2. The Execute User Task command is of
special interest because it allows the user to ex·
tend the capabilities of the iSBC 589 board byadding his own 8089 lOP assembly language routines
to the firmware package, while retaining the struc·
ture and standard functions supplied by the firm·
ware.

Table 1. User Command Interface Firmware
Parameter Block Byte Format
Command Byte
Status Byte
Command Chaining Pointer
Command Chaining Pointer
Command Chaining Pointer
Command Chaining Pointer
Device Number
MULTICHANNEL Data Type
Memory Pointer or Register Number
Memory Pointer or Register Number
Memory Pointer or Data Storage Location
Memory Pointer or Data Storage Location
Device Number
MULTICHANNEL Data Type
Memory Pointer or Register Number
Memory Pointer or Register Number
Memory Pointer
Memory Pointer
Byte Counter
Byte Counter
Byte Counter

In addition to executing transfer operations, the
firmware package executes an initialization sequence which prepares the 8089 lOP and the on·
board RAM, EPROM and 1/0 resources for further
firmware execution.

RAM Capabilities
In its standard configuration, the iSBC 589 board
contains 8K bytes of high·speed, dual'ported
static RAM. The first 256 bytes are dedicated for
use by the on·board firmware. The remaining onboard RAM may be used for storing additional
Parameter Blocks for the firmware or as a data buf·
fer for I/O operations. This memory is always addressed by the 8089 lOP as locations OOOOH to
1 FFFH. However, for. M U L TI BUS accesses
through the dual-port, the RAM base address may
be configured on any 8K·byte boundary in the first
megabyte page of the MULTIBUS memory space.
Users may install additional on-board RAM by
placing two byte-wide RAMs in the 28'pin JEDEC
standard sockets. The additional RAM is accessible only by the on-board 8089 lOP.

EPROM Capabilities
The iSBC 589 board can be configured with up to
32K bytes of non·volatile read only memory. Four
28·pin sockets are provided for the use of Intel
2716,2732 and 2764 EPROMs or byte·wide RAMs.

Table 2. User Command Interface Firmware Package Commands
Command

Description

NO·OP

Test the intelligent slave interface on the iSBC 589 board. The board reads the
Parameter Block, generates status and interrupts the host on completion.

REGISTER WRITE

Write either a word or byte of data from the Data Storage Location within the Paramo
eter Block to the. location specified by the Parameter Block Device Number and
Register Number.

REGISTER READ

Read either a word or byte of data from the location specified by the Parameter
Block Device Number and Register Number to the Data Storage Location within the
Parameter Block.

PERFORM DMA

Transfer data beginning at the location specified by the source Memory Pointer,
Device Number and Register Number parameters to the location specified by the
destination Memory Pointer, Device Number and Register Number parameters. The
number of transfers is specified by the Byte Count parameter. A Byte Count of 0
enables DMA until an external terminate condition is sensed.

EXECUTE USER TASK

Transfer 8089 lOP fJrogram execution from the Firmware Package to a user defined
8089 assembly language routine beginning at the location specified by the Memory
Pointer parameter. Upon completion, the user task returns control to the firmware.
12-52

210354-001

iSBC@589

In the default configuration, the board is jumpered
for 32K devices, and, two 2732A EPROMs containing the firmware package are installed. Users who
wish to extend the. capabilities of the Hrmware
may do so by programming unused locations in
the firmware PROMs, installing two additional
2732A PROMs or copying the firmware into 2764s
along with their own code. As an alternative, two
byte-wide RAMs of equal or smaller capacity may
be installed in the open sockets and used in conjunction with the firmware PROMs.

System Development Capabilities
For applications where it is necessary to extend
the User Command Firmware Package by writing
additional 8089 lOP assembly language code, the
development cycle can be significantly reduced
and simplified by using the Intellec Series Microcomputer Development Systems. The 8089 lOP
Software Support Package which includes a
Macro assembler, linker, locater and PROM mapper is supported by the ISIS-II disk-based operating system.

Programmable Interval Timers

In·Circuit Emulator

Three independent, fully programmable 16-bit intervalievent counters are provided by an 8254-12
Programmable Interrupt Timer. Each counter may
operate in either BCD or binary mode. One counter
is used by the. firmware package, leaving two
counters available to the firmware user. These
timers may be used for a variety of on-board and
off-board functions including timed-interval DMA
requests and terminations or fail safe time out
control for I/O operations:

The ICE-86A or ICE-86 and ICE-86U upgrade kit pro~
vide the necessary link between the software development environment provided by the Intellec
system and the "target" iSBC 589 execution system. In addition to providing a mechanism for loading executable code and data into the iSBC 589
board, the In-Circuit Emulator provides asophisticated command set to assist in debugging software and in final integration of the user hardware
and software ..

SPECIFICATIONS

iSBXTM MULTIMODULETM MODULE boards

8089 lOP

Two (2) iSBX MULTI-

110 Addressing

WORD SIZE

Interface

Instruction - 16 to 40-bits

isax Connector #1
ISBX Connector #2

Data - 8, 16-bits

~ULTICHANNEL

SYSTEM CLOCK

Interval Timer
Other On-board Devices

5.0 MHz±0.1%

I/O Addresses
FF80 thru FF9F
FFAO thru FFBF
FFDO thru FFEE
FFC8 thru FFCE
FFCO thru FFC6
FFFO thru FFFE

CYCLE TIME
2.2 microseconds for the fastest instructions

Memory Capacity
ON-BOARD EPROM

System Access Time
Dual-port Memory - 550 nanoseconds (worst
case, without contention from on-board access)

Device
Toial Capacity
2716
8K bytes
2732A16K bytes
2764
32K bytes

Address Range
FEOOO-FFFFFH
FCOOO-FFFFFH
F8000-FFFFFH

ON-BOARD RAM

110 Capacity
MULTICHANNEL I/O Bus - 1 MULTICHANNEL
port which supports 8 and 16-bit transfers and can
be configured as a Basic Talker/Listener, Controller or Supervisor

Total Capacity - 8K bytes
On-Board Address - 00000-01 FFFH
MULTIBUS@Address - Jumper selectable on 8K
byte boundaries. Default is 0H.
12-53

210354-001

iSBC®S89

110 Transfer Rates (microseconds/tranfer)
MULTICHANNEL

ISBXTM

MULTICHANNEL

-

IS~X

2.0

MULTIBUS@

On·Board
RAM

Shared

Buslock

2.0

2.4

2.2

1.8

2.0

2.4

2.2

2.0

2.4

2.4

2.8

2.2

2.2

2.2

-

-

MULTIBUS (Buslock)

2.4

2.0

On· Board RAM '

1.8

1.8

2.2

2.0

1.6

MULTI~US

(Snared)

Timers

"
.
Input Frequencies - Jumper selectable at 1.25
MHz, 625 KHz or 312.5 KHz

Output Frequencies/Timing h1tervaiil.

Dual Tlme.r/Counter
(Two Timers Cascaded)

Single Timer/Counter.
Function
Minimum

Maximum

Minimum

Maximum

Real·time delay

1.6 usee

210 msee

3.2 \lsee

1.37x 104 see

Programmable one·shot

1.6 usee

210 msee

3.2 usee

.1.37x 104 see

Rate generator

4.76 Hz

625 KHz

7.3 x 10- 5 Hz

312.5 KHz

Square·wave rate generator

4.76 Hz

625 KHz

7.3x 10- 5 Hz

312.5 KHz

Software triggered strobe

1.6 usee

210 msee

3.2 usee

1.37x 10' see

Hardware triggered strobe

1.6 usee

210 msee

3.2 usee

1.37 x 10' see

Connectors
Double·Slded
Pins (qty.)

Centers
(In.)

MULTIBUS
System Bus

86

0.156

ELFAB BS1562043PBB
Viking 2KH43/9AMK12 Solderecj PCB Mount
EDAC 337086540201
ELFAB BW1562D43PBB
EDAC 337086540202
ELFAB BW1562A43PBB Wire Wrap

Auxiliary Bus

60

0.100

EDAC 345060524802
ELFAB BS1020A30PBB
EDAC 345060540201
ELFAB BW1020D30PBB Wire Wrap

iSBX Bus (2) .

36 '

0.100

iSBX 960·5

MULTICHANNEL BUS

60

0.100

3M 3334·6000
BERG 65949·960

Interface

Mating Connectors·

• NOTE: Connectors compatible with those listed may also be used.
210354-001

iSBC® 589

Interfaces
MULTIBUS'" -

All signals TTL compatible

MULTICHANNEL ISBXTM Bus Timers -

Relative Humidity tion)

All signals TTL compatible

to 90% (without condensa-

Electrical Characteristics

All signals TTL compatible

DC POWER REQUIREMENTS

All signals TTL compatible

Auxiliary Power/Memory Protect
There is no provision made on the iSBC 589 board
for battery backup of RAM or for power fail detection.

MULTIBUS® Bus Drivers
Function

Characteristic

Sink Current (rnA)

Data
Address
Commands

Tri·state
Tri-state
Tri-state

32

(+ 5V + 5% maximum)

Without EPROM
With 8K EPROM
(using four 27165)
With 8K EPROM·
(using two 2732As)
With 16K EPROM
(using four 2732As)

4.7 amps

With 32K EPROM
(using four 21645)

32
32

Current Requirements

Configuration

5.4 amps
5.0 amps
5.3 amps
5.3 amps

• Factory default configuration

Reference Manuals
142996·001·- iSBC 589 Intelligent DMA Controller
Board Hardware Reference Manual (Not Supplied)

Physical Characteristics
Width -

12.00 in (30.48 em)

Height -

7.05 in (17.9 em)

Depth Weight -

142686·001 Supplied)

.50 in (1.27 em)

143269·001 - Intel MULTICHANNEL Bus Specifi·
cation (Not Supplied)

16 oz (453.6 gm)

Manuals may be ordered from any Intel sales representative, distributor office or from Intel literature Department, 3065 Bowers Avenue, Santa Clara,
California 95051

Environmental Characteristics
Operating Temperature -

Intel iSBX Bus Specification (Not

O·C to 55·C

ORDERING INFORMATION
Part Number

Description

SBC 589

Intelligent DMA Controller
Board

12-55

210354-001

Speech Products

13

inter
iSBC® 570, 576, 577
INTEL SPEECH TRANSACTION FAMILY
• Friendly man-machine interfacespeech is the most natural and most
easily learned form of interaction for
man.

• Freedom of Movement-More efficient
work flow

• Lower data entry cost-sourcedata
capture

• Easier training-interactive, generic
terminology

• Hands and eyes free-ability to
perform another primary task

• Higher accuracy-operator mental
encoding is eliminated.

• Complements keyboard/CRT-new
dimension to data entry

Users world wide are recognizing the many advantages of having Automatic Speech Recognition (ASR) and
Electronic Speech Synthesis (ESS) in their products and applications. Speech I/O is a new dimension in data
entry/control that complements other I/O mechanisms.
Speech 110 as a direct man-machine inter~ace can be used for a broad range of applications, such as office and
factory automation, computer-aided design, QC inspection stations, inventory control-and many more.
Whatever your application is, the benefits of speech I/O are measured in dollars saved, improved productivity
and improved product quality.

The following are trademarks of Intel Corporation and its affiliates and may be used only to identify Intel products: ax?, CREDIT, t, ICE, ieS. 1m, Insite.lntel,INTEL, Intelevision, Intellee,
iMMX, iOS?, iPOS. iRMX. iSSC, iSeX, Library Manager, MeS, MULTIMODULE, Megachassls, Micromainframe, Micromap, MULTIBUS, Multichannel, Plug·A-Subble, PROMPT,
Promware, RMX/80, System 2000, UPI, and the combination of ieS. iRMX, iSaC, iSeX, ICE, MeS,or UPI and a numerical suffix. Intel Corporation Assumes No Responsibilityfor the IJse

of Any Circuitry Other Than Circuitry Enbodied in an Intel Product. No Other Patent LiC'.enses are implied. ©INTEL CORPORATION, 1982.

13-1

FEBRUARY 1983
ORDER NUMBER: 210598

ISBCQ!) 570, 576, 577

A complete system includes not just the capabilities
for signal conditioning, Automatic Speech Recognition (ASR), and Electronic Speech Synthesis (ESS),
but must include speech transaction processing as
well. The Speech Transaction Processing task
includes:

In computer-aided design and manufacturing
(CAD/CAM), design commands by speech allow the
design engineer to keep his attention focused on the
actual graphic elements.
In manufacturing, speech transactions provideimportant advantages in productivity. Defect tracing,
production line monitoring and synchronization, and
factory data collection, all benefit from direct human
speech to computer communication.

-The conversion between spoken language and
coded representation
-Operator prompting and feedback
-Message editing
-Message buffering

In the automated office, ever-increasing machine intelligence can be controlled without mastering of
typing skills.

In addition, development tools should be available
for the generation of speech transaction files that
will define the operations of the speech I/O system.
Figure 3 shows the function of each member of the
Intel Speech Transaction Family.

The basic concept of a speech I/O system is shown in
Figure 1. The speech I/O system provides a humanoriented interface with a machine-oriented
computer-based information system or process. The
speech I/O system recognizes speech inputs, provides visual/audio prompts and verification, and
handles message editing and buffering. Depending
on what was recognized, digitally coded data is then
used to interact with the machine-oriented
computer-based system.

The Intel Speech Transaction Family, iSBC® 570,
iSBC® 576 and iSBC® 577, is a familyof products that
provides a minimal risk path to add speech InpuVOutput (I/O) to your product line. The Speech
Transaction Family will allow you to move from evaluation to integral speech driven products without
major redesigns. Depending on your stage of product development, whether it is an evaluation, or a
product simulation, or an add-on speech option, or a

The functional blocks of a speech I/O system are
shown in Figure 2.

HUMAN-ORIENTED

(

MACHINE-ORIENTED

PROMPT)

SPEECH
TRANSACTION
PROCESSING

DIGITALLY CODED DATA

NOTES:
1. INTERACTIVE
2. CONVERSION BETWEEN SPOKEN LANGUAGE AND CODED REPRESENTATION
3. PROMPTING & FEEDBACK TO OPERATOR
4. MESSAGE BUFFERING
5. MESSAGE EDITING

Figure 1. Basic Concept

13-2

COMPUTER-BASED
INFORMATION
SYSTEM OR PROCESS

ISBC® 570, 576, 577

APPLICATION
PROCESSING

Isec'

PRODUCT
FAMILY

Figure 2. Functional Blocks of Speech 1/0 System.
fully integrated speech product, the Speec,h Transaction Family's flexibility allows. your speech I/0application to grow with a minimal amount of engineering
effort. The Speech Transaction Family allows you to
adapt your product to various markets as your application needs change, without a major redesign.
Whether it is a configured speech development system, or easy-to-integrate speech board, or a maximum value-added speech component chip set, an
Intel product is ready to meet your needs.

Intel provides the total solution. Speech hardware has
been designed to work with our wide selection of
MULTIBUS@ single-board computers, memory cards,
and data 1/0 cards. Speech software is based on the
Real-Time Multi-Tasking Executive (RMX-88). Speech
transaction software development has been
implemented on our universal iSWS 090 Speech 1/0
Engineering Workstation. All of the pieces have been
engineered to provide an easily integrated speech I/O
solution.

Development of your speech VO system may have
been your stumblin·g block in the past. The requirement for speech technology expertise, extensive
hardware development and extensive software development are a thing of the past. Integral to the
Speech Transaction Family are highly sophisticated
computer-based design and development tQols that
will take you from product concept to a working
speech product with a minimal effort. In-depth
knowledge of speech algorithms and of speech
human factors considerations are no longer an absolute requirement of your system designers.

Speech 1/0 is a new technology area. Intel has developed a family of products and services, that will fit
your development sequence needs for a new technology with minimal risk and ease of use. A very
likely evaluation and development sequence you
may follow is illustrated in Figure 4 and Figure 5
along with Intel's products and services that are offered to meet those needs. Having products and services that can satisfy the illustrated sequence is very
important in reducing the risk, engineering cost, and
lowering incremental investments necessary as
product requirements change.

13-3

iSBC® 570, 576, 577

SPEECH TRANSACTION BOARO (ISBC' 576)

APPLICATION
PROCESSING

ISBC" PRODUCT
FAMILY

I
I

OPTIONAL SPEECH SYNTHESIS

L __________

-L-====.J
SPEECH
TRANSACTION
GENERATOR

SPEECH TRANSACTION DEVELOPMENT SET
(ISBC"S70)

NOTES:
• MAY BE PURCHASED AS SPEECH TRANSACTION CHIP SET (iSSC· 577)
•• CONTACT INTEL

Figure 3. Functional Blocks of the Intel Speech Transaction Family.

SPEECH TRANSACTION
DEVELOPMENT SYSTEM

SPEECH TRANSACTION
DEVELOPMENT SYSTEM

T·. . ·. · . .
...................
............
" .....

/:.:::::::::::::::::/

usL
TECHNOLOGY
EVALUATION
AND DEMO

USING

DESIGN PHASE,
APPLICATION
STUDIES,
FLOWCHARTS

Figure 4. Application Definition Phases
13-4

APPLICATION
SIMULATION &
SPEECH 1/0

inter

iSBC® 570, 576, 577

ISBC'XXX

~

SPEECH TRANSACTION
GENERATOR

E:::::::::::::::::7

USING

J

SPEECH
TRANSACTION
SOFTWARE
DEVELOPMENT
AND TesT

INITIAL
SPEECH 1/0
ADD-ON
PRODUCT

FULLY INTEGRATED
MAXIMUM VAWEADDED SPEECH

1/0

Figure 5. Application Implementation Phases

The sequence starts with a workshop to learn about the
Speech Technology and to develop a necessary
knowledge base to evaluate potential applications. The
next stage, an evaluation-oriented Speech Transaction
Development System (iSBC~ 570 and iSWS 090
Speech I/O Engineering Workstation), provides
technology evaluation and demonstrations without
engineering investment. Using the experience from the
two previous stages, plus field and factory application
support, the design phase can now proceed. Once the
application framework .has been established,
application simulation can be performed using the
Speech Transaction Development System.

Upon successful completion of simulation, the
speech transaction software development can be
easily completed on the same Speech Transaction
Development System. The initial speech I/O products
can then be shipped using the Speech Transaction
Board (iSB~ 576). When higher volume justifies
increasing the value added, the chip set, iSB~ 577,
can be used. Throughout the process, whether it is
system, board. or chip set. the same software is
utilized. Very little is lost as your product needs
change. The level of investment required tracks the
stage of product development. Your risk and exposure is kept to a minimum.

13-5

iSBC® 570
. SPEECH TRANSACTION· DEVELOPMENT SET
• Speech Transaction Generator
provides:
-Interactive deSign environment
-A speech transaction structure
embodying good human factors
engineering
-Automatic error checking of
transaction design
-Symbolic labeling for easy system
designer reference
-Speech Transaction File data base
manager facilitates Speech
Transaction File changes

• Complete De"elopment Support Set for
the Intel Speech Product Family.
Includes:
-Speech Transaction Generator
-iSBC® 576 Speech Transaction Board
-iSBC@575 Operator Control Unit
-Microphone .
.
-Demo program
-Speech Transaction Design Manual
• iSWS 090 Speech I/O Engineering
Workstation based

The Speech Transaction Development Set, iSBC® 570, provides an easy-to-use package for speech transaction
evaluation, design simulation and application development. Along with Intel's Speech Design Workshop, the Speech
Transaction Development Set becomes the starter kit that will move you into the forefront of speech I/O systems.
Using the demo program supplied, you are quickly introduced to the important attributes of speech. Using the
iSWS 090 Speech I/O Engineering Workstation and writing/modifying software based on examples provided, you'
can quickly simulate your application without hardware development. And finally, with the Speech Transaction
Generator, your speech transaction structure, definition, transaction file coding and management become a
well-defined automated task.

13-6

inter

ISBC$ 570

of the STG and resides on EPROM in an STB environment. The second part is the data base manager for the
STG and resides as an executable file under ISIS. The
STG allows a system designer (with appropriate
knowledge of transaction, fields, vocabulary and
synthesis) to specify a STF easily. The STG maintains
a set of files on the iSWS 090 Speech 110 Engineering
Workstation as the data base. In this manner, the STG
is the customization tool used by the speech system
designers to prepare application-unique speech transactions that will execute on the STB under the supervision of the Speech Transaction Manager (STM). The
STG also allows the system designer to dump portions
of this data base in an ASCII-text format to a file. This
ASCII-text file is useful for transporting data base entries
between the STG implemented on other than an ISIS
environment.

FUNCTIONAL DESCRIPTION
The iSBCI!i) 570 Speech Transaction Development Set
has been designed to meet your speech I/O needs as
your level of involvement with speech I/O system
grows. The Speech Transaction Development Set
serves three very important functiol)s. The three
functions are: 1) Technology Evaluation and
Demonstration, 2) Application Simulation of Speech
110, and 3) Design and Development of Speech Transaction Software. These three functions are discussed below.
Technology Evaluation and Demonstration - A
complete demo package is provided for you to demonstrate the capabilities of speech 110. This package
allows you to evaluate the speech technology without
investing engineering design and development time. It
is easy to use. Major attributes of a speech 110 system
are highlighted .and fully documented. The host system
for the demonstration is the iSWS 090 Speech 110
Engineering Workstation.

The things that a system designer can manipulate
with the STG are termed "objects." Objects can be
catagorized into structures and non-structures.
Structures are generally a string of characters or a
list of tags. Objects are classified as follows:

Application Simulation of Speech 110 - The Speech·
Transaction Development Set provides the necessary
tools and program examples for you to easily simulate
your speech 110 system using the iSWS 090 Speech 110
Engineering Workstation as the host. With the
iSBC@ 570 and the iSWS 090 Speech 110 Engineering
Workstation, you can now design a speech 110 system
for your application and see how it performs. Your
speech transaction structure can be developed and
checked out without doing hardware and software integration with the rest of your system.

STRUCTURES
1. Transaction
2. Fields
3. Vocabulary
4. Synthesis
NON-STRUCTURES
1. Group (list of vocabulary tags)
2. Strings (list of ASCII or non-ASCII characters)

Brief De$cription of Commands

Design and Development of Speech Transactions The Speech Transaction Generator which is provided
as part of the Speech Transaction Development Set
facilitates the design and· development of speech
transactions. The Speech Transaction Generator is
an interactive software development tool that
generates the Speech Transaction File (STF) that
configures your speech I/O system. The Speech
Transaction Generator checks for inconsistencies.or
incomplete transactions. The generated code is
guaranteed to be fully compatible with the Speech
Transaction Board. The Speech Transaction
Generator will not only shorten your development
time, but will also facilitate a well human-engineered
speech I/O interface.

UTILITY COMMANDS
HELP-Provides information about the objects
EXIT-Close data base and exit STG
PREfix-Specify prefix character for DEFine or
MODify commands
EDIT COMMANDS
DEFine
DEFINE TRANSACTION:
1. Vocabulary tag to enable this transaction?
2. Training group?
3. Starting field?
4. Host buffer strategy?
5. Verification actions?
6. Special reject actions?
7. Special illegal function action?

OPERATIONAL DESCRIPTION
The Speech Transaction Generator is implemented
in two parts. The first part is the processing element

13-7

inter

ISBC® 570

VALIDATION AND GENERATION COMMANDS

DEFINE FIELD:
1. Prompt?
2. Help message?
3. Prefix for host message?
4. Suffix for host message?
5. Special functions enable?
6. Valid sources?
7. Multiple utterance path?
If yes,
a) Vocabulary words?
b) Next field?
c) Maximum number of utterances?
d) Fixed or variable?
8. Vocabulary words?
9. Next field?

VALidate
Sequences through each of the transactions specified and validates them for completeness and proper
definition.
GENerate
Takes the result of a successful validate command
and produces a memory image of the STF. The STF
can now be executed.
INTERROGATION COMMANDS
DISplays
Displays the contents of the objects

DEFINE VOCABULARY:
1. Name?
2. Visual verify?
3. Audio verify?
4. Host message?
5. Visual train?
6. Audio train?
7. Special functions?

LiSts
Lists the di rectory of the objects
FILE INTERFACE COMMANDS
DUMp
Passes results of current validation and outputs it to
the hostin a .DMP file.

DEFINE SYNTHESIS:
1. Function?
2. Duration?
3. Delay?

USE
Takes command input from the specified file.

DELete
Removes objects from the data base.
MODify
Modifies objects already entered into the data base
with the DEFine command.

-Speech Transaction Generator software
and firmware.
-Speech I/O Demo Software.
-iSBC@ 575 Operator Control Unit.
-Shure SM-10A Microphone.
-Speech Transaction Design Manual.

SPECIFICATIONS
Operating Environment
iSWS 090 Speech 1/0 Engineering Workstation (Model
800, Series II, and Series III with 64K byte of RAM).
SUPPLIED EQUIPMENT
iSBC' 576-Speech Transaction Board with Speech
Transaction Manager Firmware.

ORDERING INFORMATION
Part Number Description
iSBC' 570

Speech Transaction Development Set
13-8

OPTIONAL EQUIPMENT
iSBX®-351-RS232 Multimodule
iSBC®-342-EPROM expansion module
-SBX synthesizers

iSBC® 576
SPEECH TRANSACTION BOARD
• Up to 200 recognition words or phrases

• On-board diagnostic

• Automatic ASR and ESS handling

• Multibus or serial host interface

• On-board Speech Transaction Manager

• iSBX® interface

• 8086, 16-bit CPU

• Built-in buffer editing functions

The iSBC® 576 Speech Transaction Board is the heart of a speech I/O system. Beside providing Automatic
Speech Recognition (ASR) capabilities, a ROM-resident Speech Transaction Manager (STM) is included on the
board. This provides a flexibile operating structure for the system designer with a fully buffered speechgenerated inp'ut-transaction handling capability. Flexibility has been designed into the STM to allow integration
into existing applications without a major rewrite/redesign of host application software and hardware. The
Speech Transaction Manager accommodates a Speech Transaction File which configures the iSBC® 576
Speech Transaction Board for each application. Also included on the board are three selectable audio feedback
tones, visual feedback/control via a CRT terminal or printer, and an optional Electronic Speech Synthesis (ESS)
capability.

13-9

inter

ISBC$ 576

FUNCTIONAL DESCRIPTION
Figure 6 shows the functional structure of the
Speech Transaction Board.
Input Signal Conditioning-Microphone input signal
is amplified and low-pass filtered. The conditioned
signal is then digitized and passed through 16 bandpass digital filters implemented by 2920/21 analog
signal processors. The 2920/21s are synchronized
and are operating in parallel. The bandpass filter
information is then assembled by an 8048 microcomputer for algorithm processing by an 8086 processor.
System-to-system portability is guaranteed by the
usage of digital signal processing techniques.
ASR-Automatic Speech Recognition is accomplished by the 8086 processor in conjunction with
two 2920/21 digital signal processors and an 8048
microcomputer: ASR handling is done completely
under the control of the Speech Transaction
Manager. This task is transparent to the system designers. Automatic statistics are also provided to
track system performance.
Tone Generator-3 audio tones are available for use
as a prompt. The tones are generated within a 2920
analog signal processor. The tone generator also
generates test patterns for use by the diagnos'tic
section.
Diagnostic-Under the control of the Speech Transaction Manager, a diagnostic check of the speech

recognition hardware and software can be performed. System integrity is automatically determined
to. insure repeatable performance.
Output Signal Conditioning-Output amplifiers are
provided to drive a speaker for the audio tones.
Volume can be varied by a potentiometer.
Terminal Driver-Under the control of the Speech
Transaction Manager, a CRT terminal/keyboard can
be connected directly to the SpeeCh Transaction
Board. The terminal can be used for visual feedback
as well as data entry/control. The interface is RS232
qompatible,
Operator Control-Two LED lights to indicate recognition status and an operator attention button are
provided. These functions are programmable under
the control of the Speech Transaction Manager.
Operator Reference Patterns-Speech patterns for
recognition are normally contained in RAM. The patterns are downloaded from the host processor under
the control of the Speech Transaction Manager. The
operator reference patterns are also generated under the control of the Speech Transaction Manager.
Speech Transaction Manager-The Speech Transaction Manager is the heart of the Speech Transaction
Board. The Speech Transaction Manager controls all
of the functions within the board. This firmware is

MICROPHONE
INPUT

AUDIO
FEEOBACK

VISUAL

I
I

---11-------1

FEEDBACK
AND KEYBOARD -.
INPUT
1

L-_ _ _....J

VISUAL LED

Figure 6. Functional Structure of the Speech Transaction Board
13-10

iSBC® 576

contained in 27128 EPROMs and is RMX®-88 (RealTime Multi-Tasking Executive) based. Processing is
provided by the 8086 processor.

Diagnostic Mode-This mode tests the hardware.
The diagnostics will test the 2920/8048 interface and
the 8048/8086 interface.

Speech Transaction File-The Speech Transaction
File determines the configuration of the board for
each application. The Speech Transaction Manager
executes this file which is normally downloaded from
ttie-host and-stored in RAM. The file can also be
stored Tn ROM/EPROM on the Speech Transaction
Board itself. These files are generated-by the Speech
Transaction Generator.

Terminal Mode-This mode provides for direct communication between the host and the Speech Transaction Board terminal. All response from the
operator (through the terminal) is passed directly to
the host. ALL host messages are passed directly to
the terminal.

,

Multibus® Interface-A slave multibus® interface is
implemented. On the multi bus the Speech Transaction Board looks like a data port.
iSBX® Interface-One SBX® interface has been implemented. This interface is controlled by the
Speech Transaction Manager. Interface with a nonMultibus® host can be implemented via this channel.

Parameter Mode-This mode lets the user define a
limited set of configuration information and to set
various other system parameters.
Evaluation Mode-This mode lets the user evaluate
the recogn ition performance of an STF vocabulary or
a vocabulary entered from the STS terminal. Use of
this mode will facilitate evaluation of training strategies, vocabulary choices and parameter settings. In
this mode statistics and automatic scoring of results
are all standard features.

OPERATIONAL DESCRIPTION

LIST OF COMMANDS

The operation of the Speech Transaction Board is
determined by the Speech Transaction Manager. The
Speech Transaction Manager has several specific
modes of operation as described below.

Monitor Mode Commands

Speech Transaction Processing Mode-This mode
enables the operator to enter by speech, or keyboard, a transaction message to a multibus or serial
host.
File Mode-This mode supports file loading from the
host through the multibus or serial interface. Loading and saving of operator reference patterns are
also handled here.

13-11

STP-enter speech transaction processing mode
FIL-enter file mode
DIA-enter diagnostic mode
TER-enter terminal mode
PAR-enter parameter mode
MaN-enter monitor mode
EVA-enter evaluation mode
HELP-list help commands
EXIT-exit current mode
INI-initialize statistics
RES-restores system status

iSBC® 576

Speech Transaction Processing
Mode Function

EXit-exit current mode
LDI-Ioad dictionary
SDI-save dictionary

Buffer Editing Functions
Diagnostic Commands
Forward
Backup
Correction
Replace
Forward Field
Backup Field

Erase Field
Continue
Beginning
Cancel
Finish

FET -front end test
EXit-exit mode
HELp-'-list help commands

Parameter Mode Commands
Utility Functions
Help-operator assistance at each field
Display-'-current transaction buffer
Next-go to next field
Detach-put terminal in "Terminal Mode"
Attach-get terminal out of "Terminal Mode"
Exit-exit STP mode
Up-raise rejection threshold
Down-lower rejection threshold
Relax-put system in not-ready.state
Ready-first of two utterances to exit not-ready
state
Attention-second of two utterances to exit notready state
Enable Transaction "N"-initiate transaction
Macro-performs a series of commands
automatically in any mode

Operator Speech Pattern
Maintenance Functions
Test Group
Test All
Retrain
Retrain Group
Retrain All
Delete
Delete All

Train
Train Group
Train All
Update
Update Group
Update All
Test

File Mode Commands
LST -load Speech Transaction File
SST-save speech transaction file
LRP-Ioad operator speech patterns
SRP-save operator speech patterns
CRP-clear operator speech pattern RAM area
HELp-list help commands
CST-clear speech transaction

BLO-block size of transfer
CHS-communication header
CON-display all configuration parameters
DIS-discrimination level
DRE-small delta rejection
EST-display extended statistics
HOS-specifies host and characteristics
HTE-host terminator string
HTO-host time-out
INS-initialize statistics
MTP-minimum training passes
RPT -operator reference pattern names
SHC-serial host baud rate
STA-displays statistics
STF-STF name
STR-ROM STF name
TST-STB terminal status
WRD-word gap and word length
FEG-front-end gain
HELp-list help commands
EXit-exit current mode

Evaluation Mode Commands
DEF-define
MVO-modify' vocabulary
RVO-remove vocabulary
RRP-remove reference pattern
RET-retrain
LIS-list vocabulary
TRAin-train
UPDate-update
TESt-test
RECognition-recognition
STA-statistics
COR-cross correlation
INS-initialize statistics
HELp-list help commands
EXit-exit current mode

ISBC® 576

SPECIFICATIONS

Physical Characteristics

Operating Environment

Width-6.75 in. (17.15 cm)
Height-0.5 in. (1. 'll cm)
Length-12.0 in. (30.48 cm)
Shipping weight-TBD
Mounting-occupies one slot of iSBC® system
chasis in cardcage/backplane. With
iSBX® Multimodule™ board mounted,
vertical height increases to 1.13 in.
(2.87 cm)

Host Processor-any iSBC® Multibus® computer
-any RS232 serial host interface
Audio Input-475!1 input impedence
-so m;v. p-p max.
-differential or single-ended

Equipment Supplied
iSBC® 576 Speech Transaction Board with Speech
Transaction Manager Firmware

Electrical Characteristics
Power Requirements'
+5V DC@3A
+10V DC @ TBD
*Multimodule™
-12V DC @ 0.02 A *Multimodule™
+12V DC@ 0.5 A

Optional Equipment
iSBX®-351
iSBX®-342
iSBC®-575

RS232 Multimodule
EPROM expansion
SBX synthesizer
Operator Control Unit

Performance Specifications

Environmental Characteristics

Recognition vocabulary....,...200 words or phrases
Utterance duration-user selectable> 100 msec.,
minimum
-user selectable < 2 sec.
maximum
Rejection Threshold-user selectable
Word gap-user selectable> 50 msec., minimum
-user selectable < 250 msec.,
maximum
Recognition Accuracy (50 state names)-99+%
Response Time (for vocabulary up to 200 words
with maximum node length 50
words) - < 500 msec.

Temperature-O to 55°C (operating): -55°C to 85°C
(non-operating)
Humidity-up to '90% relative humidity without
condensation (operating); all conditions
without condensation or frost (nonoperating)

Reference Manual
Speech Transaction Design Manual (supplied)

ORDERING INFORMATION
Part Number Description
iSBC® 576

Speech Transaction Board

13-13

iSBC® 577
SPEECH TRANSACTION RECOGNITION CHIP SET
• High-volume solution for speech 1/0

• Fully compatible with iSaC 570, 576generated software

The iSBC® 577 Speech Recognition Chip Set is a solution for your high-volume/maximum value-added speech
I/O solution. The Chip Set contains the Intel-developed proprietary components from the iSBCIII> 576 Speech
Transaction Board. With these components you can build the equivalent of the Speech Transaction Board into
your own system. The Chip Set contains the digital front-end processors, a preprogrammed 8048 interface
processor, the Speech Transaction Manager Firmware on 27128 EPROMs, and the 8086 microprocessor.

SPECIFICATIONS

Equipment Supplied

Performance

2-Preprogrammed 2920/215 (Digital Front-end
Processor)
4-Preprogrammed 27128 (Speech Transaction
Manager)
1-Preprogrammed 8048 (Interface Processor)
1-8086

-Refer to iSBCIII> 570 and iSBCIII> 576 performances.

ORDERING INFORMATION
Part Number Description
iSBCIII> 577

Speech Transaction Recognition
Chip Set

13-14

Telecommunications

14

2910A
PCM CODEC - IJ.LAW
8·BIT COMPANDED AID AND DIA CONVERTER

•

dB Dynamic Range, with Resolution
• 78
Equivalent to 12-Blt Linear Conversion

Per Channel, Single Chip Codec

Around Zero

CCITT G711 and G712 Compatible,
• ATT
T1 Compatible with 8th Bit

•

Signaling

±S% Power Supplies: +12V, +SV,
-SV

• Precision On-Chip Voltage Reference
Low Power Consumption 230 mW Typ_
• Standby
Power 33 mW Typ_
Fabricated with Reliable N-Channel
• MaS
Process

Microcomputer Interface with On-Chip
• Timeslot
Computation
• Simple Direct Mode Interface When
Fixed Timeslots are Used

The Intel. 2910A is a fully integrated PCM (Pulse Code Modulation) Codec (Coder-Decoder), fabricated with N-channel
silicon gate technology. The high density of integration allows the sample and hold circuits, the digital-to-analog
converter, the comparator and the successive approximation register to be integrated on the same chip, along with the
logic necessary to interface a full duplex PCM link and provide In-band signaling.
The primary applications are in telephone systems:
• Transmission - T1 Carrier
• Switching
- Digital PBX's and Central Office Switching Systems
• Concentration - Subscriber Carrier/Concentrators
The wide dynamic range of the 2910A (78 dB) and the minimal conversion time (80l'sec minimum) make it an ideal
product for other applications, like:
• Data Acquisition • Secure Communications Systems
• Telemetry
• Signal Processing Systems

PIN CONFIGURATION
CAP 1)(

BLOCK DIAGRAM
@SIGX_-r_ _ _ _ _ _T_RA_N_SM_IT_S_E_CT_'O_N...,A/D

~AU~;--+---ISAMPLE
r--'-----"l-+-- TS, @
CD CAP')(
H:LD 1----...,
AP~~~~~~!~~ON
~Kx ~
®CAP2 x

--t-----i

@

_-+-<

REGISTER

FS x

VF A

NC
NC

'--_ _.....r
PIN NAMES

CAP 1)(. CAP 2)(

"x

"

DR. 00 SIGx
StGR, Ox.
X
CLKc. ClKx. CLKR
FSX. FSA

AUTO

V"
V",
VDD
PDN
GRDA
GRDD
NC

Holding Capacitor
Analog Input
Analog Output
Dlgltallnput
Digital Output
Clock Input
Frame Sync Input
Auto Zero Output
Power (-511)
Power (+51J)
Power (+12V)
Power Down
Analog Ground
01 Ital Ground.
No COnnect

®

o

VF A
~GA

-+______________

__

PIN NUMBER

GRDA

GRDD

®

@

14-1

~

@

inter

2910A

PIN DESCRIPTION
Pin No. Symbol

Function

1

CAP1x

Hold

2

CAP2x

Connections for the trensmlt
holding cepacltor. Refer to Applications 1Iectlon.

3

VFx

Input

Analog Input to be encoded Into
a PCM word. The signal on this
lead Is sampled at the same rate
as the transmit frame synch.ronlzation pulse FSx, and the
sample value Is held In the external capacitor connected to
the CAP1x and CAP2x leads
until the encoding process Is
completed.

4

AUTO

Output

Description

Most significant bit of the. en·
coded PCM word (+5 V for nega·
tive. -5V for positive Inputs).
Refer to'the Codec Applications
section.

5

GRDA

Ground·

Analog return common to the
transmit .and receive analog clr·
cults. Not connected to GRDD
Internally.

6

SIGR

Output

Signaling output. SIG R is updated
with the 8th bit of the ,receive PCM
word on signaling frames. and Is
latched between two signaling
frames. TIL Interface.

7

VOl;>

Power

+12V±5%; referenced toGRDA.

8

DR

Input

Receive .PCM highway (serial
bus) Interface. The Codec serl·
ally receives a PCM word (8 bits)
through this lead at the proper
time deflned'by FSR. CLKR. De.
and CLKe.

9

PDN

Output

Active high when Codec is in the
power down state. Open drain
output.

10

VFR

Output

11

NC

No
Recommended practice Is to
Connects strap these NC's to GRDA.

Analog output. The voltage pres·
ent on VFR Is the decoded value
of the PCM word received on
lead DR. This value Is held con·
stant between two conversions.

12

NC

13

GRDD

Ground

Ground return common to the
logic power supply. Vee.

14

Ox

Output

Output of the transmit side onto
the send PCM highway (serial
bus). The 8-blt PCM word Is serio
ally sent out on this pin at the
proper time defined by FSx.
CLKx, De. and CLKe. TTL three·
state output.

Pin No. Symbol

TSx

15

Function

Description

Output

Normally high. this signal goes low
while the Codec is transmitting an
8-bit PCM word on the Ox lead.
(Timeslot information used for diagnostic purposes and also to
gate the data on the Ox lead.)
Open drain output.

16

Vee

Power

+5V ± 5%. referenced to GRDD.

17

CLKR

Input

Master receive clock defining
the bit rate on the receive PCM
highway. Typically 1.544 Mbps
for a T1 carrier system. Maxi·
mum rete 2.1 Mbps. 50% duty
cycle. TTL Interface.

18

FSR

Input

Frame synchronization pulse for
the receive PCM highway. Resets
the on-chip timeslot counter for the
receive side. Maximum repetition
rate 12 KHz. Also used to differentiate between non-signaling
frames and signaling frames on
the receive side. TTL interface.

19

CLKx

Input

Master transmit clock defining
the bit rate on the transmit PCM
highway. Typically 1.544 Mbps
for a T1 carrier system. Maxi·
mum rete 2.1 Mbps. 50% duty
cycle. TTL interface.

20

FSX

Input

Frame synchron!zf'.t!or!. PIJ!S€I for
the transmit PCM highway. Resets
the on-chip timeslot counter for the
transmit side. Maximum repetition
rate 12 KHz. Also used to differentiate between non-signaling
frames and signaling frames on
the transmit side. TTL interf.ace.

Input

Signaling input. This digital In·
put is transmitted as the 8th bit
of the PCM word on the Ox lead.
on signaling frames. TTL Interface.

21

SIGx

22

VBB

Power

-5V±5%. referenced to.GRDA.

23

De

Input

Data input to program the Codec
for the chosen mode of operation. Becomes an active low
chip select when CLKe is tied to
Vee. TTL interface.

24

CLKe

Input

Clock input to clock in the data on
the De lead when the timeslot assignment feature is used; tied to
Vee to disable this. feature. TTL
interface.

2910A
FUNCTIONAL DESCRIPTION

Typical Line Termination

The 2910A PCM Codec provides the analog-to-digital
and the dlgital-to-analog conversions necessary to Interface a full duplex (4 wires) voice telephone circuit with
the PCM highways of a time division multiplexed (TOM)
system.

I

In a typical telephone system the Codec is used between the
PCM highways and the channel filters.

I
I .---'----.

The Codec provides two major functions:

1

• Encoding and decoding of analog signals (voice and
call progress tones)

I

• Encoding and decoding of the signaling and supervision information
On a non-signaling frame, the Codec encodes the
incoming analog signal at the frame rate (FSxl into an
a-bit PCM word which is sent out on the Ox lead at the
proper time. Similarly, the Codec fetches an a-bit PCM
word from the receive highway (DR lead) and decodes an
analog value which will remain constant on lead VF R
until the next receive frame. Transmit and receive
frames are independent. They can be asynchronous
(transmisSion) or synchronous (switching) with each
other.
For channel associated signaling, the Codec transmit
side will encode the incoming analog signal as
previously described and substitute the signal present
on lead SIG x for the least significant bit of the encoded
PCM word. Similarly, on a receive signaling frame, the
Codec will decode the 7 most significant bits according
to the CCnT G733 recommendation and will output the
least significant bit value on the SIG R lead until the next
signaling frame. Signaling frames on the send and
receive sides are independent of each other, and are
selected by a double-width frame sync pulse on the
appropriate channel.

CODEC OPERATION
Codec Control
The operation of the 2910A is defined by serially loading
an a-bit word through the Dc lead (data) and the CLKc
lead (clock). The loading is asynchronous with the other
operations of the Codec, and takes place whenever transitions occur on the CLKc lead. The Dc input is loaded
in during the trailing edge of the CLKc input.

r~---------------------

PABX I C.O. SWITCHING SYSTEM /CHANNEL BA.NK

I
I
I

SUPE RV ISIaN
PROTECTION

BATTERY

FEED
RINGING

L __________________

~M~I~~VS

The 2910A Codec is intended to be used on line and
trunk terminations. The call progress tones (dial tone,
busy tone, ring-back tone, re-order tone), and the prerecorded announcements, can be sent through the
voice-path; digital signaling (off hook and disconnect
supervision, rotary dial pulses, ring control) Is sent
through the signaling path.
Circuitry is provided within the Codec to Internally
define the transmit and receive tlmeslots. In small
systems thi~ may eliminate the need for any external
timeslot exchange; In large systems it provides one
level of concentration. This feature can be bypassed and
discrete timeslots sent to each Codec within a system.
In the power-down mode, most functions of the Codec
are directly disabled to reduce power dissipation to a
minimum.
The last 6 bits of the control word define the timeslot
assignment, from 000000 (timeslot 1) to 111111 (timeslot
64). Bit 3 Is the most significant bit and bit a the least
significant bit and last into the Codec.
Bit 1 Bit 2
0
0
1
1

0
1
0
1

Mode

X&R
X
R
Standby

ClKC

Bit

DC
BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

~S~~~~T ~I~'----"::':~:i:'~
The control word contains two fields:
Bit 1 and Bit 2 define whether the subsequent 6 bits
apply to both the transmit and receive side (00), the
transmit side only (01), the receive side only (10), or
whether the Codec should go into the standby, powerdown mode (11). In the last case (11), the following 6 bits
are irrelevant.

14-3

3 4 5 6 7 8
0 0 0 0 0 0
0 0 o 0 0 1

Tlmeslot

1 1 1 1 1 1

64

··
··

1
2

··
··

The Codec will retain the control word (or words) until a
new word is loaded in or until power is lost. This feature
permits dynamic allocation of timeslots for switching
applications.

inter

2910A

Microcomputer Control Mode

c. Two frames later assign the desired receive timeslot.

In the microcomputer mode, each Codec performs Its
own timeslot computation Independently for the transmit and receive channels by counting clock pulses
(CLKx and CLKRl. All Codecs tied to the same data bus
receive Identical framing pulses (FSx and FSRl. The
framing pulses reset the on-chip tlr'neslot counters
every frame; hence the tlmeslot counters of all devices
are synchronized. Each Codec Is programmed via CLKc
and Dc for the desired transmit and receive tlmeslots
according to the description In the Codec Control
Section. All Codecs tied to the same DR bus will, In
general, have different receive tlmeslots, although that
Is ncit a device requirement There may be separate
busses for transmit and receive or all Codecs may
transmit and receive over the same bus, in which case
the transmit and receive channels must'be synchronous
(CLKx CLKR') There are no other restrictions on timeslot assignments; a device may have the same transmit
and receive tlmeslot even if a single bus is used.

4. Initialization sequence: The device contains an onchip power-on clear function 'which guarantees that
with proper sequencing of the supplies (Vee or Voo
on iast), the device will Initialize with no tlmeslot
assigned to either the transmit or receive channel.
Attera supply fallur~or whenever the supplies are
applied, It Is recommended that either power down
assignment be made first, or the first tlmeslot assignment be a transmit timeslot or a transmit/receive
timeslot. The consequence of making a receive timeslot assignment first, after supply application, is that
the transmit channel will assume timeslot 1. potentially producing bus contention.
.
5. Transmit only/receive only operatl9n'is permitted provided that a power down assignment is made first.
Otherwise. speCial circuits which use only one channel should be physically disconnected from the
unused bus; this allows a'tlmeslot to be made to an
unused channel without consequence.

=

There are several requirements for using theCLKc-De
Interface In the microcomputer mode.

6. Both frame, synchronizing pulses (FS x• FSR) must be
active at all times after power on clear (after power
supplies are turned on). This requirement must be met
during powerdown and receive cinly or transmit only
operation. as well as during normal transmit and receive
operation.

1. A complete tlmeslot assignment, consisting of eight
negative transition,s of CLKc, must be made in less
than one frame period. The assignment can overlap a
framing pulse so long as all 8 control bits are clocked
In within a total span of 125/lSec (for an 8KHz frame
rate). CLKe must be lett at a TTL low level when not
assigning a timeslot.

Example of Microcomputer Control Mode:

2. A dead period of two frames must always be Observed
between successive tlmeslot assignments. The two
frame delay is measured from the rising edge of the
first CLKe transition of the previous tlmeslot
assigned.

The two words 01000001 and 10000010 have been
loaded into ,the Codec. The transmit side is now programmed for tlmeslot 2 and the receive side for timeslot 3. The Codec will output a PCM word on the transmit PCM highway (bus) during the tlmeslot2 of the
transmit frame, and will fetch a PCM word from the
receive PCM highway during timeslot 3.

3. When the device is in the power-down state (Standby).
the following three-step sequence must be followed to
power-up the codec to avoid contention on the transmit
PCM highway.

rSEPARATEO BY AT LEAST TWO

~~

a. Assign a dummy transmit timeslot. The dummy should
be at least two timeslots greater than the maximum valid
system times lot '(usually 24 or 32). For example. in a
24 timeslot system, the dummy could be any timeslot
between 26 and 64. This will power-up the transmit side.
but prevent any spurious Ox or TSx outputs.

CLKc

XMT TIME SLOT 1

-r-

:

~~:
Dc
:, ,:
:
, ,
:------01000001~

:

10000010--_'

In this example the Codec interface to the PCM highway
then functions as shown below. (FSx and FSR may be
asynchronous.)

b. Two frames later, assign the desired transmit timeslot.

FSx IN

FRAMESl

XMT TIME SLOT 2

XMT TIME SLOT 3

Rev TIME SLOT 2

Rev TIME SLOT 3

ClK, IN

Ox

OUT

TSx OUT

I
Rev TIME SLOT 1

Fa" IN

-t: 1

elKR IN

,

DR IN

~

14-4

PCM WORD CLOCKED IN

~

2910A

Direct Control Mode
The direct mode of operation will be selected when the
CLKc pin Is strapped to the + 5 volt supply (V cd. In this
mode, the Dc pin Is an active low chip select. In other
words, when Dc Is low, the device transmits and
receives In the timeslots which follow the appropriate
framing pulses. With Dc high the device Is In the power
down state. Even though CLKc characteristics are
simpler for the 2910A It will operate properly when
plugged Into a 2910 board.
Deactivation of a channel by removal of the appropriate fram-

General Control Requirements
All. bit and frame clocks should be applied whenever the
device is active. In particular, an unused channel cannot
be deactivated by removal of Its associated frame or bit
clock while the other channel of the same device
remai ns active.

Encoding
TheVF signal to be encoded is input on the VFx lead. An
Internal switch samples the signal and the hold function
is performed by the external capaCitor connected to the
CAP1 x and CAP2 x leads. The sampling and conversion

;-

FS x

....n

Ox

TS

The Codec will enter the direct mode within three frame
times (375"sec) as measured from the time the device
power supplies settle to within the specified limits. This
assumes that CLKc is tied to Vee and that all clocks are
available at the time the supplies have settled.

A single channel cannot be deactivated except by
physical disconnection of the data lead (Ox or DRl from
the system data bus. A device (both transmit and receive
channels) may be deactivated In either control mode by
powering down the device. Both channels are always
powered down together.

is synchronized with the transmit times lot. The
word is then output on the Ox lead at the proper
slot occurrence of the following frame. The
converter saturates at approximately ± 2.2 volts
(± 3.1 volts peak).

PCM
time·
AID
RMS

-I

193XCLK x
(24 CHANNEL SYSTEM)

TIME SLOT 20

ing pulse (FS x or FS A) is not permitted. Specifically, framing
pulses must be applied for a minimum of two frames after a
change in state of Dc in order for the Dc change to be internally sensed. In particular, when entering standby in the
direct mode, framing pulses must be applied as usual for two
frames after Dc is brought high.

n

-+l I---

----- ------- --- -- -- -- -- ------- -- -- -- -- --

TIME SLOT 20

->I I+-

--0---- --- -- ---- ------------ ---------- - ---- --- ---0'- -- ---, -------- --, ------- --, ------- -- -- --'--

x------------------------,

r----~-'L-O-G-T--D-,G-,TA-L---VE-R-,~N--~~'

r-------------------------

=================~~_=~~A/D~C~D~NV~,C~Y~CL~E~========~=-~~=========C============~__~
HOLD TIME

CA"x

Decoding
The PCM word is fetched by the DR lead from the PCM
highway at the proper timeslot occurrence. The decoded
value Is held on an Internal sample and hold capacitor.

The buffered non-return to zero output signal on the VF R
lead has a dynamic range of approximately ±2.2 volts
RMS (±3.1 volts peak).

Signaling
The duration of the FS x and FS R pulses defines whether
a frame is an information frame or a signaling frame:

• A frame synchronization pulse which is two full clock
periods in duration (two CLKx periods for FSx, two
CLKR periods for FSRl deSignates a signaling frame.

• A frame synchronization pulse which is a full clock
period in duration (CLKx period for FSx, CLKR period
for FSRl designates a non·slgnallng frame.

On the encoding side, when the FSx pulse is widened,
the 8th bit of the PCM word will be replaced by the value
on the SIG x input at the time when the 8th bit Is output
on the Ox lead.

14-5

2910A

1*

TSI.

•

1 I"

TSn.

•

1

192

i

TSI •

I", ,

·1

TSn,

CLKx~,~,.Jl.SLfilJ'~

D192

Ox

._-- ------------- - - --------!-~::::::--S------------~---Gw£Xill~~~'fJ:I.BI1~

:G'

'

'
,S"
,--.r-L, __-j.I
_ _ _ _ _ _ _-...,-_ _

FSX

, 8n-7

,

XMIT SIGNAL FRAME

----~------------- -----~-++--------------~:---v-:==+=====:J:):===

X ._- - - - - - - - - - - - - - - - _ - - -

_nn_

u

On the decoding side, when the FSR pulse Is widened,
the 8th bit of the PCM word Is detected and transmitted
on the SIG R lead. That output is latched until the next
receiving signaling frame.

I-

TS1 R

-[

-

u

-s- - - " ' - - -..

-1- -

I·

TSnR

The remaining 7 bits are decoded according to the value
given In the CCITI G733 recommendation. The SIG R
lead is reset to a TIL low level whenever the Codec Is In
the power-down state.
•

I

192

r

TS1R

I•

TSnR

'

•

I

CLKR~'~'.Jl.SLfilJ'~
192
REC. SIGNAL FRAME
JI
;~; _______-,--~___

FSR

T1 Framing
The Codecwill accept the standard 03/04 framing
format of 193 clock pulses per frame (equivalent to

Standby Mode -

Power Down

To minimize power consumption and heat dissipation a
st~iidby iiiOGe' is pivviciiiu Wile-I€: ali COUttG functions are
disabled except for De and CLKe leads. These allow the
Codec to be reactivated. In the microcomputer mode the
Codec is placed into standby by loading a control word
(Dc) with a "1" in bits 1 and 2 locations. In the direct
mode when Dc Is brought high, the all "1's" control
word is internally transferred to the control register;

Power·On Clear
Whether the device Is used In the direct or microcomputer mode, an internal reset (power·on clear) Is
generated, forcing the' device Into the power down state,
when power is supplied by any of the following
methods. (1) Device power supplies ar~ turned on in a
system power·up situation where either Vee or VDD Is
applied last. (2) A large supply transient causes either of
the two positive supplies to drop to less than approximately 2 volts. (3) A board containing Codecs Is plugged
Into a "hot" system where Vee or VDD Is the last contact

Precision Voltage Reference for the
D/A Converter
The voltage reference Is generated on the chip and Is
calibrated during the manufacturing process. The
technique uses the difference in sub-surface charge
density between two suitably implanted MOS devices to
derive a temperature stable and bias stable reference
voltage.

14-6

CLKx, CLKR of 1.544Mb/sec). However, the 193rd bit
may be blanked (equivalent to CLKx, CLKR of
1.536 Mb/sec) if desired.

invoking the standby condition.
\A!h!!e in tho :;tQiidby meGg, the Dx oUlpul is illitiveiy
held in a high Impedance state to guarantee that the
PCM bus will not be driven. The SIG R output Is held low
to provide a known condition and remains this way upon
activation until It is changed by signaling.
The power consumption in the standby mode is typically
33mW.

made. It may be necessary to trim back the edge
connector pins or fingers on Vee or V DD relative to the
other supply to guarantee that the power-on clear will
operate properly when a board Is plugged into a "hot"
system. Furthermore, the Codec will inhibit activity on
TSx and Ox during the application of power supplies.
The device Is also tolerant of transients in the negative
supply (Vee) so long as Vee remains more negative than
-3.5 volts. Vee transients which exceed' this level
should be detected and followed by a system relnitlalIzatlon.

A gain setting op amp, programmed during manufacturing, "trims" the reference voltage source to the final
precision voltage reference value provided to the D/A
converter. The precision voltage reference determines
the Initial gain and dynamic range. characteristics
described in the A.C·. Transmission Specification
section.

2910A

wLaw Conversion.

COOEC TRANSFER CHARACTERISTIC

I'-Iaw represents a particular implementation of a piecewise linear approximation to a logarithmic compression
curve which is:
F(x) =Sgn(x) In(1 + I' lx ll , 0"" Ixl'" 1
. In(1 +1')
where

x = input signal
Sgn(x) = sign of input signal
I' =255 (defined by AT& 1)

The 2910A 1'= 255 law Codec uses a 15 segment approxImation to the logarithmic law. Each segment consists
of 16 steps. In adjacent segments the step sizes are In a
ratio of two to one. Within each segment the step size is
constant except for the first step of the first segment of
the encoder, as indicated In the attached table. The
output levels are midway between the corresponding
decision levels. The output levels Yn are related to the
input levels xn by the expression:

Yo = Xo = 0 for n = 0
These relationships are implicit in the attached table.

14-7

During signaling frames, a 7-bit transfer characteristic
Is Implemented in the decoder. This characteristic Is
derived from the decoder values in the attached table by
assuming a value of "1 "for the LSB (8th bit) and shifting
the decoder transfer characteristic one half-step away
from the origin. For example, the maximum decoder
output level for signaling frames has normalized value
7903, whereas it has value 8031 in normal (nonsignaling) frames.

2910A
Theoretical wLaw - Positive Input Values (for Negative Input Values, Invert Bit 1)
1
Segment
Number

2

3

No. of Steps
x Step Size

Value
at Segment
End
Points

Decision
Value
Number n

Decision
Value xn'

8159'

(128)

(8159)

127
I
I
I
I
113

7903
I
I
I
I
4319

112
I
I
I
I
97

4063
I
I
I
I
2143

4

PCM Word'
Bit Number LSB
12345678

MSB

------10000000

8

16 x 256

7

16x 128

6

16x 64

,

96
I
I
I
I
81

2015
I
I
I
I
1055

80
I
I
I
I
65

991
I
I
I
I
511

:
:

o0

0 1 1 1 1

5

16x 32

o0

i
1 1 1 1 1

4

i6x i6

64
I
!
I
I
49

479
I
!
I
I
239

3

16x8

48
I
I
I
I
33

223
I
I
I
I
103

32
I
I
I
I
17

95
I
I
I
I
35

2

16x4

15x2

16
I
I
I
I
2

31
I
I
I
I
3

t

0

I

:
i

o0

1 1 1 1

:

r-

l

(see Note 2)

I
I

c-

I

(see Note 2)

I

r-

I

(see Note 2)

1

1

1x 1

;-

(see Note 2)

1 1 1 1 1 1 1 0

1
1

0

:

1 1 1 0 1 1 1 1
31

-

(see Note 2)

1 1 0 1 1 1 1 1
95

I
I
I
48
I
I
I
I
I
I
32
I
I
I
I
I
I
16
I
I
I
I
I
I
1

-

i
I

1 1
223

I
I
I
231
I
I
I
I
I
I
99
I
I
I
I
I
I
33
I
I
I
I
I
I
2

-

(see Note 2)

1 0 1 11 1 1 1
479

127
I
I
I
I
I
I
112
I
I
I
I
I
I
96
I
I
I
I
I
I
80
I
I
I
I
I
I
64
I
I

I

1 0 1 0 1 1 1 1
991

8031
I
I
I
I
I
I
4191
I
I
I
I
I
I
2079
I
I
I
I
I
I
1023
I
I
I
I
I
I
495
I
I

-

(see Note 2)

1
2015

8
Decoder
Output
Value
Number

(see Note 2)

1
4063

7
Normalized
Value
at Decoder
Output Yn'

6

5

c-

:

1 1 1 1 1 1 1 1
0

0

Notes:
1. 8159 normalized value units correspond to the value of the on·chlp voltage reference.
2. The PCM word corresponding to positive input values between two successive decision values numbered nand n + 1 (see column 4)
Is (255 - n) expressed as a binary number.
'
3. The PCM word on the highways is the same as the one shown In column 6.
4, The voltage output on the VFR lead Is equal to the normalized value given in the table, augmented by an offset. The offset value Is
approximately 15 mV.
5. x128 is a virtual decision value.

14-8

intel'

2910A

APPLICATIONS
Circuit Interface Without External Auto Zero

Circuit Interface With External Auto Zero

r--VFx

I

R,
150 KG
~--'VVIr---1 AUTO

R,

R2
3300

I
I

470 KG

I

":'" GRDA

VF.

I

I
I

2 mV OFFSET

L_~~;

I
I

L __ _

\

_________ J

Holding Capacitor
For an 8 KHz sampling system the transmit holding
capacitor CAPx should be 2000pF± 20%.

Auto Zero
The 2910A contains a transparent on·chip auto zero plus
a device pin for implementing a sign·bit driven external
auto zero feedback loop. Theon·chip auto zero reduces
the input offset voltage of the encoder (VFx) to less than
3 mY. For most telephony applications, this input offset
is perfectly acceptable, since it insures the encoder is
biased in the lower 25% of the first segment.
Where lower input offset is required the external auto zero
loop may be used to bias the encoder exactly at the zero
crossing point. The consequence of the external auto zero
loop, aside from extra components, is the addition of the
dithering auto·zero signal to the input signal, resulting in
slightly higher idle channel noise (approximately 2dB) than
when the external loop is not used. Consequently, where the
application permits, it is recommended that the external auto
zero loop not be used .. When not used, the AUTO pin should
float.

14-9

The circuit interface with auto zero drawing shows a
possible connection between the VFx and AUTO leads
with the recommended values of C 1 0.3j.tF, R1
= 150KQ, R2 = 330Q, and R3= 470KQ.

=

Filters Interface
The filters may be interfaced as shown in the circuit
interface diagrams. Note that the output pulse stream is
of the non·return·to·zero type and hence requires the
(sin x)/x correction provided by the 2912A filter.

Ox Buffering
For higher drive capability or increased system reli·
ability it may be desirable that the Dx output of a group
of Codecs be buffered from the system PCM bus with an
external three·state or open collector buffers. A buffer
can be enabled with the appropriate Codec generated
TS x signal or signals. TS x signal may also be used to
activate external zero code suppression logic, since the
occurrence of an active state of any TSx implies the
existence of PCM voice bits (as opposed to transparent
data bits) on the bus.

inter

2910A

Absolute Maximum Ratings·
Temperature Under Bias ............ -10'C to +80'C
Storage Temperature .............. -65'C to +150'C
All Input or Output Voltages with
Respect to Vee ................... -0.3V to +20V
Vcc, Voo, GRDD, and GRDA with Respect
to Vee .......................... - 0.3V to + 20V
Power Dissipation ........................... 1.35W

*NOTlCE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

D.C. Characteristics
TA=O'C to +70'C, Voo=+12V±5%, Vcc=+5V±5%, Ves=-5V±5%, GRDA=OV, GRDD=OV, unless otherwise specified.
Symbol

Parameter

Test Conditions

DIGITAL INTERFACE
IlL

Low Level Input Current

10

~

VIN < VIL

IIH

High Level Input Current

10

".A

VIN

VIL

Input Low Voltage

0.6

V

VIH

input High Voltage

VOL

Output Low Voltage

VOH

Output High Voltage

2.0

> VIH

V
0.4

2.4

-

V

V

OX, 10L = 4.0 mA
SiGR, 10L = 0.5 mA
fSx, 10L = 3.2 mA, open drain
PON, 10L = 1.6 mA, open drain
OX,IOH=15mA

ISIGR, 10H = 0.08 mA

ANALOG INTERFACE
ZAI

Input Impedance when Sampling, VFx

125

300

500

Q

in series with CAPx to GROA,
-3.1V< VIN < 3.1V

ZAO

Small Signal Output Impedance, VFR

100

180

300

Q

-3.1 V < VOUT < 3.1 V

VOR

Output Offset Voltage at VFR

±50

mV

all "1 s" code sent to DR

VIX

Input Offset Voltage at VFx

±5

mV

VFx voltage required to
produce all "1s" code at Ox

VOL

Output Low Voltage at AUTO

VOH

Output High Voltage at AUTO

Ves
(Vcc- 2)

(Vee+ 2)

Vcc

V

400 KQ to GROA

V

400 KQ to GROA

POWER DISSIPATION
1000

Standby Current

Icco

Standby Current

.

0.7

1.1

mA

4

7.0

mA

leeo

Standby Current

1

2.5

mA

1001

Operating Current

11

16

mA

Icci

Operating Current

13

21

mA

leel

Operating Current

4

6.0

mA

Notes:

1. Typical values are for TA= 25'C and nominal power supply values.

14-10

Auto Output = Open
clock frequency = 2.048 MHz

2910A

A.C. Characteristics
TA=O'C to +70'C, Voo=+12V±5%, Vcc=+5V±5%, Vee=-5V±5%, GRDA=OV, GRDD=OV, unless otherwise specified.

Parameter

Symbol

Test Conditions

TRANSMISSION
SID

Signal/tone distortion ratio,
C-Message weighted
Half channel
(See Figure 1)

36
30
27

dB
dB
dB

VFx = 1.02 KHz, sinusoid
-30 dBmO';;; VFx';;; 0 dBmO
-40 dBmO ,;;; VFx < -30 dBmO
-45 dBmO';;; VFx < -40 dBmO

dB
dB
dB

VFx = 1.02 KHz, sinusoid
-37 dBmO';;; VFx';;; +3dBmO
-50 dBmO';;; VFx < -37 dBmO
-55 dBmO';;; VFx < -50 dBmO

llG
Gain tracking deviation
Half channel'
Reference level 0 dBmO

±.25
±.60
±1.5

±.30
±.70
±1.8

llGv

llG Variation with supplies
Half channel

±.0002 ±.0004
±.0004 1:.0008

dB/mY
dB/mY

-37 dBmO';;; VFx';;; +3 dBmO
-50 dBmO';;; VFx < -37 dBmO

llGT

6G Variation with temperature
Half channel

±.001
±.002

±.002
±.005

dB/oC
dB/oC

-37 dBmO';;; 'ilFx';;; '+3 dBmO
-50 dBmO';;; VFx < -37 dBmO

N,cl

Idle channel noise, C-Message
weighted

2

7

dBrncO

no signal ing'

N'C2

Idle channel noise, C-Message
weighted
Idle channel noise, C-Message
weighted

10

i3

dBrncO

with 6th and 12th frame
signaling'

14

18

dBrncO

with 1KHz sign bit toggle

HD

Harmonic distortion (2nd or 3rd)

-48

-44

dB

IMD

Intermodulation distortion
2nd Order
3rd Order

-45
-55

dB
dB

N'C3

VFx = 1.02 KHz, 0 dBmO;
measured at decoder output
VFR
4-tone stimulus in
accordance with BSTR
PUB 41009

36

/,-'"

~----------------

AT&T 03 CHANNEL
BANK COMPATIBILITY
SPECIFICATION
(ISSUE 3·10·77)

30 / /
,/

of'

33

,/

/
27

22

" ' - . "I'------~.'

AT&T
03 CHANNEL BANK
COMPATIBILITY
SPECIFICATION
(ISSUE 3 1(077)
END·TO·END

20

-1

10

-2
-45

-40

-30

-20

INPUT

~------5~5-----+50----_-37~1:::::::::::::1+3~~~~

-10

INPUT lEVEL (dBmO)

Figure 2. Gain Tracking Deviation (6 G)
(Half·Channel)

Figure 1. SignalfTotal Distortion Ratio
(Half·Channel)

14-11

intJ

2910A

A.C. Characteristics '(co~tinued)
TA=O·C to +70·C, VDD=+12V±5%, Vcc=+5V±5%, VBB=-5V±5%, GRDA=OV, GRDD=OV, unless otherwise specified.
Symbol

. Test Conditions

Parameter

GAIN AND DYNAMIC RANGE

DmW

Digital Milliwatt Response

5.53

DmWT DmWo Variation with Temperature

5.63

5.73

dBm

-0.001

-0.002

dB/·C

relative to 23 ·C·

±0.07

dB

supplies :1:5%·

2.23

VRMS

DmWs DniWo Variation with Supplies
AIR

Input Dynamic Range

2.17

AIRT

Input Dynamic Range with
Temperature

-0.5

mVRMs"C

AIRS

Input Dynamic Range with Supplies

:1:18

mVRMS

AOR

Output Dynamic Range, VFR

2.19

VRMS

AORT

AOR Variation with Temperature

-0.5

mVRMs'~C

:1:18

mVRMS

2.13

2.20

2.16 '

AORS . AOR Variation with Supplies

23'C, nominal supplies·

uSin8 D.C. and A.C. tests'
23° • nominal supplies
relative to 23'C
supplies :1:5%
23'C, nOminal supplies
relative to 23'C
supplies :1:5%

SUPPLY REJECTION AND CROSSTALK

PSRR1 VDD Power Supply Rejection Ratio

45

dB

decoder alone s

PSRR2 VBB Power Supply Rejection Ratio

35

dB

PSRR3 Vcc Power Supply Rejection Ratio

50

dB

decoder alones
decoder alones

PSRR~ Voo P"w~!" St~PP'Y R~!E!JlJti"r!

R-!I.tio

51)

dB

~mlJocjer alone!

PSRR5 VBB Power Supply Rejection Ratio

45

dB

encoder alone7

PSRRs Vcc Power Supply Rejection Ratio

50

dB

encoder alone7

CTR

Crosstalk Isolation, Receive Side

75

80

dB

see Note 8

CTT

Crosstalk Isolation, Transmit Side

75

80

dB

see Note 9

1600

2000

CAPX Input Sample and Hold Capacitor

2400

pF

Not••:

1. Typical values are for TA = 25·C and nominal power supply values,
2. Measured In one direction, either decoder or encoder and an Ideal device, at 23°C, nominal supplies.

3,
4.

5,
6.

7.
8.
9.

the external auto-zero is used NIC1 has a typical value of 8 dBrncO and NIC2 has a typicel value of 13 dBrncO.
DR of Device Under Test (D,U,T,) driven with repetitive digital word sequence specified in CCITT recommendation. G,711, Measurement made at VF R
output.
With the D,C. method the positive and negative clipping levels are measured and AIR Is calculated. With the A.C, method a sinusoidal input signal to
VFx is used where AIR Is measured directly,
D,U,T, decoder, Impose 200 mVp,p, 1,02 KHz on appropriate supply; measurement made at decoder output; decoder In idle channel conditions,
D,U,T, encoder, impose 200 mVp.p, 1,02 KHz on appropriate supply; measurement made at encoder output; encoder in idle channel conditions,
VFx of D,U,T,. encoder = 1,02 KHz, 0 dBmO, Decoder under quiet channel conditions; measurement made at'decoder output.
VFx = 0 Vrms, Decoder= 1,02 KHz, 0 dBmO. Encoder under quiet channel conditions; measurement made at encoder output.

If

14-12

intel'

2910A

A.C. Characteristics -

Timing Specification (1)

TA=O'C to +70'C, Voo=+12V±5%, Vcc=+5V±5%, VBB=-5V±5%, GRDA=OV, GRDD=OV, unless otherwise specified.

Symbol

Parameter

Comments

CLOCK SECTION
tCY

Clock Period

t r, tf

Clock Rise and Fall Time

tClK

Clock Pulse Width

tcoc

Clock Duty Cycle (tClK + tCY)

485
0

30

215
45

55

ns

CLKx, CLKA (2.048 MHz systems), CLKc

ns

CLKx, CLKA, CLKc

ns

CLKx, CLKA, CLKc

%

CLKx, CLKA

TRANSMIT SECTION
tVFX

Analog Input Conversion

20

tlmeslot

from leading edge of transmit timeslot2

tozx

Data Enabled on TS Entry

50

180

ns

0< ClOAO < 100pF

tOHX

Data Hold Time

80

230

ns

0< ClOAO < 100pF

tHZX

Data Float on TS Exit

75

245

ns

CLOAO=O

tSON

Timeslot

X to Enable

30

220

ns

0< ClOAO < 100pF

tSOFF

Timeslot

X to Disable

70

225

ns

ClOAO=O

tss

Signal Setup Time

ns

relative to bit 7 falling edge

tSH

Signal Hold Time

100

ns

relative to bit 8 falling edge

tFso

Frame Sync Delay

15

150

ns

91/16

91/16

timeslot

0

RECEIVE AND CONTROL SECTIONS
tVFA

Analog Output Update

tOSA

Receive Data Setup

20

ns

tOHA

Receive Data Hold

60

ns

tSIGA

SIGA Update

tFSO

Frame Sync Delay

tosc

Control Data Setup

tOHc

Control Data Hold

1
15

150

JAs

from leading edge of the channel timeslot

from trailing edge of the channel timeslot

ns

115

ns

Microcomputer mode only

115

ns

Microcomputer mode only

Notes:
1. All timing parameters referenced to 1.5V, except tHZX and tSOFF which reference to high impedance state.
2. The 20 timeslot minimum insures that the complete AID conversion will take place under any combination of receive interrupt or asynchronous
operation of the Codec. If the transmit channel only is operated, the AID conversion can be completed in a minimum of 11 timeslots. Refer
to the Codec Control General Requirement section for instructions on setting a channel in an idle condition.

14-13

intJ

2910A

TIMING WAVEFORMS(1)
TRANSMIT TIMING

"FSX
NON·SIGNAlING
FRAMES
FS,

J '".

---------

SIGNALiNG
FRAMES

SIGx

DON'TeARE

------------------~----------------RECEIVE TIMING

i

I....' ..n

NON'SIGNAL~:~J
-I 1-'''.
FSRJ
.

S'G~Ai~~~

' t'fS.

J_.
::j

_______

FRAMES

'--------____-,_____________________

CONTROL TIMING

Notes: 1. All timing parameters referenced to 1.5V, except tHZX and tSOFF which reference a high Impedance state.

14-14

2911A·1
PCM CODEC - A LAW
8·BIT COMPANDED AID AND DIA CONVERTER
• Per Channel, Single Chip Codec

• 66 dB Dynamic Range, with Resolution
Equivalent to 11-Bit Linear Conversion
Around Zero
• ±S% Power Supplies: +12V, +SV, -SV
• Precision On-Chip Voltage Reference
• Low Power Consumption 230 mW Typ.
Standby Power 33 mW Typ.
• Fabricated with Reliable N-Channel
MOS Process

• CCITI G711 and G732 Compatible,
Even Order Bits Inversion Included
• Microcomputer Interface with
On-Chip Time·Slot Computation
• Simple Direct Mode Interface When
Fixed Timeslots Are Used

The Intel@ 2911A is a fully integrated PCM (Pulse Code Modulation) Codec (Coder-Decoder), fabricated with N-channel
silicon gate technology_ The high density of integration allows the sample and hold circuits, the digital-to-analog
converter, the comparator and the successive approximation register to be integrated on the same chip, along with the
logic necessary to interface a full duplex PCM link_
'
The primary applications are in telephone systems:
• Transmission - 30/32 Channel Systems at 2.048 M bps
• Switching
- Digital PBX's and Central Office Switching Systems
• Concentration - Subscriber Carrier/Concentrators
The wide dynamic range of the 2911A (66dB) and the minimal conversion time (80"sec minimum) make it an ideal
product for other applications, like:
• Data Acquisition
• Telemetry

• Secure Communications Systems
• Signal Processing Systems

PIN CONFIGURATION
CAP1X

1

BLOCK DIAGRAM
TRANSMIT SECTION AID

CLKc

,-----._+-_

CAP2x
VFx

v••

AUTO

FSx

GRDA

ClKx

VDD
D.

FS.
ClK.

7

PDN

vee

VF.
NC

TSx

CD

VFx

@AUTO

(DCAP 'x

SAMPLE

AP~~~~~~~~;ON

&

HOLD

L.--,___.....-1-rREGISTER

®CAP2 x

T5 x

1--1--- Ox

(j])
@

I---I-_CLK,@
FSx

@

Ox
GRDD

I-'-I--I-_Oc
1---I--CLKc

PIN NAMES
CAP

'x.

CAP 2x
VFx
VF

DR. Dc
Ox. TSX

CLKC. CLKx. CLKR
F5x. FSR
AUTO

V"
Vee
VDD
PON
GRDA
GRDD
NC

@

@

L-,-...-J-t-- PDN ®

HoldlngCapacllor
Analog Input
Analog Output

I-'-I--I--DR CD

Digital Input
OigitalOutpul

I---I-_CLKR@

Clock Input
Frame Sync Input

AutoZefoOut ut
Power (-5V)
Power (+5V)
Power(+12V)
Power Down
Analog Ground
Digital Ground
NoConnecl

1 - - - I - _ F5R

a/A

OPlNM.>\1BER

14-15

@

2911A·1
PIN DESCRIPTION
Pin No. Symbol

Function

1

Hold

Connections for the transmit
holding capacitor. Refer to Applications section.

Input

Analog Input to be encoded Into
a PCM word. The signal on this
lead is sampled at the same rate
as the transmit frame synch·
ronlzatlon pulse FSx, and the
sample value Is held In the ex·
ternal capacitor connected to
the CAP1x and CAP2x leads
until the encoding process Is
completed.

CAP1X

2

CAP2x

3

VFx

4

AUTO

Output

Description

Pin No. Symbol
14

Most significant bit of the en·
coded PCM word (+ 5 V for nega·
tive, -5V for positive values).
Refer to the Codec Applications
section.

5

GRDA

Ground

Analog return common to the
transmit and receive analog clr·
cuits. Not connected to GRDD
internally.

6

Voo

Power

+12V±5%; referenced toGRDA.

7

DR

Input

Receive PCM highway (serial
bus) interface. The Codec serio
ally receives a PCM word (8 bits)
through this lead at the proper
time defined by FSR, CLKR, De,
and CLKe.

8

PDN

Output

iSx

Function

Description

Output

Normally high, this signal goes low
while the Codec is transmitting an
8-bit PCM word on the Dx lead.
(Timeslot information used for diagnostic purposes and also to
gate the data on the Dx lead.)
Open drain output.

15

Vee

Power

+5V±5%, referenced to GRDD.

16

CLKR

Input

Master receive clock defining
the bit rate on the receive PCM
highway. Typically 2.048 Mbps
for a carrier system. Maximum
rate 2.1 Mbps. 50% duty cycle.
TIL compatible.

17

FSR

Input

Frame synchronization pulse
for the receive PCM highway.
Resets the on·chlp times lot
counter for the receive side.
Maximum repetition rate 12KHz.
TIL Interface.

18

CLKx

Input

Master transmit clock defining
the bit rate on the transmit PCM
highway. Typically 2.048 Mbps
for a carrier system. Maximum
rate 2.1 Mbps. 50% duty cycle.
TIL Interface.

Input

Frame synchronization pulse
for the transmit PCM highway.
Resets the on·chip tlmeslot
cOllnt~r fnr th~ tr~msm!t s!de .
Maximum repetition rate 12 KHz.
TIL interface.

19

. FSx

Active high when the Codec is in
...... _ _ _ ••• __ ...J_ •• __

Lilt:;

..,unO'.

UUYVII

_

~_L_

~1i::tLt:::l.

-.

uptm

••

UftUn

output.
9

VFR

Output

Analog Output. The voltage
present on VF R is the decoded
value of the PCM word received
on lead DR. This value is held
constant between two conver·
slons.

10

NC

11

NC

No
Recommended practice Is to
Connects strap these NC's to GRDA.

12

GRDD

Ground

Ground return common to the
logic power supply; Vee.

13

Dx

Output

Output of the transmit side onto
the send PCM highway (serial
bus). The 8·blt PCM word Is serl·
ally sent out on this pin at the
proper time defined by FSx,
CLKx, De, and CLKe. TIL three·
state output.

14-16

20

Vee

Power

-5V ± 5%, referenced to GRDA.

21

De

Input

Data Input to program the Codec
for the chosen mode of operation. Becomes im active low
chip select when CLKe Is tied to
Vee. TIL Interface.

22

CLKe

Input

Clock Input to clock In the data
on the De lead when the time·
slot assignment feature Is used;
tied to Vee to disable this fea·
ture. TIL Interface.

intel'

2911A·1

FUNCTIONAL DESCRIPTION

Typical Line Termination

The 2911A PCM Codec provides the analog-to-dlgltal
and the digital-to-analog conversions necessary to Interface a full duplex (4 wires) voice telephone circuit with
the PCM highways of a time division multiplexed (TOM)
system_ The Codec Is Intended to be used on line and
trunk terminations.

r---------------------I
I

I
I

The Codec encodes the Incoming analog signal at the
frame rate (FSx) Into an 8-blt PCM word which Is sent
out on the Ox lead at the proper time. Similarly, on the
receive link, the Codec fetches an 8-blt PCM word from
the receive highway (DR lead) and decodes an analog
value which will remain constant on lead VFR until the
next receive frame. Transmit and receive frames are
independent. They can be asynchronous (transmission)
or synchronous (switching) with each other.

FEED

discrete tlmeslots sent to each Codec within a system.
In the power-down mode, most functions of the Codec
are directly disabled to reduce power dissipation to a
minimum.

The last 6 bits of the control word define the timeslot
assignment, from 000000 (timeslot 1) to 111111 (timeslot
64). Bit 3 is the most significant bit and bit 8 the least
significant bit and last into the Codec.

The operation of the 2911A is defined by serially loading
an 8-bit word through the Dc lead (data) and the CLKc
lead (clock). The loading is asynchronous with the other
operations of the Codec, and takes place whenever transitions occur on the CLKc lead. The Dc input is loaded
in during the trailing edge of the CLKc input.

I
L
I

II

.SELECT __
MODE

6114

BIT5

BIT6

x. R

ASSIGN
TIME SLOT:

ox.

BIT7

BI11 BI12
0
0
1
1

0
1
0
1

BII
3 4 5 6 7 8
0 0 o 0 0 0
0 0 0 0 0 1

BITS
•

CONTROL HIGHWAYS
OFF·HOOK! ROTARY DIAL PULSES

I
I RINGING
I
I _____________________ _
L

CODEC OPERATION
Codec Control

6113

TRANSMISSION

BATTERY

Circuitry is provided within the Codec to Internally
define the transmit and receive timeslots. In small
systems this may eliminate the need for any external
timeslot exchange; in large systems It provides one
level of concentration. This feature can be bypassed and

6112

CHANNel BANK

HIGHWAVS

I
I...--..L--,
I SUPERVISION
I PROTECTION
I

In a typical telephone system the Codec Is located
between the PCM highways and the channel filters.

Blrl

PABX C.O. SWITCHING SYSTEM

I

I

·
··

OR

"

The control word contains two fields:
Bit 1 and Bit 2 define whether the subsequent 6 bits
apply to both the transmit and receive side (00), the
transmit side only (01), the receive side only (10), or
whether the Codec should go Into the standby, powerdown mode (11). In the last case (11), the following 6 bits
are irrelevant.

1 1 1 1 1 1

Mode
X&R
X
R
Standby

Tlme-Slol

1
2

··
··

64

The Codec will retain the control word (or words) until a
new word Is loaded In or un~1I power Is lost. This feature
permits dynamic allocation of tlmeslots for switching
applications.

Microcomputer Control Mode
In the microcomputer mode, each Codec performs Its
own timeslot computation Independently for the transmit and receive channels by counting clock pulses,
(CLKx and CLKRl. All Codecs tied to the same data bus

receive Identical framing pulses (FSx and FSRl. The
framing pulses reset the on-chip tlmeslot counters
every frame; hence the tlmeslot counters of all devices
are synchronized. Each Cod~c Is programmed via CLKc

14-17

intJ

2911A.1
4. Initialization sequence: The device contains an on-chip
power-on clear function which guarantees that with
proper sequencing of the supplies (VCC orVDD on last),
the device will initialize with no timeslot assigned to
either the transmit or receive channel. After a supply
failure or whenever the supplies are applied, it is recommended that either power down assignment be made
first, orthe first limeslot assignment be a transmit timeslot or a transmit/receive timeslo!. The consequence of
making a receive timeslot assignment first, after supply
application, is that the transmit channel will assume
timeslot 1, potentially producing bus contention.
5. Transmit only/receive only operation is permitted provided that a power down assignment is made firs!. Otherwise, speCial circuits which use only one channel should
be physically disconnected from the unused bus; this
allows a timeslot to be made to an unused channel without consequence.
6. Both frame synchronizing pulses (FS x , FSR) must be
active at all times after power on clear (after power
supplies are turned on). This requirement must be met
during powerdown and receive only or transmit only
operation, as well as during normal transmitand receive
operation.
Example of Microcomputer Control Mode:

and Dc for the desired transmit and receive tlmeslots
according to the description In the Codec Control
Section. All Codecs tied to the same DR bus will, in
general, have different receive timeslots, although that
is not a device requirement. There may be separate
busses for transmit and receive or all Codecs may
transmit and receive over the same bus, in which case
the transmit and receive channels must be synchronous
(CLKx =CLKRl. There are no other restrictions on tlmeslot assignments; a device may have the same transmit
and receive limes lot even If a single bus is used.
There are several requirements for using the CLKc-Dc
interface in the microcomputer mode.
1. A complete timeslot assignment, consisting of eight
negative transitions of CLKc, must be made in less
than one frame period. The assignment can overlap a
framing pulse so long as all 8 control bits are clocked
in within a total span of 125"sec (for an 8 KHz frame
rate). CLKc must be left at a TTL low level when not
assigning a times lot.
2. A dead period of two frames must always be observed
between successive timeslot assignments. The two
frame delay is measured from the rising edge of the
first CLKc transition of the previous times lot
assigned.

The two words 01000001 and 10000010 have been
loaded into the Codec. The transmit side is now programmed for timeslot2 and the receive side for timeslot
3. The Codec will output a PCM word on the transmit
PCM highway (bus) during the timeslot2 of the transmit
frame, and will fetch a PCM word from the receive PCM
highway during timeslot 3.

3. When the device is in the power-down state (Standby),
the following three-step sequence must be followed to
power-up the codec to avoid contention on the transmit
PCM highway.

rSEPARATED BY AT LEAST TWO FRAMES1

a. Assign a dummy transmit timeslol. The dummy should
be at least two timeslots greater than the maximum valid
system times lot (usually 24 or 32). For example, in a
24 timeslot system, the dummy could be any timeslot
between 26 and 64. This will power-up the transmit side,
but prevent any spurious Ox or TSx outputs.

~~
CLKc

~~:
Dc

,

I

'

I

:-------10000010---_'

I n this example the Codec interface to the PCM highway
then functions as shown below. (FSx and FSR may be
asynchronous.)

c. Two frames later assign the desired receive timeslol.

-I--

I

:----0100000'-----i

b. Two frames later, assign the desired transmit timeslol.

XMT TIME SLOT 1

;

XMT TIME SLOT 2

XMT TIME SLOT 3

: 1

FSx IN
ClK. IN

Ox OUT
TS. OUT
Rev TIME SLOT 1

F80

Rev TIME SLOT 3

-j
7

IN

8:

ClKR IN

I

DR IN

PCM WORD CLOCKED IN

Direct Control Mode
The direct mode of operation will be selected when the
CLKc pin is strapped to the +5 volt supply (Vcel. In this
mode, the Dc pin is an active low chip select. In other
words, when Dc Is low, the device transmits and
receives in the timeslots which follow the appropriate

14-18

,,

-l

framing pulses. With Dc high the device is In the power
down state. Even though CLKc characteristics are
simpler for the 2911A It will operate properly when
plugged into a 2911 board.
Deactivation of a channel by removal of the appropriate
framing pulse (FS x or FSRl is not permitted.

2911A·1

Specifically, framing pulses must be applied for a minimum
of two frames after a change In state of Dc In order for the
Dc change to be internally sensed. In particular, when entering standby In the direct mode, framing pulses must be
applied as usual for two frames after Dc Is brought high.

General Control Requirements
All bit and frame clocks should be applied whenever the
device Is active. In particular, an unused channel cannot
be deactivated by removal of Its associated frame or bit
clock while the other channel of the same device
remains active.

Encoding

---256X ClK, ---

TIME SLOT 20

D,

__---I ____
~nL

-I I--

~

A single channel cannot be deactivated except by
physical disconnection of the data lead (Dx or DR> from
the system data bus. A device (both transmit and receive
channels) may be deactivated In either control mode by
powering down the device. Both channels are always
powered down together.

is synchronized with the transmit tlmeslol. The
word Is then output on the Dx lead at the proper
slot occurrence of the following frame. The
converter saturates at approximately ±2.2 volts
(± 3.1 volts peak).

The VF signal to be encoded Is input on the VFx lead. An
internal switch samples the signal and the hold function
is performed by the external capacitor connected to the
CAP1 x and CAP2x leads. The sampling and conversion

FsxJ~______
132_C_H_AN_N_El_S~VS~T~EM=I~=-~

The Codec will enter direct mode within three frame times
(375~ec) as measured from the time the device power supplies sellie to within the specified limits. This assumes that
CLKc Is tied to Vee and that all clocks are available at the
time the supplies have sellied.

PCM
timeAID
RMS

________~~~=-~__~~_____________________
TIME SLOT 20 -

~

---------------------------------·---·----0-----------------------------_.--_.-.------- ..

'i'Sx

CAP"

===============~~=__=~~~~DC~O~NV~.C~V~Cl~E~======~~~~~========~==========~~__~
HOLD TIME

Decoding
The PCM word is fetched by the DR lead from the PCM
highway at the proper times lot occurrence. The decoded
value Is held on an internal sample and hold capacitor.

The buffered non-return to zero output signal on the VFR
lead has a dynamic range of ±2.2 volts RMS (±3.1 volts
peak).

Standby Mode - Power Down

word is internally transferred to the control register,
invoking the standby condition.

To minimize power consumption and heat dissipation a
standby mode is provided where all Codec functions are
disabled except for Dc and CLKc leads. These allow the
Codec to be reactivated. In the microcomputer mode the
Codec is placed into standby by loading a control word
(Del with a "1" in bits 1 and 2 locations. In the direct
mode when Dc is brought high, the all "1's" control

Power-On Clear
Whether the device is used in the direct or microcomputer mode, an Internal reset (power-on clear) Is
generated, forCing the device Into the power down state,
when power Is supplied by any of the following

14-19

While in the standby mode, the Dx output is actively
held In a high Impedance state to guarantee that the
PCM bus will not be driven.
The power consumption In the standby mode is typically
33mW.

methods. (1) Device power supplies are turned on in a
system power-up situation where either Vee or Voo Is
applied last. (2) A large supply transient causes either of
the two positive supplies to drop to approximately 2
volts. (3) A board containing Codecs Is plugged Into a

inter

2911A·1

"hot" system whereVee or VDO Is the last contact made.
It may be necessary to trim back the edge connector
pins or fingers on Vee orVDD relative to the other supply
to guarantee that the power-on clear will operate
properly when a board Is plugged Into a "hot" system.
Furthermore, the Codec will Inhibit activity on
x' and

m

Precision Voltage Reference for the
D/A Converter
The "oltage reference Is generated on the chip and Is
calibrated during the manufacturing process. The
technique uses the difference In sub-surface charge
density between two suitably Implanted MOS devices to
derive a temperature stable and bias stable reference
voltage.

CONVERSION LAW

Ox during the application of power supplies.
The device Is also tolerant of transients In the negative
supply (Veal so long as Vee remains more negative than
-3~5 volts. Vee transients which exceed this level
should be detected and followed by a system relnltlallzatlon.

A gain setting op amp, programmed during manufacturing, "trims" the reference voltage source to the final
precision voltage reference value provided to the O/A
converter. The precision voltage, reference determines
the Initial gain and dynamic range characteristics
described In the A. C. Transmission Specification
section.

CODEC TRANSFER CHARACTERISTIC

The conversion law Is commonly referred to as the A

r\lF.~·············· ........ ·.. ·.... ···· .. ·-··

Law.
F(X l =5gn(x l

[1 1+ +IOQIo(AIXll].1/A';;;IX
';;;1
A
1

10910

F (xl = 5gn (Xl['
where:

AIXI

1 + log,o A

].0';;;1. xl';;; 1IA

x = the input signal
Sgn(xl = sign of the input Signal
A = 87.6 (defined by CCITTl

VFx

The Codec provides a piecewise linear approximation of
the logarithmic law through 13 segments. Each segment
Is made of 16 steps with the exception of the first segment, which has 32 steps. In adjacent ,segments the
step sizes are In a ratio of two to one. Within each
segment, the step size Is constant.
The outpu~ levsls are midway between the correspondIng decision levels. The output levels Yn are related to
the Input levels xn by the expression:

Yn=

Xn _l+ xn

2

,0 VIH

V

2.2
0.4

2.4

V

Dx, 10L = 4.0 mA
TSx, 10L 3.2 mA, open drain
PDN, 10L= 1.6mA, open drain

=

V

Dx, 10H

=15 mA

ANALOG INTERFACE
ZAI

Input Impedance when Sampling, VFx

125

300

500

Q

In series with CAPx to GRDA,
-3.1V 200 Hz
RL Connected
Between PWRO +
and PWROfo;;:> 200 Hz

vcc· +5V±5%; Vee· -5V±5%; GADA· OV; GADD· OV;un)e., otherwise specified. I
elK =1.S36MHz ±O.1%; CLKO =VILO (Tied to VeSl
elK =2.048MHz ±O.1%; CLKO =VIHO (Tied to Vee)
elK =1.544MHz ±O.1%; CLKO =Vila (Tied to GRDD)
ITA· O·Cto +70·C;

TRANSMIT FILTER TRANSFER CHARACTERISTICS (See Transmit Pilter Transfer Characteristics, Figure 7)
Symbol
GRX

Parameter

Min

Typll)

Max

Unit

Test Condilions
OdBmO Input Signal

Gain Relative to Gain at 1kHz
-50

dB

Gain Setting Op Amp at

50Hz

-56

-25

dB

Unity Gain

60Hz

-23

dB

16.67Hz

== 1.1 VRMS

-1.0

-0.125

dB

OdBmO Signal

-0 .• 25

0.125

UO

i(lpui cii VFxi-

3300Hz

-.35

0.03

dB

3400Hz

-0.7

-0.1

dB

OdBmO Signal

-14

dB

Output at VFXO

200Hz
"'.InnLI_ .&._

\JUVI 14

0"11" .......

1_

~V ~uvvnL

4000Hz

== 1.6 VRMS

-32

dB

3.0

3.1

dB

.0002

.002

.01

.07

-75

-65

Total C Message Noise at Output, VFXO

6

11

dBrncO Gain Setting Op Amp at
121 Unity Gain

NCX2

Total C Message Noise at Output, VFXO

9

13

dBrncO Gain Setting Op Amp at
121 20dB Gain

DDX

Differential Envelope Delay, VFXO
1kHz to 2.6kHz

60

DAX
DPX1

Absolute Delay at 1kHz, VFXO

110

}lS

Single Frequency Distortion Products

-48

dB

OdBmO Input Signal at 1kHz

DPX2

Single Frequency Distortion Products
at Maximum Signal Level of
+3dBmO at VFXO

-45

dB

0.16 VRMS 1kHz Input Signal at
VFXI+; Gain Setting Op Amp at
20dB Gain. The +3dBmO signal
at VFXO is 2.26 VRMS

4600Hz and Above
GAX

Absolute Passband Gain at 1kHz, VFXO

GAXT

Gain Variation with Temperature
at 1kHz

GAXS

Gain Variation with Supplies at 1kHz

CTRT

Cross Talk, Receive to Transmit,
Measured at VFXO
VFXO
20 log VFRO

NCX1

2.9

See next page for NOTES.

14-34

RL =

00,

Note 3

dBfoC OdBmO Signal Level
dBN OdBmO Signal Level,
Supplies ±5%
dB

VFRI = 1.6 VRMS, 1kHz Input
VFXI+, VFXI- Connected to
GSX, GSX Connected through
10kO to GRDA

}lS

intJ

2912A

A.C. CHARACTERISTICS
(TA =0° C to +70°C; vcc =+5V ±5%; VBB =-5V ±5%; GRDA =OV; GRDD =OV; unless otherwise specilied.)
Clock Input Frequency: ClK = 1.536MHz ±0.1%; ClKO = VllO (Tied to VBB)
ClK =1.544MHz ±0.1 %; ClKO =VIIO (Tied to GRDD)
ClK =2.048MHz ±0.1%; ClKO =VIHO (Tied to VCC)

RECEIVE FILTER TRANSFER CHARACTERISTICS (See Receive Filter Transier Char=wtujstics, Figure 8)
Symbol
GRR

Parameter

Min

Typ(1J

Max

OdBmO Input Signal
0.125

dB

-0.5

0.125

dB

-0.125

0.125

dB

3300Hz

-.35

0.03

dB

3400Hz

-0.7

-0.1

dB

4000Hz

-14

dB

4600Hz and Above

-30

dB

0

+0.1

dB

Below 200Hz
200Hz
300Hz to 3000Hz

Test Conditions

Unit

Gain Relative to Gain at 1kHz with
Sinx/x Correction 01 2910A or 2911 A

-0.1

OdBmO Signal
Sin (

== 1.6 VRMS x

~
Y(..3!!.-)
8000
8000

Input at VFRI

Rl

=

Notes 3, 4

GAR

Absolute Passband Gain at 1kHz, VFRO

GART

Gain Variation with Temperature
at 1kHz

.0002

.002

dB/oC OdBmO Signal level

GARS

Gain Variation with Supplies at 1kHz

.01

.07

dBIV OdBmO Signal level, Supplies
±5%

CTTR

Cross Talk, Transmit to Receive,
Measured at VFRO; 20 log (VFRO(VFXO)

-70

-60

NCR

Total C Message Noise at Output, VFRO

2

6

DDR

Differential Envelope Delay, VFRO,
1kHz to 2.6kHz

100

J.IS

DAR

Absolute Delay at 1kHz, VFRO

110

IlS

DPRl

Single Frequency Distortion Products

-48

dB

OdBmO Input Signal at 1kHz

DPR2

Single Frequency Distortion Products
at Maximum Signal level of
+3dBmO at VFRO

-45

dB

+3dBmO Signal level of
2.26 VRMS, 1kHz Input at
VFRI

dB

VFXI =1.1 VRMS, 1kHz Output
VFRI Connected to GRDA

dBrncO VFRO Output or PWRO+ and
[2J PWRO- Connected with Unity
Gain

NOTES:
1. Typical values are for TA = 25°C and nominal power supply values.
2. A noise measurement of 12dBrnc into a 600n load at the 2912A device is equivalent to 6dBrncO.
3. For gain under load refer to output resistance specs and perform gain calculation.
4. Output is non-inverting.

14-35

00,

2912A
TRANSFER CHARACTERISTICS

;~~:;;;;5~:1~f~
•. 1251:18

-.12Sd8
JOOOH,

300HI

,IEX,..

D.D
SCALE

.,

TYPICAL FIL TEA
• 33OI)H,
TRANSFER FUNCTION
-.3511 •

........
-.1'DeII

TYPICAL FILTEA

·30

TRANSFER FUNCTION

FREQUENCY (HII

Figure 7. Transmlt'Fllter

11

., 1

'2

EXPANDED

SCALE

TYPICAL FILTER TRANSFER

FUNCTlON'~1 WHEN MULTIPLIED

OF THE INTEL 2910A AND 291IACDDECS

WHEREK.~

...
FREQUENCY IHrl
NOTIES,
1. TY.tCAL TRANSFER FUNCTION OF THE RECEIVE FILTER AS A SEPARAn: COMPONENT.
2. TYPICAL TRANSFER FUNCTION OF THE lueEIVE FILUM D11IVEN BY THE SAMPLE AND
HOLDOUTPUT OF THE INTEL 2IlGA AND ZlIIACODEes. THE COMBINED flLTERICODEC
REII'ONIIE ME~TS THE STATED SPECIFICATIONS.

Figure 8. Receive Filter

14-36

inter

2912A

POWER SUPPLY REJECTION
TYPICAL VALUES OVER 3 RANGES

10

f-

50

r-

40

-

.

At YFXO with YFXI Connected to GRDAi Input Op Amp

vee

vee

I' Unit, alln

vee

ID

vaa

30

vaa

~

..

20

1M

"

1M

"C
Z

ID

I

10
3DO

500

3DOO 5000

1000

10000

50000

Frequlncy (Hz)

Figure 9. Transmit Filter

10

50

At VFRO with YFRI Connected 10 GRDA

vee

rvee

..!!:!:

40

.

vaa

ID

30

f-

20

I-

vaa

.!!!

."
".
1M

1M

~

10
300

500

3000 _

1000

10000

Freq....cy (Ha)

Figure 10. Receive Filter

14-37

50000

intJ
APPLICATIONS INFORMATION
2910~2911~2912A

SIGx

2910A
4-.-----___________________
--,

DIGITAL

~

SIGR __- - - - - - - - - - - - - - - - - - - - , . - - - - - - - + - V O O

POWER SUPPLY

CONTROL INPUTS
} FROM SYSTEM

LINE

~

ANALOG INPUT AND {

GAIN ADJUSTMENT

OUTPUT TO
ELECTRONIC HYBRIDS

PCM FRAME SVNCH
AND 81T CLOCKS

POWER AMPLIFIER INPUT

.----*-~ .----=:-:4--+-INPUT FROM peM HIGHWAY
POWER AMPLIFIER OUTPUT {
TO TRANSFORMER HYBRIDS

GRDA

~

~I

GRDO

*

11) OECOUPLING CAPACITORS

Figure 1. A Typical 2910A Codec and 2912A Filter Conflgur.tion

a'

Codec Interface

Clock Interface

The 2912A PCM Filter is designed to directly interface
to the 291 OA and 2911 A Codecs as shown above. The
transmit path is completed by connecting the VFxO
output ofthe 2£:l12A to the coupling capacitor associated
with the VFX input of the 2910A and 2911A codecs.
The receive path is completed by directly connecting
the codec output VFR to the receive input ofthe 2912A
VFRI. The PDN .input of the 2912A should be connected to the PDN output ofthe codec to allow the filter
to be put itrthe power-down standby mode under
control of the codec.

To assure proper operation, the ClK inputofthe 2912A
should be connected to the same clock provided to the
receive bit clock, CLKR of 2910A or 2911ACodec as
shown above. The ClKO input of the 29i2A should be
set to the proper voltage depending on the standard
clock frequency chosen for the codec and filter.

14-38

291 OA/2911 A/2912A

Grounding, Oecoupllng, and Layout
Recommendations
The most Important steps In designing a low noise line
card are to Insure that the layout of the circuit components and traces results in a minimum of cross coupling between analog and digital signals, and to provide
well bypassed and clean power supplies, solid ground
planes, and minimal lead lengths between components_
1_ All power source leads should be bypassed to
ground on each printed circuit board (PCB), on
which codecs are provided. At least one electrolytic
bypass capacitor (at least 50 "F) per board is recommended at the point where all power traces from
the codecs and filters join prior to interfacing with
the edge connector pins assigned to the power
leads.
2. When using two-sided PCBs, use both corresponding pins on opposite sides of the board for the same
power lead. Strap them together both on the PCB
and on the back of the edge connector.
3. Layout the traces on codec- and filter-equipped
boards such that analog signal and capacitor leads
are separated as widely as possible from the digital
clock and data leads.
4. Connect the codec sample and hold capacitor with
the shortest leads possible. Mount it as close to the
codec CAP1X, CAP2X pins as possible. Shield the
capacitor traces with analog ground.
5. Do not layout any board traces (especially digital)
that pass between or near the leads of the .sample
and hold capacltor(s) since they are In high Impedance circuits which are sensitive to noise coupling.
6. Keep analog voice circuit leads paired on their
layouts so that no Intervening circuit leads are
permitted to run parallel to them and/or between
them.
7. Arrange the layout for each duplicated line, trunk or
channel circuit in identical form.
8. Line circuits mounted extremely close to adjacent
line circuits increase the possibility of Interchannel
crosstalk.
9. Avoid assignment of edge connector pins to any
analog signal adjacent to any lead carrying digital
(periodic) signals or power.
10. The optimum grounding configuration is to maintain
separate digital and analog grounds on the circuit
boards, and to carry these grounds back to the
power supply with a low Impedance connection.
This keeps the grounds separate over the entire
system except at the power supply.
11. The voltage difference between ground leads GRDA
and GRDD (analog and digital ground) should not
exceed two volts. One method of preventing any
substantial voltage difference between leads GRDA
and GRDD is to connect two diodes back to back In
opposite directions across these two ground leads
on each board.
12. Codec-fllter pairs should be aligned so that pins 9
14-39

through 16 of the filter face pins 1 through 12 of the
codec. This minimizes the distance for analog connections between devices and with no crossing
analog lines.
13. No digital or high voltage level (such as ringing supply) lines should run under or In parallel with these
analog VF connections. If the analog lines are on the
top (component side) of the PC board, then GRDD,
GRDA, or power supply leads should be directly
under them, on the bottom to prevent analog/digital
coupling.
14_ Both the codec and filter devices should be shielded
from traces on the bottom of the PCB by using
ground or power supply leads on· the top side
directly under the device (like a ground plane).
15. Two +5 volt power supply leads (Vecl should be
used on each PCB, one to the filters, the other to the
codecs. These leads should be separately decoupled
at the PCB where they then join to a Single 5 volt
supply at the backplane connector. Decoupllng can
be accomplished with either a series resistor/
parallel capacitor (RC lowpass) or a series RF choke
and parallel capacitor for each 5 volt lead. The
capacitor should be at least 10"F In parallel with a
0.1 "F ceramic. This filters both high and low
frequencies and accommOdates large current
spikes due to switching.
16. Both grounds and power supply leads must have low
resistance and inductance. This should be accomplished by using a ground plane whenever possible.
When narrower traces must be used, a minimum
width of 4 millimeters should be maintained. Either
multiple or extra large plated through holes should
be used when passing the ground connections
through the PCB.
17. The 2912A PCM filter should have all power supplies bypassed to analog ground (GRDA). The 2910A
/2911A Codec +5V power supplies should be bypassed to the digital ground (GRDD). This is appropriate when separate + 5V power supply leads are
used as suggested In item 15. The -5V and +12V
supplies should be bypassed to analog ground
(GRDA). Bypass capacitors at each device should be
high frequency capacitors of approximately 0.1 to
1.0 "F value. Their lead lengths should be minimized by routing the capacitor leads to the appropriate ground plane under the device (either
GRDA or GRDD).
18. Relay operation, ring voltage application, interruptions, and loop current surges can produce enormous transients. Leads carrying such signals must
be routed well away from both analog and digital
circuits on the line card and In backplanes. Lead
pairs carrying current surges should be routed
closely together to minimize possible inductive
coupling. The microcomputer clock lead Is particularly vulnerable, and should be buffered. Care should
also be used in the backplane layout to prevent pickup surges. Any other latching components (relay
buffers, etc.) should also be protected from surges.
19. When not used, the AUTO pin should float with minimum
PC board track area.

inter

2910Al2911A12912A

2910Al2912A OdBmO
TRANSMIT
FILTER

ENCODER

DIGITAL
MILLIWATT
CODES
(OR EQUIV.)

5.85 dBm
1.52 Vrms

2.85 dBm
1.08 Vnns

POWER
AMPLIFIERS

RECEIVE
. FILTER

DECODER

5.85 dBm

5.83 dBm
1.48 Vrma

1.52 Vrma

SINGLE ENDED, 600 n
5.85 dBm,
1.52 Vrms

BALANCED, 600 n
11.9dBm
3.04 Vrms

2911A12912A OdBmO
ENCODER'

RLTER

2.88 dBm

5.88 dBm

1.08 Vrms

1.52Yrms

FILTER

DECODER

DIGITAL
MILLIWATT
CODES
(OR EQUIV.)

AMPLIFIERS

5.88 dBm

5.88 dBni

1.48 Vrms

1.52 Vrms

SINGLE ENDED, &oon

'5.88 dBm .

1.52 Vrms
BALANCED, 800 n

ii.9d8m
3.05 Vrms

14-40

2913 AND 2914
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
• 2914 Asynchronous clocks, 8th bit signaling, loop back test capability
• 2913 Synchronous clocks only, 300 mil package
• AT&T D3/D4 and CCITT Compatible for
Synchronous Operation

• Low Power HMOS-E Technology:
- 5mW Typical Power Down
-

• Pin Selectable p.-Iaw or A-law Operation

• Fully Differential Architecture Enhances
Noise Immunity

• Two Timing Modes:
- Fixed Data Rate Mode
1.536, 1.544, or 2.048 MHz
-

140mW Typical Operating

• On-Chip Auto Zero, Sample and Hold,
and Precision Voltage References

Variable Data Rate Mode
64 kHz 2.048 MHz

• Direct Interface with Transformer or
Electronic Hybrids

• Exceptional Analog Performance
• 28 Pin Plastic. Leaded Chip Carrier
(PLCC) for Higher Integration

The Intel 2913 and 2914 are fully integrated PCM codecs with transmit/receive filters fabricated in a highly
reliable and proven N-channel HMOS silicon gate technology (HMOS-E). These devices provide the functions
that were formerly provided by two complex chips (2910A or 2911A and 2912A). Besides the higher level of
integration, the performance of the 2913 and 2914 is superior to that of the separate devices.
The primary applications for the 2913 and 2914 are in telephone systems:
• Switching - Digital PBX's and Central Office Switching Systems
• Transmission - 03/04 Type Channel Banks and Subscriber Carrier Systems
• Subscriber Instruments - Digital Handsets and Office Workstations
The wide dynamic range of the 2913 and 2914 (78 dB) and ttie minimal conversion time make them ideal
products for other applications such as:
• Secure Communications Systems
• Satellite Earth Stations

• Voice Store and Forward
• Digital Echo Cancellers

l'
I

~
~

+

111<
to

~

n

6t

IoC

v"
v..

v""

PWRO+

PWRO+

GS,

PWRO-

VFxl-

PWRO-

YFxl -

GS,

YFxl+

PDN

GRDA

GS,

VFxl

PDN

GRDA

+

CLKSEL
DCLKR

TSx/DCLKx

D,

FS,

CLKSEL

Ne

Ne
PDN

LOOP

SIG.IASEL

.cLKSEL

SIG R

TSxlDCLKx

LOOP

D,

DCLKR

FS,

FS,

0,
FS,

elKx

GRDD

CLKR

VFxl-

Ne

GS,

51G R

Ne

DCLK R

DR

Ne

91

Figure 1.

Pin Configurations

14-41

SIGxlASEL
lSx/DelKx

0

0

8 :r i
C)

cg
IoC

2913 and 2914

TRANSMIT
SECTION

AUTO
ZERO

D,
YFxl+

SAMPLE
AND HOLD
AND DAC

VFxl -

SUCCESSIVE
APPROXIMATION
REGISTER

COMPARATOR

OUTPUT
REGISTER

.TSxlDCLKX

SIOXlASEl

-+-----'

GS, ___

ANALOG

TO
DIGITAL
CONTROL
lOGIC

......----------I----II--FS,
....- - - - - - - - - - - ; i + - - C L K x

RECEIVE
SECTION

CLKSEL
P1lJj

LOOP

GS.

D.

PWRO+_+~_ _..,

DCLKR

PWRO-

_-+-4----'

'-----1I--SIO.

Vee

Vaa

GRDD

GRDA

Figure 2. Block Diagram

Table 1. Pin Names
V BB
PWRO +, PWROGS R
PDN
CLKSEL
LOOP
SIG R
DCLKR
DR
FSR
GRDD
Vee

Power (-5V)
Power Amplifier Outputs
Receive Gain Control
Power Down Select
Master Clock Frequency
Select
Analog Loop Back
Receive Signaling Bit Output
Receive Variable Data Clock
Receive PCM Input
Receive Frame
Synchronization Clock
Digital Ground
Power (+5V)

14-42

GSx
VFxl-, VFxl +
GRDA
NC
SIG x

Transmit Gain Control
Analog Inputs
Analog Ground
No Connect
Transmit Signaling Input

ASEL
TS x
DCLKx
Ox
FS x

w or A·law Select
Timeslot Strobe/Buffer Enable
Transmit Variable Data Clock
Transmit PCM Output
Transmit Frame
Synchronization Clock
Transmit Master Clock
Receive Master Clock (2914
only, internally connected
to CLKx on 2913)

CLKx
CLKR

2913 and 2914
Table 2. Pin Description
Symbol

Function

Symbol

Function

Vee

Most negative supply; input voltage is - 5
volts ±5%.

GRDD

Digital ground for all internal logic circuits.
Not internally tied to GRDA.

PWRO+

Non-inverting output of power amplifier.
Can drive transformer hybrids or high
impedance loads directly in either a differential or single ended configuration.

CLK A

Receive master and data clock for the
fixed data rate mode; receive master clock
only in variable data rate mode.

CLKx

PWRO-

Inverting output of power amplifier. Functionally identical and complementary to
PWRO+.

Transmit master and data clock for the
fixed data rate mode; transmit master
clock only in variable data rate mode.

FS x

GSA

Input to the gain setting network on the
output power amplifier. Transmission level
can be adjusted over a 12dB range depending on the voltage at GSA'

8 KHz frame synchronization clock input!
timeslot enable, transmit channel. Operates independently but in an analogous
manner to FS A.

PDN

Power down select. When PDN is TTL
high. the device is active. When low, the
device is powered down.

CLKSEL

Input which must be pinstrapped to reflect
the master clock frequency at CLKx, CLKA.
.2.048 MHz
CLKSEL = Vee . . .
CLKSEL = GRDD . . . . . . . 1.544 MHz
CLKSEL = V cc' . . . . . . . . 1.536 MHz

LOOP

Analog loopback. When this pin is TTL
high, the analog output (PWRO +) is
internally connected to the analog input
(VFxl +), GSA is internally connected to
PWRO -, and VFxl- is internally connected to GSx ' A OdBmO digital signal input at DA is returned as a + 3dBmO digital
signal output at Dx.

SIG A

Signaling bit output, receive channel. In
fixed data rate mode, SIG A outputs the logical state of the eighth bit of the PCM word
in the most recent signaling frame.

DCLKA

Selects the fixed or variable data rate
mode. When DCLK A is connected to Vee,
the fixed data rate mode is selected. In
this mode, the device is fully compatible
with Intel 2910A and 2911 A direct mode
timing. When DCLK A is not connected to
Vee, the device operates in the variable
data rate mode. In this mode DCLKA becomes the receive data clock which operates at TTL levels from 64Kb to 2.048 Mb
data rates.

DA

FS A

The transmit channel enters the standby
state whenever FS x is TTL low for 300 milliseconds.
Dx

Transmit PCM output. PCM data is clocked
out on this lead on eight consecutive positive transitions of the transmit data clock:
CLKx in fixed data rate mode and DCLKx
in variable data rate mode.

TSx/DCLKx Transmit channel timeslot strobe (output)
or data clock (input) for the transmit channel. In fixed data rate mode, this pin is an
open drain output designed to be used as
an enable signal for a three-state buffer as
in 2910A and 2911 A direct mode timing. In
variable data rate mode, thiS pin becomes
the transmit data clock which operates at
TTL levels from 64Kb to 2.048 Mb data
rates.
SIGx/ASEL

Receive PCM input. PCM data is clocked
in on this lead on eight consecutive negative transitions of the receive data clock;
CLK A in the fixed data rate mode and
DCLK A in variable data rate mode.
8KHz frame synchronization clock input!
timeslot enable, receive channel. A multifunction input which in fixed data rate
mode distinguishes between signaling and
non-signaling frames by means of a double or single wide pulse respectively. In
variable data rate mode this signal must
remain high for the entire length of the
timeslot. The receive channel enters the
standby state whenever FS A is TTL low for
300 milliseconds.

14-43

A dual purpose pin. When connected to
Vee' A-law operation is selected. When it is
not connected to Vee this pin is a TTL level
input for signaling operation. This input is
transmitted as the eighth bit of the PCM
word during signaling frames on the Dx
lead. If not used as an input pin, ASEL
should be strapped to either Vec or GRDD.

NC

No connect

GRDA

Analog ground return for all internal voice
circuits. Not internally connected to GRDD.

VFxl+

Non-inverting analog input to uncommitted
transmit operational amplifier.

VFxl-

Inverting analog input to uncommitted
transmit operational amplifier.

GS x

Output terminal of transmit channel input
op amp. Internally, this is the voice signal
input to the transmit filter.

Vcc

Most positive supply; input voltage is + 5
volts ±5%.

2913 and 2914

FUNCTIONAL DESCRIPTION

The following major functions are provided:

The 2913 and 2914 provide the analog-to-digital and
the digital-to-analog conversions and the transmit and
receive filtering necessary to interface a full duplex
(4 wires) voice telephone circuit with the PCM highways of a time division multiplexed (TDM) system.
They are intended to be used at the analog termination of a PCM line or trunk.

• . Bandpass filtering of the analog signals prior to
encoding and after decoding
• Encoding and decoding of voice and call progress information
• Encoding and decoding of the signaling and supervision information

SWITCHING

r.C;;;;;;;;;;;;;:J

,..t;==~ TELEPHONE SET

TELEPHONE SET

~---------------------PAB'X/C.O. SWITCHING SYSTEM.
~~~~~~~S;ION

r---------------------I PABX/C.O. SWITCHING SYSTEM

I
I

I
I

I

CONTROL HIGHWAYS

I
I ,..-....J--,
I

I
OFF·HOOK/ROTARY DIAL PULSES

I r---'--,
I SUPERVISION

I
I

I

I
BATTERY
FEED

HYBRIDI~----_I

I

I
I

2W/4W

2913
OR
2914
COMBO

OFF·HOOK/ROTARY DIAL PULSES

PROTECTION
2W/4W r-----I~
BATTERY
FEED

2914
COMBO

HYBRID~----..,

RINGING

RINGING
. RING CONTROL

RING CONTROL

I
L
___________________ !..UJ

L _________________ P~M.!!I~~!!
FUNCTIONAL BLOCK DIAGRAM OF A LINE
CIRCUIT WITH BORROWED Blh BIT
SIGNALING

FUNCTIONAL BLOCK DIAGRAM OF A LINE
CIRCUIT WITH SEPARATE SIGNALING/
CONTROL HIGHWAYS

CHANNEL BANKS

1

FNNELuNiT-- -- -----

TO DISTANT
CENTRAL OFFICE
IHANNELU'NiT----

~I:::G~L--_~---,

2913

I
I
I
I
I
I
L__ _ __-'

TO LOCAL
CENTRAL

-

2914

COMBO

TIP

COMBO

OFFICE

I

~ ---------t...,...--y-!

OR

2914

RING

SIGNAL-IN-G-+---J

TO LOCAL

CENTRAL
OFFICE

SIGNALING
STROBES
A TYPICAL 4·WIRE CHANNEL UNIT WITH

SIGNALING USING BORROWED Blh BIT

A TYPICAL CCITT CHANNEL UNIT

Figure 3.

Typical Une Terminations

14-44

I

I

I
I
S~~~t~I~SG
I
L______,___ .JI

I
LEADS

DISTANT
CENTRAL
1TO
OFFICE

2913 and 2914

GENERAL OPERATION

frame sync buffers, which are required to power up
the device, are enabled in these modes. As shown
in Table 3, the digital outputs on the appropriate channels are placed in a high impedance state until the
device returns to the active mode.

System Reliability Features
The combochip can be powered up by pulsing FS x
and/or FSR while a TTL high voltage is applied to
PDN, provided that all clocks and supplies are connected. The 2913 and 2914 have internal resets on
power up (or when Vas or Vcc are re-applied) in order
to ensure validity of the digital outputs and thereby
maintain integrity of the PCM highway.

The Power Down mode utilizes an external control
signal to the PDN pin. In this mode, power consumption is reduced to the value shown in Table 3.
The device is active when the signal is high and inactive when it is low. In the absence of any signal,
the PDN pin floats to TTL high allowing the device to
remain active continuously.

On the transmit channel, digital outputs Dx and TS x
are held in a high impedance state for approximately
four frames (500JLS) after power l!E..or application of
Vss or Vcc. After this delay, Dx, TS x, and signaling
will be functional and will occur in the proper timeslot.
The analog circuits on the transmit side require approximately 60 milliseconds to reach their equilibrium
value due to the autozero circuit settling time. Thus,
valid digital information, such as for on/off hook detection, is available almost immediately, while analog
information is available after some delay.

The Standby mode leaves the user an option of powering either channel down separately or powering the
entire device down by selectively removing FS x and/
or FS R. With both channels in the standby state,
power consumption is reduced to the value shown in
Table 3. If transmit only operation is desired, FS x
should be applied to the device while FS Ris held low.
Similarly, if receive only operation is desired, FS R
should be applied while FS x is held low.

Fixed Data Rate Mode

On the receive channel, the digital output SIG Ris also
held low for a maximum of four frames after power
up or application of Vss or Vcc. SIGRwill remain low
thereafter until it is updated by a signaling frame.

Fixed data rate timing, which is 2910A and 2911 A
compatible, is selected by connecting DCLKR to Vss·
I! employs master clocks CLKx and CLKR, frame synchronization clocks FSx and FS R, and output TS x.

To further enhance system reliability, TSx and Dx will
be placed in a high impedance state approximately
30JLS after an interruption of CLKx. Similarly, SIG R
will be held low approximately 30JLS after an interruption of CLKR. These interruptions could possibly
occur with some kind of fault condition.

CLKx and CLKR serve· both as master clocks to operate the codec and filter sections and bit clocks to
clock the data in and out from the PCM highway. FSx .
and FSR are 8 kHz inputs which set the sampling
frequency and distinguish between signaling and
non-signaling frames by their pulse width. A frame
synchronization pulse which is one master clock wide
designates a non-signaling frame, while a double
wide sync pulse enables the signaling function. TS x
is a timeslot strobe/buffer enable output which gates

Power Down and Standby Modes
To minimiie power consumption, two power down
modes are provided in which most 2913/2914 functions are disabled. Only the power down, clock, and

Table 3. Power-Down Methods

Device Status

Power-Down
Method

Typical
Power
Consumption
5mW

Power Down Mode

PDN = TTL low

Standby Mode

FS x and FS R are TTL low

12mW

Only transmit is
on standby

FS x is TTL low

70mW

Only receive is
on standby

FS R is TTL low

110mW

Digital Output Status
TS x and Dx are placed in a high impedance
state and SIG R is placed in a TTL low state
within 10 us
TS x and Ox are placed in a high impedance
state and SIG R is placed ina TTL low state
300 milliseconds after FS x and FS R are
removed.

TS x and Ox are placed in a high impedance
state within 300 milliseconds.

14-45

SIG R is placed in a TTL low state within
300 milliseconds..

inter

2913 and 2914

the PCM word onto the PCM highway when an external buffer is used to drive the line.
Data is transmitted e)n the highway at Ox on the first
eight positive transitions of CLKx following the rising
edge of FSx. Similarly, on the receive side, data is
received on the first eight falling edges of CLKR. The
frequency of CLKx and CLKR is selected by the
CLKSEL pin to be either 1.536, 1.544, or 2.048 MHz.
No other frequency of operation is allowed in the fixed
data rate mode.

Variable Data Rate Mode
Variable data rate timing is selected by connecting
DCLKR te) tlie bit clock for the receive PCM highway
rather than to Vee. It employs master clocks CLKx
and CLKR, bit clocks DCLKR and DCLKx, and frame
synchronization clocks FSR and FS x.
Variable data rate timing allows for a flexible data
frequency. It provides the ability to vary the frequency
of the bit clocks, which can be asynchronous in the
case of the 2914 or synchronous in the case of the
2913, from 64 kHz to 2.048 MHz. Master clocks inputs
are still restricted to 1.536, 1.544, or 2.048 MHz.
In this mode, DCLKi:! and DCLKx become the data
clocks for the receive and transmit PCM highways.
While FSx is high, PCM data from Ox is transmitted

........................... 1... &. ................................'U. . . . . . Ift ..... · ........................ +1" ..... .,. ........ _

VIILV L.IO

111~II""'Q1

VII &110

I~OA,L

OI~II" \Al1,~g"'ULIYO

tJu..,.-

itive transitions of DCLKx' Similarly, while FS Ris high,
each PCM bit from the highway is receiveq by DR on
the next eight consecutive negative transitions of
DCLKR·

On the transmit side, the PCM word will be repeated
in all remaining timeslots in the 125/LS frame as long
as DCLKx is pulsed and FS x is held high. This feature
allows the PCM word to be transmitted to the PCM
highway more than olice per frame, if desired, and is
only available in the variable data rate mode. Conversely, Signaling is only allowed in the fixed data rate
mode since the variable mode provides no means
with which to specify a signaling frame.

Signaling
Signaling can only be performed with the 24-pin device in the fixed data rate timing mode (DCLKR =
Vee). Signaling frames on the transmit and receive
sides are independent of one another and are selected by a double-width frame sync pulse on the
appropriate channel. During a transmit signaling
frame, the codec will encode the incoming analog
signal and substitute the signal present on 'SIG x for
the least significant bit of the encoded PCM word.
Similarly, in a receive signaling frame, the codec will
decode the seven most significant bits according to
CCITT recommendation G.733 and output the logical
state of the LSB on the SIG R lead until it is updated
Iii the neltt signaling frame. Timing relationships for
signaling operation are shown in Figure 4.

Asynchronous Operation
The 2914 cail be operaied with asynchronous clocks
in either the fixed or variable data rate modes; In order
to avoid crosstalk problems associated with special
interrupt circuitry, the design of the Intel 2913/2914
combochip includes separate digital-to-analog con-

1

l

DX=~==============~SIOX===
.
, t"
. t'
.
SIOx ":'~-~----------""'----D
____________. .,. . .___ -N.T--------....
_____ -~-~ D"'ii"i""c:AJiE'
"",,-,,,,,_
'Bi~'

2!l~I1E.

~-"---------

D_~-~--------_----~.
.
SIOR __
_____
SIOR
;: .
,; RE
R_~_-------_:_"_---_ ~

'WVALUE

" Figure 4.

Signaling Timing (Used Only with Fixed Data Rate Mode)

14-46

intJ

2913 and 2914

verters and voltage references on the transmit and
receive sides to allow independent operation of the
two channels.
In either timing mode, the master clock, data clock,
and timeslot strobe must be synchronized at the beginning of each frame. CLKx and DCLKx are synchronized once per frame but may be of different
frequencies. The receive channel operates in a similar manner and is completely independent of the
transmit timing (refer to Variable Data Rate Timing
Diagrams). This approach requires the provision of
two separate master clocks, even in variable data rate
mode, but avoids the use of a synchronizer which can
cause intermittent data conversion errors.

Analog Loopback
A distinctive feature of the 2914 is its analog loop back
capability. This feature allows the user to send a control signal which internally connects the analog input
and output ports. As shown in Figure 5, when LOOP
is TTL high the analog output (PWRO + ) is internally
connected to the analog input (VFxl + ), GS Ris internally connected to PWRO -, and VFxl- is internally
connected to GSx.
With this feature, the user can test the line circuit
remotely by comparing ttie digital codes sent into the
receive channel (DR) with those generated on the
transmit channel (Ox). Due to the difference in transmission levels between the transmit and receive
sides, a 0 dBmO code sent into DR will emerge from
Ox as a + 3dBmO code, an implicit gain of 3 dB. Thus,
the maximum signal input level which can be tested
using analogloopback is 0 dBmO.

Precision Voltage References
No external components are required with the combochip to provide the voltage reference function. Voltage references are generated on-chip and are calibrated during the manufacturing process. The
technique uses ~ difference in sub-surface charge
density between two suitably implanted MOS devices
to derive a temperature and .bias stable reference
voltage. These references determine the gain and
dynamic range characteristics of the device.
Separate references are supplied to the transmit and
receive sections and each is trimmed independently
during the manufacturing process. The reference
value is then further trimmed in the gain setting opamps to a final precision value. With this method the
combochip can achieve the extremely accurate Digital Milliwatt Responses specified in the TRANSMISSION PARAMETERS, providing the user a significant
margin for error in other board components.

Conversion Laws
The 2913 and 2914 are designed to operate in both
wlaw and A-law systems. The user can select either
conversion law according to the voltage present on
the SIGxlASEL pin. In each case the coder and decoder process a companded 8-bit PCM word following CCITT recommendation G.711 for wlaw and Alaw conversion. If A-law operation is desired, SIG x
should be tied to Vee. Thus, signaling is not allowed
during A-law operation. If IL = 255-law operation is
selected, then SIG x is a TTL level input which modifies the LSB of the PCM output in Signaling frames.

--------------------------,

I-LOOP

I
I
I

TRANSMIT
VOICE

DX I

I
I

~~GJTIZED
LOOP BACK
RESPONSE

I
I
I
PWRO+
PWRO-

h
+...:-~~....:::........ t-.--I LL

I
DR I

DIGITIZED
PCM
TEST
TONE

COMBOCHIP ANALOG LOOP BACK FUNCTION

Figure 5.

SlmplHled Block Diagram of 2914 Combochlp In the Analog Loopback Configuration

14-47

2913 and 2914

TRANSMIT OPERATION
Transmit Filter
The input section provides gain adjustment in the
passband by means of an on-chip operational amplifier. This operational amplifier has a common mode
range of ± 2.17 volts, a DC offset of 25 mY, an open
loop voltage gain of 5000, and a unity gain bandwidth
of typically 1 MHz. Gain of up to 20 dB can be set
without degrading the performance of the filter. The
load impedance to ground (GRDA) at the amplifier
output (GS x) must be greater than 10 kilohms in parallel with less than 50 pF. The input signal on lead
VFxl + can be either AC or DC coupled. The input
op amp can also be used in the inverting mode or
differential amplifier mode (see Figure 6).
A low pass anti-aliasing section is included on-chip.
This section typically provides 35 dB attenuation at
the sampling frequency. No external components are
required to provide the necessary anti-aliasing function for the switched capacitor section of the transmit
filter.
The passband section provides flatness and stopband attenuation which fulfills the AT&T 03/04 channel bank transmission specification and CCITT
recommendation G.712. The 2913 and 2914 specifications meet or exceed digital class 5 central office
switching systems requirements. The transmit filter
transfer characteristics and specifications will be
within the limits shown in figure 8.
A high pass section configuration was chosen to reject low frequency noise from 50 and 60 Hz power
lines, 17 Hz European electric railroads, ringing fre-

I:

VFxl -

Encoding
The encoder internally samples the output of the
transmit filter andhblds each sample on an internal
sample and hold capacitor. The encoder then' performs an analog to digital conversion on a switched
capacitor array. Digital data representing the sample
is transmitted on the first eight data clock bits of the
next frame.
An on-chip autozero circuit corrects for DC-offset on
the input signal to the encoder. This autozero circuit
uses the sign bit averaging technique; the sign bit
from the encoder output is long term averaged and
subtracted from the input to the encoder. In this way,
all DC offset is removed from the encoder input
waveform.

RECEIVE OPERATION
Decoding
The PCM word at the DR lead is serially fetched on
the first eight data clock bits of the frame. A D/A
conversion is performed on the digital word and the
corresponding analog sample is held on an internal
sample and hold capacitor. This sample is then trans.
ferred to the receive filter.

Receive Filter
The receive filter provides passband flatness and
stopband rejection which fulfills both the AT&T 031
04 specification and CCITT recommendation G.712.
The filter contains the required compensation for the
(sin x)/x response of such decoders. The receive filter characteristics and specifications are shown in
Figure 9.

...

VFXI+

quencies and their harmonics, and other low frequency noise. Even though there is high rejection at
these frequencies, the sharpness of the band edge
gives low attenuation at 200 Hz. This feature allows
the use of low-cost transformer hybrids without external components.

Receive Output Power Amplifiers
GAIN=1+~

A balanced output amplifier is provided in order to ,
allow maximum flexibility in output configuration,
Either of the two outputs can be used Single ended
(referenced to GRDA) to drive single ended loads.
Alternatively, the differential output will drive a bridged
load directly. The output stage is capable of driving
loads as low as 300 ohms single ended or 600 ohms
differentially.

GSx

R,
R,

Figure 6.

The receive channel transmission level may be adjusted between specified limits by manipulation of the

Transmit Filter Gain Adjustment

14-48

inter

2913 and 2914

Table 4. Zero Transmission Level Points
Value

Units

OTLP1 x

Zero Transmission Level Point
Transmit Channel (OdBmO) wlaw

+2.76
+1.00

dBm
dBm

Referenced to 600n
Referenced to 900n

OTLP2x

Zero Transmission Level Point
Transmit Channel (OdBmO) A-law

+2.79
+1.03

dBm
dBm

Referenced to 600n
Referenced to 900n

OTLP1 R

Zero Transmission Level Point
Receive Channel (OdBmO) wlaw

+5.76
+4.00

dBm
dBm

Referenced to 600n
Referenced to 900n

OTLP2 R

Zero Transmission Level Point
Receive Channel (OdBmO) A-law

+5.79
+4.03

dBm
dBm

Referenced to 600n
Referenced to 900n

Symbol

Paramater

GSA input. GSA is internally connected to an analog
gain setting network. When GSA is strapped to
PWRO-, the receive level is maximized; when it is
tied to PWRO+, the level is minimized. The output
transmission level interpolates between 0 and -12
dB as GSA is interpolated (with a potentiometer) between PWRO + and PWRO -. The use of the output
gain set is illustrated in Figure 7.
Transmission levels are specified relative to the receive channel output under digital milliwatt conditions,.
that is, when the digital input at DA is the eight-code
sequence specified in CCITT recommendation G.711.

OUTPUT GAIN SET: DESIGN
CONSIDERATIONS

Test Conditions

Vo+ at PWRO+
Vo- at PWROVo = (Vo +) - (Vo - )(total differential response)
Rl and R2 are a gain setting resistor network with the
center tap connected to the GSA input.
A value greater than 10K ohms for Rl + R2 and less
than 100K ohms for Rl in parallel with R2 is recommended because:
(a) The parallel combination of Rl + R2 and RL sets
the total loading.
(b) The total capacitance at the GSA input and the
parallel combination of Rl and R2 define a time
constant which has to be minimized to avoid inaccuracies.
A is the gain of the power amplifiers,

(Refer to Figure 7.)
PWRO + and PWRO - are low impedance complementary outputs. The voltages at the nodes are:

For design purposes, a useful form is Rl/R2 as a
function of A.
R/R =4A-1
1 2
1 - A

®

PWRO+

R,

0

,.

v.

(Allowable values for A are those which make Rl/R2
positive.)
Examples are:
If A= 1 (maximum output), then
2913

Rl/R2 = co or V(GS A) = Vo -; i.e., GSA is tied to
PWRO-

OR

as.

2914

R,

®
v.-

PWRO-

DIGITAL
INPUT

*
Figure 7.

Gain Setting Configuration

If A = %, then
Rl/R2=2
If A = 1f.I, (minimum output) then
Rl/R2 = 0 or V(GS A) = Vo +; I.e., GSA is tied to
PWRO+
14-49

2913 and 2914

ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ..............................-1O°C to +80°C
Storage Temperature .................................-65°C to + 150°C
Vee and GRDD with Respect to Vee ................-0.3Vto 15V
All Input and Output Voltages
with Respect to Vee ......................................-0.3V to 15V
Power Dissipation ........................................................ 1.35W

"NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated
in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

D.C. CHARACTERISTICS
(TA = O°C to 70 C C, Vee = +5V ±5%, V BB = -5V ±5%, GRDA = OV, GRDD
Typical values are for TA = 25°C and nominal power supply values

=

OV, unless otherwise specified)

DIGITAL INTERFACE
Symbol

Parameter

Min

Max

Unit

10

IlA

GRDD "" VIN "" VIL (Note 1)

High Level Input Current

10

IlA

VIH "" VIN "" Vee

Input Low Voltage, except CLKSEL

0.8

V

0.4

V

IOL

V

IOH
IOH

IlL

Low Level Input Current

IIH
VIL

Typ

VIH

Input High Voltage, except CLKSEL

VOL

Output Low Voltage

VOH

Output High Voltage

2.4

VILO

Input Low Voltage, CLKSEL2

VeB

VeB
+0.5

V

VIIO

Input Intermediate Voltage, CLKSEL

GRDD

0.5

V

Vee

V

2.0

Test Conditions

V

= 3.2 mA at Dx, TS x and SIG A
= 9.6 mA at Dx
= 1.2 mA at SIG A

-0.5
VIHO

Input High Voltage, CLKSEL

Cox

Digital Output Capaeitance 3

5

CIN

Digital Input Capacitance

5

Vee
-0.5

pF
10

pF

POWER DISSIPATION
All measurements made at focLK = 2.048 MHz, outputs unloaded.

Typ

Max

Unit

Icc1

Vee Operating CurrentS

14

19

mA

Symbol

Parameter

Min

Test Conditions

IBB1

VBB Operating Current

-18

-24

mA

Icco

Vcc Power Down Current

0.5

1.0

mA

IBBO

VBB Power Down Current

-0.5

-1.0

mA

PDN "" VIL; after 1OilS

lecs

Vee Standby Current

1.2

2.4

mA

FSx, FS A

""

VIL; after 300 ms

IBes

Vee Standby Current

-1.2

-2.4

mA

FSx, FS A

""

VIL: after 300 ms

P01

Operating Power Dissipation 4

140

200

mW

PDN "" VIL; after 1OilS

Poo

Power Down Dissipation 4

5

10

mW

PDN "" VIL; after 10llS

PST

Standby Power Dissipation 4

12

25

mW

FSx, FS A

""

VIL

NOTES:

1. VIN is the voltage on any digital pin.
2. SIGx and DCLKR are TTL level inputs between GRDD and Vee; they are also pinstraps lor mode selection when tied to VBB. Under these
conditions VILO is the input low voltage requirement.
3. Timing parameters are guaranteed based on a 100 pi load capacitance. Up to eight digital outputs may be connected to Ii common PCM
highway without buffering, assuming a board capacitance 01 60 pI.
4. With nominal power supply values.
5. Vee applied last or simultaneously with Vee.

14-50

~913

and 2914

ANALOG INTERFACE, TRANSMIT CHANNEL INPUT STAGE
Symbol
lex'
R1x1

Parameter

Min

Typ

Input Leakage Current, VFxl +, VFxlInput Resistance, VFxl +, VFxl-

Max

Unit

100

nA

10

VOS X1

Input Offset Voltage, VFxl +, VFxl-

CMRR

Common Mode Rejection, VFxl+, VFxl-

Avol

DC Open Loop Voltage Gain, GSx

fe

Open Loop Unity Gain Bandwidth, GS x

CLX1

Load Capacitance, GSx

RLXI

Minimum Load Resistance, GS x

Test Conditions
-2.17V'" V1N

'"

2.17V

Mn
mV

25
55

dB

-2.17'" V1N

'"

2.17V

5000
1

MHz
pF

50
10

kn

ANALOG INTERFACE, RECEIVE CHANNEL DRIVER AMPLIFIER STAGE
Symbol

Parameter

Min

RORA

Output ReSistance, PWRO +, PWRO-

VOSRA

Single-Ended Output DC Offset, PWRO + ,
PWRO-

ClRA

Load Capacitance, PWRO +, PWRO-

A.C. CHARACTERISTICS -

Typ

Max

Unit

1

Test Conditions

n

75

±150

mV

100

pF

Relative to GRDA

TRANSMISSION PARAMETERS

Unless oth~rwise noted, the analog input is a 0 dBmO, 1020 Hz sine wave. 1 Input amplifier is set for unity gain,
noninverting. The digital input is a PCM bit stream generated by passing a 0 dBmO, 1020 Hz sine wave through
an ideal encoder. Receive output is measured single ended, maximum gain configuration.2 All output levels
are (sin xlix corrected. Specifications are for synchronous operation. Typical values are for T A = 25°C and
nominal power supply values. (TA = O°C to + 70°C; Vcc = +5V±5%; Vss = -5V ±5%; GRDA = OV;
GRDD = OV; unless otherwise specified).
.

GAIN AND DYNAMIC RANGE
Min

Typ

Max

Units

EmW

Encoder Milliwatt Response
(Transmit gain tolerance)

-0.18

±0.04

+0.18

dBmO

EmWTs

EmW variation with Temperature
and supplies

-0.07

±0.02

+0.07

dB

DmW

Digital Milli~att Response
(Receive gain tolerance)

-0.18

±0.04

+0.18

dBmO

DmWTS

DmW variation with temperature and
supplies

-0.07

±O.02

+0.07

dB

Symbol

Parameter

Test Conditions
Signal input of 1.064 Vrms wlaw
Signal input of 1.068 Vrms A-law
TA = 25'C, Vee = -5V, Vee =
+5V
± 5% supplies, 0 to 70'C
Relative to nominal conditions
Measure relative to OTLP R' Signal
input per CCITT Recommendation
G.711. Output signal of 1000 Hz,
Rl = 00
TA = 25'C; Vee = -5V, Vee = +5V.
± 5% supplies, 0 to 70'C

NOTES:
1. OdBmO is defined as the zero reference pOint of the channel under test (OTLP). This corresponds to an analog signal input of 1.064 volts rms
.
.
or an output of 1.503 volts rms for /Llaw.
2. Unity gain input amplifier: GSx is connected to VFxl-, Signal input VFxl +; Maximum gain output amplifier; GS R is connected to PWRO -,
output to PWRO +.

14-51

inter

2913 and 2914

GAIN TRACKING
, Reference Level = - 10dBmO
2913-1,2914-1
Symbol

Parameter

Min

Max

2913, 2914
Min

Max

Unit

GT1 x

Transmit Gain Tracking Error
Sinusoidal Input; wlaw

±0.2
±0.3
±0.65

±0.25
±0.5
±1.2

dB
dB
dB

+3 to -40 dBmO
-40 to -50 dBmO
-50 to -55 dBmO

GT2x

Transmit Gain Tracking Error
Sinusoidal Input; A-law

±0.2
±0.3
±0.65

±0.25
±0.5
±1.2

dB
dB
dB

+3 to -40 dBmO
-40 to -50 dBmO
-50 to -55 dBmO

GT1 R

Receive Gain Tracking Error
Sinusoidal Input; wlaw

±0.2
±0.3
±0.65

±0.25
±0.5
±1.2

dB
dB
dB

+3 to -40 dBmO
-40 to -50 dBmO
-50 to -55 dBmO
Measured at PWRO + ,
RL = 3000

GT2R

Receive Gain Tracking Error
Sinusoidal Input; A-law

±0.2
±0.3
±0.65

±0.25
±0.5
±1.2

dB
dB
dB

+3 to -40 dBmO
-40 to -50 dBmO
-50.to -55 dBmO
Measured at PWRO + ,
RL = 3000

Test Conditions

NOISE (All receive channel measurements are single ended)
2913-1,2914-1
Symbol

Parameter

Min

Typ

2913,2914

Max

Min

Typ. Max

Unit

Test Conditions

=

NXe1

Transmit Noise, C-Message
Weighted

13

15

dBrncO

VFxl+
GSx

GRDA, VFxl-

=

NXC2

Transmit Noise, .C-Message
Weighted with Eighth Bit Signaling

16

18

dBrncO

VFxl + = GRDA, VFxlGSx; 6th frame Signaling

=

Nxp

Transmit Noise, Psophometrically
Weighted

-77

-75

dBmOp

VFxl +
GSx

NRC1

Receive Noise, C-Message
Weighted: Quiet Code

8

11

dBrncO

DR

NRC2

Receive Noise, C~Message
Weighted: Sign bit toggle

9

12

dBrncO

Input to DR is zero code
with sign bit toggle at 1 kHz
rate

NRP

Receive Noise, Psophometrically
Weighted

-82

-79

dBmOp

DR = lowest positive
decode level

NSF

Single Frequency Noise
End to End Measurement

-50

-50

dBmO

CCITT G.712.4.2
Measure at PWRO +

PSRR,

Vee Power Supply Rejection,
Transmit Channel

-30

-30

dB

Idle channel; 200mV pop
signal on supply; 0 to
50kHz, measure at Dx

PSRR2 VBB Power Supply Rejection,
Transmit Channel

-30

-30

dB

Idle channel; 200 mV Pop
signal on supply; 0 to 50
kHz, measure at Dx

PSRR3

Vcc Power Supply Rejection,
Receive Channel

-25

-25

dB

Idle channel; 200 mV pop
signal on supply; measure
narrow band at PWRO + ,
to 50 kHz

PSRR4

VBB Power Supply Rejection,
Receive Channel

-25

-25

dB

,

=

=

GRDA, VFxl-

=

11111111

o

Idle channel; 200 mV pop
Signal on supply; measure
narrow band at PWRO + ,
to 50 kHz

o
14-52

inter

2913 and 2914

NOISE (All receive channel measurements are single ended)
2913-1,2914-1
Parameter

Max

Unit

Test Conditions

Crosstalk, Transmit to Receive

-80

-71

dB.

VFxl + = OdBmO, 1.02
kHz, DR = lowest positive
decode level, measure at
PWRO+

CTRT

Crosstalk, Receive to Transmit

-80

-71

dB

DR = OdBmO, 1.02 kHz,
VFxl + = GRDA, measure
at Dx

Min

Typ

2913, 2914

CTTR

Symbol

Min

Max

Typ

DISTORTION
Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

o to

SD1 x

Transmit Signal to Distortion, (.I-Law
Sinusoidal Input;
CCITI G.712-Method 2

36
30
25

dB
dB
dB

-30 dBmO
-30 to -40 dBmO
-40 to -45 dBmO

SD2x

Transmit Signal to Distortion, A-Law
Sinusoidal Input;
CCITI G.712-Method 2

36
30
25

dB
dB
dB

Oto -30 dBmO
-30 to -40 dBmO·
-40 to -45 dBmO

SD1 R

Receive Signal to Distortion, (.I-Law
Sinusoidal Input; CCITI G.712-Method
2

36
30
25

dB
dB
dB

o to -30 dBmO
-30 to -40 dBmO
-40 to -45 dBmO

SD2R

Receive Signal to Distortion, A-Law
Sinusoidal Input; CCITI G.712-Method
2

36
30
25

dB
dB
dB

o to -30dBmO
-30 to -40 dBmO
-40 to -45 dBmO

DPx

Transmit Single Frequency Distortion
Products

-46

dBmO

DPR

Receive Single Frequency Distortion
Products

-46

dBmO

IMD1

Intermodulation Distortion,
End to End Measurement

-35

dB

CCITIG.712 (7.1)

IMD2

Intermodulation Distortion,
End to End Measurement

-49

dBmO

CCITI G.712 (7.2)

SOS

Spurious Out 01 Band Signals,
End to E Id Measurement

-25

dBmO

'CCITIG.712 (6.1)

SIS

Spurious in Band Signals,
End to End Measurement

-40

dBmO

CCITI G. 712 (9)

DAJ(

Transmit Absolute Delay

245

(.Is

AT&T Advisory #64 (3.8)

o dBmO Input Signal

AT&T Advisory #64 (3.8)

o dBmO Input Signal

Fixed Data Rate. CLKx=2.048 MHz

o dBmO, 1.02 kHz
signal at VFxl +
Measure at Ox'

Dox

Transmit Differential Envelope Delay
Relative to DAJ(

170
95
45
105

(.IS
(.IS
(.IS
(.IS

1=
1=
1=
f =

DAR

Receive Absolute Delay

190

(.Is

Fixed Data Rate, CLK R = 2.048
MHz; Digital input is DMW
codes. Measure at PWRO +

DOR

Receive Differential Envelope Delay
Relative to DAR

45
35
85
110

(.Is
(.IS
(.Is
(.IS

f
f
f
f

14-53

=
=
=
=

500-600 Hz
600 - 1000 Hz
1000 - 2600 Hz
2600 - 2800 Hz

500-600 Hz
600 - 1000 Hz
1000 - 2600 Hz
2600 - 2800 Hz

intJ

2913 and 2914

TRANSMIT CHANNEL TRANSFER CHARACTERISTICS

.

.

Input amplifier is set for unity gain noninvertlng' maximum gain output

Symbol
Glix,

Parameter

~p

Min

Max

Unit

lest Conditions

odBmO Signal input at VFxl +

Gain Relative to Gain at 1.02 kHz
16.67 Hz

-30

dB

50 Hz

~25

dB

60 Hz

-23

dB

200 Hz

-1.8

-0.125

dB

300 to 3000 Hz

-0.125

+0.125

dB

3300 Hz

-0.35

+0.03

dB

3400 Hz

-0.7

-0.10

dB

4000 Hz

-14

dB

4600 Hz and Above

-32

dB

-j";".EO
SCALE

_1

........
-.rGIII.

TYPICAL FIL TEA
TRANSFER FUNCTION

FREQU£NCY IHII

Figure 8. Transmit Channel

14-54

2913 and 2914

RECEIVE CHANNEL TRANSFER CHARACTERISTICS
Symbol
GRR

Parameter

Min

lYP

Max

o dBmO Signal input at DR
+0.125

dB

200 Hz

-0.5

+0.125

dB

300 to 3000 Hz

-0.125

+0.125

dB

3300 Hz

-0.35

+0.03

dB

3400 Hz

-0.7

-0.1

dB

4000 Hz

-14

dB

4600 Hz and Above

-30

dB

Below 200 Hz

Test Conditions

Unit

Gain Relative to Gain at 1.02 kHz

EXPANDED
SCALE

FREOUENCY (Hrl

Figure 9. Receive Channel

14-55

2913 and 2914

A.C. CHARACTERISTICS - TIMING PARAMETERS
CLOCK SECTION
Parameter

Symbol

Typ

Min

Max

Unit

ley

Clock Period, CLKx, CLKA

488

ns

IeLK

Clock Pulse Width, CLKx, CLKA

220

ns

tOCLK

Data Clock Pulse Width

220

leoc

Clock Duty Cycle, CLKx, CLKA
Clock Rise and Fall Time

45

~,~

ns
50

5

55

%

30

ns

Max

Unit

145

ns

Test Conditions
fCLKX = fCLKA =·2.048 MHz
64 kHz,.; fOOLK ,.; 2.048 MHz

TRANSMIT SECTION, FIXED DATA RATE MODE'
Symbol

Parameter

Min

Typ

Test Conditions

tozx

Data Enabled on TS Entry

0

toox

Data Delay from CLKx
Data Float on TS Exit

0

145

ns

tHZX

60

215

ns

CLOAO = 0

tSON

Timeslot X to Enable

0

145

ns

tSOFF
tFSO

Timeslot X to Disable

60

215

ns

0< CLOAD < 100 pf
CLOAO = 0

Frame Sync Delay

100

ley-l00

ns

tss

Signal Setup Time

0

ns

tSH

Signal Hold Time

0

ns

0< CLOAD < 100 pf
0< CLOAD < 100 pf

RECEIVE SECTION, FIXED DATA RATE MODE
Svm!lo!

Pere.meter

Min

TVp

Mel!

Unit
ns

leSA

Receive Data Setup

10

leHA
tFSO
tSIGA

Receive Data Hold

60

Frame Sync Delay

100

tCy -l00

ns

0

2

!.IS

SIG A Update

ns

NOTES:
1. Timing parameters Iozx, tHZX, and tSOFF are referenced to a high impedance state.

14-56

Test Conditions

2913 and 2914

WAVEFORMS
Fixed Data Rate Timing
TRANSMIT TIMING

CLKx

FSx
NON·SIGNALING
FRAMES

FSx
SIGNALING
FRAMES

CLKx

Dx

_~'SON
TSX

I

_________________'---,SS~ ~

SIGx

DON'T CARE
NOTE: ALL TIMING PARAMETERS REFERENCED TO VIH AND VIL EXCEPT
tOZX. tSOFF AND IHZX WHICH REFERENCE A HIGH IMPEDANCE STATE

RECEIVE TIMING

FS.
NON-SIGNALING
FRAMES

FS.
SIGNALING
FRAMES

NOTE: ALL TIMING PARAMETERS REFERENCED TO VIH AND Vil.

14-57

X

VALID

-lk'SOFF
- L'S" .

X

g~~l

inter

2913 and 2914

TRANSMIT SECTION, VARIABLE DATA RATE MODEl
Symbol

Parameter

tTSOX

Timeslot Delay from DCLKl

tFso

Frame Sync Delay

toox

Data Delay from DCLKx

tOON

Timeslot to Dx Active

tOOFF

Timeslot to Dx Inactive

tox

Data Clock Period

tOFSX

Data Delay Irom FSx

Min

Typ

140
100
0
0
0
488
0

Max

Unit

tox -140

ns

lcy-100
100
50
80
15620
140

ns
ns
ns
ns

Test Conditions

0< CLOAO < 100 pf
0< CLOAO < 100 pi
o < CLOAO < 100 pi

ns
ns

RECEIVE SECTION, VARIABLE DATA RATE MODE
Symbol

Parameter

tTsOR

Timeslot Delay from DCLKR3

tFso

Frame Sync Delay

tOSR

Data Setup Time

tOHR

Data Hold Time

tOR

Data Clock Period

tSER

Timeslot End Receive Time

Min

Typ

140
100
10
60
488
60

Max

Unit

toR -140

ns

lcy-100

ns

Test Conditions

ns

ns

15620

ns
ns

64 KB OPERATION, VARIABLE DATA RATE MODE
Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

tFSLX

Transmit Frame Sync Minimum
Downtime

488

ns

FS x is TTL high lor remainder 01
frame

tFSLR

Receive Frame Sync Minimum
Downtime

1952

ns

FS R is TTL high for remainder of
irame

tocLK

Data Clock Pulse Width

10

NOTES:
1. Timing parameters tOON and tOOFF are referenced to a high impedance state.

2. tFSLX ' minimum requirements overrides tTsoX maximum spec for 64 kHz operation.
3. tFSLR minimum requirements overrides tTSOR maximum spec for 64 kHz operation.

14-58

JLS

2913 and 2914

VARIABLE DATA RATE TIMING
TRANSMIT TIMING
FS.

_-'+_-'

RECEIVE TIMING

NOTE: ALL TIMING PARAMETERS REFERENCED TO V!H AND V'L EXCEPT
lOON AND IOFF WHICH REFERENCE A HIGH IMPEDANCE STATE

A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUT/OUTPUT

u=x

0.45

2.0

2.0

>TEST POINTS<
0.8

0.8

x=

A.C. TESTING: INPUTS ARE DRIVEN AT2.4V FOR A LOGIC~1" and O.45V FOR A
LOGIC "0", TIMING MEASUREMENTS ARE MADE AT 2,OV FOR A LOGIC"1" AND
O.6V FOR A LOGIC "0",

14-59

2916 AND 2917
HMOS COMBINED SINGLE CHIP:PCM CODEC AND FILTER

•
•
•
•

•

2916,u·Law, 2.048 MHz Master Clock

•

2917 A·Law, 2.048 MHz Master Clock

•
•

New 16·Pin Package for Higher
Linecard Density
AT&T D3/o4 and CCITT Compatible
Variable Timing Mode for Flexible
Digital Interface: Supports Data
Rates from 64 KB to 2.048 MB

•
•

Fixed Timing Mode for Standard
32·Channel Systems: 2.048 MHz
Master Clock

Fully Differential Internal Architecture
Enhances Noise Immunity
Low Power HMOS·E Technology
-SmW Typical Power Down
-t40mW Typical Qperating
On Chip Auto Zero, Sample and Hold,
and Precision Voltage References.
Compatible with Direct Mode Intel
2910A, 2911A, and 2912A Designs

The Intel 2916 and 2917 are limited feature versions of Intel's 2913 and 2914 combination codec/filter
chips. They are fully integrated PCM codecs with transmit/receive filters fabricated in a highly reliable
and proven N-channel HMOS silicon gate technology (HMOS-E). These devices provide the functions
that were formerly provided by two complex chips (2910A or 2911A and 2912A). Besides the higher
level of integration, the performance of the 2916 and 2917 is superior to that.of the separate devices.
The primary applications for the 2916 and 2917 are in telephone systems:
• Switching - Digital PBX's and Central Office Switching Systems
• Subscriber Instruments - Digital Handsets and Office Workstations
Other possible applications can be found where the wide dynamic range (78 dB) and minimum conversion time (125,us) are required for analog to digital interface functions:
• High Speed Modems
• Voice Store and Forward

• Secure Communications
• Digital Echo Cancellation

vcc

VBB
PWRO+

GS x

PWRO-

VFX I -

PDN

GRDA

DCLK R

TSXIDCLKX

DR

Ox

FS R

FSx

GRDD

CLK

Figure 1. Pin Configuration

14-60

inter

2916 and 2917

XMIT
SECTION

AUTO
ZERO

GS, _ -......- - - - - ,

VFxl -

SAMPLE
AND HOLD
AND OAe

SUCCESSive
APPROXIMATION
REGISTER

COMPARATOR

ANALOG
TO
DIGITAL
CONTROL

OUTPUT
REGISTER

1----------4-----to--

FS,

L....::LO~G~'e~.tr-----::------I---eLK

Rev

SECTION

PWRO +

--+-r-t enable, transmit channel. Operates independently but in an analogous
manner to FSR. The transmit channel enters the standby state whenever FSx is
TTL low for 300 milliseconds.

Ox

PClKR

Selects the fixed or variable data rate
mode. When DClKRis connected to Vee,
the fixed data rate mode is selected. In
this mode, the device Is fully compatible
with Intel 2910A and 2911A direct mode
timing. When DClKRis not conneCted to
V~B; the device operates in the variable
data rate mode. In this mode DClKRbecomes the receive data clock which operates at TTL levels from 64Kb to 2.048 Mb
data rates.

Transmit PCM output. PCM data is clocked
out on this lead on eight consecutive positive transitions of the transmit data clock:
ClK in fixed data rate mode and DClKx In
variable data rate mode.

OR

FSR

TSx/DClKx Transmit channel timeslot strobe (output)
or data clock (input) for the transmit chan:
nel. In fixed data rate mode, this pin is an
open drain output designed to be used as
an enable signal for a three-state buffer as
in 2910A and 2911A direct rnode timing. In
variable data rate mode, this pin becomes
the transmit data clock which operates at
TTL levels from 64Kb to 2.048 Mb data
rates.

Receive PCM input. PCM data is clocked
in on this lead on eight consecutive negative transitions of the receive data clock;
ClK in the fixed data rate mode and
DCl~ in variable data rate mode.
8KHz frame synchronization clock input!
timeslot enable, receive channel. In variable data rate mode this signal must remain
high for the entire length of the timeslot.
The receive channel enters the standby
state whenever FSRis TTL low for 300
milliseconds.

14-62

GRDA

Analog ground return for all -internal voice
circuits. Not internally connected to GRDD.

VFxl -

Inverting analog Input to uncommitted
transmit operational amplifier.

GSx

Output terminal of on-chip transmit channel
input op amp. Internally, this is the voice
signal input to the transmit filter. .

Vee

Most positive supply; input voltage is + 5
volts ±5%.

inter

2916 and 2917

FUNCTIONAL DESCRIPTION

To enhance system reliability, TSx and Dx will be
placed in a high impedance state approximately 30ILS
after an interruption of ClK.

The 2916 and 2917 provide the analog-to-digital and
the digital-to-analog conversions and the transmit and
receive filtering necessary to interface a full duplex
(4 wires) voice telephone circuit with the PCM highways of a time division mUltiplexed (TDM) system.
They are intended to be used at the analog termination of a PCM line.

Power Down and Standby Modes
To minimize power consumption, two power down
modes are provided in which most 2916/2917 functions are disabled. Only the power down, clock, and
frame sync buffers, which are required to power up
the device, are enabled in these modes. As shown
in Table 3, the digital outputs on the appropriate channels are placed in a high impedance state until the
device returns to the active mode.

The following major functions are provided:
• Bandpass filtering of the analog signals prior to
encoding and after decoding

The Power Down mode utilizes an external control
signal to the PDN pin. In this mode, power consumption is reduced to an average of 5 mW. The
device is active when the signal is high and inactive
when it is low. In the absence of any signal, the PDN
pin floats to TTL high allowing the device to remain
active continuously.

• Encoding and decoding of voice and call progress information
• Encoding and decoding of the signaling and supervision information

GENERAL OPERATION
System Reliability Features
The combochip can be powered up by pulsing FS x
and/or FS R while a TTL high voltage is applied to
PDN, provided that all clocks and supplies are connected. The 2916 and 2917 have internal resets on
power up (or when Vee or Vcc are re-applied) in order
to ensure validity of the digital outputs and thereby
maintain integrity of the PCM highway.
On the transmit channel, digital outputs Dx and TS x
are held in a high impedance state for approximately
four frames (500JLS) after power up or application of
Vee or Vcc. After this delay, Dx and TS x will be functional and will occur in the proper timeslot. The analog
circuits on the transmit side require approximately 60
milliseconds to reach their equilibrium value due to
the autozero circuit settling time.

The Standby mode leaves the user an option of powering either channel down separately or powering the
entire device down by selectively removing FS x and/
or FS R• With both channels in the standby state,
power consumption is reduced to an average of 12
mW. If transmit only operation is desired, FS x should
be applied to the device while FS R is held low. Similarly, if receive only operation is desired, FS R should
be applied while FS x is held low.

Fixed Data Rate Mode
Fixed data rate timing, which is 2910A and 2911 A
compatible, is selected by connecting DClK R to VeB'
It employs master clock ClK, frame synchronization
clocks FS x and FS R, and output TS x.
ClK serves as the master clock to operate the eodee

Table 3. Power-Down Methods

Device Status

Power-Down
Method

Power Down Mode

PDN = TTL low

Standby Mode

Typical
Power
Consumption

Digital Output Status

5mW

TS x and Ox are placed in a high impedance
state within 10 I1.S.

FS x and FSR are TTL low

12mW

TS x and Ox are placed in a high impedance
state within 300 milliseconds.

Only transmit is
on standby

FSx is TTL low

70mW

TS x and Ox are placed in a high impedance
state within 300 milliseconds.

Only receive is
on standby

FS R is TTL low

110mW

14-63

inter

2916 and 2917

and filter sections and as the bit clock to clock the
data in and oLit from the PCM highway. FSx and FS R
are 8 kHz inputs which set the sampling frequency.
TSx is a timeslot strobe/buffer enable output which
gates the PCM word onto the PCM highway when an
external buffer is used to drive the line.
Data is transmitted on the highway at Dx on the first
eight positive transitions of ClK following the rising
edge of FS x. Similarly, on the receive side, data is
received on the first eight falling edges of ClK. The
frequency of ClK must be 2.048 MHz. No other frequency of operation is allowed in the fixed data rate
mode.

. value is then further trimmed in the gain setting opamps to a final precision value. With this method the
combochip can achieve the extremely accurate Digital Milliwatt Responses specified in the TRANSMISSION PARAMETERS, providing the user a significant
margin for error in other board components.

TRANSMIT OPERATION
Transmit Filter

Variable Data Rate Mode
Variable data rate timing is selected by connecting
DClKR to the bit clock for the receive PCM highway
rather than to Vss. It employs master clock ClK, bit
clocks DClKR and DClKx, .and frame synchronization clocks FS R and FS x.
Variable data rate timing allows for a flexible data
frequency. It provides the ability to vary the frequency
of the bit clocks, from 64 kHz to 2.048 MHz. The
master clock is still restricted to 2.048 MHz.
In this mode, DClKR and DClKx become the data
clocks for the receive and transmit PCM highways.
While FS x is high, PCM data from Dx is transmitted
onto the highway on the next eight consecutive positive transitions of DClKx' Similarly, while FS Ris high,
each PCM bit from the highway is received by DR on
the next eight consecutive negative transitions of
DClKR·

The input section provides gain adjustment in the
passband by means of an on-chip operational amplifier. This operational amplifier has a common mode
range of ± 2.17 volts, a maximum DC offset of 25 mV,
a minimum open loop voltage gain of 5000; and a
unity gain bandwidth of typically 1 MHz. Gain of up
to 20 dB can be set without degrading the performance of the filter. The load impedance to ground
(GRDA) at the amplifier output (GS x) must be greater
than 10 kilohms in parallel with less than 50 pF. The
input signal on lead VFxl- can be either AC or DC
coupled. The input op amp can only be used in the
inverting mode as shown in Figure 3.
A low pass anti-aliasing section is included on-chip.
This section typically provides 35 dB attenuation at
the sampling frequency. No external components are
required to provide the necessary anti-aliasing function for the switched capacitor section of the transmit
filter.

On the transmit side, the PCM word will be repeated
in all remaining timeslots in the 125tLs frame as long
as DClKx is pulsed and FS x is held high. This feature
allows the PCM word to be transmitted to the PCM
highway more than once per frame, if desired, and is
only available in the variable data rate mode.

G5 x

Precision Voltage References
No external components are required with the combochip to provide the voltage reference function. Voltage references are generated on-chip and are
calibrated during the manufacturing process. The
technique uses a difference in sub-surface charge
density between two suitably implanted MOS devices
to derive a temperature and bias stable reference
voltage. These references determine the gain and
dynamic range characteristics of the device.
Separate references are supplied to the transmit and
receive sections and each is trimmed independently
during the manufacturing process. The reference
14-64

Gain

= _ .I!£
R1

/,
Input

Figure 3. Transmit Filter Gain Adjustment

2916 and 2917

The passband section provides flatness and stopband attenuation which fulfills the AT&T 03/04 channel bank transmission specification and CCITT
recommendation G.712. The 2916 and 2917 specifications meet or exceed digital class 5 central office
switching systems requirements. The transmit filter
transfer characteristics and specifications will be
within the limits shown in Figure 4.

RECEIVE OPERATION
Decoding
The PCM word at the DR lead is serially fetched on
the first eight data clock bits of the frame. A DIA
conversion is performed on the digital word and the
corresponding analog sample is held on an internal
sample and hold capacitor. This sample is then transferred to the receive filter.

A high pass section configuration was chosen to reject low frequency noise from 50 and 60 Hz power
lines, 17 Hz European electric railroads, ringing frequencies and their harmonics, and other low frequency noise. Even though there is high rejection at
these frequencies, the sharpness of the band edge
gives low attenuation at 200 Hz. This feature allows
the use of low-cost transformer hybrids without external components.

Receive Filter
The receive filter provides passband flatness and
stopband rejection which fulfills both the AT&T 031
04 specification and CCITT recommendation G.712.
The filter contains the required compensation for the
(sin x)/x response of such decoders. The receive filter
characteristics and specifications will be within the
limits shown in Figure 5.

Encoding

Receive Output Power Amplifiers

The encoder internally samples the output of the
transmit filter and holds each sample on an internal
sample and hold capacitor. The encoder then performs an analog to digital conversion on a switched
capacitor array.· Digital data representing the sample
is transmitted on the first eight data clock bits of the
next frame.

A balanced output amplifier .is provided in order to
allow maximum flexibility in output configuration.
Either of the two outputs can be used single ended
(referenced to GRDA) to drive single ended loads.
Alternatively, the differential output will drive a bridged
load directly. The output stage is capable of driving
loads as low as 300 ohms single ended or 600 ohms
differentially.

An on-chip autozero circuit corrects for DC-offset on
the input signal to the encoder. This autozero circuit
uses the sign bit averaging technique; the sign bit
from the encoder output is long term averaged and
subtracted from the input to the encoder. In this way,
all DC offset is removed from the encoder input
waveform.

Transmission levels are specified relative to the receive channel output under digital milliwatt conditions,
that is, when the digital input at DR is the eight-code
sequence specified in CCITT recommendation G.711.

Table 4. Zero Transmission Level Points
Symbol

Parameter

Value

Units

Test Conditions

CTLPl x

Zero Transmission Level Point
Transmit Channel (CdBmC) Wlaw

+2.76
+1 ..0.0

dBm
dBm

Referenced to 6CCn
Referenced to 9CCn

CTLP2 x

Zero Transmission Level Point
Transmit Channel (CdBmC) A-law

+2.79·
+1 ..03

dBm
dBm

Referenced to 6CCn
Referenced to 9ccn

CTLP1 R

Zero Transmission Level Point
Receive Channel (CdBmC) wlaw

+5]6
+4..0.0

dBm
dBm

Referenced to 6CCn
Referenced to 9CCn

CTLP2 R

Zero Transmission Level Point
Receive Channel (CdBmC) A-law

+5.79
+4..03

dBm
dBm

Referenced to 6CCn
Referenced to 9.Oon

14-65

2916 and 2917

ABSOLUTE MAXIMUM RATINGS

"NOTICE: Stresses above those listed under
"Absolute Maximum Ratings" may cause perma·
nent damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions above those in·
dicated in the operational sections of this
specification is not implied. Exposure to abo
solute maximum rating conditions for extended
periods may affect device reliability.

Temperature Under Bias ..... - 10°C to + 80 °C
Storage Temperature ....... - 65°C to + 150°C
Vcc and GRDD with Respect
to Vee ...................... - 0.3V to 15V
All Input-and Output Voltages
with Respect to Vee ........... - 0.3V to 15V
Power Dissipation .................... 1.35W

D.C. CHARACTERISTICS

(TA = OOCt0700C,Vcc = +5V ±5%,Vee = -5V ±5%,GRDA = OV,GRDD = OV,unlessotherwise
specified)
Typical values are for TA = 25°C and nominal power supply values
DIGITAL INTERFACE
Symbol
Parameter
Typ
Max
Unit
Min
Test Conditions
IlL

Low Level Input Current

10

IlA

GRDD '" VIN '" VIL (Note 1)

IIH

High Level Input Current

10

IlA

VIH '" VIN '" Vcc

0.8

V

0.4

V

IOL

V

IOH

VIL

Input Low Voltage

V IH

Input High Voltage

VOL

Output Low Voltage

VOH

,Output High Voltage

2.0

V

2.4

Cox

Digital Output Capacitance2

5

CIN ;

Digital Input Capacitance

5

= 3.2 mA at Dx. TSx
= 9.6 mA at Dx

pF
10

pF

POWER DISSIPATION
All measurements made at fOCLK = 2.048 MHz, outputs unloaded.

Typ

Max

Unit

ICCl

Vee Operating Current'

14

19

mA

Symbol

Parameter

Min

Test Conditions

leel

Vee Operating Current

-18

-24

mA

Icco

Vcc Power Down Current

0.5

1.0

mA

PDN '" VIL; after lOllS

leeo

Vee Power Down Current

-0.5

-1.0

mA

PDN '" VIL; after lOllS

Iccs

Vcc Standby Current

1.2

2.4

mA

FSx; FS R

'"

VIL; after 300 ms

lees

Vae Standby Current

-1.2

-2.4

mA

FSx; FS R

'"

VIL: after 300 ms

POl

Operating Powe'r Dissipation 3

140

200

mW

Poo

Power Down Dlssipation 3

5

10

mW

PDN '" VIL; after lOllS

PST

Standby Power Dissipation 3

12

25

mW

FSx, FS R

'"

VIL

NOTES:
1. VIN is the voltage on any digHaI pin.
2. Timing perametelS are guaranteed based on a 100, pF load capacHance. Up 10 eight digHaI outputs may be connected \0 a common PCM
highway without buffering, assuming a board capacitance of 60 pF.
3. With nominal power supply values.
4. Vee applied last or simuHaneousiy with VeB'

14-66

-

2916 and 2917

ANALOG INTERFACE, TRANSMIT CHANNEL INPUT STAGE
Symbol

Parameter

Min

IBXl

Input Leakage Current, VFxl-

R1x1

Input Resistance, VFxl-

VOSX1

Input Offset Voltage, VFxl-

AVOL

DC Open Loop Voltage Gain, GS x

fe

Open Loop Unity Gain Bandwidth, GSx

CLX1

Load Capacitance, GSx

RLXI

Minimum Load Resistance, GS x

Typ

Max

Unit

100

nA

10

Test Conditions
-2.17V "" V1N "" 2.17V

M!1
25

mV

5000
1

MHz
50

pF

10

k!1

ANALOG INTERFACE, RECEIVE CHANNEL DRIVER AMPLIFIER STAGE
Symbol

Parameter

Min

RORA
VOSRA

Output Resistance, PWRO +, PWRO-

CLRA

Load Capacitance, PWRO +, PWRO-

Single-Ended Output DC Offset, PWRO +,
PWRO-

A.C. CHARACTERISTICS -

Typ

Max

Unit

1

!1

75

mV
100

Test Conditions
Relative to GRDA

pF

TRANSMISSION PARAMETERS

Unless otherwise noted, the analog input is a 0 dBmO, 1020 Hz sine wave. 1 Input amplifier is set for unity gain,
inverting. The digital input is a PCM bit stream generated by passing a 0 dBmO, 1020 Hz sine wave through an
ideal encoder. Receive output is measured single ended. All output levels are (sin x)/x corrected. Typical values
are for TA = 25°C and nominal power supply values. (TA = O°C to + 70°C; Vee = +5V±5%; VBB = -5V ±5%;
GRDA = OV; GRDD = OV; unless otherwise specified).
GAIN AND DYNAMIC RANGE
Symbol

Min

Typ

Max

Units

EmW

Encoder Milliwatt Response
(Transmit gain tolerance)

Parameter

-0.18

:!:0.04

+0.18

dBmO

EmWTs

EmW variation with Temperature and
supplies

-0.07

:!:0.02

+0.07

dB

DmW

Digital Milliwatt Response
(Receive gain tolerance)

-0.18

:!:0.04

+0.18

dBmO

DmWTs

DmW variation with temperature and
supplies

-0.07

:!:0.02

+0.07

dB

Test Conditions
Signal input of 1.064 Vrms wlaw
Signal input of 1.068 Vrms A-law
TA = 25°C, VBB = -5V, Vee =
+5V
:!: 5% supplies, 0 to 70°C
Relative to nominal conditions
Measure relative to OTLP R• Signal
input per CCID Recommendation
G.711. Output signal of 1000 Hz.
RL = 00
TA = 25°C; VBB = -5V,
Vee = +5V.
:!:5% supplies, 0 to 70°C

NOTES:

1. OdBmO is defined as the zero reference point of the channel under test (OTLP). This corresponds to an analog signal input of 1.064 volts rms or
an output of 1.503 volts rms (for !'law).

14-67

2916 and 2917

GAIN TRACKING

Reference Level

=

-

10dBmO
2916

Symbol

Parameter

GTl x

Transmit Gain Tracking Error
Sinusoidal Input; wlaw

GT2 x

Transmit Gain Tracking Error
Sinusoidal Input; A-law

GT1 R

Receive Gain Tracking Error
Sinusoidal Input; wlaw

GT2 R

Receive Gain Tracking Error
Sinusoidal Input; A-law

Min

2917
Max

Max

Min

0.25
0.5
1.2
0.25
0.5
1.2
0.25
0.5
1.2

0.25
0.5
1.2

Test Conditions

Unit
dB
dB
dB

+3 to -40 dBmO
-40 to -50 dBmO
-50 to -55 dBmO

dB
dB
dB

+3 to -40 dBmO
-40 to -50 dBmO
-50 to -55 dBmO

dB
dB
dB

+3 to -40 dBmO
-40 to -50 dBmO
-50 to -55 dBmO
Measured at PWRO + ,
RL = 300n

dB
dB
dB

+3 to -40 dBmO
-40 to -50dBmO
-50 to -55 dBmO
Measured at PWRO + ,
RL = 300n

NOISE (All receive channel measurements are single ended)
2917

2916
Symbol

Paramete.r

Min

Typ

Max

Min

Typ

Max

15

Unit

Test Conditions

Nxc1

Transmit Noise, C-Message
Weighted

dBrncO

Unity Gain

Nxp

Transmit Noise, Psophometrically
Weighted

dBmOp

Unity Gain

NRC1

Receive Noise, C-Message
Weighted: Quiet Code

11

dBrncO

DR

NRC2

Receive Noise, C-Message
Weighted: Sign bit toggle

12

dBrncO

Input to DR is zero code
with sign bit toggle at 1 kHz
rate

NRP

Receive Noise, Psophometrically
Weighted

-79

dBmOp

DR = lowest positive
decode level

NSF

Single Frequency Noise
End to End Measurement

-50

dBmO

CCITT G.712.4.2
Measure at PWRO +

PSRR,

Vcc Power Supply Rejection,
Transmit Channel

-30

-30

dB

Idle channel; 200mV pop
signal on supply; 0 to
50kHz, measure at Dx

PSRR2

Vee Power Supply Rejection,
Transmit Channel

-30

-30

dB

Idle channel; 200 mV pop
signal on supply; 0 to 50
kHz, measure at Dx

PSRRa

Vcc Power Supply Rejection,
Receive Channel

-25

-25

dB

Idle channel; 200 mV pop
signal on supply; measure
narroW"band at PWRO + ,
oto 50 kHz

-75

-50

14-68

= 11111111

2916 and 2917

NOISE (All receive channel measurements are single ended)
2917

2916
Parameter

Symbol

Min

Typ

Max

Vaa Power Supply Rejection,
Receive Channel

CTTA

Crosstalk, Transmit to Receive

-71

CTRT

Crosstalk, Receive to Transmit

-71

Parameter

Min

Typ

Unit

Test Conditions

dB

Idle channel; 20.0. mV pop
signal on supply; measure
narrow band at PWRO + ,
0. to 50. kHz

-71

dB

Input = DdBmD, Unity
Gain, 1.0.2 kHz, DA =
lowest positive decode
level, measure at PWRO+

-71

dB

DA = DdBmD, 1.0.2 kHz,
measure at Dx

Max

-25

-25

PSRR.

DISTORTION
Symbol

Min

Typ

Max

Unit

Test Conditions

SDl x

Transmit Signal to Distortion, ~-law
Sinusoidal Input;
CCITT G.712-Method 2 (2916)

36
30
25

dB
dB
dB

0. to -3D dBmD
-30 to -40 dBmD
-40. to -45 dBmD

SD2 x

Transmit Signal to Distortion, A-law
Sinusoidal Input;
CCITT G.712-Method 2 (2917)

36
3D
25

dB
dB
dB

Dto -3DdBmD
-30 to -40. dBmD
-40. to -45 dBmD

SD1 A

Receive Signal to Distortion. ~-law
Sinusoidal Input; CCITT G.712-Method
2 (2916)

36
3D
25

dB
dB
dB

0. to -3D dBmD
-3D to -40 dBmD
-40. to -45 dBmD

SD2 R

Receive Signal to Distortion, A-law
Sinusoidal Input; CCITT G.712-Method
2 (2917)

36
3D
25

dB
dB
dB

0. to -3D dBmD
-3D to -40. dBmD
-40. to -45 dBmD

DPx

Transmit Single Frequency Distortion
Products (2916)

-46

dBmD

AT&T Advisory #64 (3.8)
0. dBmD Input Signal

DP A

Receive Single Frequency Distortion
Products (2916)

-46

dBmD

AT&T Advisory #64 (3.8)
0. dBmD Input Signal

IMD,

Intermodulation Distortion,
End to End Measurement

-35

dB

CCITTG.712 (7.1)

IMD2

Intermodulation Distortion,
End to End Measurement

-49

dBmD

CCITT G.712 (7.2)

SOS

Spurious Out 01 Band Signals,
End to End Measurement

-25

dBmD

CCITT G.712 (6.1)

SIS

Spurious in Band Signals,
End to End Measurement

-40.

dBmO

CCITT G. 712 (9)

DAX

Transmit Absolute Delay

245

Dox

Transmit Differential Envelope Delay
Relative to DAX

170.

~s

95
45

~s

10.5
190.

~s

DAR

Receive Absolute Delay

DOR

Receive Differential Envelope Delay
Relative to DAR

45
35
85
110

14-69

~s

~s

~s

~s
~s
~s

~s

Fixed Data Rate. ClK x = 2.0.48
MHz; 0. dBmD, 1.0.2 kHz input
Signal, Unity Gain. Measure
at Dx.

1 = 50.0. - 60.0. Hz
1 = 60.0. - 100.0. Hz
1 = 100.0. - 260.0. Hz
1 = 260.0. - 280.0. Hz
Fixed Data Rate, ClK - 2.0.48
MHz; Digital Input is DMW
codes. Measure at PWRO +
1=
1=
1=
1=

50.0. - 60.0. Hz
60.0 - 100.0. Hz
10.0.0. - 260.0. Hz
2600. - 280.0. Hz

inter

2916 and 2917

TRANSMIT CHANNEL TRANSFER CHARACTERISTICS
Input amplifier is set for unity gain, inverting.
Symbol
GRX

Parameter

Typ

Min

Max

Unit

Test Conditions

o dBmO Signal input at VFxl-

Gain Relative to Gain at 1.02 kHz
16.67 Hz

-30

dB

50 Hz

-25

dB

60 Hz

-23

dB

200 Hz

-1.8

-0.125

dB

300 to 3000 Hz

-0.125

+0.125

dB

3300 Hz

-0.35

+0.03

dB

3400 Hz

-0.7

-0.10

dB

4000 Hz

-14

dB

4600 Hz and Above

-32

dB

,I

mANDW
SCALE

.,

Figure 4. Transmit Channel

14-70

2916 and 2917

RECEIVE CHANNEL TRANSFER CHARACTERISTICS
Symbol
GRR

Parameter

Min

Max

lYP

o dBmO Signal input at DR
+0.125

dB

200 Hz

-0.5

+0.125

dB

300 to 3000 Hz

-0.125

+0.125

dB

3300 Hz

-0.35

+0.03

dB

3400 Hz

-0.7

-0.1

dB

4000 Hz

-14

dB

4600 Hz and Above

-30

dB

Below 200 Hz

EXI'ANOEO
SCALE

+,125dB •. 125<18

200H.

• !'odS

200H.

Test Conditions

Unit

Gain Relative to Gain at 1.02 kHz

lOOH.

/ -.12Sd8
JOOOH.

/ -.125<18
300Hz

Figure 5. Receive Channel

14-71

2916 and 2917

A.C. CHARACTERISTICS- TIMING PARAMETERS
CLOCK SECTION
Symbol

Parameter

Typ

Min

Max

lev

488

ns

IcLK

Clock Pulse Width, ClK

220

ns

tDCLK

Data Clock Pulse Width

220

IcDC

Clock Duly Cycle, ClK

45

~, ~

Clock Rise and Fall Time

5

ns

50

Test Conditions

Unit

Clock Period, ClK

55

%

30

ns

Max

Unit

145

ns

fCLK

= 2.048 MHz

64 kHz .. f DCLK .. 2.048 MHz

TRANSMIT SECTION, FIXED DATA RATE MODEl
Symbol

Parameter

Min

Typ

Test Conditions

0< CLOAD < 100 pf
0< CLOAD < 100 pf

tDzx

Data Enabled on TS Entry

tDDX

Data Delay from ClK

0

145

ns

tHZX

Data Float on TS Exit

60

215

ns

tSON

Timeslot X to Enable

0

145

ns

CLOAD = 0
0< CLOAD < 100 pf

tSOFF
tFSD

Tlmeslot X to Disable

60

215

ns

CLOAD

Frame Sync Delay

100

lcy-l00

ns

Max

Unit

0

=0

RECEIVE SECTION, FIXED DATA RATE MODE
Symbol

Parameter

Min

!oSR

Receive Date Setup

!oHR
tFSD

Receive Date Hold

60

Frame Sync Delay

100

Typ

ns

10

ns

lev-l00

NOTES:
1. Timing parameters tozx, tHZX, and tSOFF are referenced to a high Impedance state.

14-72

ns

Test Conditions

2916 and 2917

WAVEFORMS
Fixed Data Rate Timing
TRANSMIT TIMING

~
Fs:'j
i IFSO
I,
I,
.
tCLK

elK

1

2

3

4

5

6

7

8

NOTE: ALL TIMING PARAMETERS REFERENCED TO VIH AND VIL EXCEPT tozx. tSOFF AND tHzx WHICH
REFERENCE A HIGH IMPEDANCE STATE

RECEIVE TIMING

NOTE: ALL TIMING PARAMETERS REFERENCED TO V1H AND V1Lo

14-73

inter

2916 and 2917

TRANSMIT SECTION, VARIABLE DATA RATE MODEl
Typ
Symbol
Parameter
Min
tTsoX

Max

Unit

Timeslot Delay from DCLKl

140

tox -140

ns

Frame Sync Delay

Test Conditions

100

icy-lOO

ns

toox

Data Delay from DCLKx

0

100

ns

0< ClOAO < 100 pf

tOON

Timeslot to Ox Active

0

50

ns

0< CLOAO < 100 pf

tOOFF

Timeslot to Ox Inactive

0

80

ns

0< ClOAO < 100 pf

tox

Data Clock Period

488

15620

ns

tOFSX

Data Delay from FS x

0

140

ns

t FSO

RECEIVE SECTION, VARIABLE DATA RATE MODE
Typ
Symbol
Parameter
Min

Max

Unit

tTsOR

Timeslot Delay from DCLKR3

140

toR -140

ns

tFSO

Frame Sync Delay

100

icy- 1OO

ns

tOSR

Data Setup Time

10

tOHR

Data Hold Time

60

tOR

Data Clock Period

488

tSER

Timeslot End Receive Time

60

Test Conditions

ns
ns
15620

ns
ns

64 KB OPERATION, VARIABLE DATA RATE MODE
Typ
Symbol
Min
Parameter

Max

Unit

Test Conditions

tFSLX

Transmit Frame Sync Minimum
Downtime

488

ns

FSx is TTL high for remainder of
frame

tFSlR

Receive Frame Sync Minimum
Downtime

1952

ns

FS R is TTL high for remainder of
frame

tOClK

Data Clock Pulse Width

10

NOTES:
I. Timing parameters tOON and tOO~F are referenced to a high impedance state.

2. tFsLX minimum requirements overrides ITSOX maximum spec for 64 kHz operation.
3. tFSlR minimum requirements overrides tTSOR maximum spec for 64 kHz operation.

14-74

J1S

2916 and 2917

VARIABLE DATA RATE TIMING
TRANSMIT TIMING
FSx

--4--'

RECEIVE TIMING

NOTE: ALL TIMING PARAMETERS REFERENCED TO V1H AND V1l EXCEPT
lOON AND tOfF WHICH REFERENCE A HIGH IMPEDANCE STATE

A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUT/OUTPUT

2.4=X
.

0.45

2.0

.

2.0

>TEST POINTS<
0.8

x=
.

0.8

A.C. TESTING: INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC M1" and O.4SV FOR A
LOGIC "0", TIMING MEASUREMENTS ARE MADE AT2.0YFOR A LOGIC "'" AND
a.BV FOR A LOGIC "0",

14-75

29C13 AND 29C14
CHMOS COMBINED SINGLE-CHIP PCM CODEC AND FILTER
• 29C14 Asynchronous clocks, 8th bit
signaling, loop back test capability
• 29C13 Synchronous clocks only, 300 mil
package
• Low-Power Pin Compatible Version of
Intel's 2913 and 2914
• AT&T 03/04 and CCITT Compatible
• 28-Pin Plastic Leaded Chip Carrier
(PLCC) for Higher Integration

• 3 Low-Power Modes
-5 mW Typical Power Down
-8 mW Typical Standby
-70 mW Typical Operating
• Direct Interface with Transformer or
Electronic Hybrids
• TTL and CMOS Compatible

Intel's 29C13 and 29C14 are CHMOS versions of Intel's HMOS 2913 and 2914 family members. CHMOS is
a technology built on HMOS-II, thus realizing the high performance and density obtained in that process while
achieving the low power consumption typical of CMOS circuits.
The 29C13 and 29C14 retain all the features of the 2913 and 2914: push/pull power amplifiers, JJiA law pin
select, on-chip auto zero, sample and hold and precision voltage references, power up clear and tri-state on
clock interrupt, two timing modes and two power down modes.

~

0

I

~
~::n<
~
+
n
GI

)<

v"
v..

PWRO+

PWRO+

GS,

PWRO-

VFxl -

Gs,

YFlCl

PDN

GRDA

+

CLKSEL

DCLK..

TSx/DCLKx

0,

PWRO-

VFxl-

GS,

VFxl+

PDN

GRDA

CLKSEL

NC

Ne
PDN

LOOP

SIGx/ASEL

CLKSEL

SIGR

TSxfDCLK x

LODP

DCLK R
FS,

0,

0,

SIG..

FS,

DCLK R

FS,

CLK x

GRDD

eLKR

YFxl-

Ne

Gs,

SIGxfASEL

DR

NC

;.

Figure 1.

Pin Configurations

14-76

C)

:II

0

,..

n

...

C ... '"
o
· •

'TI

UJ
)C

29C13 and 29C14

XMIT
SECTION

AUTO
ZERO

l

YFxl-tVFxl -

GSx

---- tt>rlii l

J

REFERENCE

SAMPLE
AND HOLD
AND OAe

-

I
COMPARATOR

L

1

I-

SUCCESSIVE
APPROXIMATION

REGISTER

-

I

ANALOG
TO

IOUTPUT

REGISTER

II-

---

-

f

DIGITAL
CONTROL
lOGIC

Dx
TSxlDCLKX
SIGx/ASEL

FSx
CLKx

t

GSA

I

CONTROL
SECTION

RCV
SECTION

-- ~ Ci:

CONTROL

LoaiC

SET

.-{

BUFFER

I

!----,

I-

DIGITAL
PWRO+

PWRO-

SAMPLE
AND HOLD
AND OAe

<:]-

I-

TO
ANALOG

CONTROL

r--

INPUT

REGISTER

LOGIC

REFERENCE

J

Vee

Figure 2.

~

~ -==
I-

I

-

CLKSEL

JfIlll
LOOP

DA

DClKR

J .1 . .1
Yea

GRDO

GRDA

Block Diagram

Table 1. Pin Names
Vee
PWRO +, PWROGS R
PDN
CLKSEL
LOOP
SIG R
DCLKR
DR
FS R
GRDD
Vee

Power (-5V)
Power Amplifier Outputs
Receive Gain Control
Power Down Select
Master Clock Frequency
Select
Analog Loop Back
Receive Signaling Bit Output
Receive Variable Data Clock
Receive PCM Input
Receive Frame
Synchronization Clock
Digital Ground
Power (+5V)

14-77

GS x
VFxl-, VFxl +
GRDA
NC
SIG x

Transmit Gain Control
Analog Inputs
Analog Ground
No Connect
Transmit Signaling Input

ASEL
TS x
DCLKx
Dx
FS x

W or A-law Select
Timeslot Strobe/Buffer Enable
Transmit Variable Data Clock
Transmit PCM· Output
Transmit Frame
Synchronization Clock
Transmit Master Clock
Receive Master Clock (29C14
only, internally connected
to CLKx on 29C13)

CLKx
CLKR

intJ

29C13 and 29C14
Table 2. Pin Description

Symbol

Function

Symbol

Function

Vee

Most negative supply; Input voltage is - 5
volts ± 5%.

GRDD

Digital ground for all internal logic circuits.
Not internally tied to GRDA. '

PWRO+

Non-inverting output of power amplifier.
Can drive transformer hybrids or high
Impedance loads directly in either a differential or single ended configuration.

CLKA

Receive master and data clock for the
fixed dataratEi mode; receive master clock
only in variable data rate mode.

PWRO-

CLKx

Inverting output of 'power amplifier. Functionally Identical and complementary to
PWRO+.

Transmit master and data clock for the
fixed data rate mode; transmit master
clock only in variable data rate mode.

FSx

GSA

Input to the gain setting network on the.
output power amplifier. Transmission level
can be adjusted over a 12dB range de-:
pending on the voltage at GSA'

PDN

Power down select. When PDN is TIL
high, the device is active. When low, the
device is powe~d down.

8 KHz frame synchronization clock input!
timeslot enable, transmit channel. Operates independently but in an analogous
manner to FS A.
The transmit channel enters the standby
state whenever FSx is TTL low for 300 milliseconds.

Dx

CLKSEL ,

Input which must be pinstrapped to reflect
the master clock frequency at CLKx, CLKA.
.. .2.048 MHz
CLKSEL = Vee' ..
CLKSEL =GRDD . .. . . . . 1.544 MHz
QLKSEL = Vee' ... , ..•. 1.536 MHz

Transmit PCM output. PCM data is clocked
out on this lead on eight consecutive positive transitions of the transmit data clock:
CLKx In fixed data rate mode and DCLKx
In variable data rate mode.

LOOP

Analog loopback. When this pin is TIL
high, the analog output (PWRQ +) is
internally connected to the analog input
(VFxl +), GSA is internally connected to
PWRO -, and VFxl- Is Internally connected to GSx. A OdBmO digital signal input at DA is returned as a + 3dBmO digital
signal output at Dx.

SIG A

Signaling bit output, receive channel. In
fixed, data rate mode, SIG Aoutputs the logIcal state of the eighth bit" of the PCM word
In the most recent signaling frame,

DCLKA

Selects the fixed or variable data rate
mode. When DCLKA is connected to Vee,
the fixed data rate mode is selected: In
this mode, the device Is fully compatible
with Intel 2910A and 2911A direct mode
timing. When DCLK Ais not connected to
Vee,thedeviceoperates in the variable
data rate mode. In this mode DCLKAbecoines the receive data clock which operates at TJL levels from 64Kb to 2.048 Mb
data rates.

DA

FSA
"

TSx/DCLKx Transmit channeltimeslot strobe (output)
or data clock (input) for the transmit channel. In fixed data rate modEi, this pin is an
open drain output designed to be used as
an enable signal for a three-state buffer as
in 2910A and 2911A direct mode timing. In
variable data rate mode, this pin becomes
the transmit data clock which operates at
TTL levels from 64Kb to 2.048 Mb data
rates.
SIGx/ASEL A dual purpose pin. When connected to
Vee' A-law operation is selected. When it is
not connected to Ves this pin is a TTL level
input for signaling operation. This input is
transmitted as the eighth bit of the PCM
word during signaling frames on the Dx
lead, If not used as an input pin, ASEL
should be strapped to either Vee or GRDD.
NC

No connect

GRDA

Analog ground return for all internal voice
circuits. Not internally connected to GRDD.

VFxl+

Non-inverting analog input to uncommitted
transmit operational amplifier.

Receive PCM input. PCM data is clocked
In on this lead on eight consecutive negative transitions of the.receive data clock;
CLKA in the fixed data rate mode and
DCLKA in variable data rate mode.

VFxl- .

Inverting analog input to uncommitted
transmit operational amplifier.

GSx

Output terminal of transmit input channel
op amp. Internally, this is the voice signal
Input to the transmit filter.

8KHz frame synchronization clock input!
timeslo! enable, receive channel. A multifunction input which in fixed data rate
mode distinguishes between signaling and
non-signaling frames by means of a double or single wide pulse respectively. In
variable data rate mode this signal must
remain high for the entire 'length of the
timeslot The receive channel enters the
standby state whenever FS R is TTL low for
300 milliseconds.

V '

Most positive supply; input voltage is + 5
volts ±5%,

cc

14-78

inter

29C13 and 29C14

FUNCTIONAL DESCRIPTION

The following major functions are provided:

The 2913 and 2914 provide the analog-to-digital and
the digital-to-analog conversions and the transmit and
receive filtering necessary to interface a full duplex
(4 wires) voice telephone circuit with the PCM highways of a time division multiplexed (TOM) system.
They are intended to be used at the analog termination of a PCM line or trunk.

• Bandpass filtering of the analog signals prior to
encoding and after decoding
• Encoding and decoding of voice and call progress information
• Encoding and decoding of the signaling and supervision information

SWITCHING

p;:x7c:;;: ;;';;;;~;;S;ST-;M-

r:,

-

-

-- -

r----------------------

~-;S;;;;;-

-

I

HIGHWAYS

I
I
I
I ...-""---,
I SUPERVISIO
,

-

CONTROL HIGHWAYS

I
I
I
I
I

OFF·HOOK/ROTARY DIAL PULSES

PROTEcnON

I

29C13
OR
BAnERY
FEED

HYBRID. .- - - - - I

COMBO

2W/4W I------II~

I

I
I
I

,,
L _____________________ _
,

OFF·HOOK/ROTARY DIAL PULSES
SUPERVISION
PROTECTION

BAnERY
FEED

29014

I

PABX/C.O. SWITCHING SYSTEM

I
I

RINGING

RING CONTROL

29014
COMBO

HYBRID~-----l

RINGING
RING CONTROL

L _________________P'="M.!!I~~!!
FUNCTIONAL BLOCK DIAGRAM OF A LINE
CIRCUIT WITH BORROWED 81h BIT
'
SIGNALING

FUNCTIONAL BLOCK DIAGRAM OF A LINE
CIRCUIT WITH SEPARATE SIGNALING/
CONTROL HIGHWAYS

,CHANNEL BANKS

I
~I~

~I
SIGNALING
LEADS
TO LOCAL
CENTRAL
OFFICE

FNNEluNiT-- -- ------

TO DISTANT
CENTRAL OFFICE

HANNELuNiT -

/

---

-

-.I::G~~__~
___

I

I
I

I
___.JI

~

29C14
COMBO

~'------"-~~,..J

I
SIGNAL-IN-G-t---o-l
LEADS

S~~:t~::sG

SIGNALING
STROBES

A TYPlCAL4·WIRE CHANNEL UNIT WITH
SIGNALING USING BORROWED 81h BIT

Figure 3.

Typical Une TermlnaUons

14-79

I

I
I
I
I

.
L_________
-.J·I

-TO LOCAL
CENTRAL
OFFICE

A TYPICAL CCITT CHANNEL UNIT

TO DISTANT
CENTRAL
OFFICE

I

-I

I
I

I

inter

29C13 and 29C14

GENERAL OPERATION

the device, are enabled in these modes. As shown
In Table 3, the digital outputs on the appropriate channels' are placed In a high Impedance state until the
device returns to the active mode.

System Reliability Features
The combochip can be powered up by pulsing FSx
and/or FS R while a TTL high voltage is applied to
PDN, provided that all clocks and supplies are connected. The 29C13 and 29C14 have internal resets
on power up (or when Vee or Vccare re-applied) in
order to ensure validity of the digital outputs and
thereby maintain integrity of the PCM highway.

The Power Down mode utilizes an external control
signal to the PON pin. In this mode, power consumption is reduced to the value shown in Table 3.
The device is active when the signal is high and inactive when it is low. In the absence of any Signal,
the PON pin floats to TTL high allowing the device to
remain active continuously.

On the transmit channel, digital outputs Dx and TSx
are held in a high impedance state for approximately
four frames (5001lS) after power l!Q..or application of
Vee or Vcc. After this delay, Ox, TSx, and signaling
will be functional and will occur in the proper timeslot.
The analog circuits on the transmit side require approximately 60 milliseconds to.reach their equilibrium
value due to the autozero circuit settling time. Thus,
valid digital information, such as for on/off hook detection, is available almost Immediately, while analog
information is available after some delay.

The Standby mode leaves the user an option of powering either channel down separately or powering the
entire device down by selectively removing FS and/
or FS R• With both channels in the standby state,
power consumption is reduced to the value shown in.
Table 3. If transmit only operation is desired, FSx
should be applied to the device while FS R is held low.
Similarly, if receive only operation is desired, FS R
should be applied while FSx is held low.

x

Fixed Data Rate Mode
On the receive 9hannel, the digital output SIG R is also
held low for a maximum of four frames after power
up or application of Vee or Vcc. SIG R will remain low
thereafter until it is updated by a signaling frame.

Fixed data rate timing, which is 2910A and 2911 A
compatible, is selected by connecting OCLKR to Vee'
It employs master clocks CLKx arid CLK R, frame synchronization clocks FS x and FS R, and output TS x. ,

To further enhance system reliability, TS x and Ox will
be placed in a high impedance state approximately
3011S after an interruption of CLKx ' Similarly, SIG R
will be 'held low approximately 3011S after an interruption of CLKR • These interruptions could possibly
. occur with some kind of fault condition.

Power Down and StandbY.Modes
To minimize power consumption, two power down
modes are provided in which most 29C13/C14 functions are disabled. Only the power down, clock, and
frame sync buffers, which are required to power up

CLKx and CLKR serve both as master clocks to .operate the codec and filter sections and bit clocks to
clock the data in and out from.the PCM highway. FSx
and FS R are 8 kHz inputs which set the sampling
frequency and distinguish between Signaling and
non-signaling frames by their pulse width. A frame
synchronization pulse which is one master clock wide
designates a non-signaling frame, while a double
wide sync pulse enables the signaling function. TS x
is a timeslot strobe/buffer enable output which gates·
the PCM word onto the PCM highway when an external buffer is used to drive the line.

Table 3. Power-Down Methods

Device Status

Power-Down
Method

Typical
Power
Consumption

Digital Output Status
TS x and Ox are placed in a high impedance
state and SIG R is placed in a TIL low state
within 10 ILS
TS x and Ox are placed in a high imped,lnce
state and SIG R is placed in a TIL low state
300 milliseconds after FS x and FS R are
removed.

Power Down Mode

PDN = TTL low

5mW

Standby Mode

FS x and FS R are TTL low

BmW

Only transmit is
on standby

FS x is TTL low

50mW

TS x and Ox are placed in a high impedance
state within' 300 milliseconds.

FS R is TTL low

50mW

SIG R is placed In a TIL low state within
300 milliseconds.

. Only receive is
on standby

14-80

inter

29C13 and 29C14

Data is transmitted on the highway at Ox on the first
eight positive transitions of CLKx following the rising
edge of FS x. Similarly, on the receive side, data is
received on the first eight falling edges of CLKR. The
frequency of CLKx and CLKR is selected by the
CLKSEL pin to be either 1.536, 1 .544, or 2.048 MHz.
No other frequency of operation is allowed in the fixed
data rate mode.

as DCLKx is pulsed and FS x is held high. This feature
allows the PCM word to be transmitted to the PCM
highway more than once per frame, if desired, and is
only available in the variable data rate mode. Conversely, signaling is only allowed in the fixed data rate
mode since the variable mode provides no means
with which to specify a signaling frame.

Signaling
Variable Data Rate Mode
Signaling can only be performed with the 24-pin device in the fixed data rate timing mode (DCLKR =
Vee). Signaling frames on the transmit and receive
sides are independent of one another and are selected by a double-width frame sync pulse on the
appropriate channel. During a transmit signaling
frame, the codec will encode the incoming analog
signal and substitute the Signal present on SIG x for
the least significant bit of the encoded PCM word.
Similarly, in a receive signaling frame, the codec will
decode the seven most significant bits according to
CCITT recommendation G.733 and output the logical
state of the LSB on the SIG R lead until it is updated
in the next signaling frame. Timing relationships for
signaling operation are shown in Figure 4.

Variable data rate timing is selected by connecting
DCLKR to the bit clock for the receive PCM highway
rather than to Vss. It employs master clocks CLKx
and CLKR, bit clocks DCLK R and DCLKx, and frame
synchronization clocks FS R and FS x.
Variable data rate timing allows for a flexible data
frequency. It provides the ability to vary the frequency
of the bit clocks, which can be asynchronous in the
case of the 29C14, synchronous in the case of the
29C13, from 64 kHz to 2.048 MHz. Master clocks
inputs are still restricted to 1.536, 1.544, or 2.048
MHz.
In this mode, DCLKR and DCLKx become the data
clocks for the receive and transmit PCM highways.
While FS x is high, PCM data from Ox is transmitted
onto the highway on the next eight consecutive positive transitions of DCLKx' Similarly, while FS Ris high,
each PCM bit from the highway is received by DR on
the next eight consecutive negative transitions of
DCLKR·

Asynchronous Operation
The 29C14 can be operated with asynchronous
clocks in either the fixed or variable data rate modes.
In order to avoid crosstalk problems associated with
special interrupt circuitry, the design of the Intel
29C13/C14 combochip includes separate digital-toanalog converters and voltage references on the
transmit and receive sides to allow independent operation of the two Channels.

On the transmit side, the PCM word will be repeated
in all remaining times lots in the 125/LS frame as long

CLKX

t

J

DX=~==============~SIGX===

TSi~

c'

It'

-

SIGx --------------~----D-N.-A-------~-~-~
_____________
= __ _
D~~ARE
-,>- ___

Qt~'i&.

_____ _ . ' _ - " - - - - - - - - -

DR =~:_=====:::___--=-=_==:==~==
SIGR
;:
'. ~YALUE
Figure 4.

Signaling TIming (Used Only with Fixed Data Rate Mode)

14-81

inter

29C13 and 29C14

In either timing mode, the master clock, data clock,
and timeslot strobe must be synchronized at the beginning of each frame. CLKx and DCLKx are synchronized once per frame but may be of different
frequencies. The receive channel operates in a similar manner and is completely independent of the
transmit timing (refer to Variable Data Rate Timing
Diagrams). This approach requires the provision of
two separate master clocks, even in variable data rate
mode, but avoids the use of a synchronizer which can
cause intermittent data conversion errors.

brated during the manufacturing process. These
references determine the gain and dynamic range
characteristics of the device.
Separate references are supplied to the transmit and
receive sections and each is trimmed independently
during the manufacturing process. The reference
value is then further trimmed in the gain setting opamps to a final precision value. With this method the
combochip can achieve the extremely accurate Digital Milliwatt Responses specified in the TRANSMISSION PARAMETERS, providing the user a significant
margin for error in other board components.

Analog Loopback
A distinctive feature of the 29C14 is its analog loopback capability. This feature allows the user to send
a control signal which internally connects the analog
input and output ports. As shown in Figure 5, when
LOOP is TTL high the analog output (PWRO +) is
internally connected to the analog input (VFxl + ), GSR
is internally connected to PWRO -, and VFxl- is
internally connected to GSx.
With this feature, the user can test the line circuit
remotely by comparing the digital codes sent into the
receive channel (DR) with those generated on the
transmit channel (Dx). Due to the difference in trans- .
mission levels between the transmit and receive
sides, a 0 dBmO code. sent into DR will emerge from
Dx as a + 3dBmO code, an implicit gain of 3 dB. Thus,
the maximum signal input level which can be tested
using analog loopback is 0 dBmO.

Precision Voltage References
No external components are required with the combochip to provide the voltage reference function. Voltage references are generated on-Chip and are cali-

Conversion Laws
The 29C13 and 29C14 are designed to operate in
both wlaw and A-law systems. The user can select
either conversion law according to the voltage present
on the SIGxlASEL pin. In each case the coder and
decoder process a companded 8-bit PCM word following CCITT recommendation G.711 for wlaw and
A-law conversion. If A-law operation is desired, SIG x
should be tied to Vee. Thus, signaling is not allowed
during A-law operation. If JL = 255-law operation is
selected, then SIG x is a TTL level input which modifies the LSB of the PCM output in signaling frames.

TRANSMIT OPERATION
Transmit Filter
The input section provides gain adjustment in the
passband by means of an on-chip uncommitted operational amplifier. This operational amplifier has a
common mode range of ± 2.17 volts, a DC offset of
25 mV, and a typical voltage gain of 20,000. Gain of

--------------------------,

I--LOOP

I
I

1

TRANSMIT
VOICE

Dx l

1
1

~~TIZED

~~~:O~~~K

1
1
1
I
PWRO+

4--'--.....,...-""+1

PWRO-

+-:_"""""'...:

DR I

DIGITIZED
PCM
. TEST
I TONE

I

1
I

'I
COMBOCHIP ANALOG LOOP BACK FUNCTION

Figure 5. Simplified Block Diagram of 29C14 Combochlp In the Analog Loopback Configuration

14-82

inter

29C13 and 29C14

up to 20 dB can be set without degrading the performance of the filter. The load impedance to ground
(GRDA) at the amplifier output (GS x) must be greater
than 10 kilohms in parallel with less than 50 pF. A DC
path must be provided at VFxl +. The input op amp
can also be used in the inverting mode or differential
amplifier mode (see Figure 6).

transmit filter and holds each sample on an internal
sample and hold capacitor. The encoder then performs an analog to digital conversion on a switched
capacitor array. Digital data representing the sample
is transmitted on the first eight data clock bits of the
next frame.
An on-Chip autozero circuit corrects for DC-offset on
the input Signal to the encoder. This autozero circuit
uses the sign bit averaging technique; the sign bit
from the encoder output is long term averaged and
subtracted from the input to the encoder. In this way,
all DC offset is removed from the encoder input
waveform ..

A low pass anti-aliasing section is included on-Chip.
This section typically provides 35 dB attenuation at
the sampling frequency. No external components are
required to provide the necessary anti-aliasing function for the switched capacitor section of the transmit
filter.
The passband section provides flatness and stopband attenuation which fulfills the AT&T 03/04
channel bank transmission specification and CCITT
recommendation G.712. The 29C13 and 29C14
specifications meet or exceed digital class 5 central
office switching systems requirements. The transmit
filter transfer characteristics and specifications will be
within the limits shown in Figure 8.
A high pass secti!?n configuration was chosen to reject low frequency noise from 50 and 60 Hz power
lines, 17 Hz European electric railroads, ringing frequencies and their harmonics, and other low frequency noise. Even though there is high rejection at
these frequencies, the sharpness of the band edge
gives low attenuation at 200 Hz. This feature allows
the use of low-cost transformer hybrids without external components.

RECEIVE OPERATION
Decoding
The PCM word at the DR lead is serially fetched on
the first eight data clock bits of the frame. A DIA
conversion is performed on the digital word and the
corresponding analog sal'T)ple is held on an internal
sample and hold capaCitor. This sample is then transferred to the receive filter.

Receive Filter

Encoding

The receive filter provides passband flatness and
stopband rejection which fulfills both the AT&T 03/04
specification and CCITT recommendation G.712.
The filter contains the required compensation for the
(sin x)/x response of such decoders. The receive ·fiIter characteristics and specifications are shown in
Figure 9.

The encoder internally samples the output of the

Receive Output Power Amplifiers

VFxl+

r....

VF,I-

A balanced output amplifier is provided in order to
allow maximum flexibility in output configuration.
Either of the two outputs can be used single ended
(referenced to GRDA) to drive single ended loads.
Alternatively, the differential output will drive a bridged
load directly. The output stage is capable of driving
loads as low as 300 ohms single ended or 600 ohms
differentially.
GAINa1

+-:;

GS,

R.
R,

Figure 6.

Transmit Filter Gain Adjustment

The receive channel transmission level may be adjusted between specified limits by manipulation of the
GSR input. GSR Is internally connected to an analog
gain setting network. When GSR is strapped to
PWRO-,'the receive level is unattenuated; when it
is tied to PWRO +, the level is attenuated by 12 dB.
The output transmission level interpolates between 0
and - 12 dB as GSR is interpolated (with a potentiometer) between PWRO + and PWRO -. The use
of the output gain set is illustrated in Figure 7.
Transmission levels are specified relative to the re14-83

inter

29C13 and 29C14

Table ... Zero Transmission Level Points
Value

UnHs

OTLP1 x

Zero Transmission Level Point
Transmit Channel (OdBmO) wlaw

+2.76
+1.00

dBm
dBm

Referenced to 600n
Referenced to 900n

OTLP2x

Zero Transmission Level Point
Transmit Channel (OdBmO) A-law

+2.79
+1.03

dBm
dBm

Referenced to 600n
Referenced to 900n

OTLP1 R '

Zero Transmission Level Point
Receive Channel (OdBmO) /I.-law

+5.76
+4.00

dBm
dBm

Referenced to 600n
Referenced to 900n

, OTLP2R

Zero Transmission Level Point
Receive Channel (OdBmO) A-law

+5.79
+4.03

dBm
dBm

Referenced to 600n
Referenced to 900n

Symbol

Parameter

ceive channel output under digital milliwatt conditions,
that is, when the digital input at DAiS the eight-code
sequence specified in CCITT recommendation G.711.

Test Conditions

A is the gain of the power amplifiers,

OUTPUT GAIN SET: DESIGN
CONSIDERATIONS

For design purposes, a useful form is Al/A2 as a
'function of A.

(Refer to Figure 7.)
PWAO + and PWAO - are low impedance complementary outputs. The VOltages at the nodes are:

Al/A2 =

(Allowable values for A are those which make A/A2
positive.)
Examples are:
If A= 1 (maximum output), then

Vo+ at PWAO+
Vo- at PWAOVo = (Vo +) - (Vo - )(total differential response)

Rl arid A2 are a gain setting resistor network with the
center tapc::onnected to the GSA input.

Ai/A2=ao or V(GSA)=Vo-; i.e., GSA is tied to
PWAO- '

A value greater than 10K ohms for Al + A2 and less
than 100K ohms for Al in parallel with A2 is recommended because: '
(a) The parallel combination of Al + A2 and AL sets
the total loading.
(b) The total capacitance at the GSA input and the
parallel combination of Al and A2 define a time,
constant which has to be minimized to avoid inaccuracies.

®
AL

±.1
-.

~

Yo

If A = %, then'
Al/A2=2
If A = %, (minimum output) then
Al /A2=O or V(GSA)=Vo+;
PWAO+

PWRO+

'R,

0

He13
OR

GS.

29C14

R.

I

®

4A - 1

"'1=A

D. - - - - ,
PWRO-

DIGITAL INPUT

v.-

i

-=1-

Figure 7.

Gain Setting Configuration

14-84

i.e~,

GSA is tied to

inter

29C13 and 29C14

ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias . . . . . .
Storage Temperature . . . . . . . .
Vcc and GRDD with Respect to VBB .
All Input and Output Voltages
with Respect to VBB' . . . .
All Input and Output Voltages
with Respect to Vcc'
Power Dissipation. . . . . . .

. -10°C to + 80°C
. -6SoC to +1S0°C
-0.3V to 1SV
-0.3V to 1SV
-1SV to +0.3V
. . . . . 1.3SW

*NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated
in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

D.C. CHARACTERISTICS
(TA = O°C to 70°C, Vee = +SV :tS%, Vee = -SV :tS%, GRDA = OV, GRDD = OV, unless otherwise specified)
Typical values are for TA = 2S0C and nominal power supply values

DIGITAL INTERFACE
Symbol

Parameter

Max

Unit

10

JJ-A

GRDD .;;; VIN .;;; VIL (Note 1)

High Level Input Current

10

JJ-A

VIH .;;; VIN .;;; Vcc

Input Low Volage, except CLKSEL

0.8

V

IlL

Low Level Input Current

IIH
VIL

Min

Typ

VIH

Input High Voltage, except CLKSEL

VOL

Output Low Voltage

VOH

Output High Volage

2.4

VILa

Input Low Voltage, CLKSEL2

VBB

VBB
+O.S

V

VIIO

Input Intermediate Voltage, CLKSEL

GRDD
-O.S

O.S

V

VIHO

Input High Voltage, CLKSEL

Vcc
-0.5

VcVc

V

10

PF

Max

Unit

2.0

V
0.4

Cox

Digital Output Capacitance"

5

CIN

Digital Input Capacitance

5

POWER DISSIPATION
All measurements made at
Symbol

fOCLK =

Parameter

Test Conditions

V

10L = 3.2 mA at Dx, TSx and
SIG R

V

10H '" 80 pA at Dx, SIG R

pF

2.048 MHz, outputs unloaded.
Min

Typ

Test Conditions

Icci

Vcc Operating Current

5.6

mA

IBBI

VBB Operating Current

-5.6

mA

Icco
IBBo

Vec Power Down Current

0.5

mA

PDN .;;; VIL ; after 10JJ-s

VBB Power Down Current

-0.5

mA

IxCcs

Vcc Standby Current

0.8

mA

PDN .;;; VIL ; after 10JJ-s
FS x, FS A .;;; VIL; after 300 ms

IBBs

VBB Standby Current

-0.8

mA

FS x, FS R .;;; VIL ; after 300 ms

P~I

Operating Power Dissipation 4

70

mW

PDO

Power Down Dissipation 4

5

mW

PDN .;;; VIL; after 10JJ-s

PST

Standby Power Dissipation 4

8

mW

FS x, FS R .;;; VIL

NOTES:

1. VIN Is the voltage on any digital pin.
2. SIG x and DClK A are TTL level inputs between GRDD and Vcc; they are also pinstraps lor mode selection when tied to VBS'
Under these conditions VILO is the input low voltage requirement.
3. Timing parameters are guaranteed based on a 100 pi load capacitance. Up to eight digital outputs may be connected to a common PCM highway without buffering, assuming a board capacitance 01 60 pl.
4. With nominal power supply values.

14-85

intJ

29C13 and 29C14

ANALOG INTERFACE, TRANSMIT CHANNEL INPUT STAGE
Symbol
laxl

Parameter

Min

Typ

Input Leakage Current, VFicl +, VFxl-

R,x,

Input Resistance, VFxl +, VFxl-

Max

Unit

100

nA

10

MO
25

VOSX1

Input Offset Voltage, VFxl +, VFxl-

CMRR

Common Mode Rejection, VFxl +, VFxl-

AvoL

DC Open Loop Voltage Gain, GSx

fe

Open Loop Unity Gain Bandwidth, GS x

CLX1

Load Capacitance, GSx

RLXI

Minimum Load Resistance, GSx

Test Conditions
-2.17V.;; V ,N .;; 2.17V

mV
dB

55

-2.17';; V,N .;; 2.17V

5000
1

MHz
50

pF

10

kO

ANALOG INTERFACE, RECEIVE CHANNEL DRIVER AMPLIFIER STAGE
Symbol

Parameter

Min

Typ

Max

Unit

Output Resistance, PWRO +, PWRO-

VOS AA

Single-Ended Output DC Offset, PWRO +,
PWRO-

CLRA

Load Capacitance, PWRO+, PWRO-

Test Conditions

0

1

RORA

75

±150

mV

100

pF

Relative to GRDA

A.C. CHARACTERISTICS - TRANSMISSION PARAMETERS
Unless otherwise noted, the analog input is a 0 dBmO, 1020 Hz sine wave.! Input amplifier is set for unity gain,
noninverting. The digital input is a PCM bit stream generated by passing a 0 dBmO, 1020 Hz sine wave through
an ideal encoder. Receive output is measured single ended, maximum gain configuration. 2 All output levels
are (sin x)/x corrected.

GAIN AND DYNAMIC RANGE
Symbol

Parameter

Min

Typ

. Max

Units

EmW

Encoder Milliwatt Response
(Transmit gain tolerance)

-0.18

±0.04

+0.18

dBmO

EmWrs

EmW variation with Temperature
and supplies

-0.07

±0.02

+0.07

dB

DmW

Digital Milliwatt Response
(Receive gain tolerance)

-0.18

:±:0.04

+0.18

dBmO

DmWrs

DmW variation with temperature and
supplies

-0.07

±0.02

+0.07

dB

Test Conditions
Signal input of 1.064 Vrms wlaw
Signal input of 1.068 Vrms A-law
TA = 25°C, Vee = -5V,
Vee = +5V
± 5% supplies, 0 to 70°C
Relative to nominal conditions
Measure relative to OTLP A • Signal
input per CCITT Recommendation
G.711. Output signal of 1000 Hz.
TA = 25°C; Vee = -5V,
Vee = +5V. RL = 0:
± 5% supplies, 0 to 70°C

NOTES:
1. OdBmO is defined as the zero reference pOint of the channel, under test (OTLP). This corresponds to an analog signal input of 1.064 volts rms
or an output of 1.503 volts rms for ,.daw.
2. Unity gain input amplifier: GS x is connected to VFxl-, Signal input VFxl + ; Maximum gain output amplifier; GSA is connected to PWRO -,
output to PWRO + .

14-86

29C13 and 29C14

GAIN TRACKING
Reference Level = - 10dBmO
Max

Unit

GT1 x

Transmit Gain Tracking Error
Sinusoidal Input; Wlaw

±0.25
±0.5
±1.2

dB
dB
dB

+3 to -40 dBmO
-40 to -50dBmO
-50 to -55 dBmO

GT2x

Transmit Gain Tracking Error
Sinusoidal Input; A-law

±0.25
±0.5
± 1.2

dB
dB
dB

+3 to -40 dBmO
-40 to -50 dBmO
-50 to -55 dBmO

GT1 R

Receive Gain Tracking Error
Sinusoidal Input; ,u-Iaw

±0.25
±0.5
±1.2

dB
dB
dB

+3 to -40 dBmO
-40 to -50dBmO
-50 to -55 dBmO
Measured at PWRO + ,
RL = 300n

GT2R

Receive Gain Tracking Error
Sinusoidal Input; A-law

±0.25
±0.5
±1.2

dB
dB
dB

+310 -40dBmO
-40 to -50 dBmO
-50 to -55 dBmO
Measured at PWRO + ,
RL = 300n

Symbol

Parameter

Min

Test Conditions

NOISE (All receive channel measurements are single ended)
Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

Nxc ,

Transmit Noise, C-Message
Weighted

15

dBrncO

VFxl+ = GRDA, VFxl- = GSx

Nxc2

Transmit Noise, C-Message
Weighted with Eighth Bit Signaling

18

dBrncO

VFxl + = GRDA, VFxl- = GS x;
6th frame signaling

Nxp

Transmit Noise, Psophometrically
Weighted

-75

dBmOp

VFxl + = GRDA, VFxl- = GSx

NRC'

Receive Noise, C-Message
Weighted: Quiet Code

11

dBrncO

DR = 11111111

NRC2

Receive Noise, C-Message
Weighted: Sign bit toggle

12

dBrncO

Input to DR is zero code with sign
bit toggle at 1 kHz rate

NRP

Receive Noise, Psophometrically
Weighted

-79

dBmOp

DR = lowest positive decode level

NSF

Single Frequency Noise
End to End Measurement

-50

dBmO

PSRR,

Vcc Power Supply Rejection,
Transmit Channel

-30

dB

Idle channel; 200mV pop signal on
supply; 0 to 50kHz, measure at Dx

PSRR2

VBB Power Supply Rejection,
Transmit Channel

-30

dB

Idle channel; 200 mV pop signal on
supply; 0 to 50 kHz, measure at Dx

PSRR3

Vcc Power Supply Rejection,
Receive Channel

-25

dB

Idle channel; 200 mV pop signal on
supply; measure narrow band at
PWRO +, 0 to 50 kHz

PSRR.

VBB Power Supply Rejection,
Receive Channel

-25

dB

Idle channel; 200 mV pop signal on
supply; measure narrow band at
PWRq+, 0 to 50 kHz

CTTR

Crosstalk, Transmit to Receive

-71

dB

VFxl + = OdBmO, 1.02 kHz, DR =
lowest positive decode level,
measure at PWRO +

CTRT

Crosstalk, Receive to Transmit

-71

dB

DR = OdBmO, 1.02 kHz,
VFxl + = GRDA, measure at Dx

14-87

CCITT G.712.4.2
Measure at PWRO +

inter

29C13 and 29C14

DISTORTION
Symbol

Parameter

Min

1YP

Max

Unit

Test Conditions

o to

SDl x

Transmit Signal to Distortion, ~-Law
Sinusoidal Input;
CCITT G.712-Method 2

36
30
25

dB
dB
dB

-30 dBmO
-30 to -40 dBmO
-40 to -45 dBmO

SD2x

Transmit Signal to Distortion, A-Law
Sinusoidal Input;
CCITT G.712-Method 2

36
30
25

dB
dB
dB

o to -30dBmO
-30 to -40 dBmO
-40 to -45 dBmO

SDI R

Receive Signal to Distortion, ~-Law
Sinusoidal Input; CCITT G.712-Method
2

36
30
25

dB
dB
dB

Oto -30 dBmO
-30 to -40 dBmO
-40 to -45 dBmO

SD2R

Receive Signal to Distortion, A-Law
Sinusoidal Input; CCITT G.712-Method
2

36
30
25

dB
dB
dB

o to -30 dBmO
-30 to -40 dBmO
. -40 to -45 dBmO

DPx

Transmit Single Frequency Distortion
Products

-46

dBmO

DPR

Receive Single Frequency Distortion
Products

-46

dBmO

IMD,

Intermodulation Distortion,
End to End Measurement

-35

dB

CCITT G.712 (7.1)

IMD2

Intermodulation Distortion,
End to End Measurement

-49

dBmO

CCITT G.712 (7.2)

SOS

Spurious Out 01 Band Signals,
End to End Measurement

-25

dBmO

CCITT G.712 (6.1)

SIS

Spurious in Band Signals,
End to End Measurement

-40

dBmO

CCITT G. 712 (9)

DAX

Transmit Absolute Delay

245

~s

Fixed Data Rate. CLKx = 2.048
MHz; 0 dBmO, 1.02
kHz signal at VFxl + .
Measure at Ox.

Dox

Transmit Differential Envelope Delay
Relative to DAX

170
95
45
105

~s

1=
1=
1=
1=

~s
~s
~s

AT&T Advisory #64 (3.8)

o dBmO Input Signal

AT&T Advisory #64 (3.8)

o dBmO Input Signal

500-600 Hz
600 - 1000 Hz
1000 - 2600 Hz
2600 - 2800 Hz

DAR

Receive Absolute Delay

190

~s

Fixed Data Rate, CLK R = 2.048
MHz; Digital input is DMW
codes. Measure at PWRO +.

DOR

Receive Differential Envelope Delay
Relative to DAR

45
35
85
110

~s

1=
1=
1=
1=

14-88

~s

~s
~s

500-600 Hz
600-1000 Hz
1000 - 2600 Hz
2600 - 2800 Hz

inter

29C13 and 29C14

TRANSMIT CHANNEL TRANSFER CHARACTERISTICS
Input amplifier is set for unity gain, nonlnverting; maximum gain output.

Symbol
GRX

Parameter

Min

lYP

Max

Unit

Test Conditions

o dBmO Signal input at VFxl +

Gain Relative to Gain at 1.02 kHz
16.67 Hz

-30

dB

50 Hz

-25

dB

60 Hz

-23

dB

200 Hz

-1.8

-0.125

dB

300 to 3000 Hz

-0.125

+0.125

dB

3300 Hz

-0.35

+0.03

dB

3400 Hz

-0.7

-0.10

dB

4000 Hz

-14

dB

4600 Hz and Above

-32

dB

0) ""."0
SCALE

.,

Figure 8. Transmit Channel

14-89

inter

29C13 and 29C14

RECEIVE CHANNEL TRANSFER CHARACTERISTICS
Symbol
GRR

Parameter

Min

Typ

Max

Unit

Below 200 Hz

+0.125

dB

200 Hz

-0.5

+0.125

dB

300 to 3000 Hz

-0.125

+0.125

dB

3300 Hz

-0.35

+0.03

dB

3400 Hz

-0.7

-0.1

dB

4000 Hz

-14

dB

4600 Hz and Above

-30

dB

EXPANDED

~ 12SdB •. 125018

200H,

Test Conditions

o dBmO Signal input at DR

Gain Relative to Gain at 1.02 kHz

SCALE

300Hz

/-.IZ5dB

300",

FREQUENCY IH.,

Figure 9. Receive Channel

14-90

29C13 and 29C14

A.C. CHARACTERISTICS -

TIMING PARAMETERS

CLOCK SECTION
Symbol

Parameter

Min

Typ

Max

Unit

ley

Clock Period. CLKx• CLKA

4BB

ns

IeLK

Clock Pulse Width. CLKx• CLKA

220

ns

tCCLK

Data Clock Pulse Width

220

leoc

Clock Duty Cycle. CLKx• CLK A

45

~.

Clock Rise and Fall Time

5

It

ns
50

Test Conditions
fCLlO(

= fCLKA = 2.04B MHz

64 kHz"" fOCLK "" 2.04B MHz

55

%

30

ns

Max

Unit

145

ns

0< CLOAO < 100 pf
0< CLOAO < 100 pf

TRANSMIT SECTION, FIXED DATA RATE MODEl
Symbol

Parameter

Min

Typ

0

Test Conditions

lozx

Data Enabled on TS Entry

toox

Dala Delay from CLKx

0

145

ns

tHZX

Data Float on TS Exil

60

215

ns

CLOAO = 0

ISDN

Timeslol X 10 Enable

0

145

ns

ISOFF
I FSO

Timeslot X 10 Disable

60

215

ns

0< CLOAO < 100 pf
CLOAO = 0

Frame Sync Delay

100

ley-l00

ns

Iss

Signal Selup Time

0

ns

tSH

Signal Hold Time

0

ns

RECEIVE SECTION, FIXED DATA RATE MODE
Symbol

Parameter

Min

Typ

Max

10

Unit

tOSA

Receive Data Setup

tOHA
tFSO

Receive Data Hold

60

Frame Sync Delay

100

tCy -l00

ns

tSIGA

SIG A Update

0

2

p.S

ns
ns

NOTES:
1. Timing parameters tozx • tHZX ' and tSOFF are referenced to a high impedance state.

14-91

Test Conditions

29C13 and 29C14

WAVEFORMS
Rxed Data Rate Timing
TRANSMIT TIMING

:L~~TlME;;~

~:::j?~ ~i-: c:
,_ '21b'--j[

j

6
5
3",,'--' 4 t ;,
", ' " - / ° '-/.. 7, ' ./..06· ' . /

=i

NON·SIGNALING

FRAMES

_

FSx
SIGNALING
FRAMES

tFSO

"'-------------------------------

CLKX

Ox

_________________________________'S~S1
SIGx

DON'T CARE

b -ly'SOFF__--t=~-'S-H

VALID

X

.

DON'T

CARE

NOTE: ALL TIMING PARAMETERS REFERENCED TO Viti AND VIL EXCEPT
tozx. ISOFF AND IHZX WHICH REFERENCE A HIGH IMPEDANCE STATE

RECEIVE TIMING

O.

StGR

--------------------~~-----------------+~
NOTE: ALL TIMING PARAMETERS REFERENCED TO VIH AND Vil.

14-92

inter

29C13 and 29C14

TRANSMIT SECTION, VARIABLE DATA RATE MODEl
Symbol
tTSOX

Parameter
Timeslot Delay from DCLKl

tFSO

Frame Sync Delay

toox

Data Delay from DCLKx

tOON

Timeslot to Ox Active

tOOFF

Timeslot to Ox Inactive

tox
tOFSX

Data Clock Period
Data Delay from FS x

Min

Typ

140
100

Max

Unit

tox -140

n5

lev-lOa

n5

a
a
a

100
50
80
15620
140

488

a

n5
ns
ns

Test Conditions

0<
0<
0<

CLOAO < 100 pf
CLOAO < 100 pf
CLOAO < 100 pf

ns
ns

RECEIVE SECTION, VARIABLE DATA RATE MODE
Symbol

Parameter

tTSOR

Timeslot Delay from DCLKR3

tFSO

Frame Sync Delay

tOSR

Data Setup Time

tOHR

Data Hold Time

tOR

Data Clock Period

tSER

Timeslot End Receive Time

Min

Max

Unit

toR -140

ns

fey-lOa

ns

Typ

140
100
10
60
488

Test Conditions

n5
ns

15620

a

ns
n5

64 KB OPERATION, VARIABLE DATA RATE MODE
Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

tFSLX

Transmit Frame Sync Minimum
Downtime

488

ns

FSx is TTL -high for remainder of
frame

~

Receive Frame Sync Minimum
Downtime

1952

ns

FSR is TTL high for remainder of
frame

IoclJ(

Data Clock Pulse Width

10

NOTES:

1.
2.
3.

TIming parameters loON arid tDOFF are referenced to a high impedance state.

IFSLX minimum requirements overrides ITSOX maximum spec for 64 kHz operation.
IFSLR minimum requirements overrides tTSOR maximum spec for 64 kHz operation.

14-93

/LS

29C13 and 29C14

VARIABLE DATA RATE TIMING
TRANSMIT TIMING

RECEIVE TIMING

NOTE: ALL TIMING PARAMETERS REFERENCED TO V1H AND V1L EXCEPT
100"1 AND IOFf WHICH REFERENCE A HIGH IMPEOANCE STATE

A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUT/OUTPUT

2.4==>( 2.0

2.0)<=
>TEST POINTS<

0.45

_..:0_.8_______".:.0..:.8.

A.C. TESTING: INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC ~1" and O.4SV FOR A
lOGIC''O'', TIMING MEASUREMENTS ARE MADE AT 2.0V FOR A LOGIC "1" ANO

O.SY FOR A LOGIC "0",

14-94

29C16 AND 29C17
16 PIN CHMOS SINGLE-CHIP PCM CODEC AND FILTER
• 29C16 wLaw, 2.048 MHz Master Clock
• 29C17 A-Law, 2.048 MHz Master Clock

• Low-Power Pin Compatible Version of
Intel's 2916 and 2917

D

• AT&T 03/04 and CCITT Compatible

3 Low-Power Modes
- 5mW Typical Power Down
- 8mW Typical Standby
- 70mW Typical Operating

• TTL and CMOS Compatible

• 16-Pln Package for Higher Llnecard
Densities

• Two Timing Modes
~ 64 KHz to 2 MHz Variable
- 2 MHz Direct

• Ideal for Digital Handset Applications

Intel's 29C16 and 29C17 are CHMOS versions of Intel's NMOS 2916 and 2917 family members. CHMOS is
a technology built on HMOS-II, thus realizing the high performance and density obtained in that process while
achieving the low power consumption typical of CMOS circuits.
The 29C16 and 29C17 are limited feature versions of the 29C13 and 29C14. The inherent low-power and small
package size make these devices ideal for digital handset and cellular telephones where small size and low
power are especially desirable.

vcc

VBB
PWRO+

GS x

PWRO-

VFX I -

P'ilN

GROA

OClK R

TSXIDClKX

DR

Ox

FSR

FSx

GROO

ClK

Figure 1. .Pln Configuration

14-95

29C16 and 29C17

XMIT
SECTION

AUTO
ZERO

OSx_~-----.

j
r - - Dx
OUTPUT
REGISTER

I

REFERENCE

r

~t-------.....I

r-- ........·'fixlDCLKx

Lr:::!:;:~~;;;~;-~:=====l______I__~_FSX
CONTROL

L~LO;OI~C_h----------1--CL'

•

I

CONTROL

RCV
SECTION

SECTION

~
~-

D:
.

. CONTROL

H

BUFFER

I

J.--,
SAMPLE

•...."DHD~'c" I -

PWAC.

DIGITAL
TO
ANALOO
CONTAOL

LOGIC

t-

~

IL

'---1'lfIiI .
1-

INPUT
REGISTER

.......

""'-_

PWAOREFERENCE

LOGIC

t-~DCL'"

F"
Figure 2. BloC,k Diagram

Table 1. Pin Names

Vee
PWRO +, PVVROPDN
DClK R

DR
FSR
GRDD
Vee

Power (-5V)
Power Amplifier Outputs
Power Down Select
Receive Variable Data Clock
Receive PCM Input
Receive Frame
Synchronization Clock
Digital Ground
Power (+5V)

14-96

GS x '
VFxlGRDA
TS x
DClKi<
Ox
FS x
ClK

Transmit Gain Control
Analog Input
Analog Ground
Timeslot Strobe/Buffer Enable
Transmit Variable Data Clock
Transmit PCM Output
Transmit Frame
Synchronization Clock
Master Clock

29C16 and 29C17

Table 2. Pin Description

Symbol

Symbol

Function

Function

Vee

Most negative supply; input voltage is - 5
volts ±5%.

GRDD

Digital ground for all internal logic circuits.
Not internally tied to GRDA.

PWRO+

Non-inverting output of power amplifier.
Can drive transformer hybrids or high
impedance loads directly In either a differential or single ended configuration.

ClK

Master and data clock for Ihe fixed data
rate mode; master clock only in variable
data rate mode.

FSx

PWRO-

Inverting output of power amplifier. Functionally identical and complementary to
PWRO+.

PDN

Power down select. When PDN is TTL
high. the device is active. When low, the
device Is powered down.

8 KHz frame synchronization clock input!
timeslot enable, transmit channel. Operates independently but in an analogous
manner to FSR. The transmit channel enters the standby state whenever FSx is
TTL low for 300 milliseconds.

Dx

DClKR

Selects the fixed or variable data rate
mode. When DClKRis connected to Vee,
the fixed data rate mode is selected. In
this mode, the device Is fully compatible.
with Intel 2910A and 2911 A direct mode
timing. When DClKRIs not connected to
VBB , the device operates In the variable
data rate mode. In this mode DClKRbecomes the receive data clock which operates at TTL levels from 64Kb to 2.048 Mb
data rates.

Transmit PCM output. PCM data is clocked
out on this lead on eight consecutive positive transitions of the transmit data clock:
ClK in fixed data rate mode and DClKx in
variable data rate mode.

DR

FSR

TSx/DClKx Transmit channel timeslot strobe (output)
or data clock (Input) for the transmit channel. In fixed data rate mode, this pin is an
open drain output designed to be used as
an enable signal for a three-state buffer as
in 2910A and 2911A direct mode timing. In
variable data rate mode, this pin becomes
the transmit data clock which operates at
TTL levels from 64Kb to 2.048 Mb data
rates.

Receive PCM input. PCM data is clocked
In on this lead on eight consecutive negative transitions of the receive data clock;'
ClK in the fixed data rate mode and
DClKRIn variable data rate mode.
8KHz frame synchronization clock input!
timeslot enable, receive channel. In variable data rate mode this signal must remain
high for the entire length of the timeslot.
The receive channel enters the standby
state whenever FSR Is TTL low for 300 milliseconds.

14-97

GRDA

Analog ground return for all Internal voice
circuits. Not internally connected to GRDD.

VFxl-

Inverting analog input to uncommitted
transmit operational amplifier.

GSx

Output terminal of on-Chip transmit channel
input op amp. Internally, this is the voice
signal input to the transmit filter.

Vee

Most positive supply; input voltage is + 5
volts ±5%.

intJ

29C16 and 29C17

FUNCTIONAL DESCRIPTION

milliseconds to reach their equilibrium value due to
the autozero circuit settling time.

The 29C16 and 29C17 provide the anaiog-to-digital
and the digital-to-analog conversions and the transmit
and receive filtering necessary to interface a full duplex (4 wires) voice telephone' circuit with the PCM
highways of a time division multiplexed (TDM) sys~
tem. They are intended to be used at the analog
termination of a PCM line.
'
The following major functions are provided:
• Bandpass filtering of the analog signals prior to
encoding and after decoding
• Encoding and decoding of voice' and call progress information
• Encoding and decoding of the signali!1g and supervision information

GENERAL OPERATION

System Reliability Features
The combochip can be powered up by pulsing FSx
and/or FSR while a TTL high voltage is applied to
PDN, provided that all clocks and supplies are connected. The 29C16 and 29C17 have internal resets
on power up (or when Vee or Vcc are re-applied) in
order to ensure validity of the digital outputs and
thereby maintain integrity of the PCM highway.
On the transmit channel, digital outputs Dx and TS x
are held in a high impedance state for approximately
four frames (500pS) after power up or application of
Vee or Vcc. After this delay, Dx and TSx will be functional and will occur in the proper times lot. The analog
circuits on the transmit side require approximately 60

To enhance system reliability, TSx and Dx will be
placed in a high impedance state approximately 30pS
after an interruption of ClK.

Power Down and Standby Modes
To minimize power consumption, two power down
modes are provided in which most 29C16/C17 functions are disabled. Only the power down, clock, and
frame sync buffers, which are required to power up
the device, are enabled in these modes. As shown
in Table 3, the digital outputs on the appropriate channels are placed in a high impedance state until the
device returns to the active'mode.
The Power Down mode utilizes an external control
signal to the PDN pin. In this mode, power consumption is reduced to the value shown in Table 3.
The device is active when the signal is high and inactive when it is low. In the absence of any signal,
the PDN pin floats to TTL high allowing the device to
remain active continuously.
, The Standby mode leaves the user an option of powering either channel down separately or powering the
entire device down by selectively removing FS x and/
or FS R• With both channels in the standby state,
power consumption is reduced to the value shown in
Table 3. If transmit only operation is desired, FSx
should be applied to the device while FS R is held low.
Similarly, if receive only operation is desired, FS R
should be applied while FS x is held low.

Fixed Data Rate Mode
Fixed data rate timing, which i,s 2910A and 2911 A

Table 3. Power-Down Methods

Device Status

Power-Down
Method

Typical
Power
Consumption

Digital Output Status

Power Down Mode

PDN = TTL low

5mW

TS x and Dx are placed in ahigh impedance
state within 10 ~s.

Standby Mode

FSx and FS R are TTL low

BmW

TS x and Dx are placed in a high impedance
state within 300 milliseconds,

Only transmit is
on standby

FS x is TTL low

50mW

TS x and Dx are placed in a high impedance
state within 300 milliseconds.

Only receive is
on standby

FS R is TTL low

50mW

14-98

29C16 and 29C17

compatible, is selected by connecting DClKR to V BB •
It employs master clock ClK, frame synchronization
clocks FS x and FS R, and output TS x.

references determine the gain and dynamic range
characteristics of the device.
Separate references are supplied to the transmit and
receive sections and each is trimmed independently
during the manufacturing process. The reference
value is then further trimmed in the gain setting opamps to a final precision value. With this method the
combochip can achieve the extremely accurate Digital Milliwatt Responses specified in the TRANSMISSION PARAMETERS, providing the user a significant
margin for error in other board components.

ClK serves as the master clock to operate the codec
and filter sections and as the bit clock to clock the
data in and out from the PCM highway. FSx and FS R
are 8 kHz inputs which set the sampling frequency.
TS x is a times lot strobe/buffer enable output which
gates the PCM word onto the PCM highway when an
external buffer is used to drive the line.
Data is transmitted on the highway at Dx on the first
eight positive transitions of ClK following the rising
edge of FS x. Similarly, on the receive side, data is
received on the first eight falling edges of ClK. The
frequency of ClK must be 2.048 MHz. No other frequency of operation is allowed in the fixed data rate
mode.

Variable Data Rate Mode
Variable data rate timing is selected by connecting
DClKR to the bit clock for the receive PCM highway
rather than to V BB • It employs master clock ClK, bit
clocks DClKR and DClKx, and frame synchronization clocks FS R and FS x'
Variable data rate timing allows for a flexible data
frequency. It provides the ability to vary the frequency
of the bit clocks, from 64 kHz to 2.048 MHz. The
master clock is still restricted to 2.048 MHz.
In this mode, DClKR and DClKx become the data
clocks for the receive and transmit PCM highways.
While FS x is high, PCM data from Dx is transmitted
onto the highway on the next eight consecutive positive transitions of DClKx. Similarly, while FS Ris high,
each PCM bit from the highway is received by DR on
the next eight consecutive negative transitions of
DCUtt frame.

A balanced output amplifier is provided in order to
allow maximum flexibility in output configuration.
Either of the two outputs can be used single ended
(referenced to GRDA) to drive single ended loads.
Alternatively, the differential output will drive a bridged
load directly. The output stage is capable of driving
load,s as low as 300 ohms single ended or 600 ohms
differentially.
. ,

Anon-chip autozero circuit corrects for DC-offset on
the input signal to the encoder. This autozero circuit
uses the sign bit averaging technique; the sign bit
from the encoder output ,is long term averaged and
subtracted from the input to the encoder. In this way;

Po~er

Amplifiers

Transmission levels are specified relative to the receive channel output under digital milliwatt conditions,
that is, when the digital input at DR is the eight-code
sequence specified in CCITT recommendation G.711.

Table 4. Zero Transmission Level Points
Typ

Units

OTLP1~

Zero Transmission Level Point
Transmit Channel (OdBmO) ,.-Iaw

+2.76
+1.00

dBm
dBm

Referenced to soon
Referenced to 9000.

OTLP2x

Zero Transmission Level Point
Transmit Channel (OdBmO) A-law

+2.79
+1.03

dBm
dBm

Referenced to 6000
Referenced to 9000.

OTLP1 R

Zero Transmission Level Point
Receive Channel (OdBmO) p.-Iaw

+5.76
+4.00

dBm
dBm

Referenced to 6000
Referenced to 9000.

OTLP2R

Zero Transmission Level Point
Receive Channel (OdBmO) A-law

+5.79
+4.03

dBm
dBm

Referenced to 6000.
Referenced to 9000

Symbol

Parameter

14-100

Test Conditions

29C16 and 29C17

ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias. . . . . . . . . . -1 DoC to +SO"C
Storage Temperature . . . . . . . . . . . -65DC to +l50DC
Vee and GRDD with Respect to Vee' . . . . -O.3V to 15V
All Input and Output Voltages
with Respect to Vee' . . . .
. .. -O.3V to 15V
All Input and Output Voltages
with Respect to Vee • . . . .
-15V to +O.3V
Power Dissipation : . . . . . . . . . . . . . . . . . 1.35W

"NOTICE: Stresses above those listed under
"Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

D.C. CHARACTERISTICS
(TA = ooe to 70°C, Vee = + 5V ± 5%, Vee = - 5V ± 5%, GRDA = OV, GRDD =OV, unless otherwise
specified)
Typical values are for TA = 25°C and nominal power supply values

DIGITAL INTERFACE
Symbol

Parameter

Min

Max
10

Unit
IJA

GRDD '" VIN ".; VIL (Note 1)

High Level Input Current

10
0.8

IJA
V

VIH '" VIN '" Vee

Input Low Voltage

IlL

Low Level Input Current

IIH
VIL

Typ

VIH

Input High Voltage

VOL
VOH

Output Low Voltage

Cox
CIN

Digital Output Capacitance 2

5'

Digital Input Capacitance

5

2.0

.-

V
0.4

Output High Voltage

Test Conditions

2.4

V

IOL = 3.2 mA at Ox. TSx

V

IOH = SO pA at Ox

pF
10

pF

POWER DISSIPATION
All measurements made at fOCLK
Symbol

= 2.048 MHz, outputs unloaded.

Parameter

Min

Typ

Max

. Unit

Test Conditions

lecl

Vee Operating Currentl

5.6

rnA

leel

Voo Operating Current

-5.6

mA

Iceo

Vee Power Down Current

0.5

mA

PDN .. VIL; after 101J.S

1000

Vee Power Down Current

-0.5

mA

Ices
IBes

Vee Standby Current

O.S

rnA

PDN .. VIL; after 101J.S
FSx• FS R ·.. VIL; after 300 ms

Vee Standby Current

-O.B

rnA

FSx, FS R .. VIL; after 300 ms

POl
Poo

Operating Power Dissipation3

70

mW

Power Down Dissipation 3

5

mW

PST

Standby Power Oissipation3

8

mW

PDN .. VIL; after 1OILS
FSx• FS R .. VIL; after 300 ms

NOTES:

1. VIN is the voHage on any digital pin.

.

2. Timing parameters are guaranteed based on a 100 pF load capacitance. Up to eight dig~a1 outputs may be connected to a common PCM highway wHhout buffering; assuming a board capacitance of 60 pF.
3. With

nominal power supply values.

4. Vcc applied last or simultaneously wHh Vee.

14-101

29C16 and 29C17

ANALOG INTERFACE, TRANSMIT CHANNEL INPUT STAGE
Min
Typ
Symbol
Parameter
,Isx1

Input Leakage Curre(1t. VFxl-

R1x1
VOSX1

Input Resistance, VFxl-

Ava.

DC Open Loop Voltage Gain, GSx
Open Loop Unity Gain Bandwidth, GSx

Ie
CLX1
RLXI

Max

Unit

100

nA

Test Conditions
-2;17V"; V1N .,; 2.17V

MO

10

Input Offset Voltage, VFxl-

mV

25

5000
1

Load Capacitance, GSx
Minimum Load Resistance, GSx

MHz
pF

50
10

kO

ANALOG INTERFACE, RECEIVE CHANNEL DRIVER AMPLIFIER STAGE
Symbol
Typ
Parameter
Min
Max
Unit

RoAA

Output Resistance, PWRO +, PWRO-

1

0

VOSRA

Single-Ended Output DC Offset, PWRO +,
PWRO-

75

mV

CuiA

Load Capacitance, PWRO +, PWRO-

100

Tast Conditions
Relative to GRDA

pF

A.C. CHARACTERISTICS - TRANSMISSION PARAMETERS
Unless otherwise noted, the analog input is a 0 dBmO, 1020 Hz sine wave. 1 Input amplifier is set for unity gain,
inverting. The digital input is a PCM bit stream generated by pasSing, a 0 dBmO, 1020 Hz sine wave through an
ideal encoder. ReCeive output is measured single ended. All output levels are (sin x)/x corrected. Typical values
are forTA = 25°C and nominal power supply values. (TA = OOC to +70°C; Vee = +5V±5%; VBB = -5V ±5%;
GRDA = 0; GRDD = 0; unless otherwise specified).
GAIN AND DYNAMIC RANGE
Min

Typ

Max

Units

EmW

Encoder Milliwatt Response
(Transmit gain tolerance)

-0.18

±0.04

+0.18

dBmO

EmWTS

EmW variation with Temperature and
supplies

-0.07

±0.02

+0.07

dB

DmW

Digital Milliwatt Response
(Receive gain tolerance)

-0.18

±0.04

+0.18

dBmO

DmWTS DmW variation with temperature and
supplies

-0.07

±0.02

+0.07

dB

Symbol

Parameter

Test Conditions
Signal input of 1.064 Vrms /L-Iaw
Signal input of 1.068 Vrms A-law
TA = 25OC, Vee = -5V,
Vcr; = +5V
± 5% supplies, 0 to 7O"C
Relative to nominal conditions
Measure relative to OTLPR• Signal
input per CCITI Recommendation
G.711. Output Signal of 1000 Hz.
RL = 00
TA = 25°C; Vee = -5V,
Vcr; = +5V.
± 5% supplies, 0 to 7O"C

NOTES:
1. OdBrilO is defined as the zero reference point of the channel for ,. law under last (OTLP). This corresponds 10 an analog signal input of 1.064 Volts
rms or ,an output of 1.503 wits rms.
'

14-102

inter

29C16 and 29C17

GAIN TRACKING
Reference Level = -10dBmO
2916
Symbol

Parameter

GT1 x

Transmit Gain Tracking Error
Sinusoidal Inpul; wlaw

GT2x

Transmit Gain Tracking Error
Sinusoidal Input; A-law

GT1 R

Receive Gain Tracking Error
Sinusoidal Input; Wlaw

GT2R

Receive Gain Tracking Error
Sinusoidal Inpu.t; A-law

Min

2917
Max

Min

0.25
0.5
1.2
0.25
0.5
1.2

0.25
0.5
1.2

NOISE (All receive channel measurements are single ended)
2916
Symbol

Parameter

Max

0.25
0.5
1.2

, Min

Typ Max Min

Unit

Test Conditions

dB
dB
dB

+310 -40 dBmO
-4010 -50 dBmO
-50 to -55 dBmO

dB
dB
dB

+310 -40 dBmO
-40 to -50 dBmO
-50 to -55 dBmO

dB
dB
dB

+3 to -40 dBmO
-40 to -50 dBmO
-50 to -55 dBmO
Measured at PWRO + ,
RL = 300n

dB
dB
dB

+3 to -40 dBmO
-40 to -50 dBmO
-50 to -55 dBmO
Measured at PWRO + ,
RL = 300n

2917
Typ Max

Test Conditions

Unit

Nxc ,

Transmit Noise, C-Message
Weighted

Nxp

Transmit Noise, Psophometrically
Weighted

NRC'

Receive Noise, C-Message
Weighted: Quiet Code

NRC2

Receive Noise, C-Message
Weighted: Sign bit toggle

NRP

Receive Noise, Psophometrically
Weighted

NSF

Single Frequency Noise
End to End Measurement

PSRR,

Vee Power Supply Rejection,
Transmit Channel

-30

-30

dB

Idle channel; 200 mV pop
signal on supply; 0 to 50
kHz, measure at Dx

PSRR2 VBB Power Supply Rejection,
Transmit Channel

-30

-30

dB

Idle channel; 200 mV pop
signal on supply; 0 to 50
kHz, measure at Ox

PSRRa Vcc Power Supply Rejection,
Receive Channel

-25

-25

dB

Idle channel; 200 mV pop
signal on supply; measure
narrow band at PWRO + ,
Oto 50 kHz

15

dBrncO

Unity Gain

dBmOp

Unity Gain

11

dBrncO

DR

12

dBrncO

Input to DR is zero code
with sign bit toggle at 1 kHz
rate

-79

dBmOp

DR = lowest positive
decode level

-50

dBmO

CCITT G.712.4.2
Measure at PWRO +

-75

-50

= 11111111

29C16 and 29C17

NOISE (All receive channel measurements are single ended)
2917

2916

Symbol

Parameter

Min

Typ

Max

PSRR4

VBB Power Supply Rejection,
Receive Channel

CTTA

Crosstalk, Transmit to Receive

-71

CTRT

Crosstalk, Receive to Transmit

-71

Min

-25

Typ

Max

Unit

Test Conditions

dB

Idle channel; 200 mV pop
signal on supply; measure
narrow band at PWRO + ,
Oto 50 kHz

-71

dB

Input = OdBmO, Unity
Gain, 1.02 kHz, DR =
lowest positive decode
level, measure at PWRO+

-71

dB

DR = OdBmO, 1.02 kHz,
measure at Dx

-25

DISTORTION

ISymbol

Parameter

Min

lYP

Max

Unit

Test Conditions

o to

SDl x

Transmit Signal to Distortion, I!-Law
Sinusoidal Input;
cCln G.712-Method 2 (2916)

36
30
25

dB
dB
dB

-30 dBmO
-30 to -40 dBmO
-40 to -45 d~mO

SD2x

Transmit Signal to Distortion, A-Law
Sinusoidal Input;
CCITT G.712-Method 2 (2917)

36
30
25

dB
dB
dB

o to -30 dBmO
-30 to -40 dBmO
-40 to -45 dBmO

SD1 R

Receive Signal to Distortion. I!-Law
Sinusoidal Input; cCln G. 71 2-Method
2 (2916)

36
30
25

dB
dB
dB

o to -30 dBmO
-30 to -40 dBmO
-40 to -45 dBmO

SD2R

Receive Signal to Distortion, A-Law
Sinusoidal Input; cCln G.712-Method
2 (2917)

36
30
25

dB
dB
dB

o to -30 dBmO
-30 to -40 dBmO
-40 to -45 dBmO

DPx

Transmit Single Frequency Distortion
Products (29C16)

-46

dBmO

DPR

Receive Single Frequency Distortion
Products (29C16)

-46

dBmO

IMD,

Intermodulation Distortion,
End to End Measurement

-35

dB

CClnG.712 (7.1)

IMD2

Intermodulation Distortion,
End to End Measurement

-49

dBmO

CCln G.712 (7.2)

SOS

Spurious Out 01 Band Signals,
End to End Measurement

-25

dBmO

CCIn G.712 (6.1)

SIS

Spurious in Band Signals,
End to End Measurement

-40

dBmO

CCIn G. 712 (9)

DAX

Transmit Absolute Delay

245

I!S

Fixed Data Rate. CLKx = 2.048
MHz; 0 dBmO, 1.02 kHz input
Signal, Unity Gain. Measure
at Dx.

Dox

Transmit Differential Envelope Delay
Relative to DAX

170
95
45
105

I!S
I!S
I!S
I!S

1 = 500-600 Hz

DAR

Receive Absolute Delay

190

I!S

DOR

Receive Differential Envelope Delay
Relative to DAR

45
35
85
110

I!S
I!S
I!S
I!S

14-104

AT&T Advisory #64 (3.8)

o dBmO Input Signal

AT&T Advisory #64 (3.8)
OdBmO Input Signal

f = 600-1000 Hz
f = 1000 - 2600 Hz
f = 2600 - 2800 Hz
Fixed Data Rate, CLK = 2.048
MHz; Digital Input is DMW
codes. Measure at PWRO.j.

1 = 500-600 Hz
f = 600-1000 Hz
f = 1000 - 2600 Hz
f = 2600 - 2800 Hz

29C16 and 29C17

TRANSMIT CHANNEL TRANSFER CHARACTERISTICS
Input amplifier is set for unity gain, inverting.
Symbol
GRX

Parameter

Min

1\'p

Max

Unit

Test Conditions

o dBmO Signal input at VFxl-

Gain Relative to Gain at 1.02 kHz
16.67 Hz

-30

dB

50 Hz

-25

dB

60 Hz

-23

dB

200 Hz

-1.8

-0.125

dB

300 to 3000 Hz

-0.125

+0.125

dB

3300 Hz

-0.35

+0.03

dB

3400 Hz

-0.7

-0.10

dB

4000 Hz

-14

dB

4600 Hz and Above

-32

dB

..

.

,..

olZ5dB

• Old.

""

.j. . . .
seALI

.,

.,.
.,.

...
."

.5O

FAEOUE~'tIHII

Flgu", 4. Transmit Channal

14-105
"

29C16 and 29C17

RECEIVE CHANNEL TRANSFER CHARACTERISTICS
Symbol
GRR

Parameter

Min

~p

Max

Unit

+0.125

dB

200 Hz

Below 200 Hz
-0.5

+0.125

dB

300 to 3000 Hz

-0.125

+0.125

dB

3300 Hz

-0.35

+0.03

dB

3400 Hz

-0.7

-0.1

dB

4000 Hz

':'14

dB

4600 Hz and Above

-30

dB

EXPANDED

·'2501.

•. 125d8 .'25d'
200Mr

3OOH,

_Olda
3lOOH.

"",H.

'-

-w.
......

Test Conditions

o dBmO Signal input at DR

Gain Relative to Gain at 1.02 kHz

, •. 125018
DH•

-Iwa
4OQOHI

~

IS,-~.,
..... ..

.--......-30

Figure 5. Receive Channel

14-106

SCAlf:

inter

29C16 and 29C17

A.C. CHARACTERISTICS -

TIMING PARAMETERS

CLOCK SECTION
Symbol

Parameter

Min

lev

Clock Period, ClK

4BB

Typ

Max

ns

leLK

Clock Pulse Width, ClK

220

ns

IOCLK

Data Clock Pulse Width

220

ns

leoc

Clock Duty Cycle, ClK

45

I" ~

Clock Rise and Fall Time

5

50

Test Conditions

Unit
fCLK

= 2.04B MHz

64 kHz". foCLK ". 2.04B MHz

55

%

30

ns

Max

Unit

145

ns

o<

0< CLOAo < 100 pf

TRANSMIT SECTION, FIXED DATA RATE MODEl
Symbol

Parameter

Min

Typ

Test Conditions

lozx

Data Enabled on TS Entry

loox

Dala Delay from ClK

0

145

ns

1HZ)(

Dala Floal on TS Exil

60

215

ns

CLOAo

lSON

Timeslot X to Enable

0

145

ns

0< CLOAo < 100 pf

lsoFF
I Fso

Timeslol X to Disable

60

215

ns

CLOAo

Frame Sync Delay

100

1ev-100

ns

Max

Unit

0

CLOAo < 100 pf

=0
=0

RECEIVE SECTION, FIXED DATA RATE MODE
Symbol

Parameter

Min

IOSR

Receive Dala Setup

toHR
tFSo

Receive Dala Hold

60

Frame Sync Delay

100

Typ

ns

10

ns
ley-100

NOTES:

1. Timing parameters toZH' tHZX, and tSOFF are referenced to a high impedance state.

14-107

ns

Test Conditions

29C16 and 29C17

WAVEFORMS
Fixed Data Rate Timing
TRANSMIT TIMING

~
j~"
..
ICLI(

eLK

FSx

1

2

3'

4 .

5

6

7

8

-

NOTE: ALL TIMING PARAMETERS REFERENCED TO V 1H AND V 1L EXCEPT tOZX' tSOFF AND tHZX WHICH
REFERENCE A HIGH IMPEDANCE STATE

RECEIVE TIMING

STABLE

NOTE: ALL TIMING PARAMETERS REFERENCED TO V 1H AND V1Lo

14-108

29C16 and 29C1.7

TRANSMIT SECTION, VARIABLE DATA RATE MODEl
Max

Unit

tTSDX

Timeslot Delay from DCLKl

140

tDx -140

ns

tFSD

Frame Sync Delay

100

tCy -l00

ns

Ioox

Data Delay from DCLKx

0

100

ns

0< CLOAO < 100 pf

tOON

Timeslot to Ox Active

0

50

ns

0< CLOAO < 100 pf

tOOFF

Timeslot to Ox Inactive

0< CLOAO < 100 pi

tox
toFSX

Data Clock Period

Symbol

Parameter

Data Delay from FSx

Min

Typ

0

80

ns

488

1562

ns

0

140

ns

Test Conditions

RECEIVE SECTION, VARIABLE DATA RATE MODE
Symbol
tTSOR

Parameter
Timeslot Delay from

DCLK~

Min

Max

Unit

140

toR -140

ns

lcy-lOO

tFSo

Frame Sync Delay

100

tOSR

Data Setup Time

10

tOHR

Data Hold Time

60

loR

Data Clock Period

488

IsER

Timeslot End Receive Time

Typ

Test Conditions

ns
ns
ns

1562

ns
ns

0

64 KB OPERATION, VARIABLE DATA RATE MODE
Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

tFSLX

Transmit Frame Sync Minimum
Downtime

488

ns

FSx is TTL high for remainder of
frame

tFSLR

Receive Frame Sync Minimum
Downtime

1952

ns

FSR is TTL high for remainder of
frame

IocLK

Data Clock Pulse Width

10

NOTES:

1.
2.
3.

Timing parameters tOON and tOOFF are referenced to a high impedance state.
tFSLX minimum requirements overrides tTSox maximum spec for 64 kHz operation.
tFSLR minimum requirements overrides tTSOR maximum spec for 64 kHz operation.

14-109 '

/1S

inter

29C16 and 29C17

VARIABLE DATA RATE TIMING
TRANSMIT TIMING

RECEIVE TIMING

A.C. TESTIf\iG INPUT, OUTPUT WAVEFORM
INPUT/OUTPUT

A.C. TESTING: INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC "1M and O.4SV FOR A
LOGIC "0", TIMING MEASUREMENTS ARE MADE AT 2.0V FOR A LOGIC 'T' AND

O.IV FOR A LOGIC "0",

14-110

APPLICATION
NOTE

AP-142

Note: See data sheet for latest specifications. Values given in this
application note are for reference only, and were considered correct
at the time of publication (Feb. 1982).
February 1982

14-111

AP-142

1.0 INTRODUCTION
This application note describes the features and capabilities of the 2913 and 2914 codec/filter combochips, and
relates these capabilities to the design and manufacturing
of transmission and switching Iinecards.
'

1.1

improved features help in the design of second-generation
Iinecards first by comparing the two generations of components to see where the improvements have been made,
and then by discussing specific design considerations.

1.2 Comparison of Flrst- and SecondGeneration Component Capabilities

Background

The first generation of per line codecs (Intel 2910A/llA)
and filters (Intel 2912A) economically integrated the
,analog-digital conversion circuits and PCM formatting
circuits into one chip and the filtering and gain setting
circuits into another chip. These two chips helped to
make possible the rapid conversion to digital switching
systems that Ilas taken place in the last few years.
The second generation of Intel LSI PCM telephony components, the 2913/14 Combochip, extends the level of
integration of the Iinecard by combining the codec and
filter functions for each line on a single LSI chip. In the
process of combining both' functions, circuit design
improvements have also improved performance, reduced
external component count, 'lowered power dissipation,
increased reliability, added new features, and maintained
architectural transparency.
The 2913 and 2914 data sheet contains a complete
description of both parts, including detailed discussions of
each feature and specifications for timing and performance levels. This application note, in conjunction with
the data sheet, describes in more detail how the new and

The combochip represents a higher level of component
integration than the devices.it replaces and, because of the
economics of LSI (replacing two chips with one), ultimately will cost significantly less at the component level.
But comparison of the combochip block diagram with
first-generation single-chip codec and filter reveals few
major functional differences. Figure I compares the firstgeneration codec and filter chips to the combochip. Both
provide rigidly specified PCM capabilities of voice signal
bandlimiting and nonlinear companded AI D and D I A
conversion. The first on-chip reference voltage was introduced in the 2910/2911 single-chip codecs and is included
in the combochip. The provision of uncommitted buffer
amplifiers for flexible transmission level adjustment and
enhanced analog output drive was a feature of the now standard 2912 switched-capacitor RCM filter is available on
the combochip. Likewise, independent transmit (AID)
and receive (D I A) analog voice channels which permit
the two channels to be timed from independent (asynchronous) clock sources is common to the first- and secondgeneration devices. Finally, the ability to multiplex signalling bits on a bit-stealing basis from the digital side of the
device has been duplicated on the combochip.

r------------------------------~---~--------'

I
I
I

'

I
I

I~~~~

I

I

c;w

OZ
.... 0

~iE
cw

oid
......
I
I

b
TRANSFORMER TRANSMISSION
DRIVER
LEVEL CONTROL

1---------+--tt-7
DECODE StH

PCM
LOWPASS

pORA-LAW
DECODING

SINGLE-CHIP PCM CODEC

SINGLE 10 kHz

Not Spec'd

Gain Setting

Strap Selectable

2911 + 2912
30 dB

PSRR I kHz

0.33

> 35 dB
> 35 dB

Trim Using Pot Necessary

Precision Resistors
Eliminate Trim Req.

Direct

yes

yes

Timeslot Assign

yes

no

yes

yes

15 dBrncO Transmit
II dBrncO Receive

15 dBrncO Transmit
II dBrncO Receive

S/ D - half channel.improvement

See Data Sheet

See Section 2.0

GT - half channel improvement

See Data Sheet

See Section 2.0

PDN Pin

Frame Sync Removal'or PDN Pin

Signalling

291O-8th Bit

2914-8th Bit

Auto Zero

External

Internal

S & H Caps

External Transmit
Internal Receive

Internal

Test Modes

None

Design Tests
Manufacturing Test
On-Line Operational Tests

Resistive Ladder

Capacitive Charge Redistribution
Ladder

Fuse Blowing ±0.2 dB

Fuse Blowing ±O.04 dB

Operating Modes
On-Chip Vref

ICN - half channel improvement

Power Down (Standby)

Encoder Implementation
,Filter/ Gain Trim

14-113

AP-142

XMIT
SEC1:ION .
AUTO
ZERO

DX

YFxl+

SAMPLE
AND HOLD
AND DAC

VFXI-

SUCCESSIVE
APPROXIMATION
REGISTER

COMPARATOR

OUTPUT
REGISTER

:'i'ixlDCLKx
SIOx/ASEL

OSx _-+--'-----.1
ANALOG
TO
DIGITAL
CONTROL

LOGIC

I - - - - - - - -....--~_-FSX
....-------~--__I_-CLKx

Re.

SECTION
CLKSEL

PI!R

os.

LOOP

D.

PWRO+_-+.....- - - ,

DCLKR

PWRO-_-t......- - - '

'-----II---SIGR

Vee

V.I

QRDD

GADA

(a) Combochlp Block Diagram

Vee
PWRO+, PWROGSR
PDN
CLKSEL
LOOP
SIGR
DCL~

DR
FSR
GRDD
Vee

Power (-SV)
Power Amplifier Outputs
Receive Gain Control

GSx
VFxl-. VFxl+
GRDA

Power Down Select
Master Clock Frequency
Select
Analog Loop Back
Receive Signaling Bit Output
Receive Variable Data Clock
Receive PCM Input
Receive Frame
Synchronization Clock
Digital Ground
Power (+SV)

NC
SIGx
ASEL
TSx
DCLKx
. Ox
FSx
CLKx
CLKR

Transmit Gain Control
Analog Inputs
Analog Ground
No Connect
Transmit Signaling Input

p- or A-law Select
Timeslot Strobe/Buffer Enable
Transmit Variable Data Clock
Transmit PCM Output
Transmit Frame
Synchronization Clock
Transmit Master Clock'
Receive Master Clock

(b) Combochlp Pin Names

Figure 2. Block Diagram of 2913/14 Combochlp .

14-114

AP-142

generation products shows the significant improvement in
the combochip both in performance levels and system
flexibility.

Table 3.

2914 Factors which Increase Llnecard
Manufacturing Yields and Efficiency
• Higher Reliability

2.0 DESIGN CONSIDERATIONS

-Fewer connections & components

The key point with the 2913/14 is that it will result in a
Iinecard that performs better and costs less than any twochip codec/ filter solution. The lower cost results from
many factors, as seen in Table 2. Both direct replacement
costs and less tangible design and manufacturing time
savings combine to yield lower recurring and nonrecurring costs. As an example, the wider margins to transmission specs and the higher power supply rejection ratios of
the 2913/14 will both shorten the design time needed to
build and test the Iinecard prototype and reduce the reject
rate on the manufacturing line.
Table 2.

-more integmted packaging
-more margin to specs
-lower power
-NMOS proven process
-Less sensitive to parameter variations
• Fewer Manufacturing Steps
-no gain trimming

2913/14 Factors which Lower the Cost of
Llnecard Design and Manufacturing

-on chip Vref
-wide power supply tolemnce

• Lower LSI Cost (2914 vs. 2910/ II + 2912)

-on chip te.st modes

• Fewer External Components

-wide margins to specs

• Less Board Area
• Shorter Design/ Prototype Cycle

Table 4.

• Better Yields/ Higher Reliability
• Lower Power/Higher Density

Design Factors for 2914 which Reduce
. Llnecard PCB Area

• Integmted Packaging

Part of the recurring cost of Iinecard production is the
efficiency of the manufacturing line in turning out each
board. This is measured in both parts cost and time.
Average manufacturing time is strongly effected by the
line yield, i.e., the reject rate reliability. A Iinecard using
the 2913/14 has many labor-saving features, which also
increases the reliability of the manufacturing process.
Some of these features are detailed in Table 3.
The combination of fewer parameters to trim (gain, reference voltage, etc.), tolerance to wider power supply variations, and on-chip test modes make the Iinecard very
manufacturable compared to first-generation designs.
Probably the most obvious improvement in Iinecard
design based around the 2913/14 is the reduction in linecard PCB area needed. compared to two-chip designs.
The combination of the codec and filter into a single
package alone reduced the LSI area by one-third. Table 4
shows many of the other ways in which board area is
conserved. In general, it reduces to fewer components,
more on-chip features, and layout of the chip resulting in
an efficient boa·rd layout which neatly· separates the
analog and digital signals both inside the chip and on the
board.

14-115

-2914 vs. 2910/ II + 2912 = 1/3 board area
-2913 takes even less space
• Fewer Interconnects/ Components
-codec/filter combined
-on-<:hip reference voltage
-on-<:hip auto zero
-on-<:hip capacitors
-no gain trim components
-no voltage regulators
• Efficient Layout (Facilitates Auto Insertion,
-analog/ digital sections sepamted on chip
-digital traces can cross under chip
-two power supplies only
-low power/ high density

AP-142

Table 5. 2913/14 Operating Mode Options Add Flexibility to Llnecard Design.
Option

Mode Control Pins

Results of Mode Selection
2914 (24 pin)
2913 (20 pin)

I

Companding Law
Power Down

Data Rate

Test Modes

I

SIGX/ASEL
PDN

A-Law or M-Law + Signalling
A-Law /M-Law, no Signalling
Transmit & Receive Side Go To Standby Power (5 mW)

FSX & FSR Removed
FSxRemoved

Same (12 mW)
Transmit Side Goes to Standby (110 mW)

FSR Removed

Receive Side Goes to Standby (70 mW)

=VCC/GRDD/VBB
DCLKR= VBB

1.536/1.544/2.048 Mbps in fixed data rate mode

= VCC/GRDD/VBB
DCLKR = Clock

Variable Data Rate Mode from 64 Kbps to 2.048 Mbps,
No Signalling
Implements Analog Loopback I No Loopback Capability

LOOP = VCC

Provides Access to Transmit Codec Through ASEL and TSX Pins

PDN= VBB
DR= VBB

.

Provides Access to RCV Filter Input at DCLK R and Transmit
Filter Outputs at ASEL and TSX Pins

Many of the factors discussed above-which result in
efficient, cost-effective linecard designs'-:are discussed in
more detail both in the 2913/14 data sheet and in the following sections of this note.

significant system timing, control, or software modifications. To this end, two distinct user-selectable timing
modes are possible with the combochip. For purposes of
discussion, these are designated (a) fixed data rate timing
(FDRT) and (b) variable data rate timing (VDRT).

2.1

FDRT is identical to the 2910/2911 codec timing in
which a single high-speed clock serves both as master
clock for the codec/filter internal conversion/filtering
functions and as peM bit clock for the high-speed serial
peM data bus over which the combochip transmits and
receives its digitized voice code words. In this mode,
peM bit rates are necessarily confined to one of three
distinct frequencies (1.536 MHz, 1.544 MHz, or 2.048
MHz). Many recently designed systems employ. this type
of timing which is sometimes referred to as burst-mode
timing because ofthe low duty cycle of each timeslot (i.e.,
channel) on the time division multiplexed peM bus. It is
possible for up to 32 active combochips to share the same
serial peM bus with FDRT.

Operating and Test Mode Selection

A key to designing with the 2913/14 combo is the wide
range of options available in configuring, either with strap
options or in real time, the different modes of operation.
The 2913 combochip (20 pins) is specifically aimed at
synchronous switching systems (remote concentrators,
PABXs, central offices) where small package size is especially desirable. The 2914 combochip (24 pins) has additional features which are most suitable for applications
requiring 8th-bit signalling, asynchronous operatiol)., and
remote testing of transmission paths (e.g., channel banks).
Once the specific device is selected, there is a wide range
of operating modes to use in the card design, as seen in
Table 5. This table lists the optional parameters and the
pins which control the operating mode. The result of
selecting a mode is listed for both the 2913 and 2914.
The purpose of offering these options is to ensure that the
2913/14 combo will accommodate any existing linecard
design with architectural transparency. At the same time,
features were designed in to facilitate design and manufacturing testing to reduce overall cost of development
and production.

2.2

Data Rate Modes

Any rapid conversion scenario presumes that the combochip will fit existing system architectures (retrofit) without
14-116

VDRT (sometimes referred to as shift register timing), by
comparison, utilizes one high-speed master clock for the
combochip internal conversion/filtering functions and a
separate, variable frequency, clock as the peM bit clock
for the serial peM data bus. Because the serial peM data
rate is independent of internal conversion timing, there is
considerable flexibility in the choice of peM data rate. In
this mode the master clock is permitted to be 1.536 MHz,
1.544 MHz, or 2.048 MHz, while the bit clock can be
any rate between 64 kHz and 2.048 MHz. In this mode
it is possible to have a dedicated serial bus for each combochip or to share a single serial peM bus among as many
as 32 active combochips.
Thus, the two predominant timing configurations of pres-

AP-142

ent system architectures are served by the same device,
allowing, in many cases, linecard redesign without modification of any common system hardware or software.
Additional details relating to the design of systems using
either mode are found in section 3.0.

2.3

specifications may not reflect the improved performance
margin.
Half channel measurements have been made of the
transmission parameters-gain tracking (GT), signal to
distortion ratio (Sf D), and idle channel noise (ICN).

Margin to Performance Specifications

Gain Tracking-Figure 3 shows the gain tracking data
for both the transmit and receive sides of the combo
using both sine wave testing (CCITT G712.l1 Method 2)
and white noise testing (CCITT G712.11 Method I). The
data shows a performance very nearly equal to the theoretically best achievable using both test techniques. End
to end measurements, although not spec'd, also show a
corresponding good performance with errors less than or
equal to the sum of the half channel values.

The combochip benefits from design, manufacturing, and'
test experience with first-generation PCM products on the
part of the system manufacturer, component suppliers,
and test equipment suppliers. The sub-millivolt PCM
measurement levels and tens of microvolts accuracy
requirements on the lowest signal measurements often
result in tester correlation problems, yield losses, and
excess costs for system and PCM component manufacturers alike. Thus additional performance margin built
into the PCM components themselves will have its effect
on line circuit costs even though the system transmission

Signal to Distortion Ratio-This is a measure of the
system linearity and the accuracy in implementing tlie
companding codes. Figure 4 shows the excellent perfor-

GAIN TRACKING ERROR VERSUS SIGNAL LEVEL
2914 COMBO AID
SINUSOIDAL TEST (CCITT G712.11 METHOD 2)

iii

iii

~

CJ

Z

i!

L--~ _ _ _ _ _ _ _ _ _ _

.5

0

I

•

I

I't--55-50

o

I

I--~

I-

I
1

~

-1

I

I

I I

a:
oa:

ffi

Lrrv~r

-4
0----------0+
3
,
I
IdBmO

~ -.5

Z

I

J

i

1

~

I
I

a:
oa:

ffi

GAIN TRACKING ERROR VERSUS SIGNAL LEVEL
2914 COMBO DIA
SINUSOIDAL TEST (CCITT G712.11 METHOD 2)

g

~-I

1

l- _ _ _ _ _ _ _ _ _ _ _ _

~ .5

~

I
I LEVEL
-55 -50
-40
0 +3
r------------ldBmO

-.5

1

I-~

I
-2

Figure 3.

I

Ll

~-------------:

~ .5

INPUT

t--I--+-..-

I
I
I
I

o

JI

w

-1

I

,I

GAIN TRACKING ERROR VERSUS SIGNAL LEVEL
2914 COMBO DIA
WHITE NOISE TEST (CCITT G712.11 METHOD 1)

!a:

I

Z

I

1
I

-2

o

~
~

I

~ -1

I

i!

i

~ -.5
Z

I

1

- - - - - - - - - __ 1
INPUT
I
I
I
I I LEVEL
-55 -50 -40--- - - - - - - -'0+3
1--"';
dBmo

L-L--

I-

I
I

I
I

0

~--I

Z

GAIN TRACKING ERROR VERSUS SIGNAL LEVEL
2914 COMBO AID
WHITE NOISE TEST (CCITT G712.1,1 METHOD 1)

~

I
I

.5

CJ

-2

a:

I

1

w

INPUT

~ 0

ILEVEL

i!
~ -.5

-55 -50

r-- - - -- - -- -

a:

I

I-

Z

;;:

-1

0 +3

---,dBmO
I

I-...J

I

CJ

I
I

-40

-2

I
I

2914 Half Channel Gain Tracking Performance Measurements for both Sine and Noise Testing

14-117

AP·142

--

iD
'0

0' 40

!ia:
~ 30
j:
II:

0

Iii

//

!ia:
~ 30

AID SINEWAVE TEST

j:

Iii

20

...is
~

0

5z

5c

10

c

20

10

z

CI

0
-45 -40 -35 -30 -25

-15

-5

0

5

0

iii

-45 -40 -35 -30 -25

INPUT LEVEL (dBmO)

iD

~ 40
0

!i
II:

Z 30

0
j:
II:

0

Iii

...is

20 /

0

5

-5

0

5

iD

./-m""m,,

~ 40

!i

II:

z

0
j:

30

II:

0

Iii

FULL CHANNEL SPEC-,

20 /

fi","""=
"FULL CHANNEL SPEC

...is
~

10

CI

-5

0'

g
z

-15

INPUT LEVEL (dBmO)

0 10

5c

5c
iii

D/A SINEWAVE TEST

0

...
;!:
CI

~

II:

is

iii

-

iD

'0

0' 40

z

0

CI

50 -45 -40 -35 -30 -25

-15

-5

0

5

iii

50

-45 -40 -35 -30 -25

-15

INPUT LEVEL (dBmO)

INPUT LEVEL (dBmO)

Figure 4.

0

2914 Half Channel Signal to Distortion Ratio (S/D) ,Performance Measurements for both
Sine and Noise Testing

mance of the 2914 for both the transmit (A/D) and
receive (D / A) channels using sine wave and noise testing.
The margin is greater than 3 dB above the half channel
spec which means that a larger error budget is available
to the rest of the channel.
Statistical Analysls-A statistical analysis of G.T. and
S/ D measurements over many devices shows a very tight
distribution, as seen in Figure 5. There are several consequences resulting from this highly desirable distribution:
(I) the device performance is controllable, resulting in
high yields, (2) the device circuit design is tolerant of
normal process variations, thereby ensuring predictable
production yields and high reliability, and (3) understanding of, the circuit design and process fundamentals is
clearly demonstrated-largely as a result of previous telephony experience with the Intel NMOS process.
Idle Channel Noise-The third transmission parameter
is idle channel noise (lCN). Figure 6 gives half channel
ICN measurements which show a substantial margin to
specification.

Power Supply ReJection-Circuit innovation in the
internal combochip design has resulted in significant
improvements in power supply rejection in the 5 to 50
kHz range (Figure 7), and it is this frequency band which
usually cOhtains the bulk of the switching regulator noise.
These higher frequencies, outside the audio range as they
are, are not objectionable or even detectable in the
transmit direction except to the extent that they alias into
the audio range as a result of internal sampling processes
in the transmit filter and A/ D converter. Sampling techniques in the combochip minimize this aliasing. In the
receive direction, excess high frequency noise which propagates onto the subscriber loop can interfere with signals
in adjacent wires and is thus objectionable even without
aliasing. The symmetrical true differential analog outputs
of the combochip are an improvement from earlier
designs which failed to maintain true power supply symmetry through the output amplifiers. Not only does the
differential design improve transmission performance, but
it also reduces the need for power supply bypass capacitors, thereby saving component cost on the linecard.

14-118

AP-142

r:~~-------------------,

iii"

~ 40

.

CJ

z

;;:

MINIMAX

1

I/ENVELOPE

a:

oa:

ffi

I

1

L

.5

I

1

i INPUT
-L ________ " LEVEL

1:=
-55 -50 - 4 9 . - - - - - - - - - 1 0 +3

0

a:

I- -1

z
;;:

CJ

~

~

g

1---

: dBmO

i5

1
1
1

1
I
I

/

AT&T SPEC. TA. 64
2914 COMBOCHIP
DIA SINEWAVE TEST

en 20

..J

~

o

5 10

amples that look like signals of 5 - 8 kHz = 3 kHz
and 7 - 8 kHz = 1 kHz, respectively.
Conversely, the sampling process produces replicas (aliasing) of the sampled signal around mUltiples of the sampling frequency. Therefore, if two signals are introQuced
digitally representing I kHz and 2 kHz, there will also be
frequency components located at 8 kHz = ±I kHz and 8
kHz = ±2 kHz, and so on for all multiples of 8 kHz.
Thus it is possible to generate frequencies at arbitrary
values after sampling by controlling the frequency of each
signal within the 4 kHz input band regardless of whether
it is in analog or PCM.
When an analog signal is sampled, the frequency components generated are all of the same amplitude as the corresponding input spectral components. Therefore, on the
transmit side, measurements made from the PCM data
will have a throughput gain of unity except where components are superimposed (e.g., a 4 kHz input signal will
have an alias component at 4 kHz which may double the
amplitude at 4 kHz when the two components are
combined).
When an analog signal is reconstructed from digital samples, it goes through a sample and hold stage which has
the effect of imposing a weighting function on the resulting spectral components that is represented by

Sine

['2T~

= Sin

characteristic: (I) input analog test frequencies and perform an FFT on the corresponding PCM samples that
are generated to determine spectral frequencies and amplitudes at the codec output, or (2) use an "ideal" D/ A converter on the PCM samples to convert the digital data
back to analog so that the spectral amplitUdes and frequencies can be determined using analog circuits such as
spectrum analyzers or filter banks. In either case, the
effects of sampling will be the same. Figure 13 shows two
spectral diagrams of amplitUde versus frequency. The top
diagram represents the locations of nine test frequencies
corresponding to the seven specified frequencies in the
2913/14 data sheet plus a cO,mponent at 7 kHz and one
at 10 kHz. The bottom figure shows the "equivalent"
spectral component locations when carried in the PCM
bit stream. As an example, frequency #8 is located at 7
kHz; The corresponding PCM frequency is seen in the
lower figure at I kHz. Note also that the analog component at 9 kHz (see #8~) would also generate the I kHz
component in the PCM data.
.
To test the filter, the desired test frequencies are introduced in analog to the filter input in such a way that
there is no confusion as to where the resulting component
will be after sampling (Le., don't simultaneously put in I
kHz and 7 kHz since both of these inputs result in a I
kHz component in the PCM data). Then, using either
technique (FFT or analog) mentioned above, measure the
amplitUde of the corresponding sampled component. The

o

Jwn

4

(a)

5

7

10

8

FREQ
kHz

Analog Signal Frequency Locations

2

where w is the actual spectral component frequency going
into the filter, and T is the width of the hold pulse at the
decoder output. For the 2913/14, the analog, output is
held the full sample period of 125 ILsec (1/8000 Hz) so
that a frequency component at ft ,will have a weighting of

o

8000\ ' frrftl
W =. (-:;rIt) Sm LSOOO]

(b)

Transmit Filter Test Approach-Two approaches, can
be used for half channel testing of the transmit filter

14-127

9

10

FREQ
kHz

PCM Representation of the Signals In (a)

Figure 13. Spectral Properties of the Filter Test
Frequencies In Analog and PCM

AP-142

difference between that amplitude and the input amplitude represents the filter attenuation at the frequency of
the input signal. So, if the input signal was at 7 kHz, the
FFf will determine the amplitude of the corresponding 1
kHz signal. The amplitude change relative to the input
will represent the filter attenuation at 7 kHz.

4.3 Operational On-Line Testing
Two test modes are available which facilitate on-line testing to verify operation of both the combochip and the
entire switching highway network. The first is simply the
capability to duplicate the same Dx transmission in multiple PCM time slots (redundancy checking), and the
second is the analog loopback capability which allows the
testing -of a call completion through the entire PCM voice
path including the time slot interchange network.

Receive Filter Test Approach-In this case, the PCM
test signals can be generated directly from digital circuits
or by going through an "ideal" A/ D (companded) to generate the PCM' samples. Since these samples represent
frequencies below the half sampling rate, Figure l2(b)
now represents the input signals and l2(a) the output, but
with one significant difference-a Sinc[7T fl/8000] weighting function is imposed on all the frequency components
because of the decoder sample and hold output. At the
filter output, the spectral component amplitUdes will
include the effect of the filter response and the weighting
function measured at the actual test frequency. The
receive filter includes a compensation network for the
weighting function in its passband. Therefore, inside the
passband (300 Hz to 3.4 kHz) the measured amplitUdes
should be compared directly to the data sheet specifications. Frequencies outside the passband must be compensated for the weighting function first to determine the true
filter response.

Redundancy Checklng-A feature of the 2913/14 is
that the same 8-bit PCM word can be put on the Dx
highway in multiple time slots simply by holding the
frame sync/data enable (FSx) high and continuing to
supply c10cle pulses (CLKx or DCLKx). If the data
enable was held high for multiple time slots, each time
slot would have identical data in it. By routing this data
through the PCM highways, time slot interchanges,
etc., and then correlating the data between time slots, it
would be possible to detect time slot-dependent data errors. When this test mode is used, no other data will be
generated for the transmit highway until the frame sync
returns low for at least one full clock cycle.

Summary of· Filter Testing-Table 10 lists the nine test
frequencies shown in Figure 12 for both the transmit and
receive filter testing. Fo~ each filter test, the input frequency (analog or PCM), measurement frequency, and
test circuit gain is tabulated corresponding to the desired
test frequency. The various weighting values are easily
handled by computer-based test equipment since the.
inverse weighting function can be stored in the computer
and applied to each measured amplitUde as appropriate.

Table 10
Test
Freq.

Analog Loopback-The 2914 (2913 does not have this
feature) has the capability to be remotely programmed to
disconnect the outside telephone lines and tie the transmit
input directly to the receive output to effect analog loopback within the combo chip: This is accomplished by setting the LOOP input to Vee (TTL high). The res~lt i~ to
disconnect VFxl+ and VFxl- from the external circuitry
and to connect internally PWRO+ to VFxl+, GS r to
PWRO-, and VFxl- to GS x (see Figure 14).
With this test set up, the entire PCM and analog trans-

Fliter Response Testing Input/Output Frequencies and Amplitude Gain Schedule
Transmit
Receive
Input
Measured
Amp
Input
Measured
Amp
Freq.
Weighting
Weighting
Freq.
Freq.
Freq.

1

200

200

200

1

200

200

2

300

300

300

I

300

300

1

3

3000

3000

3000

1

3000

3000

1

4

3300

3300

3300

1

3300

3300

1

5

3400

3400

3400

1

3400

3400

1

6

4000

4000

4000

o to 2

4000

4000

o to 2

7

4600

4600

3400

1

3400

4600

Sinc

4600 7r
8000

8

7000

7000

1000

1

1000

7000

Sine

7000 7r
8000

9

10000

10000

2000

1

2000

10000

14-128

1

S'me ~oooo
8000 7r

AP-142

mission path up to the SLIC can be tested remotely by
assigning a PCM word to a time slot that is read by the
combo being tested. This data is converted to analog
and passed out of the receive channel. It is taken as input by the transmit channel where it is filtered and re-

digitized (encoded) back to PCM. The PCM word can
now be put on the transmit highway and sent back to the
remote test facility. By comparing the PCM data (individually or as a series of codes) the health of that particular connection can be verified.

--------------------------,

:
I

VFXI-

TRANSMIT:
VOICE

GSX

b.

I-LOOP
:

I
DX I

I
I
I
I
I
PWRO+

I
I

..f--+-------:.......

DRI

I
I

PWRO-+r----~--~

I

DIGITIZED
PCM
LOOP BACK
RESPONSE

DIGITIZED
PCM
TEST
TONE

I

_______________ _ :
IL _ _ _ _ _ _ _ _ _
GSR

COMBOCHIP ANALOG LOOP BACK FUNCTION

Figure 14. Simplified Block Diagram of 2914 Combochlp In the Analog ,Loopback Configuration

14-129

SLD
'INTERFACE SPECIFICATION
The Subscriber Line Datalink is a three wire interface for synchronous data transfer between master
and slave devices. Four full duplex time-multiplexed
. 64 kbps channels are supported on a serial pingpong link. Each channel transfers a byte of data
every 125 /lS.
The SLD· interface was developed primarily for telecommunications applications, where 8 kHz synchronous data transfers are the norm. It provides a standardized physical interface for the transfer of circuit
switched voice and data, signalling, and control channels to and from the individual subscriber circuits,
physically (but not logically) isolating the interface to
the per-line components from the system backplane,
which is often a proprietary arrangement. This allows
a large selection of different subscriber devices to be
produced economically, with a standard interface,
and connected to the backplane through a linecard·
controller, or interface controller.

INTERFACE DESCRIPTION
The three wires of the SLD interface consist of a data
clock (SCL), a data direction signal (SDIR), and a
ping-pong data lead (SLD). The data clock and direction signals can be common to all slave devices
connected to the interface controller. A separate SLD
line is connected to each slave device. The slave
devices on this interface receive the clock signals
from 'the controller, and only drive the data line when
so indicated by the direction signal. The controller
generates both the SDIR direction signal and the SCL
data clock, which are derived from the system clock.
The SLD line itself supports a 512 kbps rate, as defined by the SCL clock. The data on this line is formatted as 32 bits of receive (towards slave) data and
32 bits of transmit (from slave) data. This pattern is
repeated at an 8 kHz rate, with the direction of transmission being defined by the 8 kHz SDIR signal.
When SDIR is high, data is transferred to the slave
device, and when SDIR is low, data is transferred
back to the master. Hence, the SDIR signal has a
duty cycle of approximately 50%. The transmit and
receive direction data is further divided into eight
bytes, four transferred in each direction. The effective
data rate over the SLD interface is 256 kbps in each
direction. Because all SLD lines handled by a controller share the same direction Signal, these separate

links are all synchronous., The exact use of the data
channels on the SLD is determined by the devices
connected to it.

USE OF THE SLD BY THE iATC 29CX
FAMILY OF COMPONENTS
The SLD interfaCe provides the data link to the perline components of the 29CX family. The iATC 2952
linecard controller operates as an SLD master, and
controls eight SLD interface lines. The 2952 can assign times lots to the first two bytes of data in each
direction and thus route this data to or from 'either of
the two TDM backplane highways it supports. These
bytes are typically used for subscriber voice and/or
circuit switched data. The remaining two bytes in each
direction can be used for commands, configuration
data, signalling, status, or additional subscriber data,
depending on the devices using the SLD. The 2952
routes data tolfromthe third and seventh bytes
through its bidirectional FIFO, or via the I£P port, and
these channels are usually used for control. The .
fourth and eight bytes are stored intermediately in .
holding registers by the 2952, and are typically used
for signalling information.
Figure 1 shows the SLD configuration in the analog
subscriber case, when the 2952 is connected to the
29C51. The first and fifth bytes (channel A) represent
the primary voice channel, and route the PCM voice
byte between the backplane and the 29C51 via the
linecard controller. The second and sixth bytes (channel B) contain PCM data to support the secondary
analog channels of the 29C51, and three party conferencing. The third byte is used as a control channel
to program the features of the 29C51, while the seventh byte can be used to read back, or verify, this
control information. The fourth and eighth bytes are
used to transport Signalling information to and from
the 29C51. The SLD link provides an efficient means
of routing all this information between the 29C51 combos and the linecard controller.
The SLD approach extends to support digital subscriber components as well. The first two bytes in
each direction support voice/data information (B1and B2-channels ofthe CCITT model). The remaining
two bytes in each direction are used for control, sta. tus, and data (D-channel) as needed for the appli-

14-130

SLO Interface Specification

SOIR

---.J

SlO

2952 - - . . 29C51

A

B

s

C

A

B

C

s

TRANSMIT DIRECTION

RECEIVE DIRECTION
A - PRIMARY VOICE CHANNEL
B - SECONDARY VOICE CHANNEL
C-CONTROL
S - SIGNALLING

Figure 1. SlO for the Analog Subscriber Case

cation. In a terminal application the SLD can be used
to interface the digital transceiver to an SLD combo
to provide voice capability. It can also function as a
general serial data port for access to data carried in
the 81-,82-, or D-channels.

SLO TIMING
The duty cycle of the 512 kHz SCL clock is typically
50%. However, because this signal is usually derived
from the system clock, it may not be practical to generate a 50% duty cycle. For example, the 2952 gen-

erates a 33% duty cycle clock if the system clock is
1.536 MHz (24 timeslot systems). All slave devices
built to interface to the SLD should accept duty cycles
of from 30% to 70%.
A special case exists for systems with a 1.544 MHz
clock. It is not possible to derive a 512 kHz SCL clock .
from this system clock. For this case, SCL is allowed
to have an instantaneous bit rate of 514.67 kHz, with
a stretched clock cycle inserted to achieve a 512 kbps
average over the 125 JLS frame. This stretched clock
cycle may occur as the last clock of the frame, or as
the first clock of the frame (see Figure 2).

SYNC--~~~~~-=-=-=-=----dr---l~-------------------------ClK
SOIR ----------------------------~

SCl
-OR-

Figure 2.
14-131

SLD Interface Specification

GENERAL SLD TIMING SPECIFICATION
Following is a general SLD timing specification which
can be used as a guideline in the design of SLD
master or slave devices. ·It allows for data reception

by the master on rising or falling edges of SeL and
fordata reception by the slave on falling edges, and
if adhered to, is compatible to all currently existing
SLD standard Intel components.

~L 17----J--+'---1----1I--"""I"i...,
SDIR

I ~
-I !-TOSS
I
I r T'
.
I- OIRR' I -+t
'I - TOHS
III
.
.

I ,

---.I I- TDON.1

I

I
TDOFF2 -t

I

SLDs

~

f

I

I

I

1

II
I
I
I

:

~
I I
I
I

I

.

-Ik!-

bI

.-kj -8I

---t---

-I-i~-~--"I

TOIRFR

I

I

I

G

I-TDOFF1

!

! }

I I.
~ i -TOON2

I

I

Figure 3. General SL.D Timing

14-132

r

i -:
-t--~r---

TOSM-I

TOHM

SLD Interface Specification

General SlD Timing
Symbol

Parameter

Min

TOSM

Oata Setup Time, Master1

150

ns

TOHM

Oata Hold Time, Master1

0

ns

TOSS

Oata Setup Time, Slave

200

ns

TOHS

Oata Hold Time, Slave

150

ns

TOOFF1

SOIR To Slave Oata High Z

Typ

Max

50

Unit

ns

TOON1

SOIR To Master Oata On

70

ns

TOOFF2

Master Oata High Z To SOIR

20

ns

TOON2

SOIR To Slave Oata On

0

ns

TOIRR

SCl To SOIR Rising Edge 2

-150

TOIRFR

SCl Rising Edge To SOIR Falling Edge 2

-150

ns

TOIRFF

SOIR Falling Edge To SCl Falling Edge 2

200

ns

SCl Outy Cycle 5

30

SCl Frequency3

100

50

70

%

512

514.7

kHz

50

ns

Rise and Fall Times, All Signals
SOIR Period

ns

125

iJS

Notes: 1) SLO master can receive on falling or rising edges.
2) It is the responsibility of the master to control SOIR properly to allow reception of data at SLO turn-around pOints.
The TOIR times above do not guarantee data reception on both rising and falling edges.
3) SeL may be 514.7 kHz (instantaneous) for 1.544 MHz system clocks. However, not all slave devices will accept
this. Refer to the timing for the specific slave devices the master will interface with. SeL must have 64 pulses per
SOIR cycle in any case.
4) To calculate capacitive load for SLO, SOIR, or SeL for a given master or slave device, determine the number of
inputs and outputs which will be connected to the Signal, and multiply by 15 pF. Then add another 20 pF.
5) Not all slave devices will accept this duty cycle range. Refer to the timing for the specific slave .devices the master
will interface with.

14-133

AR-273

Two programmable les
enhance line-card functionality
Besides handling subscriber-line interface tasks, this chip pair
takes over such responsibilities as time-slot assignment
by Fred H. Cherrick and Bhupendra K. Ahuja,

Intel Cprp.• Chandler. Ariz.

D In a major step toward the fully integrated telecom-

tions of battery feed, overvoltage protection, and ringing
inunications line card, two complementary-MOs integrat- can be effectively integrated, in bipolar technology. Also,
ed circuits will make possible computer control of the the functions of supervision, hybrid impedance balancing,
card's functions. The iATC 29C5l provides coding and and testing are being implemented as single C-MOS chips.
decoding between subscriber-line and pulse-code-moduThe 29C5l (Fig. 2) goes beyond these chips by includlated signals, filtering, and hybrid balancing-aU on a ing aU the features available in standard codec-filter and
single chip. As weU as being programmable, it includes a impedance-balancing chips, plus extra capabilities aimed
number of capabilities ordinarily requiring much addi- at improving system efficiency., The extra capabilities can
tional discrete' circuitry. Complemeritirig this IC is an 'be categorized as featllre control, a secondary' voice or
advanced line-card controUer, the iATC, , 29<::52, which data channel,and signaling. Feature control refers to the
gives the card extra intelligence to manage the increased ability of the 29C51 to be managed by commands origi- .
number of lines and the additional functions made avail- nating in system software and is achieved by making key
able by a, higher level of integration.
functions user-programmable, such as gain adjustments,
These two chips are the first of a family aimed at loop-back testing, and impedance balancing, The secondrealizing the concept of an integrated-services digital net- ary channel can be used for many purposes, including
work; or .ISDN (see "Making phone calls digital end to ' conferencing and telemetry. Signaling is the routing of
end: the ISDN," opposite). Their programmability brings status information concerning individual subscriber line!!,
important control functions down to, the line-card level such as hook condition, dialing, and ring detection.
from the central switching office. Programmability also
makes possible such new features as automated testing of The need, for impedance balancing
the line-card functions.
Because of the high voltages on the two-wire subscribIn today's analog network, the Borscht (for battery er line and the requirement for separate 'receive and
feed, overvoltage protection, ring generation, supervision, transmit digital channels, transformers are ,used to concodec, hybrid impedance balancing, and testing) func- vert signals to the four-wire transmission level. But betions (Fig. 1) make up the requirements for a line circuit cause mismatched impedances can affect transformer
in a digital switch. This circuit has geJ;leraily been built coupling, a hybrid impedance-balancing circuit is needed
,with discrete devices, transformers" and in some cases, between two-wire analog subscriber loops in a four-wire
test relays. However, the obvious benefits of integration transmission system where separate wire pairs 'are ashave already produced single-chip codec-filters.
signed for the transmit and receive directions.
In a two-to-four-wire system, there is almost unity
Recent developments have shown that the BOR func-

}
BATTERY
FEED

4-WIRE
TRANS,
MISSION
NETWORK

1. Llne-card archetype. Subscriber-line interfaces have used discrete or MSI circuits to implement the battery feed, overvoltage protection.
ring generation. superVision. codec·filter. hybrid balancing. and testing (the Borscht functions). Two VLSI chips perform the tasks as highlighted.

14-134

W ..4.,4\

:

I$."l J< \. ..:

(K

p, t;i#

;:i';:,····;',~,. . . ._ , _ _ . . .

_....1

j

Th\!lrl. •. .•.•.
rather than develop rapidly, eveni! a star1lU1rd.1s developed. . The iJ'l.TC family.is this type of sofutiorL'T
(nthe U.• S., American Telephone &Telegraph Co. has' Showshowsuchaconversionofanaloglodi'
proposed a plan to provide service wittlal~mate voice and lines will be accomrl)Odated by the addition
data transmission, capable 01 5!1-kiIObit.per-second bidirec- components aimed at providing digital tor
tional data rates over a Single subscriber fine. AT&T has phone terminal equipment

0'

coupling between the two wires in the transmiting direction and the two on the receiving side. However, there
can be undesirable coupling of signals from the receiving
to the transmitting direction. This coupling results in an
echo to the calling party if the loop impedance is significant enough to unbalance the two-to-four-wire hybrid,
The intent of the balancing is to improve the return loss
from the receive to transmit direction,
The 29C51 includes the two-to-four-wire conversion
with software~programmable balancing so that return
loss can be optimized for various subscriber-line conditions. This programmability is better understood by looking at the specific conditions needed for a subscriber line
to be balanceed and have a low return loss.
If the receive side of a hybrid balancing network has
an output impedance of Zo, and the two-wire side presents a load impedance of Z;, the two-wire subscriber
signal is given by :
V, = (Z;t!Zo+Z;)V,

wh!'re V, is the subscriber signal ap.d V, is the receive
signal. Since two-to-four-wire transmit-direction coupling is almost unity, the transmit signal is given by:
V, = (Z,/Zo+ Zb)V,

where Zb is the balancing impedance. To cancel this
receive signal from the transmit direction, a balance
network composed of Zo and Zb are used to produce the
balance signal:
Vb = (Z,/Zo+ Zb)V,

The two-to-four-wire conversion is achieved by subtracting Vb from V, with a perfect cancellation happening when Zb=Z;. From the perspective of the switch,
the subscriber loop's impedance, Z;, is highly variable,

,~

due to such factors as different loop lengths and wire
guages, However, because it is impractical to make balance impedances equally variable, hybrjd balance can
only be approximated by a discrete network, Zb and Zo,
to achieve an allowable system return loss,
The 29C51 provides the three most commonly used
test balancing networks: some systems may also use
them as the regular balancing networks. These three
common networks have been integrated in a switchedcapacitor-filter configuration, and their output is subtracted from the transmit signal. The user may choose
any of them under software control.
To meet varying requirements for two-to-four-wire
conversion, two pins have been provided with which a
user can also connect custom balance networks and still
perform the signal subtraction on chip. These pins are
provided because the subscriber loops fall into basically
two categories-short and long, or loaded and unloaded, loops. The user can choose between these two external balancing networks under software control.
The 29C5l has another feature to bring circuits into
even better balance: impedance interpolation between.
the two external balancing networks. Interpolation
makes it possible to achieve much better return loss for
loops falling within the limits of th<; external networks.
The interpolation network produces an effective
transfer function of aH1(f) + (I-a) H,(f) where H1(f)
and H,(f) are transfer functions of the two external
balancing networks, and a is the interpolation coefficient. The. user can set a to 1.0, 0.75, 0.5, 0,25 or 0
under software control and produce a wide range of
return-loss characteristics (Fig. 3) using only the two

14-135

2. Software·swltched functions. To set
programmable functions such as attenuation, hybrid impedance balancing, loop-back
testing, and primary or secondary channel
selection, users of the iATC 29C51 send
control commands to on-chip registers over a
serial port. Gain and impedance balance values may also be established externally.

TRANSMIT GAIN ADJUSTMENT

networks to serve the extremities of loop conditions.
Gain levels for receive and transmit functions in the
29C51 can be adjusted in less than a millisecond and
are dynamically controllable within software constraints. Programmable analog and digital loop-back
modes are designed to automate as much of the test
function as possible. In analog loop-back, a peM byte
can be decoded into analog form and encoded into
digital form to provide a response byte that the system
can compare with the original transmission. In digital
loop-back, an analog input to the primary or secondary
line can be encoded, transferred to the receive input,
and decoded to return the signal in the primary analog
channel. Both features are useful for a variety of test
functions associated with line quality and balancing.
Along with its primary voice channel, the 29C51 has
a secondary channel for a simultaneous information sig-

fmll1

'mill
~I

=
~

200 Hz
200 Hz

nal. This feature may be used in
many different applications, such as
telemetry, teleconferencing, remote
loop testing, and control. The channel actually provides two secondary
analog inputs (SAl), which can be
encoded in a differential or singleended mode as an 8-bit /-I.-law or Alaw companded peM word at an 8kilohertz sampling rate. On the
receive side, a secondary analog output (SAO) is provided, which is the
decoded value of the received 8-bit
peM control data.
Applications such as reading power and water meters or other narrow-bandwidth analog signals can
be sampled at 8 kHZ by the 29C51
encoder and the digitized words sent
to a central processing location.
Similarly, the SAO can be used to
control electrical appliances by sending different peM words for on or off conditions to the
29C51. One such application of this feature is in controlling power-load peaking for utilities.

Secondary-channel uses
The secondary channel also can provide conference
calling. In this mode, it is instructed to add a second
analog signal following the decoding of the primary voice
channel so these signals can then be filtered together.
This valuable conferencing tool can be expanded through
iterations of the process in different line circuits and in
specific conferencing circuits.
However, no input band-limiting filters or outputsmoothing filters are present on the 29C51 for this secondary channel. Therefore, either the user must provide
this filtering off chip or else limit the applications of the
secondary channel to carrying signals having less than a
4-kHz bandwidth.
The secondary channel can also be
used in remote loop testing where
the battery voltage or the loop current is a dc variable to be monitored

fmax =4kHz

3. Interpolated Impedance range. The
29C51 has an impedance-balancing feature
with which a wide variety of values can be
obtained by interpolating between fixed mini·
mums and maximums set externally. Values
of a equal to 1 and 0 yield the external balance values; fractional a values produce a
better balance over the frequency spectrum.

14-136

4. Comple. control made simple. Connection of eight subscriber lines to pulse-code-modulated transmission highways and their
signaling channels is made easy in the iATC
29C52 line-card controller by compiling
HDLC commands on chip. A content-addressable memory reduces control overhead
by assigning time slots automatically.

29C51
SERIAL

SUBSCRIBER
as a secondary analog input. The enPULSE'COOEcoded values of the voltage or curMODULATEO'
LINES
rent can be processed to determine if
os, } SIGNALING
a loop requires a voltage boost. The
ANO HIGH·
LEVEL
desired values can be sent as a peM
'-_ _ _.... os, g~~M~~K
word to the 29C51 on the secondary
channel, and the decoded value from
the SAO can be a control input to the
TIMe,SLOT
line card to allow adjustment of the
MATCHtNG
CONTENT
battery voltage.
ADDRESSABLE
MEMORY
The secondary channel can also
132 BY 88ITSI
detect the on- 'or off-hook signal. The
loop current is a good monitor of
this signal. which can be encoded at
OMA REQUEST
a SAl, thus simplifying the signaling
INTER RUPT-----'
overhead of a subscriber-line interCHIP SELECT-----'
face circuit. Similarly, the ringing
WRITE - - - - - - - I
tone can be sent as digitized peM
words, which when decoded at the
SAO can be used to control the ringing frequency and
modularization. The modularization of the software can
amplitude in a particular subscriber circuit. This ability be repeated in hardware design, giving flexibility that
can save considerable amounts of discrete circuitry most promotes cost-effective modules with different levels of
line cards include to perform the signaling functions: voice or voice-and-data service.
With much of the control function integrated and an
identifying and .controlling subscriber-loop conditions
on-chip high-level-protocol interface, the 29C52 (Fig. 4)
such as ringing, and on- or off-hook.
The 29C51 uses a simple communications link between represents the continuation of the trend to flexible, intelits ports and a line-card controller. This configuration ligent line cards. As a dedicated large-scale integrated
reduces the digital interface requirements for synchro- line-card controller, it provides distributed control by
nous receive and transmit operation from 13 connections exploiting the capabilities of the 29C51.
to the digital backplane for timing and data in current
Exchanging signals
codec-filters to three pins in the 29C51-the bidirectional
The controller Ie has a subscriber-line interface operatdata lead, a clock, and the data direction signal.
The chip also is equipped with a set of dedicated ing synchronously with up to eight 29C51 chips on a
signaling pins to link with line hardware that performs single card. This interface provides an exchange of prithe BOR functions. The pins will work with advanced mary voice signal, secondary-channel data, feature-consingle-chip BOR circuits such as one described by Harris trol information, and signaling status between each line
Corp. at the International Solid State Circuits Confer- circuit and the network controller. The exchange occurs
ence last month. With such a chip, the subscriber-line every peM frame simultaneously for all subscribers.
The chip's backplane interface connects the line card
circuitry is reduced to two Ies.
Until recently, subscriber-line control, supervision, and to the switching-system backplane. Two bidirectional
PeM-interface functions have been implemented with peM voice and data highways can be addressed, and
standard logic and programmable read-only memories. In these will operate at standard peM rates with 24 to 64
private branch exchanges, replacement of logic compo' time slots per direction for each l25-microsecond frame.
The 29C52 also has two signaling and control highnents by a microprocessor has already become commonplace, while in central-office switches, this trend has only ways, with one channel active at anyone time. Each
just begun. A major advantage of the software-driven signaling highway is configured with a peM highway to
structure of a microprocessor-based line card is that it form a line group. The signaling highways use a modified
lends itself to advanced analog telephony and future en- high-level data-link control protocol at the same speed as
the peM highways. All HOLe protocol control and rehanced services.
The presence of line-card intelligence provides another sponse is carried out by the 29C52, including processing
opportunity for distributed control in the switching sys- a variety of automatic responses regarding simultaneous
tem. Software development. a major portion of system reception, transmission errors, and address recognition.
The serial control structure in the HOLe protocol can
design cost, can also be made more efficient through

14-137

NO

5. Microprocessor control flow. In smaller systems or where HOLC
is not desired, a microprocessor can control the 29C52 through a
direct-memory-address port, The associated routine follows a simple
loop between the system backplane and the chip's control registers.

provide for fewer interconnections and has fewer signals
to drive around the system than would a parallel-bus
configuration. Moreover, a ser.ial structure will cost less
and present fewer noise problems.
Some of the penalties involved in this approach have
been lessened with the 29C52 because the 4-MHz data
rate helps to alleviate the bandwidth constraint inherent
in serial channels. Also, the potential for errors in the
serial structure is lessened with the HOLC protocol, which
is compiled and interpreted by the 29C52. Acknowledgment requirements, error checking, and contention resolution between the two channels are HOLC features that
improve data reliability.
The 29C52 accepts incoming HOLc-formatted commands for setting up voice calls. The opening and closing
flag are standard formats. The address includes a 7-bit
29C52 identifier and a single control bit. The standard
HOLC control byte is utilized only for bit 7, the poll-final
response bit. The auxiliary control byte indicates the type
of message in the information bytes and includes a reserved field to indicate the subscriber unit number. The
feature-control commands follow and include receive and
transmit highway and time-slot assignments. The cyclic
redundancy error-checking code follows. .
Each byte of information (FC, to FC" including the
time-slot-assignment bytes) would be placed in a message
first-in, first-out memory on the 29C52. As each frame
passes, a feature-control command byte is sent out to the
29C51 of the appropriate subscriber line, and its time-slot
data is sent to the correct location in the on-chip content-addressable memory.
The importance of reliability in system control links

cannot be underestimated. The use of the HOLC protocol
is a good start toward this goal since it can provide a
response acknowledgment, as well as its own internal
CRC code for error checking. In the event that one of the
29C52's line groups is disrupted, an external controller
or line-card logic can switch all traffic to the functioning
group, thereby identifying the problem channel.
Switching between the HOLC links has other important
consequences for reliability. Duplicate and redundant
modes can be used separately or together to provide
single or double redundancy in control communications.
When these modes are combined with the testing capability of the 29C51, automatic diagnostic testing and selfmaintenance can become very comprehensive.
.
The voice-call setup can also be completed from the
microprocessor port by following a simple program flow
(Fig. 5). The microprocessor backplane command· register (MBC) contains a bit used as an indication that a valid
address byte is about to be located in the address register. The feature-control byte is placed in the microprocessor input/output buffer (MIOB) and is transferred once
each frame to the feature-control register for that subscriber. After the byte has been transferred, the MIOB
ready bit appears in status register I ,indicating that the
previous byte has been transferred. After all bytes have
been transferred, the frame-synchronization bit in the
MBC register is cleared, and the processor can proceed.
The asynchronous portion of the 29C52 links its interface sections and provides the interface with a PBX microprocessor. The linking with synchronous circuitry occurs through the registers supporting receive and
transmit information for the subscriber-line circuits.

Handling control data
Also, the IC has an instruction decoder for control
information, which requires transmission to the subscriber circuits. This information includes both feature-control
information and receive and transmit time-slot assignment for all channels. The instruction decoder also communicates the signaling command or status between the
line circuits and the group controller at the other end of
the signaling and control highways.
The microprocessor interface is designed with a fullfeature multiplexed-bus interface, interrupt capability,
and direct-memory-access request and acknowledge signals. With added circuitry controlling tone-key dialing to
the line card, a 29C52 combined with an 8051 microprocessor could provide a complete switching function.
In such an application, the system designer can determine the line features managed by the line-card processor
because all status reports and control functions can also
be supplied by a network processor on the serial HOLC
control highways.
The 29C52 is addressed through a 7-bit location,
which either can be set on its pins if no local processor is
used or can be stored in an identification register on
chip. The controller will then respond to that identification within the HOLC destination address. Driven by control software from either a remote group controller or a
local processor, the chip is totally flexible concerning
calling features, intercom capability, line lock-out, and
0
system test and maintenance features.

Reprinted Irom ELECTRONICS, March 24. 1983. copyright 1983 by McGraw·HIIi. Inc. with all rights reserved.

14-138

Architectural 0 vervlew
.

March 1983

=----

©INTELCO RPORATION, 1983.

14-139

-~-~
Order Number 210930·001

inter

Architectural Overview

Intel is developing a family of advanced telephony line-interface circuit components which give OEM's an evolutionary
growth path toward an all-digital network. These new VSLI devices fit into system architectures which are flexible
enough to support both analog and digital subscriber lines.
These components are based on the following design philosophy:
•

Integrate as much of the low-voltage, per-line functions of the analog line circuit as is cost effective.

•

Support an all-serial backplane bus architecture for digital TDM highways, signaling and control buses, and
line-card addressing.

•

Add a wide variety of per-line features to the normal BORSCHT functions for the analog line circuit.

•

Make analog and digital subscriber line circuit cards plug-compatible in a line equipment shelf.

•

Allow all system transmission, signaling, and control buses to serve analog and/or digital subscriber lines, or
analog trunks, interchangeably.

•

Provide a graceful upgrade path from today's analog telephone service to future digital voice/data services by
allowing a common system hardware design using distributed control.

•

Retain compatibility with international transmission, signaling and control standards as they evolve.

The first two members of the family, the 29C5l Feature Control Combo and the 2952 Line Card Controller are described
in this document. Future members of the family will provide digital subscriber capability for both private and public
network switching systems in a manner compatible with CCIIT standards for the ISDN.
The analog line card partitioning shown in Figure I illustrates the generalized interfaces of both components. The 29C51,
plus the SLIC functions, provide the familiar BORSCHT functions. When the 2952 functions are added, the analog line
interface circuit functions are complete. The digital line interface has a !imilar architecture.
The combined use of the 29C51 and 2952 for analog line cards provides all of the PCM encoding, decoding, filtering,
multiplexing, line card addressing and feature control functions associated with the analog line circuit. The 2952 handles
all digital data transfers between the line~group TMD highways and the 29C51 'So Each 2952 line card controller can be
slaved or supported by a local microprocessor.

~#1

SLD
SLiC

-

• OVERVOLTAGE

CLK
29C51

2952
SDIR

• PCM & CONTROL
INTERFACE

XMIT

PCM1

REC

PCM 1

HDLC

HWY

2

• BACKPLANE 110

• LINE BALANCE

• PROTOCOL PROC.
• RINGING

• SLiC CONTROL

• BATTERY FEED

• FILTERING

• SUPERVISION

• ANALOG/DIGITAL
CONVERSION

2

• REDUNDANCY

(}

.214 WIRE
• TEST

OPTIONAL
MICROCONTROLLER

• TEST

• POWER UP CONFIGURATION
• LINE SCAN PROCESSING
SLD

~#8

SLiC

r---

29C51

eLK

~

-OFF HOOK
-DIAL PULSE
-FLASH
• LINE CARD CUSTOMIZING

Figure 1. Analog Line Card
14-140

inter
iATC 29C50A
FEATURE CONTROL COMBO
• External and User Programmable
Transmit and Receive Gain

• Flexible Signaling Interface
• Pin Selectable Channel A or B
Operation on the SLD Interface

• Programmable Internal and External
Hybrid Balance Network Select

• Three Party Conferencing

• Programmable Analog, Digital, and
Subscriber Loopback

• Low Power Consumption

• Programmable piA-Law Select
The Intel iATC 29C50A Feature Control Combo is an advanced user-programmable, fully integrated PCM
Codec with transmit/receive filters fabricated in CHMOS technology. This technology allows the 29C50A to
provide excellent transmission performance while achieving low power consumption.
The 29C50A supports the analog subscriber with a variety of added per-line features to the normal BORSCHT
functions associated with the analog line circuit. Some of these features include programmable transmit and
receive gain, on-chip or custom hybrid balancing network selection and interpol,ation, a flexible signaling interface, and programmable IL or A-Law coversions. Additionally, the 29C50A can operate on either the A or B
channel of the SLD interface, allowing two combos to be connected to one SLD link.
The 29C50A is intended for use with the 2952 Integrated Line Card Controller in digital switching applications.
The 2952 handles the transfer of voice, feature control, and signaling information between the backplane and
up to 16 29C50A combos. The 29C50A is also suited for use in ISDN terminal applications.

SlGR1

EBN1

SlGR2

EBN2

SIGO

VFR-

SIGC

VFR+

SIGB

GSR
VCC

SIGA

GNOA

SlO
GNOO

TG1

SCl

vaa

SOIR

TG2

SIGX1

VFX

Figure 1. Pin Configuration

14-141

IATC 29C50A

TRANSMIT GAIN ADJUSTMENT

TG1

w

til

{

zt:!.!

C::IO

~

>

'
~8{
Ii ... ·

~~l
:I:i

,..

VFX
BALANCE
NETWORK
SWITCH

1

~8D

Zzll:

.

TG2

EBN1

r

III
~

::I'
BALANCE
NETWORK
SELECTION AND
INTERPOLATION

EBN2

SCL
CONTROL
REGISTERS
AND LOGIC

SDIR
SLD

}
II:

w

!!!

,fllIII
::)
(I)

~

,,(I)

SIGP(n)

II.

II:

SIGRln)
SIGXln)

U

zll:

II:

~~
z-

w

(I)

<:1<:1
_w

(1)11:

CONFERENCING SWITCH

j
gB
l
w
w>
u-

VFRYFR+

Vee

GSR

III

V..

II:

GNDA'

~~

w:::;

(I)

GNDD

Figure 2. Block Diagram

14-142

IATC 29C50A

Table 1. Pin Names

VFX
VFA+, VFAGNDD
GNDA
Vee
VBB
SCL
SLD

Analog Input
Analog Output
Digital Ground
Analog Ground
Power (+5V)
Power (-5V)
Subscriber Clock
Subscriber Data Link

SDIA
TG1, TG2
GSA
EBN1, EBN2
SIGX1
SIGA1, R2
SIGA, B, C, D

Subscriber Direction
Transmit Gain Adjust
Receive Gain Adjust
External Balance Network
Transmit Signaling Input
Receive Signaling Output
Programmable Transmit!
Receive Signaling Lead

Table 2. Pin Description

Symbol

Function

Symbol

VCC

Most positive suply; input voltage is + 5V
:!:5%.

VBB

Most negative supply; input volage is - 5V
:!:5%.

GNDA

Analog ground return line. Not internally
connected to GNDD.

GNDD

Digital ground return line. Not internally
connected to GNDA.

VFX

Analog voice input to transmit channel.

TGl

Inverting input to transmit gain adjusting
op-amp. Feedback point for external gain
adjusting resistor network up to 10k ohm.

TG2

Output of the transmit gain adjusting opamp. Will drive external gain adjusting resistor network up to 10k ohm.

VFR+

Non-inverting output of the power amplifier.
Capable of directly driving transformer hybrids or high impedance loads either single
ended or differentially.

VFR-

Inverting output of power amplifier. Capable o/directly driving transformer hybrids
or high impedancce loads either single
ended or differentially.

GSR

Input to receive gain setting circuit. An external resistor network connected between
VFR - and VFR +, and GSR sets the receive channel gain from OdB to -9.54dB.
Connecting GSR to GNDA will set the gain
at -6.02dB.

EBNl

Input for the first external balance network.

EBN2

Input for the second external balance
network.

SCL

Subscriber clock. Supplied by the 2952
line card controller, this is a 512 kHz, 50%
or 33% duty cycle clock. Input will accept
TTL levels.

14-143

Function

SDIR

Subscriber direction signal and frame sync.
When high, SLD becomes an input and
data is transferred from the 2952 to the
29C50A. When low, the output buffer on
the 29C50A SLD pin is enabled and data
is transferred from the 29C50A to the
2952. Input will accept TTL levelS,

SLD

Subscriber data link. A 512kbps bidirectional serial data port, wl1ich is
clocked by SCL. SLD becomes a TTL
compatible input when SDIR is high and
an output capable of driving one TTL load
when SDIR is low.

SIGXl

Transmit signaling input. Data present at
SIGXl is latched by an internal signal preceding the falling edge of SOIR and is serially transferred on SLD during the transmit
signaling byte. TTL compatible.

SIGRl
SIGR2

Receive signaling outputs. Data received
serially on SLD during the receive signaling byte is latched on these outputs during
the following byte. Capable of driving one
TTL load.

SIGA
SIGB
SIGC
SIGD

Programmable signaling pins in default
mode. If the appropriate bit in the feature
control memory is set high (either SIGDA,
SIGDB, SIGDC, or SIGDD), the corresponding pin will become a receive signaling output, like SIGR(n). If the bit in the
feature control memory is set low, the corresponding pin will become a transmit signaling input, like SIGX1. Inputs will accept
TTL level inputs, and outputs can drive
one TTL load. During channel AlB operation, the programmable signaling pins
SIGA, SIGB, and SIGC take on different
functions. If SIGA is connected to VBB,
channel A operation is selected, and SIGB
functions as an output only. If 81GB is tied
to VBB, channel B operation is selected,
and SIGA functions as an output only.
SIGC becomes a transmit only pin for both
channel A and channel B operation. 81GD
remains programmable.

inter

IATC 29C50A

FUNCTIONAL DESCRIPTION
The 29C50A is a combined channel filter and PCM.
codec for use on analog line interface circuit 'boards
in a digital telecommunications switching system.
This device resides between the circuitry which pro- .
vides the "BORSHT" functions for a given line, and
the shared line board controiler. It provides the transmit and receive voice-path fiitering and companded
analog-to-digital and digital-to-analog conversions
necessary to interface a full duplex (4-wire) voice
telephone circuit with the PCM highways of a time
division multiplexed (TOM) system.

In the default mode (neither SIGA nor SIGBtled to
VBB), all features of the 22-lead 29C50A are identical
to those of the 28-lead 29C51 except for the number
of Signaling pins and the secondary channel capabilities. There are 7 signaling channels available on
the 29C50A, configured as one transmit, two receive,
and four programmable for either direction. There are '
no se'condary analog inputs or outputs on the
29C50A; however, three-party conferencing is available. The 29C50A can alternatively be operated in
the channel A or B mode, in which case two 29C50A's
can share one SlO link.

SLD(O)
SCL
SDIR, .

XMIT

1
2

2952

•
•
•
•
•
•

BATTERY FEED
OVERVOLTAGE
RINGING
SUPERVISION
HYBRID
TEST

•
•
•
•
•

LCC

AID CONVERSION
FILTERING
LINE BALANCE
SLiC CONTROL
SPECIAL FUNCTIONS

REC

1
2

SLD(7)
CONTROL

• TEST

• POWER UP CONFIGURATION
• LINE SCAN PROCESSING
• LINE CARD CUSTOMIZING

Figure 3. Analog Llnecard

SLD Interface
The 29C50A is intended for use with the 2952 Line
Card, Controller which manages the transfer of all
voice, feature control and signaling data to and from
the Feature Control Combo and the system backplane. The interface between the two consists of just
three leads, two of which are clock signals and the
third a unique serial bus for communication. Up to
sixteen 29C50A feature control combos per line card
can be controlled by one 2952, all sharing common
clock signals, SCl and SOIR. The SlO interface is
shown in Figure 4.

The subscriber direction (SOIR) lead provides an 8
kHz signal which divides each frame into transmit and
receive halves. Ouring the first half when SOIR is high
(RCV half-cycle), data is transmitted from the 2952
to the 29C50A and in the second (XMIT half-cycle)
transfer is from the 29C50A back to the 2952. Frame
synchronization and all internal timing for the digital
circuitry is derived from the rising edge of the SOIR
signal.
The subscriber clock (SCl) input generated by the
2952 is a fixed 512 kHz clock Signal allowing 64 bits
(8 bytes) of data to be transferred on the SlO lead

14-144

IATC 29C50A

I
:
I

I

RECEIVE HALF-CYCLE
2952-+29C50A

TRANSMIT HALF-CYCLE
29C50A-+2952

I

SDIR

I
I

I

~I

! -_ _ _ _ _ _ _ _

~I

r---~--,_--_r--_+--_,--~~--~~I

SLD ____~~--L-~-L~~L-~_+I--~L-~~--~~~~I~---

I

I

VOICE

I

I

CONTROL
I
SIGNALING :

CONTROL
I
SIGNALING :

I
1 FRAME
1.--------- 512
(125 pS) --------+1_1
KBPS
I

Figure 4. 29C50Al2952 Interface

during each 12S JLSec frame. Depending on 29S2
master clock frequency, the SCl duty cycle can be
either SO% or 33%.
The subscriber data link (SlD) is a bi-directional serial
bus that transfers eight bytes of serial data to and
from the 29CSOA each frame. During the first half of
each frame, RCV channel information is transferred
to the 29CSOA in four bytes consisting of channel A
voice, channel B voice, feature control, and signaling
information. Similarly during the second half-cycle,
four bytes of XMIT channel information are sent to
the 29S2. The MSB (bit 7) of each byte is sent first
on the SlD. After the last valid signaling bit is transmitted to the 2952, the bus is placed in a high impedance state for at least one SCl clock cycle to prevent
data contention on the bus. (See FCB #6 - Signaling
Register.)
Upon power supply application and clocks SCl and
SDIR applied, the 29CSOA will automatically enter the
power down state. During the transmit half-cycle
(29CSOA talking to the 29S2) a code of all ones will
be sent to the controller during the channel A or B
byte depending upon the selected mode. The
29CSOA SlD pin will be placed in a high impedance
state during the unused channel.

Channel AlB Operation
The 29CSOA can use either channel A or channel B
on the SlD interface for transfer of PCM voice. This
allows two 29C50A combos to share a single SlD
link, allowing up to sixteen combos to be controlled
by one 2952 line card controller. The channel AlB
mode is selected with the SIGA and SIGB pins. If
SIGA is connected to VBB, the 29CSOA will use channel A, and if SIGB is connected to VBB, the 29CSOA
will use channel B. If neither pin is connected to VBB,
the 29CSOA will operate identically to the 29CS1 Feature Control Combo, except for the lack of secondary
analog channels. Connecting both SIGA and SIGB
to VBB is not allowed. Operation of the combo on the
SlD interface is shown in Figure S.
When programming the 29C50A, the least significant
bit (last bit transmitted) of the first control byte of a
programming frame selects the 29CSOA which will
accept this and all following bytes of the frame. Only
the lSB of this first framing byte is used as a channel
select bit. It is latched until the next framing byte (00
or 01 header) is received in the feature control channel. If this bit is a zero, the channel A combo will
accept the programming data, and if this bit is a one,
the channel B combo will accept the data. Only the
selected combo will echo back the programming data.

14-145

inter

IATC 29C50A

XMIT
29C50A.... 2952

RCV
2952.... 29C50A

s~

SLD

I

~

A

B I

C

I"B" I I

________ ____
~

A

"A"

B

c

~r

I"B" I I
"A"

~E

RECEIVE
DATA " A \
OR CONFERENCING DATA ':'B" \
RECEIVE VOICE DATA "B"
OR CONFERENCING DATA "A"

Figure 5. SLD Data Format in "AlB Operation"
Similarly, when verifying thEl feature control memory
of the 29C50A, the desired device is selected using
the least Significant bit of the first byte of the verification frame. Only the selected device will respond.
Because the LSB of the feature control framing byte
must be set to a one for verification of a channel B
device, the 2952 will actually read back 10 bytes from
the SLD interface when using the bi-directional FIFO
(BFF). Only six of these bytes will contain the 29C50A
programming information. Refer to the 2952 Reference Manual for further details regarding verification
of feature control information from an SLD slave device using the 2952.

tively of byte 8 on the SLD. A channel B part will send
data from those same pins in bit positions 7, 6, and
5 respectively of byte 8. Neither combo will drive the
SLD line during the third or seventh bits. '

When neither device is being programmed or verified,
the last selected device will echo the received control
channel data during the transmit half of the SLD
frame.

TRANSMIT AND RECEIVE OPERATION

In order to take full advantage of the last look change
detection logic of the 2952, the two 29C50A combos
using one SLD line share the signaling channels each
frame. Each uses a nibble of the transmit and receive
. signaling bytes. Since one signaling pin is used to
select channel A or B operation, six pins are available
for carrying signaling data, with three configured as
receive, two as transmit, and one programmable.
For a channel A device, data received during bits 3,
2, 1, and 0 of byte 4 on the SLD will appear at SIGR1,
SIGR2, SIGB, and SIGD (if SIGD is chosen as a
receive bit), respectively. For a channel B device, the
data from bits 7, 6, 5, and 4 of byte 4 appears at
SIGR1, SIGR2, SIGA, and SIGD (if SIGD is chosen
as a receive bit), respectively.
In the transmit direction, a channel A part will send
data from SIGX1, SIGC, and SIGD (if SIGD is chosen
as a transmit bit) in bit positions 3, 2, and 1 respec-

Figure 4 shows operation of the 29C50A on the SLD
interface in the default mode, when neither the channel A nor channel B mode is selected (neither SIGA
nor SIGB connected to VBB).
Signaling field formats for all three modes are shown
in Figure 11.

Transmit Filter
A low pass anti-aliasing section is included on chip.
This section typically provides 35dB attenuation at
the sampling frequency. No external components are
required to provide the necessary anti-aliasing function for the switched capacitor section cif the transmit
filter.
The passband section provides flatnes~ and stopband attenuation which fulfills the AT&T D3/D4 specification and the CCITT G.712 recommendation. The
29C50A specifications meet the digital class 5 central
office switching systems requirements. The transmit
filter transfer characteristics and specifiations will be
within the limits shown in Figure 12.
A high pass section configuration rejects low frequency noise from 50 and 60 Hz power lines, 17 Hz
European electric railroads, ringing frequencies and
their harmonics, and other low frequency noise. Gain
of lip to 20dB can be set without degrading the performance of the filter.

14-146

"nt_l®
II I-e-·

IATC 29C50A

Encoding

. components by strapping pin GSR to VFR -, GNOA,
and VFR +, respectively.

The output of the transmit filter is internally sampled
by the encoder and held on an internal sample and
hold capacitor. OC offset is corrected by an on-chip
auto zero circuit. The signal is then encoded and
presented as PCM data on the SLO lead on the first
8 bits of the XMIT half frame (fifth byte) for channel
A operation, or the second 8 bits (sixth byte) for channel B operation.

RT2

~

RTf

'f 'f
TG1

TG2

Decoding
The PCM words received on the SLO are demultiplexed and sent to the decoder. For channel A operation, the first SLO byte is decoded. For channel B
operation the second SLO byte is used. The decoded
value is held on an internal sample and hold capacitor.
If, however, conferencing has been selected, both the
first and second SLO bytes will be decoded, added,
and subsequently passed to the receive filter.

VFRRR2
GSR
RR1
VFR+
GNDA

~

Receive Filter

Figure 6. External Gain· Connections
The receive section of the filter provides a passband
flatness and stopband rejection which fulfills the AT&T
03/04 specification and the CCITT G.712 recommendation. The receive filter transfer characteristics
and specifications will be within the limits shown in
Figure 13.

GENERAL OPERATION
External Gain Setting
Both transmit and receive gain levels are factory
trimmed, but can be modified by external resistors
during line card assembly. The value of transmit gain
is adjusted by connecting resistors RT1 and RT2 (see
Figure 6) at the two external gain setting control pins,
TG1 and TG2. These two pins are the input and output of an on-board gain amplifier stage, and the resistors provide the necessary input and feedback for
gain control. The value of external gllin is given by:

Hybrid Balancing Network
The 2- to 4-wire conversion necessary for subscriber
interface is partially integrated on-chip. Network line
balancing needed to minimize the trans-hybrid loss
from the receive to transmit direction analog signals
is handled internally. The three internal networks
shown in Figure 8 may be selected by programming
the appropriate feature control byte. These networks
are integrated in a switched capacitor configuration
and have single pole-zero characteristics in the 200
Hz to 3200 Hz range. They were chosen to serve a
wide base of U.S. an European requirements, and
can be used as standard line balancing networks or
as test networks.

A = 1 + RT1/RT2
For unity gain, pins TG1 and TG2 are tied together.
Similarly, for the receive section, external resistors
RR1 and RR2 at pins VFR+, GSR, and VFR- set
the external gain given by:
A = (RR1 + RR2)/(RR1 + 3RR2)
A value greater than 10k ohms and less than
1OOk ohms for R1 + R2 is recommended. The output
is capable of driving loads of 300 ohms at 3.2Vp
single ended or 600 ohms at 6.4Vp differentially.
Three additional gain settings of OdB, - 6dB, and
- 9.54dB can be realized without using any external
14-147

Figure 7. External Balance Network and
Interpolation Configuration

IATC 29C50A

6000

9000

,.-- --,

Zo

I
I
I
I
I

Zo

I

I ~

r--

II

19000
I
I

I
I

L ___ ..J1 2•2pF

9000

,..,

Zo

16000

"on :

I

~

,.-- ---,
I
I
I

I

'1: . ".
I
I
I

I
I
IL _ _ _ _ oJI

L ___ oJ12.2pF
1

'V
NETWORK #1
(TBN1)

NETWORK #2
(TBN2)

NETWORK #3
(TBN3)

Figure 8. Internal Balance Networks

16S00

8000

9000
~

.00SpF 1000

.0SpF

1000

ls2

ls1

Zo

f m,n -..

w_
u

-0.105

zc:
:s~
~"'~"'~~~~~~""'~'i'

'OJdB

','OdS
3lOOHl
:MOOHI

freq. = 1.02kHz for all
steps

I

o

.,

____ TYPICAL fll TER

TRANSFER FUJ'K:TION

FRECUENCY!Hrl

Figure 12. Transmit Voice Frequency Characteristics

14-156

'X,"".,•
SCALE

IATC 29C50A

RECEIVE FOICE FREQUENCY CHARACTERISTICS
GSR = VFR -. Receive Programmable Gain = OdB
Symbol
GRR

Parameter

Typ

Min

Units

Test Conditions
OdBmO input on SLD

Below 200Hz

+0.125

dB

-0.5

+0.125

dB

300 to 3000Hz

-0.125

+0.125

dB

3300Hz

-0.35

+0.03

dB

3400Hz

-0.70

-0.1

dB

-14
-30

dB
dB

200Hz

4000Hz
4600Hz & Above
aG pR

Max

Gain Relative to gain at
1.02kHz

Programmable Gain Accuracy
(Commulative Error

• 125<1B
2001'1.

dB

+.25

• 12!idB

+.125<18

"""H. ,

JOOIi,

f = 1.02kHz all steps

EXPANDED
'03dB
3lOOH.

SCALE

, 30001-1,
-",,,~;it~H'
-.)leI.
·3JOOH,
• .10••

• :MODH.

.

-14<18

OOOOH.

FAEaUENCV IH"

I'IOHS
1 TV1ICAL TRANSFER ~U"'Cll()Pj O~ 1H! REC(IIiE fit TEA AS ill U'AAAU COMI'OHENt
2 TY"CAl TAANSftA FUi'lCTION Of tHE REC(lVE fit"!! DAIVEN IV THE U .... 'U APriO

~~~~~;~E'(~:

: : : ~~!..~~r:(~~fig;:,~sCOD(CS TlfE COMBINED mnAICDOEC

Figure 13. Receive Voice Frequency Characteristics

14-157

inter

iATC 29C50A

A.C. CHARACTERISTICS - TIMING PARAMETERS
Typ
Symbol
Parameter
. Min
Toc

SCL Duty Cycle

Units

Test Conditions

28

33

·38

Max

%

45

50

55

%

2952 ClK Clock = 1.544 or
1.536MHz
2952 ClK Clock ;;.
2.048MHz

T AC
TFc

Rise, Fall Times, SCl

50

ns

TAD
T Fo

Rise, Fall Times, SlO

50

ns

TOIAA

SCl to SOIR Delay

-150

150

ns

TOIAF

SCl to SOIR Delay

-150

+420

ns

Too

SCl to

0

200

ns

29C50A Transmitting

Tso

Set-up Time, SlD to SCl

100

ns

2952 Transmitting

THO

Hold Time, SCl to SlD

100

THZ1

SDIR to SlD Active

0

100

ns

Byte 1, Bit 1 29C50A
Transmitting

THZ2

SCl to SlO High Impedance

0

100

ns

After last SIGX bit

Tss

Set-up time, signaling inputs to
SlD Byte #3, Bit 0

1

f.LS

T HS

Hold time, SlD Byte 4 Bit 7 for
all signaling inputs

1

f.LS

Tos

Delay SlD Byte 5 to signaling
outputs

sLo

Delay

ns

1

f.LS

SCL to Channel Active

0

100

ns

SCl to Channel High Impedance

0

100

ns

'In cases where the TOIF is positive, Too is to be measured from the SOIR edge.

14-158

Channel A or B, Feature
Control, Signaling as
Appropriate (Channel AlB
Operation)

inter

IATC 29C50A

TIMING PARAMETERS (ClK

= 1.544 MHz, 33% duty cycle)

CLK
IRC ~I-_"'_~

SCL

IDIRR
SDIR

~~
---c=x===x:

.
SLD

-'..-""OI..r--""""

SIGNALING TIMING

BYTE 3

OUTPUTS

BYTE 4

BYTES

OLD

A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUT/OUTPUT

A.C. TESTING: INPUTS ARE DRIVEN AT 2.4Y FOR A LOGIC "1" andOA5V FOR A
LOGIC "0'. nMING MEASUREMENTS ARE MAOE AT2.DVFOR A LOGIC "'" AND
O.IV FOR A LOGIC "0".

14-159

i®ATC 29C48
FEATURE CONTROL COMBO
.• External and User Programmable
Transmit and Receive Gain
• Programmable External Hybrid Balance
Network Select
• Programmable Analog, Digital, and
Subscriber Loopback

• Programmable piA-Law Select
• Secondary Analog Input.Channel
• Low Power Consumption
• External tone Injection to Receive Path
• SLD AlB Channel Select (for 16 Channel
Line Cards)

The Intel i®ATC 29C48 Feature Control Combo is a low cost, user-programmable, fully integrated PCM Codec
with transmit/receive filters fabricated in a CMOS technology. This technology is built on CHMOS and will allow
the 29C48 to realize the same excellent transmission performance as· in the Intel 2913/2914 combo while
achieving the low power consumption typical of CMOS circuits.
The 29C48 supports the analog subscriber with a variety of added per-line features to the normal BORSCHT
functions associated with the analog line circuit. Some of these features include secon·dary analog input channel,
programmable transmit and receive gain, custom hybrid balancing network selection, and programmable f.L or
A-law conversions. Additionally, the 29C48 can operate on e.ither the A or B channel of the SLD interface,
allowing two combos to be connected to one SLD link. In order to facilitate the SLiC interface in this configuration,
the 29C48 generates chip select signals for the proper routing of signaling inforll)ation.
A unique feature of the 29C48 is programmable tone injection. This feature and itsSLD interface makes it
particularly easy to use in conjunction with Intel's advanced tranceivers, such as the i®ATC 29C53, in subscriber
equipment environments.
The 29C48 is intended for use with the 2952 Integrated Line Card Controller in digital switching environments.
These components allow the system transmit and receive backplane highways to operate at different frequencies
from that of the subscriber interface data channels. The 2952 handles the transfer of voice and feature control
information between the backplane and the 29C48.

vee

VBB
VFR
EBN1
EBN2
EBN3IT1
EBN
SCS

VFX
.TG1
TG2
GNDA
SAl
SLD
SDIR
SCL

BlA
GNDD

Figure 1. Pin Configuration

14-160

I®ATC 29C48

TRANSMIT GAIN ADJUST
, TG1

T-G-2 .....,

.A....-

ANALOG LOOPBACK
VFX 0-+-440-+-----1

r---I-OSAI
PROGRAMMABLE
BALANCE NETWORK
GAIN (1 OR 2)
BALANCE
NETWORK
ENABLE
EBNo--r-+-------~

B/A

o-+-+-----------------l

EBN10--r-+--+-~

p/ALAW
FEATURE
CONTROL
REGISTERS
AND LOGIC

b--I---I-OSLD

EBN20--r-+--~0-

L....---r-~

TIIEBN3 o--+--+-......-If-O.....
BALANCE
NETWORKS
SELECTION
UNIT

SCS 0 - + - + - + - 1

VFR

I----I---~O::~}

SCS
GENERATION

o--+-......- - - C

RECEIVE
FILTER
RECEIVE PROGRAMMABLE GAIN

VCC

VBB

GNDA

GNDD

Figure 2. Block Diagram
14-161

FROMrrO
2952

j®ATC 29C48

Table 1. Pin Names

VFX
VFR

SCl
SlD

GNDD
GNDA
VCC

Analog Input
Analog Output
Digital Ground
Analog Ground
Power (+5V)

SDIR
TG1, TG2
EBN1/2

VBB

Power (-5V)

EBN31T1

BIA
SCS

Channel Selection
SLiC Chip Select

EBN
SAl

Subscriber Clock
Subscriber Data Link
Subscriber Direction
Transmit Gain Adjust
External Balance Network
Selection Inputs
External Balance Network
Selection Input Or Tone
Injection
External Balance Input
Secondary Analog Input

Table 2. Pin Description

Symbol

Symbol

Function

+ SV

VCC

Most positive supply; input voltage is
±S%.

VBB

Most negative supply; input voltage is
-SV ±S%.

GNDA

Analog ground return line. Not internally
connected to GNDD.

GNDD

Digital ground return line. Not internally
connected to GNDA.

VFX

Analog voice input to transmit channel. Input impedance is typically larger than
100 K-ohms.

TGI

Inverting input to transmit gain adjusting
op-amp. Feedback point for external gain
adjusting resistor network or frequency
compensation network. Input impedance is
typically larger than 10M-ohms.

TG2

Output of the transmit gain adjusting opamp. Will drive external gain adjusting resistor network as well as frequency compensation network with impedance at least
larger than 10k ohms.

VFR

Receive voice output. Capable of directly
driving tram;former hybrids or impedance
loads of 600 ohms or more.

EBN

Input to the hybrid balancing circuit. Input
impedance is typically larger than 10 Mohms.

EBN1

Input connected to a grounded switch. The
switch's on resistance is not greater than
600 ohms.

EBN2

Input connected to a grounded switch. The
switch's on resistance is not greater than
600 ohms.

14-162

Function

EBN31T1

This pin is multiplexed according to the
feature control registers. When programmed to be EBN3, it is an input connected to a grounded switch. The switch's
on resistance is not greater than 600
ohms. If this pin is programmed to be TI,
an analog signal applied on this pin will be
added to the received voice signal before
the receive power amplifier.

SCL

Subscriber clock. Supplied by the line card
controller, this is a S12 kHz, SO% or 33%
duty cycle clock. Input will accept TTL
levels.

SDIR

Subscriber direction signal and frame sync.
When high, SLD becomes an input and
data is transferred from the line card controller to the 29C48. When low, the output
buffer on the 29C48 SLD pin is enabled
and data is transferred from the 29C48 to'
the controller. Input will accept TTL levels.

SLD

Subscriber Line Datalink. A 512 kbps bidirectional serial data port, which is
clocked by SCL. SLD becomes a TTL
compatible input when SDIR is high and
an output capable of driving one TTL load
when SDIR is low, during the appropriate
SLD fields for the assigned channel.

B/A

Pin strapped to assign the 29C48 to process either A or B channel information
from the SLD bus. A low level (GNDD) on
this pin selects channel A, a high level
(VCC) channel B.

SCS

This pin is a TTL compatible output capable of driving one TTL load: when low, it
informs a SLiC device connected to the
same SLD bus as the 29C48 that it can
process the receive and transmit signalling
data of the present SLD frame.

SAl

Secondary analog input.

j®ATC 29C48

FUNCTIONAL DESCRIPTION
The 29C48 is a combined channel filter and PCM
codec for use on analog line interface circuit boards
in a digital telecommunications switching system.
This device resides between the circuitry which provides the "BORSHT" functions for a given line, and
the shared line board controller. It provides the transmit and receive voice-path filtering and companded
analog-to-digital and digital-to-analog conversions
necessary to interface a full duplex (4-wire) voice
telephone circuit with the PCM highways of a time
SLIC (x16)

division multiplexed (TDM) system. (See Figures 3a
and 3b for typical line card applications.)
The 29C48 incorporates additional features making
it particularly suited to subscriber applications. Tone
injection allows easy implementation of DTMF feedback and side tone injection, and secondary analog
signal input allows remote control and monitoring.
(See Figure 4 for a typical subscriber card
application.)

COMBO (x16)

,.....

LCC (xl)

SLO BUS (x8)

BACKPLANE

VFX

~L

SLIC OA

VFR

cs

29C48
OA

r--

SCS

BIA
SELECT

i~

SCL

TOM HWYS

SOIR

J
r-..

~L

SLOO

cs

•
•• _
SL07

SCS
29C48
VFX OB

SLIC OB

LINE
CARD
CONTROLLER

t-B/A SELECT

VFR

SYNC

_ll_

,

~

SIGNALING

SIG HWY

v

p.P

Figure 3a. Analog Line Card With Discrete Or Electronic Parallel Control SLiCs
SLIC (x16)

COMBO (x16)

n

~L

VFX
VFR

SLIC OA

cs

29C48
OA

SLO BUS (x8)

I---

LCC (xl)

BIA
SELECT

SCS
SCL

I---- TOM HWYS

SOIR
SLOO

"
;;..JL

cs
SLiC OB

BACKPLANE

•••
SL07"""""'::'SCS 29C48
VFX
OB
VFR

I+-B/A SELECT

2952
LINE CARD
CONTROLLER'

r---

~ SYNC

"1

r-

~ I,
r--~---'

IL _ _
p.P
I
_ _ ..J
Figure 3b. Analog Line Card With SLD Compatible SLICs
14-163

SIG HWY

i®ATC 29C48

SUBSCRIBER EQUIPMENT

I ..s .. INTERFACE

I

SCl

SOIR

29C48

c

c

29C53

SlO

p.P

Figure 4. Subscriber Card

TRANSMIT AND RECEIVE OPERATION
Transmit Filter

Decoding

A low pass anti-aliasing section is included on chip.
This section typically provides 35dB attenuation at
the sampling frequency. No external components are
required to provide the necessary anti-aliasing function for the switched capacitor section of the transmit
ffi~~
.

The PCM word received on the SLO lead (first or
second byte of the receive half-frame, depending
upon the channel assignment of the device) is sent
to the decoder after a serial to parallel conversion.
The decoded value is held on an internal sample and
hold capacitor.

The passband section provides flatness and stopband attenuation which fulfils the AT&T 03/04 specification and the CCITT G.712 recommendation. The.
29C48 specifications meet the digital class 5 central
office switching systems requirements. The transmit
filter transfer characteristics and specifications will be
within the limits shown in Figure 12.

Receive Filter

A high pass section configuration rejects low frequency noise from 50 and 60 Hz power lines, 17 Hz
European electric railroads, ringing frequencies and
their harmonics, and other low frequency noise. Gain
of up to 20dB can be set without degrading the performance of the filter. The transmit filter also provides
additional loss at 12 KHz and 16 KHz (frequencies
of metering pulses).

Encoding
The output of the transmit filter or the secondary analog input is internally sampled by the encoder and
held on an internal sample and hold capacitor. OC
offset is corrected by an on-Chip auto zero circuit. The
signal is then encoded and presented as PCM data
on the SLO lead. (First or second byte of the transmit
half-frames depending upon the channel assignment
of the device.)

The receive section of the filter provides a passband
flatness and stopband rejection which fulfills the AT&T
03/04 specification and the CCITT G.712 recommendation. It also provides additional loss at 12 KHz
and 16 KHz. The receive ffiter transfer characteristics
and specifications will be within the limits shown in
Figure 13.

GENERAL OPERATION
External Gain Setting
Both transmit and receive gain levels are factory
trimmed, but can be modified by external resistors
during line card assembly. The value of transmit gain
is adjusted by connecting resistors RT1 and RT2 (see
Figure 5) at the two external gain setting control pins,
TG1 and TG2. These two pins are the input and output of an on-board gain amplifier stage, and the resistors provide the necessary input and feedback for
gain control. The value of external gain is given by:
A = 1

+ RT1/RT2

For unity gain, pins TG1 and TG2 are tied together.

14-164

I®ATC 29C48

For the receive section, the external gain can be set
by the external resistors, RR1 and RR2. There are'
two possible ways of implementing the gain control.
The first is illustrated in Figure 6a, where the value
of the receive gain is given by:
A = RR2/(RR1

+

RT2

-=

RT1
TG2

TG1

RR2)

The value of RR1 + RR2 should not be less than
600 ohms to avoid degrading the output power
stage's performance. The second way of implementing the receive gain is shown in Figure 6b, where
pin EBN3/T1 is used. The value of the receive gain
in this configuration is given by:

VFX 0-+------1

A = 1 + RR1/RR2
Figure 5. Transmit Gain Setting

Hybrid Balancing Network
Three external balancing networks can be applied to
the 29C48 by the user to accommodate varying subscriber loop characteristics (see Figure 7 for external
connections). Feature control allows the grounding of
any combination of these networks in order to best
suit a particular application. Feature control also allows the user to select a gain of 0.0 or + 6.0dB in the
balance signal path to suit the type of SLiC used.

29C48

VFR
RR1

FREQUENCY COMPENSATION
The user may, if desired, compensate for the frequency response characteristics of the SLiC by adjusting the frequency response of the transmission
chain. This can be accomplished in the same way as
the external gain setting is done in the transmit and
receive directions. But, instead of using purely resistive impedances, resistor and capacitor networks
have to be used to achieve complex impedances. The
two compensation schemes are shown in Figures 8a
and 8b. The gains in the transmit and receive directions are respectively:
for Figure 8a

A = 1 + ZT1/ZT2

for Figure 8b

A = 1

RR2

Figure 6a. Receive Gain Setting

29C48

VFR

+ ZR1/ZR2

RR1

SECONDARY ANALOG INPUT

EBN31T1

Although the main application of the 29C48 will be
for voice transmission, it also offers a secondary unfiltered input channel. Narrow band analog signals
.can be supplied through this channel for remote loop
testing and various control uses.
The secondary analog input channel is accessed under software control through the SAl input. When the
SAlE bit in the feature control register is set to a
14-165

RR2

Figure 6b. Receive Gain Setting

I®ATC 29C48

VFX

logical one, the 29C48 will encode and transmit the
. signal present althe SAl input. The 29C48 will switch
back to transmission of the voice signal as soon as
the SAlE bit is set back to a logical zero..

TONE INJECTION
EBN

When specified by the feature control memory, an
audio frequency signal applied to the EBN31T1 pin will
be added to the receive voice signal at the power
amplifier. This feature allows easy implementation of
DTMF feedback and side tone injection in digital telephone applications, as well as injection of call waiting
or metering tones in line card applications. A typical
application is shown in Figure 9. Here VFR is the
combination of the receive voice signal (VO) and two
tones (V1 and V2).
VFR

= 2VO +

(V1 + V2)/2

CHANNEL ASSIGNMENT

Figure 1. Balance Networks

Two 29C48s can be attached to the same SLD line
to exchange information with the line card controller
during each SLD frame.
The B/A pin of the 29C48 is used to assign a voice
channel of the SLD frame to the device. When the
B/A pin is tied low, the 29C48 operates as an Achannel combo, receiving and transmitting voice during the first and fifth bytes of the SLD frame . When
this pin is tied high, the 29C48 operates as a Bchannel combo, receiving and transmitting voice dur~
ing the second and sixth bytes of· the SLD frame.

Figure Ba. Transmit Frequency Compensation
29C48
. VFR

RO
EBN3fT1

2RO

Vl---'l.I\II,~"

2RO
V2---JWI~""

Figure Bb. Receive Frequency
, Compensation

Figure 9. External Tone

14-166

Inj~ction

j®ATC 29C48

The feature control receive and transmit channels of
the SLD frame are shared by the two 29C48s. A
29C48 will accept or return feature control information
only if it has been instructed to do so during the first
byte of a feature control frame. This is accomplished
by setting the logic level of the channel selection bit
in feature control byte #1 to match the logic level of
the BIA pin of the appropriate 29C48. The selected
29C48 will keep exchanging feature control information with the line card controller until a new framing
byte makes a new selection. The status of the channel
select bit is sent back to the line card controller during
the seventh byte of each SLD frame, making it possible to determine which channel is transmitting feature control information.
The 29C48 does not process data received in the
signaling channel. However, it generates chip select
Signals during the appropriate time slots in order to
facilitate the SLiC interface. (See section on SUC
Chip Select.) The 29C48 enters into a high impedance state during the signaling transmit channel, the
eighth byte of the SLD frame.
SlIC Chip Select
In order to facilitate interfacing to an SLD compatible
SLlC, especially when two SUCs share the same
SLD line, the 29C48 includes a programmable chip
select Signal.
During the receive cycle of the SLD frame, the SCS
pin of the 29C48 whose channel selection pin (B/A)
has the same logic state as the channel selection bit
(see previous section on Channel Assignment) is
pulled low during the receive signalling byte.
During the transmit cycle of the SLD frame, the SCS
signal can operate in two modes. In the first mode,
called 'byte mode,' the SCS pin of the selected 29C48
is pulled low during the transmit Signaling byte, as
described above for the receive direction.
A second mode, called the 'half-byte mode,' is provided to take full advantage of the last look change
detection logic of the 2952 line card controller. In this
mode, during the transmit cycle of the SLD frame,
the SCS pin of the channel A combo is pulled low
during the least significant four bits (last four bits) of
the transmit signaling byte. During the same frame,
the SCS pin of the channel B combo is pulled low
during the most significant four bits (first four bits) of
the transmit signaling byte. This allows signaling data
from both A and B channel SLD compatible SUCs to
be processed by the 2952 during the same frame.
To minimize power consumption, operation of the
SCS signal during the receive half of the SLD frame

can be disabled through the feature control memory.
Operation of this signal in the transmit direction remains unaffected to allow continued monitoring of
subscriber status by the 2952. The SCS signal remains active in the power down mode.
The six possible sequences for SCS are shown in
Figure 10.

Precision Voltage References
Voltage references are generated on-chip and are
trimmed during the manufacturing process. Separate
references are supplied for both the transmit and receive sections of the chip, each trimmed independently. These references determine the gain and dynamic range of the device and provide the user a
significant margin for error in other board
components.

SLD Interface
The 29C48 is intended for use with the 2952 Line
Card Controller which manages the transfer of all
voice and feature control data to and from the Feature
Control Combo and the system backplane. The interface between the two consists of just three leads,
two of which are clock signals and the third a unique
serial bus for communication. Up to sixteen 29C46
feature control combos per line card can be controlled
by one 2952, all sharing common clock Signals, SCL
and SDIR.
The subscriber direction (SDIR) lead provides an 8
kHz signal which divides each frame into transmit and
receive halves. During the first half when SDIR is high
(RCV half-cycle), data is transmitted from the 2952
to the 29C48 and in the second (XMIT half-cycle)
transfer is from the 29C48 back to the 2952. Frame
synchronization and all internal timing for the digital
circuitry is derived from the rising edge of the SDIR
signal.
The subscriber clock (SCL) input generated by the
2952 is a fixed 512 kHz clock signal allowing 64 bits
(8 bytes) of data to be transferred on the SLD lead
during each 125 f.LSec frame. Depending on 2952
master clock frequency, the SCLduly cycle can be
either 50% or 33%.
The Subscriber Line Datalink (SLD) is a bi-directional
serial bus that transfers four bytes of serial data to
and from the 29C48 each frame. During the first half
of each frame, RCV channel information is expected
by the 29C48 as two bytes consisting of voice and
feature control information, while the other two bytes
of the RCV half frame are simply ignored. Similary,
during the second half frame, one byte of voice and,

14-167

j®ATC 29C48

if so Instructed by the line card controller, one byte
of feature control information is sent by the 29C48.
The 29C48 places its SLD lead in a high impedance
state while the other device connected to the SLD
line transmits its own information. The most significant bit (bit 7) of each byte is sent first on the SLD
line. The data format of an SLD frame is shown in
Figure 11.
Upon power supply application, the 29C48 enters into
a power on reset sequence. At the end of the reset
sequence, it is prevented from transmitting data for

four SLD frames, and it is unable to process data
from the line card controller for eight SLD frames.

PROGRAMMABLE FEATURES
The 29C48 is configured by the 2952 line card controller by a set of five feature control bytes (FCB).
These bytes of information are stored in internal registers which are serially multiplexed to and from the
SLD interface in the third and seventh byte locations.
The first two bits of each byte consist of a multiframe

.,... THE CHANNEL SELECTION BIT (SEE SECTION ON CHANNEL ASSIGNMENn IS ZERO/BYTE MODE RECEIVE

1

B

A

HALF-FRAME--~'--II4----TRANSMIT HALF-FRAME-........--II
C

S

sl

ABC

A-CHANNEL SCS

\'-_--1,-----

\'-_--1'
II-C~ANNEL

SCS

- THE CHANNEL SELECTION BIT IS ONE/BYTE MODE -

I. . .

----RECEIVE HALF-FRAME - -.....

IA

B

C

II~TRANSMIT HALF-FRAME - -...-11

S

sl

ABC

A-CHANNEL SCS

,

II-CHANNEL SCS

\

\'-_--1,---

- THE CHANNEL SELECTION BIT IS ZERO/HALF-BYTE MODE -

I

I+-RECEIVE HALF-FRAME---I••II4---- TRANSMIT HALF-FRAME _ _

1

AI

B

1 cl

S

A-CHANNEL SCS

\

1

.,

AI

B

1 c 1

B-CHANNEL SCS

u
Figure 10.

ScS Timing Diagram
14-168

S

1

i®ATC 29C48

synchronization and write enable code. The framing
bit (bit 7, MSS) establishes the beginning of a feature
control frame when set to a logical zero, and increments the feature control counter when set to one.
The second (bit 6) enables the writing to the 29C48
when it is the logical complement of the framing bit.
In addition to the two header bits, feature control byte
#1 also includes a channel selection bit (bit 0, LSS).
This bit is used to designate one of the two 29C48s
sharing an SLD link for feature control information
exchange. (See previous section on Channel
Assignment.)

-

When writing new feature control information to the
29C48, the first byte should contain a framing (F) and
write enable (WE) header of 01 (F =0 and WE = 1),
and an appropriate channel selection bit. This designates a new frame of information to transfer. The
subsequent bytes should each have F = 1 to advance
the counter, and WE = 0 to enable the write operation.
The controller can also request to verify the feature
control register contents by sending a 00 or 11 at the
beginning of the byte to be read. To read the first
byte, a 00 FIWE code and an appropriate channel

THE CHANNEL SELECTION BIT IS ONE/HALF-BYTE MODE --_e*"'I----TRANSMIT

B

HALF-FRAME~

I cis I
u

- MINIMUM SCS GENERATION/BYTE MODE -

I~
I

"I~

RECEIVE HALF-FRAME
A

B

C

s

I

TRANSMIT
A

I

B

HAi..F-FRAME~
I

c

I

s

I

A-CHANNEL SCS SELECTED

~

\
B-CHANNEL SCS SELECTED

- MINIMUM SCS GENERATION/HALF-BYTE MODE -

~ RECEIVE HALF-FRAME
ABC

S

IA

I

B

I

c

I

A-CHANNEL SCS

B-CHANNEL SCS

u
Figure 10_

"I

"I_TRANSMIT HALF-FRAME

i'Ci Timing Diagram (continued)
14-169

s

I

j®ATC 29C48

I
:
I

I

RECEIVE HALF-CYCLE
2952-29C48

I

SDIR

I
I

I

'TRANSMIT HALF-CYCLE
29C48-+2952

I

:
I

I

~II!-_ _ _--.____~rr----r----r---~----+I----~--_,----,_--_;I

SLD----~I~--L-~-L~--L-~_+I--~~~~--r-~-r~I-----

I VOICE A
:
I
I

: VOICE A
:
I
VOICEB
I
CONTROL
I
CONTROL
I
SIGNALING:
SIGNALING:

1~~

:
" " '_
1
_-

-

-

-

-

-

-

I

(125,..6)
512 KBPS

1

-I

I

VOICE A, VOICE B: A AND B CHANNEL VOICE BYTES RESPECnVELY.
CONTROL:
FEATURE CONTROL INFORMAnON. THIS INFORMATION IS EXCHANGED WITH THE 29C48 WHOSE CHANNEL SELECTION PIN MATCHES THE CHANNEL SELECTION ,BIT OF THE LATEST FRAMING FEATURE CONTROL BYTE.
SIGNALING: SIGNALING INFORMATION WHICH CONTROLS THE SUBSCRIBER LINE. THE 29C48 ENTERS INTO A HIGH IMPEDANCE
STATE DURING THIS TIME SLOT, AND GENERATES A CHIP SELECT SIGNAL (SEE SECTION ON SLiC CHIP SELECT).

Figure 11. 29C48/2952 Interface

selection 'bit should be sent while each subsequent
byte should have a 11 header. An internal six-stage
counter is set on the first byte verified then incremented once each 125/-15 frame. It is reset only upon
detection of a 01 or 00 FIWE. Once the counter is
greater than five, neither read nor write modes may
be selected by sending the 29C48 a 11 or 10 framing
and write enable code. While in this state, the 29C48
will then echo in byte 7 the data it received in byte 3.
Another feature control information exchange cycle
can only be initiated by establishing a new feature
control frame (sending F=O).

FCB #1 - Power Up/Down, Loop Back
Mode, piA-Law, Channel Select Register
POWER UP AND DOWN
The 29C48 can be instructed to go into the power
down or standby mode for reduced power consumption. In this mode, all analog inputs and outputs are
placed in a high impedance state, inhibiting voice
signals. A code of all ones will be output in the voice
byte on the SLD. Signaling and feature control information will continue te;> be processed to allow the
29C48 to be read or reprogramed.

The 2952 can change the state of the feature control
combo from standby to active by sending the first
feature control byte only. All other register contents
will be preserved during power down provided the
power supplies remain connected.

LOOP BACK MODE SELECT
Three modes of remote testing are incorporated in
the 29C48 and can be selected by appropriate coding
in this register. The loopback features allow a number
of tests to be performed to determine line quality and
balancing. These include digital loop back, analog
loop back, and subscriber loop back.
In the digitalloopback mode, the combo retransmits
the PCM word it receives in the voice A or, B byte of
the SLD back to the line card controller in the same
frame. This feature allows path verification and testing
of the circuit up to the combo.
When the analog loopback mode is selected, the analog output VFR is internally connected to the analog
input VFX. This feature allows functional testing of
the combo as well as gain adjustment.

14-170

I(ft)ATC 29C48

BIINllm'l
#78

nochlnge
wrlll,nlble

00

F

01

WE

_down
_up

PUP

no,mll operation
dlgllllioop bock

DLB

no"",,1 operation
..alog loop bock

o ALI

normll ope..llon
aubocrlbel' loop back

SLB

programming of this register. A ~ange from 0 to - 15.5
in O.5dB increments can be realized for the receive
channel.

LSB

MSB

BIINumbel'_-171 i

151413121' oj

J

BIINllm'l
#78

-

noah.ng.
w,lII,nlblo
Galn(dB)

A-Law
,..Law

11
10

W:}

....

_'1

#12345

-0.5
-1.0
-1.5

00000
00001
00010
00011

-15.0
-15.5

11110
11111

RGN2
M~}
RGN3
RGN4
RGN5

FCB #3 - Secondary Analog Channel, .
Chip Select, and TC)ne InjectIOn Register

ABS

SECONDARY ANALOG INPUT
In the third test mode, subscriber loopback, the digital
output of the AID converter Is internally co~nected to
the input of the DIA converter. The analog signal Input
to VFX Is sent through the transmit filter, encoded,
. then decoded, filtered and output to VFR. This mode
is used primarily for simplifying analog to analog testIng from the subscriber side of the line card. Simultaneous selection of more than one loop-back mode
is prohibited.

CONVERSION LAWS
The 29C48 can be selected for either wlaw or A-law
operation. A user can sele.ct eit~er con~ersion .law. by
assigning the corresponding bit. A logical 1 In bit 1
would select wlaw while· a logical 0 would select
A-law conversions. 80th conversions follow CCITT
recommendation G.711.

FEATURE CONTROL EXCHANGE
CHANNEL SELECT
The LS8 of feature control byte #1 is the channel
selection bit. It is used to select one of the two 29C84s
sharing an SLD link for feature control information
exchange. A logical zero will select the channel A
combo, and a logical one will select the channel 8
combo.

The 29C48 can be instructed to switch the input of
its encoder to the secondary analog input by setting
the SAlE bit to a logical one. Transmission of the voice
signal will resume as soon as SAlE is set back to a
logical zero.

PROGRAMMABLE SLiC CHIP SELECT
Although the 29C48 does not process signaling information, it generates chip select signals in order to
help In interfacing to SLD compatible SLiCs.
During the transmit half frame,the chip select works
in two possible modes determined by the CSM bit. In
the byte mode, the SCS pin of the 29C48 selected
by the chip select bit in feature control byte #1, will
be pulled low during the XSIG byte. In the half:byte
mode the SCS pin of the A-channel 29C48 Will be
pulled low during the four ieast significant bits of the
XSIG byte, and the SCS pin of the B-ch.an~~1 29C~8
will be pulled low during the four most slgmflcantblts
of the XSIG byte.
Generation of chip select signals ~uring the rec~ive
half frame can be disabled by setting the CSD bit to
a logical zero.

TONE INJECTION
FCB #2 Register

Receive Programmable Gain

The receive gain levels can be adjusted by apply~ng
external resistors as mentioned earlier, or by selective

When the TIE bit is set to a logical one, audio signal
applied at the E8N31T1 pin will b~ added to the ~utput
of the receive programmable gain module. ThiS feature can be used for easy implementation of side tone

14-171

I®ATC 29C48

injection and DTMF feedback, as well as injection at
the line card of call waiting tones, ringing or metering
pulses.
MSB

BALANCE NETWORKS

LSB

Bit Numb.r .... 17ISlsI41312111 0 1

no change

write enable

Three external balance networks can be used with
the 29C48. Feature control allows the selection of
network EBN1, EBN2, and EBN3 individually or in
combination in order to best suit a particular
application.

·~~··l~
lOWE}

Secondary Analog Input
dlsabl.d
0
enabled
1

FCB #5 - Balance Network Select and
Gain Register

EBN3 selection is not effective when TIE is set to a
logical one.

SAlE

SCS mode
byte
half·byte

0
1

CSM

50% actlv.
100% active

0
1

CSD

EBN3 pin .nabled
TI pin .nabled

0
1

TIE

SCS

ses

GAIN SETTING
An additional 6dB gain in the balance signal path can
be realized by coding this bit to a logical one. A logical
zero provides unity gain.

reserved

MSB

BltNI.m·
#76

FCB #4 Register

no change

Transmit Programmable Gain
.

write enable

Balance Network
dls.bled
enabled

The gain setting of the transmit section of the chip
operates in the same manner as the receive gain
register. A 12dB range from - 6.0dB to + 6.0dB in
O.5dB increments is available.
MSB

B~~;m·l
write enable
Galn(dB)

11
10

LSB

JI~ I

F}~
WE,

don't
care

00000
00001
00010
00011

+0,0
+0.0

11000
llXXX

0
1
432

F}
WE-

BNE

000
001
010
011
100
101
110
111

SBN2

SBNl

Balance Network Gain

OdB glln
6dB geln

#12345

+12.0
+11,5
+11,0
+10.5

11
10

SBN3--'-

no selection
EBN1/3 ••Ioctad
EBN3
s.lected
EBNl
••Iocted
EBN2
selected
EBN1/2/3 selected
EBN2I3 ••Iected
EBN1/2 .elected

Bit Number .... 171615141312111 0 1

no change

1J

LSB

Bit Numb.r __ 171 61 5 14 13 12 11101

don't care

~'l

don't care

XGN2
XGN3
XGN4
XGNS

14-172

0
1

RNG

I®ATC 29C48

ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias . . . . . -10°C to + 80°C
Storage Temperature . . . . . . - 65°C to + 150°C
All Input and Output Voltages
with Respect to Vee ......... -0.3V to 13V
All Input and Output Voltages
with Respect to Vcc ......... -13V to 0.3V
Power Dissipation . . . . . . . . . . . . . . . . 1.35W

"NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only
and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

D.C. CHARACTERISTICS
(TA = O°C to 70°C, Vcc = +5V ±5%, Vee = ~5V ±5%; SCL (50% duty), SDIR, SLD applied GNDD = OV,
GNDA = OV.) Typical values are for TA = 25°C and nominal power supply values
DIGITAL INTERFACE
Max Units
Test Conditions
Parameter
Min
Typ
Sym"ol
±10
pA
Input
Leakage
Current
0""
Vin
"" Vcc
III
0.8
V
Input Low Voltage
Vil
Input High Voltage
2.0
V
VIH
0.4
V
10l ~ - 1.6mA, 1 TTL load
Output Low Voltage
VOL
2.4
V
Output High Voltage
VOH
10H"" 50pA, 1 TTL load
POWER DISSIPATION
Symbol

Parameter

Min

Typ

Max

Units

Iccl

Vee Operating Current

9

mA

leel

Vee Operating Current

mA

Icco

Vee Standby Current

9
0.8

leeo
Poo

Vee Standby Current
Standby Power Dissipation

0.8
8

mA
mW

P01

Operating Power Dissipation

90

mW

Test Conditions
RCV Signaling Byte = 0
RCV Signaling Byte = 0

mA

A.C. CHARACTERISTICS - TRANSMISSION PARAMETERS
(TG1 '= TG2, Transmit Programmable Gain = 6dB. Receive Programmable Gain = OdB)
GAIN AND DYNAMIC RANGE
Test Conditions
Parameter
Min
Typ
Max Units
Symbol
Signal input of OdBmO
Encoder Milliwatt Response
±0.15
dB
EmW
f = 1.02KHz
Tolerance
±0.15
f = 1.02KHz
Digital Milliwatt Response
dB
DmW
Tolerance
6.14
dBm
DmWp.v Digital Milliwatt Response VFR,
Vrms
1.571
wlaw
DmWAV Digital Milliwatt Response VFR,
A-law

6.17
1.576

dBm
Vrms

Rl = 600n Signal input per
CCITT G.711

OTLP,.,x Zero Transmission Level Point
Transmit Channel (OdBmO)

0.12
.785

dBm
Vrms

OTLPAX Zero Transmission Level Point
Transmit Channel (OdBmO)

0.15
.788

dBm
Vrms

wlaw
Referenced to 600n
A-law
Referenced to 600n

14-173

I®ATC 29C48

GAIN TRACKING
Reference level = OdBmO at 1.02KHz, TG1 = TG2, Transmit
Programmable Gain = SdB, Receive Programmable Gain = OdB
Symbol
(3TT

Parameter
Transmit Gain Tracking Error
Sinusoidal Input; p, or A-law

GTR

Receive Gain Tracking Error
Sinusoidal Input; p, or A-law

Min

Typ
±.25
±.50
±1.2

Max

±.25
±.50
±1.2

Units
dB
dB
dB
dB
dB
dB

+3
- 40
- 50
+3
- 40
- 50

Test Conditions
to -40dBmO
to - 50dBmO
to - 55dBmO
to -40dBmO
to - 50dBmO
to - 55dBmO

AT&T PUB43801 and
CCITT G.712 - Method 2
ANALOG INTERFACE, RECEIVE CHANNEL
Symbol
Parameter
Min
Output Resistal1ce, VFR
ROR
VOSR1
CLR
VORl

Output Offset, VFR
Load Capacitance, VFR
Max Output Voltage Swing
across RL, VFR '

Typ
1

Max

50
100
±3.2

Units
0
mV
pF
Vp

Test Conditions
Relative to GNDA
RL~300n

ANALOG INTERFACE, TRANSMIT PRIMARY AND SECONDARY CHANNELS
Symbol
Parameter
Min
Typ
Max Units
Test Conditions
Input Leakage Current, EBN,
nA
-1.SVc:3t~.w'
ISO

q

TRANSMIT CYCLE

SOIR

,

SLO(A)

SLO (8) _ _ _ _--;:r}-+_IH_Z-(j3 - -

:-1"[ :;=J>------i:Jf--------

A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUT/OUTPUT

2.4=X
0.45

2.0

2.0

?TEST POINTS<
0.8

>C

0.8

A.C. TESTING: INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC M1" andO.45Y FOR A
LOGIC "0", TIMING MEASUREMENTS ARE MADEAT2.0VFOR A LOGIC 1" AND
M

O.BY FOR A LOGIC NO",

14-179

inter
iATC 2952
INTEGRATED LINE CARD CONTROLLER
• Provides Complete Backplane Interface
for 8 Subscribers

• Implements HDLC Protocol to
Guarantee Integrity of all Signaling and
Control Information

• Performs all Timeslot Assignments
• 2 Full-Duplex, Se.rial TOM Highways
• Serial, Bidirectional Packetized highway
for Signaling Control
• Standard MCS ILP Interface with two
channel DMA and Interrupt

• Supports Four Control Options Local or
Global Microprocessor Direct or
Interleaved HDLC Control
• Designed for 24, 32, 48 or 64 Tlmeslot
Systems
• Common Backplane Interface Supports
ISDN Upgradability

The Intel iATC 2952 Line Card Controller (LCG) is a special purpose I/O controller optimized for use in all types
of telecommunication switching systems. The 2952 is intended for use with up to eight subscriber devices in
both analog and digital line circuits. It is also useful as a general purpose I/O controller for other applications.
The 2952 represents the continuation of a trend to intelligent flexible line cards. With its modular design, the
2952 provides a graceful upgrade path from analog line circuits to an all digital system. Analog line board
density can be greatly increased using the LCC with the 29C51 or 29C50A Feature Control Combos. The 2952
handles the transfer of voice, feature control, and signaling information between the backplane and up to 8
29C51 's, or 16 29C50A's. The 2952 will interface with and control all Intel SLD compatible slave devices. The
2952 emphasizes highly serial interfaces, thus reducing the number of digital interconnections both to the
subscriber device and to the backplane.

SLD3

SLD4
SLD5

39

SLD2

SLD6

3

38

SLDl

SLD7

4

37

SLDO

DRl

5

36

RESET

ORO

6

35

INT

DXl

7

DACKl

DX1E

8

DACKO

DXO

9

WR

DxiiE

10

FS

11

SCL

12

AD6

SGSIDMIR

13

AD5

SDIRIDMOR

14

AD4

DSX

15

AD3

DsE

16

AD2

DSR

17

AD1

CS

18

ADO

ALE

19

RD

GNDD

20

2952

31

vcc
AD7

21

CLK

. Figure 1. Pin Configuration

14-180

IATC 2952

SCL~------------------------~;---------------I~------------------------FS
CLOCKS AND CONTROL
'SDIR ~-------------------------l
·SGS ~--------------------------jL

I~-----------------------CLK

____-,.,.--____I-------------------------RESET

SLDO

SLDl
SLD2
SERIAL
{
SUBSCRIBER

SLD3
SLD4

UNES

SlDS

DRO
OXD

OXDE
DRl
OX1

SLOG
SlD7

l
j

PCM
TRANSMIT
AND
RECEIVE
HIGHWAY

OX1E

DSR
DSX
DSE

DAC~-----------J

DACK1 ______________- "

' - - - - - - - - - - - - - - - - ALE

"Dual Function pin

Figure 2. 2952 Block Diagram

14-181

}

SIGNALING
AND HOLe
HIGHWAY

IATC 2952

Table 1. Pin Description

Symbol

Pin No.

Function

GNDD

20

Ground: OV.

VCC

31

Most positive supply; input
voltage is +5V ±5%.

SLDO-7

37-40
1-4

12

Subscriber Clock. This is a
512kHz signal generated by
the 2952 with 50% or 33%
duty cycle clock. Can be
connected up to 8 slave
devices.

SGS/DMIR

13

Signaling Strobe. Can be
used to strobe signaling bits
or voice bytes for enabling
external logic. In the DMA
mode DMIR functions as
DMA input request for HDLC.

SDIRI
DMOR

14

Subscriber Direction. This is
an 8kHz signal generated by
the 2952 to serve as both a
direction indicator and a
slave frame sync. When
high, the SLD bus becomes
an output and data is
transferred from the 2952 to
the slave. When low, the
output buffer on the slave
SLO pin is enabled and data
is transferred from the slave
to the 2952. In the DMA
mode, DMOR functions as
DMA output request for
HDLC.

18

19

Function

22

Read Strobe. (Active low
input). When input is low,
data is transferred from
selected register on to J.LP
bus. When no local J.LP is
connected, this pin should be
connected to GNDD.

23-30

Address/Data pins. Standard
J.LP bus used to transfer
address and data between
the J.LP and internal registers
of the 2952. When no local
J.LP is connected, the unique
10 is hardwired on pins
AD(0-7).

WR

32

Write Strobe. ~tive low
input). When WR transitions
from low to high, data on
pins AD(0-7) are latched into
the selected register. When
no local microprocessor is
connected, this pin should be
connected to GNDD.

DACKO
DACK1

33

DMA Acknowledge. DACKO
is used to acknowledge the
DMA output, and DACK1 is
used for DMA input. When
no local microprocessor is
connected, these pins are
used to hardwire mode
information.

INT

35

DR1

5

Receive PCM Highway 1.
Serial words are received on
PCM highway 1 at this
interface.

ORO

6

Receive PCM Highway O.
Serial words are received on
PCM highway 0 at this
interface.

DX1

7

Transmit PCM Highway 1.
Serial words are transmitted
onto PCM highway 1 at this
interface.

DX1E

8

Transmit PCM Highway 1
Enable. Used to enable
external tristate buffers to
drive signals onto the PCM
highway. The signal goes low
while the 2952 is transmitting
onto PCM highway 1.

AD(0-7)

34

9Jjp Select. Enables RD or
WR. A low level at this input
allows the 2952 to accept
commands or data from a
microprocessor within a write
cycle, or to transmit data
during a read cycle. When no
local uP is connected this pin
should be connected to
GNDD.

ALE

Pin No.

RD

Subscriber Data link. There
are eight bidirectional pins
that transfer serial
information between the
2952 and the subscriber
devices (e.g. 29C51).

SCL

CS

Symbol

Address Latch Enable.
(Active high input). On falling
edge of this input signal, data
on AD(0-7) is latched into
the selected register. When
no local microprocessor is
connected, this pin should be
connected to GNDD.

14-182

Interrupt Request. A standard
microprocessor interrupt, with
active low output.

IATC 2952

Table 1. Pin Description
Symbol
OXO

OXOE

Pin No.
9

10

Function
Transmit PCM Highway O.
Serial words are transmitted
onto PCM highway 0 at this
interface.
Transmit PCM Highway 0
Enable. Used to enable
external tristate buffers to
drive signals onto the PCM
highway. The signal goes low
while the 2952 is transmitting
onto PCM highway O.

DSX

15

Transmit Signaling Highway.
Serial signaling and control
data is transmitted on this
dedicated HOlC highway.

DSE

16

Transmit Signaling Highway
Enable. Used to enable
external tristate buffers to
drive signals onto the
transmit signaling highway.
The signal goes low while
the 2952 is transmitting an
HOlC packet onto OSX.

OSR

FS

ClK

RESET

17

11

21

36

fUNCTIONAllDESCRiPTION

I

EXTERNAL INTERFACE
The 2952 LCC supports interfaces for the subscriber
line devices, an optional local microprocessor, and
the backplane PCM and HOLC highways. Each is
described briefly below.

Subscriber Line Interface

Receive Signaling Highway.
Serial signaling and control
data is received on this
dedicated HOlC highway.
Frame Synchronization
System sync pulse indicating
beginning of a 1251-'3ec
frame.
Master Clock. System input
clock provides basic timing
for the 2952 and is
synchronous to the PCM
clock. The clock rate
determines the number 01
timeslots on the transmit and
receive PCM highways,
ranging from 24, 32, 48 or 64
per frame.
Reset. (Active high input).
When high, 2952 internal
circuitry is reset. The
minimum reset pulse must be
16 complete elK clock
cycles wide.

The 2952 is a highly integrated line card controller
which concentrates and multiplexes all digitai information that passes between a line card and the next
switching or control level in a digiial telecommunications system. It controls time switching funciions
between the individual subscriber line devices and
the system backplane Time Division Multiplexed
(TOM) highways. In addition, it manages the ti'ansfer
of all Signaling and ccntrol messages, either to an
optional local microprocessor or to a central control
processor. The 2952 implements all protocol control
functions using the HDLCformat for all information
transmitted between the line card and the central
processor.

The LCC provides 8 serial, bidirectionai ports lor the
digital transmission of voice, data, controi. and signaling information to and from the subscriber. T:,ese
leads, SLDO-SLD7, can be used to interface to bOth
analog and digital line card subscribers (See Figure

3).
1

The Slave Clock SCL. is a fixed 512 kHz signal output
used to transfer all signals between the subscriber
device and the 2952. Data is received and transmitted
upon the rising edge of SCL.

I

Data transmission direction is controlled by the Slave
Direction clock, SOIA. This 8 kHz signal divides the
frame transfer into transmit and receive halves refei'enced to the subscriber as shown in Figure 3. When
SOIA is high, (RCV half-cycle), information is transmitted from the 2952 to the subscriber in four bytes
conSisting of voice, data, feature control, and signaling information. In the second half (XMIT-half cycle),
the subscriber circuit sends four bytes of XMIT data
back to the 2952.

14-183

IATC 2952

I

I

I

I

I
I

FS

RECEIVE HALF-CYCLE
2952 --+ SUBSCRIBER

TRANSMIT HALF-CYCLE
SUBSCRIBER -+ 2952

I
I

------,rL

Jl~___- - -:-___
I

SDIR~

I

I

I

s

I

SLD----~~--~~-L~~L-~_+--r_~_r~--r_~~~I~--I

I

i

VOICE/DATA

I

I

I
I

SIGNALING

I

-

-

-

-

-

-

I

I

CONTROL

I
1 - 0.
1_
.

I

I

: VOICE/DATA

-

I

i

CONTROL

I

SIGNALING :

i

1 FRAME
(125 uS) --------~.I
512 KBPS

I

Figure 3. SLD Interface

Backplane Interface
The LCC supports dual TOM voice/data highways as
well as a separate high speed serial highway for signaling and control information. This information is
packetized and protected in HOLC format for transmission to a central processor.

Alternatively, the 2952 can operate in a stand alone
mode on the line card in systems using a more centralized processing architecture. In this mode, the individual line. board address and initialization information is hardwired onto the microprocessor interface
pins.

2952 BASE ARCHITECTURE
The system clock (CLK) provides data rate transfers
for both the TOM and HOLC links. The 2952 can
operate in 24, 48, 32 or 64 timeslots systems. Any
subscriber has access to any timeslot on either TOM
highway. The 2952 allows the flexibility of programmable rising or falling edge latching of data onto the
highways. Additionally, PCM highway delays can be
compensated for by programming a phase shift in
both transmit and receive timeslots as referenced to
the frame synchronization pulse. The starting point
of the bytes can be shifted up to 7 CLK clock cycles
for both transmit and receive directions in half clock
increments.

Microprocessor Interface
The microprocessor interface provides a communication path for a local /.LP and the backplane and/or
slave devices. The 2952 is designed to operate with
standard Intel 8-bit parallel microprocessors, such as
the MCS-48, MCS-51, MCS-85, and iAPX-86 families. Interrupt capability, direct-memory-access request and acknowledge signals and a full feature multiplexed address data bus are incorporated into this
interface.

The 2952 can be partitioned into three functional
blocks, according to the type of data transfers that
each provides. The synchronous portion comprises
the subscriber and PCM highway interfaces. Included
in this section is also the Master Timing Unit, a CAM
(Content Addressable Memory) for timeslot matching,
a MOOE register to configure the 2952 and for the
determination of the type of HOLC data exchange,
and the internal bus for a communication link between
the various interfaces and registers. The PCM Interface Unit and the Subscriber Interface Unit with Last
Look logic are also grouped into this segment. The
Last Look logic monitors the status of signaling information received from each subscriber every frame.
Any change of status is reported to the local /.LP or
to the LCC bus control unit.
The asynchronous portion includes the local microprocessor interface and the serial HOLC signaling
and control interface. The HOLC controller is compatible with ISO/CCITT recommendation X.25, and
is deSigned for either point-to-multipoint configurations as a primary station, or in point-to-point as a
secondary station. Each 2952 is accessed through

14-184

lATe 2952

an S-bit address, allowing up to 255 secondaries to
be addressed on one HOLe serial line. The logic level
of the HOLe implementation and the distribution and
compilation of the data packages are handled in a
separate command unit contained in this portion.
The synchronous and asynchronous portions are
linked to one another by a set of buffers and a control
unit for the Lee internal bus. Two 16-byte by 8-bit
FIFO's are used for intermediate storage of messages. The XFF, or Transmit FIFO buffers data packages for transmission to the central processor through
the HOLe interface. The type of data loaded is either
from the Last Look logic or from the p,P in package
form with direct addressing to the 2952. The BFF, or
bidirectional FIFO, is used for data exchange between the central controller (via the HOLe interface),
the local microprocessor (via the p,P bus), and the
Lee (via the Lee bus).

MODES OF OPERATION
The 2952 may operate in either a primary or secondary command mode within a single system. When

SYNCHRONOUS
SUBSCRIBER INTERFACE

SERIAL
512 kHz

instructed as a primary station, a local microprocessor must be used to instruct the 2952 and to generate
control messages for other stations. This mode is
used primarily by unit or group controllers to command secondary 2952's. When in the secondary
mode, the 2952 executes received HOLe commands
from the group controller. Additionally, a transparent
command mode may be configured in which all HOLC
messages received from the backplane are passed
directly to the local microprocessor. This allows a secondary 2952 to execute user defined protocol and
commands.
The 2952 can operate in one of two HOLe communication modes - dedicated HOLC or interleaved
HOLe. In the dedicated configuration, HOLe messages are received on OSR and are transmitted on
OSX. The interleaved mode reserves up to two timeslots per frame for transmission of signaling and control messages on the PCM highways. The HOLe
packets are disassembled and interleaved into programmed timeslots on either of the two highways.
Alternatively, the microprocessor can communicate
directly to the central controller via a direct connection, bypassing the 2952 HOLe interface completely.

ASYNCHRONOUS
MICROPROCESSOR ANO
CONTROL INTERFACE
LOCAL uP REAOIWRITE
ALL INTERNAL REGISTERS
PARALLEL
uP BUS

HOLC
PORT

Figure 4. Architectural Diagram

14-185

SYNCHRONOUS
PCM INTERFACE

SERIAL
1.536-4.096 MHz

lATe 2952

ABSOLUTe MAXiMUM RATINGS
Temperature Under Bias ............. - 10°C to + ao°c
Storage iemperature ...................... - 55°c to 125°C
All Input and Output Voltages
with respect to GNDD .................. - 0.3V to + 7V
Total Power Dissipation ................................... 1.5W

DC CHARACTERISTICS
(TA = DOC to 70°C, Vcc = +5V ± 5%; GNDD = OV
Typical values are for TA = 25°C and nominal pow~r supply value
Symbol

Typ

Parameter

Min

Max

Units

ill

Input Leakage Current

-10

+10

/-LA

GND .;;; VIN .;;; Vec

10l

Output Leakage Current

-10

+10

GND .;;; VOUT .;;; Vee

V1L

Input Low Voltage

-0.5

o.a

/-LA
V

V1H

Input High Voltage

2.0

VOL
VOH

Output Low Voltage
Output High Voltage

Icc

Vee Supply Current

85

POl

Operating Power Dissipation

425

CAPACITANCE (TA
Symbol

Vee

V

0.45

V
V

2.4
120

rnA

Test Conditions

IOl = +1.6 rnA
IOH = - 400

!-LA

Vcc = 5V

mW

= 25°C; Vee = GNDD, OV)

Parameter

CIN

Input Capacitance

CliO

Input/Output Capacitance

COUT

Output Capacitance

Min

Typ

Max

Units

5

10

pF

10

20

pF

a

15

pF

14-186

Test Conditions

fc = 1 MHz
Unmeasured pins
returned to GNDD

inter

IATC 2952

A.C. CHARACTERISTICS
(TA = O°C to 70°C; Vcc = 5V±5%, GNDD = OV)
SLD Interface Timing
Parameter

Symbol
ClK

System Backplane Clock Frequency
ClK Duty Cycle

Min

Max

Units

1.536

4.096

MHz

45

55

%

ClKRise, Fall Times

10

ns

Frame Synchronization Pulse Period

125

t FS

Frame Synchronization Pulse Width

60

tdFS

Pulse Delay to ClK

10

tSFS

Set-Up Time to ClK

50

SCl

Slave Clock SCl Frequency

512

512

~SCL

SCl Delay Time From ClK

100

165

SDIR

Slave Direction SDIR Frequency

8

8

~OIR

SDiR Delay Time to ClK

120

190

ns

~SLO

SlD Data Delay

160

300

ns

tOER

Data Enable Receive

100

180

ns

tOOR

Data Disable Receive

100

180

ns

tOEX

Data Enable Transmit

0

ns

tOHx

Data Hold Transmit

0

ns

tosx

Data Set-Up Transmit

1
2 ClK + 200

t OSIG

Signaling Strobe Delay

110

14-187

jJ-S
t.CLK

ns
ns
ns
kHz
ns
kHz

ns
160

ns

IATC 2952

A.C. CHARACTERISTICS
(TA = 25°C, Vee = GNDD = OV)
MICROPROCESSOR INTERFACE
READ CYCLE

Symbol

Min

Parameter

Max

Units

tAL
lLA

Address Set-Up to ALE
AddressHold After ALE

20

tAA

ALE Pulse Width

60

tAD

Data Delay From AD

150

ns

tOF

Data Float After AD

25

ns

107

ns

tAA

AD Pulse Width

tAl

AD control intervaP

tAl

AD control interval 2

30

ns
..

ns
ns

150
1

ns

2 x .ClK
100

. ns

WRITE CYCLE

Symbol

Min

Parameter

Max

Units

tow

Data Set-Up to WA

50

ns

two
tww

Data Hold After WA

25

WA Pluse Width

ns
ns

tWI

WA control intervaP

1
2 x .ClK

ns

tWI

WA control interval 2

50

ns

100

NOTES:

1. Read or Write· of BFF and XFF.
2. Read or Write of all other registers.

14-188

inter

IATC 2952

DMA READ
Symbol

Min

Parameter

tOMA

DMA Read Time

tOH
tAR
tRO

OMORHold Time

tOH

Data Hold after RD

Address Stable before RD

Address Hold after RD

tRR

AD Pulse Width

Units
ns

75

ns

0

Data Delay from RD

tRA

Max
1
7 x .ClK

ns

150
20
0
150

104

Min

Max

ns
ns
ns
ns

DMA WRITE
Symbol

Parameter

tOMA

DMA Write Time

1
7 x .ClK

tlH

DMIR Hold Time

80

tAW

Address Stable before WR

tWA
.tow

Address Hold after iNA

two
tww

Data Hold after iNA
iNA Pulse Width

0
0
30
25
100

Data Set-Up to WR

14-189

Units.
ns
ns
ns
ns
ns
ns
ns

inter

lATe 2952

, System Backplane Timing Parameters
PCM INTERFACE -

RECEIVE TIMING

Symbol

Parameter

Min

= 01

toSAA

Receive Data Set-Up OCR

toHAA

Receive Data Hold OCR

toSAF

Receive Data Set-Up OCR = 12
Receive Data Hold OCR = 12

toHAF

= 01

Max

Units

40

ns

10

ns

20

ns

40

ns

Test Conditions
60ns for Interleaved Mode

PCM INTERFACE - TRANSMIT TIMING
Symbol

Parameter

Min
80
45

tozxF
toHXF

=0
Data Hold Time DCX = 0
Data Enable DCX = 1
Data Hold Time DCX = 1

tHZX

Data Float After ClK TS

tSONA

Timeslot x to enable DCX

tSONF

Timeslot x to enable DCX

tSOFF

Timeslot x to disable

toZXA
toHXA

Data Enable DCX

=0
=1

Max
160

Units
ns

160

ns

40

100

ns

40

100

ns

35
70

80
130

ns
ns

40

100

ns

40

100

ns

Min

Max

Units

Test Conditions

= 200pF
CL = 200pF
CL = 200pF
CL = 200pF
CL = 150pF
CL = 150pF
CL = 150pF
CL = 150pF
CL

HDLC INTERFACE TIMING
Symbol

Parameter

Test Conditions

tos
toH

Receive Data Set Up

40

ns

Receive Data Hold

10

ns

tTD

Transmit Data Delay

40

100

Data Float on TS Exit

35

80

ns
ns

CL

tHZX
tSON

Timeslot X to enable

40

95

ns

CL

tSOFF
NOTE:

Timeslot X to enable

35

90

ns

CL

1. OCR = 0 data latched on rising edge of ClK.
2. OCR = 1 data latched on falling edge of ClK.

14-190

CL

= 200pF
= 200pF

= 150pF
= 150pF

IATC 2952

WAVEFORMS

SLD Interface Timing

FS
ClK

SCl
SOIR
SlO
(Rc)

SlO
(Tx)

SGS

l---------+-~,~~ ""
----+---~
. ~ r;r~---------:J ~tOSIG
f

Microprocessor Interface

READ CYCLE

ALE

AD BUS

WRITE CYCLE

AD BUS

IWW

\j4:::_tW'~L,----.

'~C'WD

-----------€9--

-

~8~
Q~­

TG2

SAl SELECTION SWITCH

SAI1

Zct-

oz::>
frlo(~

SAI2

'" ,;,

w

~!::S:!

e::E~

~w~
~~~

{

VFX
BALANCE
NETWORK
SWITCH

EBN1

{

"':5 0

Sc~

EBN2

wm~

r

BALANCE
NETWORK
SELECTION AND
INTERPOLATION

SCl

'-----r----lt--+----t~SDIR
_

J

SlD

SIGR(n)

co
3.
Zc {
tOw

SIGX(n)

(ij-'

S!

SIGP(n)

w

VFR-

w>
S:!w
ou
>w

VFR+

'"

t-

::>

a.

50

Vee

GSR

{

SAO

Figure 2. 29C51 Combo Block Diagram
14-196

jl

intJ

LCDK -

29C51/52

2952 Line Card Controller
The Intel iATC 2952 Line Card Controller (LCC) is a
special purpose I/O Controller optimized for use in all
types of telecommunication switching systems. The
2952 replaces the traditional MSI circuits and represents the continuation of a trend to intelligent flexible line cards.
The 2952 handles the transfer of primary voice, data,
feature control, and signalling information between
the backplane and up to eight 29C51 's; however, the
LCDK-29C51/52 will only be equipped for four
29C51 's per board. The 2952 and 29C51 communi-

cate across a Subscriber Data Link (SLD) interface.
The SLD is a three wire link comprising of a clock
signal a serial data stream and a read/write strobe.
The 2952 is equipped with a standard microprocessor
interface and independent transmit and receive DMA
channels. As well as this, the 2952 has two standard
PCM highways for connection to the backplane. Another feature of the 2952 is a fast serial interface to
the central processor. This serial interface is intended
for signalling and follows a subset of the HDLC protocol. Figure 3 shows a block diagram of the 2952.

seL -----------r-----'l~o-----------FS
*SDIR
CLOCKS AND CONTROl. 1~.o__---------eLK
*SGS
RESET

SLOO
SLD1
ORO
oxo

SLD2

SERIAL
{
SUBSCRIBER
LINES

SLD3
SL
04
SLOS
SLOO
5LD7

'DXOE
DR1

eXl

l
j

PCW
TRANSMIT
AND
RECEIVE

HIGHWAY

OX1E

DSR '} SIGNALING
DSX
AND HOLe
aSE
HIGHWAY

t

GNOO

'----------ALE

'Dual Function pin

Figure 3. 2952 Block Diagram

14-197

intJ

LCDK -

29C51/52

The 8031 CPU
The Intel 8031 belongs to the MCS-51 series of single
chip microcomputers, and is at the heart of the LCDK,
performing control and processing functions for both
the primary and secondary stations. The a031 CPU
combines, on a single chip; a 128 x 8 data RAM, 32
input/output lines, two 16-bit timer/event counters, a
five source level nested interrupt structure, a pro-

grammable serial 1/0 port; and an on chip oscillator
and clock circuits. An 8031 block diagram is shown
in Figure 4.
For additional information on the 8031 see the 8051
User's Manual.

REFERENCE
r-

----

------------------------------------~-

OSCILLATOR

•

TIMING

COUNTERS
--

-----,

4096 BYTES
PROGRAM
MEMORY
(8051 • 8751)

128 BYTES
DATA MEMORY

TWO 16-BIT
TIMER/EVENT
COUNTERS

64K-BYTE BUS
EXPANSION
CONTROL

PROGRAMMABLE
I/O

PROGRAMMABLE
SERIAL PORT
• FULL DUPLEX
USART
• SYNCHRONOUS
SHIFTER

8051
CPU

I
I
I
I

I
I
I

I
I
I
I
___ JI

I
I
I
I

L_

INTERRUPTS

CONTROL

PARALLEL PORTS,
ADDRESS/DATA BUS,
• I/O PINS

Figure 4. 8031 Block Diagram

14-198

SERIAL
IN

SERIAL
OUT

LCDK - 29C51/52

System Software

Documentation

A compact but powerful system monitor is contained
in 8K bytes of preprogrammed ROM. The monitor
includes system utilities such as command· interpretation and interface controls. Table 1 summarizes the
LCD-29C51/52 monitor commands.

In addition to detailed information on using the monitor, the LCDK-29C51/52 user's manual provides circuit diagrams, a monitor lisitng, and a description of
how the system works. The complete design library
for the LCDK-29C51/52 is shown in Figure 4 and
listed in the specification section under Reference
Manuals.

Table 1
Operation

Command
(LCC reg)
Half/Full
Help
Byte
LCC
GO

Read or Write a 2952 register.
Half or Full duplex terminal mode.
Displays a Help file.
Read or Write any external data
memory address.
Relocation of 2952 base address.
Execute user programs resident in
memory.

SPECIFICATIONS
Control Processor
Intel 8031 microcomputer.
12MHz clock rate

Memory
MEMORY
The memory is mapped via 4K byte pages; a maximum of 12K bytes are used allowing a user expansion
of memory up to 64K bytes. The memory can be
configured as8K bytes of ROM/PROM plus 2K bytes
of RAM or alternatively 12K bytes of ROM/PROM.

ROM - Socket for 256K bytes of program memory,
however, a 4K or 2K byte ROM may be inserted.
RAM - Socket for 2K bytes static RAM; user configurable as program or data memory. Alternatively a 4K EPROM such as 2732A may
be inserted.

USER INTERFACE

Feature Control Combo

Communication with the outside world is accomplished over an RS-232-C compatible link. This serial
link will hook up a CRT terminal to the serial port on
the 8031. Alternatively an Interrec Development System can be connected to the LCDK, this can now be
used as either a dumb terminal or to transport user
developed programs to the LCDK, commands for
these functions are shown in Table 2. A large area
of the board is laid out as general purpose wire-wrap
for user custom interface.

Sockets for four Intel iATC 29C51's.

Table 2
Command
DTERM
Control-D

Operation
Places Intellec development system
in dumb terminal mode.
Transports user developed programs
from Intellec development system
to the LCDK.

Line Card Controller
Intel iATC 2952.
User selectable 2.048MHz or 4.096MHz clock rate.

Interface
Ten line ribbon cable for interconnecting the primary
and secondary boards, all signals are TTL compatible. Serial RS-232-C compatible interface for a terminal. Terminal baud rate can be 300, 600, 1200,
1800, 2400, 3600 or 4800.

Software
System Monitor - Pre programmed 2732 ROM.
Monitor I/O - CRT or Interrec Development System.

ASSEMBLY

Physical Characteristics

The LCDK-29C51/52 is supplied fully assembled and
is ready to go upon power up and terminal connection.
. The monitor is initialized by twice typing the return
key on user terminal.

Width Height Depth Weight -

14-199

12 inch
1% inch
7% inch
0.864 Ibs.

LCDK -

29C51/52

Mounting

Electrical. Characteristics

The two board may be:

DC Power Requirements

- plugged into an Intel system rack
- or mounted on five horizontal legs.

Voltage

Current

±5V ±5%
-5V ±5%

2.5A
BOmA

Environmental Characteristics
Operating temperature. . . . . . . . . . . ..0 - 50°C

14-200

APPLICATION
BRIEF

14-201

Ap·225

inter

APPLICATION BRIEF

INTRODUCTION
Line balancing is a concept associated with the frequency response matching of a line at its termination.
This matching allows a reduction of echos generated
within a telephone network. Bell Laboratories book
on Telecommunications Transmission Engineering
Volume 1 should be consulted for background on line
balance and telephone network impairments. This application brief discusses line balancing implementation with the 29C51 and 2952 in a telephone network.
Finally test results are given to show the impedance
matching that can be expected. The telephony convention of data directed towards the telephone being
the transmit and that coming from the telephone being
the receive is adhered to throughout this brief.

Figure 2 shows a single and differential ended interface between the 29C51 and the line. The differential
ended interface takes one more component than the
single:ended one, however, it can deliver twice the
signal level to the line. In principle, both interfaces
operate in the same manner, so only the single-ended
will be further discussed. The 29C51 will drive loads
as low as 300n; if the parallel combination of the
networks on V FR - is below this, they may then be
scaled. The receive signal, V FR +, is divided between
Zo and the line impedance Zl seen looking down the
line from the transformer. The signal across Zl is fed
back onto the transmit direction through the VFX input.
The V FR - signal is divided between Zo and balance
network ZB1 or ZB2. The receive signals across ZB1
and ZB2 are weighted by the 29C51 summed and
added to the transmit direction. This cancelling signal
is given by:

ex H,(F)

+ (1 - ex) H2 (F)

IMPLEMENTATION
The Line Card Development Kit 29C51 152 was used
to form the subscriber loop shown in Figure 1. The
line is terminated by the two-Io-four wire hybrid, a
poor mismatch results in reflections at the hybrid
which appear as an echo to the subscriber. As well
as reflections, a portion of the received signal couples
back onto the transmit direction. The magnitude of
the coupled signal is determined by the rejection
through the hybrid, this rejection is referred to as the
transhybrid loss. A poor transhybrid loss can result
in oscillations or near oscillations, referred to as singing and near singing respectively. Note to maintain
stability, the gain through the four wire path must be
kept below unity. This brief discusses the implementation and optimization of the transhybrid loss.

2

9
C

5

-

H,(F) and H2 (F) are signals across ZB1 and ZB2
respectively

-

ex is the interpolation coefficient

The weighting is controlled by setting ex to 0, 0.25,
0.5, .75 or 1 through the 2952. The end result is
interpolation between balance network one and two
which could correspond to two extreme line conditions.
Figure 2A shows the interpolated impedance range
for the balance networks shown in Figure 3. Values
of ex equal to 1 and 0 yield the external balance values;
fractional ex values produce a better balance over the
frequency spectrum.

2
9
5
2

Figure 1

14-202

2
9
C
5

APPLICATION BRIEF

SLD

~
VL:f

EBN1
EBN2

VFR _
GBR

~
LINE

SCL
SDIR

29C51
V FR +

1:1

VFX
TG1

Differential Line Interface

TG2

SCL
SDIR
SLD.1
2952

LINE

Single Ended Line Interface

Figure 2
14-203

APPLICATION BRIEF

fm'" ' 200 Hz
~f '200 Hz
f ma ,,' 4 kHz

Figure 2A

TEST SET UP AND RESULTS
The gain through the 29C51 is externally set to unity
and programmed internally to be well below one.
Thus, the gain in the four wire path is kept below one.
Readings were taken to measure the internal cancellation performance of the 29C51 , VFX was tied to
VFR+ and EBN1 to V FR -, a was set to 1. This arrangement gives the rejection figures with perfect
impedance matching. Transhybrid loss is given by the
ratio of VFR + to the signal at TG1 or 2. Figure 4 shows
variation in transhybrid loss with frequency.
The 29C51 was then set up, as shown in Figure 2.
Measurements were taken on a single end line interface. The transformer used was a T5115, this is a
line coupling transformer with a 1:1 ratio and has a

I
1000

16500

SNF;:f::

split winding. The split side is capable of handling
direct currents of up to 100mA.
Figure 3 shows the balance networks that were used.
These are the AT&T termination networks for loaded
and unloaded lines. The subscriber side of the line
was first terminated by balance network one with a
equal to one and then terminated by balance network
two with a equal to zero. Transhybrid loss results for
these networks are plotted in Figures 5 and 6.
Simulations were carried out to determine the optimum balance networks for various unloaded O.5mm
lines, these are shown in Figure 3A.

I

I
aooo

1000

lONE

7aoo

1000

SONF ;::

I
4300

10000

68 NF ;::~

5NF ;:f::

ITWO

I

I

Figure 3. Balance Networks

Figure 3A
14-204

inter

APPLICATION BRIEF

Figure 7 shows transhybrid loss variations with frequency for O.5mm line lengths. Note again the interface between the 29C51 and the line was singleended.

The non identical loading of the VFR outputs did not
create a voltage offset or a phase shift between VFR +
and VFR -. If this is a concern to the user, the impedances on the VFR - output may be scaled up to match
the load on the VFR + output.

I
loon

Boon
;;

III

~4O

~

III
9

en
en

Q

~

9 35

30

,..~ 30

Q

'"en~ 25

en

~ 25

1=

40

35

Q

~

I

45

45

!!l

0.051'F

20+---r--+--~--+---r--+--~--+-

500

20

1000 1500 2000 2500 3000 3500 4000
FREQUENCY IN HZ

500 1000 1500 2000 2500 3000 3500 4000
FREQUENCY IN HZ

Figure 5. Transhybridloss
with frequency

Figure 4. Transhybrid loss
with frequency for ideal Matching

1650n

~

....a:

loon
0.0051'F

30

iii"

III

:e

45

III
9

Q

~

III
9

40

25
20
€ = 13000 tt, a ;;;:: 0

Q

ii:
35

III 15

III 30

~ 10

~

Q

ii:

,..
'"en

~

1=
25

e = 3000 ft, ex = 0.75
C

= 6000 ft, ex = 0.25
f Line length In leet
a Interpolation coefficient

20f---t--1---+--~--t--1---+--~

500

500 1000 1500 2000 2500 3000 3500 4000
FREQUENCY (HZ)

1000 1500 2000 2500 3000 3500 4000
FREQUENCY IN HZ

Figure 6. Transhybrid loss
with frequency

Figure 7. Simulated Transhybrid loss
with frequency for O.5mm lines
14-205

Architectural 0 vervlew
.

October 1984

©INTEL C ORPORATION, 1984
14-206

inter

Architectural Overview

ARCHITECTURAL OVERVIEW
IATC 29C53
DIGITAL EXCHANGE CONTROLLER
•
•
•
•
•

4·Wlre Digital Transceiver
144 KB/S Data Transfer Rate (2B+D)
Microprocessor Interface
CCITT Compatible ISDN'S' Interface
General Purpose Power Controller
Interface

•
•
•
•
•

SLD Interface Compatible
Full Interrupt Support
Master/Slave Modes
Programmable Power Down Mode
Low Power CHMOS

FEATURES/BENEFITS
• 4-wire full-duplex digital point-to-point and mUlti-point baseband transceiver, can be used in public or PBX digital
subscriber or data communication applications.
• CHMOS; low power consumption.
• Power down modes; for lower power consumption when idling or not in use.
• 144K bits/sec effective data transfer rate at up to 1.0Km; supporting, voice/data, voice/voice or data/data transfers.
• Master/slave modes of operation; same part can operate at both ends of subscriber loop.
• Microprocessor interface; direct interface to MCS microprocessor family.
• SLD interface; directly compatible with iATC Telecom product family.
• CCnT compatible ISDN' S' interface; the subscriber loop interface is compatible with pending CCITT recommendation
1.430.
• Power controller interface; provides four pins for control and accepts status from external devices.
• Built-in HOLC packetizing/depackizing for D-channel.

CLOCK RESET POWER

4-WIRE
LINE INTERFACE

4

29C53

POWER
CONTROLLER
INTERFACE

l---rSLD INTERFACE
3

UP INTERFACE

Figure 1. 29C53 Overview Diagram
14-207

Architectural Overview

GENERAL DESCRIPTION
The 29C53 Digital Equipment Controller is an advanced, multi-channel, multi-protocol iATC Telecom transceiver able
to interface with many types of equipment. In this capacity, the 29C53 allows the extension of digital functions, such
as digital voice and data, directly into subscriber equipment with a high speed, 4-wire digitally encoded serial interface.
The 29C53 is a 28-pin device, which, when used with a 29C51, 2952 and microprocessor, implements flexible pointto-point and multi-point digital voice/data systems primarily intended for PBX applications and ISDN Tl type terminals.
This device in these modes provides a general data communication interface to a wide variety of terminals and work
stations. The 29C53 transceiver with its programmable digital interface functions may be incorporated at either end of
the subscriber loop interface (line card or digital telephone/terminal). As shown in Figure I, the 29C53 has four separate
interfaces: a serial SLD iATC Telecom system interface, a parallel power controller interface, a parallel general purpose
microprocessor interface, and a 4-wire CCITT compatible S-interface (subscriber loop interface).
Figure 2 presents a general block diagram of the 29C53. Its three major blocks are interconnected by two buses. The
parallel bus is used to transfer status and control information while the serial bus is used to transfer data between the
subscriber loop interface and the system interface.

RESET ClK

[).CHANNEl

r-------------- - ----------,I PROCESSING
AND

I

~

I

LX+

I

LX-

SlD

SDIR

SCl

lR+

LR- -.

I

I
I
I

I
LOOP
I
SERIAL
:L ________________________
INTERFACE

POWER
CONTROllER
INTERFACE

:

~

SYSTEM
SERIAL
INTERFACE

!---:~==========:t__~C~O~N~TR~O~l~L;ER~~
POWER

INTERFACE

UP INTERFACE

Figure 2. 29C53 Block Diagram

14-208

Architectural Overview

SYSTEM INTERFACE (SLD interface)
The system interface's primary function is to allow the 29C53 to transfer a B-channel datastream to uther components
using the SLD interface. It also can pass the entire'S' datastream using the ELD mode.
As shown in Figure 3, the SLD system interface consists of three lines: the SLD bidirectional data line, the 512KHz
SCL clock line and the 8KHz SDIR data direction line. The 29C53 can be operated as an SLD master or slave. As an
SLD master, the 29C53 generates the SCL and SDIR line signals. Data information is passed bidirectionally between
the master and slave using a TCM transmission technique. The transferred data is buffered in the 29C53. allowing
asynchronous transfer between the external and internal data. When in the SLD slave mode, the system interface may
be used to access the 29C53s internal registers.

DIGITAL
SUBSCRIBER

29C50

LINE CARD

SLD

SLD

SDIR

SDIR

29C53

29C53

SCL

SCL

29C53 AS SLD MASTER

29C53 SLD SLAVE

2952

Figure 3. SLD Block Diagram

MICROPROCESSOR INTERFACE
This standard parallel interface has the capability to monitor and control the 29C53 functions as well as handle data.
To the microprocessor, the 29C53 appears as an asynchronous peripheral. When the microprocessor accesses the 29C53,
the 29C53's parallel internal bus becomes an extension of the microprocessor's bus.
All registers interfacing to the 29C53's internal parallel bus are double-buffered,permitting single-cycle (direct) access.
The microprocessor read cycles are not synchronized with the 29C53; rather, the microprocessor immediately reads data
from the slave portion of the accessed register via the parallel bus. In a microprocessor write operation, the data to be
written into a 29C53 register is first latched at the microprocessor bus interface. Then, during a synchronized internal
parallel bus cycle, this data is transferred to the addressed register after the microprocessor operation is completed.

POWER CONTROLLER INTERFACE
The power controller interface, functioning as a general purpose interface, uses four pins to provide control to and accept
status from an external device used to transfer power over the CCITT compatible S or U interfaces. Two pins are inputs,
one is an output and one is configurable as either an input or output. The bidirectional line defaults to the input mode
on power-up. This interface also can be used to indicate SLD status.

SUBSCRIBER LOOP INTERFACE
The subscriber loop interface may be operated in either of its main modes; S or ELD. The primary mode is operating
as an S transceiver. In this mode the 29C53 provides an internal driver for transformer coupled interface for 4 wire
applications conforming to CCITT recommendation 1.430.
The subscriber loop interface in the S interface mode is coupled through external pulse transformers to standard telephonetype twisted pair cables. One pair is used for transmit an? the other for receive.

14-209

inter

Architectural Overview

The 29C53, functioning as a subscriber loop interface master in a multidrop application, can interface with up to eight
slave 29C53's. In this multiplexing operation, when a slave wishes to initiate a data transfer to the master, it requests,
gains access, and transfers the data in accordance with the D-channel line access protocol defined in CCIlT recommendation 1. 440.

EXAMPLE: ISDN EXCHANGE OVERVIEW
The 29C53 transceiver can be used in a number of applications, in a digital PBX or central office system. In the typical
ISDN exchange illustrated in Figure 4, the 29C53 is used in the voice/digital work station, on the digital line cards in
the PBX, in the local data multiplexer to the PBX, and in the network terminator NT!. These applications are typical
examples to illustrate potential uses of the 29C53 and are not intended to depict actual detailed applications.

ISDN T1
VOICE/DATA
WORK STATION

4-WIRE
DIGITAL
LINE CARDS
S
INTERFACE

U
~INTERFACE

4
TERMINAL

PBX
CENTRAL
OFFICE

4

NETWORK
TERMINATOR
(NT1)

ISDN T1
VOICE/DATA
WORK STATION

Figure 4. Typical ISDN Exchange Configuration

4·WIRE DIGITAL LINE CARD
The digital line card interfaces up to eight digital subscribers with the PBX backplane. In this application, the line card
consists of up to eight 29C53 transceivers, a 2952 line card controller, and an 80C5l microprocessor.
The digital line card interfaces with two TDM highways and an HDLC line on the PBX backplane through the 2952.
The 2952 inserts its data in the assigned time slots on either TDM highway under software control and can accept data
from any time slot on either highway. The B! and B2 channels, voice/data information from the TDM highways, are
directly coupled through the 2952 and 29C53 to the subscriber equipment. Control of the interface and time slot ,allocation
is determined by the PBX central processor, and central processor control information is coupled to the 2952 over the
HDLC backplane interface or interleaved on the TDM highways. In addition to making the TOM time slot assignments,
inputs from the central processor can be used to set up the 2952 and the 29C53s, to pass commands and data to the
SOC5! and pass D-channel command information for the subscriber equipment through the 80C5l to the 29C53. The
SOC5! also can receive command information from the TDM backplane via the 2952 or directly from the central processor
through the backplane.
14-210

inter

Architectural Overview

The 2952 derives its timing from the PBX backplane and functions as the SLD interface master. In this capacity, the
2952 multiplexes up to eight digital subscribers to the PBX backplane through the generation of the SLD timing and
control signals.
The 29C53 provides a 4-wire ccnT ISDN S interface with the voice/data digital subscriber equipment. In this capacity,
it serves as the S subscriber loop interface master relaying the B I, B2, and D-channel information between the line card
and the subscriber equipment. This digital line card can also be used as a ·multipoint control for data/data transfers
through B I and B2 channels.

PBX
LINE CARD
BACK PLANE
SIGNAL USER

S SUBSCRIBER
LOOP INTERFACE

SLD
INTERFACE
B1

TO
DIGITAL
SUBSCRIBER

=:J
=:J

TO
DIGITAL
SUBSCRIBER

::=J

+

TDM TDM HDLC
HWY1 HWY2 HWY

DATA
HDLC

B2

3
29C53

~------D------~

Figure 5. 4-Wlre Digital Line Card

VOICE/DATA WORK STATION
The 29C53 transceiver in a voice/data work station enables this work station to interface with a digital PBX. In this
example, as illustrated in Figure 5, the work station includes a 29C53, an 80186 microprocessor, RAM and ROM
memory, an 8274 multi-protocol serial controller, communication interface logic, a 29C50 combo, and a VSDD video
color monitor controller.

14-211

Architectural Overview

The 80816 serves as the heart of the work station as well as handling the data portion of the voice/data telecommunications
interface. In the transfer of digital data, the 8274 packetizes the digital data, provides the serial/parallel interface and
provides the DMA handshake interface with the 80186 for efficient data block transfers. In this operation the 8274
extracts the data from the B2 channel on the SLD highway and also places the data on the SLD B2 channel. In addition,
the 8274 buffers the data, performs the serial/parallel and parallel/serial conversions required to interface the 29C53
with the microprocessor bus, and notifies the 80186 when it is ready to transmit or has received data initiating a DMA
transfer. The 29C53 power controller interface is programmed to provide status for the data on SLD; the interface logic
allows multiple slaves to share the SLD line. The 29C53 now frames the data (B2) for SLD highway insertion and
removal. The 29C50 interfaces the B I voice channel with the subscriber handset on the workstation.

In the work station operations the 8255 and keyboard accept user inputs and enable the 80186 to store them until required.
The VSDD interfaces a color monitor with the microprocessor bus. In this operation the VSDD manages and controls
the data display refresh memory. It also provides the work station with pixel orientated, high resolution, color, alphanumeric and graphic display capability. The work station ROM memory stores the operating system while the RAM
memory stores programs and data.
The 29C53 serves as the S subscriber loop interface and it receives its instructions from the PBX digital line card via
the D-channel through the 29C53 parallel microprocessor interface to the 80186. On receiving a voice select command
the 80186 programs the 29C53 to pass BI voice information to the 29C50. The 8274 also instructs the 80186 when the
29C53 is ready to transmit or receive digital data. During transmit, the 80186 transfers data from RAM memory to the
8274. During receive, the 80186 transfers data from the 8274 to the RAM memory.

SLD

S

INTERFACE

INTERFACE

c:

61

29C50

3

~_~_c:

INTERFACE
COM
INTERFACE
LOGIC

COLOR
CRT
MONITOR

Figure 6. Voice/Data Work Station

14-212

Architectural Overview

LOCAL DATA MULTIPLEXER
The local data multiplexer interfaces up to eight 19.2 kb/s terminals with the PBX over a single 4-wire S interface loop
without the need for statistical mUltiplexing. In this application, the local data multiplexer uses up to eight 8256 MUART's,
a serial/parallel shift register, an 80186 microprocessor, RAM and EPROM memory and a 29C53 transceiver.
In this local data multiplexer, two blocks of memory are reserved for each terminal; a transmit buffer memory and a
receive buffer memory. The 80186 controls the data transfers between the MUART's and the buffer memory. When a
MUART requires data for its terminal, it interrupts the 80186 and the 80186 transfers data from the appropriate data
buffer to the MUART. When a MUART receives a character from its terminal, the MUART interrupts the 80186 and
the 80186 transfers the character from the MUART to the appropriate buffer memory.

81
TERMINAL

S

SLD
INTERFACE

R8-232

+ 82
29C53

8256

C
C

•

•

FACE

•

•
•

•
TERMINAL

8256

EPROM
MEMORY

R8-232

Figure 7. Local Data Multiplexer

The serial/parallel register extracts data from and places data in the SLD Bl and B2 channels providing 128 kb/s
throughput. In addition, it buffers the data, performs the serial-to-parallel and parallel-to-serial conversions required to
interface the 29C53 with the microprocessor bus and notifies the 80186 when it is ready for a data transfer.
As in the voice/data work stations, the 29C53 serves as the S subscriber loop interface slave and receives its channel
selection commands from the 29C53 in the PBX digital line card. In this application, the 29C53 transfers data on both
B-channels across the SLD interface and the 80186 transfers data between the buffer memory and the 29C53, in the
same manner as in the previously described voice/data work station. D channel information and 29C53 commands are
passed across the 29C53 microprocessor interface.

14-213

Architectural Overview

29C53 MULTIPOINT DATA MULTIPLEXING
The 29C53 transceiver also can be used to multiplex up to eight ISDN Tl terminal in a multidrop configuration to a
29C53 line card in accordance with CCITI recommendation 1.430. In this configuration, the 29C53 in each ISDN Tl
terminal functions as the subscriber loop slave and the 29C53 in the digital line card serves as the subscriberloop master.
As illustrated in Figure 8, the eight terminals can be connection on a line up to approximately 200 meters long. The
eight terminals also can be connected on a line up to 500 meters long provided, the eight terminals are within 30 meters
electric8.Ily, from each other.
In transmitting information to the terminals the 29C53 master transmits the information in a CCITI 1.440 LAP.D
environment. Th!-s protocol assigns the B 1 annd B2 channels to the appropriate terminal.
The master 29C53 in addition to passing a D-channel message on to the line card controller, echoes the message back
to the slave 29C53 on the E-channel. The' slave 29C53 compares this E-channel input with the transmitted D-channel
message. Should the slave detect an echo error, it halts the transmission, notifies the local microprocessor to retransmit
the message, and monitors the loop to initiate another transmit operation.
A slave 29C53 requests access to the master in accordance with D-channel line access protocol defined in CCITT
recommendation 1.440. When an ISDN Tl terminal wishes to transmit data to the line card, the slave 29C53 monitors
the received D-echo channel to determine if the D-channel is available. On determining that this channel is available,
the terminal requests and gains access of the subscriber loop. On gaining access, the terminal transmit' the message
through its slave 29C53 to the master 29C53.

I..

..I

200M

TE

NT2

TE

• • • • •

•

TE

TE2

r--£J

TE1

TES

I"

TE4

TE1, TE2, TE3,
ANDTE4ARE
WlTHIN30M
OF EACH OTHER

500

"I

Figure 8. Multipoint Data Multiplexing

14-214

inter

Architectural Overview

A variety of higher level protocols can be used to transfer data from the 29C53 master to the slaves. These protocols
may be packet switching or multiframing. In a packet switching protocol, each slave may be assigned a distinct address.
In accessing a terminal, this address is included in the message headers. In a multiframe protocol, the AF pulse can
serve as a start pulse. The master 2953 inserts the AF pulse in the first frame in a predetermined block of frames. Each
terminal is assigned a particular B-channel frame in the sequence. The protocol at the master 29C53 inserts the data for
each terminal in the appropriate frame and the terminals protocol extracts the date from the assigned frame.

NETWORK TERMINATOR (NT1)
The network terminator interfaces a voice/date workstation with a 2-wire digitai central office or remote mUltiplexer unit
(RMU). This terminator consists of a U transceiver, a 29C53 transceiver and power control circuit.
The 29C53 interfaces with the subscibers voice/data work station over its 4-wire S interface loop and interfaces to the
U transceiver via the ELD interface. The U transceiver interfaces with the existing 2-wire central office wire plant. The
central office transfers date (Bl + B2) and control information (D) through the U transceiver and 29C53. The control
information for the network terminator comes from the line terminator and end terminator (LT and ET respectively).
Remote control and status information may be transferred to and from this NTI network termination over the U and
ELD interface's C-channel under the control of the line card microprocessor .

..4 t - - - - - - - - - B 1 , 82, D - - - - - - - -__
_

S
INTERFACE

LOO,"

~

ELD
INTERFACE
29C53

POWER
CONTROLLER
INTERFACE
,"OWER
CONTROL
CIRCUIT

•

cJ

U

INTERFACE
U
TRANSCEIVER

Figure 9. Network Terminator NT1

14-215

*

inter.

Archltectura.1 0 vervlew

October 1984

@INTELCORPORATION,

1984--~~
14-216

inter

Architectural Overview

IATC 29C55 CITC
COMMUNICATIONS INTERFACE
TRANSCEIVER/CONTROLLER
SLD Interface Compatible
• Complete
Interrupt Structure
• Master/Slave
• ProgrammableModes
Power Down Mode

Transceiver
• 2144WireKB/SDigital
Data
Rate
• MicroprocessorTransfer
• Microprocessor Interface
FIFO Buffers
• Synchronous Serial
Port
•

•• Low Power CHMOS

FEATURES/BENEFITS
• 2 wire 'full duplex point-to-point digital baseband transceiver; can be used in telecom PBX/digital subscribers or
datacom point-to-point modem applications
• CHMOS; low power consumption
• Power down mode; even lower power consumption when not operating.
• Synchronous serial port; allows external protocol handling with the transceiver transparently receiving/transmitting.
• 144K bits/sec effective data transfer rate; high throughput voice/data, voice/voice or data/data information transfer
• Master/slave modes of operation; same part operates on both ends of line interface
• Microprocessor interface; interfaces to MCS 48, 51, 85, and 86 families
• SLD interface; directly compatible with iATC Telecom product family
• FIFO buffers; buffers data transfers to and from the microprocessor for line'interface D and B channel communication
• Complete interrupt structure; transceiver to microprocessor error and status information keeps system software updated
without the ne,ed for polling

CLOCK

2 WIRE
]
UNEINTERFACE

POWER

29C55

"""7":3~ SLD INTERFACE

14-,10+ SERIAL PORT
4

UP INTERFACE

Figure 1. 29C55 Overview Diagram
14-217

inter

Architectural Overview

GENERAL DESCRIPTION
The 29C55 is the first transceiver in the IATC family, and the 29CSS allows the extension of digital functions such as
integrated voice and data, directly into the subscriber equipment with a high speed, 2-wire digitally encoded data transfer.
The 29C5S is a 28-pin device which, when used with the 29CSI, 29S2 and a ,",P, implements a flexible point-to-point
digital voice/data system primarily intended for PBX application. It also includes a terminal-to-terminal mode which
allows general data communication applications. The 29CS5 incorporates transceiver and digital interface functions which
may be programmed for use at either end of the loop (PBX or telephone instrument). The 29C5S has four interfaces, a
digital SLD 29CX iATC Telecom interface, a 2-wire analog line interface, a general purpose digital synchrOnous serial
interface, and an MCS compatible microprocessor interface. The 29CSS requires a line card based microprocessor
attached to its microprocessor interface to control loop acquisition and initialization. (Refer to overview diagram Figure
I.) The internal architecture has an MTU, master timing unit, that controls all internal information transfer on the parallel
data/control/address highway. Also the 29C5S has an internal loop acquisition control timing unit for automatic loop
acquisition.

UNE

INTERFACE

BLD

BLD

SDIR
BCL

PORT

1X
RX
CLK
SFS

SIO
PORT

RECEIVER
LOOP ACQUlSmON
CONTROL nUING
UNIT (LAQ)

P9
PORT

Figure 2. 29C55 Block Diagram

LINE INTERFACE OVERVIEW
The 29CSS transfers data at 144kb/s over twisted pair 10QPs. Line data over the twisted pair is formatted into two 64kb/
s B channels and a 16kb/s D (signaling or data) channel.
The line interfaCe section of the 29C5S contains the transmitter and receiver which are used for communication over
the twisted pair. The transmitter section constructs the frame to be transmitted from the various programmed data ports,
encodes the data and drives the line. The receiver has a filter, a memory mapped echo cancellor, and a descrambler.
(Refer to block diagram Figure.2 for 29CS5 interface relationships.)
The sCTambler/descrambler section guarantees data reception without accidental cancellation when both transmitted and
received data streams are identical. The memory mapped echo canceller cancels both near and far end echo's caused
by wire gauge changes, bridge taps, and the terminating impedance. Penalties for wire gauges changes and bridge tap
limitations will be detailed in a future data specification.

14-218

Architectural Overview

Chip timing is derived via a Xtal Controlled Phase Locked Loop which locks to either of two time bases, depending on
what mode the device is programmed in. The PLL signal choice is automatically selected when the transceiver is
programmed as a slave or master. When programmed as a slave, the YCO is locked to the SLD interface; when
programmed as a master, the YCO is locked to the line interface.

MICROPROCESSOR INTERFACE OVERVIEW
A standard parallel processor interf~ce is provided for both control and monitoring of the 29C55 functions as well as
data handling. All control and configuration registers are directly addressed, and can be read from and written to.
The microprocessor interface has two FIFO buffers for both communication directions, each 18 bytes deep, and a
complete interrupt scheme. The FIFO's are used to buffer B 1+ B2 or B2 or D channel information, and the interrupt
scheme notifies the microprocessor of serial 110, FIFO, and line interface status and error conditions.

SYNCHRONOUS SERIAL PORT OVERVIEW
The third port is a digital synchronous serial port controlled by the 29C55. The serial 110 frame clock and bit clock are
generated on chip. The data rate is controlled by the selected channel (D, B2 or BI + B2) at either 16kb/s, 64kb/s, or
128kb/s between an external device and the synchronized internal data structure.

SLD INTERFACE OVERVIEW
The SLD has a 512kb/s bi-directional serial interface which is used by the iATC component family and is the iATC
communication backbone. This interface is a three wire interface; a data lead (SLD), direction lead (SDIR), and clock
lead (SCL). (See SLD block diagram Figure 3 for details.)
The SLD interface is controlled by the master SLD device, that is, the master SLD device generates the SCL and SDIR
lead signals. Data information is passed bi-directionally using a TCM transmission technique to the slave device. This
digital port is double buffered, allowing asynchronous to/from data transfer. The 29C55 is a master on the SLD in the
digital subscriber, and an SLD slave on the line card.

LINE CARD
SLD

DIGITAL SUBSCRIBER
SLD
COMBO
SLAVE

SDIR

29C55
MASTER

29C55
SLAVE

SCL

SDIR
SCL

Figure 3. SLD Block Diagram

14-219

2952
MASTER

intJ

Architectural Overview

APPLICATION OVERVIEW
The following application examples illustrate, in greater detail, the application overview example shown in Figure 4.
In an ISDN environment, the central office services, in the form of an intelligent remote multiplexer unit, will be
distributed to handle voice, as well as, growing digital data traffic.· This implies that future central office architectures
will include a distributed, remote multiplexer to locally handle voice as well as data traffic. The RMU can handle both
p'ublic and private subscriber needs, and the 29C55 can handle both data/voice, as well as, data/data transmission
requirements. The RMU switch in this overview could also be a PBX switching system. These applications are typical
examples to illustrate potential uses of the 29C55 and are not intended to depict actual detailed applications.

ISND
TERMINAL
PRIVATE
SUBSCRIBER
TERMINALS

2 WIRE
TRANSCEIVER
DATANOICE

MULTIPLE
CARRIERS

PUBLIC
SUBSCRIBER

DATA/DATA
2 WIRE TRANSCEIVER

RS232C

LOCAL DATA
MULTIPLEXER

REMOTE MULTIPLEXER
UNIT (RMU)

Figure 4. Application Overview

14-220

CO

inter

Architectural Overview

REMOTE MULTIPLEXER UNIT DETAILS
The line card can handle up to eight digital subscribers in the RMU as well as general switching systems. The information
transferred to the subscribers can be voice/voice for three party conferring, or voice/data for ISDN terminal applications.
The 80C51 handles all D Channel encoding to the digital subscriber from the HDLC control highway, or from interleaved
information on PCM No.1 or No.2 highway. The 80C51 also initializes the 2952 and 29C55, and assists the 2952 in
time slot assignment management.
The call processing controller receives control and signalling information from the central office across a carrier's time
slot(s) interleaved on one of the external carriers and then across internal PCM highways through a carrier synchronization
circuit. The 80186 manages all resources, and through the same 2952, passes control/signalling information to the line
card 8OC51 's through the local line card 2952.

TODIGITAL
SUBSCRIBER
Bl

~

J
_~['29C55

INTERNAL PLM
HIGHWAY
Bl B2

UNECARD
Bl
B2

-+

2952

..-+-t--+-t-....

3

MULTIPLE
SYNC AND
CARRIERS
DRIVER . .------I~ TO
INTERFACE
SWITCH

2952

80186

'{}

~

8OC51

A.

PCM 1
PCM2
HDLC

<

II-

.

CALL PROCESSING
CONTROLLER

Figure 5. Remote Multiplexer

At 4.096mb/s, the internal PCM highways can handle 128 time slots. Each 2952 can access all time slots on both of
the PCM highways, therefore, the RMU does not need a separate space/time switch card if the following design
reqnirements are met:
e, If the blocking ratio is 1:1, 128 analog subscribers or 64 digital subscribers can be connected minus any time slots
used for signalling, tones, music, etc.

e This implies five T1 carriers can be connected to the RMU, or four PCM 30 carriers for no transmission blocking.
e Both PCM's transmit and receive paths must be tied together.

14-221

inter

Architectural Overview

LOCAL DATA MULTIPLEXER DETAILS
Eight 19.2kb/s RS232C terminals can be handled by one 29C55 transceiver without the need for statistical multiplexing.
Bandwidth considerations require that the 29C55 handle 16 bytes bi-directionally in the time that it takes 8 19.2kb/s
terminals to transfer one byte to/from the multiplexer. Eight terminals require that the 8256 MUARTs be polled every
0.5 msec when the character's are 10 bits each, and the terminals' are transmitting at 19.2kb/s. The 29C55 can transfer
2 bytes every 125 microseconds, or 8 bytes every 0.5 msec. Statistical multiplexing allows further terminal concentration
with one 29C55 based multiplexer.
The 80186 has DMA capability, and this capability can be used to efficiently transfer data to/from RAM ,.nd 8274. The
8274 can be used as a B 1 + B2 channel data protocol handler, and can be synchronized by the 29C55 transceiver serial
port. D channel signalling and control is transferred through the 29C55 parallel interface, buffered by the internal FIFOs,
decimated/collated, and transferred/interlaced in the line interface. D channel bandwidth can be used for switch is then
further encoded by the 80186 and transferred to the terminals in the form of control command, and signalling messages.
The 80186 can be used as a message buffer controller between the terminals and the switch using the D channel.

l6KS/S

L...._ _..I SIGNALLING

CONTROL

Figure 6. Load Data Multiplexer

14-222

0

TO
SWITCH

intJ

Architectural Overview

ISDN TERMINAL DETAILS
The 29C55 used in this configuration is a telecom device with the SLD interface connected to a 29C50, the programmable
codec/filter. The 29C55 is treated as a peripheral to the local microprocessor. The local microprocessor, SOC51, configures
the 29C50 through the 29C55 with information obtained from local memory or from the Iinecard via the line interface;
the 29C50 has the codec/filter functions and is the slave to the 29C55 SLD master.

81

82

o

Figure 7. ISDN Terminal

The 8044 acts as a D channel programmable protocol controller, and provides an interface to LCDs, pushbuttons, keypad
matrixes, LEDs and telemetry inputs from a line card D channel controller. The S044 has to be polled by a switching
system. The 8044 could handle a part of the HDLC LAP D protocol as a D channel protocol controller example.
The 80C51 is a data rate adapter for RS232C terminals and a keyboard interface. If high speed data rates (I2Skb/s with
B 1 + B2) are required for terminal data transfers the 80C51 can program the 29C55 to route both B I + B2 through the
parallel port, temporarily rerouting B 1 traffic away from the SLD interface. Likewise, if three party conferencing is
required, B I + B2 can be routed through the SLD interface temporarily away from data services through either the serial
or microprocessor port.
NOTE: This configuration has all CMOS parts, and could be powered by the PBX. Becaue some applications require
continuous voice information transfer regardless of local power failure, the RS232C serial information and the
29C55 serial port could be optically isolated and powered by the external terminal.

14-223

iATC 29C53
DIGITAL LOOP CONTROLLER

•
•
•
•
•

4-Wlre Full Duplex Digital Transceiver
CCITT 1.430 'IS" Interface Compatible
ISDN Basic Rate 144K Bit Per Second
D-Channel Processing Support
Point-To-Point or Point-To-Multipoint
Bus Configuration

•

Same Device Used at Both Ends of
Loop

Exceeds 1K Meter Range
• IATC
Standard SLD Interface

• MCS Standard Microprocessor

•
•
•
•

Interface
Peripheral Interface/Status Port
Low Power, High Density CHMOS
Single + 5 Volt Supply

The Intel Advanced Telecommunication Component (iATC) 29C53 Digital Loop Controller (DLC) is a 4-wire
transceiver/controller that is CCITI 1.430 compatible and can function at either loop end. This part has
integrated those features which are pertinent to the transceiver function; yet it offers efficient interfacing to
other system components such as combos, line card controllers and MCS microcontrollers through the SLD
and microprocessor interface ports. It is primarily intended for use in Integrated Services Digital Networks
(ISDN) as a basic rate digital data transceiver which transfers data at 144 Kbps as three separate channelstwo 64 Kbps digitized-voice/data channels (B-channels), and a 16 Kbps signaling/data channel (D-channel).
The B- and D-channel routing along with D-channel processing (packetization) is programmable through either
the microprocessor or SLD interface ports. The 29C53's loop interface uses a 100% pulse-width pseudo-ternary inverted line code similar to Alternate Mark Inversion, which meets CCITI's "5" interface recommendations. It is capable of interfacing with up to eight 29C53s in a passive or extended bus configuration as well as
point-to-point.

Plastic Chip Carrier"
350 x 550 MILS

28-Lead Dual-In-Line Package

_SLD_ADO
CS
INT
ADI

INT

ADO

SLD

ADI

ADZ

cs

AD2

SDIR

AD3

SCL

AD3

ALE

AD4

SDIR

AD4

RES

CLK

ALE

CLK

VCC

VSS

RES

VSS

WR

ADS

VCC

ADS

RD

AD6

WR

AD6

P4

AD7

RD

AD7

P3

PI

P4

PI

P3

P2

SCL

LX+
LRPZ
LXLR+

LX+

LR+

LX-

LR-

270097-1
270097-2
'Call sales representative for availability

Figure 1. 29C53 Pin Configurations

Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
October 1985
@ Intel Corporation, 1985
Order Number: 270097-001

14-224

inter
Symbol

IATC29C53

Vee
VSS
CLK

PinNa.
8
22
23

Res

7

LX+, LX-

13,14

LR-, LR+
SLD

15,16
2

SCL

4

SDIR

5

CS

3

RD

10

WR

9

AD (0-7)

19-21,
24-28

ALE

6

INT

1

P1,P2

18, 17

P3

12

P4

11

Function
POSITIVE SUPPLY: Input voltage is + 5V ± 5%.
GROUND:OV
MASTER CLOCK: The 3.84 MHz system clock input is the reference for the
loop and the SLD interface.
RESET: (Active high input). A high level on this pin initializes most control
registers and places most interface outputs in a high impedance state.
Operation begins when the high level is removed.
POLARIZED TRANSMIT LOOP INTERFACE PINS: These pins will directly
drive the twisted pair line through a 2.5:1 line transformer. The transmitted line
code is similar to alternate mark inversion.
RECEIVE LOOP INTERFACE PINS: The receiver is not sensitive to polarity.
SUBSCRIBER LINE DATALINK: This pin transfers serial data between the
29C53 and other SLD based components (e.g., 29C51 , 2952, 29C55, etc.).
SUBSCRIBER CLOCK: 512 KHz signal may be either generated or received by
the 29C53. This signal clocks the data on the SLD pin.
SUBSCRIBER DIRECTION: An 8 KHz signal may be either generated or
received by the 29C53 to indicate SLD data direction and framing. A high level
indicates and enables master to slave transfer; a low level indicates slave to
master transfers.
CHIP SELECT: (Active low input). A low level on this pin enables the 29C53
bus interface for the next bus cycle. The value is latched by the falling edge of
ALE.
READ STROBE: (Active low input). When low, data is transferred from the
selected register to the data pins AD (0-7). When no local microprocessor is
connected, this pin should be tied to Vss.
WRITE STROBE: (Active low input). When WR changes from low to high, data
on pins AD (0-7) is latched into the 29C53. When no local microprocessor is
connected, this pin should be tied to Vss.
ADDRESS/DATA PINS: This is a standard MCS microprocessor bus used to
transfer address and data between the local microprocessor and the internal
registers of the 29C53. When a local microprocessor is not used, these pins
should be tied to Vss.
ADDRESS LATCH ENABLE: Address is latched from AD(0-7) on falling edge
of this signal. State of CS is also latched at this time.
INTERRUPT REQUEST: This is an open drain active low output. (See text for
the interrupt conditions.)
PERIPHERAL INTERFACE INPUTS: These are standard CHMOS high
impedance inputs that are sampled at a 4 KHz rate (once per "s" frame). The
sampled data is stored in the LPS register (bits 5 and 6). If any peripheral input
bits have changed value since the previous frame, an interrup!condition is
indicated; only present status is available.
PERIPHERAL INTERFACE INPUT/OUTPUT PIN: When configured as an
input, this pin has the same characteristics as P1 and P2. The sampled data is
stored in the LPS register (bit 7). When programmed as an output, this pin
outputs the data stored in the PEC register (bit 1). The pin is configured by bit 2
of the PEC register. An alternate function of this pin and P4 is to indicate the
status of the SLD interface. See the section on the SLD interface.
PERIPHERAL INTERFACE OUTPUT PIN: This pin outputs data stored in the
PEC register (bit 0) or SLD status.
14-225

l
------------------------~

LX+

OUTPUT
DRIVER

LX-

D- CHANNEL PROCESSOR
S- BUS

XMIT FORMATIER
AND TIMING

"

.,..

~I

ANALOG
REF.

~

~

N
CD
~

.j:>
I
I\)
I\)

0>

0

~I

LR+

~I

FILTER
,
AND
LR- - - - . DETECTORS

n

3
SLD
INTERFACE

;00:-

~
U)

o

en
w

C

~'I
3

LINE
INTERFACE
UNIT

~

SLD STATUS
AND
PERIPHERAL
INTERFACE

RBUS
XFER
TIMING
CONTROL

SLD
INTERFACE
UNIT

._--------------------------

IeJ

~

:2

@

Iiiiil
c:::o

:2
'liiI

'"

~,

Co)

@
~

~
~
~

c:::o

@

:2

inter

IATC29C53

29C53 FUNCTIONAL DESCRIPTION
The 29C53 Digital loop Controller is a multi-channel
ISDN transceiver which provides a multiplicity of advanced communication functions and services. The
29C53 allows the extension of digital voice and data
directly to subscriber equipment over a 192 Kbps
baseband 4-wire serial interface. The 29C53 is a 28pin device which, when used with the iATC 29C51,
2952 and a microprocessor implements flexible
point-to-point or point-to-multipoint CCITI 1.430
compatible voice/data communications. It is primarily intended for use in PBX's and ISDN terminal
equipment.
The 29C53 may be incorporated at either end of a
subscriber loop interface (at the line card or digital
telephone/terminal). As shown in Figure 2, the
29C53 has four separate interfaces: a serial SlD
iATC Telecom system interface; a parallel peripheral
interface; a parallel microprocessor interface and a
4-wire CCITI compatible S-interface (subscriber
loop interface).

THE BLOCK DIAGRAM
Figure 2 represents a block diagram of the 29C53.
Its three major blocks, 'the line interface unit, the
D-channel processor and the SlD interface unit are
interconnected by two buses. The parallel bus
(P-bus) is used to transfer processed D-channel
data and general status and control information
while the serial bus (S-bus) is used to transfer
B-channel data and unprocessed D-channel data
between the line interface unit and the SlD interface
unit.
The SlD interface unit consists of shift registers and
serial to parallel converters. Data from both the
S-bus and the SlD interface is stored here in appropriate parallel registers before it is loaded into shift
registers and passed on. All of the timing Circuitry for
the SlD interface is located here. This block also
contains a command processor which is responsible
for contrOlling the functionality of the chip.
The D-channel prQcessor has three major sections.
An HDlC section performs some of the basic LAPD
protocol functions such as zero insertion or deletion,
flag recognition or insertion for frame delineation,
abort flag recognition, idle state transmission, and
end of packet frame check sequence for both data
directions. The FIFO section consists of two 32-byte
buffers, one for transmit and one for receive. The
control and status section monitors the FIFO data
levels and the HDlC section for progress. Interrupts
or requests for service may be generated for conditions such as a full or empty FIFO, loss of sync,
frame check error, overflows and aborts.

The line interface unit contains the line drivers and
receivers for the S interface. Connection is made to
the transmission lines through a 2.5:1 line transformer. Formatting, timing and synchronization are also
provided here. The receiver includes filters, AGC circuitry, threshold detectors and a loop delay shift register. The loop delay shift register maintains the
proper internal frame relationship regardless of loop
length (it allows extra propagation delay time for
long loops or line repeaters). The received D-channel bits are logically looped back to create the
E-channel bits in an NT application through the
E-channel circuitry.
The. microprocessor interface circuitry allows the
29C53 to function as a peripheral to an MCS microcontroller. The internal P-bus actually becomes an
extension of the microcontroller's bus. All internal
registers are directly accessible..
The spare bits processing block provides access to
all the miscellaneous bits in the S frame except for
the framing bits and the balance bits. When spare bit
functions become defined, they can be easily monitored and modified.
The peripheral interface circuitry provides an auxiliary port for contrOlling auxiliary peripherals such as
power controllers, etc.

SLDINTERFACE
The SlD interface provides half-duplex 512 Kbps
communication with other devices incorporating
SlD interfaces (such as line card controllers and codec/filters). Of the 256 Kbps in each direction, 128
Kbps is dedicated to voice/data channels B1 and
B2. The remaining bandwidth is used for the D-channel data and various control and status transfers depending on the exact application.
As shown in Figure 3, the SlD interface consists of
three lines: the SlD bidirectional data line; the
512 KHz SCl clock line; and the 8 KHz SDIR data
directon line. SlD data is updated on the rising edge
of SCl and is latched on its falling edge. The 125 pos
SlD frame period consists of 32 bits transferred in
master to slave direction followed by 32 bits in the
slave to master direction. The 32 bits compose four
8-bit bytes in the following order: B1 and B2 (voice
or data bytes); C (control byte); and 5 (signaling or
status byte). Unprocessed D-channel data may be
transported over the S-byte in bits 0 and 1, or over
the B2 byte.
The 29C53 can be operated as an SlD master or
slave. As an SlD master, it generates the SCl and
SDIR signals. When SDIR is high, the SlD pin outputs data. As a slave, it receives SCl and SDIR sig-

14-227

inter

iATC29C53

nals and SDIR enables the SLD output driver when it
is low. The SLD bus is always active; no powereddown or inactive mode is defined.

nominaIlY.0.75 volts in amplitude.' Marks alternate
polarity except when a "code violation" is created
for establishing frame reference timing.

In a network termination (NT) application (line card),
whether a microprocessor is connected to the
29C53 or not, the SLD control and signal bytes may
be used for 29C53 configuration and D-channel
transfers. The command bytes are interpreted and
executed by the 29C53's command processor circuit. The command processor generates internal Pbus cycles to carry out those commands. Internal
prioritization resolves P-bus collisions between microprocessor-interface generated and commandprocessor generated cycles. In case of collisions,
the microprocessor interface has higher priority to
minimize access time but both cycles will be completed.

The nominal bit rate is 192 Kbps. Figure 4 shows the
frame structure. The 250 f.Ls frame transfers two octets of 81, 82 and four bits of D data. The E bits in
the master to slave direction, echo received D-channel data. The "S" interface slave compares the receive E-channel . data to its transmitted D-channel
data for D-channel contention as defined in CCID
recommendation 1.440. If these bits do not agree,
then the slave will abort .its transmission effort. The
S, FA, and N bits are all accessible and programmable.

"S" TRANSCEIVER
The 4-wire "S" transceiver circuit in the 29C53 conforms to CCID recommendation. 1.430. This transceiver provides the internal drivers for transformer
coupling to standard telephone type twisted pair cables.
The "S" transceiver line code is 100% Pseudo-Ternary Inverted code which is similar to Alternate Mark
Inversion, except that logical ones are transmitted
as spaces, logical zeros as marks. A space has a
nominal differential voltage of zero volts. Marks may
be either positive or negative differential signals,

B1

SLD

SDIR

J

c

B2

The activation protocol described in 1.430 is supported by the 29C53. An inactive receiver can achieve
bit synchronization to an incoming signal with approximately 30 mark-mark transitions. Info 2 or 3
frame alignment is not officially recognized until reception of 16 frames, to allow settling of the 29C53's
adaptive receive data thresholds. The full activation
sequence will complete in approximately 10 ms.
The 29C53 is not sensitive to the polarity of the wire
pair connected to LR + and LR -. Marks are always
interpreted as zeros and framing relies on violations;
not on absolute polarity. System configurations may
dictate that care be taken in connecting the LX' outputs. In a multi-drop bus configuration all TE transmitters must be connected with the same polarity so
that positive mark to negative mark contention does
not take place in the framing and D-channel bits.

S

B1

B2

C

S

SLAVE - - - - MASTER
MASTER

~

SLAVE

SCL

270097-4
B1 • 64KBPS DATA
. B BIT BYTE
B2· 64KBPS DATA
• B BIT BYTE
CONTROL/DATA • B BIT BYTE
S· SIGNALING/DATA· B BIT BYTE
ALL BYTES ARE MSB FIRST

c·

Figure 3. SLD Interface

14-228

inter

IATC29C53

• WASTER TO SLAVE (NT TO TE)

F L

~-BI-B

BITS - l E 0 A FA N I - B2-B BITS-j E 0 SII- BI-B BITS---/ E 0 S2I-B2-B BITS-l E 0

L

:rw!~ IIIII H:H~ IIII EH~ IIII EHffiW
• WASTER TO SLAVE (TE TO NT)

f---I
2 BIT OFFSET
F L

~-BI-B

BITS

-I L

0 L FA L I - B2-B BITS-j L

0 L I- BI-B BITS---/ L

0 L I-B2-B BITS-l L 0

L

:ruff tffi-RJ1fl [DlJill8JbW 8fl:fJ
r

~B BIT WIOE FRAWE

-

~

250 MICRO SECONDS

270097-5
A· BIT USED FOR ACTIVATION
B1, 2·64 K BPS DATA
D· DCHANNEL BIT (16K BPS DATA)
E • D CHANNEL ECHO BIT
F· FRAME BIT

FA' AUX. FRAME BIT
L • DC BALANCING BIT
N· BIT =
Sl, 2· RESERVED FOR FUTURE STANDARDIZATION

FA

Figure 4. The S-Interface Frame Structure
The 29C53, functioning as an "S" interface master
in a multi-drop application, can interface with up to
eight slave systems. In this multiplexing operatiQn a
slave initiates a data transfer to the master, by requesting access and transferring the data in accordance with the D-channelline access protocol (1.440).
Figure 5 shows typical applications of the 29C53.
The frame alignment timing diagram Figure 6(b)
shows the relationship of the "S" interface data to
the SLD data. Figure 6(a) shows the block diagram
used for the timing diagram. The top timing diagram
shows the transmitted "S" data stream from the network terminator (master). The dotted lines depict up
to 20 ,""S propagation delay to the "S" receiver at the
terminal equipment (slave) end. The terminal equipment's transmitted "S" interface frame is designed
to have a fixed 2-bit frame alignment delay from that
of its received frame. The adjustment for loop propa-·
gation delay is accounted for in the network terminator's receive circuitry (loop delay section of block
diagram). The loop delay circuitry will compensate
for up to 10 bit periods of round trip propagation
delay which allows line repeaters to be placed in a
loop that is several thousand meters long.

POINT-TO-POINT

- - - l k - - -....11

1-1'

~~----------------~~
PASSIVE BUS

EXTENDED CLUSTER

1_

·1

5 0 0 M - -...

MICROPROCESSOR INTERFACE
This interface is deSigned to operate with standard
Intel 8-bit microprocessors such as the MCS@-48,
MCS-51, MCS-85 and iAPX-86 families. All of the
29C53's internal registers are accessible and most
are available by a single microprocessor cycle. access.
14-229

270097-6

Figure 5. 29C53 Bus Configurations

inter

IATC 29C53

NT

TE
RECEIVE
DATA PATH

'S' SLAVE -

TRANSMIT
DATA PATH

(8)

'S'MASTER

(A)

'u'
1 - - - - - - - , , < - - - - - - 1 29C53

TRANSMIT
DATA PATH

INTERFACE

TO c.o.

4 WIRE"S"
RECEIVE
DATA PATH

(D)

(E)
270097-7

Figure 6(a). Frame Alignment (Block Diagram)
The maskable interrupt pin, on this port, is activated
by the following interrupt status features: D·channel
errors; loss of sync on "S" loop; change in spare
bits or peripheral interface data; FIFO data transfer
requests.

configurable pin defaults to the input mode on power
up.
The peripheral interface can also be used to indicate
SLD status. Figure 7 shows the timing diagram of P3
and P4. 81, 82 and D-channel data on the SLD pin
can be selected or gated by using these signals. As
noted on the P3 timing, the D·channel is imbedded
in the last two bits (0, 1) of the signaling byte.

Alternatively, the 29C53 can operate in the stand·
alone mode in line card and NT applications. This
mode is determined on a power-up condition or after
a reset, provided all the microprocessor interface
pins have been tied to VSS, except for the interrupt
pin.

INTERNAL CONTROL AND STATUS
REGISTERS

PERIPHERAL INTERFACE

All of the 29C53's internal control and status registers may be accessed through the microprocessor
interface or through the SLD interface. When a microprocessor accesses a register, the address and
CS inputs are latched on the trailing edge of ALE.

The peripheral interface uses four pins to provide
control to, and to accept status from, external devices. Two pins are inputs, one is an output and one is
configurable either as an input or an output. The

81

SLD

SDIR

J

82

c

S

,

82

SLAVE -

MASTER -

SLAVE

c

S

,

r

MASTER

,I~
, _ _ _ _ _-~,
,

,

______--'f:

P3

270097-9

NOTE:
Status indicators are activated by the SST Bit in the PEG Register

Figure 7. 29C53 SLD Status Indicators

14-230

(A)

NT

SX

...
I--~

.81 (a)

l

A

82(a)

Bl(b)

~~~

--1

82(b-)

T

,

, ,I
I

(8)

V

DElAY

SR

....

...z
......
::I

::!!

~~
...
",

ID
C

iil

~~

-...
m

Sic
.....
~'"

"'

~

""
3

.I>I

I\)

~

SDiR

SLDR

~

III

.....

(C)
SLDX

CD

~

(D)

~

iii

SX

:=I

I\)

3

CD

o

CD

§I
3

~

(E)
SR

S-

ID

~
l§l

It:

0

ii'

~

iil
.....3

eJ~

ID

~ ...
::IU

.... '"

(F)
SLDX

~~

SDIR

~9
... ",
z

SLDR

o~

I.

'iii!

(A)
SX

I

CD

~

@
IiiiiI

~

.!.
z

~

r----

~

NOTE:

+
Depicts the beginning of the 'S' Interface frame
+ :(Ioadlng
edge of F bit) and the beginning of the SLD Interface frame.

@
aID
~

~

c::::>

@
~

IATC29C53

Op Code Table
OpCode

-

Operation

Argument

-

000

Reserved For Status Poll (Call Verify) By Master

001

Single Byte Transfer To Slave

RegAdr

010

Prepare Single Byte For Transfer To Master

RegAdr

011

Multiple-Byte o Data Transfer To Slave

!If Bytes

100

Multiple-Byte 0 Data Transfer To Master

Max !If Bytes

101

Multiple-Byte Configuration Transfer To Slave

!If Bytes

110

Multiple-Byte Status Transfer To Master

!If Bytes

111

Reserved For Status Poll (Call Verify) Tail & Idle

In an SLO access, the 29C53 receives a control byte
containing an operation code and an argument. The
three most significant bits contain the operation
code and the remaining five bits contain the argument. The operation code defines eight transfer
types.
SLD Control Byte
7

BITS

I

I

][

Argument

-

byte header specifying the number of following bytes
(less than or equal to the maximum specified) and
the status of the packet they belong to. All transferred data bytes belong to the same packet; the
transfers occur until the selected number of bytes
are transferred or an EOP (end of packet) is detect, ed. The EOP may occur even when there are additional bytes in the FIFO. The header byte contains
the byte count in the lowest five bits and the status
in the upper three bits..
!

OpCode

The 3~bit operation code in the control byte from the
iine card controller should normally be 111, indicating the idle state. The transferring of data to and
from the 29C53 is accomplished by indicating the
type and the number of bytes to transfer in· a nonidle control byte. When a polled response is requested, the 29C53 responds to the poll operation code
000. This can be used for the transfer of one or several bytes of information.
The register table below identifies the address of
each 29C53 register. The status registers are readonly registers while all control registers are read/
write registers. Because all the register addresses
do not fit into the 5-bit address space, a register test
mode has been included which permits reading the
contents of control registers at addresses which normally are status registers. Where no register is assigned a location in the register test mode, the normal status register located at this address is read.
The O-channel block transfers from the 29C53 to
the line card controller preface the data bytes with. a

Data transfers within the 29C53 cannot be made in
both directions simultaneously. Multiple commands
and data bytes may follow each other directly from
, the line card controller to the 29C53 if the previous
command has been fully executed.
It is possible to fully configure the 29C53 over the
SLO interface, as is done with analog per-line components. Provisions are also made to perform this
transfer at a 2 byte-per frame rate using both the C
and S bytes of the SLO. The first control byte of a
configuration transfer to the 29C53 specifies the
type of operation to be performed and :he n!Jmber of
data bytes to follow. The system interface command
unit loads the internal registers with the information
as it is received. When the specified number of data
bytes have been transferred, the 29C53 !lssumes
the next input is a control byte.
Ttie order of the bytes in a configuration or status
block transfer is determined by the addresses of the
internal registers. A multiple-byte transfer, beginning
with register OOH, transfers the data to or from that
register and increments the address counter.

14-232

IATC29C53

Table 1 29C53 Registers
Acc.as

Symbol

00000

RD

IXS

Interrupt Status

00000

WR(Rn

IMR

Interrupt Mask

00001

RD

DPS

D-Channel Processor Status

00001

WR (RT)

DPC

D-Channel Processor Control

00010

RD

LPS

Loop and Peripheral Interface Status

00010

WR (RT)

LCR

Loop Interface Control

00011

RDWR

PEC

Peripherl!!llnterface and E-Channel Control

Address

Name

00100

RD

RFN

Receive FIFO Status - " of Bytes Used

00100

WR(Rn

SCR

SLD Interface Control

00101

RD

XFN

Transmit FIFO Status - /I of Free Bytes

00101

WR(Rn

SOC

SLD Data Transfer Configuration

00110

RD

SBR

Spare Bits Receive Status

00110

WR(RT)

SBX

Spare Bits Transmit

00111

RDWR

LLB

Loop Interface Loopback Control

01000

RD

RFO

Receive FIFO Output

01001

WR

XFI

Transmit FIFO Input

01010

RDWR

GCR

General Command Register

01011

RDWR

DPR

D-Channel Priority Counter

01100

ROW

RFIL

Receive FIFO Interrupt Level

01101

RDWR

XFIL

Tr~nsmit

01110

RD

PLENH

Packet Length High Byte

01110

WR(RT)

DUTH

D-Channel Byte Counter Underflow
and Overflow Threshold

01111

RD

PLENL

Packet Length Low Byte

01111

WR(Rn

DOTH

D-Channel Byte Counter Overflow Threshold

10000

RDWR

AFD

Auxiliary Frame/Multiframe Division

10001

RDWR

PSR

Position Selection

10010

RD

RSR

Receive Service Request

10011

RD

XSR

Transmit Service Request

11000

RDWR

B1LS

B1 Data in Loop to SLD Direction

11001

RDWR

B2LS

B2 Data in Loop to SLD Direction

11010

RDWR

CR

Control Byte from SLD

11011

RDWR

SR

Signaling Byte from SLD

11100

RDWR

B1SL

B1 Data in SLD to Loop Direction

11101

RDWR

B2SL

B2 Data in SLD to Loop Direction

FIFO Interrupt Level

11110

RDWR

CX

Control Byte to SLD

11111

RDWR

SX

Signaling Byte to SLD
14-233

IATC29C53

ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ......... -1 O·C to + 80·C
Storage Temperature .....•.•.. - 65·C to + 150~C
Voltage on any Pin .... Vss - 0.5V to Vee to + 0.5V
Maximum Vo.ltage on Vee
with Respect to Vss ..................... + 7V
Total Power Dissipation .................. 500 mW

'Notice: Stresses above those listed under ':4bsolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

NOTICE: Specifications contained within .the
following tables are subject to change.

D.C. 'CHARACTERISTICS vee = +5V ±5%;Vss = OV;TA = 0·Ct070·C; ,
Typical Values are at TA = 25·C and Nominal Power Supply Values
DIGITAL INTERFACES
Symbol

Parameter

I,L

Input Leakage Current
(Excluding LR+, LR-)

V,L
V,H

Input Low Voltage
Input High Voltage

VOL

Output Low Voltage

VOH1

Output High Voltage
Output High Voltage

VOH2

,Max

Units

±10

,."A

-0.5

0.8

2.0

Vee + 0.5
0.45

V
V

Typ

Min

Test
Conditions
Vss

s:

Y,N

s: Vee

V

IOL = +2.0mA

2.4

V

IOH = -400,."A

0.9 Vee

V

IOH = -40~A

POWER SUPPLY CURRENT (Averaged over 1 ms)
Symbol
Parameter
Min

Typ

Max

Units

Comments
SLD and CLK Active

lee(P)

Power Down (Standby)

4

mA

lee (I)

Idle Operating Current

8

mA

Receiver, SLD, OSC
Active

lee(N)

Normal Operating Current

20

mA

Everything is Active,
(Excluding (Current
for Output Loads)

A.C. Characteristics

vee =,5V ± 5%; Vss = OV; T A = O·C - 70·C; CLK = 3.84 MHz'

RECEIVER
Symbol

. Parameter

VRD
Z,R

Received Differential Mark Voltage
LR+, LR- Input Impedance

C'R

LR + , LR- InputCapacitance

Min
200

Typ.
60
30

14-234

Max
3000

Units
mV

Comments

kO
pF

Each Pin
Each Pin

IATC29C53

TRANSMITTER
Symbol

Parameter

Vxo

Transmit Differential Mark Voltage

Zox

LX + , LX - Output Impedance

Cox

Output Capacitance

RL

Resistive Load Between LX + , LX-

CL

Capacitive Load Between LX + , LX-

tLO

Load Time Constant

tMR

Transmit Mark Rise Time

to

Damping Time Constant

IXL

Source, Sink Current Limit

VXL

Voltage Limiting

TIMING
Symbol

Min
1780

Typ

Max
1980

Units

60
30
200

18
125

Parameter
Timing EXtraction Jitter ("5" Slave Mode)

PO

Total Phase Deviation LX with Respect to LR

Comments
200 0. < RL < 2.5 ko.

ko.

Each Pin

pF

Each Pin

0.
1500
0.5
400
1.5

J

mV

Min
-5
-7

pF
/Ls
ns

= 3000., CL = 1500 pF

Note 1

/Ls
mA
%

Typ

RL

Nominal Mark Voltage

Max
+5
+15

Units
%
%

Comments
1.4308.2.2
1.4308.2.3

NOTE:

1. Risetime is measured as 10% to 90% for space mark transitions and 90% to 0% and 0% to 90% for mark-to-mark
transitions with respect to final value.

14-235

intJ

iATC29C53

ClK

SCl

P3.P4-+__~____________J~__~____________~

r-~------------+--

/-TKS
SDIR
TKDV

SlDOUT
SlD1N

-----+i~======:lJ\C=====~

TSDV--

-TKDE

::::::>)o----------------------------~s

t

~S.t:=:LL

s-----
Oenver 80222
Tel: (303) 321·8086
TWX: 910·931-2289
CONNECTICUT
Inlel Corp
26 Mill Plain Road
Oanbury 06810
Tet: (203) 748-3130
TWX: 710·456·1199
fMC Corp
222 Summer Street
Siamford 06901
Tel: (203) 3n2934
FLORIDA
Inlel Corp
242 N, Westmonte Drive
Suile 105

~~II~m$61~) ~~r~~~~Bl2714
Intel Corp
6363 NW, 6th Way. Suite 100
Ft. Lauderdale 33309
Tel: (305) 771·0600
lWX: 510·956·9407

Intel Corp
SUlle 2B Hollowbrook Park
15 Myers Corners Road
Wappinger Falls 12590
Tel (914) 297·6161
TWX: 510·248·0060

Inlel Corp.
8777 Purdue Road
Suile 125
Indianapolis 46268
Tel, (3171 875·0623

EI Segundo 90245
Tel: (213) 640·6040

fJ'3tn~t~e~~d~e~~InBrive

N,E

Corp

MARYLANO
Intel Corp'
7321 Parkway Drive South
SUite C
Hanover 21076
Tel: (301) 796·7500
TWX: 710·862·1944
Intel Corp
7833 Walker Drive
Greenbelt 20770
Tel. (301) 441·1020

Inlel Corp'
7322 s.w. Freeway
SUite 1490
Houston 77074

i~:x: (7J~6.8~~~2~~~6

Intel Corp,'
211 White Spruce Boulevard
Rochester 14623
Tel: (716) 424·1050
TWX: 510·253·7391

UTAH
Intel Corp
5201 Green Sireet
SUite 290
Murray 84123
Tel: (801) 263·8051

Intel Corp
5700 Executive Center Olive
SUite 213
Charlolle 28212
Tel: (704) 568·8966

LOUISIANA

Intel Corp."
12300 Ford Road
Suile 380
Dallas 75234
Tel: (214) 241·8087
TWX: 910·860·5617

Industrial Dlg,tal Systems Corp
5925 Sovereign
SUile 101
Houston 77036
Tel' (713)988-9421

NORTH CAROLINA

KANSAS

~ne~ys15014) O~~I~~16~~slems

Intel Corp
313 E Anderson Lane
SUIte 314
Auslln 78752
Tel: (512) 454·3628

VIRGINIA
Inlel Corp.
1603 Santa, Rosa Road
Suile 109
Richmond 23288
Tel. (804) 282·5668

Inlel Corp
2700 Wycliff Road
SUite 102
Raleigh 27607
Tel' (919) 781·8022
OHIO

WASHINGTON

Inle~ Corp,"
6500 Poe Avenue
Dayton 45414
Tel: (513) 890·5350
TWX: 810-450·2528

Intel Corp
110 110lh Avenue N_E
SUite 510
Bellevue 98004
Tel: (206) 453-8086
TWX, 910·443-3002

Inlel Corp."

~~8§~lnc?~~~~~~d B~~~~~'ar~o
Cleveland 44122
Tet: (216) 464·2736
TWX: 810·427-9298

300

,Inlel Corp
408 N. Mullan Road
Suite 102
Spokane 99206
Tel. (509) 928·8086

MASSACHUSETTS

OKLAHOMA

WISCONSIN

Intel Corp,'
Westford Corp, Center
3 Carlisle Road
Wes!lord 01886
Tel: (617) 692·3222
TWX: 710·343·6333

Intel Corp
6801 N, Broadway
Suite 115
Oklahoma City 73116
Tel: (405) 848·8086

Intel Corp
450 N. Sunnyslope Road
Suite 130
Chancellory Park t
Brookfield 53005
Tel: (414) 784·8087

OREGON
MICHIGAN
Inlel Corp
7071 Orchard take Road
SUite 100
Wesl Bloomfield 48033
Tel: (313) 851·8096

Inlel Corp
10700 S W, Beaverton
Hillsdale Highway
Suile 22
Beaverlon 97005
Tel: (503) 641-8086
TWX_ 910-467·8741

MINNESOTA
Intel Corp
3500 W, 80th Sireet
SUite 360
Bloomington 55431
Tel: (612) 835·6722
TWX: 910·576·2867
MISSOURI
Inlel Corp
4203 Earth City Expressway
SUite 131
Earth City 63045
Tel: (314) 291·1990
NEW JERSEY
Inlel Corp.'
Parkway 109 Office Cenler
328 Newman Springs Road
Red Bank 07701
Tel: (201) 747·2233

CANADA
BRITISH COLUMBIA
Intel Semiconduclor of Canada
301·2245 W. Broadway
Vancouver V6K 2E4
Tel' (604) 738·6522

PENNSYLVANIA

ONTARIO

Intel Corp
1513 Cedar Clln DfI~e
Camphlll 17011
Tel: (717) 737·5035

Inlel Semicondllctor 01 Canada
2650 Queensview Drive
Sllile 250
Ollawa K2B 8H6
Tel: (613) 829·9714
TELEX' 053·4115

Intel Corp,'
455 Pennsylvania Avenue
Fori Washington 19034
Tel: (215) 641·1000
TWX: 510·661·2077
Inlel Corp,'
400 Penn Cenler Boulevard
Suile 610
Pittsburgh 15235
Tel: (412) 823·4970
Q,E.D. Electronics
139 Terwood Road
Box T
Willow Grove 19090
Tel: (215) 657·5600

ltd

ltd

Intel Semlconduclor of Canada, Lid
190 Altwell Olive
Suile 500
Rexdale M9W 6H8
Tel, (416) 675·2105
TELEX: 06983574
QUEBEC
Inlel Semiconduclor 01 Canada. Ltd
620 SI. Jean Blvd
POinte Claire H9R 3K3
Tel: (514) 694·9130
TWX, 514·694-9134

"Field Applicalion Localion

intJ
DOMESTIC DISTRIBUTORS
ALABAMA

CALIFORNIA (Cant'd)

KANSAS

Arrow ElectrontCS, Inc.
lOIS Henderson Road
Huntsville 35805
Tel: (205) 837·6955
tHamlllon/Avnel Electronics
4812 Commercial Drive N.W.

Hunlsville 35B05
Tel: (205) 837·7210
TWX: 810-126-2162
tPioneer/TechnologlBS Group Inc.

~~~rsv~~1\13~~~5 Square
Tel: (205) B37·9300
TWX: 810-726-2197
ARIZONA

!~~m~~n~~d~s~n E~~~~niCS
Tempe 85281
Tel: (602) 231-5100

TWX: 910-950-0077
Kierullf Electronics
4134 E. Wood Street
Phoenix 85040
Tet: (602) 437·0750

tHamlllon/Avnet Electronics
9219 QUlVera Road
Overland Park 6621!J

~:x:(9J~6.7~~~O~~~0

TWX: 910·595·2638
Klerulft Electronics
10824 Hopo Street
Cypress 90430
Tol: (114) 220·6300
Kierulfl Electronics, Inc.
1180 Murphy Avenue
San Jose 95131
Tel: (408) 947·3471
TWX: 910·379·6430
Kiorulft Electronics, Inc.
14101 Franklin Avenue
Tustin 92680
Tel: (114) 731·5711
TWX: 910-595·2599
tKierul1t Electronics, Inc.
5650 Jillson Street
Commerce 90040
Tet: (213) 725·0325
TWX: 910·580·3666

TWX: 910-951-1550

~J~o Dt~~~~°"st~~~up

Wyle Distribution Group
17855 N. Black. Canyon Highway
Phoenix 85023

Calabasas 91302
Tel: (818) 880·9000
TWX: 818·372·0232

tArrow Electronics, lne.
1001 N.W. 62nd Street
SUite 108
Flo Lauderdale 33309
Tel: (305) 776·7790
TWX: 510·955·9456

KENTUCKY
Hamlllon/Avntlt Electronics
1051 D Newlor. Park
LeXIngton 40511

tArrow Eleclromcs. Inc.
60 Woodlake Drive W., Bldg. B
Palm Bay 32905
Tel: (305) 725-1480
TWX: 610·959-6337
tHamilJon/Avnet Electronics
6801 N.W. 15th Way
Ft. lauderdale 33309
Tel: (305) 971·2900
TWX: 510·956·3097

MARYLAND
Arrow Electronics, Inc.
8300 Gultord Road tlH
Rivers Center
Columbia 21046
Tel: (301) 995·0003
TWX: 710·236·9005
tHamilton/Avnel Electronics
6822 Oak Hall Lane
Columbia 21045
Tel: (301) 995·3500
TWX: 710·862·1861

f~o~;a 1~~~~t~IOg~riv~orporahon
Gaithersburg 20877
Tel: (301) 948·4350
TWX: 710·828·9702

Tel: (602) 866-2888

CAUFORNIA
Arrow Electronics, Inc.
19748 DearbOl'n Street
Chatsworth 91311
TeJ. (818) 701-7500

TWX: 910-493·2086
Arrow Electronics
9511 Ridgehaven Court
San Diego 92123
Tel: (619) 565·4800
TlX: 888064
tArrow Electronics, Inc.
521 Weddell Dnve
Sunnyvale 94086
Tel: (408) 745-6600
TWX: 910·339·9371
Arrow Electronics, Inc.
2961 Dow Avenue
Tustin 92680

t~:X:(7Jt~5~~~2~~~2
tAvnet Electronics
350 McCormick Avenue
Costa Mesa 92626
Tel: (714) 754-6051
TWX: 910-595·1928
Hamilton/Avnel Etectroni~'
1175 Bordeaux Drive
Sunnyvale 94086

~X:(4~~3~~9~~go
tHamillon/A:,net Electronics

tWyle Distribution Group
17872 Cowan Avenue

Irvine 92714

tPloneer Eleclronics
221 N. Lake Boulevard
Suile .4t2
Alta Monte Springs 32701
Tel: (305) 834·9090
TWX: 810·853·0284

IfASSACHUSEnI
tArrow Electronics. Inc.
I Arrow Drive
Woburn 01801

Tel: (714) 843·9953
TWX: 910·595·1572

t~:x: (6ii6.3~~~6~'lg

rrr~~e s~~trig~~f:r g~~~
Rancho Cordova 95670
Tel' (916) 638·5282

~~2!e g~~~~t~~~ %'r~
~:r (~~~~o 5~~~~;71

tHamillon/Avnel Electronics
IOD Centennial Drive

~:r~~r7) °19362~3701

GEORGIA

TWX: 910·335·1590

tArrow Electronics, Inc
3155 Northwoods Parkway. Suite A
Norcross 30071
Tel: (404) 449·8252
TWX: 810-766-0439

tWyle Oislrlbullon Group
3000 Bowers Avenue
Santa Clara 95051
Tel: (408) 727·2500
TWX: 910·338·0296

Hamilton/Avnet Electronics
5825 D. Peachlree Corners
Norcross 30092
Tel: (404) 447·7500
TWX: 810-766·0432

Wyle Mihlary
17810 Teller Avenue
Irvine 92750
Tel: (714) 851·9958
TWX: 310·371·9127

Pioneer Electronics
58358 Peachlree Corners E
Norcross 30092
Norcross 30092
Tel: (404) 448·1711
TWX: 810·766·4515

Wyle Systems
7382 Lampson Avenue
Garden Grove 92641
Tel: (714) 851·9953
TWX: 910·595·2642

twX: 710·393·0382
Pioneer Northeast Electronics
44 Hanwell Avenue
Lexington 02173

:reJx:(6~i6.3~~~6'lIOf

MICHIGAN
Arrow Electronics, Inc.
755 Pltoenix Drive
Ann Arbor 48104

~:(3J~6'2~~I.tglg

ILLINOIS
tArrow Electronics, Inc.
. Sireel

COLORADO
tHamillon/Avnel Electronics
20501 Plummer Street
Chatsworth 913tt
Tel: (818) 700·6271
TWX: 910-494-2207
tHamillon/Avnel Electronics
4103 Norlhgate Boulevard
Sacramento 95834
Tel: (916) 920·3150
Hamil10n/Avnel Electronics
3002 G Street
Ontario 91311
Tel: (714) 989·9411
Hamitlon/Avnet Electroni~
19515 So. Vermont Avenue
Torranco 90502
Tel: (213) 615·3909
TWX: 910·349·6263
Hamilton Electro Sales
9650 De Soto Avenue
Chatsworth 91311
Tel: (818) 700·6500

Arrow EleCtrOniCs, Inc.
1390 5. Potomac Street
Suite 136
Aurora 80012
Tel: (303) 696·1111
tWyle Distribution Group
451 E. 1241h Avenue
Thornlol1 80241
Tel: (303) 457·9953
TWX: 910·936·0770
Avnel Electroni~
rcltard Road

Hamilton Electro Sales
1361 B West 190th Street
Gardena 90248
Tel: (213) 558·2131

tPioneer Electronics
13485 Stamford
livonia 48150
Tel: (313) 525·1800
twX: 810·242·3271

MINNESOTA

INDIANA.

80111
740·1017
TWX: 910·935·0787

CONNECTICUT

,

tArrow Electronics, Inc.

~~~I::~Ar~3~st7il:lct~~r~s
Commerce Drive
Danbury 06810

TWX: 910·340·6364

tHamillon/Avnet Electronics
1130 Thorndale Avenue
Bensenville 60106
Tel: (312) 860·7780
TWX: 910·227·0060

~~:(2?,3J.4~~~9~~~0

tPioneer Northeast Electronics
112 Main Street
Norwalk 06851

Hamilton/Avnel Electronics
485 Gradle Drive
Carmel 46032
Tel: (317) 844·9333
TWX: 810·260·3966
tPloneer Electronics
6408 C8stleplace Drive
Indianapolis 46250
Tel: (317) 849·7300
TWX: 810·260·1794

tPioneer Electronics
10203 Bren Road East
Minnetonka 55343
Tel: (612) 935·5444
TWX: 910·576·2738

MISSOURI
tArrow Electronics, Inc.
2380 Schuetz
Sl. Louis 63141
Tel: (314) 567·6888
TWX: 910·764·0882

~~:(2?m.4~~:31~~5
tMlcrocomputer System Technical Demonstrator Centers

inter
DOMESTIC DISTRIBUTORS
MISSOURI (COnl'd)

NEW YORK (Cont'cf)

PENNSYLVANIA

WISCONSIN (Cont'd)

tHamilton/Avnel Eleclronics
13743 Shoreline Court

~~T~a~6~~e~~rksa~r~ve

TWX: 910-762-0684

P.O. Box 271
Por1 Washinglon 11050
Tel: (516) 621-6200
TWX: 510-223-0846

tArrow Electronics, Inc.
650 Seco Road
Monroeville 15146
Tel: (412) 856-7000

tHamiiton/Avnet Eleclronics
2975 Moorland Road
New Berlin 53151
Tet. (414) 784·4510
TWX: 910-262-1182

f:rn (3~~~ fg~~~oo

NEW HAMPSHIRE

tPioneer Northeast Electronics
~~al Vf~~~o Parkway East

tArrow Electronics, ,Inc.
a Perlmeler Road
Manchester 03103

Tel: (607) 748·8211
TWX: 510-252-0893

Tel: (603) 668-6968
TWX: 710·220-1684

Hamilton/Avnet ElectronICS
444 E. Industrial Drive
Manchester 03104

tPioneer Norlheast Electronics
60 Crossway Park West

~r~~t~' 9L~,~j76~and

11797

PIoneer Electronics
259 Kappa Drive
Plllsburgh 15238
Tel: (412) 782-2300
TWX: 710-795-3122

TWX: 510-221-2184

lEXAS

Marlton 08053

Pioneer Nor1heast Electronics
840 Fairpor1 Park
Fairpor1 14450
Tet: (716) 381·7070
TWX: 510·253·7001

Carrollton 75006
Tel: (214) 380-6464
TWX: 910-860·5377

TWX: 710-897-0829

NORTH CAROLINA

tArrow Eleclronics, Inc.
2 Industrial Road

Tel: (201, 575-5300
TWX: 710·998·2206

Zentronics

1~2'8wC;:=~~~' rJ;;;e

~gbo Nl~1hI Avenue N.E.
~:II:ga(70312~7g~'~21

fArrow Electronics. Inc.
10899 Kinghurst
SUite 100
Houston 77099

Hamllton/Avnet Electronics
105-2550 Boundry Road
Burmalay V5M 313
Tel: (604) 272-4242

BFHTISH COWMEIIA

Bldg. 36

~~1~(60~:" 4~~~~1O

TWX: 710-940-0262

tHamiiton/Avnel Electronics

10 InduSlriaJ
Falrileld 07006
Tel: (201) 575-3390
TWX: 710-734-4388
tPioneer Northeast Electronics

45 Route 46
Pinebtook 07058

Pioneer Electronics
9801 A-Southern Pme Boulevard
Charlotte 28210
Tel: (704) 524-8168
TWX: 810·621·0366

OHIO
Arrow Electronics, Inc.
7620 McEwen Road
Centerville 45459
Tel: (513) 435-5563
TWX: 810-459-1611

Tel: (201) 575·3510

TWX: 710-734-4382

l~r A~~~:~~ ~Ies

tArrow 8ectronics. IfIC.
6238 Cochran Road
Solon 44139
Tel: (216) 248-3990
TWX: 810-427-9409

Fairfield 01006
Tel: (201) 227-5552

NEW MEXICO
Alliance 8ectronics Inc.
11030 Cochiti S.Eo
Albuquerque 87123
Tel: (505) 292-3360
TWX: 910-989-1151

tHamllton/Avnet Electronics
954 Senate Drive
DaylOn 45459

~:(5Jr6.4~~2~~\0

Townline Road

tPioneer ElectroniCs
4800 E. 131st Street
Cleveland 44105
Tel (216) 587-3600
TWX: 810-422-2211

Arrow Electronics, Inc.
20 Oser Avenue
Hauppauge 11788
Tel: (516) 231-1000
TWX: 510·227-6623
Hamllton/Avnet Electronics
333 Metro Park
Rochester 14623

~:(7J~~2~~~5~j3g

Hamiiton/Mnel Electronics
103 Twin Oaks Drive
Syracuse 13206
Tel: (315) 437-2641
iWX: 710-541·1560
tHamiltoo/Avnet Electronics
933 Motor Parkway

ONTARIO
tHamillon/Avnet EleCtronics
2111 W. Walnut Hill lane
Irving 75062
Tel: (214) 659·4.100
TWX: 910-860·5929

Arrow Electronics Inc.
24 Marlin Ross Avenue
Downsview M3J 2K9
Tel: (416) 661·0220
TELEX: 06-218213

tHamillon/Avnel Eleclronics
8750 Wesl Park
Hosulon 77063
Tel: (713) 780-1711
TWX: 910-881·5523

Arrow Electronics Inc.
148 Colonnade Road
Napean K2E 7J5
Tel. (613) 226--6903

Pioneer Electronics
9901 Burnet Road
Austin 78758
Tet: (512) 835·4000
TWX: 910-874-1323

tHamilton/Avnet Electronics
6845 Rexwood Road
Unils G & H
Mlssissauga L4V lR2
Tel: (416) 677-7432
TWX: 610-492-8867

Pioneer Elec1ronics

Beclronics
Road South

15
·1700

1

Unit

Sail Lake City 84104
Tel: (801) 974-9953

tAlmac Electronics Corporation
1885 N.W. 1691h Place
Beaver10n 97006
Tel: 1503) 629-8090
TWX: 910-467·8746
Hamillon/Avnet ElectroniCS
6024 SW. Jean Road
Bldg. C, Suite 10
Lake Oswego 97034
Tel: (503) 635-7848
TWX: 910·455·8179

~O~~ib~~O~ ~~~~~

Zentronics
564/10 Weber Street North
Waterloo N2L 5C6
Tel: (519) 884-5700

tHamilton/Avnet Eteclronics
1585 West 2100 South

~~ ~~~~~u~~~o G~~ft.

OFIEGON

rt:

~: (7Jf6.8~~~1~g~S
UTAH

~:I:t ::~,i ~~~'2~~~9

Arrow Electronics, Inc.
4719 S. Memorial Drive
Tulsa 74145
i!'el: (9ta) 665-7100

Hillsboro 97124
Tel: (503) 640·6000
TWX: 910-460-2203

tZentronics
8 Tilbury Cour1
Brampton L6T 3T4
Tel: (416) 451-9600
TWX: 06·976-78

TWX: 910·925-4018

OKLAHOMA
Arrow Electronics, Inc.
7705 MaHage Drive
liverpool 13088
Tel: (315) 652-1000
TWX; 710·545-0230

Zentronics
590 Berry Street
Winnipeg R3H OSI
Tel: (204) 775-8661

Pioneer Electronics
5853 Poinl West Drive
Houston 77036

tPioneer Electronics
4433 Interpolnt Boulevard
Dayton 45424
Tel: (513) 236-9900
TWX: 810-459-1622

tArrow Electronics. Inc.
25 Hub Drive
Melville 11747
Tel: (St6) 694-6800
TWX: 510·224-6126

......ITO. .

b~I~~ 9~2~4a Road
Tet: (214) 386-7300
TWX: 910-850-5563

Hamiiton'/Avnet Electronics
2524 Baylor Drive SE
Albuquerque 87106
Tel: (50S) 765-1500
TWX: 910-989-0614

NEW YORK

Zentronics
108-11400 Bridgeport Road
Richmond V6X 1T2
Tel: (604) 273-5575
TWX: 04·5077-89

Arrrm Electronics. Inc.
10125 Metropolitan
Austin 78758
Tel: (512) 835·4180
TWX: 910·&74·1348

tHamillon/Avnel Electronics
1 Keystone Avenue

~~~pr5~~e

¥:I~a(70312~3~2586

TWX: 03-827-642

~:X: (7J~6_8~~~4~~~0

Fairfield 07006

21r:00
TWX: .510-224-6166

Hamilton/Avnel Electronics
2616 21st Street N.E.

~:X: (2J~6:6~~~6~~~0

Tel: (603) 624·9400

Tel: (609) 596-8000

ALBERTA

tPioneer Eleclronics
261 Gibraller Road
Horsham 19044

NEW' JERSEY
tArrow Electronics, Inc.
6000 Uncoln East

CANADA

Parkway

B

Zentronics
155 Colonnade Road
Unit 17
Nepean K2E 7Kl
Tel: (613) 225-8840
TWX: 06-976-78

WASHINGTON

QUEBEC

tAlmac Electronics Corporation
14360 S.E. Eastgate Way
Bellevue 98007
Tel: (206) 643-9992
TWX: 910-444-2067

Arrow Eteclronics Inc.
4050 Jean Talon Quest
Montreal H4P 1Wl
Tel: (514) 735-5511
TELEX: 05·25596

Arrow Electronics, Inc.
14320 N.E. 21st Street
Bellevue 98007
Tel: (206) 643-4800
TWX: 910-444·2017

Arrow 8ectronics Inc.
909 Charest Blvd.
Quebec 61N 269
Tel: (418) 687-4231
TLX: 05-13388

Hamilton/Avnet Eleclronics
14212 N.E. 21st Street
Bellevue 98005
Tel: (206) 453-5874
TWX: 910-443-2469

Hamilton/Avnet Electronics
2795 Rue Halpern
SI. Laurent H4S IPS
Tel: (514) 335-1000
TWX: 6tO-421-3731

WISCONSIN

lentronlcs
505 Locke Slree1
S1. laurent H4T lX7
Tet: (514) 735-5361
TWX: 05-827-535
.

tArrow Electronics, Inc.
430 W. Rausson Avenue
Oakcreek 53154
Tel: (414) 764-6600
TWX: 910-262-1193

tMicrocomputer SYSIem Technicat Demonstrator Centers

EUROPEAN SALES OFFICES
BELGIUM

FRANCE ICont'd)

ISRAEL

SPAIN

Intel Corporation SA
Parc'Seny
Rue du Moulin a Papier 51
BOlte 1
B·1160 Brussels
Tel: (02)661 07 11
TELEX: 24814

Inlel Corporation, S.A.R.L.
Immeublo BBC
4 Quai des Etroits
69005 Lyon
Tel: (7) 842 40 89
TELEX: 305153

Inlel Semiconductors LId."
Alidim Induslrial Park
Neve Sharet
OVOla Hanevia
Bldg. No. 13, 4th Floor
P.O. Box 43202
Tel Aviv 61430
Tel: 3·491099/8
Telex: 371215

Intel Iberia
Calle Zurbaran
28·1·IZQDA
28010 Madrid
Tel: (34) 1410 40 04
TELEX: 46880

WEST GERMANY

DENMARK
Intal Denmark AlS'
Glanlevej 61 • 3rd Floor
DK·2400 Copenhagen
Tel. (01) 19 80 '33
TELEX: 19567

FINLAND

Inlel Semiconductor GmbH"
Seidlstrasse 27
D·8000 Munchen 2
Tel: (89) 53891
TELEX: 05·23177 INTL D
Intel Semiconductor GmbH"
Mainzerstrasse 75
0·6200 Wiesbadan 1

t~tE~~I~'lula~888IJi'w

Intel Finland OY
Ruosllanlie 2
000390 Helsinki
Tel: (0) 544 644
TELEX: 123 332

FRANCE
Intel Paris
1 Rue Edison, BP 303
78054 Sainl·Quentin en Yvelines
Tel: (33) 1 30 64 60 00
TELEX: 69901677

D

Intel Semiconductor GmbH
8ruckstrasse 61
7012 Fallbach
Stuttgart
Tel: (711) 58 00 82
TELEX: 7254826 INTS D
Intel Semiconductor GmbH"
Hohenzollernstrasse 5"
3000 Hannover 1
Tel: (511) 34 40 81
TELEX: 923625 INTH 0

ITALY
Intel Corporation lIalia Spa'
MllanoliOli, Palazzo E
20094 Assago (Milano)
Tel: (02) 824 40 71
TELEX: 315183 INTMIL

NETHERLANDS
Intel Semiconductor Nederland BY'
Alexanderpoort Building
Marten Meeswcg 93
3068 Rollerdam
Tel: (10) 21 23 77
TELEX: 22283

NORWAY
Intel Norway AIS
P.O, Box 92
Hvamveien 4
N·2013
Sklellen
Tel: (2) 742 420
TELEX: 1801B

SWEDEN
Intel Sweden A.B,"
Da/vagen 24
5·171 36 Soilla
Tel: 817340100
TELEX: 12261

SWITZERLAND
Intel Semiconductor A.G."
Talackerslrasse 17
~~.~o~~alt:~i~~ postlach
Tel: (01) 829 29 77
TELEX: 57989 ICH CH

UNITED KINGDOM
Inlel Corporation (U.K.) Lid."
Pipers Way
Swindon, Wiltshire SN3 IRJ
Tel: (793) 696 000
TELEX: 444447 INT SWN

'FieldApplicallonLocalion

EUROPEAN DIST.RIBUTORS/REPRESENTATIVES
AUSTRIA

FRANCE (Cont'eI)

ISRAEL

SWEDEN

Bachar Erektronische Geraete GmbH
Rolenmuehlgasse 26
A 1120 Wien
Tel: (222) 83 56 46
TELEX: 11532 BASAT A

Tekelec Airlronic

Eastronics Ltd.
11 ROlanis Street
P.O. Box 39300
Tel Aviv 61390
Tel: (3) 47 51 51
TELEX: 33638

Nordisk Electromk AB

W. Moor GmbH

~~~;;~n~~snse

1/1/1

Tel: 222·85 86 46

BELGIUM
tnelco Belgium SA
Ave. des Croix de Guerre 94
81120 Brussels
Tel: (021) 216 01 60
TELEX: 25441

DENMARK

~~~ ~:rleBr~~:~

B.P.
F·9231O Sevres
Tel: (1) 534 75 35
TELEX: 204552

WEST GERMANY

ITALY

SWITZERLAND

Computer 2000
Garmischer Strasse 4·6
0·8000 Munchen 2
Tel: (089) 519·96·0
TELEX: 5214562

Electra 3S S.P.A.
Viale Elvezla, lB
I 20154 Milano
Tel: (2) 34 97 51
TELEX: 332332

Industrade AG
Hertistrasse 31
CH·8304 Wallisellen
Tet: (01) 830 50 40
TELEX: 56788 INDEL CH

Electronic 2000 Verlriebs A.G.

Inlesl
Milanotion Pat. E/5
'·20090 Assago
Milano
Tel: (2) 82470
TELEX: 311351

UNITED KINGDOM

g~~8OUbM~~~h 1~2
Tel: (89) 42 00 10
TELEX: 522561 EEC 0

iTT MultiKomponent AIS
Naverland 29
DK·2600 Gloskrup
Tel: (02) 45 66 45
TX: 33355

FINLAND
Oy Fintronic AB
Melkonkalu 24 A
SF·00210 Helsinki 21
Tel: (0) 692 60 22
TELEX: 124 224 Flron SF

FRANCE
Ganerim
l.1. de Courtaboeul
Avenue de la Baltique
F·91943 Les Ulis Cedex·B.P.88
Tel: (1) 907 78 78
TELEX: F691700

~~~mrvcn::' de

Jean·Jaures
F·94600 Choisy·Le·Roi
Tel: (I) 853 12 00
TELEX: 260 967

Melrologie
La Tour d' Asnieres
4, Avenue Laurent Gely
F·92606·Asnieres
Tel: (1) 790 62 40
TELEX: 611·448

~:4~'Ortan 1
5·171 27 Solna
Tet: (8) 734 97 70
TELEX: 10547

By tech LId.
Unit 57
London Road
Early, Reading
Berkshire RJ 12 lW
Tel: (0734) 61031
TELEX: 848215

NETHERLANDS
Koning & Hartman

~~.ers;~

CES Computer Eleclronics Systems
GmbH
Gutenbergstrasse 4
0·2359 Henstedl·Ulzburg
Tel: (04193) 4026
TELEX: 2180260
Metrologie GmbH
Hansastrasse 15
0·8000 Munich 21
Tel: (89) 57 30 84
TELEX: 52131B9
.Proeleclron Vertriebs GmbH
Max Planck Sirasse 1·3
0·6072 Dreieich
Tel: (6103) 33564
TELEX: 417983

ig220

2544 EN's Gravenhage
Tel: 31 (70) 210.101
TELEX: 3152B

NORWAY
Nordisk Elektronic (Norge) AIS
Postoflice Box 122
Smedsvingen 4
1364 Hvalslad
Tel: (2) 846 210
TELEX: 17546

'. PORTUGAL

IRELAND

Oitram
Componentes E Electronica LDA
Av. Miguel Bombarda, 133
P·1000 Llsboa
Tel: (19) 545 313
TELEX: 14182 Brieks·P

MiCfO Marketing
Glenageary OffICe Park

SPAIN

Tel: (1) 85 62 88
TELEX: 31584

ITT SESA
Miguel Angel 21, 6 Piso
Madrid 10
Tel: (34) 14 1954 00
TELEX: 27461

~~na~~~

£~~~aEsB:n~asd
28020 Madrid
Tel: 455 36 86
TELEX: 42148

5

Comway M!crosyslems Ltd.
Market Street
Bracknell
Berkshire RJ 12 IQP
Tel: (344) 55333
TELEX: 847201
Jermyn Induslfles Vest.y Estate
Oxford Road
Seven Oaks
Kent TN 14 5EU
Tel: (0732) 450144
TELEX: 95142
M.E.D.L.
East Lane Road
North Wembley
Middlesex HA9 7PP
Tel: (190) 49307
TELEX: 28817
Rapid Recall, Ltd.
Rapid House/Oenmarl< SI
High Wycombe
Bucks HPll 2EA
Tel: (494) 26 271
TELEX: 837931

YUGOSLAVIA
H. R. Microelectronics Enterprises
P.O. Box 5604
San Jose, California 95150
Tel: 408/978·BOOO
TELEX: 278·559

inter

/

INTERNATIONAL SALES OFFICES
AUSTRALIA
Intel Australia Ply

L1d.·

b~6~lin~O/~dgss)
North Sydney NSW, 2060
(Shipping Address)
Spectrum Building
200 Pacific Highway

Level 6
Crows Nesl, NSW, 2065
Tel: 011-61-2-957-2744
TELEX: 790-20097

FAX: 011-61-2-957-2744

JAPAN (Cant'd)

KOREA

Inlel Japan KK
5·6 Takodai, Toyos~lo·machi

Intel Japan K K
Shinmaru Bldg
'·5·1 Marunouchi
Chiyoda·ku, Tokyo 100
Tel: 03·201-3621

Intel Semiconductor Asia Ltd.
Singsong Bldg. 8th Floor #906
25.4 YOIdo·Dong, Youngdeungpo-Ku
Seoul 150
Tel, 011·82-2·784-8186 01 8286
TELEX: K29312 INTELKO

Tsukuba-gun, Ibarakl-ken 300-26
Tel. 029747-8511

TELEX: 03656·160
Intel Japan KK."
Komeshin Bldg
2-1-15 Naka-machi
Atsugi, Kanagawa 243

Tel: 0462-23·3511
Intel Japan KKo
Oaiichi Mitsugi Bldg

,·8889 Fuchu-cho

CHINA
Intel PRe Corporalion

IS/F, Office t, Gllie Bldg
JI8n Guo Men Wat Avenue
Beijing, PRe

HONG KONG
Intel Semiconductor Ltd."
1701·3 Connaught Centre
1 Connaughl Road

Tel:

JAPAN

01'-8~2-5-215-311

TWX: 60410 ITlHK

Fuchu,shi. TokyO 183
Tel: 0423·60·7871
Intel Japan KX·
Bldg. Kumagaya
2·69 Hon·cho
Kumagaya. Saitama 360
Tel: 0485·24·6871
Intel Japan K.K."
Ryokuchi·Slation Bldg
2·4·1 Terauchi
Toyonaka. Osaka 560
Tel: 06·863·1091

Intel ,Japan K:K.·
Flower-Hili Shln·machi Easl Bldg.
1-23-9 Shinmachi
Setagaya·ku, Tokyo 154
Tel: 03-426·2231
Intet Japan K.K·
Mitsui-Seimei Musashi.Kosugi Bldg
915-20 Shinmaruko, Nakahara-ku
Kawasakl-Shl, Kanagawa 211
Tel. 044·733·7011
Inlel Japan K.K
Mishima Tokyo-Kaijo Bldg

SINGAPORE
Intel Semiconductor Ud
101 Thomson Road
21·06 Goldhlll Square
Singapore 1130
Tel: 011-65-250-7811
TWX: RS 39921

TAIWAN
Intel Semiconductor Ltd
Rm, 808. Min Chi Bldg.
746 Min Sheng East Road
Taipei

I·, Shibahon·cho

Mishima·shi
Shizuoka¥en 411
Tel: 0559·72-4121

·Field Application location

INTERNATIONAL DISTRIBUTORS/REPRESENTATIVES
ARGEtmNA

CHINA (Cont'd)

JAPAN (Cont'd)

PAKISTAN

VLC S.R l Barlalome Mitre 1711
3 Piso
1037 Buenos Aires
Tel: 011·54·1·49·2092
Telex: 17575 EDARG-AR

Schmidt & Co, Ltd
18/F. Great Eagle Centre
Wanchai
Hong Kong
Tel: 011-852-5-822,0222
TWX: 74766 SCHMC HK

Ryoyo Electric Corporalion
Shuwa Sakurabashi Bldg
4·5·4 Hatchobori
Chuo-Ku, Tokyo 104
Tel: (03) 555·4811

Computer Applications Ltd
7D Gizri Boulevard
Defence
Karachi-46
Tel: 011·92·21-530-306
TELEX: 24434 GAFAR PK

Agent'
Soimex International Corporation
15 Park Row, Room #1730
New York. New York 10038
Tel: (212) 406·3052

AUSTRALIA
Total Electronics
(Mailing Address)
Private Bag 250
8urwood, Victoria 3125
(Shipping Address)
9 Harker Street
Burwood
VictOria 3125
Tel: 011·61·3-288-4044
TELEX: AA 31261
Total Electronics
P.O. Box 139
Arlamon. N.SW. 2064
Tel: 011-61·02-438-1855
TELEX: 26297

BRAZIL
Elebra Microelectronica SI A
A. Florida. 1821-8 ander
04571 • Sao Paulo-SP
Tel: 011·55-11·533-9977
TELEX' 1125957

CHILE
DIN
(Mailing Address)
Av. VIC, MacKenna 204
Casilla 6055
Santiago
Tel: 011·56-2-277-564
TELEX: 352-0003

(Shipping Address)
A102 Greenville Center
3801 Kennett Pike
Wilmington, Delaware 19807

CHINA
Novel PreCISion Machinery Co., Ltd
Flat 0 20 Kingsford Ind. Bldg
~~~~e ~ig6 Kwai Hei Street NT
Tel: 011·852·5-223222
TWX. 39114 JINMI HK

HONG KONG
Schmidt 8. Co, Ltd
18/F. Great Eagle Centre
Wanchai
Tel: 011·852-5-822-0222
TWX: 74766 SCHMC HK

INDIA
Micronic Devices
65 Arun Complex
DVGRoad
Basavan Gudi
Bangalore 560 0(l4
Tel: 011-91·S12-600-631
TELEX: 011·5947 MDEV
Micronic Devices
104/109C Nirmal Industrial Estate
Sion (E)
Bombay 400 022
Tel, 011·91-22-48·61-70
TELEX: 011-71447 MDEV IN
Micronic Devices
R·694 New Rajlnder Nager
New Deihl 110 (l60
Ramlak International, Inc (Agenl)
465 S, Mathilda Avenue
Suite 3(l2
Sunny\'ale, CA 94086
Tel: (408) 733-8767

Tokyo Electron Ltd
Shinjuku Nomura Bldg.
1·26·2 Nishl·Shln)uku
ShinJuku·Ku, Tokyo 160
Tel. (03) 343-4411
TELEX: 232-2220 LABTEL

KOREA
J·TEK Corporation
2nd Floor, Government PensIOn Bldg
24·3 Yoido-Dong
Youngdungpo-Ku
Seoul 150
Tel: 011-82·2-782-8039
TELEX: KODIGIT K25299
Karam Digital USA (Agent)
14066 cast Firestone Boulevard
Sante Fe Springs, CA 90670
Tel: (714) 739-2204
TELEX: 194715 KORAM DIGIT LSA
Samsung
231d FI, Dong Bang Bldg
1502·KA Taepyung-RU
Chung.Ku·
Seoul
Tel: 777-78
TELEX 27970 KORSST K

~.O& &0?~r8'60tion
San Jose 95160-0160

DICOPEL S.A
Tochtli 368 Fracc Ind. San
Azcapotzalco
C.p, 02760-Mexico, D,F
Tel. 90115255613211
TELEX: 1773790 QICOME

Asahi Electronics Co Ltd
KMM Bldg, Room 407
2·14-1 Asano, Kokuraklla-Ku
Kilo.kyushu City 802
Tel' (093) 511·6471
TELEX: AECKY 7t26-16
C, Itoh Micronics Corp.
OS 85 Bldg, 2·6·5 Suda-Cho
Kanda Chiyoda-Ku, Tokyo 101
Tel: (03) 256-2211
TELEX: (03) 252·3774

(Agent)

SINGAPORE
General Engineers Corporation Ply

Ltd
203 Henderson Road
1102 Henderson Indus!rial Park 0315
Tel: 011065-27t.3163
TELEX, RS23987 GENEACO

SOUTH AFRICA
Electronic Building Elements, Pty, Ltd
(Mailing Address)
P,O Bo)( 4609
Pretoria 0001
Tel: 011-27-12-469921
TELEX: 3-22786 SA
(Shipping Address)
Pine Square, 181h Street
Hazelwood Pretoria

Tristar Semiconductor (Agent)
5150 Great America Parkway
Santa Ctara, CA 95050
(408) 980-1630

MEXICO

JAPAN

Hom:on Training Co" Inc
1 lalayene Center
1120 20th Street NW
Suite 530
Washington, D,C. 20036
Tel' (202) 887-1900
TWX: 248890 HORN

TAIWAN
Mitae Corporation
No. 585 Ming Sheng E
Taipei
Tel: 011-96-2-501-8231
TELEX: 11942 TAIALJTO
Antonio

Road

Meetel International. Ine (Agenl)
3385 Viso Court
Santa Clara, CA 95050
Tel: (408) 988·4513
TWK 910-338·2201
FAX, 408-980-9742

NEW ZEALAND
Northrup Instruments 8. Systems Ltd
459 Kyber Pass Road
p.o, Box 9464, Newmarket
Auckland t
Tel' 011-64-9·501-219, 501-801, 587-

037

YUGOSLAVIA
H, R Microelectronics Enterprises
P.O, Bo)( 5604
San Jose, Calilornia 95150
Tel: (408) 978-8000
TELEX: 278-559

TELEX: NZ21570 THERMAL
Northrup Instrumenls & Systems Ltd
P.o Box 2406
Wellington 856658
TELEX: NZ3380
·Field Application Location



File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
Producer                        : Adobe Acrobat 9.2 Paper Capture Plug-in
Modify Date                     : 2009:12:18 02:25:07-08:00
Create Date                     : 2009:12:18 02:25:07-08:00
Metadata Date                   : 2009:12:18 02:25:07-08:00
Format                          : application/pdf
Document ID                     : uuid:b6b6621f-0d6a-49ae-8893-470ecb097000
Instance ID                     : uuid:c8123ef2-9f8a-45b7-9f1e-5e3185113f2c
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 1395