1986_Microsystem_Components_Handbook_Peripherals_Volume_2 1986 Microsystem Components Handbook Peripherals Volume 2

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MICROSYSTEM

COMPONENTS HANDBOOK

1986

About Our Cover:
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Table of Contents
NUMERIC INDEX .......................................................................

vi

CHAPTER 1
OVERVIEW
Introduction ......................................... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1

CHAPTER 2
8080, 8085 MICROPROCESSORS
DATA SHEETS
8080A/8080A-1/8080A-2 8-Bit N-Channel Microprocessor .............................
2-1
8085AH/8085AH-2/8085AH-1 8-Bit HMOS Microprocessor ............................ 2-10
8155H/8156H/8155H-2/8156H-2 2048-Bit Static HMOS RAM with I/O Ports and Timer .... 2-26
8185/8185-2 1024 x 8-Bit Static RAM for MCS®-85 .................................... 2-38
8224 Clock Generator and Driver for 8080A CPU ..................................... 2-43
8228/8238 System Controller and Bus Driver for 8080A CPU ........................... 2-48
8237A/8237A-4/8237A-5 High Performance Programmable DMA Controller............. 2-52
82C37A-5 CHMOS High Performance Programmable DMA Controller................ .. 2-67
8257/8257-5 Programmable DMA Controller .......................................... 2-78
8259A/8259A-2/8259A-8 Programmable Interrupt Controller......................... .. 2-95
82C59A-2 CHMOS Programmable Interrupt Controller........................... ... .. 2-113
8755A/8755A-2 16, 384-Bit EPROM with I/O .......................................... 2-133
APPLICATION NOTES
AP-59 Using the 8259A Programmable Interrupt Controller ............................ 2-144

CHAPTER 3
8086, 8088, 80186, 80188 MICROPROCESSCORS
DATA SHEETS
8086 16-Bit HMOS Microprocessor ..................................................
80C86/80C86-2 16-Bit CHMOS Microprocessor ......................................
80186 High Integration 16-Bit Microprocessor ........................................
iAPX 88/10 8-Bit HMOS Microprocessor .............................................
80C88/80C88-2 8-Bit CHMOS Microprocessor ........ : ..............................
80188 High Integration 8-Bit Microprocessor .........................................
8087/8087-2/8087-1 Numeric Data Coprocessor .......................................
8282/8283 Octal Latch .............................................................
8284A/8284A-1 Clock Generator and Driver for iAPX 86, 88 Processors .................
82C84A/82C84A-5 CHMOS Clock Generator and Driver for 80C86, 80C88 Processors ...
8286/8287 Octal Bus Transceiver ....................................................
8288 Bus Controller for iAPX 86, 88 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . ..
82C88 CHMOS Bus Controller for 80C86, 80C88 Processors ..........................
82188 Integrated Bus Controller for iAPX 86, 88,186,188 Processors ..•................
8289/8289-1 Bus Arbiter ............................................................
APPLICATION NOTES
AP-67 8086 System Design .........................................................
AP-113 Getting Started with the Numeric Data Processor ..............................
AP-186 Introduction to the 80186 ....................................................

3-1
3-25
3-52
3-106
3-133
3-162
3-218
3-241
3-246
3-254
3-263
3-268
3-275
3-283
3-299
3-310
3-373
3-435

CHAPTER 4
80286 MICROPROCESSORS
DATA SHEETS
iAPX 286/10 High Performance Microprocessor
4-1
with Memory Management and Protection .........................................
80287 80-Bit HMOS Numeric Processor Extension ............................. , .. '. . .. 4-56
82258 Advanced Direct Memory Access Coprocessor ................................. 4-82
82284 Clock Generator and Ready Interface for iAPX 286 Processors ................... 4-139
82288 Bus Controller for iAPX 286 Processors ........................................ 4-148
82289 Bus Arbiter for iAPX 286 Processor Family ..................................... 4-167

CHAPTER 5
80386 MICROPROCESSORS
DATA SHEETS
80386 High Performance Microprocessor with Integrated Memory Management.. . . . . . ..
82384 Clock Generator and Reset Interface for 80386 Processors ......................

iii

5-1
5-2

-VOLUME 2CHAPTER 6
MEMORY CONTROLLERS
DATA SHEETS
8202A Dynamic RAM Controller ................................................... .
8203 64K Dynamic RAM Controller ............................................•.....
8206/8206-2 Error Detection and Correction Unit ....•....................•...........
8207 Dual-Port Dynamic RAM Controller ....•.•..........•.•.•.•....................
8208'Dynamic RAM Controller ..... " ......................... , ..............•.......
82C08 CHMOS Dynamic RAM Controller ..•...............•.... ~ ..•.................
USERS M A N U A L '
,
Introduction ...................................................................... .
Programming the 8207 ............................................................ .
RAM Interface .. ; ........... '...................................................... .
Microprocessor Interfaces .............................................•...•........
8207 with ECC (8206) •............•................................................
Appendix .......•.. '.............................................................. "
APPLICATION NOTES
AP-97A Interfacing Dynamic RAM to iAPX 86/88 Using the 8202A & 8203 ....•..........
AP-141 8203/8206/2164A Memory Design ........................................... .
AP-167 Interfacing the 8207 Dynamic RAM Controller to the iAPX 186 ................. .
AP-168 Interfacing the 8207 Advanced Dynamic RAM Controller to the iAPX 286 .•......
ARTICLE REPRINTS
AR-364 FAE News 1/84 "8208 with 186" ............................................•.
AR-231 Dynamic RAM Controller Orchestrates Memory Systems ...................... .
SUPPORT PERIPHERALS
DATA SHEETS
8231 A Arithmetic Processing Unit ............................ : ..................... .
8253/8253-5Programmable Interval Tim,er ......•..............•..•..................
8254 Programmable Interval Timer ................................. : ............... '.
82C54 CHMOS Programmable Interval Timer .....................•...... , .......... .
8255A/8255A-5 Programmable Peripheral Interface ...•...............................
82C55A CHMOS Programmable Peripheral Interface .....•...........................
8256AH Multifunction Microproces,sor Support Controller ............................ .
8279/8279-5 Programmable Keyboard/Display Interface .............................. .
APPLICATION NOTES
AP-153 Designing with the 8256 .................................................... .
AP-183 8256AH Application Note
'
FLOPPY DISK CONTROLLERS
DATA SHEETS
8272A Single/Double Density Floppy Disk Controller ..................•..............
" APPLICATION NOTES
AP-116 An Intelligent Data Base System Using the 8272 .............................. .
AP-121 Software Design and Implementation of Floppy Disk Systems ................. .
HARD DISK CONTROLLERS
DATA SHEETS
82062 Winchester Disk Controller .................................................. .
82064 Winchester Disk Controller with On-Chip Error Detection and Correction ........ .
APPLICATION NOTES
AP-182 Multimode Winchester Controller Using the 82062 .. ',' ........................ .
UNIVERSAL PERIPHERAL INTERFACE SLAVE MICROCONTROLLERS
DATA SHEETS
UPI-452 Slave Microcontroller (8051) ............................................... .
UPI-41 8-Bit Slave Microcontroller ................................................. .
UPI-42 8-Bit Slave Microcontroller ............•.....................................
8243 MCS-48 Input/Output Expander .............................................. .

iv

6-1
6-15
6-30
6-52
6-98
6-121
6-151
6-152
6-157
6-166
6-174
6-177
6-181
6-217
6-223
6-228
6-235
6-246

6-253
6-263.
6-274
6-290
6-307
6-328
6-351
6-374
6-386
6-461
~-478

6-497
6-538

6-608
6-635
6-667

6-729
6-768
6-780
6-799

UPI-41/42 USERS MANUAL
Introduction .........•.......•..............•................•................. '•..• 6-805
Functional Description .....................•................•...................... 6-810
Instruction Set .. "...........................................•. ~ .................... 6-827
Single-Step, Programming, and Power-Down Modes .........................•..•..•. 6-854
System Operation ...........................•............•....•..•................ 6-859
Applications ....................................................................... 6-865
AP-161 or 61 Complex Peripheral Control with the UPI-42 ........•.•................•. 6-939
AP-90 An 8741 A/8041 A Digital Cassette Controller ..................................... 6-995
APPLICATION NOTES
Applications Using the 8042 UPI T• Microcontroller ................•..............•.... 6-1003
SYSTEM SUPPORT
ICE-42 8042 In-Circuit Emulator ....•..•................•.•.........•............... 6-1007
MCS-48 Diskette-Based Software Support Package .................................•. 6-1015
iUP-200/iUP-201 Universal PROM Programmers ..........•.•.......••....•..........• 6-1017

CHAPTER 7
ALPHANUMERIC TERMINAL CONTROLLERS
DATA SHEETS
8275H Programmable CRT Controller ................................•..............
8276H Small System CRT Controller ................................................
APPLICATION NOTES
AP-62 A Low Cost CRT Terminal Using the 8275 .....................................
ARTICLE REPRINTS
AR-178 A Low Cost CRT Terminal Does More with Less ...............................
GRAPHICS DISPLAY PRODUCTS
DATA SHEETS
82720 Graphics Display Controller ....................................•.............
ARTICLE REPRINTS
AR-255 Dedicated VLSI Chip Lightens Graphic Display Design Load ...................
AR-298 Graphics Chip Makes Low Cost High Resolution, Color Displays Possible... ....
TEXT PROCESSING PRODUCTS
DATA SHEETS
82730 Text Coprocessor.. .. . .. ... .. . .. ... ...... .... ..... . ..•.•.. . .. .. ........•... ..
ARCHITECTURAL OVERVIEW
The 82786 CHMOS Graphics Coprocessor. . . . . . . . . . . . . . . . . • . . • . . . . • . . • . • . • . . . . . . . . ..
ARTICLE REPRINTS
AR-305 Text Coprocessor Brings Quality to CRT Displays ...•.•...•...................
AR-297 VLSI Coprocessor Delivers High Quality Displays .........•.........•.........
AR-296 Mighty Chips ......................•.........•.•.....•....•.•..•...........

7-1
7-25
7-42
7-84
7-91
7-128
7-136

7-143
7-187
7-205
7-213
7-216

CHAPTER 8
ERASABLE/PROGRAMMABLE LOGIC DEVICES
DATA SHEETS
5C1211200 Gate CHMOS H-Series Eraseable/Programmable Logic Device .............
5C060 600 Gate CHMOS H-Series Erasable/Programmable Logic Device...............

v

8-1
8-15

Numeric Index
5C121 1200 Gate CHMOSH-Series Eraseable/Programmable Logic Device ............... 8-1
5C060 600 Gate CHMOS H-Series Eraseable/Programmable Logic Device .: ............ 8-15
80186 (iAPX 186) High Integration 16-Bit Microprocessor ....................... 3-52, 3-435
80188 (iAPX 188) High Integration 8-Bit Microprocessor ............................. 3-162
80286 (iAPX 286/10) High Performance Microprocessor with Memory Management
and Protection ...................................................• 4-1, 6-228, 6-247
80287 80-Bit HMOS Numeric Processor, Extension ................................... .4-56
80386 High Performance Microprocessor with Integrated Memory Management ..........• 5-1
8041A/8641A/8741A UlJiversal Peripheral Interface
8-Bit Slave Micro Controller ................................ : .......... 6-768, 6-805, 6-994
8042/8742 Universal Peripheral Interface
8-Bit Slave Micro Controller ...................... ; ..... 6-780, 6-805, 6-939, 6-1002, 6-1006
80452/83452/87452 Universal Peripheral Interface 8-Bit Slave Micro Controller ... 6-729, 6-805
8080Al8080A-1/8080A-2, 8-Bit N-Channel Microprocessor ....•...... , ................... 2-1
8085AH/8085AH-2/8085AH-1 8-Bit HMOS Microprocessors ....................•........ 2-10
8086 (iAPX 86/10) 16-Bit HMOS Microprocessor .•......................•.. 3-1, 3-310, 6-181
80C86/80C86-2 16-Bit Microprocessor ............... ; ............•................... 3~25
8087/8087-2/8087-1 Numeric Data Coprocessor ................................ 3-218, 3-373
8088 (iAPX 88/10) 8-Bit HMOS Microprocessor .........................•.. ; .. 3-106, 6-181
80C88/80C88-2 8-Bit CHMOS Microproces~or ....................................... 3-133
8155H/8156H/8155H-2/8156H-2 2048-8it Static HMOS RAM with I/O Ports and Timer .... 2-26
8185/8185-2 1024 x 8-Bit Static RAM for MCS®-85 ..................................... 2-38
8202A Dynamic RAM Controller ..............................................• 6-1, 6-181
820364K Dynamic RAM Controller ....•................................. 6-15, 6-181, 6-217
8205 High Speed 1 out of 8 Binary Decoder .................. : ...........•...............
8206 Error Detection and Correction Unit ................................ 6-30, 6-217, 6-247
82062 Winchester Disk Controller ............................ ; ~ .............. 6-608, 6-667
82064 Winchester Disk Controller with On-Chip Error Detection and Correction ....... 6-635
8207 Dual-Port Dynamic RAM Controller ................... 6-52, 6-150, 6-223, 6-228, 6-247
8208 Dynamic RAM Controller ................................................ 6-98, &235
82C08 Dynamic RAM Controller ................................................... 6-121
82188 Integrated Bus Controller for iAPX86, 88, 186, 188 Processors ................. 3-283
8224 Clock Generator And Driver for 8080A CPU ......................•............. ,2-43
82258 Advanced Direct Memory Access Coprocessor ................................. .4-82
8228/8238 System Controller and Bus Driver for 8080ACPU ........................... 2-48
82284 Clock Generator and Ready Interface for iAPX 286 Processors .•...•........... 4-139
82288 Bus Controller for iAPX 286 Processors ...................................... 4-148
82289 Bus Arbiter for iAPX 286 Processor Family ............................. ; ..... 4-167
8231 A Arithmetic Processing Unit .................................................. 6-253
8237A/8237A-4/8237A-5 High Performance Programmable DMA Controller .............. 2-52
82C37A-5 CHMOS High Performance Programmable DMA Controller .................. 2-67
82384 Clock Generator And Reset Interface for 80386 Processors ....................... 5-2
8243 MCS-48 Input/Output Expander ......................................... 6-799,6-805
vi

8253/8253-5 Programmable Interval Timer .......................................... 6-263
8254 Programmable Interval Timer ................................................. 6-274
82C54 CHMOS Programmable Interval Timer ....................................... 6-290
8255A/8255A-5 Programmable Peripheral Interface .................................. 6-307
82C55A CHMOS Programmable Peripheral Interface ................................ 6-328
8256AH Multifunction Microprocessor Support Controller ................ 6-357, 6-386, 6-461
8257/8257-5 Programmable DMA Controller ........................................... 2-78
8259A/8259A-2/8259A-8 Programmable Interrupt Controller ..................... 2-95, 2-144
82C59A-2 CHMOS Programmable Interrupt Controller ............................... 2-113
8272A Single/Double Density Floppy Disk Controller .............. ~ ..... 6-478, 6-497, 6-538
82720 Graphics Display Controller ................... 7-91,7-128,7-136,7-205,7-213,7-216
82730 Text Coprocessor 7-136, 7-143, 7-205, 7-213, 7-216 .. , ......... , .................... , .
8275H Programmable CRT Controller ......................... ~ ................. 7-1, 7-42
8276H Small System CRT Controller ....................................•...... 7-25, 7-84
82786 ............................................................................ 7-187
8279/8279-5 Programmable Keyboard/Display Interface ................... , .......... 6-374
8282/8283 Octal Latch ................................................. " . . . . . . . . .. 3-241
8284A/8284A-1 Clock Generator and Driver for iAPX 86, 88 Processors ............... 3-246
82C84A/82C84A-5 CHMOS Clock Generator And Driver
For 80C86, 80C88 Processors ................................................ ,..... 3-254
8286/8287 Octal Bus Transceiver 3-263 ................................................... .
8288 Bus Controller for iAPX 86, 88 Processors ..................................... 3-268
82C88 CHMOS Bus Controller for 80C86, 80C88 Processors ................... '...... 3-275
8289/8989-1 Bus Arbiter ........................................................... 3-299
8755A/8755A-2 16,384-Bit EPROM with I/O ......................................... 2-133

vii

CUSTOMER SUPPORT
CUSTOMER SUPPORT

Customer Support is Intel's complete support service that provides Intel customers with Customer
Training, Software Support and Hardware Support;
After a customer purchases any system hardware or software product, service and support become
major factors in determining whether that product will continue to meet a customer's expectations.
Such support requires an international support organization and a breadth of programs to meet a
variety of customer needs. intel's extensive customer support includes factory repair services as well as
worldwide field service offices providing 'hardware repair services, software support services and
customer training classes.
HARDWARE SUPPORT.

Hardware Support Services provides maintenance on Intel supported products at board and system
level. Both field and factory services are offered. Services include several types of field maintenance
agreements, instailation and warranty services, hourly contracted services (factory return for repair) and
specially negotiated support agreements for system integrators and large volume end-users having
unique service requirements. FO,r more information contact your local Intel Sales Office.
SOFTWARE SUPPORT

. Software Support Service provides maintenance on software packages via software support contracts
which include subscription services, information phone support, and updates. Consulting services can
be arranged for on-site assistance at the customer's location for both short-term and long-term needs.
For complex products such as NDS II or PICE, orientation/ installation packages are available
through membership in Insite User's Library, where customer-submitted programs are catalogued and
made available for a minimijm fee to members. For more information contact your local Intel Sales
Office.
CUSTOMER TRAINING

Customer Training provides workshops at customer sites (by agreement) and on a regularly scheduled
basis at Intel's facilities. Intel offers a breadth of workshops on microprocessors, operating systems and
programming languages, etc. For more information on these classes contact the Training Center nearest
you.
TRAINING CENTER LOCATIONS

To obtain a complete catalog of our workshops, call the nearest Training Center in your area.
Boston
Chicago
San Francisco
Washington, D.C.
Israel
Tokyo
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Toronto, Canada

(617) 692-1000
(312) 310-5700
(415) 940-7800
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03-437-6611
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(416) 675-2105

London
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viii

(0793) 696-000
(089) 5389-1
(01) 687-22-21
(468) 734-01-00
39-2-82-44-071
(10) 21-23-77
(I) 198-033
5-215311-7

OVERVIEW

INTRODUCTION
Intel microprocessors and peripherals provide a complete
solution in increasingly complex application environments. Quite often, a single peripheral device will replace
anywhere from 20 to 100 TTL devices (and the associated
design time that goes with them).
Built-in functions and standard Intel microprocessor/
peripheral interface deliver very real time and performance advantages to the designer of microprocessorbased systems.
REDUCED TIME TO MARKET
When you can purchase an off-the-shelf solution that
replaces a number of discrete devices, you're also replacing all the design, testing, and debug time that goes with
them.
INCREASED RELIABILITY
At Intel, the rate offailure for devices is carefully tracked.
Highest reliability is a tangible goal that translates to
higher reliability for your product, reduced downtime,
and reduced repair costs. And as more and more
functions are intergrated on a single VLSI device, the
resulting system requires less power, produces' less heat,
and requires fewer mechanical connections-again resulting in greater system reliability.
LOWER PRODUCTION COST
By minimizing design time, increasing reliability, and

replacing numerous parts, microprocessor and peripheral
solutions can contribute dramatically to lower product
costs.

HIGHER SYSTEM PERFORMANCE
Intel microprocessors and peripherals provide the highest
system performance for the demands of today's (and
tomorrow's) microprocessor-based applications. For example, the 80386 32 bit offers the highest performance for
multitasking, multiuser systems. Intel's peripheral products have been designed with the future in mind. They
support all of Intel's 8, 16 and 32 bit processors.

HOW TO USE THE GUIDE
The following application guide illustrates the range of
microprocessors and peripherals that can be used for the
applictions in the vertical column of the left. The
peripherals are grouped by the I/O function they control.
CRT datacommunication, universal (user programmable),
mass storage dynamic RAM controllers, and CPU/bus
support.
An "X" in a horizontal application row indicates a
potential peripheral or CPU, depending upon the features
desired. For example, a conversational terminal could
use either of the three display controllers, depending
upon features like the number of characters per row or
font capability. A "Y" indicates a likely candidate, for
example, the 8272A Floppy Disk Controller in a small
business computer.

The Intel microprocessor and peripherals family provides
a broad range of time-saving, high performance solutions.

inter

Intel's Microsystem Components Kit Solution

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WORKSTATIONS

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AH,

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ADDRESS
ALa

60
REFRESH
COUNTER

...........

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... - - - - - - - 1
iiCs-----oj

RA'So

aiJTo

m,
m2

M1

RAs3

AL,

AL,

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AL,

CAS
TIMING
GENERATOR

N.C.

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WE

0iJf3

AL4
0iJf4

SACK
REFRO/ALE

--------1

ALS

5lJfs
XACK
ALO

0uT6
GNO

Figure 1. 8202A Block Diagram

Figure 2. Pin Configuration

6-1

205215-001

8202A

Table 1. Pin Descriptions
Name and Function

Symbol

Pin
No. Type Name and Function

I
I
I
I
I
I
I

Address Low: CPU address in·
puts used to generate memory'
row address.

RASO
RAS1
RAS2
RAS3

21
22
23
26

0
0
0
0

Row Address Strobe: Used to
latch the Row Address into the
bank of dynamic RAMs, select·
ed by the 8202A Bank Select
pins (BO, Bl/0Pl).

XACK

29

0

5
4
3
2
1
39
38

I
I
I
I
I
I
I

Address High: CPU address in·
puts used to generate memory
column address.

Transfer Acknowledge: This
output is a strobe indicating val·
id data during a read cycle or
data written during a write cycle.
XACK can be used to latch valid
data from the RAM array.

SACK

30

0

BO
Bl/ 0P l

24
25

I
I

Bank Select Inputs: Used to
gate the appropriate RASO·
RAS3 output for a memory cy·
cle. B 1/ OP 1 option used to se·
lect the Advanced Read Mode.

PCS

33

I

Protected Chip Select: Used to
enable the memory read and
write inputs. Once a cycle is
started, it will not abort even if
PCS goes inactive before cycle
completion.

System Acknowledge: This
output indicates the beginning of
a memory access cycle. It can
be used as an advanced trans·
fer acknowledge to eliminate
wait states. (Note: If a memory
access request is made during a
refresh cycle, SACK is delayed
until XACK in the memory ac·
cess cycle).

(XO) OP2
(XI) ClK

36
37

110
110

Oscillator Inputs: These inputs
are designed for a quartz crystal
to control the frequency of the
oscillator. If XO/ OP2 is connect·
ed to a 1Kfl resistor pulled to
+ 12V then XI / ClK becomes a
TTL input for an external clock.

N.C.

35

Reserved for future use.

Vce

40

Power Supply:+5V.

GND

20

Ground.

Symbol

Pin
No. Type

ALo
ALI
Al2
AL3
AL4
Al5
Al6/

6
8
10
12
14
16
18

AHO
AHI
AH2
AH3
AH4
AH5
AH6

WR

31

I

Memory Write Request.

RD/Sl

32

I

Memory Read Request: SI
function used in Advanced Read
mode selected by OP 1 (pin 25).

REFRQ/
ALE

34

OUTO
OUTI
OUT2
OUT3
OUT4
OUT5
OUT6

7
9
11
13
15
17
19

I

0
0
0
0
0
0
0

External Refresh Request: ALE
function used in Advanced Read
mode, selected by OP 1 (pin 25).

NOTE: Crystal mode for the B202A·l or 8202A·3 only.

Output of the Multiplexer:
These outputs are designed to
drive the addresses olthe Dynamic
RAM array. (Note that the OUT0.6
pins do not require inverters or
drivers for proper operation.)

I--.....-~--I Xo

cs*
I

I

I

lKn
±5%

I

x,
8202A-l
or
8202A-3

WE

CAS

28

27

0

0

Write En,able: Drives the Write
Enable inputs of the Dynamic
RAM array.

Cs

< 10pF

FUNDAMENTAL XTAl

Column Address Strobe: This
output is used to latch the Col·
umn Address into the Dynamic
RAM array.

Figure 3. Crystal Operation for the 8202A-1
and the 8202A-3

6-2

205215-001

inter

8202A

Functional Description

the memory's rows. The 8-bit counter is incremented after
every refresh cycle.

The 8202A provides a complete dynamic RAM controller
for microprocessor systems as well as expansion memory
boards. All of the necessary control signals are provided for 2117 and 2118 dynamic RAMs.

Address Multiplexer
The address multiplexer takes the address inputs and the
refresh counter outputs, and gates them onto the address
outputs at the appropriate time. The address outputs, in
conjunction with the RAS and CAS outputs, determine the
address used by the dynamic RAMs for read, write, and
refresh cycles. During the first part of a read or write cycle, ALo-ALa are gated to OUTO-OUTS, then AHo-AHa
are gated to the address outputs.

All 8202A timing is generated from a single reference
clock. This clock is provided via an external oscillator or
an on chip crystal oscillator. All output signal transitions
are synchronous with respect to this clock reference, except for the CPU handshake signals SACK and XACK
(trailing edge).
CPU memory requests normally use the RD and WR inputs. The advanced READ mode allows ALE and S 1 to be
used in place of the RD input.

During a refresh cycle, the refresh counter is gated onto
the address outputs. All refresh cycles are RAS-only refresh (CAS inactive, RAS active).

Failsafe refresh is provided via an internal refresh timer
which generates internal refresh requests. Refresh requests can also be generated via the REFRQ input.

To minimize buffer delay, the information on the address
outputs is inverted from that on the address inputs.

An on-chip synchronizer / arbiter prevents memory and refresh requests from affecting a cycle in progress. The
READ, WRITE, and external REFRESH requests may be
asynchronous to the 8202A clock; on-chip logic will synchronize the requests, and the arbiter will decide if the requests should be delayed, pending completion of a cycle in
progress.

OUTO-OUT a do not need inverters or buffers unless additional drive is required.

Synchronizer / Arbiter
The 8202A has three inputs, REFRQ / ALE (pin 34), RD
(pin 32) and WR (pin 31). The RD and WR inputs allow an
external CPU to request a memory read or write cycle,
respectively. The REFRQ/ ALE allows refresh requests to
be requested external to the 8202A.

Option Selection
The 8202A has two strapping options. When OP,is selected (1SK mode only). pin 32 changes from a RD input to
an S 1 input, and pin 34 changes from a REFREQ input to
an ALE input. See "Refresh Cycles" and "Read Cycles"
for more detail. OP1 is selected by tying pin 25 to
+12V through a 5.1 K ohm resistor on the 8202A-1. or
8202A-3 only.

All three of these inputs may be asynchronous with respect to the 8202A's clock. The arbiter will resolve conflicts between refresh and memory requests, for both
pending cycles and cycles in progress. Read and write requests will be given priority over refresh requests.

System Operation

When OP2 is selected, by connecting pin 3a to + 12V
through a 1K ohm resistor, pin 37 changes from a crystal
input (X 1) to the CLK input for an external TIL .clock.

The 8202A is always in one of the following states:
a)
b)
c)
d)
e)

Refresh Timer
The refresh timer is used to monitor the time since the last
refresh cycle occurred. When the appropriate amount of
time has elapsed, the refresh timer will request a
refresh cycle. External refresh requests will reset the
refresh timer.

IDLE
TEST Cycle
REFRESH Cycle
READ Cycle
WRITE Cvcle

The 8202A is normally in the IDLE state. Whenever one of
the other cycles is requested, the 8202A will leave the
IDLE state to perform the desired cycle. If no other cycles
are pending, the 8202A will return to the IDLE state.

Refresh Counter
The refresh counter is use'd to sequentially refresh all of

Description

Pin #

Normal Function

B1/0P1

25

Bank (RAS) Select

Advanced-Read Mode (see text)

XO/OP2

36

Crystal Oscillator (8202A-1 or 8202A-3)

External Oscillator

Option Function

.... igure 4. 8202A Option Selection

6-3

205215-001

8202A

Test Cycle
The TEST Cycl!;! is used to check operation of several
8202A internal functions. TEST cycles are requested
by activating the RD and WR inputs, independent of
PCS. The TEST Cycle will reset the refresh address
counter. It will perform a WRITE Cycle if PCS is low.
The TEST Cycle should not be used in normal system
operation, since it would affect the dynamic RAM
refresh.

SO~

- - - - REFRQ

-""

8202A

'-_ _________

Refresh Cycles

Figure 5.

The 8202A has two ways of providing dynamic RAM refresh:

~:;Kor

Hidden Refresh

Read Cycles
The 8202A can accept two different types of memory,
Read requests:

1) Internal (failsafe) refresh
2) External (hidden) refresh

1) Normal Read, via the RD input
2) Advanced Read, using the S1 and ALE inputs

Both types of 8202A refresh cycles activate all of the RAS
outputs, while CAS, WE, SACK, and XACK remain inactive.
.

The user can select the desired Read request configuration via the B1 /OP1 hardware strapping option on pin 25.

Internal refresh is generated by the on-chip refresh timer.
The timer uses the 8202A clock to ensure that refresh of
all rows of the dynamic RAM occurs every 2 milliseconds.
If REFRQ is inactive, the refresh timer will request a refresh cycle every 10-16 microseconds.

Pin 25
Pin 32
Pin 34
# RAM banks
Ext. Refresh Req.

External refresh is requested via the REFRQ input (pin 34).
External refresh control is not available when the Advanced-Read mode is selected. External refresh requests
are latched, then synchronized to the 8202A clock.

Normal Read

Advanced Read

81 input
RD input
REFRQ input
4 (RAS 0.3)
Yes

+12 Volt Option
Sl input
ALE input
2 (RAS 2-3)
No

Figure 6. 8202A Read Options

The arbiter will allow the refresh request to start a refresh
cycle orily if the 8202A is not in the middle of a cycle.

Normal Reads are requested by activating the RD input,
and keeping it active until the 8202A responds with an
XACK pulse. The RD input can go inactive as soon as the
command hold time (tCHS) is met.

Simultaneous memory request and external refresh request will result in the memory request being honored first.
This 8202A characteristic can be used to "hide" refresh
cycles during system operation. A circuit similar to
Figure 5 can be used to decode the CPU's instruction
fetch status to generate an external refresh request. The
refresh request is latched while the 8202A performs the
instruction fetch; the refresh cycle will start immediately
after the memory cycle is completed, even if the RD input
has not gone inactive. If the CPU's instruction decode time
is long enough, the 8202A can complete the refresh cycle
before the next memory request is generated.

Advanced Read cycles are requested by pulsing ALE
while S 1 is active; if S 1 is inactive (low) ALE is ignored.
Advanced Read timing is similiar to Normal Read timing,
except the falling edge of ALE is used as the cycle start
reference.
If a Read cycle is requested while a refresh cycle is in
progress, then the 8202A will set the internal delayedSACK latch. When the Read cycle is eventually started,
the 8202A will delay the active SACK transition until XACK
goes active, as shown in the AC timing diagrams. This de-'
lay was designed to compensate for the CPU's READY
setup and hold times. The delayed-SACK latch is cleared
after every READ cycle.

Certain system configurations require complete external
refresh requests. If external refresh is requested faster
than the minimum internal refresh timer (tREF), then, in effect, all refresh cycles will be caused by the external refresh request, and the internal refresh timer will never
generate a refresh request.

Based on system requirements, either SACK or XACK can
be used to generate the CPU READY signal. XACK will

6-4

205215-001

8202A

normally be used; if the CPU can tolerate· an advanced
READY, then SACK can be used, but only if the CPU can
tolerate the amount of advance provided by SACK. If
SACK arrives too early to provide the appropriate number
of WAIT states, then either XACK or a delayed form of
SACK should be used.

A microprocessor system is concerned with the time data
is valid after RD goes low. See Figure 7. In order to calculate memory read access times, the dynamic RAM's A.C.
specifications must be examined, especially the RAS-access time (tRAC) and the CAS-access time (tCAC). Most
configurations will be CAS-access limited; i.e., the data
from the RAM will be stable tcc,max (8202A) + tCAC
(RAM) after a memory read cycle is started. Be sure to
add any delays (due to buffers, data latches, etc.) to calculate the overall read access time.

Write Cycles
Write cycles are similiar to Normal Read cycles, except
for the WE output. WE is held inactive for Read cycles, but
goes active for Write cycles. All 8202A Write cycles are
"early-write" cycles; WE goes active before CAS goes active by an amount of time sufficient to keep the dynamiC
RAM output buffers turned off.

Since the 8202A normally performs "early-write" cycles,
the data must be stable at the RAM data inputs by the time
CAS goes active, including the RAM's data setup time. If
the system does not normally guarantee sufficient write
data setup, you must either delay the WR input signal or
delay the 8202A WE output.

General System Considerations
All memory requests (Normal Reads, Advanced Reads,
Writes) are qualified by the PCS input. PCS should be stable, either active or ·inactive, prior to the leading edge of
RD, WR, or ALE. Systems which use battery backup
should pullup PCS to prevent erroneous memory requests,
and should also pullup WR to keep the 8202A out of its
test mode.

Delaying the WR input will delay all 8202A timing, including
the READY handshake signals, SACK and XACK, which
may increase the number of WAIT states generated by the
CPU.
If the WE output is externally delayed beyond the CAS active transition, then the RAM will use the falling edge of WE
to strobe the write data into the RAM. This WE transition
should not occur too late during the CAS active transition,
or else the WE to CAS requirements of the RAM will not be
met.

In order to minimize propagation delay, the 8202A uses an
inverting address multiplexer without latches. The system
must provide adequate address setup and hold times to
guarantee RAS and CAS setup and hold times for the
RAM. The 8202A tAD AC parameter should be used for
this system calculation.
The BO-B 1 inputs are similiar to the address inputs in that
they are not latched. BO and B 1 should not be changed
during a memory cycle, since they directly control which
RAS output is activated.

Ro~I

~----~--------~I
~

DATA

The 8202A uses a two-stage synchronizer for the memory
request inputs (RD, WR, ALE), and a separate two stage
synchronizer for the external refresh input (REFRQ). As
with any synchronizer, there is always a finite probability
of metastable states inducing system errors. The 8202A
synchronizer was designed to have a system error rate
less than 1 memory cycle every three years based on the
full operating range of the 8202A.

______

/

-J

_ _ _ II

"':q-----tRlDV

!IE

B--

-----------«

I
:
t-tRAC-.......J
I
I
RAS

i ;-

------""""'~

I

I

tCAC

I

1;-

4----+1

CAS - - - - - - - - - - - - - - " ' ' \

Figure 7. Read Access Time

6-5

205215-001

8202A

2118

DYNAMIC RAM ARRAY

AS-15

ALE

8088
ADO-7

RO
WR

~

ALO-6

...... r--AO-6

r

OTITO-6

AHO-6

80-1
8202A
{16K MODE)

~

WE

CAS

r=p

RAS,

-<

f-

RASa

RD/S1
WR

E-

RAS2t::
RAS3

SACK

."..--

~

r'

BAL

l

-

WE
CAS
RAS
DIN DOUl

-1

~

..

:::

U

+

AO-6

XACK

~
t----

O'N
DOU1

WE
CAS
RAS
DIN DOUT

D'N
DOUT

:u

'1,

II
AO-.

WE

- ,TT.
CAS
RAS

D'N

IT

DIN DOUT

~

AO-•
BAL
D'N

~S~
DATA-BUS

c.-===:

CAS
RAS
DIN DOUT

1" T

V
--1\

D'N

WE
D'N
DOUT

I

DATA

LATCH IN

D'N
DOUT

J

,ID'NDOUT
DIN
DOUT

Dour

DOUT

DOUT

.---

J j

Figure 8. Typical 8088 System

6-6

205215-001

inter

8202A

ABSOLUTE MAXIMUM RATINGS'

•NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Ambient Temperature Under Bias ............ O'C to 70'C
Storage Temperature ................ -6S0C to +150°C
Voltage On any Pin
With Respect to Ground ................ -0.5V to +7V4
Power Dissipation ............................ 1.5 Watts

D.C. CHARACTERISTICS

TA

= O°C to 70°C; VCC = 5.0V ±
Min

10%, VCC

Parameter

Vc

Input Clamp Voltage

-1.0

V

ICC

Power Supply Current

270

rnA

IF

Forward Input Current
ClK
All Other Inputs 3

-2.0
-320

IR

Reverse Input Current 3

VOL

Output low Voltage
SACK,XACK
All Other Outputs

VOH

Output High Voltage
SACK,XACK
All Other Outputs

Vil

Input low Voltage

VIHI

Input High Voltage

VIH2

Option Voltage

CIN

Input Capacitance

Max

= 5.0V ±

Symbol

Units

5% for 8202A-3, GND

IC

= -S rnA

rnA
p.A

VF
VF

= 0.45V
= O.4SV

40

p.A

VR

=Vee (Note 1)

0.45
0.45

V
V

10l
10l

V.
V

10H
10H

V

VCC = 5.0V (Note 2)

2.4
2.6
0.8
2.0

30

= OV

Test Conditions

= 5 rnA
= 3 rnA
Vil = 0.65V
=;

-1 rnA

= -1

rnA

V

VCC = 5.0V

V

(Note 4)

pF

F = 1 MHz
VB lAS = 2.SV, VCC = 5V
TA = 2S'C

NOTES:
1. IR = 200l'A for pin 37 (elK) for external clock mode.
2. For test mode RD & WR must be held at GND.
3. Except for pin 36.
4. 8202A-l and 8202A-3 supports both OP, and OP,. 8202A only supports OP,.

+12 Volt
±10%

' K

36

OP,
8202A

1

5.1 K

2S

OPI

Resistor Tolerance: ±5%

6-7

205215-001

8202A

A.C. CHARACTERISTICS
TA = O'C to 70'C, vcc "" 5V ± 10%, VCC = 5V ± 5% for 8202A-3
Measurements made with respect to RASO-RAS3, CAS, WE,OUTo-OUTe are at 2.4V and 0.8V. All
other pins are measured at 1.5V. All times are in nsec.

Symbol

Parameter

Min

Max

tp

Clock Period

40

54

tpH

External Clock High Time

20

tpL

External Clock Low Time-above (» 20 mHz

17

tpL

External Clock Low Time-below

«) 20 mHz

20

tRC

Memory Cycle Time

tREF

Refresh Time (128 cycles-16K mode)

10tp - 30

12tp

264tp

288tp

Notes

4,5

tRP

RAS Precharge Time

4tp - 30

tRSH

RAS Hold After CAS

5tp - 30

3

tASR

Address Setup to RAS

tp - 30

3

tRAH

Address Hold From RAS

tp - 10

3

tASC

Address Setup to CAS

tp - 30

3

tCAH

Address Hold from CAS

5tp - 20

3

tCAS

5tp - 10

'CAS Pulse Width

twcs

WE Setup to CAS

tp - 40

tWCH

WE Hold After CAS

5tp - 35

tRS

RD, WR, ALE, REFRQ delay from RAS

tMRP

RD, WR setup to RAS

tRMS

REFRQ setup to RD, WR

2tp

tRMP

REFRQ setup to RAS

2tp

tpcs

PCS Setup to RD, WR, ALE

20

tAL

S 1 Setup to ALE

15

tLA

S 1 Hold from ALE

30

tCR

RD, WR, ALE to RAS Delay

tp

tcc

RD, WR, ALE to CAS Delay

3tp

tsc

CMD Setup to Clock

15

tMRS

RD, WR setup to REFRQ

5

+ 30
+ 25

tCA

RD, WR, ALE to SACK Delay
CAS to XACK Delay

5tp - 25

tcs

CAS to SACK Delay

5tp - 25

tACK

XACK to CAS Setup

10

XACK Pulse Width

tCK

SACK, XACK turn-off Delay

5

0

tcx

txw

8

5tp

5

2tp
4tp

+ 70
+ 85

2
2
1

+ 47
+ 20
5tp + 40

2tp

2,9

5tp

tp - 25

2,10

7
35

tKCH

CMD Inactive Hold after SACK, XACK

10

tLL

REFRQ Pulse Width

20

tCHS

CMD Hold Time

30

tRFR

REFRQ to RAS Delay

tww

WR to WE Delay

tAD

CPU Address Delay

11

+ 100

e

0

50

8

0

40

3

4tp

6-8

205215-001

8202A

WAVEFORMS
Normal Read or Write Cycle

tRS -----+-

Advanced Read Mode

ALE

IAS-

~~1~-

__ ~'i~_I'-------_---J

ICC

-MAX
XACK

SACK

-tCA-

6-9

205215-001

intJ

8202A

WAVEFORMS (cont'd)
Memory Compatibility Timing

~~

_______________V_A_lI_D_AD_D_RE_S_S________________

~~~

~~~~ ------+

____________________________

-~~-

!\
:1

tRSH

I

tCAS

/

!\
!---tASR_

~

!--tRAH .....

ROW

-tASC--

X

I-tCAH-

K

COLUMN

Write Cycle Timing

I

\

I

1\
.1

~~C~-\
MIN

-~'i~-I'
\

--1/
_twcs_

.

tcc
MIN

.

tcc
MAX

- + - - - - tWCH

6-10

.

tww

-

I

205215-001

inter

8202A

WAVEFORMS (cont'd)
Read or Write Followed By External Refresh

\

RD, WR

\.
...- tMRS---' ........- tLl ______

REFRQ

I

It

\
\

.

1\

.

.
.

tMIccN
tcc
MAX

__ tRP_.

tRMP

l~tRS_ .---~'i~~

tRC

.r\

.1

~

External Refresh Followed By Read or Write

iffi,WR

_tRMS - . l+=========-tM-R-P==========o-I.-I-----------..
,----"""'

REFRQ

-tLL

I··---

tRs .......

J---:-----tRC - - - - - - 1

\'-----

6-11

205215-00)

intJ

8202A

WAVEFORMS (cont'd)
Clock And System Timing

elK

RD, \YR, ALE

Table 2

8202A Output Test
Loading

A.C. TESTING LOAD CIRCUIT

Test Load
Pin
SACK.XACK
OUTo-OUTe
RASo-RAS3

WE
CAS

CL=30pF
CL = leo pF
CL=60pF
CL = 224 pF
CL = 320 pF

. NOTES:
1. tsc Is a reference point only. ALE. RO. WR. and REFRQ inputs do
not have to be externally synchronized to 8202A clock.
2. If tRS min and tMRS min are met then. tCA. tCR. and tcc are
valid. otherwise tcs Is valid.
3. tASR. tRAH. tASC. tCAH. and tRSH depend upon 80-81 and CPU
.address remaining stable throughout the memory cycle. The address Inputs are not latched by the 8202A.
4. For back-to-back refresh cycles. tRC max = 13tp
5. tRC max Is valid only if tRMP min Is met (READ. WRITE followed
by REFRESH) or tMRP min Is met (REFRESH followed by READ.
WRITE).
8. tRFR Is valid only If tRS min and tRMS min are met.
7. txw min applies when RD. WR has already gone high. Otherwise
XACK follows RD. WR.
8. WE goes high according to tWCH or tWW. whichever occurs
first.·

DEVICE
UNDER
TEST

I

C
'

C, INCLUDES JIG CAPACITANCE

9. tCA applies only when In normal SACK mode.
10. tcs applies only when in delayed SACK mode.
11. tCHS must be met only to ensure a SACK active pulse when In
delayed SACK mode. XACK will always be activated for at
least txw (tp-25 nS). Violating tCHS min does not otherwise
affect device operation.

6-12

205215-001

inter

8202A

The typical rising and falling characteristic curves for the
OUT, RAS, CAS and WE output buffers can be used to
determine the effects of capacitive loading on the A.C.

Timing Parameters. Using this design tool in conjunction
""lith the timing waveforms, the designer can determine
typical timing shifts based on system capacitive load.

A.C. CHARACTERISTICS FOR DIFFERENT CAPACITIVE LOADS
5.0 , _ _ _, -_ __+---.,-----,----,------,----,----,---'C::.A,PA"'C::.'T"'A;.:NC:::E::.'.:.:,PF

0.81----1----J,~~3..s~~--_1__---1-----I---_J---_1___-_I__

__....j

O.O~--~---_+---~---~---L---~---~----L---~--~

~5n'-1

TIME

5.0 . -_ _---,_---+-----r---,-----r------,-----.------.----C-A.,.PA-C-'T-A-NC-E-',-!PF

~

...~
"o

2A~----_4----4__+4-~~~--~~~~~~~----_4------_+----~----+----~

TIME

NOTE:

MEASUREMENT CONDITIONS:

Use the Test Load as the base capacitance for estimating timing
shifts for system critical timing parameters.

TA = 25'C
Vee = +5V
tp = 50 ns

6-13

Pins not measured are loaded with the
Test Load capacitance.

205215-001

8202A

Example: Find the effect on teR and tee using 64
2118 Dynamic RAMs configured in 4 banks.
1. Determine the typical RAS and CAS capacitance:
From the data sheet RAS = 4 pF and CAS = 4 pF.
:. RAS load = 64 pF + board capacitance.
CAS load = 256 pF + board capacitance.
Assume 2 pF/in (trace length) for board
capacitance.

2. From the waveform diagrams, we determine that
the fallins. edge timing is needed for teR and tee.
Next find the curve that best app~oximates the
test load; i.e., 68 pF for RAS and 330 pF for CAS.
3. If we use 72 pF for RAS loading, then the teR
(max.) spec should be increased by about 1 ns.
Similarly if we us~ 288 pF for CAS, then tee (min.)
and (max.) should decrease about 1 ns.

6-14

205215-001

8203
64K DYNAMIC RAM CONTROLLER
• Provides All Signals Necessary to
Control64K (2164) and 16K (2117, 2118)
Dynamic Memories

• Fully Compatible with Intel® 8080A,
808SA, iAPX 88, and iAPX 86 Family Microprocessors

• Directly Addresses and Drives Up to 64
Devices Without External Drivers

• Decodes CPU Status for Advanced Read
Capability in 16K mode with the 8203-1 and
the 8203-3.

• Provides Address Multiplexing and
Strobes
• Provides a Refresh Timer and a Refresh
Counter
• Provides Refresh/ Access Arbitration
• Internal Clock Capability with the 8203-1
and the 8203-3

• Provides System Acknowledge and Transfer Acknowledge Signals
• Refresh Cycles May be Internally or Externally Requested (For Transparent Refresh)
• Internal Series Damping Resistors on All
RAM Outputs

The Intel® 8203 is a Dynamic Ram System Controller designed to provide all signals necessary to use 2164, 2118
or 2117 Dynamic RAMs in microcomputer systems. The 8203 provides multiplexed addresses and address
strobes, refresh logic, refresh/access arbitration. Refresh cycles can be started internally or axternally. The
8203-1 and the 8203-3 support an internal crystal oscillator and Advanced Read Capability. The 8203-3 is a ±5% Vee
part.

~
AH4

Vee

AH3

AH,

OiJTo--OiJT1

AH.

AH,

x,/elK

AH.

oow

'DD"'"

....

oo
REFRESH

AH,

RAJ,

a1/OPt

...,

COUNTER

W2

00/51 _ _ _ _ _- - /

"'-------/

OB-------t

..

on
~OR

....

-

Figure 1. 8203 Block Diagram

AL.

ODTo
AL,

lftlf,
AL,

16K/64I(
REFRQ/ALE

PeS
00151

Wo

iIDf2

SACK

AL3

XACK

0uT3

AL4

M4
Al,

OUTs
Al.

we
CAs
RAS3 (801

D,/0P, (AH71
Bo (AL7)

AAS2 (M71

0iJi6

RAS1

GNO

RASo

Figure 2. Pin Configuration

Intel Corporation Assumes No Responsibility for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses are Implied.
©INTELCORPORATION.1982
6-15
JANUARY 1985

ORDER NUMBER: 210444-004

8203

'NOTE: Stresses above those listed under "Absolute Maximu'!' Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for exten'ded periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS'
Ambient Temperature Under Bias ............ O°C to 70'C
Storage Temperature .....
. .... -65°C to +150'C
Voltage On any Pin
With Respect to Ground ................ -0.5V to + 7V4
Power Dissipation ............................ 1.6 Watts

D.C. CHARACTERISTICS

TA = O°C to 70'C' VCC = 50V +
- 10% (5 OV +- 5% for 8203-3)' GND = OV

Symbol

Parameter

Max

Units

Vc

Input Clamp Voltage

-1.0

V

ICC

Power Supply Current

290

rnA

IF

Forward Input Current
ClK. 64K/16K Mode select
All Other Inputs 3

-2.0
-320

rnA
/lA

VF = 0.45V
VF = 0.45V

40

/lA

VR = VCC; Note 1,5

0.45
0.45

V
V

10l = 5 rnA
10l = 3 rnA

V
V

Vil = 0.65 V
10H = -1 rnA
10H = -1 rnA

0.8

V

VCC = 5.0V (Note 2)

VCC

V

VCC = 5.0V

VCC

V

(Note 4)

30

pF

Min

IR

Reverse Input Current 3

VOL

Output low Voltage
SACK,XACK
All Other Outputs
Output High Voltage
SACK,XACK
All Other Outputs

VOH

Vil

Input low Voltage

VIH1

Input High Voltage

VIH2

Option Voltage

CIN

Input Capacitance

2.4
2.6

2.0

Test Conditions
IC =-5 rnA

F = 1 MHz

NOTES:
1. IR = 200 p.A for pin 37 (elK).
2. For test mode RD & WR must be held at GND.
3. Except for pin 36 in XTAl mode.

4. 8203-1 and 8203-3 supports both OPI and OP2, 8203 only supports OP2.

+12 Volt
±10%

8203

1K

36

L---'INI~--I

0,,"

Resistor Tolerance: ± 5'% L..._ _--I

5. IR = 150/lA for pin 35 (Mode Select 16K/64K)

6-16

VBIAS = 2.5V, VCC = 5V
TA = 25'C

8203

Table

Symbol

Pin
No.

ALa
AL1
AL2
AL3
AL4
AL5
AL6

Type

1. Pin Descriptions
Pin
No.

Type

Name and Function

RASa
RAS1
RAS21
OUT7
RAS3/BO

21
22
23

0
0
0

26

1/0

Row Address Strobe: Used to
latch the Row Address into the
bank of dynamic RAMs, selected by the 8203 Bank Select pins
(BO, B1/OP1). In 64K mode,
only RASa and RAS 1 are available; pin 23 operates as OUT 7
and pin 26 operates as the BO
bank select input.

XACK

29

0

Transfer Acknowledge: This
output is a strobe indicating valid data during a read cycle or
data written during a write cycle.
XACK can be used to latch valid
data from the RAM array.

SACK

30

0

System Acknowledge: This
output indicates the beginning of
a memory access cycle. It can
be used as an advanced transfer acknowledge to eliminate
wait states. (Note: If a memory
access request is made during a
refresh cycle, SACK is delayed
until XACK in the memory access cycle).

XOIOP2

X1 /CLK

36
37

1/0
110

Oscillator Inputs: These inputs
are designed for a quartz crystal
to control the frequency of the
oscillator. If XOIOP2 is shorted
to pin 40 (VCC) or if XOIOP2 is
connected to + 12V through a
1KQ resistor then X 1/ CLK becomes a TTL input for an external clock. (Note: Crystal mode
for the 8203-1 and the 8203-3
only).

16K/64K

35

I

Mode Select: This input selects
16K mode (2117,2118) or 64K
mode (2164). Pins 23-26
change function based on the
mode of operation.

VCC

40

Power Supply: +5V.

GND

20

Ground_

Name and Function

Symbol

6
8
10
12
14
16
18

Address Low: CPU address inputs used to generate memory
row address_

AHa
AH1
AH2
AH3
AH4
AH5
AH6

5
4
3
2
1
39
38

Address High: CPU address inputs used to generate memory
column address_

BO/AL7

24
25

Bank Select Inputs: Used to
gate the appropriate RAS output
for a memory cycle. B 11 OP 1 option used to select the Advanced
Read Mode. (Not available in
64K mode.) See Figure 5.
When in 64K RAM Mode, pins 24
and 25 operate as the AL 7 and
AH7 address inputs.

B1 /OP 1 1

AH7

PCS

33

I

Protected Chip Select: Used to
enable the memory read and
write inputs. Once a cycle is
started, it will not abort even if
PCS goes inactive before cycle
completion.

WR

31

I

Memory Write Request.

RD/S1

32

I

Memory Read Request: S1
function used in Advanced Read
mode selected by OP1 (pin 25).

REFRQI
ALE

34

I

External Refresh Request: ALE
function used in Advanced Read
mode, selected by OP 1 (pin 25).

OUTo
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6

7
9
11
13
15
17
19

0
0
0
0
0
0
0

Output of the Multiplexer:
These outputs are designed to
drive the addresses of the Dynamic RAM array. (Note that the
OUTO_7 pins do not require inverters or drivers for proper operation.)

WE

28

0

Write Enable: Drives the Write
Enable inputs of the Dynamic
RAM array.

0

Column Address Strobe: This
output is used to latch the Column Address into the Dynamic
RAM array.

CAS

27

Functional Description
The 8203 provides a complete dynamic RAM controller for microprocessor systems as well as expansion
memory boards. All of the necessary control signals
are provided for2164, 2118 and 2117 dynamic RAMs.
The 8203 has two modes, one for 16K dynamic RAMs
and one for 64Ks, controlled by pin 35.
6-17

8203

Other Option Selections
WE

Xa

I
I
CS*

1KU

I
I
I

=

±S%

--

X,

.... RASa

C!!.L

8203-1

T

8203·3

6800
":"

I

±5%

or

<

HAS1
RAS2

.J

RAS3

":"

Cs

The 8203 has two strapping options. When OP, is selected
(16K mode only), pin 32 changes from a RD input to an Sl
input, and pin 34 changes from a REFRQ input to an ALE
input. See "Refresh Cycles" and "Read Cycles" for more
detail. OP, is selected by tying pin 25to+12Vthrough a5.1K
ohm resistor on the 8203~1 or 8203-3 only.

CAS

When OP2 is selected, the internal oscillator is disabled
and pin 37 changes from a crystal input (X1) to a ClK
input for an external TTL clock. OP2 is selected by shorting pin 36 (XO/OP2) directly to pin 40 (VCC). No current
limiting resistor should be used. OP2 may also be selected
by tying pin 36 to +12V through a 1Kn resistor.

XACK

10pF

FUNDAMENTAL XTAL

SiCK

Figure 3. Crystal Operation for the 8203-1 and
8203-3
All 8203 timing is generated from a single reference clock.
This clock is provided via an external oscillator or an onchip crystal oscillator. All output signal transitions are synchronous with respect to this clock reference, except for
the trailing edges of the CPU handshake signals SACK and
XACK.

Refresh Timer
The refresh timer is used to monitor the time since the last
refresh cycle occurred. When the appropriate amount of
time has elapsed, the refresh timer will request a refresh
cycle. External refresh requests will reset the refresh
timer.

CPU memory requests normally use the RD and WR inputs. The Advanced-Read mode allows ALE and S1 to be
used in place of the RD input.

Refresh Counter
The refresh counter is used to sequentially refresh all of
the memory's rows. The a-bit counter is incremented after
.
every refresh cycle.

Failsafe refresh is provided via an internai timer which generates refresh requests. Refresh requests can also be
generated via the REFRQ input.
. .
An on-chip synchronizer I arbiter prevents memory and refresh requests from affecting a cycle in progress. The
READ, WRITE, and external REFRESH requests may be
asynchronous to the 8203 clock; on-chip logiC will synchronize the requests, and the arbiter will decide if the requests should be delayed, pending completion of a cycle in
progress ..

Pin #

16K Function

64K Function

'23
24
25
26

RAS2
Bank Select (BO)
Bank Select (B,)
RAS3

Address Output (OUT?)
Address Input (AL?)
Address Input (AH?)
Bank Select (BO)

Figure 4. 16K/64K Mode Selection

16K/64K Option Selection

Inputs

Pin 35 is a strap input that controls the two 8203 modes.
Figure 4 shows the four pins that are multiplexed. In 16K
mode (pin 35 tied to VCC or left open), the 8203 has two
Bank Se'lect inputs to select one of four RAS outputs. In
this mode, the 8203 is exactly compatible with the Intel
8202A Dynamic RAM Controller. In 64K mode (pin 35 tied
to GND), there is only'one Bank Select input (pin 26) to
select the two RAS outputs. More than two banks of 64K
dymimic RAM's can be used with external logic.

16K
Mode
64K
Mode

Outputs

B1

BO

RASO RAS1 RAS2 RAS3

a
a

a

a

1

1

1

a

1

1
1

a
1

1
1
1

-

a

0

1

1

1

a

a

1

1

"

-

1
1
1
0'

-

-

Figure 5. Bank Selection

Description

Pin #

Normal Function

Option Function

B1/0P1 (16Konly)/AH?

25

Bank (RAS) Select

. Advanced-Read Mode

XO/OP2

36

Crystal Oscillator (8203-1 and 8203-3)
Figure 6. 8203 Option Selection
6-18

External Oscillator

(8203-~~

8203

Address Multiplexer

Refresh Cycles

The address multiplexer takes the address inputs and the
refresh counter outputs, and gates them onto the address
outputs at the appropriate time. The address outputs, in
coniunction with the RAS and CAS outputs, determine the
address used by the dynamic RAMs for read, write, and
refresh cycles. During the first part of a read or write cycle, ALO-AL7 are gated to OUTO-OUT7, then AHO-AH7
are gated to the address outputs.

The 8203 has two ways of providing dynamic RAM
refresh:
1) Internal (failsafe) refresh
2) External (hidden) refresh
Both types of 8203 refresh cycles activate all of the RAS
outputs, while CAS, WE, SACK, and XACK remain
inactive.

During a refresh cycle, the refresh counter is gated onto
the address outputs. All refresh cycles are RAS-only refresh (CAS inactive, RAS active).

Internal refresh is generated by the on-chip refresh timer.
The timer uses the 8203 clock to ensure that refresh of all
rows of the dynamic RAM occurs every 2 milliseconds
(128 cycles) or every 4 milliseconds (256 cycles). If
REFRQ is inactive, the refresh timer will request a refresh
cycle every 10-16 microseconds.

To minimize buffer delay, the information on the address
outputs is inverted from that on the address inputs.
OUTO-OUT7 do not need inverters or buffers unless additional drive is required.

External refresh is requested via the REFRQ input (pin 34).
External refresh control is not available when the Advanced-Read mode is selected. External refresh requests
are latched, then synchronized to the 8203 clock.

Synchronizer / Arbiter
The 8203 has three inputs, REFRQI ALE (pin 34), RD (pin
32) and WR (pin 31). The RD and WR inputs allow an external CPU to request a memory read or write cycle, respectively. The REFRQ I ALE input allows refresh requests
to be requested external to the 8203.

The arbiter will allow the refresh request to start a refresh
cycle only if the 8203 is not in the middle of a cycle.
When the 8203 is in the idle state a simultaneous memory
request and external refresh request will result in the memory request being honored first. This 8203 characteristic
can be used to "hide" refresh cycles during system operation. A circuit similar to Figure 7 can be used to decode
the CPU's instruction fetch status to generate an external
refresh request. The refresh request is latched while the
8203 performs the instruction fetch; the refresh cycle will
start immediately after the memory cycle is completed,
even if the RD input has not gone inactive. If the CPU's
instruction decode time is long enough, the 8203 can complete the refresh cycle before the next memory request is
generated.

All three of these inputs may be asynchronous with respect to the 8203's clock. The arbiter will resolve conflicts
between 'refresh and memory requests, for both pending
cycles and cycles in progress. Read and write requests
will be given priority over refresh requests.

System Operation
The 8203 is always in one of the following states:
a)
b)
c)
d)
e)

IDLE
TEST Cycle
REFRESH Cycle
READ Cycle
WRITE Cycle

If the 8203 is not in the idle state then a simultaneous memory request and an external refresh request may result in
the refresh request being honored first.

The 8203 is normally in the IDLE state. Whenever one of
the other cycles is requested, the 8203 will leave the IDLE
state to perform the desired cycle. If no other cycles are
pending, the 8203 will return to the IDLE state.
So

Test Cycle

8085A

The TEST Cycle is used to check operation of several
8203 internal functions. TEST cycles are requested by activating the PCS, RD and WR inputs. The TEST Cycle will
reset the refresh address counter and perform a WRITE
Cycle. The TEST Cycle should not be used in normal system operation, since it would affect the dynamic RAM refresh.

~,..-_ _ _

REFRO

.

S1
8203

SACK or
CAS.

Figure 7. Hidden Refresh

6-19

inter

8203

Write Cycles

Certain system configurations require complete external
refresh requests. If external refresh is requested faster
than the minimum internal refresh timer (tREF), then, in effect, all refresh cycles will be caused by the external refresh request, and the internal refresh timer will never
generate a refresh request.

Write cycles are similiar to Normal Read cycles, except
for the WE output. WE is held inactive for Read cycles, but
goes active for Write cycles. All 8203 Write cycles are
"early-write" cycles; WE goes active before CAS goes active by an amount of time sufficient to keep the dynamic
RAM output buffers turned off.

Read Cycles
The 8203can accept two different types of memory Read
requests:

General System Considerations
All memory requests (Normal Reads, Advanced Reads,
Writes) are qualified by the PCS input. PCS should be stable, either active or inactive, prior to the leading edge of
RD, WR, or ALE. Systems which use battery backup
should pullup PCS to prevent erroneous memory requests.

1) Normal Read, via the RD input
2) Advanced Read, using the S1 and ALE inputs (16K
mode only)
The user can select the desired Read request configuration via the B 1 / OP 1 hardware strapping option on pin 25.

Pin 25
Pin 32
Pin 34
# RAM banks
Ext. Refresh

Normal Read

Advanced Read

81 input
RD input
REFRQ input
4 (RA8 0.3)
Yes

OPI (+12V)
81 input
ALE input
2 (RA8 2.3)
No

In order to minimize propagation delay, the 8203 uses an
inverting address multiplexer without latches. The system
must provide adequate address setup and hold times to
guarantee RAS and CAS setup and hold times for the
RAM. The tAD AC parameter should be used for this system calculation.
.
The BO-B 1 inputs are similiar to the address inputs in that
they are not latched. BO and B1 should not be changed
during a memory cycle, since they directly control which
RAS output is activated.

Figure 8. 8203 Read Options
Normal Reads are requested by activating the RD input,
and keeping it active until the 8203 responds with an
XACK pulse. The RD input can go inactive as soon as the
command hold time (tCHS) is met.
Advanced Read cycles are requested by pulsing ALE
while S 1 is active; if S 1 is inactive (low) ALE is ignored.
Advanced Read timing is similiar to Normal Read timing,
except the falling edge of ALE is used as the cycle start
reference.

The 8203 uses a two-stage synchronizer for the memory
request inputs (RD, WR, ALE), and a separate two stage
synchronizer for the external refresh input (REFRQ). As
with any synchronizer, there is always a finite probability
of metastable states inducing system errors. The 8203
synchronizer was designed to have a system error rate
less than 1 memory cycle every three years based on the
full operating range of the 8203.
A microprocessor system is concerned when the data is
valid after RD goes low. See Figure 9. In order to calculate
memory read access times, the dynamic RAM's A.C ..
specifications must be examined, especially the RAS-access time (tRAC) and the CAS-access time (tCAC). Most
configurations will be CAS-access limited; i.e., the data
from the RAM will be stable tcc,max (8203) + tCAC
(RAM) after a memory read cycle is started. Be sure to
add any delays (due to buffers, data latches, etc.) to calculate the overall read access time.

If a Read cycle is requested. while a refresh cycle is in
progress, then the 8203 will set the internal delayedSACK latch. When the Read cycle is eventually started,
the 8203 will delay the active SACK transition until XACK
goes active, as shown in the AC timing diagrams. This delay was designed to compensate for the CPU's READY
setup and hold times. The delayed-SACK latch is cleared
after every READ cycle.

Since the 8203 normally performs "early-write" cycles,
the data must be stable at the RAM data inputs by the time
CAS goes active, including the RAM's data setup time. If
the system does not normally guarantee sufficient write
data setup, you must either delay the WR input signal or
delay the 8203 WE output.

Based on system requirements, either SACK or XACK can
be used to generate the CPU READY signal. XACK will
normally be used; if the CPU can tolerate an advanced
READY, then SACK can be used, but only if the CPU can
tolerate the amount of advance provided by SACK. If
SACK arrives too early to provide the appropriate number
of WAIT states, then either XACK or a delayed form of
SACK should be used.

Delaying the WR input will delay all 8203 timing, including
the READY handshake Signals, SACK and XACK, which
6-20

8203

may increase the number of WAIT states generated by the
CPU.

Ro~I~--------------~I---------'

If the WE output is externally delayed beyond the CAS active transition, then the RAM will use the falling edge of WE
to strobe the write data into the RAM. This WE transition
should not occur too late during the CAS active transition,
or else the WE to CAS requirements of the RAM will not be
met.

/

.>------tRLDV

.1

1-'

I
DATA

BI

-----------«
I

I

I

I

t.---tRAC~

'\

i ;I

tCAe

The RASO-3, CAS, OUTO-7' and WE outputs contain onchip series damping resistors (typically 20m to minimize
overshoot.

I
I

i;-

'-----t
CAS - - - - - - - - - - - - - - - - - - \

Some dynamic RAMs require more than 2.4V VIH. Noise
immunity may be improved for these RAMs by adding pullup resistors to the 8203's outputs. Intel RAMs do not require pull-up resistors.

Figure g. Read Access Time

2118
DYNAMIC RAM ARRAY

AS-1S

ALE

BOBS

ADO_7
RO
WR

~

ALO-6

-

OUTO-6

AHO-6

BO-l
6203
WE

(16K MODE)

r-p

RASa

WR

g=-

RAS,

-<:

RAS2

SACK

AO-6

=:

WE

-

CAS

ROiS,

--v

RAS3

::j

l'

CAS
RAS

DIN Dour

T

-

WE
CAS
RAS

DIN DOUT

I
::j-::::~

::::

-

O'N

DOUl

Ll

+

AO-6

XACK

=:

-

O'N

r

Dour

..1.,
O'N

l-

WE
CAS
RAS

DIN Dour

Dour

n

;--l

~AO-6

BAL
O'N

~~11
DATA BUS

DATA
LATCH IN

--====

O'N

WE
CAS
RAS

DIN

DIN Dour

T

V

O'N

Dour

l

~

~

'----

Figure 10. Typical 8088 System

6-21

DIN

Dour

:IOINDour

Dour

I j

1

Dour

DOUl

~T

8203

MULTIBUS"!
TYPE
SYSTEM
BUS

8288

READ

MRDe

WRITE

MWTC

8086
BHEN
ADRO

I A9"'
OTHER
READY
INPUTS

ADo-AD15
A16-A19

ADRF

A~'6

I
I
I

READ

ur=
~
WRITE

A"i7-A19

HIGH BYTE
WRITE
WE
t-_~"A_S~X_--"J MEMORY

AD,. I

SHE

I
I
I
I

00-15

8203
CAS

2'64

256K
BYTeS

1>-----.1

DATA

DO

'6

Figure 11. 8086/256K Byte System

6-22

01

'6

8203

A.C. CHARACTERISTICS
TJ = O°C 10 70°C; VCC = 5V ± 10% (5.0V ±

5% for 8203-3); GND

= OV

Measuremenls made wilh respecllo RASO-RAS3, CAS, WE, QUTO-QUT6 are al 2.4V and 0.8V. All
olher pins are measured al 1 5V All limes are in nsec

Symbol

Parameter

Min

Max

Ip

Clock Period

40

54

IpH

Exlernal Clock High Time

20

IPL

Exlernal Clock Low Time-above (» 20 mHz

17

IpL

Exlernal Clock Low Time-below (::S) 20 mHz

20

IRC

Memory Cycle Time

IREF

Refresh Time (128 cycles)

IRP

RAS Precharge Time

41p - 30

tRSH

RAS Hold After CAS

51p - 30

3

tASR

Address Selup 10 RAS

tp - 30

3

tRAH

Address Hold From RAS

tp - 10

3

IASC

Address Selup 10 CAS

Ip - 30

3

ICAH

Address Hold from CAS

51p - 20

3

tCAS

CAS Pulse Widlh

5tp - 10

IWCS
IWCH
IRS

.

IOtp - 30

121p

2641p

2881p

Notes

4,5

WE Selup 10 CAS

Ip - 40

WE Hold Afler CAS

51p - 35

8

51p

2,6

RD, WR, ALE, REFRQ delay from RAS

IMRP

RD, WR selup 10 RAS

0

5

IRMS

REFRQ selup 10 RD, WR

21p

6

IRMP

REFRQ selup 10 RAS

21p

5

IpCS

PCS Selup 10 RD, WR, ALE

20

IAL

S 1 Selup 10 ALE

15

tLA

S l' Hold from ALE

30

+ 30
+ 25

+ 70
+ 85

ICR

RD, WR, ALE 10 RAS Delay

Ip

ICC

RD, WR, ALE 10 CAS Delay

31p

ISC

CMD Selup 10 Clock

15

1

IMRS

RD, WR selup 10 REFRQ

5

2

ICA

RD, WR, ALE 10 SACK Delay

ICX

CAS 10 XACK Delay

51p - 25

ICS

CAS 10 SACK Delay

51p - 25

lACK

XACK 10 CAS Selup

10

IXW

XACK Pulse Widlh

tCK

SACK, XACK lurn-off Delay

21p
41p

+ 47
+ 20
51p + 40
21p

2
2

2,9

51p

Ip - 25

2,10

7
35

IKCH

CMD Inaclive Hold after SACK, XACK

10

ILL

REFRQ Pulse Widlh

20
30

11

ICHS

CMD Hold Time

IRFR

REFRQ 10 RAS Delay

IWW

WR 10 WE Delay

0

50

8

lAD

CPU Address Delay

0

40

3

41p

6-23

+ 100

6

inter

8203

WAVEFORMS
Normal Read or Write Cycle

Advanced Read Mode

6-24

8203

WAVEFORMS (cont'd)
Memory Compatibility Timing

AL~~;~s'. ~
AHo-AHS

...._ _ _ _ _ _V_AL_'D_AD_DR_ES_S_ _ _ _ _ _ _

~'--------------

-~"fx-

-::,~-

1\
tRSH

I

teAs

V

\
_tASR __

CUTo-OUT6

}.

!-IRAH-

!--tASC ....

X

ROW

I-tCAH-

K

COLUMN

Write Cycle Timing

\

I

\

I

4-:li~

-

~I

tCR
""-MAX----'

\

/

.... twcs __

....--tWCH

tcc
MIN

,

tcc
MAX

6-25

.

tww
MIN

tww
MAX

H

'I

-

8203

WAVEFORMS (cont'd)
Read or Write Followed By External Refresh

\
\.
..-tMRS--+ . - - - tLL - - - . . .

\

/

REFRQ

J
l - tRS -

\

.

_tRP_

tRMP

-~Cj,~-

\
tRC

.
.

.1\

•1

tcc
MIN
tcc
MAX

\

External Refresh Followed By Read or Write

RD.WR

---l:========-t

- --------------------..
-,------------ RP
M

REFRQ

1 + - - - - - - tRC - - - - - - 1

\~

6-26

inter

8203

WAVEFORMS (cont'd)
Clock And System Timing

A.C. TESTING LOAD CIRCUIT

Table 2. 8203 Output Loading.
All specifications are
for the Test Load unless otherwise noted
Pin

Test Load

SACK.XACK
OUTO-OUTS
RASO-RAS3

CL
CL
CL
CL
CL

WE
CAS

OEVICE
UNDER

= 30 pF
= lS0 pF
= SO pF
= 224 pF
= 320 pF

TEST

NOTES:
1. tsc is a reference point only. ALE. RD. WR. and REFRQinputs do
not have to be externally synchronized to 8203 clock.
2. If tRS min and tMRS min are met thentCA. tCR. and tcc are valid.
otherwise tcs is valid.
3. tASR. tRAH. tASC. tCAH. and tRSH depend upon BO-B 1 and CPU
address remaining stable throughout the memory cycle. The ad·
dress inputs are not latched by the 8203.
4. For back·to·back refresh cycles.tRC max = 13tp
5. tRC max is valid only if tRMP min is met (READ. WRITE followed
by REFRESH) or tMRP min is met (REFRESH followed by READ.
WRITE).
6. tRFR is valid only if tRS min and tRMS min are met.
7. txw min applies when RD. WR has already gone high. Otherwise
XACK follows RD. WR.
8. WE goes high according to tWCH or tWW. whichever occurs

NOTE:

CL includes jig capacitance

9. tCA applies only when in normal SACK mode. de.
10. tcs applies only when in delayed SACK mode.
11. tCHS must be be met only to ensure a SACK active pulse
when in delayed SACK mode. XACK will always be activated
for at least txw (tp- 25 nS). Violating tCHS min does not
otherwise affect device operation.

first.

6-27

8203

The typical rising and falling characteristic curves for the
OUT, RAS, CAS and WE output buffers can be used to
determine the effects of capacitive loading on the A. C.

Timing Parameters. Using this design tool in conjunction
with the timing waveforms, the designer can determine
typical timing shifts based on system capacitive load.

A.C. CHARACTERISTICS FOR DIFFERENT CAPACITIVE LOADS
CAPACITANCE' p~
5.Dr-----~------i-------r_----_r------~----_.------_r------r_----_r----~

D.' ~--+_~~II!=31Ii5;;:2j::--_+--_+--_t---f__--+_--+_-_I
D.D~----~------;-------~----~------~----~------~------L-----_7----~

TIME

f-5n.~

CAPACITANCE: pF
•. Or-----~------;-------r_----_r------~----_.------_r------r_----~----~

NOTE:

MEASUREMENT CONDITIONS:
Pins not measured are loaded with
TA = 25°C
the Test Load capacitance
VCC = +5V
tp = 50 ns

Use the Test Load as the base capacitance for estimating timing
shifts for system critical timing parameters.

6-28

8203

Example: Find the effect on tCR and tcc using 32 2164
Dynamic RAMs configured in 2 banks.

2. From the waveform diagrams, we determine that the
falling edge timing is needed for tCR and tCC. Next find
the curve that best approximates the test load; i.e.,
68 pF for RAS and 330 pF for CAS.

1. Determine the typical RAS and CAS capacitance:
From the data sheet RAS = 5 pF and CAS = 5 pF.
RAS load = 80 pF + board capacitance.
CAS load = 160 pF + board capacitance.
Assume 2 pF / in (trace length) for board capacitance and for this example 4 inches for RAS and
8 inches for CAS.

3. If we use 88 pF for RAS loading, then tCR (min.) spec
should be increased by about 1 ns, and tCR (max.)
spec should be increased by about 2 ns. Similarly if we
use 176 pF for CAS, then tcc (min.) should decrease
by 3 ns and tcc (max.) should decrease by about 7 ns.

6-29

8206
ERROR DETECTION AND CORRECTION UNIT
• Detects All Single Bit, Double Bit and
Most Multiple Bit Errors

• Separate Input and Output Busses-No
Timing Strobes Required

• Corrects All Single Bit Errors
• 3 Selections 8206-1
8206
Detection
35ns
42ns
Correction
55ns
67ns

• Expandable to Handle 80 Bit Memories
• Supports Read With and Without
Correction, Writes, Partial (Byte)
Writes, and Read-Modify-Writes

8206-2
57ns
74ns

• HMOS III Technology for Low Power

• 8206-2 Timing Supports Single 8206
8M Hz iAPX 186, 188,86,88 and 8207-8
Systems

• 68 Pin Leadless JEDEC Package
• 68 Pin Grid Array Package

• Syndrome Outputs for Error Logging

The HMOS 8206 Error Detection and Correction Unit is a high-speed device that provides error detection and
correction for memory systems (static and dynamic) requiring high reliability and performance. Each 8206
handles 8 or 16 data bits and up to 8 check bits. 8206's can be cascaded to provide correction and detection for
up to 80 bits of data. Other 8206 features include the ability to handle byte writes. memory initialization. and
error logging.

1.

STB

POS o_,

--;::;C=:

,------1

I----_co

C81/SY1 0.7

SYO/CBO/PPO O.1

,.

c:=t:.=~

DATA

CORRECTION

PPIIPOSINSL

•pOSo_.
NSLg.,

Mis

16

)---1-+----4--.1

GND

SEOCU R/W

~5V

11
Vss

Vee

wz

BMO~l

Figure 1. 8206 Block Diagram
Intel Corporation Assumes No Responsibilly for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent Licenses are Implied.
JUNE 1985

© INTEL CORPORATION, 1982.

6-30

Order Number: 205220-007

intel

8206

16
01 0. 15

,----------1

STB-~=L=:

.-------1

Cal a.s

SYNDROME

SYO/CBO o_S

}-----_CO

16

DECODER

¢:=-:t=~

}-----_ORROR

DATA

AND
ERROR

CORRECTION

DETECTION

16

WRITE
PARTIAL PARITY
GENERATOR

GND

R/W

+5V

11

Figure 2. 8206-2 Block Diagram
Table 1. 8206 Pin Description
Symbol

Pin No.

Name and Function

Type

1,68-61,
59·53

I

Data In: These inputs accept a 16 bit data word from RAM'for error detection
and/or correction.

CBI/SYlo
CBI/SYI1
CBI/SYI2
CBI/SYI3
CBI/SYI4
CBI/SYls
CBI/SYls
CBI/SYI7

5
6
7
8
9
10
11
12

I
I
I
I
I
I
I
I

Check Bits In/Syndrome In: In a single 8206 system, or in the master in a multi8206 system, these inputs accept the check bits (5 to 8) from the RAM. ;n a
single 8206 16 bit system, CBIO_5 are used. In slave 8206's these inputs accept
the syndrome from the master.

DOIWDlo
DO/WDI 1
DOIWDI2
DOIWDI3
DOIWDI4
DO/WDls
DO/WDIS
DO/WDI7
DO/WDls
DO/WDlg
DO/WDI 1O
DO/WDI 11

51
50
49
48
47
46
45
44
42
41
40
39
38
37
36
35

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

Data Out/Write Data In: I~ad cycle, data accepted~IO_15 appears~
these outputs corrected if CRCT is low, or uncorrected if CRCT is high. The BM
inputs· must be high to enable the output buffers during the read cycle. In a
write cycle, data to be written into the RAM is accepted by these inputs for computing the write check bits. In a partial-write cycle, the byte not to be modified
appears at either DOO-7 if BMo is high, or DOS-1S if BM1 is high, for writing to
the RAM. When WZ is active, it causes the 8206 to output all zeros at DOO-15,
with the proper write check bits on CBO.

Dl o. 15

~O/wDI"
DO/WDI 13

DO/WDI 14
DO/WDI 1S

6-31

8206

Table 1. 8206 Pin Description (Continued)
Symbol
SYO/CBO/PPOo
SYO/CBO/PP01
SYO/CBO/PP02
SYO/CBO/PP03
SYO/CBO/PP04
.. -SYO/CBO/PP0 5-SYO/CBO/PP06
SYO/CBO/PP07

Pin No.

Type

Name and Function

23
24
25
27
28
29--·
30
31

0
0
0
0
0
0-0
0

Syndrome Out/Check Bits Out/Partial Parity Out: In a single 8206 system, or
in the master in a multi-8206 system, the syndrome appears at these outputs
during a read. During a write, the write check bits appear. In slave 8206's the
partial parity bits used by the master appe~ at these outputs. The syndrome is
latched (during read-modify-writes) by R/W going low.

PPIO/POSo
PPI1/POS1

13
14

I
I

Partial Parity In/Position: In the master in a multi-8206 system, these inputs
accept partial parity bits 0 and 1 from the slaves. In a slave 8206 these inputs inform it of its position within the system (1 to 4). Not used in a single 8206
system.

PPI2/NSLO
PPI3/NSL1

15
16

I
I

Partial Parity In/Number of Slaves: In the master in a multi-8206 system, these
inputs accept partial parity bits 2 and 3 from the slaves. In a multi-8206 system
these inputs are used in slave number 1 to tell it the total number of slaves in the
system (1 to 4). Not used in other slaves or in a single 8206 system.

PPI4/CE

17

I/O

Partial Parity In/Correctable Error: In the master in a multi-8206 system this
pin accepts partial parity bit 4. In slave number 1 only, or in a sin*e 8206
system, this pin outputs the correctable error flag. CE is latched by R going
low. Not used in other slaves.

PPI5
PPls
PPI7

18
19
20

I
I
I

Partial Parity In: In the master in a multi-8206 system these pins accept partial
parity bits 5 to 7. The number of partial parity bits equals the number of check
bits. Not used in single 8206 systems or in slaves.

ERROR

22

0

Error: This pin outputs the error flag in l!.§ingle 8206 system or in the master of
a multi-8206 system. It is latched by R/w going low. Not used in slaves.

CRCT

52

I

Correct: When low this pin causes data correction during a read or readmodify-write cycle. When high, it causes error correction to be disabled,
although error checking is still enabled.

STB

2

I

Strobe: STB is an input control used to strobe data at the 01 inputs and checkbits at the CBI/SYI inputs. The signal is active high to admit the inputs. The
signals are latched by the high-to-Iow transition of STB.

BMo
BM1

33
32

I
I

Byte MarkS: When high, the Data Out pins are enabled for a read cycle. When
low, th~ata Out buffers are tristated for a write cycle. BMo controls 000_7,
while BM1 controls 008-15. In partial (byte) writes, the byte mark input is low
for the new byte to be written.

R/W

21

I

Read/Write: When high this pin causes the 8206 to perform detection and
correction (if CRCT is low). When low, it causes the 8206 to generate check bits.
On the high-to-Iow transition the syndrome is latched internally for read.modify-write cycles.

WZ

34

I

Write Zero: When low this input overrides the BMO-1 and R/W inputs to cause
the 8206 to output all zeros at 000-15 with the corresponding check bits at
CBOO_7. Used for memory initialization.

M/S

4

I

Master/Slave: Input tells the 8206 whether it is a master (high) or a slave (low).

SEOCU

3

I

Single EDC Unit: Input tells the master whether it is operating as a single 8206
(low) or as the master in a multi-8206 system (high). Not used in slaves.

Vee

60

I

Power Supply: +5V

Vss

26

I

Logic Ground

Vss

43

I

Output Driver Ground

-

---

------

6-32

--

----

--

._-

---

-----

205220-007

8206

Table 2. 8206-2 Pin Description Differences over the 8206.
Pin

Type

Name and Function

5-10

I

Check Bits In: In an 8206-2 system. these inputs accept the check bits (5
to 6) from the RAM.

SYO/CBOo
SYO/CB0 1
SYOICB02
SYO/CB0 3
SYO/CB0 4
SYO/CBOs

23
24
25
27
28
29

0
0
0
0
0
0

Syndrome Out/Check Bits Out: In an 8206-2 system, the syndrome
appears at these outputs during a read. During a write, the write check
bits appear. The syndrome is latched (during read-modify·writes) by R/W
going low.

CE

17

0

Correctable Error: In an 8206-~system, this pin outputs the correctable
error flag. CE is latched by R/W going low.

WZ

34

I

Write Zero: When low this input overrides the BMo_1 and R/W inputs to
cause the 8206-2 to output all zeros at 000-15 with the corresponding check
. bits at CBOo;s. Used for memory initialization.

Strap High

4

I

Must be tied High.

Strap Low

3

I

Must be tied Low.

N.C.

11-16
18-20

I

Note: These pins have internal pull-up resistors but if possible should be
tied high or low.

N.C.

30,31

0

Note: These are no connect pins and should be left open.

Symbol
CBlo-s

FUNCTIONAL DESCRIPTION
DATA WORD BITS
The 8206 Error Detection and Correction Unit
provides greater memory system reliability through
its ability to detect and correct memory errors. It is a
single chip device that can detect and correct all
single bit errors and detect all double bit and some
higher multiple bit errors. Some other odd multiple
bit errors (e.g., 5 bits in error) are interpreted as
single bit errors, and the CE flag is raised. While
some even multiple bit errors (e.g., 4 bits in error) are
interpreted as no error, most are detected as double
bit errors. This error handling is a function of the
number of check bits used by the 8206 (see Figure 2)
and the specific Hamming code used. Errors in
check bits are not distinguished from errors in a
word.
For more information on error correction codes, see
Intel Application Notes AP-46 and AP-73.

CHECK BITS

8

5

16

6

24

6

32

7

40

7

48

8

56

8

64

8

72

8

80

8

Figure 3. Number of Check Bits Used by 8206

A single 8206 or 8206-2 handles 8 or 16 bits of data, and
up to 5 8206's can be cascaded in order to handle data
paths of 80 bits. For a single 8206 8 bit system, the
01 8- 15, DOIWDI8-1S and BM1 inputs are grounded. See
the Multi-Chip systems section for information on
24-80 bit systems.

one to accept data from the RAM (DI) and the other
to deliver corrected data to the system bus (DOl
WDI). The logic is entirely combinatorial during a
read cycle. This is in contrast to an architecture with
only one bus, with bidirectional bus drivers that
must first read the data and then be turned around to
output the corrected data. The latter architecture
typically requires additional hardware (latches
andlor transceivers) and may be slower in a system
due to timing skews of control signals.

The 8206 has a "flow through" architecture. It supports two kinds of error correction architecture: 1)
Flow-through, or correct-always; and 2) Parallel, or
check-only. There are two separate 16-pin busses,
6-33

205220-007

inter
READ CYCLE
With the RiW pin high, data is received from the RAM
outputs.into the 01 pins where it is optionally latched
by the STB signal. Check bits are generated from the
data bits and compared to the check bits read from
the RAM into the CBI pins. If an error is detected the
ERROR flag is activated and the correctable error
flag (CE) is used to inform the system whether the
error was correctable or not. With the BM inputs
high, the word appears corrected.at the DO pins if
the error was correctable, or unmodified if the error
was uncorrectable.
.
If more than one 8206 is being used, then the check
bits are read by the master. The slaves generate a
partial parity output (PPO) and pass it to the master.
The master 8206 then generates and returns the
syndrome to the slaves (SYO) for correction of the
data.
The 8206 may alternatively be used in a "checkonly" mode with the eRe'i' pin left high. With the
correction facility turned off, the propagation delay
from memory outputs to 8206 outputs is significantly shortened. In this mode the 8206 issues an
ERRORflag to the CPU, which can then perform one
of several options: lengthen the current cyCle for
correction, restart the instruction, perform a diagnostic routine, etc.
A syndrome word, five to eight bits in length and
containing all necessary information about the existence and location of an error, is made available to
the system at the SYOO-7 pins. Error logging may be
accomplished by latching the syndrome and the
memory address of the word in error.

WRITE CYCLE

8206

with the syndrome internally latched by RiW going
low. Only that part of the word not to be modified is
output onto the DO pins, as controlled by the Byte
Mark inputs. That portion of the word to be overwritten is supplied by the system bus. The 8206 then
calculates check bits for the new word, using the
byte from the previous read and the new byte from
the system bus, and writes them to the memory.

READ-MODIFY-WRITE CYCLES
Upon detection of an error the 8206 may be used to
correct the bit in error in memory. This reduces the
probability of getting multiple-bit errors in subsequent read cycles. This correction is handled by
executing read-modify-write cycles.
The read-modify-write cycle is controlled by the RNi
input. After (during) the read cycle, the system
dynamic RAM controller or CPU examines the 8206
ERROR and CE outputs to determine if a correctable
error occurred. If it did, the dynamic RAM controller
or CPU forces R/W low, telling the 8206 to latch the
generated syndrome and drive the corrected check
bits onto the CBO outputs. The corrected data .is
available on the DO pins. The DRAM controller then
writes the corrected data'and corresponding check
bits into memory.
The 8206 may be used to perform read-modifywrites in one or two RAM cycles. If it is done in two
cycles, the 8206 latches are used to hold the data
and check bits from the read cycle to be used in the
following write cycle. The Intel 8207 Advanced
Dynamic RAM controller allows read-modify-write
cycles in one memory cycle. See the System
Environment section.

For a full write, in which an entire word is written to
memory, the data is written directly to the RAM,
bypassing the 8206. The same data enters the 8206
through the WDI pins where check bits are generated. The Byte Mark inputs must be low to tristate
the DO drivers. The check bits, 5 to 8 in number, are
then written to the RAM through the CBO pins for
storage along with the data word. In a multi~chip
system, the master writes the check bits using par~
tial parity information from the slaves.

INITIALIZATION
A memory system operating with ECC requires some
form of initialization at system power-up in order to
set valid data and check bit information in memory.
The 8206 supports memory initialization by the write
zero function. By activating the WZ pin, the 8206 will
write a data pattern of zeros and the associated
check bits in the current write cycle. By thus writing
to all memory at power-up, a controller can set
memory to valid data and check bits. Massive memory failure, as signified by both data and check bits
all ones or zeros, will be detected as an uncorrectable error.

In a partial write, part of the data word is overwritten,
and part is retained in memory. Thisis accomplished
by performing a read-modify-write cycle. The complete old word is read into the 8206 and corrected,

6-34

AFN·020098

intJ

8206

the syndrome. The syndrome is then returned by the
master to the slave for error correction. In systems
with more than one slave the above description continues to apply, except that the partial parity outputs
of the slaves must be XOR'd externally. Figure 4
shows the necessary external logic for multi-chip
systems. Write and read-modify-write cycles are carried out analogously. See the System Operation section for mUlti-chip wiring diagrams.

MULTI·CHIP SYSTEMS
A single 8206 handles 8 or 16 bits of data and 5 or 6
check bits, respectively. Up to 5 8206's can be cascaded for 80 bit memories with 8 check bits.
When cascaded, one 8206 operates as a master, and
all others as slaves. As an example, during a read
cycle in a 32 bit system with one master and one
slave, the slave calculates parity on its portion of the
word-"partial parity"-and presents it to the master through the PPO pins. The master combines the
partial parity from the slave with the parity it calculated from its own portion of the word to generate

There are several pins used to define whether the
8206 will operate as a master or a slave. Tables 3 and
4 illustrate how these pins are tied.

3a. 48 BIT SYSTEM

SLAVE 2

PPO

3b. 64 BIT SYSTEM

SLAVE 3

PPO

3e. 80 BIT SYSTEM

SLAVE 4

PPO

Figure 4. External Logic For Mult-Chlp Systems

6-35

205220~007

8206

Table 3. Master/Slave Pin Assignments
Pin No.
4
3
13
14
15
16

Slave 3

Slave 4

Gnd

Gnd,

Gnd

Gnd

+5V

+5V
+5V

+5V
Gnd

+5V
+5V
+5V
+5V
+5V

Shive 1

Master
+5V
+5V
PPI
PPI
PPI
PPI

Pin Name
MIS
SEOCU
PPlo/POSo
PPl1/POS1
PPI2/NSLo
PPI3/NSLl

Gnd
Gnd

..

Slave 2

+5V
+5V
+5V

Gnd

+5V
+5V

·See Table 3,
NOTE:
Pins 13, 14, lS, 16 have internal pull-up resistors and may be left as N.C. where specified as connecting to +Sv.

Table 4. NSL Pin Assignments for Slave 1
Pin
PPI 2/NSLo
PPI3/NSL1

1
Gnd
Gnd

Number of Slaves
2
+5V

Gnd

Gnd

+5V

The timing specifications for multi-chip systems
must be calculated to take account of the external
XOR gating in 3, 4, and 5-chip systems. Let tXOR be
the delay for a single external TTL XOR gate. Then
the following equations show how to calculate the
relevant timing parameters 'for 2-chip (n=O), 3-chip
(n=1), 4-chip (n=2), and 5-chip (n=2) systems:
Data-in to corrected data-out (read cycle) =
TDVSV + TPVSV + TSVQV + ntXOR
Data-in to error flag (read cycle) =
TDVSV + TPVEV + ntXOR
Data-in to correctable error flag (read cycle) =
TDVSV + TPVSV + TSVCV + ntXOR
Write data to check-bits valid (full write cycle) =
TQVQV + TPVSV + ntXOR
Data-in to check-bits valid (read-mod-write cycle) =
TDVSV + TPVSV + TSVQV + TQVQV + TPVSV +
2ntXOR
Data-in to check-bits valid (non-correcting readmodify-write cycle) =
'
TDVQU + TQVQV + TPVSV + ntXOR

3

4
+5V
+5V

parallel. No 8206 requires more time for propagation
through logic levels than any other one, and hence
no one device becomes a bottleneck in the parity
operation. However; one or two levels of external
TTL XOR gates are required in systems with three to
five chips. The code appears in Table 5. The check
bits are derived from the table by XORing or XNORing together the bits indicated by 'X's in each row
corresponding to a check bit. For example, check bit
o in the MASTER for data word 1000110101101011
will be "0." It should be noted that the 8206 will
detect the gross-error condi!ion of all lows or all
highs.
Error correction is accomplished by identifying the
bad bit and inverting it. Table 5 can also be used as
an error syndrome table by replacing the 'X's with
'1's. Each column then represents a different syndrome word, and by locating the column corresponding to a particular syndrome the bit to be corrected may be identified. If the syndrome cannot be
located then the error cannot be corrected. For
example, if the syndrome word is 00110111, the bit
to be corrected is bit 5 in the slave one data word (bit
21).
The syndrome decoding is also summarized in Tables 6
and 7 which can be used for error logging. By finding
the appropriate syndrome word (starting with bit zero"
the least significant bit), the result is either: 1) no error;
2) an identified (correctable)' single bit error; 3) a
double bit error; or 4) a multi-bit uncorrectable error.

HAMMING CODE
The 8206 uses a modified Hamming code which was
optimized for multi-chip EDCU systems, The code is
such that partial parity is computed by all 8206's in

6-36

205220-007

cf

Table 5. Modified Hamming Code Check Bit Generation
Check bits are generated by XOR'ing (except for the CBO and CBl data bits, which are XNOR'ed in the Master) the data
bits in the rows corresponding to the check bits. Note there are 6 check bits in a l6-bit system, 7 in a 32-bit system, and
8 in 48-or-more-bit systems.
BYTE NUMBER
BIT NUMBER
CBO=
CB1 =
CHECK CB2 =
CB3 =
BITS
CB4 =
CB5 =
CB6 =
CB7 =
DATA BITS

0
01234567

------- ----------- -------

-

-

x x - - x x x x - - - - x - x -

- - x x x x x - - - - - x x x
- - - - - - - - x x x x x x x x
- - - - - . - - - - - - - - - -

16 BIT OR MASTER

SLAVE #1

4
5
01234567 01234567
xx-x-xx- x - - x - x x-x--x-x -x-xx-x-

-

- x x - x - x x - - x - x - - x -- xxx - ---- x
-- xxxxx--- - - xxx x x x x x x x x - - - - - - - - x x x x x x x x - - - - - - - - x

-

---

- x x x x x X x x

3 3 3 3 3 3 3 3 4 4 4 4 4 444
2 3 4 5 6 789 o 1 2 3 4 5 6 7

SLAVE #2

6
1 234 5 6 7

7
1 2 3 4 5 6 7

XOR
XOR
XOR
XOR
XOR
XOR
XOR

~

8

8
9
OPERATION
1 2 3 4 5 6 7 01234567
x - x, - x x - - x - x x - - x - - x x x - x x - - x x - - x XOR
- x x - x x x x x - - - x - - x x x - x x x - -~ x x XOR

o

x x x x x -

---

-

x x x - - x - x x x - - - x
- x x x - x x x - - x x x x - - x - x x x - - x x -

1 1 1 1 2 2 2 2 22222233
67690 1 2 3 45676901

c.>

-

- - - - -

XNOR
XNOR
XOR
XOR
XOR
XOR
XOR
XOR

2
3
OPERATION
2 345 6 7 01234567
-xxx-xx- - x x - - x XOR

o1

000 0 0 0 0 0 0 0 1 1 1 1 1 1
o 1 2 3 4 567 B 9 0 1 234 5

-J

DATA BITS

1
OPERATION
2 345 6 7

x x - x - x x . x - - x - x - x-x--x-x - x - x x - x -xx-x-xx - - x - x - - x
xxxxx--- x x x - - - - ---xxxxx - - - - - x x x
- - - - - - - - x x x x 1< x x x

cp

BYTE NUMBER
BIT NUMBER
CBO=
CB1 =
CHECK CB2 =
CB3 =
BITS
CB4 =
CB5 =
CB6=
CB7 =

o1

-

o

-

x x x - x x - - x x - - x - - x - - x x - x x - - x x - - - x x x x x - - - - - x x x
- - - x x x x x x x x
x x x x x x x - - - - x x x x x x x x
-

---

-

-----

o

--x - x
- x -- x

x - - x - x x - - x x - - x x x x - - x x x - - x
- x x - - - x x x x x - x - x x x x - x - - - x x x - -xxxx- - - - x - x -

-

- - - - - - x x x x x x x x

4 4 5 5 5 5 5 5 5 5 5 5 666 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7
690 1 234 5 6 7 8 9 0 1 2 3 4 5 6 7 6 9 0 1 2 3 4 5 6 7 8 9

II

SLAVE #3

.

I. I

SLAVE #4

XOR
XOR
XOR
XOR
XOR
XOR

'\§J

2&
Iiiiil
IF

~
~

~

ae1
~

inter

8206

Table 6. 8206 Syndrome Decoding
Syndrome
BII.

7

6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

5
0
0
1
1
0
0

1
1
0
0
1
1
0
0
1
1

4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

1
0
0
0

0 0
1 0
2 0
3 0

0
1
0
0

CBO CBl

N

1
1
0
0

0
0
1
0

1
0
1
0

0
1
1
0

1
1
1
0

0
0
0
1

1
0
0
1

0

CB2

5

0

0

18

CB3

0

6

7

0
0

3

32 BIT
DATA
BUS

0

0

0

1

2

0

16

4

0
0

17

I

CBS

11

19

12

0
0

8

9

0
0

10

0
0

0

13

14

0

15

0

0

21

20

0

0

66

0

22

23

CB6

0

0

25

0

26

49

0

0

48

24

0

27

0

0

0
0

52

55

0
0

28

0
0

54

33

34

0
0

0
0

37

38

39

71

44

40

41

0
0

36

77
0
0
U
0

0
0

35

43

6B
0
0

0
0

53

69

0
0

65

64
0
0

0
0

70

31

0
0

51

29

0
0

74

72

56

0
0

73

60

0
0

u

58

0
0

0
0
U

U

57

0

u

u

0

61

0

0

76

0

0

u

0

u

u

u
u

u
u

0
U
0
0

0
0

u
u

u
u

0
0

u
u

0
0

0
0

0

0

u

u

0

0

u

0

u

u

30
CB7

0
0
63
0
78

U

0

45

46

59

75

0
0

79

0

0

62

0

u

u

0

u

0
0
U

0
0
U

u
u

0
0
U

47

0

0
0
U
0

DI

32

42

1
1
1
1

0
1
1
1

0
0

~

~

1
0
1
1

0
0

67

0
50
0
0
U
U
0
0
U
0
U
U
0

SYSTEM ENVIRONMENT
The 8206 interface to a typical 32 bit memory system
is illustrated in Figure 5. For larger systems, the
partial parity bits from slaves two to four must be

DATAMEMDRY
16 BITS

x

0
0
1
1

0
0

CB4

N = No Error
. CBX = Error in Check Bit X
X = Error in Data Bit X
o = Double Bit Error
U = Uncorrectable Multi-Bit Error

OE

1
1
0
1

0
1
0
1

CHECK BITS
7 BITS

DO

DI

DATAMEMDRY
16 BITS

·DO

DI

DO

DO/WDI

DI

"1

C,

V
R

--

I

~
~

~

T

T

!l

I,
DO/wDI

DI

SYOICBO CBI...

SYID-a

PP10-6

CONTROL {
LINES

CIIl:T

PPI7

1ft

CBI,

STB

8206
MASTER

~l

~

Mil

1M,
liM,

rIt---

V--

T+ v--IEDCll

R/W

MARKS

PP00-6

V

Ir

I--

mmIi

POSo

CIIl:T .

POS 1

ViZ

HILo
8206
SLAVE

~~

I-

NSL,

i-

R/W

MIS

I-

liM,

smro

~,

IVI,

STB

PPI5-7

ERROR
SIGNALS

CE

~

+5V

J

Figure 5. 32-81t 8206 System Interface
6-38

20522CHJ07

8206

XOR'ed externally, which calls for one level of XOR
gating for three 8206's and two levels for four or five
8206's.

RAM implementation using the 8206 and 8207. The
8206/8207 combination permits such features as automatic scrubbing (correcting errors in memory during refreSh), extending RAS and CAS timings for
Read-Modify-Writes in single memory cycles, and
automatic memory initialization upon reset. Together these two chips provide a complete dualport, error-corrected dynamic RAM subsystem.

The 8206 is designed for direct connection to the Intel
8207 Advanced Dynamic RAM Controller. The 8207
has the ability to perform dual port memory control,
and Figure 6 illustrates a highly integrated dual port

1

ACKB

ACKB
ADDR
~

CMDfPEA

CAS
WE

CMD/PEB

CMD/PEB

DYNAMIC
RAM

---'\
--,;

32 BITS

-{>o-c

WE
01

CSI DOlcao

th

8207
MUX

AORe
WZ

ADORB

ClK>---- ClK

PSEN

-

CE
eRROR

MUX
CMD/PEA

-

l- i'"

ADDR

ACKA

oBM
R/W

L

PSEL

IL~

LI
CE
R/W

ERLR SYO/ ol/CBI
RfW

ADORA

ACKA

+

7 CHECK BITS

-

cao

PPI

,5V- STB

~

CRCT MASTER

wz
BM

BYTE
MARK

STB

CRCT

8206
SLAVE

-

-5V

WZ

DO/WDI

BM

Q1
lit:

r--"'-

01

PPO

8206

¢'

SYI

DD/WDI

Q
....
V

II r-

DECODER

'---

.11

-

~

L........,

XCVR

STB
LATCH

r-

r-Ro

eEl

PORT A

PORTS

Figure 6. Dual Port RAM Subsystem with 8206/8207 (32-bit bus)

6-39

205220-007

inter

8206

Table. 7. .8206-2 Syndrome Decoding
Syndrome 0

5

Bits
4 3

0

0

1
2

0
0
0

0

N

1
0
0

0
1
0

CBO CB1

1
1
0

0
0
1

1

1

1

D CB2 D

0

0
0

0

0

1

CB3

0

0

0

D

1

2

0

1

0

CB4

0

0

5

0

6

7

0

0

1

1

0

3

0

D

4

D

D

0

1

0

0

CB5

0

0

11

0

0

12

0

1

0

1

0

8

9

D

10

0

0

0

1

1

0

0

13

14

0

15

0

0

0

1

1

1

0

0

0

0

0

D

D

0

N=
CBX =
X=
0=

The 8206-2 handles 8 or 16 bits of data. For 8 bit
.8296-2 systems, the Dls-15, DO/WDls_15 and BM1.inputs are grounded.

1
1

0
1

1
0

The 8206-2 is designed for direct connection to the
Intel 8207-2 Advanced Dynamic RAM Controller. The
8207-2 has the ability to perform dual port memory
control, and Figure 7 illustrates a highly integrated
iAPX 186 RAM implementation using the 8206-2 and
8207-2. The 8206-218207-2 combination permits such
features as automatic scrubbing (correcting errors in
memory during refresh), extending RAS and CAS timings for Read-Modify-Writes in single memory cycles,
and automatic memory initialization upon reset.
Together these two chips provide a complete dual-port;
error-corrected dynamic RAM subsystems.

No Error
Error in Check Bit X
Error in Data Bit X
Double Bit Error

OTHER Ai:K
INPUTS

eLK

AACKi AOo-aRASO-3
000-3

ARDyeLK

Eiilimi 140---1

t - - - - - - - - - - - - 1 PCTLA
t---------~~

11207·2

80188
ERROR 010-15

CB1o_5
~

SlB

+SV

Figure 7. IAPX 186 RAM Correct Always Subsystem with the 8206-2 and the 8207-2

6-40

205221).007

8206

ciously choosing the proper data word to
generate the desired check bits, through
the use of the 8206 Hamming code. To
read out the check bits it is first necessary
to fill the data memory with all zeros,
which may be done by activating WZ and
incrementing memory addresses with WE
to the check bits memory held inactive,
and then performing ordinary reads. The
check bits will then appear directly at the
SYO outputs, with bits CSO and CS1
inverted.

MEMORY BOARD TESTING
The 8206 lends itself to straightforward memory
board testing with a minimum of hardware overhead. The following is a description of four common
test modes and their implementation.
Mode O-Read and write with error correction.
Implementation: This mode is the normal
8206 operating mode.
Mode 1-Read and write data with error correction
disabled to allow test of data memory.
Implementation: This mode is performed
with CRCT deactivated.

Mode 3-Write data, without altering or writing
check bits, to allow the storage of bit
combinations to cause error correction
and detection.
Implementation: This mode is implemented by writing the desired word to
memory with WE to the check bits array
held inactive.

Mode 2-Read and write check bits with error correction disabled to allow test of check bits
memory.
Implementation: Any pattern may be written into the check bits memory by judi-

6-41

205220·007

8206

BonOM

0

0

.0

~

a

~

a

"

TOP

~

"~
"I; "

~

8
wz
BM.

BMi

T

""'[

Y0

7.

01,

SY03

Vee

Vss

~l

JSYO,
SYOo

rnrDii
AI'll
]PPI 7

01,

PP1S

aw !!! Ii
E'l!!l
.,,,"

PIN NO.1 MARK

U>

II

it

U

U

0.

BOTTOM

i~

0

~

a

"

TOP

ci
~
a

6

~

"I; "

wz

ClICT

BMO
BMI
N.C.
N.C.

JVO.
SY03

V's
J

SYO

,
SYO o

rnrDii
AI'll
]

~

PIN NO.1 MARK

o

CD 0>

tii

§~

i

"

I~

II

iii
u

i

u

N.C.

zt.i

NOTE:
The 8206 and 8206-2 is packaged in a 68 pin JEDEC TYPE A hermetic chip carrier

Figure Sa. 8206 and 8206-2 Pinout Diagram

6-42

, 205220·007

inter

8206

CERAMIC PIN GRID ARRAY PACKAGE TYPE A
68-LEAD CERAMIC PIN GRID ARRAY
PACKAGE TYPE A

C

1.165 (29.591) 1.135 (28.829)

PINllD

oooooo@)oo

SWAGED PIN
STANDOFF
(4 PLACES)

.070 TYP.
(1.778)

o@)

@)@)@)@)@)@@@@)
@@

o@) D @ @
o@
@)@)
o@)
@@)
o@)
@)@)
o@)
@)@)
o@)
@)@)
.@@)@)@)@)@)@)@@
@)@)@@)@)@)@)@)@)

1.165 (29.591)
1.135 (28.829)

I

.122 (3.099)

L-[r·09~8;(2;.4~89~);;~;;~~

.140 MAX
''1
(3.556)'--=;=

1

STANDOFFi!!

L.090
(2.286)
.060 (1.524)

PIN GRID ARRAY (PGA) PIN-OUT
TOP VIEW
.~.~.~.~.~.~.~.~.~

-1

-2 '67'65-63'61'59'57-55'53'51

• 50' 49

·.

• 3 • 4

• 48 • 47

• 5 • 6
• 7

'46-45
'44'43

• 9 • 10

• 11 • 12

• 42 • 41

• 13' 14

-40'39

• 15' 16

• 38 • 37

• 17 • 19 • 21 • 23 • 25 • 27 • 29' 31 • 33' 36' 35
• 18 • 20 • 22 • 24 • 26 • 28 • 30' 32' 34

Figure 8b. 8206 Pin Grid Array Package and Pinout Diagram

6-43

205220-007

inter

8206

'NOTE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ......... O°C to 70°C
Storage Temperature ............... -65°C to +150°C
Voltage On Any Pin
With Respect to Ground ............. -0.5V to +7V
Power Dissipation .......................... 1.5 Watts

D,C. CHARACTERISTICS
Symbol

1

VIH

Parameter

1

Unit

270

mA

230

mA

Test Conditions

-0.5

0.8

V

Input High Voltage

2.0

Vcc+
0.5V

V

0.45
0.45

V
V

10l = 8mA
10l = 2.0mA

V
V

10H = -2mA
10H = -O.4mA

Output Low Voltage
-DO
-All Others,

VOH

Output High Voltage
-DO, CBO
-All Other Outputs

2.6
2.4

I/O Leakage Current
-PPI4/CE
-DO/WDI0_15

III

Max.

Input Low Voltage

VOL

IlO

Min.

Power Supply Current
-Single 8206, 8206-2 or
Slave #1
-Master in Multi-Chip
or Slaves #2,3,4

Icc

Vil

(TA = O°C to 70°C, Vcc = 5.0V ± 10%, Vss= GND)

Input Leakage Current___ 2
-PPI0-3. 5-7. CBI6_7, SEDCU
-All Other Input Only Pins

± 20
± 10

/LA
/LA

0.45V .;; VI 10

.;; Vcc

± 20
. ± 10

/LA
/LA

OV.;; VIN .;;VCC

NOTES:
1. SEDCU (pin 3) and MIS (pin 4) are device strapping options and should be tied to Vee orGND. VIH min = Vee -O.5Vand VIL max = 0.5V.
2. PPIO-7 (pins 13-20) and CB16_7 (pins 11. 12) have internal pull-up resistors and if left unconnected will be pulled to Vee.

A.C. TESTING LOAD CIRCUIT

A.C. TESTING INPUT, OUTPUT WAVEFORM

'. ~" >

TEST POINTS

0.45

0.8

<"X=

_~_~:_~s~_~_--,~,

IL.·

0.8

A.C, TESTING; INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC' l' AND OASV FOR
A LOGIC 0." TIMING MEASUREMENTS ARE MADE AT 2.0V FOR A LOGIC 1

AND 0.8V FOR A LOGIC 0

CL INCLUOES JIG CAPACITANCE

6-44

205220-007

8206

A.C. CHARACTERISTICS

(TA = O°C to 70°C. Vee
all times are in nsec.)

= +5V ±

= OV,

10%, VSS

8206-1
Symbol

Parameter

Min.

Max.

= 220,

RL

8206

= 50

pF;

8206-2
Max.

Notes

25

40

4

44

49

44

54

66

1

32

42

46

1

35

42

57

CE Valid from Data/Check Bits In

50

70

76

Corrected Data Valid from Data/Check Bits In

55

67

74

TRHEV

ERROR Valid from R/WI

20

TRHCV

CE Valid from R/WI (Single 8206)

34

TRHQV

Corrected Data Valid from R/WI

TRVSV

SYO/CBO/PPO Valid from R/W

TDVEV

ERROR Valid from Data/Check Bits In

TDVCV
TDVQV

Min.

CL

Max.

Min.

TDVSV

SYO/PPO Valid from Data/Check Bits In

40

55

65

TBHQV

Corrected Data Access Time

35

37

37

TBXQX

Hold Time From Data/Check Bits In

TBLQZ

Corrected Data Float Delay

0

TSHIV

STB High to Data/Check Bits In Valid

30

TIVSL

Data/Check Bits In to STBI Set-up

5

5

5

TSLIX

Data/Check Bits In from STBI Hold

15

25

25

0

0
25

0

1

0
28

30

0

28

30

1
2

TPVEV

ERROR Valid from Partial Parity In

21

30

TPVQV

Corrected Data (Master) from Partial Parity In

46

61

1,3

TPVSV

Syndrome/Check Bits Out from Partial Parity In

32

43

1,3

TSVQV

Corrected Data (Slave) Valid from Syndrome

41

51

3

TSVCV

CE Valid from Syndrome (Slave number 1)

43

48

3

TQVQV

Check Bits/Partial Parity Out from Write Data In

TRHSX

Check Bits/Partial Parity Out from R/W, WZ Hold

0

0

0

TRLSX

Syndrome Out from R/W Hold

0

0

0

TQXQX

Hold Time from Write Data In

0

0

0

TSVRL

Syndrome Out to RIWI Set-up

5

17

TDVRL

Data/Check Bits to R/W Set-up

24

TDVQU

Uncorrected Data Out from Data In

29

44

3,4

64

69

1

1
3

41

39

1

32

38

TTVQV

Corrected Data Out from CRCTI

25

30

33

TWLQL

WZI to Zero Out

25

30

34

TWHQX

Zero Out from WZI Hold

0

0

1

4

0

NOTES:
1. A.C. Test Levels for CBO and DO are 2.4V and 0.8V.
2. TSH1V is required to guarantee output delay timings: TDVEV, TDVCV, TDVQV, T DVSV. TSH1V + T 1VSL guarantees a min STB pulse
width of 35 ns (45 ns for the 8206-8).
3. Not required for 8/16 bit systems
4. 8206 S40037 has three parameters relaxed from full spec 8206: TRHEV = 35ns, TpVEV = 40ns, TWLQL = 40ns.

6-45

205220-007

8206

WAVEFORMS
READ

DO

6-46

205220-007

8206

WAVEFORMS (Continued)
READ-MASTER/SLAVE

STB

7r

t\t---------

1

1

l-lTsHlv

1

I

1

---I't)Z1

R/W _ _

V

I
I

1
1

l:/t

8M _ _---L...I....J.1-:7

II

(

TlVSL

I

H

:

I l......-l
TSLIX I

I

I

I

I

~

f-- TBLQZ----.I

:

C~: ---<~,-Ji'-·---!-i

I

I

I

I

'\L. . . __--1:_ _

-~f

---VAL-ID+-1

::.~~:~:::

i

~y/zvA

. r---;~:;:v~

i

I

-~I

DOIMASTER) _ - . - - - - :

1

I

I

1

I-TPVQv-I

I_TDXQX~
VALID

+---

I

I

-}}-

I

SYIISLAVE)-

:

I

l-TPvsv_1

4L
1

t---

,,----I

I...TSVQV--i

I

-~A//A
r·TPVEV..!

I

~4:

VALID

1!SVCV.I

~I'~~~~~TR~HCV~~~~.~I_ _ _ _

X/////ft//////A

CE _ _ _ _

6-47

VALID

I

~

VALID

~'~~~TR~HE;V~~~·I,LI_ _ _ _ __ _

ERROR _ _ _ _

I

k,

VALID

4

DOISLAVE)_--.!..:

I

1

XII

_~"""'-7A.,....-i-r~-r-.~.,.......r~~j{-tr--VAL-'D

SYOIMASTER)~>V///WW/
I

i

I

I

k'--__
~I
X'--1

205220·007

inter

8206/820E

WAVEFORMS (Continued)
FULL WRITE
!--TRvsv_1
I

I

,
,
,

WI

I
I
I
I
I
I

~I

RIW

I
I
I

~

iiI.l

I

I TBLOZ

,

H

DATA OUT

,
I
I
I
I
I

I
I

I

I

1:

I

Toxoxi

WRITE DATA IN

~

.. ,
,

I
I_TOVOV
I

,
,

~a

SVN

,

I
I

I

I

I

SVOICBO

I TRHSX I

r----+l
. ,

,I

,
,

I

rf

I

I
I

~

DOIWDI

TRLSX

,

X

CB

SVN

FULL WRITE-MASTER/SLAVE
J.---,TRYSV-...-..I
RJW

11·La~ I
I

I

m~:

I:
I

DOIWDI

DATA OUT

r1

I

-------..~

:

I

I

I
I

: 'yRHSX. I
I

:

:

I

,

:

-~TQVQv-------...1

I

.

I
.
I
~!

:

I

I

I

:

SyO/c.O_-:--SYN_ _

TRLSX

-l

I.

I

Taxaxl

p:~~:~::: ---------~:>0:-"74
I--

:

W.

WRITEDATAlN}

-;------'-1---------

k=

..~
TPV'V

• ,

:

-k=

----J~-r-:/h"T7~-r-l~r--c-.
6-48

20522D-007

inter

8206

WAVEFORMS (Continued)
READ MODIFY WRITE

~t

tt,..1
---------,1

TS~'VII4"'------T'vsL---...

-tt-

1-_---TSLIX---+j.1

II

I I

I
I

'{I'-----;-I...JA:
I
1

R/WJ1
, I

14"1'...L.I-----'TDVR,L-L- - -...I_TRVSV---l

!1
8M

X-,
I

::

, 1

1

---!.:-C
1

II

- - - V A - L I D - :- - - . - :

1

j!RHSXII1,lTaL~i

----+-:

-in-:

I - TaHQV ---'

, I

cg:

1

1

1

I 1-

I

--.....;....-----..~

-VAL-'-ID:

TRHQV'--+---l~1

"

1 '
:

:

J iI

:

114.-;-1----'TDVQV--::';::;~~I~_ _ _ _-I-_ _TD_XQ_X_ 1-1

DO/wD'~11 ---~:
1--:

,

I

4 : «~
il-

I ,""I_---TRVSV---~~I

I

M

I

TQXax-!

'-TRLSX

I I I I

syo/cao

1

I

II-'----'TDVSV'---+j.1

I
I
!--TQVQV-!

6-49

I

--PC

----1...1~~,.....-r-Z~Z0..--rZ~Z$'-;"""c:~SYN~~~7"'t7--,
CB

I

I

I

205220-007

8206

WAVEFORMS (Continued).
READ MODIFY WRITE-MASTER/SLAVE

;t

_ _.-J

, ' - - -_ _-...J

'!---TRHSX

I,

'

,

I

J+',
I

I

~R'D7 ~
I
,

I'

:
'i

I
I

DDIWDI
(SLAVE)

,I
,

rTSVRL~TRVSv1

I

VALID

I

II

~"W_RITEL~~'!i---------+_'!1<=
,

"J--TPV~V----'

.

,

:1

.1'

"II

I
,
I

"

I

! ~(

!
I

I I

I ,

I

SYO/CBD(M~/Z(
SYI (SLAVE)

,

, ,

, I

r-TP~s--1
.·1
I I I I

I

I

'
I
!--TBLQZ-r

-I ,

- (IlI ii:rALlD
,
I

.

I-TIVSL

I'

TDVSV-l

I ~TRVSV---;

DDIWDI
(MASTER)

X,------+i

,

, , '

,-,TSHIV'

P:::::::

,

:," ski+,I-------------------+-r
I:

I

,

----l

I

:

~TBHQV-'

,

DI
CBI

,

,

_~
STB,

A

.'{

,

SYN

I

r,

I ,

»i

VALID

:_TPVSV_,

I'

I

I

I

>0?~

CB

'K

I

~TQVQV~
I

~~20~~{----~L1-D--~~

6-50

205220-007

inter

8206

WAVEFORMS (Continued)
NON·CORRECTING READ

CRCT--------------------~~

~

~I_---..J

I

I
I

I
I

I_TTVQV_I

lI

1M=?:
I

I

I

:I (

01

CBI

I

I

I'
I

TWLQL

'i

¢:

I
I
I

I

I

UNCORRECTED

CORRECTED

}

·1

UNCORRECTED

I

I

I

;1I

I

I
I
1- TQVQV ----t
I
I

i

I

I

I

I

I
I"

------------~--------~----------~~
I
I

I

Wi

I_ TBLQZ

Iii )

------------_~

WRITE ZERO

n

I TTVQV I

!-TBHQV---I
DO/WDI

~"I

i
f.>lo--TDVQU--..... 1
I
I

I

~

I
I

I~HQ!I

I
I

I

I

:~

DO@0/#/ftff$~

i

II~

I

x=

1,....-_ _ 1

SYO'CBo~mff~/W~

6-51

VALID

205220-007

8207
DUAL·PORT DYNAMIC RAM CONTROLLER
• Provides All Signals Necessary to
Control 16K, 64K and 256K Dynamic
RAMs
• Directly Addresses and Drives up to 2
Megabytes without External Drivers
• Supports Single and Dual-Port
Configurations
• Automatic RAM Initialization in All
Modes
• Four Programmable Refresh Modes
• Transparent Memory Scrubbing in
ECC Mode

• 80286
Fast cycle
(CFS=1)
8086/186
Slow cycle
(CFS=O)

8 MHz

8207-16

6 MHz
8 MHz

8207-12
8207-8

6 MHz

8207-6

• Provides Signals to Directly Control the
8206 Error Detection and Correction Unit
• Supports Synchronous or
Asynchronous Operation on Either Port

• +5 Volt Only HMOSII Technology for
High Performance and Low Power
• 68 Lead JEDEC Type A Leadless Chip
Carrier (LCC) and Pin Grid Array
(PGA), Both in Ceramic.
See Packaging Specifications, Order #: 231369

The Intel 8207 Advanced Dynamic RAM Controller (ADRC) is a high-performance, systems-oriented,
Dynamic RAM controller that is designed to easily interface 16K, 64K and 256K Dynamic RAMs to I ntel and
other microprocessor systems. A dual-port interface allows two different busses to independently access
memory. When configured with an 8206 Error Detection and Correction Unit the 8207 supplies the necessary
logic for designing large error-corrected memory arrays. This combination provides automatic memory
initialization and transparent memory error scrubbing.

~

PCTLA

P9

RFRQ

.01---11---0-1

aSO.1C===~~
Figure 1. 8207 Block Diagram
Intel Corporation Assumes No Responsibility forthe Use of AnyCircuilry Other Than Clrc'uitry Embodied in an Intel Product. No Other Circuit
Patent Licenses are Implied. Information Contained Herein Supercedes Previously Published Specifications On These Devices From Inlel.
"'INTEL CORPORATION, 1983
JAN. 1986

6-52

ORDER NUMBER: 210463-005

intel·

8207

Table 1. Pin description
Symbol

Pin

Type

Name and Function

LEN

1

0

ADDRESS LATCH ENABLE: In two-port configurations, when Port A is running with iAPX 286 Status
interface mode, this output replaces the ALE signal from the system bus controller of port A and
generates an address latch enable signal which provides optimum setup and hold timing for the 8207.
This signal is used in Fast Cycle operation only.

XACKA/
ACKA

2

0

TRANSFER ACKNOWLEDGE PORTA/ACKNOWLEDGE PORTA: In non-ECC mode, this pin is
XACKA and inidcates that data on the bus is valid during a read cycle or that data may be removed
from the bus during a write cycle for Port A. XACKA is a Multibus-compatible signal. In ECC mode,
this pin is ACKA which can be configured, depending on the programming of th~ogram bit,
as an XACK or AACK strobe. The SA programming bit determines whether the AACK will be an
early EAACKA or a late LAACKA interface signal.

XACKB/
ACKB

3

0

TRANSFER ACKNOWLEDGE PORT B/ACKNOWLEDGE PORT B: In non-ECC mode, this pin
is XACKB and indicates that data on the bus is valid during a read cycle or that data may be removed from the bus during a write cycle for Port B. XACKB is a Multibus-compatible signal. In ECC
mode, this~ ACKB which can be configured, depending on the programming of the X program
bit, as an XACK or AACK strobe. The SB programming bit determines whether the AACK will be
an early EAACKB or a late LAACKB interface signal.

AACKA/
WZ

4

0

ADVANCED ACKNOWLEDGE PORT A/WRITE ZERO: In non-ECC mode, this pin is AACKA
and indicates that the processor may continue processing and that data will be available when required. This signal is optimized for the system by programming the SA program bit for synchronous
or asynchronous operation. In ECC mode, after a RESET, this signal will cause the 8206 to force
the data to all zeros and generate the appropriate check bits.

AACKB/
RiW

5

0

ADVANCED ACKNOWLEDGE PORT B/READ/WRITE: In non-ECC mode, this pin is AACKB and
indicates that the processor may continue processing and that data will be available when required.
This signal is optimized for the system by programming the SB program bit for synchronous or asynchronous operation. In ECC mode, this signal causes the 8206 EOCU to latch the syndrome and
error flags and generate check bits.

OBM

6

0

DISABLE BYTE MARKS: This is an ECC control output signal indicating that a read or refresh cycle is occurring. This output forces the byte address decoding logic to enable all 8206 data output
buffers. In ECC mode, this output is also asserted during memory initialization and the 8-cycle dynamic
RAM wake-up exercise. In non-ECC systems this signal indicates that either a read, refresh or 8-cycle

ESTB

7

0

ERROR STROBE: In ECC mode, this strobe is activated when an error is detected and allows a
negative-edge triggered flip-flop to latch the status of the 8206 EOCU CE for systems with error
logging capabilities. ESTB will not be issued during refresh cycles.

LOCK

8

I

LOCK: This input instructs the 8207 to lock out the port not being serviced at the time LOCK was
issued.

Vcc

9
43

I

DRIVER POWER: +5 Volts. Supplies Vcc for the output drivers.
LOGIC POWER: +5 Volts. Supplies Vcc for the internal logic circuits.

CE

10

I

CORRECTABLE ERROR: This is an ECC input from the 8206 EDCU which instructs the 8207 whether
a detected error is correctable or not. A high input indicates a correctable error. A low input inhibits
the 8207 from activating WE to write the data back into RAM. This should be connected to the CE
output of the 8206.

ERROR

11

I

ERROR: This is an ECC input from the 8206 EOCU and instructs the 8207 that an error was detected.
This pin should be connected to the ERROR output of the 8206.

MUX/
PCLK

12

0

MULTIPLEXER CONTROL/PROGRAMMING CLOCK: Immediately after a RESET this pin is used
to clock serial programming data into the PDI pin. In normal two-port operation, this pin is used
to select memory addresses from the appropriate port. When this signal is high, port A is selected
and when it is low, port B is selected. This signal may change state before the completion of a RAM
cycle, but the RAM address hold time is satisfied.

PSEL

13

0

PORT SELECT: This signal is used to select the appropriate port for data transfer. When this signal
is high port A is selected and when it is low port B is selected.

PSEN

14

0

PORT SELECT ENABLE: This signal used in conjunction with PSEL provides contention-free port
exchange on the data bus. When PSEN is low, port selection is allowed to change state.

WE

15

0

WRITE ENABLE: This signal provides the dynamic RAM array the write enable input for a write
operation.

warm~up

is in progress.

6-53

210463-005

8207

Table 1. Pin Description (Continued)
Symbol

Pin

Type

Name and Function

FWR

16

I

FULL WRITE: This is an ECC input signal that instructs the 8207, in an ECC configuration, whether the present write cycle is normal RAM write (full write) or a RAM partial
write (read-modify-write) cycle.

RESET

17

I

RESET: This signal causes all internal counters and state flip-flops to be reset and upon
release of RESET, data appearing at the POI pin is clocked in by the PCLK output. The
states of the POI, PCTLA, PCTLB and RFRO pins are sampled by RESET going inactive
and are used to program the 8207. An 8-cycle dynamic RAM warm-up is performed after
clocking POI bits into the 8207.

CASO
CAS1
CAS2
CAS3

18
19
20
21

0
0
0
0

COLUMN ADbRESS STROBE: These outputs are used by the dynamic RAM array to
latch the column address, present on the AOO-8 pins. These outputs are selected by
the BSO and BS1 as programmed by program bits RBO arid RB1. These outputs drive
the dynamic RAM array directly and need no external drivers.

RASO
RAS1
RAS2
RAS3

22
23
24
25

0
0
0
0

ROW ADDRESS STROBE: These outputs are used by the dynamic RAM array to latch
the row address, present on the AOO-8 pins. These outputs are selected by the BSO
and BS1 as programmed by program bits RBO and RB1. These outputs drive the
dynamic RAM array directly and need no external drivers.

Vss

26
60

I
I

DRIVER GROUND: Provides a ground for the output drivers.
LOGIC GROUND: Provides a ground for the remainder of the device.

AOO
A01
A02
A03
A04
A05
A06
A07
A08

35
34
33
32
31
30
29
28
27

0
0
0
0
0
0
0
0
0

ADDRESS OUTPUTS: These outputs are designed to provide the row and column
addresses of the selected port to the dynamic RAM array. These outputs drive the
dynamic RAM array directly and need no external drivers'.

BSO
BS1

36
37

I
I

BANK SELECT: These inpulS are used to select one of four banks of the dynamic
RAM array as defined by the program bits RBO and RB1.

ALO
AU
AL2
AL3
AL4
AL5
AL6
AL7
AL8

38
39
40
41
42
44
45
46
47

I
I
I
I
I
I
I
I
I

ADDRESS LOW: These lower-order address inputs are used to generate the row
address for the internal address multiplexer.

AHO
AH1
AH2
AH3
AH4
AH5
AH6
AH7
AH8

48
49
50
51
52
53
54
55
56

I
I
I
I
I
I
I
I
I

ADDRESS HIGH: These higher-order address inputs are used to generate the
column address for the internal address multiplexer.

POI

57

I

PROGRAM DATA INPUT: This input programs the various user-selectable options in the
8207. The PCLK pin shifts programming data into the POI input from optional external
shift registers. This pin may be strapped high or low to a default ECC (POI =Logic "I")
or non-ECC (POI = Logic "0") mode configuration.

RFRO

58

I

REFRESH REQUEST: This input is sampled on the falling edge of RESET. If it is high
at RESET, then the 8207 is programmed for internal refresh request or external refresh
request with failsafe protection. If.it is low at RESET, then the 8207 is programmed for
external refresh without failsafe protection or burst refresh. Once programmed the RFRO
pin accepts signals to start an external refresh with failsafe protection or external refresh
without failsafe protection or a burst refresh.

6-54

210463-005

8207

Table 1. Pin Description (Continued)
Pin

Type

ClK

Symbol

59

I

CLOCK: This input provides the basic timing for sequencing the internal logic.

Name and Function

ROB

61

I

READ FOR PORT B: This pin is the read memory request command input for port B.'
This input also directly accepts the 51 status line from Intel processors.

WRB

62

I

WRITE FOR PORT B: This pin is the write memory request command input for port B.
This input also directly accepts the SO status line from Intel processors.

PEB

63

I

PORT ENABLE FOR PORT B: This pin serves to enable a RAM cycle request for port
B. It is generally decoded from the port address.

PCTlB

64

I

PORT CONTROL FOR PORT B: This pin is sampled on the falling edge of RESET. It
configures port B to accept command inputs or processor status inputs. If low after
RESET, the 8207 is programmed to accept command or iAPX 286 status inputs or
Multibus commands. If high after RESET, the 8207 is programmed to accept status
inputs from iAPX 86 or iAPX 186 processors. The S2 status line should be connected
to this input if programmed to accept iAPX 86 or iAPX 186 status inputs. When
programmed to accept commands or iAPX 286 status, it should be tied low or it may
be used as a Multibus-compatible inhibit signal.

RDA

65

I

READ FOR PORT A: This pin is the read memory request command input for port A.
This input also directly accepts the S1 status line from Intel processors.

WRA

66

I

WRITE FOR PORT A: This pin is the write memory request command input for port A.
This input also directly accepts the SO status line from Intel processors.

PEA

67

I

PORT ENABLE FOR PORT A: This pin serves to enable a RAM cycle request for port
A. It is generally decoded from the port address.

peTlA

68

I

PORT CONTROL FOR PORT A: This pin is sampled on the falling edge of RESET. It
configures port A to accept command inputs or processor status inputs. If low after
RESET, the 8207 is programmed to accept command or iAPX 286 status inputs or
Multibus commands. If high after RESET, the 8207 is programmed to accept status
inputs from iAPX 86 or iAPX 186 processors. The S2 status line should be connected
to this input if programmed to accept iAPX 86 or iAPX 186 status inputs. When
programmed to accept commands or iAPX 286 status, it should be tied low or it may
be connected to INHIBIT when operating with Multibus.

GENERAL DESCRIPTION

FUNCTIONAL DESCRIPTION

The Intel 8207 Advanced Dynamic RAM Controller
(ADRC) is a microcomputer peripheral device which
provides the necessary signals to address, refresh
and directly drive 16K, 64K and 256K dynamic RAMs.
This controller also provides the necessary arbitration circuitry to support dual-port access of the
dynamic RAM array.

Processor Interface
The 8207 has control circuitry for two ports each
capable of supporting one of several possible bus
structures. The ports are independently configurable allowing the dynamic RAM to serve as an interface between two different bus structures.

The ADRC supports several microprocessor interface
options including synchronous and asynchronous connection to iAPX 86, iAPX 88, iAPX 186, iAPX 188, iAPX
286 and Multibus.

Each port of the 8207 may be programmed to run
synchronous or asynchronous to the processor clock.
(See Synchronous/Asynchronous Mode) The 8207
has been optimized to run synchronously with Intel's
iAPX 86, iAPX 88, iAPX 186, iAPX 188 and iAPX 286.
When the 8207 is programmed to run in asynchronous
mode, the 8207 inserts the necessary synchronization
circuitry for the RD, WR, PE, and PCTl inputs.

This device may be used with the 8206 Error Detection and Correction Unit (EDCU). When used with the
8206, the 8207 is programmed in the Error Checking
and Correction (ECC) mode. In this mode, the 8207
provides all the necessary control signals for the
8206 to perform memory initialization and transparent error scrubbing during refresh.

6-55

210463-005

8207

The 8207 achieves high performance (Le. no wait
states) by decoding the status lines directly from the
iAPX 86, iAPX 88, iAPX 186, iAPX 188 and iAPX 286
processors. The 8207 can also be programmed to
receive read or write Multibus commands or commands
from a bus controller. (See Status/Command Mode)

the iAPX 86,88, 186, 188, or 286. The.8207 adjusts
its internal timing to allow for the different clock
frequencies of these microprocessors. (See
Microprocessor Clock Frequency Option)
Figure 2 shows the different processor interfaces to
the 8207 using the synchronous or asynchronous
mode and status or command interface.

The 8207 may be programmed to accept the clock of

8207

\-------1 All
eLK

1-_ _ _.j\NRCLK
1----.jiiO

:g::~

sa
Sf

52
ADDR.JDATA

Slow-Cycle Asynchronous-Status Interface

Slow-Cycle Synchronous-Status Interface

Slow-Cycle Synchronous-Command Interface

Slow-Cycle Asynchronous-Command Interface

Figure 2A. Slow-cycle (CFS=O) Port Interfaces Supported by the 8207
6-56

210463-005

8207

NOTE:
ADDRESS LATCH NOT REQUIRED IN SINGLE-PORT MODE.

NOTE:
ADDRESS LATCH NOT REQUIRED IN SINGLE-PORT MODE.

Fast-Cycle Synchronous-Status Interface

Fast-Cycle AsynchronOUS-Status Interface

SYNCHRONOUS 80286
·MULTI·BUS OPTION

Fast-Cycle Synchronous-Command Interface

Fast-Cycle Asynchronous-Command Interface

Figure 2B. Fast·cycle (CFS=1) Port Interfaces Supported by the 8207

Single-Port Operation

Dynamic RAM Interface

The use of an address latch with the iAPX 286 status
interface is not needed since the 8207 can internally
latch the addresses with an internal signal similar in
behavior to the LEN output. This operation is active only
in single-port applications when the processor is interfaced to port A.

The 8207 is capable of addressing 16K, 64K and 256K
dynamic RAMs. Figure 4 shows the connection of the
processor address bus to the 8207 using the different RAMs.

Dual-Port Operation
The 8207 provides for two-port operation_ Two independent processors may access memory controlled
by the 8207. The 8207 arbitrates between each of the
processor requests and directs data to or from the
appropriate port. Selection is done on a priority concept that reaSSigns priorities based upon past history. Processor requests are internally queued.

The 8207 divides memory into as many as four banks,
each bank having its own Row (RAS) and Column
- (CAS) Address Strobe pair. This organization permits
RAM cycle interleaving and permits error scrubbing
during ECC refresh cycles_ RAM cycle interleaving
overlaps the start of the next RAM cycle with the RAM
Precharge period of the previous cycle. Hiding the
precharge period of one RAM cycle behind the data
access period of the next RAM cycle optimizes memory
bandwidth and is effective as long as successive RAM
cycles occur in alternate banks.

Figure 3 shows a dual-port configuration with two
iAPX 86 systems interfacing to dynamic RAM. One of
the processor systems is interfaced synchronously
using the status interface and the other is interfaced
asynchronously also using the status interface.

Successive data access to the same bank will cause
the 8207 to wait for the precharge time of the previous
RAM cycle.

6-57

210463-005

P

8284A·
READY ROY 1 ~ OTHERACK INPUTS

MEMORY

MEMORY
(LOWER)

(UPPER)

elK

WE

elK

52

51

WRB

~

80861
80186

O'l

AODR/DATA

PCTlBfROB

8207

RoA
WRA

so

a,

AACKli

PCTlA

J

51

STU
f<:-;>

8283
LATCH

MUX

AHo_sALo.a

WE

01

DO

..- I----l

WE

T

READY elK 52

P

r'-' ;..-...J

elK AACKA AC o•s RAS o_3
CASo-3

SO

DO

rP fill If

I---

ALE
8288" DEN I--

DTtA

01

PSEN PSEl

....STB

,

..-==-

~ :!];~

LATCH

f-- f-

-

~f,!

elK

~

ffi~
:z:

8288*

DEN

OTfAI--ALE

so

51 52

~ rtti
~

so

~
B086I
80186

OE STB

~~
8283

Bl
I.

~~I
........

I.

-r-"

I

I

OE

8283
LATCH

V

~

§

PORT B-ASYNCHRON DUS

STB

8283
LATCH

I---

'--

"@

dQI

I.

Iffij]

C

'---

~

~

o
....,
PORT A-SYNCHRONOUS;

~

-

5TB

ADDRJDATA

EXTENDED MEMORY UISING STATUS.

t..::.~

OE

I.

,

8283

B

BO

READY

52
SI

74LS14

'--

8283

CLK

l'

STB OE

~

CLK

5

l.....-

0>

IQ~'-'

I

74LS74

L }.

t

8284A*

NOTE:
"These components are not necessary when_ using the 80186 components. These functions are provided directly by
the 80186.
Figure 3. 8086/80186 Dual Port System

~
~

~
dQI
~

8207

A12-A20

AHO-AH8

8207

8207

8207

A3-A11

A1,A2

256K RAM INTERFACE

16K RAM INTERFACE

64K RAM INTERFACE

NOTES:
(1) Unassigned address input pins should be strapped high or low.
(2) AO along with BHE are used to select a byte within a processor word.
(3) Low order address bits ,are used as bank select inputs so that consecutive memory access requests
are to alternate banks allowing bank interleaving oT memory cycles.
Figure 4. Processor Address Interface to the 8207 Using 16K, 64K, and 256K RAMS
Table 2.
Bank Selection Decoding and
Word Expansion

If not all RAM banks are occupied, the 8207 reassigns
the RAS and CAS strobes to allow using wider data
words without increasing the loading on the RAS and
CAS drivers. Table 2 shows the bank selection
decoding and the word expansion, including RAS and
CAS assignments. For example, if only two RAM banks
are occupied, then two AAS and two CAS strobes are
activated per bank. Program bits RB1 and RBO are not
used to check the bank select inputs BS1 and BSO. The
system design must protect from accesses to "illegal",
non-existent banks of memory, by deactivating the
PEA, PEB inputs when addressing an illegal bank.

Bank
Program
Bits
Input
RB1 RBO BS1 BSe

RAS/CAS Pair Allocation

0

0

0

0

RASo_3, CASO-3 to Bank 0

0

0

0

1

Illegal

0

0

1

0

Illegal

0

0

1

1

Illegal

0

1

0

0

RASo,1, CASO,1 to Bank 0

0

1

0

1

RAS2 3, CAS2,3 to Bank 1
Illegal

The 8207 can interface to fast or slow RAMs. The
8207 adjusts and optimizes internal timings for
either the fast or slow RAMs as programmed.
(See RAM Speed Option.)

0

1

1

0

0

1

1

1

Illegal

Memory Initialization

1

0

0

0

RASo, CASo to Bank 0

After programming, the 8207 performs eight RAM
"warm-up" cycles to prepare the dynamic RAM for
proper device operation. During "warm-up" some
RAM parameters, such as tRAH, tASC, may not be
met. This causes no harm to the dynamic RAM array. If configured for operation with error correction,
the 8207 and 8206 EDCU will proceed to initialize
all of memory (memory is written with zeros with
corresponding check bits).

1

0

0

1

RAS1 , CAS1 to Bank 1

1

0

1

0

RAS2, CAS2 to Bank 2

1

0

1

1

Illegal

1

1

0

0

RASo, CASo to Bank 0

1

1

0

1

RAS1, CAS1 to Bank 1

1

1

1

0

RAS2, CAS2 to Bank 2

1

1

1

1

RAS3, CAS3 to Bank 3

6-59

210463-005

inter

8207

Because the time to initialize memory is fairly long,
the 8207 may be programmed to skip initialization in
ECC mode. The time required to initialize all of
memory is dependent on the clock cycle time to the
8207 and can be calculated by the following
equation:
eq.1

Figure 6 illustrates the interface required to drive the
CRCT pin of the 8206, in the case that one port (PORT
A) receives an advanced acknowledge (not Multibuscompatible), while the other port (PORT B) receives
XAGK (which is Multibus-compatible).

TINIT = (:t3) TCLCL
if TCLCL

=

Error Scrubbing

125 ns then TINIT = 1 sec.

The 8207/8206 performs error correction during
refresh cycles (error scrubbing). Since the 8207 must
refresh RAM, performing error scrubbing during
refresh allows it to be accomplished without additional performance penalties.

8206 ECC Interface
For operation with Error Checking and Correction
(ECC), the 8207 adjusts its internal timing and
changes some pin functions to optimize performance and provide a clean dual-port memory interface between the 8206 EDCU and memory. The 8207
directly supports a master-only (16-bit word plus 6
check bits)' system. Under extended operation and
reduced clock frequency, the 8207 will support any
ECC master-slave configuration up to 80 data bits,
which is the maximum set by the 8206 EDGU. (See
Extend Option)

Upon detection of a correctable error during refresh,
the RAM refresh cycle is lengthened slightly to permit the 8206 to correct the error and for the corrected
word to be rewritten into memory. Uncorrectable errors detected during scrubbing are ignored.

Refresh

Correctable errors detected during memory read
cycles are corrected immediately and then written
back into memory.
In a synchronous bus environment, EGG system performance has been optimized to enhance processor
throughput, while in an asynchronous bus environ- .
ment (the Multibus), EGG performance has been optimized to get valid data onto the bus as quickly as
possible. Performance optimization, processor
throughput or quick data access may be selected via
the Transfer Acknowledge Option.
The main difference between the two EGC implementations is that, when optimized for processor
throughput, RAM data is always corrected and an
advanced transfer acknowledge is issued at a point
when, by knowing the processor characteristics,
data is guaranteed to be valid by the time the processor needs it.

The 8207 provides an internal refresh interval counter and a refresh address counter to aliow the 8207 to
refresh memory. The 8207 will refresh 128 rows every
2 milliseconds or 256 rows every 4 milliseconds,
which allows all RAM refresh options to be supported. In addition, there exists the ability to refresh
256 row address locations every 2 milliseconds via
the Refresh Period programming option.
The 8207 may be programmed for any of four different
refresh options: Internal refresh only, External refresh
with failsafe protection, External refresh without failsafe
protection, Burst Refresh mode, or no refresh. (See
Refresh Options)
It is possible to decrease the refresh time interval by
10%, 20% or 30%. This option allows the 8207 to
compensate for reduced clock frequencies. Note
that an additional 5% interval shortening is built-in in
all refresh interval options to compensate for clock
variations and non-immediate response to the internally generated refresh request. (See Refresh Period
Options)

When optimized for quick data access, (valid for Multibus) the 8206 is configured in the uncorrecting
mode where the delay associated with error correction circuitry is transparent, and a transfer acknowledge is issued as soon as valid data is known to exist.
If the ERROR flag is activated, then the transfer acknowledge is delayed until after the 8207 has instructed the 8206 to correct the data and the corrected
data becomes available on the bus. Figure 5 illustrates a dual-port ECC system.

External Ref~esh Requests after RESET
External refresh requests are not recognized by the
8207 until after it is finished programming and preparing memory for access. Memory preparation includes 8 RAM cycles to prepare and ensure proper

6-60

210463-005

l

J-

DT/RB

~I

CMD/PEA

ADDR

CMD/PEB

WE

j

DENB

J

ACKB
CMD/PEB
ADDR B

-V

~o~~
f--

0)

~

CMD/PEA

-

V

ADORA
ACKA
DENA

DT/RA -

rV

-{r r-h

1WE

V

wz

ClK

PSEN

ADDR

CE
ERROR
DBM

L

R/W
ACKA

71

L

FWR PSEl

1I

~

Y

•

BYTE
MARK
DECODER

~

rV

BYTE
MARK
lATCH

~~CT
BM

r-

I

l-

WOI/DO

PPO

:::r: Jo---y

G(M

===

;=::=-

XCVR
5l1~E
DT/R

IIJ
7

~

-rc

7

,
CE

'V WR

WR

~a~~RRIDE

-

CRCT

8206

t=:=

PORTA

R/W

R

-

I

II-

ERROR SY/CB 011
R/W
CBI
ECC
PPI
MASTER

STB

,

001
CBI CBO

01

8207

MUX

DYNAMIC
RAM

SYNC

01

QI
~

o.....

ECC
SLAVE
8206

WOI/DO

5~

1
"@

PORTB

:m
M
F
=

~

~

~

~

~
~

:m
Figure 5. Two-Port ECC Implementation Using the 8207 and the 8206

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