1986_Motorola_FAST_and_LS_TTL 1986 Motorola FAST And LS TTL

User Manual: 1986_Motorola_FAST_and_LS_TTL

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Se~e(Cfcuolnl ~lJilformataol11l

fAST/lS
Co O"CIllI it Cha racteristics

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TestOiru SJ

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!FAST lOata Sheets

II

ILS Data Sheets

II

Reiiabiiity Data

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!FAST ANfD lS

Package Information
Including
Surface MOlllll1t

MOTOROLA
FAST AND lS
Prepared by
Technical Information Center

Low Power Schottky (LSTTL) has become the industry standard logic in recent years, replacing
the original 7400 TTL with lower power and higher speeds. In addition to offering the standard
LS TTL circuits, Motorola offers the FAST Schottky and TTL family. Complete specifications for
each ofthese families are provided in data sheet form. Functional selector guides not only provide
an overview of already introduced devices but planned introduction dates of new products.
Motorola reserves the right to make changes to any product herein to improve reliability, function
or design. Motorola does not assume any liability arising out of the application or use of any
product or circuit described herein; neither does it convey any license under its present patent
rights nor the rights of others.

Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does
not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its
patent rights nor the rights of others. Motorola and@areregisteredtrademarksofMotorola,lnc. Motorols, Inc. is an Equal Employment Opportunity/
Affirmative Action Employer.

Series F
©Motorola Inc., 1986
Previous Edition ©1985
"All Rights Reserved"

MOSAIC and

sOle are trademarks of Motorola Inc.

FAST is a trademark of Fairchild Camera and Instrument Corporation.

FAST AND LS TTL DATA

CONTENTS

Page
ALPHA/NUMERICAL INDEX OF DEVICES
CHAPTER 1 - SELECTION INFORMATION, FAST/LS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
CHAPTER 2 - CIRCUIT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Family Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FAST TTL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LS TTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Circuit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-1
2-2
2-2
2-2
2-2
2-3
2-3
2-4
2-4
2-5

CHAPTER 3 - DESIGN CONSIDERATIONS, SYMBOL DEFINITIONS AND TESTING . . . . . . . . . . . . . .
DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Selecting TTL Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Noise Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fan-In and Fan-Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wired-OR Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-1
3-2
3-2
3-2
3-2
3-3
3-4
3-5

~~~~tD~::;;~~it~~~e.

: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
Output Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interconnection Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DEFINITION OF SYMBOLS AND TERMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
~~~

~:~
3-5
3-5
3-6
3-7
3-7

................................................... .... N

AC Switching Parameters and Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TESTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-8
3-10
3-10
3-11

CHAPTER 4 -

FAST DATA SHEETS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

CHAPTER 5 -

LS DATA SHEETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

CHAPTER 6 - RELIABILITY DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High-Reliability Standard Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The "Better" Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
"RAP" Reliability Audit Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CHAPTER 7 -

6-1
6-2
6-4
6-6

PACKAGE INFORMATION INCLUDING SURFACE MOUNT . . . . . . . . . . . . . . . . . . . . 7-1

FAST AND LS TTL DATA

ALPHANUMERIC INDEX OF DEVICES

Description

Device

Page

MC54F/74FOO
MC54F174F02
MC54F174F04
MC54F174F08
MC54F174Fl0

Quad 2-lnput NAND Gate _............................................... _.... 4-2
Quad 2-lnput NOR Gate ...................................................... 4-4
Hex Inverter ........... _...................................................... 4-6
Quad 2-lnput AND Gate ........................... _.......................... 4-8
Triple 3-lnput NAND Gate ................................................ _.... 4-10

MC54F174Fll
MC54F174F20
MC54F174F32
MC54F174F64
MC54F174F74

Triple 3-lnput AND Gate ...................................................... 4-12
Dual4-lnput NAND Gate ...................................................... 4-14
Quad 2-lnput OR Gate ................................................... _.... 4-16
4-2-3-2 Input AND/OR/INVERT/Gate ........................................ .4-18
Dual D Flip-Flop .............................................................. 4-20

MC54F174F86
MC54F174Fl09
MC54F174Fl12
MC54F174Fl13
MC54F/74Fl14

Quad Exclusive/OR Gate ..................................................... 4-23
Dual J-K Flip-Flop w/Preset. ............................................. _.... 4-25
Dual J-K Negative Edge-Triggered Flip-Flop .................................... .4-28
Dual J-K Negative Edge-Triggered Flip-Flop ..................................... 4-31
Dual J-K Negative Edge-Triggered Flip-Flop (with Common Clock and Clears) ..... 4-34

MC54F/74F138
MC54F174F139
MC54F174F148
MC54F174F151
MC54F/74F153

1-of-8 Decoder/Demultiplexer ................................................. 4-37
Dual 1-of-4 Decoder .................... _..................................... 4-40
8-Line to 3-Line Priority Encoder ................................. _............ 4-43
8-lnput Multiplexer ......... _............................................ _... .4-46
Dual 4-lnput Multiplexer ........ _... _......................................... 4-48

MC54F174F157
MC54F/74F158
MC54F /74F160A
MC54F/74F161A
MC54F174F162A

Quad 2-lnput Multiplexer .................................................... .4-51
Quad 2-lnput Multiplexer .................................................... .4-53
Synchronous Presettable BCD Decade Counter (Asynchronous Master Reset) .... .4-55
Synchronous Presettable Binary Counter (Asynchronous Master Reset) .......... .4-59
Synchronous Presettable BCD Decade Counter ................................ .4-55

MC54F/74F163A
MC54F 174F174
MC54F174F175
MC54F174F181
MC54F174F182

Synchronous Presettable Binary Counter ...................................... .4-59
Hex D Flip-Flop, Master Reset ................................................ .4-63
Quad D Flip-Flop ............................................................ .4-66
4-Bit ALU ...................... _............................................ .4-69
Look Ahead Carry Generator .... _........................................ _... .4-74

MC54F/74F190
MC54F174F191
MC54F174F192
MC54F/74F193
MC54F174F194

Up/Down Decade Counter .................................................... 4- 77
Up/Down Binary Counter ..................................................... 4-81
Up/Down Counters with Separate Up/Down Clocks ............................ 4-86
Up/Down Counters with Separate Up/Down Clocks ........................... .4-86
Universal Shift Register ...................................................... .4-89

MC54F174F240
MC54F /74F241
MC54F174F2421243
MC54F174F244
MC54F174F245

Octal
Octal
Quad
Octal
Octal

MC54F174F251
MC54F174F253
MC54F174F257
MC54F174F258
MC54F174F280

8-lnput Multiplexer/3-State ................................................... 4-100
Dual 4-lnput Multiplexer/3-State ............................................. .4-103
Quad 3-lnput Multiplexer/3-State ..................................... _....... 4-106
Quad 2-lnput Multiplexer, Inverting/3-State .................................... 4-109
9-Bit Parity Generator/Checker ................................................ 4-112

MC54F174F283
MC54F174F350
MC54F174F352
MC54F174F353
MC54F174F373

4-Bit Full Adder .............................................................. 4-114
4-Bit Shifter/3-State ......................................................... 4-118
Dual4-lnput Multiplexer ...................................................... 4-122
Dual 4-lnput Multiplexer/3-State .............................................. 4-125
Octal Transparent Latch/3-State .............................................. 4-128

MC54F174F374
MC54F174F378
MC54F174F379
MC54F174F381
MC54F/74F521

Octal D Flip-Flop/3-State ..................................................... 4-131
Parallel D Register, Enable .................................................... 4-134
Quad Parallel Register, Enable ................................................ 4-137
4-Bit ALU .................................................................... 4-140
Octal Comparator ............................................................. 4-145

Buffer/Line Driver/3-State ............................................. .4-92
Buffer/Line Driver/3-State .............................................. 4-92
Bus Transceivers ....................................................... 4-95
Buffer/Line Driver /3-State .............................................. 4-92
Bidirectional Transceiver/3-State ....... _................................. 4-98

FAST AND LS TTL DATA

ii

ALPHANUMERIC INDEX OF DEVICES (Continued)

Description

Device

Page

MC54F174F533
MC54F174F534
MC74F2960
MC74F2968
MC74F2969

Octal Transparent Latch/3-State ............................................. .4-148
Octal D Flip-Flop/3-State ..................................................... 4-150
Error Detection and Correction Circuit. ........................................ .4-153
Dynamic Memory Controller ................................................... 4-157
Dynamic Memory Timing Controllers ........................................... 4-157

MC74F2970
MC6883
SN54LS174LSOO
SN54LS/74LS01
SN54LS174LS02

Dynamic Memory Timing Controllers ........................................... 4-157
Synchronous Address Multiplexer ............................................. 5-366
Quad 2-lnput NAND Gate ..................................................... 5-2
Quad 2-lnput NAND Gate, Open-Collector ...................................... 5-3
Quad 2-lnput NOR Gate .............................................•........ 5-4

SN54LS174LS03
SN54LS/74LS04
SN54LS/74LS05
SN54LS174LS08
SN54LS174LS09

Quad 2-lnput NAND Gate, Open-Collector ...................................... 5-5
Hex Inverter ...........••..........•.............••.••.............••.....•... 5-6
Hex Inverter, Open-Collector ..••...•.........••..•...........•................ 5-7
Quad 2-lnput AND Gate ...................................................... 5-8
Quad 2-lnput AND Gate, Open Collector .....•...........••.................... 5-9

SN54LS174LS 10
SN54LS174LS11
SN54LS174LS12
SN54LS174LS 13
SN54LS174LS 14

Triple 3-lnput NAND Gate ..................................................... 5-10
Triple 3-lnput AND Gate ...................................................... 5-11
Triple 3-lnput NAND Gate, Open-Collector ...................................... 5-12
Dual 4-Dual Schmitt Trigger ................................................... 5-13
Hex Schmitt Trigger .•..............•.......•...........•.................•... 5-13

SN54LS174LS 15
SN54LS174LS20
SN54LS174LS21
SN54LS174LS22
SN54LS174LS26

Triple 3-lnput AND Gate, Open-Collector ....................................... 5-16
Dual 4-lnput NAND Gate ...................................................... 5-17
Dual 4-lnput AND Gate ....•...............•...................•...•....•.•... 5-18
Dual4-lnput NAND Gate, Open-Collector ...................................... 5-19
Quad 2-lnput NAND Buffer, Open-Collector .............................•....•. 5-20

SN54LS174LS27
SN54LS174LS28
SN54LS174LS30
SN54LS174LS32
SN54LS174LS33

Triple 3-lnput NOR Gate ...................................................... 5-21
Quad 2-lnput NOR Buffer ..................................................... 5-22
8-lnput NAND Gate ........................................................... 5-23
Quad 2-lnput OR Gate .•......•....•........••...........••.•................. 5-24
Quad 2-lnput NOR Buffer, Open-Collector ...................................... 5-25

SN54LS174LS37
SN54LS174LS38
SN54LS174LS40
SN54LS174LS42
SN54LS174LS47

Quad 2-lnput NAND Buffer .................................................... 5-26
Quad 2-lnput NAND Buffer, Open-Collector ...........•.........••..•..••...... 5-27
Dual 4-lnput NAND Buffer ....•..••.•...................•..............•...... 5-28
1-of-10 Decoder .............................................................. 5-29
BCD to 7-Segment Decoder/Driver, Open-Collector ...........•..••..•.......... 5-32

SN54LS174LS48
SN54LS174LS49
SN54LS174LS51
SN54LS174LS54
SN54LS174LS55

BCD to 7-Segment Decoder/Driver ..................•..............••••....... 5-35
BCD to 7-Segment Decoder/Driver, Open-Collector .................•........... 5-35
Dual AND-OR-INVERT Gate ..........••.............•.••.•.......•.••......... 5-39
3-2-2-3-lnput AND-OR-INVERT Gate ........................................... 5-40
2-Wide 4-lnput AND-OR-INVERT Gate ......................................... 5-41

SN54LS174LS73A
SN54LS174LS74A
SN54LS174LS75
SN54LS174LS76A
SN54LSI74LS77

Dual J-K Flip-Flop .•...•..••..•..............•...•..•........•................ 5-42
Dual D Flip-Flop ..••......••.............•......•.................••.......... 5-45
4-Bit Bi-Stable Latch with Q and Q ............................................ 5-48
Dual J-K Flip-Flop ............................................................ 5-52
4-Bit Bi-Stable Latch with Q .................................................. 5-48

SN54LS174LS78A
SN54LS174LS83A
SN54LS174LS85
SN54LS174LS86
SN54LS174LS90

Dual J-K Flip-Flop ............................................................ 5-54
4-Bit Full Adder ...............•...•.....••....•••..•......•...•....•.••..••.. 5-56
4-Bit Magnitude Comparator .•.••...•........•.•.••.....•..•..............•••. 5-59
Quad Exclusive OR Gate .......•••••.......................•...............•.. 5-63
Decade Counter .............................................................. 5-64

SN54LS/74LS91
SN54LS174LS92
SN54LS174LS93
SN54LS174LS95B
SN54LS174LS107A

8-Bit Shift Register ..•............•....•..............•.•••.................•. 5-70
Divide-by-12 Counter ......................................................... 5-64
4-Bit Binary Counter .....•.............•..............•..........•.•....•..... 5-64
4-Bit Shift Register .............•.•....•...•..........•.•..........•....•...•. 5-72
Dual J-K Flip-Flop ..••......•....•......•..•....................•..•.......... 5-76

FAST AND LS TTL DATA

iii

ALPHANUMERIC INDEX OF DEVICES (Continued)

Device

Description

Page

SN54LS174LS109A
SN54LS174LSl12A
SN54LS174LSl13A
SN54LS174LSl14A
SN54LS174LS122

Dual J-K Edge-Triggered Flip-Flop ............................................. 5-78
Dual J-K Edge-Triggered Flip-Flop ............................................. 5-80
Dual J-K Edge-Triggered Flip-Flop ............................................. 5-82
Dual J-K Edge-Triggered Flip-Flop ............................................. 5-84
Retriggerable Monostable Multivibrator ........................................ 5-86

SN54LS/74LS 123
SN54LS174LS 125A
SN54LS174LS126A
SN54LS174LS132
SN54LS174LS133

Retriggerable Monostable Multivibrator ........................................ 5-86
Quad 3-State Buffer, Low Enable .............................................. 5-93
Quad 3-State Buffer, High Enable ............................................. 5-93
Quad 2-lnput Schmitt Trigger .............•................................... 5-95
13-lnput NAND Gate ......................................................... 5-98

SN54LS174LS137
SN54LS/74LS138
SN54LS174LS139
SN54LS/74LS145
SN54LS/74LS147

3-Line to 8-Line Decoder/Demultiplexer ....................................... 5-100
1-of-8 Decoder/Demultiplexer ................................................. 5-102
Dual 1-of-4 Decoder/Demultiplexer ............................................ 5-105
l-of-l 0 Decoder/Driver, Open-Collector ........................................ 5-108
1O-Input to 4-Line Priority Encoder ............................................ 5-111

SN54LS174LS148
SN54LS/74LS151
SN54LS174LS 153
SN54LS174LS155
SN54LS174LS156

8-lnpllt to 3-Line Priority Encoder .............................................. 5-111
8-lnput Multiplexer ........................................................... 5-115
Dual 4-lnput Multiplexer ...................................................... 5-118
Dual 1-of-4 Decoder/Demultiplexer ............................................ 5-121
Dual 1-of-4 Decoder/Demultiplexer, Open-Collector ............................ 5-121

SN54LS174LS157
SN54LS174LS158
SN54LS/74LS160A
SN54LS174LS161A
SN54LS174LS162A

Quad 2-lnput Multiplexer, Noninverting ........................................ 5-125
Quad 2-lnput Multiplexer, Inverting ............................................ 5-128
BCD Decade Counter, Asynchronous Reset (9310 Type) ......................... 5-131
4-Bit Binary Counter, Asynchronous Reset (9316 Type) .......................... 5-131
BCD Decade Counter, Synchronous Reset ...................................... 5-131

SN54LS/74LS163A
SN54LS174LS164
SN54LS174LS165
SN54LS174LS166
SN54LS174LS168

4-Bit Binary Counter, Synchronous Reset ...................................... 5-131
8-Bit Shift Register, Serial-In/Parallel Out ..................................... 5-136
8-Bit Shift Register, Parallel-In/Serial Out ..................................... 5-139
8-Bit Shift Register, Parallel-In/Serial Out ..................................... 5-142
BCD Decade (Module Bi-Directional Counters) .................................. 5-146

SN54LS174LS169
SN54LS174LS170
SN54LS174LS173A
SN54LS174LS 174
SN54LS/74LS175

BCD Decade (Module Bi-Directional Counters) .................................. 5-146
4 X 4 Register File, Open-Collector ............................................ 5-151
4-Bit Type Register, 3-State ................................................... 5-155
Hex D-Type Flip-Flop with Clear ............................................... 5-158
Quad D-Type Flip-Flop with Clear .............................................. 5-161

SN54LS/74LS181
SN54LS/74LS182
SN54LS174LS183
SN54LS174LS190
SN54LS174LS191

4-Bit ALU .................................................................... 5-164
Carry Lookahead Generator ................................................... 5-170
Dual Carry-Save Full Adder ................................................... 5-174
Up/Down Decade Counter .................................................... 5-176
Up/Down Binary Counter ..................................................... 5-176

SN54LS174LS192
SN54LS174LS193
SN54LS174LS194A
SN54LS174LS195A
SN54LS/74LS196

Up/Down Decade Counter .................................................... 5-183
Up/Down Binary Counter ..................................................... 5-183
4-Bit Right/Left Shift Register ................................................. 5-189
4-Bit Shift Register (9300 Type) .: ............................................. 5-193
Decade Counter .............................................................. 5-197

SN54LS/74LS197
SN54LS174LS221
SN54LS/74LS240
SN54LS/74LS241
SN54LS174LS242

4-Bit Binary Counter .......................................................... 5-197
Dual Monostable Multivibrator ................................................ 5-203
Octal Inverting Bus/Line Driver ............................................... 5-208
Octal Bus Line Driver ......................................................... 5-208
Quad Bus Transceiver, Inverting ............................................... 5-211

SN54LS174LS243
SN54LS174LS244
SN54LS174LS245
SN54LS174LS247
SN54LS/74LS248

Quad Bus Transceiver, Noninverting ........................................... 5-211
Octal 3-State Driver, Noninverting ............................................. 5-208
Octal Bus Transceiver, Noninverting ........................................... 5-214
BCD to 7-Segment Decoder/Driver, Open-Collector ............................. 5-216
BCD to 7-Segment Decoder/Driver ............................................ 5-216

FAST AND LS TTL DATA

iv

ALPHANUMERIC INDEX OF DEVICES (Continued)

Device

Description

Page

SN54LS174LS249
SN54LS174LS253
SN54LS174LS256
SN54LS174LS257 A
SN54LS174LS258A

BCD to 7-Segment Decoder/Driver, Open-Collector, ............................ 5-216
Dual 4-lnput Multiplexer, 3-State .............................................. 5-226
Dual4-Bit Addressable Latch .................................................. 5-229
Quad 2-lnput Multiplexer, 3-State ............................................. 5-233
Quad 2-lnput Multiplexer, 3-State ............................................. 5-233

SN54LS174LS259
SN54LS174LS260
SN54LS/74LS266
SN54LS174LS273
SN54LS174LS279

8-Bit Addressable Latch (9334) ................................................ 5-236
Dual 5-lnput NOR Gate ....................................................... 5-240
Quad Exclusive NOR Gate, Open-Collector ..................................... 5-241
Octal D-Type Flip-Flop with Clear .............................................. 5-242
Quad Set-Reset Latch ........................................................ 5-245

SN54LS174LS280
SN54LS174LS283
SN54LS174LS290
SN54LS174LS293
SN54LS/74LS298

9-Bit Odd/Even Parity Generator/Checker ..................................... 5-246
4-Bit Full Adder (Rotated LS83A) .............................................. 5-248
Decade Counter .............................................................. 5-251
4-Bit Binary Counter .......................................................... 5-251
Quad 2-lnput Multiplexer with Output Register ................................. 5-260

SN54LS174LS299
SN54LS174LS322A
SN54LS174LS323
SN54LS/74LS348
SN54LS174LS352

8-Bit Shift/Storage Register, 3-State .......................................... 5-263
B-Bit Shift Register with Sign Extend .......................................... 5-267
8-Bit Universal Shift/Storage Register, 3-State ................................. 5-270
8-lnput to 3-Line Priority Encoder, 3-State ..................................... 5-274
Dual 4-lnput Multiplexer ...................................................... 5-277

SN54LS174LS353
SN54LS174LS365A
SN54LS174LS366A
SN54LS174LS367A
SN54LS174LS368A

Dual4-lnput MUltiplexer, 3-State LS352 ....................................... 5-280
Hex Buffer with Common Enable, 3-State ...................................... 5-284
Hex Inverter with Common Enable, 3-State ..................................... 5-284
Hex Buffer, 4-Bit and 2-Bit, 3-State ............................................ 5-284
Hex-Inverter, 4-Bit and 2-Bit, 3-State .......................................... 5-284

SN54LS174LS373
SN54LS174LS374
SN54LS174LS375
SN54LSI74LS377
SN54LS174LS378

Octal Transparent Latch, 3-State .............................................. 5-286
Octal D-Type Flip-Flop, 3-State ................................................ 5-286
4-Bit Bi-Stable Latch with Q and Q ............................................ 5-291
Octal D-Type Flip-Flop with Enable ............................................ 5-294
Hex D-Type Flip-Flop with Enable .............................................. 5-294

SN54LS174LS379
SN54LS174LS385
SN54LS174LS386
SN54LS174LS390
SN54LS174LS393

4-Bit D-Type Flip-Flop with Enable ............................................. 5-294
Quadruple Serial Adder /Subtractor ............................................ 5-298
Quad Exclusive OR Gate ...•.................................................. 5-301
Dual Decade Counter ......................................................... 5-302
Dual 4-Bit Binary Counter ..................................................... 5-302

SN54LS174LS398
SN54LS174LS399
SN54LS174LS490
SN54LS/74LS540
SN54LS174LS541

Quad 2-lnput Multiplexer with Output Register ............•.................... 5-310
Quad 2-lnput Multiplexer with Output Register ................................. 5-310
Dual Decade Counter ......................................................... 5-313
Octal Inverting Bus/Line Driver ............................................... 5-316
Octal Bus/Line Driver ........................................................ 5-316

SN54LS174LS568
SN54LS174LS569
SN54LS174LS604
SN54LS174LS605
SN54LS174LS606

Decade Up/Down Counter, 3-State ............................................ 5-319
Binary Up/Down Counter, 3-State ............................................. 5-319
1 6-to-8 Multiplexer, 3-State ................................................... 5-324
16-to-8 Multiplexer, Open-Collector ............................................ 5-324
16-to-8 Multiplexer, 3-State ................................................... 5-324

SN54LS174LS607
SN54LS174LS620
SN54LS174LS621
SN54LS174LS622
SN54LS/74LS623

16-to-8 MUltiplexer, Open-Collector ............................................ 5-324
Octal Transceiver with Storage, 3,-State ........................................ 5-327
Octal Transceiver with Storage, Open-Collector ................................. 5-327
Octal Transceiver with Storage, Open-Collector ........................... , ..... 5-327
Octal Transceiver with Storage, 3-State ........................................ 5-327

SN54LS/74LS640
SN54LS/74LS641
SN54LS174LS642
SN54LS174LS643
SN54LS174LS644

Octal
Octal
Octal
Octal
Octal

Bus Transceiver with 3-State Output ..................................... 5-330
Bus Transceiver with 3-State Output ..................................... 5-330
Bus Transceiver with 3-State Output ..................................... 5-330
Bus Transceiver, True, Inverting, 3-State ................................. 5-330
Bus Transceiver, Ture, Inverting, Open-Collector .......................... 5-330

FAST AND LS TTL DATA

v

ALPHANUMERIC INDEX OF DEVICES (Continued)

Device

Description

Page

SN54LS/74LS645
SN54LS/74LS668
SN54LS/74LS669
SN54LS/74LS670
SN54LS174LS673

Octal Bus Transceiver with 3-State Output ........ " ........................... 5-330
Synchronous 4-Bit Up/Down Counters ......................................... 5-333
Synchronous 4-Bit Up/Down Counters ......................................... 5-333
4 X 4 Register File, 3-State " . " " " .. " . " " .. " .. " " " .. " .. " " " . " .. " " 5-337
16-Bit Shift Register, 3-State .. " " . " .. " " " .. " .. " . " ... " .. " " " . " .. " ,,5-341

SN54LS174LS674
SN54LS/74LS682
SN54LS/74LS683
SN54LS174LS684
SN54LS174LS685

16-Bit Shift Register, 3-State. " " . ". " " " " .. " .. ". " ... " .. " " ". " .. ",,5-341
8-Bit Magnitude Comparator, 3-State .......................................... 5-345
8-Bit Magnitude Comparator, Open-Collector ................................... 5-345
8-Bit Magnitude Comparator. 3-State .......................................... 5-345
8-Bit Magnitude Comparator, Open-Collector ................................... 5-345

SN54LS174LS686
SN54LS174LS687
SN54LS174LS688
SN54LS/74LS689
SN54LS/74LS716

8-Bit Magnitude Comparator with Enable, 3-State ............................... 5-345
8-Bit Magnitude Comparator with Enable, Open-Collector ....................... 5-345
8-Bit Magnitude Comparator, 3-State ... " .................. " ................. 5-345
8-Bit Magnitude Comparator, Open-Collector ................................... 5-345
Programmable Decade Counter (MC4016) ...................................... 5-352

SN54LS174LS718
SN54LS174LS748
SN54LS174LS795
SN54LS174LS796
SN54LS174LS797

Programmable Decade Counter (MC4018) ...................................... 5-352
8-lnput to 3-Line Priority Encoder (Glitchless) ................................... 5-111
Octal Buffer (81 LS95), 3-State ................................................ 5-390
Octal Buffer (81 LS96), 3-State ................................................ 5-390
Octal Buffer (81 LS97), 3-State ................................................ 5-390

SN54LS174LS798
SN54LS/74LS848
SN74LS136
SN74LS251
SN74LS295A

Octal Buffer (81 LS98), 3-State .................................•.............. 5-390
8-lnput to 3-Line Priority Encoder, 3-State (Glitchless) .......................... 5-274
Quad Exclusive OR Gate, Open-Collector ....................................... 5-99
8-lnput Multiplexer, 3-State"." .. " " " . " " . " " " . " " " " " " . " " .... " .. 5-222
4-Bit Shift Register, 3-State"."""."."."."""""."""".""" .. " ,,5-256

SN74LS395
SN74LS724
SN74LS783/LS785

4-Bit Shift Register, 3-State ........................................... " ...... 5-306
Voltage Controlled Oscillator .................................................. 5-363
Synchronous Address Multiplexer (MC6883) ................................... 5-366

FAST AND LS TTL DATA

vi

Se~ec1to~11il ~nfolI'matuoD1l
IFASl'/lLS

II'

GENERAL INFORMATION
TTL in Perspective
Since its introduction, TTL has become the most popular form of digital logic. It has evolved from the original
gold-doped saturated 7400 logic, to Schottky-Clamped
logic, and finally to the modern advanced families of
TTL logic. The popularity of these TTL families stem
from their ease of use, low cost, medium-to-high speed
operation, and good output drive capability.
Motorola offers two modern TTL logic families - LS
and FAST". They are pin and functionally compatible
and can easily be combined in a system to achieve maximum performance at minimum cost.
LS (Low Power Schottky) is currently the more popular and commands by far the largest share of the total
TTL logic market. It is low-cost and provides moderate
performance at low power.
FAST, the state-of-the-art, high-performance TTL
family, is growing rapidly and gaining a significant
share of the total TTL logic market. FAST offers a
20-30 percent improvement in performa'nce over the
older Standard Schottky family (74S) with a 75-80 percent reduction in power. When compared with the Advanced Schottky family (74AS), FAST offers nearly
equal performance at a 25-50 percent savings in
power.

FAST is manufactured on Motorola's MOSAIC (oxide-isolated) process. This process provides FAST with
inherent speed/power advantages over the older junction-isolated 74S and 74LS families, allowing the FAST
family to be designed and specified with improved
noise margins, reduced input currents, and superior
line driving capabilities in comparison to these earlier
families. Additionally, FAST designs incorporate
power-down circuitry on all three-state outputs, and
buffered outputs on all storage devices.
Two further advantages of FAST are the load specifications and power supply specifications. FAST ac
characteristics are specified at a heavier capacitive
load than the earlier families (50 pF versus 15 pF) to
more accurately reflect actual in-circuit performance.
Motorola's dc and ac characteristics for FAST are specified over a full 10% supply voltage range - a significant improvement over the industry standard specifications for the earlier families (5% for dc, 0% for ac).
These design and specification improvements offered by the Motorola FAST family provide the user
with better system performance, enhanced design
flexibility, and more reliable system operation.

TTL Family Comparisons
General Characteristics for Schottky TTL Logic
(ALL MAXIMUM RATINGS)

LS

FAST

Characteristic

Symbol

54L5xxx

74LSxxx

54Fxxx

74Fxxx

Units

Operating Voltage Range

vCC

5±10%

5±5%

5±10%

5± 10%

Vdc

-55t0125

o to 70

-55t0125

Oto 70

·C

liN IIH
IlL

20

20

20

20

-400

-400

-600

-600

IOH

-0.4

-0.4

-1.0

-1.0

rnA

IOL

4.0

8.0

20

20

rnA

-60to -150

-60to -150

rnA

Operating Temperature

Range
Input Current

Output Drive
Standard Output

TA

ISC

Buffer Output

-20to -100 -20to -100

p.A

IOH

-12

-15

-12

-15

rnA

IOL

12

24

48

64

rnA

-100to -225

-100 to -225

rnA

ISC

-40to -225 -40to-225

Speed/Power Characteristics for Schottky TTL Logic(1)
(ALL TYPICAL RATINGS)

Characteristic

Symbol

LS

FAST

Quiescent Supply Current/Gate

IG

0.4

1.1

rnA

Power/Gate (Quiescent)

PG

2.0

5.5

rnW

Propagation Delay

to

9.0

3.7

ns

Speed Power Product

-

18

19.2

pJ

Clock Frequency (D-FIFI

f max

33

125

MHz

Clock Frequency (Counterl

f max

40

125

MHz

NOTES: 1. Specifications are shown for the following conditions:
a) VCC = 5.0 Vdc (AC);
bl TA = 25'C
cl CL = 50 pF for FAST; 15 pF for LS

FAST AND LS TTL DATA

1-2

Units

Functional Selection
Abbreviations
5
A
B

= Synchronous
= Asynchronous
= Both Synchronous and Asynchronous

25 = 2-5tate Output
35 = 3-5tate Output
OC = Open-Collector Output
P

= Planned (See FAST/LS Selector Guide, SG-60 for latest

X

availability status)
= Available

Inverters
Description

Hex

II
Exclusive OR Gates

Type of
Output No. LS FAST
2S
OC

04
05

X
X

Description

X

Quad 2·lnput

Type of
Output No. LS FAST
2S
OC
2S

86 X
136 X
386 X

X

AND Gates
Description
Quad 2-lnput
Triple 3·lnput
Dual 4-lnput

Exclusive NOR Gates

Type of
Output No. LS FAST
2S
OC
2S
OC
2S

08
09
11
15
21

X
X
X
X
X

Description

X

Quad 2-lnput

X

AND-OR-INVERT Gates
P
Description

NAND Gates
Description
Quad 2-lnput

Quad 2-lnput, High Voltage
Triple 3-lnput
Dual 4·lnput
a·lnput
13-lnput

Dual 2-Wide, 2·lnput 3-lnput
4-Wide, 2-3-2·3-lnput
2-Wide, 4·lnput
4·Wide, 4-2·2·3-lnput

Type of
Output No. LS FAST
2S
OC
OC
OC
2S
OC
2S
OC
2S
2S

00
01
03
26
10
12
20
22
30
133

X
X
X
X
X
X
X
X
X
X

X

Description
Dual 4-lnput NAND Gate
Hex, Inverting
Quad 2-lnput NAND Gate

X

Description

Dual D w/Set & Clear
Dual JK w/Set
Dual JK wlClear

Quad 2-lnput

NOR Gates
Dual JK w/Set & Clear Individual J,
K, Cp, SD, CD Inputs
Dual JK w/Set & Clear
Common CO, Cp
Same as 76 with Different Pinout
Same as 114 with Different Pinout
Dual JK w/Set & Clear

Type of
Output No. LS FAST
2S
2S
2S

2 X
27 X
260 X

51
54
55
64

X
X
X
X

Type of
Output No. LS FAST
2S
2S
2S

13 X
14 X
132 X

P
P
P

SSI Flip-Flops
Description

Quad 2-lnput
Triple 3-lnput
Dual 5·lnput

2S
2S
2S
2S

Schmitt Triggers
X

OR Gates

Description

Type of
Output No. LS FAST

X

FAST AND LS TTL DATA

1-3

Clock
Edge
Pos
Neg
Neg
Neg
Neg

No. LS FAST
74
113
73
107
76

X
X
X
X
X

Neg

78 X

Neg
Neg
Pas

112 X
114 X
109 X

X
P

P
P
X

Multiplexers
Description
Quad 2-to-l, Non-Inverting
Quad 2-to-l, Inverting
Dual 4-to-l, Non-Inverting
'-

Dual 4-to-l, Inverting
8-to-l
Quad 2-to-l with Output Register
298 - Negative edge triggered
398 - Positive edge triggered,
Q/fi Outputs
399 - Positive edge triggered.
Q Output Only

Decoders/Demultiplexers
Type of
Output No. LS FAST
2S
3S
2S
3S
2S
3S
2S
3S
2S
3S

157
257
158
258
153
253
352
353
151
251

X
X
X
X
X
X
X
X
X
X

Type 01
Output No. LS FAST

Description

Duall-of-4

X
X
X
X
X
X
X
X
X
X

2S
2S
OC
3S
2S
3S
2S
2S
3S

1-01-8
1-01-8 with Latch
1-01-10

2S
2S

298 X
398 X

P
P

X

X

P
X
P

X
X

P

2S

399 X

P

No. 01 Type 01
Bits Output No. LS FAST

Description

4
8
8
8
8
4
4
4
8
4

Transparent, Non-Inverting

Transparent, Inverting

Encoders

10-to-4-Line BCD
8-to-3-Line Priority Encoder

X
X
X

Latches

Octal, Non-Inverting

Description

139
155
156
539
138
538
137
42
537

Type of
Output No. LS FAST
2S
2S
3S
2S
3S

147
148
348
748
848

X
X
X
X
X

Transparent, Q and 0:
Outputs
Quad Set-Reset Latch
Addressable
Dual 4-Bit Addressable

X

77
373
573
533
563
75
375
279
259
256

2S
3S
3S
3S
3S
2S
2S
2S
2S
2S

X
X

X
X
P

X
X
X
X
X

P
P

Register Files
Description
4x4

Type of
Output No. LS FAST
OC
3S

170 X
670 X

Shift Registers
Description
Serial In-Serial Out
Serial In-Parallel Out
Parallel In-Serial Out

Parallel In-Parallel Out

Parallel In-Parallel Out, Bidirectional
Sign Extended Bidirectional
Serial In-Parallel Out with Storage Register
• SR
SL

~
~

Mode"

No. 01
Bits

Type 01
Output

SR

8
8
8
8
16
4
4
4
4
4
8
8
8
16
16

2S
2S
2S
2S
3S
2S
2S
2S
3S
3S
3S
3S
3S
2S/3S
2S

X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

Shift Right
Shift Left

FAST AND LS TTL DATA

1-4

SL

Hold

Reset
A

X
X
X
X

X

X
X

X
X
X
X
X

X

A

A
A
A
A
S
A
S

No.

LS

91
164
165
166
674
95
194
195
295
395
299
323
322
673
675

X
X
X
X
X
X
X
X
X
X
X
X
X
X

FAST
P
P
P

P
P

P
P
P
P

Asynchronous Counters Description

Load

Decade (2/5)

Set Reset No.
X

X
X

Dual Decade (2/5)
Dual Decade
Modulo 12 (2/6)
4-Bit Binary (218)

X

X

Dual 4·Bit Binary
Divide-By-N (0-9)
Divide-By-N (0-15)

Cascadable Synchronous Counters Positive Edge-Triggered

Negative Edge-Triggered

X
X

X
X
X
X
X
X
X
X
X
X
X
X

LS FAST

90
196
290
390
490
92
93
197
293
393
716718-

Type of
Output Load Reset No.

Description

X
X
X
X
X
X
X
X
X
X
X
X

Decade
Decade, Up/Down

4-Bit Binary
4-Bit Binary,
Up/Down

*The 716 and 718 are positive edge-triggered.

Display Decoders/Drivers with Open-Collector Outputs
No.

Description
l-of-l0
BCD-to-7 Segment

*The 48 and 248 have mternal pullup resistors to

145
47
4849
247
248249

LS FAST

25
25
25
25
2S
35
25
25
25
2S
2S
25
35
25

5
5
5
A
A
S
5
5
5
5
A

A
5

A

A

5
5

B

A
B
A
S

160
162
168
190
192568
668
161
163
169
191
193569
669

LS FAST
X
X
X
X
X
X
X
X
X
X
X
X
X
X

X
X

P
P
P
P
X
X

P
P
P
P

*The 192 and 193 do not provide a clock enable for synchronous

cascading.

X
X
X
X
·X
X
X

Vee on their outputs.

MSI Flip-Flops/Registers
Description

No. of
Bits

Type of
Output

Set or
Reset

Clock
Enable

4
4
6
6
8
8
8
8
8
4
4
16
16
16
16

35
25
25
25
25
35
35
35
35
25
25
35
OC
35
OC

A

X

D-Type, Non-Inverting

D-Type, Inverting
D-Type, Q and

0: Outputs

Dual 8·Bit with Multiplexers

FAST AND LS TTL DATA

'-5

X
A
X

A

A
X

No.

LS

173
377
174
378
273
374
574
534
564
175
379
604
605
606
607

X

FAST

X

P

X
X
X
X

X
X

P
X
X

X
X
X
X
X
X

X
X

Arithmetic Operators

Buffers/Line Drivers

Description

No.

LS FAST

4·Bit Adder

83
283
181
381
382
182
385
183
350

X
X
X

4·BitALU

Look Ahead Carry Generator
Quad 4·Bit Adder/Subtractor
Dual Carry/Save Full Adder
4·Bit Barrel Shifter

X
X
X

Description

P
P
P
P

Quad 2·lnput NOR

X

Dual 4-lnput NAND
Quad, Non·lnverting

Quad 2·lnput NAND

P

Hex, Non·lnverting

Magnitude Comparators
Description
4-Bit
8·Bit

Res liP
8·Bit with
Output
Enable

Hex, Inverting

Type of
Output P=Q P>Q P

I-

::::>

1=
::::>

a
...l
a

>

00

20

60

40

50
100
150
200
10L. OUTPUT CURRENT ImAI

10L. - OUTPUT CURRENT -lmAI

FIGURE 2-7b - OUTPUT LOW CHARACTERISTIC

FIGURE 2-70 - OUTPUT LOW CHARACTERISTIC

VCC: 5.5V
TA ~ 25'C

"B

VCC : 5.5V
TA : 25'C

'in
~

~

a
?

w

3.0

w

'"~

'"~

a

>

a

2.0

I-

2.0

>

I-

fE
::::>

::::>

1=
::::>

a
a

>'"

a

1.0

1.0

:I:

~

-150

-50

·200

10H. OUTPUT CURRENT ImAI

10H.OUTPUT CURRENT ImAI

FIGURE 2·8a - OUTPUT HIGH CHARACTERISTIC

FIGURE 2·8b -

OUTPUT HIGH CHARACTERISTIC

AC SWITCHING CHARACTERISTICS. The propagation through a logic element depends on power supply voltage, ambient temperature, and output load. The effect of each of these parameters on ac propagation is shown
in Figures 2-9 through 2-11.
Propagation delays are specified with only one output switching, the delay through a logic-element will increase
to some extent when multiple outputs switch simultaneously due to inductance internal to the IC package. This
effect can be seen by comparing Figures 2-11 e and 2-11 F.
For LS TTL, limits are guaranteed at 25°C, VCC = 5.0 V, and CI = 15 pF (normally, resistive load has minimal
effect on propagation delay) FAST~ and TTL limits are guaranteed over the commercial or military temperature
and supply voltage ranges and with CI = 50 pF.
+4

+4
VCC: 5.0V
CL: 15 pF
LSOO

l!!
I

w

'" +2

~

u

~

c
:z

a

-

r--

~

~

g:

---

I

w

'" +2

~

~

~tPHL

S
~

:z
a

~

1-2

-2

I

I

g

TA: 1+ 25,C
CL : 15pF
LSOO

c

-4
-75

g
-25
+25
+75
TA - AMBIENT TEMPERATURE - 'C

+125

FIGURE 2-9

-4
4.5

4.75
5.0
5.25
VCC - SUPPLY VOLTAGE - V
FIGURE 2-10

FAST AND LS TIL DATA

2-5

5.5

12

20
VCC = 5.0 V
TA = 25'C
LSOO-

~

I 16

:3
UJ

'"Qz

12
tPlY

!;;(

:i
11-

8

-:: ::::::-

0

a:

11-

I

c

J!,-

4

I

tPHl

./

:3

... ...

c

z

0

;:::

«

V

C>

~

~V

0

a:

11-

I

c

100

50

V

V

100 150

200

20

c:

I

:3
UJ

CI
Z

10

~

~

o

g:

v::

V

tPlH

/

./

./

/ V

I
I

~

c:

I

:5
UJ
0

~
C>

10

0
0

a:

11-

I

VCC = 5.0L
TA = 25'C
I F2;tD1500

CI

J!,-

./ /

,/ /

/

-

'VCC = 5.0V
TA = 25'C
F240
Ail OU1Puts, DriVjn-

500
CL LOAD CAPACITANCE - pF

1000

CL LOAD CAPACITANCE - pF

l/

~ /tPHL
//
I

Z

tPHL

~

y

CI

11-

~

300

tPLH/ ~

>-

/'

/'

./

I

250

FIGURE 2-11b*

~

J!,-

~L

CL LOAD CAPACITANCE - pF

20

CI

V

tPlH

J!,-

FIGURE 2-118"

o
~

V

UJ

---

60
80
20
40
CL LOAD CAPACITANCE - pF

II

c:

~:..-- -

......-

VCC = 5.0 V
TA = 25'C
FOO

~

1000

FIGURE 2-11d*

FIGURE 2-11e"

"Data for Figures 2-11a through 2-11c was taken with only one output switching at a time. Figure 2-11d data was taken with
all 8 inputs of the F240 tied together.

FAST AND LS TIL DATA

2-6

DeS09\J1l Consnderatio!l1ls
Cdlndi TestoB1lg

!FAST AND lS

II

DESIGN CONSIDERATIONS

SELECTING TTL LOGIC. TTL Families may be mixed in a system for optimum performance. For instance, in new designs,
ALS would commonly be used in non-critical speed paths to minimize power consumption while FASr" TTL would
be used in high speed paths. The ratio of ALS to FAST~ will depend on overall system design goals.
NOISE IMMUNITY. When mixing TTL families it is often desirable to know the guaranteed noise immunity for both
LOW and HIGH logic levels. Table 3.1 lists the guaranteed logic levels for various TTL families and can be used to
calculate noise margin. Table 3.2 specifies these noise margins for systems containing LS, S, ALS and/or FASr" TTL.
Note that Table 3.2 represents "worst case" limits and assumes a maximum power supply and temperature variation
across the Ie's which are interconnected, as well as maximum rated load. Increased noise immunity can be achieved
by designing with decreased maximum allowable operating ranges.

TABLE 3.1
Worst Case TTL Logic Levels
Electrical Characteristics

II

TTL
HTIL
LPTIL
STIL
LSTIL
ALSTIL (5%
(10%
FAST TTL(5%
(10%

TTL Families
Standard TIL 9000, 54/74
High Speed TIL 54Hn4H
Low Power TIL 93LOO (MSI)
Schottky TIL 54Sn4S, 93S00
Low Power Schottky TIL 54LSn4LS
Vee) Advanced LS TIL, 54ALS/74ALS
Vee)
Vee) Advanced S TTL, 54Fn4F
Vee)

Military (-55 to ±125'C)
VIL
VIH VOL VOH
0.4
0.8
2.0
2.4
0.8
2.0
0.4
2.4
0.7
2.0
0.3
2.4
0.8
2.0
0.5
2.5
0.7
2.0
0.4
2.5
0.8

2.0

0.4

2.5

0.8

2.0

0.5

2.5

Commercial
VIL
VIH
0.8
2.0
0.8
2.0
0.8
2.0
0.8
2.0
0.8
2.0
0.8
2.0
0.8
2.0
0.8
2.0
0.8
2.0

(0 to 70'C)
VOL VOH
0.4
2.4
0.4
2.4
0.3
2.4
0.5
2.7
0.5
2.7
0.5
2.75
0.5
2.5
0.5
2.7
0.5
2.5

UNITS
V
V
V
V
V
V
V
V
V

VOL and VOH are the voltages generated at the output VIL and VIH are the voltage required at the input to generate the
appropriate levels. The numbers given above are guaranteed worst-case values.

TABLE 3.2a
LOW Level Noise Margins (Military)

TABLE 3.2b
HIGH Level Noise Margins (Military)
To
From
LS
S
LS
500
500
S
500
500
ALS
500
500
FASr"
500
500

To
LS
300
200
300
200

From
LS
S
ALS
FASr"

S
400
300
400
300

ALS
400
300
400
300

FAST Units
400
mV
mV
300
400
mV
300
mV

ALS
500
500
500
500

From "VOL" to "VIL"

From "VOH" to "VIH"

TABLE 3.2c
LOW Level Noise Margins (Commercial)

TABLE3.2d
HIGH Level Noise Margins (Commercial)
To
From
LS
S
ALS (5% Vee)
FAST (5% Vee)
ALS (10% Vccl
FAST (10% Vee)

To
From
LS
S
ALS
FASr"

LS
300
300
300
300

S
300
300
300
300

ALS
300
300
300
300

FAST Units
300
mV
mV
300
300
mV
mV
300

From "VOL" to "VIL"

LS
700
700
750
700
500
500

S
700
700
750
700
500
500

ALS
700
700
750
700
500
500

FAST Units
500
mV
mV
500
500
mV
500
mV

FAST Units
700
mV
700
mV
750
mV
700
mV
500
mV
500
mV

From "VOH" to "VIH"
POWER CONSUMPTION. With the exception of EeL, all logic families exhibit increased power consumption at high
frequencies. Figure 3.1 shows this characteristic for common logic families. This figure refers to an average single gate
dissipation, care must be taken when switching multiple gates at high frequencies to assure that their combined
dissipation does not exceed package and/or device capabilities. As indicated, TTL devices are more efficient at high
frequencies than eMOS.

FAST AND LS TIL DATA

3-2

1.0

1

-

lS

,

74HC161

I

,~

,.

AlS

~

,.~
,....,;:

-'L / L

V

.t .1

.!

10K

10KH

I-- HCMOS
Standard 'CMOS

•

fmax tYPICal
- - Avg Gate Power DISSIpatIOn
- - - Circuit DIssipation 01 Specified Part
All loads = 50 pF except ECl. < 5 pF

10'

10'

-

V

~~

)~

5

MEjl III

10K/l0KH"

f--- FAST ""

,

10'

~dlS161

74L\jlA

,

10'

10'

10'

10'

INPUT FREQUENCY (Hzl

FIGURE 3·'
AVERAGE GATE POWER DISSIPATION
versus FREQUENCY

FAN·IN AND FAN-OUT. In order to simplify designing with Motorola TTL devices, the input and output loading parameters of
all families are normalized to the following values:

=

TTL Unit Load (U.L.) 40/lA
in the HIGH state (Logic "1 ")
TTL Unit Load (U,L.) = 1,6 mA
in the LOW state (Logic "0")
Input loading and output drive factors of all products described in this handbook are related to these definitions,
EXAMPLES -INPUT LOAD
1. A 7400 gate, which has a maximum IlL of 1,6 mA and IIH of 40/lA is specified as having an input load factor of 1 U.L. (Also
called a fan·in of 1 load,)
2. The 74LS95B which has a value of IlL
factor of

=O.B mA and IIH of 40/lAon the CPterminal, is specified as having an input LOW load

O.BmA
1,6 mA or 0.5 U,L.

40/lA
40/lA

and an input HIGH load factor of

or 1 U.L

3. The 74LSOO gate which has'an IlL of 0,4 mA and an IIH of 20/lA. has an input LOW load factor of

O.4mA
1,6 mA or 0.25 U.L.

an input HIGH load factor of

20/lA
40/lA

or 0,5 U,L.

EXAMPLES - OUTPUT DRIVE
1. The output of the 7400 will sink 16 mA in the LOW (logic "0") state and source BOO /lA in the HIGH (logic "''') state, The
normalized output LOW drive factor is therefore
16mA
',6mA

= 10U,L,

and the output HIGH drive factor is
BOO/lA
40 uA or 20 U,L.

FAST AND LS TTL DATA

3-3

2. The output ofthe 74LSOO will sink 8.0 mA in the LOW state and source 400pA in the HIGH state. The normalized output LOW
drive factor is
8.0mA
1.6 mA or 5 U.L.
and the output HIGH drive factor is
400pA
40pA or 10 U.L.
Relative load and drive factors for the basic TTL families are given in Table 3.3.

FAMILY
74LSOO
7400
9000
74HOO
74S00
74ALS
74 FAST

II

INPUT LOAD
LOW
HIGH
0.5 U.L.
1 U.L.
1 U.L.
1.25 U.L.
1.25 U.L.
0.5 U.L.
0.5 U.L.

OUTPUT DRIVE
HIGH
LOW

0.25 U.L.
1 U.L.
1 U.L.
1.25 U.L.
1.25 U.L.
0.0625 U.L.
0.375 U.L.

10
20
20
25
25
10
25

U.L.
U.L.
U.L.
U.L.
U.L.
U.L.
U.L.

5 U.L.
10 U.L.
10 U.L.
12.5 U.L.
12.5 U.L.
5 U.L.
12.5 U.L.

TABLE 3.3

Values for MSI devices vary significantly from one element to another. Consult the appropriate data sheet for actual
characteristics.

WIRED-OR APPLICATIONS. Certain TIL devices are provided with an "open" collector output to permit the Wired-OR
(actually Wired-AND) function. This is achieved by connecting open collector outputs together and adding an external pull-up
resistor.

The value of the pull-up resistor is determined by considering the fan-out of the OR tie and the number of devices in the OR tie.
The pull-up resistor value is chosen from a range between maximum value (established to maintain the required VOH with all
the OR tied outputs HIGH) and a minimum value (established so that the OR tie fan-out is not exceeded when only one output is
LOW).
MINIMUM AND MAXIMUM PULL-UP
RESISTOR VALUES
RX(MIN) = __V-,C,-,C.!..(M.:..;.A-,X",)_-_V_O,,-L_ __
IOL - N2(LOW). 1.6 mA

RX(MAX) = _ _V-,C--,C.o....(M-,I_N,-)-_V-,-O_H_ __
N1 • IOH + N2(HIGH). 40pA

where:
.Rx
N1
N2
IOH = ICEX
IOL
VOL
VOH
VCC

= External Pull-up Resistor

= Number of Wired-OR Outputs
= Number of Input Unit Loads (U.L.) being Driven
= Output HIGH Leakage Current
= LOW Level Fan-out Current of Driving Element
= Output LOW Voltage Level (0.5 V)
= Output HIGH Voltage Level (2.4 V)
= Power Supply Voltage

FAST AND LS TIL DATA

3-4

Example: Four 74LS03 gate outputs driving four other LS gates or MSI inputs.
RX(MIN) =

5.25 V - 0.5 V
8mA-l.6 mA

4.75 V -7420
6.4mA

RX(MAX) = __4_._75_V_-_2_.4_V
__
4. 100 IIA

+2 0

40llA

2.35 V

- 4.9 kO

0048 mA

where:
Nl
N2 (HIGH)
N2(LOW)
IOH
IOL
VOL
VOH

=4

=4

=

0 0.5 U.l.
2 U.l.
= 4 0 0.25 U.L. = 1 U.L.
lOOIiA
=8mA
=0.5V
=2.4V

=

Any value of pull-Up resistor between 742 0 and 4.9 kO can be used. The lower values yield the fastest speeds while
the higher values yield the lowest power dissipation.
UNUSED INPUTS. For best noise immunity and switching speed, unused TTL inputs should not be left floating, but
should be held between 2.4 V and the absolute maximum input voltage.
Two possible ways of handling unused inputs are:

1. Connect unused input to VCC, LS and FASr" TTL inputs have a breakdown voltage >7.0 V and require, therefore
no series resistor.
2. Connect the unused input to the output of an unused gate that is forced HIGH.
CAUTION: Do not connect an unused LS or FAST'" input to another input of the same NAND or AND function. This
method, recommended for normal TTL, increases the input coupling capacitance and thus reduces the ae noise immunity.
INPUT CAPACITANCE. As a rule of thumb, LS and FAST'" TTL inputs have an average capacitance of 5 pF for DIP
packages. For an input that serves more than one internal function, each additional function adds approximately
1.5 pF.
LINE DRIVING - Because of its superior capacitive drive characteristics, TTL logic is often used in line driving applications
which require various termination techniques to maintain signal integrity. Parameters associated with this application
are listed in Table 3.4.
It is also often necessary to construct load lines to determine reflection waveforms in line driving applications. The
input and output characteristics graphs of section 3 (Figs. 2-4, 2-7 and 2-8) can be very useful for this purpose.
OUTPUT RISE AND FALL TIMES provide important information in determining reflection waveforms and crosstalk
coefficients. Typical rise and fall times are approximately 6.0 ns for LS and about 2.0 ns for FASr" with a 50-pF load
(measured 10-90%). Output rise and fall times become longer as capacitive load is increased.
INTERCONNECTION DELAYS. For those parts of a system in which timing is critical, designers should take into account
the finite delay along the interconnections. These range from about 0.12 to 0.15 nslinch for the type of interconnections
normally used in TTL systems. Exceptions occur in systems using ground planes to reduce ground noise during a logic
transition; ground planes give higher distributed capacitance and delays of about 0.15 to 0.22 ns/inch.
Most interconnections on a logic board are short enough that the wiring and load· capacitance can be treated as a
lumped capacitance for purposes of estimating their effect on the propagation delay of the driving circuit. When an
interconnection is long enough that its delay is one-fourth to one-half of the signal transition time, the driver output
waveform exhibits noticeable slope changes during a transition. This is evidence that during the initial portion of the
output voltage transition the driver sees the characteristic impedance of the interconnection (normally 1000 to 200 0),
which for transient conditions appears as a resistor returned to the quiescent voltage existing just before the beginning
of the transition. This characteristic impedance forms a voltage divider with the driver output impedance, tending to
produce a signal transition having the same rise or fall time as in the no-load condition but with a reduced amplitude.
This attenuated signal travels to the far end of the interconnection, which is essentially an unterminated transmission
line, whereupon the signal starts doubling. Simultaneously, a reflection voltage is generated which has the same
amplitude and polarity as the original signal, e.g., if the driver output signal is positive-going the reflection will be
positive-going, and as it travels back toward the driver it adds to the line voltage. At the instant the reflection arrives
at the driver it adds algebraically to the still-rising driver output, accelerating the transition rate and producing the
noticeable change in slope.

FAST AND LS TTL DATA

3-5

II

IALL MAXIMUM RATiNGSI
Characteristic
Operating Voltage Range
Outpul Drive:
Siandard Oulpul

LS
Symbol
Vee
IOH
IOL
Ise

Buffer Oulpul

IOH
IOL
Ise

FAST
74LSxxx
5'=5%

54Fxxx
5+10%

74Fxxx
5::!:10%

-0.4

-1.0

-1.0

B.O

20

-2010 -100

-6010 -ISO

20
-6010-150

-12

-15

-12

-IS

12
-4010 -225

24
-4010 -225

48
-10010 -225

64
-10010 -225

54LSxxx
5::!:10%
-0.4
4.0
-2010 -100

Units
Vdc
mA
mA
mA
mA
rnA
mA

TABLE 3.4
OUTPUT CHARACTERISTICS FOR SCHOTTKY TTL LOGIC

If an interconnection is of such length that its delay is longer than half the signal transition time, the attenuated output of
the driver has time to reach substantial completion before the reflection arrives. In the limit, the waveform observed atthe
driver output is a 2-step signal with a pedestal. In this circumstance the first load circuit to receive·a full signal is the one at
the far end, because of the doubling effect, while the last one to receive a full signal is the one nearest the driver since it
must wait for the reflection to complete the transition. Thus, in a worst-case situation, the net contribution to the overall
delay is twice the delay of the interconnection because the initial part ofthe signal must travel to the far end ofthe line and
the reflection must return.
When load circuits are distributed along an interconnection, the input capacitance of each will cause a small reflection
having a polarity opposite that ofthe signal transition, and each capacitance also slows the transition rate ofthe signal as it
passes by. The series of small reflections, arriving back at the driver, is subtractive and has the effect of reducing the
apparent amplitude of the signal. The successive slowing ofthe transition rate of the transmitted signal means that ittakes
longer forthe signal to rise or fall to the threshold level of any particular load circuit. A rough but workable approach is to
treat the load capacitances as an increase in the intrinsic distributed capacitance of the interconnection. Increasing the
distributed capacitance of a transmission line reduces its impedance and increases its delay. A good approximation for
ordinary TIL interconnections is that distributed load capacitance decreases the characteristic impedance by about onethird and increases the delay by one-half.

ABSOLUTE MAXIMUM RATINGS (above which the useful life may be impaired)

Storage Temperature
Temperature (Ambient) Under Bias
VCC Pin Potential to Ground Pin
"Input Voltage (dc) Diode Inputs
"Input Current (dc)
Voltage Applied to Open Collector
Outputs (Output HIGH)
High Level Voltage Applied to
Disabled 3-State Output

LS
- 65"C to + 150"C
- 55"C to + 125"C
- 0.5 V to + 7.0 V
-0.5Vto 15V
-30 mA to +5.0 mA

FAST
-65"C to+ 150"C
- 55"C to + 125"C
- 0.5 V to + 7.0 V
-0.5 V to 7.0 V
-30 mA to +5.0 mA

-0.5Vto+l0V

-0.5 V to +5.5 V

5.5 V

5.5 V

"Either input voltage limit or input circuit limit is sufficient to protect the inputs - Circuits with 5.5 V maximum limits
are listed below.
Device types having inputs limited to 5.5 V are as follows:
SN74LS242/243, SN74LS245 - Inputs connected to outputs.
SN74LS640/6411642/645
- Inputs connected to outputs.
SN74LS299/322A1323
- Certain Inputs.
SN74LS673/674
- Certain Inputs.
SN74LS151/251
- Multiplexer Inputs.

FAST AND LS TTL DATA

3-6

DEFINITION OF SYMBOLS AND TERMS USED IN THIS DATABOOK
CURRENTS - Positive current is defined as conventional current flow into a device. Negative current is defined as
conventional current flow out of a device. All current limits are specified as absolute values.
lee

Supply Current - The current flowing into the Vee supply terminal of a circuit with the specified input
conditions and the outputs open. When not specified, input conditions are chosen to guarantee worst case
operation.

IIH

Input HIGH current -

The current flowing into an input when a specified HIGH voltage is applied.

IlL

Input LOW current -

The current flowing out of an input when a specified LOW voltage is applied.

IOH

Output HIGH current. The leakage current flowing into a turned off open collector output with a specified
HIGH output voltage applied. For devices with a pull-up circuit, the IOH is the current flowing out of an
output which is in the HIGH state.

IOL

Output LOW current - The current flowing into an output which is in the LOW state.·

lOS

Output short-circuit current - The current flowing out of an output which is in the HIGH state when that
output is short circuit to ground (or other specified potential).

IOZH

Output off current HIGH - The current flowing into a disabled 3-state output with a specified HIGH output
voltage applied.

IOZL

Output off current LOW - The current flowing out of a disabled 3-state output with a specified LOW output
voltage applied.

VOLTAGES-All voltages are referenced to ground. Negativevoltage limits are specified as absolute values (i.e., -10 V is
greater than -1.0 V).
Vee

Supply voltage- The range of power supply voltage over which the device is guaranteed to operate within
the specified limits.

VIK(MAX)

Input clamp diode voltage - The most negative voltage at an input when 18 mA is forced out of that input
terminal. This parameter guarantees the integrity of the input diode which is intended to clamp negative
ringing at the input terminal.

VIH

Input HIGH voltage -

VIH(MIN)

Minimum input HIGH voltage - The minimum allowed input HIGH in a logic system. This value represents
the guaranteed input HIGH threshold for the device.

VIL

Input LOW voltage -

VIL(MAX)

Maximum input LOW voltage - The maximum allowed input LOW in a system. This value represents the
guaranteed input LOW threshold for the device.

VOH(MIN)

Output HIGH voltage - The minimum voltage at an output terminal for the specified output current IOH
and at the minimum value of Vee.

VOL(MAX)

Output LOW voltage - The maximum voltage at an output terminal sinking the maximum specified load
current IOL.

VT +

Positive-going threshold voltage - The input voltage of a variable threshold device (i.e., Schmitt Trigger)
that is interpreted as a VIH as the input transition rises from below VT-(MIN).

VT -

Negative-going threshold voltage - The input voltage of a variable threshold device (i.e., Schmitt Trigger)
that is interpreted as a VIL as the input transition falls from above VT + (MAX).

The range of input voltages that represents a logic HIGH in the system.

The range of input voltages that represents a logic LOW in the system.

FAST AND LS TTL DATA

3-7

II

AC SWITCHING PARAMETERS AND WAVEFORMS
tPLH

Propagation delay LOW-TO-HIGH:
The time delay from when the input is 1.3 V (1.5 for FAST) to when the output reaches 1.3 V (1.5 for FAST),
while the output changes to a logic HIGH.

tpHL

Propagation delay HIGH-TO-LOW:
The time delay from when the input is 1.3 V (1.5 for FAST) to when the output reaches 1.3 V (1.5 for FAST),
while the output changes to a logic LOW.

For Non Inverting

For Inverting Function

VIN

II

VOU!

Waveform Rise Time:
LOW to HIGH logic transition time, measured from the 10% to 90% points of the waveform.
Waveform Fall Time:
HIGH to LOW logic transition time, measured the 90% to the 10% points of the waveform.

90%

90%

10%

tpHZ

Output disable time: HIGH to Z
The time delay between the specified amplitude point on the enable input and when the output falls 0.3 V
(0.3 V for FAST) from the steady-state HIGH level.

tpZH

Output enable time: Z to HIGH
The time delay between the specified amplitude points on the enable input and the output, when the output
is going from a disabled state to a logic HIGH state.

Enable

Vout----....J

FAST AND LS TIL DATA

3-8

tPLZ

Output disable time: LOW to Z
Thetime delay between the specified amplitude point on the enable input and when the output fallsO.3 V
(0.3 V for FAST) from the steady-state LOW level.

tpZL

Output enable time: Z to LOW
The time delay between the specified amplitude points on the enable input and the output when the output
is going from a disabled state to a logic LOW state.

Enable

VOU! - - - - - - ' . . : ; :

Voz ~ 1.5 V
.5 for LS
.3 for FAST

trec

Recovery time
Time required between an asynchronous signal (SET, RESET, CLEAR or PARALLEL load) and the active
edge of a synchronous control signal, to insure that the device will properly respond to the synchronous
signal.

::::::~~ -_-_-_-_~J: ><: ~
__

_________

Control--------------------...J

Hold Time
The interval of time from the active edge of the control signal (usually the clock) to when the data to be
recognized is no longer required to ensure proper interpretation ofthe data. A negative hold time indicates
that the data may be removed at some time prior to the active edge of the control signal.
Setup time
The interval oftime during which the data to be recognized is required to remain constant prior to the active
edge of the control signal to ensure proper data recognition.

FAST AND LS TTL DATA

3-9

II

II

tw or
tpw

Pulse width
Thetime between the specified amplitude points(1.3 V for LS and 1.5 V for FASTTM) on the leading and trailing
edges of a pulse.

Toggle frequency/operating frequency
The maximum rate at which clock pulses meeting the clock requirements (i.e., 'WH, tWL, and t r, tf) may be
applied to a sequential circuit. Above this frequency the device may cease to function.
Guaranteed maximum clock frequency
Trie lowest possible value for fMAX.

TESTING
DC TEST CIRCUITS
The following test Circuits and forcing functions represent Motorola's typical DC test procedures

VOH AND VOL TESTS
Force 10HMAX or 10LMAX
Measure VOH or VOL

IIHH' IIH AND IlL TESTS
Force 7.0, 5.5, 2.7, or 0.4 V
Measure IIHH' IIH' or IlL

+)

VIHMIN~UT
orVILMAX
10

VIK TEST
Force Ii
Measure VIK

•

Vo

~
ViX

lOS TEST
Measure

lOS

VIHMIN~
OrVILMAX

10H' 10ZH' and 10ZL TESTS
Force 5.5, 2.4, or 0.4 V
Measure 10

~
~vo

3-10

~

lee TEST
Vee MAX

GND{

or
4.5 V'

'Unless otherwise indicated, input conditions are selected to produce a worst case condition.

FAST AND LS TTL DATA

~

)

outputs
open

AC TEST CIRCUITS The following test circuits and conditions represent Motorola's typical test procedures. AC waveforms
and terminology can be found on pages 3-8 to 3-10.
Proper testing requires that care be taken in the construction of AC test fixtures. This is especially true of FASr" TTL.
Maintaining a 50 D. environment on the ac test fixture, as well as the use of multilayer boards with internal VCC and
ground planes is highly recommended for FASr" TTL. Bypassing with both electrolytic and high quality RF type
capacitors should be provided on the board. Lead lengths for all components should be kept as short as possible
(Motorola uses and recommends chip capacitors and resistors for ac test fixtures). Following these rules will result in
cleaner waveforms as well as better correlation between Motorola and the FAST'" TTL consumer.
FUNCTIONAL TESTING OF TTL IN A NOISY ENVIRONMENT
Testing noise (noise generated by the test system itself and noise generated by TTL devices under test interacting with
the test"system) adds to, or subtracts from the threshold voltage applied to the TTL device under test. For this reason
Motorola does not recommend functional testing of TTL devices using threshold levels of 0.8 V and 2.0 V. Instead, good
TTL testing techniques call for hard levels of less than 0.5 V VIL and greater than 2.4 V VIH to be applied for functional
testing. Input threshold voltages should be tested separately, and only (for noise reasons above) after setting the device
state with a hard level.

LS TEST CIRCUITS

PULSE GENERATOR SETTINGS
(UNLESS OTHERWISE SPECIFIED)

Frequency =
Duty Cycle =
1 TLH (t r ) =
1 THL (tf) =
Amplitude =

LS
lMHz
50%
6 ns (15)*
6 ns (15)*
o to 3 V

FAST
lMHz
50%

2.5 ns
2.5 ns
o to 3 V

VOUT

*The specified propagation delay limits can be guaranteed
with a 15 ns input rise time on all parameters except those
requiring narrow pulse widths. Any frequency measurement
over 15 MHz or pulse width less than 30 ns must be performed
with a 6 ns input rise time.
Test Circuit for Open Collector Output Devices

vcc

FAST TEST CIRCUITS
+7V

L
tpZl. tplZ. O.C.

·includes all probe and jig capacitance
D.U.T.

Optional LS Load (Guaranteed-Not Tested)

OPEN

~
All OTHEA

At
500n

vcc

,--

A2

----l

I

I
I

I'1'Cl

I~

~
L _______

500n

I
I
I
I

*includes all probe and jig capacitance

I

JI
FAST AND LS TTL DATA

3-11

II

3-12

!FAST Data Sheets

II

®

MOTOROLA

MC54FOO
MC74FOO

QUAD 2-INPUT NAND GATE
VCC

QUAD 2-INPUT NAND GATE
FASTTM

SCHOTTKY TTL

GND
J Suffix - Case 632-07 (Ceramic)
N Suffix - Case 646-05 (Plastic)

GUARANTEED OPERATING RANGES
SYMBOL

MIN

TYP

MAX

UNIT

54, 74

4.5

5.0

5.5

V

54
74

-55
0

25
25

125
70

°C

PARAMETER

VCC

Supply Voltage

TA

Operating Ambient Temperature Range

10H

Output Current -

High

54, 74

-1.0

mA

10L

Output Current -

Low

54, 74

20

mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

MIN

LIMITS
TYP

MAX

UNITS

Guaranteed Input HIGH Voltage

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

O.B

V

Guaranteed Input LOW Voltage

VIK

Input Clamp Diode Voltage

-1.2

V

VCC = MIN, liN = -1 B mA

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

2.0

154,74

2.5

V

IOW-1.OmA

VCC =4.50V

1 74

2.7

V

IOH=-1.0mA

VCC=4.75V

IOL= 20 mA

VCC= MIN

0.5

V

20

VCC = MAX, VIN = 2.7 V

0.1

/lA
mA

-0.6

mA

VCC = MAX, VIN = 0.5 V

-150

mA

VCC = MAX, VOUT = 0 V

Power Supply Current
Total, Output HIGH

2.8

mA

VCC = MAX, VIN = GND

Total, Output LOW

10.2

mA

VCC = MAX, VIN = Open

IIH

Input HIGH Current

IlL

Input LOW Current

lOS

Output Short Circuit
Current (Nofe 2)

ICC

V

TEST CONDITIONS

-60

VCC = MAX, VIN - 7.0 V

NOTES:
1. For conditions shown as MIN or MAX, use the appropiate value specified under recommended operating conditions forthe applicable
device type.
2. Not more than one output should be shorted at a time. nor for more than 1 second.

FAST AND LS TTL DATA

4-2

MC54F00174FOO

AC CHARACTERISTICS

SYMBOL

PARAMETER

54174F
TA = +25°C
VCC = +5.0 V
CL = 50 pF

54F
TA = -55°C to +125°C
VCC = 5.0 V ± 10%
CL = 50 pF

74F
TA=OOCt070oC
VCC = 5.0 V ± 10%
CL = 50 pF

UNITS

MIN

MAX

MIN

MAX

MIN

tpLH

Propagation Delay

2.4

5.0

2.0

7.0

2.4

6.0

ns

tpHL

Propagation Delay

1.5

4.3

1.5

6.5

1.5

5.3

ns

AC TEST CIRCUIT

DUT

>-----Q---~&----o

Test Point for High Impedance Scopes

R2=500n

± 10%

For 50 fl scopes, add a

450

n resistor in series

with the scope and delete

R2.

Fig. 1

FAST AND LS TTL DATA

4-3

MAX

®

MOTOROI.A

MC54F02
MC74F02

QUAD 2-INPUT NOR GATE

QUAD 2-INPUT NOR GATE
FASTTM SCHOTTKY TTL

J Suffix - Case 632-07 (Ceramicl
N Suffix - Case 646-05 (Plasticl

GUARANTEED OPERATING RANGES
SYMBOL
VCC

PARAMETER
Supply Voltage

MIN

TYP

MAX

UNIT

54, 74

4,5

54
74

-55
0

5,0

5.5

V

25
25

125
70

°c

TA

Operating Ambient Temperature Range

IOH

Output Current -

High

54, 74

-1.0

mA

10L

Output Current - Low

54, 74

20

mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

MIN

LIMITS
TYP

MAX

UNITS

2.0

V

TEST CONDITIONS
Guaranteed Input HIGH Voltage

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

O.B

V

Guaranteed Input LOW Voltage

VIK

Input Clamp Diode Voltage

-1.2

V

VCC = MIN, liN = -1B mA

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

Input HIGH Current

IlL

Input LOW Current

lOS

Output Short Circuit
Current (Note 2)

ICC

1 54,74

2.5

V

IOH=-1.0mA

VCC=4.50V

74
1

2.7

V

IOH=-1.0mA

VCC-4.75V

0.5

V

IOL= 20 mA

VCC= MIN

20

VCC = MAX, VIN = 2.7 V

0.1

/LA
mA

-0.6

mA

VCC = MAX, VIN = 0.5 V

-60

VCC = MAX, VIN = 7.0 V

-150

mA

VCC = MAX, VOUT = 0 V

Power Supply Current
Total, Output HIGH

5.6

mA

Total, Output LOW

13

mA

VCC = MAX, VIN = GND
VCC = MAX, VIN = Note 3

NOTES:
1. For conditions shown as MIN or MAX, use the appropiate value specified under recommended operating conditions forthe applicable

device type.
2. Not more than one output should be shorted at a time. norfor more than' second.
3. Measured with one input high, one input low for each gate.

FAST AND LS TTL DATA

4-4

MC54F02174F02

AC CHARACTERISTICS

SYMBOL

54174F
TA =+25°e
Vee =+5.0 V
eL =50 pF

PARAMETER

54F
TA =-55°C to +125°e
Vee =5.0 V ± 10%
eL =50 pF

74F
TA =ooe to 70°C
Vee =5.0 V ± 10%
eL =50 pF

UNITS

MIN

MAX

MIN

MAX

MIN

tpLH

Propagation Delay

2.5

5.5

2.5

7.5

2.5

6.5

ns

tpHL

Propagation Delay

1.5

4.3

1.5

6.5

1.5

5.3

ns

MAX

AC TEST CIRCUIT

OUT

>----+---.....--()

Test Point for High Impedance Scopes

R2= 500 n
±10%

For 50

n scopes, add a

450 n resistor in series
with the scope and delete

R2.

Fig. 1

FAST AND LS TTL DATA

4-5

II

II

®

MOTOROLA

MC54F04
MC74F04

HEX INVERTER

HEX INVERTER
FASTTM

SCHOTTKY TTL

J Suffix - Case 632-07ICeramic)
N Suffix - Case 646-05IPlastic)

GUARANTEED OPERATING RANGES
SYMBOL

PARAMETER

VCC

Supply Voltage

TA

Operating Ambient Temperature Range

MIN

TYP

MAX

UNIT

54, 74

4.5

5.0·

5.5

V

54
74

-55
0

25
25

125
70

°c

10H

Output Current -

High

54, 74

-1.0

mA

10L

Output Current -

Low

54, 74

20

mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

MIN

LIMITS
TYP

MAX

UNITS

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

O.B

V

Guaranteed Input LOW Voltage

VIK

Input Clamp Diode Voltage

-1.2

V

VCC = MIN, liN = -1 B mA

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

Input HIGH Current

IlL

Input LOW Current

lOS

Output Short Circuit
Current (Note 2)

ICC

2.0

154,74
1 74

V

TEST CONDITIONS
Guaranteed Input HIGH Voltage

2.5

V

10H = -1.0 mA

VCC =4.50V

2.7

V

10H =-1.0 mA

VCC -4.75V

0.5

V

10L= 20 mA

VCC= MIN

20

p.A

VCC = MAX, VIN = 2.7 V

0.1

mA

VCC = MAX, VIN = 7.0 V

-0.6

mA

VCC = MAX, VIN = 0.5 V

-150

mA

VCC = MAX, VOUT = 0 V

Power Supply Current
Total, Output HIGH

4.2

mA

VCC = MAX, VIN = GND

Total, Output LOW

15.3

mA

VCC = MAX, VIN = Open

-60

NOTES:
1. For conditions shown as MIN or MAX, use the appropiate value specified under recommended operating conditions forthe applicable

device type.
2. Not more than one output should be shorted at a time, nor for more than 1 second.

FAST AND LS TTL DATA

4-6

MC54F04174F04

AC CHARACTERISTICS

SYMBOL

PARAMETER

54F
TA = -55°e to +125°e
VCC = 5.0 V± 10%
CL = 50 pF

54174F
TA = +25°e
VCC= +5.0 V
CL = 50 pF

74F
TA = oDe to 70 0 e
VCC =5.0V± 10%
CL = 50 pF

UNITS

MIN

MAX

MIN

MAX

MIN

tpLH

Propagation Delay

2.4

5.0

2.0

7.0

2.4

MAX
6.0

ns

tpHL

Propagation Delay

1.5

4.3

1.5

6.5

1.5

5.3

ns

AC TEST CIRCUIT

>---------q----------....--~.....--o
CL=50pF

± 1.0%

I

Test Point for High Impedance Scopes

R2= 500n
±10%

For 50

n scopes, add a

450 n resistor in series
with the scope and delete

R2.

Fig. 1

FAST AND LS TTL DATA

4-11

MAX

®

MOTOROL.A

MC54Fll
MC74Fll

TRIPLE 3-INPUT AND GATE

TRIPLE 3-INPUT AND GATE
FASTTM SCHOTTKY TTL

GND

J Suffix - Case 632-07 ICeramic)
N Suffix - Case 646-05 IPlastic)
GUARANTEED OPERATING RANGES

VCC

MIN

TYP

MAX

UNIT

54, 74

4.5

5.0

5.5

V

54
74

-55
0

25
25

125
70

°c

PARAMETER

SYMBOL
Supply Voltage

TA

Operating Ambient Temperature Range

IOH

Output Current -

High

54, 74

-1.0

mA

10L

Output Current -

Low

54, 74

20

mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

MIN

LIMITS
TYP

MAX

UNITS
V

2.0

TEST CONDITIONS
Guaranteed Input HIGH Voltage

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

O.B

V

Guaranteed Input LOW Voltage

VIK

Input Clamp Diode Voltage

-1.2

V

VCC = MIN, liN = -1 B mA

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

Input HIGH Current

IlL

Input LOW Current

lOS

Output Short Circuit
Current (Note 2)

ICC

154,74
1 74

2.5

V

IOH=-1.0mA

VCC=4.50V

2.7

V

IOH = -1.0 mA

VCC=4.75V

0.5

V

IOL= 20 mA

VCC= MIN

20

/LA

VCC = MAX, VIN = 2.7 V

0.1

mA

VCC = MAX, VIN = 7.0 V

-0.6

mA

VCC = MAX, VIN = 0.5 V

-150

mA

VCC = MAX, VOUT = 0 V

Power Supply Current
Total, Output HIGH

6.2

mA

VCC = MAX, VIN = Open

Total, Output LOW

9.7

mA

VCC = MAX, VIN = GND

-60

NOTES:

1. For conditions shown as MIN or MAX, use the appropiate value specified under recommended operating conditions for the applicable
device type.

2. Not more than one output should be shorted at a time, nor for more than 1 second.

FAST AND LS TTL DATA

4-12

MC54F11/74F11

AC CHARACTERISTICS

SYMBOL

54/74F
TA = +25°e
Vee = +5.0 V
eL = 50 pF

PARAMETER

54F
TA = -55°C to +125°e
Vee = 5.0 V ± 10%
eL = 50 pF

74F
TA = ooe to 70°C
Vee=5.0V±10%
eL = 50 pF

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

tpLH

Propagation Delay

3.0

5.6

2.5

7.5

3.0

6.6

ns

tpHL

Propagation Delay

2.5

5.5

2.0

7.5

2.5

6.5

ns

AC TEST CIRCUIT

OUT

Test Point for High Impedance Scopes

R2= 500n
±10%

For 50

n scopes, add a

450 n resistor in series
with the scope a nd delete

R2.
Fig. 1

II

I

FAST AND LS TTL DATA

4-13

II

®

MOTOROLA

MCS4F20
MC74F20

DUAL 4-INPUT NAND GATE
Vee

DUAL 4-INPUT NAND GATE
FASTTM

SCHOTTKY TTL

GND

J Suffix - Case 632-07 (Ceramic)
N Suffix - Case 646-05 (Plastic)

GUARANTEED OPERATING RANGES
SYMBOL
Vee

MIN

TYP

54, 74

4.5

54
74

-55
0

PARAMETER
Supply Voltage

MAX

UNIT

5.0

5.5

V

25
25

125
70

°C

TA

Operating Ambient Temperature Range

10H

Output Current -

High

54, 74

-1.0

mA

10L

Output Current - Low

54, 74

20

mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

MIN

LIMITS
TYP

MAX

UNITS
V

Guaranteed Input HIGH Voltage

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

O.B

V

Guaranteed Input LOW Voltage

VIK

Input Clamp Diode Voltage

-1.2

V

VCC= MIN, IIN=-IB mA

Output HIGH Voltage

2.5

V

10H = -1.0 mA

VCC-4.50V

VOH

2.7

V

10H = -1.0 mA

VCC=4.75V

VOL

Output LOW Voltage

0.5

V

10L= 20 mA

VCC= MIN

20

p.A

VCC = MAX, VIN = 2.7 V

IIH

Input HIGH Current

IlL

Input LOW Current

lOS

Output Short Circuit
Current (Note 2)

ICC

2.0

TEST CONDITIONS

154,74
1 74

0.1

mA

VCC = MAX, VIN - 7.0 V

-0.6

mA

VCC = MAX, VIN = 0.5 V

-150

mA

VCC = MAX, VOUT = 0 V

Power Supply Current
Total, Output HIGH

1.4

mA

VCC = MAX, VIN = GND

Total, Output LOW

5.1

mA

VCC = MAX, VIN = Open

-60

NOTES:
1. For conditions shown as MIN or MAX, use the appropiate value specified under recommended operating conditions for the applicable
device type.

2. Not more than one output should be shorted at a time, nor for more than 1 second.

FAST AND LS TTL DATA

4-14

MC54F20/74F20

AC CHARACTERISTICS·

SYMBOL

PARAMETER

54174F
TA = +25°e
Vee= +5.0V
eL = 50 pF

54F
TA = -55°C to +125°e
Vee = 5.0 V ± 10%
eL = 50 pF

74F
TA = ooe to 70°C
Vee=5.0V±10%
eL = 50 pF

UNITS

MIN

MAX

MIN

MAX

MIN

tpLH

Propagation Delay

2.4

5.0

2.0

7.0

2.4

6.0

ns

tPHL

Propagation Delay

1.5

4.3

1.5

6.5

1.5

5.3

ns

MAX

AC TEST CIRCUIT

DUT

>---+---'---0

Test Point for High Impedance Scopes

R2= 500n
±10%

For 50 n scopes, add a

450

n resistor in

series

with the scope and delete

R2.

Fig. 1

FAST AND LS TTL DATA

4-15

II

®

MOTOROLA

MC54F32
MC74F32

QUAD 2-INPUT OR GATE
Vee

QUAD 2-INPUT OR GATE
FASTTM

SCHOTTKY TTL

MIN

TYP

MAX

UNIT

54, 74

4.5

5.0

5.5

V

54
74

-55
0

25
25

125
70

DC

GND

J Suffix - Case 632-07 (Ceramicl
N Suffix -

Case 646-05 (Plasticl

GUARANTEED OPERATING RANGES
PARAMETER

SYMBOL

II

VCC

Supply Voltage

TA

Operating Ambient Temperature Ra nge

10H

Output Current -

High

54, 74

-1.0

mA

10L

Output Current -

Low

54, 74

20

mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
LIMITS
SYMBOL

PARAMETER

UNITS
MIN

TYP

TEST CONDITIONS

MAX

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

0.8

V

Guaranteed Input LOW Voltage

VIK

Input Clamp Diode Voltage

-1.2

V

VCC= MIN,IIN=-18 mA

Output HIGH Voltage

2.5

V

VOH

10H = -1.0 mA

2.7

V

IOH=-1.0mA

VCC=4.75V

V

10L = 20 mA

VCC= MIN

2.0

1 54,74
1

VOL

Output LOW Voltage

IIH

Input HIGH CUrrent

IlL

Input LOW Current

lOS

Output Short Circuit
Current (Note 2)

ICC

74

V

0.5

-60

Power Supply Current
Total, Output HIGH
Total, Output LOW

Guaranteed Input HIGH Voltage

VCC=4.50V

20

I'A

VCC = MAX, VIN = 2.7 V

0.1

mA

VCC - MAX, VIN - 7.0 V

-0.6

mA

VCC = MAX, VIN = 0.5 V

-150

mA

VCC = MAX, VOUT = 0 V

9.2
15.5

mA
mA

VCC = MAX, VIN = GND
VCC - MAX, VIN = Open

NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.
2. Not more than one output should be shorted at a time.

FAST AND LS TTL DATA

4-16

MC54F32174F32

AC CHARACTERISTICS

SYMBOL

54174F
TA = +25°C
Vce = +5.0 V
CL = 50 pF

PARAMETER

54F
TA = -55°C to +125°e
Vce= 5.0V± 10%
eL = 50 pF

74F
TA = ooe to 70°C
VCC=5.0V±10%
CL = 50 pF

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

tpLH

Propagation Delay

3.0

5.6

3.0

7.5

3.0

6.6

ns

tpHL

Propagation Delay

3.0

5.3

2.5

7.5

3.0

6.3

ns

AC TEST CIRCUIT

DUT

>----....---._--0
CL=50pF

± 1.0%

I

Test Point for High Impedance Scopes

R2= 500n
±10%

n scopes, add a
n resistor in series

For 50

450

with the scope and delete
R2.

Fig. 1

FAST AND LS TTL DATA

4-17

II

®

MOTOROI.A

MCS4F64
MC74F64

4-2-3-2-INPUT ANO-OR-INVERT GATE
VCC

4-2-3-2-INPUT
ANO-OR-INVERT GATE
FASl'M

SCHOTTKY TTL

GND
J Suffix - Case 632-07 (Ceramic)
N Suffix - Case 646-05 (Plastic)

GUARANTEED OPERATING RANGES
SYMBOL
VCC

II

PARAMETER
54, 74

Supply Voltage

54
74

MIN

TYP

MAX

UNIT

4_5

5_0

5_5

V

-55
0

25
25

125
70

°c

TA

Operating Ambient Temperature Range

10H

Output Current - High

54, 74

-1.0

rnA

10L

Output Current - Low

54, 74

20

rnA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

MIN

LIMITS
TYP

MAX

UNITS

TEST CONDITIONS

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

0.8

V

Guaranteed Input LOW Voltage

VIK

Input Clamp Diode Voltage

-1.2

V

liN = -18 rnA

VCC= MIN

V

IOH=-1.0mA

VCC=4.50V

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

2.0

1 54,74
1

IIH

Input HIGH Current

IlL

Input LOW Current

lOS

Output Short Circuit
Current (Note 2)

(CC

74

V

2.5

V

IOH=-1.0mA

VCC = 4_75 V

0.5

V

10L= 20 rnA

VCC= MIN

20

p.A

VIN= 2.7V

2.7

-60

Guaranteed Input HIGH Voltage

VCC= MAX

0.1

rnA

VIN=7.0V

-0.6

rnA

VIN=0.5 V

VCC= MAX

-150

rnA

VOUT= 0 V

VCC= MAX

Power Supply Current
Total, Output HIGH

2.8

rnA

VIN= GND

Total, Output LOW

4.7

rnA

VIN-

.

VCC= MAX

NOTES:
1. For conditions shown as MIN or MAX. use the appropiate value specified under recommended operating conditions for the applicable
device type.
2. Not more than one output should be shorted at a time. nor for more than 1 second.
* 'eel is measured with all inputs of one gate open and remaining inputs grounded.

FAST AND LS TTL DATA

4-18

MC54F64174F64

AC CHARACTERISTICS

SYMBOL

54174F
TA = +25°e
Vee = +5.0 V
eL = 50 pF

PARAMETER

54F
TA = -55°C to +125°e
Vee= 5.0V± 10%
eL = 50 pF

74F
TA = ooe to 70°C
Vee = 5.0 V ±10%
eL = 50 pF

UNITS

MIN

MAX

MIN

MAX

MIN

tPLH

Propagation Delay

2.5

6.5

2.5

B.5

2.5

7.5

ns

tPHL

Propagation Delay

1.5

4.5

1.5

6.5

1.5

5.5

ns

AC TEST CIRCUIT

OUT

>---....- - -...- - 0
CL;50pF
± 1.0%

I

Test Point for High Impedance Scopes

R2; 500n
±10%

For 50

n scopes, add a

450 n resistor in senes
with the scope and delete

R2.

Fig. 1

FAST AND LS TTL DATA

4-19

MAX

®

ItIIOTOROLA

MCS4F74
MC74F74

DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP
DESCRIPTION - The MC54F174F74 is a dual D-type flip-flop with
Direct Clear and Set inputs and complementary (0, OJ outputs.
Information at the input is transferred to the outputs on the positive
edge of the clock pulse. Clock triggering occurs at a voltage level ofthe
clock pulse and is not directly related to the transition time of the
positive-going pulse. After the Clock Pulse input threshold voltage
has been passed, the Data input is locked out and information present
will not be transferred to the outputs until the next rising edge of the
Clock Pulse input.

DUAL D-TYPE POSITIVE
EDGE-TRIGGERED FLIP-FLOP
FASTTM

SCHOTTKY TTL

lOGIC SYMBOL

4
5

2

lOGIC DIAGRAM

3
6

';:==r)o-l-t>-Q
VCC = Pin 14
GNO =Pin 7

12
11

co--------------__~-----------------J
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.

10
S02
02 02

9

CP2
C0202

8

Y

13

CONNECTION DIAGRAM
TRUTH TABLE
(Each Half)
INPUT
@In

OUTPUTS
@ In

+ 1

0

a

Q

l
H

l
H

H
l

Asynchronous Inputs:

lOW Input to So sets Q to HIGH level
lOW Input to Co sets Q to LOW level
Clear and Set are indepedent of clock
Simultaneous LOW on Co and So
makes both 0 and 0 HIGH

H = HIGH Voltage Level
L = LOW Voltage Level
tn = Bit time before clock pulse
tn + 1 = Bit time after clock pulse

J Suffix - Case 632-07
(Ceramic)
N Suffix - Case 646-05
(Plastic)

FAST AND LS TTL DATA

4-20

MC54F/74F74

GUARANTEED OPERATING RANGES
SYMBOL
VCC

PARAMETER
Supply Voltage

MIN

TYP

MAX

UNIT

54. 74

4.50

5.0

5.50

V

54
74

-55
0

25
25

125
70

°c

TA

Operating Ambient Temperature Range

10H

Output Current - High

54. 74

-1.0

rnA

10L

Output Current - Low

54. 74

20

rnA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL
VIH

PARAMETER

MIN

Input HIGH Voltage

LIMITS
TYP

TEST CONDITIONS

UNITS

MAX

2.0

V

Guaranteed Input HIGH Voltage

VIL

Input LOW Voltage

0.8

V

Guaranteed Input LOW Voltage

VIK

Input Clamp Diode Voltage

-1.2

V

liN = -18 rnA

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

Input HIGH Current

IlL

Input LOW Current
(CP and 0 Inputs)
(CD and So Inputs)

lOS

Output Short Circuit
Current (Note 2)

ICC

Power Supply Current

154• 74

I 74

VCC= MIN

2.5

3.4

V

IOH=-1.0mA

VCC =4.50V

2.7

3.4

V

IOH=-1.0mA

VCC = 4.75 V

0.5

V

10L= 20 rnA

VCC= MIN

20

p.A

VIN= 2.7 V

100

p.A

VIN=7.0V

-0.6
-1.8

rnA
rnA

VIN= 0.5 V

VCC= MAX

-150

rnA

VOUT= OV

VCC= MAX

16

rnA

VCp=OV

VCC= MAX

0.35

-60
10.5

VCC= MAX

II

I

NOTES:
1. For conditions such as MIN or MAX, use the appropriate value specified under guaranteed operating ranges.
2. Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS

S YMBOL

PARAMETER

54174F
TA = +25°C
VCC=+5.0V
CL = 50 pF
MIN
TYP
MAX

**54F
74F
TA - -55 to +125°C TA = 0 to +70 oC
VCC = 5.0 V ±10% VCC=5.0V±10%
CL = 50 pF
CL = 50 pF
MIN

MAX

100

MIN

UNITS

MAX

f max

Maximum Clock Frequency

100

125

tPLH
tpHL

Propagation Delay
eP n to On or On

3.8
4.4

5.3
6.2

6.8
8.0

3.8
4.4

8.5
10.5

3.8
4.4

7.8
9.2

ns

tpLH
tpHL

Propagation Delay
COn or SOn to On or Q n

2.5
3.5

4.6
7.0

6.1
9.0

3.2
3.5

8.0
11.5

2.5
3.5

7.1
10.5

ns

FAST AND LS TTL DATA

4-21

100

MHz

MC54F174F74

AC OPERATING REQUIAEMENTS

S YMBOL

PARAMETER

54174F
TA = +25°e
Vee = +5.0 V
MIN
TYP
MAX

54F
74F
TA = -55 to +125°e TA = 0 to +70 o e
Vee = 5.0 V ±1 0% Vee =5.0V ±10%
MIN
MAX
MIN
MAX

UNITS

ts (H)
ts IL)

Set up Time, HIGH or LOW
On to CPn

2.0
3.0

3.0
4.0

2.0
3.0

th IH)
th (L)

Hold Time, HIGH or LOW
On to eP n

1.0
1.0

2.0
2.0

1.0
1.0

tw(H)
tw(L)

eP n Pulse Width, HIGH
or LOW

4.0
5.0

4.0
6.0

4.0
5.0

ns

tw(L)

eOn or SOn Pulse Width LOW

4.0

4.0

4.0

ns

tree

Recovery Time
COn or SOn to ep

2.0

3.0

2.0

ns

II

FAST AND LS TTL DATA

4-22

ns

®

MOTOROLA

MC54F86
MC74F86
QUAD 2-INPUT EXCLUSIVE-OR GATE

VCC

CONNECTION DIAGRAM

QUAD 2-INPUT
EXCLUSIVE-OR GATE
FASTTM

J Suffix - Case 632-07 (Ceramic)

SCHOTTKY TTL

N Suffix - Case 646-05 (Plastic)

GNO

GUARANTEED OPERATING RANGES
SYMBOL

PARAMETER
54, 74

MIN

TYP

MAX

UNIT

4.50

5.0'

5.50

V

-55
0

25
25

125
70

cc

VCC

Supply Voltage

TA

Operating Ambient Temperature Range

10H

Output Current - High

54, 74

-1.0

mA

10L

Output Current - Low

54, 74

20

mA

54
74

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

MIN

LIMITS
TYP

MAX

UNITS

VIH
VIL

Input LOW Voltage

0.8

V

Guaranteed Input LOW Voltage

VIK

Input Clamp Diode Voltage

-1.2

V

IIN=-18mA

VCC= MIN,

V

IOH=-1.0 mA

VCC=4.50V

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

Input HIGH Current

IlL

Input LOW Current

lOS

Output Short Circuit
Current (Note 2)

ICC

Power Supply Current

V

TEST CONDITIONS

Input HIGH Voltage

2.0

154,74

2.5

174

2.7

3.4

Guaranteed Input HIGH Voltage

V

10H = -1.0 mA

licc =4.75 V

0.5

V

10L= 20 mA

VCC= MIN

20

p.A

VIN=2.7V

100

p.A

VIN=7.0V

-0.6

mA

VIN = 0.5 V

VCC= MAX

-150

mA

VOUT=OV

VCC= MAX

15

23

mA

Inputs LOW

18

28

3.4
0.35

-60

Inputs HIGH

NOTES:
1. For conditions such as MIN or MAX. use the appropriate value specified under guaranteed operating ranges.
2. Not more than one output should be shorted at a time. nor for more than 1 second.

FAST AND LS TTL DATA

4-23

VCC= MAX

VCC= MAX

MC54F174F86

AC CHARACTERISTICS

S YMBOL

PARAMETER

54/74F
TA = +25°C
VCC=+5.0V
CL = 50 pF
MIN
TYP
MAX

54F
74F
I
TA = -55 to +125°C TA - 0 to +70o C
VCC = 5.0 V ±10% VCC = 5.0 V ±1 0%, UNITS
CL = 50 pF
CL = 50 pF
MIN
MAX
MIN
MAX

"I

tpLH
tpHL

Propagation 'Delay
(Other Input LOW)

3.0
3.0

4.0
4.2

5.5
5.5

2.5
3-.0

7.0
7.0

3.0
3.0

6.5
6.5

ns

tpLH
tPHL

Propagation Delay
(Other Input HIGH)

3.5
3.0

5.3
4.7

7.0
6.5

3.5
3.0

8.5
8.0

3.5
3.0

8.0
7.5

ns

FAST AND LS TTL DATA

4-24

WtI (c54J.1F Jl. (O)$)
W!l (c7I4J.1F 11 @~

DUAL

JK POSITIVE EDGE-TRIGGERED FLIP-FLOP

OEseR I PTION - The MC54F 174Fl 09 consists of two high-speed,
completely independent transition clocked JK flip-flops. The clocking
operation is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D flip-flop (refer to ·F74 data
sheet) by connecting the J and K inputs together.

DUAL

JK POSITIVE

EDGE-TRIGGERED FLIP-FLOP
FASTTM SCHOTTKY TTL

LOGIC SYMBOL
5

LOGIC DIAGRAM (one half shownl
2

J So

4

CP

3

K

Co

Q

Q

7

VCC = Pin 16
GNO =Pin 8

K--t-...,._

11
14
12

CP--------i~o-----~--------+_~

J SD

10

CP

13

SDI----------------~~------+_--------~

Q

9

CD'------------~--------~

Please note that this diagram IS provided only for the understanding of logic
operations and should not be used to estimate propagation delays.

15

CONNECTION DIAGRAM
TRUTH TABLE
Asynchronous Inputs:

INPUTS

OUTPUTS

@tn

@In • 1

J

K

L
L
H
H

H
L
H
L

a

a

No Change
H
L
H
L
Toggles

LOW Input to So sets
LOW Input to Co sets

Q
Q

to HIGH level
to LOW level

Clear and Set are indepedent of clock

Simultaneous LOW on Co and So
makes both Q and Q HIGH

t n :;:: Bit time before clock pulse
tn + 1 :::: Bit time after clock pulse
H = HIGH Voltage Level
L = LOW Voltage Level

J Suffix - Case 620-08
(Ceramic)
N Suffix - Case 648-05
(Plastic)

FAST AND LS TTL DATA

4-25

II

MC54F174F1 09

GUARANTEED OPERATING RANGES
SYMBOL

PARAMETER

VCC

Supply Voltage

TA

Operating Ambient Temperature Range

MIN

TYP

MAX

UNIT

:54,74

4.5

5.0

5.5

V

54
74

-55
0

25
25

125
70

°c

10H

Output Current -

High

54, 74

-1.0

mA

10L

Output Current - Low

54, 74

20

mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

MIN

LIMITS
TYP

MAX

TEST CONDITIONS

UNITS

VIH

Input HIGH Voltage

V

Guaranteed Input HIGH Voltage

VIL

Input LOW Voltage

0.8

V

Guaranteed Input LOW Voltage

VIK

Input Clamp Diode Voltage

-1.2

V

liN = -18 mA

VCC= MIN

V

IOH=-1.0mA

:i,cC=4.50V

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

Input HIGH Current

IlL

Input LOW Current
(J, K and CP Inputs)
(CD and So Inputs)

lOS

Output Short Circuit
Current (Note 2)

ICC

Power Supply Current

2.0

154 • 74

2.5

74

2.7

I

3.4

V

IOH=-1.0mA

rVG~ = 4.75\'.

0.5

V

10L= 20 mA

VCC= MIN

20

/LA

VIN=2.7V

100

/LA

VIN=7.0V

-0.6
-1.8

mA
mA

VIN =0.5 V

VCC= MAX

-150

mA

VOUT=OV

VCC= MAX

17

mA

VCp=OV

VCC= MAX

3.4
0.35

-60
11.7

VCC=MAX

NOTES:
1. For conditions such as MIN or MAX, use the appropriate value specified under guaranteed operating ranges.
2. Not more than one output should be shorted at a time. nor for more than 1 second.

AC CHARACTERISTICS

SYMBOL

PARAMETER

54/74F
TA = +25°C
VCC= +5.0V
CL = 50 pF
MIN
TYP
MAX

54F
74F
TA = -~,5 to +125°C TA = 0 to +70°C
VCC = 5.0 V ±10% VCC=5.0V±10%
CL = 50 pF
CL = 50 pF
MIN
MAX
MIN
MAX
70

f max

Maximum Clock Frequency

100

125

tpLH
tPHL

Propagation Delay
CP n to Qn or On

3.8
4.4

5.3
6.2

7.0
8.0

3.8
4.4

9.0
10.5

3.8
4.4

8.0
9.2

ns

tpLH
tpHL

Propagation Delay
COn or SOn to Qn or On

2.5
3.5

5.2
7.0

7.0
9.0

2.5
3.5

9.0
11.5

2.5
3:5

8.0
10.5

ns

FAST AND LS TTL DATA

4-26

90

UNITS

MHz

MC54F/74F109

AC OPERATING REQUIREMENTS

S YMBOL

54174F
TA = +25°e
Vee = +5.0 V

PARAMETER
MIN

TYP

54F
74F
TA = -55 to +125°e TA = 0 to +70 o e
Vee=5.0V±10% Vee = 5.0 V ±1 0%
MAX

MIN

MAX

MIN

UNITS

MAX

ts IHI
ts ILl

Set up Time, HIGH or LOW
I n or Kn to eP n

3.0
3.0

3.0
3.0

3.0
3.0

th IHI
th ILl

Hold Time, HIGH or LOW
I n or Kn to eP n

1.0
1.0

1.0
1.0

1.0

twlHI
twiLl

eP n Pulse Width, HIGH
or LOW

4.0
5.0

4.0
5.0

4.0
5.0

ns

twiLl

COn or SOn Pulse Width LOW

4.0

4.0

4.0

ns

tree

Recovery Time
COn or SOn to ep

2.0

2.0

2.0

ns

ns

fo

II

FAST AND LS TTL DATA

4-27

II

®

MOTOROLA

MC54f112

Advance Information
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
DESCRIPTION - MC54F/74F112 contains two independent, highspeed JK flip-flops with Direct Set and Clear inputs. Synchronous
state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly
related to the transition time. The J and K inputs can change when
the clock is in either state without affecting the flip·flop, provided
that they are in the desired state during the recommended setup
and hold times relative to the falling edge of the clock. A LOW
signal on SD or CD prevents clocking and forces Q or Q HIGH,
respectively. Simultaneous LOW signals on SD and CD force both
Q and Q HIGH.

MC74fl12

DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
FAST"

SCHOTTKY TTL

LOGIC DIAGRAM (one half shawnl
LOGIC SYMBOL

30:

O---t--+-<>(

D

E::::!::::====~D

C3===~~U

1

CP

2

K

O

5

0

6

15

VCC ~ Pin 16
GND ~ Pin 8

CP--------+-------------------------~

10

TRUTH TABLE
INPUTS
@tn

13

CP

12

K CD 0

OUTPUT
@tn

+

J

K

0

L
L
H
H

L
H
L
H

On
L
H
On

1

14

CONNECTION DIAGRAM

Asynchronous Inputs:

LOW input to SD sets 0 to HIGH level
LOW input to CD sets 0 to LOW level
Clear and Set are independent of clock

VCC

Simultaneous LOW on CD and SD
makes both 0 and HIGH

CD1

a

CD2

tn ~ Bit time before clock pulse
tn + 1 ~ Bit time after clock pulse
H ~ HIGH Voltage Level
L ~ LOW Voltage Level

CP2

F;=f=E~~K2

FAST AND LS TTL DATA

4-28

MC54F/74F112

GUARANTEED OPERATING RANGES
MIN

TYP

MAX

UNIT

VCC

Supply Voltage'

54
74

4.50
4.75

5.0
5.0

5.50
5.25

V

TA

Operating Ambient Temperature Range

54
74

-55
0

25
25

125
70

'c

10H

Output Current -

High-

54,74

-1.0

mA

10L

Output Current -

Low

54,74

20

mA

SYMBOL

PARAMETER

*74F devices may be operated over the 4.5 to 5.5 V supply range where they will meet the specifications of 54f devices over the 0" to 70D e

temperature range.

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

LIMITS

PARAMETER

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

VIK

Input Clamp Diode Voltage

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

Input HIGH Current

MIN

TYP

2.0

I

I

54

2.5

74

2.7

V

Guaranteed Input HIGH Voltage

V

Guaranteed Input LOW Voltage

-1.2

V

= -18 mA
VCC = MIN
= -1.0 mA
VCC = MIN
10H = -1.0 mA
10L = 20 mA
VCC = MIN
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V

V

3.4

V

0.35

TEST CONDITIONS

0.8

3.4

Input LOW Current
(J and K Inputs)
IlL

UNITS

MAX

0.5

V

20

p.A

100

p.A

liN

10H

-0.6

mA

(CP Inputs)

-2.4

mA

(CD and So Inputs)

-3.0

mA

-150

mA

VCC

= MAX, VOUT = 0 V

19

mA

VCC

= MAX, VCP = 0 V

lOS

Output Short Circuit
Current (Note 2)

ICC

Power Supply Current

-60
12

VCC

II

= MAX, VIN = 0.5 V

I

NOTES:
1. For conditions such as MIN or MAX, use the appropriate value specified under guaranteed operating ranges.
2. Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS
54174F
SYMBOL

TA
VCC
CL

PARAMETER
MIN

TYP

f max

Maximum Clock Frequency

110

130

tpLH
tpHL

Propagation Delay
CP n to an or an

2.0
2.0

5.0
5.0

tPLH
tpHL

Propagation Delay
COn or SOn to an or an

2.0
2.0

4.5
4.5

MIN

MAX

6.5
6.5

2.0
2.0

7.5
7.5

ns

6.5
6.5

2.0
2.0

7.5
7.5

ns

MAX

MIN

MAX

MHz

FAST AND LS TTL DATA

4-29

74F

54F

TA = -55to +125'C TA = Oto +70'C
VCC = 5.0 V ±10% VCC = 5.0 V±10% UNITS
CL = 50 pF
CL = 50 pF

= +25'C
= +5.0 V
= 50 pF

MC54F174F112

AC OPERATING REQUIREMENTS
54n4F
SYMBOL

PARAMETER
MIN

Is IHI
ts ILl

Set up Time, HIGH or LOW
I n Qr Kn to CP n

Ih IHI
th ILl

Hold Time, HIGH or LOW
I n or Kn to CP n

tw IHI
twiLl

54F

TYP

74F

TA = -55 to + 125'C TA = Oto +70'C
UNITS
VCC = 5.0 V ±10% VCC = 5.0 V ± 10°1<

TA = +25'C
VCC = +5.0 V
MAX

MIN

MAX

MIN

MAX

4.0
3.0

4.0
3.0

0
0

0
0

CPn Pulse Width, HIGH or LOW

4.5
4.5

4.5
4.5

ns

twiLl

COn or SOn Pulse Width LOW

4.5

4.5

ns

tree

Recovery Time COn or SOn to CP

4.0

5.0

ns

AC TEST CIRCUIT

>"---"---"--0

Test Point for High Impedance Scopes

R2=500n
±10%
For 50 n scopes, add a
450 n resistor in series
with Ihe scope and delete
R2.

Fig. 1

FAST AND LS TTL DATA

4-30

ns

®

MOTOROLA.

MC54F113
MC74F113

Advance Information
DUAL JK NEGATIVE EDGE·TRIGGERED FLlp·FLOP
DESCRIPTION - MC54F174F113 offers individual J, K, Set and
Clock inputs. When the clock goes HIGH the inputs are enabled
and data may be entered. The logic level of the J and K inputs
may be changed when the clock pulse is in either state and the
bistable will perform according to the Truth Table as long as
minimum setup and hold times are observed. Input data is trans·
ferred to the outputs on the falling edge of the clock pulse.

DUALJK
EDGE·TRIGGERED FLlp·FLOP
·FAST'"

SCHOTTI(Y TTL

LOGIC DIAGRAM (one half shown)
LOGIC SYMBOL

a--+-o(

)0-+---0

I=!:::=;-- So
CP--------~------------------~

K

@tn

I

CP

2

K

Vee = Pin 14
GNO = Pin 7

so 5
a

a

6

10

liusoa 9

TRUTH TABLE
INPUTS

30
4

13

CP

12

K

OUTPUT
@tn + I

J

K

a

L
L
H
H

L
H
L
H

an
L
H
an

a

8

CONNECTION DIAGRAM
Asynchronous Inputs:
LOW input to So sets a to HIGH level
Set is independent of clock
tn = Bit time before clock pulse
tn + I = Bit time after clock pulse
H = HIGH Voltage Level
L = LOW Voltage Level

FAST AND LS TTL DATA

4·31

II

II

MC54F174F113

GUARANTEED OPERATING RANGES
SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

Supply Voltage"

54
74

4.50
4.75

5.0
5.0

5.50
5.25

V

TA

Operating Ambient Temperature Range

54
74

-55
0

25
25

125
70

"C

10H

Output Current -

High

54,74

-1.0

mA

10L

Output Current -

Low

54,74

20

mA

VCC

"
*74F devices may be operated over the 4.5 to 5.5 V supply range where they Will meet the specifications
of 54F devices over the 0° to 70°C
temperature range.

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL
VIH

Input HIGH Voltage

VIL

Input LOW Voltage

VIK

Input Clamp Diode Voltage

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

LIMITS

PARAMETER

MIN

TYP

I

I

Power Supply Current

"Guaranteed Input LOW Voltage

-1.2

= -18 mA
= -1.0 mA

V

liN

3.4

V

IOH

74

2.7

3.4

V

IOH = -1.0 mA

0.35

(CD and So Inputs)

ICC

Guaranteed Input HIGH Voltage

V

2.5

(CP Inputs)
Output Short Circuit
Current (Note 2)

V

54

Input HIGH Current

lOS

TEST CONDITIONS

0.8

2.0

Input LOW Current
(J and K Inputs)
IlL

UNITS

MAX

-60
12

0.5

V

20

pA

100

pA

-0.6

mA

-2.4

mA

= 20 mA
= MAX, VIN
VCC = MAX, VIN
IOL

VCC

VCC = MIN
VCC = MIN
VCC = MIN
= 2.7 V
= 7.0 V

VCC = MAX, VIN = 0.5 V

-3.0

mA

-150

mA

VCC = MAX, VOUT = 0 V

19

mA

VCC = MAX, VCP = 0 V

NOTES:
1. For conditions such as MIN or MAX. use the appropriate value specified under guaranteed operating ranges.
2. Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS
54n4F
SYMBOL

54F

PARAMETER
MIN

TYP

f max

Maximum Clock Frequency

110

130

tpLH
tpHL

Propagation Delay
CP n to On or an

2.0
2.0

4.0
4.0

tpLH
tPHL

Propagation Delay
SOn to On or an

2.0
2.0

4.5
4.5

MAX

MIN

MIN

MAX

6.0
6.0

2.0
2.0

7.0
7.0

MAX

ns

6.5
6.5

2.0
2.0

7.5
7.5

ns

MHz

FAST AND LS TTL DATA

4-32

74F

TA = -55 to + 125"C TA = Oto +70"C
VCC = 5.0 V ±10% VCC = 5.0 V ±10% UNITS
CL=50pF
CL = 50 pF

TA = +25"C
VCC = +5.0 V
CL = 50 pF

MC54F/74F113

AC OPERATING REQUIREMENTS
54F

54/74F

SYMBOL

MIN
ts (HI
ts (Ll

Set up Time. HIGH or LOW
I n or Kn to CP n

th (HI
th (Ll

I n or Kn to CP n

Hold Time, HIGH or LOW

TYP

74F

TA= -55ta+125°e TA = Ota +70o e
UNITS
Vee = 5.0 V :tl0% Vee = 5.0 V :tl0%

TA = +25°e
Vee = +5.0 V

PARAMETER

MAX

MIN

MAX

MIN

4.0
3.0

4.0
3.0

0
0

0

4.5
4.5

4.5
4.5

0

MAX

ns

tw(HI
twILl

CP n Pulse Width,

twILl

SOn Pulse Width LOW

4.5

4.5

ns

tree

Recovery Time SOn to ep

4.0

5.0

ns

HIGH or LOW

AC TEST CIRCUIT

>---,.----e---{)

Test Point for High Impedance Scopes

R2 = 500

n

±10%

For 50 n scopes, add a
450 n resistor in series
with the scope and delete
R2.
Fig. 1

FAST AND LS TTL DATA

4-33

ns

®

MOTOROLA

MC54Fl14
MC74Fl14

Advance Information
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
(WITH COMMON CLOCKS AND CLEARS)
DESCRIPTION - MC54F/74F114 contains two high:speed JK flipflops with common clock and Clear inputs. Synchronous state
changes are initiated by the falling edge of the clock. Triggering
occurs at a voltage level of the clock and is not directly related to
the transition time. The J and K inputs can change when the clock
is in either state without affecting the flip-flop, provided that they
are in the desired state during the recommended setup and hold
times relative to the falling edge of the clock. A LOW signal on
So or l:o prevents clocking and forces Q or 5 HIGH, respectively.
Simultaneous LOW signals on So and l:o force both Q and 5
HIGH.

DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
FAST'·

SCHOTTKY TTL

LOGIC DIAGRAM (one half shown)
LOGIC SYMBOL

0--_.....-0(.
10
CD-~~--~~----+-J~-+----_---r---SD

11 J

SD Q

13

F=-----K
CP--~---+-----------~

Vcc = Pin 14
GND = Pin 7

TRUTH TABLE
INPUTS
(u't n

J
L
L
H
H

OUTPUT
(ll

tn

+

K

a

L
H
L
H

an
L
H
On

1

CONNECTION DIAGRAM

Asynchronous Inputs:
LOW input to So sets a to HIGH level
LOW input to CD sets a to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and So
makes both a and 0 HIGH
H = HIGH Voltage Level
L = LOW Voltage Level
tn = Bit time before clock pulse
tn + 1 = Bit time after clock pulse

FAST AND LS TTL DATA

4-34

MC54F/74F114

GUARANTEED OPERATING RANGES
MIN

TYP

MAX

UNIT

Supply Voltage"

54
74

4.50
4.75

5.0
5.0

5.50
5.25

V

TA

Operating Ambient Temperature Range

54
74

-55
0

25
25

125
70

'c

10H

Output Current -

High

54,74

- 1.0

mA

10L

Output Current -

Low

54,74

20

mA

PARAMETER

SYMBOL
VCC

..

*74F devices may be operated over the 4.5 to 5.5 V supplV range where they Will meet the specifications of 54F devices over the 0° to 70°C
temperature range.

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL
VIH

Input HIGH Voltage

VIL

Input LOW Voltage

VIK

Input Clamp Diode Voltage

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

LIMITS

PARAMETER

MIN

TYP

2.0

I
I

54

2.5

74

2.7

V

Guaranteed Input HIGH Voltage

V

Guaranteed Input LOW Voltage

-1.2

V

= -18 mA
VCC =
= -1.0 mA
VCC =
10H = -1.0 mA
10L = 20 mA
VCC =
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V

V

3.4

V

0.35

Input HIGH Current

0.5

V

20

"A

100

"A

-0.6

mA

(CP Inputs)

-2.4

mA

(CD and So Inputs)

-3.0

mA

-150
19

lOS

Output Short Circuit
Current (Note 2)

ICC

Power Supply Current

-60
12

TEST CONDITIONS

0.8

3.4

Input LOW Current
(J and K Inputs)
IlL

UNITS

MAX

liN

MIN

10H

MIN
MIN

II

= 0.5 V

VCC

=

MAX, VIN

mA

VCC

=

MAX, VOUT ~ 0 V

mA

VCC

=

MAX, VCP

I

=

0V

NOTES:
1. For conditions such as MIN or MAX, use the appropriate value specified under guaranteed operating ranges.
2 Not more than one output should be shorted at a time. nor for more than 1 second.

AC CHARACTERISTICS
54/74F
SYMBOL

54F

TA = +25'C
VCC = +5.0V
CL = 50 pF

PARAMETER
MIN

TYP

f max

Maximum Clock Frequency

100

120

tpLH
IpHL

Propagation Delay
CP n to Q n or an

3.3
3.3

5.0
5.5

tpLH
tPHL

Propagation Delay
COn or SOn to Q n or an

2.0
2.0

4.5
4.5

MAX

MIN

MAX

6.5
7.5

3.3
3.3

7.5
8.5

MIN

MAX

ns

6.5
6.5

2.0
2.0

7.5
7.5

ns

MHz

FAST AND LS TIL DATA

4-35

74F

TA = - 55 10 + 125'C TA=010+70'C
VCC = 5.0 V ±10% VCC = 5.0 V ±10% UNITS
CL = 50 pF
CL = 50 pF

MC54F174F114

AC OPERATING REQUIREMENTS
54/74F
SYMBOL

PARAMETER
MIN

Is (HI
Is (Ll

Set up Time, HIGH or LOW
I n or Kn to CP n

th (HI
th (Ll

I n or

Hold Time, HIGH or LOW
Kn to CPn

54F

TYP

74F

TA = - 55 to + 125'C TA = 010 +70'C
UNITS
VCC = 5.0V'±10% VCC = 5.0 V ±10%

TA = +25'C
VCC = +5.0 V
MAX

MIN

MAX

MIN

MAX

4.0
3.0

4.0
3.0

0
0

0
0

4.5
4.5

4.5
4.5

ns

ns

tw(HI
twILl

CP n Pulse Width,

twILl

COn or SOn Pulse Width LOW

4.5

4.5

ns

tree

Recovery Time COn or SOn to CP

4.0

5.0

ns

HIGH or LOW

AC TEST CIRCUIT

Test Point for High Impedance Scopes

II

R2 = 500!l
±10%
For 50 !l scopes, add a
450 !l resistor in series
with the scope and delete
R2.

Fig. 1

FAST AND LS TTL DATA

4-36

~\i1 (C~'i}[f 1). 33~

~v~~71 'i}[f1).33~

1-0F-8 DECODER/
DEMULTIPLEXER
1-0F-8 DECODER/DEMULTIPLEXER

FASTTM

DESCRIPTION - The MC54F174F138 is a high speed 1-01-8 Decoder/Demultiplexer. Thisdevice is ideally suited lor high speed bipolar
memory chip select address decoding. The multiple input enables
allow parallel expansion to a 1-01-24 decoder using just three F138
devices or to a 1-01-32 decoder using lour F138s and one inverter.

SCHOTTI{Y TTL

LOGIC SYMBOL

1 2 3

o
o

o

o

456

~

DEMULTIPLEXING CAPABILITY
MULTIPLE INPUT ENABLE FOR EASY EXPANSION
ACTIVE LOW MUTUALLY EXCLUSIVE OUTPUTS
INPUT CLAMP DIODES LIMIT HIGH SPEED TERMINATION
EFFECTS

VCC = Pin 16
GND= Pin 8

CONNECTION DIAGRAM
DIP (TOP VIEWI
LOGIC DIAGRAM
VCC = Pin 16
GND = Pin 8
= Pin Numbers

o

16
15

2

3
4

13

5

12

6

10

7

8

'---~

9

J Suffix - Case 620-08
(Ceramic)
N Suffix - Case 648·05
(Plastic)
NOTE:

The Flatpak version has the same
PInOuts(Connectlon Diagram)as

the Duel In-Line Package.

FAST AND LS TTL DATA

4-37

II

MC54F174F138
GUARANTEED OPERATING RANGES
SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

54, 74

4.5

5.0

5.5

V

54
74

-55
0

25
25

125
70

°c

VCC

Supply Voltage

TA

Operating Ambient Temperature Range

IOH

Output Current -

High

54, 74

-1.0

mA

IOL

Output Current -

Low

54, 74

20

mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

MIN

LIMITS
TYP

UNITS

MAX

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

0.8

V

VIK

Input pamp Diode Voltage

-1.2

·V

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

Input HIGH Current

IlL

Input LOW Current

lOS

Output Short Circuit
Current (Note 2)

ICC

Power Supply Current

2.0

V

TEST CONDITIONS
Guaranteed Input HIGH Voltage
Guaranteed Input LOW Voltage
VCC= MIN, liN = -18 mA

1~4,74

2.5

V

10H = -1.0 mA

VCC =4.50V

I

2.7

V

10H = -1.0 mA

VCC=4.75V

0.5

V

10L= 20 mA

VCC = MIN

20

p.A

VCC = MAX, VIN = 2.7 V

74

-60

0.1

mA

VCC = MAX, VIN = 7.0 V

-0.6

mA

VCC = MAX, VIN = 0.5 V

-150

mA

VCC = MAX, VOUT = 0 V

20

mA

VCC= MAX

AC CHARACTERISTICS

S YMBOL

PARAMETER

LEVELS
OF
DELAY

54174F
TA = +25°C
VCC = +5.0 V
CL = 50 pF
MAX
MIN

54F
TA = -55°C to +125°C
VCC=5.0V±10%
CL = 50 pF
MIN
MAX

74F
TA = O°C to 70°C
VCC = 5.0V ±10%
CL = 50 pF
MIN
MAX

UNITS

tPLH
tPHL

Propagation Delay,
Address to Output

3

3.0
3.5

7·5
8.0

3.0

3.:5

12
9.5

3.0
3.5

8.5
9.0

ns
ns

tpLH
tPHL

Enable to Output
E1 0rE2

2

3.5
3.0

7.0
7.0

3.5
3.0

11
8.0

3.5
3.0

8.0
7.5

ns
ns

tpLH
tpHL

Enable to Output
E3

3

4.0
3.5

8.0
7.5

4.0
3.5

12.5
8.5

4.0
3.5

9.0
8.5

ns
ns

NOTES.
1 For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions forthe applicable
deVice type
2 Not more than one output should be shorted at a time, nor for more than 1 second.

FUNCTIONAL DESCRIPTION - The decoder accepts three binary weighted inputs (AO, Al, A2)
and when enabled provides eight mutually exclusive active LOW outputs (00-07). The F138 features three Enable inputs, two active LOW (El, E2) and one active HIGH (E3). All outputs will be
HIGH unless E1 and E2 are LOW and E3 is HIGH. This mUltiple enable function allows easy parallel expansion of the device to a 1-of-32 (5 lines to 32 lines) decoder with just four F138s and one
inverter.
The F138 can be used as an 8-output demultiplexer by using one of the active LOW Enable inputs
as the data input and the other Enable inputs as strobes. The Enable inputs which are not used must
be permanently tied to their appropriate active HIGH or active LOW state.

FAST AND LS TTL DATA

4-38

MC54F/74F138

TRUTH TABLE
OUTPUTS

INPUTS

H
L
X

E1

E2

E3

AO

A1

A2

00

01

02

03

04

Os

0&

07

H

X

X

X

X

H

H

H

H

H

H

H

H

X

H

X
X

X

X

X

H

H

H

H

H

H

H

H

X

X

L

X

X

X

H

H

H

H

H

H

H

H

L

L

H

L

L

L

L

H

H

H

H

H

H

H

L

L

H

H

L

L

H

L

H

H

H

H

H

H

L

L

H

L

H

L

H

H

L

H

H

H

H

H

L

L

H

H

H

L

H

H

H

L

H

H

H

H

L

L

H

L

L

H

H

H

H

H

H

H

L

H

H

L

H

H

H

H

H

L
H-

H

L

L

H

H

L

L

H

L

H

H

H

H

H

H

H

H

L

H

L

L

H

H

H

H

H

H

H

H

H

H

H

L

HIGH Voltage Level
LOW Voltage Level
Don't Care

AO~r---------------~r-----------------r----------------'

II
00 ____

w _________ • _________________________________ • _____ - - . - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - . - - - - - - - - - -

Ci 31

AC TEST CIRCUIT

OUT

Test Point for High Impedance Scopes

R2= SOOO

±10%

For SO 0 scopes, add a

450 n resistor in senes
with the scope and delete

R2.

Fig. 1

AC WAVEFORMS

VIN J , . S V

\,.SV

~lPHL
VOUT

VIN ' , . S V

~lPLH

t,.SV

~IPHL
~IPLH
VOUT~V

~~_,._S_V_______J~V
Fig. 2

Fig. 3

FAST AND LS TTL DATA

4-39

II

®

MOTOROLA

MC54F139
MC74F139

DUAL 1-0F-4 DECODER
FASTTM

DUAL 1-0F-4 DECODER
DESCRIPTION - The MC54F174F139 is a high speed Dual 1-of-4
Decoder/Demultiplexer. The device has two independent decoders,
each accepting two inputs and providing four mutually exclusive
active LOW Outputs. Each decoder has an active LOW Enable input
which can be used as a data input for a 4-output demultiplexer. Each
half of the F139 can be used as a function generator providing all four
minterms of two variables.

•
•
•
•

SCHOTTKY TTL

LOGIC SYMBOL

2

MULTIFUNCTION CAPABILITY
TWO COMPLETELY INDEPENDENT 1-0F-4 DECODERS
ACTIVE LOW MUTUALLY EXCLUSIVE OUTPUTS
INPUT CLAMP DIODES LIMIT HIGH SPEED TERMINATION
EFFECTS

3

DECODER

•

5

6

16

14 13

DECODER b

8

7

12 "

VCC

10 9

= Pin 16

GND' Pin 8

LOGIC DIAGRAM
AOa

CD

A1a

®

CONNECTION DIAGRAM
DIP (TOP VIEW)

Eb

@)

16

15

,.

VCC = Pin 16

J Suffix - Case 620-08

GND = Pin 8

o

N Suffix -

= Pin Numbers

(Ceramic)
Case 648-05
(Plastic)

NOTE:
The Flatpak verSion hasthesame
pinouts (ConnectIon Diagram) as
the Dual In-Line Package

FAST AND LS TTL DATA

4-40

MC54F/74F139

GUARANTEED OPERATING RANGES
SYMBOL
VCC

PARAMETER
Supply Voltage

MIN

TYP

MAX

UNIT

54, 74

4.5

5.0

5.5

V

54
74

-55
0

25
25

125
70

DC

TA

Operating Ambient Temperature Range

IOH

Output Current -

High

54, 74

-1.0

rnA

IOL

Output Current -

Low

54, 74

20

rnA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

MIN

LIMITS
TYP

MAX

TEST CONDITIONS

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

0.8

V

Guaranteed Input LOW Voltage

VIK

Input Clamp Diode Voltage

-1.2

V

VCC= MIN,IIN= -18 rnA

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

Input HIGH Current

IlL

Input LOW Current

lOS

Output Short Circuit
Current (Note 2)

ICC

Power Supply Current

2.0

UNITS
V

Guaranteed Input HIGH Voltage

l54,74

2.5

V

10H =-1.0 rnA

VCC =~:5_0V

I 74

2.7

V

IOH=-1.0rnA

VCC=4.7SV

IOL= 20 rnA

VCC= MIN

-60

0.5

V

20

p.A

VCC = MAX, VIN = 2.7 V

0.1

rnA

VCC = MAX, VIN = 7.0 V

-0.6

rnA

VCC = MAX, VIN = 0.5 V

-150

rnA

VCC = MAX, VOUT = 0 V

20

rnA

VCC= MAX

II

AC CHARACTERISTICS:

SYMBOL

PARAMETER

54174F
TA = +25°C
VCC = +5.0 V
CL = 50 pF
MIN
MAX

54F
TA = -55 DC to +125 DC
VCC = 5.0 V ±1 0%
CL = 50 pF
MIN
MAX

74F
TA = ODC to 70°C
VCC =5.0V ±10%
CL = 50 pF
MIN
MAX

UNITS

tpLH
tpHL

Propagation Delay,
Address to Output

3.5
4.0

7.5
8.0

2.5
3.5

12.0
9.5

3.0
4.0

8.5
9.0

ns
ns

tPLH
tpHL

Enable to Output

3.5
3.0

7.0
6.5

3.0
2.5

9.0
8.0

3.5
3.0

8.0
7.5

ns
ns

NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
devIce type.
2. Not more than one output should be shorted at a time. nor for more than 1 second.

FUNCTIONAL DESCRIPTION - The F139 is a high speed dual 1-of-4 decoder/demultiplexer
fabricated with the Schottky barrier diode process. The device has two independent decoders, each
of which accept two binary weighted inputs (AO, A1) and provide four mutually exclusive active
LOWoutputs (00-03). Each decoder has an active LOW Enable (E). When Eis HIGH all outputs are
forced HIGH. The enable can be used as the data input for a 4-output demultiplexer application.
Each half of the F139 generates all four miniterms of two variables. These four miniterms are
useful in some applications, replacing multiple gate functions as shown in Fig. a, and thereby
reducing the number of packages required in a logic network.

FAST AND LS TTL DATA

4-41

MC54F174F139

TRUTH TABLE
INPUTS

AO

A1

00

°1

°2

H

X

X

H

H

H

H

L
L
L
L

L

L

H

H

H

H

L
L

H

L

H

H

L

H

H

H

L

H

H

H

H

H

H

L

H
l

OUTPUTS

E

03

HIGH Voltage Level
...

X

LOW Voltage Level

Don't Care

Fig .•

AC WAVEFORMS

VINJ1.5V

\1.5V

~tPHLj
VOUT

VIN \

~tPLHl

~~_1._5_V

__________

1.5 V

~-t-PH-L-----'

~~

VOUT

1.5 V

Fig. 1

Fig. 2

AC TEST CIRCUIT

OUT

>---....---~--{) Test Point for High Impedance Scopes
R2= 500n
±10%

For 50

n scopes, add a

450 n resistor in series
with the scope and delete

R2.
Fig. 3

FAST AND LS TTL DATA

4-42

®

MOTOROLA

MC54F148
MC74F148

Advance Information
8-LlNE TO 3-LlNE
PRIORITY ENCODER
The MC54/74F148 provides three bits of binary coded output representing the position
of the highest order active input, along with an output indicating the presence of any
active input. It is easily expanded via input and output enables to provide priority encoding over many bits .
..
o
o
•
•

Encodes Eight Data Lines in Priority
Provides 3-Bit Binary Priority Code
Input Enable Capability
Signals When Data Present on Any Input
Cascadable for Priority Encoding of n Bits
10

11

1101

(11)

-

12 (12)

AD
13 (13)

#.

14 (1)

•

15 (2)
16 (3)

17

Ei

CASE 648·05

(4)

(5)

CASE 751 B·01

14

Vee

15"

EQ

16

GS

17

13

Ei

12

A2

11

Al

10

Ao

GND

Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should
not be used to estimate propagation delays.

CONNECTION
DIAGRAM

GUARANTEED OPERATING RANGES
Symbol
VCC

Min

Typ

Max

Unit

54,74

4.5

5

5.5

V

54

-55

25

125

74

0

25

70

Parameter

Supply Voltage

'c

TA

Operating Ambient Temperature Range

IOH

Output Current -

High

54,74

-1

mA

IOl

Output Current -

low

54,74

20

mA

FAST AND LS TTL DATA

4-43

II

MC54F148 • MC74F148
FUNCTIONAL DESCRIPTION·
The 'Fl48 8-input priority encoder accepts data from
eight active LOW inputs (iO-i7) and provides a binary
representation on the three active LOW outputs. A priority
is assigned to each input so that when two or more inputs
are simultaneously active, the input with the highest
priority is represented on the output, with input line 7
having the highest priority. A HIGH on the Enable Input
(8) will force all outputs to the inactive (HIGH) state and
allow new data to settle without producing erroneous

information at the outputs. A Group Signal output (GS)
and Enable Output (EO) are provided along with the three
priority data outputs (A2, Al, Ao). GS is active LOW when
any input is LOW: this indicates when any input is active.
EO is active LOW when all inputs are HIGH. Using the
Enable Output along with the Enable Input allows cascading for priority encoding on any number of input signals. Both EO and GS are in the inactive HIGH state when
the Enable Input is HIGH.

TRUTH TABLE
Inputs

Outputs

EI

10

I,

12

13

i4

15

16

f7

GS

Ao

A,

A2

EO

H
L
L
L
L

X
H
X
X
X

X
H
X
X
X

X
H
X
X
X

X
H
X
X
X

X
H
X
X
X

X
H
X
X
L

X
H
X
L
H

X
H
L
H
H

H
H
L
L
L

H
H
L
H
L

H
H
L
L
H

H
H
L
L
L

H
L
H
H
H

L
L
L
L
L

X
X
X
X,
L

X
X
X
L
H

X
X
L
H
H

X
L
H
H
H

L
H
H
H
H

H
H
H
H
H

H
H
H
H
H

H
H
H
H
H

L
L
L
L
L

H
L
H
L
H

H
L
L
H
H

L
H
H
H
H

H
H
H
H
H

H ~ HIGH Voltage Level
L ~ LOW Voltage Level
'X = Immaterial

II

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified I
Symbol
VIH

Input HIGH Voltage

VIL

Input LOW Voltage

VIK

Input Clamp Diode Voltage

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

IlL

Limits

Parameter

Min

Typ

Max

Test Conditions

V

Guaranteed Input HIGH Voltage

0.8

V

Guaranteed Input LOW Voltage

-1.2

V

2

I
J

Units

liN = -18 mA

VCC = MIN

54,74

2.5

3.4

V

10H = -1 mA

VCC = 4.5 V

74

2.7

3.4

V

10H = -1 mA

VCC = 4.75 V

0.5

V

10L = 20 mA

VCC ~ MIN

20

".A

VCC = MAX. VIN - 2.7 V
VCC = MAX. VIN = 7 V

0.35

Input HIGH Current

100

".A

10. EI

-0.6

mA

11-17

-1.2

mA

-150

mA

VCC = MAX. VOUT -

35

mA

VCC = MAX. VIN = 4.5 V

lOS

Output Short Circuit Current (Note 2)

ICC

Power Supply Current

-60
23

VCC = MAX. VIN = 0.5 V

NOTES: 1. For conditions such as MIN or MAX, use the appropnate value specified under guaranteed operatmg ranges.
2. Not more than one output should be shorted at a time, nor for more than 1 second,

FAST AND LS TTL DATA

4-44

aV

MC54F148 • MC74F148

'F148

'F148
EO

AO

GS

Al

Application
16-lnput Priority Encoder

AC CHARACTERISTICS

Symbol

Parameter

54F174F

54F

74F

TA = +25'C
VCC=+5V
CL = 50 pF

TA'VCC =
Mil
CL = 50 pF

TA'VCC =
Com
CL = 50 pF

Units

Min

Typ

Max

Min

Max

Min

Max

tpLH
tpHL

Propagation Delay
In to An

3.5
4

7
8

9
10.5

3.5
4

11
13

3.5
4

.10
12

ns

tpLH
tpHL

Propagation Delay
In to EO

2.5
2

5
5.5

6.5
7.5

2.5
2

8.5
9.5

2.5
2

7.5
8.5

ns

tpLH
tpHL

Propagation Delay
In to GS

3
2

7
6

9
8

3
2

11
10

3
2

10
9

ns

tpLH
tpHL

Propagation Delay

Ei to An

3.5
3

6.5
6

8.5
8

3.5
3

10.5
10

3.5
3

9.5
9

ns

tpLH
tpHL

Propagation Delay
Ei to GS

2.5
3

5
6

7
7.5

2.5
3

9
10

2.5
3

8
8.5

ns

tpLH
tpHL

Ei to

Propagation Delay
EO

3
4.5

5.5
8

7
10.5

3
4.5

9
13

3
4.5

8
12

ns

FAST AND LS TTL DATA

4-45

®

ItIIOTOROLA

MC54F151
MC74F151
8-INPUT MULTIPLEXER
DESCRIPTION - The MC54Fn4F151 is a high-speed a-input digital multiplexer. It provides in one package, the ability to select
one line of data from up to eight sources. The 'F151 can be used
as a universal function generator to generate any logic function
offour variables. Both asserted and negated outputs are provided.
The 'F151 is a logic implementation of a single pole, a-position
switch with the switch position controlled by the state of three
Select inputs, SO, 51, 52. The Enable input (E) is active LOW. The
logic function provided at the output is:
Z = E'(lO'50'51 '52
12' 50' 51 '52
14'50'51'52
16'50'51'52

8-INPUT MULTIPLEXER

FAST'·

SCHOTTKY TTL

+ 11'50'51'52 +
+ 13' 50' 51 ,52 +
+ 15'50'51'52 +
+ 17'50'51'52)
LOGIC SYMBOL
LOGIC DIAGRAM
12
13
14
15
1
2
3
4

zz

Z

5

Z

6

11 10 9

Vee = Pin 16
GND = Pin 8
TRUTH TABLE
OUTPUTS

INPUTS

E

S2

SI

So

Z

H
L
L
L

X
L
L
L

X
L
L
H

X
L
H
L

H
io
il
i2

Z
L
10
11
12

L
L
L
L
L

L
H
H
H
H

H
L
L
H
H

H
L
H
L
H

13
i4
i5
is
17

13
14
15
16
17

CONNECTION DIAGRAM

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

FAST AND LS TTL DATA

4-46

MC54F/74F151

GUARANTEED OPERATING RANGES
SYMBOL
VCC

PARAMETER
Supply Voltage

I

54.74
54
74

MIN

TYP

MAX

UNIT

4.50

5.0

5.50

V

-55
0

25
25

125
70

·C

TA

Operating Ambient Temperature Range

10H

Output Current -

High

54.74

-1.0

mA

10L

Output Current -

Low

54.74

20

mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

LIMITS

PARAMETER

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

VIK

Input Clamp Diode Voltage

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

Input HIGH Curren't

IlL

I nput LOW Cu rrent

lOS

Output Short Circuit
Current (Note 2)

ICC

Power Supply Current

MIN

TYP

UNITS

MAX

2.0
0.8

2.5

I

2.7

74

V

Guaranteed Input HIGH Voltage

V

Guaranteed Input LOW Voltage

V

100

pA

-0.6

mA

= -18 mA
VCC = MIN
= '71.0 mA VCC = 4.50V
VCC = 4.75V
IOH = -1.0 mA
10L = 20 mA
VCC = MIN
VCC = MAX. VIN = 2.7 V
VCC = MAX. VIN = 7.0 V
VCC = MAX. VIN = 0.5 V

-150

mA

VCC

=

MAX. VOUT

21

mA

VCC

=

MAX, VIN

-1.2
1 54• 74

3.4

V

3.4

V

0.35

-60
13.5

TEST CONDITIONS

0.5

V

20

pA

liN

10H

=0V

= 4.5 V

AC CHARACTERISTICS

54/74F
SYMBOL

TA
VCC
CL

PARAMETER

54F

= +25·C
= +5.0 V
= 50 pF

74F

TA = -55 to +125·C TA = Oto +70·C
VCC = 5.0 V ±10% VCC = 5.0 V ±10% UNITS
CL = 50 pF
CL = 50 pF

MIN

TYP

MAX

MIN

MAX

MIN

MAX

tpLH
tpHL

Propagation Delay
Sn toZ

4.0
3.2

6.2
5.6

8.0
6.1

3.5
3.0

10
8.0

3.5
3.2

9.0
7.0

ns

tPLH
tpHL

Propagation Delay
Sn to Z

4.5
4.5

9.9
7.1

13
9.0

3.0
4.0

17.5
11.5

4.0
4.0

15
10.5

ns

tpLH
tpHL

Propagation Delay
Eto Z

3.0
3.0

4.8
6.8

6.1
8.5

2.5
2.5

7.5
10.5

2.5
2.5

7.0
10

ns

tpLH
tpHL

Propagation Delay
EtoZ

5.0
3.5

7.3
5.4

9.5
7.0

3.0
3.0

14.5
9.5

4.0
3.5

11
8.0

ns

tpLH
tPHL

Propagation Delay
In to Z

2.5
1.5

4.3
2.9

5.7
4.0

2.5
1.5

7.5
6.0

2.5
1.5

6.5
5.0

ns

tpLH
tPHL

Propagation Delay
In to Z

3.0
3.0

7.6
5.2

9.5
6.5

2.5
3.0

11.5
8.0

2.5
3.0

11
7.5

ns

FAST AND LS TTL DATA

4-47

II

I

NOTES:
1. For conditions such as MIN or MAX. USB the appropriate value specified under guaranteed operating ranges.
2. Not more than one output should be shorted at a time, nor for more than' second.

®

MOTOROLA

MC54F153
MC74F153

DUAL 4-INPUT MULTIPLEXER
DESCRIPTION - The MC54Fn4F153 is a high-speed Dual 4-lnput
Multiplexer with common select inputs and individual enable inputs for each section. It can select two lines of data from four
sources. The two buffered outputs present data in the true (noninverted) form. In addition to multiplexer operation, the F153 can
generate any two functions of three variables.

DUAL 4-INPUT MULTIPLEXER
FAST'· SCHOTTKY TTL

LOGIC DIAGRAM
13a

51

@ ®

So

lOb

@J @J
CONNECTION DIAGRAM DIP
(TOP VIEW)

16

II
VCC = Pin 16
GND

Za

o

= Pin 8
= Pin Numbers

2

15

3

14

4

13

5

12

6

11

7

10

8

J Suffix - Case 620-08 (Ceramic)
N Suffix -

Case 648-05 (Plastic)

GUARANTEED OPERATING RANGES
SYMBOL

MIN

TYP

MAX

UNIT

54.74

4.5

5.0

5.5

V

54
74

-55
0

25
25

125
70

'c

-

-

-1.0

mA

20

mA

PARAMETER

VCC

Supply Voltage

TA

Operating Ambient Temperature Range

IOH

Output Current -

High

54,74

IOL

Output Current -

Low

54,74

FAST AND lS TTL DATA

4-48

MC54F/74F153

FUNCTIONAL DESCRIPTION
The F153 is a Dual 4-lnput Multiplexer. It can select two bits of data from up to four sources under the control of the
common Select Inputs (SO, 51). The two 4-input multiplexer circuits h~ve i.ndividual active LOW Enables (Ea, Eb) which
can be used to strobe the outputs independently. When the Enables (E a, Eb) are HIGH, the corresponding outputs (Za'
Zb) are forced LOW.
The F153 is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is determined by
the logic levels supplied to the two Select Inputs. The logic equations for the outputs are shown below:
Za = Ea' (lOa' 51 ,50
Zb = Eb'(lOb,51,50

+ 11a ,51 ' So + 12a' 51 ,50 + 13a ' 51 ' SO)
+ 11b'51'SO + 12b,S1,50 + 13b,S1'SO)

The F153 can be used to move data from a group of registers to a common output bus. The particular register from
which the data came would be determined by the state of the Select Inputs. A less obvious application is a function
generator. The F153 can generate two functions of three variables. This is useful for implementing highly irregular
random logic.

TRUTH TABLE

SELECT INPUTS
So
X
L
L
H
H
L
L
H
H

INPUTS (a or bl
E

S1
X
L
L
L
L
H
H
H
H

H
L
L
L
L
L
L
L
L

10
X
L
H
X
X
X
X
X
X

11
X
X
X
L
H
X
X
X
X

12
X
X
X
X
X
L
H
X
X

OUTPUT
13
X
X
X
X
X
X
X
L
H

Z

L
L
H
L
H
L
H
L
H

II

H = HIGH Voltage Level

l = LOW Voltage level
X = Immaterial

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

SYMBOL

PARAMETER

V,H

Input HIGH Voltage

V,L

Input LOW Voltage

V,K

Input Clamp Diode Voltage

VOH

Output HIGH Voltage

VOL

Output LOW Voltage
Input HIGH Current

IlL

Input LOW Current

lOS

Output Short Circuit
Current (Note 21

LIMITS
TYP MAX

2.0

154,74
1

IIH

ICC

MIN

74

V

Guaranteed Input HIGH Voltage

V

Guaranteed Input LOW Voltage

-1.2

V

mA

= -18 mA. VCC = MIN
= -1.0 mA
VCC = 4.50V
VCC = .4.75 V
IOL = -1.0 mA
10L = 20 mA
VCC = MIN
VIN = 2.7 V, VCC = MAX
Y,N = 7.0 V, VCC = MAX
VIN = 0.5 V, VCC = MAX

-150

mA

VOUT

20

mA

Y,N

V

2.7

Power Supply Current

TEST CONDITIONS

0.8
2.5

-60

UNITS

V
0.5

V

20

pA

0.1

mA

-0.6

liN

IOL

= 0 V, VCC =

= GND, VCC =

MAX
MAX

NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device

type.
2. Not more than one output should be shorted at a time, nor for more than 1 second.

FAST AND LS TTL DATA

4-49

MC54F/74F153

AC CHARACTERISTICS

SYMBOL

TA
VCC
CL

PARAMETER

S4174F
= +2S·C
= +S.O V
= SO pF

S4F
TA = -SS·C to + 12S·C
VCC = S.OV ±10%
CL = SO pF

74F
TA = O·Cto +70·C
'VCC = S.O V ± 10%
CL = SO pF

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

tpLH
tpHL

Propagation Delay
Sn to Zn

4.5
3.5

10.S
9.0

4.5
3.S

14
11

4.5
3.5

12
10.S

ns

tpLH
tpHL

Propagation Delay
En to Zn

4.5
3.0

9.0
7.0

4.S
2.5

11.S
9.0

4.5
2.S

10.S
8.0

ns

tpLH
tpHL

Propagation Delay
In to Zn

3.0
3.0

7.0
6.S

2.5
2.S

9.0
8.0

3.0
2.5

8.0
7.S

ns

AC TEST CIRCUIT

Test Point for High Impedance Scopes

R2=soon
±10%

For SO n scopes, add a
4S0
resistor in series
with the scope and delete R2.

n

II
PROPAGATION DELAY MEASUREMENTS
Non-Inverting

Inverting

VOUT

NOTES:
1. All input waveforms have the following characteristics:
Low Level

=

0V

High Level = 3.0 V
Rise and Fall Times (10% to 90%) = 2.5 ns
2. All timing is measured at 1.5 V unless otherwise indicated.

FAST AND LS TTL DATA

4-50

®

MOTOROLA

MC54F157
MC74F157
QUAD 2-INPUT MULTIPLEXER

DESCRIPTION - The MC54F/74F157 is a high-speed quad 2-input
mUltiplexer. Four bits of data from two sources can be selected using
the common Select and Enable inputs. The four buffered outputs
present the selected data in the true (non-inverted) form. The 'F157
can also be used to generate any four of the 16 different functions to

QUAD 2-INPUT
MULTIPLEXER

two variables.

FASTTM

LOGIC DIAGRAM

SCHOTTKY TTL

LOGIC SYMBOL

S
15
4

7
12

9

Za

Zb

Zc

Zd

IDa

2

11 a

3

lOb

5

11 b

6

10c

14

11 c

13

10d

11

11d

10

II
I

Vee ~ Pin 16
GND ~ Pin 8

CONNECTION DIAGRAM

TRUTH TABLE
INPUTS

Vee

OUTPUT

E

S

10

11

Z

H
L
L
L
L

X

X
X
X

X
L
H

L
H

X
X

L
L
H
L
H

H
H
L
L

IDa

E

11 a

10c
11c
Zc
10d

H ~ HIGH Voltage Level
L ~ LOW Voltage Level
X ;: Immaterial

,11d
Zd

J Suffix - Case 620-08
(Ceramic)
N Suffix - Case 648-05
(Plastic)

FAST AND LS TTL DATA

4-51

II

MC54F174F157

GUARANTEED OPERATING RANGES
SYMBOL

MIN

TYP

MAX

UNIT

54, 74

4.50

5.0

5.50

V

54
74

-55
0

25
25

125
70

°C

PARAMETER

VCC

Supply Voltage

TA

Operating Ambient Temperature Range

10H

Output Current - High

54, 74

-1.0

rnA

10L

Output Current - Low

54, 74

20

rnA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

MIN

LIMITS
TYP

UNITS

MAX

VIH

Input HIGH Voltage

2.0

VIL

Input LOW Voltage

O.B

V

VIK

Input Clamp Diode Voltage

-1.2

V

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

Input HIGH Current

IlL

Input LOW Current

lOS

Output Short Circuit
Current (Note 2)

ICC

Power Supply Current

TEST CONDITIONS

V

Guaranteed Input HIGH Voltage
Guaranteed Input LOW Voltage
liN = -1B rnA

VCC= MIN,

1 54,74

2.5

3.4

V

IOH=-1.0mA

VCC =4.50V

I

2.7

3.4

V

IOH=-1.0mA

VCC =4.75V

0.5

V

10L= 20 rnA

VCC= MIN

74

0.35

-60
15

20

/LA

VIN=2.7V

100

/LA

VIN= 7.0V

-0.6

rnA

VIN=0.5 V

VCC= MAX

-150

rnA

VOUT=OV

VCC= MAX

23

rnA

All Inputs = 4.5 V VCC= MAX

VCC= MAX

NOTES:
1. For conditions such as MIN or MAX, use the appropriate value specified under guaranteed operating ranges.
2. Not more than one output should be shofted at a time, nor for more than 1 second.

AC CHARACTERISTICS

S YMBOL

PARAMETER

54174F
TA = +25°C
VCC= +5.0 V
CL = 50 pF
MIN
TYP
MAX

54F
74F
TA = -55 to +125°C TA = 0 to +70oC
VCC= 5.0 V ±10% VCC = 5.0V ± 10% UNITS
CL = 50 pF
CL = 50 pF
MIN
MAX
MIN
MAX

tPLH
tpHL

Propagation Delay
S toZn

4.5
3.5

10.1
6.3

13
9.0

3.5
3.5

17
12.5

4.5
3.5

15
10.0

ns

tpLH
tPHL

Propagation Delay
E"toZn

5.0
3.B

7.6
5.3

10
7.0

5.0
3.8

15
B.5

5.0
3.B

11.5
B.O

ns

tPLH
tpHL

Propagation Delay
In to Zn

3.0
2.5

5.5
4.6

7.0
5.5

3.0
1.5

10
7.5

3.0

B.O
7.0

ns

2.-6

FUNCTIONAL DESCRIPTION - The F157 is a quad 2-input multiplexer. It selects four bits of data
from two sources under the control of a common Select input(S). The Enable input(E) is active LOW.
When Eis HIGH, all olthe outputs(Z) are forced LOW regardless of all other inputs. The F157 is the
logic implementation of a 4-pole, 2-position switch where the position of the switch is determined
by the logic levels supplied to the Select input. The logic equations for the outputs are shown below:
Za = E, (11 a' S + lOa' 5)
Zc = E, (11 c' S + 10c' S)

Zb=E' (l1b' S+IOb' 5)
Zd=E' (l1d' StlOd' 5)

A common useofthe F157 is the moving of data from twogroupsof registers to four common output
busses. The particular register from which the data comes is determined by the state of the Select
input. A less obvious use is as a function generator. The F1 57 can generate any four of the 16
different functions of two variables with one variable common. This is useful for implementing
highly irregular logic.

FAST AND LS TTL DATA

4-52

®

MOTOROLA

MC54F158
MC74F158

QUAD 2-INPUT MULTIPLEXER
DESCRIPTION - The MC54F174F158 is a high-speed quad 2-input
mUltiplexer. It selects four bits of data from two sources using the
common Select and Enable inputs. Thefourbuffered outputs present
the selected data in the inverted form. The 'F158 can also generate
any four of the 16 different functions of two variables.

QUAD 2-INPUT
MULTIPLEXER
FASTTM

SCHOTTKY TTL

LOGIC DIAGRAM
LOGIC SYMBOL

S
10c

S
E

4

7

15

lOa

2

11 a

3

lOb

5

11 b

6

12

10c

14

11 c

13

9

10d

11

11d

10

VCC = Pin 16
GND = Pin 8

CONNECTION DIAGRAM
TRUTH TABLE
INPUTS

OUTPUTS

10

S

10

h

Z

H
L
L
L
L

X
L
L

X
L
H

H
H

X
X

X
X
X
L

H
H
L
H
L

H

H = HIGH Voltage Level

L

=LOW Voltage Level

X;::;; Immaterial

J Suffix - Case 620-08
(Ceramic)
N Suffix - Case 648-05
(Plastic)

FAST AND LS TTL DATA

4-53

II

II

MC54F174F158

GUARANTEED OPERATING RANGES
SYMBOL
VCC

MIN

TYP

MAX

UNIT

54, 74

4.50

5.0

5.50

V

54
74

-55
0

25
25

125
70

°c

PARAMETER
Supply Voltage

TA

Operating Ambient Temperature Range

10H

Output Current -

High

54, 74

-1.0

mA

10l

Output Current -

low

54, 74

20

mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL
VIH

PARAMETER

LIMITS
TYP

MIN

Input HIGH Voltage

TEST CONDITIONS

UNITS

MAX

2.0

V

Guaranteed Input HIGH Voltage

Vil

Input lOW Voltage

0.8

V

Guaranteed Input lOW Voltage

VIK

Input Clamp Diode Voltage

-1.2

V

liN = -18 mA

VOH

Output HIGH Voltage

1 54,74
1

VOL

74

3.4

V

IOH=-1.0 mA

VCC =4.50V

2.7

3.4

V

IOH=-1.0 mA

VCC=4.75V

IOl= 20 mA

VCC= MIN

Output lOW Voltage

IIH

Input HIGH Current

III

Input lOW Current

lOS

Outpu.t Short Circuit
Current (Note 2)

ICC

Power Supply Current'

VCC= MIN,

2.5

0.35

-60
10

0.5

V

20

/loA

VIN =2.7V

VCC=MAX

100

/loA

VIN = 7.0V

-0.6

mA

VIN =0.5V

VCC=MAX

-150

mA

VOUT=OV

VCC=MAX

15

mA

VCC= MAX

NOTES:
1. For conditions such as MIN or MAX, use the appropriate value specified under guaranteed operating ranges.
2. Not more than one output should be shoned at a time, nor for more than 1 second.

AC CHARACTERISTICS

S YMBOl

PARAMETER

54174F
TA = +25°C
VCC= +5.0V
Cl = 50 pF
MIN
TYP
MAX

54F
74F
TA = -55 to +125°C TA = 0 to +70°C
VCC = 5.0V ±10% VCC= 5.0V± 10% UNITS
Cl = 50 pF
Cl = 50 pF
MIN
MAX
MIN
MAX

tplH
tPHl

Propagation Delay
Stol

4.0
4.0

6.4
6.9

8.5
9.0

4.0
4.0

10.5
10.5

4.0
4.0

9.5
10.5

ns

tplH
tpHl

Propagation Delay
Etoln

3.!!.
3.5

6.2
6.4

8.0
8.5

3.5
3.5

9.5
9.5

3.5
3.5

9.0
9.5

ns

tPlH
tpHl

Propagation Delay
In tol

3.0
1.5

4.4
3.3

5.9
4.5

2.5
1.5

8.5
6.0

3.0
1.5

7.0
5.5

ns

'ICC measured with outputs open and 4.5 V applied to all limits.

FUNCTIONAL DESCRIPTION - The F158 quad 2-input multiplexer selects four bits of data from
two sources underthe control of a common Select input(S) and presents the data in inverted form at
the four outputs. The Enable input tE) is active LOW. When Eis HIGH, all of the outputs(Z) are forced
HIGH regardless of all other inputs. The F158 is the logic implementation of a 4-pole, 2-position
switch wher/3 the position of the switch is determined by the logic levels supplied to the Select input.
A common use of the F158 is the moving of data from two groups of registers to four common
output busses. The particular register from which the data comes is determined by the state of the
Select input. A less obvious use is as a function generator. The Fl 58 can generate four functions of
two variables with one variable n common. This is useful for implementing gating functions.

FAST AND LS TTL DATA

4-54

®

MOTOROLA

MC541F160A
MC74F160A
MC54F162A
MC74F162A

SYNCHRONOUS PRESETTABLE
BCD DECADE COUNTER
The MC54174F160A and MC54174F162A are high-speed synchronous decade
counters operating in the BCD (8421) sequence. They are synchronously presettable for application in programmable dividers and have two types of Count Enable
inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The MC54174F160A has an asynchronous Master Reset input that
overrides all other inputs and forces the outputs LOW. The MC54174F162A has a
Synchronous Reset input that overrides counting and parallel loading and allows
the outputs to be simultaneously reset on the rising edge of the clock. The MC541
74F160A and MC54174F162A are high-speed versions of the MC54174F160 and
MC54174F162.

LOGIC SYMBOL
'MR for MC54/74F160A
• SA for MC54174F162A

-

" Synchronous Counting and Loading
" High-Speed Synchronous Expansion
" Typical Count Rate of 120 MHz

"

'0

PE

~7h~~4F162A

MC

CfP

,r

m

I~

i~~
,~o
,~

'CP

I~

"

I

4

,------1-----,

!~

:

al

7
11

al

--<>

a2

10

a2

14

a3

15

a3

DO

4

Dl

5

D2

12

D3

13

VCC = Pin 16
GND = Pin 8

TRUTH TABLE
INPUTS

SCHOTTKY TTL

OUTPUTS

=H

@tn"

Dn

On

an

L
H

L
H

H
L

CONNECTION DIAGRAM

t n ::; Bit time before clock positive~going transition

tn + 1 ::; Bit time after clock positive-going transition

H = HIGH Voltage Level
L = LOW Voltage Level

J Suffix - Case 620-08
(Ceramic)
N Suffix - Case 648-05
(Plastic)

FAST AND LS TTL DATA

4-66

MC54F174F175

LOGIC DIAGRAM
Dl

DD

Go

01 Ql

QO

Please note that this diagram is provided only for the understanding of logic operations and should 110t be used to estimate
propagation delays.

GUARANTEED OPERATING RANGES
SYMBOL

PARAMETER

VCC

Supply Voltage

TA

Operating Ambient Temperature Range

10H

Output Current -

High

10L

Output Current -

Low

MIN

TYP

54, 74

4.501

"5.0 "

54
74

-55
0

25
25

MAX
- 5.50

UNIT

L·

V

125
70

°c

54, 74

-1.0

mA

54, 74

20

mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

MIN

LIMITS
TYP

MAX

2.0

UNITS
V

TEST CONDITIONS
Guaranteed Input HIGH Voltage

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

0.8

V

Guaranteed Input LOW Voltage

VIK

Input Clamp Diode Voltage

-1.2

V

liN = -18 mA

VCC= MIN

V

10H = -1.0 mA

,VCC =4.50V

V

10H = -1.0 mA

VCC

V

10L= 20 mA

VCC= MIN

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

Input HIGH Current

IlL

Input LOW Current

lOS

Output Short Circuit
Current (Note 2)

ICC

Power Supply Current

1. 54,74

2.5

I

2.7

74

3.4
3.4
0.35

-60
22.5

0.5
20

Il A

VIN = 2.7V

VCC= MAX

100

Il A

VIN=7.0V

VCC= MAX

-0.6

mA

VIN = 0.5 V

VCC= MAX

-150

mA

VOUT= 0 V

VCC= MAX

mA

On = MR=4.5 V
CP=S

VCC= Max

34

NOTES:
1. For conditions such as MIN or MAX, use the appropriate value specified under guaranteed operating ranges.
2. Not more than one output should be shorted at a time, nor for more than 1 second.

FAST AND LS TTL DATA

4-67

=4:i5 V

II

MC54F174F175

AC CHARACTERISTICS

S YMBOL

PARAMETER

54174F
TA = +25°C
VCC= +5.0V
CL = 50 pF
MIN
TYP
MAX

54F
74F
TA - -55 to +125°C TA = 0 to +70 oC
VCC = 5.0 V ±10% VCC = 5.0 V ± 10% UNITS
CL = 50 pF
CL = 50 pF
MIN
MAX
MIN
MAX

f max

Maximum Clock Frequency

100

140

tpLH
tPHL

Propagation Delay
CPto Qn orOn

3.5
4.0

5.0
6.5

6.5
8.5

3.5

8.5

3.5

4.0

10.5

tpHL

Propagation Delay
MR to Qn

4.5

9.0

11.5

4.5

tpLH

Propagation Delay
MRto On

4.0

6.5

8.5

4.0

100

100

MHz

4.0

7.5
9.5

ns

15

4.5

13

ns

10

4.0

9.0

ns

AC OPERATING REQUIREMENTS

S YMBOL

PARAMETER

54174F
TA = +25°C
VCC=+5.0V
MIN
TYP
MAX

54F
74F
TA - -55 to +125°C TA - 0 to +70 oC
VCC = 5.0 V ±10% VCC = 5.0V ± 10% UNITS
MIN

MAX

MIN

MAX

ts (H)
ts (L)

Set up Time, HIGH or LOW
Dn to CP

3.0
3.0

3.0
3.0

3.0
3.0

th (H)
th (L)

Hold Time, HIGH or LOW
Dn to CP

1.0
1.0

1.0
1.0

1.0

tw(H)
twILl

CP Pulse Width, HIGH
or LOW

4.0
5.0

4.0
5.0

4.0
5.0

ns

twILl

MR Pulse Width LOW

5.0

5.0

5.0

ns

trec

Recovery Ti me
MR to CP

5.0

5.0

5.0

ns

FAST AND LS TTL DATA

4-68

ns

1.0

MC54F181
MC74F181

Advance Information
4-BIT ARITHMETIC
LOGIC UNIT

4-BIT ARITHMETIC LOGIC UNIT

FASpM

SCHOTTKY TTL

DESCRIPTION - The MC54F174F181 is a 4-bit Arithmetic Logic
Unit (ALU) which can perform all the possible 16 logic operations on
two variables and a variety of arithmetic operations. It is 40% faster
than the Schottky ALU and only consumes 30% as much power.
o PROVIDES 16 ARITHMETIC OPERATIONS
ADD. SUBTRACT. COMPARE. DOUBLE. PLUS TWELVE
OTHER ARITHMETIC OPERATIONS
o PROVIDES ALL 16 LOGIC OPERATIONS OFTWO VARIABLES
EXCLUSIVE-OR. COMPARE. AND. NAND. OR. NOR. PLUS
TEN OTHER LOGIC OPERATIONS
o FULL LOOI B and A < B.
The Function Table lists the arithmetic operations that are performed without a carry in. An incoming carry adds a one to each operation. Thus, select code LHHL generates A minus B minus 1 (2s
complement notation) without a carry in and generates A minus B when a carry is applied. Because
subtraction is actually performed by complementary addition (1 s complement), a carry out means
borrow; thus a carry is generated when there is no underflow and no carry is generated when there
is underflow. As indicated, this device can be used with either active-LOW inputs producing activeLOW outputs or with active-HIGH inputs producing active-HIGH outputs. For either case the table
lists the operations that are performed to the operands labeled inside the logic symbol.

FAST AND LS TTL DATA

4-71

--

II

MC54F174F181

AC CHARACTERISTICS

S YM80L

PARAMETER
PATH

MODE

tPLH
tpHL

Cn to Cn + 4

tpLH
tpHL

A or Bto Cn + 4

tPLH
tpHL

A orB to Cn + 4

54174F
TA = +25°C
VCC=+5.0V
CL = 50 pF
MIN
TYP
MAX

54F
74F
TA = -55 to +125°C TA = 0 to +70 oC
VCC = 5.0 V ±10% VCC = 5.0V ± 10% UNITS
CL = 50 pF
CL = 50 pF
MIN
MAX
MIN
MAX

3.0
3.0

6.4
6.1

8.5
8.0

3.0
3.0

12
11.5

3.0
3.0

9.5
9.0

ns

Sum

5.0
5.0

10
9.4

13
12

5.0
5.0

18
17

5.0
5.0

14
13

ns

Dif

5.0
5.0

10.8
10

14
13

5.0
5.0

19.5
18

5.0
5.0

15
14

ns

Any

3.0
3.0

6.7
6.5

8.5
8.5

3.0
3.0

12
12

3.0
3.0

9.5
9.5

ns

tpLH
tpHL

Cn to F

tPLH
tpHL

A or B to

G

Sum

3.0
3.0

5.7
5.8

7.5
7.5

3.0
3.0

10.5
10.5

3.0
3.0

8.5
8.5

ns

tpLH
tpHL

AorBtoG

Dif

3.0
3.0

6.5
7.3

8.5
9.5

3.0
3.0

12
13.5

3.0
3.0

9.5
10.5

ns

tpLH
tpHL

AorBtoP

Sum

3.0
3.0

5.0
5.5

7.0
7.5

3.0
3.0

10
10.5

3.0
3.0

8.0
8.5

ns

Dif

4.0
4.0

5.8
6.5

7.5
8.5

4.0
4.0

10.5
12

4.0
4.0

8.5
9.5

ns

7.0
7.2

9.0
10

3.0
3.0

12.5
14

3.0
3.0

10
10

ns

tpLH
tPHL

AorBtoP

tPLH
tpHL

Ai or Bi to Fi

Sum

3.0
3.0

tpLH
tpHL

Ai or Eli to Fi

Dif

3.0
3.0

8.2
5.0

11
11

3.0
3.0

15.5
15.5

3.0
3.0

12
12

ns

Sum

4.0
4.0

8.0
7.8

10.5
10

4.0
4.0

15.5
14

4.0
4.0

11.5
11

ns

Dif

4.5
4.5

9.4
9.4

12
12

4.5
4.5

17
17

4.5
4.5

13
13

ns

Logic

4.0
4.0

6.0
6.0

9.0
10

4.0
4.0

12.5
14

4.0
4.0

10
11

ns

Dif

11
7.0

18.5
9.8

27
12.5

11
7.0

35
17.5

11
7.0

29
13.5

ns

tpLH
tpHL

AnyAor 8
to AnyF

tPLH
tpHL

Any Ii: or 8
to AnyF

tpLH
tpHL

A or B to F

tpLH
tpHL

Aor BtoA= 8

FAST AND LS TTL DATA

4-72

MC54F/74F181

FUNCTION TABLE
ACTIVE-LOW OPERANDS
& Fn OUTPUTS

MODE SELECT
INPUTS

S:J

52

5,

So 1M =HI 1M = LI ICn = LI

LOGIC ARITHMETIC"
IM=HI 1M = LllCn = HI

L
L
L
L

L
L
L
L

L
L
H
H

L
H
L
H

Ii
A
A+B
A+B
AB
A+8
Logic a minus 1

L
L
L
L

H
H

L
L

H
H

H

L
H
L
H

H
H
H
H

L
L
L
L

L
L
H

H
H
H

H
H
H
H

L
L

LOGIC

H

H

H

H
H

ARITHMETIC""

ACTIVE-HIGH OPERANDS
& Fn OUTPUTS

A

A minus 1

liB

AB minus 1
AS minus 1

Ii+B
Logic 1

minus 1

A plus IA +81
AB plus IA + 81

A+B

B

liB

A plus AS
IA + BI plus AS

A@ B
A+S

A minus B minus 1

A+B

S
A(j)B
A8

L
H
L
H

AB
A(j)B
B
A+B

A plus IA + BI
A plus B
A8 plus IA + BI
A+B

A+B
A(j)B
B
AB

A plus AB
A plus B
IA + 81 plus AB
AB minus 1

L
H
L
H

Logic
AS
AB
A

A plus A"
AB plus A
AS minus A
A

Logic 1
A+B
A+B
A

A plus A"
IA + BI plus A
IA + 81 plus A

a

A minus B minus 1
AS minus 1

A minus 1

*Each bit is shifted to the next more significant position.
H;;; HIGH Voltage Level
**Arithmetic operations expressed in 2s complement notation. L = LOW Voltage Level

II
I

FAST AND LS TTL DATA

4-73

®

MOTOROLA

MCS4F182
MC74F182

CARRY LOOKAHEAD GENERATOR
DESCRIPTION - The MC54F174F182 is a high-speed carry lookahead generator. It is generally used with the F181. F381 or 29FOl
4-bit arithmetic logic unit to provide high-speed lookahead over word
lengths of more than fou,\bits .

CARRY LOOKAHEAD
GENERATOR
FASTTM SCHOTTKY TTL

• PROVIDES LOOKAHEAD CARRIES ACROSS A GROUP OF
FOUR ALUs
• MULTI-LEVEL LOOKAHEAD HIGH-SPEED ARITHMETIC
OPERATION OVER LONG WORD LENGTHS
LOGIC SYMBOL
13
Cn
TRUTH TABLE
INPUTS

II

Cn

~o

150

X
L
X

H
H

H

H

X
X
L
X
X
H

X
X
X
L
X
X
X
H

L
X

]5,

~2 '152

G:3 '153

X

X
H

X
L
X

X
X
X
L

X
X

X
X

H
H

H

X
X
X
X
L

X
X
X

Cn+x

Cn+y

C n+z

G fi

L
L

X
X
L

H
H

X
X
L
X

~,

OUTPUTS

1,1

L
X
X

X

X

H
H
H

H

X
L
X
X

X
X
X
X
L
L

X
X

X
X

H

H
H

X
X
X
L

X
X
L
X

H

X
X
X
X
L

9

L
L
L

H

X
X
X
L
L

X
X

X
X
X
X
L
L
L

X

X

H
H
H

H

L
)I

X
L
X
X

X
X
X
X
L
L

H

X

X
X
X
L

H

X
X

X
X
L

X
L

H

H
H
H
H
H
H
H
H

L
X
X
X

H

X
X
X
X
L
L
L

2

Cn +y
en + z

G2
P3
G3
G

15
14
6
5

7
10
VCC = Pin 16
GND=Pin8

L
L
L
L

H

3

P1
G1

P

H
H
H
H
H
H
H

en + x

4

P2

H
H
H
H
H

12

Po
Go

CONNECTION DIAGRAM
H
H
H
H

L
L
L
L

X
X
X
H

H
H
H
H

L

L

en + x

Cn + y

G

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

J Suffix - Case 620-08
(Ceramic)
N Suffix - Case 648-05
(Plastic)

FAST AND LS TTL DATA

4-74

MC54F174F182

LOGIC DIAGRAM

G2 P2

en +y
GUARANTEED OPERATING RANGES

SYMBOL

p

G

PARAMETER

MIN

TYP

MAX

UNIT

54,74

4.50

5.0

·5.50

V

54
74

-55
0

25
25

125
70

°c

VCC

Supply Voltage

TA

Operating Ambient Temperature Range

IOH

Output Current -

High

54,74

-1.0

mA

IOL

Output Current - Low

54, 74

20

mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL
VIH

PARAMETER

MIN

Input HIGH Voltage

LIMITS
TYP

MAX

UNITS
V

2.0

TEST CONDITIONS
Guaranteed Input HIGH Voltage

VIL

Input LOW Voltage

0.8

V

Guaranteed Input LOW Voltage

VIK

Input Clamp Diode Voltage

-1.2

V

liN = -18 mA

VCC= MIN

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

154,74

2.5

3.4

V

IOH = -1.0 mA

,VCC=4.50V

74

2.7

3.4

V

10H = -1.0 mA

VCC=4.75V

0.5

V

10L= 20 mA

VCC= MIN

20

!LA

VIN=2.7V

VCC= MAX

L

0.35

Input HIGH Current
Cn Input
P3 Input
P2 Input
G3, PO, P1 Inputs
GO, G2 Inputs
G1 Input

100

!LA

VIN=7.0V

VCC= MAX

-1.2
2.4
-3.6
-4.8
-8.4
-9.6

mA

VIN= 0.5 V

VCC= MAX

-150

mA

VOUT= OV

VCC= MAX

IlL

Input LOW
Current

lOS

Output Short Circuit
Current (Note 2)

ICCH

Power Supply Current
(All Outputs HIGH)

18.4

28

mA

P3, G3 = 4.5 V
All Other Inputs
= GND

VCC= MAX

ICCL

Power Supply Current
(All Outputs LOW)

23.5

36

mA

GO, G1, G2
= 4.5 V
All Other Inputs
=GND

VCC= MAX

-60

NOTES:
1. For conditions such as MIN or MAX, use the appropriate value specified under guaranteed operating ranges.
2. Not more than one output should be shorted at a time. nor for more than 1 second.

FAST AND LS TTL DATA

4-75

II

MC54F174F182

AC CHARACTERISTICS

S YMBOL

PARAMETER

54174F
TA - +25°C
VCC = +5.0 V
CL = 50 pF
MIN
TYP
MAX

54F
74F
TA - -55 to +125°C TA - 0 to +70 oC
VCC = 5.0 V ±10% VCC=5.0V±10% UNITS
CL = 50 pF
CL= 50 pF
MIN
MAX
MIN
MAX

tpLH
tpHL

Propagation Delay
Cn to Cn + x' Cn + y, Cn + z

3.0
3.0

6.6
6.8

8.5
9.0

3.0
3.0

10.5
11

3.0
3.0

9.5
10

ns

tpLH
tpHL

Po, P1

Propagation Delay
orP2 to Cn + x'
Cn + y, Cn + z

2.5
1.5

6.2
3.7

8.0
5.0

2.5
1.5

10.7
6.5

2.5
1.5

9.0
6.0

ns

tpLH
tpHL

Propagation Delay
GO, G1 or G2 to Cn + x'
Cn + y, Cn + z

2.5
1.5

6.5
3.9

8.5
5.2

2.5
1.5

10.5
6.5

2.5
1.5

9.5
6.0

ns

tPLH
tpHL

Propagation Delay
P1,P2 0rP3 toG

2.0
2.0

7.9
6.0

10
8.0

2.0
2.0

12.5
9.5

2.0
2.0

11
9.0

ns

tPLH
tPHL

Propagation Delay
GntoG

2.0
1.5

8.3
5.7

10.5
7.5

2.0
1.5

12.5
9.5

2.0
1.5

11.5
8.5

ns

tpLH
tpHL

Propagation Delay

Pn to P

2.5
2.5

5.7
4.1

7.5
5.5

2.5
2.5

11
7.5

2.5
2.5

8.5
6.5

ns

FUNCTIONAL DESCRIPTION - The F182 carry lookahead generator accepts up to four pairs of
active-LOW Carry Propagate (PO-P3) and Carry Generate (130-G3) signals and an active-HIGH Carry
input (C n ) and provides anticipated active-HIGH carries (C n + x' ~n + y, Cn + z) across fou,:..9'0ups of
binary adders. The F182 also has active-LOW Carry Propagate (P) and Carry Generate (G) outputs
which may be used for further levels of lookahead. The logic equations provided at the output are:

II

G - G3 + P3G2 + P3P2Gl + P3P2P1 GO
P - P3P2Pl Po

Cn + x = GO + POC n
Cn + y = Gl + P1 GO + PI POC n
Cn + z = G2 + P2 Gl + P2 Pl GO + P2Pl POCn

Also, the F182 can be used with binary ALUs in an active-LOW or active-HIGH input operand mode.
The connections (Figure A) to and from the ALU to the carry lookahead generator are identical in
both cases. Carries are rippled between lookahead blocks. The critical speed path follows the circled
numbers. There are several possible arrangements for the carry interconnects, but all achieve about
the same speed. A 28-bit ALU is formed by dropping the last F181 or F381.
FIGURE A - 32-Bit ALU with Ripple Carry between 16-Bit Lookehead ALU.

--------t

CIN .....

'*ALUs may be either F181, F381 or 2901A.

FAST AND LS TTL DATA

4-76

®

MOTOROLA

MCS4F190
MC74F190
Advance Information
UP/DOWN DECADE COUNTER
(With Preset and Ripple Clock)

DESCRIPTION - The MC54F/74F190 is a reversible BCD (8421)
decade counter featuring synchronous counting and asynchronous
presetting, The presetfeature allows the F190 to be used in programmable'dividers, The Count Enable input, the Terminal Count output
and the Ripple Clock output make possible a variety of methods of
implementing multistage counters, In the counting modes, state
changes are initiated bV the rising edge of the clock,

UP/DOWN DECADE COUNTER
(With Preset and Ripple Clock)
FAST"M SCHOTTKY TTL

LOGIC SYMBOL

• HIGH-SPEED - 110 MHz TYPICAL COUNT FREQUENCY
• SYNCHRONOUS COUNTING
• ASYNCHRONOUS PARALLEL LOAD
• CASCADABLE

11 15 1 10 9
RC TRUTH TABLE
INPUTS
CE
L
H
X

TC"

CP

I I
H
X
L

VX
X

MODE SELECT TABLE
INPUTS

OUTPUT
RC

PL

CE

-UH
H

H
H
L
H

L
L
X
H

MODE

UfO CP
L
H
X
X

J'
J'
X
X

Count Up
Count Down
Preset IAsVn.l
No Change IHoldl

"TC is generated Internally
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

5
4
14

13
CE
TC

3

2

6

7

VCC; Pin 16
GND;Pin8

STATE DIAGRAM

CONNECTION DIAGRAM

I

COUNT U P _
COUNT DOWN

---+

J Suffix - Case 620-08
(Ceramic)
N Suffix - Case 648-05
(plastic)

FAST AND LS TTL DATA

4-77

12

II

I

MC54F174F190

LOGIC DIAGRAM
CP

UfO

Po

~~
f----<

,,7

V

tf ~
I

f-

1

~

.....

~7

'" J

t
I

II crRC

TC

I

I

I 1 I

Y

JCLOCKKI~
PRESET
CLEAR
Q
Q

1

....

I )

':

l'

r-h c:
1 I

yl

~ PRESET
JCLOCKK I~
Q

rh

t

~t

JCLOCKK
PRESET

L-

I

~

LII

I 1

JCLOCKK I~
PRESET
Q
CLE~r

CLEi',R
Q

L-

L-

t

....

I~

CLE~R

Q

Q

j

L-

t

t

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

GUARANTEED OPERATING RANGES
SYMBOL

PARAMETER

VCC

Supply Voltage

TA

Operating Ambient Temperature Range

IOH

Output Current -

High

IOL

Output Current -

Low

MIN

TYP

MAX

UNIT

54, 74

4.50

5.0

5.50

V

54
74
54, 74
54,74

-55

25
25

125
'70
-1.0
20

FAST AND LS TTL DATA

4-78

0

°C
mA
mA

MC54F174F190

FUNCTIONAL DESCRIPTION - The F190 is a synchronous up/down BCD decade counter
containing four edge-triggered flip-flops, with internal gating and steering logic to provide individual
preset, count-up and count-down operations. It has an asynchronous parallel load capability permitting the counter to be preset to any desired number. When the Parallel Load (PL) input is LOW,
information present on the Parallel Data inputs (P0-P3) is loaded into the counter and appears on
the Q outputs. This operation overrides the counting functions, as indicated in the Mode Select
Table. A HIGH signal on the CE input inhibits counting. When CE is LOW, internal state changes are
initiated synchronously by the LOW-to-HIGH transition of the clock input. The direction of counting
is determined by the U/D input signal, as indicated in the Mode Select Table. CE andU/D can be
changed with the clock in either state, provided only that the recommended setup and hold times
are observed.
Two types of outputs are provided as overflow/underflow indicators. The Terminal Count (TC)
output is normally LOW and goes HIGH when a circuit reaches zero in the count-down mode or
reaches 9 in the count-up mode. The TC output will then remain HIGH until a state change occurs,
whether by counting or presetting or until UfO is changed. The TC output should not be used as a
clock signal because it is subject to decoding spikes. The TC signal is also used internally to enable
the Ripple Clock (RC) output. The RC output is normally HIGH. When CEis LOWand TC is HIGH, the
RC output will go LOWwhen the clock next goes LOW and will stay LOW until the clock goes HIGH
again. This feature simplifies the design of multistage counters. For a discussion and illustrations
of the various methods of implementing multistage counters, please see the F191 data sheet.

II
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

MIN

LIMITS
TYP

MAX

UNITS

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

O.B

V

Guaranteed Input LOW Voltage

VIK

Input Clamp Diode Voltage

-1.2

V

liN = -1B rnA

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

Input HIGH Current

IlL

Input LOW Current
Other Inputs
CE Input

lOS

Output Short Circuit
Current (Note 2)

ICC

Power Supply Current

2.0

V

TEST CONDITIONS
Guaranteed Input HIGH Voltage

VCC= MIN

154,74

2.5

3.4

V

IOH=-1.0mA

VCC =4.50V

174

2.7

3.4

V

10H = -1.0 rnA

VCC =4.75 V

0.35

-60
38

0.5

V

10L= 20 rnA

VCC= MIN

20

p.A

VIN=2.7V

VCC= MAX

100

p.A

VIN=7.0V

VCC= MAX

-0.6
-1.8

rnA

VIN=0.5 V

VCC= MAX

-150

rnA

VOUT= OV

VCC= MAX

55

rnA

VCC= MAX

NOTES:
1. For conditions such as MIN or MAX, USB the appropriate value specified under guaranteed operating ranges.
2. Not more than one output should be shorted at a time, nor for more than 1 second.

FAST AND LS TTL DATA

4-79

MC54F174F190

AC CHARACTERISTICS

S YMBOL

II

PARAMETER

54174F
TA = +25°C
VCC=+5.0V
CL = 50 pF
MIN
TYP
MAX

54F
74F
TA = -55 to +125°C TA = 0 to +70 oC
VCC = 5.0V ±10% VCC =5.0V ± 10% UNITS
CL = 50 pF
CL = 50 pF
MIN
MAX
MIN
MAX

f max

Maximum Count Frequency

80

110

tpLH
tpHL

Propagation Delay
CPto On

3.0
3.0

5.5
6.5

9.0
10

3.0
3.0

80
12.5
14

3.0
3.0

80
10
11

MHz
ns

tpLH
tpHL

Propagation Delay
CPtoTC

8.0
5.0

12.5
9.5

16
13

8.0
5.0

22.5
18

8.0
5.0

17
14

ns

tpLH
tpHL

Propagation Delay
CP to RC

4.0
3.0

7.0
5.0

9.5
8.0

4.0
3.0

13.5
11

4.0
3.0

10.5
9.0

ns

tPLH
tpHL

Propagation Delay
CE to RC

3.0
3.0

4.6
4.5

7.0
7.0

3.0
3.0

10
10

3.0
3.0

8.0
8.0

ns

tPLH
tPHL

Propagation Delay
U/D to RC

7.0
5.0

11
9.0

18
12

7.0
5.0

25.5
17

7.0
5.0

19
13

ns

tPLH
tpHL

Propagation Delay
U/D to TC

3.0
3.0

6.0
6.5

11
11

3.0
3.0

15.5
15.5

3.0
3.0

12
12

ns

tPLH
tPHL

Propagation Delay
Pn to On

3.0
8.0

4.6
13.4

7.0
17

3.0
8.0

10
24

3.0
8.0

8.0
18

ns

tpLH
tpHL

Propagation Delay
PL to On

3.0
4.0

6.7
7.2

11
15

3.0
4.0

15.5
21

3.0
4.0

12
16

ns

AC OPERATING REQUIREMENTS

SYMBOL

PARAMETER

54174F
TA =+25°C
VCC= +5.0 V
MIN
TYP
MAX

54F
74F
TA = -55 to +125°C TA =0 to +70°C
UNITS
VCC = 5.0 V ±10% VCC = 5.0V ± 10%
MIN
MAX
MIN
MAX

ts(H)
ts (L)

Set up Time, HIGH or LOW
Pn to Pi:

5.0
8.0

5.0
8.0

5.0
8.0

th (H)
th (L)

Hold Time, HIGH or LOW
Pn to Pi:

3.0
3.0

3.0
3.0

3.0
3.0

ts (L)

Set up Time LOW
CE to CP

10

10

10

th (L)

Hold Time LOW
CE to CP

0

0

0

tw(L)

PL Pulse Width, LOW

6.0

6.0

6.0

ns

tw(L)

CP Pulse Width LOW

6.0

6.0

6.0

ns

tree

Recovery Time
PL to CP

7.0

7.0

7.0

ns

ns

ns

FAST AND LS TTL DATA

4-80

®

MOTOROLA

MC54F191
MC74F191

Advance Information
UP/DOWN BINARY COUNTER
(With Preset and Ripple Clock)

UP/DOWN BINARY COUNTER
(With Preset and Ripple Clock)

FAS'fTM SCHOTTKY TTL

DESCRIPTION - The MC54F/74F191 is a reversible modul0-16
binary counter featuring synchronous counting and asynchronous
presetting. The preset feature allows the F191 to be used in
programmable dividers. The Count Enable input, the Terminal Count
output and the Ripple Clock output make possible a varietyof methods
of implementing multistage counters. In the counting modes, state
changes are initiated by the rising edge of the clock.

o

HIGH-SPEED -

LOGtC SYMBOL

14 4 5

110 MHz TYPICAL COUNT FREQUENCY

CD SYNCHRONOUS COUNTING

" ASYNCHRONOUS PARALLEL LOAD
• CASCADABLE

CP CE
3

2
FUNCTIONAL DESCRIPTION - The F191 is a synchronous upl
down 4-bit binary counter. It contains four edge-triggered flip-flops,
with internal gating and steering logic to provide individual preset,
count-up and count-down operations.
Each circuit has an asynchronous parallel load capability permitting
the counter to be preset to any desired number. When the Parallel
Load (jiLl input is LOW, information present on the Parallel Data
inputs (PO-P31 is loaded into the counter and appears on the Q outputs. This operation overrides the counting functions, as indicated
in the Mode Select Table.
A HIGH signal on the CE input inhibits counting. When CE is LOW,
internal state changes are initiated synchronously by the LOW-toHIGH transition of the clock input. The direction of counting is determined by the ITlo input signal, as indicated in the Mode Select Table.
CE and 'OlD can be changed with the clock in either state, provided
only that the recommended setup and hold times are observed.

INPUTS

H
H
L
H

CE U/D
L
L
X
H

L
H
X
X

.r
.r
X
X

CE
Count Up
Count Down

Preset (Asyn.l
No Change (Holdl

01

Po

15

P1

1

P2

10

P3

9

6

02

7

03
TC

RC

12

13

L
H
X

TC·

CP

I I
H
X
L

VX
X

Vcc=Pin16
GND= Pin B

CONNECTION DIAGRAM

RC
lJ"
H
H

H = HIGH Voltage Level
L = LOW Voltage Level
X::; Immaterial

J Sullix - Case 620-0B
(Ceramic)
N Suffix - Case 64B-05
(Plastic)

FAST AND LS TTL DATA

4-81

II
I

OUTPUT

INPUTS

MODE
CP

11

PL

RC TRUTH TABLE

MODE SELECT TABLE

PL

u'io

00

II

MC54F174F191

FUNCTIONAL DESCRIPTION (continued)
Two types of outputs are provided as overflow/underflow indicators. The Terminal Count (TC) output is normally LOW and goes HIGH when a circuit reaches zero in the count-down mode or reaches
15 in the count-up mode. The TC output will then remain HIGH until a state change occurs, whether
by counting or presetting or untilU/D is changed. The TC output should not be used as a clock signal
because it is subject to decoding spikes.
The TC signal is also used internally to enable the Ripple Clock(RC) output. The RC output is normally
HIGH. When CE is LOW and TC is HIGH, the RC output will go LOW when the clock next goes LOW
and will stay LOW until the clock goes HIGH again. This feature simplifies the design of multistage
counters, as indicated in Figures A and B. In Figure A, each Rc output is used as the clock input for
the next higher stage. This configuration is particularly advantageous when the clock source has a
limited drive capability, since it drives only the first stage. To prevent counting in all stages it is only
necessary to inhibit the first stage, since a HIGH signal on CE inhibits the RC·output pulse, as
indicated in the RC Truth Table. A disadvantage of this configuration, in some applications, is the
timing skew between state changes in the first and last stages. This represents the cumulative delay
of the clock as it ripples through the preceding stages.
A method of causing state changes to occur simultaneously in all stages is shown in Figure B. All
clock inputs are driven in parallel and the RC outputs propagate the carry/borrow signals in ripple
fashion. In this configuration the LOW state duration of the clock must be long enough to allowthe
negative-going edge of the carry/borrow signal to ripple through to the last stage before the clock
goes HIGH. There is no such restriction on the HIGH state duration of the clock, since the RC output
of any device goes HIGH shortly after its CP input goes HIGH.
The configuration shown in Figure C avoids ripple delays and their associated restrictions. The CE
input for a given stage is formed by combining the TC signals from all the preceding stages. Note
that in order to inhibit counting an enable signal must be included in each carry gate. The simple
inhibit scheme of Figures A and B doesn't apply, because the TC output of a given stage is not
affected by its own CEo

FAST AND LS TTL DATA

4-82

MC54F174F191

LOGIC DIAGRAM

Po

CP UIO

~
t-~7

-

~7

~~

~7

)

c
.1

c:r

1

1

-<>IIJ
PRESET
CLOCK K1IoCLE8R
Q

~C

I I
Q

RC

TC

U

~C

I
Q

~C
,,,J~,

A

-011PRESET
J CLOCK K

L--

Y

- U

......

LIIJCLOCKK
PRESET
CLEAR
Q
Q

CLE!\.R
Q

L--

PRESET
CLEAR

'11

0:
L--

Q

L--

Y

'7

J

'7

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

GUARANTEED OPERATING RANGES
SYMBOL
VCC

PARAMETER
Supply Voltage

TA

Operating Ambient Temperature Range

IOH

Output Current -

High

IOL

Output Current -

Low

MIN

TYP

MAX

UNIT

54. 74

4.50

5.0

5.50

V

54
74
54. 74
54. 74

-55
0

25
25

125
70

FAST AND LS TTL DATA

4-83

-1.0
20

°c
rnA
rnA

MC54F174F191
FIGURE A - N·Stage Counter Using Ripple Clock
DIRECTION

_~

_ _ _ _ _ _ _....,.._ _ _ _ _ _ _....,.._ _ _ _ __

CONTROL
ENABLE
CLOCK

FIGURE B - Synchronous N·Stage Counter Using Ripple Carry/Borrow
DIRECTION_~

_ _ _ _ _ _ _....,.._ _ _ _ _ _ _....,..-----_

CONTROL

CLOCK--~--------------~-------------+-----------

FIGURE C - Synchronous N·Stage Counter with Parallel Gated Carry/Borrow

----------t-----------t------

DIRECTION - - -......
CONTROL

ENABLE~--+_----....,..----1_----~----1_-----

CLOCK-----~-----------------+------------------~---------

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

MIN

LIMITS
TYP

MAX

TEST CONDITIONS

VIH
VIL

Input LOW Voltage

O.B

V

Guaranteed Input LOW Voltage

VIK

Input Clamp Diode Voltage

-1.2

V

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

Input HIGH Current

IlL

Input LOW Current
Other Inputs
CE Input

lOS

Output Short Circuit
Current (Note 2)

ICC

Power Supply Current

2.0

UNITS

Input HIGH Voltage

V

Guaranteed Input HIGH Voltage

IIN=-1B rnA

VCC= MIN

154,74

2.5

3.4

V

10H = -1.0 rnA

VCC=4.50V

174

2.7

3.4

V

IOH=-1.0mA

VCC = 4.75 V

0.5

V

10L= 20 rnA

VCC= MIN

20

p.A

VIN=2.7V

100

p.A

VIN= 7.0V

-0.6
-1.8

rnA

VIN= 0.5V

VCC= MAX

-150

rnA

VOUT= 0 V

VCC= MAX

55

rnA

VCC= MAX

0.35

-60
38

NOTES:
1. For conditions such as MIN or MAX, use the appropriate value specified under guaranteed operating ranges.
2. Not more than one output should be shorted at a time, norfor more than 1 second.

FAST AND LS TTL DATA

4-84

VCC= MAX

MC54F174F191

AC CHARACTERISTICS

SYMBOL

PARAMETER

54174F
TA= +25°C
VCC= +5.0 V
CL = 50 pF
MIN
MAX
TYP

54F
74F
TA - -55 to +125°C TA - 0 to +70 oC
VCC = 5.0 V ±10% VCC = 5.0V ± 10%
CL = 50 pF
CL = 50 pF
MIN

MAX

80

MIN

UNITS

MAX

f max

Maximum Count Frequency

80

110

80

tpLH
tPHL

Propagation Delay
CP to On

3.0
3.0

5.5
6.5

9.0
10

3.0
3.0

12.5
14

3.0
3.0

10
11

MHz
ns

tPLH
tpHL

Propagation Delay
CP to TC

8.0
5.0

12.5
9.5

16
13

8.0
5.0

22.5
18

8.0
5.0

17
14

ns

13.5
11

4.0
3.0

10.5
9.0

ns

tPLH
tpHL

Propagation Delay
CPto RC

4.0
3.0

7.0
5.0

9.5
8.0

4.0
3.0

tpLH
tpHL

Propagation Delay
GEto RC

3.0
3.0

4.6
4.5

7.0
7.0

3.0
3.0

10
10

3.0
3.0

8.0
8.0

ns

tpLH
tpHL

Propagation Delay
DID to RC

7.0
5.0

11
9.0

18
12

7.0
5.0

25.5
17

7.0
5.0

19
13

ns

tPLH
tPHL

Propagation Delay
U/DtoTC

3.0
3.0

6.0
6.5

11
11

3.0
3.0

15.5
15.5

3.0
3.0

12
12

ns

tPLH
tpHL

Propagation Delay
Pn to On

3.0
8.0

4.6
13.4

7.0
17

3.0
8.0

10
24

3.0
8.0

8.0
18

ns

tpLH
tpHL

Propagation Delay
pLto On

3.0
4.0

6.7
7.2

11
15

3.0
4.0

15.5
21

3.0
4.0

12
16

ns

II

AC OPERATING REQUIREMENTS

SYMBOL

PARAMETER

54/74F
TA = +25°C
VCC=+5.0V
MIN
TYP
MAX

54F
74F
TA - -55 to +125°C TA = 0 to +70°C
VCC = 5.0 V +10% VCC = 5.0 V + 10%
MIN

MAX

MIN

UNITS

MAX

ts (H)
ts (L)

Set up Time, HIGH or LOW
Pn to"PL

5.0
8.0

5.0
8.0

5.0
8.0

th (H)
th (L)

Hold Time, HIGH or LOW
Pn to pL

3.0
3.0

3.0
3.0

3.0
3.0

ts (L)

Set up Time LOW
CE to CP

10

10

10

th (L)

Hold Time LOW
CE to CP

0

0

0

tw(L)

PL Pulse Width, LOW

6.0

6.0

6.0

ns

tw(L)

CP Pulse Width LOW

6.0

6.0

6.0

ns

tree

Recovery Time
PI to CP

7.0

7.0

7.0

ns

ns

ns

FAST AND LS TTL DATA

4-85

®

MOTOROLA

MC54F1921193
MC74F1921193

Advance Information

UP/DOWN COUNTERS WITH SEPARATE
UP/DOWN CLOCKS

UP/DOWN COUNTERS
WITH SEPARATE
UP/DOWN CLOCKS
FAST'M

DESCRIPTION - The MC54Fn4F192 is an up/down BCD decade
(8241) counter. The MC54Fn4193 is an up/down modul0-16 binary
counter. Separate Count Up and Count Down Clocks are used,
and in either counting mode the circuits operate synchronously.
The outputs change state synchronously with the LOW-to-HIGH
transitions on the clock inputs.

LOGIC SYMBOL

Separate Terminal Count Up and Terminal Count Down outputs
are provided that are used as the clocks for a subsequent stage
without extra logic, thus simplifying multistage counter designs.
Individual preset inputs allow the circuit to be used as a programmable counter. Both the Parallel Load (PL) and the Master
Reset (MR) inputs asynchronously override the clocks.

II

12

9

PL

CPu

CPo

MODE

X

X
X

X
X

H

I

H
H

H

I

Reset (Asyn.)
Preset (Asyn.)
No Change
Count Up
Count Down

L
H
H
H

6

1

P,

0,

2

15

Po

00

3

11

MR
PL
CPU CPO

14

5

4

VCC = Pin 16
GNO = Pin 8

H = HIGH Voltage Level
L ,,; LOW-Voltage Level
X = Immaterial

CONNECTION DIAGRAM

STATE DIAGRAMS

CPO
CPU

F192

7

02

P2

MR

13

TCU TCO
P3
Q3

10

FUNCTION TABLE

H
L
L
L
L

SCHOTTKY TTL

F193

FAST AND LS TIL DATA

4-86

MC54F/74F192 • MC54F/74F193

FUNCTIONAL DESCRIPTION

cuit has reached the maximum count state; 9 ('F192) or
16 ('F193), the reset HIGH-to-LOW transition of the
Count Up Clock will cause TCU to go LOW. TCU will
stay LOW until CPU goes HIGH again, thus effectively
repeating the Count Up Clock, but delayed by two gate
delays. Similarly, the TCD output will go LOW when the
circuit is in the zero state and the Count Down Clock
goes LOW. Since the TC outputs repeat the clock waveforms, they can be used as the clock input signals to
the next higher order circuit in a multistage counter.

The 'F192, 193 are asynchronously presettable counters.
The 'F192 is a decade counter while the 'F193 is organized for 4-bit binary operation. They both contain four
edge triggered flip-flops, with internal gating and steering logic to provide master reset, individual preset,
count up and count down operations.
A LOW-to-HIGH transition on the CP input to each flipflop causes the output to change state. Synchronous
switching, as opposed to ripple counting, is achieved
by driving the steering gates of all stages from a common Count Up line and a common Count Down line,
thereby causing all state changes to be initiated simultaneously. A LOW-to-HIGH transition on the Count Up
input will advance the count by one; a similar transition
on the Count Down input will decrease the count by
one. While counting with one clock input, the other
should be held HIGH, as indicated in the Function Table.
Otherwise, the circuit will either count by twos or not
at all, depending on the state of the first flip-flop, which
cannot toggle as long as either clock input is LOW.

Both the 'F192 and the 'F193 have an asynchronous
parallel load capability permitting the counter to be preset. When the Parallel Load (PL) and the Master Reset
(MR) inputs are LOW, information present on the Parallel Data input (PO-P3) is loaded into the counter and
appears on the outputs regardless of the conditions of
the clock inputs. A HIGH signal on the Master Reset
input will disable the preset gates, override both clock
inputs, and latch each Q output in the LOW state. If one
of the clock inputs is LOW during and after a reset or
load operation, the next LOW-to-HIGH transition of that
clock will be interpreted as a legitimate signal and will
be counted.

The Terminal Count Up (TCU) and Terminal Count
Down (TCD) outputs are normally HIGH. When the cirGUARANTEED OPERATING RANGES

MIN

TYP

MAX

UNIT

VCC

Supply Voltage'

PARAMETER

54
74

4.5
4.75

5.0
5.0

5.5
5.25

V

TA

Operating Ambient Temperature Range

54
74

-55
0

25
25

125
70

·C

10H

Output Current -

-1.0

mA

SYMBOL

54,74

High

Output Cu rrent - Low
54,74
20
mA
10L
..
*74F deVices may be operated over the 4.5 to 5.5 V supply range where they Will meet the speCifications of 54F deVices over the 0 to 70 C
temperature range.

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

LIMITS

PARAMETER

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

VIK

Input Clamp Diode Voltage

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

Input HIGH Current

IlL

Input LOW Current
(MR, j5[ and Pn inputs)
(CP inputs)

lOS

Output Short Circuit
Current (Note 2)

ICC

Power Supply Current

MIN

TYP

MAX

V

2.0

I
I

UNITS

TEST CONDITIONS
Guaranteed Input HIGH Voltage

0.8

V

Guaranteed Input LOW Voltage

-1.2

V

VCC

=

MIN, liN -

54

2.5

V

10L - -1.0 mA

74

2.7

V

10L

-18 mA
VCC

= -1.0 mA
= 20 mA

=

0.5

V

20

~

VCC - MAX, VIN - 2.7 V

0.1

mA

VCC

=

MAX, VIN

= 7.0 V

-0.6

mA

VCC

=

MAX, VIN

= 0.5 V

-150

mA

VCC

=

MAX, VOUT

55

mA

VCC

= MAX

10L

MIN

VCC - MIN

-1.2
-60
38

=0V

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device

type.
2. Not more than one output should be shorted at a time. nor for more than 1 second.

FAST AND LS TTL DATA

4-87

II

II

MC54F/74F192 • MC54F/74F193

AC CHARACTERISTICS
54f74F
SYMBOL

54F

PARAMETER

74F

TA = -55 to. + 125°C TA = Oto +70°C
VCC = 5.0V ±10% VCC = 5.0V ±10% UNITS
CL = 50 pF
CL = 50 pF

TA = +25°C
VCC = +5.0 V
CL = 50 pF
MIN

TYP

f max

Maximum Count Frequency

100

125

MAX

MIN

MAX

MIN

MAX

tpLH
tpHL

Propagation Delay
CPU or CPO to TeU

4.0
3.5

7.0
6.0

9.0
8.0

4.0
3.5

10
9.0

ns

tpLH
tpHL

Propagation Delay
CPU or CPO to an

4.0
5.5

6.5
9.5

8.5
12.5

4.0
5.5

9.5
13.5

ns

tpLH
tpHL

Propagation Delay
Pn to an

3.0
6.0

4.5
11

7.0
14.5

3.0
6.0

8.0
15.5

ns

tpLH
tpHL

Propagation Delay
j5[ to an

5.0
5.5

8.5
10

11
13

5.0
5.5

12
14

ns

tpHL

Propagation Delay
MR to an

6.5

11

14.5

6.5

15.5

tpLH

Propagation Delay
MR to TeU

6.0

10.5

13.5

6.0

14.5

'tPHL

Propagation Delay
MR to Teo

7.0

11.5

14.5

7.0

15.5

tpLH
tpHL

Propagation Delay
j5[ to TCU or Teo

7.0
7.0

12
11.5

15.5
14.5

7.0
7.0

16.5
15.5

ns

tpLH
tpHL

Propagation Delay
Pn to TeU or Teo

7.0
6.5

11.5
11

14.5
14

7.0
6.5

15.5
15

ns

90

MHz

ns

AC OPERATING REQUIREMENTS
54/74F
SYMBOL

54F

MIN

TYP

74F

TA = -55 to + 125°C TA=Oto+70°C
UNITS
VCC = 5.0 V ±10% VCC = 5.0 V ±10%

TA = +25°C
VCC = +5.0V

PARAMETER

MAX

MIN

MAX

MIN

ts (H)
ts (L)

Set up Time, HIGH or LOW
Pn to j5[

6.0
6.0

6.0
6.0

th (H)
th (L)

Hold Time, HIGH or LOW
Pn to j5[

4.0
4.0

4.0
4.0

MAX

ns

twill

PL Pulse Width LOW

6.0

6.0

ns

twill

CPU or CPO Pulse Width LOW

5.0

5.0

ns

twill

CPU or CPO Pulse Width LOW
(Change of Direction)

10

10

ns

tw(H)

MR Pulse Width HIGH

6.0

6.0

ns

trec

Recovery Time
j5[ to CPU or CPO

6.0

6.0

ns

trec

Recovery Time
MR to CPU or CPO

4.0

4.0

ns

AC TEST CIRCUIT

Test Point for High Impedance Scopes
R2=500n

±10%

Fig. 1

For 50 n scopes, add a
450 n resistor in series
with the scope and delete
R2.

FAST AND LS TTL DATA

4-88

@ MOTOROLA
MC54F194
MC74F194
Advance Information
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
DES-CRIPTION - The MC54F174F194 is a high-speed 4-bit
bidirectional universal shiftregister. As a high-speed multifunctional,
sequential building block, it is useful in a wide variety of applications.
It may be used in serial-serial, shift left, shift right, serial-parallel,
parallel-serial, and parallel-parallel data register transfers. The F194
is similar in operation to the 5195 universal shift register, with added
features of shift left without external connections and hold (do
nothing) modes of operation.

4-BIT BIDIRECTIONAL
UNIVERSAL SHIFT REGISTER
FASTTM

LOGIC SYMBOL

o TYPICAL SHIFT FREQUENCY OF 150 MHz
o ASYNCHRONOUS MASTER RESET
e HOLD (DO NOTHING) MODE
o FULLY SYNCHRONOUS SERIAL OR PARALLEL DATA
TRANSFERS

FUNCTIONAL DESCRIPTION - The F194 contains four edgetriggered D flip-flops and the necessary interstage logic to synchronously perform shift right. shift left. parallel load and hold operations. Signals applied to the Select (SO, 51) inputs determine the
type of operation, as shown in the Mode Select Table. Signals on the
Select, Parallel data (PO-P3) and Serial data (DSR, DSL) inputs can
change when the clock is in either state, provided only that the
recommended setup and hold times, with respecttothe clock rising
edge, are observed. A LOW signal on Master Reset (MR) overrides
all other inputs and forces the outputs LOW.

11 10 9

15
14
13
12

CP 51 So
MR
DSR
Po
00
PI
Ql
P2
Q2
P3
Q3
DSL

2
3
4
5
6
7

INPUTS

OUTPUTS

MR

S,

So

DSR

DSL

Reset

L

X

X

X

X

Hold

H

I

I

X

Shift Left

H
H

h
h

I
I

X
X

Shift Right

H
H

I
I

h
h

I
h

Parallel Load

H

h

h

X

Pn 00 A'

02

03

X

L

L

L

L

X

X

qo

q,

q2

q3

I
h

X
X

q,
q,

q2
q2

q3
q3

L
H

X
X

X
X

L
H

qo
qo

q,
q,

q2
q2

X

pn

po

p,

P2

P3

CONNECTION DIAGRAM

I = LOW voltage level one setup time prior to the LOW-la-HIGH clock transition.
h = HIGH voltage level one setup time prior to the LOW-la-HIGH clock transition.
pn Iqn) = Lower case letters indicate the stale of the referenced input (or output)
one setup timelprior to the LOW-la-HIGH clock transition,
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

J Suffix - Case 620-08
(Ceramic)
N Suffix - Case 648-05
(Plasticl

FAST AND LS TTL DATA

4-89

II

I

VCC= Pin 16
GND = Pin 8

MODE SELECT TABLE
OPERATING
MODE

SCHOTTKY TTL

II

MC54F/74F194

LOGIC OIAGRAM

Po
Sl~DH~----4r---r----4r------4r---r----~------~--;-----~------~--+-----'

ri#----+- DSR

DSR ----------,

CP~~------------~---r--r-------~---r--r-------~---r--r-------~

MR~~----------------~--r-----------~--r-----------~--r-----------~

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

GUARANTEED OPERATING RANGES
SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

54, 74

4.50

5.0

5.50

V

54
74

-55
0

25
25

125
70

°C

VCC

Supply Voltage

TA

Operating Ambient Temperature Range

IOH

Output Current -

High

54,74

-1.0

IOL

Output Current -

Low

54, 74

20

rnA
rnA

I

AC CHARACTERISTICS

S YMBOL

PARAMETER

54174F
TA - +25°C
VCC=+5.0V
CL = 50 pF
MIN
TYP
MAX

54F
TA= 55 to +125°C
VCC = 5.0 V ±10%
CL = 50 pF
MIN

MAX

74F
TA = 0 to +70 oC
Vec = 5.0 V ± 10% UNITS
CL = 50 pF
MIN
MAX

f max

Maximum Shift Frequency

105

150

tPLH
tpHL

Propagation Delay
CPto Q n

3.5
3.5

5.2
5.5

7.0
7.0

3.0
3.0

8.5
8.5

3.5
3.5

8.0
8.0

ns

tpHL

iiiiR to Q n

4.5

8.6

12

4.5

14.5

4.5

14

ns

Propagation Delay

90

FAST AND LS TTL DATA

4-90

90

MHz

MC54F174F194

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

MIN

LIMITS
TYP

UNITS

MAX

V

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

O.B

V

Guaranteed Input LOW Voltage

VIK

Input Clamp Diode Voltage

-1.2

V

liN = -lB mA

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

2.0

TEST CONDITIONS
Guaranteed Input HIGH Voltage

2.5

3.4

V

10H = -1.0 mA

VCC=4.50V

174

2.7

3.4

V

10H = -1.0 mA

VCC=4.75V

10L= 20 mA

VCC= MIN

0.35

Input HIGH Current

IlL

Input LOW Current

lOS

Output Short Circuit
Current (Note 2)

ICC

Power Supply Current

VCC= MIN

154,74

-60

33

0.5

V

20

p.A

VIN = 2.7 V

VCC= MAX

100

p.A

VIN=7.0V

-0.6

mA

VIN = 0.5 V

VCC= MAX

-150

mA

VOUT= OV

VCC= MAX

46

mA

Sn, MR, DSR,
DSL = 4.5 V
Pn = Gnd,
Cp=...r

VCC= MAX

NOTES:
1. For conditions such as MIN or MAX, use the appropriate value specified under guaranteed operating ranges.
2. Not more than one output should be shorted at a time, nor for more than 1 second.

AC OPERATING REQUIREMENTS

S YMBOL

PARAMETER

ts (H)
ts (L)

Set up Time, HIGH or LOW
Pn or DSR or DSL to CP

th (H)
th (L)

Hold Time, HIGH or LOW
Pn or DSR or DSL to CP

ts (H)
ts (L)

Set up Time, HIGH or LOW
Sn to CP

th (H)
th (L)

Hold Time, HIGH or LOW
Sn to CP

54174F
TA= +25°C
VCC= +5.0 V
MAX
TYP
MIN

54F
74F
TA- 55 to +125°C TA = to +70 oC
VCC = 5.0V ±10% VCC =5.0V± 10% UNITS
MIN
MAX
MIN
MAX

a

4.0
4.0

4.0
4.0

4.0
4.0

a
a

1.0
1.0

1.0
1.0

B.O
B.O

B.O
B.O

B.O
B.O

a
a

a
a

a
a

ns

ns

tw(H)

CP Pulse Width HIGH

5.0

5.5

5.5

ns

twILl

MR Pulse Width LOW

5.0

5.0

5.0

ns

trec

Recovery Time
MR toCP

7.0

9.0

8.0

ns

FAST AND LS TTL DATA

4-91

II

®

MOTOROL.A

MC54/74F240
MC54/74F241
MC54/74F244

OCTAL BUFFER/LINE DRIVER WITH
3-STATE OUTPUTS
DESCRIPTION - The F240, F241 and F244are octal buffers and line
drivers designed to be employed as memory address drivers, clock
drivers and bus oriented transmitters/receivers which provide
improved PC board density.

OCTAL BUFFER/LINE DRIVER
with 3-STATE OUTPUTS
FASTTM SCHOTTKY TTL

• 3-STATE OUTPUTS DRIVE BUS LINES OR BUFFER MEMORY
ADDRESS REGISTERS
• OUTPUTS SINK 64 mA
• 15 mA SOURCE CURRENT
• INPUT CLAMP DIODES LIMIT HIGH-SPEED TERMINATION
EFFECTS

CONNECTION DIAGRAMS

F244

F241

F240

II
J Suffix - Case 732-03 (Ceramic)
N Suffix -

Case 738-02 (Plastic)

TRUTH TABLES
F241

F240

INPUTS
OE,. DE:!
L
L
H

OUTPUT

DE, DE:!

D

I~

INPUTS

H
L
Z

H = HIGH Voltage Level

L
L
H

F244

OUTPUT
D

H
H IL
H
L
X

L =LOW Voltage Level

L
H
Z

x = Immaterial

FAST AND LS TTL DATA

4-92

I-=I=-N...,P=U=-TS_--i OUTPUT
DE" DE:! D

~ 'I~
H

X

L
H
Z

Z = High Impendance

MC54174F240 •

MC54174F241 • MC54/74F244

GUARANTEED OPERATING RANGES
SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

54, 74

4.50

5.0

5.50

V

Operating Ambient Temperature Range

54
74

-55
0

25
25

125
70

°c

10H ..

Output Current -

High

54
74

-12
-15

mA

10L

Output Current -

Low

54
74

48
64

mA

VCC
TA

Supply Voltage

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

MIN

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

VIK

Input Clamp Diode Voltage

vOH

MAX

UNITS

2.0

Output HIGH Voltage

TEST CONDITIONS

V

Guaranteed Input HIGH Voltage

0.8

V

Guaranteed Input LOW Voltage

-1.2

V

liN =-18 mA

VCC= MIN

54, 74

2.4

3.4

V

10H =-3.0 mA

VCC =4.50V

74

2.7

3.4

V

10H = -3.0 mA

VCC =4.75V

54,74

2.0

V

10H = -12 mA

VCC =4.50V

74

2.0

V

10H = -15 mA

VCC =4.75V

54

0.55

V

10L= 48 mA

74

0.55

V

10L= 64 mA

Output Off Current HIGH

50

JJ.A

VOUT=2.7V

VCC= MAX

Output Off Current LOW

-50

JJ.A

VOUT= 0.5 V

VCC= MAX

VOL

Output LOW Voltage

10lH
lOlL
IIH

Input HIGH Current

IlL

LIMITS
TYP

20

lOS

Output Drive Current
Note 2

ICO'I

Power Supply
Current HIGH

ICCL

Power Supply
Current LOW

ICCl

Power Supply
Current OFF

Other

-1.0

Data Inputs
F241,F244

-1.6

54
74

-100
-100

-275
-275

F240

I'A

VIN=2.7V

VCC = MAX

VIN = 7.0V
mA

VIN = 0.5 V

VCC= MAX

mA

VOUT= GND

VCC= MAX

mA

VCC = MAX

35

F241,F244

60

F240

75

F241,F244

90

F240

75

F241,F244

90

NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.
2. Not more than one output should be shorted at a time, nor for more than 1 second.

FAST AND LS TTL DATA

4-93

II
I

100
Input LOW Current

VCC = MAX

II

MC54/74F240 • MC54/74F241 • MC54/74F244

F240
AC CHARACTERISTICS

SYMBOL

PARAMETER

54/74F
TA=+25°e
Vee=+5.0V
eL = 50 pF
MAX
MIN
TYP

54F
74F
TA = -55 to +125°e TA = 0 to +70o e,
Vee= 5.0 V±10% Vee = 5.0 V ± 10% UNITS
eL = 50 pF
eL = 50 pF
MAX
MIN
MIN
MAX

tpLH. Propagation Delay, Data to Output
tpHL

3.0
2.0

5.1
3.5

7.0
4.7

3.0
2.0

9.0
6.0

3.0
2.0

8.0
5.7

ns

tpZH
tpZL

Output Enable Time

2.0
4.0

3.5
6.9

5.2
9.0

2.0
4.0

6.5
13.5

2.0
4.0

5.7
10

ns

tpHZ
tpLZ

Output Disable Time

2.0
2.0

4.0
6.0

5.3
8.0

2.0
2.0

6.5
12.5

2.0
2.0

6.3
9.5

ns

F241
AC CHARACTERISTICS
tpLH
tpHL

Propagation Delay, Data to Output

2.5
2.5

4.0
4.0

5.2
5.2

2.0
2.0

6.5
7.0

2.5
2.5

6.2
6.5

ns

tpZH
tPZL

Output Enable Time

2.0
2.0

4.3
5.4

5.7
7.0

2.0
2.0

7.0
8.5

2.0
2.0

6.7
8.0

ns

tpHZ
tpLZ

Output Disable Time

2.0
2.0

4.5
4.5

6.0
6.5

2.0
2.0

7.0
12.5

2.0
2.0

7.0
7.5

ns

F244
AC CHARACTERISTICS
tpLH
tpHL

Propagation Delay, Data to Output

2.5
2.5

4.0
4.0

5.2
5.2

2.5
2.5

6.5
7.0

2.5
2.5

6.2
6.5

ns

tpZH
tpZL

Output Enable Time

2.0
2.0

4.3
5.4

5.7
7.0

2.0
2.0

7.0
8.5

2.0
2.0

6.7
8.0

ns

tpHZ
tpLZ

Output Disable Time

2.0
2.0

4.5
4.5

6.0
6.0

2.0
2.0

7.0
10.0

2.0
2.0

7.0
7.0

ns

FAST AND LS TIL DATA

4-94

MC54J.1F242/241l
MC14fF24J.2/243
QUAD BUS TRANSCEIVERS

(with 3-State OutputS)
DESCRIPTION - The MC54F/74F242 and MC54F174F243 are
Quad Bus TransmitterslReceivers designed for 4-line asynchronous
2-way data comm unication between data buses.

o
o

QUAD BUS TRANSCEIVERS
(WITH 3-STATE OUTPUTS)
FASTTM SCHOTTKY TTL

2-WAY ASYNCHRONOUS DATA BUS COMMUNICATION
INPUT CLAMP DIODES LIMIT HIGH-SPEED TERMINATION
EFFECTS

MC54F2421MC74F242

(TOPVIEWI

TRUTH TABLES
MC54F2421MC74F242
INPUTS
El

D

L
L
H
H

L
H

OUTPUT
H
L
(ZI
(ZI

X
X

INPUTS
E2

D

L
L
H
H

X
X
L

OUTPUT
(ZI
(ZI
H
L

H

MC54F243/MC74F243
MC54F243/MC74F243

INPUTS
El

D

L
L
H
H

L
H

OUTPUT

X
X

L
H
(ZI
(ZI

(TOPVIEWI

INPUTS
E2

D

L
L
H
H

X
X

OUTPUT

L
H

(ZI
(ZI
L
H

H =HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

Z = HIGH Impedance

Case 632-07 (Ceramicl
N Suffix - Case 646-05 (Plasticl

J Suffix -

GUARANTEED OPERATING RANGES
MIN

TYP

MAX

UNIT

54,74

4.5

5.0

5.5

V

Operating Ambient Temperature Range

54
74

-55
0

25
25

125
70

°c

IOH

Output Current -

High

54
74

-12
-15

mA

IOL

Output Current -

Low

54
74

48
64

mA

SYMBOL

PARAMETER

VCC

Supply Voltage

TA

FAST AND LS TTL DATA

4-95

MC54F/74F242 • MC54F/74F243

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
LIMITS
SYMBOL

PARAMETER

UNITS
MIN

VIH

Input HIGH Voltage

VIL

Inptlt LOW Voltage

VIK

Input Clarnp Diode Voltage

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

TYP

2.0

54
74
54.74
74

V

Guaranteed Input HIGH Voltage

0.8

V

Guaranteed Input LOW Voltage

-1.2

V

liN = -18 rnA

VCC= MIN

V
V
V
V

10H= -12 rnA
IOH=-15rnA
10H = -3.0 rnA
10H --3.0 rnA

VCC=4.50V
VCC=4.75V
VCC=4.50V
VCC-4.75V

0.55
0.55

V
V

IOL=48 rnA
10L= 64 rnA

VCC= MIN

p.A
p.A

VOUT= 2.7 V
VOUT- 5.5 V

VCC=MAX
VCC= MAX

2.0
2.0
2.4
2.7

54
74

TEST CONDITIONS

MAX

IOlH

Output Off Current HIGH

70
100

lOlL

Output Off Current LOW

-1.6

rnA

VOUT= 0.4 V

Enable
Data
Data
Enable

20
70
1.0
0.1

p.A
p.A
rnA
rnA

VIN=2.7V
VIN-2.7V
VIN = 5.5 V
VIN = 7.0V

Enable
Data*

-1.0
-1.6

rnA
rnA

VIN =0.5 V
VIN =0.5 V

VCC= MAX

-275

rnA

IIH

Input HIGH Current

IlL

Input LOW Current

lOS

Output Short Circuit Current (Note 2

VOUT=OV

VCC=MAX

ICCH

Power Supply
Current HIGH

F242
F243

60
80

rnA
rnA

Outputs
HIGH

VCC= MAX

'CCL

Power Supply
Current LOW

F242
F243

75
90

rnA
rnA

Outputs
LOW

VCC= MAX

ICCl

Power Supply
Current OFF

F242
F243

75
90

rnA
rnA

Outputs
OFF

VCC= MAX

-100

VCC= MAX

NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.
2. Not more than one output should be shorted at a time, nor for more than 1 second.

FAST AND LS TTL DATA

4-96

MC54F/74F242 • MC54F/74F243

AC CHARACTERISTICS

SYMBOL

54F174F
TA = +25°C
VCC = +5.0 V
CL = 50 pF

PARAMETER

54F
TA = -55°C to +125°C
VCC=5.0V±10%
CL = 50 pF

74F
TEST
CONDITIONS
TA = O°C to 70°C
SEE
VCC=5.0V±10% UNITS
FIGURE 1
CL = 50 pF

MIN

MAX

MIN

MAX

MIN

MAX

F242

3.0
1.5

7.0
4.7

3.0
1.5

9.0
6.0

3.0
1.5

8.0
5.7

ns
ns

Open

F242

2.0
4.0

4.7
9.0

2.0

6.5

4.0

12.0

2.0
4.0

5.7
10

ns
ns

Closed

Output Disable
Time

F242

2.0
2.0

5.3
6.5

2.0
2.0

6.5
12.5

2.0
2.0

6.3
8.0

ns
ns

Open
Closed

tPLH
tpHL

Propagation Delay,
Data to Output

F243

2.5
2.5

5.2
5.2

2.0
2.0

6.-6
8.5

2.0
2.0

6.2
6.5

ns
ns

Open

tpZH
tpZL

Output Enable
Time

F243

2.0
2.0

5.7
7.5

2.0
2.0

8.0
10.5

2.0
2.0

6.7
8.5

ns
ns

Closed

tPHZ
tpLZ

Output Disable
Time

F243

2.0
2.0

6.0
6.5"

1.5

7.5
12.5"

1.5
2.0

7.0
7.5"

ns
ns

Open
Closed

tpLH
tpHL

Propagation Delay,
Data to Output

tpZH
tpZL

Output Enable
.Jlme

tpHZ
tpLZ

2.0

S1 POSITION

NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.
2. Not more than one output should be shoned at a time, nor for more than 1 second.
*This limit may vary among competitors.

II
Fig. 1
7.0V

51

OUT

Test Point for High Impedance Scopes

For 50 n scopes, add a 450 n resistor

CL = 50 pF

in series with the scope and delete R2.

± 1.0%

FAST AND LS TTL DATA

4-97

®

MOTOROLA

MC54/74F245
OCTAL BIDIRECTIONAL TRANSCEIVER
WITH 3-STATE INPUTS/OUTPUTS
DESCRIPTION - The F245 contains eight noninverting bidirectional
buffers with 3-state outputs and is intended for bus-oriented applications. Current sinking capability is 20 rnA at the A ports and 64 m'A
at the B ports. The Transmit/Receive (T/RI input determines the direction of data flow through the bidirectional transceiver. Transmit
(active HIGHI enables data from A ports to B ports; Receive (active
lOWI enables data from B ports to A ports. The Output Enable input.
when HIGH, disables both A and B ports by placing them in a high-Z
condition.
•
•
•
•

OCTAL BIDIRECTIONAL
TRANSCEIVER WITH
3-STATE INPUTS/OUTPUTS
FASTTM SCHOTTKY TTL

NONINVERTING BUFFERS
BIDIRECTIONAL DATA PATH
B OUTPUTS SINK 64 rnA
MOS COMPATIBLE

CONNECTION DIAGRAM

TRUTH TABLE
INPUTS

----=
T/R

OUTPUT

OE

II

L
L
H

L
H

X

Bus B Data to Bus A
Bus A Data to Bus B
High-Z State

H ~ HIGH Voltage Level
L :::- LOW Voltage Level
X ~ Immatenal

J Suffix - Case 732-03
(Ceramic)

N Suffix -

Case 738-02
(Plastic)

GUARANTEED OPERATING RANGES
SYMBOL

MIN

TYP

MAX

UNIT

54, 74

4.5

5.0

5.5

V

54
74

-55
0

25
25

125
70

°c

PARAMETER

VCC

Supply Voltage

TA

Operating Ambient Temperature Range

IOH

Outpui Current -

High

An Outputs

54, 74

-3.0

rnA

IOl

Output Current -

low

An Outputs

54, 74

20

rnA

-12
-15

rnA

48
64

rnA

IOH

Output Current -

High

Bn Outputs

54
74

IOl

Output Current -

low

Bn Outputs

54
74

MOTOROLA SCHOTTKY TTL DEVICES
4-98

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
LIMITS
SYMBOL

PARAMETER

TYP

MIN

MAX

UNITS

VIH
VIL

I nput LOW Voltage

O.B

V

Guaranteed Input LOW Voltage

VIK

Input Clamp Diode Voltage

-1.2

V

liN =-18 rnA
10H =-1.0 rnA

VOH

VOH

2.0

Output HIGH Voltage
An Outputs

Output HIGH Voltage
Bn Outputs

54

2.5

3.4

V

2.4

3.3

V

2.5

3.3

V

74

2.7

3.3

V

54

2.4

3.4

V

74

2.5

3.4

V

74

2.7

3.4

54

2.0

74

2.0

V

IOH = -15 rnA

0.5
0.5

V
V

IOL= 20 rnA
IOL -24 rnA

VCC=MIN

0.55
0.55

V
V

IOL=48 rnA
IOL-B4 rnA

VCC=MIN

70

IlA

VOUT=2.7V

100

IlA
rnA

VOUT-5.5V

54
74

VOL

Output LOW Voltage
Bn Outputs

54
74

IOZH

Output Off Current HIGH

IlL
lOS
ICC

0.35
0.35

Output Off Current LOW

-1.0

OE, T/R Inputs

20

An, Bn Inputs

70

OE, T/R Inputs

100

Input HIGH Current

Input LOW Current
Output Drive
Current (Note 2)

VCC=MIN

54

Output LOW Voltage
An Outputs

IIH

Guaranteed Input HIGH Voltage

74

VOL

IOZL

V

TEST CONDITIONS

Input HIGH Voltage

10H =-3.0 rnA

VCC=4.50

10H =-3.0 rnA

VCC=4.75

10H =-3.0 rnA

VCC=4.50

V

10H =-3.0 rnA

VCC = 4.75

V

10H = -12 rnA

IlA
IlA

An, Bn Inputs

1.0

Il A
rnA

T/R Input

-O.B

rnA

An, Bn Inputs

-1.0

rnA

OE Input

-1.B

rnA

VCC=4.50

VCC = MAX

VOUT= 5.5V

VCC = MAX

VIN =2.7V
VCC=MAX

VIN =7.0V
VIN =5.5V
VIN =0.5V

VCC=MAX

An Outputs

-BO

-150

rnA

VOUT=GND

VCC = MAX

Bn Outputs

-100

-225

rnA

VOUT=GND

VCC = MAX

143

rnA

VCC = MAX

Power Supply Current

95

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable

device type.
2. Not more than one output should be shoned at a time.

AC CHARACTERISTICS

SYMBOL.

PARAMETER

54174F

54F

74F

TA = +25°C
VCC = +5.0 V
CL = 50 pF

TA = -55 to +125°C
VCC=5.0V±10%
CL = 50 pF

TA = 0 to +70·C
VCC = 5.0 V ±10%
CL = 50 pF

MIN

MIN

TYP

MAX

MIN

MAX

tpLH
tPHL

Propagation Delay
An to Bn or Bn to An

2.5
2.5

4.2
4.6

B.O
6.0

2.'5
2.5

7.0
7.0

ns

tpZH
tpZL

Output Enable Time

3.0
3.5

5.3
7.9

7.0
8.0

3.0
3.5

8.0
9.0

ns

tpHZ
tPLZ

Output Disable Time

25
2.0

5.0
3.7

6.5
6.5

2.5
2.0

.7.5
75

ns

FAST AND LS TTL DATA

4-99

MAX

UNITS

®

MOTOROLA

MC54F251
MC74F251

8-INPUT MULTIPLEXER

(With 3-State Outputs)
DESCRIPTION - The MC54F174F251 is a high-speed 8-input
digital multiplexer. It provides. in one package. the ability to select one
bit of data from uptoeightsources.ltcan be used as universal function
generator to generate any logic function of four variables. Both assertion and negation outputs are provided.

a-INPUT MULTIPLEXER
(With 3-State Outputs)
FASTTM

•
•
•

SCHOTTKY TTL

MULTIFUNCTIONAL CAPACITY
ON-CHIP SELECT LOGIC DECODING
INVERTING AND NON-INVERTING 3-STATE OUTPUTS

FUNCTIONAL DESCRIPTION - This device is a logical implementation of a single-pole. 8-position switch with the switch position controlled by the state of three Select inputs. SO. S1. S2. Both
assertion and negation outputs are provided. The Output Enable
input (OE) is active LOW. When it is activated. the logic function provided at the output is:
Z=OE· (10·
12·
14·
16·

SO· 5,. 52+11·
Sci· S1· 52+13·
SO· 51· S2 + 15·
So· S1 • S2 + 17·

SO·

5,.

S2 SI So
OE

52+

SO·

S, .

S2 +

SO· S1 • S2 +

7

10

4

11

3

12

2

13
5

Z

14

15

15

14

16

13

17

12

VCC = Pin 16
GND= Pin 8

OUTPUTS

OE

S2

S,

So

Z

Z

H
L
L
L

X
L
L
L

X
L
L
H

X
L

Z

10

H
L

I,

Z
10

12

12

L
L
L
L
L

L
H
H
H
H

H
L
L

H
L
H
L
H

13
14
15
16
17

13
14
15
16
17

H=
L=
X=
Z=

Z

6

TRUTH TABLE

H
H

9 10 11

SO· S1· S2+

When the Output Enable is HIGH. both outputs are in the high impedance (high Z) state. This feature allows multiplexer expansion by
typing the outputs of up to 128 devices together. When the outputs
olthe 3-state devices are tied together. all but one device must be in
the high impedance state to avoid high currents that would exceed
the maximum ratings. The Output Enable signals should be designed
to ensure there is no overlap in the active LOW portion of the enable
voltages.

INPUTS

LOGIC SYMBOL

CONNECTION DIAGRAM

h

HIGH Voltage Level
LOW Voltage Level
Immatenal
HIgh Impedance

J Suffix - Case 620-08
N Suffix -

FAST AND LS TTL DATA
4-100

(Ceramic)
Case 648-05
(Plastic)

MC54F174F251

LOGIC DIAGRAM

-{>

-V

-{>

- ......

."

•-V
r-....

So

T

11

I

11

II

I

) ~;t 'IIt 'IJ IIt
~illUf

J

1

h

~

z

Z

GUARANTEED OPERATING RANGES
SYMBOL
VCC

PARAMETER

MIN

Supply Voltage

TA

Operating Ambient Temperature Range

IOH

Output Current -

High

IOL

Output Current -

Low

54, 74

4.50

54
74
54, 74
54, 74

-55
0

FAST AND LS TTL DATA

4-101

I

TYP

MAX

UNIT

5.0

5.50

V

25
25

125
70
-3.0

rnA

24

rnA

°c

MC54F174F251

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

LIMITS

PARAMETER

VIH

Input HIGH Voltage

Vil

I nput lOW Voltage

VIK

Input Clamp Diode Voltage

VOH

Output HIGH Voltage

VOL

Output lOW Voltage

10ZH

MIN

TYP

MAX

2.0

UNITS

TEST CONDITIONS

V

Guaranteed Input HIGH Voltage

O.B

V

Guaranteed Input lOW Voltage

-1.2

V

liN = 18 rnA

VCC=MIN

54, 74

2.5

3.4

V

IOH=-3.0 rnA

VCC=4.50V

74

2.7

3.4

V

IOH =-3.0 rnA

VCC=4.75V

0.5

V

IOl=24 rnA

VCC=MIN

Output Off Current-HIGH

50

I'A

VOUT=2.7V

VCC = MAX

10Zl

Output Off Current-lOW

-50

I'A

VOUT=0.5V

VCC = MAX

IIH

Input HIGH Current

20

I'A

VIN=2.7V

100
-{l.6

I'A
rnA

VIN = 7.0V
VIN =0.5V

VCC = MAX

-150

rnA

VOUT=OV

VCC = MAX

rnA

In, Sn =4.5 V
OE=GND
OE,l n =4.5V

VCC=MAX

III

Input lOW Current

lOS

Output Short Circuit
Current (Note 2)

ICC

Power Supply Current

0.35

-50
ON

15

22

OFF

16

24

VCC = MAX

NOTES:
1. For conditions such as MIN or MAX. use the appropriate value specified under guaranteed operating ranges.
2. Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS

SYMBOL

PARAMETER

54174F
TA - +25°C
VCC= +5.0V
Cl = 50 pF
MIN
TYP
MAX

54F
74F
TA - -55 to +125°C TA = 0 to +70°C
VCC = 5.0 V±10% VCC = 5.0V ±10% UNITS
Cl = 50 pF
Cl = 50 pF
MIN

MAX

MIN

MAX

tPlH
tpHl

Propagation Delay
Sn toln

4.0
3.2

5.9
5.7

8.0
7.5

3.5
3.2

9.5
9.5

4.0
3.2

9.0
8.5

ns

tplH
tpHl

Propagation Delay
Sn toZn

4.5
4.5

9.6
6.9

13
9.0

3.5
3.0

16.5
10.5

4.5
4.0

14
10.5

ns

tplH
tpHl

Propagation Delay
In tol

3.0
1.5

4.1
3.0

5.7
4.0

2.5
1.5

8.0
6.0

3.0
1.5

7.0
5.0

ns

tpLH
tpHl

Propagation Delay
In toZ

4.0
3.0

7.2
5.1

9.5
6.5

3.5
3.0

11.5
7.5

4.0
3.0

10.5
7.5

ns

tpZH
tpZl

Output Enable Time
OEtol

3.0
3.0

5.4
6.4

7.0
8.5

3.0
3.0

9.5
10.5

3.0
3.0

8.0
9.5

ns

tPHZ
tpLZ

Output Disable Time
OEtoZ

3.0
2.0

5.0
3.2

6.5
4.5

3.0
2.0

8.5
7.5

3.0
2.0

7.5
5.5

ns

tPZH
tpZl

Output Enable Time
OEtoZ

4.0
3.5

6.9
6.0

9.0
8.0

4.0
3.5

10
10

4.0
3.5

10
9.0

ns

tPHZ
tpLZ

Output Disable Time
OEtoZ

3.0
2.0

4.7
3.5

6.0
4.5

3.0
2.0

7.0
8.0

3.0
2.0

7.0
5.5

ns

FAST AND LS TTL DATA

4-102

®

WlOTOROIL.A

MC54F253
MC74F253

DUAL 4-INPUT MULTIPLEXER

(with 3-State Outputs)

DESCRIPTION - The MC54Fn4F253 is a Dual 4-lnput Multiplexer
with 3-State Outputs. It can select two bits of data from four
sources using common select inputs. The outputs may be individually switched to a high-impedance state with a HIGH on the
respective Output Enable OE inputs. allowing the outputs to interface directly with bus oriented systems.

DUAL 4-INPUT MULTIPLEXER
WITH 3-STATE OUTPUTS
FAST'· SCHOTTKY TTL

LOGIC DIAGRAM

DEb

13b

@

@

12b

IDa

11 b

@

®

@

CONNECTION DIAGRAM DIP
(TOP VIEW)

OEa

(0
16
15
14
13
12
11
10
9

Vee = Pin 16
GND= PinS
= Pm Numbers

o

J Suffix - Case 620-08 (Ceramic)
N Suffix - Case 648-05 (Plastic)

GUARANTEED OPERATING RANGES
PARAMETER

SYMBOL
VCC

Supply Voltage

MIN

TYP

MAX

UNIT

54.74

4.5

5.0

5.5

V

54
74

-55
0

25
25

125
70

·C

-

-

-3.0

mA

24

mA

TA

Operating Ambient Temperature Range

IOH

Output Current - High

54.74

IOL

Output Current - Low

54.74

FAST AND LS TTL DATA

4-103

II

MC54Fn4F253

FUNCTIONAL DESCRIPTION
The F253 contains two identical 4-lnput Multiplexers with 3-State Outputs. They select two bits from four sources
selected by common Select Inputs (SO. S,). The 4-input multiplexers have individual Output Enable (OE a• OEb) inputs
which when HIGH. force the outputs to a high impedance (high Z) state.
The F253 is the logic implementation of a 2-pole. 4-position switch. where the position of the switch is determined by
the logic levels supplied to the two select inputs. The logic equations for the outputs are shown below:
Za = OEa ' (lOa' S, 'So
Zb = OEb' (lab' S, • So

+ I'a' S, • So + 12a' S, • So + 13a' S, • SO)
+ I'b' S, • So + 12b' S, • So + 13b' S, • So)

If the outputs of 3-state devices are tied together. all but one device must be in the high impedance state to avoid high
currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to 3-state devices
whose outputs are tied together are designed so that there is no overlap.
TRUTH TABLE
SELECT
INPUTS

OUTPUT
ENABLE OUTPUT

DATA INPUTS

So

51

10

11

12

X

X

X

L
L
H
H
L
L
H
H

L
L
L
L
H
H
H
H

L
H

X
X

X
X
X
X
X

X
L
H
X
X
X
X

X
X
X
X
X
X

L
H
X
X

13
X

OE

Z

H
L
L
L
L
L
L
L
L

IZ)
L
H
L
H
L
H
L
H

X

X
X
X
X

X
L
H

H = HIGH Level
L = LOW Level

X = Immaterial

IZI = High

Impedance (off)

Address inputs

So and 51

are common to both sections.

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

LIMITS

PARAMETER

MIN

TYP

MAX

UNITS

TEST CONDITIONS

VIH

Input HIG H Voltage

Vil

Input LOW Voltage

0.8

V

Guaranteed I nput LOW Voltage

VIK

Input Clamp Diode Voltage

-1.2

V

VOH

Output HIGH Voltage

VOL

Output lOW Voltage

2.0

V

Guaranteed Input HIGH Voltage
VCc::=MIN

I

54. 74

2.5

V

liN ='8 rnA
10H =-3.0 rnA

I

74

2.7

V

10H =-3.0 rnA

VCC = 4.75 V

0.5

V

IOl=24 rnA

VCC=MIN

VCC=4.50V

10ZH

Output Off Current-HIGH

50

p.A

VOUT=2.7V

VCC=MAX

10Zl

Output Off Current-lOW

-50

p.A

VCC=MAX

IIH

Input HIGH Current

III

Input lOW Current

lOS

Output Short Circuit
Current (Note 2)

ICC

-60

20

p.A

VOUT=0.5V
VIN =2.7V

0.'
-0.6

p.A

VIN=7.0V

rnA

VIN =0.5 V

VCC=MAX

-150

rnA

VOUT=OV

VCC = MAX

Power Supply Current
Total, Output HIGH

16

Total. Output lOW

23

Total at HIGH-Z

23

FAST AND LS TTL DATA

4-104

VCC = MAX

OEn=GND
10 =4.5 V; Sn, 11 -13 =GND
rnA

In, Sn, OEn = GND
VCC=MAX
OEn = 4.5 V, VCC - MAX
In, Sn=GND

MC54Fn4F253
AC CHARACTERISTICS

SYMBOL

TA
VCC
CL

PARAMETER

54F
TA = -55'C to + 125'C
VCC = 5.0 V :tl0%
CL = 50 pF

54n4F
= +25'C
= +5.0 V
= 50 pF

74F
TA = O'C to + 70'C
VCC = 5.0 V :tl0%
CL = 50 pF

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

tpLH
tpHL

Propagation Delay
Sn to Zn

4.5
3.0

11.5
9.0

3.5
2.5

15
11

4.5
3.0

13.5
10

ns

tpLH
tpHL

Propagation Delay
In to Zn

3.0
2.5

7.0
6.0

2.5
2.5

9.0
8.0

3.0
2.5

8.0
7.0

ns

tpZH
tpZL

Output Enable Time

3.0
3.0

8.0
8.0

2.5
2.5

10
10

3.0
3.0

9.0
9.0

ns

Output Disable Time

2.0
2.0

5.0
6.0

2.0
2.0

6.5
8.0

2.0
2.0

6.0
7.0

ns

tpHZ
tpLZ

SI
POSITION

OPEN

CLOSED
OPEN
CLOSED

AC TEST CIRCUIT
7.0 V

Rl = 500

n

±100/0
---0 Test Point for High Impedance Scopes

>---.....---.....
±1.0%

R2", 500
±10%

I

For 50 n scopes, add a
450 n resistor in 'series
with the scope and delete R2.

n

PROPAGATION DELAY MEASUREMENTS

I- - -+-.~ {R~'
_ _ VOL

t

0.3 V

NOTES:
1. All input waveforms have the following characteristics:
low Level = OV
High Level = 3.0 V
Rise and Fall Time. 110% to 90%) = 2.5 ns

2. All timing is measured at 1.5 V unless otherwise indicated.

FAST AND LS TTL DATA

4-105

®

MOTOROLA

MC54F257
MC74F257
QUAD 3-INPUT MULTIPLEXER
(With 3-State Outputs)

DESCRIPTION - The MC54F174F257 isa quad 2-input multiplexer
with 3-state outputs. Four bits of data from two sources ca n be
selected using a Common Data Select input. The four outputs present
the selected data in true (non-inverted) form. The outputs may be
switched to a high impedance state with a HIGH on the common
Output Enable (DE) input. allowing the outputs to interface directly
with bus oriented systems.
•
•
•

QUAD 2-INPUT MULTIPLEXER

(With 3-State Outputs)
FASTTM SCHOTTKY TTL

MULTIPLEXER EXPANSION BYTYING OUTPUTS TOGETHER
NON-INVERTING 3-STATE OUTPUTS
INPUT CLAMP DIODES LIMIT HIGH-SPEED TERMINATION
EFFECTS

LOGIC SYMBOL

S

OE
4

LOGIC DIAGRAM

7

II

Za

Zb

15

lOa

2

11a

3

lOb

5

lIb

6

12

Zc

10c

14

11 c

13

9

Zd

IOd

11

lId

10

VCC= Pin 16
GNO = Pin 8

CONNECTION DIAGRAM

VCC
OE
TRUTH TABLE
OUTPUT
ENABLE

SELECT
INPUT

OE

S

10

11

Z

H
L
L
L
L

X

X
X
X
L

X
L

(Zl

H
H
L
L

DATA
INPUTS

H

H
X
X

OUTPUTS

L
H
L
H

H :: HIGH Voltage Level
L :: LOW Voltage Level
X = Immaterial
\Z) = High Impedance

GND

J Suffix - Case 620-08
(Ceramic)

N Suffix - Case 648-05
(Plastic)

FAST AND LS TTL DATA

4-106

MC54F/74F257

GUARANTEED OPERATING RANGES
SYMBOL
VCC

PARAMETER
Supply Voltage

MIN

TYP

MAX

UNIT

54, 74

4.50

5.0

5.50

V

54
74

-55
0

25
25

125
70

DC

TA

Operating Ambient Temperature Range

10H

Output Current -

High

54, 74

-3.0

mA

10L

Output Current -

Low

54, 74

24

mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

MIN

LIMITS
TYP

MAX

UNITS
V

TEST CONDITIONS
Guaranteed Input HIGH Voltage

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

0.8

V

Guaranteed Input LOW Voltag!'

VIK

Input Clamp Diode Voltage

-1.2

V

liN; -18 mA

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

10lH

Output OFF Current -

lOlL

Output OFF Current -

2.0

54

2.5

3.4

V

10H; -1.0 mA

54

2.4

3.3

V

10H = -3.0 mA

74

2.5

3.3

V

10H = -3.0 mA

74

2.7

3.3

V

IOH=-3.0mA

Vee- 4 .75V

V

10L = 24 mA

VCC= MIN

HIGH

50

!LA

VOUT =2.7V

VCC= MAX

LOW

-50

!LA

VOUT= 0.5 V

VCC= MAX

Input HIGH Current
100

IlL

Input LOW Current

lOS

Output Short Circuit
Current (Note 2)

ICCH
ICCL
ICCl

Power Supply Current

Vec =4.50V

0.5

0.35

20
IIH

VCC; MIN

-60

!LA

VCC= MAX
VIN = 7.0 V

-0.6

mA

VIN = 0.5 V

VCC= MAX

-150

mA

VOUT= 0 V

VCC= MAX

9.0

15

14.5

22

15

VIN=2.7V

23

mA

S,11x=4.5V
OE, lOx = Gnd
11x-4.5V
OE, lOx, S = Gnd
S, lOx - Gnd
OE, 11 x = 4.5 V

NOTES:
1. For conditions such as MIN or MAX. use the appropriate value specified under guaranteed operating ranges.
2. Not more than one output should be shorted at a time. nor for more than 1 second.

FAST AND LS TTL DATA
4-107

VCC= MAX

II

MC54F/74F257

FUNCTIONAL DESCRIPTION - The F257 is a quad 2-input multiplexer with 3-state outputs. It
selects four bits of data from two sources under control of a Common Data Select input. When the
Select input is LOW, the lOx inputs are selected and when Select is HIGH, the 11 x inputs are selected.
The data on the selected inputs appears at the outputs in true (non-inverted) form. The device is the
logic implementation of a 4-pole, 2-position switch where the position of the switch is determined
by the logic levels supplied to the Select input. The logic equations forthe outputs are shown below:
Za=OE, (l1a' S+IO a '

5)

Zb= OE, (llb' S + lOb'S)

Zc = OE, (11 c' S + 10c'

5)

Zd=OE, (lld' S+IOd'

S)

When the Output Enable input (OE) is HIGH, the outputs are forced to a high impedance OFF state.
Ifthe outputs are tied together, all but one device must be in the high impedance state to avoid high
currents that would exceed the maximum ratings. Designers should ensure the Output Enable
signals to 3-state devices whose outputs are tied together are designed so there is no overlap.
AC CHARACTERISTICS

SYMBOL

54174F
TA = +25°C
VCC= +5.0V
CL = 50 pF

PARAMETER

54F
74F
TA = -55 to +125°C TA = 0 to +70 oC
VCC = 5.0 V ±10% VCC = 5.0V ±10%
CL = 50 pF
CL = 50 pF

UNITS

MIN

TYP

MAX

MIN

MAX

MIN

MAX

tpLH
tPHL

Propagation Delay
In to Zn

3.0
2.0

4.5
4.2

6.0
5.5

3.0
1.5

8.0
8.0

3.0
2.0

7.0
6.5

ns

tpLH
tpHL

Propagation Delay
StoZn

4.5
3.5

10.1
6.5

13
8.5

4.5
3.5

15.5
10.5

4.5
3.5

15
9.5

ns

tPZH
tpZL

Output Enable Time

3.0
3.0

5.9
5.5

7.5
7.5

3.0
3.0

9.5
10

3.0
3.0

8.5
8.5

ns

Output Disable Time

2.0
2.0

4.3
4.5

6.0
6.0

2.0
2.0

7.0
9.5

2.0
2.0

7.0
7.0

ns

tpZH
tpZL

FAST AND LS TTL DATA

4-108

®

MOTOROLA

MCS4F258
MC74F258
QUAD 2-INPUT MULTIPLEXER
(With 3-State Outputs)

DESCRIPTION - The MC54F174F258 is a quad 2-input mUltiplexer
with 3-state outputs. Four bits of data from two sources can be
selected using a Common Data Select input. The four outputs present
the selected data in the complement (inverted)form. The outputs may
be switched to a high impedance state with a HIGH on the common
Output Enable (OE) input, allowing the outputs to interface directly
with bus oriented systems.

QUAD 2-INPUT MULTIPLEXER
(With 3-State Outputs)
FASTTM

o MULTIPLEXER EXPANSION BYTYING OUTPUTS TOGETHER

o

SCHOTTKY TTL

LOGIC SYMBOLS

INVERTING 3-STATE OUTPUTS

S
OE
4

LOGIC DIAGRAM
OE

lOa

11 a

lOb

11b

10c

11c

10d

11d

S

7
12

9

Zd

15

lOa

2

11a

3

lOb

5

11b

6

10c

14

11c

13

10d

11

11d

10

VCC =Pin 16
GND= Pin 8

CONNECTION DIAGRAM

Zb

Zc

Zd

TRUTH TABLE

OUTPUT
ENABLE

SELECT DATA
INPUT INPUTS

OE

S

10

H
L
L
L
L

X
H
H
L
L

X
X
X
L
H

"
X
L
H
X
X

OUTPUTS
Z
Z
H
L
H
L

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance

J Suffix - Case 620-08
(Ceramic)
N Suffix - Case 648-05
(Plastic)

FAST AND LS TTL DATA

4-109

MC54F174F258

GUARANTEED OPERATING RANGES
SYMBOL
VCC

PARAMETER
Supply Voltage

MIN

TYP

MAX

UNIT

54, 74

4.50

5.0

5.50

V

54
74

-55

25
25

125
70

°c

TA

Operating Ambient Temperature Range

IOH

Output Current -

High

54, 74

-3.0

mA

10L

Output Current -

Low

54, 74

24

mA

a

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

MIN

LIMITS
TYP

MAX

UNITS

TEST CONDITIONS

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

0.8

V

Guaranteed loput LOW Voltage

VIK

Input Clamp Diode Voltage

-1.2

V

IIN=-18mA

V
V
V

VCC=4.75V

2.0

54
54
74
74

2.5
2.4
2.5

V

3.4
3.3
3.3

V
0.5

V

10L = 24 mA

VCC= MIN

Output OFF Current - HIGH

50

p.A

VOUT =2.7V

VCC= MAX

Output OFF Current - LOW

-50

p.A

VOUT= 0.5 V

VCC= MAX

Output HIGH Voltage

VOL

Output LOW Voltage

IOlH
lOlL

2.7

3.3
0.35

20
IIH

Input HIGH Current

IlL

Input LOW Current

lOS

Output Short Circuit
Current (Note 2)

ICCH

100

-60

p.A

Power Supply Current

VCC= MAX

-0.6

mA

VIN= 0.5 V

VCC= MAX

-150

mA

VOUT=

aV

VCC= MAX

mA

S,llx=4.5V
CE, lOx = Gnd
11x- 4.5V
OE, lOx, S = Gnd
S, 10x= Gnd
QE, 11x = 4.5 V

6.2

9.5

15.1

23

11.3

17

-

NOTES:
1. For conditions such as MIN or MAX, use the appropriate value speCified under guaranteed operating ranges.
2. Not more than one output should be shorted at a time, nor for more than 1 second.

FAST AND LS TTL DATA

4-110

VCC =4.50V

VIN= 2.7V
VIN = 7.0V

ICCl

VCC= MIN

IOH=-1.0mA
IOH=-3.0 mA
10H = -3.0 mA
IOH=-3.0mA

VOH

ICCL

Guaranteed Input HIGH Voltage

VCC= MAX

MC54F/74F258

FUNCTIONAL DESCRIPTION - The F258 is a quad 2-input multiplexer with 3-state outputs. It
selects four bits of data from two sources under control of a common Select input (S). When the
Select input is LOW, the lOx inputs are selected and when Select is HIGH, the 11x inputs are
selected. The data on the selected inputs appears at the outputs in inverted form. The F258 is the
logic implementation of a 4-pole, 2-position switch where the position of the switch is determined
by the logic levels supplied to the Select input. The logic equations for the outputs are shown below:
Za = OE· (11 a' S + IDa'
Zc=OE. (llc' S+loc '

5)
S)

Zb=OE. (llb' S+IOb'
Zd=OE. (lld' S+IOd'

5)
S)

When the Output Enable input (OE) is HIGH. the outputs are forced to a high impedance OFF state.
If the outputs of the 3-state devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure
that Output Enable signals to 3-state devices whose outputs are tied together are designed so there
is no overlap.
AC CHARACTERISTICS

SYMBOL

PARAMETER

54174F
TA = +25°e
Vee=+5.0V
eL = 50 pF
MIN
TYP
MAX

54F
74F
TA--55 to+125°e TA - 0 to +70 oe
Vee = 5.0V ±10% Vee = 5.0V ±10% UNITS
eL = 50 pF
eL = 50 pF
MIN
MAX
MIN
MAX

tpLH
tpHL

Propagation Delay
In to Zn

2.5
1.5

4.0
3.5

5.3
4.7

2.0
1.5

7.5
6.0

2.5
1.5

6.0
5.5

ns

tPLH
tpHL

Propagation Delay
StoZn

4.0
4.0

6.5
7.3

8.5
9.5

4.0
4.0

12
11.5

4.0
4.0

9.5
11

ns

tpZH
tPZL

Output Enable Time

3.0
3.0

5.9
5.5

7.5
7.5

3.0
3.0

11
9.5

3.0
3.0

8.5
8.5

ns

tPZH
tpZL

Output Disable Time

2.0
2.0

4.3
4.5

6.0
6.0

1.5
2.0

7.0
9.0

2.0
2.0

7.0
7.0

ns

FAST AND LS TTL DATA

4-111

II

®

MOTOROLA

MC54F280
MC74F280

Fast Schottky TTL

9-Bit Parity Generator/Checker
The MC54n4F280 is a high-speed parity generator/checker that accepts nine bits of
input data and detects whether an even or an odd number of these inputs is HIGH.
If an even number of inputs is HIGH, the Sum Even output is HIGH. If an odd number is HIGH, the Sum Even output is LOW. The Sum Odd output is the complement
of the Sum Even output.
LOGIC SYMBOL
IS

CASE 632-07

a

CASE 646-05

Please note that this diagram is
provided only for the
understanding of logic
operations and should not be
used to estimate propagation
delays.

Logic Diagram

TRUTH TABLE

1: Even

1: Odd

H
L

L
H

0,2,4,6,8
1,3,5,7,9
H

~

HIGH Voltage Level

L

~

CONNECTION
DIAGRAM

Outputs

Number of HIGH Inputs
lo-Is

LOW Voltage Level,

GUARANTEED OPERATING RANGES
Symbol
VCC

Parameter
Supply Voltage

Min

Typ

Max

Unit

54,74

4.5

5

5.5

V

54

-55

25

125

74

0

25

70

·C

TA

Operating Ambient Temperature Range

iOH

Output Current -

High

54,74

-1

mA

IOL

Output Current -

Low

54,74

20

mA

FAST AND LS TIL DATA

4-112

MC54F174F280

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits

Symbol

Parameter

Min

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

VIK

Input Clamp Diode Voltage

Typ

V

Guaranteed Input HIGH Voltage for
All Inputs

0.8

V

Guaranteed Input LOW Voltage for
All Inputs

-1.2

V

VCC = MIN, liN = -18 mA

2

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

Input HIGH Current

IlL

Input LOW Current

lOS

Short Circuit Current (Note 2)

ICC

Power Supply Current

Te.t Conditions

Units

Max

54

2.5

3.4

V

VCC = MIN, 10H = -1 mA,

74

2.7

3.4

V

VIN = VIH or VIL per Truth Table

54

0.30

0.5

V

74

0.35

0.5

V

-60
25

..

10L = 20 mA

I

VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table

20

pA

VCC = MAX, VIN = 2.7 V

100

pA

VCC = MAX, VIN = 7 V

-0.6

mA

VCC = MAX, VIN = 0.5 V

-150

mA

VCC = MAX, VOUT = 0 V

38

mA

VCC = MAX

..

NOTES: 1. For conditions such as MIN or MAX, use the appropriate value specified under guaranteed operatmg ranges .
2. Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS

Symbol

54/74F
TA = +2S'C
VCC=+5V
CL = SO pF

Parameter

54F
TA = -SS to +12S'C
VCC = SV :1:10%
CL=SOpF

74F
TA = Oto +70'C
VCC = SV :1:10%
CL = 50 pF

Min

Typ

Max

Min

Max

Min

Max

Units

tpLH
tpHL

Propagation Delay
In to ~E

6.5
6:5

10
11

15
16

6.5
6.5

20
21

6.5
6.5

16
17

ns

tPLH
tPHL

Propagation Delay
In to ~O

5.0
6.5

10
11

15
16

5.0
6.5

20
21

5.0
6.5

16
17

ns

+7V

IPZl' IpLZ, OC

OPEN

ALL OTHER

500n

500n

'INCLUDES JIG AND PROBE CAPACITANCE
Figure 1. Test Load

Figure 2. Whether Response Is Inverting or NonInverting Depends on Specific Truth Table Conditions

FAST AND LS TTL DATA

4-113

II

II

@ MOTOROl.A
MC54F283
MC74F283
Advance Information
4-BIT BINARY FULL ADDER
(With Fast Carry)
DESCRIPTION - MCS4F174F283 high-speed 4-bit binary full
adder with internal carry lookahead accepts two 4-bit binary words
(AO -A3, BO - B3) and a Carry input(Co)·lt generates the binary 5um
outputs(50 - 53) and the Carry output(C4) from the most significant
bit. The 'F283 will operate with either active-HIGH or active-LOW
operands (positive or negative logic).

4-BIT BINARY FULL ADDER
(With Fast Carry)
FAS"p M

FUNCTIONAL DESCRIPTION - The 'F283 adds tw04-bit binary
words (A plus B) plus the incoming carry CO. The binary sum appears
on the 5um (50 -53) and outgoing carry (C4) outputs. The binary
weight olthe various inputs and outputs is indicated by the subscript
numbers, representing powers of two.

SCHOTTKY TTL

LOGIC SYMBOL

7

Co

20 (AQ+BO+CO)+2' (A, +B,)
+22 (A2+B2)+23(A3+B3)
= 50 + 25, + 452 + 853 + l6C4
Where (+) = plus

4

Ao

50
51

Interchanging inputs of equal weight does not affect the operation.
ThusCO,AQ, BO can be arbitrarily assigned to pins S, 6 and7. Dueto
the symmetry of the binary add function, the 'F283 can be used
either with all inputs and outputs active HIGH (positive logic) or with
all inputs and outputs active LOW (negative logic). 5ee Figure A.
Note that if Co is not used it must be tied LOW for active-HIGH logic
or tied HIGH for active-LOW logic.

13
10

52
.53

5

BO

6

A1

3

B1

2

A2

14

B2

15

A3

12

B3

11

C4

9

Due to pin limitations, the intermediate carries of the 'F283 are not
brought out for use as inputs or outputs. However, other means
can be used to effectively insert a carry into, or bring a carry out
from, an intermediate stage. Figure 8 shows how to make a 3-bit
adder. Tying the operand inputs of the fourth adder (A3, 83) LOW
. makes S3 dependent only on, and equal to, the carry from the third
adder. Using somewhat the same principle, Figure C shows a way
of dividing the 'F283 into a 2-bit and a l-bit adder. The third stage
adder (A2, 82, 52) is used merely as a means of getting a carry
(C1O) signal into the fourth stage (via A2 and 82) and bringing out
the carry from the second stage on 52. Note that as long as A2 and
82 are the same, whether HIGH or LOW, they do not influence 52.
Similarly, when A2 and 82 are the same the carry into the third
stage does not influence the carry out of the third stage. Figure D
shows a method of implementing a S-input encoder, where the
inputs are equally weighted. The outputs SO, S, and S2 present a
binary number equal to the number of inputs I, -IS that are true.
Figure E shows one method of implementing a S-input majority
gate. When three or more of the inputs I, -IS are true, the output MS
is true.

VCC: Pin 16
GND = Pin 8

CONNECTION OIAGRAM

J Suffix - Case 620-08
(Ceramic)
N Suffix - Case 648-06
(Plastic)

FAST AND LS TTL DATA

4-114

MC54F/74F283

LOGIC DIAGRAM

Co Ao

A2

BO

So

B2

B3

S1

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

GUARANTEED OPERATING RANGES
SYMBOL
VCC

PARAMETER
Supply Voltage

TA

Operating Ambient Temperature Range

IOH

Output Current - High

IOL

Output Current -

Low

MIN

TIP

MAX

UNIT

54, 74

4.50

5.0

5.50

V

54
74
54,74
54,74

-55
0

25
25
-

125
70
-1.0
20

-

-

FIGURE A - Active-HIGH versus Active-LOW Interpretation

Co

All

A,

A2

A3

Bo B,

B2

B3

So

S,

52

Logic Levels

L

L

H

L

H

H

L

L

H

H

H

L

L

H

Active HIGH
Active LOW

0

0

1
0

0

0

0

1

1

1
0

1
0

1
0

0

1

0
1

1

1

1
0

0
1

0

Active HIGH: 0 + 10 +9 =3 + 16

1

Active LOW: 1 +5 +6 = 12 +0

FAST AND LS TTL DATA

4-115

1

53 C4

DC
mA
mA

II

MC54F 174F283

FIGURE B - 3-Bit Adder

FIGURE C - 2-Bit and I-Bit Adder.
L

Co

Cl1

FIGURE E - 5-lnput Majority Gate

FIGURE 0 - 6-lnput Encoder

II

M5

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

VIK

Input Clamp Diode Voltage

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

Input HIGH Current

IlL

Input LOW Current
Co Input
A and B Inputs

lOS

Output Short Circuit
Current (Note 2)

ICC

Power S upplV Current

MIN

LIMITS
TYP

MAX

UNITS
V

Guaranteed Input HIGH Voltage

0.8

V

Guaranteed Input LOW Voltage

-1.2

V

liN = -18 mA

VCC= MIN

V
V

10H =-1.0 mA
IOH= -1.0 mA

VCC =4.50V

0.5

V

IOL=20 mA

VCC= MIN

20
100

p.A
p.A

VIN = 2.7 V
VIN-7.0V

VCC= MAX

-0.6
-1.2

mA
mA

VIN =0.5 V

VCC=MAX

-150

mA

VOUPOV

VCC= MAX

55

mA

Inputs = 4.5 V

VCC= MAX

2.0

154.,74
174

2.5
2.7

3.4
3.4
0.35

-60
36

TEST CONDITIONS

NOTES:
1. For conditions such as MIN or MAX, use the appropriate value specified under guaranteed operating ranges.
2. Not more than one output should be shorted at a time, nor for more than I second.

FAST AND LS TTL DATA

4-116

VCC=4.75 V

MC54F174F283

AC CHARACTERISTICS

SYMBOL

PARAMETER

54174F
TA =+25°C
VCC =+5.0 V
CL =50 pF
MIN
MAX
1YP

74F
54F
TA =-55 to +125°C TA =0 to +70°C
VCC =5.0 V ±10% VCC =5.0 V ±1 0% UNITS
CL =50 pF
CL =50 pF
MIN

MAX

MIN

MAX

tPLH
tpHL

Propagation Delay
Co to Sn

3.5
4.0

7.0
7.0

9.5
9.5

3.5
4.0

14
14

3.5
4.0

10.5
10.5

ns

tpLH
tpHL

Propagation Delay
An or Bn to Sn

4.0
3.5

7.0
7.0

9.5
9.5

4.0
3.5

14
14

4.0
3.5

10.5
10.5

ns

tpLH
tpHL

Propagation Delay
Co toC4

3.5
3.0

5.7
5.4

7.5
7.0

3.5
3.0

10.5
10

3.5
3.0

B.5
8.0

ns

tpLH
tpHL

Propagation Delay
An or Bn to C4

3.5
3.0

5.7
5.3

7.5
7.0

3.5
3.0

10.5
10

3.5
3.0

8.5
8.0

ns

II
,

FAST AND LS TTL DATA

4-117

II

®

MOTOROLA

MC54F350
MC74F350

Advance Information
4-BIT SHIFTER
(With 3-State Outputs)

4-BIT SHIFTER

(With 3-State Outputs)
DESCRIPTION - MC54F/74F350 is a specialized multiplexer that
acceptsa4-bitword and shifts itO, " 2 or3 places, as determined by
two 5elect (50, 5,) inputs. For expansion to longer words, three
linking inputs are provided for lower-order bits; thus two packages
can shift an8-bitword, four packages a '6-bitword, etc. 5hifting by
more than three places is accomplished by paralleling the 3-state
outputs of different packages and using the Output Enable (OE)
inputs as a third 5elect level. With appropriate interconnections, the
'F350 can perform zero-backfill, sign-extend or end-around (barrel)
shift functions.

FASTTM SCHOTTKY TTL

LOGIC SYMBOL

'3 9 10

• Linking Inputs for Word Expansion
• 3-State Outputs for Extending Shift Range

OE S1 So
L3

FUNCTIONAL DESCRIPTION - The 'F350 isoperationally equivalent to a 4-input multiplexer with the inputs connected so that the
select code causes successive one-bit shifts of the data word. This
internal connection makes it possible to perform shiftsofO, " 2 or 3
places on words of any length.
A 7-bit data word is introduced at the In inputs and is shifted
according to the code applied to the select inputs 50,5,. Outputs
00-03 are3-state, controlled by an active-LOW output enable(OE).
When OE is LOW, data outputs will follow selected data inputs;
when HIGH, the data outputs will be forced to the high-impedance
state. This feature allows shifters to be cascaded on the same
output lines or to a common bus. The shift function can be logical,
with zeros pulled in at either or both ends of the shifting field;
arithmetic, where the sign bit is repeated during a shift down; or end
around, where the data word forms a continuous loop.

15

00

L2

2

14

01

L1

3

12

02

10

4

03

11

5

12

6

13

7

11

VCC = Pin 16
GND = Pin 8

CONNECTION DIAGRAM

LOGIC EQUATIONS
00=505, 10+505, '-, +50 5, '-2+5 0 5 , '-3
0, =505, I, +508, 10+505, '-, +505, '-2
02=508, 12+508, I, +505, 10+505, '-,
03=505,13+508,12+505,1,+505,10

TRUTH TABLE
INPUTS
OE

5,

So

00

H
L
L
L
L

X

X

L
L
H
H

L
H
L
H

Z
10
1-,
1-2
1-3

OUTPUTS
0,
02

Z

h
10
1-,
1-2

Z
12
h
10
1-,

03

Z
13
12

h
10

J Suffix - Case 620-08
(Ceramic)
N Suffix - Case 648-05
(Plastic)

H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial

FAST AND LS TTL DATA

4-118

MC54F174F350
LOGIC DIAGRAM
1.3

1.1

51

GUARANTEED OPERATING RANGES
SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

54, 74

4.50

5.0

5.50

V

54
74

-55
0

25
25

125
70

DC

VCC

Supply Voltage

TA

Operating Ambient Temperature Range

10H

Output Current -

High

54, 74

-

-

-3.0

mA

10L

Output Current -

Low

54,74

-

-

24

mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

MIN

LIMITS
TYP

MAX

UNITS

2.0

TEST CONDITIONS

VIH
VIL

Input LOW Voltage

0.8

V

Guaranteed Input LOW Voltage

VIK

Input Clamp Diode Voltage

-1.2

V

liN =-18 mA

VCC = MIN

V
V
V

IOH=-1.0mA
10H =-3.0 mA
10H =-3.0 mA

VCC= MIN

54
VOH

Output HIGH Voltage

54
74

2.5
2.4
2.7

V

Guaranteed Input HIGH Voltage

Input HIGH Voltage

3.4
3.3
3.3

VOL

Output LOW Voltage

0.5

V

10L = 20 mA

VCC = MIN

10lH

Output OFF Current -

HIGH

50

!J.A

VOUT=2.7V

VCC = MAX

lOlL

Output OFF Current -

LOW

-50

!J.A

VOUT =0.5 V

VCC = MAX

IIH

0.35

20

Input HIGH Current

IlL

Input LOW Current

lOS

Output Short Circuit
Current (Note 2)

ICCH
ICCL
ICCl

Power Supply Current

100

-60
22
26
26

VIN = 2.7 V
!J.A

VIN=7.0V

VCC = MAX

-1.2

mA

VIN =0.5 V

VCC = MAX

-150

mA

VOUT = 0 V

VCC= MAX

35
41
42

mA

Outputs HIGH
Outputs LOW
Outputs OFF

VCC= Max

NOTES: 1. For conditions such as MIN or MAX, use the appropriate value specified under guaranteed operating ranges.
2. Not more than one output should be shorted at a time, nor for more than 1 second.

FAST AND LS TTL DATA

4-119

MC54F174F350

AC CHARACTERISTICS

SYMBOL

54174F
TA - +25°C
VCC=+5.0V
CL = 50 pF
MIN
TYP
MAX

PARAMETER

54F
74F
TA - -55 to +125°C TA = 0 to +70 o C
VCC = 5.0 V ±10% VCJ:_= 5.0 V ±10% UNITS
CL = 50 pF
CL = 50 pF
MIN
MAX
MIN
MAX

tPLH
tPHL

Propagation Delay
In to On

3.0

4.5

6.0

3.0

7.5

3.0

7.0

2.5

4.0

5.5

2.5

7.0

2.5

6.5

tpLH
tpHL

Propagation Delay
Sn to On

4.0
3.0

7.8
6.5

10
8.5

4.0
3.0

13
10

4.0
3.0

11
9.5

5.0
7.0

7.0
9.0

2.5

8.5
11

2.5

8.0

3.9

5.5
5.5

4.0
2.0
2.0

6.5
6.5

tpZH
tPZL

2.5

Output Enable Time

tpHZ
tpLZ

4.0
2.0
2.0

Output Disable Time

4.0

4.0
2.0
2.0

7.0
.8.5

ns
ns
ns

10

ns

APPLICATIONS
16-Bit Shift-Up 0 to 3 Places, Zero Backfill

o

II

I

GNOI1l

r---

-

56-31.21.11011 12 13
51

~OE
yO

Y1

Y2

Y3

2

3

-

I

S~31.21.110 11 12 13

r-- 51
-c OE

12131415

8 91011

4 5 6 7

1 2 3

-

I

1

56-31.21.1 10 11 12 13

r-- 51
-c OE

-

I

Sk31.21.110 11 12 13

r-- 51

Y2

Y3

YO

Y1

Y2

Y3

OE
YO

Y1

Y2

456

7

8

9

10

11

12

13

14

YO

Y1

-(l

So
51
OE

o
51 So
L L NO SHIFT
L H 5HIFT 1 PLACE
H L SHIFT 2 PLACES
H H SHIFT 3 PLACE5

FAST AND LS TTL DATA

4-120

I

YO

15

MC54F/74F350
8-Bit End Around Shift 0 to 7 Places

o

1 2 3

4 5 6 7

I

T I

I
I

I I

.--- 5~-31.21.1 10 11

12 13

-

; - - 51

r<

OE
YO

Yl

Y2

Y3

2

3

-

.--

-

-

51
OE
YO

Yl

Y2

r<

Y3

OE
YO

I

I

12 13
r - - 5~-31.21.110 11
51

5631.21.110 11 12 13

Yl

Y2

Y3

5

6

7

-c

5~31.21.1 10 11 12 13

51
OE
YO

Yl

Y2

Y3

So
51
52

52

o
52
L
L
L
L
H

51
L
L
H
H
L

So
L
H
L
H
L

NO SHIFT
SHIFT ENO AROUND
SHIFT END AROUND
SHIFT END AROUND
SHIFT END AROUND

1
2
3
4

4
52
H
H
H

51
L
H
H

So
H SHIFT END AROUND 5
L SHIFT END AROUND 6
H SHIFT END AROUND 7

II
I

13-Bit Twos Complement Scaler

1211109

B 7 6 5

II
.------

I

56-31.21.11011 12 13

r--- 51

-:-

5631-21.110 1112 13

Yl

Y2

Y3

I

I
I
I

I
I
I

I

11

10

9

I
I

I
12

ILL
,----

-

r O EYo

Yl

Y2

I

I

I
8

7

6

51

Y3

I

-:- I

SCALE
51 So
L L.8
1/8
1/4
L H~
112
H L.2
H H NO CHANGE
1

FAST AND LS TTL DATA

4-121

5~-31.21.110 11 12 13

r O EYo

I
5

5

3 2 1

III

-

r--- 51

r O EYo
So
51

4

4

Yl

Y2

1 21

3

Y3

I

5

®

MOTOROLA

MC54F352
MC74F352

DUAL 4-INPUT MULTIPLEXER
DESCRIPTION - The MC54F174F352 is a very high speed dual
4-input multiplexer with common Select inputs and individual
Enable inputs for each section. It can select two bits of data from four
sources. The two buffered outputs present data in the inverted
(complementary) form. The 'F352 is the functional equivalent ofthe
'F153 except with inverted outputs.

DUAL 4-INPUT
MULTIPLEXER
FASTTM SCHOTTKY TTL

• Inverted Version of the 'F153
• Separate Enables for Each Multiplexer
• Input Clamp Diode limits High Speed Termination Effects

LOGIC SYMBOL
2

14

51

So

LOGIC DIAGRAM
Za

7

II

9~

Zb

Ea

1

lOa

6

11 a

5

12a

4

13a

3

lOb

10

11b

11

12b

12

13b

13

Eb

15

CONNECTION DIAGRAM

J Suffix - Case 620-08
(Ceramic)
N 5 uffix - Case 648-05
(Plastic)

FAST AND LS TTL DATA

4-122

MC54F/74F352

GUARANTEED OPERATING RANGES
SYMBOL
5upply Voltage

VCC

MIN

TYP

MAX

UNIT

54, 74

4.50

5.0

5.50

V

54
74

-55
a

25
25

'25
70

°c

-

-

-'.0

rnA

-

20

rnA

PARAMETER

TA

Operating Ambient Temperature Range

IOH

Output Current -

High

54,74

IOL

Output Current -

Low

54, 74

FUNCTIONAL DESCRIPTION - The 'F352 is a dual4-input multiplexer. It selects two bits of data from up to four sources under the
control olthe common Select inputs(SO, S, I. Thetw04-input multiplexer circuits have individual active-LOW Enables(Ea:Ebl which can be
used to strobe the outputs independently. When the Enables (Ea, Ebl are HIGH. the corresponding outputs (la, Zbl are forced HIGH.
The logic equations for the outputs are shown below:
Za = Ea- (lOa
Zb = Eb

0

0

S, • So + I, a .5, • So + (2a • 5, • 50 + 13a • 5, • SO)

(lab. 5,

0

50 + I, b • 5, • 50 + 12b • 5,

0

50 + 13b • S, • So)

The 'F352 can be used to move data from a group of registers to a common output bus. The particular register from which the
data came would be determined by the state of the Select inputs. A less obvious application is as a function generator. The
'F352 can generate two functions of three variables. This is useful for implementing highly irregular random logic.

TRUTH TABLE
SELECT
INPUTS

INPUTS la or bl

OUTPUT

So

S,

E

10

I,

12

Ia

Z

X

X

X

L
L
H

L
L
L

H
L
L
L

X
X
X

X
X
X
X

X
X
X
X

H
H
L
H

H
L
L
H
H

L
H
H
H
H

L
L
L
L
L

L
H
L
H
L

L
H
X

L

X

H

X

X
X
X
X

X
X
X
X

L
H

X
X
X

X
X

L
H

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

FAST AND LS TIL DATA

4-123

II

II

MC54F174F352

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

MIN

LIMITS
TYP

TEST CONDITIONS

UNITS

MAX

V

Guaranteed Input HIGH Voltage

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

0.8

V

Guaranteed Input LOW Voltage

VIK

Input Clamp Diode Voltage

-1.2

V

IIN=-18mA

V
V

IOH =-1.0 mA
IOH =-1.0 mA

V

IOL=20 mA

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

Input HIGH Current

IlL

Inpu't LOW Current

lOS

Output Short Circuit
Current (Note 2)

ICCH
ICCL

Power Supply Current

2.0

L54.74
I 74

2.5
2.7

3.4
3.4
0.35

0.5
20

9.3
13.3

VCC -4.75 V
VCC= MIN

VIN =2.7V
JlA

100

-60

VCC= MIN
. VCC = 4.50 V

VIN =7.0V

VCC= MAx

-0.6

mA

VIN =0.5 V

VCC=MAX

-150

mA

VOUT=OV

VCC = MAX

14
20

mA

VIN =Gnd
VIN - HIGH

VCC = MAX

NOTES:

1. For conditions such as MIN or MAX, use the appropriate value specified under guaranteed operating ranges.
2. Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS

SYMBOL

PARAMETER

54174F
TA=+25°C
VCC=+5.0V
CL = 50 pF
MIN
TYP
MAX

74F
54F
TA - -55 to +125°C TA = 0 to +70°C
VCC = 5.0 V ±10% VCC = 5.OV ±10% UNITS
CL = 50 pF
CL = 50 pF
MIN
MAX
MIN
MAX

tpLH
tpHL

Propagation Delay
Sn toZn

3.5
3.0

7.4
7.0

11
8.5

3.0
2.5

1~

11

3.0
2.5

12.5
9.5

ns

tpLH
tpHL

fropaJ!,ation Delay
En to Zn

2.5
3.0

5.0
5.0

7.0
7.0

2.0
2.5

10
9.0

2.0
2.5

8.0
8.0

ns

tPLH
tpHL

Propagation Delay
IntoZn

2.5
1.5

4.9
3.0

7.0
3.5

2.0
1.0

9.0
5.0

2.0
1.0

8.0
4.0

ns

FAST AND LS TTL DATA

4-124

®

MOTOROLA

MC54F353
MC74F353

DUAL 4·INPUT MULTIPLEXER
(With 3·State Outputs)
DESCRIPTION - The MC54F174F353 is a dual 4·input multiplexer with 3-state outputs. It can select two bits of data from four
sources using common Select inputs. The outputs may be individually switched to a high impedance state with a HIGH on the
respective Output Enable (OE) inputs, allowing the outputs to
interface directly with bus oriented systems.
8 I nverted Version of 'F253
8 Multifunction Capability
8 Separate Enables for Each Multiplexer

DUAL4-INPUT MULTIPLEXER
(With 3-5tate Outputs)

LOGIC SYMBOL

FUNCTIONAL DESCRIPTION - The 'F353 contains two identical
4-input multiplexers with 3-state outputs. They select two bits from
four sources selected by common Select inputs(SO, S1). The4-input
multiplexers have individual Output enable (OE a, OEb) inputs
which, when HIGH, force the outputs to a high impedance (high Z)
state. The logic equations for the outputs are shown below:

14

S, So
OEa

Za
Za = OEa 8 (lOa 851 8 So + 11 a 851 8 So +
12a 8 S1 8 So + 13a 8 S1 8 SO)
Zb=OEb8(IOb 8S18So+11b8S18S0+
12b8S1 8S0+13b8S1 8 SO)
Zb
If the outputs of 3-state devices are tied together, all but one device
must be in the high impedance state to avoid high currents that
would exceed the maximum ratings. Designers should ensure that
Output Enable signals to 3-state devices whose outputs are tied
together are designed so that there is no overlap.

lOa
1, a
12a
13a
lab
l,b
12b
13b
DEb

10
11
12
13
15

VCC = Pin 16

GND = Pin 8

CONNECTION DIAGRAM

TRUTH TABLE
SELECT
DATA INPUTS
INPUTS

OUTPUT
OUTPUT
ENABLE

So

S,

10

11

12

13

OE

Z

X

X

X

L
L
H

L
L
L

L
H

X
X
X

X

L

X
X
X
X

X
X
X
X

H
L
L
L

IZI
H
L
H

H
L
L
H
H

L
H
H
H
H

X
X
X
X
X

H

X

X
X
X
X

L
H

X
X
X

X
X

L
H

L
L
L
L
L

L
H
L
H
L

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
(Z) = High Impedance

Address mputs So and S1 are common to both sections.

J Suffix - Case 620-08 (Ceramic)
N Suffix - Case 648-05 (Plastic)

FAST AND LS TTL DATA

4·125

II

I

MC54F174F353

LOGIC DIAGRAM

II

GUARANTEED OPERATING RANGES
SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

54, 74

4.50

5.0

5.50

V

54
74

-55
0

25
25

125
70

°c

VCC

Supply Voltage

TA

Operating Ambient Temperature Range

IOH

Output Current -

High

54, 74

-3.0

mA

IOL

Output Current -

Low

54, 74

24

mA

AC CHARACTERISTICS

SYMBOL

PARAMETER

54174F
TA-+25°C
VCC = +5.0 V
CL" 50 pF
MIN
TYP
MAX

54F
74F
TA - -55 to +125°C
TA - 0 to +70°C
VCC"5.0V±10% VCC" 5.0 V ±10% UNITS
CL" 50 pF
CL" 50 pF
MIN

MAX

MIN

MAX

tPLH
tpHL

Propagation Delay
Sn toZn

3.5
3.5

8.0
6.5

11
8.5

3.0
2.5

14
11

3.0
2.5

12.5
9.5

ns

tPLH
tpHL

Propagation Delay
In tOln

2.5
1.0

5.6
2.5

7.0
3.5

2.0
1.0

9.0
5.0

2.0
1.0

8.0
4.0

ns

tpZH
tpZL

Output Enable Time

3.0
3.5

6.8
7.2

8.0
8.0

3.0
3.0

10.5
10.5

3.0
3.0

9.0
9.0

tPHZ
tpLZ

Output Disable Time

2.0
2.0

3.7
4.4

5.0
6.0

2.0
1.5

7.0
8.0

1.5
1.5

6.0
7.0

FAST AND LS TTL DATA

4-126

ns

MC54F174F353
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

MIN

LIMITS
TYP

MAX

UNITS

TEST CONDITIONS

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

0.8

V

Guaranteed Input LOW Voltage

VIK

Input Clarnp Diode Voltage

-1.2

V

liN = -18 rnA

VCC=MIN

V
V
V

10H =-1.0 rnA
10H =-3.0 rnA
10H =-3.0 rnA

VCC = 4.50V

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

10lH

Output OFF Current -

lOlL

54
54
74
74

2.5
2.4
2.5
2.7

V

3.4
3.3
3.3
3.3

Guaranteed Input HIGH Voltage

V

10H = -.3.0 rnA

VCC =4.75V

0.5

V

10L = 24 rnA

VCC =MIN

HIGH

50

JJ.A

VOUT=2.7V

VCC=MAX

Output OFF Current - LOW

-50

JJ.A

VOUT=0.5 V

VCC=MAX

IIH

Input HIGH Current

IlL

Input LOW Current

lOS

Output Short Circuit
Current (Note 2)

~
~
ICCl

2.0

Power Supply Current

0.35

20
100

-60
9.3
13.3
15

VIN =2.7V
JJ.A

VIN=7.0V

VCC=MAX

-0.6

rnA

VIN =0.5V

VCC = MAX

-150

rnA

VOUT=OV

VCC=MAX

14
20
23

rnA

In. Sn. OEn=Gnd
In. Sn = Gnd
VCC = Max
OEn =4.5 V

NOTES:
1. For conditions such as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable
device type.
2. Not more than one output should be shorted at a time. nor for more than 1 second.

II

FAST AND LS TTL DATA

4-127

®

MOTOROLA

MC54f373
MC74f373

OCTAL TRANSPARENT LATCH
(With 3-State Inputs)

OCTAL TRANSPARENT LATCH

DESCRIPTION - The MC54Fn4F373 consists of eight latches with
3-state outputs for bus organized system applications. The flipflops appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup times is
latched. Data appears on the bus when the Output Enable (OE) is
LOW. When OE is HIGH the bus output is in the high impedance
state.

FASTTM SCHOTTKY TTL

(With 3-State Inputs)

CONNECTION DIAGRAM

• Eight Latches in a Single Package
• 3-State Outputs for Bus Interfacing

LOGIC SYMBOL

3

II

11

4

7

8 13 14 17 18

LE

2

Vcc = Pin 20
GND = Pin 10

5

6

9 12 15 16 19

J Sullix - Case 732-03
(Ceramicl
N Sullix - Case 738-01
(Plasticl

GUARANTEED OPERATING RANGES
SYMBOL

MIN

TYP

MAX

UNIT

54, 74

4.50

5.0

5.50

V

54
74

55
0

25
25

125
70

°c

PARAMETER

VCC

Supply Vol1age

TA

Operating Ambient Temperature Range

IOH

Output Current -

High

54,74

3.0

mA

IOL

Output Current - Low

54,74

24

mA

FAST AND LS TTL DATA

4-128

MC54F174F373

FUNCTIONAL DESCRIPTION - The 'F373 contains eight D-type latches with 3-state output buffers. When the Latch
Enable(LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch
output will change state each time its D input changes. When LE is LOW the latches store the information that was present
on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-state buffers are controlled by the Output
Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering new data into the latches.

LOGIC DIAGRAM

Please note that this diagram

IS

provided only for the understanding of logic operations and should not be used to estimate propagation

delays.

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL
VIH

PARAMETER

MIN

Input HIGH Voltage

LIMITS
TYP

MAX

2.0

TEST CONDITIONS

UNITS
V

Guaranteed Input HIGH Voltage

VIL

Input LOW Voltage

0.8

V

Guaranteed Input LOW Voltage

VIK

Input Clamp Diode Voltage

-1.2

V

IIN=-18mA

V

IOH
IOH
IOH
IOH

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IOZH

Output OFF Current -

IOZL
IIH

2.5
2.4
2.5
2.7

3.4
3.3
3.3
3.3

V
V
0.5

V
V

HIGH

50

Output OFF Current - LOW

-50

0.35

20

Input HIGH Current

IlL

Input LOW Current

lOS

Output Short Circuit
Current (Note 2)

ICCZ

54
54
74
74

Power Supply Current
(All Outputs OFF)

35

rnA
rnA
rnA
rnA

VCC= MIN
VCC =4.50V
VCC=4.75V

IOL= 24 rnA

VCC= MIN

p.A

VOUT =2.7V

VCC=MAX

p.A

VOUT=0.5 V

VCC=MAX

p.A

100

-60

=-1.0
= -3.0
= -3.0
--3.0

VIN = 2.7V
VIN = 7.0V

VCC=MAX

-0.6

rnA

VIN =0.5 V

VCC = MAX

-150

rnA

VOUT=OV

VCC=MAX

55

rnA

DE =4.5 V
D n, LE = Gnd

VCC=MAX

NOTES:
1. For conditions such as MIN or MAX. use the appropriate value specified under recommended operating conditions for the applicable
deVice type.
2. Not more than one output should be shorted at a time. nor for more than 1 second.

FAST AND LS TTL DATA

4-129

II

MC54F174F373

AC CHARACTERISTICS

SYMBOL

PARAMETER

54174F
TA - +25 c e
Vee=+5.0V
eL =50 pF
MIN
TYP
MAX

54F
74F
TA - -55 to +125 c e TA - 0 to +70c e
Vee = 5.0 V ±10% Vee = 5.0V ±10%
eL = 50 pF
eL = 50 pF
MIN
MAX
MIN
MAX

UNITS

tpLH
tpHL

Propagation Delay
On toOn

3.0
2.0

5.3
3.7

7.0
5.0

3.0
2.0

8.5
7.0

3.0
2.0

8.0
6.0

ns

tpLH
tpHL

Propagation Delay
LE toOn

5.0
3.0

9.0
5.2

11.5
7.0

5.0
3.0

15
8.5

5.0
3.0

13
8.0

ns

IpZH
tpZL

Output Enable Time

2.0
2.0

5.0
5.6

11
7.5

2.0
2.0

13.5
10

2.0
2.0

12
8.5

ns

Output Disable Time

2.0
2.0

4.5
3.8

6.5
6.0

2.0
2.0

10
7.0

2.0
2.0

7.5
6.0

ns

tpHZ
tpLZ

AC OPERATING REQUIREMENTS:

II

SYMBOL

PARAMETER

54174F
TA - +25 c e
Vee =+5.0V
MIN
TYP
MAX

74F
54F
TA -55 to +125 c e TA - 0 to +70 c e
Vee = 5.0V±10% Vee = 5.0V±10% UNITS
MIN
MAX
MIN
MAX

tslH)
ts IL)

Setup Time, HIGH or LOW
On to LE

2.0
2.0

2.0
2.0

2.0
2.0

thlH)
thlL)

Hold Time, High or LOW
On to LE

3.0
3.0

3.0
3.0

3.0
3.0

twlH)

LE Pulse Width HIGH

6.0

6.0

6.0

FAST AND LS TTL DATA

4-130

ns

ns

®

MOTOROLA

MC54F314
MC141F314

OCTAL D-TYPE FLIP-FLOP

(With 3-State Outputs)
DESCRIPTION - The MC54F/74F374 is a high-speed,low-power
octal D-type flip-flop featuring separate D-type inputs for each flipflop and 3-state outputs for bus oriented applications. A buffered
Clock (CP) and Output Enable (DE) are common to all flip-flops .

OCTAL D-TYPE FLIP-FLOP
(With 3-State Outputs)
FASTTM

SCHOTTKY TTL

• Edge-triggered D-Type Inputs
• Buffered Positive Edge-triggered Clock
I) 3-State Outputs for Bus Oriented Applications
LOGIC SYMBOL

FUNCTIONAL DESCR IPTION - the 'F374 consists of eight edgetriggered flip-flops with individual D-type inputs and 3-state true
outputs. The buffered clock and buffered Output Enable are common
to all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold times requirements
on the LOW-to-HIGH Clock (CP) transition. With the Output Enable
(OE) LOW, the contents of the eight flip-flops are available at the
outputs. When the OE is HIGH, the outputs go to the high impedance
state. Operation of the DE input does not affect the state of the
flip-flops.

11

2
5
6
9
12
15
16
19

TRUTH TABLE
INPUTS
On
H
L

X

If

CP

.r
X

OE CP
00
DO
01
°1
02
°2
03
03
04
04
05
D5
06
07

D6
D7

3
4
7
8
13
14
17
18

OUTPUTS
OE

~I

On

VCC ~ Pin 20
GND ~ Pin 10

H
L

Z

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance

CONNECTION DIAGRAM

J Suffix - Case 732-03 (Ceramic)
N Suffix -

FAST AND LS TTL DATA

4-131

Case 738-01 (Plastic)

II

MC54F/74F374

LOGIC DIAGRAM

GUARANTEED OPERATING RANGES
SYMBOL
VCC

PARAMETER
Supply Voltage

MIN

TYP

MAX

UNIT

54. 74

4.50

5.0

·5.50

54
74

-55
0

25
25

125
70

°C

V

TA

Operating Ambient Temperature Range

10H

Output Current -

High

54.74

-3.0

mA

10L

Output Current -

Low

54.74

24

mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

MIN

LIMITS
TYP

MAX

UNITS

TEST CONDITIONS

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

0.8

V

Guaranteed Input LOW Voltage

VIK

Input Clamp Diode Voltage

-1.2

V

IIN=-18mA

VCC=MIN

V
V

10H = -1.0 mA
10H =-3.0 mA
10H =-3.0 mA

VCC=4.50V

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

10ZH

Output OFF Current -

10ZL

Output OFF Current -

2.0

54
54
74
74

IIH

Input HIGH Current

IlL

Input LOW Current

lOS

Output Short Circuit
Current (Note 2)

2.5
2.4
2.5
2.7

V

3.4
3.3
3.3

V

10H = -3.0 mAo

VCC=4.75V

0.5

V

10L= 24 mA

VCC=MIN

HIGH

50

p.A

VOUT =2.7V

VCC=MAX

LOW

-50

p.A

VOUT =0.5V

VCC = MAX

3.3
0.35

20
100

-60

p.A

(All Outputs OFF)

VIN=2.7V
VIN =7.0V

VCC = MAX

-0.6

mA

VIN =0.5 V

VCC = MAX

-150

mA

VOUT=OV

VCC = MAX

On = Gnd

Power Supply Current
ICCL

Guaranteed Input HIGH Voltage

55

86

mA

OE =4.5V

NOTES.
1. For conditions such as MIN or MAX, use the appropriate value specified under guaranteed operating ranges.
2. Not more than one output should be shorted at a time, nor for more than 1 second.

FAST AND LS TTL DATA

4-132

VCC=MAX

MC54F174F374

AC CHARACTERISTICS

SYMBOL

54F
74F
TA - -55 to +125°C TA = 0 to +70°C
VCC = 5.0 V ±10% VCC=5.0V±10%
CL = 50 pF
CL = 50 pF

54174F
TA-+25°C
VCC = +5.0 V
CL = 50 pF

PARAMETER
MIN

TYP

MAX

MIN

MAX

MIN

MAX
MHz

70

60

UNITS

f max

Maximum Clock Frequency

100

tpLH
tpHL

Propagation Delay
CP toOn

4.0
4.0

6.5
6.5

8.5
8.5

4.0
4.0

10.5
11

4.0
4.0

10
10

tpZH
tpZL

Output Enable Time

2.0
2.0

9.0
5.8

11.5
7.5

2.0
2.0

14
10

2.0
2.0

12.5
8.5

tPHZ
tpLZ

Output Disable Time

2.0
2.0

5.3
4.3

7.0
5.5

2.0
2.0

8.0
7.5

2.0
2.0

8.0
6.5

ns

ns

AC OPERATING REQUIREMENTS:

SYMBOL

PARAMETER

54174F
TA=+25°C
VCC = +5.0 V
MIN
TYP
MAX

74F
54F
TA = -55 to +125°C TA=Oto+70°C
VCC = 5.0 V ±10% VCC = 5.0V ±10%
MIN
MAX
MIN
MAX

ts(H)
ts(L)

Setup Time, HIGH or LOW
Dn toCP

2.0
2.0

2.5
2.0

2.0
2.0

th(H)
th(L)

Hold Time, HIGH or LOW
Dn toCP

2.0
2.0

2.0
2.5

2.0
2.0

tw(H)
tw(L)

CP Pulse Width, HIGH or LOW

5.0
5.0

7.0
6.0

7.0
6.0

FAST AND LS TTL DATA

4-133

UNITS

ns

ns

II

II

®

MOTOROLA

MC54F378
MC74F378
PARALLEL D REGISTER WITH ENABLE
DESCRIPTION - The MC54Fn4F378 is a 6-bit register with a buffered common enable. This device is similar to the 'F174, but with
common Enable rather than common Master Reset.

PARALLEL D REGISTER
WITH ENABLE

The 'F378 consists of six edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The Clock (CP) and Enable (E)
inputs are common to all flip-flops.

FAST'"

When the E input is LOW, new data is entered into the register
on the LOW-to-HIGH transition of the CP input. When the E input
is HIGH the register will retain the present data independent of
the CP input. This circuit is designed to prevent false clocking by
transitions on the E input.
• 6-BIT HIGH-SPEED PARALLEL REGISTER
• POSITIVE EDGE-TRIGGERED D-TYPE INPUTS

SCHOTTKY TTL

LOGIC SYMBOL

• FULLY BUFFERED COMMON CLOCK AND ENABLE INPUTS
• INPUT CLAMP DIODES LIMIT HIGH SPEED TERMINATION
EFFECTS
• FULL TTL AND CMOS COMPATIBLE

LOGIC DIAGRAM
DO

DS

14

DS

05

15

13

D4

C4

12

11

D3

6

D2

4

D1

3

DO

03

10

02

7

01
00

ep-C~--~~--~-+----~r---~~--~-+---,

2

9
Vee = Pin 16
GND = Pin 8

CONNECTION DIAGRAM
TRUTH TABLE
INPUTS

OUTPUT

E

ep

Dn

an

H
L
L

---'
---.r
---.r

X

No change
H
L

H
L

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial

FAST AND LS TTL DATA

4-134

MC54Fn4F378

GUARANTEED OPERATING RANGES
PARAMETER

SYMBOL
Supply Voltage

VCC

MIN

TYP

MAX

UNIT

54,74

4.5

54
74

-55
0

5.0

5.5

V

25
25

125
70

'c

TA

Operating Ambient Temperature Range

10H

Output Current -

High

54,74

-1.0

mA

10L

Output Current -

Low

54,74

20

mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

LIMITS

PARAMETER

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

VIK

Input Clamp Diode Voltage

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

Input HIGH Current

IlL

Input LOW Current

lOS

Output Short Circuit
Current (Note 2)

ICC

Power Supply Current

MIN

TYP

UNITS

MAX

2.0

V

TEST CONDITIONS
Guaranteed Input HIGH Voltage

0.8

V

Guaranteed Input LOW Voltage

-1.2

V

VCC = MIN, liN = -18 mA

154,74

2.5

V

10L = -1.0 mA

I

2.7

V

10L = -1.0 mA

VCC =4.75 V

V

10L = 20 mA

VCC = MIN

74

0.5

-60

VCC =4.50V

20

pA

VCC = MAX, VIN = 2.7 V

0.1

mA

VCC = MAX, VIN = 7.0 V

-0.6

mA

VCC = MAX, VIN = 0.5 V

-150

mA

VCC = MAX, VOUT = 0 V

mA

VCC = MAX, VCP = 0 V

30

45

NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device

type.
2. Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS
54174F
SYMBOL

PARAMETER
MIN

TYP

f max

Maximum Input Frequency

80

140

tpLH
tpHL

Propagation Delay
CP to On

3.0
3.5

5.5
6.0

MAX

MIN
I

7.5
8.5

FAST AND LS TTL DATA

4-135

74F

54F

TA = -55 to + 125'C TA = Oto +70'C
VCC = 5.0 V ±10% VCC=5.0V±10%
CL = 50 pF
CL = 50 pF

TA = +25'C
VCC = +5.0 V
CL = 50 pF

MAX

3.0
3.5

MIN

MAX

80

80
9.5
10.5

3.0
3.5

UNITS

MHz
8.5
9.5

ns

II

I

MC54F/74F378

AC OPERATING REQUIREMENTS
54174F
SYMBOL

54F

PARAMETER
MIN

TYP

74F

TA = -55to +125'C TA = Oto +70'C
UNITS
VCC = 5.0 V ±10% VCC = 5.0 V ±10%

TA = +25'C
VCC = +5.0 V

MIN

MAX

MAX

MIN

ts (HI
ts (LI

Set up Time, HIGH or LOW
Dn to CP

4.0
4.0

4.0
4.0

4.0
4.0

th (HI
th (LI

Hold Time, HIGH or LOW
Dn to CP

0,0
0.0

0.0
0.0

0.0
0.0

ts (HI
t s (LI

Set up Time, HIGH or LOW
E to CP

6.0'
6.0'

6.0
6.0

6.0'
6.0'

th (HI
th (LI

Hold Time, HIGH or LOW
E to CP

2.0
2.0

2.0
2.0

2.0
2.0

tw(HI
tw(LI

CP Pulse Width, HIGH or LOW

4.0
6.0

4.0
6.0

4.0
6.0

MAX

*This limit may vary among competitors.

AC TEST CIRCUIT

Test Point for High Impedance Scopes
R2=500n
±10%
For 50 n scopes, add a
450 n resistor in series
with the scope and delete
R2.

Fig. 1

FAST AND LS TTL DATA

4-136

ns

ns

ns

®

MOTOROLA

MC54F379
MC74F379

QUAD PARALLEL REGISTER
DESCRIPTION - The MC54F174F379 is a 4-bit register with a buffered common enable. This device is similar to the 'F175 but features the common Enable rather than common Master Reset.
The 'F379 consists of four edge-triggered D-type flip-flops with
individual D inputs and Q and Q outputs. The Clock (CP) and
Enable (E) inputs are common to all flip-flops. When E is HIGH,
the register will retain the present data independent of the CP
input. The Dn and E inputs can change when the clock is in either
state, provided that the recommended setup and hold times are
observed. This circuit is designed to prevent false clocking by
transitions on the E input.

QUAD PARALLEL REGISTER
WITH ENABLE
FAST'M

SCHOTTKY TTL

LOGIC SYMBOL

• EDGE-TRIGGERED D-TYPE INPUTS
• BUFFERED POSITIVE EDGE-TRIGGERED CLOCK
• BUFFERED COMMON ENABLE INPUT
• TRUE AND COMPLEMENT OUTPUTS

15

13

D3

12

D2

5

D1

4

DO

03
14

LOGIC DIAGRAM

10
11

7
DO

D1

6

CP--~~--4r--t-----~---r------~-+------,

2

E

3

9
00

00

01

VCC = Pin 16
GND = Pin 8

01

CONNECTION DIAGRAM

TRUTH TABLE

INPUTS

OUTPUTS

E

CP

Dn

On

On

H
L
L

...r
...r

X
H
L

NC
H
L

NC
L
H

.J"

H = HIGH Voltage Level
L = LOW Voltage Level

X = Immaterial
NC = No Change

FAST AND LS TTL DATA

4-137

II

I

MC54F/74F379

GUARANTEED OPERATING RANGES
SYMBOL

PARAMETER
Supply Voltage

VCC

MIN

TYP

MAX

UNIT

54,74

4.5

5.0

5.5

V

54
74

-55
0

25
25

125
70

·C

Operating Ambient Temperature Range

TA
10H

Output Current -

High

54,74

-1.0

mA

10L

Output Current -

Low

54,74

20

mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

LIMITS

PARAMETER

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

VIK

Input Clamp Diode Voltage

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

Input HIGH Current

IlL

Input LOW Current

lOS

Output Short Circuit
Current (Note 2)

ICC

Power Supply Current

MIN

TYP

UNITS

MAX

2.0

154,74

2.5

I

2.7

74

V
0.8

V

Guaranteed Input LOW Voltage

-1.2

V

VCC

V

10L

V

-60

TEST CONDITIONS
Guaranteed Input HIGH Voltage

0.5

V

20

p.A

= MIN, liN = -18 mA
VCC=4.50V
= -1.0 mA
VCC = 4.75 V
10L = -1.0 mA
10L = 20 mA
VCC = MIN
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V
VCC = MAX, VIN = 0.5 V

0.1

mA

-0.6

mA

-150

mA

VCC

=

MAX, VOUT

40

mA

VCC

=

MAX, D

28

= 0V

=E=

GND, CP

=...J

NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device

type.
2. Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS
54/74F
SYMBOL

TA
VCC
CL

PARAMETER

54F

= +25·C
= +5.0 V
= 50 pF

MIN

TYP

f max

Maximum Clock Frequency

100

140

tpLH
tpHL

Propagation Delay
CPto Qn, an

3.5"
5.0

5.0
6.5

MAX

MIN

MAX

90
6.5
8.5

FAST AND LS TTL DATA

4-138

74F

TA = -55to +125·C TA = Oto +70'C
VCC = 5.0V ±10% VCC = 5.0V ±10% UNITS
CL = 50 pF
CL = 50 pF

3.5
5.0

MIN

MAX
MHz

100
8.5
10.5

3.5"
5.0

7.5
9.5

ns

MC54F/74F379

AC OPERATING REQUIREMENTS
54174F
SYMBOL

54F

TA = +25'C
VCC = +5.0 V

PARAMETER
MIN

TYP

74F

TA = -55 to + 125'C TA = Oto +70'C
UNITS
VCC = 5.0V :!:10% VCC = 5.0V :!:10%

MAX

MIN

MAX

MIN

ts (H)
ts (L)

Set up Time, HIGH or LOW
On to CP

3.0
3.0

3.0
3.0

3.0
3.0

th (H)
th (Ll

Hold Time, HIGH or LOW
On to CP

1.0
1.0

1.0
1.0

1.0
1.0

ts (HI
ts (Ll

Setup Time, HIGH or LOW
Eto CP

6.0
6.0

6.0
6.0

6.0
6.0

th (HI
th (Ll

Hold Time, HIGH or LOW
Eto CP

2.0'
2.0'

2.0
2.0

2.0'
2.0'

tw(H)
tw (Ll

CP Pulse Width, HIGH or LOW

4.0
5.0

4.0
5.0

4.0
5.0

MAX

ns

"ns

ns

-This limit may vary among competitors.

AC TEST CIRCUIT

>----....- - -...--0

Test Point for High Impedance Scopes

R2=500n
:!:10%
For 50 n scopes, add a
450 n resistor in series
with the scope and delete
R2.
Fig. 1

FAST AND LS TTL DATA

4-139

II

®

MOTOROLA

MCS4F381
MC74F381

Advance Information
4-BIT ARITHMETIC LOGIC UNIT
4-BIT ARITHMETIC LOGIC UNIT
FASTTM SCHOTTKY TTL
DESCRIPTION - The MC54F174F381 performs three arithmetic
and three logic operations on two 4-bit words, A and 8. Two
additional Select input codes force the Function outputs lOW or
HIGH. Carry Propagate and Generate outputs are provided for use
with the 'F182 Carry lookahead Generator for high-speed expansion to longer word lengths. For ripple expansion, refer to the
'F382 AlU data sheet.
•
•
•
•

CONNECTION DIAGRAM

low Input Loading Minimizes Drive Requirements
Performs Six Arithmetic and Logic Functions
Selectable Low (Clear) and High (Preset) Functions
Carry Generate and Propagate Outputs for use with Carry
Lookahead Generator

lOGIC SYMBOL

II

3 4

1

2 1918 1716

15
7
6
5

VCC = Pin 20
GND = Pin 10

8

9

11

12

J Suffix - Case 732-03 (Ceramic)
N Suffix - Case 738-01 (Plastic)

GUARANTEED OPERATING RANGES
SYM80L
VCC

PARAMETER
Supply Voltage

MIN

TYP

MAX

UNIT

54, 74

4.50

5.0

5.50

V

54
74

-55
0

25
25

125
70

°C

TA

Operating Ambient Temperature Range

IOH

Output Current -

High

54, 74

-1.0

mA

IOl

Output Current -

low

54,74

20

rnA

FAST AND LS TTL DATA

4-140

MC54F174F381

LOGIC DIAGRAM

cn - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
80 --T--d=::=::I""-"

~-+_--r-tl-----ID- FO
Ao -l---f1tttm:=<
81

----.----------=;ttJtm=<

A1---L---rlU1~<
82

----.----------=:;ttJtm=<

II

A2 ----6------i
"-ttttti--'

83 ----r-------,

P

A3

~ ONLY
'F381

G

50

D-OVR

Cn +4

51

52

FAST AND LS TTL DATA

4-141

'F382
ONLY

II

MC54F174F381

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

MIN

LIMITS
TYP

UNITS

MAX

TEST CONDITIONS

VIH

Input HIGH Voltage

V

Guaranteed Input HIGH Voltage

VIL

Input LOW Voltage

0.8

V

Guaranteed Input LOW Voltage

VIK

Input Clamp Diode Voltage

-1.2

V

liN = -18 mA

VCC = MIN

V
V

IOH =-1.0 mA
IOH =-1.0 mA

VCC=4.50V
VCC=4.75V
VCC = MIN

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

IIH

154,74
174

2.5
2.7

3.4
3.4
0.35

Input HIGH Current

IlL

Input LOW Current
So - S2 Inputs
Other Inputs

lOS

Output Short Circuit
Current (Note 2)

ICC

2.0

-SO
59

Power Supply Current

0.5

V

IOL=20 mA

20

"A

VIN =2.7 V

100

"A

VIN =7.0V

..{l.S
-2.4

mA
mA

VIN =0.5 V
VIN -0.5 V

VCC=MAX

-150

mA

VOUT=OV

VCC=MAX

mA

So-S2 = GND;
VCC=MAX
Other Inputs HIGH

89

VCC=MAX

NOTES:
,. For conditions such as MIN or MAX, use the appropriate value specified under guaranteed operating ranges.
2. Not more than one output should be shorted at a time. nor for more than 1 second.

FUNCTIONAL DESCRIPTION - Signals applied to the Select inputs So -S2 determine the mode of operation, as indicated
in the Function SelectTable. An extensive listing of input and output levels is shown in the Truth Table. The circuit performs
the arithmetic functions for either active-HIGH or active-LOW operands, with output levels in the same convention. In the
Subtract operating modes, it is necessary to force a carry (HIGH for active-HIGH operands, LOW for active-LOW operands)
into the Cn input of the least significant package.
The Carry Generate (G) and Carry Propagate (p) outputs supply input signals to the 'F182 carry lookahead generator for
expansion to longer word length, as shown in Figure A. Note that an 'F382 ALU is used for the most significant package.
Typical delays for Figure A are given in Figure B.

FUNCTION SELECT TABLE
SELECT

OPERATION

So

S,

S2

L
H
L
H

L
L
H
H

L
L
L
L

Clear
B Minus A
A Minus B
A Plus B

L
H
L
H

L
L
H
H

H
H
H
H

A(±)B
A+B
AB
Preset

H = HIGH Voltage Level

L = LOW Voltage Level

FAST AND LS TTL DATA

4-142

MC54F174F381

FIGURE A -

, 6-Bit lookahead Carry ALU Expansion

COUT
OVERFLOW

..F.;.O_-F_3J,1.....l.I..--,-L_ _F_4_-_F7...1.1....I.I._.....I_ _F..;;8;..-F..;I..;IJ,1....JOI._-L_... FI2- F'5
GO Po

Cn

+x

Cn + y

G, P,

Cn + z

G2 P2

'F182 CLA

FIGURE B -

, 6-Bit Delay Tabulation

PATH SEGMENT

TOWARD
F
7.2 ns
6.2 ns
B.l ns

AI or BI to P

P; to Cn. J ('F1B21
Cn to F
en to en

+ 4.

OUTPUT
t 4, OVR

en

-

-

8.0 ns

21.5 ns

21.4 ns

OVR

Total Delay

7.2 ns
6.2 ns

AC CHARACTERISTICS

SYMBOL

PARAMETER

54/74F
TA-+25°C
VCC = +5.0 V
CL = 50 pF
MIN
MAX
TYP

54F
74F
TA - -55 to +125°C TA - 0 to +70°C
VCC = 5.0 V ±10% VCC=5.0V±10%
CL = 50 pF
CL = 50 pF

UNITS

MIN

MAX

MIN

tpLH
tpHL

Propagation Delay
Cn to Fi

2.5
2.5

8.1
5.7

10.5
8.0

2.5
2.5

15
11.5

2.5
2.5

11.5
9.0

ns

tPLH
tPHL

Propagation Delay
Any A or B to Any F

4.0
3.0

10.4
8.2

13.5
11

4.0
3.0

19
15.5

4,0
3.0

14.5
12

ns

tPLH
TpHL

Propagation Delay
Si to Fi

4.5
4.0

8.3
8.2

11
11

4.5
4.0

15.5
15.5

4.5
4.0

12
12

ns

tpLH
tpHL

Propagation Delay
Ai or Bi toG

3.5
4.0

6.4
6.8

9.0
10

3.5
4.0

12.5
14

3.5
4.0

10
11

ns

tPLH
tPHL

Propagation Delay
Ai or Bi to P

4.0
3.5

7.2
6.5

10.5
9,5

4.0
3,5

15
13

4.0
3.5

11.5
10,5

ns

tPLH
tpHL

Propagation Delay
SitoGor?

4.0
4.5

7.8
10.2

10.5
13.5

4.0
4.5

15
19

4.0
4.5

11.5
14.5

ns

FAST AND LS TTL DATA

4-143

MAX

MC54F/74F381

TRUTH TABLE
INPUTS
FUNCTION
CLEAR

B MINUS A

A MINUS B

OUTPUTS

So

51

52

Cn An

0

0

0

X

0

1

0

1

0

0

Bn

Fa

Fl

F2

F3

G

P

X

X

0

0

0

0

0

0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1
0
0
1
0
1
1
0

1
1
0
1
0
1
0
0

1
1
0
1
0
1
0
0

1
1
0
1
0
1
0
0

1
0
1
1
1
0
1
1

0
0
1
0
0
0
1
0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1
0
0
1
0
1
1
0

1
0
1
1
0
0
1
0

1
0
1
1
0
0
1
0

1
0
1
1
0
0
1
0

1
1
0
1
1
1
0
1

0
1
0
0
0
1
0
0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
1
0
1
0
0
1

0
1
1
1
0
0
0
1

0
1
1
1
0
0
0
1

0
1
1
1
0
0
0
1

1
1
1
0
1
1
1
0

1
0
0
0
1
0
0
0

1
1
1
0

1
1
0
0
1
1
1
0

A PLUS B

1

1

0

AffiB

0

0

1

X
X
X
X

0
0
1
1

0
1
0
1

0
1
1
0

0
1
1
0

0
1
1
0

0
1

1

X
X
X
X

0
0
1
1

0
1
0
1

0
1
1
1

0
1
1
1

0
1
1
1

0
1

,
1

1
1
1
1

0
0
1
1

0
1
0
1

0
0
0
1

0
0
0
1

0
0
0
1

0
0
0
1

0
1
0
1

0
1
0
0

0
0
1
1

0
1
0
1

1
1
1
1

1
1
1
1

1
1
1
1

1
1
1
1

1
1
1
1

1
1
1
0

A+B

1

0

AB

0

1

1

X
X
X
X

PRESET

1

1

1

X
X
X
X

1 = HIGH Voltage Level
0= LOW Voltage Level
X = Immaterial

FAST AND LS TTL DATA

4-144

,
0

®

MOTOROLA

MC54F521
MC74FS21
8-BIT IDENTITY COMPARATOR

DESCRIPTION - The MC54F174F521 is an expandable 8-bit
comparator. It compares two words of up to eight bits each and
provides a LOW output when the two words match bit for bit. The
expansion inputTA = B also serves as an active-LOW enable input.

8-BIT IDENTITY COMPARATOR

FASTTM SCHOTTKY TTL

• Compares Two a-Bit Words in 6.5 ns Typ
• Expandable to Any Word Length
• 20-Pin Package
LOGIC SYMBOL
LOGIC DIAGRAM

Ao
BO--[>o
A1
B1--[>0
A2
B2--[>0
A3
B3--[>0

A4
B4--J>c
AS
BS--J>c
AS
BS--[>o
A7
B7--t>O

t>:-l
t>:-l
b
b
b
b
b
b

19

OA=B

IA= B B7

18

A7
BS
AS
BS
AS
B4

17

OA=6

A4

63
A3
62
A2
61
A1
80

Ao

1S
1S
14
13
12
11
9
8
7
S
S
4
3
2

VCC = Pin 20
GND = Pin 10

CONNECTION DIAGRAM

TA=B

Please note that this diagram is provided only for the understanding
of logic operations and should not be used to estimate propagation
delays.

J Suffix - Case 732-03 (Ceramic)
N Suffix -

FAST AND LS TTL DATA

4-145

Case 738-01 (plastic)

MC54F174F521

GUARANTEED OPERATING RANGES
SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

54,74

4.50

5.0

5.50

V

54
74

-55
0

25
25

125
70

°C

VCC

Supply Voltage

TA

Operating Ambient Temperature Range

IOH

Output Current - High

54,74

·1.0

mA

10L

Output Current -

54,74

20

mA

Low

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

MIN

LIMITS
TYP

MAX

UNITS

TEST CONDITIONS

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

0.8

V

Guaranteed Input LOW Voltage

VIK

Input Clamp Diode Voltage

-1.2

V

IIN=-18mA

VCC=MIN

IOH=-1.0mA
10H =-1.0 mA

VCC=4.75V

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

V

2.0

I ~4,!4

2.5

3.4

V

I

2.7

3.4

V

74

VCC=.4.50V

0.5

V

IOL=20 mA

VCC=MIN

IIH

Input HIGH Current

20
100

p.A
p.A

VIN =2.7V
VIN =7.0V

VCC=MAX

IlL

Input LOW Current

-0.6

mA

VIN =0.5 V

V CC = MAX

lOS

Output Short Circuit
Current (Note 2)

-150

mA

VOUT=OV

VCC = MAX

mA

TA=B=Gnd

VCC=MAX

ICCH

0.35

Guaranteed Input HIGH Voltage

-60

Power Supply Current

ICCL

24

36

15.5

23

NOTES:
1. For conditions such as MIN or MAX, use the appropriate value specified under guaranteed operating ranges.
2. Not more than one output should be shorted at a time, nor for more than 1 second.

TRUTH TABLE
Output

Inputs
IA· B

A,S

OA· B

L
L
H
H

A =.8'
A#S
A = S'
A#S

L
H
H
H

H = HIGH Voltage Level
L = LOW Voltage Level
*Ao = BO, Al = Bl, A2 = B2, etc.

FAST AND LS TIL DATA

4·146

MC54F174F521

AC CHARACTERISTICS

SYMBOL

PARAMETER

54174F
TA=+25°e
Vee=+5.0V
eL = 50 pF
MIN
MAX
TYP

74F
54F
TA = -55 to +125°e TA - 0 to +70 o e
Vee = 5.0 V ±10% Vee = 5.0V ±10% UNITS
eL = 50 pF
eL = 50 pF
MIN
MAX
MIN
MAX

tpLH
tpHL

Propagation Delay
AnorBntoOA=B

2.5
3.0

6.5
6.5

10

io

2.5
3.0

15
12

2.5
3.0

11
11

ns

tPLH
tpHL

Propagation Delay

'iA = B to OA = B

2.5
3.5

4.5
5.0

6.5
9.0

2.5
3.5

8.5
10

2.5
3.5

7.5
10

ns

APPLICATIONS

Ripple Expansion

Parallel Expansion

FAST AND LS TTL DATA

4-147

®

MOTOROLA

MC54F533
MC74F533

OCTALTRAN8PARENTLATCH

(With 3-8tate Outputs)
DESCRIPTION - The MC54F174F533 consists of eight latches
with 3-state outputs for bus organized system applications. The flipflops appear transparentto the data when Latch Enable (LE) is HIGH.
When LE is LOW. the data that meets the setup times is latched.
Data appears on the bus when the Output Enable (OE) is LOW.
When OE is HIGH the bus output is in the high-impedance state. The
F533 is the same as the F373, except that the outputs are inverted.
For description and logic diagram please see the F373 data sheet.

OCTAL TRANSPARENT LATCH
(With 3-State Outputs)

FAST'" SCHOTTKY TTL

• Eight Latches in a Single Package
• 3-State Outputs for Bus Interfacing

CONNECTION DIAGRAM

LOGIC SYMBOL

3 4

7

8 131417 18

11

VCC =Pin 20
GND = Pin 10

2

5

6

9 12 151619

J Suffix -

Case 732-03
(Ceramic)

N Suffix -

Case 738-01
(Plastic)

GUARANTEED OPERATING RANGES
SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

54,74,

4.50

5.0

5.50

V

54
74

-55
0

25
25

125

70

°c

VCC

Supply Voltage

TA

Operating Ambient Temperature Range

IOH

Output Current -

High

54,74

-3.0

mA

IOL

Output Current -

Low

54, 74

24

mA

FAST AND LS TTL DATA

4-148

MC54F/74F533

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

MIN

LIMITS
TYP

UNITS

MAX

TEST CONDITIONS

VIH

Input HIGH Voltage

VIL

Input LOW Voltage

0.8

V

Guaranteed Input LOW Voltage

VIK

Input Clamp Diode Voltage

-1.2

V

IIN=-18mA

V
V
V
V

IOH =-1.0 mA
IOH =-3.0 mA
IOH =-3.0 mA
IOH =~3.0 mA

V

IOL= 24mA

VCC= MIN

2.0

54
54
74
74

V

2.5
2.4
2.5

3.4
3.3
3.3
3.3

Guaranteed Input HIGH Voltage
VCC=MIN

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

10ZH

Output OFF Current - HIGH

50

p.A

VOur=2.7V

VCC = MAX

10ZL

Output OFF Current -

-50

p.A

VOUT=0.5 V

VCC = MAX

IIH

Input HIGH Current

IlL

Input LOW Current

lOS

Output Short Circuit
Current (Note 2)

ICCZ

2.7

0.35
LOW

0.5

20

p.A

100

-60

Power Supply Current

41

mA

-150
61

VCC=4.75

VIN=2.7V
VCC = MAX

VIN =7.0V

-0.6

VCC =4.50V

VIN =0.5 V

Vee = MAX

mA

VOUT=OV

VCC=MAX

mA

OE = 4.5 V
Dn, LE = Gnd

VCC=MAX

NOTES:
1. For conditions such as MIN or MAX.. use the appropriate value specified under guaranteed operating ranges.
2. Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS

SYMBOL

PARAMETER

54174F
TA=+25°C
Vee = +5.0 V
CL = 50 pF
MIN
TYP
MAX

54F
74F
TA - -55 to +125°C TA - 0 to +70o C
Vce = 5.0 V ±10% Vee=5.0V±10%
CL = 50 pF
eL = 50 pF

UNITS

MIN

MAX

MIN

MAX

tPLH
tpHL

Propagation Delay
Dn toOn

4.0
3.0

6.9
5.2

9.0
7.0

4.0
3.0

12
9.0

4.0
3.0

10
8.0

ns

tpLH
tPHL

Propagation Delay
LE toOn

5.0
3.0

8.5
5.6

11
7.0

5.0
3.0

14
9.0

5.0
3.0

13
8.0

ns

2.0
2.0

11
7.5

ns

2.0
2.0

7.0
6.5

ns

tpZH
tpZL
tpHZ
tpLZ

Output Enable Time

2.0
2.0

7.7
5.1

10
6.5

2.0
2.0

12.5
9.0

Output Disable Time

2.0
2.0

4.7
4.1

6.0
5.5

2.0
2.0

8.5
7.5

AC CHARACTERISTICS

SYMBOL

PARAMETER

54/74F
TA = +25°C
VCC=+5.0V
MIN
TYP
MAX

54F
74F
TA = -55 to +125°e TA = 0 to +70 o e
Vce= 5.0 V±10% Vee = 5.0 V ±10%
MIN
MAX
MIN
MAX

UNITS

ts(H)
ts(L)

Setup Time, HIGH or LOW
Dn to LE

2.0
2.0

2.0
2.0

2.0
2.0

ns

th(H)
th(L)

Hold Time, HIGH or LOW
Dn to LE

3.0
3.0

3.0
3.0

3.0
3.0

ns

tw(H)

LE Pulse Width HIGH

6.0

6.0

6.0

ns

FAST AND LS TIL DATA

4-149

®

MOTOROLA

MCS4FS34
MC74FS34
OCTAL O-TYPE FLIP-FLOP

(With 3-State Outputs)

OCTAL O-TYPE FLIP-FLOP
(With 3-State Outputs)

DESCRIPTION - The MC54F174F534 isa high-speed,low-power
octal Ootype flip-flop featuring separate Ootype inputs for each flipflop and 3-state outputs for bus oriented applications. A buffered
Clock (CP) and Output Enable (OE) are common to all flip-flops. The
'F534 is the same as the 'F374 except that the outputs are inverted.

FASTTM SCHOTTKY TTL

• Edge-triggered D-Type Inputs
• Buffered Positive Edge-triggered Clock
• 3-State Outputs for Bus Oriented Applications
CONNECTION DIAGRAM

LOGIC SYMBOL
3

11

4

7

8 13 14 1718

CP

VCC = Pin 20
GND = Pin 10

2

5

6

9 12151619

J Suffix - Case 732-03 (Ceramicl
N Suffix - Case 738-01 (Plastic)

GUARANTEED OPERATING RANGES
SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

54, 74

4.50

5.0

5.50

V

54
74

-55
0

25
25

125
70

°c

VCC

Supply Voltage

TA

Operating Ambient Temperature Range

IOH

Output Current - High

54, 74

-3.0

rnA

IOL

Output Current - Low

54,74

24

rnA

FAST AND LS TTL DATA

4-150

MC54F174F534

LOGIC DIAGRAM

DO

05

06

CP~~~--~-+------~~----~~------'-~-----'~r-----'--r----~~r-----'

01

00

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.

FUNCTIONAL DESCRIPTION - The 'F534 consists of eight edge-triggered flip-flops with individual D-type inputs and
3-statetrue outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store
the state of their individual 0 inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock (CP)
transition. With the Output Enable(OE) LOW. the contents ofthe eight flip-flops are available althe outputs. When theOE is
HIGH. the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops.
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL
VIH

PARAMETER

MIN

Input HIGH Voltage

LIMITS
TYP

MAX

UNITS
V

2.0

TEST CONDITIONS
Guaranteed Input HIGH Voltage

Vil

Input lOW Voltage

0.8

V

Guaranteed Input lOW Voltage

VIK

Input Clamp Diode Voltage

-1.2

V

IIN=-18mA

V
V
V

2.5
2.4
2.5

74

'2.7

3.4
3.3
3.3

V
0.5

V

IOl=24 mA

VCC=MIN

Output OFF Current - HIGH

50

I'A

VOUT= 2.7V

VCC=MAX

Output OFF Current -

-50

I'A

VOUT=0.5 V

VCC=MAX

Output HIGH Voltage

VOL

Output lOW Voltage

10lH
lOll

3.3
0.35

lOW

20

Input HIGH Current

III

Input lOW Current

lOS

Output Short Circuit
Current (Note 2)

ICCl

Power Supply Current
(All Outputs OFF)

100

-60
55

I'A

mA
mA
mA
mA

VCC=MIN

10H =-1.0
10H =-3.0
IOH --3.0
10H --3.0

VOH

IIH

54
54
74

VIN =2.7V
VIN =7.0V

VCC=4.75V·

VCC = MAX

..{l.6

mA

VIN =0.5V

V CC=MAX

-150

mA

VOUT=OV

VCC=MAX

86

mA

On = Gnd
OE =4.5V

VCC=MAX

NOTES:
1. For conditions such as MIN or MAX, use the appropriate value specified under guaranteed operating ranges.
2. Not more than one output should be shorted at a time, nor for more than 1 second.

FAST AND LS TTL DATA

4-151

Vec =4.50V

MC54F174F534

AC CHARACTERISTICS

SYMBOL

PARAMETER

54174F
TA - +25°C
VCC=+5.0V
CL = 50 pF
MIN
TYP
MAX

74F
54F
TA - -55 to +125°C TA - 0 to +70 oC
VCC= 5.0 V±10% VCC = 5.0V ±10% UNITS
"CL = 50 p~-CL = 50 pF
MIN
MAX
MAX
MIN

'max

Maximum Clock Frequency

100

70

MHz

tPLH
tPHL

Propagation Delay
CPtoO n

4.0
4.0

6.5
6.5

8.5
8.5

4.0
4.0

10.5
11

4.0
4.0

10

tpZH
tpZL

Output Enable Time

2.0
2.0

9.0
5.8

11.5
7.5

2.0
2.0

14
10

2.0
2.0

12.5
8.5

tpHZ
tpLZ

Output Disable Time

2.0
2.0

5.3
4.3

7.0
5.5

2.0
2.0

8.0
7.5

2.0
2.0

8.0
6.5

60

10

ns

ns

AC OPERATING REQUIREMENTS

SYMBOL

PARAMETER

54174F
TA - +25°C
VCC= +5.0 V
TYP
MAX
MIN

74F
54F
TA - -55 to +125°C TA-Oto+70oC
VCC = 5.0V ±10% VCC=5.0V±10% UNITS
MIN
MAX
MIN
MAX

ts(Hl
ts(Ll

Setup Time, HIGH or LOW
On to CP

2.0
2.0

2.5
2.0

2.0
2.0

th(Hl
th (Ll

Hold Time, HIGH or LOW
On toCP

2.0
2.0

2.0
2.5

2.0
2.0

tw (Hl
twILl

CP Pulse Width
HIGH or LOW

5.0
5.0

7.0
6.0

7.0
6.0

FAST AND LS TTL DATA

4-152

ns

ns

MC74F29601
Am2960
Me74F2960-11
Am2960-1
Advance Information
ERROR DETECTION AND CORRECTION CIRCUIT

ERROR DETECTION
AND CORRECTION
CIRCUIT
ADVANCED LOW POWER SCHOTTKY

The MC74F2960 and MC74F2960-1 will be dual marked with the
AMD part numbers Am2960 and Am2960-1 to indicate plug-in compatibility. However, the device will be referred to as the MC74F2960
in the remainder of this specification. The MC74F2960-1 is the speed
selected version of MC74F2960 on the critical data paths and is a
plug-in replacement for MC74F2960.
DESCRIPTION - The MC74F2960 Error Detection and Correction
Unit (EDAC) contains the logic necessary to generate check bits on
a 16-bit data field according to a modified Hamming Code, and to
correct the data word when check bits are supplied. Operating on
data read from memory, the MC74F2960 will correct any single bit
error" and will detect all double and some triple bit errors. For 16bit words, 6 check bits are used. The MC74F2960 is expandable to
operate on 32-bit words (7 check bits) and 64-bit words (8 check
bits). In all configurations, the device makes the error syndrome
available on separate outputs for data logging.

CONNECTION DIAGRAM
Top View
CQn.RECT

PASS IHRU
OIAG MODE 1

DATA 15
DATA 14

DIAG MODE 0

DATA 13

CODE ID 2

DATA 12

CODE 10 1

lE IN

CODE 10 0

LE DIAG

GENERATE

CBS
es 0
es 5
es 4
es 3
Vee
es 2

DEBYTE 1

DATA 11
DATA 10
DATA 9
DATA 8
GROUND

DATA 7

The MC74F2960 also features two diagnostic modes, in which diagnostic data can be forced into portions of the chip to simplify
device testing and to execute system diagnostic functions. The
product will be supplied in a 48-lead DIP package.
*Double bit errors can also be corrected If at least one of the two errors is a hard error.
This requires extra processor cycles.

..
o
o
o
o
o

PIN AND FUNCTIONALLY COMPATIBLE WITH THE Am2960
BOOSTS MEMORY RELIABILITY
EXPANDABLE TO 64-BIT DATA WORDS
BUILT-IN DIAGNOSTICS PERMITS SOFTWARE SYSTEM CHECK
SEPARATE BYTE CONTROLS FACILITATE BYTE OPERATIONS
COMPATIBLE WITH MC68000 AND OTHER PROCESSORS
16-BIT TIMING IWORST CASE) FOR THE MC74F2960-1
CHECK BIT GENERATION - 28 ns
SINGLE ERROR DETECTION - 25 ns
SINGLE ERROR CORRECTION - 52 ns

FAST AND LS TTL DATA

4-153

DATA 6

CS I

DATA 5

E'R'R5R
DE SC

DATA 4
OEBYTE 0

lE OUT

SC 0

DATA 3

SC 5

DATA 2

SC 3

DATA 1

SC 2

DATA 0

SC4

SCI

se6

~-----'--

J SuffiX - Case 740·02 (CeramIc)

II

MC74F2960/Am2960. MC74F2960-1/Am2960-1

FIGURE 1 LEOUT

OfSyrEO

BLOCK DIAGRAM

D>------,

D .......- - - - ,

~C>~----~~~------------------------,
ICHECKBITS)

OATAo-7 1i:::1I7't-...,~

DATA
OUTPUT
LATCH
BYTE 0

1S:!f'iLt-t'"IH

OUTPUT
LATCH
BTYE 1

OATA

DATAe-16

LEIN

C>--t-I---'

LEDIAG

C>-----~

CODe ID

DIAG MOOE

CORREC·
TION
LOGIC

MUX

L-_ _Q

iSEsc

t---c>

ERROR

t---c>

MULl ERROR

ERROR
DETECTION

D-lf----t
D0-.4f----t

D>----I
GENEAAT'E D>------I
CORRECT D>----I

PASS niRU

TABLE 1. MAXIMUM RATINGS
Symbol

value

Unit

Supply Voltage

Rating

Vee

-0.5 to +7.0

Input Voltage (Except DATA ()'15)

Vin

-0.5 to +7.0

Input Voltage (DATAQ.15)

Vin

-0.5 to +5.5

V
V
V

Storage Temperature Range

Tstg

-55 to +150

TJ

150

Junction Temperature

°e
°e

TABLE 2. THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance (MAX)

TABLE 3. GUARANTEED OPERATING RANGES

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

4.75

5.0

5.25

V

0

25

70

°c

High

-O.B

mA

Low

B.O

mA

VCC

Supply Voltage

TA

Operating Ambient Temperature Range

IOH

Output Current -

IOL

Output Current -

FAST AND LS TIL DATA

4-154

MC74F2960/Am2960

0

MC74F2960-1/Am2960-1

TABLE 4. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
SYMBOL

PARAMETER

MIN

VIH

Input HIGH Voltage

(1)

VIL

Input LOW Voltage

(1)

VIK

Input Clamp Diode Voltage

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

10ZH

Output Off
Current· HIGH

IOZL

IIH

LIMITS
TYP

V

Guaranteed Input LOW Voltage
VCC = MIN, liN = -18 rnA

V

VCC = MIN, IOH = -0.8 rnA

0.5

V

VCC = MIN, IOL = 8.0 rnA

70

flA
flA
flA

-50

flA

DATAO-15

70

flA

OTHERS

50

flA

SCO-6

Input High
Current

V
V

50

DATAO_15

Output Off
Current· LOW

0.8

-410

SCO-6

ALL

Guaranteed Input HIGH Voltage

-1.5
2.7

DATAO-15

TEST CONDITIONS

UNITS

MAX

2.0

VCC = MAX, VOUT = 2.4 V

VCC = MAX, VOUT = 0.5 V

VCC = MAX, VIN = 2.7 V

1.0

rnA

DATAO-15

-410

flA

OTHERS

-360

flA

-85

rnA

VCC = MAX, Va = 0 V

400

rnA

VCC = MAX

IlL

Input Low
Current

lOS

Short CircUit Current (2)

Icc

Power Supply Current

-25

VCC = MAX, VIN = 5.5 V
VCC = MAX, VIN = 0.5 V

(1) These Input levels provide zero noise immunity and should be tested only in a static, noise·free environment.
(2) Not more than one output should be shorted at a time.

FIGURE 2 - AC TEST FIXTURE

Vcc
tPZHL

J A i l Other
TABLE 5. TEST OUTPUT LOADS
Pin

Pin label
00-0 15
24-30
Sen-SCB
32
ERROR
33
MULT ERROR

Rl

R2

lAI'Other

FAST AND LS TIL DATA

4-155

R,

R2

430 !l
430 !l
470n
470n

1 k!l
1 k!l
3kn
3 k!l

MC74F2960/Am2960. MC74F2960-1/Am2960-1

TABLE 6. AC CHARACTERISTICS (MAXIMUM LIMITS)

SYMBOL

VCC = 5.0 V ± 5%; TA = 0 to

PARAMETER

~ut

From
Input
tpLH, tpHL

tpZH,

tpLZ'*

ERROR

DATAO_15

SCO-6

50 pF; UNITS = ns'"

MULT ERROR

MC74F
2960

MC74F
2960-1

MC74F
2960

MC74F
2960-1

MC74F
2960

MC74F
2960-1

MC74F
2960

MC74F
2960-1

DATAo-15

32

28

65"

52'

32

25

50

50

CBO-6
(CODE ID2-0 000, 011)

28

23

56

50

29

23

47

47

CBO-6
(CODE ID2_0010, 100, 101, 110, 111)

28

28

45

34

29

29

34

34

GENERATE

35

35

63

63

36

36

55

55

CORRECT
(Not Internal Control Mode)

-

-

45

45

-

-

-

-

DIAG MODEO_l
(Not Internal Control Mode)

50

50

78

78

59

59

75

75

PASSTHRU
(Not Internal Control Mode)

36

36

44

44

29

29

46

46

CODE IDO-2

61

61

90

90

60

60

80

80

LE IN
(From latched to transparent)

39

39

72"

72"

39

39

59

59

LEOUT
(From latched to transparent)

-

-

31

31

-

-

-

-

LE DIAG
(From latched to transparent;
Not Internal Control Mode)

45

45

78

78

45

45

65

65

Internal Control Mode:
LE DIAG
(From latched to transparent)

67

67

96

96

66

66

86

86

Internal Control Mode:
DATAO-15
(Via Diagnostic Latch)

67

67

96

96

66

66

86

86

OE BYTE 1

-

-

30

30

-

-

-

-

OE SC

30

30

-

-

-

-

-

-

OE BYTE 0,
OE BYTE 1

-

-

30

30

-

-

-

-

OESC

30

30

-

-

-

-

-

-

Propagation Delay

Output Enable Time

tpZL**

tpHZ,

+ 70'C; CL =

Output Disable Time

OE BYTE 0,

·Data In or LE In to Correct Data Out measurement requires timing as shown in Figure 3.
"CL for tpZH, tpZL, tpHZ and tpLZ ~ 5.0 pF
***Inputs switching between OV and 3V at 1V/ns, measurements made at 1.5V. All outputs have maximum DC load.

FAST AND LS TTL DATA

4-156

MC74F2960/Am2960. MC74F2960·1/Am2960·1

TABLE 7. AC OPERATING REQUIREMENTS (MINIMUM LIMITS)

SYMBOL

TA = 0 to +70·C
VCC = 5.0 V ±5%

PARAMETER

UNITS

MC74F2960

MC74F2960·1

DATAO-15 10 LE IN

6
7

6
7

ns

5
6

5
6

ns
ns

Isu
Ih

Selup Time
Hold Time

Isu
Ih

Selup Time
Hold Time

CBO-6 10 LE IN

Isu
Ih

Selup Time
Hold Time

DATAO_1510 LE OUT

44
5

34
5

Isu
Ih

Selup Time
Hold Time

CBO-6 10 LE OUT
(Code ID 000, all)

35
0

35

Isu
Ih

Selup Time
Hold Time

CBO-6 10 LE OUT
(Code ID 010,100,101,110,111)

27

27
0

Isu
Ih

Selup Time
Hold Time

GENERATE 10 LE OUT

42
0

42

Isu
Ih

Selup Time
Hold Time

CORRECT 10 LE OUT

26
1

26
I

Isu
Ih

Selup Time
Hold Time

DIAG MODEO_I, 10 LE OUT

69
0

69

Isu
Ih

Selup Time
Hold Time

PASS THRU 10 LE OUT

26
0

26

Isu
Ih

Selup Time
Hold Time

CODE IDO-2' 10 LE OUT

81
0

81

Isu
Ih

Selup Time
Hold Time

LE IN 10 LE OUT

51
5

51
5

ns

Isu
Ih

Selup Time
Hold Time

DATAO_1510 LE DIAG

6
8

6
8

ns

Iw

Minimum Pulse
Widlh, High or Low

LE IN, LE OUT, or LE DIAG

15

15

ns

FIGURE 3 -

a

.XXXX .XxXXXX.
lXXXXX .X)(XX

V

\.XNI'N{

~

/xxxxxr~

Setup Time

\
~
DATA to lE IN
Hold Time

OE BYTE 0 & I

a
a
a

CORRECT
DATA
OUTPUT

DATAINt0
CORRECT DATA OUT

DATA to lE IN
LE IN

a

TIMING REQUIRED for DATA IN (or LE IN) to CORRECTED DATA OUT
VALID
INPUT
DATA

DATAQ.15

a

~
~

FAST AND lS TTL DATA

4-157

)

ns
ns
ns
ns
ns
ns
ns

MC14F2960/Am2960. MC14F2960-1/Am2960-1

PIN DEFINITIONS
DATAO-15
16 bidirectional data lines. They provide input to the Data
Input Latch and Diagnostic Latch, and receive output from
the Data Output Latch, DATAO is the least significant bit;
DATA15 the most significant.
CBO-6
Seven Check Bit input lines. The check bit lines are
used to input check bits for error detection. They are also
used to input syndrome bits for error correction in 32 and
64-bit configurations.
LE IN
Latch Enable - Data Input Latch. Controls latching of
the input data. When HIGH the Data Input Latch and Check
Bit Input Latch follow the input data and input check bits.
When LOW, the Data Input Latch and Check Bit Input Latch
are latched to their previous state.
GENERATE
Generate Check Bits input. When this input is LOW the
EDAC is in the Check Bit Generate Mode. When HIGH the
EDAC is in the Detect Mode or Correct Mode.
In the Generate Mode the circuit generates the check
bits or partial check bits specific to the data in the Data
Input Latch. The generated check bits are placed on the SC
outputs.
In the Detect or Correct Modes the EDAC detects single
and multiple errors, and generates syndrome bits based
upon the contents of the Data Input Latch and Check Bit
Input Latch. In Correct Mode, single-bit errors are also
automatically corrected - corrected data is placed at the
inputs of the Data Output Latch. The syndrome result is
placed on the SC outputs and indicates in a coded form
the number of errors and the bit-in-error.
SCO-6
Syndrome/Check Bit outputs. These seven lines hold
the check/partial-check bits when the EDAC is in Generate Mode, and will hold the syndrome/partial syndrome
bits when the device is in Detect or Correct Modes. These
are 3-state outputs.

(In a 64-bit configuration, MULT ERROR must be externally
implemented.)
CORRECT
Correct input. When HIGH this signal allows the correction network to correct any single-bit error in the Data
Input Latch (by complementing the bit-in-error) before
putting it onto the Data Output Latch. When LOW the
EDAC will drive data directly from the Data Input Latch to
the Data Output Latch without correction.
LE OUT
Latch Enable - Data Output Latch. Controls the latching of the Data Output Latch. When LOW the Data Output
Latch is latched to its previous state. When HIGH the Data
Output Latch follows the output of the Data Input Latch as
modified by the correction logic network. In Correct Mode,
single-bit errors are corrected by the network before loading into the Data Output Latch. In Detect Mode, the contents of the Data Input Latch are passed through the
correction network unchanged into the Data Output Latch.
The inputs to the Data Output Latch are unspecified if the
EDAC is in Generate Mode.
OE BYTE 0, OE BYTE 1
Output Enable - Bytes
and 1, Data Output Latch.
These lines control the 3-state outputs for each of the
two bytes of the Data Output Latch. When LOW these lines
enable the Data Output Latch and when HIGH these lines
force the Data Output Latch into the high impedance state.
The two enable lines can be separately activated to enable
only one byte of the Data Output Latch at a time.

a

PASS THRU
Pass Thru input. This line when HIGH forces the contents of the Check Bit Input Latch onto the Syndrome/
Check Bit outputs (SCO-6) and the unmodified contents of
the Data Input Latch onto the inputs of the Data Output
Latch.

OE SC
Output Enable - Syndrome/Check Bits. When LOW, the
3-state output lines SCO-6 are enabled. When HIGH, the
SC outputs are in the high impedance state.
ERROR
Error Detected output. When the EDAC is in Detect or
Correct Mode, this output will go LOW if one or more syndrome bits are asserted, meaning there are one or more bit
errors in the .data or check bits. If no syndrome bits are
asserted, there are no errors detected and the output will
be HIGH. In Generate Mode, ERROR is forced HIGH. (In a
64-bit configuration, ERROR must be externally implemented.)
MULT ERROR
MUltiple Errors Detected output. When the EDAC is in
Detect or Correct Mode, this output if LOW indicates that
there are two or more bit errors that have been detected. If
HIGH this indicates that either one or no errors have been
detected. In Generate mode, MULT ERROR is forced HIGH.

DIAG MODEO-1
Diagnostic Mode Select. These two lines control the
initialization and diagnostic operation of the EDAC.
CODE 100-2
Code Identification inputs. These three bits identify the
size of the total data word to be processed and which 16bit slice of larger data words a particular EDAC is processing. The three allowable data word sizes are 16, 32
and 64-bits and their respective modified Hamming codes
are designated 16122, 32/39 and 64172. Special CODE
10 input 001 (102, lOt. 100) is also used to instruct the
EDAC that the signals CODE 100-2, DIAG MODEO_l,
CORRECT and PASS THRU are to be taken from the Diagnostic Latch, rather than from the input control lines.
LE DIAG
Latch Enable - Diagnostic Latch. When HIGH the Diagnostic Latch follows the 16-bit data on the input lines.
When LOW the outputs of the Diagnostic Latch are latched
to their previous states. The Diagnostic Latch holds diagnostic check bits, and internal control signals for CODE
100-2, DIAG MODEO-1, CORRECT and PASS THRU.

FAST AND LS TTL DATA
4-158

MC74F2960/Am2960

0

MC74F2960-1/Am2960-1

FUNCTIONAL DESCRIPTION
The MC74F2960 contains the necessary logic to generate check bits on a 16-bit data field according to a modified Hamming code. This code allows the EDAC to 1) be
cascaded, 2) detect all double bit errors, 3) detect RAM
failure (all 1 or 0 data).
The EDAC may be configured to work on data words
from 8- to 64-bits in length. When cascaded for word
lengths in excess of 16 bits, each EDAC must know which
bits it is processing. This is done with Code ID inputs as
shown in Table8. The Internal Control Mode is described
later.

CORRECT MODE
In this mode, the EDAC functions the same as in Detect
Mode except that the correction network is allowed to correct (complement) any single-bit error of the Data Input
Latch before putting it onto the inputs of the Data Output
Latch. If multiple errors are detected, the output of the
correction network is unspecified.
If the single-bit error is a check bit there is no automatic
correction. If check bit correction is desired, this can be
done by placing the device in GENERATE MODE to produce a correct check bit sequence forthe data in the Data
Input Latch.
DIAGNOSTIC GENERATE
DIAGNOSTIC DETECT
DIAGNOSTIC CORRECT
These are special diagnostic modes where check bits
loaded into the Diagnostic Latch are substituted for either
normal check bit inputs or outputs.

MODE SELECTION
The device control lines are GENERATE, CORRECT,
PASS THRU, DIAG MODEO_1 and CODE 100-2. Table 9
lists the MC74F2960 modes of operation. The data
flow for each of these modes is shown in Figures 4
through 7.
PASS THRU MODE
In this mode, the unmodified contents of the Data Input
Latch are placed on the inputs of the Data Output Latch
and the contents of the Check Bit Input Latch are placed
on the SC outputs. ERROR and MULT ERROR are forced
HIGH in this mode.

INITIALIZE
The inputs of the Data Output Latch are forced to zeroes.
The check bit outputs (SC) are generated to correspond to
the all-zero data. ERROR and MULT ERROR are forced
HIGH in the initialize Mode.
Initialize Mode IS useful after power up when RAM contents are random. The EDAC may be placed in initialize
mode and ItS' outputs written into all memory locations
by the processor.

GENERATE MODE
In this mode check bits will be generated that correspond to the contents of the Data Input Latch. The check
bits generated are placed on the SC outputs.

INTERNAL CONTROL MODE
When in the internal control mode, the EDAC takes the
CODE IDO-2, DIAG MODEO_1, CORRECT and PASS THRU

DETECT MODE
In this mode the device examines the contents of the
Data Input Latch against the Check Bit Input Latch, and
will detect all single-bit errors, all double-bit errors and
some triple-bit errors. If one or more errors are detected,
ERROR goes LOW. If two or more errors are detected,
MULT ERROR goes LOW. Both error indicators are HIGH
if there are no errors.
Also available on the SC outputs are the syndrome bits
generated by the error detection step. The syndrome bits
may be decoded to determine if a bit error was detected
and, for single-bit errors, which of the data or check bits
is in error.
In Detect Mode, the contents of the Data Input Latch
are driven directly to the inputs of the Data Output Latch
without correction.

control signals from the Internal Diagnostic Latch rather
than from the external input lines or Memory Controller.
TABLE S. HAMMING CODE AND
SLICE IDENTIFICATION
CODE CODE CODE
ID2
IDO Hamming Code and Slice Selected
1D1
a
a
a
a
1
1
1
1

a
a
1
1
0
a
1
1

a
1
0
1
a
1
a
1

Code 16/22
Internal Control Mode

Code
Code
Code
Code
Code
Code

32139. Bytes a and
32/39. Bytes 2 and
64172. Bytes a and
64172, Bytes 2 and
64/72, Bytes 4 and
64/72. Bytes 6 and

TABLE 9. F2960 MODES OF OPERATION

OPERATING MODE'
PASSTHRU
GENERATE
DETECT
CORRECT
DIAGNOSTIC GENERATE
DIAGNOSTIC DETECT
DIAGNOSTIC CORRECT
INITIALIZE

DIAG MODEl
X
X
0
0
0
1
1
1

DIAG MODEO
X
0
X
X
1
0
0
1

CONTROL INPUTS'
GENERATE
PASSTHRU
1
X
a
0
0
1
1
0
0
0
0
1
0
1
0
X

·The internal control mode overrides controlmputs (See Text).

FAST AND LS TTL DATA

4-159

CORRECT
X
X
0
1
X
0
1
X

1
3
1
3
5
7

MC74F2960/Am2960. MC74F2960-1/Am2960-1

FIGURE 4 - CHECK BIT GENERATION
LEOUT

c>-------,

OEBYTEO C>----~

C~6C~~--~r-r_--------------__,
{CHECKBITSI
DATAo-7

1i!l!!I'i'l-"",,~
CORRECT

LOGIC

OESC

1----1D
AOME

7

ERROR

ERROR
DETECTION

/---{::>MOi'i'"ERROR

LEOIAG

C>-----J

CODE 10

C>--i~--1

OIAG MODE

C>--ii<---1

GENERATE Iil---o&!
CORRECT

C>-----I

FIGURE 5 - ERROR DETECTION AND CORRECTION
C>------,
OEBYTEOC>-----,
LEQUT

CBO_S

C+r------j;-;I------------------,

(CI-IECKBITSI
DATAo.7

g::1I7'-1---1'~

DATA(I_1S

1<:::"';"1-1-1---1

OEBYTE 1

C>-HH--J

ERROR

LOGIC

<>Esc

COOEIQ C~f--~
DIAG MODE

c>---li<---1

PASSTHRU

C>-----I

GENERATE
CORRECT

~::==!j
C

FAST AND LS TTL DATA

4-160

MC74F2960/Am2960

8

MC74F2960-1/Am2960-1

FIGURE 6 -

DIAGNOSTIC CHECK BIT GENERATION

C------,

OEBYTEO

C>7'-r----j;-;i-----------------,

C"o·6
(CHECK BITS)

CORRECT
LOGIC

DATAa-1SI!:

LEOIAG

MULl ERROR

C------"

OIAGMODE

E:.->4--~,j

GENERAfE 6>--==!"=t
CORRECT D--~-i

I

FIGURE 7 -

LEOUT

II

DIAGNOSTIC DETECT AND CORRECT

C-------,

I

OEBYTEOC~-----,
CB0-6

C.;t..r------j,......,l------------------,

[CHECK BITS)
DATAo_7

1!:'*--f!'l

PASSTHRU

C---.-j

GENERATE

8>-~=~

CORRECT

C----\

FAST AND LS TTL DATA

4-161

II

MC74F2960/Am2960. MC74F2960-1/Am2960-1

CASCADING THE MC74F2960
The system configuration, as well as the specific function of various F2960 inputs and outputs, varies slightly
depending upon the width of the data word.
The system configuration for 16-bit, 32-bit and 64-bit
data words is shown in Figures 8, 9 and 10. In addition,
accompanying figures and tables indicate the memory
word format, diagnostic latch format, check bit encode,
syndrome decode and ac calculations for each configuration.
When cascading to 32- or 64-bit configurations, syndrome bits must be fed back to the check bit inputs to
correct an erroneous data word. Figure 9 and Table 18

illustrate the use of a 3-state buffer to control the multiplexing of check bits and syndrome bits into the EDAC(s).
Cascading to a 64-bit configuration requires additional
MSllogic to generate a portion of the Syndrome and also
the ERROR flag. The implementation shown in Figure 10
results in a different meaning for the MULT ERROR flag
than in other configurations. MULT ERROR is HIGH if no
errors or a l-bit error is detected, but it is also HIGH for
some 2-bit errors. In order to determine if an error is
correctable, a DOUBLE ERROR output indicates that 2 errors have been detected when HIGH. Otherwise DOUBLE
ERROR is Low.

16-BIT DATA WORD WIDTH

TABLE 10. 16-BIT DATA FORMAT

DATA

FIGURE 8 -

16-BIT CONFIGURATION

INPUT CHECK BITS
FOR 16-BIT CONFIGURATION

CHECK BITS

r,----------~,
BYTE 0

BYTE 1

CX

CO

Cl

C2

C4

DON,
C8 CARE

o

15

Uses Modified Hamming Code 16122
- 16 data bits
-

6 check bits

-

22 bits in total

CODE
ID

EDAC

000

S2/C2
S8/C8
~------~~------~'
SYNDROMEICHECK BIT OUTPUTS
FOR 16-BIT CONFIGURATION

TABLE 11. 16-BIT MODIFIED HAMMING CODE -

CHECK BIT ENCODE CHART

Generated

Participating
Data Bits

Check

Bits

Parity

CX

0

Even IXORI

CO

Even IXORI

X

Cl

Odd IXNORI

X

C2

Odd IXNORI

X

C4

Even IXORI

C8

Even IXORI
The check bit

IS

1

2

3

X

X

X

X

X

4

7

X

X

X
X

6

X
X

X
X

5

X

8

9

X

X

X
X

X

X

X

X

X

X
X

generated as either an XOR or XNOR of the eight data bits noted by an "X"

FAST AND LS TTL DATA

4-162

11

12

13

X
X

X

X

10

In

15

X
X

X

X

14

X

X
X

X

X

X

X

X

the table.

X

X

X

X

MC74F2960/Am2960

MC74F2960-1/Am2960-1

CIl

16-81T DATA WORD WIDTH (continued)
TABLE 13. DIAGNOSTIC LATCH LOADING Data Bit

Internal Function

0

Diagnostic Check Sit X

TABLE 12. SYNDROME DECODE TO BIT-IN-ERROR

SB
S4
S2

Syndrome

Bits

0
0
0

1
0
0

1
1
0

0
1
0

1
0
1

0
0
1

1
1
1

0
1
1

0

.

C8

C4

T

C2

T

T

M

1

Cl

T

T

15

T

13

7

T

1

0

CO

T

T

M

T

12

6

1

1

T

10

4

T

0

T

T

1

0

0

CX

T

T

14

T

11

5

1

0

1

T

9

3

T

M

T

1

1

0

T

8

2

T

1

1

1

1

M

T

T

M

T

SX

SO

51

0

0

0

0

0
0

*-

Diagnostic Check Bit 0
Diagnostic Check Sit 1

3

Diagnostic Check Bit 2

4

Diagnostic Check Bit 4

Don't Care

T

8

CODE IDO

M

9

CODE ID 1

T

10

CODE ID 2

T

M

11

DIAG MODEO

T

T

M

M

M

T

12

DIAGMODE 1

the location of the Single bit-in-error

--

Diagnostic Check Bit 8

6.7

T - two errors detected
M -

1
2

5

no errors detected

Number -

16-BIT FORMAT

13

CORRECT

14

PASS THRU

15

Don't Care

three or more errors detected

32-BIT DATA WORD WIDTH

TABLE 15. DIAGNOSTIC LATCH LOADING -

TABLE 14. SYNDROME DECODE TO BIT-IN-ERROR

Data Bit
0

516
58
S4

Syndrome
Bits

0
0
0

1
0
0

0
1
0

1
1
0

0
0
1

1
0
1

0
1
1

1
1
1

C16 C8

T

C4

T

T

30

1

Diagnostic Check Bit 0

2

Diagnostic Check Sit 1

3

Diagnostic Check Sit 2
Diagnostic Check Sit 4

T

5

Diagnostic Check Bit 8

15

T

6

Diagnostic Check Bit 16

T

T

M

7

Don't Care

T

2

M

T

8

Slice 0/1 - CODE ID 0

T

22

T

T

M

T

20

T

T

M

M

T

M

M

T

T

M

T

M

14

M

11

T

21

T

T

M

9

T

19

1

M

T

T

29

0

T

M

8

T

SO

51

52

0

0

0

0

0

0

0

1

C2

T

T

27

T

5

M

0

0

1

0

Cl

T

T

25

T

3

0

0

1

1

T

M

13

T

23

0

1

0

0

CO

T

T

24

0

1

0

1

T

1

12

0

1

1

0

T

M

10

0

1

1

1

16

T

T

1

0

0

0

CX

T

1

0

0

1

T

1

0

1

0

1

0

1

1

1

0

9

Shce 0/1 - CODE ID 1

10

Shce 0/1 - CODE ID 2

T

11

Slice 0/1 - DIAG MODE 0

T

M

12

Shce 0/1 - DIAG MODE 1

T

T

31

13

Shce 0/1 - CORRECT

T

7

M

T

14

Slice 0/1 -

18

T

T

M
T

15

Don't Care

1

1

0

1

17

T

T

28

T

6

M

1

1

1

0

M

T

T

26

T

4

M

T

1

1

1

1

T

0

M

T

M

T

T

M

* - no errors detected
the location of the smgle bit-in-error

T - two errors detected
M -

Internal Function

Diagnostic Check Bit X

4

SX

Number -

32-BIT FORMAT

three or more errors detected

FAST AND LS TTL DATA
4-163

16·23

PASS THRU

Don't Care

24

Slice 2/3 - CODE ID 0

25

Slice 2/3 - CODE ID 1

26

Shce 2/3 - CODE ID 2

27

Slice 2/3 - DIAG MODE 0

28

Shce 2/3 -

29

Shce 2/3 - CORRECT

30

Shce 2/3 - PASS THRU

31

Don't Care

DIAG MODE 1

MC74F2960/Am2960 • MC74F2960-1/Am2960-1

32-BIT DATA WORD WIDTH (continued)
TABLE 15. 32-BIT DATA FORMAT
CHECK B'TS

DATA
BYTE 3

31

BYTE 2

24 23

BYTE 1

BYTE 0

o

8 7

16 15

Uses Modified Hamming Code 32/39
- 32 data bits
-

7 check bits

-

39 bits in total

FIGURE 9 INPUT DATA

32-BIT CONFIGURAT'ON

INPUT CHECK BITS

...'------------,

,,----~----~\r'-----------DAlCA16.31 DATAo_15

CX

co

C,

C,2

C,

C,8

F244

I~I

DATA

CBo

CB,

CB2

CB3

CB,

CBS

C8s
OESC

EOAC
BYTES DANe 1

~

CODE
f--010
ID

SCo

SC,

SC2

SC3

SC,

SCs

CBo

C8,

C82

CB3

CB,

CBS

SCs

'-----y
DATA

CBS
OESC

EDAC*
BYTES 2 AND 3
CODE __ 0"
ID

MULl
ERROR

ERROR

--ERROR MULl

SCo

SC,

SC2

SX/CX SOICO S1/C1

ERROR,

SC3

SC,

521C2
~

S4/C4 S8/C8 516/C16

SCs

SCs

~

OUTPUT SYNDROME/CHECK BITS

"Check Bit Latch is Forced Transparent in this
Code ID Combination for this Slice.

FAST AND LS TTL DATA

4-164

DE SC

c;s

......

MC74F2960/Am2960

II)

MC74F2960-1/Am2960-1

32-BIT DATA WORD WIDTH (continued)
TABLE 16. 32·BIT MODIFIED HAMMING CODE Generated
Check
Bits

Parity

0

CX

Even (XOR)

X

CHECI( BIT ENCODE CHART
Participating Data Bits

CO

Even (XOR)

X

Cl

Odd (XNOR)

X

C2

OddlXNORI

X

C4

Even IXORI

C8

Even IXORI

C16

Even IXORI

1
X

2

3

X
X

6

7

8

9

X

X

X

X

X

X

X

4

X

X
X

X

5

X

X

X

X

X

X

X

X

X

X

X

X

16

17

18

19

20

21

X

X

X

X

X

X

CX

Even IXORI

CO

Even IXORI

X

Cl

OddlXNORI

X

C2

OddIXNOR)

X

C4

Even IXOR)

C8

Even IXORI

X

X

C16

Even IXORI

X

X

X
X

23

X

X

X
X

22

24

25

X
X

X

X
X

X

X

X

X

X

X

X

32·Bit

Propagation Delay
From

DATA
DATA IN
DATA

Delay Calculation

To

Check Bns

IDATA to SCI + (CB to SC. CODE 10 0111

Out

IDATA to SCI + ICB to SC. CODE 100111 +
ICB to DATA. CODE 100101

Corrected

DATA OUT
Syndromes

Out

IDATA to SCI + ICB to SC. CODE 10 0111

DATA

ERROR for
32 Bits

IDATA to SCI + ICB to ERROR.
CODE 10011)

DATA

MULT ERROR for
for 32 Bits

IDATA to SCI + ICB to MULT ERROR.
CODE 100111

64·BIT DATA WORD WIDTH
TABLE 18. 64-BIT DATA FORMAT

Uses Modified Hamming Code 64172
64 data bits

-

72 bits In total

15

X

X

X

X

X
X

X

X

X

X

X

X

X

26

27

30

31

Participating Data Bits

TABLE 17. KEY AC CALCULATIONS FOR THE 32·BIT CONFIGURATION

8 check bits

14

X

Parity

-

13

X

X

X

Generated
Check
Bits

-

12
X

X
X

X

11
X

X
X

X

10

FAST AND LS TTL DATA

4-165

28

29

X

X

X

X

X

X
X

X

X
X

X

X
X

X

X

X

X

X

X

X

X

X

X

X

X

X

II

MC74F2960/Am2960. MC74F2960-1/Am2960-1

64-BIT DATA WORD WIDTH (continued)

TABLE 19. 64-BIT MODIFIED HAMMING CODE Generated
Check
Bits

CHECK BIT ENCODE CHART

Participating Data Bits
Parity

0

CX

Even (XOA)

cr:

Even (XOA)

X

C1

Odd (XNOA)

X

C2

Odd (XNOA)

X

1

2

3

X

X

X

X

X

4

5

6

X
X

7

X
X

X

X

X

X

X

X

X

X

Even (XOA)
Even (XOA)

C16

Even (XOA)

X

X

X

X

X

X

X

X

C32

Even (XOA)

X

X

X

X

X

X

X

X

16

17

18

19

20

21

X

X

X

X

X

Generated
Check
8its

X

X

10

12

13

14

15

X

X
X

X

11
X

X

C4

X

9

X

CB

X

8
X

X

X

X

X

X

X

X
X

X

X

X

X

X

X

X

26

27

2B

29

30

31

X

Participating Data Bits
Parity

CX

Even (XOA)

CO

Even (XOA)

X

C1

Odd (XNOA)

X

C2

Odd (XNOA)

X

X
X

24

25

X

X

X

X
X

X

X

X

X

X

X

X

X
X

X

X

X
X

X

X

X

C4

Even (XOAI

X

X

C8

Even (XOA)

X

X

X

X

X

X

X

X

C16

Even (XOA)

X

X

X

X

X

X

X

X

C32

Even (XOA)

X

X

X

X

X

X

X

X

42

43

46

47

Generated
Check
Bits

X

Participating Data Bits
Parity

32

CX

Even (XOA)

X

CO

Even (XOA)

X

C1

Odd (XNOA)

X

C2

Odd (XNOA)

X

C4

Even (XOA)

C8

Even (XOA)

C16

Even (XOA)

C32

Even (XOA)

Generated
Check
Bits

X

23

X

X

X
X

22

X

33
X

34
X

X

36

38

39

X

X

X

X

X

X

X

X
X

37

X

X
X

X

35

X
X

40
X

X
X

X

X

X

X

X

X

X

41

X

44

45

X

X

X

X

X

X
X

X

X
X

X

X
X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

58

59

62

63

X

Participating Data Bits
Parity

48

CX

Even (XOA)

X

,CO
C1
C2
C4
C8
C16
C32

Even (XOA)

X

Odd (XNOA)

X

Odd (XNOA)

X

49 50 51
X

X
X

52

54

55

X

X

X

X

X

X

X

Even (XOA)

X

X

53

X

X
X

X

X

X

X

X

Even (XOA)
X

X

X

X

X

X

X

57

X

Even (XOA)
Even (XOA)

56

X

60

61

X

X

X

X

X

X
X

X

X
X

X

X
X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

The check bit is generated as either an XOR or XNOR of the 32 data bits noted by an "X" in the table.

FAST AND LS TTL DATA

4-166

s:

l;2

UI::~C

063-4B

a>

~~IO;O

D31-16

C7

f'

CD

::::j

16

16

16

16

r<

~

D47-32

~

>----]

"f

~6

0

'-f

»~

'-f

~
0

r<
r<

::c

~

:t=L-r

CBG CBS CB4 CB3 CB2 CSl CBO

OE SC

ME

EDAC
BYTES 6 AND 7

SC6 SCs SC4 SC3 sez se, sea

0
~

I

0

CBB CBS CB4 C83 CB2 CB, CBO

-r

OE SC

EDAC
BYTES4AND 5

SCe SCs SC4 SC3 se2 se, sea

CBe CBS CB4 CB3 CB2 CS, C80

0

-r OE

EDAC

SC

BYTES 2 AND 3

SCe SCs SC4 SC3 se2 se, sea

0

CBe CBS CB4 CB3 CB2 C8, CBO

l-r

OE SC

a
-i

0

::z:
0-

EDAC
BYTES 0 AND 1

SCe SCs SC4 SC3 se2 Se,

0

~.

"c:
"

sea

S
"T1

Gi

~

(I)

CD

c

i>
3
N

(I)

CD

c

G

S

n
.........

~

(I)

CD

...
~

c

i>

»"T1
C/l

m

N

»z

'"f'

r

0

MULl ERROR

:0

~

0

I

--I

f'

0

(J)

C/l

"

n
.........

tIl

:::;

~

--I
--I

~

C"l
0

r

0

~

'-------l

1

»

:l::lJ;

~

~

YS4/C4

VC4

S8/C8

1XOR\J

_YsB/CB

1

~lJ;

~

~

521C2

52/C2

w

1

516/C16

Ys'6/C'6

NOR9

51/C1

~U

~
532/(32

2

"T1

w

Gi

~

I

532/C32

SOICO

:0

~

0
2

cx

so/co

1
51/C1

c

SX/I

3

(I)

CD

...
~

MC74F2960/Am2960. MC74F2960-1/Am2960-1

64-BIT DATA WORD WIDTH (continued)
TABLE 20. SYNDROME DECODE TO BIT-IN-ERROR
Syndrome
Bits

532
516
SB
54

0
0
0
0

SX

SO

51

52

0

0

0

0

.

0

0

0

1

C2

1
0
0
0

0
1
0
0

C32 C16
T

1
1
0
0

0
0
1
0

1
0
1
0

0
1
1
0

1
1
1
0

0
0
0
1

1
0
0
1

0
1
0
1

1
1
0
1

0
0
1
1

1
0
1
1

0
1
1
1

1
1
1
1

T

C8

T

T

M

C4

T

T

M

T

46

62

T

T

M

T

43

59

T

T

53

37

T

M

T

T

M
31

0

0

1

0

Cl

T

T

M

T

41

57

T

T

51

35

T

15

T

T

0

0

1

1

T

M

M

T

13

T

T

29

23

T

T

7

T

M

M

T

0

1

0

0

CO

T

T

M

T

40

56

T

T

50

34

T

M

T

T

M

0

1

0

1

T

49

33

T

12

T

T

28

22

T

T

6

T

M

M

T

0

1

1

0

T

M

M

T

10

T

T

26

20

T

T

4

T

M

M

T

0

1

1

1

16

T

T

0

T

M

M

T

T

M

M

T

M

T

T

M

1

0

0

0

CX

T

T

M

T

M

M

T

T

M

M

T

14

T

T

30

1

0

0

1

T

M

M

T

11

T

T

27

21

T

T

5

T

M

M

T

1

0

1

0

T

M

M

T

9

T

T

25

19

T

T

3

T

47

63

T

1

0

1

1

M

T

T

M

T

45

61

T

T

55

39

T

M

T

T

M

1

1

0

0

T

M

M

T

8

T

T

24

18

T

T

2

T

M

M

T

1

1

0

1

17

T

T

1

T

44

60

T

T

54

38

T

M

T

T

M

1

1

1

0

M

T

T

M

T

42

58

T

T

52

36

T

M

T

T

M

1

1

1
1
T 4B 32
* - no errors detected
Number - the location of the single bit-in-error

T

M

T

T

M

M

T

T

M

T

M

M

T

T-

two errors detected

M -

three or more errors detected

TABLE 21. DIAGNOSTIC LATCH LOADING -

Data Bit

Data Bit

Internal Function

0

Diagnostic Check Bit X

54-BIT FORMAT

31

Internal Function
Don'teare
Don't Care

1

Diagnostic Check Bit 0

32-37

2

DIagnostic Check Bit 1

38

Diagnostic Check Bit 16

3

Diagnostic Check Bit 2

39

Don't Care

4

Diagnostic Check Bit 4

40

Slice 4/5 - CODE 10 0

5

Diagnostic Check Bit 8

41

Shce 4/5 - CODE 10 1

Don't Care

42

Slice 4/5 - CODE 10 2

8

Shce 011 - CODE 100

43

Shce 4/5 - DIAG MODE 0

9

Slice 011 - CODE 10 1

44

Slice 4/5 - DIAG MODE 1

10

Slice 011 - CODE 10 2

45

Slice 4/5 - CORRECT

11

Slice 011 - DIAG MODE 0

46

Slice 4/5 - PASS THRU

12

Slice 011 - DIAG MODE 1

47

Don't Care

13

Slice 011 - CORRECT

14

Shce 011 - PASS THRU

55

Diagnostic Check Bit 32

15

Don't Care

56

Slice 6/7 - CODE 10 0

6,7

48-54

Don't Care

Don't Care

57

Shce 617 - CODE 10 1

24

Shce 2/3 - CODE ID 0

58

Shce 617 - CODE 10 2

25

Slice 2/3 - CODE 10 1

59

Slice 617 - DlAG MODE 0

26

Shce 2/3 - CODE 10 2

60

Slice 6/7 -

27

Slice 2/3 - DIAG MODE 0

61

Slice 617 - CORRECT

16-23

DIAG MODE 1

28

Slice 2/3 - DIAG MODE 1

62

Slice 6/7 - PASS THRU

29

Shce 2/3 - CORRECT

63

Don't Care

30

Slice 2/3 - PASS THRU

FAST AND LS TTL DATA
4-168

MC74F2960/Am2960. MC74F2960-1/Am2960-1

64-BIT DATA WORD'WIDTH (continued)

TABLE 22. KEY AC CALCULATIONS FOR THE 64-BIT CONFIGURATION
64-Bit
Propagation Delay

From

Delay Calculation

To

DATA

Check Bits Out

(DATA to SC) + (XOR Delay)

DATA IN

Corrected DATA OUT

(DATA to SC) + (XOR Delay) + (Buffer Delay) +
(CB to DATA, CODE 10 1xx)
(DATA to SC) + (XOR Delay)

DATA

Syndromes

DATA

ERROR for 64 Bits

(DATA to SC) + (XOR Delay) + (NOR Delay)

DATA

MULT ERROR for 64 Bits

(DATA to SCI + (XOR Delay) + (Buffer Delay) +
(CB to MULT ERROR, CODE ID 1xx)

DATA

DOUBLE ERROR for 64 Bits

(DATA to SC) + (XOR Delay) + (XOR/NOR Delay)

FIGURE 11 -

~,o~

"I

l

i

)--

OUTLINE DIMENSION

II

I

--=I
______

~l____~~________~,.~

1---0

I

VfF
~

,

I

I

,

;

I

!

I

JI- o
INCHES
MILLIMETERS
MAX
MIN
MAX
DIM MIN
A 60.35 61.57 2.376 I 2.424
B 14.63 15.34
10.604
C
3.05
4.32
~
0
0.301 0.533
F
0.762 1.397
~
G
2.54 OSC

NOTES:
I. oiMENSIoN01S DATUM.
2. PoSTloNAL TOLERANCE FOR LEADS:

I-$-Ia

0.25100101@lrjli@1

3.rn
IS SEATING PLANE.
4. DIMENSION "L" TO CENTER OF LEADS

rmJ-

WHEN Fo RMEo PARALLEL.
5. DIMENSIONING AND TOLERANCING PER
ANSI YI4.5, 1973.

J
K
L
M
N

0.203 0.330
2.54
4.19
14.99 15.65
00
00
100
1.016 1.524 0.040
CASE 740-02

FAST AND LS TTL DATA

4-169

~
~
~
~
loa
0.060

MC74F2960/Am2960. MC74F2960-1/Am2960-1

FIGURE 12 -

CPU
MC68000
Am2900
8086
Z8000

Address

eE

HIGH PERFORMANCE COMPUTER MEMORY

F2968
Dynamic
Memory
Control

, 6K, 64K, or 256K
Dynamic Memory
Array

Control

0

u
~

0

.,E

:::;

..

!!l
0

F2969 (DMC/EDAC)
F2970 (DMC) Timing
Controllers

F2960
EDAC Unit

EDAC Control Bus

II

System Data Bus

FAST AND LS TTL DATA

4-170

WilC74f2968
MC14F296~

mfilC14!F2910
Product Preview
A NEW GENERATION OF MEMORY SUPPORT PRODUCTS
Motorola and Advanced Micro Devices have agreed
to cooperate on the development of the next generati,on
of the F2960 Family of Memory Support products. These
devices are designed to maximize the speed and minimize the cost of memory systems based on the new
generation of high performance 64K and 256K MOS
Dynamic RAMs (DRAMs).
The products included in this joint development and
alternate sourcing agreement are a Dynamic Memory
Controller (DMC), the F2968, and two Memory Timing
Controllers (MTC), the F2969 and F2970. These functions are partitioned such that address generation and
refresh are provided by the F2968. Memory timing and
control is achieved with either the F2969 or F2970. This
partitioning allows greater design flexibility and higher
system performance than would be possible by combining the DMC and MTC functions on a single chip. All
three devices will be fabricated using the high performance, oxide-isolated bipolar technologies with TIL
compatible I/O levels.
The Dynamic Memory Controller, F2968, will provide
complete address multiplexing, refreshing, and output
drive for up to 88 Dynamic Random Access Memories
(DRAMs). The F2968 will be packaged in a 48-pin DIP
and will interface with 16K, 64K, or 256K DRAMs.

The memory timing controller will be available in two
versions. The F2969, a 48-pin version, will provide all
control signals for both the F2968 Memory Controller
and the F2960 Error Detection and Correction circuit
(EDAC). The F2969 Timing Controller will support error
logging and also handle memory initialization, refresh
timing, and memory cycle arbitration. The general purpose microprocessor interface on the F2969 will facilitate its use with most microprocessors with minimal
external logiC. The MC68000 AMD/lntel iAPX86, and
AMD 2900 bit-slice and 29116 devices are notable examples. System timing for all memory functions is derived from an external delay line to provide maximum
performance and flexibility.
For systems not utilizing the F2960 Error Detection
and Correction circuit (EDAC), a second version of the
timing controller, the F2970, will be available without
(EDAC) interface/functions. The F2970 will save on Ie
cost and board space as it will be packaged in 24-pin,
300-mil wide DIP.
Sample quantities on the F2968, F2969, and the F2970
are expected in the fourth quarter 1983, with production
commencing early in 1984. F2960 samples are expected
in the third quarter of 1983.

HIGH PERFORMANCE COMPUTER MEMORY
Address

CPU
MC68000
Am2900
8086
Z8000

Address

g
"o

F2968
Dynamic
Memory
Control

16K,64K,or256K
Dynamic Memory
Array

Control

U

~

o·

.,E

::;

F2969 (DMClEDAC)
F2970 (DMC) Timing
Controllers

System Data Bus

FAST AND LS TTL DATA
4-171

F2960
EDAC Unit

II

II

MC74F2968

DYNAMIC MEMORY CONTROLLER
The MC74F2968 Dynamic Memory Controller is intended to be
used with today's high performance memory systems. It has two
9-bit address latches which allow the chip to be used with 16K,
64K, or 256K dynamic RAMs. A two-bit bank select latch for the
two 1!!9!!. order address bits is provided to select one each of the
four RAS and CAS outputs.
In the refresh mode, two counters cycle through the refresh
address. Only the ROW counter is used for refresh without scrubbing, generating up to 512 addresses to refresh a 512-cycle-refresh •
DRAM. The column counter is used only for refresh with scrub~. In this mode all RAS outputs are generated with only one
CAS output.

PIN ASSIGNMENT

....

cs

EASi

"'"
....

AIIo
ACo

CAs,
00

AR,

'OR,
""

...,

0,

AC,

0,
0,

AC,

'"

AR.

DE
Vee
Oo
Oo

• Provides Control for 16K, 64K, or 256K Dynamic RAM Systems
• Outputs Directly Drive Up to 88 DRAMs
• Highest Order Two Address Bits Select One of Four Banks of
RAMs
• Separate gs and CAS Lines for Each Bank of DRAM
o Supports Memory Scrubbing During Refresh

.".

• Supports Nibble Mode Access
• Separate Output Enable for Multi-Channel Access-to-Memory

"Co

AR,

o,

AC,
AR,

Oe

"Co

m;

AR,

...,

CAS,

""
.'"
"

CAS,
AASi
MCo

..

Me,

SEL,

• . Chip Select for Easy Expansion
• 48-Pin Dual In-Line Package

LOGIC DIAGRAM

CS--------------------------------------------,
MSEL------------------------------------------------,
r-________________
~~r-----

9
9

MUX

9

r+-Latch
Address -----."'\.,
ARo_a

0-

-----v,,'

Row
r - - :>Counter

r-

(LSB)

t
Address---"'
.... ,
ACo-a------.v/

COL

o t----

-_

r'2

1---++..

CAS
Decode 1--+-4

4

CAS n

Bank

'""" r- >Counter

Of"

SELO -------I
)

L E - - - - - If

MUX

Control 1----1__--.
______ - I -

0....--+---I

~ CL

(MSB)

SEL, -------i

Or-

CL

'""" r- :>Counter

9

SO-S3

r-_ _--,Ol

Latch

l,.

1,_

"2"

RAS
I'
Decode 1-----+-+-1
4

~L..C_L_--I

-ry.____-oc:Q=]