1986_National_Programmable_Logic_Design_Guide 1986 National Programmable Logic Design Guide
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~ ·National
~ Semiconductor
320100 Rev. 1
Programmable Logic
Design Guide
Programmable Logic
National Semiconductor CorporationSanta Clara, California
iii
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iv
PLD Selection Guide
tpD 1
Icc
Outputs
Reg.
Pg.
Family
Part No.
(max)
(max)
Comb.
20-Pin
Small
PAL
(Standard
Speed)
PALlOH8
PALlOL8
PALl2H6
PALl2L6
PALl4H4
PALl4L4
PALl6H2
PALl6L2
PALl6C1
35
35
35
35
35
35
35
35
35
90
90
90
90
90
90
90
90
90
8
8
6
6
4
4
2
2
1
276
20-Pin
Small
PAL
Series-A
PAL10H8A
PALlOL8A
PALl2H6A
PALl2L6A
PALl4H4A
PAL14L4A
PALl6H2A
PALl6L2A
PALl6c1A
25
25
25
25
25
25
25
25
30
90
90
90
90
90
90
90
90
90
8
8
6
6
4
4
2
2
1
279
20-Pin
Small
PAL
Series-A2
PALlOH8A2
PALlOL8A2
PALl2H6A2
PALl2L6A2
PALl4H4A2
PALl4L4A2
PALl6H2A2
PALl6L2A2
PALl6c1A2
35
35
35
35
35
35
35
35
40
45
45
45
45
45
45
45
45
45
8
8
6
6
4
4
2
2
1
284
20-Pin
Medium
PAL
(Standard)
PAL16L8
PALl6R4
PALl6R6
PALl6R8
35
35
35
35 2
180
180
180
180
8
4
2
TTL
v
277
4
6
8
vi
Programmable Logic Design Guide
tpD
. Family
Part No.
20-Pin
Medium
PAL
Series-A
1
Icc
Outputs
(max)
(max)
Comb.
PAL16L8A
PAL16R4A
PAL16R6A
PAL16R8A
25
25
25
25 2
180
180
180
180
8
4
2
20-Pin
Medium
PAL
Series-A2
PAL16L8A2
PAL16R4A2
PAL16R6A2
PAL16R8A2
35
35
35
35 2
90
90
90
90
8
4
2
20-Pin
Medium
PAL
Series-B
PAL16L8B
PAL16R4B
PAL16R6B
PAL16R8B
15
15
15
15 2
180
180
180
180
8
4
2
20-Pin
Medium
PAL
Series-B2
PAL16L8B2
PAL16R4B2
PAL 16R6B2
PAL16R8B2
25
25
25
25 2
90
100
100
100
8
4
2
20-Pin
Medium
PAL
Series-D*
PAL16L8D
PAL16R4D
PAL16R6D
PAL16R8D
10
10
10
102
180
180
180
180
8
4
2
24-Pin
Small
PAL
(Standard
Speed)
PAL12L10
PAL14L8
PAL16L6
PAL18L4
PAL20L2
PAL20C1
40
40
40
40
40
40
100
100
100
100
100
100
10
8
6
4
2
24-Pin
XOR
PAL
(Standard)
PAL20L10
PAL20X4
PAL20X8
PAL20X10
50
50
50
50 2
165
180
180
180
10
6
2
Reg.
Pg.
280
4
6
8
286
4
6
8
282
4
6
8
288
4
6
8
377
4
6
8
290
290
4
8
10
PLD Selection Guide
tpD
Family
Part No.
24-Pin
XOR
PAL
Series-A
1
Icc
Outputs
(max)
(max)
Comb.
PAL20LlOA
PAL20x4A
PAL20X8A
PAL20XI0A
30
30
30
30 2
165
180
180
180
10
6
2
24-Pin
Medium
PAL
Series-A
PAL20L8A
PAL20R4A
PAL20R6A
PAL20R8A
25
25
25
25 2
2lO
2lO
210
210
8
4
2
24-Pin
Medium
PAL
Series-B
PAL20L8B
PAL20R4B
PAL20R6B
PAL20R8B
15
15
15
15 2
2lO
210
2lO
2lO
8
4
2
24-Pin
Medium
PAL
Series-D*
PAL20L8D
PAL20R4D
PAL20R6D
PAL20R8D
10
10
lO
lO2
210
210
210
2lO
8
4
2
24-Pin
Polarity
PAL
Series-B*
PAL20P8B
PAL20RP4B
PAL20RP6B
PAL20RP8B
15
15
15
15 2
2lO
210
210
210
8
4
2
Register
Asynch.
PALl6RA8
PAL20RAI0
30
30
170
200
PLA87X153B
20
155
GALl6V8-15L
GALl6V8-20L
GALl6V8-25Q
GALl6V8-25L
GAL 16V8-30Q3
GALl6V8-30L3
GALl6V8-35Q
15
20
25
25
30
30
35
90
90
45
90
50
90
45
20-Pin
PLA
vii
Reg.
Pg.
341
4
8
10
292
4
6
8
353
4
6
8
393
4
6
8
365
4
6
8
8
10
10
409
417
335
E2CMOS
20-Pin
Generic
Array
Logic
*Preliminary
8
8
8
8
8
8
8
425
viii
Programmable Logic Design Guide
tpD 1
(max)
(max)
Icc
Family
Part No.
24-Pin
Generic
Array
Logic
GAL20V8-15L
GAL20V8-20L
GAL20V8-25Q
GAL20V8-25L
GAL20V8-30Q3
GAL20V8-30L3
GAL20V8-35Q
15
20
25
25
30
30
35
90
90
45
90
50
90
45
PALI016p8
PALI0016p8
6
6
-240
-240
PALlO16RD8
PALlO16RC8
PALI016RD4
PALlO16RC4
PAll 00 16RD8
PALI0016RC8
PALlOO16RD4
PALI0016RC4
62
62
6
6
62
62
6
6
-260
-260
-260
-260
-260
-260
-260
-260
PALlO16LD8
PALlO16LD4
PALI0016LD8
PAL 100 16LD4
6
6
6
6
-260
-260
-260
-260
PALlO16p4A
PALI0016P4A
4
4
-220
-220
Outputs
Comb.
Reg.
Pg.
8
8
8
8
8
8
8
439
ECL
Combinatorial
Registered *
Latched·
Combinatorial
Series-A *
8
8
4
4
4
4
4
4
455
8
8
4
4
8
8
4
4
465
8
4
8
4
465
4
4
* Preliminary
Note 1: Maximum tpD for combinatorial outputs (commercial operating range).
Note 2: Denotes characteristic speed of family where product has all registered
outputs.
Note 3: Speed range offered for military grade product only.
483
Table of Contents
1.0 Introduction
1.1
Purpose of this Design Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2
Overview of Programmable Logic ............................ 1
1.3
National Semiconductor, The Leader .......................... 2
2.0 Programmable Logic Basics
2.1
What is Programmable Logic ................................ 3
User Benefits of Programmable Logic ......................... 4
2.2
Reduced Board Space .................................... 4
Fast Systems Design ..................................... 5
Design Flexibility ....................................... 5
Multi-level Logic Reduction ............................... 5
Cost Reduction ......................................... 5
Example to Illustrate Lower Component Costs ................ 7
Example of Cost Reduction Through Reliability Improvements ... 8
Small Inventory ......................................... 9
2.3
Elements of Programmable Logic ........................... 10
The PROM ............................................ 10
The FPLA ............................................. 12
The PAL (Programmable Array Logic) Device ................ 14
Comparison ........................................... 16
2.4
Programmable Logic Versus Other LSI, Semicustom and Custom
Alternatives ............................................. 17
Standardized LSI ....................................... 17
Full Custom ICs ........................................ 17
Gate Arrays ........................................... 18
3.0 Boolean Logic Review
3.1
Basic Operators and Theorems ............................. 19
3.2
Derivation of a Boolean Expression .......................... 21
3.3
Minimization ............................................ 24
3.4
K-map Method .......................................... 25
3.5
Sequential Circuit Elements ................................ 31
3.6
State Machine Fundamentals ............................... 34
ix
Programmable Logic Design Guide
x
4.0 The Programmable Logic Family
4.1
Basic Groups ............................................ 39
The PAL Family .......................................... 39
4.2
PAL Devices for Every Task .............................. 41
Gates ................................................ 41
Register Options With Feedback .......................... 41
Programmable I/O ...................................... 42
PAL Device - Speed/Power Groups ....................... 42
PAL Device Logic Symbols ............................... 43
4.3
The Prom Family ................................................ 47
4.4 Logic Diagrams ................................................. 49
5.0 How to Design With Programmable Logic
5.1
Problem Definition ....................................... 83
5.2
Device Selection ......................................... 84
5.3
Writing Logic Equations ................................... 87
5.4
Programming the Device .................................. 88
5 .5
Testing the Device ....................................... 89
5.6
Programmer Vendor List .................................. 90
5.7
Examples
Example 1: Replace Existing Logic ......................... 92
Example 2: Design a Multiplexer .......................... 95
Example 3: Design a 3-bit Counter ....................... 100
Example 4: Design a Video-Telephone Sync Pulse Detector .... 102
6.0
Software Support
6.1
Advantages of Software-Based Programmable Logic Design ...... 107
6.2
Programmable Logic Analysis by National (PLAN) ............. 108
Boolean Entry ........................................ 109
File Editing and Documentation .......................... 110
Programming and Testing ............................... 110
6.3
Other Software ......................................... 112
CUPL ....................................................... 112
PALASM .................................................... 116
ABEL ....................................................... 116
6.4
Software for Testing Programmable Logic .................... 120
6.5
Software Vendor List ..................................... 120
7.0 Testing and Reliability
7.1
National Factory Testing .................................. 121
7.2
Logic Verifications ....................................... 123
7.3
Customer's Responsibilities ............................... 126
7.4
Reliability Data ......................................... 126
7.5
PAL Device Functional Testing ............................. 127
Table of Contents
7.6
Combinational and Sequential Circuits ....................
Description of PAL (Programmable Array Logic) Device .......
PAL Device Design Procedures ...........................
Description of Functional Table ... . . . . . . . . . . . . . . . . . . . . . . .
How to Generate Test Vectors and the Function Table
From Logic Equations .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example of Testing ......................................
Example 1: Combinational PAL12H6 ......................
Description .........................................
Example 2: Sequential PAL16R4 ..........................
Description .........................................
8.0 Applications
8.1
Basic Gates ............................................
8.2
Basic Clocked Flip-Flops .................................
8.3
Memory-Mapped I/O (Address Decoder) .....................
Functional Description .................................
8.4
Hexadecimal Decoder/Lamp Driver .........................
Functional Description .................................
General Description ...................................
PAL Device Implementation .............................
8.5
Between Limits Comparator/Logic ..........................
8.6
Quadruple 3-Line/l-Line Data Selector Multiplexer .............
8.7
4-bit Counter with 2-Input Multiplexer ......................
8.8
8-bit Synchronous Counter ...............................
8.9
6-bit Shift Register with Three-state Outputs .................
8.10 Portion of Random Control Logic for 8086 CPU Board . . . . . . . . .
8.11 DP84312 Dynamic RAM Controller
Interface Circuit for the NS32032, CPU. . .. . . . . .. . . . . . . . .... . .. ..
General Description ....................................
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mnemonic Description .................................
Functional Description .................................
8.12 DP84322 Dynamic RAM Controller Interface Circuit
for the 68000 CPU ......................................
General Description ...................................
Features .............................................
Mnemonic Description .................................
Functional Description .................................
8.13 DP84332 Dynamic RAM Controller Interface Circuit
for the 8086 and 8088 CPUs ..............................
General Description ...................................
Features .............................................
Mnemonic Description .................................
xi
127
128
128
129
133
136
136
136
143
143
157
162
168
168
172
172
172
174
178
181
183
187
190
194
197
197
197
200
200
207
207
207
211
211
227
227
228
230
xii
Programmable Logic Design Guide
8.14
Functional Description .................................
System Description ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Refresh Request Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A PAL Device Interface Between the National Semiconductor
NS32032 Microprocessor, DP8409 Dynamic RAM Controller,
and the DP8400 Expandable Error Checker and Corrector . . . . . .
230
231
233
242
9.0
National Masked Logic (NML)
9.1
NML Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
9.2
NML Guidelines ........................................ 270
10.0
Advantages of National's Programmable Logic Family
10.1
Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
10.2
Broad Product Line ...................................... 271
10.3
Customer Service and Support ............................. 272
11.0 Data Sheets
11.1
PAL Device Data Sheets ........................................ 273
Description ................................................. 273
Features .................................................... 274
20-Pin, Standard, Small PAL Devices .......................... 276
20-Pin, Standard, Medium PAL Devices ........................ 277
20-Pin, Fast, Small PAL Devices ............................... 279
20-Pin, Fast, Medium PAL Devices ............................ . 280
20-Pin, Ultra High-Speed, Medium PAL Devices .............. , . 282
20-Pin, Fast, Half-Power, Small PAL Devices ............................. 284
20-Pin, Fast, Half-Power, Medium PAL Devices .......................... 286
20-PIN, Ultra High-Speed, Half-Power, Medium PAL Devices ............. 288
24-Pin, Standard PAL Devices .......................................... 290
24-Pin, Fast PAL Devices ............................................... 292
11.2
ProgrammingNerifying Procedure-20 Pin PAL Devices ......... 294
Pre-verification ........................................ 294
Programming Algorithm ................................. 295
Programming the Security Fuses .......................... 297
11.3
ProgrammingNerifying Procedure-24 Pin PAL Devices ......... 298
Pre-Verification ........................................ 298
Programming AlgOrithm ................................. 298
Programming the Security Fuses .......................... 301
11.4
Logic PROM Data Sheets .................................. 304
Descriptions .......................................... 304
Testability ............................................ 304
Reliability ............................................ 304
11.5
DM54174S188, DM54/74S288 (32 x 8) 256-bit TTL PROMs ....... 307
11.6
PL77/87X288 (32 + 8) 256-bit TI1. PROM
...................... 309
Table of Contents
xiii
DM54174LS471 (256 + 8) 2K-bit TIl. PROM .................... 311
DM54174S473, DM54174S472, DM54174S473A, DM54174S472A
DM54174S472B (512 x 8) 4K-bit TTL PROMS .................. 313
General Description .................................... 313
Features .............................................. 313
11.9
DM54174S475, DM54174S474, DM54174S475A, DM54174S474A
DM54174S474B (512 x 8) 4K-bit TTL PROMS .................. 316
General Description .................................... 316
Features .............................................. 316
11.10 DM77/87SR474, DM77/87SR474B (512 x 8) 4K-bit
Registered TTL PROMs .................................... 319
Resistered TTL PROMs
General Description ................................... 319
Features ............................................. 320
11.11 DM77/87SR476, DM77/87SR25, DM77/87SR476B, DM77/87SR25B
(512 x 8) 4K-bit Registered TTL PROMs ....................... 323
General Description .................................... 323
Features .............................................. 323
11.12
Registered PROM Programming Procedure ..................... 327
11.13
Non-Registered PROM Programming Procedure ................ 329
11.14
Quality Enhancement Programs ............................... 332
12.0 New Product Data Sheets
12.1 TTL PAL Devices
PLA87/77XI53B 18 x 42 x 10 Field Programmable Logic Array .. 335
Programmable Array Logic (PAL) 24-Pin Exclusive-OR PAL SeriesVersion A .............................................. 341
Programmable Array Logic Family Series 24B ................. 353
Programmable Array Logic (PAL) Ultra High Speed Series 24BP .. 365
Programmable Array Logic (PAL) 20-Pin Medium PAL FamilySeries D ................................................ 377
Programmable Array Logic (PAL) 24-Pin Medium PAL FamilySeries D ................................................ 393
Programmable Array Logic PAL16RA8 ...................... 409
Programmable Array Logic PAL20RA 10 ..................... 417
12.2 CMOS Programmable Logic Devices
GAL16V8 Generic Array Logic ............................. 425
GAL20V8 Generic Array Logic ............................. 439
12.3 ECL PAL Devices
ECL Programmable Array Logic (PAL) Family ................. 455
ECL Registered and Latched Programmable Array Logic (PAL)
Family ................................................. 465
4 ns ECL Programmable Array Logic (PAL) Family ............. 483
13.0 Package Outlines . ............................................ 489
14.0 Terminology ................................................. 497
11.7
11.8
xiv
Programmable Logic Design Guide
Appendix-An Overview of LSI Testing Techniques
A1
Testing Methods .............................................. 504
Concurrent Testing ......................................... 504
Explicit Testing ............................................. 505
A2
Test Generation Techniques.................................... 507
NP-Complete Problems ..................................... 508
Manual Test Generation .................................... 511
Path Sensitization and the D-Algorithm ...................... 513
Algorithmic Test Generation ................................ 515
The Thatte-Abraham Technique ............................. 516
The Abadir-Reghbati Technique ............................. 518
Simulation-Aided Test Generation ........................... 519
Binary Decision Diagrams .................................. 521
Random Test Generation ................................... 523
A3
Response Evaluation Techniques .............................. 524
Good Response Generation ................................. 524
Stored Response Testing .................................... 524
Comparison Testing ........................................ 526
Compact Testing ........................................... 526
Transition Counting ........................................ 527
Signature Analysis .......................................... 529
List of Illustrations
Figure No.
2.1.1
2.1.2
2.2.1
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
3.1.1
3.2.1
3.2.2
3.2.3
3.3.1
3.3.2
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.4.9
3.4.10
3.4.11
3.5.1
3.5.2
3.6.1
3.6.2
3.6.3
Page No.
Conventional Representation ......................................
Programmable Logic Representation ...............................
Multilevel Logic Reduction ........................................
Diode OR Matrix .................................................
4 x 4 Bit PROM ..................................................
PROM Having 16 Words x 4 Bits ..................................
FPIA Having 4 Inputs, 4 Outputs, and 16 Products ..................
PAL Device Having 4 Inputs, 4 Outputs, and 16 Products ............
(a) Logic Equation, (b) PROM Solution, (c) FPIA Solution,
(d) PAL Device Solution ..........................................
3
4
6
10
11
12
13
15
Basic Gates ......................................................
Logic Circuits ofEq. 3.2.1 .........................................
Logic Circuits of Eq. 3.2.2 .........................................
Simplified Logic Circuits ..........................................
A Random Logic Circuit ...........................................
Minimied Logic Circuit ...........................................
Truth Tables for AND and OR .....................................
K-maps for AND and OR ..........................................
K-maps for 3-Variables AND and OR ...............................
Sample 3-Variable K-maps ........................................
K-maps for Two and Three Variables ..............................
K-map of m (0, 2, 3, 7) ............................................
K-map of M (0, 1, 5, 6) ............................................
Adjacent Minterms on a K-map ....................................
Minimization .....................................................
Minimization .....................................................
Minimization .....................................................
Basic Flip-Flops ..................................................
Implement D Flip-Flop by USingJ-K ...............................
A Typical Sequential Circuit .......................................
State Diagram ....................................................
Example of Hazard Circuit ........................................
19
23
23
24
24
25
26
26
27
28
28
29
29
29
30
30
31
32
33
34
35
36
16
xv
xvi
Programmable Logic Design Guide
Figure No.
Page No.
3.6.4
3.6.5
Example of Unstable Circuit ........................................ 36
Example fo Circuit With Unpredictable Output States ............... 37
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.3.1
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
4.4.6
4.4.7
4.4.8
4.4.9
4.4.10
4.4.11
4.4.12
4.4.13
4.4.14
4.4.15
4.4.16
4.4.17
4.4.18
4.4.19
4.4.20
4.4.21
4.4.22
4.4.23
4.4.24
4.4.25
4.4.26
4.4.27
4.4.28
4.4.29
4.4.30
4.4.31
4.4.32
PAL Device Output Register Circuit, Simplified Logic Diagram .......
PAL Device Bidirectional Circuit, Logic Diagram ....................
Logic Symbol. DMPAL10H8 ........................................
PAL Device Logic Symbols - Series 20 ............................
PAL Device Logic Symbols - Series 24 ............................
PROM Logic Symbols .............................................
Logic Diagram PALlOH8 ..........................................
Logic Diagram PAL12H6 ..........................................
Logic Diagram PAL14H4 ..........................................
Logic Diagram PAL16H2 ..........................................
Logic Diagram PAL16C1 ...........................................
Logic Diagram PAL10L8 ...........................................
Logic Diagram PAL12L6 ...........................................
Logic Diagram PAL14L4 ...........................................
Logic Diagram PAL16L2 ...........................................
Logic Diagram PAL16L8 ...........................................
Logic Diagram PAL16R8 ...........................................
Logic Diagram PAL16R6 ...........................................
Logic Diagram PAL16L4 ...........................................
Logic Diagram PAL12LlO ..........................................
Logic Diagram PAL14L8 ...........................................
Logic Diagram PAL16L6 ...........................................
Logic Diagram PAL18L4 ...........................................
Logic Diagram PAL20L2 ...........................................
Logic Diagram PAL20C1 ...........................................
Logic Diagram PAL20LlO ..........................................
Logic Diagram PAL20X10 ..........................................
Logic Diagram PAL20X8 ...........................................
Logic Diagram PAL20X4 ...........................................
Logic Diagram PAL20L8 ...........................................
Logic Diagram PAL20R8 ...........................................
Logic Diagram PAL20R6 ...........................................
Logic Diagram PAL20R4 ...........................................
32 x 8 PROM Logic Diagram ......................................
256 x 8 PROM Logic Diagram .....................................
512 x 8 PROM Logic Diagram .....................................
512 x 8 PROM Logic Diagram, SR476/SR25 ........................
512 x 8 Register PROM Logic Diagram ............................
41
42
43
44
46
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
List of Illustrations
Figure No.
xvii
Page No.
5.1.1
5.3.1
5.3.2
5.4.1
5.5.1
5.7.1
5.7.2
5.7.3
5.7.4
5.7.5
5.7.6
5.7.7
5.7.8
5.7.9
5.7.10
5.7.11
5.7.12
Design Sequence of the Programmable Logic Device .............
Combinational PAL Device Design Steps .........................
Sequential PAL Device Design Steps .............................
PAL Device Programming Procedures................... .........
Test Vectors Creating Steps .....................................
Design Example, Logic Diagram .................................
Example of PALASM Program Input ..............................
PALASM Operators .............................................
Logic Diagram of the National Type 12L6 PAL Device .............
PAL Device Legend .............................................
Block Diagram of a Multiplexer .................................
Logic Diagram of the National Type 14H4 PAL Device.... .........
3-Bit Counter ..................................................
K-map .........................................................
Sweep Generation ..............................................
(a) State Diagram, (b) State Table ...............................
K-map .........................................................
83
87
88
89
90
92
93
94
96
97
98
99
100
101
102
103
105
6.1.1
6.1.2
6.2.2
6.2.2
6.3.1
6.3.2
6.3.3
6.3.4
Early Role of Software ..........................................
Expanded Role of Software .....................................
Plan File Information ...........................................
Fuse Map Display from Plan .....................................
CUPL-GTS Screen Display Example ..............................
Block Diagram: 6809 Memory Address Decoder ..................
Simplified Block Diagram .......................................
Source File: 6809 Memory Address Decoder .....................
107
108
110
111
115
117
118
119
7.1.1
7.2.1
7.2.2
7.2.3
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
PAL Device Test Flow ...........................................
PAL Devices Architecture. . . . . . . . . .. . . . . . . . . .. .. . . . .. . . . . .. . .. . . .
Function of Test Vector .........................................
3-Input and Gate ...............................................
Combinational Circuit ..........................................
Sequential Circuit ..............................................
Combinational PAL Device Design Steps .........................
Sequential PAL I!evice Design Steps .............................
PAL Device Programming Procedures................... .........
Test Vector and Function Table Creating Steps ...................
Logic Circuit of Example # 1 ....................................
State Diagram ..................................................
122
123
124
124
126
128
130
131
132
133
136
152
xviii
Programmable Logic Design Guide
Figure No.
8.1.1
8.1.2
8.2.1
8.3.1
8.3.2
8.4.1
8.4.2
8.5.1
8.5.2
8.6.1
8.7.1
8.7.2
8.9.1
8.10.1
8.11.1
8.11.2
8.11.3
8.11.4
8.11.5
8.11.6
8.12.1
8.12.2
8.12.3
8.12.4
8.12.5
8.12.6
8.12.7
8.12.8
8.12.9
8.12.10
8.12.11
8.12.12
8.13.1
8.13.2
8.13.3
8.13.4
8.13.5
8.13.6
8.13.7
8.13.8
Page No.
Basic Gates ....................................................
Logic Diagram PAL12H6 ........................................
Logic Diagram PAL16R8 .........................................
Memory Mapped 110 Logic Diagram.............................
Logic Diagram PAL16L2 .........................................
Hex Display Decoder-Driver, Combinational Logic Diagram ......
Logic Diagram PALi6iB .........................................
PAL Device 16C1 Limit Checker .................................
Logic Diagram PAL16C1 .........................................
Logic Diagram PAL14H4 ........................................
Four-Bit Counter With Two-Input Multiplexer ....................
Logic Diagram PAL16R4 .........................................
Logic Diagram PAL16R6 .........................................
Control Logic for 8086 CPU Board...............................
Connection Diagram ...........................................
System Block Diagram ..........................................
Timing Diagram; Read, Write or Hidden Refresh Memory
Cycle for the NS16032-DP8409 Interface .........................
Timing Diagram; Read, or Write Memory Cycle With One Wait ....
Timing Diagram; Forced Refresh cycle ...........................
DP84312 Logic Diagram PAL16R6 ................................
Connection Diagram ...........................................
Block Diagram .................................................
System Block Diagram................. .........................
Timing Diagram; 68000 Memory Read Cycle .....................
Timing Diagram; 68000 Memory Read Cycle and Forced Refresh .,
Timing Diagram; TAS Instruction Cycle ..........................
Timing Diagram; Memory Read Cycle............................
Timing Diagram; Memory Read Cycle and Forced Refresh ........
Modified System Block Diagram..... ............................
Timing Diagram 68000 Memory Read Cycle ......................
Timing Diagram 68000 Memory Read Cycle and Memory Refresh .
DP84322 Logic Diagram PAL Device 16R4 ........................
Connection Diagram ...........................................
Block Diagram .................................................
System Block Diagram ..........................................
Using a Flip-Flop and a Counter for Refresh Request Logic ........
Using the DP84300 Refresh Counter for Refresh Logic ............
Timing Diagram; Read Timing ...................................
Timing Diagram; Write Timing ..................................
Timing Diagram; Memory Cycle With 1 Wait State ................
157
i60
167
168
171
173
177
178
180
182
183
186
193
194
197
199
202
202
203
206
207
208
210
216
217
218
219
220
221
222
223
226
227
228
232
233
233
234
235
236
List of Illustrations
Figure No.
xix
Page No.
237
238
241
242
245
250
251
252
253
254
255
256
257
258
8.14.14
8.14.15
8.14.16
8.14.17
Timing Diagram; Forced Refresh ................................
Timing Diagram, Transparent Refresh ...........................
84332 Logic Diagram PAL16R8 ...................................
DP8400, DP8409, NS16032 6 MHz Computer System ..............
DP8400/8409 System Interface Block Diagram ....................
Timing Diagram; Read Cycle and Write Cycle ....................
Timing Diagram; Read Cycle With Simple Bit Error ...............
Timing Diagram; Byte Write .....................................
Timing Diagram; Forced Refresh Then Access ....................
Simulation Circuit ..............................................
Simulation Timing Diagram; ReadlWrtie Without Errors ..........
Simulation Timing Diagram; Read With Error and Write Cycle .....
Simulation Timing Diagram; Byte Write ..........................
Simulation Timing Diagram; Forced Refresh Then Access .........
Simulation Timing Diagram; Write, Forced Refresh and
Read Access ....................................................
Simulation Timing Diagram; Forced Refresh Followed by
Read Access (With Error) .......................................
Logic Diagram of PAL Device #1 ................................
Logic Diagram of PAL Device #2 ................................
Logic Diagram of PAL Device #3 ................................
Logic Diagram ofpAL Device #4 ................................
9.1.1
NML Procedure ................................................
270
11.1.1
11.2.1
11.3.1
11.3.2
11.4.1
11.4.2
11.4.3
11.4.4
11.5.1
11.6.1
11.7.1
11.8.1
11.9.1
11.10.1
11.11.1
11.12.1
11.13.1
Test Waveforms and Schematics of Inputs and Outputs ...........
Pin Assignment for Programming ................................
Pin Assignment for Programming ................................
Programming Waveforms .......................................
Standard Test Load .............................................
Switching Time Waveforms Non -Registered PROMs ..............
Switching Waveforms, Registered PROM .........................
Key to Timing Diagram .........................................
Block and Connection Diagram .................................
Block and Connection Diagram .................................
Block and Connection Diagram .................................
Block and Connection Diagram .................................
Block and Connection Diagram .................................
Block and Connection Diagram .................................
Block and Connection Diagram .................................
Programming Waveforms, Registered PROM .....................
Programming Waveforms, Non-Registered PROM ................
275
294
298
302
305
305
306
306
307
309
311
313
316
320
324
329
331
8.13.9
8.13.10
8.13.11
8.14.1
8.14.2
8.14.3
8.14.4
8.14.5
8.14.6
8.14.7
8.14.8
8.14.9
8.14.10
8.14.11
8.14.12
8.14.13
259
260
265
266
267
268
xx
Programmable Logic Design Guide
Figure No.
Page No.
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
13.9
13.10
NS Package ]16A, 16-Lead Cavity DIP 0) ..........................
NS Package N16E, 16-Lead Molded DIP (N) (Substitute for N16A) ..
NS Package ]20A, 20-Lead Cavity DIP 0) ..........................
NS Package N20A, 20-Lead Molded DIP (N) ......................
NS Package]24F, 24-Lead Cavity DIP 0) ..........................
NS Package N24C, 24-Lead Molded DIP (N) ......................
NS Package ]24A, 24-Lead Cavity DIP 0) ..........................
NS Package N24A, 24-Lead Molded DIP (N) ......................
NS Package PCC-20, 20-Lead Plastic Leaded Chip Carrier (V) .......
NS Package PCC-28, 28-Lead Plastic Leaded Chip Carrier (V) .......
489
490
490
491
491
492
492
493
494
495
A.I.I
A.2.I(a)
A.2.I(b)
LSI Test Technology ............................................
A One-Out-of-Four Multiplexer-Gate-Level Description ...........
Functional-Level Description ....................................
Gate-Level Description of a Three-Bit Incrementer ...............
Transfer Instruction ............................................
Add Instruction ................................................
OR Instruction .................................................
Rotate Left Instruction ..........................................
A Half-Adder ...................................................
Binary Decision Diagram for C = x·y ...........................
Binary Decision Diagram for S = X + Y( c) ......................
Simplified Binary Decision Diagrams for the Half-Adder .......... Binary Decision Diagrams for a Full-Adder .......................
Stored Response Testing ........................................
Comparison Testing ............................................
Compact Testing ...............................................
One-Out-of-Four Multiplexer. .... . .... . . ... .. . .. . . .. . . .. . .. . .. . .
The 16-Bit Linear Feedback SR Used in Signature Analysis.. . . ... ..
506
509
509
510
517
517
517
51 7
521
521
521
522
522
525
525
527
528
529
A.2.2
A.2.3(a)
A.2.3(b)
A.2.3(c)
A.2.3(d)
A.2.4(a)
A.2.4(b)
A.2.4(c)
A.2.5
A.2.6
A.3.1
A.3.2
A.3.3
A.3.4
A.3.5
List of Tables
Table No.
2.2.1
2.2.2
3.2.1
3.6.1
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.3.1
4.3.2
5.1.1
5.2.1
5.2.2
5.6.1
5.6.2
5.7.1
5.7.2
5.7.3
5.7.4
5.7.5
5.7.6
5.7.7
6.2.1
6.2.2
6.2.3
6.3.1
6.3.2
Page No.
Typical Component Cost Structure ..............................
System Cost Comparison Between SSIIMSI Based System and
PAL Device Based System .......................................
7
8
Truth Table ofEq. 3.2.1 and 3.2.2 ................................
State Table .....................................................
22
34
Members of the 20-Pin PAL Device Family ........................
Members of the 24-Pin PAL Device Family ........................
PAL Device Part Number Interpretation ..........................
20-Pin PAL Device SpeedIPower Groups .........................
24-Pin SpeeclJPower Groups ....................................
PROM Configurations ...........................................
PROM Products for Logic .......................................
39
40
40
42
43
47
48
Typical PAL Circuits .............................................
20-Pin PAL Device Configuration ................................
24-Pin PAL Device Configuration ................................
PAL Device Programmers .......................................
PAL Device Development Systems ...............................
Fuse Map ......................................................
Truth Table ....................................................
Function Table .................................................
Transition Lists .................................................
Transition Table ................................................
State Assignment ...............................................
Transition Table ................................................
84
85
86
90
91
95
98
98
100
101
104
104
Boolean Operators .............................................
Macro Entry With PLAN .........................................
Fuse Map File Formats in PLAN ..................................
Address Ranges for 6809 Controller .............................
PAIASM Operators .............................................
109
109
111
118
116
xxi
xxii
Programmable Logic Design Guide
Table No.
Page No.
7.1.1
7.2.1
7.2.2
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10
7.5.11
Test Fuses .................................................... .
Test Vectors Generated by the Exhaustive Method ............... .
Test Vectors Generated by Fault Modeling ...................... .
National's PAL Device Family ................................... .
Test Vectors ................................................... .
Test Vectors ................................................... .
Final Test Vectors ............................................. .
Final Function Table ........................................... .
Test Vectors
Test Vectors ................................................... .
Test Vectors ................................................... .
State Assignment .............................................. .
Transition Table ............................................... .
Final Function Table ........................................... .
121
8.4.1
8.11.1
8.11.2
8.11.3
8.11.4
8.12.1
8.12.2
8.12.3
8.12.4
8.12.5
8.12.6
8.13.1
8.13.2
8.13.3
8.13.4
8.13.5
Function Description .......................................... .
Recommended Operating Conditions ........................... .
Electrical Characteristics ....................................... .
Switching Characteristics ....................................... .
Function Table ..................................... '........... .
Recommended Operating Conditions ........................... .
Electrical Characteristics ....................................... .
Switching Characteristics ....................................... .
Memory Speed ................................................ .
Memory Speed of 68000 ....................................... .
Function Table ................................................ .
Recommended Operating Conditions ........................... .
Electrical Characteristics ....................................... .
Switching Characteristics ....................................... .
Memory Speed Requirements .................................. .
Function Table ................................................ .
172
11.1.1
11.1.2
11.1.3
11.1.4
11.1.5
11.1.6
20-Pin PAL Devices ............................................ .
24-Pin PAL Devices ............................................ .
Absolute Maximum Ratings .................................... .
Standard Test Load ............................................ .
AC and DC Specifications for 20-Pin, Standard, Small PAL Devices .
AC and DC Specifications for 20-Pin, Standard, Medium
PAL Devices ................................................... .
AC and DC Specifications for 20-Pin, Fast, Small PAL Devices ..... .
AC and DC Specifications for 20-Pin, Fast, Medium PAL Devices .. .
11.1.7
11.1.8
125
125
129
138
139
139
140
145
148
149
150
150
151
198
198
198
205
209
209
209
213
214
225
229
229
229
231
240
274
274
275
275
276
277
279
280
List of Tables
Table No.
11.1.9
11.1.10
11.1.11
11.1.12
11.1.13
11.1.14
11.2.1
11.2.2
11.3.1
11.3.2
11.3.3
11.4.1
11.5.1
11.5.2
11.6.1
11.6.2
11.7.1
11.7.2
11.8.1
11.8.2
11.9.1
11.9.2
11.10.1
11.11.1
11.12.1
11.13.1
11.13.2
11.14.1
A.3.1
A.3.2
xxiii
Page No.
AC and DC Specifications for 20-Pin, Ultra High-Speed,
Medium PAL Devices ...........................................
AC and DC Specifications for 20-Pin, Fast, Half-Power, Small
PAL Devices ....................................................
AC and DC Specifications for 20-Pin, Fast, Half-Power, Medium
PAL Devices ....................................................
AC and DC Specifications for 20-Pin, Ultra High-Speed,
Half-Power, Medium PAL Devices ................................
AC and DC Specifications for 24-Pin, Standard PAL Devices ........
AC and DC Specifications for 24-Pin, Fast PAL Devices ............
Input Line Select ...............................................
Input Line Select ...............................................
Input Line Select ...............................................
Product Line Select .............................................
Programming Parameters .......................................
Absolute Maximum Ratings .....................................
(32 x 8) 256-Bit TIL PROM Options .............................
AC and DC Specifications for (32 x 8) 256-Bit TIL PROMs ........
(32 x 8) 256-Bit TIL PROM Options .............................
AC and DC Specifications for (32 x 8) 256-Bit TIL
Logic PROMs ...................................................
(256 x 8) 2048-Bit TIL PROM Options ..........................
AC and DC Specifications for (256 x 8) 2048-Bit TIL PROMs ......
(512 x 8) 4096-Bit TIL PROM Options ..........................
AC and DC Specifications for (512) 4096-Bit TIL PROM ...........
(512 x 8) 4096-Bit TIL PROM ...................................
AC and DC Specifications for (512 x 8) 4096-Bit TIL
High-Speed PROM ..............................................
AC and DC Specifications for (512 x 8) 4K-Bit Registered
TIL PROMs ....................................................
AC and DC Specifications for (512 x 8) 4K-Bit Registered
TIL PROMs ....................................................
Programming Parameters Do Not Test or You May Program
the Device .....................................................
Programming Parameters Do Not Test or You May Program
the Device .....................................................
Approved Programmers for NSC PROMs .........................
Quality Enhancement Program for Bipolar Memory ..............
The eight test patterns used for testing the multiplexer
of Figure A4.4 .................................................
A different sequence of the eight multiplexer test patterns ........
282
284
286
288
290
292
295
295
299
299
301
305
307
308
309
310
311
312
313
314
316
317
321
325
328
331
332
332
529
529
1
Introduction
1.1
PURPOSE OF THIS DESIGN GUIDE
This book was conceived to fill the need for a comprehensive Design Guide about
Field-Programmable Logic Devices. The Guide is organized to serve both the experienced programmable logic user and the uninitiated. The primary objective of this guide
is to introduce the uninitiated logic designer to programmable logic and to take the
designer through a step-by-step approach to logic design by using programmable logic
devices. The Guide is comprehensive in that it covers all aspects of design, including:
Boolean logic basics, sequential and combinational circuit basics, testing, and applications. Every effort has been made to clearly illustrate points with examples. National
Semiconductor invites comments and suggestions from our users on improving this
Design Guide.
1.2
OVERVIEW OF PROGRAMMABLE LOGIC
Programmable Logic has been used for many years as the means of customizing logic
design. The early devices were primarily mask-programmed and were developed by
computer manufacturers for in-house use while the vast majority of other logic users
were relegated to the world of standard SSIIMSI devices. Then, in the mid to late seventies, along came fuse-programmable logic. The logic devices could actually be customized by the designer who used external pulses generated by simple programmer
equipment. Now logic designers had devices that could be customized instantly and
that offered higher integration than standard logic. Field-programmable logic devices
became the first, true semicustom logic that was widely available for both the small and
the larger user.
Today, the user can choose from a variety of speeds, power, packages, logic features and vendors.
The logic designer's task is being simplified even further by the rapid development
of software tools that actually perform some of the design tasks such as logic minimization, higher level Boolean representation, device selection, and test vector generation.
The final goal is to simply specify input-output or state descriptions in a high-level language to obtain a completely programmed and functionally tested device.
Technology developments are also taking place to achieve field-programmable
logic devices in low-power CMOS technology and high-speed ECL technology.
1
2
1.3
Programmable Logic Design Guide
NATIONAL SEMICONDUCTOR, THE LEADER
National Semiconductor entered the field programmable logic marketplace in 1980
with the introduction of the PAL@ device family. By 1984 National had taken the leadership of this market through technological advances and customer support. In particular, National is the first company ~o come out with the 15 ns high-performance family of
PAL devices. National also has the broadest product line of programmable-logic products that will include CMOS and ECL products. National Semiconductor is committed
to maintaining its leadership in this area through technological innovation, customer
support and product quality.
PAL is a registered trademark of and used under license to Monolithic Memories, Inc.
2
Programmable Logic Basics
2.1
WHAT IS PROGRAMMABLE LOGIC?
Programmable logic devices are essentially uncommitted logic gates where the user
determines the final logic configuration of the device. Hence, programmable logic
devices are true semicustom products. A major feature of these devices is fieldprogrammability, which offers almost instant customization. A mask-programmable
option is also available for volume applications. The internal structure of these devices
is a fuse-programmable interconnection of AND gates, OR gates, and Registers. These
devices allow the user to design combinational as well as sequential circuits. The basic
programmable array is AND-OR logic in the familiar Sum-of-Products (SOP) representation. The conventional schematic representation is shown in Figure 2. 1.1.
~------~:r-~:~:_:______~
A -----1-"""'\ AB
B
.-----~
~ -----I-~C~D~---~;:::====:r:)>------ 01
A----r-" AD
D
~~------~
Figure 2.1.1
Conventional Representation
3
4
Programmable Logic Design Guide
Its programmable logic equivalent is shown in figure 2.1.2.
D
c
B
Figure 2.1.2
A
Programmable Logic Representation
Various programmable logic products are built around this structure by adding features and other logic elements such as programmable Active-Low or Active-High outputs, output registers, internal feedback, and state registers.
A definition of programmable logic is not complete without including software.
An important part of these products is the software and design automation tools that
aid systems design with programmable logic devices.
2.2
USER-BENEFITS OF PROGRAMMABLE LOGIC
The use of programmable logic devices in systems design presents the user with many
benefits, some of which are obvious and some of which are not. The versatility and
power of programmable logic devices can be demonstrated through the most common
benefits described below.
Reduced Board Space
Today, programmable logic typically implements from 4 to 20 SSI and MSI logic devices
on a single chip. PC board real estate is one of the most valuable and limited items in a
system and programmable-logic devices are ideal for reducing board space. This can
allow the system manufacturer to reduce the size of a system or to increase the logic
power for a system of a given size.
Programmable Logic Basics
5
Fast Systems Design
Fast turnaround in systems design can be achieved. Systems can be prototyped quickly
by using available design automation development tools. Standard design tools reduce
the need for manual design and documentation. After the first prototype has been built,
modifications and correction to the logic can also be made quickly, without having to
rewire or rework the PC board. The net result is that the programmable-logic user can
enjoy a competitive advantage in the marketplace by bringing new products to
market early.
Design Flexibility
Systems design is generally an iterative process. It starts with ideas and concepts and
then progresses through an iterative series of evaluation, modification, and refinement
of the original design. Numerous logic configurations have to be evaluated in this process and the painless way to perform these evaluations is through the use of programmable logic. All of the changes can be made at the CAD terminal, which will also ensure
that the documentation is updated to include the changes.
With the use of programmable logic, the designer is not limited to standard off the
shelf parts and, therefore, can use non-standard logic structures. The engineer now
simply chooses what is needed instead of taking only what is available.
Design flexibility derived from using programmable logic means logic changes are
easy in all phases of the system life cycle. For example, logic changes can be made during proto typing, during system testing, during system production, and in the field.
Many manufacturers need to be able to perform some final customization to the
system. The use of programmable logic allows this customization to be implemented
quickly.
Multilevel Logic Reduction
The designer can compress multiple levels of logic into a two-level AND-OR structure
through the use of programmable logic, thus simplifying the design and in many cases
obtaining a speed and/or power advantage. An example is shown on the following page
in Figure 2.2.1.
Cost Reduction
The systems manufacturer can realize cost reduction by the use of programmable logic
through a variety of factors, including:
• Lower component cost through
- PC board area reduction.
- Reduction in connectors used.
- Simpler back panel.
- Smaller power supplies.
- Reduced cooling.
6
Programmable Logic Design Guide
F1 = a [b + c(d + e) + i
LOGIC EQUATION
LEVEL 5 I LEVEL 4
I
I
I
LEVEL 3
LEVEL 2
9] + hi; + k
LEVEL 1
I
I
k----""
ANDIOR NETWORK
Figure 2.2.1
Multilevel Logic Reduction
• Lower design and development cost through
- Quick-turnaround software-supported design.
- Easy-to-make changes.
- Computerized documentation.
- Simplified layout.
• Lower manufacturing cost through
- Fewer component insertions.
- Fewer boards to manufacture.
- Less component, board and system testing.
• Lower service costs through
- Improved reliability.
- Fewer spare parts.
- Faster logic fixes.
Programmable Logic Basics
7
Example to Illustrate Lower Component Costs
Table 2.2.1 is an example of the elements of component cost. The costs used are typical
of those found in the industry and will have to be modified to reflect a specific
situation.
Cost Variable
Purchasing, Receiving, Inventory
Incoming Inspection
Cost Range
Ave Cost
$
$
CostilC
$
0.01-0.03
0.02
0.02
0-0.15
0.08
0.08
10-100
30.00
0.30
0.10-0.40
0.20
0.20
Connectors, Wire, etc.
30-100
60.00
0.10
Power Supplies, Cooling
45-120
60.00
0.10
System Assembly
40-80
60.00
0.10
Rack, Cabinet, Pimels
20-50
30.00
0.05
PC Board
Assembly Labor
0.95
Total Overhead
0.12-2.00
IC Cost
Total
Ie Cost in System
0.50
1.45
Table 2.2.1
Typical Component Cost Structure
Assume a system with 600 SSIIMSl lCs. The total cost of the system is therefore as
follows:
SSIIMSl System Cost
= 600
X
$1.45
= $870
PAL devices are used to replace the SSIIMSl discrete logic devices. The replacement can be accomplished at various efficiencies, where efficiency is defined as:
Efficiency
= Average number of SSIIMSl devices replaced by one PAL.
If we assume that the cost of programming a PAL device is $0.40 then the total cost
of a PAL based system is as follows:
PAL based system cost =
600
Efficiency
600
Efficiency
X
---- X
(PAL Device Price + Overhead + Programming Cost)
(PAL Device Price + $0.95 + $0.40)
8
Programmable Logic Design Guide
Various efficiencies and PAL device prices are substituted in the above equation to
obtain the PAL based system costs in Table 2.2.2 below.
Efficiency
Factor (EF)
SSI/MSI
System
Cost (1)
PAL Device System Cost (2) at a
PAL Device Purchase Price of
$8.00
$6.00
$4.00
$3.00
3:1
870
1870
1470
1070
870
4:1
870
1403
1103
803
653
6:1
870
935
735
535
435
8:1
870
701
551
401
325
Your SSIIMSI
System Cost
Your PAL Device
System Cost
@ IPAL Device
(1) Cost = 600 ICs x 1.4511C = $870
(2) Cost = [600 -;- EF] x [PAL Device price + Overhead + Programming Cost]
= [600 -;- EF] x [PAL Device price + 0.95 + 0.40]
= [600 -;- EF] x PAL Device price + 1 .35
Table 2.2.2
System Cost Comparison Between SSI/MSI Based System and
PAL Device Based System.
Most users realize at least a 4: 1 ratio and at today's PAL device prices, it is clearly
more economical to use PAL devices. Furthermore, as prices decline, even low efficiencies become economical.
Example of Cost Reduction Through Reliability Improvements
A simple example is used here to illustrate the power of PAL devices to improve system
reliability. Assume that systems fail for only two reasons:
• External connection failures (70 %)
- Solder.
- Connectors.
- Back plane wiring .
• IC failures (30%)
A hypothetical system is defined as having 5 boards each with 100 SSI/MSI devices.
With the following assumptions:
- System is in use for 3 years.
- Single device failure probability is 0.01 % within the 3 years.
- Single device failure will cause board failure, which will result in system
failure.
- 100 systems are sold.
- $1000 cost for each system failure.
Programmable Logic Basics
9
SSIIMSI device-related system failure probability = 1 - (0.990011)5
External connection failure probability =
0.0489583
30
X
70
=.0.114236
Total system failure probability within the three years = 0.1631943
Total Expected Cost from system failures during the three years= $1000
0.1631943;;;;; $16,000
X
100
X
The logic designer now uses PAL devices and other LSI devices to realize a 5: 1 SSIIMSI
chip replacement. The system will now have one board. The system failure probability
and expected cost of the PAL device-based system is computed below:
Device-related board failure probability
External connection failure probability
= 1 - (0.9999)100 = 0.009989
=
=
0.009989
30
X
70
0.023307666
Total PAL device-based system failure probability = 0.033296666
Total Expected Cost of PAL device based system = $1000
X
100
X
0.033296666
:::::$3300
On comparing the expected costs from system failures of the SSIIMSI based system
to that of the programmable-logic based system, there is approximately a 5: 1 ratio of
cost in favor of the programmable-logic based system.
This example is somewhat simplistic and some gross assumptions were made to
illustrate the advantages of using programmable logic. In reality, the actual reliability
improvement will depend on numerous factors that have not been addressed here.
Small Inventory
The programmable logic family can be used to replace up to 90% of TTL components.
This allows the user to lower inventory costs conSiderably, in addition to simplifying
the inventory system.
10
2.3
Programmable Logic Design Guide
ELEMENTS OF PROGRAMMABLE LOGIC
The first programmable integrated circuit logic device was the diode matrix. It was
introduced in the early 1960s. This approach featured rows and columns of metallization, connected at the crosspoints with diodes and aluminum fuses (Figure 2.3.1).
These fuses could be selectively melted, leaving some of the crosspoints open and others connected. The result was a diode-logic OR matrix.
11....- - - t -....--~..----I1-e----+-
11 .....- - - H . . - - - H I - - - - - f......- - _ + _ -
12....- - - H a - - - - H I - - - - - f......~-_+_-
Figure 2.3.1
Diode OR Matrix
The PROM
Integrated circuit designers added input decoders and output buffers to the basic diode
matrix, creating the field-programmable read-only memory (PROM) (Figure 2.3.2). This
extended the programmable-logic concept considerably, since the input variables
could now be encoded. It also reduced the number of pins required per input variable.
At the same time, the input circuitry, along with the output buffers, provided TTL compatibility, the lack of which was one of the drawbacks of the diode matrix. For the sake
of simplicity and clarity, the programmable diode matrix is shown at a simple crosspoint in Figure 2.3.3
A decoder is nothing more than a collection of AND gates that combine all the
inputs to produce product terms. The basic logic implemented by the PROM is
AND-OR with the AND gates all preconnected on the chip, making this portion fixed.
Programmable Logic Basics
11
The OR matrix is implemented with diode-fuse interconnections, making it programmable. Thus, the PROM is an AND-OR logic element with fixed AND matrix and programmable OR.
There are many advantages to using PROMs as logic devices. Because they are used
in many applications, they are produced in high volume. Also, the PROM is a universal
logic solution. In other words, all of the product terms of the input variables are generated. This makes it possible to implement any AND-OR function of these variables.
On the less positive side, it is difficult to accomodate a large number of variables
with PROMs. For each variable added to the PROM, not only does the package increase
by one pin, but the size of the fuse matrix doubles. For example, an eight-function,
five-variable PROM (32 X 8) requires a 256-fuse element matrix. An eight-function,
six-variable device (64 x 8) requires a 512-element matrix. As a practical matter, PROMs
are limited in the maximum number of input variables they can be designed to handle.
Manufacturers are currently producing no larger than 13-input PROMs.
DECODER
AND
FUSE MATRIX
(OR)
r-----------,
I
1112
~~-----+~----~------~~---+--
L __________ ..J
Figure 2.3.2
4 x 4 Bit Prom
12
Programmable Logic Design Guide
"OR" ARRAY
(PROGRAMMABLE)
V
~
7
iV i'I
"AND" ARRAY
(FIXED)
Figure 2.3.3
PROM with 16 Words x 4 Bits
The FPLA
The Field-Programmable Logic Array (FPLA) overcomes some of the size restrictions of
PROMs because its designers recognized that not all product terms are required to
Programmable Logic Basics
13
implement most logic functions. By having a second fuse matrix (an AND matrix), the
FPLA allows the designer to select and program only those product terms used in each
specific function (Figure 2.3.4). These product terms are then combined in the OR fuse
array to form an AND-OR logic equation.
"OR" ARRAY
(PROGRAMMABLE)
~
V
7
~
,
~
-
,
"AND" ARRAY
(PROGRAMMABLE)
Figure 2.3.4 FPLA with 4 Inputs, 4 Outputs, and 16 Products
14
Programmable Logic Design Guide
In addition to specifying the number of inputs and functions, the FPLA manufacturer must also specify the number of product terms available, since there are less than
2n terms (with n as the number of input variables). The fact that the number of product
terms is less than 2n is what allows the FPLA to accommodate larger values of n, Le.,
more inputs. This is in contrast to the PROM where the number of product terms is
always equal to 2n.
Although the FPLA usually requires less fuses to implement a given logic function,
the additional fuse matrix does pose some difficulties of its own. The biggest problem
is the circuitry required to select and program these fuses - circuitry that is not used in
the final logic solution, but which is paid for in die area. This "chip overhead" cost is
not significant if the FPL~s capabilities are fully utilized, but it does become significant
for less complex problems that leave unused logic.
As has been shown, PROMs provide all of the product terms for a limited number
of input variables in generating AND-OR logic functions. FPLAs, on the other hand,
provide a limited number of product terms for a larger number of input variables. However, the FPLA is unrestricted in combining the product terms in the OR matrix, which
adds considerable flexibility to this device.
Because of the dual fuse matrix and the overhead cost of the circuitry required for
programming, the FPLA cannot be used economically in some low complexity logic
problems. The cost saving associated with the removal of the AND matrix (by
hardwiring it) is evident when one compares price. PROMs cost less than FPLAs. As
mentioned, however, the PROM approach significantly restricts the number of input
variables.
The PAL (Programmable Array Logic) Device
Savings similar to those of PROMs could be made without the penalty of restricting the
input variables, by removing the OR matrix from the FPLA, or hardwiring it. In the PAL
device concept (Figure 2.3.5), the AND fuse array allows the designer to specify the
product terms required. The terms are then hardwired to a predefined OR matrix to
form AND-OR logic functions.
An immediate observation is that because the OR gates in PAL devices are prewired, the degree to which the product terms can be combined at these OR gates is
restricted. PAL devices partially compensate for this by offering different part types that
vary the OR-gate configuration. Specifying the OR-gate connection therefore becomes
a task of device selection rather than of programming, as with the FPLA. With this
approach, PAL devices eliminate the need for a second fuse matrix with little loss in
overall flexibility.
Programmable Logic Basics
I
~
"OR" ARRAY
(FIXED)
I
V IV ~
.
"AND" ARRAY
(PROGRAMMABLE)
Figure 2.3.5
PAL Device Having 4 Inputs, 4 Ouputs, and 16 Products
15
16
Programmable Logic Design Guide
Comparison
To illustrate the difference among the three most popular field-programmable logic
concepts, the same four logic expressions will be solved with each, as shown in Figure
2.3.6(a). For comparison, each of the approaches is shown as an AND matrix, followed
by an OR matrix. The PROM solution shown in Figure 2.3.6(b) requires a 16-fuse
A
B
FUSIBLE OR
}-l--+-~---1-AB
LOGIC EQUATIONS
F1=A
F2=AB
F3=A+B
F4=AB+AB
)-l---Ji--t----1rAB
PROM
1--l......-+-..---1E-AB
HIt--+-....---1-AB
(a)
HARD AND
F1
F2
F3
F4
(b)
A
B
HARD OR
A
A
B
liD"
AB
FUSIBLE OR
"0"
A
PAL
A
AB
B
FPLA
B
AB
AS
AS
FUSIBLE AND
FUSIBLE AND
F1
F2
F3
F4
F1
(e)
F2
F3
F4
(d)
Figure 2.3.6 (a) Logic Equation, (b) PROM Solution, (c) FPLA Solution and
(d) PAL Device Solution
Programmable Logic Basics
17
matrix, whereas the FPLA and PAL device require 32 fuses each. If we were to add
another input variable, the number of fuses in a PROM increases to 32, while the FPLA
needs only 8 more and the PAL device needs 16 more. A fourth input again doubles the
number of PROM fuses to 64, but adds only 8 to the FPLA and 16 to the PAL device.
This example illustrates the previous statement that as the number of inputs increases,
PROMs consume more fuses than either FPLAs or PAL devices.
2.4
PROGRAMMABLE LOGIC VERSUS OTHER LSI, SEMICUSTOM AND CUSTOM
ALTERNATIVES
Logic designers are noticing an apparent "complexity gap" between TTL and LSI.
Products designed with discrete TTL devices would consume unacceptable amounts of
physical space and electrical power. Software-programmable LSI devices (microprocessors) offer high density and need relatively little power to operate. But the designer
pays a high price in software development and still has to use discretes to interface
them to the outside world. Until recently, there has been no device that provides a
really effective way of bridging this gap. National has seen this need, and now offers the
designer a family of PAL (Programmable Array Logic) devices to fill it. PAL devices offer
powerful capabilities for creating cost-effective new products or for improving the
effectiveness of existing logic designs. PAL devices save time and money by solving
many of the system partitioning and interface problems not otherwise effectively
solved by today's semiconductor device technology.
Standardized LSI
LSI (Large Scale Integration) offers many advantages, but advances have been made at
the expense of either device flexibility or software complexity. LSI technology has
been and still is leading to larger and larger standard logic functions. LSI offers high
functional density and low power consumption; single ICs now perform functions that
formerly required complete circuit cards. However, most LSI devices don't interface
with user systems without large numbers of support devices. Designers are still forced
to turn to random logic for many applications. LSI is slow, and it is rigidly partitioned.
For all its capability to perform varied and complex tasks, the microprocessor is a slow
and expensive way of doing simple, repetitive tasks when the necessary interface and
other support devices are added. And, when the time, money, and memory required
for software development are considered it is even more expensive.
Full Custom IC's
Custom IC's can be effective design solutions if the product is of low-to-medium complexity, its logic function is well-defined, and its market is high-volume. Its design cycle
is typically long, and its cost can be prohibitive. This tends to discourage its use.
18
Programmable Logic Design Guide
Gate Arrays
A close relative of the custom circuit is the gate array. With gate arrays, the total logic
capability of the chip, its pinouts, and its performance are predefined by the
semiconductor manufacturer. The user specifies only the logic interconnection pattern, a
process much the same as interconnecting standard small-scale integration (SSI) logic circuits. Since only a metallization pattern is required, the setup costs and turnaround time
for gate arrays are lower than for custom circuits, but because the designer can seldom
utilize the entire logic capability of the chip, the unit cost per active element is often
higher. The setup costs and turnaround time for gate arrays are conSiderably higher than
that for programmable logic, which has practically no turnaround delay.
3
Boolean Logic Review
3.1
BASIC OPERATORS AND THEOREMS
A gate is an electronic circuit which operates on one or more input signals to produce
an output signal. There are three basic gates from which all other logic can be realized:
AND, OR, and INVERTER gates. Figure 3.1.1 shows these three basic gates and their
truth table.
A
B
INPUT
0
F
0
0
1
1
(A) AND GATE
A
B
D
F
(B) OR GATE
A
A
I>
F
OUTPUT
F
0
0
0
1
1
INPUT
OUTPUT
A
B
F
0
0
1
1
0
1
0
1
0
1
1
1
INPUT
(C) INVERTER
Figure 3.1.1
B
0
1
0
OUTPUT
A
F
0
1
1
0
Basic Gates
To express the function of these gates by Boolean * algebra, we need
Boolean operators as follows:
=
+
•
: +:
:*:
to
define
Logical Equality
Negate (not, invert, complement)
OR (sum)
AND (product)
Exclusive OR
Exclusive NOR
19
20
Programmable Logic Design Guide
The function of an AND gate in Figure 3.1.1 can be expressed as:
F
= A. B
The function of an OR gate and INVERTER can be expressed as:
F
and
=A
+ B
F = A
Boolean operators are logical operators, which are different from arithmetic operators. For example, + is logical addition, • is logical multiplication. We call such equations Boolean equations or logic equations.
A number of logic theorems and laws will be used to manipulate and reduce logical
equations. These theorems and laws are as follows:
Theorem
Theorem
Theorem
Theorem
Theorem
Theorem
Theorem
Theorem
Theorem
Theorem
Theorem
Theorem
Theorem
a
A.a
1
2
3
4
A +
=
=
A + 1
=
A• 1
=
A + A
=
A.A
=
A+A
=
A.A
=
A
=
A + A. B
=
A(A + B)
=
(A + B).(A + C) =
A + A. B
=
5
6
7
8
9
10
11
12
13
A
a
1
A
A
A
1
a
A
A
A
A + B. C
A + B
Commutative Law
A+B
=B+A
A.B
=B.A
Associative Law
A + B + C = (A + B) + C = A + (B + C)
A • B • C = (A • B) • C = A • (B • C)
Distributive Law
A + (B • C • D) = (A + B) • (A + C) • (A + D)
A • (B + C + D) = A • B + A • C + A • D
DeMorgan's Theorem
(A + B + C)
(A • B • C)
=A.B.C
=A+B+C
• George Boole was the son of a shoemaker. His formal education ended in the third grade. Despite this, he was a hrilliant
scholar, teaching Greek and Latin in his own school, and an accepted mathematician who made lasting contributions
in the areas of differential and difference equations as well as in algebra.
Boolean Logic Review
21
The complement of any Boolean expression, or a part of any expression, may be
found by means of DeMorgan's theorem. Two steps are used to form a complement in
this theorem:
1. OR symbols are replaced with AND symbols or AND symbols with OR symbols.
2. Each of the terms in the expression is complemented.
DeMorgan's theorem is one of the most powerful tools for engineering applications. It is very useful for designing with programmable logic devices because it provides a quick and simple conversion method between PRODUCT-OF-SUMS and
SUM-OF-PRODUCTS expressions, which will be defined later.
3.2
DERIVATION OF A BOOLEAN EXPRESSION
Any logic expression can be reduced to a two-level form and expressed as either a
SUM-OF-PRODUCTS (SOP) or PRODUCT-OF-SUMS (POS). Before we define SOP or
POS, we need to define "terms."
1. Product Term - A product term is a single variable or the logical product of several
variables. The variable mayor may not be complemented.
2. Sum Term - A sum term is a single variable or the sum of several variables. The variables mayor may not be complemented.
3. Normal Term - A normal term is a product or sum term in which no variable
appears more than once.
4. Minterm - A minterm is a product term containing every variable once and only
once (either true or complemented).
5. Maxterm - A maxterm is a sum term containing every variable once and only once
(either true or complemented).
For example, the term A • B • C is a product term; A + B is a sum term; A is both a
product term and a sum term; A + B • C is neither a product term nor a sum term; A +
13 is a sum term; A • 13 • C is a product term; B is both a sum term and a product term.
We now define two most important forms:
1. SUM-OF-PRODUCTS Expression - A sum-of-products expression is a product term
or several product terms logically added together.
2. PRODUCT-OF-SUMS Expression - A product-of-sums expression is a sum term or
several sum terms logically multiplied together.
For example, the expression 1\ • B of A • B is a sum-of-products expression;
(A + B) • (1\ + B) is a product-of-sums expression.
22
Programmable Logic Design Guide
One prime reason for using sum-of-products or product-of-sums expressions is
their straightforward conversion to very simple gating networks. In their purest, simplest form they go into two-level networks, which are networks for which the longest
path through which a signal must pass from input to output is two gates long.
When designing a logic circuit, the logic designer works from two sets of known
values; the various states which the inputs to the logical network can take, and the
desired outputs for each input condition. The logic expression is derived from these
sets of values and the procedure is as follows:
1. Construct a table of the input and output values (Table 3.2.1 left half).
2a. To derive a SUM-Of-PRODUCTS (SOP) expression:
A product term column is added listing the inputs A, B, and C according to their
value in the input columns (Table 3.2.1). Then the product terms from each row
in which the output is a "1" are collected.
Therefore:
F =1\. B. C + 1\. B. C + A. B. C
(Eq. 3.2.1)
2b. To derive a PRODUCT-Of-SUMS (POS) expression:
A sum term column is added listing the inputs A, Band C according to their complement value in the input columns (Table 3.2.1). Then the sum terms from each
row in which the output is "0" are collected.
Therefore:
F = (A + B + C) (A + B + C) (1\ + B + C) (1\ + B + C) (A + B + C)
(Eq. 3.2.2)
Inputs
Outputs
A
B
C
F
Product Terms
Sum Terms
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
1
1
0
ABC
ABC
ABC
ABC
ABC
ABC
ABC
ABC
A+B+C
A+B+C
A+'B+C
A+B+C
A+B+C
A+B+C
A+B+C
A+B+C
1
1
1
Table 3.2.1
1
1
0
0
Truth Table of Eq. 3.2.1 and Eq. 3.2.2
Figure 3.2.1 is the logic circuit which direct derived from Eq. 3.2.1. Figure 3.2.2 is
derived from Eq. 3.2.2.
Boolean Logic Review
23
Eq. 3.2.1 can be simplified as shown below:
F =A. B • C + A • B • C + A • B • C
=A. B (C + C) + A • B • C
=A • B + A • B • C
=B(A+A.C)
=B(A + C)
=A.B+B.C
Eq 3.2.2 can be simplified as shown:
F=0+B+c)0+B+~~+B+C)~+B+~~+!+~
= (A + B) (A + B) (A + C)
=B(A + C)
=.i\.B + B.C
The two final expressions obtained are identical and can be implemented by' the circuit
shown in Figure 3.2.3. This is much simpler than the circuits in Figures 3.2.1 and 3.2.2.
This simplified procedure is called minimization.
!=
A~====:{~~---------
g::========~==~----------;:========~E::>-----F
i======t=)-----------1
Figure 3.2.1
A
B
C
A
B
c
A
A
!
A
!
B
C
-
Logic Circuits of Eq. 3.2.1
./
~
-
./
~
-
./
--"
./
I
I
- "'
~
~
Figure 3.2.2
Logic Circuits of Eq. 3.2.2
J
F
24
Programmable Logic Design Guide
Figure 3.2.3 Simplified Logic Circuits
3.3 MINIMIZATION
Logic circuits can be represented by logic expressions or so called logic equations. As
discussed, we can minimize the logic circuit through logic equations minimization. For
example, Figure 3.3.1 can be expressed by Eq. 3.3.1.
F
Figure 3.3.1
A Random Logic Circuit
(Eq.3.3.1)
F = (A. B • C + D) • (B + D) + A • C • (B + D)
By using the theorems and laws mentioned in 3.1, we minimize Eq. 3.3.1
as follows:
F
=
=
=
=
=
A.B.C + B.D + A.B.C.D + D + A.C.B + A.C.D
A • B • C (1 + D) + D (B + 1) + A • C • B + A • C. D Distributive Law
A• B• C + D + A• C • B + A•C • D
Theory 3
A • B (C + C) + D (1 + A. C)
Distributive Law
A. B + D.
Boolean Logic Review
25
The minimum SOP expression can now be implemented as the simple AND-OR
logic circuits as shown in Figure 3.3.2.
: -----LD~..----....,
D>-----
D
Figure 3.3.2
F
= AB+ D
Minimized Logic Circuit
We can use Boolean Algebra to reduce the number of product terms. However,
Karnaugh Mapping and the Quine-McCluskey method are two other powerful tools to
minimize the logic equations. We'll discuss Karnaugh Mapping method in the next
section.
3.4
K·MAP METHOD
A Karnaugh map, hereafter called a K-map, is a graphical method for representing a
Boolean function. It is similar to a truth table in that the K-map supplies the TRUE or
FALSE value of a Boolean function for all possible combinations of its logical argument.
There are many ways in which a K-map can be arranged. The most important considerations of the arrangement are:
1. There must be a unique location on the K-map for entering the TRUE/FALSE value of
the function that corresponds to each combination of input variables.
2. The locations should be arranged so, with minimization mentioned in Section 3.3,
that they are readily apparent to the trained observer.
The second consideration implies that a successful K-mapping arrangement should
point to groups of minterms or maxterms that can be combined into reduced forms.
K-maps are also useful in expanding partially reduced expressions into standard forms
prior to the minimization process.
The K-map is one of the most powerful tools at the hands of the logic designer. The
power of the K-map does not lie in its application of any marvelous new theorems, but
rather in its utilization of the remarkable ability of the human mind to perceive patterns
in pictorial representations of data. This is not a new idea. Anytime we use a graph
instead of a table of numerical data, we are utilizing the human ability to recognize
26
Programmable Logic Design Guide
complex patterns and relationships in a graphical representation far more rapidly and
surely than in a tabular representation. A few examples of how to create'a K-map
follow.
First, consider a truth table for two variables, We list all four possible input combinations and the corresponding function values, Le., the truth tables for AND and OR.
(Figure 3.4.1)
A B
0
0
1
1
0
1
1
0
A B
A·B
0
0
0
0
1
1
1
0
Figure 3.4.1
A+B
0
0
1
1
1
1
1
0
Truth Thbles for AND and OR
As an alternative approach, set up a diagram consisting of four small boxes, one for
each combination of variables, Place a "1" in any box representing a combination of
variables for which the function has the value 1. There is no logical objection to putting
"O's" in the other boxes, but they are usually omitted for clarity.
The diagrams in Figure 3.4.2(a) are perfectly valid K-maps, but it is more common
to arrange the four boxes in a square, as shown in Figure 3.4.2(b).
~B
00
01
11
'{B 00
10
I
11
01
I
A+B
(A)
A
B
0
A
1
B
1
1
0
0
1
0
1
1
1
1
A+B
(B)
Figure 3.4.2 K-maps for AND and OR
10
Boolean Logic Review
27
Since there must be one square for each input combination, there must be 2 n
squares in a K-map for n-variables. Whatever the number of variables, we may interpret
the map in terms of a graphical form of the truth table (Figure 3.4.3(a)) or in terms of
union and intersection of areas (Figure 3.4.3(b)).
The K-maps for some other three-variable functions are shown in Figure 3.4.4.
Particularly note the functions mapped in Figure 3.4.3(a) and 3.4.4(b). These are
both minterms. Each is represented by one square, obviously, and each one of the eight
squares corresponds to one of the eight minterms of three variables. This is the origin
of the name minterm. A minterm is the form of Boolean function corresponding to the
minimum possible area, other than 0, on a K-map. A maxterm, on the other hand, is the
form of Boolean function corresponding to the maximum possible area, other than 1,
on a K-map. Figure 3.4.3 (b) and 3.4.4 (c) are two examples.
A
B
A·B·C
C
AB
C
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
00
10
11
01
0
1
1
A·B·C
(a)
A
A
I
c
1
1
,
l' l i e
I
1
1
l'
1
B
B
A
A
I
,
B
B
A
+
B
+
C
(b)
Figure 3.4.3
K-Maps for 3-variable AND and OR
1
28
Programmable Logic Design Guide
A
AB
C
00
01
11
10
1
0
c
I I I' I' I
I
•
l
1
B
AC+AC
(a)
ABC
(b)
A
1
1
C
1
\
AB
•
I
•
\
C
1
1
0
1
1
1
00
01
11
10
1
1
1
1
1
I
C+AB
(d)
Figure 3.4.4 Sample 3-variable K-maps
Since each square on a K-map corresponds to a row in a truth table, it is appropriate to number the squares just as we numbered the row. These standard K-maps are
shown in Figure 3.4.5 for two and three variables. Now, if a function is stated in the
form of the minterm list, all we need to do is enter l's in the corresponding squares to
produce the K-map.
A
AB
0
1
0
0
2
1
1
3
B
Figure 3.4.5
00
01
11
10
0
0
2
6
4
1
1
3
7
5
C
K-maps for Two and Three Variables
If a function is stated as a maxterm list, we can enter O's in the squares listed or 1 's
in those not listed.
A map showing the O's of a function is a perfectly valid K-map, although it is more
common to show the 1's.
Boolean Logic Review
29
For example, the K-map of f(A, B, C) = m(O, 2, 3, 7) is shown in Figure 3.4.6 and
the K-map of f(A, B, C) = M(O, 1, 5,6) is shown in Figure 3.4.7. where m means minterm, M means maxterm.
AB
C
0
00
01
1
1
11
1
1
10
1
Figure 3.4.6 K-map of m(O, 2, 3, 7)
AB
C
00
0
0
1
0
01
11
AB
10
C
0
01
00
0
1
1
1
11
10
1
OR
0
1
Figure 3.4.7 K-map of M(O, 1, 5, 6)
As shown, the K-map can be generated from the truth table on minterm expression
or maxterm expression. For the remainder of this section, we will learn how to minimize the minterm expression by using the K-map.
The general principle of this minimization technique is "Any pair of n-variable
minterms which are adjacent on a K-map may be combined into a single product term
of n - 1 literals." The definition of "adjacent" should include opposite edges of the
K-map, for instance, Figure 3.4.8(a) and 3.4.8(b) both have a pair of adjacent minterms.
(a)
(b)
Figure 3.4.8 Adjacent Minterms on a K-map
30
Programmable Logic Design Guide
Consider this function
= m(O, 1, 4, 6)
= ABC + ABC
f(A, B, C)
+ ABC + ABC
Which results on the K-map, on the pattern shown in Figure 3.4.9
AB
01
00
C
0
r--
0
1
4
6
I
1
1
10
11
2
1
I
1
7
3
5
1
Figure 3.4.9 Minimization
Therefore, combine minterms 0 and 1, 4 and 6 to get a minimal expression:
= A13
f(A, B, C)
+ Ac
Figure 3.4.10 shows some examples. Notice that it is permissible to include a minterm in several terms if it helps make the term shorter.
AB
AB
00
CD
00
1
01
I
1
r-
01
11
-
10
II
1
00
CD
00
01
11
1
10
1
1
01
1
1
1
11
1
1
'--
10
11
1
10
1
Figure 3.4.10 Minimization
1
Boolean Logic Review
31
Quite often, some of the possible combinations of input values never occur. In this
case, we "don't care" what the function does if these input combinations appear. The
K-map makes it easy to take advantage of these "don't care" conditions by letting the
"don't care" minterms be 1 or 0, depending on which value results in a simpler expression. Figure 3.4.11 shows an example of the use of "don't cares" (redundancies) to simplify the terms.
cDAB
00
00
x
I
01
11
x
1
X
1
10
I
01
11
10
I
1
Figure 3.4.11
1
I
Minimization
When working with larger functions, the tabular reduction developed by Quine and
modified by McCluskey is an alternative to the K-map method. The Quine-McCluskey
minimization method involves simple, repetitive operations that compare each minterm that is present in a sun-of-minterms expression for a Boolean functions to all
other minterms with which it may form a combinable grouping.
The reader can refer to "Introduction to Switching Theory and Logic Design" by Hill
and Peterson to understand the Quine-McCluskey method.
3.5 SEQUENTIAL CIRCUIT ELEMENTS
Usually the subject of logic design is subdivided into two types: sequential and combinational. A purely combinational logic subsystem has no memory. Its outputs are completely defined by its present inputs. The analysis and design of combinational logic is
much easier. A sequential logic subsystem has memory and its outputs are functions of
not only present inputs but the previous outputs. Circuits of multiplexer/selector,
decoder/encoder, adder, and comparator are examples of combinational circuits. Shift
register, counter, state machine, and memory controller are examples of sequential
circuits.
32
Programmable Logic Design Guide
OATA -
~.r:-:l-
CLOCK--~
- -
-...
(21+ 1 = 0"
~ - ... (21+ 1 = (feQ + TeO)"
--~
--fl
0"
Q"+1
0
1
0
1
T"
Q"+1
0
Q"
(0)"
1
R
S
Q"+1
0
0
1
1
0
1
0
1
Q"
1
0
__ : [ j Q -"'a"+1=(J eO+j(eQ)"
J
K
Q"+1
--
C
--
K
0
0
1
1
0
1
0
1
Q"
0
Q
--
C
--
R
_ ... Q"+1= (S+AeSeQ)"
ReS* 1
Figure 3.5.1
X
1
(0)"
Basic Flip-Flops
Just as we have a logic gate as the basic combinational circuit element, we have a
flip-flop as a basic sequential circuit element. A flip-flop is a memory device which can
remember, or store, a binary bit of information. There are four basic flip-flop types: (1)
D flip-flop, (2) T flip-flop, (3) RS flip-flop, and (4) JK flip-flop. Figure 3.5.1 shows these
elements and their truth table.
With the memory elements, the output does not change as a function of the inputs
until the clock transition. Therefore, a superscript notation is used to indicate that the
output during clock period n + 1 is a function of the inputs during the previous clock
period n.
The D (delay) flip-flop means the input (D) is "stored" in the flip flop when the
clock occurs and will appear on the output (Q) during the next (n + 1) clock time. The
D flip-flop is thus very much like a single-bit RAM. It is very useful for data storage and
other special applications.
The other three types of flip-flops defined in Figure 3.5.1 are also one-bit storage
elements, but instead of simply storing the input, they change state in response to the
inputs by various logical rules. Since they hold their previous state in spite of the clock,
unless an input goes true, they often simplify the combinational logic functions
required to control them in control applications.
Boolean Logic Review
33
The T (toggle) flip-flop, for example, stays in its previous state if the T input is false
before the clock. If the T input is true, the output changes to the opposite state (toggle)
on the clock. The T flip-flop is thus useful, for example, in binary counters where we
want each bit to invert every time there is a carry from the lower order bits.
The R-S flip-flop sets after the S input is true and resets after the R input is true. Its
output is undefined if both Rand S are true. It is possible to define a Set Overrides Reset
(SOR) or a Reset Overrides Set (ROS) flip-flop. It will set or reset respectively if both the
R and the S inputs are true.
The J-K flip-flop sets after J is true and resets after K is true. It is similar to an R-S
flip-flop except that if J and K are both true, the output changes to the opposite state
(toggle). It can be used as a T flip-flop by tying the J and K inputs together.
Since theJ-K flip-flop can essentially do the job of both the R-S and the T flip-flop,
the R-S and the T flip-flops are seldom seen. The choice is between J-K flip-flops for
small counters and control or D flip-flops for data storage applications. Actually theJ-K
flip-flop can even do the job of the D flip-flop with the addition of a single inverter, as
shown in Figure 3.5.2.
J
D-
Q
---
K
Figure 3.5.2
Implement D Flip-Flop by Using J-K
Another memory element type, called a latch, is often described on data sheets with a
truth table like the one for the D flip-flop in Figure 3.5.1. It is definitely not like a D flipflop, however because the output changes as soon as the clock goes high and does not
"latch" until the clock falls (if the input changes while the clock is high, the output follow it). Because of this characteristic, a latch is not usable in the synchronous logic.
34
Programmable Logic Design Guide
3.6 STATE MACHINE FUNDAMENTALS
The relationships among present-state variables, primary input variables, next-state (or
excitation) variables, and primary output variables that describe the behavior of a
sequential system can be specified in several ways. As an example, consider the simple
sequential system that is shown in Figure 3.6.1.
11- - - - - - - - ( - - " " ,
I
J~------------------F
....----L,_~
y
~
12 _ _
v
-
~----------~J~~~---~
yl
DELAV
I
Figure 3.6.1
Iv
I
A Typical Sequential Circuit
This system has two primary input variables, having four different combinations of
values. There is one primary output variable and one state variable. It uses delay for
memory. There are only two possible present states: y = a and y = 1. When combined
with the four input combinations, these give eight different total present states. The
values of the next-state variable, Y, and the primary output variable, F, must be specified
for each total present state. The tabular arrangement shown in Table 3.6.1 is a common
method for presenting this information. This descriptive tool is called a state table.
NEXT-STATE
PRESENT - STATE
Y
0
1
V
1112 = 00 01 10 11
o
o
Table 3.6.1
1
o
OUTPUT
F
11 12 = 00 01 10 11
1
1 1 1
State Table
o
o
0
o
0
0 1 1
Boolean Logic Review
35
0,1/0
1, 1/0
0,1/0
Figure 3.6.2
State Diagram
A second method for describing the behavior of a sequential system is the use of a
state diagram. This method presents a pictorial representation of the
present-state/next-state sequences that apply to the sequential device. State changes are
marked with directed arrows, with the primary input and output conditions that apply
to each state transfer given beside the arrows. The state diagram for the system of Figure 3.6.1 is shown in Figure 3.6.2. A slash separates the input information from the output information.
State tables and state diagrams are essential tools in the analysis and design of
sequential digital systems. The reader should be familiar with these two tools by reading the references listed in the end of this section.
36
Programmable Logic Design Guide
Because a sequential system has feedback from its outputs to its input, certain
types of instabilities and uncertainties can occur. When present, these conditions make
the operation of circuit difficult or impossible to describe. They may even render the
circuit useless, since its behavior may not be predictable or consistent. Several of these
types of problems are listed below.
1) The input or output conditions of the system may be indeterminant. For example,
the circuit in Figure 3.6.3.
--'-1-f>o>-----1-
F
Figure 3.6.3 Example of Hazard Circuit
2) The output condition of the system may be unstable, changing even though the
external inputs do not change. Figure 3.6.4. illustrates an example.
-- "'
I
f
.......
.....
I
DELAY
Figure 3.6.4 Example of Unstable Circuit
F
Boolean Logic Review
37
3) The output condition of the system, even though stable, may not be predictable
depending upon the primary input conditions. Figure 3.6.5 is an example.
-
I
"-
-
.I
J-
.I
-"
f1
f2
I
I
I
I
Figure 3.6.5
DELAY
DELAY
I
I
I
I
Example of Circuit with Unpredictable Output States
However, these problems mentioned above can be avoided by making certain
restrictions in the way sequential systems are designed and used. For instance, the following are some restrictions:
1. Avoiding continuing instabilities (oscillations).
2. Allowing only fundamental-mode operation.
3. Allowing only pulse-mode operation.
References
Hill & Peterson "Introduction to Switching Theory and Logical Design"
Kohavi "Switching and Finite Automata Theory"
Rhyne "Fundamentals of Digital Systems Designs"
Krieger "Basic Switching Circuit Theory."
~,-",-,
4
The Programmable Logic
Family
National's programmable logic family consists of PAL devices and PROMs that come in
a variety of gate densities, pin-counts, architectures, speed and power specifications.
The following sections describe anj tabulate these var'ious options in addition to displaying the logic schematics.
4.1 BASIC GROUPS
The programmable logic devices are divided into two sections: one to address PAL
devices and the other to address PROMs.
4.2 THE PAL DEVICE FAMILY
The PAL device family is separated by pin-count and by architecture. There is a 20-pin
family and a 24-pin family. Each family contains simple combinational logic devices and
more complex devices which have on-chip feedback options and output registers. The
20-pin small PAL devices and the 20-pin medium PAL devices are listed in Table 4.2.1.
Part
No.
10H8
12H6
14H4
16H2
10L8
12L6
14L4
16L2
16C1
16L8
16R8
16R6
16R4
No. of
Inputs
No. of
Outputs
10
12
14
16
10
12
14
16
16
10
8
8
8
8
6
4
2
8
6
4
2
1
8
8
8
8
Table 4.2.1
No. of
1I0s
No. of
RegIsters
AND·OR
AND·OR
AND·OR
AND·OR
AND.NOR
AND·NOR
AND·NOR
AND·NOR
AND·OR/NOR
AND·NOR
6
2
4
Output
PolarIty
8
6
4
AND~OR
AND·OR
AND·OR
FunctIons
AND·OR Array
AND·OR Array
AND·OR Array
AND·OR Array
AND·OR.ln'vert Array
AND-OR·lnvert Array
AND-OR·lnvert Array
AND-OR·lnvert Array
AND-OR/AND·OR·lnvert Array
AND·OR·lnvert Array
AND-OR·lnvert Register
AND·OR·lnvert Register
AND-OR·lnvert Register
Members of the 20-Pin PAL Device Family
39
40
Programmable Logic Design Guide
The 24-pin PAL devices are listed in Table 4.2.2 and Table 4.2.3 shows how to read the
part numbers.
Part
No.
12L10
14L8
16L6
18L4
20L2
20L8
20L10
No. of
Inputs
No. of
1I0s
No. of
Registers
Output
Polarity
Functions
12
10
AND-NOR
14
16
8
6
AND-NOR
AND-NOR
18
20
14
4
2
2
2
AND-NOR
AND-OR Invert Gate Array
AND-NOR
AND-NOR
AND-OR Invert Gate Array
AND-OR Invert Gate Array
AND-OR Invert Gate Array
20R8
20R6
12
12
12
20R4
20X10
20X8
20X4
No. of
Outputs
6
8
8
6
2
12
4
4
8
6
4
10
10
10
10
8
4
2
10
8
6
4
Table 4.2.2
-
-
-
-
-
-
-
-
-
-
-
-
AND-NOR
AND-NOR
AND-NOR
AND-OR Invert Gate Array
AND-OR Invert Gate Array
AND-OR Invert w/Registers
AND-OR Invert w/Registers
AND-OR Invert w/Registers
AND-OR-XOR Invert w/Registers
AND-OR-XOR Invert w/Registers
AND-OR-XOR Invert w/Registers
Members of the 24-Pin PAL Device Family
-
-
AND-NOR
AND-NOR
AND-NOR
AND-NOR
AND-OR Invert Gate Array
-
-
-
-
-
-
-
-
PROGRAMMABLE LOGIC - FAMILY
PAL FOR PAL DEVICES
NL FOR NATIONAL MASKED LOG
PL FOR FACTORY PROGRAMMED PAL DEVICE
- NUMBER OF ARRAY INPUTS
-
-
-
-
-
-
-
-
-
-OUTPUT TYPE:
H = ACTIVE HIGH
L = ACTIVE LOW
C = COMPLEMENTARY
R=REGISTER
X = EXCLUSIVE-OR WITH
REGISTER
P = PROGRAMMABLE
OUTPUT POLARITY
-
-
NUMBER OF OUTPUTS
-
-
SPEED RANGE
NO SYMBOL = STANDARD SPEED
A = HIGH-SPEED
A2 = HIGH·SPEED, HALF·POWER
B = ULTRA HIGH SPEED, ETC.
--11-
PACKAGE TYPE:
N = PLASTIC DIP
.
J = CERAMIC DIP
V = PLASTIC LEADED CHIP CARRIER
TEMPERATURE RANGE:
c=o TO +75 DEG. C
M= -55 TO +125 DEG. C
PAL16L2'
AN
Thble 4.2.3
C
PAL Device Part Number Interpretation
The Programmable Logic Family
41
PAL Devices For Every Task
The members of the PAL device family are listed in Tables 4.2.1 and 4.2.2. They are
designed to cover the spectrum of logic functions at lower cost and lower package
count than SSIIMSI logic. This allows you to select the PAL device that best fits your
application. PAL devices come in three basic configurations; Gates, Register Outputs
With Feedback, and Programmable I/O.
Gates
PALs are available in sizes from 12 X 10 (12 inputs, 10 outputs) to 20 x 2, with either
active-high or active-low output configurations. One part has complimentary outputs.
This wide variety of input/output formats allows the PAL to replace many
different-sized blocks of combinational logic with single packages.
Register Options With Feedback
High-end members of the PAL device family feature latched data outputs with rp.gister
feedback. Each Sum-Of-Product term is stored in a D flip-flop on the rising edge of the
system clock. (See Figure 4.2.1) The Q-output of the flip-flop can then be gated to the
output pin by enabling the active low TRI-STATE© buffer.
In addition to being available to transmission, the Q-output is also fed back into
the PAL array as an input term. This feedback allows the PAL device to "remember" its
prior state. And, it can alter its function based upo~ that state. This allows one to configure the PAL device as a state machine that can be programmed to execute elementary
functions such as count up, count down, skip, shift, and branch.
INPUTS, FEEDBACK AND 1/0
CLOCK
....
p..--,
....
Figure 4.2.1
E
:001-
"
./
I...
.A
~~
~
....
PAL Device Output Register Circuit, Simplified Logic Diagram
Q
42
Programmable Logic Design Guide
Programmable I/O
Another feature of the high-end members of the PAL family is programmable
input/output. This allows the product terms to directly control the outputs of the PAL
device. (Figure 4.2.2) One product term is used to enable the TRI-STATE buffer, which
in turn gates the summation term to the output pin. The output is also fed back into the
PAL device array as an input. Thus, the PAL drives the I/O pin when the TRI-STATE gate
is enabled. The I/O pin is an input to the PAL device array when the TRI-STATE gate is
disabled. This feature can be used to allocate available pins for I/O functions or to provide bidirectional output pins for operations such as shifting and rotating serial data.
INPUTS, FEEDBACK AND 1/0
J--d
......
1/0
...
~
~
Figure 4.2.2
PAL Device Bidirectional Circuit, Logic Diagram
PAL Device - Speed/Power Groups
PAL devices are available with various speed/power specifications. For easy reference,
these are summarized in Tables 4.2.4 and 4.2.5.
20-Pln Small PAL
Devices
20·Pin Medium PAL Devices
10H8, 12H6, 14H4,
16H2, 10L8, 12L6, 14L4,
16L2, 16C1
16L8, 16R8, 16R6, 16R4
TAA Max
(ns)
Icc Max
(mA)
TAA Max
(ns)
Tsu Min
(ns)
TCLK Max
(ns)
Icc Max
(mA)
Standard
35
90
35
35
25
180
A Series
25
90
25
25
15
180
180
6 Series
-
-
15
15
12
A-2 Series
35
45
35
35
25
90
6-2 Series
-
-
'25
*20
*15
'90
'Preliminary information.
Table 4.2.4
20-Pin PAL Device Speed/Power Groups
The Programmable Logic Family
20Ll0
20Cl,20L2,
18L4, 16L6, 14L8,
12Ll0
20Xl0, 20X8, 20X4
43
20L8,20R8,20R6,20R4
TAA Max Icc Max Tsu Min TCLK Max Icc Max TAA Max Icc Max TAA Max Tsu Min TCLK Max Icc Max
(ns)
(rnA)
(ns)
(ns)
(ns)
(rnA)
(ns)
(rnA)
(ns)
(rnA)
(ns)
Standard
50
165
50
30
180
40
100
-
-
-
-
A Series
30
165
30
15
180
*25
*100
25
25
15
210
20
20
15
210
BSeries
Table 4.2.5
24-Pin Speed/Power Groups
PAL Device Logic Symbols
The logic symbols for each of the individual PAL devices gives a concise functional
description of that device. Figure 4.2.3 shows a typical logic symbol, that of the lOH8
gate array.
PAL10H8
Figure 4.2.3
Logic Symbol, PALlOH8
44
Programmable Logic Design Guide
PAL10H8
PAL12H6
PAL14H4
PAL16H2
PAL16C1
PAL10L8
PAL12L6
PAL14L4
PAL16L2
Figure 4.2.4 PAL Device Logic Symbols - Series 20
The Programmable Logic Family
PAL16L8
PAL16R8
PAL16R6
PAL16R4
Figure 4.2.4 PAL Device Logic Symbols - Series 20 (Contd.)
45
46
Programmable Logic Design Guide
PAL12L10
PAL14L8
PAL16L6
PAL18L4
PAL20L2
PAL20C1
PAL20L10
PAL20 x 10
PAL20x8
PAL20x4
PAL20R4
Figure 4.2.5
PAL20R6
PAL20L8
PAL Device Logic Symbols -
PAL20R8
Series 24
The Programmable Logic Family
47
4.3 THE PROM FAMILY
National's broad PROM family extends from a 32 x 8 bit (256 bit) PROM to a 4096 x 8
bit (32K) PROM. Only the low density byte-wide PROMs are considered here for programmable logic applications. The products in this category are shown in Table 4.3.1.
Part
No.
No. of
Outputs
No. of
Product Terms!
Output
No. of
Pins
TAA Max
(ns)
Density
No. of
Inputs
748288
256 Bit (32 x 8)
5
8
32
16
35
110
87X288B
256 Bit (32 x 8)
5
8
32
16
15
140
74L8471
2K (256 x 8)
8
8
256
20
60
100
74L8472
4K (512x8)
9
8
512
20
60
155
748472A
4K (512 x 8)
9
8
512
20
50
155
748472B
4K (512 x 8)
9
8
512
20
35
155
748474
4K (512 x 8)
9
8
512
24
65
170
748474A
4K (512 x 8)
9
8
512
24
45
125
748474B
4K (512 x 8)
9
8
512
24
35
170
878R474
4K (12x8)
9
8
512
·24'
35
185
878R476
4K (512 x 8)
9
8
512
24'
35
185
878R25
4K (512 x 8)
9
8
512
·24'
35
185
Military versions are also available. Above data is commercial.
'24 Pin Narrow Dual·In-Line Package
Table 4.3.1
PROM Configurations
Icc Max
(rnA)
48
Programmable Logic Design Guide
Size
(Bits) Organization
DIP
Part
TAA
TEA
ICC
Temperature
(Pins)
Number
(Max.)innS
(Max.) innS
(Max.)inmA
Celsius
-5510 +125
32 x 8 Standard PROMs
256
OC
OC
16
DM54S188
45
30
110
32x8
16
DM74S188
35
20
110
010+70
32x8
TS
16
DM54S288
45
30
110
-5510 +125
32x8
TS
16
DM74S288
35
20
110
010+70
32x8
32 x 8 Ultra High-Speed PROMs
256
32x8
TS
16
PL77X288
20
15
140
-5510 +125
32x8
TS
16
PL87X288
15
12
140
010+70
256 x 8 Standard PROMs
2048
256x8
TS
20
DM54LS471
\ 70
35
100
-5510+125
256x8
TS
20
DM74LS471
60
30
100
010+70
-5510+125
512 x 8 Standard PROMs
4096
OC
OC
20
DM54S473
75
35
155
512x8
20
DM74S473
60
30
155
010+70
512x8
TS
20
DM54S472
75
35
155
-5510 +125
512x8
TS
20
DM74S472
60
30
155
010+70
512x8
20
DM54S473A
60
35
155
-5510 +125
512x8
OC
OC
20
DM74S473A
45
25
155
010 +70
512x8
TS
20
DM54S472A
60
35
155
-5510 +125
512x8
TS
20
DM74S472A
45
25
155
010 +70
512x8
TS
20
DM54S472B
50
35
155
-5510+125
512x8
TS
20
DM74S472B
35
25
155
010 +70
512x8
24
DM54S475
75
40
170
-5510 +125
512x8
OC
OC
24
DM74S475
65
35
170
010 +70
512x8
TS
24
DM54S474
75
40
170
-5510 +125
512x8
TS
24
DM74S474
65
35
170
010+70
512x8
24
DM54S475A
60
35
170
-5510 +125
512x8
OC
OC
24
DM74S475A
45
25
170
010+70
512x8
TS
24
DM54S474A
60
35
170
-5510 +125
512x8
TS
24
DM74S474A
45
25
170
010+70
512x8
TS
24
DM54S474B
50
35
170
-5510 +125
512x8
TS
24
DM74S474B
35
25
170
010 +70
-5510 +125
512x8
512 x 8 Registered PROMs
4076
512x8
REG 24"
DM77SR474
40**
30
185
512x8
REG 24"
DM87SR474
35"
25
185
010+70
512x8
REG 24"
DM77SR476
40**
30
185
-5510 +125
512x8
REG 24"
DM77SR25
40"
30
185
-5510 +125
512x8
REG 24"
DM87SR476
35"
25
185
010+70
512x8
REG 24"
DMB7SR25
35"
25
185
010 +70
" 300 mil wide package.
"" Sel·up lime.
Table 4.3.2 PROM Products for Logic
49
The Programmable Logic Family
Q1
16
Q2
2
15
E1
Q3
3
14
A4
Q4
4
13
A3
32x8
AD
Al 2
20
Vee
A1
2
19
A7
A2
3
18
A6
A2 3
AO
Vee
A3
4
17
A5
A3 4
A4
5
16
E2
A4 5
6
15
E1
01 6
02
03
04
256x 8
512
x8
Q5
5
12
A2
Q1
Q6
6
11
A1
Q2
7
14
Q6
Q3
8
13
Q7
Q4
9
12
Q6
10
11
Q5
24
Vee
A7 I
24 Vee
2
23
Ag
A6 2
23 AB
22
PS
A5 3
22 Ne
21
G
A4 4
21 EI
Q7
7
10
AO
GND
8
9
Q8
24
A7
As
As
2
3
512 x 8 23
REG. 22
A4
4
21
GND
Vee
A7
Ag
NC
As
As
3
G
A4
4
512 x 8
REG.
GND 10
E2
A3
5
INIT(CLR)
A3
5
INIT (CLR)*
A3 5
2D
6
...j:!
20
A2
ffi
19
Gs
A2
6
A2 6
19 E3
A1
7
::::
::;;
C
18
CK
A1
7
GS
CK
07
AD B
17 OB
01 9
02 10
03 II
16 07
15
14 06
GND 12
13 04
Ao
8
17
Ao
07
8
00
9
16
Os
00
9
16
Os
01
10
15
Os
01
10
15
Os
02
11
14
04
02
11
14
04
GND
12
13
03
GND
12
13
03
Figure 4.3.1
AI 7
512 x 8
IB E4
05
PROM Logic Symbols
Note:
All of the virgin devices come with their fuses intact. But for the sake of simplicity, the
fuse-linked crosspoints in the array are shown unconnected.
4.4
LOGIC DIAGRAMS
The following pages show the logic diagrams of the PAL device and PROM family of
programmable logic devices. The logic diagrams are ordered in the following
sequence:
PAL Devices:
Figures 4.4.1-4.4.13 (20-pin PAL devices)
Figures 4.4.14-4.4.27 (24-pin PAL devices)
PROMs:
Figures
4.4.28-4.4.32
50
Programmable Logic Design Guide
Inputs (0-31)
01] 1
46
1021
2425
28193031
1
I>
-
19
-
18
0
1
2
-
L?
,•
3
L>
"
-
24
--.c
11
17
4
L>
15
5
16
~
15
12
]]
6
~
"
7
14
-
40
.
~
....
8
....
13
_
.
.z
12
-
""
9
-a.?
0123
.5
.,
<
1213
Figure 4.4.1
1611
2021
2425
2829]0)1
Logic Diagram PAL lOH8
11
The Programmable Logic Family
51
Inputs (0-31)
.
--1.>2
II
...
I
I
II
I
I
I
I
I
.A
19
....
I
!
.,
J
, '"
18
/
""
'-'
!
3
~
!
17
"
"
~
4
.JI:
I
M
""
<0
I
e
til
E
5
~
I
16
~
.
tl
~
"'C
!:!
.....,
-
15
""
.
-
14
Q.
6
>.
"
7
I
>.
.."
J
-u-T
"
'"
13
./
I
12
8
>.
9
'I
.
....
.>-
Figure 4.4.2
Logic Diagram PALl2H6
11
52
Programmable Logic Design Guide
Inputs (0-31)
a
1 2l
4 fli
1
.,1GII
lDll2211
14152&n
ZIUIDl'
----I>
2
----I>
-3
.
....
19
18
4
-
~
...
.""
J
"
-
,"
....
...
J
""
- ,"
.
...
J
17
J
5
~
""
"
-
6
,
........
16
15
./
L?
...
..
1
"
\
7
13
Lol'
8
14
J
OJ
~
...
12
~
11
9
012 J
• 5 11
',IDII
un
Figure 4.4.3
IIIl
20212213
UZS1'lJ
'I IIlDII
Logic Diagram PAL14H4
The Programmable Logic Family
53
Inputs (0-31)
o
1
1 i J
4 ~ 6 I
B ~ 10 11
1213\415
2
3
16111 B 19
2021
n 21
142~
2621
28293031
I
I
2
19
2
~
IL
. 5.
18
4
17
~
24
"
""
16
M
I
e.
en
"
11
to
Ja
5
E
~
16
./
JI
~
~
"
II
U
l4
"C
J\
16
Ci.
39
:::I
o
"
JI
"
6
15
14
-.5..
7
8
9
13
2
-.5.
L
5.
IA?'
'So
12
11
o 1 2 3
4 56 J
8 g10n
'213141~
16171819
20112223
24252621
2B29n31
Figure 4.4.4 Logic Diagram PAL 16H2
-
54
Programmable Logic Design Guide
INPUTS (0-31)
1
2
19
~
18
4
17
~~16
5
~
t::i
15
6
14
7
13
8
12
9
11
o ,
1 l
.,
i'
8 9
10 11
11 "
,."
Figure 4.4.5
'''7 1119
1011 111J
11/, Iill
"I~ JO 3.
Logic Diagram PAL16Cl
The Programmable Logic Family
55
Inputs (0-31) )
01
Zl
4&
1213
1111
20Z1
ZtZS
282!l031
1
i..;>
,
.....
19
I
2
---v
18
,
I
3
----I>
1&
11
0
17
4
I..?
16
""
5
I..l'
.--..
""
15
6
----I
..
7
.
14
"
...
8
.....
13
-
12
.
.
"
9
11
----I>
~
0123
45
"
1213
1617
21121
2425
2&293031
Figure 4.4.6 Logic Diagram PALlOL8
56
Programmable Logic Design Guide
Inputs (0-31)
0.2 J
'511
.,
~
2
.
.A
---i
I
.
-
-
""
3
J
"
19
18
./
\
I
17
""
4
...
16
"
"
5
--
31
"
15
6
~
.
---
"
14
7
-----t.JA
J
..
II
-
sa
"
"
13
./
\
8
12
.....
...,
9
----t
--~
a
1 Z]
4511
.1
lOU
!4Ul121
21 H lOll
Figure 4.4.7 Logic Diagram PAL 12L6
11
The Programmable Logic Family
57
Inputs (0-31)
0123
•
2a21
557
nil
14252621
un:;Oll
~
2
~
19
3
<;.
4
18
.,;,
~
}
"""
"
-
17
........
./
\
5
~
.
}
"
-
\
-
}
,.""
-
"
6
-U
.
16
........
"
II
./
15
0
\
J
-
""
"
7
14
0
\
~
<
IJ
~
~
~
13
12
8
11
9
0, 2 1
'5' J
•
9 1011
1113
Figure 4.4.8
102121U
HHl6l1
Hl!llOll
Logic Diagram PAL14L4
58
Programmable Logic Design Guide
Inputs (0-31)
0\ 2 J
1
"Ii 6 1
B SID"
12131415
161118\9
2021h21
24252627
----I>
2I2930Jl
I
2
19
2
~
3
----tZ
18
~
4
17
~
5
..
----I
""
""
"""
"
-.....
16
./
31
""
15
""
""
"
./
6
14
~
5.
L.?
~
l2'
~
~
~
7
13
8
9
12
11
o 121
"!i'
7
• 11011
12131.,5
Figure 4.4.9
unlll1
2021Z121
24252121
21293031
Logic Diagram PAL16L2
The Programmable Logic Family
59
Inputs (0-31)
Dill
.. 511
• '1011
1213'415
nUllu
20212221
24252521
2un031
•
,,
,•
•,
~
..
" J
1
2
..
~
,,
"
"
""
11
./
IJ
3
..
19
18
"'"
A
~
11
11
11
4
..
:>-J
"""
""
...
.1-
-----1~
c;;eo
I
eli)
5
..
E
'tI
E
"J1
7
~
""
6
---t.
.
..
".""
...
~
"
>J
"
51
...
15
14
"'1-
....
8
16
A
,.""
"""
tl
:::s
-
JJ
----I
~
IL
,.
"""
""
17
.""
13
~
"
----I
51
.."
>--J
51
9
...
""
""
..
o
1 Z 1
.. 5 i 1
.91011
12131415
Figure 4.4.10
1&171819
20212223
2&252&21
28293031
Logic Diagram PAL16L8
12
11
60
Programmable Logic Design Guide
Inputs (0-31)
0123
456)
89\011
I,I]141J
161]101,
5
3
~
S
""
""
"13
"""
10
./
11
4
.
>.
...
~
~
~
~
~
~
~
~
~
~
~
~
14
1\
16
"""
"I.
./
19
JO
11
5
...
.>.
31
J3
"35
"
"""
37
3B
6 ..
"
"
..
"
""
"""
44
./
0\
""
7 ..
-t~
'"
""
10
;,
51
53
""""./
50
5\
8
.>.
~
15
57
58
19
""'"
""
./
61
9
"
....>.
.c
0121
4 S fi)
8 9 lOll
111j:~I~
161JI819
Figure 4.4.11
101110J
""~lbll
nin03!
Logic Diagram PAL 16R8
D~
~~,,,
0-
~
The Programmable Logic Family
61
Inputs (0-31)
1
CK~
ell J
4
~
,
I
191011
II 1J "
1~
I~
II " 19
:,
14
l~
11 11
11 1! ]0 31
>iJ
,
·,,,
SR
1011 11 II
~
·
""
"
"
""
~
,,"""
""'"
./
H
4
01
.>
CD
I
e.
'"
E
~
O2
"-...
""
"
""
"'"
"
c;;5
"
./
~
"
""
'0
""
""
""
::I
'C
~
C.
03
6
"
../
~
..
"
..""
.."
"
./
"
7
..?
LlRO
£1
./
"
3
19
~
"
8 ..
"
./
,c
~
....
""
~
""
'"
9
SL
""
"
--j~
Figure 4.4.12
Logic Diagram PAL 16R6
18
NJ
~0
~
~
~
~
~
.."
""
"
""
-.:L
v
~
~
14
~
13
-yo--
1
-yo-- -
12
RILO
~
62
Programmable Logic Design Guide
Inputs (0-31)
012
J
456
J
S
~
10 I'
11111415
16 II 18 19
1011212)
H II 16 21
lilt 3D 11
:,
~
~
..,,
,
~
,
.,,
"
"
"
""
3
~
""
"
""
"
""
4
<:
"
""
"
""'"
"
CD
I
e.
Ul
E
.!!
5
"'"
-f::'
~
1;
"
"""
"""
"
~
'C
o
D:
6
./
.,
"
".."
..
"""
./
"
7
::.
'"
..
"
"""
"
\I
8
::.
""
"
"'"
""
9
.
18
~~
./
~
M
19
"
~
456
J
i
91011
12131415
16111819
Figure 4.4.13
101111n
H 251121
a191031
~
~
Logic Diagram PAL16R4
~
~
~
~
~
~
......
13
12
~
The Programmable Logic Family
o
1 2 J
..
~
1
.,
63
Inputs (0-39)
1213
1617
2D21
2425
2829
32JJ
363138U
~
0
1
~
2~
V<>--
22
,•
""lJ"
3
':r
16
17
21
~
4
20
"
25
5
~
31
33
6
..f}.
40
18
41
7
..
~
49
17
~
8
..f}.
56
16
"
9
?-
64
"
15
~
0
?-1
"
7J
14
~
1
0123
.. 5
.,
13
~
1213
1617
2021
2425
2829
3233
Figure 4.4.14 Logic Diagram PAL12LlO
36373839
64
Programmable Logic Design Guide
Inputs (0-39)
0123
"567
1
••
n13
1617
2129
2021
3Z 33 3"35
3631:J8 39
~
23
••
~
22
~
10
11
3
'"h
16
17
21
<>-
~
4
-n-n~
""
5
~
32
J3
19
:)--L
6
~
.,"
7
....
~1
17
~
8
16
:e:c>o--
"
57
9
.
.."
--<
-o-r
67
10
11
15
14
13
0123
4567
8 •
1213
1617
Figure 4.4.15
2021
2425
2819
32333435
Logic Diagram PAL14L8
36373839
The Programmable Logic Family
Inputs (0-39)
01 Z 3
4567
1
a
91011
1213
1611
2021
ZU5
2829303'
32333435
36373139
2
23
-3
22
~
'h
16
17
21
18
19
~
-4
-n.
"2S
5
""
)..
32
31
':(
."
.....
20
19
~
6
J
18
-
7
..
I>-{)--1
50
51
17
8
...f).
"
"
51
58
9
16
}.
15
0
14
11
13
0123
4567
a
9101'
1213
1617
Figure 4.4.16
2021
2425
28293031
323334:15
Logic Diagram PAL 16L6
3637383a
65
66
Programmable Logic Design Guide
INPUTS (0-39)
0123
4567
891011
12131415
1&11
1
,."
2
~
3
23
4
22
5
21
"
25
20
26
27
r-l)o-
28
6
"
32
19
3J
}.
"
J5
""
7
~
""
~~
..
rrr-
49
"
51
52
8
53
17
16
9
15
0
14
11
13
0123
4567
891011
12131415
1617
Figure 4.4.17
21121
24HH27
282930~
32J3~fi
Logic Diagram PAL18L4
~37~n
The Programmable Logic Family
Inputs (0-39)
D 1 23
1
4$&1
Ilion
IZU"~
161711'9
m~n~
NnHU
HH~~
nn~u
R~RH
2
23
3
22
4
21
~
20
5
32
33
6
7
.
."
19
.
...""
...
18
""
"
17
"
8
16
9
15
0
14
1
13
D123
f561
1110H
nUU15
WIT'."
Figure 4.4.18
mnnn
~UH27
HH~~
nUMU
Logic Diagram PAL20L2
anUB
67
68
Programmable Logic Design Guide
Inputs (0-39)
0123
1
2~
23
3
22
4
21
5
20
....,
J2
33
34
35
J6
J7
J8
6
19
J9
40
18
41
"
."
""
05-
7
17
8
16
9
15
10
14
11
13
0 ' 23
4567
891011
1213141516171819
Figure 4.4.19
2021222324252627
Z829W31
~J3343S
Logic Diagram PAL20C 1
~31~39
The Programmable Logic Family
69
Inputs (0-39)
o
1 2 3
.4 567
B 91011
12131415 16171819 20212223
2425262728293031
32333435 36373839
~
0
1
1
3
j-)
~
Jv
23
.J
...
22
...J
21
2.n-'u~
8
9
10
11
>-L
3
~
16
17
18
19
l-L
""l.J"+
4
14
15
16
17
~
31
33
34
35
~
A
20
"-V-
~
5
~
~
A., 19
... "'"
6
~
40
41
>-~
41
-J
18
J
17
.J
...
16
...
43
""l.J"~
48
49
50
51
-tJ--f-" ...
7
-
~
8
--j
~
>--L
56
57
58
59
i...J"""f"
9
64
65
66
67
f~5
~
10
~
71
~~
73
74
-t
75
14
...
13
11
~
o 1 2 3
4 5 6 7
8 9 1011 121J 1415 16171819 20212223
24252627 28293031
J233 34 35 36373839
Figure 4.4.20 Logic Diagram PAL20LlO
70
Programmable Logic Design Guide
INPUTS (0-39)
...
"0123
-4567
B 91011
1213141516111119
20212223 24252627 28293031 32333435 36373839
~
....
~9D ~I.l
0
I
,
2
23
Q
~
,
B
D
;::;.
10
11
3
17
~
"";1 21
~D
16
;::,
1B
19
!;
"";1 2 2
4
,2--L9D
24
25
26
~I
e-
27
5
rn
::E
II:
~
t:I
40
41
:~D
J._
....
6
42
43
~
18
~
I.L
17
=9 ~
Q
16
~
48
.
~ ~D
"
50
51
&
~
"
""
57
D
54
65
;::;.
"
67
~D
01
~
...
"";11 5
.....
"~D~r:!
72
73
74
75
19
I.J......
7
9'
'""J.... 2o
I.L
D
=9 ~
C
a..
....
"
"
34
3S
o
II:
~
...
14
~
3
1
0123
4567
8910111213141516171819202122232425262728293031 3233343536373839
Figure 4.4.21
Logic Diagram PAL20XlO
The Programmable Logic Family
..
INPUTS (0-39)
D 1 2 3
.. 5 Ii 7
• 11011 12131415 16171'19 20212223 24252127 21213031 32333435 36373139
~
0
I
2
3
~
~
3
~
16
17
;::..
18
19
4
5
I
e
32
33
34
35
6
:I
Q
oa:
21
20
M
~DM
9D-M
~DM
19
~~
40
41
IL
22
'"J.
;::::;
26
27
l-
9D-Mh...
9D-M.
;. 9D- h.
25
I:)
I
~
24
:::!l
a:
w
23
I.l
9
11
III
...J
-U9D-~v
•
10
f
71
42
43
7
.
49
;::..
50
51
8
"
57
58
59
hv
17
h...
16
h...
15
~
9
.."
~
;::..
"
67
0
9D~
~
72
73
"
75
~
.I....
14
~
1
D 1 23
.. 5 Ii 1
a 91011
12131.15 16171819 2D212223 24252127 21293031 323334:15 3&31Sl39
Figure 4.4.22
Logic Diagram PAL20X8
72
Programmable Logic Design Guide
INPUTS (0-39)
.......
0123
4 567
891011 12131415 1&171819 20212223 24252627 28213031 32333435 36373839
~
0
1
2
3
~
~
B
-4-
9
10
11
~
3
......
16
17
18
19
~
4
......
24
25
5
;::::.
""
.J
~
I
23
.J
I
22
~
~
21
.. J
9D ~""
Q
:=9~
32
33
34
35
~
~
~
--;:J.
...
18
9r>~
';t
17
6
40
41
~r>
"
43
7
.
.......
49
50
8
;::::.
"
56
57
58
59
J..-L
~
9
......
64
65
66
61
.J
.. I
.J
~
10
......
72
73
74
75
.J
I
.. I
11
0123
4567
8910"
12131415 16171819 20212223 2425262728293031
Figure 4.4.23
32333435 36373839
Logic Diagram PAL20X4
~
...
16
15
14
3
~
The Programmable Logic Family
73
Inputs (0-39)
20L8
0123
~
4567
a9m1.
UUM~
unRW mnun NHSU
aH~~
U~M~
J
I
.J......
......
J
21
J
"
.J......
20
J.
19
J
18
J
17
"'"
..L
.....
16
"'"
......
J
15
~~YH
c
••
10
11
12
3
",.
"
23
r-
22
-~
"
""
17
4
2D
21
22
23
-~
""
"
""
Z7
3D
5
./
31
32
33
34
""
"
37
3B
'6
".,
"
"
...
42
7
y
J
./
"'"
......
""
......
47
..
"
--I~
8
"""
"II
./
C
--I~
51
"
""
51
11
9
--I
""
~
..
"
""
8'
"
II
0
J
71
--I~
11
.J
c
c
14
13
TUU5598·10
Figure 4.4.24 Logic Diagram PAL20L8
74
Programmable Logic Design Guide
Inputs (0-39)
0123
~
4567
89Wl1
Un14~
16171819
~nn~
U~~V
~n~~
~n~~
~~~~
'"
"
8
9
10
11
12
./
"
14
3
15
~
23
I-;J.
~~
11:
16
17
18
"
19
"21
4
./
"
23
~
1;
24
~
25
"27
"
28
./
29
3D
31
5
",.
r;-
ID
.!
........
3S
"
"
./
37
III
E
~
tG1
~1
r;J.
39
~~
u:::I
1;;
4D
43
,
45
./
41
..."
'tI
e
D..
47
7
~
1;;
48
,
49
"
51
52
53
./
"
55
8
~
"
57
58
59
60
51
........
./
62
9
63
--i~
~"
65
."
"
67
./
"
10
71
10
--i~
20
~
32
e-
22
~
~
~
~8
r;J.
~
~
17
~
r;J.
16
rvo-
1.J..1 5
QJ
~
14
11
--i~
0123
4567
a9ro~
U131415
~U~19
~nnn
Figure 4.4.25
~~Hn
HH~~
nnM~
~~~~
Logic Diagram PAL20R8
3
~
TUU5598·13
The Programmable Logic Family
75
Inputs (0-39)
1
D 123
~
4517
II~"
n13M~
UflUU mnnn
~D~V
Da~~
D~M§
.U • •
23
~
••
"",.
3 "
,2
~
10
11
""
.."
22
r.J..
11
11
""'"
20
4
,/
"
,.,
.2
""
"
""
5 .."
.......
27
ZI
./
,.>
."
,
33
35
II
17
"
,/
31
II
~~
."
..."".
"
~.>
..
,
J
"
../
"
"
"""
""
~~
"
.
"'/
..
.""
...
51
57
"
9
.>
~
"IIII
10
71
10 ~
11
,2
~
D1Z:J
4117
limn IZUMU .,l0U mnun HaHn
Hn~~
UD~~
Muau
a~
~
~
Ct....
19
I,l
....
18
n
~
~
ttl
21
~17
....
~
15
14
13
TUU5S98-12
Figure 4.4.26 Logic Diagram PAL20R6
76
Programmable Logic Design Guide
20R4
~
"" ,,23
~
4567
89rol1
1213"'5
1617~19
w~n~
M~UU
~n~~
~n~35
~D~~
23
B
9
~
""
"
1Z
14
3
15
-t.2
",.
~
17
19
2D
21
4
"
23
-t.2
24
25
26
"
2B
29
I
21
J
'"
M~
""'. /"
~
~
~
~~
./
30
5
22
31
--I
""
34
35
36
37
3B
6
39
- t .2
4D
41
.,
..
43
""'"
./
45
47
7
~
~
4B
49
""
""
'"
./
54
8
55
11:
~
"
"""
"
57
62
9
"
.
.
"
~
65
56
67
70
10
~
~
'!!t~
,
0123
4561
89rol1
1213"'5
161718H
~~un
~~~27
HH~~
~nM~
~
~
363738311
cQ
~
~
16
15
14
~
TUU5598-11
Figure 4.4.27
Logic Diagram PAL20R4
The Programmable Logic Family
A4
v
A3
A2
A1
6
1
P6
V
AD
.
77
PROGRAMMABLE "OR" ARRAY'
I
\
AAA3 A2Ai AU
AAA3 A2Ai AD
AA A3 A2 A1 AU
AA A3 A2 A1 AD
AAA3A2A1AU
AAA3 A2A1 AD
AA A3 A2 A1 AU
AA A3 A2 A1 AD
AAA3A2AiAU
AAA3 A2 Ai AD
AAA3 A2 A1 Jiii
AAA3 A2 A1 AD
AAA3 A2 Ai AU
AA A3 A2 Ai AD
AA A3 A2 A1 AU
25
AND GATES
AA A3 A2 A1 AD
A4 A3 AZA1 AU
A4 A3 A2 Ai AD
A4A3AZA1 AU
A4A3AZ A1 AD
A4A3A2AiJiii
A4 A3 A2 Ai AD
A4A3A2A1 Jiii
A4A3A2A1 AD
A4A3AZA1Jiii
A4 A3 A2 Ai AD
A4 A3 A2 A1 AU
A4 A3 A2 A1 AD
A4 A3 A2 Ai AU
A4 A3 A2 Ai AD
A4 A3 A2 A1 AU
A4 A3 A2 A1 AD
FIXED "AND" ARRAY
GENERATING ALL 25
PRODUCT TERMS
G
* OR array is shown with all fuses blown
.......
~~
Q7
r2 r2 ~ ~ ~ ~7
Q6
Q5
Q4
Q3
Q2
Q1
QD
TL/L16747-3
Figure 4.4.28 32 x 8 PROM Logic Diagram
78
Programmable Logic Design Guide
b
~
~
~
b
~
~
~
~ ~ ~ ~ ~~ ~V ~ ~
I I I I I I I I I I I I I I I
28
AND
GATES
I I I I I I I I I I I I I I I
I I I I I I I I I I I I I I I
I I I I I I I I I I I I I I I
I I I I I I I I I I I I I I I
FIXED AND ARRAY
GENERATING ALL 28
PRODUCT TERMS
Figure 4.4.29 256 x 8 PROM Logic Diagram
The Programmable Logic Family
I I I I I I
29
AND
GATES
I I I I I I
I I I I I I
I I I I I I
I I I I I I
I I I I I I
I I I I I I
I I I I I I
I I I I I I
I I I I I I
FIXED AND ARRAY
GENERATING ALL 29
PRODUCT TERMS
Figure 4.4.30
512 x 8 PROM Logic Diagram
79
80
Programmable Logic Design Guide
SR476/SR25
~
b
~
~
~ ~~ ~ ~
29
AND
GATES
~
b
¢ ~~
~
~
~
~ ~ ~
111111111111111111
I I I I I I I I I I I I I I I I I I
I I I I I I I I I I I I I I I I I I
I I I I I I I I I I I I I I I I I I
I I I I I I I I I I I I I I I I I I
I
I,
I
I
I
FIXED AND ARRAY
GENERATING All 29
PRODUCT TERMS
iNiT~
INITIALIZE WORD
(ClR)--v--------t
Ps
ClK
T
L
t
t
t
t
t
t
t
a-BIT
EDGE-TRIGGERED REGISTER
GS-
Figure 4.4.31
512 x 8 Registered PROM Logic Diagram
t
The Programmable Logic Family
SR474
~
29
AND
GATES
I
I
I
I
I
I
I
I
I
I
1FJ
~ ~ ~
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
~ 1~
P~
I I I I I I I I I I I I I
I I I I
I I
I
I I
I
I I I I
I I
I I I I
I
I
I I
I I I I
I I I I I I I I
FIXED AND ARRAY
GENERATING All 29
PRODUCT TERMS
INITIALIZE WORD
ClK
Figure 4.4.32
512 x 8 Registered PROM Logic Diagram
81
5
How to Design with
Programmable Logic
There are two design objectives to keep in mind when using programmable logic
devices. The first objective is to use the programmable logic device to replace discrete
chips in the existing product. Each device will be able to replace 3 to 8 TTL chips. The
second objective is to design the programmable logic device into the new/next generation product.
Each design is different. But the procedures are similiar. Figure 5.0 shows a typical
design sequence.
DEFINE
THE
r--~
PROBLEM
SELECT
THE
DEVICE
r--
WRITE
THE
LOGIC
EQUATION
PROGRAM
THE
DEVICE
-~
TEST
THE
DEVICE
Figure 5.1.1 Design Sequence of the Programmable Logic Device
The design sequence can also be viewed as a set of five questions: (1) How do I
define the problem? (2) How do I select the logic device? (3) How do I write the logic
equations? (4) How do I program the device? (5) How do I test the device?
5.1
PROBLEM DEFINITION
First, we need to know the function of the logic circuit. Is it used for generating combinational control signals, decoding addresses/operation codes, or multiplexingidemultiplexing signals? Is it used for counting or shifting bits, generating different control
sequences, or implementing a state machine for any usage?
83
84
Programmable Logic Design Guide
Then we can decide on the type of logic circuit. Is it combinational, sequential or
mixed? Table 5.1.1 shows the typical combinational and sequential circuits and the PAL
devices that can be adapted.
Typical Circuits
PAL Devices Used For
COMBINATIONAL
Decoder/encoder, multiplexer, adder, memory mapped I/O,
strictly signal combination (no latch).
10H8, 12H6, 14H4, 16H2,
10l8, 12l6, 14l4, 16l2,
16C1, 12l10, 14l8, 16l6,
18l4, 20L2, 16L8
SEQUENTIAL
Counter, shift registers, accumulator,
Control sequence generator
16l8, 16R8, 16R6, 16R4,
20l10, 20X10, 20X8,
20X4, 20l8, 20R8, 20R6,
20R4
Table 5.1.1
Typical PAL Circuits
5.2 DEVICE SELECTION
The next question is, which PAL device should we choose to optimize space and cost?
To answer this, we first need to calculate the number of inputs and outputs of the logic
circuits being designed and decide on the outputs' polarity: active-low or active-high.
For example, if there are 10 input and 7 output signals and the majority of outputs are
active-low, then the best choice is the lOL8. If the number of outputs are six, then we
can use either the lOL8 or 12L6. Since each PAL device has limited product terms, we
need to know how many product terms each output uses. The number of product
terms each output will use can be viewed from logic equations. For instance, the logic
equation of 01 = PI + P2 + P3 + p4 + P5 will use five productterms for the output 01.
Fortunately, National's software, PIAN, will help the user to select the right PAL device.
See chapter 6 for a discussion of PLAN.
Table 5.2.1 shows National's 20 pin PAL device configurations and Table 5.2.2
shows the 24 pin PAL devices.
How to Design With Programmable Logic
Max Propagation Delay (ns)
110 (and ClK to Output)
Series
B
Icc
Max
(mA)
No. of
Data
Inputs
85
No. of Outputs
and Configurations
PAL
Complexity
(1)
Standard
Series
A
10H8
208
35
25
90
10
8x=8:D-
1018
208
35
25
90
10
8x=8:D-
12H6
208
35
25
90
12
4x=8:D-2X$-
1216
208
35
25
90
12
4x=8:D-2X~
14H4
208
35
25
90
14
4X$-
1414
208
35
25
90
14
4X$-
16C1
208
35
25
90
16
'"~
16H2
208
35
25
90
16
2X.
16L2
208
35
25
90
16
2X.
1618
20M
35
25
15
180
16-10
6X1Er2X~
16R4
20M
35/25
25/15
15/12
180
12-8
4"br4"!Er
16R6
20M
35/25
25/15
15/12
180
10-8
16R8
20M
35/25
25/15
15/12
180
8
Table 5.2.1
'"br'"!Er
8X!ttt
20 Pin PAL Device Configuration
86
Programmable Logic Design Guide
Max Propagation Delay (ns)
1/0 (and ClK to Output)
Series
B
Icc
Max
(mA)
No. of
Data
Inputs
PAL
Complexity
(1)
Standard
12110
248
40
100
12
10x=&:D-
1418
248
40
100
14
6x=&:D-2x~
1616
248
40
100
16
2x=&:D-4x~
1814
248
40
100
18
2X~2X~
20C1
248
40
100
20
2012
248
40
100
20
20L10
24M
50
165
20-12
8X~2X~
20X4
24M
50/30
180
16-10
4X~6X~
20X8
24M
50/30
180
12-10
8X~2X~
20X10
24M
50/30
180
10
(1) Complexity:
20 = 20-Pin PAL
24 = 24 Pin PAL
Series
A
No. of Outputs
and Configurations
1.:r
2X.
1O.~r-
8 = 8mall PAL
M = Medium PAL
Thble 5.2.2
24 Pin PAL Device Configuration
How to Design With Prograounable Logic
5.3
87
WRITING LOGIC EQUATIONS
Writing logic equations from an existing combinational circuit is straightforward.
Examples are given in Chapter 3. Also, the generation of logic equations for a new
design combinational circuit is quite simple. The procedures are as follows:
1. Define the inputs and outputs.
2. Generate the Truth Table.
3. Use the techniques mentioned in Section 3.2 to get the SOP expression for each
output.
4. Use the minimization techniques mentioned in Section 3.3, Le., Boolean Algebra, KMap or the QUine-McCluskey method to minimize every SOP expression.
5. These four steps result in the logic equations.
Figure 5.3.1 shows these steps:
KARNAUGH MAPS OR
BOOLEAN ALGEBRA
DEFINE INPUTS
AND OUTPUTS
FUNCTIONAL
DESCRIPTION .. -
-
- ..
TRUTH
TABLE
"'" _ _ _ ~
--
-----Figure 5.3.1
...
(PROGRAMMING THE PAL DEVICE)
TRANSFER
FUNCTION "'" _ _ _ _
(LOGIC
-EQUATIONS)
CIRCUITS
(PAL)
DEVICE
FUNCTION
TABLE
Combinational PAL Device Design Steps
It is much more complicated to generate logic equations for a sequential circuit.
Generally, the procedures are as follows:
1. Define the inputs and outputs, different states and variables.
2. Generate the state diagram.
3. Generate the state table.
4. Minimize the state table.
88
Programmable Logic Design Guide
5. Assign the new state.
6. Generate the transition table.
7. Use the minimization technique to minimize transition table.
8. These seven steps result in the logic equations.
Figure 5.3.2 shows these seven steps.
MINIMIZING THE
STATE TABLE
FUNCTIONAL
DESCRIPTION - -
-
..
STATE
DIAGRAM
STATE
ASSIGNMENT
-
~-
-.
STATE
TABLE
KARNAUGH MAPS OR
BOOLEAN ALGEBRA
TRANSITION ______ .-..
-------..
TABLE
r--
------+
Figure 5.3.2
5.4
~ -
-
MINIMAL
- . STATE TABLE -
-
..
(PROGRAMMING THE PAL DEVICE)
TRANSFER
FUNCTION
..
(LOGIC
---EQUATIONS)
CIRCUITS
(PAL)
DEVICE
FUNCTION
TABLE
Sequential PAL Device Design Steps
PROGRAMMING THE DEVICE
Given the logic equations, the PAL device programmer will manage the programming
job for us. All we need to do is to enter those logic equations into the terminal. The
programming procedures are shown in Figure 5.4.1.
After programming, the fuse status should be verified. Most programmers will provide this fuse verification capability.
Manually coding the programming format sheet, which has appeared in National's
1983 PAL Device Data Book will not be discussed in this Design Guide.
How to Design With Programmable Logic
ENTER
LOGIC
EQUATIONS
~
EXERCISE
FUNCTION TABLE
INTO LOGIC
EQUATION
(SIMULATION)
ENTER
FUNCTION
TABLE
89
...
CREATE
BIT PATTERN
-
TEST PAL's
FUNCTION
WITH TEST
VECTORS
f--;+-
ANOTHER'
LOGIC
TEST
I-
IF NO FUNCTION TABLE AVAILABLE
...
LOAD PATTERN
INTO
PROGRAMMER
--
PROGRAM
FUSE
MATRIX
-
VERIFY
FUSE
MATRIX
~
.....
BLOW
- . SECURITY FUSE
IF WANT
• FOR EXAMPLE: DATA 1I0's FINGERPRINT TEST.
Figure 5.4.1
5.5
PAL Device Programming Procedures
TESTING THE DEVICE*
Fuse verification tells us if the fuse was blown correctly or not; but it doesn't tell us if
the PAL device functions properly. Therefore, we also need to do functional testing.
There are two ways to do functional testing. One method uses function tables. Another
method uses test vectors. Each of these methods may give a different result.
Function tables are generated without reference to the logic equations. The function table tells what the PAL device should do. Function tables are used to determine if
the device functions as intended. If it does not, we have to go back to the equations,
since there may be a problem there.
Test vectors are generated directly from the logic equations. They are used to verify
the internal operation of the PAL device. If a problem is detected, it implies that something is internally wrong with the device. However, a device may pass the test vector
screening and still not function properly if the logic equations were derrived incorrectly.
It is the logic designer's responsibility to generate the function table. This is the
person who best knows the design. After the design is released, the test engineer will
• Also see Cbapter 7 for details about testing.
90
Programmable Logic Design Guide
take the responsibility for testing incoming devices. As mentioned before, the function
table can't catch all the interior bugs. Therefore, the test engine,er needs to write the
test vectors. It is a large and sophisticated job to create test vectors. Figure 5.5.1 shows
these steps and will be explained in chapter 7. There are a few software packages available for generating test vectors, for example; HILO!, and TEGAS 2 , LOGCAp3, LAZAR4.
LOGIC
EQUATIONS -
S-A-O TEST FOR EACH PRODUCT TERM
S-A-1 TEST FOR EACH PRODUCT TERM
S-A-1 TEST FOR EACH LOGIC EQUATION
~
Figure 5.5.1
TEST
VECTORS
Test Vectors Creating Steps
5.6 PROGRAMMER VENDOR LIST
Mfgr.
Basic
Equipment
PALDevice
Module
PAL
Device
DeslgnSoftware
Adapters Included
Performs
Logic
Simulation
Storage Media for
Programs
Bit
Pattern
Test
Vectors
20Pin
24Pin
Blows
Security
Fuses
No
No
Master
PAL
-
Yes
No
No
20+24
Pin
Socket
Yes
No
Master
PAL
+
Yes
Yes
Yes
MOD 21
SA27+
SA 27·1
No
No
Master
PAL
-
Yes
Yes
Yes
PM 202+
BRAL
AM10H8
Yes
No
Master
PAL
-
Yes
No
Yes
No
No
Master 7
PAL,
PROM,
EPROM
PROM
Yes
Yes
Yes
Data 1/0
Model 19,
19Aor
100A
1427
Digelec
,.p 803
FAM 51
Kontron
EPP 80 or
MPP80S
Stag
PPX
1428·1
·2
-3
·•
•
AM16Cl
Citel
System 47
PL1
All these systems program and verify the PAL in the PROM mode. They do not perform a logic simulation in the PAL device
mode. Additional (external) circuitry for logic simulation should be used if PAL devices go into volume production - otherwise, a
small percentage of the PAL devices will show failures when testing the complete PC board. OK for prototype-making.
Table 5.6.1
1.
2.
3.
4.
PAL Device Programmers
BILO is a registered trademark oj Gen Rad.
TEGAS is a registered trademark oj CDC.
LOGCAP is a registered trademark oj Phoenix Data Systems.
LAZAR is a registered trademark oj Teledyne.
How to Design With Programmable Logic
Mfgr.
Data 10
PALBasic
Device
Equipment Module
PAL
Device
DesignSoftware
Adapters Included
91
Storage Media for Programs
Performs
Logic
Simulation
Blows
Bit
Pattern
Test
Vectors
20Pin
24Pin
Security
Fuses
Master
PAL
or
External
or
Yes
Yes
Yes
Model 19.
29Aor
100 and
Any
Terminal
LogicPack
I'P 803
FAM 52
20- and
24-Pin
Adapter
Yes
Yes,
Automatic
or Manual
Generation
01 Test
Vectors
Master
PAL
External
Yes
Yes
Yes
-
ZL30
-
Yes
Yes,
Automatic
or Manual
Generation
01 Test
Vectors
Master
PAL
External
Yes
Yes
Yes
Structured
Design
Any
Terminal
50201
24
-
Yes
Yes,
Manual
Generation
01 Test
Vectors
Master
PAL
or
External
or
Yes
Yes
No
Structured
Design
Any
Terminal
S01000
-
Yes
Yes,
Manual
Generation
01 Test
Vectors
Master
PAL
or
Yes
Yes
Yes
Oigelec
Stag
Design
Ad. and
Progr.
Yes
Ad.
Yes.
Automatic
or Manual
Generation
01 Test
Vectors
EPROM
On Walertape
External
or
EPROM
All these systems allow software supported PAL device design. They perform a fuse-verify in the PROM mode and can do a
logic simulation in the PAL device mode. All 5 programmers and 5 development systems can be connected with a host computer to run more sophisticated design software and/or lor storage use.
Table 5.6.2
PAL Device Development Systems
92
5.7
Programmable Logic Design Guide
EXAMPLES
Example 1: Replace the existing logic circuit in Figure 5.7.1 by a PAL device.
12 C>--+------l~,--------o 02
-L-'>---------o 03
130-_..-_ _ _
C>------±---I"--""\
15
18 C>------+---1......J
170--..----+------1
18
~---o()Os
C>--+----.t----I"--""\
19
1--........- ' ) 0 - - - - 0 0 8
11 0 0 - - - - - - - 1
Figure 5.7.1
DeSign Example, Logic Diagram
We will follow the procedure discussed in this chapter. We know the first step is to
understand the function of this circuit. There is no register and latch involved. By
experience, we understand that this circuit is used to manipulate different input Signals
and generate different outputs. We should select the combinational PAL device (Le.,
PALIOH8, PALIOL8, PAL12H6, etc.).
The second step is to choose the specific device. Because the number of inputs is
10 and the number of outputs is 6, we limit our choice to be IOH8, 10L8, 12H6 and
12L6. Three outputs have AND-OR functions and 3 outputs have AND-OR-INVERT
functions. We could still select from either active-high or active-low (H or L) parts.
Since the more complex functions are AND-OR-INVERT, the active LOW (L) series is
most likely. Therefore, we now limit our choice to the IOL8 and 12L6 devices. A review
of the IOL8's logic diagram shows that all of its NOR gates are two-input gates, and the
design example requires a three-input gate. On the other hand, the 12L6 has two 4input gates which will accommodate the 3-input requirement. It, therefore, is selected.
The third step is to write the logic equation. It is very straightforward for this
example.
How to Design With Programmable Logic
93
We get:
01
III
02 = III * 12
03 = II + 13
04 = /(113 * 14)
Os = /(113 * Is * 16 + 17 + Is * 19)
06 = / (Is * 19 + /13 * II7 * 19 * 110 )
Since we have selected a PAL12L6 (which has inverting outputs) we need to apply
DeMorgan's theorem to convert tl1ese equations from active-high to active-low outputs. DeMorgan's theorem can be used to convert any logic form to the AND-OR or
AND-NOR structure used in PALs. Applying DeMorgan's theorem gives the active LOW
form of the equation:
10 1 = II
102
II + 112
1°3
III * 113
10 4
113 * 14
105
113 * Is * 16 + 17 + Is * 19
106
Is * 19 + 113 * 117 * 19 * 110
Assuming that there are no board layout constraints, input II through rIO may be
assigned to pins 1 through 11 (pin 10 is ground). The only constraint on output pin
assignment is that 0 s must be assigned to pin 13 or 18 to take advantage of one of the 4input NOR gates.
The fourth step is to program the PAL device. To do this we must enter the logic
equations into the computer or the PAL device programmer. National's PLAN software
allows users to enter logic equations in any format. But PALASM requires the program
shown in Figure 5.7.2 in its host computer to be used as follows:
Line
Line
Line
Line
Line
Line
Line
Line
Line
Line
Line
Line
Line
Line
Line
Line
Line
Line
1
PAL 12L6
2
PAT201
3
PAL DESIGN EXAMPLE
4
5
11 12 13 14 15 16 17 18 19 GND 110 NC 05
6
0604030201 NC Vee
7
8
101 11
9
102 11 + 112
10 103 111 • 113
11 104 113 • 14
12 106= 18.19+/13./17.19.110
13 105 113 • 15 • 16 + 17 + 18 • 19
14
15 DESCRIPTION
16
17 THIS PROGRAM IS A DESIGN SAMPLE DESCRIBING
18 THE USE OF PALASM AS A PAL DESIGN AID.
=
=
=
=
=
Figure 5.7.2
Example of PALASM Program Input
- ..
94
Programmable Logic Design Guide
Line 1:
At the left margin, the PAL device is specified. For this example, the 12L6
remains the best solution, therefore entering PAL12L6 at the left margin.
Line 2:
A unique pattern number for this PAL device design is entered at the left
margin on Line 2, followed by designer's name and date.
Line 3:
The name or description of the device or function is entered. If this runs
over one line, Line 4 may be used to complete it.
Line 4:
If not used to complete Line 3, this line is skipped.
Lines 5, 6, These lines are used for pin assignments. All 20 of the pins on the PAL are
assigned symbolic names, usually corresponding to the symbols used on
and 7:
the logic diagram. (Note that GND and Vee must be included.) Assignment
starts at pin 1 and proceeds sequentially, through pin 20.
Line 8:
Beginning on Line 8 or Line 6, if only Line 5 is needed for the pin assignments, the logic equations that describe the required functions are written
using the symbols defined in Lines 5, 6 and 7. in the format applicable to
the PAL device selected. For example, the output of the 12L6 is low for the
selected product term; therefore, the logic equations must be of the form
lOx = f(11' 12 ",,), The symbology used must be that shown in Figure 5.7.3.
EQUAL
REPLACED BY, FOLLOWING CLOCK
I COMPLEMENT
• AND. PRODUCT
+ OR, SUM
:+: XOR
.•. XNOR
( ) CONDITION TRI-STATE IF STATEMENT, ARITHMETIC
._
Figure 5.7.3
PALASM Operators
Then the PAL device software will generate the fuse map and bit pattern shown in
Table 5.7.1, load pattern into programmer, program the device and verify the fuse
matrix. Since there is no function table in this example, we need to do another logic
test to guarantee it works properly. For example, we can do the fingerprint test if we
already have a known good device, or we can generate a few (or whole) test vectors to
do the structure test in a DATA I/O programmer.
How to Design With Programmable Logic
8
9
10
11
16
17
--xxxxx
xxx x
xxx x
xxxx
xxxx
xxxx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xx
xx
xx
xx
xxxx
xxxx
xx
xx
xx
XXX,X
xxxx
X---
X--X-X-
--X-
24
25
-x----x
xxxx
xxx x
32
33
xxxx
xxxx
40
41
48
49
50
51
xx
xx
xx
95
-X--
-X--
X-
xx
-x
-X--X--
xxxx
xxxx
xx
x-
x-
xx
xx
Table 5.7.1
X-
xx
X---
xxxx
X---
xxxx
Fuse Map
Figure 5.7.4 is the logic diagram of this PAL device and Figure 5.7.5 shows the PAL
device legend.
Example 2: Design a multiplexer to select one of three input data buses which contain
4 data lines, as shown in Figure 5.7.6. The output should be high if we don't select any
data bus.
From Figure 5.7.6 we know there are 14 input lines and 4 outputs. Since we select
one out of three, we need 3 product terms in each output. In addition, we need
another product term to implement diselection which will cause all output-high. From
the PAL device select chart (Table 5.2.1) we find 14H4 is the best fit.
The logic equation is very easily derived from intuition or we can get from the
truth table shown in Table 5.7.2.
PLAN software will help us to select the device, assign pinouts, and generate a fusemap. All we need to do is enter the logic equations.
Yl
/SELA * /SELB * Al + SELA * /SELB * B1 + /SELA * SELB * C 1 + SELA *
SELB
Y2
/SELA * /SELB * A2 + SELA * /SELB * B2 + /SELA * SELB * C2 + SELA *
SELB
Y3
/SELA * /SELB * A3 + SELA * /SELB * B3 + /SELA * SELB * C3 + SELA *
SELB
Y4
/SELA * /SELB * A4 + SELA * /SELB * B4 + /SELA * SELB * C4 + SELA *
SELB
-.
..
~
96
Programmable Logic Design Guide
I
2
.
I
19
I
...
"
J
\
NC
18
". /
3
p
I
""
2
4
17
I
,.......,
,.
3
"
16
I
5
I
--"'"'
""
4
15
6
.,
5
"
14
7
I
...
-""" J
"
"
-
6'
./
13
\
,
8
9
12
..
NC
11
~
Figure 5.7.4 Logic Diagram of the National Type 12L6 PAL®
How to Design With Programmable Logic
PAL Legend
Constants
LOW(L)
NEGATIVE (N)
ZERO (0)
GND
FALSE
HIGH (H)
POSITIVE (P)
ONE (1)
Vee
TRUE
Operators
x -+- --+-
FUSE NOT BLOWN
FUSE BLOWN
EQUAL
REPLACED BY FOLLOWING CLOCK
/
COMPLEMENT
* AND, PRODUCT
+ OR, SUM
:+: XOR
:*: XNOR
( ) CONDITIONAL THREE STATE, IF STATEMENT, ARITHMETIC
:=
Equations
°101
Standard
PALASM
111;+~ 12
Il*/I2 + /Il*I2
Conventional Symbology
PAL Device Symbology
--
LOGIC STATE
FUSE
BLOWN
HLLH
Vee
INPUT
HIGH --..~--+....
Fl!SE
NOT BLOWN
INPUT
LOW
H
PRODUCT WITH ALL
' - FUSES INTACT REMAINS
LOW ALWAYS
SHORTHAND NOTATION
~A~FUSES nTT~
PAL Logic Diagram
ACTIVE HIGH THREE·STATE ENABLE
INPUT LINE NUMBER
0111
PROD UCT
LINE
NUM BER
r
;
:
:
I \ 6 I
~
1 IU I I
III II II ~
I ~ II I H iii
/0 /1/111
14 1\ Ib II
/H
I~
JQ II
};Ef
R---r ""
~
P IN
NUM BERS
/"
~CKt
J
~1
F
f:' ~
./
(
Figure 5.7.5 PAL Legend
~
19
STANDARD SU M OF PRODUCTS
T THESE NODES
(BEFORE TH E BUBBLE)
'!UATED.
R
~~
18
97
98
Programmable Logic Design Guide
EN
UP/DOWN
.....
EN
UP/DOWN
CLK
BCD
COUNTER
4~
BCD
COUNTER
4/
BUS A
/
BUSB
/
BUSC
4/
/
....
i..-
2 I:---
,
SELECT
Figure 5.7.6
A1 A2 A3 A4
A1 A2 A3 A4
X X X X
X X X X
X X X X
MULTIPLEXER
W-
~
DECODER
DRIVER
7-SEGMENT
DISPLAY
Block Diagram of a Multiplexer
B1 B2 B3 B4
X X X X
B1 B2 B3 B4
X X X X
X X X X
C1 C2 C3 C4
X X X X
X X X X
C1 C2 C3 C4
X X X X
Table 5.7.2
SELA SELB Y1
L
A1
L
H
L
B1
L
H
C1
H
H
H
Y2
A2
B2
C2
Y3
A3
B3
C3
Y4
A4
B4
C4
H
H
H
Truth Table
We can replace 2 of 74S153 in this application.
The Function Table and logic diagram are shown in Table 5.7.3 and Figure 5.7.7.
A1 A2 A3 A4
L L .L L
X X X X
H
H
B1 B2 B3 B4
X X X X
X X X X
X X X X
X
X
X
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
X
X
X
X
C1 C2 C3 C4
X X X X
X X X X
X X X X
X X X X
L L L H
L L H L
Table 5.7.3
SELA SELB Y1 Y2 Y3 Y4
L
L
L L L L
H
H
L
H
L
L
H
H
H
H
H
H
H
H
H
L
L
H
H
L
L
L
L
L
H
H
H
H
H
L
Function Table
How to Design With Programmable Logic
99
Inputs (0-31)
2011 Hll
~ .... ~
an2ln
lIl!lGll
~
C4
A2
.5.-
C3
A1
~
....
"
""
"
84
1
,
,
Y4
./
~
... J ,
.
"
II
11
-
.... J ,
,.""
- ,
"
83
..
...
~
81
.
,
--"'"
-
"
1
Y3
Y2
./
,
Y1
./
\
C2
.'S..
C1
~
~
~
SEL8
SELA
'"io.
"ll
Figure 5.7.7
4 SI J
'11'11
IltJ
'In
ullun
24nUn
JllIlll1
Logic Diagram of the National Type 14H4 PAL Device
~,.
100
Programmable Logic Design Guide
Example 3: Design a 3-bit counter which causes only one bit change for each change
of state shown in Figure 5.7.8. A RESET input will initialize the counter to 000.
The PAL device under design is used for a 3-bit counter with only one input line,
RESET. When active, it will reset all three flip-flops. Obviously we can use a 16R4 to
implement this application.
A
B
C
0
0
0
0
0
-
0
0
0
REPEAT
0
0
0
0
0
0
0
0
0
Figure 5.7.8
an _____ an+ 1 '
-
3-Bit Counter
0
0
K
X
S
0
T
----~
0
0
R
0
X
0
0
----~
1
1
1
X
1
0
1
0
0
X
1
0
1
1
1
1
X
0
X
0
0
1
1
- - - - .......
- - - - .......
J
·an , an + 1 STAND FOR PRESENT AND NEXT STATE; X IS DON'T CARE.
Thble 5.7.4 Transition Lists
How to Design With Programmable Logic
101
We can easily write the transition table for this simple example as shown in
Table 5.7.5.
ClK
R (RESET)
An
Bn
cn
An+1
Bn+1
Cn +1
t
t
t
t
t
t
t
0
0
0
0
0
0
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
0
0
1
0
1
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
1
0
1
0
1
1
0
0
0
1
0
0
0
0
0
1
X
X
X
0
0
0
t
t
Table 5.7.5
Transition Table
We can get the logic equation from Table 5.7.5 by K-map minimization technology
as shown in Figure 5.7.9.
AB
cR
AB
00
01
11
cR
10
AB
00
01
11
10
CR
00
01
11
10
0
00
0
I1
1
0
00
~
0
l2J
0
0
0
01
0
0
0
0
01
0
0
0
0
0
0
0
11
0
0
0
0
11
0
0
0
0
0
11
1
10
II 1
1
0
0
10
r1l
0
f1l
0
00
0
111
1
01
0
0
11
0
10
0
I
A
I
I
B
C
Figure 5.7.9 K-map
A: = BCR+ACR
B: = BCR+ACR
C: = ABR+ ABR
We can also get the Function Table from Table 5.7.5. In this case, we replace 2 of
74S00 and 1 of 74S175.
-",-,,,
102
Programmable Logic Design Guide
Example 4: Design a video-telephone sync pulse detector.
The video-telephone set contains a CRT for displaying the received picture from
another video-telephone, and a vidicon camera for generating the picture to be transmitted.
The vidicon sweeps across the head and shoulders view of the person talking,
starting at the upper left of the picture and moving right as shown in Figure 5.7.10.
Figure 5.7.10 Sweep Generation
The dots shown in the figure represent samples taken by the vidicon. The vidicon
produces a voltage that is proportional to the light intensity for each sample taken. The
voltage is then quantized into seven levels. These seven levels correspond to light levels
from white to black with intermediate levels of gray. Because there are seven quantized
levels, a 3-bit quantizer is employed. These seven levels are then channel-encoded such
that where the code 1 1 1 is reserved for the line sync pulse. The data are transmitted in
a bit-serial manner. When the sync pulse is detected, the receiver camera flies back to
start a new line, as shown in Figure 5.7.10. The use of the line sync pulse ensures that
o
0
0
o
o
o
0
1
1
o
-
- -
-
-
LEVELS OF GRAY
1
o
WHITE
0
101
o -----
BLACK
How to Design With Programmable Logic
103
all the lines start at a well-defined left edge. This prevents the occurrence of skewed
lines which will distort the picture.
The PAL device under design is used as a sync pulse detector which will trigger the
flyback circuit. There is another feature we need to design into this PAL device which
automatically resets to the initial state after three input pulses. This reset procedure will
ensure that no false output occurs due to consecutive sequences which produce an
overlapping 1 1 1 sequence.
From the function description above, we can generate the State Diagram and State
Table as shown in Figure 5.7.11 (a) and (b).
x
010, 1/1
0
(A) STATE DIAGRAM
Figure 5.7.11
A
DID
BID
B
EIO
CIO
C
AID
All
0
E/O
EIO
E
AID
AID
(B) STATE TABLE
(A) State Diagram (B) State Table
Where A is the initial state, the sequence A ~ B ~ C ~ A will detect the
sync pulse (1 1 1) and generate a "1" output. Note that the state diagram is arranged so
that every sequence of length 3 returns the machine to the initial state A.
Since we have 5 different states (3 registers are enough), 1 input for serial data, 1
non-register output for sync pulse detecting, we may use the 16R4 to implement this
application.
104
Programmable Logic Design Guide
Let's assign these 5 different states as in Table 5.7.6.
STATE
STATE ASSIGNMENT
Vl. V2. V3
A
B
C
D
E
000
001
010
1 01
110
Table 5.7.6 State Assignment
Then from the State table Figure 5.7.11 (B) we get the Transition table shown in
Table 5.7.7.
x
x
0
y1 y2 y3
o
1
0
1
000
1
1
o 0 1
0
0
001
1 1 0
0 1 0
0
0
o
1 0
000
000
0
1
o
1
1
X X X
X X X
X
X
100
X X X
X X X
X
X
1 0 1
1 1 0
1 1 0
0
0
110
000
000
0
0
1 1 1
x x x x x x
x
x
V1
V2 V3
Z
Table 5.7.7 Transition Table
From Table 5.7.7 Transition Table we can draw the K-map of each register output
Y1, Y2, Y3 and the non-register output Z as shown in Figure 5.7.12.
How to Design With Programmable Logic
y3 X
y3 X
o 0
o
1
1
1
1 0
y1
y2
o
0
Q
0
0
o
1
0
0
X
X
1
0
0
X
X
0
0
X
1
y1
y2
o0
0 1
o
0
0
0
1
1
o
1
0
0
X
X
1
0
0
X
X
0
X
X
1
1
Q
= V1·V3
V3
V1 V2
o
0
1
o
1 0
V2
+ V2*X
V2
X
= V3
V3 X
o0
I
1
.-V1
V1
1
o
1
I
1 1
1 0
0
o0
v1
V2
0
o
0
0
o
1 1
1 0
0
0
0
1
X
1
1
1
1
0
0
X
X
o
1
0
1
0
0
x
x
1
1
0
0
X
X
0
Ix
xJ
0
0
1
0
X
X
0
0
I
z
V3
V3 = V2·V3
z
Figure 5.7.12
Therefore, we get the logic equations as:
YI := YI*Y3+Y2*X
Y2 := Y3
Y3 := Y2*Y3
Z = YI*Y2*X
= V1·V2·X
K-map
I
x
105
106
Programmable Logic Design Guide
Summary
The four design examples are quite simple for purposes of illustration. The author
has attempted to give the reader a very clear idea and to encourage the reader to use
PAL devices. The reader can find other examples in the applications section of
Chapter 8.
Here the author would like to point out one thing; "There are many different
approaches to designing a PAL device circuit." Some users like to directly code the PAL
device logic diagram (coding "x"). In this case, users may not need logic equations. But
if circuits become more complicated, then the user will find that the logic equations are
much easier to get than directly coding "x" in the PAL device logic diagram. There are
many ways to develop logic equations. One approach is to use truth tables or transition
tables. Another way, which is widely used, is from timing waveforms.
The user can draw the timing diagram for each output, then derive his logic equations from these timing waveforms. But no matter what method is used, the user still
needs to know the K-map or other techniques (the Quine-McCluskey method is frequently used) to minimize his logic gates.
The author strongly recommends deriving the logic equations for PAL devices
rather than coding "X" in the PAL device logic diagram. Then the user can take advantage
of PAL device software (PIAN, PAIASM, etc.) instead of manually coding the PAL device programming format sheet.
6
Software Support
Today a variety of software products makes the logic design engineer's task much easier. The designer can now focus on the intricacies of logic design at the Boolean level
instead of filling in tedious fuse map charts, or worrying whether a standard logic part
exists to implement the logic. Some of the traditional programmer vendors are now
marketing full-fledged development systems or CAD systems that include the terminal,
software and the hardware for fuse blowing, and logic verification. Other vendors market software only or programmer/verifier only. The key part of any developrrient system is the software and this section describes the attributes of these products.
6.1
ADVANTAGES OF SOFTWARE-BASED PROGRAMMABLE LOGIC DESIGN
When programmable logic devices were first introduced, the only method for specifying the logic to be implemented was to manually code the status of each fuse on a form
and then enter this information into a programmer. With a device like the PAL16L8
which has 2048 fuses, this manual method is clearly time-consuming and error-prone.
Furthermore, these early programmers could not verify if the programmed device was
functional. They could only check if the correct fuses were blown. Information about
testing is found in Chapter 7.
The first phase in software development was the development of tools to eliminate
the manual fuse-map entry. Users could enter Boolean equations in Sum-Of-Products
format on a computer and the program would generate the fuse-map information
which could be downloaded to a programmer unit (Figure 6.1.1).
Figure 6.1.1
Early Role of Software
107
108
Programmable Logic Design Guide
Subsequent developments in software goes further in providing two additional capabilities. The first area of improvement is logic design. Recent developments are emphasizing design tools for logic circuit design with features like high level logic design options
and plans for logic minimization, and state-machine synthesis. The second area being
addressed is that of functional testing of programmed devices. Most of the current software has features to perform simulation for design verification, i.e., verify if the user supplied test vectors match the logic conditions described by the equations for the logic
being implemented. These test vectors can also be downloaded to a programmer which
will perform a functional test on the programmed device (Figure 6.1.2).
LOGIC
EQUATIONS
PAL DEVICE
PROGRAMMED
DEVICE
LOGIC
DESIGN AIDS
Figure 6.1.2
Expanded Role of Software
The next section describes National's contribution to advanced programmable
logic design software called Programmable Logic Analysis by National (PLAN).
6.2
PROGRAMMABLE LOGIC ANALYSIS BY NATIONAL (PLAN)
PLAN is a set of interactive software tools for logic designers who will be using programmable logic devices in their circuits. The advantages of PLAN are that: (1) it is easy
to use; and (2) it comes with clear and simple documentation that explains the numerous features of PLAN and the methods of accessing and using these features. PLAN also
has a liberal sprinkling of error messages to help the user. PLAN does not have PALASM
type input format constraints and is available on more than one operating system. The
package actually contains three programs: PLUS, SERV, and PROG.
PLUS allows the user to define logic via Boolean equations and also selects an
appropriate device and assigns pin-outs. The resulting equations, device, and pin-outs
are stored in a file.
Software Support
109
The next program, called SERV, can then be used to access the logic defined by
PLUS for possible reassignment of the device and pin-out. When the device and
pin-outs are finalized, SERV also displays the pin-out diagrams, fuse-maps and equations. For documentation purposes, the above data can also be printed out.
The third program, called PROG, takes the logic and pin assignment data and provides it to a programmer in a format that the user selects. This program can also acquire
a previously defined file containing test vectors and download it to a programmer for
functional verification.
The software package is available on 8-inch SSSD (Single Side Single Density)
floppy disks to run under CP/M-80 and 5 1I4-inch SSSD floppy disks for operation
under MS-DOS and APPLE-DOS. Future revisions will include other operating systems.
Boolean Entry
The Boolean entry operators that PLAN supports are shown in Table 6.2.1
EQUALITY
AND,PRODUCT
+ OR, SUM
I
COMPLEMENT
. - REPLACED BY (AFTER CLOCK)
CONDITIONAL TRI-STATE
: + : EXCLUSIVE OR
*
o
Table 6.2.1
Boolean Operators
An example of a logic equation using these operators is:
(lINPI * INP2) OUT2
/INP3 * INP4
=
A useful feature that PLAN offers during Boolean logic entry is the definition and
inclusion of logic macros. Table 6.2.2 is an example of the use of the macro feature in
PLAN.
MACRO IS EN1*ICK2
RESULTING EQUATION
INPUT
=
OUT1
INP1*IINP2
+ IINP1*INP2
OUT2
=INP3 + INP4
*INPS*INP6
Table 6.2.2
=
INP1*IINP*1EN1*ICK2
OUT1
+ IINP1*INP2*EN1*ICK2
OUT2
=INP3 + INP4EN1*ICK2
*INPS*INP6
Macro Entry with PLAN
..
~~.
110
Programmable Logic Design Guide
PLAN allows the user to edit the Boolean equations after entry. When the equations
are finalized, the program will automatically select a device that can implement the
defined logic and assign pin-outs to that device. This process is shown in Figure 6.2.3.
The information can also be stored in a file and the data in the file is essentially the
information in Figure 6.2.3.
EQUATIONSIVARIABLES
LAOSHG
PINOUTS
= O*KJR*/ROIUH
+ OJH*IH
OEU = EUY*KJR + OU
ERIJH = OJ*JO*JJJ*JPP
+ IOOF*OFJ*JJJ*JPP
J
OEVICE
0 - 1 \.J 20 f-VCC
KJR- 2
ROIUH- 3
OJH- 4
IH- 5
EUY- 6
OU- 7
OJ- 8
LOGIC OEVICE NAME IS PAT0099
THE SOURCE OEVICE IS A PAL 14H4
A SERIES 20 SMALL PAL WITH
ACTIVE HIGH OUTPUTS
Figure 6.2.1
JO- 9
GNO- 10
19
....
18 _OFJ
17
0-
16 f-OEU
15 f-LAOSHG
14 f-ERIJH
13 f-IOOF
12 f-JPP
11 f-JJJ
PLAN File Information
File Editing and Documentation
The program SERV can be used to change the selected device and also to change the
pin-out assignment. When the device and pin-outs have been finalized, the device diagram with pin-out, the equations or the fuse-map of the programmed device can be
printed out or viewed on the screen. Figure 6.2.4 is an example of the fuse-map display.
Programming and Testing
In order for a programmer to function, it has to receive the fuse-map information in a
specified format. The third program in PLAN, called PROG, will provide the fuse-map
information, at the users option, in any of the five formats listed in Table 6.2.3.
The programmer fuse-map data can be saved in a file for later use. PROG can also
access a file containing test vectors and download them to a programmer for functional
verification of a programmed device.
Because of its ability to support the various data formats, many programmers are
supported by PLAN and most are physically interfaced through a standard RS-232 cable.
Software Support
FUSE MAP FOR LOGIC PAT0099 - SOURCE DEVICE IS DMPAL 14H4
INPUTS (0-31)
1
1
22
23
1
22
02
46
80
2
o2
46
80
6
16 XXXX XXXX XXXX xx xx XXXX XXXX XXXX
17 XXXX XXXX XXXX xx xx XXXX XXXX XXXX
19 XXXX XXXX XXXX xx xx XXXX XXXX XXXX
24 X--EUY·KJR
X25
DU
X--26 XXXX XXXX XXXX xx xx XXXX XXXX XXXX
27 XXXX XXXX XXXX xx xx XXXX XXXX XXXX
32 X-X- -X-D· KJR ·/RDIUH
33
OJWIH
X--- X34 XXXX XXXX XXXX xx xx XXXX XXXX XXXX
35 XXXX XXXX XXXX xx xx XXXX XXXX XXXX
40
X-X- X-X- DJ·JD·JJJ·JPP
41
--X--X- --X- --X- IODPDFJ·JJJ·JPP
42 XXXX XXXX XXXX xx xx XXXX XXXX XXXX
43 XXXX XXXX XXXX xx xx XXXX XXXX
X'S REPRESENT INTACT FUSES, 152 HAVE BEEN REMOVED.
PRODUCT
TERMS
(0-63)
Figure 6_2_2
Fuse-Map Display from PLAN
MMI Hex
JEDEC
Intel Hex
Standard Hex
PALASM Format
Table 6.2.3
Fuse-Map File Formats in PLAN
Order from: National Semiconductor Corporation PLAN
2900 Semiconductor Drive
MIS D3698
Santa Clara, CA. 95057
(408) 721-4107
111
112
6.3
Programmable Logic Design Guide
OTHER SOFTWARE
CUPLTM by Assisted Technology
CUPL is the first software CAD tool designed especially for the support of all programmable logic devices (PLDs), including PALs and PROMs. It was developed specifically for
YOU, the Hardware Design Engineer. Each feature of the CUPL language has been
chosen to make using programmable logic easier and faster than conventional Tn
logic design.
Major Features of CUPL
Universal
• PRODUCT SUPPORT: CUPL supports products from every manufacturer of of
programmable logic. With CUPL you are free to use not only programmable
logic. With CUPL you are free to use not only PALS, but also other programmable
logic devices.
• PAlASM CONVERSIONS: CUPL has a PAlASM to CUPL language translator which
allows for an easy conversion from your previous PAlASM designs to CUPL.
• LOGIC PROGRAMMER COMPATIBILI1Y: CUPL produces a standardJEDEC download file and is compatible with any logic programmer that JEDEC files.
High Level Language
High Level Language means that the software has features that allow you to work in terms
that are more like the way you think than like the final PLD programming pattern. Examples of these are:
• FLEXIBLE INPUT: CUPL gives the engineer complete freedom in entering logic
descriptions for their design.
- Equations
- Truth Tables
- State Machine Syntax
• EXPRESSION SUBSTITUTION: This allows you to pick a name for an equation
and then, rather than write the equation each time it is used, you need only use
the name. CUPL will properly substitute the equation during the compile process.
Software Support
•
113
SHORTHAND FEATURES: Instead of writing out fully expanded equations CUPL
provides varous shorthand capabilities such as:
- List Notation: Rather than [A6,A5,A4,A3,A2,Al,AO]
CUPL only requires [A7 .. 0]
- Bit Fields: A group of bits may be assigned to a name,
as in FIELD ADDR = [A7 .. 0]
Then ADDR may be used in other expressions
- Range Function: Rather than
A15 & !A14 #
A15 & A14 & !A13 #
A15 & A14 & A13 & !A12
CUPL only requires ADDR: [8000 .. EFFF]
- The Distributive Property:
A& (B # C)
From Boolean Algebra, where
is replaced by
A&B#A&C
- DeMorgan's Theorem:
!(A& B)
From Boolean Algebra, where
is replaced by
!A# !B
Self Documenting
CUPL provides a template file which provides a standard "fill-in-the-blanks" documentation system that is uniform among all CUPL users. Also, CUPL allows for free form comments throughout your work so there can be detailed explanations included in each part
of the project.
Error Checking
CUPL includes a comprehensive error check capability with detailed error messages designed to lead you to the source of the problem.
Logic Reduction
CUPL contains the fastest and most powerful minimizer offered for Programmable Logic
equation reduction. The minimizer allows the choice of various levels of minimization
ranging from just fitting into the target device to the absolute minimum.
Simulation
With CSIM, the CUPL Simulator, you can simulate your logic prior to programming an actual device. Not only can this save devices but it can help in debugging a system level
problem.
Test Vector Generation
Once the stimulus/response function table information has been entered into the
Simulator, CSIM will verify the associated test vectors and append them to theJEDEC file
for downloading to the logic programmer. The programmer will verify not only the fuse
map, but also the functionality of the PLD, giving you added confidence in the operation
of your custom part.
114
Programmable Logic Design Guide
Expandability
CUPL is designed for growth so as new PALs and other devices are introduced you will
be kept current with updated device libraries and product enhancements.
CUPL-GTSTM
In recent years, programs like CUPL and ABEL have become available to provide high
level language support for PAL designs. These languages allow the designer to represent
a PAL function in terms of high-level equations, truth tables or state machines.
Many hardware deSigners, however, are most comfortable with the traditional logic
schematic as a logic description format.
CUPL-GTS is a powerful combination of hardware and software which turns an IBMPC type computer into a programmable logic workstation allowing the user to draw logic
schematics for the function of a PAL. A basic premise in creating GTS was to provide a
friendly environment where the user is isolated from the traditional keyboard as much
as possible. Virtually all functions can be actuated with one button by way of the mouse
and a series of pop-up menus which ease the user's task. An area is provided at the top of
the CUPL-GTS screen for prompting the user regarding the next operation in a command
sequence. Highlighting of various elements on the screen is coordinated with these
prompts. For the most part, the user need only utilize the conventional keyboard for defining symbolic names for wires, pins, objects, and files.
An on-screen HELP facility is provided to aid the user with CUPL-GTS commands. In
addition to the basic set of object types which can be easily picked from a pop-up menu,
the ability to call up macro-objects is also provided. These macro-objects have been previously drawn using GTS and stored away on the disk under their own symbolic name.
After a logic schematic has been entered, the user may quickly check to see if the design fits into a specific PAL. This is done by selecting the "Translate to PLD" command
from the main menu which automatically invokes the GTS translation programs. These
programs run in an on-screen window which overlays the graphical information, providing feedback in the form of error messages displayed in this window. In this way many
errors can be quickly determined and remedied without ever having to let go of
the mouse.
When the user wishes a hard copy version of a deSign, the print command from the
main menu may be selected. This causes the GTS print program to execute in an onscreen wndow according to the printer configuration file (PRINTCAP). The PRINTCAP
file allows the user to configure the GTS print function for any dot matrix printer they
might have.
Often a logic description does not fit in a particular PAL due to a logic capacity
(product-term) limitation. When this occurs, the universal capability of GTS will easily
allow the user to try placing this same logic in a different PAL of a similar architecture.
Software Support
115
Since CUPL-GTS incorporates CUPL the high level language in its internal operation,
it also benefits from CUPL's powerful "Quine Procedure" logic minimizer. This is especially advantageous for CUPL-GTS as logic descriptions showing many levels of gates can
be very deceptive in their ability to consume the logic capacity. of a PAL. The presence of
the logic minimizer can eliminate unnecessary and redundant logical functions, and
maximizes the probability that a design will fit in a target PAL.
Also included with CUPL-GTS is the CUPL Simulator, CSIM, which allows the user to
simulate a logic design prior to physically creating a programmed PAL. Not only can this
save devices, but it can help significantly in debugging a system level problem.
CUPL-GTS is designed for growth and expandability. As new programmable logic
devices are introduced users will be kept current with updated device libraries and
product enhancements.
Most of us first use PAL devices to replace TTL in order to shrink a design andlor add
functionality. The following example shows how a simple I/O decoder design would appear on the CUPL-GTS screen prior to translation to a PAL16L8 or PAL16p8.
I
Select Command From Main Menu
Help
Change Scale
Set Center
LS32
- C H,
-)
C
H,
H,
H,
H,
H,
L J;
L J;
AhEOOO
-)
-)
-)
-)
[
[
H,
H,
H,
L,
H,
H,
L,
H,
L,
H,
H,
H,
H l;
H l;
H J;
H] ;
~nE800
AhFOOO
'"hF800
er,d m6809a
Figure 6.3.4
Source File: 6809 Memory Address Decoder
Test Vectors
In this design, the test vectors are a straightforward listing of the values that must appear
on the output lines for specific address values. The address values are specified in
hexadecimal notation on the left sife of the "->" symbol. Inputs to a design always appear
on the left side of the test vectors. The expected outputs are specified to the right of the
"->" symbol. The designer chose in this case to use the symbols Hand L instead of the
binary values 1 and 0 to describe the outputs. The correspondence between the symbols
and the binary values was defined in the constant declaration section of the source file,
just above the section labeled equations.
Summary
A design described with the ABEL ™ design language has been shown. This design shows
how Boolean equations with logical and relational operators are used to describe an address decoder. Test vectors were written to test the function of the design using ABEL ™ 's
simulator. In addition to the Boolean equations shown in this example, ABEL ™ features
truth tables and state diagrams. State diagrams allow the designer to fully describe state
machines in terms of their states and state transitions. Truth tables specify designs in
terms of their inputs and outputs, much like test vectors.
Regardless of the method used to describe logic, ABEL ™ 's automatic logic reduction
and simulation ensure that the design uses as few terms as possible and that it operates
as the designer intended. The end results are savings in time, devices, board space,
and money.
120
6.4
Programmable Logic Design Guide
SOFTWARE FOR TESTING PROGRAMMABLE LOGIC
Some of the test equipment vendors also have software that can be used for testing programmed devices in a production environment. These software packages do not have
any design aids but have automatic test vector generation and simulation tools and are
generally written to run on powerful mini-computers.
6.5
SOFTWARE VENDOR LIST
Listed below are the major software vendors for Programmable Logic.
NATIONAL SEMICONDUCTOR CORPORATION
PLAN
2900 Semiconductor Drive
MIS 16-198
P.O. Box 58090
Santa Clara, CA 95052-8090
(408) 721-4107
ASSISTED TECHNOLOGIES, INC.
2381 Zanker Road, Suite 150
San Jose, CA 95131
DATA I/O CORPORATION
10525 Willows Road N.E.
C-46
Redmond, WA 98052
A vendor who supplies software for production testing of Programmable Logic is
provided below.
GENRAD
170 Tracer Lane
Waltham, MA 02254
7
Testing and Reliability
7.1
NATIONAL FACTORY TESTING
National's PAL devices include special test circuitry designed to permit thorough AC
and DC testing to be accomplished on an unprogrammed unit. This test circuitry is
used to ensure good programming yield and to verify that devices will meet all parametric and switching specifications after programming.
Each PAL device has special test fuses. These test fuses are blown during factory
testing and demonstrate beyond reasonable doubt that the device is capable of opening
all fuses when programmed by the user. They also increase the confidence level in
unique addressing.
Table 7.1.1 shows the total number of fuses and test fuses for each device. Figure
7.1.1 shows the PAL test flow in National's factory.
Since PAL devices are logic devices, in addition to testinR the fuses blown their
logic function should be tested after programming. This can be performed on a
National tester, or on some PAL device programmers, using user defined test vectors
or by comparison against a known good unit (fingerprint test).
Test vectors are relatively easy to generate for combinational designs using PAL
devices. Sequential function testing is more difficult.
National's application Note # 351 by Tom Wang tells the user how to generate these
test vectors. National also supports customer test vectors and fully tests its custom
order NML or programmed PAL devices.
AND Array Organization
Device
Number
Input
Lines
PAL10H8
PAL12H6
PAL14H4
PAL16H2
PAL16C1
PAL16L8
PAL16R8
PAL16R6
PAL16R4
10
12
14
16
16
16
16
16
16
X
TIC
X
2
2
2
2
2
2
2
2
2
DIble 7.1.1
Product
Lines
=
16
16
16
16
16
64
64
64
64
Number
of Fuses
Number of
Test Fuses
320
384
448
512
512
2048
2048
2048
2048
42
44
46
48
48
98
98
98
98
Test Fuses
121
122
Programmable Logic Design Guide
START
.. F
-
I
OPENS AND
SHORTS
WORD PATTERN
CHECK
I
-
BIT PATTERN
CHECK
ICC
I
..-
GROSS
FUNCTIONAL
"HIGH"
F
ARRAY CHECK
I
,-
GROSS
FUNCTIONAL
"LOW"
VERIFY WORD
~,
I
F
VERIFY BIT
1-'-+
I
DC
PARAMETRIC
TESTS
F
1-'-+
I
F
PROGWORD
I
-
I
MIX CHECK
PROG BIT
..--
1
F
ARRAY CHECK
I
t
FOR SAMPLE ONLY
" FOR NMUPROGRAMMED PAL
Figure 7.1.1
PAL Device Test Flow
ACTESTt
1-'-+
I
"FUNCTIONAL
TEST
-,-+
F
Testing and Reliability
7.2
123
LOGIC VERIFICATION
PAL devices are not only memory devices, but also logic devices. Therefore, in addition
to verifying the fuses blown after programming, we also need to verify the logic operation before it is put in a system. Logic verification provides assurance that a device will
function in a board. Figure 7.2.1 shows the PAL device's architecture which will clarify
the difference between fuse programming/verification and logic verification. The
programming/verification circuit is required to allow custom configuration by the user.
This circuit is operational only when a super voltage is applied to VCCo Under normal
5.0 volt operation, this circuit is invisible and the logic circuit will take over. Therefore
the skills we use to check the PAL device under normal 5.0 volt operation are called
logic verification. The most important skill we use now is called functional test.
PROGRAMMING!
VERIFICATION
CIRCUIT
-
INPUT
r------- 1-----,
PROGRAMMABLE
ARRAY
r-----I
I
OUTPUT
f-----------
LOGIC
CIRCUIT
-PROGRAMMINGIVERIFICATION FLOW
- - - FUNCTIONAL FLOW
Figure 7.2.1
PAL Device's Architecture
-------
-
124
Programmable Logic Design Guide
Functional testing must accomplish two purposes:
1) It must verify that the PAL device, after programming, performs the function
intended.
2) It must verify the circuit removed through programming does not affect the PAL
device's operation.
The functional testing technique relies on the test vectors. A test vector means a
combination of desired input variable values and expected output variable values. The
PAL device will be exercised by the desired input values. Then, the received outputs
will be compared with the expected output values. The device is considered a "malfunction" if the comparison does not match. Figure 7.2.2 shows an example.
EXERCISEDINPUTS
1 1 0 1 1 01 1 01
\
.
,
EXPECTED OUTPUTS
10110110
\
,
•
I
PAL
DEVICE
}
OUTPUTS
INPUTS
I
Figure 7.2.2
ERROR IF
COMPARISON
MISMATCH
Function of Test Vector
There are many methods of generating test vectors:
1. Exhaustive - generate the whole different input combination and the expected output values. For instance, for 3-input AND gate in Figure 7.2.3, we get eight test vectors as in Table 7.2.1. For an n-inputs device, we get 2n test vectors.
A
B
1----- F
C
Figure 7.2.3
3-Input AND Gate
Testing and Reliability
A
8
C
F
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
125
Test Vectors Generated by Exhaustive Methods
Table 7.2.1
2. Fault modeling - Use the stuck at 0 and stuck at 1 technique to sensitize the different logic path. For instance, in Figure 7.2.3, there are three different paths, i.e. AF,
BF and CF. Therefore we get six test vectors shown in Table 7.2.2 (a). Due to vector
1,3 and 5 being the same, we can reduce to four test vectors as in Table 7.2.2 (b).
A
8
C
F
A
0
0
8
C
F
0
1
0
0
0
1
0
1
0
1
(A)
Table 7.2.2
1
1
0
0
0
0
(8)
Test Vectors Generated by Fault Modeling
3. Structure Test - Only pick up the possible existing input states and their corresponding output states.
There is another skill to do the logic verification. It uses the signature analysis technique.
This technique uses random input values exercising on a good device to generate different outputs. The outputs are manipulated in certain ways to get a "test sum" called a "signature." Then, using the same sequence of input values to another device we get its signature which is compared with the known good one. Some PAL device programmer vendors offer user fingerprint tests which are based on signature analysis techniques such as
DATA VO, Digital Media.
126
7.3
Programmable Logic Design Guide
CUSTOMER'S RESPONSIBILITIES
The number of parts that are non-functional after programming is generally less than
2 % and may be picked up during board-level check. However, the author strongly
recommends that the user do the logic verification before putting PAL device components into the system.
Since the user defines the function of the PAL device, it is impossible for the supplier to perform full functional testing prior to shipment unless the user orders an NML
or programmed PAL device from National.
It is the user's responsibility to generate test vectors or do the fingerprint test. The
methods for generating test vectors was discussed in Section 7.2.
7.4
RELIABILITY DATA
Following is sample reliability data on National's PAL devices. For additional information
please contact your National representative or distributor.
Product:
Package:
Bipolar PALs (DM3300)
Molded (N) and Hermetic Q)
Test Method: Dynamic (DHU)/Static (SHU) High Temperature Operating Life
Conditions: Continuous Operation at Rated Supply Voltage, and 12SoC
Duration:
1000 Hours
Filel.D.
Device
Package
Type
Type
RMB75131
16R4
J
RMB75133
16L8
RMB75101
Test
Sample
168
Size
Hours
77
77
DHTL
500
1000
0
0
0
0
0
0
77
0
0
0
77
0
0
1
77
0
0
16R4
77
0
0
0
16L8
77
0
0
0
77
0
0
0
77
0
0
0
16R8
77
0
0
0
RMB75190
16R4
77
0
0
0
RMB75144
16R8
77
0
0
0
RMB75154
16LB
77
0
0
0
RMB75137
16R6
16R6
RMB75096
16R4
RMB75132
RMB75097
RMB75142
16R8
RMB75143
16L8
RMB75144
SHTL
N
DHTL
SHTL
Total Devices: 1001
Total Device Hours at 12S°C: 1001 *103
0
Failure Mode
Fuse verify and functional
Testing and Reliability
Failure Rate at Stress
127
= 0.2%/1000 Hours
Total Device Hours at 55°C, and O.4EV = 12.012*106
Failure Rate at 55°C, O.4EV and 60% Confidence Level:
%/1000 Hours: 0.0168; PPM Hours: 0.168; Fits: 168; MTBF: 5.9*106
Test Method: Temperature Humidity Bias Test
Conditions: Continuous Operation at Rated Supply Voltage, 85°C, and 85%RH
1000 Hours
Duration:
Filel.D.
Device
Type
Package
Type
Sample
Size
Hours
RMB75143
16L8
N
RMB75144
16R8
RMB75199
16R4
77
77
77
0
0
0
168
500
1000
0
0
0
0
0
0
Failure Mode
Total Devices: 231
Failure Rate at Stress: 0.4%/1000 Hours
7.5
PAL DEVICE FUNCTIONAL TESTING
Combinational and Sequential Circuits
Digital circuits can be classified as either combinational or sequential. Combinational circuits (e.g., decoder, multiplexer, adder, etc.) whose present value of the outputs at any
time are functions of only the present circuit inputs at that time can be described as:
Y
= F(X)
where F is Boolean sum of products transfer function (Figure 7.5.1).
INPUTS X
---.~ OUTPUTS Y
Figure 7.5.1
Combinational Circuit
Sequential circuits (e.g., counter, shift register, accumulator, etc.) whose present
value of the outputs at any given time will be the functions not only of the present circuit inputs at that time, but also the previous value of the outputs can be described as:
Y
= F(X, Y)
where F is the Boolean Sum-of-Product transfer function. See (Figure 7.5.2).
128
Programmable Logic Design Guide
CLOCK
INPUTS X
OUTPUTS Y
Figure 7.5.2
Sequential Circuit
Description of PAL (Programmable Array Logic) Device
Due to rapidly increasing integrated circuit technology, logic circuit designers face a
difficult decision: should they use conventional TTL gates or custom LSI to implement
desired combinational/sequential circuits.
Use of conventional TTL gates does not take advantage of the increased 'integration available. However, expensive and complicated software often makes custom LSI
unsatisfactory. There is a big void between these two solutions. This void is now being
addressed by semicustom approaches (e.g., PAL devices or gate array, etc). Since PAL
devices have advantages over other semicustom chips in many areas (for instance, cost
effectiveness, quick turnaround, complete software support, multi-source, etc.), it may
be the best approach for the logic designer designing combinational/sequential circuits.
National offers the designer a family of PAL devices. See Table 7.5.1 for a broad
overview of National's products.
PAL Device Design Procedure
Designing combinational circuits is straightforward. The first step is to define the circuit's function. The second step is to build a truth table. The third step is to minimize
the truth table by using Karnaugh maps or Boolean algebra, in order to get the transfer
function (Le., logic equations). Step four is programming the circuits. Figure 7.5.3 is a
flow diagram which applies to designing combinational PAL devices.
It is much more complicated to design a sequential circuit, as discussed in many
textbooks and articles. Figure 7.5.4 is a flow diagram which applies to designing
sequential PAL devices.
The last step in both Figures 7.5.3 and 7.5.4 is programming the PAL device. The
entire procedure for programming a PAL device is shown in Figure 7.5.5. The first step
is to generate the logic equations and function table. The second step is, using PAL
device software tools (e.g., PALASM®, PLAN™, etc.), to create a bit pattern and exercise
the function table, if any, in the logic equations. The third step is to load the bit p~ttern
into a PAL device programmer to program and verify the fuse matrix. The fourth step is
to functionally test the PAL device. The last step is to blow the security fuse. This last
step is optional.
Testing and Reliability
Standard
High Speed
(25 ns)
(35 ns)
10H8
12H6
14H4
16H2
1018
1216
1414
1612
16Cl
1618
16R8
16R6
16R4
10H8A
12H6A
14H4A
16H2A
10l8A
12l6A
14l4A
16l2A
16C1A
16l8A
16R8A
16R6A
16R4A
129
Ultra-High
Speed (15 ns)
low Power
(35 ns)
Package
(Pins)
16l8B
16R8B
16R6B
16R4B
10H8A2
12H6A2
14H4A2
16H2A2
10l8A2
12l6A2
14l4A2
16l2A2
16l1A2
16l8A2
16R8A2
16R6A2
16R4A2
20
20
20
20
20
20
20
20
20
20
20
20
20
10
12
14
16
10
12
14
16
16
16
16
16
16
Input,
Input,
Input,
Input,
Input,
Input,
Input,
Input,
Input,
Input,
Input,
Input,
Input,
8
6
4
4
8
6
4
2
1
8
8
6
4
24
24
24
24
24
24
24
24
24
24
12
14
16
18
20
20
20
20
20
20
Input,
Input,
Input,
Input,
Input,
Input,
Input,
Input,
Input,
Input,
10 Output AND-OR Array
8 Output AND-OR Array
6 Output AND-OR Array
4 Output AND-OR Array
2 Output AND-OR Array
1 Output AND-OR/NOR Array
8 Output AND-OR-Inv Array
8 Output AND-OR-Reg Array
6 Output AND-OR-Reg Array
4 Output AND-OR-Reg Array
24
24
24
24
20
20
20
20
Input,
Input,
Input,
Input,
10 Output AND-OR-Inv Array
10 Output AND-OR-XOR-Reg Array
8 Output AND-OR-XOR-Reg Array
4 Output AND-OR-XOR-Reg Array
(40 ns)
12110
1418
1616
1814
2012
20Cl
20l8A
20R8A
20R6A
20R4A
(50 ns)
20110
20Xl0
20X8
20X4
Table 7.5.1
Description
Output AND-OR Array
Output AND-OR Array
output AND-OR Array
Output AND-OR Array
Ouptut AND-OR Array
Output AND-OR Array
Output AND-OR Array
Output AND-OR Array
Output AND-OR/NOR Array
Output AND-OR-Inv Array
Output AND-OR-Reg Array
Output AND-OR Reg Array
Output AND-OR-Reg Array
National's PAL Device Family
Description of Functional Table
In Figures 7.5.3, 7.5.4 and 7.5.5 we encounter a step called "generating function table."
However, what is the meaning of a function table and why do we need it? A function
table is a sequence of test conditions which are representative of the device in actual
circuit operation. When we derive the logic equations by using Karnaugh maps or
Boolean algebra, it- is possible to introduce errors that may not be obvious. The function table is a means of expressing what we expect the PAL device to do in the system.
PALASM or other software simulators will exercise the function table in the logic equations and report simulation errors. Then, we can correct the function table and/or the
logic equations until no simulation error occurs.
130
Programmable Logic Design Guide
FUNCTIONAL
DESCRIPTION
!.
FUNCTION
TABLE
~
_ _ DEFINE INPUTS
AND OUTPUTS
TRUTH
TABLE
l·
KARNAUGH MAPS OR
- - BOOLEAN ALGEBRA
TRANSFER
FUNCTION
(LOGIC
EQUATIONS)
l·
(PROGRAMMING THE
PAL DEVICE)
CIRCUITS
(PAL)
DEVICE
Figure 7.5.3
Combinational PAL Device Design Steps
Even if both the logic equations and blown fuses are correct, there is no guarantee
that the PAL device will function properly. PALASM or other software tools can generate test vectors from the function table entries and exercise these test vectors in the PAL
device after it has been programmed. Even though the functional verification fallout is
very small (typically less than 2%), it is necessary to perform this test at the device
level. Ten devices on a board with a 2% device fallout translates into 18% fallout at the
board level if these devices are not individually tested.
Thus, we can see that a good function table will provide a high degree of confidence that the design is correct. It will also help ensure that the PAL device will work
properly the first time it is plugged into the system.
Testing and Reliability
FUNCTIONAL
DESCRIPTION
!
STATE
DIAGRAM
!
STATE
TABLE
1·
MINIMIZING THE
STATE TABLE
MINIMAL
STATE TABLE
1·
FUNCTION
TABLE
~
STATE
ASSIGNMENT
TRANSITION
TABLE
!.
KARNAUGH MAPS OR
BOOLEAN ALGEBRA
TRANSFER
FUNCTION
(LOGIC
EQUATIONS)
1-
(PROGRAMMING THE
PAL DEVICE)
CIRCUITS
(PAL)
DEVICE
Figure 7.5.4 Sequential PAL Device Design Steps
131
132
Programmable Logic Design Guide
ENTER LOGIC EQUATIONS
~
ENTER FUNCTION TABLE
~
CREATE BIT PATTERN
~
EXERCISE FUNCTION TABLE
IN LOGIC EQUATIONS
(SIMULATION)
~
LOAD PATTERN INTO
PROGRAMMER
l
I
PROGRAM FUSE MATRIX
I
VERIFY FUSE MATRIX
~
TEST PAL DEVICE FUNCTION
WITH TEST VECTORS OR DO
OTHER LOGIC TEST
~
BLOW SECURITY FUSE
(DO FUNCTIONAL
TESTING AGAIN)
Figure 7.5.5
PAL Device Programming Procedures
Testing and Reliability
133
How to Generate Test Vectors and the Function Table from Logic Equations
It is the PAL device designer's responsibility to generate the function table since he/she
knows the operation of the design best. However, if this is not possible, we can generate the function table manually from the existing logic equations. To do this, the correct logic equations are needed. Figure 7.5.6 outlines the procedure which will be
detailed by examples in the next section. The "optimization" procedure is sometimes
difficult and may need intuition. (Notice the different procedure between combinational and sequential PAL in the last step.)
LOGIC EQUATIONS (KNOWN GOOD)
~
SAO TEST FOR EACH PRODUCT TERM
SAl TEST FOR EACH PRODUCT TERM
SAl FOR EACH PRODUCT EQUATION
..
~
MINIMIZATION
TEST VECTORS
•
OPTIMIZATION
,
GENERATE STATE DIAGRAM AND
TRANSITION TABLE FOR STATE
SEQUENTIAL PAL
COMBINATIONAL
PAL
......
FUNCTION TABLE
Figure 7.5.6 Test Vector and Function Table Creating Steps
134
Programmable Logic Design Guide
Before going to the next section, a few conventions are defined. First, only the following symbols can be accepted in the test vectors or function table:
H-Logic High
L-Logic Low
X-Irrelevant "Don't Care"
Z-High Impedance
C-Clock
?-Undetermined
o and I can be treated as Low and High.
Second, let's consider a general logic equation (or product equation)
O} =PI +P2 +P3
where O} is the output; PI, P2 and P3 are the product terms.
If PI =I} * 12 * 113
P2 = 112 * 13 * IS
P3 = 16 * lIs * 119
where I}, 12, 13, 15, 16, Is and 19 are inputs.
Then the output O} will be
O}
= I}
* 12 * 113 + 112 * 13 * 15 + 16 * lIs * 119
where, I}, 12, 113, 15, 16, lis, 119 are called factors.
Consider a particular test vector, VI, which will cause the product term PI to be
high and the product terms P2 and P3 to be low. In this case the output, OJ, will be
high. Now, if a fault is created by the PAL device which causes PI to be low, then the
output, OJ, will be low which is different from the fault-free condition. This fault condition is called "stuck at 0" (SAO) fault. Thus, the vector, VI, is able to detect the product term, PI, for the SAO fault and we can say that VI covers PI for the SAO fault.
In order to get PI to be high, all factors of PI should be high (Le., I}, 12 and 113 are
high). Both 12 = high and 113 = high will cause P2 to be low no matter what 15 is. Therefore, the vector of:
I} 12 13 14 15 16 17 Is 19 110 111 112 O} 02 03 04 05 06
HHLXXLXXX X
X
X
H
X
X
X
X
X
will cover PI for the SAO fault.
Similarly, if there is another vector, V2, which causes PI to be lowt (only one factor of PI is low, the other factors of PI are high) provided that P2 and P3 are low, then
the output, OJ, is low. Now if a fault is created by the PAL device which causes PI to be
high then the output, OJ, will be high which is different from the fault-free condition.
t To talk about letting a product term which is under test be low means that we only force one factor of this term to be low
and the other factors should remain high.
Testing and Reliability
135
This fault condition is called "stuck at I" (SAl) fault. Thus, the vector, V2, is able to
detect the product term, PI, for SAl fault and we can say that V2 covers PI for SAl
fault.
For example, if II is low, 12 and 113 are high, the PI is low. Therefore the vector of
II 12 13 14 15 16 17 Is 19 110 III 112 01 02 03 04 05 06
LHLXXLXXXXXX L X X X X X
will cover PI for the SAl fault.
Similarly, the following vectors will cover PI for the SAl fault, too.
II 12 13 14 15 16 17 Is 19 110 III 112 0 1 02 03 04 05 06
HLLXXLXXXXXX L X X X X X
HHHXXLXXXXXX L XX X X X
To get an SAl fault test for a product equation, generate a vector which sets all the
factors in each product term to be low. The output of this product equation will then
be low. If a fault is created by an AND or OR gate of the PAL device which causes the
product term to be high, then the output will be high, which is different from the faultfree condition. For example, ifI 1, 12, 113, 15, 16, lIs, 119 are low, then the following vector
will cover equation 01 for an SAl fault.
.
II 12 13 14 15 16 17 Is 19 110 III 112 01 02 03 04 05 06
LLHXLLXHHXXX L X X X X X
A good function table should cover all of the product terms for the SAO and SA I
faults. The Product Term Coverage (PTC) is calculated as:
PTC =
Total # of SAO Faults Tested + Total # of SAl Faults Tested
2 x Total Number of Product Terms
x 100 (%)
To achieve 100% PTC is the goal of generating a function table. PALASM version
1.5 and up will inform the user of:
• Total number of SAl faults tested
• Total number of SAO faults tested
• Product term coverage (PTC)
In case all the product terms are not covered, the user receives a message which
tells him the product term and the type of fault for which it was not tested (e.g., "Product P2 ofEQN I Untested (SAO) FaUlt"). This implies that the user must update the function table by induding vectors which will cover product terms for the faults.
-.-.
136
Programmable Logic Design Guide
7.6 EXAMPLES OF TESTING
Example 1: Combinational PAL12H6
PAL12H6
PTAN301
Tom Wang
Portion of random control logic for 8086 CPU board
PD EN ED EA S 1 SA E 1 DO DE GND SO NC3 NO C3 HA SS LA MW PW VCC
(1)
MW=/SO+PW * DE
(2)
LA = ISA * IDa
(3)
SS=Sl * PD * ISA
(4)
HA = S1 * PD * ISA * EA * E 1
(5)
C3 = PD * ED * EA
NO = PD * lEN
Description
This is a portion of random control logic for 8086 CPU board. See (Figure 7.5.7).
:: --~r--"»)o---r->-cD______
MW
S O - - - - -........
)0-------
NO
J-------
C3
PO - -..n~~~---I--""""-...".
EN
ED
----------1-~
----------1----1
+-..
SA _ _ _ _ _ _ _ _ _
HA
EI
---------~--~~
SI
---------~==[)-J--I>o-- ss
SA
-...--1 ~~----........
DO -------------------~__'
Figure 7.5.7
Logic Circuit of Example 1
LA
Testing and Reliability
137
The generation of function table is described in the following steps:
Step 1: Get Test Vector Coding Form; Fill in the input and output names.
Step 2: Exercise the product term 1 (ISO) of equation 1.
SAO Fault Testing: Let PTl be high and PT2 be low, then the output of equation 1, MW, should be high; so, we get vector 1.
SAl Fault Testing: Let PT1 and PT2 be low, then the output of equation 1, MW
should be low; so we get vector 2.
Step 3: Exercise product term 2 (PW * DE) of equation 1.
SAO Fault Testing: Let PT1 be low and PT2 be high, then the output of equation 1, MW, should be high (Le., vector 3).
SAl Fault Testing: Let PT1 and PT2 be low, then the output of equation 1,
MW, should be low.
Since PT2 consists of two factors, PW and DE, we create two SAl test vectors
(i.e., vectors 4 and 5).
Step 4: SAl Fault Testing for product equation 1.
Let PT1 and PT2 be low, then the output of equation 1, MW, should be low
(i.e., vector 6).
This step is similar to the SAl test in step 3 but is different, since all the factors
in this equation were set to be low.
Step 5: Exercise product term 1 (lSA * IDO) of equation 2.
SAO Fault Testing: Let PTl be high, then the output LA should be high.
SAl Fault Testing: Let PT1 be low, then the output LA should be low.
So, we get vectors 7, 8, and 9 in Table 7.5.2
Step 6: SAl fault test for product equation 2, we get vector 10.
Step 7: Continue to exercise the rest of the product terms, completing all 31 test vectors (Table 7.5.2).
Step 8: Optimize the test vectors to get the function table.
1) Because of vector 2, we don't need vectors 4 and 6.
2) Combine vectors 7-10 with vectors 1-6.
3) Rearrange vectors 11-15, then combine with the preceding vectors.
4) Merge vectors 28-31 with vectors 23-27.
5) This results in only 17 vectors (Table 7.5.3).
6) These 17 vectors can still be minimized by comparison and intuition to get
only 7 vectors (Table 7.5.4).
7) By inserting "X" into unused spaces, the result is Table 7.5.5, which is the
function table.
-'..-
138
Programmable Logic Design Guide
Inputs
PO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
EN ED EA SI
SA
EI
L
H
Outputs
DO DE SO NC3 PW
NO
C3
HA
SS LA MW
X
L
L
X
H
L
L
H
H
H
H
H
H
L
L
L
H
H
L
L
H
L
H
L
L
H
H
L
L
L
H
L
H
H
L
H
L
H
L
L
H
L
H
L
L
H
H
H
L
L
L
H
L
H
H
H
L
H
H
H
L
L
H
L
L
H
H
L
H
L
H
H
H
H
H
L
H
L
H
L
H
L
H
H
H
L
L
L
L
L
H
L
L
H
H
H
L
H
H
L
H
H
L
H
L
H
L
H
H
L
L
L
L
L
H
L
L
H
L
L
L
H
H
L
L
H
L
Table 7.5.2
Test Vectors
Testing and Reliability
PD EN ED EA SI
SA
Inputs
EI DO DE SO NC3 PW
NO
C3
HA
Outputs
SS LA MW
1
H
H
L
L
X
L
L
H
H
2
H
H
H
L
X
H
L
L
L
L
3
H
L
L
H
H
H
H
L
L
H
H
L
H
H
L
L
L
4
L
L
H
5
L
H
L
L
6
H
H
H
L
H
H
7
H
H
L
L
H
L
8
L
H
H
L
H
L
9
H
H
H
H
H
L
10
H
L
H
L
H
L
11
H
H
H
L
L
L
12
L
L
L
H
L
L
13
H
L
H
H
H
H
14
L
L
H
H
L
L
15
H
H
L
H
L
16
H
H
L
17
L
L
L
H
H
L
L
L
L
Table 7.5.3 Test Vectors
PD EN ED EA SI
SA
Inputs
EI DO DE SO NC3 PW
NO
C3
HA
Outputs
SS LA MW
1
H
L
H
H
H
L
H
L
X
L
L
H
H
H
H
H
2
H
H
L
H
H
H
H
L
X
H
L
L
L
L
L
L
L
3
H
H
L
L
H
H
H
H
H
L
L
L
H
H
L
H
H
L
L
4
L
H
L
L
L
H
L
5
L
L
H
H
H
L
H
6
H
L
H
L
H
7
H
H
H
L
L
H
L
L
L
L
L
L
L
L
L
L
L
Table 7.5.4 Final Test Vectors
H
139
140
Programmable Logic Design Guide
PD EN ED EA
SI
Inputs
SA EI DO DE SO NC3 PW
1
H
L
H
H
H
L
H
L
2
H
H
L
H
H
H
H
L
X
X
H
3
H
X
X
H
L
L
H
H
H
H
4
L
H
L
L
L
H
L
H
L
H
5
L
L
H
H
H
L
H
6
H
L
H
L
H
H
X
X
H
7
X
H
H
L
L
X
X
X
X
X
X
X
X
X
L
Table 7.5.5
X
X
X
X
X
X
X
Outputs
NO C3 HA SS LA MW
L
H
H
H
H
H
L
L
L
L
L
L
H
L
H
X
X
L
L
L
H
H
L
L
L
L
L
L
X
X
X
L
L
L
L
X
X
L
L
X
L
X
X
X
X
X
X
X
X
Final Function Table
The following are printouts of PAL device design specifications, function table, pinout
list, fuse map, simulation result, and fault testing result. We get 100% PTe!
PALASM VERS ION 1. 5
PALl2H6
PTAN301
TOM WANG
PORTION OF RANOOM CONTROL LOGIC FOR 8086 CPU BOARO
PO EN ED EA SI SA El 00 DE GNO SO NC3 NO C3 HA SS LA
MW PW VCC
MW = ISO + PW*OE
LA = ISA* IDa
5S = 51*PO*/SA
HA = 51 *PO* ISA*EA*El
C3 = PO*EO*EA
NO = PO* lEN
FUNCTION TABLE
PO EN ED EA SI SA El DO DE SO NC3 PW NO C3 HA SS LA MW
HLHHHLHLXLXLHHHHHH
HHLHHHHLXHXLLLLLLL
HXXHLLHHHHXHXXLLLH
LHLLLHLHLHXHLLLLLL
LLHHHLHXXXXXLLLLXX
HXHLHLHXXXXXXLLXXX
HXXHHLLXXXXXXXLXXX
OE SCR I PT ION
PORTION OF RANOOM CONTROL LOG IC FOR 8086 CPU BOARD
Testing and Reliability
141
TOM WANG
.***.********.*
PO
****
* 1*
•••*
.*
EN
ED
EA
********.**.*.
*
* *
****
PAL
*20*
1 2 H 6
****
*
*•••
****
* 2*
*19*
****
*
••••
****
5A
****
*18*
MW
***.
*
••••
*
••••
* 4*
*17*
LA
****
****
* 3*
***.
*
*.**
.***
* 5*
*16*
***.
*
*.*.
*
***.
*15*
* 6*
••••
*
****
****
*14*
* 7*
••• *
*
****
*13*
* 8*
•••*
••••
NO
*
*
.***
****
* 9*
*12*
****
****
Ne3
*
*
GND
e3
.*~*
*
DE
HA
****
•••*
DO
55
****
*
El
PW
*
*
51
vee
****
** ••
*10*
*11*
***.
SO
****
*
*
**************.*.**************
8
9
10
11
12
TOM WANG
1 10111010XXOXHHHHHH01
2 11011110XX1XLLLLLL01
3 1XX100111X1XXXLLLHll
4 010001010X1XLLLLLLl1
5 0011101XXXXXLLLLXXX1
6 1X10101XXXXXXLLXXXX1
7 1XXll00XXXXXXXLXXXX1
PASS SIMULATION
8
49
TOM WANG
11 1111 1111 2222 2222 2233
0123 4567 8901 2345 6789 0123 4567 8901
BEG*FPLT
a 0000
1 0000
2 0000
3 0000
4 0000
5 0000
6 0000
7 0000
PALl2H6
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
8
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
---x 150
------XXXX
XXXX
0000
13 0000
14 0000
15 0000
---- --00
--00
XXXX XXOo
XXXX XXOO
0000 0000
0000 0000
0000 0000
0000 0000
--00
--00
XXOo
XXOO
0000
0000
0000
0000
--00
--00
XXOo
XXOO
0000
0000
0000
0000
--00
--00
XXOo
XXOO
0000
0000
0000
0000
------XXXX
XXXX
0000
0000
0000
0000
XXXX
XXXX
0000
0000
0000
0000
16
17
18
19
20
21
22
23
---XXXX
0000
0000
0000
0000
0000
0000
---XXXX
0000
0000
0000
0000
0000
0000
--00
XXOO
0000
0000
0000
0000
0000
0000
--00
XXOO
0000
0000
0000
0000
0000
0000
-XOO
XXOO
0000
0000
0000
0000
0000
0000
--00
XXOO
0000
0000
0000
0000
0000
0000
-X-XXXX
0000
0000
0000
0000
0000
0000
---- ISA* lOa
XXXX
0000
0000
0000
0000
0000
0000
24
25
26
27
28
29
30
31
--XXXXX
0000
0000
0000
0000
0000
0000
---XXXX
0000
0000
0000
0000
0000
0000
--00
XXOO
0000
0000
0000
0000
0000
0000
X-OO
XXOO
0000
0000
0000
0000
0000
0000
-XOO
XXOO
0000
0000
0000
0000
0000
0000
--00
XXOO
0000
0000
0000
0000
0000
0000
---XXXX
0000
0000
0000
0000
0000
0000
---- Sl*PO*ISA
XXXX
0000
0000
0000
0000
0000
0000
--x-
x---
PW*OE
142
Programmable Logic Design Guide
32
33
34
35
36
37
38
39
--xXXXX
0000
0000
0000
0000
0000
0000
---XXXX
0000
0000
0000
0000
0000
0000
X-OO
XXOO
0000
0000
0000
0000
0000
0000
X-OO
XXOO
0000
0000
0000
0000
0000
0000
-XOO
XXOO
0000
0000
0000
0000
0000
0000
X-OO
XXOO
0000
0000
0000
0000
0000
0000
---XXXX
0000
0000
0000
0000
0000
0000
---- Sl*PD*/SA*EA*El
XXXX
0000
0000
0000
0000
0000
0000
40
41
42
43
44
45
46
47
--XXXXX
0000
0000
0000
0000
0000
0000
X--XXXX
0000
0000
0000
0000
0000
0000
X-OO
XXOO
0000
0000
0000
0000
0000
0000
--00
XXOO
0000
0000
0000
0000
0000
0000
--00
XXOO
0000
0000
0000
0000
0000
0000
--00
XXOO
0000
0000
0000
0000
0000
0000
---XXXX
0000
0000
0000
0000
0000
0000
---- PD*ED*EA
XXXX
0000
0000
0000
DODO
0000
0000
48
49
50
51
52
53
54
55
-XXXXX X
XXXX
XXXX
0000
0000
0000
0000
---XXXX
XXXX
XXXX
0000
0000
0000
0000
--00
XXOO
XXOO
XXOO
0000
0000
0000
0000
--00
XXOO
XXOO
XXOO
0000
0000
0000
0000
--00
XXOO
XXOO
XXOO
0000
0000
0000
0000
--00
XXOO
XXOO
XXOO
0000
0000
0000
0000
---XXXX
XXXX
XXXX
0000
0000
0000
0000
---- PO*/EN
XXXX
XXXX
XXXX
0000
0000
0000
0000
56
57
58
59
60
61
62
63
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
ENO*fPLT
LEGENO:
X: fUSE NOT BLOWN (L,N,O)
PHANTOM fUSE
(L,N,O)
o:
NUMBER Of fUSES BLOWN =
fUSE BLOWN
(H,P,l)
PHANTOM fUSE (H,P,l)
a
206
TOM WANG
1
2
3
4
5
6
7
101l1010XXOXHHHHHHOl
1l01l1l0XX lXLLLLLLOl
lXX100lllX1XXXLLLHll
010001010X1XLLLLLL1l
0011l01XXXXXLLLLXxxl
lX10101XXXXXXLLXXXXl
lXXllOOXXXXXXXLXXXXl
49
PASS SIMULATION
NUMBER Of STUCK AT ONE (SAl)
8
fAULTS ARE =
7
NUMBER Of STUCK AT ZERO (SAO) fAULTS ARE =
7
PRODUCT
TERM
COVERAGE
=100%
Testing and Reliability
143
The differences between sequential and combinational circuits have been discussed. The output of sequential circuits is a function not only of the present inputs,
but the previous outputs.
There are two kinds of outputs in the sequential PAL device: registered output, and
non-registered output. For example, pin 14 of the PAL16R4 is a registered output;
pin 13 is a non-registered output. Different combinations of registered outputs are
defined as different states. Each present-state is related to the present inputs and previous state, so the function table vectors need to be arranged in proper sequential
order.
Furthermore, since the previous state is obtained from the previous vector, it is
necessary to "initialize" the registers to a "known state". (Output is a function of the
inputs but is independent of the previous state, similar to a clear or preset function).
The following is an example of the sequential PAL16R4. Referring to Figure 7.5.6,
generate the state diagram and state transition table to derive the proper function table.
Example 2: Sequentiall?AlL16R4
PAL16R4
PTAN302
Tom Wang
Op code analyzer
CLK 12B12
12B23 IB2Bl IB2B3 13B IB3B IBIB GND lEN FIST IILLOP
IA
/17
IRD
F23
VCC
If (VCC) IFIST = F23
; (1)
If (VCC) ILLOP = IA * IB * IC
; (2)
C: = A * IB * IC * IB3B + IA * IB * C * IB2B2 + RD + A * B * C * IBIB + A * IB * C *
IB2B3 * 13B + IA * B * IB2Bl
; (3)
B: = A * IB * IC * IB3B + IA * IB * C * IB2B2 + RD + A * B * C * IBlB * 12B23 +
A * IB * C * IB2B3 + IA * B * IB2Bl
; (4)
A:=A * IB * IC * IB3B+IA * IB * C * IB2B2+RD+A * B * C * IBIB * 12B12 +
A * IB * C * IB2B3 + IA * B * IB2Bl + B * IC
(5)
IC
IB
17:=A*B*C
If (VCC) IF23 = IA * IB * IC + A * B * C
(6)
(7)
Description
The function of this PAL device is to analyze the incoming op code.
The generation of the function table is described in the following steps:
Step 1:
Get test vector coding form. Fill in the input and output names. Since the
outputs C, B and A act as inputs as well, they appear on both sides and are
considered first because they feed back to themselves. Therefore, equations
3, 4, and 5 are exercised first.
144
Programmable Logic Design Guide
Step 2:
Exercise product term 1 of equation 3.
SAO Fault Testing: Let PTl (A * IB * IC * 1B3B) be high and PT2, 3, 4,5, and
6 be low; the output of equation 3 should be high; so, we
get vector 1 in Table 7.5.6.
SAl Fault Testing: Let PTl, 2, 3, 4, 5, and 6 be low; the output of equation 3
should be low; so, we get vectors 2, 3, 4, and 5 in Table
7.5.6.
Step 3:
Exercise product term 2 of equation 3.
SAO Fault Testing: Let PT2 be high and PTl, 3, 4, 5, and 6 be low; the output
of equation 3 should be high; so, we get vector 6 in Table
7.5.6.
SAl Fault Testing: Let PTl 2,3,4,5, and 6 be low; the output of equation 3
should be low; so, we get vectors 7, 8, 9, and 10 in Table
7.5.6.
Step 4:
Exercise product term 3 of equation 3 (only SAO fault testing is needed).
SAO Fault Testing: Let PT3 be high and PTl, 2, 4, 5, and 6 be low; the output
of equation 3 should be high; so, we get vector 11 in Table
7.5.6.
Step 5:
Continue to exercise the rest of the product terms, completing all of
equation 3.
Step 6:
SAl fault test for product equation 3; so, we get vector 25.
Step 7:
Repeat step 2 through step 6 for equation 4; i.e.,
SAO Fault Testing: Let PTl be high and PT2, 3,4,5, and 6 be low; the output
of equation 4 should be high.
SAl Fault Testing: Let PTl, 2, 3, 4, 5, and 6 of equation 4 be low, the output
of equation 4 should be low.
SAO Fault Testing for PT2, SAl Fault Testing for PT2.
SAO Fault Testing for PT3, SAl Fault Testing for PT3.
SAO Fault Testing for PT4, SAl Fault Testing for PT4.
SAO Fault Testing for PT5, SAl Fault Testing for PT5.
SAO Fault Testing for PT6, SAl Fault Testing for PT6.
SAO Fault Testing for equation 4.
So, we get vectors 26 to 50.
Step 8:
Repeat step 2 through step 6 for equation 5: i.e.,
SAO Fault Testing: Let PTl be high and PT2, 3, 4, 5, 6, and 7 be low; the output of equation 5 should be high.
SAl Fault Testing: Let PTl, 2, 3, 4, 5, 6, and 7 of equation 5 be low; the output of equation 5 should be low.
SAO Fault Testing for PT2, SAl Fault Testing for PT2.
SAO Fault Testing for PT3, SAl Fault Testing for PT3.
SAO Fault Testing for PT4, SAl Fault Testing for PT4.
Testing and Reliability
Inputs
ClK 2B12 2B23 B2Bl B2B2 B2B3 3B B3B BIB EN C B A RD
1
l
l L H L
2
L
L L L L
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
37
37
38
39
Outputs
IlLOP C B A 17 F23
H
L
L
L H H
L
L
L
H L H
L
L
H
L L H
L
L
L
H L L
L
H
L
H L H
L
L
L
H H L
L
L
L
L L L
L
L
H
H L L
L
L
H
H
L
H H H
L
H
L
H H L
L
L
L
H L H
L
L
L
L H H
L
L
H
H H H
L
L
L
H
L
L
H L H
L
L
H L L
L
L
L
L
H H H
L
L
L
L
L L H
L
L
L
H
H L H
L
L
H
L
H L H
L
L
H L
L
H
L
H
H
RIST
H L
L
L
H H L
L
L
L
L L H
L
L
L L L
L
L
L
L H H
L
L
L
H L H
L
L
H
L L H
L
L
L
H L L
L
H
L
H L H
L
L
L
H H L
L
L
L
L L L
L
L
H
H L L
H
H
H
H
H
H
L
L
H
H
H
L
L
H H H
L
L
L
H H L
L
L
L
L
H L H
L
L
Thble 7.5.6 Test Vectors
145
146
Programmable Logic Design Guide
Inputs
ClK
Outputs
2B12 2B23 B2Bl B2B2 B2B3 3B B3B B1B EN C B A RD
RIST
IllOP
C
B A 17 F23
40
41
L
L
L H H
L
L
H
H H H
L
L
42
43
H
L
H H H
L
L
L
L
H L H
L
H
44
L
H L L
L
L
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
L
H H H
L
L
L
L L H
L
L
H
H L H
L
L
L
H L
L
H
H
H L
L
L
H
H H L
L
L
L
L L H
L
H
L
L L L
L
L
L
H L H
L
L
H
L L H
L
L
L
H L L
L
H
L
H L H
L
L
L
H H L
L
L
L
L L L
L
L
H
H L L
L
L
65
66
67
H
H
H
H
H
H
H
L
L
H H H
L
H
L
L
H H L
L
L
L
L
H L H
L
L
L
H
H H H
L
L
H
L
H H H
L
L
L
H L H
L
H
L
H L L
L
L
68
69
L
H H H
L
L
L
L L H
L
L
70
H
H L H
L
L
H L
L
H
H L
71
72
73
74
L
H
H
H
H
H
H
H
L
L
L H
L
H
H H L
L
L
Table 7.5.6 Test Vectors Continued
Testing and Reliability
147
SAO Fault Testing for PT5, SAl Fault Testing for PT5.
SAO Fault Testing for PT6, SAl Fault Testing for PT6.
SAO Fault Testing for equation 5.
So, we get vectors 51 to 74.
Step 9:
Minimize the vectors following these rules:
1) Vectors which have same inputs can be combined to be one vector.
2) If the inputs of a vector are subsets of another vector's inputs, then they
can be combined to form one vector.
So, vectors 1, 26, and 51 can be combined to one vector 1 in Table 7.5.7; vectors 12 and 37 can be combined to one vector 21 in Table 7.5.7, etc.
3) Decide the "?" (undetermined) state in the output by using the inputs and
logic equations (inserting the known values into logic equations).
Therefore, we get Table 7.5.8.
Step 10: Assign the state numbers. See Table '7.5.9, then we get Table 7.5.10.
Step 11: Build the state diagram and transition path (Figure 7.5.8) from the vector
Table 7.5.10.
Step 12: Generate the function table from the state diagram.
1) Be aware of two rules:
a) Generate the initial state first.
b) Generate the function table in sequential order and cover all possible
paths.
2) The value of outputs FIST, ILLOP, 17 and F23 in each test vector can be
derived easily by inserting the previous values of outputs C, B, and A and
the present values of inputs (none in this example) into their corresponding logic equations.
3) We can quickly identify that the RD signal in this example is the initialize
or reset signal, so RD is set high as the first vector in the function table.
4) Finally, insert an "X" into the unused space. We get the function table as
shown in Table 7.5.11.
148
Programmable Logic Design Guide
Inputs
ClK 2B12 2B23 B2Bl B2B2 B2B3 3B B3B B1B EN C B A RD
Outputs
RIST IllOP C B A 17 F23
1
L
L L H
L
2
L
L L L
L
H H H
L L L
3
L
L H H
L
L L H
4
L
H L H
L
L L L
5
H
L L H
L
L L L
H H H
6
L
H L L
L
7
L
H L H
L
L L L
8
L
H H L
L
L L L
9
L
L L L
L
L L L
10
H
H L L
L
L L L
X X X
H
H H H
12
L
L
H L H
L
H H H
13
L
L
H L L
L
L L L
14
L
L
H H H
L
L L L
11
15
L
L
L L H
L
L L L
16
L
H
H L H
L
L L L
H
L
H L H
L
L L L
X H L
L
H H H
L L L
17
L
18
H
19
20
H
H
H
H
H
H
H
X H L
L
H
H H L
L
L L L
L
H H ?
21
L
L
H H H
22
L
L
H H L
L
L L ?
23
L
L
H L H
L
L L ?
24
L
L
L H H
L
L L ?
25
L
H
H H H
L
L L ?
26
H
L
H H H
L
H L ?
H ? H
27
L
L
H H H
L
28
L
L
H H L
L
L ? L
29
L
L
H L H
L
L ? L
30
L
H
H H H
L
L ? L
31
H
L
H H H
L
H ? L
L H X
L
? ? H
32
Table 7.5.7 Test Vectors
Testing and Reliability
Inputs
ClK 2B12
2B23
B2B1
B2B2
B2B3
Outputs
3B
B3B B1B EN
C B A
RD
L H
L
l
HIST
IllOP
C B A 17
H H H
1
l
2
L
L L L
L
L L L
3
L
L H H
L
L L H
4
L
H L H
L
L L L
5
H
L L H
L
L L L
6
L
H L L
L
H H H
7
L
H L H
L
L L L
8
L
H H L
L
L L L
9
L
L L L
L
L L L
10
H
H L L
L
L L L
H
H H H
12
L
L
H L H
L
H H H
13
L
L
H L L
L
L L L
14
L
L
H H H
L
L L L
15
L
L
L L H
L
L L L
16
L
H
H L H
L
L L L
17
H
L
H L H
L
L L L
X H L
L
H H H
L L L
11
L
18
X H L
L
H
H H L
L
L L L
L
L
H H H
L
H H H
H H L
H
19
20
H
H
21
L
22
H
H
H
H
H
H
L
L
H H H
L
23
L
L
H H L
L
L L L
24
L
L
L
H L H
L
L L H
H
25
L
L
H L H
L
L L L
26
L
L
L
L H H
L
L L H
27
L
H
L
L H H
L
L L L
28
L
H
H H H
L
L L L
L
H H H
L
H L H
L
H H H
L
30
H
H
'H
L
H L L
31
L
L
L
H H H
L
H H H
32
L
H
L
H H H
L
H L H
33
L
L
H H L
L
L L L
34
L
L
H L H
L
L H L
35
L
l
L L L
36
L
37
H
38
H
29
L
L
H L H
H
H H H
L L L
L
L
H H- H
H H L
H
L
H H H
H L L
L H H
L L H
H
39
40
H
L H X
L L H
41
L
L H L
H H H
Table 7.5.8
Test Vectors
F23
149
150
Programmable Logic Design Guide
State #
C
B
A
H
H
H
1
H
H
L
2
3
L
L
L
H
L
L
4
H
L
H
5
L
H
H
6
L
L
H
7
L
H
L
8
Table 7.5.9
State Assignment
Inputs
Outputs
ClK 2812 2823 8281 8282 8283 38 B38 818
EN
C
8
A
RD
RIST IllOP C 8 A 17 F23
1
C
L
H
7
7
7
L
1 1 1
2
C
L
H
3
3
3
L
333
3
C
L
H
6
6
6
L
777
4
C
L
H
5
5
5
L
333
5
C
H
H
7
7
7
L
333
6
C
L
H
4
4
4
L
1 1 1
7
C
L
H
5
5
5
L
333
8
C
L
H
2
2
2
L
333
9
C
L
H
3
3
3
L
333
10
C
H
H
4
4
4
L
333
11
C
H
1 1 1
12
C
L
L
H
5
5
5
L
1 1 1
13
C
L
L
H
4
4
4
L
333
H
14
C
L
L
H
1
1
1
L
333
15
C
L
L
H
7
7
7
L
333
16
C
L
H
H
5
5
5
L
333
17
C
H
L
H
5
5
5
L
333
18
C
L
H 2 or 8 20r 8 2 or 8
L
1 1 1
19
C
H
H 2 or B 2 or 8 2 or B L
333
333
20
C
H
H
H
H
2
2
2
L
21
C
L
L
L
H
1
1
1
L
1 1 1
22
C
H
L
L
H
1
1
1
L
222
H
H
H
H
H
23
C
L
L
H
2
2
2
L
333
24
C
L
L
L
H
5
5
5
L
777
25
C
L
H
L
H
5
5
5
L
333
26
C
L
L
L
H
6
6
6
L
777
27
C
L
H
L
H
6
6
6
L
333
28
C
L
H
H
1
1
1
L
333
Table 7.5.10 Transition Thble
Testing and Reliability
Inputs
Outputs
ClK 2B12 2B23 B2Bl B2B2 B2B3 3B B3B B1B EN
C
B
A
RO
KIST IllOP C B A 17 F23
29
C
L
H
L
H
1
1
1
L
555
30
C
H
H
L
H
1
1
1
L
444
31
C
L
L
L
H
1
1
1
L
1 1 1
32
C
L
H
L
H
1
1
1
L
555
333
33
C
L
L
H
2
2
2
L
34
C
L
L
L
H
5
5
5
L
888
35
C
L
H
L
H
5
5
5
L
333
36
C
L
H
H
1
1
1
L
333
37
C
H
L
L
H
1
1
1
L
222
38
C
H
H
L
H
1
1
1
L
444
39
C
H
6
6
6
L
777
40
C
H
H 8 or 6 8 or 6 8 or 6
L
777
41
C
L
H
L
1 1 1
42
C
L
ZZZ
8
8
L
8
Table 7.5.10 Transition Table Continued
FUNCTION TABLE
ClK /2B12 /2B23 /8281 /B282 /8283 /38 /B3B /B18 /EN F1ST
/IlLOP /C /B /A /17 /RO F23
Cx x x x x x x XL HH l L l l l l
C L H X X X X X H L L H L L Hl H H
C X XH X X X X X L H H L L L H H L
C L H XX X X XH L L H L L H L H H
C XXL XXXXX L HL HHHHHL
C Xx x Xx x x XL HH L L L HL L
C L L XX X X XH L L H L H H L H H
C X x XH X X X X L H H L L L H H L
C L L XX X X XH L L H L H H L H H
C Xx X L X X X X L H L H H H H H L
C Xx x Xx x x X L HH L L L HL L
C H L XX X X XH L L H L H L L H H
C Xx x X H H X X L H H L L L H H L
C HL XXXXXH L L H L H L L HH
C Xx x XL XXX L HL HHHHHL
C Xx x XXXXX L HH L L L HL L
C HL XXXXXH L L H L H L L HH
C XX X XH L X X L L H H L L H H H
C XX X X X X XX L L H H H L H H H
C XX X X X X L X L H L H H H H H L
C X X X X X X XX L H H L L L H L L
C H L X X X X XH L L H L H L L H H
C Xx XXH L XX L L HH L L HHH
C Xx x x XXXX L L HHH L HHH
C X X XX X X H X L H H L L L H H L
C XXXXXXXL L HL HHH L HL
C XXXXXXXXL HHL L L H L L
C H H XX X X XH L H H L L L L L L
OESCRI PTION
OP CODE ANALYZER
Table 7.5.11
Final Function Table
151
152
Programmable Logic Design Guide
Now we can get any test sequence we like Just by
following the state transition. The first vector
should be the initialize vector and, by intuition,
we know state CD Is the Initialize state.
Figure 7.5.8 State Diagram
The following are printouts of PAL device design specifications, function table, pinout
list, fuse map, simulation result, and fault testing result. We get 100% PTC!
PAlASM VERSION 1.5
PAl16R4
PTAN302
TOM WANG
OP CODE ANALYZER
ClK 12B12 12B23 IB2Bl IB2B2 IB2B3 13B IB3B IBIB GND
lEN FIST IIllOP IC IB IA 117 IRD F23 VCC
IF (VCC)/FIST - F23
IF (VCC)IllOP c IA*/B*/C
C:-A*/B*/C*/B3B + IA*/B*C*/B2B2 + RD + A*B*C*/BIB +
A*/B*C*/B2B3*/3B + IA*B*/B2Bl
B:-A*/B*/C*/B3B + IA*/B*C*/B2B2 + RD + A*B*C*/BIB*/2B23
A*/B*C*/B2B3 + IA*B*/B2Bl
A:=A*/B*/C*/B3B + IA*/B*C*/B2B2 + RD + A*B*C*/B18*/2B12
A*/B*C*/B2B3 + IA*B*/B2Bl + B*/C
17:- A*B*C
IF(VCC)/F23 =/A*/B*/C + A*B*C
+
+
Testing and Reliability
TOM WANG
**************
*
CLK
****
* 1*
****
12B12
12823
182Bl
18282
18283
!38
1838
181B
GNO
*
****
* 2*
****
*
****
* 3*
****
*
****
* 4*
****
*
****
* 5*
****
*
****
* 6*
****
*
****
* 7*
****
*
****
* 8*
****
*
****
* 9*
****
*
****
*10*
****
*
**************
**
PAL
1 6 R4
*
****
*20*
****
*
****
*19*
****
*
****
*18*
****
*
****
*17*
****
*
****
*16*
****
*
****
"*15*
****
*
****
*14*
1 CXXXXXXXXXOHHLLLLOLI
2 COIXXXXXIXOLHLLHLIHI
3 CXXIXXXXXXOHHLLLH1L1
4 C01XXXXXIXOLHLLHLIHl
5 CXXOXXXXXXOHLHHHHILI
6 CXXXXXXXXXOHHLLLHOLI
7 COOXXXXXIXOLHLHHLIHI
8 CXXXIXXXXXOHHLLLHILI
9 COOXXXXXIXOLHLHHLIHI
10 CXXXOXXXXXOHLHHHHILI
11 CXXXXXXXXXOHHLLLHOLI
12 CI0XXXXX1XOLHLHLLIHI
13 CXXXX11XXXOHHLLLHIL1
14 C10XXXXX1XOLHLHLLIHI
15 CXXXXOXXXXOHLHHHHILI
16 CXXXXXXXXXOHHLLLHOLI
F23
IRQ
/17
IA
IB
IC
****
*
****
*13*
****
*
****
*12*
****
*
****
*11*
****
*
*******************************
TOM WANG
VCC
/ILLOP
FlST
lEN
153
154
Programmable Logic Design Guide
17
18
19
20
21
22
23
24
25
26
27
28
CI0XXXXXIXOLHLHLLIHI
CXXXXIOXXXOLHHLLHIHI
CXXXXXXXXXOLHHHLHIHI
CXXXXXXOXXOHLHHHHILI
CXXXXXXXXXOHHLLLHOLI
CI0XXXXXIXOLHLHLL1Hl
CXXXX10XXXOLHHLLHIH1
CXXXXXXXXXOLHHHLH1Hl
CXXXXXXIXXOHHLLLHILI
CXXXXXXXOXOHLHHHLILI
CXXXXXXXXXOHHLLLHOLI
CI1XXXXXIXOHHLLLLOLl
PASS SIMULATION
29
672
TOM WANG
11 1111 1111 2222 2222 2233
0123 4567 8901 2345 6789 0123 4567 8901
BEG*FPLT PAL16R4
B
o ---- ---- ---- ---- ---- ---- ---- ----
I ---- ---- ---- --x- --x- --x- ---- ---- /A*/B*/C
2 ---- ---- ---- ---x ---x ---x ---- ---- A*B*C
3
XXXX XXx X XXXX xxxx XXXX XXXX XXXX XXXX
5
XXXX XXX X XXXX XXXX XXXX XXXX XXXX XXXX
4 XXXX XXX X XXXX XXXX XXXX XXXX xxx x XXXX
6 xxxx XXXX xxxx xxxx XXXX xxxx xxx x xxx X
7 xxx X XXXX xxxx xxxx xxxx XXXX XXXX XXXX
8 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
9 XXXX XXX X XXXX XXXX XXXX XXXX XXXX XXXX
10
11
12
13
14
15
XXXX
XXXX
XXXX
XXXX
xxxx
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
xxxx
xxxx
XXXX
XXXX
XXXX
16
17
18
19
20
21
22
23
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
24
25
26
27
28
29
30
31
---------X------------
---- ---- ---x --X- --X- X--- ---- A*/B*/C*/B3B
---- ---- X-X- "-X- ---x ---- ---- /A*/B*C*/B2B2
-------------
A*B*C*/B1B*/2B12
A*/B*C*/B2B3
/A*B*/B2Bl
B*/C
32
33
34
35
36
37
38
39
-------------------
---- ---- ---x --~- --X- X--- ------- ---- X-X- --X- ---x ---, ------x ---- ---- ---- ---- ---- ---X--- ---- ---x ---x ---x ---- X------ ---- ---x X-X- ---x ---- ------- X--- --X- ---x ---- "--- ----
A*/B*/C*/B3B
/A*/B*C*/B2B2
---- ---- ----
XXXX
XXXX
XXXX
XXXX
Xxxx
Xxxx
XXXX
XXXX
XXXX
XXXX
Xxxx
xxxx
XXXX
XXXX
XXXX
XXXX
xxxx
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
xxxx
XXXX
XXXX
XXX X
XXXX
xxxx
xxxx
---x ---x ---x ---- ----
xxxx xxxx xxxx
XXXX XXXX XXXX
XXXX XXXX XXXX
XXXX XXXX XXXX
XXXX XXXX XXXX
XXXX XXXX XXXX
XXX X XXX X XXXX
xxxx
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
xxxx
XXXX
XXxx
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
xxx X
XXXX
XXXX
XXXX
---x ---- ---- ---- ---- ---- ------- ---x ---x ---x ---- X------ ---x X-X- ---x ---- ---X--- --X- ---x ---- ---- ------- ---- ---x --X- ---- ----
xxxx XXXX XXXX XXXX XXXX XXXX XXXX XXXX
XXXX XXXX XXXX XXXX XXXX XXXX XXX X XXXX
XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
A*B*C
RD
RD
A*B*C*/BIB*/2B23
A*/B*C*/B2B3
/A*B*/B2B1
Testing and Reliability
40
41
42
43
44
45
46
47
------------------XXXX
XXXX
---- ---- ---x --X- --X- X--- ---- A*/B*/C*/B3B
---- ---/A*/B*C*/B2B2
RD
---- ---X--- A*B*C*/B1B
---- ---X-X- X--X ---- ---- A*/B*C*/B2B3*/3B
---- X--- --X/A*B*/B2B1
XXXX XXXX XXX X XXXX XXXX XXXX XXXX
XXXX XXXX XXXX XXXX XXXX XXXX XXXX
48
49
50
51
52
53
54
55
------XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
------XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
------XXXX
XXX X
XXX X
XXXX
XXXX
XXX X
-----XXXX X
XXXX
XXXX
XXXX
XXXX
XXXX
-----XXXX X
XXXX
XXXX
XXXX
XXXX
XXXX
-----XXXXX
XXXX
XXXX
XXXX
XXXX
XXXX
------XXXX
XXXX
XXX X
XXXX
XXXX
XXXX
------- /A*/B*/C
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
56
57
58
59
60
61
62
63
-----XXXXX
XXXX
XXXX
XXXX
XXXX
XXXX
------XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
------XXXX
XXXX
XXX X
XXX X
XXXX
XXX X
------XXX X
XXXX
XXXX
XXXX
XXXX
XXXX
------XXXX
XXXX
XXX X
XXXX
XXX X
XXXX
------XXXX
XXXX
XXX X
XXXX
XXXX
XXXX
------XXXX
XXXX
XXX X
XXXX
XXXX
XXX X
------- F23
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
x-x- --x- ---x ---- ------x ---- ---- ---- ---- ---- ------x ---x ---x ------x
---x ---- ---- ----
ENO*FPLT
LEGEND:
X: FUSE NOT BLOWN (L,N,O)
NUMBER OF FUSES BLOWN =
FUSE BLOWN
(H,P,I)
786
TOM WANG
FILE: PTAN302
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
FUSEPLOT A
<<<
NATIONAL SEMICONDUCTOR TIMESHARING SERVICES SVST
CXXXXXXXXXOHHLLLLOLl
COIXXXXXlXOLHLLHLlHl
CXXIXXXXXXOHHLLLHILI
COIXXXXXIXOLHLLHLlHl
CXXOXXXXXXOHLHHHHILl
CXXXXXXXXXOHHLLLHOL1
COOXXXXX1XOLHLHHLIHl
CXXXIXXXXXOHHLLLHILl
COOXXXXX 1XOLHLHHLlH 1
CXXXOXXXXXOHLHHHH1Ll
cxxxXXXXXXOHHLLLHOLl
C10XXXXX1XOLHLHLLlHl
CXXXXllXXXOHHLLLHlLl
CIOXXXXX1XOLHLHLLlHl
CXXXXOXXXXOHLHHHH1Ll
CXXXXXXXXXOHHLLLHOLl
C10XXXXXIXOLHLHLLlHl
CXXXX10XXXOLHHLLH1H1
CXXXXXXXXXOLHHHLH1H1
CXXXXXXOXXOHLHHHH1Ll
CXXXXXXXXXOHHLLLHOLI
C10XXXXX1XOLHLHLLlH1
CXXXX10XXXOLHHLLH1H1
CXXXXXXXXXOLHHHLH1H1
CXXXXXX1XXOHHLLLH1L1
CXXXXXXXOXOHLHHHLlL1
CXXXXXXXXXOHHLLLHOLI
CllXXXXX1XOHHLLLLOLl
PASS SIMULATION
672
NUMBER OF STUCK AT ONE (SAl)
29
FAULTS ARE = 24
NUMBER OF STUCK AT ZERO (SAO) FAULTS ARE = 24
PRODUCT
TERM
COVERAGE
=100%
155
156
Programmable Logic Design Guide
8
Applications *
8.1
BASIC GATES
This example demonstrates how fusable logic can implement the basic inverter, AND
OR, NAND, NOR and exclusive -OR functions. The PAL 12H6 is selected because it has 12
inputs and 6 outputs.
PAL12H6
A--[>---B
Figure 8.1.1 Basic Gates
• Applications contained in this chapter are for illustration purposes only and National makes no representation or
warranty that such applications will be suitable for the use speciJ1ed without further testing or modification.
157
158
Programmable Logic Design Guide
PALASM VERSION 1.5
PALl2H6
TOM WANG
BASIC GATE
NSC SANTA CLARA
C D F G MN P Q I GND
B = IA
E = C*D
H= F + G
J K
L R 0 H E B A VCC
L = II + IJ + IK
o = IM*/N
R = P*/Q + /P*Q
FUNCTION TABLE
ABC D E F G H I J K L MN 0 P Q R
LH
HL
xX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX X
XXX
LLL
L HL
HL L
HH H
XX X
XX X
XX X
XXX
XXX
XXX
XX X
XX X
XX X
XX X
XX X
XXX
XX X
XX X
XX X
XXX
XX X
XXX
X XX
X XX
XXX
XXX
XXX
LLL
L HH
HL H
HHH
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXXX
XXXX
XX XX
XXXX
XXXX
XXX X
XXXX
XXX X
XXXX
XXXX
LLLH
L L HH
L HL H
HL L H
HHH L
XXXX
XXXX
XXXX
XXXX
XXXX
XXX X
X XX X
XXXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
LLH
LHL
HL L
HH L
XXX
XXX
XXX
XXX
X X X ;TEST
X X X ;TEST
X X X ;TEST
X X X ;TEST
X X X ;TEST
X X X ;TEST
X X X ;TEST
X X X ;TEST
X X X ;TEST
X X X ;TEST
X X X ;TEST
X X X ;TEST
X X X ;TEST
X X X ;TEST
X X X ;TEST
X X X ;TEST
X X X ;TEST
X X X ;TEST
X X X ;TEST
L L L ;TEST
L H H ;TEST
H L H ;TEST
H H L ;TEST
INVERTER
INVERTER
AND GATE
AND GATE
AND GATE
AND GATE
OR GATE
OR GATE
OR GATE
OR GATE
NAND GATE
NAND GATE
NAND GATE
NAND GATE
NAND GATE
NOR GATE
NOR GATE
NOR GATE
NOR GATE
EXCLUSIVE
EXCLUSIVE
EXCLUSIVE
EXCLUSIVE
DESCRIPTION
BASIC GATE
************** **************
*
**
*
****
****
PAL
C * 1*
*20*
****
****
1 2 H6
*
*
****
****
*19*
D * 2*
****
****
*
*
****
****
*18*
F * 3*
****
****
*
*
****
****
*17*
G * 4*
****
****
VCC
A
B
E
OR
OR
OR
OR
GATE
GATE
GATE
GATE
Applications
M
*
****
* 5*
****
*
****
* 6*
****
*
*
****
*16*
****
*
****
*15*
****
*
****
****
P * 7*
*14*
****
****
*
*
****
****
*13*
Q * 8*
****
****
*
*
****
****
* 9*
*12*
****
****
*
*
****
****
GND *10*
*11*
****
****
*
*
*******************************
N
H
0
R
L
K
J
BASIC GATE
11 1111 1111 2222 2222 2233
0123 4567 8901 2345 6789 0123 4567 8901
BEG*FPLT PAL12H6
8
9
10
11
8
---- ---x --00 --00
xxxx xxxx XXOO XXOO
XXXX XXXX xxoo xxoo
XXXX XXXX XXoo XXoo
--00
XXOO
xxoo
XXoo
--00
XXOO
xxoo
XXoo
---/A
xxx x xxxx
xxxx xxxx
XXXX XXXX
16 X-X- ---- --00 --00 --00 --00 ---- ---- C*D
17 XXXX XXXX XXOO XXOO XXOo XXOO XXXX XXXX
24 ---- X--- --00 --00 --00 --00 ---F
25 ---- ---- X-OO --00 --00 --00 ---- ---- G
32
33
40
41
---XXXX
-------
---XXXX
-------
--00
XXOO
--00
--00
-XOO
XXOO
--00
--00
-XOO
XXOO
--00
--00
--00
XXOO
X-DO
-XOO
48
49
50
51
---------XXXX
---------XXXX
--00
--00
--00
XXOO
--00
--00
--00
XXOO
--00
--00
--00
XXOo
--00 ---- -X-- /1
--00 ---- ---x /J
--00 ---x ---- /K
XXOo XXXX XXXX
---XXXX
-X-X---
---- /M*/N
XXXX
---- P*/Q
---- /P*Q
END*FPLT
LEGEND:
X: FUSE NOT BLOWN (L,N,O)
o : PHANTOM FUSE (L,N,O)
NUMBER OF FUSES BLOWN = 306
o
FUSE BLOWN (H,P,l)
PHANTOM FUSE (H,P,l)
159
160
Programmable Logic Design Guide
BASIC GATE
BASIC GATE
1 XXXXXXXXXXXXXXXXXHOI
2 XXXXXXXXXXXXXXXXXLII
3 OOXXXXXXXXXXXXXXLXXI
4 01XXXXXXXXXXXXXXLXXI
5 10XXXXXXXXXXXXXXLXXI
6 llXXXXXXXXXXXXXXHXXI
7 XXOOXXXXXXXXXXXLXXXI
8 XXOIXXXXXXXXXXXHXXXI
9 XXI0XXXXXXXXXXXHXXXI
10 XXIIXXXXXXXXXXXHXXXI
11 XXXXXXXXOXOOHXXXXXXI
12 XXXXXXXXOXOIHXXXXXXI
13 XXXXXXXXOX10HXXXXXXI
14 XXXXXXXX1XOOHXXXXXX1
15 XXXXXXXXIX11LXXXXXXI
16 XXXXOOXXXXXXXXHXXXXI
17 XXXXOIXXXXXXXXLXXXXI
18 XXXXI0XXXXXXXXLXXXXI
19 XXXX11XXXXXXXXLXXXXI
20 XXXXXXOOXXXXXLXXXXXI
21 XXXXXXOIXXXXXHXXXXX1
22 XXXXXX10XXXXXHXXXXX1
23 XXXXXX11XXXXXLXXXXXI
1 XXXXXXXXXXXXXXXXXHOI
2 XXXXXXXXXXXXXXXXXLII
3 OOXXXXXXXXXXXXXXLXXI
4 01XXXXXXXXXXXXXXLXXI
5 10XXXXXXXXXXXXXXLXXI
6 llXXXXXXXXXXXXXXHXXI
7 XXOOXXXXXXXXXXXLXXXI
8 XXOIXXXXXXXXXXXHXXXI
9 XXI0XXXXXXXXXXXHXXXI
10 XXIIXXXXXXXXXXXHXXXI
11 XXXXXXXXOXOOHXXXXXXI
12 XXXXXXXXOXOIHXXXXXXI
13 XXXXXXXXOXI0HXXXXXXI
14 XXXXXXXXIXOOHXXXXXXI
15 XXXXXXXXIXIILXXXXXXI
16 XXXXOOXXXXXXXXHXXXXI
17 XXXXOIXXXXXXXXLXXXXI
18 XXXXI0XXXXXXXXLXXXXI
19 XXXXIIXXXXXXXXLXXXXI
20 XXXXXXOOXXXXXLXXXXXI
21 XXXXXXOIXXXXXHXXXXXI
22 XXXXXXI0XXXXXHXXXXXI
23 XXXXXXIIXXXXXLXXXXXI
PASS SIMULATION
230
PASS SIMULATION
230
PRODUCT: 1 OF EQUATION. 4
PRODUCT: 2 OF EQUATION. 4
PRODUCT: 3 OF EQUATION. 4
24
24
UNTESTED(SAO)FAULT
UNTESTED(SAO)FAULT
UNTESTED(SAO) FAULT
NUMBER OF STUCK AT ONE (SAl) FAULTS ARE = 10
NUMBER OF STUCK AT ZERO (SAO) FAULTS ARE = 7
PRODUCT TERM
COVERAGE
= 85%
Applications
161
Inputs (0-31)
1
C
o2
A
19
, "'
18
..
...
-
I
I
""
J
./
A
B
3
F
G
17
-
""
E
4
c;CD
I
.
"
rn
E
~
16
"
eM
5
ti
:I
'C
e
-
"
13
a.
N
6
15
14
"
,7
.~
-
"
8
R
.>:
..."
Q'
o
.>:
.
p
H
J
, "'
13
./
.
12
....
9
IGII
24152121
UJl3Dll
Figure 8.1.2 Logic Diagram PAL12H6
11
L
K
J
162
8.2
Programmable Logic Design Guide
BASIC CLOCKED FLIP FLOPS
This example demonstrates how fusable logic, PAL16R8, can implement the basic flipflops; J-K flip-flop; T flip-flop, D flip-flop, and S-R flip-flop. A PAL16L8 can be substituted
for this application. Then, the clock input (eLK) would be gated with the data inputs to
implement the basic flip-flop.
PALASM VERSION 1.5
PAL16R8
BFLIP
BASIC
NSC
CLK J K T PR CLR D S R GND
/OC /SRC ISRT IDC IDT /TC ITT /JKC IJKT VCC
JKT:=J*/JKT*/CLR
+/K*JKT*/CLR
+PR
JKC:=/J*K*/PR
+/J*/JKT*/PR
+K*JKT*/PR
+CLR
TT:=T*/TT*/CLR
+/T*TT*/CLR
+PR
TC:=/T*/TT*/PR
+T*TT*/PR
+CLR
DT:=D*/CLR
+PR
DC:=/D*/PR
+CLR
SRT:=S*/CLR
+/R*SRT*/CLR
+PR
SRC:=/S*R*/PR
+/S*/SRT*/PR
+CLR
FUNCTION TABLE
CLK IOC PR CLR J K JKT JKC T TT TC D DT DC S R SRT SRC
XHXX XX Z
Z
xZZ xZZ xxZ
Z;HI-Z
CLLH
CLLL
CLLL
CLLL
CLLL
CLLL
CLLL
C L HL
CLLL
CLLL
XX L
LLL
LHL
HHH
HLH
LLH
LHL
XXH
HHL
HL H
H
H
H
L
L
L
H
L
H
L
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
X XX
X XX
X XX
X XX
X XX
X XX
XXX
XXX
XXX
XXX
XXX
XX X
XXX
XXX
XXX
XXX
XXX
X;CLEAR
X·
X;
X;TOGGLE
X;
X·
X·
X;PRESET
X;TOGGLE
X;
CLLH
CLLL
CLLL
CLLL
C L HL
XXX
XXX
XXX
XXX
XXX
X
X
X
X
X
XL H
LLH
HH L
HL H
XH L
XXX XXX
XXX XXX
XXX XXX
XXX XXX
XXX XXX
X;CLEAR
X·
X;TOGGLE
X;TOGGLE
X;PRESET
·
··
·
Applications
CL LH
CL LL
CLL L
CLL L
CL HL
XXX
XXX
XXX
XXX
XXX
X
X
X
X
X
XXX
XXX
XXX
XXX
XXX
XL H
LLH
HHL
LLH
XH L
XXX
XXX
XX X
XX X
XX X
X;CLEAR
X;
x;
X;
X;PRESET
C L L H X X X X X X X X X X X X L H;CLEAR
C L L L X X X X X X X X X X L L L H;
C L L L X X X X X X X X X X H L H L;SET
C L L L X X X X X X X X X X L H L H;RESET
C L L L X X X X X X X X X X L H L H;HOLD
C L H L X X X X X X X X X X X X H L;PRESET
C L L L X X X X X X X X X X L L H L;
C L L L X X X X X X X X X X H L H L;
-----------------------------------------------------DESCRIPTION
BASIC
************** **************
*
**
*
****
****
CLK * 1*
PAL
*20*
****
****
1 6 R8
*
*
****
****
J * 2*
*19*
****
****
*
*
****
****
K * 3*
*18*
****
****
*
*
****
****
T * 4*
*17*
****
****
*
*
****
****
PR * 5*
*16*
****
****
*
*
****
****
CLR * 6*
*15*
****
****
*
*
****
****
0 * 7*
*14*
****
****
*
*
****
****
S * 8*
*13*
****
****
*
*
****
****
R * 9*
*12*
****
****
*
*
****
****
GND *10*
*11*
****
****
*
*
*******************************
VCC
IJKT
IJKC
ITT
ITC
lOT
IDC
ISRT
ISRC
10C
163
164
Programmable Logic Design Guide
BASIC
11 1111 1111 2222 2222 2233
0123 4567 8901 2345 6789 0123 4567 8901
BEG*FPLT PAL16R8
o X-X- ---- ---1 ---x -x-- ---2 ---- ---- ---3 xxxx xxxx XXXX
4 XXXX XXXX XXXX
5 XXX X XXXX XXXX
6 XXXX XXXX XXXX
7 XXXX XXXX XXXX
8
---- -x-- ---- ---- ---- J*/JKT*/CLR
---- -x-- ---- ---- ---- /K*JKT*/CLR
x--- ---- ---- ---- ---- PR
XXXX XXXX XXXX XXXX XXXX
XXXX XXXX XXXX XXX X XXXX
XXXX XXX X XXXX XXXX XXXX
XXXX XXXX XXXX XXXX XXXX
XXXX XXXX XXXX XXXX XXXX
8
9
10
11
12
13
14
15
-X-- X--- ---- -X-- ---- ---- ---- ---- /J*K*/PR
-XX- ---- ---- -X-- ---- ---- ---- ---- /J*/JKT*/PR
---x x--- ---- -x-- ---- ---- ---- ---- K*JKT*/PR
---- ---- ---- ---- X--- ---- ---- ---- CLR
XXXX XXXX XXX X XXXX XXXX XXXX XXXX XXXX
XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
XXXX XXXX XXXX XXX X XXXX XXXX XXXX XXXX
XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
16
17
18
19
20
21
22
23
---- ------- ------- ---XXXX XXXX
XXXX XXXX
XXXX,XXXX
XXXX XXXX
XXXX XXXX
x-x- ---- -X-- ---- ----X-X ---- -X-- ---- ------- X--- ---- ---- ---XXXX XXX X XXXX XXXX XXXX
XXXX XXXX XXX X XXXX XXXX
XXXX XXXX XXXX XXXX XXXX
XXX X XXXX XXXX XXXX XXXX
XXXX XXXX XXXX XXX X XXXX
24
25
26
27
28
29
30
31
---- ------- ------- ---XXXX XXXX
XXXX XXXX
xxx X XXXX
XXXX XXXX
XXXX XXXX
-XX- -X-X--X -x----- ---XXX X XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
---- ---- ---- ---- /T*/TT*/PR
T*TT*/PR
X--- ---- ---- ---- CLR
XXX X XXXX XXXX XXX X
XXXX XXXX Xxxx XXx X
XXXX XXXX XXXX XXXX
XXXX XXXX XXXX XXX X
XXXX XXXX XXXX XXX X
32
33
34
35
36
37
38
39
---- ------- ---XXX X XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
------XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
---X--XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
-X-- X------ ---XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXX X XXXX
40
41
42
43
44
45
46
47
------XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
------XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
-X-- ------- X--XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXX X XXXX
XXXX XXXX
------XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
---- T*/TT*/CLR
---- /T*TT*/CLR
---- PR
XXXX
XXXX
XXX X
XXXX
XXXX
---- ---- ---- ----
---- ---- O*/CLR
---- ---- PR
XXXX XXXX
XXXx XXx X
XXX X XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
-X-- ---- ---- /D*/PR
---- ---- ---- CLR
XXXX XXXX XXXX
XXXX XXX X XXXX
XXXX XXXX XXX X
XXXX XXXX XXXX
XXX X XXXX XXXX
XXX X XXXX XXXX
Applications
48
49
50
51
52
53
54
55
---- ---- ---- ---- -X-- ---- X--- ---- S*/CLR
---- ---- ---- ---- -X-- ---- ---x -X-- /R*SRT*/CLR
---- ---- ---- X--- ---- ---- ---- ---- PR
XXXX XXXX XXXX XXX X XXXX XXX X XXXX XXX X
XXXX XXXX XXX X XXXX XXXX XXXX XXXX XXXX
XXXX XXXX XXXX XXXX XXXX XXXX XXX X XXXX
XXXX XXXX XXXX XXXX XXX X XXXX XXXX XXXX
XXX X XXX X XXXX XXXX XXXX XXXX XXX X XXXX
56
57
58
59
60
61
62
63
---------XXXX
XXXX
XXXX
XXXX
XXXX
---- ------- ------- ---XXX X XXXX
XXXX XXXX
XXX X XXXX
XXXX XXXX
XXXX XXXX
-X-- ----X-- ------- X--XXXX XXXX
XXX X XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
---- -X----- -XX---- ---XXXX XXXX
XXX X XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
X--- /S*R*/PR
---- /S*/SRT*/PR
---- CLR
XXXX
XXXX
XXXX
XXXX
XXXX
END*FPLT
LEGEND: X: FUSE NOT BLOWN (L,N,O)
FUSE BLOWN
(H;P,I)
NUMBER OF FUSES BLOWN = 686
BASIC
1 XXXXXXXXXXIZZZZZZZZI
2 CXXXOIXXXXOXXXXXXLHI
3 CXXXOIXXXXOXXXXXXLHI
4 COOXOOXXXXOXXXXXXLHI
5 COIXOOXXXXOXXXXXXLHI
6 CIIXOOXXXXOXXXXXXHLI
7 CI0XOOXXXXOXXXXXXHLI
8 COOXOOXXXXOXXXXXXHLI
9 COIXOOXXXXOXXXXXXLHI
10 CXXXI0XXXXOXXXXXXHLI
11 CIIXOOXXXXOXXXXXXLHI
12 CI0XOOXXXXOXXXXXXHLI
13 CXXXOIXXXXOXXXXLHXXI
14 CXXXOIXXXXOXXXXLHXXI
15 CXXOOOXXXXOXXXXLHXXI
16 CXXI00XXXXOXXXXHLXXI
17 CXXI00XXXXOXXXXLHXXI
18 CXXXI0XXXXOXXXXHLXXI
19 CXXXOIXXXXOXXLHXXXXI
20 CXXXOIXXXXOXXLHXXXXI
21 CXXXOOOXXXOXXLHXXXXI
22 CXXXOOIXXXOXXHLXXXXI
23 CXXXOOOXXXOXXLHXXXXI
24 CXXXI0XXXXOXXHLXXXXI
25 CXXXOIXXXXOLHXXXXXXI
26 CXXXOIXXXXOLHXXXXXXI
27 CXXXOOXOOXOLHXXXXXXI
28 CXXXOOXI0XOHLXXXXXXI
29 CXXXOOXOIXOLHXXXXXXI
30 CXXXOOXOIXOLHXXXXXXI
31 CXXXI0XXXXOHLXXXXXXI
32 CXXXOOXOOXOHLXXXXXXI
33 CXXXOOXI0XOHLXXXXXXI
PASS SIMULATION
759
34
165
166
Programmable Logic Design Guide
BASIC
1 XXXXXXXXXXIZZZZZZZZI
2 CXXXOIXXXXOXXXXXXLHI
3 CXXXOIXXXXOXXXXXXLHI
4 COOXOOXXXXOXXXXXXLHI
5 cblXOOXXXXOXXXXXXLH1
6 CI1XOOXXXXOXXXXXXHLI
7 CI0XOOXXXXOXXXXXXHLl
8 COOXOOXXXXOXXXXXXHLI
9 COIXOOXXXXOXXXXXXLHI
10 CXXXIOXXXXOXXXXXXHLl
11 C11XOOXXXXOXXXXXXLHI
12 C10XOOXXXXOXXXXXXHLI
13 CXXX01XXXXOXXXXLHXXI
14 CXXX01XXXXOXXXXLHXXI
15 CXXOOOXXXXOXXXXLHXXI
16 CXX100XXXXOXXXXHLXXI
17 CXX100XXXXOXXXXLHXXl
18 CXXXIOXXXXOXXXXHLXXI
19 CXXX01XXXXOXXLHXXXXI
20 CXXX01XXXXOXXLHXXXXI
21 CXXXOOOXXXOXXLHXXXXI
22 CXXX001XXXOXXHLXXXXI
23 CXXXOOOXXXOXXLHXXXXI
24 CXXXIOXXXXOXXHLXXXXI
25 CXXX01XXXXOLHXXXXXXI
26 CXXX01XXXXOLHXXXXXXI
27 CXXXOOXOOXOLHXXXXXXI
28 CXXXOOX10XOHLXXXXXXI
29 CXXXOOX01XOLHXXXXXXI
30 CXXXOOX01XOLHXXXXXXI
31 CXXXIOXXXXOHLXXXXXXI
32 CXXXOOXOOXOHLXXXXXXI
33 CXXXOOX10XOHLXXXXXXI
PASS SIMULATION
PRODUCT: 1 OF
PRODUCT: 4 OF
PRODUCT: 2 OF
PRODUCT: 3 OF
PRODUCT: 2 OF
PRODUCT: 3 OF
759
EQUATION. 2
EQUATION. 2
EQUATION. 3
EQUATION. 4
EQUATION. 6
EQUATION. 8
NUMBER OF STUCK AT ONE (SAl)
34
UNTESTED(SAO) FAULT
UNTESTED(SAO)FAULT
UNTESTED(SAO) FAULT
UNTESTED(SAO) FAULT
UNTESTED(SAO)FAULT
UNTESTED(SAO)FAULT
FAULTS ARE = 23
NUMBER OF STUCK AT ZERO (SAO) FAULTS ARE = 17
PRODUCT TERM
COVERAGE
= 86%
Applications
1
ClK
167
......
~
012]
4
~
6 1
891011
.,1114H
1&111oh
2 .. 2,UIJ
,.L)I./.
,.1.:11131
,
0
,
I
:>-
·•,
5
J~
...
~
3
K ---1.2
·
,
""
""
""
)-~
""
""
)-
20
"
II
II
T
4
~
~
~~
~
~
24
""
)--
11
18
19
c;eo
I
e.
en
E
PR
5
...
""
~
~
~
19
~.
'-;t
17
V'
~
II
{E.
U
Jl
J4
lS
l6
:::I
~
11
lS
'C
e
19
11.
ClR
6
~
'-;t
15
rJ.><>-
so
"41
..
..
~
~
~
~
>-~
~
V'
>-
4l
4S
41
7 ..
D --t..2
....
50
"'"
"5253
./
50
55
8 ..
s --t..2
!C.
56
.""
59
9
"
""
.c
R --1..2
o
1 2 1
4 5 6 1
8 9 101\
It lJ 14 1~
16 1/18 19
2021112J
"
i~
lbJ/
2U 19 ]011
Figure 8.2.1 Logic Diagram PAL16R8
.A. 11
~
OC
168
Programmable Logic Design Guide
MEMORY-MAPPED 1/0 (ADDRESS DECODER)
8.3
Memory-mapped I/O is an interface technique that treats I/O devices' physical
addresses the same as memory address space. That is, no Memory-I/O decoding is
required. Furthermore, most computers have more instructions to manipulate the contents of memory than they have I/O instructions. Therefore, the use of memory mapping can make I/O control much more flexible. PAL devices can be used to make
memory-mapped I/O implementation easy, even if changes in memory addresses are
required.
Functional Description
Figure 8.3.1 shows a circuit that is typical of those found in memory-mapped I/O applications. The inputs to the decode logic are the system memory address lines,. Ao-AF'
The logic shown compares the address on the memory bus with the programmed comparison address. When an address on the bus matches, the corresponding I/O port
enable signal is set. In conjunction with other system control signals, this enable can be
used to transfer data to and from the system data bus.
PORT 1 =lF79
PORT O=lF78
ABF D
ABE
ABO D
ABC
ABB
ABA
AB9
AB8 :::::.
AB7 D
AB6
ABS
AB4 .......
AB3 .......
AB2 D
ABl D
ABO D
ABF
ABE
[> .....
[> ....
ABO
ABC
ABB
ABA
~
~
~
:::.
-
-
-
[>
~
-
~
[>[>
[>
MEMORY MAPPED 10
PORT 0
AB9
ABS
AB7
AB6
ABS
AB4
AB3
AB2
ABl
ABO
D
.......
~
[> ...
..........
....
.......
......
.....
=
~
.....
..........
~
.....
~
MEMORY MAPPED 10
Figure 8.3.1 Memory Mapped I/O Logic Diagram
PORT 1
Applications
169
PAL Device Design
One PALl6L2 can be used to monitor a 16-bit address bus, fully decode addresses,
and furnish enables to two ports, each of which can be anywhere within 64K of
address space. Partial decoding for a larger number of ports can be done using other
members of the PAL device family.
Typical logic equations for the memory-mapped I/O logic are as follows:
Port 0 = /ABO./ABl./AB2·AB3·AB4·ABS·AB6./AB7·
ABS·AB9·ABA·ABB·ABC·/ABD·/ABE·/ABF
Port 1 = ABO./ABl./AB2.AB3.AB4·ABS·AB6·/AB7·
ABS. AB9. ABA. ABB. ABC. /ABD. /ABE. /ABF
The above example shows address decoding for memory locations 1F7SH and
IF79H. The equation terms could be changed to accommodate any 16-bit address.
PALASM VERSION 1.5
PALl6L2
PAT
MEMORY
MAP
ABO AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 GND
AB9 ABA ABB ABe /PORT1 /PORTO ABD ABE ABF vee
PORTO=/ABO*/ABl*/AB2*AB3 *AB4*AB5*AB6*/AB7*AB8*AB9*
ABA*ABA*ABC*/ABD*/ABE*/ABF
PORT1=ABO*/AB1*/AB2*AB3*AB4*AB5*AB6*/AB7*AB8*AB9*
ABA*ABB*ABC*/ABD*/ABE*/ABF
DESCRIPTION
MEMORY
ABO
AB1
AB2
AB3
AB4
************** **************
*
**
*
****
****
*20*
* 1*
PAL
****
****
1 6 L2
*
*
****
****
* 2*
*19*
****
****
*
*
****
****
*18*
* 3*
****
****
*
*
****
****
* 4*
*17*
****
****
*
*
****
****
*16*
* 5*
****
****
VCC
ABF
ABE
ABD
/PORTO
170
Programmable Logic Design Guide
AB5
AB6
AB7
AB8
GND
*
*
****
****
*15*
* 6*
****
****
*
*
****
****
*14*
* 7*
****
****
*
*
****
****
*13*
* 8*
****
****
*
*
****
****
*12*
* 9*
****
****
*
*
****
****
*11*
*10*
****
****
*
*
*******************************
/PORTl
ABC
ABB
ABA
AB9
MEMORY
11 1111 1111 2222 2222 2233
0123 4567 8901 2345 6789 0123 4567 8901
BEG*FPLT PAL16L2
-x-x
24
25
26
27
28
29
30
31
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
-X-X
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
32
33
34
35
36
37
38
39
-XX- -X-X
xxxx XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
8
x-x-
X--X X--X
XXX X XXXX
XXXX XXXX
XXX X XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
X--- -XX- X-X- /ABO*/AB1*/AB2*AB3*AB4*AB5*AB6*
XXXX XXX X XXX X XXX X
XXXX XXX X XXXX XXXX
XXXX XXXX XXXX XXXX
XXXX XXXX XXXX XXXX
XXXX XXXX XXXX xxx X
XXX X XXXX XXX X XXXX
XXXX XXXX XXXX XXXX
X--X
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
X-X- X-XXXXX XXXX
XXX X XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
X--X
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
-XX- X-X- ABO*/AB1*/AB2*AB3*AB4*AB5*AB6*/
XXX X XXX X
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXX X
XXXX XXXX
XXXX XXXX
END*FPLT
LEGEND: X: FUSE NOT BLOWN (L,N,O)
o : PHANTOM FUSE (L,N,O)
NUMBER OF FUSES BLOWN
= 32
0
FUSE BLOWN (H,P,l)
PHANTOM FUSE (H,P,l)
Applications
ABo
0' I J
1
.50 i J
111011
120un
1'OliU
JDJI2l2l
JUS,liZJ
171
ZUIlO]1
~
19
2
-
~
3
18
~
"§.
4
17
""
""
""
"
"
II
5
-
ABF
ABE
ABO
16
./
12
..""
""
"
15
./
"
14
6
~
ABa
-J
17
~
16
.
""
"
"""
J......
...
""
""
""
I
2
D1
3
...
.
,,
""
""
""
~
----I
"
"
"""
"
11
"
4
A
...
I
B
C
~
~
It
II
5
...
------I
It
1I
IC
LT
NC
NC
6
7
8
9
-j~
.
.
....
D
15
E
...
...
......""
J
14
~
13
~
"
.....
"
..""
II
F
...
»o----E
""so
"
"""
"
...
------I
0111
4561
891011
121]1415
Figure 8.4.2
15111819
10!1U2J
24252621
2829l0Jl
Logic Diagram PAL 16L8
11
G
NC
178
8.5
Programmable Logic Design Guide
BETWEEN LIMITS COMPARATOR/LOGIC
PAL16Cl
Vee
GT,
LTo
GT o
BTWL
NC
NC
NC
EQ3L
GND
LT3
LOGIC SYMBOL
Figure 8.5.1 PAL Device 16Cl Limit Checker
PALASM VERSION 1.5
PAU6C1
PAT 0021
BETWEEN LIMITS COMPARITOP LOGIC
NSC
/EQ1U /LT1 /EQ1L /GT2 /EQ2U /LT2 /EQ2L /GT3 /EQ3U GND
/LT3 /EQ3L NC NC Ne /BTWL /GTO /LTO /GT1 vee
/BTWL = GT3 + GT2*EQ3U + GT1*EQ3U*EQ2U + GTO*EQ3U*EQ2U*EQ1U
LT3 + LT2*EQ3L + LT1*EQ3L*EQ2L + LTO*EQ3L*EQ2L*EQ1L
DESCRIPTION
BETWEEN LIMITS COMPARITOP LOGIC
/EQ1U
/LTl
/EQ1L
************** **************
*
**
*
****
****
* 1*
PAL
*20*
****
****
*
16e 1
*
****
****
* 2*
*19*
****
****
*
*
****
****
* 3*
*lB*
****
****
*
*
vee
/GTl
/LTO
+
Applications
/GT2
/EQ2U
/LT2
/EQ2L
/GT3
/EQ3U
GND
****
****
*17*
* 4*
****
****
*
*
****
****
*16*
* 5*
****
****
*
*
****
****
*15*
* 6*
****
****
*
*
****
****
*14*
* 7*
****
****
*
*
****
****
*13*
* B*
****
****
*
*
****
****
*12*
* 9*
****
****
*
*
****
****
*10*
*~1*
****
****
*
*
*******************************
/GTO
/BTWL
NC
NC
NC
/EQ3L
/LT3
BETWEEN LIMITS COMPARITOP LOGIC
11 1111 1111 2222 2222 2233
0123 4567 8901 2345 6789 0123 4567 8901
BEG*FPLT PAL16C1
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
------------X
-------
---------X
----------
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
-x-- ------- -x-xxxx xxxx
xxxx xxxx
----X--------------
8
---- ---- ---- -X-- ---- GT3
---- ---- ---- ---- -X-- GT2*EQ3U
-x-- ---- ---- ---- -x-- GT1*EQ3U*EQ2U
-X-X ---- ---- ---- -x-- GTO*EQ3U*EQ2U*EQ1U
---- ---- ---- ---- ---x LT3
---- -x-- ---- ---x ---- LT2*EQ3L
---- ---- -x-- ---x ---- LT1*EQ3L*EQ2L
---- ---- -x-- ---x ---- LTO*EQ3L*EQ2L*EQ1L
------x
xxxx xxxx xxxx xxx x xxxx xxxx
xxxx xxxx xxxx xxx x xxxx xxxx
XXXX XXXX
XXX X XXXX
XXXX XXXX
XXX X XXXX
XXXX XXXX
XXXX XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXX X XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXX X
END*FPLT
LEGEND: X: FUSE NOT BLOWN (L,N,O)
o : PHANTOM FUSE (L,N,O)
NUMBER OF FUSES BLOWN; 236
FUSE BLOWN
(H,P,l)
o PHANTOM FUSE (H,P,l)
179
180
Programmable Logic Design Guide
0123
1
2
• 5' 1
• 91011
12131415
16111119
20212223
24252621
28UJ031
19
L2
3
'"
4
~
5
~
""
"""
""
l.?
18
17
16
"
BTWL
~15 NC
,."
""
3l
37
"
31
6
~
I.?
./
"'
~
~
~
~
~
~
.
"
""
~
SL ~
17
"""
""
""
"
7
Rv-
18
U]~
..""
----u-
~
v-
"'
"
----t~
U
r-;:L
""
""
""
"
~
6
8
"'
./
£.
30
5
"'
./
.
..."
."""
.
."
."
""
"
.c:....
"'
./
~
"'
./
"
~
Figure 8.9.1 Logic Diagram PAL16R6
12
.A. 11
~
Q1
RILO
194
Programmable Logic Design Guide
B.10
PORTION OF RANDOM CONTROL LOGIC FOR BOB6 CPU BOARD
r=D-----t=D------------
PD~------o-----SS
Control Logic for 8086 CPU Board
PALASM VERSION 1.5
PALl2H6
PAT03
8086
CPU
PO EN EO EA Sl SA E1 DO DE GND
SO NC3 NO C3 HA SS LA MW PW VCC
MW=/SO+PW*DE
LA=/SA*/DO
SS=Sl*PD*/SA
HA=Sl*PD*/SA*EA*E1
C3=PD*EO*EA
NO=PD*/EN
DESCRIPTION
8086
PO
EN
************** **************
*
**
*
****
****
* 1*
PAL
*20*
****
****
*
1 2 H6
*
****
****
* 2*
*19*
****
****
VCC
PW
Applications
EO
EA
Sl
SA
E1
DO
DE
GND
*
*
****
****
*18*
* 3*
****
****
*
*
****
****
*17*
* 4*
****
****
*
*
****
****
*16*
* 5*
****
****
*
*
****
****
*15*
* 6*
****
****
*
*
****
****
*14*
* 7*
****
****
*
*
****
****
*13*
* 8*
****
****
*
*
****
****
*12*
* 9*
****
****
*
*
****
****
*11*
*10*
****
****
*
*
*******************************
MW
LA
SS
HA
C3
NO
NC3
SO
8086
11 1111 1111 2222 2222 2233
0123 4567 8901 2345 6789 0123 4567 8901
8EG*FPLT PAL12H6
8
9
10
11
------XXXX
XXXX
-----xXXXX
XXXX
--00
--00
XXOO
XXOO
8
--00
--00
XXOO
XXOO
--00
--00
XXOO
XXOO
--00
--00
XXOO
XXOO
------XXXX
XXXX
---x ISO
X--- PW*DE
XXXX
XXXX
16 ---- ---- --00 --00 -XOO --00 -X-- ---- ISA*/DO
17 XXXX XXXX XXOO XXOO XXOO XXOO XXXX XXXX
24 --X- ---- --00 X-OO -XOO --00 ---- ---- Sl*PD*/SA
25 XXXX XXXX XXOo XXOo XXOo XXOO XXXX XXXX
32 --X- ---- X-OO X-OO -XOO X-OO ---- ---- Sl*PD*/SA*EA*E1
33 XXXX XXXX XXoo XXOo XXOo XXOO XXXX XXXX
40 --X- X--- X-OO --00 --00 --00 ---- ---- PD*EO*EA
41 XXXX XXXX XXOo XXOo XXOo XXOO XXXX XXXX
195
196
Programmable Logic Design Guide
48 -xx- ---- --00
49 XXXX XXXX XXOO
50 XXXX XXXX XXOO
51 XXX X XXXX XXOO
--00
XXOO
XXOO
XXOO
--00
XXOO
XXOO
XXOO
--00
XXOO
XXOO
XXOO
---XXXX
XXXX
XXXX
---- PO*/EN
XXXX
XXXX
XXXX
END*FPLT
LEGEND:
X: FUSE NOT 8LOWN (L,N,O)
PHANTOM FUSE (L,N,O)
o:
0
FUSE BLOWN (H,P,1)
PHANTOM FUSE (H,P,1)
NUMBER OF FUSES BLOWN = 206
PAL DEVICES FOR EASY INTERFACE BETWEEN DP8408/09* DRAM
CONTROLLER AND POPULAR MICROPROCESSORS
High storage density and low cost have made dynamic RAMs the designers choice in
most memory applications. However, the major drawbacks of dynamic RAMs are the
complex timing involved and periodic refresh needed to keep all memory cells
charged. With the introduction of the DPS40S/09 Dynamic RAM controller/driver, the
above complexities are simplified.
Use of PAL devices adds flexibility in the design as PAL device logic equations can
be modified by the user for his/her application and programmed into any of the PAL
devices. In addition, PAL devices lower the parts count in memory system design. For
most memory operations, the PAL devices (DPS432/322/332) can be directly connected
between the control signals from the CPU chip set and the DPS40S/09 dynamic RAM
controller. The PAL device allows hidden refresh using the DPS40S/09. In a standard
memory cycle, the access can be slowed by one clock cycle to accommodate slower
memories. This extra wait state will not appear during the hidden refresh cycle, so
faster devices on the CPU bus will not be affected. Similarly, PAL devices allow for the
insertion of wait states for processors operating at high CPU clock frequencies to use
slower dynamic RAMs.
The following three applications describe the use of National's PAL16R6,
PAL16R4 and PAL16RS for the ease and flexibility of interfacing DP840S/09 with
popular microprocessors such as the 32032, 6sooo, SOS6, and SOSS. Today the PAL
device family offers the designer flexibility to design desired speed/power PAL device
in his memory systems, and achieve the memory operations at very high frequencies
with or without wait state conditions .
• DP8408/09 is part of the interface product line at National Semiconductor Corp.
Applications
8.11
197
DP84312 DYNAMIC RAM CONTROLLER INTERFACE CIRCUIT FOR THE
NS32032 CPU
General Description
The DP84312 dynamic RAM Controller interface is a PAL device for interface between
the DP8409 dynamic RAM Controller and the NS32032 microprocessor.
Using timing signals from the NS32032:timing and control unit and the NS32032
the DP84312 supplies all control signals needed to perform memory read, write, byte
write, and refresh.
Features
• Low parts count memory system.
• Allows the DP8409 to perform hidden refresh.
• Allows for the insertion of wait states for slow dynamic RAMs.
• Supplies independent CASs for byte writing.
• Possibility of operation at 8MHz with no wait states.
• 20-pin 0.3 inch wide package.
• Standard National Semiconductor PAL device part (PAL16R6).
• PAL device logic equations can be modified by the user for his/her specific application and programmed into any of the National Semiconductor PAL device family,
including the new high speed PAL devices.
Dual-In-Line Package
ClK
1
RASIN
Vee
2
19
RFSH
RFRQ
3
18
CASH
HBE
4
17
CASl
AO
5
16
NC
WAITIN
6
15
NC
CTTl
7
14
NC
CS
8
13
NC
9
12
WAIT
10
11
GND
WAIT1
GND
TOP VIEW
Figure 8.11.1 Connection Diagram
198
Programmable Logic Design Guide
Symbol
Parameter
Min
Typ
Vee
Supply Voltage
4.75
5.00
5.25
V
10H
High Level Output Current
-3.2
mA
10L
Low Level Output Current
24
(Note 2)
mA
TAA
Operating Free Air Temperature
75
°C
Table 8.11.1
Symbol
Units
Max
0
Recommended Operating Conditions
Parameter
Min
Conditions
Max
Typ
2
VIH
High Level Input Voltage
Vil
Low Level Input Voltage
Vie
Input Clamp Voltage
Vee = Min, 11= -18 mA
V OH
High Level Output Voltage
Vee = Min, VIH =2V, Vll =0.8V, 10H=Max
VOL
Low Level Output Voltage
10ZH
Units
V
0.8
V
-1.5
V
Vee = Min, VIH =2V, Vll=0.8V, 10L=Max
0.5
V
Off·State Output Current
High Level Voltage Applied
Vee = Max, VIH =2V, Vo=2.4V, VIL =0.8V
100
p.A
10Zl
Off·State Output Current
Low Level Voltage Applied
Vee= Max, VIH =2V, Vo=0.4V, Vll=0.8V
-100
p.A
II
Input Current at
Maximum Input Voltage
Vee = Max, VI = 5.5V
1.0
mA
p.A
V
2.4
IIH
High Level Input Current
Vee= Max, VI=2.4V
25
III
Low Level Input Current
Vee = Max, VI = 0.4V
-250
p.A
los
Short Circuit Output Current
Vee=Max
-130
mA
lee
Supply Current
Vee=Max
180
(Note 1)
mA
Table 8.11.2
Symbol
-30
150
Electrical Characteristics
Conditions
Rl = 6671l
Parameter
Min
Commercial
TA=OOCto + 75°C
Vee = 5.0V :t 5%
Typ
Max
Units
two
WAITIN to WAIT Delay
C l =45 pF
25
40
ns
t po
Clock to Output
CL=45 pF
15
25
ns
tpzx
Pin 11 to Output Enable
C L =45 pF
15
25
ns
t pxz
Pin 11 to Output Disable
C l =5 pF
15
25
ns
tw
Width of Clock
I
I
tsu
Set·UpTime
th
Hold Time
High
Low
25
25
ns
ns
40
ns
0
-15
Nota1: lee = max at minimum temparatura.
Nota 2: One output at a tlma; otherwise 16 mAo
Table 8.11.3
Switching Characteristics
ns
~
ADO-AD15
ADO-AD 15
l
~
DDIN
ADS
~
~74S04
AM1-AM20
DM74S139
DM74LSa-
r-+
G
PEFiiP
A, B, G
ROM
~
1
~
NS32032
--
CS
WiN
WR ~
Bl
r-----
BO
H
CO-6,7
~
RO-6,7
DD-D15
@
00-6,7
..!.+
RASO
~
WR
AO-6,7
@
'RASii
DP8409
MM5295-12
MM4164-12
@
RASI ~ RASI
ADS
@
A16-A22
~7
~
AO-A15
DP84300
RAS2 ~ RAS2
Ml
RFCK
@
RASa
HBE
-
r--+
PHI2
RDY
A16-A23
PHil
r rr
PHil
PHI2
ADS
CTTL
AD
-
CS RFSH
AD
HBE
FCLK
FCLK
NTSO
NTSO
* Nole:
@
RFRO
CTTL
NCWAIT
.
f
I
AO-A23
CASH
@
Jy\
N832201
NPER
CASL
RASIN
f
A16-A23
RDY
RAs3
RFIIO
RGCK
M2
~
For more than 16 RAM chips,
WAIT
NC WAIT IN-+ WAITIN
add huffl!r!;L
*
CASL
iT'"
CASH
~
=:
"CI
DP84312
I
@These outputs may need resistors.
PERIP
~
Figure 8.11.2 System Block Diagram
\0
\0
200
Programmable Logic Design Guide
Mnemonic Description
Input Signals
CLK
Clock input. This clock comes from the FCLK output of the NS32201
timing and control unit, and supplies timing for the internal logic.
RAS input. This input is connected to the NTSO pin of the NS32201
This signal marks the start of a memory cycle.
RFRQ
Refresh request. The DP8409 requests a forced refresh with this input.
HBE,AO
Address select inputs. These inputs select the type of write during a
write cycle, and select their respective CAS outputs. These inputs must
remain stable throughout the memory cycle.
WAITIN
This wait input allows other devices to use the NCWAIT line of the
NS16201 clock chip.
CTTL
System clock input. This clock is used to synchronize the memory system to the microprocessor clock.
Chip select. This input is used to determine if a memory cycle or a hidden refresh cycle is to be performed.
WAIT 1
Insert one wait state. This input allows the use of slow memories with
a microprocessor using a fast clock by inserting a wait state in selected
memory cycles.
Output Signals
RFSH
Refresh. This output switches the DP8409 to a refresh mode.
CASH, CASL
CAS outputs. CASH is for controlling the high bank of dynamic RAMs,
while CASL controls the CAS line of the lower bank of RAMs. If only
eight RAMs are used in each bank, the CAS outputs will directly drive
the memories. For large arrays, these outputs should be buffered with
a high current driver, such as the DP84244 MOS driver.
WAIT
This output controls the insertion of wait states. This output is ORed
with WAITIN to allow other devices to insert wait states.
Functional Description
The DP84312 detects the start of a memory cycle when NTSO from the NS32032 timing and control unit (TCU) goes low. The NTSO signal is also used to supply RASIN to
the DP8409 dynamic RAM controller. After the DP8409 has latched the row address
and supplied the column address to the DRAMs, the DP84312 latches the column
Applications
201
address. The DP84312 supplies two CAS outputs: one for the high byte of memory, and
the other for the low byte. The ability to control the upper and lower bytes of memory
separately is important during a memory write cycle where one byte of memory is to
be written (byte write).
By connecting WAITl of the DP84312 to ground, all selected memory cycles will
have one wait state inserted. This allows an NS32032 operating at high CPU clock frequency to use slower dynamic RAMs.
Memory refresh can be achieved in one of two ways: hidden or forced. Hidden
refresh is accomplished whenever a refresh is requested (internal to the DP8409) and
an unselected memory cycle occurs. With a hidden refresh, the DP84312 does nothing
while the DP8409 performs the refresh. If no refresh occurs before the trailing edge of
refresh clock, the DP8409 will request a forced refresh. The DP84312 detects this
request, and allows the current memory cycle to finish. It then outputs wait states to
the CPU, which will hold the CPU if it requests a memory cycle. During this time the
DP84312 has switched the dynamic RAM controller to the auto refresh mode, allowing
it to perform a refresh. At the end of the refresh cycle, the DP8409 is switched back to
the auto access mode, and the wait is removed after a sufficient RAS precharge time.
The total forced refresh takes four CPU clock cycles, of which some, none or all may
be actual wait states. If the CPU does not request a memory cycle during this refresh
cycle, the refresh will not impact the CPU's performance.
The DP84312 can possibly be operated at 8 MHz with no wait states (WAITI = "1")
given the following conditions:
T2 + T3 = 250 ns
NTSO generation = 15 ns max.
RASIN to CAS delay DP8409-2 = 130 ns max.
External CASH,L generation using 74S02 and 74S240
7.5 ns (74S02) + 10 ns (74S240) - 7.5 ns (less load on 8409 CAS line) = 10 ns max.
Transceiver delay = 12 ns max.
NS 16032 data setup = 20 ns max .
.'. Minimum tCAC = 63 ns
= 250 - 15 - 130 - 10 - 12 - 20
Minimum tRAS = 250 ns
Minimum tRP = 250 ns
Minimum tRAH = 20 ns
The DP84312 is a standard National PAL device part (PAL 16R6). The user can
modify the PAL device equations to support his/her particular application. The
DP84312 logic equations, function table (functional test), and logic diagram can be seen
at the end of this section.
202
Programmable Logic Design Guide
I-tl OR t4
-I--- t1 - 1 - t2
·1
t 3 - l - t 4 - I - tl OR 11-1
FCLK
CTTL
NTSO
iL __ •
RAS
IL.
CASH,L
DATA
FROM RAM _ _ _ _ _ _ _ _ _ _ _ _ _ _~( READ DATA )>-_______
(READ)
.
.
DATA
FROM
CPU-------C(ADDRESS}-{
(WRITE)
. .
_ _DATA
_ _TO_BE_WRITTEN
_ _ _ _ _.)
~.
Figure 8.11.3 Timing Diagram; Read, Write or Hidden Refresh Memory Cycle for
the NS32032-DP8409 Interface
CPU STATE l-t4 OR t , - I - t 1 - I - t 2 - I - t w - l - t 3 - l - t 4 - 1 t1 OR tl
FCLK
NTSO
NCWAIT
RAS
CASH,L
DATA
FROMRAM--------------------------------c(~~V.~~L~ID~)-----DATA
FROMCPU-----~(ADDRESS)(~_~D~A~rA~TO~B~E~W~R~IT~TE~N~TO~M~E~M~O~R~Y~_)~-Figure 8.11.4 Timing Diagram; Read, or Write Memory Cycle With One Wait
Applications
tl' t1
CPU STATE
tl' t1
tl' T1
203
TI• t1
tl' t1
1- tl OR t4 -I-tl OR t1-I-OR tH -I-OR tH -1- OR tH -1- OR tH -lOR t2
CTTL
I
NTSO
I
I
L~
--.I
----,
RFRQ
I
~'~
__ •
____________________- J
NCWAIT
RFSH
RAS
,iL__
I
---..I
Figure S.11.5 Timing Diagram; Forced Refresh Cycle
PAL16R6
DP84312
Interface Circuit for the NS32032/DP8409
Memory System
CK NTSO IRFRQ IHBE AO IWAITIN CTTL ICS ISLOW
GND IOE IWAIT ID IC IB IA ICASL ICASH IRFSH VCC
CASH:
= A*!B*C*D* HBE*CS +
IA*!B*D*HBE*CS
CASL: = A*!B*/OD*/AO *CS +
IA*!B*D*/AO*CS
A
: = IA*!B*/C*/D*/NTSO*CS*SLOW
B*/C*/D +
A*/C*/D +
A*B
B
+
: = IA*!B*/C*/D*NTSO*RFRQ*CTTL
IA*B +
A*B*/C +
B*C*D
+
204
Programmable Logic Design Guide
C
: = /A*!B*/C*/D*NTSO*RFRQ*CTIL
/A*!B*D +
A*B*D +
B*C*/D +
/A*!B*C*/D*/NTSO
D
: = /A*!B*/C*/D*/NTSO*CS*/SLOW
/A*!B*/C*/D*/NTSO*/CS +
A*/C +
!B*/C*D +
/A*B*C
+
+
IF (VCC) WAIT = !B*/C*/D*/NTSO*CS*SLOW
/A*B*D +
B*/C*/D +
A*B +
A*C*/D +
/CS*WAITIN
IF (VCC) RFSH = /A*B
B*/C*/D +
A*B*/C +
A*B*C
+
+
Applications
205
CK NTSO RFRQ HBE AD WAITIN CTTL CS SLOW OE CASH CASL A B C 0 WAIT RFSH
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
H
H
L
L
X
H
L
X
X
X
X
H
L
X
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
L
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
H
L
H
L
H
L
H
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
H
H
H
H
H
H
L
L
L
L
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
H
X
X
X
X
X
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
L
L
X
L
L
H
H
L
L
L
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Z
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Z
Table 8.11.4 Function Table
X
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
L
Z
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
Z
X X
L L
L H
H
H
L
L
L
L
H
H
L
L
H
H
L
H
H
L
L
L
L
H
H
H
L
L
H
H
H
L
Z
H
L
L
L
H
H
H
L
L
H
H
L
L
L
H
H
L
L
H
H
L
L
L
H
H
L
L
L
Z
X
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
L
L
Z
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
Z
206
Programmable Logic Design Guide
CK
Inputs (0-31)
~
D 123
.'17
11'011 1213,.15 18171'"
20212223 2U52127 21293031
0
1
2
3
1
"
•
5
•
V
7
NTSO .....
2
RFSH
~t----'
••
--H
10
"
11
12
--/
,.
13
15
RFRQ
3
...
~
20
...
~
"
19
./
21
22
23
4
"
AD
Lh~
-1.
16
17
18
HBE
19
1
...
25
26
27
28
29
3D
"
31
...
~
5
~
17
I,tA
~
-v'16
32
33
34
35
36
"
37
38
39
WAITIN ...
~
...
..
....
6
41
42
43
"
'5
47
....
CTTL ...
7-~
~
~
48
49
50
51
52
53
CS
...
x
x
x
54
55
~
...
8
56
57
58
59
60
61
62
63
SLOW ...
----t~
9
"
./
0123
"567
8 91011
12131415 16171819 20212223 24252627 28293031
*~
...
Figure 8.11.6 DP84312 Logic Diagram PAL16R6
~
~
~
C
....
14
til. 0
V'
13
WAIT
12
-
DTACK
WAIT
r+
---
REFRESHI
ACCESS
ARBITRATION
LOGIC
Figure 8.12.2 Block Diagram
M2 (RFSH)
Applications
Parameter
Min
Typ
Max
Vee
Supply Voltage
4.75
5.00
5.25
V
10H
High Level Output Current
-3.2
mA
10l
Low Level Output Current
24
(Note 2)
mA
TA
Operating Free Air Temperature
75
°C
Symbol
Table 8.12.1
Symbol
0
209
Units
Recommended Operating Conditions
Parameter
Min
Conditions
Units
Max
Typ
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
2
V
VIC
Input Clamp Voltage
Vee = Min, 11= -1BmA
VOH
High Level Output Voltage
Vee = Min, V IH =2V, VIL=O.BV, 10H= Max
VOL
Low Level Output Voltage
Vee = Min, V IH = 2V, V IL = O.BV, 10L = Max
0.5
V
10ZH
Off-State Output Current
High Level Voltage Applied
Vee= Max, VIH=2V, Vo=2.4V, VIL=O.BV
100
p.A
10ZL
Off·State Output Current
Low Level Voltage Applied
Vee;' Max, V IH =2V, Vo =0.4V, VIL=O.BV
-100
p.A
II
Input Current at
Maximum Input Voltage
Vee = Max, VI = 5.5V
1.0
rnA
p.A
O.B
V
-1.5
V
2.4
V
IIH
High Level Input Current
Vee = Max, VI = 2.4V
25
IlL
Low Level Input Current
Vee = Max, VI = 0.4V
-250
p.A
los
Short Circuit Output Current
Vee=Max
-130
rnA
Icc
Supply Current
Vec=Max
180
(Note 1)
rnA
Table 8.12.2
Symbol
-30
150
Electrical Characteristics
Commercial
TA = O·C to + 75·C
Vee = 5.0V ± 5%
Test Conditions
1\=6670
Parameter
Units
Typ
Max
25
40
ns
Clock to Output
15
25
ns
tpzx
Pin 11 to Output Enable
15
25
ns
tpxz
Pin 11 to Output Disable
Cl =5 pF
15
25
ns
tpzx
Input to Output Enable
Cl =45 pF
25
40
ns
tpxz
Input to Output Disable
Cl =5 pF
25
40
ns
tw
Width of Clock
Min
tpo
Input to Output
tpo
Cl =45 pF
I
I
High
25
ns
Low
25
ns
tsu
Set-Up Time
40
th
Hold Time
0
ns
-15
Note1: ICC = max at minimum temperature.
Note 2: One output at a time; otherwise 16 rnA.
Table 8.12.'3
Switching Characteristics
ns
N
DP84322 and DP8409 for 68000 CPU
ADDREii>S_ BUS
""II
,..
I
ADDRESS
DECODER
Al-A23
AS
,.
RO-S. 7. 8
--...
...,.
CO-S. 7. 8
lit.
OO-S. 7. 8
RASO
BO
WE
Bl
,.....
*A
*A
.
AO-S. 7. 8 DIN
CASU
CASl
* .A
WE
""
-
ADS
--*
RAS!
CS
....
....
RAS
~
.
AO-6. 7. 8 DIN
....
"III
-.
.
-- *
RGCK
•
*
RAS2
-+
WIN
R/W
AO-6. 7. 8 DIN
i+
l........+
UDS
lOS
CS
RASIN
AS
RFSH
....
M2 (RFSH)
0 - Ml
UDS
lOS DP84322
1 - MO
----+
RFRO
-:r-
WAIT
~
,.""
(/l
c§.
....
CASl
RASIN
R/W
CAS
...
~
....
RAS
WE
00-015
......
...,.
DOUT
~...
CASU
-
DTACK
WE
RFCK
10 MHz MAX
ClK
io
CASU
CASl
68000
;'
RAS
DP8409
DM74lS393
I
--...
...,.
DOUT
Vee
L..
o'""'
OE
i5TAcK ~
-*
RAS3
*
"
-+
DOUT
AO-6. 7. 8 DIN
CASU
CASU
CAS ~
WE
I
CASl
....
....
RAS
CASl
RFRO
DOUT
--...
...,.
DRAMs
DP84244
BUFFER NECESSARY IF MORE THAN ONE BANK
DATA BUS
~
--...
-,.
·These outputs may need resistors.
Figure 8.12.3 System Block Diagram
""I
,.
Applications
211
Mnemonic Description
Input Signals
CLOCK
The clock signal determines the timing of the outputs and should be
connected directly to the 68000 clock input.
Address Strobe from the 68000 CPU. This input is used to generate
RASIN to the DP8409.
Upper and lower data strobe from the 68000 CPU. These inputs,
together with AS, R/W, provide DTACK to the 68000.
R/W
Read/write from the 68000 CPU, when WAIT = O. Selects processor
speed when WAIT = 1 (" 1" = 4, to 6 MHz, "0" = 8 MHz).
Column Address Strobe from the DP8409. This input, together with
LDS and UDS, provides two separate CAS outputs for accessing upper
and lower memory data bytes.
Chip Select. This input enables DTACK output. CS
is enabled; CS = 1, DTACK output is TRI-STATE®.
=
0, DTACK output
RFRQ
Refresh Request. This input requests the DP84322 for a forced refresh.
WAIT
This input allows the necessary wait state to be inserted for memory
access cycles.
Output Signals
RASIN
CAsU,
This output provides a memory cycle start signal to the DP8409 and
provides RAS timing during hidden refresh.
CASL
These signals are the separate CAS outputs needed for byte writing.
DTACK
This output is used to insert wait states into the 68000 memory cycles
when selected and during a forced refresh cycle where the CPU
attempts to access the memory. This output is enabled when CS input
is low and TRI-STATE when CS is high.
RFSH
This output controls the mode of the DP8409. It always goes low for 4
CPU clock periods when AS is inactive and a forced refresh is
requested through RFRQ input. This allows the DP8409 to perform an
automatic forced refresh.
Functional Description
As a 68000 bus cycle begins, a valid address is output on the address bus AI-A23. This
address is decoded to provide Chip Select (CS) to the DP8409. After the address
becomes valid, AS goes low and it is used to set RASIN low from the DP84322 interface
212
Programmable Logic Design Guide
circuit. Note that CS must go low for a minimum of 10 ns before the assertion of RASIN
for a proper memory access. As an example, with an 8 MHz 68000, the address is valid
for at least 30 ns before AS goes active. AS then has to ripple through the DP84322 to
produce RASIN. This means the address is valid for a minimum of 40 ns before RASIN
goes low, and the decoding of CS should take less than 30 ns. At this speed the
DM74LS 138 or DM74LS 139 decoders can be selected to guarantee the 10 ns minimum
required by CS set-up time going low before the access RASIN goes 10w(tcsRL of the
DP8409). This is important because a false hidden refresh may take place when the
minimum tCSRL is not met.
Typically RASIN occurs at the end of S2. Subsequently, selected RAS output, row
to column select and then CAS will automatically follow RASIN as determined by mode
5 of the DP8409. Mode 5 guarantees a 30 ns minimum for row address hold time (tRAH)
and a minimum of 8 ns column address set-up time (tASe). If the system requires
instructions that use byte writing, then CASU and CASL are needed for accessing upper
and lower memory data bytes, and they are provided by the DP84322. In the DP84322,
LDS and UDS are gated with CAS from the DP8409 to provide CASL and CASU. Therefore, designers need not be concerned about delaying CAS during write cycles to
assure valid data being written into memory. The 8 MHz 68000 specifies during a write
cycle that data output is valid for a minimum of 30 ns before DS goes active. Thus,
CASL and CASU will not go low for at least 40 ns after the output data becomes stable,
guaranteeing the 68000 valid data is written tQ l11emory.
Furthermore, the gating of UDS, LOS and CAS allows the DP84322 interface controller to support the test and set instruction (TAS). The 68000 utilizes the
read-modify-write cycle to execute this instruction. The TAS instruction provides a
method of communication between processors in a multiple processor system.
Because of the nature of this instruction, in the 68000 this cycle is indivisible and the
Address Strobe AS is asserted through the entire cycle. However, DS is asserted twice
for two accesses: a read then a write. The dynamic RAM controller and the DP84322
respond to this read-modify-write instruction as follows (refer to the TAS instruction
timing diagram for clarification). First, the selected RAS goes low as a result of AS going
low, and this RAS output will remain low throughout the entire cycle. Then the
DP84322's selected CAS output (CASL or CASU) goes low to read the specified data
byte. After this read, DS goes high causing the selected CAS to go high. A few clocks
later RIW goes low and then DS is reasserted. As DS goes low, the selected CAS goes
low strobing the CPU's modified data into memory, after which the cycle is ended
when AS goes high.
The two CAS outputs from the DP84322 however, can only drive one memory
bank. For additional driving capability, a memory driver such as the DP84244 should
be added to drive loads of up to 500 pF.
Since this DP84322 interface circuit is designed to operate with all of the 68000
speed versions, a status input called WAIT is used to distinguish the 8 MHz from the
others. The WAIT input should be set low for a 6 MHz or less allowing full speed of
operation with no wait states. Data Transfer Acknowledge input (DTACK) of the 68000
at these speeds is automatically inserted during S2 for every memory transaction cycle
Applications
213
and is then negated at the end of that cycle when UDS and/or LDS go high. For the 8
MHz 68000 however, a wait state is required for every memory transaction cycle. At
these speeds, the WAIT input is set high, selecting the DP8409's CAS output to generate
DTACK and again DTACK is negated at the end of the cycle when UDS or LDS goes
high. Note that DTACK output is enabled only when the DP8409's CS is low. Therefore
when the 68000 is accessing I/O or ROM (in other words, when the DP8409 is not
selected), the DP84322 's DTACK output goes high impedance logic '1' through the
external pull-up resistor and it is now up to the designer to supply DTACK for a proper
bus cycle.
Table 8.12.4 indicates the maximum memory speed in terms of the DRAM timing
parameters: tCAC (access-time from CAS) and tRP (RAS precharge time) required by different 68000 speed versions.
Microprocessor
Clock
Maximum
Minimum
t CAC
tRP
Minimum
t RAS
8 MHz
6 MHz
4 MHz
125 ns
90 ns
270 ns
140 ns
170 ns
280 ns
220 ns
290 ns
450 ns
Table 8.12.4 Memory Speed
Pin 5 (R/W input to the DP84322) is not used as RIW when the WAIT input is high.
Therefore, when WAIT is high and pin 5 is low, this is configured for the 8 MHz 68000.
The dynamic RAM controller in this configuration operates in mode 5 and mode 1.
When both WAIT and pin 5 are high, this is configured for 4 MHz and 6 MHz
68000, allowing only two microprocessor clocks for memory refresh. Furthermore,
the designer can use the DP8408 because the dynamic RAM controller now operates in
mode 0 and mode 5 or mode 6. In addition, the programmable refresh timer, DP84300,
should be used to determine the refresh rate (RFCK) and to provide the refresh request
(RFRQ) input to the DP84322. The refresh timer can provide over two hundred different divisors. RFRQ is given at the beginning of every RFCK cycle and remains active
until M2 goes low for memory refresh. The DP84322 samples RFRQ when AS is high,
then sets M2 low for two microprocessor clocks, taking the DP8408 or DP8409 to the
external control refresh mode. RASIN for this refresh is also issued by the DP84322. If a
memory access is pending, RASIN for this access will not be given until it is delayed for
approximately one microprocessor clock, allowing RAS precharge time for the
dynamic RAMs.
214
Programmable Logic Design Guide
The following table indicates different memory speeds in terms of the DRAM
parameters required by 4 MHz and 6 MHz 68000:
Microprocessor
Clock
Maximum
tcAC
Minimum
t RAS
Minimum
t RP
Minimum
tRAH
4 MHz
6 MHz
290 ns
110 ns
200 ns
125 ns
225 ns
140 ns
20 ns
20 ns
Table 8.12.5 Memory Speed of 68000
When WAIT = 1, pin 5 = 0 (8 MHz), the PAL device controller supports read and
write cycles with one inserted wait state, forced refresh with five wait states inserted
if CS is valid, and hidden refresh. This PAL device mode does not support the TAS
instruction.
When WAIT = pin 5 = 1 (4-6 MHz), the PAL device controller supports read and
write cycles with no wait states inserted, and forced refresh with two wait states
inserted if CS is valid. This PAL device mode does not support the TAS instruction and
only supports hidden refresh when used in mode 5 with the DP8409 controller.
The DP84322 can possibly be operated at 8 MHz with no wait states (WAIT = "0")
given the following conditions:
FAST PAL DEVICE (PAL 16R4A)
S2 + S3 + S4 + S5 = 250 ns
RASIN delay = 60 ns (AS low max.)
+ 25 ns (Fast PAL delay) = 85 ns max.
RASIN to CAS delay DP8409-2 = 130 ns max.
External CASH,L generation using 74S02
and 74S240
7.5 ns (74S02) + 10 ns (74S240) - 7.5 ns (less load
on 8409 CAS line) = 10 ns max.
Transceiver delay (74LS245) = 12 ns max.
68000 data setup into s6 = 40 ns min.
:. Minimum tCAC = 53 ns
= 250 - 85 - 130 - 10 - 12 + 40
Minimum tRAS = 240 ns
Minimum tRP = 150 ns
Minimum tRAH = 20 ns
Refresh Cycle
Since the access sequence timing is automatically derived from RASIN in mode 5, RIC
and CASIN are not used and now become Refresh Clock (RFCK) and RAS-generator
Applications
215
clock (RGCK) respectively. The Refresh Clock RFCK may be divided down from RGCK,
which is the micropocessor clock, using the DM74LS393 or DM74LS390. RFCK provides the refresh time interval and RGCK the fast clock for all-RAS refresh if forced
refreshing is necessary. The DP8409 offers both hidden refresh in mode 5 and forced
refresh in mode 1 with priority placed on hidden refreshing. Assume 128 rows are
being refreshed, then a 16p.s maximum clock period is needed for RFCK to distribute
refreshing of all the rows over the 2 ms period.
The DP8409 provides hidden refreshing in mode 5 when the refresh clock (RFCK)
is high and the microprocessor is accessing RAM. In other words, when the DP8409's
chip select is inactive because the microprocessor is not accessing elsewhere, all four
.RAS outputs follow RASIN, strobing the contents of the on-chip refresh counter to
every memory bank. RASIN going high terminates the hidden refresh and also increments the refresh counter, preparing it for the next refresh cycle. Once a hidden
refresh has taken place, a forced refresh will not be requested by the DP8409 for the
current RFCK cycle.
However, if the microprocessor continuously accessed the DP8409 and memory
while RFCK was high, a hidden refresh could not have taken place and now the system
must force a refresh. Immediately after RFCK goes low, the Refresh Request signal
(RFRQ) from the DP8409 goes low, indicating a forced refresh is necessary. First, when
RFRQ goes low any time during S2 to S7, the controller interface circuit waits until the
end of the current memory access cycle and then sets M2 (RFSH) low. This refresh takes
four microprocessors clocks to complete. If the current cycle is another memory cycle,
the 68000 will automatically be put in four wait states.
Alternately, when RFRQ goes low while AS is high during SO to Sl, M2 is now set
low at S2. Therefore, it requires an additional microprocessor clock for this refresh.
Once the DP8409 is in mode 1 forced refresh, all the RAS outputs remain high until two
RGCK trailing edges after M2 goes low, when all RAS outputs go low. This allows a minimum of one and a half clock periods of RGCK for RAS precharge time. As specified in
the DP8409 data sheet, the RAS outputs remain low for two clock periods of RGCK.
The refresh counter is incremented as the RAS outputs go high. Once the forced
refresh has ended, M2 is brought high, the DP8409 back to mode 5 auto access. Note
that RASIN for the pending access is not given until it has been delayed for a full microprocessor clock, allowing RAS precharge time for the coming access.
If the 68000 bus is inactive (i.e., the 68000's instruction queue is full, or the 68000
is executing internal operations such as a multiply instruction, or the 68000 is in half
state ... ) and a refresh has been requested, a refresh will also take place because RFRQ
is continuously sampled while AS is high. Therefore, refreshing under these conditions
will be transparent to the microprocessor. Consequently, the system throughput is
increased because the DP84322 allows refreshing while the 68000 bus is inactive.
The 84322 is a standard National P~ device part (PAL16R4). The user can
modify the PAL equations to support his particular application. The 84322 logic
equations, function table, and logic diagram can be seen at the end of this section.
216
Programmable Logic Design Guide
=
=
68000 MEMORY READ CYCLE (WAIT 0, PIN 5 RIW)
CLOCK
~__________~_~_LI_D_A_D_D_R_ES_S__________-J)~-----
SELECTED RAs
OUTPUT
COLUMN ADDRESS
tcAc -l
------------------------~----~(
tOFF:1
MEMORY DATA
Figure 8.12.4 Timing Diagram; 68000 Memory Read Cycle
)L----
Applications
217
MEMORY READ CYCLE AND FORCED REFRESH (WAIT = I, PIN 5 = 0)
DP84322 DETECTS START OF
I -CYCLE, SO INSERTS REFRESH CYCLE -
I-
I
DP84322 CONTINUES
MEMORY ACCESS CYCLE-
CLOCK
ADDRESS
AO·A15
AS
OUTPUTS
FROM
68000
UOS,LOS
RJW
RASIN
4 #P CLOCK PERIODS
RFSH
OUTPUTS
FROM
DP84322
DTACK
CASU,
CASL
RAS()'
RAS3
QQ-aa
CAS
OUTPUTS
FROM
DP8409
WE
RFRQ
____________________________________________________
~
M~~~RY
DRAM
OUTPUT
Figure 8.12.5 Timing Diagram; 68000 Memory Read Cycle and Forced Refresh
218
Programmable Logic Design Guide
TAS INSTRUCTION CYCLE (WAIT
SO
S1.
.S4
S8
S6
=0, PIN 5 =R/W)
S10
S12
S14
S16
S18
SO
CLOCK
S2
A1-A23
OUTPUTS
FROM
68000
S3
S5
S7
S9
=>-<. . . ________
S11
S13
S15
S17
S19
--J}-
A_DD_R_E_S_S_ _ _ _ _ _ _
UDS,
LOS
RiW
RASiN
'iiF5H
OUTPUTS
FROM
DP84322
i5fACK
CASu,
CASL
tOFF
RASORAS3
QO-Q8
OUTPUTS
FROM
DP8409
SELECTED RAS
'OUTPUT
COLUMN ADDRESS
CAs
WE
RFRQ
DRAM
OUTPUT
Figure 8.12.6 Timing Diagram; TAS Instruction Cycle
Applications
MEMORY READ CYCLE (WAIT
=1, PIN 5 =0)
CLOCK
A1-A23
Ul:::E C
===>---<
_______________A_D_D_R_E_SS
______________J)~-----
AS
sg~
~I&.
sg!
D.I&.D.
5
Q
CAS
0
WE
DRAM
OUTPUT-------------------------------------{~~~-J
Figure 8.12.7 Timing Diagram; Memory Read Cycle
219
220
Programmable Logic Design Guide
(WAIT
=1, PIN 5 =0)
DP84322 DETECTS
START OF CYCLE, SO
I-INSERTS
REFRESH CYCLE _
DP84322
I.... ACCESS CYCLE---'
MEMORYCONTINU~
CLOCK
AO-A15
ADDRESS
AS
INPUTS
FROM
68000
ODS,LDS
A/W
RASIN
RFSH
INPUTS
FROM
DP84322
4jtP CLOCK PERIODS
STACK
CASU,
CASL
RASORAS3
QO-Q8
INPUTS
FROM
DP8409
REFRESH ADDRESS
CAS
WE
RFRQ
_ ______________________________________-(MEMO
DRAM
OUTPUT
DATA
Figure 8.12.8 Timing Diagram; Memory Read Cycle and Forced Refresh
DP8408, DP8409 AND 68000 INTERFACE
ADDRESS BUS
"'I
.,.
ADDRESS
DECODER
110.
I
,.
RO·6, 7, 8
~
CO·6, 7, 8
t----.
00·6,7,8
RASO
BO
WE
~ Bl
*..
,.
~
*....
-YVV
RAS
*
CASU
CASl
WE
I 11
Al·A23
AS
~
ADS
CS
RASl
AO·6,7,8 DIN
*....
DP8408/9
....
--,.
Dour
AO·6,7,8 DIN
RAS
CASU
CASl
WE
~vv
RFRO
....
'II
....
'II
,..
--110.
Dour
DP84300 }_M2
"l"t
...
68000
ClK
RAS2
Ric
Riw
DTACK
CASIN
~
*~
*
-+
AO·6,7,8 DIN
~vv
CASU
CASl
WE
4
"1" --t>
UDS
lOS
RASIN
CS
AS
RFSH
RNi
50R6
UDS
lOS DP84322
MOD~{~
-+
RASIN
M2 (RFSH)
Ml
MO
CAS
RFRO DTACK
"1"""" WAIT
00·015
t
-:["" OE
RAS3
CAS
I-
CASU
CASl
*....
&
1""'''''
4
*
,.
110.
Dour
AO-6,7,8 DIN
....
...
RAS
CASU
CASl
WE
I~I DP84244
DATA BUS
'II
RAS
WIN
........
....
Dour
,.
~
=:
'"0
DRAMs
BUFFER NECESSARV IF MORE
THAN ONE BANK
'These outputs may need resistors.
Figure 8,12,9 Modified System Block Diagram
III.
~
...
,..
~.
~
N
N
,..
222
Programmable Logic Design Guide
6S000 MEMORY READ CYCLE (WAIT AND PIN 5
AO·A23
OUTPUTS
FROM
6S000
H
=1)
ADDRESS
>--C
AS
ODSI
LOS
RtW
RASIN
~
RFSH
OUTPUTS
FROM
DPS4322
DTACK
CASU,.
CASL
RASO·
RAS3
QO·QS
OUTPUTS
FROM·
DPS40S/9
COLUMN ADDRESS
CAS
WE
ou~~s{
FROM
DPS4300
RFFIQ
DATA
OUT
Figure 8.12.10 Timing Diagram; 68000 Memory Read Cycle
Applications
68000 MEMORY READ CYCLE AND MEMORY REFRESH (WAIT AND PIN 5
223
=0)
DP84322 DETECTS
START OF CYCLE SO
DP84322 CONTINUES
INSERTS REFRESH CYCLE-MEMORY ACCESS CYCLE-I
I
I
END WAIT STATE
----+---...II~OF~
~----+-~--~----~--~
~+--
~~-------------------lMEMORYDATA
Figure 8.12.11 Timing Diagram; 68000 Memory Read Cycle and Memory Refresh
224
Programmable Logic Design Guide
PAL 16R4
DP84322
Dynamic RAM Controller Interface for the
MC68000-DP8409 Memory System
CK lAS IUDS /IDS R /RFRQ lCAS ICS WAIT GND
IOE ICL ICU IC /B IA /RFSH IDTACK /RASIN VCC
IF (VCe) RASIN
= AS*RFSH*IA +
RFSH*R*A*WAIT
IF (CS) DTACK = !R*CAS*WAIT +
UDS*IA*/B*/wAIT +
LDS*IA*/B*/wAIT +
AS*!R*IA*/B*WAIT +
AS*/RFSH*R*IA*/B*WAIT
RFSH:
= IAS*RFRQ +
+
+
RFSH*/R*/C*WAIT
RFSH*R*IA*WAIT
RFSH*/C*/wAIT
A: =
B:=
C: =
IF (VCC) CU =
IF (VCe) CL =
RFSH
A
B
UDS*CDS
LDS*CAS
Applicadons
CK AS UOS
c
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
H
H
H
H
H
L
L
L
L
L
H
H
H
L
L
L
L
L
L
H
H
H
L
L
L
L
L
H
H
H
H
L
L
L
H
H
L
L
L
H
H
L
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
L
L
L
H
H
LOS
L
L
H
L
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
L
L
L
L
L
H
H
H
H
H
H
H
H
H
225
R RFRQ CAS CS WAIT OE CL CU C
B
A RFSH DTACK RASIN
X
X
X
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
L
L
L
L
H
H
H
H
H
L
L
H
Z
X
X
X
X
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
L
L
L
L
H
H
H
H
H
L
L
H
H
Z
X
X
X
X
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
L
L
L
L
H
H
H
H
H
L
L
H
H
H
Z
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
L
L
L
H
H
L
L
L
L
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
L
L
H
H
H
H
H
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
Table 8.12.6 Function Table
X
X
X
X
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
L
L
L
L
H
H
H
H
H
L
L
H
H
H
H
Z
X
X
X
X
Z
L
L
H
L
L
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
L
L
Z
H
H
H
H
L
H
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
L
L
H
H
H
L
H
L
L
H
H
226
'Programmable Logic Design Guide
CLOCK
Inputs (0-31)
1
0123
.517
1I1Dl1
12131415 111111111 20212223 ZU52127 21213031
0
1
2
3
~
,•
•
7
AS ....
2
•
~
9
10
11
12
13
RASIN
19
J
.....
~
"15
UOS ...
OTACK
18
1
.t-----'
3
16
17
18
19
LOS
4
~~
.....
20
21
22
D'Q
_
Q
.,/
"
24
25
,
26
27
28
29
30
31
x
x
R/Iii ..
5
32
33
34
3S
36
37
38
R
I ..
"
6
'0
41
"'"
.,/
47
....
AS ..
7
.
"
~
~
~
~
x
,0
51
52
53
x
x
x
x ,
x
5'
CS ...
~
~
x
"
...".
"
17
>--JJ
16
15
14
CASU
13
8
51
57
.
x
x
x
x
x
58
"
"
"
&2
WA IT ..
-
---I
9
~I
0123
4567
891011
12131415 16171819 20212223 24252627 28293031
Figure 8.12.12 DP84322 Logic Diagram PAL Device 16R4
CASL
12
.A.. OE
"""'F
11
Applications
8.13
227
DP84332 DYNAMIC RAM CONTROLLER INTERFACE CIRCUIT FOR THE
8086 AND 8088 CPUS
General Description
The DP84332 dynamic RAM controller interface is a PAL device for interface between
the DP840S dynamic RAM controller and the SOS6 and SOS8 microprocessors. No wait
states are required for memory access. Memory refreshing may be hidden (no wait
states) or forced (up to three wait states).
The DP84332 supplies all the control signals needed to perform memory read, write
and refresh. Logic is also included to insert a wait state when using slow memory.
Dual-In-Line Package
CLOCK
20
Vee
AO
19
NC
SHE
18
NC
CS
17
NC
ALE
16
RFSH
RFCK
6
RDY
AWAIT
7
CASH
RFRQ
CASL
NC
RASIN
GND
11
OE
TOP VIEW
TL/F/5000·'
Figure 8.13.1 Connection Diagram
228
Programmable Logic Design Guide
Features
• Low parts count controller for the DP8408/DP8409.
• Works with 8086 systems configured in min or max mode.
• Performs hidden refresh using the DP8408 dynamic RAM controller.
• Compatible with both the 8086 and 8088 microprocessors.
• Capable of working at all CPU clock frequencies up to 8 MHz.
• Standard National Semiconductor PAL device part (PAL16R8).
• PAL device logic equations can be modified by the user for his specific application
and programmed into any of the PAL devices in the National Semiconductor family,
including the new high speed PAL devices.
~
~
r+
AWAIT
--.
COUNTER
1
~
..
CAS
GENERATOR
~
RASIN
GENERATOR
f-+
CASH
CASL
RDY1
I
~
~
RFRQ
~
RFCK
~
MEMORY
REQUEST
ENCODER
REFRESH
REQUEST
ENCODER
r-+
TlIFJ5000·2
Figure 8.13.2 Block Diagram
Applications
Symbol
229
Parameter
Min
Typ
Vee
Supply Voltage
4.75
5.00
5.25
V
10H
High Level Output Current
-3.2
mA
10L
Low Level Output Current
24
(Note 2)
mA
TA
Operating Free Air Temperature
75
°C
Table 8.13.1
Symbol I
Max
0
Units
Recommended Operating Conditions
Parameter
Conditions
Min
Typ
Max
Units
V'H
High Level Input Voltage
V'L
Low Level Input Voltage
V'c
VOH
Input Clamp Voltage
Vee=Min, 1,= -18 mA
High Level Output Voltage
Vee = Min, V'H = 2V, V'L = 0.8V, 10H = Max
VOL
Low Level Output Voltage
Vee=Min, V'H=2V, V'L=0.8V, 10L=Max
0.5
V
10ZH
Off·State Output Current
High Level Voltage Applied
Vee=Max, V'H=2V, Vo=2.4V, V'L=0.8V
100
p.A
10ZL
Off·State Output Current
Low Level Voltage Applied
Vee=Max, V'H=2V, Vo =O.4V, V'L=0.8V
-100
p.A
I,
Input Current at
Maximum Input Voltage
Vee=Max, V,=5.5V
1.0
mA
I'H
High Level Input Current
Vee=Max, V,=2.4V
25
p.A
I,L
Low Level Input Current
Vee=Max, V,=O.4V
los
Short Circuit Output Current
Vee= Max
Icc
Supply Current
Vee= Max
2
Table 8.13.2
Symbol
V
-1.5
V
2.4
V
-30
150
-250
p.A
-130
mA
180
(Note 1)
mA
Electrical Characteristics
Conditions
RL =667!1
Parameter
V
0.8
Min
Commercial
TA =O°C to + 75°C
Vee = 5.0V ± 5%
Typ
Max
Units
tpD
Clock to Output
C L =45 pF
15
25
ns
tpzx
Pin 11 to Output Enable
C L =45 pF
15
25
ns
tpxz
Pin 11 to Output Disable
C L =5 pF
15
25
ns
tw
Width of Clock
I
I
tsu
Set·Up Time
tH
Hold Time
High
Low
ns
ns
25
25
ns
40
0
-15
Note 1: ICC = max at minimum temperature.
Note 2: One output at a time; otherwise 16 rnA.
Table 8.13.3
Switching Characteristics '
ns
230
Programmable Logic Design Guide
Mnemonic Description
Input Signals
CLOCK
The CLOCK signal determines the timing of the outputs and should be
connected directly to the 8086 clock.
AO,BHE
These inputs come from the 8086 CPU. They must remain stable during the memory cycle for proper operation of the CAS outputs.
Chip enable. This input is used to select the memory and enable the
hidden refresh logic.
ALE
Address latch enable. This input is used to indicate the beginning of a
memory cycle.
RFCK
Refresh clock. The period of this input determines the refresh interval.
The duty cycle of this clock will determine the length of time that the
circuit will attempt a hidden refresh.
AWAIT
When connected to VCC, the DP84332 will insert an extra wait state in
selected memory cycles.
Refresh request. This input requests the OP84332 to perform a refresh.
The state of the RFCK input will determine what type of refresh will be
performed.
Output Signals
RASIN
This output provides a memory cycle start signal to the DP8408, and
provides RAS timing during refresh.
CASH, CASL
These signals are the separate CASs needed for byte writing. Their
presence is controlled by BHE and AO respectively.
ROY
This output is used to insert a wait state into the 8086 memory cycles
when selected and during a forced refresh cycle where the 8086
attempts to access the memory. The 8284A clock circuit should be
configured so that ASYNC is enabled.
RFSH
This output controls the mode of the OP8408 dynamic RAM controller. When low, it switches the DP8408 into an all RAS refresh mode.
This signal is also used to reset the refresh request logic.
Functional Description
A memory cycle starts when chip select (CS) and the address latch enable (ALE) are
true. RASIN is supplied from the DP84332 to the DP8408 dynamic RAM controller
which then supplies a RAS signal to the selected dynamic RAM bank. After the neces-
Applications
231
sary row address hold time, the DP8408 switches the address outputs to the column
address. The DP84332 then supplies the required CAS signals (CASH, CASL) to the
RAM. For byte operations, only one CAS will be activated. To differentiate between a
read and a write, the DT/R signal from the CPU is inverted and supplied by the DP8408
to the memory array.
A refresh cycle is started by one of two conditions. One is when a refresh is
requested (RFRQ is true), refresh clock (RFCK) is high, and a non-selected memory
cycle is started (CE is not true, ALE is high). This is called hidden refresh because it is
transparent to the CPU. In this case, the address supplied to the memories comes from
the refresh counter in the DP8408, and no CAS signals are generated from the
DP84332 . The second form of refresh occurs when a refresh is requested, refresh clock
is low, and there is no memory cycle in progress. This is called forced refresh, because
the CPU will be forced to wait during the next memory cycle to allow for the refresh to
be performed. In this case, a refresh is performed as before, but any attempt to access
memory is delayed by wait states until after the refresh is finished. In either case, the
refresh request is cleared by the refresh line (RFSH), which also goes to the DP8408.
In a standard memory cycle, the access can be slowed down by one clock cycle to
accommodate slower memories. This extra wait state will not appear during the hidden
refresh cycle, so faster devices on the CPU bus will not be affected.
With higher speed systems, memory speed requirements wili affect the performance of the system. Table 1 shows memory speed requirements at three different CPU
clock speeds.
t CAc
CPU
Clock
Frequency
No Wait
States
1 Wait
State
tRAH
8 MHz
5 MHz
::5105 ns
::5170 ns
::5223 ns
::5370 ns
::530 ns
::530 ns
Table 8.13.4 Memory Speed Requirements
System Description
For memory operation, the DP84332 can be directly connected between the control
signals from the CPU chip set and the DP8408 dynamic RAM controller. Each CAS output of the DP84332 is capable of driving eight memory devices. If additional drive is
required, a DP84244 buffer can be used to increase the fanout to the full capabilities of
the DP8408 (eight memories per output of the DP84244).
The 84332 is a standard National Semiconductor PAL part (PAL 16R8). The user
can modify the PAL equations to support his particular application. The 84332 logic
equations, function table, and logic diagram can be seen at the end of this section.
INTERFACING THE DPS40S TO AN SOS6 SYSTEM
...
N
...
ADDRESS
BUS
-- -
,.-
t
I
."
DM74lS139
9
"
99
ALE
r--+
SOS6
S284A
~
~
00-6,7
*
RAS 3
*
I'"
ADDRESS
PORT
ASVNC
ClK
DPS4300
RO-6,7
B1
BO
ADS
CS
..
RAS2
10 MHz MAX
RAS 1
~
*
~
RAS 16K,
CAS 64K
WE
AWAIT
CONTROL
'0' = NO WAIT+
'1' = ONE WAIT
SEE TABLE I
-!-
~
--..,..
16K,
64K
li'
~
(JQ
....
...
...
r')
~
..
--..
16K,
64K
~
i
~
....
It
...
...
-~
M2
(RFSH)IM1
*
-
MO.wE
f 11
CASH
CA_Sl
f
...
...
~
*
~ mmN
DP84332
JI"
...
RASO
AO
LATCHED { BHE
.
AO-6,7
WIN
RDY1
AEN1
*
CASl
CASH
I'"
16K,
64K
...
...
DRAMs
*
JDP84244~
OE
FOR CK;5;SMHz M1 = '0', MO= '1'
FOR CK>8MHz M1 ='1', MO='O' •
...
DATA BUS
"
CO-6,7
MM 74lS04
RFCK
RFRO
.. jIo.
--..
DPS40S
DTiA
DATA
PORT
N
\j.j
·THESE OUTPUTS -MAY NEED RESISTORS
Figure 8.13.3 System Block Diagram
...
Applications
233
Refresh Request Logic
To generate the refresh request for the DP84332, external circuitry is required. Figure 1
shows how this can be implemented, using standard SSI and MSI logic. A DM74LS393
counter is used to time the period between refresh cycles, while the DM74LS74
flip-flop is used to record the need of a new refresh. A better solution is to use the
24-pin DP84300 programmable refresh timer, as shown in Figure 2. This part allows a
maximum amount of time for a hidden refresh to occur before lowering the refresh
clock output, and implements the refresh request logic.
r--------------.RFCK
"0"
D
Q
SYSTEM
CLOCK
-< RFSH
1..-.____
Figure 8.13.4 Using a Flip-Flop and a Counter for Refresh Request Logic
SYSTEM _____-{>
CLOCK
DIVIDE
CONSTANT
--~~
RFSH
>------1
DP84300
Figure 8.13.5 Using the DP84300 Refresh Counter for Refresh Logic
234
Programmable Logic Design Guide
ADO·15
l
I
PCLK
I
'"
ADDRESS '"
CS
\ tsu-
ALE
hsu~
tpD
I
l
1
DATA READ
'"
I
7
- tw
1
---I
tpD
H
tpD
H
I
CAS
RAM
tpD
ADD----~(
ROW ADD
-I
X"-_____C_O_LU_M_N_A_D_D_RE_S_S_ _ _ _.....J)-
Figure 8.13.6 Timing Diagram; Read Timing
Applications
235
1--t1-1-12--,11-'--13-1-14-1
I
PCLK
ADO·15
{
L
ADDRESS
J
WRITE DATA
L
"
I
~Isu- -Iwf
ALE
Itsu~
DT/R
/
1
\
I
RASIN
t pD-
-I
tpD
-I
tpD
-I
1
CAS
tpD
RAM A D D - - - - - « ROW ADD
-I
X'-_____C_O_LU_M_N_A_D_D_R_ES_S_ _ _ _--J>-
Figure 8.13.7 Timing Diagram; Write Timing
236
Programmable Logic Design Guide
PCLK
ALE
READ DATA VALlD~
DMA ______________________________~(r--~--~}___
Figure 8.13.8 Timing Diagram; Memory Cycle With 1 Wait State
Applications
237
PCLK
RFCK
ALE
RASIN
______________~~--~~_+--~--~~~~~+_--L-
----....I
I
1..---
RAM ADD
RDY
'-----~--WAIT STATES DUE TO ALE
Figure 8.13.9 Timing Diagram; Forced Refresh
238
Programmable Logic Design Guide
1-'- - t 1 - - - - - - t 2 - - - I - - - t 3 - - - 1
r----l
PCLK---,
f
ADO·15
r----l
ADDRESS>
'\
CS
f-tsu -
ALE
~tsu
-
I
/
RFCK
~
tpD
H
tpD
H
tpD
~
tpD
H
RAMADD ...................................-«~_______R_EF_R_E_S_H_A_DD_R_E_S_S.....____J)r ---------
Figure 8.13.10 Timing Diagram, Transparent Refresh
PAL16R8
Dynamic RAM Controller Interface for the 8086-8408 System
CK AO IBHE ICS ALE RFCK WAIT /RFRQ NC GND IOE IRASIN ICA ICB
RDY IRFSH IA IB IMRQ VCC
MRQ: = IRASIN*ICA*ICB*RDY*/RFSH*IA*IB*/MRQ*RFRQ*CS*ALE*/RFCK +
MRQ*RASIN +
RAISIN*ICA*ICB*RDY*RFSH*IA*MRQ*CS*ALE
B: =
RASIN*ICA*ICB*RFSH*IA*IB +
RASIN*ICA*ICB*/RDY*/RFSH*IA*IB*WAIT +
RASIN*RDY*/RFSH*A*!B
Applications
A: =
RASIN*ICA*ICB*RDY*/RFSH*IA*/B*/wAIT +
RASIN*RDY*/RFSH*IA*B +
RASIN*RDY*IRFSH*A*/B
RFSH: = IRASIN*/CA*/CB*RDY*IRFSH*IA*IB*IMRQ*RFRQ*/CS*ALE*RFCK* +
lRASIN*/CA*/CB*RDY*IRFSH*IA*/B*IMRQ*RFRQ*IRFCK +
RASIN*/CA*/CB*RFSH*IA*/B
IRDY: = lRASIN*/CA*/CB*RDY*IRFSH*IA*/B*MRQ*RFRQ*CS*ALE*IRCFK +
RASIN*/CA*/CB*RDY*RFSH*IA*IMRQ*CS*ALE +
lRASIN*/CA*/CB*RDY*/RFSH*IA*/B*IMRQ*/RFRQ*CS*ALE*WAIT +
lRASIN*/CA*/CB*/RDY*IRFSH*IA*IB*MRQ*IRFRQ*WAIT +
RASIN*/CA*/CB*/RDY*RFSH*IA +
lRASIN*/CA*/CB*RDY*/RFSH*IA*IB*IMRQ*RFRQ*CS*ALE*RFCK*WAIT
CB: =
RASIN*/CA*/CB*/RFSH*IA*/B*BHE +
RASIN*CB*RDY*/RFSH*IA*B*WAIT +
RASIN*CB*RDT*IRFSH*N*B
=
RASIN*/CA*/CB*IRFSH*IA*/B*BHE +
RASIN*CA*RDY*IRFSH*IA*B*WAIT +
RASIN*CA*RDY*RFSH*A*/B
CA:
RASIN: = lRASIN*/CA*/CB*RDY*/RFSH*IA*/B*IMRQ*IRFRQ*CS*ALE +
lRASIN*/CA*/CB*/RDY*IRFSH*IA*IB*MRQ*/RFRQ +
RASIN*/CA*/CB*IRFSH*IA*/B +
RASIN*RDY*IRFSH*IA*B*WAIT +
lRASIN*/CA*/CB*RDY*IRFSH*IA*/B*IMRQ.*RFRQ*ALE*RFCK +
IRASIN*/CA*/CB* RDY*/RFSH*1A*/B*IMRQ*RFRQ*IRFCK +
RASIN*/CA*/CB*RFSH*IA*IB +
RASIN *RDY*IRFSH*A*/B
239
240
CK
C
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C
Programmable Logic Design Guide
AO
L
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Table 8.13.5 Function Thble
H
Applications
241
Inputs (0-31)
1
CLOCK~
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Figure 8.13.11 84332 Logic Diagram PAL16R8
'-'F OE
Programmable Logic Design Guide
242
8.14
A PAL DEVICE INTERFACE BETWEEN THE NATIONAL SEMICONDUCTOR
NS32032 MICROPROCESSOR, DP8409 DYNAMIC RAM CONTROLLER, AND
THE DP8400 EXPANDABLE ERROR CHECKER AND CORRECTOR
TERMINAL
RS·232
CPU &
CLOCK CHIP
ROM
NMC2764(2)
STATIC RAM
NMC2116(2)
.
[
Jt at
[
ADDRESS BUS_
iIo-
DATA BUS
..
16 BITS
~ ~~-'~~~~~------~
CONTROL BUS
[
oIi
INS8251
NS32202
NS32201
MONITOR
PARALLEL
PORT
INS8255
SERIAL 1/0
~
1
I ..
..
~
ADDRESS
~
4-PAL
CONTROLLER
1t
"
..
CONTROL
'II
DP8400
r
..
DP8409
,.
..
~
.
CONTROL
MEMORY (DRAM)
(256K DRAMS)
4 BANKS OF22
2M BYTES PLUS
CK BITS
..
~..
CONTROL 8409
DATA
CHECK BITS
Figure 8.14.1 DP8400, DP8409, NS16032 6 MHz Computer System
• Application 8.14 Is contributed by Webster (Rusty) Meier, Design Engineer of National Semiconductor
~
Applicatio~
243
Four PAL devices were used in this application in order to interface between the
NS32032, DPS409 and the DPS400. These PAL devices have the following features:
1.
The PAL devices control the following types of cycles:
a) READ cycles with no errors detected, ALWAYS CORRECT MODE
b) READ cycles with single error detected, the correct data will be written back
to memory
c) WRITE cycles
d) BYTE WRITE cycles
e) DRAM REFRESH cycles
The PAL devices take care of everything, no extra control logic is needed.
2.
The outputs of the PAL device control the DPS409, the DPS400 and insert
WAIT states at the appropriate times into the NS32032 cycles.
3.
The PAL device contains outputs to interrupt the NS32032, or cause a cycle
abort if an error greater than a single error is detected (DOUBLERR), or if there
is a bus parity error in data transfer from the CPU to memory (PARITYERROR).
4.
This PAL device design should work up to SMhz with the NS32032. If it is
desired to go faster, another WAIT state will have to be inserted into all cycles,
and the PAL device equations will have to be adjusted accordingly. Another
possibility would be to use the new oxide isolated DPS400 and the new DRAM
controller DPS419 (pin compatible with DPS409 in modes 0,1,4,5). These parts
would allow conSiderably more time margin.
5.
As can be seen by looking at the PAL device logic diagrams some external logic
is needed and some external logic may be added. For example, a system reset
input could be added to allow the internal flip-flops to be set to a known state
- in this case a refresh state (In PAL device number 1, for example, I used external logic to "NOR" the RFI/O input with a system RESET input). An output
enable input was also included to allow all the PAL device outputs to be
tri-stated.
6.
This PAL device interface performs HIDDEN REFRESHES (CPU not accessing
the Dynamic RAM controlled by the DPS409, indicated by /CS being high)
assuming a four-T state processor access cycle.
7.
Logic diagrams, the PAL device equations, and the timing diagrams follow this
introduction section. Basically everything is self-explanatory.
S.
I feel that if one is using this interface above 4-6MHz, he should use the fast
PAL devices (example "PAL16RSN' instead of "PAL16RS"). The fast PAL devices
have an input to output maximum time of 25ns and 15ns if it is a registered
output.
244
Programmable Logic Design Guide
The slow PAL devices have an input-to-output maximum time of 35ns and 25ns
if it is a registered output. Depending on the specific type of PAL's and logic
used, the user can calculate the speed requirements for the DRAM at the specified processor frequency with the timing that I have chosen.
9.
The four PAL devices that I have used allow full use of the DP8400 and all its
modes of operation. For example, one can perform a complete diagnostic test
of the DP8400 without needing to use the external memory. This is possible
using an I/O port to control M2 and Ml of the DP8400, along with diagnostic
control signals DIAGCS and DIAGD. These signals from the I/O port allow the
user complete control over the operating modes of the DP8400 and its data
syndrome, and check bit latches.
PAL Device Number 1 Inputs
1.
FCLK
Fast Clock (twice CTTL frequency) from NS32201
2.
CTTL
Output clock from NS32201
3.
ICS
Chip Select for the Dynamic RAM controlle;d by the
DP8409 and DP84oo.
4.
IDDIN
Data Direction in, from NS32032, indicates the direction
of the data transfer during a bus cycle.
5.
RFI/O
Refresh request output from the DP8409, is also used as a
reset input to set PAL to a known state.
6.
INCY
Output from PAL device number 2 indicating that the
NS32032is in an access cycle.
7.
IAOHBE
If address bit 0 AND high byte enable (fromNS32032) are
both low this input is high. Used to determine when byte
operations are in progress.
8.
NTSO
FromNS32201, indicating that timing state T2 is starting,
it stays low until the beginning of T4.
9.
IERRLATCH
Output from PAL device number 3 indicating that any
error, AE, was valid during a READ access cycle.
10.
IOE
Controlled externally, TRI-STATE PAL outputs.
Applications
,
ADDRESSIDATA BUS
2
BO
FROM
~ RC0-7
PROCESSOR- ~DS
SYSTEM
RGeK
~F~KOM
&
RFCK
Q0-71---....;~~\A-lADDRESS
RFRQ -HOLD
(RFI/O)
(TO "PI
DP0409
PROCESSOR)
PBUFOo---,).
"v
HOLD~_ U2 (RFSH)
RASI~_ RASIN-
RAS 0-31-;;~-JV\f"--MRAS 0-3
CAS!
CAS
WE~
WE-
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G~
CS
r-~....,
DECODER
L.---.:;.0'--...... 74LS2451+-~
,00'-.....- - - - - - - - - - - - -...... 010-7
ADD~ESSI
DATA 0-7
DIR
ADDRESSI
DATA 8-15
L.-_.;/0"---1~ 74LS2451+-.;,0.L-+------..-----------+lDI0-15
DATA
TRANSMlTt<>-H- DIR_
RECEIVE
G
MEMORY
Y
1+----~.,../<----t74LS24414__
PBUF1 0----...1
DOUTB
000-15
Y
~
DQO-7
OBO- OBO
DQO-15
OB1_ OB1
,
0
CSLE- CSLE
DLE- DLE
74LS244 ~ DOO-7
DP0400
OLE_ OLE
M 2 - M2
~OES
CO-5
0016-21
(CHECK BITS)
6/
C6'lFR'
~
"--- D116-21
'---- 74LS244 rr- (CHECK BITS)
@ RESISTOR REQUIRED DEPENDS ON DRAM LOAD .
• R=2.7KP.
Figure 8.14.2 DP8400/8409 System Interface Block Diagram
245
246
Programmable Logic Design Guide
PAL Device Number 1 Outputs
1.
lRASIN
Input to DP8409.
2.
IRFSH
Input to DP8409, causes the DP8409 to enter mode 1 to
do a refresh.
3.
IlDLY
Delay used by the PAL devices to determine the state of
the processor system.
4.
12DLY
Delay used by the PAL devices
the processor system.
5.
13DLY
Delay used by the PAL devices to determine the state of
the processor system.
6.
14DLY
Delay used by the PAL devices to determine the state of
the processor system.
7.
IODCLEN
IOLE, DLE, CSLE enable latch signal.
8.
ICYCLED
Indicates that a processor access cycle is complete.
to
determine the state of
PAL Device Number 2 Inputs
1.
IRFSH
Output from PAL device number 1 that indicates whether
the DRAMs are being refreshed.
2.
lRASIN
Output from PAL device number l.
3.
AO
Output from NS32032, address bit
4.
IHBE
Output from NS32032, high byte enable.
5.
IDDIN
Data Direction in, from NS32032.
6.
lADS
Address strobe from NS32032.
7.
NT SO
Output fromNS32201.
8.
12DLY
Output from PAL device number 1.
9.
14DLY
Output from PAL device number 1.
10.
/ERRLATCH
Output from PAL device number 3 indicating that an
error has occured during a READ cycle.
11.
CSOE
Chip select Output Enable, TRI,STATEthe outputs of the
PAL device when low, and also used for other control
purposes.
o.
Applications
247
PAL Device Number 2 Outputs
1.
lOBO
Controls DP8400 output buffer for byte "0".
2.
OBI
Controls DP8400 output buffer for byte" 1".
3.
IPBUFO
Controls the processor buffer transceiver
for byte "0".
4.
IPBUFI
Controls the processor buffer transceiver for byte "1".
5.
IDOUTB
Controls memory buffers that interface between the
DRAM and the DP8400/memory data bus.
6.
IINCY
Output indicating that theNS32032 is in an access cycle.
7.
ICWAIT
Output to NS32201 that causes WAIT states to be inserted
into the NS32032 bus cycles.
PAL Device Number 3 Inputs
1.
IDDIN
Output from NS32032.
2.
IRFSH
Output from PAL device number 1 indicating a forced
refresh of the memory.
3.
IAOHBE
Output of AO and IHBE logically NORed together. Therefore, if either input is high this signal will be low. This signal is useful to determine whether words or bytes are
being written.
4.
IERRLATCH
Output from PAL device number 4 indicating that an error
has occurred during a CS READ cycle, it may be a single or
multiple bit error.
5.
IlDLY
Input from PAL device number 1.
6.
12DLY
Input from PAL device number 1.
7.
13DLY
Input from PAL device number 1.
8.
14DLY
Input from PAL device number 1.
9.
IRESET
Input from external logic that resets the double bit error
latch IDOUBLERR or the parity error latch PARITYERR.
10.
AE
Output from DP8400 indicating an error.
11.
EO
Output from DP8400 indicating the type of error.
12.
El
Output from DP8400 indicating the type of error.
248
Programmable Logic Design Guide
13.
IPARITYERROR
This is an output of this PAL device also. This input indicates that a PARITY error has occurred during a WRITE
cycle.
14.
CSOE
Chip Select Output enable, tristates the registered outputs of the PAL device when low.
PAL Device Number 3 Outputs
1.
/WIN
Input to the DP8409.
2.
IMODECC
Input to the DP8400, changes between READ and
WRITE modes.
3.
IPARITYERR
Can be used to interrupt the system when a parity error
has been detected during a WRITE cycle.
PAL Device Number 4 Inputs
1.
FCLK
Fast clock fromNS32201.
2.
ODCLEN
10LE, DLE, CSLE latch enable input.
3.
DIAGCS
Enable input from I/O port for diagnostics to enable
CSLE, check bit syndrome latch enable.
4.
DIAGD
Enable input from I/O port for dagnostics to enable DLE,
data latch enable.
5.
IRESET
Reset input from I/O port to reset PAL error latches.
6.
ICYCLED
Output from PAL device number 1 indicating that a processor access cycle is complete.
7.
AE
Output from DP8400 indicating an error.
8.
lEO!
When this input is low it indicates that either error flag
EO or E1 was high.
9.
13DLY
This is an input from PAL device number 1.
10.
IOE
Output from 110 port that enables the PAL outputs.
11.
IDDIN
NS32032 input that indicates the direction of the bus
transfer during a bus cycle.
12.
IRFSH
Output from PAL device number 1 indicating a DRAM
refresh cycle.
Applications
249
PAL Device Number 4 Outputs
1.
DLE
Output that controls the DP8400 Data latch.
2.
CSLE
Output that controls the DP8400 Check bit Syndrome
latch.
3.
10LE
Output that controls the DP8400 Output latch.
4.
IDOUBLERR
Can be used to interrupt the system when a double bit
error has been detected during a READ cycle.
5.
IERRLATCH
Used in the PAL device controller to indicate that an error
has occurred during a ICS READ cycle, as indicated by AE
being valid.
250
Programmable Logic Design Guide
320328 MHz "READ" CYCLE (NO ERRORS)
WRITE CYCLE
FCLK
T1
CTTL
ADS
:WI
1
1
I
RASIN :
I
RAS
T2
1
1
CAS
1
1
DP8400 MEM
DATA BUS
1
1
I
~
I
TW
T4
T1
I
I I
1
1
1
1
1
I
1
1 \ 1
1
T3
1
1
I I
~I·
1
I
tV
1
1
T3
T4
I
I
1
1
1
1
~
1
I
"I' :
1
T2
I
I
I
1
I \1
1
1
1
iii
0
I I
1
1
~
A
1
1
Y
CHECK BITS
__ I
MODECC
I
WIN
I
1
1
ODIN
h
I
CWAIT
I
I
I
1
1
I
I
I
I
1
1
I
I
~
1
I
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A
.WRITE ECC
I
\ DA;::9n
1
1
1
I
1
1
1
I
I
I
1
1
1
I
I
I
I
AE
Figure 8.14.3 Timing Diagram; Read Cycle and Write Cycle
I I
Applications
32032 8 MHz "READ" CYCLE
W/SINGLE BIT ERROR
"WRITE" CYCLE - EXTENDED
FROM ERROR IN "READ" CYCLE
FCLK
CTTL
RASIN
DP8400 MEM
DATA BUS
QBC1, PBUF1
I
I
--"""''''''''''''''--1''---1-1
I
OB1, PBUFO
I
I
I
OLE, OLE I
I
CSLE
ODfLE
=
MODECC
I
I
ERRLATCH
I
Figure 8.14.4 Timing Diagram; Read Cycle With Simple Bit Error
251
252
Programmable Logic Design Guide
32032 8 MHz BYTE WRITE
FClK
CTTL
hili
ADS:
I
RASINI
I
\lJ
I
I
I
I
I
I
1
I
i',--+-1""""I--+--........-t---t---I--t-JI
~
i':
RASI
~~I~I~
I
I
DP8400 MEM
DATA BUS
OLE, OLE
CSlE = ODClE
CHECK BITS
I
I
:n
I
1--+---+1-;-:i
_I
r-----.. . .
-I-.......----\
1--+--+--+--+--+4
DDINI~~~~~~~~-~~~~~
I
Figure 8.14.5 Timing Diagram; Byte Write
Applications
NEW 32032 FORCED REFRESH THEN ACCESS
FCLK
CTTL
NTSO
CYCLED
~
RFI/O
I
RFSH
I
I
I"""""+-....+-.....-+-'
I
ODIN
I
I
CWAIT
I
I
Figure 8.14.6 Timing Diagram; Forced Refresh Then Access
253
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11
11
RESET
L
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Figure 8.14.7 Simulation Circuit
0
10
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n
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~.'"
,,~ 'r~
- tJ L::
'I
.........
.~ , ,,"
~"."'·• - ·=lrl\-l.
.~
"'-""-'
~~1'
~'
,,<-" , tt--""
~. ,,~""I~-'~
lDlY
~I
I
LLoo~
II~
~:: 2 ::~~~::YIERR
~_='"
I
LI
•
L
-
-3DlY
<>
~
f--f--
-
"",,OM
~
-2DLY
---p
1
,,~~'
1.~PBUFl
~ ~.
""",
~~
~."~~.,,: " ::f"""
-.
.....-
_
-AOS
-0'
<>
<>
-
~.-J Tn
-=~'
TC;:;:
~u
~11 ,'~OBO
-=
N
V\
-lDlY
11
nTr
_~2, II~
~
""';;;Dt::-;:Y'---~T"'--:::=
",,'
R!!,;;,2 • P ,,~OLY
'!!it'"
-..---r--l''--1:- 1
h I
- -
I
-RASIN
-RFSH
- PARITYERR
Q.
~
Applications
SIMULATION RESULTS
READ (NO ERRORS)
SCALE 2:1
STARTING TIME 591
TIME 591
591
691
791
891
I
I
CTTL
-CS
-ODIN
-RASIN
I
I
I
I
TRIGGER TIME 591
1291
1391
1491
I
I
I
-ri.- rl....rr... ri:..Jrt.J rt.JrL rL.
-i1
I
NTSO
-ADS
I
READ (W/SINGLE ERROR)
ENDING TIME 1521
1091
1191
991
-ru
I
I
I
I
-1DLY
I
I
-2DLY
I
-3DLY
I
-4DLY
-ODCLE
-INCY
-i1
rh
-CYCLED
L
-OB1
-PBUFO
-CWAIT
I •
-DOUTB
I
I
I
I •
II
II
I
I
-WIN
-MODECC
I
-ERRLAT
Figure 8.14.8 Simulation Timing Diagram; ReadlWrite Without Errors
255
256
Programmable Logic Design Guide
WRITE STANDARD FROM PREVIOUS
READ W/ERROR CYCLE
READ (W/ERROR)
CONTINUED
SCALE 2:1
TIME 1491
1491
I
CTTl
ENDING TIME 2421
TRIGGER TIME 1491
2091
2191
2291
1891
1991
STARTING TIME 1491
1591
1691
1791
I
I
I
I
I
I
I
2391
I
I
-1:.. r1- rtJr-L ri.... n:.r1-rL.
~
-CS
J
-ODIN
I
NTSO
I
I
-ADS
I
-RASIN
I
-1DlY
-2DlY
-3DlY
,
r
~
r
~
I
I
I
-4DlY
P-
I
-ODClE
-CYCLED
I
-PBUFO
I
I
I
I
~
I
I
-WIN
-ERRlAT
r-
I
-CWAIT
-MODECC
~
I"""
I
-OB1
-DOUTB
r
I
I
-INCY
I
I
I
r l-
I
I
J
Figure 8.14.9 Simulation Timing Diagram; Read With Error and Write Cycle
Applications
WRITE
BYTE WRITE
SCALE 2:1
TIME 2391 STARTING TIME 2391
2391
2491
2591
2691
I
CTTl
I
ENDING TIME 3321
TRIGGER TIME 2391
2791
2891
2991
3091
3191
I
I
I
I
I
3291
~
..rt.Jr--l.J ruru rL rL rL rL
-CS
-ODIN
I
NTSO
-ADS
I
I
-RASIN
I
-1DlY
L
j
-2DlY
I
-3DlY
-4DlY
-ODClE
-INCY
-CYCLED
-OB1
-PBUFO
-
rt-
---,
I
-
I
I
,
I
-CWAIT
-DOUTB
t
t
I
l
I
I
I
I
I
I
L-
I
-WIN
-MODECC
'---
- ru
I
I
-ERRlAT
Figure 8.14.10 Simulation Timing Diagram; Byte Write
257
258
Programmable Logic Design Guide
SCALE 2:1
TIME 3591
3591
CTTl
-CS
-ODIN
3791
3691
3891
3991
4091
4191
4291
4391
4491
-ri..JrUrL.rL'n:. rt-n:..n:.
-h
RFI-O
AD
-HBE
NTSO
-ADS
-RASIN
-RFSH
-1DlY
- rt..J
I
-
~p
- --,
/
I
I
-2DlY
I
-3DlY
I
I
I
-4DlY
I
/
\
1
L
\
-ODClE
"- ......, ....
-INCY
j
~
-CYCLED
-
-OBO
-OB1
-PBUFO
-PBUF1
Figure 8.14.11 Simulation Timing Diagram; Forced Refresh Then Access
Applications
WRITE
SCALE 2:1
CTTL
TIME 3101
259
FORCED REFRESH & READ ACCESS
(W/ERROR)
ENDING TIME 4031 TRIGGER TIME 3101
STARTING TIME 3101
3101
3201
3301
3401
3501
3601
3701
3801
3901
4001
I
I
I
I
I
I
I
I
I
I
-ri...JrL rL rt.. rt.. rt.. rr.. rL
-CS
-DDIN
I
NTSO
-ADDS
-"L1
II
I
L
LJ
-RASIN
I
-1DlY
I
I
I
r
-2DlY
-3DlY
-4DlY
-ODClE
-INCY
-CYCLED
I
I
I
--,
I
-
-OB1
-PBUFO
I
I
-CWAIT
I
~
~
~
-DOUTB
-WIN
-MODECC
_J
-n
I
I
I
-ERRlAT
Figure 8.14.12 Simulation Timing Diagram; Write, Forced Refresh and Read
Access
260
Programmable Logic Design Guide
FORCED REFRESH FOllOWED BY READ ACCESS (W/ERROR)
SCALE 2:1
TIME 4001 STARTING TIME 4001 ENDING TIME 4931 TRIGGER TIME 4001
4001
4101
4201
4301
4401
4501
4601
4701
4801
I
CTTL
I
I
I
I
I
I
I
I
4901
I
--L.n:.n:.ri: r1:-ri....ri.... r-L.tT5
-CS
-ODIN
I
NTSO
-ADDS
-RASIN
r -
/'
-1DlY
-2DlY
\
-3DlY
-4DlY
l
J
J
I
\, 1
I
•
-ODClE
L
/
I.
I
-INCY
J
•
I
I
-CYCLED
-OB1
-DOUTB
-WIN
-MODECC
-ERRLAT
t
t
t
r
•
\
-PBUFO
-CWAIT
V
...... I-
0~
•
r
I
tt-
\
•
\
~
L
1
Figure 8.14.13 Simulation Timing Diagram; Forced Refresh Followed by Read
Access (With Error)
Applications
261
PAL Device Number 1
This PAL Device is Part of a Four PAL Device Set Needed to Control the 32201 ,
8409, 8400 Interface
PAL16R8A
RFSH : =
IRFlO* IIDLY* 12DLY* IINCY* ICTTL +
RFSH *IRFlO +
RFSH*IDLY +
RFSH*4DLY
IDLY: =
RFSH *IRFlO +
RFSH *1 DLY* 14DLY +
RFSH*IDLY*CTTL +
; RFSH in idle states or in long
; accesses of, other devices or
; at the beginning of an access
IRFSH*CS*IDLY'CTTL *DDIN +
IRFSH*CS*IDLY*CTTL *IDDIN *AOHBE
;
;
;
;
;
;
;
;
Start RFSH IDLY
Hold RFSH IDLY
Extend RFSH IDLY
For READs and WRITEs
For READs
For BYTE WRITEs
Extend IDLY during READ
Extend IDLY during BYTE WRITEs
2DLY: =
IDLY*/4DLY +
IDLY*RFSH +
IRFSH*CS*IDLY*DDIN +
IRFSH *CS *1 DLY *IDDIN *AOHBE
;
;
;
;
For READs
Extend for
Extend for
Extend for
or WRITEs
RFSH
READ
BYTE WRITE
;
;
;
;
;
For READs
Extend for
Extend for
Extend for
Extend for
or WRITEs
RFSH
READ
READ with error
BYTE WRITE
;
;
;
;
;
For READs
Extend for
Extend for
Extend for
Extend for
or WRITEs
RFSH
READ
READ with error
BYTE WRITE
;
;
;
;
;
;
;
Start lRASIN
READ cycle without error
READ cycle with error
WRITE cycle
BYTE WRITE cycle
Hidden RFSH, assume on
four 'T' States.
IRFSH*RASIN* 12DLY* 13DLY* 14DLY +
IRFSH*CS*RASIN*/4DLY*DDIN +
IRFSH*CS *RASIN* 14DLY* IDDIN* AOHBE +
3DLY: =
2DLY*/4DLY
2DLY*RFSH +
IRFSH*CS*2DLY*DDIN +
IRFSH*CS*3DLY*ERRLATCH*RASIN +
IRFSH*CS*2DLY*/DDIN*AOHBE
4DLY: =
3DLY*RASIN +
3DLY*RFSH +
IRFSH*CS*3DLY*2DLY*DDIN +
IRFSH*CS*3DLY*ERRLATCH +
IRFSH*CS*RASIN*4DLY*IDDIN* AOHBE
RASIN: =
IRFSH*INCY*/CYCLED*/4DLY*/CTTL +
IRFSH*CS*RASIN*DDIN*IDLY +
IRFSH*CS*RASIN*DDIN*ERRLATCH*CYCLED +
IRFSH*CS*RASIN*DDIN*/CYCLED +
IRFSH * CS * RASIN *IDDIN* 3DLY* AOHBE +
IRFSH*INCY* INTSO* IERRLATCH* 14DLY*RASIN
262
Programmable Logic Design Guide
CYCLED: =
IRFSH*IDLY*2DLY*3DLY'4DLY +
IRFSH*/DDIN*2DLY*3DLY*/AOHBE +
CYCLED *CTTL +
CYCLED "INTSO +
CYCLED*RASIN*/DDIN* AOHBE
ODCLEN: =
CS*/RFSH"DDIN*RASIN*2DLY'
14DLY*/ERRLATCH +
CS '/RFSH*/DDIN*RASIN*/2DLY'
13DLY*/4DLY*/AOHBE +
CS */RFSH '/DDIN *RASIN* 2DLY*/4DLY* AOHBE +
CS*/RFSH*IDDIN*RASIN"IDLY*CYCLED* AOHBE
; BYTE WRITE or READ cycles
; WRITE cycle
; End CYCLED
; End BYTE WRITE cycle
; READ and READ with error
; WRITE cycle
; BYTE WRITE cycle
; BYTE WRITE cycle
PAL Device Number 2
PAL16L8A
IF (CSOE) OBO =
IDOUTB"DDIN*4DLY*RASIN*/RFSH +
IDOUTB*AO"HBE*/DDIN*4DLY*RASIN*/RFSH
IF (CSOE) OBI =
IDOUTB*DDIN*4DLY*RASIN'/RFSH +
IDOUTB • lAO "/HBE */DDIN* 4DLY* RASIN*/RFSH
IF (CSOE) PBUFO =
IDOUTB *lAO *DDIN*4DLY" RASIN*/RFSH +
IDOUTB*/AO*/HBE */DDIN*4DLY*RASIN"
IRFSH+
IDOUTB "/Av' HBE *IDDIN *RASIN*/RFSH
IF (CSOE) PBUFI =
IDOUTB*IIBE*DDIN*4DLY*RASIN*/RFSH +
;
;
;
;
READ or READ
w/error
BYTE WRITE
high byte
;
;
;
;
READ or READ
w/error
BYTE WRITE
low byte
; READ,
; READ/error
; BYTE WRITE
; Word WRITE
; READ,
; READ/error
IDOUTB * AO *HBE *IDDIN* 4DLY* RASIN *
IRFSH +
IDOUTB*/AO*HBE*IDDIN*RASIN*/RFSH
; BYTE WRITE
; Word WRITE
IF (CSOE) DOUTB =
DDIN*/RFSH*2DLY*/4DLY +
lAO */HBE "/DDIN*/RFSH'2DLY*/4DLY +
AO*HBE*/DDIN*/RFSH*2DLY*/4DLY
; READ cycle
; BYTE WRITE
; BYTE WRITE
Applications
IF (VCC) INCY =
IRFSH *ADS */4DLY +
IRFSH*CSOE*/NTSO*/RASIN +
INCY*/4DLY +
INCY*CSOE*/DDIN*RASIN +
INCY*/CSOE*RASIN
IF (CSOE) CWAIT =
RFSH*CSOE*/NTSO +
IRFSH*CSOE*/NTSO*/RASIN +
IRFSH*DDIN*RASIN*2DLY*INCY*/4DLY +
IRFSH*IDDIN*IAO*/HBE*RASIN*/4DLY +
IRFSH*IDDIN*AO*HBE*RASIN*IRDLY +
IRFSH*INCY*ERRlATCH*/2DLY*INTSO
;
;
;
;
;
;
;
Start INCY
Start INCY for access
after forced refresh
or READ w/error
Continue INCY
WRITE cycles
Non-/CS cycles
;
;
;
;
;
;
;
;
;
Access in RFSH
Access after
forced refresh
READ cycle
BYTE WRITE
BYTE WRITE
Insert WAITS
into the next
cycle
PAL Device Number 3
PAL14L4A
WIN =
IRFSH*ERRlATCH*/2DLY*3DLY*4DLY*CSOE
IRFSH*DDIN*3DLY*/AOHBE*CSOE +
IRFSH*IDDIN*AOHBE*12DLY*4DLY*CSOE
MODECC =
IRFSH*ERRlATCH*/lDLY*4DLY*CSOE +
IRFSH*IDDIN*IAOHBE*CSOE +
IRFSH*IDDIN*AOHBE*/IDLY*4DLY*CSOE
PARIlYERR =
IRFSH*IDDIN*IRESET*4DLY*
lAE*EO*/El*AOHBE*CSOE +
IRFSH*IDDIN*IRESET*4DLY*
lAE*/EO*El *AOHBE*CSOE +
IRFSH*DDIN*IRESET*4DLY*
lAE*/EO*/El *IAOHBE*CSOE +
PARIlYERR*IRESET*CSOE
+
; READ w/error
; Word WRITE
; BYTE WRITE
; READ w/error
; Word WRITE
; BYTE WRITE
;
;
;
;
Parity error byte
"1" during WRITE
Parity error byte
"0" during WRITE
; Parity error
; both bytes
263
264
Programmable Logic Design Guide
PAL Device Number 4
PAL16R6A
IDLE: =
ODCLEN+
DLE*DIAGD
; Hold IDLE for
diagnostics
ICSLE: =
ODCLEN +
CSLE*DIAGCS
; Hold ICLSE for
diagnostics
OLE: = ODCLEN
DOUBLERR: =
IRFSH* IDIAGCS" IDIAGD* IRESET*
OLE*CYCLED*AE*/EOI +
DOUBLERR *IRE SET
ERRLATCH: =
DDIN*OLE " CYCLED *IDIAGCS */DIAGD*AE +
ERRLATCH*3DLY
; Double bit error
; during READs
; or BYTE WRITEs
; Error during READ
Applications
265
(16201)
FCLK
Inputs (0-31)
........
Cl2l
4S"
i Slall
,.IJIH;
1&11,,1.
h/,lllJ
" ( " ••
,,'J.ll
r----...
!--'
(1 6201) CTTL
.
..,
2 ~
"
CS
3
~:-.....
."",
""
!=~
~
ODIN
4
RFPQ
(8409)
-
~
~
~
RFIIO
RFIIO
5
SYSTEM
RESET
f: r--....
""
"'""
"
~~
~
""
""
""
""
~
Fl---'
~
INCY
(PAL #2 OUTPUT) 6
~
~./
..
..."""
--AOHBE
:~
"
F !--'
~
7
AO
HBE
IF EITHER
INPUT HIGH
THIS IS LOW
(FRO M 16032)
8
NTSO
ERRLATCH
(PAL #3 OUTPun 9
~
Ul
r
"
""
"""
"
II
(ACTIVE
HIGH)
~
~
""
(1 6032)
~
r-
..
.."
".."
.
H~
F !-'
~
~
Ol
"
."""
r
.......
f-'
~
~
""
"
..
Figure 8.14.14 Logic Diagram of PAL Device #1
~
~
~
~
--;J.
..
19
I.:l
....
18
~17
....
-
I.J..
16
v<>R....
15
R.....
14
I.:L
13
v<>-
*~
11
266
Programmable Logic Design Guide
(PAL#l)
RFSH
Inputs (0-31)
1
Dill
4!i17
•
,,
,,•
,
.11111
UUIUS
11171111
2lI21Un
l4nlll1
21%UDJI
~
I
(PAL#l)
.
RASIN
2
3
..
AD
4 HBE
.1--
,,
""
""
""
J
~~:J
"""
"""
""
~
5
..
ODIN
(16032)
ADS
6
..
(16201)
.
NTSO
7
PAL#l)
..
2DLY
8
-
PAUl)
4DLY
9
.
OBl
18
PBUFO
17
~
"~: :
(16032)
OBO
19
J
11-
""
"
PBUFl
16
~
JI
""
""
"""
"
~
DOUTB
15
A
.t---
.."
......""
J
....
"
INCY
14
.....
...,
"
."""
....J
"
....
""
~
II
51
II
"
""
~
D 12 l
.. 5 Ii 7
•
~IDll
UIlUt!i
Figure 8.14.15
IIUIII.
2D212Ul
nlSlU7
CSOE
13
OE
TRISTATE
INPUT, MUST
BE HIGH TO
CWAIT ENABLE
12 PAL OUT PUT
ERRLATCH
11
2UUDJI
Logic Diagram of PAL Device #2
CS
Applications
267
Inputs (0-31)
II I I I
4 ~ '1
"
In 11
U Il
2011
nu
I'Hun
1IlijOli
(16201) 1
ODIN
(PAL#1)
~=
RFSH
~=
AOHBE
3
AO~3
k-
19
~
HBE~
CSOE
IF EITHE R IS HIGH
THEOU TPUT IS LOW
PARITYERR
ERRLATCH
~
....
-
""
""
(PAL#1)
....
J
,
../
"""
18
I
17
PARITYERR
1DL.Y ~
.
."
16
WIN
"
".
""
~O
..
..."
- , )0
l!
(PAL#1)
2DLY
(PAL#1)
3DLY
~
J
-
~
(PAL#1)
~
.
....
8
4DLY ---t..?
~
15
MODECC
14
13
E1
12
EO
11
9
---u>
~
~
>-
::::r--,.
>-1......-'
- YCLED
C-- 6
'"
"'
../
7 ..
AE
1J
~
"'
../
EO
8
lAl::
E1
E01
_ _ 9 ..
3 DLY
"
~
~
~
~~
~
Figure 8.14.17 Logic Diagram of PAL Device #4
i;l.
17
Q
16
It:L....
15
....
....
~
-yo-
CSLE
DOUBLERR
14
~
12
11
ERR LATCH
9
National Masked Logic (NML)
National Masked Logic (NML) was introduced to provide cost benefits of volume production to programmable logic users who have large volume applications for a given
logic pattern. NML devices are mask-programmed and functionally tested in-house by
National, thus relieving the customer of programming and testing the devices. Therefore, for these volume applications, the customer can simplify his production line and
gain cost savings through the use of NML.
The NML option is available for all of National's programmable logic products. The
NML products have the same data sheet specifications as the field-programmable products. The following are the procedures and guidelines involved in using NML.
9.1 NML PROCEDURE
The procedure for using NML is shown in Figure 9.1.1. When a customer has decided
on the NML approach, the equations should be supplied to National for generation of
programmed parts. These programmed devices are then sent to the customer for verification of the logic pattern in the application. After the logic has been verified by the
customer in his circuit, National is notified. At that point orders for the masks are
placed in-house at National. At the same time, the Test Engineering and Product Engineering departments prepare to test and qualify the product upon generation of first
silicon. After successful testing and qualification, the product is released for routine
production.
When the order is placed the customer will also be required to provide test vectors to functionally test the logic. When considering the use of NML, the customer
should keep in mind the need for functional testing of the part. He should generate a
sequence of test vectors that will test the logic functionality to meet his needs.
269
270
Programmable Logic Design Guide
VERIFICATION
ENGINEERING
PREPARES
TO QUALITEST
8-12 WEEKS
Figure 9.1.1
NML-Procedure
9.2 NML GUIDELINES
In evaluating whether NML is an economic option for a certain application, it is important to keep in mind the following guidelines. The most important and somewhat obvious point is that the logic pattern must be verified and frozen. A minimum quantity for
economic justification of NML is at least 10,000 units. At these volumes there is usually
a nominal charge for mask generation. The lead time from the point at which the equations are verified to the point at which finished goods are shipped is 8-12 weeks.
NML users typically realize cost savings of between 10-40 % over the cost of
unprogrammed devices, depending on the volume and the device being used. Keep in
mind that NML users do not have to incur programming and testing costs associated
with unprogrammed devices.
10
Advantages of National's
Programmable Logic Family
National Semiconductor has taken leadership of the programmable logic market
through commitments in technology, quality, customer service and support, and by
offering a broad product line. In addition, National is also committed to continuing
developments in software leading to automated design with programmable logic
products.
10.1 TECHNOLOGY
Through innovations in circuit design and process technology, National was the first to
introduce the fastest PAL devices, thus clearly establishing itself as the leading technology house for programmable logic devices. The technology used is the proprietary
oxide isolated OXISS process that offers higher integration than other bipolar processes
and also offers improved performance. The advantages of this superior technology are
being harnessed to produce ECL programmable logic devices that will offer speeds at
6 ns. Furthermore, National is also pursuing a major development program to introduce CMOS programmable logic devices.
10.2 BROAD PRODUCT LINE
National's leading technology position has resulted in the broad TTL product line that
is currently available. This product line offers a variety of speed, power, and density
options as evidenced by the product line description in Chapter 4. For the future,
National will offer a broader spectrum of speed and power options through CMOS and
ECL devices. More options in the TTL family of programmable products are also forthcoming. Some of the forthcoming features are FPLA-type structures, higher densities,
improved testability through register preloads, and scan registers.
To complete the product line, National is also committed to software development
and support. PLAN is the first step toward meeting that commitment.
271
272
Programmable Logic Design Guide
10.3 CUSTOMER SERVICE AND SUPPORT
Within the field offices, National has fully equipped and trained Field Application Engineers (FAEs) who can support customers in designing with programmable logic. The
FAEs also have the software and the development systems at their disposal to fully support the customer. In addition, the factory applications and engineering staff are also
available to support the customer in programmable logic-based deSigns.
Customer training seminars are also given, as part of National's service, to inform
and train customers on programmable logic products and their applications.
11
Data Sheets
11.1 PAL DEVICE DATA SHEETS
The PAL device data sheets are broken down into two main sections: 20-pin PALs and
24-pin PALs, and within each section the various speed/power groups are shown
separately.
Description
The PAL device family utilizes National's Schottky TTL process and bipolar PROM
fusible-link technology to provide user-programmable logic to replace conventional
SSIIMSI gates and flip-flops. Typical chip count reduction gained by using PAL devices
is greater than 4: 1.
The family lets the systems engineer customize his chip by opening fusible liq.ks to
configure AND and OR gates to perform desired logic functions. Complex interconnections that previously required time-consuming layouts are thus transferred from PC
board to silicon where they can be easily modified during prototype checkout or
production.
The PAL device transfer function is the familiar Sum-of-Products with a single array
of fusible links. Unlike the PROM, the PAL device is a programmable AND array, driving
a fixed OR array. (The PROM is a fixed AND array driving a programmable OR array.) In
addition, the PAL device family offers these options:
• Variable input/output ratio.
• Programmable TRI-STATE® outputs.
• Registers and feedback.
Unused inputs are tied directly to Vee or GND. Product terms with all fuses blown
assume the logical high state, and product terms connected to both true and complement
of any single input assume the logical low state. Registers consist of D-type flip-flops that
are loaded on the low-to-high transition of the clock. PAL device logic diagrams are
shown with all fuses blown, enabling the designer to use the diagrams as coding sheets.
The entire PAL device family is programmed using conventional PROM programmers with appropriate personality and socket adapter cards. Once the PAL device is
programmed and verified, two additional fuses may be blown to make verification difficult. This feature gives the user a proprietary circuit that is very difficult to copy.
273
274
Programmable Logic Design Guide
Features
• Programmable replacement for SSI and MSI TTL Logic.
• Simplifies prototyping and board layout.
• Skinny DIP packages.
• Reliable titanium-tungsten fuses.
• Available in standard, low power and high speed versions.
Part
No.
10Ha
12H6
14H4
16H2
10la
1216
1414
16L2
16C1
16la
16Ra
16R6
16R4
No. of
Inputs
No. of
Outputs
10
12
14
16
10
12
14
16
16
10
a
a
a
a
6
4
2
a
6
4
2
1
a
a
a
a
No. of
I/0s
No. of
Registers
Output
Polarity
a
6
4
AND-OR
AND-OR
AND-OR
AND-OR
AND-NOR
AND-NOR
AND-NOR
AND-NOR
AND-OR/NOR
AND-NOR
AND-OR
AND-OR
AND-OR
6
2
4
Thble 11.1.1
Part
No.
No. of
Inputs
No. of
Outputs
12L10
14la
1616
1al4
2012
20la
20110
20Ra
20R6
20R4
20X10
20Xa
20X4
12
14
16
1a
20
14
12
12
12
12
10
10
10
10
a
6
4
2
2
2
a
6
4
10
a
4
No. of
1I0s
AND-OR Array
AND-OR Array
AND-OR Array
AND-OR Array
AND-OR-invert Array
AND-OR-invert Array
AND-OR-invert Array
AND-OR-invert Array
AND-OR/AND-OR-Invert Array
AND-OR-Invert Array
AND-OR-Invert Register
AND-OR-Invert Register
AND-OR-Invert Register
20-Pin PAL Devices
No. of
Registers
6
a
2
4
a
6
4
2
6
10
a
4
Table 11.1.2
Functions
Output
Polarity
AND-NOR
AND-NOR
AND-NOR
AND-NOR
AND-NOR
AND-NOR
AND-NOR
AND-NOR
AND-NOR
AND-NOR
AND-NOR
AND-NOR
AND-NOR
Functions
AND-OR Invert Gate Array
AND-OR Invert Gate Array
AND-OR Invert Gate Array
AND-OR Invert Gate Array
AND-OR Invert Gate Array
AND-OR Invert Gate Array
AND-OR Invert Gate Array
AND-OR Invert w/Registers
AND-OR Invert w/Registers
AND-OR Invert w/Registers
AND-OR-XOR Invert w/Registers
AND-OR-XOR Invert w/Registers
AND-OR-XOR Invert w/Registers
24-Pin PAL Devices
Data Sheets
Operating
Supply Voltage, Vcc
Input Voltage
Off-State Output Voltage
Storage Temperature Range
Table 11.1.3
275
Programming
7V
12V
5.5V
12V
5.5V
12V
-65·C to +150·C
Absolute Maximum Ratings
.
5V~~' ,
.
SMPAL.
IIEDPAL
R1.3110
R2.750
COU'L •
Rl.aoo
RZ .. 310
R1 .. 56Q
RZ .. 1,1!!;
OUTPUT
Ie..
-=
RZ
';"
Table 11.1.4 Standard Test Load
-
EQUIVALENT INPUT
TYPICAL OUTPUT
akQ NOM
-
40QNOM.
I-+--
INPuro-.....-iE=--......
TIMING
'NPUT
,--------lV
LVr
(SEE NOTE Al
------:-.-114'--,__
ov
ISET'UP~!
~ _'"'_LD_ _ _ _ _ 3V
DATA
'NPUT _ _ _ _oJ
VT
VT
'-------ov
HIGH-LEVEL
PULSE____
LOW'~~~i~
ENABLE
'-------ov
IN·PHAse
-+_,
,.4-.....:+-----VOH
OU'PUT _ _ _
OUT OF PHASE
OUTPUT
v,
VT
IW--=., ___
Vt
Enable and Disable
Propagation Delay
, -_ _. - - - - - - - - - 3 V
INPUT
8
Pulse Width
Set-Up and Hold
(ENABLE PIN OR INPUTI
---~
NORMALLY HIGH
OUTPUT
.....- - - - V O L
IS10PENI
,.----VOH
NORMAllY lOW
.....- . . J ' - - - - - - - V O L
(Sl CLOSED)
OUTPUT
Note A: Vr= 1,5V
Note B: Ct. includes probe and jig capacitance.
Nate C: tn the examples above. the phase rela·
tionships between inputs and outputs have been
chosen arbitrarily,
Figure 11.1.1
Note D: All input pulses are supplied Dy generations having the following characteristics:
PAR = 1 MHz, Zoor = 50 Q.
Test Waveforms and Schematics of Inputs and Outputs
276
Programmable Logic Design Guide
10H8, 12H6, 14H4, 16H2, 16C1, 10L8, 12L6, 14L4, 16L2
Recommended Operating Conditions
Symbol
Military
Parameter
Min
Nom
4.5
5.0
Commercial
Unit
Max
Min
Nom
Max
5.5
4.75
5.00
5.25
V
VCC
Supply voltage
IOH
High-level output current
-2.0
- 3.2
mA
IOL
Low-level output current
8
8
mA
TA
Operating free air temperature
75
·C
125
- 55
0
Electrical Characteristics
Over Recommended Operating Temperature Range
Symbol
Parameter
VIH
High·level input voltage
VIL
LOW-level input voltage
VIC
Input clamp voltage
VOH
High-level output voltage
VOL
Low-level output voltage
Test Conditions
Typ
Max
VCC = MIN II = -18mA
VCC = MIN
VIH = 2V
VIL = 0.8V
IOH = MAX
VCC = MIN
VIH = 2V
VIL = 0.8V
IOL = MAX
Vce = MAX
IIH
High-level input current
Vee = MAX
IlL
Low-level input current
Vce = MAX
VI = 0.4V
lOS
Short-circuit output current
Vce = 5V
VO=OV
ICC
Supply current
Vce = MAX
Unit
V
2
Input current at maximum
input voltage
II
Min
-,0.8
0.8
V
-1.5
V
2.4
V
0.5
V
1.0
mA
25
p.A
- 250
p.A
-130
mA
90
mA
VI = 5.5 V
VI = 2.4V
- 30
55
Switching Characteristics
Over Recommended Ranges of Temperature and Vcc
Military
Symbol
Parameter
Test Condltionstt
R1 =5600
R2 = 1.1 kIl
= -55·to + 125·C
VCC = 5.0V :!: 10%
TA
Min
tpo
From any input to any output
Table 11.1.5
CL
= 50pF
Typ
25
Max
45
Commercial
TA = O· to 75·C
VCC
Min
= 5.0V
± 5%
Typ
Max
25
35
Unit
ns
AC and DC Specifications for 20-Pin Standard Small PAL Devices
Data Sheets
277
16L8, 16R8, 16R6, 16R4
Recommended Operating Conditions
Symbol
Military
Parameter
VCC
Supply voltage
IOH
High-level output current
IOl
low-level output current
TA
Operating free air temperature
Min
Nom
4.5
5.0
-55
Commercial
Unit
Max
Min
Nom
Max
5.5
4.75
5.00
5.25
V
-2.0
-3.2
mA
12
24
mA
75
·C
125'
0
'Operating Case Temperature only. TC = 125"C
Electrical Characteristics
Over Recommended Operating Temperature Range
Symbol
Parameter
Test Conditions
VIH
High·level input voltage.
Vil
low·level input voltage
VIC
Input clamp voltage
VOH
High·level output voltage
Val
low·level output voltage
10ZH
Off·state output current
high·level voltage applied
10Zl
Off·state output current
low·level voltage applied
VIH = 2V
= O.BV 10l = MAX
Vee = MAX, VIH = 2V,
Va = 2.4V. Vil = O.BV
Vee = MAX, VIH = 2V
Va = 0.4V. Vil = O.BV
Input current at maximum
input voltage
Vee = MAX
IIH
High·level input current
Vee MAX
III
low·level input current
lOS
Short·circuit output current
Min
Typ
Max
2
Vee = MIN
11= ·lB mA
Vee = MIN
VIH
,
Vil = O.BV
= 2V
10H = MAX
Unit
V
O.B
V
- 1.5
V
2.4
V
Vee = MIN
II
0.5
V
100
p.A
- 100
J1A
1.0
mA
VI = 2.4V
25
p.A
Vee MAX
VI = 0.4V
- 250
I,A
Vee = 5.0V
Vo=OV
-130
mA
Vil
16lB
Supply
ICC
Current
Vee
16A4, 16R6, 16AB
VI = 5.5 V
-30
140
lBO
150
lBO
= MAX
mA
Table 11.1.6 AC and DC Specifications for 20-Pin Standard, Medium PAL Devices
278
Programmable Logic Design Guide
Switching Characteristics
Over Recommended Ranges of Temperature and Vee
Symbol
Parameter
Test Condltlonstt
R1, R2
Military
Commercial
TA=-SSo
to+ 12SoC
Vcc = S.OV ± 10%
TA=Oo
to 7SoC
Vce S.OV±S%
Min
Typ
Max
Typ
Max
2S
45
25
35
ns
15
25
15
25
ns
15
25
15
25
ns
15
25
15
25
ns
C L = 50pF
25
45
25
35
ns
C L =5pF
25
45
25
35
ns
tpD
Input to output
tpD
Clock to output
tpzx
Pin 11 to output enable
tpxz
Pin 11 to output disable
C L =5pF
tpzx
Input to output enable
tpxz
Input to output disable
tw
Width of clock
tsu
Setup time
th
Hold time
C L =50pF
Min
Unit
High
25
25
Low
25
25
16R8. 16R6. 16R4
45
0
ns
35
-15
0
ns
-15
ns
ttSee Standard Test Load and Definition of Waveforms
Table 11.1.6 AC and DC Specifications for 20-Pin Standard, Medium PAL Devices
(Cant.)
Data Sheets
279
10H8A, 12H6A, 14H4A, 16H2A, 16C1A, 10L8A, 12L6A, 14L4A, 16L2A
Recommended Operating Conditions
Commercial
Military
Symbol
Parameter
Min
Typ
Max
Min
Typ
Max
4.5
5
5.5
4.75
5
Units
Vee
Supply Voltage
5.25
V
10H
High Level Output Current
-2
-3.2
rnA
10L
Low Level Output Current
8
8
rnA
TA
Operating Free-Air Temperature
Te
Operating Case Temperature
125
-55
75
0
°C
°C
Electrical Characteristics
Over Recommended Operating Temperature Range
Symbol
Parameter
Min.
Test Conditions
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
Vie
Input Clamp Voltage
Vee = Min., 11= -18mA
VOH
High Level Output Voltage
Vee = Min., VIH = 2V
VIL = 0.8V, 10H = Max.
VOL
Low Level Output Voltage
Vee = Min., VIH = 2V
VIL = 0.8V, 10L = Max.
II
Input Current at Maximum Input Voltage
IIH
High Level Input Current
Low Level Input Current
IlL
Max.
Typ.
Unit
V
2
-0.8
0.8
V
-1.5
V
V
2.4
0.5
V
Vee = Max., VI=5.5V
1
mA
Vee = Max., VI = 2.4 V
25
,..A
Vee = Max., VI = 0.4 V
-0.25
,..A
-130
rnA
90
mA
los
Short Clreult Output Current
Vee=5V
lee
Supply Current
Vee = Max.
-30
55
Switching Characteristics
Over Recommended Ranges of Temperature and Vee
Military: TA = - 55°C to + 125°C, Vee = 5V ± 10%
Commercial: TA = 0 to 75°C, Vee = 5V ± 5%
Symbol
tpo
Parameter
From any Input to any Output
16C1A
Test Conditions
CL =50pF
CL =50pF
Military
Min.
Commercial
Typ.
Max.
15
30
35
Min.
Typ.
15
Max.
Unit
25
ns
30
ns
Table 11.1.7 AC and DC Specifications for 20-Pin Fast, Small PAL Devices
280
Programmable Logic Design Guide
16L8A, 16R8A, 16R6A, 16R4A
Recommended Operating Conditions
Symbol
Military
Parameter
Min.
Supply Voltage
Vee
Commercial
Typ.
Max.
Min.
5.5
Typ.
Max.
5.25
4.5
5
4.75
5
Low
20
10
15
10
High
20
10
15
10
16RBA, 16R6A, 16R4A
30
16
25
16
0
-10
0
-10
0
25
Width of Clock
tw
Setup Time from Input
or Feedback to Clock
tsu
Unit
V
ns
th
Hold Time
TA
Operating Free-Air Temperature
Te
Operating Case Temperature
-55
ns
ns
75
·C
·C
125
Electrical Characteristics
Over Recommended Operating Temperature Range
Symbol
Parameter
Min.
Test Conditions
Typ.
Max.
Unit
V
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
VIC
Input Clamp Voltage
Vee=Min.,II=-1BmA
High Level OutPl,lt Voltage
IOH=-2mA
MIL
VOH
Vee=Min.
VIL=O.BV
VIH =2V
IOH=-3.2mA
COM
Low Level Output Voltage
Vee=Min.
VIL=O.BV
VIH =2V
IOL=12mA
MIL
VOL
IOL=24mA
COM
Vee = Max.
VIL=O.BV
VIH=2V
Vo =2.4V
100
,..A
Vo=O.4V
-100
,..A
mA
10ZH
Off-state Output Current
10ZL
2
-O.B
2.4
O.B
V
-1.5
V
V
2.B
0.3
II
Maximum Input Current
Vee = Max., VI = 5.5V
1
IIH
High Level Input Current
Vee = Max., VI = 2.4 V
25
IlL
Low Level Input Current
Vee = Max., VI = 0.4 V
los
Output Short-Circuit Current
Vee=5V
Icc
Supply Current
Vee = Max.
Vo=OV
-30
V
0.5
,..A
-0.02
-0.25
mA
-70
-130
mA
1BO
mA
120
Table 11.1.8 AC and DC Specifications for 20-Pin Fast Medium PAL Devices
Data Sheets
281
Switching Characteristics
Over Recommended Ranges of Temperature and Vee
Military: TA = - 55°C to + 125°C'. Vee = 5V ± 10%
Commercial: TA = 0 to 75°C; Vee = 5V ± 5%
Symbol
Parameter
Teat Condltlona U
R1, R2
Min.
Military
Commercial
Typ.
Max.
Min.
Typ.
Max.
Unit
tpD
Input or Feedback to Output
15
30
15
25
ns
tCLK
Clock to Output or Feedback
10
20
10
15
ns
tpzx
Pin 11 to Output Enable
10
25
10
20
ns
tpxz
Pin 11 to Output Disable
CL=5pF
11
25
11
20
i"ls
tpzx
Input to Output Enable
C L =50pF
10
30
10
25
ns
tpxz
Input to Output Disable
CL=5pF
13
30
13
25
fMAX
Maximum Frequency
CL=50pF
20
30
25
30
ns
ns
USee Waveforms, Test Load on pg. 24·21.
Table 11.1.8 AC and DC Specifications for 20-Pin Fast Medium PAL Devices (Cont.)
282
Programmable Logic Design Guide
16L8B, 16R8B, 16R6B, 16R4B
Recommended Operating Conditions
Symbol
Vcc
Supply Voltage
tw
Width of Clock
Commercial
Military
Parameter
Min
Typ
Max
Min
5.5
Max
5.25
4.5
5
4.75
5
I Low
12
8
10
5
I
12
8
10
5
High
V
ns
tsu
Setup Time from Input or Feedback to Clock
20
10
15
10
th
Hold Time
0
-5
0
-5
TA
Operating Free-Air Temperature
0
25
Tc
Operating Case Temperature
-55
Units
Typ
ns
ns
DC
75
DC
125
Electrical Characteristics
Over Recommended Operating Temperature Range
Symbol
Parameter
Test Conditions
VIH '
High Level Input Voltage
Vll '
Low Level Input Voltage
VIC
Input Clamp Voltage
Vcc = Min., II = - 18mA
10H= -2mA
MIL
High Level Output Voltage
Vcc=Min.
Vil =0.8V
VIH =2V
10H =/- 3.2mA
COM
Vcc=Min.
Vil =0.8V
V IH =2V
10l= 12mA
MIL
10l = 24mA
COM
VOH
VOL
Off-State Output Current
II
Maximum Input Current
IIH
High Level Input Current
Typ
Max
Units
0.8
V
-1.5
V
2
Low Level Output Voltage
10ZH
10Zl
Min
t
Vcc=Max.
V il =0.8V
V IH =2V
V
-0.8
2.4
0.5
V
Vo=2.4V
100
p.A
Vo =O.4V
-100
p.A
1
mA
25
p.A
0.3
Vcc = Max., VI = 5.5V
t
t
Vcc = Max., VI = 2.4V
III
Low Level Input Current
los
Output Short-Circuit Current"
Vcc=5V
Icc
Supply Current
Vce= Max.
V
3.4
Vcc = Max., VI = O.4V
Vo=OV
-0.04 -0.25
IExcept pins 1 & 11
-0.4
IPins 1 & 11
-30
mA
-70
-130
mA
120
180
mA
t
1/0 pin leakage is the worst case of lozx or I,x e.g. I" and 10zH'
• These are absolute voltages with respect to pin 10 on the device and include all overshoots due to system andlor tester noise. Do not attempt
to test these values without suitable equipment.
•• Only one output shorted at a time .
••• Pins 1 and 11 may be raised to 20V max.
Table 11.1.9 AC and DC Specifications for 20-Pin Ultra High-Speed, Medium
PAL Devices
Data Sheets
283
Switching Characteristics
Over Recommended Ranges of Temperature and Vcc
Military: TA = - 55°C to + 125°C', Vcc = 5V ± 10%
Commercial: TA 0 to 75°C, Vcc = 5V ± 5%
=
Sym
Parameter
Test
Conditions Min
Military
Commercial
Max
20
11
15
ns
Max
11
Min
Units
Typ
Typ
tpc
Input or Feedback to Output
tCLK
Clock to Output or Feedback
B
15
B
12
ns
tpzx
Pin 11 to Output Enable
10
20
10
15
ns
tpxz
Pin 11 to Output Disable
10
20
10
15
ns
tpzx
Input to
Output Enable
16R6B 16R4B 16LBB
11
25
11
20
ns
tpxz
Input to
Output Disable
16R6B 16R4B 16L8B
11
20
11
15
ns
fMAx
Maximum
Frequency
16R8B 16R6B 16R4B
16R6B 16R4B 16LBB
Rl =200Q
R2=390Q
30
50
40
50
MHz
Table 11.1.9 AC and DC Specifications for 20-Pin Ultra High-Speed, Medium
PAL Devices (Cant.)
284
Programmable Logic Design Guide
10H8A2, 12H6A2, 14H4A2, 16H2A2, 16C1A2,
10L8A2, 12L6A2, 14L4A2, 16L2A2
Recommended Operating Conditions
Symbol
Military
Parameter
Vee
Supply Voltage
10H
High-Level Output Current
10l
tow-Level Output Current
TA
Operaling Free-Air Temperature
Min
Typ
4.5
5
Commercial
Max
Min
Typ
5.5
4.75
5
-2.0
8
-55
125
0
25
Units
Max
5.25
V
-3.2
rnA'
8
rnA
75
'C
Max
Units
Electrical Characteristics Over Recommended Operating Temperature Range
Symbol
Parameter
Test CondHlons
VIH"
High Level Input Voltage
Vll"
Low Level Input Voltage
Vie
Input Clamp Voltage
Vee = Min., II = -18mA
VOH
High Level Output Voltage
Vee = Min.
Vil = 0.8V
VIH = 2V
VOL
Low Level Output Voltage
Vee = Min.
Vil = 0.8V
VIH = 2V
Off-State Output Currentt
Vee = Max.
Vil = 0.8V
VIH = 2V
10ZH
10Zl
II
Maximum Input Current
Min
Typ
2
V
-0.8
10H = -2mA
MIL
10H = -3.2mA
COM
2.4
Max.
0.8
V
-1.5
V
2.8
V
0.5
V
Vo = 2.4V
100
",A
Vo = O.4V
-100
",A
1
rnA
IOL
=
0.3
Vee = Max., VI = 5.5V
IIH
High Level Input Currentt
Vee = Max., VI = 2.4V
III
Low Level Input Currentt
Vee = Max., VI = 0.4V
los
Output Short-Circuit Current""
Vee = 5V, Vo = OV
lee
Supply Current
Vee = Max.
-30
25
",A
-0.02
-0.25
rnA
-70
-130
rnA
28
45
mA
t 110 pin leakage IS the worst case of lozx or ,'x, e.g. tiL and IOZH'
• These are absolute voltages with respect to the ground pin on the device and includes alt overshoots due to system andlor tester noise. 00 not attempt to test
these values without suitable equipment.
•• Only one output shorted at a time.
••• Pins 1 and 11 may be raised to 20V max.
Table 11.1.10 AC and DC Specifications for 20-Pin Fast, Half-Power, Small
PAL Devices
Data Sheets
285
Switching Characteristics
Over Recommended Ranges of Temperature and Vee
Military: TA = - 55°C to + 125°C·, Vee = 5V ± 10%
Commercial: TA = 0 to 75°C, Vcc = 5V ± 5%
Symbol
Parameter
From any Input to any Output
tpD
16C1A2
Test Conditions
CL =50pF
CL =50pF
Military
Min.
Commercial
Typ.
Max.
25
45
45
Min.
Typ.
25
Max.
Unit
35
ns
40
ns
Table 11.1.10 AC and DC Specifications for 20-Pin Fast, Half-Power, Small
PAL Devices (Cant.)
286
Programmable Logic Design Guide
16L8A2, 16R8A2, 16R6A2, 16R4A2
Recommended Operating Conditions
Military
Parameter
Symbol
Min
Vcc
tw
Supply Voltage
Width of Clock
Commercial
Typ
Max
Min
5.5
Units
Typ
Max
5.25
4.5
5
4.75
5
I
Low
25
10
25
10
I
High
25
10
25
10
V
ns
tsu
Setup Time from Input or Feedback to Clock
50
25
35
25
ns
th
Hold Time
0
-15
0
-15
ns
TA
Operating Free-Air Temperature
0
25
Tc
Operating Case Temperature
-55
125
75
°C
°C
Electrical Characteristics
Over Recommended Operating Temperature Range
Symbol
Parameter
Test Conditions
V,H •
High Level Input Voltage
V,l•
Low Level Input Voltage
V'c
Input Clamp Voltage
Vcc=Min., 1, = -18mA
10H= -2mA
High Level Output Voltage
Vcc=Min.
V,l =0.8V
V ,H =2V
Vcc=Min.
V,l =0.8V
V ,H =2V
10l = 12mA MIL
Vcc= Max.
V,l =0.8V
V ,H =2V
VOH
VOL
Off-State Output Current
10Zl
Typ
Max
2
Low Level Output Voltage
10ZH
Min
t
I,
Maximum Input Current
I'H
High Level Input Current
I'l
Low Level Input Current
los
Output Short-Circuit Current·· Vcc =5V,
Icc
Supply Current
V
-0.8
V
-1.5
V
2.4
3.4
V
10H= -3.2mA COM
0.3
0.5
V
Vo=2.4V
100
pA
Vo=0.4V
-100
pA
1
mA
10l = 24mA COM
25
V cc = Max., V, = 2.4V
-0.02 -0.25
Vcc = Max., V, = 0.4V
Vcc= Max.
0.8
MIL
Vcc=Max., V, =5.5V
t
t
Units
Vo=OV
-30
-70
70
pA
mA
-130
mA
90
mA
t
1/0 pin leakage is the worst case of lozx or I,x e.g. I" and I02H .
• These are absolute wltages with respect to the ground pin on the device and Includes all overshoots due to system and/or tester noise. Do
not attempt to test these values without suitable equipment.
•• ,Only one output shorted at a time.
Table 11.1.11
AC and DC Specifications for 20-Pin Fast, Half Power Medium
PAL Devices
Data Sheets
287
Programmable Array Logic PAL Low Power PAL Series 20A2
Symbol
Parameter
Test Conditions
Mllltar
Commercial
Typ
Max
25
15
Min
Unit
Typ
Max
50
25
35
ns
25
15
25
ns
15
25
15
25
ns
CL =5pF
15
25
15
25
ns
Min
tpo
Input or Feedback to Output
tCLK
Clock to Output or Feedback
tpzx
Pin 11 to Output Enable
tpxz
Pin 11 to Output Disable
tpzx
Input to Output Enable
C L =50pF
25
45
25
35
ns
tpxz
Input to Output Disable
CL =5pF
25
45
25
35
ns
fMAX
Maximum Frequency
Thble 11.1.11
C L =50pF
14
25
16
25
MHz
AC and DC Spc::cifications for 20-Pin Fast, Half Power Medium PAL
Devices (Cont.)
288
Programmable Logic Design Guide
16L8B2, 16R8B2, 16R6B2, 16R4B2
Recommended Operating Conditions
Symbol
Min
Vee
Commercial
Military
Parameter
lYP
Max
Min
5.5
Max
5.25
4.5
5
4.75
5
Low
15
10
10
B
High
20
10
15
B
25
10
20
10
0
-5
0
-5
0
25
Supply Voltage
tw
Width of Clock
tsu
Setup Time from Input 16RBB2, 16R6B2,16R4B2
or Feedback to Clock
th
Hold Time
TA
Operating Free-Air Temperature
Te
Operating Case Temperature
/
-55
A 12S:',
.,..,.
,,<'
.~.-"'r.~2·~
V
ns
ns
ns
75
°C
"'.
.'~
,
Units
lYP
~
°C
.,
~
:"
Electrical Characteristics
Over Recommended Operating Temperature Range
Symbol
,
Parameter
..
"
'
Teat Conditions
VIH '
High Level Input Voltage
, ,
V Il '
Low Level Input Voltage
.,
VIC
Input Clamp Voltage
V~ .. Mi!1., 11= -1BmA
10H= -2mA
MIL
High Level Output Voltage
'VccFMin.
Vil ;cO.BV
V IH =2V
10H= -3.2mA
COM
Vee = Min.
V'l=O.BV
V IH =2V
IOl=12mA
MIL
10l = 24mA
COM
VOH
VOL
"
.
Low Level Output Voltage
,
Vee = Max.
Vil =O.BV
VIH =2V
Units
O.B
V
-1.5
V
V
3.4
0.5
V
Vo=2.4V
100
pA
Vo=0.4V
-100
pA
1
mA
0.3
II
Maximum Input Current
Vee = Max., VI =5.5V
IIH
High Level Input Current t
Vee = Max., V, = 2.4V
III
Low Level Input Current t
Vee = Max., VI = 0.4V
los
Output Short-Circuit Current"
Vee =5V,
Vee = Max.
Max
V
-O.B
2.4
Off-State Output Current t
Supply Currenttt
Typ
2
10ZH
lozl
Icc
Min
-30
Vo=OV
16LBB2
16R4B2,16R6B2,16R8B2
25
p.A
-0.01
-0.25
mA
-70
70
-130
mA
90
mA
70
100
mA
t 110 pin
leakage is the worst case of lozx or I,x e.g. III and lozH.
, These are absolute voltages with respect to the ground pin on the device and includes all overshoots due to system andlor tester noise. Do
not attempt to test these values without suitable equipment.
" Only one output shorted at a time.
Table 11,1.12 AC and DC Specifications for 20-Pin Ultra High-Speed, Half Power,
Medium PAL Devices
Data Sheets
289
Switching Characteristics
Military: TA = - 55°C to + 125°C, Vee = 5V ± 10%
Commercial: TA = 0 to 75°C, Vee = 5V ± 5%
Symbol
Parameter
tpD
Input or Feedback to Output
Test Conditions
Military
Min
16R6B2,16R4B2,
16L8B2
Commercial
Typ
Max
15
30
Min
Unit
Typ
Max
15
25
ns
tCLK
Clock to Output or Feedback
8
20
8
15
ns
tpzx
Pin 11 to Output Enable
10
25
10
20
ns
tpxz
Pin 11 to Output Disable
10
25
10
20
ns
tpzx
Input to
Output Enable
16R6B2,16R4B2,
16L8B2
11
30
11
25
ns
tpxz
Input to
Output Disable
16R6B2, 16R4B2,
16L8B2
11
30
11
25
ns
fMAX
Maximum
Frequency
16R8B2, 16R6B2,
16R4B2
Table 11.1.12
R, = 2001}
R2 =3901}
20
40
28.5
40
MHz
AC and DC Specifications for 20-Pin Ultra High-Speed, Half Power,
Medium PAL Devices (Cant.)
290
Programmable Logic Design Guide
12L10, 14L8, 16L6, 18L4,20L2,20C1
20L10,20X10,20X8,20X4
Operating Conditions
Symbol
Max
Min
Typ
Max
5
5.5
4.75
5
5.25
V
75
°C
Supply Voltage
4.5
TA
-55
Tc
Operating Case Temperature
0
125
°C
Over Operating Conditions
Parameter
Test Conditions
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
VIC
Input Clamp Voltage
Vcc = Min.
II =-18mA
Min
Typ
Max
0.8
-1.5
IlL
Low Level Input Current t
Vcc = Max.
VI = Oo4V
-0.25
High Level Input Current t
Vee = Max.
VI = 204V
25
II
Maximum Input Current
Vec = Max.
V I = 5.5V
1
Low Level Output Voltage
Vec= Min.
VIL = 0.8V
IIH= 2V
VOH
High Level Output Voltage
Vee = Min.
VIL = 0.8V
V IH =2V
Off-state Output Current t
Vee = Max.
VIL = 0.8V
VIH=2V
los
Output Short-Circuit Current"
Vee = 5.0V
Icc
Supply Current
Vcc = Max.
10ZL
10ZH
Unit
2
IIH
VOL
Unit
Typ
Operating Free-air Temperature
Symbol
Commercial
Min
Vcc
Electrical Characteristics
**
Military
Parameter
10L = 12mA'
MIL
10L = 24mA'
COM
10H =-2mA
MIL
10H =-3.2mA
COM
0.5
I
204
V
-100
Vo= Oo4V
V0204V
Vo=OV
V
-30
I1A
100
I1A
-130
mA
20X4, 20X8, 20X10
120
180
20L 10
90
165
12L10, 14L8, 16L6
18L4, 20L2, 20C1
60
100
I/O pin leakage IS the worst case of lozx or Ilx' e.g., III and IOZH'
IOL ~ B mA lor 12L10, 14LB. 16L6. lBL4, 20L2 and 20Cl.
Only one output shorted at a time.
Table 11.1.13 AC and DC Specifications for 24-Pin, Standard PAL Devices
mA
Data Sheets
291
Switching Characteristics Over Operating Conditions
Symbol
Parameter
Test Conditions
R1,R2
Commercial
Military
Min
Typ
Max
Min
Typ
Max
Unit
tpo
Input or Feedback to Output
20L 10, 20Xl0
20X8,20X4
Cl = 50pF
35
60
35
50
ns
tpo
Input or Feedback to Output
12L10, 14L8, 16L6
18L4, 20L2, 20Cl
Cl = 50pF
25
45
25
40
ns
telK
Clock to Output or Feedback
Cl
20
40
20
30
ns
tpzx
Pin 13 to Output Enable
Cl
tpxz
Pin 13 to Output Disable
Cl
tpzx
Input to Output Enable
Cl
tpxz
Input to Output Disable
Cl
45
20
35
ns
45
20
35
ns
35
55
35
45
ns
35
55
35
45
ns
35
20
ns
25
10
ns
50
38
ns
40
High
30
10
60
38
0
-15
Width of Clock
tsu
Set- Up Time from Input or Feedback
th
20
20
Low
tw
fMAX
= 50pF
= 50pF
= 5pF
= 50pF
= 5pF
Hold Time
Maximum Frequency
0
10.0
20
-15
12.5
ns
MHz
Table 11.1.13 AC and DC Specifications for 24-Pin, Standard PAL Devices (Cont.)
292
Programmable Logic Design Guide
20L8A,20R8A,20R6A,20R4A
Operating Conditions
Symbol
Military
Parameter
Max
Min
Typ
Max
5
5.5
4.75
5
5.25
V
75
·C
Vee
Supply Voltage
4.5
Operating Free·Air Temperature
-55
Te
Operating Case Temperature
Symbol
Parameter
Units
Typ
TA
Electrical Characteristics
Commercial
Min
0
·C
125
Over Operating Conditions
Units
0.8
V
Vee = Min., 11= -18mA
-1.5
r-y-
Low Level Input Current t
Vee = Max., VI = 0.4 V
-{).25
mA
High Level Input Current t
Vee = Max., VI = 2.4 V
25
~
II
Maximum Input Current
Vee = Max., VI = 5.5 V
1
mA
MIL
Low Level Output Voltabe
Vee = Min.
VIL=0.8V
VIH=2V
IOL=12mA
VOL
0.5
V
IOL=24mA
COM
Vee = Min.
VIL=0.8V
VIH=2V
IOH=-2mA
MIL
IOH=-3.2mA
COM
Vee = Max.
VIL=0.8V
VIH=2V
Vo=0.4V
-100
Vo=2.4V
100
~
-130
mA
210
mA
VIH
High Level Input Voltage
VIC
Input Clamp Voltage
IlL
IIH
VOH
IOZL
r--
High Level Output Voltage
Off·State Output Currentt
lozH
Test Conditions
Typ
Max
VIL
Low Level Input Voltage
Min
2
los
Output Short·Clrcuit Current··
Vee=5V, Vo=OV
Icc
Supply Current
Vee = Max.
V
2.4
V
-30
160
1/0 pin leakage is the worst cast of fazx or ''x. e.g. IlL and 'OZH'
Pins 1 and 13 may be raised to 20V max.
•• Only one output shorted at a time.
These are absolute voltages with ~espect to the ground pin on the device and Includes all overshoots due to systam and/or tester noise.
Do not attempt to test these values without suitable equipment.
Table 11.1.14 AC and DC Specifications for 24-Pin, Fast PAL Devices
~
Data Sheets
Switching Characteristics
Symbol
293
Over Operating Conditions
Parameter
Test Conditions
Military
Min
Commercial
Typ
Max
Min
Units
Typ
Max
25
ns
tpD
Input or Feedback to Output
20L6A,20R6A
20R4A
Cl=50pF
16
30
16
tClK
Clock to Output or Feedback
Cl=50pF
12
20
12
15
ns
tpzx
Pin 13 to Output Enable
Cl =50pF
10
25
10
20
ns
tpxz
Pin 13 to Output Disable
Cl=5pF
11
25
11
20
ns
tpzx
Input to Output Enable
Cl=50pF
10
30
10
25
ns
tpxz
Input to Output Disable
Cl=5pF
13
30
13
25
ns
tw
Width of Clock
I Low
I High
20R6A, 20R6A,
20R4A
20
7
15
7
ns
20
7
15
7
ns
ns
tsu
Setup Time from Input or Feedback
30
16
25
16
th
Hold Time
0
-10
0
-10
ns
fMAX
Maximum Frequency
20
40
26.5
40
MHz
Table 11.1.14 AC and DC Specifications for 24-Pin, Fast PAL Devices (Cant.)
294
Programmable Logic Design Guide
11.2 PROGRAMMINGIVERIFYING PROCEDURE - 20 PIN PAL DEVICES·
As long as Pin 1 is at HH, Pin 11 is at ground, and Pin 12 is either at HH or Z (as defined
in Table 11.2.1) - Pins 16,17, 18, and 19 are outputs. The other pin functions are: 10
(Pin 2) through 17 (Pin 9) plus Pin 12 address the proper row; AO (Pin 15), Al (Pin 14),
and A2 (Pin 13) address the proper product lines.
When Pin 11 is at HH, Pin 1 is at ground, and Pin 19 is either at HH or Z - Pins 12, 13,
14, and 15 are outputs. The other pin functions are: 10 (Pin 2) through 17 (Pin 9) plus
Pin 19 address the proper row; AO (now Pin 18), Al (now Pin 17), and A2 (now Pin 16)
address the proper product lines.
PRODUCTS 0 TH RU 31
Figure 11.2.1
PRODUCTS 32 THRU 63
Pin Assignment for Programming
Pre-Verification
Step 1.1 Raise Vee to 5Y.
Step 1.2 Raise Output Disable pin, 00, to
VIHH'
Step 1.3 Select an input line by specifying Inputs and LlR as shown in Table 11.2.2.
Step 1.4 Select a product line by specifying AO, Al and A2 one-of-eight select as shown
in Thble 11.2.2
Step 1.5 Pulse the CLOCK pin and verify (with CLOCK at Vrd that the output pin, 0, is
in the state corresponding to an u.nblown fuse.
- For verified unblown condition, continue procedure from Step 1.3
through Step 1.5.
- For verified blown condit~on, stop procedure and reject part.
Note: For programming purposes many PAL pins have double functions.
Data Sheets
Input
Line
Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Pin Identification
17
16
15
14
13
12
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
L
H
L
H
L HH
H HH
L HH
H HH
L
H
L
H
HH
HH
HH
HH
HH
HH
HH
HH
L
H
L
H
HH
HH
HH
HH
HH
i-IH
HH
HH
HH
HH
HH
HH
L
H
L
H
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
L
H
L
H
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
I-JH
HH
HH
HH
HH
HH
HH
HH
11
10 L/R
L
Z
H Z
L HH
HH
HH
HH
HH H
L HH
H HH
L HH
H HH
HH HH
HH HH
HH HH
HH HH
HH HH
HH HH
HH HH
HH HH
HH HH
HH HH
HH HH
HH HH
HH HH
HH HH
HH HH
HH HH
HH HH
HH HH
HH HH
HH HH
HH HH
HH HH
HH HH
HH HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
z
Z
HH
HH
Product
Line
Number
0,32
1,33
2,34
3,35
4,36
5,37
6,38
7,39
8,40
9,41
10,42
11,43
12,44
13,45
14,46
15,47
16,48
17,49
18,50
19,51
20,52
21,53
22,54
23,55
24,56
25,57
26,58
27,59
28,60
29,61
30,62
31,63
295
Pin Identification
03
O2
01
00
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
A2
Z
Z
Z
Z
HH
HH
HH
HH
Z
Z
Z
Z
HH
HH
HH
HH
Z
Z
Z
Z
HH
HH
HH
HH
Z
Z
Z
Z
HH
HH
HH
HH
A1
Z
Z
Ao
Z
HH
HH
HH
HH
Z
Z
HH
HH
HH
HH
Z
Z
HH
HH
HH
HH
Z
Z
HH
HH
HH
HH
Z
Z
HH
HH
HH
HH
Z
Z
HH
HH
HH
HH
Z
Z
HH
HH
HH
HH
Z
Z
HH
HH
HH
HH
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Table 11.2.2 Input Line Select
Thble 11.2.1 Input Line Select
Programming Algorithm
Step 2.1 Raise Output Disable pin, aD to
VIHH'
Step 2.2 Programming pass. For all fuses to be blown:
Step 2.2.1 Lower CLOCK pin to ground.
Step 2.2.2 Select an input line by specifying Inputs and LlR as shown in
Table 11.2.2.
Step 2.2.3 Select a product line by specifying AO, Al and A2 one-of-eight
select as shown in Thble 11.2.2.
Step 2.2.4 Raise Vee to IHH.
296
Programmable Logic Design Guide
Step 2.2.5 Program the fuse by pulsing the output pins of the selected
product group one at a time to VIHH (as shown in the Programming Waveforms).
Step 2.2.6 Lower Vee to 5V.
Step 2.2.7 Repeat this procedure from Step 2.2.2 until pattern is complete.
Step 2.3 First verification pass. For all fuse locations:
Step 2.3.1 Select an input line by specifying Inputs and LIR as shown in
Tables 11.2.1 and 11.2.2.
Step 2.3.2 Select a product line by specifying AO, AI, and A2 one-of-eight
select as shown in Table 11.2.2.
Step 2.3.3 Pulse the CLOCK pin and verify (with CLOCK at VId that the output pin, 0, is in the correct state.
- For verified output state, continue procedure.
- For overblow condition, stop procedure and reject part.
- For underblow condition, reexecute Steps 2.2.4 through
2.2.6 and 2.2.3. If successful, continue procedure. After
three attempts to blow fuse without success, reject part but
continue procedure.
Step 2.3.4 Repeat this procedure from Step 2.3.1 until the entire array is
exercised.
Step 2.4 High Voltage Verify. For all fuse locations:
Step 2.4.1 Raise Vee to 5.5V.
Step 2.4.2 Select an input line by specifying Inputs and LlR as shown in
Thbles 11.2.1 or 11.2.2.
Step 2.4.3 Select a product line by specifying AO, AI, and A2 one-of-eight
select as shown in Thble 11.2.2.
Step 2.4.4 Pulse the CLOCK pin and verify (with CLOCK a~ VIL) that the output pin, 0, is in the correct state.
- For verified output state, continue procedure.
- For invalid output state, stop procedure and reject part.
Step 2.4.5 Repeat this procedure from Step 2.4.1 until the entire array is
exercised.
Step 2.5 Low Voltage Verify. For all fuse locations:
Step 2.5.1 ):..ower Vee to 4.5V.
Step 2.5.2 Select an input line by specifying inputs and LlR as shown in
l1tbles 11.2.1 or 11.2.2.
Step 2.5.3 Select a product line by specifying AO, AI, and A2 one-of-eight
select as shown in Thble 11.2.2.
"NSC programming spec. Rev. 1. The old programming spec. is still valid.
Data Sheets
297
Step 2.5.4 Pulse the CLOCK pin and verify (with CLOCK at Vrd that the output pin, 0, is in the correct state.
- For verified output state, continue procedure.
- For invalid output state, continue procedure and reject part.
Programming the Security Fuses
Step 3.1 Verify per Step 2.4 and Step 2.5.
Step 3.2 Raise Vee to 6v.
Step 3.3 Program the first fuse by pulsing Pin 1 to Vp. (From 1 to 5 pulses is
acceptable. )
Step 3.4 Program the second fuse by pulsing Pin 11 to Vp. (1 to 5 pulses is acceptable.)
Step 3.5 Verify per Step 2.4 and Step 2.5:
- A device is "secure" if either half fails to verify.
Voltage Legend
L = Low level input voltage, VrL
H = High level input voltage, VIH
HH = High level program voltage, VIHH
Z = 10 kO to 5V
Note: For programming purposes many PAL device pins have double functions.
298
Programmable Logic Design Guide
11.3 PROGRAMMING/VERIFYING PROCEDURE -
24 PIN PAL DEVICES·
As long as Pin 1 is at HH, Pin 13 is at ground, and Pin 14 is either at HH or Z (as defined
in Table 11.3.1) - Pins 19, 20, 21, and 22 are outputs. The other pin functions are: 10
(Pin 2) through 19 (Pin 11) plus Pin 14 address the proper row; AD (Pin 15), Al (Pin 16),
and A2 (Pin 17) address the proper product lines.
As long as Pin 13 is at HH, Pin 1 is at ground, and Pin 23 is either at HH or Z (as
defined in Table 11.3.1) - Pins 15, 16, 17 and 18 are outputs. The other pin functions
are: 10 (Pin 2) through 19 (Pin 11) plus Pin 23 address the proper row; AD (Pin 22), Al
(Pin 21), and A2 (Pin 20) address the proper product lines.
PRODUCTS 0 THRU 39
OD
24
I,
I,
I,
I,
I,
I,
I,
I,
I,
23
10
I,
GND
PRODUCTS 40 THRU T9
19
Vee
0,
0,
0,
0,
0,
18
NC
17
16
A,
A,
15
Ao
11
14
UR
12
13
CLOCK
22
21
20
CLOCK
24
Vee
I,
23
LIR
I,
I,
I,
22
20
A,
A,
A,
I.
I,
I,
I,
I,
I,
19
NC
18
GND
10
15
11
14
0,
0,
0,
0,
0,
12
13
OD
17
16
Top View
Top View
Figure 11.3.1
21
Pin Assignment for Programming
Pre-Verification
Step 1.1 Raise Vee to 5Y.
Step 1.2 Raise Output Disable pin, aD, to
VIHH.
Step 1.3 Select an input line by specifying Inputs and LlR as shown in Table 11.3.1.
Step 1.4 Select a product line by specifying AD, Al and A2 one-of-eight select as shown
in Table 11.3.2.
Step 1.5 Pulse the CLOCK pin and verify (with CLOCK at Vld that the output pin, OH,
is in the state corresponding to an unblown fuse.
- For verified unblown condition, continue procedure from Step 1.3
through Step 1.5.
- For verified blown condition, stop procedure and reject part.
Programming Algorithm
Step 2.1 Raise Output Disable pin, aD, to
VIHH'
Step 2.2 Programming pass. For all fuses to be blown:
Step 2.2.1 Lower CLOCK pin to ground.
Step 2.2.2 Select an input line by specifying inputs and LlR as shown in
Thble 11.3.1.
Data Sheets
Input
Line
Number
o
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Input
Line
Number
Pin Identification
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
L
H
L
H
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
L
H
L
H
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
L
H
L
H
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
L
H
L
H
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
Thble 11.3.1
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
L
H
L
H
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
L
H
L
H
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
L
H
L
H
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
L
H
L
H
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
L
H
L
H
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
L
H
L
H
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
Input Line Select
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
Z
Z
HH
HH
0,40
1,41
2,42
3,43
4,44
5,45
6,46
7, 47
8, 48
9,49
10, 50
11,51
12,52
13, 53
14,54
15,55
16,56
17,57
18,58
19,59
20, 60
21,61
22, 62
23, 63
24, 64
25, 65
26, 66
27, 67
28, 68
29, 69
30,70
31,71
32, 72
33, 73
34,74
35, 75
36,76
37, 77
38, 78
39, 79
299
Pin Identification
0 4 0 3 O2 0 1 0 0 A,.
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
HH
HH
HH
HH
HH
HH
HH
HH
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
HH
HH
HH
HH
HH
HH
HH
HH
Z
Z
Z
Z
Z
Z
Z
Z
Thble 11.3.2
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
HH
HH
HH
HH
HH
HH
HH
HH
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
HH
HH
HH
HH
HH
HH
HH
HH
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
HH
HH
HH
HH
HH
HH
HH
HH
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
HH
HH
HH
HH
Z
Z
Z
Z
HH
HH
HH
HH
Z
Z
Z
Z
HH
HH
HH
HH
Z
Z
Z
Z
HH
HH
HH
HH
Z
Z
Z
Z
HH
HH
HH
HH
A1
Ao
Z,
Z
Z
HH
HH
Z
HH HH
Z
Z
Z
HH
HH
Z
HH HH
Z
Z
Z
HH
HH
Z
HH HH
Z
Z
Z
HH
Z
HH
HH HH
Z
Z
HH
Z
HH
Z
HH HH
Z
Z
Z
HH
HH
Z
HH HH
Z
Z
HH
Z
HH
Z
HH HH
Z
Z
Z
HH
HH
Z
HH HH
Z
Z
Z HHZ
HH
Z
HH HH
Z
HH
Z
HH
HH
Z
HH HH
Product Line Select
300
Programmable Logic Design Guide
Step 2.2.3 Select an input line by specifying inputs and L/R as shown in
Table 11.2.2.
Step 2.2.4 Select a product line by specifying AO, AI, and A2 one-of-eight
select as shown in Table 11.2.2
Step 2.2.5 Raise Vee to VIHH.
Step 2.2.6 Program the fuse by pulsing the output pins of the selected
product group one at a time to VIHH (as shown in the Programming Waveforms).
Step 2.2.7 Lower Vee to 5V.
Step 2.2.8 Repeat this procedure from Step 2.2.2 until pattern is complete.
Step 2.3 First verification pass. For all fuse locations:
Step 2.3.1 Select an input line by specifying Inputs and L/R as shown in
Tables 11.2.1 and 11.2.2.
Step 2.3.2 Select a product line by specifying AO, AI, and A2 one-of-eight
select as shown in Table 11.2.2.
Step 2.3.3 Pulse the CLOCK pin and verify (with CLOCK at VII) that the output pin, 0, is in the correct state.
- For verified output state, continue procedure.
- For overblow condition, stop procedure and reject part.
- For underblow condition, reexecute Steps 2.2.4 through
2.2.6 and 2.2.3. If successful, continue procedure, after
three attempts to blow fuse without success, reject part but
continue procedure.
Step 2.3.4 Repeat this procedure from Step 2.3.1 until the entire array is
exercised.
Step 2.4 High Voltage Verify. For all fuse locations:
Step 2.4.1 Raise Vee to 5.5Y.
Step 2.4.2 Select an input line by specifying Inputs and L/R as shown in
.
Table 11.3.1.
Step 2.4.3 Select a product line by specifying AO, AI, and A2 one-of-eight
select as shown in Table 11.3.2.
Step 2.4.4 Pulse the CLOCK pin and verify (with CLOCK at Vrd that the output pin, 0, is in the correct state.
- For verified output state, continue the procedure.
- For invalid output state, stop procedure and reject part.
Step 2.4.5 Repeat this procedure from step 2.4.1 until the entire array is
exercised.
Step 2.5 Low Voltage Verify. For all fuse locations:
Step 2.5.1 Lower Vee to 4.5Y.
Step 2.5.2 Select an input line by specifying inputs and L/R as shown in
Table 11. 3.1.
Step 2.5.3 Select a product line by specifying AO, AI, and A2 one-of-eight as
shown in Table 11.3.2.
Data Sheets
301
Step 2.5.4 Pulse the CLOCK pin and verify (with CLOCK at Vrd that the output pin, 0, is in the correct state.
- For verified output state, continue procedure.
- For invalid output state, continue procedure and reject part.
Programming the Security Fuses
Step 3.1 Verify per Step 2.4 and Step 2.5
Step 3.2 Raise Vee to 6v.
Step 3.3 For PAL 24 and PAL 24A:
- Program the first fuse by pulsing Pin 1 to Vp
(From 1 to 5 pulses is acceptable.)
- Program the second fuse by pulsing Pin 13 to Vp
(1 to 5 pulses is acceptable.)
Step 3.4 Verify per Step 2.4 and Step 2.5:
- A device is "secure" if either half fails to verify.
Symbol
VIHH
IIHH
Parameter
Program Level Input Voltage
Program Level Input Current
Min
Typ
Max
Units
11.5
11.75
12
V
Output Program Pulse
50
00, LlR
50
All Other Inputs
10
mA
ICCH
Program Supply Gurrent
900
mA
tvccp
Pulse Width of VCC@VIHH
60
,..s
tp
Program Pulse Width
10
50
,..s
to
Delay Time
100
ns
t02
Delay Time after UR Pin
10
,..s
20
20
Veep Duty Cycle
18
Vp
Security Fuse Programming Voltage
Ip
Security Fuse Programming Supply Current
Security Fuse Programming Pulse Width
tpp
tRP
Veepp
10
18.5
40
Security Fuse Programming Duty Cycle
V
400
mA
70
,..5
50
%
Rise Time of Output Programming and Address Pulses
1
1.5
10
Rise Time of Security Fuse Programming Pulses
1
1.5
10
Vee Value During Security Fuse Programming
5.75
6
6.25
Vee Value for First Verify
4.75
5.25
Vee Value for High Vee Verify
5.4
4.4
5
5.5
Vee Value for Low Vee Verify
Table 11.3.3
4.5
%
19
5.6
4.6
Programming Parameters
*NSC programming spec. Rev. 1. The old programming spec. is still valid.
VI,..s
V
302
Programmable Logic Design Guide
Array Programming Waveforms
OD
VIHH~
V1L
CLOCK
r
tD
V1L - - - - ,
1------------
O~
I
tD
V1HH ---++-------"\
V 1H
---++
V1L----f
V1HH
A, L/R
---+-r--------..
z---.,
tD2
-tvccp
V1HH -----+r--...;.;~-.........
Vcc
REPEAT UNTIL
PATTERN IS
PROGRAMMED
5V-----f
V1HH ------t-tr---:~__;
o
VoH - - - - - " "
VOL-----J
TL/L/5598-7
Note:
Vee (Low Voltage Verlfy)=4.5V
Vee (High Voltage Verify) = 5.5V
Vee (First Verlfy)=5V
A Delay (to21 must always precede the Positive
Clock Transition. (e.g. see step 1.2.3.3 for underblow condition)
Figure 11.3.2
Programming Waveforms
-=
Data Sheets
Verification Waveforms
V1HH
j-~
OD
V1L
Vcc
V1HH
V1H
V1L
V1HH
A,UR
Z
D2
l,t
0
VOH
VOL
CLOCK
v'IH
V1L
-
VERIFY
/
REPEAT
UNTIL
ARRAY IS
VERIFIED
1fX=
H=tD
rtD
n
Security Fuse Programming waveforms
Vccp
Vcc
Vp
~
J
0
tD -
~pp-I
PIN 1
-
I--tD
Z
TppVp
tD-1
PIN 11
Z
Figure 11.3.2
Programming Waveforms (Cont.)
Refer to Chapter 5 for a List of PAL Programmer Vendors
303
304
11.4
Programmable Logic Design Guide
LOGIC PROM DATA SHEETS
Description
This generic Schottky PROM family by National provides the industry with one of the
widest selections in sizes and organizations. Four-bit wide PROMs are provided with
256 to 4096 words in pin compatible 16 and 18-pin dual-in-line packages. The 8-bit
wide devices range from 32 to 4096 words in a variety of packages. Being 'generic', all
PROMs share a common programming algorithm.
National's new Programmable Read-Only Memories (PROMs) feature titaniumtungsten (Ti:W) fuse links designed to program efficiently with only 10.5 Volts applied.
The high peformance and reliability of these PROMs are the result of fabrication by a
Schottky bipolar process, of which the titanium-tungsten metallization is an integral
part, and an on-chip programming circuit is used.
A major advantage of the titanium-tungsten fuse technology is the low programming voltage of the fuse links. At 10.5 Volts, this voltage level virtually eliminates the
need for guard-ring devices and wide spacings required for other fuse technologies.
Care is taken, however, to minimize voltage drops across the die and to reduce parasitics. The device is designed to insure that worst-case fuse operating current is low
enough for reliable long-term operation. The Darlington programming circuit is liberally designed to insure adequate power density for blowing fuse links. The complete
circuit design is optimized to provide high performance over the entire operating
ranges of Vee and temperature.
Testability
The Schottky PROM die includes extra rows and columns of fusible links for testing the
programmability of each chip. These test fuses are placed at the worst-case chip locations to provide the highest possible confidence in the programming tests in the final
product. A ROM pattern is also permanently fixed in the additional circuitry and coded
to provide a parity check of input address levels. These and other test circuits are used
to test for correct operation of the row and column-select circuits and functionality of
input and enable gates. All test circuits are available at both wafer and assembled device
levels to allow 100% functional and parametric testing at every stage of the test flow.
Reliability
As with all National products, the Ti:W PROMs are subjected to an ongoing reliability
evaluation by the Reliability Assurance Department. These evaluations employ accelerated life tests, including dynamic high-temperature operating life, temperaturehumidity life, temperature cycling, and thermal shock. To date, nearly 7.4 million
Schottky Ti:W PROM device hours have been logged. DIP (N-package) and cerdip
a-package). Device performance in all package configurations is excellent.
Data Sheets
Supply Voltage (Note 2)
Input Voltage (Note 2)
Output Voltage (Note 2)
Storage Temperature
Lead Temperature (10 seconds)
Table 11.4.1
-0.5 to
- 1.2 to
- 0.5 to
- 65 to
305
+7.0V
+ 5.5V
+ 5.5V
+ 150C
300C
Absolute Maximum Ratings
·Device input waveform characteristics are;
Repetition rate = 1MHz
Source impedance = son
Rise and Fall times = 2.5ns max.
(1.0 to 2.0 volt levels)
Vee
R1
·TAA Is measured with stable enable inputs.
·TEA and TER are measured from the 1.5
volt level on Inputs and outputs with all
address and enable inputs stable at
applicable levels .
OUTPUT 0 - -......- -.....- - 0 TEST
POINT
R2
• For IOL = 16mA, R1 = 300n and R2 = 600n
for IOL = 12mA, R1 = 400n and R2 = 800n.
·"C" Includes scope and jig capacitance.
GND
Figure 11.4.1
Standard Test Load
7Jllli;J
ADDRESS
3.0V
OV ~
VALID
r-
~-~-A-~--------------OUTPUT
_
-l~zxl-- r..I.U I
~ ~TEA~
ENABLE 3.::
Figure 11.4.2
VALID
t-TXZ:::::;j
c::TER~
_-_-_-_--J'( --------y~ -_-_-_~_-_-_
Switching Time Waveforms Non-Registered PROMs
306
Programmable Logic Design Guide
CP
- - - - - - - '.5V
1-
IpHdCP)
-I
1-' 'PLHICP).-'1'
-G
1- 'PHzlG) -I
X~----';;;;.,;++---~~-'-_---.L.JI..JI
1
1-
,~~~~~---------DV
1
--
»))
1-'mIG) -
D.5V
lo.5V
f
---------------'
)-II-_ 1
1s" NIT
-r,.(INIT)-
.NIT\ \ \
--
fr/
I~
\:
IpZHIG;i.,--
m=
'PLZIG)-I
3V
- - - - •• 5V
'------DV
-~-------------------------------------------------------------------------- ~.:V
T/ T -_ ----------------------------
--
---------------------------DV
INPUTS
OUTPUTS
MUST BE
STEADY
\\\\
flU
vn
VOL
Figure 11.4.3 Switching Waveforms, Registered PROM
WAVEFORM
~.~5V
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
STEADY
WILL BE
CHANGING
FROM H TO L
WILL BE
CHANGING
FROM L TO H
WAVEFORM
~
IDffi
INPUTS
OUTPUTS
DON'T CARE:
ANY CHANGE
PERMITTED
CHANGING:
STATE
UNKNOWN
DOES NOT
APPLY
CENTER LINE
IS HIGH
IMPEDANCE
"OFF" STATE
Figure 11.4.4 Key to Timing Diagram
Data Sheets
11.5
307
DM54/74S188, DM54/74S288 (32 x 8) 256-BIT TTL PROMs
General Description
These Schottky memories are organized in the popular 32 words by 8 bits configuration. A memory enable input is provided to control the output states. When the device
is enabled, the outputs represent the contents of the selected word. When disabled, the
8 outputs go to the OFF or high impedance state. The memories are available in both
open-collector and TRI-STATE® versions.
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location by following the programming instructions.
Features
• Advanced titanium-tungsten (Ti:W) fuses.
• Schottky-clamped for high speed.
Address access-22 ns typo
Enable access-I5 ns typo
Enable recovery-I5 ns typo
• PNP inputs for reduced input loading.
• All DC and AC parameters guaranteed over temperature.
• Low voltage TRI-SAFETM programming.
Commercial
Military
X
X
DM74S188
DM74S288
DM54S188
DM54S288
TRI-STATE
Package
X
N.J
N,J
X
J
J
X
X
X
Table 11.5.1
OpenCollector
X
(32 x 8) 256-Bit TTL PROM Options
INPUT
BUFFER ,--_ _ _ _ _ _ _ _ _ _ _--,
Ql
Q2
Q3
Q4
Q5
Q6
Q7
GND
Q8
Q7
Q6
Q5
Q4
ORDER NUMBER:
DM74S188 J, DM74S288 J,
DM54S188 J, DM54S288 J
SEE NS PACKAGE J16A
Figure 11.5.1
Q3
Q2
1
2
3
4
5
6
7
8
Ql
ORDER NUMBER:
DM74S188 N OR DM74S288 N
SEE NS PACKAGE N16A
Block and Connection Diagram
308
Programmable Logic Design Guide
DM54/74S188, DM54/74S288 (32 x 8) 256-BIT TTL PROMs
DC Electrical Characteristics
(Note 3)
DM54S188/288
Sym
Parameter
DM74S1881288
Conditions
Units
Min
Typ
Max
-80
-250
Min
Typ
Max
-80
-250
IlL
Input Load Current
Vee = Max, VIN = O.45V
IIH
Input Leakage Current
Vee = Max, VIN = 2.7V
25
25
p.A
Vee = Max, VIN = 5.5V
1.0
1.0
mA
VOL Low Level Output Voltage Vee = Min, 10L = 16mA
0.35
0.50
0.35
p.A
0.45
V
0.80
V
50
P.A
100
p.A
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
loz
Output Leakage Current
,Vee = Max, VeEx = 2.4V
I Open-Collector OnlYI
Vee = Max, VeEx = 5.5V
Ve
·Input Clamp Voltage
Vee = Min, liN = -18mA
-0.8
CI
Input Capacitance
Vee = 5.0, VIN = 2.0V
4.0
4.0
pF
Co
Output Capacitance
Vee=5.0V, Vo=2.0V
T A = 25C, 1MHz, Outputs Off
6.0
6.0
pF
lee
Power Supply Current
Vee = Max, Inputs Grounded
All Outputs Open
70
0.80
2.0
V
2.0
50
100
-0.8
-1.2
-1.2
V
TA = 25C, 1MHz
70
110
110
mA
-70
mA
TRI-STATE® Parameters
los
Short Circuit
Output Current
Vo = OV, Vee = Max
I Note 41
loz
Output Leakage
Vee = Max, Vo ='0.45 to 2.4V
+50
+50
p.A
I TRI-STATE I
Chip Disabled
-50
-50
p.A
VOH Output Voltage High
IOH=-2.0mA
-20
2.4
-70
-20
3.2
V
3.2
2.4
IOH= -6.5mA
V
AC Electrical Characteristics
(With Standard Load and Operating Conditions)
DM54S1881288
Sym
Parameter
Units
Min
TAA
TEA
TER
TZX
TXZ
DM74S1881288
JEDEC Symbol
Address Access Time
Enable Access Time
Enable Recovery Time
Output Enable Time
uutput uisable Time
TAVQV
TEVQV
TEXQX
TEVQX
TEXQZ
Typ
Max
22
15
15
15
15
30
35
30
35
Min
Typ
Max
22
15
15
15
15
35
45
20
25
20
25
Note 3: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee = S.OV and TA = 25C.
Note 4: During lOS measurement, only one output at a time should be grounded. Permanent damage may otherwise result.
Table 11.5.2
AC and DC Specifications for (32 x 8) 256-Bit TTL PROMs
ns
ns
ns
ns
ns
Data Sheets
11.6
309
PL77X288/PL87X288 (32 x 8) 256-81T TTL LOGIC PROMs
General Description
These Schottky programmable logic devices are organized in the popular 32 words by
8-bit configuration. An enable input is provided to control the output states. When the
device is enabled, the outputs represent the contents of the selected word. When disabled, the 8 outputs go to the OFF or high impedance state. The memories are available
in the TRI-STATE® version only.
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location by following the programming instructions.
Features
•
•
•
•
•
Advanced titanium-tungsten (Ti-W) fuses
Schottky-clamped for high speed
- Addressed access-IOns typ
- Enable access-8 ns typ
- Enable recovery-8 ns typ
PNP inputs for reduced input loading
All DC and AC parameters guaranteed over temperature
Low voltage TRI-SAFETM programming
Commercial
Military
PL87X288
PL77X288
X
X
Table 11.6.1
Open·
Collector
TRI-STATE
Package
X
X
N,J
J
(32 x 8) 256-Bit TIL PROM Options
Dual·ln·Llne Package
A4
A3
A2
At
AD
256 BIT OR ARRAY
PROVIDING
ALL 32 PRODUCT TERMS
ii
00
16
Vee
01
15
D
02
14
A4
Q3
13
A3
04
12
AI
05
11
Al
06
10
AD
GND
9
07
TOP VIEW
Figure 11.6.1
Block and Connection Diagram
310
Programmable Logic Design Guide
PL77X288/PL87X288 (32 x 8) 256-BIT TTL LOGIC PROMs
DC Electrical Characteristics (Note 3)
Symbol
Parameter
PL77X288
Conditions
Min
PL87X288
Typ
Max
-80
-250
Min
Typ
Max
-80
-250
Units
p.A
IlL
Input Load Current
IIH
Input Leakage Current Vee~ Max, VIN =2.7V
25
25
p.A
Vee = Max, VIN = 5.5V
1.0
1.0
mA
0.50
V
0.80
V
Vee = Max, VIN = 0.4V
VOL
Low Level Output
Voltage
Vee = Min, IOL=24 mA (Com)
10L = 12 mA (Mil)
V IL
Low Level Input
Voltage
(Note 7)
V IH
High Level Input
Voltage
(Note 7)
Ve
Input Clamp Voltage
Vee = Min, liN = -18 mA
CI
Input Capacitance
Vee = 5.0V, VIN=2.0V
TA =25'C,1 MHz
4.0
4.0
pF
Co
Output Capacitance
Vee=5.0V, Vo=2.0V
TA =25'C,1 MHz, Outputs Off
6.0
6.0
pF
Icc
Power Supply Current Vee = Max, Inputs Grounded
All Outputs Open
0.35
0.50
0.35
0.80
2.0
2.0
-0.8
V
-1.5
110
-0.8
140
-1.5
110
V
140
mA
-130
mA
100
100
p.A
-100
-100
p.A
TRI-5TATE
los
Short Circuit Output
Current
Vo=OV, Vee = Max
(Note 4)
loz
Output Leakage
(TRI·STATE)
Vee = Max, Vo=0.4V to 2.4V
Chip Disabled
Output Voltage High
10H= -2.0mA
VOH
-30
-130
2.4
-30
V
3.2
2.4
10H= -3.2mA
3.2
V
AC Electrical Characteristics with standard load and operating conditions
Symbol
Parameter
JEDEC Symbol
PL87X288
PL77X288
Min
Typ
Max
Min
Typ
Max
Units
tM
Address Access Time (Note 5)
TAVQV
10
20
10
15
ns
tEA
Enable Access Time (Note 5)
TEVQV
8
15
8
12
ns
tER
Enable Recovery Time (Note 6)
TEXQX
8
15
8
12
ns
tzx
Output Enable Time (Note 5)
TEVQX
8
15
8
12
ns
txz
Output Disable Time (Note 6)
TEXQZ
8
15
8
12
ns
Nota 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may be
operated at these values.
Note 2: These limits do not apply during programming. For the programming ratings, refer to the programming parameters.
Note 3: These limits apply over the entire operating range unless stated otherwise. All typical values are for
Vee = 5.0V and TA = 25
D
C.
Nota 4: During lOS measurement, only one output at a time should be grounded. Permanent damage may otherwise result.
Noto 5: eL = 50 pF.
Noto 6:
eL = 5 pF.
Nota 7: These are absolute voltages with respect totheground pin on thedevlce and Includes all overshoots due to system andfortester noise. Do not attempt
to test these values without suitable equipment.
Table 11.6.2 AC and DC Specifications for (32 x 8) 256-Bit TIL Logic PROMs
Data Sheets
11.7
311
DM54/74LS471 (256 x 8) 2048-81T TTL PROMs
General Description
These Schottky memories are organized in the popular 256 words by 8 bits configuration. Memory enable inputs are provided to control the output states. When the device
is enabled, the outputs represent the contents of the selected word. When disabled, the 8
outputs go to the "OFF" of high impedance state.
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location by follOWing the programming instructions.
Features
•
•
•
•
•
Advanced titanium-tungsten (Ti-W) fuses
Schottky-clamped for high speed
- Addressed access-40 ns typ
- Enable access-IS ns typ
- Enable recovery-IS ns typ
PNP inputs for reduced input loading
All DC and AC parameters guaranteed over temperature
Low voltage TRI-SAFET" programming
OpenMilitary
Commercial
DM74LS471
Collector
TRI-STATE
Package
X
N,J
X
J
X
DM54LS471
X
Table 11.7.1
(256 x 8) 2048-Bit TIL PROM Options
20 V
A7
A6
AS
19 CC
A7
18 A6
AI
A2
21J48.BITARRAY
GENERATING 256
UNIQUE PRODUCT TERMS
AD
AI
17 A5
A3
A4 5
16 -
E2
A2
01 6
15
Ei
A3
A4
~~
14
os
13 ~7
9
04
GNO 10
12 06
" 05
Order Number;
DM74LS471 J,
DM54LS471 J,
See NS Package J20B
'Ord~ Number;
DM74LS471 N
See NS Package N20A
08
07
06
05
04
Figure 11.7.1
03
02
01
Block and Connection Diagram
312
Programmable Logic Design Guide
DM54/74LS471 (256 x 8) 2048·BIT TTL PROMs
DC Electrical Characteristics I Note 31
DM54LS471
Sym
Parameter
Units
Min
IlL
Input Load Current
IIH
Input Leakage Current
Vee = Max, VIN = 0.45V
Vee = Max, VIN = 2.7V
Typ
Max
-80
-250
Vee = Max, VIN = 5.5V
VOL Low Level Output Voltage
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
Ve
Input Clamp Voltage
CI
Input Capacitance
DM74LS471
Conditions
0.35
Vee = Min, 10L = 16mA
Min
Typ
-80
25
JlA
1.0
1.0
mA
0.45
V
V
V
V
0.35
0.50
2.0
0.80
2.0
-0.8
JlA
25
0.80
Vee = Min, liN = -18mA
Vee = 5.0, VIN = 2.0V
Max
-250
-1.2
-0.8
-1.2
4.0
4.0
pF
6.0
pF
TA=25C,1MHz
Co
Output Capacitance
Vee = 5.0V, Vo = 2.0V
T A = 25C, 1MHz, Outputs Off
6.0
lee
Power Supply Current
Vee = Max, Inputs Grounded
All Outputs Open
75
100
75
100
mA
-70
mA
TRI-STATE® Parameters
lOS
loz
-20
Vo = OV, Vee = Max
Output Leakage
Vee = Max, Vo = 0.45 to 2.4V
+50
+50
JlA
ITRI-STATE I
Chip Disabled
-50
-50
JlA
VOH Output Voltage High
-70
1Note 41
10H =-2.0mA
2.4
AC Electrical Characteristics
2.4
Address Access Time
Enable Access Time
Enable Recovery Time
Output Enable Time
Ou!put Disable Time
DM74LS471
JEDEC Symbol
Units
Min
TAA
TEA
TER
TZX
TXZ
3.2
IWith Standard Load and Operating Conditions 1
DM54LS471
Parameter
V
V
3.2
10H =6.5mA
Sym
-20
Short Circuit
Output Current
TAVQV
TEVQV
TEXQX
TEVQX
TEXQZ
Typ
Max
45
70
35
35
35
35
15
15
15
15
Min
Typ
Max
40
60
15
15
15
15
30
30
30
30
ns
ns
ns
ns
ns
Note 3: These limits apply over the entire operating range unless stated otherwise. AU typical values are for Vee;;;;;; S.OV and TA = 25C.
Note 4: DUring lOS measurement, only one output at a time should be grounded. Permanent damage may otherwise result.
Table 11.7.2 AC and DC Specifications for (256 x 8) 2048-Bit TIL PROMs
Data Sheets
11.8
313
DM54/74S473, DM54/74S472; DM54/74S473A, DM54n4S472A;
DM54/74S472B (512 x 8) 4K-BIT TTL PROMs
General Description
These Schottky memories are organized in the popular 512 words by 8 bits configuration. A memory enable input is provided to control the output states. When the device
is enabled, the outputs represent the contents of the selected word. When disabled, the
8 outputs go to the OFF or high impedance state. The memories are available in both
open-collector and TRI-STATE® versions.
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location by following the programming instructions.
Features
• Advanced titanium-tungsten (Ti:W) fuses.
• Schottky-clamped for high speed.
Address access-25 ns typo
Enable access-I5 ns typo
Enable recovery-I5 ns typo
• PNP inputs for reduced input loading.
• All DC and AC parameters guaranteed over temperature.
• Low voltage TRI-SAFETM programming.
Commercial
Open.
Collector
DM74S473
X
X
DM74S472
X
Mlltary
DM54S473
X
DM54S472
X
TRI·STATE
N,J
X
N,J
X
J
X
Table 11.8.1
Package
J
512 x 8 4096-Bit TTL PROM Optics
INPUT
AS BUFFER , . . - - - - - - - - - - - - - - - ,
AO 1
A7
A6
A5
A12
409B-BIT ARRAY
GENERATING 512 UNIQUE
PRODUCT TERMS
AO
Al
A2 3
A3 4
A4 5
A2
A3
A4
Order Number:
DM74S473 J, DM74S472 J,
DM54S473 J, or DM54S472 J
See NS Package J20S
Ql 6
7
Q2 8
Q3 9
Q4
GND 10
El
07
06
Q5
Q4
Q3
Figure 11.8.1
Q2
Order Number:
DM74S473 N or DM74S472 N
Se. NS Package N20A
Ql
Block and Connection Diagram
314
Programmable Logic Design Guide
DM54/74S473, DM54/74S472, DM54/74S473A, DM54/74S472A, DM54/74S472B
DC Electrical Characteristics
(Note 3)
DM54S4731472
Sym
Parameter
Units
Min
IlL
Input Load Current
Vee = Max, VIN = O.45V
IIH
Input Leakage Current
Vee = Max, VIN = 2.7V
Vee = Max, VIN = 5.5V
VOL
VIL
VIH
loz
Low Level Output Voltage Vee = Min, 10L = 16mA
Low Level Input Voltage
High Level Input Voltage
Output Leakage Current
I Open-Collector Only I
Ve
CI
Input Clamp Voltage
Input Capacitance
Co
Output Capacitance
lee Power Supply Current
DM74S473/472
Conditions
Typ
-80
Max
-2SO
Min
Typ
Max
-80
-250
25
1.0
0.35
O.SO
0.80
2.0
Vee = Max, VeEx = 2.4V
Vee = Max, VeEX = 5.5V
Vee = Min, liN = -18mA
0.35
SO
100
-1.2
-0.8
4.0
V
V
V
50
100
-1.2
p.A
p.A
V
pF
6.0
6.0
Vee = 5.0V, Vo = 2.0V
TA = 25C, 1MHz, Outputs Off
Vee = Max, Inputs Grounded
All Outputs Open
110
155
110
p.A
p.A
mA
0.45
0.80
2.0
-0.8
4.0
Vee = 5.0, VIN = 2.0V
TA = 25C, 1MHz
25
1.0
pF
155
mA
-70
mA
TRI-STATE® Parameters
los Short Circuit
Output Current
loz Output Leakage
ITRI-STATE 1
Vo = OV, Vee = Max
I Note 41
VOH Output Voltage High
IOH=-2.0mA
IOH=6.5mA
-20
-70
-20
+SO
-SO
Vee = Max, Vo = 0.45 to 2.4V
Chip Disabled
2.4
+SO
-SO
3.2
2.4
3.2
p.A
p.A
V
V
AC Electrical Characteristics
(With Standard Load and Operating Conditions)
DM54S473/472
Sym
Parameter
Units
Min
TAA
TEA
TER
TZX
TXZ
Address Access Time
Enable Access Time
Enable Recovery Time
Output Enable Time
uutput uisable lime
DM74S473/472
JEDEC Symbol
TAVQV
TEVQV
TEXQX
TEVQX
TEXQZ
Typ
Max
40
75
35
35
35
15
15
15
15
35
Min
Typ
Max
40
15
15
15
15
60
30
30
3(!
30
Table 11.8.2 AC and DC Specifications for (512 x 8) 4096-Bit TIL PROM
ns
ns
ns
ns
ns
Data Sheets
315
AC Electrical Characteristics
(With Standard Load and Operating Conditions)
Sym
Parameter
TAA Address Access Time
TEA Enable Access Time
TER Enable Recovery Time
TZX Output Enable Time
TXZ butput Disable Time
JEDEC Symbol
TAVaV
TEVaV
TEXaX
TEVaX
TEXaZ
DM54S473A/472A, B
Min
Typ
Max
DM74S473A/472A, B
Min
Typ
Max
Units
473A/472A
25
60
25
45
ns
4728
25
50
25
35
ns
473A/472A
15
35
15
30
ns
4728
15
15
25
ns
473A/472A
15
35
35
15
30
ns
4728
15
35
15
25
ns
473A/472A
15
35
15
30
ns
15
25
ns
4728
15
35
473A/472A
15
35
15
30
ns
4728
15
35
15
25
ns
Note 3: These "mlts apply over IheenUre operatIng /lInge unless stated otherwIse. All typIcal values are for Vee
=5.0V and TA =25C.
Nola 4: During lOS measurement. only one output at a time shaullf be grounded. Permanent damage may otherwise result.
Table 11.8.2 AC and DC Specifications for (512 x 8) 4096-Bit TIL PROM (Cant.)
316
Programmable Logic Design Guide
11.9 DM54/74S475, DM54/74S474; DM54/74S475A, DM54/74S474A;
DM54/74S474B, (512 x 8) K-BIT TTL PROMs
General Description
These Schottky memories are organized in the popular 512 words by 8 bits configuration. Memory enable inputs are provided to control the output states. When the device
is enabled, the outputs represent the contents of the selected word. When disabled, the
8 outputs go to the OFF or high impedance state. The memories are available in both
open-collector and TRI-STATE® versions.
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location by following the programming instructions.
Features
• Advanced titanium-tungsten (Ti:W) fuses.
• Schottky-clamped for high speed.
Address access-25 ns typo
Enable access-I5 ns typo
Enable recovery-I5 ns typo
• PNP inputs for reduced input loading.
• All DC and AC parameters guaranteed over temperature.
• Low voltage TRI-SAFETM programming.
Military
DM74S475
DM74S474
DM54S475
DM54S474
CommercIal
OpenCollector
X
X
X
TRI-5TATE
X
X
X
X
X
Table 11.9.1
Package
N.J
N.J
J
J
(512 x 8) 4096-Bit TIL PROM
INPUT
ABBUFFER
.7
A6
r------------,
ORDER NUMBER:
AS
4096-BIT ARRAY
GENERATING 512
UNIQUE PRODUCT TERMS
A4
'3
DM74S475 J, DM74S475 J,
DM45S415 J, DM54S474 J
SEE HS PACKAGE J24A
ORDER NUMBER:
DM74S475 N OR DUNS.7, N
SEE HS PACKAGE N24A
07
OB
05
Q'
03
Figure 11.9.1
02
a1
Block and Connection Diagram
Data Sheets
317
DM54/74S745, DM54/74S474, DM54/74S475A, DM54/74S474A, DM54174S474B
DC Electrical Characteristics
(Note 3)
DM54S47S/474
Sym
Parameter
Units
Min
IlL
IIH
VOL
VIL
VIH
loz
Ve
CI
Co
Icc
DM74S475/474
Conditions
Input Load Current
Input Leakage Current
Vee = Max, VIN = O.45V
Vee = Max, VIN = 2.7V
Vee = Max, VIN = 5.5V
Low Level Output Voltage Vee = Min, 10L = 16mA
Low Level Input Voltage
High Level Input Voltage
Output Leakage Current Vee = Max, VeEX = 2.4V
(Open-Collector Only)
Vee = Max, VeEX = 5.5V
Input Clamp Voltage
Vee = Min,IIN=-18mA
Input Capacitance
Vee = 5.0, VIN = 2.0V
TA = 25C, 1MHz
Output Capacitance
Vee = 5.0V, Vo = 2.0V
TA = 25C, 1MHz, Outputs Off
Power Supply Current
Vee = Max, Inputs Grounded
All Outputs Open
Typ
Max
-250
25
1.0
0.50
0.80
-80
0.35
2.0
Typ
-80
0.35
Max
-250
25
1.0
0.45
0.80
2.0
50
100
-1.2
-0.8
4.0
I
Min
-0.8
4.0
6.0
50
100
-1.2
6.0
115
170
115
p.A.
J.lA
rnA
V
V
V
J.lA
J.lA
V
pF
pF
170
rnA
-70
rnA
+50
-50
p.A.
p.A.
V
V
TRI-STATE® Parameters
los Short Circuit
Output Current
loz Output Leakage
(TRI-STATE)
VOH Output Voltage High
Vo=OV, Vee = Max
(Note 4)
Vcc - Max, Vo - 0.45 to 2.4V
Chip Disabled
IOH=-2.0mA
10H= 6.5mA
-70
-20
-20
+50
-50
2.4
3.2
2.4
3.2
AC Electrical Characteristics
(With Standard Load and Operating Conditions)
DM54S47S/474
Sym
Parameter
Units
Min
TAA Address Access Time
TEA Enable Access Time
TER Enable Recovery Time
ILX Iuutput Enable Time
TXZ Output Disable Time
DM74S47S/474
JEDEC Symbol
TAVOV
TEVOV
TEXOX
TEVOX
TEXOZ
Typ
Max
40
20
20
20
20
75
40
40
40
40
Table 11.9.2 AC and DC Specifications for (512
High Speed PROM
X
Min
Typ
Max
40
20
20
20
20
65
35
35
35
35
8) 4096-Bit TIL
ns
ns
ns
ns
ns
318
Programmable Logic Design Guide
AC Electrical' Characteristics
(With Standard Load and Operating Conditions)
; DM54S475A/474A, B
Sym
Parameter
TAA Address Access Time
JEDEC Symbol
TAVQV
Min
Typ
Max
DM74S475A/474A, B
Min
Typ
Max
Units
I 475A/474A
25
60
25
45
ns
I 4748
25
50
25
35
ns
TEA Enable Access Time
TEVQV
15
35
15
25
ns
TER Enable Recovery Time
TEXQX
15
35
15
25
ns
TZX Output Enable Time
TEVQX
15
35
15
25
ns
TXZ Output Disable Time
TEXQZ
15
35
15
25
ns
Nole 3: TheSP. limits apply over Ihe enllre oporallng range unless staled Olherwlse. Aillypical values are for Vee = S.OV and TA = 2SC.
Nole 4: During lOS measurement. only one output at a time should be grounded. Permanent damage may otherwise result.
Table 11.9.2 AC and DC Specifications for (512 x 8) 4096-Bit TIL
High Speed RPOM (Cant.)
Data Sheets
11.10
DM77/87SR474, DM77/87SR474B (512
TTL PROM
319
x 8) 4K-BIT REGISTERED
General Description
The DM77 /87SR474 is an electrically programmable Schottky TTL read-only memory
with D-type, master-slave registers on-chip. This device is organized as 512 words by
8-bits and is available in the TRI-STATE output version. Designed to optimize system
performance, this device also substantially reduces the cost and size of pipelined
microprogrammed systems and other designs wherein accessed PROM data is temporarily stored in a register. The DM77/87SR474 also offers maximal flexibility for memory expansion and data bus control by providing both synchronous and asynchronous
output enables. All outputs will go into the OFF state if the synchronous chip enable
(GS) is high before the rising edge of the clock, or if the asynchronous chip enable (G)
is held high. The outputs are enabled when GS is brought low before the rising edge of
the clock and G is held low. The GS flip-flop is designed to power-up to the OFF state
with the application of Vee.
Data is read from the PROM by first applying an address to inputs Ao-As. During the
setup time the output of the array is loaded into the master flip-flop of the data register.
During the rising edge (low-to-high transition) of the clock, the data is then transferred
to the slave of the flip-flop and will appear on the output if the output is enabled. Following the rising edge clock transition, the addresses and synchronous chip enable can
be removed and the output data will remain stable.
The DM77/87SR474 also features an initialize function, INIT. The initialize function
provides the user with an extra word of programmable memory which is accessed with
single pin control by applying a low on INIT. The initialize function is synchronous and
is loaded into the output register on the next rising edge of the clock. The unprogrammed state of the INIT is all lows, providing a CLEAR function when not
programmed.
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location by following the programming instructions. Once
programmed, it is impossible to go back to a low.
320
Programmable Logic Design Guide
Features
• On-chip, edge-triggered registers.
• Synchronous and asynchronous enables for word expansion.
• Programmable synchronous register INITIALIZE.
• 24-pin, 300 mil thin-DIP package.
• 35 ns address setup and 20 ns clock to output for maximum system speed.
• Highly reliable, titanium tungsten fuses.
• TRI-STATE® outputs.
• Low voltage TRI-SAFPM programming.
• All parameters guaranteed over temperature.
• Pinout compatible with DM77SR181 (1 K x 8) Registered PROM for future
expansion.
INPUT
BUFFER
A,
1.
24
Vee
A,
2
23
22
A,
NC
A_
4
21
G
A3
5
20
IN IT (ClR)
A.
6
19
G.
A,
7
18
CK
Ao
8
17
Q,
A.
4096 BIT ARRAY
GENERATING
512 UNIQUE
PRODUCT TERMS
A.
A,
A.
DM77SR474
Q.
9
16
Q,
Q,
10
15
Q.
Q.
11
14
GND
12
13
QQ3
ClK --1>........- - - - 1
TUL5189
Order Number DM77SR474J,
DM87SR474J, DM87SR474N,
DM77SR474BJ, DM87SR474BJ
or DM87SR474BN
See NS Package J24F or N24C
Q.
Q,
Q.
Figure 11.10.1
Q3
Q_
Q.
Q.
Q,
Tl/l5189
Block and Connection Diagrams
Data Sheets
321
DM77/87SR474
DC Electrical Characteristics
Symbol
LIL
Parameter
Input Load Current
(Note 3)
DM77SR474
Conditions
Min. Typ.
Max.
-80
-250
Vcc=Max., VIN =0.45V
DM87SR474
Min.
Typ.
Max.
-80
-250
Units
p.A
Vcc=Max., VIN =2.7V
25
25
p.A
Vcc=Max., V IN =5.5V
1.0
1.0
mA
IIH
Input Leakage Current
VOL
Low Level Output Voltage Vcc =Min.,l oL =16mA
VIL
Low Level Input Voltage
VIH
High Level Input Voltage
loz
Output Leakage Current
Vcc = Max., VCEX = 2.4V
0.35
0.35
0.50
0.80
2.0
0.45
V
0.80
V
50
p.A
2.0
V
50
Vc
Input Clamp Voltage
Vcc = Min., liN = - 18mA
CI
Input Capacitance
Vcc =5.0, V IN =2.0V
TA = 25°C, 1MHz
-0.8
-1.2
Co
Output Capacitance
Icc
Power Supply Current
los
Short Circuit
Output Current
Vo = OV, Vcc = Max.
(Note 4)
-20
-70
loz
Output Leakage
(TRI-5TATE)
Vcc = Max., Va = 0.45 to 2.V
Chip Disabled
-50
+50
10H= -2.0mA
2.4
VOH
Output Voltage High
-0.8
-1.2
V
, 4.0
4.0
pF
Vcc= 5.0V, Va=2.0V
TA = 25°C, 1MHz, Outputs Off
6.0
6.0
pF
Vcc = Max., Inputs Grounded
All Outputs Open
135
185
135
185
mA
-20
-70
mA
-50
+50
p.A
TRI-STATE Parameters
10H= -6.5mA
3.2
V
2.4
3.2
V
Note 3: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee = 5.0V and TA = 25°C,
Note 4: During los measurement, only one output at a time should be grounded, Permanent damage may otherwise result.
Table 11.10.1 AC and DC Specifications for (512 x 8) 4K-Bit Registered TIL PROMs
322
Programmable Logic Design Guide
DM77/87SR474B
Switching Characteristics
Symbol
DM77SR474
Parameter
Min.
55
40
0
~ ~=:~:B
Typ.
20
20
-5
DM87SR474
Max. Min. Typ. Max.
50
20
35
20
0
-5
Units
tS(A)
Address to elK (High) Setup Time
tH(A)
Address to elK (High) Hold Time
tS(INIl]
INIT to elK (High) Setup Time
30
20
25
20
tH(INIT)
tpHL(CLK)
tpLH(CLK)
INIT to elK (High) Hold Time
0
-5
0
-5
lWH(CLK)
WL(CLK)
elK Width (High or low)
25
13
20
13
ns
IS(GS)
GS to elK (High) Setup Time
10
0
10
0
ns
tH(GS)
GS to elK (High) Hold Time
5
0
5
0
ns
tpZL(CLK)
tpZH(CLK)
tpZL(G)
tpZH(G)
Delay from elK (High) to Output Active (High or low)
20
35
20
30
ns
Delay from G (low) to Output Active ("!igh or Low)
15
30
15
25
ns
tpLZ(CLK)
tpHZ(CLK)
Delay from elK (High) to Output Inactive (TRI-STATE)
20
35
20
30
ns
tpLZ(G)
tpHZ(G)
Delay from
15
30
15
25
ns
Delay from elK (High) to Output (High or low)
I SR474
15
15
I SR474B
G(low) to Output Inactive (TRI-STATE)
30
25
15
15
ns
ns
ns
27
20
ns
Table 11.10.1 AC and DC Specifications for (512 x 8) 4K-Bit Registered TIL PROMs
(Cant.)
Data Sheets
11.11
323
DM77/87SR476, DM77/87SR25, DM77/87SR476B,
DM77/87SR25B (512 x 8) 4K-BIT REGISTERED TTL PROMs
General Description
The DM77 187SR476 is an electrically programmable schottky TTL read-only memory
with D-type, masterslave registers on-chip. This device is organized as 512 words by
8-bits and is available in the TRl-STATE® output version. Designed to optimize system
performance, this device also substantially reduces the cost and size of pipelined
microprogrammed systems and other designs wherein accessed PROM data is temporarily stored in a register. The DM77 187SR476 also offers maximal flexibility for memory expansion and data bus control by providing both synchronous and asynchronous
output enables. All outputs will go into the OFF state if the synchrounous chip enable
(GS) is high before the rising edge of the clock, or if the asynchrounous chip enable (G)
is held high. The outpus are enabled when GS is brought low before the rising edge of
the clock and G is held low. The GS flip-flop is designed to power up to the OFF state
with the application of Vce.
Data is read from the PROM by first applying an address to inputs AO-A8. During the
rising edge (low-to-high transition) of the clock, the data is then transferred to the slave
of the flip-flop and will appear on the output if the output is enabled. Following the rising edge clock transition, the addresses and synchronous chip enable can be removed
and the output data will remain stable.
The DM77SR476 also features an initialize function, INIT. The initialize function provides the user with an extra word of programmable memory which is accessed with
single pin control by applying a low on INIT. The initialize function is asynchronous
and is loaded into the output register when INIT is brought low. The unprogrammed
state of the INIT is all lows, which makes it compatible with the CLEAR function on the
AM27S25. PS loads lows into the output registers when brought low.
PROMs are shipped from the factory with lows in all locations. A high may be programmed into any selected location by following the programming instructions. Once
programmed, it is impossible to go back to a low.
Features
• Functionally compatible with AM27S25.
• On-chip, edge-triggered registers.
• Synchronous and asynchronous enables for word expansion.
• Programmable asynchronous INITIALIZE (SR476 only).
• 24-pin, 300 mil thin-DIP package.
• 35 ns address setup and 20 ns clock to output for maximum system speed.
324
Programmable Logic Design Guide
• Highly reliable, titanium tungsten fuses.
• TRI-STATE outputs.
• Low voltage TRI-SAFPM programming.
• All parameters guaranteed over temperature.
• Preset input.
1 OF 64
WORD
DECODER
4096-BIT ARRAY
GENERATING 512
UNIQUE PRODUCT TERMS
A.
10F8 A,
BIT As
DECODER
INIT
~L~--~O-------~
A7
1.
24
Vee
As
2
23
As
As
A.
Ao
DM77SR476
DM77SR25
A.
22
Ps
21
G
20
INIT (CLR)"
19
0;
A,
7
CK
a7
a.
as
As
8
a.
a,
a.
9
11
Q.
GND
12
a.
10
PS--~~--------~
CLK--~~---------4
'CLR only on DM77/87SR25
Order Number DM77SR476J,
DM77SR25J, DM77I87SR476N,
DM77/87SR25N, DM77SR476BJ,
DM77SR25BJ, DM77/87SR476BN
or DM77/87SR25BN
See NS Package J24F or N24C
Figure 11.11.1 Block and Connection Diagrams
TUL5190
Data Sheets
325
DM77/87SR476, DM77/87RS25, DM77/87SR476B, DM77/87SR25B
DC Electrical Characteristics
Symbol
LIL
Parameter
Input Load Current
IIH
Input Leakage Current
(Note 3)
DM77SR474
Conditions
Min. Typ.
Max.
-80
-250
Vcc = Max., VIN = 0.45V
DM87SR474
Min.
Typ.
Max.
-80
-250
Units
p.A
Vcc=Max., V IN =2.7V
25
25
p.A
Vcc=Max., VIN =5.5V
1.0
1.0
mA
0.45
V
0.35
VOL
Low Level Output Voltage Vcc = Min., 10L = 16mA
V IL
Low Level Input Voltage
VIH
High Level Input Voltage
loz
Output Leakage Current
Vcc = Max., VCEX = 2.4V
Vc
Input Clamp Voltage
Vcc = Min., liN = - 18mA
-0.8
CI
Input Capacitance
Vcc =5.0, V IN =2.0V
TA = 25°C, 1MHz
4.0
4.0
pF
Co
Output Capacitance
Vcc= 5.0V, Vo=2.0V
TA = 25°C, 1MHz, Outputs Off
6.0
6.0
pF
Icc
Power Supply Current
Vcc = Max., Inputs Grounded
All Outputs Open
135
los
Short Circuit
Output Current
Va = Ov, Vcc = Max.
(Note 4)
loz
Output Leakage
(TRI-STATE)
VOH
Output Voltage High
0.35
0.50
0.80
2.0
0.80
2.0
50
-0.8
-1.2
135
185
V
V
50
p.A
-1.2
V
185
mA
TRI·STATE Parameters
-20
-70
-20
-70
mA
Vcc = Max., Va = 0.45 to 2.V
Chip Disabled
-50
+50
-50
+50
p.A
10H= -2.0mA
2.4
V
3.2
2.4
10H= -6.5mA
3.2
V
Note 3: These limits apply over the entire operating range unless stated otherwise. All typical values are for Vee = S.OV and TA = 2SoC.
Note 4: During los measurement, only one output at a time should be grounded. Permanent damage may otherwise result.
Table 11.11.1 AC and DC Specifications for (512
X
8) 4K·Bit Registered TIL PROMs
326
Programmable Logic Design Guide
Switching Characteristics
Symbol
DMnSR476, 476B DM87SR476, 476B
DMnSR25, 25B
DM87SR25, 25B
Parameter
ISR476, SR25
ISR476B, SR25B
Min.
1\tp.
Max.
Min.
Typ.
55
20
50
20
40
20
35
20
0
-5
Units
Max.
ns
tS(A)
Address to elK (High) Setup Time
tH(A)
Address to elK (High) Hold Time
tpHL(CLK)
Delay from elK (High) to Output
tpLH(CLK)
(High or low)
tWH(CLK)
tWL(CLK)
elK Width (High or low)
25
13
25
13
ns
tS(GS)
GS to elK (High) Setup Time
10
0
10
0
ns
tH(GS)
GS to elK (High) Hold Time
5
0
5
0
tpLH(PS)
Delay from PS (low) to Output (High)
20
30
20
25
ns
tpLH(INIT)
tpHL(INIT)
Delay from INIT (low) to Output (low or High)
20
30
20
25
ns
tWL(PS)
PS Pulse Width (low)
15
10
15
10
tWL(INIT)
INIT Pulse Width (low)
15
10
15
10
ts(PS)
PS Recovery (High) to elK (High)
25
10
20
10
ns
tS(INIT)
INIT Recovery (High) to elK (High)
25
10
20
10
ns
tpZL(CLK)
tpZH(CLK)
Delay from elK (low) to Active Output (High or low)
tpZL(G)
tpZH(G)
Delay from
tpLZ(CLK)
tpHZ(CLK)
Delay from elK (High) to Inactive Output (TRI-5TATE)
tpLZ(G)
tpHZ(G)
Delay from
0
ISR476, SR25
ISR476B, SR25B
G(low) to Active Output (low or High)
G(High) to Inactive Output (TRI·STATE)
-5
ns
15
30
15
27
15
25
15
20
ns
ns
ns
20
35
20
30
ns
15
30
15
25
ns
20
35
20
30
ns
15
30
15
25
ns
Table 11.11.1 AC and DC Specifications for 20-Pin Ultra High-Speed, Medium PAL
Devices (Cant.)
Data Sheets
11.12
327
REGISTERED PROM PROGRAMMING PROCEDURE
National Schottky PROMs are shipped from the factory with all fuses intact.. As a result,
the outputs will be low (logical "0") for all addresses. To generate high (logical" 1") levels at the outputs, the device must be programmed. Information regarding commercially available programming equipment can be obtained from National. If it is desired
to build your own programmer, the following conditions must be observed:
1. Programming should be attempted only at ambient temperatures between 15 ° and
30°C.
2. Address and enable inputs must be driven with TTL logic levels during programming and verification.
3. Programming will occur at the selected address when Vee is at 1O.5V, and at the
selected bit location when the output pin representing that bit is at 1O.5V, and the
device is subsequently enabled. To achieve these conditions in the appropriate
sequence, the following procedure must be followed:
a) Select the desired word by applying high or low levels to the appropriate
address inputs. Disable the device by applying a high level to the asynchronous
Chip Enable input G. GS is held low during the enable programming time.
b) Increase Vee from nominal to 10.5 volts (± 0.5V) with a slew rate between 1.0
and 1O.OV/",s. Since Vee is the source of the current required to program the
fuse as well as the lee for the device at the programming voltage, it must be
capable of supplying 750mA at 1l.0V.
c) Select the output where a logical high is desired by raising that output voltage to
1O.5V (± O.5V). Limit the slew rate from 1.0 to 1O.OV/",s. This voltage change
may occur simultaneously with the increase in Vee, but must not precede it. It
is critical that only one output at a time be programmed since the internal circuits can only supply programming current to one bit at a time. Outputs not
being programmed must be left open or connected to a high impedance source
of 20kO minimum. (Remember that the outputs of the device are disabled at this
time.)
d) Enable the device by taking the chip enable (G) to a low level. This is done with
a pulse of lO",s. The lOiLS duration refers to the time that the circuit (device) is
enabled. Normal input levels are used, and rise and fall times are not critical.
e) Verify that the bit has been programmed by first removing the programming voltage from the output and then reducing Vee to 4.0V (± 0.2V) for one verification
and to 6.0V (± 0.2V) for a second verification. Verification at a Vee level of 4.0V
and 6.0V will guarantee proper output states over the Vee and temperature range
of the programmed part. Each data verification must be preceded by a positive
going (low-to-high) clock edge to load the data from the array into the output
register. The device must be enabled to sense the state of the outputs. During verification, the loading of the output must be within specified IOL and IOH limits.
Steps b, c, and d must be repeated up to 10 times or until verification that the bit
has been programmed.
328
Programmable Logic Design Guide
t) The initialize word is programmed by setting INIT input to a logic low and pro-
gramming the initialize word output by output in the same manner as any other
address. This can be accomplished by inverting the A9 address input from the
PROM programmer and applying it to the INIT input. Using this method, the initialize word will program at address 512.
g) Following verification, apply five additional programming pulses to the bit
being programmed. The programming procedure is now complete for the
selected bit.
h) Repeat steps a through f for each bit to be programmed to a high level. If the
procedure is performed on an automatic programmer, the duty cycle of Vee at
the programming voltage must be limited to a maximum of 25%. This is necessary to minimize device junction temperatures. After all selected bits are programmed, the entire contents of the memory should be verified.
Programming Parameters
Do not test or you may program the device
Symbol
Parameter
Vccp
Required Vcc for Programming
Iccp
Icc During Programming
Test
Conditions
Min.
Recommended
Value
10
10.5
Vcc=l1V
10
10.5
Vop
Required Output Voltage for Programming
lop
Output Current While Programming
IRR
Rate of Voltage Change of Vec or Output
1
9
10
VOUT=l1V
Max.
Units
11
V
750
mA
11
V
20
mA
10
V/p.s
11
p.S
V
PWE
Programming Pulse Width (Enabled)
VeeVL
Required Low Vee for Verification
3.8
4
4.2
VCCVH
Required High Vee for Verification
5.8
6
6.2
V
Moe
Maximum Duty Cycle for Vee at Veep
25
25
%
Table 11.12.1 Programming Parameters. Do Not Test or You May Program the Device.
Data Sheets
329
Programming Waveforms
ADDRESS
INPUTS
=t=
>C
SELECTED ADDRESS STABLE
-----------------------------------------
Tl
VCCPVcc VCCVH
5.0V
PROGRAMMEO VOH
21-
-I
17..------IWi&%! __
V;:.T
T51-
1
OUTPUT ~
VOL
ENABl~
,.
VCCVH
VCCVL
-ILn
1- ~~-T6-"""'1I
PWE
n
ClK _ _ _ _ _ _ _ _ _ _ _ _.....
CLOCK
__ I9??i%%
~
OUTPUT
VERIFY
Ta r--jT41-
OUTPUT
VERIFY
I
~~-T6-l~
n
L..__________....
L..-_ _
Tl=100 ns MIN.
T2=5 ~s MIN. (T2 MAY BE> 0 IF Vccp RISES AT THE SAME RATE OR FASTER THAN VoP.)
Ta= 100 ns MIN.
T4=1DO ns MIN.
T5=1DD ns MIN.
T6=5D ns MIN.
Figure 11.12.1
11.13
Programming Waveforms Registered PROM
NON-REGISTERED PROM PROGRAMMING PROCEDURE
National Schottky PROMs are shipped from the factory with all fuses intact. As a result,
the outputs will be low (logical "0") for all addresses. To generate high (logical" 1") levels at the outputs, the device must be programmed. Information regarding commercially available programming equipment can be obtained from National. If it is desired
to build your own programmer, the following conditions must be observed:
1. Programming should be attempted only at ambient temperatures between 15 and 30
degrees Celsius.
2. Address and enable inputs must be driven with TTL logic levels during programming and verification.
3. Programming will occur at the selected address when Vee is at 10.5 volts, and at the
selected bit location when the output pin representing that bit is at 10.5 volts, and
the device is subsequently enabled. To achieve these conditions in the appropriate
sequence, the following procedure must be followed:
330
Programmable Logic Design Guide
a) Select the desired word by applying high or low levels to the appropriate address
inputs. Disable the device by applying a high level to asynchronous Chip Enable
input G. GS is held low during the enable programming time.
b) Increase Vee from nominal to 10.5 volts (± 0.5V) with a slew rate between 1.0
and 1O.0V/JLs. Since Vee is the source of the current required to program the fuse
as well as the Icc for the device at the programming voltage, it must be capable of
supplying 750 mA at 11.0 V.
c) Select the output where a logical high is desired by raising that output voltage to
10.5 volts (± 0.5V). Limit the slew rate from 1.0 to 1O.0V/JLs. This voltage change
may occur simultaneously with the increase in Vee, but must not precede it. It is
critical that only one output at a time be programmed since the internal circuits
can only supply programming current to one bit at a time. Outputs not being programmed must be left open or connected to a high impedance source of 20kO
minimum. (Remember that the outputs of the device are disabled at this time.)
d) Enable the device by taking the chip enable (G) to a low level. This is done with a
pulse of 1Op.s. The 10JLs duration refers to the time that the circuit (device) is
enabled. Normal input levels are used and rise and fall times are not critical.
e) Verify that the bit has been programmed by first removing the programming voltage from the output and then reducing Vee to 4.0V (± 0.2V) for one verification
and to 6.0V (± 0.2V) for a second verification. Verification at a Vee level of 4.0V
and 6.0Vwill guarantee proper output states over the Vee and temperature range
of the programmed part. Each data verification must be preceded by a positive
going (low-to-high) clock edge to load the data from the array into the output
register. The device must be enabled to sense the state of the outputs. During verification, the loading of the output must be within specified IOL and IOH limits.
Steps b, c, and d must be repeated up to 10 times or until verification that the bit
has been programmed.
f) Following verification, apply five additional programming pulses to the bit being
programmed. The programming procedure is now complete for the selected bit.
g) Repeat steps a through f for each bit to be programmed to a high level. If the procedure is performed on an automatic programmer, the duty cycle of Vee at the
programming voltage must be limited to a maximum of 25 %. This is necessary to
minimize device junction temperatures. After all selected bits are programmed,
the entire contents of the memory should be verified.
Note: Since only an enabled device is programmed, it is possible to program these
parts at the board level if all of the programming parameter are complied with.
TRI-STATE® is a registered trademark of National Semiconductor Corp.
TRI-SAFETM is a trademark of National Semiconductor Corp.
Data Sheets
331
Programming Parameters
Do not test or you may program the device
Symbol
Test
Conditions
Parameter
Vccp
Required Vee for Programming
leep
Icc During Programming
Vop
Required Output Voltage for Programming
lop
Output Current While Programming
Min.
Recommended
Value
Max.
10
10.5
11
V
750
mA
Vee= l1V
10
10.5
VO UT =IIV
Units
11
V
20
mA
IRR
Rate of Voltage Change of Vec or Output
1
10
VII'S
PWE
Programming Pulse Width (Enabled)
9
10
11
1'5
VeeVL
Required Low Vee for Verification
3.8
4
4.2
V
VcevH
Required High Vee for Verification
5.8
6
6.2
V
Moe
Maximum Duty Cycle for Vee at Veep
25
25
%
Table 11.13.1
Programming Parameters
Do Not Test or You May Program the Device
Programming Waveforms Non·Registered PROM
ADDRESS
INPUTS
-y
x::=
SELECTED ADDRESS STABLE
-~-T'--------------VeepVee VeeVH
5.DV
-I T51-
_ T__
t
VopPROGRAMMED VOH
/
OUTPUT
~
VOL
ii
ENABLE
ClK
CLOCK
•
~
T31---IT41-
PWE
r- r- -1
OUTPUT
VERIFY
I
T6
n
T, = 100 ns MIN.
T2=51's MIN. (T2 MAY BE> 0 IF Veep RISES AT THE SAME RATE OR FASTER THAN VoP.)
T3=100 ns MIN.
T4=100 ns MIN.
T5=100 ns MIN.
T6=50 ns MIN.
Figure 11.13.1
~
~«l
OUTPUT
VERIFY
Ln
--1
VeeVH
VeeVL
r- --1
I
T6
n
Programming Waveforms Non-Registered PROM
332
Programmable Logic Design Guide
MANUFACTURER
SYSTEM #
DATA 1/0
PRO·LOG
KONTRON
STAG
AIM
DIGELEC
STARPLEX™
5/17/19/29A
M910, M980
MPP80S
PPX
RP400
UP803
Table 11.13.2 Approved Programmers for NSC PROMs
11.14 QUALITY ENHANCEMENT PROGRAMS
A + PROGRAM *
Guaranteed
LOTAQL5
Condition
Test
25°C
D.C.
Parametric
And
Functionality
A.C.
Parametric
B+PROGRAM
0.05
Each
Temperature
Extreme
0.05
25°C
0.4
Critical
0.01
Mechanical
Seal
Tests
Hermetic
Guaranteed
Test
D.C.
Parametric
And
Functionality
A.C.
Parametric
Condition
LOT AQL 5
25°C
0.05
Each
Temperature
Extreme
0.05
25°C
0.4
Critical
0.01
Mechanical
Major
0.28
Fine Leak
(5 x 10 ..... 1
0.4
Gross
0.4
Seal
Tests
Hermetic
Major
0.28
Fine Leak
(5 x 10 ..... 1
0.4
Gross
0.4
-Includes 160 hours of burn-in at 125°C.
Table 11.14.1
Quality Enhancement Program for Bipolar Memory
=
12
New Product Data Sheets
12.0 New Product Data Sheets
12.1
TTL PAL Devices
PLA87/77XI53B 18 x 42 x 10 Field Programmable Logic Array .. 335
Programmable Array Logic (PAL) 24-Pin Exclusive-OR PAL SeriesVersionA .............................................. 341
Programmable Array Logic Family Series 24B ................. 353
Programmable Array Logic (PAL) Ultra High Speed Series 24BP .. 365
Programmable Array Logic (PAL) 20-Pin Medium PAL FamilySeries D ................................................ 377
Programmable Array Logic (PAL) 24-Pin Medium PAL FamilySeries D ................................................ 393
Programmable Array Logic PAL 16RA8 ...................... 409
Programmable Array Logic PAL20RAI0 ..................... 417
12.2
CMOS Programmable Logic Devices
GALl6V8 Generic Array Logic ............................. 425
GAL20V8 Generic Array Logic ............................. 439
12.3
ECL PAL Devices
ECL Programmable Array Logic (PAL) Family ................. 455
ECL Registered and Latched Programmable Array Logic (PAL)
Family ................................................. 465
4 ns ECL Programmable Array Logic (PAL) Family ............. 483
333
=
New Product Data Sheets
12.1
335
TTL PAL DEVICES
PLA87/77X153B
18 X 42 X 10 Field Programmable Logic Array
General Description
Features
The PLA87177X153B is a member of the National's FPLA
family, (programmable AND array driving a programmable
OR array) utilizing National Semiconductor's advanced Oxide Isolation Schottky TIL process (OXISS)TM.
•
•
•
•
•
•
•
The PLA871nX153B contains 32 product terms (AND
terms), 10 sum terms (OR terms) and 10 control terms
(TRI-STATEiI!I terms), up to 18 inputs and 10 outputs. Each
output is individually programmable for active-high or activelow logic with TRI-STATE control. Up to 32 product terms
are available for an output.
The PLA871nX153B is available in 20-pin Molded Dip, Cerdip and PCC packages. There are 8 dedicated input pins, 10
bidirectional I/0s and 2 power pins per package.
The PLA87177X153B is field programmable supported by
standard programming equipment.
PRELIMINARY
March 1987
Advanced Oxide Isolation process
Reliable Titanium-Tungsten fuses
Skinny Dip 20-pin package
Programmable output polarity and TRI-STATE
Security fuse to prevent direct copying
Power dissipation 500 mW (typ)
Propagation delay
PLA87X153B: 20 ns
PLAnX153B: 30 ns
Logic Function
f (1) = PO + P1 ... P31 for polarity link intact
f (1) = IPO ° IP1 ... °/P31 for polarity link open where PO
through P31 are product terms
Functional & Pin Diagrams
°9
°0
,@
'0
Vee
'I
89
'2
88
'3
87
86
'5
85
84
'.
83
80
GNO
82
8,
TLlL/9218-2
Order Number PLA77X153B
or PLA87X153B
See NS Package Number
J20A,N20A,orV20A
80
Applications
89
TLlLl9218-1
• Random logic
• Code converters
• Fault detectors
• Function generators
• Address mapping
• Multiplexing
TRI-STATEtI is a registered trademark of National Semiconductor Corporation.
OXISSTM Is a trademark of National Semiconductor Corporation.
336
Programmable Logic Design Guide
Absolute Maximum Ratings
Operating
7V
5.5V
5.5V
5.5V
Supply Voltage, Vee
Input Voltage
Off-State Output Voltage
Program Enable (Pin 18)
Programming
8.75V
12V
12V
18V
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Offlcel
Distributors for availability and specifications_
±30mA
100mA
- 65·C to + 150·C
Input Current, liN
Output Current, lOUT
Storage Temperature Range
>2000V
ESO Tolerance
CZAP = 100 pF
RZAP = 1500.0
Test Method: Human Body Model
Test Specification: NSC SOP 5-028
Recommended Operating Conditions
PLA77X153B
Parameter
Symbol
Min
Typ
PLA87X153B
Max
Min
Units
Typ
Max
Vee
Supply Voltage
4.5
5
5.5
4.75
5
5.25
V
TA
Operating Free-Air Temperature
-55
25
125
0
25
75
·C
Electrical Characteristics over Recommended Operating Temperature Range
Symbol
Conditions
Parameter
Min
Typ
Max
High level Input Voltage
Vll·
low Level Input Voltage
VIC
Input Clamp Voltage
Vee = Min, 11= -18 mA
VOH 2
High level Output Voltage
Vee = Min, Vil = 0.8V
VIH = 2V
10H = -2 mA PLA77X153B
Vee = Min, Vil = 0,8V
VIH = 2V
10l = 12 mA PLA77X153B
Vee = Max, Vil = 0.8V
VIH = 2V
Vo = 5.5V
40
/LA
Vo = 0.45V
-100
/LA
/LA
VOL 1
10ZH
2
Units
VIH·
Vee = Max
V
Vee = Min
low level Output Voltage
Off-State Output Currentt
IOZl
-0.8
2.4
0.8
V
-1.2
V
V
2.8
10H = -3.2 mA PLA87X153B
0.3
0.5
V
10l = 24 mA PLA87X153B
IIH
High Level Input Currentt
Vee = Max, VI = 5.5V
40
III
Low level Input Currentt
Vee = Max, VI = 0.45V
-100
/LA
Output Short-Circuit Current···
Vee = Max, Vo = OV
-70
-130
mA
Supply Current tt
Vee = Max
PLA77X153B
100
165
mA
PLA87X153B
100
155
mA
. los
Icc
t 1/0 pin leakage is the worst case of lozx or
tt Icc is measured with 10.7 and BQ.9 at 4.5V.
-30
IIX, e.g. III and IOZl.
1. Measured with + 10V applied to 16 for BO.4. 17 for BS.9.
2. Same as 1. plus applying 10V to 15.
"'These are absolute voltages with respect to the ground pin on the device and includes all overshoots due to system andlor tester noise. 00 not attempt to test
these values without suitable equipment.
'" '" "'Only one output shorted at a time.
New Product Data Sheets
337
Switching Characteristics Over Recommended Ranges of Temperature and Vee
PLA77XI53B: TA = -55'C to + 125'C', Vee = 5V ± 10%
PLAB7XI53B: TA = 0 to 75'C, Vee = 5V ± 5%
Symbol
Parameter
PLA87X153B
PLA77XI53B
Test Conditions
Min
= 50 pF
= 50 pF
CL = 5 pF
Typ
Max
Min
Units
Typ
Max
tpD
Input or Feedback to Output
CL
12
30
12
20
ns
tpzx
Input to Output Enable
CL
12
30
12
20
ns
tpxz
Input to Output Disable
12
30
12
20
ns
ACTest Load
MIL
Rl = 390
R2 = 750
COM'L
Rl = 200
R2 = 390
'"':~J'
I
c
R2
L
TLlLl9218-4
Test Waveforms
Propagation Delay
3V
INPUT
--'
IN-PHASE
OUTPUT
Vr
Vr
- --
tpHL
- --
tpLH
tpLH
OV
Vr
tpHL
OUT OF PHASE
OUTPUT
I-
Vr
Vr
I-
Vr
TL/Ll9218-6
Enable and Disable
::x
ENABLE 3V
(ENABLE PIN 1.5V
Vr
~
OR INPUT) OV ~ . . . . . ; . . - t - - - - - - - - - NORhlALLY V _
HIGH OUTPUT OH
(51 OPEN)
Z
_
PZH
I~V~r-----------k.~
I
trPZL
NORhlALLY
z-=tv
LOW OUTPUT
(51 CLOSED) VOL
\",.,;, _ _ _ _ _ _ _ _ _ _...J
---T
TL/L/9218-7
Notes:
CL includes probe and jig capacitance.
VT
~
1.5V.
In the example above. the phase relationships between inputs and outputs have been chosen arbitrarily.
All input pulses are supplied
by generators having the following
characteristics: PAR = 1 MHz, ZOUT =
son,
tr ::;; 5 ns, If ::s;: 5 ns.
tpD is tested with switch 81 closed and CL = 50 pF.
For TAl-STATE outputs, output enable times are tested with CL = 50 pF to the 1.SV level; 51 is open for high-impedance to HIGH tests and closed for high-impedance to LOW tests. Output disable times are tested with CL = 5 pF. HIGH to high-impedance tests are made to an output voltage of VOH -O.5V with 51 open.
LOW to high-impedance tests are made to the VOL + O.5V level with 51 closed.
Programmable Logic Design Guide
338
Logic Diagram PLA87177X153B
~~~;~;;~~lH~ _nRST rUSE
INCREMENT
8Ei~~~~~ ;~~~~§~! i:l!:;[!l~!!!:;:~o
- -
m
TERM
LA'ns
0
1
2
3
•
6
7
8
[[J----.b.
1"10
~
8
NUMBERS
•
ID
6
- - ..... - - - - - - (CONTROL TrRWS)
DgDaDJDaDsD"D3D2DIDo -
(lOOC TERWS - P)
ID
ffi----b.
"
j
1"10
Do
'1
"
'3
'.
"
'.
'7
'.
'.
•
10
11
12
13
,.
"16
17
18
I.
20
"
22
23
,.
25
26
27
2B
29
30
31
32
33
34
35
I
36
37
38
:E '.
;m '8
Q ~D
-Q ~D
:I1
;m '.
39-6. ~D
4O-Q; ::)D
;ill
.,
-Q ::)D
"P ::)D
-1m "
1838
:~ ~D
~D
45-£5 ~D
1S41
SECURITY FUSE NUMBER =18.2
POlARITY FUSE NUW'ERS /
-=
"
:E '.
"
~
"
:IT: "
PIN NUMBERS
PIN LABELS
-QJ '.
=:!J
TLlLl9218-3
Note: Fuse Number = First Fuse Number + Increment
New Product Data Sheets
339
Physical Dimensions inches (millimeters)
0.985
~-----(25.019) -----~
MAX
(0.127 -0.508)
RAO TVP
0.180
(4.572)
--(0~~)0.2OII
0.290-0.320
(7.366-8.'281~
MAX
0.020 - 0.060
GLASS SEALANT
=S-~
~150
, ,
(3.810)
MIN
0.008-0.012
(0.203 - 0.305)
1--(7.874-10.41)
0.310-0.410
0.018±0.003
(0.457±0.0761
_I L
J I
0.125-0.200
(3.175 - 5.080)
J20A(REVM)
Ceramic Dual-In-Line Package (J)
Order Number PLA77X153B or PLA87X153B
NS Package Number J20A
0.092 X 0.030
(2.337 X0.762)
MAXOP
1.013-1.040
(25.73-26.42)
:-:::1
~~====~~I1~'=6=='~'=="==~13===12=='='~---r
0.260 '0.005
(6.604 '0.127)
PIN ND. llDENT
~3:~~~:~
~rrrrmrn~mT.~~~~
~ Q'-L,lijl '~r----+-r-------~--------~
F-?i
'D~,;rJ
I
I
0.032.0.005\)'9
(0.813'0.127)
RAD
PIN NO.'IDENT~
OPTlDN 2
-90", 0.004"1
(~~~9-0.381)
.
.
+0040
0.325 -0:015
0.060<0.005
(1.52400.127)
I
r
0.DIS.0.003
(0.4570 0.076)
~~
0.125-0.140
(3.175-3.556)
0.020
(0.508)
MIN
18.255 +1.016)
~
-0.381
N20A(REVGl
Molded Dual-In-Line Package (N)
Order Number PLA87X153B
NS Package Number N20A
340
Programmable Logic Design Guide
Physical Dimensions inches (millimeters) (Continued)
i1.i43i
0.045ir
x45'
0.080
i2.03zi
DIA NOM
:'-':=~--r''''''''--+--''-- PEDESTAL
~
15'
~I
VIEWA·A
0.226
(5.74oj
NOM
SOUARE
0.310-0.330
(7.874-8.382)
(CONTACT DIMENSION)
0.013 -0.018
(0.330 - 0.457)
TVP
0.020
(0.508)
0.005-0.015
(0.127-0.381)
1=====f====rrr~rm=fffl~~:t:.
MIN
0.032 - 0.040
~aE!c=~U~:":
(0.813-1.016)
0.165-0.180
(4.191-4.572)
PIN NO.1
IDENT
/
V20A (REV J)
Ceramic Dual·ln·Line Package (V)
Order Number PLA87X153B
NS Package Number V20A
New Product Data Sheets
Programmable Array Logic (PAL ®)
24-Pin Exclusive-OR PAL Series-Version A
341
November 1987
General Description
The PAL Series 24A is an enhanced performance version of
the PAL series 24. These PAL devices feature an EXCLUSIVE-OR function. The sum of products is segmented into
two sums which are then XOR'ed at the input of the D-type
output register. The D input data is loaded into the register
on the rising edge of the system clock. The Q output of the
register can then be gated to the output pin by enabling the
active low TRI-STATE buffer. In addition to being available
at the output, the Q output is internally fedback as another
input to the programmable AND array. This allows the designer to configure the PAL device as a state sequencer
which can be programmed to execute fundamental count
functions. The XOR function provides an easy implementation of the HOLD operation used in counters and other state
sequencers.
The testability of the registered devices has been increased
through the addition of the register preload feature. During
testing, any arbitrary state value can be loaded into the registers, thereby allowing complete logiC verification.
The PAL Series 24A family lets the system engineer "design
his own chip" by blowing fusible links to configure AND and
OR gates to perform his desired logiC function. Complex
interconnections which previously required time-consuming
layout are thus "lifted" from PC board etch and placed on
silicon where they can be easily modified during prototype
checkout or production. This simplifies not only the PC
board layout, but also the board itself.
Unused inputs are tied directly to Vee or GND. Products
terms with all fuses blown assume the logical high state,
and product terms connected to both true and complement
of any single input assume the logical low state. PAL logic
diagrams are shown with all fuses blown, enabling the designer use of the diagrams as coding sheets.
The entire PAL family is programmed on conventional PAL
programmers. Once the PAL is programmed and verified,
two additional fuses (security fuses) may be blown to defeat
verification. This feature gives the user a proprietary circuit
which is very difficult to copy.
Features
•
•
•
•
•
•
•
•
•
•
Programmable replacement for conventional TTL logic
Reduces chip count by 5 to 1, typically
Expedites and simplifies prototyping and board layout
Variable input/output pin ratio
Programmable TRI-STATE outputs
Registers with feedback
Register preload feature guarantees testability
Arithmetic capability
Exclusive-OR gates
Last fuse reduces possibility of copying by competitors
Ordering Information
Part Types
Part Number
PAL20L10A
Description
DECA 20 input
AND-OR-INVERT Gate Array
PAL20X10A
DECA 20 input
Registered AND-OR-XOR Gate Array
PAL20X8A
OCTAL 20 input
Registered AND-OR-XOR Gate Array
PAL20X4A
QUAD 20 input
Registered AND-OR-XOR Gate Array
PAL Part Numbers
The PAL part number reveals the logic operation the part
performs. The example shown, the PAL20X8ANC, is a device that accommodates 20 input terms and 8 Exclusive-OR
Register output· terms. It is contained in a 24-pin plastiC
dual-in-line package and meets commercial temperature
range operation.
TRI-STATE- is a registered trademark of National Semiconductor Corporation.
PALe is a registered trademark of and use under license with Monolithic Memories, Inc.
. - - - - - - - - - PROGRAMMABLE ARRAY LOGIC FAMILY
. - - - - - - - - NUMBER OF ARRAY INPUTS
, . . . - - - - - - OUTPUT TYPE
X= EXCLUSIVE - OR REGISTERED
L=ACTlVE LOW COMBINATORIAL
rr;=
c=
, . . . - - - - - NUMBER OF OUTPUTS
SPEED/POWER
A = HIGH SPEED
PACKAGE TYPE
N= PLASTIC DIP
J = CERAMIC DIP
V= PLASTIC LEADED CHIP CARRIER
r - - TEMPERATURE RANGE
1
PAL 20 X 8 A N C
C=OOC TO +750 C
1/ =-550 C TO +1250 C(CASE TEMP.)
TL/U9256-1
342
Programmable Logic Design Guide
Absolute Maximum Ratings Spec for Series 24A (Note 1)
Operating
7V
Supply Voltage, Vee
Input Voltage
5.5V
Off-State Output Voltage
5.5V
Storage Temperature
ESD rating to be determined.
Programming
12V
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
>1000V
ESD Tolerance (Note 2)
Czap = 100 pF
Rzap = 15000
Test Method: Human Body Model
Test Specification: NSC SOP 5-028
22V
12V
- 65·C to + 150"C
Recommended Operating Conditions
Symbol
Military
Parameter
Commercial
Unlta
Min
Typ
Max
Min
Typ
Max
5.5
4.75
5
5.25
V
0
25
75
·C
Vee
Supply Voltage
4.5
5
TA
Operating Free-Air Temperature
-55
25
Te
Operating Case Temperature
·C
125
Electrical Characteristics Series 24A Over Recommended Operating Temperature Range
Symbol
Parameter
Test Conditions
VIH
High Level Input Voltage
(Note 3)
Vil
Low Level Input Voltage
(Note 3)
Vie
Input Clamp Voltage
Vee = Min., II = -18mA
VOH
High Level Output Voltage
Vee = Min.
Vil = 0.8V
VIH = 2V
VOL
10ZH
10Zl
Low Level Output Voltage
Vee = Min.
Vil = 0.8V
VIH = 2V
Off-State Output Current
(Note 4)
Vee = Max.
Vil = 0.8V
VIH = 2V
Min
Typ
Max
IOH=-2mA
10H = -3.2mA
Units
V
2
-0.8
0.8
V
-1.5
V
MIL
COM
10l = 12mA
MIL
10l = 24mA
COM
2.4
2.9
V
0.5
V
Vo = 2.4V
100
p.A
Vo = 0.4V
-100
p.A
1
mA
25
p.A
-0.04
-0.25
mA
0.3
II
Maximum Input Current
Vee = Max., VI = 5.5V
IIH
High Level Input Current
(Note 4)
Vee = Max., VI = 2.4V
III
Low Level Input Current
(Note 4)
Vee = Max., VI = 0.4V
los
Output Short-Circuit Current
Vee = 5V
Vo = OV (Note 5)
-70
-130
mA
Icc
Supply Current
Vee = Max.
20L10A
115
165
mA
20X10A,20X8A,20X4A
135
180
mA
-30
Note 1: Absolute maximum rallngs are those values beyond which the device may be permanenUy damaged. They do not mean that the device may be operated at
these values.
Note 2: It is recommended that precautions be taken to minimize electrostatic discharge when handling and testing this product. Pins 1 and 13 are connected
directly to the security fuses, and. anhough the Input circuitry can withstand the specified ESD condijions. the security fuses may be damaged preventing
subsequent programming and verification operations.
Note 3: These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system andlor tester noise. Do not attempt to
test these values without suitable equipment.
Note 4: 1/0 leakage as the worst case of lozx or I,x. e.g., III and IOZl.
Note 5: During los measurement, only one output at a time should be grounded. Permanent damage otherwise may result.
New Product Data Sheets
343
Switching Characteristics Over Operating Conditions
Symbol
Parameter
Military
Test Conditions
Min
tpD
Input or Feedback to Output
20L10A,20X8A,20X4A
CL
=
50pF
tcLK
Clock to Output or Feedback
CL
=
=
=
=
=
50pF
tpzx
Pin 13 (DIP) to Registered Output Enable
CL
tpxz
Pin 13 (DIP) to Registered Output Disable
CL
tpzx
Input to Combinatorial Output Enable
CL
tpxz
Input to Combinatorial Output Disable
tw
Width of Clock
CL
th
Hold Time
fMAX
Maximum Frequency
Units
Typ
Max
35
23
30
ns
10
25
to
15
ns
11
25
11
20
ns
10
25
10
20
ns
50pF
19
35
19
30
ns
5pF
15
35
15
30
ns
35
15
25
15
ns
20
7
15
7
ns
40
20
30
20
ns
0
-15
0
-15
ns
15.3
32
22.2
32
MHz
Schematic of Inputs and Outputs
Test Load
5V=f1~"
EQUIVALENT INPUT
Vee
MIL
R1 = 390
R2 = 750
OUTPUT
TtL
R2
-=
23
Min
50pF
LLow
Setup Time from Input or Feedback
20X10A,20X8A,20X4A
Max
5pF
I High
tsu
Commercial
Typ
COM'L
R1 = 200
R2 = 390
0--""""1r-----
-----_-0
yyfltCAL OUTPUT
lilQ NOM
INPUT
V..
4DQ NOM
o-_-E--+........-
":"
....H-oOUTPUT
TLlL/9256-2
Test Waveforms
Set-Up and Hold
~-------3V
CLOCK
INPUT
TL/L/9256-5
V, (SEE NOTE AI
-----~.....y--.,.__------ov
ls_ET_.UPJ~-IH-OL-O
DATA _ _ _ _
INPUT
-----3V
~".------OV
TL/Ll9256-3
Pulse Width
HIGH·LEVEl
PULSE _ _ _ _ _,
LOW·LEVEL
PULSE
TL/Ll9256-6
Propagation Delay
,--~--------3V
INPUT
IN-PHASE
OUTPUT _ _ _-+-~
. . .------.V
Enable and Disable
,.+__+-----VOH
I'"----VOL
,-----VOH
OUT OF PHASE
OUIPUT
~---------VOL
TL/Ll9256-4
Note A:. VT = 1.5V.
Note B: CL includes probe and jig capacitance.
Note C: In Ihe examples above. the phase relationships between inputs and
outputs have been chosen arbitrarily.
NORMAlLY lOW
OUTPUT
(51 CLOSED)
TLlL/9256-7
344
Programmable Logic Design Guide
Output Register PRELOAD
The PRELOAD function allows any arbitrary state to be loaded into the PAL output registers. This allows complete logic
verification, including states that are impossible or impractical to reach. The procedure for PRELOAD is as follows:
1. Raise Vee to 4.5V.
5. Remove VILIVIH from all outputs.
6. Lower pin 13 to VIL to enable the outputs.
2. Disable output registers by setting pin 13 to VIH.
7. Verify for VOLIVOH for all output registers.
3. Apply data (VIL or VIH) to corresponding outputs.
4. Pulse pin 10 to VIHHH, then back to OV.
PIN 1
PIN 13
OV-----------------------------------------VIL - - - - - '
OUTPUT VIH ---""""'
REGISTERS VIL ___--'
PIN 10
VIL - - - - - - - - - - - - - - '
TL/Ll9256-8
10;' 100 no
twp;'
100 no
22V ;, VIHHH ;, 19V
Programmer/Development Systems
The following list is some of the manufacturers of Programmer/De(jelopment Systems. Call them to see if they currently support
this device.
Programmers
Adv. Micro. Sys.
By1ek Compo Sys.
Citel
DATA 1/0
Digelec
Digital Media
GTEX Inc.
Int. Microsys.
Kontron
Logical Devices
Oliver Adv. Eng.
Pro-Log
Stag
PROMAC
Storey Systems
Structured Design
Sunrise
Valley Date Sci.
Varix
MMI
Nat. Semi.
Software Development
DATA 1/0
PCADSys.
Programming Algorithm Specification
For a complete programming spec. request National Semiconductor Spec #TS-2100-BPM.
New Product Data Sheets
345
Logic Diagram PAL20L 10A
Inputs (0-39)
o1
2 3
4 5 8 1
• 91011 12131415 16111.19 20212223 24252821 21293031 32333435 36313139
a
1
2
3
,....,.
~
23
JJ.
....
22
.J.
21
.J.
....
20
JJ.
r
19
JJ.
...
18
""\oJ"T
r>--1
JoI.
11
.J.
16
JoI.
15
.J.
....
14
~
.
....
~
,....,.
•
9
10
11
~
3
......
16
11
18
19
~
r-
4
......
24
25
28
21
5
32
33
34
35
-
&
,....,.
40
41
42
43
J--L
1
48
49
50
51
-
8
58
51
58
59
-
9
r
.. I
,....,.
64
65
r>.-I
-
&&
61
ID
r-
,....,.
12
13
14
15
J--L
-
11
01 23
4 511
13
811011 12131415 16111.19 20212223 24252621 21293631 32333435 36313831
TLlL/9256-9
346
Programmable Logic Design Guide
Logic Diagram PAL20X10A
Inpuls (0-39)
Ito.
...
G
,
D, 2 3
4 I • 1
• 11111 '213'4'5 11111111 211212223 2HUII1 212• • :11 3nnU5 31S131st
~9C> ~~
2
-3
23
~
I
•
:::::
,D
3
"
~
'1
"
;::::;
24
21
21
21
;::::;
11
11
~D
~
b.
...
22
~C>
~
b.
...
2'
~D
~
b.21
~
'"J.
II
~
'1.
-yo
18
~
'"J...
17
~
'""J
11
r.J.....
11
4
~
I
E~I:>
32
33
3'
31
I
~~I:>
..... -
40
4'
42
43
7
~
~~D
40
4'
511
5'
I
~D
.....
aa
57
51
51
•
:=:::.
:cr~D
54
IS
II
17
~
lD
~
72
13
74
...
....
....
~
.. .
~Dl:Dir.J
-
--....
7$
~
a
~
"
D, 2 3
4 1 I 7
I . '011 12'3'415 '8171111 21212223 24252127 2821313' 32333411 38373131
TL/L/9256-10
,~
New Product Data Sheets
347
Logic Diagram PAL20X8A
Inputs (0-39)
.
1 to.,
o1
2 3
4 5 I 7
• ,,011 12131415 '1'7""
20212223 24252127 21213031 32333435 3637313.
~
0
1
2
3
~ ........
.to!.
4:i=
23
I
n.
m90tol
8
9
10
11
22
v
3
16
17
m90-
rot.
21
~D=tH-
rot...
20
:.J...
19
h
18
~
b.
17
~
h..
16
~~
r.t
.
15
M
18
19
4
24
25
26
27
5
:Di
~o-
32
33
M
:-90M
34
35
6
40
41
42
43
V
7
~D-
4B
49
50
51
8
~D..... -
56
57
58
59
9
64
65
66
67
10
~
72
73
74
75
.....,
........
-J.
...
14
~
11
o1
23
4 5 I 7
.11011 12131415 11171111 20212223 24252127 21213031 32333435 3637313.
TL/L/9256-11
348
Programmable Logic Design Guide
Logic Diagram PAL20X4A
Inputs (0-39)
1
to..
...
o1
23
4 567
191011 12131415 16171119 211212223 24252&27 21293031
32333435 31373139
0
1
2
3
2
~,
...l
I
...L
I
~
.I"s""""
......
23
~
8
9
10
11
"'\.J""'"T..... ~
22
3
~
16
17
18
19
l--L
"1..J""T
.
.J
4
21
I
~[> ::Ojr:t
24
25
26
27
zo
5
~
~[>
.. -L
32
33
34
35
6
~[>
40
41
42
43
,
7
.....
48
49
50
51
::OJ
::OJ
I.J....
19
I.J.
....
18
I.J.
17
~D~ ...
8
.....
56
57
58
59
~,
9
.J
16
.J
15
.J
14
.. I
.....
64
65
66
67
"'I...r'T
10
.. I
......
72
73
74
75
.. I
11
o1
23
4 567
8 91011 12131415 18171111 211212223 24252127 21293031
~
32333435 31373131
TLlLl9256-12
New Product Data Sheets
349
Connection Diagrams
24 Pin Dual-In-Line Package
PAL20X4AJM
PAL20X4AJC
PAl20X4ANC
PAL20L 10AJM
PAL20L 10AJC
PAL20L10ANC
"
"
"
22
21
20
19
18
17
16
10
10
15
11
"
"
12
13
12
TLlLl9256-14
TLlLl9256-13
PAL20X10AJM
PAL20X10AJC
PAL20X10ANC
PAL20X8AJM
PAL20X8AJC
PAL20X8ANC
TL/L/9256-15
TL/L/9256-16
350
Programmable Logic Design Guide
Connection Diagrams
28 Pin Plastic Leaded Chip Carrier
PAL20L10AVC
PAL20X4AVC
4321282726
4321282726
5
25
6
24
INPUT
AND
OR
GATE
ARRAY
7
8
Ne
9
I/O
OUTPUT
CELLS
10
16
17
25
24
23
7
22
8
INPUT
AND
OR
GATE
ARRAY
23
OUTPUT
CELLS
22
I/O
21
9
I/O
20
10
20
19
11
19
11
12 13 14 15
5
18
21
12 13 14 15 16 17
18
TLlLl9256-17
TLlLl9256-18
PAL20X8AVC
4
3
2
PAL20X1 OAVC
28 27 26
4
3
2
1
28 27
26
5
25
5
25
6
24
6
24
23
7
22
8
21
9
10
20
10
20
11
19
11
19
7
8
9
INPUT
AND
OR
GATE
ARRAY
OUTPUT
CELLS
12 13 14 15 16 17
18
INPUT
AND
OR
GATE
ARRAY
23
OUTPUT
CELLS
12 13 14 15 16 17
TLlL/9256-19
22
21
18
TL/Ll9256-20
Note: The pin-out of the 24 pin PAL devices in PCC has been changed to the JEDEC standard for logic devices. Please contact your local sales office for
information regarding the availability of devices conforming to the old pin-out.
New Product Data Sheets
351
Physical Dimensions inches (millimeters)
0.025
(0.135) RAD
1.290
1~-------------(32.77)MAX--------------~
+
t•
H----(~..,.:~r:-)-
0.100 ±G.Ol0 ,
(2.54 ±G.254)--I
MIN
TVP
95° :!5"
,.-
O.OOS-O.012
0.310-0.410
,
~:p03-0.305)
I-- (7.874-10.41)--1
J24FillEYGI
Ceramic Dual-In-Line Package (J)
NS Package Number J24F
D.D92
(2.337)
(2 PLS)
D.2OO±D.ODS
(6.604±D.127)
PIN ND.l
IDENT
I
DPTIDN 2
0.062
(1.575)
RAD
0.3OD-D.32D
r::'"' I
0.009-0.015
(0.229-0.381)
0.325 ~ ~:~~~
18 255 + 1.016)
~
.
0.280
(7.112)
MIN
O.04D
(1.016)
TYP
-r-J I
D.D65
(1.651)
0.075±0.015
(1.905±0.381)
I--
-0.381
N24C(REVF)
Molded Dual-In-Line Package (N)
NS Package Number N24C
352
Programmable Logic Design Guide
Physical Dimensions inches (millimeters)
VIEW A-A
0.D45
(1.143)
x45'
0.165-0.180
(4.181-4.512)
t
0.026-0.032
(0.660-0.813)
TYP
+
f f
0.104-0.118
(2.142 - 2.997)
V28A (REV GI
Plastic Chip Carrier Package (V)
NS Package Number V28A
~
-II=:
New Product Data Sheets
Programmable Array Logic Family Series 248
353
September 1967
General Description
The PALl!> Series 24 family complements the PAL Series 20
family by providing four additional inputs, allowing more
complex functions in a single package. This new family is
made feasible by the new 300 mil-wide, 24-pin package.
In addition to providing more logic functions per chip, 24
pins allow for many natural functions which were previously
unavailable in 20-pin packages. Examples include:
• 6-bit parallel-in parallel-out counters
• 6-bit parallel-in parallel-out shift registers
• 1S-line-to-1-line multiplexers
• Dual 6-line-to-1-line multiplexers
• Quad 4-line-to-1-line multiplexers
These natural functions provide twice the density of traditional 1S-pin packages.
The PAL family utilizes an advanced oxide isolated Schottky
TTL process and the bipolar PROM fusible link technology
to provide user-programmable logiC for replacing conventional SSI/MSI gates and flip-flops at reduced chip count.
The family lets the systems engineer "design his own chip"
by blowing fusible links to configure AND and OR gates to
perform his desired logic function. Complex interconnections which previously required time-consuming layout are
thus "lifted" from PC board etch and placed on silicon
where they can be easily modified during prototype checkout or production. This often simplifies not only the PC
board layout, but also the board itself.
The PAL transfer function is the familiar sum of products.
Like the PROM, the PAL has a single array of fusible links.
Unlike the PROM, the PAL is a programmable AND array
driving a fixed OR array (the PROM is a fixed AND array
driving a programmable OR array). In addition, the PAL provides these options:
TABLE I. Part Types
Part
Number
Description
PAL20L88
OCTAL
20 Input AND-OR-INVERT Gate Array
PAL20R88
OCTAL
20 Input Registered AND-OR Gate Array
PAL20R68
HEX
20 Input Registered AND-OR Gate Array
PAL20R48
QUAD
20 Input Registered AND-OR Gate Array
PAL Part Numbers
The PAL part number reveals the logiC operation the part
performs. The example shown, the PAL20RSBNC, is a device that accommodates 20 input terms and generates S
register output terms. It is contained in a 24-pin plastic dualin-line package and meets commercial temperature range
specifications.
• Variable input! output pin ratio
• Programmable TRI-STATEI!> outputs
• Registers with feedback
Unused inputs are tied directly to VCC or GND. Product
terms with all fuses blown assume the logical high state,
and product terms connected to both true and complement
of any single input assume the logical low state. Registers
consist of D-type flip-flops which are loaded on the low-tohigh transition of the clock.
The entire PAL family is programmed on inexpensive conventional PAL programmers with appropriate personality
cards and socket adapters. Once the PAL is programmed
and verified, two additional fuses may be blown to defeat
verification. This feature gives the user a proprietary circuit
which is very difficult to copy.
Features
• Programmable replacement for conventional TTL logic
• Reduces IC inventories substantially and simplifies their
control
• Reduces chip count by 5 to 1, typically
• Expedites and simplifies prototyping and board layout
• Saves space with 300 mil-wide, 24-pin DIP packages
• Programmed on standard PAL programmers
• Programmable TRI-STATE outputs
• Last fuse reduces possibility of copying by competitors
• 15 ns max. propagation delay
• Registered outputs are initialized to a low state during
power up
• Preloadable registers for increased testability
Ordering Information
r------- Programmable Array Logic Family
r----- Number of Array Inputs
r---- Output Type
H = Active High
L=Active Low
C = Complementary
R = Registered
X = Exclusive-OR Registered
A = Arithmetic Registered
r - - - - Number of Outputs
Speed Range
No Symbol = Standard Speed (35ns)
A = High·Speed (25n5)
8 = Ultra High Speed (15 ns)
fti
P~C!~~:S~i~gIP
J = Ceramic DIP
V = Plastic Leaded Chip Carrier
Temperature Range
C=O to +75 D C
M = -55 D C to +125 D C
=-PA!-:-L2'::!O:::R:6:'::BNC
TRI-STATE- is a registered trademark. of National Semiconductor Corporation
PALilII is a registered trademark of and used under license from Monolithic Memories. Inc.
TLiL/B703-1
354
Programmable Logic Design Guide
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating
Programming
Supply Voltage, Vee
7V
12V
Input Voltage
5.5V
12V (Note 2)
Off·State Output Voltage
5.5V
12V
Storage Temperature
ESD Tolerance (Note 3)
CZAP = 100 pF
RZAP = 15000
Test Method: Human Body Model
Test Specification: NSC SOP·5·028
- 65'C to
+ 150'C
2000V
Operating Conditions
Symbol
Commercial
Military
Parameter
Units
Min
Typ
Max
Min
Typ
Max
Supply Voltage
4.5
5
5.5
4.75
5
5.25
V
TA
Operating Free·Air Temperature
-55
75
'C
Te
Operating Case Temperature
Vee
0
125
'C
Electrical Characteristics Over Operating Conditions
Symbol
Parameter
Min
Test Conditions
Typ
Max
Units
0.8
V
VIL
low level Input Voltage (Note 4)
VIH
High level Input Voltage (Note 4)
Vie
Input Clamp Voltage
Vee = Min., 1= -18 mA
-1.5
V
IlL
low level Input Current (Note 5)
Vee = Max., VI = 0.4V
-0.25
mA
IIH
High level Input Current (Note 5)
Vee = Max., VI = 2.4V
25
/LA
II
Maximum Input Current
Vee = Max., VI = 5.5V
1
mA
VOL
low level Output Voltage
Vee = Min.
Vil = 0.8V
VIH = 2V
0.5
V
VOH
High level Output Voltage
2
Vee = Min.
Vil = 0.8V
VIH = 2V
IOL = 12 mA
Mil
IOL = 24 rnA
COM
IOH = -2mA
Mil
10H = -3.2mA
COM
V
-100
/LA
Vo = 2.4V
100
/LA
-130
mA
210
rnA
Vee = Max.
Vil = 0.8V
VIH = 2V
los
Output Short·Circuit Current
(Note 6)
Vee = 5V, Vo = OV
lee
Supply Current
Vee = Max.
10ZH
2.4
Vo = 0.4V
Off·State Output Current
(Note 5)
10Zl
V
-30
160
Nole 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may be operated at
these values.
Nole 2: Pins 1 and 13 may be raised to 20V max. during security fuse programming.
Nole 3: It is recommended that precautions be taken to minimize electrostatic discharge when handling and testing this product. Pins 1 and 13 are connected
directly to the security fuses, and. although the input circuitry can withstand \he specified ESO conditions. the security fuses may be damaged preventing
subsequent programming and verification operations.
Nole 4: These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system andlor tester noise. Do not allemptto
test these values without suitable equipment.
Nole 5: 110 leakage as the worst case of IOZX or Ilx. e.g. III and IOZl.
Note 6: During los measurement, only one output at a time should be grounded. Permanent damage otherwise may result.
New Product Data Sheets
355
Switching Characteristics Over Operating Conditions
Symbol
Parameter
Military
Test Conditions
Min
input or Feedback to Output
tpD
20L8B, 20R6B,
20R4B
Cl = 50pF
Commercial
Typ
Max
11
20
Min
Units
Typ
Max
11
15
ns
telK
Clock to Output or Feedback
Cl = 50 pF
8
15
8
12
ns
tpzx
Pin 13 (DIP) to Output Enable
Cl = 50 pF
10
20
10
15
ns
tpxz
Pin 13 (DIP) to Output Disable
Cl = 5 pF
8
20
8
12
ns
tpzx
Input to Output Enable
Cl = 50 pF
11
25
11
18
ns
tpxz
Input to Output Disable
Cl = 5 pF
11
20
11
15
ns
tw
Width of Clock
tsu
Setup Time from Input or Feedback
I
I High
12
8
10
5
ns
12
8
10
5
ns
20
10
15
10
ns
0
-5
0
-5
ns
30
50
37
50
MHz
41.5
55
45
55
MHz
Low
20R8B, 20R6B,
20R4B
Hold Time
- tH
Maximum Frequency
fMAX
I With Feedback
I Without Feedback
Test Load
5V~~'
R1
OUTPUT
CL
(See Note B)
T
':"
A2
MIL
R1 = 390
COM'L
R2 = 750
R2
R1 = 200
=
390
'::"
TL/Ll8703-2
Test Waveforms
Set-Up and Hold
,;(Vr,.--------3v
CLOCK
(SEE HOTE AI
Pulse Width
HIGH-LEVEL
PULSE _ _ _ _ _- "
- - - - ,....4---;-------OV
'S_IT_.UJP~~~-~0-to-----3V
~".-----ov
DATA _ _ _ _
INPUT
LOW·lEVEl
PULSE
TL/L/8703-6
TLlL/8703-3
Propagation Delay
Enable and Disable
~--~-----------3V
INPUT
'-------DV
IN·PHASE
-+_"
_-I-_-!------VOH
NORMALLY HIGH
'-----VOl
IS1DPfNj
OUTPUT
OUTPUT _ _ _
~----VOH
DUTOF PHASE
OUTPUT
ENABLE
(ENABLE PIN OR IN pun
----------VOl
(See Note E)
NORMALLY lOW
OUTPUT
(51 CLOSEDI
--~~
.....------+_~_ I as,
VT
VT
VDl-.:.::....!......:~.....- - - - - - - " . . . . ! - - - - - r D 5V
TLlLl8703-4
TLlLl8703-7
Note A: VT
~
1.5V
Note B: CL includes probe and jig capacitance.
Note C: In the examples above, the phase relationships between inputs and
outputs have been chosen arbitrarily.
Note D: All input pulses are supplied by generators having the following
characteristics: PAR = 1 MHz. ZOUT = son.
Note E: When measuring propagation delay. switch 51 is closed.
356
Programmable Logic Design Guide
Programmable Array Logic Family Series 248
PAL20L8BNC
PAL20L8BJC
PAL20L8BJM
PAL20R8BNC
PAL20R8BJC
PAL20R8BJM
PAL20R6BNC
PAL20R6BJC
PAL20R6BJM
PAL20R4BNC
PAL20R4BJC
PAL20R4BJM
23
22
21
2.
1.
AHD
DR
GATE
ARRAY
1--1':>C1-.--4l'!!!.B
17
16
I.
I.
15
11
,.
11
12
13
12
TL/L/8703-22
TLlL/8703-23
TL/Ll8703-24
PAL20L8BVC
TL/L/8703-25
PAL20R8BVC
26
25
NC
INPUT
AND
OR
GATE
NC 22
I/O
ARRAY
NC
INPUT
AND
OR
GATE
2t
20
to
t9
11
tB
24
REG
23
I/o
O~~~T
25
24
I/O
23
REG
OUTPUT
CELLS
NC
21
REG
ARRAY
20
REG
19
18
TL/L/8703-26
PAL20R6BVC
TL/Ll8703-27
PAL20R4BVC
26
26
25
25
24
REG
NC
INPUT
AND
OR
GATE
to
It
ARRAY
22
23
REG
OUTPUT
CELLS
NC
REG
REG
24
REG
22
NC
INPUT
AND
OR
GATE
2t
20
10
t9
11
TLlL/8700-2B
Note: Please contact your local sales office about availability of old (non.JEDEC) PCC pinout.
ARRAY
23
REG
OUTPUT
CEllS
NC
REG
22
2t
20
19
TLlLl8700-29
357
New Product Data Sheets
Power-Up Set
The registers of the Series 248 have been designed with
the capability to "set" during system power-up. Following
power-up all registers will be set to high, setting all outputs
to a logical zero state. Due to the asynchronous operation
of the power-up and the wide range of ways Vee can rise to
its steady state value, two conditions are required to insure
a valid power-up set, these are:
1) The Vee rise must be monotonic.
2) Following the rising Vee, the clock input must not be
driven from low to high until all applicable input and
feedback setup times are met.
Power-Up Waveforms
VCC
--....JilL
___________________________
~_I~
REGISTERED
CLOCK
m
r
OUTPUTS
TSU
=:!_
VOH
VOL
V1L--------------------,j(,;",------
TL/LlB703-17
Parameter
Description
Tpi
Power-Up Initialize
Tsu
Set-Up Time from
Input or Feedback
I
Min
Com.
Mil.
15
20
Typ
Max
Units
600
1000
ns
10
10
ns
ns
Output Register Preload
The Preload function allows the register to be loaded synchronously from data placed on the input pins. This feature will simplify
testing since any state may be jammed into the registers to control test sequencing. The procedure for preloading the registers
(in DIP package) is as follows (refer to Preload Output Configurations diagram):
1) Apply Vee.
2) Disable the registered outputs by raising pin 13 to VIH.
3) Apply VIL to inputs corresponding to all non-registered outputs.
4) Apply the desired VILIVIH to the inputs corresponding to registered outputs. (A high input will force the register high and
the output low.)
5) Raise the Preload pins (pin 1B and pin 14) to VIHH. (VIHH = 11.75V ±0.25V)
6) Apply a clock pulse.
7) Remove VIHH from the Preload pins. (The data inputs will return to normal inputs.)
B) Lower pin 13 to VIL to enable the outputs.
358
Programmable Logic Design Guide
Output Register Preload
(Continued)
Preload Output Configurations
20R6B
20R8B
vee
,CLI(
20R4B
vee
ClK
vec
CLK
Pl
PL
GND
GND
GND
TL/L/B703-19
TL/L/B703-1 B
TLlL/B703-20
Preload Waveforms
vee
PIN 13
DATA IN
::
VIH
. m m m m n ___
/~---------~\\.
--------Xn-----------------
Vil - - - - - - -......~---------------VIHH
un
n
_n
n n
n
_n
n
__
n
__
n n
PIN 18
\
/
Vil
PIN 14
CLOCK
_ _ _ _ _ __
'"----------
VI:: ___
~~.
n
m
n
________
n
n
n
n
n
m _ m n _____ /
n
n
n
n
n
-
-
n
\ ' " -_ _ _ _ _ _ _ _ _
n
-
n
TL/L/8703-30
ProgrammerIDevelopment Systems The following list names some of the manufacturers of Programmer/Development Systems. Contact them to determine current support for this device.
Programmers
Adv. Micro. Sys.
8ytek Compo Sys.
Citel
DATA 110
Digelec
Digital Media
GTEKlnc.
Int. Microsys.
Kontron
Logical Devices
Oliver Adv. Eng.
Pro-Log
Stag
PROMAC
Storey Systems
Structured Design
Sunrise
Valley Data Sci.
Varix
MMI
Nat. Semi.
Software Development
DATA 110
PCADSys.
New Product Data Sheets
359
Logic Diagram PAL20L8B
Inputs (0-39)
o1
2 3
.. 567
891011
121J,4,5
~171a19
ro~22n
~~~27
n~~~
nU~J5
I
J.
V
~J1~J9
4::i:
it
,•
10
"
11
./
"
""
L..2
13
23
22
1C.
16
~
17
18
"
"
2J
:=t
c
"
""
"
........
../
27
28
21
V
../
20
21
4
-
r
....
J
20
30
31
~>
.t,
31
JJ
J4
r--...
../
35
"3138
"
~>
l
19
.t,
40
41
.,
42
"'"
./
44
45
J.
18
V
"
47
7
it
~
..
"
,."
"
51
l....../
53
J.
17
J.
16
V
55
~...>
1C.
"
"
"""
"
)-
57
........
)-
63
..
~>
.t,
54
"
66
61
68
../
"10
~o
15
71
10
11
~
10:
~
C
0123
4567
89101112131415
16171819
W~U23
~~U27
n~G31
3233~~
14
13
~VDJ9
TL/L/8703-13
360
Programmable Logic Design Guide
Logic Diagram PAL20R4B
Inpuls (0-39)
O'lJ
4567
89m1'
ll~MB
ffl171B~
M~nn
U~~17
n~~31
nJJ~~
~J7~n
~
,
~
~
"
"
""
11
13
3
~
16
17
"
""
11
4
""
>
24
"
16
17
18
"
./
"
30
31
5
-.,.....
33
E
-
~
./
J6
17
li)
"
39
6
-1>
I-
:S::
40
..""
U
42
::I
'tI
~
"'
./
45
46
11.
7
"
::t
:S::
..
>-'
50
51
"'
./
52
""
55
8
. .::t
11::
""
""
"
~
58
59
6J
9
~
"
~
65
66
67
""
!!!..t.>
~~
70
71
11
22
21
n~
:S::
31
I
a;
~
,.
"
e-
23
~
8
:S::
.>
0123
4567
89101'
12131415
1617~19
MZl22n
~~U27
n~IDJl
J2n~J5
~J7~J9
u
~
.....
R>~
fi
~
U
16
15
14
~
TL/L/B703-14
361
New Product Data Sheets
Logic Diagram PAL20R68
Inputs (0-39)
1
o1
2 J
•
~
6 7
891Dl1
12131.'5
16171819
20~2223
N~2627
2829~~
J233~~
~31~~
~
•,
~
10
11
"
13
14
15
3
:>
16
17
18
""
"
./
10
11
12
23
4
23
~
22
u~
~
:>
"
25
"
""
27
./
""3D
J1
..
~:>
11:
J2
J3
34
"'"
"
"
~":>
~./
36
37
38
.
~
"'I
"
"""
""
43
../
"
~":>
11:
""so
"
""
51
./
53
54
55
~":>
~
l-'
"
""
"
"
57
"'"
./
61
OJ
9
.
;C
":>
"
"
"
~
65
61
68
70
71
10
11
~
~
~
0' 2 3
4561
B 9Wl1
12131415
16111819 W21un
N~2621
~293031
32333435 36373839
tkl
~
n
n
~
~
n
~
tU
~
15
14
~
TL/L/B703-1S
362
Programmable Logic Design Guide
Logic Diagram PAL20R8B
Inputs (0-39)
1
0123
4567
S9Wl1
1213U~
1S17Ul9
~nnn
~~U27
H~~~
n~~~
~v~~
~
,•
23
to.
"
[h~
"""
11
"
""
./
13
s;
.t....2
16
11
""
""
,.
21
4
~
""
.....
./
20
....
s;
~
25
26
""
27
./
""
3D
31
5
s;
---1.2
U
1U
.....
31
33
"
""
./
31
38
39
6
..::
~
".
."
>-'
""
..
43
./
41
.!....t~
11:
....
50
51
""
./
""
""
~~
..::
""
"
-...
"
./
!O
9
"""
11:
~
~"
"
..."
~
67
./
10
n
~.2
~2
~
0123
4 5 6 7
89ml1
121lU15
16111819
~n22n
~u~n
28~ID~
n33NJS
~v~~
21
20
~
U
~
U
n
n
~
~
La
~
14
~
TL/L/8703-16
New Product Data Sheets
363
Physical Dimensions inches (millimeters)
1.210
.!:!!.
RAD
(1.135)
1-------i3m) MAX--------I
0.030-0.055
(0.112-1.391)
_of.;-__
n~
~ (:_: _:_:_·O _'2_:)_T_Y_P~-+ ~ ,(:_::_:~~~I'~_J~~~':~~ !::
_________ ____
__
__
(5.715)
MAX
tf•
"---:-.!.J-~:-)-
I
0.100 :10.010
(2.54 :10.2&4)-1
MIN
TYP
85· if{'
I--
0.0111-0.012
0.310-0Al0
~ ~y~03-0.3Oi)
(J.lJ4-10A1l
J24ft.IVG)
24-Pln Dual-In-Llne Package (J)
Order Number PAL20XXBJ
NS Package Number J24F
~___________ =1.~2Q==-=1.2~ro ___________~
(31.57-32.26)
MAX
0.092
(2.337)
(2 PLII
0.260±0.OD5
(6.1ifM ±0.127)
PIN NO.1
10ENT
j
0.009-0.015
(0.229-0.3811
0.325 ~~::S
Is 255 + 1.016)
~
.
0.065
(1.651)
.,---
-+~~--I
0.075±0.015
(1.105 ±0.3S1)
I
I-
-0.3S1
N24CIAEVFJ
24-Pln Dual-In-Llne Package (N)
Order Number PAL20XXBN
NS Package Number N24C
364
Programmable Logic Design Guide
Physical Dimensions inches (millimeters) (Continued)
r
l IITI
ISMCESIIf
0.Il10
11.270)
I" ~ JJ
I:~)
PEDESTAL
0.026-0.032
10.660 -0.813)
TYP
t
t~
(2.&42-2.997)
VDAIREVGI
28-Lead Plastic Chip Carrier (V)
Order Number PAL20XXBV
NS Package Number V28A
New Product Data Sheets
365
February 1988
Programmable Array logic (PAl®)
Ultra High Speed Series 24BP
General Description
The PAL family utilizes National Semiconductor's advanced
oxide isolated Schottky TTL process and bipolar PROM fusible-link technology to provide user-programmable logic to
replace conventional SSI/MSI gates and flip-flops. Typical
chip count reduction gained by using PALs is greater than
4:1.
The family lets the systems engineer customize his chip by
opening fusible links to configure AND and OR gates to
perform his desired logic functions. Complex interconnections that previously required time-consuming layout are
thus transferred from PC board to silicon where they can be
easily modified during prototype checkout or production.
The PAL transfer function is the familiar sum of products
with a single array of fusible links. Unlike the PROM, the
PAL is a programmable AND array driving a fixed OR array.
(The PROM is a fixed AND array driving a programmable
OR array). In addition, the PAL family offers these options:
• Variable input/output ratio
• Programmable TRI-STATE® outputs
• Registers and feedback
Product terms with all fuses blown assume the logical high
state, and product terms connected to both true and complement of any single input assume the logical low state.
Registers consist of D-type flip-flops that are loaded on the
low-to-high transition of the clock. The registers power up
with a high (VOH) at the output pin, regardless of the polarity
fuse. PAL logic diagrams are shown with all fuses blown,
enabling the designer use of the diagrams as coding sheets.
The entire PAL family is programmed on inexpensive conventional programmers with appropriate personality and
socket adapter cards. Once the PAL is programmed
and verified, two additional fuses may be blown to defeat
verification. This feature gives the user a proprietary circuit
which is very difficult to copy.
Functional Description
The PAL Series 248P represents an enhancement of existing PAL architectures which provides greater deSign flexibility and improved testability. Several new features have been
incorporated into the family, including programmable output
polarity, power-up reset, and register preload.
The programmable output polarity feature allows the user to
program individual outputs either active high or active low.
This feature eliminates any possible need for inversion of
Signals outside the device.
The registered members of the Series 248P have been designed to reset during system power-up. Upon application of
power, all registers are initialized to a logic 0 state, setting
all outputs to a logic 1.
The testability of the registered devices has been increased
through the use of the preload feature. During testing, registers can be loaded with any arbitrary state value, thereby
allowing full logical verification.
Features
•
•
•
•
•
•
•
Programmable output polarity
Power up reset for all registers
Preload feature during testing
Programmable replacement for TTL logic
Simplifies prototyping and board layout
Skinny DIP packages
15 ns max. propagation delay
Ordering Information
,-----PROGRAMMABLE ARRAY LOGIC fAMILY
Part
Number
PAL20P88
Description
,----NUMBER Of ARRAY INPUTS
OUTPUT TYPE
R= REGISTERED
P = PROGRAMMABLE OUTPUT POLARITY
OCTAL 20 Input AND-OR Gate Array
PAL20RP88 OCTAL 20 Input Registered AND-OR Gate Array
PAL20RP68
HEX
PAL20RP48 QUAD
NUMBER Of REGISTERED OUTPUTS (OR
TOTAL OUTPUTS If NON-REGISTERED)
20 Input Registered AND-OR Gate Array
SPEED RANGE
NO SYMBOL = STANDARD SPEED (35ns)
A = HIGH SPEED (25ns)
B = ULTRA HIGH SPEED(15ns)
20 Input Registered AND-OR Gate Array
PAL Part Numbers
The PAL part number reveals the logic operation the part
performs. In the example shown, the PAL20RP68NC, is a
device that accommodates 20 input terms, and generates 6
register output terms. It is contained in a 24-pin plastic dualin-line package and meets commercial temperature range
speCifications.
r
r
PACKAGE TYPE
N = PLASTIC DIP
J = CERAMIC DIP
V = PLASTIC LEADED CHIP CARRIER
TEMPERATURE RANGE
C=O TO +75°C
PAL20RP6BNC M=-550C TO +1250 C
TlIL/9046-1
IS a registered trademark of National Semiconductor Corporation.
PAL- is a registered trademark of and used under license from Monolithic Memones, Inc.
TRI·STATE~
366
Programmable Logic Design Guide
Absolute Maximum Ratings
Storage Temperature
ESO Tolerance
CZAP = 100 pF
RZAP = 1500n
Test Method: Human Body Model
Test Specification: NSC SOP·5·028
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating
Programming
Supply Voltage, Vee
7V
13V
5.5V
13V
Input Voltage
Off·State Output Voltage
5.5V
13V
-65·C to
+ 15O"C
>1000V
Recommended Operating Conditions
Symbol
Military
Parameter
Min
Vee
Supply Voltage
tw
Width of Clock
tsu
Setup Time from Input
or Feedback to Clock
Commercial
Typ
Max
Min
5.5
Max
5.25
4.5
5
4.75
5
Low
12
5
10
5
High
12
5
10
5
20RP8B
20RP6B
20RP4B
20
10
15
10
0
-10
0
-10
th
Hold Time
TA
Operating Free-Air Temperature
Te
Operating Case Temperature
-55
Unlta
Typ
0
V
ns
ns
ns
·C
75
·C
125
Electrical Characteristics Over Recommended Operating Temperatures Range
Symbol
Parameter
Test Conditions
Min
VIH·
High Level Input Voltage
Vll·
Low Level Input Voltage
Vie
Input Clamp Voltage
Vee = Min, II = -18 mA
VOH
High Level Output Voltage
Vee = Min
Vil = 0.8V
VIH = 2V
IOH=-2mA
MIL
IOH = -3.2mA
COM
Vee = Min
Vil = 0.8V
VIH = 2V
IOl=12mA
MIL
IOl = 24mA
COM
VOL
IOZH
Low Level Output Voltage
Off·State Output Currentt
10Zl
Typ
Max
V
2
Vee = Max
Vil = 0.8V
. VIH = 2V
-0.8
2.4
Units
0.8
V
-1.5
V
3.4
V
0.5
V
Vo = 2.4V
100
p.A
Vo = 0.4V
-100
p.A
mA
0.3
II
Maximum Input Current
Vee = Max, VI = 5.5V
1
IIH
High Level Input Currentt
Vee = Max, VI = 2.4V
25
p.A
III
Low Level Input Currentt
Vee = Max, VI = 0.4V
-0.04
-0.25
mA
los
Output Short-Circuit Current··
Vee = 5V, Vo = OV
-70
-130
mA
lee
Supply Current
Vee = Max
140
210
mA
-30
tllO pin leakage os the worst case of 10ZX or lOX e.g. 10l and IOZl.
'These are absolute voltages with respect to pin 12 on the device and include all overshoots due to system and/or tester noise. Do not attempt to test these values
without suitable equipment.
"Only one output shorted at a time.
New Product Data Sheets
367
Switching Characteristics Over Recommended Ranges of Temperature and Vee
+12~·C,
Military:TA = -55·Cto Te =
Symbol
Vee = 5V ±10%. Commercial: TA = O·Cto 75·C, Vec = 5V ±5%
Test
Conditions
Parameter
Military
Min
Commercial
Typ
Max
Min
Typ
Max
Units
tpD
20PBB, 20RP6B, 20RP4B Input or Feedback to Output
11
20
11
15
!eLK
Clock to Output or Feedback
B
15
B
12
ns
ns
10
20
10
15
ns
ns
tpzx
Pin 13 (DIP) to Output Enable Except 20PBA
tpxz
Pin 13 (DIP) to Output Disable Except 20PBA
11
20
11
15
tpzx
Input to Output Enable
I 20RP4B, 20RP6B, and 20PBB
10
20
10
15
ns
tpxz
Input to Output Disable .i20RP4B, 20RP6B, and 20PBB
11
20
11
15
ns
fMAX
20RPBB, 20RP6B, 20RP4B Maximum Frequency
ACTestLoad
30
50
37
50
MHz
ACTest Load
5VT.1~'"'
MIL
RI = 390
OUTPUT
Ttl
':"'
R2
=
750
COM'L
RI
= 200
R2 = 390
R2
';"
TUL/904S-2
8
Test Waveforms
Setup and Hold
,---------------sv
ClOCl(
INPUT
----------~~----~-----------ov
'SET·UP
-+--t--+- 'HOLD
.-----..-t--------SV
.
DATA
INPUT _______- '
'------------ov
Pulse Width
H'GH·LEVEL
PULSE
LOW'~~~~~
V,
------..
V,
1W
Vr
V,
----TL/L/904S-4
TL/Ll904S-3
Propagation Delay
Enable and Disable
,_-_-------3V
. . .------oV
INPUT
IN·PHASE
+-_
....t-----v,"
~+-
OU'PU' _ _ _
OUT OF PHASE
OUTPUT
'-----VOl
-----"'.
---------VOl
ENABLE,~:~
ISWtfft... ~
NORMALLY HIGH
OUTPUT
IS10PEN)
NORMALLY LOW
OUTPU'
(S! CLOSED'
~
..11'--
~v~------_
"'. -:--t-~....... -__-+"",_---' osv
''''
.
V"
"U
....::.::'-.!.:...:..!_...._ _ _ _ _ _ _..L:_....,.05V
TL/Ll904S-5
TLl1I904S-S
Notes:
CL includes probe and jig capacitance.
VT
=
1.5V.
In Ihe example above, Ihe phase relalionships between inpul and oulputs have been chosen arbilrarily.
All inpul pulses are supplied by generalors having Ihe following characleristics: PRR = I MHz, ZOUT =
son, I, :<:
5 ns,
It :<: 5 ns.
Ipo and IeLK are lesled wilh swilch 5, closed and CL = 50 pF.
For TRI·5TATE oulpuls, output enable times are lesled wilh CL = 50 pF 10 Ihe 1.5V level: 5, is open for high-impedance 10 HIGH lesls and closed for high.imped.
ance 10 LOW lesls. Outpul disable limes are lesled wilh CL = 5 pF. HIGH 10 high.impedance lesls are made 10 an oulpul vollage of VOH - 0.5V w~h 5, open.
LOW 10 high-impedance lests are made 10 Ihe VOL + 0.5V level wilh 5, closed.
368
Programmable Logic Design Guide
Programmable Array Logic Family Series 24BP
PAL20P8BNC
PAL20P8BJC
PAL20P8BJM
PAL20RP8BNC
PAL20RP8BJC
PAL20RP8BJM
TL/L/9046-23
PAL20RP4BNC
PAL20RP4BJC
PAL20RP4BJM
PAL20RP6BNC
PAL20RP6BJC
PAL20RP6BJM
TL/L/9046-24
TL/L/9046-25
PAL20P8BVC
PAL20RP8BVC
~
z: > _
<.)
<.)
0
-
PLASTIC
LEADED
CHIP
CARRIER
23
22
21
10
20
11
19
I/o
Q
<.)
-
-
z:
NC
>~ _
0'
NC
10
20
Q
11
19
Q
1::1
i!i
U
z:
IC
-
a
TL/L/9046-32
PAL20RP4BVC
0
-
-
<.)
~
:P _ ~
25
Q
24
I
PLASTIC
LEADED
CHIP
CARRIER
Q
22
NC
21
Q
20
11
19
12 13 I. 15 16 17 18
I I I I I I I
Q
U
z:
If.:)
I/o
24
23
10
i!i
Q
Q
0
25
9
Q
23
21
1
uz>_-::::::'
NC
24
22
PAL20RP6BVC
S
z
PLASTIC
LEADED
CHIP
CARRIER
TL/L/9046-31
u
<.)
25
I/O
NC
I/O
I/o
i!i
-
I/o
I/O
24
NC
TL/L/9046-26
PLASTIC
LEADED
CHIP
CARRIER
I
NC
Q
NC
21
Q
10
Q
11
Q
I
I
19
12 13 14 15 16 17 18
I I I I I I I
Q
:'5.
z: <.)
z:
TLlL/9046-33
'"
""
I/O
I
:'5.
TL/L/9046-34
369
New Product Data Sheets
Logic Diagram PAL20P8B
PIN
NUMBERS
PIN
NUMBERS
I
1
a
1
2
3
4
5
6
7
2~
FIRST O~
FUSE 80 40
NUMBERS 160 120
240
3
8 10 12 14
16 18 20 22
24 26 28 30 32 34 36 38
37 39
9 11 13 15
21 23
33 35
17 19
29 31
25 27
1
- 23
>$~
200
280
-
22
--1.
320
J~
J~
J~
J~
J~
600
4
640
920
5
960
1240
6
1280
1560
7
I
--1.
1600
1880
8
1920
,J
2566
2200
21
20
19
18
17
16
v
9
2240
J
-
2520
15
2567 V
10
14
11
13
I
a
r---<"'"
INCREMENT 1
Note: JEDEC Fuse Number
2
=
4
3
6
5
7
8 10 12 14
16 18
20 22
24 26 28 30 32 34 36 38
9 11 13 15
17 19
21 23
2527
29 31
3335
37 39
First Fuse Number
+ Increment.
TL/L/9046-7
370
Programmable Logic Design Guide
Logic Diagram PAL20RP4B
.... o 1 2 3
2 --I'TFIRST -ro-=
40
FUSE
to.
4 6
8 10 12 14 16 18 20.22 24 26 28 30 32 34 36 38
5 7 .9 11 13 15 17 19 21 23 25 27 29 31 33 35 3739
23
J
....
~!?
80
NUMBERS 160 120
200
240 280
3
320
-
600
4
2561
J....
I
I
22
21
640
~Fs? g~
~c
920
20
5
960
~!?
Po-
D
~~ DPo-
1240
6
1280
1560
7
19
18
1600
~I?D ~
1880
8
17
1920
2200
9
-
2566 ....
-
2567
2240
2520
10
11
.
r-----v'"
1 02
1 3
INCREMENT
4 6
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38
5 7
9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
.J....
I
I
16
15
14
l$!2 l.... I
::~
22
320
~I? Q30-
600
21
4
640
~!?
920
5
960
~ 20
D
>$!?D~
1240
6
19
1280
>$12 0~
1560
7
18
1600
>$I? QPo-
~880
8
17
1920
~!?g Po-
2200
16
9
2240
.l
-
2520
10
11
--o-.r
4 6
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38
,02
1 3
5 7
9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
INCREMENT
2567' .....
I
15
14
Lq-
13
TL/L/9046-9
Note: JEDEC Fuse Number
= First Fuse Number + Increment.
372
Programmable Logic Design Guide
Logic Diagram PAL20RP8B
2
FIRST
FUSE
NUMBERS
""
o
~
80
160
240
1
2
3
4
5
6
7
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38
9 11 13 15
17 19
21 23
25 27
29 31
33 35 37 39
23
40
>$I? g~
120
200
280
22
3
320
>$I?D$0-
600
4
21
640
>$!?zDPo...
920
5
20
960
~~
Po-
D
~~ PoD
>$!?s DPo~!?s DPo-
1240
6
1280
1560
7
1600
1880
8
1920
2200
9 -I
19
18
17
16
2240
~I?D Po-
2520
10
11
-I.
------v"I
,---- 0
INCREMENT
1
2
3
4
5
6
7
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38
17 19
21 23
25 27
29 31
33 35
37 39
9 11 13 15
15
14
------,
I [2]
>--1>0-,---1,7 [17 ] I/O
GNO [IIi]
10
t
11
[11]
I
GNO
[10]
t
[Pee P~ NUWBE'S]
10
t
11
[pee PIN NuweERS]
TL/Ll9391-10
[1]
I
[2]
[19]
I/o
e
[1]
I
[2] 2
I [
[4]
4
GNO
[10]
10
t
PAL16R8
1
I
G
TL/Ll9391-11
PAL16R6
c
[11]
I
11
[11]
G
l'---'-----~~~[P-CC-PI-NN-uw-e'-RS];'====~-...Jt
TL/Ll9391-12
1
[19]
Q
3] 3
[4] 4
GND [10] 10
11 [11]
l,--~----~~~[pc-e-PI-NN-u.-e'-05]-1--_-_-_-_..._---'t
G
TLlLl9391-13
New Product Data Sheets
383
20-Lead PCC Connection Conversion Diagram
0
~
0
:;
20-PIN
DIP PIN - - .
NUt.iBERS
0 0
3
<.>
[2J
0
,:;>
~
0
G B
0
0 I/O
0 I/o
G I/O
G I/O
G
0
0
10
o
or
Q
or
Q
or
Q
or
Q
I/O or Q
0 G G G 0
c
:z
~
0
e>
Ie>
0
0
:;
:;
~
~
0
TL/L/9391-14
Functional Description
(Continued)
Series-D Medium PAL devices reset all registers to a low
state upon power-up (active-low outputs assume high logic
levels if enabled). This may simplify sequential circuit design
and test. To ensure successful power-up reset, Vee must
rise monotonically until the specified operating voltage is
attained. During power-up, the clock input should assume a
valid, stable logic state as early as possible to avoid interfering with the reset operation. The clock input should also
remain stable until aiter the power-up reset operation is
completed to allow the registers to capture the proper next
state on the first high-going clock transition.
As with any TTL logic circuits, unused inputs to a PAL device should be connected to ground, VOL, VOH, or resistively to Vee. However, switching any input not connected to a
product term or logic function has no effect on its output
logic state.
Typical Registered Logic Function Without Feedback
~
)- ~D
...
~
A
Q~
... "-~~
~
~
TL/L/9391-15
384
Programmable Logic Design Guide
Typical Registered Logic Function With Feedback
>~
-
~
...
~
I-
.,
A.
0
Or-
----.
~ Q~
~
TL/Ll9391-16
CLOCK FREQUENCY SPECIFICATION
Register Preload Waveform
The clock frequency (fcud parameter specifies the maximum speed at which a registered PAL device is guaranteed
to operate. Clock frequency is defined differently for the two
cases in which register feedback is used versus when it is
not. In a data-path type application, where the logic functions fed into the registers are not dependent on register
feedback from the previous cycle (i.e.-based only on external inputs), the minimum required cycle period (fCLK- 1 without feedback) is defined as the greater of the minimum
clock period (tw high + tw low) and the minimum "data
window" period (tsu + tH). This assumes optimal alignment
between data inputs and the clock input. In sequential logic
applications such as state machines, the minimum required
cycle period (fCLK- 1 with feedback) is defined as tCLK +
tsu. This provides sufficient time for outputs from the registers to feed back through the logic array and set-up on the
inputs to the registers before the end of each cycle.
G~
Output Register Preload
The preload function allows the registers to be loaded asynchronously from data placed on the output pins. This feature
simplifies device testing since any state may be loaded into
the registers at any time during the functional test sequence. This allows complete verification of sequential logic
circuits, including states that are normally impossible or difficult to reach. Register preload is not an operational mode
and is not intended for board level testing because elevated
voltage levels are required. The programming system normally provides the preload capability as part of its functional
test facility.
The register preload procedure is as follows:
1. Vee is raised to 4.5V.
2. Registered outputs are disabled by raising output enable
(G) to VIH.
3. The desired data values are applied to all registered output pins (VIL = set, VIH = reset).
4. Pin 8 is pulsed to Vp, then back to VIL.
(Vp = 18.0V ± 0.5V)
5. Data inputs are removed from registered output pins.
S. G is lowered to VIL to enable registered outputs.
7. The desired data values are verified at all registered outputs (VOL = 1, VOH = 0).
Note: The minimum recommended time delay (to) between sUCCBssive input transitions (including the Vp pulse width on Pin 8) is 100 ns.
REGISTERED
vIH/VOH J!oj+
~
+1!oi+
~
~~ :~ 1~,,",_1__
0U_TP_UT
TL/L/9391-17
Note: Vp
~
18.0V ±0.5V, to min
~
100 ns
Security Fuse
A pair of security fuses are provided which, when programmed, inhibit any further programming or verifying operations. (Each fuse secures a different portion of the logic
array.) This feature prevents direct copying of proprietary
logic patterns. The security fuses should be programmed
only after programming and verifying all other device fuses.
Register preload is not affected by the security fuses.
Design Development Support
A variety of software tools and programming hardware is
available to support the development of designs using PAL
products. Typical software packages accept Boolean logic
equations to define desired functions. Most are available to
run on personal computers and generate JEDEC-compati·
ble "fuse maps". The industry-standard JEDEC format ensures that the resulting fuse-map files can be down-loaded
into a large variety of programming equipment. Many software packages and programming units support a large variety of programmable logic products as well. The PLANTM
software package from National Semiconductor supports all
programmable logic products available from National and is
fully JEDEC-compatible. PLAN software also provides automatic device selection based on the designer's Boolean
logic equations.
Detailed logic diagrams showing all JEDEC fuse-map addresses for the 20-pin Medium PAL family are provided for
direct map editing and diagnostic purposes. For a list of
current software and programming support tools available
for these devices, please contact your local National Semiconductor sales representative or distributor. If detailed
specifications of the PAL programming algorithm are needed, please contact the National Semiconductor Programmable Device Support Department.
New Product Data Sheets
Ordering Information
....- - - - - - Programmable Array Logic Family
. - - - - - - Number of Array Inputs
.....- - - Output Type:
H= Active High
L=Active Low
C= Complementary
R= Registered
X = Exclusive-OR Registered
P = Programmable Polarity
,....--- Number of Registered Outputs(or total outputs
SpeedjPower Version:
If non-registered)
No Symbol = 35 ns
A =25ns
A2 = 35 ns, Half Power
B = 15 ns
B2 = 25 ns, Half Power
D = 10 ns
rrr
P~c~~~~~rnp~~astic DIP
J = 20-Pln Ceramic DIP
V = 20~Lead Plastic Chip Carrier
Temperature RanQe:
C=Commerclal (OOC to +75OC)
M= Military (-55OC to +125OC)
PAL 16 R8 DNC
TL/U9391-1B
385
386
Programmable Logic Design Guide
Logic Diagram-PAL 16L8D
r PIN NUMBERS
,
1
~
PRODUCT LINE FIRST FUSE NUMBERS
PIN NUMBERS---,
INPUT LINE
NUMBERS
Vcc~
L
o
,
20
2 4 6 8 10 1214 1618 2022 2426 2830.J
1 3 5 7 9 11 1315 1719 2 123 2527 2931
00 32
64 96
128 160
192 224
r--.
L./
~
....
256 288
320 352
384 416
448 480
3
..
...
~
:-..
L./
/
..
:-..
'.-/
rJ.
16
...L....
15
rJ.
14
...L....
13
r-.l
12
~
....
2-
1280 1312
1344 1376
1408 1440
1472 1504
7
17
JI:
...~
~
r
...L
~
.2
r
1024 1056
1088 1120
1152 1184
1216 1248
6
18
JI:
~
768 800
832 864
896 928
960 992
5
.;:1.
/
512 544
576 608
640 672
704 736
4
19
~
...
2"
2
...L
/
....
.
£.
~
1536 1568
1600 1632
1664 1696
1728 1760
'"
./
~
8
r
~
.2
1792 1824
1856 1888
1920 1952
1984 2016
9
..
/
~
~
10--:1...
=
....
....
11
o
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31
JEDEC Logic Array Fuse Number = Product Line First Fuse Number
TLlL/9391-19
+ Input Line Number
New Product Data Sheets
Logic Diagram-PAL 16R4D
r PIN NUMBERS
,
r--
1
PRODUCT LINE FIRST FUSE NUMBERS
387
PIN NUMBERS----,
INPUT LINE
NUMBERS
Vee, ,
L 20
o
2 4 6 810 1214 1618202224262830.-..1
1 3 5 7 9 11 13151719212 325272931
00 32
64 96
128 160
192 224
2
>--D
...
-'.1---
... ~..,256 288
320 352
384 416
448 480
3
...
P-t>...
5
..
~
.-'...
.:ot.
768 800
832 864
896 928
960 992
~
~
~
~
.
1024 1056
1088 1120
1152 1184
1216 1248
6
~
" ...
... .:ot.
...
~
./
.so
~
1536 1568
1600 1632
1664 1696
1728 1760
8
..
10
17
~h
.-D Of-
~h
D
O~
~h
.-D Of-
~~
~
16
~
15
~
14
13
...
~I--
.:ot.
b1>-
12
.s;
~
--:::L
...
b-1)
1792 1824
1856 1888
1920 1952
1984 2016
9
...
~~~
r-
1280 1312
1344 1376
1408 1440
1472 1504
7
18
.so:t---
~
512 544
576 608
640 672
704 736
4
19
o
2 4 6 8 10 12 14 16 18 20 22 2426 2830
1 3 5 7 9 11 13 15 17 19 21 23 2527 29 31
L-<]o- 11
TL/L/9391-20
JEDEC Logic Array Fuse Number ~ Product Line First Fuse Number
+
Input Line Number
388
Programmable Logic Design Guide
Logic Diagram-PAL 16R6D
r
PIN NUMBERS
,
r--
1
PRODUCT LINE FIRST FUSE NUMBERS
PIN NUMBERS--,
INPUT LINE
NUMBERS
Vcc~
L
o
,
20
2 4 6 8 10 1214 1618 20222426 2830.J
1 3 5 7 9 11 1315 1719 21232 527 2931
00 32
64 96
128 160
192 224
2
b--l>-
..
....
~'I---
~
r_
256 288
320 352
384 416
448 480
3
4
~
./
~
512 544
576 608
640 672
704 736
"
~
...
~
~
768 800
832 864
896 928
960 992
5
~
j
1024 1056
1088 1120
1152 1184
1216 1248
6
"
~
...
~
~
1280 1312
1344 1376
1408 1440
1472 1504
7
~
j
1536 1568
1600 1632
1664 1696
1728 1760
8
"
~
~
....
~
1792 1824
1856 1888
1920 1952
1984 2016
9
10
>--D
...
18
~l
..-D Q-
..-D Q-
~l
.....-D Q-
..-D QI-
~~
~
17
~
16
~
15
~
14
~
13
12
11:.:1---
~
-----:::L
D Q-
~l
~
....~
..--
~l
~
~
;oe-~
~~
~
r
19
-v
o
2 4 6 8 10 12 14 1618 2022 24 26 2830
135791113151719212325272931
l-- 11
TL/L/9391-21
JEDEC Logic Array Fuse Number
~
Product Une First Fuse Number
+
Input Line Number
New Product Data Sheets
Logic Diagram-PAL 16R8D
r PIN NUMBERS
r-
,
1
PRODUCT LINE FIRST FUSE NUMBERS
389
PIN NUMBERS----,
INPUT LINE
NUMBERS
Vcc_
L
lo
,
20
2 4 6 8101214161820222426 2830..J
1 3 5 7 9 11 1315 1719 2 123 252 7 2931
2
00 32
64 96
128 160
192 224
r---....
V
~
~
...
256 288
320 352
384 416
448 480
3
'"
V
_....."""
768 800
832 864
896 928
960 992
V
....
_....."""
D
O~
~~
D
O~
'"
V
-.....
_...."""
~
~
.--
D 01--
.......
~
o
2 4 6 8 10 1214 1618 20222426 2830
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31
~
18
~
17
~
16
~
15
~
14
~.
13
~~
.----
./
. .:.t.
~
.---
~~
.:s;
:::t.
1792 1824
1856 1888
1920 1952
1984 2016
10
D 01-
.-./
1536 1568
1600 1632
1664 1696
1728 1760
9
-.....
~
~
.
~~
'"
1280 1312
1344 1376
1408 1440
1472 1504
8
D 01-
~~
.:s;
:::t.
7
.---
.-./
1024 1056
1088 1120
1152 1184
1216 1248
6
-.....
~
~
5
~~
.:s;
.:ot.
.
..
DOl-
V
19
~~
r---
512 544
576 608
640 672
704 736
4
...
~~~
D 01-
~~
~
12
L-<]o- 11
TL/Ll9391-22
JEOEC Logic Array Fuse Number = Product Line First Fuse Number
+ Input Line Number
390
Programmable Logic Design Guide
Physical Dimensions inches (millimeters)
0.985
~----------(25.~91----------~
MAX
0.005-0.020
(0.127-0.5081
HAD TYP
0.180
(4.5721
MAX
0.D55± 0.005
(1.397±0.127)
0.290-0.320
(7.3&&-8.'281~
GlASS SEAlANT
0.2110
(5.11801
MAX
0.150
(3.8101
MIN
0.D08-0.~2
(0.203 - 0.305)
t
IL
--11--
0.125-0.200
(3.175-5.080)
t
O.OI8±O.003 __
(0.457±O.D781
J20ACAEVMI
20-Pln Ceramic Dual-In-Llne Package (J)
NS Package Number J20A
1.013-1.040
(25.73-2&.421
0.092 X0.030
(2.337 X0.762)
MAXDP
=:1
0.210 ±0.005
(6.&04 .0.1271
PIN NO. IIDENT
~
(~:~::)~
MIN
1l:V
O.o32±O.o05
'f~~~~~17~1~.~'~56£14~~13~~1Z~'~1~---r
1.
PIN ND.IIDENT~
~~mm~~~~~~
,
OPTION 2
0.300-0.320
(7.120-1.121)
0.085
(1.851)
~~~++rT~~~~Tr~
--100 .0. 004
O.OOI-O.OlJJ
0.325 .::::
20
(0 .• 13±0.,2
RAD
(0.229-0.381)
TYP
0.010.0.005
11.52400.127)
0.0IltO.003
(0.45700.07&)
~~
°1
,
0.020
0.125-0.140 (0.508)
(3.175-3.55&)
MIN
(1.255 +1.811
~
-0.381
N20AIREV01
20-Pln Plastic Dual-In-Llne Package (N)
NS Package Number N20A
New Product Data Sheets
Physical Dimensions inches (millimeters) (Continued)
4 SPACES AT
0.050
(1.270)
5
(1.143)
0.04i1
x45°
0.080
(2.032)
DIANOM
U:~-r'-""T'--+----''- PEDESTAL
18
+=
~
15 0
VIEW A-A
14~
4 s~g: AT
(1.270)
11!
:1
0.226
~--*- (5.740)
NOM
SQUARE
0.310 -0.330
(7.874-8.382)
(CONTACT DIMENSION)
0.026-0.032
(0.660-0.813)
TYP
0.020
iD.5Oai
r-==1~~JtmlIrnttra~ff- ~~_~~
MIN
~~-~mJ
(0.127-0.381)
(0.813-1.016)
0.165-0.180
(4.191-4.572)
PIN NO.1
IDENT
0.385-0.395
(9.779-10.03)
SQUARE
20-Lead Plastic Chip Carrier Package (V)
NS Package Number V20A
V20A(REVJ)
391
New Product Data Sheets
Programmable Array Logic (PAL®)
24-Pin,Medium PAL Family-Series D
393
PRELIMINARY
February 1988
General Description
The 24-pin Medium PAL family contains four of the most
popular PAL architectures and Series-D is the highest
speed version available at this time with 10 ns maximum
propagation delay. National Semiconductor's advanced oxide isolated Schottky TIL process with titanium tungsten
fusible links provides high-speed user-programmable replacements for conventional SSIIMSI logic with significant
chip-count reduction.
Programmable logic devices provide convenient solutions
for a wide variety of application-specific functions, including
random logic, custom decoders, state machines, etc. By
programming fusible links to configure ANDIOR gate connections, the system designer can implement custom logic
as convenient sum-of-products Boolean functions. System
prototyping and design iterations can be performed quickly
using these off-the-shelf products. A large variety of programming units and software makes deSign development
and functional testing of PAL devices quick and easy.
The PAL logic array has a total of 20 complementary inputs
and 8 outputs generated by a single programmable ANDgate array with fixed OR-gate connections. Device outputs
are either taken directly from the AND-OR functions
Device Types
Part
Number
(combinatorial) or passed through D-type flip-flops (registered). Registers allow the PAL device to implement sequentlallogic circuits. TRI-STATEOl> outputs facilitate busing
and provide bidirectional 1/0 capability. The medium PAL
family offers a variety of combinatorial and registered output
mixtures, as shown in the Device Types table below.
On power-up, all registers are reset to simplify sequential
circuit design and testing. Direct register preload is aiso provided to facilitate device testing. Security fuses can be programmed to prevent direct copying of proprietary logic patterns.
Features
• 10 ns maximum propagation delay (combinatorial)
• User-programmable replacement for TIL logic
.. Large variety of JEDEC-compatlble programming
equipment and design development software
available
• Fuily supported by National PLAN™development
software
• Power-up reset for registered outputs
• Register preload facilitates device testing
• Security fuse prevents direct copying of logiC patterns
Block Diagram-PAL20R8
Registered
Dedicated
Combinatorial
Outputs
Inputs
(With Feedback)
1I0s Outputs
PAL20L8
14
-
6
2
PAL20R4
12
4
4
PAL20R6
12
6
2
PAL20R8
12
8
-
-
Speed/Power Versions
Series Example
Commercial
tpD
0
PAL20L8D
10ns
I
Icc
I 210mA
Military
tpD
I
Icc
15ns 1210mA
TRI-sTATE- is a registered trademark of National Semiconductor Corporation.
PLANTM Is a trademark of National Semiconductor Corporation.
PAL- Is a registered trademaric of and Is used under license trom Monolithic MemOrieS, Inc.
TL/Ll9394-1
394
Programmable Logic Design Guide
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (Vee)
-0.5V to + 7V (Note 2)
Input Voltage
-1.5V to + 5.5V (Note 2)
Off-State Output Voltage
-1.5V to + 5.5V (Note 2)
Input Current
-30 mA to + 5.0 rnA (Note 2)
Output Current (Iou
+100mA
Storage Temperature
-65·Cto + 150"C
Ambient Temperature with Power
Applied
Junction Temperature with Power
Applied
- 65°C to + 150°C
ESO Tolerance (Note 3)
2000V
CZAP = 100 pF
RZAP = 1500.0
Test Method: Human Body Model
Test Specification: NSC SOP-5-028
Recommended Operating Conditions
Symbol
Commercial
Military
Parameter
Units
Min
Nom
Max
Min
Nom
Max
5
5.5
4.75
5
5.25
V
75
·C
Vcc
Supply Voltage
4.5
TA
Operating Free-Air Temperature
-55
Tc
Operating Case Temperature
tw
Clock Pulse Width
0
·C
125
I
Low
10
5
8
5
ns
I
High
10
5
8
5
ns
15
7
10
7
ns
0
-5
0
-5
tsu
Setup TIme from Input
or Feedback to Clock
tH
Hold Time of Input after Clock
fClK
Clock Frequency
(Note 4)
I
I
ns
With Feedback
70
37
70
55.5
MHz
Without Feedback
100
50
100
62.5
MHz
Electrical Characteristics Over Recommended Operating Conditions
Symbol
Parameter
V,l
Low Level Input Voltage (Note 5)
V,H
High Level Input Volt8ge (Note 5)
--
Test Conditions
Min
Typ
Max
Units
0.8
V
2
V
V'C
Input Clamp Voltage
Vee = Min, 1= -18 mA
-1.5
V
I,l
Low Level Input Current (Note 6)
VCC = Max, V, = 0.4V
-0.25
mA
I'H
High Level Input Current (Note 6)
Vee = Max, V, = 2.4V
25
p.A
I,
Maximum Input Current
Vce = Max, V, = 5.5V
200
p.A
VOL
Low Level Output Voltage
Vee = Min
0.5
V
VOH
High Level Output Voltage
Vee = Min
10l = 12mA
MIL
10l = 24mA
COM
IOH=-2rnA
MIL
10H = -3.2mA
COM
10Zl
Low Level Off-State Output
Current (Note 6)
Vee = Max
Vo = 0.4V
10ZH
High Level Off-State Output
Current (Note 6)
Vee = Max
Vo = 2.4V
los
Output Short-Circuit Current
(Note 7)
Vee = 5V, Vo = OV
lee
Supply Current
Vee _= Max, Outputs Open
2.4
V
-30
160
-100
p.A
100
p.A
-130
mA
210
mA
New Product Data Sheets
395
Nole 1: Absolute maximum ralings are those values beyond which the device may be permanently damaged. Proper operation is not guaranteed outside the
specified recommended operating conditions.
Note 2: Some device pins may be raised above these limits during programming and preload operations according to the applicable specification.
Nole 3: It Is recommended Ihal precautions be taken to minimize electrostatic discharge when handling and testing this product Pins 1 and t3 (DIP) are connected
direcUy to the security fuses, and although the input circuitry can withstand the specified ESD conditions, the security fuses may be damaged preventing
subsequent programming and verification operations.
Nole 4: fClK with feedback is derived as (1clK + tSU) -1.
fClK without feedback is derived as (21w) -1.
Note 5: Thase are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and/or tester noise. Do not attempt to
test these values without suitable equipment.
Nole 6: Leakage current for bidirectionai 1/0 pins is the worst case between III and 10Zl or between IIH and 10ZH.
Note 7: To avoid invalid readings in other parameter tests it is preferable to conduct the los fest last To minimize internal heating, only one output should be
shorted at a time with a maximum duration of t.O sec. each. Prolonged shorting of a high output may raise the chip temperature above normal and permanent
damage may result
Switching Characteristics Over Recommended Operating Conditions
Symbol
Parameter
Military
Test Conditions
Min
Commerlcal
Typ
Max
7
Min
Units
Typ
Max
15
7
10
ns
5
12
5
8
ns
tpD
Input or Feedback to
Combinatorial Output
CL
= 50 pF, 51 Closed
!eLK
Clock to Registered
Output or Feedback
CL
= 50 pF, 51 Closed
tPZXG
G Pin to Registered
Output Enabled
CL = 50 pF, Active High: 51 Open,
Active Low: 51 Closed
8
15
8
10
ns
tpXZG
G Pin to Registered
Output Disabled
CL = 5 pF, from VOH: 51 Open,
from VOL: 51 Closed
7
15
7
10
ns
tPZXI
Input to Combinatorial Output
Enabled via Product Term
CL = 50 pF, Active High: 51 Open,
Active Low: 51 Closed
8
15
8
10
ns
tpXZI
Input to Combinatorial Output
Disabled via Product Term
CL = 5 pF, from VOH: 51 Open,
from VOL: 51 Closed
7
15
7
10
ns
tRESET
Power-Up to Registered
Output High
600
1000
600
1000
ns
Test Load
Schematic of Inputs and Outputs
5V~
EQUIVALENT INPUT
V~o------1
51
TYPICAl. OUTPUT
__------------------------------'--oV~
Rl
40.11. NOM.
OUWUT--------.----t
R2
INPUT
0--1-1--+.--+---
TL/Ll9394-2
MIL
Rt
R2
COM'L
= 390
= 750
Rt
R2
= 200
= 390
L-.f-+-o
OUTPUT
Tl/l/9394-7
396
Programmable Logic Design Guide
Test Waveforms
Set-Up and Hold
Pulse Width
L,-----3v
DATA ----=~.I.I""'..:..~II.F=---3V
INPUT
OV
TUU9394-3
LOW-LEVEL
PULSE INPUT
Propagation Delay
INPUT
IN-PHASE
OUTPUT
(SI CLOSED)
OUT OF PHASE
OUTPUT
(51 CLOSED)
Ilvr
3V
... tpLH 1-'" tpHL I-
ENABLING INPur
OV
VOH
Vr
VOL
... tpHL 1-'" tpLH IVT
Vr
3V
OV
3V
V
OV
TUL/9394-5
Enable and Disable
Vr
Vr
8
HIGH-LEVEL
PULSE INPUT
CLOCK - - - - - - - I . j - 2 - : : - - - - - 0 V
VOH
Vr
VOL
~,,.-------~~----~
~'I~V~T--EN_AB_L_E--~~I,~D_I~-BL_E_~
NORMALLY HIGH VOH -tt,.-------k/----L. O•5V
OUTPUT
Z
(51 OPEN)
NORMALLY LOW
Z
OUTPUT
(51 CLOSED) VOL
TL/L/9394-4
TLIU9394-6
Notes:
VT
1.5V
CL includes probe and jig capacitance.
In lhe examples above, lhe phase relationships be1ween InpUlS and oulpu1s
have been chosen arbi1rarily.
~
Switching Waveforms
REGISTERED
OUTPUTS
::~::~::t::::~:*--.:....--1t::::X:::::::=
ANY INPur _ _+-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _" " ' _ - -....... ".---~
PROGRAMMED
FOR TRI-STATE CONTROL --+--~--""":'-------------~.."I---.....'I...._ : _ - - COMBINATORIAL
OUTPUTS
:::::::]~~t::::::::::::::::j-----~
TL/L/9394-8
Power-Up Reset Waveform
5V
Vee
OV----
REGISTEREDVOH
OUTPUTS
VOL
'-1..,..'7""7..,...,..,...,...,..,...,...,..,"'*---------
INTERNAL REGISTERS RESET TO LOGIC 0
VIH
CLOCK'
TUL/9394-9
'The clock input should nol be swi1ched from low 10 high until after limelRESET.
New Product Data Sheets
397
Functional Description
All of the 24-pin Medium PAL logic arrays consist of 20 complementary input lines and 64 product-term lines with a programmable fuse link at each intersection (2560 fuses). The
product terms are organized into eight groups of eight each.
Seven or eight of the product terms in each group connect
into an OR-gate to produce the sum-of-products logic function, depending on whether the output is combinatorial or
registered.
An unprogrammed (intact) fuse establishes a connection
between an input line (true or complement phase of an array input signal) and a product term; programming the fuse
removes the connection. A product term is satisfied (logically true) while all of the input lines connected to it (via unprogrammed fuses) are in the high logic state. Therefore, if
both the true and complement of at least one array input is
left connected to a product line, that product term is always
held in the low logic state (which is the state of all product
terms in an unprogrammed device). Conversely, if all fuses
on a product term were programmed, the product term and
the resulting logic function would be held in the high state.
The medium PAL family consists of four device types with
differing mixtures of combinatorial and registered outputs.
The 20L8, 20R4, 20R6 and 20R8 architectures have 0, 4, 6
and 8 registered outputs, respectively, with the balance of
the 8 outputs combinatorial. All outputs are active-low and
have TRI-8TATE capability.
Each combinatorial output has a seven product-term logic
function, with the eighth product term being used for
TRI-STATE control. A combinatorial output is enabled while
the TRI-STATE product term is satisfied (true). Combinatorial outputs also have feedback paths from the device pins
into the logic array (except for two outputs on the 20L8).
This allows a pin to perform bidirectional 1/0 or, if the associated logic function were left unprogrammed, the output
driver would remain disabled and the pin could be used as
an additional dedicated input.
Registered outputs each have an eight product-term logic
function feeding into a D-type flip-flop. All registers are triggered by the high-going edge of the clock input pin. All registered outputs are controlled by a common output enable
(G) pin (enabled while low). The output of each register is
also fed back into the logic array via an internal path. This
provides for sequential logic circuits (state machines, counters, etc.) which can be sequenced even while the outputs
are disabled.
Series-D Medium PAL devices reset all registers to a low
state upon power-up (active-low outputs assume high logic
levels if enabled). This may simplify sequential circuit design
and test. To ensure successful power-up reset, Vcc must
rise monotonically until the specified· operating voltage is
attained. During power-up, the clock input should assume a
valid, stable logic state as early as possible to avoid interfering with the reset operation. The clock input should also
remain stable until after the power-up reset operation is
completed to allow the registers to capture the proper next
state on the first high-going clock transition.
As with any TTL logic circuits, unused inputs to a PAL device should be connected to ground, Val, VOH, or resistively to VCC. However, switching any input not connected to a
product term or logic function has no effect on its output
logic state.
CLOCK FREQUENCY SPECIFICATION
The clock frequency (fClK) parameter specifies the maximum speed at which a registered PAL device is guaranteed
to operate. Clock frequency is defined differently for the two
cases in which register feedback is used versus when it is
not. In a data-path type application, where the logic functions fed into the registers are not dependent on register
feedback from the previous cycle (i.e., based only on external inputs), the minimum required cycle period (fClK- 1 without feedback) is defined as the greater of the minimum
clock period (tw high + tw low) and the minimum "data
window" period (tsu + tH). This assumes optimal alignment
between data inputs and the clock input. In sequential logic
applications such as state machines, the minimum required
cycle period (fClK- 1 with feedback) is defined as tClK +
tsu. This provides sufficient time for outputs from the registers to feed back through the logic array and set-up on the
inputs to the registers before the end of each cycle.
398
Programmable Logic Design Guide
24-Pin Medium PAL Family Block Diagrams-DIP Connections
PAL20LB
GND [,.]
PAL20R4
.NO [14]
12
t
13
12
t
[pcc ,. NUM.ERS]
[PCCPIN NUMBERS]
PAL20R8
,
C[2] ,
, [3] 2
, [3] 2
[2]
G
t
TLlLl9394-11
TL/L/9394-10
PAL20R6
c
[,.]
[,,] '/0
, [.]
3
[26]
Q
[23]
Q
, [.] •
, [0] •
[7]
[23]
Q
, [.] 7
I [0]
GIl. [,.]
tL _ _ _---1[PCC
·GtlD [14]
PIt
7
12
tL__L._=-_-_-_-~[""-"'-NU-M-.ER-S]t_-____-1_----'
,"',,"']1------'
TLlLl9394-12
TLlL/9394-13
New Product Data Sheets
399
28-Lead PCC Connection Conversion Diagram
CI
...,;;
24-PIN
r.l r:1 r.l
DIP PIN --. t!.J I!..J L.!..J
NUMBERS
Ne
I
III
5
[ill
I
[II
6
~ I/O or Q
I/}]
7
[ill
I/O or Q
28-L£AD PCC
Ne
Ne
(TOp VIEW)
21
1m
1m
I/O or Q
1m I/o or
Q
[!TII/O or Q
1m I/o or
11
-;;
Q
CI
,<0
Tl/L/9394-14
Typical Registered Logic Function Without Feedback
>.A.
~
....
r--~D
0_
~l
~
TUU9394-15
Typical Registered Logic Function With Feedback
-
)- _0
...
..
~
~
...
Qf--
~~
~
TL/L/9394-16
400
Programmable Logic Design Guide
Output Register Preload
array.) This feature prevents direct copying of proprietary
logic patterns. The security fuses should be programmed
only after programming and verifying all other device fuses.
Register preload is not affected by the security fuses.
The preload function allows the registers to be loaded asynchronously from data placed on the output pins. This feature
simplifies device testing since any state may be loaded into
the registers at any time during the functional test sequence. This allows complete verification of sequential logiC
circuits, including states that are normally impossible or difficult to reach. Register preload is not an operational mode
and is not intended for board level testing because elevated
voltage levels are required. The programming system normally provides the preload capability as part of its functional
test faCility.
Design Development Support
A variety of software tools and programming hardware is
available to support the development of designs using PAL
products. Typical software packages accept Boolean logic
equations to define desired functions. Most are available to
run on personal computers and generate JEDEC-compatible "fuse maps". The industry-standard JEDEC format ensures that the resulting fuse-map files can be down-loaded
into a large variety of programming equipment. Many software packages and programming units' support a large variety of programmable logic products as well. The PLANTM
software package from National Semiconductor supports all
programmable logic products available from National and is
fully JEDEC-compatible. PLAN software also provides automatic device selection based on the designer's Boolean
logic equations.
The register preload procedure is as follows:
1. Vee is raised to 4.5V.
2. Registered outputs are disabled by raising output enable
(G) to VIH.
3. The desired data values are applied to all registered output pins (VIL = set, VIH = reset).
4. DIP pin 8 (PCC pin 10) is pulsed to Vp, then back to VIL.
(Vp = 18.0V ± 0.5V).
5. Data inputs are removed from registered output pins.
Detailed logic diagrams showing all JEDEC fuse-map addresses for the 24-pin Medium PAL family are provided for
direct map editing and diagnostic purposes. For a list of
current software and programming support tools available
for these devices, please contact your local National Semiconductor sales representative or distributor. If detailed
specifications of the PAL programming algorithm are needed, please contact the National Semiconductor Programmable Device Support Department.
6. G is lowered to VIL to enable registered outputs.
7. The desired data values are verified at all registered outputs (VOL
= I, VOH = 0).
Not.: The minimum recommended time delay (10) between successive Input
transHions Oncluding the vp pulse width on DIP pin 8) is 100 ns.
Security Fuse
A pair of security fuses are provided which, when programmed, inhibit any further programming or verifying operations. (Each fuse secures a different portion of the logic
Register Preload Waveform
- vIL
G
RE~~~~~
VIH~
vIH/VOH
vIL/VOL
tD
11-.....;.;...--
DIP PIN 8
PCC PIN 10
VIL
TUL/9394-17
Nota: vp
= 18.0V ±O.5V, to min. = 100 ns
New Product Data Sheets
Ordering Information
. - - - - - - - Programmable Array Logic Family
r - - - - - Number of Array Inputs
r----Output Type:
H = ACtlV8 High
L=Acllve Low
C= Complementary
R= Registered
X= Exclusive-OR Registered
P = Programmable Polarity
.----Number of Registered Outputs(or total outputs
Speed/Power Version:
If non-registered)
No Sy mbol = 35 ns
A =25ns
A2 = 35 ns, Half Power
B = 15 ns
B2 = 25 ns, Half Power
D 10 ns
frr
=
P~c~~~~~,"PPiastlc DIP
J = 24-Pln Ceramic DIP
V = 28-Lead Plastic Chip Carrier
Temperature Ranqe:
C= Commercial (OOC to +75OC)
Iol = Iolllitary (-55OC to +125OC)
PAL20R8DNC
TL/Ll9394-18
401
402
Programmable Logic Design Guide
Logic Diagram-PAL20L8D
r--- DIP PIN NUMBERS
~
~
DIP PIN NUI.4B~RS::-l
INPUT LINE
NUI.4BERS
PRODUCT LINE FIRST FUSE NUI.4BERS
C~
o
2 4 6 8 10 1214 161820222426283032343638-.J
1 3 5 7 9 11 13 15 17 19 21 23 2527 29 31 33 35 37 39
2: -
~
00 40
80
160 120
240 200
280
3
~
'-"
.ot.
~
'-"
..ot.
r
~
A
~
~
"
~
12~
rJ..
18
rJ..
17
rJ..
16
v
...
.~
2240 2280
2320 2360
2400 2440
2480 2520
.ot
19
.So.
..ot.
11
,.J.
.So.
..ot.
.ot.
'""
P
1920 1960
2000 2040
2080 2120
2160 2200
10
20
... '""
.ot.
r
..l
~
1600 1640
1680 1720
1760 1800
1840 1880
9
21
...
i"---..
.ot.
8
r-l
v
f-/
1280
.
1360 1320 .
1440 1400
1520 1480
1560
7
22
'""
i"---..
960
1040 1000
1120 1080
1200 1160
1240
6
23
~
640 680
720 760
800 840
880 920
5
r-l
~
.So
320 360
400 440
480 520
560 600
4
I
...
~
24
i"---..
f-/
... ...'""
.So
0 2 4 6 810121416 18 20 22 24 26 28 30 3234 3638
1 3 5 7 9111315171921232527293133353739
,.J.
15
14
13
TVL/9394-19
JEDEC Logic Array Fuse Number = Product Una First Fuse Number
+ Input Line Number
New Product Data Sheets
403
Logic Diagram-PAL20R4D
.----OIP PIN NUMBERS
r--- PRODUCT LINE FIRST FUSE NUMBERS
~
-
H>
INPUT LINE
NUMBERS
0 2 4 6 810121416182022242628303234 363S-.l
1 3 5 7 9 11 1315 1719 21232527293133353739
~
2: -
~
~
~
..
~
.::t.
640 680
720 760
800 840
880 920
5
~
~
.s;.
~
960
1040 1000
1120 1080
1200 1160
1240
i"""'o..
i-'"
::.t.
6
~
~
~
~
~
~
1920 1960
2000 2040
2080 2120
2160 2200
~
~
~
~
::.t.
11
~
12
----"l
21
r;o~~
20
~l
r--
o
Ot-
~~
~
19
,..-o 01-
~
18
-o 01- ~,
17
~~
16
~
2240 2280
2320 2360
2400 2440
2480 2520
10
22
~~
~
1600 1640
1680 1720
1760 1800
1840 1880
9
...
i"""'o..
.::t.
8
23
~
1280 1320
1360 1400
1440 1480
1520 1560
7
24
~
320 360
400 440
480 520
560 600
4
C~
...
~
00 40
80
160 120
240 200
280
3
DIP PIN NUMB~RS::-l
.s;.
o
2 4 6 8 10 121 4 161 8 2022 2426 28 30 32 34 3638
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
15
14
l
family. It provides several new features which will dramatically benefit PAL users.
A registered asynchronous (RA) cell is shown below which
is the basic element of this elegant PAL. The PAL16RA8 is
composed of 8 RA cells.
This device is housed in a 20-pin 300 mil DIP. A 20-pin PCC
package is also available. It can be programmed by most
PAL programmers.
•
•
•
•
•
•
•
•
409
Programmable asynchronous set and reset
Individually programmable clocks
Programmable and hard-wired TRI-STATEIII> outputs
Programmable output polarity
Registers can be bypassed individually
Register preload guarantees testabilitY
Outputs can be reconfigured as inputs
Security fuse for design secrecy
RA Cell Configuration
PL
OE
o
TULl9253-1
Ordering Information
, . . . - - - - - - - - - PROGRAMABLE ARRAY LOGIC F'AMILY
, . . . - - - - - - - - NUMBER OF' ARRAY INPUTS
, . . . - - - - - - - OUTPUT TYPE
RA REGISTER ASYNCHRONOUS
fr=
~
1
PAL 16 RA 8 NC
TRI-STATE. is a registered trademark of National Semiconductor Corporation
PALe is a registered trademark of and used under license with Monolithic Memories. Inc.
=
NUMBER OF' OUTPUTS
PACKAGE TYPE
N PLASTIC DIP
J CERAMIC DIP
V PLASTIC LEADED CHIP CARRIER (PLC)
=
=
=
TEMPERATURE RANGE
C=O TO +7S"C
M=-55 "C TO +125"C
TL/L/9253-2
410
Programmable Logic Design Guide
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Oper,atlng
Programming
Supply Voltage Vee
7.0V
12.0V
5.5V
22.0V
Input Voltage
Operating
Programming
Off-State Output Voltage
5.5V
12.0V
- 65·C to + 150"C
Storage Temperature
ESD Tolerance (Note 2)
>1000V
CZAP = 100pF
RZAP = 15000
Test Method: Human Body Model
Test Specification: NSC SOP-5-028
Operating Conditions
Symbol
Military
Parameter
Min
Commercial
Typ
Max
Min
5.5
Units
Typ
Max
5.25
Vee
Supply Voltage
4.5
5
4.75
5
tw
Width of Clock
25
13
20
13
ns
lwp
Preload Pulse Width
45
15
35
15
ns
tsu
Setup Time for Input or Feedback to Clock
25
10
20
10
ns
tsup
Preload Setup Time
30
5
25
5
ns
tH
Hold Time
10
-2
10
-2
0
-6
0
-6
30
5
25
5
thp
I
I Polarity Fuse Blown
Polarity Fuse Intact
Preload Hold Time
TA
Operating Free-Air Temperature
Te
Operating Case Temperature
-55
ns
ns
75
0
V
·C
·C
125
Electrical Characteristics Over Operating Conditions
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
0.8
V
VIL
Low-Level Input Voltage
(Note 3)
VIH
High-Level Input Voltage
(Note 3)
Vie
Input Clamp Voltage
Vee = Min
11= -18mA
-0.8
-1.5
V
IlL
Low-Level Input Current
Vee = Max
VI = O.4V
-0.02
-0.25
mA
IIH
High-Level Input Current
Vee = Max
VI = 2.4V
25
p.A
II
Maximum Input Current
Vee = Max
VI = 5.5V
1
mA
VOL
Low-Level Output Voltage
Vee = Min
IOL=8mA
0.5
V
VOH
High-Level Output Voltage
Vee = Min
10H: Mil-2 mA
loz
Off-State Output Current
Vee = Max
(Note 4) Vo = 0.4 or 2.4V
-100
,100
p.A
los
Output Short-Circuit Current
Vee = 5V
(Note 5)
-30
-70
-130
mA
lee
Supply Current
135
170
mA
V
2.0
0.3
Com-3.2mA
Vo= OV
2.4
Vee = Max
V
2.8
Nate 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may be operated at
these values,
Nate 2: It is recommended that precautions be taken to minimize electrostatic discharge when handling and testing Ihls product. Pins 1 and 11 are connected
dlrectiy to the securily fuses, and, although Ihe Input clrcuilry can withstand the specHled ESO conditions, the security fuses may be damagad preventing
subsequent programming and verification operations.
Nale 3: These are absolute voltages with respect to the ground pin on the device and include all overshoots due 10 system andlor tester noise. Do not attempt \0
test these values without suitable equipment.
Nate 4: 110 leakage as the worst case ollozx or IIX, e.g. III and IOZl.
Note 5: During lOS measurement oniy one output at a time should be grounded. Permanant damage otherwise may result.
New Product Data Sheets
411
Switching Characteristics Over Operating Conditions
Symbol
tpo
Test
Conditions
Parameter
Military
Min
I Polarity Fuse Intact
I Polarity Fuse Blown
Input or Feedback to Output
10
Commercial
Typ
Max
20
25
Min
Units
Typ
Max
35
20
30
40
25
35
telK
Clock to Output or Feedback
17
35
17
30
t5
Input to Asynchronous Set
22
40
22
35
ns
tR
Input to Asynchronous Reset
27
45
27
40
ns
tpzx
Pin 11 to Output Enable
10
25
10
20
ns
R1 = 5600
R2 = 1.1 KO
10
ns
ns
tpxz
Pin 11 to Output Disable
10
25
10
20
ns
tpzx
Input to Output Enable
18
35
18
30
ns
tpxz
Input to Output Disable
15
35
15
30
fMAX
Maximum Frequency
16
20
35
ns
MHz
Switching Test Load
Schematic of Inputs and Outputs
TYPICAL OUTPUT
EQUIVALENT INPUT
Vee
35
0---""""1'"""--- •• •-----....-0 Vee
40D. NOM
•••
INPUT
o-....-+--t.....- •. •
OUTPUT
••• --""""1,....,
TL/L/9253-4
..- ••• ----~--t
~--t--
TL/L/9253-3
Definition of Waveforms
'"':_i...;.._______________I,.-----.. .
i---tpo:a
_l-tPXZj
1tpZ----<
I
LU
PI
c:::
)
I
lhp
~p:j
I
TULl9253-14
Pin Configuration
Dual-In-Llne Package
=
20
Pi:
Va:
10
RA CELL
II
RA CELL
12
RA CELL
13
RA CELL
I.
RA CELL
15
RA CELL
16
RA CELL
17
RA CELL
GNO
V20PCC
10
19
18
17
16
15
I.
13
52
Iii >8 0
0
00
01
12
18
01
02
13
17
02
14
16
03
15
15
04
14
05
03
a.
16
05
8
06
co
!::: ~ I::: ....
0
0
12
07
11_
OE
'"
TL/L/9253-16
TL/L/9253-15
Order Number PAL 16RA8
See Package Number J20A, N20A and V20A
Programmer/Development Systems
The following list is some of the manufacturers of Programmer/Development Systems. Call them to see if they currently support
this device.
Programmers
Adv. Micro. Sys.
Bytek Compo Sys.
Citel
DATA 110
Digelec
Digital Media
GTEK Inc.
Int. Microsys.
Kontron
Logical Devices
Oliver Adv. Eng.
Pro-Log
Stag
PROMAC
Storey Systems
Structured Design
Sunrise
Valley Data Sci.
Varix
PCADSys.
Nat. Semi.
Software Development
DATA 110
414
Programmable Logic Design Guide
Logic Diagram
JEDEC PRODUCT
LINE #
INPUT LINE
#
65".2
....325611_~
286
320
..0
575"1I_~
670406.
736
6676611_~
0342
544
672
696
926
960
992
10"II_~
".
1056
1088
1120
1152
11804
1216
"601l_~
1312
1344
1376
1408
1440
'472
1504
153611_~
1568
1600
1632
1664
1696
1728
1760
1179211_~
656
1824
1920
1952
1984
2016
Note: Fuse Number = JEDEC Product Line #
+
Input Lina #
TLlLl9253-17
415
New Product Data Sheets
Physical Dimensions inches (millimeters)
0.9B5
~-----------(25.019)-----------;~
MAX
O.IBO
(4.572)
.- 0.020-0.060
0.290 - 0.320
(7.36&-B.'2B)~
MAX
GLASS SEALANT
10.508 1.524)
0.200
(5.DBO)
MAX
0.125-0.200
13.175 - 5.0BO)
O.ODB - 0.012 8 6 ' J 9 '
(0.203 -0.305)
I.-
0.310- 0.410
17.B74 10.41)
--.I
t
II_
II
0.0IB±0.003 __
10.457±0.076)
0.060
(1.524)
MAX
BOTH ENOS
J20A(REVMI
Ceramic Dual-in-Line Package (J)
NS Package Number J20A
1.013-1.040
125.73-26.42)
0.092 X 0.030
(2.337 X 0.762)
::::1
(0.BI3±0.127)
0.260 ±0.005
(6.604 ±0.127)
PIN NO. llDENT
19
0.032±0.005~O
,~~====~~I=J~16~=15===I'==I='~1=2==1='~
,
-/
MAXDP
RAD
PIN NO.1IDENT~
~rrrrmm~~~rnm~~
I
OPTION 2
0.065
11.651)
~·~~~"rroH,,~,,~
0.009-0.01JJ
10.229-0.3B1)
TYP
0.325
:~:~
O.DBO 00.005
11.524<0.127)
-90',0.004°
I 0.100.0.010 I
I-- (2.54000.254)--j
I
I-
0.018>0.003
10.457<0.076)
~~
I
0.125-0.140
(J.175-J.556/
0.020
10.50B)
MIN
'8.255 +1.016)
~
-UBI
N20ACREVGl
Molded Dual-In-Llne Package (N)
NS Package Number N20A
416
Programmable Logic Design Guide
Physical Dimensions inches (millimeters) (Continued)
4 SPACES AT
0.050
(1.270)
ir
(1.143)
045
x45°
O·
IF_+..,.....-+---L..
0.080
(2.032)
DlA NOM
PEDESTAL
~
15 0
~I
VIEW A-A
0.226
(5.740)
NOM
SQUARE
0.310-0.330
(7.874-8.382)
(CONTACT DIMENSION)
0.013-0.018
(0.330 -0.457)
TYP
0.020
~(0.508)
__
0.005-0.015
(0.127 -0.381)
' ' ' ;' ' ;':=__''1+-+_
MIN
0.032-0.040
(0.813-1.016)
0.165-0.180
(4.191-4.572)
0.385-0.395
(9.779-10.03)
SQUARE
Plastic Chip Carrier Pkg (V)
NS Package Number V20A
V20A (REV J)
New Product Data Sheets
Programmable Array Logic PAL20RA10
General Description
Features
The PAl20RA10 is a new member of National's broad PAL
family. It provides several new features which will dramatically benefit PAL@ users.
•
•
•
•
•
•
•
•
A registered asynchronous (RA) cell is shown below which
is the basic element of this elegant PAL. The PAL20RA lOis
composed of lORA cells.
This device is housed in a 24-pin 300 mil DIP. A 28-pin PCC
package is also available. It can be programmed by most
PAL programmers.
417
October 1987
Programmable asynchronous set and reset
Individually programmable clocks
Programmable and hard-wired TRI-STATE@ outputs
Programmable output polarity
Registers can be bypassed individually
Register preload guarantees testability
Outputs can be reconfigured as inputs
Security fuse for design secrecy
RA Cell Configuration
PL
OE
o
TL/Ll8702-1
Ordering Information
, - - - - - - - - - PROGRAMABLE ARRAY LOGIC FAMILY
. . . - - - - - - - - - - NUMBER OF ARRAY INPUTS
r.:
1=
. - - - - - - - - - OUTPUT TYPE
RA = REGISTER ASYNCHRONOUS
NUMBER OF OUTPUTS
PACKAGE TYPE
N = PLASTIC DIP
J = CERAMIC DIP
V = PLASTIC LEADED CHIP CARRIER (PLC)
1
PAL20RA10NC
TRI..sTATE~ Is 8 registered trademark of National Semiconductor Corporation
PAlalls a registered trademark of and used under license with Monolithic Memories, Inc.
TEMPERATURE RANGE
C=O TO +75"C
M=-550C TO +125 0C
TL/L/8702-22
418
Programmable Logic Design Guide
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating
Programming
Supply Voltage Vcc
7.0V
12.0V
Input Voltage
5.5V
22.0V
Operating
Programming
5.5V
12.0V
-65·Cto + 150·C
>1000V
Off-State Output Voltage
Storage Temperature
ESO Tolerance (Note 2)
CZAP = 100 pF
RZAP = 15000
Test Method: Human Body Model
Test Specification: NSC SOP-5-028
Operating Conditions
Symbol
Commercial
Military
Parameter
Units
Min
Typ
Max
Min
Typ
Max
5.5
4.75
5
5.25
Vcc
Supply Voltage
4.5
5
tw
Width of Clock
25
13
20
13
ns
twp
Preload Pulse Width
45
15
35
15
ns
tsu
Setup Time for Input or Feedback to Clock
25
10
20
10
ns
tsuP.
Preload Setup Time
30
·5
25
5
ns
10
-2
10
-2
0
-6
0
-6
30
5
25
5
tH
Hold Time
I Polarity Fuse Intact
I Polarity Fuse Blown
thp
Preload Hold Time
TA
Operating Free-Air Temperature
Tc
Operating Case Temperature
-55
0
V
ns
ns
75
·C
·C
125
Electrical Characteristics Over Operating Conditions
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
0.8
V
VIL
Low-Level Input Voltage
(Note 3)
VIH
High-Level Input Voltage
(Note 3)
VIC
Input Clamp Voltage
Vee = Min
11= -18mA
IlL
Low-Level Input Current
Vee = Max
VI = O.4V
IIH
High-Level Input Current
Vee = Max
VI = 2.4V
25
".A
II
Maximum Input Current
Vcc = Max
VI = 5.5V
1
mA
0.5
V
V
2.0
VOL
Low-Level Output Voltage
Vcc = Min
10L = 8mA
VOH
High-Level Output Voltage
Vee = Min
IOH:MiI-2mA Com-3.2mA
2.4
-0.8
-1.5
V
-0.02
-0.25
mA
0.3
loz
Off·State Output Current
Vee = Max
(Note 4) Vo = 0.4V or 2.4V
-100
los
Output Short-Circuit Current
Vcc = 5V
(Note 5)
-30
Icc
Supply Current
Vee = Max
VO= OV
2.8
V
100
".A
-70
-130
mA
155
200
mA
Note 1: Absolute maximum ratings are those values beyond which the deVice may be permanently damaged. They do not mean that the device may be operated at
these values.
Note 2: It is recommended that precautions be taken to minimize electrostatic discharge when handling and testing this product. Pins 1 and 13 are connected
directly to the security fuses, and. although the input circuitry can withstand the specified ESD conditions, the security fuses may be damaged preventing
subsequent programming and verification operations.
Note 3: These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and/or tester noise. Do not attempt to
test these values without suitable equipment.
Note 4: I/O leakage as the worst case of lozx or I,X, e.g. I,L and 10ZL.
Nole 5: During lOS measurement only one output at a time should be grounded. Permanent damage otherwise may result.
New Product Data Sheets
419
Switching Characteristics Over Operating Conditions
Symbol
tpD
Test
Conditions
Parameter
Military
Min
Units
Typ
Max
35
20
30
25
40
25
35
Max
20
I Polarity Fuse Intact
I Polarity Fuse Blown
Input or Feedback to Output
Commercial
Typ
Min
tCLK
Clock to Output or Feedback
17
35
17
30
ns
ts
Input to Asynchronous Set
22
40
22
35
ns
tR
Input to Asynchronous Reset
27
45
27
40
ns
10
R1 = 560n
R2 = 1.1 Kn
10
ns
tpzx
Pin 13 (DIP) to Registered Output Enable
10
25
10
20
ns
tpxz
Pin 13 (DIP) to Registered Output Disable
10
25
10
20
ns
tpzx
Input to Combinatorial Output Enable
18
35
18
30
ns
tpxz
Input to Combinatorial Output Disable
15
35
15
30
ns
fMAX
Maximum Frequency
16
35
20
35
MHz
Schematic of Inputs and Outputs
EQUIVALENT INPUT
... ----------_._o
TYPICAL OUTPUT
V~ o-----~~-------
•••
INPUT
o-....-+--~II-....-
OUTPUT
TL/LlB702-4
~---t----~--
••• ----~~---t
TLlL/B702-3
Definition of Waveforms
'"~i
OE
.--------t
---=?---
-.;..j.----t-po
o:xm
tpxz j
»)
}-tpz~
YOH -0.5Y
VOL +O.5V
TL/L/B702-5
Note 1: Ipo Is lesled wilh swilch S1 closed. CL
~
50 pF and measured a11.5V oulpullevel.
Note 2: Ipzx is measured allhe 1.5V oulpullevel with CL
~
50 pF. S1 is open for high impedance 10 ", •• lesl, and closed for high impedance 10 "0" lest.
Note 3: tpxz is tested with CL = 5 pF. 8 1 is open for "1" to high impedance test, measured at VOH - 0.5 output level; 51 is closed for "0" to high impedance test
measured al VOL + 0.5V oulpullevel.
420
Programmable Logic Design Guide
Programmable Set and Reset
Programmable Output Polarity
In each cell, two product lines are dedicated to asynchro-
The outputs can be programmed either active-low or activehigh. This is represented by the exclusive-or gates shown in
the PAL20RA10 Logic Diagram. When the output polarity
fuse is blown, the lower input to the exclusive-or gate is
high, so the output is active-high. Similarly, when the output
polarity fuse is intact, the output is active-low. The programmable output polarity features allows the user a higher degree of flexibility when writing equations.
nous set and reset. If the set product line is high, the register output becomes a logic 1, the output pin becomes a O. If
the reset product line is high, the register output becomes a
logic 0, the output pin becomes a 1. The operation of the
programmable set and reset overrides the clock.
Individually Programmable
Register Bypass
Registered! Active Low
If both the set and reset product lines are high, the sum-ofproducts bypasses the register and appears immediately at
the output, thus making the output combinatorial. This allows each output to be configured in the registered or combinatorial mode.
Combinatorial!Active
Low
Programmable Clock
One of the product lines in each group is connected to the
clock. This provides the user with the additional flexibility of
a programmable clock, so each output can be clocked independently of all the others.
Programmable and Hard-wired
TRI-STATE Outputs
The PAL20RA10 provides a product term dedicated to output control. There is also an output control pin (Pin 13). The
output is enabled if both the output control pin is low and the
output control product term is HIGH. If the output control pin
is high all outputs will be disabled or if an output control
product term is low, then that output will be disabled.
TLlL/B702-11
TL/LlB702-10
Registered! Active High
Combinatorial! Active
High
Output Control Alternatives
Output Always Enabled
Programmable
TL/L/B702-13
TL/L/B702-6
TL/LlB702-12
TL/LlB702-7
Hard-Wired
Combination of
Programmable and
Hard-Wired
OE
----l-
TL/L/B702-B
TL/LlB702-9
Security Fusing
Security fusing is also provided to prevent unauthorized
copying of PAL fuse patterns. Once blown, the circuitry enabling fuse verification is permanently disabled. With the
verification circuitry not operating, it is impossible to simply
copy the PAL pattern on a PAL programmer.
New Product Data Sheets
421
Register Preload
Register preload allows any arbitrary state to be loaded into the PAL output registers. This allows complete logic verification,
including states that are impossible or impractical to reach. To use the preload feature, first disable the outputs by bringing OE
high, and present the data at the output pins. A low-level on the preload pin (PL) will then load the data into the registers.
Q~========J,-~
I
PL
TLlLl8702-14
Pin Configuration
Dual-In-Line Package
24
Pi:
RA CELL
10
RA CELL
RA CELL
12
RA CELL
13
14
RA CELL
15
RA CELL
16
RA CELL
17
RA CELL
18
19
GND
10
RA CELL
11
RA CELL
23
22
21
20
19
18
17
16
15
14
V28PCC
Vee
00
01
12
5
25
02
13
6
24
03
03
14
7
23
04
04
NC
8
22
NC
05
15
9
21
05
06
16
10
20
06
07
17
11
19
07
02
12 13 14 15 16 17 18
08
09
!!! !!! cz
12
'"
~
1::1 '"
CJ
co
CJ
TLlL/8702-23
TLlLlB702-2
Nole: The pin..,ut of the 24 pin PAL devices in PCC has been changed to
the JEDEC standard for logic devices. Please contact your local sales office
for information regarding the availability of devices conforming to the old pin-
Top View
Order Number PAL20RA 10
See Package Number J24F, N24C and V28A
out
ProgrammerIDevelopment Systems
The following list is some of the manufacturers of Programmer/Development Systems. Call them to see if they currently support
this device.
Programmers
Adv. Micro. Sys.
Bytek Compo Sys.
Citel
DATA 110
Digelec
Digital Media
GTEKlnc.
Int. Microsys.
Kontron
Logical Devices
Oliver Adv. Eng.
Pro-Log
Stag
PROMAC
Storey Systems
Structured Design
Sunrise
Valley Data Sci.
Varix
PCADSys.
Nat. Semi.
Software Development
DATA 110
Programming Algorithm Specification
For a complete programming spec. request National Semiconductor Spec #TS-2100-BPM.
422
Programmable Logic Design Guide
Logic Diagram
120
JEDEC PRODUCT
LINE I
INPUT LINE
I
o
"eo
'50
'00
,,,
'50
~1I_1I~~-fQ
520
560
800
.9::g1l_.~~5
820
119°O~!I!lI!II!lII!lIIII!I!lIIII!lII~~~~~~~~~==~~~~~
220"
720
'00
.00
."
1000
10"
1080
1120
1100
1280II_II~~-fQ
1320
1360
''''
""
""
1520
1560
"001l_1I~~
""
'680
1720
1760
1800
18"
1880
'92°Il_III1~~
20
1900
2000
20"
2080
2120
2160
22"II_II~~~
""
""
'280
2320
2360
,'"
2520
"60
2600
26"
2680
2720
2760
2800
28"
10
2880
2920
2960
3000
30"
30BO
3120
3160
11
Note: Fuse Number = JEDEC Product Line#
+
Input Une#
TL/Ll8702-15
423
New Product Data Sheets
Physical Dimensions inches (millimeters)
I.28D
.!!!
HAD
IU31)
1 - - - - - - - - 132.77) MAX----------I--i
0.030-0.055
10.762-1.3971
tFt
_of.~~__~r-_________~____I~_::_:_:__:~_2:_)_TY_P +-~____-,0._'02_0~_0_.~~oR~ADTIYP (~~::~:~~ r-__
0.110
95"
I
I
0.100 :to.OIO
12.54 :10.254)-1
TYP
0.008-0.012
10.203-0.3051
;5"
I
0.310-0.410
I-- 17.874-10.41l-l
TYP
J24FIREVGI
Ceramic Dual-In-Llne Package (J)
NS Package Number J24F
1.243-1.270
----------11
'.'.,;:""'------r
0.092
(2.3371
(2 PLSI
0.260tO.0D5
(6.604tO.1271
PIN NO.1
10ENT
I
OPTION 2
0.300-0.320
!"G:'~I
~J
0.009-0.015
(0.229-0.3811
0.325 ~~:~~
(8255 +1.016)
(.
-0.381
0.130tO.005
0.065
(1.6511
-+--"::::::"--j
0.075±0.015
(1.905 ±0.3811
I
IN24C(AEVf)
Molded Dual-In-Llne Package (N)
NS Package Number N24C
424
Programmable Logic Design Guide
Physical Dimensions inches (millimeters) (Continued)
l
~
(UI3-1.0I1'
+
l
t-=t
U. U2U
iWii
MIN
'r!::ATrrr ~
(3:'
I
15
HOM
PEDESTAL
(CU:~~~~~,1
~
[3-0.011
(0.330-0.457,
TYP
0.1111-0.1111
~
+ +
1&"
0.021-0.032
(0.Il10-0.113,
TYP
V28ACAEVGI
Plastic Chip Carrier Pkg (V)
NS Package Number V28A
425
New Product Data Sheets
12.2
CMOS PROGRAMMABLE LOGIC DEVICES
GAL ® 16V8 Generic Array Logic
PRELIMINARY
September 1987
General Description
Features
The NSC E2CMOSTM GAL device combines a high performance CMOS process with electrically erasable floating gate
technology. This programmable memory technology applied
to array logic provides designers with reconfigurable logic
and bipolar performance at significantly reduced power levels.
• Electrically eras?ble cell technology
- Reconfigurable logic
- Reprogrammable cells
- Guaranteed 100% yields
• High performance E2CMOS technology
45 mAl90 mA max active
- low power:
35 mAl70 mA max standby
- High Speed:
15 ns-35 ns max access
• Eight output logic macrocells
- Maximum flexibility for complex logic designs
- Also emulates 20-pin PAL devices with full
function/fuse map/parametric compatibility
• Preload and power-on reset of all registers
- 100% functional testability
• High speed programming algorithm
• Security cell prevents copying logic
The 20-pin GAL 16V8 features 8 programmable Output logic Macrocells (OlMCs) allowing each output to be configured by the user. Additionally, the GAL 16V8 is capable of
emulating, in a functional/fuse map/parametric compatible
device, all common 20-pin PAl® device architectures.
Programming is accomplished using readily available hardware and software tools. NSC guarantees a minimum 100
erase/write cycles.
Unique test circuitry and reprogrammable cells allow complete AC, DC, cell and functionality testing during manufacture. Therefore, NSC guarantees 100% field programmability and functionality of the GAL devices. In addition, electronic signature is available to provide positive device 10. A security circuit is built-in, providing proprietary designs with
copy protection.
Functional Block Diagram
Pin Names
'0- 115
Input
OE
CK
Clock Input
Vee
Output Enable
Power (+5V)
Bo-B5
Bidirectional
GND
Ground
Fo-F7
Output
GAL 16V8 Emulating PAL Devices
10/CK
Vee
12
I,
I.
IS
'7
I"
113
115
'7
B,
B,
"
"
's
1'2
I..
"
's
B2
's
GAL
16VB
F,
I,
F2
17
"'0
18
GNO
19
10lB
IOHB
lOPS
r
" "
"
"
'12
'"0
113
F2
'2
F,
Fo
Fo
110
19
1216
12H6
12P6
I"
I"
1'0
19
1'0
19
1414
1612
14H4
UN
's
F.
"
Bs
" "
"
B.
F2
B,
F2
F,
B2
"
'0
'0
B,
B,
Bo
'0
Bo
Bo
5E
5E
DE
'0
19
F,
F2
"
16RB '6R6 16R4 16lB
16H2 16RPB 16RP6 I,RP4 16HB
16P2
16PB
GAL 16VB
TLlLl9344-2
TL/L/9344-1
TAt·STATE' 15 a registered trademark of NatIOnal Semiconductor Corporation
GAL' IS a registered trademark of Lattice Semiconductor.
PAL IS a registered trademark of Monolithic Memones.
0,
PLANTM IS a trademark of National Semiconductor Corporation.
E2CMOSTM IS
a trademark
~f
Lattice Semiconductor.
426
Programmable Logic Design Guide
Pin Configurations
Chip Carrier
DIP
IO/ClK
Vce
F7
F6
13
4
I.
5
15
6
16
7
17
18
GND
Fs
18
16
F.
17
FS
15
F3
16
F.
F6
14
F2
15
F3
13
Fl
1.
F2
12
Fo
11
Ig/OE
10
TL/Ll9344-3
TL/l/9344-4
Absolute Maximum Ratings
Top View .
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage Vee
Note: Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress only ratings and functional operation
of the device at these or at any other conditions above
those indicated in the operational sectiqns of this specification is not implied (while programming, follow the programming specifications.)
-0.5V to + 7.0V
Input Voltage Applied
-2.5 to Vee + 1.0V
Off-State Output Voltage Applied
-2.5 to Vee +1.0V
Storage Temperature
- 65'C to + 125'C
ESD rating is to be determined.
Electrical Characteristics Over Operating Conditions
Symbol
Parameter
Conditions
Units
QUARTER POWER GAL 16V8
IIH,IIL
Input Leakage Current
GND ,;; VIN ,;; Vee Max
IBZH
IBZL
Bidirectional
Pin Leakage Current
GND ,;; VIN
< Vee Max
IFZL
IFZH
Output Pin
Leakage Current
GND ,;; BIN
< Vee Max
Icc
Operating Power Supply Current
F = 15 MHz
Vee = Vee Max
los (Note 1)
Output Short Circuit
Vee = 5.0V, VOUT = GND
ISB
Standby Power Supply Current
Vee = Vee Max
VOL
VOH
Output Low Voltage
Output High Voltage
VIH
Input High Voltage
VIL
Input Low Voltage
Vee =
Vee Min
Vee =
Vee Min
±10
/-LA
±10
/-LA
±10
/-LA
Com'l
45
mA
Millind
50
mA
-130
mA
-30
Com'l
35
mA
Millind
45
mA
10L = 24mA
Com/lnd
0.5
V
10L = 12mA
Mil
0.5
V
10H = -3.2mA
Com/lnd
2.4
V
10H = -2.0mA
Mil
2.4
V
2.0
Vee + 1
V
0.8
V
±10
/-LA
±10
/-LA
±10
/-LA
HALF POWER GAL 16V8
IIH,IIL
Input Leakage Current
GND ,;; VIN ,;; Vee Max
IBZH
I!'IZL
Bidirectional
Pin Leakage Current
GND ,;; VIN
< Vee Mal(
IFZL
IFZH
Output Pin
Leakage Current
GND ,;; BIN
< Vee Max
New Product Data Sheets
427
Electrical Characteristics Over Operating Conditions (Continued)
Symbol
Parameter
Conditions
Units
HALF POWER GAL 16V8 (Continued)
Operating Power Supply Current
lee
F=15MHz
Vee = Vee Max
los(Note 1)
Output Short Circuit
Vee = 5.0V, VOUT = GND
ISB
Standby Power Supply Current
Vee = Vee Max
Com'l
90
mA
Mil/ind
90
mA
-130
mA
-30
Com'l
70
mA
Mil/ind
70
mA
Com/lnd
0.5
V
VOL
Output Low Voltage
Vee =
Vee Min
IOL = 24mA
VOH
Output High Voltage
Vee =
Vee Min
IOH = -3.2mA
Com/lnd
2.4
V
IOH = -2.0mA
Mil
2.4
V
VIH
Input High Voltage
VIL
Input Low Voltage
Mil
IOL = 12mA
0.5
2.0
V
Vee + 1
V
0.8
V
Note 1: One output al a time for a maximum duration of one second.
Operating Range
Temperature Range
Symbol
Parameter
Industrial
Commercial
Min
Typ
Max
Min
Typ
Max
4.5
5
5.5
4.75
5
5.25
V
85
0
75
·C
Military
Min
Typ
Vee
Supply Voltage
4.5
5
TA
Ambient Temperature
-55
Te
Case Temperature
Max
5.5
-40
Units
·C
125
Switching Test Conditions
Input Pulse Levels
GNDto 3.0V
Input Rise and Fall Times
5 ns 10%-90%
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
See Figure
+5V
FROM OUTPUT (B x, Fx)_....._-.I--TEST POINT
UNDER TEST
390n
TRI-STATE@ levels are measured O.SV from steady-state active level.
TL/L/9344-5
'CL INCLUDES JIG AND PROBE TOTAL CAPACITANCE
Capacitance TA =
Symbol
25·C, f = 1.0 MHz
Conditions
Maximum
Units
CI
Input Capacitance
Parameter
Vee = 5.0V, VI = 2.0V
12
pF
CF
Output Capacitance
Vee = 5.0V, VF = 2.0V
15
pF
CB
Bidirectional Pin Cap
Vee = 5.0V, VB = 2.0V
15
pF
428
Programmable Logic Design Guide
Switching Characteristics Over Operating Conditions
Temperature Range
Military
Symbol
Conditions
(Note 1)
Parameter
Commercial/Industrial
GAL
GAL
GAL
GAL
GAL
16V8-15
16V8-25
16V8-35
16V8-20
16V8-30
Units
R(n)
CdpF)
200
50
15
25
35
20
30
ns
TDVQV2 Product Term
Enable Access Time
to Active Output
Active High
R = 00
Active Low
R = 200
50
15
25
35
20
30
ns
TDVQZ Product Term
(Note 2) Disable to
Output Off
FromVOH
R = 00
From VOL
R = 200
5
15
25
35
20
30
ns
TGHQZ OE (Output Enable)
(Note 2) High to Output
Off
FromVOH
R = 00
From VOL
R = 200
5
15
20
25
18
25
ns
Active High
R = 00
Active Low
R = 200
50
15
20
25
18
25
ns
200
50
12
15
25
15
20
Delay from Input
to Active Output
TDVQVI
OE (Output Enable)
Access Time
TGLQV
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
ns
TCHQV
Clock High to Output
Valid Access Time
TDVCH
Input or Feedback
Data Setup Time
12
20
30
15
25
ns
TCHDX
Input or Feedback
Data Hold Time
0
0
0
0
0
ns
TCHCH
Clock Period
(TDVCH + TCHQV)
24
35
55
30
45
ns
TCHCL
Clock Width High
10
15
20
12
15
ns
TCLCH
Clock Width Low
10
15
20
12
15
fMAX
MaXimum, Synch.
Frequency Asynch.
I
200
50
41.6
66.6
28.5
40.0
18.1
28.5
33.3
50.0
ns
22.2
33.3
MHz
Note I: Refe, also to Switching Test Conditions.
Note 2: TRI-STATE levels are measured O.SV from steady·state active level.
Switching Waveforms
ClK
OE
REGISTERED
OUTPUTS
FOR
--+--"1
--+--~---~-"I
::::l::::::::jC:::::~----{:::::X::::::::=
ANYINPUT~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~_~~__~
PROGRAMMED
OE CONTROL ~~~~~~~~~~:w.~:w.QI.:w.QI.~-.t:)J.~~~~~~~\:';;:::"==~"";:=:":;=:..J
COMBINATIONAL
OUTPUTS
::~:::~:Z:~C::::::::::::::~~:j~--":"=4
TLlL/9344-7
New Product Data Sheets
429
GAL 16V8 Logic Diagram
1
0
1
2
3
4
5
6
7
8
9
10
11
~v
~OlMC
5
6
2..
~IV
~ OlMC
-(18)
V
OlMC
(17)
...
8 ...
~
.
24
25
26
27
28
29
30
31
....
~J-:;o
V
OlMC
~(16)
17
ra-,
16
.....
~J-::o
32
33
34
35
36
37
38
39
~
~
V
OlMC
(15)
ra ,
15
~
-
a
ia
S
1.2
1.1
0.9
z
0.8
!
1.1
~...
'"z
!!i
1.0
0.9
0.8
/'
0.7
4.0
/'
4.5
o
"0
~
~
1.1 ~
1.0
0.9
!!i
z
0.8
0.7
4.0
6.0
~
1.0
~
0.9
z
0.8
~
"'-
1.1
0.7
4.0
4.5
is
"
5.0
"-....
5.5
J
>
~
V
10
/
~
1.0
~
0.9
ii!
il
i!l
6.0
200
400
eoo
800 1000
OUTPUT LOAD CAPACITANCE (pr)
125
"..
1.2
./
1.1
1.0
~ii!
0.9
z
0.8
/
/
0.7
-55
6.0
V
/'
/
o
25
85
125
AMBIENT TEMPERATURE ("C)
0.8
0.7
V
/'
...-
180
/
]:
120
.9
90
/
V
V
60
/
/
30
o
25
85
o
o
125
-
./~
150
2.0
1.0
AMBIENT TEMPERATURE ("C)
3.0
4.0
VOL (V)
Delta TDVQV (Tpo)
20 VB Output Loading
]:
15
V
"0
~
>
~
1/
"
5.5
85
vs Temperature
0
V
0.6
-55
~
V
fo!
vs Temperature
1.1
Delta TCHQV (Tco)
/
5.0
25
Normalized TCHQV (Tco)
is
%
""
1.2
~
20 VB Output Loading
15
o
...... ~
AMBIENT TEMPERATURE ("C)
J
4.5
SUPPLY VOLTAGE (V)
:!
'"
Normalized TDVCH (Tsu)
1.3
~
"-
0.7
-55
125
SUPPLY VOLTAGE (V)
Normalized TDVCH (Tsu)
~
85
25
1.2
~
;oj
vs Supply Voltage
1.2
"-"
0.9
1.3
SUPPLY VOLTAGE (V)
1.3
~
~z
Normalized TCHQV (Tco)
Supply Voltage
S
5.5
1.1
1.0
II
VB
fo!
5.0
!
8
1.3
/
V
/
AMBIENT TEMPERATURE ("C)
Normalized ICC(MAX)
1.3 VB Supply Voltage
_8
1.3
0.8
0.7
-55
6.0
SUPPLY VOLTAGE (V)
1.2
V
/
1/
Normalized ICC(MAX)
Temperature
VB
1.2
/~
1.0
~
ii!
0
Normalized TDVQV (Tpo)
vs Temperature
10
/
IOHVSVOH
/
100
]:
80
~
V
40
/
"'
20
200
400
eoo
800 1000
OUTPUT LOAD CAPACITANCE (pr)
o
o
1.0
"-
~
2.0
...... ..........
3.0
VOH (V)
TL/L/9343-19
New Product Data Sheets
:hl
453
Physical Dimensions inches (millimeters)
(0:635)
0025 RAD
·..-------(32.771
1.290 M A X - - - - - - - - - - I
24
0.295
(7.493)
--MAX
0.030-0.055
(0.762-1.3911
1
RADTYP
0.060 ±0.005 TYP
11.524 ±0.127)
GLASS
SEALANT\
0.020-0.070
"·r~J"
(5.715)
~~_~
__'J__.__'J~ __,~____~t~~~~=~M~AX
~
tf+
0.290-0.l20
(7.l66-8.128)
A~
____'I-_ --- ~,
(~::~:)
MIN
95'
I
0.310-0.410
I
0.008-0.012
(0.20l-0.l05)
TYP
I-- (7 .874-10.411--1
J24F(REV G)
24-Pln, 300-Mil Cerdip (J)
NS Package Number J24F
1.243 -1.270
r--------(~3~1.~57~-~3~2.=26)-------~
0.092
(2.337)
MAX
(2 PLS)
!
0.260±0.005
(6.604±0.127)
PIN NO.1
10ENT
I
0.300 - 0.320
0.040
(1.016)
TYP
0.009 - 0.015
(0.229-0.381)
+0 040
0.325 -0:015
0.280~
(7.112)~
MIN
18255 +1.016) -+--~
.
~J
0.065
(1.651)
0.075±0.015
(1.905 ±0.381)
I
I--
90' ±4' TYP
-0.381
N2,*C(RE'\1 F)
24-Pin, 300-Mil Plastic DIP (N)
NS Package Number N24C
454
Programmable Logic Design Guide
Physical Dimensions inches (millimeters) (Continued)
l
t-=t .5.
0.020
0.032-0.040
(0.813-1.0161
(co::]i~1fIONI [
~
iD.5oii
MIN
t
~-0.015 r=~I:N NO.lj
(0.127-0.3111
10ENT
0.450
ii1.i3i
I
0.013-0.018
(0.330-0.4571
TYP
0.1115-0.1111
(4.111-4.5721
c---_-L-t-Lt
jl
_
0.026-0.032
f
t..!!l!!!.=.t!.!
(0.6&0-0.8131
12.642-2.9971
TYP
REF SQ
0.485 - 0.495
~
SQUARE
V28AIAEVGj
28·Pin, Plastic Leaded
Chip Carrier (PLCC)
NS Package Number V28A
New Product Data Sheets
12.3
455
ECl PAL DEVICES
Eel Programmable Array
logic (PAl®) Family
December 1985
General Description
The PAL1016P8/10016P8 is the first member of an ECl
programmable logic device family possessing common
electrical characteristics, utilizing an easily accommodated
programming procedure, and produced with National Semiconductor's advanced oxide-isolated process. This family
includes combinatorial, latched, and registered output devices.
These devices are fabricated using National's proven Ti-W
(Titanium-Tungsten) fuse technology to allow fast, efficient,
and reliable programming.
This family allows the designer to quickly implement the defined logic function by removing the fuses required to properly configure the internal gates and I or registers. Product
terms with all fuses removed assume a logical high state. All
devices in this series are provided with an output polarity
fuse that, if removed, will permit any output to independently
provide a logic low when the equation is satisfied. When
these fuses are intact the outputs provide a logic true (most
positive voltage level) in response to the input conditions
defined by the applicable equation.
The registers, in selected devices, consist of D-type flipflops which are loaded in response to the low-to-high tran-
sition of the clock. Fuse symbols have been omitted from
the logic diagrams to allow the designer use of the diagrams
to create fuse maps representing the programmed device.
All devices in this family can be programmed using conventional programmers. After the device has been programmed
and verified, an additional fuse may be removed to inhibit
further verification or programming. This "security" feature
can provide a proprietary circuit which cannot easily be duplicated.
Features
• Programmable replacement for conventional ECl logic
• Offered in a 10 kH 1/0 compatible version with a 100k
version coming
• Simplifies prototyping and board layout
• 24-pin thin DIP packages.
• Programmed on standard PAL programmers
• Special feature reduces possibility of copying by
competitors
• Reliable titanium-tungsten fuses
• Also offered in Ceramic Chip Carriers
Ordering Information
, - - - - - PROGRAMMABLE ARRAY LOGIC FAMILY
I
ECL 110 COMPATIBLE
10 = 10KH
100= lOOK
NUMBER OF ARRAY INPUTS
f.!r=
OUTPUT TYPE
P = PROGRAMMABLE
RP = REGISTERED AND PROGRAMMABLE
LP = LATCHED PROGRAMMABLE
NUMBER OF OUTPUTS
PACKAGE
N = PLASTIC DIP
J = CERAMIC DIP
r- TEMPERATURE RANGE
t
C = O"C TO +75'C
PAl1016P8Jc
TL/L/6161-1
PLANTt.I is a trademark of National Semiconductor Corp
PAle is a registered trademark of and used under license with Monolithic Memories, Inc.
PALASMTM is a trademark of and under license with Monolithic Memories, Inc.
456
Programmable Logic Design Guide
Absolute Maximum Ratings
(Note 3)
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Temperature Under Bias (Ambient)
- 55'C to + 125'C
Storage Temperature Range
-65'Cto + 150'C
-7Vto +0.5V
VEE Relative to Vee
Any Input Relative to Vcc
Lead Temperature (Soldering, 10 seconds)
300'C
Electrical Characteristics Over Recommended Operating Temperature Range for ECL PALs.
TA = O'C to +75'C (PAL1016P8)/TA = O'C to +85'C (PAL10016P8), VEE = -5.2V ±5% (PAL1016P8)IVEE
±5% (PAL10016P8), Output Load = 500 + 5 pF to -2.0V.
Symbol
VIH
VIL
VOH
VOL
IIH
IlL
lEE
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
High Level Input Current
Low Level Input Current
Supply Current
Conditions
Guaranteed input voltage
high for all inputs
Guaranteed input voltage
low for all inputs
VIN
VIN
VIN
VIN
VEE
TA
Min
10 kH
O'C
+ 25'C
+ 75'C
-1170
-1130
-1070
100k
O'Cto 85'C
-1165
10kH
O'C
+ 25'C
+ 75'C
100k
O'Ct085'C
-1810
-1475
10kH
O'C
+ 25'C
+ 75'C
-1020
-980
-920
-840
-810
-735
100k
O'Cto 85'C
-1025
-880
10kH
O'C
+ 25'C
+ 75'C
-1950
-1950
-1950
-1630
-1630
-1600
100k
O'Ct085'C
-1810
-1620
10 kH
O'C
+ 75'C
100k
O'Cto 85'C
10 kH
O'C
+ 75'C
100k
O'Cto 85'C
10 kH
O'Cto 75'C
100k
O'Cto 85'C
= VIH Max. or VIL Min.
= VIH Max. or VIL Min.
= VIH Max.
= VIL Min.
= Max.
Except I/O Pins
All inputs and
outputs open
=
Max
-4.5V
UnHs
mV
-880
-1480
-1480
-1450
mV
mV
mV
220
p.A
0.5
p.A
-240
mA
Operating Conditions
Symbol
VEE
Parameter
Supply Voltage
Min
Typ
Max
10kH
-5.46
-5.2
-4.94
100k
-4.8
-4.5
-4.2
Units
V
RL
Standard 10 kH/100k Load
50
0
CL
Standard 10 kH/100k Load
5
pF
TA
Operating Ambient Temperature (Note 2)
10 kH
0
+75
100k
0
+85
'C
Note 1: This product family has been designed to meet the specification in the test table after thermal equilibrium has been established. The clreu" is in a test
socket or mounted on a printed circu" board and transverse air flow greater than 500 linear fpm is maintained.
Note 2: Mounted in socket or printed circuit board with transverse airflow exceeding 500 linear feet per minute.
Note 3: Absolute Max. Rat., Electrical Characteristics and Operating Conditions of PALl 00 16PS are preliminary data.
~ ~t ~Il
-2 V
-=
RL =50n
cL~5iir
(INCLUDING JIG AND
STRAY CAPACITANCE)
TL/L/6161-4
457
New Product Data Sheets
Connection Diagram
Dual-In-Llne Package
.
"
""
,.
110
10
Vtel
0
110
I
18
17
10
11
VEE
12
""
"
"
Vcc
110
0
VCC2
0
110
I
TL/L/6161-2
Top View
Switching Characteristics
Over Recommended Ranges of Temperature and Vee. TA = 00 to 7S·C (PALl 016PB)/TA = O·C to + BS·C (PALl 0016PB), VEE
= -S 2V ±S% (PAL1016PB)IVEE = -4.SV ±S% (PAL10016PB), RL = son +S pF to -2.0V.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
tpD
Input to Output'
4
6
ns
tr
Output Rise Time
1
ns
tf
Output Fall Time
1
ns
• Measure tpD at 50% pOints of waveforms
PAL Design
The first step in designing a PAL device is the selection of
the appropriate device to accommodate the logic equations.
This is accomplished by partitioning the system into logic
blocks with a defined number of inputs and outputs. Next, a
device with an equal or greater I/O capability is selected to
implement each logic block. The assignment of inputs and
outputs to specific pins follows the device selection.
This device selection procedure is most easily accomplished with the use of computer software such as the
PLANTM package of programs by National Semiconductor
Corporation, but can be done manually using the logic diagram and logic symbols pro~ided in this document.
Specifying the Fuse Pattern
Once a device with pinout is selected, the fuse pattern may
be specified. The best procedure is the use of the PLAN, or
a similar software package which will create the fuse pattern
from the defined logic for the device and download the pat·
tern to a programmer. Most common device programmers
are provided with an RS-232 port which accesses the data
provided in JEDEC or a selected HEX format.
logic diagrams can be translated to PAL logic diagrams if
desired. Fuses left intact are indicated on the logic diagram
by an "X" at the intersection of the input line and the AND
gate product line. A blown fuse is not marked. The PAL logic
diagrams are provided with no fuse locations marked, allowing the designer to use the diagram to manually create a
fuse map. Actually, the unprogrammed device is shipped
with all Xs (fuses) intact. Each fuse node is identified by a
product line number and an input line number.
Each device in the ECl PAL family has the capability for its
output polarity to be user-determined. The selection of output polarity is logically determined by the equations and implemented, if an active low output is required, by removing
the fuse representing the appropriate output.
The most common means of programming involves downloading data from a computer in the JEDEC format. In this
format the fuses are numbered and transmitted sequentially
to the device programmer. The JEDEC fuse numbers for the
array begin with fuse 0 at the intersection of input line 0 and
product line 0 and are sequentially numbered (proceeding
across each product line) ending with the fuse at the intersection of input line 31 and product line 63 with fuse 2047.
The output polarity fuse representing the least significant
product lines (output pin 21 for the PAL1 016PBI
PAL10016PB) to the fuse representing the most significant
product lines (output pin B for the PAL1 016PBI
PAL10016PB) are numbered from 204!3to 20S1 for a 4-output device and ending at 20SS for an B-output device.
National Masked Logic
If a large number of devices with the same pattern are required, it may be more economical to consider mask programming. These mask-programmed devices will meet or
exceed all of the performance specifications of the fuse·
programmed devices they replace.
To generate a mask-programmed device, National Semi·
conductor requires a set of logic equations written in either
the PLAN or PAlASMTM formats, plus test vectors which
the user generates as acceptance criteria for the finished
product.
458
Programmable Logic Design Guide
Logic Diagram PAL 1016P8/PAL 10016P8
0123
4S67
89ID111213141S1617111t2021lU3242526%7282i3031
23
22
,,
0
3
,•
•
1
at±z:
" t=
4=
1
(:::
",.
""
"
11
17
~
"
."""
"""
16
2-
15
10
14
11
13
TLll/6161-3
New Product Data Sheets
459
Programming Specification
This specification defines the programming and verification
procedure for the first programmable logic devices in Nationals generic ECL family. The internal fuse arrays consists
of 64 product lines (8 for each output), each containing 32
fuse locations (1 for each of 16 inputs and its complement)
for a total of 2048 array fuses. Eight additional fuses exist to
allow changing the active output polarity.
Each ECL device is programmed and verified as a 2048x1
TTL PROM. The connection diagrams in Figure 1 illustrate
the difference between the logical ECL device and the PROGRAMMABLE TTL device.
ECLLOGIC
TTL PROGRAMMING
1
24
Vee
A
2
23
I
A
I
I/O
0
Vee l
0
I
A
A
I/O
0
0
0
0
Vee2
0
I/O
0
Vee2
0
Vee l
0
I/O
0
0
A
A
10
15
VER
A
11
14
A
11
14
A
12
13
VEE
12
13
A
10
VEE
Vee
A
2
TL/L/6161-5
TlIlI6161-6
FIGURE 1. Connection Diagrams
Software Support
Programmer Support
Software
Vendor
PLAN
National
Semiconductor
Availability
Now
ABEL
Data I/O
Now
CUPL
Assisted
Technology
Nov 85
Model
Vendor
Availability
ECL-1
IMI
Now
Data I/O
Now
ALPS
Nov 85
E-100
460
Programmable Logic Design Guide
Array Fuse Addressing
When programming or verifying a fuse location, the output
(equation) is addressed by the 3 address pins 13, 14, and
15. The eight product lines, within the equation, are selected
by the 3 address pins 9, 10, and 11. The fuse pair locations
representing the logical inputs are selected by the 4 address pins 2, 3, 22, and 23, with the complementing fuse
within the pair by the address pin 1. The programming address data is detailed in Tables I-III.
Table I. Logic Output (Equation) Selection vs.
Programming Address Inputs.
Output
Pin
15
Address Pin
14
13
21
4
20
5
18
7
17
8
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Note that the sequence of outputs represent the physical, not numeric, order
of logical outputs.
Table II. Product Line (within Equation, or Output) vs.
Programming Address Inputs.
Product
Pin
0
1
2
3
4
5
6
7
Address Pin
11
10
9
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Table III. Input Line Selection vs. Programming Address
Inputs.
Address Pin
Input
Line
23
22
3
2
1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Note pin 1 affects complementing fuse only.
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
New Product Data Sheets
Fuse Programming and Verification
The array and output polarity fuse programming waveform
diagram is shown in Figure 2. The 8 output pins ON are used
only to change the polarity of the selected device output
and for removing the "security" fuse. Tables 4 and 5 define
the voltage and timing requirements.
Programming Procedure
1. Power is applied to the device. VCC, VCC1, and VCC2
(pins 24, 6, and 19) go to VCC. (The voltage applied to
pin 24 cannot precede the voltage applied to pin 6) The
output pins (4, 5, 7, 8, 17, 18, 20, and 21), are open circuited, or held at a logic low level, while programming the
array.
2. After TO, VCCI (pin 6) can be raised from 5.0 to 10. 75V at
a slew rate not to exceed 1OVI ",S, or not less
than 1V/ ",s.
3. The 11 address inputs (pins 1-3, 9-11, 13-15, 22, and
23) will define the location of the array fuse to be opened
or the applicable output pin will define the polarity fuse to
be opened.
4. After VCCI has been stable at 10.75V for period Tl and
the address has been stable defining the applicable fuse
location for period T2, VCC2 (pin 19) may slew from 5.0
to 10.75V at a slew rate of 1 to 10V/",S.
5. VCC2 must remain stable at 10.75V for the duration of
the programming pulse (TP) before returning to 5.0V.
6. With VCCI atl0.75V and after VCC2 has been stable at
5.0V for the period T3, VEA pin (16) may be sampled. If
the fuse was properly opened, a logic low level will be
observed. If the fuse did not open, steps 4 through 6 may
be repeated up to 15 times.
7. If additional locations are to be addressed, steps 3
through 6 must be repeated for each fuse to be opened
while observing the maximum power up time and duty
cycle.
Fuse Verification
Fuse verification may be performed independent of programming. As seen in Figure 2, with VCCI at VCCP and
VCC2 at VCC verification may occur within the defined timing constraints. (See Table V)
1 - - - - 5 mS MAXIMUM 20% DUTY CYCLE - - - - - + \
0
ON
VIL
VIL
461
POLARITY FUSE
ADDRESSING
V1H
AN
V1L
VER
VOL
TLlLl6161-7
FIGURE 2. Array/Polarity Programming Diagram
462
Programmable Logic Design Guide
TABLE IV. DC Requirements
Symbol
Vcc
Description
Min
Nom
Max
Units
Pin 24 Voltage While Programming or Verifying (Pin
19 Verifying) (Note 1)
4.75
5.00
5.25
V
200
300
mA
10.50
10.75
11.00
V
300
450
mA
10
25
mA
0.8
V
Icc
Pin 24 Current While Programming (Note 2)
Vccp
VCC1IVCC2 (Pins 6 and 19) Voltage While
Programming (Note 3)
ICCl
VCCl (Pin 6) Current While Programming (Note 2)
ICC2
VCC2 (Pin 19) Current While Programming (Note 2)
VIL
Input LOW Level-If Left Open, Pins 4, 5, 7, 8, 17,
18,20, and 21 are Held Low by Internal50K
Resistor
IlL
Input LOW Current - Pins;
1-3,9-11,13-15,22, and 23
VCCIVCC1IVCC2 = Max, VIN = 0.4V
-1.0
-1.5
mA
4,5,7,8,17,18,20, and 21 (Note 4)
VCCIVCC1IVCC2 = Max, VIN = 0.8V
-0.25
-1.5
mA
0
VIH
Input HIGH Level
IIH
Input HIGH Current
VCCIVCC1IVCC2 = Max, VIN = VCC Max
Pins 1-3, 9-11,13-15, 22, and 23
2.20
90
4,5,7,8, 17, 18,20, and 21
3
VOL
Output (Pin 16) LOW Level
VCCIVCC1IVCC2 = Min, IOL
VOH
Output (Pin 16) HIGH Level
VCCIVCC1IVCC2 = Max, IOH
Vcc
V
300
/LA
5
mA
0.8
V
= 4 mA
V
2.20
= -0.6 mA
Note 1: While programming/verifying. power can be applied to the device for 5 mS maximum with a duty cycle of 20% maximum.
Note 2: Current measurements are taken with VcclVcc,lVcC2 at maximum and with all device inputs and outputs open.
Note 3: The difference between Vcc and vccp must not exceed SY.
Note 4: If VIN (VII) is less than 0.8 volts at pins 4.5.7,8,17,18,20, or 21, means must be provided to IimH the current sourced by the device pins to 10 mAo
Note 5: Ali programming and verification to be performed at 25'C ± 5"C
TABLE V. Timing
Symbol
Description
Min
Nom
0
500
ns
VCC1 at Vccp Before Raising VCC2
400
500
ns
T2
Address Set-Up TIme to VCC2> VCCP
400
500
T3
VER Valid After VCC2 at Vcc (Note 2)
T4
VCC2 at Vcc Before Lowering VCCl
T5
VER Valid After Raising VCCl (Note 2)
200
500
ns
T5b
Address Set-Up Time to VER Valid (Note 2)
200
500
ns
T6
VER Valid Hold Time From Address
0
ns
T7
VCC2 at Vcc Before Address Change
400
500
ns
T8
VER Valid Hold Time From VCC2 > VCCP (Note 2)
0
100
ns
T9
VCCl at VCC Before Power Down
0
TP
Programming Pulse
10
TO
Power-Up Before Raising VCCl (Note 1)
Tl
200
400
= Vcc and Vcc, = VccP.
Units
ns
500
500
ns
ns
ns
10
Note 1: Observe ti1e mBXImum power-up time or 5 ms and dut'; c,,/cfG of 20% for VCC/VCC1/VCC2 dunng progiamming.
Note 2: VER is valid when VCC2
Max
30
/Ls
New Product Data Sheets
463
Security Fuse Programming
The security fuse is opened using the same procedure as used for changing the output polarity, except all 8 outputs (pins 4,
5,7,8,17,18,20, and 21) must be selected with the application of VIH. Verification is determined by the inability to further
verify the array.
r - - - - 5 m S MAXIMUM 20% DUTY CYCLE-----.,
Vce
D
o
o
ALL OUTPUTS HIGH
TO SELECT SECURITY FUSE
TLlL/6161-8
FIGURE 3. Security Fuse Programming Diagram
464
Programmable Logic Design Guide
Physical Dimensions inches (millimeters)
::,RAD
~------------~~,MAX------------~
24-Pln Dual-In-Llne Package (J)
Order Number PAL 1016P8J/PAL10016PBJ
NS Package Number J24F
0.1192
,2.337,
~----------'~:=~~I----------~
MAX
. ,2PlSI
PIN NO, 1
'DENT
0.300-0.328
i7.i2=i.iiii
0.0D9-0.015
'0.229-0.3811
24-Pln Dual-In-Une Package (N)
Order Number PAL 1016P8N/PAL10016P8N
NS Package Number N24C
N"'CtREYfl
New Product Data Sheets
Eel Registered and latched Programmable
Array logic (PAl®) Family
465
PRELIMINARY
September 1986
General Description
The registered and latched ECl PAL devices are the latest
additions to National Semiconductor's ECl PAL family. The
ECl PAL family utilizes National Semiconductor's advanced
oxide-isolated process and proven Titanium Tungsten
(Ti-W) fuse technology to provide user-programmable logic
to replace conventional ECl SSIIMSI gates and flip-flops.
Typical chip count reduction gained by using PAL devices is
greater than 4:1.
This family allows the systems engineer to customize his
chip by opening fuse links to configure AND and OR gates
to perform his desired logic function. Complex interconnections that previously required time-consuming layout are
thus transferred from PC board to silicon where they can
easily be modified during prototype checkout or production.
The PAL transfer function is the familiar sum-of-products
implemented with a single array of fusible links. The PAL
device incorporates a programmable AND array driving a
fixed OR array. The AND term logic matrix incorporates 16
complementary inputs and 64 product terms. The 64 product terms are grouped into eight OR functions with eight
product terms each. All devices in this series are provided
with output polarity fuses. These fuses permit the designer
to configure each output independently to provide either a
logic true (by leaving the fuse intact) or a logic false (by
programming the fuse) when the equation defining that output is satisfied. In addition, the ECl PAL family offers these
options:
• Output registers
• Output latches
• Dual (split) clocks
• ORed (common) clocks
Product terms with all fuses programmed assume a logical
high state, while product terms connected to both the true
and compliment of any input assume a logical low state. All
product terms in an unprogrammed part are logically low.
Registers consist of D-type flip-flops which are loaded in
response to the low-to-high transition of the clock. latches
are transparent while the enable is low, and hold data while
PLANTU Is a trademark 01 National Semiconductor Corporation.
PALe Is a registered trademark of and used under license from Monolithic Memories, Inc.
the enable is high. Fuse symbols have been omitted from
the logic diagrams to allow the designer use of the diagrams
for logic editing.
These ECl PAL devices may be programmed on most PlD
programmers. Programming is accomplished with TTL voltage levels. Once the PAL is programmed and verified, an
additional fuse may be programmed to defeat verification.
This feature gives the user a proprietary circuit which is difficult to copy.
Features
• High speed:
Combinatorial and latched outputs
tpd = 6 ns max
Registered outputs
tsu = 5 ns min
telk = 3 ns max
f max = 125 MHz max
• Both 10 KH and 100K 1/0 compatible versions
• Eight output functions with feedback; eight dedicated
inputs
• Eight registered or latched outputs, or four registered or
latched outputs with four combinatorial outputs
• Individually programmable polarity on all logic outputs
• Output enable gate on all registered or latched outputs
• Reliable Titanium Tungsten fuses
• Security fuse to prevent direct copying
• Programmed on most PlD programmers
• Fully Supported by PLANTM Software
• Packaging:
24-pin thin DIP (0.300")
28-pin SCC (leadless Square Chip Carrier)
24-pin QUAD CERPAK
Applications
• Programmable replacement for ECl logic
• Programmable state machine
• Address or instruction decoding
466
Programmable Logic Design Guide
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
-55°C to + 125"C
Temperature Under Bias (Ambient)
Storage Temperature Range
-65°C to + 150"C
VEE Relative to Vee
Any Input Relative to Vee
Lead Temperature (Soldering. 10 seconds)
-7Vto +0.5V
VEE to +0:5V
300°C
ESD rating is to be determined.
Electrical Characteristics Over Recommended Operating Temperature Range for ECL PAL Devices. (Note 1)
10 KH: TA = O"Cto + 75°C, VEE = -5.2V ±5%
100K:TA = O"Cto + 85°C, VEE = -4.5V ±5%
Output Load = 50n + 5 pF to -2.0V
Symbol
VIH
Parameter
High Level Input Voltage
Conditions
Guaranteed Input Voltage
High For All Inputs
10 KH
lOOK
VIL
Low Level Input Voltage
Guaranteed Input Voltage
Low For All Inputs
O°Cto +85°C
O°C
+ 25°C
+75°C
10KH
lOOK
VOH
High Level Output Voltage
VIN = VIH Max. or VIL Min.
lOOK
Low Level Output Voltage
10KH
lOOK
IIH
High Level Input Current
VIN = VIH Max.
(Note 4)
Low Level Input Current
VIN = VIL Min. Except 1/0 Pins
lOOK
lEE
Supply Current
VEE = Max.
All Inputs and
Outputs Open
-1950
-1950
-1950
-1810
mV
10KH
O°Cto + 75°C
O°Cto +B5·C
lOOK
mV
-1475
-840
-810
-735
mV
-880
-1630
-1630
-1600
-1620
mV
220
O°Cto +B5°C
O"C
+ 75°C
O°Cto +B5°C
10KH
Units
-880
O°C
+ 75°C
10 KH
lOOK
IlL
-1810
-1020
-980
-920
-1025
O°Cto +85°C
O"C
+ 25°C
+ 75°C
O°Cto + 85°C
VIN = VIH Max. or VIL Min.
Max
-1480
-1480
-1450
O°Cto +85°C
O°C
+ 25°C
+ 75°C
10KH
VOL
Min
-1170
-1130
-1070
-1165
TA
O°C
+ 25°C
+ 75°C
/LA
0.5
/LA
-260
mA
Operating Conditions
Symbol
VEE
TA
Parameter
Supply Voltage
10 KH
Operating Ambient Temperature (Note 2)
lOOK
10KH
lOOK
RL
CL
tsu
tH
tw
tWMR
Standard 10 KH/l00K Load
Standard 10 KH/l00K Load
Input Setup Time (Note 3)
Input Hold Time (Note 3)
Clock or Enable Pulse Width (Note 3)
Master Reset Pulse Width (Note 3)
Min
-5.46
-4.B
Typ
-5.2
-4.5
Max
-4.94
-4.2
0
+75
0
+B5
Units
V
°C
50
5
n
pF
ns
5
0
ns
4
4
.. .
...
ns
ns
Note t: This product family has been designed to meet the specification In the test table after thenmal eqUlhbnum has been estabhshed. The CircUit IS '" a test
socket or mounted on a printed clrcu" board and transverse air flow graater than 500 linaar fpm is maintained.
Nota 2: Mounted in socket or printed circuit board with transverse airflow exceeding 500 linear feet per minute.
Nota 3: Applies to registered and latched outputs.
Nota 4: Except for clock inputs (350 ,.A) and MR (1 mAl.
Dout
J~±
TLlLl8785-2
New Product Data Sheets
467
Ordering Information
The 16 products in the family are differentiated by their logic
level compatibility (10 KH or 100K), by their output type (registered, latched or mixed combinatorial) and by their clock
configuration (Common ORed or Dual clocks). The family
consists of the following products:
Part
Number
Description
PAL1016RC8
PAL10016RC8
8 Registered Outputs with Common
ORedClock
PAL1016RD8
PAL10016RD8
8 Registers with Dual Clocks
(4 Registers Each)
PAL1016RC4
PAL 10016RC4
4 Registers (Common Clock)
Plus 4 CombinatorialllOs
PAL1016RD4
PAL10016RD4
4 Registers (Dual Clocks)
Plus 4 CombinatorialllOs
PAL1016LC8
PAL10016LC8
8 Latched Outputs with Common
ORedClock
PAL1016LD8
PAL10016LD8
8 Latches with Dual Clocks
(4 Latches Each)
PAL1016LC4
PAL10016LC4
4 Latches (Common Clock)
Plus 4 CombinatorialllOs
PAL1016LD4
PAL10016LD4
4 Latches (Dual Clocks)
Plus 4 CombinatorialllOs
r-----PROGRAMMABlE ARRAY lOGIC FAMilY
. - - - - - ECl I/O COMPATIBilITY
10= 10KH
100= lOOK
......---NUMBER OF ARRAY INPUTS
OUTPUT TYPE
RC = REGISTERED W/COMMON CLOCKS
RD =1iEGISTERED W/DUAL CLOCKS
LC = LATCHED W/COMMON CLOCKS
LD = LATCHED W/DUAl CLOCKS
~fr
NUMBER OF REGISTERED/ LATCHED OUTPUTS
PA~~g~RAMIC DIP
W= QUAD eERPACK
E= CERAMIC LCC
TEMPERATURE RANGE
C=OOC TO +75OC FOR 10KH,
DOC TO +85OC FOR 100 K
r
PAllO 16RD 8 J C
TL/Ll8765-1
Switching Characteristics
Symbol
Measured
Parameter
From
tclK (Note 1)
Clock to Output
tLE (Note 2)
Enable to Output
Min
L,;-J,
a
a
Cn
t
Max
Units
3
ns
3
ns
To
tpD (Note 2, 3)
Input to Output
I
OorllO
6
ns
tpLH (Note 1, 2)
Output Enable
G-J,
at
4.5
ns
tpHl (Note 1, 2)
Output Disable
O-J,
4.5
ns
tMR (Note 1, 2)
Master Reset to Output
Cit
MR t
O-J,
4.5
ns
125
MHz
fMAX (Note 1, 4)
Maximum Frequency
tr
Output Rise Time
t,
Output Fall Time
Note 1: Applies to regIstered outputs.
Note 2: Applies to latched outputs.
Note 3: Applies to combinatorial outputs.
Note 4: 'MAX = (tsu
+ !eLK)-1
Measured Between
20% and 80% points
1
3.5
ns
1
3.5
ns
468
Programmable Logic Design Guide
Timing Waveform-All Registered Outputs
5:r
+ tH ::1_
~
_C IsU
c ---{:
111&"
I
tw
~_ _ _ _ _ _ _ _ _ _ _ _ _ __
50%~""":/~/rl"'/"7'/"7/~/"'T"l/~/rl"'/"7'/"71~/"'T"l/~/rl"'/"7'/"7/~/"'T"l/~/rl"'/"7'1"7/~{
i--IcLK
=I.
50#~--t:-tP-H:O-j (~j r- ~:9
:G _ _ _ _ _ _ _ _
IF
_ _ _ _ _ _ _ _ _...;5.;..;.,0"
50" _
I
1=~IIR=:j
IIR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~5~0"~
S;~
TLlL/8765-3
Timing Waveform-All Latched Outputs
[~€
. .F"",1 ~ ::L
50% ~,..,II""7/..,.I.,.I.,../7""':/,..,I,..,0""7/..,.I.,.I.,../7""':1""1""11""7/""1"'1""/7""':/""1""11""/~{
I III
II--I-Q
G
tP~
tLE
Y ----t:--t-PH-::}-"
5o";f
t..::1 r- '"'1
50" _
I
I=tWIIR=:j
IIR
50"~
50%~
TL/Ll8765-4
New Product Data Sheets
469
Connection Diagrams (24-pin Dual-In-Line Packages)
PAL1016RC4/PAL10016RC4
PAL1016RD4/PAL10016RD4
PAL 1016RC8/PAL10016RC8
PAL 1016RD8/PAL10016RD8
MR
I
24
MR
Vee
I
24
2
I
I
I
22
Q
Q
I/O
21
Q
Q
Q
Vcco
Q
Q
Q
Q
I/O
C,CI
I
C,CI
C,C2
I
G
I/O
Vcco
0
I/O
C,C2
9
I
10
II
14
VEE
12
13
I
VEE
I
Q
Vcco
Vcco
Q
Vee
23
G
TLILl8765-6
TLlL18765-5
PAL1016LC4/PAL10016LC4
PAL1016LD4/PAL10016LD4
PAL 1016LC8/PAL10016LCB
PAL 1016LD8/PAL10016LD8
MR
24
Vee
I
I
23
I
I
I
I
Q
Q
Q
Q
MR
Veeo
Q
Q
L,Li
vee
I
I/O
I/O
0
Vcco
Q
Vcco
Veeo
0
0
Q
0
L.L2
I/o
I/O
L,Li
L,L2
I
I
VEE
I
G
VEE
12
13
G
TLIL18765-8
TLlLl8785-7
Pin Descriptions
Pin
I
Q
Description
Eight dedicated inputs to logic array.
Pin
C,L2
Four or eight outputs from registered or latched logic
functions.
1/0
Four outputs from combinatorial logic functions on
'RC4, 'RD4, 'LC4 and 'LD4. Pin signal fed back as
input into logic array. Pin can be used as input or
output.
C, C1 Clock input for registers on output pins 4, 5, 7 and 8
on dual-clock devices; ORed with C2 to control all
registers on common-clock devices. Data is written
into registers on rising edge of clock.
C, C2 Clock input for registers on output pins 17, 18, 20
and 21 on dual-clock devices; ORed with C1 to control all registers on common-clock devices. Data is
written into registers on rising edge of clock.
C, L1
Latch enable input for latches on output pins 4, 5, 7
and 8 on dual-clock devices; ORed with L2 to control
all latches on common-clock devices. Latches are
transparent (data written into latch) while the enable
signal is low.
MR
Description
Latch enable input for latches on output pins 17,
18,20 and 21 on dual-clock devices; ORed with L1
to control all latches on common-clock devices.
Latches are transparent (data written into latch)
while the enable signal is low.
Master Reset input. Asynchronously resets all registers or latches to the low state while MR is high
(overrides clock and latch enable).
Output enable input. Enables output drivers while G
is low; forces all registered or latched output drivers
to the low state as long as G is high. Register or
latch contents and feedbacks are not affected.
Combinatorial outputs are not affected.
Supply voltage.
Ground for internal circuitry.
Ground for output drivers (4 outputs per Vcca).
470
Programmable Logic Design Guide
Connection Diagrams (28-pin Leadless Square Chip Carrier)
PAL 1016RC4/PAL10016RC4
PAL1016RD4/PAL10016RD4
PAL 1016RC8/PAL10016RC8
PAL1016RD8/PAL10016RD8
:2
""
z
u
>g _
_
25
Q
I/O
5
25
I/O
Q
24
Q
Q
6
24
Q
Vcco
23
Vcco
Vcco
7
8
23
Vcco
NC
22
NC
Q
9
21
Q
I/O
10
20
I/O
C,Cl
11
19
C,C2
Q
5
NC
NC
Q
Q
Q
C,Cl
10
Q
11
C,C2
-
-
>1:1 uz "" -
-
-
-
~
§E '''' -
TLlL/B765-1B
TL/LlB765-17
PAL1016LC4/PAL10016LC4
PAL1016LD4/PAL10016LD4
PAL 1016LC8/PAL10016LC8
PAL 1016LD8/PAL10016LD8
_
""::IE
u
Z
""::IE
.}--
Q
5
Q
I/O
Q
6
Q
Q
-
5
25
I/O
24
Q
7
23
Vcco
8
22
NC
Q
Q
9
21
Q
20
Q
I/O
10
20
I/o
19
L.L2
L,U
11
19
L,Ll
Vcco
8
NC
Q
9
21
Q
10
11
>1:1 uz '''' -
g
> -
NC
7
NC
-
Z
Vcco
Vcco
L,U
u
-
TL/L/B765-19
-
~
§E '''' -
TLlL/B765-20
New Product Data Sheets
471
Connection Diagrams (24-pin Quad Car-Pack)
PAL 1016RC8/PAL10016RC8
PAL 1016RD8/PAL10016RD8
_
_
ICt
PAL 1016RC4/PAL10016RC4
PAL 1016RD4/PAL10016RD4
>1:1
- - ,e»
1:1
>
18
C,C2
1
18
C,Cl
a
a
2
17
a
C,C2
I/O
2
17
C,Cl
I/O
3
16
0
a
3
16
a
Vcco
4
15
Vcco
Vcco
4
15
Veeo
a
a
5
14
Q
a
5
14
a
6
13
a
I/O
6
13
I/O
- - J! ~
0<>:
~::IE
TL/L/B765-22
TL/LlB765-21
PAL 1016LC8/PAL 10016LC8
PAL1016LD8/PAL10016LD8
_
L.LZ
a
a
_
Ie
PAL 1016LC4/PAL10016LC4
PAL 1016LD4/PAL10016LD4
>1:1
-
1
18
I,ll
2
17
3
16
a
a
Vcco
4
15
Vcco
a
a
5
14
6
13
a
a
- - >!:l
-
1:1
'" >
CL2
1
18
I/O
2
17
I/O
a
3
16
0
I,Ii
Vcco
4
15
Vcco
Q
5
14
a
I/O
6
13
I/O
- - J! ~
~
TL/L/B765-23
TL/L/B765-24
472
Programmable Logic Design Guide
Logic Diagram PAL 1016RC8/PAL 10016RC8
INPUT LINE NUt.tBER-+O
2
1
4
3
6
5
8 10
7
9
12 14
11
13 15
11 18
17 19
20 22
21 23
24 26
2S 11
Vee 2~
-
28 30
29 31
23
;-t>-
Qrr
22
~
~'j!J~
PRODUCT LINE
FIRST CELL NU~9ER-:~ 32
96
D
128 '60
:R:t-
192 22~
of:)-,
R
3
.iQ;" poat!G~
;:<:I
256288
320352
384 ~16
4-18<180
R
§:~D>
512 5«
576 608
6~ 672
70~ 736
10
~
~
kJc¥<51~
768 800
832 ~
896 928
960 992
B:I
..
~ 2)!:l[)o
102~'056
1088 1120
"52"8~
'2'6'2~
--
~
>---<>'
~
~~m
Q
[Y
13«1376
,~,«O
,m,~
KJ
~~[)o
,536 ,568
,600 ,632
'66~'696
tJ
!t>-
VCC019
--
1280 1312
B=
1728 1760
!(]
[Y
. "0-
6 Veeo
LQ
q
kJ&<55~
q D-
'792'82~
1856'888
,920 ,952
'9M 2016
~
~15
14
11
~
12 VEE
--
Q
TL/LlB765-9
JEDEC logic array cell number
=
product line first cell number
+
input line number.
473
New Product Data Sheets
Logic Diagram PAL 1016RD8/PAL 10016RD8
INPUT LINE NUM8ER-+O
2
1 ,
"
6
5 7
8
12 1.
10
9
11
13 15
16
20 22
18
17
19
21 2l
24 26 2B.3Q
25 27
Vee 2.
-
29 31
23
;-t>-
22
FIRST ~~~~U~~i~~~_O 32
I?~
o
6. 96
128 160
§:1
192 22•
3
Di w~;
512
576
640
70.
l(]
~
--
256 288
320 352
4<18"",
~~[)c
5••
60B
672
736
j:Ct-"
-0-
~c¥C~R:l
lfJ
960 992
...,...
h
~~[)o
Rt-'"
0I----.".,
rat¥(J~
~
D-
1280 1312
13«1376
1408, ..a
,472 ,504
.-<:I
~~[)o
,66',696
172B1760
1..1':
Veeo 19
-
896 928
1536 '56B
,600 ,632
!CJ
0V
768 BOO
832 as.
~
LQ
R
38-< .,6
,024 ,056
1088 1120
1152 11B4
,216 ,248
e Veeo
21
Q
B=
~ ra&-
22
2
PRODUCT LINE
FIRST CELL NUMBER-+~ 32
~D
96
128 '60
192 224
21
8:
3
2049
4
Ea
256288
320 352
f:8
B:I
!I
384 416
448...,
§;~o-n
~~
DRQ1~
5'2 544
576 608
640 672
704 736
E.(]:j ~~~
-t:8
768
832
896
960
~
. QRD
"'"'
,,-
800
864
928
992
Veco ,9
--
"0-
I~[)o
'024'056
'088 1120
1152 1184
6 Veco
--
1216 1248
~
...,..
LQ
~
ra~
1280 1312
13441376
1408'440
1472'504
KJ
~~D
1536'568
'600'632
1664'696
1728 1760
'792 '824
,856 ,888
'920 '952
1984 2016
"'"'
:1
,7
8=
a~
8
~
D-
~IS
!t>-
14
11
W
,2 VEE
--
Q
TL/L/8785-11
JEOEC logic array cell number
=
product line first cell number + Input line number.
475
New Product Data Sheets
Logic Diagram PAL 1016RD4/PAL 10016RD4
INPUT LINE NUMBER-f,oO
2
1
"
,
6
5
7
8 10 12 I. 16 18 20 22 24 26 28 30
911 13 15 17 19 21 2.3 25 27 29 31
-23
~
22
PRODUCT LlNE-+O
FIRST CELL NUMBER 64 ~~
~~D
128 160
192 224
21
1
S:
3
at!'G1
4
256 288
320 352
3S4 416
..... 480
-~~ rro
512 544
576 608
640 672
704 736
1Q;"
~
p-a~~
ORQ
768 800
960 992
........
~~Do
1024 '056
1088 '120
6 Veea
1152 1184
1216 1248
--
B:
-
- -
22
2
PRODUCT LlNE_O
FIRST CELL NUMBER 6.!!
~p~
~
128 160
0
21
Q
L R
192 22 •
3
iQ;"
w~1
256 288
320 352
384 416
«11480
~2~[)o
512 544
576 608
640 672
704 736
D
~-
-
6 Veeo
--
D
~~
1024 '056
1088 1120
,,52 ,,84
12,6 ,U8
-
0-1
---
22
PRODUCT L1NE-+
FIRST CELL NUMBER ~ 32
96
128 '60
~
~
1
gj
t:8
3B4 416
""'480
~[)o
512 5«
576 608
640 672
704 736
D
~
--
LQ
§:r
~~tii
~
.
10
Veco 19
--
960 992
"'0-
~[)o
a=-
-
'
or
a
or
a
1280'312
13«1376
,408 , «0
'472,51).4.
~~[)o
1536'568
,6°°,632
,664 ,696
B:;
1728 1760
(] ~~
1.Q I
~~
768 BOO
832 B64
896 928
,024 ,056
1088 1120
1152 1184
12,6 ,248
6 Veeo
21
1792'82"
,856 ,888
1920 '952
1984 2016
L
.A 16
....., 15
9 -"
lD -,..
14
11
~
12 VEE
--
TL/L/8765-14
JEDEC logic array cell number ~ product line first cell number
+ input line number.
Programmable Logic Design Guide
478
Logic Diagram PAL 1016LC4/PAL 10016LC4
INPUT LINE
NU~BER-+.
1
2
,
• •
5
• ,. 12 "
7
9
11
16
13 15
18
17 19
20 22
21 2l
Vee 24
2.,. ,. '"
Z:5 'IT
--
29 31
23
:-t>-
22
2
Vee
PRODUCT lINE_O
FIRST CELL NU~BER
64 32
2048
,28 , :
192 224
21
I
Q-1
3
Vee
4
atZJ~
;::8
256 288
320 352
384 416
448<180
~po-pr
~RQ rO
512 544
576 608
640 672
704 736
1(];"
~
p-a~~
768
832
896
960
800
864
928
992
"0-
6VCCO
--
Vee
~2O~Do
,024 ,056
,088 ,,20
,,52 ,,84
,2,6 ,248
~
--
"""'
p~~~
Vee
LQ
12801312
13«1376
PI
U
,<08 ,440
1.472 1504
r-o
Vee
B~4
J:C
1536 '568
,600 ,632
1664 1696
s:;
1728 1760
8
Vcco 19
-
a~~
-;:§
17
I
,792 ,824
,856 ,888
1920 1952
1984 2016
...... 16
~15
9 ......
10 ,.....
14
11
---
22
~~D
~
PRODUCT lINE_O
FIRST CELL NU~BER
64!~
128 160
192 224
21
3
o;Q~
512 5«
576 608
640 672
704 736
iQ]
p-a~ .
768 800
832 864
Q R0
L
960 992
'<>-
i~[)o
1024 1056
1088 1120
1152 1184
6 Veeo
--
1216'248
~
LQ
p
Veeo 19
--
896 928
r---<'"
Vee
~~~
Pr
0-
1280 '312
1344 '376
1408'«0
1472,5(U
~~D
S:
1536'568
1600 632
1664
1728 '760
~696
17
I
Vee
2055~
8
1792 ,82,(
1856 1888
1920 '952
1984 2016
~
-.,
~
I
A
16
...,. 15
9 .......
-v
14
10
11
W
12 VEE
--
TL/l/8765-16
JEOEC logiC array cell number
=
product line first cell number
+ input cell number.
480
Programmable Logic Design Guide
Functional Testing
As with all field-programmable devices, the user of the Eel
PAL provides the final manufacturing step and must assume
some responsibility for testing the programmed device. National's PAL devices undergo extensive testing when they
are manufactured, but their logic function can be fully tested
only after they have been programmed to the user's pattern.
To ensure that the programmed PAL device will operate
properly in your system, National Semiconductor (along with
most other manufacturers of PAL devices) strongly recom-
mends that PAL devices be functionally tested before they
are installed in your system. Even though the number of
post-programming function failures is small, testing the logic
function of the PAL devices before they reach system assembly will save PCB debugging and rework costs. Refer to
National Semiconductor's Application Note #351 and the
Programmable Logic De~ign Guide for more information
about the functional testing of PAL devices.
New Product Data Sheets
481
Physical Dimensions inches (millimeters)
0.404
-(10.26)-
r-
sa
0.065-0.076
(1.651-1.9301
D
TOP
VIEW
BOTTOM
VIEW
SlOE
VIEW
E28A(AEVC)
28-Pln Ceramic Leadless Chip Carrier
Order Number PAL 1016XXXE/PAL10016XXXE
NS Package Number E28A
0.025 RAD
(0.635)
!.ZaD
1-------(32.71) MAX--------l
0.030-0.055
(3.175)
MIN
J24fIR~V
24-Pln Dual-In-Llne Package (J)
Order Number PAL 1016XXXJ/PAL10016XXXJ
NS Package Number J24F
GI
482
Programmable Logic Design Guide
Physical Dimensions inches (millimeters) (Continued)
0370
(9.398)
MIN SQUARE
0.250 -0.360
(6.350-9.144)
TYP
-
~I+-
0.250 -0.360
(6.350 -9.144)
TYP
II
0.004-0.006
(0.102 0.152)
PIN NO.1
IDENT\
1 24 23 22 21 20 1918
2
3
4
5
17
16
15
14
6 7 8 9 1011 1213
l/i
..
-~~
0.075
0.016-0.018
(0.406 -0.457jTYP
_
0.400
--_
1 905
8 •PLCS)
MAX
f- 0.050",0.005
(1.270",0.127)
TYP
(10.16)
SQUARE MAX
GLASS
0.035 -0.050
(0.889-1.270)
0.085
(2.159)
MAX
W24BIREVCI
24-Pin Quad Cerpak
Order Number PAL 1016XXXW/PAL10016XXXW
NS Package Number W24B
New Product Data Sheets
4 ns Eel Programmable
Array logic (PAl®) Family
483
PRELIMINARY
November 1987
General Description
The PAL1016P4A and PAl10016P4A are members of the
National Semiconductor ECl PAL family. The PAL 101
10016P4A is a functional subset of the PAL 10/10016P8
(6 ns tpd) and is compatible in pinout, JEDEC map format,
and programming algorithm. The ECl PAL family utilizes
National Semiconductor's advanced oxide-isolated process
and proven Titanium-Tungsten (Ti-W) fuse technology to
provide user-programmable logic to replace conventional
ECl SSIIMSI gates and flip-flops. Typical chip count reduction gained by using PAL devices is greater than 4:1.
This family allows the systems engineer to customize his
chip by opening fuse links to configure AND and OR gates
to perform his desired logic function. Complex interconnections that previously required time-consuming layout are
thus transferred from PC board to silicon where they can
easily be modified during prototype checkout or production.
The PAL transfer function is the familiar sum-of-products
implemented with a single array of fusible links. The PAL
device incorporates a programmable AND array driving a
fixed OR array. The AND term logiC matrix incorporates 16
complementary inputs and 32 product terms. The 32 product terms are grouped into four OR functions with eight
product terms each. All devices in this series are provided
with output polarity fuses. These fuses permit the designer
to configure each output independently to provide either a
logic true (by leaving the fuse intact) or a logic false (by
programming the fuse) when the equation defining that output is satisfied.
Product terms with all fuses programmed assume a logical
high state, while product terms connected to both the true
and complement of any input assume a logical low state. All
product terms in an unprogrammed part are logically low.
Fuse symbols have been omitted from the logic diagrams to
allow the deSigner use of the diagrams for logiC editing.
These ECl PAL devices may be programmed on many PlD
programmers. Programming is accomplished using TTL
voltage levels. Once programmed and verified, an additional
fuse may be programmed to disable further verification. This
feature gives the user a proprietary circuit which is difficult
to copy.
Features
• High speed:
Combinatorial outputs
tpd = 4 ns max
• Both 10 KH and 100K 110 compatible versions
• Four output functions; sixteen dedicated inputs
• Individually programmable polarity for all logic outputs
• Reliable titanium-tungsten fuses
• Security fuse to prevent direct copying
• Programmed on many PlD programmers
• Fully Supported by PLANTM Software
• Packaging:
24-pin thin DIP (0.300·)
24-pin QUAD CERPAK
Applications
• Programmable replacement for ECl logic
• Address or instruction decoding
Ordering Information
, - - - - - - - PROGRAMMABLE ARRAY lOGIC rAMllY
, - - - - - - ECl I/O COMPATIBLE
10=10KH
100=100K
r - - - - - NUMBER or ARRAY INPUTS
, - - - - OUTPUT TYPE
P = COMBINATORIAL WITH
PROGRAMMABLE POlA1TY
NUMBER or OUTPUTS
SPEED RANGE
NO SYMBOL = STANDARD SPEED (6 n5)
A = HIGH SPEED (4 ns)
PACKAGE
J = CERAMIC DIP
W = ~UAD CERPACK
lrr
TEMPERATURE RANGE
C = OoC TO + 75°C rOR 10 KH
o HOC TO + 850C rOR lOOK
PAL 10 16 P 4 A J C
TL/L/913B-1
PLANTM is a trademark of National Semiconductor Corporation.
PAL" is a registered trademark of and used under license from Monolithic Memories, Inc.
484
Programmable Logic Design Guide
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Temperature Under Bias
-55·C to + 125·C
Storage Temperature Range
-65·C to + 150"C
Vee Relative to Vee
Any Input Relative to Vee
Lead Temperature (Soldering, 10 seconds)
ESO rating is to be determined.
-7V to + 0.5V
Vee to + 0.5V
300"C
Recommended Operating Conditions
Symbol
Vee
T
Min
Typ
Max
10 KH
-5.46
-5.2
-4.94
100K
-4.82
-4.5
-4.19
10 KH
0
+75
100K
0
+85
Parameter
Supply Voltage
Operating Temperature (Note)
Units
V
·C
DC Electrical Characteristics Over Recommended Operating Conditions
Output Load = 500 to - 2.0V
Symbol
VIH
VIL
VOH
VOL
IIH
IlL
lee
Parameter
TA
Min
Max
10KH
O·C
+ 25·C
+ 75·C
-1170
-1130
-1070
-840
-810
-735
100K
O·Cto +85·C
-1165
-880
10 KH
O·C
+ 25·C
+ 75·C
-1950
-1950
-1950
-1480
-1480
-1450
100K
O·Cto +85·C
-1810
-1475
10KH
O"C
+ 25·C
+ 75·C
-1020
-980
-920
-840
-810
-735
100K
O·Cto +85·C
-1025
-880
10 KH
O·C
+ 25·C
+ 75·C
-1950
-1950
-1950
-1630
-1630
-1600
100K
O·Cto +85·C
-1810
-1620
10KH
O"C
+ 75·C
100K
O·Cto +85·C
10 KH
O·C
+ 75·C
100K
O·Cto +85·C
10KH
O·Cto +75·C
100K
O"Cto +85·C
Conditions
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
High Level Input Current
Low Level Input Current
Supply Current
Guaranteed Input Voltage
High For Allinpuis
Guaranteed Input Voltage
Low For All Inputs
VIN
VIN
VIN
VIN
Vee
= VIH Max. or VIL Min.
= VIH Max. or VIL Min.
= VIH Max.
= VIL Min.
= Min.
Allinpuis and Outputs Open
..
..
220
..
Units
mV
mV
mV
mV
/LA
0.5
/LA
-220
mA
Note: Operallng temperatures for CIICUIIs In Dual·ln·Une packages are speCified as ambient temperatures (T A) with CIrCUits In a test socket or mounted on a printed
circuit board and transverse air flow greater than 500 linear fpm is maintained. Operating temperatures for circuils packaged in QUAD CERPAK are specified as
case temperatures (TC). All specifications apply after thermal equilibrium has been established.
New Product Data Sheets
Switching Characteristics
Over Recommended Operating Conditions, Output load: RL =
Symbol
Parameter
son to
485
-2.0V, CL = 5 pF to GND
Measured Test Conditions
tpo
Input to Output
Measured at 50% points
tr.
Output Rise Time
tf
Output Fall Time
Measured between
20% and 80% points
Units
Max
Min
4
ns
0.5
2.5
ns
0.5
2.5
ns
Timing Measurements
INPUTS
Output Load
-O.9V---~
YO%
• -------
-1.7V
t pD
OUTPUTS
Dout
=:!,
~lu",_,
j
:::::::::::::~:5_0-7._.-_-_-_TlIlI913B-7
Connection Diagrams
24-pin Quad Cerpack
Dual-In-Line Package
0
24
Vee
I
2
23
3
22
4
21
5
-
0
0
0
I
-
1.
18
17
I
3
16
0
Veeo
4
15
Veco
0
5
14
0
6
13
,;-<>
VEE
13
12
TL/lI913B-5
TL/L/913B-3
Top View
t:f
>
2
0
Vcco
Veeo
-
486
Programmable Logic Design Guide
Logic Diagram PAL 1016P4A/PAL10016P4A
INPUT LINE NUMBER-+o
2
1
4
3
6
5
7
8 10 12 14 16 18 20 22 24 26 28 30
9 11 13 15 17 19 21 23 25 27 29 31
Vee 24
-
1
23
2
22
3
21
4
PRODUCT LINE
FIRST CELL NUMBER
512
576
640
704
2050
544
608
672
[)o----1l
736
2051
768 800
832 864
896 928
~
Veco 19
--
960 992
2052
1024 1056
1088 1120
1152 1184
1216 1248
6 Veeo
--
~
2053
1280 1312
13441376
1408 1440
1472 1504
L-.o(J
17
8
16
9
15
10
14
11
13
r--<'"
12 VEE
TL/L/9138-4
JEDEC logiC array cell number
=
product line first cell number
+ input line number
Functional Testing
As with all field-programmable devices, the user of the ECl
PAL devices provides the final manufacturing step. While
National's PAL devices undergo extensive testing when
they are manufactured, their logic function can be fully tested only after they have been programmed to the user's pattern.
To ensure that the programmed PAL devices will operate
properly in your system, National Semiconductor (along with
most other manufacturers of PAL devices) strongly recom-
mends that devices be functionally tested before being installed in your system. Even though the number of post-programming functional failures is small, testing the logic function of the PAL devices before they reach system assembly
will save board debugging and rework costs. Refer to National Semiconductor's Application Note #351 and the Programmable Logic Design Guide for more information about
the functional testing of PAL devices.
Please contact your local sales office for a list of current
programming support tools for ECl PAL devices.
New Product Data Sheets
487
Physical Dimensions inches (millimeters)
1.290
'.1125
1---------(32.771 MAX---------o-\
10.1351 RAD
0.030-0.055
10.162-1.3971
__
~~ n~
___
(~_: _:_:!'~_~_IT_Y_P ~~
_________v____
__
__
____-, ___
~~R=="~ ~~:::,:, r--
~I
(2.54 ±O.254I-1
TYP
t:=i-_.
I
0.310-0.410
I ~:~-0.3051
I-- (7.874-10.411-1
J24F{REVGI
24-Pin Ceramic Dual-In-Llne Package
Order Number PAL 1016P4AJC/PAL10016P4AJC
NS Package Number J24F
488
Programmable Logic Design Guide
Physical Dimensions inches (millimeters) (Continued)
..
0.370
19.398)
MIN SQUARE
•
0.250 -0.360
(6.350-9.144)
TYP
-
-I~
0.250-0.360
(6.350-9.144)
TYP
"
0.004-0.006
(0.102 0.152)
PIN NO. 1
IDENT\
1 24 23 22 21 2Q 1918
2
3
4
5
6
17
16
15
14
7 8 9 10 11 1213
0.075
0.016-0.018
(0.406 -0.457)
TYP
•
~~ I-I-~
(10.16)
SQUARE MAX
GLASS
-
kil.905)
8 PLCS
MAX
'-- 0.D50 ",0.D05
(1.270",0.127)
TYP
0.035-0.050
(0.889-1.270)
0.085
12.159)
MAX
W24B(REVC)
24-Pln Quad Cerpak
Order Number PAL 1016P4AWC/PAL10016P4AWC
NS Package Number W24B
13
Package Outlines
0.785
1---(19.939)-----1
Ililimilffi1
15 14
0.025
MAX
13
12
Iiillii1ml
11
10 9 - .
(0.635)
RAD
0.220 - 0.31 0
0.005 - 0.020
(0.127 - 0.508)
RADTYP
0.290 - 0.320
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489
490
Programmable Logic Design Guide
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491
492
Programmable Logic Design Guide
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493
494
Programmable Logic Design Guide
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495
14
Terminology
Term
Explanation
PAL Device
Programmable Array Logic. AND-OR Array with
a programmable AND array and a fixed OR
array.
PROM
Programmable Read-Only Memory. AND-OR
Array with a fixed AND array and a
programmable OR array.
FPLA
Field-Programmable Logic Array. AND-OR Array
with a programmable AND array and a
programmable OR array.
Product Term
(Pn)
Logical AND operation on input variables.
Example: Po = AoA1A1s, PIO = A2As
Summing Term
(Sn)
Logical OR operation on product terms.
Example: S1 = Po + P IO
= AoA1A1S + A2As
Output Polarity
Inversion or Non-inversion of summing term
outputs.
Don't Care
Variable can take any logic state without
affecting logic operation.
Active High
Output is a logic high when Sum-of-Products
expression is true. Within programmable logic
context, refers to a non-inverted output.
Active Low
Output is a logic low when Sum-of-Products
expression is true. Within programmable logic
context, refers to an inverted output.
+
+
Fixed connection.
Programmable connection in virgin array.
497
498
Programmable Logic Design Guide
Term
Explanation
+
Unconnected in programmed part.
+
Programmed, connected.
Maximum Clock Frequency, fMAX :
The highest rate at which the clock input of a
bistable circuit can be driven through its
required sequence while maintaining stable
transitions of logic level at the output with
input conditions established that should cause
changes of output logic level in accordance
with the specification.
High Level Input Current, IIH:
The current into an input when a high level
voltage is applied to that input. •
High Level Output Current, 10H:
The current into an output with input
conditions applied that, according to the
product specification, will establish a high level
at the output. *
Low Level Input Current, IlL:
The current into an input when a low level
voltage is applied to that input. *
Low Level Output Current, 10L:
The current into an output with input
conditions applied that, according to the
product specification, will establish a low level
at the output.'
Off-State (High-Impedance State)
Output Current of a 3-State
Output), loz:
The current into an output having 3-state
capability with input conditions applied that,
according to the product specification, will
establish the high-impedance state at the
output. *
Short-Circuit Output Current, los:
The current into an output when that output is
short-circuited to ground (or other specified
potential) with input conditions applied to
establish the output logic level farthest from
ground potential (or other specified potential). *
Supply Current, Icc:
The current into the Vee Supply terminal of an
integrated circuit. *
Tenninology
Term
499
Explanation
The interval during which a signal is retained at
a specified input terminal after an active
transition occurs at another specified input
terminal.
Notes:
1. The hold time is the actual time between
two events and may be insufficient to
accomplish the intended result. A minimum
value is specified that is the shortest interval
for which correct operation of the logic
element is guaranteed.
2. The hold time may have a negative value, in
which case the minimum limit defines the
longest interval (between the release of data
and the active transition) for which correct
operation of the logic element is guaranteed.
Output Enable Time (of a 3-State
Output) to High Level, tpZH(or
Low Level, tpzd:
The propagation delay time between the
specified reference points on the input and
output voltage waveforms with the 3-state
output changing from a high-impedance (oft)
state to the defined high (or low) level.
Output Enable Time (of a 3-State
Output) to High or Low Level,
tpzx:
The propagation delay time between the
specified reference points on the input and
output voltage waveforms with the 3-state
outP~t changing from a high-impedance (oft)
state to either of the defined active levels (high
or low).
Output Disable Time (of a 3-State
Output) from High Level, tPHZ(or
Low Level, tPLZ):
The propagation delay time between the
specified reference points on the input and
output voltage waveforms with the 3-state
output changing from the defined high (or low)
level to a high-impedance (oft) state.
Output Disable Time (of a 3-State
Output) from High or Low Level,
tpxz:
The propagation delay time between the
specified reference points on the input and
output voltage waveforms with the 3-state
output changing from either of the defined
active levels (high or low) to a high-impedance
(oft) state.
500
'Programmable Logic Design Guide
Term
Explanation
Propagation Delay Time, tpD:
The time between the specified reference points
on the input and output voltage waveforms with
the output changing from one defined level
(high or low) to the other defined level.
Propagation Delay Time,
Low-to-High Level Output, tpLH:
The time between the specified reference
points on the input and output voltage
waveforms with the output changing from the
defined low level to the defined high level.
Propagation Delay Time,
High-to-Low Level Output, tpHL:
The time between the specified reference
points on the input and output voltage
waveforms with the output changing from the
defined high level to the defined low level.
Pulse Width, tw:
The time interval between specified reference
points on the leading and trailing edges of the
pulse waveform.
Setup Time, tsu
The time interval between the application of a
signal that is maintained at a specified input
terminal and a consecutive active transition at
another specified input terminal.
Notes:
1. The setup time is the actual time between
two events and may be insufficient to
accomplish the setup. A minimum value is
specified that is the shortest interval for
which correct operation of the logic
element is guaranteed.
2. The setup time may have a negative value in
which case the minimurv limit defines the
longest interval (between the active
ttansition and the application of the other
signal) for which correct operation of the
logic element is guaranteed.
High Level Input Voltage, VIH:
An input voltage within the more positive (less
negative) of the two ranges of values used to
represent the binary variables.
Note: A minimum is specified that is the least
positive value of high level voltage for which
Terminology
501
Explanation
Term
operation of the logic elements within
specification limits is guaranteed.
High Level Output Voltage, VO H :
The voltage at an output terminal with input
conditions applied that, according to the
product specification, will establish a high level
at the output.
Input Clamp Voltage, VIC:
An input voltage in a region of relatively low
differential resistance that serves to limit the
input voltage swing.
Low Level Input Voltage, VIL :
An input voltage level within the less positive
(more negative) of the two ranges of values
used to represent the binary variables.
Note: A maximum is specified that is the most
positive value of the low level input voltage for
which operation of the logic element within
specification limits is guaranteed.
Low Level Output Voltage, VOL:
The voltage at an output terminal with input
conditions applied that according to the
product specification will establish a low level
at the output.
Negative-Going Threshold
Voltage, Vr-
The voltage level at a transition-operated input
that causes operation of the logic element
according to specification as the input voltage
falls from a level above the positive-going
threshold voltage, Vr + .
Positive-Going Threshold Voltage,
Vr+ :
The voltage level at a transition-operated input
that causes operation of the logic element
according to specification as the input voltage
rises from a level below the negative-going
threshold voltage, VT _ .
*Current out of a terminal is given as a negative value.
Appendix - an Overview of
LSI Testing Techniques
The growth in the complexity and performance of digital circuits can only be
described as explosive. Large-scale integrated circuits are being used today in a variety
of applications, many of which require highly reliable operation. This is causing concern among designers of tests for LSI circuits. The testing of these circuits is difficult for
several reasons:
• The number of faults that has to be considered is large, since an LSI circuit contains
thousands of gates, memory elements, and interconnecting lines, all individually
subject to different kinds of faults.
• The observability and controllability of the internal elements of any LSI circuit are
limited by the available number of I/O pins. As more and more elements are packed
into one chip, the task of creating an adequate test becomes more difficult. A typical
LSI chip may contain 5000 gates but only 40 I/O pins.
• The implementation details of the circuits usually are not disclosed by the
manufacturer. For example, the only source on information about commercially available microprocessors is the user's manual, which details the instruction set and
describes the architecture of the microprocessor at the register-transfer level, with
some information of the system timing. The lack of implementation information eliminates the use of many powerful test generation techniques that depend on the actual
implementation of the unit under test.
• As more and more gates and flip-flops are packed into one chip, new failure modes
- such as pattern-sensitivity faults - arise.! These new types of faults are difficult
to detect and require lengthy test patterns.
• The dynamic nature of LSI devices requires high-speed test systems that can test the
circuits when they are operating at their maximum speeds.
• The bus structure of most LSI systems makes fault isolation more difficult because
many devices - any of which can cause a fault - share the same bus.
© 19B3 IEEE, Reprinted, witb permission, from IEEE MICRO, Vol. 3, No.1, pp. 34, February 19B3.
M.S. Abadir, H.K. Regbbati, Autbors.
503
504
Programmable Logic Design Guide
• Solving the problems above increases the number of test patterns required for a successful test. This in turn increases both the time required for applying that test and
the memory needed to store the test patterns and their results.
LSI testing is a challenging task. Techniques that worked well for SSI and MSI circuits, such as the D-algorithm, do not cope with today's complicated LSI and VLSI circuits. New testing techniques must be developed. In what follows, we describe some
basic techniques developed to solve the problems associated with LSI testing.
A.1
TESTING METHODS
There are many test methods for LSI circuits, each with its own way of generating and
processing test data. These approaches can be divided into two broad categories concurrent and explicit. 2
In concurrent approaches, normal user-application input patterns serve as diagnostic patterns. Thus testing and normal computation proceed concurrently. In explicit
approaches, on the other hand, special input patterns are applied as tests. Hence, normal computation and testing occur at different times.
Concurrent Testing
Systems that are tested concurrently are designed such that all the information
transferred among various parts of the system is coded with different types of error
detecting codes. In addition, special circuits monitor this coded data continuously and
signal detection of any fault.
Different coding techniques are required to suit the different types of information
used inside LSI systems. For example, m-out-of-n codes (n-bit patterns with exactly m
l's and n - m O's) are suitable for coding control Signals, while arithmetic codes are best
suited for coding ALU operands. 3
The monitoring circuits - checkers - are placed in various locations inside the
systems so that they can detect most of the faults. A checker is sometimes designed in a
way that enables it to detect a fault in its own circuitry as well as in the monitored data.
Such a checker is called a self-Checking checker. 3
Hayes and McCluskey surveyed various concurrent testing methods that can be
used with microprocessor-based LSI systems. 2 Concurrent testing approaches provide
the following advantages:
• Explicit testing expenses (e.g., for test equipment, down time, and test pattern generation) are eliminated during the life of the system, since the data patterns used in
normal operation serve as test patterns.
• The faults are detected instantaneously during the use of the LSI chip, hence the first
faulty data pattern caused by a certain fault is detected. Thus, the user can rely on the
correctness of his output results within the degree of fault coverage provided by the
'"",
Appendix
505
error detection code used. In explicit approaches, on the other hand, nothing can be
said about the correctness of the results until the chip is explicitly tested.
• Transient faults, which may occur during normal operation, are detected if they cause
any faulty data pattern. These faults cannot be detected by any explicit
testing method.
Unfortunately, the concurrent testing approach suffers from several problems that
limit its usage in LSI testing:
• The application patterns may not exercise all the storage element or all the internal
connection lines. Defects may exist in places that are not exercised, and hence the
faults these defects would produce will not be detected. Thus, the assumption that
faults are detected as they occur, or at least before any other fault occurs, is no
longer valid. Undetected faults will cause fault accumulation. As a result, the fault
detection mechanism may fail because most error detection codes have a limited
capability for detecting multiple faults.
• Using error detecting codes to code the information signals used in an LSI chip
requires additional I/O pins. At least two extra pins are needed as error signal indicators. (A single pin cannot be used, since such a pin stuck at the good value could go
undetected.) Because of constraints on pin count, however, such requirements cannot be fulfilled.
• , Additional hardware circuitry is required to implement the checkers and to increase
the width of the data carriers used for storing and transferring the coded information.
• Designing an LSI circuit for concurrent testing is a much more complicated task
than designing a similiar LSI circuit that will be tested explicitly.
• Concurrent approaches provide no control over critical voltage or timing parameters.
Hence, devices cannot be tested under marginal timing and electrical conditions.
• The degree of fault coverage usually provided by concurrent methods is less than
that provided by explicit methods.
The above-mentioned problems have limited the use of concurrent testing for most
commercially available LSI circuits. However, as digital systems grow more complex and
difficult to test, it becomes increasingly attractive to build test procedures into the UUT
(unit under test) itself. We will not consider the concurrent approach further in this
article. For a survey of work in concurrent testing, see Hayes and McCluskey.2
Explicit Testing
All explicit testing methods separate the testing process from normal operation. In general, an explicit testing process involves three steps:
• Generating the test patterns. The goal of this step is to produce those input patterns which will exercise the UUT under different modes of operation while trying
to detect any existing fault.
....
506
Programmable Logic Design Guide
• Applying the test patterns to the UUT. There are two ways to accomplish this
step. The first is external testing - the use of special test equipment to apply the test
patterns externally. The second is internal testing - the application of test patterns
internally by forcing the DDT to execute a self-testing procedure. 2 Obviously, the
second method can only be used with systems that can execute programs (for example, with microprocessor-based systems.) External testing gives better control over
the test process and enables testing under different timing and electrical conditions.
On the other hand, internat" testing is easier to use because it does not need special
test equipment or engineering skills.
• Evaluating the responses obtained from the UUT. This step is designed with
one of two goals in mind. The first is the detection of an erroneous response, which
indicates the existence of one or more faults (go/no-go testing). The other is the isolation of the fault, if one exists, in an easily replaceable module (fault location testing). Our interest in this article will be go/no-go testing, since fault location testing
of LSI circuits sees only limited use.
Many explicit test methods have evolved in the last decade. They can be distinguished by the techniques used to generate the test patterns and to detect and evaluate
the faulty responses (Figure A.l.l). In what follows, we concentrate on explicit testing
GOOD
RESPONSE
GENERATION
Figure A.I.I
LSI Test Technology
COMPACT
TESTING
Appendix
507
and present in-depth discussions of the methods of test generation and response evaluation employed with explicit testing.
A.2
TEST GENERATION TECHNIQUES
The test generation process represents the most important part of any explicit testing
method. Its main goal is to generate those test patterns that, when applied to the UUT,
sensitize existing faults and propagate a faulty response to an observable output of the
UUT. A test sequence is considered good if it can detect a high percentage of the possible
UUT faults; it is considered good, in other words, if its degree ofjault coverage is high.
Rigorous test generation should consist of three main activities:
• Selecting a good descriptive model, at a suitable level, for the system under consideration. Such a model should reflect the exact behavior of the system in all its possible modes of operation.
• Developing a fault model to define the types of faults that will be considered during
test generation. In selecting a fault model, the percentage of possible faults covered
by the model should be maximized, and the test costs associated with the use of the
model should be minimized. The latter can be accomplished by keeping the complexity of the test generation low and 'the length of the tests short. Clearly these
objectives contradict one another - a good fault model is usually found as a result
of a trade-off between them. The nature of the fault model is usually influenced by
the model used to describe the system.
• Generating tests to detect all the faults in the fault model. This parr of test generation is the soul of the whole test process. Designing a test sequence to detect a certain fault in a digital circuit usually involves two problems. First, the fault must be
excited; i.e., a certain test sequence must be applied that will force a faulty value to
appear at the fault site if the fault exists. Second, the test must be made sensitive to
the fault; i.e., the effect of the fault must propagate through the network to an
observable output.
Rigorous test generation rests heavily on both accurate descriptive (system)
models and accurate fault models.
Test generation for digital circuits is usually approached either at the gate-level or
at the functional level. The classical approach of modeling digital circuits as a group of
connected gates and flip-flops has been used extensively. Using this level of description, test designers introduced many types of fault models, such as the classical stuck-at
model. They also assumed that such models could describe physical circuit failures in
terms of logic. This assumption has sometimes restricted the number of physical failures that can be modeled, but it has also reduced the complexity of test generation
since failures at the elementary level do not have to be considered.
Many algorithms have been developed for generating tests for a given fault in combinational networks. 1,4,5,6,7 However, the complexity of these algorithms depends on
the topology of the network; it can become very high for some circuits. Ibarra and
508
Programmable Logic Design Guide
',.NP.;cOMPt::.ete. PROBLEMS
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,Jynomial. For example, the best algOrithms described in·H9roVV~t2;:.;thd Sabni's,
i,book2 for thetra'veling salesman anQ the knapsack probl~ haY~'a'complexity o(!',
·.··.·O(n22n ) and 0(2n/2); respecti'veli:In)t\c"quest to develop' efficient algorithms;no,•.
~·:one has beenahk todeve!op ,a,p{)l¥i.W¢j;}ltime algoritbm'fbrany problem ,4:1 the,~:.
secondgroup',:f'~" . "
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. . The theory of NP~<;C)n1Pleteness 'does not provide a method for obtaining'
polynomW-timealgorithms for these problems.· Bitt neither does' it say thataigO:~"";
. rithms of thiS compleXity do not exisCWhatitdoes show isiliat·.rnanyof~e'!<:
. problems for whi~h'~ll~re is no kno~'pofttJOrhial~timealgOrithIb::'are.compu~-::.~;
tionally related, Infact, a problem that 15 NP,:c,omplete has the propeftythaqt (;~:,.',
be solved in pOlynomhll.time.if.:l,U,othet:NP-com:plete problems ·.can.also,be::'
solved in polynomial time.
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Sahni have shown that the problem of generating tests to detect single stuck-at faults in
a combinational circuit modeled at the gate level is an NP-complete problem. 8 Moreover, if the circuit is sequential, the problem can become even more difficult depending
on the deepness of the circuit's sequential logic.
Thus, for LSI cicuits having many thousands of gates, the gate level approach to
the test generation problem is not very feasible. A new appoach, the functional level, is
needed,
Another important reason for conSidering faults at the functional level is the constraint imposed on LSI testing by a user environment - the test patterns have to be generated without a knowledge of the implementation details of the chip at the gate level.
Appendix
509
The only source of information usually available is the typical IC catalog, which details
the different modes of operation and describes the general architecture of the circuit.
With such information, the test designer finds it easier to define the functional behavior
of the circuit and to associate faults with the functions. He can partition the UUT into various modules such as registers, multiplexers, ALUs, ROMs, and RAMs. Each module can
be treated as a "black box" performing a specified input/output mapping. These modules
can then be tested for functional failures; explicit consideration of faults affecting the
internal lines is not necessary. The example given below clarifies the idea.
Consider a simple one-out-of-four multiplexers such as the one shown in Figure
A2.1. This multiplexer can be modeled at the gate level as shown in FigureA.2.1(a), or at
the functional level as shown in Figure A2.1(b).
y
x
z
w
..t---------~------~
Co~~------~~------
C,~~-------H~-------+t-----~~~-----,
u
(a)
(b)
Figure A.2.1
z w
x y
u
C,
Co
U
0
0
x
0
1
Y
1
0
Z
1
1
W
(a) A One-out-of-four Multiplexer-gate-Ievel Description;
(b) Functional-level Description.
A possible fault model for the gate-level description is the single stuck-at fault
model. With this model, the fault list may contain faults such as the line labeled with
''/'' is stuck at 0, or the control line "Co" is stuck at 1.
At the functional level, the multiplexer is considered a black box with a
well-defined function. Thus, a fault model for it may specify the following as possible
faults: selection of wrong source, selection of no source, or presence of stuck-at faults
in the input lines or in the multiplexer output. With this model, the fault list may contain faults such as source "X" is selected instead of source "Y," or line "2" is stuck at 1.
510
Programmable Logic Design Guide
Ad hoc methods - which determine what faults are the most probable - are
sometimes used to generate fault lists. But if no fault model is assumed, then the tests
derived must be either exhaustive or a rather ad hoc check of the functionality of the
system. Exhaustive tests are impossible for even small systems because of the enormous number of possible states, and superficial tests provide neither good coverage
nor even an indication of what faults are covered.
Once the fault list has been defined, the next step is to find the test patterns
required to detect the faults in the list. As previously mentioned, each fault first has to
be excited so that an error signal will be generated somewhere in the DDT. Then this
signal has to be sensitized at one of the observable outputs of the DDT. The three examples below describe how to excite and sensitize different types of faults in the types of
modules usually encountered in LSI circuits.
Consider the gate-level description of the three-bit incrementer shown in Figure A2.2.
C1
0---++---1
Figure A.2.2
Gate-level Description of a Three-Bit Incrementer
The incrementer output, Y2 Y I Yo, is the binary sum of Cj and the three-bit binary
number X2XIX O, while Co is the carry-out bit of the sum. Note that Xo(Y o) is the least
significant bit of the incrementer input (output).
Assume we want to detect the fault "linefis stuck at 0." To excite that fault we will
force a 1 to appear on linefso that, if it is stuck at 0, a faulty value will be generated at
the fault site. To accomplish this both Xo and Cj must be set to 1. To sensitize the faulty
at f, we have to set XI to 1; this will propagate the fault to Y2 independent of the value
of X2. Note that if we set Xl to 0, the fault will be masked since the AND gate output
will be 0, independent of the value atf. Note also that X2 was not specified in the above
test. However, by setting X2 to 1, the fault will propagate to both Y2 and Co, which
makes the response evaluation task easier.
Consider a microprocessor RAM and assume we want to generate a test sequence
to detect the fault "accessing word i in the RAM results in accessing the wordj instead."
°
Appendix
511
To excite such a fault, we will use the following sequence of instructions (assume a
microprocessor with single-operand instructions):
Load the word 00 . . . 0 into the accumulator.
Store the accumulator contents into memory address j.
Load the word 11 . . . 1 into the accumulator.
Store the accumulator contents into memory address i.
If the fault exists, these instructions will force all ... 1 word to be stored in memory address j instead of 00 ... O. To sensitize the fault, we need only read what is in
memory address j, using the appropriate instructions. Note that the RAM and its fault
have been considered at the functional level, since we did not specify how the RAM is
implemented.
Consider the program counter (PC) of a microprocessor and assume we want to generate a test sequence that will detect any fault in the incrementing mode of this PC, i.e.,
any fault that makes the PC unable to be incremented from x to x + 1 for any address x.
One way to excite this fault is to force the PC to step through all the possible addresses.
This can be easily done by initializing the PC to zero and then executing the no-operation
instruction x + 1 times. As a result, the PC will contain an address different than x + 1. By
executing another no-operation instruction, the wrong address can be observed at the
address bus and the fault detected. In practice, such an exhaustive test sequence is very
expensive, and more economical tests have to be used. Note that, as in the example
immediately above, the problem and its solution have been considered at the functional
level.
Four methods are currently used to generate test patterns for LSI circuits: manual
test generation, algorithmic test generation, simulation-aided test generation, and random test generation.
Manual Test Generation
In manual test generation, the test designer carefully analyzes the DDT. This analysis
can be done at the gate level, at the functional level or at a combination of the two. The
analysis of the different parts of the DDT is intended to determine the specific patterns
that will excite and sensitize each fault in the fault list. At one time, the manual
approach was widely used for medium-and small-scale digital circuits. Then, the formulation of the D-algorithm and similar algorithms eliminated the need for analyzing
each circuit manually and provided an efficient means to generate the required test patterns. l •5 However, the arrival of LSI circuits and microprocessors required a shift back
toward manual test generation techniques, because most of the algorithmic techniques
used with SSI and MSI circuits were not suitable for LSI circuits.
Manual test generation tends to optimize the length of the test patterns and provides a relatively high degree of fault coverage. However, generating tests manually
takes a considerable amount of effort and requires persons with special skills. Realizing
512
Programmable Logic Design Guide
that test generation has to be done economically, test designers are now moving in the
direction of automatic test generation.
One good example of manual test generation is the work done by Sridhar and
Hayes,9 who generated test patterns for a simple bit-sliced microprocessor at the functional level.
A bit-sliced microprocessor is an array of n identical ICs called slices, each of which
is a simple processor for operands of kbit length, where k is typically 2 or 4. The interconnections among the n slices are such that the entire array forms a processor for nkbit
operands. The simplicity of the individual slices and the regularity of the interconnections make it feasible to use systematic methods for fault analysis and test generation.
Sridhar and Hayes considered a one-bit processor slice as a simplified model for
the commercially available bit-sliced processors such as the Am2901. 1O A slice can be
modeled as a collection of modules interconnected in a known way. These modules are
regarded as black boxes with well-defined input-output relationships. Examples of
these functional modules are ALUs, multiplexers, and registers. Combinational modules are described by their truth tables, while sequential modules are defined by their
state tables (or state diagrams).
The following fault categories were considered:
• For combinational modules, all possible faults that induce arbitrary changes in the
truth table of the module, but that cannot convert it into a sequential circuit.
• For sequential modules, all possible faults that can cause arbitrary changes in the
state table of the module without increasing the number of states.
Only one module was assumed to be faulty at any time.
To test for the faults allowed by the above-mentioned fault model, all possible
input patterns must be applied to each combinational module (exhaustive testing), and
a checking sequence ll to each sequential module. In addition, the responses of each
module must be propagated to observable output lines. The tests required by the individual modules were easily generated manually - a direct consequence of the small
operand size (k = 1). And because the slices were identical, the tests for one slice were
easily extended to the whole array of slices. In fact, Sridhar and Hayes showed that an
arbitrary number of simple interconnected slices could be tested with the same number of tests as that required for a single slice, as long as only one slice was faulty at one
time. This property is called C-testability. Note that the use of carry-Iookahead when
connecting slices eliminates C-testability. Also note that slices with operand sizes equal
to 2 or more usually are not C-testable.
The idea of modeling a digital system as a collection of interconnected functional
modules can be used in modeling any LSI circuit. However, using exhaustive tests and
checking sequences to test individual modules is feasible only for toy systems. Hence,
the fault model proposed by Sridhar and Hayes, though very powerful, is not directly
applicable to LSI testing.
Appendix
513
PATH SENSITIZATION AND THE D·ALGORITHM
One of the classical fault detection methods at the gate and flip-flop level is the Dalgorithm 1,5 employing the path sensitization testing technique. 4 The basic principle involved in path sensitization is relatively simple. For an input X; to detect a
fault "line a is stuck atj,j= 0,1," the input X; must cause the signal a in the normal (fault-free) circuit to take the value;' This condition is necessary but not sufficient to detect the fault. The error signal must be propagated along some path
from its site to an observable output.
To generate a test to detect a stuck-at fault in a combinational circuit, the following path sensitization procedure must be followed:
• Excitation-The inputs must be specified so as to generate the appropriate
value (0 for stuck-at 1 and 1 for stuck-at 0) at the site of the fault.
• Error propagation-A path from the fault site to an observable output must be
selected, and additional signal values to propagate the fault signal along this
path must be specified.
• Line justification-Input values must be specified so as to produce the signals
values specified in the step above.
There may be several possible choices for error propagation and line justification, Also, in some cases there may be a choice of ways in which to excite the
fault. Some of these choices may lead to an inconsistency, and so the procedure
must backtrack and consider the next alternative. If all the alternatives lead to an
inconsistency, this implies that the fault cannot be detected.
To facilitate the path sensitization process, we introduce the symbol D to represent a signal which has the value 1 in a normal circuit and a in a faulty circuit, and
i5 to represent a signal which has the value 0 in a normal circuit and 1 in a faulty
circuit. The path sensitization procedure can be formulated in terms of a cubical
algebra 1,5 to enable automatic generation of test. This also facilitates test generation for more complex fault models and for fault propagation through complex
logic elements.
We shall define three types of cubes (Le" line values specified in positional
notation):
• For a circuit element E which realizes the combinational functionJ, the "primitive cubes" offer a typical presentation of the prime implicants of J and 1
These cubes concisely represent the logical behavior of E.
• A "prilll.!tive D-cube of a fault" in a logic element E specifies the minimal input
that must be applied to E in order to produce an error signal (D· or
. conditions
_
.J,:,
:;.Dyat the output of E.
514
Programmable Logic Design Guide
• The "propagation D:~:
derived in Step 3.
:'>" ' " ' , ".'
, .
'..
<, "':':~(,\, -.",
'<
"~
.:.,.
.
."
.:.';'~., ~~i~'~1i
5. Step$ 3 and 4 are repeated until the faulty signal has bee'4.RtopaS?-t<::d"t~'~,9~"':':~1
'put of the circuit. · · h ' c , " " .. ".:' . " ) ' "
~. " .... ';,,:
','
~>
Appendix
515
6. Line justification-Execution of Steps 1 to 5 may result in specifying the output value of an element E but leaving some of the inputs to the element unspecified. The unspecified inputs of such an element are assigned values so as to
produce the desired output value. This is done by intersecting the test cube with
any primitive cube of the element which has no specified Signal values that differ
from those of the test cube.
7. Implication of line justification-Implication is performed on the new test
cube derived in Step 6.
, 8. 'Steps 6 and 7 are repeated until all specified element outputs have been justified. Backtracking may again be required.
References
1. M.A. Breuer and A.D. Friedman, Diagnosis and Reliable Design Of Digital Sys-
tems, Computer Science Press, Washington, DC, 1976.
4. D.B. Armstrong, "On Finding a Nearly Minimal Set of Fault Detection Tests for
Combinatorial Nets;' IEEE Trans. Electronic Computers, Vol. EC-15, No. Z,
Feb. 1966, pp. 63-73 .
.5.
J. P. Roth, W.G. Bouricius, and P.R. Schneider, "Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits," IEEE
Trans. Electronic Computers, Vol. EC~16, No.5, Oct. 1967, pp. 567-580.
Algorithmic test generation
In algorithmic test generation, the test designer devises a set of algorithms to generate the
l's and O's needed to test the UUT. Algorithmic test techniques are much more economical than manual techniques. They also provide the test designer with a high level of flexibility. Thus, he can improve the fault coverage of the tests by replacing or modifying
parts of the algorithms. Of course, this task is much simpler than modifying the l's and
O's in a manually generated test sequence.
Techniques that use the gate-level description of the UUT, such as path sensitization4 and the D-algorithm,5 can no longer be used in testing complicated LSI circuits.
Thus, the problem of generating meaningful sets of tests directly from the functional
description of the UUT has become increasingly important. Relatively little work has
been done on functional-level testing of LSI chips that are not memory elements. 9 ,12,13,14,15,16,17 Functional testing of memory chips is relatively simple because
of the regularity of their design and also because their components can be easily controlled and observed from the outside. Various test generation algorithms have been
516
Programmable Logic Design. Guide
developed to detect different types of faults in memories. 1, 18 In the rest of this section
we will concentrate on the general problem of generating tests for irregular LSI chips,
i.e., for LSI chips which are not strictly memory chips.
It is highly desirable to find an algorithm that can generate tests for any LSI circuit,
or at least most LSI circuits. One good example of work in this area is the technique
proposed by Thatte and Abraham for generating tests for microprocessors. 12 ,13
Another approach, pursued by the authors of this article, is a test generation procedure
capable of handling general LSI circuits. 15 ,16,17
The Thatte-Abraham Technique
Microprocessors constitute a high percentage of today's LSI circuits. Thatte and Abraham 12 ,13 approached the microprocessor test generation problem at the functional
level.
The test generation procedure they developed was based on:
• A functional description of the microprocessor at the register-transfer level. The
model is defined in terms of data flow among storage units during the execution of
an instruction. The functional behavior of a microprocessor is thus described by
information about its instruction set and the functions performed by each instruction .
• A fault model describing faults in the various functional parts of the UUT (e.g., the
data transfer function, the data storage function, the instruction decoding and control function). This fault model describes the faulty behavior of the UUT without
knowing its implementation details.
The microprocessor is modeled by a graph. Each register in the microprocessor
(including general-purpose registers and accumulator, stack, program counter, address
buffer, and processor status word registers) is represented by a node of the graph.
Instructions of the microprocessors are classified as being of transfer, data manipulation, or branch type. There exists a directed edge (labeled with an instruction) from
one node to another if during an execution of the instruction data flow occurs from the
register represented by the first node to that represented by the second. Examples of
instruction representation are given in Figure A2.3.
Having described the function or the structure of the UUT, one needs an appropriate fault model in order to derive useful tests. The approach used by Thatte and Abraham is to partition the various functions of a microprocessor into five classes: the
register decoding function, the instruction decoding and control function, the data
storage function, the data transfer function, and the data manipulation function. Fault
models are derived for each of these functions at a higher level and independently of
the details of implementation for the microprocessor. The fault model is quite general.
Tests are derived allowing any number of faults, but only in one function at a time; this
restriction exists solely to cut down the complexity of test generation.
Appendix
(a) .
Figure A.2.3
(b)
(e)
517
Cd)
Representations of Microprocessor Instruction - 11, (a) Transfer
Instruction, R2-RI; (b) Add Instruction, R3-RI + R2; (c) 13, OR
Instruction, R2 - R 1 OR R2; (d) 14 Rotate Left Instruction.
The fault model for the register decoding function allows any possible set of registers to be accessed instead of a particular register. (If the set is null then no register is
accessed.) This fault model is thus very general and independent of the actual realization of the decoding mechanism.
For the instruction decoding and control function, the faulty behavior of the
microprocessor is specified as follows. When instruction If, is executed anyone of the
following can happen:
• Instead of instruction Ij, some other instruction Ik is executed. This fault is denoted
by F(I/I k).
• In addition to instruction If' some other instruction Ik is activated. This fault is
denoted by F(I/If + Ik).
• No instruction is executed. This fault is denoted by F(I/¢).
Under this specification, any number of instructions can be faulty.
In the fault model for the data storage function, any cell in any data storage module
is allowed to be stuck at a or 1. This can occur in any number of cells.
The fault model for the data transfer function includes the following types of faults:
• A line in a path used in the execution of an instruction is stuck at
a or
1.
• Two lines of a path used in the instruction are coupled; i.e., they fail to carry different logic values.
Note that the second fault type cannot be modeled by single stuck-at faults. The
transfer paths in this fault model are logical paths and thus will account for any failure
in the actual physical paths.
Since there is a variety of designs for the AL U and other functional units such as
increment or shift logic, no specific fault model is used for the data manipulation function. It is assumed that complete test sets can be derived for the functional units for a
given fault model.
By carefully analyzing the logical behavior of the microprocessor according to the
fault models presented above, Thatte and Abraham formulated a set of algorithms to
518
Programmable Logic Design Guide
generate the necessary test patterns. These algorithms step the microprocessor through
a precisely defined set of instructions and addresses. Each algorithm was designed for
detecting a particular class of faults, and theorems were proved which showed exactly
the kind of faults detected by each algorithm. These algorithms employ the excitation
and sensitization concepts previously described.
To gain insight into the problems involved in using the algorithms, Thatte investigated the testing of an eight-bit microprocessor from Hewlett-Packard. 12 He generated
the test patterns for the microprocessor by hand, using the algorithms. He found that
96 percent of the single stuck-at faults that could affect the microprocessor were
detected by the test sequence he generated. This figure indicates the validity of the
technique.
The Abadir-Reghbati technique
Here we will briefly describe a test generation technique we developed for LSI circuits. 15 ,16 We assumed that the tests would be generated in a user environment in
which the gate-and flip-flop-Ievel details of the chip were not known.
We developed a module-level model for LSI circuits. This model bypasses the gate
and flip-flop levels and directly describes blocks of logic (modules) according to their
functions. Any LSI circuit can be modeled as a network of interconnected modules
such as counters, registers, ALUs, ROMs, RAMs, multiplexers, and decoders.
Each module in an LSI circuit was modeled as a black box having a number of nmctions defined by a set of binary decision diagrams (see box, page 521 ).19 This type of
diagram, a functional description tool introduced by Akers in 1978, is a concise means
for completely defining the logical operation of one or more digital functions in an
implementation-free form. The information usually found in an Ie catalog is sufficient to
derive the set of binary decision diagrams describing the functions performed by the different modules in a device. These diagrams - like truth tables and state tables - are
amenable to extensive logical analysis. However, unlike truth tables and state tables, they
do not have the unpleasant property of growing exponentially with the number of variables involved. Moreover, the diagrams can be stored and processed easily in a digital computer. An important feature of these diagrams is that they state exactly how the module
will behave in everyone of its operation modes. Such information can be extracted from
the module's diagrams in the form of a set of experiments. 15,20 Each of these experiments
describes the behavior of the module in one of its modes of operation. The structure of
these experiments makes them suitable for use in automatic test generation.
We also developed a functional-level fault model describing faulty behavior in the
different modules of an LSI chip. This model is quite independent of the details of
implementation and covers functional faults that alter the behavior of a module during
one of its modes of operation. It also covers stuck-at faults affecting any input or output
pin or any interconnection line in the chip.
Using the above-mentioned models, we proposed a functional test generation procedure based on path sensitization and the D-algorithm. 15 The procedure takes the
Appendix
519
module-level model of the LSI chip and the functional description of its modules as
parameters and generates tests to detect faults in the fault model. The fault collapsing
technique! was used to reduce the length of the test sequence. As in the D-algorithm,
the procedure employs three basic operations, namely implication, D-propagation, and
line justification. However, these operations are performed on functional modules.
We also presented algorithmic solutions to the problems of performing these operations on functional modules. 16 For each of the three operations, we gave an algorithm
which takes the module's set of experiments and current state (i.e., the values assigned
to the module inputs, outputs, and internal memory elements) as parameters and generates all the possible states of the module after performing the required operation.
We have also reported our efforts to develop test sequences based on our test generation procedure for typical LSI circuits.17 More specifically, we considered a one-bit
microprocessor slice C that has all the basic features of the four-bit Am2901 microprocessor slice. 10 The circuit C was modeled as a network of eight functional modules: an
ALD, a latch register, an addressable register, and five multiplexers. The functions of the
individual modules were described in terms of binary decision diagrams or equivalent
sets of experiments. Tests capable of detecting various faults covered by the fault model
were then generated for the circuit C. We showed that if the fault collapsing technique
is used, a significant reduction in the length of the final test sequence results.
The test generation effort was quite straightforward, indicating that the technique
can be automated without much difficulty. Our study also shows that for a simplified
version of the circuit C the length of the test sequence generated by our technique is
very close to the length of the test sequence manually generated by Sridhar and Hayes 9
for the same circuit. We also described techniques for modeling some of the features of
the Am2909 four-bit microprogram sequencerlO that are not covered by the circuit C.
The results of our case study were quite promising and showed that our technique
is a viable and effective one for generating tests for LSI circuits.
Simulation-aided Test Generation
Logic simulation techniques have been used widely in the evaluation and verification of
new digital circuits. However, an important application of logic simulation is to interpret the behavior of a circuit under a certain fault or faults. This is known asfault simulation. To clarify how this technique can be used to generate tests for LSI systems, we
will first describe its use with SSIIMSI-type circuits.
To generate a fault simulator for an SSIIMSI circuit, the following information is
needed:!
• the gate-level description of the circuit, written in a special language;
• the initial conditions of the memory elements; and
• a list of the faults to be simulated, including classical types of faults such as stuck-at
faults and adjacent pin shorts.
520
Programmable Logic Design Guide
The above is fed to a simulation package which generates the fault simulator of the
circuit under test. The resulting simulator can simulate the behavior of the circuit
under normal conditions as well as when any faults exist.
Now, by applying various input patterns (either generated by hand, by an algorithm, or at random), the simulator checks to see if the output response of the correct
circuit differs from one of the responses of the faulty circuits. If it does, then this input
pattern detects the fault which created the wrong output response; otherwise the input
pattern is useless. If an input pattern is found to detect a certain fault, this fault is
deleted from the fault list and the process continues until either the input patterns or
the faults are finished. At the end, the faults remaining in the fault list are those which
cannot be detected by the input patterns. This directly measures the degree of fault
coverage of the input patterns used.
Two examples of this type of logic simulator are LAMP - the Logic Analyzer for
Maintenance Planning developed at Bell Laboratories,21 and the Testaid III fault simulator developed at the Hewlett-Packard Company. 12 Both work primarily at the gate level
and simulate stuck-at faults only. One of the main applications of such fault simulators
is to determine the degree of fault coverage provided by a test sequence generated by
any other test generation technique.
There are two key requirements that affect the success of any fault simulator:
• the existence of a software model for each primitive element of the circuit, and
• the existence of a good fault model for the DDT which can be used to generate a
fault list covering most of the actual physical faults.
These two requirements have been met for SSI/MSI circuits, but they pose serious
problems for LSI circuits. If it can be done at all, modeling LSI circuits at the gate level
requires great effort. One part of the problem is the lack of detailed information about
the internal structure of most LSI chips. The other is the time and memory required to
simulate an LSI circuit containing thousands of gates. Another severe problem facing
almost all LSI test generation techniques is the lack of good fault models at a level
higher than the gate level.
The Abadir-Reghbati description model proposed in the previous section permits
the test designer to bypass the gate-level description and, using binary decision diagrams, to define blocks of logic according to their functions. Thus, the simulation of
complex LSI circuits can take place at a higher level, and this eliminates the large time
and memory requirements. Furthermore, the Abadir-Reghbati fault model is quite efficient and is suitable for simulation purposes. In fact, the implication operation 16
employed by the test generation procedure represents the main building block of any
fault simulator. It must be noted that fault simulation techniques are very useful in optimizing the length of the test sequence generated by any test generation technique.
Appendix
521
BINARY DECISION DIAGRAMS
Binary decision diagrams are a means of defining the logical operation of digital
functions. 19 They tell the user how to determine the output value of a digital function by examining the values of the inputs. Each node in these diagrams is associated with a binary variable, and there are two branches coming out from each
node. The right branch is the" 1" branch, while the left branch is the "0" branch.
Depending on the value of the node variable, one of the two branches will be
selected when the diagram is processed.
To see how binary decision diagrams can be used, consider the half-adder
shown in Figure A2.4(a). Assume we are interested in defining a procedure to
determine the value of C, given the binary values of X and Y We can do this by
looking at the value ofX. If X = O,then C::; 0, and we are finished. If X = 1, we look
at Y. If Y = 0, then C '" 0, else C = 1, and in either case we are finished. Figure
A2.4(b) shows a simple diagram of this procedure. By entering the diagram at the
node indicated by the arrow labeled with C and then proceeding through the diagram following the appropriate branches until a or 1 value is reached, we can
determine the value C. Figure A2.4(c) shows the diagram representing the function S of the half-adder.
°
x
y
c
s
HALF·ADDER
o
c
1
o
o
S
(a)
(b)
Figure A.2.4 (a) A Half-add~r; (b) Binary Decision Diagram for C =
Decision Diagram for S = X €a y
(c)
x. Yj (c) Binary
To simpUfy the diagrams, any diagram node which has two branches as exit
branches can be replaced by the variable itself or its complement. These variables
are called exit variables. Figure A2.5 shows how this convention is used to sim':p!iiji the,diagrarns describing the half-adder.
,~..
".'>..'
,
':,
'
522
Programmable Logic Design Guide
c
S
·A/~i
"0 "
Figure A.2.5
"
v
y
,
"
y
Simplified Binary Decision Diagram~ f~r; theffillf:ad~~ ,
In the previous discussion, we have considered only·Simple'diagrams in which
the variables within the nodes are primaryillP\;lt,variaNe,s:.. H~eyer, we can expand .
the scope of these diagrams by using auXjliary,~UWI~saStl>:ehQp.<:; Varl\lbles. These
auxiliary variables are defined by theii~~.;;rn:us,'when'lis.~~~ll~cNl1ter5.'Such ,
~ node variable: sayg, while, tra,cinga,path, h;e ti1~1~:t,Pi:?~~~,
,'h.,>,d~~",.
fig g to determme the value of g, and then return to'the oogttJ.:a.l ' . ,~dJaR:ethe,
appropriate branch. This process is sinlilarrothe,Use of sub.rOutin,e~,ih high-level '
programming languages.
"
,
For example, consider the full-adder defined by:
Cj + J
=EF~f +;EiAf "., "
t·'
~>'~~~)f~)
:
> ....
~:
,M
0)-
where Ef:= Aj + Bf. Figure A,2.6 shows the diagrams for theset~~,'e ';,~#~j:ifJk;
the user wants to know the value of Cj + [when the values~t)le,~~rP~;,\"
inputs At,Bf' and C are alII's, he enters the Cj+ 1 diagram, w.~r~h~~p.'C8~ntei5",
, ,; \~{.;).!~";"
Figure A.2.6
~~,"::
.. ": ':' _ :: ::;{i··~t~:<
D
Appendix
523
the node variable Ej- by traversing the Ej diagram, he obtains a value of O. Returning to the original Cj + 1 diagram with Ej ;: 0 will result in taking the 0 branch and
exiting with Cj + 1 = Aj = 1.
Since node variables can refer to other auxiliary functions, we can simply
describe complex modules by breaking their functions into small subfunctions.
Thus, the system diagram will consist of small diagrams connected in a hierarchical structure. Each of these diagrams describes either a module output or an auxi/Bary variable.
Akers 19 described two procedures to generate the binary decision diagram of a
combinational functionf. The first one uses the truth table description off, while
the other uses the boolean expression off. A similar procedure can be derived to
generate the binary decision diagram for any sequential function defined by a
state table.
Binary decision diagrams can be easily stored and processed by a computer
through the use of binary tree structures. Each node can be completely defined
by an ordered triple: the node variable and two pointers to the two nodes to
which its 0 and 1 branches are directed. Binary decision diagrams can be used in
functional testing. 20
'
References
19. S.B. Akers, "Binary Decision Diagram;' IEEE Trans Computers, Vol. C-27,
No.6, June 1978, pp. 509-516.
20. S.B. Akers, "Functional Testing with Binary Decision Diagram," Proc. 8th
Int'l Symp. Fault-Tolerant Computing, june 1978, pp. 82-92.
Random Test Generation
This method can be considered the simplest method for testing a device. A random
number generator is used to simultaneously apply random input patterns both to the
UUT and to a copy of it known to be fault-free. (This copy is called the golden unit.)
The results obtained from the two units are compared, and if they do not match, a fault
in the UUT is detected. This response evaluation technique is known as comparison
testing; we will discuss it later. It is important to note that every time the UUT is tested,
a new random test sequence is used.
The important question is how effective the random test is, or, in other words,
what fault coverage a random test of given length provides. This question can be
answered by employing a fault simulator to simulate the effect of random test patterns
of various lengths. The results of such experiments on SSI and MSI circuits show that
524
Programmable Logic Design Guide
random test generation is most suitable for circuits without deep sequential logic. 1,22,23
However, by combining random patterns with manually generated ones, test designers
can obtain very good results.
The increased sequentiality of LSI circuits reduces the applicability of random testing. Again, combining manually generated test patterns with random ones improves
the degree of fault coverage. However, two factors restrict the use of the random test
generation technique:
• The dependency on the golden unit, which is assumed to be fault-free, weakens the
level of confidence in the results.
• There is no accurate measure of how effective the test is, since all the data gathered
about random tests are statistical data. Thus, the amount of fault coverage provided
by a particular random test process is unpredictable.
A.3
RESPONSE EVALUATION TECHNIQUES
Different methods have been used to evaluate UUT responses to test patterns. We restrict
our discussion to the case where the final goal is only to detect faults or, equivalently, to
detect any wrong output response. There are two ways of achieving this goal - using a
good response generator or using a compact testing technique.
Good Response Generation
This technique implements an ideal strategy: comparing UUT responses with good
response patterns to detect any faulty response. Clearly, the key problems are how to
obtain a good response and at what stage in the testing process that response will be
generated. In current test systems, two approaches to solving these problems are taken
- stored response testing and comparison testing.
Stored Response Testing
In stored response testing, a one-shot operation generates the good response patterns
at the end of the test generation stage. These patterns are stored in an auxiliary memory
(usually a ROM). A flow diagram of the stored response testing technique is shown in
Figure A.3.1.
Different methods can be used to obtain good responses of a circuit to a particular
test sequence. One way is to do it manually by analyzing the UUT and the test patterns.
This method is the most suitable if the test patterns were generated manually in the first
place.
The method most widely used to obtain good responses from the UUT is to apply
the test patterns either to a known good copy of the UUT - the golden unit - or to a
software-simulated version of the UUT. Of course, if fault simulation techniques were
used to generate the test patterns, the UUT's good responses can be obtained very easily as a partial product from the simulator.
Appendix
TEST
PATTERNS
525
UUT
ERROR
·~-"SIGNAL
Figure A.3.1
UUT
Stored Response Testing
UUT
RESPONSE
ERROR
SIGNAL
GOLDEN
UNIT
Figure A.3.2
GOOD
RESPONSE
Comparison Testing
The use of a known good device depends on the availability of such a device.
Hence, different techniques must be used for the user who wants to test his LSI system
and for the designer who wants to test his prototype design. However, golden units are
usually available once the·device goes into production. Moreover, confidence in the
correctness of the responses can be increased by using three or five good devices
together to generate the good responses.
The major advantage of the stored response technique is that the good responses
are generated only once for each test sequence, thus reducing the cost of the response
evaluation step. However, the stored response technique suffers from various disadvantages:
• Any change in the test sequence requires the whole process to be repeated.
S26
Programmable Logic Design Guide
• A very large memory is usually needed to store all the good responses to a reasonable test sequence, because both the length and the width of the responses are relatively large. As a result, the cost of testing equipment increases.
• The speed with which the test patterns can be applied to the DDT is limited by the
access time of the memory used to store the good responses.
Comparison Testing
Another way to evaluate the responses of the DDT during the testing process is to apply
the test patterns simultaneously to both the UUT and a golden unit and to compare
their responses to detect any faulty response. The flow diagram of the comparison testing technique is shown in Figure A.3.2. The use of comparison testing makes possible
the testing of the DUT at different speeds under different electrical parameters, given
that these parameters are within the operating limits of the golden unit, which is
assumed to be ideal.
Note that in comparison testing the golden unit is used to generate the good
responses every time the DDT is tested. In stored response testing, on the other hand,
the golden unit is used to generate the good responses only once.
The disadvantages of depending on a golden unit are more serious here, however,
since every explicit testing process requires one golden unit. This means that every tester
must contain a golden copy of each LSI circuit tested by that tester.
One of the major advantages of comparison testing is that nothing has to be
changed in the response evaluation stage if the test sequence is altered. This makes
comparison testing highly desirable if test patterns are generated randomly.
Compact Testing
The major drawback of good response generation techniques in general, and stored
response testing in particular, is the huge amount of response data that must be analyzed and stored. Compact testing methods attempt to solve this by compressing the
response data R into a more compact formJtR) from which most of the fault information in R can be derived. Thus, because only the compact form of the good responses
has to be stored, the need for large memory or expensive golden units is eliminated. An
important property of the compression function! is that it can be implemented with
simple circuitry. Thus, compact testing does not require much test equipment and is
especially suited for field maintenance work. A general diagram of the compact testing
technique is shown in Figure A.3.3.
Several choices for the function! exist, such as "the number of 1 's in the
sequence," "the number of 0 to 1 and 1 to 0 transitions in the sequence" (transition
counting),24 or "the signature of the sequence" (signature analysis).25 For each compression function!, there is a slight probability that a response Rl different from the
fault-free response RO will be compressed to a form equal to JtRO) , i.e., JtRl) = JtRO).
Appendix
527
Thus, the fault causing the DDT to produce Rl instead of RO will not be detected, even
though it is covered by the test patterns.
The two compression functions that are the most widely accepted commercially
are transition counting and signature analysis.
TEST
PATTERNS
UUT
RESPONSES
R
ERROR
~~~SIGNAL
Figure A.3.3
Compact Testing
Transition Counting
In transition counting, the number of logical transitions (0 to 1 and vice versa) is computed at each output pin by simply running each output of the DDT into a special
counter. Thus, the number of counters needed is equal to the number of output pins
observed. For every m-bit output data stream (at one pin), an n-bit counter is required,
where n = [10g2m]. As in stored response testing, the transition counts of the good
responses are obtained by applying the test sequence to a golden copy of the DDT and
counting the number of transitions at each output pin. This latter information is used as
a reference in any explicit testing process.
In the testing of an LSI circuit by means of transition counting, the input patterns
can be applied to the DDT at a very high rate, since the response evaluation circuitry is
very fast. Also, the size of the memory needed to store the transition counts of the
good responses can be very small. For example, a transition counting test using 16 million patterns at a rate of one MHz will take 16 seconds, and the compressed stored
response will occupy only K 24-bit words, where K is the number of output pins. This
can be contrasted with the 16 million K-bit words of storage space needed if regular
stored response testing is used.
The test patterns used in a transition counting test system must be designed such
that their output responses maximize the fault coverage of the test. 24 The example
below shows how this can be done.
528
Programmable Logic Design Guide
Consider the one-out-of-four multiplexer shown in Figure A3.4. To check for multiple stuck-at faults in the multiplexer input lines, eight test patterns are required, as
shown in Table A.3.1. The sequence of applying these eight patterns to the multiplexer
is not important if we want to evaluate the output responses one by one. However, this
sequence will greatly affect the degree of fault coverage if transition counting is used.
To illustrate this fact, consider the eight single stuck-at faults in the four input lines
Xl,X2,X3, and X4 (i.e., Xl stuck-at 0, Xl stuck-at 1, X2 stuck-at 0, and so on). Each of
these faults will be detected by only one pattern among the eight test patterns. For
X1
X2
X3
X4
So
0
0
Sl
0
1
1
0
1
1
y
X1
X2
X3
X4
y
Figure A.3.4
One-Out-of-Four Multiplexer
example, the fault "Xl stuck-at 0" will be detected by applying the first test pattern in
Table A.3.1, but the other seven test patterns will not detect this fault. Now, suppose we
want to use transition counting to evaluate the output responses of the multiplexer.
Applying the eight test patterns in the sequence shown in Table A3.1 (from top to bottom) will produce the output response 10101010 (from left to right), with a transition
count of seven. Any possible combination of the eight faults described above will
change the transition count to a number different from seven, and the fault will be
detected. (Note that no more than four of the eight faults can occur at anyone time.)
Thus, the test sequence shown in Table A3.1 will detect all single and multiple stuck-at
faults in the four input lines of the multiplexer.
Now, if we change the sequence of the test patterns to the one shown in Table
A.3.2, the fault coverage of the test will decrease considerably. The output responses of
the sequence of Table A.3.2 will be 11001100, with a transition count of three. As a
result, six of the eight single stuck-at faults will not be detected, because the transition
count of the six faulty responses will remain three. For example, the fault "Xl stuck-at
1" will change the output response to 11101100, which has a transition count of three.
Hence, this fault will not be detected. Moreover, most of the multiple combinations of
the eight faults will not change the transition count of the output, and hence they will
not be detected either.
It is clear from the above example that the order of applying the test patterns to the
UUT greatly affects the fault coverage of the test. When testing combinational circuits,
the test designer is completely free to choose the order of test patterns. However, he
Appendix
529
So
SI
X1
X2
X3
X4
Y
So
SI
X1
X2
X3
X4
Y
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
0
0
0
1
1
1
0
0
1
1
0
1
1
0
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
0
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
Table A.3.1
1
The eight test patterns
used for testing the
multiplexer of
Figure A.3.4
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
Table A.3.2 A different sequence of
the eight multiplexer
test patterns
cannot do the same with test patterns for sequential circuits. More seriously, because
he is dealing with LSI circuits that probably have multiple output lines, he will find that
a particular test sequence may give good results at some outputs and bad results at others. One way to solve these contradictions is to use simulation techniques to find the
optimal test sequence. However, because of the limitations discussed here, transition
counting cannot be recognized as a powerful compact LSI testing method.
Signature Analysis
In 1977 Hewlett-Packard Corporation introduced a new compact testing technique
called Signature analysis, intended for testing LSI systems. 25 -28 In this method, each
output response is passed through a 16-bit linear feedback shift register whose contents
f(R) , after all the test patterns have been applied, are called the test signature. Figure
.A.3.5 shows an example of a linear feedback shift register used in signature analysis.
16-BIT SHIFT REGISTER
SERIAL
DATA
INPUT
Figure A.3.S
The 16-bit Linear Feedback Shift Register Used in Signature Analysis
530
Programmable Logic Design Guide
The signature provided by linear feedback shift registers can be regarded as a
unique fingerprint - hence, test designers have extremely high confidence in these
shift registers as tools for catching errors. To better understand this confidence, let us
examine the 16-bit linear feedback shift register shown in Figure A,3.5. Let us assume a
data stream of length n is fed to the serial data input line (representing the output
response to be evaluated). There are 2 n possible combinations of data streams, and
each one will be compressed to one of the 216 possible signatures. Linear feedback shift
registers have the property of equally distributing the different combinations of data
streams over the different signatures. 27 This property is illustrated by the following
numerical examples.
• Assume n = 16. Then each data stream will be mapped to a distinctive signature
(one-to-one mapping).
• Assume n = 17. Then exactly two data streams will be mapped to the same signature. Thus, for a particular data stream (the UUT good output response), there is
only one other data stream (a faulty output response) that will have the same signature; i.e., only one faulty response out of 217 - 1 possible faults will not be
detected.
• Assume n = 18. Then four different data streams will be mapped to the same signature. Hence, only three faults out of 218 - 1 possible faults will not be detected.
We can generalize the results obtained above. For any response data stream of
length n> 16, the probability of missing a faulty response when using a 16-bit signature analyzer is27
2 n - 16_1
____ - 2 - 16, for n> > 16.
Hence, the possibility of missing an error in the bit stream is very small (on the order of
0.002 percent). Note also that a great percentage of the faults will affect more than one
output pin - hence the probability of not detecting these kind of faults is even lower.
Signature analysis provides a much higher level of confidence for detecting faulty
output responses than that provided by transition counting. But, like transition counting, it requires only very simple hardware circuitry and a small amount of memory for
storing the good signatures. As a result, the signatures of the output responses can be
calculated even when the UUT is tested at its maximum speed. Unlike transition counting, the degree of fault coverage provided by signature analysis is not sensitive to the
order of the test patterns. Thus, it is clear that signature analysis is the most attractive
solution to the response evaluation problem.
The rapid growth of the complexity and performance of digital circuits presents a
testing problem of increasing severity. Although many testing methods have worked
well for SSI and MSI circuits, most of them are rapidly becoming obsolete. New techniques are required to cope with the vastly more complicated LSI circuits.
Appendix
531
In general, testing techniques fall into the concurrent and explicit categories. In
this article, we gave special attention to explicit testing techniques, especially those
approaching the problem at the functional level. The explicit testing process can be
partitioned into three steps: generating the test, applying the test to the UUT, and evaluating the UUT's responses. The various testing techniques are distinguished by the
methods they use to perform these three steps. Each of these techniques has certain
strengths and weaknesses.
We have tried to emphasize the range of testing techniques available, and to highlight some of the milestones in the evolution of LSI testing. The details of an individual
test method can be found in the sources we have cited.
References
1. M.A. Breuer and A.D. Friedman, Diagnosis and Reliable Design of Digital Systems,
Computer Science Press, Washington, DC, 1976.
2. J.P. Hayes and E.J. McCluskey, "Testing Considerations in Microprocessor-Based
Design," Computer, Vol. 13, No.3, Mar. 1980, pp. 17-26.
3. J. Wakerly, Error Detecting Codes, Self-Checking Circuits and Applications, American Elsevier, New York, 1978.
4. D.B. Armstrong, "On Finding a Nearly Minimal Set of Fault Detection Tests for
Combinatorial Nets," IEEE Trans. Electronic Computers, Vol. EC-15, No.2, Feb.
1966, pp. 63-73.
5. J.P. Roth, W.G. Bouricius, and P.R. Schn~ider, "Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits," IEEE
Trans. Electronica Computers, Vol. EC-16, No.5, Oct. 1967, pp. 567-580.
6. S.B. Akers, "Test Generation Techniques," Computer, Vol. 13, No.3, Mar. 1980,
pp.9-15.
7. E.I. Muehldorf and A.D. Savkar, "LSI Logic Testing - An Overview," IEEE Trans.
Computers, Vol. C-30, No.1, Jan. 1981, pp. 1-17.
8. O.H. Ibarra and S.K. Sahni, "Polynomially Complete Fault Detection Problems,"
IEEE Trans. Computers, Vol. C-24, No.3, Mar. 1975, pp 242-249.
9. T. Sridhar and J.P. Hayes, "Testing Bit-Sliced Microprocessors," Proc. 9th Int'l
Symp. Fault-Tolerant Computing, 1979, pp. 211-218.
532
Programmable Logic Design Guide
10. The Am2900 Family Data Book, Advanced Micro Devices, Inc., 1979.
11. Z. Kohavi, Switching and Finite Automata Theory, McGraw-Hill, New York, 1970.
12. S.M. Thatte, "Test Generation for Microprocessors," PhD thesis, University of IllinOis, Urbana, 1979.
13. S.M. Thatte andJ.A. Abraham, "Test Generation for Microprocessors," IEEE Trans.
Computers, Vol. C-29, No.6, June 1980, pp. 429-441.
14. M.A. Breuer and A.D. Friedman, "Functional Level Primitives in Test Generation,"
IEEE Trans. Computers, Vol. C-29, No.3, Mar. 1980, pp. 223-235.
15. M.S. Abadir and H.K. Reghbati, "Test Generation for LSI: A New Approach," Tech.
Report 81-7, Dept. of Computational Science, University of Saskatchewan, Saskatoon, 1981.
16. M.S. Abadir and H.K. Reghbati, "Test Generation for LSI: Basic Operations," Tech.
Report 81-8, Dept. of Computational Science, University of Saskatchewan, Saskatoon, 1981.
17. M.S. Abadir and H.K. Reghbati, "Test Generation for LSI: A Case Study," Tech.
Report 81-9, Dept. of Computational Science, University of Saskatchewan, Saskatoon, 1981.
18. M.S. Abadir and H.K. Reghbati, "Functional Testing of Semiconductor Random
Access Memories," Tech. Report 81-6, Dept. of Computational Science, Univeristy
of Saskatchewan, Saskatoon, 1981.
19. S.B. Akers, "Binary Decision Diagram," IEEE Trans Computers, Vol. C-27, No.6,
June 1978, pp. 509-516.
Appendix
533
20. S.B. Akers, "Functional Testing with Binary Decision Diagram," Proc. 8th Int'l
Symp. Fault-Tolerant Computing, June 1978, pp. 82-92.
21. B.A. Zimmer, "Test Techniques for Circuit Boards Containing Large Memories and
Microprocessors," Proc. 1976 Semiconductor Test Symp., pp. 16-21.
22. P. Agrawal and VD. Agrawal, "On Improving the Efficiency of Monte Carlo Test
Generation," Proc. 5th Int'l Symp. Fault-Tolerant Computing, June 1975, pp. 205209.
23. D. Bastin, E. Girard,].C. Rault, and R. Tulloue, "Probabilistic Test Generation Methods," Proc. 3rd Int'l Symp. Fault-Tolerant Computing, June 1973, p. 171.
24. J.P. Hayes, "Transition Count Testing of Combinational Logic Circuits," IEEE Trans.
Computers, Vol. C-25, No.6, June 1976, pp. 613-620.
25. "Signature Analysis," Hewlett Packard]., Vol.28, No.9, May 1977.
26. R. David, "Feedback Shift Register Testing," Proc. 8th Int'l Symp. Fault-Tolerant
Computing, June 1978.
27. H.]. Nadig, "Testing a Microprocessor Product Using Signature Analysis," Proc.
1978 Semiconductor Test Symp., pp. 159-169.
28. ].B. Peatman, Digital Hardware Design, McGraw-Hill, New York, 1980.
29. M. Garey and D. Johnson, Computers and Intractability: A Guide to the Theory oj
NP-Completeness, W.H. Freeman, San Francisco, 1978.
30. E. Horowitz and S. Sahni, Fundamentals of Computer Algorithms, Computer Science Press, Washington, DC, 1978.
.
~ National
~ Semiconductor
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