1986_OKI_Microcontroller 1986 OKI Microcontroller
User Manual: 1986_OKI_Microcontroller
Open the PDF directly: View PDF 
.
Page Count: 406
| Download | |
| Open PDF In Browser | View PDF |
OKI
MICROCONTROLLER
DATA BOOK
ISSUE DATE : DEC 1986
PREFACE
A high technology company with an aggresive approach to innovation, OKI has been
supplying single-chip microcontrollers since 1975. OKI's single-chip microcontrollers
find wide application in various types of electronic equipment in the consumer and the
industrial fields. Our products have been enjoying a good reputation for their high
quality and high performance. The most outstanding feature employed in all of OKI's
microcontrollers is CMOS technology which ensures low power operation.
OKI will continue to enhance the its microcontroller series and program development
systems to cater to cutomers' requirements.
OKI makes no warranty for the use of its products and assumes no
responsibility for any errors which may appear in this document nor
does it make a commitment to update the information contained
herein.
OKI.retains the right to make changes to these specifications at
any time, without notice.
CONTENTS
1. PROGRAM DEVELOPMENT SYSTEM . ................................................. .
2. LINE-UP AND TYPICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
3. CODE ENTRY ..........................................................................
15
1. USABLE MEDIA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 17
2. SINGLE CHIP MICROCONTROllER DEVELOPMENT STAGES. . . . . . . . . . . . . . . . . . . . . . .. 18
4. PACKAGING...........................................................................
19
5. RELIABILITY INFORMATION .. ..................................................... , . . .
33"
6. DATA SHEET .............. "...........................................................
43
• OlMS-40 SERIES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
MSM5840 . ... ............. ...... ......... ... ..... ........ ........... .... ..........
47
MSM5842 . ..... ...... ..... ...... .......... ....... ........ ......... ................
58
MSM58421 ........................................................................
66
MSM58422 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
76
MSM5847 ............................................•............................
84
• OlMS-50/60 SERIES ..............................................................
89
MSM5052 .... ".....................................................................
91
MSM5054 ............. .......................... ....... .............. ......... ....
97
MSM5055 ......................................................................... 104
MSM5056 .................................................................. "...... 111
MSM6051 .................................................................. "...... 118
MSM6351 ......................................................................... 126
MSM6052 ......................................................................... 129
MSM6352 ......................................................................... 1 39
•
OlMS-64 SERIES . ................... ". . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 143
MSM6404 ...........................................................".............. 145
MSM6404VS ...................................................................... 157
MSM6408 ..............................................................".......... 159
MSM6411 ......................................................................... 170
MSM6422 ......................................................................... 181
MSM6431 ......................................................................... 189
MSM6442 ......................................................................... 201
MSC6458 ......................................................................... 206
MSC6458VS ........................................................................ 216
iii
•
OLMS-65 SERIES ................................................................... 217
•
8 BIT SERIES (OKI ORIGINAL) ....................................................... 229
MSM6502/6512 .................................................................... 219
MSM62580 ......................................................................... 231
MSM66301 ......................................................................... 240
•
8 BIT SERIES (INTEL COMPATIBLE) ................................................. 259
MSM80C35/48, MSM80C39/49, MSM80C40/50 .................................... 261
MSM80C31 F/MSM80C51 F ......................................................... 286
MSM80C51 FVS .................................................................... 311
MSM80C154/MSM83C154 ......................................................... 312
MSM85C154VS .................................................................... 346
7. PROGRAM DEVELOPMENT SUPPORT SySTEMS .... .................................... 347
EASE40 ................................................................................ 349
EASE6400 ............................................................................. 358
EASE6502 ............................................................................. 368
EASE80C49 ........................................................................... 378
MAC51 ............................................................................... 398
iv
PROGRAM DEVELOPMENT
SYSTEMS
PROGRAM DEVELOPMENT SYSTEMS FOR
OKI MICROCONTROLLERS
OLMS-40 SERIES
target chip
MSM5840
MSM5842
development tool
package name
standard software
(included in package)
adaptor module
(if necessary)
EASE 40
(SERIAL INTERFACE)
(BUS INTERFACE)
DB400 debugger
ASM40 cross assembler
-
MSM58421
MPB421
MSM58422
MPB422
MSM5847
dedicated hardware
·simul.ator
field debugging
tool
MPB202
-
[Note]
1. The standard software DB400 and ASM40 are avalable on CP/M-80 for most of personal computers, or ISIS-II for
INTEL MOS.
CP/M is a registered trade mark of Digital Research, and ISIS-II, MDS of Intel.
LOW POWER SERIES
target chip
development tool package name
standard software
MSM5052
EASE5052/56
MSM5056
AMS50
cross assembler
MSM5054
EASE5054/55
MSM5055
MSM6051
(EASE6051)
MSM6351
EASE
host
monitor
ASM6351
ASM6351
(EASE6351/6353)
ASM6353
MSM6353
MSM6052
EASE6052, (EASE6352/6052)
ASM50
MSM6352
(EASE6352/6052)
ASM6352
[Note]
1. The standard software is avilable under following operating system.
CP/M-80 for most of personal computers
MSDOS for OKI if800, NEC PC9801 etc.
PCDOS for IBM PC-XT, AT, IBM 5550
3
o
• PROGRAM DEVELOPMENT SYSTEMS . - - - - - - - - - - - - - OLMS-64 SERIES
target chip
development tool
package name
1/0 adaptor
module
MSM6408
-
MSM6404
-
MSM6402
-
MSM6422
EASE6400
standard software
(included in package)
leld debugging
tool
-
ASM6408
MSM6404VS
-
PAM6422
EASE
host
monitor
ASM6404
PEM6422
MSM6411
PAM6411
MSM6442
(PAM6442)
(PEM6442)
MSM6431
PAM6431
PEM6431
MSC6458
[Note)
-
EASE6458
Piggyback
PEM6411
-
ASM6458
,
MSC6458VS
The standard software is available under following operating system.
EASE, ASM6400
CP/M-80 for most of personal computers,
MSDOS for OKI if800, NED PC9801 etc.
PCDOS for IBM PC-XT, AT,IBM 5550
ASM6408,
ASM6458 .......... CP/M-80 for most of personal computers
OlMS-65 SERIES
target chip
development tool
package name
standard software
(included in package)
field debugging tool
MSM6502/6512
EASE6502
EASE65
ASM6502
MPB6502EVA
[Note)
The standard software is available under CP IM-80, MSDOS, or PC DOS.
8 BIT SERIES (INTEL compatible)
target chip
development tool
standard software
optional software
piggyback
EASE80C49
EASE49
ASM49
-
-
EASE
See Note 1.
MSM80C51VS
MSM80C48
MSM80C49 '
MSM80C50
MSM80C51
MSM83C154
EASE80C51 m KII
ASM51
MSM85C154VS
[Note)
1. Optional Software for MSM80C51/83C154
PASM preprocessor, MAC51 relocatable assembler, RL51 object linker, LlB51 librarian SID51 symbolic debugger
2. The softwares are available under following operating system.
EASE49 .............................. CP/M-80,ISIS-1I
ASM49 ....................... , ....... CP/M-80, ISIS-II .
EASE & ASM51 ....................... CP/M-80forOKI il800, NEC PC8801 etc.
MSDOS for OKI il800, NEC PC9801 etc.
PC DOS for IBM PC-XT, AT,IBM 5550
PASM, MAC51, RL51, LlB51 .......... MSDOS for OKI il80, NEC PC9801 etc.
SID51
PC DOS for IBM PC-XT, AT,IBM 5550
4
o
- - - - - - - - - - - - - - - . PROGRAM DEVELOPMENT SYSTEMS •
8 BIT SERIES (OKI original)
development tool
package name
standard software
{included in package}
optional software
MSM66301
EASE66301'
ASM66301
EASE
See Note 1.
MSM62580
EASE62580'
ASM62580
EASE
target chip
• under development
[Note]
1. Optional Software for MSM66301
c-compiler (VMS for uVAX-II)
relocatable assembler (VMS)
object linker and librarian (VMS)
cc66 debuger (VMS)
symbolic debugger (VMS)
• under development
5
LINE-UP AND TYPICAL
CHARACTERISTICS
• OLM8-40 SERIES
TYPE NO.
PROCESS
POWER
SUPPLY
VOLTAGE
CLOCK
FREQUENCY
ROM
(BIT)
RAM
(BIT)
INPUT
PORT
OUTPUT PORT
MSM5840
CMOS
5V
4.2MHz
2048 x 8
128)(4
6
MSM5842
CMOS
5V
4.2MHz
768)(8
32)(4
5
MSM58421
CMOS
5V
4.2MHz
1536)(8
4Ox4
6
MSM58422
CMOS
5V
4.2MHz
1536)(8
4Ox4
5
MSM6847
CMOS
3V
32kHz
1536x8
96)(4
-
I/O
PORT
TIMER
COUNTER
16
8
8 Bit R/W
8
8
35LCD Seg.
SLeD Seg. or LOGIC
7 x 5FLTSeg.
5Discreate
24 x 3LeD Seg.
INTER·
INSTRUC. MACHINE
STACK
RUPT
TION
CYCLE
POWER CONSUMPTION
ACTIVE
STAND-BY
PACKAGE
REMARKS
2
4
98
7.61'S
1.6mA
-
420lP/44FLA T
8 Bit
-
1
52
7.6JlS
1.5mA
-
28DIP/32FLAT
8
12 Bit
-
1
52
7.6"S
2.OmA
-
60FLAT
8
12 Bit
-
1
52
7.6"S
2.OmA
-
60FLAT
7
13 Bit
-
2
43
610"S
50,.A
-
44FLAT/CHIP
-----------_._-
~---
•
• OLMS-50/60 SERIES
PROCESS
POWER
SUPPLY
VOLTAGE
CLOCK
FREQUENCY
ROM
(BIT)
MSM5052
CMOS
1.5V
32kHz
1280x 1
62)(4
8
MSM5054
CMOS
1.5V/3V
32kHz
1024x 14
62)(4
6
MSM5055
CMOS
1.5V/3V
32kHz
1792x14
96)(4
8
MSM6068
CMOS
1.5V
32kHz
1792 xl
90)(4
4
MSM6051
CMOS
1.5V/3V
32kHz
2560x 14 120)(4
9
TYPE NO.
RAM
(BIT)
INPUT
PORT
MSM6351
CMOS
1.5V/3V
32kHz
4096)(15 1024)(4
-
MSM6052
CMOS
3V
3.5~MHz
2048 x 14 640x4
12
MSM6352
CMOS
3V
3.58MHz
2048 x 14 640x4
12
I/O
PORT
TIMER
COUNTER
ACTIVE
STAND-BY
-
-
-
-
42
122pS
3pA
-
CHIP
4 lOGIC
-
-
-
-
40
122pS
3pA
-
CHIP
60 x 2LCD Seg.
4 LOGIC
-
-
-
-
42
122"S
3pA
-
CHIP
38 x 2LCD Seg.
-
-
-
-
42
1221'S
3,.A
-
CHIP
-
-
1
2
,59
91.5pS
3pA
-
CHIP
OUTPUT PORT
26 x 2LCD Seg.
5 LOGIC
44)( 2LCD Seg.
4 LOGIC
63 x 3leC Seg.
4 LOGIC
59 x 3lec Seg. or
58 x 4LCD Seg.
12
12
INTER·
INSTRUC. MACHINE
STACK
RUPT
TION
CYCLE
POWER CONSUMPTION
REMARKS
PACKAGE
Built-in temperature detector
Z
Connection with
solar cell available
7
65
61.0,,5
3pA
-
CHIP/l00FLAT
4
4 Bit
1
5
52
17.9".5
1.2mA
0.2pA
28DIP/40DIP
Built-in DTMF
28DIP/40DIP
Built-in DTMF
under
development
5
52
17.9".5
1.2mA
0.2pA
~
'tI
n
•
•::u:z:
•
r-
Under
3
1
'tI
C
-
4 Bit
I
C
•
20
4
C
z
m
development
()
()
-I
m
::u
iii
-I
co
n
en
=
•
=
...o
•
r-
Z
m
I
C
'V
:I>
Z
C
• OLMs-&4 SERIES
TYPE NO.
PROCESS
POWER
SUPPLY
VOLTAGE
CLOCK
FREQUENCV
ROM
(BIT)
RAM
(BIT)
INPUT
PORT
OUTPUT PORT
1/0
PORT
TIMER
COUNTER
12 Bit
12 Bit R/W
8 bit R/W
MSM6404
CMOS
SV
4.2MHz
4000 x 8
256><4
4
-
32
MSM6408
CMOS
SV
4.0MHz
8000)( 8 256)(4
4
-
32
MSM6411
CMOS
SV
4.2MHz
1014)( 8
32x4
4
-
MSM6422
CMOS
5V
4.2MHz -
2048 x 8
64)(4
1
MSM6431
CMOS
SV
4.2MHz
.1024)( 8
48x4
4
INTERINSTRUe- MACHINE
sTACK
RUPT
TION
CYClE
POWER CONSUMPTION
ACTIVE
STAND-BY
PACKAGE
REMARKS
~
'V
S
32
121
952n5
6mA
1"A
42DIP/44FLAT
12 Bit R/W
8 Bit R/W
5
32
121
1.5
6mA
1"A
42DIP/44FLAT
8
-
2
8
63
952n5
6mA
1.A
24DIP/44FLAT
-
18
12 Bit
2
16
63
952n5
SmA
1.A
l6D1P
1
10
10 Bit
3
8
53
952n5
6mA
1"A
24DIP/24FLAT
n
:J>
r-
12 Bit
(')
::z:
:I>
:1:1
:I>
MSM6442
CMOS
5V
4.2MHz
2048_ 8 128x4
1
46 x 2LCD Seg.
16
Msd~4S8
Bi-CMOS
SV
4.3MHz
8000 x 8 512)( 4
9
12)( 12FLT Seg.
24
16 Bit R/W
8 Bit R/W
POWER
SUPPLY-_
VOLTAGE
CLOCK
FREQUENCY
ROM
(BIT)
RAM
(BIT)
INPUT
PORT
OUTPUT PORT
1/0
PORT
TIMER
COUNTER
3V
32kHz
2000 x 8
128)(4
4
108LCO Seg.
8
12 Bit
3
32
68
91.5",5
4SpA
I
30"A
44FLAT
3V
32kHz
2000 x 8
128)(4
4
10BLCD Seg.
8
12 Bit
3
32
68
91.5,,5
30"A
I
12p.A
44FLAT
8 Bit RIW
4
16
76
952nS
6mA
1.A
8
32
147
930nS
9mA
lpA
12 Bit
80FLAT
(')
-I
Built in AID
Converter
iii
n
en
Built-in FlT Con·
troller/Driver
PACKAGE
REMARKS
• OLMS-65 SERIES
TYPE NO.
PROCESS
MSM8502
CMOS
MSM6512
CMOS
--
INTERINSTRUe- MACHINE
STACK
RUPT
TION
CYCLE
POWER CONSUMPTION
ACTIVE
STAND-BY
:1:1
Built-in LCD Controller/Driver
, 64 FLAT
64 Shrink DIPI
m
-I
•
• 8 Bit SERIES (INTEL compatible)
TYPE NO.
PROCESS
POWER
SUPPLY
VOLTAGE
CLOCK'
FREQUENCY
ROM
(BIT)
RAM
(BIT)
INPUT
PORT
OUTPUT PORT
-
110
PORT
TIMER
COUNTER
INTERRUPT
-
24
8 Bit R/W
2
8
111
-
24
8 Bit R/W
2
8
24
8 BitR/W
2
STACK
INSTRUC- MACHINE
- CYCLE
TION
POWER CONSUMPTION
REMARKS
PACKAGE
ACTIVE
STAND-BY
1.36,,5
lOrnA
1.A
40DIP/44FLAT
111
1.36,,5
lOrnA
'.A
400lP{44FLAT
8
111
2.5"S
lOrnA
1".4
40DIP/44FLAT
MSMBOC35
CMOS
5V
l1MHz
-
64 x 8
MSM80C39
CMOS
5V
l1MHz
-
128>< 8
-
MSM80C40
CMOS
5V
6MHz
-
256x 8
-
MSM80C31F
CMOS
5V
16MHz
-
128)( 8
32
16 Bit R/Wx2
5
64
111
0.7S"S
20mA
I.A
40DIP/44FLAT
MSMBOC154
CMOS
5V
16MHz
-
256x 8
32
16 Bit RIWx3
6
128
111
0.751'5
20mA
I,A
40DIP
MSM80C48
CMOS
5V
1,MHz
1024 x B
64)( 8
24
8 Bit AIW
2
8
111
1.36,,5
lOrnA
I,A
40DIP/44FLAT
MSM80C49
CMOS
5V
'1MHz
2048
x
8
128)( 8
24
8 Bit R/W
2
8
111
1.361{S
lOrnA
I.A
40DIP/44FlAT
MSM80C50
CMOS
5V
6MHz
4096
x
8 256x 8
24
8 Bit R/W
2
8
111
2.5"S
lOrnA
1".4
40DIP/44FLAT
MSM80C51F
CMOS
5V
16MHz
128,.. 8
32
16 Bit R/Wx 2
5
64
111
0.7S"S
20mA
I.A
40DIP/44FLAT
MSM83C1S4
CMOS
5V
12MHz
32
16 Bit RiWx3
6
128
I.S
20mA
I.A
40DIP
-
4096 x 8
16384x8 256
>C
8
-----
,
111
•
r"
Z
m
I
C
'V
:J>
Z
tJ
....
-----
~
'V
• 8 BIT SERIES (OKI original)
TYPE NO.
MSM62580
PROCESS
CMOS
POWER
SUPPLY
VOLTAGE
5V
CLOCK
FREQUENCY
4.9MHz
ROM
(BIT)
RAM
(BIT)
INPUT
PORT
128)( 8
3072 x 8
OUTPUT PORT
110
PORT
TIMER
COUNTER
INTER-
RUPT
-
1
STACK
32
INSTRUC- MACHINE
TION
CYCLE
95
860n5
POWER CONSUMPTION
ACTIVE
4rnA
PACKAGE
STAND-BY
10p.A
T.B.O
64 Shrink DIP!
MSM66301
CMOS
5V
10MHz
16384
x
8 512" 8
8
40
16 Bit x4
17
256
99
400nS
-
-
68 PLCCI
64 FLAT
i
REMARKS
Fan Ie cards
under deVelop- .
ment
Under developmen!
- AIOC Bch. 1 Obit
• USART
-PWM
• Chapter register
o:J>
r"
(')
::z::
:J>
2J
:J>
(')
-I
m
2J
iii
-I
o
•
U)
=
• LINE-UP AND TYPICAL CHARACTERISTICS . - - - - - - - - - - - - -
I
LOW POWER
HIGH SPEED
OlMS-65 SERIES
TYPE NO.
ROM
(BYTE I
(NIBBLES)
RAM
MSM6502
2000 x 8
12B
MSM6512
2000 x 8
12B
POWER
CONSUMPTION
LCD SEGMENT
70p.A
10B
OlMS-64 SERIES
10B
ROM
RAM
MACHINE
(BYTE)
(NIBBLES)
CYCLE
1/0 PORT
M$M6404
4000 x B
256
1"
(4MHz)
36
MSM640B
8000 x 8
256
1"
(4MHz)
36
MSM6411
1024)(8
32
1"
(4MHz)
12
MSM6422
2048)( 8
64
3,A
MSM6431
1024)(8
48
TYPE NO.
a
MSM6442
2048)(
MSC6458
8000 x 8
12B
512
OlMS-SO/60 SERIES
TYPE NO.
ROM
(BYTE I
RAM
(NIBBLES)
POWER
CONSUMP-
REMARK
TION
MSM5052
1280x 14
62
Orl chip Temperature Delectlon
CirCUlI 52 Set LCD Ofiller
MSM5054
1020x 14
62
88 Seg. LCD Driver
MSM5055
1792)( 14
96
120 Seg. LCD Driver
MSM5056
1792)(14
90
Connection with solar
cell available
76 Seg. LCD Driver
MSM6051
2560)(14
120
189 Seg. LCD Driver
MSM6351
4096)( 15
1024
232 Seg. LCD Driver
MSM6052
2048)( 14
640
1.2mA
Built-in DTMF
MSM6352
2048)( 14
640
1.2mA
Built-in DTMF
OlMS-40 SERIES
TYPE NO.
ROM
(BYTE)
RAM
(NIBBLES)
MSM5840
2048)( 8
12B
MSM5842
768x 2
32
MSM58421
1536 x 8
46
MSM58422
1536x8
46
MSM5847
1536x8
96
MACHINE
CYCLE
8",
(4MHz)
8"
(4MHz)
8",
(4MHz)
8}.!-5
(4MHz)
600l's
(32kHz)
----_ ..
1 :1~1:1:1
4BIT
12
REMARK
I/O port; 40
1/0 port; 21
35 Seg. LCD Driver
35 Seg. FLT Driver
72 Seg. LCD Driver
(4MHz)
19
1",
(4MHz)
14
(4MHz)
1",
17
1",
(4MHz)
33
- - - - - - - - - - - - - . LINE-UP AND TYPICAL CHARACTERISTICS.
I
HIGH PERFORMANCE
I
II
COMPATIBLE WITH INTEL'S
8 BIT MICROCONTROLLER
TYPE NO
ROM
(BYTE)
RAM
(BYTE)
MACHINE
CYCLE
1.36/15
(11 MHz)
MSM80C48
1024
64
MSM80C49
2048
128
MSM80C50
4096
256
2.5/ls
(6 MHz)
MSM80C51F
4096
128
0.75"s
(16 MHzl
MSM83C154
16384
256
1.36/,5
(11 MHz)
1/,5
(12MHzl
MSM80C35
64
1.36/15
(11 MHz)
MSM80C39
28
1.36/15
(11 MHz)
MSM80C40
256
2.5p.s
(6 MHzl
MSM80C31F
128
O.75"s
(16 MHz I
MSM80C154
256
(12MHz)
1/18
8 BIT
13
CODE ENTRY
-------------------------------------------eCODEENTRYe
CODE ENTRY
The program code ENTERING method is outlined below.
1. USABLE MEDIA
(1) 2 pieces of same type EPROMs containing identical DATA
o
EPROM specification
2716
2732
27C32
27C32A
2764
27C64
27128
27256
(2) 1 copy of object machine code list
17
• CODE ENTRY. - - - - - - - - - - - - - - - - - - - - - - -
2. SINGLE CHIP MICROCONTROLLER DEVELOPMENT STAGES
USER 1
D
• Program with OKI development tool.
TOOL
if 800
USER 2
II
• Prepare 2 pcs of EPROM and programming list
EPROM
Printout
OKI 3
• Print out identical EPROM da~t:a.~~~~~~r;JZI11-1
OKI4
• Engineering Sample
Actual production sample of your microcontroller
chip prepared for final approval.
,
II
~
~ ······~~y\toVED
I
II
18
.f,9.:~ ~
(j,
sY..~~
.......... .
~
OKI5
'.
..
• Volume production of single chip microcontrollers.
PACKAGING
PACKAGING
PACKAGE/PIN COUNT
DIP
FLAT
PLCC
MSM5840
42PIN
44PIN
-
MSM5842
28PIN
32 PIN
-
MSM58421
-
60 PIN
-
MSM58422
-
60PIN
-
MSM5847
-
44PIN
-
MSM5052
-
56PIN
-
MSM5054
-
56PIN
-
MSM5055
-
80PIN
-
MSM5056*
-
-
-
MSM6051 *
-
-
-
MSM6351
-
100PIN
-
MSM6052
28/40 PIN
44PIN
-
MSM6352
28/40 PIN
44PIN
-
MSM6404
42PIN
44PIN
44PIN
-
-
MSM6404VS
42 PIN PIGGY BACK
MSM6408
42PIN
44PIN
44PIN
MSM64ll
l6PIN
-
-
MSM6422
24PIN
24PIN
-
MSM6431
24PIN
24PIN
-
MSM6442
-
80 PIN
-
MSC6458
64 PIN SHRINK
64PIN
68PIN
MSC6458VS
64 PIN SHRINK
PIGGYBACK
-
-
NOTE: * means DIE SALES.
21
• PACKAGING . - - - - - - - - - - - - - - - - - - - - - - - - -
PACKAGE/PIN COUNT
DIP
PLCC
MSM6502
-
56 PIN(S)
-
MSM6512
-
56PIN(S)
-
MSM62580
T.B.D.
T.B:D
T.B.D.
64PIN
68PIN
MSM66301
64 PIN SHRINK
MSM80C35
40PIN
44PIN
44PIN
MSM80C39
40PIN
44PIN
44PIN
MSM80C40
40PIN
44PIN
44PIN
MSM80C31
40PIN
44PIN
44PIN
MSM80C48
40PIN
44PIN
44PIN
MSM80C49
40PIN
44 PIN
44PIN
MSM80C50
40PIN
44PIN
44PIN
MSM80C31 F
40PIN
44PIN
44PIN
-
-
MSM80C51 FVS
40 PIN PIGGY BACK
MSM80C51 F
40PIN
44PIN
44PIN
MSM80C154
40PIN
44PIN
44PIN
MSM83C154
40PIN
44PIN
44PIN
-
-
MSM85C154VS
22
FLAT
40 PIN PIGGY BACK
- - - - - - - - - - - - - - - - - - - - - - - - ' . PACKAGING·
• 16 PIN PLASTIC DIP
(Unit: mm)
7.62±030
0°_15°
2.54±025
SEATING PLANE
• 18 PIN PLASTIC DIP
(Unit:mm)
2.54±o.25
0"-15°
SEATING PLANE
23
• PACKAGING .----------------------------------------------~-• 24 PIN PLASTIC DIP
(Unit:mm)
II
15.24±0.30
2.54:;1:0.25
0°-15'
• 28 PIN PLASTIC DIP
SEATING PLANE
24
• PACKAGING •
• 40 PIN PLASTIC DIP
52.8 MAX
(Unit: mm)
15.24 ±03 0
SEATING PLANE
• 42 PIN PLASTIC DIP
(Unitmm)
52.8 MAX
15.24 ±030
.
><
:I
SEATING PLANE
25
•. • PACKAGING .I----------~------------• 64 PIN SHRINK DIP
(Unit:mm)
58.0 MAX
I
INDEX MARK
D
19.05±O.30
0'>...15'
SEATING PLANE
26
- - - - - - - - - - - - - - - - - - - - - - - . PACKAGING •
• 24 PIN PLASTIC FLAT
(Unit:mm)
16.0 ±O.3
n
0.35±O;
"II
o
I
1--
~
+I
0">
r---:
CD
INDEX MARK
;;
+1
0
N
@
• 32 PIN PLASTIC FLAT
(Unit:mm)
2.2±O.2
0.1-0.3
INDEX MARK
27
• PACKAGING ...- - - - - - - - - - - - - - - - - - - - - - - • 44 PIN PLASTIC FLAT
(Unit:mm)
14.S±O.4
1.5±0.2
D· _10·
o
INDEX MARK
• 56 PIN PLASTIC FLAT
(Unit:mm)
14.5±O.4
INDEX MARK
28
- - - - - - - - - - - - - - - - - - - - - - - - . PACKAGING.
•
60 PIN PLASTIC FLAT
(Unit:mm)
24.0±04
19.0±03
1.0±O.1
CD
INDEX MARK
• 80 PIN PLASTIC FLAT
(Unitmm)
2.1 ±O.2
25.0±O'
20.0 ±O.3
0-10"
O.S±O.I
INDEX MARK
29
• PACKAGING .-------------------------------------------------• 44 PIN PLASTIC PLCC
mm)
( u.n rmax:
t=-min:mm
INDEX MARK
1.27 T~P
~
16. 00
14.99
1
I
• 68 PIN PLASTIC PLCC
.
max:mm)
~unlt=--min:mm
INDEX MARK
;;;;5270
.2
~
~~\u:w
.o
~
f
@)
24.332
.~ ~4.130
®~.
'0
0
C::
§;
-
:~ ~
~
w
ww
0
O~
®
~
I.
30
.
23.62
·22.61
•
1
------------------e.
PACKAGING.
• 40 PIN PIGGY BACK
(Unit:mm)
• 42 PIN PIGGY BACK
(Unit:mm)
33.02
f-------
z_
2.54
~
x
<
en '('.1
m
ci Lr.i
31
ePACKAGINGe-------------------------------------------• 64 PIN SHRINK PIGGY BACK
(Unit:mm)
-----~- 58.00
1"-['
X
l
\
I
\
\
\
,,
General
electronic
"
m OSCb
\.:. PG J
'-PF.J LpE.....I \....po-' '-PK-"
PFalso
open drain
xl098
'----./
ADAH
76543210
SYNC MODE
'--ADAl ---I
&
Instruction
47
.MSM5840.--------------------------------------------~-----
PIN CONFIGURATION (Top View)
44 Pin Plastic Flat Package
42 PIN PLASTIC DIP (RS)
u
z
>
"'
Ao
A,
A,
A,
~
~
~
i.
~
~
0
0
>
l1 "' "' "' Ii.
~
~
~
B,
SYNC
B,
!NT
"-
RESET
0
PH:"
PHo
MODE
MODE
G,
WR
G,
RO
Go
osc,
PGo
OSCo
PG;
PG,
PGo
Ko
K,
PF o
PF;
PK,
K,
K,
E,
0,
PK,
PF,
PK,
PF'J
0,
0,
0,
"
GND
a -6
~
~
0
~
0
~
0
z uz I~
"
g'
~
~
w
~
PIN DESCRIPTION
Designation
Pin No,
GND
21
VDD
42
Main power source (+5V)
OSCo
10
Crystal OSC input, external ,clock input
OSC,
Crystal OSC input, external clock output (not TTL compatible)
PA,PB
1 t04
38 to 41
Pseudo-bidirectional ports for 4-bit parallel I/O. Used as a pair for 8-bit I/O. Used
to output 8 LSBs of address in external ROM mode, Used to read external
instruction during IF.
PD,PE,
PE,PG
17t020
23t034
Output ports for 4-bit parallel output and bit set/reset. Specified by internal
port pointer, Bit position specified by set/reset instruction, PD also used for
instruction address MSBs in external ROM mode during IF,
13 to 16
4-bit parallel or bit test input port (u nlatched)
PK
",PH
48
9
Function
CircuitGND potential
36 and 37
2-bit input port with latched memory (negative level sensitive)
RESET
7
RESET has_priority over every other signal. (see MSM5840 user's manual for
initialization sequence)
MODE
8
Used to enable external ROM mode during RESET and also to enable STOP mode
during execution (for stepping program)
INT
6
Negative edge sensitive external interrupt signal associated with EI and DI
instructions. Vectors to location 200H.
CIN
35
Negative edge sensitive external input for counter associated with ECT and DCT
instructions, Vectors to location 1OOH. (same as timer)
SYNC
5
General purpose synchronizing signal output at the beginning of each machine
cycle, Used for address strobe during external ROM mode.
Read strobe pulseoccuring when port A or B is read (1 A, 1B, 1AB)
RD
12
WR
11 '
Write strobe pulse occurring when port A or B is written (OA, OB, OAB, OBS, OTD)
IF
22
Read strobe pulse occurring during an instruction fetch from external ROM.
- - - - - - - - - - - - - - - - - - - - - - - - - - . MSM5840 •
FUNCTIONAL DESCRIPTION
Program ROM
The MSM5840 will address up to 4K bytes of
program ROM and can have 2K bytes of internal
masked ROM, or all ROM may be located externally. External EPROM may be used for program
development with conversion to internal ROM occurring after program debug and system checkout and verification. All instructions are byte
wide. Only three of the 98 instructions require
two bytes of program code. The instructions are
routed to a programmed logic array which generates the necessary internal control Signals.
Data RAM
Data is organized in 4 bit nibbles. Internal
data RAM consists of 128 nibbles, 8 nibbles of
which are dedicated registers accessible directly
under program control. These are the general
purpose registers, W, X, Y and Z, and the 4 save
(exchange) registers, CH, A, L, and AX. All other
DATA RAM must be addressed indirectly
through the DP (data po,nter) registers, a seven
bit pointer (directly accessible by numerous instructions) consisting of 4 bit DPL register and a
3 bit DPH register. Any nibble of internal data
RAM can be accessed through the DP registers.
Some instructions automatically change the contents of the DP registers allowing efficient array
processing.
Input/Output Ports
PA, PB - These two ports are pseudobidirectional ports which can be used as simple
I/O lines or used as either a 4-bit or 8-bit parallel
bus. An instruction fetches the external ROM
data through these ports by outputting the 8 low
order bits of address during SYNC followed by
an IF (instruction fetch) cycle. In addition,
synchronized data transfers are possible
throLl9il these ports with the I/O pin signals RD
and WR associated with certain input/output instructions dedicated to these ports. In short, PA
and PB can be used as a multiplexed address/
instruction/data bus.
PD, PE, PF, PG - These four output ports are
addressed indirectly through the TWO BIT port
pOinter whose contents are changed through
certain instructions. These ports are bit
(set/reset) addressable. PD is also used for the
high order bits of address during an external instruction fetch. PF and PG are open drain outputs and PG is set high by a hardware RESET.
PK is an input port without memory, addressable either as a nibble or bit level input.
PH is a two-bit input port with memory, which
can be tested and reset under program control.
External Interrupt
The TNT pin can be tested under program
control Dr enabled to cause a vectored interrupt
to location 200H. It is negative edge sensitive.
Timer/Counter
The timer/counter is an 8-bit counter whose
input is selected under program control to be
either an external Signal (CIN) or an internal
square wave of 1/128 the frequency of the OSCo
input (2 MHz/128 = 15.625 kHz). The
timer/counter can be enabled or disabled under
program control as can be associated internal interrupt which vectors to location 100H and has
higher priority than the external interrupt.
Stack
The stack is an LIFO queue for storing returnfrom-interrupt and return-from-subroutine address information. It is eleven bits wide and 4
levels deep.
Program Counter (PC)
The program counter is 11 bits wide and
loaded under program control.
Accumulator
The accumulator register is the data path
focal point of the CPU. Approximately one-half of
the instructions involve the accumulator. Its contents are t~e source and destination for many
ALU operations and port operations. CASE statements (computed GOTOs) are possible by using
the Jump with Accumulator (JA) instruction.
Flags
The MSM5840 is endowed with the following
set of flags.
Z - zero flag
Indicates that the result
of the previous operation
was zero
F- all ones
Indicates a carry from the
DPL register
0- all zeros
Indicates a borrow from
the DPL register
C - carry
Indicates a carry from the
previous operation
T - timer
Indicates that the timer/
counter is specified as a
timer
CT - counter
Indicates that the timer/
counter is specified as a
counter
TM - timer flag
Indicates an overflow of
the timer/counter register
INT - interrupt
Latching memory flag for
the external interrupt
INTE - interrupt
Indicates that interrupts
enable
have been enabled
Ho - Ho memory
Indicates that an input
has been detected on the
Ho input
same as Ho except H 1
input
X
o indicates internal ROM,
1 indicates external
ROM. If all external ROM,
o indicates first bank of
2K.
49
• MSM5840 . ' - - - - - - - - - - - - - ' - - - - - - - - - - - - - -
INSTRUCTION SET
Mnemonic
Instruction Code
Description
7
6
5
4
3
2
1
Byte
Cycle
0
CLA
Clear Accumulator
0
0
0
1
0
0
0
0
1
1
CLL
ClearDPL
0
0
1
0
0
0
0
0
1
1
CLH
ClearDPH
0
1
1
0
0
0
0
0
1
1
LAI
Load Accumulatorwith Immediate
0
0
0
1
Is
12
11
10
1
1
LLI
Load DPL with Immediate
0
0
1
0
13
i2
11
10
1
1
LHI
Load DPH with Immediate
0
1
1
0
'0
12
11
10
1
1
L
Load Accumulator with M~mory
1
0
0
1
0
1
0
0
1
1
LM
Load Accumulator with Memory then Modify DPH
1
0
0
1
0
1
11
10
1
1
LAL
Load Accumulator with DPL
0
1
0
1
0
1
0
1
1
1
LLA
Load DPL with Accumulator
0
1
0
1
0
1
0
0
1
1
LAW
Load Accumulator with W Register
1
0
0
0
0
1
0
0
1
1
LAX
Load Accumulatorwith X Register
1
0
0
0
0
1
0
1
1
1
a:
LAY
Load Accumulator with Y Register
~
1
0
0
0
0
1
1
0
1
1
LAZ
1
:;;
Q)
(3
-g
Q)
.9
(f)
, j SI
21 SMI,
...J
Load Accumulator with Z Register
1
0
0
0
0
1
1
1
1
Store Accumulator to Memory then Increment DPL
1
0
0
1
0
0
0
0
1
1
Store Accumulator to Memory then Modify DPH
and Increment DPL
1
0
0
1
0
0
11
10
1
1
1
LWA
. Load W Registerwith Accumulator
1
0
0
0
0
0
0
0
1
LXA
Load X Register with Accumulator
1
0
0
0
0
0
0
1
1
1
LYA
Load Y Register with Accumulator
1
0
0
0
0
0
1
0
1
1
LZA
Load Z Register with Accumulator
1
0
0
0
0
0
1
1
1
1
LPA
Load Port Pointer with Accumulator
0
1
0
1
1
0
0
0
1
1
LTI
Load Timerwith Immediate
0
1
15
0
I.
1
Is
0
0
0
2
2
17
1
I.
12
11
10
RTH
Read TimerH
0
1
1
0
1
0
1
0
1
1
RTL
ReadtimerL
0
1
1
0
1
0
1
1
1
1
XA
Exchange Accumulator with Save Register A
0
1
0
0
1
0
0
1
1
1
XL
Exchange DPL with Save Register L
0
1
0
0
1
0
1
0
1
1
XCH
Exchange DPH and Carry with Save Register CH
0
1
0
0
1
0
0
0
1
1
X
Exchange Accumulatorwith Memory
1
0
0
1
1
0
0
0
1
1
XM
Exchange Accumulator with Memory then Modify
DPH
1
0
0
1
1
0
11
10
1
1
XAX
Exchange Accumulator with Save Register AX
0
1
0
0
1
0
1
1
1
1
INA
Increment Accumulator
0
0
0
0
0
0
0
1
1
1
INL
Increment DPL
0
1
0
1
0
1
1
1
1
1
0
INM
Increment Memory
0
1
0
1
1
1
0
1
1
1
Cl
.....
INW
Increment W Register
1
0
0
0
1
0
0
0
1
1
INX
Increment X Register
1
0
0
0
1
0
0
1
1
1
INY
Increment Y Register
1
0
0
0
1
0
1
0
1
1
INZ
Increment Z Register
1
0
0
0
1
0
1
1
1
1
Q)
Cl
<:
to
.r::
0
x
UJ
C
Q)
E
~
Q)
C
Q)
E
~
0
.!:
50
Skip if Zero
----------------------------------------------------eMSM5840e
INSTRUCTION SET (CONT.)
Mnemonic
DCA
Description
Decrement Accumulator - Skip if Not All Ones
"E
DCL
Q)
Decrement DPL
E DCM
Decrement Memory
~
u
"'
Instruction Code
7
6
5
4
3
2
1
Byte
Cycle
0
0
0
0
0
1
1
1
1
1
1
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
1
1
DCW
Decrement W Register
DCX
Decrement X Register
1
0
0
0
1
1
0
1
1
1
E DCY
Decrement Y Register
1
0
0
0
1
1
1
0
1
1
u
.E
DCZ
Decrement Z Register
1
0
0
0
1
1
1
1
1
1
DCH
Decrement DPH - Skip if All Ones and C = Zero
0
1
0
1
1
1
1
1
1
1
CAO
Complement Accumulator of One
0
1
0
1
0
0
0
0
1
1
AND
And Accumulator with Memory
0
1
0
0
0
1
0
0
1
1
OR
Or Accumulatorwith Memory
0
1
0
0
0
1
0
1
1
1
EOR
Exclusive or Accumulator with Memory
0
1
0
0
0
1
1
0
1
1
RAL
Rotate Accumulator Left through Carry
0
1
0
0
0
1
1
1
1
1
AC
Add Memory to Accumulator with Carry
0
1
0
0
1
1
0
0
1
1
ACS
Add Memory to Accumulator with Carry, Skip
if Carry
0
1
0
0
1
1
0
1
1
1
1
0
1
1
10
1
1
0
1
1
. 1
Q)
e"E
Q)
~
"iii
u
"0>
0
...J
Skip if All Ones
~
AS
Add Memory to Accumulator, Skip if Carry
0
1
0
0
1
1
u
AIS
Add Immediate to Accumulator, Skip if Carry
0
0
0
0
13
12
E
DAS
Decimal adjust Accumulator in Subtraction
0
1
0
1
1
0
"
~
CM
Compare Accumulatorwith Memory, Skip if Equal
0
1
0
1
1
1
1
0
1
AWS
Add W Register to Accumulator, Skip if Carry
1
1
1
0
0
1
i
AXS
Add X Register to Accumulator, Skip if Carry
1
0
0
1
1
1
0
1
1
1
AYS
And Y Register to Accumulator, Skip if Carry
1
0
0
1
1
1
1
0
1
1
AZS
Add Z Register to Accumulator, Skip if Carry
1
0
0
1
1
1
1
1
1
1
SPB
Set Port Bit
1
0
1
1
0
0
11
10
1
1
RPB
Reset Port Bit
1
0
1
1
0
1
11
10
1
1
5MB
Set Memory Bit
1
0
1
1
1
0
11
10
1
1
RMB
Reset Memory Bit
1
0
1
1
1
1
11
10
1
1
en
TAB
Test Accumulator Bit
1
0
1
0
0
0
11
10
1
1
Q)
TMB
Test Memory Bit
1
0
1
0
0
1
1
1
1
0
1
0
1
0
"
10
Test K Port Bit
11
10
1
1
1
0
1
0
1
1
0
10
1
1
~
£;
fE.
"-
gj TKB
~
Q)
C/)
[ii
0
0
1
1
THB
Test H Port Bit
TI
Test Interrupt flag
1
0
1
0
1
1
1
1
1
1
TTM
Test Time flag
1
0
1
0
1
1
1
0
1
1
1
Skip if One
TC
Test Carry flag
0
1
0
0
0
0
1
0
1
SC
Set Carry flag
0
1
0
0
0
0
0
0
1
1
RC
Reset Carry flag
0
1
0
0
0
0
0
1
1
1
51
• MSM5840 ••----------------------------------------------------
INSTRUCTION SET (CONT.)
Mnemonic
Q)
J
I nstruction Code
Description
Jump
:§
7
6
5
4
3
1
0
0
17
0
I.
1
I.
1
I.
0 110 19
10 I. il
10
1
I.
I.
10
i2
i1
10
0
2
a
Byte
Cycle
2
2
1
1
:::l
e
JC
Jump in Current Page
1
:::l
(j)
JA
Jump with Accumulator
0
1
0
0
0
1
1
1
1
CAL
Call Subroutine
0
17
0
1
I.
1 110 19
10 I. il
a
2
2
I.
1
I.
RT
Return from Subroutine
0
1
0
1
1
0
0
1
1
2
OBS
Output Byte String
0
1
1
1
0
0
0
0
1
2-17
OTD
Output Table Data
0
1
1
1
0
0
0
1
1
2
OA
Output Accumulator to Port A
0
1
1
1
0
0
1
0
1
1
OB
Output Accumulator to Port B
0
1
1
1
0
0
1
1
1
1
Output Accumulator to Port P designated Port
Pointer
0
1
1
1
0
1
0
0
1
1
.c
".<:
0
c:
f!!
ID
'5Q.
OP
'5
0
:;;;
10
:::l
OAB
Output Memory and Accumulatorto Ports A and B
0
1
1
1
0
1
0
1
1
1
E
OPM
Output Memory to Port P designated Port Pointer
0
1
1
1
0
1
1
0
1
1
IA
Input PortA in Accumulator
0
1
1
1
1
0
1
0
1
1
IB
Input Port B in Accumulator
0
1
1
1
1
0
1
1
1
1
IK
Input Port K in Accumulator
0
1
1
1
1
1
0
0
1
1
lAB
Input Ports A and B in Memory and Accumulator
0
1
1
1
1
1
0
1
1
1
EI
Enable Interrupt
0
1
0
1
0
0
1
1
1
1
DI
Disable Interrupt
0
1
0
1
0
0
1
0
1
1
ET
Enable Timer
0
1
1
0
1
1
1
1
1
1
Q.
ec:
0
(.)
52
DT
Disable Timer
0
1
1
0
1
1
1
0
1
1
ECT
Enable Counter
0
1
1
1
1
1
1
1
1
1
DCT
Disable Counter
0
1
1
1
1
1
1
0
1
1
HLT
Halt
0
1
1
0
1
1
0
1
1
1
EXP
Exchange Program
0
1
1
0
1
0
0
1
1
1
NOP
No Operation
0
0
0
0
0
0
0
0
1
1
- - - - - - - - - - - - - - - - - - - - - - - - - . MSM5840 •
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Input Voltage
Operating Voltage PF PG
Storage Temperature
Symbol
Conditions
VDD
Ta=25°C
-0.3t07
V
VI
Ta=25°C
-0.3toVDD
V
Vo
Ta=25°C
-0.3 to 25
V
-55to+150
°C
Tstg
Limits
Unit
Note: Stresses above those listed under ABSOLUTE MAXIMUM RATI NGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device atthese or at any other condition above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
OPERATING CONDITIONS
Parameter
Symbol
Supply Voltage
VDD
Operating Temperature
Top
Fan Out
N
Conditions
Limits
Unit
@1 MHz
3t06
V
@4.2MHz
4.5 t05.5
V
-40to+85
°C
MOSLoad
15
TTL Load
1
D.C. CHARACTERISTICS
(VDD
= 5V± 10%, Ta = -20° to + 70
0
e)
Symbol
Conditions
Min.
High Input Voltage
VIH
-
3.6
Low Input Voltage
VIL-
-
Parameter
High Output Voltage (1)
Low Output Voltage
OSCo Input Leak Current
PA, PB High Output Current
V
0.8
4.2
V
V
VOL
10= 1.6mA
0.4
V
VI =VDD/OV
25
I---25
/LA
VI =VDD/OV
1
I---50
/LA
VI =VDD/OV
I---
IIH
IIH
IIH
IlL
High Output Current(l)
Unit
VOH
IlL
Input Leak Current(2)
Max.
10=-40/LA
IlL
RESET, MODE LeakCurrent
Typ.
1
-1
-1
/LA
mA
10H
VOH=0.4V
IOH
VOH=2.5V
-0.25
mA
10L
VOL =0.4V
1.6
mA
BVOH
IO=10/LA
20
V
Input Capacitance
CI
f= 1 MHz
Ta=25°C
5
pF
Output Capacitance
Co
f=lMHz
Ta=25°C
7
pF
IDD
VI =VDD/OV
10
200
/LA
IDD
VI =VDD/OV
f=4.2MHz
1.6
4
mA
Low Output Current
PF, PG Output Breakdown Voltage
Current Consumption(3)
Notes: (1) Except PA, PB (see graphs)
, (2) Except OSCo, RESIT, iiilCiDE
(3) Typical Value of VDD is 5V
53
\ • MSM5840 ...--------~---------------'----
A.C. CHARACTERISTICS (INTERNAL ROM MODE)
(VDD
= 5V±1 0%, Ta = -:-40° to +85°C)
Parameter
Symbol
Cycle Time
Sync Pulse Width
RD Pulse Width
tRW
Sync 1toRO 1
Typ.
Min.
Max.
tCY
/LS
tsw
0.95
/LS
1.9
/LS
tRD
tww
Sync 1toWR 1
tWD
CL =50pF
CL =50pF
112 tCY +0.5
/LS
0.95
/LS
13/16 tCY +0.5
/LS
tDSR
4/16tCY
Port Input Hold Time
tDHR
0
WR 1to New Data Valid
tDDW
PA,PB
CL =50pF
Sync 1to New Data Valid
tDDS
PD, PE, PF, PG
CL =50pF
(1 )
PHo, PH ,Input Pulse Width
tHW
CIN Input Pulse Width
tcw
INT Input Pulse Width
tlNTW
(1 )
/LS
0.8
/LS
0.8
/LS
13/16tCY+0.5
/LS
500
nS
250
nS
500
nS
Note: (1) The processor logi c wi II ignore the followi ng events:
1. An INTfalling edge occurring during TINH of a TI instruction .
.2. A PHoor PH ,low level occurring only during TINH of a THB instruction.
TIMING CHARTS
SYNC
--'
~
I
·1
'Cy
[;-tRD
FlO
two
tRW--
~I
+'WW
WR
I
PA, PB
)
(11
INPUT DATA
!----tDSR_
PK
I
DON'T CARE
8-
~ NEW OUTPUT
DATA
I--tDHR
INPUT DATA
DON'T CARE
'I
tDDS
:1
PD,PE
OLD DATA
PF, PG
ftH~i
tcw
JI
NEW DATA
·1
I
i
~
I-tINTW
tNT
It-----\
I
1/2 tCY
I
I
tlNH
17/16t Cyl
Note: (1) All 'ONES' must be output before reading port A or B.
54
Unit
7.6
WR Pulse Width
Port Input Setup Time
Conditions
I
1/16tCY
- - - - - - - - - - - - - - - - - - - - - - - - - ' . MSM5840 •
A.C. CHARACTERISTICS (EXTERNAL ROM MODE)
(Voo
= 5V±1 0%, Ta = -40° to +85°C)
Parameter
Conditions
Symbol
CycleTime
Sync Pulse Width
IF Pulse Width
Sync TtolF!
Address Low Delay
Address Low Hold
Min.
Typ.
Max.
Unit
tcv
7.6
1-'5
tsw
0.95
1-'5
tlW
1.425
1-'5
tiD
CL=50pF
tLAD
CL=50pF
3/16 tcv + 1
1-'5
0.8
tLAH
1/16tCV
Instruction Setup
'tiS
1/16tCV
Instruction Hold
tlH
Data Recovery
tOR
CL=50pF
Address High Delay
tHAD
CL =50pF
Address High Hold
tHAH
1-'5
1-'5
1/16tCV+1
1-'5
nS
'20
0
0
0.8
1-'5
0,5
1-'5
0,5
1-'5
CV
tsw
SYNC
~
--I
tiD
tLAD
~tL~H.:I
1--,
PA,PB
DATA
tlW_
{
INSTR
tHAD
PO
DATA
--
tlS_
ADDRESS
LOW
HH
ADDRESS HIGH
I
Cycle Dependent Timings
4MHz
1
I
DATA
tOR
DATA
tHAH
2MHz
1MHz
500kHz
1/16tcv
0.51-'5
11-'5
21-'5
1/16tCV+1
1.51-'5
21-'5
31-'5
51-'5
3/16tcV+1
2.51-'5
41-'5
71-'5
131-'5
4/16!cV-1
11-'5
31-'5
71-'5
151-'5
1/2tC),+1
51-'5
91-'5
171-'5
331-'5
41-'5
7/16tCV
3.51-'5
71-'5
141-'5
281-'5
13/16tcV+1
7.51-'5
141'5
271'5
531'5
55
.MSM5840.'----------------~----------------------------------
TYPICAL PERFORMANCE CURVES
Supply Current vs Supply Voltage
Supply Current vs Oscillator Frequency
(Ta = 25°C, No Load)
(Ta = 25°C, No Load)
lpm ,-----.---,-~-,__--r--__,
10m ,------,..----,__---.,.-__,
Voo =6V
I
5V
lm~---~---+_~~
~
C
C
l00j,l
100j,l~---T7~~~+_--__i
~
0
E
_ _ _.L.-_ _ _
10M
1M
lOOK
10j,lL_~~_L_
10j,l
10K
f
0.1 j,I
~
(OSC) (Hz)
' - - - ' - _ - ' -_ _.L.-_-'-_ _---'
o
5
3
7
10
Voo(V)
Oscillator Frequency vs Supply Voltage
Oscillator Frequency vs Temperature
(CL = 50pF)
(Ta,; 25°C, CL = 50pF)
10
10
8
j
N
J:
~
6
en
.....
V
4
..........
J:
~
/
(j
g
8
N
6
r--..
(j
en
g
.....
-
4
I
2
o
2
o
1
3
5
VOO(V)
5~
7
10
-50
o
50
Ta (OC)
100
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ e MSM5840 e
High Current Out vs Voltage
iLow Current Out vs Voltage
(Ta = 25°C, Except PA, PS)
-10r-.-----,-----r-----r-------,
~r-~----+_--~----_r------~
~
E
-6
t-~----+_--~----_r------~
:c
1 0 r--tH'---:;;;;......~-+
o
5~~~--+_----r_--~------~
3
5
10
7
3
Va (V)
Rise Time vs Load
(Ta = 25°C, PA, PB, PO, PE, RO, WR,IF, SYNC)
on
c:
...I-
(Ta = 25°C, PO, PE, RO, WR,
1000
1000
800
800
..s:c
600
200
10
20
50
--100
VOO =5V
~
200
CL (pF)
iF, SYNC)
/
600
/
/VOO=5V
...J
t"
400
o
10
7
Va (V)
Fall Time vs Load
-:J
:c
5
400
-
200
...V
/
/
o
500
1000
10
20
50
100
200
500. 1000
CL (pF)
57
OKI
semiconductor
MSM5842
CMOS 4-BIT SINGLE CHIP MICROCONTROLLER
GENERAL DESCRIPTION
The OKI MSM5842 microcontroller is a low-power, high-performance single chip device implemented in complementary metal oxide semiconductor technology. Integrated with this one chip are
6K bits of mask program ROM, 128 bits of data RAM, 21 Input/Output lines, an 8-bit binary
timer/counter, and oscillator. Program memory is byte wide and data paths are organized in 4 bit nibbles. RAM and I/O lines are bit addressable. 52 instructions include binary, BCD, operations; bit set,
reset, test;8-bit I/O; relative jumps; multifunctional instructions (increment, modify, skip); 8-bit wide
table output; subroutine call and return. 94% of instructions are Single byte, Single cycle operations.
Available in plastic (RS) package.
FEATURES
•
•
•
•
•
•
•
Low Power Consumption - 7mW Typical
100% Static Logic - 1 OO/lW Standby
768 x 8 Internal ROM
32 x 4 Internal RAM /
21 I/O Lines Inci. 8 Bit Data Bus
8 Bit Binary Timer/Counter
Self-contained Oscillator
FUNCTIONAL BLOCK DIAGRAM
32)(4
I
,
RAM
,
FEDCBA9876
DEC
32103210
'-PE-J
58
'-po--.J
3
'----PK---J
•
•
•
•
•
•
•
52 Instructions
1 Stack Level
-20° to +70°C Operating Temperature
3V to 6V Operating VDD
Battery Powered or Battery Backup
TTL Compatible (with pullups)
7.6"s Cycle Time @4.2MHz
• MSM5842 •
PIN CONFIGURATION (Top View)
32 Pin Flat Package
28 PIN PLASTIC DIP (RS)
vOO
PE,
PE,
PE,
PA,
PBo
PB,
PO,
PB,
PB,
NC
PO,
GNO
PEo
PO,
POo
PBo
PK,
PB,
PK,
PB,
PK,
PB,
PKo
GNO
CIN
0
PA,
PA,
PAo
RESET
OSC,
OSC,
SYNC
PHo
NC
PK,
PK,
YOD
NC
PE,
PE,
PE,
NC
POo
PO,
PEo
PO,
PO,
CIN
PKo
PK,
PIN DESCRIPTION
Designation
Pin No.
GND
14
CircuitGND potential
VDD
2B
Main power source (+5V)
Function
OSCo
4
Crystal OSC input, external clock input
OSC,
3
Crystal OSC input, external clock output (not TTL compatible)
PA,PB
6to 13
QuaSi-bidirectional ports for 4 bit parallel I/O. Used as a pairforB bit I/O.
PD,PE
20t027
Output ports for 4 bit parallel output and bit sel/reset. Specified by internal port
pointer. Bit position specified by set/reset instruction.
PK
16 to 19
4 bit parallel or bit test input port (unlatched)
PH
1
1 bit input port with latched memory (negative level sensitive)
RESET
5
RESET must be low for more than one machine cycle and has priority over every
other signal. (see MSM5B42 user's manual for initialization sequence)
CIN
15
SYNC
2
Negative edge sensitive external input for timer/counter.
General purpose synchronizing signal output at the beginning of each machine
cycle.
59
• MSM5842
.--~--------------------'"---
FUNCTIONAL DESCRIPTION
Program ROM
The MSM5842 will address up to 768 bytes
of program ROM. All instructions are byte wide.
Only three of the 52 instructions require two
bytes of program code. The instructions are
routed to a programmed logic array which generates the necessary internal contral signals.
Data RAM
Data is organized in 4 bit nibbles. Internal
data RAM consists of 32 nibbles and one nibble
which is a dedicated general purpose register,
W, accessible directly under program contraL
DATA RAM must be addressed indirectly
through the DP (data pointer) register, a five bit
pointer (directly accessible by numerous instructions) consisting of a 4 bit DPL register and a 1
bit DPH register. Any nibble of internal data RAM
can be accessed through the DP registers. Some
instructions, automatically change the contents
of the DP register allowing efficient array processing.
Input/Output Ports
PA, PB - These two ports are pseudobidirectional ports which can be used as simple
I/O lines or used as either a 4 bit or 8 bit parallel
bus.
PO, PE - These two output ports are addressed indirectly through the ONE BIT port
pOinter whose contents are changed through
certain instructions. These ports are bit (set!
reset) addressable.
PK is an input port without a Latch circuit, addressable as a nibble input.
PH is a one bit input port with a Latch circuit,
which can be tested and reset under program
control.
Timer/Counter
The timer/counter is an 8-bit counter whose
input is an external signal (CiN). The TM flag is
set when the timer/counter generates a carry.
Stack
The stack is a single register for storing
return-fram-subroutine address information. It is
ten bits wide.
Program Counter (PC)
The program counter is ten bits wide.
Accumulator
The accumulator register is the data path
focal point of the CPU. Approximately one-half of
the instructions involve the accumulator. Its
contents are the source and destination for
many ALU operations and port operations. CASE
statements (computed GOTOs) are possible by
using the Jump with Accumulator (JA) instruction.
Flags
The MSM5842 is endowed with the following
set of flags.
Z - zero flag
Indicates that the result
of the previous operation
was zero
C - carry
Indicates a carry from the
previous operation
Indicates an overflow of
TM - timer flag
the timer/counter register
Ho - Ho memory
Indicates that an input
has been detected on the
Ho input
INSTRUCTION SET
Mnemonic
CLA
CCL
CLH
~
LAI
(I)
Q LL.I
"Ci LHI
(I)
a: L
~ LAL
LLA
LAW
.9 SI
LWA
LPA
LTI
'"
c5
-g
60
Description
Instruction Code
4
3
0
1
0
0
0
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
Is
Is
12
12
"
0
0
0
1
0
0
10
10
10
0
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
7
6
5
Clear Accumulator
0
0
ClearDPL
ClearDPH
Load Accumulator with Immediate
0
0
0
0
1
0
Load DPL with Immediate
Load DPH with Immediate
Load Accumulatorwith Memory
Load Accumulator with DPL
0
0
1
0
1
0
0
0
1
1
1
0
0
0
1
1
Load DPL with Accumulator
Load Accumulatorwith W Register
Store Accumulatorto Memory then Increment DPL
Load W Registerwittr Accumulator
Load Port POinter with Accumulator
Load Timer with All Zeros
1
1
0
0
1
0
0
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
1
0
1
1
2
1
11
0
Byte
Cycle
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
--------------------~----------------------------.MSM5842.
INSTRUCTION SET (CONT.)
Descri ptlon
Mnemonic
Instruction Code
Byte
Cycle
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
1
0
1
1
1
1
1
1
1
I.
0
1
0
1
11
1
1
0
0
10
0
0
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
1
0
0
0
11
11
11
11
0
1
1
0
0
10
10
10
10
10
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 0 0
I. I. I.
17
1
I. Ia I.
0
0 0 0 0
0 ,0 1 1 1 0
17 I. I. I. Ia I.
0 1 0 1 1 0
I.
11
11
1
I.
11
0
I.
10
10
1
2
2
1
1
1
1
•
2
2
7
6
5
4
3
2
1
0
Exchange Accumulatorwith Memory
1
0
0
1
1
0
0
INL
INM
INW
DCA
DCL
DCM
Increment Accumulator
Increment DPL
Skip if Zero
Increment Memory
IncrementW Register
Decrement Accumulator- Skip if Not All Ones
Decrement DPL
} Skip if All Ones
Decrement Memory
0
0
0
1
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
0
1
0
0
1
1
0
CAO
RAL
Complement Accumulatorof One
Rotate Accumulator Left through Carry
0
0
1
1
0
0
1
0
0
0
0
1
AC
AS
AIS
DAS
CM
Add Memory to Accumulatorwith Carry
Add Memory to Accumulator, Skip if Carry
Add Immediate to Accumulat9r, Skip if Carry
Decimal adjust Accumulator in Subtraction
Compare Accumalator with Memory, Skip if Equal
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
I.
1
1
5MB
RMB
TAB
TMB
THB
TIM
TC
SC
RC
Set Memory Bit
Reset Memory Bit
Test Accumulator Bit
Test Memory Bit
Test H Port Bit
TestTimer flag
Test Carry flag
Set Carry flag
Reset Carry flag
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
J
Jump
0
JC
JA
CAL
Jump in Current ~age
Jump with Accumulator
Call Subroutine
Q)
01
c::
os
.&;
X
0
><
w
'EQ) INA'
E
e?
&l
c
:::c::
Q)
E
e?
0
c::
os
0
'e,
0
~
0
i
E
:5
~
'iii
~
1i
Q)
a:
-..
1ii
en
iii
Q)
.S:
:;
2
.c
:>
en
-..
.&;
0
c::
~
aJ
:;
Q,
:;
~Q,
1
I.
I.
1
10
RT
Return from Subroutine
1
1
2
OTD
OA
OB
OP
Output Table Data
Output Accumulator to Port A
Output Accumulator to Port B
Output Accumulator to Port P designated Port
Pointer
Output Memory to Port P deSignated Port Pointer
Input Port A in Accumulator
Input·Port B in Accumulator
Input Port K in Accumulatgr
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
0
1
1
1
2
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
1
1
1
1
1
1
1
No Operation
0
0
0
0
0
0
0
0
1
1
0
.E
0
I.
1
1
0
0
0
OPM
IA
IB
IK
2
NOP
'E
0
U
61
eMSM5842
.e----------------------------------------------------
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Input Voltage
Storage Temperature
Unit
Symbol
Conditions
VDD
Ta=25°C
-0.3t07
V
VI
Ta=25°C
-Q.3toVDD
V
-55 to +150
°C
Tstg
Limits
Note: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or at any other condition above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
OPERATING CONDITIONS
Parameter
Supply Voltage
Operating Temperature
Symbol
VDD
Conditions
Limits
Unit
1MHz
3t06
V
4.2MHz
4.5t05.5
V
-40t085
°C
Top
Fan Out
MOSLoad
40
TTL Load
1
,
D.C. CHARACTERISTICS
(Voo
= 5V±1 0%, Ta = -40° to +85°C)
Symbol
Conditions
Min.
High Input Voltage
VIH
-
3.6
Low Input Voltage
VIL
-
High Output VOltage (1)
VOH
10=-4O!LA
Low Output Voltage
VOL
10= 1.6mA
Parameter
OSCo Input Leak Current
IIH
IlL
RESET Leak Current
IIH
IlL
Input Leak Current(2)
IIH
IlL
Typ.
Max.
Unit
V
0.8
4.2
V
V
0.45
V
25
VI=VDD/OV
f----
VI =VDD/OV
-
VI=VDDIOV
-
-25
!LA
1
-20
!LA
1
-1
PA, PB High Output Current
10H
VOH=0.4V
High Output Curreni( 1)
10H
VOH=2.5V
-'0.25
Low Output Current
10L
VOL=0.45V
1.6
Input Capacitflnce
CI
f= 1 MHz
Ta=25°C
5
pF
Output Capacitance
Co
f= 1 MHz
Ta=25°C
7
pF
IDD
VI=VDD/OV
20
200
!LA
IDD
VI=VDD/OV
f=4.2MHz
1.5
4
rnA
Current Consumption(3)
Notes: (1) Except PA, PB (see graphs)
(2) Except OSCo, RESET
(3) Typical Value of VDD is 5V
62
-1
!LA
mA
mA
rnA
- - - - - - - - - - - - - - - - - - - - - - - - - - . MSM5842 •
A.C. CHARACTERISTICS
(VDD
= 5V±1 0%, Ta = -40° to +85°C)
Symbol
Conditions
Min.
Cycle Time
Parameter
tCY
OSC=;4MHz
7.6
Sync Pulse Width
tsw
Port Input Invalid Time
tDiV
Port Input Valid Time
tDV
Typ.
Max.
Unit
Io'S
0.95
Io'S
112 tCY +0.5
2
Sync Tto New Data Valid
tDDS
PD, PE CL = 50pF
PHo Input Pulse Width
tHW
(1 )
Ciiifinput Pulse Width
tcw
Io'S
10'8
13/16 tCY + 0.5
Io'S
250
nS
250
nS
Notes: (1) The processor logic may ignore the following event:
A PHo low level occurring only during TINH of a THB instruction.
(2) All 'ONES' must be output before reading port A or B.
TIMING CHARTS
tCY
_tSW.=i
r--
}
SYNC - - J
PA,PB
NEW OUTPUT DATA
INPUT DATA
Note 2
tOlV
PK
tDV-
DON'T CARE
INPUT DATA
DON'T CARE
tDDS
PD,PE
OLD DATA
NEW DATA
f--tHWPH O
If
CIN
1/2 tCY
~
tcw-y
-"\"-
tlNH
7 /16 tCY
I
I
1/16 tc y
63
eMSM5842
e----------------------------------------------------
TYPICAL PERFORMANCE CURVES
Supply Current vs Supply Voltage
Supply Current vs Oscillator Frequency
(Ta = 25°C, CL = 15pF)
(Ta = 25°C, No Load)
10m
10m
I(OSC) = 8MHz
4MHz
1m ~~~~~~q2MHz
lMHz
100KHz
5
100 1L
1m
5
Cl
100IL
~
Cl
.9
.9
lOlL
I
V
VOO = 5 ' l
/
lOlL
OHz
1/L
0.11L L-oL-o-L_....L._...I.._--'
o 1
3
5
7
10
10K lOOK
VOo(V)
Oscillator Frequency vs Temperature
(Ta = 25°C, CL = 50pF)
N
~
6(/)
8
0
6
;::;
:c
:2
G
V
I'
8
(/)
o
;::;
6
4
2
2
o
3
5
VOo(V)
64
......... ~=5V
N 10
4
0
(CL =50pF)
12
/
:c
6
14
V
10
10M
I(OSC)(Hz)
Oscillator Frequency vs Supply Voltage
12
1M
7
10
-50
100
- - - - - - - - - - - - - - - - - - - - - - - - - - - . MSM5842 •
Low Current Out vs Voltage
High Current Out vs Voltage
(Ta = 25°C)
(Ta = 25°C)
-4
20
15
«E
10
/'
5
o
I--
I
.9
VDD=5V
1
r-.....
-2
5
7
10
o
3
5
Fall Time vs Load
10
Rise Time vs Load
(Ta = 25°C, PA, PB, PD, PE, SYNC)
(Ta = 25°C, PD, PE, SYNC)
1000
1000
I
800
800
Cii
c:
c:
I..J
7
Vo(V)
Vo(V)
(ij
PD,PE
SYNC
VDD=5V
15y(PA~
o
3
I'-..
VDD~
-1
V
o
-3
':J
600
:r:
!:"
!:"
400
/
600
j
400
200
o
10
20
-
D=5V
~
V
50 1 00 200
CL(pF)
VI'
500 1000
200
o
-
10 20
V
VDD
=5V
V
V
50 1 00 200 500 1 000
CL(pF)
65
OKI
semiconductor
MSM58421
CMOS 4-BIT SINGLE CHIP MICROCONTROLLER WITH LCD DRIVER
GENERAL DESCRIPTION
The OKI MSM58421 is a low-power, high-performance 4-bit single-chip microcontroller implemented in complementary metal oxide semiconductor technology.
Integrated within this one chip is a 5 digit 7-segment LCD driver and PLA which can change the
character font for the 7 segments freely under the control of the mask programmable data.
Also integrated in this chip are mask ROM of 1536 x 8 bits for programming, data RAM of 40 x 4
bits, 13 general-purpose input/output ports, 12-bit timer, and clock oscillator to facilitate easy application to equipment with an LCD display.
FEATURES
•
•
•
•
•
•
•
•
Low Power Consumption CMOS 4-bit
One-Chip Microcomputer
100% Static Logic
1536 x 8 bits Mask ROM
40 x 4 bits Data RAM
1 Static Register
Built-in 1 2-bit Timer (with 32 Hz Common
Output)
All Input Ports Contain Schmitt Trigger
Circuits
8-bit Interface Bus
•
•
52 Instructions
94% of the 52 Instructions are 1 Byte and1
Machine Cycle
Integrated with 13 Input/Output Ports and 40
Static LCD Driver Circuit
+5V Single Power Supply, 60-Pin Mold Flat
Package
7 -Segment Character User Programmable
Font (32 Words x 7 Segments)
Various Functions Changeable under Mask
Program Control
•
•
•
•
FUNCTIONAL BLOCK DIAGRAM
54321 gfedcbagfedcba gfedcba:gfedcba'gtedcba
\'PlCD6J'-PLCD5-J'-PLCD4--"-PLCD3...J\"'PLCO:z-,J'-PLC01..J
C
Z
3
21
0
PH
3 2 1
L - PK-J
a
N
• Crystal Oscillator 4.194304 MHz, SYNC
66
= 7.63 ,",sec LCD common signal
0
3 2 1
0
'---PB--J
M
32 Hz
"'6 OVoo G
y 5 S
N
Nee
0
5
c
1 0
- - - - - - - - - - - - - - - - - - - - - - - - - . MSM58421 •
LOGIC SYMBOL
PIN CONFIGURATION
~
~
) PORT A
;J;;J;
RESET
i~ ~~ ±~ j ~
~ ~
~
.,
~~
0
!J
0
0
~ ~
r
~
J
PORT B
RES-ET
PLCDJ-e
PLCD5-c
PLCD3-d
J
PLeD 1
PLCD3-c
J
PLeD 2
PLCD2-e
] PLeD 3
PLCD2-c
PLCD6-5
PORT H
PlCD2-d
PORT K [
Ko
K,
K,
PLCD2-g
J
K;
PLCD1-e
PLeD 4
J PLeD 5
J PLeD 6
PLC01-d
PLCDS-f
PLeD l-c
PLC01-b
PLeD 1-9
PLCD5-Q
PlC06-!
PH
GND
COMMON
SYNC
+5V-
vDD
OSCI
ov
SYNC
COMMON
-
SYNC SIGNAL OUTPUT
- - - COMMON SIGNAL OUTPUT
o
o
>
PIN DESCRIPTION
Designation
Pin No.
GND
33
VDD
23
Main power source (+5V)
OSCo
17
Crystal OSC input, external clock input
Function
CircuitGND potential
OSC,
16
PA,PB
19 to 22
24 t027
Pseudo-bidirectional ports for 4-bits parallel I/O. To input data from these ports, it is
necessary to write "1" to them beforehand. When nothing is applied to their
terminals, the content of output ports is written in them, sothey can also be used as
registers. In addition, it is possible to use them for make 8-bit parallel output
depending on instructions.
PK
28t031
Input ports for4-bit parallel input with no latching function.
PH
14
Input port with latching function to be set by negative logical signal.
That is, this terminal is set at the time when the negative logical signal is applied to it
from the. outside.
It is reset automatically after execution of the test instruction of this port.
RESET
18
The RESET signal which input has priority over all of other signals and performs the
following functions:
(1) Resets all bits of the program counter;
(2) Resets the timer counter and timer flag;
(3) Resets the port pointer;
(4) Resets the accumulator;
(5) Resets I/O ports PA and PB;
(6) Resets the input port PH flag;
(7) Initializes the output port PLCD for LCD;
(8) Resets the machine cycle to M ,.
Since the RESETterminal is pulled up to VDD by an internal resistor (approx. 800
kO), it is possible to make power ON/reset by connecting itwith an external
capacitor.
Crystal OSC input, external clock output (not TTL compatible)
67
.e------------------------------------~----~-------
eMSM58421
PIN DESCRIPTION (CONT.)
Designation
Pin No.
SYNC
15
PLCD
1 -6
1 to 13
34 to 60
Function
General-purpose synchronizing signal output. The signal is output at the beginning
of each machine cycle. Output constantly, this signal is used also as clock pulse to
external units.
The cycle of SYNC becomes 32 times that of the original oscillation (8,..,s when the
clock pulse is 4 MHz).
PLCD 1 - 6 (Pins 1 - 13 and 34 - 60)
7 -bit and 5-bit parallel output ports, respectively. They are used to direct drive an
LCD (static type). Specification of each port is done by the port pointer (PP) as
shown in the table below:
Content of PP
Port Specified
b3
b2
b,
bo
x
0
0
0
PLCDl
x
0
0
1
PLCD2
x
0
1
0
PLCD3
x
0
1
1
PLCD4
x
1
0
0
PLCD5
x
1
0
1
PLCD61 "'--4
x
1
1
0
PLCD6 5 and BI
x
1
1
1
--
X: Don't care
BI: 7 Segment DecoderPLA Blank Input
The data of bo, olthe internal4-bit bus is written to 5 of PLCD6, and that of b3 to
BI.
32
COMMON
COMMON (Pin 32)
COMMON output terminal. This output signal is connected tothe common electrode
of static type LCD. The frequency of the COMMON signal output is given with the
following equation:
f(COM) = f(OSC)/217
Where the basic clock f(OSC) is 4.19304 MHz, f(COM) becomes 32 Hz (duty ratio:
50%).
MASK OPTION TABLE
f(ose) ~4.194304MHz
PortKO
PortK2
PortK3
Com mom
No.
28pin
30pin
31 pin
32pin
0
K,
K2
K,
32Hz
12bit
1
K,
BUZZER
COMMON
32Hz
12bit
Timer
2
K,
BUZZER
K,
32Hz
12bit
3
K,
BUZZER
K,
64Hz
11 bit
4
K,
K,
K,
64Hz
11 bil
5
Ko
K,
K,
128Hz
10bit
6
K,
BUZZER
K,
128Hz
10bit
7
K,
K,
K,
256Hz
9bit
8
K,
K2
K,
512Hz
8bit
9
K,
BUZZER
K,
512Hz
8bit
f (BUZZER)~2048Hz
68
- - - - - - - - - - - - - - - - - - - - - - - - - . MSM58421 •
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Power Supply Voltage
Voo
Input Voltage
VI
Ta=25°C
Po
Ta = 25°C per 1 package
Limits
Unit
-0.3 to 7
V
-0.3toVOO
V
200
mW
-55to+150
°C
Conditions
Limits
Unit
VOO
I(OSC) = 0 to 4.2 MHz
4t06
V
TOp
-
-40 to +S5
°C
MOSLoad
15
TTL Load
1
Power Dissipation
Storage Temperature
Conditions
. Ta=25°C
Tstg
OPERATING RANGE
Parameter
Symbol
Power Supply Voltage
Operating Temperature
Fan Out (excluding COM, SEC)
N
-
D.C. CHARACTERISTICS
(Voo = 5V±1 0%, Ta
= -40 to +85°C)
Parameter
Symbol
"H" Input Voltage
VIH
"L" Input Voltage
VIL
Conditions
Min.
Typ.
Max.
3.6
Unit
V
O.S
V
"H" Output Voltage( 1)
VOH
10=-SOf.LA
VOO
-0.1
V
"H" Output Voltage(2)
VOH
10=-2Of.LA
VOO
-0.1
V
"H" Output Voltage(3)
VOH
10=-4Of.LA
4.2
V
4.2
"H" Output Voltage(4)
V
VOH
10=-15f.LA
"L" Output Voltage (1 )
VOL
10=SOf.LA
0.1
V
"L" Output Voltage(2)
VOL
10 = 20f.LA
0.1
V
VOL
10=1.6mA
0.4
V
101-10
f.LA
1/-20
f.LA
"L" Output Voltage(5)
OSCo Input Leak Current
IIH/IIL
VI =VOOIVI =OV
Input Current(6)
IIH/IIL
VI =VOOIVI =OV
PA
"H"
PB
Output Current
10H
VO=0.4V
"H" Output Current(3)
10H
VO=2.5V
-0.25
10L
VO=0.4V
1.6
"L" Output Current(4)
Input Capacity
Output Capacity
Current Consumption
-1
rnA
rnA
rnA
CI
1=1 MHz, Ta=25°C
5
pF
Co
1=1 MHz, Ta=25°C
7
pF
100
1.= 4.194304 MHz,
at no load
2
5
rnA
Notes: (1) Applied to COMMON
(2) Applied to SEGMENT
(3) Applied to SYNC
(4) Applied to PA, PB
(5) Applied to SYNC, PA, and PB
(6) Applied to RESET, PK, and PH
69
• MSM58421 .---------------------------------------------------
SWITCHING CHARACTERISTIC
(Voo
=
5V±1 0%, Ta
=
-40° to +85°C)
Parameter
SYNC Delay Time from
Clock (OSCo)
Clock (OSCo) Pulse
Width
Symbol
t¢d
Conditions
Min.
Typ.
CL =50pF
IcpWH
tcf>WL
Max.
Unit
800
ns
115
ns
Cycle Time
tCY
(1 )
,",s
SYNC Pulse Width
tsw
(2)
,",S
PA
PB Data Valid Time
PK
tDV
CL =50pF
(3)
,",S
PA
PB Data Invalid Time
PK
tDiV
CL =50pF
Data Delay Time
tDDS
CL =50pF
Port H Set Pulse Width(?)
tHW
COMMON Delay Time
from SYNC
tSCd
CL =50pF
SEGMENT Delay Time
from COMMON
tCSd
CL =50pF
(4)
500
ns
500
ns
tCPWL
CLOCK (OSCo)
SYNC
70
,",S
2
,",$
1
,",S
- - - - - - - - - - - - - - - - , - - - - - - - - - - - - . MSM58421 •
~--~~------_tCY~(l~)----------~
SYNC
(4)
t------tD IV-----+-(6)
PA, PB,PK
IN VALID
INPUT MODE - - -_ _ _
IN VALID
+-_____-..J
PA,PB
OUTPUT
MODE
~
___
_J)(~:!·:~~~~~~~~O~L_~_D_:_:_:5_~_-_-_-_-_-_-_-_-_-~~~~~~-N-E-W-D-A-T-A-
tT
.I.[L
PH
_____. . .T-\ :
T"""STRUeT.O" CYCLE
SYNC
'~
.1.
16xl/f(OSC)
TINH
15xl/f(OSC)
1 xl /f(OSC)
Notes: (1 )lCV = 32 x l/f(OSC)
(2) tsw = 4 x l/f(OSC)
(3) tDV = 8 x l/f(OSC)
x 1If(OSC) + 0.5 "'s
(5) tDDS = 26 x l/f(OSC) + 1 P.s
(6) When data is input from PA or PB, set the contents of PA or PB to"1" prior to reading instruction.
(4) tDIV = 16
(7) At execution ofthe THB instruction, any input made during a period ofTlNH (15
x 1If(OSC» shownin the
above figure may be neglected.
SYNC
tscd
COMMON
tcsd
SEGMENT ____________~
tcsd
r------------~
(WHEN THE DISPLAY - - - - - - - - - - - - - CONTENT IS FIXED)
71
• MSM58421 . ' - - - - - - - - - - - - - - - - - - - - - - - - - -
DESCRIPTION OF TERMINALS
GND (Pin 33)
Circuit grounding potential
VDD (Pin 23)
Main power supply
OSCo (Pin 11)
Input of internal oscillation circuit at one side
of crystal resonator and ceramic vibrator.
OSC 1 (Pin 16)
Output of internal oscillation circuit at the
other side of crystal resonator and ceramic vibrator (not TTL compatible)
PA, PB (Pins 19 ......, 22 and 24 - 27)
These are quasi-bidirectional ports for 4-bit
parallel 110. To input data from these ports, it is
necessary to write "1" to them beforehand.
When nothing is applied to their terminals, the
content of output ports is written in them, so they
can also be used as registers. In addition, it is
possible to use them to make an 8-bit parallel
output depending on instructions.
PK (Pins 28 - 31)
Input ports for 4-bit parallel input with no
latching function.
PH (Pin 14)
Input port with latching function to be set by
negative logical signal.
This terminal is set at the time when the negative logical signal is applied to it from the outside.
It is reset automatically after execution of the
test instruction of this port.
RESET (Pin 18)
Reset must be active for greater than 1 machine cycle.
The RESET signal, when input, has priority
over all of other Signals and performs the following functions:
(1) Resets all bits of the program counter;
(2) Resets the timer counter and timer flag;
(3) Resets the port pointer;
(4) Resets the accumulator;
(5) Resets I/O ports PA and PB;
(6) Resets the input port PH flag;
(7) Initializes the output port PLCD for LCD; and
(8) Resets the machine cycle to M 1.
72
Since the RESET terminal is pulled up to VDD
by an internal resistor (approx. 800k!l), it is
possible to activate power ON/reset by connecting it to an external capacitor.
SYNC (Pin 15)
This is a general-purpose synchronizing
signal output. The signal is output at the beginning of each machine cycle. Output constantly,
this Signal is used also as clock pulse to external
units.
The cycle of SYNC becomes 32 times that of
the original oscillation (8ILs when the Clock pulse
is4MHz).
PLCD 1 -6 (Pins 1 -13and 34 -60)
These are 7 -bit and 5-bit parallel output
ports, respectively. They are used to directly
drive an LCD (static type). SpeCification of each
port is done by the port pointer (PP) as shown in
the table below;
b3
Content of PP
b,
b2
bo
Port Specified
x
0
0
0
PLCDl
x
0
0
1
PLCD2
x
0
1
0
PLCD3
x
0
1
1
PLCD4
x
1
0
0
PLCD5
x
1
0
1
PLCD6-4
x
1
1
0
PLCD6 5 and BI
x
1
1
1
-
X: Don't Care
BI: 7 Segment Decoder PLA Blank Input
The data of bo, of the internal 4-bit bus is written to
5 of PLCD6, and that of b3 to BI.
COMMON (Pin 32)
This is a COMMON output terminal. This
output signal is connected to the common electrode of static type LCD. The frequency of the
COMMON signal output is given with the following equation:
f(COM)
=
f(OSC)/217
Where the basic clock f(OSC) is 4.19304 MHz,
f(COM) becomes 32 Hz (duty ratio: 50%).
- - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ e MSM.58421 e
INSTRUCTIONS LIST
Mnemonic
CLA
CLL
CLH
LAI
LLI
LHI
L
LAL
LLA
LAW
SI
LWA
LPA
LTI
Description
INA
INL
INM
INW
DCA
DCL
DCM
CAO
RAL
AC
AS
AIS
DAS
CM
5MB
RMB
TAB
TMB
THB
TTM
TC
SC
RC
J
Clear Accumulator
ClearDPL
ClearDPH
Load Accumulator with Immediate
Load DPL with Immediate
Load DPH with Immediate
Load Accumulator with Memory
Load Accumulator with DPL
Load DPL with Accumulator
Load Accumulator with W Register
Store Accumulator to Memory then Increment DPL
Load W Register with Accumulator
Load Port Pointer with Accumulator
Load Timerwith Immediate "0" (ClearTimer& TMF)
Exchange Accumulatorwith Memory
Increment Accumulator
Increment DPL
Increment Memory
Increment W Register
Decrement Accumulator
Decrement DPL
Decrement Memory
Complement Accumulator of One
Rotate Accumulator Left through Carry
Add Memory to Accumulator with Carry
Add Memory to Accumulator, Skip if Carry
Add Immediate to Accumulator, Skip if Carry
Decimal adjust Accumulator in Subtraction
Compare Accumulator with Memory
Set Memory Bit
Reset Memory Bit
Test Accoumulator Bit
Test Memory Bit
Test H Port Bit
TestTimeflag
Test Carry flag
Set Carry flag
Reset Carry flag
Jump
JC
JA
CAL
Jump in Current Page
Jump with Accumulator
Call Subroutine
X
RT
OTD
OA
OB
OP
OPM
IA
IB
IK
NOP
Return from Subroutine
Output Table Data
Output Accumulator to Port A
Output Accumulator to Port B
Output Accumulator to Port deSignated Port Pointer
Output Memory to Port P designated Port Pointer
Input PortA in Accumulator
Input Port B in Accumulator
Input Port K in Accumulator
No Operation
7
0
0
0
0
0
0
1
0
0
1
1
1
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
17
1
0
0
17
0
0
0
0
0
0
0
0
0
0
Instruction Code
5 4 3 2 1
0 0 1 0 0 0
0 1 0 0 0 0
1 1 0 0 0 0
0 0 1 Is I, 11
0 1 0 13 i2 11
1 1 0 0 10 11
0 0 1 0 1 0
1 0 1 0 1 0
1 0 1 0 1 0
0 0 0 0 1 0
0 0 1 0 0 0
0 0 0 0 0 0
1 0 1 1 0 0
1 1 0 1 0 0
0 0 1 1 0 0
0 0 0 0 0 0
1 0 1 0 1 1
1 0 1 1 1 0
0 0 0 1 0 0
0 0 0 1 1 1
1 0 1 0 1 1
1 0 1 1 1 0
1 0 1 0 0 0
1 0 0 0 1 1
1 0 0 1 1 0
1 0 0 1 1 1
0 0 0 13 I, 11
1 0 1 1 0 1
1 0 1 1 1 1
0 1 1 1 0 11
0 1 1 1 1 11
0 1 0 0 0 11
0 1 0 0 1 11
0 1 0 1 1 0
0 1 0 1 1 1
1 0 0 0 0 1
1 0 0 0 0 0
1 0 0 0 0 0
0 1 1 0 110 19
I. 15 I. Is i2 11
1 15 I. Is I, 11
1 0 0 0 0 1
0 1 1 1 1,0 19
I. 15 I. Is I, 11
1 0 1 1 0 0
1 1 1 0 0 0
1 1 1 0 0 1
1 1 1 0 0 1
1 1 1 0 1 0
1 1 1 0 1 1
1 1 1 1 0 1
1 1 1 1 0 1
1 1 1 1 1 0
0 0 0 0 0 0
6
0
0
0
0
10
10
10
0
Byte
Cycle
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
2
2
1
1
1
1 1
1
0
0
0
1
0
15
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
1
0
0
0
1
0
0
10
0
0
10
10
10
10
0
0
0
0
1
e
10
10
1
e
10
0
2
73
• MSM58421 .~------------------------------------------------
TYPICAL PERFORMANCE CURVES
Output Current (lOH) TYP
OuJput Current (lOL) TYP
(VOO
= 5V, Ta = 25°C)
-1 0
20r--'--~----~~(C-O-M-M-rO-N-t-er-m~in-a~l)~
.~
.~ 400
400
200
o
10
-
20
50
:rr
100
200
Load capacity CL (pF)
74
VOO=51
E
::I:soo
t-.
~.
/
SOO
0;
...J
.~
...
"
S0"
10
7
5
Output voltage Vo (V)
500 1000
...
"
S0"
/
--
200
o
10
20
/
j ..../ V
50
100
200
Load capacity CL (pF)
500 1000
-------------------------------------------------4eMSM58421 e
f(OSC) - Ta Characteristic TYP
f(OSC) - VDD Characteristic TYP
(CL = 15pF)
(CL = 15pF, Ta = 25°C)
12
/
I
'N
:I:
~
10
U
en
J.>
.
u
8
"cr
!
6
/
U
0
u
E
"
E
'N
:I:
~
4
J.>
."
u
/
~V
..........
8
"""""
cr
!
.J<
6
U
0
u
E
"E
"x
'"
:::i:
'"
:::i:
o
~
I:
"x
o
10
U
en
J
I:
.J<
12
7
5
3
Power supply voltage VOO (V)
o
10
IDD - VDD Characteristic TYP
4
-50
o
50
Ambient temperature Ta (OC)
iDD - f(OSC) Characteristic TYP
(CL = 15pF, Ta = 25°C)
(CL = 15pF, Ta = 25°C)
..~~~
10m
1m
100
10m~-------,---------.--------_,
~
\~
0
0
1m
I:
0
.~
E
a
~
I:
g 1001l
8
E
1001l
I!!
;;
()
7
/
1OIL
10K
0
/
/
5
3
Power supply voltage
100K
1M
10M
Clock frequency f(OSC) (Hz)
7
10
Voo (V)
75
OKI
semiconductor
MSM58422
CMOS 4-BIT SINGLE CHIP MICROCONTROLLER WITH FLT DRIVER
GENERAL DESCRIPTION
OKI's MSM58422 is a low-power, high-performance 4-bit single-chip microcontroller implemented in complementary metal oxide semiconductor technology.
Integrated within the one chip is a mask ROM of 1536 x 8 bits, RAM of 40 x 4 bits, 10 input/output ports 11-bit timer-counter, clock oscillator, 4-bit parallel arithmetic circuit, 40 static FLT drivers
etc.
MSM58422 has an instruction set which consists of 4-bit arithmetic instructions, Boolean (bit)
manipulation instructions (bit-set, bit-reset, bit-test), data input/output instructions, and 8-bit code
translation (Table data out) instructions.
Also the pseudo-bilateral ports are used for connection to the buses of other 8-bit systems.
FEATURES
•
•
•
•
•
•
•
Low Power Consumption CMOS 4-bit
One-Chip Microcomputer
1 00% Static Logic
1536 x 8 bits MASK ROM
8-bit Interface Bus
1 Stack Register
52 Instructions
+5V Single Power Supply
• 60-Pin Flat Package
• Built-in 11-bit Timer
• 94% of the 52 Instructions and 1 Byte and 1
Machine Cycle
• Integrated with 10 Input/Output Ports and 40
Static FLT Driver Circuit
• PK and PH Input contain S9hmidt Trigger
Circuits
FUNCTIONAL BLOCK DIAGRAIVI
FED
C
o
5 4 3 2 1 gledcba
PFl T6
PFTL5
PFl T4
PFTl3
PFlT2
PFTL 1
B PK
U
Z
Z
E
R
PH
3
2
PA
SROO
1 0
PB
VG
YESSDN
NSCC 00
CE 1 0
T
OSC 4,194304 MHz. SYNC = 7.63 f.Lsec
76
- - - - - - - - - - - - - - - - - - - - - - - . MSM58422 •
PIN CONFIGURATION
LOGIC SYMBOL
44 Pin Flat Package
_.c.cca
~~~~
~~~~
a. a. a. a.
(----:..0 csc,
OSCJ
X'ial
PFLT 5-c
PFlT3-a
1
2
PFLT3-b
PFLT5-d
PFLT2-f
PFLT2-a
PFLT5--e
PFLT 2-b
PFLT1-f
PFLTS-f
PFLT1-a
PFLT1-b
PFLT5-g
PFLTPH
45
PFLT 3-e
PFLT 3-d
PORTA
B· ,
PORTS
SYNC
TEST
H,
PORTH
4
9
PFLT l-e
1
PFLT1-d
PFLT l-c
PFLT1-g
4
PFLTS-l
PFLTt a-9
PFlT2a-g
PORTK
PFLT 2-c
PFLT2-g
PFLTSVNC
PFLTOSC,
SYNC
'0'
DIM,
DIM?
DIM (
BUZZER
PFLT3a-g
PFlT4a-g
BUZZER
64Hz
64Hz
5V
DV
VDD
PFLT5a-g
PFLT61-5
1
ABSOLUTE MAXIMUM RATING
Symbol
Conditions
Limits
Voo
Ta =25°C
-0.3 -7
V
Input Voltage
VI
Ta =25°C
-0.3 -VOO
V
Output Voltage (FLT)
Vo
Ta =25°C
VOO -30
V
Power Oissipation
Po
Ta = 25°C per 1 package
200
Ta = 25°C per 1 FLT
8
-
-55 -+125
°C
Symbol
Condition
Limits
Unit
Supply Voltage
VOO
HOSC) = 0 to 4.2 MHz
4-6
V
Operating Temperature
TOp
-
-40 -+85
°C
Vo
-
VOO -26
V
MOSLoad
15
TTL Load
1
Parameter
Supply Voltage
Storage Temperature
Tstg
Unit
mW
OPERATING CONDITIONS
Parameter
Output Voltage (FLT)
Fan Out (excluding FLTs)
N
-
77
eMSM58422
e--------------------------------------------------
DC CHARACTERISTICS
(Voo = 5V±1 0%, Ta = -40 - +85°C)
\
Parameter
"H" Input Voltage
Symbol
Conditions
Typ.
Max.
3.6
VIH
"L" Input Voltage
Min.
Unit
V
0.8
VIL
V
"H" Output Voltage (1)
VOH
10=-15/LA
4.2
V
"H" Output Voltage (2)
VOH
10 =-40/LA
4.2
V
"L" Output Voltage (3)
VOL
10 = 1.6 mA
0.4
V
/LA
OSCo Input Leak Current
IIH/IIL
VI =VOO/OV
101-10
Input Current (4)
IIH/IIL
VI =VOO/OV
1/-20
/LA
"H" Output Current (1)
10H
Vo =0..4 V
-1
mA
"H" Output Current (5)
10H
Vo =2.5 V
-0.25
mA
mA
mA
"H" Output Current (6)
10H
Vo =3V
-1
"L" Output Current (3)
10L
VO=O.4V
1.6
FLT Output Leak Current
ILO
VO=VOO-26V
Input Capacity
CI
f = 1 MHz, Ta = 25°C
5
pF
Output Capacity
Co
f = 1 MHz, Ta = 25°C
7
pF
Current Consumption
IOD
f = 4.2 MHz at no load
2
Notes: (1)
(2)
(3)
(4)
(5)
(6)
78
Applied
Applied
Applied
Applied
Applied
Applied
to PA, PB
to SYNC, BUZZER, 64 Hz and PFTL
to PA, PB, SYNC, BUZZER and 64Hz
to PH, RESET, OIM and PK
to SYNC and 64Hz
to BUZZER and PFLT
-10
5
/LA
mA
- - - - - - - - - - - - - - - - - - - - - - - - - . MSM58422 •
SWITCHING CHARACTERISTICS
(VDD = 5V±1 0%, Ta = -40 - +85°C)
Parameter
SYNC Delay Time from
Clock (OSCe)
Symbol
Conditions
td
CL =50pF
Min.
Typ.
Max.
Unit
800
ns
tWH
tWL
115
ns
Cycle Time
TCY
(1 )
/Ls
SINC Pulse Width
tsw
(2)
/Ls
PA
PB Data Valid Time
PK
tDV
CL =50pF
(3)
/Ls
PA
PB Data Invalid Time
PK
tDV
CL =50pF
(4)
/Ls
Data Delay Time
tDDS
CL =50pF
(5)
ns
Port H Set Pulse Width (8)
tHW
64Hz Delay Time
from SYNC
tSFD
CL =50pF
2
/Ls
BUZZER Delay Time
from SYNC
tSBD
CL =50pF
2
/Ls
SEGMENT Delay Time
from SYNC
tSSD
CL =50pF (8)
2
/Ls
Clock (OSCe) Pulse Width
Notes: (1)
(2)
(3)
(4)
(5)
500
ns
tCY = 32 x 1/f(OSC)
tsw = 4 x 1/f(OSC)
tDV = 8 x 1/f(OSC)
tDIV = 16 x 1 If(OSC) + 0.5 /Ls
tDDS = 26 x 1/f(OSC) + 1 /Ls
CLOCK (OSCo)
SYNC
79
• MSM58422 • - - - - - - - - - - - - - - - - - - - - - - - - -
1---.,..-,._ _ _ _ tCy.:.;(1:.:.)_ _ _ _ _--I
SYNC
(4)
1---tDIV--oo+-(S)
PA,PB,PK
IN VALID
INPUT MODE _ _ _ _ _-1_ _ _ _ _ _-'
PA,PB
OUTPUT
MODE
IN VALID
VALID
'\._
_...J ' - - - - - - - - -
____~x ------O-L::::~ -----'---'OD-r*. .
,_N_E_W_D_A_T_A_
1-1
n
PH
Notes: (6) When data input from PA or PB, set the contents of PA or PB to "1" prior to reading instruction.
(7) Alteration by the instructions relative to output ports PFLT (it is in the case that the out.
puts of open drain are pulled down to GND by a resistor below 20 kOl.
______
~
THB 'NSTRUOT'ON CYCLE
SYNC
'~
lSxl/f(OSC)
.1.
TINH
15xl/f(OSC)
:1.:f"L
1 xl/f(OSC)
Notes: (8) At execution of the THB instruction, any input made during a period of TINH (15 x
1If(OSC) shown in the above figure may be neglected.
80
- - - - - - - - - - - - - - - - - - - - - - - - - . MSM58422 •
32 pulses
1024 pulses
32 pulses
--~
ISBD
ISFD
64Hz
~=-=------------ ---~-------------------------------------32 pulses
SYNElLfLJUUL _______ _
L
L
SEG
H
L
SEG
L
H
SEG
Notes: (9) The waveform shown above is in lighting up state, in the case that that open-drain output
of FLT driver is pulled down to GND by a resistor below 20 k!1.
DIM 1 and DIM2 inputs must be in the state specified above.
81
eMSM58422e-----------------------------------------------DESCRIPTION OF TERMINALS
GND (Pin 33)
Circuit grounding potential
VDD (Pin 23)
Main power supply
OSC 0 (Pin 17)
Input of the internal oscillation circuit at one
side of the crystal resonator and ceramic
vibrator.
.
OSC , (Pin 16)
Output of the internal oscillation circuit at the
other side of the crystal resonator and ceramic
vibrator (not TTL compatible)
PA, PB (Pins 19 - 22 and 24 - 27)
These are quasi-bidirectional ports for a 4-bit
parallel I/O. To input data from these ports, it is
necessary to write a "1" to them beforehand.
When nothing is applied to their terminals, the
content of the output ports is written into them,
so they can also be used as registers. In addition, it is possible to use them to make an 8-bit
parallel output depending on instructions.
PK (Pin 31)
1-bit input port with no latching function. Contains Schmidt a Schmidt Trigger Circuit.
PH (Pin 14)
Input port with latching function to be set by
negative logical signal.
This terminal is set at the time the negative
logical signal is applied to it from the outside. It is
reset automatically after execution of the test
instruction at this port.
RESET (Pin 18)
Reset must be active for greater than 1
machine cycle.
The RESET signal input has priority over all
of other signals and. performs the following
.
functions:
(1) Resets all bits of the program counter;
(2) Resets the .latches of I/O ports PA, PB and
output port PFL T6;
(3) Resets the timer flag (TMF);
(4) Resets the accumulator;
(5) Resets the skip F/F circuit;
(6) Resets the machine cycle to MI;
(7) Resets the output port PFLT5-1 to the data
of 7 Seg PLA address 0;
Since the RESET terminal is pulled up to VDD
by an internal resistor (approx. 800 kfl), it is
possible to activate power ON/reset by
connecting it to an external capacitor.
SYNC (Pin 15)
This is a general-purpose synchronizing
signal output. The Signal is output at the
beginning of each machine cycle. Output
constantly, this signal is used also as ;Q clock
pulse to external units.
One SYNC cycle is 32 times that of the
original oscillation (8 /1-s when the clock pulse is
4 MHz).
82
PFL T 1 - 6 (Pins 1 - 13 and 34 - 60)
These are 7 -bit and 5-bit parallel output
ports, respectively. They are used to directly
drive an FL T (static type). Specification of each
port is accomplished by the port pOinter (PP),
which is a 4-bit register and is set to the
contents of the accumulator by the LPA
instruction.
Latching data of each port is output through
the logical AND operation with the DIMA signal
(later described) and via buffer circuits. (When
the data in the latch is 1, DIMA is output. When it
is 0, the output is at high impedance.)
ContentofPP
Port Specified
b3
b2
b,
bo
x
0
0
0
PFLT1
x
0
0
1
PFLT2
x
0
1
0
PFLT3
x
0
1
1
PFLT4
x
1
0
0
PFLT5
x
1
0
1
PFLT6-1....,.4
x
1
1
0
PFLT6-5, BI and BZ
x
1
1
1
-
x : Don't care
BI: 7 Segment Decoder PLA Blank Input
BZ: Control Signal output forthe buzzer output
The inputs with the latching function of ports
PFLT1-5 are connected to the outputs of the 7
segment decoder PLA and that of PFLT6 directly
to the internal buses.
DIM1, DIM2 (Pins 28, 29)
Input terminals for the dimmer control of
output ports PFLT1-6.
DIM1
DIM2
DIMA
o
o
o
1/4 duty
1/8 duty
1/16 duty
1
1
o
1
1
1
BUZZER (Pin 30)
This terminal outputs the value of the logical
AND operation between latching bit 2 of output
port PFLT6 and the timer output (aS).
By externally connecting a resistor and a
transistor, this BUZZER output terminal is used
to control an alarm, buzzer etc.
64 Hz (Pin 32)
This is an output terminal, whose frequency
is 1/65536 of the OSCO. For example, when the
frequency of oscillator is 4.194304 MHz, the
frequency of the 64 Hz signal output is given 64
Hz.
. This olltput pulse is used for adjusting the
frequency. Its duty is 50%.
- - - - - - - - - - - - - - - - - - - - - - - - - . MSM58422 •
INSTRUCTIONS LIST
Mnemonic
Description
ClA
Cll
ClH
lAI
lLi
lHI
l
lAl
llA
lAW
SI
lWA
lPA
lTI
Clear Accumulator
ClearDPl
ClearDPH
load Accumulator with Immediate
load DPl with Immediate
load DPH with Immediate
load Accumulator with Memory
load Accumulator with DPl
load DPl with Accumulator
load Accumulator with W Register
Store Accumulator to Memory then Increment DPl
load W Register with Accumulator
load Port POinter with Accumulator
load Timer with Immediate "0" (Clear Timer & TMF)
X
INA
INl
INM
INW
DCA
DCl
DCM
CAO
RAl
AC
AS
AIS
DAS
CM
5MB
RMB
TAB
TMB
THB
TTM
TC
SC
RC
J
Exchange Accumulator with Memory
Increment Accumulator
Increment DPl
Increment Memory
IncrementW Register
Decrement Accumulator
Decrement DPl
Decrement Memory
Complement Accumulator 01 One
Rotate Accumulator left through Carry
Add Memory to Accumulator with Carry
Add Memory to Accumulator, Skip il Carry
Add Immediate to Accumulator, Skip if Carry
Decimal adjust Accumulator in Subtraction
Compare Accumulator with Memory
Set Memory Bit
Reset Memory Bit
Test Accoumulator Bit
Test Memory Bit
Test H Port Bit
TestTimellag
Test Carry flag
Set Carry flag
Reset Carry flag
j
Jump
JC
JA
CAL
Jump in Current Page
Jump with Accumulator
Cali Subroutine
RT
OTD
OA
OB
OP
OPM
IA
IB
IK
Return from Subroutine
Output Table Data
Output Accumulator to Port A
Output Accumulatorto Port B
Output Accumulator to Port deSignated Port Pointer
Output Memory to Port P designated Port Pointer
Input Port A in Accumulator
Input Port B in Accumulator
Input Port K in Accumulator
No Operation
0
0
0
0
0
0
0
0
0
Instruction Code
5 4 3 2 1
0 1 0 0 0
1 0 0 0 0
1 0 0 0 0
0 1 b 12 I,
1 0 b i2 I,
1 0 0 10
0 1 0 1 0
0 1 0 1 0
0 1 0 1 0
0 0 0 1 0
0 1 0 0 0
0 0 0 0 0
0 1 1 0 0
1 0 1 0 0
0 0 1 1 0 0
0 0 0 0 0 0
1 0 1 0 1 1
1 0 1 1 1 0
0 0 0 1 0 0
0 0 0 1 1 1
1 0 1 0 1 1
1 0 1 1 1 0
1 0 1 0 0 0
1 0 0 0 1 1
1 0 0 1 1 0
1 0 0 1 1 1
0 0 0 13 12 I,
1 0 1 1 0 1
1 0 1 1 1 1
0 1 1 1 0
0 1 1 1 1 I,
0 1 0 0 0
0 1 0 0 1 I,
0 1 0 1 1 0
0 1 0 1 1 1
1 0 0 0 0 1
1 0 0 0 0 0
1 0 0 0 0 0
0 1 1 0 1'0 I.
I. Is I. b i2
1 Is I. b i2 I,
1 0 0 0 0 1
0 1 1 1 110 I.
I. Is I. b 12 I,
1 0 1 1 0 0
1 1 1 0 0 0
1 1 1 0 0 1
1 1 1 0 0 1
1 1 1 0 1 0
1 1 1 0 1 1
1 1 1 1 0 1
1 1 1 1 0 1
1 1 1 1 1 0
0
0
7
0
0
0
0
0
0
1
0
0
1
1
1
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
17
1
0
0
17
NOP
6
0
0
1
0
0
1
0
1
1
0
0
0
1
1
"
"
"
"
0
0
0
0
0
0
0
0
0
10
10
10
0
1
0
0
0
0
0
0
0
1
1
1
0
1
0
0
0
1
0
0
10
0
0
10
10
10
10
0
0
0
0
1
•
10
10
1
•
Byte
Cycle
1
1.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
2
10
1
1
1 1-15
0
1
1
1
1
0
1
0
1
0
1
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
2
1
1
1
1
1
1
, 1
1
83
OKI
semiconductor
MSM5847
CMOS 4 BIT SINGLE CHIP MICROCONTROLLER WITH LCD DRIVER
GENERAL DESCRIPTION
OKI's MSM5847 microcontroller is a low-power, high performance single-chip device implemented in complementary metal oxide semiconductor technology. Integrated onto single chip are 1536 x
8 bits of mask program ROM, 96 x 4 bits of data RAM, 7 input/output lines, 1 output line, a timer, LCD
Driver and oscillator. Program memory is byte wide and data paths are organized in 4 bit nibbles. RAM
is bit addressable. 43 instructions include binary, logical operations; bit set, reset, test; multifunctional instruction (increment, skip); subroutine call and return. 95% of instructions are single byte, single
cycle operations.
FEATURES
• Low Power Consumption 50 ,,"A Typical
• 1 .5K x 8 Internal ROM
• 96 x 4 Internal RAM
• 7 I/O lines, 1 output line including 8 bit data
bus
• 1 3 bit Timer
• Self-contained Oscillator'
•
•
•
•
•
•
•
43 Instructions
2 Stack Levels
-20° to +70°C Operating Temperature
3 V Operating VDD
61 O,,"s Cycle Time @32.768 kHz
44 pin Flat Package
Chip Form
FUNCTIONAL BLOCK. DIAGRAM
PROGRAM
MEMORY
DATA MEMORY (RAM)
(MASK
ROM)
16x6x4bit
W
F E
LCD DRIVER
Timing
1/3 dutyl/3 bias
Control
222018161412109876543210
23211917 lS 13 11
321
\........J
Common
Segment
84
34 B
3 2 1 0
32 1 0
Hz U
Z
Z
E
R
SROOVG
'----i
'----I
PA
PB
YESSDN
NSCCDD
CE01
T
-----------------------------------------------------eMSM5847e
PIN CONFIGURATION
LOGIC SYMBOL
44 Pin Flat Package
oseo
/
.;J; J;. 32.768kHz
osc,
}ortA
'RESET
RESET
}ortB
J
SEGMENTD
SegmentD
seg~ent23
23
34 Hz
34 Hz Output
BUZZER
Buzzer Output
Synchronized
Signal
SYNC
+3V
VDO
DV
GNO
Segment 22
Segment 21
Segment 20
Segment 19
Segment18
Segment17
Segment16
Segment 15
Segment 14
Segment 13
Segment 12
PBo
PB,
PB,
PB3
SegmentO
Segment 1
Segment 2
Segment 3
Segment 4
Segment 5
Segment 6
Common 1
Common 2
Common 3
COMMON 1
COMMON 2
COMMON3
ABSOLUTE MAXIMUM RATING
Parameter
Supply Voltage
Symbol
Conditions
Limits
Unit
-0.3 -7
V
-0.3 -VOO
V
-0.3 -VOO
V
-
-55 - +125
°C
Symbol
Condition
Limits
Unit
VOO
HOSC) = 32.768 kHz
2.7 -3.3
V
TOp
-
-20 - +70
DC
VDD
Input Voltage
VI
Output Voltage
Vo
Storage Temperature
Tstg
Ta = 25 DC
OPERATING CONDITIONS
Parameter
Supply Voltage
Operating Temperature
85
e MSM5847e-------,..-------------------AC CHARACTERISTICS
(VDD = 3V±1 0%, Ta = -20 - +70°C)
Parameter
SYNC Delay Time
from Clock (OSCo)
Symbol
Condition
Min.
TYIil·
Max.
Unit
tet>
CL =50 pF
-
-
5
JLS
tet>WH
tet>WL
-
15
-
-
JLs
Cycle Time
tCY
-
Note (1)
-
-
JLs
SYNC Pulse Width
tsw
-
Note (2)
-
-
JLs
PA, PB Data Valid Time
tDV
-
Note (3)
-
-
JLs
PA, PB Data Invalid Time
tDIV
CL =50pF
-
-
Note (4)
JLs
Data Delay Time
tDDS
-
-
-
Note (5)
JLs
Clock (OSCo) Pulse Width
Note: (1) tCY =
(2) tsw =
(3) tDV =
(4) tDIV =
(5) tDDS =
20 x 1lf (OSC)
2 x 11f (OSC)
4 x 11f (OSC)
8 x 11f (OSC) + 20 JLS
1 7 x 11f (OSC) + 40 JLS
[
f(OSC)
tCY
tsw
tDV
tDIV
tDDS
=32.768kHZ]
=610JLs
= 61JLs
= 122JLs
= 264JLs
= 558.5JLs
tWH
CLOCK(OSCo)
tpD
SYNC
_%
tCY
"''----
tsw
SYNC
K
n
tDIV
PA,PB
Input mode
tDV
INVALID
VALID
INVALID
tDDS
PA,PB
Output mode
86
OLD DATA
NEW DATA
- - - - - - - - - - - - - - - - - - - - - - - - -... MSM5847.
DC CHARACTERISTICS
(Voo =3V±10%, Ta =-20 - +70°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
"H" Input Voltage
VIH
-
VOO
-0.2
-
-
V
"L" Input Voltage
VIL
-
-
-
0.3
V
Va
0
-
0.2
V
V,
113 VOO
-0.2
-
113 VOO
+0.2
V
2/3 VOO
-0.2
-
2/3 VOO
+0.2
V
VOO
-0.2
-
VOO
V
*1
Common, Segment
Output Voltage
V2
Applicable to
Common 1-3
Segment 0-23
V3
"H" Output Voltage
*2 *3 *4
VOH
10 = 1JLA
VOO
-0.2
-
-
V
"L" Output Voltage *2
VOL
10 = 1JLA
-
-
0.2
V
"L" Output Voltage *3 *4
VOL
10=1 mA
-
-
1.0
V
OSCo Input Current
IIH/IIL
VI=VOOIVI=OV
-
-
5/-5
JLA
RESET Input Current
IIH/IIL
VI=VOOIVI=OV
-
-
1/-15
JLA
Current Consumption
100
VOO=3V
f = 32.768kHz,
no load
-
50
100
JLA
Note: *1 Applicable to PAO-2, PBo-3, SYNC and 34 Hz
*2 Applicable to PA3
*3 Applicable to BUZZER
Level of Output Voltage for Common, Segment
,.....-...,------------V3
----V2
-----V,
L--~-----Vo
87
eMSM5847e'-------------------------------------------------i
,
TYP. Output Current (lOL) vs Output
Voltage (VOL) for Low-level State
TYP. Output Current (lOH) vs Output
Voltage (VOH) for High-level State
(Voo=3V, Ta=25°C)
10
-·1.8
9
-1.6
8
-1.4
-;;( -1.2 k
..s
::c -1.0
o
-
(VOO=3V, Ta=25°C)
-2.0
-0.8
7
34 Hz terminal
-;;(
'\
SYNC terminal
..s
6
..J
5
.9
r\
-0.2
o
A/
3
C6M
terminal \
SEG'~\ PA, PB terminal
-0.4
1/
4
~I\
-0.6
PA3 terminal
o 1 2 3
4
5
6
7
10-
IJ
2
I
BUZZER termi~al
PAa - 2, PBa - 3, SYNC term ina
~ ~ COM, SEG terminal
8
9
o
10
1
I I I I
2
3
4
5
TYP. Output Current (11, 12l vs
Output Voltage (V 1, V 2) for Middle
-level State
8
10
9
Supply Current (100) vs
Supply Voltage (Voo)
(Ta=25°C, No Load)
(Voo=3V, Ta=25°C)
10m
/
20
6 ·7
VOL (V)
VOH (V)
25
J
I
34 Hz ttminal
I
I
_ _ ~.
.-
5m
II
15
~
..:::
V1/
10
/
1m
Iv,/
I II COM, SEG terminal
5
0
/
-5
500/1
S
I
0
-10 / /
I il
-15
-20
-25
o
.9 100/1
f(OSC)
50/1
I
o Hz
./
I
./
10/1
1
2
3
4 5 6
V " V2 (V)
7
8
9
10
32.768 kHz
./
5/1
100 n
o
1
2
3
4
5
6
VOO (V)
88
7 \8
9
10
OlMS-SO/60 SERIES
OKI
semiconductor
MSM5052
CMOS 4 BIT SINGLE CHIP VERY LOW POWER MICROCONTROLLER WITH
TEMPERATURE DETECTION CIRCUIT AND LCD DRIVER
GENERAL DESCRIPTION
The OKI MSS5052 is a low-power and high-performance single-chip microcontroller employing
complementary metal oxide semiconductor technology.'lntegrated onto a single chip are a 4 bit ALU,
18K bits of mask programmable ROM, 248 bits of data RAM, crystal oscillator, voltage doubler, timer,
LCD driver, input port, output port and CR oscillator for temperature detection.
The MSM5052 is widely used in electronic products requiring low power operation, for example,
thermometer and clinical thermometer with a time piece.
FEATURES
•
•
•
•
•
•
•
Low Power Consumption 3 /LA Typical
1280 x 14 Internal ROM
62 x 4 Internal RAM
4 x 2 Input Port
5 Output Port
4 x 4 Key Matrix Input (K1-K4, M1-M4)
26 LCD Driver
(112 Duty, 112 Bias, 52 Segment)
•
•
•
•
•
•
42 Instructions
1.5 V Operating Voltage
32.768 kHz Crystal Oscillator
122.1 I1-s Instruction Cycle
-20 to 75°C Operating Temperature
61 pad die
FUNCTIONAL BLOCK DIAGRAM
Bo
A3-AO
Lo
~======~~~:~~~~=Jll~~]~~~~~
SEGMENT
OUT1
LATCH
and
DISPLAY
DRIVER
\
SEGMENT
OUT26
COMl
COM2
K,
I
K4
INSTRUC·
liON
DECODER
,
s,
s,
!!II!
TH R' C IN
I !!J I r
91
• MSM5052 .----------------------------------------------~~~
CHIP PAD LAYOUT
LOGIC SYMBOL
SECMENTOUT
OSCILLATION [
~
INPUT PORT [
'(S1~S4)
SEGMENT
OUT26
COM1
COM2
INPUT PORT [
(K1 ~K4)
OUTPUT PORT [ (Ml-M4)
OUTPUT PORT
RESET
POWER SOURCE [ _
Ml
M2
M3
M4
LD
--
OSC3
LCD DRIVER
OSC2
OSCl
J
VDD
OSCILLATION
CIRCUIT FOR
AC
TEMPERATURE
VCP
DETECTION
AC
VDD
VSS1
VSS2
VCP
VCM
BUZZER OUTPUT
VCM
-J
Sl
TEST
S2
S3
S4
CHIP SIZE 4.77
x
4.36 (mm)
PIN DESCRIPTION
Designation
92
Function
VDD
Circuit ground potential
VSS l
Power source (-l.S V)
VSS 2
Power source for LCD driver (-3.0 V)
This terminal is connected to VDD terminal through a 0.1 /-tF capacitor.
VCP, VCM
Booster capacitor connection terminals
VCP terminal is connected to VCM terminal through a 0.1 /-tF capacitor.
OSC1,OSC3
Input and output terminals of oscillator inverter,
32.768 kHz crystal is connected to these terminals.
Tl -TS
Terminals to test internal logic, Tl - T3 and TS are pulled down to VSS 1 •
T4 is output. Test pins must be normally open.
AC
Terminal to clear internal logic pulled down to VSS 1•
After power is turned on, the MSMSOS2 must be reset by this terminal.
BD
Buzzer output
TH,R,C,'IN
Terminal to CR oscillation circuit for temperature detection,
fundamental resistor, thermistor, capacitor connection terminal.
______________________________________________--e. MSM5052.
FUNCTIONAL DESCRIPTION
A block diagram of the MSM5052 is given on
page 91. Each block of logic will be briefly
discussed. For more information, please refer to
the MSM5052 user's manual.
Program ROM
The MSM5052 addresses up to 1.25 K
words of internal mask programmable ROM.
Each word consists 0.1 14 bits and all
instructions are one word. The instructions are
routed to a programmed logic array which
generates the signals necessary for control of
logic.
Data RAM
Data is organized in 4-bit nibbles. Internal
data RAM consists of 62 nibbles.
The RAM is addressed by page address and
column address. Normally page address is
specified with page register, but direct
addressing is available in Page O.
Column address is directly addressed by
operand of various instructions.
. ALU
The ALU performs 4-bit parallel operation on
RAM and ACC contents, or RAM contents and
an immediate digit. It sets or resets the flags (Z,
C) depending on the condition.
P.rogram Counter (PC)
The program counter is 11 bits wide and
specifies the address of the program ROM.
The PC is incremented by one every
execution of the instruction, and then specifies
the next instruction to be executed. However, the
contents of the PC are rewritten by the execution
of the Jump or Branch instruCtion.
There is no boundary in the ROM, so a Jump
or Branch instruction can be put anywhere in the
ROM.
Input Port (K1 - K4)
The input port (K1 - K4) is a 4 bit parallel
input port. Each pin of the port is pulled down to
VSS1 by an internal resistor, and the status of
the port is fetched by an input instruction.
Output Port (M1 - M4)
The output port (M1 - M4) is a 4 bit parallel
output port. This port consists of data latches
and buffers, and the contents of the data latches
are rewritten by an output instruction.
Output Port (LD)
The output port (LD) is single output port.
This terminal is used for loading of M1 to M4
data.
Display Function
The MSM5052 is provided with a segment
output terminal which can directly drive a 1/2
bias, 112 duty LCD and the common drive output
terminal COM1 and COM2.
The segment drive circuit consists of the
display data latch, multiplexer and driver. If the
data is sent to the display data latch with a
display instruction, the LCD drive waveform is
output to the segment drive output terminal.
Time Base
The time base for the CPU is provided by
connecting a 32.768 kHz crystal to the OSC1
and OSC3 pins. One machine cycle is 122.1 p.s.
A hardware divider up to 1 Hz is provided
enabling programs to implement a clock function
by counting signals between 16 and 1 Hz.
Temperature Detection Circuit
The temperature detection circuit is
composed of an external thermistor, a
fundamental resistor, a capacitor and a built-in
CR oscillation circuit.
Two types of temperature measurement
circuit, as shown below, are available,
Input/Output Port
Input Port (51 - 54)
The input port (S1 - S4) is a 4 bit parallel
input port. Each pin of the port is pulled down to
VSS1 by an internal resistor, and the status of
the port is fetched by an input instruction.
R
MSM5052
Thermometer
(R. TH series)
TH
R
MSM5052
Clinical
Thermometer
(R. TH parallel)
TH
93
• MSM5052 . - - - - - - - - - - - - - - - - - - - - - - - - - -
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Conditions
Limits
Unit
VOO-VSS,
Ta =25°C
-0.3 to +2.0
V
VOO - VSS 2
Ta =25 DC
-0.3 to +4.0
V
Input Voltage
VIN,
Ta =25 DC
VSS, -0.3 to +0.3
V
Storage Temperature
Tstg
-55 to 125
°c
Supply Voltage 1
Supply Voltage 2
OPERATING CONDITIONS
Parameter
Operating Voltage
Operating Temperature
Symbol
Limits
Unit
VOO-VSS,
1.25 to 1.65
V
Topr
-20to 75
DC
DC CHARACTERISTICS
(VOO =OV, VSS, = -1.55V, VSS2 = -3.OV, CI = 30kO, Ta = 25°C)
o
Limits
Parameter
Symbol
Condition
Power supply current 1
100,
Temperature sampling off
Power supply current 2
1002
Temperature sampling on
Oscillation start
voltage
Within 10 seconds
-VOSC VSS, terminal
IOH,
Output current 1
COM
Unit
VOH, =-0.2V
Min.
Typ.
Max.
-
3.0
-
/LA
-
100
-
/LA
1.45
-
-
V
-4
-
-
4/-4
-
-
10M,
YOM, =VSS, ± 0.2V
IOL,
VOL, =-2.8V
4
-
-
IOH2
VOH2=-0.2V
-0.4
-
-
IOL2
VOL2 =-2.8V
0.4
-
-
Output current 3
C.R.TH
IOH3
VOH3 =-0.4 V
-400
-
-
IOL3
VOL3 = -1.15V
400
-
-
Output current 4
IOH.
VOH. =-0.4V
-100
-
"-
IOL.
VOL. = -1.15V
10
-
-
IOH5
VOH5= -0.4V
-50
-
-500
4
-
-
Output current 2
SEGMENT
M1-M.
LO
Output current 5
SO
Input current
S1-S4
K1-K4
Oscillator built-in
capacitor
94
-
IOL5
VOL5 = -1.15V
IIH,
VIH, =OV
1
10
100
IlL,
VIL, = -1.55V
-
-
..,..0.2
-
25
-
CO
/LA
/LA
/LA
/LA
/LA
/LA
pF
------------------------~----------------------~. MSM5052·
MEASURING CIRCUIT
VCP
VCM
r---.:-.,....-!IN
C
C2
OSC3
+-.JVI1\rl R
OSCl
R
'--JW"v-ITH
TH
X-tal
Cl
Cl
C2,C3
C4
X-tal
R,TH
20pF
O.l,..F
3000pF
32.768 kHz
10KO
TYPICAL APPLICATION
LCD
TH
R
M,
HI } Alarm output
M. 1 - - - - LO
IN
M.
TH
R.
C
C2 0
32.768 kHz
C3
OSCl
(CO=25pF)
OSC3
VCP
MSM5052
LO
BO
VSS,
VOO
--'-
AC
*1
R, =33 kO
R.= 20 kO
TH
40BT-5
40KO ±1 0% at 25°C
B=3550±2%
C,=680pF
C.=5 -35pF
C3=0.1,..F
C.=O.l,..F
*1. Inner switch or pad on PCB
*2. Bonding option
1
2
Thermomet~~19n"gesecond sam lin
Thermomet~~ll 0second sam ling
4
W~~JP~t~~~ alarm
rJI~J~r~~~e alarm
5
Clock
3
95
eMSM5052
e----------------------------------------------------
DESCRIPTION OF INSTRUCTIONS
Instruction Code
Mnemonic
Operation
131211109 8
7
5 4 3 2
6
ADDACC,AP
0
0
0
0
0
P 0
ADD #D,AP
0
1
1 0
0
P
ADCAP
0
0
0
0
0
P 0
1 0
c:
SUB ACC, AP
0
0
0
0
1
P 0
1 0
~
SUB #D,AP
0
1
1 0
1
P
SBCAP
0
0
0
0
1
P 0
1 0
CMPACC,AP
0
0
0
0
1
P 1
1
CMP #D,AP
0
1 0
1
INCAP
0
1
0
(])
a.
0
1 0
1 0
AP -
A
AP-(AP) - D
1
A
AP - Decimal adjust
{(AP) + (ACC) + (C)l
0
A
AP - (AP) - (ACC)
A
AP -
1
A
AP - Decimal adjust
{(AP) - (ACC) - (C)l
1 0
A
(AP) -. (ACC)
D
()
:;
E
:5
~
1 0
1 P
0
D
P 0
0
0
1
(AP)
+ (ACC)
A
0
D
(AP) - D
A
(AP) - D
A
AP -(AP)
+1
DECAP
0
1
1 0
1 P 0
0
0
1
A
A
XORACC,AP
0
0
0
0
1
1
1
A
AP -
(AP)"V"(ACC)
XOR #D,AP
0
1
1
1
1
P
A
AP -
(AP)itD
BIT ACC, AP
0
0
0
0
0
P 1
1 0
A
(AP) V (ACC)
c:
BIT #D,AP
0
1 0
1 0
P
A
(AP)VD
~
BISACC, AP
0
0
0
P 0
1 0
A
AP -
(AP) V (ACC)
a.
BIS #D,AP
0
1 0
o '0
A
AP -
(AP) VD
iii
BICACC, AP
0
0
0
0
1 0
A
AP -
(AP) A(ACC)
BIC #D,AP
0
1 0
0
1 P
A
AP - (AP) AD
ASRAP
0
0
0
0
0
P 0
0
1
1
A
L..(C) 0 -
ASlAP
0
0
0
0
1 P 0
0
1
1
A
(C) -(AP)-O
0
P 0
D
1
D
<-
(AP) - 1
0
0
(])
...
0
:::
:c
rn
0
1
P
D
1 P 0
1
D
-------
0
0
0
0
Z-O
0
1 0
0
0
0
C-O
1 0
1
1 0
0
0
0
Z-O, C-O
1 0
1 0
1 0
0
0
0
0
Z-1
0
1 0
1 0 .0
1 0
0
0
0
C +-1
0
1 0
1 0
1
1
0
0
0
Z-1,C-1
0
0
ClZ
0
0
0
0
0
0
1 0
1 0
c:
ClC
0
0
0
0
0
0
1 0
~
...(])
a.
ClA
0
0
0
0
0
0
SEZ
0
0
0
0
SEC
0
0
0
SEA
0
0
0
0
0
(AP)::J
Cl
til
u:
MOVACC,AP
1
1
1
1 0
P 0
MOVACC,.AX
1
1
1
1 0
0
'lii
MOV#D,AP
0
1
1
1 0
P
~
MOVAP,ACC
1
1
1
1
MOVAX,ACC
1
1
1
1
CHGAP
1
1
1 0
0
P 0
CHGAX
1
1
1 0
0
0
lii
c:
~
0
96
1
X
D
P 0
1 0
0
0
0
0
0
0
0
X
0
0
X
0
0
A
AP -(ACC)
A
AX-(ACC)
A
AP-D
A
ACC -(AP)
A
ACC- (AX)
A
(ACC)~(AP)
A
(ACC)~(AX)
OKI
semiconductor
MSM5054
CMOS 4 BIT SINGLE CHIP VERY LOW POWER MICROCONTROLLER WITH
LCD DRIVER
GENERAL DESCRIPTION
The OKI MSM5054 is a low-power, high-performance single-chip microcontrolier employing
complementary metal oxide semiconductor technology. Integrated onto a single chip are 4-bit of ALU,
14K bits of mask programmable ROM, 248 bits of data RAM, crystal oscillator, voltage doubler, timer,
LCD driver, input port and output port.
The MSM5054 is widely used in electronic products requiring low power operation, for example,
Clocks, Timers and Games.
FEATURES
•
•
•
•
•
•
•
Low Power Consumption 3 ,."A Typical
1024 x 14 Internal ROM
62 x 4 Internal RAM
6 Input Port
4 Output Port'
4 x 4 Key Matrix Input (S,-S", M,-M4)
44 LCD Driver .
(1/2 Duty, 1/2 Bias, 88 Segment)
• 40 Instructions
• 1.5 V or 3 V Operating Voltage
(Masking Option)
• 32.768 kHz Crystal Oscillator
• 122.1 P.s Instruction Cycle
• -20 to 75°C Operating Temperature
• 74 pad die
FUNCTIONAL BLOCK DIAGRAM
80-----1
A3-AO
SEGMENT
LO
OUTl
S
SEGMENT
OUT44
COM,
COM 2
INSTRUC·
TION
DECODER
IIIIII
1111111
97
·MSM5054·------------------~--------~----------------------
LOGIC SYMBOL
CHIP PAD LAYOUT
COM1
SEGME;NT
OUT,
OSCILLATION [
N.C
VDD
XT
INPUT PORT [
(51 ..... 54)
INPUI~;~:2j
SEGMENT
OUT44
[
OUTPUT PORT [
(M,-M4)
RESET
M,
M,
M,
M4
AC
S,
S,
VEE
COM,
COM,
BD
LD
BUZZER
OUTPUT
LAMP OUTPUT
K,
K,
voo
_rn [
SOURCE
M,
VSS 1
32Hz
T,
T,
T,
T4
T,
VSS 2
VEE
VCP
VCM
M,
lTEST
M.
COM2
SEG1
SEGMENT OUTPUT
CHIP SIZE 4.68 x 4.23 (mm)
PIN DESCRIPTION
Designation
98
Function
VDD
Circuit ground potential
VSS,
Power source (-1 .S V)
VSS 2
Power source for LCD driver (-3.0 V)
This terminal is connected to VDD terminal through a 0.1 /LF capacitor.
VEE
Power source for internal logic (-1.S to -3.0 V)
This terminal is connected to VDD terminal through a 0.1/LF capacitor.
VCP, VCM
Booster capacitor connection terminals
VCP terminal is connected to VCM terminal through a 0.1 /LF capacitor.
XT,XT
Input and output terminals of oscillator inverter,
32.768 kHz crystal is connected to these terminals.
T,-T5
Terminals to test internal logic, T, - T3 and T5 are pulled down to VSS,.
T 4 is output. Test pins must be normally open.
AC
Terminal to clear internal logic pulled down to VSS,.
After power is turned on, the MSMSOS4 must be reset by this terminal.
BD
Buzzer output
LD
Lamp output
-----------------------------------------------------. MSM5054 •
FUNCTIONAL DESCRIPTION
A block diagram of the M8M5054 is given on
page 97. Each block of logic will be briefly
discussed. For more information, please refer to
the MSM5054 user's manual.
Program ROM
The MSM5054 addresses up to 1 K word of
internal mask programmable ROM. Each word
consists of 14 bits, and all instructions are one
word. The instructions are routed to a
programmed logic array which generates the
signals necessary for control of logic.
Data RAM
Data is organized in 4-bit nibbles. Internal
data RAM consists of 62 nibbles.
The. RAM is addressed by page address and
column address. Normally page address is
specified by the page register, but direct
addreSSing is available in Page O.
Column address is directly addressed by the
operand of various instructions.
ALU
The ALU performs 4-bit parallel operation of
RAM and ACC contents, or RAM contents and
an immediate digit. It sets or resets the flags (Z,
C) depending on the condition.
Program Counter (PC)
The program counter is 10 bits_ wide and
specifies the address of the program ROM.
The PC is incremented by one at every
execution of the instruction, and then specifies
the next instruction to be executed. However, the
contents of the PC are rewritten by the execution
of the Jump or Branch instruction.
There is no boundary in the ROM, so the
Jump or Branch instruction can be put anywhere
in the ROM.
Input/Output Port
Input Port (81 - 84)
The input port (81 - S4) is a 4-bit parallel
input port. Each pin of the port is pulled down to
VSS1 by an internal resistor, and the status of
the port is fetched by the SWITCH instruction.
Input Port (K1 - K4)
The input port (K1 - K2) is a 2-bit parallel
input port. Each pin of the port is pulled down to
VSS1 by an internal resistor, and the status of
the port is fetched by the KSWITCH instruction.
Output Port (M1 - M4)
The output port (M1 - M4) is a 4-bit parallel
output port. This port consists of data latches
and buffers, and the contents of the data latches
are rewritten by a matrix instruction.
Display Function
The MSM5054 is provided with a segment
output terminal which can directly drive a 1/2
bias, 112 duty LCD, and the common drive
output terminal COM1 and COM2. The segment
drive circuit consists of the display data latch,
multiplexer and driver. If the data is sent to the
display data latch with a display instruction, the
LCD drive waveform is output to the segment
drive output terminal.
Time Base
The time base of the CPU is provided by
connecting a 32.768 kHz crystal to the XT and
XT pins. One machine cycle is 122.1 '"S.
A hardware divider of up to 1 Hz is provided,
enabling programs to implement a clock function
by counting signals between 32 and 1 Hz.
99
·MSM5054.------------------------------------------------~
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Conditions
Limits
Unit
Supply Voltage 1
VOO -VSSl
Ta = 25°C
-0.3 to +2.0
V
Supply Voltage 2
VOO-VSS2
Ta = 25°C
-0.3 to +4.0
V
Supply Voltage 3
VOO-VEE
Ta = 25°C
. -0.3 to +4.0
V
Ta=:25°C
VSS 1-O.3 to +0.3
V
-55 to 125
°c
Input Voltage
VINl
Storage Temperature
Tstg
,
OPERATING CONDITIONS
Parameter
Operating Voltage
Operating Temperature
Symbol
Limits
Unit
VOO-VSSl
1.25 to 1.65
V
Topr
-20 to 75
°c
DC CHARACTERISTICS
(VOO =OV, VSS 1' VEE = -1.55V, VSS 2 = -3.0V, CI = 30kO, Ta = 25°C)
Limits
Parameter
Symbol
Condition
Unit
Min.
Power supply current
100
Oscillation start
voltage
. Within 5 seconds
-VOSC VSS 1terminal
-
Typ. Max.
-
3.0
-
/LA
1.45
-
-
V
-4
-
/LA
lOLl
VOL1=-2.8V
4
Output current 2
SEGMENT
IOH2
VOH2=-0.2V
-0.4
IOL2
VOL2=-2.8V
0.4
-
Output current 3
SO
IOH3
VOH3=-0.4V
-50
-
-500
IOL3
VOL3= -0.8V
VSS 1= -1.25V
VEE =-1.25V
VSS 2 =-2.4V
2.5
7.5
Output current 4
LO
IOH4
VOH4 = ,-0.55V
-21
-83
IOL4
VOL4 = -1.15V
VSS l = -1.25V
VEE=-2.4V
VSS 2 =-2.4V
1
-
Output current 5
Ml-M4
IOH5
VOH5=-0.5V
-100
-
-
IOL5
VOL5=-1.0V
1.5
-
7.5
Input current 1
Sl-S4
IIHl
VIHl =OV
1
10
50
IILl
VILl = -1.55V
-
-
-0.2
Input current 2
Kl,K2
IIH2
VIH2=OV
2.5
6
12
IIL2
VIL2 = -1.55V
-
-
-0.2
20
-
Output current 1
COM
Oscillator built-in
capacitor
100
IOHl
VOHl =-0.2V
IOMl
VOMl =VSS l ± 0.2V
CO
4/-4
-
-
/LA
/LA
/LA
J.lA
/LA
/LA
pF
---------------------------------------------------.4. MSM5054 •
MEASURING CIRCUIT
VCP
VCM
Xl'
XT '------"'r-
Ca
XTAL
0.1 j.tF
30pF
32.768kHz
TYPICAL APPLICATION
LCD
Lamp
SEGMENTS
COM 2
LD 1-----[
BD I----+--f
MSM5054
VSS11-----T-
XT
X-tal c::::::I
VDDI----~
(CD=20pF)
AC
VSS 2 VEE
5 - 35pF
0.1j.tF
1.5V
20mH
101
• MSM5054
.----------------~---------
DESCRIPTION OF INSTRUCTIONS
,
Instruction Code
Mnemonic
Operation
131211109 8
;;;
...
Q)
a.
0
1 0
0
P 0
1
1 0
0
P
D
0
0
1 P 0
1 0
ADD#D,AP
0
SUB ACC,AP
0
0
1
1 0
1
1 0
0
0
ADJUST N, AP
4
0
0
c:
5
6
0
ADDACC,AP
.2 SUB#D,AP
7
0
0
0
2
1 0
A
+ (ACC)
AP+-(AP) + D
A
AP +- (AP) - (ACC)
AP +- (AP)
A
0
D
A
AP+-(AP) - D
N+1
A
AP +- N adjust {(AP)}
1
A
(AP) - (ACC)
A
(AP)-D
1 P
P
3
0
CMP ACC, AP
0
0
0
0
1 P
E
CMP#D,AP
0
1 0
1
1 P
0
1
1 0
0
P 0
0
0
1
A
AP +- (AP)
0
1
1 0
1 P 0
0
0
1
A
A+- (AP)-1
1
1
1
A
AP +- (AP)Ir(ACC)
A
AP +- (AP)-'- FORMATAP
a.
'"
1/1
6
1/1
.&:
0
01:1
...
E
"0
0
C)
::>
D..
C)
1 0 0
digit
P
1 1 0 P
digit
0 0 0 0 0 0 0
0
1
Halt
INTMODEAP
1
1 0
1 0 P 0
1 0 0
A
AP --Interrupt mode
PAGEAO
1 1 0
1 1 0 0
1 0
1
A
Preg --(AO)
1 0 0 0
1 0
1
N
Preg --N'
0 P 1 0 0
1
A
AP - DIVIDER (8 Hz-1 Hz)
PAGEN
0 0
RATEAP
1 1 0
1,
RSTRATE
0 0 0
1 0 0
BACKUP
ON/OFF
0 0 0
1 0 0 0 0 0
NOP
0 0 0 0 0 0 0 0 0 0 0
0
1 0 0 0
1 0 0 0
1 b3 b2 0 0
0 0 0
DIVIDER (8 Hz-1 Hz) -- 0
Backup ON/OFF
No operation
103
OKI
semiconductor
MSM5055
CMOS 4 BIT SINGLE CHIP VERY LOW POWER MICROCONTROLLER WITH
LCD DRIVER
GENERAL DESCRIPTION
The OKI MSM5055 is a low-power, high-performance single-chip microcontroller employing
complementary metal oxide semiconductor technology. Integrated onto a single chip are 4 bits of
ALU, 25K bits of mask programmable ROM, 384 bits of data RAM, crystal oscillator, voltage doubler,
timer, LCD driver, input port, output port and interface circuit for voice LSI (MSM6212).
The MSM5055 is widely used in electronic products requiring low power operation, for example,
multi-functioned watches, voice synthesizer watches and games.
FEATURES
• Low Power Consumption 3,..A Typical
• 1792 x 14 Internal ROM
• 96 x 4 Internal RAM
• 4 x 2 Input Port
• 4 X 1 Output Port
• 4 X 4 Key Matrix Input (K1-K4, M1-M4)
• 60 LCD Driver
(112 Duty, 112 Bias, 120 Segment)
• 42 Instructions
• 1.5 V or 3 V Operating Voltage
(Masking Option)
• 32.768 kHz Crystal Oscillator
• 122.1,..S Instruction Cycle
• -20 to 75°C Operating Temperature
• 94 pad die
FUNCTIONAL BLOCK DIAGRAM
DATA RAM
-+
BD _ _ _
96 word x 4 bit
LD
SEGMENT
M1
oun
I
M4
\
LO
SEGMENT
OUT60
K1
COMl
\
K4
COM2
INsrRUCTION
DECODE
1792 word x 14 bit
j j j
Ij i
AC T1 T2 T3 T4 T5
104
________________________________________________-4. MSM5055 •
CHIP PAD LAYOUT
LOGIC SYMBOL
OSCILLATION (_________
INPUT PORT [
(81-84)
-
N
SEGMENT
DUn
~~
83
LCD DRIVER
S4
INPUT PORT [
(K1-K41
SEGMENT
OUT6D
COM1
COM2
-
LOAD
M'
M2
M3
M4
LO
RESET
AC
OUTPUT PORT [
(M1-M41
POWER SOURCE -
BO
XTOUT
AC'J
~~g1
VSS2
T
i3'2
VCP
VGM
T4
TS
[ ~VEE
-
BUZZER OUTPUT
LD
LAMP OUTPUT
~ 8D~8b-fULSE
RESET
J TEST
L -_ _---l
SEGM~NT
OUTPUT
CHIP SIZE 5.49 x 4.71 (mm)
PIN DESCRIPTION
Designation
Function
VDD
Circuit ground potential
VSS,
Power source (-1.S V)
VSS 2
Power source for LCD driver (-3.0 V)
This terminal is connected to VDD terminal through a 0.1 p,F capacitor.
VEE
Power source for internal logic (-1.S to -3.0 V)
This terminal is connected to VDD terminal through a 0.1 p,F capacitor.
VCP, VCM
Booster capacitor connection terminals
VCP terminal is connected to VCM terminal through a 0.1 p,F capacitor.
XT,XT
Input and output terminals of oscillator inverter,
32.768 kHz crystal is connected to these terminals.
T1 -TS
Terminals to test internal logic, T1 - T3 and TS are pulled down to VSS ,.
T4 is output. Test pins must be normally open.
AC
Terminal to clear internal logic pulled down to VSS ,.
After power is turned on, the MSMSOSS must be reset by this terminal.
BD
Buzzer output
LD
Lamp output
LO
Load data terminal of M1 to M4
AC2
Reset terminal for external circuit
XTOUT
Clock output for external circuit
105
• MSMSOSS·,-------------------------------------------------FUNCTIONAL DESCRIPTION
A block diagram of the MSM5055 is given on
page 104. Each block of logic will be briefly
discussed. For more information, please refer to
the MSM5055 user's manual.
Program ROM
The MSM5055 addresses up to 1 K word of
internal mask programmable ROM. Each word
consists of 14 bits, and all instructions are one
word. The instructions are routed toa
programmed logic array which generates the
signals necessary for control of logic.
Data RAM
Data is organized in 4-bit nibbles. Internal
data RAM consists of 62 nibbles.
The RAM is addressed by page address and
column address. Normally page address is
specified by the page register, but direct
addressing is available in Page o.
Column address is directly addressed by the
operand of various instructions.
ALU
The
ALU performs 4-bit parallel operation of
RAM and ACC contents, or RAM contents and
an immediate digit. It sets or resets the flags (Z,
C) depending on the condition.
Program Counter (PC)
The program counter is 10 bits wide and
specifies the address of the program ROM.
The PC is incremented by one at every
execution of the instruction, and then specifies
the next instruction to be executed. However, the
contents of the PC are rewritten by the execution
of the Jump or Branch instruction.
There is no boundary in the ROM, so the
Jump or Branch instruction can be put anywhere
inthe ROM.
106
Input/Output Port
Input Port (81 - 84)
The input port (S1 - S4) is a 4-bit parallel
input port. Each pin of the port is pulled down to
VSS1 by an internal resistor, and the status of
the port is fetched by the SWITCH instruction.
Input Port (K 1 - K4)
The input port (K1 - K2) is a 2-bit parallel
input port. Each pin of the port is pulled down to
VSS1 by an internal resistor, and the status of
the port is fetched by the KSWITCH instruction.
Output Port (M1 - M4)
The output port (M1 - M4) is a 4-bit parallel
output port. This port consists of data latches
and buffers, and the contents of the data latches
are rewritten by a matrix instruction.
Display Function
The MSM5055 is provided with a segment
output terminal which can directly drive a 1/2
bias; 112 duty LCD, and the common drive
output terminal COM1 and COM2. The segment
drive circuit consists of the display data latch,
multiplexer and driver. If the data is sent to the
display data latch with a display instruction, the
LCD drive waveform is output to the segment
drive output terminal.
Time Base
The time base of the CPU is provided by
connecting a 32.768 kHz crystal to the XT and
XT pins. One machine cycle is 122.1 ILs.
A hardware divider of up to 1 H;z is provided,
enabling programs to implement a clock function
by counting signals between 32 and 1 Hz.
--------------------------------~----~-------------. MSM5055 •
ABSOLUTE MAXIMUM RATINGS
. Parameter
Symbol
Conditions
Limits
Unit
Supply Voltage 1
VDD -VSS,
Ta = 25°C
-0.3 to +2.0
V
Supply Voltage 2
VDD - VSS 2
Ta = 25°C
-0.3 to +4.0
V
VDD -VEE
Ta = 25°C
-0.3 to +4.0
V
Input Voltage
VIN,
Ta = 25°C
VSS, -0.3 to +0.3
V
Storage Temperature
Tstg
-55 to 125
DC
Supply Voltage 3
OPERATING CONDITIONS
Parameter
Operating Voltage
Operating Temperature
Symbol
Limits
Unit
VDD-VSS,
1.25 to 1.65
V
Topr
-20 t6 75
°c
DC CHARACTERISTICS
(VDD =OV, VSS" VEE = -1.55V, VSS 2 = -3.0V, CI = 30kfl, Ta = 25 DC)
Limits
Parameter
Symbol
Conditions
Unit
Min.
Power supply current
IDD
Oscillation start
voltage
-VOSC Within 5 seconds
VSS, terminal
IOH,
VOH, =-0.2V
Output current 1
COM
10M,
VOM, =VSS,
IOl,
Output current 2
SEGMENT
Output current 3
AC2 lOAD, XTOUT
Typ. Max.
-
3.0
-
/LA
1.45
-
-
V
-4
-
-
4/-4
-
-
VOL, =-2.8V
4
-
-
IOH2
VOH2 =-0.2V
-0.4
-
-
IOl2
VOl 2 =-2.8V
0.4
-
-
IOH3
VOH3 =-0.5V
-10
-
-
IOl3
VOl 3 = -1.05V
10
-
IOH.
VOH.=-0.5V
-100
-
-
IOl.
VOL. =-1.0V
1.5
-
12.7
IOHs
VOHs = -0.55V
-21.6
-
':"83
tOls
VOl s =-1.15V
1
-
-
Output current 5
SD
IOHa
VOHa =-O.4V
-50
-
-
IOHa
VOla =-0.8V
-
5
.-
Input current 1
S,-S4
IIH,
VIH, =OV
1
10
50
Ill,
Vll,=-1.55V
-
-
-0.2
Input current 2
K,-K.
IIH2
VIH2=OV
2.5
6
~12
IIl2
VIl2 = -1.55V
-
-
-0.2
-
20
-
Output current 4
M1-M4
Output current 5
lD
Oscillator built-in
capacitor
CD
± 0.2V
Vss,=-1.25V
VEE =-2.4V
VSS 2 =-2.4V
VSS, =VEE
=-1.25V
VSS 2=-2.4V
/LA
/LA
/LA
/LA
/LA
/LA
/LA
/LA
pF
.107
e MSM5055ee-------------------------------------------------MEASURING CIRCUIT
VCP
VCM
C3
XT
XTAL
XT
C1 .C2.C3 0.1 J.tF
C4
30 pF
X-tal
32.768 kHz
TYPICAL APPLICATION
LCD
Lamp
COM 1
SI-L
S2
-L
S3 -L
S4
-L...
SI
S2
S3
S4
SEGMENTS
COM 2
LD
BD
MSM5055
VSS 1
XT
(CD=20pF)
C1
VDD
AC
r
5 - 35pF
0.1,uF
1.5V
20mH
108
________________________________________________--e.
MSM5055.
DESCRIPTION OF INSTRUCTIONS
Instruction Code
Mnemonic
Operation
131211109 8
ADD ACC,AP
c:
.2
iii
ADD#D,AP
0
SUB ACC,AP
0 0
SUB#D,AP
0
loa. ADJUSTN,AP
0
t)
CMPACC,AP
~ CMP#D,AP
E
:;; INCAP
~
c:
0
0 0
7 6
5 4 3 2 1 0
0 0 0 P 0 1 0 0
1 1 0 0
0 0
P
D
1 P 0
1 0
0
A
AP - (AP) + (ACC)
A
AP-(AP) +D
A
AP - (AP) - (ACC)
1 1 0
1 P
D
A
AP-(AP) -D
1 1 0 0
0 P
N+ 1
A
AP - N adjust {(AP)}
A
(AP) - (ACC)
A
(AP) -D
0 0
0 0
1 P 1 1
1 1 P
0
1 0
0
1 1 0 0
1 0
D
P 0 0 0
1
A
AP-(AP) + 1
DECAP
0 1 1 0 1 P 0 0 0
1
A
A-(AP) -1
XOR ACC, AP
0 0 0 0 0
1 1 1
A
AP -(AP) -V- (ACC)
XOR#D,AP
0
A
AP - (AP) -V- D
BITACC,AP
0 0 0
0 0
P 1 1 1 0
A
(AP) V (ACC)
BIT#D,AP
0
1 0
P
A
(AP)VD
A
APV (ACC)
~ BISACC,AP
lo·
a. BIS#D,AP
0
-
iii BICACC,AP
P 0
1 1 1 1 P
1 0
D
D
0 0 0 0 0 P 0
0
1 0
1 1 0
0 0 P
D
0 0 0 0
1 P 0
BIC#D,AP
0
1 P
;:
ASRAP
0 0 0 0 0 P 0 0
(f)
ASlAP
0 0 0 0
ClZ
0 0 0 0 0 0
ClC
0 0 0 0 0 0
0 0 0 0 0 0
1 0
1 1 0 0
0 0 0 0
1 0
1 0
1 0
SEC
0 0 0 0
1 0
1 0 0
SEA
0 0 0 0
1 0
1 0
MOVACC,AP
1
1 1
lo
U; MOVACC,AX
1
1 1 1 0
0 0
g
MOV#D,AP
0
1 1 1 0
P
S
MOVAP,ACC
1 1
MOVAX,ACC
1 1 1
JMP adrs
1 0
1 0
0
1 1 0
D
A
(AP)VD
A
AP A (ACC)
A
AP AD
1 1
A
C(C)
1 1
A
(C)-(AP)-O
1 0
1 0
0 0 0 0
1 0
0
.s::
c:
0
~
loa. ClA
0
SEZ
Cl
t1l
u::
c:
t1l
0
a. JMP@AP
..., JMPIO@AP
E
::l
BEQ
BZE
+n
+n
0
1
1 P 0
1 0
P 0
o a,o a9
1
1 0 0 0
0
0
0 0
O-(AP)::::J
z-o
C-O
Z-O,C-O
0 0 0 0
Z-l
1 0 0 0 0
C-1
1 0
Z-l,C-l
0 0 0
0 0 0
A
AP-(ACC)
X
A
AX-(ACC)
A
AP-D
0 0 0
A
ACC-(AP)
X
A
ACC-(AX)
D
1 1 P 0
1 1 0
0
as a 7 a 6 a 5 a. a 3 a 2 a, a o
PC -adrs
+1
0 0 0 0 P 1 1 0
1
A
PC - (PC) + (AP)
1 P 1 1 0
1
A
PC - (PC) + {(AP) A 7H} +1
0 0 0 0
0 0 0
1 1 0
0
1 0 n. n3 n 2 n, no
PC
+-
(PC)+n+1, ifZ=l
109
., • .MS.M5055 . - - - - - - - - - - - - - - - - - , . . . . - - - - - - ' - - -
DESCRIPTION OF INSTRUCTIONS (CONT.)
Instruction Code
Mnemonic
Operation
131211109 8
7 6 5
+n
+n
0 0 0
1 1 0
1 1 0 n 4, n3 n 2 n 1 no
PC +- (PC)+i1+1 , if Z=O
+n
0
1 1 0 0 0 0 n 4 n3 n 2 n 1 no
PC - (PC)+n+1, if C=l
+n
0 0 0
1 1 0
SWITCHAP
1 1 0
1 0 P 0 0 0
KSWITCHAP
1 1 0
1 0
MATRIXAP
1
BNE
a. BNZ
E
...,::s BCS
BCC
0 0
4 3
2
:1
0
1 0 0 n 4 n3 n 2 n 1 no
PC - (PC)+n+1, if C=O
1
A
P 0 0
1 0
A
AP -INPUT PORT (K1 - K4)
1 0
1 1 P 0 0
1 0
A
OUTPUT PORT (M1 ....;, M4)
-(AP)
MATRIXMn
0
:;::.
::s XTCPON/OFF
a.
0 0 0
1 0 0 0 0
1 0 M4M3M2M1
0 0 0
1 0 0
1 0 0 0
-=
FREON
0 0 0
1 0 0
1 1 0
1
BUZZER sound
0 0 .0 1 0 0
1 1 0
0 b3 b2 1 0
....::s
.s-::s
:>.
1\1
a.
rn
0 0 0
LAMP ON/OFF
0 0 0 1 0 0 0 0 0 1 0
DSP digit, AP
0 0
DSPHdigit, AP
0 0 1 0
XTOUT ON/OFF
b1 bo
Mreg - sound, Buzzer start
Buzzer stop
LDON/OFF
P
digit
A
Digit (Low part) - (AP) , (ACC)
digit
A
Digit (High part) ...;. (AP), (ACC)
1 1 0
FORMATN
0 0 0 1 0 0 0
1 1 P 0 0
1 ·1
b ,1
1
A
FMT reg. - (AP)
N
FMTreg.
-N
1 1 0 P
digit
A
Digit (Low part) - (AP)
via table
DSPFH digit, AP 0 0 1 1 1 P
digit
A
Digit (High part) - (AP)
via table
0 0
HALT
0 0 0
1 0 0 0
INTENAB
32/16
0 0 0
1 0 0
0
1 0 0 0
rn
(jj
.c ,INTMODEAP
(5
PAGEAO
oiS
.PAGE N -.
ADRSAP
,Q
:::> ADRSN
a.
0
110
OUTPUT PORT (M1 -M4)
- Mn (n=l, 2, 3, 4)
Freq -N
1 0 0 0 0 0 0
o
AP -INPUT PORT (S1 - S4)
1 P
1 0 0
FORMAT AP
INTDSAB
32/16
Q
1
0 b1 bo
N
BSO
Ci DSPF digit, AP
eC
1 CY 0
o
)
0 0
0 0
0 0 0 0 0
1 0
1 1 1 0 0 0
1 0
1 0 0 0 0
1' 1 0
1 0 0
Halt
Enable ti~er
;
0 0 0
1 0 0
0 0 0
1 0 0 0
1 0 0 0 0 0
1 0
1 0 0
A
AP -Interrupt mode
1
A
Preg -(AO)
0 0 0 1 0 0 0 1 0 1
N
Preg +-N
1\ 1 P 0
1 1 0
A
Areg -(AP)
1 1 0
N
Areg -N
1
A
AP - DIVIDER (8 Hz-1 Hz)
1
1 0
1 1 0
1
1
0
1 0
P 0
1 1 -0, 0
0 9 0 '1
0 0
0
1 0
RATEAP
1
1 0
1 0 P 1 0 0
RSTRATE
0
0 0
1 0 0 1
BACKUP
ON/OFF
0 0 0
NOP
0 0
1 0 0
0
0 0
1 0 0
1
0
Disable timer
DIVIDER (8 Hz---1 Hz)-O
0 0 0
1 b3 b2 0 0
Backup ON/OfF
0 0 0 0 0 0 0
0 0 0 0 0
No operation
OKI
semiconductor
MSM5056
CMOS 4BIT SINGLE CHIP VERY LOW POWER MICROCONTROLLER WITH
LCD DRIVER
GENERAL DESCRIPTION
The OKI MSM5056 is a low-power, high-performance single-chip microcontroller employing
complementary metal oxide semiconductor technology. Integrated onto a single chip are a 4-bit ALU,
25K bits of mask programmable ROM, 360 bits of data RAM, crystal oscillator, voltage doubler, timer,
LCD driver, input port, output port and overcharge protection circuit for connection to a solar cell.
The MSM5056 is widely used in electronic products requiring low power operation, for example,
solar calculator watches and games.
FEATURES
• Low Power Consumption 3 !LA Typical
• 1792 x 14 Internal ROM
• 90 x 4 Internal RAM
• 4 Input Port
• 4 Output Port
• 4 x 4 Key Matrix Input (K 1-K4, M 1-M4)
• 38 LCD Driver
(112 Duty, 112 Bias, 88 Segment)
• 42 Instructions
• /1 .5 V Operating Voltage
(The solar.cell can be connected.)
• 32.768 kHz Crystal Oscillator
• 122.1!Ls Instruction Cycle
• -20 to 75°C Operating Temperature
• 68 pad die
FUNCTIONAL BLOCK DIAGRAM
DATA RAM
SD
A3-AO
SEGMENT
OUT t
LD
~~~~~2~DISPLAY
I
SEGMENT
OUT 38
LATCH
and
IS=======r~~~~~g~~~~~~~~~~~==~DRIVER
---+
COMl
COM,
INSTRUCTION
OECOOEA
I I I I 1I
VOD
VSS2
Vsc
VCM
VEE
vcp VIN
vss,
111
•
MSM5056·----~----------------,------
CHIP PAD LAYOUT
LOGIC SYMBOL
SEGMENT OUTPUT
OSCILLATION [
M,
M,
M,
M,
RESET
BO
LD
VOO
~~ J
VSS 1,
~~~2
ADJUSTMENT for
LAMP OUTPUT
AC
T4
VSC
VCP
VCM
TEST
Ts
V IN
~~i~:g:LL CRAMP'--_ _ _- '
CHIP SIZE 5.42 x 4.13 (mm)
PIN DESCRIPTION
Designation
VOO
VSS,
Power sQurce (-1.5 V)
VSC
Solar cell connection terminal
VSS 2
Power source for LCD driver (-3.0 V)
This terminal is cOnl1ectedtoVoO terminal through a 0.1 fJ.F capacitor.
VEE
Power source for internal logic (-1.5 to -3.0 V)
This terminal is connected to VOO terminal through a 0.1 fJ.F capacitor.
VCP,VCM
Booster capacitor connection terminals
VCP terminal is connected to VcM terminal through a 0.1 fJ.F capacitor.
XT,XT
Input and output terminals of ,oscillator inverter,
32.768 kHz crystal is connected to these terminals.
T,-Ts
Terminals to test internal logic, T, - T3 and Tsare pulled down to VSS,.
T4 is output. Test pins must be normaly open.
AC
Terminal to clear internal logic pulled down to VSS,.
After power i~ turned on, the MSM5056 must be reset by this terminal.,
BO
Buzzer output
LO,
Lamp output
VIN
112
Function
Circuit ground potential
Adjustment for solar cell cramp voltage
, This termi!1al is connected to VSS, termilJal through 50 - 200 kG resistor.
---------------------------e. MSM5056 •
FUNCTIONAL DESCRIPTION
A block diagram of the MSM5056 is given on
page 111. Each block of logic will be briefly
discussed. For more information, please refer to
the MSM5056 user's manual.
Program RPM
The MSM5056 will address up to 1.75 K
words of internal mask programmable ROM.
Each word consists of 14 bits and all
instructions are one word. The instructions are
routed to a programmed logic array which
generates the signals necessary for control of
logic.
Data RAM
Data is organized in 4 bit nibbles. Internal
data RAM consists of 90 nibbles.
The RAM is addressed by page address and
column address. Normally page address is
specified with the page register, but direct
addressing is available at Page O.
Column address is directly addressed by the
operands of various instructions.
ALU
The ALU performs 4-bit parallel operation of
RAM and AC contents, or RAM contents and an
immediate digit. It sets or resets the flags (Z, C)
depending on the condition.
Program Counter (PC)
The program counter is an 11-bit wide
counter and specifies the address of the
program ROM.
The PC is incremented by one at every
execution of an instruction,· and then specifies
the next instruction to be executed. However, the
contents of thePC are rewritten by the execution
ota Jump or Branch instruction.
There is no boundary in the ROM, so a Jump
or Branch instruction can be put anywhere in the
ROM.
Input/Output Port
Input Port (K1 - K2)
The input port (K1 - K4) is a 4-bit parallel
input port. Each pin of the port is pulled down to
VSS1 by an internal reSistor, and the status of
the port can be fetched by an input instruction.
•+
Kl
K2
K3
~
K4
Ml
M2
M3
M4
Display Function
The MSM5056 is provided with a segment
output terminal which can directly drive a 1/2
bias, 1/2 duty LCD and common drive output
terminals. COM1 and COM2. The segment drive
circuit consists of the display data latch,
multiplexer and driver. If the data is sent to the
display data latch with the display instruction,
the LCD drive waveform is output to the segment
drive output terminal.
Time Base
Time base of the CPU is provided by
connecting a 32.768 kHz crystal to the OSC1
and OSC3 pin. One machine cycle is 1 22.1 /Ls.
A hardware divider up .to 1 Hz is provided
enabling programs to implement and a clock
function by counting Signals between 16 and 1
Hz.
.
Solar Cell Overcharge Protection Circuit
When a solar cell is connected to prolong the
usefull life of the battery, a resistor is inserted
between the VIN pin and VSS1 to adjust the
overcharge protection voltage.
...-----1 VSS,
~"'\A\i","""--I V I N
MSM5056
Output Port (M1 - M4)
. The output port (M1 - M4) is a 4-bit parallel
output port. This port consists of data latches
and buffers. The contents of data latches are
rewritten by an output instruction. A key matrix
is used in combination with K1 to K4.
113
•
MSM5056··--~--------------------~----~------------------
ABSOLUTE MAXIMUM RATINGS
Limits
Unit
-0.3 to +3.0
V
Ta =25°C
-0.3 to +3.5
V
VOO - VSS 2
Ta = 25°C
-0.3 to +6.0
V
VOO -VEE
Ta = 25°C
-0.3 to +6.0
V
Ta = 25°C
VSS, -0.3 to +0.3
V
-55 to 125
°C
Symbol
Conditions
Supply Voltage 1
VOO-VSS,
Ta = 25°C
Supply Voltage 2
VOO -VSC
Supply Voltage 3
Supply Voltage 4
Parameter
Input Voltage
VIN,
Storage Temperature
Tstg
,
OPERATING CONDITIONS
Parameter
Operating Voltage
Operating Temperature
Symbol
Limits
Unit
VOO-VSS,
1.25 to 1.65
V
Topr
-20 to 75
°C
DC CHARACTERISTICS
(Voo =OV, VSS" VEE = -1.55V, VSS 2 = -3.0V, CI = 30kfl, CG = 30pF, Ta = 25°C)
Limits
Parameter
·Condition
Symbol
Unit
Min.
Operating voltage 1
-VSS,
VSS, terminal
Operating voltage 2
Typ. Max.
1.25 1.55
2.0
V
-VSC
VSC terminal
0
2.0
3.0
V
Power supply current
'DO
VSS, terminal
-
3.0
-
p.A
Oscillation start
voltage
-VOSC
Within 10 seconds
VSS, terminal
1.45
-
-
V
IOH,
VOH, =-0.2V
-4
-
-
10M,
VOM, = VSS, ± 0.2V
4/-4
-
-
IOL,
VOL, =-2.8V
4
-
-
Output current 2
SEGMENT
IOH2
VOH2 =-0.2V
-0.4
-
-
IOL2
VOL2=-2.8V
0.4
-
-
Output current 3
M,-M.
IOH3
VSS" VEE -1.25V
-100
-
-
IOL3
VSS 2 -2.3V
3
-
8
Output current 4
IOH.
VOH. =-O.4V
IOL.
VOL. = -1.15V
IIH,
IlL,
Output current 1
COM
BO
Input current
K,-K.
Oscillator built-in
capacitor
CD
Solar battery cramp
resistor
RIN
114
I VOH3 -0.4 V
I VOL3-0 .85V
-50 -100 -200
p.A
p.A
/LA
3
10
VIN =-OV
5
10
15
VIN = -1.55V
-
-
-0.2
-
20
-
pF
-
200
kfl
VSS, = -1.8V
VIN terminal
50
30
p.A
p.A
-------------------------------------------e. MSM5056.
MEASURING CIRCUIT
30pF
0.1j.1F
32.768kHz
TYPICAL APPLICATION
LCD
TR2
Kl
K2
K3
K4
M4
M3
BD
MSM5056
M2
Ml
VSC
VIN
AC
'--_-.......---~-------1
CG : 5-35pF
C1 .C 2 .C 3 : 0.1j.1F
TR1. TR2 : hfe'" 200
TR2 : VCEo..> 35V
20-~OmH
Ll
:
B
R
: 1.5V'
: 50 - 200kO
115
•
M$M5056·~.----~----------------------------~------~---
DESCRIPTION
OF INSTRUCTIONS
Instruction Code
Mnemonic
Operation
131211109 8
c
0
:;...
8.
0
7
6 5 4
ADD ACC,AP
0
0
0
ADD #o,AP
0
1
1 0
AoCAP
0
0
0
SUBACC,AP
0
0
/) 0
1
SUB #0, AP
o
'1
1 0
1 P
SBCAP
0
0
0 0
1 P 0
1 0
CMPACC,AP
0
0
0 0
1 P 1
1
0 0
o
0 0
P 0
1 0
P
3
1 0
2
0
AP--(AP) - 0
P 0
1 0
1
A
Af' -- Decimal adjust
{(AP) + (ACC) + (C)}
P 0
1 0 0
A
AP -- (AP) - (ACC)
A
AP --(AP) - 0
1
A
AP-- Decimal adjust
{(AP) - (ACC) - (C)}
1 0
A
(AP) - (ACC)
0
:;
E
.c
«
CMP #o,AP
0
1 0
INCAP
0
1 1 0
1
0
1
0
0 0
1
1 P
0
0
BIT#o,AP
0
1 0
...
BISACC,AP
0
0
c.
BIS#o,AP
0
1. 0
iii
BICACC,AP
0 0
BIC #0, AP
0
1 0
0
1 P
ASRAP
0
0
0
0
0
ASlAP
0
0
0
0
1 P 0
elZ
0
0
0 0 .0 0
~
en
c
0
:;...
8.
0
A--(AP) - 1
A
AP -- (AP) "'It" (ACC)
A
AP --(AP)VD
A
(AP) V (ACC)
1 0
0
P 1
0 0
0
1 0
1
P
0
0 0 .0 P 0
0
A
1
1
1 1
-
i
1
0
0 .0 0
Q)
0
0
1 .P
0
0
AP"':"(AP)
0 .0 P 0
XOR #o,AP
iii
(AP) - 0
A
0
BITACC,AP
c
.2
A
1
0
P 0
0
1 0
oECAP
XORACC,AP
1 P
0
(AP)
+ (ACC)
AP
A
(.)
=E
~
A
0
1
P
1
0
0
1 P 0
1
1 0
+1
A
(AP)Vo
A
AP -- (AP) V (ACC)
A
AP --(AP) VD
A
AP -- (AP) I\(ACC)
A
AP -- (AP) 1\ 0
1
A
L-(C) 0 - (AP):::I
.0 1 1
A
0
P .0 0
1
1 0
1 0
0
0
(C) -- (AP) -- 0
0
0
Z--O
1 0 0
1 0
0 0
0
C--O
.0. 0 0 0 0
1 0
1 0
0 0
0
Z --0, C--O
0
0 0
0
1 0
1 0
1 0 0 0 0 0
0
0 0
0
1 0
1 0
0
0
0 0
0
1 0
1 0
1
1
1
1
1
0
ClC
.0 0 0 0 0 0
ClA
0
SEZ
SEC
1
Z"-1
CI
III
u:
SEA
!
MOVACC,AP
P 0
0 0
1 0
0
1 0
0 0
0
...
MOVACC,AX
1
1
1 1 0 0 0
'0
MOV#D,AP
0
1
1
III
MOVAP,ACC
1
1
1 1 1 P 0 0 0 0
MOV AX, ACC
1 1 1 1 1 0 0
CHGAP
1 1
1 0
CHGAX
1 1
1 0 .0 0
Q)
c
=
~
0
116.
1 0
0
X
P
0
P 0
0
X
0
0
X
0
0
0
C-1
O. Z-1,C"-1
A
AP-(ACC)
A
AX --(ACC)
A.
AP --0
A
ACC --(AP)
A
ACC-(AX)
A
(ACC)-(AP)
A
(ACC)-(AX)
--------------------------~----------------------__e.
MSM5056 •
DESCRIPTION OF INSTRUCTIONS (CONT.)
Instruction Code
Operation
Mnemonic
131211109 8
7
6
5
4
3
1
2
0
JMP adrs
1
0
0 a lO a9 a 8 a7 ae as a. a3 a2 a, ao
JMP @AP
0
0
0
0
0
P
1
1 0
1
A
PC -
(PC) + (AP) + 1
JMPIO @AP
0
0
0
0
1
P
1
1 0
1
A
PC -
(PC) + ((AP)A7H) + +1
BEQ
BZE
+n
+n
0
0
0
1
1
0
0
1 0 n. n3 n2 n, no
PC -
(PC)+n+1, if Z=1
BNE
BNZ
+n
+n
0
0
0
1
1 0
1
1 0 n. n 3 n 2 n, no
PC -
(PC) +n + 1, if Z =0
BCS
BLT
+n
+n
0
0
0
1
1
0
0
0
1 n. n3 n2 n, no
PC -
(PC)+n+1, if C=1
BCC
BGE
+n
+n
0
0
0
1
1
0
1 0
1 n. n 3 n2 n, no
PC -
(PC) + n + 1, if C = 0
BGT
+n
0 .0
0
1
1
0
1
1
1 n. n3 n2 n, no
PC -(PC)+n+1,ifZ=0
and C=O
BLE
+n
0
0
0
1
1
0
0
1
1 n. n3 n2 n, no
PC -
(PC) +n+ 1, if Z= 1
orC=1
INP Port, AP
1
1 0
1
0
P
(Port)
OUT AP, Port
1
1 0
1
1
-0 OUT #0, Port
1
0
a.
E
:;,
...,
-
-:;,
.....
:;,0.
0.-
PC -adrs
Port
A
AP -
P
Port
A
Port -
0
Port
D
Port - 0
(AP)
1:::;'
0
0
0
>
C1I
OSP digit, AP
0
0
1 0
0
P
digit
A
digit -
(AP). (ACC)
III
OSPF digit, AP
0
0
1
1
0
P
digit
A
digit -
(AP) via table
HALT
0
0
0
1
0
0
0
0
0
0
0
0
0
0
Halt CPU
NOP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
No Operation
a.
i5
e
::::>-
0..1::
08
117
OKI
semiconductor
MSM6051
CMOS 4BIT. HIGH PERFORMANCE SINGLE CHIP VERY LOW POWER
MICROCONTROLLER WITH LCD DRIVER
GENERAL DESCRIPTION
OKl's MSM6051 is a low-power and high-performance single-chip microcontroller employing
complementary metal oxide semiconductor technology. Integrated onto a single chip are a 4-bit ALU,
35K bits of mask programmable ROM, 480 bits of data RAM, crystal oscillator, voltage doubler, timer,
LCD driver, input port and output port.
The MSM6051 is widely used in electronic products requiring low power operation, for example,
stopwatches with lap time memory, calculator watches and handy terminals.
FEATURES
•
•
•
•
•
•
•
Low Power Consumption 3 !LA Typical
2560 X14 Internal ROM
120 x 4 Internal RAM
9 Input Port
4 Output Port
4 x 4 Key Matrix Input (K1-K4, M1-M4)
66 LCD Driver (including 3 common)
(1/3 Duty, 1/3 Bias, 189 Segment)
•
•
•
•
•
•
59 Instructions
1.5 V or 3 V Operating Voltage
(Masking Option)
32.768 kHz crystal Oscillator
91.5 /Ls Instruction Cycle
-20 to 75°C Operating Temperature
101 pad die
FUNCTIONAL BLOCK DIAGRAM
DATA RAM
SD
120 word x 4bit
LD
M1
I
SEGMENT
oun
M4
LO
S
SEGMENT
PROGRAMAOM
OPTION
256 word x 14 bit
VSS 1
!!
VDD
118
INSTRUCTION
DECODER
VSS3
vep
j j j j
VSS2
VEE
!
VCM
!!1j !!j
AC T1 T2 T3' T4 T5 32Hz
- - - - - - - - - - - - - - - - - - - - - - - - - - . MSM6051 •
LOGIC SYMBOL
OSCILLATION (
XT
XT
CHIP PAD LAYOUT
SEGMENT
OUTl
INPUT PORT [
(Sl-S4)
INPUT PORT [
(Kl-K4)
OPTION INPUT
SEGMENT
OUTee
BD
LD
SEG60
\l,roM~'
OPIN
VDD
VSS2
VSS3
VCP
VCM
Sl
S4
VSS1
DO
XT
XTOUT
AC2
S2
S3
BUZZER OUTPUT
VEE
VCH
Kl
K2
K3
K4
Ml
M2
M3
M4
LO
LAMP OUTPUT
CLOCK PULSE
OUTPUT
OUTPUT PORT [
(Ml-M4)
SEG34
VDD
Xl
RESET
LOAD
SEG1
LD
AC
T3
T1
T4
T2
T5
32Hz
~~~~~~~~
SEG33
SEGMENT OUTPUT
CHIP SIZE 5.85
x 4.10(mm)
PIN DESCRIPTION
Designation
Function
VDD
Circuit ground potential
VSS 1
Power source (-1.5 V)
VSS 2
Power source for LCD driver (-3.0 V)
This terminal is connected to VDD terminal through a 0.1 JLF capacitor.
VSS3
Power source for LCD driver (-4.5 V)
This terminal is connected to VDD terminal through a 0.1 JLF capacitor.
VEE
Power source for internal logic (-1.5 to -3.0 V)
This terminal is connected to VDD terminal through a 0.1 JLF capacitor.
VCP, VCM
Booster capacitor connection terminals
VCP terminal is connected to VCM terminal through a 0.1 JLF capacitor.
XT,XT
Input and output terminals of oscillator inverter,
32.768 kHz crystal is connected to these terminals.
Tl-T5
Terminals to test internal logic, T 1 - T3 and T 5 are pulled down to VSS 1•
T4 is output. Test pins must be normally open.
AC
Terminal to clear internal logic pulled down to VSS 1•
After power is turned on, the MSM6051 must be reset by this terminal.
BD
Buzzer output
LD
Lamp output
LO
Load data terminal of M 1 to M 4.
AC2
Reset terminal for external circuit.
XTOUT
Clock output for external circuit.
119
• MSM6051
.------------~--------------------------------------
FUNCTIONAL DESCRIPTION
Input/Output Port
A block diagram oUhe MSM6051 Js given on
page 118. Each block of logic will be briefly
discussed. For more information, please refer to
the MSM6051 user's manual.
Input Port (51 - 54)
The input port (S1 - S4) is a 4-bit parallel
input port. Each pinof the port is pulled down to
VSS 1 by an internal resistor, and the status of
the port is fetched by a SWITCH instruction.
Program ROM
The MSM6051 addresses up to 2.5 K words
of internal mask programmable ROM. Each word
consists of 1 4 bits, and a:II instructions are one
word. The instructio.ns are routed to a
programmed logic array which generates the
signals necessary for control. of logic.
Data RAM
Data is organized in 4 bit nibbles. Internal
data RAM consists of 1 20 nibbles.
The RAM is addressed by page address and
column address. Normally page address is
specified the with page register, but direct
addressing is available at Page O.
Column address is directly addressed by
operand of various instructions.
ALU
The ALU performs 4-bit parallel operation of
RAM and ACC contents, or RAM contents and
an immediate digit. It sets or resets the flags (Z,
C, G) depehding on the condition.
Program Counter (PC)
The program counter is 12 bits wide and
specifies the address of the program ROM.
The PC is incremented by one at every
execution of the instruction, and then specifies
the next instruction to be executed. However, the·
contents of the PC are rewritten by the execution
of a Jump, Call or Branch instruction.
There is no boundary in the ROM, so a Jump
or Branch instruction can be put anywhere in the
ROM.
5tack
The MSM6051 has a 3 level stack apart from
data RAM. The contents of the PC are loaded
into the stack when a call instruction is executed
or an interrupt is generated.
120
Input Port (K1 - K4)
The input port (K1 - K4) is a 4-bit parallel
input port. Each pin of the port is pulled down to
VSS 1 by an internal resistor, and the status of
the port is fetched by a KSWITCH instruction.
Input Port (OPIN)
The input port (OPIN) is single input port.
OPIN is pulled down to VSS , by an internal
power save circuit, and the status of the port is
fetched by an input instruction.
Output Port (M1 - M4)
The output port (M1 - M4)is a 4-bit parallel
output port. This port consists of data latches
and buffers, and the contents of data latches are
rewritten by a matrix instruction.
Display Function
The MSM6051 is provided with the segment
output terminal which can directly drive a 1/3
bias, 1/3 duty LCD, and the common.drive
output terminals COM1, COM2 and COM3.
The segment drive .circuit consists of the
display data latch, multiplexer and driver. If the
data is sent to the display data latch with the
display instruction, the LCD drive waveform is
output to the segment drive output terminal.
Time Base
The time base of the CPU is provided by
connecting 32.768 kHz crystal to the XT and XT
pin. One machine cycle is 91.5 fls.
A hardware divider up to 1 Hz is provided
enabling programs to implement a clock function
by counting signals between 32 and 1 Hz.
Also, a 1/100 second digit counting function
is provided as a hardware feature to make for
easy implementation of a stopwatch function.
- - - - - - - - - - - - - - - - - - - - - - - - - - . MSM6051 •
ABSOLUTE MAXIMUM RATINGS
Symbol
Conditions
Limits
Supply Voltage 1
VDD -VSS,
Ta = 25°C
-2.0 to +0.3
V
Supply Voltage 2
VDD -VSS2
Ta =25°C
-4.0 to +0.3
V
Supply Voltage 3
VDD - VSS3
Ta = 25°C
-6.0 to +0.3
V
Supply Voltage 4
VDD -VEE
Ta = 25°C
-4.0 to +0.3
V
VSS, -0.3 to +0.3
V
-55 to 125
°c
Parameter
Input Voltage
VIN,
Storage Temperature
Tstg
Ta
=
25°C
Unit
OPERATING CONDITIONS
Parameter
Operating Voltage
Operating Temperature
Unit
Symbol
Limits
VDD-VSS,
1.25 to 1.65
V
Topr
-20 to 75
°c
DC CHARACTERISTICS
(VDD =OV, VSS" VEE = -1.55V, VSS 2= -3.0V, VSS3 = -4.5V, CI = 30kn, Ta = 25°C)
Limits
Parameter
Symbol
Conditions
Unit
Min.
Power supply current
Oscillation start
voltage
IDD
Output current 2
SEGMENT
Max.
-
/-LA
-
V
1.45
-
VOH, =-0.2V
-4
-
-
IOMH, VOMH, =VSS, ± 0.2
4/-4
-
-
IOML, VOML, = VSS 2 ± 0.2
4/-4
-
-
IOL,
VOL, =-4.3V
4
-
-
IOH2
VOH2 =-0.2V
Within 5 seconds
-VOSC VSS, terminal
IOH,
Output current 1
COM
3.0
-
VSS terminal
Typ.
-4
-
-
IOMH2 VOMH2 = VSS,±0.2
4/-4
-
-
IOML2 VOML2 = VSS 2±0.2
4/-4
-
-
IOL2
VOL2 =-4.3V
4
-
-
Output current 3
AC2 LOAD XTOUT
IOH3
VOH3 =-0.5 V
-10
-
-
IOL3
VOL3 = -1.15V
10
-
-
Output current 4
IOH4
VOH4=-0.5V
-100
-
-
IOL4
VOL4 =-1.0V
2
-
10
IOH5
VOH5 = -0.55V
IOL5
VOL5 = -0.85V
IOHe
VOHe = -0.55V
IOLe
VOLe = -0.85V
M,-M4
Output current 5
LD
Output current 6
SD
VSS, =-1.25V
VEE =-2.0V
VSS 2=-2.0V
Vss,=-1.25V
VEE =-2.0V
VSS 2 =-2.0V
-12.5 -25
/-LA
/-LA
/-LA
/-LA
-83
1
-
-
-17
-30
-62
-
5
-
/-LA
/-LA
121
• MSM6051 ••--------~----------------------~--------------Limits
Parameter
Symbol
Conditions
Unit
Min.
Typ.
Max.
VIH, =OV
2
20
100
IlL,
VIL,=-1.55V
-
-
-0.2
Input current 2
K,-K.
IIH2
VIH2 =OV
5
13
26
IIL2
VIL2 = -1.55V
-
-
-0.2
I nput current 3
OPIN
IIHa
VIHa =OV .
-
30
45
VILa = -1.55V
-
-
-0.2
-
20
-
IIH,
Input current 1
S,-S.
liLa
Oscillator built-in
capacitance
CD
p.,A
p.,A
p.,A
MEASURING CIRCUIT
VCP
VCM
XT
XT
VEE
C1.C2.C3 .C4 0.1 JLF
C5
30 pF
X-tal
32.768 kHz
C4
=
C5
TYPICAL APPLICATION
C1
C2toC5
LCD
B
L
5-35 pF
0.1 JLF
1.5 V
20mH
Lamp
S1 --'S2 ___
S3....L...
S4 .....:...
S1
S2
LD
S3
BD
S4
MSM6051
X-tal
=
C1
122
XT
(CD=20 pF)
VSS,
VDD
B
pF
------------~------------------~------------------. MSM6051 •
DESCRIPTION OF INSTRUCTIONS
Instruction Code
Mnemonic
Operation
131211109 8
AOOACC,AP
0 0
AOO#O,AP
0
AOCAP
0
7 6
4
1 0
0
A
AP - (AP) + (ACC)
A
AP-(AP) +0
1
A
AP - Decimal adjust
{(AP) + (ACC) + (C)l
A
AP - N adjust {(AP) + (C)l
0
A
AP - (AP) - (ACC)
A
AP-(AP) -D
A
AP - Decimal adjust
{(AP) - (ACC) - (C)l
A
AP - N adjust ((AP) - (C) I
A
(AP) - (ACC)
A
(AP) -0
0
0
P 0
1
1 0
0
P
0
0
0 0
P 0
0 0
P
N
1 P 0
1 0
0
AOCNAP
1
1 0
SUB ACC,AP
0
0
c::
SUB#D,AP
0
1
~
SBCAP
0 0
SBCNAP
CMP ACC, AP
0
0
3
2
0
1 0
1 0
1 P
0
0
1 P 0
1
1 0
0
1 P
0
0
0
0
1 P 1
:5 CMP#D,AP
0
1 0
1
1 P
INCAP
1
1
1 0
0
P 0
INCAX
1
1
1 0
0
0
DECAP
1
1
1 0
1 P 0
DEC AX
1 1
1 0
1 0 0
XORACC,AP
0
0
0
0
0 P 0
1 1
XOR #D,AP
0
1
1
1
1 P
BITACC,AP
0
0
0
0
0
BIT #D,AP
0
1 0
1 0
0
0
0
0
0
P 0
0
1 0
0
0
P
0
0
0
0
1 P 0
BIC#D,AP
0
1 0
0
1 P
RORAP
0
0
0
0
0
P 0
0
ROlAP
.....
Q)
a; ASRAP
0
0
0
0
1 P 0
0
0
0
0
0
0 P 0
0
1
II:
0
0
0
0
1 P 0
0
0
1 0
5
D
0
t
1
Qi
a.
0
0
~
E
~
c:
0
~
Qi BISACC,AP
a.
0
BIS #0, AP
iii BIC ACC, AP
~
:.c
(J)
"0
c:
0
:;....
Q)
a.
0
01
III
u::
ASLAP
N
1 1 0
0
A
AP - (AP) + 1
X
A
AX-(AX) + 1
0 0
A
AP -(AP)-1
X
A
AX -(AX)-1
A
AP - (AP) -V- (ACC)
A
AP - (AP) "'f D
A
(AP) V (ACC)
A
(AP) V D
A
(AP) V (ACC)
A
(AP)VD
A
(AP) /\ (ACC)
A
(AP) /\ D
1 0
A
L. (C) - (AP)---i
1 0
A
L(C)-(AP)~
1
A
L. (C) 0 - (AP)--l
1 1
A
0 0
0
0
0
1
D
P 1
1
1 0
D
P
1 1 0
D
1
1 0
D
ClZ
0
0
0
0
0
0
1 0
ClC
0
0
0
0 0
0
1 0 0
ClG
0 0
0
0 0
0
1 0
0 0
ClA
0
0
0
0
0
0
1 0
1
SEZ
0
0
0
0
1 0
1 0
1
SEC
0
0
0
0
1 0
1 0
0
1 0
o
(C) -(AP)-O
0
0
Z-O
0 0
0
C-O
0
0
0
G-O
1 0
0 0
0
Z -0, C -0, G-O
o
0 0
0
Z-1
0
0
C-1
1 0 0
1 0
0
0
0
123
eMSM6051 e~------------------------------------------~-----
DESCRIPTION OF INSTRUCTIONS (CONT.)
Instruction Code
Operation
Mnemonic
131211109 8
....
~
(J)
7 6
5
4 3
2
1 0
SEG
0
0
0
0
1 0
1
0
0
0
0
0
0
G-1
SEA
0
0
0
0
1 0
1 0
1
1 0 0
0
0
Z-1,C-1,G-1
MOVACC,AP
1
1
1
1 0 P 0
0
0
MOVACC,AX
1
1
1
1 0 0
MOV#D,AP
0
1
1
1
0 P
MOVAP, ACC
1
1
1
1
1 P 0
0
0
X
0
A
AP-(ACC)
A
AX-(ACC)
<::
g
FORMATAP
tIS
c.
III
0 0 0 1 0 0 1 0 0 0 0
1 aa a 7 as a 5 a 4 a 3 a 2 a, ao
b, b o
Melody stop
LD ON/OFF
0 1 1
A
FMT reg. -- (AP)
FORMATN
0 0 0 1 0 0 0 0 1 1
N
FMTreg.--N
DSPF digit, AP
0 0 1 1 0 P
digit
A
Digit (Low part) -- (AP) via table
digit
A
Digit (High part) --(AP) via tab I
DSPFH digit, AP 0 0
1 1 P 0
o
Stack -- (PC), PC ..... adrs,
Melody start
1 1 1 P
HALT
0 0 0 1 0 0 0 0 0 0 0 0 0 0
INTENAB
32/16/2
0
0 0 1 0 0 1 0 1 1 1 0 0 0
0
0 0 1 0 0 0 1 0 0 b 3 0 b, 0
INTDSAB
32/16/2
0
0 0 1 0 0 1 0 1 1 0 1 0 0
0
0 0 1 0 0 0 1 0 0 0 b2 0 bo
ACTIVATE
Halt
Enable timer interrupt
Disable timer interrupt
0 0 0 1 0 0 1 0 0 1 0 0 0 0
Activate main routine
INTMODEAP
1 1 0
AP -- Interrupt mode
...
KENAB
0 0 0 1 0 0 0 1 1 1 1
0 0
Enable INPUT PORT (K1-K4)
.r.
KDSAB
0 0 0 1 0 0 0 1 1 1 0 1 0 0
Disable INPUT PORT (K1-K4)
OIl
STATUSAP
1 1 0
1 0
1 0
A
AP --Status
PAGEAO
1 1 0
1 1 0
0 1 0 1
A
Preg --(AO)
PAGEN
0 0 0 1 0 0 0 1 0 1
N
Preg --N
ADRSAP
1 1 0
1 0
A
Areg--(AP)
ADRSN
0 0 0 1 0 0 0 1 1 0
N
Areg --N
RATEAP
1 1 0
A
RSTRATE
0 0 0 1 0 0 1 0 0 0 1
FLAGINAP
1 1 0
1 0 P 1 1 1 0
A
AP -- S1 on flag, S2 on flag
S1 RATE AP
1 1 0
1 0
P 1
1 0 0
A
AP --S1reg.
S2RATEAP
1
1 0
P 1
1 0
A
AP --S2reg.
BACKUP
ON/OFF
0 0 0 1 0 0 0 0 0 1 b3 b2 0 0
Backup ON/OFF
NOP
0 0 0 0 0 0 0 0 0 0 000 0
No operation
III
1 0 P 0
1 0
A
0
o
Q)
0
e"E
0
Co)
::l
Q.
Co)
1 0
P 1 0
1 1 P 0
1 0
1
P 1 0
0 1
1
o
AP -- DIVIDER (8 Hz-1 Hz)
0 0
DIVIDER (8 Hz-1 Hz)--O
125
OKI
semiconductor
MSM6351
CMOS 4BIT HIGH PERFORMANCE AND VERY LOW POWER SINGLE CHIP
MICROCONTROLLER WITH LCD DRIVER
GENERAL DESCRIPTION
OKl's MSM6351 is a low-power, high-performance single-chip microcontroller employing silicon
gate CMOS technology. Integrated onto a single chip are 4-bit ALU, 61 K bits of mask programmable
ROM,·4096 bits of RAM, 20 bits of 110 port, serial 110 port, time-base counter, LCD driver, 3
interrupts, crystal oscillator and voltage trjpler.
The MSM6351 is widely used in electronic products requiring low power consumption, a large
number of LCD drivers and a large size of memory.
FEATURES
\
•
•
•
•
•
Low Power Consumption 3 p..A Typical
4096 x 15 Internal ROM
1024 x 4 Internal RAM
20 Input/Port Ports
62 LCD Drivers
1/3 Duty, 1/3 Bias or 1/4 Duty 1/3 Bias
(Selectable by software)
• Serial I/O Port
8 bits or 5 bits data frame mode
Asynchronous or synchronous
receiver/transmitter mode
Internal or external clock mode
• 15 stages Time Base Counter
• Watch Dog Timer
• Capture function by external trigger signal
126
• 3 Interrupt Sources
Real time interrupt
External interrupt
Serial 110 port interrupt
• Melody Circuit
• 65 Instructions
• Sub-routine Nesting: 7 levels
• 32.768 kHz Crystal Oscilator
• Machine Cycle: 61.0 p..sec.
• Power Supply: 1.5V or 3.0V (selectable by
mask option)
• 100 pad die orl 00 Pin Flat Package
• Silicon gate CMOS Process
- - - - - - - - - - - - - - - - - - - - - - - - . MSM6351 •
FUNCTIONAL BLOCK DIAGRAM
LOGIC SYMBOL
PORTO
PORn
C
C
PO.O
PO.l
PO.2
PO.3
Pl.0
Pl.1
P1.2
P1.3
PORT2C
P2.0
££.1.
Pg·2
P2.3
PORT3
PORT4
C
C
SIN
SOUT
SCK
Bo
==: J
SERIAL PORT
BUZZER
DRIVER
seGO
SEGl
SEG2
SEG3
SEG4
P3.0
P3.1
P3.2
P3.3
P4.Q
P4·1
P4.2
P4.3
LCD
DRIVER
gEG58
SEG59
SeGruL
SEG6l
XTOUT
Voo
RESET
XT
Voo
X'f
VSS1
RESET
VSS2
VSS3
TESTe
TEST1
TEST2
TEST3
VEE
VCM
VCP
l
POWER
SUPPLY
J
127
• MSM6351 • - - - - - - , . - - - - - - - - - - - - - - - - - - -
PIN DESCRIPTION
Designation
Function
PO.O -PO.3
4 bits input/output port.
PO.O and PO.1 have a secondary function of capture trigger signal input pins.
P1.0 - P1.3
4 bits input/output port.
P2.0 -P2.3
4 bits input/output port.
P2.0, P2.1 and P2.2 have a secondary function of external interrupt signal
input pins.
P3.0 -P3.3
4 bits input/output port.
P4.0 -P4.3
4 bits input/output port.
SIN
Serial input port.
SOUT
Serial output port.
SCK
Serial port clock input/output pin.
SEGO-SEG61
LCD drive output pins.
These outputs can derive 1/3 dutY-1 /3 bias LCD which has 177 segments or
1/4 dutY-1 /3 bias LCD which has 232 segments.
Designation
128
Function
BD
Buzzer drive output pin.
XTOUT
Clock output pin.
XT,XT
Input and output pins of oscillator inverter.
RESET
System reset input pin pulled down to VSS1 .
TEST1 -3
Internal logic test pin pulled to VSS1.
VDD
Circuit ground potential
VSS1
Power source (-1 .5V)
VSS2
Power source for LCD driver (-3.0V)
This pin is connected to VDD pin through a capacitor.
VSS3
Power source for LCD driver (-4.5V)
This pin is connected to VDD pin through a apacitor.
VEE
Power source for internal logic.
This pin is connected to VDD pin through a capacitor.
VCP, VCM
Booster capacitor connection pins.
VCP pin is connected to VCM pin through a capacitor.
-
OKI
semiconductor
MSM6052
CMOS 4BIT SINGLE CHIP LOW POWER MICROCONTROLLER FOR
TELEPHONE
GENERAL DESCRIPTION
The OKI MSM6052 is low-power, high-performance single-chip 4-bit microcontroller employing
complementary metal oxide semiconductor technology, especially designed for use in sophisticated
telephone sets. Integrated onto a single chip are 4 bits of ALU, 28K bits of mask programmable ROM,
2560 bits of data RAM, programmable timer, oscillator, 12-bits of input port, 12-bits of output port and
4-bits of input/output port. In addition to these units, a DTMF generator is provided.
With the MSM6052, sophisticated telephone sets become feasible through a single chip instead
of the conventional 3-chip configuration.
FEATURES
•
•
•
•
•
•
•
•
•
Low Power Consumption 0.3mA Typical @3V
(DTMF output off)
2048 x 14 Internal ROM
640 x 4 Internal RAM
3 x 4 Input Port
3 x 4 Output Port
1 x 4 Input/Output Port
DTMF Generator
Buzzer Sound Output
4-Bit Programmable Timer Applicable for
Output of Dial Pulse
• Interrupt by Progammable Timer
• 5 Level Stack
• Power Down Mode
• 52 Instructions
• Instructions Useful for Data Management
(Data Search and Block Data Transfer)
• 2.5 to 6.0V Operating Voltage
• 3.58 MHz Oscillator
• 1 7.9 Ils Instruction Cycle
• -20 to 75°C Operating Temperature
• 28 Pin DIP or 40 Pin DIP
FUNCTIONAL BLOCK DIAGRAM
[iPOUT
DTMFOUT
BD
DATA RAM
640 word x 4 bit
R.
R2
~~
RS
~
He
PROGRAMMABLE
TIMER
g
DTMF
CIRCUIT
••'3
C.
C2
-g~
8~
03
D.
EO.
E02
E03
EO.
10.
102
18~
10E
INSTRUCTION
HS --l'------''---'
DECODER
PROGRAM ROM
2048 word x 14 bit
XT
Xi'
32kHz
TIMING
'GENERATOR
!!
AC TEST
11
"DO Vss
l _________________
t.::::::::~===========~JI
~
129
• MSM6052 ••----------------------------~--------~--------~
PIN CONFI.GURATION
(Top View) 40 Lead Plastic DIP
E03
C1
E04
C2
(Top View) 28 Lead Plastic DIP
C3
02
RS
R7
03
VDD
LOGIC SYMBOL
KEYBOARD [
INPUT
R1
R2
R3
R4
KEYBOARD [
. INPUT
RS
RS
R7
R8
INPUT PORT [
11
12
13
14
KEYBOARD [
OUTPUT
C1
C2
C3
C4
E01
E02
E03
E03
] OUTPUT PORT
] 10PORT
OUTPUT ENABLE
DPOUT
DTMFOUT
BD
32kHz
AC
OUTPUT [
PORT
DIALPUSLE
OUTPUT
DTMFOUTPUT
BUZZER OUTPUT
32kHz OUTPUT
RESET
TEST
) POWER
HOOK SWITCH
OSCILLATION (
130
----------------------------------------~----------.
MSM6052 •
PIN DESCRIPTION
Designation
VDD
Function
Pource source
VSS
Circuit ground potential
AC
Terminal to clear internal logic, pulled down to VSS.
After power is turned on, the MSM6052 must be reset by this terminal.
TEST
Terminal to test internal logic, pulled down to VSS.
This terminal must be open in normal operation.
XT,XT
Input and output terminals of oscillator inverter.
3.58 MHz ceramic resonator is connected to these terminals.
HS
Input terminal connected to the hook switch, pulled up tp VDD.
DPOUT
Output terminal of dial pulse.
Dial pulse rate (10 pps or 20 pps) and Make Break ratio (40% or 33 %) can
be selected by software.
DTMFOUT
Output terminal of DTMF signal
BD
Output terminal of buzzer sound
32 kHz
Output terminal of 32 kHz clock
R,-R.
Rs-Rs
Input port pulled down to VSS.
1,-1.
Input port having clocked pull-down resistor to VSS.
Only when this port is accessed, pull-down resistors are connected to this
port.
C,-C.
0,-0.
Output port
10,-10.
Tri-state bidirectional port
10E
Output terminal
When 10, -104 is accessed, input completion signal (when read) or
load signal (when written) is output from 10E terminal.
131
e MSM6052 e'--------------------------------------------------
FUNCTIONAL DESCRIPTION
A block diagram of the MSM6052 is given on
page 129. Each block of logic will be briefly
discussed. For more information, please refer to
the MSM6052 user's manual.
Program ROM
The MSM6052 will address up to 2 K words
of internal mask programmable ROM. Each word
consists of 14-bits and all instructions are one
word. The instructions are routed to a
programmed logic array which generates the
signals necessary for control of logic.
Data RAM
Data is organized in 4-bit nibbles. Internal
data RAM consists of 640 nibbles.
All locations are addressed by 10-bit
address registers (AR " AR2), 2-bit bank register
(B), 4-bit page register (P) or a part of the
instruction's operand.
ALU
The ALU performs a 4-bit parallel operation
on RAM and ACC contents, or on RAM contents
and an immediate digit. It sets or resets the three
flags (Z, C, G) depending on the condition.
Program Counter (PC)
The program counter is an 11-bit wide
counter that specifies the address of program
ROM.
The PC is incremented by one at every
execution of the instruction, and then specifies
the next instruction to be executed. However, the
contents of the PC are rewritten by the execution
of a Jump, Call or Branch instruction.
As there is no boundary in the ROM, and a
Jump, Call or Branch instruction can be put
anywhere in the ROM.
Stack
The MSM6052 has a 5 level stack apart from
the data RAM. The contents of the PC are loaded
into stack when a Call instruction is executed or
an interrupt is generated. Nesting of subroutines
within subroutines can continue up to 4 times,
including the interrupt.
•
Input Port
Port (R1 - R4)
4-bit input port. Each pin of the port is pulled
down to VSS by an internal reSistor, and status
of the port is fetched by an input instruction.
Port (R5 - R8)
4-bit input port. Each pin of the port is pulled
down to VSS by an internal resistor, and the
status of the port is fetched by an input
instruction.
132
Port (I1 -14)
4-bit input port. Each pin of the port is pulled
down to VSS by an internal resistor and
'transistor. Only when it is desired to fetch status
of the port, input current flows through these
pins. Status of the port is fetched by an input
instruction.
• Output Port
Port (C1 - C4)
4-bit output port. These ports consist of data
latches and buffers, and the contents of the data
latches are rewritten by an output instruction.
Port (01 - 04)
4-bit output port. This port consists of data
latches and buffers, and the contents of the data
latches are rewritten by an output instruction.
Electrical characteristics of 03 and 04 are
different from those of 01 and 02. 03 and 04 of
the ports are used as XMIT MUTE and MUTE
normally.
Port (E01 - E04)
4-bit output port. This port consists of data
latches and buffers, and the contents of data
latches are rewritten by an output instruction.
• Input/Output Port
Port (I01 - 104)
4-bit bidirectional port. This port consists of
data latches, output buffers and input buffers.
The contents of the data latches are rewritten by
an output instruction, and status of the port is
fetched by an input instruction.
Address Registers (AR1, AR2)
The address registers are used to specify the
1O-bit address of data RAM, when a data search
instruction (ROAR) or block data transfer
instruction (MVAR) is executed.
This register is an up/down counter, and is
incremented or decremented by 1 with
execution of the instruction.
Timing Generator
By connecting a 3.58 MHz ceramic resonator
to the XT and XT terminal, the timing generator
generates a basic timing signal to control the
MSM6052 .
The MSM6052 can operate in 2 modes,
normal operating mode and power down mode.
STOP instruction is used to place the MSM6052
in the power down mode. The oscillation stops
and all functions are stopped. However, .the
contents of RAM and all registers are maintained.
--------------------------------------------------. MSM6052 •
Programmable Timer
The programmable timer consists of a 4-bit
down counter and a 1/100 prescaler.
Any of a 7990.1 Hz clock, 1997.5 Hz clock
and 998.8 Hz clock is input to the 1/100
prescaler. Output of the 1/100 pres caler
decrements the 4-bit down counter by 1 .
When the contents of the 4-bit down counter
is decremented to 0, the programmable timer
generates an interrupt.
This programmable timer can be used as a
dial pulse generator. The dial pulse rate (10 pps,
20 pps) and Make/Break ratio (40%, 33%) of the
dial pulsll which the programmable timer
generates are selectable.
DTMF Circuit
OTMF circuit is used to generate a OTMF
signal. 12 kinds of OTMF signal (0 to 9, #, *) can
be output by an output instruction.
BDCircuit
The BO circuit generates the square wave
which can be used as the confirmation sound,
warning sound and so on. 15 kinds of sound
(4.66 to 0.82 kHz) are output by an output
instruction specifying the frequency.
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Conditions
Limits
Unit
VOO
Ta = 25°C
-0.3 to 7.0
V
VI
Ta =25°C
-0.3 to VOO+0.3
V
Vo
Ta = 25°C
-0.3 to VOO+0.3
V
Tstg
-
-55 to 125
°C
Po
Ta = 25°C
200
mW
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature
Power Dissipation
OPERATING CONDITIONS
Parameter
Operating Voltage
Memory Retension
Voltage
Symbol
Limits
Unit
VOO
2.5 to 6.0
V
1.2to 6.0
V
-20 to 75
°C
VOOM
Operating Temperature
Topr
DC CHARACTERISTICS
(VOO = 3V, Ta = -20 to 75°C)
Limits
,
Parameter
"H" Input Voltage
Conditions
Symbol
VOO=3V
VIH
Unit
Min.
Typ.
Max.
2.2
-
-
V
-V
VOO=6V
4.4
-
-
VOO=3V
-
-
0.8
VOO=6V
-
-
1.6
V
VOH=2.6V
-200
-
-
p.,A
VOL=O.4V
500
-
-
p.,A
VOH=2.6V
-1
-
-
mA
V
"L" Input Voltage
VIL
"H" Output Current (1)
10Hl
"L" Output Current (1)
lOLl
"H" Output Current (2)
IOH2
"L" Output Current (2)
IOL2
VOL=O.4V
10
-
-
p.,A
"H" Output Current (3)
IOH3
VOH=2.6V
-20
-
-
p.,A
"L" Output Current(3)
IOL3
VOL=0.4V
10
-
-
p.,A
03,0.
OPOUT
C,-C,
0,,02, BO
133
• MSM6052 .------~--------~--------------------------------~
DC CHARACTERISTICS (CONT.)
Limits
Parameter
Symbol
"H" Output Current (4)
10H.
"L" Output Current (4)
IOL4
"H" Output Current (5)
10Hs
Conditions
10,- 10.
10E
EO , -E0 4
32 kHz
Unit
Min.
Typ.
Max.
VOH=2.6V
-150
-
-
/LA
VOL=O.4V
300
-
-
/LA
VOH=2.6V
-40
-
-
/LA
VOL=O.4V
25
-
-
/LA
"L" Output Current (5)
10Ls
Pull-up Resistance
RUp
HS
17
-
150
kO
Pull down
Resistance (1)
Rdwon 1
R,-Ra
33
-
300
kO
Pull down
Resistance (2)
Rdwon 2
1,-14, AC, TEST
10
100
kO
/LA
Input Leak Current
IlL
10,- 104
o :SVIN :SVOO
VOO= 2.5 to 6.0V
-
-
±2
Current
Consumption (1)
lOOp
OTMFoutput
off
VOO=3V
-
0.3
0.6
mA
VOO=6V
-
1.2
2.4
mA
Current
Consumption (2)
lOOT
OTMFoutput
on
VOO=3V
-
1.2
2.4
mA
VOO=6V
--
3.5
7.0
mA
ONHOOK
VOO=2.5V
Ta=25°C
-
0.01
0.2
/LA
-
2
/LA
Memory retention
Current
100M
Ta=-20t075°C
AC CHARACTERISTICS
(VOO = 3V, Ta = -20 to 75°C)
Limits
Parameter
,
Symbol
Conditions
Key Input Time
TKIN
VOO=2.5 to 6.0V
Tone Output Voltage
VOUT
Row only
RL =1 kO
Unit
Min.
Typ.
Max.
33
-
-
ms
VOO=2.5V
150
250
350
VOO=4.0V
200
350
570
VOO=6.0V
300
480
850
mV
rms
High/Low Level Ratio
dBCR
VOO=2.5 to 6.0V
1
2
3
dB
Oistortion Ratio
%OIS
RL=l kO
-
1
5
%
tTLHl
03,04, OP OUT
CL=50 pF
-
-
0.5
Rise/FaliTime (1)
tTHLl
tTLH2······
Rise/Fall Time (2)
tTHL2
Rise/Fall Time (3)
tTLH3
tTHL3
Rise/Fall Time (4)
tTLH4
tTHL4
134
-
0.5
C,-C4
CL=50 pF
-
-
0.5
-
-
10
0,,02, BO, 32 kHz
CL=50 pF
-
-
5
-
10
10,-104, 10E, EO, -.... E04
CL=50 pF
-
-
1
-
-
1
/LS
/LS
/LS
/LS
---------------------------------------------------.. MSM6052 •
DESCRIPTION OF INSTRUCTIONS
Instruction Code
Mnemonic
Operation
1312 11 110 19 1 8
7 6
5 14
3
21 1 1 0
ADD ACC,AP
0 0
ADD #D,AP
0
1 1 0 0
P
0 0
P 0
1 0
1
A
+ ACC
+D
AP +- (AP) + ACC + C
1 P 0
1 0
0
A
AP +- (AP) - ACC
A
AP +- (AP) - D
0 0
0
P 0
1 0
0
D
A
AP +- (AP)
A
AP +-(AP)
ADCAP
0
SUB ACC,AP
0 0
0
SUB #D,AP
0
1
1 0
SBCAP
0
0 0
0
1 P 0
1 0
1
A
AP +- (AP) - ACC - C
CMP ACC, AP
0 0 0
0
1 P 1
1 1 0
A
(AP) -ACC
1 0
1
1 P
A
(AP) -D
XOR ACC, AP
0 0 0
0
0
P 0
A
AP +- (AP) "'it ACC
XOR #D,AP
0
1 1
1
1
P
A
AP+-(AP)"'itD
BIT ACC,AP
0 0
A
(AP) V ACC
BIT #D,AP
0
A
(AP)VD
~
BISACC,AP
0 0
-
BIS#D,AP
0
()
·til
.Q
0 0
0
1:1
c:
-0
Q.c
()
<::
'x"
.<::
0
LAMM
n2
A-M,H-HVn,
39-3B
1
1
LAMD
mm
A-Md
10mm
2
2
LMAD
mm
Md-A
11mm
2
2
LMTD
mm
Md(w) - T (M(w), A), T =ROM table
19mm
2
3
LMCT
M(w)-CT
3E59
2
2
LCTM
CT-M(w)
3E51
2
2
LMSR
M(w)-SR
3E5A
2
2
LSRM
SR-M(w)
3E52
2
2
LTMM
TM-(M(w),A)
3E50
2
2
PUSH
ST -C, A, H, L, SP -SP-4
1C
1
3
POP
C, A, H, L -, ST SP -SP+4
1D
1
3
X
A~M
28
1
1
29-2B
1
1
XM
n,
A-M,H-HVn,
X+
A ~M,L-L+1,SkipifL=0
3C
1
1
X-
A~M,
2C
1
1
INA
A -A+1, Skip if A=O
30
1
1
1
1
L1J
-<:: <::
----E
L -L-1,SkipifL=F
Q)
Q)
E
Q)
~
0
Q)
o
~
INM
M-M+1,SkipifM=0
33
1
INL
L-L+1,SkipifL=0
31
1
Q)
ED
147
eMSM6404e------------------------------------------------INSTRUCTION LIST (Continued)
Mnemonic
Description
INH
H -H+1. Skip if M =0
Code
Byte
Cycle
32
1
1
12mm
2
2
c:III
INMD
~
DCA
A -A-1. Skip if A =F
34
1
1
:;:,
DCM
M-M-1.SkipifM =F
37
1
1
E
DCl
l -l-1.Skip ifL=F
35
1
1
"
DCH
H -H-1.SkipifH =F
36
1
1
13mm
2
2
E
"III
Cl
mm
Md -Md+1.SkipifMd =0
c:
III
~
.E
DCMD
E
:5
~
~
"'E
0.
Md -Md-1.SkipifMd =F
ADS
A - A+M. Skip if Cy =1
02
1
1
ADCS
A. C -A+M+C. Skip if Cy=1
01
1
1
ADC
A.C-A+M+C
03
1
1
3E4n
2
2
AIS
"
~
mm
n
A -A+n. Skip if Cy =1
DAA
A-A+6
06
1
1
DAS
A-A+10
OA
1
1
AND
A-AVM
00
1
1
OR
A-AVM
05
1
1
EOR
A-AVM
04
1
1
CMA
A-A
OB
1
1
CIA
A-A+1
OC
1
1
RAl
Rotate left with C
OE
1
1
RAR
Rotate Right with C
OF
1
1
TC
SkipifC=1
09
1
1
SC
C-1
07
1
1
RC
C-O
08
1
1
,
CAl
n
SkipifA=n
3EOn
2
2
CLI
n
Skipifl =n
3E2n
2
2
CPI
p. n
Skip if Pp=n
17pn
2
2
CMI
n
Skip if M =n
3E1n
2
2
SkipifA=M
16
1
1
0
0
CAM
TAB
n2
Skip if Abit (n2) =1
54-57
1
1
RAB
n2
Abit(n,)-O
64-67
1
1
III
SA8
n2
Abit(n,)-1
74-77
1
1
iii
TM8
n2
Skip if Mbit (n,) =1
58-5B
1
1
RMB
n2
Mbit(n,,)-O
68-68
1
1
c:
g
~
0.
0
148
- - - - - - - - - - - - - - - - - - - - - - - - - . MSM6404 •
INSTRUCTION LIST (Continued)
Mnemonic
Description
Code
Byte
Cycle
5MB
n
Mbit(n,)-l
78-7B
1
1
TFB
n2
Skip if Fbit (n,) =1
5C-5F
1
1
RFB
n2
Fbit(n,) -0
SC-SF
1
1
SFB
n2
Fbit(n,) -1
7C-7F
1
1
e
TPB
n2
Skip if Pbil (n,) ';'1
50-53
1
1
0
RPB
n2
Pbit(n,) -0
SO-S3
1
1
c:
0
CD
c.
iii
SPB
n
Pbit(n,)-l
TPBO
pn2
Skip if Ppbit (n,) =1
RPBO
pn2
SPBO
pn2
70-73
1
1
30pO-3
2
2
Ppbit (n,) =0
30p4-'
2
2
Ppbit (n,) =1
30pB-B
2
2
MEl
MEIF-1
3ESO
2
2
MOl
MEIF-O
3ES1
2
2
EITB
EITBF-1
30C9
2
2
EITM
EITMF-1
30CA
2
2
EICT
EICTF-1
30CB
2
2
EIEX
EIEXF-1
30C8
2
2
OITB
EITBF-O
30C5
2
2
OITM
EITMF-O
30CS
2
2
OICT
EICTF-O
30C7
2
2
OIEX
EIEXF-O
30C4
2
2
C.
::l
TITB
Skip If EITBF =1
30C1
2
2
.Sl
TITM
Skip If EITMF =1
30C2
2
2
TICT
Skip If EICTF =1
30C3
2
2
TIEX
Skip If EIEXF =1
30CO
2
2
TOEX
Skip If IROEX =1
3020
2
2
TOTB
Skip If IROTB =1
3000
2
2
TOTM
Skip If IROTM =1
3001
2
2
TOCT
Skip If IROCT =1
3002
2
2
TOSR
Skip If IROSR =1
3003
2
2
ROEX
IROEX-O
3024
2
2
ROTB
II~OTB-O
3004
2
2
ROTM
IROTM-O
3005
2
2
ROCT
IROCT-O
300S
2
2
ROSR
IROSR-O
3007
2
2
t:::
oS
149
• MSM6404 • - - - - : - - - - - - ' - - - - - - - - - - - - - - - - - -
INSTRUCTION LIST (Continued)
Mnemonic
E
'"
Description
Code
Byte
Cycle
ECT
CTF -1 (start)
3DBB
2
2
ESR
SRF -1 (start)
3DBA
2
2
DCT
CTF ..... O (stop)
3DB7
2
2
~ .~
..c:
Q)
~
(/)
li;
-.:
DSR
SRF -0 (stop)
3DB6
2
2
TCT
Skip If CTF =1
3DB3
2
2
TSR
Skip If SRF =1
3DB2
2
2
PC-a6
CO-FF
1
1
:::l
0
0
JCP
a6
JP
a'2
PC-a'2
4a'2
2
2
CZP
a
ST - PC+l , PC -2a,
SP-SP-4
Ba
1
4
CAL
a12
ST -PC+2, PC -a 12,
SP-SP-4
Aa'2
2
4
.c:
()
c
!Ii'"
IfI
:;
Q.
:;
S2
:;
Q.
E
E!
::Ja. c
OPT
Ps, P4 -T (M(w), A),
T=ROMtable
18
1
3
RT
PC -ST, SP -SP+4
IE
1
4
RTS
PC -ST, SP -SP+4,
Skip unconditional
IF
1
4
'JA
PC -(PC -A)+1
IA
1
1
JM
PC - (M(w), A)
IB
1
2
IP
A-P
20
1
1
IPD
A-Pp
3DpD
2
2
P-A
23
1
1
3DpC
2
2
P
OP
OPD
P
Pp-A
NOP
No Operation
00
1
1
HALT
HaltCPU
3DB8
2
2
STOP
Slop Clock
3DB9
2
2
08
150
----~----------------------------------------------.MSM6404.
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Symbol
Conditions
Voo
Input Voltage
VI
Output Voltage
Vo
Ta=25°C
Storage Temperature
Unit
-0.St07,
V
-O.Sto VOO
V
-O.StoVOO
V
200 max.
mW
Ta = 25°C per output
50 max.
mW
-
-55to+150
DC
Ta = 25°C per package
Power Dissipation
,
Limits
Po
Tstg
OPERATING RANGE
Parameter
Supply Voltage
Data-Hold Voltage
Operating Temperature
Symbol
Conditions
Limits
Unit
I(OSC) ~ 1 MHz
St06
V
V
VOO
I(OSC) :;;4.2 MHz
4.5t05.5
VOOH
I (OSC) =OHz
2t06
V
TOp
-
-40 to +S5
DC
MOSLoad
15
TIL Load
1
FanOut
N
-
DC CHARACTERISTICS
(Voo = 5V± 10%, Ta = -40 to +85°C)
Parameter
Symbol
Conditions
"H"lnput Voltage'1:2
VIH
"H"lnput Voltage'S;'4
VIH
"L"lnput Voltage
VIL
-
"H" Output Voltage'l :5
VOH
"L" Output Voltage'l
"L" Output Voltage'5
Min.
Typ.
Max.
Unit
2.4
-
VOO
V
S.6
-
VOO
V
-O.S
-
O.S
V
10="':15p.A
4.2
-
V
VOL
10=1.6mA
-'
0.4
V
VOL
10 = 15p.A
-
0.4
V
Input Current'S
IIH/IIL
VI=VOO/OV
-
15/-15
p.A
Input Current'2:4
1 I-SO
p.A
-
mA
-1.2
mA
IIH/IIL
VI=VOO/OV
-
"H" Output Current'l
10H
VO=2.4V
-0.1
"H" OutputCurrent'l
10H
VO= OAV
-
-
-
5
-
-
7
-
VOO=2V, no load
Ta=25°C
-
0.2
5
p.A
No load
-
1
100
p.A
Quarts oscillation
1=4 MHz, no load
-
6
12
mA
Input Capacity
CI
Output Capacity
Co
Current Dissipation
(when stop condition)
Current Dissipation
'1
'2
1=1 MHz
Ta=25°C
pF
IOOS
100
Applied to PO, Pl , PS, P4, P5, P6, P7 and PS
Applied to P2
's Applied to OSCo
'4
Applied to RESET
'5
Applied to OSC,
151
• MSM6404 . ' - - - - - - - - - - - - - - - - - - - - - - - - - -
AC CHARACTERISTICS
(VDD = 5V± 10%, Ta = -40° to +85°C)
Parameter
D
Symbol
Conditions
Min.
Typ.
Max.
Unit
Clock Pulse Width
Clock (OSC)
tq,W
-
Cycle Time
tCY
952
Input Data Setup Time
tDS
Input Data Hold Time
tDH
-
119
-
nS
120
-
Input Data, Input
Clock Pulse Width
tDW
-
SR Data Setup Time
tss
-
120
-
-
nS
120
-
SR Data Hold Time
tSH
-
-
-
-
nS
120
Data Delay Time
tDR
CL=15pF
tCy+300
nS
-
7/8tCy+300
nS
120
nS
nS
nS
nS
Data Delay Time at
Mode Switching
tDCR
CL = 15pF
-
Data Delay Time at
OPT Instruction
tDl1
CL = 15pF
-
-
6/8tCy+300
nS
Data Delay Time at
OPT Instruction
tDI2
CL = 15pF
-
-
7/8tCy+300
nS
CTITM Data Delay
Time using TBC Clock
tCT/tTT
CL = 15pF
-
-
2/8tCy+360
nS
SR/TM Data Delay
Time using PR Clock
tSR/tTR
CL = 15pF
-
-
tCy+480
nS
CT Data Delay Ti me
using PR Clock
tCR
CL= 15pF
-
-
1018 ICY + 480
nS
CT Data Delay Time
using External Clock
tcp
CL = 15pF
-
-
2/8tCY+360
nS
SR/TM Data Delay
Time using External
Clock
tSp/tTP
CL =50pF
-
-
360
nS
tSINH
-
2/8tCY
-
nS
tliNH
-
1/8tCY
-
nS
SR Clock Invalid Time
INT Invalid Time
152
-
J
----------------------------------------------------'. MSM6404.
TIMING CHARTS
Output Condition
OSC O
PO,P"P,
p.,p"p,
P" p.
0,1,3
PA=4,5,6
7 or 8
POI
Po,
Pl l
PA = 9 or A
p.
OPT INST.
Ps
OPT INST.
POI
Pl l
Po,
Pl l
TBC clock
0Vi/ifi--rL
~I.------------t-DR--------------------------~---~~~-------r-------------tD-C-R-------------~~--------I·
,~-----------tD-I-1----------J--------------.
-------------t-D-12----------------~J~------
I'.
CT
TM
POI clock' SR
P 12 clock' TM
P ,O clock' CT
:
tCT
tTT
d
~tSR~~~
l
~1·========tctcRR========~~
tTR
CT
-tcpSR
TM
-----
~
tsp
I---
tTP ~
, Output Data to port will be clock for SR, TM or CT.
153
.MSM6404.,----------------------~------------~--------------
Input Condition
1MC
asc
O
PO.PI.p,
p,.p •• p,
P6 .P 7 .P,
SR clock
TM clock
- - tow I---
1,---,
j
POI
SR clock
INPUT
I'- DATA
tss
tSH
1MC
asc
O
ts INH
ts INH: Po1 (SR clock) INH period during LMSRINST.
(Note: POI is used for clock of SR)
tIINH: P,o (interrupt) INH period during RPBand RPBD INST.
154
- - - - - - - - - - - - - - - - - - - - - - - - - - . MSM6404 •
TYP. Current vs Voltage for High State Output
(I0H)
(YO H)
TYP. Current vs. Voltage for Low State Output
(loll
(VOL)
(Ta = 25°C)
-1.0
20
6V /
-0.9
-
-0.8
-0.7
-0.6
~
E
-0.5
:c -0.4
.P
18
r-- I-..
-0.3
-0.2
I
-0.1
"""
Nv
r-...
0
2
'"
~
'"
\
...J
.P
\
\
12
E
1\
'i
\
'\
3
14
Voo = 6V
'
"
'"
4V
~
I
III
[I
f/
16
I---..
\
\
4
\
5
10
If
6
'/ . / I-- 3V
4
fL
0
2
U
en
9-
(Ta
10
10
6
7
9
10
/
8
........
r-
N
7
~
6
:c
-
U
en
Q
5
V
4
3
3
2
2
0
20
Ta
(OC)
40
60
80
100
/
5
4
-20
8
= 25°C. CL = 15 pF)
~oo=5V
6
-40
5
9
r-....
...............
o
4
TYP. Maximum Oscillator Frequency vs.
f(OSC)
Supply Voltage
(YOD)
11
""
3
VOL (V)
11
7
4V
8
(CL = 15 pF)
N
:c
~
",... ~
7
TYP. Maximum Oscillator Frequency vs
f(OSC)
Temperature
(Ta)
8
5V
I---Voo
2
6
VOH (V)
9
/'
0
/
/
/
2345678
Voo (V)
155
e MSM6404
e-------------------.,..-------TVP.Supply Current YS. Supply Voltage
ODD)
(VDD)
(Ta=25°C)
No Load
10m
1 (OSC)=4MHz::
.#'
-
V
1m
2JHZ
~
1JHZ
500kHz
~
100kHz
100!,
/'
i-- OHz
,.....
lOOn
o
2
3
4
5
6
VOO(V)
156
7
8
9
10
OKI
semiconductor
MSM6404VS
MSM6404 PIGGY BACK
GENERAL DESCRIPTION
The MSM6404VS is a device whose built-in ROM is replaced by external EPROM using the piggyback method.
FEATURES
•
Supply Voltage: 5V
± 5%
• Frequency: DC - 4.2 MHz
• Operating Temperature: 0 - 70°C
Note: There are a few differences in the electrical characteristics of this chip and the evaluation chip.
Please refer to next page for the detail.
PUTTING METHOD OF ROM
Please refer to drawing below.
M6404VS
OKI
JAPAN4X30
PIN CONFIGURATION
Pin Connection between MSM6404 VS and EPROM
Vee
A12
All
10
9
8
7
To AO - A 12
of MSM6404VS
11
'Y
ADDRESS
6
5
4
3
2
1
AO
DO
1
.2
ToDl0 -D7
of MSM6404VS
11
'Y
NoIe: When putting 2732A,
pin 1,2,27, 28 are not used.
-
-
_vPP
A12
A7
A6
A5
A4
A3
A2
Al
AO
00
01
02
GND
1"""'-'""28
2
27
3
26
4
25
5
24
6
23
7276422
8
21
9
20
10
19
11
18
12
17
13
16
14
15
Vcc_
PGMN.C.A8A9
All
~~O-'
CE
g~::::=.-0504-
1
03
DATA
3
4
5
6
07
GND
157
• MSM6404VS
.--------------------~--------------r_--~--------
DIFFERENCES BETWEEN MSM6404 AND MSM6404VS (PIGGY-BACK)
Item
6404
6404VS (Piggy-Back)
1. Port
in itialization
during reset
Port PO, 1,3 are set to "1 " and port
2,4,5,6,7,8 are reset to "0"
directly by signal put into the
RESET..
Port PO, 1,3 are set to "1" and port 2,
4,5,6,7,8 are reset to "0" during reset
cycle being executed.
2. Timer
Operation
After being reset, timer stops
counting until data are set in it.
It is undecidable whether the timer
starts counting or not after being reset.
Therefore, the timer should be
initialized by software.
3. Shift registor
Serial Out F/F (SOF/F) is set to "0"
after being reset.
It is undecidable whether Serial Out
F/F (SOF/F) is set to "0" or "1" after
being reset. Therefore Serial Out F/F
should be initialized by software.
Internal clock ~
Internal clock
4. Port
input/output
timing
JlIL
t
r
Data are input
at this moment
Data are input
at this moment
Synchronized
with falling edge
Internal clock
Internal clock ~
~
~
k=
Data are output
at this moment
Data are output
at this moment
5. Port
input/output
(maracteristics)
TTL FO=1
(lOL = 1.6 rnA O.4V)
LSTTL FO=1
(lOL = 0.4 rnA O.4V)
VDDVDD
VDD
4-
P20-3
P20-3
TTL compatible input
POO-P83
~
(Except P20-3)
~
CMOS input
POO-83
o-----t>-
(Except P20-3)
Available
ROM capacity
4K byte
Accessible up to 8K byte
IPLcall
instruction
Not available
Available
,
158
OKI
semiconductor
MSM6408
HIGH-SPEED 4-BIT SINGLE CHIP MICROCONTROLLER
GENERAL DESCRIPTION
The OKI MSM6408 microcontroller is a low power, high-performance single-chip device
implemented in complementary metal oxide semiconductor technology. 64K bits of mask program
ROM, 1024 bits of data RAM, 36 Input/Output lines, a programmable timer/event-counter, and
oscillator are integrated onto one chip. Program memory is byte wide and data-paths are organized in
4-bit nibbles. RAM and I/O lines are bit addressable. 122 instructions include binary, BCD
operations; bit set, reset, test; 8-bit I/O; relative jumps; multifunctional instructional (increment,
modify, skip) 8-bit wide table output; subroutine call and return.
FEATURES
• 8000 x 8 MASK ROM
An evaluation board is available for up to 8K
x 8.
• 256 x 4 RAM (including the stack area)
• 9 x 4 Ports, 36 I/O lines
4 lines for input ports having a latch, and the
other 32 lines for bit operation are available.
• Three built-in counters
1 2-bit time-base counter
12-bit programmable timer
8-bit high-speed programmable timer/event
counter
• Built-in 8-bit serial I/O register (with 3-bit
counter)
• Five interrupts with five priority levels
(4 internal,1 external)
• 32 stack levels (in RAM)
• Power down features
• Instruction execution time
1.0 P.s 4.0 MHz clock
• Instruction systems suitable for control
• 1 22 instructions
• Mask option
P60-63 for input port
• Full static operation
• Low power consumption
TYP 0.4p.W at VDD=2V
TYP 5p.W at VDD=5V OHz clock
• 5V single power supply, 42-pin DIP or
44-pin FLAT
BLOCK DIAGRAM
3210
3210 3210 3210 3210
3210_3UO 3210
INTO
L;!I, lLsoSCK
TCK
eTa eLK
LSI
159
.MSM6408·------------------------------------~--------~
PIN CONFIGURATION
(Top View) 42-pin Plastic DIP
44 Pin Plastic Flat Package
_
0
~ it" l'" :. :.
0",,,,
0 ....
>
0.
0.
"
if if If
0
0
P31
P32
Pe2
P33
P60
oseo
P60
NC
OSC,
P73
P73
P72
P72
TEST
P71
P20
P83
P82
P21
P22
P23
POO
POl
P02
P71
P20
P90
P21
P83
P22
P82
P23
Pel
P13
P12
P03
Pll
Pl0
80. ~ It
'" It" oz "z 0:0 0: ii:'" "r. Ii:0.
"
PIN DESCRIPTION
Pin name
Input/~utput
po~
Function
When reset
Input/output
4-bit input/output port.
P01 to P03 are also used as serial interface
terminals.
111 "
P10/CIN
P11/TMO
P12/TCK
P13
Input/output
4-bit input port with latch.
Built-in pull up register for all bit input.
"1 "
P20/INT
P21
P22
P23
Input
4-billnput port with a latch. P20 is shared with INT
input. (l7all trigger input) P21 - 23 are levei in!lut.
Built-in pull up register for all bit input.
P30-33
Input/output
4-bit input/output port
"1 It
P40-43
Input/output
4-bit input/output port
"0"
P50-53
Input/output
4-bit input/output port
P60-63
Input/output
4-bit input/output port'1
"orr
P70-73
Input/output
4-bit input/output port
"0"
PSO-S3
Input/output
4-bit input/output port
110"
OSCo
OSC,
Input/output
X'tal connection terminal for system clock oscillation
Oscillation
wave
TEST
Output
(Test terminal for Maker)
Pulse output
RESET
Input
,System reset input terminal
P01/SCK
P02/S0
P03/SI
VDD
GND
I'S-bit output port
Power source voltage supply
Note: When each port is used for output, it is possible to drive one TTL (one input).
*1· Can be made as a port dedicated to input (mask option).
160
The latch is
reSet.
"0"
- - - - - - - - - - - - - - - - - - - - - - - - - - . MSM6408 •
INSTRUCTION LIST
Mnemonic
0.
0
CL
.,
.If:
::l
CL
-ti
Descri ption
8yte
Cycle
LAI
n
A-n
9n
1
1
LLI
n
L-n
8n
1
1
LHLI
nn
HL-nn
15nn
2
2
LMI
nn
M(w)-nn
14nn
2
2
LAL
A-L
21
1
1
LLA
L-A
2D
1
1
LAH
A-H
22
1
1
LHA
H-A
2E
1
1
LAM
A-M
38
1
1
LMA
M-A
2F
1
1
LAM+
A -M, L -L+1, Skip if L=O
24
1
1
LAM-
A -M, L -L-1, SkipifL=F
25
1
1
LMA+
M -A, L -L+1, Skip if L=O
26
1
1
LMA-
01
0
Code
27
1
1
LAMM
n,
M -A, L -L-1, Skip ifL=F
A-M,H-HVn,
39-38
1
1
LAMD
mm
A-Md
10mm
2
2
LMAD
mm
Md-A
11mm
2
2
LMTD
mm
-'
Md(w) - T (M(w), A), T =ROM table
19mm
2
3
LMCT
M(w)-CT
3E59
2
2
LCTM
CT-M(w)
3E51
2
2
LMSR
M(w)-SR
3E5A
2
2
LSRM
SR-M(w)
3E52
2
2
LTMM
TM - (M(w), A)
3E50
2
2
PUSH
ST -C, A, H, L, SP -SP-4
1C
1
3
POP
C, A, H, L, -ST SP -SP+4
1D
1
3
28
1
1
29-28
1
1
A-M
X
Q)
Cl
c
01
XM
n,
A-M,H-HVn,
.s:::
0
><
w
X+
A-M, L-L+1,SkipifL,:",0
3C
1
1
X-
A-M, L-L-1,SkipifL=F
2C
1
1
1
----
INA
A -A+1, Skip if A=O
30
1
E
Q)
INM
A -M+l, Skip if M=O
33
1
1
INL
L -L+1, Skip ifL =0
31
1
1
c
C Q)
Q) E
~
Q)
~
0
OQ)
Eo
161
• MSM6408 • - - - - - - - - - - - - - - - - - - - - - - - - - -
INSTRUCTION LIST (Continued)
Mnemonic
Description
INH
C
Q)
INMD
H -H+1, Skip if M =0
mm
Md -Md+1,Skip ifMd =0
Code
Byte,
Cycle
32
1
1
12mm
2
2
E
~
0
DCA
A-A-1, Skip if A =F
34
1
1
Q)
Cl
:;:,
c
Q)
E
DCM
M-M-1,SkipifM=F
37
1
1
DCl
L - l -1 , Skip if l = F
35
1
1
DCH
H -H-1, Skip if H =F
36
1
1
~
0
E
DCMD
0
Md!-Md-1, Skip if Md = F
13mm
2
2
A -A+M, Skip ifCy =1
02
1
1
ADCS
A, C -A+M+C, Skip ifCy=l
01
1
1
ADC
A,C-A+M+C
03
1
1
AIS
~
mm
ADS
3E4n
2
2
DAA
n
A -A+n, Skip ifCy =1
A-A+6
06
1
1
DAS
A-A+10
OA
1
1
AND
A-AVM
OD
1
1
E
OR
A-AVM
05
1
1
~
EOR
A-AVM
04
1
1
CMA
A-A
OB
1
1
CIA
A-A+1
OC
1
1
RAl
Rotate left with C
OE
1
1
RAR
Rotate Right with C
OF
1
1
TC
SkipifC =1
09
1
1
SC
C-1
07
1
1
:::
RC
~
'"
c.
E
C-O
08
1
1
CAl
n
Skipif A =n
3EOn
2
2
CLI
n
Skip ifl =n
3E2n
2
2
CPI
p,n
Skip ifPp=n
17pn
2
2
CMI
n
SkipifM =n
3E1n
2
2
SkipifA=M'
16
1
1
0
()
CAM
c
0
~
Q)
g
iii
162
TAB
n2
Skip if Abit (n,) =1
54-57
1
1
RAB
n2
Abit(n2) -0
64-67
1
1
SAB
n2
Abit(n,) -1
74-77
1
1
TMB
n2
Skip if Mbit (n,) =1
58-5B
1
1
RMB
n2
Mbit (n,)-O
68-6B
1
1
- - - - - - - - - - - - - - - - - - - - - - - - - . MSM6408 •
INSTRUCTION LIST (Continued)
Mnemonic
Description
Code
Byte
Cycle
5MB
n
Mbit(n,)-1
78-7B
1
1
TFB
n,
Skip if Fbit (n,) =1
5C-5F
1
1
RFB
n,
Fbit (n,)-O
SC-SF
1
1
c:
SFB
n,
Fbit(n,)-1
7C-7F
1
1
~
TPB
n,
Skip if Pbit (n ,) =1
50-53
1
1
RPB
n,
Pbit (n,)-O
SO-S3
1
1
0
Q)
00
iii
SPB
n
70-73
1
1
TPBO
pn,
Skip if Ppbit (n,) =1
30pO-3
2
2
RPBO
pn,
Ppbit (n,) =0
30p4-7
2
2
SPBO
pn,
Ppbit (n ,) =1
3Dps-B
2
2
. Pbit(n,)-1
MEl
MEIF-1
3ESO
2
2
MOl
MEIF-O
3ES1
2
2
EITB
EITBF-1
30C9
2
2
EITM
EITMF-1
30CA
2
2
EICT
EICTF-1
30CB
2
2
EIEX
EIEXF-1
30C8
2
2
OITB
EITBF-O
30C5
2
2
OITM
EITMF-O
30CS
2
2
OICT
EICTF-O
30C7
2
2
OIEX
EIEXF-O
30C4
2
2
TITB
Skip If EITBF =1
30C1
2
2
0.
2
TITM
Skip 11 EITMF =1
30C2
2
2
E
TICT
Skip 11 EICTF =1
30C3
2
2
TIEX
Skip 11 EIEXF =1
30CO
2
2
TOE X
Skip 11 IROEX =1
3020
2
2
TOTB
Skip If IROTB =1
3000
2
2
TOTM
Skip 11 IROTM =1
3001
2
2
TOCT
Skip If IROCT =1
3002
2
2
TOSR
Skip If IROSR =1
30D3
2
2
ROEX
IROEX-O
3024
2
2
ROTB
IROTB-O
3004
2
2
~
ROTM
IROTM-O
3005
2
2
ROCT
IROCT-O
300S
2
2
ROSR
IROSR -0
3007
2
2
163
• MSM6408 • - - - - - . . , . . - - - - - - - - - - - - - - - - - - - -
INSTRUCTION LIST (Continued)
Mnemonic
Description
Code
Byte
Cycle
3DBB
2
2
3DBA
2
2
ECT
CTF -1 (start)
ESR
SRF -1 (start)
DCT
CTF -0 (stop)
3DB7
2
2
...
DSR
SRF -0 (stop)
3DB6
2
2
::J
TCT
Skip If CTF =1
3DB3
2
2
TSR
Skip IfSRF =1
3DB2
2
2
5
=:!2
.- .,
\
.r:.G)
en ...
.!
<:
0
0
JCP
a.
PC-a.
CO-FF
1
1
JP
a,_
PC-a,_
4a,_
2
2
LJP
a,.
PC-a,.
3F
3
4
CZP
a
ST -PC+1, PC -2a,
SP-SP-4
Ba
1
4
CAL
a,_
ST -PC+2, PC -a, ..
SP-SP-4
Aa,.
2
4
RT
PC -ST, SP -SP+4
IE
1
4
RTS
PC -ST, SP -SP+4,
Skip unconditional
IF
1
4
JA
PC -(PC -A)+1
IA
1
1
JM
PC - (M(w), A)
IB
1
2
IP
A-P
20
1
1
A-Pp
3DpD
2
2
P-A
23
1
1
3DpC
2
2
00
1
1
.r:.
"<:
~
ID
:;
c.
:;
0
:;:,
::J
C.
IPD
P
OP
.5
OPD
e
fs8
::::l-
164
P
Pp-A
NOP
No Operation
HALT
Halt CPU
3DB8
2
2
STOP
Stop Clock
3DB~
2
2
- - - - - - - - - - - - - - - - - - - - - - - - - . MSM6408 •
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Symbol
Conditions
VDD
Input Voltage
VI
Output Voltage
Vo
Ta =25°C
Ta = 25°C per package
Power Dissipation
Unit
V
-0.3toVDD
V
-0.3toVDD
V
200 max.
mW
PD
Ta = 25°C per output
Storage Temperature
Limits
-0.3t07
50 max.
mW
Tstg
-
-55 to +150
°C
Symbol
Conditions
Limits
Unit
f(OSC);;;1 MHz
3t06
V
f(OSC) ;;; 4.0 MHz
4.5to 5.5
V
f (OSC) =0 Hz
2t06
V
°C
OPERATING RANGE
Parameter
Supply Voltage
Data-Hold Voltage
Operating Temperature
VDD
VDDH
TOp
Fan Out
N
-
-40to +85
MOSLoad
15
TTL Load
1
-
DC CHARACTERISTICS
(Voo = 5V±1 0%, Ta = -40 to +85°C)
Parameter
Typ.
Max.
Unit
2.4
-
VDD
V
3.6
.-
VDO
V
-0.3
-
0.8
V
10=-15/LA
4.2
-
-
V
0.4
V
0.4
V
15/-15
/LA
-
1/-30
/LA
-
-
mA
-1.2
rnA
Symbol
Conditions
"H" Input Voltage '1,*2
VIH
-
"H" Input Voltage '3,*4
VIH
-
"L" Input Voltage
VIL
-
"H" Output Voltage'1,*5
VOH
Min.
"L" Output Voltage"
VOL
10 =1.6mA
-
"L" Output Voltage '5
VOL
10 = 15/LA
Input Current'3
IIH/IIL
VI =VDD/OV
Input Current'2, '4
IIH/IIL
VI =VDD/OV
-
"H" Output Current'1
10H
VO=2.4V
-0.1
"H" Output Current'1
10H
VO=0.4V
-
Input Capacity
CI
Output Capacity
Co
Current Dissipation
(when stop condition)
Current Dissipation
'1
'2
f=1MHz
Ta=25°C
5
pF
-
7
-
VDD=2V, no load
Ta=25°C
-
0.2
5
/LA
No load
-
1
100
/LA
-
6
12
rnA
IDDS
IDD
Applied to PO, P1 , P3, P4, P5, P6, P7 and P8
Applied to P2
'3 AppliedtoOSCo
Quarts oscillation
f=4 MHz, no load
'4
I
Applied to RESET
'5
Applied to OSC 1
165
•
MSM~408
•
--------'-----c-------------------
AC CHARACTERISTICS
(Voo = 5V±1 0%, Ta = -40 to +85°C)
Symbol
Conditions
Min.
Typ.
Max.
Unit
Clock Pulse Width
Clock (OSC)
Parameter
tW
-
125
-
-
nS
Cycle Time
tCY
1
-
-
/LS
tDS
-
120
-
-
nS
Input Data Hold Time
tDH
-
120
-
-
nS
In put Data, In put
Clock Pulse Width
tDW
-
120
-
-
nS
SR Data Setup Time
tss
-
120
-
-
nS
tSH
-
120
-
-
nS
tDR
CL = 15pF
-
-
tCY +300
nS
tDCR
CL = 15pF
-
-
7/8tCy+300
nS
CT ITM Data Delay
Time using TBC Clock
tCT/tn
CL = 15pF
-
-
2/8tCY +360
nS
SR/TM Data Delay
Time using PR Clock
tSR/tTR
CL = 15pF
-
-
ICY +480
nS
CT Data DelayTime
using PR Clock
tCR
CL=15pF
-
-
1018 tCY + 480
nS
CT Data Delay Ti me
using External Clock
tcp
CL = 15pF
-
-
'2/8tCY +360
nS
SR/TM Data Delay
Time using External
Clock
tSp/tTP
CL =50pF
-
-
360
nS
2/8tCY
-
-
nS
Input Data Setup Time
SR Data Hold Time
Data Delay Ti me
Data Delay Time at
Mode Switching
SR Clock Invalid Time
INT Invalid Time
166
tSINH
tliNH
_.
118 tCY
nS
- - - - - - - - - - - - - - - - - - - - - - - - - • MSM6408 •
TIMING CHARTS
Output Condition
OSC O
Po, PI' p.
p.,ps'p.
P" p.
0,1,3
PA=4,5,6
7 or 8
PA = 9 or A
TBC clock
W\Jiii-rL
~I,------------t-D-R~~~~~~~~~~~~~~~~~~----~1,----------tD-CR----------f~-------
CT
TM
POI clock' SR
P 12 clock' TM
P IO clock" CT
~.======~~tCR~=======~
I
PIO ' POI' P 12 EXT clock
CT
I----tcP-SR
TM
--
tsp
tTP
I--I-.. Output Data to port will be clock for SR, TM or CT.
167
• MSM6408 . - - - - - - - - - - - - - - - - - - - - - - - - - -
Input Condition
lMC
asc
O
--------~i~J~:1f~------------------
PO,PI,P,
p"p.,p,
p.,p"p.
SR clock
TM clock
o
-tDW-
1\
POI
I
SRclock
INPUT
~ DATA
tss
tSH
lMC
asc O
ts INH
ts INH: POI (SR clock) INH period during LMSR INST.
(Note: POI is used for clock of SR)
tIINH:
168
p,. (interrupt) INH period during RPBand RPBD INST.
- - - - - - - - - - - - - - - - - - - - - - - - - - . MSM6408 •
TYP. Current YS Voltage for High State Output
(lOH)
(VOH)
TYP. Current ys. Voltage for Low State Output
(lOL)
(VOL)
(Ta = 25° C)
(Ta = 25°C)
-1.0
6V
-0.9
18
-
-0.8
-0.7
-......
-0.6
~
r--0.5
E
I
.9
I
I
III
20
-0.4
16
- "'"
~V
'"
r-- ......., 4V ~
-0.3
-0.2
I
-0.1
0
~
E
...J
.9
\
\
I'\.
2
3
.~
\
\
4
5
II
8
/'
'J
4
\
~ 4V
'/
10
6
\
\
rl .,...
12
~
"'"
~
14
VDD = 6V
5V
f..-VPD
/
-
3V
2
6
7
0
VOH (V)
2
3
4
5
6
7
8
9
10
VOL (V)
TYP. Maximum Oscillator Frequency YS
f(OSC)
Temperature
(Ta)
TYP. Maximum Oscillator Frequency vs.
f(OSC)
Supply Voltage
(VOO)
(CL = 15 pF)
(Ta = 25°C. CL = 15 pF)
11
11
10
10
9
8
N
7
~
6
"'"
9
r-....
2
/
~DD=5V
........
I
G
en
V
8
N
-...........
7
/
I
r--....
~
6
G
en
2
5
4
4
3
3
2
2
o
-40
-20
0
20
Ta (OC)
40
60
80
100
/
5
0
V
/
2345678
VDD (V)
169
01
OKI
semiconductor
MSM6411
CMOS 4-BIT SINGLE CHIP MICROCONTROLLER
GENERAL DESCRIPTION
The OKI MSM6411 microcontroller is a low-power, high-performance single-chip device
implemented in complementary metal oxide semiconductor technology. 1024 x 8 bits of program
ROM, 32 x 4 bits of data RAM, 11 Input/Output lines and oscillator. Program memory is byte wide
and data paths are organized as 4-bit wide. 63 instructions include binary, logical operations; bit set,
reset, test; multifunctional.
FEATURES
•
•
•
•
•
•
•
D
1024 x 8 Internal ROM
32 x 4 Internal RAM
11 110 Lines (8 I/O Lines, 3 Input Lines)
8-bit serial I/O Register
2 Interrupt Levels
8 Stack Levels
952 ns 4.2MHz (VOO 5V±1 0%)
• 63 Instructions
• Self-Contained Oscillator
• -40 to +85°C Oper.ating Temperature
• 3 to 6V Operating VOO
• Low Power Consumption 5 f.LW Typical
(STOP, VOO = 5V, no load)
• Mask Option Crystal/Ceramic
Oscillator
FUNCTIONAL BLOCK DIAGRAM
ROM
INST.
DEC.
INT
$ISO
SCK
170
RESET
1024
OSCo
osc.
x8
ff
VODGND
----------------------------------------------------. MSM6411 •
PIN CONFIGURATION
LOGIC SYMBOL
(Top View)
16 PIN PLASTIC DIP (RS)
5V
OV
RESET
CLOCK
2
P2
PIN DESCRIPTION
Designation
POO
P01/SCK
P02/S0
P03/SI
P10
P11
P12
P13
Input/Output
Pin No.
Function
Input/Output
10
11
12
13
4 Bits I/O port.
poi to P03 are used both I/O
port and terminal of shift resister
Input/Output
14
15
1
2
4 Bits I/O port
Reset
"1 "
"1 "
P20/INT
P21
P22
Input
3
4
5
3 Bits input port with latch.
Latch is reset.
("0")
P20 is used as both input port and
input terminal of INT (input of
falling edge trigger).
OSCo
Input
7.
Input terminal of system clock.
Oscillation circuit consists of
OSCo and OSCI.
OSC,
Output
6
Oscillation circuit consists of
OSCo and OSCI.
RESET
Input
,.9
Input terminal of system reset
VDD
GND
Input
16
Main power source and circuit
GND potential.
8
Clock pulse In
171
• MSM6411 .---------------------------------------------------
FUNCTIONAL DESCRIPTION
ROM
ROM is organized in 1024 words by 8 bits. It
is used to stored developed application
programs (instructions). It is addressed by the
program counter (PC).
PC
The PC consists of a 10-bit binary counter
and is used to address ROM.
Stack and Stack Pointer
An interrupt or CAL instruction causes. the
contents of the PC to be saved in the stack. The
PC is restored from the stack by RT instruction.
All RAM locations (up to 8 levels) are
available as the stack. Note that four words of
RAM are used for each level.
The stack pOinter is a S-bit up-down counter
that points to the address of the next stack to be
used. It allows the RAM locations to be used as a
push-down stack.
RAM
RAM consists of up to 32 words 4 bits wide. It
is addressed by the H- and L-registers or by the
contents of the second byte of an instruction.
L-REGISTER
A 4-bit register which specifies RAM
locations A3-AO.
H-REGISTER
A 1-bit register which specifies RAM location
A4.
172
ALU
A 4-bit logic circuit that provides arithmetic
and logical operations.
ACC
Consisting of a 4-bit register, the
accumulator holds the result of operations or the
data present on ports.
CFLAG
The flag that holds a carry generated from the
result of operations.
INPUT/OUTPUT Ports (2 x 4 bit)
Organized into 4 bits, 2 ports are provided for
effecting and controlling data transfer to and
from an external source. The ports are selected
by codes included in instructions.
Input Ports (1 x 4 bit)
Contained port 2 (P2), which is an input port
with latching function. P20 is set at falling edge
of the input signal P21 and P22 are set at "0"
level inputs. Also, P20 is used as an interrupt
request flag. When P20 is set and an interrupt
operation occurs, it is automatically reset.
TIMING CONTROL (TC)
A 0 level on the RESET pin for longer than 2
machine cycles initializes the internal circuitry.
Clock pulses are supplied to the XT pin from
an external source. Also, by mask-option, it
organizes a circuit of oscillation with P20 and
produces clock pulses (by connecting externally
to crystal, ceramic or CR).
--------------------------------------------------. MSM6411 •
INSTRUCTION LIST
Mnemonic
Description
\
Code
Byte
Cycle
LAI
n
A-n
90-9F
1
1
LLI
n
L-n
80-8F
1
1
LHLI
nn
HL-nn
15nn
2
2
LAL
A-L
21
1
1
LLA
L-A
20
1
1
LAM
A-M
38
1
1
='
0..
LMA
M-A
2F
1
1
"ti
ca
LAMD
mm
A-Md
10mm
2
2
LMAD
mm
Md-A
11mm
2
2
LMSR
M(w)-SR
3E5A
2
2
LSRM
SR--M(w)
3E52
2
2
PUSH
ST-G,A, H, L, SP-SP-1
1C
1
3
POP
C,A,H,L-ST, SP-SP+1
10
1
3
0.
~
£
rn
.3
....='
.... 0.
IPD
P
A-Pp
3DpD
2
2
c.=,
.50
OPD
p
Pp-A
3DpC
2
2
=' ....
ADS
A- A+M, SKIP IF Cy = "1 "
02
1
1
ADC
C,A-C+A+M
03
1
1
3E4n
2
2
AIS
0
~
E
.s::
='=
<
.
.
n
A -A+n, SKIP IFCy= "1"
DAS
A-A+10
OA
1
1
AND
A-AAM
00
1
1
EOR
A-A¥M
04
1
1
CMA
A-A
OB
1
1
CAM
SKIPIFA= M
16
1
1.
SC
C~u1"
07
1
1
RC
C+-HO"
08
1
1
TC
SKIP IFC = "1"
09
1
1
RAL
CC -
OE
1
1
X
A+---+M
28
1
1
INL
L - L+1, SKIP IF L = "0"
31
1
1
INH
H - H+1, SKIP IF H = "0"
32
1
1
INM
M-M+1,SKIP IFM ="0"
33
1
1
r--A--.
3 :<-2-1- 0 i
_CI
, c:
~1i
........
... c
cCD
CDE
E
Q)
CD ...
"0
°CD
.50
173
eMSM6411
e.----------------------------------------------------
INSTRUCTION LIST (CONT.)
...
Mnemonic
,"'c...
CQ)
Q)E
EQ)
Q) .....
..... u
UQ)
INMO
Oescription
mm
Md - Md+1, SKIP IF Md = "0"
Code
Byte
Cycle
12mm
2
2
OCl
l-l-1, SKIP IF l= "F"
35.
1
1
OCH
H-H-1
36
1
1
OCM
M -M-1, SKIP IF M = "F"
37
1
1
':0
TAB
n2
SKIPIF [A bit n2J = "1 "
54-57
1
1
TMB
n2
SKIP IF [M bit n2) = "1 "
58-5B
1
1
0
RMB
n2
[M bit n2) - "0"
68-6B
1
1
~
5MB
n2
[M bit n2) - "1 "
78-7B
1
1
TPBO
p, n2
SKIP IF [Pp bit n2)
30 pO-3
2
2
RPBO
p, n2
[Pp bit n2) - "0"
30 p4-7
2
2
SPBO
p, n2
[Pp bit n2) -"1 "
30 p8-B
2
2
JCP
a6
PC-a6
CO-FF
1
1
,c
U
C
JP
a10
PC -a10
40
00
- 43FF
2
2
co
CAL
a10
ST - PC+2, PC -a1 0,
SP-SP-1
AO A3
OO-FF
2
4
1E
1
4
C
~
Co
...
iii
0
~
= "1"
RT
PC - ST, SP - SP+1
MEl
MEIF-"1"
3E60
2
2
MOl
MEIF-"O"
3E61
2
2
EICT
EICTF-"1"
30CB
2
2
EIEX
EIEXF-"1"
30C8
2
2
OICT
EICTF-"O"
30C7
2
2
a.;:
OIEX
EIEXF-"O"
30C4
2
2
lii
'E
TlCT
SKIP IF EICTF = "1 "
30C3
2
2
TIEX
SKIP IF EIEXF = "1 "
30CO
2
2
TQEX
SKIP IF IRQEX = "1 "
3020
2
2
TQSR
SKIP IF IRQSR = "1 "
3003
2
2
RQEX
IRQEX-"O"
3024
2
2
RQSR
IRQSR-"O"
3b07
2
2
.....
ESR
SRF-"1"
30BA
2
2
~.~
.- CJl
'cQ)
OSR
SRF-"O"
30B6
2
2
TSR
SKIP IF SRF = "1 "
30B2
2
2
STOP
STOP CLOCK
30B9
2
2
NOP
NO OPERATION
00
1
1
.8
CI) .....
0
.....
...
(Lc
~
08
174
----------------------------------------------------1. MSM6411 •
ABSOLUTE MAXIMUM RATING
Parameter
Supply Voltage
Symbol
Limits
-0.3 -7
V
Ta = 25°C
-0.3 -VOO
V
-0.3- VOO
V
Ta= 25°C
per one package
200 max.
mW
Ta= 25°0
per one output
50 max.
mW
:-55 - +150
°C
Limits
Unit
3-6
V
4.5 -5.5
V
VOO
Input Voltage
VI
Output Voltage
Vo
Power Dissipation
Po
Storage Temperature
Conditions
Tstg
Unit
OPERATING CONDITIONS
Parameter
Supply Voltage
Data-Hold Voltage
Operating Temperature
Fan Out
Symbol
Condition
f(OSC) ~ 1 MHz
VOO
f(OSC) ~ 4.2MHz
VOOH
f(OSC) =OHz
TOp
N
-
2-6
V
-40-+85
°c
MOSLoad
15
TTL Load
1
-
175
eMSM6411
e----------------------------------------------------
DC CHARACTERISTICS
(Voo = 5V±1 0%, Ta = -40 - +85°C)
Parameter
Symbol
Condition
Min.
Typ
Max.
Unit
VOO
V
VOO
V
0.8
V
-
V
0.4
V
0.4
V
"H" Input Voltage *1, *2
VIH
2.4
....,
"H" Input Voltage *3, *4
VIH
3.6
"L" Input Voltage
Vll
-0.3
"H" Output Voltage"1, *5
VOH
10=-·15/LA
4.2
"l" Output Voltage *1
VOL
10= 1.6mA
-
"l" Output Voltage *5
VOL
10 = 15/LA
-
-
VI=VOO/OV
-
-
-15
~
/LA
VI=VOO/OV
-
-
Ao
/LA
-0.1
-
-
rnA
-1.2
rnA
Input Current *3
Input Current *2, *4
II~
III
I~III
"H" Output Current *1
10H
VO=2.4V
"H" Output Current *1
10H
VO=0.4V
Input Capacitance
Output Capacitance
Power Consumption
(STOP)
Power Consumption
*1 Applied to PO and P1 .
*2 Applied to P2.
*3 Applied to OSCo
*4 Applied to RESET
*5 Applied to 0SC1
176
CI
f = 1 MHz, Ta = 25°C
Co
IOOS
100
-
5
-
pF
7
~
Voo = 2V,no load
Ta= 25°C
-
0.2
5
/LA
No load
-
1
100
/LA
Crystal oscillation,
No load, 4.2MHz
-
6
12
rnA
--------------------------------------------------. MSM6411 •
AC CHARACTERISTICS
(VDD = 5V±1 0%, Ta = -40 - +85°C)
Parameter
Symbol
Condition
Min.
Typ
Max.
Unit
Clock (OSCo) Pulse Width
t
20
b...
4
VOH (V)
10
9
"r\,1\,
"
~
'\
VDD(V)
TYP. Maximum Oscillator Frequency
f(OSC)
vs Temperature
CL= 15pF
(Ta)
1\
..... 1'\
4V
i"'"" ~
9
12
10
8
3
6
2
4
6VJ
IV
I--"" f-
VDD=5V
fJ
I
j..- 4V
I
1/
I-- 3V
Ii"'"
2
o
-40
-20
o
40
80
120
20
60
100
Ta(OC)
0
2
3
4
5
6
7
8
9 10
VOL (V)
179
• MSM6411 ••------------------------------------------------TYP. Supply Current vs Supply Voltage
(JDD)
(VDD)
Ta=25°e
No Load
10m
,,-v
V
/~V
/
V
/
1m
"
100J.L
/
V
= 4MHz
~ t(ose)
I
.. 2MHz
~
I
.. 1 MHz
~
I
500kHz
.....
.........
_JJ
/
10J.L
V
100n
o
I
2
V
V
3
4
5
VDD(V)
180
VOHz
6
7
8
9
10
OKI
semiconductor
MSM6422
CMOS 4-BIT SINGLE CHIP MICROCONTROLLER
GENERAL DESCRIPTION
The OKI MSM6422 is a low power, high performance single-chip device implemented in
complementary metal oxide semiconductor technology.
Integrated onto a single chip are 16K bits of mask program ROM; 256 bits of data RAM; 18
Input/Output lines and oscillator. Program memory is byte wide and data-paths are organized in 4 bit
nibbles. RAM and I/O lines are bit addressable. 63 instructions include Binary, BCD operations; Bit
set, Reset, Test; Subroutine call and return.
FEATURES
•
•
•
•
•
•
•
•
Low power consumption - 30 mW Typical
2048 x 8 Internal ROM
64 x 4 Internal RAM
18 I/O Lines include 8 Bit Data Bus
Self-contained Oscillator
631nstructions
2 Interrupt Levels
16 Stack Levels
•
•
-40 to +85°C Operating Temperature
4.5 to 5.5V Operating VDD at 4.2 MHz
3 to 6V Operating VDD at 1 MHz
• TTL Compatible
• 952ns Cycle Time @ 4.2MHz
(VDD 5V ±1 0%)
FUNCTIONAL BLOCK DIAGRAM
ROM
2048x8
10
3210
3210
wWr
3210
3210
0
/
I"
N
T
Timing
&
Control
tt
GV
NO
DO
iI I
00
R
SSE
C C
S
1 0
E
T
181
• MSM6422 ••--------------------------------------~-----------
LOGIC SYMBOL
(Top View)
24 PIN PLASTIC DIP (RS)
P51
P50
24 PIN FLAT PACKAGE
o
P43
P42
P41
P40
P33
P32
P31
OSCo
GND
P30
RESET
PIN DESCRIPTION
Terminal symbol
182
Input/Output
Function
Reset
POO
P01
P02
P03
1/0
4-bit 1/0 ports
(pseudo bidirectional
configuration)
"1 "
P10
P11
P12
P13
1/0
4-bit 1/0 ports
(pseudo bidirectional
configuration)
"1"
P30
P31
P32
P33
I/O
4-bit 1/0 ports
(pseudo bidirectional
configuration)
"1 "
P40
P41
P42
P43
I/O
4-bit 1/0 ports
(pseudo bidirectional
configuration)
"0"
P50
P51
1/0
2-bit 1/0 ports
(pseudo bidirectional
configuration)
"0"
P20/lNT
Input
1-bit input port with a latch.
Combined use with an
interrupt input(falling edge
trigger input)
The latch is
reset to "0".
OSCo
Input
System clock (SYSCLK)
input terminal. This provides
an oscillation circle with
OSC 1 terminal.
-
OSC,
Output
System clock output
terminal. This provides an
oscillation circle with
OSCo terminal.
-
RESET
Input
RESET input terminal.
-
VDD
GND
Input
Power Supply terminals.
-
~------------------------------~----------------.MSM6422.
FUNCTIONAL DESCRIPTION
Program ROM
Organized into as many as 2,048 words by 8
bits, ROM is used to store developed application
programs (instructions). It is addressed by the
program counter (PC).
Data RAM
RAM consists of up to 64 words 4 bits wide. It
is addressed by the H- and L-registers or by the
contents of the second byte of an instruction.
Input/Output Ports
18 input/output port lines are provided for
effecting and controlling data transfer to and
from an external source. The ports are selected
by codes included in instructions.
P20/INT PIN (1 line)
A low on this interrupt input pin sets the
interrupt request flag. The flag is automatically
reset when an external interrupt occurs.
The line can be used as an input port when
interrupt is not used.
12-BIT TIME BASE COUNTER (TBC)
The. time base counter consists of a 1 2-bit
binary counter. An interrupt request is generated
each time an overflow occurs from the division of
OSCo input signals by 212.
PROGRAM COUNTER (PC)
The program counter (PC) consists of a
11-bit binary up counter. It is used to address
ROM.
STACK AND STACK POINTER (SP)
An interrupt or subroutine call (CAL) causes
the contents of the program counter to be saved
in the stack. The program counter is restored
from the stack by the RT instruction.
All RAM locations (up to 16 leve.ls) are
available as the stack. Note that four words of
RAM are used for each level.
The stack pointer is a 4-bit up-down counter
that points to the address of the next stack to be
used. It allows the RAM locations to be used as a
push-down stack.
L-REGISTER
A 4-bit register which specifies RAM locations A3-AO.
H-REGISTER
A 4-bit register whose two low-order bits
specify RAM locations A5-A4.
ALU
The 4-bit logic circuit that provides arithmetic
and logical operations.
ACCUMULATOR (Ace)
Consisting of a 4-bit register, the accumulator holds the result of operations or the data
present on ports.
C-FLAG
The flag that holds a carry generated from the
result of operations.
TIMING CONTROL (TC)
A 0 level on the RESET pin for longer than a
predetermined period initializes the internal
circuitry and ports.
Clock pulses are supplied to the OSCopin
from an external source. A crystal or ceramic
oscillator may be connected to OSCo and OSC 1
to form an oscillator circuit to produce clock
pulses.
ABSOLUTE MAXIMUM RATING
Parameter
Supply Voltage
Symbol
VOO
Input Voltage
VI
Output Voltage
Va
Power Oissipation
Storage'Temperature
Conditions
Po
Tstg
Limits
Unit
-0.3 -7
V
-0.3 -VOO
V
-0.3 -VOO
V
Ta = 25°C
per one package
200 max.
mW
Ta = 25°C
per one output
50 max.
mW
-55 - +150
°C
Ta=25°C
-
183
•
MSM6422··----------------------~------~--------------------
OPERATING CONDITIONS
Symbol
Parameter
Condition
HOSC) ~ 1 MHz
Supply Voltage
Memory-Hold Voltage
Operating Temperature
Limits
Unit
3-6
V
VOO
HOSC) ~ 4.2MHz
4.5 -5.5
V
VOOH
-
2-6
V
-
-40 - +85
°C
MOS Load
15
.-
TTL Load
1
-
TOp
Fan Out
N
DC CHARACTERISTICS
(Voo = 5V± 10%, Ta = -40 - +85°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
"H" Input Voltage *1, *2
VIH
-
2.4
-
VOO
V
"H" Input Voltage *3, *4
VIH
-
4.2
-
VOO
V
"L" Input Voltage
VIL
-
-0.3
-
0.8
V
"H" Output Voltage *1, *5
VOH
10=-15/l-A
4.2
-
-
V
"L" Output Voltage *1
VOL
10 = 1.6mA
-
-
0.4
V
"L" Output Voltage *5
VOL
10 = 15/l-A
-
-
0.4
V
IIH/
IlL
VI =VOO/OV
-
-
1~
-15
/l-A
II~
VI =VOO/OV
-
-
--_.
Input Current *3
Input Current *2, *4
IlL
,%0 /l-A
"H" Output Current *1
10H
Vo =2.4V
-0.1
-
-
mA
"H" Output Current * t
10H
Vo =O.4V
-
-
-1.2
mA
-
5
-
-
7
-
VOO = 2V, no load
Ta = 25°C
-
0.2
5
/l-A
No load
-
1
100
/l-A
Crystal oscillation,
No load, 4.194304MHz
-
6
12
mA
Input Capacity
Output Capacity
Current Consumption
(STOP)
Current Consumption
CI
f = 1 MHz, Ta = 25°C
Co
IOOS
100
*1 Applied to PO, P1, P3, P4, and P5
*2 Applied to P2
*3 Applied to OSC o
*4 Applied to RESET
*5 Applied to OSC 1
184
pF
--------------------------e MSM6422 e
AC CHARACTERISTICS
(Voo = 5V±1 0%, Ta = -40 - +85°C)
Symbol
Condition
Min.
Typ.
Max.
Unit
Clock (OSCo) Pulse Width
tq,w
-
119
-
-
ns
Cycle Time
tCY
-
952
-
-
ns
120
-
-
ns
Parameter
1
Input Data Setup Time
tos
-
Input Data Hold Time
tOH
-
120
-
-
ns
Input Data/Input Clock
Pulse Width
tow
-
120
-
-
ns
Data Delay Time
tOR
CL=15pF
-
-
tCY +300
ns
1 MC
tCY
PO,P"P3
P",P5
P2o/INT
w
..
185
e MSM6422e---------------------------------------------------INSTRUCTION SET
Mnemonic
,
"0
«I
0
....J
eC
0
()
,- c
cQl
Ql E
EQl
Ql ....
.... u
uQl
E"O
Byte
Cycle
Description
LAI
n
90-9F
1
1
Acc-n
LLI
n
80-8F
1
1
L-n
LAL
21
1
1
Acc-L
LLA
20
1
1
L-Acc
LAH
22
1
1
Acc-H
LHA
2E
1
1
H-Acc
LAM
38
1
1
Acc-M
LMA
2F
1
1
M-Acc
X
28
1
1
Acc-M
LMI
nn
14·nn
2
2
M(W)-nn
LHLI
nn
15·nn
2
2
HL-nn
LAMO
mm
10·mm
2
2
Acc -Md
LMAO
mm
11 ·mm
2
2
Md -Acc
IPO
P
30·pO
2
2
Acc -Pp
OPO
P
30·pC
2
2
Pp-Acc
MEl
3E·60
2
2
MEIF-"1"
MOl
3E·61
2
2
MEIF-"O"
EIEX
30·C8
2
2
EIEXF-"1"
EITB
30·C9
2
2
EITBF -"1"
OIEX
30·C4
2
2
EIEXF-"O"
OITB
30·C5
2
2
EITBF-"O"
TIEX
30·CO
2
2
SKIP IF EIEXF="1"
TITB
30·C1
2
2
SKIP IF EITBF="1"
TOEX
30·20
2
2
SKIP IF IROEX="1 "
TOTB
30·00
2
2
SKIP IF IROTB="1"
ROEX
30·24
2
2
IROEX <'- "0"
ROTB
30·04
2
2
IROTB-"O"
INL
31
1.
1
L - L+ 1, SKIP IF L="O"
INH
32
1
1
H ~ H+ 1, SKIP IF H="O"
INM
33
1
1
M - M+1, SKIP IF M="O"
DeL
35
1
1
L - L-1 ,SKIP LF L="F"
H - H-1 , SKIP IF H="F"
OCH
36
1
1
OCM
37
1
1
M - M-1, SKIP IF M="F"
12·mm
2
2
Md-Md+1,
SKIP IF Md="O"
INMO
186
Hex op code
mm
- - - - - - - - - - - - - - - - - - - - - - - - - - . MSM6422 •
INSTRUCTION SET (CONT.)
Mnemonic.
Cl
Hexopcode
Byte
Cycle
Description
TAB
n2
54-57
1
1
SKIP IF (Acc-Bit n2) = "1 "
TMB
n2
58-5B
1
1
SKIP IF (M-Bit n2) = "1 "
RMB
n2
68-6B
1
1
(M-Bit n2) - "0"
78-7B
1
1
(M-Bit n2) - "1 "
5MB
n2
=ct::
TPBDp
n2
3D·pO-3
2
2
SKIP IF (Pp-Bit n2) = "1 "
-
RPBDp n2
3D·p4-7
2
2
(Pp-Bit n2) - "0"
SPBDp
3D·p8-B
2
2
(Pp-Bit n2) - "1 "
TC
09
1
1
SKIP IF C = ''1 "
.5
as
.s::
ill
n2
RC
08
1
1
C-"O"
SC
07
1
1
C-"1"
ADS
02
1
1
Acc-Acc+M,
SKIP IF Cy="1"
ADC
03
1
1
C, Acc - C+Acc+M
3E·4n
2
2
Acc-Acc+n,
SKIP IF Cy="1 "
DAS
OA
1
1
Acc -Acc+10
0
AND
OD
1
1
Acc-AccAM
E
OR
05
1
1
Acc-AccVM
:!::
EOR
04
1
1
Acc-AccVM
CMA
OB
1
1
Acc -Ace
CAM
16
1
1
SKIP IF Acc=M
3E·On
2
2
SKIP IF Acc=n
OE
1
1
AIS
:a;
n
.s::
<
CAl
n
RAL
.s::
0
t::
as
"-
!Xl
III
Q;
JCP
a6
CO- FF
1
1
PC-a6
JP
a11
40 -47
OO-FF
2
2
PC -a11
CAL
a11
AO-A7
00- FF
2
4
STACK - PC+2, PC-a11,
SP-SP-1
RT
1E
1
4
PC - STACK, SP - SP+ 1
PUSH
1C
1
3
STACK - PC+2, PC-a11,
SP-SP-1
POP
1D
1
3
C, Acc, H, L -STACK,
SP-SP+1
STOP
3D·B9
2
2
CLOCK STOP
NOP
00
1
1
NO OPERATION
.s::
(5
r- Acc ____
[C - 3-2-1-0-,
187
• MSM6422 ••---------------------------------------------------TYP. Current (lOL) vs Voltage (Vod
for Low state Output
TYP. Current (lOH) vs Voltage (VOH)
for High state Output
-1.0
-0.9
-
-0.8
...,0.7
~-0.6
20
18
'"i: -0.5 =-
-=
.9-0.4
-0.3
-0.2
o
o
~
~
\
'"
\
I ....-
CAM
16
1
1
SkipilA=M
AIS
n
Description
,--A~
,--A~
3->2->1->0)
CAl
n
3E· On
2
2
Skip il A = n
CMI
n
3E·1n
2
2
SkipilM=n
CLI
n
3E·2n
2
2
Skip il l = n
CPI
p,n
17· pn
2
2
Skip il Pp = n
Code
Bytes
Cycles
CO-FF
1
1
PC <-a6
JA
1A
1
2
PC <- (PC <- A) +1
JM
1B
1
2
PC <- (M (w), A)
Branch Instructions, etc.
Mnemonic
JCP
a6
Description
JP
a12
40 4F
OO-FF
2
2
PC <-a12
CAL
a12
AO AF
OO-FF
2
4
ST <- PC+2, PC <- a12, SP <- SP-4
CZP
a
Sa
1
4
ST <- PC+ 1, PC <- 2a, SP <- SP-4
LJP
a13
3F 3F
00-1F
00 FF
3
4
PC <-a13
lCAl
a13
3F 3F
80-9F
00 FF
3
4
ST <- PC+3, PC <- a13, SP <- SP-4
RT
1E
1
4
PC <- ST, SP <- SP+4
RTS
1F
1
4
PC <- ST, SP <- SP+4, then Skip
213
• MSC6458 • - - - - - - - - - - - - - - - - - - - - - - - - Counter Control Instructions, etc.
Code
Bytes
Cycles
LCTM
3E· 51
2
2
CTR <-M (w)
LMCT
3E·59
2
2
M (w) <-CT
ECT
3D· BB
2
2
CTF <- "1"
(Counter Start)
OCT
3D· B7
2
2
CTF~"O"
(Counter Stop)
TCT
3D· B3
2
2
Skip if CTF
LTMM
3E·50
2
3
TMR<-M (2w)
LMTM
3E·58
2
3
M (2w) <-TM
LSRM
3E·52
2
2
SR <- M (w), SC <- "0"
LMSR
3E·5A
2
2
M (w)<-SR
ESR
3D· BA
2
2
SRF <- "1"
(Shift Register Start)
DSR
3D· B6
2
2
SRF <-"0"
(Shift Register Stop)
TSR
3D· B2
2
2
Skip if SRF
Code
Bytes
Cycles
PUSH
1C
1
3
ST <- C, A, H, L, SP <- SP-4
POP
10
1
3
C,. A, H, L <- ST, SP <- SP+4
HALT
3D· B8
2
2
Halt CPU
STOP
3D· B9
2
2
Stop CPU
00
1
1
No Operation
Mnemonic
Description
= "1"
SC: Shift Counter
= "1"
CPU Control Instructions, etc.
Mnemonic
NOP
I
214
Description
- - - - - - - - - - - - - - - - - - - - - - - - - - . MSC6458 •
Explanations of Instruction Symbols
A
H
L
: Accumulator (4-bit)
: H register (4-bit)
: L register (4-bit)
F
: F register (4-bit)
M
: RAM word addressed by the Hand L registers
Md
: RAM word addressed by second byte of an instruction code
M(w)
: Two RAM words addressed by the Hand L register/H3-0 and L3-1 (a-bit)
Md (w) : Two RAM words addressed by second byte of an instruction code (a-bit)
M (2w) : Four RAM words addressed by the Hand L register/H3-0 and L3-2 (16-bit)
ST
: Four RAM words (16-bit) allocated as a stack area
: Stack pointer (a-bit)
SP
PC
: Program counter
P
: Port specified by the L register (4-bit)
: Port specified by 4 high-order bits of second byte of an instruction code (4-bit)
Pp
CTR
: a-Bit counter/register
CT
: a-Bit programmable counter
CTF
: Programmable counter start flag
TMR
: 16-Bit timer/register
TM
: 16-Bit programmable timer
SR
: a-Bit shift register
SRF
: Shift register start flag
(X, Y)
: ROM address data specified by a11-4 as X and a3-0 as Y (12-bit)
T (X, Y) : ROM table data specified by a 11-4 as X and a3-0 as Y (a-bit)
: Immediate data (4-bit)
n
nn
: Immediate data (a-bit)
n2
: Two low-order bits of an instruction code
: Bit specified by the two low-order bits of an instruction code
(n2)
a
: ROM address data
aX
: ROM address data (X-bit)
: RAM address data (a-bit)
mm
: Carry flag
C
: Flag indicating a carry in a calculation result
Cy
215
OKI
semiconductor
MSC6458VS
MSC6458 PIGGY BACK
GENERAL DESCRIPTION
The MSC6458VS is a device whose built-in ROM is replaced by external EPROM using the
piggyback method.
FEATURES
•
•
Supply Voltage: 5V±5%
Frequency: DC - 4.3MHz
•
Operating Temperature: 0 - 70°C
ROM INSERTION
Please refer to drawing below.
C6458
OKI
JAPAN
PIN CONFIGURATION
Pin Connection between MSC6458 VS and EPROM
Vee
A13
A12
An
10
9
ToAO -A13
of MSC6458VS
A
'vi
ADDRESS
8
7
6
5
4
A4
A3
A2
Al
AD
00
01
02
GND
AO
DO
1
2
10-1
11
'vi
Note: When inserting a 2764,
pin 26 is not used.
216
DATA
'--Vpp
A12
A7
A6
A5
3
2
1
MSC6458VS
-
-
3
4
5
6
D7
GND
"1"'-'2s
2
27
3
26
4
25
5
24
6
23
72712822
8
21
9
20
10
19
11
18
12
17
13
16
14
15
,J
PGM
A13 A8A9All
OE
Al0
CE
070605-
g;Jl
OlMS-6S SERIES
OKI
semiconductor
MSM6502/6512
CMOS 4 BIT SINGLE CHIP MICROCONTROLLER WITH LCD DRIVER
GENERAL DESCRIPTION
The OKI MSM6502/6512 is a low-power, high-performance 4 bit single-chip microcontroller implemented in complementary metal oxide semiconductor technology.
Integrated within this one chip is a 108 (4 x 27) dot LCD Driver. Also integrated in this chip are
16K bits of mask program ROM, 512 bits of data RAM, Input/Output lines, a programmable
timer/counter, and oscillator.
The advantages of the MSM6502/6512 in comparison with the OLMS-40 Series include, among
other features, a lower drive voltage, multiplexed interrupts, a larger number of drivable liquid crystal
elements, a buzzer output, and larger memories.
FEATURES
•
•
•
•
•
•
•
•
•
ROM
RAM
Numberof
Instructions
Clock Oscillation
Cycle Time
Timer Interrupt
I/O Ports
Input ports
LCD Drive
•
•
Buzzer
Interrupt
2000 x 8 bit
128 x 4 bit
68
Crystal 32.768 kHz
91.5/Ls
Dual (16 & 128 Hz)
4 bit x 2 Port
4 bit x 1 Port
108 (4 x 27)
picture elements
2K/1 K/512 Hz/Soft
Three types
(external, two timer
types)
•
Stack
•
•
•
Power down
Operating power
supply voltage
Consumption
current
(VDD=3V,
OSC=
32.768 kHz)
•
Package
Nesting RAM stack
pointer = 7 bits
Halt mode available
2.4V - 3.6V
MSM6502
; 45/LA (Typical)
30/LA (Halt mode)
MSM6512
; 30/LA (Typical)
1 2/LA (Halt mode)
; 56 pin FLAT (Small type)
FUNCTIONAL BLOCK DIAGRAM
00
R
4
32 1
SSE '"'----"
CCS
TEST
0'
E
T
N
T
V G
o
o
N
0
T
219
• MSM6502/6512 • - - - - - - - - - - - - - - - - - - - - - -
PIN CONFIGURATION (TOP VIEW)
LOGIC SYMBOL
Crystal
resonator
J
PortO
, (input/output ports)
connection
Reset
J
Port1
(input/output ports)
Interrupt
Test pins
l
42 SEG13
P02
P03
P10
TEST3
TEST4
J
LCD
common output
P21
P22
P23
LCD
segment output
BZ
ilZ
25
26
IfI
+3V
VDD
BZ
OV
GND
ilZ
J
Buzzeroutput
PIN DESCRIPTION
Designation
Pin No.
GND
24
VDD
21,49
Function
CircuitGND potential
Main power source
22
Crystal OSC input, internal clock input
OSC,
23
Crystal OSC input, internal clock output
PO, P1
1 t04
St08
OSCo
--
Pseudo-bidirectional ports for 4-bits parallel 110. To input data from these ports,
it is necessary to write "1" beforehand.
The port to be selected is specified by the L register. The register contents and
the corresponding specified ports are listed below.
Content of L register
0.8
1.9
2.0AH
3.0BH
4.0CH
S.ODH
6.7.0EH.OFH
Port Specified
PO
P1
P2
P3
P4
PS
No designation
Note: P3, P4, PS are internal ports.
P2
9t012
INT
16
220
Input ports for 4-bit parallel input with no latching function.
Input pin to request an interruptfrom the external circuit. Theinput flag is set by
the fali of the input signal.
- - - - - - - - - - - - - - - - - - - - - - . MSM6502/6512 •
Designation
Function
Pin No.
RESET
15
The reset mode starts after "a" is input to the RESET pin for more than 2
machine cycles.
The reset signal has priority over all of other signals and performs the following
operations automatically:
(1 ) Resets all bits of the PC (Program counter) to "0".
(2) Sets all bits of the parallel I/O ports (POO to P13) to "1 ".
(3) Resets the internal resister (H, L, ACC, C, P3, P4, P5).
(4) Resets the skip flag.
(5) Resets all bits of the time base counter (TBC).
(6) Resets the interrupt request flag (lRQF).
(7) Resets the interrupt enable flag (ElF).
(8) Resets the master interrupt enable flag (MEIF).
(9) Sets all bits of the stack pointer (SP) to "1 ".
(10) Initializes the segment and common outputs.
(11) Sets all bits of the index register (lDR) to "1 ".
Since the RESET pin is pulled up to VDD by an internal resister (approx. 800
kil), itis possible to achieve power ON/reset by connecting it with an
external capacitor.
LCD Drive Pins
SEGO-26
29t048
50t056
25 to 28
COM 1 -4
13,14
BZ/BZ
A special AC waveform designed to comply with liquid crystal properties is
required for liquid crystal drive purpose. The MSM6502B is equipped with a
1/4 duty 1 /3 bias liquid crystal drive circuit with four common output ports and
27 segments to enable displays of 1 08 picture elements. On/off selection of
picture element displays involves writing "a" or "1" in the corresponding bits in
the RAM OOH to thru 1 AH display area, and subsequent automatic hardware
controlled display. The frame frequency is 64 Hz.
BZ and BZ are used in the generation of alarms and other sounds. The
selectable frequencies include three hardware frequencies (TBC output) 51 2,
1024, and 2048 Hz, and a software type based on P50 data. These frequencies
are selected at P3.
When one of the.hardware frequencies is selected by P3, output of that
frequency is continuous. But selection of the software type results in output of
P50 contents to generate a melody by program.
INSTRUCTION LIST
Grouping
Load
Mnemonic
Code
Byte
Cycle
Function
LAI
n
Sn
1
1
Acc-n
LLI
n
7n
1
1
L-n
LHLI
nS
6A
nS
2
2
HL-nS
LXI
nS
69
nS
2
2
X-nS
LAM
BO
1
1
Acc-M
LAL
B1
1
1
Acc-L
LAH
B2
1
1
Acc-H
LMA
B4
1
1
M -Acc
LLA
B5
1
1
L-Acc
LHA
B6
1
1
H-Acc
2
2
M -Acc
LMAD
m7
1B
m7
221
• MSM6502/6512 • - - - - - - - - - - - - - - - - - - - - - -
INSTRUCTION LIST (CO NT.)
Grouping'
Code
Mnemonic
Function
Byte
Cycle
2
2
Acc-M
I
LAMD , m7
1A
LMT
m7
67
1
2
M -ROM
PUSH
HL
BC
1
2
STACK -HL, SP -SP-2
PUSH
CA
BD
1
2
~TACK
POP
HL
BE
1
2
HL -STACK, SP -SP+2
POP
CA
BF
1
2
C, Acc.-STACK, SP -SP+2
XAM
B8
1
1
Acc-~M
XAMD m7
1C
2
2
Acc~M
XHS
3F
1
1
HL-~SP
INA
10
1
1
Acc - Ar:;c + 1, Skip if Acc= 0
INL -
11
1
1
L-L+1,SkipifL=O
INM
12
1
1
M-M+l,Skipif
M=O
INX
5C
1
1
X-X+1
DCA
14
1
1
Acc -Acc-1,Skip ifAcc= F
DCL
15
1
1
L-L-1
DCM
16
1
1
M-M-l,Skip ifM=
F
DCX
5D
1
1
X-X-1
DSC
60
1
1
C,Acc+-:-C+Acc+M < HL >, Adjust if C=O
DAC
61
1
1
C,Acc-C+Acc+(M < HL > +6), Adjust if
C=O
ADS
62
1
1
Acc -Acc+M., Skip ifCy=l
63
1
1
C,Acc -C+Acc+M < HL > ,Skip if C=l
On
1
1
Acc-Acc+n, Skip if Cy=l
CMA
65
1
1
Acc-Acc
EOR
66
1
1
Acc -Acc¥M
AND
4C
1
1
Acc -Acc/\M
OR
4D
1
1
Acc -AccVM
CAM
6B
1
1
SkipifAcc=M
CPAL
6C
1
1
Skip if Acc = L
CAXL
6D
1
1
Skip if Acc = XL
CAXH
6E
1
1
Skip if Acc = XH
SC
1F
1
1
C-"l"
RC
1EJ
1
1
C_uO"
TC
4E
1
l'
SkipifC="l"
Load
Exchange
Increment
and
decrement
ADCS
AIS
Operation
)
222
n
m7
-C, Acc, SP -SP-2
SkipifL=F
- - - - - - - - - - - - - - - - - - - - - - - . MSM6502/6512 •
INSTRUCTION LIST (CONT.)
Grouping
Mnemonic
Code
Byte
Cycle
RAL
18
1
1
,.-- Acc----.
(*) -C -3-2-1--<>-(*)
RAR
19
1
1
,.-- Acc ---,
(*) - C - 3-2-1-0-(*)
30-33
1
1
M bltn2 -"1"
2
2
M bitn2-"1"
Operation
5MB
Bit
Function
n2
- 53m7
5MBO m7,n2
50
m7
SPB
n2
20-23
1
1
Pbitn2 -"1"
RMB
n2
34-37
1
1
M bit n2 -"0"
2
2
M bitn2 -"0"
RMBO m7,n2
54
m7
- 57m7
Operation
RPB
n2
24-27
1
1
Pbitn2-"0"
TMB
n2
38-3B
1
1
Skip il M bit n2 = "1"
TMBO
m7,n2
58
m7
2
2
Skip iIM bitn2 ="1"
TPB
n2
28-2B
1
1
Skip ilP bit n2 ="1"
TAB
n2
2C-2F
1
1
Skip il Acc bit n2 = "1"
TIRB
n2
49-4B
1
1
illROF bit n2="1" Skip & IROF bit n2 -"0"
5E
1
1
MEIF-"1"
EI
- 5B
m7
Interrupt
01
Branch
Input!
Output
CPU
Control
5F
1
1
MEIF-"O"
J
a11
9000-97CF
2
2
PClO-0-a11
CAL
a11
AOOO-A7CF
2
3
STACK-PC+2, SP-SP-3, PClO - o-a11
JCP
a6
CO-FF
1
1
PC5-0-a6
RT
3C
1
2
PC -STACK, SP-SP+3
RTS
30
1
1
PC -STACK., SP-SP+3, then Skip
IP
B3
1
1
Acc-P
OP
B7
1
1
P-Acc
HALT
4F
1
1
HLF-"1"
NOP
00
1
1
No Operaiion
223
[I
eMSM6502/6512 e --------------------------------------------ELECTRICAL CHARACTERISTIC
ABSOLUTE MAXIMUM RATING
Parameter
Power Supply Voltage
Symbol
VDD
Input Voltage
V,
Output Voltage
Vo
Power Dissipation
PD
StorageTern peratu re
Conditions
Tstg
Ta=25°C
Ta=25°C
per package
-
Limits
Unit
-0.3-7
V
-0.3-VDD
V
-0.3-VDD
V
200
mV
-55 -+150
°C
OPERATING RANGE
Parameter
Symbol
Conditions
Limits
Unit
Power Supply Voltage
VDD
f(osc)=32.768 kHz
2.4 -3.6
V
Operating Temperature
Top
-20-+70
°C
o
224
-
- - - - - - - - - - - - - - - - - - - - - - . MSM6502/6512 •
D.C. CHARACTERISTICS
(VDD = 3V, Ta = -20 - +70°C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
"H" Input Voltage
VIH
-
2.6
-
-
V
"L" Input Voltage
VIL
-
-
-
0.4
V
"H" Output
Voltage(l )
VOH
IO=-1.0mA
2.0
-
-
V
"L" Output
Voltage(2)
VOL
lo=1.0mA
-
~
1.0
V
2.8
-
3.0
V
1.8
-
2.2
V
0.8
-
1.2
V
0.0
-
0.2
V
MSM6502
IO=-5/-LA
MSM6512
IO=-2/-LA
MSM6502
IO=±2/-LA
MSM6512
IO=±0.5/-LA
MSM6502
IO=±2/-LA
MSM6512
IO=±0.5/-LA
MSM6502
IO=5/-LA
MSM6512
IO=±2/-LA
V3
V,
LCO Orive
Output Voltage(3)
V,
Vo
OSCo Input Current
IIH/IIL
VI =VOOIVI =OV
-
-
2/-2
/-LA
Input Current(4)
IIH/IIL
VI =VDDIVI =OV
-
-
1/-10
/-LA
Input Current(5)
IIH/IIL
VI =VOOIVI =OV
-
-
1000/-1
/-LA
Input Current(6)
IIH/IIL
VI =VOOIVI =OV
-
-
1/-40
/-LA
-
-
-50
/-LA
-
45
70
-
30
55
-
30
40
-
12
25
-
15
25'
-
5
15
-
-
10
PO,Pl
"H" Output Current
Vo=OV
IOH
MSM6502
100
MSM6512
Current
Consumption
MSM6502
IOOHLT
MSM6512
1(osc) = 32.768 kHz
at no load
1(osc) =32.768 kHz
at HLT execution
MSM6502
MSM6512
TOSC
/-LA
Statis
IOOS
Oscillation Start
Time
/-LA
-
/-LA
SEC
225
.MSM6502/6512·----------------------------------------~---
(1) Applied to BZ, BZ
(2) Applied to BZ, BZ, PO, P1
(3) Applied to COMMON, SEGMENT
- - - - - - V3
- - - - - - V2
------V1
~-
- - - Vo
(4) Applied to RESET, INT
(5) Applied to P2 (When input is unable)
(6) Applied to P2 (When input is able)
SWITCHING CHARACTERISTIC
(VDD =3V, Ta =-20 - +70°C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
tq,W
-
15
-
-
MS
Cycle Time
tCY
-
(1 )
-
-
MS
PO
P1 Data Valid Time
P2
tDV
-
(2)
-
-
MS
PO
P1 Data Invalid Time
P2
tDiV
-
-
-
(3)
MS
~? Data Delay Ti me
tDDS
-
-
(4)
MS
Clock (OSCo) Pulse Width
(1)
(2)
(3)
(4)
CL=50pF
tCY = 3 x 1/t(osc)
tDV = 112 x 1/f(osc)
tDIV = 1 x 1!f(osc) + 1OMS
tDDS = 5/2 x 1/t(osc) + 1 5MS
1MC tCY
OSCo
tc/>w
PO
P1 Input mode
P2
tc/>w
INVALID
tDIV
PO
P1 Output Mode
INVALID
tDV
OLD DATA
tDDS
226
NEW DATA
- - - - - - - - - - - - - - - - - - - - - - - . MSM6502/6512 •
TYPICAL PERFORMANCE CURVES for MSM6502
Low-level Output Current (loL>
- Output Voltage (VoL>
High-level Output Current (lOH)
- Output Voltage (VOH)
(Voo =3V, Ta= 25°C)
(VOO= 3V, Ta= 25°C)
10
-5
9
8
-4
7
«
.sJ:
9
-3
'-2
(BZ, BZterminal)
f'\
«
.s
5
9
4
..J
V
2
(COMMON, SEGMENT terminal)
o
o
rI
~(PO, Pl terminal)
-.l
1
2
3
4
5
6
7
8
9
I-
(BZ,I Bi iermlnal)
(COMMO,N SEGMENT terminal)
o
o
10
(PO, Pl terminal)
/I -
3
1\
-1
6
2
3
4
5
6
7
8
10
9
VOH(V)
VOL (V)
Middle-level Output Current (11, 12)
- Output Voltage (V1, V2)
Current Consumption (lDD)
- Power Supply Voltage (VDO)
(Ta= 25°C, No load)
(VOO= 3V, Ta= 25°C)
25
10m
20
5m
15
Vl
10
«
.5
N
.:
V2
1m
/ /
5
5001'-
II LI
0
)
-10 II II
)
-5
(COMMON, SEGMENTterminal)
1001'-
-15
5
-20
.9
-25
HOSC) = 32,768 KHz
501'-
V V oJz
Cl
V
101'-
o
1
2
3
4
5
6
7
8
9
10
51'-
V" V.(V)
500n
100n
o
1
2
3
4
5
6
7
8
9
10
VDO(V)
227
r::~
• MSM6502/6512 . - - - . . . . : . - - - - - - - , - - - - - - - - - - - - - -
TYPICAL PERFORMANCE CURVES for MSM6512
Low-level Output Current (lod
- Output Voltage (VOL)
High-level Output Current (lOH)
- Output Voltage (VOH)
(Voo =3V. Ta= 2S0C)
(Voo= 3V. Ta= 2S0C)
10
-S
9
8
-4
<
..s
-3
.9
-2
J:
7
-
(BZ. BZterminal)
'\\
<
..s
S
.9
4
....J
3
\
-1
6
/
2
(COMMON. SEGMENT terminal>
, I
o
o
1
I
~ (PO. P1 terminal)
2
3
4
S
6
o
7
8
9
10
I
JI
o
-
(PO. P1 terminal)
.1-.1
--" (8Z. BZ terminal>
(COMMO,N SEGMENT, terminal)
2
3
4
S
6
7
8
9
10
VOL(V)
VOH(V)
Current Consumption (100)
- Power Supply Voltage (VOO)
Middle-level Output Current (11 ,12)
- Output Voltage (V1, V2)
(Ta= 2SoC. No load)
(VOO= 3V. Ta= 2S0C)
2S
10m
20
Sm
1S
V1
10
N
~
1m
/ I
S
<
3-
V2
SOOJL
[TV
0
J J (COMMON. SEGMENT terminal)
-10 I II
-S
100JL
-1S
5
-20
.9
-2S
!(OSC) = 32.768 KHz
SOJL
Cl
/
10JL
o
1
2
3
4
S
6
7
8
9
10
SJL
/
/ o~z
/'
1JL
SOOn
100n
o
2
3
4
S
6
Voo(V)
228
7
8
9
10
8 BIT SERIES (OKI ORIGINAL)
OKI
semiconductor
MSM62580
CMOS 8-BIT SINGLE CHIP MICROCONTROLLER WITH 16K BIT E2PROM
GENERAL DESCRIPTION
The MSM62580 is a CMOS one-chip microcontrollar with on-board 16K bit E2PROM for applications such as IC-cards, etc.
The powerful instruction set consists of 95 instructions including special instructions for IC cards,
executed by the 8-bit CPU in 800 ns at 5.0 MHz clock frequency.
The MSM62580 has improved hardware and software for security. Consequently, this chip suits
application such as IC cards of low cost, high security and high reliability.
APPLICATION EXAMPLES
•
•
•
•
IC Cards
Mechanical Controls
Automobile Controls
Industrial Controls
•
•
•
•
Compact Disc Players
AudiolVideo Equipment
Household Appliances
Musicallnstruments
FEATURES
High speed instruction cycle
High number of instructions, and an efficient instruction set
(For example)
• Instructions for
• Instructions for
auto increment
SIN, SOUT, DLY
serial interface
and auto crecre• Index addressing
ment
• 1 byte call addresing
CZP
Small package size
• Simplified E2PROM write/erase operation by using control ROM.
From D.C to 5 MHz clock frequency
• 9600 baud-rate serial interface using "DLY" instruction.
INC, DEC
SPECIFICATIONS
•
•
•
•
•
•
Single chip, low power CMOS
8-Bit Microcontroller
3K Bytes program ROM
512 Bytes control ROM
2K Bytes E2PROM
128 Bytes data RAM
•
•
•
•
•
•
•
•
Clock frequency
Instrucion cycle
Number of instructions:
Operation current
Ambient range
Number of pads
Supply voltage
Die size
o-
5.0 MHz
800ns @ 5 MHz
95
4 mA typo
o to 70°C
5
+5 V ± 10%
5.0 x 4.5 mm
231
• MSM62580 • - - - - - - - - - - - - - - - - - - - - - - - - -
BLOCK DIAGRAM
S-I/O
VDD
c:::J--
E'PROM
2kx8
elK
GND
• E2PROM is not used as instruction area.
ALU
E2PROM
ROM
RAM
Arithmetic Logic Unit
Electrically Erasable-Programmable ROM
Read Only Memory
Randam Access Memory (Data memory)
PIN DESCRIPTION
Description
Input/Output
S-1I0
Input/Output
VDD
GND
-
RES
Input
"Reset" has priority over every other signal.
RES input initialize the processor.
Active "0" level.
CLK
Input
External clock input
232
Function
Serial data input/output port.
Quasi bidirectional 110 port.
Set "1" level after "Reset".
Main power source
Circuit GND potential
- - - - - - - - - - - - - - - - - - - - - - - - - . MSM62580 •
REGISTER DIAGRAM
17 ,
,01
Accumulator
17,
,01
B·register
l><:Jp,H,Z,CI
CCR
k
,01
O-register
k
,01
111 ,
,01
Stack pointer (SP)
Program Counter (PC)
MEMORY MAP
17FFH
6K
E'PROM
1FH
F
1EH
E
1CH
1DH
1000H
4K
--------
-127
STACK
i
7
0
R"
7FH
EOOH
BFFH
3K
--
R,
/
RAM map
ROM
R,
2
4
3
R,
R,
0
6
5
R.
1
R,
31
Ro
0
An : local resister (when instruction "DJNZ", n "" 4 to 7)
(a)
3
R,
ZP
2
1
1FH
0
0
ZP: is Zero Page address called by instruction "GZP"
(b)
ROM, E'PROM map
233
• MSM62580 • - - - - - - - - - - - , - - - - - - - - - - - - - - - - -
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Conditions
Limits
Unit
VDD
Ta = 25°C
-0.5 to 7
V
Input Voltage
VI
Ta = 25°C
-0.3 to VDD +0.5
V
Output Voltage
Vo
Ta = 25°C
-0.3 to VDD +0.5
V
Supply Voltage
Storage Temperature
o to
Tstg
+70
°C
OPERATING CONDITIONS
Parameter
Symbol
Limits
Unit
Supply Voltage
VDD
4.5 to 5.5
V
Operating Temperature
TOp
o to
°C
+70
D.C. CHARACTERISTICS
(VDD
=
5V± 10%, Ta = 0 to +70°C)
Parameter
Operating Current
Symbol
Conditions
Min
IDD
f = 5 MHz
-
Unit
10
mA
-
0.5
-0.3
-
0.5
SIO
-0.3
-
0.8
ClK
2.4
-
VDD
4
-
VDD
2.0
-
VDD
RES
High Input Voltage
4
Max
-0.3
ClK
low Input Voltage
Typ
RES
Vil
VIH
-
-
SIO
V
V
low Output Voltage
VOL
10l MAX = 1.6mA
0
-
0.4
V
High Output Voltage
VOH
IOH MAX = -100;;'A
2.4
-
VDD
V
-
-
20
p.A
-
-
-1
mA
-
15
-
pF
-
20
-
pF
Input Current (ClK, RES)
IIH1/11l1
VI=ONDD
Input Current (SIO)
IIH2/11l2
Input Capacitance
CI
Output Capacitance
Co
f=1MHz
Ta=25°C
Notes: = ClK, RES has poll down resistance SIO has pull up resistance.
,
234
--------------------------------------------------eMSM62580e
A.C. CHARACTERISTICS
(VDD = SV± 10%, Ta = 0 to +70°C)
Parameter
Symbol
Min
Typ
Max
Unit
ClK Cycle Time
TCY
200
-
-
ns
ClK Cycle low Width
TCl
0.4*TCY
-
0.6*TCY
ns
ClK Cycle High Width
TCH
O.4*TCY
-
0.6*TCY
ns
ClK Cycle Rise Time
TCR
-
-
S.O
f-Is
ClK Cycle Fall Time
TCR
-
-
5.0
f-IS
RES Pulse Width
TRW
8*TCY
-
-
f-Is
SIO INPUT Rise Time
TSR
-
-
5.0
f-Is
SIO INPUT Fall Time
TSF
-
-
5.0
f-Is
Note:
at output capacitance Co
= 30pF
TIMING CHARTS
~-----------TCY-- ---------
TCl--2.4V
ClK
~
2.4V
O.SV
TCH-~
TCR
TCF
TSR
TSF
SIO
\
RES
'
r----TRW------l.i
~-O.8V
/
O.8V¥
235
• MSM62580 • - - - - - - - - - - - , - - - - - - - - - - - - - - - -
INSTRUCTION LIST
MNEMONIC
opr
OPERATION
FLAGS
BYTE CYCLE
C
MOV A, opr
MOV opr, A
P
H
Z
B
A<-B
1
1
*
0
A<-D
1
1
*
@D
A <- (D)
1
1
*
@D+
A<-(D), 0<-0 + 1
1
2
*
@D-
A<-(D), 0<-0-1
1
2
*
N
A <- (N)
2
2
*
N+D
A <- (N+D)
2
3
*
#N
A <- #N
2
2
*
B
B<-A
1
1
0
D<-A
1
1
@D
(D) <- (A)
1
1
@D+
(D)<-A, 0<-0 + 1
1
2
@D-
(D) <-A, D<-D-1
1
2
N
(N) <- A
2
2
N+@D
(N+D) <- A
2
3
Rn
o <-
Rn
1
2
#N
0<- #N
2
2
0
Rn <- 0
1
2
#N
Rn <- #N
2
3
@D
(BA) <- (D)
1
4
@BA
(D) <- (BA)
1
4
MOV @D+, opr
#N
(0)<- #N,D<-D+
2
2
MOVW @O+ , opr
BA
(D)<-A, (D+1)<-B
1
3
MOVW SA, opr
@D
A<-(D), B<- (D+1)
1
3
*
MOVW SA, opr
#N
A<-#N1, B<-#N2
3
3
*
MOV D, opr
MOV Rn, opr
MOV @SA, opr
MOV @D, opr
236
- - - - - - - - - - - - - - - - - - - - - - - . MSM62580·
MNEMONIC
opr
OPERATION
FLAGS
8YTE CYCLE
C
XCH A, opr
P
H
Z
8
A .... 8
1
2
*
0
A .... 0
1
2
*
@D
A .... (D)
1
2
*
N
A- (N)
2
2
*
8
0-8
1
2
SP
0 - SP
1
2
XCH C, opr
P
C-P
1
1
ADD A, opr
@D
A +- A+(D)
1
1
*
*
N
A +- A+(N)
2
2
#N
A+- A+ #N
2
@D
A+-A+(D)+C
N
#N
XCH 0, opr
ADC A, opr
*
*
*
*
*
2
*
*
*
1
1
*
*
*
A+-A+(N)+C
2
2
*
*
*
A+-A+#N+C
2
2
*
*
*
Decimal adjust
1
1
*
*
@D
A +- (D)
1
1
*
*
N
A +- (N)
2
2
*
#N
A+- #N
2
2
*
@8A
(D) +- (8A)
1
4
*
@D
A+- AV(D)
1
1
*
N
A +- AV(N)
2
2
*
#N
A+- AV#N
2
2
*
@D
A+- AV(D)
1
1
*
N
A+- AV(N)
2
2
*
#N
A+- AV#N
2
2
*
@D
A +- A (D)
1
1
*
N
A +- A #(N)
2
2
*
#N
A +- A #N
2
2
*
DAA
CMP A, opr
CMP @D, opr
EOR A, opr
OR A, opr
AND A, opr
*
.
*
*
*
237
• MSM62580 . - - - - - - - - . . . , - - - - - - - - - - - - - - - - -
MNEMONIC
opr
OPERATION
FLAGS
BYTE CYCLE
C
P
H
Z
A
A+-A+1
1
1
D
D+-D+1
1
1
@D
(D) +- (D) + 1
1
1
*
N
(N) +- (N) + 1
2
2
*
A
A +- A-1
1
1
*
D
D+-D-1
1
1
@D
(D) +- (D)-1
1
1
*
N
(N) +- (N)-1
2
2
*
A
C;C .... A7 -0:1
1
1
*
*
@D
4C .... (D)7-0:::J
1
1
*
*
N
l;C .... (N)7-0:1
2
2
*
*
A
CC+-A7-0+l
1
1
*
*
@D
[C +- (D)7-0~
1
1
*
*
N
Cc +- (N)7-0~
2
2
*
*
1
3
1
2
CCR+-(SP -1), A+-(SP - 2),
SP+-SP+2
1
3
D
D+-SP+1, SP+-SP+1
1
2
JZ opr
addr
if Z= 1, PC+-PC+2+addr
2
2/3
JNZ opr
addr
if Z= 1, PC+-PC+2+addr
2
2/3
JC opr
addr
if C= 1, PC+-PC+2+addr
2
2/3
JNC opr
addr
if C=1, PC+-PC+2+addr
2
2/3
JB opr
baddr,addr
if(baddr) = 1,PC+-PC+ 3 +addr
2
3/4
JNB opr
baddr,addr
if(baddr) = 1, PC+-PC+3+addr
2
3/4
2
3/4
INC opr
DEC opr
,
RRC opr
RLC opr
PUSH opr
PSW
(SP)+-A,(SP -1)+-CCR,
SP+-SP-2
D
POP opr
PSW
(SP)+-D, SP""'SP-1
Rn-Rn-1, if Rn=O,
PC+-PC+2+addr (n=4-7)
DJNZ opr
Rn,addr
JMNE opr
#N,addr
if (D)
#N, PC-PC+3+addr
3
3/4
JDNE apr
#N,addr
itO", #N, PC+-PC+3+addr
3
3/4
238
"*
*
*
*
*
*
- - - - - - - - - - - - - - - - - - - - - - - - - . MSM62580 •
FLAGS
MNEMNIC
opr
OPERATION
BYTE CYCLE
C
2
2
2
4
(SP)+-PC+2,PC+-ZP,SP+-SP-2
1
4
PC+-(SP), SP+-SP + 2
1
3
No Operation
1
1
A+-O
1
1
RC
C+-O
1
1
0
SC
C +- 1
1
1
1
JMP opr
addr
CAL opr
addr
CZP opr
addr
RT
NOP
CLR opr
A
PC+-addr(O-4K)
~P)+-PC+2,
PC+-addr(O-4K)
P+-SP-2
baddr
(baddr) +- 0
2
2
SB
baddr
(baddr) +- 1
2
2
A
A+-A
1
1
C
C+-C
1
1
*
P
P+-C, if A=odd, C+-1 ELSE C+-O
1
1
*
SIN
C +- SIO
1
1
*
SOUT
SilO +- C
1
1
DELAY N+3 CYCLES
2
3-258
CHK opr
DLY opr
#N
H
Z
1
RB
CPL opr
P
*
*
239
OKI
semiconductor
MSM66301
OKI ORIGINAL HIGH PERFORMANCE
CMOS SINGLE-COMPONENT 8/l6-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The OKI MSM66301 is a an new generation, high performance single component microcontroller
inplemented in sill icon gate complementary metal oxide semiconductor technology (CMOS).
Integrated within this chip are 16-bit ALU, 16K bytes of mask program ROM, 512 bytes of data RAM,
48 I/O lines, built-in 16-bit timers, 1O-bit AID converter, serial I/O port pulse, width modulator (PWM),
and oscillator.
FEATURES
• 8-Bit External Data Bus Interface
• 16-Bit Internal Architecture
• 64K address space for program memory
(including 16K bytes onchip ROM)
• 512K address space for data memory
(including 512 bytes onchip RAM)
• High speed execution
Minimum Cycle for Instruction: 400ns
(10MHz)
• The Abundance of Powerful Instructions
8/16 data transfer operation
8/16 bit arithmetic operation
16(8) bit x 16(8) bit ~ 32(16) bit
32(16) bitl16 (8) bit ~ 32(16) bit
16(8) bit ± 16(8) bit ~ 16(8) bit
8/1 6 logic operation
Bit operation
Siring operation
User stack operation
ROM table access operation
• The same instruction allows both byte' and
word width operation according to Data
Descriptor.
That is to say, the same algorithm and the
same source program lines are applicable to
byte and word width data manipulation with
only changing Data Descriptor.
• Many Addressing Modes
240
•
•
•
•
•
•
•
•
•
8 Input lines, 40 InputiOutput lines
Built-in 16 bit timer x 4
Each timer has the following 4 modes.
Auto reload timer mode
Clock out mode
Capture register mode
Real time output mode
Serial Port x 1ch.
(variable bit length, baud rate generators for
transmitter & receiver)
Asyncronous normal mode
Asyncronous multi processor
communication mode
Syncronous normal mode
Syncronous multi processor
communication mode
16 bit Pulse Width Modulator x 2
Transition Detector x 4
10 bit A/D converter (8 channel)
1 non-maskable interrupt, 1 6 maskable
interrupts
Stand-by Function
software Clock stop
software CPU stop
hardware CPU stop
64 pin Shrink DIP/64 pin plastic flat
package/68 pin PLCC
- - - - - - - - - - - - - - - - - - - - - - - - . MSM66301 •
PIN CONFIGURATION
VDD
VREF
AGND
1
ADO/POO
AOf/POt
AD21P02
AOS/P03
PS7/A17
•
AD41P04
AD51P05
P5S/AIS
ADB/Poe
P54/AI4
AD71P07
P53/A13
P52/AI2
AS/P11
Al01P12
Al1!P13
A12/Pt4
P47ffRANS3
P4&ITRANS2
P45ITRANSf
A14/P16
P44ITRANSO
A1S/PH 1
P43/PWM1
A16/P20 1
P42/PWMO
P41/TM1CK
P4QITMOCK
CLKOUT/P23
P37fTM310
RESOUT 21
P36ITM21O
ALE
P35/TM11O
2
2.
PSEN
Rii
P34fTMOiO
P33/iNT"1
WR
P32/iNTO
READY,
P31/RXD
EA
7
RES
29
m
P30ITXD
P27IRXC
P26ITXC
OseD
P25/HLDA
6§lIT
P24IHOLD
GND
FUNCTIONAL BLOCK DIAGRAM
TMCK1
TMCKO
TMIO.
TMI02
TMlO1
EA
TMIOO
READY
-ALE
-~
-AD
-WR
RxD
RxD
RxC
TXC
TRANS3 -
ROM
TRANS.
TRANS1
AD7
TRANSG
ADD
VREF
A17-A10
"8
AGND
AS
PWM1
PWMD
SYSTEM CONTROL!
tt
V G
D N
D D
tllfnflft
00 C R R.F H H T T
SSLEELOLNN
CCKSSTLDTT
o 1 0 E 0 0 ·A. 1 0
U T U
T
PS
P4
P3
P2
PI
PO
T
2.41
eMSM66301
e----------------------------------__------------
PIN DESCRIPTION
Designation
Input/Output
Poo- P07/
ADo-AD7
I/O
P1O- P17/
I/O
As- A15
P20- P22f
A1S-A1S
P23/CLKOUT
P24/HOLD
I/O
P25/HLDA
P2s/TxC
Pu /RxC
P30/TxD
P31/RxD
P3211NTO
P3311NT1
P34/TMOI0
P35/TM110
P3s/TM210
I/O
Function
PO: a-bit I/O port. Each bit can ·be assigned to input or
output.
AD: Outputs the lower a bits of program counter during
external program memory fetch, and receives the
addressed instruction under the control of PSEN.
Also outputs the address, Outputs or inputs data
during an external data memory access
instruction, under control of ALE, RD, and WR.
P1 : 84:>it I/O port. Each bit can be assigned to input or
output.
A: Outputs the middle a bits of program counter
(PCa-15) during external, program memory fetch.
Also outputs the middle a bits of address during
an external data memory access instructions.
P2: 8-bit I/O port. Each bit can be assigned to input or
output.
A: Outputs the upper 3 bits of address during external
data memory access instructions.
CLKOUT: clock output pin. Output frequency range is
equal to or twice the system clock.
Input pin to request the CPU to enter the
HOLD:
hardware power-down state.
HOLD ACKNOWLEDGE: the HLDA signal
HLDA:
appears in reponse to the HOLD signal and
indicates that the CPU has entered the
power-down state.
Transmitter clock input pin.
TxC:
Receiver clock input pin.
RxC:
P3: -a-bit I/O port. Each bit can be aSSigned to input or
output
Transmitter data output pin.
TxD:
Receiver data input pin.
RxD:
Interrupt Request Input pin.
INT:
Falling edge trigger or level trigger is
selectable.
TMOIO - TM310: One of the following signals is output
or input:
clock twice the frequency range of the 16
bit timer overflow
load trigger signal to the capture register
input
s~tting value output
The signal that is input or output depends on the mode.
•
•
•
P37/TM310
242
- - - - - - - - - - - - - - - - - - - - - - - - - . MSM66301 •
PIN DESCRIPTION (Continued)
Designation
Input/Output
P4o/TMOCK.
P4dTM1 CK
P42/PWMO
1/0
P43/PWM1
P44-P4?1
TRANSO - TRNS:J
Function
P4: 8 bit 1/0 port. Each bit can be assigned to input or
output.
TMOCK, TM 1 CK: clock input pins of timer 0, timer 1 .
TRNS: Transition Detector.
The input pins which sense the falling edge
and set the flag.
PWM: Pulse Wide Modulator output pin.
P50-P5?1
AIO-AI?
INPUT
RESOUT
OUTPUT
Output 'H' level when the CPU is in RESET cycle.
Reset to 'L' level by program.
ALE
OUTPUT
Address Latch
Enable:
The timing pulse to latch the lower
8 bit of the address output from
port 0 when the CPU accesses the
external data memory.
PSEN
OUTPUT
Program Store
Enable:
The strobe pulse to fetch to external program memory.
RD
OUTPUT
Output strobe activated during a BUS read.
Can be used to enable data on to the bus from the
external data memory.
WR
OUTPUT
Output strobe during a bus write.
Used as write strobe to external data memory.
P5:
AI:
8 bit input port.
analog sygnal input pin to AID converter.
READY
INPUT
Used when the CPU accesses low speed peripherals.
EA
INPUT
Normaly set to 'H' level.
If set to 'L' level, the CPU fetches the code to external
program memory.
FLT
INPUT
If FLT is 'H' level, ALE, WR, RD, PSEN are set 'H' level
when reset.
If FLT is set to 'L', ALE, WR, RD PSEN are set to floating
level when reset.
RESET
INPUT
RESET input pin
243
• MSM66301 .--~------------------------------~--------------
PIN DESCRIPTION (Continued)
Designation
Input/Output
Oscillation circuit consists of OSCo, OSC ,.
OSCo,OSC,
NMI
Function
INPUT
non maskable interrupt input pin (falling edge)
VREF
reference voltage input pin for AID converter
AGND
ground for AID converter
VDD
system power supply
GND
ground
REGISTERS
15
•
ACCUMULATOR
•
CONTROL REGISTERS (CR)
0
C
ACC
pc
PROGRAM COUNTER
D
•
LOCAL REGISTER BASE
LRB
I
SYSTEM STACK POINTER
sSP
I
POINTING REGISTERS (PR)
INDEX REGISTER1
Xl
INDEX REGISTER2
X2
DATA POINTER
DP
usp
USER STACK POINTER
•
•
I
I
psw
PROGRAM STATUS WORD
LOCAL REGISTERS
erO
rl
rO
erl
r3
r2
er2
r5
r4
er3
r7
r6
SPECIAL FUNCTION REGISTERS (SFR)
All of the 1/0 functions are controlled by SFRs.Also, some of the internal functions (Timer, WDT,
etc, .. .) are controlled by SFRs. SFRs are located in the top of RAM space (OOOH - 007FH).
244
- - - - - - - - - - - - - - - - - - - - - - - - - - . MSM66301 •
MSM66301 Special Function Registers [1]
Address
0000
Name
System Stack Pointer
0001
0002
SSPl
R/W
8/16
FF
Program Status Word
PSWl
FF
R/W
8/16
unknown
R/W
8/16
00
lRBH
PSWH
Accumulator
ACCl
00
R/W
8/16
ACCH
0008
Source Index Register
0009
for Block Transfer
OOOB
When
reset
lRBl
0007
OOOA
8/16
Operation
SSPH
0005
0006
R/W
local Register Base
0003
0004
Abbrebiation
Destination Index Register
00
00
SI
R/W
16
unknown
01
R/W
16
unknown
CX
R/W
16
unknown
BSDI
R/W
8
unknown
SBYCON
R/W
8
00
WDT
R/W
8
PRPHF
R/W
8
01
R/W
16
unknown
R/W
8/16
00
for Block Transfer
Counter Register
OOOC
for Block Transfer
Source/Destination
OOOE
Bank Register
0010
Stand-By Control Register
0011
Watch Dog Timer
0012
Peripheral Control Register
0016
Work Area for Emulator
0017
0018
Interrupt Request Flag
0019
001A
IRQH
Interrupt Enable Flag
001B
001C
IRQl
IEl
00
R/W
8/16
00
IEH
External Interrupt
Control Register
EXICON
00
R/W
8
-
00
245
•
MSM66301·----------------------------------------~--------
MSM66301 Special Function Registers [2]
Name
Address
Abbrebration
R/W
8/16
Operation
When
reset
0020
Port 0 Data Register
P'O
R/W
8
Unknown
0021
Port 0 Mode Register
POlO
R/W
8
00
0022
Port 1 Data Register
P1
R/W
8
unknown
0023
Port 1 Mode Register
P110
R/W
8
00
0024
Port 2 Data Register
P2
R/W
8
unknown
0025
Port 2 Mode Register
P210
R/W
8
00
0026
Port 2 Special Function
Control Register
P2SF
R/W
8
00
0028
Port 3 Data Register
P3
R/W
8
unknown
0029
Port 3 Mode Register
P310
R/W
8
00
002A
Port 3 Special Function
Control Register
P3SF
R/W
8
00
002C
Port 4 Data Register
P4
R/W
8
unknown
0020
Port 4 Mode Register
P410
R/W
8
00
002E
Port 4 Special Function
Control Register
P4SF
R/W
8
00
002F
Port 5
0030
Timer 0 Counter
P5
R
8
TMO
R/W
16
0031
0032
00
Timer 0 Register
TMRO
R/W
16
0033
0034
Timer 1 Counter
TM1
R/W
16
Timer 1 Register
TMR1
R/W
16
Timer 2 Counter
TM2
R/W
16
Timer 2 Register
TMR2
R/W
16
003F
246
00
00
Timer 3 Counter
TM3
R/W
16
Timer 3 Register
TMR3
R/W
16
0030
003E
00
00
0038
003C
00
00
0039
003A
00
00
0037
0038
00
00
0035
0036
00
00
00
00
00
- - - - - - - - - - - - - - - - - - - ' - - - - - - - - . MSM66301 •
MSM66301 Special Function Registers [3]
Address
Name
Abbrebiation
R/W
8/16
Operation
When
reset
0040
Timer 0 Control Register
TCONO
R/W
8
00
0041
Timer 1 Control Register
TCON1
R/W
8
00
0042
Timer 2 Control Register
TCON2
R/W
8
00
0043
Timer 3 Control Register
TCON3
R/W
8
00
0046
Transition Detector Reg.
TRNS
R/W
8
00
0013
Stop Mode Buffer Flag
R/W
8
00
247
eMSM66301
e-----------------------------------------------MSM66301 Special Function Registers [4]
Address
Name
Abbrebiation
R/W
8/16
Operation
When
reset
0046
Transition Detector
TRNS
R/W
8
00
0048
Transmitter Clock Generator
STTM
R/W
8
00
0049
Transmitter Clock Generator
Control Register
STTMR
R/W
8
00
004A
Transmitter Control Register
STTMC
R/W
8
00
004C
Receiver Clock Generator
SRTM
R/W
8
00
0040
Receiver Clock Generator
Control Register
SRTMR
R/W
8
00
004E
Receiver Control Register
SRTMC
R/W
8
00
0050
Transmitter Mode Control Register
STCON
R/W
8
00
0051
Transmitter Data Buffer
STBUF
W
8
unknown
0054
Receiver Mode Control Register
SRCON
R/W
8
00
0055
Receiver Data Buffer
SRBUF
R
8
unknown
0056
Receiver Eroor Status Register
SRSTAT
R
8
00
0058
AID Scanning Mode Register
ADSCAN
R
8
00
0059
AID Select Mode Register
ADSEL
R/W
8
00
0060
AID Convert Result Register 0
ADCROL
R
8/16
unknown
R
8/16
unknown
R
8/16
unknown
R
8/16
unknown
R
8/16
unknown
8/16
unknown
R
8/16
unknown
R
8/16
unknown
ADCROH
0061
0062
AID Convert Result Register 1
ADCR1H
0063
0064
AID Convert Result Register 2
AID Convert Result Register 3
AID Convert Result Register 4
AID Convert Result Register 5
AID Convert Result Register 6
006F
248
ADCR6L
ADCR6H
0060
006E
ADCR5L
ADCR5H
006B
006C
ADCR4L
ADCR4H
0069
006A
ADCR3L
ADCR3H
0067
0068
ADCR2L
ADCR2H
0065
0066
ADCR1L
AID Convert Result Register 7
ADCR7L
ADCR7H
- - - - - - - - - - - - - - - - - - - - - - - - - - . MSM66301 •
MSM66301 Special Function Registers [5]
Address
0070
Name
PWM 0 Counter
R/W
8/16
Operation
R/W
8/16
PWM 0 Register
00
00
PWMROL
R/W
0074
PWM 1 Counter
00
00
PWMC1L
R/W
8/16
PWMC1H
0075
0076
8/16
PWMROH
0073
PWM 1 Register
00
00
PWMR1L
R/W
8/16
PWMR1H
0077
When
reset
00
PWMCOL
PWMCOH
0071
0072
Abbrebiation
00
0078
PWM 0 Control Register
PWCONO
R/W
8
00
007A
PWM 1 Control Register
PWCON1
R/W
8
00
249
• MSM66301 .~~----------------------------------------------
ADDRESSING MODE
The MSM66301 supports 512KB (64KB x 8BANKs) 05 data space and 64KB of prog~am space
with verious typeS of addressing methods. These methods divide into the following types.
1. RAM ADDRESSING (FOR DATA SPACE)
1.1
Register Direct Addressing
RDR
DP
l-·--------l»/WffiDP0%/ffiJ
1.2 Displacement Addressing
a) Zero Page
[~
OOOH
L
0010H
o
b) Direct Page
r - - ex.
ST
off XXI OH
A,
xxOOH
,
,
RAM
!.. - - - - - - - --
xxl0H
1.3 POinting Register Indirect Addressing
a) Data Pointer (DP) Indirect
[DP]
SLL
---;-
,
!
DP
b) User Stack Pointer (USP) Indirect
r - - - ex. ----------------------------~----------------------------_,
SRL
10H
[USP]
1
r'------,.U"'S.."P--0-255
250
RAM
- - - - - - - - - - - - - - - - - - - - - - - - - . MSM66301 •
c)
Index register (X1, X2) Indirect
ex.
---------------------------------~
INC
[X 11
300H
I ,.,~,
X1
1.4 Immediate Addressing
MOV
SSP,
#
~~27~F~H~~
;1
2. ROM ADDRESSING (FOR PROGRAM SPACE)
2.1
Direct Addressing
L
_
_I------.JI.
_~
'-------Fh0WflVA
ex. _ J M P- , - - - - - 2 0 0 H
_ROM
0>,,"
"
2.2 Pointing Register Indirect Addressing
a) Data Pointer (DP) Indirect
[~
LC
[DP]
DP
b) User Stack Pointer (USP) Indirect
ex.---·--------------------------------------------,
10H
[USP]
T~55 ~I
i_-..:::.;US;:.:..p_----'
-
T
~
c) POinting Register (X1, X2, DP, USP) Indirect with 16bit displacement
ex.
----------------------------------------------------~--~
CMPC
300H
[X1]
--I
I'
X1
0-65535
251
, • MSM66301 . - - - - - - - - - - - - - - - - - - - - - - - - -
INSTRUCTIONS
Data Transfer
Instruction
Function
L
A,-
A
--
ST
A,_
A
--+
MOV
*, A
*
MOV
-, #
*
MOV
er. _
er
MOV
d, *
(d)
MOV
DP, _
DP
MOV
X1, _
X1
MOV
X2,_
X2
MOV
USP, *
USP
MOV
PSW,.
PSW
MOV
SSP, •
SSP
MOV
LRB,.
SSP
CLR
*
SWAP
*
-
-
-
Function
LB
A, *
AL
-
-
STB
A,*
AL
--+
A
MOVB
A, *
AI--
Imme.
MOVB
-,A
MOVB
*,
*
---
--
-*
-
Instruction
#
MOVB
r, -
MOVB
d, *
MOVB
PSWO, *
MOVB
SCB,-
CLRB
*
--r
*
*
AL
1m me.
--
-
(d)
PSWO
SCB
*
-*
*
*
-
*
0
-- 0
A15-8~A7-O
SWAPB
A7-4-A3-0
XCHGB
AL-*
XCHG
A,
A-*
XNBL
A,
A3-0---*3-0
TRNS USP, LRB
USPW3
USP2-0
TRNS LRB, USP
LRB,2'-O
LRB'5-'3
--
--
LRB'2-0
0
USP,5-3
0
Push & Pop
Instruction
Function
Instruction
Function
PUSHU
*
•
--+
USER STACK
PUSHUB
*
*
POPU
A
A
-
USER STACK
POPUB
A
AL -
PUSHS
*
-
POPS
*
* -
252
--+
SYSTEM STACK
SYSTEM STACK
--+
USER STACK
USERSTACK
- - - - - - - - - - - - - - - - , - - - - - - - - - - - . MSM66301 •
Rotate & Shift
Function
Instruction
ROL
•
Rotate
ROR
•
Rotate
SLL
•
Shift
SRL
SRA
·
·
Shift
Shift
-
-
Function
Instruction
ROLB
•
Rotate
RORB
•
Rotate
Logical
SLLB
·
Shift
Logical
SRLB
*
Shift
Arithmetic
SRAB
•
Shift
-
-
-
Logical
Logical
Arithmetic
Increment & Decrement
Instruction
Function
Instruction
Function
-
INC
· •-
*+1
INCB
*
DEC
*
*-1
DECB
· •-
*
-
*
*+1
*- 1
ROM Table Reference
Instruction
Function
LC
A,*
A -
CMPC
A,*
A-. (ROM)
• (ROM)
Instruction
Function
LCB
A,*
AL -
• (ROM)
CMPCB
A, •
AL - * (ROM)
253
• MSM66301 • - - - - - - - - - - - - - - - - - - - - ' - - - - - - - Arithmetic Operation
Instruction
Function
MUL
er1: A
DIV
erO: A
ADD
A, *
A
ADD
*, A
*
ADD
*, d
*
ADD
*, #
*
ADC
A, *
A
ADC
*, A
*
ADC
*, d
*
ADC
*, #
*
SUB
A,*
A
SUB
*, A
*
SUB
*, d
*
SUB
*, #
*
SBC
A, ..
A
SBC
*,A
*
SBC
*, d
*
SBC
*, #
*
254
-
-
-
-
-
-
-
-
-
Instruction
Function
AXerO
MULB
A.
erO: Afer2
DIVB
A
A+*
ADDB
A, *
AL
*+A
ADDB
*,A
*
* + !d)
ADDB
*, d
*
* + Imme.
ADDB
*, #
*
A+* +C
ADCB
A,*
AL
* +A+C
ADCB
*,A
*
* + (d) +C
ADCB
*, d
*
* +Imme. +C
ADCB
*, #
*
SUBB
A, *
AL
*-A
SUBB
*,A
*
* - (d)
SUBB
*, d
*
* -Imme.
SUBB
*, #
*
A-*-C
SBCB
A, *
AL
*-A-C
SBCB
*,A
*
* - (d) - C
SBCB
*, d
*
* -Imme.-C
SBCB
*,#
*
A- *
-
-
-
ALxrO
AfrO
AL +*
* +AL
* + (d)
* + Imme.
-
AL +* +C
* +AL +C
-
* + (d) +C
-
* +Imme. +C
-
-
-
-
-
AL -*
*-AL
*- (d)
* -Imme.
AL -* C
* - AL - C
* - (d) - C
* -Imme. - C
- - - - - - - - - - - - - - - - - - - - " ' - - - - - . MSM66301 •
Logical,Operation
Instruction
Function
AND
A,.
A
AND
-, A
*
AND
*, d
-
AND
-, #
-
OR
A,-
A
OR
-, A
-
OR
-, d
-
OR
-, #
-
XOR
A, -
A
XOR
*, A
-
XOR
*, d
*
XOR
-, #
*
Function
Instruction
Aand *
ANDB
A, •
AL
~
* and A
ANDB
-,A
•
~
- and (d)
ANDB
" d
- and Imme.
AN DB
" #
-
A or-
ORB
A,-
AL
~
- or A
ORB
-,A
-
~
- or (d)
ORB
-, d
~
- or Imme.
ORB
-, #
-
Axor *
XORB
A, -
AL
- xor A
XORB
*,A
~
* xor (d)
XORB
*, d
~
* xor Imme.
XORB
-, #
-
~
~
~
~
~
.
AL and·
~
~
• and AL
~
* and (d)
- and Imme.
~
AL or-
~
- or AL
~
* or (d)
~
- or Imme.
~
~
AL xor* xor AL
~
- xor (d)
~
- xor Imme.
~
Comparison
Instruction
Function
Instruction
Function
CMP
A, *
A- *
CMPB
A, *
AL
CMP
*, A
*- A
CMPB
*, A
* -AL
CMP
-, d
- - (d)
CMPB
*, d
* - (d)
CMP
-, #
- -Imme.
CMPB
*,
#
-
*
* -Imme.
255
eMSM66301
e--------------------------------------------------
Stack Operation
Instruction
Function
ADD A. [+USP]
USP
ADC A. [+USP]
USP
SUB A. [+USP]
USP
SBC A. [+USP]
USP
ANDA. [+USP]
USP
ORA.[+USP]
USP
XOR A. [+USP]
USP
CMP A. [+USP]
USP
-
USP+2,A
USP+2,A
USP+2,A
-
USP+2,A
USP+2,A
-
USP +2,A
USP +2,A
-
-
-
A + [USP]
A +[USP] +C
A- [USP]
A- [USP]-C
A and [USP]
Aor [USP]
Axor [USP]
USP + 2, A - [USP]
Decimal Adjust
Instruction
Function
DAA
Decimal Adjust for Add
DAS
Decimal Adjust for Substruct
Bit Operation
Instruction
Function
SBR
*
bit
RBR
*
bit
MBR
C, *
C
MBR
*, C
bit
TRB
*
Z
-
-
-
Instruction
1
SB
*
bit
0
RB
*
bit
bit
MB
C, •
C
C
MB
*, C
bit
bit
Execute
Instruction
EX
256
Function
*
Function
Execute Specified Data as the'lnstruction
-
1
0
bit
C
- - - - - - - - - - - - - - - - - - - - - - - - - . MSM66301 •
Jump & Call
Instruction
Short Jump
SCAl
Jump
CAL
adrs
SJ
I
*
"
Instruction
Function
Function
adrs
Short Call
* Call Subroutine
JC
EQ, adrs
Jump if '='
JC
NE, adrs
Jump if' 'f-
>' x
JC
lE, adrs
Jump if '< ='
JC
IT,adrs
Jump if'*'
<
JC
GE, adrs
Jump if'
JC
GT, adrs
Jump if'
>
='
<
='
JBS bit, adrs
Jump if bit-on
JBR bit, adrs
Jump if bit-off
JRNZ, DP, adrs
loop Function
VCAladrs
Vector Call
Return
Instruction
Function
RT
Return from Subroutine
RTI
Return from Interrupt
String Operation
Instruction
Function
SMOVI
String Transfer with Increasing Pointers
SMOVD
String Transfer with Decreasing Pointers
SCMP
String Compare
Others
Instruction
Function
-
SC
C
SS
STACK FLAG
NOP
No Operation
Instruction
1
-
1
Function
-
RC
C
BRK
Software Reset
0
(Note)
'#' and 'imme.'
'..-J and '-'
Addressing expression (See Addressing mode)
Immediate value
Bit-shift direction
257
8 B,IT SERIES (INTEL COMPATIBLE)
OKI
semiconductor
MSM80C35/48
MSM80C39/49
MSM80C40/50
CMOS 8-BIT SINGLE CHIP MICROCONTROLLER
, GENERAL DESCRIPTION
The OKI MSM80C48/MSM80C49/MSM80C50 microcontroller is a low-power, high-performance
8-bit single chip devicer implemented in silicon gate complementary metal oxide semiconductor
technology. Integrated within these chips are 8K/16K/32K bits of mask program ROM,
512/1024/2048 bits of data RAM, 27 I/O lines, built-in 8 bit timer/counter, and oscillator. Program
memory and data paths are byte wide. Eleven new instructions have been added to the NMOS version's instruction set, thereby optimizing power down, port data transfer, decrement and port float
functions.
Available in 40-pin plastic DIP (RS) or 44-pin plastic flat packages (GSK).
FEATURES
• Lower power consumption enabled by CMOS
silicon gate process
• Completely static operation
• Improved power-down feature
• Minimum instruction cycle 1.36 p,s (11 MHz)
@VCC=+5V±10%
11 MHz version of MSM80C50 (6 MHz <
XTAL 1.2 < 11 MHz) is under development.
•
•
•
•
•
•
• Every signal input terminal is provided with a
Schmitt circuit, except XTAL 1 Pin.
• Every signal output terminal is capable of
driving a standard TTL, except XTAL2 Pin.
• 111 instructions
• All instructions are usable even during
execution of external ROM instructions.
• Operation facility
Addition, logical operations, and decimal
adjust
1K x 8 bits
• Program memory (ROM)
(MSM80C48)
2K x 8 bits
(MSM80C49)
4K x 8 bits
(MSM80C50)
64 x 8 bits
• Data memory (RAM)
(MSM80C48)
128 x 8 bits
(MSM80C49)
256 x 8 bits
(MSM80C50)
•
•
•
•
•
•
•
Two sets of working registers
External and timer interrupts
Two test inputs
Built-in 8-bit timer counter
Extendable external memory and I/O ports
Input/output ports
Input/output ports
- 8 bits x 2
Data bus input/output
- 8 bits x 1
Single-step execution function
Every Signal input terminal is provided with a
Schmitt circuit, except XTAL 2 Pin
Every signal output terminal is capable of
driving a standard TTL, except X'tal ,2 Pin.
Wide range of operating voltage, from +2.5V
to +6V of VCC.
High noise margin action
Two kinds of package; 40-pin plastic DIP and
44-pin plastic flat package
Compatible with Intel's 8048, 8049 and 8050
261
• MSM80C35/48, 80C39/49, 80C40/50
.1--------------
FUNCTIONAL BLOCK DIAGRAM
DATA MEMORY (AAM)
64 x 8 MSMBOC48RS
128 x 8 MSM80C49RS
SINGLE
STEP
256
~
8 MSM80C50AS
PIN CONFIGURATION
(Top View) 40 Lead Plastic DIP
TO
T1
XTAL2
RESET
P2 7
P2 6
55
P2,
INT
P2.
EA
P1 7
AD
Pl.
?SEN
Pl,
WR
Pl.
ALE
P13
DBo
Pl,
DB,
Pl,
DB,
Plo
DB3
VDD
DB.
DB,
PROG
DB7
P23
P2,
P2,
Vss
P2 0
DB.
262
Vee
XTAL1
Pin Name
P1 0 - P1 7
P2 0 - P27
DBo - DB7
TO, T1
INT
RD
WR
ALE
PSEN
RESET
SS
EA
XTAL 1, 2
:
:
:
:
:
:
:
:
:
:
:
:
:
I nput/output port (PORTH
Input/output port (PORT2)
Data bus port (BUS PORT)
Test
Interrupt
Read
Write
Address Latch Enable
Program Store Enable
Reset
Single Step
ROM Mode
Crystal Controlled Oscillator
- - - - - - - - - - - - - -...... MSM80C35/48, 80C39/49, 80C40/50 •.
PIN DESCRIPTION
Designation
InputlOutput
Function
PI 0- PI7
(PORT I)
Input/Output
8-bit quasi-bidirectional port
P20-P27
(PORT 2)
Input/Output
8-bit quasi-bidirectional port
The high-orderfour bits of external program memory addresses can be
output from P20-P23, to which the 1/0 expander MSM82C43RS may also
be connected.
DBo-DB7
(BUS)
Input/Output
Bidirectional port
The low-order eight bits of external program memory address can be
output from this port, and the addressed instruction is fetched under the
control of PSEN signal. Also, the external data memory address is output, and
data is read and written synchronously using RD and WR signals.
The port can also serve as either a statically latched output port or a
non-latching input port.
TO
(Test 0)
InputlOutput
The input can be tested with the conditional jump instructions JTO and
JNTO. The execution of the ENTO ClK instruction causes a clock output to
be generated.
T1
Input
The input can be tested with the conditional jump instructions JTI and
JNTI . The execution of a STRT CNT instruction causes an internal
counter inputlo be activated.
!NT
Input
Interrupt input. If interrupt is enabled, INT input initiates an interrupt.
Interrupt is disabled after a reset.
Also testable with a JNI instruction. Can be used toterminate the
power-down mode. (Active"O"level)
(Interrupt)
RD
(Read)
Output
WR
(Write)
A signal to read data from external data memory. (Active "O"level)
A signal to write data to external data memory. (Active "O"level)
ALE
Address &
Data latch
Clock
This signal is generated in each cycle. It may b:: :.:sed as a clock output.
External data memory or external program memory is addressed upon the
falling edge. Forthe external ROM, this signal is used to latch the bus port
data upon the ALE signal rise-up after the execution of the OUll BUS, A
instruction.
PSEN
Program
Store Enable
Output
A signal to fetch an instruction from external program memory
(Active "0" level)
RESET
Output
(RESET) input initialize the processor. (Active "O"level)
Used to terminate the power-down mode.
SS
(Single Step)
Output
A program is executed step by step. This pin can also be used to control
internal osci lIation when the power-down mode is reset.
(Active"O"level)
EA
(External Access)
Input
PROG
(Expander Strobe)
Output
When held at high level, all instructions are fetched from external memory.
(Active "I "level)
This output strobes the MSM82C43RS 1/0 expander.
263
• MSM80C3S/48, 80C39/49, 80C40/50 .------....,..----.;...-------
PIN DESCRIPTION (CONT.)
Designation
Input/Output
Function
XTAL 1
(Crystal 1)
Input
XTAL2
(Crystal 2)
Output
VCC
-
Power supply terminal
VOO
-
Standby control input. Normally, "1" level. When set to "O"level,
oscillation is stopped and processor goes into sta.ndby mode.
VSS
-
GNO
One side of the crystal input for the internal oscillator. An external source can
also be input.
Other side of Crystal input for internal oscillator.
Note: The required RESET pulse duration is at least two machine cycles under the condition that the power supply
and the oscillator have been stabilized.
264
----------~---_e. MSM80C3S/48, 80C39/49, 80C40/S0 •
ADDED FUNCTIONS OF MSM80C48, MSM80C49 AND MSM80C50
The MSM80C48, MSM80C49 and
MSM80C50 basically incorporate the capabilities of Intel's 8048, 8049, and 8050 plus the following new functions:
1.
Power-Down Mode Enhancements
1 .1 Power-down by software
(1)
(2)
(3)
Clock (See item 4, "Power-down mode", for
details.)
a. Crystal-controlled oscillator halt (HLTS
instruction)
Power requirements can be minimized.
b. Clock supply halt (HALT instruction)
Restart is accomplished without oscillator wait.
1/0 ports (See Table 4-1 and 4-2 for
details.)
110 port floating instructions
Power consumption resulting from inputsl
outputs can be minimized with FLT and
FLTT instructions.
Port floating is cancelled !!Lexecuting
FRES instruction, "0" level at INT pin or "0"
level at RESET pin.
Six types of power-down can be done by a
combination of HL TS/HAL T and FL TIFLTT
instructions.
ing up the rise time of the output signals.
When these ports are used as input ports,
the internal pullup resistance becomes approximately 9 kf! when input data is "1".
The internal pullup resistance rises to ap':
proximately 100 kf! when input data is "0".
Thus, a high noise margin can be obtained by
selecting the impedance and thus the outflow of
current is minimized whenever these ports are
used as output or input ports.
3.3 Clock generation control via the SS
terminal
When the crystal-controlled oscillator is
halted in the HLTS or hardware power-down
mode, the SS terminal is pulled down by a resistor of 20 - 50 kn, while its internal pullup resistor of 200 - 500 kn is isolated from VCC. When
the power-down mode is cancelled, the internal
resistor of the SS terminal is changed from pulldown to pullup. Consequently, the CPU can be
halted for any period of time until the crystalcontrolled oscillator resumes normal oscillation
when a capacitor is connected to the SS terminal.
4.
Power-Down Mode
1.2 Power-down by hardware (See 4.3,
Power-down mode by VDDpin utilization
for details.)
Crystal-controlled oscillators can be halted
by controlling the VDD terminal, thereby floating
all 1/0 ports for minimum power consumption.
The MSM80C48, MSM80C49, and
MSM80C50 power-down mode can be enabled
in 2 different ways-through software by a combination of clock control and port floating
instructions, and through hardware by control of
theVDD pin.
2.
4.1 Software power-down mode
Power-down mode can be done by a combination of the following instructions.
Additional Instructions (11)
HLTS
HALT
FLT
FLTT
FRES
MOVA, P1
3.
MOVA, P2
MOVP1,@ R3
MOVP1 P, @R3
DEC @Rr
DJNZ @ R, addr
(1 )
Instruction
code:
3.2 P1 0 - 7 and P20 - ?
The MSM80C48, MSM80C49 and
MSM80C50 are designed to minimize power
consumption when P1 0 - 7 and P20 - 7 are used
as input/output ports, to maximize the performance of CMOS.
When these porfs are used as output ports,
the acceleration circuit is actuated only when
output data changes from "0" to "1 ", thus speed-
I0
0 0 0 I0 0 0
1
I
Although crystal-controlled
oscillator operation is continued, the clock supply to
the CPU control circuit is
halted and CPU operations
suspended. When cancelling
this software mode, restart is
accom plished without oscillator wait. Timing charts
are outlined in Figs. 4-1 and
4-2.
HLTS (oscillation stop)
Description:
Improved Uses of BUS Po - 7, P1 0 - 7,
P20 - 7, and SS terminals
3.1 BUSPo-7
The MSM80C48, MSM80C49, and
MSM80C50 remove the limitation on the use of
OUTL BUS, A instructions during the external
ROM access mode by having an independent
data latch and external ROM mode address
latch in BUS Po - 7.
Consequently, there is no need to relocate
bus port instructions when in the external ROM
access mode.
HALT (clock supply halt to control circuit)
(2)
Instruction
code:
Description:
rl-1~·-0--0--0--1-0--0--1--0~
The oscillator operation is
halted and CPU operations
suspended. In cancelling
this power down mode, connecting a capacitor to the SS
pin enables a reasonable
265
• MSM80C35/48, 80C39/49, 80C40/50 .---r------~---~
(3)
wait period to be. accomplished before normal operation is resumed. [Except iT
the case of using the RESE
pinJ
Timing charts are outlined in
Figs. 4-3 and 4-4.
FL T (floating P1 0 - 7, P20 - 7, and SPo - 7)
Instruction
code:
101
000 1 0
I
Description·
~
Internal ROM
mode
PI
(4)
External ROM mode
Floating
P2
Floating
BP
Floating
Floating
P20 -- 3 operation
P2. - 7Iloating
Operation
Details of IC pin status as a result of executing the FLT instruction are shown in Table
4-1.
FLTT (floating of alloutput pins)
Instruction
code:
Description·
~
Internal ROM
mode
External ROM mode
ALE
Floating
Operation
PSEN
Floating
Operation
PROG
Floating
Floating
WR
Floating
Floating
RD
Floating
Floating
Floating
Floating
TOOUT
PI
Floating
Floating
P20 -- 3 operation
P2
Floating
BP
Floating
Operation
XTAL
Operation
Operation
P2. -
7
floating
Details of IC pin status as a result of executing the FLTT instruction are shown in Table
4-2.
Example 1: Power-down mode accomplished by stopping oscillation.
o Setting by execution of
HLTS [82HJ instruction.
Example 2: Power-down mode accomplished by stopping the clock
supply to the CPU control
circuit.
o Setting by execution of
HALT [01 HJ instruction.
Example 3: Power-down mode by floating
of P1 0 - 7, P20 - 7 and SPo 7, and subsequent stopping of
CPU oscillation.
266
o Setting by first executing
the FLT[A2 HJ instruction
and then the HLTS[82HJ instruction.
Example 4: Power-down mode by floating
P10 - 7, P20 - 7 and SPo - 7,
and then stopping the clock
supply to the CPU control circuit.
o Setting by first executing
the FLT[A2HJ instruction,
and then the HALT[01 HJ instruction.
Example 5: Power-down mode by floating
all output pins, followed by
stopping oscillation.
o Setting by first executing
the FLTT[C2HJ instruction
followed by execution of
the HLTS[82HJ instruction.
Example 6: Power-down mode by floating
all output pins, followed by
stopping of the clock supply to
the CPU control circuit.
o Setting by first executing
the FLTT[C2HJ instruction,
followed by execution of
the HALT[01 HJ instruction.
4.2 Cancellation of software power-down
mode
The power-down mode status outlined
above in examples 1 to 6 can be cancelled by
using either the interrupt pin or the RESET pin.
(1) Use of the INT pin during external interrupt
enabled mode (j.e. following execution of
EN I instruction).
o The clock generator is activated and the
CPU started J!Q.. when a "0" level is applied to the INT pin. If this "0" level is
maintained until at least 2 ALE output
'signals occur, an external interrupt is
generated, and execution proceeds from
address 3. If, however, the power-down
mode has been done during the interrupt
processing routine, execution is
resumed just after the power-down
instruction.
(2) Use of the INT pin during external interrupt
disabled mode (j.e. following execution of
DIS I instruction or hardware reset)
o The clock generator is activated and the
CPU. started .!!Q.. when a "0" level is applied to the INT pin. If this "0" level is
maintained until at least 2 ALE output
signals occur, execution is resumed just
after the ~ower-down instruction.
(3) Use of the R SET pin
o The clock generator is activated and the
CPU started-':!.P....Y'Lhen a "0" level is applied to the RESET pin. If this "0" level is
maintained until at least 2 ALE output
signals occur, the CPU is reset and execution proceeds from address '0. In case
cancellation is done in oscillation stop
mode, the "0" level must be input to the
RESET PIN uritil oscillation is stabilized.
---------------e. MSM80C35/48, 80C39/49, 80C40/50 •
Table 4-1
Pin No.
Details of Pin Status Following Execut.ion of FLT Instruction
Pin Name
Internal ROM
External ROM
1P
TO
Active
Active
2P
XTAL1
Active
Active
3P
XTAL2
Active
Active
4P
RESET
Active
Active
5P
SS
200 - 500 kO pullup
200 - 500 kO pullup
6P
INT
Active
Active
7P
EA
Active
Active
8P
RD
Active
Active
9P
PSEN
Active
Active
10P
WR
Active
Active
11 P
ALE
Active
Active
12P
DBO
Floating
Active
13P
DB1
Floating
Active
14P
DB2
Floating
Active
15P
DB3
Floating
Active
16P
DB4
Floating
Active
17P
DB5
Floating
Active
18P
DB6
Floating
Active
19P
DB7
Floating
Active
20P
VSS
o [V]
o [V]
21P
P20
Floating
Active
22P
P21
Floating
Active
23P
P22
Floating
24P
P23
Floating
25P
PROG
Active
Active
26P
VDD
"1 "level
"1" level
27P
P10
Floating,
Floating
28P
P11
Floating
Floating
29P
P12
Floating
Floating
30P
P13
Floating
Floating
31P
P14
Floating
Floating
32P
P15
Floating
Floating
Floating
AcUve
..
Active
33P
P16
Floating
34P
P17
Floating
Floating
35P
P24
Floating
Floating
36P
P25
Floating
Floating
37P
P26
Floating
Floating
Floating
38P
P27
Floating
39P
T1
Active
Active
40P
Vee
+2 to +6 [V]
+2 to +6 [V]
Note: The FLT mode itself is reset by executing the FRES instruction, or supplying "O"level to INT or RESET pin.
267
• MSM80C35/48, 80C39/49,80C40/50 . , - - - ' - - - - - - - - - - - - - Table 4·2
Pin No.
Pin Name
Internal ROM
External ROM
1P
TO
Floating if output enabled
Floating if output enabled
Active
2P
XTAL1
Active
3P
XTAL2
Active
Active
4P
RESET
Active
,Active
SS
200 to 500 kO pullup
INT
Active
5P
6P
~
200 to 500
kO~ pullup
Active
7P
EA
Active
Active
8P
RD
Floating
Floating
PSEN
Floating
Active
10P
.WR
Floating
Floating
,11P
ALE
Floating
12P
DBO
Floating
13P
DB1
Floating
Active
14P
DB2
Floating
Active
15P
9P
\
Details of Pin Status Following Execution of FLTT Instruction.
,
Active
Active
DB3
Floating
Active
16P
DB4
Floating
Active
17P
DB5
Floating
Active
18P
DB6
Floating
Active
19P
DB7
Floating
20P
VSS
o[V)
o [V)
21P
P20
Floating
Active
22P
P21
Floating
Active
23P
P22
Floating
Active
24P
P23
Floating
Active
25P
PROG
Floating
Floating
26P
VDD
11'1" level
"1 "level
27P
P10
Floating,
Floating
28P
P11
Floating
Floating
29P
P12
Floating
Floating
30P
P13
Floating
Floating
31P
P14
Floating
Floating
32P
P15
Floating
Floating
33P
P16
Floating
34P
P17
Floating
35P
P24
Floating
Floating
36P
P25
Floating
Floating
37P
P26
Floating
Floating
38P
P27
Floating
Floating
39P
T1
Active
Active
Vee
+2.5to+6M
+2.5 to +6 [V)
40P
Active
"
Floating
.
Floating
Note: The FLTT mode itself is reset by executing the, FRES instruction, or supplying "0" level to INT or RESET pin.
268
-
----------------e. MSM80C35/48, 80C39/49, 80C40/50 •
•1
'T11T21T31
1 I '1
I
I
II
T4
nnnnnnnnnnnnn nnnn n
XTAL 1
0'UUUpUUpUUpUU""UUU~~4
1:o :
---+""1 ~
I '
I
' I
m':
I r-!1---!f1-1
f T l .:H I'
I'
I
I
I
,
I
I
I
. I
I
I
1
I
I L-r-I-+-1
I I:
I
:
:
IHALT EXECUTErl
! !I
I
I
I
CPU MODE -f----lRUN
I
STOP-{!
I
'I
RUNI
:
:
XTAL1 2 ~1_~I~~i-~I--~,~--~~I-~I,RUN-~--~:~I~I_~-+_~_,_~I_+II:
"
:
I I I
I
I
I
ALE
. 'I
:
1 I
I
RESET
i
I
I
(
:
:
I
':
II,'
O'T--I""-~------I
I
I
I
,
I
I
I
I
I
I
I
:
-+---'
I
'
:
I
: : : :
X'TAL1
1
0
1
'
,
I
I
I
,
I
:': : : I :
* Cancellation Condition: Use RESET pin.
Fig. 4-1
,
' " , '
III
~--I--J.-.-"'I"-T--II
I
1
I
I
RESET EXECUTE I :
I
:
:
:
:
:
I
I
HALT [01 H] Instruction Execution Timing Chart
I
UJL
, ' I
i
'
m:
I: -t--I-::
ALE
,
,
li
rtr4---t-
11::'1
(f
oI I I I
I '+,
-t-',
I
I i
I
:
:
IHALT EXECUTEI-l
I
I :I i :
'
CPU MODE f----+RUI')I
STOP-fl
I:
IR~~
I
I
X'TAL 1 . 2 I
:
1
I"
'IRUN--t----"'--!I'""II---+-.;_--i---i--i-I--tiI
I
1
I
I
"
I
I
I
I
11
I
,I
I
I
I
I
I
INT
I
I
I
I
I
I I
"I
I
I
O+---,--r-t--------L.--t""-T---i--+--~"T--I...-T-,-I-~-rI
I
I
I
I
,
I
.
,
,
I
,
INTER~UPT EX~CUTE i
I -i
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I,
,I,
I
I
I
I
I
* Cancellatio~ Conditio'n: Use I NT pin.
I
I
I
,I
I
I
I :
i
Fig.4-2 HALT [01 H] Instruction Execution Timing Chart
I.
:.T1
X'TAL 1
i T2 I T3 I
1 nnnnnnnnnn~--+'I~"""
O'~Uu",uu!luu!---f:
I
I
I
ALE
1 I
I
I II""-+I---!I--I-o
I
I
I
I. I
:
I
0:.r
I
HLTS EXECUTE-'
,
: I I
CPU MODE -r---jRU~---rSTOPf·t='o:t'S~C:-'-";.,.t
..V-O~kI-E..........;--+-~-+1 Ry~I-";-"---4--+----"'---+--1X'TAL l ' 2 -t----!RUN-+STOPfl-j----1 ,
IRUN-+--+-.L--+-~-+I
I
I
I
RESET pin must bel
I I I
I
I
I
I
held at "0" level
I
I' ,
l'
I
I
,
until the oscillation I
I :'
I
RESET
I
I
I..L
becomes norma!.
I
I
I
I
I
O~--r-t--I-""'--'
,
I
-t--~I
!:
1
I
I
I
I
I
I:
I
I'
I
I
j--r-t--l--tI
0 I
I
J
I
:
I
I
I
_! I "
1_
I I
I'
SS 200-500Kn ,
r 55 200I I
IRESET EXECUTE
'PULLUP'
'500Kn ,I
,I"'"
55 20-50KO PULLDOWN
PULLUP
Cancellation Condition: Use RESET pin.
55
*
I
.,
,!'
i
I
I
-,
,
FIg. 4-3 HLTS [82H] Instruction Execution Timing Chart
269
• MSM80C3S/48, 80C39/49, 80C40/S0 . , - , - - - - - - - - - - - - - -
;.
.
IT1'T21T31
,.'
T4
-
I
..
I
IT51Tl'T2'T'T4'T51Tl'T2'T3'T4,T51
IIII'!/~
X'T AL 1
~.JUUl1UUl1UlflI--'JJU
ALE
I
1 I
I
I
I
I
Ol!
:
I
I
I
"
I II
'·1
I
,,1
I
I
I
I
I
I
i I'
I.'
I
,
I
I
,
,
I
'HLTS EXECUTE-J
,
T--'lRUN----I-STOP{f I
I, I
HRU~--l-STOP/~OSC E'!,OKE
I
,
I
I
When,,! 0.47 /.IF capacitor is-l 50- ~ ,
connected to the SS pin,
GOms
'
50-60 ms wait
WAIT
:
CPU MODE
X'TAL 1· 2
I
I
I
I
I
,
1!
I
I
I
I '
I
I
,
I
I
I,!:
IRUN
I
' RUN
I
,I
I
I
I
I
I
I
'
I
.1.
I
J
,
,
,
I
,
I
I rTli
i
,
I
I
"
I
I
I
I,1!l..L...-...i: I ,
I
I
I
!
!!
I
,
I
'
I
I
I
I
I
I
I
,
,
-,
I
::
I , '
I
I
I
I'·-+--r-.J--.,--.l.--1"--~I
,I
I I
i i ',
O~--T---~-t------·
I
'I'
I '
I
ri i :, ,I
-!
'I
I
I
,
I
:
I
"
,
1m'
,
I
I
I:
'_','
I SS 200-'
,.:
I 500KnpULLUP
SS 20-50Kn PULLDOWN
SS 200-500Kn ,.
i PULLUP ,
:
: : I:
,,!,
I
INTERRUPT EXECUTE'
'"
I
I
I
I
I.
'
i
I
,
,
,
* Canceilation Condition: Use INT pin.
Fig.4-4
HLTS [82H] Instruction Execution Timing Chart
4.3 Hardware power-down mode
In the MSM80C48, MSM80C49 and
MSM80C50, forcing the level at the VDD pin [pin
261 to a "0" during either external ROM or internal ROM mode results in suspension of the oscillator function and subsequent floating (high
impedance) of all the 1/0 pins except the RESET,
SS and XTAL 1/2 pins. The CPU is thereby
stopped while maintaining internal status.
Details of the IC pin status at this time are outlined in Table 4-3.
4.4 Cancellation of hardware power-down
mode
(1) Use of RESET pin
o The clock generator is activated and the
CPU started up when a "1" level is applied
to t~ pin while a "0" level is input to
the RESET pin. If this "0" level is kept applied to the RESET pin until oscillation
become stable, the CPU will be reset and
will start executing froinaddress o. The
timing chart IS outlined in Fig. 4-5.
(2) Use of the INT pin during external interrupt
enabled status (I.e. following execl)tion of
EN I instruction)
o The clock generator is activated and the
CPU started up when a "1" level is applied
to the VDD pin while a "0" level is applied to
the INT pin.
270
(3)
o
(4) o
If this "0" level is maintained until at least 2
ALE output signals occur, an external interrupt is generated, and execution starts from
.
address 3. .
However, if the power-down mode is started
during an interrupt processing routine, exe~ution will be continued on the next instruction after the present instruction. The timing
chart is outlined in Fig. 4-6.
Use of the TNT pin during external interrupt
disabled mode (I.e. following execution of
DIS I'instruction or hardware reset)
The clock generator is activated and the
CPU started up when a "1" level is applied
to the VDD pin while a "0" level is applied to
the INT pin. If this "0" level is maintained
until at least 2 ALE output signals occur, exI\lcution is continued on the next instruction
after the present instruction. The timing
chart is outlined in Fig. 4-6.
Use of VDD pin only
The clock generator is activated and the
CPU started up when a "1." level is applied
to the VDD pin while a "1" level.1§.. also applied to both the RESET and INT pins. In
this case, execution is resumed from the
stopped position. The timing chart is outlined in Fig. 4-7.
----------------e.
Table 4-3
MSM80C35/48, 80C39/49, 80C40/50 •
Details of Pin Status during Hardware Power-Down Mode
Pin Name
Normal Operation
(VDD = "1 " level)
Power Down Mode
(VDD = "0" level)
lP
TO
Active
Floating if output enabled
2P
XTALl
Active
Active
3P
XTAL2
Active
Active
4P
RESET
Active
Active
5P
SS
200 to 500 kO pullup
20 to 50 kO pulldown
6P
INT
Active
Active
7P
EA
Active
Active
8P
RD
Active
Floating
Pin No.
9P
PSEN
,Active
Floating
lOP
WR
Active
Floating
11 P
ALE
Active
Floating
12P
DBO
Active
Floating
13P
DBl
Active
Floating
14P
DB2
Active
Floating
15P
DB3
Active
Floating
16P
DB4
Active
Floating
17P
DB5
Active
Floating
18P
DB6
Active
Floating
Floating
19P
DB7
Active
20P
VSS
o [V]
o [V]
21P
P20
Active
Floating
22P
P21
Active
Floating
23P
P22
Active
Floating
24P
P23
Active
Floating
25P
PROG
Active
Floating
26P
VDD
"1 "level
"O"level
27P
Pl0
Active
Floating
28P
Pll
Active
Floating
29P
P12
Active
Floating
30P
P13
Active
Floating
31P
P14
Active
Floating
32P
P15
Active
Floating
33P
P16
Active
Floating
34P
P17
Active
Floating
35P
P24
Active
Floating
36P
P25
Active
Floating
37P
P26
Active
Floating
38P
P27
Active
Floating
39P
Tl
Active
Active
40P
Vee
+2 to +6 [V]
+2 to +6 [V]
271
eMSM80C3S/48, 80C39/49, 80C40/S0
I
: T1
M1.
i T2: T~i
or
e--------------
M2
M1
fI T4
X'tal 1 ·2
~ ~r----llillL
ALE
O I
1~:
:
I
IFLOA~TING
I
I
,I
~RUN-W...STOP~., I
I
I
' I I
IOSC I
I
CPU MODE
I
I
I
, I
-t-tRU~---t--l-STOP{!-tEV.OKk
X'tal 1 ·2
I
I
I
I
I
I
;,
RUN
'I
:
!
:
l
I
: :
I I
I I
:
.I
I
I
I
I I
I
1___
I
I
I
rt RESET pin must be held!
~~:;~~t:~~e~~~~~!~e:
normal
I
I
I
I
r
l'
VDD
~Ny)ll
I
o ~9ffi2J?a I If__L
11
iI :I~~'
I
odr~
0-1.-"'1"-.,.I
I
r'
1
I
I
I
o
I
I
SS 200-500Kn
PULLUP
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SS 200-500Kn PULLUP
iI iI,i
I
I
I
I
I
I
I
r
I
I
I
I
I .,..--r--I.-"'1"--t--..,..-+I
I
I
I
I
I
I
I
I
I
I
I
I RESET EXECUTE
I
I
I
SS 20-50Kn PULLDOWN
* Cancellation Condition: Use RESET pin.
D
Fig.4-5
iT1 , T2 i ni
X'tal
ALE
CPU MODE
X'tal 1 ·2
Hardware Power-Down Mode Timing Chart
II T4
~~~JlL
1:
:FLOA~
::
O~I
.,----lRUN-i+STOPS+-1~:~--tl-+---r-;--i-+
HRu~-{-I-STOP{1~e~K·;'\§"-tI-+-~-..l---+50-
When a 0.47 I'F ca~acitor is
connected to the
pin,
50-60 ms wait.
ss-
I
I
60ms
WAIT
r-:
I
I I
1 I J n.....~
o ~~yl~
1 I
I
I
I
I
o -1--"'1" -~--"'~...,,"""~---....;..-+---+-........--i.......J
1..:.1_+......J~-;
0-'
-t:=::;===1-
SS 200- 500Kn
PULLUP
500KO PULLUP
SS 20-50Kn PULLDOWN
* Cancellation Condition: Use the I NT pin.
Fig.4-6
272
I
I
Ii
I
I
I
I
___ "':--'--i-...j_J_LL_L~_+_+_~_L
I
I
I
I
,I
-
I
I
I
I
:
I
I
I
,
I
I
Hardware Power-Down Mode Timing Chart
I I
---------------e. MSM80C3S/48, 80C39/49, 80C40/S0 •
I
.1.
: ,Tl: T2: T3:
X'tal
ALE
CPU MODE
X'tall ·2
1
If T4
nnnnnnnnnn
o IpUUrUU~UU~f
1 I
0;
I
II 11/
I
tjlJJf:
FLOATIN~
I
I
i
rj\--If--(
+---T---ti;
. I
I
I
i--1RU~~STOP~~S-rI~!--~~--T--;-1
4--4RUN~STOP~OSCEVOKE
RUIN-;--4-~--4-~--;-
I
I
I! I
I
I
I
When a 0.47 I'F c~citor is -150- I-- I
connected to the ss- pin,
60 ms
:
50-60 ms wait.
WAIT
I
I
I
:
f
I
VDD
I
I
1
I
Iii
1
I
I
I
1 I
1
:I i i
1
1
I
:
I
1 I
I
I
I
I
I
I
I
I
1.1.
o f2Q
e
~
~
.5
ge
a
0
FRES
1
1
1
0
0 .0
1
0
E2
1
1
FLT,FLITRESET
HLT
0
0
0
0
0
0
0
1
01
1
1
CPU Control Clock Stop
HALTS
1
0
0
0
0
0
1
0
82
1
1
XTAL 1'2 Stop
MOVA,T
0
1
0
0
0
0
1
0
42
1
1
(A)
-(T)
eli
MOVT,A
0
1
1
0
0
0
1
0
62
1
1
(T)
--(A)
,,E~
STRTT
0
1
0
1
0
1
0
1
55
1
1
(T)
-~-XTAL
STRTCNT
0
1
0
0
0
1
0
1
45
1
1
(T)
-T1Clock
STOP TCNT
0
1
1
0
0
1
0
1
65
1
1
(T) Count Stop
0
0
0
0
0
0
0
0
00
\1
1
(PC)
SII>
8'5
~2
j::'-
~"
","e
NOP'
5j~
278
--(PC) + 1
-----,..----------e MSM80C35/48, 80C39/49, 80C40/50 •
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Input Voltage
Storage Temperature
Symbol
Limits
Conditions
Unit
·V
VCC
Ta=25°C
-0.3 to 7
VI
Ta=25°C
-0.3toVCC
V
-55to+150
°c
Tstg
OPERATING RANGE
Symbol
Conditions
Limits
Unit
Supply Voltage
VCC
lose = DC-11 MHz'
+2.5 to +6
V
RAM Retention Voltage
VCC
+2 to +6
V
TA
-40 to +85
°c
Parameter
Ambient Temperature
Fan Out
11 MHz version 01 MSM80C50 (6 MHz
N
< XTAL1.2 < 11
MOSload
10
TTL load
1
MHz) is under development.
279
• MSM80C3S/48, 80C39/49, 80C40/S0 . - . . , . . . - - - - - - - - - - - - -
DC ELECTRICAL CHARACTERISTICS
(Vee
= 5V±1 0%, Ta = -40 to +85°e)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
V
"L" Input Voltage
VIL
-0.3
0.8
"H" Input Voltage (1)
VIH
2.2
VCC
V
"H" Input Voltage (2)
VIH
3.8
Vec
V
"L" Output Voltage (3)
VOL
IOL=2mA
0.45
V
"L" Output Voltage (4)
VOL
10L =1.6mA
0.45
"H" Output Voltage (3)
VOH
IOH=400/LA
"H" Output Voltage (4)
VOH
"H" Output Voltage (3)
"H" Output Voltage (4)
V
IOH=50/LA
2.4
V
VOH
IOH=20/LA
4.2
V
VOH
10H = 10/LA
4.2
Input Leak Current
IlL
Output Leak Current (5)
10L
RESET Pull up
Resistance
RR
VIN~ VIH'S./
VIN;;;VIL -
Oscillation
stop/oscillation
SS Pull up Resistance
(6)
P1, P2 Pull up
Resistance
V
2.4
RSS
Rp1, P2
Meas,uring
Circuit
1
V
VSS'S. VIN'S. VCC
±10
/LA
2
VSS'S. VO'S. VCC
±10
/LA
3
20/500
50/750
kO
20/200
50/500
kO
5/75
15/150
kO
VIN~VIH/
2
3
VIN;;;VIL
At hardware power
downVCC=2V
(TA = +25°C) (7)
1
10
/LA
At HLTS execution 'VCC=2V
(TA = +25°C) (7)
1
10
/LA
At HALT (6 MHz)
1.5
3
mA
At HALT (11 MHz)
2.5
5
mA
Atexecution
(6 MHz)
5
10
mA
At execution
(11 MHz)
10
20
mA
4
Power Supply Current
ICC
Notes: (1) This does not apply to RESET, XTAL 1, XTAL2, and VDD.
(2) RESET, XTAL 1, XTAL2, VDD
(3) BUS, RD, WR, PSEN, ALE
(4) Other outputs
(5) High-impedance state
(6) This operates as a pull-down resistor when the oscillation is stopped in the HLTS or hardware power-down
mode and as a pull-up resistor in other states.
(7) This does not contain flow out current from I/O Ports and Signal pins.
280
- - - - - - - - - - - - - - . MSM80C35/48, 80C39/49, 80C40/50 •
AC CHARACTERISTICS
(Vee = 5V±1 0%, TA = -40 o e to +85°e)
Limits
Parameter
Symbol
11 MHz Clock
Min.
Max.
Variable Clock (0 - 11 MHz)
Min.
Unit
Max.
CycleTime
tCY
1.36
1.36
,",S
ALE Pulse Width
tLL
150
7/3OtCy-165
ns
Address Set up ALE
tAL
70
2/15tCy-110
ns
Address Hold from ALE
tLA
50
1/15tCy-40
ns
Bus Port Latch Data Setup
to ALE
tBL
110
5/30tCy-115
ns
Bus Port Latch Data Hold
from ALE
tLB
90
3/3OtCy-45
ns
Control Pulse Width
(PSEN, RD, and WR)
tcc
300
6/15tCy-245
ns
Data Setup before WR
tow
250
6/15tCy-295
ns
2/15tCy-140
Data Hold after WR
two
40
Data Hold after RD
tDR
0
PSEN, RD to Data-in
tRD
Address Setup to WR
Address Setup to Data-in
tAW
100
0
200
200
ns
5/15tCy-250
ns
ns
6/15tCy-345
400
tAD
ns
100
8/15tCy-325
ns
Address Float to RD, PSEN
tAFC
0
Port Control Setup to PROG
tcp
100
Port Control Hold from PROG
tpc
60
PROG toP21nputVaiid
tpR
-
Output Data Setup
top
200
6/15tCy-345
Output Data Hold
tpD
20
3/15tCy-250
Input Data Hold from PROG
tpF
0
PROG Pulse Width
tpp
700
10/15tCy-205
ns
Port 21/0 Setup to ALE
tpL
150
9/30tCy-255
ns
Port 21/0 Hold from ALE
tLP
20
3/30tCy-115
ns
Note: Control output:
Bus output:
0
ns
ns
2/15tCy-80
ns
4/15tCy-300
650
150
9/15tCy-165
0
ns
ns
ns
150
ns
CL =80 pF
CL = 150 pF [for 20 pF (tWO)]
281
• MSM80C3S/48, 80C39/49, 80C40/S0 ••- - - - - - - - - - - - - -
MSM80C49 OPERATION GUARANTEE RANGE
Ta = -40 to +85°e
I
I·
I
I
I
I
I
I
I
(jJ sec)
I
I
I
I
100
Operation Guarantee Range
1.
10
-1.5MHz
E
"\
.
i=
u
\
>()
,
-3MHz
"
~
\
\
MSM80C40/50·
- - ' 6MHz
I'..
"
"
1
2
3
4
SupplV Voltage (Veel
·11 MHz version of MSM80C40/50 is underdevelopment
282
-
5
6
(VI
11 MHz
- - - - - - - - - - - - - - - - ' . MSM80C35/48, 80C39/49, 80C40/50 •
TIMING CHART
Instruction Fetch (from external program memory)
~-------------tCY------------~
ALE
tAFC
BUS
Read (from external data memory)
ALE
t----tcc------t
BUS
283
• MSM80C35/48, 80C39/49, 80C40/50 ...- - - - - - - - - - - - - Write (to external memory)
ALE
J..---tcc----I
BUS
II
4 low-order bits InpuVoutput of port 2 when expanded I/O is used
(in external program memory access mode)
P26-3
(Output
model
PCH
P20-3
(Input
mode)
284
PCH
---------------e. MSM80C35/48, 80C39/49, 80C40/50 •
MEASUREMENT CIRCUIT
2
~
~
(1 )
VIH
(3)
I-
l::J
::J
I>.
l::J
I>.
~
::J
::J
1=
~
0
VIL
I-
II>.
::J
0
GND
=3
J
=- =-
-
4
Notes: (1) This is repeated for each specified input pin.
(2) This is repeated for each specified output pin.
(3) Input logic for setting the specified state.
285
OKI
5en1iconductor
MSM80C31 F/MSM80C51 F
CMOS SINGLE-COMPONENT 8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The OKI MSM80C31 F/MSM80C51 F microcontroller is a low power, high performance 8-bit single
component device implemented in OKl'ssilicon gate complementary metalloxide semiconductor
process technology. Integrated within the device is 4K bytes of mask programmable ROM
(MSM80C51 F only), 128 bytes of data RAM, 32 I/O lines, two 16-bit timer/counters, a five-source
two-level interrupt structure, a full duplex serial port, and an on chip oscillator and clock circuitry. In
addition, the device has two software selectable modes for further power reduction - Idle and Power
Down. Idle mode freezes the CPU's instruction execution while maintaining RAM and allowing the
timers, serial port and interrupt system to continue functioning. Power Down mode saves the RAM
contents but freezes the oscillator causing all other device functions to be inoperative.
FEATURES
• Operating temperature: -40 - +85°C
• Operating frequency:
0.5 - 16 MHz
• CMOS technology, 2fLm Silicon gate
• Minimum instruction cycle:
1.0fLS (@ 12MHz, Vcc = 5V±20%)
0.75fLS (@ 16MHz, Vcc = 5V±1.0%)
• Low power consumption:
Normal Operation
16 mA @ 5V, 12MHz
Idle Mode
3.7 mA @ 5V, 12MHz
Power Down Mode
50fLA @ 2V
• Instruction set includes 111 instructions
• 8-bit CPU
• On chip oscillator and clock circuitry
•
•
•
•
•
•
•
32 Input/Output lines
4069 x 8 bits on chip ROM (MSM80C51 F)
128 x 8 bits on chip RAM
64K address space for program memory
64K address space for external data memory
Two 16-bit timer/counters
Five source two-priority level interrupt
structure
• Full duplex serial port
• Boolean processor
• CMOS and TTL compatible
• CMOS ROM LESS development device
(MSM80C31 F)
DIFFERENCES BETWEEN MSM80C31 F/MSM80C51 F AND
MSM80C31lMSM80C51
•
Operating frequency
. 0.5 -16 MHz ............. MSM80C31 F/MSM80C51 F
0.5 -12 MHz ............. MSM80C31/MSM80C51
• External clock inputterminal
XTAL1 .................... MSM80C31F/MSM80C51F
XTAL2 .................... MSM80C31/MSM80C51
• Emulation mode
Output impedance of ALE and PSEN pins becomes about 20kfl while CPU is being reset in
MSM80C31 F/MSM80C51 F.
Any other functions and electrical characteristics of MSM80C31 F/MSM80C51 F except for the above
three differences are the same as those of MSM80C31 /MSM80C51.
286
."
C
Z
(')
CONTROL SIGNALS
r -"'-"-L..
___
- -- -- -- -- -- -- -- -SE9~~ 14096 I
-_-_==~ -_~_-_-_-_~~:~.
~
NI
P20 - P27
i
I
n
II
=iE
0
::l
...
~M
RIW SIGNALS
::::!
~...J....,ll
)10
I I
I I I __ .. I
I I I _.
I
r-
o
WORD
.8 BIT
(')
ii"
Q
Q
C
I C
:;
~
POO - P07
r-
m
~
II:
o I .
oz
II:
Ci)
~
::II
)10
s:::
XTAL1 - - - 1 - XTAL2
ALE
Pffii
EA
-I
~
RESET
S~.!U~L~ _
..J
s::
s::
tn
CI)
o
o
P30 - P37
(0)
L _____________________
.....
~
=!!
CI)
o
o(II
.....
"TI
I\.l
00
-..J
;
•
• MSMSOC31F/SOC51F ••----------------------------------------PIN CONFIGURATION
MSM80C51 F-XXRS/MSM80C31 FRS
(Top View) 40-Lead Plastic DIP
Pl.0
Pl.t
Pl.2
P1.3
Pl.4
Pl.S
Pl.&
Pl.7
RESET
RXDIP3.0
TXDIP3.1
iN'i'O/P3 .2
INTt/P3.3
TO/P3.4
Tl/P3.5
WR1P3.6
RO/P3.7
XTAL2
XTALI
VSS
MSM80C51 F-XXGSK/MSM80C31 FGSK
(Top View) 44-Lead Plastic Flat Package
vee
PO.O/ADO
PO. l/AD 1
PO.2/AD2
PO.3/AD3
PO.4/AD4
PO.5/AD5
PO.6/AD6
PO.7/AD7
Pl.5
P1.6
Pt.7
RESET
PO.4/AD4
PO.5/AD5
PO.6/AD6
PO.7/AD7
EA
NC
EA
RXD/P3.0
TXD/P3.1
T;:;'i'O/P3.2
tm1/P3.3
TO/P3.4
Tl/P3.5
ALE
Pffii
P2.7/A15
P2.&/A14
P2.5/A13
P2.4/A12
P2.3/All
P2.2/Al0
P2.1/A9
P2.0/AB
ALE
PSEN
NC
P2.71AD15
P2.6/AD14
P2.5/AD13
MSM80C51 F-XXJS/MSM80C31 FJS
(Top View) 44 Lead Plastic Leaded Chip Carrier
P1.5
:rJ
l~! L5J ~J l3J ~J
P1.6 :~]
Pl.7 -9~
RESET
P3.0/RXO
Ll1
o
t~ ~~ t~ ~~ ~S
PO.~
[¥t PO.6
fei]
tfJ
~~
coco
00
NC [~J
00
"'01
[~
[~~
PO.7
EA
[q{ NC
P3.2/INTO
E]
C:P: ALE
[if PSEN
P3.3/iNT1
l~]
[E
P3.l/TXD r:f~
P3.4/TO I~]
P3.5/T1
P2.7
[@ P2.6
{fJ ... , .... ,.., ,., ,.., ,., ,., r, r, ,., r., [~ P2.5
lH~ .1~
288
~~ P.04
[58
l2cr
:111) 12~ ;2~ ~~ ?~ ?~ :2~ :2~
-----------------------------------------eeMSMSOC31F/SOC51F e
PIN DESCRIPTIONS
Designation
Description
VSS
Ground potential
VCC
Supply voltage during Normal, Idle and Power Down operation
Porta
Port a is an 8-bit open drain bidirectional 1/0 port. It is also the multiplexed
low-order address and data bus during accesses to external memory.
Port 1
Port 1 is an 8-bit bidirectional 1/0 port with internal pullups. It can drive CMOS
inputs without external pullups.
Port 2
Port 2 is an 8-bit bidirectional 1/0 port with internal pullups. It receives the
high-order address byte during accesses to external memory. It can drive
CMOS inputs without external pullups.
Port 3
Port 3 is an 8-bit bidirectional 1/0 port with internal pullups. It also serves the
functions of various special features, as shown below:
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Alternate Fucntion
(serial input port)
RXD
(serial output port)
TXD
INTO
(external interrupt)
(external interrupt)
INT1
(Timer a external input)
TO
(Timer 1 external input)
T1
(external data memory write strobe)
WR
(external data memory read strobe)
RD
It can drive CMOS inputs without external pullups.
RESET
ALE
Reset input pin. A reset is accomplished by holding the RESET pin high for at
least 1 fJ- second, even if the oscillator has been stopped. The CPU responds
by executing an internal reset. An internal pulldown resistor permits Power-On
reset using only a capacitor connected to VCC.
This pin does not receive the power down voltage since the function has been
transferred to the VCC pin.
Address Latch Enable output for latching the low byte of the address during
accesses to external memory. For this purpose, ALE is activated twice every
machine cycle or at a constant rate of 116 the oscillator frequency, except
. during an external memory access at which time one ALE pulse is skipped. It
can drive CMOS inputs without an external pullup.
PSEN
Program Store Enable output is the read strobe to external Program Memory.
PSEN is activated twice each machine cycle during fetches from external
Program Memory. (However, when executing out of external Program Memory,
two activations of PSEN are skipped during each access to external Data
Memory.) PSEN is not activated during fetches from internal Program Memory.
It can drive CMOS inputs without an external pullup.
EA
External Access input pin. When EA is held high, the CPU executes out of
internal Program Memory (unless the Program Counter exceeds OFFFH).
When EA is held low, the CPU executes only out of external Program Memory.
EA must not be floated.
XTAL1
Crystal 1 pin. It is an input to the inverting amplifier which forms the internal
oscillator. It also receives the external clock signal when an external oscillator
is used. (External clock signal should be at 50% duty and C-MOS level).
XTAL2
Crystal 2 pin. It is an output of the inverting amplifier that forms the internal
oscillator.
289
• MSMSOC31F/SOC51F ••------------~----~--------------------
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS·
Item
Symbol
Conditions
Rating
Units
Supply Voltage
VCC
-0.5 to +7.0
V
Voltage from any Pin to VSS
VAP
-0.5 to VCC +0.5
v.
TSTG
-55 to +150
°C
PO
1.0
W
Conditions
Rating
lInits
Storage Temperature
Power Dissipation
OPERATING RANGE
Item
Symbol
..
Supply Voltage
VCC
fosc =0.5 -16
MHz
2.5 to +6.0
V
RAM Retention Voltage
VPD
Power Down
2.0 to +6.0
V
Operating Temperature
TOP
-40 to +85
°C
'NOTlCE: Stresses at or above those listed under 'Absolute Maximum Ratings' may cause permanent damage to
the device. This is a stress rating only and functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions may affect device reliability .
•• DC and AC characteristics in the range of 12 MHz <.f ::s 16 MHz and 2.5 V ::s Vcc < 4 V will be specified elsewhere.
DC CHARACTERISTICS
(TA = -40°C to +85°; VCC= 4 to 6V: VSS = OV)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Input Low Voltage
(ExceptEA)
VIL
-
-0.5
-
0.2VCC-O.1
V
Input Low Voltage
ToEA
VIL1
-
-0.5
-
0.2VCC-0.3
V
Input High Voltage
(Except XTAL1 , RESET)
VII-!
-
0.2VCC+0.9
-
VCC+0.5
V
Input High Voltage
(XTAL 1 and RESET)
VIH
-
·0.7VCC
-
VCC+0.5
V
Power Down Voltage
to Vec in PO mode
VPD
-
2.0
-
6.0
V
Output Low Voltage
Ports 1, 2. 3 (Note 1)
VOL
IOL =1.6mA
-
-
0.45
V
Output Low Voltage
Port 0, ALE, PSEN
(Note 1)
VOL1
IOL=3.2mA
-
-
0.45
V
VOH
IOH
0.9VCC
-
-
V
IOH=-30~A
0.75VCC
-
-
V
IOH=-60~A
2.4
-
-
V
Output High Voltage
Ports 1,2,3
..
=-10~A
NOTE1: VOL is degraded when the 80C31 F/80C51 F rapidly discharges external capacitance. This AC noise is
most pronounced during the emission of address data. When using external memory. locate the latch or
buffer as close to the80C31 F/80C51 F as possible.
290
-----------------------------------------e. MSMSOC31F/SOC51F
•
DC CHARACTERISTICS (CONT.)
(TA = -40°C to +8S0;
vcc = 4 to 6V: vss = OV)
Item
Output High Voltage
Port OOn External Bus Mode),
ALE, PSEN
Symbol
VOH1
Condition
Min.
Typ.
Max.
Unit
10H =-40!-,A
(Note 2)
0.9VCC
-
-
V
10H = -1S0!-,A
0.7SVCC
-
-
V
10H = -400!-,A
2.4
-
-
V
-
-200
!-,A
Logical 0 Input Current
Ports 1,2,3
IlL
Yin = O.4SV
-
Logical 1 To 0 Transition
Current-Ports 1,2,3
ITL
Yin =2.0V
-
-
-SOO
!-,A
Input Leakage Current
Port 0, EA
III
VSS 9] or [(AC) = 1 II
THEN (A3- 0)·-(A3- 0) +6
AND
IF [[(A7-.) > 9] OR [(C) = 1ll
THEN (A7-.) -(A7-.) +6
ANLA,Rn
0
1
0
1
58-5F
1
1
(A) - (A) AND (Rn)
ANLA, direct
0 1 0 1 0 1 0 1
a7 a. as a. a3 a2 at ao
55
Byte 2
2
1
(A) - (A) AND (direct)
ANLA,@Ri
0
56-57
1
1
(A) - (A) AND «Ril)
ANLA,#data
0 1 ·0 1 0 1 0 0
d7 d. ds d. d3 d2 dt do
54
Byte 2
2
1
(A) - (A) AND #data
til
c:
·~e
0
INCRn
1
0
1
1 n2 n, no
0
1
1
1
---------------------------------------e. MSMSOC31F/SOC51F •
INSTRUCTION SET DETAILS (CONT.)
Mnemonic
c:
'"
"8m
Q)
ACALL addr 11
0
810 89
1
a.
1
1
0
0
0
0
1
0
87 8s a. a. a3 a. a,
LCALLaddr 16
0
0
0
1
0
0
1
815814 a'3 812 811 810 89
1
87
86
8s
84
83 82
RET
0
0
1
0
0
0
1
0
22
1
2
(PC,. -.) - ((SP))
(SP) - (SP) - 1
(PC7 - ol- ((SP))
(SP) - (SP) - 1
RETI
0
0
1
1
0
0
1
0
32
1
2
(PC,.-.) -((SP))
(SP) - (SP) - 1
(PC7 - ol- ((SP))
(SP) - (SP) - 1
Byte 1
Byte 2
2
2
(PC) - (PC) + 2
(PC '0 - 0) - page address
02
Byte 2
Byte 3
3
2
(PC) -addr,.-o
C>
c:
:c:
(J
c
f!
.c
E
~
e
0..
AJMP addr 11
LJMPaddr 16
a. 0 0 0 0 1
a7 a6 a. a. a3 a. a, ao
810 89
0
0
0
0
0
0
1
0
a.
87 86 8s 84 83 82 8, ao
815814813812811 810 89
303
• MSM80C31 Ff80C51F ••----------------------------------------INSTRUCTION SET DETAILS (CONT.)
en
c:
:.c0
c:
~
Instruction Code
07 D. Os D. Os 02 0, Do
Hexadecimal
SJMPrel
1
r7
0
r.
0
rs
0 0
r. rs
0 0
r2 r,
0
ro
SO
Byte 2
2
2
(PC) - (PC) + 2
(PC) - (PC) + rei
JMP@A+DPTR
0
1
1
1
0
0
1
1
73
1
2
(PC) - (A) + (DPTR)
JZ rei
0
r7
1
r.
1
r.
0
r.
0 0
rs r2
0
r,
0
ro
60
Byte
2
2
(PC) - (PC) + 2
IF (A) = 0 THEN (PC) - (PC) + rei
JNZrel
0
r7
1 1 1 0 0
r. rs r. rs r2
0
r,
0
ro
70
Byte 2
2
2
(PC) - (PC) + 2
IF (A) ~ 0 THEN (PC) - (PC) + rei
JCrel
0
r7
1
r.
0
rs
0 0 0
r. rs r2
0
r,
0
ro
40
Byte 2
2
2
(PC) - (PC) + 2
IF (C) ~ 1 THEN (PC) - (PC) + rei
JNCrel
0
r7
1
r.
0 1 0 0
r. r. rs r2
0
r,
0
ra
50
Byte 2
2
2
(PC) - (PC) + 2
IF (C) ,. 0 THEN (PC) - (PC) + rei
JB bit, rei
0 0 1 0 0 0 0 0
b7 b. b. b. bs b2 b, bo
r7 r. rs r. rs r2 r, ro
20
Byte 2
Byte 3
3
2
(PC) - (PC) + 3
IF (bit) = 1 THEN (PC) - (PC) + rei
JNB bit, rei
0 0 1 1 0 0 0 0
b7 b. b. b. bs b2 b, bo
r7 r. rs r. rs r2 r, ro
30
Byte 2
Byte 3
3
2
(PC) - (PC) + 3
IF (bit) = 0 THEN (PC) - (PC) + rei
JBC bit, rei
0 0 0 1 0 0 0 0
b7 b. b5 b. bs b2 b, bo
r7 r. r. r. rs r2 r, ro
10
Byte 2
Byte 3
3
2
(PC) - (PC) + 3
IF (bit) = 1 THEN (bit) -0
(PC) - (PC) + rei
CJNE A, direct,
rei
1 0 1 1 0 1 0 1
a7 a. as a. as a2 a, ao
r7 r. r. r. rs r2 r, ro
B5
Byte 2
Byte 3
3
2
(PC) - (PC) + 3
IF (direct) < (A) THEN (PC) - (PC)
+reland(C)-O
IF (direct) > (A) THEN (PC) - (PC)
+ rei and (C)-l
CJNE A, #data,
rei
1 0 1 1 0 1 0 0
d7 d. ds d. ds d2 d, do
r7 r. rs r. rs r2 r, ro
B4
Byte 2
Byte 3
3
2
(PC) - (PC) + 3
IF #data < (A)
THEN (PC) - (PC) + rei and
(C)-O
IF #data> (A) THEN (PC) - (PC) +
rei and (C) -1
CJNE Rn, #data,
rei
1 0 1 1 1 n2 n, no BS-BF
d7 d. ds d. ds d2 d, do
Byte 2
r7 r. rs r. rs r2 r, ro
Byte 3
3
2
(PC) - (PC) + 3
IF #data < (Rn) THEN (PC) - (PC)
+ rei and (C)-O
IF #data> (Rn) THEN (PC) - (PC)
+ rei and (C) -1
CJNE@Ri,
#data,rel
1 0 1 1 0 1 1 1 B6-B7
d7 d. d. d. ds d2 d, do
Byte 2
r7 r. rs r. rs r2 r, ro
Byte 3
3
2
(PC) - (PC) + 3
IF #data < «Rill THEN (PC) (PC) + rei and (C)-O
IF #data> «Ril) THEN (PC) (PC) + rei and (C) - 1
DJNZRn, rei
1
r7
1 n2 n, no OS-OF
rs r2 r, ro
Byte 2
2
2
(PC) - (PC) + 2
(Rn) - (Rn) - 1
IF (Rn) 'I' 0 THEN (PC) - (PC) + rei
DJNZ direct, rei
1 1 0 1 0 1 0 1
a7 a. as a. as a2 a, ao
r7 r. rs r. rs r2 r, ro
05
Byte 2
Byte 3
3
2
(PC) - (PC) + 3
(direct) - (direct) - 1
IF (direct) "F 0 THEN (PC) - (PC)
+ rei
NOP
0
00
1
1
(PC) - (PC) + 1
Mnemonic
Byte Cycle
.c
E
~
en
E!
0..
304
1
r.
0
r.
1
r.
.
0
0
0
0
0
0
0
Explanation
- - - - - - - - - - - - - - - - - - - -..... MSM80C31 F/SOC51 F •
NOTES ON THE INSTRUCTION SET AND THE ADDRESSING MODES
Rn
- Register R7 -RO of the currently
selected Register Bank.
direct
- 8-bit internal data location's address.
This could be an Internal Data RAM
location (0 - 1 27) or a SFR [i.e., I/O
port, control register, status register,
etc. (128 - 255)].
@Ri
- 8-bit internal data RAM location (0 255) addressed indirectly through
register R1 or RO.
#data
. - 8-bit constant included in instruction.
#data 16 - 16-bit constant included in instruction.
addr 16 - 16-bit destination address. Used by
LCALL & LJMP. A branch can be
anywhere within the 64K-byte
Program Memory address space.
addr 11
- 11 -bit destination address. Used by
ACALL & AJMP. The branch will be
within the same 2K-byte page of
program memory as the first byte of
the following instruction.
rei
- Signed (two's complement) 8-bit offset
byte. Used by SJMP and all conditional
jumps. Range is -128 to +127 bytes
relative to first byte of the following
instruction.
bit
- Direct Addressed bit in Internal Data
RAM or Special Function Register.
INSTRUCTIONS THAT AFFECT FLAG SETTINGS 1
INSTRUCTION
FLAG
INSTRUCTION
C OVAC
x
RRC
RLC
X X
X X X
X X X
0 X
0 X
X
X
X
SETac
I
ADD
AD DC
SUSS
MUL
DIV
DA
1
FLAG
C OVAC
CLRC
CPLC
ANL C, bit
ANL C,Ibit
ORL c, bit
0
X
X
X
X
ORL C, fbit
MOV c, bit
CJNE
X
X
X
Note that operations on SFR byte address 208 or bit
addresses 208-215 (i.e., the PSW or bits in the PSW) will
also affect flag settings.
305
• MSM80C31 F/80C.51 F ••- - - - - - - - - - - - - - - - - - - -
APPLICATION EXAMPLES
P1.0
P1.1
P1.2
P1.3
:~::
L..........:.::.,~XTAL2
:
MSM82C43
I/O
P2.0 t-;,:-_ _1;.;1,... P20· EXPANDER
P1.6
P1.7
8.2K
~9
::;V----,---.-..t~ RESET
MSM80C51 F
10",
1
2
3
4
'--_ _..;;3;.;.1.., EA
Pl.O (RXD)
Pl.1 (TXDI
P3.2 (INTO)
P3.3(lNT1)
P3.4 (TO)
P3.5 (T1)
Pl.6 (WR)
P3.7 (RD) ALE
Pi.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
8
1
iT.:---....
P21
P22
,P23
H'r-::'--'
PO.O
PO.1
P02
PO.3
PO.4
PO.5
PO.6
PO.7
29
The following software driver is required to interface to the 82C43
Mixing Parallel Output, Input, and
Control Strobes on Port 2.
INPuT DATA FROM AN 82C43 110 EXPANDER
CONNECT TO P23-P20
P25 & P24 MIMIC CSt & PROG
P27-P26 USED AS INPUTS
PORT TO BE READ IN ACC
IN82C43
MOV
MOV
ClR
ORl
MOV
SETB
P21 P20
0
0
0
0
A, #110100008
P2,A
;OUTPUT INSTRUCTION CODE
P2.4
;FAllING EDGE OF PROG
P2,#OOOO1111B
;SET FOR INPUT
. A,P2
;READ INPUT DATA
P2.4
;RETURN PROG HIGH
Address
Code
Port 4
Port 5
Port 6
Port 7
P23
P22
0
0
0
Instruction
Code
0
1/0 ExpanslonJUslng an 82C43
306
Read
Write
ORlD
ANlD
1/0
-----------------------------------------4eMSM80C31F/SOC51F •
APPLICATION EXAMPLES (CONT.)
19~
7I
F
Cl
]!8~
-=;opf["
XTAL2
8.2K
*~t
RESET
110
EA
10
11
12
13
14
15
16
"o{
17
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
(RXD)
(TXD)
(INTO)
(INn)
(TO)
(n)
(WR)
(RD) ALE
PSEN
PO.O
PO.1
PO.2
PO.3
PO.4
PO.5
PO.6
PO.7
39
38
37
36
35
34
33
32
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
1
2
3
4
5
6
7
8
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
21
22
23
24
25
26
27
28
29
7 I Jj.
19
XTAL 1 Vee
VSS
F
O::;opf!"
]l8~
XTAL2
8.2 K
cr
31
,~{
10
11
12
13
14
15
16
17
RESET
MSM80C51F
EA
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
po.o
(RXD)
(TXD)
(INTO)
(INn)
(TO)
(n)
(WR)
(RD) ALE
PO.1
PO.2
PO.3
PO.4
PO.5
PO.6
PO.7
I/O
39
38
37
36
35
34
33
32
29
Multiple 80C51 F's Using Half-Duplex Serial Communication
307
• MSMSOC31F/SOC51F .--------------------------------------•
APPLICATION EXAMPLES (CONT.)
19
1~rIE!;~
1OP~
12K
XTAL2
~E9RESET
GND
20
Eli:
31
w{
+5V
MSM80C51F
10.,
10
11
12
13
14
P3.0IRXDI
P3.1 1!l!QI
P3.2I1NTOI
P3.31iR'i'i1
P3AITOI
P3.5ITll
P3.6Iiil1l
P3.71ii1i1 ALE
PO.O
PO.l
PO.2
PO.3
POA
PO.S
PO.6
PO.7
jiffij
30
29
39
12
1
14
1
16
37
18
1
33
ADO
ADI
AD2
AD3
AD4
ADS
AD6
AD7
MSM81C55
I/O
10iM
iiii
10
WR
plio :
PBl
11
~
ALE
TIMER
IN
CAN BE SOI'PLIED BY SYSTEM RESET . .OR PORT LINE OF 8OC51
Adding a Data Memory and 1/0 Expander
31
32
PM
34
PB7
38
=:3
...."O':~-"ll""!3~-. .
,
,.
TIMER
19
XTAL2
110
MSM80C51F
P3.0 IRXDI
P3.1ITXDI
....- ....- - - - : ' - ; f f P3.21i1m11
P3.31im'l1
P3.4ITOI
P3.5 I!!I
P3.6!!!!!1
P3.7 IRDI ALE
Multiple Interrupt Sources
308
-----------------------------------------eeMSMSOC31F/SOC51F e
MSM80C31/MSM80C51 INSTRUCTION CODES
~
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
0
0000
NOP
AJMP
address 11
(Page 0)
LJMP
address 16
RRA
INCA
INC
direct
INC@RO
INC@Rl
1
0001
JBCbit,
rei
ACALL
address 11
(Page 0)
LCALL ....
address 16
RRCA
DECA
DEC
direct
DEC@RO
DEC@Rl
2
0010
JBbit,
rei
AJMP
address 11
(Page 1)
RET
RLA
ADD A,
#data
ADDA,
direct
ADDA,
@RO
ADD A,
@Rl
3
0011
JNBbit,
rei
ACALL
address 11
(Page 1)
RETI
RLCA
ADDCA,
#data
ADDCA,
direct
ADDCA,
@RO
ADDCA,
@Rl
4
JCbit,
ORLA,
ORLA,
@RO
@Rl
direct
ANLA,
@RO
ANLA,
@Rl
XRLA,
direct
XRLA,
@RO
XRLA,
@Rl
MOV
direct,
#data
MOV@RO,
#data
MOV@Rl,
#data
MOV
direct 1,
direct 2
MOV
direct,
@RO
MOV
direct,
@Rl
SUBBA,
@RO
SUBBA,
@Rl
Jll"'MOV@RO,
direct
MOV@Rl,
direct
AJMP
ORL
ORLA,
JII'" ORLA,
direct, A
direct,
#data
#data
direct
JII'" ANLA,
ORL
0100
rei
address 11
(Page 2)
5
0101
JNCrel
ACALL
address 11
(Page 2)
ANL
direct, A
ANL
direct,
#data
ANLA,
#data
6
0110
JZrel
AJMP
address 11
(Page 3)
XRL
direct, A
XRL
direct,
#data
XRLA,
#data
7
0111
JNZrel
ACALL
address 11
(Page 3)
ORLC,
bit
8
1000
SJMPrel
AJMP
address 11
(Page 4)
ANLC,
bit
9
1001
,.
JII'" MOVA,
JMP
@A+DPTR
#data
MOVCA,
@A+PC
DIVAB
ACALL
MOVDPTR,
address 11
#data 16
(Page 4)
MOVbit,
C
MOVCA, JII'" SUBBA,
@A+DPTR
#data
SUBBA,
direct
....
A
1010
ORLC/bit
AJMP
address 11
(Page 5)
MOVC,
bit
INC DPTR
MULAB
B
1011
ANLC/bit
ACALL
address 11
(Page 5)
CPL bit
CPLC
CJNEA,
#data,
rei
CJNEA,
direc(,
rei
C
1100
PUSH
direct
JII'"
AJMP
CLRbit
address 11
(Page 6)
CLRC
SWAP A
XCHA,
direct
XCHA,
@RO
XCHA,
@Rl
D
1101
POP
direct
JII'"
ACALL
address 11
SETBbit
(Page 6)
SETBC
DAA
DJNZ
direct,
rei
XCHDA,
XCHDA,
@RO
@Rl
MOVXA,
@RO
MOVXA,
@Rl
CLRA
MOVA,
direct
MOVA,
@RO
MOVA,
@Rl
MOVX
@RO,A
MOVX
@Rl,A
CPLA
MOV
direct, A
MOV
@RO,A
MOV
@Rl,A
E
1110
MOVXA,
@DPTR
AJMP
address 11
(page 7)
F
1111
MOVX
@DPTR,A
ACALL
address 11
(page 7)
....
JII'"
CJNE@RO, CJNE@Rl,
#data,
#data,
rei
rei
3 BYTE
2 BYTE
MNEMONIC
2 CYCLE
4 CYCLE
309
• MSMSOC31F/SOC51F ••-----------------------------------------
1000
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
INCRO
INCRl
INCR2
INCR3
INCR4
INCR5
INCR6
INCR7
DECRO
DECRl
DECR2
DECR3
DECR4
DECR5
DECR6
DECR7
ADDA,RO
ADDA, Rl
ADDA,R2
ADDA,R3
ADDA, R4
ADDA,R5
ADDA,R6
ADDA,R7
ADDCA,RO
ADDCA,Rl
ADDCA,R2
ADDCA,R3
ADDCA,R4
ADDCA,R5
ADDCA,R6
ADDCA,R7
ORLA,RO
ORLA,Rl
ORLA,R2
ORLA,R3
ORLA,R4
ORLA,R5
ORLA,R6
ORLA,R7
ANLA,RO
ANLA,Rl
ANLA, R2
ANLA,R3
ANLA,R4
ANLA,R5
ANLA, R6
ANLA,R7
XRLA,RO
XRLA,Rl
XRLA, R2
XRLA, R3
XRLA,R4
XRLA, R5
XRLA,R6
XRLA, R7
MOVRO,
#data
MOVR1,
#data
MOVR2,
#data
MOVR3,
#data
,. MOVR4,
#data
MOVR5,
#data
MOVR6,
#data
MOVR7,
#data
MOV
direct,
RO
MOV
direct,
Rl
MOV
direct,
R2
MOV
direct,
R6
SUBBA,
RO
SUBBA,
Rl
MOVRO,
direct
CJNERO, ....
#data,
rei
8
,.
,.
XCHA,
RO
DJNZRO,
rei
,.
I
,.
MOV
direct,
R3
MOV
direct,
R4
MOV
direct,
R5
SUBBA,
R2
SUBBA,
R3
SUBBA,
R4
SUBBA,
R5
MOVR1,
direct
MOVR2,
direct
MOVR3,
direct
MOVR4,
direct
CJNE Rl,
#data,
rei
CJNER2, ....
#dala,
rei
CJNER3,
#data,
rei
CJNE R4, ....
#data,
rei
XCHA,
Rl
DJNZR1,
rei
,.
XCHA,
R2
I
XCHA,
R3
DJNZR2,
rei
DJNZR3,
rei
,.
,.
MOV
direct,
R7
SUBBA,
R6
SUBBA,
R7
MOVR5,
direct
MOVR6,
direct
MOVR7,
direct
CJNE R5, ....
#data,
rei
CJNER6,
#data,
rei
CJNER7, ....
#data,
rei
XCHA,
R4
XCHA,
R5
DJNZR4,
rei
DJNER5,
rei
I
,.
XCHA,
R6
XCHA,
R7
DJNER6,
rei
DJNER7,
rei
MOVA,RO
MOVA, Rl
MOVA,R2
MOVA,R3
MOVA,R4
MOVA,R5
MOVA,H6
MOVA,R7
MOVRO,A
MOVR1,A
MOVR2,A
MOVR3,A
MOVR4,A
MOVR5,A
MOVR6,A
MOVR7,A
310
OKI
semiconductor
MSM80C51 FVS
M80C51 PIGGY BACK
GENERAL DESCRIPTION
The MSM80C51 FVS is a device whose built-in ROM is replaced by external EPROM using the
piggy-back method. External EPROM capacity is up to 4K bytes. It can be used for evaluation of programs for MSM80C51 F.
FUNCTIONAL BLOCK DIAGRAM
CONTROL SIGNALS
P/W SIGNALS
r------------------
I
P20 - P27
POO-P07
XTAL 1 ---i---I
XTAL2 - - T - - I
ALE--+--I
PSEN--T--I
EA
RESET --T--L...:~~
Pl0-P17
~
I",
P30- P37
~
_ _ _ _ _ _ _ _ _ _ _ _ _ _--.-J
IL __________________________
~~====================~~
~
INSTALLATION METHOD FOR EXTERNAL ROM
Recommended EPROMS - 2764, 2732
M80C51VS
OKI
Japan 5101
Pin 1 For 80C51VS ROM Socket
Pin 1 For 2732
Pin 1 For80C51VS ROM Socket
311
OKI
semiconductor
MSM80C154/ MSM83C154
CMOS 8-bit One-Chip Microcontroller
GENERAL DESCRIPTION
The MSM83C154/MSM80C154 is a high performance 8-bit one-chip microcontroller implementing large
integration, high speed and low power consumption by 2 ,um silicon gate CMOS process technology.
The MSM83C154 features 16K byte ROM, 256 byte RAM, 32 I/O ports, three 16-bit timer/counters,
multifunctional serial port and clock generator. In addition, the MSM83C154 has three standby modes
enabling further power reduction.
The MSM80C154 is identical to the MSM83C154 except the omission of 16K byte ROM.
FEATURES
•
•
•
•
•
•
•
Fully static circuit
On-chip program memory
On-chip data memory
External program memory address space
External data memory address space
I/O ports
(Port 1,2,3, impedance programmable)
16-bit timer/counters
(includes watch dog timer & 32 bit timer)
Multifunctional serial port'
•
•
•
6-source 2-priority level
interrupt and multi-level
interrupt available by programming IP and IE registers
Memory-mapped special function registers
Bit addressable data memory and SFRs
Minimum instruction cycle
: 0.75 ,us @16 MHz operation
•
•
•
•
•
•
:
:
:
:
16K x 8 bit ROM (MSM83C154 only)
256 x 8 bit RAM
64K bytes
64K bytes
: 32
: 3
I/O Expansion mode
: UART mode (featuring error detection)
16 MHz version of MSM83C154 (12 MHz < XTAL1 .2
.;; 16 MHz) is now under development.
"Multiply" /"divide" instruction cycle
: 3,us @16 MHz operation
Standby functions
: Idle mode (CPU halt)
: Power down mode (Oscillator stop)
Activated by Software or Hardware; Providing ports with
floating or active status
The software power down mode is terminated by
interrupt signal enabling excution from the interrupted
address.
Lower power consumption achieved by 2 ,um silicon gate CMOS process
Upward compatible with MSM80C51/80C31
Packages
: 40-pin DIP, 44-pin flat package and 44-pin PLCC
312
(')
:xl
(')
c:
=i
P2.0
R/WSIGNAL
P2.7
OJ
r-
g
"c
»
C)
::D
»
~
P1.0
•
P1.7
31:
en
iii:
'11 12<:1 123 12~"~ J2f, 127, t28
*1 Flat package type and PLCC type is being developed,
PIN FUNCTIONS
Pin Name
Description
PO.O
~
PO.7
Bidirectional I/O ports. They are also the data/address bus (input/output
of data and output of lower 8-bit address when external memory is accessed.
They are open drain output when used as I/O ports, but tri'state output when used
as data/address bus.
Pl.0
~
Pl.7
Pl.0 to Pl.7 are quasi-bidirectional I/O ports. They are pulled up internally when
used as input ports. Two of them have the following secondary functions:
• Pl.0 (T2)
: Used as external clock input pin for the timer/counter 2 .
• Pl.1 (T2EX)
: Used as trigger input for the timer/counter 2 to be reloaded
or captured; causing the timer/counter 2 interrput.
314
- - - - - - - - - - - - - - - - - - - - . MSM80C154/83C154 •
PIN FUNCTIONS (CaNT.)
Description
Pin Name
P2.0 - P2.7
P2.0 to P2.7 are quasi-bidirectional I/O ports. They also output the higher 8-bit
address when an external memory is accessed. They are pulled up internally when
used as input ports.
P3.0 - P3.7
P3.0 to P3.7 are quasi-bidirectional I/O ports. They are pulled up internally when
used as input ports. They also have the following secondary functions:
.P3_0 (RXD)
Serial data input/output in the I/O expansion mode and serial data input in the
UART mode when the serial port is used .
• P3.1 (TXD)
Synchronous clock output in the I/O expansion mode and serial data output in
the UART mode when the serial port is used .
• P3.2 (INTO)
Used as input pin for the external interrupt 0, and as count-up control pin for the
timer/counter O.
• P3.3 (INT1)
Used as input pin for the external interrupt 1, and as count-up control pin for the
timer /counter 1 .
• P3.4 (TO)
Used as external clock input pin for the timer/counter O.
• P3.5 (Tl)
Used as external clock input pin for the timer/counter 1 and power down mode
control input pin .
• P3.6 (WR)
Output of the write strobe signal when data is written into external data memory .
• P3.7 (RD)
Output of the read strobe signal when data is read from external data memory.
ALE
Address latch enable output for latching the lower 8-bit address during external
memory access. Two ALE pulses are activated per machine cycle except during
external data memory access at which time one ALE pulse is skipped.
PSEN
Program store enable output which enable the external memory output to the bus
during external program memory access. Two PSEN pulses are activated per
machine cycle except during external data memory access at which two PSEN
pulses are skipped.
EA
When EA is held at "H" level, the MSM83C154 executes instructiohs from
internal program memory at address OOOOH to 3FFFH, and executes instructions
from external program memory above address 3FFFH.
When EA is held at "L" level, the MSM80C154/MSM83C154 executes instructions
from external program memory for all addresses .
RESET
If this pin remains "H" for at least 1 Jl second, the MSM80C154/MSM83C154 is
reset. Since this pin is pulled down internally, a power-on reset is achieved by
simply connecting a capacitor between Vcc and this pin.
XTAL1
Oscillator inverter input pin. External clock is input through XTAL1 pin .
XTAL2
Oscillator inverter output pin.
-------
..
VCC
-~-~--
-~,---
. ---
Power supply pin during both normal operation and standby operations_
--f---
VSS
GND pin.
315
• MSM80C154/83C154 . - - - - - - - - - - - - - - - - - - - -
DATA MEMORY AND SPECIAL FUNCTION REGISTER
LAYOUT DIAGRAM
r-oFFH
OF8H
::2:
--
-------
------ f-
r-
I----<
I----<
I----<
....- I----<
---------
--
ffff-
r~
30H
2FH
20H
1FH
18H
17H
10H
OFH
7F BIT
78
ADDRESSABLE
7 RAM
0
R7
BANK 3
RO
-R7
BANK 2
RO
R7
BANK 1
08H
07H
~
OOH
RO
'--
~
-
DIRECT BIT A DDRESSING
REGISTER AD DRESSING
DIRECT BYTE ADDRESSING
R7
BANKO
316
t---
INDIRECT AD DRESSING
- - - - - - - - - - - - - - - - - - - - - . MSM80C154/83C154 •
DETAILED DIAGRAM OF DATA MEMORY (RAM)
OFFH
255
7FH
127
2FH
7F
7E
70
7C
78
7A
79
78
47
2EH
77
76
75
74
73
72
71
70
46
20H
6F
6E
60
6C
68
6A
69
68
45
2CH
67
66
65
64
63
62
61
60
44
28H
5F
5E
50
5C
58
5A
59
58
43
2AH
57
56
55
54
53
52
51
50
42
Ci5
29H
(!)
(!)
Z
Z
Ci5
(!)
w
a:
a:
0
0
Ci5
Ul
w
«
Ul
4F
4E
40
4C
48
4A
49
48
41
28H
47
46
45
44
43
42
41
40
40
«
27H
3F
3E
30
3C
38
3A
39
38
39
26H
37
36
35
34
33
32
31
30
38
25H
2F
2E
20
2C
28
2A
29
28
37
24H
27
26
25
24
23
22
21
20
36
23H
1F
1E
10
1C
18
1A
19
18
35
22H
17
16
15
14
13
12
11
10
34
21H
OF
OE
00
OC
08
OA
09
08
33
20H
07
06
05
04
03
02
01
00
1FH
0
0
Z
a:
w
0
0
t:
I-
aJ
>aJ
le..>
le..>
Ie..>
w
a:
0
w
a:
0
«
II
w
a:
0
~
32
31
8ank 3
(!)
24
23
18H
17H
8ank 2
10H
OFH
Ul
W
~-
16
15
8ank 1
Z
Ci5
Ul
w
a:
0
0
«
a:
w
I-
Ul
08H
07H
8
7
(!)
w
a:
8ank 0
OOH
0
317
• MSM80C154/83C154 . - - - - - - - - - - - - - - - - - - - -
DETAILED DIAGRAM OF,SPECIAL FUNCTION REGISTERS
Direct
Byte
Address
U
Bit Address
(MSB)
(LSB)
WOT T32 SE RR IZC P3HZ P2HZ P1 HZ ALF
OF8H
FF
FE
FO
FC
FB
OFOH
F7
F6
F5
F4
F3
OEOH
E7
E6
E5
E4
E3
CY
AC
FO
RS1
RSO
07
06
05
04
03
OOOH
F9
1 FA 1
1
1
F8
10CON
F1
FO
B
E1
EO
ACC
OV
F1
P
02
01
DO
F2
E2
1
1
PSW
OCOH
Not Bit Addressable
TH2
OCCH
Not Bit Addressable
TL2
OCBH
Not Bit Addressable
RCAP2H
OCAH
Not Bit Addressable
RCAP2L
TF2 EXF2 RCLK TCLKEXEN2 TR2
OC8H
1 CF
1 CE
PCT
1 CO 1 CC
PT2
PS
BO
BC
1 CB
C/T2 CP/RL2
1 CA 1 C9 1 C8 1
PTl PX1
PTO
I BA I
I B8 I
·IP
I
P3
BF
I
OBOH
B7
I B6 I B5 I B4 I B3 I B2 I B1 I BO
-
ET2
ES
BB
ET1
EX1
B9
ETO
EXO
OA8H
I AI'
1
-
1 AD 1 AC
1 AB 1 AA IA9
1 A8
OAOH
1 A7
1 A6
1 A51 A4
1 A3
1 AO
90H
1 A1
Not Bit Addressable
99H
98H
1 A2
SM1
9F
9E
1 90
I
97
1 96
1 95
1 94
I I
I
SM2
REN
SMO
9C
TB8
RB8
T2CON
PXO
OB8H
EA
318
Special
Function
. Register
Symbol
TI
RI
IE
I
P2
I
SBUF
1'19B
1 9A
1 99
1 98
SCON
I
1 92
1 91
1 90
P1
93
- - - - - - - - - - - - - - - - - - - - . MSM80C154/83C154 •
Direct
Byte
Address
Special
Function
Register
Symbol
Bit Address
(LSB)
(MSB)
8DH
Not Bit Addressable
TH1
8CH
Not Bit Addressable
THO
8BH
Not Bit Addressable
TL1
8AH
Not Bit Addressable
TLO
89H
Not Bit Addressable
TMOD
88H
TCON
87H
PCON
83H
Not Bit Addressable
82H
Not Bit Addressable
DPL
81H
Not Bit Addressable
SP
80H
87
I 86 I 85 I 84 I 83 I 82 I 81 I
DPH
80
PO
319
• MSM80C154/83C154 . - - - - - - - - - - - - - - - - - - - -
SPECIAL FUNCTION REGISTERS
Timer mode register (TMOO)
NAME
ADDRESS
TMOD
89H
MSB
7._._-
LSB
c/f
GATE
BIT LOCATION
FLAG
-------4---------4M1
TMOD.O
MO
5
4
3
2
1
o
M1
MO
GATE
c/f
M1
MO
r-...6
FUNCTION
I
:
I
MO
: Timer/counter 0 mode setting
- - - - - -,- - - - I
o :
- -- - - - t o :
0
- - -
1
- - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - --
: 8-bit timer /counter with 5-bit prescalar.
J- I
- -
-
-
-
-
-
-
- - -
-
-
-
-
-
- - -
-
- -
-
- - -
-
-
- - - --
16-bit timer/counter.
___ - - - - - - - - _1- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
1
TMOD.1
M1
:
0
---1- --:- - ; I
:
:
D
: 8-bit timer/counter with 8-bit auto reloading.
-i- Ti~~;/;o~~;;rO ;e~;~;ed-i~;O-TLO-(8~bi;) ;i;;'~;/- --: counter and THO (8-bit) timer/counter. TFO is set
: by T LO carry, and TF 1 is set by THO carry.
TMOD.2
CIT
Timer/counter 0 count clock designation control bit.
XTAL1 ·2 divided by 12 clocks. is the input applied to timer/counter
o when cif = "0".
The external clock applied to the TO pin is the input applied to
timer/counter 0 when c/f = "1 ".
TMOD.3
GATE
When this bit is "0", the TRO bit of TCON (timer control register) is
used to control the start and stop of timer /counter 0 counting.
If this bit is "1", ti mer/counter 0 starts counting when both
the TRO bit of TCON and INTO pin input signal are "1", and stops
counting when either is changed to "0".
-------------4---------4-TMOD.4
MO
M1
:
MO
: Timer/counter 1 mode setting.
- - - - - - - - - - - - 1- -
-
-
- - - - - - - - -
- - - - - - - - -
-
- -
-
-
-
-
-
- - - -
- --
o : 0 : 8-bit timer/counter with 5-bit prescalar.
.
~ ~ -_~ ~ -r~~ ~ ~ ~1~~~i~-:i_~~!~~~~u~~ir~ ~ ~~_-_-_-_-_-~~ ~_-_~~~ ~ ~ -_-_~-_~
I
_-
-------------+----------1------1-1
:
0___1_: 8-bit
timer/counter with 8-bit auto reloading.
____
_,--------- _________________ _
320
TMOD.5
M1
TMOD.6
CIT
TMOD.7
GATE
1
:
1
: Timer/counter 1 operation stopped.
I
Timer/counter 1 count clock designation control bit.
XTAL 1 ·2 divided by 12 clocks is the input applied to timer/counter
1 when cif = "0".
The external clock applied to the T1 pin is the input applied to
timer/counter 1 when cif = "1 ".
When this bit is "0", the TR1 bit of TCON is used to control
the start and stop of timer/counter 1 counting.
If this bit is "1", timer/counter 1 starts counting when both
the TR1 bit of TCON and INT1 pin input signal are "1 ", and stops
counting when either is changed to "0".
- - - - - - - - - - - - - - - - - - - - - . MSM80C154/83C154 •
Power control register (peON)
NAME
ADDRESS
MSB
7
6
5
PCON
87H
SMOD
HPD
RPO
4
3
2
1
LSB
0
-
GF1
GFO
PD
IDL
FLAG
FUNCTION
PCON.O
IDL
IDLE mode set when this bit is set to "1". CPU operations are
stopped when I DLE mode is set, but XTAL 1 -2, timer /counters 0, "
and2, the interrupt circuits, and serial port remain active. IDLE mode
is cancelled when the CPU is reset or when an interrupt is generated.
PCON.1
PD
PD mode set when this bit is set to "1". CPU operations and XT ALl' 2
are stopped when PD mode is set. PD mode is cancelled when the CPU
is reset or when an interrupt is generated.
PCON.2
GFO
General purpose bit.
Testing this flag when IDLE mode is cancelled by an interrupt shows
whether the interrupt is a normal interrupt or an I DLE mode release
interrupt.
PCON.3
GF1
General purpose bit.
Testing this flag when PD mode is cancelled by an interrupt shows
whether the interrupt is a normal interrupt or a PD mode release
interrupt.
BIT LOCATION
PCON.4
-
PCON.5
RPD
Bit used to specify cancellation of CPU power down mode IIDLE or
PD) by interrupt signal.
Power down mode cannot be cancelled by interrupt signal if interrupt
is not enabled by IE !interrupt enable register) when this bit is "0".
If the interrupt flag is set to "1" by an interrupt request signal when
this bit is "1" leven if interrupt is disabled), the program is executed
from the next address of the power down mode setting instruction.
The flag is reset to "0" by software.
PCON.6
HPD
The hard power down setting mode is enabled when this bit is set to
"1 ".
If the level of the power failure detect signal applied to the HPDI pin
Ipin 3.5) is changed from "1" to "0" when this bit is "1", XTAL 1 -2
oscillation is stopped and the system is put into hard power down
mode. HPD mode is cancelled when the CPU is reset.
PCON.7
SMOD
Reserved bit. The output data is "1" if the bit is read.
When the timer/counter 1 carry signal is used as a clock in mode 1,
2 or 3 of the serial port, this bit has the following functions.
The serial port operation clock is reduced by 1/2 when the bit is
"0" for delayed processing. And when the bit is "1", the serial port
operation clock is normal for faster processing.
321
• MSM80C154/83C154
.--------------~------
Timer control register (TCON)
NAME
ADDRESS
MSB
7
6
5
4
3
2
1
LSB
0
TCON
88H
TFl
TRl
TFO
TRO
IEl
ITl
lEO
ITO
BIT LOCATION
FLAG
FUNCTION
TCON.O
ITO
External interrupt 0 signal used in level detect mode when this bit is
"0". and in trigger detect mode when "1".
TCON.l
lEO
Interrupt request flag for external interrupt O.
Bit is reset automatically when interrupt is serviced.
Bit can be set and reset by software when ITO = "1".
TCON.2
ITl
External interrupt 1 signal used .in level detect mode when this bit is
"0". and in trigger detect mode when "1".
TCON.3
IEl
Interrupt request flag for external interrupt 1.
Bit is reset automatically when interrupt is serviced.
Bit can be set and reset by software when ITl = "1 ".
TCON.4
TRO
Counting start and stop control bit for timer/counter O.
Timer /counter 0 starts counting when this bit is "1". and stops
counting when "0".
TCON.5
TFO
Interrupt request flag for timer interrupt O.
Bit is reset automatically when interrupt is serviced.
Bit is set to "1" when carry signal is generated from timer/counter O.
TCON.6
TRl
Counting start and stop control bit for timer/counter 1.
Timer/counter 1 starts counting when this bit is "1 .... and stops
counting when "0".
TCON.7
TFl
Interrupt request flag for timer interrupt 1.
Bit is reset automatically when interrupt is serviced.
Bit is set to "1" when carry signal is generated from timer/counter 1.
322
- - - - - - - - - - - - - - - - - - - - . MSM80C154/83C154 •
Serial port control register (SCON)
NAME
ADDRESS
SCON
98H
BIT LOCATION
FLAG
6
5
4
3
2
.1
LSB
0
SM1
SM2
REN
TB8
RB8
TI
RI
MSB
7
SMO
--
FUNCTION
SCON.O
RI
"End of serial port reception" interrupt request flag.
This flag must be reset by software during interrupt service routine.
This flag is set after the eighth bit of data has been received when in
mode 0, or by the STOP bit when in any other mode. In mode 2
or 3, however, R I is not set if the R B8 data is "0" with SM2 = "1".
RI is set in mode 1 if STOP bit is received when SM2 = "1 ".
SCON.1
TI
"End of serial port transmission" interrupt request flag. This flag
must be reset by software during interrupt service routine.
This flag is set after the eighth bit of data has been sent when in
mode 0, or after the last bit of data has been sent when in any other
mode.
SCON.2
RB8
The ninth bit of data received in mode 2 or 3 is passed to RB8.
The STOP bit is applied to RB8 if SM2 = "0" when in mode 1.
RB8 can not be used in mode O.
SCON.3
TB8
The TB8 data is sent as the ninth data bit when in mode 2 or 3.
Any desired data can be set in TB8 by software.
SCON.4
REN
Reception enable control bit
No reception when RE N = "0".
Reception enabled when REN = "1 ".
SCON.5
SM2
If the ninth bit of received data is "0" with SM2 = "1" in mode 2 or
3, the "end of reception" signal is not set in the RI flag.
Nor is the "end of reception" signal set in the RI flag if the STOP
bit is not "1" when SM2 = "1" in mode 1.
SCON.6
SM1
,I SM1 'MODE:
----------,
,
--
-
I
0
J
0
J
0
J
1
I
J
1
1
J
8-bit UART variable baud rate
J
J
9-bit UART 1/32 XTAL 1, 1/64 XTAL 1
-- -
0
2
J
- - - -
1
-
8-bit shift register I/O
0
------- - - - ---- --------------------------J
---------
SMO
J
_ _ _ _ _ .J _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
--------J
SCON.7
--
J
SMO
,
-,- -------------- --- ---- - - - - - --- ---: baud rate
( ______________________________________
_1- _ _ _ _ _
:
1
I
,J
3
:,
, 9-bit UART variable baud rate
323
• MSM80C154/83C154 . - - - - - - - - - - - - - - - - - - - Interrupt enable register (IE)
5
4
3
2
,
LSB
0
ET2
ES
ET'
EX'
ETO
EXO
NAME
ADDRESS
MSB
7
IE
OA8H
EA
BIT LOCATION
FLAG
IE.O
EXO
IE.'
ETO
IE.2
EX'
Interrupt control bit for external interrupt 1.
Interrupt disabled when bit is "0".
Interrupt enablea when bit is "'''.
IE.3
ETl
Interrupt control bit for timer interrupt ,.
Interrupt disabled when bit is "0".
I nterrupt enabled when bit is ",".
lEA
ES
IE.5
ET2
IE.6
-
IE.7
EA
6
-
FUNCTION
Interrupt control bit for external interrupt O.
Interrupt disabled when bit is "0".
Interrupt enabled when bit is ",".
I
Interrupt control bit for timer interrupt O.
Interrupt disabled when bit is "0".
Interrupt enabled when bit is "'''.
Interrupt control bit for serial port.
Interrupt disabled when bit is "0".
Interrupt enabled when bit is "'''.
~
324
Interrupt control bit for timer interrupt 2.
Interrupt disabled when bit is "0".
Interrupt enabled when bit is "'''.Reserved bit. The output data is "'" if the bit is read.
Overall interrupt control bit.
All interrupts are disabled when bit is "0".
All interrupts are controlled by IE.O thru IE.5 when bit is ",".
- - - - - - - - - - - - - ' - - - - - - - - - . MSM80C154/83C154 •
I nterrupt priority register (I P)
NAME
ADDRESS
MSB
7
6
5
4
3
2
1
LSB
0
IP
OB8H
PCT
-
PT2
PS
PTl
PXl
PTO
PXO
BIT LOCATION
FLAG
IP.O
PXO
Interrupt priority bit for external interrupt O.
Priority is assigned when bit is "1 ".
IP.l
PTO
Interrupt priority bit for timer interrupt O.
Priority is assigned when bit is "1 ".
IP.2
PXl
Interrupt priority bit for external interrupt 1.
Priority is assigned when bit is "1".
IP.3
PTl
Interrupt priority bit for timer interrupt 1.
Priority is assigned when bit is "1".
IP.4
PS
IP.5
PT2
IP.6
-
IP.7
PCT
FUNCTION
Interrupt priority bit for serial port.
Priority is assigned when bit is "1".
Interrupt priority bit for timer interrupt 2.
Priority is assigned when bit is "1".
Reserved bit. The output data is "'" if the bit is read.
Priority interrupt circuit control bit.
The priority register contents are valid and priority assigned
interrupts can be processed when this bit is "0". When the bit is
"1", the priority interrupt circuit is stopped, and interrupts can only
be controlled by the interrupt enable register (IE).
325
eMSM80C154/83C154
e - - - - - - - - - - - - - - - - - -__
Program status word register (PSW)
NAME
ADDRESS
MSB
7
6
5
4
3
2
PSW
ODOH
CY
AC
FO
RS'
RSO
OV
BIT LOCATION
FLAG
PSW.O
LSB
0
F'
P
FUNCTION
Accumulator (ACC) parity indicator.
"'" when the "'" bit number in the accumulator is an odd number,
and "0" when an even number.
PSW.'
F'
User flag which may be set to "0" or "'" as desired by the user.
PSW.2
OV
Overflow flag which is set if the carry C6 from bit 6 of the ALU or
CY is "'" as a result of an arithmetic operation. The flag is also
set to "'" if the resultant product 'of executing a,multiplication
instruction (MUL AB) is greater than OFFH, but is reset to "0"
if the product is less than or equal to OFFH.
PSW.3
RSO
RAM register bank switch
PSW.4
326
P
,
RS'
RS'
RSO
BANK
0
0
,
0
,
OOH - 07H
0
2
'OH-'7H
3,
'SH -'FH
0
,
,
,
RAM ADDRESS
OSH -OFH
PSW.5
FO
User flag which may be set to "0" or "'" as desired by the user.
PSW.6
AC
Auxiliary carry flag.
This flag is.set to "'" if a carry C 3 is generated from bit 3 of the
ALU as a result of executing an arithmetic operation instruction.
In all other cases, the flag is reset to "0".
PSW.7
CY
Main carry flag.
This flag is set to "'" if a carry C 7 is generated from bit 7 of
the ALU as result of executing an arithmetic operation instruction.
If a carry C 7 is not generated, the flag is reset to "0".
- - - - - - - - - - - - - - - - - - - - . MSM80C154/83C154 •
I/O control register (lOCON)
NAME
ADDRESS
.. _-----------
laCON
OF8H
BIT LOCATION
FLAG
IOCON.O
ALF
M~=f 6~5SERRI~C
.I,;c= ~i
3J:,:~
1
P2~~P1HZ
'-~~T
--:;:-;;
LSB
0
1
ALF
FUNCTION
If CPU power down mode (PD, HPD) is activated with this bit set to
"1 ", the outputs from ports 0,1,2, and 3 are switched to floating
status.
When this bit is "0", ports 0, 1,2, and 3 are in output mode .
..
IOCON.1
P1 HZ
Port 1 becomes a high impedance input port when this bit is "1 ",
IOCON.2
P2HZ
Port 2 becomes a high impedance input port when this bit is "1 ".
IOCON.3
P3HZ
Port 3 becomes a high impedance input port when this bit is "1".
IaCONA
IZC
IOCON.5
SERR
IOCON.6
T32
IOCON,7
WDT
_.
-_..
-
The 10 kohm pull-up resistance for ports 1,2, and 3 i.s switched off
when this bit is "1 ", leaving only the 100 kohm pull-up resistance.
Serial port reception error flag.
This flag is set to "1" if an overrun or framing error is generated
when data is received at a serial port.
The flag is reset by software.
Timer/counters 0 and 1 are connected serially to form a 32-bit
timer/counter when this bit is set to "1 ",
TF1 of TCON is set if a carry is generated in the 32·bit timer/counter.
Watchdog timer mode is set when this bit is set to "1 ", And if TF1
is set to "1" after watchdog timer mode has been set, the CPU is
reset and the program is executed from address O.
327
eMSM80C154/83C154 e - - - - - . , - - - - - - - - - - - - - - - Timer 2 control register (T2CON)
NAME
ADDRESS
MSB
7
T2CON
OC8H
TF2
BIT LOCATION
FLAG
I
I
I
I EXF21 RCLK I TCLK
6
5
4
3
I
2
EXEN21 TR2
LSB
0
I
I
I C/T2 I CP/RL2
1
FUNCTION
T2CON.0
CP/RL2
Capture mode is set when TCLK + RCLK = "0" and CP/RL2 = "1 ".
16-bit auto reload mode is set when TCLK + RCLK = "0" and.
CP/RL2 = "0".
CP/R L2 is ignored when TCLK + RCLK = "1 ".
T2CON.1
C/T2
Timer/counter 2 count clock designation control bit.
The internal clocks (XTAL 1 ·2 -;- 12, XTAL 1 ·2 -;- 2) are used when
this bit is "0", and the external clock applied to the T2 pin is passed
to timer/counter 2 when the bit is "1 ".
T2CON.2
TR2
Timer/counter 2 counting start and stop control bit.
Timer/counter 2 commences counting when this bit is "1" and stops
counting when "0".
T2CON.3
EXEN2
T2CON.4
TC.LK
T2EX timer/counter 2 external control signal control bit.
Input of the T2EX signal is disabled when this bit is "0", and
enabled when "1".
:
I
Serial port transmit circuit drive clock control bit.
Timer/counter 2 is switched to baud rate generator mode when this
bit is "1 ", and the timer/counter 2 carry signal becomes the serial
port transmit clock.
Note, however, that the serial ports can only use the timer/counter 2
carry signal in serial port modes 1 and 3.
T2CON.5
RCLK
Serial port receive circuit drive clock control bit.
Timer/counter 2 is switched to baud rate generator mode when this
bit is "1 ", and the timer/counter 2 carry signal becomes the serial
port receive clock.
Note, however, that the serial ports can only use the timer/counter 2
carry signal in serial port modes 1 and 3.
T2CON.6
EXF2
Timer/counter 2 external flag.
This bit is set to "1" when the T2EX timer/counter 2 external
control signal level is changed from "1" to "0" while EXEN2 = "1".
This flag serves as the timer interrupt 2 request signal. If an interrupt
is generated, EXF2 must be reset to ;'0" bY,software.
T2CON.7
TF2
Timer/counter 2 carry flag.
This bit is set to "1" by a carry signal when timer/counter 2 is in
16-bit auto reload mode or in capture mode.
This flag serves as the timer interrupt 2 request signal. If an interrupt
is generated, TF2 must be reset to "0" by software.
--
328
- - - - - - - - - - - - - - - - - - - - . MSM80C154/83C154 •
LIST OF INSTRUCTIONS
LIST OF INSTRUCTION SYMBOLS
A
AB
AC
B
C
DPTR
PC
Rr
SP
AND
OR
XOR
+
x
;
;
;
;
;
;
;
;
;
;
:
:
:
:
:
/
(X)
((X))
#
@
<
>
:
:
:
:
;
bit address
:
code address:
data
relative offset:
direct address:
Accumulator
Register pair
Auxiliary carry flag
Arithmetic operation register
Carry flag
Data pointer
Program counter
Register indicator (r ; 0 - 7)
Stack poi nter
Logical product
Logical sum
Exclusive OR
Addition
Subtraction
Multiplication
Division
Denotes the contents of X
Denotes the contents of address determined by the contents of X
Denotes the immediate data
Denotes the indirect address
Equality
Non equality
Substitution
Substitution
Negation
Smaller than
Larger than
RAM and the special function register bit specifier address (b o - b,)
Absolute address (Ao - A, s)
Immediate data (10 - I,)
Relative jump address offset value (Ro - R,)
RAM and the special function register byte specifier address (a o - a,)
329
e MSM80C154/83C154
e-------------------'--
MSM80C154/MSM83C154 INSTRUCTION TABLE
~
0
0000
0
0000
NOP
1
0001
JBC bit,
rei
2
0010
JB bit,
rei
3
0011
JNB bit,
rei
4
0100
JC bit,
rei
5
0101
JNC rei
6
0110
JZ rei
7
0111
JNZ rei
I
1~01
I
I
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
RR A
INCA
INC
direct
INC @RO
INC@Rl
ACALL
LCALL
i address 11 dd
16 . RRC A
.... (PageO) .:.. ress
i
DEC A
DEC
direct
DEC @RO
DEC @Rl
ADD A,
#data
ADDA,
direct
ADDA,
@RO
ADDA,
@Rl
ADDC A,
@RO
ADDC A,
@Rl
ORLA,
@RO
ORLA,
@Rl
II"'" AJMP
""~"
8
1
0001
1000 ~
LJMP
address 11
(Page 0) address 16
...
I
AJMP
i address 11
... (Page 1)
l
I
RET
ACALL I
address 11
(Page 1)
D
1101
RLC A
III..
rI ACAL~
r
r
AJMP
XRL
address 11 I d·
t A
I (Page 3) i Irec,
I
"'II'"ORL A
#d t '
a a
I
"'II'"
i ANL
ORLA,
direct
II"'"
ANL
direct,
#data
A,
#data
ANLA,
direct
ANLA,
@RO
ANLA,
@Rl
I
XRL
XRLA
direct, I #d t '
#data.
a 'l.
XRLA,
direct
XRLA,
@RO
XRLA,
@Rl
MOV @RO,
#data
MOV @Rl,
#data
MOV
direct,
@RO
MOV
direct,
@Rl
SUBB A,
@RO
SUBB A,
@Rl
MOV @RO,
direct
MOV @Rl,
direct
l
I
T
r
tACALLr"
.
MOV
'address 11. ORL C,
JMP
I MOV A,
direct,
, (Page 3) ~ bit
:'A+DPTR I #data
... #data
r
AJMP
ANL C
address 11
b·t'
(Page 4)....
I
ACALL
address 11
l(page 4)
r;MOV bit,.
l
I
MOVC A
@A+PC'
"!
I
C
MOVC A,
~A+DPTR
MOV C,
bit
INC
DPTR
I
lilt..
r
ANLC,bit I
11 ,
(Page 5)
AJMP
PUSH
address 11
direct
(Page 6)
- - ~-~ACALL
POP
address 11
direct
(Page 6)
AJMP
address 11
(Page 7)
F
1111
MOVX
@DPTR,A
ACALL
address 11
~~ag: 7)
-
I
r.
!
I
MOV
,direct 1,
... ' direct 2
SUBB A,
#data
SUBB A,
direct
MUL AB
...
i CJNE A,
I
#data,
rei
I
SWAP A
...
....
lit..
...
CJNE A, CJNE @RO~ CJNE @Rl,
#data,
#data,
I direct,
rei
rei
rei
II"'"
-r
CLR bit
I
CLR C
XCH A,
direct
XCH A,
@RO
XCH A,
@Rl
XCHD A,
(a) RO
XCH A,
@Rl
MOVA,
@RO
MOVA,
@Rl
MOV
@RO,A
MOV
@Rl,A
--~~--
SETB C
SETB bit
MOVX A MOVX A,
(al RO
'
(a) Rl
...
...
MOVX
(wRO, A
~
DAA
_.
DJNZ
direct,
III.. rei
II"'"
CLR A
MOVA,
direct
CPL A
MOV
direct, A
--
MOVX
(a' Rl, A
"~--~
2 BYTE
3 BYTE
MNEMONIC
2 CYCLE
I
~
f---"-~.-
MOVX A,
@DPTR
I DIV AB
,..
II"'"
...
,..
raddress
ACALL
i CPL bit
CPL C
E
1110
330
ADDC A, AD DC A,
direct
#data
I
address 11 , ANL
i
~ (Page 2) I direct, A
l
C
1100
,..
RETI
AJMP
A
ORA L C, bit: address 11
1010
(Page 5)
B
1011
RLA
I!
' AJMP
,.. ORL
I ORL
lddress 11 d·
t A I direct,
(Page 2) , Irec,
... #data
SJMP rei
MOV
DPTR
#data 16
....
4 CYCLE
----~
"-~~-
'-----
- - - - - - - - - - - - - - - - - - - - . MSM80C154/83C154 •
~--r------,------'---------
.
__.. _-_.._-
_.
__.. _- . - , - - - - , - - - - , - - - - - - - - ,
o
8
1000
9
1001
A
1010
B
1011
C
1100
1101
E
1110
F
1111
INC RO
INC Rl
INC R2
INC R3
INC R4
INC R5
INC R6
INC R7
0001
DEC RO
DEC Rl
DEC R2
DEC R3
DEC R4
DEC R5
DEC R6
DEC R7
2
0010
ADD A,
RO
ADDA,
Rl
ADD A,
R2
ADD A,
R3
ADDA,
R4
ADD A,
R5
ADD A,
R6
ADD A,
R7
3
0011
AD DC A,
RO
ADDC A,
Rl
AD DC A,
R2
ADDC A,
R3
AD DC A,
R4
AD DC A,
R5
ADDC A,
R6
ADDC A,
R7
4
0100
DRL A,
RO
ORL A,
Rl
ORL A,
R2
ORL A,
R3
ORL A,
R4
5
ANL A,
RO
ANL A,
Rl
XRL A,
RO
XRL A,
Rl
I""'H L
IH ~
o
0000
1
0101
6
0110
7
0111
8
1000
9
1001
"
MOV RO,
#data
'"MOV
d'Irect,
.... RO
SUBB A,
RO
XCH A,
RO
DJNZ RO
rei
....
E
MOV A,
1110RO
F
1111
XRL A,
R4
XRL A,
R3
XRL A,
R5
I
I
ORL A,
R7
MOV" MOV
direct,
direct,
R2.... R3
SUBB A,
Rl
SUBB A,
R2
MOV
direct,
R4
SUBB A,
R3
XRLA,
R6
XRL A,
R7
MOV R6,
#data
MOV R7,
#data
I,
r
r
r
r
MOV R2, "MOV R3, ! MOV R4, MOV R5,
#data
#data
#data: #data
MOV
direct,
Rl
I
I
MOV
MOV
I direct
I direct,
~ R5 ' . ~ R6
SUBB A, • SUBB A,
R4
R5
MOV R2, "MOV R3'I MOV R4, rMOV R5,
: direct
direct
direct:. direct
I
MOV
direct,
R7
SUBB A,
R6
SUBB A,
R7
MOV R6,
direct
MOV R7,
direct
.................
XCH A,
Rl
~--_,,~---~---
1101
i
CJNE RO~ CJNE Rl, CJNE R2, CJNE R31 CJNE R41 CJNE R5, CJNE R6~ CJNE R7;
#data,
#data,
#data,
#data, i #data, . #data,
#data,
#data,
.... rei
.. rei
rei.... rei
~ ; rei
... rei
.... rei
rei
C
1100
o
XRLA,
R2
MOV Rl,
#data
....
B
1011
ORL A,
R6
i
ANL A,
R7
,.
-A "MOV RO, I""MOV Rl,
1010
direct
direct
ORL A,
R5
II
MOV RO,
A
__
DJNZ Rl
rei
'MOV A,
Rl
MOV Rl,
A
XCH A,
R2
XCH A,
R3
I:
XCH A,
XCH A,
I
XCH A,
R6
R~R5
XCH A,
R7
~----~,.r---~,,~
DJNZ R2, DJNZ R3, DJNZ R4'I DJNE R5, DJNE R6, DJNE R7,
rei
rei
rei
rei
rei
rei
....
MOV A,
R2
MOV R2,
A
........
MOV A,
R3
MOV. A,
R4
MOV R3, . MOV R4,
A
A
....
MOV A,
R5
MOV A,
R6
MOV A,
R7
MOV R5,
A
MOV R6,
A
MOV R7,
A
331
• MSM80C154/83C154 . - - - - - - - - - - - - - - - - - - - - -
INSTRUCTION SET DETAILS
..
I nstruction Code
a.
Mnemonic
>
t-
Description
Bytes Cycles
0 7 D. Os D. D. 0, 0,0 0
ADDA, Rr
0
0
1 0
1
r, r, ro
1
1
(AC), (OV), (C), (A) - (A)+(Rrl
ADD A, direct
0
0
1 0
0
1 0
2
1
(AC), (OV), (Cl, (A) - (A)+(direct
address)
1 ro
1
1
(AC), (OV), (C), (A) - (A)+((Rrl)
0 1 O. 0 1 0 0
17 I. Is I. 13 I, I, 10
2
1
(AC), (OV), (C), (A) - (A)+#data
1
a7 a. as a. a3 a, a, ao
ADD A,@Rr
0
ADD A, #data
0
ADDC A, Rr
0
0
1
1 1 r. r, ro
1
1
(AC), (OVI. (C), (A) - (A)+(C)+(Rrl
0
0
1
1 0
2
1
(AC), (OV), (C), (A) - (A)+(C)+(direct
address)
1
1
(AC), (OV), (Cl, (A) - (A)+(C)+«Rrl)
2
1
(AC), (OV), (Cl, (A) +- (A)+(C)+#data
1
1
(AC), (OV), (C), (A)
2
1
(AC), (OV), (C), (A) - (A)-«C)+{direct
address))
1
1
(AC), (OV), (C), (A) - (A)-«C)+((Rr))
2
1
(AC), (OV), (C), (A) - (A)-«C)+#data)
ADDC A, direct
0
1 0 0
1
1 0
1
a7 a. as a. a3 a. a, ao
.
ADDCA,@Rr
0
0
1
1 0
1
0
ADDC A, #data
0
0
1
1 0
1 0
1 ro
c:
'£
0
I, I. Is I. I. I. I, 10
:l
~
.!:
SUBB A, Rr
1 0 0
1
1 0
1 0
1 r. r, ro
<-
(A)-«C))+((Rrl)
c:
.g
D
..E
....
.E
a.
0
SUBB A, direct
0
1 0
1
a7 a. as a. a. a. a, ao
SUBB A,@Rr
1 0 0
1 0
1
1 0
1 0
1 0
1 ro
;;
SUBB A, #data
I-
RRC A
0 0 0
1
0 0
1
1
1
Accumulator
1
f"H:1-1-1-1-1-1-1;1
....
-'Ii
::l I:
E'-
::l
U
U
«
SWAP A
1
1
0 0 0
1 0
0
1
1
(A. - ,) ... (A. - 3)
INC
A
0 0
0 0 0
1 0
0
1
1
(A)
INC
Rr
0 0 0 0
1 r. r, r.
1
1
(Rd
...
INC
direct
0 0 0 0 0 1 0 1
a, a. as a. a3 a. a, a.
2
1
(direct address)
E
INC
@Rr
0
0 0 0 0
1 1 r.
1
1
((Rd)
....&!
INC
DPTR
1
0
1
1
2
(DPTR)
DEC
A
0 0 0
1 0
1 0 0
1
1
(A)
DEC
Rr
0 0 0
1
1 r, r, r.
1
1
(Rd
DEC
direct
0 0 0 1 0 1 0 1
a, a. as a_ a3 a. a, a.
2
1
(direct address)
DEC
@Rr
0 0 0
1
1
((Rd)
+-
1
(A)
+-
(A) AND (Rd
1
(A)
+-
(A)
I 1
(A)
+-
(A) AND ((Rd)
+-
(A)+l
(Rd+l
+-
+-
(direct address)+l
I:
e
~
I:
E
eu
-
1
0 0 0
1
+-
+-
((Rd)+l
+-
(DPTR)+l
(A)-l
+-
,
(Rd-l
I:
I:
A,Rr
0
1 r. r, r.
1
ANL
A, direct
0 1 0 1 0 1 0 1
a7 a. as a. a3 a. a, a.
2
A,@Rr
..
I:
,2
u
'c,
0
oJ
1 0
1 1 r.
AND (direct address)
I
1
2 , 1
(A) <- (A) AND #data
0 1 0 1 0 1 0 0
17 I. Is I- 13 I. I, I.
ANL
direct, A
0 1 0 1 0 0 1 0
a, a. as a_ a3 a. a, a.
2
1
(direct address) <- (direct address)
AND(A)
ANL
direCt,
#data
0 1 0 1 0 0 1 1
a7 a. as a. a3 a. a, a.
17 I. Is I- 13 I. I, I.
3
2
(direct address)
AND #data
ORL
A,Rr
0
1 r. r, r.
1
1
(A)<-(A)OR(Rd
ORL
A, direct
0 1 0 0 0 1 0 1
a, a. as a. a3 a, a, a.
2
1
(A)
+-
(A) OR (direct address)
ORL
A,@Rr
0
1 r.
1
1
(A)
+-
(A) OR ((Rd)
ORL
A, #data
0
1 0 0 0 1 0 0
I, I. Is I- 13 I. I, I.
2
1
(A) <- (A) OR #data
----
~
c.
0
'iij
1 0
1
((Rr))-l
A, #data
tJ
::l
0
1 0
I
I
(direct address)-l
ANL
,2
t:
,:
1 1 r.
ANL
ANL
III
1 0
+-
1 0
1 0
"-----_.
0
0 0
1
+-
(direct address)
333
• MSM80C154/83C154 . - - - - - - - - - - - - - - - - - - - - - , - - - -
INSTF)UCTION SET DETAILS (CONT.)
.,
c.
>
-I-
I nstruction Code
Mnemonic
Description
Bytes Cycles
0, D. 0, 0_ D. O 2 0 1 Do
ORL
direct, A
0 1 0 0 0 0 1 0
a, a. a, a_ a. a. al ao
2
1
(direct address)
(A)
+-
(direct address) OR
ORL
direct,
#data
0 1 0 0 0 0 1 1
a, a. as a. a. a. al ao
I, I. I, I. I. I. II 10
3
2
(direct address)
#data
+-
(direct
address) OR
,
XRL
A, Rr
0
r. rl ro
1
1
(A)
+-
(A) XOR (Rd
XRL
A, direct
0 1 1 0 0 1 0 1
a, a. a, a. a. a. al ao
2
1
(A)
+-
(A) XOR (direct address)
XRL
A,@Rr
0
ro
1
1
(A)
+-
(A) XOR ((R'd)
XRL
A, #data
0 1 1 0 0 1 0 0
I, I. I, I. I. I. II 10
2
1
(A)
+-
(A) XOR #data
XRL
direct, A
0 1 1 0 0 0 1 0
a, a. a, a_ a. a. al ao
2
1
(direct address)
XOR(A)
+-
(direct address)
XRL
direct,
#data
0 1 1 0 0 0 1 1
a, a. a, a. a. a. al ao
I, I. 15 I_ I. I. II 10
3
2
(direct address)
#data
+-
(direct address) XOR
MOV A, #data
0 1 1 1 0 1 0 0
I, I. I, I_ I. I. II 10
2
1
(A)
MOV Rr, #data
{)
1 1 1 1 r. rl ro
I, I. I, I_ I. I. II 10
2
1
(Rd
MOV direct,
#data
0 1 1 1 0 1 0 1
a, a. a, a. a. a. al ao
I; I. I, I. I. I. II 10
3
2
(direct address)
+-
#data
....,
.S!
'"
MOV @Rr, #data
0
1 1 1 0 1 1 ro
I, I. I, I_ I• I. II 10
2
1
(Rd)
a!
MOV DPTR,
#data 16
1 0 0 1 0 0 0 0
II; h_ II. III 111 110 I. I.
I, I. I, I. I. I. II 10
3
2
(DPTR)
eLR
e
1
1
0
0
SETB e
1
1
0
1 0
'"e:
.g
u
2
1;;
.!:
e:
0
.;:;
~
1
1
1
1
0
0
1
0
1
1
Q)
c.
0
c;;
.~
Cl
0
...J
'"e:
0
.;:;
u
2
1;;
e:
Cl
e:
'E
lIA
l!l
'tl
E
E
-
'"e:
0
.;:;
u
2
e:
+-
#data
+-
1
1
1
1
(e) ..... 0
1
1
1
1
(e)
+-
1
1
1
(C)
+-
(e)
ANL
C, bit
1 0 0 0 0 0 1 0
b, b. b, b_ b. b. b l b o
2
2
(e)
+-
(e) AND (bit address)
ANL
e.lbit
1 0 1 1 0 0 0 0
b, b. b, b. b. b. b l b o
2
2
(e)
+-
(e) AND (bit address)
ORL
C, bit
0 1 1 1 0 0 1 0
b, b. b, b. b. b. b l b o
2
2
(e) ..... (e) OR (bit address)
ORL
e.lbit
1 0 1 00 0 0 0
b, b. b,- b. b. b. b l bo
2
2
(e)
+-
(e) OR (bit address)
MOV C, bit
1 0 1 0 0 0 1 0
b, b. b, b_ b. b. b l bo
2
1
(C)
+-
(bit address)
~
1
1
#data 16
1
.!:
.g
0
#data
e
1;;
1 0
0
+-
ePL
0
1
0 0
#data
+-
Q)
c.
0
Cl
~
~.
_.-
'"
U
-
- - - - - - - - - - - - - - - - - - - - - - . MSM80C154/83C154 •
INSTRUCTION SET DETAILS (CONT.)
.,0.
Instruction Code
Mnemonic
>
t-
Description
Bytes Cycles
D, D. D, D. D3 D2 D, Do
MOV bit, C
2
2
(bit address)
+-
(C)
1 1 0 1 0 0 1 0
b 7 b. b, b. b 3 b 2 b, b o
2
1
(bit address)
+-
1
1
0
0
1
0
0
1
0
1:>, b. b, b. b 3 b 2 b, b o
SETS bit
c:
on
o c:
',fj 0
"'.-
... CLR
.,U
bit
2
1
(bit address)
+-
0
.~ ~
1 1 0 0 0 0 1 0
b 7 b. b, b. b 3 b 2 b, b o
CPL
bit
1 0 1 1 0 0 1 0
b 7 b. b, b. b 3 b 2 b, b o
2
1
(bit address)
+-
(bit address)
MOV
A,Rr
1
r2 r, ro
1
1
(A)
+-
(Rrl
MOV A, direct
1 1 1 0 0 1 0 1
a7 a. a, a. a3 a2 a, ao
2
1
(A)
+-
(direct address)
MOV A,@Rr
1
1
1
0
0
1
ro
1
1
(A)
+-
((Rrl)
MOV Rr, A
1
1
1
1
1
r 2 r, r 0
1
1
MOV Rr,direct
1 0 1 0 1 r 2 r, ro
a7 a. a, a. a3 a2 a, ao
2
MOV direct, A
1 1 1 1 0 1 0 1
a7 a. a, a • a3 a2 a, ao
2
~
c.:::>
aJ .-
on
c:
0
.;;
u
:::>
~
.!:
.,
~
't;
c:
...~
'"
1
0
1
1
(Rrl
+-
(A)
2
(Rrl
+-
(direct address)
1
(direct address)
+-
(A)
MOV direct, Rr
1 0_ 0 0 1 r2 r, ro
a7 a. a, a. a3 a2 a, ao
2
2
(direct address)
+-
(Rr)
MOV direct,
@Rr
1 0 0 0 0 1 1 ro
a7 a. a, a. a3 a2 a, ao
2
2
(direct address)
+-
((Rrl)
MOV @Rr,A
1
ro
1
1
((Rrl)
+-
(A)
MOV @Rr,
direct
1 0 1 0 0 1 1 ro
a7 a. as a. a3 a2 a, ao
2
2
((Rrl)
+-
(d irect address))
1 0
0
1
0
0
1
1
1
2
(A)
((A)+(DPTR))
1 0
0
0
0
0
1
1
1
2
(PC) +- (PC) + 1
(A) +- ((A) + (PC))
0
0
1
1
1
1
0
1
1
., on
"oc: MOVCA,
8.2
+-
@A+DPTR
c:o
'" :::>
t;,;;
MOVC A,@A+PC
§ ~
u·-
.,
I
-----
~
0
1
XCH
A, Rr
1
r2 r, ro
1
1
(A) "" (Rr)
XCH
A, direct
1 1 0 0 0 1 0 1
a7 a. a, a. a3 a2 a, ao
2
1
(A) "" (direct address)
A,@Rr
1
1
0
0
0
1
1
r0
1
1
(A) "" ((Rr))
XCHD A,@Rr
1
1
0
1
0
1
1
r0
1
1
(Ao - 3 ) "" (( R r 0 - 3 ))
1
Olon
c: c:
'" .0
.<:
u'"
XU
., 2
",t;;
... c: XCH
0
"'.-
335
eMSM80C154/83C154e---------------------------------------INSTRUCTION SET DETAILS (CONT.)
.,Co
>
I-
I nstruction Code
Mnemonic
Description
Bytes Cycles
D, D. Ds D, D3 D2 D, Do
PUSH direct
1 1 0 0 0 0 0 0
a, a. as a, a3 a2 a, a o
2
2
(SP) <- (SP)+l
((SP)) <- (direct address)
POP
1 1 0 1 0 0 0 0
a, a. as a, a 3 a 2 a, ao
2
2
(direct address) <- ((SP))
(SP) <- (SP)-l
ACALL addr 11
A,oA9 A. 1 0 0 0 1
A,A.A s A,A 3 A2 A,A o
2
2
(PC) <- (PC)+2
(SP) <- (SP)+l
((SP)) <- (PC o -,)
(SP) +-- (SP)+1
((SP)) +-- (PC. -,,)
(PCo-,o) <- Ao-,o
LCALL addr 16
0 0 0 1 0 0 1 0
A15AI,A13A'2Al1AIOA9 A.
A,A6 A S A,A3 A 2 A ,Ao
3
2
(PC) +-- (PC)+3
(SP) <- (SP)+1
((SP)) <- (PC. -,)
(SP) <- (SP)+1
((SP)) <- (PC.- IS )
(PC. -IS) <- A.-IS
RET
0
0
1
0
0
0
1
0
1
2
(PC. -IS) +-- ((SP))
(SP) +-- (SP)-1
(PC.-,) <- ((SP))
(SP) +-- (SP)-1
RETI
0
0
1
1
0
0
1
0
1
2
(PC.- IS ) +-- ((SP))
(SP) <- (SP)-1
(PC.-,) +-- I(SP))
(SP) +-- (SP)-l
AJMP addr 11
AloA. A. 0 0 0 0 1
A, A. As A, A3 A2 Al Ao
2
2
(PC) <- (PC)+2
(PCo-,o) <-A o- Io
UMP addr 16
0 0 0 0 0 0 1 0
A15AI,A13A12Al1AloA. A.
A, A. As A, A3 A2 Al Ao
3
2
(PC. -IS) <- A.-IS
SJMP rei
1 0 0 0 0 0 0 0
R, R. Rs R, R3 R2 R, Ro
2
2
(PC) +-- (PC)+2
(PC) <- (PC)+relative offset
1
2
(PC) <- (A)+(QPTR)
3
2
3
2
direct
c'"
0
'fi
2
1;;
c
.,c
.;:
:l
e
.0
:l
en
'"c
0
"E
2
1;;
C
Co
E
...,:l
JMP
@A+DPTR
0
1
1
1
0
0
1
1
CJNE A, direct,
rei
1 0 1 1 0 1 0 1
a, a. as a, a3 a2 al a.
R,R.RsR,R3R2RIRo
CJNE A, #data,
rei
1 0 1 1 0 1 0 0
I, I. Is I, 13 12 II 10
R,R.R s R,R 3 R,R,R o
'"c
.g
"2
1;;
"c
cD'"
'*
...
.S
.t:
(PC) <- (PC)+3
. (A) (direct address)
.IF
THEN
(PC) <- (PC)+relative offset
(A) < (direct address)
IF
THEN
(C) <- 1
ELSE
(C) +-- 0
(PC)
I-
Bytes Cycle
Mnemonic
.
c:
..cO JBC
u·-
bit, reI
. c tJ '
ca:::J '
'- '-
3
2
(PC) +- (PC)+3
(bit address) = 1
IF
THEN
(bit address) +- 0
(PC) +- (PC)+relative offset
1 fo
1
2
(A)
+-
((Rr)) EXTERNAL RAM
0 0 0 0
1
2
(A)
+-
((DPTR)) EXTERNAL RAM
0 0 0 1 0 0 0 0
b, b. bs b. b 3 b. b, bo
R,R.RsR4 R 3 R • R I R o
eDt;
.!:
~
Description
0, D. 05 D. 0 3 D. 0, D~
0 0
0 ..
MOVX A,@Rr
1
1 1 0
E'~
MOVXA,@DPTR
1
1
1 0
.....,Et;
-c:
x
MOVX@Rr,A
1
1
1
1 0
0
1 ro
1
2
(Rr)
MOVX@DPTR,A
1
1
1
1 0
0 0 0
1
2
((DPTP))
0
0 0 0 0 0 0 0
1
1
(PC)
E c:
-:::J
ca '-
w
..
c:
'- 0 NOP
Q)";:;
..cu
... :::J
0'-
t:
.!:
338
+-
+-
(A) EXTERNAL RAM
+-
(A) EXTERNAL RAM
(PC)+1
- - - - - - - - - - - - - - - - - - - . MSM80C154/83C154 •
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Supply voltage
Input voltage
Storage temperature
Symbol
Conditions
Rating
Unit
Vee
Ta = 25 DC
-0.5 -7
V
VI
Ta = 25 DC
-0.5 - Vee + 0.5
V
-55 - + 150
DC
Tstg
Operational Range
Symbol
Conditions
Rating
Unit
Supply voltage
Vee
*1 fosc = DC-16 MHz
2.5 - 6
V
Memory hold voltage
Vee
Parameter
Ambient temperature
Ta
2-6
V
-40-+85
DC
*1: 2.5 V .;; Vee < 4 V DC characteristics will be specified elsewhere.
16 MHz version of MSM83C154 (12 MHz < XTAL 1·2.;; 16 MHz) is being developed.
DC Characteristics
(VCC =5V±10%, Ta =-40to +85 D C)
Parameter
Symbol
Conditions
Min.
TVp.
Max.
Unit
Input Low Voltage
VIL
-0.5
0.2 VCC-O.1
V
Input High Voltage
VIH
Except XTALl and
RESET
0.2 VCC +0.9
VCC + 0.5
V
. Input High Voltage
VIHI
XT AL 1 and RESET'
0.7 VCC
VCC + 0.5
V
Output Low Voltage
(PORT 1,2,3)
VOL
IOL = 1.6mA
0.45
V
Output Low Voltage
(PORT 0, ALE, PSEN)
Vall
IOL =3.2 mA
0.45
V
Output High Voltage
(PORT 1, 2, 3)
VOH
IOH =-60jJA
VCC = 5 V ± 10%
2.4
V
IOH = -30/JA
0.75 VCC
V
Meas·
uring
circuit
1
Output High Voltage
(PORT 0, ALE, PSEN)
VOHI
IOH = -10jJA
0.9 VCC
V
IOH = -400jJA
VCC=5V± 10%
2.4
V
IOH=-150/JA
0.75 VCC
V
IOH= -40/JA
0.9 VCC
V
-10
Logical 0 Input Current
(PORT 1,2, 3)
IlL
VI=0.45V
Logical 1 to 0 Transition
Current (PORT 1,2,3)
ITL
Input Leakage Current
(PORT 0 floating, EA)
III
-200
jJA
VI=2.0V
-500
jJA
VSS addr·exp [6. & n]] [6. ASM]
GO [6. URAM/UROM] [6. FROMoaddr·exp]
[6. TILL 6. Port·exp = data·exp] [6. ASM]
STEP
STEP [6. URM/UROM] [6. FROM 6. addr·exp]
[6. COUNT 6.n][ 6.ASM]
@
@
VERIFY
VERIFY [6. H/O] 6. Pathname [6. EXT] [6. URAM/UROM] [address]
SAVE
SAVE [6. H/O] 6. Path name [6. URAM/UROM] [address]
6. ..... Space,
[...] ..... May be omitted,
o
I ..... Slash denoting "or".
353
e EASE40ee--------------------------------------------------DEBUGGER COMMAND SAMPLES
DB400
DB400 »
OLMS40 SERIES ON LINE DEBUGGER
VERS 1 . 3
*LOAD A:SAMPLl.HEX
*IB
« INITIAL BUFFER »
F E D C B A 9 8 7 6 5 4 3 2 1 0
0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3 : 0 0 0 0 0 0 0 0 0 0, 0 0 0 0 0 0
4 : 0 0 0 0 0 0 0 o ,0 0 0 0 0 0 0 0
5: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RW=O RX=O RY=O RZ=O XCH=O A=O
ACC=O CY=O DPH=O. D PL=O PP=O
PF=O PG=O
*GO URAM FROM 7A1 TILL PC=7CF &2
Y
Y/N/E ?
MODE: I B TO FB
PA=F PB=F PD=C PE=5
PC=07CF 74
PA=F PB=F PD=O PE=5
PC=07CF 74
*GO FROM 7Al TILL PF=9
Y/N/E ?
N
MODE: I B TO FB
MODE=NON TO FB
PA=F PB=F PD=F PE=F
PC=07CF 74
*FB
« FINAL BUFFER »
F E D C B A 9 8 7 6 5 4 3 2 1 0
0: 0 0 0 0 0 0 0 0 0 0 a a 0 0 0 0
1 : a a a a a 0 0 0 a a a a a 0 0 a
2: 0 a a 0 0 0 0 a a a a a 0 0 a a
3 : 0 a 0 a 0 a 0 0 0 0 0 a a a a a
4 : 0 0 a a a 0 0 a 0' 0 a a 0 a a a
5: 0 a 0 a a 0 0 a a a 0 0 a a a a
6: a a a a 0 0 0 a a 0 a a a a a a
7: 0 F * * 9 E 4 F a a 0 0 a 0 0 0
RW=F RX=4 RY=E RZ=9 XCH=* A=*
ACC=9 CY=l DPH=2 DPL=O PP=*
PA=F PB=F PD=F PE=F PF=9 PG=O
PK=B PH=2 CIN=O INT=l
*STEP FROM 7A1 COUNT 6
PA=F PB=F PD=C PE=O
PC=O 7 A l' 37,0 0
PA=F PB=F PD=C PE=O
PC=0700 AC
PA=F PB=F PD=C PE=O
PC=0702 AD
PA=F PB=F PD=C PE=O
PC=0704 65
PA=F PB=F PD=C PE;'O
PC=0705 26
PA=F PB=F PD=C PE=O
PC=0706 37A3
*EXIT
«
II
354
PF=O PG=O PK=B PI=A
PF=O PG=O PK=B PI=A
PF=9 PG=O PK=B PI=A
PF=9
PF=9
PF=9
PF=9
PF=9
PF=9
PG=O
PG=O
PG=O
PG=O
PG=O
PG=O
PK=B
PK=B
PK=B
PK=B
·PK=B
PK=B
PI=A
PI=A
PI=A
PI=A
PI=A
PI=A
---------------------------------------------------eEASE40e
SELECTION OF MICROCONTROLLER AND EVALUATION BOARDS/SOFTWARE
Evaluation board
Dedicated board
~--
--~
Serial interface type
,...-----,
MPB401
~~----,MS47
___ ~ L___~
Dedicated hardware
simulator
EVALUATION MICROCONTROLLERS
OLMS40
MSM5840
MPB400 board accessories
OLMS42
MSM5840
MPB400 board accessories
OLMS421 MSM5840
MPB421 board accessories
OLMS422 MSM5840
MPB422 board accessories
D
SOFTWARE
Serial interface type
FD40S·CP/M
Assembler/(serial)debugger CP/M single side single density 8-inch
Two (serial) monitor software EPROMs
FD40B·ISIS
Assembler/(bus) debugger ISIS-II single sided single density 8-inch
Two (bus) monitor software EPROMSs
PD40B·CP/M
Assembler/(bus) debugger CP/M single sided single density 8-inch
Two (bus) monitor software EPROMS
Bus interface type
355
e EASE40
e-----------------------------------------------------
MPB400 Board
The MPB400 board is used for OLMS-40 Series
microcontroiler program generation and evaluation.
With the MSM8085A used for control purposes,
several system configurations can be achieved in
combination with other boards and software.
Dimensions: 202 x 305 (mm)
MPB401 Board
The MPB401 board, used together with the MPB400
board, consists of interface circuit with the development
system and transfer speed converter unit.
Dimensions: 105 x 205 (mm)
80 x 115 (mm)
D
MPB202 Board
The MPB202 board is equipped with an evaluation
microcontroiler and 4K bytes of program EPROM
sockets. This miniature size board is used effectively
in mounting evaluations when built into application
equipment for final testing of debugged programs.
Dimensions: 95 x 120 (mm)
356
-----------------------------------------------------e. EASE40 •
MPB421
The MPB421 board has been designed for OLMS-421
microcontrolier program evaluation, and is used connected to the MPB400. This board is equipped with
LCD driver circuits and PLA EPROM sockets.
Dimensions; 145 x 180 (mm)
o
357
EASE6400 PROGRAM DEVELOPMENT SUPPORT SYSTEM
for the
OlMS-64 SERIES CMOS 4-Bit, 1-Chip Microcontroller
EASE6400 PROGRAM DEVELOPMENT SUPPORT
SYSTEM
The EASE6400 Program Development Support System has been specifically designed for·rapid and
efficient program development of Oki's OlMS-64 series of CMOS 4-bit, 1-chip microcontroller.
(Target chips: MSM6404, MSM6402, MSM6422, MSM6411, MSM6431, MSM6442 and MSM6408)
FEATURES
1. In-circuit emulation when connected to an
RS232C interface equipped a host computer
or to an input/output device such as a CRT
terminal and the EASE8 (option).
D
3. Six types of break conditions (for interruption
of emulation) including execution address
and machine cycle counter.
4. EPROM writer (for 2732,' 2732A, 2764) to
enable programming, transfer, and
verification of user program area contents.
5. User program debugging operations directed
by debug commands entered from the keyboard of the connected input/output device.
6. Program evaluation by use of dedicated evaluation chip (MSM6400E), theret;>y enabling
358
the same operations to be executed as when
the MSM6404 chip is used.
7. Built-in system diagnostic program.
HOST COMPUTER REQUIREMENTS
1. Operating system is one of the follows.
(1) CP/M®-80 (ver 2.0 or later)
memory capacity of the host computer
must be sufficient to run at least 52K
CP/M.
(2) MS-DOS® (ver 1.25, ver2.11)
(3) PC-DOS® (ver 1.25, ver2.11)
2. At least one RS232C communication port is
implemented.
3. Data transfer is performed through RS2:32C
communication port using BDOS function
call 6 on condition that console device is
assigned to TTY:.
- - - - - - - - - - - - - - - - - - - - - - - - - - . EASE6400 •
SYSTEM CONFIGURATION
The EASE6400 Program Development Support
System consists of the EASE6400 Emulator (a
high performance program emulator which
includes the EASE Host Monitor, the EASE6400
Evaluation, and the host computer) and the
ASM6404 Assembler. With the EASE6400
Evaluation connected online to the host
computer equipped with an RS232C interface,
the system covers all operations from assembly
of the source program through program
evaluation and debugging.
• 7 bits, 2 stop bits, even parity
• 7 bits, 2 stop bits, odd parity (switchable)
• EASE
• ASM6400
EASE6400
Evaluation Kit
COMMUNICATION WITH HOST
COMPUTER
ICs used
• Communication interface MSM82C51A
• Driver/receiver -SN75188N, SN75189N
Transmission format
• 110 to 9600 bps (switchable)
• 8 bits, 2 stop bits, non-parity
:8
I~I
o
Note: CPIM is a registered trademark ofDigital
Research Inc. (U.S.A.)
EASE and ASM6404 for PC-DOS, MS-DOS are
optional softwares.
D
359
• EASE6400 • - - - - - - - - - - - - - - - - - - - ' - - - - - - - - ' - -
ASM6400 ASSEMBLER
The ASM6400 is a floppy disk based high-performance assembler which operates on CP/M-80,
MS-DOS, or PC-DOS.
This assembler is used to translate source files generated on disk by using an editor (available on the
market), thereby generating object files (Intel HEX format), assemble list files, and cross-reference
list files in the specified devices.
FEATURES
1. Free descriptive format source files
2. Capacity to describe up to ten types of operators
in the source program operand column
3. Ability to specify the number of characters
per line and the number of lines per page in
assembly list files
4. Cross-reference list file generation capacity
5. 13 types of powerful pseudo-instructions available
6. Object codes where internal page jump instructions and all page jump instructions are assigned
automatically can be obtained by branch pseudoinstructions
7. Control of assembly list file outputs by LIST
or NLST pseudo-instruction
LIST OF PSEUDO-INSTRUCTIONS
Pseudoinstruction
TYP
Specifies a type of target chip
EQU
Assignment of operand value to name.
SET
Same as EQU pseudo-instruction, but
with redefinition capacity
ORG
Setting of program start address
END
Indication of end of program
B
Automatic conversion to internal page or
all page jump instruction after checking
branch destination
DB
8-bit data or ASCII character definition
DS
Reserves memory area for specified
number of bytes
NSE
360
FUnction
Setting of 0 in the 4 lower order bits of
the assembler location counter, and
addition of 16. The NOP instruction is
assigned to blank areas where no
machine language instruction has been
assigned.
DATE
Insertion of date in assemble list title
PAGE
Execution of assemble list page feed
TITL
Insertion of assemble list title
LIST
Designation of assemble list output
NLST
Inhibition of assemble list output
- - - - - - - - - - - - - - - - - - - - - - - - - . EASE6400 •
EASE6400 EMULATOR
Consisting of a host computer and the EASE6400 Program Evaluation Kit, the EASE6400 Emulator
supports a wide,range of development debugging operations efficiently and effectively. OLMS-64
application programs can be debugged without user application circuits just as easily as completed
systems.
a) User program execution
FEATURES
1. Real-time tracing function does not effect
execution time
The EASE6400 Evaluation Kit incorporates a
realtime trace area for 2048 machine cycles.
When the tracing for a particular user program
area address has been set, the address,
operation code, port, and probe status are traced
each time the specified address is executed.
2. Execution time measurement
The user program execution time can be measured by using the cycle counter on the
EASE6400 Evaluation Kit. (Max. 16,777,215 cycles)
This counter can also be used as a pass counter
to indicate the number of times a specified address is executed. And emulation can be
stopped after a specified address has been executed a specified number of times.
3. Mass storage
With an 8192-bytes of static RAM area in the
EASE6400 Evaluation Kit for use as a· user
program area, there is no problem with
inadequate memory area during debugging. And,
needless to say, user programs can be
loaded/saved from the host computer.
Furthermore, with an EPROM writer included on
this board, the user program area contents can
be written into EPROMs,and the EPROM
contents can be read out.
4. Ample break functions
The emulator can suspend (break) program execution by any of the following six break conditions.
a) Breakpoint break
Break upon execution of specified address. (Any
address may be specified.)
b) Extemal break
Break by application of external break signal.
c) Halt/stop instruction break
Break by execution of HALT or STOP instruction.
d) Trace buffer full break
Break when overflow of trace area occurs.
e) Cycle counter overflow break
Break when overflow of cycle counter occurs.
f) Probe match break
Break when probe data matches set data.
Input format:
STP number of instructions, start address
Input of this command results in the specified
number of instructions in the user program being
executed from the specified address (start
address).
Input format:
G start address, break address (n)
Input of this command results in the user program
being executed from the specified address (start
address). Emulation is subsequently stopped
when the specified address (break address) is
executed n times.
Note: Program execution is suspended temporarily each
time the specified address is executed.
Input format:
G start address, break address RAM
(address-n)
Input of this command results in the user program
being executed from the specified address (start
address). Emulation is subsequently stopped if
the contents of the specified RAM address are n
when the specified address (break address) is
executed. In this case, too, program execution is
suspended temporarily whenever the specified
address is executed.
b) Use of floppy disks
Input format:
LOD filename .
Input of this commartd enables the specified
file contents (user program) to be loaded into
theEASE6400 Evaluation Kit code memory
which serves as the OLMS-64 masked ROM
area.
Input format:
SAV filename start address, end address
Input of this command enables the contents of the
specified range of code memory to be saved at
the specified filename.
5. Extensive range of debugging commands
Input format:
DIAG2
In addition to display/updating of all register, port, and
RAM contents, the following commands enable
all debugging operations to be executed
efficiently,
Input of this command enables execution of commands within the specified file.
This execution can be suspended temporarily by
using the PAUSE command.
361
IJ
• EASE6400 • - - - - - - - - - - - - - - - - - - - - - - - -
c) Instruction executed bit memory
The EASE6400 Emulator includes an instruction
executed bit memory which indicates which user
program addresses have been executed. Program flow can be detennined by examination of
the contents of this memory.
6. Easy to remember command format
TheEASE6400Emuiator debugging commands. consist of command mnemonicS followed by parameters
(address or mnemonic).
Command mnemonic configuration
a) First character
Denotes the function to be executed by the
emulator.
b) Second and following characters
Name of function to be executed by the
emulator- that is, MSM6400E evaluation
chip or EASE6400 Evaluation Kit register,
memory, or port name (abbreviation).
362
Example:
*0
OM O,1F..J
II \J I V I
ab
cdef
a: denotes wait for command input from emulator
b: denotes display of contents of specified object
c: data memory (equivalent MSM6400E RAM area)
designation
.
d: start address of contents to be displayed
e: end address of contents to be displayed
f: carriage return denoting end of command input
- - - - - - - - - - - - - - - - - - - - - - - - - . EASE6400 •
EASE6400 EMULATOR MEMORY CONFIGURATION
The EASE6400 emulator memory area,which can be used by the user, is outlined in the following diagram. The
sections enclosed in boxes represent the register and memory areas which can be accessed from the host
computer keyboard, and which can be displayed/updated by debugging command.
CM
CODE
MEMORY
PROGRAM
COUNTER
ACCUMULATOR
PORT 9
U
c:=J
~
CARRY
PORTA
~
c::=J
13
STACK
POINTER
c:=J
D
8192x8
HL
REGISTER
DM
DATA
MEMORY
PORTO
I
FLAG
REGISTER
I
41
I
41
I
41
PORT 6
D
U
r==J D
PROBE
COMPARE
REGISTER
PROBE
MASK
EXECUTION
MODE
REGISTER
~
~
BP
TR
IE
SO
CE
T
8192 8192 8192 8192
x1
x1
x1
x1
t
8192
x1
L
4]
PORT 3
I
41
MEMORY
2048x66
41
r=J
BREAK
STATUS
REGISTER
I
D
41
P3
PORT 8
BREAK
CONTROL
REGISTER
II
BS
61
FB
IB
FINAL
BUFFER
INITIAL
BUFFER
139x8
210x8
CYCLE COUNTER ENABLE BIT MEMORY
SYNC OUTPUT BIT MEMORY
INSTRUCTION EXECUTED BIT MEMORY
TRACE ENABLE BIT MEMORY
BREAKPOINT BIT MEMORY
CYCLE COUNTER
IRQ
PORT?
M
TRACE
I
P2
PORT 5
EM
PORTD
PORT 2
PORT 4
I
41
~
FR
P1
ElF
PORTB
PORT 1
PO
PORTC
I
TRACE POINTER
BLK
BLOCK
MEMORY
TP
8192x1
363
eEASE6400e-------------------------------------------------
MAJOR MEMORY OPERATIONS
1. Code memory
6. Sync ouput bit memory
The code memory is an 8192 x 8-bit RAM area
which corresponds to the OlMS-64 masked
ROM area where user programs are stored.
(The MSM6404 ROM capacity is 4000 bytes)
The sync output bit memory IS another 8192 x 1-bit
RAM area which has addresses identical to the code
memory. When the code memory contents are executed, the corresponding bits in the sync output
memory are checked, and if a "1" bit is found, an output sync signal (active lOW) is passed to the probe
terminal.
2. Data memory
The data memory is a 256 x 4-bit RAM area corresponding to the MSM6400E RAM area.
3. Instruction executed bit memory
This memory is an 8192 x 1-bit RAM area which has
addresses identical to the code memory. When a
code memory program is executed, the bits corresponding to the excuted addresses are set to "1". The
program flow can thus be determined by checking the
contents of this memory.
The cycle counter enable bit memory is also another
8192 x 1-bit RAM area which has addresses identical to the code memory. When the code memory
contents are executed, the corresponding bits in the
cycle counter enable bit memory are checked,
and if a "1" bit is found, the cycle counter is
counted up in step with that machine cycle.
4. Break point bit memory
S. Probe comparison register/probe mask
The break point bit memory is also an 8192 x 1-bit
RAM area which has addresses identical to the code
memory. If a particular bit in this memory is "1", program execution is suspended immediately after the
code memory contents corresponding to that bit are
executed.
5. Trace enable bit memory
D
7. Cycle counter enable bit
The trace enable bit memory is another 8192 x 1-bit
RAM area which has addresses identical to the code
memory. If a particular bit in this memory is "1", port!
register contents, etc., are stored in the trace
memory when the code memory contents
corresponding to that bit are executed.
364
The conditions for generating a break by input data
from the probe (probe match break) can be changed
by altering these two settings.
9. Initlallflnal buffers
These two memories are 210 x 8-bit RAM areas
used to store the initialized settings of the MSM6400E
evaluation chip or the MSM6400E status immediately
after a break when real-time emulation is executed.
10. Trace memory
The trace memory is a 2048 x 56-bit RAM area used
to store traced data.
The trace instruction is given by the trace enable bit.
---------------------------------------------------eEASE6400e
LIST OF DEBUGGING COMMANDS
Load, save, and Verify Commands
LOD [dr ;] filename ~
SAV [dr ;] filename [address, address] ~
VER [dr ; ] filename [address, address] ~
Load programs into code memory
Save code memory program
Verify file with code memory
EPROM Commands
PPR address, address [, address] ~
TPR address, address [, address] ~
VPR address, address [, address] ~
Commands Used
PC
SP
AC
Program Code Memory into EPROM
Transfer EPROM into Code Memory
Verify EPROM with Code Memory
to Display/Change Internal Status of Evac:hip
DPC
CPC address ~
Display Program Counter
Change Program Counter
DSP~
Display Stack Pointer
Change Stack Pointer
CSP data~
DAC~
DisplayAoc
ChangeAcc
CACdata~
DCY~
CCYdata~
Display Carry Flag
Change Carry Flag
HL
DHL~
CHLdata~
Display H-L Registers
Change H-L Registers
FR
DFR~
CFRdata~
Display Flag Register
Change Flag Register
PO-P8
DPn~
CPndata~
CY
(n = 0, 1, 2, 3, ... 8)
(n = 0, 1, 2, 3, ... 8)
DcMR~
Display Port n
Change Port n
Display Counter Mode Register
Change Counter-Mode Register
(port 9)
CCMRdata~
PA
DSMR~
CSMRdata~
Display Shift Mode Register
Change Shift Mode Register
(portA)
PB
DCFR
* Change CFR command is not permitted
Display Control Flag Register
(port B)
PC
DEIF ~
CEIFdata
Display Enable Interrupt Flag
Change Enable Interrupt Flag
(port C)
Display Interr:upt Request Flag
(port D)
P9
PD
MEl
~
DIRQ
II
* Change IRQ command is not permitted
DMEI~
CMEldata~
Display Master Enable Interrupt Flag
Change Master Enable Interrupt Flag
D~
Display all internal status
~
Data & Code Memory Display, Change, and Fill Commands
DM
DDM address [, address] ~
CDM address.-'
data data...
FDM address, address, data ~
CM
DCM address [, address] ~
CCM address ~
datadata... ~
FCF address, address, data ~
~
Display Data Memory
Change Data Memory
Fill Data Memory
Display Code Memory
Change Code Memory
Fill Code Memory
365
.EASE6400·----------------~-------------------------------
Attribute Memory Display, Enable, and Reset Commands
BP
DBP address [, address)';
EBP address [, address).;
RSP address [, address).;
Display Break Point Bits Memory
Enable Bteak Point Memory
Reset Break Point Bits Memory
TR
DTR address [, address)';
ETR address [, address)';
RTR address [, address)';
Display Trace Enable Bits Memory
Enable Trace Enable Bits Memory
Reset Trace Enable'Bits Memory
IE
DIE address [, address)';
RIE address [, address)';
Display Instruction Executed Bits Memory
Reset Instruction Executed Bits Memory
CE
DCE address [, address)';
ECE adaress [, address)';
RCE address [, address) .J
Display Cycle Counter Enable Bits Memory
Enable Cycle Counter Enable Bits Memory
Reset Cycle Counter Enable Bits Memory
SO
DSO address [, address) .;
ESO address [, address).;
RSO address [, address)';
Display Sync Out Enable Bits Memory
Enable Sync Out Enable Bits Memory
Reset Sync Out Enable Bits Memory
Trace Memory Display Commands
TM
DTM
DTl
Display Trace Memory
Display Trace List
Other Hardware Display and Change Commands
DCC';
CCC number .;
Display Cycle Counter
Change Cycle Counter
DBC';
SBC [[±) mnemonic, ... )
Display Break Condition Register
Set Break Condition Register
mnemonic means one of following key words
here.
BB ........ Break at Break Point
XB ........ External Break
CO ........ Cycle Counter Over Flow
TF ......... Trace Memory Full
PM ........ Probe Match
HS ........ HALT/STOP Instruction Executed
BS
DBS';
Display Break Status Register
PM
DPM';
CPMdata';
Display Probe Mask Register
Change Probe Mask Register
CR
DCR';
CCRdata';
Display Probe Compare Register
Change Probe Compare Register
DEM
CEM mode-ref .;
Display Execution Mode Register
Change Execution Mode Register
moc;te-ref means one of following keywords
here.
'
IF .......... IB
TOFB
IN ......... IB
TO NON
NN ........ NON TO NON
NF ........ NONTOFB
FF ......... FB TOFB
DBl address [, address) .;
SPB address [, address)';
SDB address [, address)';
Display Block Memory
Set Block Memory into Program Block
Set Block Memory into Data Block
BANK 1 or2
Set Attribute Memory Bank Register
CC
I)
BC
EM
BlK
BANK
366
J
-------------------------------------------------eEASE6400e
Initial Buffer & Final Buffer
DIB,)
DFB,)
CI key-word data ,)
IB
FB
CIDM address,) data data... ,)
CF key-word data ,)
CFDM address
data data... ,)
FIDM address, address, data').
FFDM address, address, data ,)
Display Initial Buffer
Display Final Buffer
Change elements of Initial Buffer
key-word ... AC, HL, FA, SMR, CMR, MEl,
ElF, CY, Pn (n=O, 1,3,4, ... ,8)
Change Initial Buffer Data Memory
Change elements of Final Buffer
key-word ... AC, HL, FR, SMR, CMR, MEl,
ElF, CY, Pn (n=O, 1, 3, 4, ... ,8)
Change Final Buffer Data Memory
Fillnitial Buffer Data Memory
Fill Final Buffer Data Memory
Assemble & Disassemble Commands
ASM address ,) mnemonic... ,)
DASM address [, address],)
Assemble to Code Memory
Disassemble to Console
Emulation Commands
G [start-address] [, break-parameter, ...... ],)
GD [start-address] [, break-parameter, ......],)
STP [number] [, address],)
Go (Start Real Time Emulation)
Go Direct (Start Real Time Emulation)
break-parameter format is shown below
1) address
2) asddress (n)
3) addres (n) & address (m)
4) addres RAM (address - data)
1 < n, m < 65535
Start Step Execution
Other Commands
@ [-n],)
HELP,)
EXIT ,)
RES')
RESE,)
SIO H or F ,)
DEV,)
ST mnemonic ,)
FDD [dr ... drl ,)
DIR [dr:l,)
(n = 1, 2, ..... , 9) Command - Repeat
Display Help File (EASE 64, HLP
Exit to CP/M
Reset EASE 6400 system
Reset Eva - chip (MSM 6400E)
Set 1/0 Mode
CH2 port Output Control
Family Set
Flopy Disk Unit Set
Display file directory
o
367
EASE6502 PROGRAM DEVELOPMENT SUPPORT SYSTEM
for the
MSM6502 CMOS 4-Bit, 1-Chip Microcontroller
EASE6502 PROGRAM DEVELOPMENT SUPPORT SYSTEM
The EASE6502 Program Development Support System has been specifically designed for rapid and efficient
program development of Oki's MSM6502 CMOS 4-bit, 1-chip microcontroller.
FEATURES
II
1. Connecting the MPB6502 Evaluation Board
to a host computer or to an I/O terminal such
as a CRT terminal includes an RS232C
interface circuit. All debugging operations
can be entered from the console keyboard.
2. Executes user programs with the trace in real
time or in single step mode.
3. Mass storage user program area (4K bytes).
4. Six types of break conditions, including
execution address and machine cycle
counter.
5. EPROM programmer (for 2716, 2732, 2732A) to
enable programming, transfer, and verifing with
user program area contents.
6. The same operation as the MSM6502,
because OKi designed the original evaluation
chip (MSM6502E).
7. Built-in system diagnostic program.
SYSTEM CONFIGURATION
The EASE6502 Program Development Support
System consists of the EASE6502 Emulator (a
high performance program emulator which
includes the EASE65 Host Monitor, the
MPB6502 Evaluation Board, and the host
computer) and the ASM6502 Assembler. With
the MPB6502 Evaluation Board connected
online to the host computer equipped with an
RS232C interface, the system covers all
operations from assembly of the source program
. through to program evaluation and debugging.
User's application
circuit
•
•
EASE65
ASM6502
HOST COMPUTER REQUIREMENTS
1. Operating system is one of the follows.
(1) CP/M®-80 (ver 2.0 or later)
memory capacity of the host computer
must be sufficient to run at least 52K
CP/M.
(2) MS-DOS'" (ver 1.25, ver2.11)
(3) PC-DOS® (ver 1.25, ver2.11)
2. At least one RS232C communication port is
implemented.
3. Data transfer is performed through RS232C
communication port using BOOS function
call 6 on condition that console device is
assigned to TTY:.
COMMUNICATION WITH HOST
COMPUTER
ICs used
• Communication interface MSM82C51A
• Driver/receiver SN75188N, SN75189N
Transmission format
• 110 to 9600 bps (selectable)
• 8 bits, 2 stop bits, non-parity
7 tilts, 2 stop bits, even parity
7 bits, 2 stop bits, odd parity (selectable)
368
MPB6502
Evaluation Board
:8
IC§JI
+5V +12V -12V
~
(4.5A) (O.2A) (O.2A)
Note: CP/M is the registered trademark of Digital Research
Inc. (U.S.A.)
EASE65 and ASM6502 for MS-DOS, PC-DOS
are optional softwares.
-------------------------------------------------..EASE6502.
ASM6502 ASSEMBLER
The ASM6502 is a floppy disk based high-performance assembler.
This assembler is used to translate source files generated on disk by using an editor (available on the
market), thereby generating object files (Intel HEX format), assembly list files, and cross-reference
list files on the specified devices.
FEATURES
LIST OF PSEUDO-INSTRUCTIONS
1. Free descriptive format source files
2. Capacity to describe up to ten types of arithmetic
in the source program operand field
3. Ability to specify the number of characters per line
and the number of lines per page in assembly
list files
4. Cross-reference list file generation capacity
5. 13 types of powerful pseudo-instructions available
6. Object codes where all page jump instructions and
inter-page jump instructions are assigned
automatically can be obtained by branch pseudoinstructions
7. Control of assemble list file outputs by LIST or
NLST pseudo-instruction
Pseudoinstruction
Function
EQU
Assign the operand value to the name.
SET
Same as EQU pseudo-instruction, but
with redefinition capacity
ORG
Define assembler location counter.
END
Terminte assembly
B
Automatic conversion to aU-page or
inter-page jump instruction after checking branch destination
DB
8-bit data or ASCII character string
definition
DS
Reserve n bytes area of uninitialized
storage
NSE
Setting of 0 in the 4 lower order bits of
the assembler location counter, and
addition of 16. The NOP instruction is
asSigned to blank areas where no
machine language instruction has been
assigned.
DATE
Insertion of date in assemble list title
PAGE
Execute page eject
TITL
Insert assemble list title
LIST
Turn on assemble list output
NLST
Tum off assemble list output
369
D
• EASE6502 .--------------------------------~-------------
EASE6502 EMULATOR
Consisting of a host computer and the MPB650~ Program .Evaluat~o~ Board, the EAS.E6502 Emulator
supports a wide range of development debugging opera~lon~ effl?le~tly .and effectl.vely. MSM6502
application programs can be debugged without user application circuits Just as easily as completed
systems.
FEATURES
1. Real-time tracing' ~unction does not effect
execution time
The MPB6502 Evaluation Board incorporates a realtime trace area for 2048 machine cycles. When tracing for a particular user program area address has
been set, the port, HL register, and MEl flag status
are traced each time the specified address is executed.
2. Execution time measurement
The user program execution time can be measured
by using the cycle counter on the MPB6502 Evaluation Board. (Max. 16,777,215 cycles)
This counter can also be used as a pass counter
to indicate the number of times a specified
address is executed. Emulation can be stopped
after a specified address has been executed a
specified number of times.
D
3. Mass storage user program area
With a 4096-byte static FjAM area in the
MPB6502 Evaluation Board for use as a user
program area, there is no problem with
inadequate memory area during debugging. And,
needless to say, user programs can be
loaded/saved from the host computer.
Furthermore, with an EPROM programmer
included on this board, the user program area
contents can be written into EPROMs, and the
EPROM contents can be read out.
4. Ample break functions
The emulator can suspend (break) program execution by any of the following six brteak conditions.
a) Breakpoint break
Break upon execution of specified address. (Any
address may be specified.)
b) Extemal break
Break by application of extemal break signal.
c) Halt instruction break
.
Break by execution of HALT instruction.
d) Trace buffer full break
Break when overflow of trace area occurs.
e) Cycle counter overflow break
Break when overflow of cycle counter occurs.
t) Probe match break
Break when probe data matches set data.
370
5. Extensive range of debugging commands
In addition to display/updating of all register, port, and
RAM contents, the following commands enable all
debugging operations to be executed efficiently.
a) User program execution
Input format:
STP number of
instructions~
start address
Input of this command results in the specified
number of instructions in the user program being
executed from the specified address (start
address).
And if the terminal to be used to display the contents has been specified by SDF command at this
time, the display can be put into an easy to read
format.
Input format:
G start address, break address (n)
Input of this command results in the user program
being executed from the specified address (start
address). Emulation is subsequently stopped
when the specified address (break address) is
executed n times.
Note: Program execution is suspended temporarily each
time the specified address is executed.
Input format:
G start address, break address RAM
(address-n)
Input of this command'results in the user prog"~m
being executed from the specified address (sta~.
address). Emulation is subsequently stopped if
the contents of the specified RAM address are n
when the specified address (break address) is
executed. In this case, too, program execution is
suspended temporarily whenever the specified
address is executed.
________________________________________________-4. EASE6502 •
b) Use of floppy disks
Input format:
LaD filename
Input of this command enables the specified file
contents (user program) to be loaded into the
MPB6502 Evaluation Board code memory which
serves as the MSM6502 masked ROM area.
Input format:
SAY filename start address, end address
Input of this command enables the contents of the
specified range of code memory to be saved at
the specified filename.
Example:
*DDM
II
ab
\j
c
0,
1F
.J
I eV If
d
a: denotes wait for command input from emulator
b: denotes display of contents of specified registter /
memory/board
c: data memory (equivalent MSM6502 RAM area)
designation
d: start address of contents to be displayed
e: end address of contents to be displayed
f: carriage retum denoting end of command input
Input format:
DIAG filename
Input of this command enables execution of commands within the specified file automatically.
This execution can be suspended temporarily by
using the PAUSE command.
Input format:
LIST filename
NLiST
If the list command is entered, the emulator creat
the CP/M file and write into it the any characters
which are output to the console till entering the
NLST command.
o
c) Instruction executed bit memory
The
EASE6502
Emulator
includes
an
instruction executed bit memory which indicates
which user program addresses have been executed. Program flow can be known by examination of the contents of this memory.
6. Easy to remember command format
The MPB6502 Emulator debugging commands consist of command mnemonics followed by parameters
(address or mnemonic).
Command mnemonic configuration
a) First character
Stand for the emulator function (display/update)
b) Second and follOWing characters
Represent one of the MPB6502 Evaluation Board
or the MSM6502E evaluation chip element (register, memory or port name).
371
.EASE6502, ••--------------------------------------~--~-----
EASE6502EMULATOR MEMORY CONFIGURATION
The EASE6502 emulator memory area which can be used by the user is outlined in the following diagram. The
sections enclosed in boxes represent the register and memory areas which can be accessed from the host
computer keyboard, and which can be displayed/updated by debugging command.
INSTRUCTION EXECUTED BIT MEMORY
TRACE ENABLE BIT MEMORY
CYCLE COUNTER ENABLE BIT MEMORY
BREAKPOINT BIT MEMORY
VM
CM
VERIFY
MEMORY
CODE
MEMORY
TM
4096x8
BTl
PRE
S C
0 E
2048x66
4096x8
4096x5
DM
SG
DATA
MEMORY
SEGMENT
DATA
MEMORY
128x4
D
Hl
ACCUMULATOR
~
~
PORTO
PORT 1
E]
~
E]
CARRY
MEl FLAG
INDEX
REGISTER
PROBE
COMPARE
REGISTER
E]
IB
INITIAL
BUFFER
139x8
~
I
TP
Icc
REGISTER
STACK
POINTER
INSTRUCTION
DATA
U
E]
E]
PORT 2
PORT 4
PORT 3
EJ EJ
EMULATION
MODE
EJ EJ
PROBE
MASK
TRACE POINTER
EJ
EXTERNAL
PROBE
BREAK
CONTROL
REGISTER
BREAK
STATUS
REGISTER
E]
E]
.~
FB
FINAL
BUFFER
139x8
111
CYCLE COUNTER
208x8
PROGRAM
COUNTER
~
TRACE MEMORY
BlK
BLOCK
MEMORY
4096 x 1
PORT 5
~
241
---------------------------------------------------4. EASE6502 •
MAJOR MEMORY OPERATIONS
1. Code memory
The code memory is an 4096 x 8·bit RAM area
which corresponds to the MSM6502 masked ROM
area where user programs are stored.
(The MSM6502 ROM capacity is 2000 bytes)
2. Data memory
The data memory is a 128 x 4-bit RAM area corresponding to the MSM6502 masked RAM area.
3. Verify memory
The verify memory is a RAM area with addresses
identical to the code memory. When a user program
is loaded into the code memory identical contents are
also set in this memory.
Comparrison of this memory with the code memory
enables the operator to determine what sections of
the user program have been changed after loading.
4. Instruction executed bit memory
This memory is an 4096 x 1-bit RAM area which has
addresses identical to the code memory. When a
code memory program is executed, the bits corresponding to the executed addresses are set to "1".
The program flow can thus be known by checking the
contents of this memory.
9. Probe comparl register/probe mask
The conditions for generating break by input data
from the probe (probe match break) can be changed
by altering these two settings.
10. Segment data memory
The segment data memory is a 208 x 8-bit RAM
area with coordinates 0 thru 7 on the vertical axis and
A thru Z on the horizontal axis. This memory is used
to display the status of each bit of the MSM6502 RAM
liquid crystal display area at the specified coordinate
and by the specified character.
Displaying the status of this memory provides an
image of the liquid crystal display status.
11. Initial/final buffers
These two memories are 139 x 8-bit RAM areas
used to store the initialized settings of the MSM6502E
evaluation chip or the MSM6502E status immediately
after a break when real-time emulation is executed.
12. Trace memory
The trace memory is a 2048 x 66-bit RAM area used
to store traced data.
The trace instruction is given by the trace enable bit.
5. Break point bit memory
The break point bit memory is also an 4096 x 1-bit
RAM area which has addresses identical to the code
memory. If a particular bit in this memory is "1", program execution is suspended immediately after the
code memory contents corresponding to that bit are
executed.
o
6. Trace enable bit memory
The trace enable bit memory is another 4096 1-bit
RAM area which has addresses identical to the code
memory. If a particular bit in this memory is "1", port/
register contents, etc., are stored in the trace
memory when the code memory contents corresponding to that bit are executed.
x
7. Sync ouput bit memory
The sync output bit memory is another 4096 x 1-bit
RAM area which has addresses identical to the code
memory. When the code memory contents are executed, the corresponding bits in the sync output
memory are checked, and if a "1" bit is found, an output sync signal (active LOW) is passed to the probe
terminal.
8. Cycle counter enable bit
The cycle counter enable bit memory is also another
4096 x 1-bit RAM area which has addresses identical to the code memory. When the code memory
contents are executed, the corresponding bits in the
cycle counter enable bit memory are checked, and if
a "1" bit is found, the cycle counter is counted up in
step with that machine cycle.
373
• EASE6502 .-------------------------------------------------
DEBUGGING COMMAND TABLE
Load, Save, and Verify Commands
1. LOD [dr:] filename
2.
3.
4.
5.
6.
SAV [dr:] filename [address, address]
VER· [dr:] filename [adress, address]
LSG [dr:] filename [address, address]
SSG [dr:] filename
VCM address [, address]
Load Program into Code Memory
Save Code Memory Program
Verifty File with Code Memory
Load Segment data
Save Segment data
Verify Code Memory with Verify Memory
EPROM Commands
1. PPR address, address [, address]
2. TPR address, address
3. VPR address, address [, address]
Program Code Memory into EPROM
Transfer EPROM into Code Memory
Verify EPROM with Code Memory
Display Commands
o
1. 0
2.DAC
3.DHL
4.DCY
5. DSP
6. OLD
7. DEI
8. DPn
9. DPC
10. DCC
11. DCR
12. DPM
13. DBC
14. DBS
15. DEM
16. DIB
17. DFB
18. DSG
19. DBP address [, address]
20. DCE address [, address]
21. DSO address [, address]
22. DIE address [, address]
23. DTR address [, address]
24. DDM address [, address]
25. DCM address [, address]
26. DVM address [, address]
27. DTM tp-address, line-number
28. DTL -number, line-number
All Register, Flag, Port
Acc Register
HL Register
Carry Flag
Stack Pointer
LCD Driver ON/OFF status (Port 4-0 bit)
Enable Interupt Flag (MEl, TBC EI, ext. INT EI)
Port N (n=O, 1, 2, 3, 4)
Program Counter
Cycle Counter
Probe Compare Register
Probe Mask Register
Break Condition
Break Status
Emulation Mode
Initial buffer & Final buffer
Final buffer & In~ial buffer
Segment Data Status
Break Point Bit Memory
Cycle Counter Enable Bit Memory
Sync Output Enable Bit Memory
Instruction Executed B~ Memory
Trace Enable Bit Memory
Data Memory (M6502E Internal RAM)
Code Memory
Verify Memory
Trace Memory
Trace List
Change Commands
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
374
CAC data
CHL data
CCY Oorl
CSP data
CLD Oorl
CEI [data]
CIR data
CPn data
CPC address
CCC (+ or -) data
CCR data
CPM data
CBZ Oorl
CEM mode
CI key-word data
CF key-word data
CSG
CCM address
COm address
BANK 0 or 1
Acc Register
HL Register
Carry Flag"
Stack Pointer
LCD Driver ON/OFF Status
Enable Interrupt Flag
Index Register
Port n (n=O, 1,3,4,5)
Program Counter
Cycle Counter
probe Compare Register
Probe Mask Register
Buzzer Output Select Hard or Soft
Emulation Mode
*mode*
to FB
IF
IB
IN
IB
to NON
NN
NON to NON
NF
NON to FB
FN
FB to NON
Initial Buffer
Final Buffer
Segment data
CooeMemory
Data Memory (M6502E Internal RAM)
Attribute Memory Bank
--------------------------------------~----------_e. EASE6502 •
Enable Commands
1.
2.
3.
4.
EBP
ECE
ESO
ETR
address
address
address
address
I. address]
I. address]
I. address]
I. address]
Break Point Bit Memory
Cycle Counter Enable Bit Memory
Sync Output Enable Bit Memory
Trace Enable Bit Memory
I. address]
I. address]
[. address]
I. address]
I. address]
Break Point Bit Memo~
Cycle Counter Enable it Memory
Instruction Executed Bit Memory
Sync Output Enable Bit
Trace Enable Memory
M6502E Eva-chip
MPB6502 Board
Reset Commands
1.
2.
3.
4.
5.
6.
7.
RBP
RCE
RIE
RSO
RTR
RES
RES
address
address
address
address
address
E
Fill Commands
1.
2.
3.
4.
FCM
FDM
FIDM
FFDM
address. address. data
address. address. data
address. address. data
address. address. data
Code Memory
Data Memory
Initial Data Memory
Final Data Memory
Emulation Commands
1st-address] I. break-parameter. ___ oj
Begin Emulation
1st-address] I. break-parameter. ___ oj
Begin Emulation
If the optional st-address is given. emulator will begin emulation from st-address. And if optional breakparameter is given. emulation will break on the first break-parameter to be satisfied.
Break-parameter = break-address
= break-address (pass count)
= break-address (pass count) & break-address (pass count)
= break-address RAM (RAM address-data)
3. STP
Single Step
Inumber] I. st-address]
1. G
2. GO
Other Commands
1. ASM
2.DASM
3. LIST
4. NLST
5. DBLK
6. SPB
7. SOB
8. SIO
9. EXIT
10. PAUSE
11. DIAGI
12. DIAG
13. @ I-n]
14. HELP
15. SBC
address
address I. address]
Idr :] filename
Assemble to Code Memory
Disassemble to Console
List Console Output into Disk File
End listing
Display Block Memory
address I. address]
address I. address]
Set Program Block
Set DB Block
addres I. address]
ForH
Set Emulator to 110 terminal mode
Return to CP/M
Stop Command File Execution
Start Sell Check P~ram
Idr:] filename
Execute Command ile
Repeat Command
Display HELP File
(+ or -) mnemonic I. (+ or -) mnemonic. __ oj
Set/Reset Break Condition Register
* mnemonic*
BB
Break when Break Point Reached
XB
External Break
Break on Cycle Counter Overflow
CO
TF
Break when Trace Buffer Full
PM
Break on Probe Match
HT
Break on HALT Instruction
16. SDF
(+ or -) mnemonic I. (+ or -) mnemonic. __ oj
Set/Reset Dump Format
1. DEL
Delete the last character entered
2. CntrllC
Return to CP/M
3. CntrI/P
Copy all subsequent console output to the currently assigned list device
4. Cntrl/Q
Continue normal dispaly
5. CntrllS
Stop display
6. CntrllR
Echoe current input line
7. ESC
Abort any command inprogress
8. @ I-n]
Repeat the command
Note: The MSM6502 RAM area corresponds to the EASE6502 Emulator data memory. and the-mask ROM corresponds to
the code memory.
.
375
o
• EASE6502 .---------------------------------------------------
SAMPLES
A>EASE65
«
EAS£65
Sep.3.1983
Now,
»
OKI
PI" eli mIn a r y
electric
start up
It 1 .0
ind.co.,ltd
MPB6502 board.
HARD WARE
SELF CHECK
[ NORMAL EN~ ]
«
MPB6502
EMULATOR
PRELIMINARY
COPYRIGHT OK!
ELECTRIC
1t1.5
IND.
CO.,
»
LTD.
1984
ACTIVE BREAK CONDITION ---> BREAK POINT BREAK
HALT INSTRUCTION BREAK
** NOW DEVICE NO.
[ KEY
= A,B
**
IN OTHER DEVICE NO. ]
~EVICE
NO."A:B:]
[PRESENTE~
o
'" DIAG INrTl
INITIALIZATION
* ;
START
'" FeM '"
*
LSG
PIC.DAT
SGRAM SET-UP COMPLETED
* LDO RAMSEr
LOAD COMPLETED
NEXT ADDRESS=OOZO
'" LIST CRT.Lsr
'" ; NOW INITIALIZATION END
AND
LIST START
DIAG COMHAND END
*
GDO, 1 F
EXECUTION
BAN K :
1
(RESET
TRACE
MO~E
NON
TO
NON
POINTER)
EMULATION GO "'*
PARAMETER=OOlF(
0)
A~~RESS
BREAK
[BREAK PC"01F
NEXT PC"O;OJ
[NEXT TRACE POINTER"17]
'" DDM 0,3
LOC"03-00
5 5 5 2
'"
D TM
4,3
LOC"012 82
LO C = 0 13
*
B4
l 0 C = 014 11
DIE 0,.2 0
LAI
LMA
IN L
PORT (0-2) =FFO Hl"'OO CY=O MEI;;O
PORT 10-2) =FFO HL=OO Cyo 0 MEI"O
PORT(0-2) =FFO Hl=OO CY=O MEl = 0
XP=FF
XP" FF
XP=FF
1100 0000 0000 0000
1 111 1111 1111 1101
lOC"'OOO
lO(:=020
o
* DAS M 0,13
lOC=OOO 5F
~ I
JCP
010
lOC"OOI ~O
DB
00 00 00 00 00 00 00 00
00 00 00 00 00 00
LOC"002
lOC=010 SAOO
L HL I 00
lOC"'012 82
LAI
LOC"'013 B4
L MA
* NLST
* EXIT
A'
376
TP"'4
TP=5
TP",
---------------------------------------------------. EASE6502 •
EASE6502 PROGRAM DEVELOPMENT SUPPORT SYSTEM
for the MSM6502 CMOS 4-BIT 1-CHIP MICROCONTROLLER
Category
Hardware
Software
Manual
Model
MPB6502
EASE65
Floppy disk based host monitor*
ASM6502
Floppy disk assembler*
TM-6502
EASE6502 Development Support System - User's Manual
TCU-6502
TCS-1
Accessories
Title
4-bit 1-chip microcontroller evaluation board
User application circuit connection cables
Host CP/M@ computer connecting cables (for if800 model 10/20/30)
TCP-1
Power supply cables (+5V, 4.5A) (+12V, 0.2A) (-12V, 0.2A)
TCX-1
External probe cables
TCC-1
Board connecting cables
• Available under following operating system
• CP/M-80 (ver 2.0 or later)
• MS-DOS (ver 1.25, ver 2.11)
• PC-DOS (ver 1 .25, ver 2.11)
OPTIONS
Option name
MPB6502 EVA
Board
Remarks
A simplified evaluation board consisting of the MSM6502E plus EPROM sockets,
and designed for the MSM6502. Programs are evaluated by inserting the EPROM
where the user program is stored into an EPROM socket.
Dimensions: 160 x 127 (mm)
D
377
EASE 80C49 PROGRAM DEVELOPMENT SUPPORT SYSTEM
for
MSM80C48RS/MSM80C49RS/MSM80C50RS CMOS 8-Bit Microcontrollers
EASE80C49 PROGRAM DEVELOPMENT SUPPORT
SYSTEM
The EASE80C49 Program Developinent Support System has been specifically designed for rapid and
efficient program development of Oki's MSM80C48RS, MSM80C49RS and MSM80C50RS CMOS
8-bit, 1-chipmicrocontrollers.
D
FEATURES
SYSTEM CONFIGURATION
1. In-circuit emulation when connected to an RS232C
interface equipment host computer or to an
input/output device such as a CRT terminal.
2. 4K byte user program area available for code
transfer to/from floppy disk, collation/updating of
area contents, and continuous/step execution.
3. Eight types of break conditions (for interruption
of emulation) including execution address and
machine cycle counter.
4. EPROM programmer (for 2716, 2732, 2732A) to
enable writing, transfer, and comparison of user
program area contents.
5. User program debugging operations directed by
debug commands entered from the keyboard of
the connected input/output device.
6. Built-in system diagnostic program.
The EASE80C49 Program Development Support
System consists of the EASE80C49 Emulator (a high
performance program emulator which includes the
EASE49 Host Monitor, the MPB800 Evaluation
Board, and the host computer) and the ASM-49
Assembler.
With the MPB800 Evaluation Board connected
online to the host CP/M computer (such as an
if800) equippped with an RS232C interface, the
system covers all operations from assembly of
the source program through to program
evaluation and debugging.
• EASE49
• ASM49
HOST COMPUTER REQUIREMENTS
1. Operating system is one of the follows.
(1) CP/M""-80 (ver 2.0 or later)
memory capacity of the host computer
must be sufficient to run at least 52K
CP/M.
(2) MS-DOS® (ver 1.25, ver2.11)
(3) PC-DOS® (ver 1 .25, ver2 .11)
2. At least one RS232C communication port is
implemented.
3. Data transfer is performed through RS232C
communication port using BDOS function
call 6 on condition that console device is
assigned to TTY:.
MPB800 EVALUATION BOARD DATA
TRANSFER SYSTEM
ICs used
• Communication interface MSM82C51A
• Driver/receiver
SN75188N,
SN75189N
Transmission format
• 110 to 9600 bps (Switch able)
• 8 bits, 2 stop bits, non-parity
378
MPBBOO
Evaluation Board
:8
I~I
+5V +12V -12V
(4.5A) (O.2A) (O.2A)
Note:
B
CP/M is a registered trademark of Digital
Research Inc. (U.S.A.)
When the EASE80C49 is used on the
MSM80C50, the MSM80C39 evaluation chip
on the emulation board is to be replaced by
MSM80C40.
EASE49 and ASM-49 for PC-DOS, MS-DOS are
optional softwares.
--------------------------------------------------. EASE80C49 •
ASM-49 CROSS-ASSEMBLER
The ASM-49 is a floppy disk based high-performance assembler.
It translates source files generated on disk by using an editor, thereby generating object code files and
assembly list files.
LIST OF PSEUDO-INSTRUCTIONS
FEATURES
1. Free descriptive format source files
2. 35 types of powerful pseudo-instructions
available for assembler control purposes
3, Macro definition ability
4. 11 types of pseudo-instructions to enable
conditional assembly
5. Assembly repetition processing (loop processing)
6. Determination of variable values in the
source program by input from a console
during assembly, and linking to existing
source programs. (INPUT and LINK pseudoinstructions)
7. Capacity to describe up to 13 types of operators in
the source program operand column
Pseudo-instructions
Function
ORG Expression
Location counter value defined
as nnn. (Expression=nnn)
DS Expression
Reserves memory area for n
number of bytes. The first and
last byte values may be
changed.
Use ORG $+n to prevent
change of values.
(Expression = n)
DW Expression
16-bit data definition
DB Expression
8-bit data or ASCII character
string definition
EQU
Assignment of operand value
to name
SET
Same as EQU pseudoinstruction, but with
redefinition capacity
IF Expression
Evaluate expression value,
and skip to next ENDIF, END
or EDF (end of file) if result is
zero. Assemble the next
instruction if result is not zero.
NIF Expression
Evaluate expression value,
and skip to next ENDIF, END
or EDF (end of file) if result is
not zero.
END Expression
End of assembly
MACRO
Macro definition
GOTOLabel
Branch the subsequent
assembly to the destination
indicated in the label
REPT Expression
Denotes repetition block.
Assembly is executed the
number of repetitions indicated
by the expression value.
REPND
Definition of end of repetition
block
LIST
Pass option invalidated, and
output of full assembly list
NOLST
Inhibition of assembly list
outputs apart from error
messages
TITLE
Allocation of title at head of
assembly list page
379
D
eEASE80C49
e----~------------------------------~----------
EASE80C49 EMULATOR
Consisting of a host computer and the MPB800 Program Evaluation Board, the EASE80C49 Emulator
supports a wide range of development debugging operations efficiently and effectively.
MSM80C49RS and MSM80C50RS application programs can be debugged without user application
circuits just as easily as completed systems.
FEATURES
1. Real-time tracing function does not effect
execution time
The MPBBOO Evaluation Board incorporates a
real-time trace area for 1024 machine cycles.
When tracing for a particular user program area
address has been set, the port, program counter,
and probe data status are traced each time the
specified address is executed.
2. Execution time measurement
The user program execution time can be measured
by using the cycle counter on the MPB800 Evaluation Board. (Max. 16,777, 215 cycles)
This counter can also be used as a pass-Counter
to indicate the number of times a specified address
is executed.
D
3. 4096-byte user program area
A 4096-byte static RAM area in the MPB800
Evaluation Board is used as a user program area,
and user programs can be loaded/saved from the
host computer into this area. Furthermore,
with an EPROM programmer included on this
board the user program area contents can be
written into EPROMs, and EPROM contents
can be read.
4. Ample break functions
The emulator can suspend (break) program
execution by any of the following eight break
conditions.
a) BB (Breakpoint Break)
Break upon execution of specified address.
(Any address may be specified.)
b) EB (External Break)
Break by application of external break signal.
c) CO (Cycle counter Overflow break)
Break when overflow of cycle counter occurs.
d) TF (Trace Full break)
. Break when 4097 tracings executed.
e) PM (Probe Match break)
Break when probe data matches set data
f) IF (Instruction Fetch)
Break when machine code is fetched.
g)MX (MovX)
Break by MOVX instruction.
h) ER (Error code)
Break if incorrect machine code is fetched.
380
5. Extensive range of debugging commands
In addition to display/updating of all register, port,
and RAM contents, the following commands
enable all debugging operations to be executed
efficiently.
a) User program execution
Input format:
. STP number of instructions, start address
Input of this command results in the specified
number of instructions in the user program
being executed from the specified address
(start address).
Input format:
G [. start address]
Input of this command results in the user program being executed from the specified address
(start address). If no start address is specified,
'execution is started from the address indicated
by the program counter at that time.
b) Use of floppy disks
Input format:
LOA filename
Input of this command enables the specified file
contents (user program) to be loaded into the
MPBSOO Evaluation Board code memory which
serves as the MSM80C49RS/MSM80C50RS
. masked ROM area.
The same contents can also be loaded into the
utility buffer by using the LOU command.
Input format:
SAV, start address, end address, filename
Input of this command enables the contents of
the specified range of code memory to be saved
at the specified filename.
c) Instruction excuted bit memory
The EASE80C49 Emulator includes an instruction executed bit memory which indicates which
user program addresses have been executed.
Program flow can be determined by examination
of the contents of this memory.
------------------------------------------------eEASE80C49 e
MAJOR MEMORY OPERATIONS
6. Easy to remember command format
The MPB800 Emulator debugging commands
consist of command mnemonics followed by
parameters (address or mnemonic).
Command mnemonic configuration
a) First character
Denotes the function to be executed by the
emulator.
b) Second and following characters
Name of function to be executed by the
emulator-that is, MSM80C39 microcomputer or
MPB800 Evaluation Board register, memory, or
port name (abbreviation).
Example:
*DDM 0, 1F t
II \j I V I
ab cd e f
a: denotes wait for command input from emulator
b: denotes display of contents of specified register!
memory!board
c: data memory (equivalent MSM80C49RS!
MSM80C50RS RAM area) designation
d: start address of contents to be displayed
e: end address of contents to be displayed
I : carriage return denoting end of command input
1. Code memory
The code memory is an 4096 x 8-bit RAM area
which corresponds to the MSM80C49RS!
MSM80C50RS program area (masked ROM)
where user progrSlms are stored.
2. Data memory
The data memory is a 128 x 8-bit RAM area
corresponding to the data memory (RAM) on the
MSM80C49RS chip. The data memory area for
MSM80C50RS is 256 x 8-bits.
3. Utility buffer
The utility buffer is a 4096 x 8-bit RAM area used
in temporary saving from the emulator when a
load, save, or transfer command is entered.
4. Break point bit memory
The break point bit memory is also an 4096 x 1-bit
RAM area which has addresses identical to the
code memory. II a particular bit in this memory is
"1 ", program execution is suspended immediately
after the code memory contents corresponding to
that bit are executed.
5. Trace enable bit memory
The trace enable bit memory is another 4096 x 1-bit
RAM area which has addresses identical to the
code memory. If a particular bit in this memory is
"1 ", port and probe data is stored in the trace
memory when the code memory contents corresponding to that bit are executed.
6. Sync output bit memory
The sync output bit memory is another 4096 x 1-bit
RAM area which has addresses identical to the
code memory. When the code memory contents
are executed, the corresponding bits in the sync
output memory are checked, and if a "1" bit is
found, an output sync signal (active LOW) is
passed to the probe terminal.
7. Cycle counter enable bit
The cycle counter enable bit memory is also
another 4096 x'1-bit RAM area" which has
addresses identical to the code memory. When
the code memory contents are executed, the
corresponding bits in the cycle counter enable bit
memory are checked, and il a "1" bit is lound, the
cycle counter is counted up in step with that
machine cycle.
8. Probe comparison reglster!probe mask register
The conditions for generating a break by input
data from the probe (probe match break) can be
changed by altering these two settings.
9. Trace memory
The trace memory is a 1024 x 56-bit RAM area
used to store traced data.
The trace instruction is given by the trace enable
bit.
381
II
• EASE80C49 .,--------------------~--------------------------
EASE80C49 EMULATOR MEMORY CONFIGURATION
The EASE80C49 emulator which consists of a host CP/M'~ computer and the MPB800 Evaluation Board has
been designed for efficient debugging of MSM80C49RS and MSM80C50RS application programs.
The various sections of the EASE80C49 Emulator which can be used are outlined in the following diagram.
The sections enclosed in boxes represent the register and memory areas which can be accessed from the
host computer keyboard, and which can be displayed/update by emulator command.
INSTRUCTION EXECUTED BIT MEMORY
TRACE ENABLE BIT MEMORY
SYNC OUTPUT BIT MEMORY
CYCLE COUNTER ENABLE BIT MEMORY
BREAKPOINT BIT MEMORY
BTl
PRE
CM
S
0
C
E
UB
TM
UTILITY
BUFFER
CODE
MEMORY
TRACE
MOMORY
4096 x 8
4Q96x8
1024x56
"-\ 1/
4096xl
TRACE POINTER
I
DM
DATA
MEMORY
CYCLE COUNTER.
I
12ax8
CC
PROGRAM COUNTER ACCUMULATOR INSTRUCTION DATA
XM
PC
EXTERNAL
MEMORY
256x8
(Option)
PROBE.
COMPARE
REGISTER
I
INTERUPT
E]
PR
81
121
PROBE
;:.;MA;.;;S~K.:..---,
I·
PM
81
I
AC
I
BC
EXTERNAL
PROBE
TEST 0
IVDll
XP
ITO 11
81
TEST 1
24
PROGRAM STATUS WORD
IDal
PS
BREAK CONTROL BREAK STATUS
REGISTER
REGISTER
VDD
al
81
I
BS
E] I
PO
TIMER
TI
81
PORTO
(Bus Port)
Emulator memory configuration
382
1
10
TP
ERROR CODE
I
al
PORT 1
81
Pl
81
EC
81
PORT 2
81
P2
81
----~------------------------------------------.
EASE80C49 •
EXECUTION EXAMPLE
In this sample program, 1 byte is read from port 1, and a parity check is executed on the first 7 bits. The MSB
(most significant bit) is set to "1" if parity is odd parity, and reset to "0" if even parity. The result is then passed
to port 2. Note that errors have been intentionally included in this program for demonstration purposes. Various
emulator commands are used to correct the errors.
It is assumed that the program has already been assembled, and the object code has been stored in hexadecimal format in a file called "PARITY. HEX" in drive A.
Program list
o0
o0
o0
o0
o0
p0
o0
o0
o0
o0
o0
o0
o0
o0
o0
o0
o0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
***********************
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
o0 0 0
o0 0 I
o0 0 3
o0 0 5
o0 0 7
o0 0 9
*****
This program reads a byte from Port I and checks
bits 0 thru 6 for parity. If Parity is odd. then
bit 7 in the byte will be set and the result will
be output to Port 2. If the Parity is even. bit 7
will be reset before the byte is output to Port 2.
****************************
**************
*
MAIN PROGRAM
*
**************
PARITY
o9
5 3 7
140
E6 0
4 3 0
3 A
040
F
C
9
8
000 A
A
000 C
000 C
000 C
BA 0 8
000 C
000 E
9 7
000 F
I 2 I 2
A 7
o0 1 I
o0 I 2
7 7
o0 I 3
EA 0 F
o0 I 5
8 3
o0 I 6
0000
ERRORS
SYMBOL TABLE
PAR 0
0 0 0 C
PAR I
WAIT
ORG
IN
ANL
CALL
JNC
ORL
OUTL
JMP
; Input byte from PI
; Mask out bit 7
A. P I
A, # 7FH
PAR 0
PAR I
A, # 8H
P2, A
WAIT
; Jump if even parity
; Set bit 7
; Output byte to P2
o
**************
*
SUBROUTINES
*
**************
PAR 0
PAR 2
PAR 3
PARI
R 2, # 8
C
0, PAR 3
C
A
R 2 , PAR 2
MOV
CLR
JB
CPL
RR
DJNZ
RET
END
o0 0 9
PAR 2
o0
0 F
;
;
;
;
Set loop count
Initialize Carry Flag
Jump if bit 0 = I
Toggle Carry Flag
; Loop 8 times and ret
PAR 3
o0
I 2
383
,·EASE80C49 .,------------------------------------~---------A>EASE49
MPB80080C49
J~E.1982.
COPYRIGHT
• F CM
0
EMULATOR. VER
FFF
FF -
OKI
4.3
SEMICONDUCTOR
Code memory is filled with FFH
• LOA PAR ITY _ _f Contents of the "PARITY. HeX" file are transferred to the code, memory
* D CM 0 1 F - - - - Code memory location contents from address OH thru 1FH are displayed
000=09
53
7F
14
OC E6
09
010=12
A7
77
EA
OF
FF FF FF
83
43
08
3A
04
OA
BA
08
97
12
FF FF FF
FF
FF FF
FF
·EBP A -----Break point at address AH is set to "1".
F F F - - - Break paint bits from address 17H thru FFFH are st to "1"
• E BPI 7
• DBP 0
2 F - - - The break point bit status from address OH thru 2FH is displayed
00'0=0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
010=0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
020= 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
D
• CP 1
0
• CP 2
0 - - - - - Port 2 is set to "0"
·G
Port 1 is set to "0" (even parity)
0 - - - - - - ' - . ' Start of emulation from address OH
EMULATION BEOUN"
PC=O OA TERMI NATED
R 1 =CA
• CP 1
PO=FF PI=OO P2=00 TO=1 Tl=1 XP=FF AC=OO RO=
----. Port 2 is correct in respect to even parity
1 - - - - - Port 1 is set to "1" (odd parity)
• S DF -AL
PIP 2
AC - - Dump format is changed
• G 0 - - - - - - Start of emulation from address OH
EMULATION BEGUN
P C= 0 0 ATE RM IN ATE D P 1=01 P 2=09 AC=O 9- Port 2 is not correct in respect to odd parity
* dP 1
3
*CP2
0 - - - - - Port 2 is set to "0"
Port 1 is set to "3" (even parity)
• G 0 - - - - - - Start of emulation from address OH
EMULATION BEOUN
PC=OOA TERMINAT
• CP 1
4 - - - - - Port 1 is set to "4" (odd parity)
• CP 2
0
Port 2 is set to "0"
• G O ' . Start of emulation from address OH
384
------------------------------------------------eEASE80C4ge
EMULATIOM BEGUN
PC=O OA T b:RMINATED Pl=04 P2=OC AC=OC - Port 2 is not correct in respect to odd parity
·DTM - 1 0 . 1 0 - - - Trace contents of the last ten cycles are displayed
PC=015 RET
PO=FF P1=04 P2=00 TO=1 T1=1 IN=l
PC=005 JNC 09
PO=FF P1=04 P2=00 TO=1 Tl=l IN=l
POSSIBLE INTERRUPT ......... SEE APPENDIX3
PC=007 ORL A.f08 PO=FF Pl=04 P2=00 TO=l Tl=l IN=l
PC=009 OUTL P2.A PO=FF P1=04 P2=OC TO=1 T1=1 IN=1
PC=OOA JMP OOA
PO=FF Pt=04 P2=OC TO=l Tl=l IN=1
.EBP 5
.CP2 0
The break point bit at address 5H is set to "1"
.G
Start of emulation from address OH
XP=FF TP=0062
XP=FF TP=0064
XP=FF TP=0066
Port 2 is set to "0"
0
EMULATION BEGUN
PC=007 TERMINATED
·STP 5
PC=007
PC=009
PC=OOA
PC=OOA
PC=OOA
XP=FF TP=0058
XP=FF TP=0060
P1=04 ,P2=00 AC=04
Five steps (instructions) are executed
ORL
OUTL
JMP
JMP
JMP
A.f08
P2.A
OOA
OOA
o OA
P1=04
P1=04
P1=04
P1=04
P1=04
P2=00
P2=OC
P2=OC
P2=OC
P2=OC
AC=OC
AC=OC
AC=OC
AC=OC
AC=OC
·DCM 0 F - - - - " Code memory location contents from address OH thru FH are displayed
000=09
• CCM 8
• D CM 0
000=09
• R BPS
• CP 1
o
S3 '7F 14 OC E6 09 43 08 3A 04 OA BA 08 97 12
80
Gode memory location contents at address 8H are changed to "80H"
F
Code memory location contents from address OH thru FH are displayed
53 7F 14 OC E6
09
43 80 3A 04 OA BA 08
97
12
rhe break point bit at address 5H is set to "0" (reset)
Port 1 is set to "1" (execution of odd parity again)
1
·CP2 0
·G
0
EMULATION BEGUN
PC=OOA TERMINATED P1=01 P2=81 AC=81• CP 1
Port 1 is set to "7F" (execution of odd parity again)
7F
·CP2 0
·G 0
EMULATION BEGUN
PC=OOA TERMINATED P1=7F P2=FF AC=FF- Port 2 is correct in respect to odd parity
• SAy 0 1 F PRTY 1- Program with file name of "PRTY1.HEX" is stored
• FCM 0 FFF FF-- Code memory is filled with FFH
• V PRO F F F 0 - - EPROM is inserted into an EPROM socket and a blank check is
executed
• LOA P RTY 1
Program with file name of "PRTY.HEX" is transferred to code memory
• P PRO 1 F 0 - - - Transferred contents are written in the EPROM
•VPR
• tC
A>
0
1F
0 - - - EPROM contents are compared with code memory contents
-==--==- No error message (EPROM and code memory contents are identical)
------...: Return to CP/M(R) control
385
eEASE80C49
.e------------------------------------------------
LIST OF DeBUGGING COMMANDS
Characters which can be used
AaBbCcDdEeFfGgHhliJjKkLlMmNnOoPpQqRrSsTtUuVvWwXxYyZz 1234567890.,@+Cnti/C Cnti/P Cl1t1/Q Cntl/R CntlfT Escape Space
Display Commands
o
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
DAC
DBP, 000 I,FFF]
DBS
DCC
DCE, 000 [,FFF]
DCM, 000 I,FFF]
DDM, 00 [,7F]
DIE, 000 [,FFF]
DPO
DP1
DP2
DPC
DPS
DRG
DSK
DSO, 000 [,FFF]
DTI
DTM, XXX, YYYY
DTP
DTR, 000 [,FFF]
DVD
DXM, 00 [,FF]
DXP
Display Accumulator
Display Breakpoint Bit(s) Status
Display Break Status
Display Cycle Counter
Display Cycle Counter Enable Bit(s) Status
Display Code Memory
Display Data Memory
Display Instruction Executed Bit(s) Status
Display Port 0 (Bus Port)
Display Port 1
Display Port 2
Display Program Counter
Display Program Status Word, Test 0, Test 1, Interrupt Pin
Display Registers RO thru R7
Display Stack
Display Sync Output Bit Memory
Display Timer
Move Trace Pointer (XXXX) and display Trace Memory (YYYY)
Display Trace Pointer
Display Trace Enable Bit(s) Status
Display Vdd Pin
Display Extemal Memory
Display Extemal Probe Byte, Probe Mask and Probe Compare ~egister
Change Commands
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
CAC, FF
CCC, ZZZZZ77Z
CCM, FFF, FF
CDM, 7F, FF
CPO, FF
CP1, FF
CP2, FF
CPC,FFF
CPM, BBBBBBBB
CPR, BBBBBBBB
CPS, FF
Cl\FF
CXM, FF, FF
Change Accumulator
Change Cycle Counterr (Z77ZZZZZ is a positive or negative decimal number)
Change Code Memory
Change Data Memory
Change Port 0 (Bus Port)
Change Port 1
Change Port 2
Change Program Counter
Change Probe Mask (BBBBBBBB is a binary number)
Change Probe Compare Register (BBBBBBBB is a binary number)
Change Progr.am Status Word
Change Timer
Change External Memory
Fill Commands
1. FCM, 000, FFF, FF
2. FDM, 00, 7F, FF
3. FXM, 00, FF, FF
Fill Code Memory
Fill Data Memory
Fill External Memory
Enable C.ommands
1.
2.
3.
4.
386
EBP, 000 [,FFF]
ECE, 000 [,FFF]
ESO, 000 [,FFF]
ETR, 000 [,FFF]
Enable Breakpoint 6it(s)
Enable Cycle Counter Bit(s)
Enable Sync Output Bit(s)
Enable Trace Bit(s)
--------------------------------------------------. EASE80C49 •
Reset Commands
1.
2.
3.
4.
5.
6.
RBP, 000 [,FFF]
RCE, 000 [,FFF]
RIE, 000 [,FFF]
RSO, 000 [,FFF]
RTR, 0000 [,FFF]
RES
Reset Breakpoint Bit(s)
Reset Cycle Counter Enable Bit(s)
Reset Instruction Executed Bit(s)
Reset Sync Output Bit(s)
Reset Trace Enable Bit(s)
Reinitialize MPB800 System
Utility & Disk Input/Output Commands
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
CUB, FFF, FF
DUB, 000 [,FFF]
FUB, 000, FFF, FF
TCM, 000, FFF
TUB, 000, FFF
TST
LOA, filename
LOU, Filename
SAV, 000, FFF, filename
SVU, 000, FFF, filename
Change Utility Buffer
Display Utility Buffer
Fill Utility Buffer
Transfer Code Memory into Utility Buffer
Transfer Utility Buffer into Code Memory
Test
Load Program into Code Memory
Load Program into Utility Buffer
Save Code Memory Program
Save Utility Buffer Program
EPROM Writer Commands
1. PPR, 000, FFF, FF
2. VPR, 000, FFF, FF
3. TPR, 000, FFF
Pogram Code Memory onto EPROM
Verify EPROM with Code Memory
Transfer EPROM into Code Memory
Emulation Commands
1. G[,HHH]
2. STP [,EEEE][,HHH]
3. SBC, mnemonic
[,mnemonic]
4. SDF, mnemonic
[,mnemonic]
Begin real time emulation. HHH is the start address (hex).
Step emulation, where EEEE is the ,decimal number of instruction to execute,
and HHH is the start address (hex).
Set/Reset Break Control Bit
Set/Reset Dump Format
Command Line Editing & Keyboard Operation
1. Rubout
2. Cntl/C
3. Cntl/P
4.
5.
6.
7.
8.
CntllQ
CntllR
CntllS
Escape
@
Delete the last character entered
Return to CP/M
Copy all subsequent console output to the currently assigned list device.
Output is sent to both the list device untill the next Cnt/P is typed.
Continue normal display
Echoe current input line
Stop display
Abort any command inprogress
Repeat last command
387
o
• EASE80C49 •
EASE80C49 8-BIT 1-CHIP MICROCONTROLLER
PROGRAM DEVELOPMENT SUPPORT SYSTEM
Category
Hardware
Software
Manual
Model
Title
MPB800
8-bit 1-chip microcontroller evaluation board
EASE-49
Floppy disk based emulator'
ASM-49
Floppy disk based assembler'
TM-800
Program Development Support System-User's Manual
TCU-800
User application system connecting cables
TCS-B
Host CP/M(R) computer connecting cables (for if800 model 20/30)
TCP-8
Power supply cables (+5V,3.5A) (+ 12V, 0.2A) (-12V,0.2A)
TCX-1
External probe emulation purposes
Accessories
• Available under following operating system
• CP/M-80 (ver 2.0 or later)
• MS-DOS (ver 1.25, ver 2.11)
• PC-DOS (ver 1 .25, ver 2.11)
D
388
EASE80C51 mkll PROGRAM DEVELOPMENT SYSTEM
for
MSM83C154/80C51 CMOS 8-BIT, 1-CHIP MICROCONTROLLER
EASE80C51mkil PROGRAM DEVELOPMENT SYSTEM
The EASE80C51 mkll Program Development System is a high-performance dedicated system
featuring Oki's exclusive technology, and which has been specifically designed for rapid and efficient
program development of the Oki MSM83C154/80C51 8-bit single-chip microcontroller.
SYSTEM CONFIGURATION
The EASE80C51 mkll Program Development
System consists of the EASE80C51 Emulator (a
high performance program emulator which includes the EASE Host Monitor, the EASE8051 mkll Emulation Kit, and the host CP/M® or
PC-DOS computer) and the ASM51 Assembler
(a powerful assembler operated in CP/M® or
PC-DOS. With the EASE80C51 mkll Emulation
Kit connected online to the host CP/M computer
(such as the if800) equipped with an RS232C
interface, the system covers all operations from
assembly of the source program through to
program evaluation and debugging.
HOST COMPUTER REQUIREMENTS
1. Operating system is one of the follows.
(1) CP/M@l_80 (ver 2.0 or later)
memory capacity of the host computer
must be sufficient to run at least 52K
CP/M.
(2) MS-DOS@ (ver 1.25, ver2.11)
(3) PC-DOS"" (ver 1.25, ver2.11)
2. At least one RS232C communication port is
implemented.
3. Data transfer is performed through RS232C
communication port using BDOS function
call 6 on condition that console device is
assigned to TTY:.
EMULATOR DATA TRANSFER
ICs used
• Communication interface MSM82C51A
• Driver/receiver
SN75188N,
SN75189N
Transmission format
• 300 to 19200 bps (Switchable)
• 8 bits, 2 stop bits, non-parity
• Asynchronous
D
389
• EASESOC5.1mkll .-------~----------------
User's
application
circuit
User's
application
circuit
• EASE51
• ASM51
User cable
User cable
Terminal Unit
Host
computer
(CRT terminal etc.)
RS232C
RS232C
EASE80C51 mkll
Emulation
Kit
<3
c§
~
EASE80C51 mkll
Emulation
Kit
/
"'" AC power supply
(1) Connection to host computer
(2) Connection to terminal unit
Fig. 1 System configuration
Note 1. CP/M is a registered trademark of Digital Research Inc. (U.S.A.)
2. The AC power supply can be switched to 90-132V and 180V-264V at a terminal inside the emulation kit.
3. PC-DOS stands for IBM personal computer DOS.
390
----------------------------------------~-----.
EASE80C51mkll •
ASM51 ASSEMBLER
The ASM51 is a floppy disk based high-performance assembler.
This assembler is used to translate source files generated on disk by using an editor (available on the market),
thereby generating object files (Intel HEX format), assemble list files, cross-reference list files, and symbol list
files in the specified devices.
OUTPUT FILES
1.
2.
3.
4.
PART OF PSEUDO-INSTRUCTIONS LIST
Object files (Intel HEX format)
Assembly list files
Cross-reference list files
SymbOlic list files
Pseudo-instructions
Function
EQU
Assignment of operand value
to name
SET
Same as EQU pseudoinstruction, but with
redefinition capacity
ORG
Setting of program start
address
FEATURES
1. Free descriptive format source files
2. Capacity to describe up to ten types of operators
in the source program operand column
3. Ability to specify the number of characters per line
and the number of lines per page in assemble list
files
4. 24 powerful pseudo-instructions
5. Control of assemble list file outputs by LIST or
NOLIST pseudO-instruction
6. Output file and output device can be specified
when the assembler is started.
END
Indication of end of program
JMP
Automatic change to relative,
internal 2K page, or all pages
jump instruction after checking
branch destination
CALL
ASM51 ASSEMBLER FUNCTIONAL
BLOCK DIAGRAM
Automatic chang to relative,
internal2K page, or all pages
call instruction after checking
branch destination
RADIX
Radix changed to 2, 8,10, or
16 depending on value of
operand
DB
8-bit data or ASCII character
definition
Source file
DW
16-bit data definition
DS
Reserves memory area for
specified number of bytes
NSE
Setting of 0 in the 4 lower
order bits of the assembler
location counter, and addition
of 16. The NOP instruction is
assigned to blank areas
where no machine language
instruction has been assigned.
DATE
Insertion of date in assemble
list title
EJECT
Assemble list page feed
operation
ASM51
Assembly list files
'------.. Symbol list files
......... Cross~reference
list files
TITLE
Insertion of assemble list title
LIST
Designation of assemble list
output
NOLIS
Zuhibition of assemble list
output
391
o
eEASE80C51mkil
e---------------------------------------------
EASE80C51mkil EMULATOR
Connected to the host computer via an RSS232C interface, the EASE80C51 mkll Emulator supports a
wide range of development debugging operations efficiently and effectively.
MSM83C154/80C51 application programs can be debugged without user application circuits just as
easily as completed systems.
FEATURES
1. Real-time emulation
/
Real-time emulation without insertion of a wait
state is possible because of the MSM83C154E
evachip.
2. Execution time measurement
The user program execution time can be measured with the cycle counter in the Emulation Kit.
(Max. 4,294,836,225 cycles)
This cycle counter start/stop is effected according to the cycle counter start address/stop address set by the command.
o
3. Mass storage user program area
This emulator provides a 64K-byte RAM area,
(which is the entire address space of
MSM83C154/80C51l as the code memory
(user program area). So, the largest program for
MSM83C154/80C51 can be fully loaded in this
RAM area.
It is also possible to assign 4K-byte units of program
memory area to the RAM area on the emulation kit or
the ROM on the u$Elr's application circuit by using
the mapping command.
This emulator further provides the EPROM programmer to enable the user program area contents to be written to the EPROM or the EPROM
contents to be read.
(EPROMs supported: Intel 2732, 2732A, 2764
or 27128 or equivalent:)
4. Ample break functions
The emulator can suspend (break) program execution by any of the following break conditions.
All conditions can be set and cancelled as
desired.
.
a) Breakpoint break
Br~ak upon execution of the address where a
break point has been set. (Any address to be
specified,)
b) Address break
Break execution of the address specified
when the emulation command input was applied. It is also possible to specify a break
after the specified address has been executed n times.
c) Power down break
Break occured when evachip going to the
power down mode ..
d) Break by external forced bre.ak signal
Break by input of low level break signal from
outside via the attached probe cable.
392
e) Break by trace memory overflow
Break occurs when the trace memory is filled
up with trace data.
f) Break by cycle counter overflow
g) Break by internal RAM/SFR area contents
Break occurs when the contents of the specified RAM/SFR in the MSM83C154E matched
with the specified contents the specified
number of times upon execution of the program at the specified address.
5. Comprehensivli! real-time trace functions
This emulator has the following two real time
trace areas not affecting the execution time.
1. Trace memory
This is the memory to trace (store) the status of
the ports, carry flag and accumulator of the
MSM83C154E when an instruction in the program memory area is executed. (Up to 2048 machine cycles)
Tracing is instructed in three ways as shown
below.
a) To start tracing each time the specified address is executed.
b) To start tracing upon execution of a special
instruction (ACALL, AJMP, LCALL, LJMP,
RET, RET!, PUSH or POP)
c) To cause tracing by trace start/stop bit
2. Flash trace memory
The memory to trace status of the whole internal
RAM or SFRarea in the MSM83C154E, when
the instruction at the address specified by the
emulator command (debug command) being
executed.
The contents of the internal RAM or SFR area
can be stored up to 16 times in this memory.
6. Easy-to-use emulator commands
The emulator command (debug command) of
this emulator consists of the command mnemonic and succeeding parameter(s) (address or
mnemonic).
Command mnemonic structure
a) First letter
Represents the function to be performed by
the emulator.
b) Second letter and on
Represent MSM83C154E evachip (or EASE80C51 mkll emulation kit) register, memory, or
port name.
- - - - - - - - - - - - - - - " ' - - - - - - - - - - - . EASE80C51 mkll •
Example:
*DDM
0
1F..J
I/\Jc dI eVI
ab
f
a: Indication of waiting for command input from
emulator
b: Instruction of displaying contents of specified
object
c: Instruction of data memory (equivalent to internal
RAM area in MSM83C154E)
d: Start address 01 contents to be displayed
e: End address 01 contents to be displayed
I: Carriage return indicating end 01 command input
This emulator provides various emulator commands not only for display/modification of the
contents of each register and port of the special
evaluation chip MSM83C154E but also for
efficient debugging operation.
Input format:
STP number-of-instructions start-address
Inputting the above command causes the user
program to be executed for as much as the
specified number of instructions from the
specified addresses (start address).
It is possible to modify the display format to be
easier to read by specifying the object of
contents display by the SSF command.
Input format:
G start-address, parameter
Parameter input format
(1) Break-address, ... , break-address
(2) Break-address (n)
(3) Break-address RAM ram-address (byte-n)
(4) Break-address sfr-mnemonic (byte-n)
Inputting the command as shown in (1) causes the
user program to be executed from the specified address (start address), and breaks the program execution upon execution of any of the specified break addresses.
Inputting the command as shown in (2) causes the
user program to be executed from the specified start
address, and breaks the program execution when it
has passed the specified break address in times.
Inputting the command, as shown in (3), causes the
program to be executed from the specified address
(start address). When the user program at the
specified break address is executed, the contents of
the specified address (ram address) of the internal
RAM in the MSM83C154E are compared with
the specified contents (byte) and the program execution is broken if they agree the specified
number of times (n).
Inputting the command, as shown in (4), causes the
user program to be executed from the specified address (start address). When the user program at the
specified break address is executed, the contents of
the specified SFR in the MSM83C154E are
checked. If the contents agree with the specified
value (byte) the specified number of times (n),
breaking occurs.
Input format:
(1) LOD filename
(2) SAY filename start-address end-address
(3) VER filename start-address end-address
Inputting the command, as shown in (1), enables the
contents (user program) of the specified file on
the host computer to be loaded into the code
memory on the EASE80C51 mkll emulation kit
corresponding to the program memory area
(user program area) of the MSM83C154/80C51 .
Inputting the command, as shown in (2), enables the
block of code in the specified range of the code
memory to be saved using the specified file name.
Inputting the command, as shown in (3), enables the
block of code in the specified file to be compared with
the block of code in the code memory.
Input format:
(1) DIAG filename
(2) M
(3) @
Inputting the command, as shown in (1), enables the
command in the specified file to be executed automatically. Use of the PAUSE command in combination enables execution of the command in the file to
be suspended temporarily.
Inputting the command, as shown in (2), enables the
command line defined by the MAC command to be
executed.
Inputting the command, as shown in (3), enables the
last command to be executed again.
Input format:
(1) LIST filename
(2) NLST
If LIST command is entered, the emulator create
the CP/M file on the host computer and writes
into it any characters which are output to the
console until entering the NLST command.
Use of the above "DIAG" command in combination
enable the debugging work to be executed and stored
in the file automatically.
Input format:
S tm-mnemonic data number
Using the S command, you can search out the trace
information in the trace memory.
Where the "tm-mnemonic" is the element of the
trace information in the trace memory that you
wish to search, and "data" is a value of that
element. "number" is the time of an agreement.
For example, Entering "S" PO 2 3", the emulator
searches through the trace memory from the top
and finds the pOSition where the trace PO data is
equal to 2, three times, and displays the trace
information at that position.
393
o
eEASE80C51mkll
e------------------__--------------------------
DISK ACCESS COMMANDS
1.
2.
3.
4.
5.
6.
7.
8.
LOD
SAV
VER
DIAG
LIST
NLST
HELP
FDD
[dr:) filename
[dr:) filename [address adress)
[dr:) filename [address adress)
[dr:) filename
[dr:) filename
dr: ... dr:
Load Program into Code Memory
Save Code Memory Program
Verify File with Code Memory
Execute command file
List console Output into Disk file
End listing
Display HELP File
Set Disk Drive
EPROM PROGRAMMER COMMANDS
1.
2.
3.
4.
PPR address address [address)
TPR address address [address)
VPR address address [address)
TYPE mnemonic
Program Code Memory into EPROM
Transfer EPROM into Code Memory
Verify EPROM with Code Memory
Set EPROM type
ASSEMBLE COMMANDS
1.
2.
3.
4.
5.
ASM
DASM
DBLK
SPB
SDB
address
address
address [address)
address [address)
address [address)
I
Assemble to Code Memory
Disassemble to Console
Display Block Memory
Set Program Block
Set Data Block
TRACE COMMANDS
1.
2.
3.
4.
5.
6.
D
7.
8.
9.
10.
DTM-numbernumber
DFTM number number
DTG
DFA
S mnemonic data number
SFF mnemon ic
STG mnemonic
SFA address [... address)
RFA address [... address)
RTG
Display Trace Memory
Display Flash Trace Memory
Display Trigger Mode
Display Flash Trace address
Search Trace Memory data
Set Flash Trace Display format
Set Trigger Mode
Set Flash Trace address
Reset Flash Trace address
ResetTrigger Mode
EMULATION COMMANDS
1.
2.
3.
STP number [number)
G[st-address) [,break-parameter)
. If the optional st-address if given, emulator will begin emulation from st-address.
And if optional break-parameter is given.
emulation will break on the first break-parameter to be satisfied.
break-parameter = break-address, ..... , break-address (max. 10)
break-address (pass count)
break-address RAM ram-address (byte-pass count)
break-address sfr-mnemonic (byte-pass count)
SSF (+/-) mnemonic [...(+/-) mnemonic)
Set STP Command Display format
DISPLAY COMMANDS
1.
2.
3.
4.
5.
6.
394
D
Dsfr-mnemonic
DSFR mnemonic [ ... mnemonic)
DPC
DREG
OSBUF
Display Register Flag Port
Display sfr-mnemonicoata
Display mnemonic data
Display Program Counter
Display all Register Bank
Display receiver data
,
------------------------------------------------e EASE80C51mkil e
CHANGE COMMANDS
.1.
2.
3.
4.
5.
Csfr-mnemonic data
CSFR [mnemonic .. ,mnemonic!
CPCdata
CREGdata
CSBUFdata
Change sfr-mnemonic
ChangeSFR
Change Program Counter
Change Register bank
Change Transmitter data
CODE MEMORY & DATA MEMORY COMMANDS
1.
2.
3.
4.
5.
6.
7.
8.
9.
DCM address [address!
DDM address [address!
DXDM address [address!
CCMaddress
COM address
CXDM address
FCM address address byte
FDM address address byte
FXDM address address byte
Display Code Memory
Display Data Memory
Display External Data Memory
Change Code Memory
Change Data Memory
Change External Data Memory
Fill Code Memory with byte
Fill Data Memory with byte
Fill External Data Memory with byte
ATTRIBUTE MEMORY COMMANDS
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
DBP address [address!
DTR address [address!
DSO address [address!
DIE address [address!
EBP address ... address
ETR address ... address
ESO address ... address
FPB address address byte
FTR address address byte
FSO address address byte
RBF\address ... address
RTR'address ... address
RSO address ... address
RIE
Display Break Point Bit Memory
Display Trace Enable Bit Memory
Display Sync Output Enable Bit Memory
Display Instruction Executed Bit Memory
Enable Brak Point Bit
Enable Trace Enable Bit
Enable Sync Output Enable Bit
Fill Break Point Bit Memory with byte
Fill Trace Enable Bit Memory with byte
Fill Sync Output Enable Bit Memory with byte
Reset Break Point Bit
Reset Trace Enable Bit
Reset Sync Output Enable Bit
Reset Instruction Executed Bit Memory
BUFFER MEMORY COMMANDS
1.
2.
3.
DBUF
TBUF
LBUF
D
Display Buffer Memory
Transfer Data Memory & SFR Data into Buffer Memory
Load Buffer Memory into Data Memory & SFR
CYCLE COUNTER COMMANDS
1.
2.
3.
DCC
CCCdata
TIME data
Display Cycle Counter
Change Cycle Counter
Set 1 cycle time
BREAK CONDITION & STATUS COMMANDS
1.
2.
3.
DBC
DBS
SBC (+/-) mnemonic .. (+/-) mnemonic
Display Break Condition
Display Break Status
Set Break
OTHER COMMANDS
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
RES
RESE
SIOForH
PAUSE
EXIT
DIR[dr:!
MAP [address!
MAC
M
@
M80C51
M83C154
EASE80C51 mKIl System initialization
MSM83C154E Evachip reset
Set Emulator to I/O terminal mode
Stop command file execution and wait key-in
Return Host computer's OS
Display file directory
Mapping
Define command execution
Execute Defined command
Repeat front com mand
Set Emulatortothe MSM80C51 checking mode
Set Emulatortothe MSM83C154 checking mode
395
• EASE80C51 mkll . - - - - - - - - - - - - - - - - - - - - - - - -
EASE80C51mkil PROGRAM DEVELOPMENT SUPPORT SYSTEM
for the MSM83C154/80C51 CMOS 8-BIT 1-CHIP MICROCONTROLLER
Clock select switch
AC power
connector
Reset SWit\ \
r----,
Mode switch
Probe cable
connector
Crystal oscillator
connector
EPROM programmer
User cable
connector
300 (W) x 105 (D) x 210 (H) mm
RS232C
connector
Category
o
Model name
Component name
Hardware
EASE80C51 mkll
Emulation kit
Emulation kit for MSM83C154/80C51
Software
EASE
ASM 51
Host monitor for floppy disk based (Note 2)
Assembler for floppy disk based (Note 2)
Manuals
TM-80C51
AM-80C51
EASE80C51 mkll Emulator User's Manual
ASM51 Assembler User's Manual
Accesories
TCU-80C51
TCS-n
TCP-2
TCX-2
User application circuit connection cable
Host computer connection cable (3) (Note 3)
AC power supply cable
Em ulation probe cable
Note 1. Refer to the ASM51 Assembler User's Manual for assembler details.
Note 2. PCDOS 51 /4 floppy disk, PC format, double-side double-density (8 sectors x 40 tracks x 2)
PC DOS stands for IBM personal computer DOS.
CP/M-80 8-inch floppy disk, IBM3? 40 soft-sectored format, single-side single-density.
CP/M-80 is the registered trademark of Digital Research Co.
Note 3. Two cables are used for connecting the if800 or equivalent computer to the EASE80C51 mkll
Emulation Kit-one to the CH1 port, and the other to the CH2 port. (Model name, TCS-2)
The third cable is for connection of an IBM PC or equivalent computer to the EASE80C51 mkll
Emulation Kit. This calbe is connected to the CH1 port. (Model name, TSC-3).
396
--------------------------------~-----------.
EASE80C51mkll •
OPTIONAL SOFTWARE
OS
Name
Supplied software
CP/M-BO
MS-DOS
PC-DOS
PASM
0
0
0
MAC51
0
0
0
RL51
0
0
0
LIB51
0
0
0
0
0
0
0
SID51
OBJHEX
.
.
VMS
UNIX
·
·
·
·
·
·
·
·
·
·
·
·
Pre-Processor
Macro-Assembler
Linker
Librarian
Symbolic Debugger
Object Converter
• ·····Seing developed
OPTIONAL HARDWARE
Type
EASEB
Remarks
Handy 1/0 terminal
EASE8 can be used as a terminal unit for the EASE80C51 mkll Emulation Kit.
(Convenient portable model)
o
397
PAC~GE
for the
MSM80C51 CMOS 8-BIT MICROCONTROLLER
MAC51 SUPPORT SOFTWARE
FEATURES
1. Symbolic relocatable assembly language programming for 80C51 1154 microcontrollers
2. Produces Relocatable Object Code which is
linkable to other 8051 Object Modules
3. Encourages modular program design for
maintainability and reliability
4. Macro Assembler features conditional assembly and macro capabilities
MAC51 SUPPORT SOFTWARE PACKAGE
The following MAC51 programs are available
to develop user programs.
PASM Pre-processor
PASM is used to expand macro calls,
conditional assembly statements, and INCLUDE
statements included in user generated source
programs, thereby generating expanded source
programs. A number of items of development
information are inserted in these developed
source programs for MAC51 .
IJ
MAC51 Assembler
MAC51 converts source programs into
relocatable codes to form relocatable object files
(OBJ files). Print, symbol, cross reference, and
error files are generated as assembly
information.
398
LIB51 Librarian
The LlB51 program manages OBJ files for
each module. Files consisting of a number of
relocatable object modules (OBJ modules)
generated by LlB51 are called the object library.
LlB51 handles object library generation, and
OBJ module addition, deletion, and upgrading.
RL51 Linker
RL51 links and relocates one or more OBJ
modules to generate one absolute object
module. RL51 also generates a list file
consisting of symbol table and link map as link
information. OBJ modules which serve as the
RL51 input can be OBJ files generated by
MAC51, and OBJ modules located within the
object library generated byLlB51.
SID51 Symbolic debugger'
SID51 is used when a symbol using
debugger is selected. Absolute object files are
converted to Intellec HEX format files.
Outline of Program Development
The procedures involved in the processing
from source program generation through ROM .
loading are described below in the sequence
indicated in Figure 1-1. For further details of
individual utilities, refer to the respective
manuals.
- - - - - - - - - - - - - - - - - - - - - - - - - - - - . MAC51 •
1. Generation of MAC51 assembly language
source program by the editor.
Source programs can contain basic and
pseudo instructions, and assembler control,
macro call, conditional assembly, and
INCLUDE statements.
2. When macros are used, macro definitions are
generated in macro library files (with MAC
extension) by the editor. Macro call
statements are described within source
programs.
3. Where macro call, conditional assembly
statement, and INCLUDE statement
descriptions are included in a source
program, there are expanded by PASM to
form an expanded source program.
4. Source programs or expanded source
programs are assembled by MAC51 to form
relocatable object files.
5. A group of relocatable object files can be
managed by LlB51 together in a relocatable
object library files (LIB extension). When
required, object modules can be called from
this object library by RL51.
6. Relocatable object files are converted to
absolute object files by RL51. At this stage,
one or more relocatable object files can be
linked to relocatable object modules in the
library file.
7. ABS modules are converted by SID51 or
OBJHEX to Intellec HEX format files. With
EASE80C51 mkll, HEX file contents can be
written into EPROM devices .
o
5.
EASE80C51mkil
Fig. 1 -1 Program development flow
399
Note: Product data and specification information herein are subject to
change without advance notice for the sake of technical improvements in
performance and reliability since OKI is permanently endeavoring to supply
the best products possible. The manufacturer does not assume responsibility for customer product designs and for the fitness to any particular
application , nor for patent rights or other right s of third parties and infringements thereof resulting from the use of his products . Thi s publication does
not commit immediate availability of the product(s) described by it. If in
doubt, please . contact your nearest OKI representative . The information
furnished by OKI is believed to be accurate and reliable . However, no
responsib ility is assumed for inaccuracies that may not have been detected
prior to printing , and for tho se whi ch occur beyond our cont ro l. Thi s issue
substitutes and supersedes all publications previously supplied by OKI for
the captioned product(s) . This document may not, in wh ole or part, be
copied, photocopied, reprodu ced, translated , or converted to any machine
readable form , without prior written consent from OK!.
OKI Semiconductor
650 North Mary Avenue, Sunnyvale, CA #94086, U.S.A.
Q Tel: (408)720-1900 QFax : (408)720 -1918 0 Telex : 296687 OKI SNTA
FOR FURTHER INFORMATION PLEASE CONTACT :
OKI ELectric Industry Co., Ltd,
Head Office Annex
10·3, Shibaura, 4·chome,
Minato ·k~ , Tokyo tOO, Japan
Tel : 3- 454- 2ttt
Fax : 3- 798- 7643
Telex . J22627
Electr onic Devices Group
Overseas Marketing Dept.
Printed in USA
OKI Semiconductor
650 North Mary Avenue,
Sunnyvale , CA #94086, U.S.A
Tel : (408 ) 720- 1900
Fax : (408) 720- 1918
Telex : 296687 OKI SNTA
OKI Electric Europe GmbH
Niederkasseler Lohweg 8,
0 - 4000 Dusseldorf II ,
Fed . Rep . of Germany
Tel ' 0211 - 59550
Fax : 0211 - 591669
Telex 858- 4312
OKI Electronics (Hong Kong) Ltd.
16th Floor , Fairm ont House,
8 Cotton Tree Drive, Hong Kong
Tel 5- 263111
Fax : 5- 200102
Telex . 62459 OKIHK HX
Source Exif Data:
File Type : PDF
File Type Extension : pdf
MIME Type : application/pdf
PDF Version : 1.3
Linearized : No
XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
Create Date : 2013:08:01 08:37:46-08:00
Modify Date : 2013:08:02 03:20:29-07:00
Metadata Date : 2013:08:02 03:20:29-07:00
Producer : Adobe Acrobat 9.55 Paper Capture Plug-in
Format : application/pdf
Document ID : uuid:84b71186-c041-4549-9b04-c980a6ef7308
Instance ID : uuid:01518aa6-9ec0-f84a-a2d1-a69ddd573e1e
Page Layout : SinglePage
Page Mode : UseNone
Page Count : 406
EXIF Metadata provided by EXIF.tools