1986_OKI_Microprocessor_Databook 1986 OKI Microprocessor Databook
User Manual: 1986_OKI_Microprocessor_Databook
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MICROPROCESSOR
DATABOOK
1986
1310 Kifer Road
Sunnyvale, CA 94086
Pt)U6- CO~gFTT
(408) 737'()204
,Irst t:dltlon February , 1986
CONTENTS
[!]
CMOS MICROPROCESSOR LINE-UP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
~ SYSTEM CONFIGURATION (PERSONAL COMPUTER, WORD PROCESSOR) . . . . . . . . .
PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
5
DATA SHEET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
13
[II
[!]
•
•
CPU.........................................................
MSM80C85A RS/GS
8·BIT MICROPROCESSOR. . . . . . . . . . . . . . . . . . . . ..
15
16
MSM80C85A·2. RS/GS
8·BIT MICROPROCESSOR .................. . . ..
33
MSM80C86
RS/GS
16·BIT MICROPROCESSOR .•...................
52
MSM80C88
RS/GS
a·BIT MICROPROCESSOR
77
I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
MSM81C55
RS/GS
2KS RAM WITH I/O, TIMER ..................... 102
MSM83C55
RS/GS
16K ROM WITH I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
MSM82C12
RS/GS
MSM82C37 A-5 RS/GS
8-BIT INPUT/OUTPUT PORT .................... 122
PROGRAMMABLE DMA CONTROLLER ............... 130
MSM82C43
RS/GS
INPUT/OUTPUT PORT EXPANDER ................ 154
MSM82C51A
RS/GS
PROGRAMMABLE COMMUNICATIONS INTERFACE ... 160
MSM82C53-5
RS/GS
PROGRAMMABLE INTERVAL TIMER ............. 176
PROGRAMMABLE PERIPHERAL INTERFACE ........ 187
MSM82C55A-5 RS/GS
•
.....................
MSM82C59A-2 RS/GS
PROGRAMMABLE INTERRUPT CONTROLLER ....... 203
MSM82C84A
RS/GS
CLOCK GENERATOR AND DRIVER ............... 220
MSM82C84A-5 RS/GS
CLOCK GENERATOR AND DRIVER ............... 230
MSM82C88
BUS CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
AS/GS
PERiPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . 249
MSM5832
RS
REAL TIME CLOCK/CALENDAR. .. "
MSM58321
RS
REAL TIME CLOCK/CALENDAR. ................. 260
............ 250
MSM6242
RS/GS
REAL TIME CLOCK/CALENDAR (BUS INTERFACE) .... 276
CMOS
MICROPROCESSOR
LINE - UP
CMOS MICROPROCESSOR LINE - UP
POWER SUPPLY
PRODUCTS FAMILY NAME
VOLTAGE CURRENT
(MAX)
PACKAGE
REMARKS
MSM80C85A
5V
22m A
40 DIP
44 FLAT
8 BIT MICROPROCESSOR
3 MHz,
MSM80C85A-2
5V
25m A
40 DIP
44 FLAT
8 BIT MICROPROCESSOR
5MHz
16 BIT CPU
MSM80C86
5V
55mA
40 DIP
56 FLAT
16 BIT MICROPROCESSOR
5MHz
8 BIT CPU
MSM80C88
5V
55mA
40 DIP
56 FLAT
8 BIT MICROPROCESSOR
5MHz
MSM81C55
5V
5mA
40 DIP
44 FLAT
2048 BIT STATIC RAM with
I/O and TIMER
MSM83C55
5V
5mA
40 DIP
44 FLAT
16384 .BIT ROM with I/O
MSM82C12
5V
1mA
24 DIP
24 FLAT
8 BIT INPUT/OUTPUT PORT
MSM82C37 A-5
5V
10mA
40 DIP
44 FLAT
PROGRAMMABLE DMA
CONTROLLER
MSM82C43
5V
1mA
24 DIP
24 FLAT
INPUT/OUTPUT PORT EXPANDER
MSM82C51A
5V
5mA
28 DIP
32 FLAT
PROGRAMMABLE COMMUNICATIONS INTERFACE
MSM82C53-5
5V
5mA
24 DIP
32 FLAT
PROGRAMMABLE INTERVAL
TIMER
MSM82C55A-5
5V
5mA
40 DIP
44 FLAT
PROGRAMMABLE PERIPHERAL
INTERFACE
MSM82C59A-2
5V
5mA
28 DIP
32 FLAT
PROGRAMMABLE INTERRUPT
CONTROLLER
MSM82C84A
5V
10mA
18 DIP
24 FLAT
CLOCK GENERATOR and DRIVE'R
MSM82C84A-5
5V
10mA
18 DIP
24 FLAT
CLOCK GENERATOR and DRIVER
MSM82C88
5V
10mA
20 DIP
24 FLAT
BUS CONTROLLER
MSM5832
5V
0.1mA
18 DIP
REAL TIME CLOCK
MSM58321
5V
0.1mA
16 DIP
REAL TIME CLOCK
MSM6242
5V
10~
18 DIP
24 FLAT
REAL TIME CLOCK
DIRECT BUS CONNECTED
8 BIT CPU
I/O
PERIPHERALS
2
-
SYSTEM
CONFIGURATION
~
en-a
.~
MROM
MSM83C55
MSM3864
MSM38128A
MSM38256
MSM53256
MSM531000
EPROM
MSM2764
MSM27128
MSM27256
MSM27C64*
2
E PROM
MSM2816A
DRAM
MSM3764
MSM41256
MSM41464*
MSM41 000*
SRAM
MSM81C55
MSM2114
MSM2128
MSM5114
MSM5128
MSM5165
MSM5188*
MPD101
MPD200
MPD640
~III
==
i~
MSM58292
MSM5219
MSM5838
MSM5238
MSM5839
MSM5260
n~
0.-
MSM82C53-6
MSM6242
MSM5832
MSM58321
zn
... 0
-I
Q-a
Cc
MSM82C59A-2
INTERRUPT
CONT.
; iii
C
-;l1l:I
P
CLOCK GEN.
DRIVER
MSM82C84A-6
MSM82C84A
0---
U
MSMSOC85A
MSMSOC85A-2 1 KEYBOAR D
MSMSOC86
ENCODER
MSMSOC88
MSM3914
MSM5840
MSM5842
MSM80C49
COMMUNICATION
INTERFACE
z~
FDD
CONTROLLER
MSM82C51A
I/O PORT
rr
MSM82C12
PERIPHERAL
INTERFACE
li
DMA
CONTROLLER
MSM82C55A-6
MSM82C37A-5
;l1l:I
C
-a
R
en
MSA151*
III
en
*Under Development
o
;l1l:I
PACKAGING
PACKAGING
PAGKAGE
I
PRODUCTS
I.J
I
DIP
FLAT
MSM80C85A
40
44
MSM80C85A-2
40
44
MSM80C86
40
56
MSM80C88
40
56
MSM81C55
40
44
MSM83C55
40
44
MSM82C12
24
24
MSM82C37 A-5
40
44
MSM82C43
24
24
MSM82C51A
28
32
MSM82C53-5
24
32
MSM82C55A-5
40
44
MSM82C59A-2
28
32
MSM82C84A
18
24
MSM82C84A-5
18
24
MSM82C88
20*
24
MSM5832
18
-
MSM58321
16
-
MSM6242
18
24
Note: 1. Model numbers suffixed by RS denote plastic DIP, while GS denotes plastic FLAT.
Ex.
MSM80C85ARS. . . . . . .. plastic DIP
MSM80C85AGS . . . . . . .. plastic FLAT
2. MSM82C88 is packaged into ceramic DIP for the time being.
Ex.
MSM82C88AS . . . . . . . .. ceramic DIP
MSM82C88GS. . . . . . . .. plastic FLAT
6
----------------------------------~----------. PACKAGING •
• 20 PIN CERAMIC DIP
25.40 ±0.25
It)
N
c:i
+1
N
<0
r-:
INDEX MARK
MSM82C88
0.35 MAX
• 16 PIN PLASTIC
20.0MAX
\ INDEX MARK
7.62±O.30
11
iru
MSM58321
N
I
15° MAX
Seating Plane
7
• PACKAGING .----------------------------------------------• 18 PIN PLASTIC
7.62:tO.30
MSM82C84A
MSM82C84A·5
~--I--
2.54:tO.25
• 24 PIN PLASTIC
15
~ ~ 1--...:..
=.2=-4=%.:.,:0.::;,;30=---I
~~m~i
2.54:t0.25
MSM82C12
MSM82C43
MSM82C53-6
8
O.65MAX
15"MAX
• PACKAGING ..
• 28 PIN PLASTIC
~~~~---------------z,; ~E315'24±O'30
i~t
O.6MAX
S:;tin;
MSM82C51A
MSM82C59A·2
15"MAX
Pi'ail8
• 40 PIN PLASTIC DIP
i
MSM80C85A
MSM80C85A·2
MSM80C86
MSM80C88
MSM81C56
MSM83C55
MSM82C55A-6
MSM82C37 A-6
(unit: mm)
15.24 ± 0.30
0"-15"
0'6MA~
9
• PACKAGING .----------------------------------------------• 24 PIN PLASTIC FLAT
a..
>....
I
It)
11
~I
_I
0
~
,...
f'!
0
N
-
N
o
~
,... ~
+f
~-- ~~
0
en
M cD
ici
10
a..
2.0 to.4
MSM82C12
MSM82C43
MSM82C84A
MSM82C88
MSM82C84A-5
MSM6242
8.0 to.2
>-
2.0 to.4 ~I
~
• 32 PIN PLASTIC FLAT
N
ci
+f
o
cD
r
c
o
+f
N
o
MSM82C51A
MSM82C53-6
MSM82C59A-2
10
ci
c--m ___
,~jL~
~'O
-----------------------------------------------. PACKAGING •
• 44 PIN PLASTIC FLAT
v
ci
- - - - - - - - - +1_
o
N
N
v
ci
ci
+1
+1
LO
ci
v
ci
------+1
o
N
~
MSMSOcS5A
MSMSOCS5A-2
MSMS1C55
MSMS3C55
MSMS2C55A-6
MSMS2C37 A-5
2.0 ± 0.4
0.15 - 0.05
9.5 ± 0.2.
~-----~~--~~
• 56 PIN PLASTIC FLAT
v
LO ci
N_+I
-I-I-
1.5±0.1
C! 0
.... N
v
ci
N
ci
+1
+I
LO
N
ci
,29
15
I
I
.,1.
2.0 ± 0.4,
MSMSOC86
MSMSOCSS
,.
TI ~~~l
.. ~
.128
J~·65±0.~~tO.11
,
I
·8.45 ± 0.2
9.5 ± 0.2
J ,0.5~?
12.0 ± 0.4
",.
I
11
DATA SHEET
CPU
OKI
semiconductor
MSM80C85A RS/GS
8-BIT CMOS MICROPROCESSOR
GENERAL DESCRIPTION
The MSM80C85A is a complete 8-bit parallel central processor implemented in silicon gate C-MOS technology.
It is designed with same processing speed and lower power consumption compared with MSM8085A, thereby
offering a high level of system integration.
The MSM80C85A uses a multiplexed address/data bus. The address is split between the 8-bit address bus and
the 8-bit data bus. The on-chip address latches of MSM81 C55/MSM83C55 memory products allow a direct interface
with the MSM80C85A.
FEATURES
• Four Vectored Interrupt Inputs (One is non-maskablel
Plus the 8080A-compatible interrupt.
• Serial I n/Serial Out Port
• Decimal, Binary and Double Precision Arithmetic
• Addressing Capability to 64K Bytes of Memory
•
•
•
•
•
•
Low Power Dissipation: 50 mW TYP
Single +4 to +6 V Power Supply
-40 to +85°C, Operating Temperature
1.3Jllnstruction Cycle
On-Chip Clock Generator (with External Crystal)
On-Chip System Controller; Advanced Cycle Status
Information Available for Large System Control
• TTL Compatible
FUNCTIONAL BLOCK DIAGRAM
INTA
RST6.5
TRAP
C REG (8)
E REG (8)
]
L REG (8)
Power { _ +5V
SupplV
GND
A 1S -As
ADDRESS BUS
16
AD7-ADO
ADDRESS/DATA BUS
- - - - - - - - - - - - - - - - - - . CPU· MSM80C85ARS/GS •
PIN CONFIGURATION
MSM80C85ARS (Top View)
40 Lead Plastic DIP
XI
X2
HLDA
RESET OUT
eLK (OUT)
SOD
READY
TRAP
RST1.5
3
[I
101M
RST6.5
RST5.5
WR
ALE
So
AlS
AI3
AI2
An
AIO
A9
As
MSM80C85AGS (Top View)
44 Lead Plastic Flat Package
44434241403938 37363534
TRAP
RST7.5
~o
RST6.5
3
33
READY
101M
SI
RST5.5
RD
INTR
29
WR
INTA
28
ALE
ADo
ADI
27
So
26
AI5
AD2
10
25
24
AI4
AD3
N.C
11
23
12 13 14 15 16 17 18 19 20 21 22
AI2
AI3
17
• CPU· MSM80C85ARS/GS •
MSM80C85A FUNCTIONAL PIN DEFINITION
The following describes the function of each pin:
Symbol
Function
As-A1S
(Output,3-state)
Address Bus: The most significant 8-bits of the memory address or the 8-bits of the I/O
address, 3-stated during Hold and Halt modes and during RESET.
ADo-AD,
(Input/Output)
3-state
Multiplexed Address/Data Bus: Lower 8-bits of the memory address (or I/O address)
appear on the bus during the first clock cycle (T state) of a machine cycle. It then
becomes the data bus during the second and third clock cycles.
ALE
(Output)
Address Latch Enable: It occurs during the first clock state of a machine cycle and enables
the address to get latched into the on-chip latch of peripherals. The falling edge of ALE
is set to guarantee setup and hold times for the address information. The falling edge
of ALE can also be used to strobe the status information ALE is never 3-stated.
So, S1,10/M
(Output)
Machine cycle status:,
States
10/M S1 So
0
0 1 Memory write
0
1 0 Memory read
1
0 1 I/O write
1
1 0 I/O read
0
1 1 Opcode fetch
-
10/M S1 So
1
1
0
1
0
x
x
x
x
Interrupt
Halt . =
Hold
Reset x =
States
Acknowledge
3-5tate
(high impedance)
unspecified
S1 can be used as an advanced R/W status. 10/M, SO and S1 become valid at the beginning
of a machine cycle and remain stable throughout the cycle. The falling edge of ALE may
be used to latch the state of these lines.
RD
(Output,3-state)
READ control: A low level on RD indicates the selected memory or I/O device is to be
read and that the Data Bus is available for the data transfer, 3-stated during Hold and Halt
modes and during RESET.
WR
(Output,3-state)
WRITE control: A low level on WR indicates the data on the Data Bus is to be written
into the selected memory or I/O location. Data is set up at the trailing edge of WR,
3-stated during Hold and Halt modes and during RESET.
READY
(Input)
If READY is high during a read or write cycle, it indicates that the memory or peripheral
is ready to send or receive data. If READY is low, the cpu will wait an integral number
of clock cycles for READY to go high before comp·leting the read or write cycle READY
must conform to specified setup and hold times.
HOLD
(Input)
HOLD indicates that another master is requesting the use of the address and data buses.
The cpu, upon receiving the hold request, will relinquish the use of the bus as soon as the
completion of the current bus transfer. Internal processing can continue. The processor
can regain the bus only after the HOLD is removed. When the HOLD is acknowledged,
the Address, Data, RD, WR, and 10/M lines are 3-stated.
HLDA
(Output)
HOLD ACKNOWLEDGE: Indicates that the cpu has received the HOLD request and
tl:1at it will relinquish the bus in the next clock cycle. H LOA goes low after the Hold
request is removed. The cpu takes the bus one half clock cycle after HLDA goes low.
INTR
(Input)
INTERRUPT REQUEST: Is used as a general purpose interrupt. It is sampled only during
the next to the last clock cycle of an instruction and during Hold and Halt states. If it is
active, the Program Counter (PC) will be inhibited from incrementing and an INTA will be
issued. During this cycle a RESTART or CALL instruction can be inserted to jump to the
interrupt service routine. The INTR is enabled and disabled by software. It is disabled by
Reset and immediately after an interrupt is accepted.
INTA
(Output)
INTERRUPT ACKNOWLEDGE: Is used instead of (and has the same timing as) RD
during the instruction cycle after an INTR is accepted.
RST 5.5
RST6.5
RST 7.5
(Input)
RESTART INTERRUPTS: These three inputs have the same timing as INTR except they
cause an internal REST ART to be automatically inserted.
The priority of these interrupts is ordered as shown in Table 1. These interrupts have a
higher priority than INTR. In addition, they may be individually masked out using the
SIM instruction.
TRAP
Trap interrupt is a nonmaskable RESTART interrupt. It is recognized at the same timing
as INTR or RST 5.5-7.5. It is unaffected by any mask or Interrupt Disable. It has the
highest priority of any interrupt. (See Table 1.)
(lnput~
18
----------------~--.--. CPU· MSM8OC85ARS/GS •
Symbol
Function
RESET IN
(Input)
Sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops.
The data and address buses and the control lines are 3-stated during RESET and because
of the asynchronous nature of RESET, the processor's internal registers and flags may be
altered by RESET with unpredictable results. RESET IN is a Schmitt-triggered input,
allowing connection to an R-C network for power-on RESET delay. The cpu is held in
the reset condition as long as RESET IN is applied.
RESET OUT
(Output)
Indicates cpu is being reset. Can be used as a system reset. The signal is synchronized to
the processor clock and lasts an integral number of clock periods.
Xl, X2
(Input)
Xl and X2 are connected to a crystal to drive the internal clock generator. Xl can also
be an external clock input from a logic gate. The input frequency is divided by 2 to give
the processor's internal operating frequency.
CLK
(Output)
Clock Output for use as a system clock. The period of CLK is twice the Xl, Xl input
period.
SID
(Input)
Serial input data line. The data on this line is loaded into accumulator bit 7 whenever
a RIM instruction is executed.
SOD
(Output)
Serial output data line. The output SOD is set or reset as sPecified by the SIM instruction.
VCC
GND
+5 volt supply.
Ground Reference.
Table 1 Interrupt Priority, Restart Address, and Sensitivity
Name
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR
Not.:
(1)
(2)
Priority
Address Branched To (1)
When Interrupt Occurs
1
24H
2
3CH
34H
2CH
(2)
3
4
5
Type Trigger
Rising edge and high leviti until
sampled.
Rising edge (latched).
High level until sampled.
High level until sampled.
High level until sampled.
The processor pushes the PC on the stack before branching to the indicated address.
The address branched to depends on the instruction provided to the cpu when the interrupt is acknowledged.
19.
• CPU· MSM80C85ARS/GS •
FUNCTIONAL DESCRIPTION
a
1
The MSMSOCS5A is a complete 8-bit parallel
central processor. It is designed with silicon gate
C-MOS technology and requires a single +5 volt supply.
Its basic clock speed is 3MHz, thus improving on the
present 8080A's performance with higher system speed.
Also it is designed to fit into a minimum system of three
IC's: The cpu (MSM80C85A), a RAM/IO (MSMS1C55),
and a ROM/IO chip (MSMS3C55).
The MSMSOC85A: has twelve addressable 8-bit
registers. Four of them can function only as two 16-bit
register pairs. Six others can be used interchangeably
as S-bit regist~rs or a 16-bit register pairs. The MSM8OC85A register set is as follows:
Mnemonic
Register
ACCor A
Accumulator
Program Counter
PC
BC, DE, HL General-Pu rpose
Registers;
data pointer (H L)
Stack Pointer
SP
Flag Register
Flags or F
Contents
S-bits
16-bit address
S-bit x 6 or
16-bits x 3
16-bit address
5 flags (S·bit space)
The MSMaOCS5A uses a multiplexed Data Bus.
The address is split between the higher S-bit Address
Bus and the lower S-bit Address/Data Bus. During
the first T state (clock cycle) of a machine cycle the low
order address is sent out on the Address/Data Bus.
These lower S-bits may be latched externally by the
Address Latch Enable signal (ALE). During the rest of
the machine cycle the data bus is used for memory or
I/O data.
The MSM80CS5A provides RD, WR, So, S1 and
10/M signals for bus control. An Interrupt Acknowledge signal (lNTA) is also provided. Hold and all
Interrupts are synchronized with the processor's internal
clock. The MSM80CS5A also provides Serial Input Data
(SID) and Serial Output Data (SOD) lines for a simple
serial interface.
In addition to these features, the MSMSOCS5A has
three maskable, vector interrupt pins and one nonmaskable TRAP interrupt.
INTERRUPT AND SERIAL I/O
The MSM8OCS5A has 5 interrupt inputs: INTR,
RST 5.5, RST 6.5. RST 7.5, and TRAP, INTR is identical in functi·~r· (0 ttl'e 8080A INT. Each of the three
RESTART inputs, 5.5,.6.5, and 7.5, has a programmable mask. TRAP is also a RESTART interrupt but
it is nonmaskable.
The three maskable interrupts cause the internal
20
execution of RESTART (saving the program counter
in the stack and branching to the RESTART address)
if the interrupts are enabled and if the interrupt mask is
not set. The nonmaskable TRAP causes the internal
execution of a RESTART vector independent of the
state of the interrupt enable or masks. (See Table 1.)
There are two different types of inputs in the
restart interrupts. RST 5.5 and RST 6.5 are high
level-sensitive like INTR (and INT on the 8080A) and
are recognized with the same timing asJNTR. RST 7.5
is rising edge-sensitive.
.
For RST 7.5, only a pulse is required to set an
internal flip-flop which generates the internal interrupt
request. The RST 7.5 request flip-flop remains set until
the request is serviced. Then it is reset automatically.
This flip-flop may also be reset by using the SIM instruction or by issuing a RESET IN to the MSM80CS5A.
The RST 7.5 internal flip-flop will be set by a pulse on
the RST 7.5 pin even when the RST 7.5 interrupt is
masked out.
The interrupts are arranged in a fixed priority that
determines which interrupt is to be recognized if more
than one is pending as follows: TRAP--highest priority,
RST 7.5, RST 6.5, RST 5.5, INTR-Iowest priority.
This priority scheme does not take into account the
priority of a routine that was started by a higher priority interrupt. RST 5.5 can interrupt an RST 7.5 routine
if the interrupts are re-enabled before the end of the
RST 7.5 routine.
The TRAP interrupt is useful for catastrophic
events such as power failure or bus error. The TRAP
input is recognized just as any other interrupt but has
the highest priority. It is not affected by any flag or
mask. Tile TRAP input is both edge and level sensitive.
The TRAP input must go high and remain high until
it is acknowledged. It will not be recognized again
until it goes low, then high again. This a90ids any false
triggering due to noise or logic glitches. Figure 3 illustrates the TRAP interrupt request circuitry within the
MSMSOCS5A. Note that the servicing of any interrupt
(TRAP, RST 7.5, RST 6.5, RST 5.5, INTR) disables all
future interrupts (except TRAPs) until an EI instruction
is executed.
The TRAP interrupt is special in that it disables
interrupts, but preserves the previous interrupt enable
status. Performing the first RIM instruction following
a TRAP interrupt allows you to determine whether
interrupts were enabled or disabled prior to the TRAP.
AII"subsequent RIM instructions provide current interrupt enable status. Performing a RIM instruction following INTR orRST 5.5-7.5 will provide current
interrupt Enable status, revealing that interrupts are
disabled.
The serial I/O system is also controlled by the RIM
and SIM instructions. SID is read by RIM, and SIM
sets the SOD data.
- - - - - - - - - - - - - - - - - - . CPU· MSM8OC85ARS/GS •
EXTERNAL
TRAP
INTERRUPT
REQUEST
TRAP
RESET IN
INSIDE THE MSMSOC85A
SCHMITT
TRIGGER
RESET
INTERNAL
TRAP
ACKNOWLEDGE
Figure 3 Trap and RESET IN Circuit
DRIVING THE Xl and Xl INPUTS
Drive level: 10 mW
Frequency tolerance: ±.005% (suggested)
Note the use of the capacitors between Xl, Xl and
ground. These capacitors are required to assure oscillator startup at the correct freql!ency.
Figure 4 shows the recommended clock driver
circuits. Note in 8 that puJlup resistor is required to
assure that the high level voltage of the input is at least
4V.
For driving frequencies up to and including 6 MHz
you may supply the driving signal to Xl and leave Xl
open-circuited (Figure 48). To prevent self-oscillation
of the MSM80C85A, be sure that Xl is not coupled
back to Xl through the driving circuit.
You may drive the clock inputs of the MSMSOCS5A with a crystal, or an external clock source. The
driving frequency must be at least 1 MHz, and must be
twice the desired internal clock frequency; hence, the
MSM80C85A is operated with a 6 MHz cyrstal (for
3 MHz clock!. If a crystal is used, it must have the following characteristics:
Parallel resonance at twice the clock frequency
desired
CL (load capacitance) ~ 30 pF
C (shunt capacitance) ~ 7 pF
RS (equivalent shunt resistance) ~ 75 ohms
s
A.
Quartz Crystal Clock Driver
B.
Xl
----,
80CS5A
I
I
*CINT
I
1-6 MHz Input Frequency External Clock
Drive Ch:cuit
VIH > O.SVCC
High tJrn_e > 60ns
Low ti me > 60ns
= 15pF
XL __ J
_____________
2~
100pF Capacitor required for crystal frequency < 4MHz.
50pF Capacitor required for crystal frequency:;:: 4 MHz.
* Xl Left floating
Figure 4 Clock Driver Circuits
21
• CPU· MSM80C85ARS/GS •
BASIC SYSTEM TIMING
The MSM80C85A has a multiplexed Data Bus.
ALE is used as a strobe to sample the lower 8-bits of
address on the Data Bus. Figure 5 shows an instruction
fetch. memory read and I/O write cycle (as would occur
during processing of the OUT instruction). Note that
during the I/O write and read cycle that the I/O port
address is copied on both the upper and lower half of
the address.
There are seven possible types of machine cycles.
Which of these seven takes place is defined by the
status of the three status lines (loiM. S .. So) and the
three control signals (RD. WR. and INTA). (See Table
2.1 The status line can be used as advanced controls
(for device selection, for example), since they become
active at the T I state, at the outset of each machine
cycle. Control lines RD and WR become active later,
at the time when the transfer of data is to take place,
so are used as command lines.
A machine cycle normally consists of three T
states, with the exception of OPCODE FETCH, which
normally has either four or six T states. (unless WAIT
or HOLD states are forced by the receipt of READY
or HOLD inputs). Any T state must be one of ten
possible states, shown in Table 3.
Table 2 MSM80C85A Machine Cycle Chart
Status
Machine Cycle
Control
SI
So
RD
WR
INTA
Opcode Fetch
(OF)
0
1
1
0
1
1
Memory Read
(MR)
0
1
0
0
1
1
Memory Write
(MW)
0
0
1
1
0
1
I/O Read
(lOR)
1
1
0
0
1
1
I/O Write
(lOW)
1
0
1
1
0
1
Acknowledge of INTR (INA)
1
1
1
1
1
0
0
1
0
1
1
1
1
TS
1
1
0
0
1
TS
1
TS
1
1
(BI):DAD
ACK.OF
RST, TRAP
HALT
Bus Idle
10/M
Table 3 MSM80C85A Machine State Chart
Status & Buses
Control
Ma.:hine State
SI,SO
10/M
As-Als
ADo-AD,
RD,WR
INTA
TI
X
X
X
X
1
1
1(1)
T2
X
X
X
X
X
X
0
TWAIT
X
X
X
X
X
X
0
T3
X
X
X
X
X
X
0
T4
1
X
TS
1
1
0
Ts
1
X
TS
1
1
0
T6
1
o (2)
o (2)
o (2)
X
TS
1
1
0
TRESET
X
TS
TS
TS
TS
1
0
THALT
0
TS
TS
TS
TS
1
0
THOLD
X
TS
TS
TS
TS
1
0
0= Logic "0"
1 == Logic "1"
TS = High Impedance
X = Unspecified
Notes: (1)
(2)
22
ALE
ALE not generated during 2nd and 3rd machine cycles of DAD instruction.
10/M = 1 during T 4 -T 6 of I NA machine cycle.
- - - - - - - - - - - - - - - - - - . CPU· MSM80C85ARS/GS •
CLK
ALE
loiM
STATUS
SlS0 (FETCH)
10 (READ)
01 WRITE
11
Figure 5· MSMSOC85A Basic System Timing
Table 4 Absolute Maximum Ratings
Ambient Temperature under Bias .. .
Storage Temperature . . . . . . . . . . .
Supply Voltage Respect to Ground ..
Input Voltage Respect to Ground
Power Dissipation . . . . . . . . . . . .
-40°C to + 85°C
_55°C to + 150°C
-0.3V to + 7.0V
-0.3V to VDD + 0.3V
1.0 Watt (DIP)
0.7 Watt (FLAT)
Note: Stresses above .those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
23
• CPU· MSM80C85ARS/GS • - - - - - - - - - - - - - - - - - D.C. CHARACTERISTICS
(TA = -40°C to + 85°C; VCC = 5V ±10%; unless otherwise specified)
Symbol
Min.
Input low Voltage
Vil
-0.3
Input High Voltage
VIH
2.2
Parameter
Output low Voltage
Typ.
VOL
Max.
Units
+0.8
V
VCC+0.3
V
0.45
V
IOl = 2mA
V
IOH =-400~
2.4
11
Output High Voltage
VOH
IOH =-40~
4.2
Input leak
III
-10
Output leak
IlO
-10
10
#J.A
OV ~ VIN ~ VCC
OV 5 VOUT ~ VCC
10
#J.A
+0.8
V
VCC +0.3
V
I
Input low level, RESET
VllR
Input High level, RESET
VIHR
3.0
VHY
0.25
Hysteresis, RESET
Power Supply Current
-0.3
V
10
22
mA
10
17
mA
5
6
V
ICC
Power Supply Voltage
Test Conditions
VCC
4
VCC = 4.5V to 5.5V
tCYC=
TA = -40°C to +85°C 320ns
VCC =4.75V to 5.25V Reset
Active
T A = O°C to +85°C
A.C. CHARACTERISTICS
(TA = -40°C to 85°C; VCC = 5V ±10%)
Parameter
24
Symbol
80C85A
Units
Min.
Max.
320
2000
C lK Cycle Period
tCYC
ClK low Time
tl
80
ClK High Time
t2
120
ClK Rise and Fall Time
t r , tf
XI Rising to ClK Rising
tXKR
ns
ns
ns
30
ns
30
120
ns
30
150
ns
XI Rising to ClK Falling
tXKF
AS-IS Valid to leading Edge of Control (1)
tAC
270
AO-7 Valid to leading Edge of Control
tACl
240
AO-IS Valid to Valid Data In
tAD
Address Float After leading Edge of RD (lNTA)
tAFR
AS-IS Valid Before Trailing Edge of AlE(1)
tAL
AO-7 Valid Before Trailing Edge of ALE
tAll
ns
ns
575
0
ns
ns
115
ns
90
ns
READY Valid from Address Valid
tARY
Address (As-A ls ) Valid After Control
tCA
120
220
ns
ns
Width of Control low (RD, WR, INTA)
tcc
400
ns
Trailing Edge of Control to leading Edge of ALE
tCl
50
ns
Data Valid to Trailing Edge of WR
tow
420
H lOA to Bus Enable
tHABE
210
ns
Bus Float After HlDA
tHABF
210
ns
ns
.-
- - - - - - - - - - - - - - - - - - . CPU· MSM80C85ARS/GS •
A.C. CHARACTERISTICS cont'd
Parameter
aoca5A
Symbol
Units
Min.
HLDA Valid to Trailing Edge of CLK
110
tHACK
HOLD Hold Time
Max.
ns
tHDH
0
HOLD Setup Time to Trailing Edge of CLK
tHDS
170
ns
INTR Hold Time
tlNH
0
ns
INTR. RST. and TRAP Setup Time to Falling Edge
ofCLK
tiNS
160
ns
Address Hold Time After ALE
tLA
100
ns
ns
ns
Trailing Edge of ALE to Leading Edge of Control
ns
tLC
130
ALE Low During CLK High
tLCK
100
ALE to Valid Data During Read
tLDR
460
ns
ALE to Valid Data During Write
tLOW
200
ns
ALE Width
tLL
140
ns
ALE to READY Stable
tLRY
Trailing Edge of RDto Re-Enabling of Address
tRAE
RD (or INTA) to Valid Data
tRD
Control Trailing Edge to Leading Edge of Next Control
tRV
Data Hold Time After RD INTA (7)
tROH
0
ns
READY Hold Time
tRYH
0
ns
ns
110
300
400
READY Setup Time to Leading Edge of CLK
tRYS
110
two
100
LEADING Edge of WR to Data Valid
.twOL
Notes:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
ns
150
Data Valid After Trailing Edge of WR
ns
ns
ns
ns
.40
ns
As-A15 address Specs apply to 101M. SO. and S1 except As-A15 are undefined during T4-T 6 of OF
cycle whereas 101M. SO. and S1 are stable.
Test conditions: tCYC 320ns CL 150pF
For all output timing where CL = 150pF use the following correction factors:
25pF::;; CL < 150pF: -o.10ns/pF
150pF < C L ::;; 300pF: +0.30ns/pF
Output timings are measured with purely capacitive load.
All timings are measured at output voltage VL = o.av. VH = 2.2V. and 1.5V with 10ns rise and fall time
on inputs.
To calculate timing specifications at other values of tCYC use Table 7.
Data hold time is guaranteed under all loading conditions.
=
=
Input Waveform for A.C. Tests:
2.4
------X::::: ~~~TS ~:::X. .______
0.45 _ _ _ _ _- J
-
25
• CPU· MSM80C85ARS/GS • - - - - - - - - - - - - - - - - - Table 7 Bus Timing Specification as a T eve Dependent
MSM80C85A
tAL
-
(1/2)T - 45
MIN
tlA
-
(1/2)T - 60
MIN
tll
-
(1!2)T - 20
MIN
tlCK
-
(1/2)T - 60
MIN
tlC
-
(1/2)T - 30
MIN
tAD
-
(5/2 + N)T - 225
MAX
(3/2 + N)T -180
MAX
(1/2)T - 10
MIN
tRD
tRAE
teA
tow
(1/2)T - 40
MIN
(3/2 + N)T - 60
MIN
two
-
(1/2)T,- 60
MIN
tee
-
(3/2 + N)T - 80
MIN
tCl
tARV
tHACK
tHABF
tHABE
tAC
tl
t2
tRV
tlDR
-
(1/2)T-110
MIN
-
(3/2)T - 260
MAX
(1/2)T - 50
MIN
(1/2)T + 50
MAX
(1!2)T+ 50
MAX
(2/2)T - 50
MIN
(1/2)T - 80
MIN
(1/2)T - 40
MIN
(3/2)T -80
MIN
(2+N)T -180
MAX
Note: N is equal to the total WAIT states.
T= tcvc
Xl INPUT
ClK,
OUTPUT
Figure 6 Clock Timing Waveform
26
- - - - - - - - - - - - - - - - - - . CPU· MSM80C85ARS/GS •
READ OPERATION
elK
\
As-A1S
T2
/
\
Tl
I
ADDRESS
9
ADo-AD7
ALE
tRD
tee
RDINTA
WRITE OPERATION
ADDRESS
DATA OUT
~--------tDW--------~
ALE
-"II--twDl
--+---+---~ ' - " - - - - - - - t e e - - - - - - t
r---+----
21
• CPU· MSM80C85ARS/GS • - - - - - - - - - - - - - - - - - -
Read operation with Wait Cycle (Typical)same READY timing applies to WRITE operation
TWAIT
---'"
ClK
AS-AIS
ALE
READY
Note: READY must remain stable during setup and hold times.
Figure 7 MSMSOC85A Bus Timing, Wit", and Without Wait
HOLD OPERATION
elK
HOLD
HlDA
BUS
(ADDRESS,
CONTROLS)
Figure 8 MSMSOC85A Hold Timing
28
- - - - - - - - - - - - - - - - - - . CPU· MSM80C85ARS/GS •
BUS FLOATING (1)
ALE
tHABE--I--+-
HOLD
\
tHDS
HLDA
....,I
if
HDH
--------------~
tHACK
Note: (1)
I
tHABF
101M is also floating during this time.
Figu.. 9 MSM80C85A Interrupt MId Hold Timing
29
• CPU· MSM80C85ARS/GS • - - - - - - - - - - - - - - - - - Table 8
Instruction Set Summary
Instructiun Code (1)
Mnemonic
11
I
MOVE, LOAD,
MOVr1 r2
MOVMr
MOVrM
MVI r
MVIM
LXIB
LXI 0
LXIH
LXI SP
STAX B
STAXD
LoAXB
LDAXo
STA
LOA
SHLD
LHLo
XCHG
Description
AND STORE
Move register to register
Move register to memory
Move memory to register
Move immediate register
Move immediate memory
Load immediate register Pair B & C
Load immediate register Pair 0 & E
Load immediate register Pair H & L
Load immediate stack pointer
Store A indirect
Store A indirect
Load A indirect
Load A indirect
Store A direct
Load A di rect
Store H & L direct
Load H & L direct
Exchange 0 & E H& L registers
Clock (2)
Cycles
07
06
Os
04
03
02
01
Do
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
S
S
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
S
S
1
1
1
S
S
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
7
7
7
10
10
10
10
10
7
7
7
7
13
13
16
16
b
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
4
4
STACK OPS
PUSH B
PUSH 0
PUSH H
PUSH PSW
POPB
POP 0
POP H
POPPSW
XTHL
SPHL
Push register Pair B & C on stack
Push register Pair 0 & E on stack
Push register Pair H & L on stack
Push A and Flags on stack
Pop register Pair B & C off stack
Pop register Pair 0 & E off stack
Pop register Pair H & L off stack
Pop A and F lags off stack
Exchange top of stack H & L
H & L to stack pointer
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
12
12
12
12
10
10
10
10
16
6
JUMP
JMP
JC
JNC
JZ
JNZ
JP
JM
JPE
JPO
PCHL
Jump unconditional
Jump on carry
Jump on no carry
Jump on zero
Jump on no zero
Jump on positive
Jump on minus
Jump on parity even
Jump on parity odd
H & L to program counter
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
q
0
0
0
0
1
1
1
1
1
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
1
10
7/10
7/10
7/10
7/10
7/10
7/10
7/10
7/10
6
CALL
CALL
CC
CNC
CZ
CNZ
CP
CM
CPE
CPO
Call
Call
Call
Call
Call
Call
Call
Call
Call
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
18
9/18
9/18
9/18
9/18
9/18
9/18
9/18
9/18
.
30
unconditional
on carry
on no carry
on zero
on no zero
on positive
on minus
on parity even
on parity odd
0
0
0
0
0
1.
1
1
1
0
- - - - - - - - - - - - - - - - - - . CPU· MSM80C85ARS/GS •
Table 8
Instruction Set Summary cont'd
Instruction Code( 1)
07
06
Os
04
03
02
01
Do
Clock(2),
Cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
'1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
10
6/12
6/12
6/12
6/12
6/12
6/12
6/12
6/12
Description
Mnemonic
RETURN
RET
RC
RNC
RZ
RNZ
RP
RM
RPE
RPO
Return
Return
Return
Return
Return
Return
Return
Return
Return
RESTART
RST
Restart
1
1
A
A
A
1
1
1
12
INPUT/OUTPUT
IN
Input
OUT
Output
1
1
1
1
0
0
1
1
1
0
0
0
1
1
1
1
10
10
INCREMENT AND DECREMENT
INR r
Increment register
OCR r
Decrement register
INRM
Increment memory
DCRM
Decrement memory
INX B
Increment B & C registers
INX 0
Increment 0 & E registers
Increment H & L registers
INX H
INXSP
Increment stack pointer
DCX B
Decrement B & C
Decrement 0 & E
DCXD
DCX H
Decrement H & L
Decrement stack pointer
DCXSP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D
1
1
0
0
1
1
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1
1
4
4
1
1
0
1
0
1
0
1
0
1
D
0
0
0
0
0
0
1
1
1
1
ADD
ADDr
ADC r
ADDM
ADCM
ADI
ACI
DAD B
DAD 0
DAD H
DAD SP
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
S
S
1
1
1
1
0
0
0
0
S
S
1
1
1
1
0
0
0
0
S
S
0
0
0
0
1
1
1
1
10
10
10
10
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0'
0
0
0
1
1
1
1
1
1
0
1
0
1
0
1
S
S
1
1
1
1
S
S
1
1
1
1
S
S
0
0
0
0
4
4
7
7
7
7
on
on
on
on
on
on
on
on
carry
no carry
zero
no zero
positive
minus
parity even
parity odd
I
SUBTRACT
SUB r
SBB r
SUBM
SBB M
SUI
SBI
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
register to A
register to A with carry
memory to A
memory to A with carry
immediate to A
immediate to A with carry
B & C to H & L
D & E to H & L
H & L to H & L
stack pointer to H & L
Subtract
Subtract
Subtract
Subtract
Subtract
Subtract
borrow
register from A
register from A with borrow
memory from A
memory from A with borrow
immediate from A
immediate from A with
10
10
6
6
6
6
6
6
6
6
4
4
7
7
7
7
31
• CPU· MSM80C85ARS/GS • - - - - - - - - - - - - - - - - - Table 8
Mnemonic
II
I
Instruction Set Summary cont'd
Description
Instruction Code (1)
Clock(2)
Cycles
07
06
Os
04
03
02
01
Do
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
S
S
S
S
S
S
S
S
S
S
S
S
4
4
4
4
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
7
7
7
7
7
7
7
7
LOGICAL
ANAr
XRAr
ORA r
eMP r
MilA M
XRAM
ORAM
CMPM
ANI
XRI
ORI
CPI
And register with A
Exclusive Or register with A
Or register with A
Compare register with A
And memory with A
Exclusive Or memory with A
Or memOry with A
Compare memory with A
And immediate with A
Exclusive Or immediate with A
Or immediate with A
ComPare immediate with A
1
1
1
1
1
ROTATE
RLe.
RRC
RAL
RAR
Rotate
Rotate
Rotate
Rotate
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
4
4
4
4
SPECIALS
CMA
STC
CMC
DAA
Complement A
Set carry
Complement carry
Decimal adjust A
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
4
4
4
4
01
Enable Interrupts
Disable Interrupt
1
1
NOP
HLT
RIM
SIM
Halt
Read Interrupt Mask
Set Interrupt Mask
1
1
0
0
0
0
1
1
0
1
1
1
1
1
0
1
0
1
1
0
0
0
0
0
0
0
0
1
0
0
1
1
0
1
0
0
1
1
0
0
0
0
4
4
4
5
4
4
CONTROL
EI
Notes:
left
right
left through carry
right through carry
No~peration
(1)
(2)
32
A
A
A
A
1
1
o.
1
0
0
1
1
1
DOD or SSS. B 000. C 001.0010. E 011. H 100. L 101. Memory 110. A 111.
Two possible cycle times, (6112) indicate instruction cycles dependent on condition flags.
OKI semiconductor
MSM80C85A-2RS/GS
8-BIT CMOS MICROPROCESSOR
GENERAL DESCRIPTION
The MSM80C85A-2 is a complete 8-bit parallel central processor implemented in silicon gate C-MOS technology
and compatible with MSM80C85A.
It is designed with higher processing speed (max. 5 MHz) and lower power consumption compared with
MSM80C85A and power down mode is provided, thereby offering a high level of system integration.
The MSM80C85A-2 uses a multiplexed address/data bus. The address is split between the 8-bit address bus and
the 8-bit data bus. The on-chip address latches a MSM81 C55-5 memory products allow a direct interface with the
MSM80C85A-2.
FEATURES
• Power down mode
• Low Power Dissipation: 50mW TYP
• Single +3 to +6 V Power Supply
• -40 to +85°C, Operating Temperature
• Compatible with MSM80C85A
• O.~ Instruction Cycle (VCC = 5V)
• Four Vectored Interrupt Inputs (One is non-maskable)
Plus the 8080A-compatible interrupt.
• Serial I n/Serial Out Port
• Decimal, Binary and Double Precision Arithmetic
• Addressing Capabil ity to 64K Bytes of Memory
·TTL Compatible
• On-Chip Clock Generator (with External Crystal)
• On-Chip Syst~m Controller; Advanced Cycle Status
Information Available for Large System Control
FUNCTIONAL BLOCK DIAGRAM
C REG (B)
E REG (B)
L REG (B)
Power {_+5V
Supply
PROGRAM COUNTER (16)
-GND
x,
X,
A1s-A.
ADDRESS BUS
AD, -ADo
ADDRESS/DATA BUS
33
• CPU· MSM80C85A-2RS/GS • - - - - - - - - - - - - - - - - PIN CONFIGURATION
MSM80C85A-2 RS (Top View)
40 Lead Plastic DIP
Vec
Xl
X2
HOLD
RESET OUT
HLDA
ClK (OUT)
SOD
RESET IN
SID
~
TRAP
READY
RST7.5
101M
RST6.5
Sl
RST5.5
RD
INTR
WR
INTA
ALE
ADo
ADI
So
A 1S
AD:a
Al4
AD]
A13
AD4
All
ADs
All
AD6
A 10
AD?
A9
GND
As
I-
::>
o
MSM80C85A-2 GS (Top View)
44 Lead Plastic Flat Package
I-
w
g g ~a::
VJ
TRAP
:J)
4443424140393837363534
1
33
RST7.5
2
RST6.5
3
RST5.5
0
loiM
Sl
RD
~
4
31
30
INTR
5
29
iN'TA
6
28
ALE
ADo
ADI
7
8
27
So
9
26
25
A 1S
AD2
AD3
10
24
N'C
11
23
12 13 14 15 16 17 18 19 20 21 22
Al3
All
... 0 U
0 00 ozu«
« « « « <9 >
'GO
34
READY
32
~
-i «: uZ.
Al4
- - - - - - - - - - - - - - - - - . CPU· MSM80C85A-2RS/GS •
MSM80C85A-2 FUNCTIONAL PIN DEFINITION
The following describes the function of each pin:
Function
Symbol
As-AI5
(Output,3-state)
Address Bus: The most significant 8-bits of the memory address or the 8-bits of the I/O
address, 3-stated during Hold and Halt modes and during RESET.
ADo -AD,
(I nput/Output)
3-state
Multiplexed Address/Data Bus: Lower 8-bits of the memory address (or I/O address)
appear on the bus during the first clock cycle (T state) of a machine cycle. It then
becomes the data bus during the second and third clock cycles.
ALE
(Output)
Address Latch Enable: It occurs during the first clock state of a machine cycle and enables
the address to get latched into the on-chip latch of peripherals. The falling edge of ALE
is set to guarantee setup and hold times for the address information. The falling edge
of ALE can also be used to strobe the status information ALE is never 3-stated.
So, SI, 10/M
(Output)
Machine cycle status:
10/MSI SO
States
0
0 1 Memory write
1 0 Memory read
0
1
0 1 I/O write
1
1 0 I/O read
1 1 Opcode fetch
0
-
10/M SI So
1
1
0
1
0
x
x
x
x
States
Interrupt Acknowledge
Halt
= 3-state
(high impedance)
Hold
Reset x= unspecified
SI can be used as an advanced R/W status. 10/M, SO and SI become valid at the beginning
of a machine cycle and remain stable throughout the cycle. The falling edge of ALE may
be used to latch the state of these lines.
RD
(Output,3-state)
READ control: A low level on RD indicates the selected memory or I/O device is to be
read and that the Data Bus is available for the data transfer, 3.-stated du ring Hold and Halt
modes and during RESET.
WR
(Output, 3-state)
WR ITE control: A low level on WR indicates the data on the Data Bus is to be written
into the selected memory or I/O location. Data is set up at the trailing edge of WR,
3-stated during Hold and Halt modes and during RESET.
READY
(Input)
If READY is high during a read or write cycle, it indicates that the memory or peripheral
is ready to send or receive data. If READY is low, the cpu will wait an integral number
of clock cycles for READY to go high before completing the read or write cycle READY
must conform to specified setup and ho!d times.
HOLD
(Input)
HOLD indicates that another master is requesting the use of the address and data buses.
The cpu, upon receiving the hold request, will relinquish the use of the bus as soon as the
completion of the current bus transfer. Internal processing can continue. The processor
can regain the bus only after the HOLD is removed. When the HOLD is acknowledged,
the Address, Data, RD, WR, and 10/M lines are 3~stated. And status of power down is
controlled by HOLD.
HLDA
(Output)
HOLD ACKNOWLEDGE: Indicates that the cpu has received the HOLD request and
that it will relinquish the bus in the next clock cycle. HLDA goes low after the Hold
request is removed. The cpu takes the bus one half clock cycle after HLDA goes low.
INTR
(Input)
INTERRUPT REQUEST: Is used as a general purpose interrupt. It is sampled on during
the next to the last clock cycle of an instruction and during Hold and Halt states. If it is
active, the Program Counter (PC) will be inhibited from incrementing and an INTA will
be issued. During this cycle a RESTART or CALL instruction can be inserted to jump
to the interrupt service routine. The INTR is enabled and disabled by software. It is
disabled by Reset and immediately after an interrupt is accepted. Power down mode is
reset by INTR.
INTA
(Output)
INTERRUPT ACKNOWLEDGE: Is used instead of (and has the same timing as) RD
during the instruction cycle after an INTR is accepted.
RST 5.5
RST 6.5
RST 7.5
(Input)
RESTART INTERRUPTS: These three inputs have the same timing as INTR except
they cause an internal RESTART to be automatically inserted.
The priority of these interrupts is ordered as shown in Table 1. These interrupts have a
higher priority than INTR. In addition, they may be individually masked out using the
SIM instruction. Power down mode is reset by these interrupts.
TRAP
(Input)
Trap interrupt is a nonmaskable RESTART interrupt. It is recognized at the same timing
as INTR or RST 5.5-7.5. It is unaffected by any mask or Interrupt Disable. It has the
highest priority of any interrupt. (See Table 1.) Power down mode is reset by input of
TRAP.
35
• CPU • MSM80C85A-2RS/GS • - - - - - - - - - - - - - - - - Symbol
II
I
Function
RESET IN
(Input)
Sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops
and release power down mode. The data and address buses and the control lines are 3stated during RESET and because of the asynchronous nature of RESET, the processor's
internal registers and flags may be altered by RESET with unpredictable results. RESET
TN is a Schmitt-triggered input, allowing connection to an R-C network for power-on
RESET delay. The cpu is,held in the reset condition as long as RESET IN is applied.
RESET OUT
(Output)
Indicated cpu is b~ing reset. Can be used as a system reset. The signal is synchronized to
the processor clock and lasts an integral number of clock periods.
Xl, Xl
(Input)
Xl and Xl are connected to a crystal to drive the internal clock generator. Xl can also
be an external clock input from a logic gate. The input frequency is divided by 2 to give
the processor's internal operating frequency.
CLK
(Output)
Clock Output for use as a system clock. The period of CLK is twice the Xl , Xl input
period.
SID
(Input)
Serial input data line. The data on this line is loaded into accumulator bit 7 whenever
a RIM instruction is executed.
SOD
(Output)
Serial output data line. The output SOD is set or reset as specified by the SIM instruction.
VCC
+5 volts supply.
GND
Ground Reference.
Table 1 Interrupt Priority, Restart Address, and Sensitivity
Name
TRAP
1
Address Branched To (1)
When Interrupt Occurs
24H
Type Trigger
Rising edge and high level until
sampled.
RST 7.5
2
3CH
Rising edge (latched).
RST6.5
3
34H
High level until sampled.
RST 5.5
4
5
2CH
(2)
High level until sampled.
INTR
Notes: (1)
(2)
36
Priority
High level until sampled.
The processor pushes the PC on the stack before branching to the indicated address.
The address branched1to depends on the instruction provided to the cpu when the interrupt is acknowledged.
- - - - - - - - - - - - - - - - - . CPU· MSM80C85A-2RS/GS •
FUNCTIONAL DESCRIPTION
The MSMSOCS5A-2 is a complete S-bit parallel
central processor. It is designed with silicon gate
C-MOS technology and requires a single +5 volt supply.
Its basic clock speed is 5MHz, thus improving on the
present MSMSOCS5A's performance with higher system
speed and power down mode. Also it is designed
to fit into a minimum system of three IC's: The cpu
(MSMSOCS5A-2), RAM/IO (MSM81C55-5)
The MSMSOCS5A-2 has twelve addressable S-bit
register pairs. Six others can be used interchangeably
as S-bit registers or a l6-bit register pairs. The MSM80CS5A-2 register set is as follows:
a
Mnemonic
Register
Contents
Accumulator
8-bits
ACC or A
PC
Program Cou nter 16-bit address
BC, DE, HL General-Purpose 8-bit x 6 or
Registers;
16-bits x 3
data pointer (HL)
SP
Stack Pointer
16-bit address
Flags or F
Flag Register
5 flags (S-bit space)
The MSM80C85A-2 uses a multiplexed Data Bus.
The address is split between the higher 8-bit Address
Bus and the lower S-bit Address/Data Bus. During
the first T state (clock cycle) of a machine cycle the low
order address is sent out on the Address/Data Bus.
These lower S-bits may be latched externally by the
Address Latch Enable signal (ALE). During the rest of
the machine cycle the data bus is used for memory or
I/O data.
The MSM80CS5A-2 provides RD, WR, So, SI and
10/M signals for bus control. An Interrupt Acknowledge signal (lNTA) is also provided. Hold and all
Interrupts are synchronized with the processor's internal
clock. The MSMSOC85A-2 also provides Serial Input
Data (SID) and Serial Output Data (SOD) lines for a
simple serial interface.
In addition. to these features, the MSMSOCS5A-2
has three maskable, vector interrupt pins, one nonmaskable TRAP interrupt and power down mode with HALT
and HOLD.
INTERRUPT AND SERIAL I/O
The MSMSOCS5A-2 has 5 interrupt inputs: INTR,
RST 5.5, RST 6.5, RST 7.5, and TRAP, INTR is identical in function to the 80S0A INT. Each of the three
RESTART inputs, 5.5, 6.5, and 7.5, has a programmable mask. TRAP is also a RESTART interrupt but
it is nonmaskable.
The three maskable interrupts cause the internal
execution of RESTART (saving the program counter
in the stack and branching to the RESTART address)
if the interrupts are enabled and if the interrupt mask is
not set. The nonmaskable TRAP causes the internal
execution of a RESTART vector independent of the
state of the interrupt enable or masks. (See Table 1.)
There are two different types of inputs in the
restart interrupts. RST 5.5 and RST 6.5 are high
level-sensitive like INTR (and INT on the 80S0A) and
are recognized with the same thiming as INTR. RST
7.5 s rising edge-sensitive.
For RST 7.5, only a pulse is required to set an
internal flip-flop which generates the internal interrupt
request. The RST 7.5 request flip-flop remains set until
the request is serviced. Then it is reset au'tomatically.
This flip-flop may also be reset by using the SIM instruction or by issuing a RESET IN to the MSM80C85A.
The RST 7.5 internal flip-flop will be set by a pulse on
the RST 7.5 pin even when the RST 7.5 interrupt is
masked out.
The interrupts are arranged in a flixed priority that
determines which interrupt is to be reCognized if more
than one is pending as follows: TRAP-highest priority,
RST 7.5, RST 6.5, RST 5.5, INTR-Iowest priority.
This priority scheme does not take into account the
priority of a routine that was started by a higher priority interrupt. RST 5.5 can interrupt an RST 7.5 routine
if the interrupts are re-enabled before the end of the
RST 7.5 routine.
The TRAP interrupt is useful for catastrophic
events such as power failure or bus error. The TRAP
input is 'recognized just as any other interrupt but has
the highest priority. It is not affected by any flag or
mask. The TRAP input is both edge and level sensitive.
The TRAP input must go high and remain high until
it is acknowledged. It will not be recognized again
until it goes low, then high again. This avoids any false
triggering due to noise or logic glitches. Figure 3 illustrates the TRAP interrupt request circuitry within the
MSMSOC85A-2. Note that the servicing of any interrupt
(TRAP, RST 7.5, RST 6.5, RST 5.5, INTR) disables all
future interrupts (except TRAPs) until an EI instruction
is executed.
The TRAP interrupt is special in that it disables
interrupts, but preserves the previous interrupt enable
status. Performing the first R 1M instruction following
a TRAP interrupt allows you to determine whether
interrupts were enabled or disabled prior to the TRAP.
All subsequent R 1M instructions provide current interrupt enable status. Performing a R 1M instruction following INTR or RST 5.5-7.5 will provide current
Interrupt Enable status, revealing that Interrupts are
disabled.
The serial I/O system is also controlled by the RIM
and SIM instructions. SID is read by RIM, and SIM
sets the SOD data.
37
• CPU· MSM80C85A-2RS/GS • - - - - - - - - - - - - - - - - -
EXTERNAL
TRAP
INTERRUPT
TRAP
REQUEST
INSIDE THE MSM80C85A-2
R E_S_E_T_I_N-H SCHM I TT
TRIGGER
RESET
+5V
D
D
F/F
CLEAR
TRAP F.F
INTERNAL
TRAP
ACKNOWLEDGE
Figure 3 Trap and RESET IN Circuit
DRIVING THE Xl and X2 INPUTS
Drive level: 10 mW
Frequency tolerance: ±.005% (suggested)
Note the use of the capacitors between XI, X 2 and
ground. These capacitors are required to assure oscillator startup at the correct frequency.
Figure 4 shows the recommended clock driver
circuits. Note in B that pullup resistor is required to
assure that the high level voltage of the input is at least
4V.
For driving frequencies up to and including 6 MHz
you may supply the driving signal to XI and leave X 2
open-circuited (Figure 4B). To prevent self-oscillation
of the MSM80C85A-2; be sure that X 2 is not coupled
back to XI through the driving circuit.
You may drive the clock inputs of the MSM80C85A-2 with a crystal, or an external clock source. The
driving frequency must be at least 1 MHz, and must be
twice the desired internal clock frequency; hence, the
MSM80C85A-2 is operated with a 6 MHz crystal (for
3 MHz clock~. If a crystal is used, it must have the following characteristics:
Parallel resonance at twice the clock frequency
desired
C L (load capacitance) ~ 30 pF
Cs (shunt capacitance) ::;. 7 pF
RS (equivalent shunt resistance) ::;. 75 ohms
A.
Quartz Crystal Clock Driver
B.
---..,
XI
80C85A-2
1-10 MHz Input Frequency External Clock
Drive Circuit
VIH > 0.8VCC
High time> 40ns
Low time> 40ns
" I
I
=:=CINT
X~ __
= 15pF
J
33pF Capacitor required for crystal freql,lency 10 "'6.25 MHz.
50pF Capacitor required for crystal frequency 6.25 "'4 MHz.
100pF Capacitor required for crystal frequency <4 MHz.
Figure 4 Clock Driver Circuits
38
/
I
* X 2 Left floating
XI
- - - - - - - - - - - - - - - - - . CPU· MSM80C85A-2RS/GS •
BASIC SYSTEM TIMING
The MSM80C85A-2 has a multiplexed Data Bus.
ALE is used as a strobe to sample the lower 8-bits of
address on the Data Bus. Figure 5 shows an instruction
fetch, memory read and I/O write cycle (as would occur
during processing of the OUT instruction). Note that
during the I/O write and read cycle that the I/O port
address is copied on both the upper and lower half of
the address.
There are seven possible types of machine cycles.
Which of these seven takes place is defined by the
status of the three status lines (io/iiii', SI , So) and the
three control signals (RD, WR, and INTA). (See Table
2.) The status line can be used as advanced controls
(for device selection, for example), since they become
active at the T 1 state, at the outset of each machine
cycle. Control lines RD and WR become active later,
at the time when the transfer of data is to take place,
so are used as command lines.
A machine cycle normally consists of three T
states, with the exception of OPCODE FETCH, which
normally has either four Or six T states (unless WAIT
or HOLD states are forced by the receipt of READY
or HOLD inputs). Any T state must be one of ten
possible states, sllown in Table 3.
Table 2 MSM80C85A-2 Machine Cycle Chart
Status
Machine Cycle
10/M
Opcode Fetch
(OF)
0
Memory Read
(MR)
0
Memory Write
(MW)
0
Acknowledge of INTR (INA)
,
,
,
Bus Idle
0
I/O Read
(lOR)
I/O Write
(lOW)
(BI): DAD
ACK.OF
RST, TRAP
HALT
,
TS
SI
Control
,
RD
WR
,
INTA
0
0
0
,
,
,
,
,
0
,
,
,
,
,
,
,
So
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
0
0
TS
0
0
0
0
0
0
TS
,
0
Table 3 MSM80C85A-2 Machine State Chart
Status & Buses
Machine State
Control
SI,SO
10/M
A s -A 1S
ADo-AD7
X
X
,
ALE
X
,
INTA
X
Tz
X
X
X
X
X
X
0
TWAIT
X
X
X
X
X
X
0
T3
X
X
X
X
X
0
T4
0(2)
X
TS
0(2)
X
TS
T6
,
,
0(2)
X
TS
,
,
,
X
TRESET
X
TS
TS
TS
TS
THALT
0
TS
TS
TS
TS
THOLD
X
TS
TS
TS
TS
T1
,
Ts
o=
RD,WR
,
,
,
,
,
1
,
(,)
0
0
0
0
0
0
Logic "0"
, = Logic "'"
TS= High Impedance
X = Unspecified
Notes:
(1)
(2)
ALE not generated during 2nd and 3rd machine cycles of DAD instruction.
10/M = 1 during T4 ~ T6 of INA machine cycle.
39
• CPU· MSM80C85A-2RS/GS • - - - - - - - - - - - - - - - - -
II
I
101M
STATUS
SI So (FETCH)
10 (READ)
Figure 5. MSM80C85A-2 Basic System Timing
.40
01 WRITE
11
- - - - - - - - - - - - - - - - - - . CPU· MSM80C85A-2RS/GS •
POWER DOWN Mode (a newly added function)
The MSM80C85A-2 is compatible to MSM80C85A
in function and also with the POWER DOWN mode, this
reducing the power consumption further.
There are two methods available for starting this
POWER DOWN mode. One is made under the software
control by using the HALT command and the other is
under the hardware control by using the pin HOLD.
This mode is released by pins HOLD, RESET, and interrupt pins (TRAP, RST7.5, RST6.5, RST5.5, or INTR).
(See Table 4.)
Since the sequence of the HALT, HOLD, RESET,
and INTERRUPT is compatible to MSM80C85A, every
user can use the POWER DOWN mode with no particular attention.
Table 4 POWER DOWN Mode Releasing Method
Start by means of
HA L T command
Released by using pins RESET
and INTERRUPT (not by pin
HOLD)
Start by means of
pin HOLD
Released by using pins RESET
and HOLD (not by interrupt
pins)
(1)
(2)
Start by means of HALT command
(See Figures 6 and 7.)
The POWER DOWN mode can be started by executing the HALT command.
At this time, the system is made into the HOLD
status and therefore the POWER DOWN mode
cannot be released even when the HOLD is released
later.
In this case, the POWER DOWN mode can be released by means of the RESET or interrupt.
Start by means of pin (See Figure 8.)
During the execution of commands other than the
HALT, the POWER DOWN mode is started when
the system is made into the HOLD status by means
of pin HOLD.
Since no interrupt works during the execution of
the HOLD, the POWER DOWN mode cannot be
released by means of interrupt pins.
In this case, the POWER DOWN mode can be
released either by means of pin RESET or by
releasing the HOLD status by means of pin HOLD.
41
• CPU· MSM80C85A-2RS/GS • - - - - - - - - - - - - - - - - -
MI
TI
_I_
TRESET
-/
~II I T2
I
ClK
OUT
ALE
ADO.7
fJ
POWER
DOWN
RUN
CPU
MODE
RUN
RESET IN
Figure 6. Started by HALT and Released by RESET IN
MI
TI
I I I I~121·
T3
T2
-I ~II I T2 1
THlT
T4
ClK
OUT
ALE
RST5.5
'RUN
CPU
MODE
POWER
DOWN
RUN
Figure 7. Started by HALT and Released by RSTS.S
ClK
OUT
ALE
~
______~______________~~t--------~fl~---~
HOLD
HlDA
CPU
MODE
RUN
Figure 8. Started and Released by HOLD
42
POWER
DOWN
RUN
- - - - - - - - - - - - - - - - - . CPU· MSM80C85A-2RS/GS •
ABSOLUTE MAXIMUM RATINGS
Limits
Parameter
Symbol
Power Supply Voltage
VCC
Input Voltage
VIN
Condition
MSM80C85A-2RS
IMSM80C85A-2GS
Unit
-0.5 - +7
V
-0.5 ~ VCC +0.5
With respect to GND
V
VOUT
-0.5 ~ VCC +0.5
V
Storage Temperature
Tstg
-55~+150
°c
Power Dissipation
Po
Output Voltage
Ta = 25°C
I
1.0
W
0.7
OPERATING RANGE
Symbol
Limits
Power Supply Voltage
Parameter
VCC
3~6
Operating Temperature
Top
-40
~
Unit
V
bC---
+85
RECOMMENDED OPERATING CONDITIONS
Symbol
Min.
Typ.
Max.
Power Supply Voltage
Parameter
VCC
4.5
5
5.5
V
Operating Temperature
TOp
-40
+25
+85
°c
"L" Input Voltage
VIL
-0.3
+0.8
V
"H" Output Voltage
VIH
2.2
VCC + 0.3
V
"L" RESET IN
Input Voltage
VILR
-0.3
+0.8
V
"H" RESET IN
Input Voltage
VIHR
3.0
VCC+0.3
V
Unit
D.C. CHARACTERISTICS
Parameter
"L" Output Voltage
"H" Output Voltage
Symbol
Conditions
VOH
Input Leak Current
ILl
Output Leak Current
ILO
ICC
IOH= -400/J.A
2.4
IOH= -40/J.A
4.2
O~ VIN ~ VCC
O~ VOUT ~ VCC
I
Operating Supply
Current
Min.
IOL = 2mA
VOL
V CC = 4.5V ~ 5.5V
Ta = -40°C ~ +85°C
Typ.
Max.
Unit
0.45
V
V
V
-10
10
IJ.A
-10
10
IJ.A
20
mA
7
mA
Tcy~
= 200ns
CL = OpF at reset
Tcyc = 200ns
CL = OpF at power
down mode
..
43
• CPU· MSM80C85A-2RS/GS • - - - - - - - - - - - - - - - - -
A.C. CHARACTERISTICS
ITa = -40°C - 85°C, VCC = 4.5V - 5.5V)
Min.
Max.
tCYC
200
2000
ClK low Time
t,
40
ClK High Time
t2
70
Parameter
ClK Cycle Period
lJ
I
Symbol
ClK Rise and Fall Tim.
tr,tf
X, Rising to ClK Rising
tXKR
X, Rising to CKK Falling
A,
Valid to leading Edge of Control (1)
-IS
. A. - , Valid to leading Edge of Control
Ao
Valid Data In
""15
-IS
Valid Before Trailing Edge of ALE (1)
A. -, Valid Before Trailing Edge of ALE
READY Valid from Address Valid
Address lA, -,.) Valid After Control
120
tXKF
30
150
tAC
115
tACl
115
330
tAFR '
tAL
50
tAll
50
100
tARY
tCA
60
Width of Control law IRD, WR,INTA)
tcc
230
Trailing Edge of Control to Leading Edge of ALE
tCl
25
Data Valid to Trailing Edge of WR
tow
230
H LOA to Bus Enable
tHABE
Bus Float After HLDA
tHABF
HLDA Valid to Trailing Edge of CLK
tHACK
HOLD Hold Time
tHDH
HOLD Step Up Time to Trailing Edge of ClK
tHDS
INTR Hold Time
tlNH
150
tCYC = 200ns
CL = 150pF
150
40
120
I NTR, RST and TRAP Setup Time to Falling Edge of ClK
tiNS
Address Hold Time After ALE
tlA
50
Trailing Edge of ALE to leading Edge of Control
tLC
60
ALE low During CLK High
tlCK
50
ALE to Valid Data During Read
tlDR
ALE to Valid Data During Write
tlDW
ALE Width
tlL
ALE to READY Stable
tLRY
Trailing Edge of RD to Re·enabling of Address
tRAE
RD lor INTA) to Valid Data
tRD
Control Trailing Edge to Leading Edge of Next Control
tRV
150
250
140
80
30
90
150
220
Data Hold Time After RD INTA (7)
tRDH
READY Hold Time
tRYH
READY Setup Time to leading Edge of ClK
tRYS
100
Data Valid After Trailing Edge of WR
two
60
lEADING Edge of WR to Data Valid
tWDL
Not.. :
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Unit
30
25
tAD
Address Float After leading Edge of RD INTA
A,
Condition
20
AS-A lS address Specs apply to 101M, So, and SI except As-AI5 are undefined during T4-TS of OF
cycle whereas 101M, So, and S 1 are stable.
Test conditions: tCYC = 200ns C L = 150pF
For all output timing where CL = 150pF use the following correction factors:
25pF s: CL < 150pF: -O.10ns/pF
150pF < Cl s: 3OOpF: +O.30ns/pF
Output timings are measured with purely capacitive load.
All timings are measured at output voltage VL = O.8V, VH = 2.2V, and 1.5V with 10ns rise and fall time
on inputs.
To calculate timing specifications at other values of teye use Table 7.
Data hold time is guaranteed under all loading conditions.
Input Waveform for A.C. Tests:
. .______
2.4-----~X:~::: ~~s;. <~X
0.45-------'
44
-
- - - - - - - - - - - - - - - - - . CPU· MSM80C85A-2RS/GS •
Table 7 Bus Timing Specification as a TCYC Dependent
MSM80C85A·2
tAL
-
(1/2)T - 50
MIN
MIN
tlA
-
(1/2)T - 50
tll
-
(1/2)T - 20
MIN
tlCK
-
(1/2)T - 50
MIN
tlC
-
(1/2)T - 40
MIN
tAD
-
(5/2 + N)T - 170
MAX
tAD
-
(3/2 + N)T - 150
MAX
tAAE
-
(1/2)T - 10
MIN
MIN
tCA
-
(1/2)T -40
tow
-
(3/2 + N)T - 70
MIN
two
-
(1/2)T - 40
MIN
MIN
tcc
-
(3/2 +N)T - 70
tCl
-
(1/2)T - 75
MIN
tAAY
-
(3/2)T - 200
MAX
tHACK
-
(1/2)T - 60
MIN
tHABF
-
(l/2)T + 50
MAX
MAX
tHABE
-
(1/2)T + 50
tAC
-
(2/2)T - 85
MIN
tl
-
(1/2)T -60
MIN
t2
-
(1/2)T - 30
MIN
tAV
-
(3/2)T - 80
MIN
tlOR
-
(2+N)T - 150
MAX
Note: N is equal to the total WAIT states.
T = tCYC
XI INPUT
ClK
OUTPUT
tXKF
Figure 6 Clock Timing Waveform
45
• CPU· MSM80C85A-2RS/GS • - - - - - - - - - - - - - - - - READ OPERATION
/ tLCK}
ClK \
TI
T2
T\
/
\
I
I
II
A s -A I5
ADDRESS
tAD
ADo-AD,
tlDR
ALE
tRD
tcc
RDINTA
WRITE OPERATION
ClK
\
TIl
f-tLC)
Aa- A I5
Tj
\
ADDRESS
ADo-AD,
DATA OOT
tow
ALE
tWDl
tcc
WR
tAC
46
T3/
\
TI
/
- - - - - - - - - - - - - - - - - . CPU· MSM80C85A-2RS/GS •
Read operation with Wait Cycle (Typical) same READY timing applies to WRITE operation
TWAIT
, - - -....
ClK
AD o -AD 7
ALE
READY
Note: READY must remain stable during setup and hold times.
Figure 7
MSMSOCS5A-2 Bus Timing, With and Without Wait
HOLD OPERATION
elK
HOLD
HlDA
BUS
(ADDRESS,
CONTROLS)
Figure 8
MSMBOC85A-2 Hold Timing
47
• CPU· MSM80C85A-2RS/GS • "-"- - - - - - - - - - - - - - - - -
I
~
BUS FLOATING (1)
ALE
RD
INTA
tHABE-.........-4--
,
HOLD
\
HLDA _ _ _ _ _ _ _ _
I
\.J
111
tHAC~~1
Note: (1)
101M is also floating during this time.
Figure 9
48
'HABF
MSMSOC85A-2 Interrupt and Hold Timing
- - - - - - - - - - - - - - - - - . CPU· MSM80C85A-2RS/GS •
Table 8 Instruction Set Summary
I nstruction Code (1)
Mnemonic
Description
0,
06
Ds
04
03
O2
01
Do
D
Clock (2)
Cycles
MOV~LOAO.ANOSTORE
MOVr1 r2
MOVM r
MOVrM
MVI r
MVIM
LXIB
LXIO
LXIH
LXI SP
STAX B
STAX 0
LOA X 8
LOAX 0
STA
LOA
SHLO
LHLO
XCHG
Move register to register
Move register to memory
Move memory to register
Move immediate register
Move immediate memory
Load immediate register Pair B & C
Load immediate register Pair 0 & E
Load immediate register Pair H & L
Load immediate stack pointer
Store A indirect
Store A indirect
Load A indirect
Load A indirect
Store A direct
Load A direct
Store H & L direct
Load H & L direct
Exchange 0 & E H & L registers
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
1
1
0
0
0
0
1
1
1
1
1
0
1
0
0
1
0
1
0
1
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
S
S
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
S
S
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
S
S
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
7
7
7
10
10
10
10
10
7
7
7
7
13
13
16
16
STACK OPS
PUSH 8
PUSH 0
PUSH H
PUSH PSW
POP 8
POPO
POP H
POP PSW
XTHL
SPHL
Push register Pair 8 & C on stack
Push register Pair 0 & E on stack
Push register Pair H & L on stack
Push A and F lags on stac k
Pop register Pair 8 & C off stack
Pop register Pair 0 & E off stack
Pop register Pair H & L off stack
Pop A and Flags off stack
Exchange top of stack H & L
H & L to stack pointer
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
12
12
12
12
10
10
10
10
16
6
JUMP
JMP
JC
JNC
JZ
JNZ
JP
JM
JPE
JPO
PCHL
Jump unconditional
Jump on carry
Jump on no carry
Jump on zero
Jump on .no zero
Jump on positive
Jump on minus
Jump on parity even
Jump on parity odd
H & L to program counter
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
1
10
7/10
7/10
7/10
7/10
7/10
7/10
7/10
7/10
6
CALL
CALL
CC
CNC
CZ
CNZ
CP
CM
CPE
CPO
Call
Call
Call
Call
Call
Call
Call
Cali
Call
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
18
9/18
9/18
9/18
9/18
9/18
9/18
9/18
9/18
unconditional
on carry
on no carry
on zero
on no zero
on positive
Qn minus
on parity even
on parity odd
4
4
49
• CPU· MSM80C85A-2RS/GS • - - - - - - - - - - - - - - - - Table 8 Instruction Set Summary cont'd
Instruction Code( 1)
D7
D6
Ds
D4
D3
D2
Dl
Do
Clock(2)
Cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
10
6/12
6/12
6/12
6/12
6/12
6/12
6/12
6/12
1
1
A
A
A
1
1
1
12
1
1
1
1
0
0
1
1
1
0
0
0
1
1
1
1
10
10
INCREMENT AND DECREMENT
INR r
Increment register
DCR r
Decrement register
INRM
Increment memory
DCR M
Decrement memory
INX B
Increment B & C registers
INX D
Increment D & E registers
INX H
Increment H & L registers
INXSP
Increment stack pointer
DCX B
Decrement B & C
DCX D
Decrement D & E
DCX H
Decrement H & L
DCX SP
Decrement stack pointer
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D
D
1
1
0
0
1
1
0
0
1
1
D
D
1
1
0
1
0
1
0
1
0
1
D
D
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1
1
4
4
10
10
6
6
6
6
6
6
6
6
ADD
ADD r
ADC r
ADDM
ADCM
ADI
ACI
DAD B
DAD D
DAD H
DAD SP
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
S
S
1
1
1
1
0
0
0
0
S
S
1
1
1
1
0
0
0
0
S'
S
0
0
0
0
1
1
1
1
4
4
7
7
7
7
10
10
10
10
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
1
0
1
0
1
S
S
1
1
1
1
S
S
1
1
1
1
S
S
0
0
0
0
4
4
7
7
7
7
Mnemonic
Description
RETURN
RET
RC
RNC
RZ
RNZ
RP
RM
RPE
RPO
Return
Return
Return
Return
Return
Return
Return
Return
Return
RESTART
RST
Restart
on
on
on
on
on
on
on
on
carry
no carry
zero
no zero
positive
minus
parity even
parity <:>dd
INPUT/OUTPUT
IN
OUT
SUBTRACT
SUB r
SBB r
SUB M
SBB M
SUI
S81
50
I Input
Output
Add
Add
Add
Add
Add
Add
Add
Add
Add
Add
register to A
register to A with carry
memory to A
memory to A with carry
immediate to A
immediate to A with carry
B & C to H & L
D & E to H & L
H & L to H & L
stack pointer to H & L
Subtract
Subtract
Subtract
Subtract
Subtract
Subtract
borrow
register from A
register from A with borrow
memory from A
memory from A with borrow
immediate from A
immediate from A with
- - - - - - - - - - - - - - - - - - . CPU· MSM80C85A-2RS/GS •
Table 8 Instruction Set Summary cont'd
Instruction Code(1)
Mnemonic
Description
D7
D6
Ds
D4
D3
D2
D1
Do
Clock(2)
'Cycles
LOGICAL
ANA r
XRAr
ORA r
CMPr
ANAM
XRAM
ORAM
CMPM
ANI
XRI
ORI
CPI
And register with A
Exclusive Or register with A
Or register with A
Compare register with A
And memory with A
Exclusive Or Memory with A
Or memory with A
Compare memory with A
And immediate with A
Exclusive Or immediate with A
Or immediate with A
Compare immediate with A
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
S
S
S
S
1
1
1
1
1
1
1
1
S
S
S
S
1
1
1
1
1
1
1
1
S
S
S
S
0
0
0
0
0
0
0
0
4
4
4
4
7
7
7
7
7
7
7
7
ROTATE
RLC
RRC
RAL
RAR
Rotate
Rotate
Rotate
Rotate
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
4
4
4
4
SPECIALS
CMA
STC
CMC
DAA
Complement A
Set carry
Complement carry
Decimal adjust A
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
4
4
4
4
CONTROL
EI
DI
NOP
HLT
RIM
SIM
Enable Interrupts
Disable Interrupts·
No-operation
Halt (Power down)
Read Interrupt Mask
Set Interrupt Mask
1
1
0
0
0
0
1
1
0
1
0
0
1
1
0
1
1
1
1
1
0
1
0
1
1
0
0
0
0
0
0
0
0
1
0
0
1
1
0
1
0
0
1
1
0
0
0
0
4
4
4
Notes:
(1)
(2)
A
A
A
A
left
right
left through carry
right through carry
5
4
4
DDD or SSS. 8 000. COOL D 010. E 011. H 100. L 101. Memory 110. A 111.
Two possible cycle times, (6/12) indicate instruction cycles dependent on condition flags.
51
OKI
semiconductor
MSM80C86 RS/GS
16-BIT CMOS MICROPROCESSOR
GENERAL DESCRIPTION
I
II
The MSM80C86 is a complete 16-bit CPU implemented in Sillicon Gate CMOS technology. It is designed with
same processing speed as NMOS 8086 but considerably less power consumption. It is directly comp~tible with
MSM80C88 software and MSM80C85A hardware and peripherals.
FEATURES
•
•
•
•
.8 and 16-!?it Signed and Unsigned Arithmetic Operation
.5 MHz Clock Rate
• Low Power Dissipation (MAX 55 mAl
1 Mbyte Direct Addressable Memory Space
Internal 14 Word by 16-bit Register Set
24 Operand Addressing Modes
Bit, Byte, Word and String Operations
CIRCUIT CONFIGURATION
EXECUTION UNIT
REGISTER FILE
DATA
POINTER AND
INDEX REGS
(8WORDS)
BUS INTERFACE UNIT
I
i
RELOCATION
REGISTER FILE
SEGMENT
REGISTERS
AND
INSTRUCTION
POINTER
(5WORDS)
BHE/S7
A19/S6
16BIT ALU
FLAGS
BUS
INTERFACE
UNIT
A16/S3
AD15 - ADO
DT/R, DEN,ALE
6BYTE
INSTRUCTION
~UEUE
TEST
INTR
NMI
OSO,OS1
RO/GTO,1
HOLD
HLDA
CLK
RESET READY MN/MX
GND
Vee
52
•
CPU . MSM80C86RS/GS
•
PIN CONFIGURATION
MSM8OC86RS (Top View)
40 Lead Plastic DIP
GND
vee
AD14
AD15
AD13
A16/S3
AD12
A17/S4
AD11
A1S/S5
AD10
A19/S6
AD9
BHE/S7
ADS
MN/MX
AD7
RD
AD6
RQ/GTO (HOLD)
AD5
RQ/GT1 (HlDA)
AD4
LOCK (WR)
AD3
S2(M/IO)
S1
AD2
a
(DT/R)
so (DEN)
AD1
ADO
QSO (ALE)
NMI
aS1 (INTA)
INTR
elK
READY
GND
RESET
Fig.2a MSM80C86RS
MSM80C86GS (Top View)
56 Lead Plastic Flat Package
» » » » z zGl Z (")< (")< z » al
~ ~ ~
..... 00
~ ~ ~ ~ 0 0 0 (") (") 0 ~
enw ~ en
w l>
(11
I'-)
~
(11
(11
(11
(11
l>
(11
w
(11
I'-)
~
(11
0
l>
CD
l>
00
l>
.....
l>
al
l>
(11
l>
l>
l>
W
l>
N.C.
AD10
I'-)
AD9
w
ADS
l>
AD7
(11
AD6
al
0
I'-)
N.C.
~
A19/56
l>
0
BHE/57
w
MN/MX
CD
w
00
RD
w
Fm/GiO (HOLD)
.....
N.C.
.....
al
w
N.C.
N.C.
00
w
N.C.
AD5
CD
AD4
15
(11
N.C.
w
w
w
Rn"/GT'f (HLDA)
~
w
52 (M/iO)
l>
AD3
AD2
w
I'-)
I'-)
AD1
W
ADO
~
0
I'-)
CD
a;
~
z Z
(")
(11
~
-l
Jl
r
7\
0;
co
I'-)
0
~
I'-)
I'-)
1'-).1'-)
w
Z
Z
z Z Gl
z (")< 0 0
0 0 0(")
l>
I'-)
I'-)
(11
al
Jl Jl
m m
CIl
m 0»
-l
Fig.2b MSM8OC86GS
-<
I'-)
.....
0
§I ...
LOCK (Vim)
Sf
(DT/R")
"SO{~)
I'-)
00
0
CIl
CIl
=1-lZ
r
j;
0
m
~-
53
• CPU· MSM80C86RS/GS • - - - - - - - - - - - - - - - - - ABSOLUTE MAXIMUM RATINGS
Limits
Parameter
Symbol
MSM80C86RS
I
V
Power Supply Voltage
VCC
-0.5 - +7
Input Voltage
V,N
-0.5 - VCC +0.5
V
VOUT
-0.5 - V CC +0.5
V
Output Voltage
Storage Temperature
Power Dissipation
Tstg
-65 - 150
I
1.0
PD
Conditions
Unit
MSM80C86GS
With respect to GND
°c
-
W
Ta = 25°C
0.7
OPERATING RANGE
Parameter
Unit
Symbol
Limits
Power Supply Voltage
VCC
3-6
V
Operating Temperature
TOp
-40 - 85
°c
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
MIN
TYP
MAX
Power Supply Voltage
VCC
4.5
5.0
5.5
V
Operating Temperature
TOp
-40
+25
+85
°c
"l" Input Voltage
V,l
"H" Input Voltage
*1 Only ClK,
V,H
*2 Reset & Ready,
Unit
-0.5
+0.8
V
(* 1)
VCC-0.8
VCC +0.5
V
(*2)
3.0
VCC +0.5
V
(*3)
2.2
VCC +0.5
V
*3 Except ClK, Reset and Ready
DC CHARACTER ISTICS
(Vee
= 4.5V to 5.5V, Ta = -4oo e to +85°e)
Parameter
MIN
VOL
"H" Output Voltage
VOH
3.0
VCC-O·4
TYP
MAX
0.4
Unit
Conditions
V
10l = 2.5mA
V
10H =-2.5mA
10H = -100 IlA
Input Leak Current
'll
-1.0
+1.0
p.A
O:s. V,:s. VCC
Output Leak Current
'lO
-10
+10
p.A
O:s. VO:s. VCC
Operating Supply Current
ICC
55
mA
,
TClCl=200NS, Ta=25°C
CL = OpF, at Reset
5
pF
Output Capacitance
Cout
15
pF
*4
I/O Capacitance
CliO
20
pF
*4
I nput Capac itance
*4.Test Conditions:
54
Symbol
"l" Output Voltage
Cin
a) Freq = 1 MHz.
b) Unmeasured Pins at GNO.
cl V,N at 5.0V or GND.
*4
• CPU • MSM80C86RS/GS •
A.C. CHARACTERISTICS
(VCC
= 4.5V to 5.5V, Ta = -40°C to +85°C)
Minimum Mode System
Timing Requirements
Parameter
Symbol
Min.
Max.
Unit
ClK Cycle Period
TClCl
200
500
ns
ClK Low Time
TClCH
118
ClK High Time
TCHCl
65
ns
ns
ClK Rise Time (From 1.0V to 3.5V)
TCH1CH2
10
ClK Fall Time (From 3.5V to 1.0V)
TCl2Cl1
10
TDVCl
Data in Setup Time
ns
ns
30
ns
TClDX
10
ns
RDY Setup Time into MSM 82C84A (See Notes 1,2)
TR1VCl
35
ns
RDY Hold Time into MSM 82C84A (See Notes 1,2)
TClR1X
0
ns
READY Setup Time into MSM 80C86
TRYHCH
110
ns
READY Hold Time into MSM 80C86
TCHRYX
30
ns
Data in Hold Time
READY Inactive to ClK (See Note 3)
TRYlCl
-8
ns
HOLD Setup Time
THVCH
35
ns
INTR, NMI, TEST Setup Time (See Note 2)
TINVCH
30
ns
Input Rise Time (Except ClK) (From 0.8V to 2.2V)
TlllH
15
ns
Input Fall Time (Except ClK) (From 2.2V to 0.8V)
TIHIL
15
ns
Timing Responses
Symbol
Min.
Max.
Unit
Address Valid Delay
TCLAV
10
110
ns
Address Hold Time
TClAX
10
Address Float Delay
TCLAZ
TClAX
ALE Width
TLHll
TClCH-20
Parameter
ns
80
ns
ns
ALE Active Delay
TCllH
80
ns
A lE I nactive Delay
TCHLl
85
ns
Address Hold Time to ALE Inactive
TlLAX
TCHCL-10
Data Valid Delay
TCLDV
10
ns
110
ns
ns
Data Hold Time
TCHDX
10
Data Hold Time after WR
TWHDX
TClCH-30
ns
ns
Control Active Delay 1
TCVCTV
10
110
Control Active Delay 2
TCHCTV
10
110
ns
Control I nactive Delay
Address Float to RD Active
TCVCTX
10
110
ns
TAZRL
0
ns
ns
RD Active Delay
TClRL
10
165
RD Inactive Delay
TClRH
10
150
R D I nactive to Next Address Active
HLDA Valid Delay
RDWidth
TRHAV
TCLCL-45
TCLHAV
10
TRlRH
2TClCl-75
ns
ns
160
ns
ns
55
• CPU· MSM80C86RS/GS • - - - - - - - - - - - - - - - - - Symbol
Min.
WRWidth
Parameter
TWLWH
2TCLCL-60
ns
Address Valid to ALE Low
TAVAL
TCLCH-60
ns
Output Rise Time (From 0.8V to 2.2V)
TOLOH
20
ns
Output Fall Time (From 2.2V to 0.8V)
TOHOL
15
ns
Notes:
I
II
I
56
Max.
1. Signals at MSM82C84A shown for reference only.
2. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
3. Applies only to T2 state. (8 ns into T3)
Unit
- - - - - - - - - - - - - - - - - - . CPU· MSM80C86RS/GS •
Maximum Mode System (Using MSM 82C88 Bus Controller)
Timing Requirements
Symbol
Min.
Max.
ClK Cycle Period
TClCl
200
500
ClK low Time
TClCH
118
TCHCl
65
Parameter
ClK High Time
Unit
ns
ns
ns
ClK Rise Time (From 1.0V to 3.5V)
iCH1CH2
10
ns
ClK Fall Tillie (From 3.5V to 1.0V)
TCl2Cl1
10
ns
ns
Data in Setup Time
TDVCl
30
Data in Hold Time
TClDX
10
ns
RDY Setup Time into MSM 82C84A (See Notes 1, 2)
TR1VCl
35
ns
RDY Hold Time into MSM 82C84A (See Notes 1, 2)
TClR1X
0
ns
READY Setup Time into MSM 80C86
TRYHCH
110
ns
READY Hold Time into MSM 80C86
TCHRYX
30
ns
READY inactive to ClK (See Note 3)
TRYlCl
-8
ns
Setup Time for Recognition (NMI, INTR, TEST)
(See Note 2)
TINVCH
30
ns
RQ/GT Setup Time
TGVCH
30
ns
RQ Hold Time into MSM 80C86
TCHGX
40
ns
Input Rise Time (Except ClK) (From 0.8V to 2.2V)
TlllH
15
ns
Input Fall Time (Except ClK) (From 2.2V to 0.8V)
TIHll
15
ns
Timing Responses
Parameter
Symbol
Min.
Max.
Unit
Command Active Delay (See Note 1)
TClMl
5
45
ns
Command Inactive Delay (See Note 1)
TClMH
5
35
ns
READY Active to Status Passive (See Note 4)
TRYHSH
110
ns
Status Active Delay
TCHSV
10
110
ns
Status Inactive Delay
TClSH
10
130
ns
Address Valid Delay
TClAV
10
110
Address Hold Time
TClAX
10
TClAX
ns
ns
Address Float Delay
TClAZ
80
ns
Status Valid to ALE High (See Note 1)
TSVlH
35
ns
Status Valid to MCE High (See Note 1)
TSVMCH
35
ns
ClK low to ALE Valid (See Note 1)
TCllH
35
ns
ClK low to MCE High (See Note 1)
TClMCH
35
ns
35
ns
ALE Inlactive Delay (See Note 1)
TCHll
MCE Inactive Delay (See Note 1)
TClMCl
4
Data Valid Delay
TCLDV
10
10
35
ns
110
ns
ns
ns
ns
Data Hold Time
TCHDX
Control Active Delay (See Note 1)
TCVNV
5
45
Control I nactive Delay (See Note 1)
TCVNX
5
45
Address Float to RD Active
TAZRl
0
ns
57
• CPU • MSM80C86RS/GS • -~---------------Symbol
Min.
Max.
Unit
R D Active Delay
TCLRL
10
165
ns
R D I nactive Delay
TCLRH
10
150
ns
R D I nactive to Next Address Active
TRHAV
TCLCL-45
50
ns
Parameter
Direction Control Active Delay (See Note 1)
TCHDTL
Direction Control Inactive Delay (See Note 1)
TCHDTH
ns
35
ns
GT Active Delay
TCLGL
0
85
ns
GT Inactive Dealy
TCLGH
0
85
RD Width
TRLRH
2TClCl-75
Output Rise Time (From 0.8V to 2.2V)
TOLOH
Output Fall Time (From 2.2V to O.8V)
Notes:
58
1.
2.
3.
4.
TOHOL
ns
ns
20
ns
15
ns
Signals at MSM 82C84A orMSM 82C88 are shown for reference only.
Setup requirement for asynchronous signal only to guarantee recognition at next ClK.
Applies only to T2 state (8 ns· into T3)
Applies only to T3 and wait states.
- - - - - - - - - - - - - - - - - - . CPU· MSM80C86RS/GS •
TIMING CHART
A.C. Testing Load Circuit
Input/Output
2 . 4 : Y l . 5 -TESTPOINTS- 1 . ? (
0.45
'-----
A.C. TESTING: INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC
"'" AND 0.45V FOR A LOGIC "0" TIMING MEASUREMENTS
ARE '.5V FOR BOTH A LOGIC "1" AND "0"
DEVICE
UNDER
TEST
Ii
1.
........ CL =
100pF
CL INCLUDES JIG CAPACITANCE
Minimum Mode
T1
T4
VIH
CLK (MSM 82C84A Output)
VIL
BHE/S7,A 19/56-A 16/S3
ALE
RDY (MSM 82C84A Input)
SEE NOTE 5
READY (MSM BOCB6 Inp"') {
READ CYCLE
AD15-ADO
(NOTE 1)
TCHCTV
1WFi,INTA=VOH)
59
• CPU· MSM80C86RS/GS • - - - - - - - - - - - - - - - - - rJlinimum Mode (Continued)
T1
T3
T2
T4
VIH
ClK o(MSM 82C84A Output)
VIL
BHE/S7,A19/S6 - A16/S3
S7-S3
ALE
WRITE CYCLE
DATA OUT
(NOTE 1)
(RD, INTA,
DT/R =VOH)
DEN
-+---+--~~~-+'~--~---TWlWH----~~,r_t_------
INTA CYCLE
AD15-ADO
-+-__-+-J
DT/A
(NOTES 1&3)
(RD,WR = VOH
BHE = VOL)
SOFTWARE HAlT- AD15
~ ____
ADO -+-J
RD, WR, INTA = VOH
TCLAV
DT/R= INDETERMINATE
.60
~
INVALID ADDRESS
________________
_
SOFTWARE HALT
- - - - - - - - - - - - - - - - - - . CPU· MSM80C86RS/GS •
MaximlJm Mode
T1
T2
T3
T4
VIH
ClK (MSM 82C84A output)
Vll
aSO,aS1
S2,51,SO (EXCEPT HALT)
BHE/S7,A19/S6 - A16/S3
TSVlH
ALE (MSM
TCllH
82C88 OUTPUT)
,--
I
SEE NOTE 5
R DY (MSM 82C84A
INPUT)
READY (MSM SOC86
INPUT)
1
READ CYCLE
AD15-ADO
DT/R"
MSM 82C88
OUTPUTS
SEE NOTES 5, 6
MRDC OR
IORC
1
DEN
61
• CPU· MSM80C86RS/GS • - - - - - - - - - - - - - - - - - - . Maximum Mode (Continued)
T1
T2
S2,
51,
T3
T4
TW
VIH
ClK (MSM 82C84A output)
VIL
SO (EXCEPT HALT)
WRITE CYCLE
AD15 - ADO
DEN
MSM 82C88
OUTPUTS.
SEE NOTES 5, 6
AMWC OR AIOWC
MWTC OR IOWC
INTA CYCLE
~
AD15
ADO {
SEE NOTE 3,4
TSVMCH
MCE/
DT/R
MSM 82C88
OUTPUTS
SEE NOTES 5, 6
DEN
SOFTWARE HAlT(DEN=VOl; RD, MRDC, IORC, MWTC,
AMWC, IOWC, AIOWC, INTA,=VOH)
AD15 - ADO
INVALID ADDRESS
-----+~'I--------------TClAV
S2,S1,~ ~~______~/
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
62
',---'-----
All signals switch between VOH and VOL unless otherwise specified.
ROY is sampled near the end of T2,T3,TW to determine if TW machines states are to be inserted.
Cascade address is val id between first and second I NT A cycle.
Two INTA cycles run back-to-back. The MSM 80C86 LOCAL AD DR/DATA BUS is floating during both INTA
cycles. Control for pointer address is shown for second I NT A cycle.
Signals at MSM 82C84A or MSM 82C88 are shown for reference only.
The issuance of the MSM 82C88 command and control signals (MRDC,MWTC,AMWC,IORC,IOWC,AIOWC,
INTA and DEN) lags the active high MSM 82C88 CEN.
All timing measurements are made at 1.5V unless otherwise noted.
Status inactive in state just prior to T4.
- - - - - - - - - - - - - - - - - - - . CPU· MSM80C86RS/GS •
Asynchronous Signal Recognition
ClK~
NMI
INTR
TEST
~
}
SIGNAL
--A
TlNVCH (SEE NOTE 1)
;
•
NOTE: 1. SETUP REQUIREMENTS FOR ASYNCHRO·
NOUS SIGNALS ONLY TO GUARANTEE RECOGNITION
AT NEXT ClK
Bus Lock Signal Timing (Maximum Mode Only)
~NY eLK;_e~~jANY
Reset Timing
e; CYCLE!
VCC
~
ClK
~I
~
lOCK •
TeLAV;
I
,
ClK
RESET
;?4 ClK CYCLES
Request/Grant Sequence Timing (Maximum Mode Only)
ClK
RO/GT
A015 - ADO
A 19/56- A 16/S3
S2. ST, SO, 1-1--------..;..;.,;;:..-----11 :
RD, lOCK
MSM BOCB6
••
1
BHE/S7
1-------
Note:
COPROCESSOR
(SEE NOTE 1)
1. The coprocessor may not drive the buses outside the region shown without risking contention.
Hold/Hold Acknowledge Timing (Minimum Mode Only)
ClK
TClHAV
HlDA
~----I ~_ _ _C_O_P_R~~C~E_S_S_O_R_ _ _ _
AD15- ADO,
_ _ _ _ _M_S_M_B_O_C86--(,'
A19/S6- A16/S3, r
••
RD,
f
J
MSM BOCB6'
BHE/S7, M/IO,
DT/R, WR, DEN
63
• CPU· MSM80C86RS/GS • - - - - - - - - - - - - - - - - - PIN DESCRIPTION
ADO-AD15
ADDRESS DATA BUS: Input/Output
These lines are multiplexed address and data bus.
These are address bus at T1 cycle and data bus at
T2, T3, TW and T4 cycle.
At T1 cycle, ADO low indicates Data Bus Low (DO
- 07) Enable. These lines are high impedance during
interrupt acknowledge and hold acknowledge.
A16/S3. A17/S4, A18/S5, A19/S6
ADDRESS/STATUS: Output
These are four most significant address, at T1
cycle. Accessing I/O port address, these are low at T1
cycle. These lines are Status lines at T2, T3. TW and T4
cycle. S3 and S4 are encoded as shown.
S3
S4
(l
0
Alternate Data
Characteristics
1
0
Stack
0
1
Code or None
1
1
Data
These lines
acknowledge.
are
high impedance during hold
BHE/S7
BUS HIGH ENABLE/STATUS: Output
This line indicates Data Bus High Enable (BHE) at
T1 cycle.
This line is status line at T2, T3, TW and T4 cycle.
This line is high impedance during hold acknowledge.
INTR
INTERRUPT REQUEST: Input
This line is level triggered interrupt request signal
which is sampled during the last clock cycle of instruction and string manipulation.
It can be internally masked by software.
This Signal is active high and internally synchronized.
TEST
TEST: Input
This line is examined by WAIT instruction.
When TEST is high, CPU enter idle cycle.
When TEST is low, CPU exit idle cycle.
NMI
NON MASKABLE INTERRUPT: Input
This line causes type 2 interrupt.
NMI is not maskable.
This signal is internally synchronized and needs
2 clock cycles pulse width.
RESET
RESET: Input
This signal causes CPU to initialize immediately.
This signal is active high and must be at least four
clock cycles.
CLK
CLOCK: Input
This signal provides the basic timing for internal
circuit.
MN/MX
MINIMUM/MAXIMUM: Input
This signal selects CPU's operate mode.
When VCC is connected, CPU operates Minimum
mode.
When GND is connected, CPU operates Maximum
mode.
RD
READ: Output
This line indicates that CPU is memory or I/O
read cycle.
This line is read strobe signal when CPU read data
from memory or I/O device.
This line is active low.
This line is high impedance during hold acknowledge.
VCC
VCC:
+3 - +6V supplied.
READY
READY: Input
This line indicates to CPU that addressed memory
or I/O device is ready to read or write.
This line is active high.
If the setup and hold time is out of specification,
illegal operation will occur.
The following pin function descriptions are maximum mode only.
Other pin functions are already described.
.64
GND
GROUND:
SO,81,S2
STATUS: Output
These lines indicate bus status and they are used
by the MSM82C88 Bus Controller to generate all
memory and I/O access control signals.
These lines are high impedance dUring hold
acknowledge.
These status lines are encoded as shown .
- - - - - - - - - - - - - - - - - - - . CPU· MSM80C86RS/GS •
S1
so
a (LOW)
a
a
a
a
1
Read I/O Port
a
1
a
Write I/O Port
S2
Characteristics
Interrupt acknowledge
a
1
1
Halt
1 (HIGH)
a
a
Code Access
1
a
1
Read Memory
1
1
a
Write Memory
1
1
1
Passive
RO/GTO
RO/GT1
REQUEST/GRANT: Input/Output
These lines are used for Bus Request from other
device and Bus GRANT to other deivce.
These lines are bidirectional and active low.
LOCK
LOCK: Output
This line is active low.
When this line is low, other device could not gain
control of the bus.
This line is high impedance during hold acknowledge.
OSO/OS1
QUEUE STATUS: Output
These lines are Queue Status that indicate internal
instruction queue status.
Characteristics
QS1
QSa
a (LOW)
a
No Operation
a
1
First Byte of Op Code from
Queue
1 (HIGH)
a
Empty the Queue
1
1
Subsequent Byte from Queue
The following pin function descriptions are mini-·
mum mode only. Other pin functions are already
described.
WR
WR ITE: Output
This line indicates that CPU is memory or I/O
write cycle.
This line is write strobe signal when CPU write
data to memory or I/O device.
This line is active low.
This line is high impedance during hold acknowledge.
INTA
INTERRUPT ACKNOWLEDGE: Output
This line is read strobe signal for interrupt acknowledge cycle.
This line is active low.
ALE
ADDRESS LATCH ENABLE: Output
This line is used for latching address into
MSM82C12 address latch. It is possitive pulse and
trailing edge is used to strobe the address. This line is
never floated.
DTiR
DATA TRANSMIT/RECEIVE: Output
This line is used for control a direction of bus
transcei ver.
When this line is high, CPU transmit data, and
when it is low, CPU receive data.
This line is high impedance during hold acknowledge.
DEN
DATA ENABLE: Output
This line is used for control an output enable of
bus transceiver.
This line is active low. This line is high impedance
during hold acknowledge.
HOLD
HOLD REQUEST: Input
This line is used for Bus Request from other
device.
This line is active high.
HLDA
HOLD ACKNOWLEDGE: Output
This line is used for Bus Grant to other device.
This line is active high.
MIlO
STATUS: Output
This line selects memory address space or I/O
address space.
When this line is high, CPU select memory address
space and when it is low, CPU select I/O address space.
This line is high impedance during hold acknowledge.
65
• CPU· MSM80C86RS/GS • - - - - - - - - - - - - - - - - - FUNCTIONAL DESCRIPTION
GENERAL OPERATION
The internal function of MSM80C86 consist of
Bus Int~rface Unit (BIU) and Execution Unit (EU).
These units operate mutually but perform as separate
processor.
BIU performs instruction fetch and queueing,
operand fetch, DATA read and write address relocation
and basic bus control. By instruction pre-fetch while
waiting for decording and execution of instruction.
CPU's performance is increased. Up to 6-bytes of
instruction stream can be queued.
E U receives pre-fetched instructions from B I U
queue, decodes and executes instruction and provided
un-relocated operand address to BIU.
MEMORY ORGANIZATION
MSM80C86 has 20-bit address to memory.
Each
address has 8-bit data width. Memory is organized
OOOOOH to FFFFFH and is logicaly divided into four
segments, code,. data, extra data and stack'segment. Each
segment contains up to 64 Kbytes and locates on
16-byte boundary. (Fig. 3a)
All memory references are made relative to segment register which is according to select rule. Word
operand can be located on even or odd address
boundary.
BIU automatically performs the proper number of
memory access. Memory consists of even address and
odd address. Byte data of even address is transfered on
the DO - D7 and byte data of odd address is transfered on the D8 - D15.
CPU provides two enable signals SHE and AO to
access either an odd address, even address or both:
Memory location FFFFOH is start address after
reset and OOOOOH through 003FFH are reserved for
interrupt pointer, where 256 types interrupt pointer
are there.
Each interrupt type has 4-byte pointer element
consist of 16-bit segment address and 16-bit offset
address.
Reserved Memory Locations
Memory Organization
.a:
01 FFFFFH
~
}CODE
SEGMENT
~
RESET BOOTSTRAP
PROGRAM JUMP
,----L--eoJ::----t
FFFFOH
'~----t'
I
t
XXXXOH
}
+OFFSET
SEGMENT
REGISTER FILE
•
STACK
SEGMENT
..
CS
}
DS
ES
)--
}
T
_66
3FFH
INTERRUPT POINTER
FOR TYPE 255
3FCH
~-oSS~__~)______~____~ DAT~EGMENT
I
FFFFFH
,.
EXTRA DATA
SEGMENT
OOOOH
t - - - - - - . . . . , . - - - - t 7H
INTERRUPT POINTER
FOR TYPE 1
4H
t-IN-T-E-R-R-U-P-T-P-O-I-N-T-E-R-I 3H
"-_ _
FO_R_T_Y_P_E_O____ OH
- - - - - - - - - - - - - - - - - - . CPU· MSM80C86RS/GS •
Memory
Reference Need
Segment Register
Used
Segment
Selection Rule
Instructions
CODE (CS)
Automatic with all instruction prefetch.
Stack
STACK (SS)
All stack pushes and pops. Memory references relative to
BP base register except data references.
Local Data
DATA (DS)
Data references when relative to stack destination of string operation, or explicitly overridden.
External (Global) Data
EXTRA (ES)
Destination of string operations: Explicitly selected using a segment overriden.
MINIMUM AND MAXIMUM MODES
MSM8OC86 has two system modes: minimum and
maximum mode. As using maximum mode, it is easy to
organize multi-CPU system with 82C88 Bus Controller
which generate bus control signal generate.
As using minimum mode, it is easy to organize
simple system by generating bus control signal itself.
MN/MX is mode select pin. Definition of 24-31
pin changes depend on the MN/MX pin.
BUS OPERATION
MSM80C86 has a time multiplexed address and
data bus. If non-multiplexed bus is desired for system,
it is only to add the address latch.
CPU bus cycle consists of at least four clock cycles.
T1, T2 T3 and T4. (Fig. 4)
The address output occurs during T1 and data
transfer occurs during T3 and T4. T2 is used for changing the direction of the bus at read operation. When the
device which is accessed by CPU is not ready to data
transfer and send to CPU "NOT READY", TW cycles
are inserted between T3 and T4.
When bus cycle is not needed. T1 cycles are
inserted between bus cycles for internal execution. At
T1 cycle, ALE signal is output from CPU or MSM82C88
depending on MN!MX. At the trailing edge of ALE, a
valid address may be latched.
Status bits S3 through S7 are multiplexed with
A 16 - A 19, and BH E, therefore there are valid during
T2 through T4.
S3 and S4 indicate which segment register was
selected on the bus cycle, according to the following
table.
S3
Characteristics
0
Alternate Data (Extra segment)
0
1
Stack
1 (HIGH)
0
Code or None
1
1
Data
S4
o (LOW)
S5 indicates interrupt enable Flag.
I/O ADDRESSING
MSM80C86 has 64 Kbyte I/O or 32 Kword I/O.
When CPU accesses I/O device, address AO - A 15 are
same format as a memory access, and A 16 - A 19 are
low.
I/O ports address are same as memory, so it is need
to care of using 8-bit peripherals.
Status bits SO, Sf and S2 are used in maximum
mode, by the bus controller to recognize the type of
bus operation according to the following table.
-
S2
-
Characteristics
S1
SO
o (LOW)
0
0
0
0
1
Read I/O
0
1
0
Write I/O
Interrupt acknowledge
0
1
1
Halt
1 (HIGH)
0
0
I nstruction Fetch
1
0
1
Read Data from Memory
1
1
0
Write Data to Memory
1
1
1
Passive (no bus cycle)
67
• CPU· MSM80C86RS/GS • - - - - - - - - - - - - - - - - - Basic System Timing
1 - ( 4 + N*WAIT) = TCY - - - 1 - ( 4 + N*WAIT) =
I T1
I
T2
I
T3
ITWAITI
T4
I I
T1
T2
I
T3
TCY~
ITWAITI
T4
I
ClK
GOES INACTIVE IN THE STATE
JUST PRIOR TO T4
m
ALE
I
BHE, A19-A16
ADDR/
STATUS
ADDR/DATA
S7-S3
S7-S3
BUS RESERVED
015-00
FOR DATA IN
VALID
r---~,)
___ -~~D-A-T-A-O-U-T----~\~
~
(D15-DO)~
READY
READY
READY
WAIT
WAIT
DT/R
MEMORY ACCESS TIME
\'---_~I
68
- - - - - - - - - - - - - - - - - - . CPU· MSM80C86RS/GS •
EXTERNAL INTERFACE
bytes in size and corresponds to an 8 bit type number
which is sent from interrupt request device during
interrupt acknowledge cycle.
RESET
CPU Initialization is executed by RESET pin.
MSM80C86's RESET High signal is required for greater
than 4 clock cycles.
Rising edge of RESET terminates present operation
immediately. Falling edge of RESET triggers internal
reset sequence for approximately 10 clock cycles.
After internal reset sequence is done, normal operation
beings from absolute location FFPFOH.
NON-MASKABLE INTERRUPT (NMI)
MSM80C86 has Non-maskable Interrupt (NMIl
which is higher priority than maskable interrupt request
(INTR).
NMI request pulse width needs minimum 2 clock
cycles. NMI will be serviced at the end of the current
instruction or between string manipulation.
INTERRUPT OPERATIONS
Interrupt operation is classified as software or
hardware and hardware interrupt is classified as nonmaskable or maskable.
Interrupt causes to a new program location which
is defined interrupt pointer table, according to interrupt
type. Aboslute location OOOOOH through 003FFH is
reserved for interrupt pointer table. Interrupt pointer
table consists of 256-elements, and each element is 4
MASKABLE INTERRUPT (JNTR)
MSM80C86" provides an another interrupt request
(lNTR) which can be masked by software. INTR is
level triggered, so it must be held until interrupt request
is acknowledged.
INTR will be serviced at the end of the current
instruction or between string manipulation.
Interrupt Acknowledge Sequence
I
ALE
T1
I
T2
I
T3
I T4 ITII T1
I
T2
I
T3
T4
I
~~--
LOCK
\----.Ull._-----II
\________r
ADO-AD15
~
FLOAT
~--------------~f~------~' - - _ _ _J
INTERRUPT ACKNOWLEDGE
During the interrupt acknowledge sequence,
further interrupts are disabled. Interrupt enable bit is
reset by any interrupt, after Flag register is automatically pushed onto the stack. During acknowledge sequence,
CPU emits the lock signal from T2 of first bus cycle to
T2 of second bus cycle. At second bus cycle, byte is
fetched from external device as a vector which identified the type of interrupt, and this vector is multiplied
by four and used as a interrupt pointer address. (lNTR
only)
The Interrupt Return (JREn instruction includes a
Flag pop operation which returns the original interrupt
enable bit when it restores the Flag.
HALT
When Halt instruction is executed, CPU enters Halt
state. Interrupt request or RESET will force the
MSM80C86 out of the Halt state.
SYSTEM TIMING - MINIMUM MODE
Bus cycle begins T1 with ALE signal. The trailing
edge of ALE is used to latch the address. From T1 to
T4 the M/IO sign~1 indicates a memory or I/O operation. From T2 to T4, the address data bus change
address bus to data bus.
The read (RD), write (WR), interrupt acknowledge
(I NTA) signal cuases the addressed device to enable data
bus. These signal becomes active at beginning of T2 and
inactive at beginning of T4.
SYSTEM TIMING - MAXIMUM MODE
At maximum mode, MSM82C88 Bus Controller is
added to system. CPU sends status information to Bus
Controller. Bus timing signals are generated by Bus
Controller. Bus timing is almost same as minimum
mode.
69
-m~
•
DATA TRANSFER
MOV = Move:
Register/memory to/from register
Immediate to register/memory
I mmediate to register
Memory to accumulator
Accumulator to memory
Register/memory to segment register
Segment register to register/memory
7
1
1
1
1
1
1
1
5 4 3
0 0' 0 1
1 0 0 0
0 1 1 w
0 1 0 0
0 1 0 0
0 0 0 1
0 0 0 1
6
2 1 0 7 6
0 d w mod
1
1
reg
0 0
0 1
1 1
1 0
w mod
w
w
0 mod
0 mod
5 4
3
reg
0 0 0
data
addr-Iow
addr-Iow
0 reg
0 reg
2
1 0
rIm
rIm
rIm
rim
7
6
5 4
3
2
1
data
data if w = 1
addr-high
acfdr-high
0
7
6
5 4
3
2
1
data if w= 1
0
n
~
c
3:
tI)
3:
CO
8
~
::0
PUSH
=: Push:
Register/memory
Register
Segment register
1
1
mod
1
1
0
rIm
mod
0
0
0
rim
1
0
0
1
1
0
1
0
0
1 1
1 0
reg
1
reg
1 1
0
1
0
0
0
1
0
0
0
0
0 1
1 1
reg
1
1
reg
1 1
1
1
1
0
0
0
0
0
1
0
0
1
1
reg
w
1
1
1
1
1
1
0
0
0
1
1
1
0
0
w
w
port
1 1
1 1
1 1
1 0
1 1
1 1
1 0
1 0
1 0
1 0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
0
0
w
w
1
1 mod
1 mod
0 mod
1
0
0
1
port
POP = Pop:
Register/memory
Register
Segment register
1
XCHG = Exchange:
Register/memory with register
Register with accumulator
mod
reg
rim
IN = Input from:
Fixed port
Variable port
OUT = Output to:
Fixed port
Variable port
X LA T = Translate byte to A L
LEA = Load EA to register
LDS = Load pointer to DS
LES = Load pointer to ES
LAHF = Load AH with flags
SAHF = Store AH into flags
PUSHF = Push flags
POPF = Pop flags
reg
reg
reg
rim
rim
rim
~
•
tI)
ARITHMETIC
ADD
= Add:
Reg./memory with register to either
Immediate to register/memory
Immediate to accumulator
ADC
= Add
0
0
0
0
0
0
0
0
0
0
0
1
d
s
0
w mod
w mod
w
reg
0 0 0
data
rim
rim
I
data
data if w
data if s:w
= 01
=1
I
I
0
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
0
0
0
1
1
0
0
1
0
1
1
1
0
1
0
1
0
0
0
1
0
1
0
0
0
0
1
0
1
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
d
s
0
w mod
w mod
w
0
1
reg
1 1
1 1
w mod
0
1
0
1
0
0
1
d
s
0
w mod
w mod
w
1
1
0
1
0 d
0 s
1 0
w mod
w mod
w
0
reg
1 0
data
rim
rim
0
0
rim
reg
0 1
data
rim
rim
reg
1 1
data
rim
rim
data
data if w
=1
data
data if w
=1
data
data if w
=1
data if s:w
= 01
data if s:w
= 01
= Increment:
Register/memory
Register
AAA
DAA
SUB
0
0
0
with carry:
Reg./memory with register to either
Immediate to register/memory
Immediate to accumulator
INC
I
0
1
0
= ASCII adjust for add
= Decimal adjust for add
1
1
= subtract:
Reg./memory and register to either
I mmediate from register/memory
Immediate from accumulator
SBB = Subtract with borrow:
Reg./memory and register to either
Immediate from register/memory
Immediate from accumulator
DEC
data if s:w = 01
•
o
c
~
= Decrement:
Register /memory
Register
NEG = Change sign
1
0
1
1
1
1
1
0
1
1
0
1
1
1
0
1 w mod
reg
1 1 w mod
1
0
0
1
rim
0
1
1
rim
I
I
CMP
= Compare:
I
Register/memory and register
Immediate with register/memory
Immediate with accumulator
AAS = ASCII adjust for subtract
~
.....
0
1
0
0
0
0
0
0
1
0
1
1
1
0
1
1
1
0
1
1
0 d
0 s
1 0
1 1
w mod
w mod
w
1
reg
1 1 1
data
rim
rim
I
data
data if w = 1
data if s;w
= 01
I
3:
en
3:
CO
o
o
~
::0
se
G')
I
en
•
!!
~
DAS = Decimal adjust for subtract
MUL = Multiply (unsigned)
IMUL = Integer multiply (signed)
AAM = ASCII adjust for multiply
DIV = Divide (unsigned)
IDIV = Integer divide (signed)
AAD = ASCII adjust for divide
CBW = Convert byte to word
CWO = Convert word to double word
0
0
1
1
1
1
1
1
1
1
1 0
1 1
1 1
1 0
·1 1
1 1
1 0
1 0 0
1 0 0
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1 1 1
1 1 w mod
1 1 w mod
1 0 0 0 0
1 1 w mod
1 1 w mod
1 0
0 0
0 0
1 0 0
0
1
•
1 0
0
1
rIm
rIm
1 0
0 0 1 0 1 0
rIm
1 1 0
1 1 1
rIm
0 0 1 0 1 0
o
."
C
3:
3:
(I)
CO
o
oCO
en
:JJ
(I)
G5
(I)
•
LOGIC
NOT = Invert
SH L/SAL = Shift logical/arithmetic left
SHR = Shift logical right
SAR = Shift arithmetic right
ROL = Rotate left
ROR = Rotate right
RCL = Rotate left through carry
RCR = Rotate right through carry
AND
= And function
1 1 0
0 1 0
0 1 0
0 1 0
0 1 0
0 1 0
0 1 0
0 1 0
1
0
0
0
0
0
0
0
1 w mod
v w mod
v w mod
v w mod
v w mod
v w mod
v w mod
v w mod
0
1
1
1
0
0
0
0
0 0
1 0
0 0
1 0 0 0 d w mod
0 0 0 0 0 w mod
1 0 0 1 0 w
1
1 0
1 1
1 0
0 0 0 1 0 w mod
1 1 0 1 1 w mod
1 0 1 0 0 w
0
XOR
1
1
1
reg
0 0
data
rIm
rIm
reg
0 0
data
rIm
rIm
0 0 0 0 1 0 d w mod
1 0 0 0 0 0 0 w mod
0 0 0 0 1 1 0 w
reg
0 0 1
data
rIm
rIm
0 0 1 1 0 0 d w mod
1 0 0 0 0 0 0 w mod
0 0 1 1 0 1 0 w
1
reg
1 0
data
rIm
rIm
data
data if w
=1
data
data if w
=1
data
data if w
=
data if w
=1
data if w
=
data if w
=1
data if w
=1
1
1
= Exclusive or:
Reg.!memory and register to either
Immediate to register/memory
Immediate to accumulator
STRING MANIPULATION
REP = Repeat
MOVS = Move byte/word
CMPS = Compare byte/word
seAS = Scan byte/word
LaDS = Load byte/word to AL/AX
STOS = Store byte/word from AL/AX
.....
1
0 0
0 1
1 0
rIm
r!m
rIm
rIm
rIm
rIm
rIm
rIm
= Or:
Reg./memory and register to either
Immediate to register/memory
Immediate to accumulator
.W
1 0
0 0
0 1
to flags, no result:
Register/memory and register
Immediate data and register/memory
Immediate data and accumulator
OR
1
1
1
1
1
1
1
1
= And:
Reg./memory and register to either
Immediate to register/memory
Immediate to accumulator
TEST
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0 0 1 z
0 1 0 w
0 1 1 w
1 1 1 w
0 1 1 0 w
0 1 0 1 w
1
0
0
0
•
data
data if w
=1
o
~
C
3:
en
3:
00
o
o
~
:D
S!?
G')
en
•
-m~
CJMP
•
=Conditional JI\{IP
JE/JZ = Jump on equal/zero
JZ/JNGE = Jump on less/not greater or equal
JLE/JNG = Jump on less or equal/not greater
JB/JNAE = Jump on below/not above or equal
JBE/JNA = Jump on below or equal/not above
JP/JPE = Jump on parity/parity even
JO = Jump on over flow
JS = Jump on sign
JNE/JNZ = Jump on not equal/not zero
JNL/JGE = Jump on not less/greater or equal
JNLE/JG = Jump on not less or equal/greater
JNB/JAE = Jump on not below/above or equal
JNBE/JA = Jump on not below or equal/above
JNP/JPO = Jump on not parity/parity odd
JNO = Jump on not overflow
JNS = Jump on not sign
LOOP = Loop CX times
LOOPZ/LOOPE = Loop while zero/equal
LOOPNZ/LOOPNE = Loop while not zero/equal
JCXZ = Jump on CX zero
1
1
1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 0
1 1 0
1 1 0
1 1 0
0
1
1
0
0
1
0
1
0
1
1
0
0
1
0
1
0
0
0
0
1 0
1 0
1 1
0 1
1 1
0 1
0 0
0 0
1 0
1 0
1 1
0 1
1 1
0 1
0 0
0 0
0 1
0 0
0 0
0 1
1
1
1
1
1
1
1
1
1
1
1
1
1 0 1
1 0 0
1 1 0
1 1 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
o."
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
1
1
1
1
0
1
0
1
C
3:
en
3:
CO
o
oCO
0)
:xl
~
G)
en
•
INT = Interrupt:
Type speci fied
Type 3
INTO = Interrupt on overflow
I R ET = Interrupt return
-
0
0
0
0
0
0
0
0
type
- -
PROCESSOR CONTROL
CLC = Clear carry
CMC = Complement carry
STC = Set carry
CLD = Clear direction
STD = Set direction
CLI = Clear interrupt
STI = Set interrupt
HLT=Halt
WAIT = Wait
ESC = Escape (to external device)
LOCK = Bus lock prefix
--
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 0 0
1 1 0
1 1 1
1 1
1 0
1 1
1 1
1 1
1 1
1 1
1 0
1 1
1 1
1 0
0
1
0
1
1
0
0
1
0
0
0
0
0
0
1
1
0
1
0
1
1
0
1
0
1
0
1
x
x
x
0
0
0
mod
x
x
x
rIm
CONTROL TRANSFER
CALL = Call:
Direct within segment
Indirect within segment
Direct intersegment
7 6 5 4
1 1 1 0
1 1 1 1
1 0 0 1
3 2 1 0 7 6
1 0 0 0
1 1 1 1 mod
1 0 1 0
Indirect intersegment
1
1
1
1
1
Direct within segment
Direct within segment-short
Indirect within segment
Direct intersegment
1
1
1
1
1
1
1
0
0
1
0
1
1
1
1
1
1
1
1
Indirect intersegment
1
1
1
1
1 0
1 0
1 0
1 0
JMP
RET
1
1
1
0
0
1
1 0
0
1
1
1
1
1
1
0
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
1
0
1
0
mod
5
4
3
2
1 0
disp-Iow
0
1 0
1
1
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
disp-high
rim
offset-low
seg-Iow
0
7
offset-high
seg-high
rim
= Unconditional Jump:
= Return
disp-Iow
disp
mod
1 0
0
disp-high
rim
I
offset-low
seg-Iow
mod
1 0
1
offset-high
seg-high
rim
I
from CALL:
Within segment
Within seg. adding immediate to SP
I ntersegment
Intersegment adding immediate to SP
1
1
1
data-low
data-high
data-low
data-high
•
(')
."
C
s:
s:CO
(I)
o
(')
~
JJ
S!?
C')
(I)
~
•
c
• CPU· MSM80C86RS/GS • - - - - - - - - - - - - - - - - - Footnotes:
Al = 8-bit accumulator
AX = 18-bit accumulator
CX = Count register
OS = Data segment
ES = Extra segment
Above/below refers to unsigned value
Greater = more positive
less = less positive (more negative) signed value
If d = 1 then "to" reg: If d = 0 then "from" reg.
If w = 1 then word instruction: If w = 0 then byte instruction
If
If
If
If
mod
mod
mod
mod
=
=
=
=
11 then
00 then
01 then
10 then
If rIm = 000 then
If rim = 001 then
If rim = 010 then
If rim = 011 then
If rIm = 100 then
If rim = 101 then
If rIm = 110 then
If rim = 111 then
DISP follows 2nd
rIm is treated as a REG field
DISP = 0*, disp-Iow and disp-high are absent
DISP = disp-Iow sign-extended to 16-bits, disp-high is absent
DISP = disp-high: disp-Iow
EA = (BX) + (SJ) + DISP
EA = (BX) + (01) + DIS.P
EA = (BP) + (SI) + DISP
EA = (BP) + (01) + DISP
EA = (SI) + DISP
EA = (OJ) + DISP
EA = (BP) + DISP*
EA = (BX) + DISP
byte of instruction (before data if required)
* except if mod = 00 and rim = 110 then EA-disp-high: disp-Iow
If s:w = 01 then 16 bits of immediate data form the operand
If s:w = 11 then an immediate data byte is sign extended to form the 16-bit operand
If v = a then "count" = 1: If v = 1 then "count" in (Cl)
x = don't care
z is used for string primitives for comparison with ZF FLAG
SEGMENT OVERRIDE PREFIX
001 reg 110
REG is assigned according to the following table:
16-Bit
000
001
010
all
100
101
110
111
(w = 1)
AX
CX
OX
BX
SP
BP
SI
01
8-Bit (w=O)
000
Al
001
Cl
010 Dl
all
Bl
100 AH
101
CH
DH
110
111
BH
Segment
00 ES
01 CS
10 SS
11 OS
Instructions which reference the flag register file as a 16-bit object use the symbol FLAGS to represent the file:
FLAGS = x:x:x:x:(OF):(DF):(JF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF)
.76
OKI
semiconductor
MSM80C88RS/GS
8-BIT CMOS MICROPROCESSOR
GENERAL DESCRIPTION
The MSM80C88 is a internal 16-bit CPU with 8-bit interface implemented in Sillicon Gate CMOS technology.
It is designed with same processing speed as the NMOS8088 but with considerably less power consumption.
The processor has attributes of both 8- and 16-bit microprocessor. It is directly compatible with MSM80C86
software and MSM80C85A hardware and peripherals.
FEATURES
•
•
•
•
•
•
a-8it Data 8us Interface
16-8it Internal Architecture
1 Mbyte Direct Addressable Memory Space
Software Compatible with MSM80C86
Internal 14 Word by 16-bit Register Set
24 Operand Addressing Modes
• 8it, 8yte, Word and String Operations
• a and 16-bit Signed and Unsigned Arithmetic Operation
• 5 MHz Clock Rate
• Low Power Dissipation (MAX 55 mAl
FUNCTIONAL BLOCK DIAGRAM
EXECUTION UNIT
BUS INTERFACE UNIT
I
REGISTER FILE
DATA
POINTER AND
INDEX REGS
(8WOADS)
I
RELOCATION
REGISTER FILE
SEGMENT
REGISTERS
AND
INSTRUCTION
POINTER
(5WORDS)
SSo
A19/S6
1SBIT ALU
A8
AD7-ADO
FLAGS
INTA,
RD, WR,10lM
DT/R, DEN,AlE
4 BYTE
INSTRUCTION
QUEUE
TEST
INTR
NMI
Ra/GTo,1
HOLD
HLDA
ClK
RESET READY MNIMX
GND
Vee
77
•
CPU . MSM80C88RS/GS •
PIN CONFIGURATION
MSMSOC88RS (Top View)
40 Lead Plastic DIP
GND
VCC
A15
A16/S3
A17/S4
A18/S5
A19/S6
SSO (HIGH)
MN/MX
A14
A13
A12
A11
A10
A9
A8
AD7
(I
RD
AD6
I
HOLD (RQ/GTO)
HLDA (RQ/GT1)
AD5
AD4
AD3
AD2
AD1
ADO
'NMI
WR (LOCK)
IO/M{S2)
DT/A (51)
DEN (SO)
ALE (OSO)
INTA(OS1)
TEST
READY
RESET
INTR
ClK
GND
Fig.2a MSM80C88RS
~ ~ ~ ~
MSM8OC88GS (Top View)
56 Lead Plastic Flat Package
I\)
w
.".
z C) z < < z
0
0 z0 0
(')
(')
.".
~
(0
~ ~ ~ ~
(j)
(')
(')
(11
'-J
enw ~
.".
.".
I\)
A9
w
A8
.".
AD7
(11
AD6
(j)
0
I\)
N.C.
~
A 19/56
.".
0
SSO (HIGH)
w
MN/iliix
(0
w
OJ
RD
w
HOLD (RO/GTO)
-.J
N.C.
w
N.C.
en
w
N.C.
w
N.C.
w
w
w
HlDA (RO/GT1 )
(j)
N.C.
OJ
AD5
(0
AD4
<5
AD3
~
AD2
;;:;
AD1
W
ADO
~
.".
I\)
~
w
0
I\)
(0
U;
m~
Z
z z C) < z
Z (')
r
-I
0 z (')
~
:D
A
00 to
0
I\)
0
~
o (')
I\)
I\)
w ~
I\)
Z
0 0
I\)
(11
:D J)
m m
(f)
m 0
l>
-I
-<
Fig.2b MSM80C88GS
78
(f)
(11
OJ
N,C.
A10
~
I\)
(j)
I\)
OJ
r
> _
~I l-ll>
Z
-I
m
a
en
~
p
8
WR (LOCK)
IO/M (S2)
DT/R (51)
DEN (SO)
- - - - - - - - - - - - - - - - - - - . CPU· MSM80C88RS/GS •
ABSOLUTE MAXIMUM RATINGS
Limits
Symbol
Power Supply Voltage
VCC
-0.5 - +7
V
VIN
-0.5 - V CC +0.5
V
VOUT
-0.5 - V CC +0.5
V
MSMOOC88RS
Input Voltage
Output Voltage
Storage Temperature
Power Dissipation
I
MSMOOC88GS
-65- 150
Tstg
I
1.0
PD
Conditions
Unit
Parameter
With respect to GND
°c
-
W
Ta = 25°C
0.7
OPERATING RANGE
Parameter
Unit
Symbol
Limits
Power Supply Voltage
VCC
3-6
V
Operating Temperature
TOp
-40 - 85
°c
RECOMMENDED OPERATING CONDITIONS
Symbol
MIN
TYP
MAX
Power Supply Voltage
Parameter
VCC
4.5
5.0
5.5
V
Operating Temperature
TOp
-40
+25
+85
°c
"L" Input Voltage.
VIL
"H" Input Voltage
*1 Only CLK,
VIH
*2 Reset & Ready,
Unit
-0.5
+0.8
V
(*1 )
Vec-0.8
VCC +0.5
V
(*2)
3.0
VCC +0.5
V
(*3)
2.2
VCC +0.5
V
*3 Except CLK, Reset and Ready
DC CHARACTERISTICS
o
(Vee = 4.5V to 5.5V, Ta = -40 e to +85°e)
Parameter
Symbol
"L" Output Voltage
VOL
"H" Output Voltage
VOH
MIN
TYP
MAX
0.4
3.0
VCC-O·4
Unit
Conditions
V
10L = 2.5mA
V
10H =-2.5 mA
10H = -100J,LA
Input Leak Current
III
-1.0
+1.0
J.lA
O:s. VI:s. VCC
Output Leak Current
ILO
-10
+10
J.lA
O:s. VO:s. VCC
Operating Supply Current
ICC
55
mA
Cin
5
pF
Cout
15
pF
*4
CI/O
20
pF
*4
Input Capacitance
Output Capacitance
I/O Capacitance
*4.Test Conditions:
TCLCL=200NS, Ta='25°C
CL = OpF, at Reset
*4
a) Freq = 1 MHz.
b) Unmeasured Pins at GND.
c) Vin at 5.0V or GND.
79
• CPU • MSM80C88RS/GS •
A.C. CHARACTERISTICS
(Vcc
=
4.SV to
s.sv, Ta =
-40°C to +8SoC)
Minimum Mode System
Timing Requirements
Symbol
MIN
MAX
Unit
ClK Cycle Period
TClCl
200
500
NS
ClK low Time
TClCH
11B
NS
ClK High Time
TCHCl
65
NS
Parameter
ClK Rise Time (From 1.0V to 3.5V)
TCH1CH2
10
ClK Fall Time (From 3.5V to 1.0V)
TCl2Cl1
10
Data in Setup Time
TDVCl
Data in Hold Time
NS
NS
30
NS
NS
TClDX
10
RDY Setup Time into MSM 82CB4A (See Notes 1,2)
TR1VCl
35
NS
RDY Hold Time into MSM 82C84A (See Notes 1, 2)
TClR1X
0
NS
READY Setup Time into MSM 80CB8
TRYHCH
110
NS
READY Hold Time into MSM BOCB8
TCHRYX
30
NS
READY Inactive to ClK (See Note 3)
TRYlCl
-8
NS
HOLD Setup Time
THVCH
35
NS
INTR, NMI, TEST Setup Time (See Note 2)
TINVCE
30
NS
Input Rise Time (Except ClK) (From 0.8V to 2.2V)
TILIH
15
NS
Input Fall Time (Except CLK) (From 2.2V to 0.8V)
TIHll
15
NS
Unit
Timing Responses
Symbol
MIN
MAX
Address Valid Delay
TClAV
10
110
Address Hold Time
TClAX
10
Parameter
Address Float Delay
TClAZ
TClAX
ALE Width
TlHll
TClCH·20
A lE Active Delay
TCllH
80
ALE Inactive Delay
TCHll
85
Address Hold Time to ALE Inactive
TllAX
TCHCl·10
Data Valid Delay
TClDV
10
Data Hold Time
TCHDX
10
NS
Data Hold Time after WR
TWHDX
TClCH·30
NS
Control Active Delay 1
TCVCTV
10
110
NS
Control Active Delay 2
TCHCTV
10
110
NS
Control Inactive Delay
TCVCTX
10
110
Address Float to RD Active
TAZRl
0
RD Active Delay
TClRl
10
165
NS
RD Inactive Delay
TClRH
10
150
NS
RD Inactive to Next Address Active
TRHAV
TClCl·45
H lDA Valid Delay
TClHAV
10
RD Width
TRlRH
2TClCl·75
NS
WR Width
TWlWH
2TClCl·60
NS
TClCH-60
80
NS
NS
NS
NS
NS
110
NS
NS
NS
NS
160
NS
Address Valid to ALE low
TAVAl
Output Rise Time (From O.BV to 2.2V)
TOlOH
20
NS
Output Fall Time (From 2.2V to O.BV)
TOHOl
15
NS
NOTES: 1. Signals at MSM 82C84A shown for reference only.
2. Setup requirement for asynch(onous signal only to guarantee recognition at next ClK.
3. Applies only to T2 state. (Bns into T3)
80
NS
NS
NS
- - - - - - - - - - - - - - - - - - - , - - - . CPU • MSM80C88RS/GS •
Max. mode system (Using MSM 82C88 Bus Controller)'
Timing Requirement
Symbol
MIN
MAX
Unit
C lK Cycle Period
Parameter
TCLCL
200
500
NS
ClK LOVliTime
TCLCH
118
ClK High Time
TCHCL
65
NS
NS
ClK Rise Time (From 1.0V to 3.5V)
TCH1CH2
10
NS
ClK Fall Time (From 3.5V to 1.0V)
TCL2CL1
10
NS
Data in Setup Time
TDVCl
30
NS
Data in Hold Time
TCLDX
10
NS
R D Y Setup Time into MSM 82C84A (See Notes 1, 2)
TR1VCL
RDY Hold Time into MSM 82C84A (See Notes 1,2)
TCLR1X
0
NS
READY Setup Time into MSM 80C88
TRYHCH
110
NS
READY Hold Time into MSM 80C88
TCHRYX
30
NS
READY Inactive to CLK (See Note 3)
TRYLCL
-8
NS
Setup Time for Recognition (NM1, INTR, TEST) (See Note 2)
TINVCH
30
NS
RQ/GT Setup Time
TGVCH
30
NS
RQ Hold Time into MSM 80C88
TCHGX
40
35
NS
NS
Input Rise Time (Except CLK) (From 0.8V to 2.2V)
TILIH
15
NS
Input Fall Time (Except CLK) (From 2.2V to 0.8V)
TIHIL
15
NS
81
• CPU· MSM80C88RS/GS • - - - - - - - - - - - - - - - - - Timing Responses
Symbol
MIN
MAX
Unit
Command Active Delay (See Note 1 )
Parameter
TClMl
5
45
NS
Command Inactive Delay (See Note 1)
TClMH
5
35
NS
110
NS
READY Active to Status Passive (See Note 4)
TRYHSH
Status Active Delay
TCHSV
10
110
NS
Status Inactive Delay
TClSH
10
130
NS
Address Valid Delay
TClAV
10
110
NS
Address Hold Time
TClAX
10
Address Float Delay
TClAZ
TClAX
Status Valid to ALE High (See Note 1)
Status Valid to MCE High (See Note 1 )
I
II
NS
TSVlH
35
NS
TSVMCH
35
NS
ClK low to ALE Valid (See Note 1 )
TCllH
35
NS
ClK low to MCE High (See Note 1)
TClMCH
35
NS
35
NS
35
NS
110
NS
ALE Inactive Delay (See Note 1)
TCHll
MCE Inactive Delay (See Note 1)
TClMCl
4
Data Val id Delay
TClDV
10
Data Hold Time
TCHDX
10
Control Active Delay (See Note 1 )
TCVNV
5
45
Control Inactive Delay (See Note 1)
TCVNX
5
45
Address Float to R D Active
TAZRl
0
RD Active Delay
TClRl
10
165
RD Inactive Delay
TClRH
10
150
TRHAV
TClCl-45
-
-
RD Inactive to Next Address Active
NS
NS
NS
NS
NS
NS
NS
Direction Control Active Delay (See Note 1 )
TCHDTl
50
NS
Direction Control Inactive Delay (See Note 1 )
TCHDTH
35
NS
GT Active Delay
TClGl
0
85
NS
GT Inactive Delay
TClGH
0
85
NS
2TClCl·75
RD Width
TRlRH
Output Rise Time (From 0.8V to 2.2V)
TOlOH
20
NS
Output Fall Time (From 2.2V to O.8V)
TOHOl
15
NS
NOTES: 1.
2.
3.
4.
82
NS
80
Signal at MSM 82C84A and MSM82C88 shown for reference only.
Setup requirement for asynchronous signal only to guarantee recognition at next ClK.
Applies only to T2 state. (8ns into T3)
Applies only to T3 and wait states.
NS
• CPU· MSM80C88RS/GS •
A.C. TESTING INPUT, OUTPUT WAVEFORM
2.4
=x
1.5
TEST POINTS
1.5
)C
0 . 4 5 1 . ... -_ _ _......,._ _ _ _ _ _•
A.C. TESTING: INPUTS ARE DRIVEN AT 2.4V
FOR A LOGIC "1" AND 0.45V FOR A LOGIC
"0" TIMING MEASUREMENTS ARE 1.5V FOR
BOTH A LOGIC "1" AND "0"
A.C. TESTING LOAD CIRCUIT
l
CL
=
100pF
CL INCLUDES JIG CAPACITANCE
TIMING CHART
Minimum Mode
T4
VIH
CLK (MSM B2CB4A Output I
VIL
laiM.
SSO
A15-AB
A19/S6-A16/S3
ALE
RDY (MSMB2CB4A Inputl
SEE NOTE 4
READY (MSM80C88 Input I
AD7-ADO
READ CYCLE
(NOTE 11
(WR. INTA " VOHI
TCHCTV
DT/R
DEN
83
• CPU· MSM80C88RS/GS • .:..----------~-------Minimum Mode (Continued)
VIH
CLK (MSM 82C84A Output)
VIL
C
101M:
SSO
I
,A19/S6-A16/S3
ALE
AD7-ADO
WRITE CYCLE
(NOTE 1)
(RD. INTA.
DT/R=VOH)
DEN
AD7-ADO
DT/R
INTA CYCLE
(NOTES 1 & 3)
(RD.WR =.vOH
BHE = VOL)
SOFlWARE HAL TiN'i'A = VOH
DT/R = INDETERMINATE
RD.iWi.
INVALID ADDRESS
SOFlWARE HALT TCLAV
TCLAV
NOTES:
1. All signals switch between VOH and VOL unless otherwise specified.
2. ROY is sampled near the end of T2. T3. TW to determine if TW machines states are'to be inserted.
3. Two INTA cycles run back-to-back. The MSM 80e88 LOCAL AOOR/OATA BUS is floating during both INTA
cycles. Control signals shown for second INTA cycle.
4. Signals at MSM 82C84A 'shown for reference only.
5. All timing measurements are made at 1.5V unless otherwise noted.
84
- - - - - - - - - - - - - - - - - - . CPU· MSM80C88RS/GS •
Maximum Mode
T2
T1
j--- -
TCH1CH2_
VIH
ClK (MSMS2C84A OUTPUT)
I'-----J
Vil -.I
TCLAV--
r-
1------
TCH5V
'---
"------I
!-TCHCL..
X
-
f/////Ii
A15-A8
..
ALE (MSMS2CS8
OUTPUT)
,
I1:L~V
I--- TfTLt:~X-o
~-
56-53
'---
I
I
::~~i
-----
I-
"~~
R"OV '"'" "'" IN'UTI!
~
AD7-ADO
~
TAYHSH
TA1VC,L
~\\\\\\\\\W
~\\\
~TCLA1X
--
_TCHAYX
~
TCLAXITAYHCH"'l01
TCLAZI-
'AD7-AD~
TAiAL_
I--
TDVCL-.... TCL°X,I
1
:7\
\.I
J.,
DATA IN
DTiR'
MSM 82C88
OUTPUTS
SEE NOTE 5,6
TCLAL
I
,I
-t:
TALAH
\
TCLMH_
TCLML--MADC OA lORe
\
TCVNV--
DEN
F~O~~
TCLAH
v1
TCHDTL-
r-
r---
\
ADY (MSM 82C84A INP UTI
READ CYCLE
1..------
+CHLL
1
TCLAV ....
\
TCHDX'-
X
IA19_A16(
J
SEE NOTE 5
-------\
I(//#(SEE NOTE S)
A15-AS
1\
A19/56-A16/S3
TSVlHTCLLH-
r
I--TCLSH
S2. Sf,"SO (EXCEPT HALT)
-
~rL
'--TCLCH.
I
aso, aS1
TW
rr--;
~
v-----,
,r---\
T4
T3
I-- TCL2CL 1
I---TCLCL-_
,
IrTCVNX--
TAHAV
~
r
I~\
C
C
"""
\
/
~
85
• CPU . MSM80C88RS/GS •
Maximum Mode (Continued)
T1
T2
T4
T3
TW
VIH
ClK (MSM82C84A OUTPUTS)
Vil
52, sf, SO
(EXCEPT HAL TI
WRITE CYCLE
A07-AOO
OEN
MSM 82C88 OUTPUTS
SEE NOTES 5, 6
ANMCOR
Aibwc
iVlWTCOR
IOWC
INTA CyCLE
A15-A8
(SEE NOTES 3 & 41
FLOAT
A07-AOO
I
~O~~ ----I--'
I
OT/R
MSM 82C88 OUTPUTS
SEE NOTES 5, 6
INTA
OEN
SOFTWARE HALT
IOEN VOL; RD, MRDC,
fOR-C-,
MW-l'C, AMWC,
10WC-, AIOWC,INTA,
VOHI
A07-AOO, A15-A8
INVALIO AOORESS
TCLAV
\'---_---J/
\~-------
\
\._------
NOTES:
1. All sIgnals sWItch between VOH and VOL unless otherwIse spec,f,ed
2 RDY IS sampled near the end of T2, T3, TW to determIne If TW mach,nes states are to be Inserted.
3 Cascade address IS valid between first and second INTA cycle.
4. Two INTA cycles run back-to-back. The MSM 80C88 LOCAL ADDR/DATA BUS IS floating dUling both INTA cycles
Control for pOi'nter address is shown for second INTA cycle.
5. Signal at MSM 82C84A and MSM82C88 shown for reference only.
6
The Issuance of the MSM 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA
and DEN) lags the active high MSM 82C88 CEN.
All timing measurements are made at 1.5V unless otherwise noted.
Status Inactive In state lust pilar to T4
86
r----
- - - - - - - - - - - - - - - - - - . CPU· MSM80C88RS/GS •
Asynchronous Signal Recognition
NMI
"'~
,m
)
INTR
TEST
SIGNAL
==:X
-n,,,"
'0", "
:
NOTE: 1. SETUP REQUIREMENTS FOR ASYNCHRONOUS
SIGNALS ONLY TO GUARANTEE RECOGNITION
AT NEXT CLK.
Bus Lock Signal Timing (Maximum Mode Only)
Reset Timing
VCC
CLK
'DO'
~~
__________
CLK
~
RESET
::; 4 CLK CYCLES
Request/Grant Sequence Timing (Maximum Mode Only)
CLK
~~~is:~2i:,1~-AS ~I------------~I
:52,51, so,
MSM SOCSS
1-1--------~
COPROCESSOR
An, COCK
(SEE NOTE 11
NOTE: 1. THE COPROCESSOR MAY NOT DRIVE THE SUSSES OUTSIDE
THE REGION SHOWN WITHOUT RISKING CONTENTION.
Hold/Hold Acknowledge Timing (Minimum Mode Only)
CLK
HLDA
I--_ _ _ _ _ _ _
A07-ADO, A15-A8
A19/S6-A16/S3,
RDL-
MSM SOCSS
~
____________
~I~----~-J
I
~
,~Ir\.._TC_L_A_Z
"
_ _ _..;
COPROCESSOR
MSM BOCSS
I-_ _ _ _ _ _ _ _ _ _J
IO/IYL _ _
DT/R, WR, DEN
87
• CPU· MSM80C88RS/GS •
PIN DESCRIPTION
ADO-AD7
ADDRESS DATA BUS: Input/Output
These lines are multiplexed address and data bus.
These are address bus at T1 cycle and data bus at
T2, T3, TW and T4 cycle.
These lines are high impedance during interrupt
acknowledge and hold acknowledge.
INTR
INTERRUPT REQUEST: Input
This line is level triggered interrupt request signal
which is sampled during the last clock cycle of
instruction and string manipulation.
It can be internally masked by software.
This signal is active high and internally synchronized.
A8-A15
ADDRESS BUS: Output
These lines are address bus of bit 8 thru 15 at all
cycles.
These lines do not have to be latch by ALE signal.
These lines are high impedance during interrupt
acknowledge and hold acknowledge.
TEST
TEST: Input
This line is examined by "WAIT" instruction.
When TEST is high, CPU enter idle cycle.
When TEST is low, CPU exit idle cycle.
A16/S3, A17/S4, A18/S5, A19/S6
ADDRESS/STATUS: Output
These are four most significant address at T1 cycle.
Accessing I/O port address, these are low at T1
Cycle.
These lines are Status lines at T2, T3, TW and T4
Cycle.
S5 indicate interrupt enable Flag.
S3 and S4 are encoded as shown.
NMI
NON MASKABLE INTERRUPT: Input
This line causes type 2 interrupt.
NMI is not maskable.
This signal is internally synchronized and needs 2
clock cycles pulse width.
RESET
RESET: Input
This signal causes CPU to initialize immediately.
This signal is active high and must be at least four
clock cycles.
S3
S4
0
0
Alternate Data
elK
1
0
Stack
0
1
Code or None
CLOCK: Input
This signal provide the basic timing for internal
circuit.
1
1
Data
Characteristics
These lines are high impedance during hold acknowledge.
RD
READ: Output
This line indicates that CPU is memory or I/O read
cycle.
This line is read strobe signal when CPU read data
from memory or I/O device.
This line is active low.
This line is high impedance during hold acknowledge.
READY
READY: Input
This line indicates to CPU that addressed memory
or I/O device is ready to read or write.
This lihe is active high.
If the setup and hold time is out of specification
illegal operation will occur.
88
MN/MX
MINIMUM/MAXIMUM: Input
This signal selects CPU's operate mode.
When VCC is connected. CPU operates minimum
mode.
When GND is connected. CPU operates maximum
mode.
Vee
VCC:
+ 3 -+6 V supplied.
GND
GROUND:
The following pin function descriptions are maximum mode only.
Other pin functions are already described.
- - - - - - - - - - - - - - - - - - - - , - . CPU· MSM80C88RS/GS •
SO, S1, S2
STATUS: Output
These lines indicate bus status and they are used by
the MSM82C88 Bus Controller to generate all
memory and I/O access control signals.
These lines are high impedance during hold
acknowledge.
These status lines are encoded as shown.
Characteristics
S2
S1
SO
o (LOW)
0
0
0
0
1
Read I/O Port
0
1
0
Write I/O Port
Interrupt acknowledge
0
1
1
Halt
1 (HIGH)
0
0
Code Access
1
0
1
Read Memory
1
1
0
Write Memory
1
1
1
Passive
When this line is low. CPU select memory address
space and when it is high. CPU select I/O address
space.
This line is high impedance during hold acknowledge.
WR
WRITE: Output
This line indicates that CPU is memory or I/O
write cycle.
This line is write strobe signal when CPU write data
to memory or I/O device.
This line is active low.
This line is high impedance during hold acknowledge.
INTA
INTERRUPT ACKNOWLEDGE: Output
This line is read strobe signal for interrupt acknowledge cycle.
This line is active low.
RQ/GTO
RQ/GT1
REQUEST/GRANT: Input/Output
These lines are used for Bus Request from other
device and Bus GR(\NT to other device.
These lines are bidirectional and active low.
LOCK
LOCK: Output
Th is line is active low.
When this line is low, other device could not gain
control of the bus.
This line is high impedance during hold acknowledge.
aSO/QS1
QUEUE STATUS: Output
These lines are Queue Status that indicate internal
instruction queue status.
QS1
QSO
o (LOW)
0
No Operation
0
1
First Byte of Op Code from
Queue
1 (HIGH)
0
Empty the Queue
1
1
Subsequent Byte from Queue
Characteristics
The following pin function descriptions are minimu m mode only. Other pin functions are already
described.
ALE
ADDRESS LATCH ENABLE: Output
This line is used for latching address into
MSM82C12 address latch. It is positive pulse and
trailing edge is used to strobe the address. This
line is never floated.
DT/R
DATA TRANSMIT/RECEIVE: Output
This line is used for control a direction of bus
transceiver.
When this line is high. CPU transmit data, and
when it is low. CPU receive data.
This line is high impedance during hold acknowledge.'
DEN
DATA ENABLE: Output
This line is used for control an output enable of
bus tr"ansceiver.
This line is active low. This line is high impedance
during hold acknowledge.
HOLD
HOLD REQUEST: Input
This line is used for Bus Request from other
device.
This line is active high.
HLDA
HOLD ACKNOWLEDGE: Output
Th is I ine is used for Bus Grant to other device.
This line is active high.
10lM
SSO
STATUS: Output
STATUS: Output
This line is logically equivalent to
mum mode.
This line selects memory address space or I/O
address space.
SO
in the maxi-
89
• CPU· MSM80C88RS/GS •
~-----------------
FUNCTIONAL OEseR IPTION
GENERAL OPERATION
The. internal function of MSM80C88 consist of Bus
Interface Unit (BIU) and Execution Unit (EU). These
units operate mutually but perform as separate processor.
B I U performs instruction fetch and queueing,
operand fetch, OAT A read and write address relocation
and basic bus control. By instruction pre-fetch wh ile
waiting for decoding and execution of instruction.
CPU's performance is increased. Up to 4-bytes of instruction stream can be queued.
EU receives pre-fetched instructions from BIU
queue, decodes and executes instruction and provided
un-relocated operand address to BIU.
MEMORY ORGANIZATION
MSM80C88 has 20-bit address to memory. Each
address has 8-bit data width. Memory is organized
000001-! to F F F FF H and is logically divided four
segment, code, data, extra data and stack segment.
Each segment contain up to 64 Kbytes and locate on
16-byte boundary. (Fig.3a)
All memory references are made relative to segment register which is according to select rule. Memory
location F F F FOH is start address after reset and
OOOOOH through 003FFH are reserved for interrupt
pointer, where 256 types interrupt pointer are there.
Each interrupt type has 4-byte pointer element
consist of 16-bit segment address and 16-bit offset
address.
Memory Organization
Reserved Memory Locations
.r---:l FFFFFH
I
64 KB
}CODE SEGMENT
r----'-----.'I:---c1
XXXX0 H
} ST ACK SEGMENT
+OFFSET
SEGMENT
REGISTER FILE
,-'--+t-----I
CS
} DATA SEGMENT
SS
OS
}-----t----L
ES
D
H}EXTRADATA
SEGMENT
~OOOOOH
Memory Reference Need
Segment Register Used
Segment Selection Rule
Instructions
CODE (CS)
Automatic with all instruction prefetch.
Stack
STACK (SS)
All stack pushes and pops. Memory references
relative to BP base register except data references.
Local Data
DATA (OS)
Data references when relative to stack, destination
of string operation, or explicitly overridden.
External (Global) Data
EXTRA (ES)
Destination of string operations: Explicitly selected
using a segment override.
MINIMUM AND MAXIMUM MODES
MSM80C88 has two system mode: minimum and
maximum mode. As using maximum ode, it is easy to
organize multi-CPU system with MSM82C88 Bus
Controller which general bus control signal generate.
90
As using minimum mode, it is easy to organize
simple system by generating bus control signal itself.
MN/MX is mode select pin. Definition of 24-31, 34
pin changes depend on the MN/MX pin.
- - - - - - - - - - - - - - - - - - - . CPU· MSM80C88RS/GS •
BUS OPERATION
MSM80C88 has a time multiplexed address and
data bus. If non·mu Itiplexed bus is desired for system,
it is only to add the address latch.
CPU bus cycle consists of at least four clock cycles.
T1, T2, T3 and T4. (Fig.4)
The address output occurs during T1 and data
transfer occurs during T3 and T4. T2 is used for
changing the direction of the bus at read operation.
When the device which is accessed by CPU is not ready
to data transfer and send to CPU "NOT READY".
TW cycles are inserted between T3 and T4.
When bus cycle is not needed. T1 cycles are
inserted between nus cycles for internal execution. At
T1 cycle A LE signal is output from CPU or MSM82C88
depending in MN/MK At the trailing· edge of ALE,
a valid address may be latched. Status bits SO, S1
and S2 are used in maximum mode, by the bus
controller to recognize the type of bus operation
according to the following table.
S2
S1
So
o (LOW)
0
0
0
0
1
Read I/O
0
1
0
Write I/O
Halt
0
1
1
1 (HIGH)
0
0
1
0
1
1
1
0
1
1
1
..
-
Status bits
A16-A19, and
through T4. S3
was selected on
ing table.
S3 through S6 are multiplexed with
therefore there are valid during T2
and S4 indicate which segment register
the bus cycle, according to the follow·
S4
S3
Characteristics
o (LOW)
0
Alternate Data (Extra Segment)
0
1
Stack
1 (HIGH)
0
Code or None
1
1
Data
S5 indicates interrupt enable Flag.
I/O ADDRESSING
MSM80C88 has 64 Kbyte I/O. When CPU accesses
I/O device, address AO-A 15 are same format as a
memory access, and A 16-A 19 are low.
I/O ports address are same as memory.
Characteristics
Interrupt acknowledge
I nstruction Fetch
-----------
---
.-
Read Data from Memory
Write Data to Memory
- - - - - - ---_._.- _.-
-
Passive (no bus cycle)
91
• CPU· MSM80C88RS/GS • - - - - - - - - - - - - - - - - - Basic System Tim ing
(4 + N*WAIT) = TCY
T2
I
T3
hWAITI
ClK
11
ALE
I
A19-A16
ADDRI
STATUS
S6-S3
86-S3
----'
ADDR
A15-A8
A15-A8
07-00
VALID
ADDRI
DATA
READY
READY
READY
WAIT
WAIT
DT/R
\'-------',
92
"I
14 + N'WAITJ· TCY
T4
- - - - - - - - - - - - - - - - - - . CPU • MSM80C88RS/GS •
EXTERNAL INTERFACE
RESET
CPU initialization is executed by RESET pin.
MSM80C88's RESET High signal is required for greater
than 4 clock cycles.
Rising edge of RESET terminate present operation
immediately. Falling edge of RESET triggered internal
reset sequence for approximately 10 clock:cycles. After
internal reset sequence is done, normal operation begin
from absolute location FFFFOH.
INTERRUPT OPERATIONS
Interrupt operation is classified as software or
hardware and hardware interrupt is classified as nonmaskable or maskable.
Interrupt causes to a new program location which
is defined interrupt pointer table, according to interrupt
type. Absolute location OOOOOH through 003FFH is
reserved for interrupt pointer table. Interrupt pointer
table consist of 256-element, and each element is 4
bytes in size and corresponds to an 8 bit type number
which is sent from interrupt request device during interrupt acknowledge cycle.
INTERRUPT ACKNOWLEDGE
During the interrupt acknowledge sequence,
further interrupts are disabled. Interrupt enable bit is
reset by any interrupt, after Flag register is automati·
cally pushed onto the stack. During acknowledge
sequence. CPU emits the lock signal from T2 of first
bus cycle to T2 of second bus cycle. At second bus
cycle, byte is fetched from external device as a vector
which identified the type of interrupt, and this vector is
multiplied by four and used as a interrupt pointer
address (INTR only l.
The Interrupt Return (lRET) instruction includes
a Flag pop operation which returns the original interrupt enable bit when it restores the Flag.
HALT
When Halt instruction is executed, CPU enter Halt
state. Interrupt request or RESET will force the
MSM80C88 out of the Halt state.
NON-MASKABLE INTERRUPT (NMt)
MSM80C88.has Non-maskable Interrupt (NM1)
which is higher priority than maskable interrupt request
(lNTR).
NMI request pulse width need minimum 2 clock
cycles. NM I will be serviced at the end of the current
instruction or between string manipulation.
SYSTEM TIMING-MINIMUM MODE
Bus cycle begins T1 with ALE signal. The trailing
edge of ALE is used to latch the address. From T1 to
T4 the 10/M signal indicates a memory or I/O operation. From T2 to T4, the address data bus change
address bus to data bus.
The read (RD), write (WRI. interrupt acknowledge
(INT A) signal causes the addressed device to enable data
bus. These signal becomes active at beginning of T2 and
inactive at beginning of T4.
MASKABLE INTERRUPT (lNTR)
MSM80C88 provides an another interrupt request
(lNTR) which can be m~sked by software. INTR is
level triggered, so it must be hold until interrupt request
is acknowledged.
INTR will be serviced at the end of the current
instruction or between string manipulation.
SYSTEM TIMING -MAXIMUM MODE
At maximum mode, MSM82C88 Bus Controller
is added to system. CPU sends status information to
Bus Controller. Bus timing signals are generated by
Bus Controller. Bus timing is almost same as minimum
mode.
Interrupt Acknowledge Sequence
I
ALE
Tl
I
T2
I
T3
I T41TII
Tl
I
T2
I
T3
T4
~r-f\-----\'--------lIS!-
ADO~::7=>FLOA~
_--II
~~YPEVEC;:
93
cto
~
•
DATA TRANSFER
MOV = Move:
Register/memory to/from register
Immediate to register/memory
Immediate to register
Memory to accumulator
Accumulator to memory
Register/memory to segment register
Segment register to register/memory
PUSH
1
1
1
1
1
1
3
2 1 0 7 6
1 0 d w mod
0 1 1 w mod
reg
w
0
0
0
0
1
1
1
1
0
1
1
0
w
w
0
0
mod
mod
5 4
3
reg
0
0
0
data
addr-Iow
addr-Iow
0 reg
0 reg
2
1 0
rim
rim
rim
rim
XCHG
5 4
3
2
1
0
7 6
5 4
3
2
1
01
data if w
=1
=1
I
:
o
(')
CO
CO
se.
C)
1
1
1
0
0
0
1
0
0
1 1
1 0
reg
1
reg
1 1
1
1
mod
1
1
0
rim
en
•
0
0
0
0
0
0
1
1 1
reg
1
reg
1 1
1
1
0
0
0
0
0 0
l' 0
1
1
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
1
1 0
0 0
1 0
1 0
0 0
0 0
0 0
0 0
0
0
1
0
0
0
1
1
i
1
1
1
1
1
0
0
0
1
1
1
mod
0
0
0
rim
1
1 w mod
reg
reg
rim
I
1
w
port
W
I
I
= Output to:
Fixed port
Variable port
X LA T = Translate byte to A L
LEA = Load EA to register
LDS = Load pointer to DS
LES = Load pointer to ES
LAHF = Load AH with flags
SAHF = Store AH into flags
PUSHF = Push flags
POPF = Pop flags
s::en
s::CO
::17
= Input from:
Fixed port
Variable port
(')
"lJ
C
data
data if w
addr-high
addr-high
= Exchange:
Register/memory with register
Register with accumulator
OUT
7 6
= Pop:
Register/memory
Register
Segment register
IN
5 4
0- 0
1 0 0
0 1 1
0 1 0
0 1 0
0 0 0
0 0 0
6
1 0
= Push:
Register/memory
Register
Segment register
POP
7
1
1
1
1
1
1
1
1
1
0
1
0
1
0
0
1 1
1 1
1 1
1 1
w
w
1
1 mod
1 mod
0 mod
1
1 1 0
1 0 0
1 0 1
1 0
1 0
1 0
1 1
I
port
I
reg
reg
reg
rim
rim
rim
ARITHMETIC
ADD
= Add:
Reg./memory with register to either
Immediate to register/memory
Immediate to accumulator
ADC
= Add with
AAA
DAA
SUB
= ASCII adjust for add
= Decimal adjust for add
0
0
0
0
0
0
0 d
0 s
1 0
w mod
w mod
w
0
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
d
s
0
VJ mod
w mod
w
0
1
0
0
0
1
1
0
0
·1
0
1
1
1
0
1
0
1
0
0
0
1
1
reg
1 1
1 1
w mod
0
0 0
1 0
0 0
1
0
1
0
0
0
1
0
1
0 d
0 s
1 0
w mod
w mod
w
1
0
1
0
0
0
0
1
0
1
1
0
1
0 d
0 s
1 0
w mod
w mod
w
0
0
reg
0 0
data
rIm
rIm
reg
1 0
data
rIm
rIm
0
0
rIm
reg
0 1
data
rIm
rIm
reg
1 1
data
rIm
rIm
data
data if w
=1
data
data if w
=1
data
data if w
=1
data
data if w
=1
data if s:w
= 01
data if s:w
= 01
data if s:w
= 01
SBB
data if s:w
= 01
= SUbtract with
borrow:
Reg./memory and register to either
Immediate from register/memory
Immediate from accumulator
DEC
1
1
= subtract:
Reg./memory and register to either
Immediate from register/memory
Immediate from accumulator
0
0
0
..
o
"'tI
= Decrement:
C
Register /memory
Register
NEG = Change sign
1
1
0
1
0
1
1
1
1
1
0
1
1
0
1
0
1
0
0
0
0
0
0
1
0
1
1
1 1
0 0
1 1
1 1
1
1 w mod
reg
1 1 w mod
0
0
1
rIm
0
1
1
rIm
reg
1 1 1
data
rim
s:en
s:00
o
= Compare:
o
Register/memory and register
I mmediate with register/memory
Immediate with accumulator
AAS = ASCII adjust for subtract
co
0
0
0
= Increment:
Register/memory
Register
CMP
0
0
0
carry:
Reg./memory with register to either
Immediate to register/memory
Immediate to accumulator
INC
0
1
0
- - - -
--
0 d
0 s
1 0
1 1
----
w mod
w mod
w
1
rIm
data
data if w
data if s:w
=1
= 01
00
00
:tJ
~
C)
en
--'-----
•
C1'I
c
c(0
en
DAS = Decimal adjust for subtract
MUL = Multiply (unsigned)
JMUL = Integer multiply (signed)
AAM = ASCII adjust for multiply
DIV = Divide (unsigned)
IIJIV = Integer divide (signed)
AAD = ASCII adjust for divide
CBW = Convert byte to word
CWO = Convert word to double word
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
•
1
1
1
1
w mod
w mod
1
1
0
0
0
0
1
1
w mod
w mod
1 0 0
0
0 0
0 0
0
1
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
(')
rim
rim
0
1
""0
C
0
rim
rim
0
1
0
s:en
s:CO
8CO
CO
:::D
S!?
G')
(I)
•
LOGIC
NOT = Invert
SHL/SAL = Shift logical/arithmetic left
SHR = Shift logical right
SAR = Shift arithmetic right
ROL = Rotate left
ROR = Rotate right
RCL = Rotate left through carry
RCR = Rotate right through carry
AND
= And function
0 0
1 0
0 0
0
0
0
0
0
0
0
w mod
v w mod
v w mod
v w mod
v w mod
v w mod
v w mod
v w mod
1 0 0 0
0 0 0 0
0 0
d w mod
0 w mod
0 w
0
0
0
1
0 0
0 0
0
0
0
0
1
1
0
0
rim
rIm
rim
rim
rim
rim
rim
rim
reg
0 0
data
rim
rim
reg
0 0
data
rim
rim
reg
0 1
data
rim
rim
reg
1 0
data
rIm
data
data if w
=1
data
data if w
=1
data
data if w
=1
data if w
=1
data if w
=1
data if w
=1
data if w
=1
to flags, no result:
Register/memory and register
Immediate data and register/memory
Immediate data "and accu mu lator
OR
0
0
0
0
0
0
0
0
= And:
Reg./memory and register to either
Immediate to register/memory
Immediate to accumulator
TEST
1
0
0
0
0
0
0
0
0 0 0 0
0 w mod
1
1 0 1 1 w mod
0
0 0 w
0
0
= Or:
Reg./memory and register to either
Immediate to register/memory
Immediate to accumulator
0 0
0
0 0
0
0
0
0
0
0
0
0
0 0
1
0 0
1 0
0 0
d w mod
0 w mod
0 w
0
XOR = Exclusive or:
Reg./memory and register to either
Immediate to register/memory
Immediate to accumulator
0
0 0 d w mod
0 0 0 w mod
0 w
0
STRING MANIPULATION
REP = Repeat
MOVS = Move byte/word
CMPS = Compare byte/word
SCAS = Scan byte/word
LODS = Load byte/word to AL/AX
STOS = Store byte/word from AL/ AX
co
:""01
rim
•
data
data if w
=1
"C"
3:
3:
(I)
1
1
1
1
1
1
1 1 1 0 0
0 1 0 0 1
0 1 0 0 1
0 1 0 1 1
0 1 0 1 1
0 1 0 1 0
1
0
1
1
0
1
z
w
w
w
w
w
CO
o
(')
CO
CO
::D
(I)
C5
(I)
•
-c
CD
0)
CJMP
INT
•
=Conditional JMP
JE/JZ = Jump on equal/zero
JZ/JNGE = Jump on less/not greater or equal
JLE/JNG = Jump on less or equal/not greater
JB/JNAE = Jump on below/not above or equal
JBE/JNA = Jump on below or equal/not above
JP/JPE = Jump on parity/parity even
JO = Jump on over flow
JS = Jump on sign
JNE/JNZ = Jump on not equal/not zero
JNL/JGE = Jump on not less/greater or equal
IN LE/JG = Jump on not less or equal/greater
JNB/JAE = Jump on not below/above or equal
JNBE/JA = Jump on not below or equal/above
JNP/JPO = Jump on not parity/parity odd
JNO = Jump on not overflow
JNS = Jump on not sign
LOOP = Loop CX times
LOOPZ/LOOPE = Loop while zero/equal
LOOPNZ/LOOPNE = Loop while not zero/equal
JCXZ = Jump on CX zero
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
0
1
1
1
0
1
0
0
0
0
0
0
0
1 1
1 1
1 1
1 1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 0 0
1 1 0
1 1 1
1
1
1
1
1
1
1
1
1
1
1
1 0
0 1
1 0
1 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
0
1
0
1
1
0
0
1
0
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
disp
1
type
n
"g
C
~
(I)
~
Q)
o
n
Q)
Q)
::D
~
G)
(I)
•
= Interrupt:
Type speci fied
Type 3
INTO = Interrupt on overflow
IRET = Interrupt return
0
0
0
1 0
1 1
L.
PROCESSOR CONTROL
CLC = Clear carry
CMC = Complement carry
STC = Set carry
CLD = Clear direction
STD = Set direction
CLI = Clear interrupt
STI = Set interrupt
HLT=Halt
WAIT = Wait
ESC = Escape (to external device)
LOCK = Bus lock prefix
0 0
0 1
0 1
0 0
1 0 1
0 1 0
0 1 1
1 0 0
0 1 1
1
1
1
0
1
1 x
0 0
x
x
0
0
mod
x
x
x
rim
CONTROL TRANSFER
CALL = Call:
Direct within segment
Indirect within segment
Direct intersegment
7 6 5 4 3 2 1 0 7 6
1 1 1 0 1 0 0 0
1 1 1 1 1 1 1 1 mod
1 0 0 1 1 0 1 0
Indirect intersegment
1
1
1
1
1
1
1
1
Direct within segment
Direct within segment-short
Indirect within segment
Direct intersegment
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
0
1
Indirect intersegment
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
JMP
RET
= Unconditional
= Return
mod
5 4 3 2
1
0
1 0
0
7 6
5 4 3 2
disp-high
disp-Iow
1
0
7 6
5 4 3 2 1
01
rIm
offset-low
seg-Iow
rIm
0 1 1
offset-high
seg-high
Jump:
0
1
1
1
0
1
1
1
0
0
1 0
1 0
1
1
1
1
1
disp-Iow
disp
mod
mod
1 0 0
rIm
offset-low
seg-Iow
1 0 1
rIm
disp-high
offset-high
seg-high
from CALL:
Within segment
Within seg. adding immediate to SP
I ntersegment
Intersegment adding immediate to SP
1
0
data-low
data-high
data-low
data-high
1
0
•
n
"'a
C
s:
s:CO
(I)
o
n
CO
CO
:tI
S!?
C)
(I)
<0
<0
•
c
• CPU· MSM80C88RS/GS • - - - - - ' - - - - - - - - - - - - - - Footnotes:
AL = 8-bit accumulator
AX = 18-bit accumulator
CX = Co'unt register
OS = Data segment
ES = Extra segment
Above/below refers to unsigned value
Greater = more positive
Less = less positive (more negative) signed value
If d = 1 then "to" reg: If d = 0 then "from" reg.
If w = 1 then word instruction: If w = 0 then byte instruction
If
If
If
If
mod
mod
mod
mod
=
=
=
=
11 then
00 then
01 then
10 then
If rIm = 000 then
If rIm = 001 then
If rIm = 010 then
If rIm = 011 then
If rIm = 100 then
If rIm = 101 then
If rIm = 110 then
If rim = 111 then
OISP follows 2nd
rIm is treated as a REG field
OISP = 0*, disp-Iow and disp-high are absent
OISP = disp-Iow sign-extended to 16-bits, disp-high is absent
OISP = disp-high: disp-Iow
EA = (BX) + (SI) + OISP
EA = (BX) + (01) + OISP
EA = (BP) + (SI) + OISP
EA = (BP) + (01) + OISP
EA = (SI) + OISP
EA = (01) + OISP
EA = (BP) + OISP*
EA = (BX) + OISP
byte of instruction (before data if required)
* except if mod = 00 and rim = 110 then EA-disp-high: disp-Iow
If s:w = 01 then 16 bits of immediate data form the operand
If s:w = 11 then an immediate data byte is sign extended to form the 16-bit operand
If v = 0 then "count" = 1: If v = 1 then "count" in (CLI
x = don't care
z is used for string primitives for comparison with ZF FLAG
SEGMENT OVERRIDE PREFIX
00 1 ~eg 110
REG is assignee according to the following table:
16-Bit
000
001
010
011
100
101
110
111
(w =
AX
CX
OX
BX
SP
BP
SI
01
11
8-Bit (w=O)
000
AL
001
CL
010
OL
011
BL
100
AH
101
CH
OH
110
111
BH
Segment
00 ES
01 CS
10 SS
11 OS
Instructions which reference the flag register file as a 16-bit object use the symbol F LAGS to represent the file:
FLAGS = x:'x:x:x:(OF):(OF):( IF): (TF):(SF) :(ZF):X:(AF) :X:(PF):X:(CF)
100
1/0
OKI
semiconductor
MSM81C55RS/GS
2048 BIT CMOS STATIC RAM WITH I/O PORTS AND TIMER
GENERAL DESCRIPTION
The MSM81C55RS/GS is a 2k bit static RAM (256 byte) with parallel I/O ports and timer. It uses
silicon gate CMOS technology and consumes a standby current of 100 micro ampere maximum while the chip is
not selected. Featuring a maximum access time of 400 ns, the MSM81 C55RS/GS can be used in an 80C85A system
without using wait states. The parallel I/O consists of two 8-bit ports and one 6-bit port (both general purpose). The
MSM81C55RS,also contains a 14-bit programmable counter/timer which may be used for sequence-wave generation
or terminal count-pulsing.
FEATURES
• High speed and low power achieved with silicon gate
CMOS technology.
• 256 words x 8 bits
• Single power supply, 3 to 6V
• Completely static operation
• On-<:hip address latch
• 8-bit programmable I/O ports (port A and B)
• TTL Compatible
• RAM data hold characteristic at 2V
• 6-bit programmable I/O port (port C)
• 14-bit programmable binary counter/timer
• Multiplexed address/data bus
.40 pin DIP package (MSM81 C55RS)
.44 pin flat package (MSM81 C55GS)
• Direct interface with MSM80C85A (3MHz)
FUNCTIONAL BLOCK DIAGRAM
PORTA
10/M
ADo-7
256 x 8
STATIC
RAM
CE
ALE
AD
WR
RESET
TIMER IN
TIMER OUT
102
TIMER
B
B
PAO-7
PBO-7
B
VCC (+5V)
GND (OV)
PCo-s
- - - - - - - - - - - - - - - - - - - . I/O· MSM81C55RS/GS •
PIN CONFIGURATION
MSM81 C55RS (Top View)
PC3
PC4
40 Lead Plastic DIP
VCC
PC2
PCt
PCo
PB7
PB 6
PBs
PB4
PB3
PB2
PBt
PBo
PA7
PA6
PAs
PA4
PA3
PA2
PAt
PAo
TIMER IN
RESET
PCs
TIMER OUT
101M
CE
RD
WR
ALE
ADo
ADt
AD2
a
~
MSM81C55GS (Top View)
44 Lead Plastic Flat Package
I-a:
1I)~~~
uu('O_oruw-uu U z' U
UUal
0..0..0..0..
....
0..a:1-0..0..>
44 43 42 41 40 39 38 37 36 35 34
TIMER OUT
101M
~ <:)
~~
CE
31
RD
WR
30
29
ALE
28
ADo
ADt
AD2
AD3
26
25
N.C
27
10
24
11 ,
23
12 13 14 15 16 17 18 19 20 21 22
103
• I/O· MSM81C55RS/GS • - - - - - - - - - - - - - - - - - - ABSOLUTE MAXIMUM RATINGS
Limits
Parameter
Symbol
Supply Voltage
VCC
Input Voltage
VIN
Output Voltage
Storage Temperature
Conditions
Unit
MSM81C55GS
-0.5 to +7
Referenced to GNO
VOUT
Tstg
Power- Dissipation
I
MSM81C55RS
Ta = 25°C
Po
V
-0.5 to VCC + 0.5
V
-0.5 to VCC + 0.5
V
-55 to + 150
°c
I
1.0
W
0.7
OPERATING CONDITION
Parameter
Supply Voltage
Operating Temperature
Unit
Symbol
Limits
VCC
3to 6
V
TOp
-40 to +85
°c
RECOMMENDED OPERATING CONDITIONS
Symbol
Min.
Typ.
Max.
Supply Voltage
Parameter
VCC
4.5
5
5.5
Unit
V
Operating Temperature
TOp
-40
+25
+85
°c
"L" Level Input
VIL
-0.3
+0.8
V
"H" Level Input
VIH
2.2
VCC + 0.3
V
DC CHARACTERISTICS
Parameter
"L" Level Output Voltage
"H" Level Output Voltage
Symbol
VOL
VOH
Conditions
IOH = -400#LA
2.4
IOH = -40#LA
4.2
Input Leak Current
III
O~VIN ~ VCC
Output Leak Current
ILO
0~VOUT5VCC
CE
Standby Current
ICCS
Mean Operating Current
ICC
104
Min.
Typ.
IOL = 2mA
~ VCC-O.2V
VIH ~ VCC-O· 2V
VIL ~ VCC-O.2V
Memory' cycle time:
1#lS
VCC= 4.5V to
5.5V
Ta= -40°C to
85°C
Max.
Unit
0.45
V
V
V
-10
10
#LA
-10
10
#LA
100
#LA
5
mA
0.1
- - - - - - - - - - - - - - - - - - - . I/O· MSM81C55RS/GS •
AC CHARACTERISTICS
(Vcc = 4.5 to 5.5V, Ta = -40 to +85° C)
Symbol
Min.
Address/latch Set-up Time
Parameter
tAL
50
Max.
Unit
Latch/address Hold Time
tLA
30
ns
Latch/read (write) Delay Time
tLC
100
ns
Read/output Delay Time
tRD
170
ns
Address/output Delay Time
tAD
400
ns
Latch Width
tLL
Read/data Bus Floating Time
100
ns
100
ns
tRDF
0
Read (write)/Iatch Delay Time
tCL
20
ns
Re!ld (write) Width
tcc
250
ns
Data In/write Set-up Time
tow
150
ns
Write/data-in Hold Time
two
0
ns
Recovery Time
tRV
300
ns
Write/port Output Delay Time
twP
Port Input/read Set-up Time
tPR
70
ns
Read/port Input Hold Time
tRP
50
ns
Strobelbuffer Full Delay Time
Strobe Width
tss
Strobe/buffer Empty Delay Time
400
400
tSBF
200
ns
ns
tRBE
400
ns
tSI
400
ns.
Read/interrupt-off Delay Time
tRDI
Port Input/strobe Set-up TilTie
tpss
50
Strobe/port-input Hold Time
tPHS
120
Write/buffer-full Delay Time
Write/interrupt-off Delay Time
Timer Output Delay Time Low
Timer
Ou~put
Delay Time High
Read/data Bus Enable Delay Time
400
tSBE
twBF
400
ns
twl
400
ns
tTL
400
ns
400
ns
tRDE
Timer Cycle Time
tCYC
320
Timer Input Rise and Fall Times
tr,tf
Timer Input High Level Time
ns
ns
10
Timer Input Low Level Time
ns
ns
400
tTH
Load capaci"
tance: 150pF
ns
Strobe/interrupt-on delay time
Strobelbuffer-empty Delay Time
Remarks
ns
80-
ns
ns
ns
t1
80
ns
t2
120
ns
Note: Timing are measured with VL = 0.8V and VH = 2.2V for both input and output.
105
'. I/O· MSM81C55RS/GS • - - - - - - - - - - - - - - - - - - TIMING
Read Cycle
CE
loiM
I
III
ADo-7
I
ALE
RD
Write Cycle
106
- - - - - - - - - - - - - - - - - - - . I/O· MSM81C55RS/GS •
Strobe Input Mode
BF
tSBF--+---1
INTR
INPUT DATA
FROM PORT
Strobe Output Mode
BF
INTR
OUTPUT DATA
TOPORT ________________________~~---------------------------
107
• I/O· MSM81C55RS/GS • - - - - - - - - - - - - - - - - - - Basic Input Mode
PORT INPUT
I
(I
DATABUS
___________
=-~=====_=x
B.ic Output Mode
DATA BUS
PORT OUTPUT
Note: The DATA BUS timing is the same as the read and write cyc,les.
Timer Waveforms
Load Counter from
Count length register
Load Counter from
Count length register1
1
2
I
5
1
4
.1
3
I
2
I
---I
1
I
5
(T.C')
tf
TIMER OUT
(pulse)
TIMER OUT
(square wave)
\
~
(note)
_ _ _ _ _ _J
I
Note: Periodically output according to the output mode (m1=1) programming contents.
108
- - - - - - - - - - - - - - - - - - . I/O· MSM81C55RS/GS •
RAM DATA HOLD CHARACTERISTICS AT LOW SUPPLY VOLTAGE
Item
Data Holding Supply Voltage
Data Holding Supply Current
Symbol
Condition
=OVor VCC, ALE =OV
VCCH
VIN
ICCH
VCC = VCCH, ALE =0
VIN == OVor VCC
Specification
Unit
Min.
Typ.
Max.
2.0
-
-
-
0.05
20
Il
-
-
ns
Set-up Time
tsu
30
Hold Time
tR
20
V
ns
Two ways to place device in standby mode:
(1) Method using CE
tsu
Standby mode
5V
4.5V
VCC
VCCH
ALE
0.8V
OV
2.2V
CE
VCCH
(2)
Method using RESET
t----Standby
mode---.......
VCCH-----RESET
G N D - - - - - . . . L - - - - - - - _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Note: In this case, the CIS register is reset, the port is set into the input mode, and the timer stops.
109
• I/O· MSM81C55RS/GS • - - - - - - - - - - - - - - - - - PIN FUNCTIONS
Symbol
RESET
ALE
ADO~7
I~
CE
10/M
-RD
WR
PAO~7
(PBO~7)
PCo~s
TIMER IN
TIMER OUT
110
Function
A high level input to this pin resets the chip, places all three I/O ports in the input mode,
resets all output latches and stops timer.
Negative going edge of the ALE (Address Latch Enable) input latches ADo-7, 10/M, and
CE signals into the respective latches.
Three·state, bi-directional address/data bus. Eight-bit address, information on this bus is read
into the internal address latch at the negative going edge of the ALE. Eight bits of data can
be read from or written to the chip using this bus depending on the state of the WR ITE or
READ input.
When the CE input is high, both read and write operations to the chip are disabled.
A high level input to this pin selects the internal I/O functions, and a low level selects the
memory.
If this pin is low, data from eit~r the memory or ports is read onto the ADO-7 lines depending on the state of the 10/M line.
If this pin is low, data on lines ADo-7 is written into either the memory or into the sele-t:ted
port depending on the state of the 10/M line.
General-purpose I/O pins. Input/output directions ca~ be determined by programming the
command/status (C/S) register.
Three
ports.
PCO:
PC1:
PC2:
PC3:
PC4:
PC5:
pins are usable either as general-purpose I/O pins or control pins for the PA and PB
When used as control pins, they are assigned to the following functions:
A INTR (port A interrupt)
A BF (port A full)
A STB (port A strobe)
B INTR (port B interrupt)
B BF (port B buffer full)
B STB (port B strobe)
Input to the counter/timer
Timer output. When the present count is reached during timer operation, this pin provides
a square-wave or pulse output depending on the programmed control status.
VCC
3-6V power supply
GND
GND
- - - - - - - - - - - - - - - - - - - . I/O· MSM81C55RS/GS •
OPERATION
Description
MSM81 C55RS/GS has 3 functions as described
below .
• 2K bit static RAM (256 words x 8 bits)
• Two 8-bit I/O ports (PA and PB) and a 6-bit I/O port
(PC)
• 14-bit timer counter
The internal register is shown in the figure below,
and the I/O addresses are described in the table below.
I/O Address
Selecting Register
A7
A6
A5
A4
x
x
x
x
x
x
x
x
A3
A2
A1
AO
x
x
x
x
0
0
0
Internal command/status register
0
0
1
Universal I/O port A (PA)
x
x
x
0
1
0
Universal I/O port B (PB)
x
x
x
x
x
0
1
1
I/O port C (PC)
~
x
x
x
x
1
0
0
Timer count lower position 8 bits (LSB)
x
x
x
x
x
1
0
1
Timer count upper position 6 bits and timer mode 2 bits
(MSB)
x: Don't care.
111
• I/O· MSM81C55RS/GS • - - - - - - - - - - - - - - - - - - (1) Programming the Command/Status (C/S) Register
an I/O address of xxxxxOOO. Bit assignments for
the register are shown below:
The contents of the command register can be
written during an I/O cycle by addressing it with
7
6
5
o
2
3
4
Definition of PAo-7
<------ Definition of PBO-7
' - - - - - - - - - - Definition of PCo-s
} °=
= input
1
{
output
OO=ALT1
11 = ALT2
01 = ALT3
10=ALT4
see
the port]
control
assignment
[table.
Port A interrupt enable} 1 = enabled
' - - - - - - - - - - - - - - - - - Port B interrupt enable
0= disabled
00 = NOP: Does not affect counter operations.
01 = STOP: Stops the timer if it is running.
NOP if the timer is not running.
'-------~Timer.
command
----~
10 = STOP AFTER TC: Stops the timer when it
reaches TC.
NOP if the timer is not
running.
11 = START: If the timer is not running, loads the
mode and the count length, and
immediately starts timer operation.
If the timer is running, loads a new
mode and the count length, and starts
timer operation immediately after TC
is reached.
Port Control Assignment Table
112
Pin
ALT1
ALT2
ALT3
ALT4
PCo
Input port
Output port
AINTR
AINTR
PC l
Input port
Output port
A BF
A BF
PC2
Input port
Output port
ASTB
ASTB
PCa
Input port
Output port
Output port
BINTR
PC4
Input port
Output port
Output port
B BF
PCs
Input port
Output port
Output port
BSTB
- - - - - - - - - - - - - - - - - - - -I/O • MSM81C55RS/GS (2)
Reading the CIS Register
The I/O and timer status can be accessed by
reading the contents of the Status register located
at I/O address xxxxxOOO. The status word format
is shown below:
Port A interrupt request
Port A buffer full
Port A interrupt enable
Port B interrupt request
Port B buffer full
Port B interrupt enable
Timer interrupt. This bit is set high when the timer
reaches TC, and is reset when the CIS register is read
or a hardware reset occurs.
(3)
PA and PB Registers
These registers may be used as either input or out·
put ports depending on the programmed contents
of the CIS register. They may also be used either
in the basic mode or in the strobe mode.
I/O address of the PA register: xxxxxOOl
I/O address of the PB register: xxxxxOl0
(4) PC Register
The PC register may be used as an input port, output port or control register depending on the
programmed contents of the CIS register. The I/O
address of the PC register is xxxxxOll.
(5) Timer
The timer is a 14-bit down counter which counts
TIMER I N pulses.
The low order byte of the timer register has an I/O
address of xxxxxl00, and the high order byte of
the register has an I/O address of xxxxxl0l.
The count length register (ClR) may be preset
with two bytes of data. Bits 0 through 13 are
assigned to the count length and bits 14 and
15 specify the timer output mode. A read operation of the ClR reads the contents of the counter
and the pertinent output mode. The initial value
• range which can initially be loaded into the counter is 2 through 3FFF hex. Bit assignments to the
timer counter and possible output modes are
shown in the following.
Mlilj1
Output mode
T13
T12
Tn
I T10 I T9
Ts
High order 6 bits of count length
TS
low order byte of count length
TO
o
o
Note 1:
Note 2:
Outputs a low-level signal in the latter
half (Note 1) of a count period.
Outputs a low-level signal in the latter
half of a count period, automatically
loads the programmed count length,
and restarts counting when the TC value
is reached.
Outputs a pulse when the TC value is
reached.
Outputs a pulse each time the preset TC
value is reached, automatically loads the
programmed count length, and restarts
from the beginning.
When counting an asymmetrical value
such as (9), a high level is output during
the first period of five, and a low level is
output during the second period of four.
If an internal counter of the MSM81 C55RS/GS receives a reset signal, count
operation stops but the counter is not
set to a specific initial value or output
mode. When restarting count operation
after reset, the START command must
be executed again through the CIS
register.
Note that while the counter is counting, you may
load a new count and mode into the ClR. Before
the new count and mode will be used by the
counter, you must issue a START command to the
counter.
Please note the timer circuit on the 81 C55 is
designed to be a square-wave timer, not a event
counter. To achieve this, it counts down by twos
twis in completing one cycle. Thus, its registers do
not contain values directly representing the number of TIMER IN pulse received. After the timer
has started counting down, the values residing in
the count registers can be used to calculate the
actual number of TIMER IN pulse required to
complete the timer cycle if desired. To obtain the
remaining count, perform the following operations
in order:
113
• I/O· MSM81C55RS/GS • - - - - - - - - - - - - - - - - - Note:
1. STOP the counter
If you started with an odd count and
you read the count registers before the
third count pulse occurs, you will not be
able to recognize whether one or two
counts has occurred. Regardless of this,
the 81C55 always counts out the right
number of pulses in generating the
TIMER OUT waveforms.
2. Read in the 16 bit value from the
count registers.
3. Reset the upper two mode bits
4. Reset the carry and rotate right one
position all 16 bits through carry
5. If carry is set, add Y2 of the full original count (Y2 full count-1 if full count
is odd).
TIMER IN
11
n=5
I
START
5
I
5
2-
4
3
I
5
5
(TC) ...
1- - - 1 - - - " -
I
TIMER OUT (SQUARE WAVE)
I
I
------------~--4-------~--f
n=4
I~--~--~
L......-I
I
I
TIMER OUT (PULSE)
:
START
5
3
TIMER OUT (SQUARE WAVE)
I
2
I 5
(TC) ...
1
4
__--..1----.11
I
I
_-+-__
3
4
1
I
I
I
----------~~--~~IL-......JI~--~~~L
TIMER OUT (PULSE)
Note: n is the value set in the CLR.
Figures in the diagram refer to counter value.
(6)
114
Standby Mode (see page 7)
The MSM81 C55RS/GS is placed in standby mode
when the high level at CE input is latched during
the negative going edge of A LE. All input ports
and the timer input should be pulled up or down
to either VCC or GND potential.
When using battery back-up, all ports should be
set low or in input port mode. The timer output
should be set low. Otherwise, a buffer should be
added to the timer output and the battery should
be connected to the power supply pins of the
buffer.
By setting the reset input to a high level, the standby mode can be selected. In this case, the command register is reset, so the ports automatically
set to the input mode and the timer stops.
OKI
semiconductor
MSM83C55-XXRS/GS
2048 x 8 BIT MASK ROM WITH I/O PORTS
GENERAL DESCRIPTION
MSM83C55 is a combination of MROM and I/O devices used in ,a microcomputer system. Owing to the adoption of the
CMOS silicon gate technology, it operates on a low power supply as small as 100 #J.A (max.) in the standby current in
the chip non-select status. As the ROM is composed of 2048 words x 8 bits and its access time (max.) is 400 ns, it can
be applied without using the wait state in the 80C85A system, too. The I/O circuit is composed of 2 universal I/O
ports. Each of these I/O ports has 8 port lines and each of these port lines can be programmed as input or output line
independently.
FEATURES
• High speed and low power consumption owing to
adoption of silicon gate CMOS
• Composed of 2048 words x 8 bits
• 3 - 6 V single power supply
• Address latch circuit incorporated
• Provided with 2 universal 8-bit I/O ports
• TTL Compatible
• Indivisual I/O port line programmable as input or
output
• Time division address/data bus
• 40-pin DIP (MSM83C55-xxRS)
• 44-pin flat package (MSM83C55-xxGS)
• Direct interface with MSM80C85A (3M Hz)
CIRCUIT CONFIGURATION
ClK
READY
AS-tO
CE2
2K x 8
10/M
ROM
ALE
FIT)
lOW
RESET
D
PORTA
ADO-7
[J
PAO- 7
PBO-7
lOR
CE1
Vce
GND
115
• I/O· MSM83C55-XXRS/GS • - - - - - - - - - - - - - - - - PIN CONFIGURATION
MSM83C55-xxRS (Top View)
40 Lead Plastic DIP
III
CEI
VCC
CE2
PB7
ClK
P96
RESET
PBs
N.C
PB4
READY
PB3
101M
lOR
PB 2
1
RD
lOW
ALE
ADo
PAs
ADI
PA4
AD2
PA3
PA2
PAl
PAo
AD6
AD71
AIO
Ag
GND
As
MSM83C55-xxGS (Top View)
44 Lead Plastic Flat Package
44 43 42 41 40 39 38 37 36 35 34
N.C
1
PB4
PBs
PB6
2
3
4
PB7
5
VCC
6
7
28
8
26
25
CEI
CE2
ClK
RESET
READY
116
9
10
PAl
N.C
0
31
PAo
30
29
A~
27
24
11
23
1213141516171819202122
Alo
As
GND
AD7
AD6
ADs
N.C
- - - - - - - - - - - - - - - - - . I/O· MSM83C55·XXRS/GS •
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Limits
Conditions
MSM83C55RS
Supply Voltage
VCC
I
Unit
MSM83C55GS
-0.5 to +7
V
-0.5 to VCC +0.5
V
Input Voltage
VIN
Output Voltage
VOUT
-0.5 to VCC +0.5
V
Storage Temperature
Tstg
-55 to +150
°c
Power Dissipation
PD
With respect to G N D
Ta=25°C
1.0
J
0.7
W
OPERATING RANGE
Parameter
Symbol
Limits
Supply Voltage
VCC
3 to6
V
Operating Temperature
TOp
-40 to +85
°c
Unit
RECOMMENDED OPERATING RANGE
Symbol
Min.
Typ.
Max.
Supply Voltage
VCC
4.5
5
5.5
V
Operating Temperature
TOp
-40
+25
+85
°c
"L" Input Voltage
VIL
-0.3
+0.8
V
"H" Input Voltage
VIH
2.2
VCC +0.3
V
Parameter
Unit
DC CHARACTERISTICS
Parameter
"L" Output Voltage
Symbol
VOL
Conditions
Min.
Typ.
Max.
0.45
IOL=2mA
V
V
2.4
IOH=-400Io'A
Unit
"H" Output Voltage
VOH
Input Leak Current
III
O~ VIN ~VCC
V CC=4.5V to 5.5V
-10
10
Io'A
Output Leak Current
ILO
O~ VOUT~ VCC
Ta=-40°C to +85°C
-10
10
Io'A
100
Io'A
5
mA
V
4.2
CEl ~ VCC-O.2V
Supply Current
(standby)
IOW-40 Io'A
ICCS
CE2~0.2V
0.1
VIH ~ VCC-O·2V
VIL ~0.2V
10 write
Average Supply
Current (active)
ICC
cycle time:
11£S
117
• I/O· MSM83C55-XXRS/GS • - - - - - - - - - - - - - - - - - AC CHARACTERISTICS
(VCC=4.5V to 5.5V. Ta=40°C to +S5°C)
Parameter
I
(I
Symbol
Min.
Clock Cycle Time
tCYC
320
Clock Pulse Width
T.
SO
ns
Clock Pulse Width
T2
120
ns
Unit
ns
Clock Rise and Fall Time
tf. tr
Address to latch Setup Time
tAL
Address Hold Time after latch
tlA
30
ns
Latch to READ/WRITE Control
tlC
100
ns
Valid Data Out Delay from READ Control
tRD
170
ns
Address Stable to Data Out Valid
tAD
400
ns
I
Latch Enable Width
tLL
Data Bus Float after READ
30
ns
ns
50
ns
100
100
ns
tRDF
0
READ/WRITE Control to Latch Enable
tCl
20
READ/WRITE Control Width
tcc
250
ns
Data In to WRITE Setup Time
tow
150
ns
10
Data In Hold Time after WRITE
two
WRITE to Port Output
twp
Port Input Setup Time
tpR
50
Port Input Hold Time
tRP
READY Hold Time
tpYH
0
Address to READY
tARY
Data Out Delay from READ Control
ALE to Data Out Valid
tRV
tRDE
tlD
Note: Timing is measured at VL = O.S V and VH = 2.2 V for both input and output
load condition: Cl = 150 pF
~--------tCYC--------~
Fig. 1 Clock Signal for MSM83C55
ns
ns
400
50
Recovery Time between Controls
.118
Max.
ns
ns
ns
160
ns
160
ns
ns
300
ns
10
350
ns
- - - - - - - - - - - - - - - - - - . I/O· MSM83C55-XXRS/GS •
ADDRESS
DATA
- - - ( ADDRESS
>-
ALE
lOR RD
lOW
~------tcc------~
Fig. 2 Timing for ROM Reading and for 1/0 Reading and Writing
A. Input mode
RD OR lOR
Port input
*Data bus
_______
--------v:
-A________
B. Output mode
*Data bus
======><_____,.,X'-___
*See Figure 2 for the timing of data bus.
Fig. 3 1/0 Port Timing
Fig.4 Wait State Timing (READY = 0)
119
• I/O' MSM83C55-XXRS/GS • - - - - - - - - - - - - - - - - - PIN DESCRIPTION
Function
Pin symbol
RESET
When this signal becomes high level, ports A and B becomes the input mode.
ALE
This pin is used to fetch the AD 0-7, A 8-10, 10/M, CE1, and CE2 signals to their
respective latch circuits at the fall of the ALE (Address Latch Enable) signal.
CE1, CE2
When CE1 fetched to the latch circuit is high level orCE2 is low level, no read nor
write operation is performed. The AD 0-7 and READY output signals are made into
the floating status.
ADO-7
Three-stake bidirectional address/data bus. This bus fetch 8-bit address information to
the latch circuit upon the fall of the ALE signal. When CE1 in holding is low level and
yet CE2 is high level, data is output from chip to bus if RD or lOR is low level and it is
fetched from bus to chip if lOW is low level.
A8-10
These are high order bits of ROM address and have no relation to I/O operation.
101M
When RD is low level, this pin selects I/O port if the 10/M in holding is high level or
ROM if it is low level.
RD
If the R D is low level, the memory data is output to AD 0-7 when the ROM cycle is
selected, but the selected port data is output to the same when the I/O cycle is selected.
lOR
The port data selected at low level is output to AD 0-7. When turned to the low level,
the lOR becomes the same function as that when lo/iiii is turned to the high level and
RD to the low level. When both RD and lOR become high level, the output of AD 0-7
is made into the floating state.
lOW
At the low level, the AD 0-7 data is written to the selected port.
CLK
This signal is used to generate the READY signal for the generation of 1 wait cycle
built in 83C55.
READY
This signal becomes low level when the ALE is high level and the CE1 and CE2 are active.
It becomes high level at the rise of CLK after the fall of the ALE.
PAO-7
These are universal I/O pins and the input/output is determined by the content of the data
direction register. When writing data to port A, make the chip enable active and turn the
lOW to low level after selecting AD 0,1 to 0, O. When reading it, turn the lOR to low
level instead of lOW and 101M to high level.
120
F'BO-7
Same as the operation of PAO-7, excepting that ADO is selected to 1 and AD1 to O.
VCC
+5 V power supply
GND
OV
- - - - - - - - - - - - - - - - - - . I/O· MSM83C55-XXRS/GS •
OPERATIONAL DESCRIPTION
ROM Block
The ROM block in the chip is specified in address
by the chip enable and 11-bit address. Upon the fall of
the ALE signal, the address and chip enable are fetched
in the address latch circuit. When the chip enable is
active and 10iM is low level, 8-bit content of ROM at
the address held in the address latch circuit is transmitted to the bus through the output buffer of AD 0-7 upon
the fall of the RD.
I/O Block
The I/O block in the chip is specified in address by
the value of 2-bits of AD 0-1 a·nd chip enable. Two
8·bit data direction registers (DDR) built in MSM83C55
are used to turn corresponding individual port pins to
the input mode or output mode. It becomes the input
mode when set to 0 and the output mode when set to 1.
It is impossible to read the DDR from outside, however.
DO
0
OUTPUT
lATCH
ADl
ADo
0
0
Selection
Port A
0
1
Port B
1
0
Port A data direction register (DDRA)
1
1
Port B data direction register (DDRB)
Upon the fall of lOW when the chip enable is
active, the AD 0-7 data is written to the I/O port to be
determined by the value of AD 0-1 in holding. During
this operation, selected side I/O bits are all subject to its
influence irrespective of the I/O status and 10/M status.
The output level remains unchanged until the lOW
returns to high level. The data can be read from ports
when the chip enable in holding is active and 10/M is
high level and yet the RD or lOR signal falls. In both
input and outpUt, the data on the selected side exists on
the line of AD 0-7. The function of I/O ports and DDR
(data direction register) is shown in the block diagram
below:
Q
ClK
II)
::>
[JJ
«
«0
WRITE PA
I.J
OUTPUT
ENABLE
DDR
lATCH
«z
a:
w
Q
I-
~
RESET
WRITE DDRA
Do
READ PA
Writing "0" to the DDR is equivalent to the RESET
operation when the port output is made into the High
impedance status and the input mode is specified. Note
that the data can be written to the ports· even if the
output pin was already in the high impedance status
(input mode) by the DDR. Likewise, it is also possible
to read the data once set to those ports.
121
OKI
semiconductor
MSM82C12RS/GS
8-BIT INPUT/OUTPUT PORT
GENERAL DESCRIPTION
IJ
,
MSM82C12 is an 8 bit input/output port employing 3 J.L silicon gate CMOS technology. It insures low operating
power. This device incorporates service request flip-flop for generation and control of interrupts for CPU, in addition
to a 8-bit latch circuit having a three-state output buffer.
It is effective when used as an address latch device to separate the time division bus line outputs in systems
employing MSM80C85A CPU or similar processors using multiplexed address/data bus line.
FEATURES
• Operated on a low power consumption due to silicon
gate CMOS.
• 3 V - 6 V single power supply
• Full static operation
• Parallel 8-bit data register and buffer
• Provided with interrupt generating function by the
adoption of the service request flip-flop
• Equipped with a clear terminal which operates asynchronously
• TTL compatible
• 24-pin DIP (MSM82C12RS)
• 24-pin flat package (MSM82C1 2GS)
• Functionally compatible with 821 2
CIRCUIT CONFIGURATION
.,r-----,-
Service Request Flip-flop
OSl
DS2
MD
STB
01,
01 2
01 3
01 4
Dis
01 6
01 7
Dig
CLR
122
Data Latch
Output Buffer
- - - - - - - - - - - - - - - - - - - - - - . I/O· MSM82C12RS/GS •
PIN CONFIGURATION
MSM82C12RS (Top View) 24 Lead Plastic DIP
MSM82C12GS (Top View) 24 Lead Plastic Flat Package
DS1
Vec
OS1
MD
INT
MD
INT
011
Dis
Dis
001
DOs
011
001
01 2
01 2
01 7
002
01 3
DOs
s::en
s::
00
I\J
~
01 7
007
01 6
00 6
002
00 7
01 3
01 6
003
01 4
003
00 6
004
DOs
STB
CLR
01 4
Dis
GNO
OS2
00 4
DOs
I\J
G)
en
Dis
STB
GNO
PIN DESCRIPTION
Pin Name
Item
Input/Output
Function
Oil-Dis
Data input
Input
These pins are 8-bit data inputs. The data input is connected to
input 0 pins of the 8-bit data latch circuit built in the device.
DOl-DOs
Data output
Output
These pins are 8-bit data outputs. Each bit is composed of 3state output buffers.
These buffers can be made into enable or disable (high impedance status).
MO
Mode input
Input
This input pin is used for status control of output buffers and
for selection clock input to data latch.
STB
Strobe input
Input
This pin is a clock input of data latch. It is also used to reset
the internal service request flip-flop at the same time.
OS1,OS2
Device select
input
Input
The AND of these two inputs functions to make the status control of output buffers or becomes clock input to data latch. It
also functions to make set/reset of the internal service request
flip-flop.
CLR
Clear input
Input
This pin clears the internal data latch in low level. It also sets
the internal service request flip-flop at this time. The clear is
operated asynchronously to the clock.
INT
Interrupt
output
Output
This pin is output of the internal service request flip-flop, but
is inverted to output it in low level operation.
VCC
+5V power supply
GNO
GNO
123
• I/O· MSM82C12RS/GS • - - - - - - - - - - - - - - - - - - FUNCTIONAL DESCRIPTION
Service Request Flip-flop
Output Buffer Status Control and Data Latch Clock
.Input
fI
The service request flip-flop is used to generate and
control interrupt for CPU when the MSM82C12 is used
as input/output port in a microcomputer system. The
flip-flop is set asynchronously by input CLR. When the
flip-flop is set, the system is in non·interrupt status.
When the input MD is in high level, the output
buffer is enabled and the device select input (D51.D52)
becomes clock input to data latch. When the input
MD is in low level, the status of output buffer is determined by the device select input (D51.DS2) (the output
buffer is enabled when (DS1.DS2) is in high levell.
At this time, the input STB becomes clock input to data
latch.
MD
(DS1 . DS2)
STB
DOl - DOs
0
0
0
High impedance status
I
CLR
(DS1 . D52)
0
0
INT
STB
Q
0
0
1
1
1
0
1
0
1
1
i...-
1
0
1
0
1
0
0
0
1
High impedance status
1
1
0
0
Data latch
1
0
0
1
1
1
0
1
Data latch
1
0
~
0
0
0
1
0
Data latch
0
1
1
Data in
Clear
1
1
0
Data in
1
1
1
Data in
When the clear input becomes low level, the internal data latch is cleared irrespective of clock and it
become low level.
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Limits
Conditions
MSM82C12RS
Supply Voltage
Vee
Input Voltage
VIN
Output Voltage
VOUT
Storage Temperature
Tstg
Power Dissipation
PD
With
respect
toGND
Ta
= 25°C
I
Unit
MSM82C12GS
-0.5 to +7
V
-0.5 to V CC+0.5
V
-0.5 to Vec+0.5
V
-55 to +150
DC
I
0.9
0.7
W
OPERATING RANGE
Parameter
5upply Voltage
Operating Temperature
Unit
Symbol
Limits
VCC
3to 6
V
TOp
-40 to +85
°c
RECOMMENDED OPERATING CONDITION
Parameter
Supply Voltage
Symbol
Min.
Typ.
Max.
5
5.5
Unit
V
+25
+85
°c
VCC
4.5
Operating Temperature
TOp
-40
"L" Input Voltage
VIL
-0.3
+0.8
V
"H" Input Voltage
VIH
2.2
VCC +0.3
V
124
- - - - - - - - - - - - - - - - - - . I/O· MSM82C12RS/GS •
DC CHARACTERISTICS
Parameter
Symbol
"L" Output Voltage
Conditions
VOL
"H" Output Voltage
VOH
IOH = -4mA
Input Leak Current
III
O~VIN~VCC
Typ.
Max.
Unit
V
3.7
ILO
O~VOUT~VCC
Supply Current (Standby)
ICCS
VIH ~ VCC - 0.2V
VIL~0.2V
Average Supply Current
(active)
ICC
f = 1 MHz
Output Leak Current
Min.
0.4
IOL = 4mA
VCC = -4.5V
to 5.5V
Ta = -40°C
to +85°C
V
-10
10
#LA
-10
10
#LA
100
#LA
1
mA
0.1
AC CHARACTERISTICS
(VCC = 4.5 - 5.5V, Ta = -40°C +85°C)
Min.
tpw
30
Data to Output Delay
tpD
20
45
ns
twE
31
60
ns
Parameter
Write Enable to Output Delay
Data Set Up Time
Data Hold Time
Typ.
Max.
Unit
Symbol
Pulse Width
Remarks
ns
tSET
15
ns
tH
30
ns
Clear to Output Delay
tc
19
40
ns
Reset to Output Delay
tR
21
45
ns
Set to Output Delay
ts
25
45
ns
Output Enable Time
tE
52
90
ns
Output Disable Time
to
30
55
ns
Load 30pF
Load 20pF +
1kn
Note: TYP is measured where VCC = 5 V and Ta = 25°C.
Timing is measured where VL = VH = 1.5V in both input and output.
tE and to are measured at VOL + 0.5V or VOH - 0.5V when the two are made into high impedance status.
OUTPUT CHARACTERISTICS (DC Characteristics Reference Value)
(1)
Output "H" voltage (VOH)
output current (lOH)
~
5
~ lo
Ta = -40-+85 C -
::J:
0
>CIl
4
VCC = 5.0V
en
c·
>
~
3
~
2
...
e
VS.
(2)
Output OIL" voltage (VOL) vs.
output current (lOL)
5
~
-I
0
>
4
CIl
en
g
~
3
~...
2
::l
VCC = 5.0V
::l
Ta = -40-+85°C
e
::l
::l
0
0
11
0
0
o
-1
-3
-4
-2
-5
Output current IOH (mA)
o
I
1
234
5
Output current IOL (mA)
Note: The direction of flowing in is taken as positive for output current.
125
• I/O' MSM82C12RS/GS • - - - - - - - - - - - - - - - - - - OUTPUT CHARACTERISTICS
(1 I
(AC Characteristics Reference Value)
tpD vs. load capacitance
60
60
50
50
I
~
on
..s
40
'"i
..J
~
30
0
!-
VCC =4.5V
on
... ,. ~
~
~~
~
20 ~
..,
~'
VCC =4.5V
VCC = 5.0V
~VCC =5.5V
~~-
..:.
':J
L""'::: VCC = 5.0V
40
J:
~
..,~
30
0
!-
(Ta = 25"C)
10
20
~
~
."..
~
~ VCC = 5.5V
(Ta = 25°C)
10
o
200
400
o
600
200
400
600
Load capacitance CL (pFI
Load capacitance CL (pFI
(21 tpD and tWE vs. supply voltage
I.
40
E
40
I
twE ..
I-(DS1 . OS2) .......
I
30
tvJE
f----(STB) ......
I
~"""'" 1'-0.. or-
tPO __ ioo..
- -...
--
on
c
J:
~
~
~-
w
~
0
!-
I""'-
Ta = 25°C
CL= 30pF
10
~
-"":.~.
20
tie
(STB)
10
tpo
-:,tWE(OS1 . DS2)
=
Ta 25°C
CL = 30pF
..LL
II
4
5
Supply voltage VCC (VI
126
30
':J
6
4
5
Supply voltage VCC (V)
6
- - - - - - - - - - - - - - - - - - - . I/O • MSM82C12RS/GS •
TIMING CHART
Data Latch Operation
01
STB
(OS1·0S2)
DO
Gate Buffer Operation
01
DO
Interrupt Operation
(OS1 ·OS2)
STB
127
• I/O· MSM82C12RS/GS • - - - - - - - - - - - - - - - - - Clear Operation
DO
Output Buffer Enable/Disable (High Impedance Status) Operation
(OS1 ·052)
DO
tE
ItPZL)
128
- - - - - - - - - - - - - - - - - - . I/O' MSM82C12RS/GS •
EXAMPLE OF APPLICATION OF MSM82C12
Address Latch of MSMSOC85A
Used to separate the time division data bus (8 low
order bits of the address bus and 8-bit data bus) into
~
ADo
MSM
80C85A
the address bus and data bus by means of the ALE
(Address Latch Enable) signal.
12
13
AOl
14
A02
15
A03
16
A04
17
ADs
18
A06
19
A07
Data
Bus
Vce
-r-
ALE
30
Q14
CLR
~ 011
~ 01
001
00 2
2
7
003
013
9 014 MSM 004
16 0ls82C1200s
18
016
006
20
007
01 7
22
Dis
DOs
STB MO OS1
1
:J1
4
6
8
10
15
17
19
Address Bus
(8 low order
bits)
21
r
'iT
129
OKI.'
semiconductor
MSM82C37A - 5 RS/GS
PROGRAMMABLE DMA CONTROLLER
GENERAL DESCRIPTION
'a
The MSM82C37A-5RS/GS, DMA (Direct Memory Access) controller capable of high-speed data transfer
without a CPU, intervention is used as a peripheral device in microcomputer systems. The device features four
independent programmable DMA channels.
Due to the use of silicon gata CMOS technology, standby current is 100 /.lA (maxJ, and the power consumption
is still as low as 10 MA (maxJ when 5 MHz clock is generated.
I
FEATURES
• DREQ and DACK input/output logic inversion
• DMA address increment/decrement selection
• Memory-to-Memory Transfers
• Channel extension by cascade connection
• DMA transfer termination by EOP input
• 40-pin DIP (MSM82C37A-5RS)
• 44-pin flat package (MSM82C37A-5GS)
• Intel 8237A-5 compatibility
• TTL Compatible
• Maximum operating frequency of 5 MHz (V cc = 5 V)
• High-speed operation at very low power consumption
due to silicon gate CMOS technology
• Wide power supply voltage range of 3 to 6 V
• Wide operating temperature range from _40° to
+85°C
• 4-channels independent DMA control
• DMA request masking and programming
• DMA request priority function
PIN CONNECTIONS
44-pin plastic flat-package (top view)
40-pin plastic DIP (top view)
TOR
A7
TOW
A6
MEMR
A5
MEMW
A4
N.C.
READY
A3
HLDA
A2
I~ I~ I~ 19
u
>u
~ « «
<0
In
HLDA
144 43 42 41 40 39 38 37 36 35 34
33
32
ADSTB
31
A1
READY
0
4
A3
A2
ADSTB
Al
AEN
30
AO
AEN
AO
HRO
29
Vee
HRO
Vee (+5 V)
N.C.
28
NC
CS
27
DBO
CLK
26
DB1
25
DB2
24
DB3
CS
DBO
CLK
DB1
RESET
DB2
DACK2
DB3
RESET
DACK2
DACK3
DB4
DRE03
DACKO
DRE02
DACKl
DREOl
DB5
DREOO
DB6
GND
DB7
Note: N.C. (No Connection)
130
EOP
U
Z
10
DACK3
DB4
M
N
II:
II:
0
0
aUJ aUJ
a
§ 8
II:
II:
0
0
0
z
(!)
u ....
u 0
<0
lJ
Q)
3
Ol
!!l
'0
>
--
tpO. tH. and tACC vs. power supply voltage (Vce)
700
-........
600
en
E
3-
2
r-...
~
'\~
"
500
u
400
$
0
300
~
()
::l
9-
o
::l
0
o
E:-
-1
-2
-3
-4
-5
Output current IOH (mA)
200
--
100
0
3
Output "L" voltage (VOL) vs. output current (IOL)
~
...J
0
>
~,
tAee
tpo
I--- ~tH
5
6
Power supply voltage (Vee)
5
4
Q)
Ol
!!l
'0
>
3
2
~
...
::l
9::l
0
--- -
I-
~
0
o
-1
-2
-3
-4
-5
Output current IOL (mA)
Operating frequency vs. power supply voltage (ICC)
~
S
./
2
()
~
...c:::
~::l
tJ
>
Q.
c.
V"
~
lii
/
/
Vee = 4.5V
~
5.5 V
;'
~
0
Q"
0
3
6
11
MSM80e49 operating frequency (MHz)
158
Note: The direction which the output current flows
through the device is taken as the positive direction.
- - - - - - - - - - - - - - - - - - - . I/O· MSM82C43RS/GS •
GUARANTEED MSM82C43 OPERATING RANGE
N
:c
-Guaranteed operating range
~
Q)
Cl
C
~
Cl
C
';;
~
Q)
a.
o
en
~
o
~
3
--------
'6
----------
en
~
11
_______________ 30....._ _ _--...1
2
3
4
5
6
Power supply voltage (Vee)
159
OKI
semiconductor
MSM82C51 ARS/GS
UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER
GENERAL DESCRIPTION
(I
I
MSM82C51 A is USART(Universal Synchronous Asynchronous Receiver Transmitter) for serial data communication developed for the microcomputer system.
As a peripheral device of the microcomputer system, MSM82C51 A receives parallel data from CPU and transmits serial data after conversion. This device also receives serial data from outside and transmits parallel data to CPU
after conversion. Thus the device is used for serial data communication.
MSM82C51 A configures a fully static circuit u~ing silicon gate CMOS technology. Therefore, it operates on an
extremely low power supply at 100 /.LA (max) of standby current by suspending all the operations.
FEATURES
• Wide power supply voltage range from 3 V to 6 V.
0
• Wide temperature range from _40 C to 85° C.
• Synchronous communication upto 64K baud.
• Asynchronous communlcation upto 38.4K baud.
• Transmitting/receiving operations under double buffered configuration.
• Error detection (parity, overrun and framing)
• 28-pin DIP (MSM82C51 ARS)
• 32-pin flat package (MSM82C51 AGS)
FUNCTIONAL BLOCK DIAGRAM
TRANSMIT
BUFFER
TxD
(P-S)
RESET
ClK
C/O
AD
TxRDY
TRANSMIT
CONTROL
TxE
TxC
WR
CS
RECEIVE
BUFFER
RxD
(S-PI
RxRDY
~J~i~~El
160
Axe
- - - - - - - - - - - - - - - - - - . I/O· MSM82C51ARS/GS •
PIN CONFIGURATION
o
MSM82C51 ARS (Top View)
28 Lead Plastic DIP
FUNCTION
MSM82C51 AGS (Top View)
32 Lead Plastic Flat Package
by setting a necessary command, reading a status and
reading/writing data.
Outline
MSM82C51 A's functional configuration is programed by the software.
Operation between MSM82C51 A and CPU is
executed by program control. Table 1 shows the operation between CPU and the device.
Internal reset
yes
Table 1 Operation between MSM82C51 A and CPU
CS
C/O
RD
WR
1
X
X
X
0
X
1
1
Data bus 3-state
0
1
0
1
Status -+ CPU
Data bus 3-state
0
1
1
0
Control word +- CPU
0
0
0
1
Data-+CPU
0
0
1
0
Data +-CPU
It is necessary to execute a function-setting sequence after resetting on MSM82C51 A. Fig. 1 shows
the function-setting sequence.
If the function was set, the device is ready to
receive a command, thus enabling the transfer of data
yes
Fig_ 1 Function-Setting Sequence
(Mode Instruction Sequence)
161
• I/O· MSM82C51ARS/GS • - - - - - - - - - - - - - - - - - Control Words
•
•
•
•
•
Stop bit length (asynchronous mode)
Character length
Parity bit
Baud rate factor (asynchronous mode)
Internal/external synchronization (synchronous
mode)
• No. of synchronous characters (synchronous
mode)
The bit configuration of mode instruction
is shown in Fig.'s 2 and 3. In the case of synchronous mode, it is necessary to write one- or twobyte sync characters.
If sync characters were written, a function
will be set because the writing of sync characters
constitutes part of mode instruction .
There are two types of control word.
1. Mode instruction (setting of function)
2. Command (setting of operation)
1)
Mode Instruction
Mode instruction is used for setting the
function of MSM82C51 A. Mode instruction will
be in "wait for write" at either internal reset
or external reset. That is, the writing of control
word after resetting will be recognized as "mode
instruction. "
Items to be set by mode instruction are as
follows:
• Synchronous/asynchronous mode
Os
l
S2
I
SI
I
Do
EP
I PEN I
L2
I
Ll
I
B2
I
Bl
Baud rate factor
L.-
a
a
Refer to
Fig. 3
SYNC
1
a
1
a
1
1
1x
16x
64x
Character length
a
a
1
a
1
a
1
1
5 bits
6 bits
7 bits
8 bits
Parity check
a
a
Disable
1
a
1
a
1
1
Odd
parity
Disable
Even
parity
Stop bit length
Fig. 2
162
a
a
1
a
1
a
1
1
Inhibit
1 bit
Bit Configuration of Mode Instruction (Asynchrnous)
1.5 bits
2 bits
- - - - - - - - - - - - - - - - - - . I/O' MSM82C51ARS/GS •
I scs I
Do
DS
D7
ESD
I
EP
I
PENI
L2
I
Ll
I
0
0
I 1
Character length
~
0
1
0
1
0
0
1
1
5 bits
6 bits
7 bits
8 bits
0
1
0
1
0
0
1
1
Disable
Odd
parity
Disable
Even
parity
Parity
Synchronous Mode
~
0
1
Internal External
synchro- synchronization nization
No. of synchronous sharacters
Fig. 3
2)
0
1
2 characters
1 character
Bit Configuration of Mode Instruction (Synchronous)
Command
Command is used for setting the operation
of MSM82C51 A.
It is possible to write a command whenever
necessary after writing mode instruction and sync
characters.
Items to be set by command are as follows:
• Transmit
Enable/Disable
• Receive
Enable/Disable
Output of data.
DTR, RTS
Resetting of error flag.
Sending of break characters
Internal resetting
Hunt mode (synchronous mode)
The bit configuration of a command is shown
in Fig. 4.
•
•
•
•
•
163
• I/O' MSM82C51ARS/GS • - - - - - - - - - - - - - - - - - -
D7
I
EH
DO
Ds
J
IR
j RTS j
ER
j SBRK
J
RXEl DTRj TxEN
1 ...• Transmit Enable
'"- O.... Disable
m
I
DTR
1 -+DTR = 0
O-+DTR = 1
1 .... Receive Enable
O.... Disable
1 ...• Send break
character.
O•... Normal operation
1 •... Reset error
flag.
O.... Normal operation
RTS
1 -+RTS = 0
O-+RTS = 1
1 .•.. lnternal reset
O.... Normal operation
1 •..• Hunt mode
(Note)
O.... Nomal operation
(Note)
Fig. 4
164
Search mode for synchronous
characters in synchronous mode.
Bit Configuration of Command
- - - - - - - - - - - - - - - - - - . I/O' MSM82C51ARS/GS •
StatuI Word
It is possible to see the internal status of MSM82C51 A by reading a status word.
0,
Ir OSR
The bit configuration of status word is shown in
Fig. 5.
Os
!SYNDETI
ISO I
FE
I I
OE
PE
I Tx I Rx
IEMPTY! ROY
I
DO
Tx
ROY
Partly different from
TXROY terminal.
'-- Refer to "Explanation of TXROY
Terminal.
Same as terminal.
Refer to "Explanation of Terminals.
1 .... Parity error
1 .... Overrun error
1 .... Framing error
(Note) only asynchrnous mode.
Stop bit cannot
be detected.
Shows terminal OSR.
1 .... 0SR = 0
O.... OSR = 1
Fig. 5
Bit Configuration of Status Word
165.
• I/O· MSM82C51ARS/GS • - - - - - - - - - - - - - - - - - -
I
fJ
I
Standby Status
It is possible to put MSM82C51 A in "standby
status" for the complete static configuration of CMOS.
Jt is when the following conditions have been
satisfied that MSM82C51 A is in "standby status."
(1) CS terminal shall be fixed at Vcc level.
(2) Input pins other than CS, Do to 0 7 , RD, WR
and C/O shall be fixed at Vcc or GND level
(including SYNDET in external synchronous
model.
Note When all outputs current are 0, ICCS
specification is applied.
Explanation of Each Terminal
Do to 07 (I/O terminal)
This is a bidirectional data bus which receive control word and transmit data from CPU and send status
word and received data to CPU.
RESET (Input terminal)
A "High" on this input forces the MSM82C51 A
into "reset status."
The device waits for the writing of "mode instruction."
The min. reset width is six clock inputs during
the operating status of C lK.
ClK (Input terminal)
ClK signal is used to generate an internal device
timing.
ClK signal is independent of RXC or TXC.
However, the frequency of ClK must be greater
than 30 times the RXC and TXC at Synchronous mode
and Asynchronous "x1" mode, and must be greater
than 5 times at Asynchronous "x16" and "x64" mode.
WR (Input terminal)
This is "active low" input terminal which receives
a signal for writing transmit data and control words
from CPU into MSM82C51 A.
RD (Input terminal)
This is "active low" input terminal which receives
a signal for reading receive data and status words from
MSM82C51A.
C/O (Input terminal)
This is an input terminal which receives a signal for
selecting data or command word and status word when
MSM82C51 A is accessed by CPU.
If C/O = low, data will be accessed.
If C/O = high, command word or status word will
be accessed.
CS (Input terminal)
This is "active low" input terminal which selects
the MSM82C51 A at low level when CPU accesses.
Note The device won't be in "standby status"
only setting CS = High.
Refer to "Explanation of Standby Status."
166
TXD (Output terminal)
This is an output terminal for transmit data from
which serial-converted data is sent out.
The device is in "mark status" (high level) after
resetting or during a status when transmit is disable.
It is also possible to set the device in "break
status" (low levell by a command.
TXRDY (Output terminal)
This is an output terminal which indicate that
MSM82C51 A is ready to accept a transmit data character. But the terminal is always at low level if CTS = high
or the device was set in "TX disable status" by a command.
Note TXRDY of status word indicates that
transmit data character is receivable, regardless of CTS or command.
If CPU write a data character, TXRDY will be reset
by the leadingedge or WR signal.
TXEMPTY (Output terminal)
This is an output terminal which indicates that
MSM82C51 A transmitted all the characters and had no
data character.
In "synchronous mode," the terminal is at high
level, if transmit data characters are no longer left and
sync characters are automatically transmitted.
If CPU write a data character, TXEMPTY will be
reset by the leadingedge of WR signal.
Note As transmitter is disabled by setting CTS
"High" or command, a data written before
disabled will be sent out, then TXD and
TXEMPTY will be "High".
Even if a data is written after disabled, that
data is not sent out and TXE will be "High".
After enabled transmitter, it sent out.
(Refer to Timing Chart of Transmitter Control and Flag Timing)
TXC (Input terminal)
This is a clock input signal which determines the
transfer speed of transmit data.
In "synchronous mode," the baud rate will be the
same as the frequency of TXC.
In "Asynchronous mode", it is possible to select
baud rate factor by mode instruction.
It can be 1,1/16 or 1/64 the TXC.
The falling edge of TXC sifts the serial data out of
the MSM82C51 A.
RXD (Input terminal)
This is.a terminal which receives serial data.
RXRDY (Output terminal)
This is a terminal which indicates that MSM82C51 A contains a character that is ready to READ.
If CPU read a data character, RXRDY will be reset
by the leadingedge of RD signal.
Unless CPU reads a data character before next one
character is received completely, the preceding data will
be lost. In such a case, an overrun error flag of status
word will be set.
- - - - - - - - - - - - - - - - - - . I/O· MSM82C51ARS/GS •
RXC (Input terminal)
This is a clock input signal which determines the
transfer speed of receive data.
In "synchronous mode," the baud rate will be the
same as the frequency of RXC.
In "asynchronous mode," it is possible to select
baud rate factor by mode instruction.
It can be 1, 1/16, 1/64 the RXC.
SYNDET/BD (Input or output terminal)
This is a terminal which function changes according to mode.
In "internal synchronous mode," this terminal is
at high level, if sync characters are received and synchronized. If status word is read, the terminal will be
reset.
In "external synchronous mode," this is an input
terminal.
If "High" on this input forces, MSM82C51 A starts
receivi ng data character.
In "asynchronous mode," this is an output terminal which generates "high level" output upon the detec·
tion of "break" character, if receiver data contained
"low-level" space between stop bits of two continuous
characters. The terminal will be reset, if RXD is at
high level.
DSR (Input terminal)
This is an input port for MODEM interface. The
input status of the terminal can be recognized by CPU
reading status words.
DTR (Output terminal)
This is an output port for ~ODEM interface. It
is possible to set the status of DTR' by a command.
CTS (Input terminal)
This is an input terminal for MODEM interface
which is used for. controlling a transmit circuit. The
terminal controls data transmit if the device is set in
"TX Enable" status by a command. Data is transmitable if the terminal is at low level.
RTS (Output terminal)
This is an output port for MODEM interface. It
is possible to set the status of RTS by a command.
167
• I/O· MSM82C51ARS/GS • - - - - - - - - - - - - - - - - - ABSOLUTE MAXIMUM RATINGS
Parameter
Limits
Symbol
MSM82C51 ARS
Unit
JMSM82C51 AGS
Power supply voltage
VCC
-0.5 - +7
V
Input voltage
VIN
-0.5 - VCC'+ 0.5
V
VOUT
-0.5 - VCC + 0.5
V
-55 - 150
°c
Output voltage
Storage temperature
Power dissipation
Tstg
1
0.9
Po
0.7
Conditions
With respect to G N 0
W
Ta
= 25°C
OPERATING RANGE
Parameter
Symbol
Limits
Power supply voltage
VCC
3-6
V
Operating temperature
TOp
-40 - 85
°c
Unit
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min.
Typ.
Max.
Power supply voltage
VCC
4.5
5
5.5
Unit
V
Operating temperature
TOp
-40
+25
+85
°c
"l" input voltage
VIl
-0.3
+0.8
V
"H" input voltage
VIH
2.2
VCC + 0.3
V
DC CHARACTERISTICS
(Vee = 4.5 - 5.5V Ta = _40°C - +85°C)
Parameter
Symbol
Min.
Typ.
Measurement Conditions
Max.
Unit
0.45
V
lOl
V
lOH
= 2mA
= -400 #LA
"l" output voltage
VOL
"H" output voltage
VOH
3.7
Input leak current
III
-10
10
#LA
Output leak current
IlO
-10
10
#LA
o S:;VOUT S:;VCC
OS:;VIN S:;VCC
Operating supply current
ICCO
5
mA
Asynchronous X64 during
transm itti ng/receivi ng
Standby supply current
ICCS
100
#LA
All input voltage shall be
fixed at VCC or GNO level.
168
- - - - - - - - - - - - - - - - - - • I/O· MSM82C51ARS/GS.
AC CHARACTE R ISTICS
(Vee = 4.5 ~ 5.5V, Ta = -40 ~ 85°C)
CPU Bus Interface Part
Parameter
Address stable before RD
Symbol
Min.
Max.
Unit
NS
Note 2
Note 2
tAR
20
Address hold time for RD
tRA
20
NS
RD pulse width
tRR
250
NS
Data delay from RD
tRD
RD to data float
tDF
Recovery time between RD
tRVR
Address stable before WR
NS
200
10
Remarks
NS
100
Note 5
6
Tcy
tAW
20
NS
Note 2
Address hold time for WR
tWA
20
NS
Note 2
WR pulse width
tww
250
NS
Data set·up time for WR
tDW
150
NS
Data hold time for WR
tWD
20
NS
Recovery time between WR
tRVW
6
Tcy
RESET pulse width
tRESW
6
Tcy
Note 4
Serial Interface Part
Parameter
Symbol
Min.
Main clock period
tcy
250
Clock low time
ti
90
Clock high time
tet>
120
Clock rise/fall time
tR, tF
TXD delay from falling edge of TXC
Transmitter clock frequency
Transmitter clock low time
Transmitter clock high time
Receiver clock frequency
Receiver clock low time
Receiver clock high time
Unit
Remarks
NS
Note 3
NS
tcy-90
NS
20
NS
1
tDTX
}JS
DC
64
kHz
fTX
DC
615
kHz
615
kHz
1X Baud
fTX
16X, Baud
64X, Baud
Max.
fTX
DC
1X Baud
tTPW
13
TCY
16X, 64X Baud
tTPW
2
TC'L
1X Baud
tTPD
15
Tcy
16X, 64X Baud
tTPD
3
1X Baud
fRX
DC
64
kHz
16X Baud
fRX
DC
615
kHz
615
kHz
Tcy
64X Baud
fRX
DC
1 X Baud
tRPW
13
Tcv
16X, 64X Baud
tRPW
2
T.cy
1 X Baud
tRPD
15
TCY
16X, 64X Baud
tRPD
3
Tcy
Time from the center of last bit to the rise
of TXRDY
Time from the leading edge of WR to the fall
of TXRDY
Time from the center of last bit to the rise
of RXRDY
tTXRDY
tTXRDY CLEAR
tRXRDY
Note 3
8
Tcy
400
NS
26
Tcy
Note 3
169
• 1l0'·'MSM82C51ARS/GS. ----------~------Parameter
Symbol
Time from the leading edge of RD to the fall
of RXRDY
tRXRDY CLEAR
Internal SYNDET delay time from rising edge
of RXC
tiS
SYNDETsMuptimefurRXC
I
Max.
Unit
400
NS
26
Tcy
tES
18
Tcy
tTXEMPTY
20
Tcy
MODEM control signal delay time from rising
edge of WR
twc
8
TCY
MODEM control signal setup time for falling
edge of RD
tCR
20
Tcy
RXD setup time for rising edge of RXC
(1 X Baud)
tRXDS
11
Tcy
RXD hold time for falling edge of RXC
(lX Baud)
tRXDH
17
Tcy
TXE delay time from the center of last bit
II
Min.
Caution
Remarks
1 ) AC characteristics are measured at 150 pF capacity load as an output load based orf 0.8 V at low
level and 2.2 Vat high level for output and 1.5 V for input.
2) Addresses are CS and clo.
3) fTX or fRX ::;; 1/(30 Tcy)
1 x baud
fTX or fRX ~ 1/(5 Tcy)
16 x, 64 x Baud
4) This recovery time is mode Initialization only.
Recovery time between command writes for
Asynchronous Mode is 8 tCY and for Synchronous Mode is 18 tCY.
Write Data is allowed only when TXRDY = 1.
5) This recovery time is Status read only.
Read Data is allowed only when RXRDY = 1.
6) Status update can have a maximum delay of 28 clock periods from event affecting the status.
TIMING CHART
System .Clock Input
ClK
Transmitter Clock and Data
TPW'TPD
TxC
U.MODE)
T.C U6.MODE)
T.D = = = * = ' D T X
170
~
-l ~-tDTX
~
• I/O· MSM82C51ARS/GS •
Receiver Clock and Data
IRxBAUD COUNTER STARTS HERE)
RxD
Axe 11 xMODE)
Axe IISxMODE)
INT SAMPLING P U L S E - - - - - - - - - - - '
Write Data Cycle (CPU -+ USART)
TxRDY
DATA IN _ _ _ _ _D_O_N_'_T_C_A_R_E_ _ _ _<1
DON'T CARE
(D. B.l
C/O
Read Data Cycle (CPU +- USART)
RxRDY
tRxR DY CLEAR
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~ ....----tRR---~
~------_
RD
.-tDF
DATA OUT _ _ _ _ _.....;;;D;.;.A.;.;T;.;.A.;..F;..L;;.O;.;A_T
_ _ _ _ __+_~
(D.B.)
C/O
DATA OUT ACTIVE
DATA FLOAT
----------------------~----~----------------+---~--------
171
• I/O· MSM82C51ARS/GS.
Write Control or Output Port Cycle (CPU -+ USART)
.DTR.RTS
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J
WR
DATAIN _________O_O_N_'_T_C_A_R_E______~
(OB)
I
lJ
DON'T CARE
C/o
I
Read Control or Input Port (CPU +- USART)
-.Jx=
OSR.CTS _ _ _ _ _
j:==tCR
______________________________
~~------tRR----~~I~~-------------
RD
tOF
DATA OUT _______.....;D;;,;A.;"T;.,;A..;.;.,F..
L,;;;O.;.;A:.;,T_______-+-...(I
(D. BJ
DATA OUT ACTIVE
1\..._ _ _ _ _ _ _ _ _.11
C/o
Transmitter Control and Flag Timing (ASYNC Mode)
TxEMPTY
tTxEMPTY
TxRDY ------~
(STATUS BIT)
TxRDY
IPIN)----e
c/o
TxD
(Nota)
172
The wave-form chart is based on the case of. 7 bit data length + parity bit + 2 stop bit.
DATA FLOAT
Receiver Control and Flag Timing (ASVNC Mode)
~
BREAK DETECT
FRAMING ERROR
(STATUS BIT)
OVERRUN ERROR
(STATUS BIT)
~
CHAR 2
-ij:';-tRXRDY
~LOST
RxRDY
/r""""
Rd DATA
C/O
·WR
.J
1\
\...
1~
~
P"
I
IT
Wr ERROR
AD
RxDATA
I
I
\
Wr RxEn
~
~
'!r-v
/
~
RxEn
/
CHAR 1
CHAR 2
CHAR 3
I- I- I- I-
BREAK
RxEn Err Res
CiiCiiCiiCii
>-0..1-<1:
1- 0 [(1-1-<1:<1:
[((/)1-0
0
en
COUNTER
#0
COUNTER
#1
f-
;..
...;
..:;
COUNTER
#2
f-
...
..:;
...
7
~
::-
:::>
I-
IXl
..J
«
Z
a:
w
~
7
~
I
...;
;..
..:
::-
DATA
BUS
BUFFER
t ,
II
uo
uz
>(!)
Us
V
o
o
,...I
o
176
I
~
~
(
/S
/
'<:
READ/
WRITE
LOGIC
p-
L
::-
CONTROL
WORD
REGISTER
f-
- - - - - - - - - - - - - - - - - - . I/O· MSM82C53-5RS/GS •
PIN CONFIGURATION
MSM82C53-5RS (TOP VIEW)
24 LEAD PLASTIC DIP
VCC
AD
a
CS
Ao
CLK2
OUT2
MSM82C53-5GS (TOP VIEW)
32 LEAD PLASTIC FLAT PACKAGE
N.C
N.C
VCC
07
WA
Os
RD
N.C
N.C
~o
3
4
5
6
7
DO
CLKO
N.C
8
9
10
11
12
13
14
15
16
AO
CLK2
OUT2
GATE2
N.C
ClK1
OUTO
GATE1
GATEO
OUT1
GND
N.C
CS
(NC denotes "not connected")
N.C
177
-I/O . MSM82C53-5RS/GS - - - - - - - - - - - - - - - - - - ABSOLUTE MAXIMUM RATINGS
Limits
Parameter
Symbol
Conditions
MSM82C53-5 RS
Supply Voltage
Input Voltage
Storage Temperature
II
Power Dissipation
MSM82C53-5GS
-0.5 to +7
Vce
Respect to G N 0
VIN
Output Voltage
Unit
I
VOUT
Tstg
V
-0.5 to VCC + 0.5
V
-0.5 to VCC + 0.5
V
°c
-55 to + 150
Ta = 25°C
Po
I
0.9
W
0.7
I
OPERATING RANGES
Symbol
Limits
Supply Voltage
Parameter
VCC
3 to 6
Operating Temperature
TOp
-40 to +85
Conditions
Unit
VIL = 0.2V, VIH = VCC - 0.2V,
operating frequency 2.6 MHz
V
°c
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Unit
Symbol
Min.
Typ.
Max.
5
5.5
V
+25
+85
°c
VCC
4.5
Operating Temperature
TOp
-40
"L" Input Voltage
VIL
-0.3
+0.8
V
VIH
2.2
VCC + 0.3
V
"H" Input Voltage
DC CHARACTERISTICS
Parameter
"L" Output Voltage
"H" Output Voltage
Symbol
VOL
Conditions
Min.
Typ.
Max.
0.45
IOL=4mA3.7
IOH = -lmA
Unit
V
V
VOH
Input Leak Current
III
O~VIN ~VCC
VCC=4.5V to 5.5V
-10
10
IJ.A
Output Leak Current
ILO
OS VOUT~VCC
Ta=-40°C to +85°C
-10
10
IJ.A
100
IJ.A
5
mA
CS~ VCC -0.2V
Standby Supply Current
ICCS
VIH ~ VCC - 0.2V
VIL~0.2V
Operating Supply Current
178
ICC
tCLK = 200 ns
- - - - - - - - - - - - - - - - - - . I/O· MSM82C53-5RS/GS •
AC CHARACTERISTICS
(Vcc = 4.5V - 5.5V. Ta = -40 - +85°C)
Parameter
Symbol
Min.
Max.
Unit
Address Set-up Time before reading
TAR
30
ns
Address Hold Time after reading
TRA
0
ns
Read Pulse Width
TRR
150
ns
Read Recovery Time
TRVR
200
ns
ns
Address Set-up Time before writing
TAW
0
Address Hold Time after writing
TWA
30
ns
Write Pulse Width
TWW
150
ns
Data Input Set-up Time before writing
TDW
100
ns
Data Input Hold Time after writing
TWD
30
ns
Write Recovery Time
TRVW
200
ns
Clock Cycle Time
TCLK
200
Clock "H" Pulse Width
TPWH
60
ns
Clock "L" Pulse Width
TPWL
60
ns
ns
D.C.
"H" Gate Pulse Width
TGW
50
TGL
50
ns
Gate Input Set-up Time before clock
TGS
50
ns
Gate Input Hold Time after clock
TGH
50
Output Delay Time after reading
TRD
TDF
90
ns
TODG
120
ns
Output Delay Time after clock
TOD
150
ns
Output Delay Time after address
TAD
180
ns
= 2.2V for both
Clock
and
gate
timing
ns
Output Delay Time after gate
Timing measured at VL = 0.8V and VH
Write
cycle
ns
120
Output Floating Delay Time after reading
Note:
CL = 150pF
Read
cycle
ns
"L" Gate Pulse Width
5
Conditions
Delay
time
inputs and outputs.
TIME CHART
Write Timing
AO-l.CS
--t--r--TWA
- - -....-TWD
179
• I/O· MSM82C53-5RS/GS • - - - - - - - - - - - - - - - - - .Read Timing
DO-7--------------------------------------~
HIGH IMPEDANCE
Clock & Gate Timing
~-------TCLK----~
CLK
GATE
OUT
180
HIGH IMPEDANCE
- - - - - - - - - - - - - - - - - - . I/O· MSM82C53-5RS/GS •
DESCRIPTION OF PIN FUNCTIONS
Pin Symbol
Name
Input/output
07 - DO
Bidirectional
data bus
Input/output
CS
Chip select
input
Input
Data transfer with the CPU is enabled when this pin is at low
level. When at high level, the data bus (Do thru 0,) is
switched to high impedance state where neither writing nor
reading can be executed. Internal registers, however, remain
unchanged.
RD
Read input
Input
Data can be transferred from MSM82C53-5 to CPU when
this pin is at low level.
WR
Write input
Input
Data can be transferred from CPU to MSM82C53-5 when
t!lis pin is at low level.
AO,A1
Address input
Input
One of the three internal counters or the control word register is selected by AO/A 1 combination. These two pins are
normally connected to the two lower order bits of the
address bus.
CLKO-2
Clock input
Input
Supply of three clock signals to the three counters incorporated in MSM82C53-5.
GATEO-2
Gate input
Input
Control of starting, interruption, and restarting of counting
in the three respective counters in accordance to the set control word contents.
OUTO-2
Counter output
Output
Output of counter output waveform in accordance with the
set mode and count value.
Function
Three-state 8-bit bidirectional data bus used when writing
control words and count values, and reading count values
upon reception of WR and RD signals from CPU.
SYSTEM INTERFACING
I
l
l
ADDRESS BUS
A1
)
' 16 bits
AO
I
CONTROL BUS
I
DATA BUS
I
I
/
/'~
'8 bits
I
.....V ~bits
')
A1 AO
CS
,..,,7
()
(
07-0
RD
WR
82C53-5
COUNTER #Q
I
I
OUT GATE CLK
COUNTER #1
I
I
OUT GATE CLK
!
,
COUNTER #2
I
I
OUT GATECLK
4
!
181
• I/O' MSM82C53-5RS/GS • - - - - - - - - - - - - - - - - - DESCRIPTION OF BASIC OPERATIONS
Data transfers between the internal registers and the external data bus is outlined in the following table.
Function
CS
RD
WR
A1
AO
0
1
0
0
0
Data bus to counter # 0 Writing
0
1
0
0
1
Data bus to counter # 1 Writing
0
1
0
1
0
Data bus to counter # 2 Writing
0
1
0
1
1
Data bus to control word register Writing
0
0
1
0
0
Data !Jus from counter # 0 Reading
0
0
1
0
1
Data bus from counter # 1 Reading
0
0
1
1
0
Data bus from counter # 2 Reading
0
0
1
1
1
1
x
x
x
x
0
1
1
x
x
x denotes "not
}
Data bus in high impedance status
specified~'.
•
DESCRIPTION OF OPERATION
82C53-5 functions are selected by control word
from CPU. In the required program sequence, the
control word setting is followed by the count value
setting and execution of the desired timer operation.
M2 M1
Control Word and Count Value Program
Each counter operating mode is set by control
word programming. The control word format is outlined below.
07
!
DQ
05
04
03
Set Contents
MO
0
Mode 0 (Interrupt on Terminal Count)
0
1
Mode 1 (Programmable One-Shod
1
0
Mode 2 (Rate Generatod
x
1
1
Mode 3 (Square Wave Generator)
1
0
0
Mode 4 (Software Triggered Strobe)
1
0
1
Mode 5 (Hardware Triggered Strobe)
0
0
0
x
DO
x denotes "not spe.cified".
1
Select
Counter
Read/Load
(CS = 0, AO, A 1 = 1,1,
•
01
Operation waveform mode
s_c_1_I_s_c_0....!.I_R_L_1_I_R_LO---'I,Ic..._M_2_ _
M_1_M_O_tflt]
L-
•
02
Mode (M2, M1, MO):
setting
Mode
BCD
Ri5 =
1, WR = 0)
Select Counter (SCO, SC1): Selection of set counter
SC1
SCO
Set Contents
0
0
Counter # 0 selection
0
1
Counter # 1 selection
1
0
Counter # 2 selection
1
1
Illegal combination
Read/Load (RL 1, RLO):
Loading format setting
Count value Reading/
Set Contents
RLl
RLO
0
0
Counter Latch operation
0
1
Reading/Loading of Least Significant
byte (LSB)
1
0
Reading/Loading of Most Significant
byte (MSB)
1
1
Reading/Loading of LSB followed by
MSB
182
•
BCD: Operation count mode setting
BCD
Set Contents
0
Binary Count (16-bits Binary)
1
BCD Count (4-decades Binary Coded
Decimal)
After setting Read/Load, Mode, and BCD in each
counter as outlined above, next set the desired count
value. (In some Modes, counting is started immediately
after the count value has been written). This count
value setting must conform with the Read/Load format
set in advance. And note that the internal coun~ers are
reset to OOOOH during control word setting. But the
counter value (OOOOH) can't be read.
If the two bytes (LSB and MSB) are written at this
stage (R LO and R L 1 = 1,1), take note of the following
precaution.
Although the count values may be set in the three
counters in any sequence after the control word has
been set in each counter, count values must be set
consecutively in the LSB - MSB order in anyone
counter.
- - - - - - - - - - - - - - - - - - . I/O· MSM82C53-5RS/GS •
•
Example of control word and count value setting
1 byte Read/Load .... When the new count
value is written, counting is stopped
immediately, and then restarted at
the new count value by the next
clock.
2-byte Read/Load ...• When byte 1 (LSB) of
the new count value is written,
counting is stopped immediately.
Counting is restarted at the new
count value when byte 2 (MSB) is
written.
Counter # 0: Read/Load LSB only, Mode 3,
Binary count, count value 3H
Counter # 1: Read/Load MSB only, Mode 5,
[
Binary count, count value AAOOH
Counter # 2: Read/Load LSB and MSB, Mode 0,
BCD count, count value 1234
MVI A, 1EH] Counter #0 control word setting
OUTn3
MVI A, 6AH] Counter
OUTn3
.
MVI A, B1H] Counter
OUTn3
MVI A,03H ]
Counter
OUT nO
MVI A,AAH]
Counter
OUTn1
#1 control word setting
•
Mode 1 (programmable one-shot)
The counter output is switched to "H" level by the
mode setting. Note that in this mode, counting is
not started if only the count value is written. Since
counting has to be started in this mode by using
the leading edge of the gate input as a trigger, the
counter output is switched to "L" level by the next
clock after the gate input trigger. This "L" level
status is maintained during the set count value, and
is switched back to "H" level when the terminal
count is reached.
Once counting has been started, there is no interruption until the terminal count is reached, even if
the gate input is switched to "L" level in the meantime. And although counting continues even if a
new count value is written during the counting,
counting is started at the new count value if another
trigger is applied by the gate input.
•
Mode 2 (rate generator)
The counter output is switched to "H" level by the
mode setting. When the gate input is at "H" level,
counting is started by the next clock after the count
value has been written. And if the gate input is at
"L" level, counting is started by using the rising
edge of the gate input as a trigger after the count
value has been set.
An OIL" level output pulse appears at the counter
output during a single clock duration once every
n clock inputs where n is the set count value. If a
new count value is written during while counting
is in progress, counting is started at the new count
value following output of the pulse currently being
counted. And if the gate inpllt is switched to "L"
level during counting, the counter output is forced
to switch to "H" level, the counting being restarted
by the rising edge of the gate input.
•
Mode 3 (squara waveform rate generator)
The counter output is switched to "H" level by the
mode setting. Counting is started in the same way as
described for mode 2 above.
The repeated square wave output appearing at the
counter output contains half the number of counts
as the set count value. If the set count value(n) is
an odd number, the repeated square wave output
consists of only (n + 1 )/2 clock inputs at "H" level
and (n - 1 )/2 clock inputs at "L" level.
If a new count value is written during counting, the
new count value is reflected immediately after the
#2 control word setting
#0 count value setting
#1 count value setting
MVI A,34H]
Counter #2 count value setting
OUTn2
MVI A,12H (LSB then MSB)
OUTn2
Note: nO:
n1:
n2:
n3:
•
Counter #0 address
Counter #1 address
Counter #2 address
Control word register address
The minimum and maximum count valu. which can
be counted in each mode are listed below.
Remarks
Mode
Min.
Max.
0
1
0
1
1
0
2
2
0
1 cannot be counted
3
2
1
1 executes 10001 H count
4
1
0
5
1
0
o executes 10000H count
(ditto in other modes)
Mode Definition
• Mode 0 (terminal count!
The counter output is set to "L" level by the mode
setting. If the count value is then written in the
counter with the gate input at "H" level (that is,
upon completion of writing the MSB when there are
two bytes), the clock input counting is started.
When the terminal count is reached, the output is
switched to "H" level and is maintained in this
status IJntii the control word and count value are set
again.
Counting is interrupted if the gate input is switched
to "L" level, and restarted when switched back to
"H"level.
When Count Values are written during counting,
the operation is following.
183
• I/O· MSM82C53-5RS/GS • - - - - - - - - - - - - - - - - - change ("H" to "l" or "l" to "H") in the next
counter output to be executed. The counting operation at the gate input is done the same as in mode 2.
•
stopped when the gate input is switched to "l"
level, and restarted from the set count value when
switched back to "H" level.
•
Mode 4 (software trigger strobe)
The counter output is switched to "H" level by the
mode setting. Counting is started in the same way
as described for mode O. A single "l" pulse equivalent to one clock width is generated at the counter
output when the terminal count is reached.
This mode differs from 2 in that the "l" level output appears one clock earlier in mode 2, and that
pulses are not repeated in mode 4. Counting is
Mode
~
Mode 5 (hardware trigger strobe)
The counter output is switched to "H" level by the
mode setting. Counting is started, and the gate input
used, in the same way as in mode 1.
The counter output is identical to the mode 4 output.
The various roles of the gate input Signals in the
above modes are summarized in the following table.
"l" level Falling Edge
0
Rising Edge
"H" level
Counting not possible
Counting possible
(1)
1
(2)
2
3
Start of counting
Retriggering
(1 )
(2)
Counting not possible
Counter output forced to "H" level
Start of counting
Counting possible
(1)
Counting not possible
Counter output forced to "H" level
Start of counting
Counting possible
(2)
Counting not possible
4
Counting possible
(1 )
(2)
5
Start of counting
Retriggering
Mode 0
ClK
[
WR
~
OUT (GATE = 'H')
WR (n=4)]
[
,
3
2
0
~
0
2
i
I
i
I
I
GATE
II
4
OUT
3
I
0
2
I
I
Mode 1
ClK
WR (n=4il
[
[
184
GATE
J
GATE
OUT (n= 4)
4
3
2
J
4
I
0
I
I
OUT
3
LJI4
2
3
2
0
r
- - - - - - - - - - - - - - - - - - . I/O· MSM82C53-5RS/GS •
Mode 2
elK
[
[
WR
1
•
(n = 41
OUT (GATE = 'H'I
(n= 21
4
3
2
4
3
I
2
4
3
2
1
J
4
1
2
1
4
3
2
LJ
OUT (n=41
2
~
LJ
,
GATE
1
a
1
L
Mode 3
elK
[
[
WR
1
•
.(n=41
I (n = 31 I
4
2
4
4
2
2
4
2
3
2
3
3
Lr
I
I
OUT (GATE = 'H'I
I
GATE
5
2
4
5
5
2
4
2
L-J
OUT(n~
5
I
2
5
4
I
Mode 4
elK
[
[
WR
,
-,
4
3
0
2
LJ
OUT (GATE = 'H'I
f
GATE
4
4
3
0
2
Lr-
OUT
ModeS
elK
GATE
--.t
4
3
0
2
LJ
OUT (n';41
GATE
---1
t
4
3
2
1
4
3
OUT (n= 41
2
0
LJ
Note: "n" is the value set in the counter.
Figures in these diagrams refer to counter values.
185
• I/O· MSM82C53-5RS/GS • - - - - - - - - - - - - - - - - - Reading of Counter Values
All 82C53-5 counting is down-counting, the
counting being in steps of 2 in mode 3. Counter values
can be read during counting by (1) direct reading, and
(2) counter latching ("read on the fly").
•
I
[J
I
•
Direct reading
Counter values can be read by direct reading operations.
Since the counter value read according to the timing
of the RD and ClK signals is not guaranteed, it is
necessary to stop the counting by a gate input signal,
or to interrupt the clock input temporarily by an
external circuit to ensure that the counter value is
correctly read.
Counter latching
In this method, the counter value is latched by
writing a counter latch command, thereby enabling
a stable value to be read without effecting the
counting in any way at all. An example of a counter
latching program is given below.
Counter latching executed for counter #1 (Read/
load 2-byte setting)
MVI A
01 00 x x x x
~ Denotes counter latching
OUT n3 L W r i t e in control word address
(n3)
The counter value at this point
is latched
IN n1 L R e a d i n g of the lSB of the
counter value latched from
counter #1.
n1: Counter #1 address
MOV B,A
IN n1
MOV C,A
186
Reading of MSB from counter
#1.
Example of Practical Application
•
82C53-5 used as a 32-bit counter.
82C53-5
,..
~
~
ClKO
aUTO
..,
""
r - - ClK1
OUT1
"V
ClK2
OUT2 r -
Use counter #1 and counter #2
Counter #1: mode 0,. upper order 16-bit counter
value
Counter #2: mode 2, lower order 16-bit counter
value
This setting enables counting up to a maximum of 2 32 •
OKI
semiconductor
MSM82C55A-5RS/GS
CMOS PROGRAMMABLE PERIPHERAL INTERFACE
GENERAL DESCRIPTION
MSM82C55A-5 is a programmable universal I/O interface device which operates at a high speed and on a low
power consumption due to the 3 JJ. silicon gate CMOS technology. It is the best fit as I/O port in a system which
employs 8-bit parallel processing CPU MSM80C85A. Basically. this device has 24-bit I/O pins equivalent to three
8-bit I/O ports and all inputs/outputs are TTL interface compatible.
FEATURES
• High speed and low power consumption, due to 3 JJ.
silicon gate CMOS technol,ogy
• 3 V to 6 V single power supply
• Full static operation
• Programmable 24-bit I/O ports
• Bidirectional bus operation (Port A)
• Bit set/reset function (Port C)
• TTL compatible
.40-pin DIP (MSM82C55A-5RS)
• 44-pin flat package (MSM82C55A-5GS)
• Compatible with 8255A-5
CIRCUIT CONFIGURATION
VCC---+e-
GND----+-e-
PA O - PA,
PC4 - PC,
8
Do - 0,
DATA
BUS
BUFFER
PCo - PC3
RD
WR
RESET
READ/
WRITE
CONTROL
LOGIC
PB o - PB,
CS
Ao
A1
187
• I/O· MSM82C55A-5RS/GS • - - - - - - - - - - - - - - - - PIN CONFIGURATION
MSM82C55A·5RS (Top View)
PA3
PA2
PAl
PAo
RD
CS
GNO
A1
Ao
PC,
40 Lead Plastic DIP
fJ
1
PA6
PA,
WR
RESET
Do
01
02
03
04
Os
06
0,
PCs
PC4
PCo
PC1
PC2
PC3
PBo
PB1
PB2
VCC
PB,
PB6
PBs
PB4
PB3
MSM82C55A·5GS (Top View)
44 Lead' Plastic Flat Package
44 43 42 41 40 3938 37 36 35 34
CS
GNO
A1
Ao
PC,
PC 6
PCs
PC4
PC o
PC 1
PC2
1
33
32
0
2
3
31
4
30
29
5
6
7
28
8
26
25
27
9
10
24
11
23
12 13 14 15 16 1718 19 20 21 22
(.)
..,
0
-
...
·(.)COCOCO
ZQ.Q.Q.Q.
188
(.)
..,
~
III'
RESET
Do
01
02
03
04
Os
06
0,
VCC
PB,
'" (.)
~~~~~i.
(N.C: Not Connected)
----------------~-.
I/O· MSM82C55A-5RS/GS •
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Limits
Conditions
MSM82C55A-5RS
VOUT
Ta = 25"C
with
respect
to GND
Storage Temperature
Tstg
-
Power Dissipation
Po
Ta = 25°C
Supply Voltage
VCC
Input Voltage
VIN
Output Voltage
Unit
MSM82C55A-5GS
J
-0.5 to +7
V
-0.5 to VCC -to.5
V
-0.5 to VCC -to.5
V
-55 to +150
°c
I
1.0
W
0.7
OPERATING RANGE
Parameter
Symbol
Limits
Supply Voltage
VCC
3 to 6
Operating Temperature
TOp
-40 to
Unit
V
°c
85
RECOMMENDED OPERATING RANGE
Symbol
Min.
Typ.
Max.
Supply Voltage
Parameter
VCC
4.5
5
5.5
V
Operating Temperature
TOp
-40
+25
+85
°c
"L" Input Voltage
VIL
-0.3
+0.8
V
VIH
2.2
VCC+0.3
V
"H" Input Voltage
Unit
DC CHARACTERISTICS
Parameter
"L" Output Voltage
"H" Output Voltage
Symbol
VOL
Conditions
IlA
IOIH = -40 ",A
Input Leak Current
III
O~ VIN::; VCC
Output Leak Current
ILO
0::; VOUT':sVCC
ICCS
CS~ VCC -D.2V
VIH ~ VCC-0.2V
Supply Current (standby)
Typ.
10L = 2.5mA
10H = -400
VOH
Min.
VCC=4.5V to 5.5V
Ta = -40°C to +85"c
Max.
Unit
0.45
V
2.4
V
4.2
V
-10
10
",A
-10
10
",A
100
",A
5
mA
0.1
VIL ~0.2V
Average Supply Current
(active)
ICC
I/O write cycle
time: 1 #J.S
189
• I/O· MSM82C55A-5RS/GS • - - - - - - - ' - - - - - - - - - - - - AC CHARACTERISTICS
(Vcc = 4.5V to 5.5V, Ta = -40 to +85°C)
Parameter
Symbol
Min.
Max.
Unit
Setup Time of address to the falling edge of RD
tAR
Hold Time of address to the rising edge of RD
RD Pulse Width
Delay Time from the falling edge of RD to the output
of defined data
tRD
Delay Time from the rising edge of RD to the floating
of data bus
tDF
10
Time From the rising edge of RD or WR to the next
falling edge of RD or WR
tRY
850
ns
ns
20
ns
tRA
20
ns
tRR
300
ns
200
ns
100
ns
Setup Time of address before the falling edge of WR
tAW
0
Hold Time of address after the rising edge of WR
twA
30
ns
WR Pulse Width
tww
300
ns
Setup Time of bus data before the rising edge of WR
tow
100
ns
Hold Time of bus data after the rising edge of WR
two
40
ns
Delay Time from the rising edge of WR to the output
of defined data
twB
350
ns
Setup Time of port data before the falling edge of RD
tlR
20
ns
Hold Time of port data after the rising edge of RD
tHR
20
ns
ACK Pulse Width
tAK
300
ns
STB Pulse Width
tST
300
ns
Setup Time of port data before the rising edge of STB
tpS
20
ns
Hold Time of port data after the rising edge of STB
tPH
180
ns
Delay Time from the falling edge of ACK to the output
of defined data
tAD
Delay Time from the rising edge of ACK to the floating
of port (Port A in mode 2)
tKD
20
300
ns
250
ns
Delay Time from the rising edge of WR to the falling
edge of OBF
twOB
650
ns
Delay Time from the falling edge of ACK to the rising
edge of OBF
tAOB
350
ns
Delay Time from the falling edge of STB to the rising
edge of IBF
tSIB
300
ns
Delay Time from the rising edge of RD to the falling
edge of IBF
tRIB
300
ns
Delay Time from the falling edge of RD to the falling
edge of INTR
tRIT
400
ns
Delay Time from the rising edge of STB to the rising
edge of INTR
tSIT
300
ns
Delay Time from the rising edge of ACK to the rising
edge of INTR
tAIT
350
ns
Delay Time from the falling edge of WR to the falling
edge of INTR
twiT
850
ns
Note: Timing is measured at Vt.:. = 0.8 V and VH = 2.2 V for both inputs and outputs.
190
Remarks
Load
150 pF
- - - - - - - - - - ' - - - - - - - - - - - - . I/O' MSM82C55A-5RS/GS •
Basic Input Operation (Mode 0)
____________________~I-----tRR-----.~,---------------------Port input
07 - Do - - - - - - - - - - - i-----tOF------t
Basic Output Operation (Mode 0)
07 - Do
----~-----t-A-W------~----J
CS.Al.Ao
Port output
----------------------------------~~-------
Strobe Input Operation (Mode 1)
ISF
INTR
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~-JI
-~---------------
Port input
I-------tps----I
191
• I/O· MSM82C55A-5RS/GS • - - - - - - - - - - - - - - - - - Strobe Output Operation (Mode 1)
OBF
INTR
ACK
Port output
tWB
Bidirectional Bus Operation (Mode 2)
WR
OBF
INTR
ACK
STB
IBF
Port A - - - - - - - - -
192
- - - - - - - - - - - - - - - - - - . I/O' MSM82C55A-5RS/GS •
OUTPUT CHARACTERISTICS (REFERENCE VALUE)
Output "H" Voltage (VOH)
Output Current (lOH)
VI.
5
I
~
Ta = -40-85°e
4
::I:
0
Vec ='5.0V
>
3
CI)
Cl
!!!
(5
>
2
!-...
::J
9::J
0
0
o
-1
-2
-3
-4
-5
Output current IOH (rnA)
2
Output OIL" Voltage (VOL)
VI.
Output Current (lOL)
5
~
...J
4
0
>
CI)
tn
!!!
3
]
~
2
...
Vce = 5.0V
9::J
Tit = -40-85°e
::J
I
0
0
o
2
3
4
5
Output current IOL (rnA)
Note: The direction of flowing into the device is taken as positive for the output current.
193
• I/O· MSM82C55A-5RS/GS • - - - - - - - - - - - - - - - - - FUNCTIONAL DESCRIPTION OF PIN
Pin No.
Item
Function
Input/Output
07 - DO
Bidirectional
data bus
Input and
output
These are three-state 8-bit bidirectional buses used to write and
read data upon receipt of the WR and RD signals from CPU and
also used when control words and bit set/reset data are transferred from CPU to MSM82C55A-5.
RESET
Reset input
Input
This signal is used to reset the control register and all internal
registers when it is in high level. At this time, ports are all made
into the input mode (high impedance status).
CS
Chip select
input
Input
When the CS is in low level, data transmission is enabled with
CPU. When it is in high level, the data bus is made into the high
impedance status where no write nor read operation is performed.
Internal registers hold their previous status, however.
RD
Read input
Input
When RD is in low level, data is transferred from MSM82C55A-5
to CPU.
WR
Write input
Input
When WR is in low level, data or control words ate transferred
from CPU to MSM82C55A-5.
AO,A1
Port select
input
(address)
Input
By combination of AO and A 1, either one is selected from among
port A, port B, port C, and control register. These pins are usually
connected to low order 2 bits of the address bus.
PA7 - PAO
Port A
Input and
output
These are universal 8-bit I/O ports. The direction of inputs/outputs can be determined by writing a control word. Especially,
port A can be used as a bidirectional port when it is set to mode 2.
PB7 - PBO
Port B
Input and
output
These are universal 8-bit I/O ports. The direction of inputs/outputs can be determined by writing a control word.
PC7 - PCO
Port C
Input and
output
These are universal 8-bit I/O ports. The direction of inputs/outputs can be determined by writing a control word as 2 ports
with 4 bits each. When port A or port B is used in mode 1 or
mode 2 (port A only). they become control pins. Especially
when port C is used as an output port, each bit can be set/reset
independently.
VCC
+5 V power supply.
GND
GND
BASIC FUNCTIONAL DESCRIPTION
Group A and Group B
When setting a mode to a port having 24 bits, set
it by dividing it int() two groups of 12 bits each.
Group A: Port A (8 bits) and high order 4 bits
of port C (PC7 - PC4)
Group B: Port B (8 bits) and low order 4 bits of
port C (PC3 - PCO)
Mode 0, 1,2
There are 3 types of modes to be set by group as
follows:
Basic input operation/output operation
Mode 0:
(Available for both groups A and B)
Strobe input operation/output operaMode 1:
tion
(Available for both groups A and B)
Bidirectional bus operation
Mode 2:
(Available for group A only)
194
When used in mode 1 or mode 2, however, port C
has bits to be defined as ports for control signal for
operation ports (port A for group A and port B for
group B) of their respective groups.
Port A, B, C
The internal structure of 3 ports is as follows:
Port A:
One 8-bit data output latch/buffer and
one 8-bit data input latch
Port B:
One 8-bit data input/output latch/buffer and one 8-bit data input buffer
Port C:
One 8-bit data output latch/buffer and
one 8-bit data input buffer (no latch
for input)
Single bit set/reset function for port C
When port C is defined as output port, it is possible to set (to turn to high level) or reset (to turn to low
level) anyone of 8 bits individually without affecting
other bits.
- - - - - - - - - - - - - - - - - - . I/O· MSM82C55A-5RS/GS •
OPERATIONAL DESCRIPTION
Control Logic
Operations by addresses and control signals, e.g., read and write, etc. are as shown in the table below:
Operation
Input
Output
Control
Others
Al
AO
CS
WR
RD
0
0
0
1
0
Port A -Data Bus
Operation
0
1
0
1
0
Port B -+ Data Bus
1
0
0
1
0
Port C -+ Data Bus
0
0
0
0
1
Data Bus -+ Port A
0
1
0
0
1
Data Bus -+Port B
1
0
0
0
1
Data Bus -+Port C
1
1
0
0
1
Data Bus -+Control Register
1
1
0
1
0
Illegal Condition
x
x
1
x
x
Data bus is in the high impedance status.
Setting of Control Word
The control register is composed of 7-bit latch circuit and l-bit flag as shown below.
Group A Control Bits
Group B Control Bits
Definition of input!
output of low order
4 bits of port C.
o= outp.ut
{ 1 = Input
' - - - - - - - Definition of input!
output of 8 bits of
port B
{ o1 == Output
Input
' - - - - - - - - - - Mode definition
of group B
O= Mode 0
{ 1 = Mode 1
Definition of input!
output of high order
4 bits of port C
Definition of input!
output of 8 bits of
port A
{O1 == Output
Input
.fo = Output
1.1 = Input
' - - - - - - - - - - - - - - - - - - - - Mode definition of group A
' - - - - - - - - Control word identification flag
Be sure to set 1 for the control
word to define a mode and input!
output.
(When set to 0, it becomes the
control word for bit set!reset.)
Precaution for mode selection
The output registers for ports A and C are cleared
to cP each time data is written in the command register
and the mode is changed, but the port B state is undefined.
Os
Mode
0
Mode 0
0
1
Mode 1
1
x
Mode 2
06
0
Bit Set/Reset Function
When port C is defined as output port, it is possible
to set (set output to 1) or reset (set output to 0) any
one of 8 bits without affecting other bits as shown
next page.
195
• I/O· MSM82C55A-5RS/GS • - - - - - - - - - - - - - - - - -
I I I
06
07
I
Os
04
111
O2
03
01
I
Do
J
L
} De"";';o" of
1
Reset
Set
Port C
03
02
01
PCo
0
'0
0
'-----y-----'
PCl
0
0
1
Don't Care
PC2
0
1
0
PC3
0
1
1
PC4
1
0
0
bit wanted
to be set or
reset
~ Control word identification flag
Be sure to set to 0 for bit set/
reset.
(When set to 1 , it becomes the
control word to define a mode
and input/output,)
Interrupt Control Function
When MSM82C55A-5 is used in mode 1 or mode 2,
the interrupt signal for CPU is provided. The interrupt
request signal is output from port C. When the internal
flip-flop INTE is set beforehand at this time, the desired
interrupt request. signal is output. When it is reset
beforehand, however, the interrupt request signal is not
output. The set/reset of the internal flip-flop is made
by the bit set/reset operation for port C virtually.
Bit set -+ INTE is set -+ Interrupt allowed
Bit reset -+ INTE is reset -+ Interrupt inhibited
~ontrol
Word
06
Os
04
03
PCs
1
0
1
PC6
1
1
0
PC7
1
1
1
Operational Description by Mode
1. Mode 0 (Basic input/output operation)
Mode 0 makes MSM82C55A-5 operate as a basic
input port or output port. As no control signal
such as interrupt request, etc. is required in this
mode. All of 24 bits can be used as two-B-bit ports
and two 4-bit ports. Sixteen combinations are then
possible for inputs/outputs. The inputs are not
latched, but the outputs are.
Group A
Type
07
{O ==
Definition of setlreset
for a desired bit
02
01
Do
Group B
Port A
High Order 4 Bits
of Port C
Port B
Low Order 4 Bits
of Port C
Output
1
1
0
0
0
0
0
0
0
Output
Output
Output
2
1
0
0
0
0
0
0
1
Output
Output
Output
Input
3
1
0
0
0
0
0
1
0
Output
Output
Input
Output
4
1
0
0
0
0
0
1
1
Output
Output
Input
Input
5
1
0
0
0
1
0
0
0
Output
Input
Output
Output
6
1
0
0
0
1
0
0
1
Output
Input
Output
Input
7
1
0
0
0
1
0
1
0
Output
Input
Input
Output
8
1
0
0
0
1
0
1
1
Output
Input
Input
Input
9
1
0
0
1
0
0
0
0
Input
Output
Output
Output
10
1
0
0
1
0
0
0
1
Input
Output
Output
Input
11
1
0
0
1
0
0
1
0
Input
Output
Input
Output
12
1
0
0
1
0
0
1
1
Input
Output
Input
Input
Output
13
1
0
0
1
1
0
0
0
Input
Input
Output
14
1
0
0
1
1
0
0
1
Input
Input
Output
Input
15
1
0
0
1
1
0
1
0
Input
Input
Input
Output
16
1
0
0
1
1
0
1
1
Input
Input
Input
Input
Note: When used in mode 0 for both groups A and B
196
- - - - - - - - - - - - - - - - - - . I/O· MSM82C55A-5RS/GS •
2. Mode 1 (Strobe input/output operation)
In this mode 1, the strobe, interrupt and other
control signals are used when input/output operations are made from a specified port_ This mode is
available for both groups A and B. In group A at
this time, .port A is used as data line and port C as
the control signal.
Following is a descrption of the input operation in
mode 1.
STB (Strobe input) .
• When this signal is in low level, the data output
from terminal to port is fetched into the internal
latch of the port. This can be made independent
from CPU and the data is not output to the
data bus until the RD signal arrives from CPU.
IBF (Input buffer full flag output)
• This is the response signal for the STB. This
signal when turned to high level indicates that
data is fetched into the input latch. This signal
turns to high level at the falling edge of STB and
low level at the rising edge of RD.
INTR (Interrupt request output)
• This is the interrupt request signal for CPU of
the data fetched into the input latch. It is indicated by high level only when the internal INTE
flip-flop is set. This signal turns to high level at
the rising edge of the STB ClBF = 1 at this time)
and low level at the falling edge of the RD when
Mode 1 Input
the INTE is set.
INTEA of group A is set when the bit for PC4 is
set, while INTEB of group B is set when the bit
for PCz is set.
Following is a description of the output operation of mode 1.
OBF (Output buffer full flag output)
• This signal when turned to low level indicates
that data is written to the specified port upon receipt of the i7im signal from CPU. This Signal
turns to low level at the rising edge of the "WFf
and high level at the falling edge of the ACK.
ACK (Acknowledge input)
• This signal when turned to low level indicates
that the terminal has received data.
INTR (Interrupt request output)
• This is the signal used to interrupt CPU when a
terminal receives data from CPU via MSM82C55A-5. It indicates the occurrence of the interrupt in high level only when the internal I NTE
flip-flop is set. This signal turns to high level
at the rising edge of the ACK (OBF = 1 at this
time) and low level at the falling edge of WR
when the INTEB is set.
INTEA of group A is set when the bit for PC 6
is set, while INTEB of group B is set when the
bit for PCz is set.
Mode 1 output
(Group A)
r--,
IINTEAI
L
_ .....
(Group t;J)
r--,I
I
IINTEBI
L
_..J
PB7
1
PBo
Note: Although belonged to group B, PC3 operates as
the control signal of group A functionally.
197
• I/O· MSM82C55A-5RS/GS • - - - - - - - - - - - - - - - - - Port C Function Allocation in Mode 1
1\
Combination of
Input/Output
\
Port C
a
I
Note:
Group A: Input
Group B: Input
Group A: Input
Group B: Output
Group A: Output
Group B: Input
Group A: Output
Group B: Output
PCo
INTRB
INTRB
INTRB
INTRB
PC l
IBFB
OBFB
IBFB
OBFB
PC 2
STBB
ACKB
STBB
ACKB
PC3
INTRA
INTRA
INTRA
INTRA
PC4
STBA
STBA
I/O
I/O
PC s
IBFA
IBFA
I/O
I/O
PC 6
I/O
I/O
ACKA
ACKA
PC,
I/O
I/O
OBFA
OBFA
I/O is a bit not used as the control signal, but it is available as a port of mode O.
Examples of the relation between the control words and pins when used in mode 1 is shown below:
(a) When group A is mode 1 output and group B is mode 1 input.
0,
Cont.ol wo",
06
I I I
1
0
05
1
03
04
I
0
I
1/0
02
01
I I I
1
1
L
Do
2~I
A,
Selection of I/O
of PC4 and PC s
when not defi ned
as a control pin.
of PC. -PC,
bits become a control
pin in this case, this
bit is "Don't Care".
{1 = Input
0= Output
8
PA7-PAO
WR-
I-t-
PC, I-- OBFA
PC6 I-- ACKA
PC 3 f-- INTRA
2
PC4,PCS ~ I/O
PB7-PBO
~
PC2 I-- STBB
RO-
PCl
I-- IBFB
PCo I-- INTRB
198
( Group A: Mode 1 output)
Group B: Mode 1 input
- - - - - - - - - - - - - - - - - - . I/O· MSM82C55A-5RS/GS •
(b)
When group A is mode 1 input and group B is mode 1 output.
D,
D6
Ds
D4
D3
D2
D1
Do
0
X
1/0
0
Selection of I/O of PCG
and PC7 when not defined as a control pin
fJ
{1 = Input
0= Output
8
PA7-PAO
RD
PC4
STBA
PCs
IBFA
PC3
INTRA
PC6,PC7
WR
(Group A: Mode 1 input )
Group B: Mode 1 output
I/O
PCl
OBFB
PC2
ACKB
INTRB
3. Mode 2 (Strobe bidirectional bus I/O operation)
STB (Strobe input)
In mode 2, it is possible to transfer data in 2 directions I/O through a single 8-bit port. This operation
is akin to a combination between input and output
operations. Port C waits for the control signal in
this case, too. The mode 2 is available only for
group A, however.
Next, a description is made on mode 2.
•
OBF (Output buffer full flag output)
•
This signal when turned to low level indicates
that data has been written to the internal output
latch upon receipt of the WR signal from CPU.
At this time, port A is still in the high impedance
status and the data is not yet output to outside.
This signal turns to low level at the rising edge
of the WR and high level at the falling edge of
the ACK
ACK (Acknowledge input)
• When low level signal is input to this input pin,
the high impedance status of port A is cleared,
the buffer is enabled, and _the data written to
the internal output latch is output to port A.
When the input returns to high level, port A is
made into the high impedance status.
When this signal turns to low level, the data
output to port from pin is fetched into the
internal input latch. The data is output to the
data bus upon receipt of the RD signal from
CPU, but it remains in the high imPedance status
until then.
IBF (Input buffer full flag output)
•
This signal when turned to high level . indicates
that data from pin has been fetched into the input latch. This Signal turns to high level at the
falling edge of the STB and low level at the
rising edge of the RD.
INTR (Interrupt request output)
•
This signal is used to interrupt CPU and its operation in the same as in mode 1. There are two
INTE flip-flops internally available for input and
output to select either interrupt of input or output operation. The INTE1 is used to control
the interrupt request for output operation and
it can be reset by the bit set for PCG. The
INTE2 is used to control the interrupt request
for the input operation and it can be set by the
bit set for PC4.
199
• I/O· MSM82C55A-5RS/GS • - - - - - - - - - - - - - - - - - Mode 2 I/O Operation
Port C Function Allocation in Mode 2
Port C
PCo
PC l
Function
Confirmed to the
group B mode
PC2
PC3
INTRA
PC4
STBA
PCs
IBFA
PC6
ACKA
PC,
OBFA
Following is an example of the relation between
the control word and pin when used in mode 2.
When input in mode 2 for group A and in mode 1
for group B.
As all of 8 bits of port C becomes control pins in this
case, 03 and DO bits are
treated as "Don't Care".
When group A is set to
mode 2, this bit is
treated as "Don't Care".
No I/O specification is required
for mode 2, since it is a bidirectional operation. This bit is
therefore treated as "Don't Care".
OBFA
ACKA
STBA
IBFA
STBB
200
PCl
IBFB
.pC o
INTRa
f Group A:
mode 2
)
\ Group B: mode 1 input
- - - - - - - - - - - - - - - - - - . I/O· MSM82C55A-5RS/GS •
4. When Group A is Different in Mode from Group B
possible to set the one not defined as control pin
in port C to both input and output as a port which operates in mode 0 at the 3rd and Oth bits of the
control word.
Group A and group B can be used by setting them
in different modes each other at the same time.
When either group is set to model or mode 2, it is
(mode conbinations that define no control bit at port C)
Port C
Group A
Group B
PC,
PC6
PCs
PC4
PC3
PC2
PCl
PCo
1
Mode 1
input
Mode 0
I/O
I/O
IBFA
STBA
INTRA
I/O
I/O
I/O
2
Mode 0
output
Mode 0
OBFA
ACKA
I/O
I/O
INTRA
I/O
I/O
I/O
3
Mode 0
Mode 1
input
I/O
I/O
I/O
I/O
I/O
STBB
IBFB
INTRB
4
Mode 0
Mode 1
output
I/O
I/O
I/O
I/O
I/O
ACKB
OBFB
INTRB
5
Mode 1
input
Mode 1
input
I/O
I/O
IBFA
STBA
INTRA
STBB
IBFB
INTRB
6
Mode 1
input
Mode 1
output
I/O
I/O
IBFA
STBA
INTRA
ACKB
OBFB
INTRB
7
Mode 1
output
Mode 1
input
OBFA
ACKA
I/O
I/O
INTRA
STBB
IBFB
INTRB
8
Mode 1
output
Mode 1
output
OBFA
ACKA
I/O
I/O
INTRA
ACKB
OBFB
INTRB
9
Mode 2
Mode 0
OBFA
ACKA
IBFA
STBA
INTRA
I/O
I/O
I/O
.
Controlled at the 3rd bit (03)
of the control word
When the I/O bit is set to input in this case, it is
possible to access data by normal port C read operation.
When set to output, PC7 - PC4 bits can be accessed
by the bit set/reset function only. While, 3 bits from
PC2 to PCO can be accessed by normal write operation.
Controlled at the Oth bit (DO)
of the control word
The bit set/reset function can be used for all of
PC3 - PCO bits. Note that the status of port C
varies according to the combination of modes like
this.
201
• I/O· MSM82C55A-5RS/GS • - - - - - - - - - - - - - - - - - 5. Port C Status Read
When port C is used for the control signal, that is,
in either mode 1 or mode 2, each control signal and
Group A
11
I
bus status signal can be read out by reading the
content of port C.
The status read out is as follows:
Status read on the data bus
Group B
07
06
Os
04
03
02
01
00
1
Mode 1
input
Mode 0
I/O
I/O
IBFA
INTEA
INTRA
I/O
I/O
I/O
2
Mode 1
output
Mode 0
OBFA
INTEA
I/O
I/O
INTRA
I/O
I/O
I/O
3
Mode 0
Mode 1
input
I/O
I/O
I/O
I/O
I/O
INTEB
IBFB
INTRB
4
Mode 0
Mode 1
output
I/O
I/O
I/O
I/O
I/O
INTEB
OBFB
INTRB
5
Mode 1
input
Mode 1
input
I/O
I/O
IBFA
INTEA
INTRA
INTEB
IBFB
INTRB
6
Mode 1
input
Mode 1
output
I/O
I/O
IBFA
INTEA
INTRA
INTEB
OBFB
INTRB
7
Mode 1
output
Mode 1
input
OBFA
INTEA
I/O
I/O
INTRA
INTEB
IBFB
INTRB
8
Mode 1
output
Mode 1
output
OBFA
INTEA
I/O
I/O
INTRA
INTEB
OBFB
INTRB
9
Mode 2
Mode 0
OBFA
INTEl
IBFA
INTE2
INTRA
I/O
I/O
I/O
10
Mode 2
Mode 1
input
OBFA
INTEl
IBFA
INTE2
INTRA
INTEB
IBFB
INTRB
11
Mode 2
Mode 1
output
OBFA
INTEl
IBFA
INTE2
INTRA
INTEB
OBFB
INTRB
6. Reset of MSM82C55A-5
Be sure to keep the RESET signal at power ON in
the high level at least for 50 J,lS. Subsequently, it
becomes the input mode at a high level pulse above
500 ns.
Notes:
After a write command is executed to the command register, the internal latch is cleared in PORTA PORTC. For
instance,OOH is output at the beginning of a write command when the output port is assigned. However, if PORTB
is not cleared at this time, PORTB is unstable. In other words, PORTB only outputs ineffective data (unstable value
according to the device) during the period from after a write command is executed till the first data is written to
PORTB.
202
OKI
semiconductor
MSM82C59A-2RS/GS
PROGRAMMABLE INTERRUPT CONTROLER
GENERAL DESCRIPTION
The MSM82C59A-2 is a programmable interrupt controller for use in MSM80C85A1 A-2 and MSM80C86/88
microcomputer systems.
Based on CMOS silicon gate technology, this device features an extremely low standby current of 100J,tA (max.)
in chip non-selective status. And during interrupt control status, the power consumption is still very low with only 5
mA (max,) being required.
Internally, the MSM82C59A-2 can control priority interrupts up to 8 levels, and can be expanded up to 64 levels
by cascade connections of a number of devices.
FEATURES
• Silicon gate CMOS technology for high speed and low
power consumption.
.3 V to 6 V single power supply
• 80C85A system compatibility
• 80CS6/88 system compatibility
• 8-level priority interrupt control
• Interrupt levels expandable up to 64 levels
•
•
•
•
•
•
Programmable interrupt mode
Maskable interrupt
Automatically generated CALL code (85 mode)
'TTL compatible
28-pin plastic DIP (MSM82C59A-2RS)
32-pin plastic flat package (MSM82C59A-2GS)
CIRCUIT CONFIGURATION
DATA BUS
BUFFER
Ri5
IR,
WR
IR,
A"
IR,
IR,
IR,
cs
IRs
IR,
IR,
INTERRUPT MASK REGISTER (lMRI
INTERNAL BUS 18 b,tl
MSM82C59A-2 Internal block dLagram
203
• I/O' MSM82C59A-2RS/GS • - - - - - - - - - - - - - - - - - PIN CONNECTIONS
MSM82C59A-2 GS (top view)
32-pin lead plastic flat package
MSM82C59A-2RS (top view)
28-pin lead plastic DIP
CS
~
WR
VCC
AO
RO
CS
10
WR
2
31
VCC
AO
INTA
RO
3
INTA
0,
06
IR,
N.C.
4
N.C.
IR6
0,
5
lA,
Os
04
IRS
06
6
IA6
IR4
0
5
7
lAs
03
IR3
04
8
IR4
O2
IR2
IR3
IRI
03
O2
9
01
10
IA2
Do
CAS o
IRo
01
11
IRI
INT
Do
N.C.
12
13
IRo
N.C.
CASu
CAS I
GNO
14
INT
15
S1S"/EN
16
CAS 2
SP/EN
CAS I
GNO
CAS 2
NC: Not Connected
ELECTRIC CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Limits
Conditions
MSM82G59A-2AS
Power supply voltage
VCC
Input voltage
VIN
Output voltage
Storage temperature
Power dissipation
-0.5 - VCC + 0.5
V
-0.5 - VCC + 0.5
V
Ta
= 25°C
°c
-55-+150
-
Tstg
Unit
V
-0.5 - +7
Respect to GNO
VOUT
PO
I MSM82C59A-2GS
0.9
I
0.7
W
Operating Ranges
Symbol
Range
Power supply voltage
VCC
3-6
V
Operating temperature
TOp
-40 - +85
°c
Parameter
Unit
Recommended Operating Conditions
Symbol
Max.
Typ.
Min.
Power supply voltage
VCC
4.5
5
5.5
V
Operating temperature
Top
-40
+25
+85
°c
"L" level input voltage
VIL
-0.5
+0.8
V
"H" level input voltage
VIH
2.2
VCC +0.5
V
Parameter
204
Unit
- - - - - - - - - - - - - - - - - - . I/O· MSM82C59A-2RS/GS •
DC Characteristics
Parameter
Symbol
"L" level output voltage
VOL
"H" level output voltage
VOH
I nput leak current
III
IR Input leak current
ILiR
Output leak current
ILO
Conditions
IOL
= 2.5
IOH
= -2.5 mA
IOH
= -100 J.l.A
Max.
Unit
0.4
V
V
vee VCC=4.5V-5.5V
Ta=-4
(
rl--------~~--~~--~~~~------------_,
Cascade bus
a
~..>
CS AO DO-71INTA
CAS0-2V--
82C59A-2
(Slave)
SP/EN
7
L--
6
5
4
3
INT~
2
o
ct:
82C59A-2
GND
7
CAS0-2
(Slave)
EN
6,
5
4
3
INT
2
0
t ~..>
+ ~..>
~
CS AO D(}'7 INTA
CAS0-2
82C59A-2
SP/EN
INT I---
(Master)
M7 M6 M5 M4 M3 M2 M1 MO
t
1
•
.::::.
o
7
6
5
4
3
2
o
7
6
5
4
3
2
o
7
5
4
2
o
s::en
s::
Q)
N
Interrupt requests
82C59A-2 cascade connections
o
U'I
~
N
::ll
en
.......
N
~
<0
G)
en
•
OKI
semiconductor
MSM82C84ARS/GS
CLOCK GENERATOR AND DRIVER
GENERAL DESCRIPTION
The MSM82C84ARS/GS is a clock generator designed to generate MSM80C86 and MSM80C88 system clocks.
Due to the use of silicon gate CMOS technology, standby current is only 100~A (MAX.), and the power consumption is still very low with 10MA (MAX.) when a 5MHz clock is generated.
FEATURES
• Operating frequency of 6 to 15 MHz (ClK output 2
to 5 MHz)
• 3~ silicon gate CMOS technology for low power consumption
• Built-in crystal oscillator circuit
• 3V ~ 6V single power supply
• Built-in synchronized circuit for MSM80C86 and
MSM80C88 READY and RESET
• TTL compatible
• Built-in Schmitt trigger circuit (RES input)
• 18-pin DIP (MSM82C84ARS)
• 24-pin flat package (MSM82C84AGS)
FUNCTIONAL BLOCK DIAGRAM
-~
I
RES~----------------------------~
D
RESET
Q
X1
OSC
X2
1
1
2'
'3
EFI4---------------~--'
S
Y
N
C
CSYNC~------------------------------~----~--~r---~
RDY1-r------------,
PClK
S
Y
N
C
ClK
AEN1~---------------O--'
AEN2~---------------q
RDY2~------------~
ASYNC~----------------------------------~
220
READY
- - - - - - - - - - - - - - - - - - . I/O· MSM82C84ARS/GS •
PIN CONFIGURATION
18 lead Plastic DIP
•
VCC
X1
9
X2
AEN1
ASYNC
EFI
FIC
RDY2
OSC
RES
RESET
GND 9
24 lead Plastic Flat Package
CSYNC
10
VCC
PClK
2
N·C
3
22
X2
AEN1
4
21
N·C
20
ASYNC
X1
RDY1
5
READY
6
EFI
N·C
7
N·C
RDY2
8
FIC
AEN2
9
OSC
N·C
N·C
ClK
RES
GND
13
RESET
(N·e not connected)
221
• I/O· MSM82C84ARS/GS • - - - - - - - - - - - - - - - - - ABSOLUTE MAXIMUM RATINGS
Limits
Parameter
Symbol
Supply Voltage
+7
V
VIN
-0.5
-0.5
~
V CC +0.5
V
VOUT
-0.5
~
VCC +0.5
V
VCC
Input Voltage
Output Voltage
Storage Temperature
Unit
I MSM82C84AGS
MSM82C84ARS
Tstg
Power Dissipation
-55
0.8
Po
~
~
Respect to G N 0
°c
+150
I
Conditions
-
W
0.7
Ta
= 25°C
OPERATING RANGES
Parameter
Symbol
Limits
Supply Voltage
VCC
3~6
V
Operating Temperature
TOp
~
°c
-40
Unit
+85
RECOMMENDED OPERATING CONDITIONS
Symbol
MIN
TYP
MAX
Supply Voltage
Parameter
VCC
4.5
5
5.5
V
Operating Temperature
TOp
-40
+25
+85
°c
"L" Level Input Voltage
VIL
-0.3
+0.8
V
VCC +0.3
V
"H" Level Input Voltage (except RES)
Unit
2.2
VIH
"H" Level Input Voltage (RES)
3.0
DC CHARACTERISTICS
Parameter
"L" Level Output Voltage
"H" Level Output Voltage
RES Input Hysteresis
Input Leak Current
Symbol
MIN
MAX
Unit
VOL
-
0.45
V
IOL
= 5mA
IOH
= -lmA
VOH
3.7
-
V
VIHR
-VILR
0.25
-
V
III
-10
10
JJ.A
Conditions
-
O~ VIN~ VCC
Xl ~ VCC -0.2V
VCC
~
= 4.5V
5.5V
X2 ~ 0.2V
Standby Supply Current
ICCS
-
100
JJ.A
Fie ~
vcc -0.2V
VIH ~ VCC -0.2V
VIL ~ 0.2V
Operating Supply Current
222
ICC
-
10
mA
Input frequency
15 MHz
Output load capacitance
CL = OpF
Ta
= -40°C
~ +85°C
- - - - - - - - - - - - - - - - - - . I/O' MSM82C84ARS/GS •
AC CHARACTERISTICS
(Vce = 5V ±10%, Ta = -40 - 85°e)
(1)
Parameter
Conditions
MIN
tEHEl
20
ns
90%-90%
EF I "L" Pulse Width
tElEH
20
ns
10%-10%
tElEl
66
ns
EFI Cycle Time
6
Crystal Oscillator Frequency
MAX
Unit
Symbol
EF I "H" Pulse Width
15
MHz
Set Up Time of ROY1 or ROY2 to
ClK Falling Edge (Active)
tR1VCl
35
ns
ASYNC
= High
Set Up Time of ROY1 or ROY2 to
ClK Rising Edge (Active)
tR1 VCH
35
ns
ASYNC
= low
Set Up Time of ROY1 or ROY2 to
ClK Falling Edge (Inactive)
tR1VCl
35
ns
Hold Time of ROY1 or ROY2 to
ClK Falling Edge
tClR1 X
0
ns
Set Up Time of ASYNC to ClK
Falling Edge
tAYVCl
50
ns
Hold Time of ASYNC to ClK
Falling Edge
tClAYX
0
ns
Set Up Time of AEN1 (AEN2) to
ROY1 (ROY2) Rising Edge
tA1R1V
15
ns
Hold Time of AEN1 (AEN2) to
ClK Falling Edge
tClA1X
0
ns
Set Up Time of CSYNC to EFI
Rising Edge
tYHEH
20
ns
Hold Time of CSYNC to EFI Rising
Edge
tEHYl
10
ns
CSYNC Pulse Width
tYHYl
2xtElEL
ns
Set Up Time of RES to ClK Falling
Edge
tl1HCl
65
ns
Hold Time of RES to ClK Falling
Edge
tCLl1H
20
ns
Output load
capacitance
elK output
Cl = 100pF
Others 30pF
Input Rising Edge Time
tlLlH
20
ns
Input Falling Edge Time
tlHll
20
ns
Note: Parameters where timing has not been indicated in the above table are measured at V l
for both inputs and outputs.
= 1.5V
and V H
= 1.5V
223
• I/O· MSM82C84ARS/GS • - - - - - - - - - - - - - - - - - AC CHARACTERISTICS
(Vcc = 5V ±10%, Ta = -40 - 85°C)
(2)
MIN
tClCl
200
ns
ClK "H" Pulse Width
tCHCl
65
ns
ClK "l" Pulse Width
tClCH
119
ns
Parameter
ClK Rising and Falling Edge Times
tCH1CH2
tCl2CL1
MAX
Unit
Symbol
ClK Cycle Time
15
ns
PClK "H" Pulse Width
tpHPl
180
ns
PClK "l" Pulse Width
tplPH
180
ns
Time from READY Falling Edge to
ClK Falling Edge
tRYlCl
-8
ns
Time .from READY Rising Edge to
ClK Rising Edge
tRYHCH
114
ns
Conditions
1.0V-3.5V
Output load
capacitance
ClK output
Cl = 100pF
Delay from ClK Falling Edge to
RESET Falling Edge
tCLIl
40
ns
Delay from ClK Falling Edge to
PClK Rising Edge
tClPH
22
ns
Delay from ClK Falling Edge to
PClK Falling Edge
tClPl
22
ns
Delay from OSC Falling Edge to ClK
Rising Edge
tOlCH
-5
22
ns
Delay from OSCFailing Edge to ClK
Falling Edge
tOlCl
2
35
ns
Output Rising Edge Time (Except
ClK)
tOlOH
15
ns
0.8V-2.2V
Output Falling Edge Time (Except
ClK)
tOHOl
15
ns
2.2V-0.8V
Others 30pF
Note: Parameters where timing has not been indicated in the above table are measured at V l = 1.5V and VH = 1.5V
for both inputs and outputs.
224
- - - - - - - - - - - - - - - - - ' - - . I/O· MSM82C84ARS/GS •
PIN DESCRIPTION
Pin symbol
Name
Input/
output
Function
CSYNC
Clock
synchronization
signal
Input
Synchronizing signal for output of in-phase ClK signals when more
than one MSM82C84A is used.
The internal counter is reset when this signal is at high level, and a
high level ClK output is generated. The internal counter is subsequently activated and a 33% duty ClK output is generated when
this signal is switched to low level.
When th is signal is used, external synchron ization of E F I is necessary.
When internal oscillator is used, it is necessary for th is pin to be kept
to be low level.
PClK
Peripheral clock
output
Output
This peripheral circuit clock signal is output in a 50% duty cycle at
a frequency half that of the clock signal.
AENl
Address enable
signals
Input
The AENl signal enables ROY1, and the AEN2 signal enables ROY2.
The respective ROY inputs are activated when the level applied to
these pins is low.
Although two separate inputs are used in multi-master systems, only
the AEN which enables the ROY input to be used is to be switched
to low level in the case of not using multi-master systems.
Bus ready signals
Input
Completion of data bus reading and writing by the device connected
to the system data bus is indicated when one of these signals is
switched to high level.
The relevant ROY input is enabled only when the corresponding AEN
is at low level.
READY
Ready output
Output
This signal is obtained by synchronizing the bus ready signal with
ClK.
This signal is output after guaranteeing the hold time for the CPU in
phase with the ROY input.
ClK
Clock output
Output
This signal is the clock used by the CPU and peripheral devices connected to the CPU system data bus. The output waveform is generated in a 33% duty cycle at a frequency 1/3 the oscillating frequency
of the crystal oscillator connected to the Xl and X2 pins, or at a
frequency 1/3 the EFI input frequency.
RES
Reset in
Input
This low-level active input is used to generate a CPU reset signal.
Since a Schmitt trigger is included in the input circuit for this signal,
"power on resetting" can be achieved by connection of a simple RC
circuit.
RESET
Reset output
Output
This signal is obtained by ClK synchronization of the input signal
applied to RES and is output in opposite phase to the RES input.
This signal is applied to the CPU as the system reset signal.
F/C
Clock select signal
Input
This signal selects the fundamental signal for generation of the ClK
signal. The ClK is generated from crystal oscillator output when this
signal is at low level, and from the EFI input signal when at high level.
EFI
External clock
signal
Input
The signal applied to this input pin generates the ClK signal when
F/C is at high level. The frequency of the input signal needs to be
three times greater than the desired ClK frequency.
Xl,X2
Crystal oscillator
connecting pins
Input
Crystal oscillator connections.
The crystal oscillator frequency needs to be three times greater than
the desired ClK frequency.
OSC
Crystal resonator
output
Output
Crystal oscillator output. This output frequency is the same as the
oscillating frequency of the oscillator connected to the Xl and X2
pins. As long as a Xtal oscillator is connected to the Xl and X2 pins,
th is output signal can be obtained independently even if F /C is set to
high level to enable the E F I input to be used for ClK generation
purposes.
AEN2
ROYl
ROY2
225
• J/O· MSM82C84ARS/GS' • - - - - - - - - - - - - - - - - - -
Pin symbol
---
ASYNC
Name
Ready
synchron ization
select signal
Input/
output
Input
Function
Signal for selection of the synchronization mode of the READY
signal generator circuit. When this signal is at low level, the READY
signal is generated by double synchronization. And when at high
level, the READY signal is generated by single synchronization.
Since this pin has not been equipped with internal pull-up resistance,
this pin must not be opened.
VCC
+5V power supply
GND
GND
TIMING CHART
ClK • PClK • OSC waveforms
EFI
OSC
CSYNC
tCLCL
tOLCL
tCH1CH2
tCHCL
CLK
tCLCH
tCLPL
tCL2CL1
tpHPL
PCLK
tCLPH
RESET waveform
----J'1
C L K - 1 ' ' - - - - . . . J I t.....
-1__
R E S - - - - - - - - - - - - . + ' -_ _ _ _ _ _· _
1=...., 'CLl1
r
Ii
~ i+-'"
.
HCL
r-
RESET
226
~
___________~________J~----------------------I~-t
. . _______
-
tCLlL
-----------------~. I/O· MSM82C84ARS/GS •
READY waveform (ASYNC = LI
ClK
RDYl-2-----------,jj
AENl-2---------~
ASYNC---------------~
tAYVCL
READY------------------~
tRYHCH
READY waveform (ASYNC = HI
tRlVCl
tR1VCL
ClK
RDYl-2 -------------------'1
AENl-2--------------~
tAYVCL
ASYNC-------------~
tRYHCH
READY---------------------~
227
• I/O· MSM82C84ARS/GS • -------------'----~---DESCRIPTION OF OPERATION
(1)
Oscillator Circuit
(2)
The MSM82C84A internal oscillator circuit can be
driven by connecting a crystal oscillator to the X 1 and
X2 pins.
The frequency of the crystal oscillator in this case
needs to be three times greater than the desired ClK
frequency.
And since oscillator circuit output (the same output as for the crystal resonator frequency) appears at
the OSC pin, independent use of this output is also
possible.
Recommended Oscillator Circuit
.-----e~---1X1
OSCt----
MSM82C84A
--._---tX2
When input frequency is 6 to 15 MHz,
C1
= C 2 = 33 pF
CLK=7
RDY
This circuit generates two clock outputs-ClK
obtained by dividing the input external clock or crystal
oscillator circuit output by three, and PClK obtained
by halving ClK. ClK and PClK are generated from the
external clock applied to the EF I pin when Fie is at
high level, and are generated from the crystal oscillator
circuit when at low level.
(3)
Reset Circuit
Since a Schmitt trigger circuit is used in the RES
input, the MSM82C84A can be reset by "power on" by
connection to a simple RC circuit. If the 80C86 or
80C88 device is used as the CPU in this case, it is necessary to keep the RES input at low level for at least
50/..ls after V CC reaches the 4.5V level.
(4)
Crystal oscillator
Clock Generator Circuit
Ready Circuit
The READY signal generator circuit can be set to
synchronization mode by ASYNC.
(i) When ASYNC is at low level
The RDY input is output as the READY signal by
double synchronization.
The high-level RDY input is synchronized once by
the rising edge of the ClK of the first stage flipflop (F1 in the circuit diagram), and then synchronized again by the falling edge of the ClK of the
next stage flip-flop (F2 in the circuit diagram),
resulting in output of a high-level READY output
signal (see diagram below!'
o The low-level RDY input is synchronized directly
by the falling edge of the ClK of the next stage
flip-flop, resulting in output of a low-level READY
output signal (see diagram below).
1\ c\ 1\
\
I
I
I
I
I
READY
228
t.
I
I
I
I
i
I
,
,I
I
~
- - - - - - - - - - - - - - - - - - . I/O· MSM82C84ARS/GS •
When ASYNC is at high level
The ROY input is output as the READY signal by
single synchronization.
o Both low-level and high-level ROY inputs are
Iii)
CLK=J\
ROY
~\
1\
\
I
j
I
I
r
I
1"L-
J\
D
I
I
I
I
I
I
\
I
,
I
I
I
READY
synchronized by the falling edge of the ClK of the
next stage flip-flop, resulting in output of respective low-level and high-level READY output signals
(see diagram belowl.
I
I
f
EXAMPLE OF USE (CSYNC)
The 82C84A 1/3 frequency divider counter is unsettled when the power is switched on. Therefore, the
CSYNC pin has been included to synchronize ClK with
another signal. When CSYNC is at high level, both ClK
and PClK are high-level outputs. If CSYNC is then
switched to low level, ClK is output from the next
input clock rising edge, and is divided by 3.
If CSYNC has not been synchron ized with the
input clock, use the following circuit to achieve the
required synchronization.
MSM82C84A
External
synchronizi ng
signal
External
clock signal
(EFI)
0
-rJ>r
Q
0
Q
CSYNC
J>CK~
CKt
r---
EFI ClK
ClK
When an external clock EFI is used as the clock source
MSM82C84A
External
synchronizing
signal
Xl
CSYNC
X2
0
CKt
Q
0
Q
CK~
OSC FIe
ClK
1
ClK
When the crystal oscillator is used as the clock source
229
OKI semiconductor
MSM82C84A-5RS/GS
CLOCK GENERATOR AND DRIVER
GENERAL DESCRIPTION
The MSM82C84A-5RS/GS is a clock generator designed to generate MSM80C86 and MSM80C88 system clocks.
Due to the use of silicon gate CMOS technology. standby current is only 40 fJ.A (MAX .). and the power consumption is still very low with 10MA (MAX.) when a 5MHz clock is generated.
FEATURES
• Operating frequency of 6 to 15 MHz (ClK output 2
to 5 MHz)
·3fJ. silicon gate CMOS technology for low power consumption
• Built-in crystal oscillator circuit
• 3V - 6V single power supply
• Built-in synchronized circuit for MSM80C86 and
MSM80C88 READY and RESET
• TTL compatible
• Built-in Schmitt trigger circuit (RES input)
• 18-pin DIP (MSM82C84A-5RS)
• 24-pin flat package (MSM82C84A-5GS)
FUNCTIONAL BLOCK DIAGRAM
-~
RES
0
RESET
Q
X1
OSC
X2
FIC
EFI
CSYNC
'2
S
Y
N
C
PClK
S
Y
N
C
lK
RDY1
AEN1
AEN2
c~
RDY2
ASYN
230
o
(F2)Q
~
READY
- - - - - - - - - - - - - - - - - - . I/O· MSM82C84A-5RS/GS •
PIN CONFIGURATION
18 lead Plastic DIP
24 lead PI astic F I at Pac kage
CSYNC
1
PClK
2
AEN1
3
•
VCC
X1
16
X2
RDY1
4
15
ASYNC
READY
5
14
EFI
RDY2
6
13
Fie
AEN2
7
12
OSC
ClK
8
11
RES
GND 9
10
RESET
10
24
PClK
2
23
X1
N·C
3
22
X2
AEN1
4
21
N'C
CSYNC
VCC
RDY1
5
ASYNC
READY
6
EFI
N·C
7
N'C
RDY2
8
Fie
9
OSC
AEN2
[I
N'C
N'C
ClK
RES
GND
RESET
(N·C not connected)
231
• I/O· MSM82C84A-5RS/GS • - - - - - - - - - - - - - - - - - ABSOLUTE MAXIMUM RATINGS
Parameter
Limits
Symbol
MSM82C84A-5RS
Supply Voltage
Unit
-0.5 - +7
VIN
-0.5 - V CC +0;5
V
VOUT
-0.5 - VCC +0.5
V
Storage Temperature
Tstg
Power Dissipation
Po
I
-55-+150
I
0.8
II
Conditions
V
VCC
Input Voltage
Output Voltage
IMSM82C84A-5GS
Respect to GND
°c
-
W
Ta = 25°C
0.7
I
OPERATING RANGES
Parameter
Symbol
Limits
Supply Voltage
VCC
3-6
V
Operating Temperatu re
TOp
-40 - +85
°c
Unit
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
MIN
TYP
MAX
Supply Voltage
VCC
4.5
5
5.5
V
Operating Temperature
TOp
-40
+25
+85
°c
"L" Level Input Voltage
VIL
-0.5
+0.8
V
VCC+ 0 .5
V
"H" Level Input Voltage (except RES)
2.2
VIH
"H" Level I nput Voltage (R ES)
0.6*VCC
DC CHARACTERISTICS
Parameter
Unit
(Vcc = 5V ± 10%, Ta = -40 - 85°C)
Symbol
MIN
MAX
Unit
Conditions
"L" Level Output Voltage (CLK)
VOL
-
0.4
V
IOL=4mA
"L" Level Output Voltage (OTHERS)
VOL
-
0.4
V
IOL
"H" Level Output Voltage (CLK)
VOH
VCC-OA
-
V
IOH
VOH
VCC-OA
V
IOH
VIHR
- VILR
0.2 * VCC
V
"H" Level Output Voltage (OTHERS)
RES Input Hysteresis
= 2.5mA
= -4mA
= -1mA
III
-1
+1
/lA
o
Input Current ( ASYNC )
ILIA
-100
+10
/lA
0 ~ Vin ~ VCC
Standby Supply Current
ICCS
+40
/lA
Operating Supply Current
ICC
10
mA
Input Capacitance
Cin
7
pF
Input Leak Current (EXCEPT ASYNC )
NOTE 1: X1 ~ VCC - 0.2V, X2 ~ O,2V
F/C ~ VCC - 0.2V, ASYNC = VCC or open
VIH ~ VCC - O.2V, VIL ;:;:;; O,2V
232
~ Vin ~ VCC
NOTE 1
f
= 15MHz, CL = OpF
f = 1 MHz
- - - - - - - - - - - - - - - - - - . I/O· MSM82C84A-5RS/GS •
AC CHARACTERISTICS
(VCC = 5V ± 10%, Ta = -40 - 85°C)
(1 )
Parameter
EFI "H" Pulse Width
Symbol
MIN
tEHEl
20
MAX
Unit
90%-90%
10%-10%
EFI "l" Pulse Width
tElEH
20
ns
EFI Cycle Time
tElEl
66
ns
Crystal Oscillator Frequency
Set Up Time of ROY1 or ROY2 to
ClK Falling Edge (Active)
6
tR1VCl
15
Conditions
ns
MHz
35
ns
ASYNC
= High
ASYNC
= low
Set Up Time of ROY1 or ROY2 to
ClK Rising Edge (Active)
tR1VCH
35
ns
Set Up Time of ROY1 or ROY2 to
ClK Falling Edge (Inactive)
tR1VCl
35
ns
Hold Time of ROY1 or ROY2 to
ClK Falling Edge
tClR1X
0
ns
Set Up Time of ASYNC to ClK
Falling Edge
tAYVCl
50
ns
Hold Time of ASYNC to ClK
Falling Edge
tClAYX
0
ns
Set Up Time of AEN1 (AEN2) to
ROY1 (ROY2) Rising Edge
tA1R1V
15
ns
Hold Time of AEN1 (AEN2) to
ClK Falling Edge
tClA1 X
0
ns
Set Up Time of CSYNC to EFI
Rising Edge
tYHEH
20
ns
Hold Time of CSYNC to EFI Rising
Edge
tEHYl
10
ns
CSYNC Pulse Width
tYHYl
2 x tElEl
ns
Set Up Time of RES to ClK Falling
Edge
tl1HCl
65
ns
Hold Time of RES to ClK Falling
Edge
tCLl1H
20
ns
Input Rising Edge Time
tlLlH
15
ns
Input Falling Edge Time
tlHll
15
ns
Output load
capacitance
ClK output
Cl = 100pF
Others 30pF
Note: Parameters where timing has not been indicated in the above table are measured at VL = 1.5V and VH = 1.5V
for both inputs and outputs.
233
• I/O· MSM82C84A-5RS/GS • - - - - - - - - - - - - - - - - - AC CHARACTER ISTICS
(VCC = 5V ±10%, Ta = -40 - 85°C)
(2)
Symbol
MIN
ClK Cycle Time
tClCl
200
ClK "H" Pulse Width
tCHCl
1
"3TClCl + 2
ns
ClK "l" Pulse Width
tClCH
2
3"TClCl -15
ns
Parameter
ClK R ising and Fall ing Edge
Times
MAX
Unit
tCH1CH2
10
tCl2Cl1
ns
PClK "H" Pulse W.idth
tpHPl
TClCl - 20
ns
PClK "l" Pulse Width
tplPH
TClCl - 20
ns
Time from READY Falling Edge
to ClK Falling Edge
tRYlCl
-8
ns
Time from READY Rising Edge
to ClK Rising Edge
tRYHCH
~3 TClCl -
Conditions
ns
1.0V-3.5V
Output load
capac itance
ns
15
ClK output
Cl = 100pF
Delay from ClK Falling Edge
to RESET Falling Edge
tCLIl
40
ns
Delay from ClK Falling Edge
to PClK Rising Edge
tClPH
22
ns
Delay from ClK Falling Edge
to PClK Falling Edge
tClPl
22
ns
Delay from OSC Falling Edge
to ClK Rising Edge
tOlCH
-5
22
ns
Delay from OSC Falling Edge
to ClK Falling Edge
tOlCl
2
35
ns
Output R ising Edge Time
(Except ClK)
tOlOH
15
ns
0.8V-2.2V
Output Falling Edge Time
(Except ClK)
tOHOl
15
ns
2.2V-0.8V
Others 30pF
Note: Parameters where timing has not been indicated in the above table are measured at Vl = 1.5V and VH = 1.5V
for both inputs and outputs.
234
- - - - - - - - - - - - - - - - - - . I/O· MSM82C84A-5RS/GS •
PIN DESCRIPTION
Pin symbol
Name
CSYNC
Clock
synchronization
singal
Inputl
output
Function
Input
Synchronizing signal for output of in-phase ClK signals when more
than one MSM82C84A-5 is used.
The internal counter is reset when this signal is at high level, and a
high level ClK output is generated. The internal counter is subseqently activated and a 33% duty ClK output is generated when
this signal is switched to low level.
When this signal is used, external synchronization of EFI is necessary.
When internal oscillator is used, it is necessary for this pin to be kept
to be low level.
PClK
Peripheral clock
output
Output
This peripheral circuit clock Signal is output in a 50% duty cycle at
a frequency half that of the clock signal.
AEN1
Address enable
signals
Input
The AEN1 signal enables ROY1, and the AEN2 signal enables ROY2.
The respective ROY inputs are activated when the level applied to
these pins is low.
Although two separate inputs are used in multi-master systems, only
the AEN which enables the ROY input to be used is to be switched
to low level in the case of not using multi-master systems.
Bus ready signals
Input
Completion of data bus reading and writing by the device connected
to the system data bus is indicated when one of these signals is
switched to high level.
The relevant ROY input is enables only when the corresponding AEN
is at low level.
READY
Ready output
Output
This signal is obtained by synchronizing the bus ready signal with
ClK.
This signal is output after guaranteeing the hold time for the CPU in
phase with the ROY input.
ClK
Clock output
Output
This signal is the clock used by the CPU and peripheral devices connected to the CPU system data bus. The output waveform is generated in a 33% duty cycle at a frequency 113 the oscillating frequency
of the crystal oscillator connected to the X1 and X2 pins, or at a
frequency 113 the E F I input frequency.
AEN2
ROY1
RDY2
RES
Reset in
Input
This low-level active input is used to generate a CPU reset signal.
Since a Schmitt trigger is included in the input circuit for this signal,
"power on resetting" can be achieved by connection of a simple RC
circuit.
RESET
Reset output
Output
This signal is obtained by ClK synchronization of the input signal
applied to RES and is output in opposite phase to the RES input.
This signal is appl ied to the CPU as the system reset signal.
F/C
Clock select signal
Input
This signal selects the fundamental signal for generation of the ClK
signal. The ClK is generated from crystal oscillator output when this
signal is at low level,' and from the EF I input signal when at high level.
EFI
External clock
signal
Input
The signal applied to this input pin generates the ClK signal when
F/C is at high level. The frequency of the input signal needs to be
three times greater than the desired ClK frequency.
X1, X2
Crystal oscillator
connecting pins
Input
Crystal oscillator connections.
The crystal oscillator frequency needs to be three times greater than
the desired ClK frequency.
OSC
Crystal resonator
output
Output
Crystal oscillator output. This output frequency is the same as the
oscillating frequency of the oscillator connected to the X1 and X2
pins. As long as a Xtal oscillator is connected to the X1 and X2 pins,
this output signal can be obtained independently even if F/C is set to
high level to enable the EFI input to be used for ClK generation
purposes.
235
• I/O· MSM82C84A-5RS/GS • - - - - - - - - - - - - - - - - - -
Name
, Pin symbol
ASYNC
Ready
synchronization
select signal
Input/
output
Input
Function
Signal for selection of the synchronization mode of the READY
signal generator circuit. When this signal is at low level, the READY
signal is generated by double synchronization. And When at high
level, the READY signal is generated by single synchronization.
This pin is equipped with internal pull-up resister.
VCC
+5V power supply
GND
GND
TIMING CHART
ClK • PClK • OSC waveforms
EFI
OSC
tClPH
RESET waveform
ClK
----.f"\L..------Jn-~_--J'l
Hl--_---Jr
+. . _______4_1=_-'1 ~CLllH
R E S - - - - - - - - - -....
rtllHCL
~
r
tcLil
RESE~~--------------------________________~/r----------------------------------------_j-+~1~-------------
236
- - - - - - - - - - - - - - - - - . I/O· MSM82C84A-5RS/GS •
READY
waveform
(ASYNC
= L)
ClK
RDY1-2 ---------4
~tA1R1V
AEN1-2------------~ I
ASYNC----------------~
READY---------------------~
tRYHCH
READY waveform (ASYNC = H)
tR1VCl
tR1VCl
ClK
ROY 1-2 --------------------IJ
tClA1X
AEN 1-2 --------------.1
tAYVCl
ASYNC-------------~
tRYHCH
READY--------------------~
237
• I/O' MSM82C84A-5RS/GS • - - - - - - - - - - - - - - - - OESCR IPTION OF OPERATION
Oscillator Circuit
The MSM82C84A-5 internal oscillator circuit can
be driven by connecting a crystal oscillator to the X1
and X2 pins.
The frequency of the crystal oscillator in this case
needs to be three times greater than the desired ClK
frequency.
And since oscillator circuit output (the same output as for the crystal resonator frequency) appears at
the OSC pin, independent use of this output is also
possible.
(1)
I
1[1
I
Recommended Oscillator Circuit
(2)
Clock Generator Circuit
This circuit generates two clock outputs-ClK
obtained by dividing the input external clock or crystal
oscillator circuit output by three, and PClK obtained
by halving ClK. ClK and PClK are generated from the
external clock applied to the EFI pin when F/C is at
high level, and are generated from the crystal oscillator
circuit when at low level.
Reset Circuit
Since a Schmitt trigger circuit is used in the RES
input, the MSM82C84A-5 can be reset by "power on"
by connection to a simple RC circuit. If the 80C86 or
80C88 device is used as the CPU in this case, it is necessary to keep the RES input at low level for at least
So Ils after VCC reaches the 4.5V level.
(3)
Ready Circuit
The READY signal generator circuit can be set to
synchronization mode by ASYNC.
(j)
When ASYNC is at low level
The ROY input is output as the READY signal by
double synchronization.
The high-level ROY input is synchronized once by
the rising edge of the ClK of the first stage flipflop (F1 in the circuit diagram), and then synchronized again by the falling edge of the ClK of the
next stage flip-flop (F2 in the circuit diagram),
resulting in output of a high-level READY output
signal (see diagram below).
The low-level ROY input is synchronized directly
by the falling·edge of the ClK of the next stage
flip-flop, resulting in output of a low-level READY
output signal (see diagram below)'
(4)
Crystal oscillator
1C'l rJi
r-----4-J-+)-;
C2
T
X1
OSCt----
MSM82C84A-5
--~---fX2
When input frequency is 6 to 15 MHz.
C1
= C2 = 33 pF
ClK~
ROY
1\ c\ 1\
I
READY
238
I
•
I
I
I
I
I
,
I
f
+
,
I
I
I
~
- - - - - - - - - - - - - - - - - - . I/O· MSM82C84A-5RS/GS •
(ii)
synchronized by the falling edge of the ClK of the
next stage flip-flop, resulting in output of respective low-level and high-level READY output signals
(see diagram below!'
When ASYNC is at high level
The RDY input is output as the READY signal by
single synchronization.
Both low-level and high-level
CLK=J\
I
:\
I
I
I
I
,
I
I
(
9
READY
~\
J\
I
RDY
RDY inputs are
J\
C
,
I
I
,J
I
Il....--
I
~
r
~
EXAMPLE OF USE (CSYNC)
switched to low level, ClK is output from the next
input clock rising edge, and is divided by 3.
If CSYNC has not been synchronized with the
input clock, use the following circuit to achieve the
required synchronization
The ?2C84A-5 1/3 frequency divider counter is
unsettled when the power is switched on. Therefore, the
CSYNC pin has been included to synchronize ClK with
another signal. When CSYNC is at high level, both ClK
and PClK are high-level outputs. If CSYNC is then
MSM82C84A-5
External
synchroniz i."
signal
External
clock signa
(EFI)
D
~rt>
1
CKt
a
D
CSYNC
Q
~ CK~
....-- EFI
Cl
ClK
When an external clock EFI is used as the clock source
MSM82C84A-5
External
rf'-----~~-_;:;~
synchronizin
D
Ot----fD
signal
CKt
Q~--~
CK.
SC
F/
ClKt------ClK
When the crystal oscillator is used as the clock source
239
OKI
semiconductor
MSM82C88AS/GS
BUS CONTROLLER
GENERAL DESCRIPTION
The MSM82C88 is a bus controller for MSM80C86 and MSM80C88 CPU. Based on silicon gate CMOS technology, low-power 16-bit microprocessor system is realized.
The MSM82C88 generates commands control timing signals on reception of status signals from CPU.
FEATURES
• Silicon gate CMOS technology for low power consumption
• 3 to 6V wide voltage range and single power supply
• -40 to 85°C wide guaranteed operating temperature
range
•
•
•
•
•
Advanced write control output
Three-state command output driver
System bus mode & I/O bus mode
20-pin DIP (MSM82C88AS)
24-pin flat package (MSM82C88GS)
CIRCUIT CONFIGURATION
STATUS
INPUT
50
MRDC
~
MWTC
COMMAND
SIGNAL
GENERATOR
82
AMWC
10RC
COMMAND
OUTPUT
10WC
AIOWC
INTA
ClK
CONTROL
INPUT
AEN
CEN
lOB
CONTROL
CONTROl..-------4 SIGNAL
lOGIC
GENERATOR
VCC (+5V)
240
GND (OV)
DTiR"
DEN
MCE/PDEN
ALE
CONTROL
OUTPUT
- - - - - - - - - - - - - - - - - - - . I/O· MSM82C88AS/GS •
PIN CONFIGURATION
MSM82C88AS (top view)
20-lead DIP
lOB
VCC
ClK
Sa
~
S;
fJ
MCE/PDEN
DT/R
ALE
DEN
AEN
CEN
MRDC
INTA
AMWC
10RC
MWTC
AIOWC
GND
10WC
MSM82C88GS (top view)
24-lead plastic flat package
24
VCC
23
S;;
3
22
NC
4
21
~
DT/R
5
20
MCE/PDEN
ALE
6
19
DEN
CEN
INTA
lOB
ClK
2
NC
~
0
AEN
7
18
MRDC
8
17
AMWC
9
16
10RC
NC
10
15
NC
MWTC
11
14
AIOWC
GND
12
13
10WC
Note: NC pin must not be connected.
241
• I/O· MSM82C88AS/GS • - - - - - - - - - - - - - - - - - - ABSOLUTE MAXIMUM RATINGS
limits
Parameter
Symbol
Conditions
MSM82C88AS
Power Supply Voltage
VCC
Input Voltage
VIN
Output Voltage
Storage Temperature
Power Dissipation
With respect
to GND
VOUT
Ta
PD
= 25°C
Unit
-0.5 - +7
V
-0.5 - V CC +0.5
V
-0.5 - VCC +0.5
V
-55 - 150
°c
-
Tstg
I MSM82C88GS
I
1.1
0.7
W
OPERATING RANGES
Unit
Symbol
Limits
Power Supply Voltage
VCC
3-6
V
Operating Temperature
TOp
-40 - 85
°c
Parameter
RECOMMENDED OPERATING CONDITIONS
Unit
Symbol
Min.
Typ.
Max.
Power Supply Voltage
VCC
4.5
5
5.5
V
Operating Temperature
TOp
-40
+25
+85
°c
"l" Input Voltage
VIL1
-0.3
-
+0.8
V
-
VCC +0.3
V
Parameter
VIH1
3.0
"l" Input Voltage
VIl2
-0.3
-
+0.8
V
"H" Input Voltage
VIH2
2.2
-
VCC +0.3
V
"H" Input Voltage
Note: VIL1 and VIH1 are input voltages for ClK, 5;;, 57, andS";.
VIl2 and VIH2 are input voltages for AEN, CEN, and lOB.
242
- - - - - - - - - - - - - - - - - - - : - - . I/O· MSM82C88AS/GS •
DC CHARACTERISTICS
(Vcc = 4.5V to 5.5V, Ta
= -40°C
to +85°C)
Parameter
Symbol
Conditions
Command output
IOL
"L" Output Voltage
VOL
=
12mA
Control output
IOL
= 8mA
Command output
IOH
"H" Output Voltage
VOH
= -5mA
Control output
IOH
= -1mA
Min.
Typ.
Max.
Unit
-
-
0.45
V
-
-
0.45
V
3.7
-
-
V
3.7
-
-
V
Input Leak Current
'll
0:5. V,N:5. VCC
-10
-
10
IJA
Output Leak Current
'LO
0:5. VOUT:5. VCC
-10
-
10
IJA
Status Input Current
'llS
0:5. V,N:5. VCC
-100
-
10
/lA
Operation Power Supply Current
ICCO
CL = OpF
tc LC L = 200ns
-
-
10
mA
Standby Power Supply Current
ICCS
Note 3
-
-
100
IJA
Remarks
Note 1
Note 2
Note 1. This input leak current is the leak current on input pins except status inputs (50 ,S;, and S;).
Note 2. The status input leak current is the leak current at the status inputs (So, S; , and S; ).
Note 3. The measuring conditions for the standby power supply current include the ~, S;, and S; status inputs being
at VCC potential, and the other inputs being at VCC or GND. All output pins are left open.
AC CHARACTERISTICS
(VCC = 4.5V to 5.5V, Ta
= -40°C
to +85°C)
Timing conditions
Parameter
Symbol
Min.
Max.
Unit
Clock Cycle
tCLCL
200
-
nS
Clock Low Time
tCLCH
118
-
nS
Clock High Time
tCHCL
65
-
nS
Status Active Setup Time
tSVCH
35
-
nS
Status Inactive Hold Time
tCHSV
10
-
nS
Status Inactive Setup Time
tSHCL
35
-
nS
Status Active Hold Time
tCLSH
10
-
nS
243
• I/O· MSM82C88AS/GS • - - - - - - - - - - - - - - - - - Timing response
Parameter
Symbol
Min.
Max.
Unit
Test Circuit
Delay from CLK Leading Edge to DEN,
PDEN Active
tCVNV
5
45
nS
4
Delay from CLK Trailing Edge to DEN,
PDEN Inactive
tCVNX
5
:
45
nS
4
Delay from eLK Trailing to ALE
Active
tCLLH
-
35
nS
4
Delay from CLK Trailin!l Edge to
MCE Active
tCLMCH
-
35
nS
4
Delay from Status Input Falling Edge
to ALE Active
tSVLH
-
35
nS
4
Delay from Status Input Falling Edge
to MCE Active
tSVMCH
-
35
nS
4
Delay from CLK Leading Edge to
ALE Inactive
tCHLL
4
35
nS
4
Delay from CLK Trailing Edge to
Command Output Active
tCLML
5
45
nS
3
Delay from CLK Trailing Edge to
Command Output Inactive
tCLMH
5
45
nS
.3
Delay from CLK Leading Edge to
DT/R Active
tCHDTL
-
50
nS
4
Delay from CLK Leading Edge to
DT/R Inactive
tCHDTH
-
35
nS
4
Delay from AEN Leading Edge to
Command Enable
tAELCH
-
45
nS
2
Delay from AEN Trailing Edge to
Command Disable
tAEHCZ
-
40
nS
1
Delay from AEN Leading Edge to
Command Output Active
tAELCV
90
250
nS
3
Delay from AEN to DEN
tAEVNV
-
35
nS
4
Delay from CEN to DEN, PDEN
tCEVNV
-
35
nS
4
Delay from CEN to Command Output
tCELRH
-
Output Rise Time
tOLOH
-
Output Fall Time
tOHOL
-
Remarks
nS
3
20
nS
3,4
From O.BV to 2.2V
12
nS
3,4
From 2.2V toO.BV
tCLML +20
Note: AC timing measurements are made at 1.5V for both logic "1" and "0".
Input rise and fall times are
5 ± 2 nS between O.BV and 2.2V for AEN, CEN and lOB.
S ± 2 nS between O.SV and 3.0V for SO, si, 52 and CLI<:.
Test Circuit
v
R
Out
244
---~t------Test
Point
Test Circuit
V(V)
R(U)
1
1.5
1BO
50
2
1.5
300
150
C(PF)
3
2.74
190
150
4
3.34
360
BO
- , . . - - - - - - - - - - - - - - - - - - - . I/O' MSM82C88AS/GS •
TIME CHARTS
T4
State
CLK
T1
T2
tCLCL
tCLCH
--.J'" '----'~ h ~
tc HSV_
s"s"s;;
I-
-
~
tCHCL
,.....tSVCHtc SH_
,
AD"DR
ADDR ESS/DA T A
-~
'-wfr'
j-tCHLL
Ir@
ALE
-
tCLMHMRDC, IORC, INTA
AMWC, AIOWC
If
J
-,
tCLML-
i-tCLML
1\
J
V
\
j
tCVNV-
I-
,
1\
-
~
1\
I-tCVNX
It
.,~
DEN (WRITE)
J
-PDEN (WR ITE)
I--tCVNV
tCVNX_
I--
V-1\
DTH--
-
r-
~
---
MCE
~
-tSHCL
DA~:!J1L1DG)
VALID
tCLLH- I-
-r
Y'
If
J:
tCLMCH--
\
I@
~
tCHDTL
-
tCHDTH_
'{
FtCVNX
:--tSVMCH
Note 1. The ADDRESS/DATA bus signal is shown for reference purposes.
Note 2. The ALE and MCE leading edges are synchronized with the falling edge of CLK or status going active,
whichever occurs last.
Note 3. All timing measurements are made at 1.5V unless specified otherwise.
245
• I/O· MSM82C88AS/GS •
----------.---~-------
DEN, PDEN Timing
\1(
CEN
r\
'II
J~
tAEVNV
-
~I
I\.
DEN
\V
J\
tCEVNV
\V
J\
AEN Timing
tAELCV
1.5V
All command outputs
when in system bus
mode, MRDC, MWTC,
and AMWC when in
I/O bus mode.
--iAELCIH'__
1.5V
~~______________~__L-VOH
CEN
Note: To control the command and control signal outputs, CEN must be switched to low level before T 2
246
- - - - - - - - - - - - - - - - - - - . I/O· MSM82C88AS/GS •
PIN DESCRIPTION
Input/output
Function
Input
These pins are input pins for status signals (so, s., and S2 ), output .from
the CPU (MSM80C86, 80C88). The MSM82C88 generates commands and
control signals after decoding these status signals. And since these pins are
connected to internal pull-up resistor, they are set to high level when the
ClK
Input
This pin is input pin for clock signals output from the clock generator
(MSM82C84A). The timing of all MSM82C88 output signals is controlled by
this clock signal.
ALE
Output
Strobe signal for latch ing output address from the CPU to address latch.
Address latching occurs on the trailing edge of ALE.
DEN
Output
Control signal for setting the data bus transceiver to data enable. The local
bus or system bus transceiver is enabled when this signal is high.
DEN is switched to low when the CEN input is low.
DT/R
Output
Control of the direction of data flow in the data bus transceiver. When the
CPU is switched to write mode, this signal is high, and when switched to
read mode, this signal is low.
Pin Name
so,s. '
S2
CPU status output is at high impedance.
-AEN
Input
Address enable signal.
• lOB = l (SYSTEM BUS MODE)
When the AEN input is switched to high level, all command outputs are
switched to high impedance status .
• lOB = H (I/O BUS MODE)
When the AEN input is switched to high level, only the MRDC, MWTC,
and AMWC command outputs are switched to high impedance status.
When AEN is switched from high to low level, high impedance command
outputs are not switched to active status (low level) for at least 90 'nS,
irrespective of the lOB input status.
CEN
Input
Command enable signal.
All command outputs, DEN and PDEN outputs are switched to inactive
status when a low level input is applied to CEN. All command outputs, DEN
and PDEN outputs are switched to active status when a high level input is
applied to CEN.
lOB
Input
I/O bus mode signal.
The MSM82C88 is switched to I/O bus mode when a high level input is
applied to lOB, and to system bus mode when a low level input is applied.
10WC
3-state
output
This pin is active-low, and three-state output. This signal is for writing data
into the I/O device.
AIOWC
3-state
output
This pin is active-low and three-state output. Although this signal is also
used for writing into I/O devices like the I/O write command (lOWC), it is
made active one clock earlier than 10WC.
10RC
3-state
output
This pin is active-low and three-state output. This signal is for reading data
from I/O devices.
MWTC
3-state
output
This pin is active-low and three-state output. This signal is for writing data
into memory.
AMWC
3-state
output
This pin is active-low and three-state output. Although this signal is also
used for writing into memory like the memory write command (MWTC),
it is made active one cycle earlier than MWTC.
MRDC
3-state
output
This pin is ac~ive-Iow and three-state output. This signal i,s for reading data
from memory.
INTA
3-state
output
This pin is active-low and three-state output. This signal informs the interrupt controller that the interrupt has been accepted, and then requests
output of a vector address onto the data bus.
---
247
• I/O· MSM82C88AS/GS •
Pin Name
Input/output
Function
MCE/PDEN
Output
This pin has two functions.
MCE (lOB = Low) master cascade enable function.
This is active-high signal and used to enable a slave PIC (priority interrupt
controller) to read the cascade address output on the data bus by the master
PIC during an interrupt sequence.
PDEN (lOB = High) peripheral data enable function.
This is active-low signal and used to enable the data bus transceiver on the
I/O bus.
I
(I
FUNCTION
Command Logic
The command output is decided by decoding
status signals (~. ~ • S; ) output from the CPU.
These status signals have the following meanings.
-S2 -SI 50
CPU status
Command
output
INTA
0
0
0
0
0
Interrupt acknowledge
1
I/O read
10RC
0
1
0
I/O write
10WC.AIOWC
-
0
1
1
Halt
1
0
Instruction fetch
1
0
0
1
Memory read
MRDC
1
1
0
Memory write
MWTC.AMWC
1
1
1
Passive
MRDC
-
I/O Bus Mode (lOB = High)
When an I/O access status signal is received from
the CPU in I/O bus mode. one of the I/O commands
(IORC. 10WC. AIOWC. INTA) corresponding to the
status signal becomes active irrespective of the AEN
status. At the same ,time. the PDEN and DT/R outputs
which control the data bus transceiver are generated.
As in system bus mode. the memory commands
(MRDC. MWTC. and AMWC) are not switched to low
level for at least 90 ns after AEN is SWitched to low
leveJ.
System Bus Mode (lOB = Low)
When the bus is usable. MSM82C88 is enabled by
the AEN signal from the bus arbiter. Consequently. no
command output becomes active unless the AEN signal
becomes low. Also note that there is a delay of at least
90 ns befor~ any command output becomes active
afte! the AEN signal is switched to low level.
System bus mode is used when more than one CPU
is connected to a single bus. and the bus I/O. memory.
etc. are used in common.
Command Outputs
The advanced write commands (AIOWC and
AMWC) become active one cycle earlier than normal
248
write commands (IOWC and MWTC). This prevents the
CPU from being switched to an additional period of
wait status.
INTA (interrupt acknowledge) is output during the
interrupt acknowledge cycle in the same way as
MRDC in the read cycle. The purpose of this signal is
to inform the device which has requested the interrupt
that the interrupt has been accepted. and requests a
vector address output on the data bus.
MRDC
Memory read command
Memory write command
I/O read command
I/O write command
AMWC
Advanced memory write command
AIOWC - Advanced I/O write command
Interrupt acknowledge
Control Output
The control output signals are DEN (Data Enable),
DTi'R (Transmit/Receive). and MCE/PDEN (Master
Cascade Enable/Peripheral Data Enable).
DEN signal enables the local bus or system bus.
when it is high.
The DT/R signal determines the direction of the
data on the local bus or system bus.
The function of the MCE/PDEN pin is switched
according to lOB. The PDEN function is selected in I/O
bus mode (lOB = hight to provide the I/O or peripheral/
system bus data enable signal. When the MCE function
is selected in system bus mode (lOB = low). the MCE
signal is active (high) level at an interrupt acknowledge
status.
The MCE signal is used when a master and slave
interrupt controller exists 'in the system.
ALE (Address Latch Enable)
ALE is generated in each machine cycle to latch
the current address to the address latch.
CEN (Command Enable)
This signal is used to enable command outputs. All
command outputs become inactive if a low level input is
applied to the CEN pin.
PERIPHERALS
OKI
semiconductor
MSM5832RS
REAL TIME CLOCK/CALENDER
GENERAL DESCRIPTION
I
II
The MSM5832RS is a metal-gate CMOS Real Time Clock/Calendar for use in bus-oriented microprocessor
applications. The on-chip 32.768Hz crystal controlled oscillator time base is divided to provide addressable 4-bit
I/O data of SECONDS, MINUTES, HOURS, DAY-OF-WEEK, DATE, MONTH, and YEAR. Data access is
controlled by 4-bit address, chip select read, write and hold inputs. Other functions include 12H/24H format
selection, leap year identification and manual ±30 second correction.
The MS5832RS normally operates from a 5V ±5% supply. Battery backup operation down to 2.2V allows
continuation of time keeping when main power is off. One test input facilitates rapid testing of the time keeping
operations. The MS5832 is offered in an 18-lead dual-in-lire plastic (RS suffix) package.
FEATURES
·7 Function - SECOND, MINUTE, HOUR, DAY,
DAY-OF-WEEK, MONTH, YEAR
• Automcttic leap year calendar
• 12 or 24 hou r format
• ±30 second error COrrection
• 4-BIT DATA BUS
• 4-BIT ADDRESS
• READ, WRITE, HOLD, and CHIP SELECT inputs
FUNCTIONAL BLOCK DIAGRAM
250
• Interrupt signal outputs - 1024, 1, 1/60, 1/3600Hz
• 32.768kHz crystal controlled operation
• Single 5V power supply
• Back-up battery operation to VDD = 2.2V
• Low Power Dissipation
90 JJ,W Max. at VDD = 3V
2.5 mW Max. at VDD = 5V
• 18 pin plastic DIP package
- - - - - - - - - - - - - - - - - . PERIPHERALS· MSM5832RS •
PIN CONFIGURATION
AO to A3
WRITE
REAO
HOLO
CS
00 to 03
TEST
±30 AOJ
XT&XT
VOO
GNO
VOO
Address Inputs
Write Enable
Read Enable
'Count Hold
Chip Select
Oata Input Output
Test Input
±30 Second Correction Input
xtal oscillator connections
+5V Supply
Ground
HOLO
WRITE
Xl-
REAO
XT
Ao
±30 AOJ
AI
TEST
Al
GNO
A3
03
CS
O2
00
01
a
REGISTER TABLE
Oata Input/Output
Address
Input
Register
Name
00
01
O2
03
S1
*
*
*
*
0
S10
*
*
*
0
0
M11
*
*
*
1
0
0
M110
*
*
*
0
1
0
H1
*
*
*
Ao
AI
A2
A3
0
0
0
0
1
0
0
0
1
1
0
Oata
Limit
0~9
0~5
*
(2)
S1 or S1 0 are reset to zero irrespective
of input data 00-03 when write
instruction is executed with address
selection.
0~9
0~5
*
0~9
b(,
1
0
1
0
H10
*
*
t
0
1
1
0
W
*
*
*
1
1
1
0
01
*
*
*
0
0
0
1
010
*
*
t
1
0
0
1
M01
*
*
*
0
1
0
1
M010
*
1
'1
0
1
Y1
*
*
*
*
0-9
0
0
1
1
Y10
*
*
*
*
0-9
t
0~2
(1)
Remarks
02
= "1 "
02
02
= "1" for 29 days in month 2
= "0" for 28 days in month 2
for PM 03
= "1 "
for
24 hour format
02 = "0" for AM 03 = "0" for
12 hour format
0~6
*
0-9
0-3
*
(2)
0-9
0-1
*data valid as "0" or "1".
Blank does not exist (unrecognized during a write and held at "0" during a read)
tdata bits used for AM/PM, 12/24 HOUR and leap year.
If 02 previously set to "1", upon completion of month 2 day 29, 02 will be internally reset to "0".
Table 1
251
• PERIPHERALS· MSM5832RS . - - - - - - - - - - - - - - - - OSCILLATOR FREQUENCY DEVIATIONS
Frequency Deviation vs Temperature
=
(ppm)
Vee=
25°e
3V: T
=
1000000.0 p.S
Vee=
5V: T
=
999999.7 p.S
Ta
(0 ppm)
j
+6.0
(0 ppm)
.... ~
J,.V-/
+4.0
~,
I..--?"
+2.0
~
//
-20
V = 3V
V
V = 5V
V
gt'
V
0/
/"1
+25
+40
+80
+60
Ta(Oe)
-4.0
V
-6.0
Figure 1
Frequency Deviation vs Supply Voltage
(ppm)
+3.0
Sample #1 : T = 1000000.8 J.l.S
(0 ppm)
I--
I"
Sample
\
\
II'.
#2 : T
= 1000000.2 J.l.S
(0 ppm)
+2.0
~
~ ~
~ 2-....
~~
1'...."
+1.0
"i~
~~
.~
2.0
2.5
3.0
3.5
4.0
4.5
6.5
6.0
5.0 ... 5.5
7.0
Vee(V)
\.~
,,~
~~
-1.0
1",,-
~~
,"'-'t
-2.0
Sample
#1
Sample
#2
I
Figure 2
252
- - - - - - - - - - - - - - - - - . PERIPHERALS· MSM5832RS •
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
~
Unit
Supply voltage
VOO
-0.3
7.0
V
Input voltage
VI
-0.3 ~ VCC + 0.3
V
Data I/O voltage
VO
-0.3 ~ VCC + 0.3
V
Storage Temperature
Tstg
-55
°c
~
150
OPERATING CONDITIONS
Symbol
Min.
Typ.
Max.
Unit
Conditions
Supply Voltage
VOO
4.75
5
5.25
V
5V±5%
Standby Supply Voltage
VOH
2.2
-
7
V
VIH
3.6
-
VOO
V
VIL
-0.3
-
0.8
V
Parameter
I nput Signal Level
Crystal Oscillator Freq.
f(XT)
-
Operating Temperature
TOp
-30
-
kHz
-
+85
°c
32.768
VOO = 5V ± 5%
Respect to GNO
DC CHARACTERISTICS
(V cc = 5V ±5%; T A = -30 to +85° C)
Parameter
Min.
Typ.
Max.
Unit
IIH
10
25
50
tiL
-1
-
1
IJ.A
IJ.A
Data I/O Leakage
Current
ILO
-1
-
1
fJA
Output Low Voltage
VOL
-
-
0.4
V
Output Low Current
10L
1.6
-
-
mA
IJ.A
IJ.A
Input Current (I)
Operating Supply Current
(1)
Symbol
XT,
100S
-
15
30
100
-
100
500
Conditions
VIN =5V
VIN = OV
VI/O = 0 to VOO
CS = "0"
10 = 1.6 mA, CS = "1",
READ = "1"
Vo = O.4V, CS = "1",
READ = "1"
VCC = 3V, Ta = 25°C·
VCC = 5V, Ta = 25°C
XT and Do - 0 3 excluded.
253
• PERIPHERALS· MSM5832RS . - - - - - . . . . . . , . - - - - - - - - - - - SWITCHING CHARACTERISTICS
(1) READ mode
(Vcc = 5V ± 5%; Ta = 25°C)
Symbol
Min.
HOLD Set-up Time
tHS
150
HOLD Hold Time
tHH
0
HOLD Pulse Width
tHW
READ Hold Time
tRH
READ Access Time
tRA
Parameter
Typ.
Max.
Unit
J.LS
/J.S
1
SEC
6
J.LS
0
J.LS
READ CYCLE
HOLD
READ
Ao-A,
-----+-'
Do-D,
(DATA O..;;.U...;"T):"'-_~::"-+--fL4
HIGH IMPEDANCE
Figure 3 Read Cycle
Notes: 1. A Read occurs during the overlap of a high CS and a high READ.
2. Output Load: 1 TTL Gate, CL = 50 pf and RL = 4.7 k~l
3. CS may be a permanent "1", or may be coincident with HOLD pulse.
254
- - - - - - - - - - - - - - - - - . PERIPHERALS· MSM5832RS •
(2) WRITE mode
(Vee = 5V ± 5%;Ta = 25°e)
Parameter
Symbol
Min.
HOLD Set-up Time
tHS
150
HOLD Hold Time
tHH
0
HOLD Pulse Width
tHW
Typ.
Max.
Unit
JlS
JlS
1
SEe
ADDRESS Pulse Width
tAW
1.7
JlS
OATA Pulse Width
tow
1.7
JlS
DATA Set-up Time
tos
0.5
JlS
OAT A Hold Time
tOH
0.2
JlS
WRITE Pulse Width
tww
1.0
JlS
tHW
50%
HOLD
tHH
50%
A.-A,
P~..;.:fA
50%
IN)
J
WRITE
tww
~
Figure 4 Write Cycle
Notes:l. A WRITE occurs during the overlap of a high es, a high HOLD and a high WRITE.
2. es may be permanent "1", or may be coincident with HOLD pulse.
255
• PERIPHERALS· MSM5832RS . - - - - - - - - - - - - - - - - PIN DESCRIPTION
Pin No.
Description
Power supply pin. Application circuits for power supply are described in
Figure 9.
2
Data write pin. Data write cycle is described in Figure 4.
3
Data read pin. Data read cycle is described in Figure 3.
4 '" 7
8
Address input pins used to select internal counters for read/write operations.
The address is specified by 4-bit binary code as shown in Table 1.
Chip slect pin which is required to interface with the external circuit. HOLD,
WRITE, READ, ±30ADJ, TEST, Do '" Ds and Ao '" As pins are activated if
CS is set at H level, while all of these pins are disabled if CS is set at L level.
As shown in Figure 8, CS can be used to detect system power failure by connecting system power (+5V) to CS, so that when system power is on, all inputs and
outputs will be enabled, and when system power is off, all inputs and outputs
will be disabled. The threshold voltage of CS is higher than all other inputs to
ensure correct operation of this function.
Data input/output pins (bidirectional bus).
As shown in Figure 5, external pull-up registers of 4.7
or higher are required
by the open-drain NMOS output. Ds is the MSB, while Do is the LSB
kn
+5V
9°0
I
I
I
I
R
I
I
I
I
I
+5V
DO,
R
Di,
c.S.
MSM5832RS
Figure 5
256
- - - - - - - - - - - - - - - - - . PERIPHERALS· MSM5832RS •
Name
Pin No.
Description
GND
13
Ground pin.
TEST
14
Test pin. Normally this pin should be left open or should be set at ground level.
With es at Vce, pulses to Vee on the TEST input will directly clock the SI ,
Milo, W, Dl and Yl counters, depending on which counter is addressed (Wand
Dl are selected by Dl address in,this mode only). Roll-over to next counter is
enabled in this mode.
±30ADJ
15
This pin is used to adjust the time within the exteut of ±30 seconds. If this pin is
set at H level when the digits of seconds are 0 ..... 29, the digits of seconds are
cleared to O. If this pin is set at H level when the digits of seconds are 30 ..... 59,
the digits of second will be cleared to 0 and the digits of minutes will be added
by + 1. To enable this function, 31 .25 ms Or more width's pulse should be input
to this pin.
XT
16
Oscillator pin. 32.768 KHZ crystal, capacitor and trima condensor for frequency
adjustment are to be connected to these pins. See Figure 6. As for oscillator
frequency deviation, refer to Figure 1 and Figure 2.
If an extern~1 clock is to be used for MSM5832RS's oscillation source, the external
clock is to be input to XT and )n' should be left open.
17
XT
C
GND or
1
\
_
-
~'tal
.....
~
VDD~~
:
C2
TXT
~
\..
---
RS
-"./V\rMSM5832RS
Figure 6
HOLD
18
Switching this input to Vee inhibits the internal 1 Hz clock to the S1 counter.
After the specified HOLD set-up time (150 JLS), all counters will be in a static
state, thus allowing error-free read or write operations. So long as the HOLD pulse
width is less than 1 second, accuracy of the real time will be undisturbed. Pulldown to GND is provided by an internal resistor.
257
• PERIPHERALS· MSM5832RS . - - - - - - - - - - - - - - - - REFERENCE SIGNAL OUTPUT PIN
Condition
Output
Reference Frequency
Pulse Width
HOLD =
L
Do (1)
READ =
H
01
1 Hz
122.1
=
H
O2
1/60 Hz
122.1
Ao - A3 = H
03
1/3600 Hz
CS
(1)
1024 Hz
duty 50%
JJS
JJS
122.1 JJS
1024 Hz signal at Do not dependent on HOLD input level.
TYPICAL APPLICATION
+5V
8255 PP1
MSM5832RS
MICROCOMPUTER INTERRUPT
r - t - - - - - - f _ 122p.S pulse each second
PAl t----iI---4~~DI
(Ao - A3 and READ = VCC)
32.768kHz
5.35pf
MICROCOMPUTER
SYSTEM BUS
20pf
PB o
PBI
CS
+5V
10K
PB 2
TEST
GND
PC s
t-----1I---i~---1lvvR I TE
*30 ADJ
*30 sec Adjust
Figure 7
258
220n
V CC t--..............,..f+--vV\l--
+12V
+5V
- - - - - - - - - - - - - - - - - . PERIPHERALS· MSM5832RS •
TYPICAL APPLICATION - POWER SUPPLY CIRCUIT
C
.+5V
RL
-=
lOOn
i
~:
-
GND
MSM5832RS
-
1.5 X 2 = 3V
Dry Cells
VCE(sat) = O.lV
Ripple
Operating: 20mV p _ p
Battery Backup: OmV
+5V
4.7 J.1.f
51K
10K
a
VCC
(1: l
GN D
MSM5832RS
1.2 X 3 = 3.6V
Ni-Cd
FigureS
259
OKI
semiconductor
MSM58321RS
REAL TIME CLOCK/CALENDAR
GENERAL DESCRIPTION
The MSM58321 RS is a metal gate CMOS Real Time Clock/Calendar with a battery backup function for use in
bus-oriented microprocessor applications.
The 4-bit bidirectional bus line method is used for the data I/O circuit; the clock is set, corrected, or read by
accessing the memory.
The time is read with 4-bit DATA I/O, ADDRESS WRITE, READ, and "MJSV; it is written with 4-bit DATA
I/O, ADDRESS WRITE, WRITE, and ~.
FEATURES
·7 Function-Second, Minute, Hour, Day, Day-of-Week,
Month, Year
• Automatic leap year of calender
• 12/24 hour format
• Frequency divider 5-poststage reset
• Busy circuit reset
• Reference signal output
FUNCTIONAL BLOCK DIAGRAM
READ
260
• 32.768KHz crystal controlled operation
• Single 5V power supply
• Bock-up battery operation to VCC = 2.2V
• Low power dissipation
90/N'J max. at VCC = 3V
2.5mW max. at VCC = 5V
• 16 pin plastic DIP packqge
- - - - - - - - - - - - - - - - - . PERIPHERALS· MSM58321 RS •
PIN CONFIGURATION
CS 2
VDD
WRITE
XT
READ
XT
Do
CS 1
01
TEST
O2
STOP
03
BUSY
GND
ADDRESS WRITE
[I
REGISTER TABLE
Data input/
Address input
Do
(Ao)
0,
(A,)
o
0,
(A,)
0,
(A,)
0
0
Register
output
Name
Count value
Remarks
0-1 or 0-2
02 = 1 specifies PM,D2 - 0 speelfies AM, 03 = 1 specifies 24·hour timer, and
03 = 0 specifies 12-hour timer.
When 03 = 1 is written, the 02 bit is reset inside the IC.
S,
S,o
o
.
o
0
W
0,
o
A
0
C
0
0'0
. 000
The 02 and 03 bits in 010 are used to saleet a leap year.
Gregorian calendar
Showa
0
3
YIO
A selector to reset 5 poststages in the 1/2" frequency divider and the BUSY
circuit. They are reset when this code is latched with ADDRESS LATCH
and the WR ITE input goes to 1 .
o
A selector to obtain reference signal output. Reference signals are output to
E-F .0/1
DO - 03 when this code is latched with ADDRESS LATCH and READ input
goes to 1.
Notes: (1) There are no bits in blank fields for data input/output. 0 signals are output by reading and data is not stored by writing because there are no bits.
(2) The bit with marked 0 is usad to seleet the 12/24-hour timer and the bits marked 0 are usad to select a leap year. These three bits can be read or
written.
(3)
When signals are input to bus lines DO - 03 and ADDRESS WRITE goes to 1 for acldress input, ADDRESS information is latched with ADDRESS LATCH.
261
• PERIPHERALS· MSM58321RS . - - - - - - - - - - - - - - - ABSOLUTE MAXIMUM RATINGS
Symbol
Condition
Rating
VDD
Ta = 25°C
-0.3 - 7
Input voltage
V,
Ta = 25°C
GND-0.3VDD + 0.3
Output voltage
Vo
Ta=25°C
GND-0.3VDD + 0.3
Parameter
Power voltage
Storage temperature
Tstg
-
Unit
V
V
V
-55 - +150
°c
Rating
Unit
OPERATING CONDITIONS
Parameter
Symbol
Condition
Power voltage
VDD
-
4.5 -7
V
Date hold voltage
VDH
-
2.2 -7
V
Crystal frequency
f(XT)
-
Operating temperature
Top
-
kHz
32.768
°c
-30 - +85
Note: The data hold voltage guarantees the clock operations, though it does not guarantee operations outside the
IC and data input/output.
DC CHARACTERISTICS
(VDD = 5 V ±5%, Ta = -30 - +85°C)
Parameter
H input voltage
Symbol
Condition
-
V,HI
V,H2
L input voltage
V,L
L output voltage
VOL
L output current
Note 1
Note 2
-
Min.
Typ.
3.6
VDD-0.5
-
-
-
0.8
V
-
0.4
V
10L
Vo = 0.4 V
1.6
H input current
I'HI
IIH2
VI = 5 V Note 3
V, = 5 V Note 4
10
-
L input current
I,L
V, =OV
-
Input capacity
C,
f
= 1 MHz
-
5
= 32.768 kHz
VDD = 5VIVDD = 3V
-
100/15
Note: 1.
2.
3.
4.
262
'DD
CS2 , WRITE, READ, ADDRESS WRITE, STOP, TEST, Do - D3
CSI
CSI, CS2 , WRITE, READ, ADDRESS WRITE, STOP, TEST
Do - D3
Unit
V
-
Current consumption
-
.-
10 = 3.6 mA
f
Max.
~
-
-
mA
-
50
1
I1A
-
-1
I1A
-
pF
500/30
I1A
25
------------~---.
PERIPHERAl;.S·MSM58321RS.
SWITCHING CHARACTERISTICS
(1) WRITE mode
(V DO = 5 V ±5%, Ta = 2S0C)
Min.
Typ.
Max.
Unit
-
0
-
0
-
tAS
-
0
Address write pulse width
tAW
-
0.5
-
-
IJ.s
-
-
/Js
Address hold time
tAH
-
0.1
-
-
/Js
Data setup time
tDS
-
0
-
-
/Js
Write pulse width
tww
-
2
-
-
/Js
Data hold time
tDH
-
0
-
-
/Js
Parameter
Symbol
CS setup time
tcs
CS Hold time
tCH
Address setup time
CS1
CS2
DO - D3
(ADDRESS/DATA)
H
Condition
/Js
/Js
--
--tcs
tAS
tAW
tAH tDS
tWW
tDH
--
tCH
I--
r--t-
~
X
I----
~
High Impe dance
ADDRESS WRITE
r-WRITE
IC internal
ADDRESS
X
IX
X
IC internal DATA
f--
-
ADDRESS
I-DATA
-
Write Cycle
Note: ADDRESS WRITE and WRITE inputs are activated by the level, not by the edge.
263
• PERIPHERALS· MSM58321RS . - - - - - - - - - - - - - - - (2) READ mode
(VDD = 5 V ±5%, Ta = 2S0C)
Min.
Typ.
Max.
Unit
CS setup time
Symbol
tcs
-
0
-
-
Jls
CS Hold time
tCH
-
0
-
-
Jls
Address setup time
tAS
-
0
-
-
Jls
Address write pulse width
tAW
-
0.5
-
-
Jls
Address hold time
tAH
-
0.1
-
-
Read access time
tRA
-
-
-
Read delay time
too
-
-
-
1
Jls
Read inhibit time
tRI
-
0
-
-
Jls
Parameter
I
m
I
Note 1.
tRA
= 1 Jls + CR
H
In (
Condition
VOD
.)
VDD - VIH min
--
CSl
CS2
tCS
DO - D3
(ADDRESS/DATA)
ADDRESS WRITE
READ
ADDRESS
DATA
Read Cycle
Note: ADDRESS WRITE and READ inputs are activated by the level, not by the edge.
264
see Note 1
Jls
Jls
- - - - - - - - - - - - - - - - . PERIPHERALS· MSM58321 RS •
(3) WRITE & READ mode
Min.
Typ.
Max.
CS setup time
tcs
-
0
-
-
J,J.s
CS hold time
tCH
-
0
-
-
J,J.s
Parameter
Symbol
Condition
Unit
Address setup time
tAS
-
0
-
-
J,J.s
Address write pulse width
tAW
-
0.5
-
-
J..Ls·
Address hold time
tAH
-
0.1
-
-
J,J.s
Data setup time
tDS
-
0
-
-
J,J.s
Write pulse width
tww
-
2
-
-
J,J.s
Data hold time
tDH
-
0
-
-
J,J.s
Read access time
tRA
-
-
-
Read delay time
tDD
-
-
-
1
J,J.s
Read inhibit time
tRI
-
0
-
-
J,J.s
Note 1.
tRA = 1 J,J.s + CR In (
see Note 1
J,J.s
VDD
.)
VDD-VIH mm
DATA INVALID
DATA VALID
/
H
--
tRI
I
CS1
CS2
DO - D3
(ADDR ESS/DATA)
-
tCS
tAS
tAW
tAH
tDS
tWW
tD~
t~AJ
.m-
~
/
(
I
I
II- ___
r---I-
/rD
-
ADDRESS WRITE
=--,
CH
~~
I
H igh Impedance
t--WRITE
READ
K
IC internal
ADDRESS
lX
IC internal DATA
-
ADDRESS
--
DATA
-
DATA READ
WRITE
Read & Write Cycle
265
.----~-----------
• PERIPHERALS- MSM58321RS
PIN DESCRIPTION
Name
Pin No.
Description
Chip select pins. These pins enable the interface with the external circuit when
both of these pins are set at H level simultanuously.
WRITE
13
If one of these pins is set at L level, STOP, TEST, WRITE, READ, ADDRESS
WRITE pins and Do ~ D3 pins are inactivated.
Since the threshold voltage VT for the CS 1 pin is higher than that for other pins,
it should be connected to the detector of power circuit and peripherals and CS 2
is to be connected to the microcontroller.
2
WRITE pin is used to write data; it is activated when it is at the H level. Data bus
data inside the IC is loaded to the object digit while this WRITE pin is at the H
level, not at the WRITE input edge. Refer to Figure 2 below.
[81 digit]
WRITE
[E
@------- ~
--~;-----~--------------~r------------
~~
02 ~r-----------------------r---------03
-==}
OATABU8
81
C81 = CS2
="H"
r-; _ n '-----
L ---------f-----------'
.......
DO
H -----+--------------4-----------~_+_+--------81
WRITE
F/F 00.0
-
I-
Figure 2
266
- - - - - - - - - - - - - - - - - . PERIPHERALS· MSM58321RS •
Name
Pin No.
READ
3
Descrip'
READ pin is used to read data; it is activated when it is at the H level. Address
contents are latched with ADDRESS LATCH inside the IC at the DO - D3 and
ADDRESS WRITE pins to select the object digit, then an H-Ievel signal is input
to the READ pin to read data.
If a count operation is continued by setting the STOP input to the L level, read
operation must be performed, in principle, while the BUSV output is at the H
level. While the -eusv output is at the L level, count operations are performed
by digit counters and read data is not guaranteed, therefore, read operations are
inhibited in this period. Figure 3 shows a time chart of the BUSV output, 1 Hz
·signal inside the IC, and READ input.
A read operation is stopped temporarily within a period of 244 J-Ls from the SUSY
output trailing edge and it is restarted when the BUSV output goes to the H level
again.
: - - - - - 427115
-
-
1 Hz (inside Ie)
f-----
____~----~r-r~--___
I
The counter inside the
Ie
starts counting at the
1 Hz signal leading edge.
Read-enabled period
244115
Read-enabled
period
--~.----.~----~---Read-inhibited period
Read operation is enabled in this period:
however, it is used for program switching.
BUSY
1 Hz linside Ie)
READ input
~
~
~~-_-_-_-_-_-_-_-_-_-_-_-_-'-tl+-----
-..L.Lf-f---lIL.....L.1. LI.. .LI_ _ _ _ _ _ _ _ _ _
I-~_ _ _ _ _ _ _ _ _
1 sec
•
Figure 3
If the counter operation is stopped by setting the STOP input to the H level, read
operations are enabled regardless of the SUS'Voutput.
A read operation is enabled by microcomputer software regardless of the BOW
output during the counter operation by setting the STOP input to the L level.
In this method, read operations are performed two or more times continuously
and data that matches twice is used as guaranteed data.
267
• PERIPHERALS· MSM58321 RS • - - - - - - - - - - - - - - - -
Name
Pin No.
Description
Data input/output pins. (Bidirectional bUs). The output is a open-drain type and
4.7 kn or higher pull-up registers are required utilize these pins as output pins.
GND
ADDRESS
WRITE
8
9
Ground pin.
ADDRESS WRITE pin is used to load address information from the DO - D3
I/O bus pins to the ADDRESS LATCH inside the IC; it is activated when it is
at the H level. This input is activated by the level, not by the edge. Figure 4 shows
the relationships between the DO address input, ADDRESS WRITE input, and
ADDRESS LATCH input/output.
l
DO input
ADDRESS WRITE
J
DJOL
Ie inside
See Figure 1 "Circuit
Configuration" for
the signal names.
{
AO
- - - - , L_ _ _.......J1
LATCH output
Figure 4
10
BUSV pin outputs the IC operation state. It is N-channel MOSFET open-drain
output. An external pull-Up resistor of 4.7 knor more must be connected (see
Figure 5) to use the SlrnV output. The signals are output in negative logics. If
the oscillator oscillates at 32.768 kHz, the frequency is always 1 Hz regardless of
the CS1 and CS2 unless the D output of the ADDRESS DECODER inside the IC
is H (CODE = H· L· H· H) and CS1 = CS2 = WRITE = H.
Figure 6 shows the SUW output time chart.
tperlpheral circuit power)
The counter inside the
BUSY
Ie
starts counting at the
1 Hz signal leading edge.
\
1 Hz Onside IC)
244JlS
r----
I
1122JlS b1Jl
427JlS
-
I-SRead/write-inhibited period
1 Hz
Onside IC)
1 sec
Figure 6
268
- - - - - - - - - - - - - - - - . PERIPHERALS· MSM58321RS •
Name
Description
Pin No.
STOP
11
The STOP pin is used to input on/off control for a 1 Hz signal. When this pin goes
to the H level. 1 Hz signals are inhbited and counting for all digits succeeding the
Sl digit is stopped. When this pin goes to the L level. normal operations are
performed; the digits are counted up. This STOP input controls stopping digit
counting. Writing of external data in digits can be assured by setting the STOP
input to the H level to stop counting. then writing sequentially from the loworder digits.
TEST
12
The TEST pin is used to test this IC; it is normally open or connected to GND. It
is recommended to connect it to GND to safeguard against malfunctions from
noise.
The TEST pulse can be input to the following nine digits:
51.510. MilO. Hl. 01 (W). MOl. Yl and Yl0
When a TEST pulse is input to the 01 digit. the W digit is also counted up
simultaneously.
Input a TEST pulse as follows:
Set the address to either digit explained above. then input a pulse to the TEST pin
while CSl = CS2 = STOP = H and WRITE = L. The specified and succeeding digits
are coU'tlted up. (See Figure 7)
0-9
0-9
C1
I ""l.J
~ 51
T.rD R
TEST
_ Rp
CoS
Cl0
Hp-
510
Cl0~-
JII~ll
~
Q
I
TEST-P
Cl0
I
I
510
51
0-6
0-9
HPl-Ol
I
co
Cl
010
I
Rp • 200 kQ TYP
Figure 7
A digit is counted up at the leading edge (changing point from L to H) of a TEST
pin input pulse. The pulse condition for TEST pin input at VDD = 5 V ±5% is
described in Figure 8 below.
tH
= lOllS MIN
tL =10115 MIN
FigureS
269
• PERIPHERALS· MSM58321 RS • - - - - - - - - - - - - - - - -
Name
XT
XT
Pin No.
14
15
Description
Oscillator pin. A 32.768K crystal oscillator, capacitors and trima condensor for
frequency adjustment are to be connected as shown in Figure 8 below.
I
lC..T
RFB
=
RS
= 200 Kn typ
10Mntyp
GND or VDD
C2
(
....
I· _ _ _R_S_M_S_M_5_83_21 RS
X·TAL 32.768 kHz, The crystal impedance is 30 knor less.
Figure 8
If an external clock is to be used for MSM58321 RS's oscillation source, the
external clock is to be input to XT, while XT should be left open. Refer to the
Figure 9 below.
CMOS
s
XT
.'"
.....,
or +5V
/1
~/("
~
I
~
...
MSM58321RS
'------
TTL
Figure 9
VDD
270
16
Power supply pin. Refer to the application circuit.
- - - - - - - - - - - - - - - - . PERIPHERALS· MSM58321RS •
REFERENCE SIGNAL OUTPUT
Reference signals are output from the DO - D3 pins under the following conditions:
Conditions
Output
pin
Reference signal
frequency
Pulse width
Output logic
WRITE = L
Do
1024 Hz
488.3 J.l.s
Positive logic
READ = H
Dl
1 Hz
122.1 J.l.s
Negative logic
CS1 = CS2 = H
D2
1/60 Hz
122.1 J.l.s
Negative logic
ADDRESS = E or F
D3
1/3600 Hz
122.1 J.l..s
Negative logic
-
488.3J.l.S
488.3J.l.S
1024 Hz
1 Hz
~
0....--
-
1/60 Hz
1/3600 Hz
~
r---
1 Hz
(inside Ie)
BUSY
244J.l.S
122J.l.S ~1~ S
10- 3
122.1J.l.S = 32,768 X 4
10- 3
488.3J.l.S = 32,768 X 16
Figure 10
271
• PERIPHERALS· MSM58321 RS
.~---------------
APPLICATION NOTES
•
Do '" 03
• READ mode
If CS1 = CS2 = H, WRITE = L, and READ = H, the ANALOG switch is in the OFF state. If data bus DO is
at the H level, the NOR gate output goes to L, N-channel MOSFET goes to OFF, and the DO pin goes to the H level
because it is pulled up to +5 V with the pull-up resistor; if it is at the L level, the NOR gate output goes to the H level,
N-channel MOSFET goes to ON, therefore, the DO pin goes to the L level. In the READ mode, four NAND gates
connected to the DO-D3 pins are meaningless.
I
I~
I
• WRITE mode
If CS1 = CS2 = H, READ = L, and WR ITE = H, the output of four NOR gates connected to the data buses
goes to the L level and N-channel MOSFET goes to OFF. The ANALOG switch goes to ON and data information
from the DO-D3 pins appear at the data buses via the NAND gate, INV gate, and ANALOG switch.
If the WRITE mode, the N-channel MOSFETs connected to the DO-D3 pins are meaningless because they
are set OFF.
• ADDRESS WRITE mode
If CS1 = CS2 = H, WRITE = READ = L, and ADDRESS WRITE = H, the N-channel MOSFETs connected to
the DO-D3 pins and the ANALOG switch connected to the data buses are set OFF. Address information input
to the DO-D3 pins is loaded to the ADDRESS LATCH via the NAND gate with an ADDRESS WRITE signal. The
output of ADDRESS latch is connected to the input of ADDRESS DECODER; the ADDRESS DECODER output
is decided by the ADDRESS LATCH output.
•
WRITE and STOP
Note that the timing relationships between the STOP and WRITE inputs vary by the related digit when counting
is stopped by the STOP input to write data. The time (tSH) between the STOP input leading edge and WRITE
input trailing edge for each digit is limited to the minimum value. (See Figure 11)
r---
The counter inside
the IC starts counting
at the 1 Hz signal
leading edge.
~
1 Hz (inside IC)
244J1S
Write-enabled
period
---
427 J1S
122J1S
61~
S
Wri te-enabled
period
--Write-inhibited period
Figure 11
tSHS1 = 1 J1s,tSHS10=2J1s, tSHMI1 =3J1s, tSHM10=4J1s, tSHH1 =5J1s
tSHH10 = 6 J1s, tSHD1 = 7 J1s, tSHW'= 7 J1s, tSHD10 = 8 J1s, tSHM01 = 9 J1s
tSHM010 = 10 J1s, tSHY1 = 11 J1s, tSHY10 = 12 J1s.
272
- - - - - - - - - - - - - - - - - . PERIPHERALS-MSM58321RS·
If a count operation is continued by setting the STOP input to the level, write operation must be performed,
in principle, while the BOW output is at the H level. While the 'B1JSV output is at the L level, count operations
are performed by the digit counters and write operation is inhibited, but there is a marginal period of 244 fJ.s from
the 80S"? output trailing edge. If the BlJSV output goes to the L level during a write operation, the write operation
is stopped temporarily within 244 fJ.s and it is restarted when the BUSV output goes to the H level again. Figure 12
shows a time chart of ~ output, 1 Hz signal inside the IC, and WRITE.input.
Write operation is enabled in this period;
however, it is used for program switching.
1 Hz (inside Ie)
J
III I
11
WRITE input
1 sec
Figure 12
If the WR ITE and READ inputs go to the H level sir:lUltaneously, the WR ITE input has priority.
•
Frequency divider and BUSY circuit reset
If AO-A3 = H·L·H·H is input to ADDRESS DECODER, the DECODER output (D) goes to the H level. If
CS1 = CS2 = H and WRITE = H in this state, the 5 poststages in the 15-stage frequency divider and the BUSY' circuit
are reset.
In this period, the BOSV output remains at the H level and the 1 Hz signal inside the IC remains at the L level,
and counting is stopped. If this reset is inactivated while the oscillator operates, the BUSV output goes to the
L level after 1000.1221 ±31.25 ms and the 1 Hz signal inside the IC goes to the H level after 1000.3663 ±31.25 ms.
These times are not the same because the first ten stages in the 15-stage frequency divider are not reset. (See
Figure 13)
15·stage
frequency
divider
32,768 kHz
Stages
11-15
1 Hz
"1-1
From ADDRESS DECODER
AO Al
H L
A2
H
A3
linside IC)
1 Hz
(inside IC)
RESET (inside Ie)
tl = 1000.1221 ± 31.25 ms
t2 = 1000.3663 ± 31.25 ms
t3 "1000 ± 31.25 ms
Figure 13
273
• PERIPHERALS· MSM58321RS . - - - - - - - - - - - - - - - •
Selection of leap year
This IC is designed to select leap year automatically.
Four types of leap years can be selected by writing a select signal in the 02 and 03 bits of the 010 digit (COOE
= LoL·LoHI. (See Table 1 for the functionsJ
'
Gregorian calendar, Japanese Showa, or other calendars can be set arbitrarily in the Y1 and Y2 digits of this IC.
There is a leap year every four years and the year number varies according to whether the Gregorian calendar or
Showa is used. There are four combinations of year numbers and leap years. (See the Table below)'
No.1:
No.2:
No.3:
No.4:
Gregorian calendar year. The remainder obtained by dividing the year number by 4 is
Showa year. The remainder obtained by dividing the year number by 4 is 3.
The remainder obtained by dividing the year number by 4 is 2.
The remainder obtained by dividing the year number by 4 is 1.
010 digit
02
03
Remainder obtained by
dividing the year number by 4
o.
No.1
Calendar
1
Gregorian
L
L
0
1980,1984,1988,1992,
1996,2000,2004
2
Showa
H
L
3
(83) (87) (91) (95) (99)
55, 59, 63, 67, 71,
75, 79
3
L
H
2
82, 86,
102, 106
90,
94,
98,
4
H
H
1
81, 85,
101,105
89,
93,
97,
274
Leap years (examples)
- - - - - - - - - - - - - - . PERIPHERALS· MSM58321RS •
APPLICATION CIRCUIT -
POWER SUPPLY CIRCUIT
Open or ground unused pins (pins other than the XT, XT, 00-03, and
'BUSY pins).
VF = 0.69V
1S1588
Ripple
+5.7V
Operating state
20mV p.p
Backup
OmV
a) .
or
rJ
C372
GNO
MSM58321RS
::'
1.2x3 = 3.6V
Ni-Cd battery
VF= 0.69
VCE (Sat) = 0.1 V
Ripple
A495
Operating state
51K
+
20mV Pop
4.7/J.
VOO
b) .
10K
Backup
OmV
'GNO
":"
-=-
=-
MSM58321RS
1.2x3 = 3.6V
Ni-Cd battery
RL
+5V
100n
c) .
4.7/J.
+
-=
MAM58321RS
GNO
-=
1.5x2 = 3V
Dry cell
d) .
VOO
(Recommended circuit)
+V
02
(Power voltage
approximately
1.5V higher than
5V)
100n
circuit power)
4.7/J.
VOO
MSM58321RS
3.6V
Ni-Cd
battery
Note: Use the same diodes for 01 and 02 to reduce the level difference between +5V and VOO of the MSM58321 RS.
275.
OKI
semiconductor
MSM6242RS/GS
DIRECT BUS CONNECTED CMOS REAL TIME CLOCK/CALENDAR
GENERAL DESCRIPTION
The MSM6242 is a silicon gate CMOS Real Time Clock/Calendar for use in direct bus-connection Microprocessor/Microcomputer applications. An on-chip 32.768KHz crystal oscillator time base is divided to provide
addressable 4-bit I/O data for SECONDS, MINUTES, HOURS, DAY OF WEEK, DATE, MONTH and YEAR. Data
access is controlled by 4-bit address, chip selects (CSO, CS1), iiifRlTE", FfEAlJ, and ALE. Control Registers D, E
and F provide for 30 SECOND error adjustment, INTERRUPT REQUEST (IRQ FLAG) and BUSY status bits, clock
STOP, HOLD, and RESET FLAG bits, 4 selectable INTERRUPTS rates are available at the STD.P (STANDARD
PULSE) output utilizing Control Register inputs TO, T1 and the ITRPT/STND (INTERRUPT/STANDARD).
Masking of the interrupt output (STD.P) can be accomplished via the MASK bit. The MSM6242 can operate in
a 12/24 hour format and Leap Year timing is automatic.
The MSM6242 normally operates from a 5V ± 10% supply at -30 to 85°C. Battery backup operation down
to 2.0V allows continuation of time keeping when main power is off. The MSM6242 is offered in a 18-pin
plastic DIP package.
FEATURES
DIRECT MICROPROCESSOR/MICROCONTROLLER BUS CONNE
TIME
23:59:59
MONTH
DATE
YEAR
12
31
80
• 4-bit data bus
• 4-bit address bus
• READ, WRITE, ALE and CHIP SELECT
INPUTS
• Status registers - I RQ and BUSY
• Selectable interrupt outputs - 1/64 second,
1 second, 1 minute, 1 hour
• Interrupt masking
• 32.768KHz crystal controlled operation
7
•
•
•
•
•
•
12/24 hour format
Auto leap year
±30 second error correction
Single 5V supply
Battery backup down to VDD = 2.0V
Low power dissipation:
20 pW max at VDD = 2V
150 J..LW max at VDD = 5V
• 18-pin plastic DIP package
FUNCTIONAL BLOCK DIAGRAM
D,
D,
D,
D.
A,
A,
A,
A.
ALE
CS,
276
DAY OF WEEK
~ $1 ..... W.... y 10 are time counter register
,. Co ...... CF are control register
- - - - - - - - - - - - - - - . PERIPHERALS· MSM6242RS/GS •
PIN CONFIGURATION
VDD
"CS;-
XT
AO-A3:
DO-D3:
Address input
Data input/output
CHIP SELECTS 0, 1
READ enable
WRITE enable
Address latch enable
Standard pulse output
XTAL oscillator input/output
+5V supply
ground
C"SU,~
Frn":
WR":
A,
es,
D,
A,
A,
A,
A,
A,
D,
A .•
D,
Rll
D,
WR
GND
18 pin Plastic DIP Package
ALE:
STD.P:
XT, XI:
VDD:.
VSS:
24 pin Plastic Flat Package
REGISTER TABLE
Address Input
Address
Input
A3
A2
Data
Register
Name
Al
Ao
D3
D2
Count
value
Dl
Description
Do
0
0
0
0
0
Sl
S8
S4
S2
Sl
l'J- 9
1-second digit register
1
0
0
0
1
SIO
*
S40
S20
SIO
0
~
1O-second digit register
~
5
2
0
0
1
0
Mil
mia
mi 4
mi 2
.mil
0
3
0
0
1
1
Milo
*
mi. o
mi 20
mho
0
4
0
1
0
0
HI
hs
h4
h2
hi
0
HIO
*
PM/
AM
h lo
0 -2
or O' j
5
0
1
6
0
7
0
0
1
h 20
1
1
0
01
ds
d4
d2
dl
0
1
1
1
DIO
*
*
d 20
d lo
0
~
~
~
~
9
l-minute digit register
5
10-minute digit register
9
l-hour digit register
PM/ AM, 10-hour' digit
register
9
l-day digit register
3
10-day digit register
8
1
0
0
0
Mal
mos
m04
m02
mOl
0
9
1
0
0
1
Malo
*
*
*
Malo
0
A
1
0
1
0
Yl
Ys
Y4
Y2
Yl
0
~
9
1-year digit register
B
1
0
1·
1
Y IO
Yso
Y40
Y20
YIO
0
~
9
1O·year digit register
C
1
1
0
0
W
*
W4
W2
WI
0
~
6
Week register
IRQ
FLAG
D
1
1
0
1
CD
30
sec.
ADJ
E
1
1
1
0
CE
tl
to
F
1
1
1
1
CF
TEST
24/12
~
~
9
1-month digit register
1
10-month digit register
HOLD
-
Control Register D
ITRPT
MASK
/STND
-
Control Register E
STOP
-
Control Register F
BUSY
REST
REST = RESET
ITRPT/STND = INTERRUPT/STANDARD
Note 1) Note 2) Note 3) -
Bit * does not exist (unrecognized during a write and held at "0" during a read).
Be sure to mask the AM/PM bit when processing 10's of hour's data.
BUSY bit is read only. The IRO FLAG bit can only be set to a "0", Setting the IRO FLAG to a "1" is
done by hardware.
Figure 1. Register Table
277
~
• PERIPHERALS· MSM6242RS/GS •
-~-------------
OSCI LLATOR FREOUENCY DEVIATIONS
0
tJ
0
~
~
c..
~
-50
--........
c..
-1
--
-2
~
....
= 0, the data of the register is output to Do - 0 3 . If both RL> and WR" are
set at 0 simaltanuously, Rn is to be inhibited.
Chip Select Pins. These pins enable/disable ALE, Ff[) and"WR operation. CSo
and A LE work in combination with one another, while CS I work independent
with ALE. CS I must be connected to power failure detection as shown in Figure
18.
CS o
2
2
CS I
15
20
1
1
STD.P
Output pin of N-CH OPEN DRAIN type. The output data is controlled by the
0 1 data content of CE register. This pin has a priority to ~ and CS I .
Refer to Figure 9 and FUNCTIONAL DESCRIPTION OF REGISTERS.
XT
16
22
XI
17
23
32.768 kHz crystal is to be connected to these pins.
When an external clock of 32.768 kHz is to be used for MSM6242's oscillation
source, either CMOS output or pull-up TTL output is to be input from XT, while
XI should be left open.
VDO
18
24
Power supply pin. +2 - +6V power is t6 be applied to this pin.
GNO
9
12
Ground pin.
XT
,~
C,
x'tal..l
c:::J
=r
'''~'' .~
,~---
GND OR V DD ... -II
lI_
c' XT
~'m'D"T,"T
N-CH
C, ; C,'; 15-30pF
'The impedance of the crvstal should be less than 30kn
Figure 8. Oscillotor Circuit
Figure 9.
283
• PERIPHERALS· MSM6242RS/GS • - - - - - - - - - - - - - - FUNCTIONAL DESCRIPTION OF REGISTERS
•
a)
b)
c)
d)
e)
f)
.SI' SIO' Mil' Milo' HI' H lo ' 0 1 , 0 10 , MOl' MOI~' VI' V IO ' W
These are abbreviations for SECOND1, SECOND10, MINUTE1, MINUTE10, HOUR1, HOUR10, DAY1,
DAY10, MONTH1, MONTH10, YEAR1, YEAR10, and WEEK. These values are in BCD notation.
All registers are logica"y positive. For example, (S8, S4, S2, S1) = 1001 which means 9 seconds.
If data is written which is out of the clock register data limits, it can result in erroneous clock data being read
back.
PM/AM,h 2o ,h lO
In the mode setting of 24-hour mode, PM/AM bit is ignored, while in the setting of 12-hour mode h20 is to be
set. Otherwise it causes discrepancy. In reading out the PM/AM bit in the 24-hour mode, it is continuously read
out as O. In reading out h20 bit in the 12-hour mode, 0 is written into this bit first, then it is continuously read
out as 0 unless 1 is being written into this bit.
Registers Y1, Y10, and Leap Year. The MSM6242 is designed exclusively for the Christian Era and is capable
of. identifying a leap year automatically. The result of the setting of a non-existant day of the month is shown
in the following example: If the date February 29 or November 31, 1985, was written, it would be changed
automatically to March 1, or December 1, 1985 at the exact time at which a carry pulse occurs for the day's
digit.
The Register W data limits are 0-6 (Table 1 shows a possible data definition).
TABLE 1
W2
WI
0
0
0
Sunday
0
0
1
Monday
0
1
0
Tuesday
0
1
1
Wednesday
1
0
0
Thursday
1
0
1
Friday
1
1
0
Saturday
Using HOLD Bit
or Read data from
registers 5. -VII
Figure 10. Reading and Writing of Registers 5, -VII
284
Day of Week
W4
Not Using HOLD Bit
- - - - - - - - - - - - - - - . PERIPHERALS· MSM6242RS/GS •
• CO REGISTER (Control 0 Register)
a) HOLD (DO) -
Setting this bit to a "1" inhibits the 1 Hz clock to the S1 counter, at which time the Busy status
bit can be read, and when Busy = 0 register's SI - W can be read or written. During this
procedure if a carry occurs the S1 counter will be incremented by 1 second after HOLD = 0
(this condition is guaranteed as long as HOLD = 1 does not exceed 1 second in duration). If
CS1 = 0 then HOLD = 0 irrespective of any condition.
b) BUSY (01) -
Status bit which shows the interface condition with microcontroller/microprocessors. As for
the method of writing into and reading from SI - W (address if> - C)' refer to the flow chart
described in Figure 10.
c) IRQ FLAG (02) - This status bit corresponds to the output level of the STO.P output. When STO.P = 0, then
IRQ = 1; when STO.P =1, then IRQ = O. The IRQ FLAG indicates that an interrupt has occurred
to the microcomputer if IRQ = 1. When 00 of register CE (MASK) = 0, then the STO.P output
changes according to the timing set by 03 (tl) and 02 (to) of register E. When 01 of register E
(ITRPT/STNO) = 1 (interrupt mode), the STO.P output remains low until the IRQ FLAG is
written to a "0". When IRQ = 1 and timing for a new interrupt occurs, the new interrupt is
ignored. When ITRPT/STNO = 0 (Standard Pulse Output mode) the STO.P output remains low
until either "0" is written to the IRQ F LAG; otherwise, the IRQ F LAG automatically goes to
"0" after 7.8125 ms.
When writing the HOLO or 30 second adjust bits of register 0, it is necessary to write the IRQ
FLAG bit to a "1".
d) ±30 AOJ (03) - When 30-second adjustment is necessary, a "1" is written to bit 03 during which time the
internal clock registers should not be read from or written to 125J.Ls after bit 03 = 1 it will
automatically return to a "0", and at that time reading or writing of registers can occur.
(8)
(A)
Figure 11. Writing 30-Second Adj. bit (Two Ways A, B)
285
• PERIPHERALS· MSM6242RS/GS • - - - - - - - - - - - - - - • CE REGISTER (Control E Register)
a) MASK (DO) -
This bit controls the STO.P output. When MASK = 1, then STO.P = 1 (open); when MASK = 0,
then STO.P = output mode. The relationship between the MASK bit and STO.P output is shown
Figure 12.
b) INTRPT/STNO (01) - The INTRPT/STNO input is used to switch the STO.P output between its two modes
of operation. Interrupt and Standard timing waveforms. When INTRPT/STNO = 0 a fixed cycle
waveform with a .Iow-Ievel puise width of 7.8125 ms is present at the STO.P output. At this time
the MASK bit must = 0, while the period in either mode is determined by TO(02) and T1 (03) of
Register E.
c) TO (02), T1 (03) - These two bits determine the period of the STO.P output in both Interrupt and Fixed timing
waveform modes. The tables below show the timing associated with the TO, T1 inputs as well as
their relationship to INTRPT/STNO and STO.P.
MASK BIT
v
"0"
n.~
"1"
"n"
"1" OUTPUT DOES NOT OCCUR
n . f)1 AT LOW LEVEL BECAUSE
n"
MAS~~(~ITIS"l"
STD.Ptp=i
OUTPUT
••••••• LOW LEVEL
t'
:
:
......
"INTERRUPT" TIMING
OPEN
LOW LEVEL
OUTPUT TIMING
'-----~---
INTRT/STND BIT; "1"
AUTOMATIC RETURN
INTRT/STND BIT; "0"
Figure 12.
t1
to
Period
0
0
1
1
0
1
0
1
1/64 second
1 second
1 minute
1 hour
Outy CYCLE of "0" level when
ITRPT/STNO bit is "0".
1/2
1/128
1/7680
1/560800
TABLE 2
The timing of the STO.P output designated by T1 and TO occurs the moment that a carry occurs to a clock digit.
(EXAMPLE) WHEN t, = 1, to = 1 and MASK = O.
I;PM12:00
II' PMl :00
I
I
WHEN ITRPT/STNO/"'"
------~L---OPEN
BITis"l"
L..,,:!__
-----LOWLEVEL
STO.P OUTPUTI
WHEN ITRPT/STNn....
i r- - - OPEN
BIT IS "0"
U - - - - _ LOW LEVEL
-'--U
286
I
- - - - - - - - - - - - - - - . PERIPHERALS· MSM6242RS/GS •
d) The low-level pulse width of the fixed cycle waveform (ITRPT/STND = 0) is 7.8125 ms independent of TO/T1
inputs.
e) The fixed cycle waveform mode can be used for adjustment of the oscillator frequency time base. (See Figure 141.
f)
During ±30 second adjustment a carry can occur that will cause the STD.P output to go low when TO/T1 = 1,0
or 1,1. However, when T1/TO = 0,0 and ITRPT/STND = 0, carry does not occur and the STD.P output resumes
normal operation.
g) The STD.P output is held (frozen) at the point at which STOP
= 1 while
ITRPT/STND
= o.
h) No STD.P output change occurs as a result of writing data to registers S1 - H1 .
• CF REGISTER (Control F Register)
a) REST (DO) "R ESET"
This bit is used to clear the clock's internal divider/counter of less than a second. When
REST = 1, the counter is Reset for the duration of R EST. I n order to release this counter from
Reset, a "0" must be written to the R EST bit. If C"SO" = 0 then REST = 0 automatically.
b) STOP (D1) -
The STOP FLAG Only inhibits carries into the 8192Hz divider stage. There may be up to 122J1s
delay before timing starts or stops after changing this flag; 1 = STOP/O = RUN.
"1"
"1"
STOP BIT
~
"0"
"1"
n
~---'
"0"
n
--~
"0"
'----
TIMING OF
"CARRY"
T08192Hz----~----~----~~----~----~~----~--
"CARRY" EXECUTEDt
"CARRY" NOT EXECUTED
c) 24/12 (D2) "24 HOURI
12 HOUR"
d) TEST (d3) -
t
I
Figure 13
This bit is for selection of 24/12 hour time modes. If D2 = 1-24 hour mode is selected and the
PM/AM bit is invalid. If D2 = 0-12 hour mode is selected and the PM/AM bit is valid.
Setting of the 24/12 hour bit is .as follows:
1) REST bit = 1
2) 24/12 hour bit = 0 or 1
3) REST bit = 0
* R EST bit must = 1 to write to the 24/12 hour bit.
When the TEST flag is a "1 ", the input to the SECONDS counter comes from the counter/divider
stage instead of the 15th divider stage. This makes the SECONDS counter count at 5.4163KHz
instead of 1 Hz. When TEST = 1 (Test Mode) the STOP & REST (Reset) flags do not inhibit
internal counting. When Hold = 1 during Test (Test = 1) internal counting is inhibited; however,
when the HOLD FLAG goes inactive (Hold = 0) counter updating is not guaranteed.
287
• PERIPHERALS· MSM6242RS/GS • - - - - - - - - - - - - - - TYPICAL APPLICATION INTERFACE WITH MSM6242 AND
MICROCONTROLLERS
MSM6242
8085
8085
A/D
AD3 1 - - - - - - -.......-1 D3
MSM6242
1------......... D3
AD2
D2
D2
AD!
DI
DI
ADo
Do
A3
A2
A3
Al
Al
Do
A2
Ao
P-----1CSo
Ao
10----4 CS o
ALE 1 - - - - - - - - - 1 ALE
ALE
RD
RD
RD
t--------~RD
WR
WR
WR
t-------~
WR
I/O MAPPED
MEMORY MAPPED
Figure 15.
MSM6242
MCS48
MSM6242
Z80
I
D3
D3
D2
D2
DI
DI
Do
Do
A3
A2
A3
D3
BUS 2
BUS I
DI
BUS o
Do
D2
~
'---
A2
Al
Al
Ao
Ao
DECODER
CS o
A4 -A ls
10RO
MREO
A3
A2
Al
D~ER
BUS 4-7
ALE
ALE
-
---
Ao
CS o
ALE
RD
RD
RD
RD
WR
WR
WR
WR
G2
Figure 16.
288
)
BUS 3
,
,
)
Figure 17.
- - - - - - - - - - - - - - - . PERIPHERALS· MSM6242RS/GS •
TYPICAL APPLICATIONS -
INTERFACE WITH MSM80C49
10PI~
~I*"""I
~ltUMV1
BATTERY
__-----~--*_~.~.I--__
.
*
>- 18K
>
>
26
2~~f
t
T
il
X,
I
I
I
T
17I
ALE~1_1_ _ _ _ _ _ _3~ALE
Cl
22pf
18
(VFWD =
1.8K
I
A
VI
. A
vvv
:~ ~
1.8K
~
....... 10pf
?---<
I
I :.
A
TR2
1.8K
n
1.8K
1.8K>
>
3 ..
20
--
.>
I
2
~
..J?O
220
+-1
-::-
RS232
INTERFACE
I
TRl = 2N2907
TR2 = 2N2907
TR3 = 2N2222
I *=
lN4148
I
I
I
I
I
I
I
I
1
~
I
I
L - - - - ----~
5.2V
Figure 18.
289
• PERIPHERALS· MSM6242RS/GS • - - - - - - - - - - - - - - APPLICATION NOTE
1. Power Supply
Voo = 5V
-- - STO.P
Output =
Open Output
TEST Bit
REST Bit
24/12 Bit
STOP Bit
+-0
+-1
+-1*
+-1
1*=2*
(1 or 0)
Start Operation
2. Adjustment of Frequency
Co ~ CF are to be set at as described in the
figure and the capacitor is to be adjusted
to meet the settle frequency of to and t1 .
If the right oscillation can not be get ...
1. Check the waveform of XT
2. Check CD ~ CF content
3. Check the noise.
Voo
290
- - - - - - - - - - - - - - - . PERIPHERALS· MSM6242RS/GS •
3. CH, (Chip Select)
VI~ and
V;L of CHI has 3 functions.
a) To accomplish the interface with microcontroller/microprocessor.
b) To inhibit ~he control bus, data bus and address bus in the stand-by mode.
c) To protect MSM6242 device when the mode is moved to and from standby mode.
To realize above functions:
a) More than 4/5 VOO should be applied to MSM6242 for the interface with microcontroller/microprocessor
in 5V operation.
b) In moving to the standby mode, 115 VOO should be applied so that all data bus should be disabled. In
the standby mode, approx. OV should be applied.
c) To and from the standby mode, please obey following Timing chart.
To Standby Mode
From Standby Mode
--
- -- ---.,-----
VOO
CS I
CS;; : H
or
WI1:
H
4. Set STO.P at arlarm mode
Set alarm at 9:00
MASK BIT +- 0
ITRPT/STNO BIT +- 1
tl , to +- 1
Start interruption
CPU Activation
Repeat
Read HI 0 and
HI Content
CPU STAND BY
291
• PERIPHERALS· MSM6242RS/GS . - - - - - - - - - - - - - - TYPICAL APPLICATION -
VCE (SAT.)
+5V
POWER SUPPLY CIRCUIT
RIPPLE
OPERATING' 20 mV P-P
BATTERY BACKUP: OmV
~0.1V
,.--..--~----,
)
+5 V _---4I__---,R L
lOOn -
MSM
+
-i
~1.2X3~3.6V
Ni-Cd
6242
VSS
Figure 19.
Figure 20.
220n
r - -.......--.-KI~--N\r-- ..6.5V
.
I
+
47/l1
+
-
=
-l
DJ
RL
6V
Ni-Cd
Figure21.
292
+5V
1.2X-3-=...3 ......,r - -
A ll spec if lcal lo ns and details publis hed are sub,ec l to change Wi tho ut notice
OKI Electric Industry Co ., ltd.
10 -3 Shlbaura 4 -chome . Mmato-ku .
Tokyo 108, Japan
Tel
Tokyo 4 5 4 -2111
Telex J22627
Fax
Tokyo 452 -5912 (Gill)
ElectroniCs devices Group
Overseas Marketing Dept
E3S00562
OKI Semiconductor Group
OKI Elec tri c EUrope GmbH
OKI Elec tronics (Hong Kong) ltd .
650 N Mary Avenue
Sunnyvale . Calif 9 4 086 . USA
Tel
408-720 - 1900
Telex 9103380508 OKI SUV L
Fax
408-72 0 -1918 (GIIO
Nlederkasseler Lohweg 8
D 4000 Dusseldorf 1 1
West Germany
Tel
0 211 - 5955 0
Telex 8584312
Fax
0 211 -591669 (Gil l)
16th Floor Fairmo nt House.
8 Cotton Tree Drive Hong Kong
Tel
5 - 263111 - 3
Tele .. 62 4 59 OKIHK HX
Fa..
5 - 200 10 2 (Gill )
86-02-1A/ 151 PRINTED IN JAPAN
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